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authorLinus Torvalds <torvalds@linux-foundation.org>2008-07-20 20:43:29 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-07-20 20:43:29 -0400
commitdb6d8c7a4027b48d797b369a53f8470aaeed7063 (patch)
treee140c104a89abc2154e1f41a7db8ebecbb6fa0b4 /drivers/net
parent3a533374283aea50eab3976d8a6d30532175f009 (diff)
parentfb65a7c091529bfffb1262515252c0d0f6241c5c (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (1232 commits) iucv: Fix bad merging. net_sched: Add size table for qdiscs net_sched: Add accessor function for packet length for qdiscs net_sched: Add qdisc_enqueue wrapper highmem: Export totalhigh_pages. ipv6 mcast: Omit redundant address family checks in ip6_mc_source(). net: Use standard structures for generic socket address structures. ipv6 netns: Make several "global" sysctl variables namespace aware. netns: Use net_eq() to compare net-namespaces for optimization. ipv6: remove unused macros from net/ipv6.h ipv6: remove unused parameter from ip6_ra_control tcp: fix kernel panic with listening_get_next tcp: Remove redundant checks when setting eff_sacks tcp: options clean up tcp: Fix MD5 signatures for non-linear skbs sctp: Update sctp global memory limit allocations. sctp: remove unnecessary byteshifting, calculate directly in big-endian sctp: Allow only 1 listening socket with SO_REUSEADDR sctp: Do not leak memory on multiple listen() calls sctp: Support ipv6only AF_INET6 sockets. ...
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/3c503.c14
-rw-r--r--drivers/net/3c515.c4
-rw-r--r--drivers/net/3c523.c37
-rw-r--r--drivers/net/3c527.c45
-rw-r--r--drivers/net/8139cp.c44
-rw-r--r--drivers/net/8139too.c66
-rw-r--r--drivers/net/8390.h19
-rw-r--r--drivers/net/8390p.c66
-rw-r--r--drivers/net/Kconfig191
-rw-r--r--drivers/net/Makefile15
-rw-r--r--drivers/net/a2065.c4
-rw-r--r--drivers/net/acenic.c21
-rw-r--r--drivers/net/acenic.h1
-rw-r--r--drivers/net/amd8111e.c137
-rw-r--r--drivers/net/arm/ixp4xx_eth.c3
-rw-r--r--drivers/net/atarilance.c2
-rw-r--r--drivers/net/atlx/atl1.c3
-rw-r--r--drivers/net/au1000_eth.c2
-rw-r--r--drivers/net/b44.c140
-rw-r--r--drivers/net/bfin_mac.c2
-rw-r--r--drivers/net/bnx2.c1339
-rw-r--r--drivers/net/bnx2.h115
-rw-r--r--drivers/net/bnx2_fw.h80
-rw-r--r--drivers/net/bnx2_fw2.h8858
-rw-r--r--drivers/net/bnx2x.c9988
-rw-r--r--drivers/net/bnx2x.h1585
-rw-r--r--drivers/net/bnx2x_fw_defs.h483
-rw-r--r--drivers/net/bnx2x_hsi.h1101
-rw-r--r--drivers/net/bnx2x_init.h352
-rw-r--r--drivers/net/bnx2x_init_values.h19186
-rw-r--r--drivers/net/bnx2x_link.c4527
-rw-r--r--drivers/net/bnx2x_link.h168
-rw-r--r--drivers/net/bnx2x_main.c10294
-rw-r--r--drivers/net/bnx2x_reg.h1969
-rw-r--r--drivers/net/bonding/bond_alb.c6
-rw-r--r--drivers/net/bonding/bond_main.c824
-rw-r--r--drivers/net/bonding/bond_sysfs.c103
-rw-r--r--drivers/net/bonding/bonding.h17
-rw-r--r--drivers/net/chelsio/cxgb2.c2
-rw-r--r--drivers/net/chelsio/sge.c70
-rw-r--r--drivers/net/cpmac.c35
-rw-r--r--drivers/net/cxgb3/adapter.h18
-rw-r--r--drivers/net/cxgb3/common.h1
-rw-r--r--drivers/net/cxgb3/cxgb3_ctl_defs.h5
-rw-r--r--drivers/net/cxgb3/cxgb3_ioctl.h1
-rw-r--r--drivers/net/cxgb3/cxgb3_main.c19
-rw-r--r--drivers/net/cxgb3/cxgb3_offload.c32
-rw-r--r--drivers/net/cxgb3/l2t.c2
-rw-r--r--drivers/net/cxgb3/regs.h10
-rw-r--r--drivers/net/cxgb3/sge.c391
-rw-r--r--drivers/net/cxgb3/t3_cpl.h51
-rw-r--r--drivers/net/cxgb3/t3cdev.h4
-rw-r--r--drivers/net/declance.c4
-rw-r--r--drivers/net/dl2k.c10
-rw-r--r--drivers/net/dm9000.c1161
-rw-r--r--drivers/net/dm9000.h11
-rw-r--r--drivers/net/e1000/e1000_main.c64
-rw-r--r--drivers/net/e1000e/e1000.h4
-rw-r--r--drivers/net/e1000e/netdev.c84
-rw-r--r--drivers/net/fealnx.c43
-rw-r--r--drivers/net/fec_mpc52xx.c2
-rw-r--r--drivers/net/forcedeth.c82
-rw-r--r--drivers/net/fs_enet/fs_enet-main.c33
-rw-r--r--drivers/net/gianfar.c82
-rw-r--r--drivers/net/gianfar.h11
-rw-r--r--drivers/net/hamachi.c12
-rw-r--r--drivers/net/hamradio/6pack.c26
-rw-r--r--drivers/net/hamradio/bpqether.c14
-rw-r--r--drivers/net/hamradio/mkiss.c2
-rw-r--r--drivers/net/hp.c14
-rw-r--r--drivers/net/hplance.c4
-rw-r--r--drivers/net/ibm_emac/Kconfig70
-rw-r--r--drivers/net/ibm_emac/Makefile11
-rw-r--r--drivers/net/ibm_emac/ibm_emac.h329
-rw-r--r--drivers/net/ibm_emac/ibm_emac_core.c2263
-rw-r--r--drivers/net/ibm_emac/ibm_emac_core.h222
-rw-r--r--drivers/net/ibm_emac/ibm_emac_debug.c211
-rw-r--r--drivers/net/ibm_emac/ibm_emac_debug.h62
-rw-r--r--drivers/net/ibm_emac/ibm_emac_mal.c570
-rw-r--r--drivers/net/ibm_emac/ibm_emac_mal.h267
-rw-r--r--drivers/net/ibm_emac/ibm_emac_phy.c398
-rw-r--r--drivers/net/ibm_emac/ibm_emac_phy.h80
-rw-r--r--drivers/net/ibm_emac/ibm_emac_rgmii.c200
-rw-r--r--drivers/net/ibm_emac/ibm_emac_rgmii.h64
-rw-r--r--drivers/net/ibm_emac/ibm_emac_tah.c110
-rw-r--r--drivers/net/ibm_emac/ibm_emac_tah.h87
-rw-r--r--drivers/net/ibm_emac/ibm_emac_zmii.c253
-rw-r--r--drivers/net/ibm_emac/ibm_emac_zmii.h82
-rw-r--r--drivers/net/ibm_newemac/core.c4
-rw-r--r--drivers/net/ifb.c14
-rw-r--r--drivers/net/igb/e1000_82575.c446
-rw-r--r--drivers/net/igb/e1000_82575.h36
-rw-r--r--drivers/net/igb/e1000_defines.h38
-rw-r--r--drivers/net/igb/e1000_hw.h16
-rw-r--r--drivers/net/igb/e1000_mac.c144
-rw-r--r--drivers/net/igb/e1000_mac.h1
-rw-r--r--drivers/net/igb/e1000_nvm.c52
-rw-r--r--drivers/net/igb/e1000_phy.c138
-rw-r--r--drivers/net/igb/e1000_regs.h9
-rw-r--r--drivers/net/igb/igb.h51
-rw-r--r--drivers/net/igb/igb_ethtool.c203
-rw-r--r--drivers/net/igb/igb_main.c1284
-rw-r--r--drivers/net/ipg.c105
-rw-r--r--drivers/net/ipg.h83
-rw-r--r--drivers/net/irda/ali-ircc.h2
-rw-r--r--drivers/net/irda/au1000_ircc.h1
-rw-r--r--drivers/net/irda/donauboe.c6
-rw-r--r--drivers/net/irda/smsc-ircc2.c1
-rw-r--r--drivers/net/irda/smsc-ircc2.h1
-rw-r--r--drivers/net/irda/via-ircc.h1
-rw-r--r--drivers/net/ixgb/Makefile2
-rw-r--r--drivers/net/ixgb/ixgb.h21
-rw-r--r--drivers/net/ixgb/ixgb_ee.c28
-rw-r--r--drivers/net/ixgb/ixgb_ee.h12
-rw-r--r--drivers/net/ixgb/ixgb_ethtool.c120
-rw-r--r--drivers/net/ixgb/ixgb_hw.c40
-rw-r--r--drivers/net/ixgb/ixgb_hw.h2
-rw-r--r--drivers/net/ixgb/ixgb_ids.h10
-rw-r--r--drivers/net/ixgb/ixgb_main.c499
-rw-r--r--drivers/net/ixgb/ixgb_osdep.h4
-rw-r--r--drivers/net/ixgb/ixgb_param.c44
-rw-r--r--drivers/net/ixgbe/ixgbe.h9
-rw-r--r--drivers/net/ixgbe/ixgbe_ethtool.c27
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c191
-rw-r--r--drivers/net/ixp2000/ixpdev.c4
-rw-r--r--drivers/net/lib8390.c100
-rw-r--r--drivers/net/loopback.c8
-rw-r--r--drivers/net/mac8390.c8
-rw-r--r--drivers/net/macb.c8
-rw-r--r--drivers/net/macsonic.c19
-rw-r--r--drivers/net/macvlan.c30
-rw-r--r--drivers/net/mv643xx_eth.c4557
-rw-r--r--drivers/net/myri10ge/myri10ge.c1076
-rw-r--r--drivers/net/natsemi.c4
-rw-r--r--drivers/net/ne.c14
-rw-r--r--drivers/net/ne2.c16
-rw-r--r--drivers/net/niu.c203
-rw-r--r--drivers/net/niu.h2
-rw-r--r--drivers/net/ns83820.c9
-rw-r--r--drivers/net/pci-skeleton.c1
-rw-r--r--drivers/net/pcmcia/3c574_cs.c47
-rw-r--r--drivers/net/pcmcia/3c589_cs.c49
-rw-r--r--drivers/net/pcmcia/axnet_cs.c70
-rw-r--r--drivers/net/pcnet32.c6
-rw-r--r--drivers/net/phy/Kconfig9
-rw-r--r--drivers/net/phy/Makefile1
-rw-r--r--drivers/net/phy/broadcom.c201
-rw-r--r--drivers/net/phy/mdio-bitbang.c2
-rw-r--r--drivers/net/phy/mdio-ofgpio.c205
-rw-r--r--drivers/net/ppp_generic.c22
-rw-r--r--drivers/net/ps3_gelic_net.c10
-rw-r--r--drivers/net/ps3_gelic_net.h2
-rw-r--r--drivers/net/ps3_gelic_wireless.c236
-rw-r--r--drivers/net/ps3_gelic_wireless.h7
-rw-r--r--drivers/net/qla3xxx.c4
-rw-r--r--drivers/net/r8169.c145
-rw-r--r--drivers/net/s2io.c183
-rw-r--r--drivers/net/s2io.h3
-rw-r--r--drivers/net/saa9730.c1139
-rw-r--r--drivers/net/saa9730.h384
-rw-r--r--drivers/net/sb1250-mac.c2
-rw-r--r--drivers/net/sfc/Kconfig2
-rw-r--r--drivers/net/sfc/Makefile2
-rw-r--r--drivers/net/sfc/boards.c2
-rw-r--r--drivers/net/sfc/boards.h3
-rw-r--r--drivers/net/sfc/efx.c6
-rw-r--r--drivers/net/sfc/falcon.c74
-rw-r--r--drivers/net/sfc/i2c-direct.c381
-rw-r--r--drivers/net/sfc/i2c-direct.h91
-rw-r--r--drivers/net/sfc/net_driver.h11
-rw-r--r--drivers/net/sfc/sfe4001.c126
-rw-r--r--drivers/net/sh_eth.c1174
-rw-r--r--drivers/net/sh_eth.h464
-rw-r--r--drivers/net/sis190.c2
-rw-r--r--drivers/net/sis900.c2
-rw-r--r--drivers/net/sky2.c241
-rw-r--r--drivers/net/sky2.h24
-rw-r--r--drivers/net/smc911x.c422
-rw-r--r--drivers/net/smc911x.h494
-rw-r--r--drivers/net/spider_net.c4
-rw-r--r--drivers/net/starfire.c111
-rw-r--r--drivers/net/sunlance.c4
-rw-r--r--drivers/net/tc35815.c2
-rw-r--r--drivers/net/tehuti.c2
-rw-r--r--drivers/net/tehuti.h1
-rw-r--r--drivers/net/tg3.c1268
-rw-r--r--drivers/net/tg3.h40
-rw-r--r--drivers/net/tlan.c490
-rw-r--r--drivers/net/tlan.h26
-rw-r--r--drivers/net/tokenring/3c359.c20
-rw-r--r--drivers/net/tokenring/3c359.h2
-rw-r--r--drivers/net/tsi108_eth.c11
-rw-r--r--drivers/net/tulip/21142.c6
-rw-r--r--drivers/net/tulip/de2104x.c10
-rw-r--r--drivers/net/tulip/eeprom.c6
-rw-r--r--drivers/net/tulip/interrupt.c5
-rw-r--r--drivers/net/tulip/media.c5
-rw-r--r--drivers/net/tulip/pnic.c5
-rw-r--r--drivers/net/tulip/pnic2.c5
-rw-r--r--drivers/net/tulip/timer.c6
-rw-r--r--drivers/net/tulip/tulip.h4
-rw-r--r--drivers/net/tulip/tulip_core.c8
-rw-r--r--drivers/net/tun.c458
-rw-r--r--drivers/net/typhoon.c3
-rw-r--r--drivers/net/ucc_geth.c33
-rw-r--r--drivers/net/ucc_geth_ethtool.c4
-rw-r--r--drivers/net/usb/Kconfig10
-rw-r--r--drivers/net/usb/Makefile1
-rw-r--r--drivers/net/usb/hso.c2836
-rw-r--r--drivers/net/usb/rndis_host.c14
-rw-r--r--drivers/net/via-rhine.c27
-rw-r--r--drivers/net/via-velocity.c183
-rw-r--r--drivers/net/via-velocity.h5
-rw-r--r--drivers/net/virtio_net.c3
-rw-r--r--drivers/net/wan/Kconfig3
-rw-r--r--drivers/net/wan/c101.c6
-rw-r--r--drivers/net/wan/dscc4.c22
-rw-r--r--drivers/net/wan/farsync.c70
-rw-r--r--drivers/net/wan/hd6457x.c33
-rw-r--r--drivers/net/wan/hdlc.c2
-rw-r--r--drivers/net/wan/hdlc_cisco.c4
-rw-r--r--drivers/net/wan/hdlc_fr.c54
-rw-r--r--drivers/net/wan/hdlc_raw_eth.c2
-rw-r--r--drivers/net/wan/hdlc_x25.c6
-rw-r--r--drivers/net/wan/pc300_drv.c71
-rw-r--r--drivers/net/wan/pc300_tty.c6
-rw-r--r--drivers/net/wan/wanxl.c26
-rw-r--r--drivers/net/wireless/Kconfig25
-rw-r--r--drivers/net/wireless/Makefile2
-rw-r--r--drivers/net/wireless/adm8211.c58
-rw-r--r--drivers/net/wireless/adm8211.h1
-rw-r--r--drivers/net/wireless/airo.c156
-rw-r--r--drivers/net/wireless/arlan-main.c40
-rw-r--r--drivers/net/wireless/arlan.h1
-rw-r--r--drivers/net/wireless/ath5k/Kconfig3
-rw-r--r--drivers/net/wireless/ath5k/base.c377
-rw-r--r--drivers/net/wireless/ath5k/base.h36
-rw-r--r--drivers/net/wireless/ath5k/hw.c4
-rw-r--r--drivers/net/wireless/atmel.c70
-rw-r--r--drivers/net/wireless/b43/b43.h49
-rw-r--r--drivers/net/wireless/b43/debugfs.c436
-rw-r--r--drivers/net/wireless/b43/debugfs.h24
-rw-r--r--drivers/net/wireless/b43/dma.c119
-rw-r--r--drivers/net/wireless/b43/dma.h3
-rw-r--r--drivers/net/wireless/b43/lo.c731
-rw-r--r--drivers/net/wireless/b43/lo.h115
-rw-r--r--drivers/net/wireless/b43/main.c450
-rw-r--r--drivers/net/wireless/b43/main.h7
-rw-r--r--drivers/net/wireless/b43/nphy.c2
-rw-r--r--drivers/net/wireless/b43/phy.c291
-rw-r--r--drivers/net/wireless/b43/phy.h16
-rw-r--r--drivers/net/wireless/b43/pio.c44
-rw-r--r--drivers/net/wireless/b43/pio.h8
-rw-r--r--drivers/net/wireless/b43/rfkill.c27
-rw-r--r--drivers/net/wireless/b43/xmit.c88
-rw-r--r--drivers/net/wireless/b43/xmit.h4
-rw-r--r--drivers/net/wireless/b43legacy/b43legacy.h17
-rw-r--r--drivers/net/wireless/b43legacy/dma.c172
-rw-r--r--drivers/net/wireless/b43legacy/dma.h7
-rw-r--r--drivers/net/wireless/b43legacy/main.c72
-rw-r--r--drivers/net/wireless/b43legacy/phy.c14
-rw-r--r--drivers/net/wireless/b43legacy/pio.c27
-rw-r--r--drivers/net/wireless/b43legacy/pio.h7
-rw-r--r--drivers/net/wireless/b43legacy/radio.c12
-rw-r--r--drivers/net/wireless/b43legacy/rfkill.c28
-rw-r--r--drivers/net/wireless/b43legacy/xmit.c70
-rw-r--r--drivers/net/wireless/b43legacy/xmit.h2
-rw-r--r--drivers/net/wireless/hostap/hostap.h3
-rw-r--r--drivers/net/wireless/hostap/hostap_80211_rx.c21
-rw-r--r--drivers/net/wireless/hostap/hostap_ap.c32
-rw-r--r--drivers/net/wireless/hostap/hostap_hw.c19
-rw-r--r--drivers/net/wireless/hostap/hostap_ioctl.c63
-rw-r--r--drivers/net/wireless/hostap/hostap_main.c20
-rw-r--r--drivers/net/wireless/hostap/hostap_wlan.h14
-rw-r--r--drivers/net/wireless/iwlwifi/Kconfig32
-rw-r--r--drivers/net/wireless/iwlwifi/Makefile11
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-hw.h13
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-led.c146
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-led.h2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-rs.c17
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.c131
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.h51
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-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c4004
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-5000-hw.h134
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-5000.c1580
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-calib.c802
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-calib.h84
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-commands.h (renamed from drivers/net/wireless/iwlwifi/iwl-4965-commands.h)462
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-core.c1259
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-core.h219
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-csr.h38
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-debug.h31
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-debugfs.c103
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-dev.h (renamed from drivers/net/wireless/iwlwifi/iwl-4965.h)567
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.c171
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.h206
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-fh.h391
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-hcmd.c15
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-helpers.h92
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-led.c209
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-led.h5
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-power.c423
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-power.h76
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-prph.h333
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-rfkill.c106
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-rfkill.h6
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-rx.c1321
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-scan.c931
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-sta.c712
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-sta.h28
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-tx.c1519
-rw-r--r--drivers/net/wireless/iwlwifi/iwl3945-base.c535
-rw-r--r--drivers/net/wireless/iwlwifi/iwl4965-base.c5004
-rw-r--r--drivers/net/wireless/libertas/Makefile8
-rw-r--r--drivers/net/wireless/libertas/assoc.c8
-rw-r--r--drivers/net/wireless/libertas/cmd.c192
-rw-r--r--drivers/net/wireless/libertas/cmd.h8
-rw-r--r--drivers/net/wireless/libertas/cmdresp.c25
-rw-r--r--drivers/net/wireless/libertas/decl.h8
-rw-r--r--drivers/net/wireless/libertas/defs.h14
-rw-r--r--drivers/net/wireless/libertas/dev.h8
-rw-r--r--drivers/net/wireless/libertas/host.h17
-rw-r--r--drivers/net/wireless/libertas/hostcmd.h4
-rw-r--r--drivers/net/wireless/libertas/if_cs.c315
-rw-r--r--drivers/net/wireless/libertas/if_usb.c22
-rw-r--r--drivers/net/wireless/libertas/main.c254
-rw-r--r--drivers/net/wireless/libertas/persistcfg.c453
-rw-r--r--drivers/net/wireless/libertas/rx.c4
-rw-r--r--drivers/net/wireless/libertas/scan.c36
-rw-r--r--drivers/net/wireless/libertas/types.h30
-rw-r--r--drivers/net/wireless/libertas/wext.c32
-rw-r--r--drivers/net/wireless/mac80211_hwsim.c515
-rw-r--r--drivers/net/wireless/orinoco.c30
-rw-r--r--drivers/net/wireless/p54/p54.h2
-rw-r--r--drivers/net/wireless/p54/p54common.c138
-rw-r--r--drivers/net/wireless/p54/p54common.h1
-rw-r--r--drivers/net/wireless/p54/p54pci.c2
-rw-r--r--drivers/net/wireless/prism54/isl_ioctl.c49
-rw-r--r--drivers/net/wireless/rndis_wlan.c205
-rw-r--r--drivers/net/wireless/rt2x00/Kconfig63
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c352
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.h7
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c312
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.h11
-rw-r--r--drivers/net/wireless/rt2x00/rt2500usb.c307
-rw-r--r--drivers/net/wireless/rt2x00/rt2500usb.h47
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h105
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00config.c2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00debug.c10
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00dev.c362
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00firmware.c8
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00lib.h78
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00mac.c172
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.c231
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.h45
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.c413
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.h136
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00reg.h145
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00rfkill.c114
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.c361
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.h69
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c344
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.h7
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c270
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.h7
-rw-r--r--drivers/net/wireless/rtl8180_dev.c71
-rw-r--r--drivers/net/wireless/rtl8187.h119
-rw-r--r--drivers/net/wireless/rtl8187_dev.c558
-rw-r--r--drivers/net/wireless/rtl8187_rtl8225.c250
-rw-r--r--drivers/net/wireless/rtl8187_rtl8225.h15
-rw-r--r--drivers/net/wireless/rtl818x.h36
-rw-r--r--drivers/net/wireless/wl3501_cs.c10
-rw-r--r--drivers/net/wireless/zd1201.c21
-rw-r--r--drivers/net/wireless/zd1211rw/zd_mac.c262
-rw-r--r--drivers/net/wireless/zd1211rw/zd_mac.h16
-rw-r--r--drivers/net/wireless/zd1211rw/zd_usb.c29
379 files changed, 73427 insertions, 53115 deletions
diff --git a/drivers/net/3c503.c b/drivers/net/3c503.c
index 9c23336750e2..900b0ffdcc68 100644
--- a/drivers/net/3c503.c
+++ b/drivers/net/3c503.c
@@ -149,7 +149,7 @@ el2_pio_probe(struct net_device *dev)
149#ifndef MODULE 149#ifndef MODULE
150struct net_device * __init el2_probe(int unit) 150struct net_device * __init el2_probe(int unit)
151{ 151{
152 struct net_device *dev = alloc_ei_netdev(); 152 struct net_device *dev = alloc_eip_netdev();
153 int err; 153 int err;
154 154
155 if (!dev) 155 if (!dev)
@@ -340,7 +340,7 @@ el2_probe1(struct net_device *dev, int ioaddr)
340 dev->stop = &el2_close; 340 dev->stop = &el2_close;
341 dev->ethtool_ops = &netdev_ethtool_ops; 341 dev->ethtool_ops = &netdev_ethtool_ops;
342#ifdef CONFIG_NET_POLL_CONTROLLER 342#ifdef CONFIG_NET_POLL_CONTROLLER
343 dev->poll_controller = ei_poll; 343 dev->poll_controller = eip_poll;
344#endif 344#endif
345 345
346 retval = register_netdev(dev); 346 retval = register_netdev(dev);
@@ -386,7 +386,7 @@ el2_open(struct net_device *dev)
386 outb_p(0x00, E33G_IDCFR); 386 outb_p(0x00, E33G_IDCFR);
387 if (*irqp == probe_irq_off(cookie) /* It's a good IRQ line! */ 387 if (*irqp == probe_irq_off(cookie) /* It's a good IRQ line! */
388 && ((retval = request_irq(dev->irq = *irqp, 388 && ((retval = request_irq(dev->irq = *irqp,
389 ei_interrupt, 0, dev->name, dev)) == 0)) 389 eip_interrupt, 0, dev->name, dev)) == 0))
390 break; 390 break;
391 } 391 }
392 } while (*++irqp); 392 } while (*++irqp);
@@ -395,13 +395,13 @@ el2_open(struct net_device *dev)
395 return retval; 395 return retval;
396 } 396 }
397 } else { 397 } else {
398 if ((retval = request_irq(dev->irq, ei_interrupt, 0, dev->name, dev))) { 398 if ((retval = request_irq(dev->irq, eip_interrupt, 0, dev->name, dev))) {
399 return retval; 399 return retval;
400 } 400 }
401 } 401 }
402 402
403 el2_init_card(dev); 403 el2_init_card(dev);
404 ei_open(dev); 404 eip_open(dev);
405 return 0; 405 return 0;
406} 406}
407 407
@@ -412,7 +412,7 @@ el2_close(struct net_device *dev)
412 dev->irq = ei_status.saved_irq; 412 dev->irq = ei_status.saved_irq;
413 outb(EGACFR_IRQOFF, E33G_GACFR); /* disable interrupts. */ 413 outb(EGACFR_IRQOFF, E33G_GACFR); /* disable interrupts. */
414 414
415 ei_close(dev); 415 eip_close(dev);
416 return 0; 416 return 0;
417} 417}
418 418
@@ -698,7 +698,7 @@ init_module(void)
698 if (this_dev != 0) break; /* only autoprobe 1st one */ 698 if (this_dev != 0) break; /* only autoprobe 1st one */
699 printk(KERN_NOTICE "3c503.c: Presently autoprobing (not recommended) for a single card.\n"); 699 printk(KERN_NOTICE "3c503.c: Presently autoprobing (not recommended) for a single card.\n");
700 } 700 }
701 dev = alloc_ei_netdev(); 701 dev = alloc_eip_netdev();
702 if (!dev) 702 if (!dev)
703 break; 703 break;
704 dev->irq = irq[this_dev]; 704 dev->irq = irq[this_dev];
diff --git a/drivers/net/3c515.c b/drivers/net/3c515.c
index 105a8c7ca7e9..e4e3241628d6 100644
--- a/drivers/net/3c515.c
+++ b/drivers/net/3c515.c
@@ -572,12 +572,16 @@ static int corkscrew_setup(struct net_device *dev, int ioaddr,
572 int irq; 572 int irq;
573 DECLARE_MAC_BUF(mac); 573 DECLARE_MAC_BUF(mac);
574 574
575#ifdef __ISAPNP__
575 if (idev) { 576 if (idev) {
576 irq = pnp_irq(idev, 0); 577 irq = pnp_irq(idev, 0);
577 vp->dev = &idev->dev; 578 vp->dev = &idev->dev;
578 } else { 579 } else {
579 irq = inw(ioaddr + 0x2002) & 15; 580 irq = inw(ioaddr + 0x2002) & 15;
580 } 581 }
582#else
583 irq = inw(ioaddr + 0x2002) & 15;
584#endif
581 585
582 dev->base_addr = ioaddr; 586 dev->base_addr = ioaddr;
583 dev->irq = irq; 587 dev->irq = irq;
diff --git a/drivers/net/3c523.c b/drivers/net/3c523.c
index 239fc42fb8df..dc6e474229b1 100644
--- a/drivers/net/3c523.c
+++ b/drivers/net/3c523.c
@@ -202,7 +202,6 @@ static void elmc_xmt_int(struct net_device *dev);
202static void elmc_rnr_int(struct net_device *dev); 202static void elmc_rnr_int(struct net_device *dev);
203 203
204struct priv { 204struct priv {
205 struct net_device_stats stats;
206 unsigned long base; 205 unsigned long base;
207 char *memtop; 206 char *memtop;
208 unsigned long mapped_start; /* Start of ioremap */ 207 unsigned long mapped_start; /* Start of ioremap */
@@ -989,18 +988,18 @@ static void elmc_rcv_int(struct net_device *dev)
989 skb->protocol = eth_type_trans(skb, dev); 988 skb->protocol = eth_type_trans(skb, dev);
990 netif_rx(skb); 989 netif_rx(skb);
991 dev->last_rx = jiffies; 990 dev->last_rx = jiffies;
992 p->stats.rx_packets++; 991 dev->stats.rx_packets++;
993 p->stats.rx_bytes += totlen; 992 dev->stats.rx_bytes += totlen;
994 } else { 993 } else {
995 p->stats.rx_dropped++; 994 dev->stats.rx_dropped++;
996 } 995 }
997 } else { 996 } else {
998 printk(KERN_WARNING "%s: received oversized frame.\n", dev->name); 997 printk(KERN_WARNING "%s: received oversized frame.\n", dev->name);
999 p->stats.rx_dropped++; 998 dev->stats.rx_dropped++;
1000 } 999 }
1001 } else { /* frame !(ok), only with 'save-bad-frames' */ 1000 } else { /* frame !(ok), only with 'save-bad-frames' */
1002 printk(KERN_WARNING "%s: oops! rfd-error-status: %04x\n", dev->name, status); 1001 printk(KERN_WARNING "%s: oops! rfd-error-status: %04x\n", dev->name, status);
1003 p->stats.rx_errors++; 1002 dev->stats.rx_errors++;
1004 } 1003 }
1005 p->rfd_top->status = 0; 1004 p->rfd_top->status = 0;
1006 p->rfd_top->last = RFD_SUSP; 1005 p->rfd_top->last = RFD_SUSP;
@@ -1018,7 +1017,7 @@ static void elmc_rnr_int(struct net_device *dev)
1018{ 1017{
1019 struct priv *p = (struct priv *) dev->priv; 1018 struct priv *p = (struct priv *) dev->priv;
1020 1019
1021 p->stats.rx_errors++; 1020 dev->stats.rx_errors++;
1022 1021
1023 WAIT_4_SCB_CMD(); /* wait for the last cmd */ 1022 WAIT_4_SCB_CMD(); /* wait for the last cmd */
1024 p->scb->cmd = RUC_ABORT; /* usually the RU is in the 'no resource'-state .. abort it now. */ 1023 p->scb->cmd = RUC_ABORT; /* usually the RU is in the 'no resource'-state .. abort it now. */
@@ -1046,24 +1045,24 @@ static void elmc_xmt_int(struct net_device *dev)
1046 printk(KERN_WARNING "%s: strange .. xmit-int without a 'COMPLETE'\n", dev->name); 1045 printk(KERN_WARNING "%s: strange .. xmit-int without a 'COMPLETE'\n", dev->name);
1047 } 1046 }
1048 if (status & STAT_OK) { 1047 if (status & STAT_OK) {
1049 p->stats.tx_packets++; 1048 dev->stats.tx_packets++;
1050 p->stats.collisions += (status & TCMD_MAXCOLLMASK); 1049 dev->stats.collisions += (status & TCMD_MAXCOLLMASK);
1051 } else { 1050 } else {
1052 p->stats.tx_errors++; 1051 dev->stats.tx_errors++;
1053 if (status & TCMD_LATECOLL) { 1052 if (status & TCMD_LATECOLL) {
1054 printk(KERN_WARNING "%s: late collision detected.\n", dev->name); 1053 printk(KERN_WARNING "%s: late collision detected.\n", dev->name);
1055 p->stats.collisions++; 1054 dev->stats.collisions++;
1056 } else if (status & TCMD_NOCARRIER) { 1055 } else if (status & TCMD_NOCARRIER) {
1057 p->stats.tx_carrier_errors++; 1056 dev->stats.tx_carrier_errors++;
1058 printk(KERN_WARNING "%s: no carrier detected.\n", dev->name); 1057 printk(KERN_WARNING "%s: no carrier detected.\n", dev->name);
1059 } else if (status & TCMD_LOSTCTS) { 1058 } else if (status & TCMD_LOSTCTS) {
1060 printk(KERN_WARNING "%s: loss of CTS detected.\n", dev->name); 1059 printk(KERN_WARNING "%s: loss of CTS detected.\n", dev->name);
1061 } else if (status & TCMD_UNDERRUN) { 1060 } else if (status & TCMD_UNDERRUN) {
1062 p->stats.tx_fifo_errors++; 1061 dev->stats.tx_fifo_errors++;
1063 printk(KERN_WARNING "%s: DMA underrun detected.\n", dev->name); 1062 printk(KERN_WARNING "%s: DMA underrun detected.\n", dev->name);
1064 } else if (status & TCMD_MAXCOLL) { 1063 } else if (status & TCMD_MAXCOLL) {
1065 printk(KERN_WARNING "%s: Max. collisions exceeded.\n", dev->name); 1064 printk(KERN_WARNING "%s: Max. collisions exceeded.\n", dev->name);
1066 p->stats.collisions += 16; 1065 dev->stats.collisions += 16;
1067 } 1066 }
1068 } 1067 }
1069 1068
@@ -1215,12 +1214,12 @@ static struct net_device_stats *elmc_get_stats(struct net_device *dev)
1215 ovrn = p->scb->ovrn_errs; 1214 ovrn = p->scb->ovrn_errs;
1216 p->scb->ovrn_errs -= ovrn; 1215 p->scb->ovrn_errs -= ovrn;
1217 1216
1218 p->stats.rx_crc_errors += crc; 1217 dev->stats.rx_crc_errors += crc;
1219 p->stats.rx_fifo_errors += ovrn; 1218 dev->stats.rx_fifo_errors += ovrn;
1220 p->stats.rx_frame_errors += aln; 1219 dev->stats.rx_frame_errors += aln;
1221 p->stats.rx_dropped += rsc; 1220 dev->stats.rx_dropped += rsc;
1222 1221
1223 return &p->stats; 1222 return &dev->stats;
1224} 1223}
1225 1224
1226/******************************************************** 1225/********************************************************
diff --git a/drivers/net/3c527.c b/drivers/net/3c527.c
index fae295b6809c..6aca0c640f13 100644
--- a/drivers/net/3c527.c
+++ b/drivers/net/3c527.c
@@ -158,7 +158,6 @@ struct mc32_local
158 int slot; 158 int slot;
159 159
160 u32 base; 160 u32 base;
161 struct net_device_stats net_stats;
162 volatile struct mc32_mailbox *rx_box; 161 volatile struct mc32_mailbox *rx_box;
163 volatile struct mc32_mailbox *tx_box; 162 volatile struct mc32_mailbox *tx_box;
164 volatile struct mc32_mailbox *exec_box; 163 volatile struct mc32_mailbox *exec_box;
@@ -1093,24 +1092,24 @@ static void mc32_update_stats(struct net_device *dev)
1093 1092
1094 u32 rx_errors=0; 1093 u32 rx_errors=0;
1095 1094
1096 rx_errors+=lp->net_stats.rx_crc_errors +=st->rx_crc_errors; 1095 rx_errors+=dev->stats.rx_crc_errors +=st->rx_crc_errors;
1097 st->rx_crc_errors=0; 1096 st->rx_crc_errors=0;
1098 rx_errors+=lp->net_stats.rx_fifo_errors +=st->rx_overrun_errors; 1097 rx_errors+=dev->stats.rx_fifo_errors +=st->rx_overrun_errors;
1099 st->rx_overrun_errors=0; 1098 st->rx_overrun_errors=0;
1100 rx_errors+=lp->net_stats.rx_frame_errors +=st->rx_alignment_errors; 1099 rx_errors+=dev->stats.rx_frame_errors +=st->rx_alignment_errors;
1101 st->rx_alignment_errors=0; 1100 st->rx_alignment_errors=0;
1102 rx_errors+=lp->net_stats.rx_length_errors+=st->rx_tooshort_errors; 1101 rx_errors+=dev->stats.rx_length_errors+=st->rx_tooshort_errors;
1103 st->rx_tooshort_errors=0; 1102 st->rx_tooshort_errors=0;
1104 rx_errors+=lp->net_stats.rx_missed_errors+=st->rx_outofresource_errors; 1103 rx_errors+=dev->stats.rx_missed_errors+=st->rx_outofresource_errors;
1105 st->rx_outofresource_errors=0; 1104 st->rx_outofresource_errors=0;
1106 lp->net_stats.rx_errors=rx_errors; 1105 dev->stats.rx_errors=rx_errors;
1107 1106
1108 /* Number of packets which saw one collision */ 1107 /* Number of packets which saw one collision */
1109 lp->net_stats.collisions+=st->dataC[10]; 1108 dev->stats.collisions+=st->dataC[10];
1110 st->dataC[10]=0; 1109 st->dataC[10]=0;
1111 1110
1112 /* Number of packets which saw 2--15 collisions */ 1111 /* Number of packets which saw 2--15 collisions */
1113 lp->net_stats.collisions+=st->dataC[11]; 1112 dev->stats.collisions+=st->dataC[11];
1114 st->dataC[11]=0; 1113 st->dataC[11]=0;
1115} 1114}
1116 1115
@@ -1178,7 +1177,7 @@ static void mc32_rx_ring(struct net_device *dev)
1178 skb=dev_alloc_skb(length+2); 1177 skb=dev_alloc_skb(length+2);
1179 1178
1180 if(skb==NULL) { 1179 if(skb==NULL) {
1181 lp->net_stats.rx_dropped++; 1180 dev->stats.rx_dropped++;
1182 goto dropped; 1181 goto dropped;
1183 } 1182 }
1184 1183
@@ -1189,8 +1188,8 @@ static void mc32_rx_ring(struct net_device *dev)
1189 1188
1190 skb->protocol=eth_type_trans(skb,dev); 1189 skb->protocol=eth_type_trans(skb,dev);
1191 dev->last_rx = jiffies; 1190 dev->last_rx = jiffies;
1192 lp->net_stats.rx_packets++; 1191 dev->stats.rx_packets++;
1193 lp->net_stats.rx_bytes += length; 1192 dev->stats.rx_bytes += length;
1194 netif_rx(skb); 1193 netif_rx(skb);
1195 } 1194 }
1196 1195
@@ -1253,34 +1252,34 @@ static void mc32_tx_ring(struct net_device *dev)
1253 /* Not COMPLETED */ 1252 /* Not COMPLETED */
1254 break; 1253 break;
1255 } 1254 }
1256 lp->net_stats.tx_packets++; 1255 dev->stats.tx_packets++;
1257 if(!(np->status & (1<<6))) /* Not COMPLETED_OK */ 1256 if(!(np->status & (1<<6))) /* Not COMPLETED_OK */
1258 { 1257 {
1259 lp->net_stats.tx_errors++; 1258 dev->stats.tx_errors++;
1260 1259
1261 switch(np->status&0x0F) 1260 switch(np->status&0x0F)
1262 { 1261 {
1263 case 1: 1262 case 1:
1264 lp->net_stats.tx_aborted_errors++; 1263 dev->stats.tx_aborted_errors++;
1265 break; /* Max collisions */ 1264 break; /* Max collisions */
1266 case 2: 1265 case 2:
1267 lp->net_stats.tx_fifo_errors++; 1266 dev->stats.tx_fifo_errors++;
1268 break; 1267 break;
1269 case 3: 1268 case 3:
1270 lp->net_stats.tx_carrier_errors++; 1269 dev->stats.tx_carrier_errors++;
1271 break; 1270 break;
1272 case 4: 1271 case 4:
1273 lp->net_stats.tx_window_errors++; 1272 dev->stats.tx_window_errors++;
1274 break; /* CTS Lost */ 1273 break; /* CTS Lost */
1275 case 5: 1274 case 5:
1276 lp->net_stats.tx_aborted_errors++; 1275 dev->stats.tx_aborted_errors++;
1277 break; /* Transmit timeout */ 1276 break; /* Transmit timeout */
1278 } 1277 }
1279 } 1278 }
1280 /* Packets are sent in order - this is 1279 /* Packets are sent in order - this is
1281 basically a FIFO queue of buffers matching 1280 basically a FIFO queue of buffers matching
1282 the card ring */ 1281 the card ring */
1283 lp->net_stats.tx_bytes+=lp->tx_ring[t].skb->len; 1282 dev->stats.tx_bytes+=lp->tx_ring[t].skb->len;
1284 dev_kfree_skb_irq(lp->tx_ring[t].skb); 1283 dev_kfree_skb_irq(lp->tx_ring[t].skb);
1285 lp->tx_ring[t].skb=NULL; 1284 lp->tx_ring[t].skb=NULL;
1286 atomic_inc(&lp->tx_count); 1285 atomic_inc(&lp->tx_count);
@@ -1367,7 +1366,7 @@ static irqreturn_t mc32_interrupt(int irq, void *dev_id)
1367 case 6: 1366 case 6:
1368 /* Out of RX buffers stat */ 1367 /* Out of RX buffers stat */
1369 /* Must restart rx */ 1368 /* Must restart rx */
1370 lp->net_stats.rx_dropped++; 1369 dev->stats.rx_dropped++;
1371 mc32_rx_ring(dev); 1370 mc32_rx_ring(dev);
1372 mc32_start_transceiver(dev); 1371 mc32_start_transceiver(dev);
1373 break; 1372 break;
@@ -1489,10 +1488,8 @@ static int mc32_close(struct net_device *dev)
1489 1488
1490static struct net_device_stats *mc32_get_stats(struct net_device *dev) 1489static struct net_device_stats *mc32_get_stats(struct net_device *dev)
1491{ 1490{
1492 struct mc32_local *lp = netdev_priv(dev);
1493
1494 mc32_update_stats(dev); 1491 mc32_update_stats(dev);
1495 return &lp->net_stats; 1492 return &dev->stats;
1496} 1493}
1497 1494
1498 1495
diff --git a/drivers/net/8139cp.c b/drivers/net/8139cp.c
index a453eda834d5..6011d6fabef0 100644
--- a/drivers/net/8139cp.c
+++ b/drivers/net/8139cp.c
@@ -340,7 +340,6 @@ struct cp_private {
340 u32 rx_config; 340 u32 rx_config;
341 u16 cpcmd; 341 u16 cpcmd;
342 342
343 struct net_device_stats net_stats;
344 struct cp_extra_stats cp_stats; 343 struct cp_extra_stats cp_stats;
345 344
346 unsigned rx_head ____cacheline_aligned; 345 unsigned rx_head ____cacheline_aligned;
@@ -457,8 +456,8 @@ static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
457{ 456{
458 skb->protocol = eth_type_trans (skb, cp->dev); 457 skb->protocol = eth_type_trans (skb, cp->dev);
459 458
460 cp->net_stats.rx_packets++; 459 cp->dev->stats.rx_packets++;
461 cp->net_stats.rx_bytes += skb->len; 460 cp->dev->stats.rx_bytes += skb->len;
462 cp->dev->last_rx = jiffies; 461 cp->dev->last_rx = jiffies;
463 462
464#if CP_VLAN_TAG_USED 463#if CP_VLAN_TAG_USED
@@ -477,17 +476,17 @@ static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
477 printk (KERN_DEBUG 476 printk (KERN_DEBUG
478 "%s: rx err, slot %d status 0x%x len %d\n", 477 "%s: rx err, slot %d status 0x%x len %d\n",
479 cp->dev->name, rx_tail, status, len); 478 cp->dev->name, rx_tail, status, len);
480 cp->net_stats.rx_errors++; 479 cp->dev->stats.rx_errors++;
481 if (status & RxErrFrame) 480 if (status & RxErrFrame)
482 cp->net_stats.rx_frame_errors++; 481 cp->dev->stats.rx_frame_errors++;
483 if (status & RxErrCRC) 482 if (status & RxErrCRC)
484 cp->net_stats.rx_crc_errors++; 483 cp->dev->stats.rx_crc_errors++;
485 if ((status & RxErrRunt) || (status & RxErrLong)) 484 if ((status & RxErrRunt) || (status & RxErrLong))
486 cp->net_stats.rx_length_errors++; 485 cp->dev->stats.rx_length_errors++;
487 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) 486 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
488 cp->net_stats.rx_length_errors++; 487 cp->dev->stats.rx_length_errors++;
489 if (status & RxErrFIFO) 488 if (status & RxErrFIFO)
490 cp->net_stats.rx_fifo_errors++; 489 cp->dev->stats.rx_fifo_errors++;
491} 490}
492 491
493static inline unsigned int cp_rx_csum_ok (u32 status) 492static inline unsigned int cp_rx_csum_ok (u32 status)
@@ -539,7 +538,7 @@ rx_status_loop:
539 * that RX fragments are never encountered 538 * that RX fragments are never encountered
540 */ 539 */
541 cp_rx_err_acct(cp, rx_tail, status, len); 540 cp_rx_err_acct(cp, rx_tail, status, len);
542 cp->net_stats.rx_dropped++; 541 dev->stats.rx_dropped++;
543 cp->cp_stats.rx_frags++; 542 cp->cp_stats.rx_frags++;
544 goto rx_next; 543 goto rx_next;
545 } 544 }
@@ -556,7 +555,7 @@ rx_status_loop:
556 buflen = cp->rx_buf_sz + RX_OFFSET; 555 buflen = cp->rx_buf_sz + RX_OFFSET;
557 new_skb = dev_alloc_skb (buflen); 556 new_skb = dev_alloc_skb (buflen);
558 if (!new_skb) { 557 if (!new_skb) {
559 cp->net_stats.rx_dropped++; 558 dev->stats.rx_dropped++;
560 goto rx_next; 559 goto rx_next;
561 } 560 }
562 561
@@ -710,20 +709,20 @@ static void cp_tx (struct cp_private *cp)
710 if (netif_msg_tx_err(cp)) 709 if (netif_msg_tx_err(cp))
711 printk(KERN_DEBUG "%s: tx err, status 0x%x\n", 710 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
712 cp->dev->name, status); 711 cp->dev->name, status);
713 cp->net_stats.tx_errors++; 712 cp->dev->stats.tx_errors++;
714 if (status & TxOWC) 713 if (status & TxOWC)
715 cp->net_stats.tx_window_errors++; 714 cp->dev->stats.tx_window_errors++;
716 if (status & TxMaxCol) 715 if (status & TxMaxCol)
717 cp->net_stats.tx_aborted_errors++; 716 cp->dev->stats.tx_aborted_errors++;
718 if (status & TxLinkFail) 717 if (status & TxLinkFail)
719 cp->net_stats.tx_carrier_errors++; 718 cp->dev->stats.tx_carrier_errors++;
720 if (status & TxFIFOUnder) 719 if (status & TxFIFOUnder)
721 cp->net_stats.tx_fifo_errors++; 720 cp->dev->stats.tx_fifo_errors++;
722 } else { 721 } else {
723 cp->net_stats.collisions += 722 cp->dev->stats.collisions +=
724 ((status >> TxColCntShift) & TxColCntMask); 723 ((status >> TxColCntShift) & TxColCntMask);
725 cp->net_stats.tx_packets++; 724 cp->dev->stats.tx_packets++;
726 cp->net_stats.tx_bytes += skb->len; 725 cp->dev->stats.tx_bytes += skb->len;
727 if (netif_msg_tx_done(cp)) 726 if (netif_msg_tx_done(cp))
728 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail); 727 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
729 } 728 }
@@ -956,7 +955,7 @@ static void cp_set_rx_mode (struct net_device *dev)
956static void __cp_get_stats(struct cp_private *cp) 955static void __cp_get_stats(struct cp_private *cp)
957{ 956{
958 /* only lower 24 bits valid; write any value to clear */ 957 /* only lower 24 bits valid; write any value to clear */
959 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff); 958 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
960 cpw32 (RxMissed, 0); 959 cpw32 (RxMissed, 0);
961} 960}
962 961
@@ -971,7 +970,7 @@ static struct net_device_stats *cp_get_stats(struct net_device *dev)
971 __cp_get_stats(cp); 970 __cp_get_stats(cp);
972 spin_unlock_irqrestore(&cp->lock, flags); 971 spin_unlock_irqrestore(&cp->lock, flags);
973 972
974 return &cp->net_stats; 973 return &dev->stats;
975} 974}
976 975
977static void cp_stop_hw (struct cp_private *cp) 976static void cp_stop_hw (struct cp_private *cp)
@@ -1142,7 +1141,7 @@ static void cp_clean_rings (struct cp_private *cp)
1142 PCI_DMA_TODEVICE); 1141 PCI_DMA_TODEVICE);
1143 if (le32_to_cpu(desc->opts1) & LastFrag) 1142 if (le32_to_cpu(desc->opts1) & LastFrag)
1144 dev_kfree_skb(skb); 1143 dev_kfree_skb(skb);
1145 cp->net_stats.tx_dropped++; 1144 cp->dev->stats.tx_dropped++;
1146 } 1145 }
1147 } 1146 }
1148 1147
@@ -1214,7 +1213,6 @@ static int cp_close (struct net_device *dev)
1214 1213
1215 spin_unlock_irqrestore(&cp->lock, flags); 1214 spin_unlock_irqrestore(&cp->lock, flags);
1216 1215
1217 synchronize_irq(dev->irq);
1218 free_irq(dev->irq, dev); 1216 free_irq(dev->irq, dev);
1219 1217
1220 cp_free_rings(cp); 1218 cp_free_rings(cp);
diff --git a/drivers/net/8139too.c b/drivers/net/8139too.c
index 53bd903d2321..75317a14ad1c 100644
--- a/drivers/net/8139too.c
+++ b/drivers/net/8139too.c
@@ -107,8 +107,8 @@
107#include <linux/mii.h> 107#include <linux/mii.h>
108#include <linux/completion.h> 108#include <linux/completion.h>
109#include <linux/crc32.h> 109#include <linux/crc32.h>
110#include <asm/io.h> 110#include <linux/io.h>
111#include <asm/uaccess.h> 111#include <linux/uaccess.h>
112#include <asm/irq.h> 112#include <asm/irq.h>
113 113
114#define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION 114#define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
@@ -134,7 +134,7 @@
134 134
135#if RTL8139_DEBUG 135#if RTL8139_DEBUG
136/* note: prints function name for you */ 136/* note: prints function name for you */
137# define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args) 137# define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
138#else 138#else
139# define DPRINTK(fmt, args...) 139# define DPRINTK(fmt, args...)
140#endif 140#endif
@@ -145,7 +145,7 @@
145# define assert(expr) \ 145# define assert(expr) \
146 if(unlikely(!(expr))) { \ 146 if(unlikely(!(expr))) { \
147 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \ 147 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
148 #expr,__FILE__,__FUNCTION__,__LINE__); \ 148 #expr, __FILE__, __func__, __LINE__); \
149 } 149 }
150#endif 150#endif
151 151
@@ -219,7 +219,7 @@ enum {
219#define RTL8139B_IO_SIZE 256 219#define RTL8139B_IO_SIZE 256
220 220
221#define RTL8129_CAPS HAS_MII_XCVR 221#define RTL8129_CAPS HAS_MII_XCVR
222#define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG 222#define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
223 223
224typedef enum { 224typedef enum {
225 RTL8139 = 0, 225 RTL8139 = 0,
@@ -574,7 +574,6 @@ struct rtl8139_private {
574 u32 msg_enable; 574 u32 msg_enable;
575 struct napi_struct napi; 575 struct napi_struct napi;
576 struct net_device *dev; 576 struct net_device *dev;
577 struct net_device_stats stats;
578 577
579 unsigned char *rx_ring; 578 unsigned char *rx_ring;
580 unsigned int cur_rx; /* RX buf index of next pkt */ 579 unsigned int cur_rx; /* RX buf index of next pkt */
@@ -1711,7 +1710,7 @@ static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1711 dev_kfree_skb(skb); 1710 dev_kfree_skb(skb);
1712 } else { 1711 } else {
1713 dev_kfree_skb(skb); 1712 dev_kfree_skb(skb);
1714 tp->stats.tx_dropped++; 1713 dev->stats.tx_dropped++;
1715 return 0; 1714 return 0;
1716 } 1715 }
1717 1716
@@ -1762,27 +1761,27 @@ static void rtl8139_tx_interrupt (struct net_device *dev,
1762 if (netif_msg_tx_err(tp)) 1761 if (netif_msg_tx_err(tp))
1763 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n", 1762 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1764 dev->name, txstatus); 1763 dev->name, txstatus);
1765 tp->stats.tx_errors++; 1764 dev->stats.tx_errors++;
1766 if (txstatus & TxAborted) { 1765 if (txstatus & TxAborted) {
1767 tp->stats.tx_aborted_errors++; 1766 dev->stats.tx_aborted_errors++;
1768 RTL_W32 (TxConfig, TxClearAbt); 1767 RTL_W32 (TxConfig, TxClearAbt);
1769 RTL_W16 (IntrStatus, TxErr); 1768 RTL_W16 (IntrStatus, TxErr);
1770 wmb(); 1769 wmb();
1771 } 1770 }
1772 if (txstatus & TxCarrierLost) 1771 if (txstatus & TxCarrierLost)
1773 tp->stats.tx_carrier_errors++; 1772 dev->stats.tx_carrier_errors++;
1774 if (txstatus & TxOutOfWindow) 1773 if (txstatus & TxOutOfWindow)
1775 tp->stats.tx_window_errors++; 1774 dev->stats.tx_window_errors++;
1776 } else { 1775 } else {
1777 if (txstatus & TxUnderrun) { 1776 if (txstatus & TxUnderrun) {
1778 /* Add 64 to the Tx FIFO threshold. */ 1777 /* Add 64 to the Tx FIFO threshold. */
1779 if (tp->tx_flag < 0x00300000) 1778 if (tp->tx_flag < 0x00300000)
1780 tp->tx_flag += 0x00020000; 1779 tp->tx_flag += 0x00020000;
1781 tp->stats.tx_fifo_errors++; 1780 dev->stats.tx_fifo_errors++;
1782 } 1781 }
1783 tp->stats.collisions += (txstatus >> 24) & 15; 1782 dev->stats.collisions += (txstatus >> 24) & 15;
1784 tp->stats.tx_bytes += txstatus & 0x7ff; 1783 dev->stats.tx_bytes += txstatus & 0x7ff;
1785 tp->stats.tx_packets++; 1784 dev->stats.tx_packets++;
1786 } 1785 }
1787 1786
1788 dirty_tx++; 1787 dirty_tx++;
@@ -1818,7 +1817,7 @@ static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1818 if (netif_msg_rx_err (tp)) 1817 if (netif_msg_rx_err (tp))
1819 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n", 1818 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1820 dev->name, rx_status); 1819 dev->name, rx_status);
1821 tp->stats.rx_errors++; 1820 dev->stats.rx_errors++;
1822 if (!(rx_status & RxStatusOK)) { 1821 if (!(rx_status & RxStatusOK)) {
1823 if (rx_status & RxTooLong) { 1822 if (rx_status & RxTooLong) {
1824 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n", 1823 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
@@ -1826,11 +1825,11 @@ static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1826 /* A.C.: The chip hangs here. */ 1825 /* A.C.: The chip hangs here. */
1827 } 1826 }
1828 if (rx_status & (RxBadSymbol | RxBadAlign)) 1827 if (rx_status & (RxBadSymbol | RxBadAlign))
1829 tp->stats.rx_frame_errors++; 1828 dev->stats.rx_frame_errors++;
1830 if (rx_status & (RxRunt | RxTooLong)) 1829 if (rx_status & (RxRunt | RxTooLong))
1831 tp->stats.rx_length_errors++; 1830 dev->stats.rx_length_errors++;
1832 if (rx_status & RxCRCErr) 1831 if (rx_status & RxCRCErr)
1833 tp->stats.rx_crc_errors++; 1832 dev->stats.rx_crc_errors++;
1834 } else { 1833 } else {
1835 tp->xstats.rx_lost_in_ring++; 1834 tp->xstats.rx_lost_in_ring++;
1836 } 1835 }
@@ -1890,7 +1889,7 @@ static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1890} 1889}
1891 1890
1892#if RX_BUF_IDX == 3 1891#if RX_BUF_IDX == 3
1893static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring, 1892static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1894 u32 offset, unsigned int size) 1893 u32 offset, unsigned int size)
1895{ 1894{
1896 u32 left = RX_BUF_LEN - offset; 1895 u32 left = RX_BUF_LEN - offset;
@@ -1913,9 +1912,9 @@ static void rtl8139_isr_ack(struct rtl8139_private *tp)
1913 /* Clear out errors and receive interrupts */ 1912 /* Clear out errors and receive interrupts */
1914 if (likely(status != 0)) { 1913 if (likely(status != 0)) {
1915 if (unlikely(status & (RxFIFOOver | RxOverflow))) { 1914 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1916 tp->stats.rx_errors++; 1915 tp->dev->stats.rx_errors++;
1917 if (status & RxFIFOOver) 1916 if (status & RxFIFOOver)
1918 tp->stats.rx_fifo_errors++; 1917 tp->dev->stats.rx_fifo_errors++;
1919 } 1918 }
1920 RTL_W16_F (IntrStatus, RxAckBits); 1919 RTL_W16_F (IntrStatus, RxAckBits);
1921 } 1920 }
@@ -2016,8 +2015,8 @@ no_early_rx:
2016 skb->protocol = eth_type_trans (skb, dev); 2015 skb->protocol = eth_type_trans (skb, dev);
2017 2016
2018 dev->last_rx = jiffies; 2017 dev->last_rx = jiffies;
2019 tp->stats.rx_bytes += pkt_size; 2018 dev->stats.rx_bytes += pkt_size;
2020 tp->stats.rx_packets++; 2019 dev->stats.rx_packets++;
2021 2020
2022 netif_receive_skb (skb); 2021 netif_receive_skb (skb);
2023 } else { 2022 } else {
@@ -2025,7 +2024,7 @@ no_early_rx:
2025 printk (KERN_WARNING 2024 printk (KERN_WARNING
2026 "%s: Memory squeeze, dropping packet.\n", 2025 "%s: Memory squeeze, dropping packet.\n",
2027 dev->name); 2026 dev->name);
2028 tp->stats.rx_dropped++; 2027 dev->stats.rx_dropped++;
2029 } 2028 }
2030 received++; 2029 received++;
2031 2030
@@ -2072,7 +2071,7 @@ static void rtl8139_weird_interrupt (struct net_device *dev,
2072 assert (ioaddr != NULL); 2071 assert (ioaddr != NULL);
2073 2072
2074 /* Update the error count. */ 2073 /* Update the error count. */
2075 tp->stats.rx_missed_errors += RTL_R32 (RxMissed); 2074 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2076 RTL_W32 (RxMissed, 0); 2075 RTL_W32 (RxMissed, 0);
2077 2076
2078 if ((status & RxUnderrun) && link_changed && 2077 if ((status & RxUnderrun) && link_changed &&
@@ -2082,12 +2081,12 @@ static void rtl8139_weird_interrupt (struct net_device *dev,
2082 } 2081 }
2083 2082
2084 if (status & (RxUnderrun | RxErr)) 2083 if (status & (RxUnderrun | RxErr))
2085 tp->stats.rx_errors++; 2084 dev->stats.rx_errors++;
2086 2085
2087 if (status & PCSTimeout) 2086 if (status & PCSTimeout)
2088 tp->stats.rx_length_errors++; 2087 dev->stats.rx_length_errors++;
2089 if (status & RxUnderrun) 2088 if (status & RxUnderrun)
2090 tp->stats.rx_fifo_errors++; 2089 dev->stats.rx_fifo_errors++;
2091 if (status & PCIErr) { 2090 if (status & PCIErr) {
2092 u16 pci_cmd_status; 2091 u16 pci_cmd_status;
2093 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status); 2092 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
@@ -2227,12 +2226,11 @@ static int rtl8139_close (struct net_device *dev)
2227 RTL_W16 (IntrMask, 0); 2226 RTL_W16 (IntrMask, 0);
2228 2227
2229 /* Update the error counts. */ 2228 /* Update the error counts. */
2230 tp->stats.rx_missed_errors += RTL_R32 (RxMissed); 2229 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2231 RTL_W32 (RxMissed, 0); 2230 RTL_W32 (RxMissed, 0);
2232 2231
2233 spin_unlock_irqrestore (&tp->lock, flags); 2232 spin_unlock_irqrestore (&tp->lock, flags);
2234 2233
2235 synchronize_irq (dev->irq); /* racy, but that's ok here */
2236 free_irq (dev->irq, dev); 2234 free_irq (dev->irq, dev);
2237 2235
2238 rtl8139_tx_clear (tp); 2236 rtl8139_tx_clear (tp);
@@ -2472,12 +2470,12 @@ static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2472 2470
2473 if (netif_running(dev)) { 2471 if (netif_running(dev)) {
2474 spin_lock_irqsave (&tp->lock, flags); 2472 spin_lock_irqsave (&tp->lock, flags);
2475 tp->stats.rx_missed_errors += RTL_R32 (RxMissed); 2473 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2476 RTL_W32 (RxMissed, 0); 2474 RTL_W32 (RxMissed, 0);
2477 spin_unlock_irqrestore (&tp->lock, flags); 2475 spin_unlock_irqrestore (&tp->lock, flags);
2478 } 2476 }
2479 2477
2480 return &tp->stats; 2478 return &dev->stats;
2481} 2479}
2482 2480
2483/* Set or clear the multicast filter for this adaptor. 2481/* Set or clear the multicast filter for this adaptor.
@@ -2561,7 +2559,7 @@ static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2561 RTL_W8 (ChipCmd, 0); 2559 RTL_W8 (ChipCmd, 0);
2562 2560
2563 /* Update the error counts. */ 2561 /* Update the error counts. */
2564 tp->stats.rx_missed_errors += RTL_R32 (RxMissed); 2562 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2565 RTL_W32 (RxMissed, 0); 2563 RTL_W32 (RxMissed, 0);
2566 2564
2567 spin_unlock_irqrestore (&tp->lock, flags); 2565 spin_unlock_irqrestore (&tp->lock, flags);
diff --git a/drivers/net/8390.h b/drivers/net/8390.h
index 04ddec0f4c61..8e209f5e7c11 100644
--- a/drivers/net/8390.h
+++ b/drivers/net/8390.h
@@ -30,8 +30,10 @@ extern int ei_debug;
30 30
31#ifdef CONFIG_NET_POLL_CONTROLLER 31#ifdef CONFIG_NET_POLL_CONTROLLER
32extern void ei_poll(struct net_device *dev); 32extern void ei_poll(struct net_device *dev);
33extern void eip_poll(struct net_device *dev);
33#endif 34#endif
34 35
36/* Without I/O delay - non ISA or later chips */
35extern void NS8390_init(struct net_device *dev, int startp); 37extern void NS8390_init(struct net_device *dev, int startp);
36extern int ei_open(struct net_device *dev); 38extern int ei_open(struct net_device *dev);
37extern int ei_close(struct net_device *dev); 39extern int ei_close(struct net_device *dev);
@@ -42,6 +44,17 @@ static inline struct net_device *alloc_ei_netdev(void)
42 return __alloc_ei_netdev(0); 44 return __alloc_ei_netdev(0);
43} 45}
44 46
47/* With I/O delay form */
48extern void NS8390p_init(struct net_device *dev, int startp);
49extern int eip_open(struct net_device *dev);
50extern int eip_close(struct net_device *dev);
51extern irqreturn_t eip_interrupt(int irq, void *dev_id);
52extern struct net_device *__alloc_eip_netdev(int size);
53static inline struct net_device *alloc_eip_netdev(void)
54{
55 return __alloc_eip_netdev(0);
56}
57
45/* You have one of these per-board */ 58/* You have one of these per-board */
46struct ei_device { 59struct ei_device {
47 const char *name; 60 const char *name;
@@ -69,7 +82,6 @@ struct ei_device {
69 unsigned char reg0; /* Register '0' in a WD8013 */ 82 unsigned char reg0; /* Register '0' in a WD8013 */
70 unsigned char reg5; /* Register '5' in a WD8013 */ 83 unsigned char reg5; /* Register '5' in a WD8013 */
71 unsigned char saved_irq; /* Original dev->irq value. */ 84 unsigned char saved_irq; /* Original dev->irq value. */
72 struct net_device_stats stat; /* The new statistics table. */
73 u32 *reg_offset; /* Register mapping table */ 85 u32 *reg_offset; /* Register mapping table */
74 spinlock_t page_lock; /* Page register locks */ 86 spinlock_t page_lock; /* Page register locks */
75 unsigned long priv; /* Private field to store bus IDs etc. */ 87 unsigned long priv; /* Private field to store bus IDs etc. */
@@ -116,13 +128,14 @@ struct ei_device {
116/* 128/*
117 * Only generate indirect loads given a machine that needs them. 129 * Only generate indirect loads given a machine that needs them.
118 * - removed AMIGA_PCMCIA from this list, handled as ISA io now 130 * - removed AMIGA_PCMCIA from this list, handled as ISA io now
131 * - the _p for generates no delay by default 8390p.c overrides this.
119 */ 132 */
120 133
121#ifndef ei_inb 134#ifndef ei_inb
122#define ei_inb(_p) inb(_p) 135#define ei_inb(_p) inb(_p)
123#define ei_outb(_v,_p) outb(_v,_p) 136#define ei_outb(_v,_p) outb(_v,_p)
124#define ei_inb_p(_p) inb_p(_p) 137#define ei_inb_p(_p) inb(_p)
125#define ei_outb_p(_v,_p) outb_p(_v,_p) 138#define ei_outb_p(_v,_p) outb(_v,_p)
126#endif 139#endif
127 140
128#ifndef EI_SHIFT 141#ifndef EI_SHIFT
diff --git a/drivers/net/8390p.c b/drivers/net/8390p.c
new file mode 100644
index 000000000000..71f19884c4b1
--- /dev/null
+++ b/drivers/net/8390p.c
@@ -0,0 +1,66 @@
1/* 8390 core for ISA devices needing bus delays */
2
3static const char version[] =
4 "8390p.c:v1.10cvs 9/23/94 Donald Becker (becker@cesdis.gsfc.nasa.gov)\n";
5
6#define ei_inb(_p) inb(_p)
7#define ei_outb(_v,_p) outb(_v,_p)
8#define ei_inb_p(_p) inb_p(_p)
9#define ei_outb_p(_v,_p) outb_p(_v,_p)
10
11#include "lib8390.c"
12
13int eip_open(struct net_device *dev)
14{
15 return __ei_open(dev);
16}
17
18int eip_close(struct net_device *dev)
19{
20 return __ei_close(dev);
21}
22
23irqreturn_t eip_interrupt(int irq, void *dev_id)
24{
25 return __ei_interrupt(irq, dev_id);
26}
27
28#ifdef CONFIG_NET_POLL_CONTROLLER
29void eip_poll(struct net_device *dev)
30{
31 __ei_poll(dev);
32}
33#endif
34
35struct net_device *__alloc_eip_netdev(int size)
36{
37 return ____alloc_ei_netdev(size);
38}
39
40void NS8390p_init(struct net_device *dev, int startp)
41{
42 return __NS8390_init(dev, startp);
43}
44
45EXPORT_SYMBOL(eip_open);
46EXPORT_SYMBOL(eip_close);
47EXPORT_SYMBOL(eip_interrupt);
48#ifdef CONFIG_NET_POLL_CONTROLLER
49EXPORT_SYMBOL(eip_poll);
50#endif
51EXPORT_SYMBOL(NS8390p_init);
52EXPORT_SYMBOL(__alloc_eip_netdev);
53
54#if defined(MODULE)
55
56int init_module(void)
57{
58 return 0;
59}
60
61void cleanup_module(void)
62{
63}
64
65#endif /* MODULE */
66MODULE_LICENSE("GPL");
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9940ca325837..3e5e64c33e18 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -26,14 +26,6 @@ menuconfig NETDEVICES
26# that for each of the symbols. 26# that for each of the symbols.
27if NETDEVICES 27if NETDEVICES
28 28
29config NETDEVICES_MULTIQUEUE
30 bool "Netdevice multiple hardware queue support"
31 ---help---
32 Say Y here if you want to allow the network stack to use multiple
33 hardware TX queues on an ethernet device.
34
35 Most people will say N here.
36
37config IFB 29config IFB
38 tristate "Intermediate Functional Block support" 30 tristate "Intermediate Functional Block support"
39 depends on NET_CLS_ACT 31 depends on NET_CLS_ACT
@@ -515,6 +507,18 @@ config STNIC
515 507
516 If unsure, say N. 508 If unsure, say N.
517 509
510config SH_ETH
511 tristate "Renesas SuperH Ethernet support"
512 depends on SUPERH && \
513 (CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712)
514 select CRC32
515 select MII
516 select MDIO_BITBANG
517 select PHYLIB
518 help
519 Renesas SuperH Ethernet device driver.
520 This driver support SH7710 and SH7712.
521
518config SUNLANCE 522config SUNLANCE
519 tristate "Sun LANCE support" 523 tristate "Sun LANCE support"
520 depends on SBUS 524 depends on SBUS
@@ -917,6 +921,23 @@ config DM9000
917 To compile this driver as a module, choose M here. The module 921 To compile this driver as a module, choose M here. The module
918 will be called dm9000. 922 will be called dm9000.
919 923
924config DM9000_DEBUGLEVEL
925 int "DM9000 maximum debug level"
926 depends on DM9000
927 default 4
928 help
929 The maximum level of debugging code compiled into the DM9000
930 driver.
931
932config DM9000_FORCE_SIMPLE_PHY_POLL
933 bool "Force simple NSR based PHY polling"
934 depends on DM9000
935 ---help---
936 This configuration forces the DM9000 to use the NSR's LinkStatus
937 bit to determine if the link is up or down instead of the more
938 costly MII PHY reads. Note, this will not work if the chip is
939 operating with an external PHY.
940
920config ENC28J60 941config ENC28J60
921 tristate "ENC28J60 support" 942 tristate "ENC28J60 support"
922 depends on EXPERIMENTAL && SPI && NET_ETHERNET 943 depends on EXPERIMENTAL && SPI && NET_ETHERNET
@@ -934,19 +955,11 @@ config ENC28J60_WRITEVERIFY
934 Enable the verify after the buffer write useful for debugging purpose. 955 Enable the verify after the buffer write useful for debugging purpose.
935 If unsure, say N. 956 If unsure, say N.
936 957
937config DM9000_DEBUGLEVEL
938 int "DM9000 maximum debug level"
939 depends on DM9000
940 default 4
941 help
942 The maximum level of debugging code compiled into the DM9000
943 driver.
944
945config SMC911X 958config SMC911X
946 tristate "SMSC LAN911[5678] support" 959 tristate "SMSC LAN911[5678] support"
947 select CRC32 960 select CRC32
948 select MII 961 select MII
949 depends on ARCH_PXA || SH_MAGIC_PANEL_R2 962 depends on ARCH_PXA || SUPERH
950 help 963 help
951 This is a driver for SMSC's LAN911x series of Ethernet chipsets 964 This is a driver for SMSC's LAN911x series of Ethernet chipsets
952 including the new LAN9115, LAN9116, LAN9117, and LAN9118. 965 including the new LAN9115, LAN9116, LAN9117, and LAN9118.
@@ -1234,7 +1247,6 @@ config IBMVETH
1234 To compile this driver as a module, choose M here. The module will 1247 To compile this driver as a module, choose M here. The module will
1235 be called ibmveth. 1248 be called ibmveth.
1236 1249
1237source "drivers/net/ibm_emac/Kconfig"
1238source "drivers/net/ibm_newemac/Kconfig" 1250source "drivers/net/ibm_newemac/Kconfig"
1239 1251
1240config NET_PCI 1252config NET_PCI
@@ -1277,20 +1289,6 @@ config AMD8111_ETH
1277 To compile this driver as a module, choose M here. The module 1289 To compile this driver as a module, choose M here. The module
1278 will be called amd8111e. 1290 will be called amd8111e.
1279 1291
1280config AMD8111E_NAPI
1281 bool "Use RX polling (NAPI)"
1282 depends on AMD8111_ETH
1283 help
1284 NAPI is a new driver API designed to reduce CPU and interrupt load
1285 when the driver is receiving lots of packets from the card. It is
1286 still somewhat experimental and thus not yet enabled by default.
1287
1288 If your estimated Rx load is 10kpps or more, or if the card will be
1289 deployed on potentially unfriendly networks (e.g. in a firewall),
1290 then say Y here.
1291
1292 If in doubt, say N.
1293
1294config ADAPTEC_STARFIRE 1292config ADAPTEC_STARFIRE
1295 tristate "Adaptec Starfire/DuraLAN support" 1293 tristate "Adaptec Starfire/DuraLAN support"
1296 depends on NET_PCI && PCI 1294 depends on NET_PCI && PCI
@@ -1305,20 +1303,6 @@ config ADAPTEC_STARFIRE
1305 To compile this driver as a module, choose M here: the module 1303 To compile this driver as a module, choose M here: the module
1306 will be called starfire. This is recommended. 1304 will be called starfire. This is recommended.
1307 1305
1308config ADAPTEC_STARFIRE_NAPI
1309 bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
1310 depends on ADAPTEC_STARFIRE && EXPERIMENTAL
1311 help
1312 NAPI is a new driver API designed to reduce CPU and interrupt load
1313 when the driver is receiving lots of packets from the card. It is
1314 still somewhat experimental and thus not yet enabled by default.
1315
1316 If your estimated Rx load is 10kpps or more, or if the card will be
1317 deployed on potentially unfriendly networks (e.g. in a firewall),
1318 then say Y here.
1319
1320 If in doubt, say N.
1321
1322config AC3200 1306config AC3200
1323 tristate "Ansel Communications EISA 3200 support (EXPERIMENTAL)" 1307 tristate "Ansel Communications EISA 3200 support (EXPERIMENTAL)"
1324 depends on NET_PCI && (ISA || EISA) && EXPERIMENTAL 1308 depends on NET_PCI && (ISA || EISA) && EXPERIMENTAL
@@ -1661,7 +1645,7 @@ config SUNDANCE_MMIO
1661 1645
1662config TLAN 1646config TLAN
1663 tristate "TI ThunderLAN support" 1647 tristate "TI ThunderLAN support"
1664 depends on NET_PCI && (PCI || EISA) && !64BIT 1648 depends on NET_PCI && (PCI || EISA)
1665 ---help--- 1649 ---help---
1666 If you have a PCI Ethernet network card based on the ThunderLAN chip 1650 If you have a PCI Ethernet network card based on the ThunderLAN chip
1667 which is supported by this driver, say Y and read the 1651 which is supported by this driver, say Y and read the
@@ -1701,26 +1685,6 @@ config VIA_RHINE_MMIO
1701 1685
1702 If unsure, say Y. 1686 If unsure, say Y.
1703 1687
1704config VIA_RHINE_NAPI
1705 bool "Use Rx Polling (NAPI)"
1706 depends on VIA_RHINE
1707 help
1708 NAPI is a new driver API designed to reduce CPU and interrupt load
1709 when the driver is receiving lots of packets from the card.
1710
1711 If your estimated Rx load is 10kpps or more, or if the card will be
1712 deployed on potentially unfriendly networks (e.g. in a firewall),
1713 then say Y here.
1714
1715config LAN_SAA9730
1716 bool "Philips SAA9730 Ethernet support"
1717 depends on NET_PCI && PCI && MIPS_ATLAS
1718 help
1719 The SAA9730 is a combined multimedia and peripheral controller used
1720 in thin clients, Internet access terminals, and diskless
1721 workstations.
1722 See <http://www.semiconductors.philips.com/pip/SAA9730_flyer_1>.
1723
1724config SC92031 1688config SC92031
1725 tristate "Silan SC92031 PCI Fast Ethernet Adapter driver (EXPERIMENTAL)" 1689 tristate "Silan SC92031 PCI Fast Ethernet Adapter driver (EXPERIMENTAL)"
1726 depends on NET_PCI && PCI && EXPERIMENTAL 1690 depends on NET_PCI && PCI && EXPERIMENTAL
@@ -2004,9 +1968,6 @@ config E1000E
2004 To compile this driver as a module, choose M here. The module 1968 To compile this driver as a module, choose M here. The module
2005 will be called e1000e. 1969 will be called e1000e.
2006 1970
2007config E1000E_ENABLED
2008 def_bool E1000E != n
2009
2010config IP1000 1971config IP1000
2011 tristate "IP1000 Gigabit Ethernet support" 1972 tristate "IP1000 Gigabit Ethernet support"
2012 depends on PCI && EXPERIMENTAL 1973 depends on PCI && EXPERIMENTAL
@@ -2038,6 +1999,15 @@ config IGB
2038 To compile this driver as a module, choose M here. The module 1999 To compile this driver as a module, choose M here. The module
2039 will be called igb. 2000 will be called igb.
2040 2001
2002config IGB_LRO
2003 bool "Use software LRO"
2004 depends on IGB && INET
2005 select INET_LRO
2006 ---help---
2007 Say Y here if you want to use large receive offload.
2008
2009 If in doubt, say N.
2010
2041source "drivers/net/ixp2000/Kconfig" 2011source "drivers/net/ixp2000/Kconfig"
2042 2012
2043config MYRI_SBUS 2013config MYRI_SBUS
@@ -2095,27 +2065,13 @@ config R8169
2095 To compile this driver as a module, choose M here: the module 2065 To compile this driver as a module, choose M here: the module
2096 will be called r8169. This is recommended. 2066 will be called r8169. This is recommended.
2097 2067
2098config R8169_NAPI
2099 bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
2100 depends on R8169 && EXPERIMENTAL
2101 help
2102 NAPI is a new driver API designed to reduce CPU and interrupt load
2103 when the driver is receiving lots of packets from the card. It is
2104 still somewhat experimental and thus not yet enabled by default.
2105
2106 If your estimated Rx load is 10kpps or more, or if the card will be
2107 deployed on potentially unfriendly networks (e.g. in a firewall),
2108 then say Y here.
2109
2110 If in doubt, say N.
2111
2112config R8169_VLAN 2068config R8169_VLAN
2113 bool "VLAN support" 2069 bool "VLAN support"
2114 depends on R8169 && VLAN_8021Q 2070 depends on R8169 && VLAN_8021Q
2115 ---help--- 2071 ---help---
2116 Say Y here for the r8169 driver to support the functions required 2072 Say Y here for the r8169 driver to support the functions required
2117 by the kernel 802.1Q code. 2073 by the kernel 802.1Q code.
2118 2074
2119 If in doubt, say Y. 2075 If in doubt, say Y.
2120 2076
2121config SB1250_MAC 2077config SB1250_MAC
@@ -2218,6 +2174,7 @@ config VIA_VELOCITY
2218config TIGON3 2174config TIGON3
2219 tristate "Broadcom Tigon3 support" 2175 tristate "Broadcom Tigon3 support"
2220 depends on PCI 2176 depends on PCI
2177 select PHYLIB
2221 help 2178 help
2222 This driver supports Broadcom Tigon3 based gigabit Ethernet cards. 2179 This driver supports Broadcom Tigon3 based gigabit Ethernet cards.
2223 2180
@@ -2273,6 +2230,19 @@ config GELIC_WIRELESS
2273 the driver automatically distinguishes the models, you can 2230 the driver automatically distinguishes the models, you can
2274 safely enable this option even if you have a wireless-less model. 2231 safely enable this option even if you have a wireless-less model.
2275 2232
2233config GELIC_WIRELESS_OLD_PSK_INTERFACE
2234 bool "PS3 Wireless private PSK interface (OBSOLETE)"
2235 depends on GELIC_WIRELESS
2236 help
2237 This option retains the obsolete private interface to pass
2238 the PSK from user space programs to the driver. The PSK
2239 stands for 'Pre Shared Key' and is used for WPA[2]-PSK
2240 (WPA-Personal) environment.
2241 If WPA[2]-PSK is used and you need to use old programs that
2242 support only this old interface, say Y. Otherwise N.
2243
2244 If unsure, say N.
2245
2276config GIANFAR 2246config GIANFAR
2277 tristate "Gianfar Ethernet" 2247 tristate "Gianfar Ethernet"
2278 depends on FSL_SOC 2248 depends on FSL_SOC
@@ -2282,10 +2252,6 @@ config GIANFAR
2282 This driver supports the Gigabit TSEC on the MPC83xx, MPC85xx, 2252 This driver supports the Gigabit TSEC on the MPC83xx, MPC85xx,
2283 and MPC86xx family of chips, and the FEC on the 8540. 2253 and MPC86xx family of chips, and the FEC on the 8540.
2284 2254
2285config GFAR_NAPI
2286 bool "Use Rx Polling (NAPI)"
2287 depends on GIANFAR
2288
2289config UCC_GETH 2255config UCC_GETH
2290 tristate "Freescale QE Gigabit Ethernet" 2256 tristate "Freescale QE Gigabit Ethernet"
2291 depends on QUICC_ENGINE 2257 depends on QUICC_ENGINE
@@ -2294,10 +2260,6 @@ config UCC_GETH
2294 This driver supports the Gigabit Ethernet mode of the QUICC Engine, 2260 This driver supports the Gigabit Ethernet mode of the QUICC Engine,
2295 which is available on some Freescale SOCs. 2261 which is available on some Freescale SOCs.
2296 2262
2297config UGETH_NAPI
2298 bool "Use Rx Polling (NAPI)"
2299 depends on UCC_GETH
2300
2301config UGETH_MAGIC_PACKET 2263config UGETH_MAGIC_PACKET
2302 bool "Magic Packet detection support" 2264 bool "Magic Packet detection support"
2303 depends on UCC_GETH 2265 depends on UCC_GETH
@@ -2387,18 +2349,11 @@ config CHELSIO_T1_1G
2387 Enables support for Chelsio's gigabit Ethernet PCI cards. If you 2349 Enables support for Chelsio's gigabit Ethernet PCI cards. If you
2388 are using only 10G cards say 'N' here. 2350 are using only 10G cards say 'N' here.
2389 2351
2390config CHELSIO_T1_NAPI
2391 bool "Use Rx Polling (NAPI)"
2392 depends on CHELSIO_T1
2393 default y
2394 help
2395 NAPI is a driver API designed to reduce CPU and interrupt load
2396 when the driver is receiving lots of packets from the card.
2397
2398config CHELSIO_T3 2352config CHELSIO_T3
2399 tristate "Chelsio Communications T3 10Gb Ethernet support" 2353 tristate "Chelsio Communications T3 10Gb Ethernet support"
2400 depends on PCI 2354 depends on PCI && INET
2401 select FW_LOADER 2355 select FW_LOADER
2356 select INET_LRO
2402 help 2357 help
2403 This driver supports Chelsio T3-based gigabit and 10Gb Ethernet 2358 This driver supports Chelsio T3-based gigabit and 10Gb Ethernet
2404 adapters. 2359 adapters.
@@ -2426,7 +2381,8 @@ config EHEA
2426 2381
2427config IXGBE 2382config IXGBE
2428 tristate "Intel(R) 10GbE PCI Express adapters support" 2383 tristate "Intel(R) 10GbE PCI Express adapters support"
2429 depends on PCI 2384 depends on PCI && INET
2385 select INET_LRO
2430 ---help--- 2386 ---help---
2431 This driver supports Intel(R) 10GbE PCI Express family of 2387 This driver supports Intel(R) 10GbE PCI Express family of
2432 adapters. For more information on how to identify your adapter, go 2388 adapters. For more information on how to identify your adapter, go
@@ -2464,20 +2420,6 @@ config IXGB
2464 To compile this driver as a module, choose M here. The module 2420 To compile this driver as a module, choose M here. The module
2465 will be called ixgb. 2421 will be called ixgb.
2466 2422
2467config IXGB_NAPI
2468 bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
2469 depends on IXGB && EXPERIMENTAL
2470 help
2471 NAPI is a new driver API designed to reduce CPU and interrupt load
2472 when the driver is receiving lots of packets from the card. It is
2473 still somewhat experimental and thus not yet enabled by default.
2474
2475 If your estimated Rx load is 10kpps or more, or if the card will be
2476 deployed on potentially unfriendly networks (e.g. in a firewall),
2477 then say Y here.
2478
2479 If in doubt, say N.
2480
2481config S2IO 2423config S2IO
2482 tristate "S2IO 10Gbe XFrame NIC" 2424 tristate "S2IO 10Gbe XFrame NIC"
2483 depends on PCI 2425 depends on PCI
@@ -2486,20 +2428,6 @@ config S2IO
2486 More specific information on configuring the driver is in 2428 More specific information on configuring the driver is in
2487 <file:Documentation/networking/s2io.txt>. 2429 <file:Documentation/networking/s2io.txt>.
2488 2430
2489config S2IO_NAPI
2490 bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
2491 depends on S2IO && EXPERIMENTAL
2492 help
2493 NAPI is a new driver API designed to reduce CPU and interrupt load
2494 when the driver is receiving lots of packets from the card. It is
2495 still somewhat experimental and thus not yet enabled by default.
2496
2497 If your estimated Rx load is 10kpps or more, or if the card will be
2498 deployed on potentially unfriendly networks (e.g. in a firewall),
2499 then say Y here.
2500
2501 If in doubt, say N.
2502
2503config MYRI10GE 2431config MYRI10GE
2504 tristate "Myricom Myri-10G Ethernet support" 2432 tristate "Myricom Myri-10G Ethernet support"
2505 depends on PCI && INET 2433 depends on PCI && INET
@@ -2564,6 +2492,7 @@ config BNX2X
2564 tristate "Broadcom NetXtremeII 10Gb support" 2492 tristate "Broadcom NetXtremeII 10Gb support"
2565 depends on PCI 2493 depends on PCI
2566 select ZLIB_INFLATE 2494 select ZLIB_INFLATE
2495 select LIBCRC32C
2567 help 2496 help
2568 This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards. 2497 This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards.
2569 To compile this driver as a module, choose M here: the module 2498 To compile this driver as a module, choose M here: the module
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 9010e58da0f2..4b17a9ab7861 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -4,7 +4,6 @@
4 4
5obj-$(CONFIG_E1000) += e1000/ 5obj-$(CONFIG_E1000) += e1000/
6obj-$(CONFIG_E1000E) += e1000e/ 6obj-$(CONFIG_E1000E) += e1000e/
7obj-$(CONFIG_IBM_EMAC) += ibm_emac/
8obj-$(CONFIG_IBM_NEW_EMAC) += ibm_newemac/ 7obj-$(CONFIG_IBM_NEW_EMAC) += ibm_newemac/
9obj-$(CONFIG_IGB) += igb/ 8obj-$(CONFIG_IGB) += igb/
10obj-$(CONFIG_IXGBE) += ixgbe/ 9obj-$(CONFIG_IXGBE) += ixgbe/
@@ -67,6 +66,7 @@ obj-$(CONFIG_FEALNX) += fealnx.o
67obj-$(CONFIG_TIGON3) += tg3.o 66obj-$(CONFIG_TIGON3) += tg3.o
68obj-$(CONFIG_BNX2) += bnx2.o 67obj-$(CONFIG_BNX2) += bnx2.o
69obj-$(CONFIG_BNX2X) += bnx2x.o 68obj-$(CONFIG_BNX2X) += bnx2x.o
69bnx2x-objs := bnx2x_main.o bnx2x_link.o
70spidernet-y += spider_net.o spider_net_ethtool.o 70spidernet-y += spider_net.o spider_net_ethtool.o
71obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o 71obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o
72obj-$(CONFIG_GELIC_NET) += ps3_gelic.o 72obj-$(CONFIG_GELIC_NET) += ps3_gelic.o
@@ -80,6 +80,7 @@ obj-$(CONFIG_VIA_RHINE) += via-rhine.o
80obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o 80obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o
81obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o 81obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o
82obj-$(CONFIG_RIONET) += rionet.o 82obj-$(CONFIG_RIONET) += rionet.o
83obj-$(CONFIG_SH_ETH) += sh_eth.o
83 84
84# 85#
85# end link order section 86# end link order section
@@ -105,11 +106,11 @@ ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y)
105endif 106endif
106obj-$(CONFIG_68360_ENET) += 68360enet.o 107obj-$(CONFIG_68360_ENET) += 68360enet.o
107obj-$(CONFIG_WD80x3) += wd.o 8390.o 108obj-$(CONFIG_WD80x3) += wd.o 8390.o
108obj-$(CONFIG_EL2) += 3c503.o 8390.o 109obj-$(CONFIG_EL2) += 3c503.o 8390p.o
109obj-$(CONFIG_NE2000) += ne.o 8390.o 110obj-$(CONFIG_NE2000) += ne.o 8390p.o
110obj-$(CONFIG_NE2_MCA) += ne2.o 8390.o 111obj-$(CONFIG_NE2_MCA) += ne2.o 8390p.o
111obj-$(CONFIG_HPLAN) += hp.o 8390.o 112obj-$(CONFIG_HPLAN) += hp.o 8390p.o
112obj-$(CONFIG_HPLAN_PLUS) += hp-plus.o 8390.o 113obj-$(CONFIG_HPLAN_PLUS) += hp-plus.o 8390p.o
113obj-$(CONFIG_ULTRA) += smc-ultra.o 8390.o 114obj-$(CONFIG_ULTRA) += smc-ultra.o 8390.o
114obj-$(CONFIG_ULTRAMCA) += smc-mca.o 8390.o 115obj-$(CONFIG_ULTRAMCA) += smc-mca.o 8390.o
115obj-$(CONFIG_ULTRA32) += smc-ultra32.o 8390.o 116obj-$(CONFIG_ULTRA32) += smc-ultra32.o 8390.o
@@ -165,7 +166,6 @@ obj-$(CONFIG_EEXPRESS_PRO) += eepro.o
165obj-$(CONFIG_8139CP) += 8139cp.o 166obj-$(CONFIG_8139CP) += 8139cp.o
166obj-$(CONFIG_8139TOO) += 8139too.o 167obj-$(CONFIG_8139TOO) += 8139too.o
167obj-$(CONFIG_ZNET) += znet.o 168obj-$(CONFIG_ZNET) += znet.o
168obj-$(CONFIG_LAN_SAA9730) += saa9730.o
169obj-$(CONFIG_CPMAC) += cpmac.o 169obj-$(CONFIG_CPMAC) += cpmac.o
170obj-$(CONFIG_DEPCA) += depca.o 170obj-$(CONFIG_DEPCA) += depca.o
171obj-$(CONFIG_EWRK3) += ewrk3.o 171obj-$(CONFIG_EWRK3) += ewrk3.o
@@ -235,6 +235,7 @@ obj-$(CONFIG_USB_CATC) += usb/
235obj-$(CONFIG_USB_KAWETH) += usb/ 235obj-$(CONFIG_USB_KAWETH) += usb/
236obj-$(CONFIG_USB_PEGASUS) += usb/ 236obj-$(CONFIG_USB_PEGASUS) += usb/
237obj-$(CONFIG_USB_RTL8150) += usb/ 237obj-$(CONFIG_USB_RTL8150) += usb/
238obj-$(CONFIG_USB_HSO) += usb/
238obj-$(CONFIG_USB_USBNET) += usb/ 239obj-$(CONFIG_USB_USBNET) += usb/
239obj-$(CONFIG_USB_ZD1201) += usb/ 240obj-$(CONFIG_USB_ZD1201) += usb/
240 241
diff --git a/drivers/net/a2065.c b/drivers/net/a2065.c
index 6c5719ae8cca..9c0837435b68 100644
--- a/drivers/net/a2065.c
+++ b/drivers/net/a2065.c
@@ -475,16 +475,12 @@ static irqreturn_t lance_interrupt (int irq, void *dev_id)
475 return IRQ_HANDLED; 475 return IRQ_HANDLED;
476} 476}
477 477
478struct net_device *last_dev;
479
480static int lance_open (struct net_device *dev) 478static int lance_open (struct net_device *dev)
481{ 479{
482 struct lance_private *lp = netdev_priv(dev); 480 struct lance_private *lp = netdev_priv(dev);
483 volatile struct lance_regs *ll = lp->ll; 481 volatile struct lance_regs *ll = lp->ll;
484 int ret; 482 int ret;
485 483
486 last_dev = dev;
487
488 /* Stop the Lance */ 484 /* Stop the Lance */
489 ll->rap = LE_CSR0; 485 ll->rap = LE_CSR0;
490 ll->rdp = LE_C0_STOP; 486 ll->rdp = LE_C0_STOP;
diff --git a/drivers/net/acenic.c b/drivers/net/acenic.c
index 6c192650d349..e4483de84e7f 100644
--- a/drivers/net/acenic.c
+++ b/drivers/net/acenic.c
@@ -1457,11 +1457,6 @@ static int __devinit ace_init(struct net_device *dev)
1457 ace_set_txprd(regs, ap, 0); 1457 ace_set_txprd(regs, ap, 0);
1458 writel(0, &regs->RxRetCsm); 1458 writel(0, &regs->RxRetCsm);
1459 1459
1460 /*
1461 * Zero the stats before starting the interface
1462 */
1463 memset(&ap->stats, 0, sizeof(ap->stats));
1464
1465 /* 1460 /*
1466 * Enable DMA engine now. 1461 * Enable DMA engine now.
1467 * If we do this sooner, Mckinley box pukes. 1462 * If we do this sooner, Mckinley box pukes.
@@ -2041,8 +2036,8 @@ static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
2041 netif_rx(skb); 2036 netif_rx(skb);
2042 2037
2043 dev->last_rx = jiffies; 2038 dev->last_rx = jiffies;
2044 ap->stats.rx_packets++; 2039 dev->stats.rx_packets++;
2045 ap->stats.rx_bytes += retdesc->size; 2040 dev->stats.rx_bytes += retdesc->size;
2046 2041
2047 idx = (idx + 1) % RX_RETURN_RING_ENTRIES; 2042 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2048 } 2043 }
@@ -2090,8 +2085,8 @@ static inline void ace_tx_int(struct net_device *dev,
2090 } 2085 }
2091 2086
2092 if (skb) { 2087 if (skb) {
2093 ap->stats.tx_packets++; 2088 dev->stats.tx_packets++;
2094 ap->stats.tx_bytes += skb->len; 2089 dev->stats.tx_bytes += skb->len;
2095 dev_kfree_skb_irq(skb); 2090 dev_kfree_skb_irq(skb);
2096 info->skb = NULL; 2091 info->skb = NULL;
2097 } 2092 }
@@ -2863,11 +2858,11 @@ static struct net_device_stats *ace_get_stats(struct net_device *dev)
2863 struct ace_mac_stats __iomem *mac_stats = 2858 struct ace_mac_stats __iomem *mac_stats =
2864 (struct ace_mac_stats __iomem *)ap->regs->Stats; 2859 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2865 2860
2866 ap->stats.rx_missed_errors = readl(&mac_stats->drop_space); 2861 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2867 ap->stats.multicast = readl(&mac_stats->kept_mc); 2862 dev->stats.multicast = readl(&mac_stats->kept_mc);
2868 ap->stats.collisions = readl(&mac_stats->coll); 2863 dev->stats.collisions = readl(&mac_stats->coll);
2869 2864
2870 return &ap->stats; 2865 return &dev->stats;
2871} 2866}
2872 2867
2873 2868
diff --git a/drivers/net/acenic.h b/drivers/net/acenic.h
index 60ed1837fa8f..4487f32759a4 100644
--- a/drivers/net/acenic.h
+++ b/drivers/net/acenic.h
@@ -693,7 +693,6 @@ struct ace_private
693 __attribute__ ((aligned (SMP_CACHE_BYTES))); 693 __attribute__ ((aligned (SMP_CACHE_BYTES)));
694 u32 last_tx, last_std_rx, last_mini_rx; 694 u32 last_tx, last_std_rx, last_mini_rx;
695#endif 695#endif
696 struct net_device_stats stats;
697 int pci_using_dac; 696 int pci_using_dac;
698}; 697};
699 698
diff --git a/drivers/net/amd8111e.c b/drivers/net/amd8111e.c
index 85f7276aaba5..c54967f7942a 100644
--- a/drivers/net/amd8111e.c
+++ b/drivers/net/amd8111e.c
@@ -101,9 +101,9 @@ Revision History:
101 101
102#include "amd8111e.h" 102#include "amd8111e.h"
103#define MODULE_NAME "amd8111e" 103#define MODULE_NAME "amd8111e"
104#define MODULE_VERS "3.0.6" 104#define MODULE_VERS "3.0.7"
105MODULE_AUTHOR("Advanced Micro Devices, Inc."); 105MODULE_AUTHOR("Advanced Micro Devices, Inc.");
106MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version 3.0.6"); 106MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS);
107MODULE_LICENSE("GPL"); 107MODULE_LICENSE("GPL");
108MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl); 108MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
109module_param_array(speed_duplex, int, NULL, 0); 109module_param_array(speed_duplex, int, NULL, 0);
@@ -671,11 +671,7 @@ This is the receive indication function for packets with vlan tag.
671*/ 671*/
672static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag) 672static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
673{ 673{
674#ifdef CONFIG_AMD8111E_NAPI
675 return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag); 674 return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
676#else
677 return vlan_hwaccel_rx(skb, lp->vlgrp, vlan_tag);
678#endif /* CONFIG_AMD8111E_NAPI */
679} 675}
680#endif 676#endif
681 677
@@ -722,7 +718,6 @@ static int amd8111e_tx(struct net_device *dev)
722 return 0; 718 return 0;
723} 719}
724 720
725#ifdef CONFIG_AMD8111E_NAPI
726/* This function handles the driver receive operation in polling mode */ 721/* This function handles the driver receive operation in polling mode */
727static int amd8111e_rx_poll(struct napi_struct *napi, int budget) 722static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
728{ 723{
@@ -734,7 +729,6 @@ static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
734 int min_pkt_len, status; 729 int min_pkt_len, status;
735 unsigned int intr0; 730 unsigned int intr0;
736 int num_rx_pkt = 0; 731 int num_rx_pkt = 0;
737 /*int max_rx_pkt = NUM_RX_BUFFERS;*/
738 short pkt_len; 732 short pkt_len;
739#if AMD8111E_VLAN_TAG_USED 733#if AMD8111E_VLAN_TAG_USED
740 short vtag; 734 short vtag;
@@ -850,108 +844,6 @@ rx_not_empty:
850 return num_rx_pkt; 844 return num_rx_pkt;
851} 845}
852 846
853#else
854/*
855This function will check the ownership of receive buffers and descriptors. It will indicate to kernel up to half the number of maximum receive buffers in the descriptor ring, in a single receive interrupt. It will also replenish the descriptors with new skbs.
856*/
857static int amd8111e_rx(struct net_device *dev)
858{
859 struct amd8111e_priv *lp = netdev_priv(dev);
860 struct sk_buff *skb,*new_skb;
861 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
862 int min_pkt_len, status;
863 int num_rx_pkt = 0;
864 int max_rx_pkt = NUM_RX_BUFFERS;
865 short pkt_len;
866#if AMD8111E_VLAN_TAG_USED
867 short vtag;
868#endif
869
870 /* If we own the next entry, it's a new packet. Send it up. */
871 while(++num_rx_pkt <= max_rx_pkt){
872 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
873 if(status & OWN_BIT)
874 return 0;
875
876 /* check if err summary bit is set */
877 if(status & ERR_BIT){
878 /*
879 * There is a tricky error noted by John Murphy,
880 * <murf@perftech.com> to Russ Nelson: Even with full-sized
881 * buffers it's possible for a jabber packet to use two
882 * buffers, with only the last correctly noting the error. */
883 /* reseting flags */
884 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
885 goto err_next_pkt;
886 }
887 /* check for STP and ENP */
888 if(!((status & STP_BIT) && (status & ENP_BIT))){
889 /* reseting flags */
890 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
891 goto err_next_pkt;
892 }
893 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
894
895#if AMD8111E_VLAN_TAG_USED
896 vtag = status & TT_MASK;
897 /*MAC will strip vlan tag*/
898 if(lp->vlgrp != NULL && vtag !=0)
899 min_pkt_len =MIN_PKT_LEN - 4;
900 else
901#endif
902 min_pkt_len =MIN_PKT_LEN;
903
904 if (pkt_len < min_pkt_len) {
905 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
906 lp->drv_rx_errors++;
907 goto err_next_pkt;
908 }
909 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
910 /* if allocation fail,
911 ignore that pkt and go to next one */
912 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
913 lp->drv_rx_errors++;
914 goto err_next_pkt;
915 }
916
917 skb_reserve(new_skb, 2);
918 skb = lp->rx_skbuff[rx_index];
919 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
920 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
921 skb_put(skb, pkt_len);
922 lp->rx_skbuff[rx_index] = new_skb;
923 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
924 new_skb->data, lp->rx_buff_len-2,PCI_DMA_FROMDEVICE);
925
926 skb->protocol = eth_type_trans(skb, dev);
927
928#if AMD8111E_VLAN_TAG_USED
929 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
930 amd8111e_vlan_rx(lp, skb,
931 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
932 } else
933#endif
934
935 netif_rx (skb);
936 /*COAL update rx coalescing parameters*/
937 lp->coal_conf.rx_packets++;
938 lp->coal_conf.rx_bytes += pkt_len;
939
940 dev->last_rx = jiffies;
941
942err_next_pkt:
943 lp->rx_ring[rx_index].buff_phy_addr
944 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
945 lp->rx_ring[rx_index].buff_count =
946 cpu_to_le16(lp->rx_buff_len-2);
947 wmb();
948 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
949 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
950 }
951
952 return 0;
953}
954#endif /* CONFIG_AMD8111E_NAPI */
955/* 847/*
956This function will indicate the link status to the kernel. 848This function will indicate the link status to the kernel.
957*/ 849*/
@@ -1280,29 +1172,22 @@ static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1280 writel(intr0, mmio + INT0); 1172 writel(intr0, mmio + INT0);
1281 1173
1282 /* Check if Receive Interrupt has occurred. */ 1174 /* Check if Receive Interrupt has occurred. */
1283#ifdef CONFIG_AMD8111E_NAPI 1175 if (intr0 & RINT0) {
1284 if(intr0 & RINT0){ 1176 if (netif_rx_schedule_prep(dev, &lp->napi)) {
1285 if(netif_rx_schedule_prep(dev, &lp->napi)){
1286 /* Disable receive interupts */ 1177 /* Disable receive interupts */
1287 writel(RINTEN0, mmio + INTEN0); 1178 writel(RINTEN0, mmio + INTEN0);
1288 /* Schedule a polling routine */ 1179 /* Schedule a polling routine */
1289 __netif_rx_schedule(dev, &lp->napi); 1180 __netif_rx_schedule(dev, &lp->napi);
1290 } 1181 } else if (intren0 & RINTEN0) {
1291 else if (intren0 & RINTEN0) {
1292 printk("************Driver bug! \ 1182 printk("************Driver bug! \
1293 interrupt while in poll\n"); 1183 interrupt while in poll\n");
1294 /* Fix by disable receive interrupts */ 1184 /* Fix by disable receive interrupts */
1295 writel(RINTEN0, mmio + INTEN0); 1185 writel(RINTEN0, mmio + INTEN0);
1296 } 1186 }
1297 } 1187 }
1298#else 1188
1299 if(intr0 & RINT0){
1300 amd8111e_rx(dev);
1301 writel(VAL2 | RDMD0, mmio + CMD0);
1302 }
1303#endif /* CONFIG_AMD8111E_NAPI */
1304 /* Check if Transmit Interrupt has occurred. */ 1189 /* Check if Transmit Interrupt has occurred. */
1305 if(intr0 & TINT0) 1190 if (intr0 & TINT0)
1306 amd8111e_tx(dev); 1191 amd8111e_tx(dev);
1307 1192
1308 /* Check if Link Change Interrupt has occurred. */ 1193 /* Check if Link Change Interrupt has occurred. */
@@ -1340,9 +1225,7 @@ static int amd8111e_close(struct net_device * dev)
1340 struct amd8111e_priv *lp = netdev_priv(dev); 1225 struct amd8111e_priv *lp = netdev_priv(dev);
1341 netif_stop_queue(dev); 1226 netif_stop_queue(dev);
1342 1227
1343#ifdef CONFIG_AMD8111E_NAPI
1344 napi_disable(&lp->napi); 1228 napi_disable(&lp->napi);
1345#endif
1346 1229
1347 spin_lock_irq(&lp->lock); 1230 spin_lock_irq(&lp->lock);
1348 1231
@@ -1374,9 +1257,7 @@ static int amd8111e_open(struct net_device * dev )
1374 dev->name, dev)) 1257 dev->name, dev))
1375 return -EAGAIN; 1258 return -EAGAIN;
1376 1259
1377#ifdef CONFIG_AMD8111E_NAPI
1378 napi_enable(&lp->napi); 1260 napi_enable(&lp->napi);
1379#endif
1380 1261
1381 spin_lock_irq(&lp->lock); 1262 spin_lock_irq(&lp->lock);
1382 1263
@@ -1384,9 +1265,7 @@ static int amd8111e_open(struct net_device * dev )
1384 1265
1385 if(amd8111e_restart(dev)){ 1266 if(amd8111e_restart(dev)){
1386 spin_unlock_irq(&lp->lock); 1267 spin_unlock_irq(&lp->lock);
1387#ifdef CONFIG_AMD8111E_NAPI
1388 napi_disable(&lp->napi); 1268 napi_disable(&lp->napi);
1389#endif
1390 if (dev->irq) 1269 if (dev->irq)
1391 free_irq(dev->irq, dev); 1270 free_irq(dev->irq, dev);
1392 return -ENOMEM; 1271 return -ENOMEM;
@@ -2036,9 +1915,7 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
2036 dev->irq =pdev->irq; 1915 dev->irq =pdev->irq;
2037 dev->tx_timeout = amd8111e_tx_timeout; 1916 dev->tx_timeout = amd8111e_tx_timeout;
2038 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT; 1917 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
2039#ifdef CONFIG_AMD8111E_NAPI
2040 netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32); 1918 netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
2041#endif
2042#ifdef CONFIG_NET_POLL_CONTROLLER 1919#ifdef CONFIG_NET_POLL_CONTROLLER
2043 dev->poll_controller = amd8111e_poll; 1920 dev->poll_controller = amd8111e_poll;
2044#endif 1921#endif
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index c617b64c288e..9b777d9433cd 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -522,7 +522,6 @@ static int eth_poll(struct napi_struct *napi, int budget)
522#endif 522#endif
523 523
524 if ((n = queue_get_desc(rxq, port, 0)) < 0) { 524 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
525 received = 0; /* No packet received */
526#if DEBUG_RX 525#if DEBUG_RX
527 printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n", 526 printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
528 dev->name); 527 dev->name);
@@ -543,7 +542,7 @@ static int eth_poll(struct napi_struct *napi, int budget)
543 printk(KERN_DEBUG "%s: eth_poll all done\n", 542 printk(KERN_DEBUG "%s: eth_poll all done\n",
544 dev->name); 543 dev->name);
545#endif 544#endif
546 return 0; /* all work done */ 545 return received; /* all work done */
547 } 546 }
548 547
549 desc = rx_desc_ptr(port, n); 548 desc = rx_desc_ptr(port, n);
diff --git a/drivers/net/atarilance.c b/drivers/net/atarilance.c
index 4cceaac8863a..0860cc280b01 100644
--- a/drivers/net/atarilance.c
+++ b/drivers/net/atarilance.c
@@ -243,7 +243,7 @@ struct lance_private {
243 243
244/* Possible memory/IO addresses for probing */ 244/* Possible memory/IO addresses for probing */
245 245
246struct lance_addr { 246static struct lance_addr {
247 unsigned long memaddr; 247 unsigned long memaddr;
248 unsigned long ioaddr; 248 unsigned long ioaddr;
249 int slow_flag; 249 int slow_flag;
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 3c798ae5c343..3e22e7817bc3 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -1859,7 +1859,8 @@ static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
1859 1859
1860 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use); 1860 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
1861 1861
1862 skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN); 1862 skb = netdev_alloc_skb(adapter->netdev,
1863 adapter->rx_buffer_len + NET_IP_ALIGN);
1863 if (unlikely(!skb)) { 1864 if (unlikely(!skb)) {
1864 /* Better luck next round */ 1865 /* Better luck next round */
1865 adapter->net_stats.rx_dropped++; 1866 adapter->net_stats.rx_dropped++;
diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c
index 7023d77bf380..3ab61e40e86a 100644
--- a/drivers/net/au1000_eth.c
+++ b/drivers/net/au1000_eth.c
@@ -912,7 +912,7 @@ au1000_adjust_link(struct net_device *dev)
912 // link state changed 912 // link state changed
913 913
914 if (phydev->link) // link went up 914 if (phydev->link) // link went up
915 netif_schedule(dev); 915 netif_tx_schedule_all(dev);
916 else { // link went down 916 else { // link went down
917 aup->old_speed = 0; 917 aup->old_speed = 0;
918 aup->old_duplex = -1; 918 aup->old_duplex = -1;
diff --git a/drivers/net/b44.c b/drivers/net/b44.c
index 59dce6aa0865..c3bda5ce67c4 100644
--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
@@ -148,9 +148,9 @@ static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
148 unsigned long offset, 148 unsigned long offset,
149 enum dma_data_direction dir) 149 enum dma_data_direction dir)
150{ 150{
151 dma_sync_single_range_for_device(sdev->dma_dev, dma_base, 151 ssb_dma_sync_single_range_for_device(sdev, dma_base,
152 offset & dma_desc_align_mask, 152 offset & dma_desc_align_mask,
153 dma_desc_sync_size, dir); 153 dma_desc_sync_size, dir);
154} 154}
155 155
156static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev, 156static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
@@ -158,9 +158,9 @@ static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
158 unsigned long offset, 158 unsigned long offset,
159 enum dma_data_direction dir) 159 enum dma_data_direction dir)
160{ 160{
161 dma_sync_single_range_for_cpu(sdev->dma_dev, dma_base, 161 ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
162 offset & dma_desc_align_mask, 162 offset & dma_desc_align_mask,
163 dma_desc_sync_size, dir); 163 dma_desc_sync_size, dir);
164} 164}
165 165
166static inline unsigned long br32(const struct b44 *bp, unsigned long reg) 166static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
@@ -613,10 +613,10 @@ static void b44_tx(struct b44 *bp)
613 613
614 BUG_ON(skb == NULL); 614 BUG_ON(skb == NULL);
615 615
616 dma_unmap_single(bp->sdev->dma_dev, 616 ssb_dma_unmap_single(bp->sdev,
617 rp->mapping, 617 rp->mapping,
618 skb->len, 618 skb->len,
619 DMA_TO_DEVICE); 619 DMA_TO_DEVICE);
620 rp->skb = NULL; 620 rp->skb = NULL;
621 dev_kfree_skb_irq(skb); 621 dev_kfree_skb_irq(skb);
622 } 622 }
@@ -653,29 +653,29 @@ static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
653 if (skb == NULL) 653 if (skb == NULL)
654 return -ENOMEM; 654 return -ENOMEM;
655 655
656 mapping = dma_map_single(bp->sdev->dma_dev, skb->data, 656 mapping = ssb_dma_map_single(bp->sdev, skb->data,
657 RX_PKT_BUF_SZ, 657 RX_PKT_BUF_SZ,
658 DMA_FROM_DEVICE); 658 DMA_FROM_DEVICE);
659 659
660 /* Hardware bug work-around, the chip is unable to do PCI DMA 660 /* Hardware bug work-around, the chip is unable to do PCI DMA
661 to/from anything above 1GB :-( */ 661 to/from anything above 1GB :-( */
662 if (dma_mapping_error(mapping) || 662 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
663 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) { 663 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
664 /* Sigh... */ 664 /* Sigh... */
665 if (!dma_mapping_error(mapping)) 665 if (!ssb_dma_mapping_error(bp->sdev, mapping))
666 dma_unmap_single(bp->sdev->dma_dev, mapping, 666 ssb_dma_unmap_single(bp->sdev, mapping,
667 RX_PKT_BUF_SZ, DMA_FROM_DEVICE); 667 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
668 dev_kfree_skb_any(skb); 668 dev_kfree_skb_any(skb);
669 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA); 669 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
670 if (skb == NULL) 670 if (skb == NULL)
671 return -ENOMEM; 671 return -ENOMEM;
672 mapping = dma_map_single(bp->sdev->dma_dev, skb->data, 672 mapping = ssb_dma_map_single(bp->sdev, skb->data,
673 RX_PKT_BUF_SZ, 673 RX_PKT_BUF_SZ,
674 DMA_FROM_DEVICE); 674 DMA_FROM_DEVICE);
675 if (dma_mapping_error(mapping) || 675 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
676 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) { 676 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
677 if (!dma_mapping_error(mapping)) 677 if (!ssb_dma_mapping_error(bp->sdev, mapping))
678 dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE); 678 ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
679 dev_kfree_skb_any(skb); 679 dev_kfree_skb_any(skb);
680 return -ENOMEM; 680 return -ENOMEM;
681 } 681 }
@@ -750,9 +750,9 @@ static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
750 dest_idx * sizeof(dest_desc), 750 dest_idx * sizeof(dest_desc),
751 DMA_BIDIRECTIONAL); 751 DMA_BIDIRECTIONAL);
752 752
753 dma_sync_single_for_device(bp->sdev->dma_dev, le32_to_cpu(src_desc->addr), 753 ssb_dma_sync_single_for_device(bp->sdev, le32_to_cpu(src_desc->addr),
754 RX_PKT_BUF_SZ, 754 RX_PKT_BUF_SZ,
755 DMA_FROM_DEVICE); 755 DMA_FROM_DEVICE);
756} 756}
757 757
758static int b44_rx(struct b44 *bp, int budget) 758static int b44_rx(struct b44 *bp, int budget)
@@ -772,7 +772,7 @@ static int b44_rx(struct b44 *bp, int budget)
772 struct rx_header *rh; 772 struct rx_header *rh;
773 u16 len; 773 u16 len;
774 774
775 dma_sync_single_for_cpu(bp->sdev->dma_dev, map, 775 ssb_dma_sync_single_for_cpu(bp->sdev, map,
776 RX_PKT_BUF_SZ, 776 RX_PKT_BUF_SZ,
777 DMA_FROM_DEVICE); 777 DMA_FROM_DEVICE);
778 rh = (struct rx_header *) skb->data; 778 rh = (struct rx_header *) skb->data;
@@ -806,8 +806,8 @@ static int b44_rx(struct b44 *bp, int budget)
806 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod); 806 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
807 if (skb_size < 0) 807 if (skb_size < 0)
808 goto drop_it; 808 goto drop_it;
809 dma_unmap_single(bp->sdev->dma_dev, map, 809 ssb_dma_unmap_single(bp->sdev, map,
810 skb_size, DMA_FROM_DEVICE); 810 skb_size, DMA_FROM_DEVICE);
811 /* Leave out rx_header */ 811 /* Leave out rx_header */
812 skb_put(skb, len + RX_PKT_OFFSET); 812 skb_put(skb, len + RX_PKT_OFFSET);
813 skb_pull(skb, RX_PKT_OFFSET); 813 skb_pull(skb, RX_PKT_OFFSET);
@@ -966,25 +966,25 @@ static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
966 goto err_out; 966 goto err_out;
967 } 967 }
968 968
969 mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE); 969 mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
970 if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) { 970 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_30BIT_MASK) {
971 struct sk_buff *bounce_skb; 971 struct sk_buff *bounce_skb;
972 972
973 /* Chip can't handle DMA to/from >1GB, use bounce buffer */ 973 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
974 if (!dma_mapping_error(mapping)) 974 if (!ssb_dma_mapping_error(bp->sdev, mapping))
975 dma_unmap_single(bp->sdev->dma_dev, mapping, len, 975 ssb_dma_unmap_single(bp->sdev, mapping, len,
976 DMA_TO_DEVICE); 976 DMA_TO_DEVICE);
977 977
978 bounce_skb = __dev_alloc_skb(len, GFP_ATOMIC | GFP_DMA); 978 bounce_skb = __dev_alloc_skb(len, GFP_ATOMIC | GFP_DMA);
979 if (!bounce_skb) 979 if (!bounce_skb)
980 goto err_out; 980 goto err_out;
981 981
982 mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data, 982 mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
983 len, DMA_TO_DEVICE); 983 len, DMA_TO_DEVICE);
984 if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) { 984 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_30BIT_MASK) {
985 if (!dma_mapping_error(mapping)) 985 if (!ssb_dma_mapping_error(bp->sdev, mapping))
986 dma_unmap_single(bp->sdev->dma_dev, mapping, 986 ssb_dma_unmap_single(bp->sdev, mapping,
987 len, DMA_TO_DEVICE); 987 len, DMA_TO_DEVICE);
988 dev_kfree_skb_any(bounce_skb); 988 dev_kfree_skb_any(bounce_skb);
989 goto err_out; 989 goto err_out;
990 } 990 }
@@ -1082,8 +1082,8 @@ static void b44_free_rings(struct b44 *bp)
1082 1082
1083 if (rp->skb == NULL) 1083 if (rp->skb == NULL)
1084 continue; 1084 continue;
1085 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ, 1085 ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
1086 DMA_FROM_DEVICE); 1086 DMA_FROM_DEVICE);
1087 dev_kfree_skb_any(rp->skb); 1087 dev_kfree_skb_any(rp->skb);
1088 rp->skb = NULL; 1088 rp->skb = NULL;
1089 } 1089 }
@@ -1094,8 +1094,8 @@ static void b44_free_rings(struct b44 *bp)
1094 1094
1095 if (rp->skb == NULL) 1095 if (rp->skb == NULL)
1096 continue; 1096 continue;
1097 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len, 1097 ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
1098 DMA_TO_DEVICE); 1098 DMA_TO_DEVICE);
1099 dev_kfree_skb_any(rp->skb); 1099 dev_kfree_skb_any(rp->skb);
1100 rp->skb = NULL; 1100 rp->skb = NULL;
1101 } 1101 }
@@ -1117,14 +1117,14 @@ static void b44_init_rings(struct b44 *bp)
1117 memset(bp->tx_ring, 0, B44_TX_RING_BYTES); 1117 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1118 1118
1119 if (bp->flags & B44_FLAG_RX_RING_HACK) 1119 if (bp->flags & B44_FLAG_RX_RING_HACK)
1120 dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma, 1120 ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
1121 DMA_TABLE_BYTES, 1121 DMA_TABLE_BYTES,
1122 DMA_BIDIRECTIONAL); 1122 DMA_BIDIRECTIONAL);
1123 1123
1124 if (bp->flags & B44_FLAG_TX_RING_HACK) 1124 if (bp->flags & B44_FLAG_TX_RING_HACK)
1125 dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma, 1125 ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
1126 DMA_TABLE_BYTES, 1126 DMA_TABLE_BYTES,
1127 DMA_TO_DEVICE); 1127 DMA_TO_DEVICE);
1128 1128
1129 for (i = 0; i < bp->rx_pending; i++) { 1129 for (i = 0; i < bp->rx_pending; i++) {
1130 if (b44_alloc_rx_skb(bp, -1, i) < 0) 1130 if (b44_alloc_rx_skb(bp, -1, i) < 0)
@@ -1144,25 +1144,27 @@ static void b44_free_consistent(struct b44 *bp)
1144 bp->tx_buffers = NULL; 1144 bp->tx_buffers = NULL;
1145 if (bp->rx_ring) { 1145 if (bp->rx_ring) {
1146 if (bp->flags & B44_FLAG_RX_RING_HACK) { 1146 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1147 dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma, 1147 ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
1148 DMA_TABLE_BYTES, 1148 DMA_TABLE_BYTES,
1149 DMA_BIDIRECTIONAL); 1149 DMA_BIDIRECTIONAL);
1150 kfree(bp->rx_ring); 1150 kfree(bp->rx_ring);
1151 } else 1151 } else
1152 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES, 1152 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1153 bp->rx_ring, bp->rx_ring_dma); 1153 bp->rx_ring, bp->rx_ring_dma,
1154 GFP_KERNEL);
1154 bp->rx_ring = NULL; 1155 bp->rx_ring = NULL;
1155 bp->flags &= ~B44_FLAG_RX_RING_HACK; 1156 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1156 } 1157 }
1157 if (bp->tx_ring) { 1158 if (bp->tx_ring) {
1158 if (bp->flags & B44_FLAG_TX_RING_HACK) { 1159 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1159 dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma, 1160 ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
1160 DMA_TABLE_BYTES, 1161 DMA_TABLE_BYTES,
1161 DMA_TO_DEVICE); 1162 DMA_TO_DEVICE);
1162 kfree(bp->tx_ring); 1163 kfree(bp->tx_ring);
1163 } else 1164 } else
1164 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES, 1165 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1165 bp->tx_ring, bp->tx_ring_dma); 1166 bp->tx_ring, bp->tx_ring_dma,
1167 GFP_KERNEL);
1166 bp->tx_ring = NULL; 1168 bp->tx_ring = NULL;
1167 bp->flags &= ~B44_FLAG_TX_RING_HACK; 1169 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1168 } 1170 }
@@ -1187,7 +1189,7 @@ static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1187 goto out_err; 1189 goto out_err;
1188 1190
1189 size = DMA_TABLE_BYTES; 1191 size = DMA_TABLE_BYTES;
1190 bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size, &bp->rx_ring_dma, gfp); 1192 bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
1191 if (!bp->rx_ring) { 1193 if (!bp->rx_ring) {
1192 /* Allocation may have failed due to pci_alloc_consistent 1194 /* Allocation may have failed due to pci_alloc_consistent
1193 insisting on use of GFP_DMA, which is more restrictive 1195 insisting on use of GFP_DMA, which is more restrictive
@@ -1199,11 +1201,11 @@ static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1199 if (!rx_ring) 1201 if (!rx_ring)
1200 goto out_err; 1202 goto out_err;
1201 1203
1202 rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring, 1204 rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
1203 DMA_TABLE_BYTES, 1205 DMA_TABLE_BYTES,
1204 DMA_BIDIRECTIONAL); 1206 DMA_BIDIRECTIONAL);
1205 1207
1206 if (dma_mapping_error(rx_ring_dma) || 1208 if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
1207 rx_ring_dma + size > DMA_30BIT_MASK) { 1209 rx_ring_dma + size > DMA_30BIT_MASK) {
1208 kfree(rx_ring); 1210 kfree(rx_ring);
1209 goto out_err; 1211 goto out_err;
@@ -1214,9 +1216,9 @@ static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1214 bp->flags |= B44_FLAG_RX_RING_HACK; 1216 bp->flags |= B44_FLAG_RX_RING_HACK;
1215 } 1217 }
1216 1218
1217 bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size, &bp->tx_ring_dma, gfp); 1219 bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
1218 if (!bp->tx_ring) { 1220 if (!bp->tx_ring) {
1219 /* Allocation may have failed due to dma_alloc_coherent 1221 /* Allocation may have failed due to ssb_dma_alloc_consistent
1220 insisting on use of GFP_DMA, which is more restrictive 1222 insisting on use of GFP_DMA, which is more restrictive
1221 than necessary... */ 1223 than necessary... */
1222 struct dma_desc *tx_ring; 1224 struct dma_desc *tx_ring;
@@ -1226,11 +1228,11 @@ static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1226 if (!tx_ring) 1228 if (!tx_ring)
1227 goto out_err; 1229 goto out_err;
1228 1230
1229 tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring, 1231 tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
1230 DMA_TABLE_BYTES, 1232 DMA_TABLE_BYTES,
1231 DMA_TO_DEVICE); 1233 DMA_TO_DEVICE);
1232 1234
1233 if (dma_mapping_error(tx_ring_dma) || 1235 if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
1234 tx_ring_dma + size > DMA_30BIT_MASK) { 1236 tx_ring_dma + size > DMA_30BIT_MASK) {
1235 kfree(tx_ring); 1237 kfree(tx_ring);
1236 goto out_err; 1238 goto out_err;
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index 41443435ab1c..a6a3da89f590 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -357,7 +357,7 @@ static void bfin_mac_adjust_link(struct net_device *dev)
357 if (!lp->old_link) { 357 if (!lp->old_link) {
358 new_state = 1; 358 new_state = 1;
359 lp->old_link = 1; 359 lp->old_link = 1;
360 netif_schedule(dev); 360 netif_tx_schedule_all(dev);
361 } 361 }
362 } else if (lp->old_link) { 362 } else if (lp->old_link) {
363 new_state = 1; 363 new_state = 1;
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 367b6d462708..5ebde67d4297 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -47,6 +47,7 @@
47#include <linux/prefetch.h> 47#include <linux/prefetch.h>
48#include <linux/cache.h> 48#include <linux/cache.h>
49#include <linux/zlib.h> 49#include <linux/zlib.h>
50#include <linux/log2.h>
50 51
51#include "bnx2.h" 52#include "bnx2.h"
52#include "bnx2_fw.h" 53#include "bnx2_fw.h"
@@ -56,8 +57,8 @@
56 57
57#define DRV_MODULE_NAME "bnx2" 58#define DRV_MODULE_NAME "bnx2"
58#define PFX DRV_MODULE_NAME ": " 59#define PFX DRV_MODULE_NAME ": "
59#define DRV_MODULE_VERSION "1.7.5" 60#define DRV_MODULE_VERSION "1.7.9"
60#define DRV_MODULE_RELDATE "April 29, 2008" 61#define DRV_MODULE_RELDATE "July 18, 2008"
61 62
62#define RUN_AT(x) (jiffies + (x)) 63#define RUN_AT(x) (jiffies + (x))
63 64
@@ -68,7 +69,7 @@ static char version[] __devinitdata =
68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 69 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69 70
70MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); 71MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver"); 72MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709 Driver");
72MODULE_LICENSE("GPL"); 73MODULE_LICENSE("GPL");
73MODULE_VERSION(DRV_MODULE_VERSION); 74MODULE_VERSION(DRV_MODULE_VERSION);
74 75
@@ -87,6 +88,7 @@ typedef enum {
87 BCM5708S, 88 BCM5708S,
88 BCM5709, 89 BCM5709,
89 BCM5709S, 90 BCM5709S,
91 BCM5716,
90} board_t; 92} board_t;
91 93
92/* indexed by board_t, above */ 94/* indexed by board_t, above */
@@ -102,9 +104,10 @@ static struct {
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 104 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
103 { "Broadcom NetXtreme II BCM5709 1000Base-T" }, 105 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 106 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
107 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
105 }; 108 };
106 109
107static struct pci_device_id bnx2_pci_tbl[] = { 110static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 111 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T }, 112 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 113 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
@@ -123,6 +126,8 @@ static struct pci_device_id bnx2_pci_tbl[] = {
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 }, 126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S, 127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, 128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
129 { PCI_VENDOR_ID_BROADCOM, 0x163b,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
126 { 0, } 131 { 0, }
127}; 132};
128 133
@@ -226,7 +231,7 @@ static struct flash_spec flash_5709 = {
226 231
227MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); 232MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
228 233
229static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi) 234static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
230{ 235{
231 u32 diff; 236 u32 diff;
232 237
@@ -235,7 +240,7 @@ static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
235 /* The ring uses 256 indices for 255 entries, one of them 240 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped. 241 * needs to be skipped.
237 */ 242 */
238 diff = bp->tx_prod - bnapi->tx_cons; 243 diff = txr->tx_prod - txr->tx_cons;
239 if (unlikely(diff >= TX_DESC_CNT)) { 244 if (unlikely(diff >= TX_DESC_CNT)) {
240 diff &= 0xffff; 245 diff &= 0xffff;
241 if (diff == TX_DESC_CNT) 246 if (diff == TX_DESC_CNT)
@@ -289,7 +294,6 @@ bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
289 REG_WR(bp, BNX2_CTX_CTX_CTRL, 294 REG_WR(bp, BNX2_CTX_CTX_CTRL,
290 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); 295 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
291 for (i = 0; i < 5; i++) { 296 for (i = 0; i < 5; i++) {
292 u32 val;
293 val = REG_RD(bp, BNX2_CTX_CTX_CTRL); 297 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
294 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) 298 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
295 break; 299 break;
@@ -488,7 +492,7 @@ bnx2_netif_start(struct bnx2 *bp)
488{ 492{
489 if (atomic_dec_and_test(&bp->intr_sem)) { 493 if (atomic_dec_and_test(&bp->intr_sem)) {
490 if (netif_running(bp->dev)) { 494 if (netif_running(bp->dev)) {
491 netif_wake_queue(bp->dev); 495 netif_tx_wake_all_queues(bp->dev);
492 bnx2_napi_enable(bp); 496 bnx2_napi_enable(bp);
493 bnx2_enable_int(bp); 497 bnx2_enable_int(bp);
494 } 498 }
@@ -496,99 +500,162 @@ bnx2_netif_start(struct bnx2 *bp)
496} 500}
497 501
498static void 502static void
499bnx2_free_mem(struct bnx2 *bp) 503bnx2_free_tx_mem(struct bnx2 *bp)
500{ 504{
501 int i; 505 int i;
502 506
503 for (i = 0; i < bp->ctx_pages; i++) { 507 for (i = 0; i < bp->num_tx_rings; i++) {
504 if (bp->ctx_blk[i]) { 508 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
505 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE, 509 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
506 bp->ctx_blk[i], 510
507 bp->ctx_blk_mapping[i]); 511 if (txr->tx_desc_ring) {
508 bp->ctx_blk[i] = NULL; 512 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
513 txr->tx_desc_ring,
514 txr->tx_desc_mapping);
515 txr->tx_desc_ring = NULL;
509 } 516 }
517 kfree(txr->tx_buf_ring);
518 txr->tx_buf_ring = NULL;
510 } 519 }
511 if (bp->status_blk) { 520}
512 pci_free_consistent(bp->pdev, bp->status_stats_size, 521
513 bp->status_blk, bp->status_blk_mapping); 522static void
514 bp->status_blk = NULL; 523bnx2_free_rx_mem(struct bnx2 *bp)
515 bp->stats_blk = NULL; 524{
525 int i;
526
527 for (i = 0; i < bp->num_rx_rings; i++) {
528 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
529 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
530 int j;
531
532 for (j = 0; j < bp->rx_max_ring; j++) {
533 if (rxr->rx_desc_ring[j])
534 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
535 rxr->rx_desc_ring[j],
536 rxr->rx_desc_mapping[j]);
537 rxr->rx_desc_ring[j] = NULL;
538 }
539 if (rxr->rx_buf_ring)
540 vfree(rxr->rx_buf_ring);
541 rxr->rx_buf_ring = NULL;
542
543 for (j = 0; j < bp->rx_max_pg_ring; j++) {
544 if (rxr->rx_pg_desc_ring[j])
545 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
546 rxr->rx_pg_desc_ring[i],
547 rxr->rx_pg_desc_mapping[i]);
548 rxr->rx_pg_desc_ring[i] = NULL;
549 }
550 if (rxr->rx_pg_ring)
551 vfree(rxr->rx_pg_ring);
552 rxr->rx_pg_ring = NULL;
516 } 553 }
517 if (bp->tx_desc_ring) {
518 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
519 bp->tx_desc_ring, bp->tx_desc_mapping);
520 bp->tx_desc_ring = NULL;
521 }
522 kfree(bp->tx_buf_ring);
523 bp->tx_buf_ring = NULL;
524 for (i = 0; i < bp->rx_max_ring; i++) {
525 if (bp->rx_desc_ring[i])
526 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
527 bp->rx_desc_ring[i],
528 bp->rx_desc_mapping[i]);
529 bp->rx_desc_ring[i] = NULL;
530 }
531 vfree(bp->rx_buf_ring);
532 bp->rx_buf_ring = NULL;
533 for (i = 0; i < bp->rx_max_pg_ring; i++) {
534 if (bp->rx_pg_desc_ring[i])
535 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
536 bp->rx_pg_desc_ring[i],
537 bp->rx_pg_desc_mapping[i]);
538 bp->rx_pg_desc_ring[i] = NULL;
539 }
540 if (bp->rx_pg_ring)
541 vfree(bp->rx_pg_ring);
542 bp->rx_pg_ring = NULL;
543} 554}
544 555
545static int 556static int
546bnx2_alloc_mem(struct bnx2 *bp) 557bnx2_alloc_tx_mem(struct bnx2 *bp)
547{ 558{
548 int i, status_blk_size; 559 int i;
549 560
550 bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); 561 for (i = 0; i < bp->num_tx_rings; i++) {
551 if (bp->tx_buf_ring == NULL) 562 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
552 return -ENOMEM; 563 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
553 564
554 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE, 565 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
555 &bp->tx_desc_mapping); 566 if (txr->tx_buf_ring == NULL)
556 if (bp->tx_desc_ring == NULL) 567 return -ENOMEM;
557 goto alloc_mem_err;
558 568
559 bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring); 569 txr->tx_desc_ring =
560 if (bp->rx_buf_ring == NULL) 570 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
561 goto alloc_mem_err; 571 &txr->tx_desc_mapping);
572 if (txr->tx_desc_ring == NULL)
573 return -ENOMEM;
574 }
575 return 0;
576}
577
578static int
579bnx2_alloc_rx_mem(struct bnx2 *bp)
580{
581 int i;
582
583 for (i = 0; i < bp->num_rx_rings; i++) {
584 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
585 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
586 int j;
562 587
563 memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring); 588 rxr->rx_buf_ring =
589 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
590 if (rxr->rx_buf_ring == NULL)
591 return -ENOMEM;
564 592
565 for (i = 0; i < bp->rx_max_ring; i++) { 593 memset(rxr->rx_buf_ring, 0,
566 bp->rx_desc_ring[i] = 594 SW_RXBD_RING_SIZE * bp->rx_max_ring);
567 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
568 &bp->rx_desc_mapping[i]);
569 if (bp->rx_desc_ring[i] == NULL)
570 goto alloc_mem_err;
571 595
572 } 596 for (j = 0; j < bp->rx_max_ring; j++) {
597 rxr->rx_desc_ring[j] =
598 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
599 &rxr->rx_desc_mapping[j]);
600 if (rxr->rx_desc_ring[j] == NULL)
601 return -ENOMEM;
573 602
574 if (bp->rx_pg_ring_size) { 603 }
575 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE * 604
576 bp->rx_max_pg_ring); 605 if (bp->rx_pg_ring_size) {
577 if (bp->rx_pg_ring == NULL) 606 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
578 goto alloc_mem_err; 607 bp->rx_max_pg_ring);
608 if (rxr->rx_pg_ring == NULL)
609 return -ENOMEM;
610
611 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
612 bp->rx_max_pg_ring);
613 }
614
615 for (j = 0; j < bp->rx_max_pg_ring; j++) {
616 rxr->rx_pg_desc_ring[j] =
617 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
618 &rxr->rx_pg_desc_mapping[j]);
619 if (rxr->rx_pg_desc_ring[j] == NULL)
620 return -ENOMEM;
579 621
580 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE * 622 }
581 bp->rx_max_pg_ring);
582 } 623 }
624 return 0;
625}
583 626
584 for (i = 0; i < bp->rx_max_pg_ring; i++) { 627static void
585 bp->rx_pg_desc_ring[i] = 628bnx2_free_mem(struct bnx2 *bp)
586 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE, 629{
587 &bp->rx_pg_desc_mapping[i]); 630 int i;
588 if (bp->rx_pg_desc_ring[i] == NULL) 631 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
589 goto alloc_mem_err; 632
633 bnx2_free_tx_mem(bp);
634 bnx2_free_rx_mem(bp);
590 635
636 for (i = 0; i < bp->ctx_pages; i++) {
637 if (bp->ctx_blk[i]) {
638 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
639 bp->ctx_blk[i],
640 bp->ctx_blk_mapping[i]);
641 bp->ctx_blk[i] = NULL;
642 }
591 } 643 }
644 if (bnapi->status_blk.msi) {
645 pci_free_consistent(bp->pdev, bp->status_stats_size,
646 bnapi->status_blk.msi,
647 bp->status_blk_mapping);
648 bnapi->status_blk.msi = NULL;
649 bp->stats_blk = NULL;
650 }
651}
652
653static int
654bnx2_alloc_mem(struct bnx2 *bp)
655{
656 int i, status_blk_size, err;
657 struct bnx2_napi *bnapi;
658 void *status_blk;
592 659
593 /* Combine status and statistics blocks into one allocation. */ 660 /* Combine status and statistics blocks into one allocation. */
594 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); 661 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
@@ -598,27 +665,37 @@ bnx2_alloc_mem(struct bnx2 *bp)
598 bp->status_stats_size = status_blk_size + 665 bp->status_stats_size = status_blk_size +
599 sizeof(struct statistics_block); 666 sizeof(struct statistics_block);
600 667
601 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size, 668 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
602 &bp->status_blk_mapping); 669 &bp->status_blk_mapping);
603 if (bp->status_blk == NULL) 670 if (status_blk == NULL)
604 goto alloc_mem_err; 671 goto alloc_mem_err;
605 672
606 memset(bp->status_blk, 0, bp->status_stats_size); 673 memset(status_blk, 0, bp->status_stats_size);
607 674
608 bp->bnx2_napi[0].status_blk = bp->status_blk; 675 bnapi = &bp->bnx2_napi[0];
676 bnapi->status_blk.msi = status_blk;
677 bnapi->hw_tx_cons_ptr =
678 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
679 bnapi->hw_rx_cons_ptr =
680 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
609 if (bp->flags & BNX2_FLAG_MSIX_CAP) { 681 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
610 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) { 682 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
611 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 683 struct status_block_msix *sblk;
612 684
613 bnapi->status_blk_msix = (void *) 685 bnapi = &bp->bnx2_napi[i];
614 ((unsigned long) bp->status_blk + 686
615 BNX2_SBLK_MSIX_ALIGN_SIZE * i); 687 sblk = (void *) (status_blk +
688 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
689 bnapi->status_blk.msix = sblk;
690 bnapi->hw_tx_cons_ptr =
691 &sblk->status_tx_quick_consumer_index;
692 bnapi->hw_rx_cons_ptr =
693 &sblk->status_rx_quick_consumer_index;
616 bnapi->int_num = i << 24; 694 bnapi->int_num = i << 24;
617 } 695 }
618 } 696 }
619 697
620 bp->stats_blk = (void *) ((unsigned long) bp->status_blk + 698 bp->stats_blk = status_blk + status_blk_size;
621 status_blk_size);
622 699
623 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; 700 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
624 701
@@ -634,6 +711,15 @@ bnx2_alloc_mem(struct bnx2 *bp)
634 goto alloc_mem_err; 711 goto alloc_mem_err;
635 } 712 }
636 } 713 }
714
715 err = bnx2_alloc_rx_mem(bp);
716 if (err)
717 goto alloc_mem_err;
718
719 err = bnx2_alloc_tx_mem(bp);
720 if (err)
721 goto alloc_mem_err;
722
637 return 0; 723 return 0;
638 724
639alloc_mem_err: 725alloc_mem_err:
@@ -993,9 +1079,9 @@ bnx2_copper_linkup(struct bnx2 *bp)
993} 1079}
994 1080
995static void 1081static void
996bnx2_init_rx_context0(struct bnx2 *bp) 1082bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
997{ 1083{
998 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID); 1084 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
999 1085
1000 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 1086 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1001 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; 1087 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
@@ -1028,6 +1114,19 @@ bnx2_init_rx_context0(struct bnx2 *bp)
1028 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); 1114 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1029} 1115}
1030 1116
1117static void
1118bnx2_init_all_rx_contexts(struct bnx2 *bp)
1119{
1120 int i;
1121 u32 cid;
1122
1123 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1124 if (i == 1)
1125 cid = RX_RSS_CID;
1126 bnx2_init_rx_context(bp, cid);
1127 }
1128}
1129
1031static int 1130static int
1032bnx2_set_mac_link(struct bnx2 *bp) 1131bnx2_set_mac_link(struct bnx2 *bp)
1033{ 1132{
@@ -1093,7 +1192,7 @@ bnx2_set_mac_link(struct bnx2 *bp)
1093 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); 1192 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1094 1193
1095 if (CHIP_NUM(bp) == CHIP_NUM_5709) 1194 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1096 bnx2_init_rx_context0(bp); 1195 bnx2_init_all_rx_contexts(bp);
1097 1196
1098 return 0; 1197 return 0;
1099} 1198}
@@ -1392,7 +1491,7 @@ bnx2_phy_get_pause_adv(struct bnx2 *bp)
1392 return adv; 1491 return adv;
1393} 1492}
1394 1493
1395static int bnx2_fw_sync(struct bnx2 *, u32, int); 1494static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1396 1495
1397static int 1496static int
1398bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) 1497bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
@@ -1445,7 +1544,7 @@ bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1445 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg); 1544 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1446 1545
1447 spin_unlock_bh(&bp->phy_lock); 1546 spin_unlock_bh(&bp->phy_lock);
1448 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0); 1547 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1449 spin_lock_bh(&bp->phy_lock); 1548 spin_lock_bh(&bp->phy_lock);
1450 1549
1451 return 0; 1550 return 0;
@@ -1875,7 +1974,7 @@ bnx2_setup_phy(struct bnx2 *bp, u8 port)
1875} 1974}
1876 1975
1877static int 1976static int
1878bnx2_init_5709s_phy(struct bnx2 *bp) 1977bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1879{ 1978{
1880 u32 val; 1979 u32 val;
1881 1980
@@ -1890,7 +1989,8 @@ bnx2_init_5709s_phy(struct bnx2 *bp)
1890 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); 1989 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1891 1990
1892 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1991 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1893 bnx2_reset_phy(bp); 1992 if (reset_phy)
1993 bnx2_reset_phy(bp);
1894 1994
1895 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); 1995 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1896 1996
@@ -1924,11 +2024,12 @@ bnx2_init_5709s_phy(struct bnx2 *bp)
1924} 2024}
1925 2025
1926static int 2026static int
1927bnx2_init_5708s_phy(struct bnx2 *bp) 2027bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
1928{ 2028{
1929 u32 val; 2029 u32 val;
1930 2030
1931 bnx2_reset_phy(bp); 2031 if (reset_phy)
2032 bnx2_reset_phy(bp);
1932 2033
1933 bp->mii_up1 = BCM5708S_UP1; 2034 bp->mii_up1 = BCM5708S_UP1;
1934 2035
@@ -1981,9 +2082,10 @@ bnx2_init_5708s_phy(struct bnx2 *bp)
1981} 2082}
1982 2083
1983static int 2084static int
1984bnx2_init_5706s_phy(struct bnx2 *bp) 2085bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
1985{ 2086{
1986 bnx2_reset_phy(bp); 2087 if (reset_phy)
2088 bnx2_reset_phy(bp);
1987 2089
1988 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 2090 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1989 2091
@@ -2018,11 +2120,12 @@ bnx2_init_5706s_phy(struct bnx2 *bp)
2018} 2120}
2019 2121
2020static int 2122static int
2021bnx2_init_copper_phy(struct bnx2 *bp) 2123bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2022{ 2124{
2023 u32 val; 2125 u32 val;
2024 2126
2025 bnx2_reset_phy(bp); 2127 if (reset_phy)
2128 bnx2_reset_phy(bp);
2026 2129
2027 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { 2130 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2028 bnx2_write_phy(bp, 0x18, 0x0c00); 2131 bnx2_write_phy(bp, 0x18, 0x0c00);
@@ -2070,7 +2173,7 @@ bnx2_init_copper_phy(struct bnx2 *bp)
2070 2173
2071 2174
2072static int 2175static int
2073bnx2_init_phy(struct bnx2 *bp) 2176bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2074{ 2177{
2075 u32 val; 2178 u32 val;
2076 int rc = 0; 2179 int rc = 0;
@@ -2096,14 +2199,14 @@ bnx2_init_phy(struct bnx2 *bp)
2096 2199
2097 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 2200 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2098 if (CHIP_NUM(bp) == CHIP_NUM_5706) 2201 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2099 rc = bnx2_init_5706s_phy(bp); 2202 rc = bnx2_init_5706s_phy(bp, reset_phy);
2100 else if (CHIP_NUM(bp) == CHIP_NUM_5708) 2203 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2101 rc = bnx2_init_5708s_phy(bp); 2204 rc = bnx2_init_5708s_phy(bp, reset_phy);
2102 else if (CHIP_NUM(bp) == CHIP_NUM_5709) 2205 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2103 rc = bnx2_init_5709s_phy(bp); 2206 rc = bnx2_init_5709s_phy(bp, reset_phy);
2104 } 2207 }
2105 else { 2208 else {
2106 rc = bnx2_init_copper_phy(bp); 2209 rc = bnx2_init_copper_phy(bp, reset_phy);
2107 } 2210 }
2108 2211
2109setup_phy: 2212setup_phy:
@@ -2159,7 +2262,7 @@ bnx2_set_phy_loopback(struct bnx2 *bp)
2159} 2262}
2160 2263
2161static int 2264static int
2162bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent) 2265bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2163{ 2266{
2164 int i; 2267 int i;
2165 u32 val; 2268 u32 val;
@@ -2169,6 +2272,9 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2169 2272
2170 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); 2273 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2171 2274
2275 if (!ack)
2276 return 0;
2277
2172 /* wait for an acknowledgement. */ 2278 /* wait for an acknowledgement. */
2173 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) { 2279 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2174 msleep(10); 2280 msleep(10);
@@ -2345,28 +2451,27 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2345} 2451}
2346 2452
2347static void 2453static void
2348bnx2_set_mac_addr(struct bnx2 *bp) 2454bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2349{ 2455{
2350 u32 val; 2456 u32 val;
2351 u8 *mac_addr = bp->dev->dev_addr;
2352 2457
2353 val = (mac_addr[0] << 8) | mac_addr[1]; 2458 val = (mac_addr[0] << 8) | mac_addr[1];
2354 2459
2355 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val); 2460 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2356 2461
2357 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 2462 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2358 (mac_addr[4] << 8) | mac_addr[5]; 2463 (mac_addr[4] << 8) | mac_addr[5];
2359 2464
2360 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val); 2465 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2361} 2466}
2362 2467
2363static inline int 2468static inline int
2364bnx2_alloc_rx_page(struct bnx2 *bp, u16 index) 2469bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2365{ 2470{
2366 dma_addr_t mapping; 2471 dma_addr_t mapping;
2367 struct sw_pg *rx_pg = &bp->rx_pg_ring[index]; 2472 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2368 struct rx_bd *rxbd = 2473 struct rx_bd *rxbd =
2369 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)]; 2474 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2370 struct page *page = alloc_page(GFP_ATOMIC); 2475 struct page *page = alloc_page(GFP_ATOMIC);
2371 2476
2372 if (!page) 2477 if (!page)
@@ -2381,9 +2486,9 @@ bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2381} 2486}
2382 2487
2383static void 2488static void
2384bnx2_free_rx_page(struct bnx2 *bp, u16 index) 2489bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2385{ 2490{
2386 struct sw_pg *rx_pg = &bp->rx_pg_ring[index]; 2491 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2387 struct page *page = rx_pg->page; 2492 struct page *page = rx_pg->page;
2388 2493
2389 if (!page) 2494 if (!page)
@@ -2397,12 +2502,12 @@ bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2397} 2502}
2398 2503
2399static inline int 2504static inline int
2400bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index) 2505bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2401{ 2506{
2402 struct sk_buff *skb; 2507 struct sk_buff *skb;
2403 struct sw_bd *rx_buf = &bp->rx_buf_ring[index]; 2508 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2404 dma_addr_t mapping; 2509 dma_addr_t mapping;
2405 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)]; 2510 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2406 unsigned long align; 2511 unsigned long align;
2407 2512
2408 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size); 2513 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
@@ -2422,7 +2527,7 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
2422 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; 2527 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2423 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; 2528 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2424 2529
2425 bnapi->rx_prod_bseq += bp->rx_buf_use_size; 2530 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2426 2531
2427 return 0; 2532 return 0;
2428} 2533}
@@ -2430,7 +2535,7 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
2430static int 2535static int
2431bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event) 2536bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2432{ 2537{
2433 struct status_block *sblk = bnapi->status_blk; 2538 struct status_block *sblk = bnapi->status_blk.msi;
2434 u32 new_link_state, old_link_state; 2539 u32 new_link_state, old_link_state;
2435 int is_set = 1; 2540 int is_set = 1;
2436 2541
@@ -2466,11 +2571,9 @@ bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2466{ 2571{
2467 u16 cons; 2572 u16 cons;
2468 2573
2469 if (bnapi->int_num == 0) 2574 /* Tell compiler that status block fields can change. */
2470 cons = bnapi->status_blk->status_tx_quick_consumer_index0; 2575 barrier();
2471 else 2576 cons = *bnapi->hw_tx_cons_ptr;
2472 cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
2473
2474 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT)) 2577 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2475 cons++; 2578 cons++;
2476 return cons; 2579 return cons;
@@ -2479,11 +2582,16 @@ bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2479static int 2582static int
2480bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) 2583bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2481{ 2584{
2585 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2482 u16 hw_cons, sw_cons, sw_ring_cons; 2586 u16 hw_cons, sw_cons, sw_ring_cons;
2483 int tx_pkt = 0; 2587 int tx_pkt = 0, index;
2588 struct netdev_queue *txq;
2589
2590 index = (bnapi - bp->bnx2_napi);
2591 txq = netdev_get_tx_queue(bp->dev, index);
2484 2592
2485 hw_cons = bnx2_get_hw_tx_cons(bnapi); 2593 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2486 sw_cons = bnapi->tx_cons; 2594 sw_cons = txr->tx_cons;
2487 2595
2488 while (sw_cons != hw_cons) { 2596 while (sw_cons != hw_cons) {
2489 struct sw_bd *tx_buf; 2597 struct sw_bd *tx_buf;
@@ -2492,7 +2600,7 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2492 2600
2493 sw_ring_cons = TX_RING_IDX(sw_cons); 2601 sw_ring_cons = TX_RING_IDX(sw_cons);
2494 2602
2495 tx_buf = &bp->tx_buf_ring[sw_ring_cons]; 2603 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2496 skb = tx_buf->skb; 2604 skb = tx_buf->skb;
2497 2605
2498 /* partial BD completions possible with TSO packets */ 2606 /* partial BD completions possible with TSO packets */
@@ -2522,7 +2630,7 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2522 2630
2523 pci_unmap_page(bp->pdev, 2631 pci_unmap_page(bp->pdev,
2524 pci_unmap_addr( 2632 pci_unmap_addr(
2525 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)], 2633 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2526 mapping), 2634 mapping),
2527 skb_shinfo(skb)->frags[i].size, 2635 skb_shinfo(skb)->frags[i].size,
2528 PCI_DMA_TODEVICE); 2636 PCI_DMA_TODEVICE);
@@ -2538,44 +2646,46 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2538 hw_cons = bnx2_get_hw_tx_cons(bnapi); 2646 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2539 } 2647 }
2540 2648
2541 bnapi->hw_tx_cons = hw_cons; 2649 txr->hw_tx_cons = hw_cons;
2542 bnapi->tx_cons = sw_cons; 2650 txr->tx_cons = sw_cons;
2651
2543 /* Need to make the tx_cons update visible to bnx2_start_xmit() 2652 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2544 * before checking for netif_queue_stopped(). Without the 2653 * before checking for netif_tx_queue_stopped(). Without the
2545 * memory barrier, there is a small possibility that bnx2_start_xmit() 2654 * memory barrier, there is a small possibility that bnx2_start_xmit()
2546 * will miss it and cause the queue to be stopped forever. 2655 * will miss it and cause the queue to be stopped forever.
2547 */ 2656 */
2548 smp_mb(); 2657 smp_mb();
2549 2658
2550 if (unlikely(netif_queue_stopped(bp->dev)) && 2659 if (unlikely(netif_tx_queue_stopped(txq)) &&
2551 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) { 2660 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2552 netif_tx_lock(bp->dev); 2661 __netif_tx_lock(txq, smp_processor_id());
2553 if ((netif_queue_stopped(bp->dev)) && 2662 if ((netif_tx_queue_stopped(txq)) &&
2554 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) 2663 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2555 netif_wake_queue(bp->dev); 2664 netif_tx_wake_queue(txq);
2556 netif_tx_unlock(bp->dev); 2665 __netif_tx_unlock(txq);
2557 } 2666 }
2667
2558 return tx_pkt; 2668 return tx_pkt;
2559} 2669}
2560 2670
2561static void 2671static void
2562bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi, 2672bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2563 struct sk_buff *skb, int count) 2673 struct sk_buff *skb, int count)
2564{ 2674{
2565 struct sw_pg *cons_rx_pg, *prod_rx_pg; 2675 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2566 struct rx_bd *cons_bd, *prod_bd; 2676 struct rx_bd *cons_bd, *prod_bd;
2567 dma_addr_t mapping; 2677 dma_addr_t mapping;
2568 int i; 2678 int i;
2569 u16 hw_prod = bnapi->rx_pg_prod, prod; 2679 u16 hw_prod = rxr->rx_pg_prod, prod;
2570 u16 cons = bnapi->rx_pg_cons; 2680 u16 cons = rxr->rx_pg_cons;
2571 2681
2572 for (i = 0; i < count; i++) { 2682 for (i = 0; i < count; i++) {
2573 prod = RX_PG_RING_IDX(hw_prod); 2683 prod = RX_PG_RING_IDX(hw_prod);
2574 2684
2575 prod_rx_pg = &bp->rx_pg_ring[prod]; 2685 prod_rx_pg = &rxr->rx_pg_ring[prod];
2576 cons_rx_pg = &bp->rx_pg_ring[cons]; 2686 cons_rx_pg = &rxr->rx_pg_ring[cons];
2577 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 2687 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2578 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 2688 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2579 2689
2580 if (i == 0 && skb) { 2690 if (i == 0 && skb) {
2581 struct page *page; 2691 struct page *page;
@@ -2604,25 +2714,25 @@ bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi,
2604 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons)); 2714 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2605 hw_prod = NEXT_RX_BD(hw_prod); 2715 hw_prod = NEXT_RX_BD(hw_prod);
2606 } 2716 }
2607 bnapi->rx_pg_prod = hw_prod; 2717 rxr->rx_pg_prod = hw_prod;
2608 bnapi->rx_pg_cons = cons; 2718 rxr->rx_pg_cons = cons;
2609} 2719}
2610 2720
2611static inline void 2721static inline void
2612bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, 2722bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2613 u16 cons, u16 prod) 2723 struct sk_buff *skb, u16 cons, u16 prod)
2614{ 2724{
2615 struct sw_bd *cons_rx_buf, *prod_rx_buf; 2725 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2616 struct rx_bd *cons_bd, *prod_bd; 2726 struct rx_bd *cons_bd, *prod_bd;
2617 2727
2618 cons_rx_buf = &bp->rx_buf_ring[cons]; 2728 cons_rx_buf = &rxr->rx_buf_ring[cons];
2619 prod_rx_buf = &bp->rx_buf_ring[prod]; 2729 prod_rx_buf = &rxr->rx_buf_ring[prod];
2620 2730
2621 pci_dma_sync_single_for_device(bp->pdev, 2731 pci_dma_sync_single_for_device(bp->pdev,
2622 pci_unmap_addr(cons_rx_buf, mapping), 2732 pci_unmap_addr(cons_rx_buf, mapping),
2623 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); 2733 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2624 2734
2625 bnapi->rx_prod_bseq += bp->rx_buf_use_size; 2735 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2626 2736
2627 prod_rx_buf->skb = skb; 2737 prod_rx_buf->skb = skb;
2628 2738
@@ -2632,33 +2742,33 @@ bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2632 pci_unmap_addr_set(prod_rx_buf, mapping, 2742 pci_unmap_addr_set(prod_rx_buf, mapping,
2633 pci_unmap_addr(cons_rx_buf, mapping)); 2743 pci_unmap_addr(cons_rx_buf, mapping));
2634 2744
2635 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 2745 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2636 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 2746 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2637 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; 2747 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2638 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; 2748 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2639} 2749}
2640 2750
2641static int 2751static int
2642bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, 2752bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2643 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr, 2753 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2644 u32 ring_idx) 2754 u32 ring_idx)
2645{ 2755{
2646 int err; 2756 int err;
2647 u16 prod = ring_idx & 0xffff; 2757 u16 prod = ring_idx & 0xffff;
2648 2758
2649 err = bnx2_alloc_rx_skb(bp, bnapi, prod); 2759 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2650 if (unlikely(err)) { 2760 if (unlikely(err)) {
2651 bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod); 2761 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2652 if (hdr_len) { 2762 if (hdr_len) {
2653 unsigned int raw_len = len + 4; 2763 unsigned int raw_len = len + 4;
2654 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT; 2764 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2655 2765
2656 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages); 2766 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2657 } 2767 }
2658 return err; 2768 return err;
2659 } 2769 }
2660 2770
2661 skb_reserve(skb, bp->rx_offset); 2771 skb_reserve(skb, BNX2_RX_OFFSET);
2662 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size, 2772 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2663 PCI_DMA_FROMDEVICE); 2773 PCI_DMA_FROMDEVICE);
2664 2774
@@ -2668,8 +2778,8 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2668 } else { 2778 } else {
2669 unsigned int i, frag_len, frag_size, pages; 2779 unsigned int i, frag_len, frag_size, pages;
2670 struct sw_pg *rx_pg; 2780 struct sw_pg *rx_pg;
2671 u16 pg_cons = bnapi->rx_pg_cons; 2781 u16 pg_cons = rxr->rx_pg_cons;
2672 u16 pg_prod = bnapi->rx_pg_prod; 2782 u16 pg_prod = rxr->rx_pg_prod;
2673 2783
2674 frag_size = len + 4 - hdr_len; 2784 frag_size = len + 4 - hdr_len;
2675 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT; 2785 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
@@ -2680,9 +2790,9 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2680 if (unlikely(frag_len <= 4)) { 2790 if (unlikely(frag_len <= 4)) {
2681 unsigned int tail = 4 - frag_len; 2791 unsigned int tail = 4 - frag_len;
2682 2792
2683 bnapi->rx_pg_cons = pg_cons; 2793 rxr->rx_pg_cons = pg_cons;
2684 bnapi->rx_pg_prod = pg_prod; 2794 rxr->rx_pg_prod = pg_prod;
2685 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, 2795 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2686 pages - i); 2796 pages - i);
2687 skb->len -= tail; 2797 skb->len -= tail;
2688 if (i == 0) { 2798 if (i == 0) {
@@ -2696,7 +2806,7 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2696 } 2806 }
2697 return 0; 2807 return 0;
2698 } 2808 }
2699 rx_pg = &bp->rx_pg_ring[pg_cons]; 2809 rx_pg = &rxr->rx_pg_ring[pg_cons];
2700 2810
2701 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), 2811 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2702 PAGE_SIZE, PCI_DMA_FROMDEVICE); 2812 PAGE_SIZE, PCI_DMA_FROMDEVICE);
@@ -2707,11 +2817,12 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2707 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); 2817 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2708 rx_pg->page = NULL; 2818 rx_pg->page = NULL;
2709 2819
2710 err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod)); 2820 err = bnx2_alloc_rx_page(bp, rxr,
2821 RX_PG_RING_IDX(pg_prod));
2711 if (unlikely(err)) { 2822 if (unlikely(err)) {
2712 bnapi->rx_pg_cons = pg_cons; 2823 rxr->rx_pg_cons = pg_cons;
2713 bnapi->rx_pg_prod = pg_prod; 2824 rxr->rx_pg_prod = pg_prod;
2714 bnx2_reuse_rx_skb_pages(bp, bnapi, skb, 2825 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2715 pages - i); 2826 pages - i);
2716 return err; 2827 return err;
2717 } 2828 }
@@ -2724,8 +2835,8 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2724 pg_prod = NEXT_RX_BD(pg_prod); 2835 pg_prod = NEXT_RX_BD(pg_prod);
2725 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons)); 2836 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2726 } 2837 }
2727 bnapi->rx_pg_prod = pg_prod; 2838 rxr->rx_pg_prod = pg_prod;
2728 bnapi->rx_pg_cons = pg_cons; 2839 rxr->rx_pg_cons = pg_cons;
2729 } 2840 }
2730 return 0; 2841 return 0;
2731} 2842}
@@ -2733,8 +2844,11 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2733static inline u16 2844static inline u16
2734bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi) 2845bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2735{ 2846{
2736 u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0; 2847 u16 cons;
2737 2848
2849 /* Tell compiler that status block fields can change. */
2850 barrier();
2851 cons = *bnapi->hw_rx_cons_ptr;
2738 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)) 2852 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2739 cons++; 2853 cons++;
2740 return cons; 2854 return cons;
@@ -2743,13 +2857,14 @@ bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2743static int 2857static int
2744bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) 2858bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2745{ 2859{
2860 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2746 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; 2861 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2747 struct l2_fhdr *rx_hdr; 2862 struct l2_fhdr *rx_hdr;
2748 int rx_pkt = 0, pg_ring_used = 0; 2863 int rx_pkt = 0, pg_ring_used = 0;
2749 2864
2750 hw_cons = bnx2_get_hw_rx_cons(bnapi); 2865 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2751 sw_cons = bnapi->rx_cons; 2866 sw_cons = rxr->rx_cons;
2752 sw_prod = bnapi->rx_prod; 2867 sw_prod = rxr->rx_prod;
2753 2868
2754 /* Memory barrier necessary as speculative reads of the rx 2869 /* Memory barrier necessary as speculative reads of the rx
2755 * buffer can be ahead of the index in the status block 2870 * buffer can be ahead of the index in the status block
@@ -2765,7 +2880,7 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2765 sw_ring_cons = RX_RING_IDX(sw_cons); 2880 sw_ring_cons = RX_RING_IDX(sw_cons);
2766 sw_ring_prod = RX_RING_IDX(sw_prod); 2881 sw_ring_prod = RX_RING_IDX(sw_prod);
2767 2882
2768 rx_buf = &bp->rx_buf_ring[sw_ring_cons]; 2883 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2769 skb = rx_buf->skb; 2884 skb = rx_buf->skb;
2770 2885
2771 rx_buf->skb = NULL; 2886 rx_buf->skb = NULL;
@@ -2773,7 +2888,8 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2773 dma_addr = pci_unmap_addr(rx_buf, mapping); 2888 dma_addr = pci_unmap_addr(rx_buf, mapping);
2774 2889
2775 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr, 2890 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2776 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); 2891 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2892 PCI_DMA_FROMDEVICE);
2777 2893
2778 rx_hdr = (struct l2_fhdr *) skb->data; 2894 rx_hdr = (struct l2_fhdr *) skb->data;
2779 len = rx_hdr->l2_fhdr_pkt_len; 2895 len = rx_hdr->l2_fhdr_pkt_len;
@@ -2785,7 +2901,7 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2785 L2_FHDR_ERRORS_TOO_SHORT | 2901 L2_FHDR_ERRORS_TOO_SHORT |
2786 L2_FHDR_ERRORS_GIANT_FRAME)) { 2902 L2_FHDR_ERRORS_GIANT_FRAME)) {
2787 2903
2788 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons, 2904 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2789 sw_ring_prod); 2905 sw_ring_prod);
2790 goto next_rx; 2906 goto next_rx;
2791 } 2907 }
@@ -2805,22 +2921,23 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2805 2921
2806 new_skb = netdev_alloc_skb(bp->dev, len + 2); 2922 new_skb = netdev_alloc_skb(bp->dev, len + 2);
2807 if (new_skb == NULL) { 2923 if (new_skb == NULL) {
2808 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons, 2924 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2809 sw_ring_prod); 2925 sw_ring_prod);
2810 goto next_rx; 2926 goto next_rx;
2811 } 2927 }
2812 2928
2813 /* aligned copy */ 2929 /* aligned copy */
2814 skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2, 2930 skb_copy_from_linear_data_offset(skb,
2931 BNX2_RX_OFFSET - 2,
2815 new_skb->data, len + 2); 2932 new_skb->data, len + 2);
2816 skb_reserve(new_skb, 2); 2933 skb_reserve(new_skb, 2);
2817 skb_put(new_skb, len); 2934 skb_put(new_skb, len);
2818 2935
2819 bnx2_reuse_rx_skb(bp, bnapi, skb, 2936 bnx2_reuse_rx_skb(bp, rxr, skb,
2820 sw_ring_cons, sw_ring_prod); 2937 sw_ring_cons, sw_ring_prod);
2821 2938
2822 skb = new_skb; 2939 skb = new_skb;
2823 } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len, 2940 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2824 dma_addr, (sw_ring_cons << 16) | sw_ring_prod))) 2941 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2825 goto next_rx; 2942 goto next_rx;
2826 2943
@@ -2869,16 +2986,15 @@ next_rx:
2869 rmb(); 2986 rmb();
2870 } 2987 }
2871 } 2988 }
2872 bnapi->rx_cons = sw_cons; 2989 rxr->rx_cons = sw_cons;
2873 bnapi->rx_prod = sw_prod; 2990 rxr->rx_prod = sw_prod;
2874 2991
2875 if (pg_ring_used) 2992 if (pg_ring_used)
2876 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX, 2993 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
2877 bnapi->rx_pg_prod);
2878 2994
2879 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod); 2995 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
2880 2996
2881 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq); 2997 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
2882 2998
2883 mmiowb(); 2999 mmiowb();
2884 3000
@@ -2892,11 +3008,11 @@ next_rx:
2892static irqreturn_t 3008static irqreturn_t
2893bnx2_msi(int irq, void *dev_instance) 3009bnx2_msi(int irq, void *dev_instance)
2894{ 3010{
2895 struct net_device *dev = dev_instance; 3011 struct bnx2_napi *bnapi = dev_instance;
2896 struct bnx2 *bp = netdev_priv(dev); 3012 struct bnx2 *bp = bnapi->bp;
2897 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 3013 struct net_device *dev = bp->dev;
2898 3014
2899 prefetch(bnapi->status_blk); 3015 prefetch(bnapi->status_blk.msi);
2900 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3016 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2901 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 3017 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2902 BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 3018 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
@@ -2913,11 +3029,11 @@ bnx2_msi(int irq, void *dev_instance)
2913static irqreturn_t 3029static irqreturn_t
2914bnx2_msi_1shot(int irq, void *dev_instance) 3030bnx2_msi_1shot(int irq, void *dev_instance)
2915{ 3031{
2916 struct net_device *dev = dev_instance; 3032 struct bnx2_napi *bnapi = dev_instance;
2917 struct bnx2 *bp = netdev_priv(dev); 3033 struct bnx2 *bp = bnapi->bp;
2918 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 3034 struct net_device *dev = bp->dev;
2919 3035
2920 prefetch(bnapi->status_blk); 3036 prefetch(bnapi->status_blk.msi);
2921 3037
2922 /* Return here if interrupt is disabled. */ 3038 /* Return here if interrupt is disabled. */
2923 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 3039 if (unlikely(atomic_read(&bp->intr_sem) != 0))
@@ -2931,10 +3047,10 @@ bnx2_msi_1shot(int irq, void *dev_instance)
2931static irqreturn_t 3047static irqreturn_t
2932bnx2_interrupt(int irq, void *dev_instance) 3048bnx2_interrupt(int irq, void *dev_instance)
2933{ 3049{
2934 struct net_device *dev = dev_instance; 3050 struct bnx2_napi *bnapi = dev_instance;
2935 struct bnx2 *bp = netdev_priv(dev); 3051 struct bnx2 *bp = bnapi->bp;
2936 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 3052 struct net_device *dev = bp->dev;
2937 struct status_block *sblk = bnapi->status_blk; 3053 struct status_block *sblk = bnapi->status_blk.msi;
2938 3054
2939 /* When using INTx, it is possible for the interrupt to arrive 3055 /* When using INTx, it is possible for the interrupt to arrive
2940 * at the CPU before the status block posted prior to the 3056 * at the CPU before the status block posted prior to the
@@ -2968,21 +3084,16 @@ bnx2_interrupt(int irq, void *dev_instance)
2968 return IRQ_HANDLED; 3084 return IRQ_HANDLED;
2969} 3085}
2970 3086
2971static irqreturn_t 3087static inline int
2972bnx2_tx_msix(int irq, void *dev_instance) 3088bnx2_has_fast_work(struct bnx2_napi *bnapi)
2973{ 3089{
2974 struct net_device *dev = dev_instance; 3090 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2975 struct bnx2 *bp = netdev_priv(dev); 3091 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2976 struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC];
2977
2978 prefetch(bnapi->status_blk_msix);
2979 3092
2980 /* Return here if interrupt is disabled. */ 3093 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
2981 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 3094 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
2982 return IRQ_HANDLED; 3095 return 1;
2983 3096 return 0;
2984 netif_rx_schedule(dev, &bnapi->napi);
2985 return IRQ_HANDLED;
2986} 3097}
2987 3098
2988#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \ 3099#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
@@ -2991,10 +3102,9 @@ bnx2_tx_msix(int irq, void *dev_instance)
2991static inline int 3102static inline int
2992bnx2_has_work(struct bnx2_napi *bnapi) 3103bnx2_has_work(struct bnx2_napi *bnapi)
2993{ 3104{
2994 struct status_block *sblk = bnapi->status_blk; 3105 struct status_block *sblk = bnapi->status_blk.msi;
2995 3106
2996 if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) || 3107 if (bnx2_has_fast_work(bnapi))
2997 (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
2998 return 1; 3108 return 1;
2999 3109
3000 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != 3110 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
@@ -3004,33 +3114,9 @@ bnx2_has_work(struct bnx2_napi *bnapi)
3004 return 0; 3114 return 0;
3005} 3115}
3006 3116
3007static int bnx2_tx_poll(struct napi_struct *napi, int budget) 3117static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3008{
3009 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3010 struct bnx2 *bp = bnapi->bp;
3011 int work_done = 0;
3012 struct status_block_msix *sblk = bnapi->status_blk_msix;
3013
3014 do {
3015 work_done += bnx2_tx_int(bp, bnapi, budget - work_done);
3016 if (unlikely(work_done >= budget))
3017 return work_done;
3018
3019 bnapi->last_status_idx = sblk->status_idx;
3020 rmb();
3021 } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons);
3022
3023 netif_rx_complete(bp->dev, napi);
3024 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3025 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3026 bnapi->last_status_idx);
3027 return work_done;
3028}
3029
3030static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3031 int work_done, int budget)
3032{ 3118{
3033 struct status_block *sblk = bnapi->status_blk; 3119 struct status_block *sblk = bnapi->status_blk.msi;
3034 u32 status_attn_bits = sblk->status_attn_bits; 3120 u32 status_attn_bits = sblk->status_attn_bits;
3035 u32 status_attn_bits_ack = sblk->status_attn_bits_ack; 3121 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3036 3122
@@ -3046,24 +3132,60 @@ static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3046 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); 3132 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3047 REG_RD(bp, BNX2_HC_COMMAND); 3133 REG_RD(bp, BNX2_HC_COMMAND);
3048 } 3134 }
3135}
3049 3136
3050 if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons) 3137static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3138 int work_done, int budget)
3139{
3140 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3141 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3142
3143 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3051 bnx2_tx_int(bp, bnapi, 0); 3144 bnx2_tx_int(bp, bnapi, 0);
3052 3145
3053 if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) 3146 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3054 work_done += bnx2_rx_int(bp, bnapi, budget - work_done); 3147 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3055 3148
3056 return work_done; 3149 return work_done;
3057} 3150}
3058 3151
3152static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3153{
3154 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3155 struct bnx2 *bp = bnapi->bp;
3156 int work_done = 0;
3157 struct status_block_msix *sblk = bnapi->status_blk.msix;
3158
3159 while (1) {
3160 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3161 if (unlikely(work_done >= budget))
3162 break;
3163
3164 bnapi->last_status_idx = sblk->status_idx;
3165 /* status idx must be read before checking for more work. */
3166 rmb();
3167 if (likely(!bnx2_has_fast_work(bnapi))) {
3168
3169 netif_rx_complete(bp->dev, napi);
3170 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3171 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3172 bnapi->last_status_idx);
3173 break;
3174 }
3175 }
3176 return work_done;
3177}
3178
3059static int bnx2_poll(struct napi_struct *napi, int budget) 3179static int bnx2_poll(struct napi_struct *napi, int budget)
3060{ 3180{
3061 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); 3181 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3062 struct bnx2 *bp = bnapi->bp; 3182 struct bnx2 *bp = bnapi->bp;
3063 int work_done = 0; 3183 int work_done = 0;
3064 struct status_block *sblk = bnapi->status_blk; 3184 struct status_block *sblk = bnapi->status_blk.msi;
3065 3185
3066 while (1) { 3186 while (1) {
3187 bnx2_poll_link(bp, bnapi);
3188
3067 work_done = bnx2_poll_work(bp, bnapi, work_done, budget); 3189 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3068 3190
3069 if (unlikely(work_done >= budget)) 3191 if (unlikely(work_done >= budget))
@@ -3106,6 +3228,7 @@ bnx2_set_rx_mode(struct net_device *dev)
3106{ 3228{
3107 struct bnx2 *bp = netdev_priv(dev); 3229 struct bnx2 *bp = netdev_priv(dev);
3108 u32 rx_mode, sort_mode; 3230 u32 rx_mode, sort_mode;
3231 struct dev_addr_list *uc_ptr;
3109 int i; 3232 int i;
3110 3233
3111 spin_lock_bh(&bp->phy_lock); 3234 spin_lock_bh(&bp->phy_lock);
@@ -3161,6 +3284,25 @@ bnx2_set_rx_mode(struct net_device *dev)
3161 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; 3284 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3162 } 3285 }
3163 3286
3287 uc_ptr = NULL;
3288 if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3289 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3290 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3291 BNX2_RPM_SORT_USER0_PROM_VLAN;
3292 } else if (!(dev->flags & IFF_PROMISC)) {
3293 uc_ptr = dev->uc_list;
3294
3295 /* Add all entries into to the match filter list */
3296 for (i = 0; i < dev->uc_count; i++) {
3297 bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3298 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3299 sort_mode |= (1 <<
3300 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3301 uc_ptr = uc_ptr->next;
3302 }
3303
3304 }
3305
3164 if (rx_mode != bp->rx_mode) { 3306 if (rx_mode != bp->rx_mode) {
3165 bp->rx_mode = rx_mode; 3307 bp->rx_mode = rx_mode;
3166 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); 3308 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
@@ -3213,7 +3355,7 @@ load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3213} 3355}
3214 3356
3215static int 3357static int
3216load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) 3358load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3217{ 3359{
3218 u32 offset; 3360 u32 offset;
3219 u32 val; 3361 u32 val;
@@ -3297,7 +3439,6 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
3297static int 3439static int
3298bnx2_init_cpus(struct bnx2 *bp) 3440bnx2_init_cpus(struct bnx2 *bp)
3299{ 3441{
3300 struct cpu_reg cpu_reg;
3301 struct fw_info *fw; 3442 struct fw_info *fw;
3302 int rc, rv2p_len; 3443 int rc, rv2p_len;
3303 void *text, *rv2p; 3444 void *text, *rv2p;
@@ -3333,122 +3474,57 @@ bnx2_init_cpus(struct bnx2 *bp)
3333 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2); 3474 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3334 3475
3335 /* Initialize the RX Processor. */ 3476 /* Initialize the RX Processor. */
3336 cpu_reg.mode = BNX2_RXP_CPU_MODE;
3337 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3338 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3339 cpu_reg.state = BNX2_RXP_CPU_STATE;
3340 cpu_reg.state_value_clear = 0xffffff;
3341 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3342 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3343 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3344 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3345 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3346 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3347 cpu_reg.mips_view_base = 0x8000000;
3348
3349 if (CHIP_NUM(bp) == CHIP_NUM_5709) 3477 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3350 fw = &bnx2_rxp_fw_09; 3478 fw = &bnx2_rxp_fw_09;
3351 else 3479 else
3352 fw = &bnx2_rxp_fw_06; 3480 fw = &bnx2_rxp_fw_06;
3353 3481
3354 fw->text = text; 3482 fw->text = text;
3355 rc = load_cpu_fw(bp, &cpu_reg, fw); 3483 rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3356 if (rc) 3484 if (rc)
3357 goto init_cpu_err; 3485 goto init_cpu_err;
3358 3486
3359 /* Initialize the TX Processor. */ 3487 /* Initialize the TX Processor. */
3360 cpu_reg.mode = BNX2_TXP_CPU_MODE;
3361 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3362 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3363 cpu_reg.state = BNX2_TXP_CPU_STATE;
3364 cpu_reg.state_value_clear = 0xffffff;
3365 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3366 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3367 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3368 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3369 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3370 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3371 cpu_reg.mips_view_base = 0x8000000;
3372
3373 if (CHIP_NUM(bp) == CHIP_NUM_5709) 3488 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3374 fw = &bnx2_txp_fw_09; 3489 fw = &bnx2_txp_fw_09;
3375 else 3490 else
3376 fw = &bnx2_txp_fw_06; 3491 fw = &bnx2_txp_fw_06;
3377 3492
3378 fw->text = text; 3493 fw->text = text;
3379 rc = load_cpu_fw(bp, &cpu_reg, fw); 3494 rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3380 if (rc) 3495 if (rc)
3381 goto init_cpu_err; 3496 goto init_cpu_err;
3382 3497
3383 /* Initialize the TX Patch-up Processor. */ 3498 /* Initialize the TX Patch-up Processor. */
3384 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3385 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3386 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3387 cpu_reg.state = BNX2_TPAT_CPU_STATE;
3388 cpu_reg.state_value_clear = 0xffffff;
3389 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3390 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3391 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3392 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3393 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3394 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3395 cpu_reg.mips_view_base = 0x8000000;
3396
3397 if (CHIP_NUM(bp) == CHIP_NUM_5709) 3499 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3398 fw = &bnx2_tpat_fw_09; 3500 fw = &bnx2_tpat_fw_09;
3399 else 3501 else
3400 fw = &bnx2_tpat_fw_06; 3502 fw = &bnx2_tpat_fw_06;
3401 3503
3402 fw->text = text; 3504 fw->text = text;
3403 rc = load_cpu_fw(bp, &cpu_reg, fw); 3505 rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3404 if (rc) 3506 if (rc)
3405 goto init_cpu_err; 3507 goto init_cpu_err;
3406 3508
3407 /* Initialize the Completion Processor. */ 3509 /* Initialize the Completion Processor. */
3408 cpu_reg.mode = BNX2_COM_CPU_MODE;
3409 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3410 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3411 cpu_reg.state = BNX2_COM_CPU_STATE;
3412 cpu_reg.state_value_clear = 0xffffff;
3413 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3414 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3415 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3416 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3417 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3418 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3419 cpu_reg.mips_view_base = 0x8000000;
3420
3421 if (CHIP_NUM(bp) == CHIP_NUM_5709) 3510 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3422 fw = &bnx2_com_fw_09; 3511 fw = &bnx2_com_fw_09;
3423 else 3512 else
3424 fw = &bnx2_com_fw_06; 3513 fw = &bnx2_com_fw_06;
3425 3514
3426 fw->text = text; 3515 fw->text = text;
3427 rc = load_cpu_fw(bp, &cpu_reg, fw); 3516 rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3428 if (rc) 3517 if (rc)
3429 goto init_cpu_err; 3518 goto init_cpu_err;
3430 3519
3431 /* Initialize the Command Processor. */ 3520 /* Initialize the Command Processor. */
3432 cpu_reg.mode = BNX2_CP_CPU_MODE;
3433 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3434 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3435 cpu_reg.state = BNX2_CP_CPU_STATE;
3436 cpu_reg.state_value_clear = 0xffffff;
3437 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3438 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3439 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3440 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3441 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3442 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3443 cpu_reg.mips_view_base = 0x8000000;
3444
3445 if (CHIP_NUM(bp) == CHIP_NUM_5709) 3521 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3446 fw = &bnx2_cp_fw_09; 3522 fw = &bnx2_cp_fw_09;
3447 else 3523 else
3448 fw = &bnx2_cp_fw_06; 3524 fw = &bnx2_cp_fw_06;
3449 3525
3450 fw->text = text; 3526 fw->text = text;
3451 rc = load_cpu_fw(bp, &cpu_reg, fw); 3527 rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3452 3528
3453init_cpu_err: 3529init_cpu_err:
3454 vfree(text); 3530 vfree(text);
@@ -3511,7 +3587,7 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3511 bp->autoneg = autoneg; 3587 bp->autoneg = autoneg;
3512 bp->advertising = advertising; 3588 bp->advertising = advertising;
3513 3589
3514 bnx2_set_mac_addr(bp); 3590 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3515 3591
3516 val = REG_RD(bp, BNX2_EMAC_MODE); 3592 val = REG_RD(bp, BNX2_EMAC_MODE);
3517 3593
@@ -3562,7 +3638,8 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3562 } 3638 }
3563 3639
3564 if (!(bp->flags & BNX2_FLAG_NO_WOL)) 3640 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3565 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0); 3641 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3642 1, 0);
3566 3643
3567 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 3644 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3568 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || 3645 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
@@ -4203,35 +4280,43 @@ nvram_write_end:
4203} 4280}
4204 4281
4205static void 4282static void
4206bnx2_init_remote_phy(struct bnx2 *bp) 4283bnx2_init_fw_cap(struct bnx2 *bp)
4207{ 4284{
4208 u32 val; 4285 u32 val, sig = 0;
4209 4286
4210 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP; 4287 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4211 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) 4288 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4212 return; 4289
4290 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4291 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4213 4292
4214 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB); 4293 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4215 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) 4294 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4216 return; 4295 return;
4217 4296
4218 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) { 4297 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4298 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4299 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4300 }
4301
4302 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4303 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4304 u32 link;
4305
4219 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; 4306 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4220 4307
4221 val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); 4308 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4222 if (val & BNX2_LINK_STATUS_SERDES_LINK) 4309 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4223 bp->phy_port = PORT_FIBRE; 4310 bp->phy_port = PORT_FIBRE;
4224 else 4311 else
4225 bp->phy_port = PORT_TP; 4312 bp->phy_port = PORT_TP;
4226 4313
4227 if (netif_running(bp->dev)) { 4314 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4228 u32 sig; 4315 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4229
4230 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4231 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4232 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4233 }
4234 } 4316 }
4317
4318 if (netif_running(bp->dev) && sig)
4319 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4235} 4320}
4236 4321
4237static void 4322static void
@@ -4261,7 +4346,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4261 udelay(5); 4346 udelay(5);
4262 4347
4263 /* Wait for the firmware to tell us it is ok to issue a reset. */ 4348 /* Wait for the firmware to tell us it is ok to issue a reset. */
4264 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1); 4349 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4265 4350
4266 /* Deposit a driver reset signature so the firmware knows that 4351 /* Deposit a driver reset signature so the firmware knows that
4267 * this is a soft reset. */ 4352 * this is a soft reset. */
@@ -4322,13 +4407,13 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4322 } 4407 }
4323 4408
4324 /* Wait for the firmware to finish its initialization. */ 4409 /* Wait for the firmware to finish its initialization. */
4325 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0); 4410 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4326 if (rc) 4411 if (rc)
4327 return rc; 4412 return rc;
4328 4413
4329 spin_lock_bh(&bp->phy_lock); 4414 spin_lock_bh(&bp->phy_lock);
4330 old_port = bp->phy_port; 4415 old_port = bp->phy_port;
4331 bnx2_init_remote_phy(bp); 4416 bnx2_init_fw_cap(bp);
4332 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) && 4417 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4333 old_port != bp->phy_port) 4418 old_port != bp->phy_port)
4334 bnx2_set_default_remote_link(bp); 4419 bnx2_set_default_remote_link(bp);
@@ -4412,7 +4497,7 @@ bnx2_init_chip(struct bnx2 *bp)
4412 4497
4413 bnx2_init_nvram(bp); 4498 bnx2_init_nvram(bp);
4414 4499
4415 bnx2_set_mac_addr(bp); 4500 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4416 4501
4417 val = REG_RD(bp, BNX2_MQ_CONFIG); 4502 val = REG_RD(bp, BNX2_MQ_CONFIG);
4418 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; 4503 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
@@ -4498,15 +4583,25 @@ bnx2_init_chip(struct bnx2 *bp)
4498 BNX2_HC_CONFIG_COLLECT_STATS; 4583 BNX2_HC_CONFIG_COLLECT_STATS;
4499 } 4584 }
4500 4585
4501 if (bp->flags & BNX2_FLAG_USING_MSIX) { 4586 if (bp->irq_nvecs > 1) {
4502 u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4503 BNX2_HC_SB_CONFIG_1;
4504
4505 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, 4587 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4506 BNX2_HC_MSIX_BIT_VECTOR_VAL); 4588 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4507 4589
4590 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4591 }
4592
4593 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4594 val |= BNX2_HC_CONFIG_ONE_SHOT;
4595
4596 REG_WR(bp, BNX2_HC_CONFIG, val);
4597
4598 for (i = 1; i < bp->irq_nvecs; i++) {
4599 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4600 BNX2_HC_SB_CONFIG_1;
4601
4508 REG_WR(bp, base, 4602 REG_WR(bp, base,
4509 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE | 4603 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4604 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4510 BNX2_HC_SB_CONFIG_1_ONE_SHOT); 4605 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4511 4606
4512 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, 4607 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
@@ -4516,13 +4611,13 @@ bnx2_init_chip(struct bnx2 *bp)
4516 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF, 4611 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4517 (bp->tx_ticks_int << 16) | bp->tx_ticks); 4612 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4518 4613
4519 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; 4614 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4520 } 4615 (bp->rx_quick_cons_trip_int << 16) |
4616 bp->rx_quick_cons_trip);
4521 4617
4522 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) 4618 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4523 val |= BNX2_HC_CONFIG_ONE_SHOT; 4619 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4524 4620 }
4525 REG_WR(bp, BNX2_HC_CONFIG, val);
4526 4621
4527 /* Clear internal stats counters. */ 4622 /* Clear internal stats counters. */
4528 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); 4623 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
@@ -4538,7 +4633,7 @@ bnx2_init_chip(struct bnx2 *bp)
4538 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); 4633 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4539 } 4634 }
4540 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, 4635 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4541 0); 4636 1, 0);
4542 4637
4543 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT); 4638 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4544 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS); 4639 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
@@ -4554,23 +4649,27 @@ static void
4554bnx2_clear_ring_states(struct bnx2 *bp) 4649bnx2_clear_ring_states(struct bnx2 *bp)
4555{ 4650{
4556 struct bnx2_napi *bnapi; 4651 struct bnx2_napi *bnapi;
4652 struct bnx2_tx_ring_info *txr;
4653 struct bnx2_rx_ring_info *rxr;
4557 int i; 4654 int i;
4558 4655
4559 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { 4656 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4560 bnapi = &bp->bnx2_napi[i]; 4657 bnapi = &bp->bnx2_napi[i];
4658 txr = &bnapi->tx_ring;
4659 rxr = &bnapi->rx_ring;
4561 4660
4562 bnapi->tx_cons = 0; 4661 txr->tx_cons = 0;
4563 bnapi->hw_tx_cons = 0; 4662 txr->hw_tx_cons = 0;
4564 bnapi->rx_prod_bseq = 0; 4663 rxr->rx_prod_bseq = 0;
4565 bnapi->rx_prod = 0; 4664 rxr->rx_prod = 0;
4566 bnapi->rx_cons = 0; 4665 rxr->rx_cons = 0;
4567 bnapi->rx_pg_prod = 0; 4666 rxr->rx_pg_prod = 0;
4568 bnapi->rx_pg_cons = 0; 4667 rxr->rx_pg_cons = 0;
4569 } 4668 }
4570} 4669}
4571 4670
4572static void 4671static void
4573bnx2_init_tx_context(struct bnx2 *bp, u32 cid) 4672bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4574{ 4673{
4575 u32 val, offset0, offset1, offset2, offset3; 4674 u32 val, offset0, offset1, offset2, offset3;
4576 u32 cid_addr = GET_CID_ADDR(cid); 4675 u32 cid_addr = GET_CID_ADDR(cid);
@@ -4592,43 +4691,43 @@ bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4592 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4691 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4593 bnx2_ctx_wr(bp, cid_addr, offset1, val); 4692 bnx2_ctx_wr(bp, cid_addr, offset1, val);
4594 4693
4595 val = (u64) bp->tx_desc_mapping >> 32; 4694 val = (u64) txr->tx_desc_mapping >> 32;
4596 bnx2_ctx_wr(bp, cid_addr, offset2, val); 4695 bnx2_ctx_wr(bp, cid_addr, offset2, val);
4597 4696
4598 val = (u64) bp->tx_desc_mapping & 0xffffffff; 4697 val = (u64) txr->tx_desc_mapping & 0xffffffff;
4599 bnx2_ctx_wr(bp, cid_addr, offset3, val); 4698 bnx2_ctx_wr(bp, cid_addr, offset3, val);
4600} 4699}
4601 4700
4602static void 4701static void
4603bnx2_init_tx_ring(struct bnx2 *bp) 4702bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4604{ 4703{
4605 struct tx_bd *txbd; 4704 struct tx_bd *txbd;
4606 u32 cid = TX_CID; 4705 u32 cid = TX_CID;
4607 struct bnx2_napi *bnapi; 4706 struct bnx2_napi *bnapi;
4707 struct bnx2_tx_ring_info *txr;
4608 4708
4609 bp->tx_vec = 0; 4709 bnapi = &bp->bnx2_napi[ring_num];
4610 if (bp->flags & BNX2_FLAG_USING_MSIX) { 4710 txr = &bnapi->tx_ring;
4611 cid = TX_TSS_CID; 4711
4612 bp->tx_vec = BNX2_TX_VEC; 4712 if (ring_num == 0)
4613 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM | 4713 cid = TX_CID;
4614 (TX_TSS_CID << 7)); 4714 else
4615 } 4715 cid = TX_TSS_CID + ring_num - 1;
4616 bnapi = &bp->bnx2_napi[bp->tx_vec];
4617 4716
4618 bp->tx_wake_thresh = bp->tx_ring_size / 2; 4717 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4619 4718
4620 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT]; 4719 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4621 4720
4622 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32; 4721 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4623 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff; 4722 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4624 4723
4625 bp->tx_prod = 0; 4724 txr->tx_prod = 0;
4626 bp->tx_prod_bseq = 0; 4725 txr->tx_prod_bseq = 0;
4627 4726
4628 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; 4727 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4629 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; 4728 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4630 4729
4631 bnx2_init_tx_context(bp, cid); 4730 bnx2_init_tx_context(bp, cid, txr);
4632} 4731}
4633 4732
4634static void 4733static void
@@ -4656,17 +4755,25 @@ bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4656} 4755}
4657 4756
4658static void 4757static void
4659bnx2_init_rx_ring(struct bnx2 *bp) 4758bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4660{ 4759{
4661 int i; 4760 int i;
4662 u16 prod, ring_prod; 4761 u16 prod, ring_prod;
4663 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID); 4762 u32 cid, rx_cid_addr, val;
4664 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 4763 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4764 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4665 4765
4666 bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping, 4766 if (ring_num == 0)
4767 cid = RX_CID;
4768 else
4769 cid = RX_RSS_CID + ring_num - 1;
4770
4771 rx_cid_addr = GET_CID_ADDR(cid);
4772
4773 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4667 bp->rx_buf_use_size, bp->rx_max_ring); 4774 bp->rx_buf_use_size, bp->rx_max_ring);
4668 4775
4669 bnx2_init_rx_context0(bp); 4776 bnx2_init_rx_context(bp, cid);
4670 4777
4671 if (CHIP_NUM(bp) == CHIP_NUM_5709) { 4778 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4672 val = REG_RD(bp, BNX2_MQ_MAP_L2_5); 4779 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
@@ -4675,54 +4782,101 @@ bnx2_init_rx_ring(struct bnx2 *bp)
4675 4782
4676 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); 4783 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4677 if (bp->rx_pg_ring_size) { 4784 if (bp->rx_pg_ring_size) {
4678 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring, 4785 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4679 bp->rx_pg_desc_mapping, 4786 rxr->rx_pg_desc_mapping,
4680 PAGE_SIZE, bp->rx_max_pg_ring); 4787 PAGE_SIZE, bp->rx_max_pg_ring);
4681 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; 4788 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4682 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); 4789 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4683 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, 4790 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4684 BNX2_L2CTX_RBDC_JUMBO_KEY); 4791 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4685 4792
4686 val = (u64) bp->rx_pg_desc_mapping[0] >> 32; 4793 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4687 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); 4794 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4688 4795
4689 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff; 4796 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4690 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); 4797 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4691 4798
4692 if (CHIP_NUM(bp) == CHIP_NUM_5709) 4799 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4693 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); 4800 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4694 } 4801 }
4695 4802
4696 val = (u64) bp->rx_desc_mapping[0] >> 32; 4803 val = (u64) rxr->rx_desc_mapping[0] >> 32;
4697 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); 4804 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4698 4805
4699 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff; 4806 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4700 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); 4807 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4701 4808
4702 ring_prod = prod = bnapi->rx_pg_prod; 4809 ring_prod = prod = rxr->rx_pg_prod;
4703 for (i = 0; i < bp->rx_pg_ring_size; i++) { 4810 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4704 if (bnx2_alloc_rx_page(bp, ring_prod) < 0) 4811 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4705 break; 4812 break;
4706 prod = NEXT_RX_BD(prod); 4813 prod = NEXT_RX_BD(prod);
4707 ring_prod = RX_PG_RING_IDX(prod); 4814 ring_prod = RX_PG_RING_IDX(prod);
4708 } 4815 }
4709 bnapi->rx_pg_prod = prod; 4816 rxr->rx_pg_prod = prod;
4710 4817
4711 ring_prod = prod = bnapi->rx_prod; 4818 ring_prod = prod = rxr->rx_prod;
4712 for (i = 0; i < bp->rx_ring_size; i++) { 4819 for (i = 0; i < bp->rx_ring_size; i++) {
4713 if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) { 4820 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4714 break; 4821 break;
4715 }
4716 prod = NEXT_RX_BD(prod); 4822 prod = NEXT_RX_BD(prod);
4717 ring_prod = RX_RING_IDX(prod); 4823 ring_prod = RX_RING_IDX(prod);
4718 } 4824 }
4719 bnapi->rx_prod = prod; 4825 rxr->rx_prod = prod;
4826
4827 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4828 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4829 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4720 4830
4721 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX, 4831 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4722 bnapi->rx_pg_prod); 4832 REG_WR16(bp, rxr->rx_bidx_addr, prod);
4723 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4724 4833
4725 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq); 4834 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4835}
4836
4837static void
4838bnx2_init_all_rings(struct bnx2 *bp)
4839{
4840 int i;
4841 u32 val;
4842
4843 bnx2_clear_ring_states(bp);
4844
4845 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4846 for (i = 0; i < bp->num_tx_rings; i++)
4847 bnx2_init_tx_ring(bp, i);
4848
4849 if (bp->num_tx_rings > 1)
4850 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4851 (TX_TSS_CID << 7));
4852
4853 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4854 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4855
4856 for (i = 0; i < bp->num_rx_rings; i++)
4857 bnx2_init_rx_ring(bp, i);
4858
4859 if (bp->num_rx_rings > 1) {
4860 u32 tbl_32;
4861 u8 *tbl = (u8 *) &tbl_32;
4862
4863 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4864 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4865
4866 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4867 tbl[i % 4] = i % (bp->num_rx_rings - 1);
4868 if ((i % 4) == 3)
4869 bnx2_reg_wr_ind(bp,
4870 BNX2_RXP_SCRATCH_RSS_TBL + i,
4871 cpu_to_be32(tbl_32));
4872 }
4873
4874 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4875 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4876
4877 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4878
4879 }
4726} 4880}
4727 4881
4728static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size) 4882static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
@@ -4750,12 +4904,12 @@ bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4750 u32 rx_size, rx_space, jumbo_size; 4904 u32 rx_size, rx_space, jumbo_size;
4751 4905
4752 /* 8 for CRC and VLAN */ 4906 /* 8 for CRC and VLAN */
4753 rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8; 4907 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4754 4908
4755 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD + 4909 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4756 sizeof(struct skb_shared_info); 4910 sizeof(struct skb_shared_info);
4757 4911
4758 bp->rx_copy_thresh = RX_COPY_THRESH; 4912 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
4759 bp->rx_pg_ring_size = 0; 4913 bp->rx_pg_ring_size = 0;
4760 bp->rx_max_pg_ring = 0; 4914 bp->rx_max_pg_ring = 0;
4761 bp->rx_max_pg_ring_idx = 0; 4915 bp->rx_max_pg_ring_idx = 0;
@@ -4770,14 +4924,14 @@ bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4770 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, 4924 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4771 MAX_RX_PG_RINGS); 4925 MAX_RX_PG_RINGS);
4772 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1; 4926 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4773 rx_size = RX_COPY_THRESH + bp->rx_offset; 4927 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
4774 bp->rx_copy_thresh = 0; 4928 bp->rx_copy_thresh = 0;
4775 } 4929 }
4776 4930
4777 bp->rx_buf_use_size = rx_size; 4931 bp->rx_buf_use_size = rx_size;
4778 /* hw alignment */ 4932 /* hw alignment */
4779 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN; 4933 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4780 bp->rx_jumbo_thresh = rx_size - bp->rx_offset; 4934 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
4781 bp->rx_ring_size = size; 4935 bp->rx_ring_size = size;
4782 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS); 4936 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4783 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1; 4937 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
@@ -4788,36 +4942,42 @@ bnx2_free_tx_skbs(struct bnx2 *bp)
4788{ 4942{
4789 int i; 4943 int i;
4790 4944
4791 if (bp->tx_buf_ring == NULL) 4945 for (i = 0; i < bp->num_tx_rings; i++) {
4792 return; 4946 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
4793 4947 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
4794 for (i = 0; i < TX_DESC_CNT; ) { 4948 int j;
4795 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4796 struct sk_buff *skb = tx_buf->skb;
4797 int j, last;
4798 4949
4799 if (skb == NULL) { 4950 if (txr->tx_buf_ring == NULL)
4800 i++;
4801 continue; 4951 continue;
4802 }
4803 4952
4804 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping), 4953 for (j = 0; j < TX_DESC_CNT; ) {
4954 struct sw_bd *tx_buf = &txr->tx_buf_ring[j];
4955 struct sk_buff *skb = tx_buf->skb;
4956 int k, last;
4957
4958 if (skb == NULL) {
4959 j++;
4960 continue;
4961 }
4962
4963 pci_unmap_single(bp->pdev,
4964 pci_unmap_addr(tx_buf, mapping),
4805 skb_headlen(skb), PCI_DMA_TODEVICE); 4965 skb_headlen(skb), PCI_DMA_TODEVICE);
4806 4966
4807 tx_buf->skb = NULL; 4967 tx_buf->skb = NULL;
4808 4968
4809 last = skb_shinfo(skb)->nr_frags; 4969 last = skb_shinfo(skb)->nr_frags;
4810 for (j = 0; j < last; j++) { 4970 for (k = 0; k < last; k++) {
4811 tx_buf = &bp->tx_buf_ring[i + j + 1]; 4971 tx_buf = &txr->tx_buf_ring[j + k + 1];
4812 pci_unmap_page(bp->pdev, 4972 pci_unmap_page(bp->pdev,
4813 pci_unmap_addr(tx_buf, mapping), 4973 pci_unmap_addr(tx_buf, mapping),
4814 skb_shinfo(skb)->frags[j].size, 4974 skb_shinfo(skb)->frags[j].size,
4815 PCI_DMA_TODEVICE); 4975 PCI_DMA_TODEVICE);
4976 }
4977 dev_kfree_skb(skb);
4978 j += k + 1;
4816 } 4979 }
4817 dev_kfree_skb(skb);
4818 i += j + 1;
4819 } 4980 }
4820
4821} 4981}
4822 4982
4823static void 4983static void
@@ -4825,25 +4985,33 @@ bnx2_free_rx_skbs(struct bnx2 *bp)
4825{ 4985{
4826 int i; 4986 int i;
4827 4987
4828 if (bp->rx_buf_ring == NULL) 4988 for (i = 0; i < bp->num_rx_rings; i++) {
4829 return; 4989 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
4990 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4991 int j;
4830 4992
4831 for (i = 0; i < bp->rx_max_ring_idx; i++) { 4993 if (rxr->rx_buf_ring == NULL)
4832 struct sw_bd *rx_buf = &bp->rx_buf_ring[i]; 4994 return;
4833 struct sk_buff *skb = rx_buf->skb;
4834 4995
4835 if (skb == NULL) 4996 for (j = 0; j < bp->rx_max_ring_idx; j++) {
4836 continue; 4997 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
4998 struct sk_buff *skb = rx_buf->skb;
4837 4999
4838 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping), 5000 if (skb == NULL)
4839 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); 5001 continue;
4840 5002
4841 rx_buf->skb = NULL; 5003 pci_unmap_single(bp->pdev,
5004 pci_unmap_addr(rx_buf, mapping),
5005 bp->rx_buf_use_size,
5006 PCI_DMA_FROMDEVICE);
4842 5007
4843 dev_kfree_skb(skb); 5008 rx_buf->skb = NULL;
5009
5010 dev_kfree_skb(skb);
5011 }
5012 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5013 bnx2_free_rx_page(bp, rxr, j);
4844 } 5014 }
4845 for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4846 bnx2_free_rx_page(bp, i);
4847} 5015}
4848 5016
4849static void 5017static void
@@ -4866,14 +5034,12 @@ bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4866 if ((rc = bnx2_init_chip(bp)) != 0) 5034 if ((rc = bnx2_init_chip(bp)) != 0)
4867 return rc; 5035 return rc;
4868 5036
4869 bnx2_clear_ring_states(bp); 5037 bnx2_init_all_rings(bp);
4870 bnx2_init_tx_ring(bp);
4871 bnx2_init_rx_ring(bp);
4872 return 0; 5038 return 0;
4873} 5039}
4874 5040
4875static int 5041static int
4876bnx2_init_nic(struct bnx2 *bp) 5042bnx2_init_nic(struct bnx2 *bp, int reset_phy)
4877{ 5043{
4878 int rc; 5044 int rc;
4879 5045
@@ -4881,7 +5047,7 @@ bnx2_init_nic(struct bnx2 *bp)
4881 return rc; 5047 return rc;
4882 5048
4883 spin_lock_bh(&bp->phy_lock); 5049 spin_lock_bh(&bp->phy_lock);
4884 bnx2_init_phy(bp); 5050 bnx2_init_phy(bp, reset_phy);
4885 bnx2_set_link(bp); 5051 bnx2_set_link(bp);
4886 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 5052 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
4887 bnx2_remote_phy_event(bp); 5053 bnx2_remote_phy_event(bp);
@@ -5141,11 +5307,13 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5141 struct l2_fhdr *rx_hdr; 5307 struct l2_fhdr *rx_hdr;
5142 int ret = -ENODEV; 5308 int ret = -ENODEV;
5143 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; 5309 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5310 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5311 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5144 5312
5145 tx_napi = bnapi; 5313 tx_napi = bnapi;
5146 if (bp->flags & BNX2_FLAG_USING_MSIX)
5147 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
5148 5314
5315 txr = &tx_napi->tx_ring;
5316 rxr = &bnapi->rx_ring;
5149 if (loopback_mode == BNX2_MAC_LOOPBACK) { 5317 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5150 bp->loopback = MAC_LOOPBACK; 5318 bp->loopback = MAC_LOOPBACK;
5151 bnx2_set_mac_loopback(bp); 5319 bnx2_set_mac_loopback(bp);
@@ -5183,7 +5351,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5183 5351
5184 num_pkts = 0; 5352 num_pkts = 0;
5185 5353
5186 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)]; 5354 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5187 5355
5188 txbd->tx_bd_haddr_hi = (u64) map >> 32; 5356 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5189 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; 5357 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
@@ -5191,11 +5359,11 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5191 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; 5359 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5192 5360
5193 num_pkts++; 5361 num_pkts++;
5194 bp->tx_prod = NEXT_TX_BD(bp->tx_prod); 5362 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5195 bp->tx_prod_bseq += pkt_size; 5363 txr->tx_prod_bseq += pkt_size;
5196 5364
5197 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod); 5365 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5198 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); 5366 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5199 5367
5200 udelay(100); 5368 udelay(100);
5201 5369
@@ -5209,7 +5377,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5209 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE); 5377 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5210 dev_kfree_skb(skb); 5378 dev_kfree_skb(skb);
5211 5379
5212 if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod) 5380 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5213 goto loopback_test_done; 5381 goto loopback_test_done;
5214 5382
5215 rx_idx = bnx2_get_hw_rx_cons(bnapi); 5383 rx_idx = bnx2_get_hw_rx_cons(bnapi);
@@ -5217,11 +5385,11 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5217 goto loopback_test_done; 5385 goto loopback_test_done;
5218 } 5386 }
5219 5387
5220 rx_buf = &bp->rx_buf_ring[rx_start_idx]; 5388 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5221 rx_skb = rx_buf->skb; 5389 rx_skb = rx_buf->skb;
5222 5390
5223 rx_hdr = (struct l2_fhdr *) rx_skb->data; 5391 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5224 skb_reserve(rx_skb, bp->rx_offset); 5392 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5225 5393
5226 pci_dma_sync_single_for_cpu(bp->pdev, 5394 pci_dma_sync_single_for_cpu(bp->pdev,
5227 pci_unmap_addr(rx_buf, mapping), 5395 pci_unmap_addr(rx_buf, mapping),
@@ -5269,7 +5437,7 @@ bnx2_test_loopback(struct bnx2 *bp)
5269 5437
5270 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); 5438 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5271 spin_lock_bh(&bp->phy_lock); 5439 spin_lock_bh(&bp->phy_lock);
5272 bnx2_init_phy(bp); 5440 bnx2_init_phy(bp, 1);
5273 spin_unlock_bh(&bp->phy_lock); 5441 spin_unlock_bh(&bp->phy_lock);
5274 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK)) 5442 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5275 rc |= BNX2_MAC_LOOPBACK_FAILED; 5443 rc |= BNX2_MAC_LOOPBACK_FAILED;
@@ -5531,7 +5699,6 @@ bnx2_restart_timer:
5531static int 5699static int
5532bnx2_request_irq(struct bnx2 *bp) 5700bnx2_request_irq(struct bnx2 *bp)
5533{ 5701{
5534 struct net_device *dev = bp->dev;
5535 unsigned long flags; 5702 unsigned long flags;
5536 struct bnx2_irq *irq; 5703 struct bnx2_irq *irq;
5537 int rc = 0, i; 5704 int rc = 0, i;
@@ -5544,7 +5711,7 @@ bnx2_request_irq(struct bnx2 *bp)
5544 for (i = 0; i < bp->irq_nvecs; i++) { 5711 for (i = 0; i < bp->irq_nvecs; i++) {
5545 irq = &bp->irq_tbl[i]; 5712 irq = &bp->irq_tbl[i];
5546 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 5713 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5547 dev); 5714 &bp->bnx2_napi[i]);
5548 if (rc) 5715 if (rc)
5549 break; 5716 break;
5550 irq->requested = 1; 5717 irq->requested = 1;
@@ -5555,14 +5722,13 @@ bnx2_request_irq(struct bnx2 *bp)
5555static void 5722static void
5556bnx2_free_irq(struct bnx2 *bp) 5723bnx2_free_irq(struct bnx2 *bp)
5557{ 5724{
5558 struct net_device *dev = bp->dev;
5559 struct bnx2_irq *irq; 5725 struct bnx2_irq *irq;
5560 int i; 5726 int i;
5561 5727
5562 for (i = 0; i < bp->irq_nvecs; i++) { 5728 for (i = 0; i < bp->irq_nvecs; i++) {
5563 irq = &bp->irq_tbl[i]; 5729 irq = &bp->irq_tbl[i];
5564 if (irq->requested) 5730 if (irq->requested)
5565 free_irq(irq->vector, dev); 5731 free_irq(irq->vector, &bp->bnx2_napi[i]);
5566 irq->requested = 0; 5732 irq->requested = 0;
5567 } 5733 }
5568 if (bp->flags & BNX2_FLAG_USING_MSI) 5734 if (bp->flags & BNX2_FLAG_USING_MSI)
@@ -5574,7 +5740,7 @@ bnx2_free_irq(struct bnx2 *bp)
5574} 5740}
5575 5741
5576static void 5742static void
5577bnx2_enable_msix(struct bnx2 *bp) 5743bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5578{ 5744{
5579 int i, rc; 5745 int i, rc;
5580 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC]; 5746 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
@@ -5587,21 +5753,16 @@ bnx2_enable_msix(struct bnx2 *bp)
5587 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { 5753 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5588 msix_ent[i].entry = i; 5754 msix_ent[i].entry = i;
5589 msix_ent[i].vector = 0; 5755 msix_ent[i].vector = 0;
5756
5757 strcpy(bp->irq_tbl[i].name, bp->dev->name);
5758 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5590 } 5759 }
5591 5760
5592 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC); 5761 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5593 if (rc != 0) 5762 if (rc != 0)
5594 return; 5763 return;
5595 5764
5596 bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot; 5765 bp->irq_nvecs = msix_vecs;
5597 bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix;
5598
5599 strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name);
5600 strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base");
5601 strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name);
5602 strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5603
5604 bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
5605 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; 5766 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5606 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) 5767 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5607 bp->irq_tbl[i].vector = msix_ent[i].vector; 5768 bp->irq_tbl[i].vector = msix_ent[i].vector;
@@ -5610,13 +5771,16 @@ bnx2_enable_msix(struct bnx2 *bp)
5610static void 5771static void
5611bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) 5772bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5612{ 5773{
5774 int cpus = num_online_cpus();
5775 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5776
5613 bp->irq_tbl[0].handler = bnx2_interrupt; 5777 bp->irq_tbl[0].handler = bnx2_interrupt;
5614 strcpy(bp->irq_tbl[0].name, bp->dev->name); 5778 strcpy(bp->irq_tbl[0].name, bp->dev->name);
5615 bp->irq_nvecs = 1; 5779 bp->irq_nvecs = 1;
5616 bp->irq_tbl[0].vector = bp->pdev->irq; 5780 bp->irq_tbl[0].vector = bp->pdev->irq;
5617 5781
5618 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi) 5782 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5619 bnx2_enable_msix(bp); 5783 bnx2_enable_msix(bp, msix_vecs);
5620 5784
5621 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi && 5785 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5622 !(bp->flags & BNX2_FLAG_USING_MSIX)) { 5786 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
@@ -5631,6 +5795,11 @@ bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5631 bp->irq_tbl[0].vector = bp->pdev->irq; 5795 bp->irq_tbl[0].vector = bp->pdev->irq;
5632 } 5796 }
5633 } 5797 }
5798
5799 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5800 bp->dev->real_num_tx_queues = bp->num_tx_rings;
5801
5802 bp->num_rx_rings = bp->irq_nvecs;
5634} 5803}
5635 5804
5636/* Called with rtnl_lock */ 5805/* Called with rtnl_lock */
@@ -5645,29 +5814,19 @@ bnx2_open(struct net_device *dev)
5645 bnx2_set_power_state(bp, PCI_D0); 5814 bnx2_set_power_state(bp, PCI_D0);
5646 bnx2_disable_int(bp); 5815 bnx2_disable_int(bp);
5647 5816
5817 bnx2_setup_int_mode(bp, disable_msi);
5818 bnx2_napi_enable(bp);
5648 rc = bnx2_alloc_mem(bp); 5819 rc = bnx2_alloc_mem(bp);
5649 if (rc) 5820 if (rc)
5650 return rc; 5821 goto open_err;
5651 5822
5652 bnx2_setup_int_mode(bp, disable_msi);
5653 bnx2_napi_enable(bp);
5654 rc = bnx2_request_irq(bp); 5823 rc = bnx2_request_irq(bp);
5824 if (rc)
5825 goto open_err;
5655 5826
5656 if (rc) { 5827 rc = bnx2_init_nic(bp, 1);
5657 bnx2_napi_disable(bp); 5828 if (rc)
5658 bnx2_free_mem(bp); 5829 goto open_err;
5659 return rc;
5660 }
5661
5662 rc = bnx2_init_nic(bp);
5663
5664 if (rc) {
5665 bnx2_napi_disable(bp);
5666 bnx2_free_irq(bp);
5667 bnx2_free_skbs(bp);
5668 bnx2_free_mem(bp);
5669 return rc;
5670 }
5671 5830
5672 mod_timer(&bp->timer, jiffies + bp->current_interval); 5831 mod_timer(&bp->timer, jiffies + bp->current_interval);
5673 5832
@@ -5691,17 +5850,14 @@ bnx2_open(struct net_device *dev)
5691 5850
5692 bnx2_setup_int_mode(bp, 1); 5851 bnx2_setup_int_mode(bp, 1);
5693 5852
5694 rc = bnx2_init_nic(bp); 5853 rc = bnx2_init_nic(bp, 0);
5695 5854
5696 if (!rc) 5855 if (!rc)
5697 rc = bnx2_request_irq(bp); 5856 rc = bnx2_request_irq(bp);
5698 5857
5699 if (rc) { 5858 if (rc) {
5700 bnx2_napi_disable(bp);
5701 bnx2_free_skbs(bp);
5702 bnx2_free_mem(bp);
5703 del_timer_sync(&bp->timer); 5859 del_timer_sync(&bp->timer);
5704 return rc; 5860 goto open_err;
5705 } 5861 }
5706 bnx2_enable_int(bp); 5862 bnx2_enable_int(bp);
5707 } 5863 }
@@ -5711,9 +5867,16 @@ bnx2_open(struct net_device *dev)
5711 else if (bp->flags & BNX2_FLAG_USING_MSIX) 5867 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5712 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name); 5868 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5713 5869
5714 netif_start_queue(dev); 5870 netif_tx_start_all_queues(dev);
5715 5871
5716 return 0; 5872 return 0;
5873
5874open_err:
5875 bnx2_napi_disable(bp);
5876 bnx2_free_skbs(bp);
5877 bnx2_free_irq(bp);
5878 bnx2_free_mem(bp);
5879 return rc;
5717} 5880}
5718 5881
5719static void 5882static void
@@ -5726,7 +5889,7 @@ bnx2_reset_task(struct work_struct *work)
5726 5889
5727 bnx2_netif_stop(bp); 5890 bnx2_netif_stop(bp);
5728 5891
5729 bnx2_init_nic(bp); 5892 bnx2_init_nic(bp, 1);
5730 5893
5731 atomic_set(&bp->intr_sem, 1); 5894 atomic_set(&bp->intr_sem, 1);
5732 bnx2_netif_start(bp); 5895 bnx2_netif_start(bp);
@@ -5752,6 +5915,8 @@ bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5752 5915
5753 bp->vlgrp = vlgrp; 5916 bp->vlgrp = vlgrp;
5754 bnx2_set_rx_mode(dev); 5917 bnx2_set_rx_mode(dev);
5918 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
5919 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
5755 5920
5756 bnx2_netif_start(bp); 5921 bnx2_netif_start(bp);
5757} 5922}
@@ -5771,18 +5936,26 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5771 u32 len, vlan_tag_flags, last_frag, mss; 5936 u32 len, vlan_tag_flags, last_frag, mss;
5772 u16 prod, ring_prod; 5937 u16 prod, ring_prod;
5773 int i; 5938 int i;
5774 struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec]; 5939 struct bnx2_napi *bnapi;
5940 struct bnx2_tx_ring_info *txr;
5941 struct netdev_queue *txq;
5775 5942
5776 if (unlikely(bnx2_tx_avail(bp, bnapi) < 5943 /* Determine which tx ring we will be placed on */
5944 i = skb_get_queue_mapping(skb);
5945 bnapi = &bp->bnx2_napi[i];
5946 txr = &bnapi->tx_ring;
5947 txq = netdev_get_tx_queue(dev, i);
5948
5949 if (unlikely(bnx2_tx_avail(bp, txr) <
5777 (skb_shinfo(skb)->nr_frags + 1))) { 5950 (skb_shinfo(skb)->nr_frags + 1))) {
5778 netif_stop_queue(dev); 5951 netif_tx_stop_queue(txq);
5779 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n", 5952 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5780 dev->name); 5953 dev->name);
5781 5954
5782 return NETDEV_TX_BUSY; 5955 return NETDEV_TX_BUSY;
5783 } 5956 }
5784 len = skb_headlen(skb); 5957 len = skb_headlen(skb);
5785 prod = bp->tx_prod; 5958 prod = txr->tx_prod;
5786 ring_prod = TX_RING_IDX(prod); 5959 ring_prod = TX_RING_IDX(prod);
5787 5960
5788 vlan_tag_flags = 0; 5961 vlan_tag_flags = 0;
@@ -5844,11 +6017,11 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5844 6017
5845 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE); 6018 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5846 6019
5847 tx_buf = &bp->tx_buf_ring[ring_prod]; 6020 tx_buf = &txr->tx_buf_ring[ring_prod];
5848 tx_buf->skb = skb; 6021 tx_buf->skb = skb;
5849 pci_unmap_addr_set(tx_buf, mapping, mapping); 6022 pci_unmap_addr_set(tx_buf, mapping, mapping);
5850 6023
5851 txbd = &bp->tx_desc_ring[ring_prod]; 6024 txbd = &txr->tx_desc_ring[ring_prod];
5852 6025
5853 txbd->tx_bd_haddr_hi = (u64) mapping >> 32; 6026 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5854 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; 6027 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
@@ -5862,12 +6035,12 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5862 6035
5863 prod = NEXT_TX_BD(prod); 6036 prod = NEXT_TX_BD(prod);
5864 ring_prod = TX_RING_IDX(prod); 6037 ring_prod = TX_RING_IDX(prod);
5865 txbd = &bp->tx_desc_ring[ring_prod]; 6038 txbd = &txr->tx_desc_ring[ring_prod];
5866 6039
5867 len = frag->size; 6040 len = frag->size;
5868 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset, 6041 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5869 len, PCI_DMA_TODEVICE); 6042 len, PCI_DMA_TODEVICE);
5870 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod], 6043 pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod],
5871 mapping, mapping); 6044 mapping, mapping);
5872 6045
5873 txbd->tx_bd_haddr_hi = (u64) mapping >> 32; 6046 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
@@ -5879,20 +6052,20 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5879 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; 6052 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5880 6053
5881 prod = NEXT_TX_BD(prod); 6054 prod = NEXT_TX_BD(prod);
5882 bp->tx_prod_bseq += skb->len; 6055 txr->tx_prod_bseq += skb->len;
5883 6056
5884 REG_WR16(bp, bp->tx_bidx_addr, prod); 6057 REG_WR16(bp, txr->tx_bidx_addr, prod);
5885 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); 6058 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5886 6059
5887 mmiowb(); 6060 mmiowb();
5888 6061
5889 bp->tx_prod = prod; 6062 txr->tx_prod = prod;
5890 dev->trans_start = jiffies; 6063 dev->trans_start = jiffies;
5891 6064
5892 if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) { 6065 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
5893 netif_stop_queue(dev); 6066 netif_tx_stop_queue(txq);
5894 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh) 6067 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
5895 netif_wake_queue(dev); 6068 netif_tx_wake_queue(txq);
5896 } 6069 }
5897 6070
5898 return NETDEV_TX_OK; 6071 return NETDEV_TX_OK;
@@ -6095,6 +6268,12 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6095 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)) 6268 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6096 goto err_out_unlock; 6269 goto err_out_unlock;
6097 6270
6271 /* If device is down, we can store the settings only if the user
6272 * is setting the currently active port.
6273 */
6274 if (!netif_running(dev) && cmd->port != bp->phy_port)
6275 goto err_out_unlock;
6276
6098 if (cmd->autoneg == AUTONEG_ENABLE) { 6277 if (cmd->autoneg == AUTONEG_ENABLE) {
6099 autoneg |= AUTONEG_SPEED; 6278 autoneg |= AUTONEG_SPEED;
6100 6279
@@ -6152,7 +6331,12 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6152 bp->req_line_speed = req_line_speed; 6331 bp->req_line_speed = req_line_speed;
6153 bp->req_duplex = req_duplex; 6332 bp->req_duplex = req_duplex;
6154 6333
6155 err = bnx2_setup_phy(bp, cmd->port); 6334 err = 0;
6335 /* If device is down, the new settings will be picked up when it is
6336 * brought up.
6337 */
6338 if (netif_running(dev))
6339 err = bnx2_setup_phy(bp, cmd->port);
6156 6340
6157err_out_unlock: 6341err_out_unlock:
6158 spin_unlock_bh(&bp->phy_lock); 6342 spin_unlock_bh(&bp->phy_lock);
@@ -6414,7 +6598,7 @@ bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6414 6598
6415 if (netif_running(bp->dev)) { 6599 if (netif_running(bp->dev)) {
6416 bnx2_netif_stop(bp); 6600 bnx2_netif_stop(bp);
6417 bnx2_init_nic(bp); 6601 bnx2_init_nic(bp, 0);
6418 bnx2_netif_start(bp); 6602 bnx2_netif_start(bp);
6419 } 6603 }
6420 6604
@@ -6457,7 +6641,7 @@ bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6457 rc = bnx2_alloc_mem(bp); 6641 rc = bnx2_alloc_mem(bp);
6458 if (rc) 6642 if (rc)
6459 return rc; 6643 return rc;
6460 bnx2_init_nic(bp); 6644 bnx2_init_nic(bp, 0);
6461 bnx2_netif_start(bp); 6645 bnx2_netif_start(bp);
6462 } 6646 }
6463 return 0; 6647 return 0;
@@ -6725,7 +6909,7 @@ bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6725 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); 6909 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6726 } 6910 }
6727 else { 6911 else {
6728 bnx2_init_nic(bp); 6912 bnx2_init_nic(bp, 1);
6729 bnx2_netif_start(bp); 6913 bnx2_netif_start(bp);
6730 } 6914 }
6731 6915
@@ -6951,7 +7135,7 @@ bnx2_change_mac_addr(struct net_device *dev, void *p)
6951 7135
6952 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 7136 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6953 if (netif_running(dev)) 7137 if (netif_running(dev))
6954 bnx2_set_mac_addr(bp); 7138 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
6955 7139
6956 return 0; 7140 return 0;
6957} 7141}
@@ -7108,6 +7292,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7108 } 7292 }
7109 7293
7110 pci_set_master(pdev); 7294 pci_set_master(pdev);
7295 pci_save_state(pdev);
7111 7296
7112 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 7297 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7113 if (bp->pm_cap == 0) { 7298 if (bp->pm_cap == 0) {
@@ -7125,7 +7310,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7125 INIT_WORK(&bp->reset_task, bnx2_reset_task); 7310 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7126 7311
7127 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0); 7312 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7128 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1); 7313 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
7129 dev->mem_end = dev->mem_start + mem_len; 7314 dev->mem_end = dev->mem_start + mem_len;
7130 dev->irq = pdev->irq; 7315 dev->irq = pdev->irq;
7131 7316
@@ -7272,7 +7457,6 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7272 reg &= BNX2_CONDITION_MFW_RUN_MASK; 7457 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7273 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && 7458 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7274 reg != BNX2_CONDITION_MFW_RUN_NONE) { 7459 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7275 int i;
7276 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR); 7460 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7277 7461
7278 bp->fw_version[j++] = ' '; 7462 bp->fw_version[j++] = ' ';
@@ -7294,8 +7478,6 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7294 bp->mac_addr[4] = (u8) (reg >> 8); 7478 bp->mac_addr[4] = (u8) (reg >> 8);
7295 bp->mac_addr[5] = (u8) reg; 7479 bp->mac_addr[5] = (u8) reg;
7296 7480
7297 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
7298
7299 bp->tx_ring_size = MAX_TX_DESC_CNT; 7481 bp->tx_ring_size = MAX_TX_DESC_CNT;
7300 bnx2_set_rx_ring_size(bp, 255); 7482 bnx2_set_rx_ring_size(bp, 255);
7301 7483
@@ -7345,8 +7527,6 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7345 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) 7527 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7346 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; 7528 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7347 } 7529 }
7348 bnx2_init_remote_phy(bp);
7349
7350 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 || 7530 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7351 CHIP_NUM(bp) == CHIP_NUM_5708) 7531 CHIP_NUM(bp) == CHIP_NUM_5708)
7352 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX; 7532 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
@@ -7355,6 +7535,8 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7355 CHIP_REV(bp) == CHIP_REV_Bx)) 7535 CHIP_REV(bp) == CHIP_REV_Bx))
7356 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC; 7536 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7357 7537
7538 bnx2_init_fw_cap(bp);
7539
7358 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || 7540 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7359 (CHIP_ID(bp) == CHIP_ID_5708_B0) || 7541 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7360 (CHIP_ID(bp) == CHIP_ID_5708_B1)) { 7542 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
@@ -7451,15 +7633,19 @@ static void __devinit
7451bnx2_init_napi(struct bnx2 *bp) 7633bnx2_init_napi(struct bnx2 *bp)
7452{ 7634{
7453 int i; 7635 int i;
7454 struct bnx2_napi *bnapi;
7455 7636
7456 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { 7637 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7457 bnapi = &bp->bnx2_napi[i]; 7638 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7639 int (*poll)(struct napi_struct *, int);
7640
7641 if (i == 0)
7642 poll = bnx2_poll;
7643 else
7644 poll = bnx2_poll_msix;
7645
7646 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7458 bnapi->bp = bp; 7647 bnapi->bp = bp;
7459 } 7648 }
7460 netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64);
7461 netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll,
7462 64);
7463} 7649}
7464 7650
7465static int __devinit 7651static int __devinit
@@ -7476,7 +7662,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7476 printk(KERN_INFO "%s", version); 7662 printk(KERN_INFO "%s", version);
7477 7663
7478 /* dev zeroed in init_etherdev */ 7664 /* dev zeroed in init_etherdev */
7479 dev = alloc_etherdev(sizeof(*bp)); 7665 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
7480 7666
7481 if (!dev) 7667 if (!dev)
7482 return -ENOMEM; 7668 return -ENOMEM;
@@ -7491,7 +7677,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7491 dev->hard_start_xmit = bnx2_start_xmit; 7677 dev->hard_start_xmit = bnx2_start_xmit;
7492 dev->stop = bnx2_close; 7678 dev->stop = bnx2_close;
7493 dev->get_stats = bnx2_get_stats; 7679 dev->get_stats = bnx2_get_stats;
7494 dev->set_multicast_list = bnx2_set_rx_mode; 7680 dev->set_rx_mode = bnx2_set_rx_mode;
7495 dev->do_ioctl = bnx2_ioctl; 7681 dev->do_ioctl = bnx2_ioctl;
7496 dev->set_mac_address = bnx2_change_mac_addr; 7682 dev->set_mac_address = bnx2_change_mac_addr;
7497 dev->change_mtu = bnx2_change_mtu; 7683 dev->change_mtu = bnx2_change_mtu;
@@ -7612,11 +7798,97 @@ bnx2_resume(struct pci_dev *pdev)
7612 7798
7613 bnx2_set_power_state(bp, PCI_D0); 7799 bnx2_set_power_state(bp, PCI_D0);
7614 netif_device_attach(dev); 7800 netif_device_attach(dev);
7615 bnx2_init_nic(bp); 7801 bnx2_init_nic(bp, 1);
7616 bnx2_netif_start(bp); 7802 bnx2_netif_start(bp);
7617 return 0; 7803 return 0;
7618} 7804}
7619 7805
7806/**
7807 * bnx2_io_error_detected - called when PCI error is detected
7808 * @pdev: Pointer to PCI device
7809 * @state: The current pci connection state
7810 *
7811 * This function is called after a PCI bus error affecting
7812 * this device has been detected.
7813 */
7814static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7815 pci_channel_state_t state)
7816{
7817 struct net_device *dev = pci_get_drvdata(pdev);
7818 struct bnx2 *bp = netdev_priv(dev);
7819
7820 rtnl_lock();
7821 netif_device_detach(dev);
7822
7823 if (netif_running(dev)) {
7824 bnx2_netif_stop(bp);
7825 del_timer_sync(&bp->timer);
7826 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7827 }
7828
7829 pci_disable_device(pdev);
7830 rtnl_unlock();
7831
7832 /* Request a slot slot reset. */
7833 return PCI_ERS_RESULT_NEED_RESET;
7834}
7835
7836/**
7837 * bnx2_io_slot_reset - called after the pci bus has been reset.
7838 * @pdev: Pointer to PCI device
7839 *
7840 * Restart the card from scratch, as if from a cold-boot.
7841 */
7842static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7843{
7844 struct net_device *dev = pci_get_drvdata(pdev);
7845 struct bnx2 *bp = netdev_priv(dev);
7846
7847 rtnl_lock();
7848 if (pci_enable_device(pdev)) {
7849 dev_err(&pdev->dev,
7850 "Cannot re-enable PCI device after reset.\n");
7851 rtnl_unlock();
7852 return PCI_ERS_RESULT_DISCONNECT;
7853 }
7854 pci_set_master(pdev);
7855 pci_restore_state(pdev);
7856
7857 if (netif_running(dev)) {
7858 bnx2_set_power_state(bp, PCI_D0);
7859 bnx2_init_nic(bp, 1);
7860 }
7861
7862 rtnl_unlock();
7863 return PCI_ERS_RESULT_RECOVERED;
7864}
7865
7866/**
7867 * bnx2_io_resume - called when traffic can start flowing again.
7868 * @pdev: Pointer to PCI device
7869 *
7870 * This callback is called when the error recovery driver tells us that
7871 * its OK to resume normal operation.
7872 */
7873static void bnx2_io_resume(struct pci_dev *pdev)
7874{
7875 struct net_device *dev = pci_get_drvdata(pdev);
7876 struct bnx2 *bp = netdev_priv(dev);
7877
7878 rtnl_lock();
7879 if (netif_running(dev))
7880 bnx2_netif_start(bp);
7881
7882 netif_device_attach(dev);
7883 rtnl_unlock();
7884}
7885
7886static struct pci_error_handlers bnx2_err_handler = {
7887 .error_detected = bnx2_io_error_detected,
7888 .slot_reset = bnx2_io_slot_reset,
7889 .resume = bnx2_io_resume,
7890};
7891
7620static struct pci_driver bnx2_pci_driver = { 7892static struct pci_driver bnx2_pci_driver = {
7621 .name = DRV_MODULE_NAME, 7893 .name = DRV_MODULE_NAME,
7622 .id_table = bnx2_pci_tbl, 7894 .id_table = bnx2_pci_tbl,
@@ -7624,6 +7896,7 @@ static struct pci_driver bnx2_pci_driver = {
7624 .remove = __devexit_p(bnx2_remove_one), 7896 .remove = __devexit_p(bnx2_remove_one),
7625 .suspend = bnx2_suspend, 7897 .suspend = bnx2_suspend,
7626 .resume = bnx2_resume, 7898 .resume = bnx2_resume,
7899 .err_handler = &bnx2_err_handler,
7627}; 7900};
7628 7901
7629static int __init bnx2_init(void) 7902static int __init bnx2_init(void)
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 2377cc13bf61..c3c579f98ed0 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -309,6 +309,7 @@ struct l2_fhdr {
309#endif 309#endif
310}; 310};
311 311
312#define BNX2_RX_OFFSET (sizeof(struct l2_fhdr) + 2)
312 313
313/* 314/*
314 * l2_context definition 315 * l2_context definition
@@ -4157,6 +4158,23 @@ struct l2_fhdr {
4157 4158
4158 4159
4159/* 4160/*
4161 * rlup_reg definition
4162 * offset: 0x2000
4163 */
4164#define BNX2_RLUP_RSS_CONFIG 0x0000201c
4165#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI (0x3L<<0)
4166#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI (0L<<0)
4167#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI (1L<<0)
4168#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI (2L<<0)
4169#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI (3L<<0)
4170#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI (0x3L<<2)
4171#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI (0L<<2)
4172#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI (1L<<2)
4173#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI (2L<<2)
4174#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI (3L<<2)
4175
4176
4177/*
4160 * rbuf_reg definition 4178 * rbuf_reg definition
4161 * offset: 0x200000 4179 * offset: 0x200000
4162 */ 4180 */
@@ -5527,6 +5545,9 @@ struct l2_fhdr {
5527#define BNX2_HC_TX_QUICK_CONS_TRIP_OFF (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \ 5545#define BNX2_HC_TX_QUICK_CONS_TRIP_OFF (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \
5528 BNX2_HC_SB_CONFIG_1) 5546 BNX2_HC_SB_CONFIG_1)
5529#define BNX2_HC_TX_TICKS_OFF (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1) 5547#define BNX2_HC_TX_TICKS_OFF (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
5548#define BNX2_HC_RX_QUICK_CONS_TRIP_OFF (BNX2_HC_RX_QUICK_CONS_TRIP_1 - \
5549 BNX2_HC_SB_CONFIG_1)
5550#define BNX2_HC_RX_TICKS_OFF (BNX2_HC_RX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
5530 5551
5531 5552
5532/* 5553/*
@@ -5855,6 +5876,9 @@ struct l2_fhdr {
5855#define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5876#define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
5856 5877
5857#define BNX2_RXP_SCRATCH 0x000e0000 5878#define BNX2_RXP_SCRATCH 0x000e0000
5879#define BNX2_RXP_SCRATCH_RSS_TBL_SZ 0x000e0038
5880#define BNX2_RXP_SCRATCH_RSS_TBL 0x000e003c
5881#define BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES 128
5858 5882
5859 5883
5860/* 5884/*
@@ -6412,10 +6436,15 @@ struct l2_fhdr {
6412#define MAX_ETHERNET_PACKET_SIZE 1514 6436#define MAX_ETHERNET_PACKET_SIZE 1514
6413#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014 6437#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
6414 6438
6415#define RX_COPY_THRESH 128 6439#define BNX2_RX_COPY_THRESH 128
6416 6440
6417#define BNX2_MISC_ENABLE_DEFAULT 0x17ffffff 6441#define BNX2_MISC_ENABLE_DEFAULT 0x17ffffff
6418 6442
6443#define BNX2_START_UNICAST_ADDRESS_INDEX 4
6444#define BNX2_END_UNICAST_ADDRESS_INDEX 7
6445#define BNX2_MAX_UNICAST_ADDRESSES (BNX2_END_UNICAST_ADDRESS_INDEX - \
6446 BNX2_START_UNICAST_ADDRESS_INDEX + 1)
6447
6419#define DMA_READ_CHANS 5 6448#define DMA_READ_CHANS 5
6420#define DMA_WRITE_CHANS 3 6449#define DMA_WRITE_CHANS 3
6421 6450
@@ -6478,6 +6507,11 @@ struct l2_fhdr {
6478#define TX_CID 16 6507#define TX_CID 16
6479#define TX_TSS_CID 32 6508#define TX_TSS_CID 32
6480#define RX_CID 0 6509#define RX_CID 0
6510#define RX_RSS_CID 4
6511#define RX_MAX_RSS_RINGS 7
6512#define RX_MAX_RINGS (RX_MAX_RSS_RINGS + 1)
6513#define TX_MAX_TSS_RINGS 7
6514#define TX_MAX_RINGS (TX_MAX_TSS_RINGS + 1)
6481 6515
6482#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) 6516#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
6483#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) 6517#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
@@ -6556,7 +6590,7 @@ struct flash_spec {
6556}; 6590};
6557 6591
6558#define BNX2_MAX_MSIX_HW_VEC 9 6592#define BNX2_MAX_MSIX_HW_VEC 9
6559#define BNX2_MAX_MSIX_VEC 2 6593#define BNX2_MAX_MSIX_VEC 9
6560#define BNX2_BASE_VEC 0 6594#define BNX2_BASE_VEC 0
6561#define BNX2_TX_VEC 1 6595#define BNX2_TX_VEC 1
6562#define BNX2_TX_INT_NUM (BNX2_TX_VEC << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT) 6596#define BNX2_TX_INT_NUM (BNX2_TX_VEC << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT)
@@ -6568,24 +6602,56 @@ struct bnx2_irq {
6568 char name[16]; 6602 char name[16];
6569}; 6603};
6570 6604
6571struct bnx2_napi { 6605struct bnx2_tx_ring_info {
6572 struct napi_struct napi ____cacheline_aligned; 6606 u32 tx_prod_bseq;
6573 struct bnx2 *bp; 6607 u16 tx_prod;
6574 struct status_block *status_blk; 6608 u32 tx_bidx_addr;
6575 struct status_block_msix *status_blk_msix; 6609 u32 tx_bseq_addr;
6576 u32 last_status_idx; 6610
6577 u32 int_num; 6611 struct tx_bd *tx_desc_ring;
6612 struct sw_bd *tx_buf_ring;
6578 6613
6579 u16 tx_cons; 6614 u16 tx_cons;
6580 u16 hw_tx_cons; 6615 u16 hw_tx_cons;
6581 6616
6617 dma_addr_t tx_desc_mapping;
6618};
6619
6620struct bnx2_rx_ring_info {
6582 u32 rx_prod_bseq; 6621 u32 rx_prod_bseq;
6583 u16 rx_prod; 6622 u16 rx_prod;
6584 u16 rx_cons; 6623 u16 rx_cons;
6585 6624
6625 u32 rx_bidx_addr;
6626 u32 rx_bseq_addr;
6627 u32 rx_pg_bidx_addr;
6628
6586 u16 rx_pg_prod; 6629 u16 rx_pg_prod;
6587 u16 rx_pg_cons; 6630 u16 rx_pg_cons;
6588 6631
6632 struct sw_bd *rx_buf_ring;
6633 struct rx_bd *rx_desc_ring[MAX_RX_RINGS];
6634 struct sw_pg *rx_pg_ring;
6635 struct rx_bd *rx_pg_desc_ring[MAX_RX_PG_RINGS];
6636
6637 dma_addr_t rx_desc_mapping[MAX_RX_RINGS];
6638 dma_addr_t rx_pg_desc_mapping[MAX_RX_PG_RINGS];
6639};
6640
6641struct bnx2_napi {
6642 struct napi_struct napi ____cacheline_aligned;
6643 struct bnx2 *bp;
6644 union {
6645 struct status_block *msi;
6646 struct status_block_msix *msix;
6647 } status_blk;
6648 u16 *hw_tx_cons_ptr;
6649 u16 *hw_rx_cons_ptr;
6650 u32 last_status_idx;
6651 u32 int_num;
6652
6653 struct bnx2_rx_ring_info rx_ring;
6654 struct bnx2_tx_ring_info tx_ring;
6589}; 6655};
6590 6656
6591struct bnx2 { 6657struct bnx2 {
@@ -6612,14 +6678,7 @@ struct bnx2 {
6612#define BNX2_FLAG_USING_MSI_OR_MSIX (BNX2_FLAG_USING_MSI | \ 6678#define BNX2_FLAG_USING_MSI_OR_MSIX (BNX2_FLAG_USING_MSI | \
6613 BNX2_FLAG_USING_MSIX) 6679 BNX2_FLAG_USING_MSIX)
6614#define BNX2_FLAG_JUMBO_BROKEN 0x00000800 6680#define BNX2_FLAG_JUMBO_BROKEN 0x00000800
6615 6681#define BNX2_FLAG_CAN_KEEP_VLAN 0x00001000
6616 /* Put tx producer and consumer fields in separate cache lines. */
6617
6618 u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
6619 u16 tx_prod;
6620 u8 tx_vec;
6621 u32 tx_bidx_addr;
6622 u32 tx_bseq_addr;
6623 6682
6624 struct bnx2_napi bnx2_napi[BNX2_MAX_MSIX_VEC]; 6683 struct bnx2_napi bnx2_napi[BNX2_MAX_MSIX_VEC];
6625 6684
@@ -6627,7 +6686,6 @@ struct bnx2 {
6627 struct vlan_group *vlgrp; 6686 struct vlan_group *vlgrp;
6628#endif 6687#endif
6629 6688
6630 u32 rx_offset;
6631 u32 rx_buf_use_size; /* useable size */ 6689 u32 rx_buf_use_size; /* useable size */
6632 u32 rx_buf_size; /* with alignment */ 6690 u32 rx_buf_size; /* with alignment */
6633 u32 rx_copy_thresh; 6691 u32 rx_copy_thresh;
@@ -6637,14 +6695,7 @@ struct bnx2 {
6637 6695
6638 u32 rx_csum; 6696 u32 rx_csum;
6639 6697
6640 struct sw_bd *rx_buf_ring;
6641 struct rx_bd *rx_desc_ring[MAX_RX_RINGS];
6642 struct sw_pg *rx_pg_ring;
6643 struct rx_bd *rx_pg_desc_ring[MAX_RX_PG_RINGS];
6644
6645 /* TX constants */ 6698 /* TX constants */
6646 struct tx_bd *tx_desc_ring;
6647 struct sw_bd *tx_buf_ring;
6648 int tx_ring_size; 6699 int tx_ring_size;
6649 u32 tx_wake_thresh; 6700 u32 tx_wake_thresh;
6650 6701
@@ -6722,16 +6773,11 @@ struct bnx2 {
6722 u16 fw_wr_seq; 6773 u16 fw_wr_seq;
6723 u16 fw_drv_pulse_wr_seq; 6774 u16 fw_drv_pulse_wr_seq;
6724 6775
6725 dma_addr_t tx_desc_mapping;
6726
6727
6728 int rx_max_ring; 6776 int rx_max_ring;
6729 int rx_ring_size; 6777 int rx_ring_size;
6730 dma_addr_t rx_desc_mapping[MAX_RX_RINGS];
6731 6778
6732 int rx_max_pg_ring; 6779 int rx_max_pg_ring;
6733 int rx_pg_ring_size; 6780 int rx_pg_ring_size;
6734 dma_addr_t rx_pg_desc_mapping[MAX_RX_PG_RINGS];
6735 6781
6736 u16 tx_quick_cons_trip; 6782 u16 tx_quick_cons_trip;
6737 u16 tx_quick_cons_trip_int; 6783 u16 tx_quick_cons_trip_int;
@@ -6750,7 +6796,6 @@ struct bnx2 {
6750 6796
6751 u32 stats_ticks; 6797 u32 stats_ticks;
6752 6798
6753 struct status_block *status_blk;
6754 dma_addr_t status_blk_mapping; 6799 dma_addr_t status_blk_mapping;
6755 6800
6756 struct statistics_block *stats_blk; 6801 struct statistics_block *stats_blk;
@@ -6812,6 +6857,9 @@ struct bnx2 {
6812 6857
6813 struct bnx2_irq irq_tbl[BNX2_MAX_MSIX_VEC]; 6858 struct bnx2_irq irq_tbl[BNX2_MAX_MSIX_VEC];
6814 int irq_nvecs; 6859 int irq_nvecs;
6860
6861 u8 num_tx_rings;
6862 u8 num_rx_rings;
6815}; 6863};
6816 6864
6817#define REG_RD(bp, offset) \ 6865#define REG_RD(bp, offset) \
@@ -6912,6 +6960,7 @@ struct fw_info {
6912#define BNX2_DRV_MSG_CODE_DIAG 0x07000000 6960#define BNX2_DRV_MSG_CODE_DIAG 0x07000000
6913#define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 6961#define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
6914#define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 6962#define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000
6963#define BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE 0x0d000000
6915#define BNX2_DRV_MSG_CODE_CMD_SET_LINK 0x10000000 6964#define BNX2_DRV_MSG_CODE_CMD_SET_LINK 0x10000000
6916 6965
6917#define BNX2_DRV_MSG_DATA 0x00ff0000 6966#define BNX2_DRV_MSG_DATA 0x00ff0000
@@ -7240,6 +7289,10 @@ struct fw_info {
7240#define BNX2_FW_CAP_SIGNATURE_MASK 0xffff0000 7289#define BNX2_FW_CAP_SIGNATURE_MASK 0xffff0000
7241#define BNX2_FW_CAP_REMOTE_PHY_CAPABLE 0x00000001 7290#define BNX2_FW_CAP_REMOTE_PHY_CAPABLE 0x00000001
7242#define BNX2_FW_CAP_REMOTE_PHY_PRESENT 0x00000002 7291#define BNX2_FW_CAP_REMOTE_PHY_PRESENT 0x00000002
7292#define BNX2_FW_CAP_MFW_CAN_KEEP_VLAN 0x00000008
7293#define BNX2_FW_CAP_BC_CAN_KEEP_VLAN 0x00000010
7294#define BNX2_FW_CAP_CAN_KEEP_VLAN (BNX2_FW_CAP_BC_CAN_KEEP_VLAN | \
7295 BNX2_FW_CAP_MFW_CAN_KEEP_VLAN)
7243 7296
7244#define BNX2_RPHY_SIGNATURE 0x36c 7297#define BNX2_RPHY_SIGNATURE 0x36c
7245#define BNX2_RPHY_LOAD_SIGNATURE 0x5a5a5a5a 7298#define BNX2_RPHY_LOAD_SIGNATURE 0x5a5a5a5a
diff --git a/drivers/net/bnx2_fw.h b/drivers/net/bnx2_fw.h
index 3b839d4626fe..e4b1de435567 100644
--- a/drivers/net/bnx2_fw.h
+++ b/drivers/net/bnx2_fw.h
@@ -886,6 +886,23 @@ static struct fw_info bnx2_com_fw_06 = {
886 .rodata = bnx2_COM_b06FwRodata, 886 .rodata = bnx2_COM_b06FwRodata,
887}; 887};
888 888
889/* Initialized Values for the Completion Processor. */
890static const struct cpu_reg cpu_reg_com = {
891 .mode = BNX2_COM_CPU_MODE,
892 .mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT,
893 .mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA,
894 .state = BNX2_COM_CPU_STATE,
895 .state_value_clear = 0xffffff,
896 .gpr0 = BNX2_COM_CPU_REG_FILE,
897 .evmask = BNX2_COM_CPU_EVENT_MASK,
898 .pc = BNX2_COM_CPU_PROGRAM_COUNTER,
899 .inst = BNX2_COM_CPU_INSTRUCTION,
900 .bp = BNX2_COM_CPU_HW_BREAKPOINT,
901 .spad_base = BNX2_COM_SCRATCH,
902 .mips_view_base = 0x8000000,
903};
904
905
889static u8 bnx2_CP_b06FwText[] = { 906static u8 bnx2_CP_b06FwText[] = {
890 0x9d, 0xbc, 0x0d, 0x78, 0x13, 0xe7, 0x99, 0x2e, 0x7c, 0xcf, 0x48, 0xb2, 907 0x9d, 0xbc, 0x0d, 0x78, 0x13, 0xe7, 0x99, 0x2e, 0x7c, 0xcf, 0x48, 0xb2,
891 0x65, 0x5b, 0xb6, 0xc7, 0xb6, 0x0c, 0x22, 0x65, 0x41, 0x83, 0x47, 0x20, 908 0x65, 0x5b, 0xb6, 0xc7, 0xb6, 0x0c, 0x22, 0x65, 0x41, 0x83, 0x47, 0x20,
@@ -2167,6 +2184,22 @@ static struct fw_info bnx2_cp_fw_06 = {
2167 .rodata = bnx2_CP_b06FwRodata, 2184 .rodata = bnx2_CP_b06FwRodata,
2168}; 2185};
2169 2186
2187/* Initialized Values the Command Processor. */
2188static const struct cpu_reg cpu_reg_cp = {
2189 .mode = BNX2_CP_CPU_MODE,
2190 .mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT,
2191 .mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA,
2192 .state = BNX2_CP_CPU_STATE,
2193 .state_value_clear = 0xffffff,
2194 .gpr0 = BNX2_CP_CPU_REG_FILE,
2195 .evmask = BNX2_CP_CPU_EVENT_MASK,
2196 .pc = BNX2_CP_CPU_PROGRAM_COUNTER,
2197 .inst = BNX2_CP_CPU_INSTRUCTION,
2198 .bp = BNX2_CP_CPU_HW_BREAKPOINT,
2199 .spad_base = BNX2_CP_SCRATCH,
2200 .mips_view_base = 0x8000000,
2201};
2202
2170static u8 bnx2_RXP_b06FwText[] = { 2203static u8 bnx2_RXP_b06FwText[] = {
2171 0xec, 0x5b, 0x5d, 0x70, 0x5c, 0xd7, 0x5d, 0xff, 0xdf, 0xb3, 0x2b, 0x69, 2204 0xec, 0x5b, 0x5d, 0x70, 0x5c, 0xd7, 0x5d, 0xff, 0xdf, 0xb3, 0x2b, 0x69,
2172 0x2d, 0x4b, 0xf2, 0x95, 0xbc, 0x71, 0x56, 0xa9, 0x92, 0xec, 0x5a, 0x57, 2205 0x2d, 0x4b, 0xf2, 0x95, 0xbc, 0x71, 0x56, 0xa9, 0x92, 0xec, 0x5a, 0x57,
@@ -2946,6 +2979,22 @@ static struct fw_info bnx2_rxp_fw_06 = {
2946 .rodata = bnx2_RXP_b06FwRodata, 2979 .rodata = bnx2_RXP_b06FwRodata,
2947}; 2980};
2948 2981
2982/* Initialized Values for the RX Processor. */
2983static const struct cpu_reg cpu_reg_rxp = {
2984 .mode = BNX2_RXP_CPU_MODE,
2985 .mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT,
2986 .mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA,
2987 .state = BNX2_RXP_CPU_STATE,
2988 .state_value_clear = 0xffffff,
2989 .gpr0 = BNX2_RXP_CPU_REG_FILE,
2990 .evmask = BNX2_RXP_CPU_EVENT_MASK,
2991 .pc = BNX2_RXP_CPU_PROGRAM_COUNTER,
2992 .inst = BNX2_RXP_CPU_INSTRUCTION,
2993 .bp = BNX2_RXP_CPU_HW_BREAKPOINT,
2994 .spad_base = BNX2_RXP_SCRATCH,
2995 .mips_view_base = 0x8000000,
2996};
2997
2949static u8 bnx2_rv2p_proc1[] = { 2998static u8 bnx2_rv2p_proc1[] = {
2950 /* Date: 12/07/2007 15:02 */ 2999 /* Date: 12/07/2007 15:02 */
2951 0xd5, 0x56, 0x41, 0x6b, 0x13, 0x51, 0x10, 0x9e, 0xdd, 0x6c, 0xbb, 0xdb, 3000 0xd5, 0x56, 0x41, 0x6b, 0x13, 0x51, 0x10, 0x9e, 0xdd, 0x6c, 0xbb, 0xdb,
@@ -3651,6 +3700,22 @@ static struct fw_info bnx2_tpat_fw_06 = {
3651 .rodata = bnx2_TPAT_b06FwRodata, 3700 .rodata = bnx2_TPAT_b06FwRodata,
3652}; 3701};
3653 3702
3703/* Initialized Values for the TX Patch-up Processor. */
3704static const struct cpu_reg cpu_reg_tpat = {
3705 .mode = BNX2_TPAT_CPU_MODE,
3706 .mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT,
3707 .mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA,
3708 .state = BNX2_TPAT_CPU_STATE,
3709 .state_value_clear = 0xffffff,
3710 .gpr0 = BNX2_TPAT_CPU_REG_FILE,
3711 .evmask = BNX2_TPAT_CPU_EVENT_MASK,
3712 .pc = BNX2_TPAT_CPU_PROGRAM_COUNTER,
3713 .inst = BNX2_TPAT_CPU_INSTRUCTION,
3714 .bp = BNX2_TPAT_CPU_HW_BREAKPOINT,
3715 .spad_base = BNX2_TPAT_SCRATCH,
3716 .mips_view_base = 0x8000000,
3717};
3718
3654static u8 bnx2_TXP_b06FwText[] = { 3719static u8 bnx2_TXP_b06FwText[] = {
3655 0xad, 0x7b, 0x7f, 0x70, 0x9b, 0x75, 0x7a, 0xe7, 0xe7, 0xd5, 0x0f, 0x5b, 3720 0xad, 0x7b, 0x7f, 0x70, 0x9b, 0x75, 0x7a, 0xe7, 0xe7, 0xd5, 0x0f, 0x5b,
3656 0xb2, 0x65, 0x59, 0x0e, 0x4a, 0x90, 0x77, 0xbd, 0x8d, 0x5e, 0xf4, 0xca, 3721 0xb2, 0x65, 0x59, 0x0e, 0x4a, 0x90, 0x77, 0xbd, 0x8d, 0x5e, 0xf4, 0xca,
@@ -4531,3 +4596,18 @@ static struct fw_info bnx2_txp_fw_06 = {
4531 .rodata = bnx2_TXP_b06FwRodata, 4596 .rodata = bnx2_TXP_b06FwRodata,
4532}; 4597};
4533 4598
4599/* Initialized Values for the TX Processor. */
4600static const struct cpu_reg cpu_reg_txp = {
4601 .mode = BNX2_TXP_CPU_MODE,
4602 .mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT,
4603 .mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA,
4604 .state = BNX2_TXP_CPU_STATE,
4605 .state_value_clear = 0xffffff,
4606 .gpr0 = BNX2_TXP_CPU_REG_FILE,
4607 .evmask = BNX2_TXP_CPU_EVENT_MASK,
4608 .pc = BNX2_TXP_CPU_PROGRAM_COUNTER,
4609 .inst = BNX2_TXP_CPU_INSTRUCTION,
4610 .bp = BNX2_TXP_CPU_HW_BREAKPOINT,
4611 .spad_base = BNX2_TXP_SCRATCH,
4612 .mips_view_base = 0x8000000,
4613};
diff --git a/drivers/net/bnx2_fw2.h b/drivers/net/bnx2_fw2.h
index ed0514cba0ee..fe753b6bcb41 100644
--- a/drivers/net/bnx2_fw2.h
+++ b/drivers/net/bnx2_fw2.h
@@ -15,842 +15,848 @@
15 */ 15 */
16 16
17static u8 bnx2_COM_b09FwText[] = { 17static u8 bnx2_COM_b09FwText[] = {
18 0xcd, 0x7c, 0x7f, 0x6c, 0x5c, 0xd7, 0x95, 0xde, 0x79, 0x6f, 0x1e, 0xc9, 18 0xcd, 0x7c, 0x7f, 0x6c, 0x5c, 0xd7, 0x75, 0xe6, 0x79, 0x6f, 0xde, 0x90,
19 0xe1, 0x88, 0xa2, 0x1e, 0xe9, 0x31, 0x3d, 0x8e, 0xb9, 0xc9, 0x0c, 0xe7, 19 0x43, 0x8a, 0xa2, 0x1e, 0x99, 0x31, 0x33, 0x8e, 0xd8, 0x7a, 0x86, 0xf3,
20 0x91, 0xa2, 0x4d, 0x26, 0xfb, 0xcc, 0x8e, 0x6d, 0x3a, 0x99, 0xb5, 0xc6, 20 0x48, 0xd1, 0x21, 0xe3, 0x3e, 0x33, 0x63, 0x99, 0x76, 0xa6, 0xd6, 0x64,
21 0x33, 0x94, 0xad, 0xc4, 0x8c, 0x41, 0x3b, 0xca, 0xd6, 0x28, 0xdc, 0x80, 21 0x66, 0x28, 0x2b, 0x0e, 0x69, 0xd0, 0x8e, 0x82, 0x4d, 0x01, 0x03, 0xe5,
22 0x1d, 0x52, 0x8e, 0xb3, 0x75, 0xbb, 0x8e, 0x1b, 0xa4, 0x89, 0x11, 0x44, 22 0x0e, 0xa9, 0x54, 0xd9, 0xf5, 0x22, 0xda, 0x34, 0x45, 0x8a, 0xa2, 0x88,
23 0x93, 0x21, 0xa5, 0x55, 0x82, 0x21, 0x67, 0x22, 0xd3, 0xdc, 0xfc, 0xb1, 23 0x26, 0x24, 0xe5, 0x2a, 0xcd, 0x88, 0x1c, 0xcb, 0x34, 0x1b, 0x14, 0x5e,
24 0x68, 0xc6, 0x43, 0x52, 0x71, 0xb6, 0x23, 0xd1, 0x4e, 0xb2, 0x41, 0x16, 24 0x64, 0x3c, 0xa4, 0x14, 0xb7, 0x1d, 0x89, 0x72, 0xe2, 0x2d, 0xbc, 0x58,
25 0xd8, 0xc0, 0x2c, 0x25, 0xcb, 0xc2, 0x22, 0x2d, 0xdc, 0x34, 0x28, 0x82, 25 0x07, 0x66, 0xa9, 0x1f, 0x4e, 0x83, 0x14, 0xf0, 0x2e, 0xbc, 0x68, 0x60,
26 0xec, 0xfe, 0x21, 0xc8, 0xce, 0xc6, 0x29, 0xd2, 0xc2, 0xed, 0x06, 0x8d, 26 0xa4, 0x80, 0x20, 0xbb, 0x8d, 0xb3, 0xc8, 0x62, 0x83, 0xdd, 0x00, 0x71,
27 0x37, 0x48, 0xf2, 0xfa, 0x7d, 0xf7, 0xde, 0x37, 0x1a, 0x8d, 0x68, 0x27, 27 0x02, 0x27, 0x6f, 0xbf, 0xef, 0xde, 0xfb, 0xc8, 0xd1, 0x88, 0x76, 0xd2,
28 0xdd, 0xfe, 0x53, 0x02, 0x83, 0xfb, 0xde, 0xfd, 0x79, 0xee, 0xb9, 0xe7, 28 0xfc, 0xb5, 0x04, 0x06, 0xf7, 0xfd, 0xb8, 0x3f, 0xce, 0x3d, 0xf7, 0xdc,
29 0x9e, 0xf3, 0x9d, 0x73, 0xef, 0xe3, 0x3d, 0x22, 0x31, 0x31, 0x7f, 0xfb, 29 0x73, 0xbe, 0x73, 0xee, 0x79, 0x7c, 0x40, 0xa4, 0x53, 0xcc, 0xdf, 0x5e,
30 0xf1, 0xcb, 0xfc, 0xab, 0x3f, 0x5e, 0xb8, 0xe3, 0x7d, 0xfe, 0xfb, 0xf8, 30 0xfc, 0x32, 0xff, 0xe1, 0xb3, 0xb3, 0x63, 0x77, 0x65, 0xee, 0xc2, 0xe5,
31 0x6e, 0x77, 0x89, 0xc3, 0x34, 0x82, 0x5f, 0x1c, 0xbf, 0x29, 0xf3, 0xbc, 31 0x87, 0xed, 0xf7, 0x3b, 0x0e, 0x9f, 0x47, 0xf0, 0x8b, 0xe3, 0x37, 0x66,
32 0xd7, 0x9f, 0x8b, 0xdf, 0x9d, 0x96, 0xc8, 0xfc, 0x7f, 0x13, 0xb1, 0x3a, 32 0xae, 0x77, 0xfb, 0x73, 0xf1, 0x3b, 0x68, 0x89, 0xcc, 0xfc, 0x4f, 0x11,
33 0xca, 0xa2, 0x7b, 0xd4, 0x0f, 0x82, 0xb7, 0xe9, 0xc8, 0xfc, 0xd9, 0xf8, 33 0xab, 0xe5, 0x5d, 0xec, 0x5d, 0xda, 0xbc, 0xd7, 0x9f, 0xfd, 0x1b, 0xb4,
34 0x25, 0xdf, 0xb9, 0xca, 0xff, 0xf3, 0x5f, 0x44, 0x93, 0xad, 0xe6, 0xcd, 34 0xf9, 0xd7, 0xfe, 0x45, 0x34, 0xd9, 0x6a, 0xde, 0xfc, 0x49, 0xcc, 0xce,
35 0x9f, 0x44, 0xed, 0x6c, 0xfd, 0x81, 0xbc, 0x27, 0xd1, 0x48, 0x76, 0x6d, 35 0xce, 0x4c, 0xe6, 0x3d, 0x89, 0x45, 0xb2, 0x47, 0xa7, 0x66, 0x3d, 0x91,
36 0x76, 0xc1, 0x13, 0xc9, 0x35, 0x27, 0x92, 0x05, 0xf9, 0x75, 0x50, 0x8a, 36 0x5c, 0x63, 0x24, 0x59, 0x90, 0x5f, 0x04, 0xe5, 0xb8, 0x23, 0x7c, 0xfe,
37 0x3b, 0xc2, 0xfc, 0xdf, 0xcb, 0xfe, 0xea, 0xab, 0xdf, 0xbd, 0x2b, 0xf5, 37 0x5b, 0xd9, 0x77, 0xbe, 0xf6, 0xad, 0x7b, 0x53, 0x3f, 0xae, 0x45, 0x24,
38 0x66, 0x3d, 0x22, 0x51, 0x37, 0xfb, 0x96, 0xb8, 0x63, 0x12, 0x1d, 0x46, 38 0xe6, 0x66, 0xdf, 0x16, 0x77, 0x48, 0x62, 0xfd, 0x68, 0xf3, 0xcc, 0x81,
39 0x9b, 0x3f, 0x3b, 0x78, 0xc9, 0x96, 0xfe, 0xb0, 0x2f, 0x77, 0x3e, 0x92, 39 0x57, 0x6d, 0xe9, 0x0e, 0xfb, 0x72, 0x67, 0x22, 0x59, 0x99, 0x3e, 0x56,
40 0x95, 0xb9, 0x63, 0x95, 0xe3, 0x81, 0xed, 0x49, 0xc9, 0xc9, 0x7a, 0xe3, 40 0x39, 0x19, 0xd8, 0x9e, 0x94, 0x9d, 0xac, 0x37, 0x5c, 0x97, 0xae, 0xf1,
41 0x0d, 0xe9, 0x9b, 0xde, 0xca, 0xdc, 0x25, 0x78, 0x9f, 0x3b, 0xd6, 0x8c, 41 0x73, 0x99, 0x7b, 0x05, 0xf7, 0xd3, 0xc7, 0x1a, 0x31, 0x99, 0x6f, 0x94,
42 0x4a, 0xb9, 0x59, 0xea, 0xb3, 0x3d, 0x0f, 0xa9, 0x44, 0xbb, 0xb3, 0x8b, 42 0xbb, 0x6c, 0xcf, 0x43, 0x29, 0xb1, 0xb6, 0xec, 0x62, 0xec, 0x9a, 0xc7,
43 0xd1, 0x8b, 0x1e, 0xc7, 0xfe, 0x21, 0xc6, 0xbe, 0x45, 0xba, 0xbc, 0x20, 43 0xb1, 0xbf, 0x8a, 0xb1, 0xf7, 0x4b, 0xd4, 0x0b, 0x82, 0x73, 0x18, 0xfb,
44 0xd8, 0xc2, 0xd8, 0xf7, 0x35, 0x7f, 0x1d, 0x3c, 0xe7, 0xe8, 0x71, 0xed, 44 0x70, 0xe3, 0x17, 0xc1, 0xb3, 0x8e, 0x1e, 0xd7, 0xce, 0x9e, 0x88, 0xb0,
45 0xec, 0x93, 0x11, 0xa6, 0x56, 0xf6, 0xf2, 0x03, 0x23, 0x4d, 0xbe, 0x7b, 45 0xb4, 0xb2, 0xb5, 0xc9, 0x81, 0x06, 0xef, 0x8b, 0xed, 0x9a, 0x4e, 0xbf,
46 0x3d, 0x9a, 0x4e, 0x37, 0x06, 0x3a, 0xa3, 0x4e, 0x76, 0x2e, 0xb6, 0x8c, 46 0x13, 0x74, 0xc6, 0x9c, 0xec, 0x89, 0xce, 0x45, 0x94, 0xd1, 0x6c, 0x7c,
47 0xb4, 0x2b, 0xfb, 0xe8, 0xed, 0x5b, 0xaa, 0xde, 0xeb, 0xa6, 0xde, 0x13, 47 0xec, 0x9c, 0xaa, 0xb7, 0x6e, 0xea, 0x3d, 0x1e, 0xd5, 0xed, 0xde, 0x9a,
48 0x5d, 0xba, 0xdd, 0xf8, 0xec, 0x58, 0x93, 0x69, 0x66, 0x76, 0x54, 0xa5, 48 0x1c, 0x6a, 0xb0, 0xfc, 0xc9, 0xe4, 0xa0, 0x2a, 0xdf, 0x99, 0x4c, 0xab,
49 0xd9, 0xd9, 0xb4, 0x4a, 0x73, 0xb3, 0x23, 0x2a, 0x9d, 0x99, 0xf5, 0x54, 49 0x52, 0xa6, 0x06, 0x54, 0xe9, 0x4c, 0x79, 0xaa, 0x7c, 0xc6, 0x3c, 0x7f,
50 0xfa, 0xb7, 0x0f, 0xe8, 0xfc, 0x37, 0x1e, 0x48, 0xaa, 0xf4, 0x67, 0x26, 50 0x6e, 0x32, 0xa9, 0xca, 0x86, 0x29, 0x2f, 0x99, 0xf2, 0x05, 0x53, 0xbe,
51 0x7d, 0xd3, 0xa4, 0x3f, 0x37, 0xe9, 0x5b, 0x26, 0xfd, 0x95, 0x49, 0x65, 51 0x68, 0xca, 0x97, 0x4c, 0xb9, 0x69, 0xca, 0x2b, 0x93, 0xba, 0x9f, 0x6f,
52 0x56, 0xa7, 0x8e, 0xe9, 0x27, 0x6a, 0xde, 0xfb, 0x4c, 0xea, 0x9a, 0x34, 52 0x9b, 0xfb, 0xef, 0x9a, 0xf2, 0x55, 0x53, 0xbe, 0x66, 0xca, 0xef, 0x99,
53 0x6e, 0xd2, 0x84, 0x49, 0x87, 0x0d, 0x5d, 0x49, 0x93, 0x7a, 0x26, 0x9d, 53 0xf2, 0xfb, 0x86, 0xae, 0xeb, 0xa6, 0x7c, 0xd3, 0x94, 0x3f, 0x32, 0xef,
54 0x34, 0xe5, 0xbe, 0xa1, 0x77, 0x1a, 0xf4, 0x7e, 0xa1, 0xcb, 0xc8, 0x2a, 54 0x7f, 0x6c, 0xe8, 0x7d, 0x1b, 0x74, 0xfd, 0x49, 0xd4, 0xc8, 0x2a, 0xe6,
55 0xe6, 0x9d, 0x94, 0x85, 0x8a, 0x23, 0xe5, 0x6a, 0x44, 0x0a, 0x6a, 0x0d, 55 0x9d, 0x94, 0xd9, 0x8a, 0x23, 0xf3, 0xcb, 0x11, 0x29, 0xa8, 0x35, 0xfc,
56 0x1f, 0xd9, 0x2f, 0x31, 0x47, 0x96, 0xb6, 0xa3, 0x72, 0x59, 0x89, 0xe8, 56 0xca, 0x5e, 0xe9, 0x74, 0x64, 0x61, 0x23, 0x26, 0xd7, 0x95, 0x88, 0xbe,
57 0x1b, 0xc1, 0x77, 0x0f, 0x4a, 0xc9, 0xce, 0xba, 0xf2, 0xc2, 0x76, 0x5c, 57 0x15, 0x7c, 0xeb, 0x80, 0x94, 0xed, 0xac, 0x2b, 0x97, 0x36, 0xe2, 0xf2,
58 0x5e, 0xda, 0x16, 0x6b, 0x2e, 0xd3, 0x2b, 0xf6, 0xe9, 0x77, 0x49, 0xce, 58 0xf2, 0x86, 0x58, 0xd3, 0x99, 0x0e, 0xb1, 0xcf, 0x7e, 0x40, 0x72, 0xae,
59 0xb5, 0x24, 0xa2, 0x78, 0x9a, 0x94, 0x7c, 0x65, 0x08, 0xef, 0xa9, 0x84, 59 0x25, 0x11, 0xc5, 0xd3, 0xa4, 0xe4, 0x2b, 0x7d, 0xb8, 0x4f, 0x25, 0x44,
60 0xc8, 0xe9, 0xfd, 0x7a, 0xfd, 0xa2, 0x12, 0x59, 0xe7, 0x9a, 0x3c, 0x3d, 60 0xae, 0xee, 0xd5, 0xeb, 0x17, 0x93, 0xc8, 0x2a, 0xd7, 0xe4, 0xfe, 0xa9,
61 0x7b, 0x71, 0x2d, 0x21, 0xce, 0xea, 0x24, 0xc6, 0xe8, 0x93, 0xae, 0x75, 61 0x6b, 0x2b, 0x09, 0x71, 0x96, 0x46, 0x31, 0x46, 0x97, 0x44, 0x57, 0xa5,
62 0x19, 0x8e, 0xc8, 0x68, 0xe2, 0x31, 0xd4, 0x98, 0x69, 0x3a, 0x72, 0xb8, 62 0x3f, 0x22, 0x83, 0x89, 0x4f, 0xa3, 0x46, 0xb1, 0xe1, 0xc8, 0x44, 0xc3,
63 0x69, 0x89, 0xe3, 0x45, 0x21, 0x1f, 0x7d, 0xf8, 0xb9, 0xf8, 0xc5, 0xf1, 63 0x12, 0xc7, 0x8b, 0x41, 0x3e, 0xba, 0xf0, 0x73, 0xf1, 0x8b, 0xe3, 0x97,
64 0x4b, 0xe0, 0xf7, 0x97, 0xe8, 0x67, 0x58, 0x0a, 0x4d, 0xf6, 0x89, 0x71, 64 0xc0, 0xef, 0x47, 0xe8, 0xa7, 0x5f, 0x0a, 0x0d, 0xf6, 0x89, 0x71, 0x97,
65 0xab, 0x18, 0xbf, 0x9a, 0x72, 0xe7, 0x85, 0x74, 0x25, 0xe4, 0xbb, 0x07, 65 0x31, 0xfe, 0x72, 0xca, 0x9d, 0x11, 0xd2, 0x95, 0x90, 0x6f, 0x1d, 0x20,
66 0x49, 0x97, 0x4b, 0x7a, 0x40, 0x5b, 0xd4, 0xca, 0xaf, 0xc9, 0x93, 0x05, 66 0x5d, 0x2e, 0xe9, 0x01, 0x6d, 0x31, 0x2b, 0xbf, 0x22, 0x27, 0x0a, 0xbe,
67 0x5f, 0x92, 0xb6, 0x17, 0x93, 0xa2, 0x6b, 0x25, 0x17, 0xc7, 0x07, 0xa5, 67 0x24, 0x6d, 0xaf, 0x53, 0x4a, 0xae, 0x95, 0x9c, 0x1b, 0xee, 0x95, 0xf2,
68 0x74, 0x14, 0xe5, 0x55, 0xc9, 0xd9, 0xe8, 0xbf, 0xe8, 0xca, 0xbc, 0x2e, 68 0x51, 0xbc, 0x5f, 0x96, 0x9c, 0x8d, 0xfe, 0x4b, 0xae, 0xcc, 0xe8, 0x77,
69 0x63, 0xde, 0x5b, 0xd8, 0xab, 0x29, 0x97, 0x42, 0xfb, 0x52, 0xf5, 0xdb, 69 0x7c, 0xf6, 0x36, 0xf6, 0x6a, 0xca, 0xa5, 0xd0, 0xbe, 0xbc, 0xfc, 0xb7,
70 0x78, 0x66, 0x7f, 0xff, 0xe0, 0x68, 0xba, 0x7f, 0x81, 0x77, 0xe6, 0xff, 70 0xb8, 0x66, 0x7f, 0x3f, 0x77, 0x34, 0xdd, 0x3f, 0xc5, 0x3d, 0x9f, 0x0f,
71 0x7d, 0x9f, 0x7e, 0xe7, 0x33, 0xeb, 0x86, 0xe3, 0x86, 0xf3, 0xe5, 0xf8, 71 0x99, 0x79, 0xf0, 0x9a, 0x75, 0xc3, 0x71, 0xc3, 0xf9, 0x72, 0xfc, 0x61,
72 0xe3, 0x98, 0x33, 0x69, 0x08, 0xe7, 0x2c, 0xa5, 0x2e, 0xd0, 0xd2, 0x58, 72 0xcc, 0x99, 0x34, 0x84, 0x73, 0x96, 0x72, 0x14, 0xb4, 0xd4, 0x57, 0xba,
73 0xeb, 0xb3, 0x36, 0xd6, 0x26, 0xe5, 0x64, 0xf5, 0x1e, 0xc9, 0xfb, 0x41, 73 0xac, 0xb5, 0x95, 0x51, 0x79, 0x62, 0xf9, 0x01, 0xc9, 0xfb, 0x41, 0x30,
74 0xb0, 0xe0, 0x4b, 0xdc, 0x96, 0x51, 0xb7, 0x80, 0x0a, 0xbb, 0x4d, 0xb1, 74 0xeb, 0x4b, 0xdc, 0x96, 0x41, 0xb7, 0x80, 0x0a, 0x5b, 0x0d, 0xb1, 0xea,
75 0x1a, 0x15, 0x89, 0xf6, 0x80, 0x2f, 0x3f, 0x59, 0x63, 0xdf, 0x0e, 0xf2, 75 0x15, 0x89, 0xb5, 0x83, 0x2f, 0x3f, 0x58, 0x61, 0xdf, 0x0e, 0x9e, 0xf5,
76 0x86, 0x50, 0xbf, 0xdf, 0xda, 0x5c, 0x03, 0xfd, 0x59, 0xf2, 0x27, 0x08, 76 0xa1, 0x7e, 0xb7, 0xb5, 0xbe, 0x02, 0xfa, 0xb3, 0xe4, 0x4f, 0x10, 0x2c,
77 0x96, 0xfd, 0xd1, 0xc4, 0x22, 0xc6, 0x3c, 0xdf, 0x1c, 0x9d, 0xbe, 0x22, 77 0xfa, 0x83, 0x89, 0x39, 0x8c, 0x79, 0xb9, 0x31, 0x38, 0x7e, 0x43, 0x5c,
78 0x2e, 0xfa, 0x1c, 0x44, 0x1d, 0xf2, 0x8a, 0x7d, 0xb1, 0x4f, 0xf6, 0xd7, 78 0xf4, 0xd9, 0x8b, 0x3a, 0xe4, 0x15, 0xfb, 0x62, 0x9f, 0xec, 0xaf, 0x0b,
79 0x87, 0xb6, 0x71, 0x94, 0x91, 0xae, 0x20, 0xc8, 0xfb, 0x2e, 0xdf, 0x65, 79 0x6d, 0xe3, 0x78, 0x47, 0xba, 0x82, 0x20, 0xef, 0xbb, 0xbc, 0x97, 0x4d,
80 0x07, 0xfc, 0xdb, 0x21, 0xff, 0x62, 0xc3, 0xf2, 0x4a, 0x93, 0x63, 0xec, 80 0xf0, 0x6f, 0x93, 0xfc, 0xeb, 0xec, 0x97, 0x57, 0x1a, 0x1c, 0x63, 0x37,
81 0x45, 0xfb, 0xc4, 0xff, 0x87, 0xb4, 0x27, 0xd0, 0x7f, 0x1c, 0xe9, 0x3e, 81 0xda, 0x47, 0xfe, 0x3f, 0xa4, 0x3d, 0x81, 0xfe, 0xe3, 0x28, 0xf7, 0x58,
82 0xab, 0x51, 0x0b, 0x30, 0x7e, 0x02, 0xcf, 0x7b, 0xcd, 0xe3, 0xb2, 0x5a, 82 0xf5, 0x6a, 0x80, 0xf1, 0x13, 0xb8, 0xde, 0x6d, 0x1e, 0xd7, 0xd5, 0xda,
83 0xfb, 0x17, 0xb0, 0xf6, 0x6e, 0x36, 0x2e, 0x2f, 0x6e, 0x0f, 0x63, 0x1e, 83 0x5f, 0xc2, 0xda, 0xbb, 0xd9, 0xb8, 0x3c, 0xbf, 0xd1, 0x8f, 0x79, 0x24,
84 0x09, 0xf9, 0x06, 0x64, 0x73, 0xe0, 0xce, 0x7d, 0x92, 0x86, 0x6c, 0x72, 84 0xe4, 0x1b, 0x90, 0xcd, 0x9e, 0x83, 0x7b, 0x24, 0x0d, 0xd9, 0xe4, 0x9a,
85 0xcd, 0xa7, 0xd6, 0x1f, 0x95, 0x62, 0x3c, 0x35, 0x4e, 0x3d, 0x9a, 0x9f, 85 0x8f, 0xad, 0xce, 0x49, 0x29, 0x9e, 0x1a, 0xa6, 0x1e, 0xcd, 0x8f, 0xed,
86 0xea, 0xc1, 0x7c, 0xb5, 0xb6, 0x1a, 0x59, 0x8d, 0x4b, 0x7a, 0x3d, 0x77, 86 0xc3, 0x7c, 0xb5, 0xb6, 0x1a, 0x58, 0xca, 0xed, 0xb7, 0xe5, 0x90, 0xd8,
87 0x83, 0x9e, 0x57, 0xdd, 0x92, 0x58, 0x49, 0xec, 0x73, 0x21, 0x6f, 0xc6, 87 0x59, 0x8c, 0x9b, 0x19, 0x01, 0x2d, 0x11, 0xbc, 0x8b, 0x8b, 0xb7, 0x9a,
88 0x4d, 0xbd, 0x96, 0x1c, 0x5b, 0xf6, 0x7a, 0x9f, 0x15, 0x59, 0x9f, 0x94, 88 0xc3, 0xb3, 0x54, 0xa2, 0x04, 0x1a, 0xe7, 0x41, 0x63, 0x49, 0xca, 0x62,
89 0x13, 0x7b, 0xf0, 0xa4, 0x01, 0x9e, 0xd8, 0xab, 0xa1, 0x9c, 0x3b, 0x78, 89 0x5f, 0x7c, 0xce, 0x0a, 0xf7, 0x8a, 0xe6, 0xdd, 0xb0, 0xe9, 0x67, 0x5b,
90 0x1f, 0x42, 0xdd, 0x7e, 0xcb, 0x59, 0xbf, 0x9e, 0x1f, 0x1b, 0xcd, 0x51, 90 0xce, 0x2d, 0x7b, 0xb5, 0xcb, 0x8a, 0xac, 0x8e, 0xca, 0xa9, 0x5d, 0x78,
91 0x7f, 0x17, 0xfc, 0xb0, 0xd7, 0x07, 0x51, 0xe7, 0x7a, 0x7e, 0x34, 0xc0, 91 0x56, 0x07, 0xcf, 0xec, 0xa5, 0x70, 0x1f, 0x38, 0xb8, 0xef, 0x43, 0xdd,
92 0x0f, 0x7b, 0x5d, 0xf3, 0xa2, 0x01, 0x5e, 0xd8, 0xa0, 0xb3, 0x01, 0x5e, 92 0x6e, 0xcb, 0x59, 0xbd, 0x95, 0x5f, 0x6b, 0x8d, 0x41, 0x7f, 0x0b, 0xfc,
93 0xd8, 0xa7, 0x35, 0x2f, 0x1a, 0x66, 0x4f, 0x9c, 0x51, 0xfa, 0x28, 0x07, 93 0xb2, 0x57, 0x7b, 0x51, 0xe7, 0x56, 0x7e, 0xd5, 0xc1, 0x2f, 0x7b, 0x55,
94 0x5a, 0x2d, 0xd1, 0x3a, 0x29, 0x27, 0xd4, 0x3d, 0x91, 0xec, 0x0c, 0xf6, 94 0xf3, 0xaa, 0x0e, 0x5e, 0xd9, 0x4b, 0x71, 0x94, 0x7b, 0x2c, 0xfb, 0xac,
95 0xb2, 0x8d, 0xb9, 0x3a, 0x32, 0x33, 0x65, 0xc9, 0x82, 0x2a, 0x9b, 0x91, 95 0xe6, 0x55, 0xdd, 0xec, 0x99, 0xf3, 0x4a, 0x5f, 0xe5, 0x40, 0xab, 0x25,
96 0x74, 0xf3, 0x5d, 0x60, 0xd4, 0xc4, 0x38, 0x2c, 0x41, 0xa9, 0x3b, 0xfb, 96 0x5a, 0x67, 0xe5, 0x84, 0xba, 0x29, 0x92, 0x2d, 0x62, 0xaf, 0xdb, 0xe0,
97 0x1d, 0x7b, 0xb7, 0x12, 0x95, 0x82, 0x93, 0x14, 0x6f, 0x95, 0xfd, 0xcc, 97 0x85, 0x23, 0xc5, 0x31, 0x4b, 0x66, 0xd5, 0xbb, 0xa2, 0xa4, 0x1b, 0x1f,
98 0xb7, 0xf5, 0x33, 0x8f, 0x7e, 0x76, 0xc1, 0x0f, 0x0b, 0xba, 0x93, 0x65, 98 0x00, 0x23, 0x47, 0x86, 0x61, 0x29, 0xca, 0x6d, 0xd9, 0x17, 0xed, 0xad,
99 0x8f, 0xaa, 0x7d, 0x9d, 0x5e, 0x77, 0x64, 0x74, 0x95, 0x75, 0x4a, 0xf6, 99 0x4a, 0x4c, 0x0a, 0x4e, 0x52, 0xbc, 0x25, 0xa5, 0xc7, 0x9b, 0xfa, 0x99,
100 0x85, 0xe6, 0xaf, 0x02, 0xdd, 0xef, 0xa3, 0x1c, 0xd3, 0xb5, 0xb3, 0xcb, 100 0x41, 0x3f, 0xdf, 0x01, 0x3f, 0x2c, 0xe8, 0x56, 0xbe, 0x7b, 0x4c, 0xed,
101 0xf6, 0xf9, 0xcd, 0x53, 0xf6, 0xcb, 0x4d, 0xf4, 0xdb, 0x24, 0xaf, 0xb1, 101 0xfb, 0xf4, 0xaa, 0x23, 0x83, 0x4b, 0xac, 0x53, 0xb6, 0xaf, 0x34, 0xde,
102 0x16, 0x55, 0xac, 0x45, 0x15, 0xeb, 0x62, 0xf6, 0x6c, 0x5d, 0xed, 0x9d, 102 0x09, 0x74, 0xbf, 0x8f, 0x71, 0x4c, 0xd7, 0xce, 0x2e, 0xda, 0x97, 0xd7,
103 0xa4, 0x59, 0x37, 0xd2, 0xc0, 0xb5, 0x4b, 0x60, 0xcd, 0xb8, 0x76, 0x62, 103 0x4f, 0xdb, 0x57, 0x1b, 0xe8, 0xb7, 0xc1, 0xb5, 0xc0, 0x5a, 0x2d, 0x63,
104 0xbd, 0x9a, 0xd9, 0x27, 0x91, 0xd3, 0x11, 0xb5, 0x66, 0x03, 0xeb, 0x1f, 104 0xad, 0x96, 0xb1, 0x6e, 0x66, 0x4f, 0xd7, 0xd4, 0xde, 0x4a, 0x9a, 0x75,
105 0x68, 0xad, 0xd9, 0xc8, 0xd4, 0x81, 0xd6, 0x9a, 0xd9, 0xab, 0xb9, 0x5b, 105 0x25, 0x0d, 0x5c, 0xdb, 0x04, 0xd6, 0x94, 0x6b, 0x2b, 0xd6, 0xab, 0x99,
106 0x6c, 0x39, 0x24, 0x76, 0x16, 0xfc, 0xc9, 0x4c, 0x80, 0x5f, 0x11, 0x94, 106 0x3d, 0x12, 0x39, 0x1b, 0x51, 0x6b, 0xda, 0xb3, 0xfa, 0x91, 0xed, 0x35,
107 0xc5, 0xc5, 0x59, 0xcf, 0x21, 0x2f, 0x95, 0x28, 0x82, 0x8f, 0x65, 0xf0, 107 0x1d, 0x68, 0x5a, 0x53, 0xfb, 0x5d, 0xd6, 0xd4, 0xd9, 0x65, 0x4d, 0xb7,
108 0xb1, 0x28, 0x25, 0xc8, 0xcc, 0xcf, 0x2c, 0xad, 0xdf, 0x7e, 0x29, 0x46, 108 0x1a, 0x3f, 0x31, 0x6b, 0xfa, 0x73, 0x31, 0xb2, 0xff, 0x9e, 0xfc, 0x1a,
109 0xb6, 0xdf, 0x91, 0x5f, 0x23, 0xe0, 0x97, 0xf7, 0x3b, 0xf0, 0xcb, 0xd9, 109 0x00, 0xbf, 0xbc, 0x5f, 0x83, 0x5f, 0xce, 0xae, 0xfc, 0xea, 0xb3, 0x5b,
110 0x93, 0x5f, 0xfd, 0x76, 0x27, 0xbf, 0x22, 0xe0, 0x57, 0xd7, 0xef, 0xcc, 110 0xf9, 0x15, 0x01, 0xbf, 0xa2, 0xbf, 0x36, 0xbf, 0xc0, 0x87, 0x5d, 0x79,
111 0x2f, 0xf0, 0x61, 0x4f, 0x5e, 0x45, 0xa1, 0xd7, 0x4a, 0x92, 0xcf, 0x88, 111 0x15, 0x83, 0xde, 0x2b, 0x4b, 0x3e, 0x23, 0x92, 0xaf, 0x6a, 0x5d, 0x5d,
112 0xe4, 0x6b, 0x5a, 0x17, 0x97, 0x94, 0x4e, 0xa6, 0x2e, 0x0a, 0x75, 0x32, 112 0x56, 0x3a, 0x9b, 0xba, 0x2a, 0xd4, 0xd9, 0xd4, 0xd7, 0x6a, 0x9f, 0x58,
113 0xf5, 0xb1, 0xda, 0x07, 0x56, 0xa1, 0x92, 0x84, 0xae, 0x74, 0x90, 0x3e, 113 0x85, 0x4a, 0x12, 0xba, 0xd4, 0x41, 0xf9, 0x1c, 0xca, 0x3d, 0xd6, 0x74,
114 0x8f, 0x74, 0x9f, 0x35, 0x57, 0x83, 0x68, 0xf5, 0x07, 0xe2, 0x4e, 0x85, 114 0xb5, 0x1f, 0x76, 0x36, 0x10, 0x77, 0x2c, 0xb4, 0x97, 0xe5, 0x84, 0x8b,
115 0xf6, 0xb0, 0x94, 0x70, 0xb1, 0x36, 0xee, 0xfb, 0xba, 0x44, 0x86, 0x52, 115 0xb5, 0x71, 0xef, 0x8a, 0x8a, 0xf4, 0xa5, 0xc0, 0xa7, 0x14, 0xde, 0xa7,
116 0xe0, 0xd3, 0xcd, 0x28, 0x4f, 0x25, 0x72, 0x92, 0xb1, 0x43, 0xdc, 0x92, 116 0x12, 0x39, 0xc9, 0xda, 0x21, 0xae, 0xc9, 0x57, 0x3a, 0xde, 0xce, 0xa9,
117 0xaf, 0xf4, 0xbe, 0x95, 0x53, 0x4f, 0xcc, 0x67, 0xbb, 0x0c, 0xf2, 0xba, 117 0x2b, 0x3e, 0x67, 0xbb, 0x0c, 0x9e, 0x45, 0x65, 0x06, 0x76, 0xa0, 0xe8,
118 0x64, 0x1e, 0x7a, 0x7e, 0xc6, 0xe3, 0x78, 0xec, 0x3f, 0x39, 0xcf, 0x71, 118 0x71, 0x3c, 0xf6, 0x9f, 0x9c, 0xe1, 0xb8, 0x85, 0x46, 0xa8, 0xb3, 0x25,
119 0x0b, 0xcd, 0x50, 0x27, 0x4b, 0x0e, 0x36, 0x1a, 0x65, 0xdc, 0x97, 0xd3, 119 0x07, 0x1b, 0x8e, 0x77, 0xdc, 0xb7, 0xe3, 0x56, 0x41, 0xd9, 0xa0, 0x8c,
120 0x56, 0x41, 0xdb, 0x46, 0xf1, 0x9a, 0xed, 0xf6, 0xa3, 0x45, 0x27, 0xf6, 120 0x78, 0x8d, 0x66, 0xfb, 0xb2, 0x4d, 0x27, 0xf6, 0x73, 0x0e, 0x72, 0x4d,
121 0x6b, 0x8e, 0x72, 0x8d, 0xb1, 0x93, 0xd8, 0x73, 0xe5, 0x48, 0xb8, 0x3e, 121 0xda, 0x92, 0xd8, 0x7b, 0xc7, 0x22, 0xe1, 0xfa, 0x38, 0xd9, 0x71, 0x81,
122 0x4e, 0x76, 0x5a, 0x60, 0x77, 0xa5, 0x5c, 0x61, 0x7f, 0x9f, 0xb1, 0x22, 122 0x5d, 0x96, 0xf9, 0x0a, 0xfb, 0xfb, 0x63, 0x2b, 0x72, 0x31, 0xec, 0x9f,
123 0xe7, 0xc2, 0xfe, 0xc9, 0x47, 0xf6, 0xad, 0xfb, 0x2b, 0x37, 0xdf, 0x30, 123 0x7c, 0x64, 0xdf, 0xba, 0xbf, 0xf9, 0xc6, 0x5b, 0x46, 0x37, 0x28, 0x5b,
124 0x7b, 0x5f, 0xd9, 0x22, 0xf4, 0x57, 0x6a, 0xeb, 0xaf, 0x64, 0x45, 0x56, 124 0x85, 0xfe, 0xca, 0x4d, 0xfd, 0x95, 0xad, 0xc8, 0x92, 0xec, 0x53, 0xf6,
125 0xe5, 0x80, 0xd2, 0xf7, 0x47, 0xc9, 0xbf, 0x53, 0x28, 0xbb, 0x2c, 0x11, 125 0xe0, 0x28, 0xf9, 0x77, 0x1a, 0xef, 0xae, 0x4b, 0x84, 0x32, 0xa3, 0xf6,
126 0xca, 0x8c, 0xda, 0x63, 0xdc, 0xe7, 0x9f, 0xe5, 0x7c, 0xdb, 0x78, 0x3b, 126 0x18, 0xf7, 0xfb, 0x97, 0x38, 0xdf, 0x26, 0xde, 0x4e, 0xc3, 0xc6, 0x71,
127 0x07, 0x1b, 0xc6, 0xfd, 0x85, 0x35, 0x8e, 0x33, 0xff, 0x2e, 0x43, 0x93, 127 0x7f, 0x61, 0x8d, 0xe3, 0x7c, 0x7e, 0xc8, 0xd0, 0xe4, 0x48, 0x4e, 0xdd,
128 0x23, 0x39, 0xf5, 0xfe, 0xb5, 0x7d, 0xa1, 0x7e, 0xc4, 0x7e, 0x06, 0x6d, 128 0x7f, 0x63, 0x4f, 0xa8, 0x3f, 0xb1, 0x9f, 0x41, 0xdb, 0x8b, 0x6a, 0x8e,
129 0xdf, 0x51, 0x73, 0xb4, 0xb3, 0x59, 0xf0, 0xa6, 0x9d, 0x46, 0x85, 0x05, 129 0x76, 0x36, 0x0b, 0xde, 0x34, 0xd3, 0xc8, 0x79, 0x67, 0xb1, 0xc6, 0xa1,
130 0xb0, 0xc6, 0xa1, 0x8e, 0x0a, 0xd7, 0x8a, 0xb8, 0xc5, 0xb1, 0x96, 0x2a, 130 0x0e, 0x0b, 0xd7, 0x8a, 0xb8, 0xc6, 0xb1, 0x16, 0x2a, 0x5d, 0xb0, 0x8f,
131 0x7d, 0xb0, 0x7f, 0x51, 0x63, 0x63, 0xd9, 0x7e, 0x19, 0xed, 0x99, 0xcf, 131 0x31, 0x63, 0x83, 0xd9, 0x7e, 0x11, 0xed, 0xf9, 0x9c, 0x6d, 0xbb, 0x60,
132 0xb6, 0x7d, 0xb0, 0xb7, 0x6c, 0xbf, 0x6c, 0xda, 0x5f, 0xb5, 0xbb, 0xdc, 132 0x8f, 0xd9, 0x7e, 0xd1, 0xb4, 0xdf, 0xb1, 0xcb, 0xdc, 0x2b, 0xb4, 0xc9,
133 0x2b, 0xb4, 0xb9, 0x17, 0x32, 0xc0, 0x3a, 0x6b, 0xb6, 0x14, 0x7c, 0xe0, 133 0x57, 0x32, 0xc0, 0x42, 0x2b, 0xb6, 0x14, 0x7c, 0xe0, 0x1c, 0xbf, 0xdf,
134 0x18, 0x7f, 0xd8, 0xec, 0x0b, 0x2d, 0x9b, 0xf7, 0x3a, 0x96, 0xf4, 0x78, 134 0xec, 0x0b, 0x2d, 0x9b, 0x1f, 0x75, 0x2c, 0x69, 0xf7, 0x76, 0x93, 0xcd,
135 0x7b, 0xc9, 0xe6, 0xcb, 0xb6, 0xb6, 0x65, 0x57, 0x65, 0x73, 0x09, 0x3a, 135 0x7f, 0xb0, 0xb5, 0xad, 0xdb, 0x91, 0xcd, 0x05, 0xe8, 0xa8, 0x53, 0x90,
136 0xea, 0x04, 0x64, 0x65, 0xb9, 0x55, 0x8f, 0x72, 0xa9, 0x64, 0x14, 0xb2, 136 0x95, 0xc5, 0xed, 0x7a, 0x94, 0x4b, 0x25, 0xa3, 0x90, 0xcd, 0xd4, 0x38,
137 0x99, 0x9a, 0xe6, 0x34, 0x2f, 0x34, 0xdb, 0x65, 0x34, 0xec, 0x23, 0xaa, 137 0xa7, 0x79, 0xa5, 0xd1, 0x2c, 0xa3, 0x61, 0x1f, 0x31, 0x25, 0x07, 0x7a,
138 0xe4, 0x40, 0x8f, 0xb3, 0xdc, 0x36, 0xce, 0x72, 0xdb, 0x38, 0x27, 0x0d, 138 0x9c, 0xc5, 0xa6, 0x71, 0x16, 0x9b, 0xc6, 0x59, 0x32, 0xd8, 0x8e, 0xfd,
139 0x76, 0x63, 0x3f, 0xda, 0x6e, 0x5e, 0xbe, 0xc6, 0x5e, 0x73, 0xcd, 0x3e, 139 0x68, 0xbb, 0x7a, 0xfd, 0x26, 0x7b, 0xce, 0x35, 0xfb, 0x24, 0xf6, 0xa4,
140 0x8a, 0x3d, 0xa9, 0x65, 0x01, 0x58, 0x4c, 0xaf, 0x41, 0xc5, 0x95, 0xf2, 140 0x96, 0x05, 0x60, 0x35, 0xbd, 0x06, 0x15, 0x57, 0xe6, 0x37, 0x2e, 0x84,
141 0xf6, 0xd9, 0x70, 0xaf, 0x96, 0x7a, 0x90, 0xff, 0x53, 0xe4, 0x8f, 0xaf, 141 0x7b, 0xb5, 0xdc, 0x8e, 0xe7, 0x3f, 0xc4, 0xf3, 0xe1, 0x33, 0x2e, 0xec,
142 0xb8, 0xb0, 0x43, 0xc4, 0x62, 0x7f, 0x25, 0x5b, 0x15, 0xca, 0xc8, 0x77, 142 0x14, 0xb1, 0xda, 0x4b, 0x72, 0xae, 0x42, 0x19, 0x79, 0x11, 0x74, 0xa7,
143 0x40, 0x77, 0xda, 0xef, 0xb6, 0xc8, 0xd7, 0xd4, 0xf8, 0x19, 0x49, 0x25, 143 0xfd, 0x36, 0x8b, 0x7c, 0x4d, 0x0d, 0x9f, 0x97, 0x54, 0x72, 0x5e, 0x46,
144 0xcb, 0x32, 0xe1, 0x33, 0x3d, 0x49, 0x45, 0x8d, 0x7a, 0x1a, 0xe3, 0x7c, 144 0x7c, 0x96, 0x4f, 0x88, 0xc2, 0x58, 0xa2, 0x31, 0xd0, 0x8b, 0x90, 0x3f,
145 0x07, 0xf2, 0x27, 0xf2, 0x66, 0xa5, 0x47, 0xec, 0xa9, 0x9f, 0x06, 0xb4, 145 0x91, 0x1f, 0x57, 0xda, 0xc5, 0x1e, 0xfb, 0x61, 0x40, 0x3b, 0x78, 0x7a,
146 0x73, 0xa7, 0xb6, 0x3b, 0xfb, 0x11, 0x19, 0x5b, 0x51, 0xfd, 0xa0, 0x8f, 146 0xa3, 0xb5, 0x1f, 0x91, 0xa1, 0x33, 0xaa, 0x1f, 0xf4, 0x91, 0xf6, 0xbf,
147 0xb4, 0x7f, 0x49, 0xf5, 0x17, 0xf6, 0x85, 0x79, 0x4e, 0x75, 0xf6, 0xe7, 147 0xad, 0xfa, 0x0b, 0xfb, 0xc2, 0x3c, 0xc7, 0x5a, 0xfb, 0x73, 0xe4, 0xba,
148 0xc8, 0x65, 0xd7, 0x46, 0x7f, 0xb7, 0x98, 0x39, 0xf2, 0x19, 0x32, 0xe2, 148 0x6b, 0xa3, 0xbf, 0xb4, 0x99, 0x23, 0xaf, 0x21, 0x23, 0xae, 0x83, 0xf2,
149 0x3a, 0x48, 0xef, 0xb3, 0x43, 0x99, 0xb1, 0xa7, 0xfe, 0x3a, 0xc8, 0xcd, 149 0x61, 0x3b, 0x94, 0x19, 0x7b, 0xec, 0x3b, 0x41, 0x6e, 0x9a, 0x73, 0x2b,
150 0x71, 0x6e, 0xff, 0xcc, 0xe4, 0xfd, 0x47, 0x23, 0x6f, 0x52, 0xb3, 0xb3, 150 0x99, 0x67, 0xff, 0xc3, 0xc8, 0x9b, 0x54, 0xed, 0x2c, 0x78, 0x96, 0x19,
151 0xe0, 0x59, 0x66, 0x14, 0xe3, 0xf1, 0x3d, 0x09, 0xfc, 0x23, 0x25, 0xe2, 151 0xc4, 0x78, 0xbc, 0x4f, 0x02, 0x1f, 0x49, 0x99, 0xf8, 0xac, 0x54, 0xf9,
152 0xaf, 0x62, 0xe5, 0x37, 0x41, 0xce, 0xd1, 0x98, 0x49, 0xaf, 0x3d, 0xcb, 152 0x65, 0x90, 0x73, 0x34, 0xa6, 0xd2, 0x6b, 0xcf, 0xf7, 0x96, 0x14, 0x50,
153 0x2d, 0x29, 0xa0, 0xee, 0x92, 0xd1, 0x07, 0x33, 0xcd, 0xcb, 0x8a, 0x7f, 153 0x77, 0xc1, 0xe8, 0x83, 0x62, 0xe3, 0xba, 0xe2, 0xdf, 0xf3, 0x6a, 0x1f,
154 0x2f, 0xaa, 0x7d, 0x94, 0x3a, 0x55, 0xa2, 0xde, 0xd8, 0x8e, 0x46, 0xb8, 154 0xa5, 0x4e, 0x97, 0xa9, 0x37, 0x36, 0xdc, 0x08, 0xf7, 0xf8, 0x25, 0xff,
155 0xc7, 0x5f, 0xf0, 0x37, 0x83, 0xa5, 0x6a, 0x2a, 0x99, 0xb4, 0x47, 0xa5, 155 0xa5, 0x60, 0x61, 0x39, 0x95, 0x4c, 0xda, 0x83, 0x52, 0xaa, 0x0e, 0x96,
156 0x58, 0x1b, 0x2d, 0xd9, 0x48, 0x9f, 0xac, 0x27, 0xe4, 0xc9, 0x0a, 0xfb, 156 0x6d, 0x94, 0x27, 0x6a, 0x09, 0x39, 0x51, 0x61, 0x3f, 0xfb, 0x51, 0x07,
157 0xb9, 0x01, 0x75, 0xa0, 0x88, 0x6c, 0x6c, 0xf2, 0x21, 0xea, 0x1a, 0x8e, 157 0x8a, 0xc8, 0xc6, 0x26, 0xef, 0xa3, 0xae, 0xe1, 0x98, 0x6f, 0x5b, 0x7a,
158 0xf9, 0x96, 0xa5, 0xc7, 0xc4, 0x1c, 0xbc, 0x1d, 0xeb, 0x93, 0xcd, 0x0b, 158 0x4c, 0xcc, 0xc1, 0xdb, 0xb4, 0xfe, 0x63, 0xe3, 0x8a, 0x55, 0xaa, 0x71,
159 0x56, 0xb1, 0xce, 0xf5, 0x47, 0x7e, 0xb3, 0x5d, 0x1f, 0xb5, 0xeb, 0xed, 159 0xfd, 0xf1, 0xbc, 0xd1, 0xac, 0x8f, 0x42, 0x5d, 0xb4, 0x83, 0xc5, 0x22,
160 0x50, 0x5f, 0xeb, 0xb5, 0x73, 0xb0, 0xef, 0x6a, 0x95, 0x65, 0xab, 0xbc, 160 0xd9, 0x45, 0xab, 0xb4, 0x22, 0x76, 0xde, 0x8f, 0x12, 0x0f, 0x26, 0x45,
161 0x26, 0x76, 0xde, 0xef, 0x32, 0xf2, 0x68, 0xb9, 0x7a, 0xce, 0x4f, 0x46, 161 0xee, 0x75, 0xf5, 0x3c, 0x3f, 0x19, 0xa1, 0x1e, 0x74, 0xbc, 0xd3, 0xe8,
162 0xa8, 0x13, 0x23, 0xde, 0x29, 0xab, 0x5c, 0xb9, 0x55, 0x72, 0x0e, 0x31, 162 0xbb, 0x53, 0x72, 0x0e, 0xd7, 0x9f, 0xd7, 0x12, 0x44, 0xb2, 0x1e, 0x6d,
163 0x1c, 0x9f, 0x25, 0x88, 0x64, 0x3d, 0xda, 0x4d, 0x27, 0x92, 0x4d, 0x63, 163 0xa5, 0x13, 0xc9, 0x3a, 0xd8, 0x63, 0xac, 0xf3, 0x52, 0xc0, 0xbd, 0x90,
164 0xbf, 0xb1, 0xce, 0x66, 0xf0, 0x65, 0x8c, 0x33, 0x72, 0x1a, 0xfa, 0xd9, 164 0xaf, 0x6a, 0x19, 0x29, 0xef, 0x60, 0x2f, 0xd0, 0x9b, 0x83, 0x8e, 0x11,
165 0x7f, 0x0f, 0xfa, 0xe1, 0xf8, 0xbd, 0x78, 0x77, 0xcc, 0xbe, 0xec, 0x42, 165 0x1b, 0x7b, 0xcc, 0x8d, 0x64, 0xf9, 0x7c, 0x1c, 0xd7, 0x9b, 0xa8, 0x4f,
166 0xbd, 0x14, 0x36, 0xf7, 0xc5, 0x7e, 0xe9, 0x7f, 0x06, 0x7a, 0x36, 0xec, 166 0x1d, 0x0b, 0x4c, 0x5a, 0x53, 0xbc, 0xc3, 0x58, 0x39, 0xab, 0x58, 0x09,
167 0x9b, 0x75, 0x12, 0xa6, 0x4e, 0x9f, 0xa9, 0x73, 0x37, 0xca, 0x3f, 0x86, 167 0x79, 0xf2, 0x52, 0xf0, 0xe4, 0x72, 0x88, 0x11, 0x94, 0x6c, 0xc9, 0xc0,
168 0x7a, 0x29, 0x9f, 0xd0, 0x16, 0x29, 0xf2, 0x06, 0x31, 0x47, 0xd4, 0x6d, 168 0xd9, 0xa4, 0xd9, 0xd7, 0x5d, 0xdc, 0x73, 0xe4, 0x3f, 0x9e, 0xf9, 0xe6,
169 0xdc, 0x60, 0xde, 0xc3, 0xf6, 0x77, 0xb6, 0xd5, 0xe5, 0xfb, 0xb5, 0x7a, 169 0x59, 0x7b, 0xd3, 0xb3, 0x70, 0xff, 0x7f, 0x09, 0xb4, 0xf5, 0x2b, 0xfe,
170 0x78, 0xbe, 0xa5, 0x87, 0xc9, 0xc3, 0x1c, 0xf4, 0x9e, 0xd8, 0xd8, 0xf7, 170 0xd8, 0xd9, 0x23, 0x56, 0x5e, 0xe1, 0x93, 0x20, 0x28, 0x78, 0x51, 0x29,
171 0x6e, 0x24, 0xcb, 0xfc, 0x69, 0x3c, 0x3f, 0x1f, 0x94, 0xab, 0xd4, 0xfb, 171 0x8d, 0xfe, 0x09, 0xe6, 0xca, 0x77, 0x65, 0x30, 0x9c, 0x76, 0x63, 0x78,
172 0xc0, 0xc1, 0x75, 0xa5, 0xff, 0xd0, 0x6f, 0xce, 0x9a, 0xa9, 0x84, 0xeb, 172 0x72, 0xd6, 0x4b, 0x29, 0xfb, 0x9f, 0xc7, 0xfe, 0xd3, 0x3a, 0x53, 0xca,
173 0xc4, 0x79, 0x85, 0xb8, 0x44, 0xf1, 0x0c, 0xf4, 0x26, 0xaf, 0xd2, 0xeb, 173 0x3d, 0xa0, 0xdd, 0x5b, 0xe2, 0x9a, 0xbc, 0x14, 0x9c, 0x05, 0x16, 0x9e,
174 0x2a, 0x99, 0x40, 0x9e, 0x6f, 0xf2, 0x7a, 0xda, 0xf2, 0x42, 0x9d, 0xf4, 174 0x5e, 0x2a, 0x5a, 0x03, 0xd8, 0x12, 0x76, 0x9f, 0x05, 0x3e, 0x77, 0x49,
175 0x05, 0xcc, 0x6b, 0x58, 0xad, 0x99, 0x9d, 0x3d, 0x62, 0xe5, 0x15, 0x26, 175 0xfe, 0x22, 0xd7, 0x82, 0x75, 0xf8, 0xbc, 0x4d, 0xa6, 0xe3, 0xad, 0xb6,
176 0x0a, 0x82, 0x82, 0xd7, 0x25, 0xc5, 0xc9, 0xa7, 0xc1, 0x2b, 0x96, 0x95, 176 0xf2, 0xdc, 0x3e, 0xe9, 0x24, 0xbf, 0x51, 0x77, 0xe9, 0xff, 0x46, 0xb4,
177 0xdc, 0x88, 0xc2, 0xf1, 0x73, 0x0f, 0x2c, 0x78, 0x29, 0x85, 0x49, 0xf2, 177 0x5e, 0x76, 0x65, 0x60, 0x95, 0x7c, 0x2f, 0x5a, 0xb3, 0x15, 0xea, 0xb1,
178 0xd0, 0x09, 0x5a, 0x8f, 0x4b, 0x69, 0x00, 0xb4, 0x7b, 0xab, 0xe4, 0xc5, 178 0x0e, 0xd8, 0x47, 0x3e, 0x67, 0x9f, 0x78, 0x77, 0xbe, 0xb5, 0x8f, 0xdf,
179 0x66, 0x70, 0x1a, 0xf8, 0x7b, 0x6e, 0x75, 0xc6, 0x1a, 0x59, 0xc5, 0xba, 179 0x8b, 0xe8, 0x3e, 0xd8, 0x2e, 0xec, 0xa3, 0x99, 0x1f, 0x7b, 0x94, 0x9e,
180 0x0f, 0x59, 0xe0, 0x4b, 0x9f, 0xe4, 0xcf, 0x91, 0x2f, 0xac, 0xc3, 0xfc, 180 0xeb, 0xcd, 0xf6, 0xb6, 0xf4, 0x9b, 0x68, 0xea, 0x17, 0xef, 0xce, 0x7f,
181 0x6e, 0x99, 0x8b, 0x77, 0xda, 0xef, 0x3f, 0x3e, 0x20, 0x31, 0xf2, 0x01, 181 0x37, 0x42, 0x5c, 0xf6, 0xf2, 0x32, 0xf8, 0xac, 0xe6, 0xc4, 0x77, 0x6c,
182 0x75, 0x57, 0x21, 0xec, 0x31, 0x8d, 0x89, 0x47, 0xd6, 0x29, 0x47, 0x33, 182 0x53, 0xb4, 0x0a, 0x4b, 0x41, 0x30, 0xed, 0xdb, 0x12, 0xe9, 0x0b, 0xeb,
183 0xd6, 0x42, 0x85, 0xba, 0xb5, 0x17, 0x36, 0x5b, 0xad, 0x3f, 0xfa, 0x44, 183 0xea, 0x79, 0x15, 0x31, 0xaf, 0x3c, 0xe6, 0x65, 0xf7, 0xb5, 0xd2, 0xf4,
184 0xd9, 0x99, 0xce, 0x3e, 0x3e, 0x1d, 0xd1, 0x7d, 0xb0, 0x5d, 0xd8, 0x47, 184 0xfb, 0x86, 0xa6, 0xde, 0x26, 0x9a, 0xe2, 0xef, 0x31, 0xaf, 0xf8, 0x2e,
185 0x3b, 0x3f, 0xf6, 0x29, 0xdd, 0x3b, 0x98, 0x1d, 0xec, 0xe8, 0x37, 0xd1, 185 0xf3, 0x7a, 0xa9, 0x57, 0xf7, 0x11, 0x6f, 0xea, 0xa3, 0xaf, 0xa5, 0x0f,
186 0xd6, 0x2f, 0xca, 0xce, 0xfc, 0x34, 0x42, 0x2c, 0xf8, 0x52, 0x15, 0x7c, 186 0xe8, 0xfd, 0x38, 0xdb, 0xf7, 0xed, 0xd2, 0xfe, 0x87, 0x1d, 0xba, 0x3d,
187 0x56, 0x73, 0x62, 0x19, 0xdb, 0xcc, 0x58, 0x85, 0xd5, 0x20, 0x98, 0xf3, 187 0xdb, 0xb4, 0x41, 0xb7, 0xf7, 0x1b, 0xbd, 0x78, 0xa2, 0x49, 0x97, 0x9d,
188 0x6d, 0x89, 0x0c, 0x85, 0x75, 0xf5, 0xbc, 0x66, 0x30, 0xaf, 0x3c, 0xe6, 188 0x80, 0x2e, 0x6b, 0x6e, 0xd3, 0x2c, 0xff, 0xa1, 0x8f, 0x44, 0xff, 0x28,
189 0x65, 0x0f, 0x75, 0xd2, 0xf4, 0x39, 0x43, 0xd3, 0x60, 0x1b, 0x4d, 0xf1, 189 0xc4, 0x8a, 0x1f, 0x50, 0x18, 0x64, 0x07, 0x63, 0xc7, 0x80, 0x47, 0xba,
190 0x77, 0x98, 0x57, 0x7c, 0x8f, 0x79, 0x9d, 0x1c, 0xd4, 0x7d, 0xc4, 0xdb, 190 0x60, 0xff, 0xbb, 0xe9, 0x07, 0x19, 0x4c, 0x48, 0xbf, 0x88, 0x38, 0x50,
191 0xfa, 0x18, 0xea, 0xe8, 0x03, 0xb6, 0x28, 0xce, 0xf6, 0x43, 0x7b, 0xb4, 191 0x3c, 0xa0, 0x28, 0xe8, 0x96, 0xc1, 0xc4, 0x31, 0x11, 0xe5, 0x07, 0x11,
192 0xff, 0x49, 0xaf, 0x6e, 0xcf, 0x36, 0xdd, 0xb0, 0x37, 0xc3, 0x46, 0x57, 192 0x5f, 0xd3, 0x27, 0xe2, 0x38, 0xf4, 0x89, 0xb8, 0xee, 0xbc, 0x2f, 0x6c,
193 0x3f, 0xd9, 0xa6, 0x5f, 0x9f, 0x84, 0x7e, 0x6d, 0x6f, 0x13, 0xca, 0x65, 193 0xfb, 0x48, 0xfd, 0xd8, 0xf7, 0xc4, 0xc7, 0xdc, 0x33, 0xa1, 0xad, 0x69,
194 0xbb, 0x5f, 0x46, 0x9f, 0x2c, 0xc4, 0xaf, 0xef, 0x52, 0xb8, 0xe8, 0x2a, 194 0xd6, 0xa7, 0xbb, 0xd1, 0xd4, 0xdf, 0x42, 0x13, 0x74, 0x12, 0x7c, 0xb3,
195 0xae, 0x8f, 0x02, 0x23, 0xf5, 0x01, 0x93, 0xf4, 0xd3, 0xf7, 0x32, 0x38, 195 0x05, 0xc8, 0x23, 0x30, 0x29, 0x74, 0xe0, 0xfd, 0x53, 0xe7, 0x56, 0x44,
196 0x95, 0xbe, 0x18, 0xb1, 0xa9, 0x78, 0x40, 0x76, 0xd0, 0x77, 0xa3, 0x89, 196 0x4a, 0x0d, 0xda, 0xc7, 0x51, 0x81, 0x5f, 0x05, 0xba, 0xd8, 0xb7, 0xb2,
197 0x63, 0x22, 0xca, 0xf7, 0x22, 0xa6, 0xa7, 0x1f, 0xc6, 0x71, 0xe8, 0x87, 197 0x91, 0xd0, 0x4d, 0xdd, 0x39, 0x3b, 0x3b, 0x08, 0x3f, 0xdc, 0x91, 0x39,
198 0x71, 0xdd, 0xf9, 0x5e, 0x68, 0xf9, 0x65, 0xc3, 0xd0, 0x45, 0xc4, 0xe4, 198 0x43, 0xdb, 0x8c, 0xf2, 0xe1, 0xba, 0x50, 0x26, 0x94, 0x5c, 0xcd, 0x80,
199 0xc4, 0xaf, 0xa1, 0xfd, 0x6b, 0xd7, 0xf1, 0x7b, 0xd1, 0x34, 0xdc, 0x41, 199 0x3e, 0x5e, 0xcf, 0x18, 0xec, 0x7e, 0xac, 0xd1, 0x4a, 0xdb, 0xf7, 0x40,
200 0x13, 0xf4, 0x24, 0xfc, 0xc1, 0x25, 0xc8, 0x23, 0x70, 0x32, 0xf4, 0xf2, 200 0x9b, 0x07, 0x1a, 0x92, 0xf2, 0x02, 0xb0, 0xfb, 0x37, 0xd5, 0xbe, 0x0c,
201 0xd3, 0xb3, 0x5b, 0x6b, 0x22, 0xc5, 0x26, 0x6d, 0xf6, 0xa4, 0xc0, 0x97, 201 0x75, 0x17, 0x65, 0x29, 0x55, 0x2d, 0xcb, 0x66, 0xb0, 0xb2, 0xcc, 0x7d,
202 0x03, 0x5d, 0xec, 0x5b, 0xd9, 0x6d, 0xe8, 0xcb, 0xfe, 0x9c, 0x9d, 0x1d, 202 0x4b, 0x1b, 0xde, 0x25, 0x65, 0xac, 0xd7, 0xc0, 0x52, 0x2a, 0x99, 0xb3,
203 0x85, 0xef, 0xef, 0xc8, 0xa2, 0xa1, 0x6d, 0x5e, 0xf9, 0x8d, 0x7d, 0x48, 203 0xc5, 0x7a, 0xdf, 0x41, 0xca, 0xd3, 0xe3, 0x32, 0x70, 0x51, 0x2c, 0x67,
204 0x13, 0x4a, 0xae, 0xe6, 0x41, 0x1f, 0x9f, 0xe7, 0x8d, 0xbf, 0x70, 0xac, 204 0x09, 0x7b, 0xbd, 0x3b, 0xc4, 0x57, 0x9c, 0xdf, 0x6f, 0x63, 0x7e, 0xe8,
205 0xd9, 0x49, 0xdb, 0x0f, 0x41, 0x9b, 0x07, 0x1a, 0x92, 0xf2, 0x2d, 0xf8, 205 0x7b, 0x39, 0x9c, 0x5f, 0x97, 0x94, 0x56, 0x39, 0xbf, 0xed, 0xb9, 0xc5,
206 0x0b, 0xdf, 0x54, 0xfb, 0x32, 0xd4, 0x67, 0x4a, 0x57, 0xd4, 0x4a, 0xf2, 206 0x19, 0x11, 0xf9, 0x1c, 0xf4, 0x35, 0xe6, 0x08, 0x1a, 0xc7, 0x81, 0x73,
207 0x7c, 0xb0, 0x56, 0xe5, 0xbe, 0x25, 0xae, 0xe8, 0x93, 0x12, 0xd6, 0x6b, 207 0xef, 0x30, 0x73, 0xea, 0xc2, 0x9c, 0x60, 0xa3, 0x97, 0xd8, 0x1e, 0x74,
208 0x64, 0x35, 0x95, 0xcc, 0xd9, 0x62, 0xdd, 0x70, 0x27, 0xe5, 0xe9, 0x09, 208 0x81, 0xe6, 0x12, 0xea, 0xcd, 0x2f, 0x71, 0xcd, 0x41, 0x2b, 0xd6, 0xbd,
209 0x19, 0x39, 0x27, 0x96, 0xb3, 0x8a, 0xbd, 0xde, 0x1f, 0x62, 0x3e, 0xce, 209 0xd4, 0xe0, 0xda, 0x73, 0x6e, 0xda, 0xae, 0x3b, 0x1e, 0xe7, 0xc7, 0x79,
210 0xef, 0xdd, 0x98, 0x1f, 0xfa, 0xae, 0x86, 0xf3, 0xeb, 0x93, 0xe2, 0x3a, 210 0x0e, 0x63, 0x5e, 0xac, 0xc3, 0x76, 0xad, 0x32, 0x32, 0xfc, 0x1e, 0xeb,
211 0xe7, 0xd7, 0x9a, 0x5b, 0x9c, 0x51, 0x98, 0xa7, 0x60, 0x43, 0x30, 0x47, 211 0xf1, 0xdb, 0x2d, 0xeb, 0x21, 0x66, 0x3d, 0x62, 0xd2, 0xb6, 0xaa, 0xfc,
212 0xd0, 0x38, 0x0d, 0xec, 0xfd, 0x1e, 0x33, 0xa7, 0x3e, 0xcc, 0x09, 0xb8, 212 0x65, 0x45, 0x03, 0x7d, 0x08, 0x07, 0xf4, 0x2f, 0xae, 0xc8, 0x68, 0x54,
213 0x61, 0x95, 0xed, 0x41, 0x17, 0x68, 0x2e, 0xa2, 0x5e, 0x79, 0x95, 0x6b, 213 0x48, 0x7b, 0x82, 0xcf, 0x32, 0x6d, 0x32, 0xe8, 0x5f, 0x81, 0x5c, 0x95,
214 0x0e, 0x5a, 0xb1, 0xee, 0xc5, 0x26, 0xd7, 0x9e, 0x73, 0xd3, 0x58, 0xc3, 214 0x20, 0x0b, 0xf4, 0x07, 0x5e, 0x5e, 0xd6, 0x6b, 0x51, 0x6a, 0x74, 0xc2,
215 0xf1, 0x38, 0x3f, 0xce, 0x73, 0x1c, 0xf3, 0x62, 0x1d, 0xb6, 0xeb, 0x94, 215 0x47, 0xe7, 0xf8, 0xe4, 0x37, 0xe7, 0xe6, 0xaa, 0x75, 0x68, 0x5e, 0x97,
216 0x91, 0xf1, 0x77, 0x58, 0x8f, 0x77, 0x77, 0xac, 0x87, 0x98, 0xf5, 0x88, 216 0x4f, 0xdf, 0xb2, 0x2e, 0xd4, 0xbb, 0xd4, 0x03, 0xc4, 0x3d, 0xd4, 0x05,
217 0x4a, 0xf7, 0xba, 0xf2, 0xd1, 0x15, 0x0d, 0xf4, 0x6b, 0x1c, 0xd0, 0xbf, 217 0x61, 0x4c, 0xa0, 0xe6, 0xea, 0xfd, 0x14, 0xda, 0x9f, 0xeb, 0xdb, 0xf8,
218 0xbc, 0x26, 0x93, 0x0c, 0x60, 0xd1, 0x36, 0x20, 0x2f, 0xd3, 0x2d, 0xa3, 218 0x52, 0xaf, 0x59, 0xc2, 0xc4, 0x05, 0xba, 0xc4, 0x5e, 0xbd, 0x83, 0x7a,
219 0xfe, 0x05, 0xc8, 0x55, 0x11, 0xb2, 0x40, 0x1f, 0xe5, 0xa5, 0xaa, 0x5e, 219 0x1f, 0xf6, 0x27, 0x9c, 0xdf, 0xef, 0xe0, 0x3e, 0x71, 0xd3, 0x7a, 0xd8,
220 0x8b, 0x62, 0x33, 0x26, 0xf6, 0x69, 0x8e, 0x4f, 0x7e, 0x73, 0x6e, 0xae, 220 0x98, 0x93, 0xa3, 0xe6, 0xa8, 0xd6, 0x62, 0x5b, 0xe6, 0xe6, 0x1a, 0x7a,
221 0x5a, 0x87, 0xf6, 0x75, 0x79, 0xec, 0xba, 0x75, 0xd9, 0x84, 0x1e, 0xa5, 221 0x5e, 0xce, 0xd2, 0x1e, 0xb3, 0x1e, 0x31, 0x3c, 0xe3, 0xbc, 0x42, 0x9b,
222 0x1e, 0x20, 0x16, 0xa3, 0x2e, 0x08, 0xe3, 0x10, 0x7f, 0xe4, 0xea, 0xfd, 222 0xc3, 0x79, 0x91, 0x5e, 0xd7, 0xc8, 0x1c, 0xe7, 0xc3, 0xfd, 0xd7, 0x2c,
223 0x14, 0xda, 0xc4, 0xcb, 0x2d, 0xcc, 0xfb, 0xa2, 0xf2, 0x1d, 0xf4, 0x9c, 223 0x6b, 0x2f, 0x05, 0xd5, 0xe5, 0xa8, 0x9a, 0x7b, 0xde, 0xef, 0x26, 0x46,
224 0xf2, 0x19, 0xe8, 0xa5, 0xb5, 0x1b, 0xb0, 0x77, 0x68, 0x13, 0x37, 0x83, 224 0xa3, 0x8e, 0x34, 0xfa, 0x89, 0xcf, 0x69, 0x07, 0xf1, 0x2e, 0x43, 0x19,
225 0x5a, 0xb5, 0x4b, 0xd1, 0x90, 0xf7, 0xfb, 0x89, 0xdf, 0x44, 0xdb, 0x01, 225 0xc2, 0x7d, 0x9d, 0xf7, 0xcd, 0x36, 0xed, 0x79, 0x47, 0xeb, 0x01, 0xc6,
226 0xa6, 0xcc, 0xa7, 0x8d, 0x44, 0x59, 0x86, 0x6b, 0x89, 0xf7, 0x06, 0xdf, 226 0x9f, 0xde, 0xdb, 0xd6, 0x45, 0xb3, 0x62, 0xad, 0x57, 0xe8, 0x33, 0x07,
227 0xdb, 0xf5, 0xfe, 0x7f, 0x72, 0xf4, 0x7e, 0x64, 0xec, 0x69, 0x2f, 0x3b, 227 0xc0, 0x5d, 0x77, 0x40, 0xaf, 0x1c, 0x92, 0x92, 0x0b, 0x7b, 0x3d, 0x7c,
228 0x78, 0x35, 0xe6, 0xe0, 0xc0, 0x57, 0x2e, 0xaf, 0x05, 0xc0, 0x63, 0xef, 228 0x3b, 0xe6, 0x3c, 0x2e, 0x2a, 0xde, 0x30, 0xbc, 0x17, 0xd7, 0x7b, 0x94,
229 0xc1, 0xde, 0xce, 0x49, 0xd1, 0x85, 0x1d, 0x1f, 0xbf, 0x19, 0x7c, 0x9d, 229 0xef, 0x52, 0x1a, 0xfe, 0x90, 0xe4, 0xa6, 0x69, 0xd3, 0x7e, 0x5f, 0x66,
230 0x16, 0x15, 0x67, 0x18, 0xdf, 0x8f, 0xe7, 0x7d, 0xca, 0xa7, 0x29, 0x8e, 230 0x60, 0x5b, 0x4b, 0xc3, 0x77, 0x82, 0x3e, 0xde, 0x43, 0x27, 0x7a, 0x43,
231 0xbf, 0x57, 0x72, 0x73, 0xc4, 0x43, 0x8f, 0xcb, 0x3c, 0x6c, 0x6e, 0x71, 231 0x8c, 0x51, 0xe0, 0xef, 0x71, 0x13, 0x9b, 0x39, 0x80, 0xfb, 0x3d, 0xa8,
232 0x1c, 0x36, 0x31, 0xce, 0x77, 0xe8, 0x25, 0x6f, 0x8c, 0xb1, 0x09, 0xfc, 232 0xf3, 0x49, 0x53, 0xa7, 0x1b, 0x75, 0x06, 0x5b, 0xea, 0x70, 0xbc, 0xfb,
233 0xfd, 0x1b, 0x13, 0x93, 0x39, 0x88, 0xf7, 0x7d, 0xa8, 0xf3, 0x31, 0x53, 233 0x50, 0x07, 0xf6, 0x14, 0x56, 0xd2, 0xf6, 0x0e, 0xe2, 0x37, 0x81, 0x67,
234 0xa7, 0x7f, 0x8f, 0x3a, 0x79, 0xbc, 0xdf, 0x8d, 0x3a, 0x31, 0x8c, 0x01, 234 0xf7, 0xe2, 0xd9, 0x3d, 0x78, 0x76, 0x0f, 0xee, 0x7f, 0xd7, 0xc4, 0x3c,
235 0x4c, 0x0b, 0x5b, 0x66, 0x7b, 0x1f, 0x46, 0xde, 0x5d, 0xc8, 0xbb, 0x0b, 235 0xc2, 0x36, 0xdd, 0xb8, 0xff, 0x12, 0xde, 0x43, 0xc7, 0xb9, 0xdf, 0xc6,
236 0x79, 0x77, 0xe0, 0xbd, 0x60, 0x62, 0x1d, 0x61, 0x9b, 0x7e, 0xbc, 0x7f, 236 0xfb, 0xfb, 0xf0, 0x1b, 0x6b, 0xa9, 0xe3, 0xb6, 0xdc, 0x9f, 0x76, 0x74,
237 0x01, 0xe5, 0xd0, 0x33, 0xee, 0x25, 0x94, 0xdf, 0xad, 0xda, 0x5d, 0x5b, 237 0x8c, 0x84, 0xcf, 0x82, 0xc8, 0xce, 0xf5, 0x7f, 0x35, 0xcf, 0xbd, 0xa6,
238 0x67, 0xb0, 0xe3, 0x7d, 0xcb, 0xd1, 0xb1, 0x11, 0xe6, 0x0d, 0x9b, 0x67, 238 0xf7, 0x1f, 0x37, 0xd7, 0xad, 0xb2, 0x94, 0x86, 0x2c, 0xf1, 0xfd, 0x57,
239 0xb1, 0x96, 0x2b, 0x7c, 0xff, 0xa1, 0x79, 0xbf, 0xb7, 0x23, 0xff, 0x71, 239 0xf6, 0xe9, 0xb5, 0xb8, 0x43, 0xc7, 0x1f, 0x6e, 0xc2, 0x1b, 0x4a, 0xfc,
240 0xf3, 0xde, 0xb9, 0xae, 0xb7, 0x61, 0x5d, 0x59, 0xfe, 0xd1, 0x03, 0x7a, 240 0x71, 0xbd, 0x09, 0x9c, 0x41, 0xec, 0xd1, 0x8c, 0x3b, 0x48, 0x8b, 0xab,
241 0x3d, 0xc6, 0x74, 0xfc, 0xe1, 0x1a, 0x3c, 0xa2, 0x44, 0x11, 0xcf, 0x3b, 241 0xe4, 0xf5, 0xe5, 0xe5, 0xd7, 0xba, 0xf5, 0x18, 0x62, 0xd5, 0x21, 0x73,
242 0xc0, 0x21, 0xc4, 0x26, 0xed, 0xb8, 0x84, 0x34, 0xa9, 0xfa, 0x66, 0x9c, 242 0x13, 0x2a, 0x16, 0xf1, 0x33, 0xf3, 0xcc, 0xdb, 0xb7, 0xf3, 0x6e, 0xaf,
243 0xe7, 0xfa, 0xc3, 0x71, 0xcb, 0x90, 0x81, 0xc3, 0x6b, 0x61, 0xfe, 0xc5, 243 0x4c, 0x54, 0xff, 0x68, 0xdf, 0x0e, 0x6d, 0x93, 0x4d, 0xd7, 0x3b, 0x98,
244 0xfe, 0x6b, 0xe9, 0xf9, 0x9f, 0x6d, 0xf5, 0xf6, 0xcb, 0xe1, 0x5a, 0x98, 244 0x02, 0xfe, 0x84, 0xbd, 0x83, 0x77, 0x72, 0xf6, 0x5c, 0xa3, 0x68, 0xeb,
245 0x7f, 0xe8, 0xc0, 0xb5, 0xf5, 0x6e, 0x3e, 0x70, 0x75, 0xae, 0xad, 0x78, 245 0x71, 0x59, 0x07, 0xef, 0x1a, 0x9b, 0x3d, 0x8e, 0x92, 0xfd, 0x9c, 0x4d,
246 0x09, 0x68, 0xfb, 0x8c, 0x7d, 0x15, 0x2b, 0xe5, 0xec, 0xc5, 0xe6, 0x8c, 246 0x5f, 0xa3, 0xbc, 0xc6, 0xeb, 0xdb, 0x51, 0x36, 0xb7, 0xed, 0x87, 0x1e,
247 0xad, 0x69, 0x62, 0x1d, 0x94, 0x35, 0x77, 0x06, 0x1c, 0x25, 0xa3, 0x39, 247 0xcf, 0xd9, 0x9a, 0xee, 0xd6, 0xf6, 0xe1, 0xbe, 0xf1, 0x65, 0xa1, 0x0a,
248 0x9b, 0x7e, 0x4a, 0x69, 0x83, 0xcf, 0x37, 0x23, 0x6d, 0x6f, 0x3b, 0x0c, 248 0x99, 0xf3, 0x52, 0xc3, 0x65, 0xac, 0xdd, 0xac, 0x9f, 0x9a, 0xa6, 0x4c,
249 0x7d, 0x9b, 0xb3, 0xf5, 0x9c, 0x3a, 0xdb, 0x87, 0xf2, 0xed, 0xcb, 0x52, 249 0xc2, 0x9f, 0xfd, 0x94, 0xc8, 0xa4, 0xcc, 0x57, 0x1f, 0x06, 0xfe, 0x0e,
250 0x0d, 0x32, 0xe9, 0xa5, 0xc6, 0x4b, 0xf0, 0x73, 0x17, 0xfc, 0xd4, 0x1c, 250 0xe4, 0x21, 0xe0, 0x8a, 0x7f, 0x0f, 0x5c, 0x52, 0x83, 0xac, 0xd7, 0x1a,
251 0x65, 0x16, 0xbe, 0xf0, 0x23, 0x22, 0xb3, 0x52, 0xae, 0x3d, 0x08, 0xec, 251 0x1e, 0x7e, 0xfd, 0xf2, 0x57, 0x95, 0x84, 0x3c, 0x07, 0x7f, 0x02, 0xb2,
252 0x1e, 0xc8, 0x87, 0x60, 0xff, 0xff, 0x25, 0xf0, 0x43, 0x1d, 0xba, 0xa0, 252 0x06, 0x3d, 0x9c, 0x76, 0x1f, 0x12, 0xe9, 0xb1, 0xe5, 0xf2, 0xbd, 0xb6,
253 0xde, 0xf4, 0xf0, 0x1b, 0x96, 0xaf, 0x57, 0x12, 0xf2, 0x3c, 0x7c, 0x91, 253 0x8c, 0x24, 0x07, 0xac, 0x74, 0x02, 0x3f, 0xb7, 0x0d, 0xbf, 0x22, 0x7c,
254 0xc6, 0x1a, 0xf5, 0x65, 0xda, 0xfd, 0x90, 0xc8, 0x80, 0x2d, 0xe7, 0xef, 254 0xb8, 0xb5, 0x06, 0x63, 0x01, 0x71, 0xf9, 0xeb, 0xf5, 0x24, 0x7e, 0x7d,
255 0xb2, 0x65, 0x22, 0x39, 0x62, 0xa5, 0x13, 0xf8, 0xb9, 0xdd, 0xf8, 0xcd, 255 0xf2, 0x37, 0xeb, 0x1c, 0x7f, 0xc0, 0x94, 0x6a, 0x1f, 0xc3, 0xe7, 0x28,
256 0xc0, 0xff, 0xdb, 0x68, 0x32, 0x8e, 0x10, 0x97, 0x3f, 0xdf, 0x4c, 0xe2, 256 0xcb, 0x62, 0x26, 0x21, 0x0b, 0x95, 0xe0, 0xa4, 0xf6, 0x99, 0x3d, 0xf8,
257 0x37, 0x24, 0xff, 0x7e, 0x93, 0xe3, 0x8f, 0x98, 0x34, 0xf4, 0x4d, 0xbe, 257 0xc8, 0xdc, 0xb3, 0x2f, 0x60, 0xcf, 0xe2, 0xb9, 0xc2, 0x9e, 0xa1, 0xdd,
258 0x05, 0x1d, 0x71, 0x29, 0x58, 0xae, 0x32, 0x26, 0x14, 0xda, 0xa1, 0x6f, 258 0x7b, 0x01, 0x76, 0x2f, 0x5c, 0x23, 0xce, 0xb3, 0x75, 0x7d, 0xd8, 0x2f,
259 0x29, 0x3b, 0xb4, 0x54, 0x09, 0x8e, 0x6b, 0x1f, 0xdc, 0x83, 0xcf, 0x8d, 259 0xd7, 0x88, 0x7a, 0x9d, 0xba, 0x3c, 0x06, 0xfc, 0x10, 0xea, 0x76, 0xea,
260 0xf7, 0xe6, 0x5b, 0x56, 0xa3, 0x35, 0xc7, 0x1d, 0xab, 0x61, 0xd6, 0xad, 260 0x08, 0x6f, 0xdb, 0x0f, 0x7d, 0xe4, 0x60, 0x17, 0xb0, 0x86, 0xc4, 0xe2,
261 0xd1, 0x9a, 0x23, 0xca, 0x9b, 0x17, 0x20, 0x0b, 0xd4, 0xbf, 0xa1, 0xee, 261 0xd9, 0x9f, 0xca, 0xca, 0x59, 0xee, 0x1b, 0xda, 0xe3, 0xbb, 0x21, 0x6f,
262 0xf5, 0x0c, 0x2e, 0x0a, 0xf5, 0x2f, 0xf6, 0x70, 0x4d, 0xa2, 0xf1, 0xec, 262 0xa9, 0xaf, 0x96, 0x89, 0x99, 0xbd, 0x0c, 0xf8, 0x51, 0x96, 0xe9, 0x83,
263 0x2f, 0x64, 0xed, 0x34, 0xf7, 0x14, 0xed, 0xe5, 0x34, 0x64, 0x31, 0xf5, 263 0xab, 0xbd, 0x5a, 0x4e, 0x26, 0xc5, 0x39, 0xfb, 0x85, 0xa8, 0x74, 0x9f,
264 0x95, 0x12, 0x71, 0xb6, 0xc7, 0x98, 0xc0, 0x25, 0xf4, 0x31, 0x3f, 0xa8, 264 0x94, 0x45, 0x1f, 0x7e, 0xa9, 0x5d, 0x0e, 0x22, 0x9e, 0x97, 0x28, 0x28,
265 0x65, 0xe7, 0x12, 0xf6, 0xf9, 0xac, 0x38, 0xa7, 0x3f, 0xdf, 0x25, 0xfd, 265 0xbf, 0x69, 0x05, 0x74, 0xc6, 0x64, 0xe2, 0x2c, 0xeb, 0x9c, 0x84, 0x8c,
266 0xc7, 0x65, 0xd9, 0x87, 0x3f, 0x6b, 0x97, 0x82, 0x88, 0xe7, 0x25, 0x0a, 266 0xb5, 0x81, 0xe6, 0x76, 0x39, 0x15, 0x4f, 0x95, 0x0b, 0xf0, 0xf7, 0x6d,
267 0xca, 0xdf, 0x5a, 0x03, 0x5d, 0xdf, 0x03, 0x26, 0x3e, 0xae, 0xfc, 0xba, 267 0xaf, 0x47, 0x06, 0xea, 0x2c, 0x89, 0x41, 0xfe, 0x37, 0xe4, 0x87, 0xd7,
268 0x63, 0x35, 0xd6, 0xed, 0xc6, 0x7a, 0xa4, 0x4a, 0x05, 0xac, 0xd5, 0x89, 268 0xf0, 0x03, 0x57, 0xf9, 0x7c, 0x00, 0x25, 0x9f, 0x7b, 0xd0, 0x2f, 0xe4,
269 0xf8, 0x05, 0x94, 0x05, 0x81, 0xed, 0x0d, 0x48, 0xb1, 0x1e, 0x3e, 0x43, 269 0x07, 0x70, 0xc3, 0xc5, 0xb2, 0x9c, 0xca, 0x4c, 0x4a, 0xbd, 0x2a, 0xd6,
270 0xf6, 0x37, 0xff, 0x01, 0x32, 0xc6, 0x67, 0xc0, 0xc4, 0x75, 0x96, 0x8d, 270 0x42, 0x06, 0x7b, 0xa0, 0x96, 0x95, 0x3a, 0x78, 0x51, 0x6a, 0x1c, 0x87,
271 0x20, 0x65, 0x39, 0xcb, 0x3c, 0xa5, 0xeb, 0x8a, 0x4d, 0xd2, 0x31, 0x2b, 271 0xdf, 0xf9, 0x26, 0xca, 0x39, 0x94, 0xd7, 0x51, 0x3e, 0x8e, 0xf2, 0x2d,
272 0x85, 0x1a, 0xe7, 0x04, 0xbb, 0x58, 0xbf, 0x14, 0x9c, 0xa8, 0x5e, 0x00, 272 0x94, 0xa4, 0xfd, 0xb8, 0xd4, 0x6b, 0x7b, 0xda, 0xa4, 0x93, 0x7d, 0x6c,
273 0xaf, 0x38, 0x5e, 0x56, 0x1a, 0x58, 0x8b, 0x72, 0xf3, 0x71, 0x60, 0xfa, 273 0x18, 0x9a, 0xe1, 0x3b, 0x1e, 0x3c, 0x0e, 0x2c, 0x1a, 0x3e, 0x3f, 0x2e,
274 0xd7, 0x91, 0x2e, 0x22, 0xbd, 0x8c, 0xf4, 0x09, 0xa4, 0x6f, 0x20, 0xe5, 274 0x52, 0xff, 0x0c, 0x7e, 0x0f, 0xaa, 0x7b, 0xfa, 0x96, 0x0b, 0x99, 0x71,
275 0xbc, 0x1e, 0x97, 0x46, 0x3d, 0xd1, 0x2d, 0x31, 0xf6, 0xf3, 0xd9, 0xd6, 275 0xe0, 0x7a, 0xb1, 0x4e, 0x65, 0x1e, 0x37, 0xfd, 0x7c, 0x06, 0xe3, 0x5d,
276 0x7c, 0xca, 0xd0, 0x0d, 0xb9, 0x56, 0x3e, 0x9f, 0x99, 0x7e, 0x02, 0xe9, 276 0xc5, 0xd8, 0x31, 0xc8, 0x48, 0x20, 0x8f, 0xf8, 0x27, 0xe5, 0x73, 0xfe,
277 0x47, 0x91, 0xf7, 0x3d, 0x3c, 0x4f, 0x4b, 0xa1, 0xf2, 0x04, 0xec, 0x30, 277 0x7e, 0x19, 0xeb, 0x8d, 0x95, 0x63, 0x59, 0xce, 0x9f, 0x7a, 0x6a, 0xb7,
278 0xb1, 0xea, 0x27, 0x30, 0x2e, 0xc7, 0x7f, 0x19, 0x74, 0xb0, 0x2c, 0x90, 278 0xf9, 0x87, 0xf3, 0xe6, 0x9c, 0xa1, 0x5b, 0x97, 0xf6, 0x6a, 0xdc, 0x6d,
279 0x4f, 0x62, 0x9e, 0xf9, 0xda, 0x71, 0x79, 0xd8, 0xbf, 0x45, 0xa6, 0x1e, 279 0x7f, 0x39, 0xaa, 0x69, 0xb1, 0x64, 0x60, 0x88, 0xfd, 0x65, 0x25, 0x72,
280 0x26, 0x3d, 0xe4, 0x0d, 0xf5, 0xdb, 0x5e, 0xbc, 0x21, 0x5f, 0x42, 0x7e, 280 0x76, 0xc8, 0xcd, 0xd8, 0x23, 0xf0, 0x52, 0xd2, 0xf8, 0x9d, 0x84, 0xfc,
281 0xf4, 0x61, 0x5e, 0xd4, 0x55, 0xc4, 0xc6, 0x10, 0xc0, 0x7e, 0x8d, 0x77, 281 0x79, 0xa7, 0x07, 0xec, 0xdb, 0x40, 0x13, 0xde, 0xd5, 0x39, 0x0e, 0xec,
282 0x46, 0xc6, 0x02, 0x79, 0xc8, 0xcf, 0x4a, 0xe4, 0xf4, 0x98, 0x9b, 0xb1, 282 0xe9, 0x3d, 0xaf, 0x62, 0x6e, 0x65, 0x69, 0xbf, 0x27, 0x2b, 0x37, 0x1a,
283 0x27, 0xe0, 0xf9, 0xa4, 0xf1, 0x3b, 0x0e, 0xb9, 0xf4, 0x4e, 0x8d, 0xd8, 283 0xbc, 0x86, 0x3d, 0xba, 0x30, 0x29, 0xff, 0x5c, 0xbd, 0x2a, 0x4f, 0x54,
284 0x23, 0xa0, 0x09, 0x65, 0x0d, 0x8e, 0x73, 0x29, 0xf8, 0x93, 0xea, 0xab, 284 0x27, 0xe5, 0x0d, 0x94, 0x8b, 0xd5, 0x32, 0xf8, 0xc8, 0x58, 0x3c, 0xfb,
285 0xf0, 0xdb, 0xb3, 0x72, 0xa5, 0xf9, 0x2a, 0xe4, 0x83, 0xf4, 0x08, 0xe8, 285 0x08, 0xb0, 0x2e, 0x83, 0xf0, 0x8d, 0x3e, 0x98, 0x98, 0xc3, 0xfa, 0xcd,
286 0x9c, 0x95, 0x1f, 0xd7, 0x5e, 0x96, 0x93, 0xe0, 0xfd, 0x6b, 0x48, 0x97, 286 0xb8, 0x81, 0x9c, 0xf3, 0xcb, 0x72, 0x6e, 0x1c, 0x6d, 0x6a, 0x1d, 0x12,
287 0x6b, 0x25, 0xf0, 0x95, 0xf1, 0x7b, 0xf6, 0x11, 0x60, 0xcd, 0x46, 0xe1, 287 0x7d, 0x96, 0xf3, 0xed, 0x96, 0x02, 0x2c, 0x7a, 0x31, 0x43, 0x9d, 0xd9,
288 0x6f, 0xdd, 0x96, 0x58, 0xc4, 0xfa, 0xce, 0xbb, 0x81, 0x6c, 0xf9, 0x25, 288 0x29, 0x85, 0x5a, 0xab, 0xdc, 0x51, 0xde, 0xde, 0xb6, 0xea, 0xdb, 0x3a,
289 0xd9, 0x9a, 0x46, 0x9b, 0x3a, 0xdb, 0xf7, 0xca, 0x61, 0x95, 0x52, 0xfe, 289 0x60, 0xd3, 0xfa, 0x66, 0x83, 0x36, 0x78, 0x37, 0x7b, 0xaa, 0xe5, 0xae,
290 0xfa, 0x31, 0xc7, 0x98, 0xe2, 0xf3, 0x72, 0x35, 0x94, 0x3d, 0xca, 0x61, 290 0x5e, 0xa3, 0x4d, 0xdd, 0x91, 0xbd, 0x3a, 0xfc, 0xb9, 0x7a, 0xf5, 0xba,
291 0xa7, 0xfc, 0x91, 0xee, 0x1d, 0xeb, 0x9b, 0x4d, 0xda, 0xd1, 0xbd, 0x6c, 291 0x91, 0x3f, 0x25, 0xb7, 0x58, 0x17, 0x62, 0xf1, 0x9f, 0x08, 0xb0, 0x1f,
292 0x62, 0x28, 0x97, 0xb4, 0x8b, 0xed, 0xb2, 0x29, 0xd2, 0xa8, 0x69, 0xff, 292 0x78, 0x14, 0xc6, 0x09, 0xb5, 0x7f, 0x54, 0x03, 0xad, 0x85, 0x38, 0x71,
293 0xe6, 0x1b, 0xdb, 0x4a, 0xd6, 0xb1, 0x3e, 0xc4, 0xd3, 0x3f, 0x17, 0xe0, 293 0x06, 0xac, 0x5b, 0xed, 0x0b, 0x8a, 0x57, 0xde, 0xd9, 0x7e, 0xa9, 0x2e,
294 0x37, 0xf0, 0x29, 0x8c, 0x2f, 0x6a, 0xbf, 0xab, 0x0e, 0x7a, 0xe1, 0x6b, 294 0x93, 0xbf, 0x29, 0xd7, 0xb6, 0x95, 0x4f, 0x02, 0xbe, 0x7a, 0x58, 0x9f,
295 0x00, 0x2b, 0x88, 0xd4, 0xeb, 0x9f, 0x57, 0xfc, 0xf2, 0x4e, 0x0f, 0x4b, 295 0xf0, 0x7d, 0x0a, 0x7e, 0xd2, 0x49, 0x71, 0xc7, 0x3a, 0x31, 0x27, 0x5e,
296 0xad, 0x4a, 0x1e, 0xa7, 0x5c, 0xdb, 0x56, 0xfe, 0x0d, 0x78, 0xeb, 0x41, 296 0x8b, 0x4c, 0x5f, 0x6c, 0xc5, 0x91, 0xa1, 0x9d, 0x68, 0x83, 0x3f, 0x1e,
297 0x56, 0xc2, 0xf2, 0x14, 0xfc, 0xaf, 0xe3, 0xe2, 0x4e, 0xc5, 0x60, 0xbf, 297 0xc5, 0x5a, 0x76, 0xc1, 0x9f, 0x86, 0x9f, 0x0a, 0x39, 0xfa, 0x33, 0x60,
298 0xf8, 0x2c, 0x32, 0x77, 0xae, 0x13, 0x0b, 0x86, 0x36, 0xa6, 0x1b, 0x7e, 298 0xaf, 0xd3, 0xca, 0xb7, 0xe6, 0x9e, 0xea, 0x9e, 0x1a, 0x58, 0x67, 0xb9,
299 0x7e, 0x17, 0x74, 0x41, 0x1f, 0xfc, 0x74, 0xf8, 0xbf, 0x90, 0xa7, 0x3f, 299 0x77, 0x2a, 0x5d, 0x63, 0x19, 0x9f, 0xd2, 0xbe, 0x64, 0x62, 0x4a, 0xc7,
300 0x01, 0x7e, 0x3a, 0xa5, 0x7c, 0x76, 0xee, 0xc3, 0x07, 0x67, 0x47, 0x36, 300 0xed, 0x93, 0x53, 0x07, 0x54, 0xe9, 0x4d, 0x0d, 0xab, 0x72, 0x78, 0x6a,
301 0x99, 0x7e, 0x78, 0x36, 0x5d, 0x67, 0x7a, 0xd4, 0xc4, 0xf5, 0x1f, 0x31, 301 0x27, 0x66, 0x42, 0x9e, 0x8a, 0x95, 0xcf, 0x64, 0xa4, 0x58, 0x21, 0x8d,
302 0xf1, 0xfe, 0xf9, 0xd9, 0x83, 0x2a, 0x5d, 0x9c, 0x1d, 0x57, 0xe9, 0xe3, 302 0xe2, 0x1c, 0x83, 0x3c, 0xcd, 0x01, 0xcb, 0xe4, 0x2b, 0xbe, 0x9c, 0xda,
303 0xb3, 0x57, 0x63, 0x31, 0x17, 0x20, 0xab, 0xa4, 0x4d, 0x9c, 0x62, 0x26, 303 0xc8, 0x82, 0x66, 0xe8, 0x99, 0xac, 0x8f, 0x52, 0xcc, 0x5f, 0xd8, 0xb6,
304 0x23, 0x9b, 0x15, 0x1f, 0x7e, 0xf7, 0x34, 0xf0, 0xc7, 0x34, 0xe4, 0x36, 304 0x8d, 0x31, 0x32, 0xae, 0x99, 0xf1, 0x33, 0x7d, 0xfa, 0x99, 0xcd, 0x7f,
305 0x0b, 0x7a, 0xa1, 0x7f, 0xb2, 0x3e, 0x52, 0x31, 0x7f, 0x61, 0xbb, 0x6e, 305 0xec, 0x0f, 0xb2, 0x49, 0xfb, 0xf9, 0x0b, 0xf8, 0xc6, 0xe2, 0x94, 0x32,
306 0xc6, 0xdd, 0xb8, 0x66, 0xc6, 0x77, 0xf5, 0xe9, 0xbb, 0xb6, 0xff, 0xb1, 306 0x6c, 0xeb, 0xc3, 0x07, 0x17, 0xd9, 0x5a, 0x91, 0x58, 0x2c, 0xfb, 0x1d,
307 0x4f, 0xc8, 0x38, 0xed, 0xee, 0xaf, 0xe1, 0x6f, 0xb3, 0x7f, 0xb6, 0x65, 307 0x89, 0x3d, 0x1d, 0x04, 0x3f, 0xf0, 0x53, 0x47, 0xca, 0x02, 0x5e, 0x59,
308 0xff, 0x22, 0xbb, 0x6b, 0x12, 0x8d, 0x66, 0xff, 0x5a, 0xa2, 0xcf, 0x06, 308 0x78, 0xbe, 0xce, 0x77, 0xd4, 0x4d, 0x23, 0xee, 0x0d, 0xc8, 0x5c, 0xee,
309 0xc1, 0x4f, 0xfc, 0xd4, 0x91, 0x92, 0x80, 0x4f, 0x16, 0xf2, 0x37, 0x59, 309 0xa8, 0xc8, 0x2b, 0x78, 0x56, 0x5f, 0xe1, 0x1a, 0x7c, 0x17, 0x6b, 0x60,
310 0x46, 0x9d, 0x35, 0xe1, 0x5e, 0x81, 0xcc, 0xe5, 0x8e, 0x8a, 0xbc, 0x82, 310 0xd6, 0x44, 0x3d, 0x63, 0x3d, 0xf8, 0x58, 0x71, 0xce, 0x63, 0xc4, 0x6d,
311 0xbc, 0xc6, 0x1a, 0xf9, 0xff, 0x3d, 0xf0, 0xdf, 0xac, 0x87, 0xca, 0x63, 311 0x47, 0xfb, 0xda, 0x3a, 0xdb, 0xa4, 0xc6, 0x79, 0xe4, 0xf5, 0xca, 0xba,
312 0x3d, 0xf8, 0x48, 0x71, 0xca, 0xdc, 0x84, 0xdb, 0x83, 0xf6, 0xf5, 0x4d, 312 0x9e, 0xdf, 0xe1, 0xcc, 0xb0, 0x5c, 0xae, 0xa8, 0x3e, 0x20, 0xeb, 0xbf,
313 0xb6, 0x49, 0x4d, 0xf3, 0x98, 0xec, 0x95, 0xcd, 0x0b, 0x4a, 0x5f, 0x75, 313 0x44, 0x9b, 0x4d, 0xc8, 0x2d, 0x63, 0x53, 0x59, 0x99, 0x07, 0x4e, 0x9b,
314 0x67, 0xc7, 0x19, 0x43, 0x92, 0x8d, 0xb5, 0xdf, 0x04, 0x0b, 0xfe, 0x0e, 314 0xaf, 0xa4, 0x21, 0x3b, 0x8e, 0xcc, 0x24, 0x48, 0xb6, 0x27, 0x5b, 0x95,
315 0x80, 0x5a, 0x0a, 0x72, 0x9f, 0x95, 0xf3, 0xc0, 0x58, 0xe7, 0x2b, 0x69, 315 0x37, 0xdb, 0x88, 0x85, 0xf3, 0x1e, 0xaf, 0xc7, 0x51, 0x67, 0x5a, 0x88,
316 0xac, 0x0d, 0xf0, 0x6d, 0x82, 0x24, 0x7b, 0xa8, 0xf7, 0x66, 0x37, 0x71, 316 0xb7, 0xf2, 0x19, 0xce, 0xa9, 0x99, 0x17, 0xfa, 0xaf, 0x84, 0xb5, 0x30,
317 0x6c, 0x9e, 0xe7, 0x47, 0x95, 0x69, 0xd9, 0x6d, 0xce, 0x09, 0xb1, 0x52, 317 0x73, 0x54, 0x7f, 0x7a, 0x1c, 0xb4, 0x37, 0xe3, 0x14, 0x01, 0x53, 0xe0,
318 0x3e, 0xc3, 0xf9, 0xb4, 0xf3, 0x41, 0xff, 0x15, 0xb1, 0x06, 0x66, 0x7e, 318 0x6b, 0x4a, 0xfa, 0x82, 0xe3, 0xe4, 0x2b, 0x8e, 0x0c, 0x5c, 0xc0, 0xb6,
319 0xea, 0x0f, 0x74, 0x62, 0x3f, 0xa1, 0xbd, 0xbf, 0x83, 0xbd, 0x91, 0x82, 319 0xca, 0x1a, 0x5e, 0x34, 0x42, 0x59, 0x0b, 0x31, 0x10, 0x65, 0x8b, 0x3c,
320 0x7e, 0x15, 0x07, 0x7e, 0xa2, 0xa4, 0xcf, 0x3a, 0x4e, 0xbe, 0xe2, 0xc8, 320 0x48, 0x95, 0x37, 0xc1, 0xec, 0xde, 0xec, 0x35, 0x79, 0x74, 0x55, 0xcf,
321 0xc8, 0x59, 0x6c, 0xa9, 0xac, 0xe1, 0x43, 0x33, 0x94, 0xb1, 0x50, 0xe7, 321 0xd9, 0x3e, 0x2f, 0x3c, 0x0b, 0x91, 0x1b, 0x2b, 0x29, 0xff, 0x3a, 0xf4,
322 0x51, 0xa6, 0x38, 0xff, 0x54, 0x69, 0x07, 0x8c, 0x1e, 0xcc, 0x5e, 0x94, 322 0x7d, 0x21, 0xee, 0x43, 0x56, 0xfe, 0x4b, 0x1b, 0xf6, 0xf4, 0x78, 0xce,
323 0x87, 0xd7, 0xf5, 0x7c, 0xed, 0x33, 0xc2, 0xb3, 0x13, 0xb9, 0xb2, 0x96, 323 0xde, 0xdf, 0xae, 0x6d, 0xac, 0x83, 0x3d, 0x01, 0xac, 0x59, 0xc9, 0xa1,
324 0xf2, 0x2f, 0x0b, 0xfd, 0x5f, 0x1f, 0x32, 0x72, 0xb1, 0x1b, 0xfb, 0x79, 324 0x4d, 0xbb, 0xfc, 0x5b, 0x07, 0xd7, 0xc4, 0x9e, 0x78, 0x66, 0xec, 0x22,
325 0x3a, 0x67, 0x1f, 0xec, 0xd1, 0xb6, 0xd9, 0xc1, 0x1e, 0x00, 0x4e, 0xac, 325 0xae, 0x75, 0x7f, 0xf3, 0x98, 0x87, 0x8e, 0x03, 0x5b, 0xf2, 0x28, 0x2c,
326 0xc0, 0x6f, 0xf6, 0x7a, 0xe4, 0x5f, 0x38, 0x78, 0x26, 0x6e, 0x44, 0x9e, 326 0x88, 0xa0, 0xff, 0x01, 0x33, 0xd6, 0xc0, 0xf9, 0x50, 0x36, 0x40, 0xf7,
327 0xb1, 0xa3, 0x78, 0xd6, 0xfd, 0x95, 0x31, 0x0f, 0x1d, 0x57, 0xb6, 0xe4, 327 0x6a, 0x16, 0xf8, 0xdd, 0x31, 0x7e, 0x2b, 0x75, 0x8c, 0xec, 0xe2, 0xf7,
328 0x61, 0x58, 0x15, 0x41, 0xff, 0x23, 0x66, 0xac, 0x91, 0x33, 0x17, 0xd4, 328 0x34, 0xc7, 0x5e, 0x63, 0x2a, 0x4e, 0x47, 0x2c, 0x47, 0xd9, 0x3a, 0x62,
329 0x7e, 0x4d, 0xaf, 0x67, 0x81, 0xa3, 0x1c, 0xe3, 0x6f, 0x52, 0x4f, 0xc9, 329 0x64, 0xeb, 0x33, 0x90, 0xad, 0xe3, 0x4a, 0xb6, 0x02, 0xf9, 0x81, 0xef,
330 0x1e, 0xfe, 0x4a, 0x28, 0xa3, 0x17, 0x82, 0x2f, 0x56, 0xc3, 0x98, 0x40, 330 0xcb, 0x97, 0x77, 0x95, 0xaf, 0xd6, 0xbf, 0x2e, 0xd0, 0xcb, 0x5f, 0x9f,
331 0x46, 0x46, 0x56, 0xb4, 0x4c, 0x3d, 0x9e, 0x81, 0xce, 0x86, 0x2c, 0x8d, 331 0x2c, 0xfc, 0x05, 0xc6, 0xbd, 0xe0, 0xe2, 0x3a, 0x95, 0x9b, 0x11, 0xf2,
332 0xac, 0x04, 0xf2, 0x13, 0xdf, 0x97, 0x53, 0xdb, 0x7b, 0xc9, 0x54, 0xe7, 332 0x31, 0x81, 0xeb, 0x18, 0xca, 0x7e, 0x55, 0x67, 0xe0, 0x02, 0xec, 0x1a,
333 0x5f, 0x1f, 0xe8, 0xe4, 0x6f, 0x48, 0x96, 0xfe, 0x14, 0x74, 0x9e, 0x75, 333 0xe4, 0x8d, 0xfc, 0x9d, 0x87, 0x8d, 0x1b, 0xb8, 0x10, 0x85, 0x2d, 0xe4,
334 0xf1, 0x9c, 0x9a, 0x9b, 0xa7, 0x8f, 0x70, 0x16, 0xba, 0x14, 0xbe, 0xac, 334 0x9e, 0x95, 0x5e, 0x1b, 0xba, 0x81, 0xf5, 0xeb, 0xd8, 0x3b, 0x03, 0x17,
335 0x7d, 0x76, 0x58, 0xd5, 0xb1, 0xcf, 0xc2, 0xc6, 0x41, 0xc6, 0x6c, 0xf0, 335 0xba, 0x50, 0x26, 0x55, 0x5f, 0xf5, 0x8a, 0xa7, 0xda, 0xd7, 0x2b, 0xc3,
336 0xb5, 0x0c, 0x7b, 0x67, 0x9f, 0xed, 0x82, 0x5d, 0xe4, 0x1e, 0x95, 0x41, 336 0xaa, 0x5d, 0xbd, 0x32, 0x8a, 0x12, 0xfa, 0x3d, 0xe3, 0xcb, 0xd0, 0x85,
337 0x1b, 0xba, 0x80, 0xf5, 0x1b, 0xd8, 0x2b, 0xf6, 0xd9, 0x3e, 0xa4, 0x49, 337 0x8c, 0x24, 0x2f, 0x58, 0x52, 0x9a, 0x0e, 0x82, 0x18, 0x68, 0x1f, 0xbe,
338 0xd5, 0x57, 0xa3, 0xe2, 0xa9, 0xf6, 0x8d, 0xca, 0xb8, 0x6a, 0xd7, 0xa8, 338 0xd0, 0x23, 0xd7, 0xa7, 0x39, 0x37, 0xea, 0x62, 0xb1, 0x16, 0x33, 0xd3,
339 0x4c, 0x22, 0x85, 0x8e, 0xcf, 0xf8, 0xd2, 0x7d, 0x36, 0x23, 0x72, 0xd6, 339 0xd8, 0x9b, 0xe4, 0x1f, 0xb0, 0xfe, 0x85, 0x22, 0x6c, 0x6e, 0x51, 0x4e,
340 0x92, 0xe2, 0x5c, 0x10, 0xc4, 0x40, 0x7b, 0xec, 0xec, 0x01, 0xb9, 0xac, 340 0xad, 0x90, 0x3f, 0x8c, 0xb5, 0x6f, 0x25, 0x22, 0x92, 0x82, 0x2e, 0x3b,
341 0xd6, 0x76, 0x4e, 0x46, 0x9e, 0x25, 0xbf, 0xb2, 0xa8, 0x3b, 0x23, 0xe9, 341 0x2a, 0x73, 0xd5, 0x76, 0xe8, 0x32, 0xc7, 0xad, 0xcb, 0x13, 0x58, 0xa3,
342 0x67, 0x67, 0xc4, 0x7b, 0x96, 0x3c, 0x61, 0xac, 0x7e, 0x57, 0xc9, 0xd4, 342 0x41, 0xca, 0x03, 0xf8, 0x92, 0x45, 0xdf, 0x45, 0x29, 0xa0, 0x4d, 0x71,
343 0x27, 0xe4, 0x28, 0xec, 0x4a, 0x0f, 0xf6, 0x84, 0xe3, 0x96, 0x65, 0x05, 343 0x65, 0xa7, 0x7e, 0x49, 0xda, 0xb1, 0xa7, 0x8e, 0xca, 0xb1, 0x2a, 0xfb,
344 0x6b, 0x32, 0xea, 0x1e, 0x86, 0x9c, 0xc9, 0xdb, 0xd6, 0x67, 0x5d, 0xb6, 344 0x71, 0xdc, 0x79, 0x39, 0x00, 0x19, 0xf2, 0xdc, 0x09, 0xf4, 0x03, 0x1b,
345 0x61, 0xfd, 0x83, 0x90, 0x17, 0x0f, 0xf5, 0x8f, 0xc2, 0xc6, 0xb4, 0xf3, 345 0xd9, 0xf4, 0xc7, 0xfd, 0x97, 0x7b, 0x0f, 0x99, 0x0c, 0xf7, 0x5d, 0xac,
346 0x82, 0xfb, 0x2c, 0xf7, 0x0e, 0xf2, 0x17, 0xee, 0xaf, 0x0b, 0xc1, 0xc9, 346 0xdc, 0x96, 0x9d, 0xb6, 0xb6, 0x32, 0xe2, 0xcc, 0x66, 0x1e, 0xb2, 0x5e,
347 0x2a, 0xf7, 0x18, 0xf7, 0xd7, 0x87, 0xe4, 0x15, 0x6f, 0x4e, 0x76, 0xbd, 347 0xc9, 0x64, 0xac, 0x2b, 0x99, 0x9c, 0x75, 0x35, 0x53, 0xb4, 0xae, 0xc1,
348 0x8c, 0x5c, 0x00, 0x0e, 0x7d, 0xd9, 0x9b, 0x91, 0x8b, 0x5e, 0xb4, 0x87, 348 0x36, 0xd5, 0x37, 0xde, 0x81, 0xfc, 0x00, 0x4f, 0x10, 0x7b, 0x6f, 0xaf,
349 0x31, 0xb6, 0x06, 0x71, 0x72, 0x6b, 0xcd, 0xe2, 0xc6, 0x1f, 0x79, 0x43, 349 0x61, 0xdc, 0xf8, 0x39, 0x6f, 0xc9, 0xb9, 0x0a, 0xed, 0x74, 0x70, 0x68,
350 0xb6, 0x2a, 0xb4, 0xd5, 0xc1, 0xa1, 0x05, 0xbf, 0x74, 0x33, 0x68, 0x03, 350 0xd6, 0x2f, 0xdf, 0x0e, 0xfa, 0x40, 0x07, 0xe3, 0x11, 0x3b, 0xb6, 0x23,
351 0x1d, 0x8c, 0x1b, 0x5c, 0xb5, 0x11, 0x5d, 0xd8, 0x43, 0x1b, 0xca, 0x46, 351 0x9a, 0x1d, 0x06, 0x4e, 0xa0, 0xed, 0xe8, 0xa2, 0xed, 0xf0, 0x0b, 0xb2,
352 0xf4, 0xd1, 0x46, 0xf8, 0x05, 0xd9, 0x2f, 0xbb, 0x35, 0x1d, 0xd3, 0xcb, 352 0x57, 0xb6, 0xaa, 0x3a, 0x2e, 0x97, 0x07, 0x6e, 0xda, 0xaa, 0xc5, 0xe5,
353 0x03, 0x43, 0xed, 0xd6, 0xb9, 0xfe, 0x71, 0xf9, 0x52, 0x95, 0x73, 0x2d, 353 0xcb, 0xcb, 0xa1, 0x2c, 0x71, 0xbe, 0xf3, 0xef, 0xeb, 0x90, 0x88, 0x1c,
354 0xdf, 0x10, 0x93, 0x88, 0x1c, 0x51, 0x36, 0xbb, 0x5f, 0xce, 0x6f, 0x02, 354 0x51, 0xf6, 0xba, 0x5b, 0x2e, 0xaf, 0x03, 0xd3, 0x02, 0x81, 0xd8, 0x77,
355 0xf3, 0x02, 0x7d, 0xd8, 0xb7, 0x32, 0x26, 0x64, 0xab, 0x18, 0x83, 0x0c, 355 0x32, 0xce, 0x63, 0xab, 0xf8, 0x85, 0xf4, 0xf0, 0x3c, 0xf0, 0x1f, 0xc0,
356 0xd0, 0x66, 0xfd, 0x17, 0xf0, 0x88, 0x71, 0x20, 0xcc, 0x71, 0x80, 0xb3, 356 0x2b, 0x9e, 0xd9, 0x61, 0x9e, 0x3d, 0x9c, 0x51, 0x78, 0x3f, 0x8a, 0x3d,
357 0x09, 0xdf, 0x27, 0x65, 0xb7, 0xc2, 0x67, 0x4b, 0x0a, 0xf0, 0x27, 0x77, 357 0xc9, 0x6b, 0x4b, 0x0a, 0xc0, 0xed, 0x5b, 0x15, 0x96, 0x09, 0x94, 0x26,
358 0x2b, 0x4c, 0x13, 0x48, 0x4d, 0x8c, 0x5f, 0x61, 0xf8, 0xbf, 0x55, 0xe5, 358 0x56, 0x0f, 0x5d, 0x10, 0xc9, 0xfe, 0xa3, 0x7a, 0xdf, 0xee, 0x89, 0x35,
359 0x3d, 0xde, 0x2c, 0xd6, 0x85, 0x72, 0x8b, 0x74, 0x4b, 0x8f, 0x5b, 0x80, 359 0x0b, 0x3b, 0x5c, 0x5a, 0xa1, 0x4c, 0xa3, 0x5c, 0xd7, 0x63, 0x17, 0x7c,
360 0xcf, 0x5f, 0x9c, 0xec, 0xa5, 0xfd, 0x02, 0x6e, 0x72, 0x64, 0x5e, 0xd5, 360 0x60, 0xe6, 0xd1, 0x0e, 0xda, 0x37, 0xe0, 0x27, 0xec, 0x7b, 0x85, 0xed,
361 0xcf, 0xc8, 0xc5, 0xca, 0xcf, 0xcc, 0x3e, 0x99, 0x36, 0xcf, 0x2c, 0x67, 361 0x33, 0xd8, 0x73, 0x3f, 0x68, 0xa7, 0x6d, 0x3f, 0xec, 0x8f, 0xcb, 0xb5,
362 0xac, 0x87, 0x3e, 0xcd, 0x91, 0xd9, 0x65, 0xef, 0x03, 0xa6, 0x5c, 0xc5, 362 0x0a, 0xaf, 0xf9, 0x3e, 0xe5, 0x8b, 0x8a, 0x1b, 0xc7, 0xa6, 0x16, 0x3d,
363 0x5c, 0xac, 0x0f, 0x02, 0x43, 0x8e, 0xac, 0x74, 0x63, 0x3e, 0xf6, 0x90, 363 0xdf, 0xec, 0x31, 0x15, 0xd3, 0xb1, 0x3e, 0x06, 0xcc, 0x38, 0x70, 0xa6,
364 0x3e, 0x93, 0x39, 0x24, 0x33, 0xfe, 0x41, 0xd0, 0x7f, 0x40, 0xca, 0xf0, 364 0x4d, 0xd2, 0x4f, 0xdb, 0x7d, 0xfa, 0x7c, 0xe5, 0x90, 0x14, 0xfd, 0x03,
365 0x95, 0x96, 0xb6, 0xa1, 0x57, 0xc6, 0xe1, 0x13, 0xbb, 0xb7, 0x13, 0xa3, 365 0x98, 0xc3, 0x3e, 0x99, 0x87, 0x2f, 0xb6, 0xb0, 0x31, 0x2c, 0xf3, 0xc3,
366 0xa9, 0x98, 0x52, 0xd9, 0x1d, 0x45, 0xda, 0x83, 0xf4, 0x66, 0x29, 0x3f, 366 0xf0, 0xb9, 0xdd, 0xbb, 0x89, 0xd5, 0xf0, 0xeb, 0xc0, 0xf3, 0x41, 0x94,
367 0x73, 0x43, 0x54, 0xf7, 0xd7, 0xd5, 0xf1, 0xfe, 0x3c, 0xc7, 0x4e, 0x26, 367 0xed, 0x28, 0x6f, 0x97, 0xf9, 0xa7, 0xba, 0x63, 0xba, 0xbf, 0x68, 0xcb,
368 0xad, 0xdf, 0x86, 0x07, 0xdb, 0xb1, 0x20, 0xe9, 0xe8, 0x12, 0xef, 0xcb, 368 0xfd, 0xb3, 0x1c, 0x3b, 0x99, 0xb4, 0x7e, 0x15, 0x2e, 0x6c, 0xc6, 0x84,
369 0x7d, 0x32, 0xba, 0xe2, 0xca, 0xd8, 0x4a, 0x42, 0x0e, 0xae, 0x0c, 0xcb, 369 0xa4, 0x23, 0x2a, 0xde, 0x93, 0x5d, 0x32, 0x78, 0xc6, 0x95, 0xa1, 0x33,
370 0xf8, 0x4a, 0x52, 0x6e, 0x5d, 0x09, 0xf1, 0xd8, 0x83, 0xb3, 0x69, 0x63, 370 0x09, 0x39, 0x70, 0xa6, 0x5f, 0x86, 0xcf, 0x24, 0xe5, 0xce, 0x33, 0x21,
371 0x07, 0xbc, 0xdf, 0xd1, 0x0e, 0xdc, 0xda, 0xd4, 0xd8, 0xb4, 0xbc, 0x71, 371 0xfe, 0xea, 0x9e, 0x4a, 0x1b, 0x5b, 0xe1, 0xfd, 0x9a, 0xb6, 0xe2, 0xce,
372 0x01, 0x36, 0x7b, 0x07, 0xfb, 0x37, 0x03, 0x2c, 0xe6, 0x43, 0x27, 0x4d, 372 0x86, 0xc6, 0xa8, 0xf3, 0x6b, 0xc4, 0x74, 0xaf, 0x62, 0xef, 0x6e, 0xaa,
373 0x42, 0x27, 0x8d, 0x43, 0x27, 0x4d, 0x53, 0x27, 0x01, 0xff, 0xbd, 0x0a, 373 0xf3, 0xca, 0x4b, 0x1b, 0x41, 0x70, 0xc9, 0x6f, 0x77, 0xa7, 0x85, 0xfc,
374 0xfc, 0x77, 0x8f, 0xbc, 0x06, 0x9d, 0xfb, 0x82, 0xdf, 0xe3, 0xce, 0x81, 374 0xce, 0x00, 0x9f, 0xf9, 0xd0, 0x61, 0xa3, 0xd0, 0x61, 0xe3, 0xca, 0x36,
375 0x1f, 0x87, 0xd5, 0xb9, 0x57, 0xea, 0x2b, 0x3b, 0x90, 0x81, 0xc6, 0xd7, 375 0xd6, 0xbf, 0x2e, 0xd6, 0xb1, 0xcc, 0x03, 0xb2, 0x06, 0xd9, 0x7e, 0xd0,
376 0x24, 0x3a, 0x00, 0x7d, 0x75, 0xfb, 0x7a, 0x8f, 0x6c, 0xc4, 0x83, 0xe0, 376 0x4f, 0x7d, 0x75, 0x53, 0xf1, 0x47, 0x62, 0x3d, 0xd0, 0x67, 0x77, 0xaf,
377 0x34, 0xf6, 0xfa, 0x95, 0x8a, 0x96, 0xd9, 0xbc, 0xc7, 0x3d, 0xff, 0x20, 377 0xb6, 0xcb, 0x1b, 0xf1, 0x20, 0x38, 0x0b, 0x1d, 0x50, 0xaf, 0x68, 0xf9,
378 0xe6, 0x3e, 0x89, 0xbc, 0x1c, 0x74, 0x98, 0x8e, 0xa3, 0x34, 0x8e, 0x26, 378 0xcd, 0x7b, 0xd4, 0x05, 0x0f, 0x61, 0xfe, 0xa3, 0x78, 0x96, 0x33, 0xba,
379 0x64, 0xf3, 0xe0, 0x74, 0x47, 0xbd, 0x0c, 0xde, 0xa9, 0x33, 0xfe, 0x39, 379 0xbd, 0x43, 0x6e, 0xc4, 0x13, 0xb2, 0x7e, 0x60, 0xbc, 0xa5, 0x5e, 0x06,
380 0xea, 0x53, 0x7f, 0xbb, 0xb2, 0x05, 0x8c, 0x78, 0xe6, 0x60, 0x6a, 0x3a, 380 0xf7, 0xc0, 0x3d, 0x8d, 0xdf, 0x23, 0xbf, 0xf0, 0xdc, 0x95, 0x73, 0xf0,
381 0x69, 0x53, 0xdf, 0x25, 0xa5, 0xfe, 0xb5, 0x84, 0x6c, 0x54, 0xb5, 0xcd, 381 0x99, 0xcf, 0x1f, 0x48, 0x8d, 0x27, 0x6d, 0xea, 0xc3, 0xa4, 0xd4, 0xbe,
382 0x59, 0x00, 0x26, 0x2c, 0x00, 0xef, 0x6e, 0x00, 0x67, 0x15, 0x9a, 0x5a, 382 0x9e, 0x90, 0xb5, 0x65, 0x6d, 0x97, 0x66, 0xbd, 0x71, 0x29, 0x00, 0xfb,
383 0xdf, 0xdb, 0xd9, 0x2e, 0x61, 0x7f, 0x85, 0x66, 0x1e, 0xf8, 0x58, 0x9c, 383 0xae, 0x2d, 0x67, 0x51, 0xb2, 0x7e, 0xa8, 0x73, 0xb4, 0x5c, 0x16, 0x33,
384 0x7c, 0x86, 0x74, 0x4e, 0x24, 0x22, 0x76, 0x0f, 0x64, 0x81, 0xfb, 0xe3, 384 0x79, 0xec, 0x63, 0xee, 0x0f, 0x6d, 0x77, 0x6c, 0xbb, 0x1d, 0x72, 0xc4,
385 0x41, 0xd8, 0x53, 0x96, 0xd1, 0x36, 0x53, 0xff, 0x3f, 0x15, 0x25, 0xc6, 385 0x3d, 0xf1, 0x30, 0x9e, 0xe7, 0xb1, 0xaf, 0x69, 0xc7, 0xd3, 0x90, 0xaf,
386 0x2b, 0xf8, 0xc4, 0xd3, 0x79, 0x94, 0xa5, 0x12, 0x69, 0xe4, 0xcf, 0x49, 386 0xcf, 0xc6, 0x28, 0x1f, 0x05, 0x9f, 0xf8, 0x9a, 0x6d, 0x52, 0x89, 0x34,
387 0x5a, 0x9d, 0x21, 0x2d, 0x60, 0xcf, 0x97, 0x15, 0xcd, 0x11, 0xc6, 0xa4, 387 0x9e, 0x4f, 0x4b, 0x5a, 0x9d, 0x0b, 0xcd, 0xfa, 0x61, 0x7f, 0x59, 0xa3,
388 0x28, 0x1e, 0x51, 0x1d, 0x2f, 0x0c, 0xf3, 0x27, 0xdc, 0x22, 0xd6, 0x38, 388 0x17, 0x22, 0x8c, 0x81, 0xe1, 0xef, 0x64, 0x8c, 0xf2, 0x18, 0xf1, 0xc2,
389 0xc7, 0xbe, 0xab, 0xcc, 0x4b, 0xbb, 0x6c, 0x57, 0xf0, 0xf9, 0x2e, 0xf2, 389 0xe7, 0x23, 0xb0, 0x3d, 0x51, 0x35, 0xc6, 0xfc, 0x32, 0x9f, 0xa5, 0x5d,
390 0x91, 0x26, 0xe3, 0x27, 0x51, 0x79, 0xb8, 0xd9, 0x07, 0x9a, 0xba, 0x7f, 390 0xb6, 0x2f, 0xf8, 0xbc, 0x17, 0xf9, 0x44, 0x83, 0xf1, 0x9a, 0x98, 0x3c,
391 0x8b, 0x3d, 0x71, 0xdb, 0xec, 0xc9, 0x6e, 0xc2, 0x85, 0x9e, 0x58, 0x34, 391 0xda, 0xe8, 0x02, 0xbd, 0x6d, 0xbf, 0xc2, 0xf6, 0xec, 0xec, 0x73, 0x3b,
392 0x7a, 0xc5, 0x99, 0xd2, 0x18, 0xf8, 0xa5, 0x2a, 0xd6, 0xa8, 0x8a, 0x35, 392 0xbb, 0x95, 0x70, 0x95, 0x6e, 0xa1, 0x1e, 0xa1, 0x0e, 0x69, 0x17, 0x67,
393 0xaa, 0x62, 0x8d, 0xaa, 0x58, 0xa3, 0x2a, 0xf5, 0x07, 0x75, 0x4d, 0xce, 393 0x8c, 0xfb, 0x0c, 0x6b, 0xb2, 0x8c, 0x35, 0x5a, 0xc6, 0x1a, 0x2d, 0x63,
394 0x9c, 0x31, 0x50, 0x87, 0x3c, 0x8f, 0xb5, 0x9c, 0x93, 0x6f, 0x6f, 0xcf, 394 0x8d, 0x96, 0xb1, 0x7e, 0xcb, 0xd4, 0x2d, 0x83, 0xd8, 0xcf, 0x39, 0x73,
395 0xca, 0x5f, 0x6c, 0x1f, 0x01, 0xc6, 0x9e, 0xc1, 0xba, 0xe6, 0xb0, 0xae, 395 0x86, 0x40, 0xfd, 0xf2, 0x1c, 0xd6, 0x76, 0x5a, 0xfe, 0x76, 0x63, 0x52,
396 0xd3, 0x58, 0xd3, 0xa3, 0x58, 0xd3, 0x2c, 0xcf, 0xd9, 0xe4, 0xcb, 0x95, 396 0xfe, 0xf3, 0xc6, 0x11, 0xe0, 0xee, 0x22, 0xd6, 0x35, 0x87, 0x75, 0xcd,
397 0xd4, 0x0b, 0x25, 0x85, 0xef, 0xdf, 0xc0, 0xfa, 0x4e, 0x89, 0xb7, 0x3e, 397 0x62, 0x5d, 0x8f, 0x62, 0x5d, 0xc7, 0x55, 0xcc, 0xb3, 0x5a, 0x49, 0x5d,
398 0x0c, 0x9d, 0x50, 0x0a, 0xe2, 0x5e, 0x70, 0x08, 0x18, 0x1a, 0xf3, 0x2f, 398 0x2a, 0x2b, 0x8c, 0xff, 0x16, 0xe4, 0x61, 0x4c, 0x9c, 0xd5, 0x7e, 0xe8,
399 0xa5, 0x1c, 0x45, 0x83, 0xe7, 0x7e, 0x0a, 0x13, 0xbf, 0x21, 0x9b, 0xaa, 399 0x8b, 0x72, 0x10, 0xf7, 0x82, 0x43, 0xc0, 0xd6, 0x18, 0xbb, 0x9c, 0x72,
400 0x51, 0x3d, 0x6d, 0xd5, 0xc6, 0xa5, 0x78, 0x0e, 0xf5, 0x4f, 0xf7, 0x81, 400 0x94, 0xee, 0xf3, 0xdc, 0xcf, 0x63, 0xaf, 0xbc, 0x2f, 0x9b, 0xaa, 0x52,
401 0xdf, 0xc4, 0x6f, 0xa9, 0x52, 0x51, 0x76, 0xa0, 0xcf, 0x72, 0xa0, 0xf1, 401 0x75, 0x9d, 0xab, 0x0e, 0x4b, 0xe9, 0x22, 0xea, 0x9f, 0xed, 0x02, 0xad,
402 0xbd, 0x52, 0x8e, 0xa7, 0x9e, 0xe7, 0x3e, 0xbb, 0x71, 0x95, 0xf1, 0x01, 402 0xc4, 0x7c, 0xa9, 0xd3, 0x25, 0xd9, 0x84, 0xbe, 0xcb, 0x81, 0xc6, 0x0f,
403 0x1b, 0xbc, 0x21, 0xed, 0x78, 0x3e, 0x97, 0x55, 0x31, 0xbe, 0xbc, 0x7f, 403 0xc9, 0x7c, 0x3c, 0xf5, 0x9c, 0xc8, 0xb8, 0xdc, 0x03, 0x3f, 0x9d, 0xf1,
404 0xc0, 0xec, 0x63, 0x8d, 0x49, 0xeb, 0xc2, 0x71, 0x39, 0xde, 0x67, 0x64, 404 0xcc, 0x9c, 0x8a, 0xb1, 0xe1, 0xfa, 0x62, 0x16, 0xfe, 0x36, 0x6d, 0xec,
405 0x11, 0xb8, 0xcf, 0xce, 0x12, 0x57, 0x78, 0x09, 0x8c, 0x19, 0x5d, 0x38, 405 0x3e, 0xe3, 0x87, 0x6b, 0x1c, 0x5b, 0x13, 0x8e, 0xcb, 0xf1, 0xfe, 0x58,
406 0xe7, 0x46, 0x17, 0xcf, 0xb1, 0x9f, 0xa8, 0xa4, 0x57, 0xa9, 0x97, 0xd8, 406 0xe6, 0x80, 0x15, 0xe1, 0xeb, 0x03, 0x8b, 0x78, 0x09, 0x8c, 0x19, 0x9b,
407 0x0f, 0x74, 0x36, 0xfa, 0x8e, 0xa8, 0x33, 0xb5, 0x09, 0xb4, 0xfb, 0x03, 407 0xbd, 0xe8, 0xc6, 0xe6, 0x2e, 0xb2, 0x9f, 0x98, 0x44, 0x96, 0xa8, 0xb3,
408 0x60, 0x46, 0xcd, 0xc3, 0xfc, 0x69, 0x6d, 0xc7, 0xf2, 0x8d, 0x76, 0xcc, 408 0xd8, 0x0f, 0x74, 0x3b, 0xfa, 0x4e, 0xab, 0x33, 0xb3, 0x11, 0xb4, 0xfb,
409 0x06, 0x1d, 0x02, 0x3b, 0x97, 0x6b, 0x68, 0xfc, 0x35, 0xa3, 0xf0, 0x99, 409 0x5d, 0xe0, 0x4c, 0xcd, 0xc7, 0xfc, 0x59, 0x6d, 0xf7, 0xf2, 0xf5, 0x66,
410 0xc6, 0x66, 0x47, 0xe5, 0x50, 0xaf, 0xc4, 0x3c, 0x35, 0x9f, 0xf4, 0xe9, 410 0xac, 0x07, 0xdd, 0x02, 0xbb, 0x98, 0xab, 0x6b, 0xdc, 0x56, 0x54, 0xb8,
411 0x1d, 0x62, 0x52, 0x8c, 0xa1, 0xe3, 0xcc, 0x57, 0xe9, 0xce, 0x60, 0x2e, 411 0x4e, 0x63, 0xba, 0xa3, 0x72, 0xa8, 0x43, 0x3a, 0x3d, 0x35, 0x9f, 0xc8,
412 0x37, 0xf7, 0x86, 0x31, 0x41, 0x7b, 0x55, 0x9f, 0x41, 0xd9, 0xe7, 0x7c, 412 0xd9, 0x4d, 0xe2, 0x58, 0x8c, 0xc1, 0x36, 0xd1, 0x26, 0xba, 0x33, 0xb0,
413 0xcc, 0x47, 0x86, 0x18, 0x65, 0xb4, 0x31, 0x87, 0x7b, 0x95, 0x9d, 0x9d, 413 0xa7, 0xb7, 0x77, 0x50, 0x66, 0x3e, 0x09, 0xdc, 0x38, 0xb0, 0xa4, 0xcf,
414 0x62, 0xec, 0x0f, 0xb2, 0x4d, 0xfd, 0x32, 0x84, 0xbd, 0xc1, 0x77, 0x1d, 414 0x98, 0x06, 0x2e, 0xfa, 0x98, 0x8f, 0xf4, 0x31, 0xb2, 0x69, 0x63, 0x0e,
415 0x53, 0xee, 0xf1, 0x28, 0x2f, 0x71, 0xc8, 0x20, 0x74, 0x4d, 0xff, 0xb0, 415 0x1f, 0x55, 0x76, 0x79, 0x0c, 0xb6, 0xd8, 0x85, 0xac, 0x53, 0xe7, 0xf4,
416 0xd4, 0xb7, 0x59, 0x36, 0xac, 0xf4, 0xb0, 0x83, 0x35, 0x58, 0xae, 0x04, 416 0x61, 0xff, 0xf0, 0x9e, 0xba, 0x87, 0x7a, 0x8c, 0x32, 0x13, 0x07, 0x6e,
417 0x87, 0xf2, 0x7e, 0x09, 0xda, 0x92, 0x3c, 0x27, 0x3f, 0xc8, 0xf7, 0x49, 417 0x82, 0xfe, 0xe9, 0xee, 0x97, 0xda, 0x06, 0xdf, 0xf5, 0x2b, 0x1d, 0xed,
418 0xd0, 0x46, 0x1e, 0xf7, 0x97, 0xf4, 0xb9, 0xe6, 0x7e, 0x29, 0xd6, 0xa8, 418 0x60, 0x0d, 0x16, 0x2b, 0xc1, 0xa1, 0xbc, 0x5f, 0x86, 0x16, 0x25, 0xcf,
419 0x8b, 0x91, 0xd6, 0xf7, 0x9b, 0xd8, 0x46, 0x5c, 0x72, 0x73, 0x9c, 0x3b, 419 0xc9, 0x0f, 0xf2, 0x7d, 0x14, 0xb4, 0x91, 0xc7, 0xdd, 0x65, 0x7d, 0x6e,
420 0x7d, 0x13, 0xa0, 0xba, 0xd5, 0x94, 0x5f, 0xb7, 0x67, 0xa5, 0x48, 0xf9, 420 0xb9, 0x57, 0x4a, 0x55, 0xea, 0x69, 0x94, 0xb5, 0xbd, 0xf0, 0x9d, 0x5c,
421 0x84, 0x6e, 0x2c, 0x6e, 0x4e, 0xc9, 0xf2, 0x1a, 0xe3, 0x7d, 0x3c, 0x7b, 421 0x85, 0x65, 0x73, 0xd3, 0x9c, 0x7b, 0xac, 0xec, 0x42, 0x6e, 0xdd, 0x83,
422 0x9e, 0x88, 0x4a, 0x7f, 0x10, 0x6c, 0xf9, 0xb4, 0xf3, 0x79, 0x29, 0x20, 422 0x93, 0x2a, 0xa6, 0x72, 0x79, 0x29, 0xe5, 0xd7, 0x6c, 0x8c, 0x09, 0x9d,
423 0xdf, 0x5e, 0x87, 0x9d, 0x3f, 0xaa, 0x79, 0xc7, 0xf9, 0x96, 0x37, 0xfe, 423 0x69, 0x9f, 0x1f, 0x93, 0xb9, 0x95, 0x6e, 0x19, 0x5c, 0xe5, 0xf9, 0xf2,
424 0x6f, 0xf8, 0xf8, 0xf6, 0x38, 0x77, 0x66, 0x0f, 0x9c, 0xfb, 0xea, 0x39, 424 0x50, 0x4c, 0xba, 0x83, 0xe0, 0x9c, 0x9f, 0x57, 0xb1, 0xc7, 0x81, 0x55,
425 0xc8, 0x5f, 0x15, 0xb2, 0x09, 0x9f, 0xe9, 0x2f, 0xaa, 0x90, 0x4d, 0xd8, 425 0x60, 0x82, 0xa3, 0x9a, 0x77, 0x9c, 0x2f, 0x74, 0xc4, 0xbf, 0x82, 0x8f,
426 0x8c, 0x6f, 0x56, 0x21, 0x9b, 0xd8, 0x3b, 0x2f, 0xc2, 0xa7, 0xd1, 0x98, 426 0xef, 0x8e, 0x8f, 0x8b, 0xbb, 0xe0, 0xe3, 0x57, 0x2f, 0x42, 0xfe, 0x96,
427 0xe2, 0x11, 0x85, 0x29, 0x4e, 0x54, 0x89, 0xf9, 0x2f, 0x41, 0x96, 0x27, 427 0x21, 0x9b, 0xcb, 0x90, 0xcd, 0x65, 0xc8, 0xe6, 0x32, 0x64, 0x73, 0x19,
428 0x21, 0xc7, 0x49, 0xc8, 0xaf, 0x0f, 0xd9, 0x1d, 0x87, 0x3c, 0x7b, 0x90, 428 0xb2, 0x89, 0xfd, 0xf3, 0xfc, 0xf2, 0xb8, 0xc1, 0x1f, 0x9f, 0x82, 0x2c,
429 0xe7, 0x61, 0x15, 0xf7, 0x79, 0x61, 0x3b, 0x2a, 0xf7, 0xc3, 0x9f, 0x38, 429 0x7f, 0xdb, 0xe0, 0x8f, 0x51, 0xc8, 0x70, 0x12, 0xb2, 0xeb, 0x43, 0x6e,
430 0x53, 0x23, 0x1f, 0x8f, 0xcb, 0xff, 0x82, 0x2f, 0xb1, 0xeb, 0xef, 0x80, 430 0x87, 0x21, 0xcb, 0x1e, 0x64, 0xb9, 0x1f, 0x72, 0x9c, 0x50, 0xfe, 0xe3,
431 0x87, 0x39, 0x59, 0xf4, 0xc8, 0xaf, 0x9c, 0xbd, 0xe0, 0xd1, 0xd7, 0x70, 431 0x04, 0xb0, 0xe8, 0x83, 0xf0, 0x41, 0xce, 0x57, 0xfb, 0x65, 0x51, 0xd1,
432 0xe5, 0xcc, 0x06, 0x7d, 0x04, 0xea, 0x88, 0x57, 0xe5, 0x9b, 0x95, 0x1f, 432 0x12, 0xc8, 0x96, 0xbf, 0x49, 0x1e, 0x62, 0x5f, 0xd0, 0x3f, 0x77, 0xe5,
433 0xc8, 0xb7, 0x80, 0x05, 0x0a, 0xf0, 0x9b, 0x37, 0x9e, 0xa1, 0xcf, 0xa8, 433 0xfc, 0x5a, 0x48, 0xdb, 0xab, 0xf2, 0xcd, 0xca, 0x6b, 0xf2, 0x42, 0x85,
434 0x68, 0x84, 0xdc, 0xc5, 0x65, 0x73, 0xfb, 0x76, 0x79, 0xca, 0xa5, 0x0c, 434 0x34, 0xe6, 0x64, 0x11, 0xef, 0xd6, 0x9e, 0xa2, 0x1f, 0xa9, 0xe8, 0x83,
435 0xc7, 0xa1, 0x5b, 0xf0, 0x7e, 0x90, 0x7a, 0x28, 0x83, 0xfd, 0x09, 0x39, 435 0xcc, 0x9d, 0x94, 0xff, 0x03, 0x5e, 0xae, 0x6f, 0x7c, 0x58, 0x3e, 0xe7,
436 0x87, 0x6e, 0xa8, 0xd9, 0x3c, 0xc3, 0x28, 0x05, 0x03, 0xd4, 0x59, 0x35, 436 0x52, 0x86, 0xe3, 0xd0, 0x35, 0xb8, 0x3f, 0x40, 0xbd, 0x04, 0x3f, 0xb4,
437 0xcf, 0x1d, 0xb1, 0xc9, 0x9b, 0x5b, 0x18, 0x73, 0xfa, 0x0a, 0x84, 0x17, 437 0x92, 0x2a, 0x97, 0xa0, 0x27, 0xaa, 0xf6, 0x08, 0x30, 0x58, 0x39, 0xe8,
438 0x79, 0xb4, 0xd9, 0x48, 0xeb, 0xd0, 0x8d, 0xcf, 0x90, 0x8f, 0xf4, 0x61, 438 0xa1, 0x0e, 0xab, 0x7a, 0xee, 0x80, 0x4d, 0xde, 0xec, 0x87, 0xbc, 0xa4,
439 0xf1, 0xbc, 0xc1, 0xbd, 0xf6, 0x73, 0x15, 0xcb, 0x2d, 0xce, 0xc1, 0x5f, 439 0xbe, 0x0a, 0xe1, 0xc5, 0x33, 0xda, 0x73, 0x94, 0x35, 0xe8, 0xcf, 0xa7,
440 0xdf, 0x20, 0x9f, 0x20, 0x2b, 0xcf, 0x90, 0x8f, 0xe4, 0x9d, 0xe6, 0xe3, 440 0xc8, 0x47, 0xfa, 0xb5, 0xb8, 0x56, 0xba, 0xf7, 0x27, 0x2a, 0x7e, 0x5c,
441 0x43, 0x12, 0xf2, 0x90, 0x65, 0x9d, 0x3c, 0xfc, 0x77, 0x90, 0xc3, 0x38, 441 0x9a, 0x86, 0x2f, 0xbf, 0x46, 0x3e, 0x41, 0x56, 0x9e, 0x22, 0x1f, 0x49,
442 0xe6, 0xfd, 0xd5, 0x28, 0x63, 0x8e, 0x37, 0x7a, 0x5c, 0xf3, 0x57, 0xe5, 442 0x9f, 0xe6, 0xe3, 0x23, 0x12, 0xf2, 0x90, 0xef, 0x5a, 0x79, 0x08, 0x27,
443 0xc9, 0x26, 0xc7, 0x7a, 0xd9, 0x8c, 0xf9, 0xfd, 0xe0, 0xe1, 0x38, 0x69, 443 0xaa, 0x33, 0x8e, 0xb9, 0x7f, 0x2d, 0x66, 0x62, 0xc8, 0xc6, 0x26, 0xbf,
444 0xe7, 0x7a, 0xee, 0x93, 0xc6, 0x90, 0x6f, 0xe2, 0x2a, 0xbf, 0xcd, 0xde, 444 0x2a, 0xd3, 0x0d, 0xce, 0xc7, 0x92, 0xdb, 0xbc, 0xab, 0xf0, 0xa9, 0x38,
445 0xb0, 0x1e, 0x78, 0x0d, 0xbd, 0xf2, 0xad, 0x2a, 0x78, 0x0c, 0xbf, 0xe9, 445 0xf6, 0xab, 0xc1, 0xa3, 0x71, 0xce, 0x81, 0xeb, 0xba, 0x47, 0xea, 0x7d,
446 0x1b, 0xf0, 0x9b, 0x18, 0x6b, 0xd4, 0xeb, 0x32, 0x6d, 0xe2, 0xa6, 0x9d, 446 0xbe, 0x89, 0xaf, 0xfc, 0x2a, 0x5b, 0xc4, 0x7a, 0xe0, 0x3b, 0xf4, 0xcb,
447 0xf1, 0xd2, 0x24, 0xd6, 0x85, 0xbe, 0x79, 0xaa, 0x74, 0x19, 0xba, 0xef, 447 0x0b, 0xcb, 0xe0, 0x37, 0xfc, 0xae, 0x6f, 0xc0, 0xef, 0x62, 0x9c, 0x53,
448 0x45, 0x9f, 0x71, 0xc4, 0x40, 0xbe, 0xef, 0xb7, 0x6b, 0x37, 0x15, 0x63, 448 0xaf, 0xcf, 0xb8, 0x89, 0xd9, 0xb6, 0xc6, 0x6a, 0x93, 0x58, 0x23, 0xfa,
449 0x96, 0x87, 0xa0, 0x0f, 0x1f, 0x86, 0x3e, 0xfc, 0xc8, 0x75, 0xf7, 0x7b, 449 0xed, 0xa9, 0xf2, 0x75, 0xe8, 0xc1, 0xe7, 0x7d, 0xc6, 0xf8, 0x02, 0xf9,
450 0x28, 0x67, 0x4f, 0xcf, 0x2e, 0xac, 0x8d, 0x96, 0x22, 0xf6, 0xb0, 0xcc, 450 0xef, 0x7e, 0xb3, 0xa6, 0x53, 0xf1, 0x6d, 0x79, 0x04, 0xba, 0xf1, 0x51,
451 0x5d, 0xa3, 0x1b, 0x19, 0x4f, 0x4c, 0x9a, 0x78, 0x68, 0x3b, 0xfe, 0x0c, 451 0xe8, 0xc6, 0x4f, 0xdc, 0x92, 0xe7, 0x43, 0x79, 0xbb, 0x7f, 0x6a, 0x76,
452 0x63, 0x9e, 0x94, 0xe7, 0x40, 0x2e, 0xfa, 0xa5, 0xbe, 0x88, 0x3a, 0x97, 452 0x65, 0xb0, 0x1c, 0xb1, 0xfb, 0x31, 0xa7, 0xe6, 0xb6, 0x8c, 0xf1, 0x25,
453 0xe6, 0xba, 0xee, 0x85, 0x2d, 0xbf, 0x6d, 0xf6, 0x30, 0x65, 0xab, 0xf3, 453 0x4d, 0x2c, 0xb6, 0x19, 0xb3, 0x86, 0xf1, 0x56, 0xca, 0x74, 0x20, 0xd7,
454 0xdc, 0x98, 0xe7, 0xd0, 0xfd, 0xf0, 0x13, 0xb8, 0x57, 0x53, 0xc9, 0x1c, 454 0xfc, 0x72, 0x57, 0x44, 0x9d, 0x3f, 0x7b, 0xb4, 0x13, 0xbb, 0xfc, 0xbd,
455 0xf6, 0x73, 0x79, 0x9b, 0xfa, 0x9f, 0xd8, 0xb0, 0x9b, 0xf1, 0xbc, 0xf9, 455 0xd8, 0xa1, 0xed, 0xf3, 0x5b, 0x46, 0xc6, 0x76, 0x72, 0x99, 0x26, 0x32,
456 0x9e, 0x2c, 0x63, 0x01, 0xfd, 0xf0, 0x3f, 0x7e, 0x24, 0x5b, 0x6b, 0x7f, 456 0xe1, 0x99, 0x73, 0x37, 0x6c, 0x1e, 0xf7, 0x6d, 0x2a, 0x99, 0xc3, 0xde,
457 0xd3, 0xab, 0xf7, 0x91, 0xbe, 0x6f, 0x66, 0x9f, 0xeb, 0x8c, 0x63, 0xd2, 457 0x9e, 0xdf, 0xa0, 0x5d, 0x20, 0x9e, 0x6c, 0x63, 0x4c, 0x6f, 0xa6, 0x3d,
458 0xa6, 0x4a, 0xb4, 0x17, 0x76, 0xf1, 0xd6, 0x67, 0xfb, 0x95, 0xdd, 0xbb, 458 0xcb, 0xd8, 0x41, 0x37, 0xfc, 0x97, 0xd7, 0xe5, 0xdc, 0xca, 0x3f, 0x75,
459 0xcf, 0x77, 0x64, 0x27, 0xce, 0xfe, 0x7e, 0x24, 0x3f, 0x5e, 0x1b, 0x89, 459 0xe8, 0xfd, 0xa4, 0x73, 0xcf, 0xec, 0x8b, 0xad, 0x71, 0x54, 0xbd, 0x46,
460 0x31, 0xfe, 0xb9, 0x0c, 0x3e, 0xef, 0x2a, 0xdd, 0xf5, 0x20, 0xea, 0x64, 460 0x85, 0x4c, 0x37, 0x30, 0x0c, 0xfd, 0xa5, 0x6b, 0xca, 0x5f, 0x3a, 0xec,
461 0xe5, 0xf5, 0x35, 0xda, 0xd6, 0xb4, 0x7b, 0x46, 0x26, 0x12, 0x67, 0xc0, 461 0x3b, 0xb2, 0x19, 0x67, 0x9f, 0xaf, 0xcb, 0xb1, 0x95, 0xe1, 0x4e, 0xc6,
462 0xcb, 0x53, 0x68, 0x03, 0x7f, 0x38, 0x98, 0x41, 0xde, 0xcb, 0xf4, 0xb9, 462 0x2b, 0x17, 0x97, 0x0f, 0xc8, 0x96, 0xd2, 0x65, 0x0f, 0xa3, 0x6e, 0x16,
463 0x2d, 0x3e, 0x4f, 0xb8, 0x5f, 0x04, 0x4e, 0xce, 0xb9, 0x69, 0xb7, 0xd7, 463 0x7b, 0x36, 0x08, 0x26, 0xfc, 0xb4, 0x7b, 0x5e, 0x46, 0x12, 0xe7, 0xc1,
464 0xba, 0xa4, 0xce, 0x9d, 0x22, 0x1e, 0xfb, 0x1a, 0x92, 0xc2, 0xa6, 0xa6, 464 0xd3, 0x3f, 0x43, 0x1b, 0xf8, 0xd4, 0x41, 0x11, 0xcf, 0xae, 0xc2, 0x6f,
465 0xf1, 0xca, 0x26, 0xc7, 0xe0, 0x5c, 0x48, 0xe3, 0xdf, 0xf0, 0x5c, 0x01, 465 0xbf, 0x21, 0xbc, 0x1e, 0x71, 0x4f, 0x43, 0x18, 0x72, 0x6e, 0xda, 0x7d,
466 0xf4, 0xdf, 0x06, 0x9f, 0x84, 0x98, 0xe5, 0x12, 0x64, 0x66, 0x08, 0xfa, 466 0x4b, 0x42, 0xdb, 0x45, 0x3b, 0xc5, 0x33, 0xeb, 0x3e, 0x29, 0xac, 0x6b,
467 0x81, 0xbe, 0x0a, 0xcf, 0x2c, 0xc9, 0xb3, 0xcf, 0x03, 0xef, 0xc7, 0x21, 467 0x5a, 0xe7, 0x41, 0xeb, 0xa9, 0x15, 0x8e, 0xc1, 0x79, 0x91, 0xde, 0x7f,
468 0xab, 0xc8, 0xdf, 0xbc, 0xea, 0x1f, 0x2e, 0xb7, 0x70, 0x3d, 0x6d, 0xe3, 468 0xe2, 0x19, 0x07, 0xe6, 0xf2, 0x41, 0x60, 0x59, 0xe2, 0x28, 0x1d, 0x8b,
469 0x2c, 0x6c, 0xe4, 0xbb, 0x14, 0x3d, 0x47, 0x7c, 0xf8, 0xda, 0xcf, 0x50, 469 0x28, 0xa0, 0x8d, 0xc2, 0x5a, 0x3e, 0xcf, 0x2b, 0xc9, 0xc7, 0x2f, 0xc2,
470 0xbe, 0x0e, 0x4a, 0x31, 0x4e, 0x5c, 0x49, 0x7d, 0xb2, 0x9b, 0x88, 0x02, 470 0x6f, 0x88, 0x43, 0x8e, 0xf1, 0x7c, 0xbd, 0x39, 0xe6, 0xcb, 0xfa, 0xfa,
471 0xd7, 0x46, 0x6f, 0xe7, 0xbe, 0x3b, 0x22, 0xf7, 0x7b, 0x0f, 0xca, 0x07, 471 0x1c, 0xed, 0x92, 0xf2, 0x11, 0xf2, 0xc0, 0x85, 0x93, 0xa8, 0xcb, 0x78,
472 0xbd, 0x49, 0x99, 0xf1, 0xee, 0x91, 0xc3, 0x5e, 0x5e, 0xee, 0xf3, 0x60, 472 0x67, 0x10, 0x1c, 0xf7, 0xe1, 0xc7, 0x3f, 0x45, 0xd9, 0xbb, 0x53, 0x4a,
473 0x9b, 0x14, 0x3e, 0xef, 0xc1, 0x3c, 0x38, 0xf6, 0x90, 0x39, 0xdf, 0xd3, 473 0xca, 0xe7, 0x20, 0x86, 0x65, 0xfe, 0xc6, 0x96, 0x1b, 0xc3, 0xfe, 0x9c,
474 0xf8, 0xf4, 0xeb, 0xdb, 0x5a, 0x27, 0xe5, 0xd7, 0xb2, 0x31, 0xda, 0xe4, 474 0x86, 0x6d, 0xcb, 0xc3, 0xb6, 0x45, 0xee, 0x3e, 0x02, 0x3c, 0xab, 0xce,
475 0x23, 0xfe, 0x8c, 0xb1, 0xc9, 0xf0, 0xf9, 0x55, 0xbd, 0x19, 0x65, 0xbb, 475 0xd9, 0x60, 0x3f, 0x39, 0xee, 0xc3, 0xd6, 0xdf, 0x67, 0x46, 0x81, 0x6f,
476 0xcb, 0x9b, 0x73, 0x48, 0x61, 0xc7, 0x37, 0xa7, 0x81, 0xfb, 0xe9, 0x4b, 476 0x1f, 0x00, 0xbe, 0x65, 0x1e, 0x59, 0x1e, 0x18, 0x97, 0xf8, 0xd6, 0x95,
477 0xe5, 0xf0, 0x7e, 0x0f, 0xde, 0x3f, 0x84, 0xf4, 0x08, 0x52, 0x75, 0xae, 477 0xbf, 0xda, 0xc8, 0x43, 0xb7, 0x4d, 0x74, 0x52, 0x17, 0x1f, 0xd9, 0xb6,
478 0x19, 0xd3, 0xb1, 0xdb, 0xd6, 0xb9, 0x1d, 0xe4, 0xeb, 0xe8, 0xec, 0x42, 478 0xd3, 0x45, 0x63, 0xc7, 0xf7, 0x49, 0x41, 0x9d, 0xbb, 0x15, 0x95, 0xbd,
479 0x2d, 0x8c, 0x81, 0x1f, 0x92, 0xc7, 0x7d, 0x7d, 0x96, 0x7e, 0x18, 0x7e, 479 0x9f, 0x5f, 0x27, 0xae, 0x87, 0xed, 0x5f, 0x87, 0xef, 0x57, 0xa1, 0x8f,
480 0x74, 0x0c, 0xf8, 0xe9, 0x43, 0xcf, 0x4e, 0x49, 0xe4, 0xee, 0x43, 0x62, 480 0x96, 0xc3, 0xfd, 0x03, 0xb8, 0x7f, 0x08, 0xe5, 0x11, 0x94, 0xda, 0xf7,
481 0xdf, 0x6d, 0xc9, 0xc2, 0x24, 0xe8, 0x9b, 0x1c, 0xc5, 0x3c, 0x86, 0xe5, 481 0xb9, 0xb4, 0x1c, 0xe9, 0xd4, 0x31, 0xde, 0x44, 0x93, 0xff, 0x43, 0x39,
482 0xc4, 0xb6, 0xf2, 0x51, 0x0d, 0x5e, 0xa4, 0x1e, 0x07, 0xd6, 0xdd, 0x0e, 482 0x8c, 0x4f, 0xcd, 0x56, 0xc3, 0x38, 0xfd, 0x21, 0x39, 0xee, 0xeb, 0xb3,
483 0x71, 0x63, 0x37, 0x70, 0x05, 0xe3, 0x7b, 0x49, 0x85, 0x77, 0xed, 0x1b, 483 0xf5, 0x09, 0xf8, 0xeb, 0x9d, 0xc0, 0x60, 0x0f, 0x3d, 0x0d, 0x9b, 0x71,
484 0xb9, 0xbe, 0x7d, 0x92, 0xbf, 0x91, 0xfc, 0x63, 0x1e, 0xfc, 0x9d, 0x1b, 484 0xdf, 0x21, 0xb1, 0xef, 0xb3, 0x64, 0x76, 0x14, 0x74, 0x8f, 0x0e, 0x42,
485 0xb5, 0xdd, 0x48, 0xaf, 0x70, 0x6d, 0x7a, 0x4c, 0xec, 0x96, 0x36, 0x80, 485 0x3f, 0xf7, 0xc3, 0xdf, 0x56, 0x7e, 0xb0, 0xc1, 0x9c, 0xd4, 0xfb, 0x71,
486 0xe9, 0x6a, 0xac, 0x85, 0x0b, 0x19, 0x9f, 0xb1, 0x6e, 0x8f, 0x5d, 0xbd, 486 0xf9, 0xf3, 0x8d, 0x10, 0x7b, 0xb6, 0x01, 0xa7, 0x32, 0x56, 0x98, 0x54,
487 0x67, 0x16, 0xca, 0x73, 0x78, 0x7f, 0xc0, 0x53, 0x38, 0xe7, 0x44, 0xf5, 487 0xb8, 0xd9, 0xbe, 0x8d, 0xeb, 0xdf, 0x25, 0xf9, 0xdb, 0xc8, 0x53, 0x3e,
488 0x05, 0xcc, 0x81, 0x36, 0x3d, 0x22, 0xdd, 0xd0, 0x6b, 0x5b, 0x1e, 0xf7, 488 0x03, 0xa6, 0x51, 0xd7, 0x71, 0x49, 0x9f, 0xe1, 0xba, 0xb5, 0x9b, 0x18,
489 0x1e, 0x6d, 0xce, 0x11, 0xcc, 0x87, 0x36, 0x9e, 0xb6, 0xfe, 0xde, 0x7e, 489 0x2f, 0x6d, 0x06, 0xcb, 0xbf, 0xec, 0xdc, 0xc6, 0x96, 0x8c, 0x01, 0x59,
490 0xe9, 0xa7, 0x9d, 0x67, 0xfd, 0x24, 0xca, 0x58, 0x97, 0x79, 0x97, 0x51, 490 0xe3, 0x9d, 0x3b, 0x79, 0x69, 0xa1, 0xdc, 0x87, 0xf9, 0x04, 0x94, 0xff,
491 0x9f, 0xb1, 0x29, 0xf8, 0x3e, 0xd5, 0x45, 0xe8, 0x19, 0x0f, 0xe9, 0xe3, 491 0x4b, 0xa0, 0x9f, 0xf6, 0x9e, 0xb6, 0xc1, 0xb5, 0xa2, 0x07, 0x89, 0x05,
492 0x48, 0xc7, 0x91, 0x3e, 0x81, 0x54, 0xc7, 0xb1, 0x36, 0x9f, 0x61, 0x2c, 492 0x22, 0xd2, 0xe6, 0x71, 0x9f, 0xd2, 0x4e, 0x1d, 0xc1, 0x9c, 0x88, 0x0d,
493 0x49, 0xc5, 0x68, 0x14, 0xbe, 0xa0, 0x4d, 0x9c, 0xf3, 0xa9, 0x27, 0x8f, 493 0x3e, 0xdf, 0x2d, 0xdd, 0xc4, 0x07, 0x49, 0x3c, 0xbb, 0x8e, 0x7a, 0xbc,
494 0x8b, 0x3d, 0x75, 0x1b, 0xf2, 0xe8, 0x6b, 0x63, 0xd4, 0xf7, 0x7f, 0xde, 494 0x67, 0x3d, 0xf8, 0x52, 0xcb, 0x62, 0x45, 0x0e, 0xce, 0x41, 0xae, 0x3d,
495 0xc4, 0x88, 0x5a, 0x71, 0x25, 0x63, 0x07, 0xd6, 0xd0, 0x17, 0xfb, 0xa1, 495 0x5c, 0x1f, 0x47, 0x39, 0x8c, 0xf2, 0x71, 0x94, 0xd4, 0x4f, 0x57, 0x65,
496 0x2f, 0xfb, 0x0b, 0x79, 0xf8, 0x9a, 0xd8, 0x5c, 0x2b, 0xde, 0x34, 0x5d, 496 0x56, 0xc7, 0x7f, 0x14, 0x0e, 0xa1, 0xed, 0x9c, 0xf6, 0xa9, 0x53, 0x4f,
497 0x50, 0x3a, 0x96, 0x7c, 0x81, 0x7e, 0x75, 0x33, 0xf2, 0xb5, 0xed, 0x01, 497 0x8a, 0x3d, 0xf6, 0x41, 0x3c, 0xa3, 0x1f, 0x8f, 0x91, 0xee, 0xff, 0x82,
498 0xe8, 0xaf, 0x38, 0xb1, 0x26, 0xf0, 0xb6, 0xc6, 0x6e, 0x8b, 0x98, 0x9b, 498 0x89, 0x3f, 0x6d, 0xc7, 0xac, 0x8c, 0x4e, 0x5e, 0x51, 0x31, 0xfc, 0xf5,
499 0xb6, 0xef, 0x71, 0xf9, 0xbb, 0xb5, 0x61, 0xf9, 0x71, 0x25, 0x21, 0xaf, 499 0xa7, 0xe8, 0x23, 0xff, 0x54, 0x1e, 0xbd, 0x29, 0xb6, 0xb7, 0x1d, 0xcb,
500 0x57, 0x82, 0xe0, 0xa2, 0x9f, 0xf6, 0xef, 0x13, 0xb9, 0xbd, 0x5b, 0x9f, 500 0x1a, 0x2f, 0x28, 0x5d, 0x4c, 0x7e, 0x40, 0x0f, 0xbb, 0x19, 0xf9, 0xfa,
501 0xfd, 0xa3, 0x86, 0x3e, 0xaf, 0x2f, 0xab, 0x33, 0x7b, 0xd4, 0x83, 0x5e, 501 0x46, 0x0f, 0xf4, 0x5b, 0x5c, 0xde, 0x58, 0x09, 0x80, 0xd5, 0xb9, 0x37,
502 0x79, 0xbd, 0xf9, 0xf7, 0xe0, 0xaf, 0xee, 0xb3, 0xb3, 0xed, 0xae, 0x6e, 502 0x47, 0x60, 0x33, 0x5d, 0x83, 0x03, 0xe2, 0xf2, 0x2f, 0x90, 0xf3, 0x7f,
503 0xcb, 0x33, 0xff, 0xc4, 0x8e, 0xa4, 0xcd, 0xdd, 0x81, 0x34, 0xda, 0xa6, 503 0xae, 0x24, 0xe4, 0xcd, 0x4a, 0x10, 0x5c, 0xf3, 0xd3, 0xfe, 0x61, 0x91,
504 0xc7, 0x37, 0x5a, 0xed, 0xd9, 0x36, 0xa3, 0xec, 0x40, 0x71, 0x73, 0x50, 504 0xbb, 0xdb, 0x74, 0x0e, 0x00, 0x6a, 0xe8, 0x73, 0xfb, 0x79, 0x75, 0x76,
505 0x1a, 0x7f, 0xca, 0xfd, 0x01, 0xbf, 0x53, 0x9d, 0xcb, 0x30, 0xe5, 0x39, 505 0x8f, 0x7a, 0xd0, 0x3b, 0x6f, 0x36, 0x7e, 0x01, 0xbe, 0xea, 0x3e, 0x5b,
506 0x07, 0xeb, 0x24, 0x4d, 0xf9, 0x88, 0x29, 0xf7, 0x54, 0x6c, 0x70, 0xb9, 506 0xdb, 0x6e, 0xe9, 0xb6, 0x3c, 0xfb, 0x4f, 0x6c, 0x4a, 0xda, 0xe4, 0x10,
507 0x4a, 0x19, 0x85, 0x1f, 0x4a, 0x6c, 0xd8, 0x24, 0x76, 0x0d, 0xe3, 0x61, 507 0xa4, 0xd1, 0x36, 0x3d, 0xbc, 0xb6, 0xdd, 0x9e, 0x6d, 0x33, 0xca, 0x5e,
508 0xd4, 0xd3, 0xb3, 0x52, 0x56, 0x71, 0x2d, 0xda, 0xa0, 0x5e, 0x15, 0xd3, 508 0x94, 0xd6, 0x7b, 0xa5, 0xfe, 0x17, 0xdc, 0x2b, 0xf0, 0x63, 0xd5, 0x99,
509 0xd2, 0xb1, 0x3e, 0x96, 0x3d, 0x2c, 0x73, 0xee, 0x71, 0x19, 0x98, 0xba, 509 0x11, 0x4b, 0x9e, 0x55, 0xb0, 0x4e, 0xd2, 0xbc, 0x1f, 0x30, 0xef, 0x3d,
510 0x36, 0x6e, 0xd7, 0xeb, 0x1d, 0x87, 0x6f, 0xa5, 0xec, 0xac, 0xfb, 0x41, 510 0x85, 0x5f, 0x9d, 0xed, 0x18, 0x20, 0x7c, 0xdb, 0xe5, 0xd4, 0x69, 0x65,
511 0x21, 0x8f, 0xbb, 0x69, 0x17, 0x72, 0xb6, 0x05, 0xdf, 0xf4, 0xcb, 0x19, 511 0x47, 0x18, 0xb7, 0x5d, 0xa6, 0x7f, 0x4f, 0x5d, 0x3e, 0x69, 0xec, 0x09,
512 0x79, 0x7e, 0x3b, 0x95, 0x14, 0xac, 0xd7, 0x07, 0xe1, 0x7b, 0xda, 0xcf, 512 0x7c, 0x8f, 0xda, 0x71, 0x99, 0x51, 0xd7, 0x9f, 0x90, 0x47, 0x5c, 0xf2,
513 0xe1, 0x9d, 0x71, 0xae, 0x67, 0xe3, 0x12, 0x79, 0x76, 0x58, 0x7a, 0x56, 513 0xee, 0xa4, 0xf8, 0x63, 0x1a, 0x4b, 0x89, 0x89, 0x09, 0x76, 0x78, 0x27,
514 0x88, 0x3f, 0xc8, 0xd3, 0x84, 0x74, 0xaf, 0x10, 0xfb, 0x32, 0x2e, 0x9c, 514 0xe1, 0x9b, 0x29, 0x7b, 0xec, 0x7e, 0x4c, 0xc8, 0xe3, 0x36, 0xda, 0x8f,
515 0x9a, 0xbe, 0x22, 0x8c, 0xb7, 0xa4, 0xfc, 0x0b, 0xf8, 0xed, 0x62, 0xde, 515 0x9c, 0x6d, 0x01, 0x83, 0x3d, 0x99, 0x91, 0xe7, 0x36, 0x50, 0x17, 0xeb,
516 0x3d, 0xf0, 0x9b, 0xbb, 0xcf, 0xea, 0x76, 0xf6, 0xd6, 0x10, 0x00, 0x1f, 516 0xf5, 0x31, 0xc1, 0xfd, 0xb3, 0xb8, 0x67, 0x1c, 0xed, 0xe9, 0xb8, 0x44,
517 0x7c, 0xee, 0x15, 0xfa, 0xd9, 0x4c, 0xe9, 0x77, 0xb3, 0x0c, 0xb2, 0xbd, 517 0x9e, 0xee, 0x97, 0xf6, 0x33, 0xc4, 0x29, 0xe4, 0x69, 0x42, 0xda, 0xce,
518 0x35, 0x62, 0xca, 0xe8, 0x53, 0x73, 0x7c, 0x9e, 0xd9, 0xeb, 0x7b, 0xa0, 518 0x10, 0x2f, 0x33, 0xb6, 0x9c, 0x1a, 0xbf, 0x21, 0x8c, 0xe5, 0xa4, 0xfc,
519 0xf6, 0x18, 0x7d, 0x52, 0x5f, 0x5e, 0xdc, 0x60, 0x0c, 0xfc, 0x55, 0xf8, 519 0x2b, 0xf8, 0x6d, 0x61, 0xde, 0xed, 0xf0, 0xc3, 0xdb, 0x2e, 0xe8, 0x76,
520 0x6f, 0x19, 0x89, 0xac, 0x64, 0x20, 0x87, 0x3e, 0x6c, 0x29, 0x71, 0x1c, 520 0xf6, 0xb9, 0x3e, 0x00, 0xc3, 0x98, 0xd8, 0xf0, 0x59, 0xec, 0x0b, 0x2c,
521 0xed, 0x17, 0xf2, 0x61, 0x73, 0x36, 0x9e, 0x51, 0x31, 0x87, 0x92, 0x93, 521 0xbb, 0x50, 0xf2, 0x1d, 0x48, 0x3a, 0x37, 0x60, 0xde, 0x41, 0x37, 0x5e,
522 0x85, 0xcc, 0xd5, 0x3f, 0x63, 0x97, 0xdb, 0x6c, 0x54, 0xd9, 0xd8, 0xa8, 522 0xe0, 0xf8, 0xb0, 0x8f, 0xbe, 0xce, 0x17, 0x1d, 0x18, 0xf2, 0xe5, 0xd2,
523 0xb2, 0xb1, 0x51, 0xe5, 0x66, 0xb8, 0x3f, 0x38, 0xc6, 0x71, 0xd8, 0xd5, 523 0x1a, 0x65, 0x93, 0x71, 0x74, 0x62, 0x97, 0x57, 0xc5, 0x5e, 0xca, 0x48,
524 0x2e, 0x79, 0x2a, 0x4e, 0x59, 0xd1, 0xb2, 0x17, 0xb1, 0xc7, 0x94, 0xac, 524 0xe4, 0x4c, 0x06, 0x72, 0xe8, 0xc3, 0xee, 0x12, 0xf3, 0xd1, 0xd6, 0xe1,
525 0xce, 0xd0, 0xde, 0x3e, 0xe3, 0xee, 0x83, 0xaf, 0x55, 0x52, 0x7b, 0xe3, 525 0x39, 0xf0, 0x56, 0xfd, 0x29, 0xce, 0xe9, 0xaa, 0xd8, 0xf5, 0x5f, 0x65,
526 0x99, 0x50, 0xce, 0x78, 0xe7, 0x33, 0x90, 0x1a, 0xb0, 0x4c, 0xd9, 0xb3, 526 0xc3, 0xc2, 0x7d, 0xc1, 0x31, 0x4e, 0xc2, 0xfe, 0x46, 0xe5, 0x73, 0x71,
527 0x64, 0xc9, 0x3b, 0xae, 0xb0, 0xde, 0xc3, 0xe8, 0xe3, 0x49, 0xd3, 0xc7, 527 0xca, 0x8a, 0x96, 0xbd, 0xb4, 0x3d, 0xa4, 0x64, 0xb5, 0x48, 0xbb, 0xfc,
528 0x92, 0x8c, 0x19, 0x79, 0xe7, 0xda, 0x44, 0xd5, 0x79, 0xc5, 0x43, 0xfe, 528 0xd4, 0xed, 0x7b, 0xe0, 0xa7, 0x9d, 0x2e, 0x6f, 0xcb, 0x18, 0xf3, 0x42,
529 0xef, 0xc9, 0xc0, 0x20, 0xd7, 0x93, 0xf2, 0x4f, 0x7c, 0xc1, 0xf5, 0x60, 529 0x03, 0xa9, 0x02, 0xef, 0xcc, 0x7b, 0x96, 0x2c, 0x78, 0x27, 0x15, 0x1e,
530 0x8c, 0xff, 0x6d, 0x63, 0xa9, 0xea, 0x0e, 0x5f, 0xa1, 0x42, 0x5b, 0xb2, 530 0x7c, 0x14, 0xed, 0x4f, 0x98, 0xf6, 0x0b, 0x32, 0x64, 0x64, 0x5d, 0xc5,
531 0x1f, 0xf2, 0x9b, 0x81, 0xff, 0x1d, 0xc6, 0x53, 0xd5, 0xbe, 0x4a, 0xd8, 531 0x11, 0xa0, 0xc7, 0xb8, 0x66, 0xbc, 0xff, 0x2d, 0xf1, 0x7b, 0xb9, 0x9e,
532 0x36, 0xec, 0xda, 0xd8, 0xd8, 0x78, 0x51, 0x8e, 0x4b, 0x19, 0x7e, 0x2b, 532 0x27, 0x65, 0x60, 0x4c, 0xe3, 0x90, 0x92, 0x4d, 0x1c, 0xf2, 0xae, 0x71,
533 0x69, 0x58, 0x82, 0x1d, 0xdb, 0xf0, 0xff, 0x2e, 0xf8, 0x64, 0x3c, 0x55, 533 0x5a, 0x95, 0xcb, 0x57, 0xa8, 0xd0, 0xce, 0xec, 0x85, 0xfc, 0xc2, 0x27,
534 0x9a, 0x97, 0xce, 0x18, 0x27, 0x7d, 0xf1, 0xb7, 0x8b, 0x73, 0x1e, 0x51, 534 0xda, 0x08, 0x63, 0xb5, 0x6a, 0x5f, 0x25, 0x06, 0x6c, 0x4b, 0xbc, 0xa1,
535 0xfa, 0xf1, 0x5a, 0x2c, 0x15, 0xc6, 0x38, 0xe7, 0x3a, 0x62, 0x9c, 0xfa, 535 0xa1, 0xe1, 0x12, 0xf0, 0xc9, 0x3c, 0x7c, 0x5e, 0xd2, 0xb1, 0x00, 0x3b,
536 0xec, 0xac, 0x27, 0x4b, 0xbd, 0x7e, 0xca, 0xfa, 0x71, 0x26, 0x22, 0x0d, 536 0xb7, 0xe6, 0xff, 0x4b, 0x70, 0x22, 0x9e, 0x3a, 0x3d, 0xf3, 0xae, 0xf1,
537 0x60, 0xca, 0xfb, 0x7c, 0x62, 0xa4, 0x92, 0xf5, 0x7a, 0x45, 0xd4, 0x7b, 537 0xfb, 0x30, 0x6e, 0xdf, 0x7c, 0x9e, 0xb2, 0x69, 0xfd, 0x61, 0xe3, 0x88,
538 0xc1, 0x8f, 0xe8, 0x58, 0xbb, 0x0b, 0xdb, 0xb2, 0xed, 0x98, 0xb3, 0x22, 538 0xd2, 0x91, 0x37, 0xe3, 0xae, 0x30, 0x7e, 0x3f, 0x7d, 0x53, 0x1c, 0xb5,
539 0x07, 0x79, 0xb6, 0xf2, 0x77, 0x8b, 0x4a, 0x27, 0x27, 0xfa, 0x24, 0x46, 539 0xd4, 0x08, 0x73, 0xf0, 0x42, 0x3d, 0x7f, 0x1a, 0xba, 0x3a, 0x22, 0x37,
540 0x3d, 0x75, 0x2f, 0xde, 0x79, 0x5e, 0x71, 0xa4, 0x23, 0x7f, 0x67, 0x80, 540 0x80, 0x41, 0x27, 0xc0, 0xbb, 0x73, 0x6b, 0x65, 0xeb, 0x4a, 0x45, 0xd4,
541 0x7b, 0xac, 0x0c, 0x3c, 0xb6, 0xe4, 0x69, 0x7e, 0x39, 0xe0, 0xf1, 0x0c, 541 0x7d, 0xc1, 0x67, 0x4e, 0xde, 0x47, 0xc0, 0x3b, 0xd8, 0x98, 0x0d, 0xc7,
542 0x30, 0xce, 0x95, 0x26, 0x71, 0x6d, 0xcc, 0xe0, 0x5a, 0xe2, 0x26, 0xac, 542 0x9c, 0x29, 0x39, 0x78, 0x66, 0x2b, 0x9f, 0xb9, 0xa4, 0x74, 0xf3, 0xe1,
543 0xd1, 0xf6, 0x28, 0xca, 0x88, 0x9d, 0xe2, 0xca, 0xaf, 0x53, 0x58, 0xca, 543 0x2e, 0x9e, 0xb9, 0x5c, 0x5a, 0xfe, 0x28, 0xee, 0x79, 0xf6, 0x71, 0xa4,
544 0x2f, 0x18, 0x3b, 0x41, 0x99, 0xa2, 0x3c, 0x11, 0x93, 0x69, 0x99, 0x5a, 544 0xe5, 0xf9, 0x66, 0x4f, 0x54, 0x63, 0x37, 0xf0, 0x5d, 0xf3, 0xcd, 0x01,
545 0xa8, 0xb8, 0x1d, 0xf2, 0xe4, 0xfe, 0x23, 0xe5, 0xe9, 0xa6, 0x3e, 0x9e, 545 0xbf, 0x8b, 0x8c, 0xe7, 0x35, 0x88, 0x83, 0x3b, 0x0d, 0x0e, 0x26, 0xce,
546 0xf7, 0xbc, 0x84, 0xfd, 0x79, 0x12, 0xf6, 0x74, 0xa3, 0xb6, 0x4f, 0x76, 546 0xc2, 0x7a, 0x6d, 0x30, 0x0e, 0x43, 0xac, 0x15, 0x57, 0x7e, 0xa1, 0xc2,
547 0x6b, 0xa3, 0xc0, 0xc5, 0xcc, 0xe3, 0xbe, 0x4c, 0xc8, 0xfd, 0x95, 0x59, 547 0x5e, 0xfe, 0x31, 0x93, 0x7f, 0x71, 0xab, 0x5c, 0xcd, 0x56, 0x42, 0x3c,
548 0x39, 0x5c, 0x8b, 0xca, 0xc5, 0x9a, 0x7d, 0x4f, 0x8f, 0x30, 0x46, 0x4d, 548 0xd7, 0x2c, 0x57, 0xee, 0x6f, 0x20, 0x57, 0x13, 0x5d, 0x3a, 0xdf, 0x81,
549 0xcc, 0xf1, 0x0d, 0xa5, 0xd7, 0x7e, 0xe2, 0x5f, 0x6d, 0xbf, 0x84, 0xf6, 549 0x36, 0xcd, 0x92, 0x37, 0xaa, 0x7b, 0x64, 0xab, 0xfa, 0x20, 0x70, 0xb4,
550 0x0d, 0xb4, 0x5f, 0xa8, 0xdd, 0x28, 0x45, 0xd5, 0x7e, 0xfd, 0xba, 0x31, 550 0xca, 0xfb, 0x90, 0x2d, 0xac, 0xc5, 0x83, 0x95, 0x49, 0x99, 0xa8, 0xc6,
551 0xae, 0xd6, 0xe9, 0x33, 0xf6, 0x33, 0x3c, 0x97, 0xa4, 0x6d, 0xee, 0xc2, 551 0xe4, 0x5a, 0xd5, 0x7e, 0xa0, 0x5d, 0x18, 0x07, 0x27, 0x36, 0xf9, 0x1b,
552 0xbc, 0xe1, 0x27, 0x65, 0x90, 0xd6, 0x79, 0x36, 0x49, 0xdb, 0xfe, 0x47, 552 0xa5, 0xdf, 0x7e, 0xe0, 0xef, 0xb4, 0xe7, 0xb9, 0xca, 0x0d, 0xb4, 0x9f,
553 0xae, 0x4e, 0x13, 0x6d, 0x76, 0x21, 0xd9, 0x66, 0x17, 0xde, 0x68, 0xbb, 553 0xad, 0xde, 0x2b, 0x25, 0xd5, 0xbe, 0x7e, 0xcb, 0x18, 0x51, 0x33, 0x46,
554 0x4b, 0xa9, 0xef, 0x65, 0xbf, 0x9c, 0x01, 0xf6, 0xab, 0x0d, 0xb5, 0xdd, 554 0xbd, 0x7a, 0x97, 0x89, 0xdf, 0x95, 0xe5, 0x12, 0xb0, 0xaf, 0x7d, 0x96,
555 0xa9, 0x48, 0x95, 0x68, 0x93, 0x18, 0x0b, 0xdb, 0xac, 0x84, 0xba, 0x3a, 555 0xf3, 0xbd, 0xc3, 0xe4, 0x77, 0xc5, 0x9a, 0xfc, 0x91, 0xa8, 0xf1, 0x47,
556 0x37, 0xc0, 0x38, 0xfe, 0xb2, 0x4f, 0xbe, 0x4b, 0x32, 0x92, 0xa5, 0xae, 556 0x7e, 0x06, 0x3d, 0xfe, 0x94, 0x44, 0xbd, 0xb0, 0x2f, 0xe6, 0x6a, 0x27,
557 0xf7, 0xa3, 0xbb, 0xc0, 0x68, 0x0d, 0x75, 0x4e, 0x1d, 0xc1, 0x0f, 0xb6, 557 0x4c, 0x6e, 0xc7, 0x5e, 0xf4, 0x75, 0x10, 0xef, 0xee, 0xc3, 0xef, 0x49,
558 0xd0, 0xb1, 0xc4, 0xf5, 0x98, 0x57, 0xd2, 0x58, 0xd7, 0x85, 0xde, 0xb4, 558 0xd4, 0xa3, 0xbd, 0xe2, 0xd9, 0x28, 0x31, 0x02, 0xcf, 0xeb, 0x7a, 0x51,
559 0x55, 0x9d, 0x64, 0xde, 0xbf, 0xc9, 0xbc, 0x43, 0xbf, 0x55, 0xde, 0x3b, 559 0xaf, 0x03, 0x58, 0x72, 0xbf, 0x79, 0x16, 0xf6, 0x11, 0xd6, 0x0d, 0xef,
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782 0x77, 0x4d, 0x79, 0x88, 0x45, 0x87, 0xb1, 0x5f, 0x1f, 0x95, 0xc6, 0x5a, 782 0x47, 0x58, 0x87, 0x7c, 0x0d, 0xe3, 0x9a, 0xea, 0x5b, 0xcb, 0xa4, 0x58,
783 0x3a, 0xf1, 0x98, 0x84, 0xfd, 0x06, 0x87, 0x78, 0x8e, 0x30, 0x93, 0x99, 783 0x96, 0xb4, 0x79, 0x9c, 0xfb, 0x54, 0x8f, 0xc6, 0x40, 0x6c, 0x97, 0x76,
784 0x70, 0x97, 0x14, 0x3d, 0xa9, 0x04, 0xef, 0xdd, 0x9e, 0xc7, 0x78, 0x8d, 784 0x0f, 0xab, 0xfe, 0x78, 0xb6, 0xc7, 0xf3, 0xaf, 0xb0, 0x1f, 0xe6, 0x43,
785 0x66, 0x67, 0xbc, 0x21, 0x95, 0xdb, 0x91, 0xb4, 0xaf, 0xd7, 0x66, 0x4c, 785 0x31, 0xe7, 0x8a, 0xba, 0xaf, 0x99, 0x06, 0x6d, 0xff, 0xdf, 0x50, 0xb1,
786 0x76, 0xb0, 0x36, 0x5f, 0x32, 0x6b, 0xf3, 0x41, 0xf4, 0xed, 0xad, 0x4c, 786 0xf4, 0x71, 0xd4, 0xa7, 0x8d, 0x86, 0xbc, 0xd4, 0x12, 0xdb, 0xdf, 0x7c,
787 0x4a, 0x7a, 0x25, 0x9d, 0x3c, 0x25, 0x3c, 0x9b, 0x3b, 0xc0, 0xb8, 0x95, 787 0x68, 0x5e, 0xf2, 0xfa, 0x99, 0xed, 0x6f, 0x32, 0xec, 0xbb, 0x5d, 0xf3,
788 0x75, 0x7f, 0x26, 0x89, 0xf9, 0xa6, 0x30, 0x5f, 0xa4, 0x4d, 0x3e, 0x4f, 788 0x3e, 0xc4, 0xa5, 0xfd, 0xd8, 0xaf, 0x8f, 0x49, 0x7d, 0x25, 0x9d, 0xf8,
789 0xc0, 0x1f, 0xdf, 0xc7, 0xbd, 0x7d, 0x88, 0x3a, 0x93, 0xbc, 0x98, 0x51, 789 0xb4, 0x84, 0xfd, 0x06, 0x87, 0x78, 0xde, 0x51, 0xcc, 0x8c, 0xb8, 0x0b,
790 0x65, 0x8f, 0x9a, 0xbb, 0x94, 0xdf, 0xe3, 0xfa, 0xa8, 0xb8, 0xdf, 0xe5, 790 0x8a, 0x9e, 0x54, 0x82, 0x39, 0xc8, 0x97, 0x31, 0x5e, 0xbd, 0xd1, 0x1a,
791 0x26, 0xcf, 0xeb, 0x34, 0x7d, 0x05, 0xd0, 0xb7, 0xa8, 0xe9, 0x4b, 0xce, 791 0x7b, 0x48, 0xe5, 0x36, 0x25, 0xed, 0xeb, 0xb5, 0x19, 0x92, 0x4d, 0xac,
792 0xb7, 0xf0, 0x6a, 0x2a, 0x71, 0x42, 0x88, 0x97, 0x88, 0x5f, 0x88, 0xe5, 792 0xcd, 0x9f, 0x9b, 0xb5, 0xf9, 0x18, 0xfa, 0xf6, 0xce, 0x8c, 0x4a, 0xfa,
793 0x6f, 0x19, 0xd4, 0xdf, 0x7e, 0xc0, 0x77, 0xbd, 0x3d, 0xd7, 0x9a, 0x7b, 793 0x4c, 0x3a, 0x79, 0x5a, 0x78, 0x96, 0xb8, 0x8f, 0x31, 0x2c, 0xeb, 0xc1,
794 0x37, 0xea, 0x5e, 0x80, 0xee, 0xa7, 0xbc, 0x1c, 0x91, 0x0f, 0x48, 0xee, 794 0x4c, 0x12, 0xf3, 0x4d, 0x61, 0xbe, 0x28, 0x1b, 0xbc, 0x1e, 0x81, 0x6f,
795 0x91, 0x54, 0x32, 0x67, 0x79, 0x06, 0x03, 0x22, 0xad, 0xf3, 0x99, 0x3a, 795 0xbe, 0x87, 0x7b, 0xfb, 0x10, 0x75, 0x26, 0x79, 0x51, 0x54, 0xef, 0x80,
796 0xd7, 0x33, 0xd8, 0x82, 0x6b, 0x93, 0xc1, 0x58, 0xfa, 0x3b, 0x92, 0x5d, 796 0x4f, 0x9e, 0x26, 0x4d, 0x00, 0xca, 0x9d, 0x29, 0x15, 0x07, 0xbc, 0xde,
797 0xcc, 0x2d, 0xaf, 0x64, 0xed, 0xf7, 0xb1, 0x87, 0xf4, 0xff, 0xb3, 0x38, 797 0xe0, 0xf9, 0xa2, 0xa6, 0xaf, 0x00, 0xfa, 0xe6, 0x34, 0x7d, 0xc9, 0x99,
798 0x0f, 0x3e, 0x96, 0xc1, 0xc7, 0xc7, 0xaf, 0xc3, 0x60, 0x5d, 0x2d, 0x0c, 798 0x6d, 0xec, 0x9a, 0x4a, 0x9c, 0x12, 0xe2, 0x25, 0xe2, 0x17, 0xe2, 0xfa,
799 0xb6, 0xab, 0xc6, 0xb3, 0x40, 0x53, 0xc1, 0x25, 0xfe, 0x2a, 0xb7, 0x64, 799 0x47, 0x7a, 0xc3, 0x6f, 0x5a, 0xf2, 0x77, 0xe7, 0xb6, 0xe7, 0xde, 0x86,
800 0x85, 0x34, 0x4d, 0xf2, 0x7f, 0xd2, 0xc8, 0xcb, 0x19, 0xae, 0x07, 0x30, 800 0xba, 0x57, 0x32, 0x2a, 0xbf, 0xd9, 0x3d, 0x22, 0x1f, 0x91, 0xdc, 0xa7,
801 0x18, 0xfa, 0xdb, 0xb8, 0x2a, 0x4b, 0x98, 0xbf, 0x92, 0x5f, 0xc8, 0x6e, 801 0x52, 0xc9, 0x9c, 0xe5, 0x19, 0x0c, 0x88, 0xb2, 0xc6, 0x6b, 0xea, 0x5c,
802 0xca, 0x75, 0x2c, 0xae, 0x05, 0xfb, 0x13, 0xeb, 0x22, 0x68, 0xd9, 0x55, 802 0xcf, 0x60, 0x0b, 0xae, 0x4d, 0x06, 0x63, 0x29, 0xde, 0xc2, 0x67, 0xea,
803 0x72, 0xa0, 0x65, 0x60, 0xb7, 0x1e, 0x7b, 0x07, 0x19, 0xe0, 0x3c, 0x29, 803 0x87, 0xcc, 0x53, 0xd6, 0x7e, 0x07, 0x7b, 0x48, 0xff, 0x9f, 0x8e, 0xcb,
804 0x7f, 0xa1, 0xec, 0xb5, 0xbe, 0x39, 0x87, 0x4f, 0x5b, 0x92, 0xdb, 0xee, 804 0xe0, 0xe3, 0x3c, 0xf8, 0x78, 0xfc, 0x16, 0x0c, 0x16, 0xdd, 0xc6, 0x60,
805 0xc8, 0x4a, 0x7e, 0x85, 0x67, 0x4b, 0x62, 0x4d, 0xdc, 0x41, 0x99, 0x24, 805 0x5b, 0x6a, 0xbc, 0x7b, 0x41, 0x53, 0xc1, 0x25, 0xfe, 0x9a, 0xdf, 0x96,
806 0x4e, 0x00, 0x86, 0x4c, 0x90, 0xc7, 0x1a, 0x0f, 0xce, 0x3f, 0xb7, 0x1f, 806 0x15, 0xd2, 0x34, 0xca, 0xff, 0xb5, 0x23, 0x57, 0x33, 0x5c, 0x0f, 0x60,
807 0xbf, 0x73, 0x03, 0xbc, 0x5b, 0x92, 0xdf, 0xa2, 0xbe, 0x12, 0xeb, 0xd6, 807 0x30, 0xf4, 0xb7, 0xb6, 0x23, 0x4b, 0x98, 0xbf, 0x92, 0x5f, 0xc8, 0x6e,
808 0x3b, 0xb4, 0x4f, 0x78, 0x25, 0x0e, 0x9e, 0xa3, 0x7c, 0xe4, 0xcb, 0xdd, 808 0xca, 0x75, 0x2c, 0xae, 0x05, 0xfb, 0x13, 0xeb, 0x1a, 0x68, 0xd9, 0x52,
809 0xd0, 0x57, 0x8e, 0x99, 0x37, 0xdf, 0xc9, 0x57, 0xa4, 0xcf, 0x71, 0x5c, 809 0x72, 0xa0, 0x65, 0x60, 0xab, 0xd6, 0xf9, 0x1e, 0x32, 0xc0, 0x79, 0x52,
810 0xed, 0x5f, 0xe8, 0x38, 0x20, 0xf7, 0x45, 0x49, 0x16, 0xa1, 0x0f, 0x16, 810 0xfe, 0x42, 0xd9, 0xdb, 0xc9, 0xa7, 0xe8, 0x00, 0x4f, 0x3e, 0x78, 0x4f,
811 0x32, 0x31, 0x39, 0x5c, 0x8b, 0xcb, 0x91, 0xca, 0xb4, 0x7c, 0xb1, 0xd2, 811 0x56, 0xf2, 0x67, 0x78, 0x16, 0x26, 0xd6, 0xc8, 0x3d, 0x94, 0x49, 0xe2,
812 0xa7, 0x70, 0xc3, 0x9f, 0xfb, 0xe9, 0xc4, 0xb8, 0x15, 0xc8, 0xfd, 0xc0, 812 0x04, 0x60, 0xc8, 0x04, 0x79, 0xac, 0xf1, 0xe0, 0xcc, 0xb3, 0x7b, 0xf1,
813 0x3f, 0xf3, 0xc3, 0xdd, 0xf2, 0xfa, 0xa4, 0xa5, 0xf4, 0xde, 0x15, 0x7e, 813 0x7b, 0xb3, 0x87, 0x39, 0x33, 0xf9, 0x73, 0xd4, 0x57, 0x62, 0xdd, 0x79,
814 0x18, 0xed, 0xf2, 0x0e, 0x27, 0xe7, 0x03, 0xbd, 0x6f, 0xc1, 0x17, 0xb0, 814 0x8f, 0xf6, 0x0f, 0x6f, 0xc4, 0xc1, 0x73, 0xbc, 0x1f, 0x78, 0xb2, 0x0d,
815 0x78, 0x6f, 0xaf, 0x4f, 0x1e, 0xf0, 0x91, 0xde, 0xe8, 0xab, 0xef, 0x62, 815 0xfa, 0xca, 0x31, 0xf3, 0xe6, 0x3d, 0xf9, 0x8a, 0xf2, 0xd9, 0x29, 0xa3,
816 0xcd, 0x77, 0x5c, 0x46, 0x8f, 0x9c, 0x33, 0x63, 0x1f, 0x31, 0x69, 0x6a, 816 0x03, 0xa8, 0x47, 0xc4, 0xec, 0x8b, 0xb2, 0xcc, 0x31, 0x46, 0x9f, 0xe9,
817 0xb0, 0x8d, 0x16, 0x6b, 0x31, 0x13, 0x51, 0xf3, 0x2b, 0xd7, 0xa9, 0xdf, 817 0x94, 0x09, 0xe8, 0xb5, 0x23, 0x95, 0x71, 0xf9, 0x72, 0xa5, 0x4b, 0xe1,
818 0xd8, 0x06, 0xfa, 0x04, 0x7b, 0xb7, 0x0b, 0x7c, 0xd9, 0x80, 0x7e, 0x29, 818 0x86, 0xbf, 0xf6, 0xd3, 0x89, 0x61, 0x2b, 0x90, 0x07, 0x81, 0x7f, 0x66,
819 0xd6, 0xc4, 0xda, 0xca, 0x00, 0x51, 0x7b, 0x1a, 0x7f, 0x16, 0x21, 0x5f, 819 0xfa, 0xdb, 0xe4, 0xcd, 0x51, 0x9d, 0xfb, 0x7b, 0x83, 0xc9, 0x8d, 0x2e,
820 0x0b, 0x35, 0xea, 0xbf, 0x23, 0x90, 0x05, 0xda, 0x6f, 0x87, 0xdf, 0xdc, 820 0xf3, 0x55, 0x39, 0x1f, 0xe8, 0x7d, 0x0b, 0xbe, 0x80, 0xd5, 0x2e, 0x33,
821 0x00, 0x43, 0x98, 0x3b, 0x1f, 0x31, 0xc6, 0x40, 0xda, 0x75, 0x58, 0xf8, 821 0xf1, 0x2e, 0xf9, 0xb8, 0x8f, 0xf2, 0x36, 0x5f, 0x7d, 0x63, 0x9c, 0x8b,
822 0x3f, 0x67, 0x3e, 0x3e, 0x28, 0xfd, 0x25, 0xac, 0x4b, 0x88, 0xb9, 0xc1, 822 0x37, 0xeb, 0x91, 0x37, 0xcd, 0xd8, 0x5f, 0x34, 0xe5, 0xbf, 0xe9, 0x6d,
823 0x53, 0x8c, 0x99, 0x57, 0xeb, 0x14, 0xae, 0x09, 0x75, 0x4f, 0x88, 0x37, 823 0xa2, 0xc5, 0x9a, 0xcb, 0x44, 0xd4, 0xfc, 0xe6, 0x6b, 0xd4, 0x6f, 0x6c,
824 0xda, 0xfd, 0x23, 0xee, 0x59, 0xda, 0x0b, 0x29, 0x45, 0x81, 0x69, 0x7b, 824 0x03, 0x7d, 0xd2, 0xe0, 0x39, 0x51, 0x59, 0xd6, 0xa0, 0x5f, 0x4a, 0x55,
825 0x57, 0x60, 0xbb, 0x6b, 0x59, 0xc8, 0x0a, 0xef, 0xe1, 0x4f, 0x4b, 0x19, 825 0xb1, 0xce, 0x65, 0x80, 0xa8, 0x3d, 0x8d, 0x3f, 0x4b, 0x90, 0xaf, 0xd9,
826 0xd8, 0xed, 0xe3, 0xfe, 0xe7, 0xc4, 0x7e, 0xf6, 0xa0, 0x6c, 0xd4, 0x7a, 826 0xaa, 0x8a, 0x59, 0xaa, 0xbc, 0xed, 0x59, 0x60, 0x5d, 0xf8, 0xc4, 0xc0,
827 0xc1, 0x0f, 0xda, 0x85, 0x2e, 0xe5, 0x53, 0x5f, 0x39, 0x4a, 0x7b, 0x47, 827 0x10, 0x26, 0x7f, 0xa5, 0x93, 0xf1, 0x90, 0x66, 0x1d, 0x16, 0xfe, 0x2f,
828 0x5b, 0xa2, 0xd7, 0x62, 0xb7, 0x0e, 0x27, 0x38, 0xa6, 0xf3, 0x76, 0xea, 828 0x9d, 0xff, 0xd4, 0x2b, 0xdd, 0x65, 0xac, 0x4b, 0x88, 0xb9, 0xc1, 0x53,
829 0xa1, 0x2d, 0xe4, 0xf7, 0x34, 0x5d, 0xc6, 0x2e, 0xc7, 0xa0, 0xbb, 0xd7, 829 0x8c, 0x99, 0x57, 0xeb, 0x14, 0xae, 0x09, 0x75, 0x4f, 0x73, 0xbe, 0x78,
830 0xa5, 0xa1, 0xfc, 0x73, 0xce, 0x9f, 0x36, 0xa8, 0x8b, 0xf7, 0xc7, 0xac, 830 0x88, 0x39, 0xb8, 0x67, 0x69, 0x2f, 0xa4, 0x1c, 0x03, 0xa6, 0xed, 0x38,
831 0x86, 0xc7, 0xb9, 0xb7, 0xdb, 0x20, 0x8d, 0x3b, 0xdc, 0x3b, 0x39, 0x1e, 831 0x03, 0xdb, 0x5d, 0xcd, 0x42, 0x56, 0xc6, 0x55, 0xde, 0xe7, 0x3c, 0xb0,
832 0xef, 0x26, 0x70, 0x8e, 0x71, 0xe9, 0x3a, 0xf3, 0xa8, 0xd8, 0xf0, 0x5b, 832 0xdb, 0x1f, 0xf8, 0x7f, 0x2a, 0xf6, 0xd3, 0x07, 0x64, 0xad, 0xda, 0x01,
833 0x22, 0xab, 0xc4, 0x7a, 0xd7, 0xfa, 0x2e, 0x91, 0x73, 0x51, 0xf3, 0xfd, 833 0x7e, 0xd0, 0x2e, 0x44, 0x95, 0x7f, 0x7d, 0xe3, 0x28, 0xed, 0x1d, 0x6d,
834 0xf0, 0xa8, 0xc6, 0x32, 0x19, 0xa4, 0x8d, 0xf0, 0x9b, 0x62, 0xfe, 0xda, 834 0x89, 0x5e, 0x8b, 0xad, 0xda, 0xf7, 0x7a, 0xf5, 0xb7, 0x33, 0x7b, 0x65,
835 0xed, 0x66, 0xe8, 0x5b, 0xec, 0x69, 0x4b, 0xf1, 0xf7, 0x7f, 0x00, 0xb6, 835 0xb3, 0x16, 0xda, 0x42, 0xf8, 0x87, 0xd5, 0xa8, 0xb1, 0xcb, 0x9d, 0xd0,
836 0x9d, 0x3c, 0x32, 0x44, 0x4b, 0x00, 0x00, 0x00 }; 836 0xdd, 0xdf, 0x8f, 0xd6, 0x95, 0xaf, 0xce, 0xf9, 0xd3, 0x06, 0x45, 0x99,
837 0x17, 0xd7, 0x59, 0xf7, 0x38, 0xf7, 0x66, 0x1b, 0xa4, 0x71, 0x87, 0x7b,
838 0x90, 0xe3, 0x31, 0x87, 0x82, 0x73, 0x8c, 0x4b, 0xf4, 0xfc, 0x63, 0x62,
839 0xc3, 0x6f, 0x89, 0x2c, 0x11, 0xeb, 0xdd, 0xec, 0xbb, 0x44, 0x2e, 0xba,
840 0xe6, 0x5b, 0xec, 0x41, 0x8d, 0x65, 0x32, 0x28, 0xeb, 0xe1, 0xf7, 0xd9,
841 0xfc, 0x35, 0xdb, 0xcd, 0xd0, 0xb7, 0xd8, 0xd5, 0x96, 0xe2, 0xef, 0xff,
842 0x01, 0x37, 0x64, 0x26, 0x2b, 0x1c, 0x4c, 0x00, 0x00, 0x00 };
837 843
838static const u32 bnx2_COM_b09FwData[(0x0/4) + 1] = { 0x0 }; 844static const u32 bnx2_COM_b09FwData[(0x0/4) + 1] = { 0x0 };
839static const u32 bnx2_COM_b09FwRodata[(0x30/4) + 1] = { 845static const u32 bnx2_COM_b09FwRodata[(0x30/4) + 1] = {
840 0x80080100, 0x80080080, 0x80080000, 0x80080240, 0x08000e94, 0x08000eec, 846 0x80080100, 0x80080080, 0x80080000, 0x80080240, 0x08000e20, 0x08000e78,
841 0x08000f30, 0x08000fc4, 0x08001008, 0x80080100, 0x80080080, 0x80080000, 847 0x08000ebc, 0x08000f50, 0x08000f94, 0x80080100, 0x80080080, 0x80080000,
842 0x00000000 }; 848 0x00000000 };
843 849
844static struct fw_info bnx2_com_fw_09 = { 850static struct fw_info bnx2_com_fw_09 = {
845 /* Firmware version: 4.0.5 */ 851 /* Firmware version: 4.4.23 */
846 .ver_major = 0x4, 852 .ver_major = 0x4,
847 .ver_minor = 0x0, 853 .ver_minor = 0x4,
848 .ver_fix = 0x5, 854 .ver_fix = 0x17,
849 855
850 .start_addr = 0x080000f8, 856 .start_addr = 0x080000f8,
851 857
852 .text_addr = 0x08000000, 858 .text_addr = 0x08000000,
853 .text_len = 0x4b40, 859 .text_len = 0x4c18,
854 .text_index = 0x0, 860 .text_index = 0x0,
855 .gz_text = bnx2_COM_b09FwText, 861 .gz_text = bnx2_COM_b09FwText,
856 .gz_text_len = sizeof(bnx2_COM_b09FwText), 862 .gz_text_len = sizeof(bnx2_COM_b09FwText),
@@ -860,1202 +866,1210 @@ static struct fw_info bnx2_com_fw_09 = {
860 .data_index = 0x0, 866 .data_index = 0x0,
861 .data = bnx2_COM_b09FwData, 867 .data = bnx2_COM_b09FwData,
862 868
863 .sbss_addr = 0x08004ba0, 869 .sbss_addr = 0x08004c60,
864 .sbss_len = 0x38, 870 .sbss_len = 0x38,
865 .sbss_index = 0x0, 871 .sbss_index = 0x0,
866 872
867 .bss_addr = 0x08004bd8, 873 .bss_addr = 0x08004c98,
868 .bss_len = 0xbc, 874 .bss_len = 0xbc,
869 .bss_index = 0x0, 875 .bss_index = 0x0,
870 876
871 .rodata_addr = 0x08004b40, 877 .rodata_addr = 0x08004c18,
872 .rodata_len = 0x30, 878 .rodata_len = 0x30,
873 .rodata_index = 0x0, 879 .rodata_index = 0x0,
874 .rodata = bnx2_COM_b09FwRodata, 880 .rodata = bnx2_COM_b09FwRodata,
875}; 881};
876 882
877static u8 bnx2_CP_b09FwText[] = { 883static u8 bnx2_CP_b09FwText[] = {
878 0xad, 0xbc, 0x0f, 0x74, 0x53, 0xd7, 0x95, 0x2e, 0xfe, 0xdd, 0x2b, 0xc9, 884 0xad, 0xbc, 0x0b, 0x74, 0x1c, 0xd5, 0x95, 0x2e, 0xfc, 0x55, 0x75, 0xb7,
879 0x96, 0x6d, 0xd9, 0x96, 0x8d, 0x70, 0xe4, 0xc4, 0x0d, 0x52, 0x7c, 0x05, 885 0xd4, 0x92, 0xda, 0x52, 0x4b, 0x6e, 0xcb, 0x6d, 0xd0, 0xe0, 0x6a, 0xab,
880 0x0a, 0x36, 0xe9, 0x95, 0x11, 0x89, 0xd3, 0x77, 0x13, 0x54, 0x70, 0x82, 886 0xda, 0x6a, 0x2c, 0x01, 0xd5, 0xb2, 0x0c, 0x4d, 0xa6, 0xc0, 0x1d, 0x5b,
881 0x49, 0x68, 0xe2, 0x10, 0xa6, 0x75, 0x67, 0x98, 0xa9, 0x1e, 0x21, 0x09, 887 0x80, 0x0c, 0x26, 0x11, 0xc6, 0xb9, 0x23, 0xe6, 0x7a, 0xfe, 0xf4, 0x18,
882 0x49, 0x99, 0x3c, 0xb7, 0xaf, 0xed, 0x23, 0xf9, 0xd1, 0xf1, 0xad, 0xcd, 888 0x03, 0x86, 0x90, 0x5c, 0x33, 0x93, 0x9b, 0x71, 0xb8, 0x9e, 0xeb, 0x8a,
883 0x1f, 0x03, 0x92, 0x25, 0x1b, 0xf3, 0x27, 0x6f, 0xba, 0x5e, 0x84, 0x31, 889 0xe4, 0x87, 0xc0, 0xa5, 0xee, 0x96, 0x90, 0x1f, 0xac, 0x35, 0xeb, 0xa7,
884 0x18, 0x12, 0xd9, 0x4e, 0xda, 0x4c, 0x87, 0xbc, 0xd5, 0x79, 0x78, 0x0c, 890 0x2d, 0xcb, 0x92, 0x21, 0xad, 0x16, 0x49, 0x98, 0x19, 0xe7, 0xe6, 0x81,
885 0x24, 0x90, 0x34, 0x7f, 0x9a, 0xb4, 0xab, 0x69, 0xa7, 0x6f, 0xe2, 0x12, 891 0xc6, 0xd8, 0x60, 0x93, 0xf0, 0xc8, 0x6b, 0xfd, 0x4c, 0xfe, 0xb9, 0x7f,
886 0x92, 0x92, 0x7f, 0x94, 0x34, 0x9d, 0x0e, 0x74, 0x86, 0xde, 0xdf, 0xb7, 892 0x3c, 0xb6, 0x79, 0x83, 0xe3, 0x3c, 0x47, 0x9e, 0xc1, 0xa9, 0xff, 0xdb,
887 0xaf, 0x24, 0x30, 0x94, 0xa4, 0xed, 0x5a, 0xcf, 0x6b, 0x69, 0x49, 0xf7, 893 0xd5, 0xdd, 0xb6, 0xec, 0x40, 0x1e, 0xeb, 0x8e, 0xd6, 0xaa, 0xa5, 0xee,
888 0xde, 0x73, 0xf6, 0x39, 0x67, 0x9f, 0xbd, 0xbf, 0xfd, 0xed, 0x73, 0xce, 894 0xaa, 0x73, 0xf6, 0x39, 0x67, 0x9f, 0xbd, 0xbf, 0xfd, 0xed, 0x73, 0x4e,
889 0xf5, 0xa7, 0x80, 0x52, 0xe4, 0xff, 0xca, 0xf9, 0xb9, 0x2e, 0xda, 0x71, 895 0xb5, 0x06, 0x54, 0xa3, 0xf4, 0x37, 0x8b, 0xd7, 0xd5, 0x1d, 0x1b, 0xee,
890 0x0f, 0xe6, 0x5d, 0xa7, 0xcb, 0xb5, 0xd3, 0x05, 0x27, 0xfe, 0xc4, 0xbf, 896 0x5e, 0xdc, 0x7e, 0x75, 0x87, 0x7c, 0xf7, 0xce, 0xf5, 0x7a, 0xf1, 0x61,
891 0xc0, 0x9f, 0x5a, 0x30, 0xff, 0xe7, 0x00, 0xbc, 0x85, 0x36, 0xe5, 0x03, 897 0x7f, 0x26, 0x12, 0x97, 0xde, 0xd2, 0x3e, 0xb4, 0xe0, 0x47, 0xfc, 0x25,
892 0xb7, 0x6a, 0xac, 0xfb, 0xe2, 0x02, 0x0d, 0x6e, 0x87, 0x11, 0x5d, 0x7e, 898 0x10, 0x91, 0x7f, 0xad, 0xa5, 0xaf, 0x1e, 0x20, 0x58, 0x6e, 0x5f, 0x2e,
893 0x8f, 0x06, 0xc4, 0xb2, 0x0d, 0x81, 0x85, 0x38, 0x67, 0x99, 0x3e, 0x27, 899 0xf8, 0x55, 0xb3, 0xf3, 0xbf, 0x2e, 0xd3, 0xe1, 0xf7, 0x98, 0x9f, 0xff,
894 0xe4, 0xfe, 0xa7, 0x8c, 0xff, 0x7c, 0xec, 0x9f, 0x6e, 0x08, 0x9e, 0xce, 900 0x8b, 0xbb, 0x75, 0x20, 0x99, 0x6f, 0xd5, 0x96, 0xe3, 0x9c, 0x63, 0x85,
895 0x38, 0xe0, 0xf6, 0x1a, 0x5f, 0x83, 0x77, 0x26, 0xdc, 0x75, 0xac, 0xf3, 901 0xbc, 0x90, 0xfb, 0x7f, 0x62, 0x7e, 0xf0, 0xc4, 0xb7, 0xae, 0x8b, 0x9c,
896 0xed, 0x59, 0xb3, 0x55, 0x54, 0x14, 0x64, 0x05, 0xfd, 0x19, 0x04, 0xbd, 902 0xc9, 0x79, 0xe0, 0x0f, 0x9a, 0x16, 0x82, 0x0b, 0xe1, 0x6f, 0x62, 0x9d,
897 0x26, 0x82, 0x61, 0x13, 0x88, 0x3b, 0x0d, 0xc4, 0x8b, 0x0d, 0x37, 0x8a, 903 0xbf, 0x6b, 0xd9, 0xa6, 0xa2, 0xb6, 0x2c, 0x2b, 0x12, 0xce, 0x21, 0x12,
898 0xb4, 0x22, 0xc4, 0xbd, 0x6b, 0x02, 0xeb, 0xa2, 0xc0, 0x82, 0x84, 0x3b, 904 0xb4, 0x10, 0x89, 0x59, 0x40, 0xca, 0x6b, 0x22, 0x55, 0x69, 0xfa, 0x51,
899 0x70, 0x3c, 0x0b, 0xdc, 0x93, 0x70, 0x63, 0xd2, 0xe1, 0x09, 0xbc, 0x99, 905 0xa1, 0x57, 0x20, 0x15, 0xdc, 0xa8, 0x6d, 0xe1, 0x18, 0x97, 0xd9, 0x7e,
900 0xbd, 0xb9, 0x32, 0xa7, 0x83, 0x18, 0x1c, 0x1a, 0xe2, 0xaa, 0x21, 0xf7, 906 0xed, 0x44, 0x1e, 0xb8, 0xdb, 0xf6, 0xe3, 0xb8, 0x27, 0xa0, 0x9d, 0xcc,
901 0x11, 0x58, 0x98, 0x8d, 0x62, 0x7d, 0xca, 0xb2, 0x9c, 0x1a, 0x9c, 0x83, 907 0xef, 0xab, 0x2b, 0xea, 0x23, 0x09, 0x8f, 0x8e, 0x94, 0x6a, 0xca, 0x7d,
902 0x8d, 0x0e, 0xc4, 0xbc, 0x0a, 0x76, 0x6b, 0x51, 0x74, 0x8f, 0x05, 0x39, 908 0x68, 0xcb, 0xf3, 0x48, 0xf9, 0xcc, 0xcf, 0x6b, 0xe3, 0x36, 0xd0, 0x9b,
903 0x58, 0x29, 0x23, 0xed, 0xfc, 0xe6, 0xdc, 0xc6, 0xd4, 0x49, 0xeb, 0x9f, 909 0x69, 0x36, 0x4e, 0xa0, 0x35, 0x7c, 0x18, 0x95, 0x48, 0x85, 0x22, 0x31,
904 0x66, 0x79, 0xf1, 0xe4, 0x98, 0x0f, 0x07, 0xc7, 0x82, 0xa6, 0x89, 0x2a, 910 0xe0, 0x83, 0x73, 0x8f, 0x66, 0x14, 0xf8, 0xf4, 0xd9, 0xe8, 0xdc, 0x0b,
905 0x9c, 0x48, 0x37, 0xe2, 0xa4, 0x56, 0x87, 0x37, 0x35, 0x0b, 0xeb, 0xf5, 911 0x3c, 0x92, 0x89, 0x24, 0x75, 0x05, 0xe8, 0x9f, 0x94, 0xba, 0x91, 0x60,
906 0x30, 0x54, 0x2d, 0xa8, 0x43, 0xf1, 0x63, 0xd0, 0x1b, 0x0c, 0xc4, 0xc1, 912 0x8e, 0xcf, 0xb7, 0x64, 0x80, 0xad, 0x99, 0xd9, 0xd8, 0x96, 0x75, 0xf0,
907 0x4e, 0x54, 0x04, 0xc3, 0xe3, 0xac, 0x9b, 0x4a, 0x21, 0x5e, 0x64, 0x38, 913 0x9c, 0xd1, 0x1c, 0xdc, 0xc7, 0x16, 0x7a, 0xdd, 0xe7, 0xb3, 0x61, 0xe5,
908 0x51, 0xa2, 0xdd, 0x8c, 0x53, 0xdb, 0x0c, 0x7c, 0xb0, 0x0d, 0xcb, 0x2b, 914 0xe4, 0xf9, 0x5b, 0xce, 0xb7, 0x5a, 0x82, 0x78, 0x7a, 0x32, 0x84, 0x67,
909 0x60, 0x59, 0xd9, 0x48, 0xa8, 0x6d, 0xb5, 0xe2, 0x0d, 0x3c, 0x9f, 0x45, 915 0x27, 0xeb, 0xf1, 0x48, 0xb6, 0x1e, 0xdb, 0xb3, 0x31, 0xa8, 0xba, 0x83,
910 0xe0, 0x58, 0x76, 0xaa, 0xde, 0x38, 0x21, 0xd5, 0x6c, 0x27, 0x15, 0xc5, 916 0x58, 0x3c, 0x86, 0x8a, 0xeb, 0x1d, 0x9c, 0x34, 0xda, 0xb0, 0x95, 0x82,
911 0x4e, 0xf6, 0xcd, 0x3b, 0x2b, 0x8a, 0xf4, 0x18, 0xdb, 0x4e, 0x49, 0x7f, 917 0x5f, 0x6d, 0x6b, 0xc4, 0xda, 0x60, 0x13, 0xb6, 0xe8, 0xd7, 0xa1, 0x38,
912 0xfc, 0xf8, 0xa7, 0x59, 0x7f, 0xcd, 0xf9, 0x64, 0x5b, 0x94, 0xbd, 0x21, 918 0xd6, 0x0f, 0xce, 0x65, 0x32, 0xd2, 0x3f, 0xaf, 0xaa, 0xea, 0x37, 0xe2,
913 0xf5, 0x3a, 0xfb, 0x55, 0x87, 0xef, 0x8e, 0xf9, 0xf1, 0x1d, 0xf6, 0xed, 919 0xf4, 0x4e, 0x13, 0xef, 0xef, 0xc4, 0x9a, 0x5a, 0x38, 0x4e, 0x3e, 0x1e,
914 0x29, 0x29, 0x37, 0x16, 0x60, 0x1f, 0xab, 0x70, 0x84, 0xfd, 0xfb, 0x21, 920 0xed, 0x7e, 0x50, 0x09, 0x6a, 0x4f, 0xe5, 0xd9, 0xa1, 0x55, 0x5e, 0xca,
915 0xfb, 0xf7, 0x0a, 0xfb, 0xb7, 0x9b, 0xfd, 0x5b, 0xd1, 0x1c, 0xdc, 0x69, 921 0x83, 0x36, 0x92, 0x9f, 0x39, 0x15, 0x6c, 0x2f, 0xc3, 0x76, 0x33, 0xd2,
916 0x42, 0xc1, 0xd2, 0xc6, 0x36, 0xe9, 0x1b, 0xc7, 0xc7, 0x8f, 0xaa, 0x22, 922 0x97, 0x30, 0xbe, 0xd5, 0xf2, 0xdf, 0x68, 0x0f, 0xc5, 0x31, 0x6d, 0xcd,
917 0x56, 0x1d, 0x0c, 0x07, 0xd4, 0x60, 0x18, 0x76, 0x9f, 0xa5, 0xfd, 0xdf, 923 0xbc, 0xc6, 0x3e, 0x69, 0xec, 0x4f, 0x13, 0xbe, 0x36, 0x19, 0xc6, 0x57,
918 0x9c, 0x4b, 0xa6, 0x60, 0xba, 0xa9, 0x57, 0x97, 0x71, 0x33, 0xb2, 0xec, 924 0xd9, 0xb7, 0xaf, 0x4c, 0x4a, 0x1f, 0x23, 0x7b, 0x2c, 0xd4, 0x63, 0x34,
919 0xf3, 0x13, 0xdb, 0x42, 0xcd, 0xab, 0x54, 0x2c, 0xf1, 0xb0, 0xdf, 0x0f, 925 0xdb, 0x84, 0xa7, 0xf5, 0x36, 0x7c, 0x85, 0x7d, 0xec, 0x33, 0x62, 0x58,
920 0x46, 0x42, 0x81, 0xd9, 0xec, 0xf7, 0x50, 0x56, 0x55, 0x55, 0xcd, 0x17, 926 0x9b, 0xb8, 0x8b, 0xfd, 0x51, 0xb0, 0xaa, 0xed, 0x2f, 0x4b, 0xfd, 0x8a,
921 0x18, 0xce, 0x2a, 0x88, 0x2d, 0x55, 0x39, 0x7e, 0xb6, 0x9b, 0x62, 0x5f, 927 0x68, 0x50, 0x55, 0x24, 0x1b, 0x22, 0x31, 0x4d, 0x15, 0x99, 0x17, 0xfa,
922 0x52, 0xec, 0x4b, 0x8a, 0x7d, 0x49, 0x49, 0x9f, 0xc3, 0xec, 0x6f, 0x4e, 928 0x3b, 0x90, 0x81, 0xe5, 0x37, 0xa5, 0xcf, 0x37, 0x22, 0xcf, 0xfe, 0x7e,
923 0xd7, 0x83, 0xd9, 0xcb, 0xf5, 0x35, 0xd8, 0xc3, 0xb9, 0xa4, 0x3e, 0xa5, 929 0x79, 0x67, 0xd4, 0x58, 0xaf, 0x62, 0x65, 0x80, 0x7d, 0x7e, 0x20, 0x1e,
924 0xcf, 0x96, 0xf5, 0xaa, 0xbe, 0x88, 0x7d, 0xb0, 0xac, 0x8f, 0x74, 0xe9, 930 0x4d, 0x2c, 0x62, 0x9f, 0xc7, 0xf3, 0x2a, 0xc7, 0x13, 0xd2, 0xc6, 0xd8,
925 0x9b, 0xf4, 0xab, 0x1c, 0x31, 0x5f, 0x8a, 0x73, 0x56, 0xe8, 0x1b, 0x8c, 931 0xf7, 0xe4, 0x2a, 0x95, 0x7d, 0x67, 0x5f, 0x32, 0xec, 0x4b, 0x86, 0x7d,
926 0x6a, 0xcc, 0x30, 0x5d, 0x86, 0xcc, 0xbb, 0xca, 0xfb, 0x21, 0xfd, 0x23, 932 0xc9, 0xb0, 0x2f, 0x6e, 0xbf, 0x63, 0xec, 0x73, 0x71, 0x8e, 0x46, 0xf2,
927 0xc0, 0x1a, 0x8c, 0x7a, 0x03, 0x1b, 0xb2, 0xbe, 0x40, 0x17, 0x75, 0xd9, 933 0xc7, 0xd9, 0xdf, 0x99, 0xfd, 0x6c, 0x62, 0xdf, 0x91, 0xaa, 0xe7, 0xbc,
928 0x9d, 0x0d, 0xfa, 0xc5, 0x56, 0xff, 0xb0, 0x2f, 0x41, 0x6f, 0xdc, 0x9e, 934 0x35, 0xa7, 0x65, 0xde, 0x1c, 0xe7, 0x55, 0xc3, 0x71, 0x7e, 0x6e, 0x04,
929 0x53, 0xe9, 0xd3, 0x64, 0x7e, 0x3e, 0x2d, 0xeb, 0x15, 0xdd, 0xcf, 0xb6, 935 0xa8, 0xbf, 0x0c, 0xed, 0xa0, 0xdc, 0x9f, 0xf9, 0x56, 0x85, 0x89, 0x4e,
930 0xa5, 0x3f, 0x51, 0xbb, 0xed, 0x0f, 0x75, 0x44, 0xbd, 0x10, 0xbb, 0x08, 936 0x9a, 0xa0, 0x73, 0xa4, 0x23, 0x9a, 0x68, 0x50, 0x54, 0x78, 0xf5, 0xa0,
931 0x99, 0x3f, 0xb4, 0xed, 0xcb, 0x1b, 0x48, 0x67, 0x59, 0xe6, 0xbc, 0x1c, 937 0xd6, 0x52, 0x88, 0x18, 0xd4, 0x8f, 0x16, 0x2d, 0x40, 0xd3, 0x0b, 0x94,
932 0x27, 0xc7, 0x0a, 0xb6, 0x65, 0x59, 0xbb, 0xb5, 0xa0, 0x57, 0xda, 0xca, 938 0x75, 0x51, 0xbb, 0x91, 0xe0, 0x14, 0xa4, 0x5d, 0x8d, 0xed, 0x1f, 0x2f,
933 0x8d, 0x51, 0xec, 0x46, 0xec, 0xc4, 0x1f, 0xf7, 0x18, 0x5e, 0xca, 0x44, 939 0xcd, 0x9d, 0xc8, 0x0f, 0xb3, 0x4d, 0x69, 0x5f, 0x64, 0x3b, 0xce, 0xcf,
934 0xdb, 0xce, 0x64, 0xa7, 0x55, 0xab, 0x89, 0x2e, 0xb5, 0x35, 0xb5, 0x0e, 940 0x0c, 0xe8, 0x41, 0x44, 0xad, 0x41, 0xda, 0x9f, 0xc7, 0x0c, 0x6a, 0x1b,
935 0x4f, 0xf3, 0xa9, 0x79, 0x5f, 0x31, 0xcb, 0xa3, 0x11, 0x94, 0x6a, 0xf0, 941 0xf2, 0x7c, 0x7e, 0x5e, 0x46, 0x71, 0x3e, 0xd6, 0xe6, 0xb5, 0xd2, 0x18,
936 0x94, 0x68, 0x68, 0xeb, 0x1d, 0x29, 0x35, 0xcb, 0x8c, 0xef, 0xdf, 0x9d, 942 0x22, 0xec, 0x82, 0xd8, 0x41, 0x38, 0x15, 0x30, 0x83, 0xd2, 0xf7, 0xee,
937 0x1c, 0x71, 0xa3, 0x74, 0x44, 0x43, 0xc9, 0x48, 0xc8, 0x89, 0x0a, 0x03, 943 0x3d, 0x03, 0x9b, 0x9d, 0x79, 0xba, 0xe8, 0x4a, 0xdf, 0x38, 0xcf, 0x13,
938 0x5b, 0xc6, 0xde, 0x71, 0xe4, 0xc6, 0xbb, 0xb0, 0x30, 0x6e, 0xb1, 0x71, 944 0x48, 0x9c, 0x5e, 0xf2, 0x90, 0x35, 0xab, 0x23, 0x8e, 0x6a, 0x1d, 0x81,
939 0xf7, 0x5b, 0x89, 0xd3, 0x56, 0x91, 0x56, 0xf2, 0x05, 0x87, 0xa1, 0x05, 945 0x2a, 0x1d, 0xdd, 0xe9, 0x89, 0x6a, 0xab, 0xc6, 0xfc, 0xe6, 0x9d, 0x03,
940 0xf6, 0x02, 0xa7, 0x57, 0x44, 0xfd, 0xe8, 0xa2, 0xcd, 0xce, 0xd0, 0x7e, 946 0x13, 0x7e, 0x54, 0x4f, 0xe8, 0xa8, 0x9a, 0x78, 0xdc, 0x8b, 0x5a, 0x03,
941 0xe2, 0x41, 0x45, 0x2b, 0xcc, 0xb1, 0x1a, 0xf1, 0x07, 0xac, 0x4f, 0x58, 947 0x3b, 0x26, 0xff, 0xcc, 0x5b, 0x1c, 0xdb, 0xcd, 0xa5, 0x31, 0xba, 0xb6,
942 0x56, 0x91, 0x71, 0xf7, 0xdd, 0x2c, 0xe7, 0xdd, 0x8b, 0x5a, 0x2c, 0xf4, 948 0xef, 0x7f, 0xdd, 0x3e, 0xe3, 0x54, 0xe8, 0x55, 0x7f, 0xe6, 0x31, 0x75,
943 0x62, 0xed, 0xfa, 0xe8, 0xaf, 0x95, 0x7d, 0x03, 0xcb, 0x61, 0x0e, 0xaf, 949 0x6d, 0x0c, 0x38, 0xb3, 0xb6, 0x63, 0x39, 0x7a, 0x83, 0x0a, 0xe6, 0xeb,
944 0xe6, 0x47, 0x05, 0xaa, 0xae, 0xbe, 0xda, 0x71, 0xe3, 0x72, 0x74, 0x0f, 950 0x7f, 0x32, 0x0b, 0xb5, 0x26, 0xac, 0xc9, 0xc6, 0x54, 0x85, 0x19, 0x4a,
945 0xb3, 0xaf, 0xa9, 0x18, 0xed, 0x53, 0x6c, 0x6b, 0x35, 0x36, 0x0d, 0x3f, 951 0x71, 0x6e, 0xf0, 0x82, 0x9d, 0x83, 0x6f, 0xc0, 0x71, 0xa4, 0xec, 0x49,
946 0x04, 0x73, 0xf7, 0x4a, 0x96, 0x91, 0x31, 0x75, 0xf1, 0xbb, 0x15, 0x8f, 952 0xdc, 0x79, 0xa7, 0x6a, 0x1e, 0xba, 0xc6, 0x87, 0x4e, 0x96, 0xc7, 0xa6,
947 0x8d, 0x89, 0x7c, 0xe9, 0xc6, 0xe5, 0xe4, 0xbf, 0x63, 0x2d, 0xf4, 0x89, 953 0xa3, 0x1d, 0x3f, 0x57, 0xd4, 0x9d, 0xdd, 0xb0, 0xc6, 0x3d, 0x48, 0x06,
948 0x7c, 0x27, 0x36, 0x26, 0xec, 0x79, 0x51, 0x68, 0x9f, 0xe1, 0x13, 0xb4, 954 0x53, 0xfc, 0x7f, 0xc5, 0x15, 0x2b, 0x13, 0xdd, 0xb0, 0xc7, 0xa7, 0x79,
949 0x95, 0x6e, 0xdd, 0x40, 0x4f, 0xaa, 0x19, 0x1b, 0x53, 0xb1, 0x20, 0xd1, 955 0xdf, 0xcb, 0x7b, 0x26, 0xd2, 0x99, 0x2b, 0xae, 0xb8, 0x3d, 0x91, 0xc2,
950 0x80, 0xf3, 0xd6, 0x06, 0xd5, 0x08, 0xb5, 0x76, 0x41, 0x7c, 0x02, 0x4a, 956 0xc0, 0xb8, 0x7c, 0xf6, 0x62, 0xaa, 0x3e, 0x85, 0xed, 0xbb, 0x35, 0xd4,
951 0xa9, 0x01, 0x67, 0x36, 0x3a, 0xe9, 0x7e, 0x31, 0xa1, 0xb5, 0x3f, 0xae, 957 0xe9, 0xdd, 0xc8, 0x8c, 0xcb, 0x67, 0xc7, 0x39, 0x65, 0x7c, 0x09, 0x7b,
952 0xb8, 0x10, 0xaf, 0x92, 0x36, 0x26, 0xdd, 0x2f, 0x27, 0x14, 0xfc, 0x52, 958 0xda, 0xe8, 0xff, 0x73, 0xbb, 0xb1, 0x6d, 0xb7, 0x85, 0x4a, 0xdd, 0xa2,
953 0x0b, 0x75, 0xbc, 0xab, 0x4c, 0xba, 0x5f, 0xca, 0x7a, 0x51, 0x9b, 0x0c, 959 0xee, 0x15, 0xef, 0x3f, 0xb7, 0x29, 0xd0, 0xee, 0x84, 0xb7, 0x42, 0x17,
954 0xb6, 0x9b, 0x4a, 0x33, 0x9e, 0xc9, 0xfa, 0xe0, 0x4f, 0x1a, 0x38, 0x90, 960 0xbd, 0x25, 0xbc, 0xf7, 0xd8, 0x66, 0x70, 0xbe, 0xee, 0x38, 0x23, 0xc6,
955 0xd5, 0xb1, 0xff, 0x22, 0x9f, 0xb9, 0xec, 0x9f, 0xe9, 0x60, 0x5f, 0x57, 961 0x22, 0x7c, 0xba, 0x7b, 0x2d, 0xac, 0x7d, 0x01, 0x58, 0xab, 0xe5, 0x7f,
956 0x26, 0x02, 0xe8, 0xd2, 0xcf, 0x59, 0x31, 0x2f, 0xe2, 0x95, 0xc6, 0xa4, 962 0x37, 0x75, 0xb8, 0x16, 0xbd, 0xfb, 0xd6, 0xa2, 0xff, 0x31, 0x3a, 0x6e,
957 0xfb, 0x83, 0x24, 0x94, 0x0a, 0x43, 0xf3, 0x8f, 0x2a, 0xbf, 0xb0, 0xe2, 963 0x7d, 0xd0, 0x9d, 0xa7, 0x6f, 0xb5, 0x48, 0x9f, 0xa4, 0x7f, 0x3d, 0xbc,
958 0x3e, 0x29, 0xc6, 0xfe, 0x8d, 0xc9, 0x58, 0x97, 0x50, 0xef, 0x06, 0xe7, 964 0x44, 0xb7, 0x5f, 0xe0, 0x7f, 0x29, 0x33, 0xed, 0x60, 0xce, 0x85, 0x32,
959 0xfd, 0xb4, 0x55, 0xc6, 0x39, 0x2b, 0x32, 0xae, 0xc4, 0xf0, 0x80, 0x86, 965 0xdb, 0x59, 0x66, 0xdb, 0x45, 0x65, 0x4c, 0x3c, 0x31, 0x29, 0xba, 0x10,
960 0xfd, 0x1c, 0xeb, 0xfb, 0xfa, 0x78, 0xb3, 0x07, 0x5a, 0xdb, 0x7b, 0x08, 966 0x95, 0xfd, 0x3e, 0x5d, 0x7c, 0xdb, 0xe9, 0x0d, 0x89, 0x2e, 0xac, 0x1e,
961 0xc6, 0x66, 0x2b, 0x06, 0x8e, 0x66, 0x35, 0x0c, 0x25, 0x0c, 0x1c, 0x4a, 967 0x1f, 0x22, 0xdd, 0xf7, 0x2a, 0x5e, 0xac, 0x18, 0x00, 0xeb, 0xd0, 0x09,
962 0xd4, 0x7b, 0xbb, 0x31, 0x17, 0x31, 0x7f, 0x0e, 0x1f, 0x47, 0xd8, 0xef, 968 0xaa, 0x23, 0xc9, 0x85, 0x8a, 0x89, 0xea, 0x01, 0x05, 0x2b, 0xe2, 0x55,
963 0xc1, 0x50, 0x1b, 0x2a, 0x8d, 0x66, 0x4c, 0xb0, 0xdf, 0xa7, 0xe6, 0x89, 969 0xd0, 0xea, 0x45, 0xde, 0x8f, 0x1c, 0x2b, 0x28, 0xfd, 0x3d, 0x8a, 0x1a,
964 0x1c, 0x1d, 0x2f, 0xfd, 0x09, 0x7d, 0x15, 0xbd, 0x3e, 0xca, 0xbe, 0x36, 970 0xde, 0x5f, 0x17, 0xff, 0x01, 0xf1, 0x4c, 0xfa, 0x14, 0x67, 0xf9, 0x3b,
965 0xcf, 0x3d, 0x67, 0x61, 0x9a, 0x1b, 0xc7, 0xf5, 0x2b, 0x88, 0x47, 0x30, 971 0x78, 0xff, 0x95, 0x19, 0xdf, 0xa5, 0x9c, 0xe3, 0xf4, 0x19, 0x06, 0xfa,
966 0x4b, 0x0c, 0xb7, 0xb3, 0x27, 0xe1, 0xc5, 0xbe, 0xac, 0xc7, 0xd9, 0x9d, 972 0x33, 0x6d, 0xd8, 0x9e, 0x49, 0x46, 0xa8, 0x25, 0xcb, 0x67, 0xf2, 0xbe,
967 0xf0, 0x61, 0x77, 0x36, 0x80, 0x5a, 0x03, 0xa6, 0x9f, 0x72, 0x6b, 0xe9, 973 0x19, 0xed, 0xea, 0x85, 0xb4, 0x03, 0xa5, 0xda, 0x84, 0x37, 0xdf, 0x71,
968 0x4b, 0xa3, 0x03, 0x75, 0x18, 0x1b, 0x08, 0xea, 0x2f, 0x13, 0x7b, 0xf6, 974 0xdc, 0xff, 0x92, 0xad, 0xf7, 0x3c, 0xa5, 0xf8, 0x68, 0xec, 0xd2, 0xce,
969 0x0e, 0x5d, 0x89, 0x91, 0x01, 0x05, 0xc3, 0x21, 0xf6, 0x9d, 0xbf, 0x9f, 975 0x71, 0xff, 0x2b, 0xb6, 0x82, 0x37, 0xf5, 0xe8, 0x86, 0x77, 0x94, 0xe3,
970 0x18, 0xb8, 0x1a, 0xd9, 0x01, 0x07, 0xb6, 0xd8, 0x7a, 0xb5, 0xfd, 0x30, 976 0xfe, 0x97, 0xf3, 0x41, 0xcc, 0x1b, 0x88, 0xf4, 0x58, 0x4a, 0x02, 0x5f,
971 0xff, 0x7d, 0x25, 0x32, 0x43, 0x70, 0xce, 0x4e, 0x7a, 0xf1, 0x78, 0xd6, 977 0xcf, 0x87, 0x10, 0x1e, 0x30, 0x71, 0x30, 0x6f, 0xe0, 0xc9, 0x8b, 0x70,
972 0xe9, 0xd4, 0x92, 0x3e, 0x0c, 0x65, 0xbf, 0xce, 0x79, 0x13, 0xd9, 0x01, 978 0xe0, 0x43, 0xff, 0x2c, 0x0f, 0xc7, 0xbe, 0xce, 0xd6, 0xd0, 0x6b, 0x9c,
973 0x0c, 0x26, 0xfe, 0x9a, 0xbf, 0x65, 0x1c, 0xb7, 0x2b, 0xf9, 0xd8, 0x41, 979 0x73, 0x92, 0x41, 0xa4, 0xea, 0xcc, 0xe3, 0xfe, 0xf7, 0x07, 0xa0, 0xd4,
974 0xcc, 0x0e, 0x10, 0x4f, 0x5b, 0xd0, 0x95, 0x72, 0x60, 0x85, 0x8d, 0xeb, 980 0x9a, 0x7a, 0xb8, 0xa0, 0xfc, 0xab, 0x93, 0x0a, 0x49, 0x31, 0xf6, 0xcf,
975 0x29, 0x3e, 0x6b, 0xa1, 0xcd, 0x17, 0xe4, 0x0a, 0xbe, 0x07, 0x88, 0xbd, 981 0xc5, 0xb2, 0x24, 0xed, 0xce, 0x20, 0xce, 0x9d, 0x71, 0x6a, 0x68, 0xb3,
976 0x47, 0xe9, 0x03, 0x51, 0xda, 0xbf, 0x8e, 0xff, 0x33, 0xd6, 0x88, 0x7f, 982 0x15, 0xe6, 0x65, 0x18, 0x1f, 0xd6, 0xf1, 0xa4, 0xed, 0x38, 0xef, 0x19,
977 0x1c, 0x0b, 0xe3, 0x7b, 0x63, 0x1a, 0xfe, 0x81, 0xb8, 0xf4, 0xf4, 0xd8, 983 0x53, 0x89, 0x00, 0xf4, 0xee, 0x77, 0x11, 0x49, 0x2e, 0xa2, 0x5e, 0x8e,
978 0x54, 0xff, 0xbf, 0x9b, 0xe3, 0x13, 0x1f, 0x34, 0xb0, 0x2e, 0x55, 0x84, 984 0xe6, 0x75, 0x8c, 0xda, 0x26, 0x9e, 0xb3, 0x9b, 0x83, 0x7d, 0x58, 0x8c,
979 0x0d, 0x03, 0xa5, 0xe8, 0x1e, 0xa8, 0x0f, 0x1f, 0xa2, 0xdd, 0x7c, 0x4f, 985 0x64, 0xb8, 0x18, 0x43, 0x26, 0xd8, 0xef, 0x91, 0x68, 0x37, 0xea, 0xcc,
980 0xff, 0x1c, 0xc6, 0xab, 0x29, 0x83, 0xfe, 0xbb, 0x89, 0xf7, 0x37, 0x0f, 986 0x04, 0x0e, 0xb1, 0xdf, 0xa7, 0x97, 0x88, 0x1c, 0x03, 0x2f, 0xff, 0x01,
981 0xd4, 0x53, 0xef, 0x96, 0xa5, 0x46, 0x1a, 0x9a, 0x27, 0x88, 0x59, 0x93, 987 0x7d, 0x25, 0xbe, 0xe3, 0x71, 0xf6, 0x35, 0xb1, 0xf8, 0x9c, 0x83, 0xd9,
982 0xbe, 0x60, 0x60, 0x5c, 0x0d, 0x06, 0x62, 0x70, 0x21, 0xd1, 0xa8, 0xc2, 988 0x7e, 0x9c, 0x30, 0xe6, 0xd2, 0x0e, 0x61, 0x55, 0x99, 0x7e, 0x6f, 0xbf,
983 0x9c, 0x1e, 0xcc, 0x98, 0xc4, 0x4d, 0x9f, 0x76, 0xb5, 0x22, 0xd8, 0x66, 989 0x1d, 0xc4, 0x81, 0x7c, 0xc0, 0xdb, 0x67, 0x87, 0xb0, 0x8f, 0xfe, 0x36,
984 0xaa, 0x06, 0x6d, 0x8e, 0x78, 0xa7, 0xc6, 0xe8, 0x13, 0xa5, 0xf8, 0x60, 990 0x8f, 0xa6, 0x1e, 0xa6, 0xdc, 0x79, 0xc4, 0xb5, 0xc2, 0x70, 0x13, 0x26,
985 0x20, 0xd8, 0x63, 0xaa, 0x77, 0xc1, 0xac, 0xb6, 0xac, 0xef, 0x44, 0xd0, 991 0x87, 0x23, 0xc6, 0x2b, 0x4a, 0x18, 0x63, 0xa3, 0x97, 0x61, 0x62, 0x58,
986 0x71, 0x85, 0x81, 0xd8, 0x74, 0x62, 0xc8, 0xd5, 0xc6, 0x12, 0x10, 0x9f, 992 0xc1, 0x78, 0x94, 0x7d, 0xe7, 0xe7, 0x2f, 0x0f, 0x5f, 0x81, 0xfc, 0xb0,
987 0x71, 0x2a, 0xa9, 0xf9, 0x7f, 0xa2, 0xdc, 0x8d, 0xaf, 0xb7, 0x05, 0x03, 993 0x07, 0x3b, 0x5c, 0xbd, 0xba, 0x38, 0x53, 0xfa, 0x7f, 0x19, 0x72, 0xa3,
988 0x01, 0xb5, 0xc1, 0xdc, 0xad, 0x36, 0xd3, 0xd4, 0x11, 0xf0, 0x1b, 0xb7, 994 0xf0, 0x2e, 0x1a, 0x08, 0xe2, 0xa9, 0xbc, 0xd7, 0xab, 0x0f, 0x84, 0x30,
989 0x61, 0x8d, 0x3d, 0x56, 0x05, 0x5e, 0x2d, 0x86, 0xee, 0x14, 0x2b, 0xf9, 995 0x9a, 0xff, 0x36, 0xe7, 0x4d, 0x64, 0x6b, 0x18, 0xb1, 0xc7, 0xdc, 0x39,
990 0xea, 0xdb, 0xfb, 0xd4, 0xfa, 0x33, 0xba, 0x1a, 0x3c, 0xda, 0xa6, 0x12, 996 0xac, 0x33, 0x29, 0xac, 0x18, 0x5f, 0x19, 0xcb, 0x34, 0xc6, 0x99, 0x04,
991 0x2f, 0xe6, 0x9e, 0xb2, 0x02, 0x35, 0x96, 0xd5, 0x34, 0x57, 0xda, 0x0c, 997 0x71, 0x48, 0x7c, 0xdc, 0x4f, 0x0c, 0x12, 0x1f, 0x7f, 0x4d, 0x41, 0x6d,
992 0xa0, 0x9a, 0x73, 0x53, 0xc5, 0xb9, 0x69, 0x1a, 0x2d, 0xc5, 0xbb, 0x03, 998 0x02, 0x7d, 0x93, 0xe5, 0xe7, 0x0a, 0xed, 0xdf, 0x8b, 0x75, 0x41, 0x03,
993 0x30, 0xaf, 0x30, 0x82, 0xad, 0x0f, 0xaa, 0xa5, 0x78, 0x67, 0xa8, 0x14, 999 0x76, 0x46, 0xec, 0xb4, 0x8c, 0xcb, 0xf2, 0x59, 0xe6, 0xbf, 0x1a, 0xd6,
994 0x6f, 0x0e, 0x38, 0x71, 0x72, 0xc0, 0xb2, 0xee, 0xd5, 0x2b, 0x51, 0x14, 1000 0xfe, 0x6a, 0xec, 0xa0, 0x8f, 0x3d, 0xba, 0x53, 0xee, 0x3b, 0xce, 0x7d,
995 0xc1, 0xf4, 0x22, 0x84, 0x4e, 0x0f, 0xc2, 0xc4, 0xef, 0x59, 0xf6, 0x37, 1001 0xf1, 0x3a, 0xda, 0x18, 0x6e, 0xaa, 0x42, 0xd4, 0x78, 0xcb, 0xed, 0x9b,
996 0x03, 0x7e, 0xfc, 0xdb, 0xc0, 0x67, 0xf0, 0x74, 0x75, 0xec, 0xd8, 0x34, 1002 0x85, 0xb1, 0xbc, 0xc4, 0x50, 0x8d, 0xf1, 0xed, 0x28, 0xdb, 0xea, 0x60,
997 0xf8, 0x70, 0x86, 0x73, 0x7e, 0x2a, 0x11, 0x6c, 0xaf, 0x75, 0x04, 0xd7, 1003 0x3b, 0x06, 0xbe, 0x3d, 0xd9, 0x86, 0x7f, 0x9c, 0x8c, 0xe1, 0x1f, 0x26,
998 0x00, 0x0d, 0xab, 0x1e, 0x56, 0x82, 0xf1, 0x97, 0x95, 0x60, 0x20, 0xa9, 1004 0x75, 0xfc, 0xfd, 0xa4, 0x86, 0x67, 0x2e, 0xc2, 0xf5, 0x3b, 0xa9, 0x2b,
999 0xf8, 0xf0, 0x1e, 0x6d, 0xeb, 0x44, 0xb6, 0xbe, 0xf9, 0x35, 0xb6, 0xff, 1005 0xc1, 0x30, 0x03, 0x5b, 0x32, 0x15, 0xd8, 0x36, 0x5c, 0x8d, 0xbe, 0xe1,
1000 0x5b, 0xfd, 0x7b, 0xd6, 0x78, 0x8d, 0xe8, 0x50, 0xf4, 0x45, 0x9d, 0xa7, 1006 0xe6, 0xd8, 0x73, 0xc4, 0xe3, 0x7f, 0x30, 0x6e, 0xc7, 0x54, 0x43, 0x87,
1001 0xa8, 0x73, 0xe2, 0xee, 0xf7, 0x52, 0xd4, 0x39, 0xfb, 0xf3, 0xf4, 0x1f, 1007 0xeb, 0x33, 0x8f, 0xf0, 0xfe, 0xa3, 0xc3, 0xcd, 0x9c, 0x43, 0xc7, 0x51,
1002 0xe0, 0xa0, 0xcc, 0x57, 0x33, 0x7d, 0xfd, 0x2a, 0xfc, 0x9d, 0x3d, 0xb6, 1008 0xe3, 0xad, 0x89, 0x43, 0xc4, 0xf7, 0xe3, 0xa1, 0x88, 0x36, 0xa5, 0x46,
1003 0x63, 0xd6, 0xff, 0xf0, 0xc9, 0xf8, 0x7e, 0x34, 0x3d, 0xe7, 0xe3, 0x32, 1009 0xb4, 0x24, 0x7c, 0xb0, 0xdb, 0x54, 0x58, 0x73, 0x22, 0x39, 0x7a, 0x31,
1004 0xce, 0xa3, 0x56, 0xdc, 0x2b, 0x63, 0x94, 0xb1, 0xda, 0xba, 0x0c, 0x74, 1010 0x42, 0xfa, 0x7d, 0x1c, 0x5b, 0x44, 0xb3, 0x54, 0x83, 0xf6, 0xcb, 0x98,
1005 0x28, 0xd3, 0x55, 0x94, 0x5a, 0xd6, 0x56, 0x3d, 0xff, 0xdc, 0x57, 0x18, 1011 0xa1, 0x76, 0x10, 0x5f, 0xaa, 0xf1, 0xfe, 0x70, 0xa4, 0xdf, 0x52, 0xef,
1006 0xeb, 0xbf, 0xd2, 0x0e, 0x64, 0xbc, 0x6b, 0x1d, 0xa2, 0xfb, 0x80, 0xfa, 1012 0x80, 0xd5, 0xe0, 0x38, 0x5f, 0x8d, 0x63, 0xc3, 0x5c, 0x13, 0xc9, 0x39,
1007 0xaa, 0xf8, 0xbf, 0x19, 0x43, 0xb9, 0x47, 0x62, 0x60, 0xec, 0xfc, 0xf5, 1013 0x8c, 0x05, 0x57, 0x98, 0x49, 0x30, 0x8e, 0xe1, 0xf4, 0x80, 0x1e, 0xfe,
1008 0x53, 0x15, 0x17, 0x3f, 0xa7, 0x6d, 0xd9, 0xed, 0xfd, 0x3b, 0xaf, 0x65, 1014 0x7f, 0x94, 0x3b, 0xf1, 0xdf, 0xbb, 0x23, 0x9a, 0xa6, 0xb6, 0x5a, 0xfb,
1009 0x2c, 0xaf, 0xd0, 0x6e, 0xc4, 0x4e, 0x38, 0x9d, 0x86, 0xd8, 0xcc, 0xa5, 1015 0x54, 0x92, 0x8d, 0x46, 0x68, 0x61, 0xf3, 0x56, 0x6c, 0x74, 0x79, 0x82,
1010 0xf6, 0x22, 0xb6, 0xd2, 0x48, 0xbb, 0xfa, 0x17, 0x62, 0x62, 0x07, 0x9e, 1016 0x82, 0xa0, 0xde, 0x81, 0xbe, 0x0c, 0x2b, 0x85, 0x9a, 0x7b, 0x06, 0xd5,
1011 0xbc, 0xde, 0x2d, 0xd3, 0x1c, 0x70, 0x18, 0x26, 0x3e, 0x1f, 0x75, 0xe0, 1017 0xe6, 0x69, 0x43, 0x8d, 0x1c, 0xed, 0x56, 0x89, 0xb7, 0x8b, 0x4f, 0x3b,
1012 0xab, 0x51, 0x05, 0xd3, 0xb4, 0x60, 0x06, 0xaa, 0x69, 0x55, 0x91, 0x5b, 1018 0x5a, 0xa3, 0xe3, 0xb4, 0x2f, 0x96, 0x36, 0x35, 0x34, 0x70, 0x9e, 0xeb,
1013 0x6c, 0xe8, 0x4d, 0x63, 0xc3, 0x18, 0x50, 0xd9, 0x0b, 0x77, 0x85, 0x61, 1019 0x39, 0xcf, 0xed, 0x85, 0x6a, 0xbc, 0x33, 0x0c, 0x6b, 0xae, 0x19, 0xe9,
1014 0xe0, 0xa5, 0x24, 0xdc, 0x65, 0xf4, 0xcb, 0x2f, 0x27, 0xeb, 0xc7, 0xdf, 1020 0x7a, 0x40, 0xad, 0xc6, 0xdb, 0xa3, 0xd5, 0x38, 0x39, 0xec, 0xc5, 0x5b,
1015 0x56, 0x82, 0xb1, 0xd7, 0xa9, 0x4f, 0xea, 0xb5, 0xcd, 0xaf, 0x04, 0x5b, 1021 0xc3, 0x8e, 0x73, 0x8f, 0x51, 0x87, 0x8a, 0x38, 0xe6, 0x54, 0x20, 0x7a,
1016 0x57, 0x2b, 0xc1, 0xe6, 0xd9, 0x0a, 0xdc, 0x0a, 0xcb, 0x85, 0xb3, 0x69, 1022 0x66, 0x04, 0x16, 0x7e, 0xc3, 0xb2, 0xbf, 0x1c, 0x0e, 0xe3, 0x57, 0xc3,
1017 0xa4, 0xc6, 0xe4, 0x77, 0x33, 0x66, 0x65, 0xfb, 0xf2, 0x7d, 0x14, 0x3f, 1023 0x1f, 0xc3, 0x33, 0x0d, 0xc9, 0x63, 0xb3, 0x19, 0x23, 0xa7, 0x69, 0x3f,
1018 0x06, 0x8e, 0xd0, 0xbf, 0x87, 0x9a, 0x15, 0xe2, 0xc9, 0x3b, 0x56, 0xcc, 1024 0xa7, 0xed, 0x48, 0xcf, 0x3c, 0x4f, 0x64, 0x23, 0x79, 0xcb, 0xfa, 0x2f,
1019 0x47, 0xf9, 0x29, 0xb8, 0x4b, 0x59, 0xe7, 0xb6, 0x64, 0x1a, 0x8c, 0x99, 1025 0x2a, 0x91, 0xd4, 0x2b, 0x4a, 0x44, 0x1b, 0x50, 0x42, 0x78, 0x97, 0x76,
1020 0xee, 0x12, 0xd6, 0xb9, 0x36, 0x09, 0x78, 0x7a, 0x05, 0xf3, 0x83, 0x81, 1026 0x7a, 0x2a, 0xdf, 0x9c, 0xf8, 0x01, 0xdb, 0xff, 0xb5, 0xf1, 0x0f, 0xce,
1021 0x6b, 0x94, 0xfa, 0xf6, 0xa4, 0x12, 0x0c, 0xdf, 0xae, 0x34, 0xe8, 0x4f, 1027 0x54, 0xa3, 0xe8, 0x50, 0xf4, 0x45, 0x9d, 0xd3, 0x77, 0xff, 0x91, 0x31,
1022 0x90, 0xb7, 0x6c, 0x40, 0xae, 0x8d, 0x50, 0x36, 0x27, 0xbf, 0x3e, 0x0b, 1028 0xea, 0x1f, 0x32, 0xd4, 0x39, 0xfb, 0xf3, 0xcc, 0x6f, 0xc5, 0x2f, 0x99,
1023 0x65, 0x46, 0x12, 0x9e, 0x5a, 0x6d, 0x26, 0xce, 0x4e, 0xb3, 0xdb, 0x51, 1029 0xaf, 0x04, 0xe7, 0xf1, 0x72, 0xfc, 0x4f, 0x77, 0x6c, 0xc7, 0x9c, 0xbf,
1024 0x2a, 0x93, 0x01, 0x3b, 0x96, 0x56, 0x8e, 0x00, 0x2f, 0xf5, 0x5b, 0x38, 1030 0x09, 0xc9, 0xf8, 0x3a, 0x1b, 0x8b, 0x18, 0x24, 0xe3, 0x3c, 0xea, 0xa4,
1025 0x14, 0xa9, 0xa7, 0xbf, 0xb5, 0xc1, 0xcf, 0x32, 0x39, 0x5b, 0xb4, 0xb1, 1031 0x82, 0x32, 0x46, 0x19, 0xab, 0xab, 0x4b, 0x6d, 0x83, 0xf2, 0x90, 0x8a,
1026 0x42, 0xe9, 0x49, 0xd0, 0xe9, 0xa6, 0xcb, 0xa5, 0x0f, 0xf1, 0xcf, 0x23, 1032 0x6a, 0xc7, 0x79, 0xcc, 0x28, 0x3d, 0x0f, 0x95, 0xc7, 0xfa, 0x31, 0xde,
1027 0x26, 0xf7, 0x76, 0x26, 0xa0, 0xf4, 0x26, 0x82, 0x3b, 0x01, 0x6d, 0x4d, 1033 0x97, 0xf1, 0xbe, 0xe3, 0x11, 0xdd, 0x6b, 0xea, 0xd5, 0xfc, 0x1e, 0xb1,
1028 0x95, 0x23, 0xf6, 0x40, 0x25, 0x3a, 0x31, 0x11, 0x09, 0xc5, 0x07, 0x95, 1034 0x92, 0xb8, 0x33, 0xc0, 0xef, 0xb1, 0xe4, 0xf9, 0xef, 0xde, 0xba, 0x8b,
1029 0x50, 0x7b, 0xbf, 0xa2, 0xbb, 0xb7, 0xb0, 0xbd, 0xcd, 0x2c, 0xb3, 0x81, 1035 0x9f, 0xd3, 0x4e, 0xdd, 0xf6, 0xee, 0xe4, 0x77, 0x19, 0xcb, 0xab, 0xb4,
1030 0x9f, 0x45, 0x21, 0xad, 0xf5, 0x43, 0xc4, 0xae, 0x2d, 0x61, 0x99, 0x43, 1036 0x9b, 0x0f, 0xb3, 0x13, 0xb1, 0x91, 0x18, 0xed, 0xe9, 0x94, 0xc4, 0x15,
1031 0x7a, 0xe8, 0xcc, 0x6e, 0x84, 0x8e, 0xfe, 0xda, 0xa1, 0xbb, 0x1f, 0xcd, 1037 0x2b, 0x64, 0xfa, 0x2d, 0xd5, 0x84, 0x46, 0x9c, 0xf0, 0x2b, 0xe6, 0x06,
1032 0x8a, 0xac, 0x66, 0x65, 0x68, 0xf4, 0x26, 0x35, 0xe7, 0xfb, 0xff, 0x33, 1038 0x68, 0x79, 0x0b, 0x9f, 0xea, 0xf0, 0xe0, 0xaf, 0x3a, 0x14, 0xcc, 0xd6,
1033 0xaf, 0x83, 0xaf, 0xcb, 0xb5, 0xdd, 0xb6, 0x33, 0x79, 0xb4, 0xf4, 0x0f, 1039 0x37, 0x20, 0x7b, 0xad, 0xe5, 0xd4, 0xeb, 0x7b, 0x55, 0xf1, 0x81, 0x8a,
1034 0xef, 0x71, 0x92, 0x2e, 0xba, 0xd7, 0xe0, 0x1d, 0xa2, 0xdf, 0x38, 0xb4, 1040 0x34, 0x2c, 0xfa, 0x1d, 0x12, 0xe4, 0x4a, 0x75, 0x7f, 0xaa, 0xe0, 0x44,
1035 0x12, 0xfa, 0xb9, 0xf0, 0x95, 0x58, 0xd8, 0x05, 0xb9, 0xe7, 0x40, 0xc6, 1041 0x3c, 0x4a, 0x9b, 0xdb, 0x82, 0x6d, 0x9c, 0xf3, 0x59, 0x69, 0xf8, 0x03,
1036 0x19, 0xf3, 0x3b, 0xf0, 0x9f, 0x56, 0x6c, 0x99, 0xdc, 0x2b, 0x45, 0xbc, 1042 0xa6, 0x09, 0x7b, 0x00, 0xfe, 0x2a, 0xfa, 0xfe, 0x95, 0x03, 0xcd, 0x1b,
1037 0xad, 0xc1, 0xef, 0x44, 0x43, 0xf3, 0x7a, 0xfa, 0xf0, 0xe4, 0xb2, 0x05, 1043 0xc6, 0x94, 0x48, 0x22, 0xad, 0x44, 0xba, 0xa9, 0x6f, 0xe3, 0xb4, 0x8b,
1038 0x7c, 0x16, 0xd2, 0x0f, 0xa1, 0x3e, 0xb0, 0x1e, 0xf2, 0xfb, 0x2c, 0x6d, 1044 0x1b, 0x11, 0xad, 0x42, 0x91, 0x76, 0x4c, 0xb4, 0xe4, 0xb7, 0x60, 0x60,
1039 0x6d, 0x81, 0xd4, 0x65, 0x99, 0x1c, 0x27, 0x13, 0x8c, 0x58, 0xa7, 0x5b, 1045 0x52, 0x3e, 0x27, 0xa0, 0xe7, 0x7f, 0x5c, 0xea, 0x3b, 0xfc, 0x3e, 0xf6,
1040 0x78, 0x56, 0x87, 0x59, 0x6c, 0x1c, 0x50, 0x8e, 0x27, 0x7e, 0x6f, 0xc5, 1046 0x61, 0xbf, 0xfd, 0xba, 0x93, 0x0b, 0x46, 0xb4, 0x9c, 0xfb, 0x7d, 0x3d,
1041 0x9c, 0x58, 0x42, 0x7f, 0xd2, 0x35, 0x05, 0x01, 0xb7, 0x11, 0x0a, 0x1c, 1047 0xbf, 0xc3, 0x5f, 0x61, 0x3e, 0x88, 0xe7, 0xed, 0x37, 0xe7, 0x94, 0xcb,
1042 0x25, 0xfb, 0xa4, 0x6d, 0x28, 0x93, 0xd9, 0x75, 0xca, 0x5b, 0xd9, 0x1e, 1048 0x15, 0xfb, 0x7a, 0x69, 0x7f, 0xfe, 0xb7, 0x93, 0x0c, 0xb9, 0xfd, 0xf1,
1043 0xe5, 0x44, 0x56, 0xea, 0x1e, 0x50, 0xde, 0xcc, 0x4a, 0xec, 0xa9, 0x0b, 1049 0xd7, 0xb0, 0x8d, 0xcf, 0x0c, 0xb0, 0x8d, 0x4c, 0xb9, 0x3f, 0x40, 0x20,
1044 0x1c, 0x61, 0x2c, 0x65, 0x1c, 0x57, 0xbb, 0xc9, 0xda, 0x36, 0xe8, 0x15, 1050 0x2d, 0x71, 0x38, 0xa2, 0x2d, 0x50, 0x9a, 0x8d, 0x01, 0x25, 0x12, 0xbb,
1045 0xe4, 0x8e, 0x5a, 0x78, 0x90, 0xfd, 0xdd, 0x13, 0x85, 0xbe, 0x51, 0x77, 1051 0x57, 0x69, 0x4d, 0x8c, 0x91, 0x5f, 0x6e, 0x47, 0xb1, 0x4f, 0xd1, 0x7c,
1046 0x61, 0xd2, 0x0b, 0x4f, 0xb7, 0xee, 0x94, 0x6b, 0xc6, 0x34, 0xa9, 0x5b, 1052 0xb1, 0x3f, 0x0b, 0xf2, 0x50, 0x3c, 0x03, 0x08, 0xcc, 0xd7, 0x17, 0x62,
1047 0x17, 0x58, 0x9f, 0x3d, 0x47, 0xbf, 0xc8, 0x5d, 0xef, 0x89, 0x16, 0xee, 1053 0xb3, 0x3b, 0xa7, 0x50, 0xc2, 0x03, 0x1a, 0x6a, 0xc9, 0x5f, 0xc2, 0x13,
1048 0x7d, 0x64, 0x8d, 0x2f, 0x53, 0x79, 0xfd, 0xa2, 0x8c, 0x9b, 0x75, 0xa7, 1054 0xc0, 0xe4, 0x10, 0xb9, 0x5c, 0xbc, 0x19, 0x9f, 0x63, 0x2c, 0x98, 0xc7,
1049 0x72, 0x45, 0x89, 0xdb, 0x2a, 0xb9, 0x69, 0x15, 0x4c, 0x6f, 0xd0, 0xcc, 1055 0x32, 0x5f, 0x0c, 0x9e, 0xc7, 0x2f, 0xa5, 0xdf, 0x26, 0xc0, 0xcc, 0x29,
1050 0x60, 0x09, 0x7d, 0xe7, 0x30, 0xb9, 0xac, 0x9f, 0x71, 0x69, 0x09, 0xb1, 1056 0xf2, 0xb2, 0xd4, 0x7f, 0x41, 0x52, 0xee, 0x3d, 0x6e, 0x43, 0xc9, 0xd8,
1051 0x54, 0x78, 0x98, 0xc2, 0xe7, 0x1e, 0xdc, 0x92, 0xf8, 0x87, 0x3c, 0xc7, 1057 0x91, 0x3d, 0x80, 0x3e, 0x15, 0xf7, 0x24, 0xef, 0x0f, 0x63, 0x33, 0x4e,
1052 0x65, 0x6c, 0xae, 0x71, 0x08, 0x9f, 0xf4, 0xca, 0xdc, 0x1e, 0x4c, 0x4d, 1058 0xc7, 0xa3, 0xa9, 0x82, 0x12, 0x35, 0x86, 0x14, 0xc3, 0xbf, 0x8d, 0xed,
1053 0xe5, 0x7e, 0x75, 0x81, 0x93, 0xec, 0x77, 0x89, 0xa6, 0x85, 0x4b, 0x94, 1059 0xed, 0x60, 0x99, 0xed, 0xbc, 0x1e, 0x88, 0xea, 0x5d, 0x77, 0x28, 0xc9,
1054 0xba, 0xc0, 0x5b, 0xd9, 0x25, 0xf4, 0xcd, 0x77, 0xd9, 0xae, 0x07, 0x6f, 1060 0x2b, 0xab, 0x58, 0xe6, 0xa4, 0x11, 0x25, 0xcf, 0x8c, 0x4e, 0xaf, 0x82,
1055 0x25, 0x2a, 0xc8, 0x6b, 0x83, 0x31, 0x93, 0x02, 0x6f, 0x25, 0x2f, 0x20, 1061 0xe1, 0x7f, 0x22, 0x2f, 0xb2, 0x12, 0xca, 0x96, 0xc2, 0xe3, 0x6a, 0x11,
1056 0xbf, 0x98, 0xf2, 0xd7, 0x06, 0xc6, 0x5a, 0x89, 0x87, 0xea, 0xa2, 0x79, 1062 0x8f, 0x7e, 0x5d, 0xd2, 0xd9, 0x49, 0xf9, 0xee, 0xb6, 0xed, 0x1d, 0x68,
1057 0xcd, 0x58, 0x95, 0x85, 0x73, 0x65, 0xd4, 0xc0, 0xbd, 0x8c, 0xa3, 0xf7, 1063 0xaa, 0xf9, 0xed, 0x7b, 0xda, 0x9c, 0x8b, 0xef, 0xb5, 0x06, 0x47, 0xe9,
1058 0x33, 0x36, 0xad, 0x66, 0xdc, 0xd9, 0x12, 0xe1, 0xd8, 0xaa, 0x2c, 0xab, 1064 0x7f, 0x1e, 0xbd, 0x8a, 0x73, 0x27, 0xfc, 0x28, 0x19, 0xf3, 0x41, 0xee,
1059 0x58, 0xeb, 0x14, 0x8e, 0x8c, 0x24, 0xe3, 0xde, 0x3d, 0x9a, 0x13, 0xeb, 1065 0x79, 0x90, 0xf3, 0x26, 0xc3, 0x1e, 0x7c, 0xe0, 0x24, 0x57, 0xcb, 0xbd,
1060 0xf8, 0xfb, 0xc5, 0xec, 0x7f, 0x58, 0xf7, 0x93, 0xa3, 0x3f, 0x7b, 0x91, 1066 0x6a, 0xa4, 0xba, 0x5b, 0xc3, 0x5e, 0xb4, 0x26, 0xb6, 0x12, 0x0b, 0x8e,
1061 0x4c, 0xa8, 0x43, 0x5a, 0x43, 0x78, 0x3d, 0xe3, 0x1e, 0xe5, 0x9a, 0x15, 1067 0xaf, 0x5e, 0xc6, 0x67, 0x51, 0xe3, 0x39, 0x34, 0x6b, 0x5b, 0x21, 0x9f,
1062 0x86, 0x65, 0x5d, 0x1b, 0x0a, 0xc6, 0x5c, 0x8a, 0x8e, 0x43, 0x23, 0x93, 1068 0xcf, 0xd2, 0x66, 0x97, 0x49, 0x5d, 0x96, 0x29, 0x72, 0x1f, 0xc1, 0x9a,
1063 0x56, 0x60, 0xba, 0xf0, 0xf3, 0x42, 0x6c, 0x90, 0xb1, 0x16, 0xf8, 0x9f, 1069 0x2d, 0x86, 0x83, 0xe7, 0x0d, 0x58, 0x95, 0xe6, 0x41, 0xe5, 0x84, 0xfd,
1064 0x70, 0xbd, 0xa9, 0x3e, 0xad, 0xe2, 0xd6, 0x01, 0xe1, 0xa6, 0x7e, 0x2c, 1070 0x1b, 0x27, 0xe9, 0xc5, 0x4a, 0xfa, 0xa5, 0x41, 0xda, 0xab, 0xf9, 0xcd,
1065 0x4d, 0x7c, 0x0b, 0x87, 0x1a, 0x9d, 0x68, 0x25, 0x6f, 0x5f, 0x94, 0xf0, 1071 0xa8, 0x76, 0x94, 0x99, 0x82, 0xc7, 0xb4, 0x94, 0xe3, 0xf9, 0x2d, 0xca,
1066 0xe0, 0x2e, 0x62, 0xe0, 0xe2, 0x44, 0x31, 0xe7, 0xc6, 0x87, 0xdb, 0x12, 1072 0xeb, 0xf9, 0x7e, 0xe5, 0x54, 0x5e, 0xea, 0x1e, 0x54, 0x4e, 0xe6, 0x25,
1067 0x4e, 0x1c, 0x6e, 0x9c, 0x06, 0xd3, 0x57, 0x8c, 0xf7, 0x74, 0x07, 0x8e, 1073 0x1e, 0x36, 0x69, 0x47, 0xc8, 0x6f, 0xc8, 0xa9, 0xd4, 0x3e, 0x03, 0xca,
1068 0xe8, 0x5e, 0x64, 0x6c, 0x7f, 0xd8, 0x42, 0xec, 0x0a, 0xe6, 0xf9, 0xa2, 1074 0x36, 0xa3, 0x96, 0x3c, 0x5f, 0x8f, 0x8d, 0xb0, 0xbf, 0xfb, 0x3b, 0x60,
1069 0xe8, 0xd0, 0x41, 0x7d, 0xaa, 0x88, 0x9f, 0xd7, 0xe1, 0xe5, 0xb8, 0x60, 1075 0x6c, 0x37, 0x7c, 0x38, 0x1e, 0x44, 0xa0, 0xcf, 0xf0, 0xca, 0x77, 0xe6,
1070 0x81, 0x07, 0x7e, 0x68, 0xc5, 0xa7, 0x4b, 0x7d, 0x98, 0x1e, 0x43, 0xc6, 1076 0x03, 0x52, 0xb7, 0x49, 0xdb, 0x9a, 0x3f, 0x47, 0xff, 0x2a, 0x7e, 0xdf,
1071 0x21, 0x5c, 0x4a, 0x47, 0xf7, 0x48, 0x8c, 0x9c, 0x67, 0xea, 0x50, 0x4f, 1077 0xdf, 0x51, 0xbe, 0xf7, 0x0b, 0x67, 0x6a, 0xb5, 0xca, 0xef, 0x7f, 0xea,
1072 0x93, 0xc7, 0x55, 0xe2, 0x75, 0x4d, 0x78, 0xdc, 0x2b, 0xf0, 0xd2, 0x77, 1078 0xe1, 0x50, 0x58, 0x77, 0x26, 0x3f, 0x17, 0x2e, 0xa5, 0x92, 0x3f, 0xd6,
1073 0x7b, 0x46, 0x42, 0x1d, 0xa7, 0x15, 0x07, 0x5e, 0xd4, 0x2a, 0xe2, 0x6e, 1079 0xc3, 0x0a, 0x46, 0xac, 0x1c, 0x73, 0x85, 0xbe, 0x4c, 0x3b, 0xfd, 0x2d,
1074 0xfa, 0xf4, 0xc6, 0x11, 0x38, 0xd7, 0xcf, 0xd3, 0xd1, 0x3b, 0xd2, 0xd5, 1080 0xcc, 0x58, 0x99, 0x24, 0xbe, 0x93, 0xf7, 0xb2, 0xcd, 0x0a, 0x3d, 0x80,
1075 0x5c, 0x0e, 0x12, 0x9b, 0x79, 0x39, 0xfe, 0xf1, 0x65, 0xea, 0x76, 0x45, 1081 0x9b, 0xec, 0x66, 0x4f, 0x51, 0x7f, 0x2a, 0x31, 0xcc, 0xc3, 0x98, 0x2e,
1076 0xc4, 0xe6, 0x1f, 0xb9, 0xd8, 0xeb, 0xb5, 0x2c, 0xe6, 0x0c, 0xd4, 0x33, 1082 0x1c, 0xef, 0x52, 0xce, 0xdd, 0xa4, 0xbd, 0xc5, 0x7e, 0x57, 0xe9, 0x7a,
1077 0xb0, 0x2f, 0xaf, 0xe3, 0x3d, 0xfc, 0xdd, 0x93, 0xd7, 0xf1, 0x3a, 0xca, 1083 0xac, 0x4a, 0x69, 0xd2, 0x5e, 0xcf, 0x27, 0xe9, 0xe3, 0x3d, 0x6c, 0x37,
1078 0xa3, 0xff, 0x61, 0xc3, 0x45, 0x9c, 0x21, 0x80, 0x62, 0x43, 0x30, 0x88, 1084 0x80, 0xd7, 0xed, 0x5a, 0xe6, 0x20, 0x91, 0xa4, 0x45, 0x81, 0x37, 0x77,
1079 0xf8, 0x49, 0x3c, 0x89, 0x51, 0xc7, 0xcf, 0x65, 0x7f, 0xc7, 0xb1, 0x06, 1085 0x84, 0x41, 0xce, 0x37, 0xe3, 0xaf, 0x1b, 0x8c, 0xff, 0x12, 0xa3, 0xd5,
1080 0x39, 0xdd, 0x62, 0x4f, 0x8c, 0x85, 0xea, 0x67, 0x1c, 0xc4, 0x55, 0xea, 1086 0x5b, 0x96, 0x24, 0xb0, 0x3e, 0x0f, 0xef, 0xba, 0x0e, 0x13, 0xf7, 0x30,
1081 0x41, 0xf4, 0x2c, 0xfa, 0xb5, 0xac, 0x7e, 0x5d, 0x74, 0x2c, 0xfa, 0x16, 1087 0xb6, 0xdf, 0xc7, 0x78, 0xf9, 0x20, 0x63, 0xe1, 0x8e, 0x38, 0xc7, 0x56,
1082 0xbd, 0xe7, 0xf0, 0x93, 0x7c, 0xbf, 0x07, 0x48, 0xb3, 0xac, 0x83, 0x78, 1088 0xef, 0x38, 0x95, 0xfa, 0x66, 0xc9, 0x67, 0x30, 0xc0, 0x58, 0x7c, 0x37,
1083 0x69, 0xe0, 0xbb, 0x6d, 0x62, 0x3b, 0xe5, 0x76, 0x8c, 0x9b, 0x33, 0xd3, 1089 0xe3, 0xcb, 0x16, 0x7e, 0x7e, 0x29, 0xff, 0x1f, 0xce, 0x7d, 0xcc, 0xa7,
1084 0xb2, 0x9e, 0x8a, 0x04, 0xf0, 0xbe, 0xd6, 0xd0, 0xdc, 0xa4, 0x06, 0xd9, 1090 0x9e, 0xbf, 0x48, 0x26, 0xd4, 0x51, 0xbd, 0x35, 0xb6, 0x95, 0xb1, 0x98,
1085 0xd7, 0x25, 0x48, 0x8c, 0xc5, 0x38, 0x77, 0x57, 0x93, 0x87, 0x8b, 0xad, 1091 0x72, 0xad, 0x5a, 0xd3, 0x71, 0xae, 0x8c, 0x46, 0x92, 0x3e, 0xc5, 0xc0,
1086 0xa1, 0xa3, 0xc8, 0xc6, 0x5c, 0xe0, 0x44, 0x42, 0x0b, 0x6f, 0xe0, 0x9c, 1092 0x73, 0x13, 0xc7, 0x1d, 0x6d, 0x8e, 0xe4, 0x52, 0xe5, 0x38, 0x28, 0x63,
1087 0xed, 0xf6, 0x2d, 0x23, 0x67, 0x52, 0x5b, 0x98, 0xb5, 0x90, 0xab, 0x68, 1093 0x95, 0x1c, 0x41, 0xf0, 0x41, 0xf2, 0x84, 0x99, 0x18, 0xa1, 0xe2, 0xe6,
1088 0xe6, 0x26, 0xbc, 0x6b, 0x65, 0x7c, 0x16, 0xe3, 0x9b, 0x0a, 0xa7, 0x36, 1094 0x61, 0xc9, 0x13, 0xc2, 0x58, 0x65, 0x7f, 0x09, 0xcf, 0xb5, 0x79, 0xd1,
1089 0x03, 0x87, 0xbd, 0x0e, 0x3c, 0x1f, 0xae, 0x41, 0xac, 0x4a, 0x41, 0x99, 1095 0xc5, 0x1c, 0xeb, 0x16, 0x3b, 0x80, 0x3b, 0x88, 0xa5, 0x2b, 0x6c, 0xe6,
1090 0xf6, 0x4b, 0xeb, 0x05, 0x9f, 0xb4, 0xc3, 0x7c, 0x43, 0xfd, 0x39, 0xfb, 1096 0x4e, 0xc1, 0x10, 0x6e, 0xb5, 0xbd, 0x38, 0xdc, 0xc6, 0x1c, 0x28, 0x54,
1091 0xad, 0xb0, 0x8c, 0xc8, 0x5d, 0x86, 0xae, 0xb1, 0x4b, 0xdb, 0xff, 0x85, 1097 0x89, 0x77, 0x0d, 0x0f, 0x8e, 0x18, 0x41, 0xe4, 0x5c, 0x7f, 0xd8, 0x41,
1092 0x35, 0xe9, 0x93, 0xf6, 0x83, 0xde, 0x80, 0xfa, 0x49, 0x73, 0xf8, 0xaa, 1098 0x0c, 0xa4, 0x1e, 0x55, 0xc9, 0x1d, 0x44, 0x87, 0x1e, 0xea, 0x53, 0x45,
1093 0xf5, 0x5a, 0x4e, 0xa6, 0x1d, 0x7f, 0xa0, 0x8a, 0xbc, 0xc7, 0x39, 0x3e, 1099 0xea, 0xbc, 0x0e, 0x3f, 0x2c, 0x17, 0x90, 0x7e, 0x49, 0x3e, 0xf0, 0x33,
1094 0x91, 0x59, 0x68, 0x47, 0xfc, 0x6c, 0x3f, 0xef, 0xc9, 0x33, 0xb1, 0x91, 1100 0x27, 0x35, 0x47, 0xea, 0xc3, 0x0a, 0x98, 0x32, 0x0e, 0xe1, 0xb7, 0x06,
1095 0x75, 0x6c, 0xf7, 0x90, 0x85, 0x1a, 0xb9, 0xde, 0x6c, 0x97, 0x35, 0xc7, 1101 0xfa, 0x26, 0x3a, 0xc8, 0xed, 0x66, 0x0e, 0xf5, 0x0c, 0xb9, 0x75, 0x1d,
1096 0x26, 0x16, 0x3b, 0x31, 0x1f, 0xb3, 0x22, 0x0b, 0x16, 0xca, 0x58, 0x54, 1102 0x5e, 0xd3, 0x85, 0x5b, 0xbf, 0x8a, 0x20, 0x7d, 0xb7, 0x7f, 0x22, 0xba,
1097 0x23, 0x16, 0x70, 0xc3, 0xac, 0x71, 0x10, 0x8b, 0xdf, 0x6e, 0x6c, 0xc4, 1103 0xe1, 0x8c, 0xe2, 0xc1, 0x4b, 0x7a, 0x2d, 0x79, 0x9f, 0x89, 0xed, 0x13,
1098 0xc2, 0xec, 0xa4, 0xf5, 0x2e, 0xc1, 0xa5, 0x4b, 0x73, 0x60, 0x9c, 0xe3, 1104 0xf0, 0x6e, 0x5d, 0x62, 0x20, 0x3d, 0xd1, 0x9b, 0x98, 0xc5, 0xb4, 0xd7,
1099 0xdb, 0xaf, 0x4b, 0x6e, 0x68, 0x61, 0x51, 0xc4, 0x8c, 0xd3, 0x63, 0xcd, 1105 0xbb, 0xa4, 0xc8, 0x89, 0x3e, 0x43, 0xdd, 0xae, 0x8d, 0xbb, 0x9c, 0xa8,
1100 0x72, 0xda, 0x4e, 0xa9, 0x26, 0xf1, 0xb9, 0x02, 0x65, 0x86, 0x33, 0xfc, 1106 0xc8, 0x07, 0x82, 0x8e, 0x73, 0x52, 0x17, 0x3d, 0x03, 0x07, 0x4a, 0x3a,
1101 0x2e, 0x82, 0xfa, 0x16, 0xf2, 0x93, 0x40, 0xd5, 0xac, 0x66, 0x17, 0xb5, 1107 0xde, 0xcf, 0xcf, 0xfd, 0x25, 0x1d, 0x6f, 0xa1, 0x3c, 0xfa, 0x1f, 0xb6,
1102 0xfb, 0x52, 0x22, 0xd4, 0x7c, 0x44, 0xc9, 0xf9, 0xc3, 0x73, 0x9c, 0xdb, 1108 0x5d, 0xc4, 0x63, 0x34, 0x54, 0x9a, 0xc2, 0x6f, 0x88, 0xc3, 0xc4, 0x93,
1103 0xd7, 0x13, 0xda, 0x9a, 0x62, 0x47, 0xee, 0xfa, 0xe5, 0xac, 0xe4, 0x23, 1109 0x24, 0x75, 0xfc, 0x42, 0x7e, 0xbd, 0xe0, 0x36, 0xa7, 0xbb, 0xdd, 0xc5,
1104 0x05, 0x7f, 0xf0, 0xe7, 0x71, 0xc3, 0xed, 0x3e, 0x91, 0xc0, 0x69, 0x95, 1110 0xef, 0xa4, 0x7a, 0x80, 0x76, 0x20, 0x7a, 0x78, 0xad, 0x94, 0xdb, 0x38,
1105 0xf8, 0x53, 0x65, 0xe0, 0x74, 0xb7, 0x9e, 0x51, 0x5c, 0x5a, 0x05, 0x71, 1111 0xce, 0x90, 0x21, 0x3a, 0x2e, 0xe7, 0x65, 0xa2, 0xeb, 0x36, 0xc9, 0xb1,
1106 0x55, 0xb0, 0xb4, 0x88, 0x31, 0x41, 0x62, 0xb6, 0xdb, 0xfd, 0x2e, 0xcb, 1112 0xfa, 0x81, 0xdf, 0xb0, 0xac, 0x87, 0xb8, 0x6b, 0xe2, 0x6b, 0xdd, 0x62,
1107 0x2c, 0x8e, 0x60, 0x32, 0x7c, 0x63, 0x43, 0xb3, 0x1b, 0x31, 0xb3, 0x98, 1113 0x3b, 0xb3, 0xdc, 0x58, 0x79, 0xd5, 0x42, 0xc7, 0xf9, 0x4a, 0x5c, 0xc3,
1108 0x7e, 0x59, 0x6e, 0xf8, 0xdc, 0x73, 0x46, 0xcd, 0x1a, 0x0f, 0xed, 0xba, 1114 0x7b, 0x7a, 0x6b, 0xa2, 0x5d, 0x8d, 0xb0, 0xaf, 0x49, 0xd8, 0x93, 0x1d,
1109 0xcc, 0x40, 0xcb, 0xac, 0xde, 0xd6, 0x4a, 0x54, 0x34, 0x62, 0xf5, 0x88, 1115 0x9c, 0xbb, 0x2b, 0x90, 0x0c, 0x89, 0xad, 0x61, 0x43, 0x45, 0x11, 0xc3,
1110 0xe4, 0x96, 0x7d, 0x35, 0x2a, 0xfb, 0xea, 0xd2, 0xca, 0xe1, 0xaa, 0x5e, 1116 0x71, 0xca, 0xd6, 0x63, 0xdb, 0x38, 0x67, 0xfb, 0x42, 0x5d, 0xe4, 0x71,
1111 0x3d, 0x5f, 0x35, 0x7e, 0x80, 0xb6, 0xa8, 0xbb, 0x45, 0x1f, 0x9d, 0x9a, 1117 0x6a, 0x27, 0xd3, 0x7f, 0xf2, 0x27, 0xdd, 0x7a, 0x04, 0xef, 0x38, 0xb9,
1112 0xe3, 0x08, 0x46, 0x9a, 0x35, 0x95, 0xc4, 0xc7, 0x0a, 0x43, 0xf2, 0x9b, 1118 0x90, 0xc3, 0x38, 0x29, 0xb9, 0xd1, 0x7c, 0x1c, 0x0e, 0x7a, 0xf0, 0x62,
1113 0x40, 0xcb, 0xcb, 0x36, 0x7e, 0x7a, 0xc9, 0xc7, 0x7f, 0xe6, 0xff, 0xf3, 1119 0xac, 0x11, 0xc9, 0x7a, 0x05, 0x35, 0xfa, 0x9b, 0xce, 0x77, 0x42, 0xd2,
1114 0xeb, 0x3c, 0x4f, 0x1d, 0x4b, 0x9b, 0xf2, 0x2d, 0xb9, 0x26, 0x9c, 0xcc, 1120 0x0e, 0x73, 0x3c, 0xf5, 0x56, 0x8f, 0xe4, 0x80, 0x5e, 0x5d, 0xe4, 0x76,
1115 0x1d, 0xd1, 0x35, 0xec, 0x61, 0x7e, 0x21, 0x73, 0x03, 0x77, 0x91, 0x11, 1121 0x31, 0xc7, 0xbd, 0xb4, 0xfd, 0x7f, 0x75, 0x8e, 0x87, 0xa4, 0xfd, 0x48,
1116 0xfe, 0xcb, 0x67, 0xe9, 0x17, 0x2e, 0xea, 0x78, 0x93, 0x66, 0x12, 0xce, 1122 0x50, 0x53, 0x7f, 0xd7, 0x1c, 0x7e, 0xdf, 0xf9, 0x81, 0x2b, 0x33, 0xe3,
1117 0x2d, 0x4b, 0x8b, 0x04, 0xfd, 0x45, 0x4a, 0x00, 0x1b, 0x1b, 0x7f, 0x47, 1123 0xea, 0x01, 0xaa, 0xc8, 0x23, 0x54, 0x54, 0x8b, 0xcc, 0x72, 0x3b, 0xe2,
1118 0x5b, 0x00, 0xf1, 0x0a, 0x24, 0xab, 0x35, 0x58, 0x37, 0x5c, 0x31, 0xa5, 1124 0x67, 0x73, 0x79, 0x4f, 0x9e, 0x89, 0x8d, 0x6c, 0x61, 0xbb, 0xcf, 0x39,
1119 0xde, 0xbe, 0xf3, 0xf5, 0x92, 0x9a, 0x19, 0x97, 0x7a, 0x43, 0x91, 0x60, 1125 0x68, 0x94, 0xef, 0xd3, 0x1e, 0x29, 0x6b, 0x4d, 0x1e, 0x5a, 0xe1, 0xc5,
1120 0xfb, 0x06, 0xd6, 0xdb, 0xcc, 0x7a, 0x31, 0xc6, 0xc8, 0x7b, 0xe9, 0x9b, 1126 0x52, 0xb4, 0xc4, 0x97, 0x2d, 0x97, 0xb1, 0xa8, 0x66, 0x52, 0xf3, 0xc3,
1121 0x2e, 0xe6, 0x37, 0xeb, 0x99, 0xeb, 0x4c, 0x69, 0xef, 0xaf, 0x0a, 0xf5, 1127 0x6a, 0xf4, 0x10, 0x8b, 0xdf, 0x68, 0x6b, 0xc3, 0x72, 0xe6, 0x8c, 0xef,
1122 0x1e, 0xd5, 0xcc, 0x71, 0xbb, 0xbd, 0xb9, 0xc1, 0x35, 0x45, 0x8e, 0x00, 1128 0x10, 0x5c, 0x7a, 0x75, 0x0f, 0xa6, 0x38, 0xbe, 0x27, 0x0d, 0x59, 0x2f,
1123 0x7a, 0x59, 0x6f, 0x9c, 0xf5, 0xde, 0x1a, 0xa9, 0xce, 0x97, 0x77, 0x62, 1129 0x70, 0x70, 0x4b, 0xdc, 0x4a, 0xd1, 0x63, 0xad, 0x59, 0xb4, 0x9d, 0x6a,
1124 0xc3, 0xac, 0x5c, 0xd9, 0x1e, 0xcd, 0xf4, 0x4b, 0x59, 0x67, 0x24, 0xd8, 1130 0x5d, 0xe2, 0x7c, 0x2d, 0x6a, 0x4c, 0x6f, 0xec, 0x1d, 0x44, 0x8c, 0x1d,
1125 0x7c, 0x1f, 0xb1, 0xba, 0x4b, 0xda, 0x60, 0xdf, 0xde, 0xb2, 0xe3, 0x0a, 1131 0xe4, 0x39, 0x5a, 0x7d, 0x4b, 0xc2, 0x47, 0xed, 0xbe, 0x6c, 0x47, 0x13,
1126 0x6e, 0x7a, 0x21, 0x91, 0x9a, 0x74, 0x6a, 0x5a, 0xdb, 0x4a, 0x25, 0xa6, 1132 0x47, 0x94, 0xa2, 0x3f, 0xbc, 0xc0, 0xb9, 0x7d, 0xcd, 0xd6, 0x37, 0x56,
1127 0x2c, 0x9e, 0x67, 0xcf, 0xef, 0x4d, 0xc7, 0xb2, 0x9d, 0xd8, 0xa8, 0x4d, 1133 0x7a, 0x8a, 0xdf, 0x5f, 0x71, 0xf3, 0xd1, 0xb2, 0x3f, 0x84, 0x4b, 0xb8,
1128 0x44, 0x8a, 0x59, 0xef, 0x88, 0x36, 0xe1, 0x77, 0xd1, 0xd7, 0x56, 0xb2, 1134 0xe1, 0xf7, 0x9f, 0xb2, 0x71, 0x86, 0x54, 0x88, 0x79, 0x29, 0xce, 0xf4,
1129 0xed, 0x2e, 0xe6, 0x15, 0x2a, 0x7d, 0x7b, 0xdd, 0xb0, 0xf0, 0x01, 0x9d, 1135 0x19, 0x53, 0x8a, 0x4f, 0xaf, 0x25, 0xae, 0x0a, 0x96, 0x56, 0x90, 0x13,
1130 0x7c, 0xa3, 0x8e, 0x76, 0x28, 0xfa, 0x91, 0x36, 0x65, 0x9e, 0x45, 0x17, 1136 0x4a, 0xec, 0xf7, 0xfb, 0xdf, 0x61, 0x19, 0x72, 0xba, 0xe3, 0xb1, 0xeb,
1131 0xc1, 0xf0, 0xb0, 0xad, 0x0b, 0xa5, 0x7a, 0x5f, 0x23, 0x8d, 0xa5, 0x8a, 1137 0x5b, 0x13, 0x7e, 0x24, 0xad, 0x4a, 0xfa, 0xe5, 0x2c, 0x33, 0xe4, 0xbf,
1132 0xfc, 0xab, 0x51, 0x62, 0xa2, 0x42, 0x3c, 0xbe, 0x12, 0x1b, 0xec, 0x3c, 1138 0xaa, 0x60, 0x35, 0x06, 0x68, 0xd7, 0x35, 0xcc, 0x57, 0x5b, 0xd2, 0x13,
1133 0xad, 0x8e, 0x5c, 0xc7, 0xb2, 0xf6, 0xe8, 0x96, 0xf5, 0xac, 0x3e, 0x03, 1139 0x8c, 0xe1, 0x6d, 0x78, 0x70, 0x82, 0x23, 0x6b, 0x18, 0x6c, 0x54, 0x4d,
1134 0xfb, 0xf4, 0x60, 0x5c, 0x6c, 0xf3, 0x97, 0xfa, 0x82, 0x6b, 0x5d, 0x08, 1140 0x59, 0x83, 0x08, 0xc2, 0xd7, 0xf0, 0xe0, 0x0d, 0xaa, 0x79, 0x1c, 0x3d,
1135 0x32, 0xe1, 0xff, 0x14, 0xc6, 0x69, 0x2f, 0x25, 0x9a, 0xf8, 0xa0, 0x02, 1141 0x1d, 0xfe, 0xce, 0x44, 0x01, 0xfe, 0x7a, 0x73, 0x13, 0xe2, 0x69, 0xc9,
1136 0x7f, 0xc8, 0x19, 0x28, 0x53, 0x2c, 0xb8, 0xe7, 0xce, 0x5c, 0x33, 0x93, 1142 0x3b, 0x05, 0x23, 0x93, 0x5b, 0x89, 0x5a, 0x8d, 0x75, 0xd7, 0x96, 0xf5,
1137 0x7a, 0xaa, 0xb8, 0x51, 0xc1, 0x07, 0x73, 0x14, 0x4c, 0xcc, 0x09, 0xf9, 1143 0x0d, 0xb5, 0xd6, 0x94, 0xfc, 0x53, 0xeb, 0x7c, 0xc5, 0xc5, 0xd2, 0x20,
1138 0x07, 0x95, 0x72, 0xe2, 0x6d, 0xa8, 0xad, 0x45, 0x31, 0x8f, 0xb2, 0x6e, 1144 0xf3, 0x85, 0x1f, 0x87, 0xff, 0xcf, 0xea, 0x27, 0x38, 0x27, 0xd2, 0x17,
1139 0xac, 0xd1, 0xc1, 0x7c, 0x5a, 0xa9, 0x24, 0x16, 0xcc, 0x0a, 0x08, 0x1d, 1145 0xf9, 0x2f, 0x79, 0x3f, 0xbc, 0x2a, 0xb1, 0xb0, 0x77, 0xdc, 0xcb, 0xfc,
1140 0x70, 0x26, 0x43, 0xfe, 0xcd, 0xfc, 0x76, 0x8c, 0x28, 0x18, 0xd1, 0x82, 1146 0x4a, 0xe6, 0x4c, 0xe2, 0xf1, 0x6b, 0xff, 0xf5, 0x79, 0xfa, 0x8b, 0x8f,
1141 0x31, 0xd8, 0xf2, 0xd9, 0x76, 0x44, 0xc1, 0x75, 0x21, 0xcb, 0x3a, 0x16, 1147 0xba, 0x7f, 0x44, 0xb7, 0x08, 0xf3, 0x8e, 0xa3, 0xc7, 0x23, 0xe1, 0x0a,
1142 0x69, 0xf0, 0x1e, 0xc3, 0x2f, 0x2d, 0x59, 0x4b, 0xf1, 0x87, 0xce, 0xe7, 1148 0x45, 0xc3, 0xf6, 0xb6, 0x7f, 0xa7, 0x8d, 0x80, 0x38, 0x06, 0x12, 0xeb,
1143 0x06, 0x28, 0x4d, 0x6a, 0xb1, 0x16, 0x65, 0xbb, 0x53, 0x38, 0xc5, 0xaa, 1149 0x5a, 0x6c, 0x19, 0xaf, 0x98, 0x51, 0xaf, 0x67, 0x4d, 0xb9, 0xde, 0x80,
1144 0xac, 0xc4, 0xc8, 0x42, 0x7f, 0x0b, 0xb1, 0xd2, 0xb2, 0x7e, 0xa9, 0xe7, 1150 0x6e, 0xa5, 0xa4, 0xde, 0x68, 0x3c, 0xd2, 0xb3, 0x8d, 0xf5, 0x1e, 0x65,
1145 0x64, 0x79, 0xa3, 0xc2, 0xcd, 0x66, 0x60, 0x4c, 0x0b, 0xb6, 0x8e, 0x53, 1151 0xbd, 0x24, 0x63, 0xe7, 0x3d, 0x13, 0x41, 0x37, 0x9f, 0xb3, 0xc6, 0xab,
1146 0x07, 0x7e, 0xfa, 0x60, 0x2d, 0xe7, 0x7d, 0xd2, 0x15, 0xf4, 0x4e, 0x2a, 1152 0x67, 0xb6, 0x77, 0xbe, 0xde, 0xe3, 0xba, 0x35, 0xe5, 0xb6, 0xb7, 0x38,
1147 0x0b, 0xcf, 0xaa, 0x98, 0xbd, 0xea, 0x31, 0xa5, 0xa1, 0xa3, 0x04, 0x5a, 1153 0xb2, 0xb1, 0xc2, 0xe3, 0x45, 0x9a, 0xf5, 0xa6, 0x58, 0xef, 0xf5, 0x09,
1148 0x6c, 0x54, 0xb9, 0x82, 0x3a, 0x31, 0xfd, 0x1e, 0x04, 0xbd, 0x2b, 0x61, 1154 0x59, 0x8f, 0xc0, 0x0d, 0xe3, 0x76, 0xe6, 0xb8, 0x47, 0xd7, 0x83, 0x27,
1149 0xc7, 0x6d, 0xdc, 0x9e, 0x70, 0xc6, 0xce, 0xa0, 0x9e, 0xfe, 0xa0, 0xb5, 1155 0x91, 0x24, 0xe6, 0xba, 0x73, 0x79, 0xc3, 0x58, 0x7e, 0x33, 0xb6, 0xeb,
1150 0xdf, 0x4f, 0x6e, 0x07, 0x7c, 0x96, 0x84, 0x5f, 0xfa, 0x5a, 0x83, 0xf8, 1156 0x87, 0xe2, 0x95, 0xac, 0x77, 0x44, 0x3f, 0x14, 0xf6, 0xd1, 0xaf, 0xd6,
1151 0x5f, 0x58, 0xd6, 0x03, 0xec, 0xeb, 0x16, 0xf6, 0x75, 0x75, 0xe4, 0x7d, 1157 0x51, 0x5e, 0x2f, 0xf3, 0x1a, 0x95, 0xfe, 0xb2, 0x65, 0x5c, 0x62, 0xbf,
1152 0xeb, 0x17, 0xb6, 0xcc, 0x9b, 0x31, 0xa8, 0x5d, 0x2a, 0xf7, 0x3d, 0x0b, 1158 0x41, 0x5e, 0x12, 0xa2, 0xcd, 0xc9, 0x98, 0xa5, 0x5d, 0x99, 0x53, 0x19,
1153 0xd3, 0x45, 0xae, 0x0b, 0xb7, 0x4e, 0x67, 0xee, 0x11, 0x15, 0x2c, 0x79, 1159 0x5f, 0x24, 0x36, 0xee, 0x8e, 0x4f, 0x99, 0x7b, 0x40, 0x72, 0xdd, 0x7a,
1154 0x84, 0xf9, 0xb9, 0xc8, 0x63, 0x5c, 0x51, 0x2f, 0x8d, 0xcd, 0x0e, 0x30, 1160 0x0b, 0x7d, 0x6d, 0x12, 0xff, 0x14, 0x62, 0x6f, 0x03, 0xf3, 0x4f, 0x69,
1155 0xe6, 0xf9, 0xe3, 0x8a, 0x5a, 0x57, 0x06, 0x2f, 0xdc, 0x9a, 0x85, 0x07, 1161 0x23, 0x84, 0x6d, 0xf4, 0xed, 0xfd, 0x86, 0xe3, 0x3c, 0x6f, 0xcc, 0xc7,
1156 0xc9, 0x23, 0x62, 0xd3, 0x2b, 0xf1, 0x90, 0xee, 0x46, 0x79, 0x48, 0xbd, 1162 0x01, 0x23, 0x92, 0x12, 0x3b, 0x7c, 0xd3, 0x58, 0x76, 0xa5, 0xe4, 0x96,
1157 0xd2, 0xc1, 0x39, 0xd9, 0x17, 0x91, 0x6b, 0x17, 0xc6, 0xa7, 0x3b, 0xd0, 1163 0xc0, 0x9f, 0x60, 0x8a, 0xb6, 0x51, 0xa5, 0x8b, 0xbf, 0x29, 0x08, 0x47,
1158 0x49, 0x7e, 0xe1, 0x0d, 0xa9, 0xb5, 0x72, 0xdf, 0xdd, 0x24, 0xd7, 0xec, 1164 0xbd, 0x5a, 0x8d, 0xe2, 0xc0, 0xbf, 0x78, 0xe1, 0xc6, 0x85, 0x1c, 0x7b,
1159 0xff, 0x15, 0x0a, 0x1e, 0xa0, 0x55, 0xa8, 0xa1, 0x2e, 0xbf, 0xdc, 0x6f, 1165 0xed, 0xf5, 0x0a, 0xde, 0xbf, 0x4a, 0xc1, 0xa1, 0xab, 0xa2, 0xe1, 0x11,
1160 0xd5, 0xe5, 0x5a, 0x41, 0x7d, 0xc4, 0xc9, 0x79, 0xb1, 0xe0, 0x60, 0xdf, 1166 0x65, 0x16, 0xb1, 0x35, 0xda, 0xdd, 0xa9, 0x58, 0x47, 0x59, 0x37, 0xd9,
1161 0x4b, 0x43, 0xbc, 0x1f, 0x91, 0xdf, 0xb1, 0x07, 0x38, 0xee, 0xd8, 0x6e, 1167 0xe6, 0x89, 0x84, 0xa1, 0xd4, 0xd1, 0xef, 0x5b, 0x34, 0x09, 0xfd, 0xde,
1162 0x45, 0xb0, 0xe7, 0xc7, 0xd6, 0xf3, 0x8c, 0x2d, 0x5e, 0x3e, 0x7f, 0x88, 1168 0x81, 0x68, 0xf8, 0x51, 0xfe, 0xf7, 0x4c, 0x28, 0x98, 0xd0, 0x23, 0x49,
1163 0x6d, 0x1f, 0x8d, 0x3c, 0x6b, 0xd5, 0x12, 0x73, 0x8f, 0x35, 0x07, 0x30, 1169 0xb8, 0xf2, 0xd9, 0x36, 0xd3, 0xce, 0xab, 0xa3, 0x8e, 0x73, 0x2c, 0xde,
1164 0x63, 0x4e, 0x1d, 0x26, 0xef, 0x96, 0x31, 0x2b, 0x28, 0xd7, 0xca, 0x5d, 1170 0x1a, 0x3c, 0x86, 0x37, 0x89, 0x6d, 0xd2, 0x4e, 0x19, 0xeb, 0xc1, 0x5c,
1165 0x92, 0xe7, 0x55, 0x68, 0x57, 0xe0, 0xd6, 0xbb, 0x72, 0xf7, 0x4a, 0x28, 1171 0x56, 0x4f, 0x76, 0x2a, 0x8e, 0x57, 0xf8, 0xc3, 0xfa, 0xbc, 0xc4, 0xc3,
1166 0x2f, 0x4c, 0xdc, 0x2d, 0x99, 0x53, 0x8d, 0x40, 0xfe, 0xde, 0xc2, 0x90, 1172 0x72, 0x7f, 0xcb, 0x71, 0xd1, 0x71, 0xde, 0x34, 0x8a, 0xb2, 0x82, 0x1d,
1167 0xb3, 0xad, 0x5c, 0xd1, 0xbc, 0xb7, 0x2b, 0xf2, 0xfc, 0x37, 0xb4, 0x71, 1173 0x91, 0x14, 0x30, 0x1f, 0x93, 0x7a, 0xa4, 0x6b, 0x8a, 0x3a, 0x08, 0xd3,
1168 0xcb, 0x7a, 0x90, 0xf3, 0x35, 0x2b, 0xe2, 0xc1, 0x29, 0xb6, 0xd3, 0x45, 1174 0xdf, 0xe6, 0xe9, 0x8d, 0x38, 0xee, 0x8b, 0x04, 0x8f, 0x2b, 0xcb, 0xcf,
1169 0xfd, 0x2d, 0x39, 0x3f, 0x5f, 0x85, 0xfa, 0xbf, 0xb6, 0x02, 0x7f, 0x21, 1175 0xaa, 0x58, 0xb4, 0xfe, 0x09, 0xa5, 0x75, 0x43, 0x15, 0xf4, 0x64, 0x41,
1170 0x75, 0x45, 0xc6, 0xcc, 0xd6, 0x5b, 0x95, 0xe7, 0x9c, 0x92, 0x33, 0xac, 1176 0x99, 0x2b, 0x3a, 0x09, 0x07, 0xc8, 0xa5, 0xd6, 0xc1, 0x8d, 0xd1, 0xb8,
1171 0x8e, 0xd8, 0x3a, 0x63, 0xd9, 0x5a, 0x97, 0x5c, 0x7b, 0xa3, 0xaf, 0x9f, 1177 0xcd, 0xf6, 0x26, 0xa7, 0xd1, 0x4c, 0xdb, 0xd7, 0x7b, 0xee, 0x23, 0x0f,
1172 0x5f, 0x7f, 0x39, 0x6d, 0xc7, 0xa8, 0x05, 0x37, 0x7a, 0x31, 0x69, 0x55, 1178 0x04, 0x3e, 0xce, 0x24, 0x41, 0xfa, 0xda, 0x88, 0xd4, 0xa7, 0x1c, 0xe7,
1173 0x35, 0x99, 0xde, 0x62, 0x48, 0xac, 0xaa, 0x0f, 0x3f, 0x45, 0xb9, 0xaf, 1179 0x7e, 0xf6, 0x75, 0x07, 0xfb, 0xfa, 0x60, 0xfc, 0x3d, 0xe7, 0x5f, 0x5d,
1174 0xe9, 0xb9, 0x38, 0xb6, 0x47, 0x0f, 0xa6, 0x4d, 0xfa, 0x43, 0x9c, 0x39, 1180 0x99, 0x37, 0x62, 0x44, 0xbf, 0x54, 0xee, 0xbb, 0xcc, 0xf5, 0x45, 0xae,
1175 0x5f, 0x8b, 0xbd, 0x56, 0xb4, 0x87, 0xf3, 0x30, 0x03, 0xc5, 0x4d, 0xc1, 1181 0x0f, 0x37, 0xcf, 0x61, 0xbe, 0xd2, 0x21, 0xb8, 0x71, 0xd2, 0x4b, 0xdc,
1176 0x9e, 0x6b, 0x98, 0x03, 0x39, 0xa2, 0x12, 0xff, 0x64, 0x7e, 0xec, 0x32, 1182 0xa0, 0x3c, 0xc6, 0x10, 0xf5, 0xd2, 0x38, 0xec, 0x01, 0xe3, 0x5b, 0x38,
1177 0x6c, 0xab, 0x04, 0x0b, 0xd9, 0xc7, 0x48, 0xd3, 0x1f, 0x8b, 0x1d, 0x22, 1183 0xa5, 0xa8, 0x24, 0x42, 0x41, 0xf8, 0x75, 0x07, 0x0f, 0x90, 0x33, 0x24,
1178 0x47, 0xac, 0x33, 0xd8, 0x13, 0xc3, 0x1f, 0x2b, 0x0b, 0x46, 0x6a, 0xc4, 1184 0xe7, 0xd4, 0xe1, 0x73, 0x86, 0x1f, 0xb3, 0xa2, 0xea, 0x65, 0x1e, 0xce,
1179 0x1d, 0x86, 0xfb, 0xa6, 0x78, 0x56, 0x25, 0xf7, 0x28, 0xf2, 0x76, 0x45, 1185 0xc9, 0x81, 0xb8, 0x7c, 0xf7, 0x61, 0x6a, 0x8e, 0x07, 0x9b, 0xc9, 0x25,
1180 0x6b, 0xf8, 0x91, 0xe7, 0xce, 0x9b, 0x56, 0x64, 0xcf, 0xaf, 0x29, 0x21, 1186 0x82, 0x51, 0x75, 0x9e, 0xdc, 0xf7, 0xb7, 0xcb, 0x77, 0xf6, 0x7f, 0xae,
1181 0xad, 0x17, 0x41, 0xbd, 0x4e, 0x70, 0x9c, 0x88, 0xec, 0x95, 0xf1, 0x99, 1187 0x82, 0xfb, 0x69, 0x15, 0x6a, 0xb4, 0x37, 0x2c, 0xf7, 0xbb, 0x0c, 0xf9,
1182 0xcd, 0x5e, 0x3b, 0x87, 0x5e, 0xfb, 0x85, 0x7b, 0xb4, 0xa0, 0xfe, 0x26, 1188 0xae, 0xa0, 0x39, 0xee, 0xe5, 0xbc, 0x38, 0xf0, 0x48, 0x7a, 0x1f, 0xe5,
1183 0x5b, 0x3c, 0x4c, 0x8e, 0x63, 0xda, 0x9e, 0x21, 0xbe, 0x3e, 0x15, 0x47, 1189 0xfd, 0xb8, 0x7c, 0x4e, 0xde, 0xcf, 0x71, 0x27, 0xf7, 0x29, 0x82, 0x33,
1184 0x25, 0xae, 0x88, 0x4c, 0xc1, 0xd0, 0x2b, 0xd1, 0xb7, 0xa3, 0x03, 0x81, 1190 0x3f, 0x72, 0x5e, 0x64, 0x1c, 0x09, 0xf2, 0xf9, 0xe7, 0xd8, 0xf6, 0xd1,
1185 0x9a, 0x1c, 0x66, 0xb9, 0x8c, 0xb9, 0xd8, 0x93, 0xde, 0xec, 0xca, 0xf1, 1191 0xf8, 0xf3, 0xce, 0x3c, 0xe2, 0xeb, 0xb1, 0x84, 0x86, 0xf9, 0x57, 0x35,
1186 0xf2, 0x4e, 0x3c, 0x45, 0x4c, 0xdb, 0xb8, 0x63, 0xa2, 0xb6, 0x8a, 0xba, 1192 0xe1, 0xf8, 0x9d, 0x32, 0x66, 0x05, 0xb3, 0xf4, 0x2f, 0xf8, 0x24, 0xcf,
1187 0xea, 0xd0, 0x1b, 0xf4, 0xd3, 0xb8, 0x83, 0x7e, 0x2e, 0x65, 0x27, 0xbe, 1193 0xac, 0xd5, 0xe7, 0xe2, 0xe6, 0x3b, 0x8a, 0xf7, 0xaa, 0xa2, 0xb2, 0x4e,
1188 0x52, 0x05, 0x29, 0x67, 0xe1, 0x48, 0xa4, 0x06, 0xc9, 0x1d, 0x9f, 0x46, 1194 0xa8, 0xa1, 0xea, 0xaa, 0x06, 0x68, 0xa5, 0x7b, 0xcb, 0xa3, 0xde, 0xee,
1189 0x66, 0xba, 0xdc, 0x97, 0x7b, 0x6e, 0xe2, 0xb0, 0x0f, 0xeb, 0x77, 0xf8, 1195 0x59, 0x8a, 0x1e, 0xbc, 0x4d, 0x91, 0xe7, 0xbf, 0x24, 0xb7, 0x75, 0x9c,
1190 0x91, 0xf1, 0xc9, 0x5a, 0x99, 0xac, 0x57, 0x0a, 0x36, 0xbf, 0x61, 0x99, 1196 0x07, 0x38, 0x5f, 0x2d, 0xf1, 0x00, 0x4e, 0xb3, 0x9d, 0x5e, 0xea, 0x6f,
1191 0x5e, 0xe9, 0x87, 0xc4, 0xf7, 0x50, 0x73, 0x37, 0x63, 0x9a, 0xd7, 0x88, 1197 0xe5, 0xf9, 0xf9, 0x2a, 0xd7, 0xff, 0xb9, 0xa3, 0x7d, 0x4a, 0xea, 0x8a,
1192 0x11, 0x3f, 0xc8, 0x3d, 0x46, 0x7f, 0x62, 0x65, 0x6c, 0x0e, 0xef, 0x36, 1198 0x8c, 0x85, 0x5d, 0x37, 0x2b, 0x1c, 0x50, 0xb5, 0xe8, 0xd9, 0xd5, 0x19,
1193 0x85, 0x23, 0x3d, 0xab, 0x35, 0xc4, 0x8e, 0xb0, 0x07, 0xf1, 0xec, 0x7f, 1199 0xcb, 0xf6, 0xba, 0xdf, 0x83, 0x1d, 0xaf, 0x9d, 0x5f, 0xf3, 0x3a, 0xe3,
1194 0xd2, 0x47, 0x9c, 0xb8, 0x47, 0xfb, 0xb8, 0xfe, 0x7b, 0xd8, 0x3f, 0xb8, 1200 0xc6, 0xa3, 0x65, 0xd7, 0x07, 0x71, 0xdc, 0xa9, 0x6f, 0xb7, 0x82, 0x95,
1195 0x9d, 0xc4, 0x76, 0xf2, 0x48, 0x62, 0x70, 0xc8, 0x25, 0x31, 0xbf, 0x88, 1201 0x90, 0xb8, 0xd4, 0x1c, 0xfb, 0x0a, 0xe5, 0xfe, 0xc0, 0x28, 0xc6, 0xac,
1196 0xed, 0x6f, 0xd9, 0xa1, 0xa0, 0x85, 0x18, 0xb8, 0x99, 0x36, 0xf5, 0x40, 1202 0xfd, 0x46, 0x24, 0x6b, 0xd1, 0x1f, 0x52, 0xcc, 0x13, 0x3b, 0x25, 0x76,
1197 0x08, 0xce, 0xd6, 0x39, 0xe4, 0x35, 0xf8, 0x02, 0x73, 0x1a, 0x1f, 0x36, 1203 0x4f, 0xd6, 0xfa, 0x50, 0x3b, 0x1f, 0x95, 0xed, 0x91, 0xfe, 0x05, 0xcc,
1198 0x0d, 0x63, 0x6e, 0x56, 0x1b, 0xaf, 0xf5, 0xa0, 0xc7, 0x25, 0xdc, 0xd6, 1204 0x9b, 0x3c, 0x1d, 0x12, 0xeb, 0x64, 0x7e, 0xdc, 0x32, 0x6c, 0xab, 0x0a,
1199 0x24, 0xde, 0xe7, 0xe4, 0xec, 0xbb, 0x44, 0x4e, 0x0d, 0x1e, 0xcd, 0xcb, 1205 0xcb, 0xd9, 0xc7, 0x78, 0xfb, 0xef, 0x8b, 0x13, 0x22, 0x47, 0xac, 0x33,
1200 0xd9, 0x49, 0x39, 0x9f, 0x9e, 0x05, 0x67, 0xc5, 0xa7, 0x65, 0x2e, 0x17, 1206 0xd2, 0x9f, 0xc4, 0xef, 0x2b, 0x0b, 0x46, 0x65, 0x59, 0x4f, 0xf2, 0xdf,
1201 0xd2, 0xbf, 0x6a, 0x90, 0xb2, 0xe3, 0x04, 0x79, 0xe0, 0x67, 0xa0, 0x68, 1207 0x90, 0xca, 0xab, 0xe4, 0x19, 0x15, 0xc1, 0xde, 0x8e, 0x46, 0x5e, 0xf2,
1202 0x33, 0x25, 0x67, 0x58, 0x6a, 0xd7, 0xbb, 0xa5, 0x71, 0xfc, 0x4c, 0x15, 1208 0xdc, 0x7b, 0xc3, 0xda, 0xfc, 0xf9, 0x75, 0x3c, 0x64, 0x8d, 0x0a, 0xa8,
1203 0xc1, 0xf5, 0xf4, 0xac, 0x71, 0x3a, 0x72, 0x41, 0x27, 0xde, 0x42, 0x5f, 1209 0x57, 0x0b, 0x66, 0x13, 0x7d, 0x83, 0x32, 0x3e, 0x8b, 0x56, 0x2e, 0x39,
1204 0xff, 0xea, 0x42, 0x1b, 0x1c, 0x33, 0xed, 0xcb, 0x1d, 0x95, 0xbe, 0x3d, 1210 0x7a, 0xe7, 0x5d, 0x77, 0xd3, 0x9f, 0x9f, 0x63, 0x8b, 0xa3, 0xe4, 0x33,
1205 0x6e, 0xb5, 0x7a, 0x73, 0x73, 0x95, 0xd8, 0x11, 0x0c, 0xb4, 0x51, 0xe7, 1211 0x96, 0xeb, 0x19, 0xe2, 0xeb, 0x33, 0xd7, 0xf5, 0x24, 0x86, 0x94, 0xd7,
1206 0x5b, 0xf4, 0xfa, 0xb6, 0x34, 0x29, 0xcc, 0x03, 0x73, 0x3e, 0x4d, 0xdf, 1212 0x06, 0x1b, 0x30, 0xb8, 0xfb, 0x0e, 0x68, 0x8d, 0x45, 0x1c, 0x52, 0xcd,
1207 0xf7, 0x63, 0xf3, 0x30, 0x6e, 0x18, 0xd1, 0x24, 0xc6, 0x8c, 0x07, 0xcb, 1213 0xc5, 0x58, 0x96, 0x7d, 0xdb, 0x57, 0xe4, 0xe0, 0xb5, 0x18, 0xd8, 0x1d,
1208 0x2f, 0x9a, 0x83, 0xab, 0xa9, 0xef, 0x6a, 0xca, 0x27, 0xbf, 0x9b, 0x55, 1214 0x47, 0x6e, 0x8e, 0x3c, 0x93, 0x7b, 0x7e, 0x08, 0x4e, 0x6e, 0xdf, 0x7d,
1209 0xe8, 0x3b, 0xfb, 0x41, 0xfc, 0x7e, 0x74, 0x87, 0xe4, 0xc2, 0x75, 0xe4, 1215 0x99, 0xe4, 0xd4, 0x61, 0x91, 0x9b, 0xa2, 0xef, 0xa8, 0xfa, 0xdb, 0x8e,
1210 0x58, 0x96, 0x75, 0x90, 0x63, 0x68, 0x9e, 0xd5, 0xb0, 0xe6, 0xb8, 0xa3, 1216 0x15, 0x14, 0xf9, 0x87, 0xae, 0xf4, 0x52, 0x87, 0x37, 0xa1, 0xb5, 0x67,
1211 0x16, 0x93, 0xd3, 0xaf, 0xc4, 0xce, 0x61, 0x89, 0x3f, 0x01, 0xd6, 0x6d, 1217 0x0c, 0xa7, 0xc8, 0xeb, 0xdc, 0x35, 0x54, 0xad, 0xd2, 0x9c, 0xba, 0xdf,
1212 0xaa, 0xcc, 0x71, 0x1b, 0xb8, 0x6e, 0xe5, 0x58, 0x0f, 0xe7, 0xc7, 0xe1, 1218 0x87, 0x68, 0x6a, 0x9c, 0x38, 0x10, 0x98, 0xf0, 0x93, 0x9f, 0xcc, 0x77,
1213 0xd2, 0xc4, 0x26, 0x9a, 0xb0, 0x67, 0xe0, 0xfc, 0xf3, 0xe0, 0x2d, 0xda, 1219 0xd7, 0x8e, 0x96, 0x91, 0x7f, 0xa4, 0xc8, 0x6d, 0x3f, 0xee, 0xf5, 0xe2,
1214 0x78, 0xd0, 0xf5, 0x07, 0xb6, 0x32, 0xce, 0xef, 0x0a, 0x89, 0x33, 0x17, 1220 0x6e, 0x62, 0xc6, 0x7e, 0xbd, 0x75, 0xc3, 0x18, 0x7e, 0x45, 0xac, 0x93,
1215 0xe9, 0x75, 0xdd, 0xf0, 0x69, 0x7e, 0x57, 0x33, 0x2e, 0xe6, 0xfa, 0xbd, 1221 0xf2, 0x3f, 0x60, 0x7b, 0x22, 0xd3, 0xcb, 0xf6, 0xe0, 0xf7, 0x12, 0x8f,
1216 0x6e, 0xf8, 0x5f, 0x79, 0x2d, 0x7d, 0xb7, 0xb0, 0xce, 0xce, 0x63, 0x8a, 1222 0xc9, 0x09, 0xbd, 0x3e, 0x3d, 0xed, 0x93, 0xf8, 0x2d, 0xdc, 0x75, 0xc7,
1217 0x18, 0xdf, 0x04, 0x9b, 0xc5, 0xae, 0x6b, 0x24, 0x8f, 0x6b, 0xce, 0x40, 1223 0x6e, 0x05, 0x9d, 0x94, 0xf3, 0x28, 0x6d, 0xe6, 0xfe, 0x28, 0xbc, 0x5d,
1218 0x62, 0xb3, 0xd8, 0xf2, 0x80, 0xd8, 0x72, 0xd8, 0xa1, 0x00, 0x43, 0xe7, 1224 0x57, 0x91, 0xa3, 0x90, 0xf3, 0x61, 0x4e, 0x00, 0x8f, 0x8c, 0x23, 0x91,
1219 0x6d, 0xb9, 0x13, 0x3f, 0xd0, 0x26, 0xee, 0x2a, 0xc6, 0xc4, 0x17, 0x65, 1225 0xd7, 0xa7, 0xe6, 0x05, 0xf0, 0x26, 0xe5, 0x08, 0xae, 0x57, 0x94, 0xe4,
1220 0xad, 0xb8, 0x23, 0x82, 0x63, 0x8b, 0x88, 0x13, 0x6f, 0xe9, 0x05, 0xbd, 1226 0xf4, 0xac, 0xb9, 0x58, 0x4e, 0x2d, 0x1e, 0x2f, 0xc9, 0xd9, 0x43, 0x39,
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1222 0xaa, 0x9f, 0xed, 0x5e, 0x8a, 0xa5, 0xd2, 0x7f, 0x1d, 0x7b, 0x12, 0x13, 1228 0x19, 0x17, 0xdb, 0xc9, 0xe9, 0x3e, 0x06, 0x45, 0x5f, 0x28, 0xfc, 0xff,
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1225 0x05, 0x2f, 0x86, 0xfc, 0xf9, 0xb5, 0xd8, 0x2b, 0x91, 0x1c, 0x9e, 0x38, 1231 0xd9, 0x4e, 0xb9, 0x8d, 0x06, 0xde, 0x0b, 0xe1, 0x11, 0xe6, 0x71, 0x37,
1226 0x46, 0x2e, 0x44, 0x7d, 0x4e, 0xac, 0xf1, 0xb3, 0x2f, 0xa7, 0x23, 0x05, 1232 0xb1, 0x9d, 0x03, 0x86, 0x70, 0xb1, 0x56, 0xa3, 0x4a, 0x91, 0xbc, 0x36,
1227 0xfb, 0x11, 0x9c, 0x98, 0x2a, 0x43, 0xfc, 0x03, 0x4a, 0xc5, 0x4c, 0xac, 1233 0xcc, 0xb8, 0xde, 0x80, 0x3e, 0x37, 0x16, 0x84, 0x59, 0x7f, 0x77, 0x5d,
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1838 0x7d, 0x54, 0x91, 0xb8, 0xef, 0xc1, 0x83, 0x8c, 0xcf, 0x8b, 0x7b, 0xfd, 1844 0x30, 0x76, 0x2f, 0xe7, 0x40, 0xca, 0x6a, 0xb4, 0x3f, 0x0b, 0x95, 0xe4,
1839 0x88, 0x8f, 0x5a, 0xd6, 0x2b, 0x51, 0x1f, 0x1e, 0x60, 0xfd, 0xd6, 0xde, 1845 0x84, 0x9d, 0xe9, 0x9f, 0x3a, 0xf3, 0x4d, 0x77, 0x1f, 0x0e, 0xeb, 0x0a,
1840 0x01, 0x74, 0xd1, 0x2e, 0xe2, 0x7b, 0xb5, 0x80, 0x97, 0xf1, 0x7e, 0xe5, 1846 0x3a, 0xe3, 0x5d, 0x35, 0x52, 0x23, 0x4f, 0x38, 0x75, 0xa6, 0x17, 0x6b,
1841 0xa8, 0x9b, 0x31, 0xac, 0x1a, 0x8b, 0xb6, 0x07, 0xf0, 0x95, 0x51, 0x0f, 1847 0x0b, 0x6d, 0xb8, 0x69, 0xc8, 0x71, 0x4e, 0x2f, 0x49, 0x22, 0x60, 0x06,
1842 0xe3, 0x9b, 0x35, 0xff, 0x4d, 0xdd, 0xbc, 0xd6, 0x01, 0x0d, 0x6b, 0x46, 1848 0x88, 0x61, 0x01, 0x3c, 0x94, 0xae, 0xe1, 0x7f, 0x07, 0x15, 0x8c, 0xc9,
1843 0x7d, 0x58, 0xd2, 0x1b, 0x3c, 0x23, 0xef, 0x5a, 0x9f, 0xd5, 0xc3, 0x58, 1849 0x2d, 0xaa, 0xbe, 0x7e, 0x9e, 0x47, 0xef, 0x29, 0x28, 0x12, 0xf7, 0x03,
1844 0x3d, 0xea, 0xc7, 0xed, 0xbd, 0x13, 0x5f, 0x99, 0x01, 0xf3, 0xff, 0xab, 1850 0x78, 0x80, 0xf1, 0x79, 0x45, 0x3a, 0x8c, 0x54, 0xc1, 0x71, 0x5e, 0xed,
1845 0x45, 0x23, 0xbe, 0x3c, 0x5a, 0x47, 0xf9, 0xc1, 0x55, 0x2f, 0x2b, 0x75, 1851 0x08, 0xe1, 0x7e, 0xd6, 0xef, 0x4a, 0xf7, 0xa3, 0x97, 0x76, 0x91, 0x1a,
1846 0xf8, 0xdb, 0xbd, 0x3a, 0xe5, 0xab, 0xb8, 0x8d, 0x72, 0x6e, 0xed, 0xbd, 1852 0xd3, 0xb5, 0x20, 0xe3, 0xfd, 0xba, 0x82, 0x9f, 0x31, 0xac, 0x01, 0xb7,
1847 0x1a, 0x0f, 0xee, 0x8d, 0xe2, 0xbe, 0xd1, 0xb9, 0x58, 0xc8, 0xf8, 0xd4, 1853 0xec, 0xd2, 0xf0, 0x50, 0x21, 0xc0, 0xf8, 0xe6, 0x2c, 0x3d, 0x69, 0x58,
1848 0xc1, 0xbc, 0x0e, 0x9f, 0x07, 0x6e, 0xef, 0x17, 0xdd, 0x43, 0x79, 0x25, 1854 0x57, 0x7a, 0xa0, 0x63, 0x63, 0x21, 0x84, 0x95, 0xe9, 0xc8, 0xb4, 0xbc,
1849 0x3a, 0x0e, 0x37, 0xe3, 0x1d, 0x0d, 0x91, 0xf7, 0x1a, 0xc9, 0xc1, 0x74, 1855 0x47, 0x7d, 0xd6, 0x88, 0xe1, 0xc1, 0x42, 0x18, 0xb7, 0xa5, 0x0f, 0x3d,
1850 0xdc, 0xbe, 0x6b, 0xae, 0xbd, 0x9f, 0x5e, 0x1f, 0x29, 0x46, 0xbc, 0x4d, 1856 0x34, 0x1f, 0xd6, 0xff, 0x98, 0x87, 0x36, 0x7c, 0xa6, 0xd0, 0x44, 0xf9,
1851 0x41, 0x4b, 0xbf, 0xc4, 0x59, 0xe1, 0x36, 0x3a, 0xe3, 0x6a, 0x88, 0x6d, 1857 0x91, 0xf5, 0xaf, 0x28, 0x4d, 0xf8, 0xec, 0x98, 0x41, 0xf9, 0x2a, 0x6e,
1852 0xe8, 0x8c, 0xab, 0xb9, 0xfb, 0x5d, 0x29, 0x39, 0x6b, 0xf5, 0x06, 0xf9, 1858 0xa5, 0x9c, 0x9b, 0xd3, 0x57, 0xe0, 0x81, 0xb1, 0x0e, 0xdc, 0x5b, 0x58,
1853 0x52, 0x04, 0x2d, 0x76, 0x8c, 0x76, 0x93, 0x5f, 0x9b, 0x70, 0x32, 0x76, 1859 0x8c, 0xe5, 0x8c, 0x4f, 0x1b, 0x98, 0x1b, 0xe2, 0xbf, 0x00, 0xb7, 0x0d,
1854 0x47, 0x68, 0xe3, 0xf3, 0x9b, 0x24, 0x56, 0x37, 0x32, 0x4f, 0x34, 0x30, 1860 0x89, 0xee, 0xa1, 0xbc, 0xda, 0x31, 0xc5, 0x7c, 0xdc, 0x00, 0x0d, 0x91,
1855 0xd6, 0xa7, 0x75, 0x9c, 0x51, 0x0c, 0x8c, 0xee, 0x92, 0x98, 0xe8, 0xc3, 1861 0xf7, 0x74, 0x72, 0x30, 0x03, 0xb7, 0xed, 0x5d, 0xec, 0xee, 0xc9, 0x37,
1856 0xea, 0x5e, 0x03, 0x6f, 0xca, 0x59, 0xfa, 0x39, 0xb1, 0xc5, 0x65, 0xd0, 1862 0xc7, 0x2b, 0x91, 0xea, 0x56, 0xd0, 0x39, 0x24, 0x71, 0x56, 0xb8, 0x8d,
1857 0xf4, 0x07, 0x11, 0x32, 0x8f, 0x31, 0xb6, 0x9f, 0xce, 0x54, 0xe3, 0x96, 1863 0xc1, 0xb8, 0x1a, 0x65, 0x1b, 0x06, 0xe3, 0x6a, 0xf1, 0x7e, 0x6f, 0x46,
1858 0xed, 0x52, 0xa6, 0x09, 0x6f, 0x0d, 0x39, 0x71, 0x4b, 0xef, 0x5a, 0x3c, 1864 0xd6, 0x2e, 0x7e, 0x42, 0xbe, 0x14, 0x47, 0xa7, 0x1b, 0xa3, 0xfd, 0xe4,
1859 0x96, 0x76, 0x60, 0x50, 0xaf, 0xef, 0x51, 0x19, 0x3f, 0x6f, 0x6c, 0x0a, 1865 0xd7, 0x16, 0xbc, 0x8c, 0xdd, 0x71, 0xda, 0xf8, 0xd2, 0x76, 0x89, 0xd5,
1860 0x7a, 0x9f, 0x21, 0x57, 0x3d, 0x33, 0x97, 0x51, 0xf9, 0x8a, 0x28, 0x5a, 1866 0x3a, 0x06, 0xe8, 0x0f, 0x93, 0x83, 0xfa, 0x86, 0x69, 0xc5, 0x44, 0x61,
1861 0xd8, 0xaf, 0x16, 0x2d, 0x77, 0x96, 0xe2, 0xbe, 0xe8, 0x5a, 0x1c, 0x4b, 1867 0xaf, 0xc4, 0xc4, 0x10, 0x1e, 0x4c, 0x9b, 0x38, 0x29, 0xe7, 0xf8, 0xaf,
1862 0x6b, 0xe6, 0x7e, 0xe6, 0xcb, 0xee, 0x26, 0x3e, 0x9f, 0xee, 0x44, 0xb7, 1868 0x4a, 0xae, 0xa8, 0x81, 0x6e, 0x3c, 0x80, 0xa8, 0x75, 0x8c, 0xb1, 0xfd,
1863 0x26, 0x9c, 0xb6, 0x91, 0xbe, 0x25, 0xeb, 0x2a, 0x51, 0xbc, 0x49, 0x7b, 1869 0x4c, 0xae, 0x01, 0x37, 0xed, 0x92, 0x32, 0xed, 0x78, 0x7d, 0xd4, 0x8b,
1864 0xed, 0xc9, 0xcc, 0x67, 0xec, 0x97, 0x98, 0x2f, 0x67, 0xfd, 0x4c, 0x54, 1870 0x9b, 0xd2, 0x9b, 0xf0, 0x44, 0xd6, 0x83, 0x11, 0xa3, 0xb9, 0x5f, 0x65,
1865 0xde, 0xa0, 0xe0, 0xf8, 0x6e, 0xe1, 0x58, 0xf3, 0xf1, 0x45, 0xea, 0xa9, 1871 0xfc, 0xbc, 0xbe, 0x3d, 0x12, 0xfc, 0x3a, 0xb9, 0xea, 0xf4, 0x62, 0x46,
1866 0xa5, 0x57, 0xc5, 0x8d, 0x7b, 0x97, 0xe3, 0xd4, 0xb6, 0x1c, 0xe7, 0x7a, 1872 0xe5, 0xb9, 0x1d, 0xe8, 0x64, 0xbf, 0x3a, 0x75, 0xf1, 0x49, 0x0b, 0xf7,
1867 0x25, 0x62, 0x7e, 0x99, 0x9c, 0xab, 0xbd, 0x9c, 0x9c, 0x8b, 0x5c, 0x2e, 1873 0x76, 0x6c, 0xc2, 0xb1, 0xac, 0x6e, 0x3d, 0x29, 0xeb, 0x0c, 0xed, 0x7c,
1868 0xbc, 0x5a, 0x71, 0x22, 0x34, 0xda, 0x4c, 0x5e, 0x21, 0xfc, 0x82, 0xfe, 1874 0x3e, 0xc7, 0x8b, 0x3e, 0x5d, 0x38, 0xad, 0x4e, 0xdf, 0x22, 0xeb, 0xd4,
1869 0x9a, 0x8d, 0x62, 0x51, 0x6f, 0x1d, 0x86, 0xc9, 0xb7, 0x32, 0xc4, 0x8b, 1875 0x3b, 0x70, 0x92, 0xf6, 0xda, 0x9f, 0x5b, 0xca, 0xd8, 0x2f, 0x31, 0xdf,
1870 0x4c, 0x96, 0x71, 0x65, 0xa8, 0x86, 0x9f, 0x00, 0x3f, 0xd7, 0xf0, 0xa3, 1876 0x6f, 0x85, 0x59, 0xaf, 0xee, 0x3a, 0x05, 0x27, 0xf6, 0x09, 0xc7, 0x5a,
1871 0xd9, 0xf7, 0x56, 0xd0, 0x96, 0x63, 0x6d, 0x8a, 0x7d, 0xce, 0x7e, 0x30, 1877 0x8a, 0xbb, 0xa8, 0xa7, 0xce, 0xb4, 0x8a, 0xeb, 0xc7, 0xd6, 0xe0, 0xf4,
1872 0x2b, 0xb1, 0x5a, 0x41, 0x95, 0xf6, 0x17, 0x55, 0x92, 0x67, 0x7a, 0x35, 1878 0xce, 0x22, 0xe7, 0x7a, 0x35, 0x6e, 0x7d, 0x86, 0x9c, 0xab, 0x67, 0x16,
1873 0x05, 0xaf, 0xa5, 0x03, 0xf8, 0x6a, 0xd3, 0x5a, 0x25, 0x56, 0x6d, 0xbf, 1879 0x39, 0x17, 0xb9, 0x5c, 0xec, 0x41, 0xc5, 0x8b, 0x68, 0x21, 0x41, 0x5e,
1874 0xa7, 0x6a, 0x96, 0xb2, 0x6f, 0x8b, 0xe6, 0xc9, 0x3a, 0x64, 0x98, 0x39, 1880 0x21, 0xfc, 0x22, 0x8c, 0xa7, 0xf2, 0x1d, 0xb8, 0x25, 0xdd, 0x84, 0x71,
1875 0xaf, 0xfc, 0x8f, 0x02, 0x05, 0x0f, 0x30, 0x97, 0x0f, 0x54, 0x05, 0xe4, 1881 0xf2, 0xad, 0x1c, 0xf1, 0x22, 0x97, 0x67, 0x5c, 0x19, 0x6d, 0xe4, 0xa5,
1876 0x1c, 0x14, 0xfd, 0xdd, 0x87, 0x17, 0x12, 0x71, 0x64, 0x13, 0x0d, 0x3d, 1882 0xf1, 0x5a, 0xc0, 0x4b, 0x77, 0xef, 0xad, 0xa5, 0x2d, 0x27, 0xbb, 0x25,
1877 0xab, 0x15, 0xd9, 0xef, 0x09, 0x36, 0xc7, 0x95, 0x1c, 0xe7, 0x2f, 0x67, 1883 0x4f, 0x23, 0xff, 0xcd, 0x4b, 0xac, 0x56, 0x98, 0xb7, 0xfe, 0xaf, 0x7a,
1878 0xdd, 0xdd, 0xf3, 0x3a, 0xd0, 0x41, 0x6e, 0x7f, 0x3a, 0xc7, 0xed, 0x03, 1884 0xc9, 0x4d, 0x83, 0xba, 0x82, 0xaf, 0x65, 0x35, 0xfc, 0x55, 0xfb, 0x76,
1879 0x93, 0xe8, 0xc0, 0xca, 0x84, 0xec, 0x6f, 0xc6, 0xad, 0x2e, 0xce, 0xc1, 1885 0x25, 0xd9, 0xe0, 0xbe, 0x83, 0x4a, 0xdf, 0xb6, 0x70, 0x92, 0x63, 0xba,
1880 0xe1, 0x44, 0x07, 0xee, 0x4c, 0x34, 0x74, 0x10, 0x5a, 0x30, 0x7e, 0x57, 1886 0x37, 0x2b, 0x76, 0x49, 0x19, 0xcc, 0xd1, 0x8f, 0x19, 0xf5, 0xd0, 0xea,
1881 0x07, 0x5a, 0x12, 0xf5, 0xe3, 0x5b, 0xe5, 0x7f, 0x50, 0x4d, 0xd3, 0x70, 1887 0x35, 0x39, 0xd7, 0xc4, 0xd8, 0xc1, 0xf8, 0x6b, 0xa7, 0xc8, 0xa3, 0x5a,
1882 0x60, 0x4c, 0x45, 0xad, 0x16, 0x20, 0xf6, 0x07, 0x30, 0x98, 0x6a, 0x38, 1888 0xbb, 0x5b, 0x55, 0x8f, 0xbc, 0x9f, 0x67, 0x68, 0xaa, 0xf8, 0x58, 0x0a,
1883 0xd3, 0xa5, 0xde, 0xa9, 0x4c, 0x5e, 0x21, 0x39, 0x64, 0x33, 0x9e, 0x4f, 1889 0x15, 0x69, 0xbf, 0x55, 0x27, 0xf5, 0x97, 0x6c, 0x60, 0x3c, 0x68, 0x5d,
1884 0x78, 0x50, 0x96, 0x34, 0x69, 0xfb, 0x40, 0xe9, 0x48, 0x94, 0xf9, 0xc3, 1890 0xff, 0xb2, 0xf0, 0xfb, 0x39, 0x11, 0x6d, 0x0a, 0x1b, 0xb0, 0xce, 0xd6,
1885 0x63, 0x56, 0x95, 0x11, 0x4a, 0x8b, 0x5e, 0x4a, 0x46, 0xe6, 0xe3, 0x0d, 1891 0x19, 0x03, 0xd7, 0x38, 0xbd, 0x9c, 0x87, 0x51, 0x7b, 0x03, 0xee, 0xb2,
1886 0xc6, 0xdc, 0xfa, 0xeb, 0x35, 0xef, 0x42, 0x1b, 0x8b, 0x7e, 0x65, 0xd5, 1892 0x5b, 0xa7, 0x1e, 0xa7, 0x6d, 0xe1, 0xce, 0x0d, 0xe8, 0xe4, 0xb3, 0x91,
1887 0x1a, 0x65, 0x98, 0xb1, 0x2b, 0xd4, 0xdc, 0xc2, 0xf8, 0xda, 0x7c, 0x03, 1893 0x4c, 0xf3, 0x74, 0x2f, 0x75, 0x7d, 0x7c, 0x76, 0xcc, 0x5d, 0xf7, 0x97,
1888 0xed, 0x80, 0xb1, 0xaf, 0xd2, 0xd8, 0xc9, 0x39, 0x16, 0x7b, 0xf2, 0xa0, 1894 0x33, 0xe4, 0xa3, 0xe4, 0xd7, 0x5f, 0xcd, 0xb4, 0x26, 0x87, 0xd4, 0x1e,
1889 0x7c, 0xc4, 0x47, 0x1c, 0xa2, 0xe8, 0x11, 0x0d, 0x7b, 0xd9, 0x2f, 0xef, 1895 0x05, 0x73, 0x24, 0x97, 0x4c, 0x90, 0x53, 0x05, 0xf0, 0x99, 0xb4, 0x45,
1890 0x88, 0x9c, 0x0b, 0x0a, 0xb6, 0xdf, 0x27, 0xff, 0x53, 0x64, 0x4f, 0xee, 1896 0x1f, 0x00, 0x6d, 0xae, 0x83, 0x79, 0xc5, 0x13, 0x4e, 0xbd, 0x19, 0x35,
1891 0xfc, 0xe1, 0xfb, 0x89, 0xcf, 0x40, 0x92, 0x51, 0xcf, 0x88, 0x07, 0x1f, 1897 0x44, 0x3f, 0xeb, 0x0b, 0x4b, 0xf1, 0x14, 0x63, 0x6f, 0xf3, 0xb5, 0x7a,
1892 0x26, 0xe4, 0x0c, 0x1f, 0x69, 0xcd, 0x48, 0x00, 0x55, 0xac, 0xfb, 0x66, 1898 0xf0, 0x39, 0x68, 0xf0, 0x99, 0x3f, 0x75, 0x1a, 0xcc, 0x1a, 0x3c, 0x30,
1893 0xa2, 0x3e, 0xfd, 0xdf, 0x51, 0x1f, 0xb8, 0x55, 0xad, 0xb4, 0xcf, 0x0a, 1899 0x12, 0x4d, 0xdc, 0xc4, 0x38, 0xdb, 0x79, 0xad, 0x7e, 0xf4, 0x14, 0x63,
1894 0x39, 0x47, 0x6e, 0xc2, 0x89, 0x74, 0x70, 0x9c, 0x79, 0xf4, 0xaa, 0x76, 1900 0xe0, 0x7c, 0xd3, 0x96, 0xf3, 0x26, 0xe4, 0x3b, 0x01, 0xd7, 0xce, 0x4f,
1895 0xaa, 0x98, 0xb9, 0xae, 0x79, 0x8d, 0xd2, 0xd0, 0xa1, 0xaa, 0xc1, 0xf0, 1901 0xdb, 0xe2, 0x27, 0x3a, 0x71, 0x33, 0x84, 0xcf, 0xd1, 0xce, 0xdf, 0xb7,
1896 0xa8, 0x02, 0xca, 0x73, 0xb2, 0x8d, 0x9b, 0xf0, 0x76, 0xba, 0x14, 0x45, 1902 0x63, 0x98, 0x24, 0xdf, 0xf8, 0x2c, 0xfd, 0xe3, 0x8c, 0x1d, 0x49, 0x5d,
1897 0xbb, 0x76, 0xd2, 0xee, 0x8b, 0xb0, 0x78, 0x9b, 0x1b, 0x25, 0x7b, 0xc4, 1903 0xa3, 0xea, 0xd8, 0x40, 0xff, 0x78, 0xd7, 0x4e, 0xd0, 0x77, 0x3e, 0xc6,
1898 0x56, 0x45, 0xaf, 0x92, 0xef, 0x83, 0xb6, 0x6a, 0x62, 0x6f, 0x74, 0x39, 1904 0xab, 0x8d, 0xfe, 0x10, 0x63, 0x1d, 0x8d, 0x7e, 0x10, 0x72, 0xcf, 0x95,
1899 0x9e, 0x1f, 0x90, 0x7d, 0xf4, 0x0b, 0x1c, 0xbc, 0x2d, 0x62, 0xde, 0xae, 1905 0x8e, 0x65, 0x9a, 0xbb, 0x1f, 0x42, 0x73, 0xec, 0x66, 0xa5, 0x8e, 0x79,
1900 0x32, 0x06, 0xad, 0x4f, 0x85, 0xe2, 0x25, 0xb4, 0x09, 0x87, 0x11, 0x6a, 1906 0x6a, 0x10, 0xf7, 0x14, 0x6e, 0xc0, 0x89, 0x6c, 0x64, 0x9a, 0x39, 0xf9,
1901 0xef, 0xe6, 0xd8, 0x1b, 0x46, 0xc5, 0xce, 0x9a, 0xf1, 0x1d, 0x8e, 0xa5, 1907 0xc6, 0xa5, 0x0a, 0xee, 0x20, 0x67, 0x5b, 0x5f, 0xad, 0xb4, 0x4e, 0x3d,
1902 0x9f, 0x36, 0x31, 0x9c, 0xa8, 0xc3, 0x46, 0xda, 0x84, 0x49, 0x9b, 0x30, 1908 0xa5, 0x44, 0x68, 0x93, 0x8c, 0x97, 0xf4, 0xcf, 0xcf, 0xb2, 0xcc, 0x99,
1903 0x39, 0xff, 0x26, 0x6d, 0xc2, 0xa4, 0x4d, 0x98, 0xb4, 0x09, 0x93, 0x36, 1909 0x6c, 0x35, 0x36, 0x8c, 0xd8, 0xe8, 0xcf, 0x54, 0xa0, 0x6a, 0xa7, 0x1f,
1904 0x61, 0x66, 0xe7, 0x63, 0x5f, 0x5a, 0x45, 0xcf, 0x50, 0x19, 0xe2, 0xd5, 1910 0xf7, 0x8f, 0xe9, 0xc8, 0x64, 0x64, 0x1d, 0xd9, 0x6f, 0xd5, 0x12, 0x37,
1905 0xf2, 0x1e, 0xbd, 0x86, 0xb1, 0x54, 0x97, 0x32, 0x79, 0xd7, 0x4d, 0x18, 1911 0x46, 0x89, 0x0d, 0x2f, 0x2d, 0x01, 0xa6, 0xf7, 0xae, 0xc1, 0x81, 0x9d,
1906 0x4c, 0xdf, 0xcc, 0x8f, 0x82, 0x76, 0xda, 0xc5, 0xce, 0x8c, 0xd8, 0x99, 1912 0x3a, 0xe3, 0x5d, 0xd1, 0x3e, 0x82, 0x71, 0x97, 0x93, 0xa7, 0x84, 0x93,
1907 0x1b, 0xdf, 0xcd, 0xce, 0x99, 0x86, 0xd2, 0x5c, 0xac, 0x7c, 0xcc, 0xbe, 1913 0x57, 0x99, 0x12, 0xfb, 0xa2, 0x3d, 0x8f, 0x50, 0x07, 0xb7, 0x15, 0xc4,
1908 0xa7, 0x70, 0x8e, 0xdc, 0x78, 0x26, 0x2b, 0xf7, 0x4c, 0x9c, 0xa0, 0xfd, 1914 0xee, 0x12, 0x9c, 0xa3, 0x30, 0x06, 0x69, 0x23, 0xfb, 0xec, 0x26, 0xe6,
1909 0xf7, 0x50, 0x9e, 0x1a, 0x91, 0xfd, 0x92, 0x28, 0xf9, 0xbe, 0x9c, 0x0b, 1915 0xe6, 0x01, 0x58, 0xb4, 0x11, 0x4b, 0xde, 0x53, 0xa5, 0x8d, 0x58, 0xb4,
1910 0xdf, 0xc9, 0x7e, 0x0b, 0xcf, 0x30, 0xb1, 0x65, 0x1e, 0xd0, 0xd4, 0xbf, 1916 0x11, 0x8b, 0x36, 0x62, 0xd1, 0x46, 0xac, 0xfc, 0x52, 0xe6, 0x4c, 0x3a,
1911 0x16, 0x0f, 0xf5, 0x61, 0xbc, 0x9c, 0xcf, 0xbe, 0x93, 0xd9, 0x49, 0x1f, 1917 0xc6, 0xd9, 0xe6, 0xb6, 0x51, 0x72, 0xf7, 0xa0, 0xd8, 0x4a, 0x0c, 0x5f,
1912 0x6e, 0xb4, 0xd7, 0x30, 0xee, 0x6f, 0x52, 0xf0, 0xa5, 0xb4, 0x9c, 0x27, 1918 0xcf, 0xf4, 0x2b, 0xda, 0x9d, 0x37, 0x60, 0x24, 0x7b, 0x23, 0x2f, 0x05,
1913 0xaf, 0x8f, 0x6d, 0x44, 0xc4, 0xf6, 0xdb, 0xfe, 0xd4, 0x4e, 0xa4, 0xf8, 1919 0xb7, 0xd2, 0x56, 0x1e, 0xcd, 0x89, 0xed, 0xe9, 0xee, 0xef, 0xd3, 0x3c,
1914 0xcc, 0x1f, 0x69, 0xa2, 0x4f, 0x56, 0xe3, 0xdd, 0x6d, 0x41, 0xfd, 0x35, 1920 0x9b, 0xdf, 0x33, 0x1b, 0xd5, 0xe2, 0x03, 0x8c, 0x45, 0xee, 0x7d, 0x39,
1915 0x68, 0xad, 0x23, 0xb0, 0xe6, 0x2f, 0x8c, 0x84, 0xcc, 0x7a, 0xa5, 0x09, 1921 0x73, 0xec, 0xc7, 0x68, 0xfe, 0x82, 0x5f, 0x7c, 0x4f, 0xce, 0xab, 0xb4,
1916 0x6d, 0x7b, 0x9b, 0x98, 0x3b, 0x04, 0xf5, 0xd7, 0xe9, 0x73, 0xcf, 0x45, 1922 0xcb, 0x6f, 0xc5, 0x74, 0x30, 0x0f, 0x90, 0x73, 0xee, 0x32, 0x4e, 0x19,
1917 0xe6, 0x33, 0x7f, 0x88, 0xe1, 0x2b, 0xe4, 0xf9, 0x77, 0x0d, 0xaa, 0x1c, 1923 0x57, 0x71, 0x4c, 0x55, 0x83, 0x9b, 0xf0, 0xf5, 0x41, 0x9d, 0xb1, 0xca,
1918 0x53, 0xa3, 0xbd, 0xf6, 0xf1, 0x9c, 0xfd, 0x0e, 0x5c, 0x54, 0xce, 0xc8, 1924 0xc0, 0x93, 0x39, 0x89, 0xe5, 0xe2, 0xdf, 0x32, 0x0f, 0xe2, 0xeb, 0x1e,
1919 0x28, 0x0f, 0x12, 0x73, 0x16, 0x27, 0x0f, 0x5a, 0xf2, 0x4e, 0xed, 0xca, 1925 0xd4, 0xb4, 0x7b, 0x11, 0x70, 0xfd, 0xbc, 0x39, 0xbc, 0x43, 0xb1, 0xe9,
1920 0xeb, 0x9a, 0xb1, 0x3f, 0x6b, 0xe0, 0xc9, 0xf4, 0x1b, 0x96, 0xaa, 0xc5, 1926 0x3b, 0xba, 0x9c, 0x03, 0x9d, 0x0a, 0xeb, 0x0d, 0x38, 0xbd, 0xbb, 0x1d,
1921 0xce, 0x3a, 0xc9, 0x45, 0x3c, 0xc4, 0x8c, 0x6c, 0x46, 0xfc, 0x5f, 0xf6, 1927 0xff, 0x6d, 0xa7, 0x87, 0x3c, 0xc0, 0x59, 0xfa, 0x52, 0x5c, 0x4f, 0x4e,
1922 0xc0, 0x0d, 0x7c, 0x98, 0xd6, 0xd2, 0x0d, 0x8c, 0x4b, 0xbf, 0xe6, 0xbd, 1928 0x2b, 0xd1, 0xd8, 0x2c, 0xa5, 0x1d, 0xf7, 0x90, 0xfb, 0x6f, 0x18, 0x8c,
1923 0x9d, 0xc4, 0x11, 0xf7, 0x56, 0xed, 0xa8, 0x4a, 0x0e, 0x3f, 0xdf, 0x61, 1929 0x74, 0x33, 0x66, 0x1b, 0xb7, 0x28, 0x4b, 0x51, 0xc5, 0x1c, 0xa0, 0x8d,
1924 0xa0, 0x68, 0xb7, 0xcc, 0x81, 0xe0, 0x56, 0x00, 0x63, 0x89, 0x18, 0xee, 1930 0x39, 0xc0, 0x83, 0xc4, 0x80, 0xaf, 0x66, 0xbc, 0x68, 0x59, 0x2c, 0xbf,
1925 0xa4, 0xfd, 0x8c, 0x26, 0x5a, 0x70, 0x07, 0x6d, 0x63, 0x24, 0xd1, 0x8a, 1931 0x4d, 0xa6, 0xbb, 0x6b, 0x3b, 0x2f, 0x90, 0xa3, 0xce, 0x37, 0x3b, 0xe4,
1926 0xcf, 0x31, 0x37, 0xd8, 0x9d, 0x10, 0x3f, 0x5b, 0x82, 0x85, 0xb4, 0x95, 1932 0x2c, 0x8e, 0x72, 0xf6, 0xba, 0x29, 0x24, 0x28, 0x7f, 0xcc, 0xcd, 0x2f,
1927 0xfd, 0xa9, 0xff, 0x05, 0x7d, 0x7a, 0x00, 0xbb, 0x6d, 0xae, 0x29, 0xfb, 1933 0x12, 0x38, 0x98, 0x27, 0x6e, 0x70, 0xdc, 0xaf, 0xb4, 0xfd, 0x84, 0xf9,
1928 0xd6, 0x50, 0x56, 0x26, 0xdc, 0xcc, 0x6d, 0xe2, 0x56, 0x7f, 0x4a, 0x38, 1934 0xb0, 0x70, 0x7b, 0x13, 0x13, 0x39, 0x97, 0xff, 0x47, 0xea, 0x88, 0x19,
1929 0x50, 0x27, 0x6e, 0x89, 0x34, 0x62, 0x0b, 0xe5, 0x65, 0xc9, 0x75, 0x87, 1935 0xd9, 0x41, 0xbd, 0xcb, 0xaf, 0x9a, 0x78, 0x64, 0xaf, 0xf8, 0xb0, 0x89,
1930 0x98, 0x4f, 0xad, 0xde, 0xb5, 0x9c, 0x98, 0x7c, 0x61, 0xee, 0x4f, 0xeb, 1936 0xf6, 0x21, 0x3d, 0x7c, 0x9b, 0x1a, 0x0d, 0xae, 0xe3, 0xb3, 0x05, 0x9c,
1931 0xe6, 0x21, 0x62, 0x41, 0xd8, 0xcf, 0x79, 0x57, 0x69, 0xc3, 0x72, 0xce, 1937 0xcf, 0xc7, 0x33, 0x32, 0x8f, 0x1a, 0x5a, 0x18, 0x9b, 0xdf, 0x9c, 0xd0,
1932 0x7c, 0x90, 0x63, 0x9f, 0x43, 0x3c, 0x70, 0xa7, 0xc4, 0x7e, 0x82, 0x47, 1938 0xb1, 0x88, 0x71, 0xfa, 0x9d, 0x89, 0x18, 0x96, 0x32, 0x66, 0x3b, 0xcc,
1933 0x19, 0xf2, 0x1e, 0xae, 0x95, 0x77, 0x15, 0xe8, 0x1b, 0x33, 0x52, 0x56, 1939 0x1f, 0x12, 0x19, 0xf1, 0x45, 0xf2, 0x81, 0x09, 0x8d, 0x71, 0x56, 0xd6,
1934 0xa7, 0x93, 0x71, 0x64, 0x53, 0xb4, 0x0e, 0x07, 0x47, 0x6e, 0x86, 0x77, 1940 0x87, 0x9e, 0xc0, 0xd8, 0x6a, 0x0d, 0xfb, 0xdc, 0xf3, 0x7c, 0x7e, 0xab,
1935 0x6b, 0x1d, 0x46, 0x93, 0x7e, 0x64, 0x93, 0xa8, 0xf5, 0x42, 0xbd, 0xc1, 1941 0x81, 0x58, 0xd9, 0x39, 0xe0, 0xc7, 0xa7, 0x87, 0x36, 0xe3, 0xf5, 0xc5,
1936 0x8b, 0x60, 0xf3, 0x21, 0xc6, 0x89, 0xb7, 0x95, 0x86, 0xf6, 0x37, 0x11, 1942 0xc2, 0x95, 0xd6, 0x38, 0xa2, 0x9f, 0xc7, 0x29, 0x73, 0x8c, 0xbc, 0x78,
1937 0xec, 0xd9, 0xac, 0x04, 0xbd, 0x0d, 0xaa, 0xb4, 0x4d, 0x3c, 0xa1, 0x1f, 1943 0x94, 0x79, 0xd7, 0xc2, 0x7d, 0x6b, 0xf0, 0xc9, 0x5d, 0x17, 0xf2, 0xb4,
1938 0x0c, 0xd2, 0xde, 0x33, 0x23, 0xc4, 0x14, 0xd6, 0x75, 0x6d, 0x75, 0xc9, 1944 0x33, 0x71, 0xeb, 0x6e, 0xda, 0xc4, 0xfa, 0x00, 0x6d, 0xa2, 0x96, 0x36,
1939 0x3a, 0xf1, 0x78, 0x95, 0xe6, 0xc3, 0x9e, 0x3d, 0xc4, 0xb8, 0x1d, 0xf2, 1945 0x61, 0x67, 0xa2, 0xc9, 0x02, 0x6d, 0x22, 0x46, 0xdc, 0xc8, 0x0e, 0x48,
1940 0xbf, 0x03, 0x6a, 0xb0, 0x6f, 0xcf, 0xcd, 0x98, 0xb1, 0x35, 0x80, 0x83, 1946 0x39, 0xf7, 0x9d, 0x99, 0xbb, 0xe4, 0xdd, 0x65, 0x83, 0xbe, 0xb3, 0x75,
1941 0xbc, 0x57, 0xbb, 0xe3, 0x1a, 0x3c, 0x43, 0x3f, 0xc9, 0xd0, 0x0f, 0x8b, 1947 0xc0, 0xd9, 0xec, 0x65, 0xbc, 0x79, 0xa4, 0xa3, 0x89, 0xd8, 0x72, 0x23,
1942 0xb6, 0xaa, 0xd8, 0xbb, 0xe7, 0x26, 0x54, 0x92, 0xd7, 0x9f, 0x0a, 0x29, 1948 0xf6, 0x0c, 0x36, 0xa1, 0x85, 0x31, 0x63, 0x61, 0x1a, 0x77, 0x84, 0xa1,
1943 0x36, 0xf6, 0x26, 0x38, 0xae, 0xdd, 0x29, 0xfb, 0xdc, 0xbc, 0xf2, 0x22, 1949 0xce, 0x0f, 0x23, 0xb2, 0xe1, 0x1d, 0x44, 0xa7, 0xef, 0x56, 0x5a, 0x8f,
1944 0xf3, 0x81, 0xee, 0x11, 0x1d, 0x9b, 0x79, 0x3f, 0xc5, 0xb9, 0xde, 0x42, 1950 0xbe, 0xa8, 0x44, 0x36, 0xfe, 0x84, 0x36, 0x7c, 0x56, 0x91, 0xb6, 0x9b,
1945 0xcc, 0x3d, 0xbe, 0xad, 0x1a, 0xf7, 0x6f, 0xd3, 0x62, 0xd7, 0xa8, 0xd6, 1951 0x70, 0x35, 0xfd, 0xe4, 0x2a, 0xfa, 0x84, 0xc6, 0x5c, 0x52, 0x63, 0xdd,
1946 0xfc, 0xb7, 0xf4, 0xd0, 0x19, 0x17, 0xe7, 0xd8, 0x62, 0x0e, 0x77, 0xb6, 1952 0xfe, 0x41, 0x1f, 0xe6, 0x33, 0xd7, 0x93, 0xb3, 0xca, 0xb1, 0x31, 0x2f,
1947 0xef, 0xa0, 0x55, 0x45, 0xac, 0x77, 0x69, 0xf3, 0x31, 0x73, 0x6e, 0x0c, 1953 0xb2, 0x3b, 0xf5, 0xa9, 0x47, 0xd0, 0x08, 0x63, 0xec, 0x46, 0x6c, 0x1d,
1948 0xaf, 0x47, 0x9b, 0x70, 0x66, 0x97, 0xe8, 0xca, 0x62, 0x0c, 0x90, 0xf8, 1954 0xd4, 0x10, 0xe5, 0xbd, 0xbe, 0x9d, 0x0b, 0xd0, 0x4c, 0xfb, 0xd6, 0xe8,
1949 0x10, 0x45, 0x9c, 0x39, 0xdd, 0x6e, 0xe6, 0x74, 0xf7, 0x30, 0xa7, 0x7b, 1955 0xa7, 0xbd, 0x83, 0x2a, 0x16, 0x8c, 0xdd, 0x80, 0x1d, 0x83, 0x0a, 0xee,
1950 0xb0, 0x4f, 0x74, 0xdc, 0x89, 0x25, 0x11, 0x83, 0x3a, 0x6c, 0x24, 0x7e, 1956 0x8b, 0x2a, 0x68, 0x19, 0x91, 0x1c, 0x2c, 0x86, 0xa7, 0x32, 0xc2, 0x15,
1951 0x19, 0x50, 0xfb, 0xb4, 0xe6, 0xbb, 0x88, 0xf1, 0xc5, 0x76, 0x8e, 0x67, 1957 0xa1, 0xb4, 0x5c, 0x4b, 0x8e, 0x4c, 0xee, 0xf9, 0x93, 0x9c, 0xcc, 0xb9,
1952 0x10, 0x27, 0x24, 0x4f, 0x30, 0xf0, 0xd3, 0x4c, 0xce, 0xef, 0x6a, 0x19, 1958 0xe8, 0x53, 0x7e, 0x53, 0xa6, 0x1d, 0x9f, 0xdb, 0xd9, 0x80, 0xab, 0x76,
1953 0xd3, 0x0f, 0x8c, 0xb4, 0xe0, 0xbb, 0xcc, 0xe1, 0x46, 0xfb, 0x42, 0x3b, 1959 0xeb, 0xd6, 0x69, 0xc5, 0x59, 0x7a, 0x80, 0x7c, 0xde, 0xaf, 0x16, 0xe7,
1954 0x5f, 0x56, 0x5a, 0xf1, 0x5d, 0x3b, 0x5e, 0x88, 0x0d, 0xb7, 0xe2, 0xdd, 1960 0xfc, 0xc1, 0xc1, 0x67, 0x19, 0x2f, 0x7e, 0xe2, 0x04, 0xf5, 0xa5, 0xe8,
1955 0x84, 0x16, 0x5f, 0xa8, 0x84, 0xda, 0xd3, 0xbc, 0xff, 0x5e, 0xf6, 0x66, 1961 0x8b, 0x27, 0xb1, 0xb6, 0xa3, 0x1d, 0x6b, 0xf7, 0x8a, 0xbe, 0x1c, 0xe6,
1956 0x72, 0xd8, 0x25, 0x38, 0x4e, 0x1b, 0xee, 0x49, 0x09, 0x96, 0x3b, 0xe1, 1962 0x87, 0xcc, 0xfd, 0x26, 0xa7, 0xf0, 0x0e, 0xfd, 0x77, 0x11, 0x39, 0xed,
1957 0xda, 0x76, 0x07, 0xde, 0x1a, 0xce, 0xe5, 0x6e, 0x21, 0xe6, 0x6e, 0x77, 1963 0x52, 0xc6, 0x89, 0x37, 0x16, 0x9b, 0xd4, 0x9f, 0xee, 0x9e, 0xf5, 0x9b,
1958 0xf6, 0xd3, 0x1e, 0x52, 0x10, 0x6f, 0x60, 0x0e, 0x17, 0x5c, 0x55, 0xc4, 1964 0x67, 0x9a, 0xa8, 0x1d, 0xd4, 0x19, 0x67, 0x4c, 0xcc, 0xda, 0x2b, 0xed,
1959 0xfc, 0xed, 0xa3, 0x48, 0x2e, 0x7f, 0x8b, 0x57, 0x07, 0xf5, 0x17, 0x15, 1965 0x99, 0xb8, 0x67, 0x50, 0x4f, 0x3d, 0xcd, 0xb9, 0x14, 0xbb, 0x11, 0xcc,
1960 0x73, 0xa7, 0xbc, 0x7b, 0xf4, 0x1a, 0x72, 0xe7, 0xc6, 0x4f, 0x10, 0x6b, 1966 0xae, 0x61, 0xec, 0x3f, 0x39, 0x29, 0x38, 0xd5, 0x89, 0x13, 0xcc, 0x03,
1961 0x37, 0xd1, 0x07, 0xae, 0x8b, 0x48, 0x7e, 0xa7, 0x61, 0x38, 0x65, 0xbf, 1967 0xde, 0x7c, 0x2c, 0xda, 0xfd, 0x33, 0xe6, 0x74, 0xef, 0x50, 0x46, 0x96,
1962 0xcf, 0xad, 0xff, 0x94, 0xf3, 0xeb, 0xd7, 0xc4, 0x06, 0x1c, 0x38, 0xad, 1968 0xfd, 0x1b, 0xe0, 0xbc, 0x56, 0xa4, 0xf5, 0x8d, 0xff, 0x8c, 0x28, 0xfd,
1963 0xd7, 0x7b, 0xbd, 0x0e, 0x07, 0x6e, 0xd1, 0x83, 0xab, 0x8e, 0x20, 0xca, 1969 0xbb, 0x0b, 0xb5, 0xd4, 0xc9, 0x81, 0xc1, 0x95, 0xf0, 0xd3, 0x16, 0x1e,
1964 0x79, 0x97, 0xbd, 0xc2, 0x5c, 0x3c, 0x75, 0x26, 0xe5, 0x1d, 0x94, 0x4e, 1970 0xc9, 0x88, 0xdd, 0x10, 0xbf, 0x77, 0x7e, 0x02, 0x5b, 0xf7, 0x17, 0xf3,
1965 0xbc, 0x35, 0xf7, 0xef, 0xf3, 0x79, 0x58, 0x21, 0x1f, 0x13, 0x9b, 0x6b, 1971 0xbc, 0x7b, 0x06, 0x36, 0xd1, 0xc6, 0x85, 0xb3, 0xc7, 0x68, 0xef, 0x98,
1966 0x68, 0x76, 0xa0, 0xde, 0x2c, 0x86, 0x96, 0x49, 0x93, 0x5f, 0xc6, 0x39, 1972 0xe7, 0x43, 0xb2, 0x9e, 0x18, 0x91, 0x58, 0x4e, 0xcc, 0x7c, 0xd4, 0x20,
1967 0xd7, 0x71, 0x08, 0xf6, 0x37, 0x98, 0x5e, 0x84, 0xed, 0xff, 0xf9, 0xf5, 1973 0xae, 0xd6, 0x47, 0xc2, 0x2d, 0xaa, 0x95, 0x60, 0x5e, 0x17, 0xbe, 0x0f,
1968 0x7c, 0xc2, 0x3e, 0x03, 0x4a, 0x9c, 0xcb, 0xe1, 0xea, 0x73, 0x89, 0x52, 1974 0xd2, 0xbe, 0x85, 0x75, 0x4b, 0x36, 0x61, 0x4f, 0xd6, 0x8b, 0xaa, 0xc5,
1969 0x80, 0xf8, 0x94, 0xe0, 0xd8, 0x8a, 0x47, 0x4c, 0xb8, 0x0c, 0xfa, 0x57, 1975 0x1e, 0xe2, 0xb1, 0x60, 0x94, 0x15, 0x94, 0xe7, 0x6b, 0x21, 0x7e, 0x22,
1970 0x9f, 0x07, 0xea, 0x2e, 0x0f, 0xfc, 0xc9, 0xc7, 0xac, 0x72, 0xe2, 0x6a, 1976 0xf3, 0xeb, 0xc1, 0x99, 0x78, 0xf3, 0x86, 0xac, 0xfc, 0x96, 0x05, 0x73,
1971 0xd9, 0x2e, 0xce, 0x91, 0xc3, 0xb2, 0x9e, 0x9a, 0x27, 0x38, 0x2b, 0x65, 1977 0xbe, 0xcf, 0xa2, 0x83, 0x73, 0x2f, 0xfe, 0x98, 0xc0, 0x3d, 0x63, 0xc2,
1972 0xb5, 0xd6, 0x0f, 0x79, 0xad, 0x11, 0x67, 0x35, 0x62, 0x6b, 0x05, 0xf1, 1978 0xd5, 0xc8, 0xe7, 0x6c, 0x3f, 0xfe, 0x3a, 0x2b, 0x9c, 0x6e, 0x33, 0xee,
1973 0xb1, 0x3b, 0x59, 0x8d, 0xcd, 0xdb, 0x06, 0xa8, 0x73, 0x2f, 0x1c, 0xbc, 1979 0x69, 0x2f, 0xe7, 0x6e, 0x62, 0x77, 0xad, 0xd3, 0x1e, 0x34, 0x93, 0x93,
1974 0x4e, 0x25, 0xfd, 0x36, 0x76, 0x82, 0xbf, 0x2b, 0xe9, 0x33, 0xa0, 0x9d, 1980 0xe9, 0xb9, 0xac, 0x1a, 0xb1, 0x52, 0x88, 0xf4, 0xa7, 0x20, 0x71, 0xa2,
1975 0x6d, 0x4d, 0x5a, 0xf3, 0xef, 0x8c, 0x98, 0x7d, 0x95, 0xec, 0xcb, 0x34, 1981 0xd5, 0xe2, 0x0c, 0x53, 0x36, 0xb9, 0xa5, 0xed, 0x41, 0x1d, 0x7d, 0x5c,
1976 0xe2, 0xed, 0xc6, 0x64, 0xd0, 0x7b, 0xab, 0xaa, 0xe0, 0xf6, 0x88, 0xce, 1982 0x7e, 0x44, 0xae, 0x9d, 0xf6, 0xf3, 0xac, 0x5d, 0x0d, 0xcd, 0xb5, 0x75,
1977 0xb6, 0x3d, 0xe8, 0x4b, 0x0a, 0x4e, 0x4c, 0x50, 0x8f, 0x66, 0x43, 0x19, 1983 0x2f, 0x96, 0x16, 0x2c, 0xe2, 0xed, 0x52, 0xb4, 0x3d, 0x16, 0xc0, 0x35,
1978 0x75, 0xe9, 0xa2, 0x2e, 0x67, 0xd8, 0xe7, 0x55, 0xeb, 0x50, 0xbe, 0x27, 1984 0xe4, 0x26, 0x57, 0xa7, 0x9f, 0x70, 0x66, 0x11, 0x7b, 0xdb, 0x46, 0xa2,
1979 0xca, 0x3e, 0x37, 0x12, 0x8b, 0x4d, 0x6c, 0xe2, 0xcf, 0xf9, 0xbb, 0x97, 1985 0xc1, 0x23, 0xe4, 0x81, 0x07, 0x96, 0xfc, 0xd4, 0xf1, 0x98, 0xae, 0x5f,
1980 0xe3, 0xba, 0x6d, 0x76, 0xee, 0xbb, 0x40, 0xf2, 0x99, 0xd7, 0x22, 0x21, 1986 0x68, 0xf4, 0x00, 0xe7, 0x33, 0x1d, 0xfa, 0xd4, 0x0e, 0x04, 0x90, 0x20,
1981 0xfd, 0x1e, 0xd5, 0x89, 0xb7, 0xb3, 0x82, 0xb5, 0xf2, 0x3e, 0x3d, 0xc6, 1987 0x7e, 0x5e, 0x99, 0x69, 0x40, 0xfb, 0xee, 0x7e, 0xce, 0x7f, 0x10, 0x57,
1982 0x67, 0x68, 0xcd, 0x58, 0x9a, 0x14, 0x8c, 0xf2, 0x93, 0x67, 0x47, 0xb1, 1988 0xf2, 0xfb, 0x62, 0xc6, 0x37, 0x8d, 0xd8, 0xaa, 0xc9, 0xe7, 0x82, 0xd8,
1983 0x24, 0x29, 0xfe, 0x68, 0xe2, 0xb6, 0xeb, 0xeb, 0xf0, 0xfe, 0xf9, 0x75, 1989 0x4b, 0x98, 0x7e, 0xe4, 0x2c, 0xbd, 0xb3, 0xdd, 0xba, 0x63, 0x36, 0xf5,
1984 0x0b, 0x1f, 0x26, 0x89, 0x99, 0x93, 0xc4, 0xcc, 0x49, 0x62, 0xe6, 0xa4, 1990 0xd5, 0x42, 0x5c, 0x5e, 0x9a, 0x89, 0x6c, 0xbc, 0x59, 0x51, 0xb0, 0xb2,
1985 0xbd, 0x16, 0xa1, 0xe2, 0xf4, 0x90, 0x82, 0xf7, 0x6c, 0xfc, 0xdb, 0x69, 1991 0xdd, 0x60, 0xdb, 0x01, 0xc4, 0x32, 0xb2, 0x36, 0x70, 0xe8, 0xa1, 0x3a,
1986 0x73, 0xa8, 0x27, 0x19, 0xd3, 0xdb, 0xd3, 0x3a, 0x0e, 0xd0, 0x16, 0x92, 1992 0x58, 0xad, 0x01, 0xda, 0xe9, 0x11, 0x45, 0xd6, 0x35, 0x44, 0x6f, 0x4d,
1987 0x29, 0xb1, 0x35, 0x05, 0x4f, 0xf5, 0x45, 0x50, 0x45, 0xdb, 0xd9, 0x4a, 1993 0xb8, 0x8a, 0x7c, 0x44, 0x23, 0x66, 0xc7, 0x0a, 0xa2, 0x43, 0x60, 0x6d,
1988 0x9b, 0x7e, 0x78, 0xbb, 0x16, 0x98, 0xef, 0x08, 0xb5, 0xa6, 0xd0, 0x84, 1994 0x6e, 0x0d, 0xf6, 0x0c, 0x8b, 0x7f, 0x0a, 0x76, 0x3a, 0x4e, 0xe5, 0xe2,
1989 0x07, 0x88, 0x57, 0x0f, 0x31, 0x97, 0x39, 0x44, 0x4c, 0xbb, 0x67, 0x70, 1995 0xa8, 0xf1, 0x36, 0x75, 0xf8, 0xc6, 0x84, 0x60, 0x90, 0x82, 0x79, 0xb4,
1990 0x2d, 0x96, 0xf4, 0xa9, 0xc4, 0x2c, 0x62, 0xd5, 0x74, 0xc1, 0x6e, 0xc1, 1996 0x63, 0x55, 0x97, 0x58, 0x2b, 0xb8, 0x15, 0xa6, 0xdf, 0x76, 0xe0, 0xd3,
1991 0x4b, 0x79, 0x57, 0x2e, 0x2a, 0xeb, 0x9a, 0xca, 0x5d, 0xc4, 0xaa, 0xc6, 1997 0x8c, 0x6d, 0xd5, 0x9c, 0x83, 0x55, 0x4b, 0x9a, 0xe8, 0xbf, 0xc4, 0xc9,
1992 0x5e, 0xe1, 0x38, 0xcc, 0x93, 0x18, 0x8b, 0x12, 0xc4, 0xaa, 0x2d, 0x69, 1998 0x89, 0x20, 0xaf, 0x10, 0x8e, 0xef, 0x6f, 0xe4, 0xa5, 0xf1, 0x5a, 0xc0,
1993 0x99, 0xaf, 0x4e, 0xdc, 0x4b, 0xbb, 0x5e, 0x9f, 0x5f, 0x97, 0x98, 0xb3, 1999 0x4b, 0xe7, 0x3d, 0x15, 0x67, 0xf6, 0x93, 0x33, 0xed, 0x15, 0x0e, 0x22,
1994 0x55, 0x3b, 0x73, 0x40, 0xc9, 0x71, 0x9d, 0x5e, 0x5e, 0x1f, 0xee, 0x0b, 2000 0x3e, 0xe8, 0xc7, 0xd3, 0x13, 0x20, 0x8f, 0x31, 0xc8, 0x43, 0x04, 0xff,
1995 0x50, 0x0f, 0x06, 0x8e, 0xed, 0x92, 0x3c, 0x48, 0xfa, 0x13, 0xc0, 0x21, 2001 0x64, 0x9e, 0x98, 0xc7, 0x0c, 0xc6, 0x11, 0x1d, 0x29, 0x72, 0x8e, 0x93,
1996 0xe2, 0x93, 0x83, 0xba, 0x7e, 0x99, 0xf8, 0x54, 0x49, 0x7c, 0x7a, 0x8d, 2002 0xc3, 0x7a, 0xcf, 0x5a, 0x44, 0xb5, 0xbf, 0x26, 0x7e, 0x9d, 0x1a, 0x6d,
1997 0xf8, 0x34, 0x8d, 0xf8, 0xf4, 0x6a, 0x1e, 0x9f, 0xaa, 0x47, 0xc4, 0x16, 2003 0xc7, 0x74, 0x96, 0xb8, 0xb5, 0xb8, 0x1d, 0x6f, 0xe7, 0x36, 0xd1, 0xff,
1998 0x72, 0x5c, 0xfb, 0x78, 0xe2, 0xb9, 0x2a, 0xf9, 0x5f, 0x62, 0x82, 0xf3, 2004 0x55, 0x9c, 0x25, 0x66, 0x69, 0x73, 0x05, 0xd7, 0x05, 0x43, 0xfd, 0xb4,
1999 0x97, 0xc7, 0xff, 0xa5, 0x78, 0x71, 0x00, 0xee, 0x19, 0xe4, 0xb2, 0x16, 2005 0xd7, 0x0e, 0x59, 0x03, 0x55, 0xe2, 0xc4, 0xac, 0x6b, 0xd2, 0xcf, 0x3a,
2000 0xf1, 0xe6, 0x03, 0xc7, 0x52, 0xfc, 0x74, 0xa8, 0xc0, 0x61, 0x27, 0xed, 2006 0xb5, 0x3a, 0x73, 0x2a, 0x35, 0x81, 0x0c, 0x31, 0xcb, 0xce, 0xca, 0x7c,
2001 0x5c, 0xb9, 0xdc, 0x90, 0x75, 0x30, 0x59, 0x03, 0xab, 0xcb, 0xef, 0x0b, 2007 0x6d, 0xc6, 0x56, 0xe2, 0xd5, 0xd6, 0x9c, 0xd8, 0x37, 0x6d, 0x7a, 0x50,
2002 0x9a, 0xf8, 0xce, 0x3c, 0xe1, 0x8d, 0xb2, 0xae, 0x53, 0x44, 0x7e, 0xd8, 2008 0x0f, 0x16, 0x68, 0xdb, 0xea, 0x5e, 0x91, 0x61, 0xa2, 0x8f, 0xb1, 0xfd,
2003 0x86, 0xe1, 0x6d, 0xcf, 0x62, 0x53, 0x9f, 0x7a, 0x6b, 0x19, 0xc8, 0x85, 2009 0x33, 0x1d, 0x26, 0x76, 0xe4, 0x24, 0x0e, 0x0a, 0x07, 0xd3, 0x98, 0x97,
2004 0x95, 0x4e, 0x38, 0x22, 0x95, 0x98, 0x19, 0x11, 0x1b, 0x64, 0x2e, 0x32, 2010 0x24, 0xd1, 0x43, 0x9c, 0x7a, 0xdb, 0xee, 0xc4, 0x0a, 0xe2, 0xd4, 0x2f,
2005 0xf6, 0x6d, 0x74, 0xef, 0x2e, 0xc3, 0x84, 0xd7, 0xb2, 0x9e, 0xd4, 0x6b, 2011 0x98, 0xa7, 0xdc, 0x49, 0x9c, 0x7a, 0xc3, 0x2e, 0xe2, 0xd4, 0xcd, 0x13,
2006 0xe5, 0xdf, 0x00, 0x08, 0x5e, 0x7a, 0x8a, 0x18, 0xa3, 0x6e, 0x1d, 0xfd, 2012 0x62, 0x0b, 0x45, 0x5e, 0x7e, 0xc2, 0x6e, 0x6b, 0x90, 0xdf, 0x39, 0xab,
2007 0xb8, 0x33, 0xa7, 0x6b, 0xf0, 0xc5, 0xed, 0x8f, 0xa0, 0x7d, 0xfb, 0x37, 2013 0x36, 0x7f, 0x57, 0x5c, 0x58, 0x85, 0x97, 0x86, 0xcb, 0x7b, 0xc5, 0x91,
2008 0xe9, 0x7b, 0x33, 0x7b, 0x6a, 0x69, 0x87, 0xd7, 0x35, 0x8d, 0xe3, 0x44, 2014 0xe4, 0xed, 0xe4, 0xcc, 0x47, 0x47, 0xcb, 0x9c, 0xf7, 0xb8, 0x9b, 0x5b,
2009 0x84, 0xb1, 0xcf, 0xa7, 0xe0, 0x87, 0x73, 0x66, 0x8a, 0x1c, 0xfe, 0x7d, 2015 0xcf, 0x32, 0xcb, 0xfb, 0x96, 0xe5, 0xfd, 0x06, 0x0b, 0x5f, 0x5d, 0x22,
2010 0x60, 0x05, 0x6c, 0x79, 0x6f, 0xe5, 0xfd, 0xe3, 0x39, 0x1f, 0xc7, 0x4e, 2016 0x3c, 0x53, 0xd6, 0x81, 0x2a, 0xc8, 0x27, 0xbb, 0x31, 0xbe, 0xf3, 0x3d,
2011 0xd9, 0x27, 0xbc, 0xf9, 0xb3, 0x9b, 0x7f, 0x42, 0x5b, 0x3f, 0x13, 0x19, 2017 0x3c, 0x32, 0xa8, 0xde, 0x5c, 0xc3, 0xd8, 0x7a, 0x8b, 0xb2, 0x19, 0x9e,
2012 0xfc, 0x2b, 0xc8, 0x78, 0xdd, 0x8a, 0x2d, 0x93, 0x7a, 0x45, 0xf9, 0x36, 2018 0xb8, 0xbc, 0x47, 0x2a, 0x6b, 0xe5, 0xcc, 0x5d, 0x26, 0xb3, 0xe8, 0xdb,
2013 0xbe, 0x49, 0x8e, 0x47, 0x9e, 0xa7, 0xf3, 0x7b, 0xf0, 0x59, 0x91, 0xcf, 2019 0x57, 0x83, 0x43, 0x41, 0xc7, 0x79, 0xda, 0x98, 0x27, 0x3f, 0x13, 0x20,
2014 0x67, 0x05, 0xf9, 0x2f, 0x5a, 0xb1, 0x36, 0xb9, 0x96, 0x32, 0x1f, 0xf1, 2020 0xb8, 0x19, 0xa8, 0xa0, 0x2f, 0xdc, 0xfc, 0x5b, 0xbf, 0xdd, 0x58, 0xde,
2015 0x99, 0x94, 0x2b, 0x3c, 0x7b, 0x36, 0x2f, 0xa7, 0x18, 0x81, 0xea, 0x9c, 2021 0x3b, 0xd8, 0x88, 0xbb, 0x76, 0x3d, 0x8c, 0x9e, 0x5d, 0x7f, 0x8b, 0x4f,
2016 0x9c, 0x2f, 0x51, 0xce, 0x69, 0x62, 0x9e, 0x7a, 0xfd, 0x54, 0x59, 0x85, 2022 0x0e, 0x2d, 0xec, 0x9f, 0xe7, 0x71, 0x9c, 0xab, 0xdb, 0xa7, 0x70, 0x2a,
2017 0x76, 0xff, 0xf7, 0x79, 0x59, 0xb9, 0x72, 0x45, 0xd3, 0x51, 0x2a, 0x65, 2023 0xce, 0xd8, 0x18, 0x52, 0xf0, 0xbd, 0xab, 0x16, 0x8a, 0x1c, 0xfe, 0xbd,
2018 0xa7, 0xae, 0x7b, 0x17, 0xd1, 0x77, 0x43, 0xde, 0xf5, 0xf6, 0x7a, 0xb3, 2024 0xef, 0x68, 0xae, 0xbc, 0x5b, 0x4b, 0x3e, 0x92, 0x98, 0xc3, 0xf1, 0x53,
2019 0x8e, 0x15, 0x17, 0xe7, 0x4c, 0xf2, 0xde, 0x1b, 0xb9, 0x82, 0x17, 0x6f, 2025 0xf6, 0x8a, 0xfa, 0xd2, 0xbb, 0xc2, 0x7f, 0x40, 0x5b, 0x3f, 0x16, 0x19,
2020 0x33, 0x47, 0xca, 0xad, 0xbf, 0x4b, 0xfe, 0x65, 0xe0, 0xf1, 0x44, 0xb0, 2026 0xfc, 0x2b, 0xcb, 0x78, 0xcd, 0x49, 0xae, 0x96, 0x7a, 0x15, 0xa5, 0x36,
2021 0x75, 0xa5, 0xd2, 0x10, 0x9b, 0x4d, 0x6e, 0x81, 0x2a, 0x59, 0x93, 0x6e, 2027 0xfe, 0x96, 0x9c, 0x90, 0xbc, 0xd0, 0xe0, 0xff, 0x91, 0xeb, 0x44, 0x3e,
2022 0xb6, 0xff, 0x5f, 0x5e, 0x36, 0xd4, 0xcc, 0x3c, 0xcd, 0xa0, 0x2d, 0x05, 2028 0x9f, 0x95, 0xe5, 0xbf, 0xe4, 0x24, 0xbb, 0xe5, 0xbb, 0x94, 0x59, 0xc7,
2023 0x3b, 0x4e, 0xd8, 0xfb, 0x89, 0x06, 0x5e, 0xca, 0xbe, 0x92, 0x3f, 0x8f, 2029 0x67, 0x52, 0xae, 0xfc, 0xec, 0xf9, 0x92, 0x9c, 0x4a, 0x68, 0x0d, 0x45,
2024 0x28, 0x73, 0x1e, 0xe6, 0x9c, 0x4f, 0x5d, 0x13, 0x95, 0xf9, 0x0f, 0xa6, 2030 0x39, 0x9f, 0xa6, 0x9c, 0x33, 0x8b, 0x93, 0x50, 0xaf, 0x9d, 0x29, 0xab,
2025 0x33, 0xa8, 0x16, 0x1e, 0x68, 0x9a, 0xd0, 0xe9, 0x37, 0x26, 0x43, 0xd8, 2031 0xdc, 0xee, 0xff, 0x3a, 0x2f, 0xab, 0x58, 0xee, 0x6f, 0xe6, 0xc8, 0xbe,
2026 0x0d, 0x88, 0xfb, 0x64, 0x6f, 0xc1, 0x97, 0xff, 0x3f, 0x66, 0xac, 0xf7, 2032 0x80, 0x7a, 0xed, 0xcc, 0x75, 0xf2, 0x0a, 0xfa, 0x6f, 0x34, 0xb8, 0xd5,
2027 0x09, 0x6b, 0x3c, 0x60, 0xbd, 0xdc, 0x99, 0x33, 0x1d, 0xe6, 0xd8, 0xd5, 2033 0x5d, 0x9f, 0x36, 0xb0, 0xf6, 0xe2, 0x1c, 0x4b, 0xb0, 0x03, 0xe3, 0x76,
2028 0xc8, 0x78, 0x65, 0xfd, 0x00, 0xe6, 0x34, 0x23, 0x00, 0x9f, 0x76, 0x37, 2034 0xb0, 0x94, 0x53, 0xc9, 0x2d, 0x13, 0x5f, 0x66, 0xce, 0xf6, 0x94, 0x1d,
2029 0xc7, 0xed, 0xc2, 0x74, 0xe6, 0x47, 0x91, 0x99, 0x0d, 0x6d, 0x4d, 0xea, 2035 0xe9, 0x5a, 0xa7, 0xb4, 0x26, 0x17, 0x31, 0xce, 0xa0, 0x5e, 0xd6, 0xb0,
2030 0x15, 0x88, 0x55, 0xc9, 0x79, 0x22, 0x9d, 0xf6, 0x0f, 0x14, 0xf7, 0xca, 2036 0x13, 0xee, 0xef, 0xf9, 0xe5, 0xa3, 0x09, 0xe4, 0x69, 0x8f, 0xaf, 0xd8,
2031 0xf9, 0x0d, 0xb3, 0xd5, 0x8d, 0xa0, 0x7f, 0xae, 0xa2, 0xa0, 0x28, 0x04, 2037 0x91, 0x0d, 0xa7, 0xdc, 0xfd, 0x3b, 0x13, 0x2f, 0xe7, 0x5f, 0x2d, 0xed,
2032 0xe7, 0xfd, 0x59, 0xf2, 0xb0, 0x99, 0x1f, 0x59, 0x3f, 0xf2, 0xe9, 0xcc, 2038 0x33, 0x95, 0x7f, 0x4f, 0x6c, 0xe6, 0x1a, 0xaa, 0xcc, 0xbf, 0x9c, 0xb1,
2033 0xe7, 0x0b, 0x7d, 0xd0, 0xf1, 0xf5, 0xd1, 0x4b, 0x33, 0xc8, 0x82, 0xcc, 2039 0x6e, 0x90, 0xb5, 0x0a, 0xcb, 0xa2, 0x9f, 0xf7, 0x66, 0xac, 0xb0, 0x8a,
2034 0xf7, 0xad, 0xd8, 0x74, 0x69, 0x5b, 0xe4, 0x7e, 0x52, 0x5f, 0x73, 0x7d, 2040 0xeb, 0x90, 0x0a, 0xc9, 0xbe, 0xc4, 0xd6, 0xd2, 0x6f, 0x52, 0xb1, 0xde,
2035 0xfc, 0xa7, 0x59, 0xf5, 0x01, 0x07, 0x2a, 0xb1, 0x5e, 0x37, 0xa6, 0xcb, 2041 0xef, 0x58, 0x13, 0x02, 0x8c, 0xd2, 0x39, 0xb6, 0x18, 0xac, 0xc9, 0x2b,
2036 0xd9, 0xec, 0x7b, 0x65, 0x8d, 0xc5, 0x3e, 0xcf, 0x36, 0xf5, 0x5c, 0xd6, 2042 0xc8, 0xc5, 0x64, 0xbd, 0x01, 0xd6, 0x6c, 0x53, 0x43, 0x48, 0x3f, 0xcc,
2037 0xd4, 0x75, 0x63, 0x2f, 0xaa, 0x89, 0xe1, 0x25, 0x49, 0xd1, 0xf5, 0x35, 2043 0x71, 0xfb, 0x30, 0x87, 0xf9, 0x54, 0x7c, 0x61, 0x6b, 0x77, 0xbb, 0x3a,
2038 0x50, 0xa9, 0xef, 0x63, 0xc4, 0xa2, 0xe2, 0xa4, 0x87, 0x79, 0xab, 0x87, 2044 0x57, 0x70, 0x36, 0x98, 0x54, 0x63, 0x12, 0x07, 0x50, 0x99, 0x96, 0xb3,
2039 0x58, 0x67, 0xe0, 0xb9, 0x6c, 0x07, 0x5c, 0xe4, 0x4e, 0x13, 0xd9, 0x30, 2045 0x26, 0x56, 0x97, 0x9f, 0x98, 0xba, 0x98, 0xd8, 0x52, 0x11, 0x85, 0xf7,
2040 0x5e, 0xcd, 0xce, 0x99, 0x2e, 0xe7, 0x5e, 0xa9, 0x02, 0x38, 0x67, 0xca, 2046 0xbe, 0xbc, 0x17, 0xc1, 0x85, 0xbf, 0x70, 0x7e, 0x18, 0x8a, 0x61, 0xdb,
2041 0x6f, 0x53, 0xde, 0xe7, 0x53, 0x72, 0xbf, 0xdf, 0xb7, 0xdf, 0x35, 0x77, 2047 0x64, 0xb9, 0x0f, 0x06, 0xfe, 0x7b, 0xe1, 0xd2, 0x8c, 0xb3, 0x2c, 0xf3,
2042 0x18, 0x2b, 0x71, 0x4f, 0xa2, 0x4a, 0xd6, 0xda, 0x4d, 0x9f, 0x61, 0x5a, 2048 0x3d, 0x27, 0x39, 0x47, 0xda, 0x2e, 0xca, 0xfd, 0xe8, 0xbe, 0x4a, 0x1f,
2043 0xd3, 0xb4, 0xaa, 0xe9, 0xb9, 0xf3, 0x30, 0xc1, 0xf6, 0xa5, 0xc4, 0x91, 2049 0xa5, 0xaf, 0xcd, 0x1a, 0x51, 0x15, 0x5b, 0x8d, 0x89, 0x39, 0xf2, 0x9b,
2044 0xd5, 0x11, 0xad, 0xed, 0xbf, 0x2b, 0xc1, 0x40, 0x5a, 0x69, 0x63, 0xf9, 2050 0x3f, 0xf7, 0xb8, 0x67, 0xd3, 0x65, 0x0e, 0xe4, 0xfd, 0xf1, 0x04, 0xee,
2045 0x30, 0x36, 0x8f, 0x4a, 0x5d, 0x85, 0xe3, 0x2d, 0xec, 0x57, 0x37, 0x04, 2051 0x93, 0xf7, 0x30, 0x19, 0xb3, 0xee, 0xcd, 0xbb, 0xef, 0x77, 0x42, 0x7e,
2046 0x42, 0xea, 0xaf, 0x0b, 0x67, 0xa1, 0xdd, 0x45, 0x46, 0x1c, 0xcf, 0x26, 2052 0x17, 0xf1, 0xde, 0x7c, 0x51, 0x7f, 0x0f, 0xe5, 0x03, 0xe4, 0xdd, 0x01,
2047 0xa6, 0xcb, 0xff, 0x2c, 0x90, 0x35, 0x95, 0xbc, 0x4c, 0x8f, 0x59, 0x65, 2053 0xcb, 0x6b, 0x6e, 0x80, 0x4f, 0x97, 0x33, 0x67, 0x65, 0x5d, 0xfe, 0xdf,
2048 0x48, 0x5b, 0xed, 0x6c, 0xcb, 0x3c, 0xeb, 0x25, 0x86, 0xb8, 0xb4, 0xe0, 2054 0x73, 0x24, 0x97, 0xff, 0x2a, 0xfd, 0xc9, 0xbb, 0x50, 0x3e, 0x5b, 0xf2,
2049 0xd1, 0xaf, 0x22, 0xb8, 0x66, 0xbe, 0xa3, 0x13, 0x67, 0x22, 0x5a, 0xc7, 2055 0xae, 0xa2, 0x52, 0xfc, 0x7c, 0xc6, 0x7d, 0xef, 0x5d, 0x35, 0xd7, 0xd1,
2050 0x47, 0x6c, 0xa3, 0xca, 0x11, 0x46, 0x6f, 0x5e, 0xbe, 0xfc, 0x9f, 0xd8, 2056 0x2f, 0x67, 0xbb, 0xef, 0xeb, 0x89, 0x7e, 0x42, 0xa6, 0xe5, 0xcc, 0xd6,
2051 0x9c, 0xac, 0x86, 0x55, 0x45, 0xea, 0x69, 0x2b, 0x33, 0x3d, 0x27, 0xbf, 2057 0x03, 0xb4, 0x91, 0xde, 0x39, 0xa5, 0x77, 0x0f, 0xba, 0xee, 0x20, 0x8e,
2052 0xd8, 0x58, 0xce, 0xfc, 0xd8, 0x43, 0xb9, 0x72, 0xe6, 0x36, 0xb8, 0xf3, 2058 0x2c, 0x22, 0xb7, 0x5a, 0xac, 0x44, 0xb4, 0x55, 0x4a, 0x37, 0xeb, 0x51,
2053 0xd7, 0x30, 0xad, 0x6a, 0x4d, 0xeb, 0xf9, 0xaa, 0xda, 0x89, 0x15, 0x4d, 2059 0x4f, 0x05, 0x91, 0xa1, 0xb8, 0xbf, 0xbd, 0xeb, 0xa3, 0x8c, 0xfd, 0x76,
2054 0xc1, 0xc0, 0x32, 0xda, 0x48, 0x95, 0x2d, 0x23, 0x16, 0x2e, 0xfa, 0xd8, 2060 0xab, 0xe6, 0x53, 0x7f, 0x5e, 0x3a, 0x7b, 0x2d, 0x7b, 0xf1, 0x29, 0x3c,
2055 0x33, 0x71, 0xf4, 0x23, 0xc8, 0xba, 0x23, 0xcb, 0x95, 0xca, 0x99, 0x31, 2061 0x6f, 0xcf, 0xc1, 0xd4, 0x6f, 0xc9, 0x3d, 0xbf, 0x66, 0xfd, 0x4f, 0x41,
2056 0x79, 0xd7, 0xd4, 0x89, 0x85, 0x8c, 0x6f, 0xf1, 0xc2, 0xff, 0x74, 0xb2, 2062 0x62, 0x88, 0x4f, 0x8f, 0x6c, 0x8c, 0x7b, 0x22, 0xeb, 0xa7, 0xe9, 0xd3,
2057 0xf7, 0x86, 0xbe, 0x31, 0xfd, 0xc2, 0xff, 0xd9, 0xfd, 0xff, 0x01, 0x02, 2063 0x85, 0xb8, 0x9e, 0xfa, 0x1a, 0xdb, 0xf8, 0x3e, 0xb9, 0x85, 0x3d, 0x43,
2058 0x8b, 0x0c, 0x6e, 0x74, 0x57, 0x00, 0x00, 0x00 }; 2064 0x7e, 0x51, 0x56, 0x6b, 0x4f, 0x85, 0x7a, 0xc6, 0x29, 0xbe, 0x77, 0x2d,
2065 0xbf, 0xfb, 0xbb, 0x06, 0xc1, 0xb4, 0xe5, 0x84, 0x28, 0x73, 0xbe, 0x19,
2066 0xd9, 0x53, 0xaf, 0xea, 0xd9, 0xcf, 0xab, 0x9b, 0xb1, 0x56, 0x8e, 0x7c,
2067 0x98, 0x11, 0xed, 0xd3, 0xb4, 0x8f, 0x76, 0x57, 0x46, 0x32, 0x56, 0x81,
2068 0x8f, 0x3a, 0xd3, 0xc6, 0xf1, 0x41, 0xd6, 0x28, 0x59, 0xce, 0xdd, 0xe3,
2069 0x97, 0xf7, 0x77, 0x98, 0x63, 0xdb, 0xf2, 0xbb, 0xa6, 0x6e, 0x33, 0xa5,
2070 0x7d, 0x24, 0xe6, 0xc8, 0x8c, 0x97, 0xf7, 0xc8, 0x6f, 0xc8, 0x55, 0x07,
2071 0x70, 0xaf, 0x2d, 0xeb, 0x0e, 0xff, 0x3f, 0x45, 0x18, 0xff, 0x64, 0x3c,
2072 0x59, 0x00, 0x00, 0x00 };
2059 2073
2060static const u32 bnx2_CP_b09FwData[(0x84/4) + 1] = { 2074static const u32 bnx2_CP_b09FwData[(0x84/4) + 1] = {
2061 0x00000000, 0x0000001b, 0x0000000f, 0x0000000a, 0x00000008, 0x00000006, 2075 0x00000000, 0x0000001b, 0x0000000f, 0x0000000a, 0x00000008, 0x00000006,
@@ -2064,1091 +2078,1077 @@ static const u32 bnx2_CP_b09FwData[(0x84/4) + 1] = {
2064 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, 2078 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002,
2065 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, 2079 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002, 0x00000002,
2066 0x00000001, 0x00000001, 0x00000001, 0x00000000 }; 2080 0x00000001, 0x00000001, 0x00000001, 0x00000000 };
2067static const u32 bnx2_CP_b09FwRodata[(0x178/4) + 1] = { 2081static const u32 bnx2_CP_b09FwRodata[(0x16c/4) + 1] = {
2068 0x80080100, 0x80080080, 0x80080000, 0x080015a0, 0x080015d8, 0x08001600, 2082 0x80080100, 0x80080080, 0x80080000, 0x08001744, 0x08001744, 0x0800177c,
2069 0x08001600, 0x08001614, 0x080015bc, 0x080018a4, 0x0800186c, 0x080018f8, 2083 0x0800177c, 0x08001790, 0x08001760, 0x080019b8, 0x08001984, 0x08001a10,
2070 0x080018f8, 0x08001980, 0x080018b4, 0x80080240, 0x80080100, 0x80080080, 2084 0x08001a10, 0x08001a98, 0x080019c8, 0x80080240, 0x08003260, 0x080031cc,
2071 0x80080000, 0x08003148, 0x080030b4, 0x08003170, 0x08003198, 0x080031c0, 2085 0x08003288, 0x080032b0, 0x080032d8, 0x080032fc, 0x08003344, 0x08003320,
2072 0x080031e4, 0x0800322c, 0x08003208, 0x08003250, 0x0800311c, 0x08003344, 2086 0x08003368, 0x08003234, 0x0800345c, 0x0800344c, 0x080031e8, 0x080031e8,
2073 0x08003334, 0x080030d0, 0x080030d0, 0x080030d0, 0x080032a4, 0x080032a4, 2087 0x080031e8, 0x080033bc, 0x080033bc, 0x080031e8, 0x080031e8, 0x0800343c,
2074 0x080030d0, 0x080030d0, 0x08003324, 0x080030d0, 0x080030d0, 0x080030d0, 2088 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x0800342c, 0x080031e8,
2075 0x080030d0, 0x08003314, 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 2089 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8,
2076 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 2090 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8,
2077 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 0x08003304, 0x080030d0, 2091 0x080031e8, 0x0800341c, 0x080031e8, 0x080031e8, 0x0800340c, 0x080031e8,
2078 0x080030d0, 0x080032f4, 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 2092 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8,
2079 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 2093 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8,
2080 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 0x080030d0, 2094 0x080031e8, 0x080031e8, 0x080031e8, 0x080031e8, 0x080033f4, 0x080031e8,
2081 0x080030d0, 0x080032dc, 0x080030d0, 0x080030d0, 0x080032cc, 0x080032bc, 2095 0x080031e8, 0x080033e4, 0x080033d4, 0x08003d6c, 0x08003d40, 0x08003d0c,
2082 0x08003c0c, 0x08003be8, 0x08003bbc, 0x08003b9c, 0x08003b7c, 0x08003b24, 2096 0x08003ce0, 0x08003cc0, 0x08003c74, 0x80080100, 0x80080080, 0x80080000,
2083 0x80080100, 0x80080080, 0x80080000, 0x80080080, 0x00000000 }; 2097 0x80080080, 0x00000000 };
2084 2098
2085static struct fw_info bnx2_cp_fw_09 = { 2099static struct fw_info bnx2_cp_fw_09 = {
2086 /* Firmware version: 4.0.5 */ 2100 /* Firmware version: 4.4.23 */
2087 .ver_major = 0x4, 2101 .ver_major = 0x4,
2088 .ver_minor = 0x0, 2102 .ver_minor = 0x4,
2089 .ver_fix = 0x5, 2103 .ver_fix = 0x17,
2090 2104
2091 .start_addr = 0x08000074, 2105 .start_addr = 0x08000080,
2092 2106
2093 .text_addr = 0x08000000, 2107 .text_addr = 0x08000000,
2094 .text_len = 0x5770, 2108 .text_len = 0x5938,
2095 .text_index = 0x0, 2109 .text_index = 0x0,
2096 .gz_text = bnx2_CP_b09FwText, 2110 .gz_text = bnx2_CP_b09FwText,
2097 .gz_text_len = sizeof(bnx2_CP_b09FwText), 2111 .gz_text_len = sizeof(bnx2_CP_b09FwText),
2098 2112
2099 .data_addr = 0x08005900, 2113 .data_addr = 0x08005ac0,
2100 .data_len = 0x84, 2114 .data_len = 0x84,
2101 .data_index = 0x0, 2115 .data_index = 0x0,
2102 .data = bnx2_CP_b09FwData, 2116 .data = bnx2_CP_b09FwData,
2103 2117
2104 .sbss_addr = 0x08005988, 2118 .sbss_addr = 0x08005b44,
2105 .sbss_len = 0x99, 2119 .sbss_len = 0x91,
2106 .sbss_index = 0x0, 2120 .sbss_index = 0x0,
2107 2121
2108 .bss_addr = 0x08005a28, 2122 .bss_addr = 0x08005bd8,
2109 .bss_len = 0x20c, 2123 .bss_len = 0x19c,
2110 .bss_index = 0x0, 2124 .bss_index = 0x0,
2111 2125
2112 .rodata_addr = 0x08005770, 2126 .rodata_addr = 0x08005938,
2113 .rodata_len = 0x178, 2127 .rodata_len = 0x16c,
2114 .rodata_index = 0x0, 2128 .rodata_index = 0x0,
2115 .rodata = bnx2_CP_b09FwRodata, 2129 .rodata = bnx2_CP_b09FwRodata,
2116}; 2130};
2117 2131
2118static u8 bnx2_RXP_b09FwText[] = { 2132static u8 bnx2_RXP_b09FwText[] = {
2119 0xec, 0x5b, 0x7f, 0x70, 0x1c, 0xf5, 0x75, 0xff, 0x7c, 0xf7, 0xf6, 0xa4, 2133 0xec, 0x5c, 0x7f, 0x70, 0x1c, 0xd5, 0x7d, 0xff, 0xbc, 0xbd, 0xbd, 0xbb,
2120 0x95, 0x74, 0xba, 0x5b, 0x49, 0x27, 0xf9, 0x14, 0x8c, 0xb5, 0x8b, 0x56, 2134 0x95, 0x74, 0x3e, 0xed, 0x9d, 0x4e, 0xb2, 0x04, 0x06, 0xef, 0xa2, 0x95,
2121 0x27, 0x61, 0x19, 0x77, 0x4f, 0x3a, 0xd9, 0x4a, 0x66, 0x1b, 0x2e, 0xb6, 2135 0x74, 0x58, 0xc6, 0xec, 0x9d, 0x4e, 0xb6, 0x48, 0xb7, 0xc9, 0xd5, 0x36,
2122 0x63, 0xe4, 0x81, 0x82, 0xb0, 0x09, 0x31, 0x53, 0x26, 0xa8, 0xb6, 0x63, 2136 0x20, 0x17, 0x52, 0x84, 0xa1, 0xc1, 0xcc, 0x30, 0x9d, 0x1b, 0x63, 0x8c,
2123 0xc4, 0x8f, 0x34, 0x26, 0x61, 0x06, 0x11, 0x68, 0xd8, 0x48, 0x36, 0xa6, 2137 0xb0, 0x1d, 0xa2, 0x00, 0x33, 0xc8, 0x29, 0x13, 0x16, 0xfc, 0xb3, 0xf8,
2124 0xf6, 0x9e, 0xd6, 0x36, 0x12, 0xe0, 0x99, 0x74, 0x22, 0x64, 0x59, 0x36, 2138 0xa4, 0x93, 0x8d, 0x8c, 0xc9, 0xf4, 0xd7, 0x21, 0xcb, 0x8a, 0x81, 0x93,
2125 0xe4, 0xa4, 0x33, 0x90, 0x1f, 0x66, 0x5a, 0x6a, 0x81, 0xf9, 0x61, 0x88, 2139 0xce, 0x04, 0xda, 0x98, 0x69, 0xa8, 0x15, 0x6c, 0x53, 0x87, 0x5f, 0x21,
2126 0x0d, 0x84, 0x42, 0x02, 0x33, 0x99, 0x89, 0xf9, 0x11, 0xc7, 0x66, 0x68, 2140 0x19, 0x68, 0x4d, 0x9b, 0x99, 0xa8, 0x06, 0x1c, 0xd3, 0xa6, 0xd4, 0xb4,
2127 0x50, 0x5a, 0x92, 0x8a, 0x89, 0xea, 0x6f, 0xdf, 0xbb, 0x93, 0xf8, 0x61, 2141 0x0e, 0xb5, 0x8b, 0xeb, 0xd7, 0xef, 0x77, 0x4f, 0x97, 0x50, 0x42, 0xcb,
2128 0x3a, 0x4d, 0x3b, 0xd3, 0x3f, 0xf7, 0xcd, 0xdc, 0x68, 0xf7, 0xfb, 0x7d, 2142 0x64, 0xa6, 0x7f, 0xee, 0x77, 0xe6, 0xe6, 0xf6, 0xde, 0xfb, 0xbe, 0xef,
2129 0xef, 0x7d, 0xdf, 0xef, 0xf7, 0xbe, 0x3b, 0xa3, 0x5b, 0x23, 0x28, 0xc7, 2143 0x7b, 0xdf, 0xdf, 0x9f, 0xb7, 0x1a, 0xfb, 0xbe, 0x08, 0x6a, 0x31, 0x4b,
2130 0x1c, 0x54, 0xd2, 0x2f, 0xbd, 0xa5, 0xef, 0x5b, 0x1d, 0x4b, 0xed, 0xa5, 2144 0x73, 0xe8, 0x93, 0x19, 0x18, 0xbc, 0x27, 0xbd, 0x28, 0xb3, 0x88, 0x1e,
2131 0xfc, 0x1e, 0x0a, 0x43, 0xe5, 0xbf, 0x02, 0x01, 0x04, 0x10, 0x40, 0x00, 2145 0xbb, 0x02, 0x73, 0x55, 0x95, 0xc7, 0x05, 0x7c, 0xf2, 0xc9, 0x27, 0x9f,
2132 0x01, 0x04, 0x10, 0x40, 0x00, 0x01, 0x04, 0x10, 0x40, 0x00, 0x01, 0x04, 2146 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2,
2133 0x10, 0x40, 0x00, 0x01, 0x04, 0x10, 0x40, 0x00, 0x01, 0x04, 0x10, 0x40, 2147 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27,
2134 0x00, 0x01, 0x04, 0x10, 0x40, 0x00, 0x01, 0x04, 0x10, 0x40, 0x00, 0x01, 2148 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c,
2135 0x04, 0x10, 0x40, 0x00, 0x01, 0x04, 0x10, 0x40, 0x00, 0x01, 0x04, 0x10, 2149 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xf2, 0xc9,
2136 0x40, 0x00, 0x01, 0x04, 0x10, 0x40, 0x00, 0x01, 0xfc, 0x7f, 0x42, 0x08, 2150 0x27, 0x9f, 0x7c, 0xf2, 0xc9, 0x27, 0x9f, 0x7c, 0xfa, 0xff, 0xa4, 0x00,
2137 0xd0, 0xf9, 0x6f, 0xe5, 0xdc, 0x0f, 0x9a, 0xe2, 0x8c, 0x7c, 0x67, 0x85, 2151 0xa0, 0xf3, 0xf7, 0x9c, 0xd9, 0x0f, 0x34, 0xc5, 0x71, 0x37, 0x2e, 0xb5,
2138 0x05, 0x2d, 0xe4, 0xc4, 0xef, 0xd8, 0x68, 0x01, 0x99, 0x5c, 0xab, 0xb1, 2152 0xa0, 0x05, 0x9c, 0x33, 0x1b, 0x6f, 0xb7, 0x80, 0x6c, 0xa9, 0xd3, 0x58,
2139 0x12, 0xff, 0x29, 0xdd, 0xb8, 0x0a, 0x5e, 0x3f, 0xdf, 0x99, 0xfd, 0xc1, 2153 0x86, 0xff, 0x92, 0x6e, 0x42, 0x05, 0x8f, 0x5f, 0xe2, 0x9c, 0xff, 0xf3,
2140 0x13, 0xcb, 0xcd, 0xe9, 0x91, 0x10, 0x34, 0xdd, 0x79, 0x39, 0xa5, 0x27, 2154 0x17, 0x96, 0x98, 0xa7, 0x8b, 0x01, 0x68, 0xba, 0xf3, 0x46, 0x4a, 0x6f,
2141 0xa1, 0x2d, 0x24, 0x9a, 0xef, 0x37, 0x6f, 0xab, 0x46, 0x74, 0x9e, 0x17, 2155 0x87, 0x36, 0x8f, 0xd6, 0xfc, 0x49, 0xc7, 0x95, 0x71, 0x44, 0xab, 0xb2,
2142 0x5c, 0xc5, 0x91, 0x72, 0xbf, 0x2d, 0xf1, 0xac, 0xed, 0x8a, 0xae, 0x34, 2156 0xe0, 0x2a, 0x8e, 0x94, 0xfb, 0x6c, 0x89, 0x97, 0x6c, 0x57, 0xf4, 0x66,
2143 0xdc, 0x90, 0x73, 0x58, 0xdc, 0xe0, 0x9d, 0x95, 0x46, 0xb8, 0x78, 0xb2, 2157 0xe0, 0x06, 0x9c, 0x83, 0xe2, 0xae, 0xfc, 0x05, 0x69, 0x04, 0x2b, 0x3b,
2144 0x3a, 0xa1, 0x21, 0xbc, 0x1f, 0xba, 0xea, 0x28, 0x08, 0x5b, 0xe5, 0x28, 2158 0xab, 0x93, 0x1a, 0x82, 0xfb, 0xa0, 0xab, 0x8e, 0x82, 0xa0, 0x55, 0x8b,
2145 0x79, 0xb0, 0x02, 0xe1, 0x07, 0x13, 0x28, 0x9d, 0x38, 0x24, 0x7a, 0x46, 2159 0xd0, 0x13, 0x75, 0x08, 0x3e, 0xd1, 0x8c, 0xf0, 0xe4, 0x01, 0x91, 0x2b,
2146 0x34, 0x9c, 0x0c, 0x1d, 0x16, 0x9b, 0x72, 0xe8, 0x09, 0x3b, 0x33, 0x57, 2160 0x6a, 0x98, 0x09, 0x1c, 0x14, 0x6b, 0x4a, 0xc8, 0x05, 0x9d, 0xb3, 0x37,
2147 0x8c, 0x12, 0x5d, 0xa6, 0xf0, 0xff, 0x25, 0x53, 0x57, 0x8c, 0xe5, 0xa0, 2161 0x8c, 0xd1, 0xba, 0xac, 0xf7, 0xef, 0x4b, 0xa6, 0x6f, 0x18, 0x2f, 0x41,
2148 0x87, 0x1c, 0x28, 0xaa, 0xf3, 0x34, 0x3d, 0x33, 0xde, 0xcc, 0x15, 0xfb, 2162 0x0f, 0x38, 0x50, 0x54, 0xe7, 0x08, 0x3d, 0x33, 0xdf, 0xd9, 0x1b, 0xf6,
2149 0x72, 0xa7, 0xe5, 0x13, 0xcd, 0x71, 0x1c, 0xc9, 0xeb, 0x38, 0x94, 0xff, 2163 0x96, 0x4e, 0xc9, 0x17, 0x3a, 0x12, 0x38, 0x54, 0xd6, 0x71, 0xa0, 0xfc,
2150 0x25, 0xc9, 0x61, 0xba, 0x2e, 0x34, 0x57, 0x75, 0x5c, 0x6c, 0x4b, 0x87, 2164 0x10, 0x9d, 0xc3, 0x74, 0x5d, 0x68, 0xae, 0xea, 0xb8, 0xd8, 0x92, 0x09,
2151 0x31, 0xbe, 0xeb, 0xac, 0x0c, 0x59, 0xa6, 0x01, 0xc5, 0xd2, 0x8f, 0x82, 2165 0x62, 0x62, 0xe4, 0x82, 0x0c, 0x58, 0xa6, 0x01, 0xc5, 0xd2, 0x0f, 0x83,
2152 0xf0, 0x7c, 0xc2, 0xf3, 0xc3, 0x18, 0x1d, 0x79, 0xb3, 0x1a, 0xe5, 0x09, 2166 0xf8, 0x0a, 0xc4, 0x57, 0x08, 0x62, 0xac, 0xb8, 0x23, 0x8e, 0xda, 0x66,
2153 0x3c, 0xd1, 0xcc, 0xf4, 0x4c, 0xcb, 0x3c, 0x42, 0xb1, 0x79, 0xfa, 0x12, 2167 0xbc, 0xd0, 0xc1, 0xeb, 0x79, 0x2d, 0xcb, 0xf8, 0x38, 0x5a, 0x5d, 0x1f,
2154 0xa2, 0x7f, 0x26, 0x0d, 0x8c, 0xed, 0xea, 0x26, 0x52, 0x89, 0x01, 0xbb, 2168 0xa2, 0xf5, 0x47, 0x33, 0xc0, 0xf8, 0x48, 0x1f, 0x2d, 0x95, 0xd8, 0x64,
2155 0x14, 0x1b, 0x74, 0xb8, 0x65, 0x0e, 0xf3, 0x9a, 0xe7, 0xe3, 0x0a, 0x63, 2169 0x87, 0xb1, 0x5a, 0x87, 0x5b, 0xe3, 0xb0, 0xac, 0xaa, 0x1c, 0x57, 0x18,
2156 0x22, 0xaa, 0x17, 0xf9, 0x40, 0x68, 0x16, 0xdc, 0xd2, 0x73, 0xf6, 0x4f, 2170 0x93, 0xff, 0x5c, 0x5f, 0x91, 0x03, 0xa1, 0x59, 0x70, 0xc3, 0x9f, 0x9a,
2157 0xe7, 0xe6, 0xf7, 0xef, 0xa1, 0x73, 0x34, 0xda, 0xef, 0xc5, 0x4f, 0xf2, 2171 0x3f, 0x55, 0xaa, 0xce, 0x6f, 0xa7, 0x7d, 0x34, 0x9a, 0xef, 0xc7, 0x5f,
2158 0x9b, 0xf0, 0xe3, 0xfc, 0xb5, 0x78, 0x2c, 0xdf, 0x4d, 0xe7, 0xde, 0x4a, 2172 0x96, 0xd7, 0xe0, 0x2f, 0xca, 0xb7, 0xe1, 0xd9, 0x72, 0x1f, 0xed, 0x7b,
2159 0xe7, 0x6e, 0xc1, 0x3f, 0xe7, 0x6f, 0xc6, 0x4f, 0xf3, 0x3d, 0xf8, 0x51, 2173 0x1f, 0xed, 0x3b, 0x80, 0xbf, 0x2e, 0x6f, 0xc0, 0x77, 0xcb, 0x39, 0x3c,
2160 0x7e, 0x3d, 0x1e, 0xcd, 0x5f, 0x85, 0x47, 0xf2, 0x28, 0xc8, 0x70, 0x3a, 2174 0x57, 0x5e, 0x85, 0xef, 0x94, 0x6f, 0xc6, 0x33, 0x65, 0x78, 0x67, 0x38,
2161 0xdd, 0x22, 0x7e, 0xee, 0x95, 0x41, 0xdd, 0xbd, 0x15, 0x53, 0xb9, 0x30, 2175 0x95, 0x49, 0x8a, 0x1f, 0xe5, 0x6b, 0xa0, 0xee, 0xdc, 0x8c, 0xe9, 0x52,
2162 0xc2, 0xbb, 0x25, 0x76, 0xd9, 0xe6, 0x03, 0x40, 0xb3, 0x1e, 0x86, 0xc0, 2176 0x10, 0xc1, 0x9d, 0x12, 0x23, 0xb6, 0xf9, 0x38, 0xd0, 0xa1, 0x07, 0x21,
2163 0x4a, 0xdb, 0x3c, 0x08, 0x7c, 0x01, 0x3d, 0x71, 0xf3, 0x10, 0x50, 0x27, 2177 0xb0, 0xcc, 0x36, 0xf7, 0x03, 0x5f, 0x40, 0x2e, 0x61, 0x1e, 0x00, 0x9a,
2164 0x5e, 0x19, 0xaa, 0x13, 0x27, 0x86, 0x54, 0xf1, 0xa2, 0x27, 0x10, 0x73, 2178 0xc4, 0x8f, 0x47, 0x9b, 0xc4, 0x6b, 0xa3, 0xaa, 0x78, 0x3d, 0x2f, 0x50,
2165 0x10, 0x79, 0x21, 0x2d, 0xe5, 0xa5, 0x6d, 0x52, 0xe6, 0x52, 0x56, 0xd7, 2179 0xef, 0x20, 0xf2, 0x72, 0x46, 0xca, 0xeb, 0xd2, 0x52, 0x96, 0x52, 0x56,
2166 0x4b, 0xc2, 0xb4, 0x77, 0x88, 0x45, 0x30, 0x6a, 0xcd, 0xcc, 0x8d, 0x42, 2180 0xef, 0x0f, 0x85, 0x69, 0x3f, 0x22, 0x2e, 0x85, 0xd1, 0x68, 0x66, 0xd7,
2167 0x73, 0xcb, 0x89, 0xff, 0x9a, 0x0e, 0xc0, 0xda, 0x6d, 0x90, 0x1f, 0x58, 2181 0x09, 0xcd, 0xad, 0x25, 0xf9, 0x2b, 0xba, 0x01, 0x6b, 0xa7, 0x41, 0x7e,
2168 0xc7, 0x6d, 0xf8, 0x7a, 0x21, 0x26, 0xba, 0x51, 0x63, 0xad, 0xc4, 0xb7, 2182 0x60, 0x1d, 0x37, 0xe1, 0x0e, 0x2f, 0x26, 0xfa, 0xd0, 0x60, 0x2d, 0xc5,
2169 0xbb, 0x6d, 0x8c, 0xe4, 0xa1, 0x55, 0x39, 0x1f, 0x20, 0x35, 0x28, 0x60, 2183 0xbd, 0x7d, 0x36, 0x8a, 0x65, 0x68, 0x31, 0xe7, 0x0c, 0x52, 0xc3, 0x02,
2170 0x93, 0xbf, 0x05, 0x3d, 0xdb, 0xb9, 0x27, 0x6b, 0x8a, 0xfe, 0x26, 0xd9, 2184 0x36, 0xf9, 0x5b, 0xd0, 0xb3, 0x5d, 0x5a, 0xdf, 0x50, 0xf1, 0x37, 0x9d,
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3054 0x38, 0x91, 0xcc, 0xa7, 0x0e, 0x76, 0x61, 0x65, 0xd0, 0x1b, 0x18, 0xa2, 3068 0xd7, 0x6b, 0x13, 0x2a, 0xa6, 0xd4, 0x4c, 0x1e, 0x39, 0x96, 0xd4, 0xd6,
3055 0xef, 0xbd, 0xa0, 0x8b, 0x9d, 0x4a, 0xed, 0xd7, 0x43, 0x0c, 0x0d, 0x08, 3069 0xe7, 0xdb, 0xe4, 0x0c, 0xc5, 0x55, 0xeb, 0x3d, 0xeb, 0x88, 0xed, 0x9f,
3056 0x06, 0xaa, 0x29, 0xf1, 0xc9, 0xb4, 0x3d, 0xe1, 0xd8, 0x0e, 0xea, 0xc6, 3070 0x89, 0x47, 0xcd, 0x18, 0xd8, 0xff, 0x3e, 0x63, 0x90, 0x3c, 0xe3, 0x77,
3057 0xd6, 0xe1, 0xb7, 0xd0, 0x12, 0x95, 0x7c, 0xeb, 0x71, 0x3c, 0x9a, 0xa4, 3071 0xcc, 0xaf, 0x9d, 0x58, 0xdd, 0xe6, 0xc1, 0x83, 0x71, 0xa9, 0x9d, 0xae,
3058 0x0f, 0xd2, 0x68, 0xb7, 0x8b, 0x1c, 0xd0, 0xca, 0x24, 0x27, 0xec, 0xc0, 3072 0xaf, 0xca, 0x9c, 0x01, 0x91, 0xef, 0x0e, 0x74, 0xe8, 0x04, 0xd9, 0xea,
3059 0xda, 0xf8, 0x7c, 0x44, 0xaa, 0xa4, 0xae, 0xb2, 0x12, 0xdb, 0x07, 0x15, 3073 0x2f, 0xcc, 0x4a, 0x2b, 0x2f, 0xfd, 0xbf, 0x19, 0x9b, 0x49, 0xe4, 0x2d,
3060 0xfc, 0x56, 0x6a, 0x98, 0x8c, 0xc1, 0x5f, 0x27, 0x47, 0x9c, 0x8c, 0x6e, 3074 0x14, 0x1f, 0xef, 0x9d, 0x64, 0x02, 0x69, 0xd9, 0x5d, 0x15, 0xbf, 0xcb,
3061 0xc1, 0x88, 0x59, 0xa3, 0xd6, 0xfa, 0xaa, 0xed, 0xe1, 0x17, 0x4b, 0xc9, 3075 0x5c, 0xda, 0x81, 0xed, 0xd8, 0x56, 0x25, 0x7c, 0xe6, 0xc9, 0x89, 0xd9,
3062 0xb7, 0x13, 0xba, 0xbf, 0x9d, 0xf6, 0xe8, 0x29, 0x6a, 0xf2, 0x87, 0x63, 3076 0xf7, 0xe7, 0xea, 0x32, 0x95, 0x59, 0x4e, 0x95, 0xb3, 0x37, 0xe9, 0x05,
3063 0xca, 0x57, 0xf8, 0x37, 0xf3, 0xae, 0x8d, 0xee, 0xda, 0x44, 0x5d, 0xdf, 3077 0x46, 0x94, 0x27, 0xa2, 0x2d, 0xca, 0xda, 0xa8, 0xf4, 0x03, 0x6d, 0xd1,
3064 0x33, 0x2c, 0xfd, 0xb8, 0xc7, 0x5b, 0xe6, 0x3a, 0xac, 0x77, 0xdd, 0xad, 3078 0x22, 0x72, 0x18, 0xdf, 0x52, 0x13, 0xdf, 0x0e, 0x1d, 0x57, 0x76, 0x5a,
3065 0xbc, 0xe4, 0x5b, 0x38, 0x98, 0x76, 0xe1, 0xa9, 0xb8, 0x47, 0xb1, 0xef, 3079 0xe7, 0x66, 0xe5, 0xac, 0x2b, 0x50, 0x3e, 0xd1, 0xac, 0xec, 0x8a, 0x7e,
3066 0x51, 0xd1, 0x12, 0xf7, 0x9e, 0xbc, 0x60, 0x37, 0x8c, 0xba, 0xc5, 0x25, 3080 0x62, 0x6e, 0xb4, 0x7a, 0xf0, 0x79, 0xd6, 0x79, 0x9c, 0xfc, 0x09, 0x17,
3067 0x98, 0x21, 0xbf, 0xa8, 0x5c, 0x2c, 0x3e, 0xe1, 0x3f, 0x23, 0x55, 0xd5, 3081 0xca, 0x8e, 0xc8, 0xf9, 0x41, 0x0d, 0x15, 0x13, 0x8f, 0x91, 0xb7, 0x0a,
3068 0x4c, 0x6c, 0x43, 0xa1, 0x6d, 0x89, 0x57, 0xb7, 0xd9, 0x7d, 0xad, 0x33, 3082 0xd7, 0x31, 0x5a, 0x1c, 0xd6, 0xb9, 0xb6, 0xe6, 0x97, 0x72, 0xe7, 0xda,
3069 0xd8, 0x8a, 0xbc, 0xb1, 0x07, 0xcc, 0x75, 0x7f, 0x23, 0x2e, 0xef, 0x2f, 3083 0x1c, 0x31, 0x79, 0x1b, 0xd9, 0xfa, 0x8f, 0xb9, 0xd2, 0x51, 0xe6, 0x4a,
3070 0xd5, 0x53, 0xdf, 0xe8, 0x27, 0x0f, 0x89, 0x0c, 0x11, 0xa9, 0x6c, 0x82, 3084 0x66, 0xd3, 0xb7, 0x43, 0xc6, 0xee, 0x0a, 0x78, 0x03, 0xe5, 0x36, 0xc3,
3071 0xa7, 0xa2, 0x69, 0xd7, 0x7c, 0xe4, 0x7f, 0x45, 0xce, 0x3d, 0x8d, 0x89, 3085 0x94, 0x7a, 0xce, 0x6b, 0x24, 0x8c, 0xeb, 0x6a, 0x0d, 0x3c, 0x5c, 0x2b,
3072 0xa4, 0xd6, 0x51, 0x62, 0x33, 0x70, 0x3a, 0x78, 0x27, 0x52, 0x66, 0x0d, 3086 0xef, 0x1f, 0xca, 0xbb, 0xc7, 0x5d, 0x38, 0x1a, 0xea, 0xc2, 0x2f, 0xf5,
3073 0x63, 0x25, 0xfa, 0x07, 0x25, 0x3f, 0xaf, 0x40, 0x5b, 0x54, 0x40, 0xce, 3087 0x2e, 0xec, 0xd1, 0xe5, 0x4c, 0x43, 0x31, 0x65, 0xd5, 0xa6, 0xa2, 0xd0,
3074 0xa7, 0x05, 0x5e, 0xb4, 0x49, 0xcd, 0x79, 0x0b, 0xbe, 0xc1, 0xbd, 0xde, 3088 0xf4, 0xb4, 0xa2, 0x9d, 0xb9, 0x0e, 0xef, 0x01, 0x9f, 0xe2, 0x35, 0x56,
3075 0x1f, 0x15, 0x7b, 0xd5, 0xdc, 0x6d, 0x4a, 0xf8, 0xaa, 0x9d, 0x7b, 0xfd, 3089 0x29, 0x1a, 0xae, 0x8e, 0x7b, 0x67, 0x4a, 0xe9, 0x03, 0x37, 0xc6, 0x03,
3076 0xb5, 0xee, 0x3f, 0xf9, 0x6b, 0xbb, 0x7f, 0x2a, 0x64, 0xd7, 0x5d, 0x93, 3090 0x98, 0x21, 0xae, 0x26, 0x27, 0xe5, 0xfc, 0xc9, 0x02, 0x0c, 0x4d, 0x7e,
3077 0xe3, 0x2a, 0x31, 0xc4, 0x8a, 0x31, 0xd3, 0xe4, 0xb4, 0x85, 0x1c, 0xb7, 3091 0x4d, 0xb8, 0x81, 0x41, 0x4c, 0xb2, 0xce, 0x48, 0x3e, 0x2f, 0xbd, 0x4e,
3078 0x20, 0x78, 0x89, 0xdc, 0x40, 0xc6, 0x5d, 0x3e, 0x0f, 0xc5, 0x2d, 0xe8, 3092 0x67, 0x30, 0xcb, 0x61, 0x0c, 0x65, 0x53, 0x43, 0x09, 0x6e, 0x30, 0x3a,
3079 0xdf, 0xfb, 0xa1, 0x11, 0x6e, 0x93, 0x39, 0xfe, 0xc0, 0xb8, 0xd4, 0x89, 3093 0xfd, 0x6d, 0xba, 0x93, 0xf9, 0x1c, 0xde, 0xa8, 0x81, 0xfd, 0x3b, 0x6e,
3080 0x95, 0x6b, 0x3d, 0x58, 0x11, 0x97, 0x9c, 0xea, 0x8f, 0x2b, 0x2d, 0xdd, 3094 0xd4, 0x25, 0xe7, 0xe0, 0x44, 0x5d, 0x39, 0xf2, 0x70, 0x6c, 0xf4, 0x45,
3081 0x92, 0xef, 0x0e, 0x74, 0xe8, 0x04, 0xdb, 0xaa, 0x2f, 0x8d, 0x0a, 0x33, 3095 0x72, 0xfc, 0xee, 0xf6, 0x52, 0xe6, 0xa7, 0x13, 0xa3, 0x4e, 0xa4, 0x52,
3082 0x66, 0xbd, 0x6f, 0xbe, 0xe8, 0x4b, 0x6f, 0xe2, 0x85, 0xf9, 0x62, 0xdf, 3096 0x52, 0x73, 0xb0, 0x7a, 0x96, 0xd3, 0x0e, 0xfa, 0x52, 0x7f, 0x02, 0x75,
3083 0xbd, 0x13, 0x4f, 0xbb, 0x2d, 0xbd, 0x7b, 0x99, 0xdf, 0x65, 0x2c, 0x6d, 3097 0x35, 0x61, 0x7f, 0xb2, 0xc6, 0xae, 0x72, 0x8e, 0x4a, 0xa4, 0xd2, 0x1a,
3084 0xdf, 0x16, 0x9c, 0xa9, 0x14, 0x5e, 0xf3, 0xe8, 0xf8, 0xec, 0xf6, 0x56, 3098 0x3f, 0x01, 0x7e, 0x82, 0xfc, 0x34, 0xe2, 0xdb, 0xf4, 0xd9, 0x32, 0xe2,
3085 0xbd, 0xea, 0xf5, 0x6b, 0xb9, 0x1a, 0xa9, 0x13, 0x86, 0x95, 0xb6, 0x68, 3099 0xed, 0xf7, 0xd3, 0x25, 0xf8, 0x24, 0xa9, 0x05, 0x74, 0xda, 0xc1, 0x28,
3086 0xab, 0xb2, 0x3a, 0x2a, 0xb5, 0x42, 0x5b, 0xa8, 0x80, 0x1c, 0xe6, 0x98, 3100 0x73, 0x04, 0xc3, 0xd2, 0x53, 0x09, 0xae, 0xd3, 0x4f, 0x5f, 0x0e, 0x95,
3087 0x2e, 0xef, 0xea, 0x65, 0xeb, 0x86, 0x11, 0xa5, 0x2f, 0x44, 0xc6, 0x33, 3101 0xc0, 0x4c, 0xdd, 0x2d, 0x27, 0x94, 0xdc, 0x16, 0x6a, 0x61, 0x58, 0xf8,
3088 0xd6, 0xac, 0xec, 0x88, 0x96, 0xc9, 0x5d, 0x07, 0xea, 0xa5, 0x83, 0x32, 3102 0xe2, 0x31, 0x25, 0x95, 0x3d, 0xf3, 0xf5, 0xea, 0x38, 0xda, 0xcb, 0xc3,
3089 0x75, 0x21, 0x67, 0x54, 0x62, 0xf2, 0x02, 0xe4, 0x1c, 0xd0, 0x90, 0x3b, 3103 0xae, 0xe0, 0xea, 0xb8, 0xfd, 0x13, 0x79, 0x9f, 0x75, 0x43, 0x83, 0xbc,
3090 0xd6, 0x8e, 0x11, 0x32, 0xb8, 0x92, 0xda, 0x72, 0x1c, 0x0a, 0xc8, 0x5d, 3104 0xf3, 0xe4, 0x0a, 0x3e, 0x3d, 0xe1, 0x0a, 0xae, 0x8f, 0x1f, 0x53, 0x28,
3091 0x8e, 0x0a, 0x14, 0x09, 0xb6, 0x6a, 0x3d, 0x78, 0xb5, 0x0d, 0x4a, 0x41, 3105 0xcf, 0x81, 0x1a, 0xbb, 0x2b, 0xf8, 0xe4, 0xc4, 0xb1, 0x85, 0x99, 0xbc,
3092 0xed, 0x6c, 0x9e, 0x6a, 0xde, 0x5f, 0x57, 0xdd, 0x4d, 0xe2, 0xdb, 0x25, 3106 0x0f, 0xca, 0xd3, 0xb5, 0x06, 0x6d, 0x8c, 0x79, 0xef, 0x32, 0xe9, 0xcb,
3093 0xc7, 0x6f, 0xd5, 0x1d, 0xcf, 0xa6, 0x37, 0x60, 0x4c, 0xe5, 0xb2, 0xb5, 3107 0x68, 0x9d, 0x57, 0xec, 0x85, 0x46, 0x4d, 0xd8, 0xeb, 0xa9, 0xb1, 0xcb,
3094 0x7f, 0x33, 0xc6, 0x2b, 0xcc, 0x77, 0x7e, 0xc8, 0x81, 0x0f, 0x93, 0x03, 3108 0xd9, 0x90, 0x69, 0xc4, 0x93, 0xf2, 0xae, 0x97, 0xd8, 0xfe, 0x3f, 0x99,
3095 0x1b, 0xcb, 0xba, 0x82, 0x91, 0x9f, 0xd5, 0xc0, 0xdb, 0xa7, 0xdb, 0xbd, 3109 0x46, 0x99, 0x9c, 0xf5, 0xe8, 0x44, 0x5c, 0x2b, 0x67, 0xee, 0x24, 0x67,
3096 0x9e, 0x46, 0x9b, 0xe4, 0x10, 0xa0, 0xe4, 0xd4, 0x46, 0x90, 0x5b, 0x5b, 3110 0xcd, 0x8f, 0x86, 0xa2, 0xb1, 0x62, 0x79, 0x77, 0xb6, 0xe9, 0x7b, 0x21,
3097 0x18, 0xb1, 0x53, 0xbf, 0xcf, 0xe8, 0x22, 0xfb, 0x2e, 0xec, 0xd4, 0xf3, 3111 0x6f, 0xcb, 0xa0, 0x62, 0x3c, 0x5e, 0x04, 0xd9, 0xd7, 0x2e, 0xe2, 0xb7,
3098 0xe5, 0x7d, 0xf9, 0x48, 0x31, 0x79, 0x4b, 0x0c, 0x9a, 0x7a, 0x1a, 0xda, 3112 0xa6, 0x3a, 0x15, 0x6f, 0x63, 0x0f, 0x02, 0x38, 0x91, 0x16, 0x5d, 0x07,
3099 0xcc, 0x27, 0xec, 0xb7, 0x82, 0xf6, 0xd0, 0x3d, 0xe6, 0x0d, 0x5f, 0x54, 3113 0xe5, 0x8c, 0xba, 0xa5, 0xeb, 0x5b, 0x67, 0xae, 0x33, 0xb6, 0xb3, 0x2d,
3100 0xbc, 0x53, 0x77, 0xd3, 0x46, 0x5e, 0x19, 0xa3, 0x1d, 0x12, 0x77, 0xfb, 3114 0xea, 0xe0, 0x5f, 0xb1, 0x17, 0x1b, 0x63, 0x0a, 0xe3, 0x8a, 0x65, 0x33,
3101 0x69, 0x03, 0x7d, 0xb4, 0x85, 0x7d, 0x13, 0x87, 0x84, 0x47, 0xf4, 0xb5, 3115 0xb7, 0x64, 0x5c, 0x57, 0xdb, 0x85, 0xc9, 0x50, 0xa1, 0xbc, 0x77, 0xcd,
3102 0x2b, 0xd6, 0x3d, 0x4c, 0xab, 0xde, 0x2e, 0x35, 0xb5, 0x88, 0xb2, 0x21, 3116 0xb8, 0xee, 0x0d, 0x7c, 0xa2, 0x58, 0xf1, 0xdc, 0x28, 0x62, 0x9c, 0x7d,
3103 0x24, 0x7e, 0xb0, 0x08, 0xe7, 0x93, 0xc0, 0x91, 0x74, 0x0e, 0x5e, 0x1b, 3117 0x61, 0xfc, 0xef, 0xcc, 0xf6, 0x6a, 0xc1, 0x2b, 0x3b, 0xc7, 0x5e, 0xc7,
3104 0x41, 0x8b, 0x0d, 0xf6, 0x5e, 0x17, 0xea, 0xd6, 0xa9, 0x78, 0xa3, 0xae, 3118 0x6b, 0xa9, 0x5b, 0xe3, 0x5a, 0x38, 0xae, 0x90, 0xe3, 0x8a, 0xc2, 0x92,
3105 0x40, 0xfe, 0x87, 0x11, 0x15, 0x9d, 0x8c, 0x09, 0xcb, 0xb0, 0x62, 0xb7, 3119 0x3b, 0x7a, 0xf5, 0xb5, 0x8a, 0xe6, 0x29, 0x50, 0xa4, 0x57, 0xa6, 0xe1,
3106 0xb1, 0xec, 0xae, 0x45, 0xc6, 0xb2, 0xcd, 0xfa, 0x63, 0x58, 0x63, 0x62, 3120 0xbd, 0xf4, 0xe4, 0x42, 0xc9, 0x79, 0x7b, 0x27, 0xcb, 0xb1, 0x6e, 0xaf,
3107 0x4c, 0x77, 0x7b, 0x01, 0xe3, 0xdb, 0x1f, 0x8e, 0x38, 0x91, 0x4a, 0xb1, 3121 0xd9, 0xb4, 0x68, 0xa9, 0xd9, 0x94, 0x0e, 0x45, 0xcd, 0x97, 0xab, 0x64,
3108 0x17, 0xe5, 0x35, 0x9c, 0xc2, 0x03, 0x0e, 0x62, 0x27, 0xfd, 0x58, 0x5d, 3122 0x4f, 0xa5, 0xff, 0x27, 0x63, 0x34, 0xd5, 0xc7, 0x5c, 0xf3, 0x6b, 0x7a,
3109 0x71, 0x93, 0xbf, 0xed, 0x6e, 0x85, 0xbc, 0x32, 0x5d, 0x81, 0x54, 0x5a, 3123 0x6f, 0xf6, 0xcc, 0x2e, 0xed, 0x9a, 0xcf, 0x38, 0x9d, 0x12, 0x3b, 0xd9,
3110 0xe3, 0x5f, 0x80, 0x7f, 0x0d, 0xfc, 0x6b, 0xc4, 0x9a, 0xa8, 0xe8, 0xa8, 3124 0xd1, 0xee, 0x62, 0x3e, 0x2a, 0xef, 0x87, 0x1e, 0xe5, 0xfe, 0x1f, 0x49,
3111 0x1b, 0x63, 0xe9, 0x22, 0x7c, 0x98, 0xd4, 0x02, 0x2e, 0xea, 0xcf, 0x88, 3125 0xfd, 0xcd, 0x42, 0x39, 0xc3, 0x2e, 0x67, 0x08, 0x80, 0xff, 0x0f, 0x1d,
3112 0x3e, 0x6e, 0x44, 0xda, 0xac, 0x38, 0xe4, 0xf3, 0xa4, 0xe4, 0x74, 0x8a, 3126 0xab, 0x22, 0x97, 0x70, 0x78, 0x00, 0x00, 0x00 };
3113 0xf0, 0x59, 0xea, 0xf4, 0x7c, 0x8b, 0xdb, 0x77, 0xe1, 0x62, 0x30, 0x3f,
3114 0x52, 0x6a, 0xfa, 0x1c, 0x6f, 0xe0, 0x35, 0x68, 0xeb, 0xae, 0x70, 0xdf,
3115 0xbb, 0xc6, 0x52, 0xc6, 0xb9, 0x0a, 0xb1, 0xf5, 0xe3, 0xf8, 0x49, 0xf2,
3116 0x8a, 0x51, 0x23, 0x9c, 0x33, 0x21, 0xf7, 0xf5, 0xad, 0x3c, 0x8b, 0xc4,
3117 0x46, 0x85, 0x4b, 0x67, 0x9f, 0xc9, 0x71, 0xa4, 0x53, 0xb3, 0xcf, 0x05,
3118 0xed, 0x8e, 0x26, 0x57, 0xc3, 0x8e, 0xa8, 0xfd, 0x4a, 0x3e, 0x79, 0xd4,
3119 0xfd, 0x4b, 0x34, 0xbd, 0x4e, 0x71, 0x35, 0xf4, 0xa6, 0x5d, 0x0d, 0x7d,
3120 0xd1, 0xd9, 0xe7, 0x7a, 0x44, 0xb1, 0x37, 0xc9, 0x38, 0x7e, 0xc6, 0xdc,
3121 0xd9, 0xb1, 0x5c, 0x0d, 0xdd, 0xe9, 0xd9, 0x63, 0x75, 0xa1, 0x23, 0x28,
3122 0x67, 0xe4, 0xdd, 0xe4, 0xbc, 0xa1, 0x6e, 0x20, 0x3e, 0xdc, 0x7c, 0xcf,
3123 0xa5, 0xe3, 0xbb, 0xd7, 0xfa, 0x6a, 0xc4, 0x32, 0xfa, 0xc5, 0x89, 0xd9,
3124 0xfd, 0xa7, 0xf1, 0x6e, 0xd2, 0xfc, 0x7f, 0x06, 0x74, 0x7c, 0xce, 0x18,
3125 0xf1, 0x54, 0xf0, 0xb0, 0xe1, 0x29, 0x15, 0x19, 0x1f, 0xc7, 0x07, 0xdc,
3126 0x5b, 0xa1, 0xb6, 0xb5, 0xdd, 0xad, 0x69, 0x27, 0x3f, 0xb6, 0x3b, 0x50,
3127 0xb7, 0xf4, 0x38, 0x4e, 0xa4, 0xe4, 0x0c, 0x8b, 0xcc, 0x77, 0x6d, 0x27,
3128 0x79, 0x06, 0x07, 0x53, 0xc5, 0xb7, 0xcb, 0xfd, 0x75, 0xbb, 0xdc, 0x63,
3129 0xc6, 0xff, 0x07, 0xb6, 0x0b, 0xca, 0xea, 0xc4, 0x79, 0x00, 0x00, 0x00 };
3130 3127
3131static const u32 bnx2_RXP_b09FwData[(0x0/4) + 1] = { 0x0 }; 3128static const u32 bnx2_RXP_b09FwData[(0x0/4) + 1] = { 0x0 };
3132static const u32 bnx2_RXP_b09FwRodata[(0xb0/4) + 1] = { 3129static const u32 bnx2_RXP_b09FwRodata[(0xf0/4) + 1] = {
3133 0x80080100, 0x80080080, 0x80080000, 0x08005054, 0x08005054, 0x08005130, 3130 0x5f865437, 0xe4ac62cc, 0x50103a45, 0x36621985, 0xbf14c0e8, 0x1bc27a1e,
3134 0x08005104, 0x080050e8, 0x08005024, 0x08005024, 0x08005024, 0x0800505c, 3131 0x84f4b556, 0x094ea6fe, 0x7dda01e7, 0xc04d7481, 0x80080100, 0x80080080,
3135 0x080073b8, 0x08007404, 0x080073c4, 0x080072ec, 0x080073c4, 0x080073f4, 3132 0x80080000, 0x08004efc, 0x08004efc, 0x08004fd8, 0x08004fac, 0x08004f90,
3136 0x080073c4, 0x080072ec, 0x080072ec, 0x080072ec, 0x080072ec, 0x080072ec, 3133 0x08004ecc, 0x08004ecc, 0x08004ecc, 0x08004f04, 0x08007220, 0x0800726c,
3137 0x080072ec, 0x080072ec, 0x080072ec, 0x080072ec, 0x080072ec, 0x080073e4, 3134 0x0800722c, 0x08007150, 0x0800722c, 0x0800725c, 0x0800722c, 0x08007150,
3138 0x080073d4, 0x080072ec, 0x080072ec, 0x080072ec, 0x080072ec, 0x080072ec, 3135 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x08007150,
3139 0x080072ec, 0x080072ec, 0x080072ec, 0x080072ec, 0x080072ec, 0x080072ec, 3136 0x08007150, 0x08007150, 0x08007150, 0x0800724c, 0x0800723c, 0x08007150,
3140 0x080072ec, 0x080073d4, 0x00000000 }; 3137 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x08007150,
3138 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x08007150, 0x0800723c,
3139 0x080077f4, 0x080076bc, 0x080077bc, 0x08007718, 0x080076e8, 0x080075a4,
3140 0x00000000 };
3141 3141
3142static struct fw_info bnx2_rxp_fw_09 = { 3142static struct fw_info bnx2_rxp_fw_09 = {
3143 /* Firmware version: 4.0.5 */ 3143 /* Firmware version: 4.4.23 */
3144 .ver_major = 0x4, 3144 .ver_major = 0x4,
3145 .ver_minor = 0x0, 3145 .ver_minor = 0x4,
3146 .ver_fix = 0x5, 3146 .ver_fix = 0x17,
3147 3147
3148 .start_addr = 0x080031d0, 3148 .start_addr = 0x080031d0,
3149 3149
3150 .text_addr = 0x08000000, 3150 .text_addr = 0x08000000,
3151 .text_len = 0x79c0, 3151 .text_len = 0x786c,
3152 .text_index = 0x0, 3152 .text_index = 0x0,
3153 .gz_text = bnx2_RXP_b09FwText, 3153 .gz_text = bnx2_RXP_b09FwText,
3154 .gz_text_len = sizeof(bnx2_RXP_b09FwText), 3154 .gz_text_len = sizeof(bnx2_RXP_b09FwText),
@@ -3158,522 +3158,532 @@ static struct fw_info bnx2_rxp_fw_09 = {
3158 .data_index = 0x0, 3158 .data_index = 0x0,
3159 .data = bnx2_RXP_b09FwData, 3159 .data = bnx2_RXP_b09FwData,
3160 3160
3161 .sbss_addr = 0x08007aa0, 3161 .sbss_addr = 0x08007980,
3162 .sbss_len = 0x58, 3162 .sbss_len = 0x58,
3163 .sbss_index = 0x0, 3163 .sbss_index = 0x0,
3164 3164
3165 .bss_addr = 0x08007af8, 3165 .bss_addr = 0x080079d8,
3166 .bss_len = 0x1c, 3166 .bss_len = 0x1c,
3167 .bss_index = 0x0, 3167 .bss_index = 0x0,
3168 3168
3169 .rodata_addr = 0x080079c0, 3169 .rodata_addr = 0x0800786c,
3170 .rodata_len = 0xb0, 3170 .rodata_len = 0xf0,
3171 .rodata_index = 0x0, 3171 .rodata_index = 0x0,
3172 .rodata = bnx2_RXP_b09FwRodata, 3172 .rodata = bnx2_RXP_b09FwRodata,
3173}; 3173};
3174 3174
3175static u8 bnx2_xi_rv2p_proc1[] = { 3175static u8 bnx2_xi_rv2p_proc1[] = {
3176 /* Date: 04/25/2008 22:02 */ 3176 /* Date: 06/17/2008 16:52 */
3177 0xbd, 0x56, 0x4f, 0x68, 0x1c, 0x55, 0x18, 0xff, 0x76, 0x76, 0x77, 0x66, 3177 0xbd, 0x56, 0xcf, 0x6b, 0x1c, 0x75, 0x14, 0x7f, 0x3b, 0xbb, 0x33, 0x3b,
3178 0x33, 0x3b, 0xbb, 0xb3, 0xd8, 0x34, 0x4c, 0xb7, 0x2b, 0x59, 0x83, 0x97, 3178 0x99, 0x9d, 0xdd, 0x99, 0xda, 0x34, 0x4c, 0xb7, 0x2b, 0xd9, 0x86, 0x5e,
3179 0xdd, 0x6c, 0x69, 0xa2, 0x15, 0x04, 0x53, 0x5a, 0x72, 0x09, 0xd8, 0x9e, 3179 0x36, 0x99, 0x62, 0xa2, 0x11, 0x0a, 0x46, 0x5b, 0x72, 0x09, 0xd8, 0x9e,
3180 0x02, 0xb5, 0x52, 0x84, 0xb6, 0x8b, 0xf4, 0x52, 0x5a, 0x28, 0x78, 0x11, 3180 0x02, 0x95, 0x22, 0x82, 0x71, 0xa9, 0x3d, 0xd8, 0x96, 0xe2, 0x5f, 0xe0,
3181 0x84, 0x0e, 0x6d, 0x93, 0x82, 0xe8, 0x61, 0xc1, 0x06, 0x12, 0x44, 0xa3, 3181 0x90, 0x9a, 0x08, 0x45, 0x0f, 0x0b, 0x36, 0x90, 0x20, 0x1a, 0x7b, 0x50,
3182 0x07, 0x95, 0x60, 0x61, 0x07, 0x3c, 0x78, 0x10, 0x14, 0x15, 0x11, 0x6c, 3182 0x09, 0x0a, 0x3b, 0x07, 0x41, 0x44, 0x2d, 0xa8, 0x88, 0x60, 0x3d, 0x08,
3183 0x0f, 0x85, 0x88, 0xf6, 0xd2, 0x54, 0x4b, 0x0b, 0x1e, 0x5b, 0x3c, 0xd6, 3183 0x85, 0xda, 0x8b, 0x51, 0x8b, 0x8a, 0x07, 0x0f, 0x01, 0x8f, 0x9a, 0xf1,
3184 0x8c, 0xef, 0xfb, 0xf3, 0x92, 0x99, 0x97, 0x9d, 0x24, 0xa7, 0x2e, 0xb4, 3184 0xfb, 0x7e, 0x7c, 0x37, 0x33, 0x93, 0xdd, 0x24, 0x27, 0x03, 0xed, 0x87,
3185 0x3f, 0xbe, 0x37, 0xdf, 0xbf, 0xf7, 0xfd, 0xf9, 0xbd, 0xd4, 0x00, 0xc0, 3185 0xf7, 0x9d, 0xf7, 0x7d, 0xdf, 0xf7, 0xde, 0xf7, 0xf3, 0x3e, 0xdf, 0xf5,
3186 0x82, 0x30, 0x1a, 0x55, 0x08, 0x65, 0x2b, 0x5f, 0x52, 0x90, 0x03, 0xf8, 3186 0x01, 0xc0, 0x80, 0x28, 0x1e, 0x55, 0x08, 0x87, 0x8c, 0xa2, 0xad, 0xa0,
3187 0x1a, 0xf8, 0x57, 0xf4, 0x48, 0x0e, 0x0f, 0x8a, 0x3c, 0xce, 0x10, 0x8e, 3187 0x00, 0xf0, 0x21, 0xf0, 0x9f, 0xe9, 0x92, 0x1d, 0x3d, 0x22, 0xf6, 0x04,
3188 0xd7, 0xd4, 0xff, 0x17, 0xe0, 0x48, 0x13, 0x31, 0x0f, 0x47, 0x5e, 0x40, 3188 0x43, 0x34, 0xe1, 0xab, 0xff, 0xaf, 0xc2, 0xe9, 0x26, 0x62, 0x11, 0x4e,
3189 0x3c, 0x0c, 0xdf, 0x37, 0x03, 0x85, 0xff, 0xc5, 0x10, 0xa2, 0x3c, 0xdc, 3189 0x1f, 0x47, 0x7c, 0x12, 0x6e, 0x37, 0x03, 0x85, 0xff, 0x26, 0x10, 0xa1,
3190 0xff, 0x36, 0x2a, 0x93, 0xff, 0x35, 0xb1, 0xff, 0x33, 0xcf, 0xf8, 0x6a, 3190 0x3d, 0xdc, 0xfd, 0x24, 0xae, 0x50, 0xfc, 0x4d, 0xd9, 0xff, 0x63, 0x91,
3191 0xa7, 0xc4, 0x7e, 0x04, 0xe1, 0x40, 0x8d, 0x60, 0xb5, 0x87, 0xf2, 0x89, 3191 0xf1, 0x54, 0x68, 0x73, 0x1c, 0x41, 0x38, 0xe9, 0x13, 0xdc, 0xed, 0xa0,
3192 0x13, 0x60, 0xa3, 0x9f, 0x4f, 0x94, 0x02, 0xca, 0x8d, 0x5c, 0x78, 0x40, 3192 0x7d, 0xfe, 0x3c, 0x58, 0x18, 0xe7, 0x6d, 0xe5, 0x80, 0x76, 0xa3, 0x10,
3193 0xf2, 0xb2, 0x58, 0xef, 0x5e, 0xcf, 0xc7, 0x73, 0xb8, 0x3f, 0x8d, 0xf2, 3193 0x9d, 0x94, 0xbc, 0x0c, 0xf6, 0xfb, 0xa9, 0xe3, 0xe1, 0x3a, 0xfc, 0x3c,
3194 0x3e, 0xf7, 0x5a, 0x0f, 0x31, 0x80, 0x73, 0x25, 0x8f, 0xef, 0x33, 0xca, 3194 0x8b, 0xf6, 0x51, 0xe7, 0xd5, 0x0e, 0x62, 0x00, 0x97, 0x6c, 0x97, 0xeb,
3195 0x6e, 0xd7, 0xda, 0x68, 0xa7, 0x74, 0xdb, 0xe2, 0xb7, 0x88, 0x7e, 0xff, 3195 0x19, 0xe5, 0xb0, 0x9b, 0xe3, 0xb8, 0x4f, 0xf9, 0x8e, 0x4b, 0x5c, 0x13,
3196 0x89, 0xd9, 0x2f, 0xfa, 0x4b, 0xfa, 0x69, 0x28, 0x3f, 0x78, 0x6e, 0x4b, 3196 0xe3, 0xfe, 0x99, 0x70, 0x5c, 0x8c, 0x97, 0x8e, 0xd3, 0x50, 0x71, 0x70,
3197 0x5e, 0xb6, 0x91, 0x97, 0xad, 0xf2, 0x90, 0x3a, 0x80, 0xce, 0x03, 0x71, 3197 0xdd, 0x92, 0xbc, 0xac, 0x5c, 0x5e, 0x96, 0xca, 0x43, 0xfa, 0x00, 0x3a,
3198 0xaf, 0x8a, 0x8b, 0x7e, 0x1f, 0xcb, 0xbd, 0x01, 0x4e, 0x37, 0xc5, 0x7f, 3198 0x0f, 0xc4, 0x23, 0xea, 0x5c, 0x8c, 0xbb, 0x25, 0x75, 0x03, 0x3c, 0xdf,
3199 0x84, 0xe8, 0xe5, 0xd8, 0x9f, 0xfa, 0x27, 0xf7, 0xd8, 0xea, 0x47, 0xd7, 3199 0x94, 0xf8, 0x31, 0xa2, 0x5b, 0xe0, 0x78, 0xea, 0x9f, 0xd4, 0xb1, 0x3b,
3200 0x29, 0x9d, 0xbf, 0xd3, 0xd1, 0xdf, 0x75, 0x3f, 0x30, 0xce, 0x1d, 0x15, 3200 0x8e, 0xee, 0x53, 0x36, 0xff, 0x72, 0xa8, 0xbf, 0xeb, 0xfb, 0xc0, 0x73,
3201 0x27, 0xa9, 0x0f, 0x3b, 0xe8, 0xff, 0xa6, 0xf4, 0xd3, 0x7e, 0xf9, 0xfc, 3201 0x7e, 0x50, 0xe7, 0xa4, 0xfd, 0x61, 0x1f, 0xff, 0xef, 0x94, 0x7f, 0x36,
3202 0xd7, 0xcd, 0xf3, 0xd6, 0xa0, 0xba, 0x15, 0x8d, 0xba, 0xfd, 0x28, 0x75, 3202 0x2e, 0xaf, 0x7f, 0xbb, 0xb3, 0xde, 0xea, 0xd7, 0x37, 0x33, 0xd7, 0xb7,
3203 0x9b, 0x81, 0x17, 0xad, 0x80, 0xf4, 0x0a, 0x80, 0xb8, 0x5f, 0x25, 0x80, 3203 0x2f, 0xa5, 0x6f, 0x73, 0x70, 0xc2, 0x08, 0xc8, 0xaf, 0x04, 0x88, 0xc7,
3204 0xf8, 0xbc, 0xe0, 0x45, 0xc1, 0xcf, 0x04, 0x97, 0x05, 0xf7, 0x0a, 0x0e, 3204 0x54, 0x02, 0x88, 0x0f, 0x0b, 0x5e, 0x13, 0xbc, 0x25, 0xf8, 0xae, 0xe0,
3205 0x0b, 0xee, 0x11, 0x7c, 0x4e, 0xf0, 0x6f, 0xc1, 0x9a, 0xa0, 0x2f, 0x58, 3205 0x11, 0xc1, 0x61, 0xc1, 0xc3, 0x82, 0x0f, 0x09, 0x6e, 0x09, 0xfa, 0x82,
3206 0x15, 0xbc, 0x27, 0xe8, 0x09, 0x96, 0x0d, 0x7f, 0x75, 0xc1, 0x92, 0x60, 3206 0x9e, 0x60, 0x4d, 0xf0, 0x2f, 0x41, 0x57, 0xb0, 0x92, 0x8b, 0x57, 0x17,
3207 0x24, 0xf8, 0x9a, 0x61, 0xef, 0xe6, 0x18, 0x57, 0x45, 0x3e, 0x28, 0xf2, 3207 0xb4, 0x05, 0x3f, 0x17, 0x7c, 0x22, 0xb7, 0xff, 0x68, 0x81, 0xf1, 0x81,
3208 0x49, 0x91, 0xb1, 0xa0, 0x32, 0xf7, 0xa9, 0x7a, 0x7d, 0xbe, 0xd1, 0xdf, 3208 0xd8, 0x4f, 0x89, 0x7d, 0x41, 0x6c, 0x6c, 0xa8, 0xf0, 0x3e, 0xd3, 0xaf,
3209 0xd5, 0x9e, 0x7c, 0x6f, 0x69, 0xbd, 0x12, 0xd5, 0x0f, 0xda, 0x49, 0xfd, 3209 0x5b, 0xbd, 0xfb, 0xbd, 0xdb, 0x91, 0xef, 0x2d, 0xed, 0x67, 0x53, 0xff,
3210 0x8f, 0xb7, 0xd1, 0x67, 0xb5, 0xe9, 0xd6, 0x20, 0xbb, 0x1b, 0x31, 0xe7, 3210 0x60, 0x3c, 0xed, 0xff, 0xd6, 0x1e, 0xfe, 0xec, 0x36, 0xdb, 0xea, 0xb7,
3211 0xf1, 0x91, 0xd8, 0x07, 0xfd, 0xef, 0x32, 0xf6, 0x68, 0xaa, 0x63, 0xce, 3211 0xef, 0x66, 0xc2, 0x79, 0xbc, 0x29, 0xfb, 0x83, 0xee, 0x67, 0x03, 0xe6,
3212 0xd7, 0xa0, 0x3d, 0x7a, 0x45, 0xf6, 0xe8, 0xd0, 0x96, 0xf9, 0xe5, 0x39, 3212 0x68, 0x26, 0xcc, 0xf3, 0xab, 0xdf, 0x1c, 0x3d, 0x2e, 0x73, 0x34, 0xbd,
3213 0x3d, 0x2a, 0xf6, 0x53, 0x32, 0x9f, 0x8d, 0x0c, 0xbd, 0x30, 0xb1, 0xaf, 3213 0x8b, 0xbf, 0xcc, 0xd3, 0x33, 0xb2, 0x7f, 0x46, 0xf8, 0xd9, 0x18, 0xe0,
3214 0x14, 0x2f, 0x63, 0x1f, 0x6e, 0xe6, 0xba, 0x1d, 0x8c, 0x5b, 0x94, 0xb8, 3214 0x17, 0xa5, 0xe6, 0x95, 0xce, 0x1b, 0x30, 0x0f, 0x1f, 0x15, 0xda, 0x61,
3215 0x59, 0xf9, 0xa1, 0xbd, 0xcc, 0x6f, 0x4b, 0xcf, 0x71, 0x7a, 0x7e, 0x79, 3215 0xc0, 0xfc, 0x89, 0xf6, 0xca, 0x0f, 0xf7, 0x0b, 0x7f, 0x5b, 0x9a, 0xc7,
3216 0x0e, 0x6d, 0x63, 0x0e, 0x2f, 0xed, 0xd0, 0x87, 0xb2, 0x51, 0xcf, 0xf3, 3216 0x59, 0xfe, 0x32, 0x0f, 0xad, 0x1c, 0x0f, 0x5f, 0xde, 0xe7, 0x1e, 0x2a,
3217 0x4a, 0x9f, 0x45, 0xcb, 0x62, 0x5c, 0x62, 0xec, 0x78, 0x76, 0x01, 0xf1, 3217 0xb9, 0x7e, 0x5e, 0x56, 0xfe, 0x6c, 0x1a, 0x06, 0xe3, 0x1a, 0x63, 0xe8,
3218 0x90, 0xf7, 0x0b, 0xfb, 0x1b, 0xa5, 0x7b, 0x78, 0xc1, 0x02, 0xed, 0x6d, 3218 0x5a, 0x25, 0xc4, 0x69, 0xf7, 0x1b, 0x8e, 0x37, 0x4a, 0x75, 0xb8, 0xc1,
3219 0x01, 0x16, 0xec, 0x21, 0x85, 0x4f, 0xe3, 0x0f, 0x59, 0xaf, 0x5e, 0xbc, 3219 0x0a, 0xcd, 0x6d, 0x09, 0x56, 0xac, 0x21, 0x85, 0xff, 0x24, 0x6f, 0xb0,
3220 0x4d, 0x18, 0x2c, 0xdd, 0x62, 0xfd, 0x3f, 0x9a, 0x9c, 0xf7, 0x1b, 0xe3, 3220 0x5f, 0xdd, 0xfc, 0x9e, 0x30, 0x58, 0xbb, 0xc3, 0xfe, 0xf7, 0x9a, 0x9c,
3221 0x60, 0xfc, 0xf4, 0x77, 0xd9, 0x77, 0x1f, 0xe5, 0x7f, 0x73, 0x61, 0xa4, 3221 0xf7, 0x33, 0x13, 0x90, 0xfb, 0xd3, 0xdf, 0x65, 0xde, 0x3d, 0xb4, 0xff,
3222 0xe3, 0x88, 0xdd, 0x79, 0xbd, 0x47, 0xfc, 0xbb, 0x62, 0xd7, 0xa8, 0x6e, 3222 0x2e, 0x44, 0xb1, 0x3e, 0x47, 0xf6, 0x5d, 0xd6, 0x73, 0xc4, 0x7f, 0x8b,
3223 0xef, 0x47, 0x24, 0x0e, 0x7b, 0xf3, 0xcc, 0xaf, 0x1f, 0x44, 0xfa, 0x3e, 3223 0x96, 0x4f, 0xf5, 0xde, 0x88, 0xc9, 0x1c, 0x76, 0x97, 0x7d, 0xfa, 0xfa,
3224 0xc2, 0x2b, 0x6d, 0xb6, 0xab, 0x50, 0x9c, 0x3d, 0xfd, 0x65, 0x63, 0x3e, 3224 0x7a, 0xac, 0xeb, 0x11, 0x5d, 0x19, 0xd7, 0xf5, 0xf3, 0xfe, 0x2a, 0x9d,
3225 0x9a, 0xbb, 0xe2, 0xd7, 0x27, 0xf1, 0x26, 0xbf, 0x26, 0xef, 0xaf, 0xf9, 3225 0x77, 0xb8, 0xbb, 0x9e, 0xe3, 0x49, 0xf3, 0x40, 0x3a, 0xbb, 0x95, 0xec,
3226 0xb5, 0x04, 0x67, 0x66, 0x7c, 0x8a, 0x57, 0xb5, 0xd9, 0xcd, 0x9b, 0x3e, 3226 0xe8, 0x6c, 0xba, 0x0f, 0x5a, 0x67, 0x6d, 0x58, 0x98, 0xf3, 0xe8, 0xdc,
3227 0xe3, 0xdb, 0x2e, 0xe3, 0x43, 0x17, 0xeb, 0x13, 0xc7, 0xe7, 0xca, 0x2c, 3227 0x9a, 0xc5, 0x61, 0x2e, 0x78, 0x8c, 0x17, 0x1d, 0xc6, 0xdf, 0x1c, 0xec,
3228 0x9f, 0xad, 0xe8, 0xbd, 0xd6, 0xf6, 0x3a, 0xaf, 0xed, 0xf2, 0xc1, 0xf8, 3228 0x53, 0x92, 0x5c, 0xaa, 0xb0, 0xfd, 0x42, 0x55, 0xcf, 0xb7, 0xde, 0xaf,
3229 0x3a, 0x8e, 0xce, 0x43, 0xc7, 0x4b, 0xcf, 0x43, 0x76, 0x5c, 0xc6, 0xae, 3229 0xf3, 0xda, 0x2b, 0x1f, 0x3c, 0x5f, 0x9f, 0xa3, 0xf3, 0xd0, 0xe7, 0x65,
3230 0x95, 0xae, 0xc3, 0xd2, 0x04, 0x63, 0x61, 0x12, 0xf3, 0xfa, 0x21, 0xde, 3230 0x79, 0x31, 0xf8, 0x5c, 0xc6, 0xb6, 0x91, 0xed, 0xc3, 0xda, 0x24, 0x63,
3231 0xd8, 0xeb, 0x56, 0x8d, 0xf4, 0xc6, 0x80, 0xe5, 0x59, 0x99, 0xbf, 0x59, 3231 0x69, 0x0a, 0xf3, 0xba, 0x9d, 0xf4, 0xe6, 0xbb, 0xe5, 0x93, 0xdf, 0x18,
3232 0xda, 0x47, 0xc5, 0x37, 0x16, 0x62, 0x1d, 0x42, 0x7a, 0x6f, 0x2c, 0xf7, 3232 0xb0, 0x3d, 0x2f, 0x3c, 0x9c, 0xa7, 0xb9, 0x54, 0xba, 0x63, 0x20, 0xd6,
3233 0x67, 0x9a, 0x87, 0xbc, 0x9c, 0xab, 0xfa, 0x8f, 0xa5, 0xf7, 0x78, 0x8d, 3233 0x21, 0xa2, 0x77, 0xc7, 0x70, 0xbe, 0x26, 0x5e, 0x14, 0x65, 0x5d, 0xdd,
3234 0xe7, 0xad, 0x94, 0x9e, 0xd3, 0x46, 0x3c, 0x78, 0xfe, 0xdd, 0xfe, 0x72, 3234 0xc3, 0x58, 0x76, 0x9e, 0x37, 0x99, 0x77, 0x76, 0x96, 0xaf, 0xc7, 0x84,
3235 0x6f, 0x50, 0x3f, 0x74, 0x7e, 0x01, 0x74, 0x27, 0xb3, 0xde, 0x09, 0xfd, 3235 0xaf, 0x4e, 0x77, 0xbd, 0xb3, 0xdf, 0x3c, 0x48, 0xc1, 0xbd, 0xfe, 0x6b,
3236 0x3e, 0x6b, 0x9e, 0xa4, 0xe3, 0x7e, 0x98, 0x4f, 0xdd, 0xfb, 0x28, 0x74, 3236 0x3d, 0xd4, 0xef, 0xb2, 0xd6, 0x3d, 0xfa, 0xdc, 0x8d, 0x8a, 0x99, 0x3a,
3237 0x06, 0xf9, 0xff, 0x46, 0xbf, 0x7b, 0x03, 0xf6, 0x76, 0xa7, 0xb8, 0x29, 3237 0xcf, 0x40, 0xd8, 0xef, 0x7e, 0x3f, 0x16, 0x3d, 0x99, 0x16, 0x7d, 0x53,
3238 0xff, 0x55, 0xb5, 0x39, 0xb0, 0x75, 0xef, 0x1c, 0x63, 0x4f, 0x9f, 0xae, 3238 0x97, 0x18, 0x65, 0xf6, 0xd5, 0x80, 0xf2, 0x29, 0xe7, 0xe6, 0xac, 0xd4,
3239 0xf3, 0x9e, 0x36, 0xb6, 0xcc, 0xa7, 0xe6, 0xaf, 0xe6, 0xb6, 0xfc, 0xf5, 3239 0x9b, 0x9b, 0x45, 0x6b, 0x80, 0xde, 0x99, 0xfc, 0x7e, 0x2e, 0xcc, 0xe1,
3240 0xac, 0xf8, 0xca, 0x02, 0xe6, 0x2b, 0x7c, 0x4f, 0xd2, 0x79, 0x3a, 0xfa, 3240 0xb9, 0x76, 0xe3, 0x06, 0xcd, 0x7f, 0x19, 0xfe, 0x70, 0xf9, 0x5e, 0xda,
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3272 0xe0, 0x3f, 0xdd, 0xd1, 0x99, 0x07, 0x78, 0x0d, 0x00, 0x00, 0x00 };
3268 3273
3269static u8 bnx2_xi_rv2p_proc2[] = { 3274static u8 bnx2_xi_rv2p_proc2[] = {
3270 /* Date: 04/25/2008 22:02 */ 3275 /* Date: 06/17/2008 16:52 */
3271#define XI_RV2P_PROC2_MAX_BD_PAGE_LOC 5 3276#define XI_RV2P_PROC2_MAX_BD_PAGE_LOC 5
3272#define XI_RV2P_PROC2_BD_PAGE_SIZE_MSK 0xffff 3277#define XI_RV2P_PROC2_BD_PAGE_SIZE_MSK 0xffff
3273#define XI_RV2P_PROC2_BD_PAGE_SIZE ((PAGE_SIZE / 16) - 1) 3278#define XI_RV2P_PROC2_BD_PAGE_SIZE ((BCM_PAGE_SIZE / 16) - 1)
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3389 0x90, 0xa6, 0x77, 0x44, 0x62, 0x70, 0xe0, 0xc1, 0xfc, 0x9d, 0x00, 0x7f, 3394 0xff, 0xb2, 0xb1, 0x39, 0x92, 0x53, 0x2a, 0x0a, 0x29, 0x0e, 0x4b, 0xfc,
3390 0x09, 0xd6, 0x5b, 0x4f, 0x51, 0x1f, 0xfa, 0x94, 0xe8, 0x67, 0x3f, 0x4e, 3395 0xb3, 0xb0, 0x27, 0x92, 0x60, 0x1c, 0xfa, 0x9e, 0x05, 0x3d, 0xcc, 0x71,
3391 0xd4, 0x72, 0xde, 0x57, 0xc1, 0x8f, 0x3d, 0xcf, 0x40, 0x9f, 0x1e, 0xce, 3396 0xa0, 0xfc, 0x7b, 0x75, 0x83, 0x46, 0xe7, 0xa6, 0xfa, 0x71, 0x8f, 0xca,
3392 0x9f, 0xdb, 0xdc, 0x5f, 0xc0, 0xff, 0x7e, 0xbd, 0x63, 0x94, 0xfd, 0xcd, 3397 0xa3, 0xf4, 0xb9, 0x58, 0xc5, 0x45, 0x49, 0x03, 0xad, 0x45, 0xd7, 0x21,
3393 0x71, 0xb8, 0x8b, 0x79, 0xb8, 0x05, 0x1e, 0x74, 0xc5, 0x43, 0xca, 0xe4, 3398 0xb2, 0x53, 0xf7, 0xa7, 0x8c, 0x27, 0x1d, 0x2b, 0xee, 0xdb, 0xa9, 0xf1,
3394 0x41, 0xd5, 0x19, 0xeb, 0x3e, 0x85, 0x46, 0x1c, 0x49, 0x5c, 0xa0, 0x5f, 3399 0x22, 0xe3, 0x49, 0xc5, 0xad, 0x39, 0xce, 0xcc, 0x71, 0x94, 0x1a, 0x3f,
3395 0xa1, 0x3e, 0x2c, 0x8f, 0xed, 0x36, 0xe4, 0x1a, 0xa4, 0x7d, 0x61, 0xb6, 3400 0x7e, 0xea, 0x2f, 0x7a, 0x31, 0xa0, 0x77, 0x89, 0x2b, 0x92, 0x18, 0x7e,
3396 0x2f, 0x24, 0x76, 0x2e, 0xb7, 0xae, 0x0b, 0xf2, 0xba, 0x80, 0xb1, 0x0e, 3401 0x38, 0x8e, 0xa7, 0x80, 0x63, 0x84, 0xf5, 0xd6, 0xa2, 0x34, 0x8f, 0x3e,
3397 0xf3, 0xc8, 0x53, 0x7d, 0x1e, 0x7e, 0x25, 0x8f, 0x6a, 0xdf, 0xdc, 0x7c, 3402 0x25, 0x86, 0xd8, 0x9f, 0xd3, 0xd5, 0x9c, 0xff, 0x15, 0xf0, 0x67, 0xdf,
3398 0xb4, 0xf2, 0x49, 0x15, 0x9a, 0xfe, 0x50, 0x87, 0x0c, 0xbf, 0x51, 0xbd, 3403 0x0a, 0xe8, 0xd3, 0xc7, 0x79, 0x74, 0x87, 0xe7, 0x0c, 0xc4, 0x81, 0x5b,
3399 0xd2, 0xcd, 0xfa, 0x73, 0x97, 0xea, 0x79, 0xe0, 0x64, 0x37, 0xea, 0xc5, 3404 0xeb, 0x9c, 0x60, 0xbf, 0x73, 0x3c, 0x76, 0x33, 0x0e, 0xb7, 0x81, 0x83,
3400 0xc9, 0xee, 0xd3, 0x7c, 0xff, 0x32, 0x2f, 0x2d, 0xf4, 0x6e, 0x30, 0xb8, 3405 0xa6, 0x70, 0x88, 0x1a, 0x38, 0xa8, 0x7a, 0x63, 0x96, 0x53, 0xa0, 0xc7,
3401 0xab, 0xb2, 0xd7, 0x1f, 0xbb, 0x1e, 0x15, 0x16, 0x3d, 0xd4, 0xb9, 0x0f, 3406 0x93, 0xa4, 0x4b, 0xb4, 0xab, 0x34, 0x8f, 0xe5, 0xb0, 0xdd, 0x3a, 0x5f,
3402 0xeb, 0x0f, 0xd0, 0x9f, 0x6e, 0xa0, 0xfe, 0x40, 0x33, 0xfb, 0x6c, 0xfb, 3407 0x83, 0xb4, 0xcf, 0xcf, 0xf6, 0xf9, 0xc4, 0xbe, 0x35, 0xe6, 0x73, 0x79,
3403 0x3d, 0x72, 0xeb, 0xfe, 0xe3, 0xde, 0x23, 0x5b, 0x1a, 0xac, 0xe7, 0xc5, 3408 0x7c, 0xce, 0xab, 0x9f, 0xc3, 0x3e, 0xf2, 0x55, 0xcb, 0x82, 0xaf, 0xc4,
3404 0xc4, 0xd8, 0x08, 0xce, 0x69, 0xe1, 0x7b, 0x7b, 0x3b, 0xe7, 0xf7, 0xb5, 3409 0x51, 0xc9, 0x4d, 0xcf, 0x4b, 0x33, 0x9e, 0x54, 0xa9, 0xe9, 0x0f, 0xf5,
3405 0x40, 0x84, 0xce, 0x4d, 0xbe, 0x46, 0xf6, 0x8a, 0x68, 0x10, 0xf6, 0x25, 3410 0x48, 0xf7, 0x1b, 0xd5, 0x2d, 0xcd, 0xa8, 0x43, 0xf7, 0xa8, 0xae, 0x7b,
3406 0x5f, 0xc7, 0xf7, 0x64, 0x08, 0xf3, 0xe5, 0x21, 0xfc, 0x3e, 0xd0, 0xe2, 3411 0x4f, 0xf7, 0xa2, 0x6e, 0x9c, 0xee, 0x3d, 0xcb, 0x7d, 0x98, 0x71, 0x69,
3407 0xd7, 0x49, 0xbe, 0x3c, 0x04, 0x8c, 0x72, 0x5d, 0x18, 0x33, 0xdf, 0x11, 3412 0xa1, 0xf7, 0x83, 0x8e, 0x5d, 0x45, 0x6a, 0x1d, 0x4a, 0xd5, 0xa3, 0xcc,
3408 0xc0, 0x21, 0xdf, 0x7c, 0xef, 0x08, 0xbc, 0xc7, 0xce, 0xfb, 0x50, 0x37, 3413 0xa4, 0x87, 0xba, 0x77, 0xb1, 0x39, 0x01, 0x73, 0xea, 0x16, 0x9a, 0x13,
3409 0x44, 0x0c, 0xfd, 0x73, 0x53, 0x8d, 0x4e, 0xdf, 0x5b, 0x63, 0xb8, 0x9f, 3414 0x3c, 0xc6, 0xbc, 0x9d, 0xda, 0x4f, 0x26, 0x1f, 0x3c, 0x6e, 0x3f, 0xd9,
3410 0x51, 0x97, 0xe7, 0xda, 0x55, 0x81, 0x78, 0x2d, 0xcf, 0xbe, 0x37, 0xac, 3415 0xd9, 0x60, 0xbe, 0xaf, 0x46, 0x4c, 0x8e, 0xe3, 0x9e, 0x16, 0xee, 0xdf,
3411 0xef, 0x12, 0x3d, 0x31, 0x68, 0xf6, 0xfd, 0x76, 0x3d, 0x90, 0x67, 0x72, 3416 0xbb, 0x39, 0xcf, 0xaf, 0x7b, 0x03, 0x74, 0x6f, 0xc7, 0x2b, 0x64, 0xaf,
3412 0x7f, 0x1a, 0x1a, 0xfd, 0xf5, 0xa3, 0xbc, 0x47, 0x3c, 0xdc, 0xaf, 0xdd, 3417 0x08, 0xe5, 0xc1, 0xbe, 0x8e, 0xed, 0xf8, 0xde, 0xe1, 0xc3, 0x7e, 0xa9,
3413 0x99, 0x45, 0xbc, 0x16, 0x89, 0x0b, 0x23, 0xe0, 0x61, 0x6c, 0xc4, 0x29, 3418 0x0f, 0xbf, 0xa3, 0xb4, 0xb8, 0x35, 0xe2, 0x2f, 0xf5, 0x81, 0x86, 0xb8,
3414 0x8f, 0xa5, 0x1e, 0xea, 0x1c, 0xd8, 0xa5, 0xec, 0xcc, 0x9e, 0x0b, 0xbd, 3419 0x3e, 0x4c, 0x1a, 0xef, 0x09, 0xd0, 0x51, 0x57, 0xb6, 0xf7, 0x04, 0xde,
3415 0x76, 0xb0, 0xfe, 0xbf, 0xd2, 0xef, 0x17, 0x51, 0xb6, 0x57, 0xee, 0x8b, 3420 0x65, 0x17, 0x5d, 0xa8, 0x1f, 0xa2, 0x06, 0x73, 0x74, 0x53, 0x95, 0x46,
3416 0xf9, 0x8d, 0xf4, 0x6e, 0xca, 0x13, 0x69, 0x73, 0x6c, 0x7f, 0xcf, 0xb4, 3421 0xdf, 0x5b, 0x6b, 0xd0, 0xa7, 0x51, 0x9f, 0x33, 0xed, 0x2a, 0x43, 0xbc,
3417 0x90, 0x5e, 0x85, 0x7c, 0xaf, 0x47, 0x2d, 0xfd, 0x07, 0xe4, 0x8b, 0xeb, 3422 0x96, 0x26, 0xdf, 0x1d, 0xe6, 0xf7, 0x89, 0x16, 0x49, 0x18, 0xf3, 0x7f,
3418 0x81, 0xc7, 0xea, 0x95, 0xdf, 0x94, 0x7f, 0x95, 0x3f, 0xe1, 0xf7, 0xe8, 3423 0xaa, 0x1e, 0xc8, 0x33, 0x29, 0x9f, 0x96, 0xfa, 0x9c, 0xfd, 0x28, 0xef,
3419 0x4a, 0x12, 0x6b, 0x4c, 0xae, 0xa4, 0x84, 0xaf, 0x4f, 0x4e, 0xa9, 0x7b, 3424 0x12, 0x07, 0xcf, 0x6d, 0x77, 0xf9, 0x77, 0x82, 0x42, 0x71, 0x69, 0x1c,
3420 0x1e, 0xeb, 0xb7, 0xc4, 0xa5, 0xfc, 0x07, 0xe2, 0xfb, 0x38, 0x2e, 0xd6, 3425 0x38, 0x4c, 0x8e, 0x5b, 0xe5, 0xb1, 0xd4, 0x43, 0xdd, 0x03, 0xbb, 0x94,
3421 0x9f, 0x19, 0xb3, 0xfd, 0xbd, 0xe0, 0x3f, 0xeb, 0x3b, 0xc1, 0x23, 0xce, 3426 0x9d, 0xc9, 0x7b, 0xa1, 0xd7, 0x5e, 0xd6, 0xff, 0x06, 0xfd, 0x9e, 0x11,
3422 0xe7, 0xf1, 0x74, 0x83, 0xea, 0x7b, 0xe7, 0x7b, 0xef, 0x48, 0x3b, 0x3e, 3427 0x62, 0x7b, 0xa5, 0x5c, 0xec, 0x6f, 0xa5, 0xf7, 0x53, 0x8e, 0x88, 0x19,
3423 0xba, 0x9f, 0xdb, 0x47, 0x67, 0xfb, 0x60, 0x65, 0xaf, 0x5c, 0x57, 0xcf, 3428 0xeb, 0xd4, 0x77, 0x4d, 0x0b, 0xe9, 0x55, 0xc0, 0xfd, 0x3d, 0x64, 0x9a,
3424 0x71, 0xac, 0x89, 0xa6, 0x0d, 0xf8, 0x7d, 0x23, 0xec, 0x47, 0xde, 0x84, 3429 0x43, 0xc0, 0x1f, 0xac, 0x03, 0x1d, 0xa9, 0x53, 0x7e, 0x53, 0xfe, 0x55,
3425 0xfd, 0x4e, 0xef, 0x52, 0x23, 0x8e, 0xf2, 0xa9, 0x60, 0x2c, 0x2c, 0xcc, 3430 0xfe, 0x84, 0xdf, 0x43, 0xf5, 0xc4, 0xd6, 0xd8, 0x51, 0x4f, 0x09, 0x5f,
3426 0x27, 0xfb, 0x8e, 0x5c, 0xbc, 0x44, 0x62, 0x9f, 0x0d, 0x06, 0x31, 0x5f, 3431 0xd7, 0x31, 0xab, 0xfa, 0x3d, 0xce, 0xef, 0x0c, 0x4b, 0xfe, 0x77, 0xc4,
3427 0xd2, 0x84, 0x63, 0xbc, 0x14, 0xf7, 0x1e, 0x71, 0x08, 0x79, 0xf1, 0xe9, 3432 0x77, 0x61, 0x34, 0xd8, 0x9f, 0x99, 0x26, 0xe7, 0x7c, 0xc1, 0x7f, 0xe6,
3428 0x31, 0xe0, 0x27, 0xe2, 0x55, 0xec, 0x53, 0x78, 0x90, 0xee, 0x53, 0xad, 3433 0xf7, 0x82, 0x43, 0x5c, 0xcc, 0xe1, 0xed, 0x06, 0x35, 0xff, 0x66, 0x7b,
3429 0x04, 0x34, 0x67, 0x06, 0x39, 0xde, 0x4b, 0xdd, 0xf4, 0xfb, 0xe2, 0xac, 3434 0xf7, 0x48, 0x3b, 0xba, 0x1f, 0xa4, 0xcf, 0xd3, 0xc9, 0x79, 0x58, 0xd9,
3430 0x08, 0x49, 0xf4, 0x99, 0xf9, 0x8b, 0xb8, 0xf6, 0x5a, 0xfc, 0xff, 0xa8, 3435 0x2b, 0xcf, 0xd5, 0x71, 0x1c, 0x7b, 0x44, 0xd3, 0x16, 0xfc, 0xce, 0xe1,
3431 0x71, 0x4e, 0xf5, 0xc9, 0x88, 0x63, 0x6c, 0xc3, 0xf1, 0xae, 0xe5, 0xc6, 3436 0x77, 0x23, 0x6f, 0xfc, 0x6e, 0xab, 0xf7, 0xa9, 0x1e, 0x47, 0xb9, 0x54,
3432 0xbb, 0xe2, 0xa9, 0xd4, 0xed, 0x18, 0xdf, 0xab, 0xe7, 0xc6, 0xb7, 0xd2, 3437 0x30, 0x96, 0x16, 0xe4, 0x92, 0x7d, 0x27, 0x2e, 0x7f, 0x43, 0x6c, 0x1f,
3433 0x4f, 0xf2, 0x7d, 0xd7, 0xbc, 0x3f, 0xe7, 0xee, 0x8f, 0xf7, 0xd3, 0x85, 3438 0x25, 0xf2, 0xb0, 0x5f, 0xd4, 0x84, 0x6b, 0x9c, 0x14, 0xf7, 0x0e, 0x71,
3434 0x27, 0x16, 0xdf, 0xc0, 0x8d, 0xd5, 0xf2, 0xfc, 0x92, 0x39, 0x7d, 0x72, 3439 0x14, 0x79, 0xf1, 0xe1, 0x08, 0xe8, 0x07, 0xe2, 0x65, 0xc8, 0x29, 0x18,
3435 0x6e, 0xfe, 0xa1, 0xde, 0xbd, 0x61, 0xc4, 0xc3, 0x7f, 0x69, 0x4a, 0x77, 3440 0xa0, 0xbe, 0xea, 0x29, 0x02, 0xcc, 0xf1, 0x04, 0xc7, 0x7b, 0xb1, 0x9d,
3436 0x8f, 0xc8, 0x15, 0x00, 0x00, 0x00 }; 3441 0x7e, 0x87, 0x5d, 0x10, 0x3e, 0xfe, 0x9d, 0x8c, 0xf3, 0x17, 0x71, 0xed,
3442 0x34, 0xf9, 0xff, 0x51, 0xe3, 0x1c, 0xfd, 0x33, 0xc1, 0x7e, 0xe7, 0x78,
3443 0xf7, 0xa4, 0xc7, 0xbb, 0xc2, 0xa9, 0xd8, 0x6e, 0x19, 0xdf, 0xeb, 0x33,
3444 0xe3, 0x5b, 0xe9, 0x97, 0xda, 0x3f, 0x33, 0xe5, 0xe3, 0x1d, 0x75, 0xe9,
3445 0x89, 0xc5, 0x37, 0xe8, 0xd6, 0x4a, 0x79, 0x7f, 0x51, 0xc6, 0xbc, 0x9c,
3446 0x9e, 0x7f, 0xa8, 0x77, 0xd5, 0x7a, 0x3c, 0xfc, 0x07, 0xd7, 0x0d, 0x36,
3447 0x4f, 0xf0, 0x16, 0x00, 0x00, 0x00 };
3437 3448
3438static u8 bnx2_TPAT_b09FwText[] = { 3449static u8 bnx2_TPAT_b09FwText[] = {
3439 0xbd, 0x58, 0x5d, 0x6c, 0x1c, 0xd5, 0x15, 0x3e, 0x73, 0x67, 0xd6, 0x3b, 3450 0xbd, 0x58, 0x5d, 0x6c, 0x1c, 0x57, 0x15, 0x3e, 0x73, 0xe7, 0xee, 0x7a,
3440 0xb6, 0x9c, 0x78, 0x4c, 0xb6, 0xb0, 0x14, 0x47, 0xcc, 0xc4, 0xe3, 0x9f, 3451 0x6d, 0x39, 0xf1, 0xb8, 0x99, 0x96, 0x4d, 0x63, 0xd4, 0x99, 0x78, 0xfc,
3441 0xca, 0x16, 0x0c, 0xe9, 0x96, 0x1a, 0x69, 0x55, 0x0d, 0xbb, 0x1b, 0x63, 3452 0x43, 0x6d, 0x95, 0x69, 0x59, 0x15, 0x17, 0x56, 0x68, 0xba, 0xbb, 0x71,
3442 0xa5, 0x3c, 0x18, 0x29, 0x52, 0x91, 0xa0, 0xc8, 0x5d, 0x13, 0xe0, 0x81, 3453 0xad, 0xaa, 0xaa, 0x5c, 0x29, 0x88, 0x4a, 0x8d, 0x90, 0x59, 0x37, 0x6d,
3443 0x87, 0xa0, 0xf6, 0xa1, 0x15, 0x0f, 0x59, 0xd6, 0x9b, 0x90, 0x87, 0x6d, 3454 0x79, 0x4b, 0x11, 0x0f, 0x48, 0x45, 0xca, 0xb2, 0x76, 0xd2, 0x08, 0x2d,
3444 0x06, 0x96, 0x2a, 0x79, 0x68, 0x55, 0x45, 0x0e, 0x8e, 0xa3, 0x76, 0xe5, 3455 0x99, 0xd6, 0x85, 0x44, 0x42, 0x7d, 0x88, 0x9c, 0x3a, 0xee, 0xc3, 0xca,
3445 0x25, 0x48, 0x7d, 0x8c, 0x40, 0xa1, 0x4a, 0x5f, 0x79, 0xa0, 0x15, 0x7d, 3456 0x9b, 0x8a, 0x07, 0x24, 0xa4, 0xa8, 0x55, 0x80, 0xc0, 0x1b, 0x7d, 0xa8,
3446 0x22, 0x52, 0x5f, 0x78, 0xe8, 0x4f, 0x84, 0xd4, 0x16, 0xb5, 0x34, 0xb7, 3457 0xf8, 0x79, 0x22, 0x12, 0x0f, 0x54, 0x08, 0x90, 0x85, 0x04, 0x2a, 0xa5,
3447 0xdf, 0x77, 0x67, 0xc6, 0x6c, 0x4d, 0x22, 0xc4, 0x4b, 0x57, 0x5a, 0xdd, 3458 0xe4, 0xf2, 0x7d, 0x77, 0x67, 0x92, 0xc5, 0x4d, 0x41, 0xe5, 0x81, 0x95,
3448 0x99, 0x7b, 0xcf, 0x39, 0xf7, 0xdc, 0xf3, 0xf3, 0x9d, 0x73, 0xe7, 0x90, 3459 0x56, 0x77, 0xe6, 0xde, 0x73, 0xce, 0x3d, 0xf7, 0xfc, 0x7c, 0xe7, 0xdc,
3449 0x92, 0x31, 0xc9, 0x7e, 0xfb, 0xf0, 0xaf, 0xfc, 0xe0, 0xc4, 0x8f, 0xbe, 3460 0x39, 0xec, 0xc8, 0x88, 0x64, 0xbf, 0x7d, 0xf8, 0x57, 0xbe, 0x72, 0xe2,
3450 0xf5, 0x40, 0xf4, 0x00, 0xdf, 0xad, 0x82, 0x38, 0xf2, 0x7f, 0xfc, 0xd9, 3461 0xeb, 0x0f, 0xdc, 0x57, 0xb9, 0x0f, 0x8f, 0x0f, 0x3a, 0x77, 0x6b, 0x2d,
3451 0x22, 0x5e, 0xae, 0x07, 0xff, 0xe2, 0xaa, 0xea, 0xda, 0xc1, 0x5a, 0x28, 3462 0xff, 0xc7, 0x9f, 0x2b, 0xe2, 0xe5, 0x7a, 0xf0, 0x2f, 0x25, 0x55, 0x4d,
3452 0xae, 0x5d, 0x5d, 0x79, 0x60, 0x3d, 0x14, 0x89, 0xfb, 0x0b, 0x7e, 0x5d, 3463 0x0e, 0xd6, 0x22, 0x29, 0xb9, 0xd5, 0xea, 0xfc, 0x6a, 0x24, 0x92, 0x74,
3453 0xfe, 0xa3, 0x5b, 0x25, 0x47, 0x38, 0x7f, 0xb0, 0xfa, 0xd9, 0x83, 0x57, 3464 0xe7, 0x82, 0xba, 0xfc, 0xd3, 0xb4, 0x7c, 0x2d, 0x9c, 0xff, 0x64, 0xf5,
3454 0xbf, 0x1d, 0xdc, 0xbc, 0x60, 0x8b, 0xeb, 0x55, 0xcf, 0xb8, 0xde, 0xac, 3465 0x83, 0x4f, 0x5f, 0xf9, 0x6c, 0xb8, 0x7b, 0xc1, 0x95, 0x92, 0x57, 0x3d,
3455 0xb8, 0x53, 0xe0, 0xf9, 0xc5, 0x5c, 0x6f, 0x44, 0xf6, 0xe7, 0xb2, 0x5a, 3466 0xa3, 0xbd, 0x69, 0x29, 0x4d, 0x80, 0xe7, 0xd5, 0x99, 0x6f, 0x17, 0x64,
3456 0x5a, 0x85, 0x37, 0xf4, 0xd5, 0xb9, 0xd0, 0x6b, 0x4b, 0x49, 0xae, 0x0c, 3467 0x7f, 0x2e, 0xab, 0x65, 0x54, 0x74, 0xdd, 0x5c, 0x99, 0x89, 0xbc, 0x36,
3457 0x7c, 0xa9, 0x0d, 0xa6, 0xe4, 0x9d, 0x41, 0x59, 0xde, 0x1e, 0x78, 0xf2, 3468 0x36, 0xb8, 0xdc, 0x0b, 0xa4, 0xd6, 0x2b, 0xcb, 0x9b, 0x3d, 0x5f, 0xde,
3458 0xd6, 0xc0, 0x91, 0xe3, 0x6f, 0x9c, 0x94, 0x4e, 0x14, 0x94, 0x1b, 0xb6, 3469 0xe8, 0x69, 0x39, 0xfe, 0xca, 0x49, 0x59, 0x8f, 0xc3, 0x72, 0xc3, 0x2d,
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3607 0xf0, 0xda, 0x6f, 0xb0, 0xc6, 0x39, 0xde, 0x37, 0x58, 0x43, 0xd1, 0xff, 3618 0x47, 0xb9, 0x7f, 0xfa, 0x71, 0x5a, 0xd7, 0xa4, 0x81, 0x0f, 0x37, 0x46,
3608 0x3f, 0x4c, 0x1f, 0xe5, 0xfe, 0x49, 0xe3, 0xb0, 0xee, 0x90, 0x06, 0x3e, 3619 0x11, 0x4f, 0xcc, 0xe9, 0x3c, 0x9e, 0x02, 0xc4, 0x72, 0xce, 0x8f, 0x7e,
3609 0xec, 0x8d, 0x8b, 0x7d, 0x96, 0x39, 0x9b, 0xc7, 0x8c, 0x8f, 0x58, 0xcd, 3620 0xf3, 0x28, 0x63, 0xa1, 0x60, 0xf3, 0xc6, 0xad, 0xe6, 0x34, 0x65, 0x59,
3610 0xf9, 0xd1, 0x4f, 0x1e, 0x63, 0x2c, 0x14, 0x4c, 0x5e, 0xd8, 0xd5, 0x9c, 3621 0x44, 0x2f, 0xf7, 0x63, 0x8e, 0xdd, 0x7e, 0xac, 0x14, 0x37, 0x4a, 0xf2,
3611 0xa6, 0x2c, 0xcb, 0xe8, 0xd5, 0xde, 0xe3, 0xd8, 0x4f, 0x63, 0x65, 0xa4, 3622 0xfc, 0x0c, 0xb1, 0x2b, 0x8c, 0xaf, 0x42, 0xe7, 0x6b, 0x91, 0x2f, 0x85,
3612 0xe7, 0xca, 0x4b, 0x73, 0xc4, 0xa6, 0x20, 0xba, 0x06, 0x9d, 0xaf, 0x87, 3623 0x69, 0xe6, 0x33, 0xab, 0x51, 0x11, 0x31, 0x84, 0xbb, 0x55, 0x6a, 0x4e,
3613 0x25, 0x29, 0xcc, 0x32, 0x5f, 0x59, 0x6d, 0x46, 0x10, 0x43, 0xb8, 0x77, 3624 0xa2, 0xdf, 0x0a, 0x34, 0xfc, 0xfc, 0x32, 0xe2, 0x88, 0xd8, 0x8a, 0x98,
3614 0x25, 0xfa, 0x24, 0xfa, 0x29, 0xdf, 0x81, 0x9f, 0x5f, 0x47, 0x1c, 0x11, 3625 0x98, 0xdd, 0x44, 0x4c, 0x1c, 0xe7, 0xbb, 0xdd, 0xb7, 0x60, 0x69, 0x5d,
3615 0x3b, 0x11, 0x13, 0xf3, 0x9b, 0x88, 0x89, 0xe3, 0x7c, 0x37, 0xfb, 0x16, 3626 0xbb, 0xbf, 0x0f, 0xfd, 0x4b, 0x32, 0x74, 0xce, 0xe0, 0x4e, 0x75, 0x8b,
3616 0x0c, 0xad, 0x6d, 0xf6, 0x2f, 0x41, 0x7f, 0x57, 0x8a, 0xe7, 0x34, 0xee, 3627 0xef, 0xb4, 0x8d, 0x5f, 0x60, 0x09, 0xe6, 0x57, 0x6d, 0xfc, 0xd2, 0xa7,
3617 0x5b, 0x9f, 0xf3, 0x9d, 0x36, 0xf1, 0x0b, 0xac, 0xc0, 0xfc, 0xba, 0x89, 3628 0x8c, 0x7b, 0x63, 0x7e, 0x67, 0xf3, 0xe6, 0xd7, 0x16, 0x03, 0xae, 0xc5,
3618 0x5f, 0xfa, 0x34, 0xf0, 0x88, 0xf3, 0x7f, 0x32, 0xb9, 0xf1, 0xa1, 0xc9, 3629 0x36, 0x9e, 0x63, 0xf6, 0x9b, 0xa7, 0xbb, 0x3f, 0xd7, 0x16, 0x23, 0x36,
3619 0xf1, 0xeb, 0x91, 0x89, 0xe7, 0x88, 0xfd, 0xe4, 0xe9, 0xfe, 0xfb, 0x05, 3630 0x8c, 0x9c, 0x8a, 0x6d, 0xac, 0xcd, 0xbe, 0x81, 0x63, 0xbf, 0xd6, 0xcf,
3620 0x83, 0x01, 0xc8, 0x8f, 0x53, 0x91, 0x89, 0xb5, 0xf9, 0x2b, 0x38, 0xf6, 3631 0x85, 0x01, 0x39, 0x93, 0xde, 0x23, 0x90, 0x83, 0x9a, 0x17, 0xac, 0xb1,
3621 0x9b, 0x69, 0x2e, 0x0c, 0xc9, 0x99, 0xf6, 0x1e, 0x4b, 0x73, 0xcb, 0xdf, 3632 0x3f, 0x88, 0xa7, 0xd0, 0x2f, 0x81, 0xae, 0xbb, 0x17, 0x2f, 0xc6, 0x31,
3622 0x30, 0x77, 0x8a, 0x19, 0xf4, 0x43, 0xa0, 0xeb, 0xef, 0xc5, 0x83, 0x49, 3633 0xd2, 0xde, 0x7f, 0x80, 0x5c, 0x0f, 0x36, 0xa4, 0x1c, 0xea, 0x4d, 0xbd,
3623 0x8c, 0xb4, 0xf7, 0x27, 0x90, 0xeb, 0xc1, 0x86, 0x94, 0x43, 0xbd, 0xa9, 3634 0x46, 0x25, 0x3a, 0x9b, 0xeb, 0xf4, 0x17, 0xab, 0xcb, 0xbf, 0xcb, 0xc3,
3624 0xd7, 0xb8, 0x84, 0x67, 0x73, 0x9d, 0x3e, 0x31, 0xba, 0xfc, 0xaf, 0x3c, 3635 0xfa, 0xce, 0xed, 0xf8, 0xbc, 0x01, 0xbe, 0x3f, 0xdf, 0x86, 0x0f, 0xeb,
3625 0xac, 0xef, 0xdc, 0x8e, 0xcf, 0x1b, 0xe2, 0xfb, 0xeb, 0x6d, 0xf8, 0xb0, 3636 0x3b, 0xe4, 0x19, 0xb9, 0xd9, 0x6b, 0xd4, 0x6f, 0xc6, 0x75, 0x82, 0xb8,
3626 0xbe, 0x43, 0x9e, 0xb1, 0xdd, 0x5e, 0xa2, 0xbe, 0x1b, 0xd7, 0x31, 0xe2, 3637 0x27, 0xef, 0xde, 0xbb, 0xdc, 0x60, 0x0e, 0xe4, 0x35, 0x9e, 0x71, 0xce,
3627 0x9e, 0xbc, 0x7b, 0xef, 0x79, 0xc3, 0x39, 0x90, 0xd7, 0x70, 0xc6, 0x39, 3638 0x3d, 0xf3, 0x58, 0xcf, 0x63, 0x3c, 0x8f, 0xf9, 0x3c, 0xd6, 0xc3, 0xf8,
3628 0xf7, 0xcc, 0x63, 0x3d, 0x8f, 0xf1, 0x3c, 0xe6, 0xf3, 0x58, 0x0f, 0xa2, 3639 0x19, 0xe9, 0xfb, 0x57, 0x6f, 0x84, 0xd8, 0x7f, 0xe4, 0x7f, 0xb8, 0xb7,
3629 0xe7, 0x24, 0xf5, 0xaf, 0xd3, 0x0b, 0xb0, 0xff, 0xd8, 0x1d, 0xee, 0x26, 3640 0x10, 0x23, 0x24, 0xb9, 0x75, 0xd7, 0xfb, 0x69, 0xd6, 0xaf, 0x94, 0x98,
3630 0x5f, 0x56, 0x8f, 0x24, 0xfe, 0xfc, 0x1e, 0xf8, 0xfb, 0xac, 0x67, 0x74, 3641 0x6b, 0xf8, 0xb3, 0x8f, 0xdf, 0x45, 0x7f, 0x10, 0x67, 0xb6, 0x4d, 0xb2,
3631 0x99, 0x6b, 0xf8, 0xb3, 0x4f, 0xbf, 0x89, 0xfa, 0x1f, 0x65, 0xb6, 0x8d, 3642 0xb1, 0x4f, 0xd3, 0xef, 0x07, 0xbf, 0x9a, 0x61, 0xf2, 0x17, 0xfb, 0xf5,
3632 0xb3, 0x31, 0xa5, 0x49, 0xfb, 0xbd, 0x9f, 0x64, 0x98, 0xfb, 0xfd, 0xb4, 3643 0x47, 0xf2, 0x9c, 0x62, 0x0e, 0xd9, 0x9c, 0xe2, 0x79, 0x70, 0x0f, 0x37,
3633 0xbe, 0x48, 0x9e, 0x53, 0xcc, 0x21, 0x93, 0x53, 0x3c, 0x0f, 0xee, 0xe8, 3644 0x66, 0x19, 0x7e, 0x7c, 0x3e, 0xce, 0xf3, 0x08, 0xf1, 0xf4, 0x40, 0x9e,
3634 0x5a, 0xaf, 0xc2, 0x8f, 0x2f, 0x45, 0x79, 0x1e, 0x21, 0x9e, 0x0e, 0xe7, 3645 0xe3, 0xb0, 0x53, 0x74, 0xc3, 0xe8, 0xe9, 0x04, 0x36, 0xe3, 0xdd, 0xb7,
3635 0x39, 0x0e, 0x3b, 0x85, 0xb7, 0xb4, 0x33, 0x1b, 0xc3, 0x66, 0xbc, 0x17, 3646 0x81, 0xde, 0x89, 0x76, 0x5a, 0x72, 0x9e, 0xb8, 0x79, 0xdf, 0xdd, 0xdb,
3636 0x37, 0xd0, 0x1b, 0xd1, 0x4e, 0x2b, 0xd6, 0x13, 0xbb, 0x77, 0xe1, 0xbd, 3647 0x27, 0xd1, 0x6e, 0xb4, 0xeb, 0xa0, 0xdd, 0xc2, 0x78, 0x5c, 0x11, 0x03,
3637 0x7d, 0x10, 0xed, 0x46, 0xbb, 0x0e, 0xdb, 0x2d, 0x88, 0x26, 0x15, 0x31, 3648 0x6e, 0x87, 0x13, 0x79, 0x3d, 0x07, 0x06, 0x4d, 0xe7, 0x76, 0xfa, 0xd8,
3638 0xe0, 0x76, 0x38, 0x91, 0xd7, 0x6b, 0x60, 0xd0, 0x6c, 0x6e, 0xa7, 0xaf, 3649 0x35, 0x3d, 0xe9, 0x7f, 0x2b, 0xd8, 0x8b, 0x0f, 0xdb, 0xee, 0x00, 0x3e,
3639 0x5c, 0xb3, 0xe3, 0xf4, 0x3b, 0xc2, 0x5e, 0x7c, 0xd8, 0xb4, 0x87, 0xf0, 3650 0xdc, 0xa6, 0xe7, 0xa4, 0x0c, 0xda, 0x00, 0xf5, 0xcd, 0xf6, 0x21, 0xec,
3640 0xe1, 0x36, 0x3d, 0x25, 0x65, 0xd0, 0x06, 0xa8, 0x5f, 0xa6, 0xcf, 0x60, 3651 0x31, 0x6f, 0x18, 0xd7, 0xf6, 0x9b, 0xc4, 0x46, 0xf6, 0x99, 0xdf, 0x2c,
3641 0x0f, 0x79, 0x4b, 0xdb, 0xa6, 0x9f, 0x24, 0x36, 0xb2, 0x8f, 0xec, 0x8c, 3652 0xc8, 0xc8, 0x3e, 0xfb, 0x9e, 0x6c, 0x73, 0x64, 0x4c, 0x48, 0xbf, 0x6e,
3642 0xc8, 0xd8, 0x3e, 0xf3, 0x1e, 0x6f, 0x73, 0x64, 0x4c, 0x48, 0x5a, 0x97, 3653 0x59, 0xfd, 0x1f, 0xcf, 0xf4, 0xef, 0xeb, 0x2c, 0xea, 0xa3, 0x30, 0x8d,
3643 0x8c, 0xfe, 0xcf, 0x64, 0xfa, 0xa7, 0x3a, 0x8b, 0xba, 0x13, 0xa6, 0x51, 3654 0xba, 0x7a, 0xd0, 0x35, 0xcc, 0xed, 0xd2, 0x52, 0xd5, 0x13, 0xd2, 0xa8,
3644 0x57, 0x0f, 0xba, 0x3e, 0x94, 0xdb, 0xa5, 0xa5, 0xaa, 0x27, 0xa4, 0x51, 3655 0xb0, 0x5f, 0x12, 0xdc, 0xb5, 0xa0, 0xc3, 0x02, 0xf5, 0x28, 0x43, 0x8f,
3645 0x31, 0x77, 0x5b, 0xdc, 0xa5, 0xa0, 0xc3, 0x12, 0xf5, 0x28, 0x43, 0x8f, 3656 0x51, 0xdc, 0x4d, 0xc2, 0xa5, 0x96, 0x84, 0xc9, 0x0a, 0x08, 0x67, 0xbe,
3646 0x71, 0xdc, 0x3d, 0x82, 0x95, 0x96, 0x04, 0xf1, 0x1a, 0x08, 0xe7, 0x7e, 3657 0x43, 0xbb, 0x1d, 0xd3, 0x5b, 0x1d, 0xda, 0xed, 0x49, 0xbd, 0xde, 0x99,
3647 0x4a, 0xbb, 0x3d, 0xed, 0x6e, 0x75, 0x69, 0xb7, 0x27, 0xdd, 0x4e, 0x77, 3658 0x44, 0x7f, 0x18, 0xc2, 0xdb, 0xe1, 0xec, 0x25, 0x61, 0x8c, 0xcd, 0xc5,
3648 0x1a, 0xfd, 0x5f, 0x00, 0x6f, 0x07, 0xf3, 0x97, 0x84, 0x31, 0xb6, 0x10, 3659 0x1c, 0x4f, 0x0b, 0xfb, 0xb1, 0x63, 0x7a, 0xaa, 0xcb, 0xf1, 0x49, 0x1d,
3649 0x71, 0x3c, 0x2d, 0xec, 0xb7, 0x9e, 0x76, 0x67, 0xfa, 0x1c, 0x9f, 0x74, 3660 0x75, 0x07, 0xe5, 0xfe, 0xc9, 0x00, 0x13, 0x93, 0xeb, 0xc8, 0xa3, 0x17,
3650 0xc3, 0xfe, 0xb0, 0xdc, 0xbf, 0x68, 0x60, 0x62, 0x7c, 0x03, 0x79, 0xf4, 3661 0x7b, 0xfd, 0xbd, 0x71, 0x3f, 0xcc, 0xe4, 0x62, 0x2e, 0xcd, 0x65, 0x0b,
3651 0xea, 0x20, 0xdd, 0x1b, 0xf7, 0xbf, 0x4c, 0x2e, 0xe6, 0x92, 0x5c, 0xb6, 3662 0x71, 0x8a, 0xb2, 0x21, 0x77, 0x32, 0xfe, 0x99, 0xdd, 0x83, 0xf7, 0xa3,
3652 0x10, 0xa7, 0x28, 0x1b, 0x72, 0xa7, 0xa3, 0xdf, 0x99, 0x3d, 0x78, 0xff, 3663 0x8f, 0xda, 0xe3, 0xae, 0xfc, 0xfb, 0x04, 0x72, 0xa7, 0x60, 0xb1, 0x67,
3653 0xb9, 0xd3, 0x1e, 0x77, 0xe7, 0xdf, 0x2e, 0x90, 0x3b, 0x05, 0x83, 0x3d, 3664 0x2d, 0xc5, 0x9d, 0xda, 0x37, 0xa6, 0x19, 0xbd, 0x0d, 0xdb, 0xa1, 0x47,
3654 0x1b, 0x09, 0xee, 0xcc, 0x25, 0xad, 0x9b, 0xe1, 0x87, 0xb0, 0x1d, 0x7a, 3665 0x98, 0xf7, 0xf0, 0x07, 0xae, 0x2e, 0x73, 0x0d, 0x7d, 0x38, 0xee, 0x82,
3655 0x80, 0x45, 0x0f, 0x7f, 0xe0, 0xea, 0x2a, 0xd7, 0xd0, 0x67, 0xe3, 0xae, 3666 0xbc, 0xcf, 0xad, 0xa5, 0x5c, 0x63, 0x8c, 0xa3, 0x57, 0x9c, 0xff, 0x15,
3656 0xc7, 0xfb, 0xda, 0x46, 0xc2, 0x35, 0xc6, 0x38, 0x7a, 0xc1, 0xc5, 0x8f, 3667 0x68, 0xdf, 0x31, 0xad, 0x9e, 0xb2, 0xf7, 0x75, 0x15, 0xe1, 0x1e, 0xd6,
3657 0x40, 0xfb, 0x81, 0x6e, 0x0d, 0x94, 0xb9, 0x8f, 0xab, 0x10, 0xf7, 0xac, 3668 0x63, 0x3f, 0x23, 0x4e, 0x23, 0x95, 0xa0, 0x19, 0x2f, 0xd8, 0xfb, 0x5a,
3658 0x01, 0xfb, 0x15, 0xb1, 0x1a, 0x89, 0xf8, 0xcd, 0x68, 0xc9, 0xdc, 0xc7, 3669 0xe2, 0x05, 0xbc, 0x93, 0xa2, 0x07, 0x9d, 0x1f, 0xe8, 0x41, 0xe7, 0xd1,
3659 0x62, 0xcf, 0xe7, 0x9d, 0x13, 0x3d, 0xe6, 0xe2, 0x50, 0x8f, 0xb9, 0x88, 3670 0x83, 0x8e, 0x15, 0x11, 0xe7, 0x09, 0xee, 0xa1, 0xaa, 0xd9, 0xcf, 0x9b,
3660 0x1e, 0xf3, 0x9e, 0x22, 0xe2, 0x3c, 0xc6, 0x3d, 0x53, 0x35, 0xd3, 0xbc, 3671 0x31, 0xde, 0x39, 0xdb, 0xbe, 0xec, 0x43, 0x77, 0x05, 0xdd, 0x22, 0xec,
3661 0x99, 0xe0, 0x9d, 0xb2, 0x5d, 0x92, 0x7d, 0xe8, 0x9e, 0xa0, 0x5b, 0x88, 3672 0xcf, 0xf5, 0x3b, 0xb3, 0xef, 0x5a, 0xa3, 0xa0, 0x4f, 0x6c, 0x3f, 0xd6,
3662 0xfd, 0xb9, 0x7e, 0x30, 0xfb, 0xee, 0x85, 0x4d, 0xc7, 0x62, 0xd3, 0x6f, 3673 0xf6, 0x8b, 0xd2, 0x8c, 0x49, 0x73, 0x28, 0xa3, 0xf9, 0xf2, 0x1e, 0x9a,
3663 0xb5, 0x4b, 0x23, 0xa8, 0xff, 0xa4, 0xb9, 0x2f, 0xa3, 0x79, 0x6e, 0x0f, 3674 0x3b, 0x79, 0x46, 0xca, 0x96, 0xe6, 0x2b, 0xcc, 0x3b, 0xd6, 0xd2, 0x62,
3664 0xcd, 0xd7, 0x78, 0x46, 0xca, 0x96, 0xe6, 0x1b, 0xcc, 0x3b, 0xd6, 0xd2, 3675 0x96, 0x6f, 0x27, 0xf0, 0x3c, 0x94, 0x3d, 0xe7, 0xf4, 0xf7, 0xee, 0xe1,
3665 0x91, 0x2c, 0xdf, 0x4e, 0xe0, 0xb9, 0x98, 0x3d, 0xe7, 0xf4, 0x87, 0xf7, 3676 0x7f, 0xc8, 0xe9, 0xbf, 0xf3, 0x99, 0x3a, 0x27, 0xec, 0x93, 0x21, 0x6f,
3666 0xf0, 0x3f, 0xa2, 0xd2, 0x77, 0x3e, 0x53, 0xe7, 0x98, 0x7d, 0x30, 0xe4, 3677 0xc1, 0xe9, 0x7f, 0x27, 0xc1, 0x85, 0x73, 0x84, 0x3e, 0xe9, 0xf7, 0x17,
3667 0x2d, 0x59, 0xe9, 0xb7, 0x92, 0xf3, 0x38, 0x3b, 0x7d, 0x92, 0xf6, 0x17, 3678 0xc0, 0x60, 0x74, 0x5f, 0x53, 0xb0, 0xbb, 0x31, 0xed, 0x05, 0xe2, 0xda,
3668 0xc0, 0x60, 0x74, 0x57, 0x33, 0xb0, 0xbb, 0xd6, 0xed, 0x25, 0xe2, 0xda, 3679 0xdc, 0xec, 0x11, 0x8b, 0x6f, 0x6a, 0x42, 0x49, 0x8e, 0xb9, 0x83, 0xcf,
3669 0xc2, 0xfc, 0x11, 0x83, 0x6f, 0x6a, 0x4a, 0x49, 0x8e, 0xb9, 0xc3, 0xcf, 3680 0x18, 0x17, 0xec, 0x37, 0x03, 0xbc, 0xf7, 0x65, 0x6c, 0xe1, 0xfe, 0x2c,
3670 0x18, 0x97, 0xcc, 0x37, 0x01, 0xbc, 0xa7, 0x32, 0xb6, 0x70, 0x3f, 0x16, 3681 0xc8, 0xe1, 0x96, 0xd5, 0xcb, 0xe9, 0xdf, 0x8b, 0xbc, 0x1a, 0xeb, 0x01,
3671 0xe4, 0x70, 0xcb, 0xe8, 0x65, 0xa5, 0xf7, 0x1e, 0xaf, 0xc6, 0x7a, 0x80, 3682 0xea, 0xc6, 0x0c, 0xf5, 0xba, 0xf9, 0x6d, 0x63, 0x05, 0xb5, 0xe6, 0x2d,
3672 0xba, 0xf1, 0x20, 0xf5, 0xda, 0xfd, 0x76, 0xb1, 0x86, 0x5a, 0xf3, 0x2e, 3683 0xc4, 0x3e, 0xf2, 0xd3, 0xf6, 0x58, 0x5b, 0xf6, 0xdb, 0x02, 0xea, 0xd0,
3673 0x62, 0x1f, 0xf9, 0x69, 0x7a, 0xa8, 0x2d, 0xf3, 0xed, 0x00, 0x75, 0x08, 3684 0x08, 0xee, 0x4b, 0xd1, 0xcd, 0x6f, 0x0c, 0x72, 0x01, 0x34, 0x17, 0xb1,
3674 0xd7, 0xa0, 0x4e, 0xb8, 0xfb, 0x0d, 0x41, 0x2e, 0x80, 0xe6, 0x22, 0xd6, 3685 0x76, 0xba, 0x9b, 0xf7, 0xbc, 0xe8, 0xf3, 0x81, 0x7b, 0xab, 0xd1, 0xfb,
3675 0x4e, 0xf7, 0xf3, 0x9e, 0x16, 0x7d, 0x3c, 0x70, 0x6f, 0x3d, 0xfc, 0x97, 3686 0xa6, 0xe9, 0x0f, 0xd2, 0xf2, 0xf7, 0x2f, 0x97, 0xa2, 0x15, 0x3a, 0x18,
3676 0x6e, 0x96, 0x86, 0x69, 0xf9, 0xfb, 0x2f, 0xb4, 0x78, 0xd5, 0x79, 0x38,
3677 0x15, 0x00, 0x00, 0x00 }; 3687 0x15, 0x00, 0x00, 0x00 };
3678 3688
3679static const u32 bnx2_TPAT_b09FwData[(0x0/4) + 1] = { 0x0 }; 3689static const u32 bnx2_TPAT_b09FwData[(0x0/4) + 1] = { 0x0 };
@@ -3681,15 +3691,15 @@ static const u32 bnx2_TPAT_b09FwRodata[(0x4/4) + 1] = {
3681 0x00000001, 0x00000000 }; 3691 0x00000001, 0x00000000 };
3682 3692
3683static struct fw_info bnx2_tpat_fw_09 = { 3693static struct fw_info bnx2_tpat_fw_09 = {
3684 /* Firmware version: 4.0.5 */ 3694 /* Firmware version: 4.4.26 */
3685 .ver_major = 0x4, 3695 .ver_major = 0x4,
3686 .ver_minor = 0x0, 3696 .ver_minor = 0x4,
3687 .ver_fix = 0x5, 3697 .ver_fix = 0x1a,
3688 3698
3689 .start_addr = 0x08000888, 3699 .start_addr = 0x08000488,
3690 3700
3691 .text_addr = 0x08000800, 3701 .text_addr = 0x08000400,
3692 .text_len = 0x1534, 3702 .text_len = 0x1514,
3693 .text_index = 0x0, 3703 .text_index = 0x0,
3694 .gz_text = bnx2_TPAT_b09FwText, 3704 .gz_text = bnx2_TPAT_b09FwText,
3695 .gz_text_len = sizeof(bnx2_TPAT_b09FwText), 3705 .gz_text_len = sizeof(bnx2_TPAT_b09FwText),
@@ -3699,863 +3709,871 @@ static struct fw_info bnx2_tpat_fw_09 = {
3699 .data_index = 0x0, 3709 .data_index = 0x0,
3700 .data = bnx2_TPAT_b09FwData, 3710 .data = bnx2_TPAT_b09FwData,
3701 3711
3702 .sbss_addr = 0x08001d60, 3712 .sbss_addr = 0x08001940,
3703 .sbss_len = 0x48, 3713 .sbss_len = 0x48,
3704 .sbss_index = 0x0, 3714 .sbss_index = 0x0,
3705 3715
3706 .bss_addr = 0x08001da8, 3716 .bss_addr = 0x08001988,
3707 .bss_len = 0x10a0, 3717 .bss_len = 0x12b4,
3708 .bss_index = 0x0, 3718 .bss_index = 0x0,
3709 3719
3710 .rodata_addr = 0x08001d34, 3720 .rodata_addr = 0x08001914,
3711 .rodata_len = 0x4, 3721 .rodata_len = 0x4,
3712 .rodata_index = 0x0, 3722 .rodata_index = 0x0,
3713 .rodata = bnx2_TPAT_b09FwRodata, 3723 .rodata = bnx2_TPAT_b09FwRodata,
3714}; 3724};
3715 3725
3716static u8 bnx2_TXP_b09FwText[] = { 3726static u8 bnx2_TXP_b09FwText[] = {
3717 0xa5, 0x7b, 0x0b, 0x74, 0x1c, 0x55, 0x7a, 0xe6, 0x77, 0xab, 0xba, 0xa5, 3727 0xc5, 0x7b, 0x7b, 0x74, 0x1c, 0x55, 0x9a, 0xdf, 0xef, 0x56, 0x3f, 0x54,
3718 0xea, 0x56, 0xab, 0x55, 0x92, 0xdb, 0xa6, 0x95, 0xd1, 0xe0, 0x2e, 0x77, 3728 0xdd, 0x6a, 0xb5, 0x4a, 0x72, 0xdb, 0x6e, 0xed, 0x68, 0xc6, 0x5d, 0xee,
3719 0xb5, 0xdc, 0x58, 0xc2, 0x54, 0xcb, 0x2d, 0xd3, 0x44, 0xe5, 0xb8, 0xc7, 3729 0x6a, 0xb9, 0xb1, 0x84, 0x5d, 0x2d, 0xb5, 0xec, 0x66, 0x5d, 0xb1, 0x7b,
3720 0x08, 0x5b, 0x06, 0x4d, 0x46, 0x38, 0xca, 0xac, 0x98, 0xc3, 0x2e, 0x1d, 3730 0x8c, 0xb0, 0x65, 0x10, 0x3b, 0xc2, 0xeb, 0x9d, 0x88, 0x09, 0x27, 0xf4,
3721 0x63, 0x83, 0x30, 0x06, 0x04, 0xc3, 0x66, 0x95, 0x2c, 0x89, 0x6a, 0xe4, 3731 0x18, 0x19, 0x64, 0x63, 0x40, 0x30, 0x64, 0xa3, 0xd9, 0x25, 0xeb, 0x1a,
3722 0x07, 0x7e, 0xb4, 0xba, 0xf5, 0x32, 0x32, 0xd9, 0x9c, 0xb8, 0x2d, 0xc9, 3732 0xf9, 0x81, 0x1f, 0xad, 0xee, 0xd6, 0xc3, 0xc8, 0xec, 0xd9, 0x13, 0x64,
3723 0x96, 0x81, 0x7e, 0xc0, 0x00, 0x33, 0x43, 0x76, 0x67, 0xe9, 0x35, 0x60, 3733 0x49, 0xb6, 0xcc, 0xd0, 0x0f, 0x33, 0xc0, 0xcc, 0x30, 0x27, 0x13, 0x77,
3724 0x0c, 0x8c, 0x61, 0x92, 0x3d, 0x67, 0x97, 0xc9, 0x99, 0x49, 0x7c, 0x30, 3734 0x8c, 0x01, 0x03, 0x63, 0x98, 0xdd, 0x6c, 0x92, 0x99, 0x3d, 0x49, 0xd6,
3725 0x78, 0x6c, 0xde, 0x9b, 0x99, 0xdd, 0x15, 0x09, 0x93, 0xda, 0xff, 0xaf, 3735 0x07, 0xf3, 0xb0, 0xc1, 0x60, 0x32, 0x43, 0x12, 0xb1, 0xcb, 0x4c, 0xe5,
3726 0x96, 0x8c, 0x61, 0xd8, 0x24, 0x9b, 0xd5, 0x39, 0x7d, 0x4a, 0x5d, 0x75, 3736 0xfb, 0xaa, 0x25, 0x63, 0x58, 0xb2, 0x9b, 0x6c, 0xfe, 0x88, 0xce, 0xd1,
3727 0xeb, 0xde, 0xff, 0xfd, 0x7f, 0xff, 0x7f, 0x6f, 0x47, 0x00, 0x2f, 0x16, 3737 0xe9, 0xee, 0xaa, 0x5b, 0xf7, 0x7e, 0xef, 0xef, 0xf7, 0x7d, 0xf7, 0x56,
3728 0xfe, 0x6a, 0xe9, 0x13, 0x1f, 0x18, 0x7c, 0xb0, 0x7d, 0xb5, 0xb1, 0xda, 3738 0x04, 0xf0, 0x62, 0xee, 0xaf, 0x86, 0xfe, 0xe3, 0xfd, 0x03, 0x0f, 0xb7,
3729 0xb9, 0xe1, 0x86, 0x8b, 0x1f, 0xae, 0x15, 0x40, 0xea, 0x5d, 0xfc, 0x8b, 3739 0xae, 0x88, 0xaf, 0xa0, 0xaf, 0x6d, 0x58, 0xec, 0x74, 0xf2, 0xcd, 0x55,
3730 0xfe, 0xbe, 0xfa, 0x2f, 0x7b, 0x0d, 0x32, 0xa0, 0x2e, 0xd2, 0xc4, 0x1f, 3740 0x02, 0x48, 0xbd, 0x87, 0x7f, 0xd4, 0xdf, 0x57, 0xff, 0x71, 0x8f, 0xc1,
3731 0x28, 0x92, 0x99, 0xfb, 0xcd, 0x0d, 0x3a, 0x14, 0xd9, 0xec, 0x5b, 0x77, 3741 0x01, 0x28, 0xf3, 0x34, 0xf1, 0x3f, 0x64, 0xc9, 0x30, 0xd7, 0xac, 0xd7,
3732 0xbb, 0x0e, 0x24, 0xf3, 0x2d, 0xa1, 0xeb, 0xf1, 0x2b, 0xdb, 0x0a, 0xb8, 3742 0x20, 0x3b, 0x8c, 0xc4, 0xda, 0xbb, 0x34, 0x20, 0x99, 0x6f, 0x0e, 0xdd,
3733 0xc0, 0xf7, 0xbf, 0x6a, 0x7e, 0x3a, 0xf4, 0xc3, 0x6b, 0xb5, 0x8f, 0x73, 3743 0x88, 0xdf, 0x58, 0x66, 0xc0, 0x09, 0xbe, 0xfe, 0x55, 0xe3, 0xd3, 0x5d,
3734 0x32, 0x14, 0xd5, 0x9c, 0x84, 0xda, 0x0c, 0xa5, 0x89, 0xde, 0xf9, 0xd3, 3744 0x3f, 0x5d, 0xad, 0x7e, 0x34, 0xe1, 0x80, 0xac, 0x18, 0x63, 0x50, 0x9a,
3735 0x95, 0xdf, 0x77, 0xc1, 0xbf, 0x38, 0x17, 0x2c, 0xb7, 0x69, 0x60, 0x57, 3745 0x20, 0x37, 0xd2, 0x33, 0x7f, 0xb6, 0xec, 0x79, 0x27, 0xfc, 0xf3, 0x73,
3736 0x76, 0x00, 0x73, 0x71, 0xe0, 0x42, 0x3a, 0x62, 0xec, 0x02, 0x46, 0x25, 3746 0xc1, 0x74, 0x19, 0x3a, 0x76, 0x67, 0xfb, 0x31, 0x13, 0x07, 0x2e, 0xa6,
3737 0x33, 0x12, 0x3a, 0x89, 0x10, 0x66, 0xf3, 0xb0, 0xaa, 0x4d, 0x1d, 0xfb, 3747 0x23, 0xfa, 0x6e, 0x20, 0x27, 0x19, 0x91, 0xd0, 0x69, 0x84, 0x30, 0x9d,
3738 0x4a, 0x21, 0x5c, 0x4c, 0xff, 0x83, 0x1d, 0x72, 0x0f, 0xe0, 0xed, 0x38, 3748 0x87, 0x59, 0x65, 0x68, 0xd8, 0x5f, 0x0a, 0xe1, 0x52, 0xfa, 0xb7, 0x56,
3739 0x94, 0xa0, 0xf9, 0x10, 0x82, 0x59, 0x28, 0xb5, 0xe6, 0x20, 0x0a, 0x23, 3749 0xc8, 0xd5, 0x8f, 0xb7, 0xe2, 0x90, 0x83, 0xc6, 0x23, 0x08, 0x66, 0x21,
3740 0xc0, 0x9e, 0xb4, 0x36, 0x00, 0x68, 0x7d, 0x45, 0x11, 0x3e, 0x7d, 0x02, 3750 0xd7, 0x18, 0x03, 0x28, 0x0c, 0x01, 0x7b, 0xd3, 0x6a, 0x3f, 0xa0, 0xf6,
3741 0x5a, 0x4f, 0xa3, 0xdc, 0x92, 0xba, 0x45, 0x68, 0xc9, 0x9d, 0x02, 0x8a, 3751 0x14, 0x45, 0xf8, 0xec, 0x09, 0xa8, 0xdd, 0x0d, 0x8e, 0xe6, 0xd4, 0xed,
3742 0xa0, 0xb1, 0xab, 0xf2, 0x7c, 0x1d, 0x44, 0x34, 0xaf, 0xe0, 0xac, 0xcc, 3752 0x42, 0x4d, 0xee, 0x14, 0x90, 0x05, 0x8d, 0x5d, 0x9e, 0xe7, 0xcf, 0x01,
3743 0xcb, 0x9a, 0x24, 0x67, 0x01, 0x97, 0x6e, 0x60, 0x4f, 0x16, 0x96, 0xcb, 3753 0x44, 0xf3, 0x32, 0xce, 0x3b, 0x78, 0x59, 0x83, 0xe4, 0x2c, 0xe0, 0xd4,
3744 0x14, 0xd8, 0x15, 0x8f, 0xa8, 0x33, 0xe0, 0xe7, 0x21, 0x0c, 0x3b, 0xe3, 3754 0x74, 0xec, 0xcd, 0xc2, 0x74, 0x1a, 0x02, 0xbb, 0xe3, 0x11, 0x65, 0x0a,
3745 0x34, 0xe2, 0xd8, 0xb6, 0x77, 0x1b, 0xb6, 0x7d, 0xcc, 0xa8, 0x86, 0xa5, 3755 0x7c, 0x3f, 0x84, 0x41, 0x7b, 0x9c, 0x4a, 0x1c, 0x5b, 0xd6, 0x1e, 0xdd,
3746 0x6a, 0x41, 0x40, 0x60, 0xd8, 0x90, 0x90, 0x54, 0x37, 0x84, 0x5c, 0xd0, 3756 0xb2, 0x8e, 0xe9, 0x55, 0x30, 0x15, 0x35, 0x08, 0x08, 0x0c, 0xea, 0x12,
3747 0x82, 0xdb, 0xf1, 0xf7, 0xc4, 0x6f, 0x32, 0xea, 0x46, 0x65, 0x7c, 0x0a, 3757 0x92, 0xca, 0xfa, 0x90, 0x13, 0x6a, 0x70, 0x1b, 0xfe, 0x96, 0xf8, 0x4d,
3748 0xd5, 0x28, 0xab, 0x15, 0x89, 0x4d, 0xa7, 0x6d, 0xfb, 0x94, 0xee, 0xc2, 3758 0x46, 0x5d, 0xa8, 0x8c, 0x4f, 0xa1, 0x0a, 0x65, 0xa5, 0x22, 0xb1, 0xc9,
3749 0x31, 0x92, 0xcd, 0x70, 0xfe, 0xef, 0xed, 0x32, 0xc9, 0x65, 0xb7, 0xbe, 3759 0xb4, 0x65, 0xbd, 0xa4, 0x39, 0x71, 0x8c, 0x64, 0x33, 0x98, 0xff, 0x5b,
3750 0xb8, 0xbe, 0x82, 0x9c, 0x6a, 0xdb, 0x33, 0xf4, 0x6c, 0x6f, 0x7e, 0x51, 3760 0xab, 0x4c, 0x72, 0xd9, 0xa3, 0xcd, 0xaf, 0x2f, 0x63, 0x42, 0xb1, 0xac,
3751 0xc6, 0xb6, 0x2d, 0xe9, 0xb6, 0x7d, 0xbb, 0xfe, 0x77, 0xf6, 0xd6, 0xcf, 3761 0x29, 0xba, 0xb7, 0x2f, 0x3f, 0x2f, 0x63, 0xcb, 0x92, 0x34, 0xcb, 0xba,
3752 0x8d, 0x8d, 0xe1, 0xf1, 0x51, 0x15, 0x4f, 0x64, 0x93, 0xc8, 0xa7, 0x6d, 3762 0x4b, 0xfb, 0x1b, 0x6b, 0xeb, 0xe7, 0xc6, 0xc6, 0xf0, 0xfd, 0x9c, 0x82,
3753 0xc8, 0xa6, 0x0b, 0xfd, 0x23, 0x21, 0xec, 0x2c, 0x74, 0xa2, 0x90, 0xd6, 3763 0xa7, 0xb2, 0x49, 0xe4, 0xd3, 0x16, 0x1c, 0x86, 0x13, 0x7d, 0x43, 0x21,
3754 0x52, 0x67, 0xe9, 0xbd, 0xad, 0x71, 0x1d, 0xf7, 0x14, 0xba, 0x30, 0x97, 3764 0xec, 0x2c, 0x74, 0xa0, 0x90, 0x56, 0x53, 0xe7, 0xe9, 0xb9, 0xad, 0x71,
3755 0x86, 0xed, 0x31, 0xf5, 0xb2, 0x47, 0x44, 0x71, 0x67, 0xa1, 0x1b, 0xc5, 3765 0x0d, 0xf7, 0x15, 0x3a, 0x31, 0x93, 0x86, 0xe5, 0x31, 0xb4, 0xb2, 0x47,
3756 0xb4, 0x7e, 0x7a, 0x58, 0x44, 0x06, 0x1b, 0x65, 0x17, 0xee, 0x2b, 0xb4, 3766 0x44, 0x71, 0x4f, 0xa1, 0x0b, 0xc5, 0xb4, 0x76, 0x76, 0x50, 0x44, 0x06,
3757 0xe2, 0xde, 0x42, 0x82, 0xde, 0xb1, 0x71, 0x63, 0xac, 0x89, 0xc6, 0xb7, 3767 0x1a, 0x1c, 0x4e, 0x3c, 0x50, 0x68, 0xc1, 0xfd, 0x85, 0x04, 0x3d, 0x63,
3758 0xe1, 0xb1, 0x49, 0xdb, 0x8e, 0xc6, 0x54, 0xf4, 0x17, 0x0c, 0xcc, 0x8d, 3768 0xe1, 0xe6, 0x58, 0x23, 0x8d, 0x6f, 0xc5, 0x93, 0x63, 0x96, 0x15, 0x8d,
3759 0x4a, 0x48, 0x1d, 0x73, 0x21, 0x75, 0x14, 0xb8, 0xf3, 0x68, 0x1b, 0x66, 3769 0x29, 0xe8, 0x2b, 0xe8, 0x98, 0xc9, 0x49, 0x48, 0x1d, 0x73, 0x22, 0x75,
3760 0x46, 0x6d, 0x6c, 0x35, 0x86, 0x1b, 0x25, 0x32, 0xbb, 0x94, 0x2a, 0xe0, 3770 0x14, 0xb8, 0xe7, 0x68, 0x2b, 0xa6, 0x72, 0x16, 0xb6, 0xea, 0x83, 0x0d,
3761 0xd6, 0xfd, 0xd8, 0xae, 0x56, 0x68, 0x3f, 0x2b, 0x0b, 0xec, 0x38, 0x1a, 3771 0x12, 0x5c, 0x48, 0x29, 0x02, 0x2e, 0xcd, 0x8f, 0x6d, 0x4a, 0x85, 0xf6,
3762 0xc5, 0x9b, 0x69, 0x0b, 0x37, 0xb6, 0x07, 0x31, 0x58, 0x08, 0xe0, 0x8d, 3772 0xf3, 0x0e, 0x81, 0x1d, 0x47, 0xa3, 0xf8, 0x45, 0xda, 0xc4, 0xcd, 0xed,
3763 0x74, 0x80, 0xd6, 0x30, 0xf0, 0x7a, 0x5a, 0xa1, 0x75, 0x5a, 0xf1, 0x62, 3773 0x41, 0x0c, 0x14, 0x02, 0x78, 0x23, 0x1d, 0xa0, 0x35, 0x74, 0xbc, 0x9e,
3764 0x9a, 0xc7, 0xf0, 0x58, 0x1f, 0xb6, 0x15, 0x9a, 0x70, 0x26, 0x1d, 0xa4, 3774 0x96, 0x69, 0x9d, 0x16, 0x9c, 0x49, 0xf3, 0x18, 0x1e, 0xeb, 0x43, 0x6f,
3765 0x35, 0x03, 0x78, 0x85, 0xc6, 0xdd, 0x55, 0xd0, 0x71, 0x9a, 0xc6, 0xf5, 3775 0xa1, 0x11, 0xe7, 0xd2, 0x41, 0x5a, 0x33, 0x80, 0x57, 0x68, 0xdc, 0xf6,
3766 0x17, 0x42, 0x78, 0x39, 0xed, 0x23, 0x5a, 0x03, 0x38, 0x99, 0x1e, 0xc0, 3776 0x82, 0x86, 0xb3, 0x34, 0xae, 0xaf, 0x10, 0xc2, 0xcb, 0x69, 0x1f, 0xd1,
3767 0xae, 0x74, 0xcb, 0xe9, 0xeb, 0x49, 0x86, 0xa1, 0x25, 0xbc, 0x0e, 0xdf, 3777 0x1a, 0xc0, 0xe9, 0x74, 0x3f, 0x76, 0xa7, 0x9b, 0xcf, 0xde, 0x48, 0x32,
3768 0x7b, 0xdb, 0xee, 0x0e, 0x38, 0x66, 0x42, 0xeb, 0x2c, 0xae, 0x3b, 0x80, 3778 0x0c, 0x2d, 0xe0, 0x75, 0xf8, 0xda, 0x5b, 0x56, 0x57, 0xc0, 0x36, 0x13,
3769 0xe1, 0xf4, 0x8b, 0x0b, 0x7e, 0x62, 0x60, 0xff, 0xe8, 0xbc, 0xfd, 0xc3, 3779 0x5a, 0x67, 0x7e, 0xdd, 0x7e, 0x0c, 0xa6, 0xcf, 0xcc, 0xf9, 0x89, 0x8e,
3770 0x95, 0x4d, 0x38, 0x91, 0x05, 0x1e, 0x9b, 0x01, 0x66, 0xb2, 0x96, 0x5d, 3780 0x03, 0xb9, 0x59, 0xeb, 0xa7, 0xcb, 0x1a, 0x71, 0x22, 0x0b, 0x3c, 0x39,
3771 0x6b, 0xda, 0xf6, 0x74, 0x7b, 0x2b, 0xc9, 0x4b, 0xef, 0xdb, 0x4a, 0xa3, 3781 0x05, 0x4c, 0x65, 0x4d, 0xab, 0xc6, 0xb0, 0xac, 0xc9, 0xf6, 0x16, 0x92,
3772 0x9e, 0x28, 0xb9, 0x80, 0xa3, 0x5a, 0x5f, 0x19, 0x12, 0x72, 0x73, 0x2e, 3782 0x97, 0xd6, 0xb3, 0x95, 0x46, 0x3d, 0x55, 0x72, 0x02, 0x47, 0xd5, 0x9e,
3773 0x54, 0x8d, 0x68, 0x5d, 0x39, 0x68, 0xa7, 0xef, 0x24, 0x4f, 0x3a, 0x96, 3783 0x32, 0x24, 0x4c, 0xcc, 0x38, 0xe1, 0x1e, 0x52, 0x3b, 0x27, 0xa0, 0x9e,
3774 0xd5, 0x7a, 0x2c, 0x0c, 0xd9, 0x41, 0xb3, 0x39, 0xd4, 0x2a, 0xdb, 0xf0, 3784 0xbd, 0x87, 0x3c, 0xe9, 0x58, 0x56, 0xed, 0x36, 0xb1, 0xcb, 0x0a, 0x1a,
3775 0x93, 0x2d, 0xa4, 0x5b, 0x6d, 0xbb, 0xee, 0x5a, 0xdb, 0x3e, 0xd3, 0x0e, 3785 0x4d, 0xa1, 0x16, 0x87, 0x05, 0x3f, 0xd9, 0x42, 0xba, 0xc5, 0xb2, 0x6a,
3776 0x5b, 0x32, 0xf5, 0xd3, 0x25, 0xe8, 0xe5, 0x0f, 0xa0, 0x0f, 0x9e, 0x44, 3786 0x57, 0x5b, 0xd6, 0xb9, 0x76, 0x58, 0x92, 0xa1, 0x9d, 0x2d, 0x41, 0x2b,
3777 0xf9, 0xab, 0x3e, 0x44, 0xfa, 0xc3, 0x72, 0x64, 0x60, 0x9e, 0xde, 0xad, 3787 0x7f, 0x00, 0x6d, 0xe0, 0x34, 0xca, 0x5f, 0xf5, 0x21, 0xd2, 0x17, 0x76,
3778 0x2d, 0x90, 0x29, 0x13, 0x2f, 0x3a, 0xd9, 0x60, 0xa1, 0xa4, 0xc0, 0x45, 3788 0x44, 0xfa, 0x67, 0xe9, 0xd9, 0x9a, 0x02, 0x99, 0x32, 0xf1, 0xa2, 0x91,
3779 0xfc, 0xb4, 0x8e, 0xd8, 0xb6, 0x4b, 0xf7, 0xc1, 0x47, 0xf2, 0xdd, 0x74, 3789 0x0d, 0x16, 0x4a, 0x32, 0x9c, 0xc4, 0x4f, 0xcb, 0x90, 0x65, 0x39, 0x35,
3780 0xc8, 0xb6, 0xcf, 0x1b, 0x2a, 0xaa, 0x48, 0x37, 0x37, 0x8c, 0xd9, 0x98, 3790 0x1f, 0x7c, 0x24, 0xdf, 0x8d, 0x87, 0x2d, 0xeb, 0x1d, 0x5d, 0x81, 0x9b,
3781 0x36, 0x4e, 0x92, 0x3c, 0x05, 0x52, 0x3d, 0x71, 0x7a, 0x27, 0x40, 0xe3, 3791 0x74, 0x73, 0xd3, 0xb0, 0x85, 0x49, 0xfd, 0x34, 0xc9, 0x53, 0x20, 0xd5,
3782 0x13, 0xd8, 0x34, 0x12, 0xc4, 0xe3, 0x59, 0x05, 0x3f, 0x5c, 0x19, 0x45, 3792 0x1d, 0xa7, 0x67, 0x02, 0x34, 0x3e, 0x81, 0x8d, 0x43, 0x41, 0x7c, 0x3f,
3783 0x0d, 0xcd, 0xe5, 0x25, 0x59, 0x55, 0x93, 0xfc, 0x50, 0x20, 0x73, 0x2b, 3793 0x2b, 0xe3, 0xa7, 0xcb, 0xa2, 0xa8, 0xa6, 0xb9, 0xbc, 0x24, 0xab, 0x2a,
3784 0x54, 0xec, 0x11, 0x85, 0xb3, 0xc4, 0x63, 0x10, 0xdf, 0x2d, 0x05, 0xf0, 3794 0x92, 0x1f, 0x0a, 0x64, 0x6e, 0x85, 0x8a, 0x3d, 0xa2, 0x70, 0x9e, 0x78,
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4081 0xdf, 0x28, 0x34, 0x91, 0xbc, 0x83, 0xb8, 0xbe, 0x10, 0xc2, 0x89, 0x34, 4091 0xb4, 0x0f, 0xb7, 0x17, 0xe2, 0x84, 0xbd, 0x15, 0xa2, 0x3d, 0x81, 0x52,
4082 0xe7, 0x6f, 0xd3, 0xb3, 0x35, 0xde, 0x84, 0xae, 0x82, 0x8e, 0xd9, 0x34, 4092 0x3a, 0x80, 0x6f, 0x14, 0x1a, 0x49, 0xde, 0x41, 0xdc, 0x58, 0x08, 0xe1,
4083 0x3c, 0xf7, 0xc5, 0x43, 0xe8, 0x2c, 0x44, 0x51, 0x20, 0x0c, 0xf7, 0x75, 4093 0x44, 0x9a, 0xf3, 0xb7, 0xe1, 0xd9, 0x1a, 0x6f, 0x44, 0x67, 0x41, 0xc3,
4084 0x9a, 0xf3, 0x16, 0xd2, 0x49, 0x6b, 0x21, 0x80, 0x15, 0x11, 0xe0, 0xba, 4094 0x74, 0x1a, 0x9e, 0x07, 0xe2, 0x21, 0x74, 0x14, 0xa2, 0x28, 0x10, 0x86,
4085 0x82, 0x4f, 0x0c, 0x12, 0xb6, 0x4a, 0x14, 0x1a, 0x70, 0x61, 0x8c, 0xed, 4095 0xbb, 0x95, 0xe6, 0xbc, 0x9d, 0x74, 0xd2, 0x52, 0x08, 0x60, 0x69, 0x84,
4086 0xdc, 0xe8, 0xd8, 0x3d, 0xaa, 0x22, 0x54, 0xc0, 0x35, 0x0a, 0xb0, 0x93, 4096 0x22, 0x72, 0xc1, 0x27, 0x06, 0x08, 0x5b, 0x25, 0x0a, 0xf5, 0xb8, 0x38,
4087 0xaa, 0xc3, 0x54, 0x81, 0xe8, 0x3d, 0xd0, 0x5e, 0xe9, 0xdd, 0xae, 0x2a, 4097 0xcc, 0x76, 0xae, 0x18, 0x7b, 0x72, 0x0a, 0x42, 0x05, 0xac, 0x94, 0x01,
4088 0x7c, 0xc6, 0x6f, 0x1d, 0xe9, 0xe9, 0xa3, 0x43, 0xb3, 0xde, 0x4f, 0xe2, 4098 0x0a, 0xd6, 0x91, 0x54, 0x81, 0xe8, 0x3d, 0xd8, 0x5e, 0xe9, 0xe1, 0x2e,
4089 0x1c, 0x9b, 0x9a, 0x3a, 0x5e, 0x3f, 0x04, 0x44, 0xa7, 0x98, 0x37, 0x27, 4099 0x2f, 0x7c, 0xc6, 0x6f, 0x2d, 0xe9, 0xe9, 0xca, 0xe1, 0x69, 0xef, 0x27,
4090 0x36, 0x72, 0x3c, 0x6c, 0x55, 0xf0, 0xb7, 0x36, 0xd5, 0xa0, 0xa1, 0x19, 4100 0x71, 0x8e, 0x4d, 0x9f, 0xae, 0x79, 0xfd, 0x30, 0x10, 0x1d, 0x67, 0xde,
4091 0xde, 0x23, 0xd0, 0x7d, 0x44, 0x87, 0x8a, 0x24, 0xad, 0x7d, 0x53, 0xe1, 4101 0xec, 0xd8, 0xc8, 0xf1, 0xb0, 0x45, 0xc6, 0xaf, 0x2c, 0xaa, 0x41, 0x43,
4092 0x7b, 0xf6, 0xd6, 0xa5, 0x41, 0xdc, 0x18, 0xa9, 0xc8, 0xea, 0x0c, 0xe9, 4102 0x53, 0xbc, 0x57, 0xa0, 0xf9, 0x88, 0x0e, 0x05, 0x49, 0x5a, 0xfb, 0x96,
4093 0x70, 0x7a, 0xac, 0x11, 0x73, 0x44, 0x83, 0xdb, 0x6c, 0xee, 0x38, 0x36, 4103 0xc2, 0x0f, 0xad, 0xad, 0x0b, 0x83, 0xb8, 0x39, 0x52, 0x91, 0xd5, 0x39,
4094 0x69, 0x63, 0xa3, 0x61, 0x79, 0x5f, 0x6b, 0x5f, 0x85, 0x7b, 0x0f, 0x0d, 4104 0xd2, 0xe1, 0xe4, 0x70, 0x03, 0x66, 0x88, 0x06, 0x97, 0xe1, 0x36, 0x8e,
4095 0x9f, 0xae, 0x22, 0xbd, 0xce, 0x1b, 0xb7, 0xe2, 0xe1, 0x29, 0x5c, 0xd9, 4105 0x8d, 0x59, 0xd8, 0xa0, 0x9b, 0xde, 0xd7, 0xda, 0x97, 0xe3, 0xfe, 0xc3,
4096 0x08, 0x3c, 0x14, 0x04, 0xf7, 0xaa, 0xb5, 0xd0, 0x09, 0x44, 0xba, 0xee, 4106 0x83, 0x67, 0xdd, 0xa4, 0xd7, 0x59, 0xfd, 0x0e, 0x3c, 0x3a, 0x8e, 0xaf,
4097 0x43, 0x44, 0xd5, 0x85, 0x66, 0xbc, 0x2c, 0x90, 0xac, 0x31, 0x23, 0xa7, 4107 0x35, 0x00, 0x8f, 0x04, 0xc1, 0x3d, 0x6b, 0x35, 0x74, 0x02, 0x91, 0xce,
4098 0x6f, 0x02, 0x5e, 0xac, 0x22, 0x0f, 0xbe, 0xa5, 0xe0, 0x22, 0x19, 0x05, 4108 0x07, 0x10, 0x51, 0x34, 0xa1, 0xea, 0x2f, 0x0b, 0x24, 0xab, 0x8d, 0xc8,
4099 0x51, 0x1a, 0xab, 0x82, 0x4c, 0x7e, 0x72, 0x51, 0xc7, 0xc6, 0x3a, 0x92, 4109 0xd9, 0x5b, 0x80, 0x33, 0x6e, 0xf2, 0xe0, 0xdb, 0x0b, 0x4e, 0x92, 0x51,
4100 0xb5, 0x2c, 0x14, 0xd2, 0x73, 0x2b, 0x8e, 0x8d, 0x2c, 0xca, 0xca, 0x87, 4110 0x10, 0xa5, 0x61, 0x37, 0x1c, 0xe4, 0x27, 0x97, 0x34, 0x6c, 0xa8, 0x25,
4101 0x1b, 0x48, 0x86, 0x4f, 0x8c, 0xd8, 0x43, 0x7a, 0x2c, 0x40, 0xb2, 0x56, 4111 0x59, 0x3b, 0x84, 0x4c, 0x7a, 0x6e, 0xc1, 0xb1, 0xa1, 0x79, 0x59, 0xf9,
4102 0x89, 0xbe, 0x45, 0x39, 0xb1, 0xfc, 0x16, 0xe5, 0x74, 0x2b, 0x76, 0xcf, 4112 0x70, 0x13, 0xc9, 0xf0, 0xa9, 0x21, 0x6b, 0x97, 0x16, 0x0b, 0x90, 0xac,
4103 0xb1, 0xdc, 0xfe, 0x5f, 0xe4, 0x35, 0xeb, 0xd8, 0xdd, 0xc6, 0xc9, 0x28, 4113 0x15, 0xa2, 0x6f, 0x5e, 0x4e, 0x2c, 0xbf, 0x79, 0x39, 0xdd, 0x81, 0x3d,
4104 0x1a, 0x0f, 0x5d, 0x92, 0x1d, 0xd3, 0xf7, 0x10, 0xf1, 0xf1, 0x1d, 0xff, 4114 0x33, 0x2c, 0xb7, 0xff, 0x1b, 0x79, 0x4d, 0xdb, 0x76, 0xb7, 0x61, 0x2c,
4105 0xb5, 0x91, 0xfe, 0xf7, 0x84, 0x8f, 0xe8, 0x51, 0x49, 0x37, 0xef, 0xb9, 4115 0x8a, 0x86, 0xc3, 0x57, 0x65, 0xc7, 0xf4, 0x3d, 0x42, 0x7c, 0x7c, 0xcf,
4106 0x19, 0xbb, 0x93, 0x4c, 0x2e, 0xc9, 0x38, 0x48, 0x32, 0x0e, 0x4e, 0xb1, 4116 0xbf, 0x3a, 0xd2, 0xf7, 0xbe, 0xf0, 0x11, 0x3d, 0x0a, 0xe9, 0xe6, 0x03,
4107 0xac, 0x9b, 0x48, 0xd6, 0xc0, 0xeb, 0x84, 0xcb, 0xae, 0x8b, 0x45, 0x51, 4117 0x17, 0x63, 0x77, 0x92, 0xc9, 0x55, 0x19, 0x07, 0x49, 0xc6, 0xc1, 0x71,
4108 0x7b, 0x48, 0x4b, 0x36, 0xca, 0xe1, 0x44, 0x9d, 0x00, 0x55, 0x25, 0x68, 4118 0x96, 0xf5, 0xa7, 0x6b, 0xae, 0x90, 0x7c, 0x5f, 0x27, 0x5c, 0x76, 0x43,
4109 0xad, 0xc5, 0x87, 0x2c, 0x67, 0x83, 0xe4, 0xfc, 0x9d, 0x61, 0xe2, 0x67, 4119 0x2c, 0x8a, 0x9a, 0xc3, 0x6a, 0xb2, 0xc1, 0x11, 0x4e, 0xd4, 0x0a, 0x50,
4110 0x03, 0xcd, 0xb7, 0x91, 0xe4, 0x9c, 0x24, 0xfe, 0x6f, 0x72, 0xe6, 0x6d, 4120 0x55, 0x82, 0x96, 0x1a, 0x7c, 0xc8, 0x72, 0xd6, 0x49, 0xce, 0xdf, 0x1b,
4111 0xa2, 0x79, 0x7b, 0xa9, 0xf6, 0x98, 0xf5, 0x5e, 0x24, 0x7a, 0xa2, 0x9f, 4121 0x24, 0x7e, 0xd6, 0xd3, 0x7c, 0x1b, 0x48, 0xce, 0x49, 0xe2, 0xff, 0x16,
4112 0xd1, 0x42, 0x68, 0x3c, 0x12, 0x7c, 0x8f, 0x6a, 0xec, 0xeb, 0x9d, 0x71, 4122 0x7b, 0xde, 0x46, 0x9a, 0x77, 0x0b, 0xd5, 0x1e, 0xd3, 0xde, 0x4b, 0x44,
4113 0x2a, 0x8d, 0x63, 0xda, 0x7f, 0x5c, 0x2d, 0xe9, 0x5f, 0xd6, 0x67, 0xfe, 4123 0x4f, 0xf4, 0x33, 0x5a, 0x08, 0x8d, 0x47, 0x82, 0xef, 0x53, 0x8d, 0x7d,
4114 0x16, 0xb8, 0xe7, 0x60, 0xa1, 0x8f, 0xea, 0x88, 0x5e, 0xaa, 0x95, 0x14, 4124 0xa3, 0x3d, 0x4e, 0xa1, 0x71, 0x4c, 0xfb, 0xcf, 0xab, 0x24, 0xed, 0xcb,
4115 0xca, 0x6d, 0x16, 0xbe, 0x1b, 0xd7, 0xa2, 0xf5, 0x82, 0xe3, 0x9f, 0x45, 4125 0xfa, 0xcd, 0xdf, 0x02, 0xf7, 0x1c, 0x4c, 0xf4, 0x50, 0x1d, 0xb1, 0x85,
4116 0x7e, 0x58, 0xa6, 0x3a, 0x29, 0x1c, 0x9a, 0x43, 0x50, 0x91, 0x8a, 0x0a, 4126 0x6a, 0x25, 0x99, 0x72, 0x9b, 0x89, 0x1f, 0xc4, 0xd5, 0x68, 0x9d, 0xe0,
4117 0xe1, 0xc1, 0x26, 0x45, 0x2e, 0x92, 0xbf, 0x06, 0xfb, 0x08, 0x4f, 0xbb, 4127 0xf8, 0x67, 0x92, 0x1f, 0x96, 0xa9, 0x4e, 0x0a, 0x87, 0x66, 0x10, 0x94,
4118 0xf0, 0x52, 0xde, 0x85, 0x57, 0xd2, 0xbd, 0xd8, 0x5f, 0xf2, 0x10, 0x6e, 4128 0xa5, 0xa2, 0x4c, 0x78, 0xb0, 0x51, 0x76, 0x14, 0xc9, 0x5f, 0x83, 0x3d,
4119 0xb6, 0x3c, 0xae, 0xb5, 0x7f, 0x56, 0x55, 0x89, 0xc9, 0x2b, 0xd1, 0x3d, 4129 0x84, 0xa7, 0x9d, 0x78, 0x31, 0xef, 0xc4, 0x2b, 0xe9, 0x2d, 0x38, 0x50,
4120 0xfe, 0x20, 0x6a, 0x32, 0xae, 0x1e, 0xca, 0xa7, 0xc6, 0x4d, 0x24, 0x97, 4130 0xf2, 0x10, 0x6e, 0x36, 0x3d, 0xce, 0x55, 0x13, 0xee, 0x4a, 0x4c, 0x5e,
4121 0x8d, 0x45, 0x7e, 0xde, 0x84, 0x4c, 0x3a, 0x45, 0x18, 0x28, 0x4c, 0x35, 4131 0x86, 0xae, 0x91, 0x87, 0x51, 0x9d, 0x71, 0x76, 0x53, 0x3e, 0xd5, 0x6f,
4122 0x90, 0x0b, 0xb9, 0xc6, 0x26, 0xa7, 0x9f, 0x3b, 0x4a, 0xf7, 0x46, 0x4b, 4132 0x21, 0xb9, 0x6c, 0x28, 0xf2, 0xfd, 0x46, 0x64, 0xd2, 0x29, 0xc2, 0x40,
4123 0x5f, 0xec, 0x33, 0xdf, 0xba, 0xd0, 0x5f, 0xee, 0xc7, 0xde, 0x6c, 0x1f, 4133 0x61, 0xaa, 0x81, 0x9c, 0x98, 0x68, 0x68, 0xb4, 0xfb, 0xba, 0x39, 0xba,
4124 0x61, 0xd3, 0x5e, 0x8a, 0xef, 0x15, 0x1a, 0x67, 0xe3, 0x3d, 0xd8, 0x9b, 4134 0x96, 0x2b, 0x7d, 0xb1, 0xdf, 0x7c, 0xc7, 0x5c, 0x9f, 0xb9, 0x0f, 0xfb,
4125 0x37, 0x2f, 0xc5, 0x8f, 0x69, 0x27, 0x7e, 0x0c, 0xa0, 0xba, 0x9d, 0xf7, 4135 0xb2, 0x3d, 0x84, 0x4d, 0xb7, 0x50, 0x7c, 0xaf, 0xd0, 0x38, 0x1d, 0xef,
4126 0xad, 0x7a, 0x71, 0x7b, 0x1a, 0x78, 0x37, 0xcd, 0x7d, 0x44, 0xc2, 0x14, 4136 0xc6, 0xbe, 0xbc, 0x71, 0x35, 0x7e, 0x4c, 0xda, 0xf1, 0xa3, 0x1f, 0x55,
4127 0x94, 0x0f, 0x0e, 0x1a, 0x9c, 0x43, 0x7b, 0xb1, 0x22, 0x6f, 0x23, 0x6f, 4137 0xed, 0xbc, 0x7f, 0xb5, 0x05, 0x77, 0xa5, 0x81, 0xf7, 0xd2, 0xdc, 0x4f,
4128 0xd8, 0x38, 0x6d, 0xe8, 0x94, 0xa3, 0x39, 0x57, 0x0f, 0x0a, 0x9d, 0xf2, 4138 0x24, 0x4c, 0x41, 0xf9, 0xe0, 0x90, 0xce, 0x39, 0x74, 0x0b, 0x96, 0xe6,
4129 0xb3, 0xe5, 0x1a, 0x40, 0xa4, 0x9d, 0x75, 0xf4, 0xe0, 0xc2, 0xfe, 0xd3, 4139 0x2d, 0xe4, 0x75, 0x0b, 0x67, 0x75, 0x8d, 0x72, 0x34, 0xe7, 0xea, 0x01,
4130 0x80, 0xb3, 0xff, 0x34, 0x97, 0x96, 0xf1, 0x04, 0x29, 0xe2, 0xb9, 0x6c, 4140 0xa1, 0x51, 0x7e, 0x36, 0x9d, 0xfd, 0x88, 0xb4, 0xb3, 0x8e, 0x1e, 0x9e,
4131 0x38, 0xf4, 0x2e, 0xec, 0x21, 0xd9, 0xd4, 0x12, 0x2e, 0x99, 0xf7, 0x65, 4141 0xdb, 0x87, 0xea, 0xb7, 0xf7, 0xa1, 0x66, 0xd2, 0x0e, 0x3c, 0x45, 0x8a,
4132 0x78, 0x5f, 0x4a, 0xef, 0x59, 0x21, 0x6b, 0x46, 0x51, 0xb4, 0xf4, 0xbd, 4142 0x78, 0x3e, 0x1b, 0x0e, 0xbd, 0x07, 0x6b, 0x97, 0xc3, 0x50, 0x13, 0x4e,
4133 0x8d, 0xf2, 0x26, 0x05, 0x5a, 0xe8, 0x35, 0x44, 0xa2, 0x5d, 0xbc, 0xf7, 4143 0x07, 0xef, 0xcf, 0xf0, 0xfe, 0x94, 0xd6, 0xbd, 0xd4, 0xa1, 0xea, 0x45,
4134 0x50, 0xaa, 0xe4, 0xee, 0x95, 0x0b, 0xb9, 0x5b, 0xcf, 0x7b, 0x45, 0x78, 4144 0xd1, 0xdc, 0xf3, 0x16, 0xca, 0x1b, 0x65, 0xa8, 0xa1, 0xd7, 0x10, 0x89,
4135 0x4c, 0x42, 0x6e, 0xc6, 0xb6, 0x24, 0xb2, 0xdf, 0x19, 0x9a, 0xf3, 0x07, 4145 0x76, 0xf2, 0x1e, 0x44, 0xa9, 0x92, 0xbb, 0x97, 0xcd, 0xe5, 0x6e, 0x2d,
4136 0xd9, 0x21, 0x64, 0x63, 0xb6, 0x7d, 0x4b, 0x5c, 0xef, 0x6f, 0x94, 0xf1, 4146 0xef, 0x15, 0xe1, 0x61, 0x09, 0x13, 0x53, 0x96, 0x29, 0x91, 0xfd, 0x4e,
4137 0xfb, 0x94, 0xc9, 0x41, 0x36, 0x9f, 0x22, 0x5f, 0x0b, 0xed, 0x68, 0xb7, 4147 0xd1, 0x9c, 0x3f, 0xce, 0xee, 0x42, 0x36, 0x66, 0x59, 0xb7, 0xc7, 0xb5,
4138 0xec, 0x2a, 0xa7, 0xae, 0xe0, 0xbe, 0x64, 0xb7, 0x68, 0x2d, 0xf4, 0x8a, 4148 0xbe, 0x06, 0x07, 0xfe, 0x90, 0x32, 0x39, 0xc8, 0xe6, 0x53, 0xe4, 0x6b,
4139 0x55, 0x84, 0xdd, 0x42, 0xc7, 0xb6, 0x88, 0xe6, 0xa3, 0x15, 0xec, 0x16, 4149 0xa1, 0x1d, 0xed, 0xa6, 0xe5, 0xb6, 0xeb, 0x0a, 0xee, 0x4f, 0x76, 0x89,
4140 0x29, 0x7c, 0xd6, 0x3b, 0xbd, 0x31, 0x6d, 0x23, 0x4d, 0x7c, 0x3d, 0xf1, 4150 0x96, 0xc2, 0x16, 0xb1, 0x9c, 0xb0, 0x5b, 0xe8, 0xd8, 0x66, 0xd1, 0x74,
4141 0x6b, 0x7c, 0xb1, 0x2e, 0x06, 0x70, 0x55, 0x3b, 0xfb, 0xe2, 0x83, 0x38, 4151 0xb4, 0x82, 0xdd, 0x22, 0x85, 0xcf, 0x7a, 0xa8, 0x37, 0xa7, 0x2d, 0xa4,
4142 0x96, 0x66, 0x3b, 0x1f, 0xc0, 0x6e, 0x92, 0xcf, 0xea, 0x11, 0xde, 0x07, 4152 0x89, 0xaf, 0xa7, 0xfe, 0x0e, 0x5f, 0xac, 0x8b, 0x7e, 0x5c, 0xd7, 0xce,
4143 0xd3, 0x4e, 0x0f, 0x23, 0xdc, 0xff, 0xaa, 0xd0, 0xca, 0x05, 0xb4, 0x18, 4153 0xbe, 0xf8, 0x30, 0x8e, 0xa5, 0xd9, 0xce, 0xfb, 0xb1, 0x87, 0xe4, 0xb3,
4144 0xb5, 0x32, 0xc7, 0x57, 0x6d, 0xb0, 0x59, 0xae, 0xd0, 0x9f, 0xc8, 0x83, 4154 0x62, 0x88, 0xf7, 0xc3, 0xd4, 0xb3, 0x83, 0x08, 0xf7, 0xbd, 0x2a, 0xd4,
4145 0xe2, 0x69, 0x85, 0x87, 0x6b, 0xf2, 0x2b, 0xc8, 0x56, 0x2d, 0xcf, 0xc5, 4155 0x72, 0x01, 0xcd, 0x7a, 0x8d, 0x83, 0xe3, 0xab, 0x3a, 0xd0, 0xe4, 0xa8,
4146 0x78, 0xcb, 0x40, 0x0d, 0x36, 0x8a, 0x0f, 0x66, 0x43, 0xf0, 0x1e, 0x4a, 4156 0xd0, 0x9f, 0xc8, 0x83, 0xe2, 0x69, 0x85, 0x87, 0x95, 0xf9, 0xa5, 0x64,
4147 0x2e, 0xf5, 0xa3, 0x53, 0xbc, 0xeb, 0xd4, 0x8b, 0x5d, 0xe2, 0x7c, 0xbe, 4157 0xab, 0xa6, 0xe7, 0x52, 0xbc, 0xb9, 0xbf, 0x1a, 0x1b, 0xc4, 0x07, 0xd3,
4148 0x47, 0xbc, 0x9f, 0xeb, 0x46, 0x64, 0xec, 0x1e, 0xf1, 0x4e, 0x8e, 0xe9, 4158 0x21, 0x78, 0x0f, 0x27, 0x17, 0xfa, 0xd1, 0x21, 0xde, 0xb3, 0xeb, 0xc5,
4149 0xec, 0x13, 0x67, 0x67, 0xb9, 0x3f, 0x6a, 0x63, 0xb7, 0xc1, 0xbd, 0xd1, 4159 0x4e, 0xf1, 0x4e, 0xbe, 0x5b, 0x5c, 0x9e, 0xe8, 0x42, 0x64, 0xf8, 0x3e,
4150 0xa5, 0xd5, 0xf0, 0xdb, 0x38, 0x66, 0xb0, 0x3e, 0xb9, 0x4f, 0x58, 0xe9, 4160 0xf1, 0xf6, 0x04, 0xd3, 0xd9, 0x23, 0xce, 0x4f, 0x73, 0x9f, 0xd4, 0xc2,
4151 0x2f, 0x6d, 0x8c, 0x8f, 0xda, 0x2e, 0x9d, 0x7b, 0xc4, 0x41, 0x87, 0xdf, 4161 0x1e, 0x9d, 0xfb, 0xa2, 0x8b, 0xab, 0xe0, 0xb7, 0x70, 0x4c, 0x67, 0x7d,
4152 0x19, 0xc2, 0xd1, 0xb3, 0xb9, 0x5e, 0x71, 0x3c, 0x5f, 0xe1, 0x75, 0x3a, 4162 0x72, 0x9f, 0xb0, 0xd2, 0x5f, 0xda, 0x10, 0xcf, 0x59, 0x4e, 0x8d, 0x7b,
4153 0xcf, 0xf6, 0xab, 0x90, 0x8e, 0xbf, 0x98, 0xa7, 0x2d, 0xa8, 0xed, 0x41, 4163 0xc5, 0x41, 0x9b, 0xdf, 0x29, 0xc2, 0xd1, 0xd3, 0x13, 0x5b, 0xc4, 0xf1,
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4522 0xda, 0x41, 0x71, 0xf7, 0x33, 0x5e, 0x6b, 0x47, 0xf8, 0x7c, 0xd7, 0x00, 4532 0xf3, 0xd9, 0x66, 0xe1, 0x3c, 0xba, 0x45, 0x78, 0x0b, 0x3d, 0xc2, 0x7f,
4523 0xfc, 0x5f, 0xb2, 0x27, 0x76, 0xe6, 0xb3, 0x3d, 0xb1, 0xc4, 0x63, 0x42, 4533 0xcc, 0xc4, 0xfd, 0xf1, 0x2e, 0x9c, 0x1b, 0xe6, 0xb3, 0x6c, 0xf7, 0x89,
4524 0x2b, 0xcf, 0x11, 0xbf, 0xd5, 0xf2, 0xe7, 0xf6, 0xc3, 0x16, 0xf6, 0xc2, 4534 0x9a, 0xb9, 0xbd, 0x39, 0x6f, 0xa1, 0xd1, 0x5f, 0x48, 0x73, 0x7f, 0xf7,
4525 0xba, 0x84, 0xaf, 0xc0, 0xf5, 0x79, 0xbc, 0xe3, 0xf5, 0x91, 0x4e, 0xe1, 4535 0xe3, 0x35, 0xe9, 0xa1, 0x45, 0xfe, 0xa7, 0xc6, 0x02, 0xfe, 0x27, 0xc7,
4526 0x3d, 0x36, 0x46, 0xf9, 0x71, 0x23, 0xf1, 0xcc, 0xe7, 0xae, 0xba, 0x85, 4536 0xd4, 0xfe, 0x7d, 0xc2, 0xb2, 0x76, 0xc6, 0xfe, 0x03, 0xeb, 0xd0, 0x6a,
4527 0xbf, 0xb0, 0x45, 0xf8, 0x88, 0xcf, 0x1a, 0xe2, 0x13, 0xc7, 0x3c, 0xc2, 4537 0x8e, 0x55, 0xf0, 0xc1, 0x6e, 0x92, 0xc7, 0x36, 0xca, 0x2d, 0x93, 0x7a,
4528 0x4b, 0x3c, 0x7a, 0x88, 0x47, 0xef, 0x02, 0x8f, 0x9e, 0x42, 0xd0, 0x9f, 4538 0xf3, 0x1c, 0x16, 0x51, 0x53, 0xfc, 0xee, 0x1b, 0xfd, 0x77, 0x73, 0x6e,
4529 0x4e, 0x37, 0xf8, 0x1f, 0x9e, 0x54, 0xfd, 0x7b, 0x27, 0x6d, 0xfb, 0x3d, 4539 0xe3, 0x7d, 0x4d, 0x67, 0x3b, 0x28, 0xee, 0x7e, 0xc6, 0x6b, 0xcd, 0x10,
4530 0xe3, 0x67, 0x0e, 0x5f, 0xaf, 0x1a, 0x5f, 0xe4, 0xeb, 0x3a, 0xe2, 0xab, 4540 0x9f, 0x51, 0xeb, 0x87, 0xff, 0x4b, 0xf6, 0xf5, 0xce, 0x7d, 0xb6, 0xaf,
4531 0xb2, 0x8f, 0x49, 0x3a, 0x4c, 0xb1, 0x0e, 0xf9, 0x0c, 0xc4, 0x22, 0x5f, 4541 0x97, 0x78, 0x52, 0xa8, 0xe5, 0x19, 0xe2, 0xb7, 0xca, 0xf1, 0xb9, 0x3d,
4532 0x07, 0xd2, 0xbc, 0x8f, 0xc1, 0x7b, 0x7e, 0x83, 0x62, 0x35, 0xf1, 0x55, 4542 0xbd, 0xb9, 0xfd, 0xbc, 0x4e, 0xe1, 0x2b, 0x70, 0x7d, 0x1e, 0x30, 0x5e,
4533 0x26, 0xbe, 0xae, 0xf9, 0x12, 0xbe, 0x3e, 0xbc, 0x8c, 0xaf, 0x57, 0xff, 4543 0x1f, 0xea, 0x10, 0xde, 0x63, 0xc3, 0x94, 0x1f, 0x37, 0x10, 0xcf, 0x7c,
4534 0x51, 0xbe, 0x3c, 0x62, 0xd5, 0x18, 0xc7, 0xa1, 0xfb, 0x3b, 0x94, 0x31, 4544 0x76, 0xac, 0x4b, 0xf8, 0x0b, 0x9b, 0x85, 0x8f, 0xf8, 0xac, 0x26, 0x3e,
4535 0x9b, 0xb0, 0xa3, 0x8c, 0xc7, 0x67, 0x80, 0x62, 0x76, 0x08, 0x0a, 0xc5, 4545 0x71, 0xcc, 0x23, 0xbc, 0xc4, 0xa3, 0x87, 0x78, 0xf4, 0xce, 0xf1, 0xe8,
4536 0x9b, 0x93, 0xf1, 0x48, 0xe8, 0x15, 0xaa, 0x27, 0x67, 0x4b, 0x5e, 0xb1, 4546 0x29, 0x04, 0xfd, 0xe9, 0x74, 0xbd, 0xff, 0xd1, 0x31, 0xc5, 0xbf, 0x6f,
4537 0xd2, 0xd9, 0xcf, 0xc4, 0x6a, 0x85, 0x68, 0x9a, 0x73, 0x7e, 0x9f, 0x05, 4547 0xcc, 0xb2, 0xde, 0xd7, 0x15, 0x3f, 0xf3, 0xf5, 0xaa, 0xfe, 0x45, 0xbe,
4538 0xa3, 0x4e, 0x67, 0x5d, 0xea, 0xa7, 0xb7, 0x22, 0x52, 0x8e, 0xc8, 0xdd, 4548 0x6e, 0x20, 0xbe, 0x2a, 0x7b, 0xb1, 0xa4, 0xc3, 0x14, 0xeb, 0x90, 0xcf,
4539 0x22, 0x51, 0xe0, 0xfd, 0xcb, 0x5e, 0x71, 0x8d, 0xb3, 0x77, 0xd9, 0x25, 4549 0x71, 0xcc, 0xf3, 0x75, 0x30, 0xcd, 0xfb, 0x95, 0xbc, 0x6f, 0x39, 0x20,
4540 0xae, 0x2e, 0x74, 0x8a, 0x56, 0xb2, 0x8b, 0x96, 0x63, 0x7c, 0x96, 0x6a, 4550 0x56, 0x10, 0x5f, 0x65, 0xe2, 0x6b, 0xe5, 0x97, 0xf0, 0xf5, 0xe1, 0x35,
4541 0x8b, 0x68, 0x59, 0x90, 0xc7, 0x2a, 0x92, 0xc7, 0xc8, 0xe7, 0xe4, 0xb1, 4551 0x7c, 0xbd, 0xfa, 0xf7, 0xf2, 0xe5, 0x11, 0xcb, 0x87, 0x39, 0x0e, 0xdd,
4542 0xc4, 0xcf, 0xf2, 0xf8, 0x91, 0x71, 0xe1, 0xb2, 0x1e, 0x1a, 0xd7, 0x55, 4552 0x66, 0xc8, 0xc3, 0x16, 0x61, 0x47, 0x07, 0xbe, 0x3f, 0x05, 0x14, 0xb3,
4543 0x94, 0x0d, 0xa9, 0x76, 0xaa, 0x5b, 0xa8, 0x9d, 0xde, 0x8e, 0xf1, 0x19, 4553 0xbb, 0x20, 0x53, 0xbc, 0x39, 0x1d, 0x8f, 0x84, 0x5e, 0xa1, 0x7a, 0x72,
4544 0x19, 0xcb, 0xae, 0xd5, 0x11, 0x72, 0x99, 0x5a, 0xdf, 0x49, 0xa1, 0xa7, 4554 0xba, 0xe4, 0x15, 0xcb, 0xec, 0x3d, 0x59, 0xac, 0x90, 0x89, 0xa6, 0x19,
4545 0xee, 0x11, 0xc9, 0xcd, 0x3e, 0xaa, 0x7f, 0x76, 0xc4, 0x22, 0xc9, 0x55, 4555 0xfb, 0x5d, 0x33, 0xe8, 0xb5, 0x1a, 0xeb, 0x52, 0x3b, 0xbb, 0x15, 0x91,
4546 0x22, 0x92, 0x70, 0x09, 0xce, 0x2b, 0x86, 0x52, 0x5d, 0xb4, 0xb0, 0x97, 4556 0x72, 0xc4, 0xd1, 0x25, 0x12, 0x05, 0xde, 0x83, 0xdd, 0x22, 0x56, 0xda,
4547 0xe2, 0xdb, 0x4b, 0xa3, 0x12, 0x61, 0x07, 0xfe, 0xcd, 0x96, 0x0b, 0xd7, 4557 0xfb, 0xaf, 0x9d, 0xe2, 0xfa, 0x42, 0x87, 0x68, 0x21, 0xbb, 0x68, 0x3e,
4548 0xab, 0x3e, 0x1c, 0x21, 0xdc, 0xf1, 0x68, 0xb6, 0x1f, 0x47, 0xf2, 0xdb, 4558 0xc6, 0xe7, 0xc1, 0x36, 0x8b, 0xe6, 0x39, 0x79, 0x2c, 0x27, 0x79, 0x0c,
4549 0xf0, 0x68, 0xfe, 0xd7, 0x7e, 0x9f, 0xa2, 0x78, 0xcd, 0x9e, 0x6b, 0x2b, 4559 0x7d, 0x4e, 0x1e, 0x1b, 0x6c, 0x79, 0xfc, 0x4c, 0xbf, 0x78, 0x4d, 0x0f,
4550 0xfb, 0xf8, 0xd1, 0xc4, 0x55, 0x11, 0x96, 0xcd, 0x4f, 0x5b, 0x94, 0x08, 4560 0x8d, 0xeb, 0x2a, 0xca, 0x86, 0x54, 0x3b, 0xd5, 0xce, 0xd5, 0x4e, 0x6f,
4551 0xd7, 0xba, 0x89, 0xeb, 0x7e, 0xae, 0xb3, 0x2f, 0xa6, 0xdb, 0x4f, 0x39, 4561 0xc5, 0xf8, 0x9c, 0x8f, 0x69, 0xd5, 0x68, 0x08, 0x39, 0x0d, 0xb5, 0xe7,
4552 0x58, 0xe4, 0xed, 0xb6, 0x63, 0xce, 0xf9, 0xa2, 0x5f, 0xae, 0xde, 0xed, 4562 0xb4, 0xd0, 0x52, 0xf7, 0x89, 0xe4, 0x26, 0x1f, 0xd5, 0x3f, 0x3b, 0x62,
4553 0xfc, 0x7e, 0x32, 0xb9, 0xf6, 0x76, 0x9d, 0xfd, 0xe1, 0xa7, 0x6b, 0x36, 4563 0x91, 0xe4, 0x72, 0x11, 0x49, 0x38, 0x05, 0xe7, 0x15, 0x5d, 0xae, 0x2a,
4554 0x38, 0xf9, 0xd5, 0x5c, 0x57, 0xf9, 0x6d, 0x49, 0x62, 0x5d, 0xa5, 0x57, 4564 0x9a, 0xd8, 0x47, 0xf1, 0xed, 0xc5, 0x9c, 0x44, 0xd8, 0x81, 0xdf, 0x3f,
4555 0x13, 0x5f, 0x17, 0x75, 0xae, 0xc9, 0x75, 0x95, 0x7d, 0xe2, 0x9e, 0x75, 4565 0x73, 0xe2, 0x46, 0x82, 0x12, 0x4f, 0x10, 0xee, 0x78, 0x3c, 0xdb, 0x87,
4556 0xcd, 0xce, 0xb5, 0x6b, 0x5d, 0xc5, 0xa7, 0x3a, 0xd7, 0xe9, 0xce, 0xb5, 4566 0x27, 0xf2, 0xbd, 0x78, 0x3c, 0xff, 0x77, 0xde, 0xb5, 0x91, 0xbd, 0x46,
4557 0x77, 0x5d, 0x25, 0x2f, 0x77, 0xaf, 0x5b, 0x71, 0xe9, 0x37, 0x29, 0xfc, 4567 0x63, 0xa2, 0x72, 0x16, 0xe1, 0xe3, 0xc4, 0x75, 0x11, 0x96, 0xcd, 0x89,
4558 0xf7, 0x7f, 0x00, 0x2f, 0xc1, 0x67, 0x8a, 0x54, 0x3a, 0x00, 0x00, 0x00 }; 4568 0x16, 0x39, 0xc2, 0xb5, 0xae, 0xf3, 0x77, 0xdf, 0xd5, 0xd8, 0x17, 0x7b,
4569 0x56, 0xbd, 0x64, 0x63, 0x91, 0x93, 0x6d, 0xc7, 0xec, 0x33, 0x52, 0xe5,
4570 0x95, 0x7b, 0xec, 0x77, 0x41, 0x7d, 0xab, 0xef, 0xd2, 0xd8, 0x1f, 0x4e,
4571 0xc4, 0xd7, 0xdb, 0xf9, 0xb5, 0x71, 0x6d, 0xe5, 0x3d, 0x99, 0xe0, 0xda,
4572 0x4a, 0xaf, 0x26, 0xb0, 0x36, 0x6a, 0x7f, 0x86, 0xd6, 0x56, 0xf6, 0xba,
4573 0xf5, 0xb5, 0x4d, 0xf6, 0x67, 0x74, 0x6d, 0xc5, 0xa7, 0xb4, 0xb5, 0x9a,
4574 0xfd, 0x19, 0x5f, 0x5b, 0xc9, 0xcb, 0x2d, 0x6b, 0x97, 0x5e, 0x7d, 0xbf,
4575 0x86, 0xff, 0xfe, 0x17, 0x9f, 0xed, 0x4e, 0xb2, 0x20, 0x3b, 0x00, 0x00,
4576 0x00 };
4559 4577
4560static const u32 bnx2_TXP_b09FwData[(0x0/4) + 1] = { 0x0 }; 4578static const u32 bnx2_TXP_b09FwData[(0x0/4) + 1] = { 0x0 };
4561static const u32 bnx2_TXP_b09FwRodata[(0x30/4) + 1] = { 4579static const u32 bnx2_TXP_b09FwRodata[(0x30/4) + 1] = {
@@ -4564,15 +4582,15 @@ static const u32 bnx2_TXP_b09FwRodata[(0x30/4) + 1] = {
4564 0x00000000 }; 4582 0x00000000 };
4565 4583
4566static struct fw_info bnx2_txp_fw_09 = { 4584static struct fw_info bnx2_txp_fw_09 = {
4567 /* Firmware version: 4.0.5 */ 4585 /* Firmware version: 4.4.23 */
4568 .ver_major = 0x4, 4586 .ver_major = 0x4,
4569 .ver_minor = 0x0, 4587 .ver_minor = 0x4,
4570 .ver_fix = 0x5, 4588 .ver_fix = 0x17,
4571 4589
4572 .start_addr = 0x08000094, 4590 .start_addr = 0x08000094,
4573 4591
4574 .text_addr = 0x08000000, 4592 .text_addr = 0x08000000,
4575 .text_len = 0x3a50, 4593 .text_len = 0x3b1c,
4576 .text_index = 0x0, 4594 .text_index = 0x0,
4577 .gz_text = bnx2_TXP_b09FwText, 4595 .gz_text = bnx2_TXP_b09FwText,
4578 .gz_text_len = sizeof(bnx2_TXP_b09FwText), 4596 .gz_text_len = sizeof(bnx2_TXP_b09FwText),
@@ -4582,15 +4600,15 @@ static struct fw_info bnx2_txp_fw_09 = {
4582 .data_index = 0x0, 4600 .data_index = 0x0,
4583 .data = bnx2_TXP_b09FwData, 4601 .data = bnx2_TXP_b09FwData,
4584 4602
4585 .sbss_addr = 0x08003aa0, 4603 .sbss_addr = 0x08003b80,
4586 .sbss_len = 0x6c, 4604 .sbss_len = 0x6c,
4587 .sbss_index = 0x0, 4605 .sbss_index = 0x0,
4588 4606
4589 .bss_addr = 0x08003b0c, 4607 .bss_addr = 0x08003bec,
4590 .bss_len = 0x24c, 4608 .bss_len = 0x24c,
4591 .bss_index = 0x0, 4609 .bss_index = 0x0,
4592 4610
4593 .rodata_addr = 0x08003a50, 4611 .rodata_addr = 0x08003b1c,
4594 .rodata_len = 0x30, 4612 .rodata_len = 0x30,
4595 .rodata_index = 0x0, 4613 .rodata_index = 0x0,
4596 .rodata = bnx2_TXP_b09FwRodata, 4614 .rodata = bnx2_TXP_b09FwRodata,
diff --git a/drivers/net/bnx2x.c b/drivers/net/bnx2x.c
deleted file mode 100644
index 70cba64732ca..000000000000
--- a/drivers/net/bnx2x.c
+++ /dev/null
@@ -1,9988 +0,0 @@
1/* bnx2x.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2008 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18/* define this to make the driver freeze on error
19 * to allow getting debug info
20 * (you will need to reboot afterwards)
21 */
22/*#define BNX2X_STOP_ON_ERROR*/
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/kernel.h>
27#include <linux/device.h> /* for dev_info() */
28#include <linux/timer.h>
29#include <linux/errno.h>
30#include <linux/ioport.h>
31#include <linux/slab.h>
32#include <linux/vmalloc.h>
33#include <linux/interrupt.h>
34#include <linux/pci.h>
35#include <linux/init.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/skbuff.h>
39#include <linux/dma-mapping.h>
40#include <linux/bitops.h>
41#include <linux/irq.h>
42#include <linux/delay.h>
43#include <asm/byteorder.h>
44#include <linux/time.h>
45#include <linux/ethtool.h>
46#include <linux/mii.h>
47#ifdef NETIF_F_HW_VLAN_TX
48 #include <linux/if_vlan.h>
49 #define BCM_VLAN 1
50#endif
51#include <net/ip.h>
52#include <net/tcp.h>
53#include <net/checksum.h>
54#include <linux/workqueue.h>
55#include <linux/crc32.h>
56#include <linux/prefetch.h>
57#include <linux/zlib.h>
58#include <linux/version.h>
59#include <linux/io.h>
60
61#include "bnx2x_reg.h"
62#include "bnx2x_fw_defs.h"
63#include "bnx2x_hsi.h"
64#include "bnx2x.h"
65#include "bnx2x_init.h"
66
67#define DRV_MODULE_VERSION "1.42.4"
68#define DRV_MODULE_RELDATE "2008/4/9"
69#define BNX2X_BC_VER 0x040200
70
71/* Time in jiffies before concluding the transmitter is hung. */
72#define TX_TIMEOUT (5*HZ)
73
74static char version[] __devinitdata =
75 "Broadcom NetXtreme II 5771X 10Gigabit Ethernet Driver "
76 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
77
78MODULE_AUTHOR("Eliezer Tamir");
79MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver");
80MODULE_LICENSE("GPL");
81MODULE_VERSION(DRV_MODULE_VERSION);
82
83static int use_inta;
84static int poll;
85static int onefunc;
86static int nomcp;
87static int debug;
88static int use_multi;
89
90module_param(use_inta, int, 0);
91module_param(poll, int, 0);
92module_param(onefunc, int, 0);
93module_param(debug, int, 0);
94MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
95MODULE_PARM_DESC(poll, "use polling (for debug)");
96MODULE_PARM_DESC(onefunc, "enable only first function");
97MODULE_PARM_DESC(nomcp, "ignore management CPU (Implies onefunc)");
98MODULE_PARM_DESC(debug, "default debug msglevel");
99
100#ifdef BNX2X_MULTI
101module_param(use_multi, int, 0);
102MODULE_PARM_DESC(use_multi, "use per-CPU queues");
103#endif
104
105enum bnx2x_board_type {
106 BCM57710 = 0,
107};
108
109/* indexed by board_t, above */
110static struct {
111 char *name;
112} board_info[] __devinitdata = {
113 { "Broadcom NetXtreme II BCM57710 XGb" }
114};
115
116static const struct pci_device_id bnx2x_pci_tbl[] = {
117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
119 { 0 }
120};
121
122MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
123
124/****************************************************************************
125* General service functions
126****************************************************************************/
127
128/* used only at init
129 * locking is done by mcp
130 */
131static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
132{
133 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
134 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
135 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
136 PCICFG_VENDOR_ID_OFFSET);
137}
138
139#ifdef BNX2X_IND_RD
140static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
141{
142 u32 val;
143
144 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
145 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
146 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
147 PCICFG_VENDOR_ID_OFFSET);
148
149 return val;
150}
151#endif
152
153static const u32 dmae_reg_go_c[] = {
154 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
155 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
156 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
157 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
158};
159
160/* copy command into DMAE command memory and set DMAE command go */
161static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
162 int idx)
163{
164 u32 cmd_offset;
165 int i;
166
167 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
168 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
169 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
170
171/* DP(NETIF_MSG_DMAE, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
172 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); */
173 }
174 REG_WR(bp, dmae_reg_go_c[idx], 1);
175}
176
177static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
178 u32 dst_addr, u32 len32)
179{
180 struct dmae_command *dmae = &bp->dmae;
181 int port = bp->port;
182 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
183 int timeout = 200;
184
185 memset(dmae, 0, sizeof(struct dmae_command));
186
187 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
188 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
189 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
190#ifdef __BIG_ENDIAN
191 DMAE_CMD_ENDIANITY_B_DW_SWAP |
192#else
193 DMAE_CMD_ENDIANITY_DW_SWAP |
194#endif
195 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
196 dmae->src_addr_lo = U64_LO(dma_addr);
197 dmae->src_addr_hi = U64_HI(dma_addr);
198 dmae->dst_addr_lo = dst_addr >> 2;
199 dmae->dst_addr_hi = 0;
200 dmae->len = len32;
201 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
202 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
203 dmae->comp_val = BNX2X_WB_COMP_VAL;
204
205/*
206 DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
207 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
208 "dst_addr [%x:%08x (%08x)]\n"
209 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
210 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
211 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
212 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
213*/
214/*
215 DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
216 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
217 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
218*/
219
220 *wb_comp = 0;
221
222 bnx2x_post_dmae(bp, dmae, port * 8);
223
224 udelay(5);
225 /* adjust timeout for emulation/FPGA */
226 if (CHIP_REV_IS_SLOW(bp))
227 timeout *= 100;
228 while (*wb_comp != BNX2X_WB_COMP_VAL) {
229/* DP(NETIF_MSG_DMAE, "wb_comp 0x%08x\n", *wb_comp); */
230 udelay(5);
231 if (!timeout) {
232 BNX2X_ERR("dmae timeout!\n");
233 break;
234 }
235 timeout--;
236 }
237}
238
239#ifdef BNX2X_DMAE_RD
240static void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
241{
242 struct dmae_command *dmae = &bp->dmae;
243 int port = bp->port;
244 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
245 int timeout = 200;
246
247 memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
248 memset(dmae, 0, sizeof(struct dmae_command));
249
250 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
251 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
252 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
253#ifdef __BIG_ENDIAN
254 DMAE_CMD_ENDIANITY_B_DW_SWAP |
255#else
256 DMAE_CMD_ENDIANITY_DW_SWAP |
257#endif
258 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
259 dmae->src_addr_lo = src_addr >> 2;
260 dmae->src_addr_hi = 0;
261 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
262 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
263 dmae->len = len32;
264 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
265 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
266 dmae->comp_val = BNX2X_WB_COMP_VAL;
267
268/*
269 DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
270 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
271 "dst_addr [%x:%08x (%08x)]\n"
272 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
273 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
274 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
275 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
276*/
277
278 *wb_comp = 0;
279
280 bnx2x_post_dmae(bp, dmae, port * 8);
281
282 udelay(5);
283 while (*wb_comp != BNX2X_WB_COMP_VAL) {
284 udelay(5);
285 if (!timeout) {
286 BNX2X_ERR("dmae timeout!\n");
287 break;
288 }
289 timeout--;
290 }
291/*
292 DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
293 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
294 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
295*/
296}
297#endif
298
299static int bnx2x_mc_assert(struct bnx2x *bp)
300{
301 int i, j, rc = 0;
302 char last_idx;
303 const char storm[] = {"XTCU"};
304 const u32 intmem_base[] = {
305 BAR_XSTRORM_INTMEM,
306 BAR_TSTRORM_INTMEM,
307 BAR_CSTRORM_INTMEM,
308 BAR_USTRORM_INTMEM
309 };
310
311 /* Go through all instances of all SEMIs */
312 for (i = 0; i < 4; i++) {
313 last_idx = REG_RD8(bp, XSTORM_ASSERT_LIST_INDEX_OFFSET +
314 intmem_base[i]);
315 if (last_idx)
316 BNX2X_LOG("DATA %cSTORM_ASSERT_LIST_INDEX 0x%x\n",
317 storm[i], last_idx);
318
319 /* print the asserts */
320 for (j = 0; j < STROM_ASSERT_ARRAY_SIZE; j++) {
321 u32 row0, row1, row2, row3;
322
323 row0 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) +
324 intmem_base[i]);
325 row1 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 4 +
326 intmem_base[i]);
327 row2 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 8 +
328 intmem_base[i]);
329 row3 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 12 +
330 intmem_base[i]);
331
332 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
333 BNX2X_LOG("DATA %cSTORM_ASSERT_INDEX 0x%x ="
334 " 0x%08x 0x%08x 0x%08x 0x%08x\n",
335 storm[i], j, row3, row2, row1, row0);
336 rc++;
337 } else {
338 break;
339 }
340 }
341 }
342 return rc;
343}
344
345static void bnx2x_fw_dump(struct bnx2x *bp)
346{
347 u32 mark, offset;
348 u32 data[9];
349 int word;
350
351 mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
352 mark = ((mark + 0x3) & ~0x3);
353 printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
354
355 for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
356 for (word = 0; word < 8; word++)
357 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
358 offset + 4*word));
359 data[8] = 0x0;
360 printk(KERN_CONT "%s", (char *)data);
361 }
362 for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
363 for (word = 0; word < 8; word++)
364 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
365 offset + 4*word));
366 data[8] = 0x0;
367 printk(KERN_CONT "%s", (char *)data);
368 }
369 printk("\n" KERN_ERR PFX "end of fw dump\n");
370}
371
372static void bnx2x_panic_dump(struct bnx2x *bp)
373{
374 int i;
375 u16 j, start, end;
376
377 BNX2X_ERR("begin crash dump -----------------\n");
378
379 for_each_queue(bp, i) {
380 struct bnx2x_fastpath *fp = &bp->fp[i];
381 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
382
383 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x) tx_pkt_cons(%x)"
384 " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)"
385 " *rx_cons_sb(%x) rx_comp_prod(%x)"
386 " rx_comp_cons(%x) fp_c_idx(%x) fp_u_idx(%x)"
387 " bd data(%x,%x)\n",
388 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
389 fp->tx_bd_cons, *fp->tx_cons_sb, *fp->rx_cons_sb,
390 fp->rx_comp_prod, fp->rx_comp_cons, fp->fp_c_idx,
391 fp->fp_u_idx, hw_prods->packets_prod,
392 hw_prods->bds_prod);
393
394 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
395 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
396 for (j = start; j < end; j++) {
397 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
398
399 BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
400 sw_bd->skb, sw_bd->first_bd);
401 }
402
403 start = TX_BD(fp->tx_bd_cons - 10);
404 end = TX_BD(fp->tx_bd_cons + 254);
405 for (j = start; j < end; j++) {
406 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
407
408 BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
409 j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
410 }
411
412 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
413 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
414 for (j = start; j < end; j++) {
415 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
416 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
417
418 BNX2X_ERR("rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
419 j, rx_bd[0], rx_bd[1], sw_bd->skb);
420 }
421
422 start = RCQ_BD(fp->rx_comp_cons - 10);
423 end = RCQ_BD(fp->rx_comp_cons + 503);
424 for (j = start; j < end; j++) {
425 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
426
427 BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
428 j, cqe[0], cqe[1], cqe[2], cqe[3]);
429 }
430 }
431
432 BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_x_idx(%u)"
433 " def_t_idx(%u) def_att_idx(%u) attn_state(%u)"
434 " spq_prod_idx(%u)\n",
435 bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
436 bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
437
438
439 bnx2x_mc_assert(bp);
440 BNX2X_ERR("end crash dump -----------------\n");
441
442 bp->stats_state = STATS_STATE_DISABLE;
443 DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");
444}
445
446static void bnx2x_int_enable(struct bnx2x *bp)
447{
448 int port = bp->port;
449 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
450 u32 val = REG_RD(bp, addr);
451 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
452
453 if (msix) {
454 val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
455 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
456 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
457 } else {
458 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
459 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
460 HC_CONFIG_0_REG_INT_LINE_EN_0 |
461 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
462
463 /* Errata A0.158 workaround */
464 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
465 val, port, addr, msix);
466
467 REG_WR(bp, addr, val);
468
469 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
470 }
471
472 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
473 val, port, addr, msix);
474
475 REG_WR(bp, addr, val);
476}
477
478static void bnx2x_int_disable(struct bnx2x *bp)
479{
480 int port = bp->port;
481 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
482 u32 val = REG_RD(bp, addr);
483
484 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
485 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
486 HC_CONFIG_0_REG_INT_LINE_EN_0 |
487 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
488
489 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
490 val, port, addr);
491
492 REG_WR(bp, addr, val);
493 if (REG_RD(bp, addr) != val)
494 BNX2X_ERR("BUG! proper val not read from IGU!\n");
495}
496
497static void bnx2x_int_disable_sync(struct bnx2x *bp)
498{
499
500 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
501 int i;
502
503 atomic_inc(&bp->intr_sem);
504 /* prevent the HW from sending interrupts */
505 bnx2x_int_disable(bp);
506
507 /* make sure all ISRs are done */
508 if (msix) {
509 for_each_queue(bp, i)
510 synchronize_irq(bp->msix_table[i].vector);
511
512 /* one more for the Slow Path IRQ */
513 synchronize_irq(bp->msix_table[i].vector);
514 } else
515 synchronize_irq(bp->pdev->irq);
516
517 /* make sure sp_task is not running */
518 cancel_work_sync(&bp->sp_task);
519
520}
521
522/* fast path code */
523
524/*
525 * general service functions
526 */
527
528static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 id,
529 u8 storm, u16 index, u8 op, u8 update)
530{
531 u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_PORT_BASE * bp->port) * 8;
532 struct igu_ack_register igu_ack;
533
534 igu_ack.status_block_index = index;
535 igu_ack.sb_id_and_flags =
536 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
537 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
538 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
539 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
540
541/* DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
542 (*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr); */
543 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack));
544}
545
546static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
547{
548 struct host_status_block *fpsb = fp->status_blk;
549 u16 rc = 0;
550
551 barrier(); /* status block is written to by the chip */
552 if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
553 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
554 rc |= 1;
555 }
556 if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
557 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
558 rc |= 2;
559 }
560 return rc;
561}
562
563static inline int bnx2x_has_work(struct bnx2x_fastpath *fp)
564{
565 u16 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
566
567 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
568 rx_cons_sb++;
569
570 if ((rx_cons_sb != fp->rx_comp_cons) ||
571 (le16_to_cpu(*fp->tx_cons_sb) != fp->tx_pkt_cons))
572 return 1;
573
574 return 0;
575}
576
577static u16 bnx2x_ack_int(struct bnx2x *bp)
578{
579 u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_PORT_BASE * bp->port) * 8;
580 u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr);
581
582/* DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
583 result, BAR_IGU_INTMEM + igu_addr); */
584
585#ifdef IGU_DEBUG
586#warning IGU_DEBUG active
587 if (result == 0) {
588 BNX2X_ERR("read %x from IGU\n", result);
589 REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0);
590 }
591#endif
592 return result;
593}
594
595
596/*
597 * fast path service functions
598 */
599
600/* free skb in the packet ring at pos idx
601 * return idx of last bd freed
602 */
603static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
604 u16 idx)
605{
606 struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
607 struct eth_tx_bd *tx_bd;
608 struct sk_buff *skb = tx_buf->skb;
609 u16 bd_idx = tx_buf->first_bd;
610 int nbd;
611
612 DP(BNX2X_MSG_OFF, "pkt_idx %d buff @(%p)->skb %p\n",
613 idx, tx_buf, skb);
614
615 /* unmap first bd */
616 DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
617 tx_bd = &fp->tx_desc_ring[bd_idx];
618 pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
619 BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
620
621 nbd = le16_to_cpu(tx_bd->nbd) - 1;
622#ifdef BNX2X_STOP_ON_ERROR
623 if (nbd > (MAX_SKB_FRAGS + 2)) {
624 BNX2X_ERR("bad nbd!\n");
625 bnx2x_panic();
626 }
627#endif
628
629 /* Skip a parse bd and the TSO split header bd
630 since they have no mapping */
631 if (nbd)
632 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
633
634 if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
635 ETH_TX_BD_FLAGS_TCP_CSUM |
636 ETH_TX_BD_FLAGS_SW_LSO)) {
637 if (--nbd)
638 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
639 tx_bd = &fp->tx_desc_ring[bd_idx];
640 /* is this a TSO split header bd? */
641 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
642 if (--nbd)
643 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
644 }
645 }
646
647 /* now free frags */
648 while (nbd > 0) {
649
650 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
651 tx_bd = &fp->tx_desc_ring[bd_idx];
652 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
653 BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
654 if (--nbd)
655 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
656 }
657
658 /* release skb */
659 BUG_TRAP(skb);
660 dev_kfree_skb(skb);
661 tx_buf->first_bd = 0;
662 tx_buf->skb = NULL;
663
664 return bd_idx;
665}
666
667static inline u32 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
668{
669 u16 used;
670 u32 prod;
671 u32 cons;
672
673 /* Tell compiler that prod and cons can change */
674 barrier();
675 prod = fp->tx_bd_prod;
676 cons = fp->tx_bd_cons;
677
678 used = (NUM_TX_BD - NUM_TX_RINGS + prod - cons +
679 (cons / TX_DESC_CNT) - (prod / TX_DESC_CNT));
680
681 if (prod >= cons) {
682 /* used = prod - cons - prod/size + cons/size */
683 used -= NUM_TX_BD - NUM_TX_RINGS;
684 }
685
686 BUG_TRAP(used <= fp->bp->tx_ring_size);
687 BUG_TRAP((fp->bp->tx_ring_size - used) <= MAX_TX_AVAIL);
688
689 return (fp->bp->tx_ring_size - used);
690}
691
692static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
693{
694 struct bnx2x *bp = fp->bp;
695 u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
696 int done = 0;
697
698#ifdef BNX2X_STOP_ON_ERROR
699 if (unlikely(bp->panic))
700 return;
701#endif
702
703 hw_cons = le16_to_cpu(*fp->tx_cons_sb);
704 sw_cons = fp->tx_pkt_cons;
705
706 while (sw_cons != hw_cons) {
707 u16 pkt_cons;
708
709 pkt_cons = TX_BD(sw_cons);
710
711 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
712
713 DP(NETIF_MSG_TX_DONE, "hw_cons %u sw_cons %u pkt_cons %d\n",
714 hw_cons, sw_cons, pkt_cons);
715
716/* if (NEXT_TX_IDX(sw_cons) != hw_cons) {
717 rmb();
718 prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
719 }
720*/
721 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
722 sw_cons++;
723 done++;
724
725 if (done == work)
726 break;
727 }
728
729 fp->tx_pkt_cons = sw_cons;
730 fp->tx_bd_cons = bd_cons;
731
732 /* Need to make the tx_cons update visible to start_xmit()
733 * before checking for netif_queue_stopped(). Without the
734 * memory barrier, there is a small possibility that start_xmit()
735 * will miss it and cause the queue to be stopped forever.
736 */
737 smp_mb();
738
739 /* TBD need a thresh? */
740 if (unlikely(netif_queue_stopped(bp->dev))) {
741
742 netif_tx_lock(bp->dev);
743
744 if (netif_queue_stopped(bp->dev) &&
745 (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
746 netif_wake_queue(bp->dev);
747
748 netif_tx_unlock(bp->dev);
749
750 }
751}
752
753static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
754 union eth_rx_cqe *rr_cqe)
755{
756 struct bnx2x *bp = fp->bp;
757 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
758 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
759
760 DP(NETIF_MSG_RX_STATUS,
761 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
762 fp->index, cid, command, bp->state, rr_cqe->ramrod_cqe.type);
763
764 bp->spq_left++;
765
766 if (fp->index) {
767 switch (command | fp->state) {
768 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
769 BNX2X_FP_STATE_OPENING):
770 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
771 cid);
772 fp->state = BNX2X_FP_STATE_OPEN;
773 break;
774
775 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
776 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
777 cid);
778 fp->state = BNX2X_FP_STATE_HALTED;
779 break;
780
781 default:
782 BNX2X_ERR("unexpected MC reply(%d) state is %x\n",
783 command, fp->state);
784 }
785 mb(); /* force bnx2x_wait_ramrod to see the change */
786 return;
787 }
788
789 switch (command | bp->state) {
790 case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
791 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
792 bp->state = BNX2X_STATE_OPEN;
793 break;
794
795 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
796 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
797 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
798 fp->state = BNX2X_FP_STATE_HALTED;
799 break;
800
801 case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
802 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n",
803 cid);
804 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
805 break;
806
807 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
808 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
809 break;
810
811 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
812 DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n");
813 break;
814
815 default:
816 BNX2X_ERR("unexpected ramrod (%d) state is %x\n",
817 command, bp->state);
818 }
819
820 mb(); /* force bnx2x_wait_ramrod to see the change */
821}
822
823static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
824 struct bnx2x_fastpath *fp, u16 index)
825{
826 struct sk_buff *skb;
827 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
828 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
829 dma_addr_t mapping;
830
831 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
832 if (unlikely(skb == NULL))
833 return -ENOMEM;
834
835 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
836 PCI_DMA_FROMDEVICE);
837 if (unlikely(dma_mapping_error(mapping))) {
838
839 dev_kfree_skb(skb);
840 return -ENOMEM;
841 }
842
843 rx_buf->skb = skb;
844 pci_unmap_addr_set(rx_buf, mapping, mapping);
845
846 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
847 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
848
849 return 0;
850}
851
852/* note that we are not allocating a new skb,
853 * we are just moving one from cons to prod
854 * we are not creating a new mapping,
855 * so there is no need to check for dma_mapping_error().
856 */
857static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
858 struct sk_buff *skb, u16 cons, u16 prod)
859{
860 struct bnx2x *bp = fp->bp;
861 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
862 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
863 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
864 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
865
866 pci_dma_sync_single_for_device(bp->pdev,
867 pci_unmap_addr(cons_rx_buf, mapping),
868 bp->rx_offset + RX_COPY_THRESH,
869 PCI_DMA_FROMDEVICE);
870
871 prod_rx_buf->skb = cons_rx_buf->skb;
872 pci_unmap_addr_set(prod_rx_buf, mapping,
873 pci_unmap_addr(cons_rx_buf, mapping));
874 *prod_bd = *cons_bd;
875}
876
877static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
878{
879 struct bnx2x *bp = fp->bp;
880 u16 bd_cons, bd_prod, comp_ring_cons;
881 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
882 int rx_pkt = 0;
883
884#ifdef BNX2X_STOP_ON_ERROR
885 if (unlikely(bp->panic))
886 return 0;
887#endif
888
889 hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
890 if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
891 hw_comp_cons++;
892
893 bd_cons = fp->rx_bd_cons;
894 bd_prod = fp->rx_bd_prod;
895 sw_comp_cons = fp->rx_comp_cons;
896 sw_comp_prod = fp->rx_comp_prod;
897
898 /* Memory barrier necessary as speculative reads of the rx
899 * buffer can be ahead of the index in the status block
900 */
901 rmb();
902
903 DP(NETIF_MSG_RX_STATUS,
904 "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
905 fp->index, hw_comp_cons, sw_comp_cons);
906
907 while (sw_comp_cons != hw_comp_cons) {
908 unsigned int len, pad;
909 struct sw_rx_bd *rx_buf;
910 struct sk_buff *skb;
911 union eth_rx_cqe *cqe;
912
913 comp_ring_cons = RCQ_BD(sw_comp_cons);
914 bd_prod = RX_BD(bd_prod);
915 bd_cons = RX_BD(bd_cons);
916
917 cqe = &fp->rx_comp_ring[comp_ring_cons];
918
919 DP(NETIF_MSG_RX_STATUS, "hw_comp_cons %u sw_comp_cons %u"
920 " comp_ring (%u) bd_ring (%u,%u)\n",
921 hw_comp_cons, sw_comp_cons,
922 comp_ring_cons, bd_prod, bd_cons);
923 DP(NETIF_MSG_RX_STATUS, "CQE type %x err %x status %x"
924 " queue %x vlan %x len %x\n",
925 cqe->fast_path_cqe.type,
926 cqe->fast_path_cqe.error_type_flags,
927 cqe->fast_path_cqe.status_flags,
928 cqe->fast_path_cqe.rss_hash_result,
929 cqe->fast_path_cqe.vlan_tag, cqe->fast_path_cqe.pkt_len);
930
931 /* is this a slowpath msg? */
932 if (unlikely(cqe->fast_path_cqe.type)) {
933 bnx2x_sp_event(fp, cqe);
934 goto next_cqe;
935
936 /* this is an rx packet */
937 } else {
938 rx_buf = &fp->rx_buf_ring[bd_cons];
939 skb = rx_buf->skb;
940
941 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
942 pad = cqe->fast_path_cqe.placement_offset;
943
944 pci_dma_sync_single_for_device(bp->pdev,
945 pci_unmap_addr(rx_buf, mapping),
946 pad + RX_COPY_THRESH,
947 PCI_DMA_FROMDEVICE);
948 prefetch(skb);
949 prefetch(((char *)(skb)) + 128);
950
951 /* is this an error packet? */
952 if (unlikely(cqe->fast_path_cqe.error_type_flags &
953 ETH_RX_ERROR_FALGS)) {
954 /* do we sometimes forward error packets anyway? */
955 DP(NETIF_MSG_RX_ERR,
956 "ERROR flags(%u) Rx packet(%u)\n",
957 cqe->fast_path_cqe.error_type_flags,
958 sw_comp_cons);
959 /* TBD make sure MC counts this as a drop */
960 goto reuse_rx;
961 }
962
963 /* Since we don't have a jumbo ring
964 * copy small packets if mtu > 1500
965 */
966 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
967 (len <= RX_COPY_THRESH)) {
968 struct sk_buff *new_skb;
969
970 new_skb = netdev_alloc_skb(bp->dev,
971 len + pad);
972 if (new_skb == NULL) {
973 DP(NETIF_MSG_RX_ERR,
974 "ERROR packet dropped "
975 "because of alloc failure\n");
976 /* TBD count this as a drop? */
977 goto reuse_rx;
978 }
979
980 /* aligned copy */
981 skb_copy_from_linear_data_offset(skb, pad,
982 new_skb->data + pad, len);
983 skb_reserve(new_skb, pad);
984 skb_put(new_skb, len);
985
986 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
987
988 skb = new_skb;
989
990 } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
991 pci_unmap_single(bp->pdev,
992 pci_unmap_addr(rx_buf, mapping),
993 bp->rx_buf_use_size,
994 PCI_DMA_FROMDEVICE);
995 skb_reserve(skb, pad);
996 skb_put(skb, len);
997
998 } else {
999 DP(NETIF_MSG_RX_ERR,
1000 "ERROR packet dropped because "
1001 "of alloc failure\n");
1002reuse_rx:
1003 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1004 goto next_rx;
1005 }
1006
1007 skb->protocol = eth_type_trans(skb, bp->dev);
1008
1009 skb->ip_summed = CHECKSUM_NONE;
1010 if (bp->rx_csum && BNX2X_RX_SUM_OK(cqe))
1011 skb->ip_summed = CHECKSUM_UNNECESSARY;
1012
1013 /* TBD do we pass bad csum packets in promisc */
1014 }
1015
1016#ifdef BCM_VLAN
1017 if ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags)
1018 & PARSING_FLAGS_NUMBER_OF_NESTED_VLANS)
1019 && (bp->vlgrp != NULL))
1020 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1021 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1022 else
1023#endif
1024 netif_receive_skb(skb);
1025
1026 bp->dev->last_rx = jiffies;
1027
1028next_rx:
1029 rx_buf->skb = NULL;
1030
1031 bd_cons = NEXT_RX_IDX(bd_cons);
1032 bd_prod = NEXT_RX_IDX(bd_prod);
1033next_cqe:
1034 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1035 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1036 rx_pkt++;
1037
1038 if ((rx_pkt == budget))
1039 break;
1040 } /* while */
1041
1042 fp->rx_bd_cons = bd_cons;
1043 fp->rx_bd_prod = bd_prod;
1044 fp->rx_comp_cons = sw_comp_cons;
1045 fp->rx_comp_prod = sw_comp_prod;
1046
1047 REG_WR(bp, BAR_TSTRORM_INTMEM +
1048 TSTORM_RCQ_PROD_OFFSET(bp->port, fp->index), sw_comp_prod);
1049
1050 mmiowb(); /* keep prod updates ordered */
1051
1052 fp->rx_pkt += rx_pkt;
1053 fp->rx_calls++;
1054
1055 return rx_pkt;
1056}
1057
1058static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1059{
1060 struct bnx2x_fastpath *fp = fp_cookie;
1061 struct bnx2x *bp = fp->bp;
1062 struct net_device *dev = bp->dev;
1063 int index = fp->index;
1064
1065 DP(NETIF_MSG_INTR, "got an msix interrupt on [%d]\n", index);
1066 bnx2x_ack_sb(bp, index, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1067
1068#ifdef BNX2X_STOP_ON_ERROR
1069 if (unlikely(bp->panic))
1070 return IRQ_HANDLED;
1071#endif
1072
1073 prefetch(fp->rx_cons_sb);
1074 prefetch(fp->tx_cons_sb);
1075 prefetch(&fp->status_blk->c_status_block.status_block_index);
1076 prefetch(&fp->status_blk->u_status_block.status_block_index);
1077
1078 netif_rx_schedule(dev, &bnx2x_fp(bp, index, napi));
1079 return IRQ_HANDLED;
1080}
1081
1082static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1083{
1084 struct net_device *dev = dev_instance;
1085 struct bnx2x *bp = netdev_priv(dev);
1086 u16 status = bnx2x_ack_int(bp);
1087
1088 if (unlikely(status == 0)) {
1089 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1090 return IRQ_NONE;
1091 }
1092
1093 DP(NETIF_MSG_INTR, "got an interrupt status is %u\n", status);
1094
1095#ifdef BNX2X_STOP_ON_ERROR
1096 if (unlikely(bp->panic))
1097 return IRQ_HANDLED;
1098#endif
1099
1100 /* Return here if interrupt is shared and is disabled */
1101 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1102 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1103 return IRQ_HANDLED;
1104 }
1105
1106 if (status & 0x2) {
1107 struct bnx2x_fastpath *fp = &bp->fp[0];
1108
1109 prefetch(fp->rx_cons_sb);
1110 prefetch(fp->tx_cons_sb);
1111 prefetch(&fp->status_blk->c_status_block.status_block_index);
1112 prefetch(&fp->status_blk->u_status_block.status_block_index);
1113
1114 netif_rx_schedule(dev, &bnx2x_fp(bp, 0, napi));
1115
1116 status &= ~0x2;
1117 if (!status)
1118 return IRQ_HANDLED;
1119 }
1120
1121 if (unlikely(status & 0x1)) {
1122
1123 schedule_work(&bp->sp_task);
1124
1125 status &= ~0x1;
1126 if (!status)
1127 return IRQ_HANDLED;
1128 }
1129
1130 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status is %u)\n",
1131 status);
1132
1133 return IRQ_HANDLED;
1134}
1135
1136/* end of fast path */
1137
1138/* PHY/MAC */
1139
1140/*
1141 * General service functions
1142 */
1143
1144static void bnx2x_leds_set(struct bnx2x *bp, unsigned int speed)
1145{
1146 int port = bp->port;
1147
1148 NIG_WR(NIG_REG_LED_MODE_P0 + port*4,
1149 ((bp->hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
1150 SHARED_HW_CFG_LED_MODE_SHIFT));
1151 NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
1152
1153 /* Set blinking rate to ~15.9Hz */
1154 NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
1155 LED_BLINK_RATE_VAL);
1156 NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port*4, 1);
1157
1158 /* On Ax chip versions for speeds less than 10G
1159 LED scheme is different */
1160 if ((CHIP_REV(bp) == CHIP_REV_Ax) && (speed < SPEED_10000)) {
1161 NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 1);
1162 NIG_WR(NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4, 0);
1163 NIG_WR(NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + port*4, 1);
1164 }
1165}
1166
1167static void bnx2x_leds_unset(struct bnx2x *bp)
1168{
1169 int port = bp->port;
1170
1171 NIG_WR(NIG_REG_LED_10G_P0 + port*4, 0);
1172 NIG_WR(NIG_REG_LED_MODE_P0 + port*4, SHARED_HW_CFG_LED_MAC1);
1173}
1174
1175static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
1176{
1177 u32 val = REG_RD(bp, reg);
1178
1179 val |= bits;
1180 REG_WR(bp, reg, val);
1181 return val;
1182}
1183
1184static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
1185{
1186 u32 val = REG_RD(bp, reg);
1187
1188 val &= ~bits;
1189 REG_WR(bp, reg, val);
1190 return val;
1191}
1192
1193static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1194{
1195 u32 cnt;
1196 u32 lock_status;
1197 u32 resource_bit = (1 << resource);
1198 u8 func = bp->port;
1199
1200 /* Validating that the resource is within range */
1201 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1202 DP(NETIF_MSG_HW,
1203 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1204 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1205 return -EINVAL;
1206 }
1207
1208 /* Validating that the resource is not already taken */
1209 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8);
1210 if (lock_status & resource_bit) {
1211 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1212 lock_status, resource_bit);
1213 return -EEXIST;
1214 }
1215
1216 /* Try for 1 second every 5ms */
1217 for (cnt = 0; cnt < 200; cnt++) {
1218 /* Try to acquire the lock */
1219 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8 + 4,
1220 resource_bit);
1221 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8);
1222 if (lock_status & resource_bit)
1223 return 0;
1224
1225 msleep(5);
1226 }
1227 DP(NETIF_MSG_HW, "Timeout\n");
1228 return -EAGAIN;
1229}
1230
1231static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
1232{
1233 u32 lock_status;
1234 u32 resource_bit = (1 << resource);
1235 u8 func = bp->port;
1236
1237 /* Validating that the resource is within range */
1238 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1239 DP(NETIF_MSG_HW,
1240 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1241 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1242 return -EINVAL;
1243 }
1244
1245 /* Validating that the resource is currently taken */
1246 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8);
1247 if (!(lock_status & resource_bit)) {
1248 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1249 lock_status, resource_bit);
1250 return -EFAULT;
1251 }
1252
1253 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8, resource_bit);
1254 return 0;
1255}
1256
1257static int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1258{
1259 /* The GPIO should be swapped if swap register is set and active */
1260 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1261 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ bp->port;
1262 int gpio_shift = gpio_num +
1263 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1264 u32 gpio_mask = (1 << gpio_shift);
1265 u32 gpio_reg;
1266
1267 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1268 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1269 return -EINVAL;
1270 }
1271
1272 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1273 /* read GPIO and mask except the float bits */
1274 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1275
1276 switch (mode) {
1277 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1278 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1279 gpio_num, gpio_shift);
1280 /* clear FLOAT and set CLR */
1281 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1282 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1283 break;
1284
1285 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1286 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1287 gpio_num, gpio_shift);
1288 /* clear FLOAT and set SET */
1289 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1290 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1291 break;
1292
1293 case MISC_REGISTERS_GPIO_INPUT_HI_Z :
1294 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1295 gpio_num, gpio_shift);
1296 /* set FLOAT */
1297 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1298 break;
1299
1300 default:
1301 break;
1302 }
1303
1304 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1305 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_GPIO);
1306
1307 return 0;
1308}
1309
1310static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1311{
1312 u32 spio_mask = (1 << spio_num);
1313 u32 spio_reg;
1314
1315 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1316 (spio_num > MISC_REGISTERS_SPIO_7)) {
1317 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1318 return -EINVAL;
1319 }
1320
1321 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1322 /* read SPIO and mask except the float bits */
1323 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1324
1325 switch (mode) {
1326 case MISC_REGISTERS_SPIO_OUTPUT_LOW :
1327 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1328 /* clear FLOAT and set CLR */
1329 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1330 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1331 break;
1332
1333 case MISC_REGISTERS_SPIO_OUTPUT_HIGH :
1334 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1335 /* clear FLOAT and set SET */
1336 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1337 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1338 break;
1339
1340 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1341 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1342 /* set FLOAT */
1343 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1344 break;
1345
1346 default:
1347 break;
1348 }
1349
1350 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1351 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_SPIO);
1352
1353 return 0;
1354}
1355
1356static int bnx2x_mdio22_write(struct bnx2x *bp, u32 reg, u32 val)
1357{
1358 int port = bp->port;
1359 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1360 u32 tmp;
1361 int i, rc;
1362
1363/* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x val 0x%08x\n",
1364 bp->phy_addr, reg, val); */
1365
1366 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1367
1368 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1369 tmp &= ~EMAC_MDIO_MODE_AUTO_POLL;
1370 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1371 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1372 udelay(40);
1373 }
1374
1375 tmp = ((bp->phy_addr << 21) | (reg << 16) |
1376 (val & EMAC_MDIO_COMM_DATA) |
1377 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
1378 EMAC_MDIO_COMM_START_BUSY);
1379 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp);
1380
1381 for (i = 0; i < 50; i++) {
1382 udelay(10);
1383
1384 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1385 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1386 udelay(5);
1387 break;
1388 }
1389 }
1390
1391 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1392 BNX2X_ERR("write phy register failed\n");
1393
1394 rc = -EBUSY;
1395 } else {
1396 rc = 0;
1397 }
1398
1399 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1400
1401 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1402 tmp |= EMAC_MDIO_MODE_AUTO_POLL;
1403 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1404 }
1405
1406 return rc;
1407}
1408
1409static int bnx2x_mdio22_read(struct bnx2x *bp, u32 reg, u32 *ret_val)
1410{
1411 int port = bp->port;
1412 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1413 u32 val;
1414 int i, rc;
1415
1416 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1417
1418 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1419 val &= ~EMAC_MDIO_MODE_AUTO_POLL;
1420 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1421 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1422 udelay(40);
1423 }
1424
1425 val = ((bp->phy_addr << 21) | (reg << 16) |
1426 EMAC_MDIO_COMM_COMMAND_READ_22 |
1427 EMAC_MDIO_COMM_START_BUSY);
1428 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val);
1429
1430 for (i = 0; i < 50; i++) {
1431 udelay(10);
1432
1433 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1434 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1435 val &= EMAC_MDIO_COMM_DATA;
1436 break;
1437 }
1438 }
1439
1440 if (val & EMAC_MDIO_COMM_START_BUSY) {
1441 BNX2X_ERR("read phy register failed\n");
1442
1443 *ret_val = 0x0;
1444 rc = -EBUSY;
1445 } else {
1446 *ret_val = val;
1447 rc = 0;
1448 }
1449
1450 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1451
1452 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1453 val |= EMAC_MDIO_MODE_AUTO_POLL;
1454 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1455 }
1456
1457/* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x ret_val 0x%08x\n",
1458 bp->phy_addr, reg, *ret_val); */
1459
1460 return rc;
1461}
1462
1463static int bnx2x_mdio45_ctrl_write(struct bnx2x *bp, u32 mdio_ctrl,
1464 u32 phy_addr, u32 reg, u32 addr, u32 val)
1465{
1466 u32 tmp;
1467 int i, rc = 0;
1468
1469 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1470 * (a value of 49==0x31) and make sure that the AUTO poll is off
1471 */
1472 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1473 tmp &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1474 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1475 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1476 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1477 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1478 udelay(40);
1479
1480 /* address */
1481 tmp = ((phy_addr << 21) | (reg << 16) | addr |
1482 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1483 EMAC_MDIO_COMM_START_BUSY);
1484 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1485
1486 for (i = 0; i < 50; i++) {
1487 udelay(10);
1488
1489 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1490 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1491 udelay(5);
1492 break;
1493 }
1494 }
1495 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1496 BNX2X_ERR("write phy register failed\n");
1497
1498 rc = -EBUSY;
1499
1500 } else {
1501 /* data */
1502 tmp = ((phy_addr << 21) | (reg << 16) | val |
1503 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1504 EMAC_MDIO_COMM_START_BUSY);
1505 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1506
1507 for (i = 0; i < 50; i++) {
1508 udelay(10);
1509
1510 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1511 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1512 udelay(5);
1513 break;
1514 }
1515 }
1516
1517 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1518 BNX2X_ERR("write phy register failed\n");
1519
1520 rc = -EBUSY;
1521 }
1522 }
1523
1524 /* unset clause 45 mode, set the MDIO clock to a faster value
1525 * (0x13 => 6.25Mhz) and restore the AUTO poll if needed
1526 */
1527 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1528 tmp &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT);
1529 tmp |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1530 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG)
1531 tmp |= EMAC_MDIO_MODE_AUTO_POLL;
1532 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1533
1534 return rc;
1535}
1536
1537static int bnx2x_mdio45_write(struct bnx2x *bp, u32 phy_addr, u32 reg,
1538 u32 addr, u32 val)
1539{
1540 u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1541
1542 return bnx2x_mdio45_ctrl_write(bp, emac_base, phy_addr,
1543 reg, addr, val);
1544}
1545
1546static int bnx2x_mdio45_ctrl_read(struct bnx2x *bp, u32 mdio_ctrl,
1547 u32 phy_addr, u32 reg, u32 addr,
1548 u32 *ret_val)
1549{
1550 u32 val;
1551 int i, rc = 0;
1552
1553 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1554 * (a value of 49==0x31) and make sure that the AUTO poll is off
1555 */
1556 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1557 val &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1558 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1559 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1560 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1561 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1562 udelay(40);
1563
1564 /* address */
1565 val = ((phy_addr << 21) | (reg << 16) | addr |
1566 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1567 EMAC_MDIO_COMM_START_BUSY);
1568 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1569
1570 for (i = 0; i < 50; i++) {
1571 udelay(10);
1572
1573 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1574 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1575 udelay(5);
1576 break;
1577 }
1578 }
1579 if (val & EMAC_MDIO_COMM_START_BUSY) {
1580 BNX2X_ERR("read phy register failed\n");
1581
1582 *ret_val = 0;
1583 rc = -EBUSY;
1584
1585 } else {
1586 /* data */
1587 val = ((phy_addr << 21) | (reg << 16) |
1588 EMAC_MDIO_COMM_COMMAND_READ_45 |
1589 EMAC_MDIO_COMM_START_BUSY);
1590 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1591
1592 for (i = 0; i < 50; i++) {
1593 udelay(10);
1594
1595 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1596 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1597 val &= EMAC_MDIO_COMM_DATA;
1598 break;
1599 }
1600 }
1601
1602 if (val & EMAC_MDIO_COMM_START_BUSY) {
1603 BNX2X_ERR("read phy register failed\n");
1604
1605 val = 0;
1606 rc = -EBUSY;
1607 }
1608
1609 *ret_val = val;
1610 }
1611
1612 /* unset clause 45 mode, set the MDIO clock to a faster value
1613 * (0x13 => 6.25Mhz) and restore the AUTO poll if needed
1614 */
1615 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1616 val &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT);
1617 val |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1618 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG)
1619 val |= EMAC_MDIO_MODE_AUTO_POLL;
1620 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1621
1622 return rc;
1623}
1624
1625static int bnx2x_mdio45_read(struct bnx2x *bp, u32 phy_addr, u32 reg,
1626 u32 addr, u32 *ret_val)
1627{
1628 u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1629
1630 return bnx2x_mdio45_ctrl_read(bp, emac_base, phy_addr,
1631 reg, addr, ret_val);
1632}
1633
1634static int bnx2x_mdio45_vwrite(struct bnx2x *bp, u32 phy_addr, u32 reg,
1635 u32 addr, u32 val)
1636{
1637 int i;
1638 u32 rd_val;
1639
1640 might_sleep();
1641 for (i = 0; i < 10; i++) {
1642 bnx2x_mdio45_write(bp, phy_addr, reg, addr, val);
1643 msleep(5);
1644 bnx2x_mdio45_read(bp, phy_addr, reg, addr, &rd_val);
1645 /* if the read value is not the same as the value we wrote,
1646 we should write it again */
1647 if (rd_val == val)
1648 return 0;
1649 }
1650 BNX2X_ERR("MDIO write in CL45 failed\n");
1651 return -EBUSY;
1652}
1653
1654/*
1655 * link management
1656 */
1657
1658static void bnx2x_pause_resolve(struct bnx2x *bp, u32 pause_result)
1659{
1660 switch (pause_result) { /* ASYM P ASYM P */
1661 case 0xb: /* 1 0 1 1 */
1662 bp->flow_ctrl = FLOW_CTRL_TX;
1663 break;
1664
1665 case 0xe: /* 1 1 1 0 */
1666 bp->flow_ctrl = FLOW_CTRL_RX;
1667 break;
1668
1669 case 0x5: /* 0 1 0 1 */
1670 case 0x7: /* 0 1 1 1 */
1671 case 0xd: /* 1 1 0 1 */
1672 case 0xf: /* 1 1 1 1 */
1673 bp->flow_ctrl = FLOW_CTRL_BOTH;
1674 break;
1675
1676 default:
1677 break;
1678 }
1679}
1680
1681static u8 bnx2x_ext_phy_resove_fc(struct bnx2x *bp)
1682{
1683 u32 ext_phy_addr;
1684 u32 ld_pause; /* local */
1685 u32 lp_pause; /* link partner */
1686 u32 an_complete; /* AN complete */
1687 u32 pause_result;
1688 u8 ret = 0;
1689
1690 ext_phy_addr = ((bp->ext_phy_config &
1691 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1692 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1693
1694 /* read twice */
1695 bnx2x_mdio45_read(bp, ext_phy_addr,
1696 EXT_PHY_KR_AUTO_NEG_DEVAD,
1697 EXT_PHY_KR_STATUS, &an_complete);
1698 bnx2x_mdio45_read(bp, ext_phy_addr,
1699 EXT_PHY_KR_AUTO_NEG_DEVAD,
1700 EXT_PHY_KR_STATUS, &an_complete);
1701
1702 if (an_complete & EXT_PHY_KR_AUTO_NEG_COMPLETE) {
1703 ret = 1;
1704 bnx2x_mdio45_read(bp, ext_phy_addr,
1705 EXT_PHY_KR_AUTO_NEG_DEVAD,
1706 EXT_PHY_KR_AUTO_NEG_ADVERT, &ld_pause);
1707 bnx2x_mdio45_read(bp, ext_phy_addr,
1708 EXT_PHY_KR_AUTO_NEG_DEVAD,
1709 EXT_PHY_KR_LP_AUTO_NEG, &lp_pause);
1710 pause_result = (ld_pause &
1711 EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 8;
1712 pause_result |= (lp_pause &
1713 EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 10;
1714 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1715 pause_result);
1716 bnx2x_pause_resolve(bp, pause_result);
1717 }
1718 return ret;
1719}
1720
1721static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status)
1722{
1723 u32 ld_pause; /* local driver */
1724 u32 lp_pause; /* link partner */
1725 u32 pause_result;
1726
1727 bp->flow_ctrl = 0;
1728
1729 /* resolve from gp_status in case of AN complete and not sgmii */
1730 if ((bp->req_autoneg & AUTONEG_FLOW_CTRL) &&
1731 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1732 (!(bp->phy_flags & PHY_SGMII_FLAG)) &&
1733 (XGXS_EXT_PHY_TYPE(bp) == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1734
1735 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
1736 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1737 &ld_pause);
1738 bnx2x_mdio22_read(bp,
1739 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1740 &lp_pause);
1741 pause_result = (ld_pause &
1742 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1743 pause_result |= (lp_pause &
1744 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1745 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
1746 bnx2x_pause_resolve(bp, pause_result);
1747 } else if (!(bp->req_autoneg & AUTONEG_FLOW_CTRL) ||
1748 !(bnx2x_ext_phy_resove_fc(bp))) {
1749 /* forced speed */
1750 if (bp->req_autoneg & AUTONEG_FLOW_CTRL) {
1751 switch (bp->req_flow_ctrl) {
1752 case FLOW_CTRL_AUTO:
1753 if (bp->dev->mtu <= 4500)
1754 bp->flow_ctrl = FLOW_CTRL_BOTH;
1755 else
1756 bp->flow_ctrl = FLOW_CTRL_TX;
1757 break;
1758
1759 case FLOW_CTRL_TX:
1760 bp->flow_ctrl = FLOW_CTRL_TX;
1761 break;
1762
1763 case FLOW_CTRL_RX:
1764 if (bp->dev->mtu <= 4500)
1765 bp->flow_ctrl = FLOW_CTRL_RX;
1766 break;
1767
1768 case FLOW_CTRL_BOTH:
1769 if (bp->dev->mtu <= 4500)
1770 bp->flow_ctrl = FLOW_CTRL_BOTH;
1771 else
1772 bp->flow_ctrl = FLOW_CTRL_TX;
1773 break;
1774
1775 case FLOW_CTRL_NONE:
1776 default:
1777 break;
1778 }
1779 } else { /* forced mode */
1780 switch (bp->req_flow_ctrl) {
1781 case FLOW_CTRL_AUTO:
1782 DP(NETIF_MSG_LINK, "req_flow_ctrl 0x%x while"
1783 " req_autoneg 0x%x\n",
1784 bp->req_flow_ctrl, bp->req_autoneg);
1785 break;
1786
1787 case FLOW_CTRL_TX:
1788 case FLOW_CTRL_RX:
1789 case FLOW_CTRL_BOTH:
1790 bp->flow_ctrl = bp->req_flow_ctrl;
1791 break;
1792
1793 case FLOW_CTRL_NONE:
1794 default:
1795 break;
1796 }
1797 }
1798 }
1799 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", bp->flow_ctrl);
1800}
1801
1802static void bnx2x_link_settings_status(struct bnx2x *bp, u32 gp_status)
1803{
1804 bp->link_status = 0;
1805
1806 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1807 DP(NETIF_MSG_LINK, "phy link up\n");
1808
1809 bp->phy_link_up = 1;
1810 bp->link_status |= LINK_STATUS_LINK_UP;
1811
1812 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1813 bp->duplex = DUPLEX_FULL;
1814 else
1815 bp->duplex = DUPLEX_HALF;
1816
1817 bnx2x_flow_ctrl_resolve(bp, gp_status);
1818
1819 switch (gp_status & GP_STATUS_SPEED_MASK) {
1820 case GP_STATUS_10M:
1821 bp->line_speed = SPEED_10;
1822 if (bp->duplex == DUPLEX_FULL)
1823 bp->link_status |= LINK_10TFD;
1824 else
1825 bp->link_status |= LINK_10THD;
1826 break;
1827
1828 case GP_STATUS_100M:
1829 bp->line_speed = SPEED_100;
1830 if (bp->duplex == DUPLEX_FULL)
1831 bp->link_status |= LINK_100TXFD;
1832 else
1833 bp->link_status |= LINK_100TXHD;
1834 break;
1835
1836 case GP_STATUS_1G:
1837 case GP_STATUS_1G_KX:
1838 bp->line_speed = SPEED_1000;
1839 if (bp->duplex == DUPLEX_FULL)
1840 bp->link_status |= LINK_1000TFD;
1841 else
1842 bp->link_status |= LINK_1000THD;
1843 break;
1844
1845 case GP_STATUS_2_5G:
1846 bp->line_speed = SPEED_2500;
1847 if (bp->duplex == DUPLEX_FULL)
1848 bp->link_status |= LINK_2500TFD;
1849 else
1850 bp->link_status |= LINK_2500THD;
1851 break;
1852
1853 case GP_STATUS_5G:
1854 case GP_STATUS_6G:
1855 BNX2X_ERR("link speed unsupported gp_status 0x%x\n",
1856 gp_status);
1857 break;
1858
1859 case GP_STATUS_10G_KX4:
1860 case GP_STATUS_10G_HIG:
1861 case GP_STATUS_10G_CX4:
1862 bp->line_speed = SPEED_10000;
1863 bp->link_status |= LINK_10GTFD;
1864 break;
1865
1866 case GP_STATUS_12G_HIG:
1867 bp->line_speed = SPEED_12000;
1868 bp->link_status |= LINK_12GTFD;
1869 break;
1870
1871 case GP_STATUS_12_5G:
1872 bp->line_speed = SPEED_12500;
1873 bp->link_status |= LINK_12_5GTFD;
1874 break;
1875
1876 case GP_STATUS_13G:
1877 bp->line_speed = SPEED_13000;
1878 bp->link_status |= LINK_13GTFD;
1879 break;
1880
1881 case GP_STATUS_15G:
1882 bp->line_speed = SPEED_15000;
1883 bp->link_status |= LINK_15GTFD;
1884 break;
1885
1886 case GP_STATUS_16G:
1887 bp->line_speed = SPEED_16000;
1888 bp->link_status |= LINK_16GTFD;
1889 break;
1890
1891 default:
1892 BNX2X_ERR("link speed unsupported gp_status 0x%x\n",
1893 gp_status);
1894 break;
1895 }
1896
1897 bp->link_status |= LINK_STATUS_SERDES_LINK;
1898
1899 if (bp->req_autoneg & AUTONEG_SPEED) {
1900 bp->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
1901
1902 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
1903 bp->link_status |=
1904 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1905
1906 if (bp->autoneg & AUTONEG_PARALLEL)
1907 bp->link_status |=
1908 LINK_STATUS_PARALLEL_DETECTION_USED;
1909 }
1910
1911 if (bp->flow_ctrl & FLOW_CTRL_TX)
1912 bp->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1913
1914 if (bp->flow_ctrl & FLOW_CTRL_RX)
1915 bp->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1916
1917 } else { /* link_down */
1918 DP(NETIF_MSG_LINK, "phy link down\n");
1919
1920 bp->phy_link_up = 0;
1921
1922 bp->line_speed = 0;
1923 bp->duplex = DUPLEX_FULL;
1924 bp->flow_ctrl = 0;
1925 }
1926
1927 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %d\n"
1928 DP_LEVEL " line_speed %d duplex %d flow_ctrl 0x%x"
1929 " link_status 0x%x\n",
1930 gp_status, bp->phy_link_up, bp->line_speed, bp->duplex,
1931 bp->flow_ctrl, bp->link_status);
1932}
1933
1934static void bnx2x_link_int_ack(struct bnx2x *bp, int is_10g)
1935{
1936 int port = bp->port;
1937
1938 /* first reset all status
1939 * we assume only one line will be change at a time */
1940 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1941 (NIG_STATUS_XGXS0_LINK10G |
1942 NIG_STATUS_XGXS0_LINK_STATUS |
1943 NIG_STATUS_SERDES0_LINK_STATUS));
1944 if (bp->phy_link_up) {
1945 if (is_10g) {
1946 /* Disable the 10G link interrupt
1947 * by writing 1 to the status register
1948 */
1949 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
1950 bnx2x_bits_en(bp,
1951 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1952 NIG_STATUS_XGXS0_LINK10G);
1953
1954 } else if (bp->phy_flags & PHY_XGXS_FLAG) {
1955 /* Disable the link interrupt
1956 * by writing 1 to the relevant lane
1957 * in the status register
1958 */
1959 DP(NETIF_MSG_LINK, "1G XGXS phy link up\n");
1960 bnx2x_bits_en(bp,
1961 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1962 ((1 << bp->ser_lane) <<
1963 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
1964
1965 } else { /* SerDes */
1966 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
1967 /* Disable the link interrupt
1968 * by writing 1 to the status register
1969 */
1970 bnx2x_bits_en(bp,
1971 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1972 NIG_STATUS_SERDES0_LINK_STATUS);
1973 }
1974
1975 } else { /* link_down */
1976 }
1977}
1978
1979static int bnx2x_ext_phy_is_link_up(struct bnx2x *bp)
1980{
1981 u32 ext_phy_type;
1982 u32 ext_phy_addr;
1983 u32 val1 = 0, val2;
1984 u32 rx_sd, pcs_status;
1985
1986 if (bp->phy_flags & PHY_XGXS_FLAG) {
1987 ext_phy_addr = ((bp->ext_phy_config &
1988 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1989 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1990
1991 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
1992 switch (ext_phy_type) {
1993 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
1994 DP(NETIF_MSG_LINK, "XGXS Direct\n");
1995 val1 = 1;
1996 break;
1997
1998 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
1999 DP(NETIF_MSG_LINK, "XGXS 8705\n");
2000 bnx2x_mdio45_read(bp, ext_phy_addr,
2001 EXT_PHY_OPT_WIS_DEVAD,
2002 EXT_PHY_OPT_LASI_STATUS, &val1);
2003 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2004
2005 bnx2x_mdio45_read(bp, ext_phy_addr,
2006 EXT_PHY_OPT_WIS_DEVAD,
2007 EXT_PHY_OPT_LASI_STATUS, &val1);
2008 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2009
2010 bnx2x_mdio45_read(bp, ext_phy_addr,
2011 EXT_PHY_OPT_PMA_PMD_DEVAD,
2012 EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
2013 DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd);
2014 val1 = (rx_sd & 0x1);
2015 break;
2016
2017 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2018 DP(NETIF_MSG_LINK, "XGXS 8706\n");
2019 bnx2x_mdio45_read(bp, ext_phy_addr,
2020 EXT_PHY_OPT_PMA_PMD_DEVAD,
2021 EXT_PHY_OPT_LASI_STATUS, &val1);
2022 DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2023
2024 bnx2x_mdio45_read(bp, ext_phy_addr,
2025 EXT_PHY_OPT_PMA_PMD_DEVAD,
2026 EXT_PHY_OPT_LASI_STATUS, &val1);
2027 DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2028
2029 bnx2x_mdio45_read(bp, ext_phy_addr,
2030 EXT_PHY_OPT_PMA_PMD_DEVAD,
2031 EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
2032 bnx2x_mdio45_read(bp, ext_phy_addr,
2033 EXT_PHY_OPT_PCS_DEVAD,
2034 EXT_PHY_OPT_PCS_STATUS, &pcs_status);
2035 bnx2x_mdio45_read(bp, ext_phy_addr,
2036 EXT_PHY_AUTO_NEG_DEVAD,
2037 EXT_PHY_OPT_AN_LINK_STATUS, &val2);
2038
2039 DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x"
2040 " pcs_status 0x%x 1Gbps link_status 0x%x 0x%x\n",
2041 rx_sd, pcs_status, val2, (val2 & (1<<1)));
2042 /* link is up if both bit 0 of pmd_rx_sd and
2043 * bit 0 of pcs_status are set, or if the autoneg bit
2044 1 is set
2045 */
2046 val1 = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
2047 break;
2048
2049 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2050 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
2051
2052 /* clear the interrupt LASI status register */
2053 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2054 ext_phy_addr,
2055 EXT_PHY_KR_PCS_DEVAD,
2056 EXT_PHY_KR_LASI_STATUS, &val2);
2057 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2058 ext_phy_addr,
2059 EXT_PHY_KR_PCS_DEVAD,
2060 EXT_PHY_KR_LASI_STATUS, &val1);
2061 DP(NETIF_MSG_LINK, "KR LASI status 0x%x->0x%x\n",
2062 val2, val1);
2063 /* Check the LASI */
2064 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2065 ext_phy_addr,
2066 EXT_PHY_KR_PMA_PMD_DEVAD,
2067 0x9003, &val2);
2068 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2069 ext_phy_addr,
2070 EXT_PHY_KR_PMA_PMD_DEVAD,
2071 0x9003, &val1);
2072 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x->0x%x\n",
2073 val2, val1);
2074 /* Check the link status */
2075 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2076 ext_phy_addr,
2077 EXT_PHY_KR_PCS_DEVAD,
2078 EXT_PHY_KR_PCS_STATUS, &val2);
2079 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
2080 /* Check the link status on 1.1.2 */
2081 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2082 ext_phy_addr,
2083 EXT_PHY_OPT_PMA_PMD_DEVAD,
2084 EXT_PHY_KR_STATUS, &val2);
2085 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2086 ext_phy_addr,
2087 EXT_PHY_OPT_PMA_PMD_DEVAD,
2088 EXT_PHY_KR_STATUS, &val1);
2089 DP(NETIF_MSG_LINK,
2090 "KR PMA status 0x%x->0x%x\n", val2, val1);
2091 val1 = ((val1 & 4) == 4);
2092 /* If 1G was requested assume the link is up */
2093 if (!(bp->req_autoneg & AUTONEG_SPEED) &&
2094 (bp->req_line_speed == SPEED_1000))
2095 val1 = 1;
2096 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
2097 break;
2098
2099 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2100 bnx2x_mdio45_read(bp, ext_phy_addr,
2101 EXT_PHY_OPT_PMA_PMD_DEVAD,
2102 EXT_PHY_OPT_LASI_STATUS, &val2);
2103 bnx2x_mdio45_read(bp, ext_phy_addr,
2104 EXT_PHY_OPT_PMA_PMD_DEVAD,
2105 EXT_PHY_OPT_LASI_STATUS, &val1);
2106 DP(NETIF_MSG_LINK,
2107 "10G-base-T LASI status 0x%x->0x%x\n", val2, val1);
2108 bnx2x_mdio45_read(bp, ext_phy_addr,
2109 EXT_PHY_OPT_PMA_PMD_DEVAD,
2110 EXT_PHY_KR_STATUS, &val2);
2111 bnx2x_mdio45_read(bp, ext_phy_addr,
2112 EXT_PHY_OPT_PMA_PMD_DEVAD,
2113 EXT_PHY_KR_STATUS, &val1);
2114 DP(NETIF_MSG_LINK,
2115 "10G-base-T PMA status 0x%x->0x%x\n", val2, val1);
2116 val1 = ((val1 & 4) == 4);
2117 /* if link is up
2118 * print the AN outcome of the SFX7101 PHY
2119 */
2120 if (val1) {
2121 bnx2x_mdio45_read(bp, ext_phy_addr,
2122 EXT_PHY_KR_AUTO_NEG_DEVAD,
2123 0x21, &val2);
2124 DP(NETIF_MSG_LINK,
2125 "SFX7101 AN status 0x%x->%s\n", val2,
2126 (val2 & (1<<14)) ? "Master" : "Slave");
2127 }
2128 break;
2129
2130 default:
2131 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2132 bp->ext_phy_config);
2133 val1 = 0;
2134 break;
2135 }
2136
2137 } else { /* SerDes */
2138 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
2139 switch (ext_phy_type) {
2140 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2141 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2142 val1 = 1;
2143 break;
2144
2145 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2146 DP(NETIF_MSG_LINK, "SerDes 5482\n");
2147 val1 = 1;
2148 break;
2149
2150 default:
2151 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
2152 bp->ext_phy_config);
2153 val1 = 0;
2154 break;
2155 }
2156 }
2157
2158 return val1;
2159}
2160
2161static void bnx2x_bmac_enable(struct bnx2x *bp, int is_lb)
2162{
2163 int port = bp->port;
2164 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2165 NIG_REG_INGRESS_BMAC0_MEM;
2166 u32 wb_write[2];
2167 u32 val;
2168
2169 DP(NETIF_MSG_LINK, "enabling BigMAC\n");
2170 /* reset and unreset the BigMac */
2171 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2172 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2173 msleep(5);
2174 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2175 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2176
2177 /* enable access for bmac registers */
2178 NIG_WR(NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2179
2180 /* XGXS control */
2181 wb_write[0] = 0x3c;
2182 wb_write[1] = 0;
2183 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2184 wb_write, 2);
2185
2186 /* tx MAC SA */
2187 wb_write[0] = ((bp->dev->dev_addr[2] << 24) |
2188 (bp->dev->dev_addr[3] << 16) |
2189 (bp->dev->dev_addr[4] << 8) |
2190 bp->dev->dev_addr[5]);
2191 wb_write[1] = ((bp->dev->dev_addr[0] << 8) |
2192 bp->dev->dev_addr[1]);
2193 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
2194 wb_write, 2);
2195
2196 /* tx control */
2197 val = 0xc0;
2198 if (bp->flow_ctrl & FLOW_CTRL_TX)
2199 val |= 0x800000;
2200 wb_write[0] = val;
2201 wb_write[1] = 0;
2202 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_write, 2);
2203
2204 /* set tx mtu */
2205 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; /* -CRC */
2206 wb_write[1] = 0;
2207 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_write, 2);
2208
2209 /* mac control */
2210 val = 0x3;
2211 if (is_lb) {
2212 val |= 0x4;
2213 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2214 }
2215 wb_write[0] = val;
2216 wb_write[1] = 0;
2217 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
2218 wb_write, 2);
2219
2220 /* rx control set to don't strip crc */
2221 val = 0x14;
2222 if (bp->flow_ctrl & FLOW_CTRL_RX)
2223 val |= 0x20;
2224 wb_write[0] = val;
2225 wb_write[1] = 0;
2226 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_write, 2);
2227
2228 /* set rx mtu */
2229 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2230 wb_write[1] = 0;
2231 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_write, 2);
2232
2233 /* set cnt max size */
2234 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; /* -VLAN */
2235 wb_write[1] = 0;
2236 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
2237 wb_write, 2);
2238
2239 /* configure safc */
2240 wb_write[0] = 0x1000200;
2241 wb_write[1] = 0;
2242 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2243 wb_write, 2);
2244
2245 /* fix for emulation */
2246 if (CHIP_REV(bp) == CHIP_REV_EMUL) {
2247 wb_write[0] = 0xf000;
2248 wb_write[1] = 0;
2249 REG_WR_DMAE(bp,
2250 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
2251 wb_write, 2);
2252 }
2253
2254 /* reset old bmac stats */
2255 memset(&bp->old_bmac, 0, sizeof(struct bmac_stats));
2256
2257 NIG_WR(NIG_REG_XCM0_OUT_EN + port*4, 0x0);
2258
2259 /* select XGXS */
2260 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2261 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2262
2263 /* disable the NIG in/out to the emac */
2264 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2265 NIG_WR(NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2266 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2267
2268 /* enable the NIG in/out to the bmac */
2269 NIG_WR(NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2270
2271 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2272 val = 0;
2273 if (bp->flow_ctrl & FLOW_CTRL_TX)
2274 val = 1;
2275 NIG_WR(NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2276 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2277
2278 bp->phy_flags |= PHY_BMAC_FLAG;
2279
2280 bp->stats_state = STATS_STATE_ENABLE;
2281}
2282
2283static void bnx2x_bmac_rx_disable(struct bnx2x *bp)
2284{
2285 int port = bp->port;
2286 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2287 NIG_REG_INGRESS_BMAC0_MEM;
2288 u32 wb_write[2];
2289
2290 /* Only if the bmac is out of reset */
2291 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2292 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)) {
2293 /* Clear Rx Enable bit in BMAC_CONTROL register */
2294#ifdef BNX2X_DMAE_RD
2295 bnx2x_read_dmae(bp, bmac_addr +
2296 BIGMAC_REGISTER_BMAC_CONTROL, 2);
2297 wb_write[0] = *bnx2x_sp(bp, wb_data[0]);
2298 wb_write[1] = *bnx2x_sp(bp, wb_data[1]);
2299#else
2300 wb_write[0] = REG_RD(bp,
2301 bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL);
2302 wb_write[1] = REG_RD(bp,
2303 bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL + 4);
2304#endif
2305 wb_write[0] &= ~BMAC_CONTROL_RX_ENABLE;
2306 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
2307 wb_write, 2);
2308 msleep(1);
2309 }
2310}
2311
2312static void bnx2x_emac_enable(struct bnx2x *bp)
2313{
2314 int port = bp->port;
2315 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2316 u32 val;
2317 int timeout;
2318
2319 DP(NETIF_MSG_LINK, "enabling EMAC\n");
2320 /* reset and unreset the emac core */
2321 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2322 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2323 msleep(5);
2324 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2325 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2326
2327 /* enable emac and not bmac */
2328 NIG_WR(NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2329
2330 /* for paladium */
2331 if (CHIP_REV(bp) == CHIP_REV_EMUL) {
2332 /* Use lane 1 (of lanes 0-3) */
2333 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2334 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2335 }
2336 /* for fpga */
2337 else if (CHIP_REV(bp) == CHIP_REV_FPGA) {
2338 /* Use lane 1 (of lanes 0-3) */
2339 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2340 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2341 }
2342 /* ASIC */
2343 else {
2344 if (bp->phy_flags & PHY_XGXS_FLAG) {
2345 DP(NETIF_MSG_LINK, "XGXS\n");
2346 /* select the master lanes (out of 0-3) */
2347 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4,
2348 bp->ser_lane);
2349 /* select XGXS */
2350 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2351
2352 } else { /* SerDes */
2353 DP(NETIF_MSG_LINK, "SerDes\n");
2354 /* select SerDes */
2355 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2356 }
2357 }
2358
2359 /* enable emac */
2360 NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 1);
2361
2362 /* init emac - use read-modify-write */
2363 /* self clear reset */
2364 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2365 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
2366
2367 timeout = 200;
2368 while (val & EMAC_MODE_RESET) {
2369 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2370 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
2371 if (!timeout) {
2372 BNX2X_ERR("EMAC timeout!\n");
2373 break;
2374 }
2375 timeout--;
2376 }
2377
2378 /* reset tx part */
2379 EMAC_WR(EMAC_REG_EMAC_TX_MODE, EMAC_TX_MODE_RESET);
2380
2381 timeout = 200;
2382 while (val & EMAC_TX_MODE_RESET) {
2383 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_TX_MODE);
2384 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
2385 if (!timeout) {
2386 BNX2X_ERR("EMAC timeout!\n");
2387 break;
2388 }
2389 timeout--;
2390 }
2391
2392 if (CHIP_REV_IS_SLOW(bp)) {
2393 /* config GMII mode */
2394 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2395 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
2396
2397 } else { /* ASIC */
2398 /* pause enable/disable */
2399 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
2400 EMAC_RX_MODE_FLOW_EN);
2401 if (bp->flow_ctrl & FLOW_CTRL_RX)
2402 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
2403 EMAC_RX_MODE_FLOW_EN);
2404
2405 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
2406 EMAC_TX_MODE_EXT_PAUSE_EN);
2407 if (bp->flow_ctrl & FLOW_CTRL_TX)
2408 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
2409 EMAC_TX_MODE_EXT_PAUSE_EN);
2410 }
2411
2412 /* KEEP_VLAN_TAG, promiscuous */
2413 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
2414 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
2415 EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
2416
2417 /* identify magic packets */
2418 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2419 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_MPKT));
2420
2421 /* enable emac for jumbo packets */
2422 EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE,
2423 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
2424 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); /* -VLAN */
2425
2426 /* strip CRC */
2427 NIG_WR(NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2428
2429 val = ((bp->dev->dev_addr[0] << 8) |
2430 bp->dev->dev_addr[1]);
2431 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
2432
2433 val = ((bp->dev->dev_addr[2] << 24) |
2434 (bp->dev->dev_addr[3] << 16) |
2435 (bp->dev->dev_addr[4] << 8) |
2436 bp->dev->dev_addr[5]);
2437 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
2438
2439 /* disable the NIG in/out to the bmac */
2440 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2441 NIG_WR(NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2442 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2443
2444 /* enable the NIG in/out to the emac */
2445 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2446 val = 0;
2447 if (bp->flow_ctrl & FLOW_CTRL_TX)
2448 val = 1;
2449 NIG_WR(NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2450 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2451
2452 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
2453 /* take the BigMac out of reset */
2454 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2455 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2456
2457 /* enable access for bmac registers */
2458 NIG_WR(NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2459 }
2460
2461 bp->phy_flags |= PHY_EMAC_FLAG;
2462
2463 bp->stats_state = STATS_STATE_ENABLE;
2464}
2465
2466static void bnx2x_emac_program(struct bnx2x *bp)
2467{
2468 u16 mode = 0;
2469 int port = bp->port;
2470
2471 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2472 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2473 (EMAC_MODE_25G_MODE |
2474 EMAC_MODE_PORT_MII_10M |
2475 EMAC_MODE_HALF_DUPLEX));
2476 switch (bp->line_speed) {
2477 case SPEED_10:
2478 mode |= EMAC_MODE_PORT_MII_10M;
2479 break;
2480
2481 case SPEED_100:
2482 mode |= EMAC_MODE_PORT_MII;
2483 break;
2484
2485 case SPEED_1000:
2486 mode |= EMAC_MODE_PORT_GMII;
2487 break;
2488
2489 case SPEED_2500:
2490 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2491 break;
2492
2493 default:
2494 /* 10G not valid for EMAC */
2495 BNX2X_ERR("Invalid line_speed 0x%x\n", bp->line_speed);
2496 break;
2497 }
2498
2499 if (bp->duplex == DUPLEX_HALF)
2500 mode |= EMAC_MODE_HALF_DUPLEX;
2501 bnx2x_bits_en(bp, GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2502 mode);
2503
2504 bnx2x_leds_set(bp, bp->line_speed);
2505}
2506
2507static void bnx2x_set_sgmii_tx_driver(struct bnx2x *bp)
2508{
2509 u32 lp_up2;
2510 u32 tx_driver;
2511
2512 /* read precomp */
2513 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
2514 bnx2x_mdio22_read(bp, MDIO_OVER_1G_LP_UP2, &lp_up2);
2515
2516 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_TX0);
2517 bnx2x_mdio22_read(bp, MDIO_TX0_TX_DRIVER, &tx_driver);
2518
2519 /* bits [10:7] at lp_up2, positioned at [15:12] */
2520 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2521 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2522 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2523
2524 if ((lp_up2 != 0) &&
2525 (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) {
2526 /* replace tx_driver bits [15:12] */
2527 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2528 tx_driver |= lp_up2;
2529 bnx2x_mdio22_write(bp, MDIO_TX0_TX_DRIVER, tx_driver);
2530 }
2531}
2532
2533static void bnx2x_pbf_update(struct bnx2x *bp)
2534{
2535 int port = bp->port;
2536 u32 init_crd, crd;
2537 u32 count = 1000;
2538 u32 pause = 0;
2539
2540 /* disable port */
2541 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2542
2543 /* wait for init credit */
2544 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2545 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2546 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2547
2548 while ((init_crd != crd) && count) {
2549 msleep(5);
2550
2551 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2552 count--;
2553 }
2554 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2555 if (init_crd != crd)
2556 BNX2X_ERR("BUG! init_crd 0x%x != crd 0x%x\n", init_crd, crd);
2557
2558 if (bp->flow_ctrl & FLOW_CTRL_RX)
2559 pause = 1;
2560 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, pause);
2561 if (pause) {
2562 /* update threshold */
2563 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2564 /* update init credit */
2565 init_crd = 778; /* (800-18-4) */
2566
2567 } else {
2568 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)/16;
2569
2570 /* update threshold */
2571 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2572 /* update init credit */
2573 switch (bp->line_speed) {
2574 case SPEED_10:
2575 case SPEED_100:
2576 case SPEED_1000:
2577 init_crd = thresh + 55 - 22;
2578 break;
2579
2580 case SPEED_2500:
2581 init_crd = thresh + 138 - 22;
2582 break;
2583
2584 case SPEED_10000:
2585 init_crd = thresh + 553 - 22;
2586 break;
2587
2588 default:
2589 BNX2X_ERR("Invalid line_speed 0x%x\n",
2590 bp->line_speed);
2591 break;
2592 }
2593 }
2594 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2595 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2596 bp->line_speed, init_crd);
2597
2598 /* probe the credit changes */
2599 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2600 msleep(5);
2601 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2602
2603 /* enable port */
2604 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2605}
2606
2607static void bnx2x_update_mng(struct bnx2x *bp)
2608{
2609 if (!nomcp)
2610 SHMEM_WR(bp, port_mb[bp->port].link_status,
2611 bp->link_status);
2612}
2613
2614static void bnx2x_link_report(struct bnx2x *bp)
2615{
2616 if (bp->link_up) {
2617 netif_carrier_on(bp->dev);
2618 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
2619
2620 printk("%d Mbps ", bp->line_speed);
2621
2622 if (bp->duplex == DUPLEX_FULL)
2623 printk("full duplex");
2624 else
2625 printk("half duplex");
2626
2627 if (bp->flow_ctrl) {
2628 if (bp->flow_ctrl & FLOW_CTRL_RX) {
2629 printk(", receive ");
2630 if (bp->flow_ctrl & FLOW_CTRL_TX)
2631 printk("& transmit ");
2632 } else {
2633 printk(", transmit ");
2634 }
2635 printk("flow control ON");
2636 }
2637 printk("\n");
2638
2639 } else { /* link_down */
2640 netif_carrier_off(bp->dev);
2641 printk(KERN_INFO PFX "%s NIC Link is Down\n", bp->dev->name);
2642 }
2643}
2644
2645static void bnx2x_link_up(struct bnx2x *bp)
2646{
2647 int port = bp->port;
2648
2649 /* PBF - link up */
2650 bnx2x_pbf_update(bp);
2651
2652 /* disable drain */
2653 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
2654
2655 /* update shared memory */
2656 bnx2x_update_mng(bp);
2657
2658 /* indicate link up */
2659 bnx2x_link_report(bp);
2660}
2661
2662static void bnx2x_link_down(struct bnx2x *bp)
2663{
2664 int port = bp->port;
2665
2666 /* notify stats */
2667 if (bp->stats_state != STATS_STATE_DISABLE) {
2668 bp->stats_state = STATS_STATE_STOP;
2669 DP(BNX2X_MSG_STATS, "stats_state - STOP\n");
2670 }
2671
2672 /* indicate no mac active */
2673 bp->phy_flags &= ~(PHY_BMAC_FLAG | PHY_EMAC_FLAG);
2674
2675 /* update shared memory */
2676 bnx2x_update_mng(bp);
2677
2678 /* activate nig drain */
2679 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
2680
2681 /* reset BigMac */
2682 bnx2x_bmac_rx_disable(bp);
2683 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2684 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2685
2686 /* indicate link down */
2687 bnx2x_link_report(bp);
2688}
2689
2690static void bnx2x_init_mac_stats(struct bnx2x *bp);
2691
2692/* This function is called upon link interrupt */
2693static void bnx2x_link_update(struct bnx2x *bp)
2694{
2695 int port = bp->port;
2696 int i;
2697 u32 gp_status;
2698 int link_10g;
2699
2700 DP(NETIF_MSG_LINK, "port %x, %s, int_status 0x%x,"
2701 " int_mask 0x%x, saved_mask 0x%x, MI_INT %x, SERDES_LINK %x,"
2702 " 10G %x, XGXS_LINK %x\n", port,
2703 (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
2704 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4),
2705 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), bp->nig_mask,
2706 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2707 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c),
2708 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2709 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)
2710 );
2711
2712 might_sleep();
2713 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_GP_STATUS);
2714 /* avoid fast toggling */
2715 for (i = 0; i < 10; i++) {
2716 msleep(10);
2717 bnx2x_mdio22_read(bp, MDIO_GP_STATUS_TOP_AN_STATUS1,
2718 &gp_status);
2719 }
2720
2721 bnx2x_link_settings_status(bp, gp_status);
2722
2723 /* anything 10 and over uses the bmac */
2724 link_10g = ((bp->line_speed >= SPEED_10000) &&
2725 (bp->line_speed <= SPEED_16000));
2726
2727 bnx2x_link_int_ack(bp, link_10g);
2728
2729 /* link is up only if both local phy and external phy are up */
2730 bp->link_up = (bp->phy_link_up && bnx2x_ext_phy_is_link_up(bp));
2731 if (bp->link_up) {
2732 if (link_10g) {
2733 bnx2x_bmac_enable(bp, 0);
2734 bnx2x_leds_set(bp, SPEED_10000);
2735
2736 } else {
2737 bnx2x_emac_enable(bp);
2738 bnx2x_emac_program(bp);
2739
2740 /* AN complete? */
2741 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
2742 if (!(bp->phy_flags & PHY_SGMII_FLAG))
2743 bnx2x_set_sgmii_tx_driver(bp);
2744 }
2745 }
2746 bnx2x_link_up(bp);
2747
2748 } else { /* link down */
2749 bnx2x_leds_unset(bp);
2750 bnx2x_link_down(bp);
2751 }
2752
2753 bnx2x_init_mac_stats(bp);
2754}
2755
2756/*
2757 * Init service functions
2758 */
2759
2760static void bnx2x_set_aer_mmd(struct bnx2x *bp)
2761{
2762 u16 offset = (bp->phy_flags & PHY_XGXS_FLAG) ?
2763 (bp->phy_addr + bp->ser_lane) : 0;
2764
2765 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK);
2766 bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
2767}
2768
2769static void bnx2x_set_master_ln(struct bnx2x *bp)
2770{
2771 u32 new_master_ln;
2772
2773 /* set the master_ln for AN */
2774 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2775 bnx2x_mdio22_read(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2776 &new_master_ln);
2777 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2778 (new_master_ln | bp->ser_lane));
2779}
2780
2781static void bnx2x_reset_unicore(struct bnx2x *bp)
2782{
2783 u32 mii_control;
2784 int i;
2785
2786 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2787 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
2788 /* reset the unicore */
2789 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2790 (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
2791
2792 /* wait for the reset to self clear */
2793 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
2794 udelay(5);
2795
2796 /* the reset erased the previous bank value */
2797 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2798 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2799 &mii_control);
2800
2801 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
2802 udelay(5);
2803 return;
2804 }
2805 }
2806
2807 BNX2X_ERR("BUG! %s (0x%x) is still in reset!\n",
2808 (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
2809 bp->phy_addr);
2810}
2811
2812static void bnx2x_set_swap_lanes(struct bnx2x *bp)
2813{
2814 /* Each two bits represents a lane number:
2815 No swap is 0123 => 0x1b no need to enable the swap */
2816
2817 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2818 if (bp->rx_lane_swap != 0x1b) {
2819 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP,
2820 (bp->rx_lane_swap |
2821 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
2822 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
2823 } else {
2824 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
2825 }
2826
2827 if (bp->tx_lane_swap != 0x1b) {
2828 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP,
2829 (bp->tx_lane_swap |
2830 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
2831 } else {
2832 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
2833 }
2834}
2835
2836static void bnx2x_set_parallel_detection(struct bnx2x *bp)
2837{
2838 u32 control2;
2839
2840 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2841 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2842 &control2);
2843
2844 if (bp->autoneg & AUTONEG_PARALLEL) {
2845 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2846 } else {
2847 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2848 }
2849 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2850 control2);
2851
2852 if (bp->phy_flags & PHY_XGXS_FLAG) {
2853 DP(NETIF_MSG_LINK, "XGXS\n");
2854 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_10G_PARALLEL_DETECT);
2855
2856 bnx2x_mdio22_write(bp,
2857 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
2858 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
2859
2860 bnx2x_mdio22_read(bp,
2861 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2862 &control2);
2863
2864 if (bp->autoneg & AUTONEG_PARALLEL) {
2865 control2 |=
2866 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2867 } else {
2868 control2 &=
2869 ~MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2870 }
2871 bnx2x_mdio22_write(bp,
2872 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2873 control2);
2874
2875 /* Disable parallel detection of HiG */
2876 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2877 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
2878 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
2879 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
2880 }
2881}
2882
2883static void bnx2x_set_autoneg(struct bnx2x *bp)
2884{
2885 u32 reg_val;
2886
2887 /* CL37 Autoneg */
2888 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2889 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2890 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2891 (bp->autoneg & AUTONEG_CL37)) {
2892 /* CL37 Autoneg Enabled */
2893 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
2894 } else {
2895 /* CL37 Autoneg Disabled */
2896 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2897 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
2898 }
2899 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2900
2901 /* Enable/Disable Autodetection */
2902 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2903 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
2904 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
2905
2906 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2907 (bp->autoneg & AUTONEG_SGMII_FIBER_AUTODET)) {
2908 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2909 } else {
2910 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2911 }
2912 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
2913
2914 /* Enable TetonII and BAM autoneg */
2915 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_BAM_NEXT_PAGE);
2916 bnx2x_mdio22_read(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2917 &reg_val);
2918 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2919 (bp->autoneg & AUTONEG_CL37) && (bp->autoneg & AUTONEG_BAM)) {
2920 /* Enable BAM aneg Mode and TetonII aneg Mode */
2921 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2922 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2923 } else {
2924 /* TetonII and BAM Autoneg Disabled */
2925 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2926 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2927 }
2928 bnx2x_mdio22_write(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2929 reg_val);
2930
2931 /* Enable Clause 73 Aneg */
2932 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2933 (bp->autoneg & AUTONEG_CL73)) {
2934 /* Enable BAM Station Manager */
2935 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_USERB0);
2936 bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2937 (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2938 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2939 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));
2940
2941 /* Merge CL73 and CL37 aneg resolution */
2942 bnx2x_mdio22_read(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
2943 &reg_val);
2944 bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
2945 (reg_val |
2946 MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));
2947
2948 /* Set the CL73 AN speed */
2949 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB1);
2950 bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB1_AN_ADV2, &reg_val);
2951 /* In the SerDes we support only the 1G.
2952 In the XGXS we support the 10G KX4
2953 but we currently do not support the KR */
2954 if (bp->phy_flags & PHY_XGXS_FLAG) {
2955 DP(NETIF_MSG_LINK, "XGXS\n");
2956 /* 10G KX4 */
2957 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2958 } else {
2959 DP(NETIF_MSG_LINK, "SerDes\n");
2960 /* 1000M KX */
2961 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2962 }
2963 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
2964
2965 /* CL73 Autoneg Enabled */
2966 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2967 } else {
2968 /* CL73 Autoneg Disabled */
2969 reg_val = 0;
2970 }
2971 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
2972 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2973}
2974
2975/* program SerDes, forced speed */
2976static void bnx2x_program_serdes(struct bnx2x *bp)
2977{
2978 u32 reg_val;
2979
2980 /* program duplex, disable autoneg */
2981 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2982 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2983 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2984 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
2985 if (bp->req_duplex == DUPLEX_FULL)
2986 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2987 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2988
2989 /* program speed
2990 - needed only if the speed is greater than 1G (2.5G or 10G) */
2991 if (bp->req_line_speed > SPEED_1000) {
2992 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2993 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2994 /* clearing the speed value before setting the right speed */
2995 reg_val &= ~MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK;
2996 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2997 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2998 if (bp->req_line_speed == SPEED_10000)
2999 reg_val |=
3000 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
3001 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_MISC1, reg_val);
3002 }
3003}
3004
3005static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x *bp)
3006{
3007 u32 val = 0;
3008
3009 /* configure the 48 bits for BAM AN */
3010 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
3011
3012 /* set extended capabilities */
3013 if (bp->advertising & ADVERTISED_2500baseX_Full)
3014 val |= MDIO_OVER_1G_UP1_2_5G;
3015 if (bp->advertising & ADVERTISED_10000baseT_Full)
3016 val |= MDIO_OVER_1G_UP1_10G;
3017 bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP1, val);
3018
3019 bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP3, 0);
3020}
3021
3022static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x *bp)
3023{
3024 u32 an_adv;
3025
3026 /* for AN, we are always publishing full duplex */
3027 an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3028
3029 /* resolve pause mode and advertisement
3030 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
3031 if (bp->req_autoneg & AUTONEG_FLOW_CTRL) {
3032 switch (bp->req_flow_ctrl) {
3033 case FLOW_CTRL_AUTO:
3034 if (bp->dev->mtu <= 4500) {
3035 an_adv |=
3036 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3037 bp->advertising |= (ADVERTISED_Pause |
3038 ADVERTISED_Asym_Pause);
3039 } else {
3040 an_adv |=
3041 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3042 bp->advertising |= ADVERTISED_Asym_Pause;
3043 }
3044 break;
3045
3046 case FLOW_CTRL_TX:
3047 an_adv |=
3048 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3049 bp->advertising |= ADVERTISED_Asym_Pause;
3050 break;
3051
3052 case FLOW_CTRL_RX:
3053 if (bp->dev->mtu <= 4500) {
3054 an_adv |=
3055 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3056 bp->advertising |= (ADVERTISED_Pause |
3057 ADVERTISED_Asym_Pause);
3058 } else {
3059 an_adv |=
3060 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3061 bp->advertising &= ~(ADVERTISED_Pause |
3062 ADVERTISED_Asym_Pause);
3063 }
3064 break;
3065
3066 case FLOW_CTRL_BOTH:
3067 if (bp->dev->mtu <= 4500) {
3068 an_adv |=
3069 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3070 bp->advertising |= (ADVERTISED_Pause |
3071 ADVERTISED_Asym_Pause);
3072 } else {
3073 an_adv |=
3074 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3075 bp->advertising |= ADVERTISED_Asym_Pause;
3076 }
3077 break;
3078
3079 case FLOW_CTRL_NONE:
3080 default:
3081 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3082 bp->advertising &= ~(ADVERTISED_Pause |
3083 ADVERTISED_Asym_Pause);
3084 break;
3085 }
3086 } else { /* forced mode */
3087 switch (bp->req_flow_ctrl) {
3088 case FLOW_CTRL_AUTO:
3089 DP(NETIF_MSG_LINK, "req_flow_ctrl 0x%x while"
3090 " req_autoneg 0x%x\n",
3091 bp->req_flow_ctrl, bp->req_autoneg);
3092 break;
3093
3094 case FLOW_CTRL_TX:
3095 an_adv |=
3096 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3097 bp->advertising |= ADVERTISED_Asym_Pause;
3098 break;
3099
3100 case FLOW_CTRL_RX:
3101 case FLOW_CTRL_BOTH:
3102 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3103 bp->advertising |= (ADVERTISED_Pause |
3104 ADVERTISED_Asym_Pause);
3105 break;
3106
3107 case FLOW_CTRL_NONE:
3108 default:
3109 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3110 bp->advertising &= ~(ADVERTISED_Pause |
3111 ADVERTISED_Asym_Pause);
3112 break;
3113 }
3114 }
3115
3116 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3117 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV, an_adv);
3118}
3119
3120static void bnx2x_restart_autoneg(struct bnx2x *bp)
3121{
3122 if (bp->autoneg & AUTONEG_CL73) {
3123 /* enable and restart clause 73 aneg */
3124 u32 an_ctrl;
3125
3126 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
3127 bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3128 &an_ctrl);
3129 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3130 (an_ctrl |
3131 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
3132 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
3133
3134 } else {
3135 /* Enable and restart BAM/CL37 aneg */
3136 u32 mii_control;
3137
3138 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3139 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3140 &mii_control);
3141 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3142 (mii_control |
3143 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
3144 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
3145 }
3146}
3147
3148static void bnx2x_initialize_sgmii_process(struct bnx2x *bp)
3149{
3150 u32 control1;
3151
3152 /* in SGMII mode, the unicore is always slave */
3153 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
3154 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
3155 &control1);
3156 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
3157 /* set sgmii mode (and not fiber) */
3158 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
3159 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
3160 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
3161 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
3162 control1);
3163
3164 /* if forced speed */
3165 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3166 /* set speed, disable autoneg */
3167 u32 mii_control;
3168
3169 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3170 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3171 &mii_control);
3172 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
3173 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
3174 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
3175
3176 switch (bp->req_line_speed) {
3177 case SPEED_100:
3178 mii_control |=
3179 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
3180 break;
3181 case SPEED_1000:
3182 mii_control |=
3183 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
3184 break;
3185 case SPEED_10:
3186 /* there is nothing to set for 10M */
3187 break;
3188 default:
3189 /* invalid speed for SGMII */
3190 DP(NETIF_MSG_LINK, "Invalid req_line_speed 0x%x\n",
3191 bp->req_line_speed);
3192 break;
3193 }
3194
3195 /* setting the full duplex */
3196 if (bp->req_duplex == DUPLEX_FULL)
3197 mii_control |=
3198 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
3199 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3200 mii_control);
3201
3202 } else { /* AN mode */
3203 /* enable and restart AN */
3204 bnx2x_restart_autoneg(bp);
3205 }
3206}
3207
3208static void bnx2x_link_int_enable(struct bnx2x *bp)
3209{
3210 int port = bp->port;
3211 u32 ext_phy_type;
3212 u32 mask;
3213
3214 /* setting the status to report on link up
3215 for either XGXS or SerDes */
3216 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3217 (NIG_STATUS_XGXS0_LINK10G |
3218 NIG_STATUS_XGXS0_LINK_STATUS |
3219 NIG_STATUS_SERDES0_LINK_STATUS));
3220
3221 if (bp->phy_flags & PHY_XGXS_FLAG) {
3222 mask = (NIG_MASK_XGXS0_LINK10G |
3223 NIG_MASK_XGXS0_LINK_STATUS);
3224 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
3225 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3226 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3227 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3228 (ext_phy_type !=
3229 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
3230 mask |= NIG_MASK_MI_INT;
3231 DP(NETIF_MSG_LINK, "enabled external phy int\n");
3232 }
3233
3234 } else { /* SerDes */
3235 mask = NIG_MASK_SERDES0_LINK_STATUS;
3236 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
3237 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3238 if ((ext_phy_type !=
3239 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
3240 (ext_phy_type !=
3241 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
3242 mask |= NIG_MASK_MI_INT;
3243 DP(NETIF_MSG_LINK, "enabled external phy int\n");
3244 }
3245 }
3246 bnx2x_bits_en(bp,
3247 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3248 mask);
3249 DP(NETIF_MSG_LINK, "port %x, %s, int_status 0x%x,"
3250 " int_mask 0x%x, MI_INT %x, SERDES_LINK %x,"
3251 " 10G %x, XGXS_LINK %x\n", port,
3252 (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
3253 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4),
3254 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3255 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
3256 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c),
3257 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3258 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)
3259 );
3260}
3261
3262static void bnx2x_bcm8072_external_rom_boot(struct bnx2x *bp)
3263{
3264 u32 ext_phy_addr = ((bp->ext_phy_config &
3265 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3266 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3267 u32 fw_ver1, fw_ver2;
3268
3269 /* Need to wait 200ms after reset */
3270 msleep(200);
3271 /* Boot port from external ROM
3272 * Set ser_boot_ctl bit in the MISC_CTRL1 register
3273 */
3274 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3275 EXT_PHY_KR_PMA_PMD_DEVAD,
3276 EXT_PHY_KR_MISC_CTRL1, 0x0001);
3277
3278 /* Reset internal microprocessor */
3279 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3280 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3281 EXT_PHY_KR_ROM_RESET_INTERNAL_MP);
3282 /* set micro reset = 0 */
3283 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3284 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3285 EXT_PHY_KR_ROM_MICRO_RESET);
3286 /* Reset internal microprocessor */
3287 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3288 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3289 EXT_PHY_KR_ROM_RESET_INTERNAL_MP);
3290 /* wait for 100ms for code download via SPI port */
3291 msleep(100);
3292
3293 /* Clear ser_boot_ctl bit */
3294 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3295 EXT_PHY_KR_PMA_PMD_DEVAD,
3296 EXT_PHY_KR_MISC_CTRL1, 0x0000);
3297 /* Wait 100ms */
3298 msleep(100);
3299
3300 /* Print the PHY FW version */
3301 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, ext_phy_addr,
3302 EXT_PHY_KR_PMA_PMD_DEVAD,
3303 0xca19, &fw_ver1);
3304 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, ext_phy_addr,
3305 EXT_PHY_KR_PMA_PMD_DEVAD,
3306 0xca1a, &fw_ver2);
3307 DP(NETIF_MSG_LINK,
3308 "8072 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
3309}
3310
3311static void bnx2x_bcm8072_force_10G(struct bnx2x *bp)
3312{
3313 u32 ext_phy_addr = ((bp->ext_phy_config &
3314 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3315 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3316
3317 /* Force KR or KX */
3318 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3319 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_CTRL,
3320 0x2040);
3321 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3322 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_CTRL2,
3323 0x000b);
3324 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3325 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_PMD_CTRL,
3326 0x0000);
3327 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3328 EXT_PHY_KR_AUTO_NEG_DEVAD, EXT_PHY_KR_CTRL,
3329 0x0000);
3330}
3331
3332static void bnx2x_ext_phy_init(struct bnx2x *bp)
3333{
3334 u32 ext_phy_type;
3335 u32 ext_phy_addr;
3336 u32 cnt;
3337 u32 ctrl;
3338 u32 val = 0;
3339
3340 if (bp->phy_flags & PHY_XGXS_FLAG) {
3341 ext_phy_addr = ((bp->ext_phy_config &
3342 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3343 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3344
3345 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3346 /* Make sure that the soft reset is off (expect for the 8072:
3347 * due to the lock, it will be done inside the specific
3348 * handling)
3349 */
3350 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3351 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3352 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
3353 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)) {
3354 /* Wait for soft reset to get cleared upto 1 sec */
3355 for (cnt = 0; cnt < 1000; cnt++) {
3356 bnx2x_mdio45_read(bp, ext_phy_addr,
3357 EXT_PHY_OPT_PMA_PMD_DEVAD,
3358 EXT_PHY_OPT_CNTL, &ctrl);
3359 if (!(ctrl & (1<<15)))
3360 break;
3361 msleep(1);
3362 }
3363 DP(NETIF_MSG_LINK,
3364 "control reg 0x%x (after %d ms)\n", ctrl, cnt);
3365 }
3366
3367 switch (ext_phy_type) {
3368 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3369 DP(NETIF_MSG_LINK, "XGXS Direct\n");
3370 break;
3371
3372 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3373 DP(NETIF_MSG_LINK, "XGXS 8705\n");
3374
3375 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3376 EXT_PHY_OPT_PMA_PMD_DEVAD,
3377 EXT_PHY_OPT_PMD_MISC_CNTL,
3378 0x8288);
3379 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3380 EXT_PHY_OPT_PMA_PMD_DEVAD,
3381 EXT_PHY_OPT_PHY_IDENTIFIER,
3382 0x7fbf);
3383 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3384 EXT_PHY_OPT_PMA_PMD_DEVAD,
3385 EXT_PHY_OPT_CMU_PLL_BYPASS,
3386 0x0100);
3387 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3388 EXT_PHY_OPT_WIS_DEVAD,
3389 EXT_PHY_OPT_LASI_CNTL, 0x1);
3390 break;
3391
3392 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3393 DP(NETIF_MSG_LINK, "XGXS 8706\n");
3394
3395 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3396 /* Force speed */
3397 if (bp->req_line_speed == SPEED_10000) {
3398 DP(NETIF_MSG_LINK,
3399 "XGXS 8706 force 10Gbps\n");
3400 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3401 EXT_PHY_OPT_PMA_PMD_DEVAD,
3402 EXT_PHY_OPT_PMD_DIGITAL_CNT,
3403 0x400);
3404 } else {
3405 /* Force 1Gbps */
3406 DP(NETIF_MSG_LINK,
3407 "XGXS 8706 force 1Gbps\n");
3408
3409 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3410 EXT_PHY_OPT_PMA_PMD_DEVAD,
3411 EXT_PHY_OPT_CNTL,
3412 0x0040);
3413
3414 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3415 EXT_PHY_OPT_PMA_PMD_DEVAD,
3416 EXT_PHY_OPT_CNTL2,
3417 0x000D);
3418 }
3419
3420 /* Enable LASI */
3421 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3422 EXT_PHY_OPT_PMA_PMD_DEVAD,
3423 EXT_PHY_OPT_LASI_CNTL,
3424 0x1);
3425 } else {
3426 /* AUTONEG */
3427 /* Allow CL37 through CL73 */
3428 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3429 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3430 EXT_PHY_AUTO_NEG_DEVAD,
3431 EXT_PHY_OPT_AN_CL37_CL73,
3432 0x040c);
3433
3434 /* Enable Full-Duplex advertisment on CL37 */
3435 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3436 EXT_PHY_AUTO_NEG_DEVAD,
3437 EXT_PHY_OPT_AN_CL37_FD,
3438 0x0020);
3439 /* Enable CL37 AN */
3440 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3441 EXT_PHY_AUTO_NEG_DEVAD,
3442 EXT_PHY_OPT_AN_CL37_AN,
3443 0x1000);
3444 /* Advertise 10G/1G support */
3445 if (bp->advertising &
3446 ADVERTISED_1000baseT_Full)
3447 val = (1<<5);
3448 if (bp->advertising &
3449 ADVERTISED_10000baseT_Full)
3450 val |= (1<<7);
3451
3452 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3453 EXT_PHY_AUTO_NEG_DEVAD,
3454 EXT_PHY_OPT_AN_ADV, val);
3455 /* Enable LASI */
3456 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3457 EXT_PHY_OPT_PMA_PMD_DEVAD,
3458 EXT_PHY_OPT_LASI_CNTL,
3459 0x1);
3460
3461 /* Enable clause 73 AN */
3462 bnx2x_mdio45_write(bp, ext_phy_addr,
3463 EXT_PHY_AUTO_NEG_DEVAD,
3464 EXT_PHY_OPT_CNTL,
3465 0x1200);
3466 }
3467 break;
3468
3469 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3470 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3471 /* Wait for soft reset to get cleared upto 1 sec */
3472 for (cnt = 0; cnt < 1000; cnt++) {
3473 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
3474 ext_phy_addr,
3475 EXT_PHY_OPT_PMA_PMD_DEVAD,
3476 EXT_PHY_OPT_CNTL, &ctrl);
3477 if (!(ctrl & (1<<15)))
3478 break;
3479 msleep(1);
3480 }
3481 DP(NETIF_MSG_LINK,
3482 "8072 control reg 0x%x (after %d ms)\n",
3483 ctrl, cnt);
3484
3485 bnx2x_bcm8072_external_rom_boot(bp);
3486 DP(NETIF_MSG_LINK, "Finshed loading 8072 KR ROM\n");
3487
3488 /* enable LASI */
3489 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3490 ext_phy_addr,
3491 EXT_PHY_KR_PMA_PMD_DEVAD,
3492 0x9000, 0x0400);
3493 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3494 ext_phy_addr,
3495 EXT_PHY_KR_PMA_PMD_DEVAD,
3496 EXT_PHY_KR_LASI_CNTL, 0x0004);
3497
3498 /* If this is forced speed, set to KR or KX
3499 * (all other are not supported)
3500 */
3501 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3502 if (bp->req_line_speed == SPEED_10000) {
3503 bnx2x_bcm8072_force_10G(bp);
3504 DP(NETIF_MSG_LINK,
3505 "Forced speed 10G on 8072\n");
3506 /* unlock */
3507 bnx2x_hw_unlock(bp,
3508 HW_LOCK_RESOURCE_8072_MDIO);
3509 break;
3510 } else
3511 val = (1<<5);
3512 } else {
3513
3514 /* Advertise 10G/1G support */
3515 if (bp->advertising &
3516 ADVERTISED_1000baseT_Full)
3517 val = (1<<5);
3518 if (bp->advertising &
3519 ADVERTISED_10000baseT_Full)
3520 val |= (1<<7);
3521 }
3522 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3523 ext_phy_addr,
3524 EXT_PHY_KR_AUTO_NEG_DEVAD,
3525 0x11, val);
3526 /* Add support for CL37 ( passive mode ) I */
3527 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3528 ext_phy_addr,
3529 EXT_PHY_KR_AUTO_NEG_DEVAD,
3530 0x8370, 0x040c);
3531 /* Add support for CL37 ( passive mode ) II */
3532 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3533 ext_phy_addr,
3534 EXT_PHY_KR_AUTO_NEG_DEVAD,
3535 0xffe4, 0x20);
3536 /* Add support for CL37 ( passive mode ) III */
3537 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3538 ext_phy_addr,
3539 EXT_PHY_KR_AUTO_NEG_DEVAD,
3540 0xffe0, 0x1000);
3541 /* Restart autoneg */
3542 msleep(500);
3543 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3544 ext_phy_addr,
3545 EXT_PHY_KR_AUTO_NEG_DEVAD,
3546 EXT_PHY_KR_CTRL, 0x1200);
3547 DP(NETIF_MSG_LINK, "8072 Autoneg Restart: "
3548 "1G %ssupported 10G %ssupported\n",
3549 (val & (1<<5)) ? "" : "not ",
3550 (val & (1<<7)) ? "" : "not ");
3551
3552 /* unlock */
3553 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3554 break;
3555
3556 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3557 DP(NETIF_MSG_LINK,
3558 "Setting the SFX7101 LASI indication\n");
3559 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3560 EXT_PHY_OPT_PMA_PMD_DEVAD,
3561 EXT_PHY_OPT_LASI_CNTL, 0x1);
3562 DP(NETIF_MSG_LINK,
3563 "Setting the SFX7101 LED to blink on traffic\n");
3564 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3565 EXT_PHY_OPT_PMA_PMD_DEVAD,
3566 0xC007, (1<<3));
3567
3568 /* read modify write pause advertizing */
3569 bnx2x_mdio45_read(bp, ext_phy_addr,
3570 EXT_PHY_KR_AUTO_NEG_DEVAD,
3571 EXT_PHY_KR_AUTO_NEG_ADVERT, &val);
3572 val &= ~EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH;
3573 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3574 if (bp->advertising & ADVERTISED_Pause)
3575 val |= EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE;
3576
3577 if (bp->advertising & ADVERTISED_Asym_Pause) {
3578 val |=
3579 EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC;
3580 }
3581 DP(NETIF_MSG_LINK, "SFX7101 AN advertize 0x%x\n", val);
3582 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3583 EXT_PHY_KR_AUTO_NEG_DEVAD,
3584 EXT_PHY_KR_AUTO_NEG_ADVERT, val);
3585 /* Restart autoneg */
3586 bnx2x_mdio45_read(bp, ext_phy_addr,
3587 EXT_PHY_KR_AUTO_NEG_DEVAD,
3588 EXT_PHY_KR_CTRL, &val);
3589 val |= 0x200;
3590 bnx2x_mdio45_write(bp, ext_phy_addr,
3591 EXT_PHY_KR_AUTO_NEG_DEVAD,
3592 EXT_PHY_KR_CTRL, val);
3593 break;
3594
3595 default:
3596 BNX2X_ERR("BAD XGXS ext_phy_config 0x%x\n",
3597 bp->ext_phy_config);
3598 break;
3599 }
3600
3601 } else { /* SerDes */
3602/* ext_phy_addr = ((bp->ext_phy_config &
3603 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >>
3604 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT);
3605*/
3606 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3607 switch (ext_phy_type) {
3608 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
3609 DP(NETIF_MSG_LINK, "SerDes Direct\n");
3610 break;
3611
3612 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
3613 DP(NETIF_MSG_LINK, "SerDes 5482\n");
3614 break;
3615
3616 default:
3617 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
3618 bp->ext_phy_config);
3619 break;
3620 }
3621 }
3622}
3623
3624static void bnx2x_ext_phy_reset(struct bnx2x *bp)
3625{
3626 u32 ext_phy_type;
3627 u32 ext_phy_addr = ((bp->ext_phy_config &
3628 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3629 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3630 u32 board = (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK);
3631
3632 /* The PHY reset is controled by GPIO 1
3633 * Give it 1ms of reset pulse
3634 */
3635 if ((board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G) &&
3636 (board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G)) {
3637 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3638 MISC_REGISTERS_GPIO_OUTPUT_LOW);
3639 msleep(1);
3640 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3641 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
3642 }
3643
3644 if (bp->phy_flags & PHY_XGXS_FLAG) {
3645 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3646 switch (ext_phy_type) {
3647 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3648 DP(NETIF_MSG_LINK, "XGXS Direct\n");
3649 break;
3650
3651 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3652 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3653 DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
3654 bnx2x_mdio45_write(bp, ext_phy_addr,
3655 EXT_PHY_OPT_PMA_PMD_DEVAD,
3656 EXT_PHY_OPT_CNTL, 0xa040);
3657 break;
3658
3659 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3660 DP(NETIF_MSG_LINK, "XGXS 8072\n");
3661 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3662 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3663 ext_phy_addr,
3664 EXT_PHY_KR_PMA_PMD_DEVAD,
3665 0, 1<<15);
3666 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3667 break;
3668
3669 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3670 DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
3671 break;
3672
3673 default:
3674 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
3675 bp->ext_phy_config);
3676 break;
3677 }
3678
3679 } else { /* SerDes */
3680 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3681 switch (ext_phy_type) {
3682 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
3683 DP(NETIF_MSG_LINK, "SerDes Direct\n");
3684 break;
3685
3686 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
3687 DP(NETIF_MSG_LINK, "SerDes 5482\n");
3688 break;
3689
3690 default:
3691 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
3692 bp->ext_phy_config);
3693 break;
3694 }
3695 }
3696}
3697
3698static void bnx2x_link_initialize(struct bnx2x *bp)
3699{
3700 int port = bp->port;
3701
3702 /* disable attentions */
3703 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3704 (NIG_MASK_XGXS0_LINK_STATUS |
3705 NIG_MASK_XGXS0_LINK10G |
3706 NIG_MASK_SERDES0_LINK_STATUS |
3707 NIG_MASK_MI_INT));
3708
3709 /* Activate the external PHY */
3710 bnx2x_ext_phy_reset(bp);
3711
3712 bnx2x_set_aer_mmd(bp);
3713
3714 if (bp->phy_flags & PHY_XGXS_FLAG)
3715 bnx2x_set_master_ln(bp);
3716
3717 /* reset the SerDes and wait for reset bit return low */
3718 bnx2x_reset_unicore(bp);
3719
3720 bnx2x_set_aer_mmd(bp);
3721
3722 /* setting the masterLn_def again after the reset */
3723 if (bp->phy_flags & PHY_XGXS_FLAG) {
3724 bnx2x_set_master_ln(bp);
3725 bnx2x_set_swap_lanes(bp);
3726 }
3727
3728 /* Set Parallel Detect */
3729 if (bp->req_autoneg & AUTONEG_SPEED)
3730 bnx2x_set_parallel_detection(bp);
3731
3732 if (bp->phy_flags & PHY_XGXS_FLAG) {
3733 if (bp->req_line_speed &&
3734 bp->req_line_speed < SPEED_1000) {
3735 bp->phy_flags |= PHY_SGMII_FLAG;
3736 } else {
3737 bp->phy_flags &= ~PHY_SGMII_FLAG;
3738 }
3739 }
3740
3741 if (!(bp->phy_flags & PHY_SGMII_FLAG)) {
3742 u16 bank, rx_eq;
3743
3744 rx_eq = ((bp->serdes_config &
3745 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
3746 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
3747
3748 DP(NETIF_MSG_LINK, "setting rx eq to %d\n", rx_eq);
3749 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
3750 bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0)) {
3751 MDIO_SET_REG_BANK(bp, bank);
3752 bnx2x_mdio22_write(bp, MDIO_RX0_RX_EQ_BOOST,
3753 ((rx_eq &
3754 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
3755 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
3756 }
3757
3758 /* forced speed requested? */
3759 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3760 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3761
3762 /* disable autoneg */
3763 bnx2x_set_autoneg(bp);
3764
3765 /* program speed and duplex */
3766 bnx2x_program_serdes(bp);
3767
3768 } else { /* AN_mode */
3769 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3770
3771 /* AN enabled */
3772 bnx2x_set_brcm_cl37_advertisment(bp);
3773
3774 /* program duplex & pause advertisement (for aneg) */
3775 bnx2x_set_ieee_aneg_advertisment(bp);
3776
3777 /* enable autoneg */
3778 bnx2x_set_autoneg(bp);
3779
3780 /* enable and restart AN */
3781 bnx2x_restart_autoneg(bp);
3782 }
3783
3784 } else { /* SGMII mode */
3785 DP(NETIF_MSG_LINK, "SGMII\n");
3786
3787 bnx2x_initialize_sgmii_process(bp);
3788 }
3789
3790 /* init ext phy and enable link state int */
3791 bnx2x_ext_phy_init(bp);
3792
3793 /* enable the interrupt */
3794 bnx2x_link_int_enable(bp);
3795}
3796
3797static void bnx2x_phy_deassert(struct bnx2x *bp)
3798{
3799 int port = bp->port;
3800 u32 val;
3801
3802 if (bp->phy_flags & PHY_XGXS_FLAG) {
3803 DP(NETIF_MSG_LINK, "XGXS\n");
3804 val = XGXS_RESET_BITS;
3805
3806 } else { /* SerDes */
3807 DP(NETIF_MSG_LINK, "SerDes\n");
3808 val = SERDES_RESET_BITS;
3809 }
3810
3811 val = val << (port*16);
3812
3813 /* reset and unreset the SerDes/XGXS */
3814 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3815 msleep(5);
3816 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3817}
3818
3819static int bnx2x_phy_init(struct bnx2x *bp)
3820{
3821 DP(NETIF_MSG_LINK, "started\n");
3822 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
3823 bp->phy_flags |= PHY_EMAC_FLAG;
3824 bp->link_up = 1;
3825 bp->line_speed = SPEED_10000;
3826 bp->duplex = DUPLEX_FULL;
3827 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + bp->port*4, 0);
3828 bnx2x_emac_enable(bp);
3829 bnx2x_link_report(bp);
3830 return 0;
3831
3832 } else if (CHIP_REV(bp) == CHIP_REV_EMUL) {
3833 bp->phy_flags |= PHY_BMAC_FLAG;
3834 bp->link_up = 1;
3835 bp->line_speed = SPEED_10000;
3836 bp->duplex = DUPLEX_FULL;
3837 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + bp->port*4, 0);
3838 bnx2x_bmac_enable(bp, 0);
3839 bnx2x_link_report(bp);
3840 return 0;
3841
3842 } else {
3843 bnx2x_phy_deassert(bp);
3844 bnx2x_link_initialize(bp);
3845 }
3846
3847 return 0;
3848}
3849
3850static void bnx2x_link_reset(struct bnx2x *bp)
3851{
3852 int port = bp->port;
3853 u32 board = (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK);
3854
3855 /* update shared memory */
3856 bp->link_status = 0;
3857 bnx2x_update_mng(bp);
3858
3859 /* disable attentions */
3860 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3861 (NIG_MASK_XGXS0_LINK_STATUS |
3862 NIG_MASK_XGXS0_LINK10G |
3863 NIG_MASK_SERDES0_LINK_STATUS |
3864 NIG_MASK_MI_INT));
3865
3866 /* activate nig drain */
3867 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3868
3869 /* disable nig egress interface */
3870 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0);
3871 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
3872
3873 /* Stop BigMac rx */
3874 bnx2x_bmac_rx_disable(bp);
3875
3876 /* disable emac */
3877 NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 0);
3878
3879 msleep(10);
3880
3881 /* The PHY reset is controled by GPIO 1
3882 * Hold it as output low
3883 */
3884 if ((board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G) &&
3885 (board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G)) {
3886 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3887 MISC_REGISTERS_GPIO_OUTPUT_LOW);
3888 DP(NETIF_MSG_LINK, "reset external PHY\n");
3889 }
3890
3891 /* reset the SerDes/XGXS */
3892 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3893 (0x1ff << (port*16)));
3894
3895 /* reset BigMac */
3896 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3897 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3898
3899 /* disable nig ingress interface */
3900 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0);
3901 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0);
3902
3903 /* set link down */
3904 bp->link_up = 0;
3905}
3906
3907#ifdef BNX2X_XGXS_LB
3908static void bnx2x_set_xgxs_loopback(struct bnx2x *bp, int is_10g)
3909{
3910 int port = bp->port;
3911
3912 if (is_10g) {
3913 u32 md_devad;
3914
3915 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3916
3917 /* change the uni_phy_addr in the nig */
3918 REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18),
3919 &md_devad);
3920 NIG_WR(NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3921
3922 /* change the aer mmd */
3923 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK);
3924 bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x2800);
3925
3926 /* config combo IEEE0 control reg for loopback */
3927 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
3928 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3929 0x6041);
3930
3931 /* set aer mmd back */
3932 bnx2x_set_aer_mmd(bp);
3933
3934 /* and md_devad */
3935 NIG_WR(NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3936
3937 } else {
3938 u32 mii_control;
3939
3940 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3941
3942 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3943 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3944 &mii_control);
3945 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3946 (mii_control |
3947 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
3948 }
3949}
3950#endif
3951
3952/* end of PHY/MAC */
3953
3954/* slow path */
3955
3956/*
3957 * General service functions
3958 */
3959
3960/* the slow path queue is odd since completions arrive on the fastpath ring */
3961static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3962 u32 data_hi, u32 data_lo, int common)
3963{
3964 int port = bp->port;
3965
3966 DP(NETIF_MSG_TIMER,
3967 "spe (%x:%x) command %d hw_cid %x data (%x:%x) left %x\n",
3968 (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
3969 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
3970 HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
3971
3972#ifdef BNX2X_STOP_ON_ERROR
3973 if (unlikely(bp->panic))
3974 return -EIO;
3975#endif
3976
3977 spin_lock(&bp->spq_lock);
3978
3979 if (!bp->spq_left) {
3980 BNX2X_ERR("BUG! SPQ ring full!\n");
3981 spin_unlock(&bp->spq_lock);
3982 bnx2x_panic();
3983 return -EBUSY;
3984 }
3985
3986 /* CID needs port number to be encoded int it */
3987 bp->spq_prod_bd->hdr.conn_and_cmd_data =
3988 cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
3989 HW_CID(bp, cid)));
3990 bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
3991 if (common)
3992 bp->spq_prod_bd->hdr.type |=
3993 cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
3994
3995 bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
3996 bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
3997
3998 bp->spq_left--;
3999
4000 if (bp->spq_prod_bd == bp->spq_last_bd) {
4001 bp->spq_prod_bd = bp->spq;
4002 bp->spq_prod_idx = 0;
4003 DP(NETIF_MSG_TIMER, "end of spq\n");
4004
4005 } else {
4006 bp->spq_prod_bd++;
4007 bp->spq_prod_idx++;
4008 }
4009
4010 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(port),
4011 bp->spq_prod_idx);
4012
4013 spin_unlock(&bp->spq_lock);
4014 return 0;
4015}
4016
4017/* acquire split MCP access lock register */
4018static int bnx2x_lock_alr(struct bnx2x *bp)
4019{
4020 int rc = 0;
4021 u32 i, j, val;
4022
4023 might_sleep();
4024 i = 100;
4025 for (j = 0; j < i*10; j++) {
4026 val = (1UL << 31);
4027 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
4028 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
4029 if (val & (1L << 31))
4030 break;
4031
4032 msleep(5);
4033 }
4034
4035 if (!(val & (1L << 31))) {
4036 BNX2X_ERR("Cannot acquire nvram interface\n");
4037
4038 rc = -EBUSY;
4039 }
4040
4041 return rc;
4042}
4043
4044/* Release split MCP access lock register */
4045static void bnx2x_unlock_alr(struct bnx2x *bp)
4046{
4047 u32 val = 0;
4048
4049 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
4050}
4051
4052static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
4053{
4054 struct host_def_status_block *def_sb = bp->def_status_blk;
4055 u16 rc = 0;
4056
4057 barrier(); /* status block is written to by the chip */
4058
4059 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4060 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4061 rc |= 1;
4062 }
4063 if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
4064 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
4065 rc |= 2;
4066 }
4067 if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
4068 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
4069 rc |= 4;
4070 }
4071 if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
4072 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
4073 rc |= 8;
4074 }
4075 if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
4076 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
4077 rc |= 16;
4078 }
4079 return rc;
4080}
4081
4082/*
4083 * slow path service functions
4084 */
4085
4086static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
4087{
4088 int port = bp->port;
4089 u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_PORT_BASE * port) * 8;
4090 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4091 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4092 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
4093 NIG_REG_MASK_INTERRUPT_PORT0;
4094
4095 if (~bp->aeu_mask & (asserted & 0xff))
4096 BNX2X_ERR("IGU ERROR\n");
4097 if (bp->attn_state & asserted)
4098 BNX2X_ERR("IGU ERROR\n");
4099
4100 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
4101 bp->aeu_mask, asserted);
4102 bp->aeu_mask &= ~(asserted & 0xff);
4103 DP(NETIF_MSG_HW, "after masking: aeu_mask %x\n", bp->aeu_mask);
4104
4105 REG_WR(bp, aeu_addr, bp->aeu_mask);
4106
4107 bp->attn_state |= asserted;
4108
4109 if (asserted & ATTN_HARD_WIRED_MASK) {
4110 if (asserted & ATTN_NIG_FOR_FUNC) {
4111
4112 /* save nig interrupt mask */
4113 bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
4114 REG_WR(bp, nig_int_mask_addr, 0);
4115
4116 bnx2x_link_update(bp);
4117
4118 /* handle unicore attn? */
4119 }
4120 if (asserted & ATTN_SW_TIMER_4_FUNC)
4121 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4122
4123 if (asserted & GPIO_2_FUNC)
4124 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4125
4126 if (asserted & GPIO_3_FUNC)
4127 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4128
4129 if (asserted & GPIO_4_FUNC)
4130 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4131
4132 if (port == 0) {
4133 if (asserted & ATTN_GENERAL_ATTN_1) {
4134 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4135 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4136 }
4137 if (asserted & ATTN_GENERAL_ATTN_2) {
4138 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4139 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4140 }
4141 if (asserted & ATTN_GENERAL_ATTN_3) {
4142 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4143 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4144 }
4145 } else {
4146 if (asserted & ATTN_GENERAL_ATTN_4) {
4147 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4148 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4149 }
4150 if (asserted & ATTN_GENERAL_ATTN_5) {
4151 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4152 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4153 }
4154 if (asserted & ATTN_GENERAL_ATTN_6) {
4155 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4156 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4157 }
4158 }
4159
4160 } /* if hardwired */
4161
4162 DP(NETIF_MSG_HW, "about to mask 0x%08x at IGU addr 0x%x\n",
4163 asserted, BAR_IGU_INTMEM + igu_addr);
4164 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, asserted);
4165
4166 /* now set back the mask */
4167 if (asserted & ATTN_NIG_FOR_FUNC)
4168 REG_WR(bp, nig_int_mask_addr, bp->nig_mask);
4169}
4170
4171static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4172{
4173 int port = bp->port;
4174 int reg_offset;
4175 u32 val;
4176
4177 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4178
4179 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4180 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4181
4182 val = REG_RD(bp, reg_offset);
4183 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4184 REG_WR(bp, reg_offset, val);
4185
4186 BNX2X_ERR("SPIO5 hw attention\n");
4187
4188 switch (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
4189 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
4190 /* Fan failure attention */
4191
4192 /* The PHY reset is controled by GPIO 1 */
4193 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4194 MISC_REGISTERS_GPIO_OUTPUT_LOW);
4195 /* Low power mode is controled by GPIO 2 */
4196 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4197 MISC_REGISTERS_GPIO_OUTPUT_LOW);
4198 /* mark the failure */
4199 bp->ext_phy_config &=
4200 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4201 bp->ext_phy_config |=
4202 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4203 SHMEM_WR(bp,
4204 dev_info.port_hw_config[port].
4205 external_phy_config,
4206 bp->ext_phy_config);
4207 /* log the failure */
4208 printk(KERN_ERR PFX "Fan Failure on Network"
4209 " Controller %s has caused the driver to"
4210 " shutdown the card to prevent permanent"
4211 " damage. Please contact Dell Support for"
4212 " assistance\n", bp->dev->name);
4213 break;
4214
4215 default:
4216 break;
4217 }
4218 }
4219}
4220
4221static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4222{
4223 u32 val;
4224
4225 if (attn & BNX2X_DOORQ_ASSERT) {
4226
4227 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4228 BNX2X_ERR("DB hw attention 0x%x\n", val);
4229 /* DORQ discard attention */
4230 if (val & 0x2)
4231 BNX2X_ERR("FATAL error from DORQ\n");
4232 }
4233}
4234
4235static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4236{
4237 u32 val;
4238
4239 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4240
4241 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4242 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4243 /* CFC error attention */
4244 if (val & 0x2)
4245 BNX2X_ERR("FATAL error from CFC\n");
4246 }
4247
4248 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4249
4250 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4251 BNX2X_ERR("PXP hw attention 0x%x\n", val);
4252 /* RQ_USDMDP_FIFO_OVERFLOW */
4253 if (val & 0x18000)
4254 BNX2X_ERR("FATAL error from PXP\n");
4255 }
4256}
4257
4258static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4259{
4260 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4261
4262 if (attn & BNX2X_MC_ASSERT_BITS) {
4263
4264 BNX2X_ERR("MC assert!\n");
4265 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4266 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4267 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4268 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4269 bnx2x_panic();
4270
4271 } else if (attn & BNX2X_MCP_ASSERT) {
4272
4273 BNX2X_ERR("MCP assert!\n");
4274 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4275 bnx2x_mc_assert(bp);
4276
4277 } else
4278 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4279 }
4280
4281 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4282
4283 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4284 BNX2X_ERR("LATCHED attention 0x%x (masked)\n", attn);
4285 }
4286}
4287
4288static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4289{
4290 struct attn_route attn;
4291 struct attn_route group_mask;
4292 int port = bp->port;
4293 int index;
4294 u32 reg_addr;
4295 u32 val;
4296
4297 /* need to take HW lock because MCP or other port might also
4298 try to handle this event */
4299 bnx2x_lock_alr(bp);
4300
4301 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4302 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4303 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4304 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4305 DP(NETIF_MSG_HW, "attn %llx\n", (unsigned long long)attn.sig[0]);
4306
4307 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4308 if (deasserted & (1 << index)) {
4309 group_mask = bp->attn_group[index];
4310
4311 DP(NETIF_MSG_HW, "group[%d]: %llx\n", index,
4312 (unsigned long long)group_mask.sig[0]);
4313
4314 bnx2x_attn_int_deasserted3(bp,
4315 attn.sig[3] & group_mask.sig[3]);
4316 bnx2x_attn_int_deasserted1(bp,
4317 attn.sig[1] & group_mask.sig[1]);
4318 bnx2x_attn_int_deasserted2(bp,
4319 attn.sig[2] & group_mask.sig[2]);
4320 bnx2x_attn_int_deasserted0(bp,
4321 attn.sig[0] & group_mask.sig[0]);
4322
4323 if ((attn.sig[0] & group_mask.sig[0] &
4324 HW_INTERRUT_ASSERT_SET_0) ||
4325 (attn.sig[1] & group_mask.sig[1] &
4326 HW_INTERRUT_ASSERT_SET_1) ||
4327 (attn.sig[2] & group_mask.sig[2] &
4328 HW_INTERRUT_ASSERT_SET_2))
4329 BNX2X_ERR("FATAL HW block attention"
4330 " set0 0x%x set1 0x%x"
4331 " set2 0x%x\n",
4332 (attn.sig[0] & group_mask.sig[0] &
4333 HW_INTERRUT_ASSERT_SET_0),
4334 (attn.sig[1] & group_mask.sig[1] &
4335 HW_INTERRUT_ASSERT_SET_1),
4336 (attn.sig[2] & group_mask.sig[2] &
4337 HW_INTERRUT_ASSERT_SET_2));
4338
4339 if ((attn.sig[0] & group_mask.sig[0] &
4340 HW_PRTY_ASSERT_SET_0) ||
4341 (attn.sig[1] & group_mask.sig[1] &
4342 HW_PRTY_ASSERT_SET_1) ||
4343 (attn.sig[2] & group_mask.sig[2] &
4344 HW_PRTY_ASSERT_SET_2))
4345 BNX2X_ERR("FATAL HW block parity attention\n");
4346 }
4347 }
4348
4349 bnx2x_unlock_alr(bp);
4350
4351 reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_PORT_BASE * port) * 8;
4352
4353 val = ~deasserted;
4354/* DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
4355 val, BAR_IGU_INTMEM + reg_addr); */
4356 REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val);
4357
4358 if (bp->aeu_mask & (deasserted & 0xff))
4359 BNX2X_ERR("IGU BUG\n");
4360 if (~bp->attn_state & deasserted)
4361 BNX2X_ERR("IGU BUG\n");
4362
4363 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4364 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4365
4366 DP(NETIF_MSG_HW, "aeu_mask %x\n", bp->aeu_mask);
4367 bp->aeu_mask |= (deasserted & 0xff);
4368
4369 DP(NETIF_MSG_HW, "new mask %x\n", bp->aeu_mask);
4370 REG_WR(bp, reg_addr, bp->aeu_mask);
4371
4372 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4373 bp->attn_state &= ~deasserted;
4374 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4375}
4376
4377static void bnx2x_attn_int(struct bnx2x *bp)
4378{
4379 /* read local copy of bits */
4380 u32 attn_bits = bp->def_status_blk->atten_status_block.attn_bits;
4381 u32 attn_ack = bp->def_status_blk->atten_status_block.attn_bits_ack;
4382 u32 attn_state = bp->attn_state;
4383
4384 /* look for changed bits */
4385 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4386 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4387
4388 DP(NETIF_MSG_HW,
4389 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4390 attn_bits, attn_ack, asserted, deasserted);
4391
4392 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4393 BNX2X_ERR("bad attention state\n");
4394
4395 /* handle bits that were raised */
4396 if (asserted)
4397 bnx2x_attn_int_asserted(bp, asserted);
4398
4399 if (deasserted)
4400 bnx2x_attn_int_deasserted(bp, deasserted);
4401}
4402
4403static void bnx2x_sp_task(struct work_struct *work)
4404{
4405 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task);
4406 u16 status;
4407
4408 /* Return here if interrupt is disabled */
4409 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
4410 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
4411 return;
4412 }
4413
4414 status = bnx2x_update_dsb_idx(bp);
4415 if (status == 0)
4416 BNX2X_ERR("spurious slowpath interrupt!\n");
4417
4418 DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
4419
4420 /* HW attentions */
4421 if (status & 0x1)
4422 bnx2x_attn_int(bp);
4423
4424 /* CStorm events: query_stats, port delete ramrod */
4425 if (status & 0x2)
4426 bp->stat_pending = 0;
4427
4428 bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, bp->def_att_idx,
4429 IGU_INT_NOP, 1);
4430 bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
4431 IGU_INT_NOP, 1);
4432 bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
4433 IGU_INT_NOP, 1);
4434 bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
4435 IGU_INT_NOP, 1);
4436 bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
4437 IGU_INT_ENABLE, 1);
4438
4439}
4440
4441static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4442{
4443 struct net_device *dev = dev_instance;
4444 struct bnx2x *bp = netdev_priv(dev);
4445
4446 /* Return here if interrupt is disabled */
4447 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
4448 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
4449 return IRQ_HANDLED;
4450 }
4451
4452 bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, 0, IGU_INT_DISABLE, 0);
4453
4454#ifdef BNX2X_STOP_ON_ERROR
4455 if (unlikely(bp->panic))
4456 return IRQ_HANDLED;
4457#endif
4458
4459 schedule_work(&bp->sp_task);
4460
4461 return IRQ_HANDLED;
4462}
4463
4464/* end of slow path */
4465
4466/* Statistics */
4467
4468/****************************************************************************
4469* Macros
4470****************************************************************************/
4471
4472#define UPDATE_STAT(s, t) \
4473 do { \
4474 estats->t += new->s - old->s; \
4475 old->s = new->s; \
4476 } while (0)
4477
4478/* sum[hi:lo] += add[hi:lo] */
4479#define ADD_64(s_hi, a_hi, s_lo, a_lo) \
4480 do { \
4481 s_lo += a_lo; \
4482 s_hi += a_hi + (s_lo < a_lo) ? 1 : 0; \
4483 } while (0)
4484
4485/* difference = minuend - subtrahend */
4486#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
4487 do { \
4488 if (m_lo < s_lo) { /* underflow */ \
4489 d_hi = m_hi - s_hi; \
4490 if (d_hi > 0) { /* we can 'loan' 1 */ \
4491 d_hi--; \
4492 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
4493 } else { /* m_hi <= s_hi */ \
4494 d_hi = 0; \
4495 d_lo = 0; \
4496 } \
4497 } else { /* m_lo >= s_lo */ \
4498 if (m_hi < s_hi) { \
4499 d_hi = 0; \
4500 d_lo = 0; \
4501 } else { /* m_hi >= s_hi */ \
4502 d_hi = m_hi - s_hi; \
4503 d_lo = m_lo - s_lo; \
4504 } \
4505 } \
4506 } while (0)
4507
4508/* minuend -= subtrahend */
4509#define SUB_64(m_hi, s_hi, m_lo, s_lo) \
4510 do { \
4511 DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
4512 } while (0)
4513
4514#define UPDATE_STAT64(s_hi, t_hi, s_lo, t_lo) \
4515 do { \
4516 DIFF_64(diff.hi, new->s_hi, old->s_hi, \
4517 diff.lo, new->s_lo, old->s_lo); \
4518 old->s_hi = new->s_hi; \
4519 old->s_lo = new->s_lo; \
4520 ADD_64(estats->t_hi, diff.hi, \
4521 estats->t_lo, diff.lo); \
4522 } while (0)
4523
4524/* sum[hi:lo] += add */
4525#define ADD_EXTEND_64(s_hi, s_lo, a) \
4526 do { \
4527 s_lo += a; \
4528 s_hi += (s_lo < a) ? 1 : 0; \
4529 } while (0)
4530
4531#define UPDATE_EXTEND_STAT(s, t_hi, t_lo) \
4532 do { \
4533 ADD_EXTEND_64(estats->t_hi, estats->t_lo, new->s); \
4534 } while (0)
4535
4536#define UPDATE_EXTEND_TSTAT(s, t_hi, t_lo) \
4537 do { \
4538 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
4539 old_tclient->s = le32_to_cpu(tclient->s); \
4540 ADD_EXTEND_64(estats->t_hi, estats->t_lo, diff); \
4541 } while (0)
4542
4543/*
4544 * General service functions
4545 */
4546
4547static inline long bnx2x_hilo(u32 *hiref)
4548{
4549 u32 lo = *(hiref + 1);
4550#if (BITS_PER_LONG == 64)
4551 u32 hi = *hiref;
4552
4553 return HILO_U64(hi, lo);
4554#else
4555 return lo;
4556#endif
4557}
4558
4559/*
4560 * Init service functions
4561 */
4562
4563static void bnx2x_init_mac_stats(struct bnx2x *bp)
4564{
4565 struct dmae_command *dmae;
4566 int port = bp->port;
4567 int loader_idx = port * 8;
4568 u32 opcode;
4569 u32 mac_addr;
4570
4571 bp->executer_idx = 0;
4572 if (bp->fw_mb) {
4573 /* MCP */
4574 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
4575 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4576#ifdef __BIG_ENDIAN
4577 DMAE_CMD_ENDIANITY_B_DW_SWAP |
4578#else
4579 DMAE_CMD_ENDIANITY_DW_SWAP |
4580#endif
4581 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
4582
4583 if (bp->link_up)
4584 opcode |= (DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE);
4585
4586 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4587 dmae->opcode = opcode;
4588 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, eth_stats) +
4589 sizeof(u32));
4590 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, eth_stats) +
4591 sizeof(u32));
4592 dmae->dst_addr_lo = bp->fw_mb >> 2;
4593 dmae->dst_addr_hi = 0;
4594 dmae->len = (offsetof(struct bnx2x_eth_stats, mac_stx_end) -
4595 sizeof(u32)) >> 2;
4596 if (bp->link_up) {
4597 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4598 dmae->comp_addr_hi = 0;
4599 dmae->comp_val = 1;
4600 } else {
4601 dmae->comp_addr_lo = 0;
4602 dmae->comp_addr_hi = 0;
4603 dmae->comp_val = 0;
4604 }
4605 }
4606
4607 if (!bp->link_up) {
4608 /* no need to collect statistics in link down */
4609 return;
4610 }
4611
4612 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
4613 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
4614 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4615#ifdef __BIG_ENDIAN
4616 DMAE_CMD_ENDIANITY_B_DW_SWAP |
4617#else
4618 DMAE_CMD_ENDIANITY_DW_SWAP |
4619#endif
4620 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
4621
4622 if (bp->phy_flags & PHY_BMAC_FLAG) {
4623
4624 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
4625 NIG_REG_INGRESS_BMAC0_MEM);
4626
4627 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
4628 BIGMAC_REGISTER_TX_STAT_GTBYT */
4629 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4630 dmae->opcode = opcode;
4631 dmae->src_addr_lo = (mac_addr +
4632 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
4633 dmae->src_addr_hi = 0;
4634 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
4635 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
4636 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
4637 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
4638 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4639 dmae->comp_addr_hi = 0;
4640 dmae->comp_val = 1;
4641
4642 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
4643 BIGMAC_REGISTER_RX_STAT_GRIPJ */
4644 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4645 dmae->opcode = opcode;
4646 dmae->src_addr_lo = (mac_addr +
4647 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
4648 dmae->src_addr_hi = 0;
4649 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
4650 offsetof(struct bmac_stats, rx_gr64));
4651 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
4652 offsetof(struct bmac_stats, rx_gr64));
4653 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
4654 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
4655 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4656 dmae->comp_addr_hi = 0;
4657 dmae->comp_val = 1;
4658
4659 } else if (bp->phy_flags & PHY_EMAC_FLAG) {
4660
4661 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
4662
4663 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
4664 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4665 dmae->opcode = opcode;
4666 dmae->src_addr_lo = (mac_addr +
4667 EMAC_REG_EMAC_RX_STAT_AC) >> 2;
4668 dmae->src_addr_hi = 0;
4669 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
4670 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
4671 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
4672 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4673 dmae->comp_addr_hi = 0;
4674 dmae->comp_val = 1;
4675
4676 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
4677 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4678 dmae->opcode = opcode;
4679 dmae->src_addr_lo = (mac_addr +
4680 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
4681 dmae->src_addr_hi = 0;
4682 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
4683 offsetof(struct emac_stats,
4684 rx_falsecarriererrors));
4685 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
4686 offsetof(struct emac_stats,
4687 rx_falsecarriererrors));
4688 dmae->len = 1;
4689 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4690 dmae->comp_addr_hi = 0;
4691 dmae->comp_val = 1;
4692
4693 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
4694 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4695 dmae->opcode = opcode;
4696 dmae->src_addr_lo = (mac_addr +
4697 EMAC_REG_EMAC_TX_STAT_AC) >> 2;
4698 dmae->src_addr_hi = 0;
4699 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
4700 offsetof(struct emac_stats,
4701 tx_ifhcoutoctets));
4702 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
4703 offsetof(struct emac_stats,
4704 tx_ifhcoutoctets));
4705 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
4706 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4707 dmae->comp_addr_hi = 0;
4708 dmae->comp_val = 1;
4709 }
4710
4711 /* NIG */
4712 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4713 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
4714 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
4715 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4716#ifdef __BIG_ENDIAN
4717 DMAE_CMD_ENDIANITY_B_DW_SWAP |
4718#else
4719 DMAE_CMD_ENDIANITY_DW_SWAP |
4720#endif
4721 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
4722 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
4723 NIG_REG_STAT0_BRB_DISCARD) >> 2;
4724 dmae->src_addr_hi = 0;
4725 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig));
4726 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig));
4727 dmae->len = (sizeof(struct nig_stats) - 2*sizeof(u32)) >> 2;
4728 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig) +
4729 offsetof(struct nig_stats, done));
4730 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig) +
4731 offsetof(struct nig_stats, done));
4732 dmae->comp_val = 0xffffffff;
4733}
4734
4735static void bnx2x_init_stats(struct bnx2x *bp)
4736{
4737 int port = bp->port;
4738
4739 bp->stats_state = STATS_STATE_DISABLE;
4740 bp->executer_idx = 0;
4741
4742 bp->old_brb_discard = REG_RD(bp,
4743 NIG_REG_STAT0_BRB_DISCARD + port*0x38);
4744
4745 memset(&bp->old_bmac, 0, sizeof(struct bmac_stats));
4746 memset(&bp->old_tclient, 0, sizeof(struct tstorm_per_client_stats));
4747 memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
4748
4749 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port), 1);
4750 REG_WR(bp, BAR_XSTRORM_INTMEM +
4751 XSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
4752
4753 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port), 1);
4754 REG_WR(bp, BAR_TSTRORM_INTMEM +
4755 TSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
4756
4757 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port), 0);
4758 REG_WR(bp, BAR_CSTRORM_INTMEM +
4759 CSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
4760
4761 REG_WR(bp, BAR_XSTRORM_INTMEM +
4762 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port),
4763 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4764 REG_WR(bp, BAR_XSTRORM_INTMEM +
4765 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) + 4,
4766 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4767
4768 REG_WR(bp, BAR_TSTRORM_INTMEM +
4769 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port),
4770 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4771 REG_WR(bp, BAR_TSTRORM_INTMEM +
4772 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) + 4,
4773 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4774}
4775
4776static void bnx2x_stop_stats(struct bnx2x *bp)
4777{
4778 might_sleep();
4779 if (bp->stats_state != STATS_STATE_DISABLE) {
4780 int timeout = 10;
4781
4782 bp->stats_state = STATS_STATE_STOP;
4783 DP(BNX2X_MSG_STATS, "stats_state - STOP\n");
4784
4785 while (bp->stats_state != STATS_STATE_DISABLE) {
4786 if (!timeout) {
4787 BNX2X_ERR("timeout waiting for stats stop\n");
4788 break;
4789 }
4790 timeout--;
4791 msleep(100);
4792 }
4793 }
4794 DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");
4795}
4796
4797/*
4798 * Statistics service functions
4799 */
4800
4801static void bnx2x_update_bmac_stats(struct bnx2x *bp)
4802{
4803 struct regp diff;
4804 struct regp sum;
4805 struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac);
4806 struct bmac_stats *old = &bp->old_bmac;
4807 struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
4808
4809 sum.hi = 0;
4810 sum.lo = 0;
4811
4812 UPDATE_STAT64(tx_gtbyt.hi, total_bytes_transmitted_hi,
4813 tx_gtbyt.lo, total_bytes_transmitted_lo);
4814
4815 UPDATE_STAT64(tx_gtmca.hi, total_multicast_packets_transmitted_hi,
4816 tx_gtmca.lo, total_multicast_packets_transmitted_lo);
4817 ADD_64(sum.hi, diff.hi, sum.lo, diff.lo);
4818
4819 UPDATE_STAT64(tx_gtgca.hi, total_broadcast_packets_transmitted_hi,
4820 tx_gtgca.lo, total_broadcast_packets_transmitted_lo);
4821 ADD_64(sum.hi, diff.hi, sum.lo, diff.lo);
4822
4823 UPDATE_STAT64(tx_gtpkt.hi, total_unicast_packets_transmitted_hi,
4824 tx_gtpkt.lo, total_unicast_packets_transmitted_lo);
4825 SUB_64(estats->total_unicast_packets_transmitted_hi, sum.hi,
4826 estats->total_unicast_packets_transmitted_lo, sum.lo);
4827
4828 UPDATE_STAT(tx_gtxpf.lo, pause_xoff_frames_transmitted);
4829 UPDATE_STAT(tx_gt64.lo, frames_transmitted_64_bytes);
4830 UPDATE_STAT(tx_gt127.lo, frames_transmitted_65_127_bytes);
4831 UPDATE_STAT(tx_gt255.lo, frames_transmitted_128_255_bytes);
4832 UPDATE_STAT(tx_gt511.lo, frames_transmitted_256_511_bytes);
4833 UPDATE_STAT(tx_gt1023.lo, frames_transmitted_512_1023_bytes);
4834 UPDATE_STAT(tx_gt1518.lo, frames_transmitted_1024_1522_bytes);
4835 UPDATE_STAT(tx_gt2047.lo, frames_transmitted_1523_9022_bytes);
4836 UPDATE_STAT(tx_gt4095.lo, frames_transmitted_1523_9022_bytes);
4837 UPDATE_STAT(tx_gt9216.lo, frames_transmitted_1523_9022_bytes);
4838 UPDATE_STAT(tx_gt16383.lo, frames_transmitted_1523_9022_bytes);
4839
4840 UPDATE_STAT(rx_grfcs.lo, crc_receive_errors);
4841 UPDATE_STAT(rx_grund.lo, runt_packets_received);
4842 UPDATE_STAT(rx_grovr.lo, stat_Dot3statsFramesTooLong);
4843 UPDATE_STAT(rx_grxpf.lo, pause_xoff_frames_received);
4844 UPDATE_STAT(rx_grxcf.lo, control_frames_received);
4845 /* UPDATE_STAT(rx_grxpf.lo, control_frames_received); */
4846 UPDATE_STAT(rx_grfrg.lo, error_runt_packets_received);
4847 UPDATE_STAT(rx_grjbr.lo, error_jabber_packets_received);
4848
4849 UPDATE_STAT64(rx_grerb.hi, stat_IfHCInBadOctets_hi,
4850 rx_grerb.lo, stat_IfHCInBadOctets_lo);
4851 UPDATE_STAT64(tx_gtufl.hi, stat_IfHCOutBadOctets_hi,
4852 tx_gtufl.lo, stat_IfHCOutBadOctets_lo);
4853 UPDATE_STAT(tx_gterr.lo, stat_Dot3statsInternalMacTransmitErrors);
4854 /* UPDATE_STAT(rx_grxpf.lo, stat_XoffStateEntered); */
4855 estats->stat_XoffStateEntered = estats->pause_xoff_frames_received;
4856}
4857
4858static void bnx2x_update_emac_stats(struct bnx2x *bp)
4859{
4860 struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac);
4861 struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
4862
4863 UPDATE_EXTEND_STAT(tx_ifhcoutoctets, total_bytes_transmitted_hi,
4864 total_bytes_transmitted_lo);
4865 UPDATE_EXTEND_STAT(tx_ifhcoutucastpkts,
4866 total_unicast_packets_transmitted_hi,
4867 total_unicast_packets_transmitted_lo);
4868 UPDATE_EXTEND_STAT(tx_ifhcoutmulticastpkts,
4869 total_multicast_packets_transmitted_hi,
4870 total_multicast_packets_transmitted_lo);
4871 UPDATE_EXTEND_STAT(tx_ifhcoutbroadcastpkts,
4872 total_broadcast_packets_transmitted_hi,
4873 total_broadcast_packets_transmitted_lo);
4874
4875 estats->pause_xon_frames_transmitted += new->tx_outxonsent;
4876 estats->pause_xoff_frames_transmitted += new->tx_outxoffsent;
4877 estats->single_collision_transmit_frames +=
4878 new->tx_dot3statssinglecollisionframes;
4879 estats->multiple_collision_transmit_frames +=
4880 new->tx_dot3statsmultiplecollisionframes;
4881 estats->late_collision_frames += new->tx_dot3statslatecollisions;
4882 estats->excessive_collision_frames +=
4883 new->tx_dot3statsexcessivecollisions;
4884 estats->frames_transmitted_64_bytes += new->tx_etherstatspkts64octets;
4885 estats->frames_transmitted_65_127_bytes +=
4886 new->tx_etherstatspkts65octetsto127octets;
4887 estats->frames_transmitted_128_255_bytes +=
4888 new->tx_etherstatspkts128octetsto255octets;
4889 estats->frames_transmitted_256_511_bytes +=
4890 new->tx_etherstatspkts256octetsto511octets;
4891 estats->frames_transmitted_512_1023_bytes +=
4892 new->tx_etherstatspkts512octetsto1023octets;
4893 estats->frames_transmitted_1024_1522_bytes +=
4894 new->tx_etherstatspkts1024octetsto1522octet;
4895 estats->frames_transmitted_1523_9022_bytes +=
4896 new->tx_etherstatspktsover1522octets;
4897
4898 estats->crc_receive_errors += new->rx_dot3statsfcserrors;
4899 estats->alignment_errors += new->rx_dot3statsalignmenterrors;
4900 estats->false_carrier_detections += new->rx_falsecarriererrors;
4901 estats->runt_packets_received += new->rx_etherstatsundersizepkts;
4902 estats->stat_Dot3statsFramesTooLong += new->rx_dot3statsframestoolong;
4903 estats->pause_xon_frames_received += new->rx_xonpauseframesreceived;
4904 estats->pause_xoff_frames_received += new->rx_xoffpauseframesreceived;
4905 estats->control_frames_received += new->rx_maccontrolframesreceived;
4906 estats->error_runt_packets_received += new->rx_etherstatsfragments;
4907 estats->error_jabber_packets_received += new->rx_etherstatsjabbers;
4908
4909 UPDATE_EXTEND_STAT(rx_ifhcinbadoctets, stat_IfHCInBadOctets_hi,
4910 stat_IfHCInBadOctets_lo);
4911 UPDATE_EXTEND_STAT(tx_ifhcoutbadoctets, stat_IfHCOutBadOctets_hi,
4912 stat_IfHCOutBadOctets_lo);
4913 estats->stat_Dot3statsInternalMacTransmitErrors +=
4914 new->tx_dot3statsinternalmactransmiterrors;
4915 estats->stat_Dot3StatsCarrierSenseErrors +=
4916 new->rx_dot3statscarriersenseerrors;
4917 estats->stat_Dot3StatsDeferredTransmissions +=
4918 new->tx_dot3statsdeferredtransmissions;
4919 estats->stat_FlowControlDone += new->tx_flowcontroldone;
4920 estats->stat_XoffStateEntered += new->rx_xoffstateentered;
4921}
4922
4923static int bnx2x_update_storm_stats(struct bnx2x *bp)
4924{
4925 struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
4926 struct tstorm_common_stats *tstats = &stats->tstorm_common;
4927 struct tstorm_per_client_stats *tclient =
4928 &tstats->client_statistics[0];
4929 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
4930 struct xstorm_common_stats *xstats = &stats->xstorm_common;
4931 struct nig_stats *nstats = bnx2x_sp(bp, nig);
4932 struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
4933 u32 diff;
4934
4935 /* are DMAE stats valid? */
4936 if (nstats->done != 0xffffffff) {
4937 DP(BNX2X_MSG_STATS, "stats not updated by dmae\n");
4938 return -1;
4939 }
4940
4941 /* are storm stats valid? */
4942 if (tstats->done.hi != 0xffffffff) {
4943 DP(BNX2X_MSG_STATS, "stats not updated by tstorm\n");
4944 return -2;
4945 }
4946 if (xstats->done.hi != 0xffffffff) {
4947 DP(BNX2X_MSG_STATS, "stats not updated by xstorm\n");
4948 return -3;
4949 }
4950
4951 estats->total_bytes_received_hi =
4952 estats->valid_bytes_received_hi =
4953 le32_to_cpu(tclient->total_rcv_bytes.hi);
4954 estats->total_bytes_received_lo =
4955 estats->valid_bytes_received_lo =
4956 le32_to_cpu(tclient->total_rcv_bytes.lo);
4957 ADD_64(estats->total_bytes_received_hi,
4958 le32_to_cpu(tclient->rcv_error_bytes.hi),
4959 estats->total_bytes_received_lo,
4960 le32_to_cpu(tclient->rcv_error_bytes.lo));
4961
4962 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
4963 total_unicast_packets_received_hi,
4964 total_unicast_packets_received_lo);
4965 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
4966 total_multicast_packets_received_hi,
4967 total_multicast_packets_received_lo);
4968 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
4969 total_broadcast_packets_received_hi,
4970 total_broadcast_packets_received_lo);
4971
4972 estats->frames_received_64_bytes = MAC_STX_NA;
4973 estats->frames_received_65_127_bytes = MAC_STX_NA;
4974 estats->frames_received_128_255_bytes = MAC_STX_NA;
4975 estats->frames_received_256_511_bytes = MAC_STX_NA;
4976 estats->frames_received_512_1023_bytes = MAC_STX_NA;
4977 estats->frames_received_1024_1522_bytes = MAC_STX_NA;
4978 estats->frames_received_1523_9022_bytes = MAC_STX_NA;
4979
4980 estats->x_total_sent_bytes_hi =
4981 le32_to_cpu(xstats->total_sent_bytes.hi);
4982 estats->x_total_sent_bytes_lo =
4983 le32_to_cpu(xstats->total_sent_bytes.lo);
4984 estats->x_total_sent_pkts = le32_to_cpu(xstats->total_sent_pkts);
4985
4986 estats->t_rcv_unicast_bytes_hi =
4987 le32_to_cpu(tclient->rcv_unicast_bytes.hi);
4988 estats->t_rcv_unicast_bytes_lo =
4989 le32_to_cpu(tclient->rcv_unicast_bytes.lo);
4990 estats->t_rcv_broadcast_bytes_hi =
4991 le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
4992 estats->t_rcv_broadcast_bytes_lo =
4993 le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
4994 estats->t_rcv_multicast_bytes_hi =
4995 le32_to_cpu(tclient->rcv_multicast_bytes.hi);
4996 estats->t_rcv_multicast_bytes_lo =
4997 le32_to_cpu(tclient->rcv_multicast_bytes.lo);
4998 estats->t_total_rcv_pkt = le32_to_cpu(tclient->total_rcv_pkts);
4999
5000 estats->checksum_discard = le32_to_cpu(tclient->checksum_discard);
5001 estats->packets_too_big_discard =
5002 le32_to_cpu(tclient->packets_too_big_discard);
5003 estats->jabber_packets_received = estats->packets_too_big_discard +
5004 estats->stat_Dot3statsFramesTooLong;
5005 estats->no_buff_discard = le32_to_cpu(tclient->no_buff_discard);
5006 estats->ttl0_discard = le32_to_cpu(tclient->ttl0_discard);
5007 estats->mac_discard = le32_to_cpu(tclient->mac_discard);
5008 estats->mac_filter_discard = le32_to_cpu(tstats->mac_filter_discard);
5009 estats->xxoverflow_discard = le32_to_cpu(tstats->xxoverflow_discard);
5010 estats->brb_truncate_discard =
5011 le32_to_cpu(tstats->brb_truncate_discard);
5012
5013 estats->brb_discard += nstats->brb_discard - bp->old_brb_discard;
5014 bp->old_brb_discard = nstats->brb_discard;
5015
5016 estats->brb_packet = nstats->brb_packet;
5017 estats->brb_truncate = nstats->brb_truncate;
5018 estats->flow_ctrl_discard = nstats->flow_ctrl_discard;
5019 estats->flow_ctrl_octets = nstats->flow_ctrl_octets;
5020 estats->flow_ctrl_packet = nstats->flow_ctrl_packet;
5021 estats->mng_discard = nstats->mng_discard;
5022 estats->mng_octet_inp = nstats->mng_octet_inp;
5023 estats->mng_octet_out = nstats->mng_octet_out;
5024 estats->mng_packet_inp = nstats->mng_packet_inp;
5025 estats->mng_packet_out = nstats->mng_packet_out;
5026 estats->pbf_octets = nstats->pbf_octets;
5027 estats->pbf_packet = nstats->pbf_packet;
5028 estats->safc_inp = nstats->safc_inp;
5029
5030 xstats->done.hi = 0;
5031 tstats->done.hi = 0;
5032 nstats->done = 0;
5033
5034 return 0;
5035}
5036
5037static void bnx2x_update_net_stats(struct bnx2x *bp)
5038{
5039 struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
5040 struct net_device_stats *nstats = &bp->dev->stats;
5041
5042 nstats->rx_packets =
5043 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
5044 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
5045 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
5046
5047 nstats->tx_packets =
5048 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
5049 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
5050 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
5051
5052 nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
5053
5054 nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
5055
5056 nstats->rx_dropped = estats->checksum_discard + estats->mac_discard;
5057 nstats->tx_dropped = 0;
5058
5059 nstats->multicast =
5060 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi);
5061
5062 nstats->collisions = estats->single_collision_transmit_frames +
5063 estats->multiple_collision_transmit_frames +
5064 estats->late_collision_frames +
5065 estats->excessive_collision_frames;
5066
5067 nstats->rx_length_errors = estats->runt_packets_received +
5068 estats->jabber_packets_received;
5069 nstats->rx_over_errors = estats->brb_discard +
5070 estats->brb_truncate_discard;
5071 nstats->rx_crc_errors = estats->crc_receive_errors;
5072 nstats->rx_frame_errors = estats->alignment_errors;
5073 nstats->rx_fifo_errors = estats->no_buff_discard;
5074 nstats->rx_missed_errors = estats->xxoverflow_discard;
5075
5076 nstats->rx_errors = nstats->rx_length_errors +
5077 nstats->rx_over_errors +
5078 nstats->rx_crc_errors +
5079 nstats->rx_frame_errors +
5080 nstats->rx_fifo_errors +
5081 nstats->rx_missed_errors;
5082
5083 nstats->tx_aborted_errors = estats->late_collision_frames +
5084 estats->excessive_collision_frames;
5085 nstats->tx_carrier_errors = estats->false_carrier_detections;
5086 nstats->tx_fifo_errors = 0;
5087 nstats->tx_heartbeat_errors = 0;
5088 nstats->tx_window_errors = 0;
5089
5090 nstats->tx_errors = nstats->tx_aborted_errors +
5091 nstats->tx_carrier_errors;
5092
5093 estats->mac_stx_start = ++estats->mac_stx_end;
5094}
5095
5096static void bnx2x_update_stats(struct bnx2x *bp)
5097{
5098 int i;
5099
5100 if (!bnx2x_update_storm_stats(bp)) {
5101
5102 if (bp->phy_flags & PHY_BMAC_FLAG) {
5103 bnx2x_update_bmac_stats(bp);
5104
5105 } else if (bp->phy_flags & PHY_EMAC_FLAG) {
5106 bnx2x_update_emac_stats(bp);
5107
5108 } else { /* unreached */
5109 BNX2X_ERR("no MAC active\n");
5110 return;
5111 }
5112
5113 bnx2x_update_net_stats(bp);
5114 }
5115
5116 if (bp->msglevel & NETIF_MSG_TIMER) {
5117 struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
5118 struct net_device_stats *nstats = &bp->dev->stats;
5119
5120 printk(KERN_DEBUG "%s:\n", bp->dev->name);
5121 printk(KERN_DEBUG " tx avail (%4x) tx hc idx (%x)"
5122 " tx pkt (%lx)\n",
5123 bnx2x_tx_avail(bp->fp),
5124 *bp->fp->tx_cons_sb, nstats->tx_packets);
5125 printk(KERN_DEBUG " rx usage (%4x) rx hc idx (%x)"
5126 " rx pkt (%lx)\n",
5127 (u16)(*bp->fp->rx_cons_sb - bp->fp->rx_comp_cons),
5128 *bp->fp->rx_cons_sb, nstats->rx_packets);
5129 printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u\n",
5130 netif_queue_stopped(bp->dev)? "Xoff" : "Xon",
5131 estats->driver_xoff, estats->brb_discard);
5132 printk(KERN_DEBUG "tstats: checksum_discard %u "
5133 "packets_too_big_discard %u no_buff_discard %u "
5134 "mac_discard %u mac_filter_discard %u "
5135 "xxovrflow_discard %u brb_truncate_discard %u "
5136 "ttl0_discard %u\n",
5137 estats->checksum_discard,
5138 estats->packets_too_big_discard,
5139 estats->no_buff_discard, estats->mac_discard,
5140 estats->mac_filter_discard, estats->xxoverflow_discard,
5141 estats->brb_truncate_discard, estats->ttl0_discard);
5142
5143 for_each_queue(bp, i) {
5144 printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
5145 bnx2x_fp(bp, i, tx_pkt),
5146 bnx2x_fp(bp, i, rx_pkt),
5147 bnx2x_fp(bp, i, rx_calls));
5148 }
5149 }
5150
5151 if (bp->state != BNX2X_STATE_OPEN) {
5152 DP(BNX2X_MSG_STATS, "state is %x, returning\n", bp->state);
5153 return;
5154 }
5155
5156#ifdef BNX2X_STOP_ON_ERROR
5157 if (unlikely(bp->panic))
5158 return;
5159#endif
5160
5161 /* loader */
5162 if (bp->executer_idx) {
5163 struct dmae_command *dmae = &bp->dmae;
5164 int port = bp->port;
5165 int loader_idx = port * 8;
5166
5167 memset(dmae, 0, sizeof(struct dmae_command));
5168
5169 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
5170 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
5171 DMAE_CMD_DST_RESET |
5172#ifdef __BIG_ENDIAN
5173 DMAE_CMD_ENDIANITY_B_DW_SWAP |
5174#else
5175 DMAE_CMD_ENDIANITY_DW_SWAP |
5176#endif
5177 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
5178 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
5179 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
5180 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
5181 sizeof(struct dmae_command) *
5182 (loader_idx + 1)) >> 2;
5183 dmae->dst_addr_hi = 0;
5184 dmae->len = sizeof(struct dmae_command) >> 2;
5185 dmae->len--; /* !!! for A0/1 only */
5186 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
5187 dmae->comp_addr_hi = 0;
5188 dmae->comp_val = 1;
5189
5190 bnx2x_post_dmae(bp, dmae, loader_idx);
5191 }
5192
5193 if (bp->stats_state != STATS_STATE_ENABLE) {
5194 bp->stats_state = STATS_STATE_DISABLE;
5195 return;
5196 }
5197
5198 if (bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0, 0, 0, 0) == 0) {
5199 /* stats ramrod has it's own slot on the spe */
5200 bp->spq_left++;
5201 bp->stat_pending = 1;
5202 }
5203}
5204
5205static void bnx2x_timer(unsigned long data)
5206{
5207 struct bnx2x *bp = (struct bnx2x *) data;
5208
5209 if (!netif_running(bp->dev))
5210 return;
5211
5212 if (atomic_read(&bp->intr_sem) != 0)
5213 goto timer_restart;
5214
5215 if (poll) {
5216 struct bnx2x_fastpath *fp = &bp->fp[0];
5217 int rc;
5218
5219 bnx2x_tx_int(fp, 1000);
5220 rc = bnx2x_rx_int(fp, 1000);
5221 }
5222
5223 if (!nomcp) {
5224 int port = bp->port;
5225 u32 drv_pulse;
5226 u32 mcp_pulse;
5227
5228 ++bp->fw_drv_pulse_wr_seq;
5229 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5230 /* TBD - add SYSTEM_TIME */
5231 drv_pulse = bp->fw_drv_pulse_wr_seq;
5232 SHMEM_WR(bp, func_mb[port].drv_pulse_mb, drv_pulse);
5233
5234 mcp_pulse = (SHMEM_RD(bp, func_mb[port].mcp_pulse_mb) &
5235 MCP_PULSE_SEQ_MASK);
5236 /* The delta between driver pulse and mcp response
5237 * should be 1 (before mcp response) or 0 (after mcp response)
5238 */
5239 if ((drv_pulse != mcp_pulse) &&
5240 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5241 /* someone lost a heartbeat... */
5242 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5243 drv_pulse, mcp_pulse);
5244 }
5245 }
5246
5247 if (bp->stats_state == STATS_STATE_DISABLE)
5248 goto timer_restart;
5249
5250 bnx2x_update_stats(bp);
5251
5252timer_restart:
5253 mod_timer(&bp->timer, jiffies + bp->current_interval);
5254}
5255
5256/* end of Statistics */
5257
5258/* nic init */
5259
5260/*
5261 * nic init service functions
5262 */
5263
5264static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
5265 dma_addr_t mapping, int id)
5266{
5267 int port = bp->port;
5268 u64 section;
5269 int index;
5270
5271 /* USTORM */
5272 section = ((u64)mapping) + offsetof(struct host_status_block,
5273 u_status_block);
5274 sb->u_status_block.status_block_id = id;
5275
5276 REG_WR(bp, BAR_USTRORM_INTMEM +
5277 USTORM_SB_HOST_SB_ADDR_OFFSET(port, id), U64_LO(section));
5278 REG_WR(bp, BAR_USTRORM_INTMEM +
5279 ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, id)) + 4),
5280 U64_HI(section));
5281
5282 for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
5283 REG_WR16(bp, BAR_USTRORM_INTMEM +
5284 USTORM_SB_HC_DISABLE_OFFSET(port, id, index), 0x1);
5285
5286 /* CSTORM */
5287 section = ((u64)mapping) + offsetof(struct host_status_block,
5288 c_status_block);
5289 sb->c_status_block.status_block_id = id;
5290
5291 REG_WR(bp, BAR_CSTRORM_INTMEM +
5292 CSTORM_SB_HOST_SB_ADDR_OFFSET(port, id), U64_LO(section));
5293 REG_WR(bp, BAR_CSTRORM_INTMEM +
5294 ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, id)) + 4),
5295 U64_HI(section));
5296
5297 for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
5298 REG_WR16(bp, BAR_CSTRORM_INTMEM +
5299 CSTORM_SB_HC_DISABLE_OFFSET(port, id, index), 0x1);
5300
5301 bnx2x_ack_sb(bp, id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
5302}
5303
5304static void bnx2x_init_def_sb(struct bnx2x *bp,
5305 struct host_def_status_block *def_sb,
5306 dma_addr_t mapping, int id)
5307{
5308 int port = bp->port;
5309 int index, val, reg_offset;
5310 u64 section;
5311
5312 /* ATTN */
5313 section = ((u64)mapping) + offsetof(struct host_def_status_block,
5314 atten_status_block);
5315 def_sb->atten_status_block.status_block_id = id;
5316
5317 bp->def_att_idx = 0;
5318 bp->attn_state = 0;
5319
5320 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5321 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5322
5323 for (index = 0; index < 3; index++) {
5324 bp->attn_group[index].sig[0] = REG_RD(bp,
5325 reg_offset + 0x10*index);
5326 bp->attn_group[index].sig[1] = REG_RD(bp,
5327 reg_offset + 0x4 + 0x10*index);
5328 bp->attn_group[index].sig[2] = REG_RD(bp,
5329 reg_offset + 0x8 + 0x10*index);
5330 bp->attn_group[index].sig[3] = REG_RD(bp,
5331 reg_offset + 0xc + 0x10*index);
5332 }
5333
5334 bp->aeu_mask = REG_RD(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5335 MISC_REG_AEU_MASK_ATTN_FUNC_0));
5336
5337 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5338 HC_REG_ATTN_MSG0_ADDR_L);
5339
5340 REG_WR(bp, reg_offset, U64_LO(section));
5341 REG_WR(bp, reg_offset + 4, U64_HI(section));
5342
5343 reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
5344
5345 val = REG_RD(bp, reg_offset);
5346 val |= id;
5347 REG_WR(bp, reg_offset, val);
5348
5349 /* USTORM */
5350 section = ((u64)mapping) + offsetof(struct host_def_status_block,
5351 u_def_status_block);
5352 def_sb->u_def_status_block.status_block_id = id;
5353
5354 bp->def_u_idx = 0;
5355
5356 REG_WR(bp, BAR_USTRORM_INTMEM +
5357 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
5358 REG_WR(bp, BAR_USTRORM_INTMEM +
5359 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
5360 U64_HI(section));
5361 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port),
5362 BNX2X_BTR);
5363
5364 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
5365 REG_WR16(bp, BAR_USTRORM_INTMEM +
5366 USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
5367
5368 /* CSTORM */
5369 section = ((u64)mapping) + offsetof(struct host_def_status_block,
5370 c_def_status_block);
5371 def_sb->c_def_status_block.status_block_id = id;
5372
5373 bp->def_c_idx = 0;
5374
5375 REG_WR(bp, BAR_CSTRORM_INTMEM +
5376 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
5377 REG_WR(bp, BAR_CSTRORM_INTMEM +
5378 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
5379 U64_HI(section));
5380 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port),
5381 BNX2X_BTR);
5382
5383 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
5384 REG_WR16(bp, BAR_CSTRORM_INTMEM +
5385 CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
5386
5387 /* TSTORM */
5388 section = ((u64)mapping) + offsetof(struct host_def_status_block,
5389 t_def_status_block);
5390 def_sb->t_def_status_block.status_block_id = id;
5391
5392 bp->def_t_idx = 0;
5393
5394 REG_WR(bp, BAR_TSTRORM_INTMEM +
5395 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
5396 REG_WR(bp, BAR_TSTRORM_INTMEM +
5397 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
5398 U64_HI(section));
5399 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port),
5400 BNX2X_BTR);
5401
5402 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
5403 REG_WR16(bp, BAR_TSTRORM_INTMEM +
5404 TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
5405
5406 /* XSTORM */
5407 section = ((u64)mapping) + offsetof(struct host_def_status_block,
5408 x_def_status_block);
5409 def_sb->x_def_status_block.status_block_id = id;
5410
5411 bp->def_x_idx = 0;
5412
5413 REG_WR(bp, BAR_XSTRORM_INTMEM +
5414 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
5415 REG_WR(bp, BAR_XSTRORM_INTMEM +
5416 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
5417 U64_HI(section));
5418 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port),
5419 BNX2X_BTR);
5420
5421 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
5422 REG_WR16(bp, BAR_XSTRORM_INTMEM +
5423 XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
5424
5425 bp->stat_pending = 0;
5426
5427 bnx2x_ack_sb(bp, id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
5428}
5429
5430static void bnx2x_update_coalesce(struct bnx2x *bp)
5431{
5432 int port = bp->port;
5433 int i;
5434
5435 for_each_queue(bp, i) {
5436
5437 /* HC_INDEX_U_ETH_RX_CQ_CONS */
5438 REG_WR8(bp, BAR_USTRORM_INTMEM +
5439 USTORM_SB_HC_TIMEOUT_OFFSET(port, i,
5440 HC_INDEX_U_ETH_RX_CQ_CONS),
5441 bp->rx_ticks_int/12);
5442 REG_WR16(bp, BAR_USTRORM_INTMEM +
5443 USTORM_SB_HC_DISABLE_OFFSET(port, i,
5444 HC_INDEX_U_ETH_RX_CQ_CONS),
5445 bp->rx_ticks_int ? 0 : 1);
5446
5447 /* HC_INDEX_C_ETH_TX_CQ_CONS */
5448 REG_WR8(bp, BAR_CSTRORM_INTMEM +
5449 CSTORM_SB_HC_TIMEOUT_OFFSET(port, i,
5450 HC_INDEX_C_ETH_TX_CQ_CONS),
5451 bp->tx_ticks_int/12);
5452 REG_WR16(bp, BAR_CSTRORM_INTMEM +
5453 CSTORM_SB_HC_DISABLE_OFFSET(port, i,
5454 HC_INDEX_C_ETH_TX_CQ_CONS),
5455 bp->tx_ticks_int ? 0 : 1);
5456 }
5457}
5458
5459static void bnx2x_init_rx_rings(struct bnx2x *bp)
5460{
5461 u16 ring_prod;
5462 int i, j;
5463 int port = bp->port;
5464
5465 bp->rx_buf_use_size = bp->dev->mtu;
5466
5467 bp->rx_buf_use_size += bp->rx_offset + ETH_OVREHEAD;
5468 bp->rx_buf_size = bp->rx_buf_use_size + 64;
5469
5470 for_each_queue(bp, j) {
5471 struct bnx2x_fastpath *fp = &bp->fp[j];
5472
5473 fp->rx_bd_cons = 0;
5474 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5475
5476 for (i = 1; i <= NUM_RX_RINGS; i++) {
5477 struct eth_rx_bd *rx_bd;
5478
5479 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
5480 rx_bd->addr_hi =
5481 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
5482 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
5483 rx_bd->addr_lo =
5484 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
5485 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
5486
5487 }
5488
5489 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
5490 struct eth_rx_cqe_next_page *nextpg;
5491
5492 nextpg = (struct eth_rx_cqe_next_page *)
5493 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
5494 nextpg->addr_hi =
5495 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
5496 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
5497 nextpg->addr_lo =
5498 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
5499 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
5500 }
5501
5502 /* rx completion queue */
5503 fp->rx_comp_cons = ring_prod = 0;
5504
5505 for (i = 0; i < bp->rx_ring_size; i++) {
5506 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
5507 BNX2X_ERR("was only able to allocate "
5508 "%d rx skbs\n", i);
5509 break;
5510 }
5511 ring_prod = NEXT_RX_IDX(ring_prod);
5512 BUG_TRAP(ring_prod > i);
5513 }
5514
5515 fp->rx_bd_prod = fp->rx_comp_prod = ring_prod;
5516 fp->rx_pkt = fp->rx_calls = 0;
5517
5518 /* Warning! this will generate an interrupt (to the TSTORM) */
5519 /* must only be done when chip is initialized */
5520 REG_WR(bp, BAR_TSTRORM_INTMEM +
5521 TSTORM_RCQ_PROD_OFFSET(port, j), ring_prod);
5522 if (j != 0)
5523 continue;
5524
5525 REG_WR(bp, BAR_USTRORM_INTMEM +
5526 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port),
5527 U64_LO(fp->rx_comp_mapping));
5528 REG_WR(bp, BAR_USTRORM_INTMEM +
5529 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port) + 4,
5530 U64_HI(fp->rx_comp_mapping));
5531 }
5532}
5533
5534static void bnx2x_init_tx_ring(struct bnx2x *bp)
5535{
5536 int i, j;
5537
5538 for_each_queue(bp, j) {
5539 struct bnx2x_fastpath *fp = &bp->fp[j];
5540
5541 for (i = 1; i <= NUM_TX_RINGS; i++) {
5542 struct eth_tx_bd *tx_bd =
5543 &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
5544
5545 tx_bd->addr_hi =
5546 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
5547 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5548 tx_bd->addr_lo =
5549 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
5550 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5551 }
5552
5553 fp->tx_pkt_prod = 0;
5554 fp->tx_pkt_cons = 0;
5555 fp->tx_bd_prod = 0;
5556 fp->tx_bd_cons = 0;
5557 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
5558 fp->tx_pkt = 0;
5559 }
5560}
5561
5562static void bnx2x_init_sp_ring(struct bnx2x *bp)
5563{
5564 int port = bp->port;
5565
5566 spin_lock_init(&bp->spq_lock);
5567
5568 bp->spq_left = MAX_SPQ_PENDING;
5569 bp->spq_prod_idx = 0;
5570 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5571 bp->spq_prod_bd = bp->spq;
5572 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5573
5574 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PAGE_BASE_OFFSET(port),
5575 U64_LO(bp->spq_mapping));
5576 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PAGE_BASE_OFFSET(port) + 4,
5577 U64_HI(bp->spq_mapping));
5578
5579 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(port),
5580 bp->spq_prod_idx);
5581}
5582
5583static void bnx2x_init_context(struct bnx2x *bp)
5584{
5585 int i;
5586
5587 for_each_queue(bp, i) {
5588 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
5589 struct bnx2x_fastpath *fp = &bp->fp[i];
5590
5591 context->xstorm_st_context.tx_bd_page_base_hi =
5592 U64_HI(fp->tx_desc_mapping);
5593 context->xstorm_st_context.tx_bd_page_base_lo =
5594 U64_LO(fp->tx_desc_mapping);
5595 context->xstorm_st_context.db_data_addr_hi =
5596 U64_HI(fp->tx_prods_mapping);
5597 context->xstorm_st_context.db_data_addr_lo =
5598 U64_LO(fp->tx_prods_mapping);
5599
5600 context->ustorm_st_context.rx_bd_page_base_hi =
5601 U64_HI(fp->rx_desc_mapping);
5602 context->ustorm_st_context.rx_bd_page_base_lo =
5603 U64_LO(fp->rx_desc_mapping);
5604 context->ustorm_st_context.status_block_id = i;
5605 context->ustorm_st_context.sb_index_number =
5606 HC_INDEX_U_ETH_RX_CQ_CONS;
5607 context->ustorm_st_context.rcq_base_address_hi =
5608 U64_HI(fp->rx_comp_mapping);
5609 context->ustorm_st_context.rcq_base_address_lo =
5610 U64_LO(fp->rx_comp_mapping);
5611 context->ustorm_st_context.flags =
5612 USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT;
5613 context->ustorm_st_context.mc_alignment_size = 64;
5614 context->ustorm_st_context.num_rss = bp->num_queues;
5615
5616 context->cstorm_st_context.sb_index_number =
5617 HC_INDEX_C_ETH_TX_CQ_CONS;
5618 context->cstorm_st_context.status_block_id = i;
5619
5620 context->xstorm_ag_context.cdu_reserved =
5621 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
5622 CDU_REGION_NUMBER_XCM_AG,
5623 ETH_CONNECTION_TYPE);
5624 context->ustorm_ag_context.cdu_usage =
5625 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
5626 CDU_REGION_NUMBER_UCM_AG,
5627 ETH_CONNECTION_TYPE);
5628 }
5629}
5630
5631static void bnx2x_init_ind_table(struct bnx2x *bp)
5632{
5633 int port = bp->port;
5634 int i;
5635
5636 if (!is_multi(bp))
5637 return;
5638
5639 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
5640 REG_WR8(bp, TSTORM_INDIRECTION_TABLE_OFFSET(port) + i,
5641 i % bp->num_queues);
5642
5643 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5644}
5645
5646static void bnx2x_set_client_config(struct bnx2x *bp)
5647{
5648#ifdef BCM_VLAN
5649 int mode = bp->rx_mode;
5650#endif
5651 int i, port = bp->port;
5652 struct tstorm_eth_client_config tstorm_client = {0};
5653
5654 tstorm_client.mtu = bp->dev->mtu;
5655 tstorm_client.statistics_counter_id = 0;
5656 tstorm_client.config_flags =
5657 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
5658#ifdef BCM_VLAN
5659 if (mode && bp->vlgrp) {
5660 tstorm_client.config_flags |=
5661 TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE;
5662 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
5663 }
5664#endif
5665 if (mode != BNX2X_RX_MODE_PROMISC)
5666 tstorm_client.drop_flags =
5667 TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR;
5668
5669 for_each_queue(bp, i) {
5670 REG_WR(bp, BAR_TSTRORM_INTMEM +
5671 TSTORM_CLIENT_CONFIG_OFFSET(port, i),
5672 ((u32 *)&tstorm_client)[0]);
5673 REG_WR(bp, BAR_TSTRORM_INTMEM +
5674 TSTORM_CLIENT_CONFIG_OFFSET(port, i) + 4,
5675 ((u32 *)&tstorm_client)[1]);
5676 }
5677
5678/* DP(NETIF_MSG_IFUP, "tstorm_client: 0x%08x 0x%08x\n",
5679 ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]); */
5680}
5681
5682static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5683{
5684 int mode = bp->rx_mode;
5685 int port = bp->port;
5686 struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
5687 int i;
5688
5689 DP(NETIF_MSG_RX_STATUS, "rx mode is %d\n", mode);
5690
5691 switch (mode) {
5692 case BNX2X_RX_MODE_NONE: /* no Rx */
5693 tstorm_mac_filter.ucast_drop_all = 1;
5694 tstorm_mac_filter.mcast_drop_all = 1;
5695 tstorm_mac_filter.bcast_drop_all = 1;
5696 break;
5697 case BNX2X_RX_MODE_NORMAL:
5698 tstorm_mac_filter.bcast_accept_all = 1;
5699 break;
5700 case BNX2X_RX_MODE_ALLMULTI:
5701 tstorm_mac_filter.mcast_accept_all = 1;
5702 tstorm_mac_filter.bcast_accept_all = 1;
5703 break;
5704 case BNX2X_RX_MODE_PROMISC:
5705 tstorm_mac_filter.ucast_accept_all = 1;
5706 tstorm_mac_filter.mcast_accept_all = 1;
5707 tstorm_mac_filter.bcast_accept_all = 1;
5708 break;
5709 default:
5710 BNX2X_ERR("bad rx mode (%d)\n", mode);
5711 }
5712
5713 for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
5714 REG_WR(bp, BAR_TSTRORM_INTMEM +
5715 TSTORM_MAC_FILTER_CONFIG_OFFSET(port) + i * 4,
5716 ((u32 *)&tstorm_mac_filter)[i]);
5717
5718/* DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
5719 ((u32 *)&tstorm_mac_filter)[i]); */
5720 }
5721
5722 if (mode != BNX2X_RX_MODE_NONE)
5723 bnx2x_set_client_config(bp);
5724}
5725
5726static void bnx2x_init_internal(struct bnx2x *bp)
5727{
5728 int port = bp->port;
5729 struct tstorm_eth_function_common_config tstorm_config = {0};
5730 struct stats_indication_flags stats_flags = {0};
5731
5732 if (is_multi(bp)) {
5733 tstorm_config.config_flags = MULTI_FLAGS;
5734 tstorm_config.rss_result_mask = MULTI_MASK;
5735 }
5736
5737 REG_WR(bp, BAR_TSTRORM_INTMEM +
5738 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(port),
5739 (*(u32 *)&tstorm_config));
5740
5741/* DP(NETIF_MSG_IFUP, "tstorm_config: 0x%08x\n",
5742 (*(u32 *)&tstorm_config)); */
5743
5744 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
5745 bnx2x_set_storm_rx_mode(bp);
5746
5747 stats_flags.collect_eth = cpu_to_le32(1);
5748
5749 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port),
5750 ((u32 *)&stats_flags)[0]);
5751 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port) + 4,
5752 ((u32 *)&stats_flags)[1]);
5753
5754 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port),
5755 ((u32 *)&stats_flags)[0]);
5756 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port) + 4,
5757 ((u32 *)&stats_flags)[1]);
5758
5759 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port),
5760 ((u32 *)&stats_flags)[0]);
5761 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port) + 4,
5762 ((u32 *)&stats_flags)[1]);
5763
5764/* DP(NETIF_MSG_IFUP, "stats_flags: 0x%08x 0x%08x\n",
5765 ((u32 *)&stats_flags)[0], ((u32 *)&stats_flags)[1]); */
5766}
5767
5768static void bnx2x_nic_init(struct bnx2x *bp)
5769{
5770 int i;
5771
5772 for_each_queue(bp, i) {
5773 struct bnx2x_fastpath *fp = &bp->fp[i];
5774
5775 fp->state = BNX2X_FP_STATE_CLOSED;
5776 DP(NETIF_MSG_IFUP, "bnx2x_init_sb(%p,%p,%d);\n",
5777 bp, fp->status_blk, i);
5778 fp->index = i;
5779 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping, i);
5780 }
5781
5782 bnx2x_init_def_sb(bp, bp->def_status_blk,
5783 bp->def_status_blk_mapping, 0x10);
5784 bnx2x_update_coalesce(bp);
5785 bnx2x_init_rx_rings(bp);
5786 bnx2x_init_tx_ring(bp);
5787 bnx2x_init_sp_ring(bp);
5788 bnx2x_init_context(bp);
5789 bnx2x_init_internal(bp);
5790 bnx2x_init_stats(bp);
5791 bnx2x_init_ind_table(bp);
5792 bnx2x_int_enable(bp);
5793
5794}
5795
5796/* end of nic init */
5797
5798/*
5799 * gzip service functions
5800 */
5801
5802static int bnx2x_gunzip_init(struct bnx2x *bp)
5803{
5804 bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
5805 &bp->gunzip_mapping);
5806 if (bp->gunzip_buf == NULL)
5807 goto gunzip_nomem1;
5808
5809 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5810 if (bp->strm == NULL)
5811 goto gunzip_nomem2;
5812
5813 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
5814 GFP_KERNEL);
5815 if (bp->strm->workspace == NULL)
5816 goto gunzip_nomem3;
5817
5818 return 0;
5819
5820gunzip_nomem3:
5821 kfree(bp->strm);
5822 bp->strm = NULL;
5823
5824gunzip_nomem2:
5825 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
5826 bp->gunzip_mapping);
5827 bp->gunzip_buf = NULL;
5828
5829gunzip_nomem1:
5830 printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
5831 " uncompression\n", bp->dev->name);
5832 return -ENOMEM;
5833}
5834
5835static void bnx2x_gunzip_end(struct bnx2x *bp)
5836{
5837 kfree(bp->strm->workspace);
5838
5839 kfree(bp->strm);
5840 bp->strm = NULL;
5841
5842 if (bp->gunzip_buf) {
5843 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
5844 bp->gunzip_mapping);
5845 bp->gunzip_buf = NULL;
5846 }
5847}
5848
5849static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
5850{
5851 int n, rc;
5852
5853 /* check gzip header */
5854 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
5855 return -EINVAL;
5856
5857 n = 10;
5858
5859#define FNAME 0x8
5860
5861 if (zbuf[3] & FNAME)
5862 while ((zbuf[n++] != 0) && (n < len));
5863
5864 bp->strm->next_in = zbuf + n;
5865 bp->strm->avail_in = len - n;
5866 bp->strm->next_out = bp->gunzip_buf;
5867 bp->strm->avail_out = FW_BUF_SIZE;
5868
5869 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5870 if (rc != Z_OK)
5871 return rc;
5872
5873 rc = zlib_inflate(bp->strm, Z_FINISH);
5874 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5875 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
5876 bp->dev->name, bp->strm->msg);
5877
5878 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5879 if (bp->gunzip_outlen & 0x3)
5880 printk(KERN_ERR PFX "%s: Firmware decompression error:"
5881 " gunzip_outlen (%d) not aligned\n",
5882 bp->dev->name, bp->gunzip_outlen);
5883 bp->gunzip_outlen >>= 2;
5884
5885 zlib_inflateEnd(bp->strm);
5886
5887 if (rc == Z_STREAM_END)
5888 return 0;
5889
5890 return rc;
5891}
5892
5893/* nic load/unload */
5894
5895/*
5896 * general service functions
5897 */
5898
5899/* send a NIG loopback debug packet */
5900static void bnx2x_lb_pckt(struct bnx2x *bp)
5901{
5902#ifdef USE_DMAE
5903 u32 wb_write[3];
5904#endif
5905
5906 /* Ethernet source and destination addresses */
5907#ifdef USE_DMAE
5908 wb_write[0] = 0x55555555;
5909 wb_write[1] = 0x55555555;
5910 wb_write[2] = 0x20; /* SOP */
5911 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5912#else
5913 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB, 0x55555555);
5914 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB + 4, 0x55555555);
5915 /* SOP */
5916 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB + 8, 0x20);
5917#endif
5918
5919 /* NON-IP protocol */
5920#ifdef USE_DMAE
5921 wb_write[0] = 0x09000000;
5922 wb_write[1] = 0x55555555;
5923 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5924 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5925#else
5926 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB, 0x09000000);
5927 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB + 4, 0x55555555);
5928 /* EOP, eop_bvalid = 0 */
5929 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB + 8, 0x10);
5930#endif
5931}
5932
5933/* some of the internal memories
5934 * are not directly readable from the driver
5935 * to test them we send debug packets
5936 */
5937static int bnx2x_int_mem_test(struct bnx2x *bp)
5938{
5939 int factor;
5940 int count, i;
5941 u32 val = 0;
5942
5943 switch (CHIP_REV(bp)) {
5944 case CHIP_REV_EMUL:
5945 factor = 200;
5946 break;
5947 case CHIP_REV_FPGA:
5948 factor = 120;
5949 break;
5950 default:
5951 factor = 1;
5952 break;
5953 }
5954
5955 DP(NETIF_MSG_HW, "start part1\n");
5956
5957 /* Disable inputs of parser neighbor blocks */
5958 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5959 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5960 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5961 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
5962
5963 /* Write 0 to parser credits for CFC search request */
5964 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5965
5966 /* send Ethernet packet */
5967 bnx2x_lb_pckt(bp);
5968
5969 /* TODO do i reset NIG statistic? */
5970 /* Wait until NIG register shows 1 packet of size 0x10 */
5971 count = 1000 * factor;
5972 while (count) {
5973#ifdef BNX2X_DMAE_RD
5974 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5975 val = *bnx2x_sp(bp, wb_data[0]);
5976#else
5977 val = REG_RD(bp, NIG_REG_STAT2_BRB_OCTET);
5978 REG_RD(bp, NIG_REG_STAT2_BRB_OCTET + 4);
5979#endif
5980 if (val == 0x10)
5981 break;
5982
5983 msleep(10);
5984 count--;
5985 }
5986 if (val != 0x10) {
5987 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5988 return -1;
5989 }
5990
5991 /* Wait until PRS register shows 1 packet */
5992 count = 1000 * factor;
5993 while (count) {
5994 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5995
5996 if (val == 1)
5997 break;
5998
5999 msleep(10);
6000 count--;
6001 }
6002 if (val != 0x1) {
6003 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6004 return -2;
6005 }
6006
6007 /* Reset and init BRB, PRS */
6008 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x3);
6009 msleep(50);
6010 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x3);
6011 msleep(50);
6012 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
6013 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
6014
6015 DP(NETIF_MSG_HW, "part2\n");
6016
6017 /* Disable inputs of parser neighbor blocks */
6018 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6019 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6020 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6021 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
6022
6023 /* Write 0 to parser credits for CFC search request */
6024 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6025
6026 /* send 10 Ethernet packets */
6027 for (i = 0; i < 10; i++)
6028 bnx2x_lb_pckt(bp);
6029
6030 /* Wait until NIG register shows 10 + 1
6031 packets of size 11*0x10 = 0xb0 */
6032 count = 1000 * factor;
6033 while (count) {
6034#ifdef BNX2X_DMAE_RD
6035 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6036 val = *bnx2x_sp(bp, wb_data[0]);
6037#else
6038 val = REG_RD(bp, NIG_REG_STAT2_BRB_OCTET);
6039 REG_RD(bp, NIG_REG_STAT2_BRB_OCTET + 4);
6040#endif
6041 if (val == 0xb0)
6042 break;
6043
6044 msleep(10);
6045 count--;
6046 }
6047 if (val != 0xb0) {
6048 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6049 return -3;
6050 }
6051
6052 /* Wait until PRS register shows 2 packets */
6053 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6054 if (val != 2)
6055 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6056
6057 /* Write 1 to parser credits for CFC search request */
6058 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6059
6060 /* Wait until PRS register shows 3 packets */
6061 msleep(10 * factor);
6062 /* Wait until NIG register shows 1 packet of size 0x10 */
6063 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6064 if (val != 3)
6065 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6066
6067 /* clear NIG EOP FIFO */
6068 for (i = 0; i < 11; i++)
6069 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6070 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6071 if (val != 1) {
6072 BNX2X_ERR("clear of NIG failed\n");
6073 return -4;
6074 }
6075
6076 /* Reset and init BRB, PRS, NIG */
6077 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6078 msleep(50);
6079 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6080 msleep(50);
6081 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
6082 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
6083#ifndef BCM_ISCSI
6084 /* set NIC mode */
6085 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6086#endif
6087
6088 /* Enable inputs of parser neighbor blocks */
6089 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6090 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6091 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6092 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x1);
6093
6094 DP(NETIF_MSG_HW, "done\n");
6095
6096 return 0; /* OK */
6097}
6098
6099static void enable_blocks_attention(struct bnx2x *bp)
6100{
6101 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6102 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6103 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6104 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6105 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6106 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6107 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6108 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6109 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6110/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6111/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6112 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6113 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6114 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6115/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6116/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6117 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6118 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6119 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6120 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6121/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6122/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6123 REG_WR(bp, PXP2_REG_PXP2_INT_MASK, 0x480000);
6124 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6125 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6126 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6127/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6128/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
6129 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6130 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6131/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6132 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18); /* bit 3,4 masked */
6133}
6134
6135static int bnx2x_function_init(struct bnx2x *bp, int mode)
6136{
6137 int func = bp->port;
6138 int port = func ? PORT1 : PORT0;
6139 u32 val, i;
6140#ifdef USE_DMAE
6141 u32 wb_write[2];
6142#endif
6143
6144 DP(BNX2X_MSG_MCP, "function is %d mode is %x\n", func, mode);
6145 if ((func != 0) && (func != 1)) {
6146 BNX2X_ERR("BAD function number (%d)\n", func);
6147 return -ENODEV;
6148 }
6149
6150 bnx2x_gunzip_init(bp);
6151
6152 if (mode & 0x1) { /* init common */
6153 DP(BNX2X_MSG_MCP, "starting common init func %d mode %x\n",
6154 func, mode);
6155 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6156 0xffffffff);
6157 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6158 0xfffc);
6159 bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END);
6160
6161 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
6162 msleep(30);
6163 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
6164
6165 bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END);
6166 bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END);
6167
6168 bnx2x_init_pxp(bp);
6169
6170 if (CHIP_REV(bp) == CHIP_REV_Ax) {
6171 /* enable HW interrupt from PXP on USDM
6172 overflow bit 16 on INT_MASK_0 */
6173 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6174 }
6175
6176#ifdef __BIG_ENDIAN
6177 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6178 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6179 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6180 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6181 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6182 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 1);
6183
6184/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6185 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6186 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6187 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6188 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6189#endif
6190
6191#ifndef BCM_ISCSI
6192 /* set NIC mode */
6193 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6194#endif
6195
6196 REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 5);
6197#ifdef BCM_ISCSI
6198 REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
6199 REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
6200 REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
6201#endif
6202
6203 bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END);
6204
6205 /* let the HW do it's magic ... */
6206 msleep(100);
6207 /* finish PXP init
6208 (can be moved up if we want to use the DMAE) */
6209 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6210 if (val != 1) {
6211 BNX2X_ERR("PXP2 CFG failed\n");
6212 return -EBUSY;
6213 }
6214
6215 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6216 if (val != 1) {
6217 BNX2X_ERR("PXP2 RD_INIT failed\n");
6218 return -EBUSY;
6219 }
6220
6221 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6222 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6223
6224 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
6225
6226 bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END);
6227 bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END);
6228 bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END);
6229 bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END);
6230
6231#ifdef BNX2X_DMAE_RD
6232 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6233 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6234 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6235 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6236#else
6237 REG_RD(bp, XSEM_REG_PASSIVE_BUFFER);
6238 REG_RD(bp, XSEM_REG_PASSIVE_BUFFER + 4);
6239 REG_RD(bp, XSEM_REG_PASSIVE_BUFFER + 8);
6240 REG_RD(bp, CSEM_REG_PASSIVE_BUFFER);
6241 REG_RD(bp, CSEM_REG_PASSIVE_BUFFER + 4);
6242 REG_RD(bp, CSEM_REG_PASSIVE_BUFFER + 8);
6243 REG_RD(bp, TSEM_REG_PASSIVE_BUFFER);
6244 REG_RD(bp, TSEM_REG_PASSIVE_BUFFER + 4);
6245 REG_RD(bp, TSEM_REG_PASSIVE_BUFFER + 8);
6246 REG_RD(bp, USEM_REG_PASSIVE_BUFFER);
6247 REG_RD(bp, USEM_REG_PASSIVE_BUFFER + 4);
6248 REG_RD(bp, USEM_REG_PASSIVE_BUFFER + 8);
6249#endif
6250 bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
6251 /* soft reset pulse */
6252 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6253 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6254
6255#ifdef BCM_ISCSI
6256 bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END);
6257#endif
6258 bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END);
6259 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_BITS);
6260 if (CHIP_REV(bp) == CHIP_REV_Ax) {
6261 /* enable hw interrupt from doorbell Q */
6262 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6263 }
6264
6265 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
6266
6267 if (CHIP_REV_IS_SLOW(bp)) {
6268 /* fix for emulation and FPGA for no pause */
6269 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513);
6270 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 513);
6271 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0);
6272 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0);
6273 }
6274
6275 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
6276
6277 bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END);
6278 bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END);
6279 bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
6280 bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
6281
6282 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
6283 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
6284 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
6285 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
6286
6287 bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
6288 bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
6289 bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END);
6290 bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END);
6291
6292 /* sync semi rtc */
6293 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6294 0x80000000);
6295 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6296 0x80000000);
6297
6298 bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END);
6299 bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END);
6300 bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END);
6301
6302 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6303 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
6304 REG_WR(bp, i, 0xc0cac01a);
6305 /* TODO: replace with something meaningful */
6306 }
6307 /* SRCH COMMON comes here */
6308 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6309
6310 if (sizeof(union cdu_context) != 1024) {
6311 /* we currently assume that a context is 1024 bytes */
6312 printk(KERN_ALERT PFX "please adjust the size of"
6313 " cdu_context(%ld)\n",
6314 (long)sizeof(union cdu_context));
6315 }
6316 val = (4 << 24) + (0 << 12) + 1024;
6317 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6318 bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END);
6319
6320 bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
6321 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6322
6323 bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
6324 bnx2x_init_block(bp, MISC_AEU_COMMON_START,
6325 MISC_AEU_COMMON_END);
6326 /* RXPCS COMMON comes here */
6327 /* EMAC0 COMMON comes here */
6328 /* EMAC1 COMMON comes here */
6329 /* DBU COMMON comes here */
6330 /* DBG COMMON comes here */
6331 bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END);
6332
6333 if (CHIP_REV_IS_SLOW(bp))
6334 msleep(200);
6335
6336 /* finish CFC init */
6337 val = REG_RD(bp, CFC_REG_LL_INIT_DONE);
6338 if (val != 1) {
6339 BNX2X_ERR("CFC LL_INIT failed\n");
6340 return -EBUSY;
6341 }
6342
6343 val = REG_RD(bp, CFC_REG_AC_INIT_DONE);
6344 if (val != 1) {
6345 BNX2X_ERR("CFC AC_INIT failed\n");
6346 return -EBUSY;
6347 }
6348
6349 val = REG_RD(bp, CFC_REG_CAM_INIT_DONE);
6350 if (val != 1) {
6351 BNX2X_ERR("CFC CAM_INIT failed\n");
6352 return -EBUSY;
6353 }
6354
6355 REG_WR(bp, CFC_REG_DEBUG0, 0);
6356
6357 /* read NIG statistic
6358 to see if this is our first up since powerup */
6359#ifdef BNX2X_DMAE_RD
6360 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6361 val = *bnx2x_sp(bp, wb_data[0]);
6362#else
6363 val = REG_RD(bp, NIG_REG_STAT2_BRB_OCTET);
6364 REG_RD(bp, NIG_REG_STAT2_BRB_OCTET + 4);
6365#endif
6366 /* do internal memory self test */
6367 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6368 BNX2X_ERR("internal mem selftest failed\n");
6369 return -EBUSY;
6370 }
6371
6372 /* clear PXP2 attentions */
6373 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR);
6374
6375 enable_blocks_attention(bp);
6376 /* enable_blocks_parity(bp); */
6377
6378 switch (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
6379 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
6380 /* Fan failure is indicated by SPIO 5 */
6381 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
6382 MISC_REGISTERS_SPIO_INPUT_HI_Z);
6383
6384 /* set to active low mode */
6385 val = REG_RD(bp, MISC_REG_SPIO_INT);
6386 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
6387 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
6388 REG_WR(bp, MISC_REG_SPIO_INT, val);
6389
6390 /* enable interrupt to signal the IGU */
6391 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6392 val |= (1 << MISC_REGISTERS_SPIO_5);
6393 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6394 break;
6395
6396 default:
6397 break;
6398 }
6399
6400 } /* end of common init */
6401
6402 /* per port init */
6403
6404 /* the phys address is shifted right 12 bits and has an added
6405 1=valid bit added to the 53rd bit
6406 then since this is a wide register(TM)
6407 we split it into two 32 bit writes
6408 */
6409#define RQ_ONCHIP_AT_PORT_SIZE 384
6410#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
6411#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
6412#define PXP_ONE_ILT(x) ((x << 10) | x)
6413
6414 DP(BNX2X_MSG_MCP, "starting per-function init port is %x\n", func);
6415
6416 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + func*4, 0);
6417
6418 /* Port PXP comes here */
6419 /* Port PXP2 comes here */
6420
6421 /* Offset is
6422 * Port0 0
6423 * Port1 384 */
6424 i = func * RQ_ONCHIP_AT_PORT_SIZE;
6425#ifdef USE_DMAE
6426 wb_write[0] = ONCHIP_ADDR1(bnx2x_sp_mapping(bp, context));
6427 wb_write[1] = ONCHIP_ADDR2(bnx2x_sp_mapping(bp, context));
6428 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
6429#else
6430 REG_WR_IND(bp, PXP2_REG_RQ_ONCHIP_AT + i*8,
6431 ONCHIP_ADDR1(bnx2x_sp_mapping(bp, context)));
6432 REG_WR_IND(bp, PXP2_REG_RQ_ONCHIP_AT + i*8 + 4,
6433 ONCHIP_ADDR2(bnx2x_sp_mapping(bp, context)));
6434#endif
6435 REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4, PXP_ONE_ILT(i));
6436
6437#ifdef BCM_ISCSI
6438 /* Port0 1
6439 * Port1 385 */
6440 i++;
6441 wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
6442 wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
6443 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
6444 REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
6445
6446 /* Port0 2
6447 * Port1 386 */
6448 i++;
6449 wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
6450 wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
6451 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
6452 REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
6453
6454 /* Port0 3
6455 * Port1 387 */
6456 i++;
6457 wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
6458 wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
6459 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
6460 REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
6461#endif
6462
6463 /* Port TCM comes here */
6464 /* Port UCM comes here */
6465 /* Port CCM comes here */
6466 bnx2x_init_block(bp, func ? XCM_PORT1_START : XCM_PORT0_START,
6467 func ? XCM_PORT1_END : XCM_PORT0_END);
6468
6469#ifdef USE_DMAE
6470 wb_write[0] = 0;
6471 wb_write[1] = 0;
6472#endif
6473 for (i = 0; i < 32; i++) {
6474 REG_WR(bp, QM_REG_BASEADDR + (func*32 + i)*4, 1024 * 4 * i);
6475#ifdef USE_DMAE
6476 REG_WR_DMAE(bp, QM_REG_PTRTBL + (func*32 + i)*8, wb_write, 2);
6477#else
6478 REG_WR_IND(bp, QM_REG_PTRTBL + (func*32 + i)*8, 0);
6479 REG_WR_IND(bp, QM_REG_PTRTBL + (func*32 + i)*8 + 4, 0);
6480#endif
6481 }
6482 REG_WR(bp, QM_REG_CONNNUM_0 + func*4, 1024/16 - 1);
6483
6484 /* Port QM comes here */
6485
6486#ifdef BCM_ISCSI
6487 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
6488 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
6489
6490 bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START,
6491 func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
6492#endif
6493 /* Port DQ comes here */
6494 /* Port BRB1 comes here */
6495 bnx2x_init_block(bp, func ? PRS_PORT1_START : PRS_PORT0_START,
6496 func ? PRS_PORT1_END : PRS_PORT0_END);
6497 /* Port TSDM comes here */
6498 /* Port CSDM comes here */
6499 /* Port USDM comes here */
6500 /* Port XSDM comes here */
6501 bnx2x_init_block(bp, func ? TSEM_PORT1_START : TSEM_PORT0_START,
6502 func ? TSEM_PORT1_END : TSEM_PORT0_END);
6503 bnx2x_init_block(bp, func ? USEM_PORT1_START : USEM_PORT0_START,
6504 func ? USEM_PORT1_END : USEM_PORT0_END);
6505 bnx2x_init_block(bp, func ? CSEM_PORT1_START : CSEM_PORT0_START,
6506 func ? CSEM_PORT1_END : CSEM_PORT0_END);
6507 bnx2x_init_block(bp, func ? XSEM_PORT1_START : XSEM_PORT0_START,
6508 func ? XSEM_PORT1_END : XSEM_PORT0_END);
6509 /* Port UPB comes here */
6510 /* Port XSDM comes here */
6511 bnx2x_init_block(bp, func ? PBF_PORT1_START : PBF_PORT0_START,
6512 func ? PBF_PORT1_END : PBF_PORT0_END);
6513
6514 /* configure PBF to work without PAUSE mtu 9000 */
6515 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + func*4, 0);
6516
6517 /* update threshold */
6518 REG_WR(bp, PBF_REG_P0_ARB_THRSH + func*4, (9040/16));
6519 /* update init credit */
6520 REG_WR(bp, PBF_REG_P0_INIT_CRD + func*4, (9040/16) + 553 - 22);
6521
6522 /* probe changes */
6523 REG_WR(bp, PBF_REG_INIT_P0 + func*4, 1);
6524 msleep(5);
6525 REG_WR(bp, PBF_REG_INIT_P0 + func*4, 0);
6526
6527#ifdef BCM_ISCSI
6528 /* tell the searcher where the T2 table is */
6529 REG_WR(bp, SRC_REG_COUNTFREE0 + func*4, 16*1024/64);
6530
6531 wb_write[0] = U64_LO(bp->t2_mapping);
6532 wb_write[1] = U64_HI(bp->t2_mapping);
6533 REG_WR_DMAE(bp, SRC_REG_FIRSTFREE0 + func*4, wb_write, 2);
6534 wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64);
6535 wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64);
6536 REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2);
6537
6538 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10);
6539 /* Port SRCH comes here */
6540#endif
6541 /* Port CDU comes here */
6542 /* Port CFC comes here */
6543 bnx2x_init_block(bp, func ? HC_PORT1_START : HC_PORT0_START,
6544 func ? HC_PORT1_END : HC_PORT0_END);
6545 bnx2x_init_block(bp, func ? MISC_AEU_PORT1_START :
6546 MISC_AEU_PORT0_START,
6547 func ? MISC_AEU_PORT1_END : MISC_AEU_PORT0_END);
6548 /* Port PXPCS comes here */
6549 /* Port EMAC0 comes here */
6550 /* Port EMAC1 comes here */
6551 /* Port DBU comes here */
6552 /* Port DBG comes here */
6553 bnx2x_init_block(bp, func ? NIG_PORT1_START : NIG_PORT0_START,
6554 func ? NIG_PORT1_END : NIG_PORT0_END);
6555 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + func*4, 1);
6556 /* Port MCP comes here */
6557 /* Port DMAE comes here */
6558
6559 switch (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
6560 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
6561 /* add SPIO 5 to group 0 */
6562 val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6563 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6564 REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val);
6565 break;
6566
6567 default:
6568 break;
6569 }
6570
6571 bnx2x_link_reset(bp);
6572
6573 /* Reset PCIE errors for debug */
6574 REG_WR(bp, 0x2114, 0xffffffff);
6575 REG_WR(bp, 0x2120, 0xffffffff);
6576 REG_WR(bp, 0x2814, 0xffffffff);
6577
6578 /* !!! move to init_values.h */
6579 REG_WR(bp, XSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1);
6580 REG_WR(bp, USDM_REG_INIT_CREDIT_PXP_CTRL, 0x1);
6581 REG_WR(bp, CSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1);
6582 REG_WR(bp, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1);
6583
6584 REG_WR(bp, DBG_REG_PCI_REQ_CREDIT, 0x1);
6585 REG_WR(bp, TM_REG_PCIARB_CRDCNT_VAL, 0x1);
6586 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
6587 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x0);
6588
6589 bnx2x_gunzip_end(bp);
6590
6591 if (!nomcp) {
6592 port = bp->port;
6593
6594 bp->fw_drv_pulse_wr_seq =
6595 (SHMEM_RD(bp, func_mb[port].drv_pulse_mb) &
6596 DRV_PULSE_SEQ_MASK);
6597 bp->fw_mb = SHMEM_RD(bp, func_mb[port].fw_mb_param);
6598 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x fw_mb 0x%x\n",
6599 bp->fw_drv_pulse_wr_seq, bp->fw_mb);
6600 } else {
6601 bp->fw_mb = 0;
6602 }
6603
6604 return 0;
6605}
6606
6607/* send the MCP a request, block until there is a reply */
6608static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
6609{
6610 int port = bp->port;
6611 u32 seq = ++bp->fw_seq;
6612 u32 rc = 0;
6613
6614 SHMEM_WR(bp, func_mb[port].drv_mb_header, (command | seq));
6615 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
6616
6617 /* let the FW do it's magic ... */
6618 msleep(100); /* TBD */
6619
6620 if (CHIP_REV_IS_SLOW(bp))
6621 msleep(900);
6622
6623 rc = SHMEM_RD(bp, func_mb[port].fw_mb_header);
6624 DP(BNX2X_MSG_MCP, "read (%x) seq is (%x) from FW MB\n", rc, seq);
6625
6626 /* is this a reply to our command? */
6627 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
6628 rc &= FW_MSG_CODE_MASK;
6629
6630 } else {
6631 /* FW BUG! */
6632 BNX2X_ERR("FW failed to respond!\n");
6633 bnx2x_fw_dump(bp);
6634 rc = 0;
6635 }
6636
6637 return rc;
6638}
6639
6640static void bnx2x_free_mem(struct bnx2x *bp)
6641{
6642
6643#define BNX2X_PCI_FREE(x, y, size) \
6644 do { \
6645 if (x) { \
6646 pci_free_consistent(bp->pdev, size, x, y); \
6647 x = NULL; \
6648 y = 0; \
6649 } \
6650 } while (0)
6651
6652#define BNX2X_FREE(x) \
6653 do { \
6654 if (x) { \
6655 vfree(x); \
6656 x = NULL; \
6657 } \
6658 } while (0)
6659
6660 int i;
6661
6662 /* fastpath */
6663 for_each_queue(bp, i) {
6664
6665 /* Status blocks */
6666 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
6667 bnx2x_fp(bp, i, status_blk_mapping),
6668 sizeof(struct host_status_block) +
6669 sizeof(struct eth_tx_db_data));
6670
6671 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
6672 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
6673 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
6674 bnx2x_fp(bp, i, tx_desc_mapping),
6675 sizeof(struct eth_tx_bd) * NUM_TX_BD);
6676
6677 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
6678 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
6679 bnx2x_fp(bp, i, rx_desc_mapping),
6680 sizeof(struct eth_rx_bd) * NUM_RX_BD);
6681
6682 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
6683 bnx2x_fp(bp, i, rx_comp_mapping),
6684 sizeof(struct eth_fast_path_rx_cqe) *
6685 NUM_RCQ_BD);
6686 }
6687
6688 BNX2X_FREE(bp->fp);
6689
6690 /* end of fastpath */
6691
6692 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6693 (sizeof(struct host_def_status_block)));
6694
6695 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6696 (sizeof(struct bnx2x_slowpath)));
6697
6698#ifdef BCM_ISCSI
6699 BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024);
6700 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024);
6701 BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024);
6702 BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024);
6703#endif
6704 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, PAGE_SIZE);
6705
6706#undef BNX2X_PCI_FREE
6707#undef BNX2X_KFREE
6708}
6709
6710static int bnx2x_alloc_mem(struct bnx2x *bp)
6711{
6712
6713#define BNX2X_PCI_ALLOC(x, y, size) \
6714 do { \
6715 x = pci_alloc_consistent(bp->pdev, size, y); \
6716 if (x == NULL) \
6717 goto alloc_mem_err; \
6718 memset(x, 0, size); \
6719 } while (0)
6720
6721#define BNX2X_ALLOC(x, size) \
6722 do { \
6723 x = vmalloc(size); \
6724 if (x == NULL) \
6725 goto alloc_mem_err; \
6726 memset(x, 0, size); \
6727 } while (0)
6728
6729 int i;
6730
6731 /* fastpath */
6732 BNX2X_ALLOC(bp->fp, sizeof(struct bnx2x_fastpath) * bp->num_queues);
6733
6734 for_each_queue(bp, i) {
6735 bnx2x_fp(bp, i, bp) = bp;
6736
6737 /* Status blocks */
6738 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
6739 &bnx2x_fp(bp, i, status_blk_mapping),
6740 sizeof(struct host_status_block) +
6741 sizeof(struct eth_tx_db_data));
6742
6743 bnx2x_fp(bp, i, hw_tx_prods) =
6744 (void *)(bnx2x_fp(bp, i, status_blk) + 1);
6745
6746 bnx2x_fp(bp, i, tx_prods_mapping) =
6747 bnx2x_fp(bp, i, status_blk_mapping) +
6748 sizeof(struct host_status_block);
6749
6750 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
6751 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
6752 sizeof(struct sw_tx_bd) * NUM_TX_BD);
6753 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
6754 &bnx2x_fp(bp, i, tx_desc_mapping),
6755 sizeof(struct eth_tx_bd) * NUM_TX_BD);
6756
6757 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
6758 sizeof(struct sw_rx_bd) * NUM_RX_BD);
6759 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
6760 &bnx2x_fp(bp, i, rx_desc_mapping),
6761 sizeof(struct eth_rx_bd) * NUM_RX_BD);
6762
6763 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
6764 &bnx2x_fp(bp, i, rx_comp_mapping),
6765 sizeof(struct eth_fast_path_rx_cqe) *
6766 NUM_RCQ_BD);
6767
6768 }
6769 /* end of fastpath */
6770
6771 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6772 sizeof(struct host_def_status_block));
6773
6774 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6775 sizeof(struct bnx2x_slowpath));
6776
6777#ifdef BCM_ISCSI
6778 BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);
6779
6780 /* Initialize T1 */
6781 for (i = 0; i < 64*1024; i += 64) {
6782 *(u64 *)((char *)bp->t1 + i + 56) = 0x0UL;
6783 *(u64 *)((char *)bp->t1 + i + 3) = 0x0UL;
6784 }
6785
6786 /* allocate searcher T2 table
6787 we allocate 1/4 of alloc num for T2
6788 (which is not entered into the ILT) */
6789 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);
6790
6791 /* Initialize T2 */
6792 for (i = 0; i < 16*1024; i += 64)
6793 * (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
6794
6795 /* now fixup the last line in the block to point to the next block */
6796 *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping;
6797
6798 /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */
6799 BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024);
6800
6801 /* QM queues (128*MAX_CONN) */
6802 BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
6803#endif
6804
6805 /* Slow path ring */
6806 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6807
6808 return 0;
6809
6810alloc_mem_err:
6811 bnx2x_free_mem(bp);
6812 return -ENOMEM;
6813
6814#undef BNX2X_PCI_ALLOC
6815#undef BNX2X_ALLOC
6816}
6817
6818static void bnx2x_free_tx_skbs(struct bnx2x *bp)
6819{
6820 int i;
6821
6822 for_each_queue(bp, i) {
6823 struct bnx2x_fastpath *fp = &bp->fp[i];
6824
6825 u16 bd_cons = fp->tx_bd_cons;
6826 u16 sw_prod = fp->tx_pkt_prod;
6827 u16 sw_cons = fp->tx_pkt_cons;
6828
6829 BUG_TRAP(fp->tx_buf_ring != NULL);
6830
6831 while (sw_cons != sw_prod) {
6832 bd_cons = bnx2x_free_tx_pkt(bp, fp, TX_BD(sw_cons));
6833 sw_cons++;
6834 }
6835 }
6836}
6837
6838static void bnx2x_free_rx_skbs(struct bnx2x *bp)
6839{
6840 int i, j;
6841
6842 for_each_queue(bp, j) {
6843 struct bnx2x_fastpath *fp = &bp->fp[j];
6844
6845 BUG_TRAP(fp->rx_buf_ring != NULL);
6846
6847 for (i = 0; i < NUM_RX_BD; i++) {
6848 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
6849 struct sk_buff *skb = rx_buf->skb;
6850
6851 if (skb == NULL)
6852 continue;
6853
6854 pci_unmap_single(bp->pdev,
6855 pci_unmap_addr(rx_buf, mapping),
6856 bp->rx_buf_use_size,
6857 PCI_DMA_FROMDEVICE);
6858
6859 rx_buf->skb = NULL;
6860 dev_kfree_skb(skb);
6861 }
6862 }
6863}
6864
6865static void bnx2x_free_skbs(struct bnx2x *bp)
6866{
6867 bnx2x_free_tx_skbs(bp);
6868 bnx2x_free_rx_skbs(bp);
6869}
6870
6871static void bnx2x_free_msix_irqs(struct bnx2x *bp)
6872{
6873 int i;
6874
6875 free_irq(bp->msix_table[0].vector, bp->dev);
6876 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
6877 bp->msix_table[0].vector);
6878
6879 for_each_queue(bp, i) {
6880 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq "
6881 "state(%x)\n", i, bp->msix_table[i + 1].vector,
6882 bnx2x_fp(bp, i, state));
6883
6884 if (bnx2x_fp(bp, i, state) != BNX2X_FP_STATE_CLOSED)
6885 BNX2X_ERR("IRQ of fp #%d being freed while "
6886 "state != closed\n", i);
6887
6888 free_irq(bp->msix_table[i + 1].vector, &bp->fp[i]);
6889 }
6890
6891}
6892
6893static void bnx2x_free_irq(struct bnx2x *bp)
6894{
6895
6896 if (bp->flags & USING_MSIX_FLAG) {
6897
6898 bnx2x_free_msix_irqs(bp);
6899 pci_disable_msix(bp->pdev);
6900
6901 bp->flags &= ~USING_MSIX_FLAG;
6902
6903 } else
6904 free_irq(bp->pdev->irq, bp->dev);
6905}
6906
6907static int bnx2x_enable_msix(struct bnx2x *bp)
6908{
6909
6910 int i;
6911
6912 bp->msix_table[0].entry = 0;
6913 for_each_queue(bp, i)
6914 bp->msix_table[i + 1].entry = i + 1;
6915
6916 if (pci_enable_msix(bp->pdev, &bp->msix_table[0],
6917 bp->num_queues + 1)){
6918 BNX2X_LOG("failed to enable MSI-X\n");
6919 return -1;
6920
6921 }
6922
6923 bp->flags |= USING_MSIX_FLAG;
6924
6925 return 0;
6926
6927}
6928
6929
6930static int bnx2x_req_msix_irqs(struct bnx2x *bp)
6931{
6932
6933 int i, rc;
6934
6935 rc = request_irq(bp->msix_table[0].vector, bnx2x_msix_sp_int, 0,
6936 bp->dev->name, bp->dev);
6937
6938 if (rc) {
6939 BNX2X_ERR("request sp irq failed\n");
6940 return -EBUSY;
6941 }
6942
6943 for_each_queue(bp, i) {
6944 rc = request_irq(bp->msix_table[i + 1].vector,
6945 bnx2x_msix_fp_int, 0,
6946 bp->dev->name, &bp->fp[i]);
6947
6948 if (rc) {
6949 BNX2X_ERR("request fp #%d irq failed "
6950 "rc %d\n", i, rc);
6951 bnx2x_free_msix_irqs(bp);
6952 return -EBUSY;
6953 }
6954
6955 bnx2x_fp(bp, i, state) = BNX2X_FP_STATE_IRQ;
6956
6957 }
6958
6959 return 0;
6960
6961}
6962
6963static int bnx2x_req_irq(struct bnx2x *bp)
6964{
6965
6966 int rc = request_irq(bp->pdev->irq, bnx2x_interrupt,
6967 IRQF_SHARED, bp->dev->name, bp->dev);
6968 if (!rc)
6969 bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;
6970
6971 return rc;
6972
6973}
6974
6975/*
6976 * Init service functions
6977 */
6978
6979static void bnx2x_set_mac_addr(struct bnx2x *bp)
6980{
6981 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
6982
6983 /* CAM allocation
6984 * unicasts 0-31:port0 32-63:port1
6985 * multicast 64-127:port0 128-191:port1
6986 */
6987 config->hdr.length_6b = 2;
6988 config->hdr.offset = bp->port ? 31 : 0;
6989 config->hdr.reserved0 = 0;
6990 config->hdr.reserved1 = 0;
6991
6992 /* primary MAC */
6993 config->config_table[0].cam_entry.msb_mac_addr =
6994 swab16(*(u16 *)&bp->dev->dev_addr[0]);
6995 config->config_table[0].cam_entry.middle_mac_addr =
6996 swab16(*(u16 *)&bp->dev->dev_addr[2]);
6997 config->config_table[0].cam_entry.lsb_mac_addr =
6998 swab16(*(u16 *)&bp->dev->dev_addr[4]);
6999 config->config_table[0].cam_entry.flags = cpu_to_le16(bp->port);
7000 config->config_table[0].target_table_entry.flags = 0;
7001 config->config_table[0].target_table_entry.client_id = 0;
7002 config->config_table[0].target_table_entry.vlan_id = 0;
7003
7004 DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x)\n",
7005 config->config_table[0].cam_entry.msb_mac_addr,
7006 config->config_table[0].cam_entry.middle_mac_addr,
7007 config->config_table[0].cam_entry.lsb_mac_addr);
7008
7009 /* broadcast */
7010 config->config_table[1].cam_entry.msb_mac_addr = 0xffff;
7011 config->config_table[1].cam_entry.middle_mac_addr = 0xffff;
7012 config->config_table[1].cam_entry.lsb_mac_addr = 0xffff;
7013 config->config_table[1].cam_entry.flags = cpu_to_le16(bp->port);
7014 config->config_table[1].target_table_entry.flags =
7015 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
7016 config->config_table[1].target_table_entry.client_id = 0;
7017 config->config_table[1].target_table_entry.vlan_id = 0;
7018
7019 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
7020 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
7021 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
7022}
7023
7024static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
7025 int *state_p, int poll)
7026{
7027 /* can take a while if any port is running */
7028 int timeout = 500;
7029
7030 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
7031 poll ? "polling" : "waiting", state, idx);
7032
7033 might_sleep();
7034
7035 while (timeout) {
7036
7037 if (poll) {
7038 bnx2x_rx_int(bp->fp, 10);
7039 /* If index is different from 0
7040 * The reply for some commands will
7041 * be on the none default queue
7042 */
7043 if (idx)
7044 bnx2x_rx_int(&bp->fp[idx], 10);
7045 }
7046
7047 mb(); /* state is changed by bnx2x_sp_event()*/
7048
7049 if (*state_p == state)
7050 return 0;
7051
7052 timeout--;
7053 msleep(1);
7054
7055 }
7056
7057 /* timeout! */
7058 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
7059 poll ? "polling" : "waiting", state, idx);
7060
7061 return -EBUSY;
7062}
7063
7064static int bnx2x_setup_leading(struct bnx2x *bp)
7065{
7066
7067 /* reset IGU state */
7068 bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
7069
7070 /* SETUP ramrod */
7071 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
7072
7073 return bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0);
7074
7075}
7076
7077static int bnx2x_setup_multi(struct bnx2x *bp, int index)
7078{
7079
7080 /* reset IGU state */
7081 bnx2x_ack_sb(bp, index, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
7082
7083 /* SETUP ramrod */
7084 bp->fp[index].state = BNX2X_FP_STATE_OPENING;
7085 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0, index, 0);
7086
7087 /* Wait for completion */
7088 return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index,
7089 &(bp->fp[index].state), 0);
7090
7091}
7092
7093
7094static int bnx2x_poll(struct napi_struct *napi, int budget);
7095static void bnx2x_set_rx_mode(struct net_device *dev);
7096
7097static int bnx2x_nic_load(struct bnx2x *bp, int req_irq)
7098{
7099 u32 load_code;
7100 int i;
7101
7102 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
7103
7104 /* Send LOAD_REQUEST command to MCP.
7105 Returns the type of LOAD command: if it is the
7106 first port to be initialized common blocks should be
7107 initialized, otherwise - not.
7108 */
7109 if (!nomcp) {
7110 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
7111 if (!load_code) {
7112 BNX2X_ERR("MCP response failure, unloading\n");
7113 return -EBUSY;
7114 }
7115 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED) {
7116 BNX2X_ERR("MCP refused load request, unloading\n");
7117 return -EBUSY; /* other port in diagnostic mode */
7118 }
7119 } else {
7120 load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
7121 }
7122
7123 /* if we can't use msix we only need one fp,
7124 * so try to enable msix with the requested number of fp's
7125 * and fallback to inta with one fp
7126 */
7127 if (req_irq) {
7128 if (use_inta) {
7129 bp->num_queues = 1;
7130 } else {
7131 if ((use_multi > 1) && (use_multi <= 16))
7132 /* user requested number */
7133 bp->num_queues = use_multi;
7134 else if (use_multi == 1)
7135 bp->num_queues = num_online_cpus();
7136 else
7137 bp->num_queues = 1;
7138
7139 if (bnx2x_enable_msix(bp)) {
7140 /* failed to enable msix */
7141 bp->num_queues = 1;
7142 if (use_multi)
7143 BNX2X_ERR("Multi requested but failed"
7144 " to enable MSI-X\n");
7145 }
7146 }
7147 }
7148
7149 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", bp->num_queues);
7150
7151 if (bnx2x_alloc_mem(bp))
7152 return -ENOMEM;
7153
7154 if (req_irq) {
7155 if (bp->flags & USING_MSIX_FLAG) {
7156 if (bnx2x_req_msix_irqs(bp)) {
7157 pci_disable_msix(bp->pdev);
7158 goto load_error;
7159 }
7160
7161 } else {
7162 if (bnx2x_req_irq(bp)) {
7163 BNX2X_ERR("IRQ request failed, aborting\n");
7164 goto load_error;
7165 }
7166 }
7167 }
7168
7169 for_each_queue(bp, i)
7170 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
7171 bnx2x_poll, 128);
7172
7173
7174 /* Initialize HW */
7175 if (bnx2x_function_init(bp,
7176 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON))) {
7177 BNX2X_ERR("HW init failed, aborting\n");
7178 goto load_error;
7179 }
7180
7181
7182 atomic_set(&bp->intr_sem, 0);
7183
7184
7185 /* Setup NIC internals and enable interrupts */
7186 bnx2x_nic_init(bp);
7187
7188 /* Send LOAD_DONE command to MCP */
7189 if (!nomcp) {
7190 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
7191 if (!load_code) {
7192 BNX2X_ERR("MCP response failure, unloading\n");
7193 goto load_int_disable;
7194 }
7195 }
7196
7197 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
7198
7199 /* Enable Rx interrupt handling before sending the ramrod
7200 as it's completed on Rx FP queue */
7201 for_each_queue(bp, i)
7202 napi_enable(&bnx2x_fp(bp, i, napi));
7203
7204 if (bnx2x_setup_leading(bp))
7205 goto load_stop_netif;
7206
7207 for_each_nondefault_queue(bp, i)
7208 if (bnx2x_setup_multi(bp, i))
7209 goto load_stop_netif;
7210
7211 bnx2x_set_mac_addr(bp);
7212
7213 bnx2x_phy_init(bp);
7214
7215 /* Start fast path */
7216 if (req_irq) { /* IRQ is only requested from bnx2x_open */
7217 netif_start_queue(bp->dev);
7218 if (bp->flags & USING_MSIX_FLAG)
7219 printk(KERN_INFO PFX "%s: using MSI-X\n",
7220 bp->dev->name);
7221
7222 /* Otherwise Tx queue should be only reenabled */
7223 } else if (netif_running(bp->dev)) {
7224 netif_wake_queue(bp->dev);
7225 bnx2x_set_rx_mode(bp->dev);
7226 }
7227
7228 /* start the timer */
7229 mod_timer(&bp->timer, jiffies + bp->current_interval);
7230
7231 return 0;
7232
7233load_stop_netif:
7234 for_each_queue(bp, i)
7235 napi_disable(&bnx2x_fp(bp, i, napi));
7236
7237load_int_disable:
7238 bnx2x_int_disable_sync(bp);
7239
7240 bnx2x_free_skbs(bp);
7241 bnx2x_free_irq(bp);
7242
7243load_error:
7244 bnx2x_free_mem(bp);
7245
7246 /* TBD we really need to reset the chip
7247 if we want to recover from this */
7248 return -EBUSY;
7249}
7250
7251
7252static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
7253{
7254 int port = bp->port;
7255#ifdef USE_DMAE
7256 u32 wb_write[2];
7257#endif
7258 int base, i;
7259
7260 DP(NETIF_MSG_IFDOWN, "reset called with code %x\n", reset_code);
7261
7262 /* Do not rcv packets to BRB */
7263 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7264 /* Do not direct rcv packets that are not for MCP to the BRB */
7265 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7266 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7267
7268 /* Configure IGU and AEU */
7269 REG_WR(bp, HC_REG_CONFIG_0 + port*4, 0x1000);
7270 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7271
7272 /* TODO: Close Doorbell port? */
7273
7274 /* Clear ILT */
7275#ifdef USE_DMAE
7276 wb_write[0] = 0;
7277 wb_write[1] = 0;
7278#endif
7279 base = port * RQ_ONCHIP_AT_PORT_SIZE;
7280 for (i = base; i < base + RQ_ONCHIP_AT_PORT_SIZE; i++) {
7281#ifdef USE_DMAE
7282 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
7283#else
7284 REG_WR_IND(bp, PXP2_REG_RQ_ONCHIP_AT, 0);
7285 REG_WR_IND(bp, PXP2_REG_RQ_ONCHIP_AT + 4, 0);
7286#endif
7287 }
7288
7289 if (reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7290 /* reset_common */
7291 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7292 0xd3ffff7f);
7293 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7294 0x1403);
7295 }
7296}
7297
7298static int bnx2x_stop_multi(struct bnx2x *bp, int index)
7299{
7300
7301 int rc;
7302
7303 /* halt the connection */
7304 bp->fp[index].state = BNX2X_FP_STATE_HALTING;
7305 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, 0, 0);
7306
7307
7308 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index,
7309 &(bp->fp[index].state), 1);
7310 if (rc) /* timeout */
7311 return rc;
7312
7313 /* delete cfc entry */
7314 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1);
7315
7316 return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, index,
7317 &(bp->fp[index].state), 1);
7318
7319}
7320
7321
7322static void bnx2x_stop_leading(struct bnx2x *bp)
7323{
7324 u16 dsb_sp_prod_idx;
7325 /* if the other port is handling traffic,
7326 this can take a lot of time */
7327 int timeout = 500;
7328
7329 might_sleep();
7330
7331 /* Send HALT ramrod */
7332 bp->fp[0].state = BNX2X_FP_STATE_HALTING;
7333 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, 0, 0);
7334
7335 if (bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
7336 &(bp->fp[0].state), 1))
7337 return;
7338
7339 dsb_sp_prod_idx = *bp->dsb_sp_prod;
7340
7341 /* Send PORT_DELETE ramrod */
7342 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
7343
7344 /* Wait for completion to arrive on default status block
7345 we are going to reset the chip anyway
7346 so there is not much to do if this times out
7347 */
7348 while ((dsb_sp_prod_idx == *bp->dsb_sp_prod) && timeout) {
7349 timeout--;
7350 msleep(1);
7351 }
7352 if (!timeout) {
7353 DP(NETIF_MSG_IFDOWN, "timeout polling for completion "
7354 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
7355 *bp->dsb_sp_prod, dsb_sp_prod_idx);
7356 }
7357 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
7358 bp->fp[0].state = BNX2X_FP_STATE_CLOSED;
7359}
7360
7361
7362static int bnx2x_nic_unload(struct bnx2x *bp, int free_irq)
7363{
7364 u32 reset_code = 0;
7365 int i, timeout;
7366
7367 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
7368
7369 del_timer_sync(&bp->timer);
7370
7371 bp->rx_mode = BNX2X_RX_MODE_NONE;
7372 bnx2x_set_storm_rx_mode(bp);
7373
7374 if (netif_running(bp->dev)) {
7375 netif_tx_disable(bp->dev);
7376 bp->dev->trans_start = jiffies; /* prevent tx timeout */
7377 }
7378
7379 /* Wait until all fast path tasks complete */
7380 for_each_queue(bp, i) {
7381 struct bnx2x_fastpath *fp = &bp->fp[i];
7382
7383 timeout = 1000;
7384 while (bnx2x_has_work(fp) && (timeout--))
7385 msleep(1);
7386 if (!timeout)
7387 BNX2X_ERR("timeout waiting for queue[%d]\n", i);
7388 }
7389
7390 /* Wait until stat ramrod returns and all SP tasks complete */
7391 timeout = 1000;
7392 while ((bp->stat_pending || (bp->spq_left != MAX_SPQ_PENDING)) &&
7393 (timeout--))
7394 msleep(1);
7395
7396 for_each_queue(bp, i)
7397 napi_disable(&bnx2x_fp(bp, i, napi));
7398 /* Disable interrupts after Tx and Rx are disabled on stack level */
7399 bnx2x_int_disable_sync(bp);
7400
7401 if (bp->flags & NO_WOL_FLAG)
7402 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7403
7404 else if (bp->wol) {
7405 u32 emac_base = bp->port ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
7406 u8 *mac_addr = bp->dev->dev_addr;
7407 u32 val = (EMAC_MODE_MPKT | EMAC_MODE_MPKT_RCVD |
7408 EMAC_MODE_ACPI_RCVD);
7409
7410 EMAC_WR(EMAC_REG_EMAC_MODE, val);
7411
7412 val = (mac_addr[0] << 8) | mac_addr[1];
7413 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
7414
7415 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7416 (mac_addr[4] << 8) | mac_addr[5];
7417 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
7418
7419 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7420
7421 } else
7422 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7423
7424 /* Close multi and leading connections */
7425 for_each_nondefault_queue(bp, i)
7426 if (bnx2x_stop_multi(bp, i))
7427 goto unload_error;
7428
7429 bnx2x_stop_leading(bp);
7430 if ((bp->state != BNX2X_STATE_CLOSING_WAIT4_UNLOAD) ||
7431 (bp->fp[0].state != BNX2X_FP_STATE_CLOSED)) {
7432 DP(NETIF_MSG_IFDOWN, "failed to close leading properly!"
7433 "state 0x%x fp[0].state 0x%x",
7434 bp->state, bp->fp[0].state);
7435 }
7436
7437unload_error:
7438 bnx2x_link_reset(bp);
7439
7440 if (!nomcp)
7441 reset_code = bnx2x_fw_command(bp, reset_code);
7442 else
7443 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7444
7445 /* Release IRQs */
7446 if (free_irq)
7447 bnx2x_free_irq(bp);
7448
7449 /* Reset the chip */
7450 bnx2x_reset_chip(bp, reset_code);
7451
7452 /* Report UNLOAD_DONE to MCP */
7453 if (!nomcp)
7454 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
7455
7456 /* Free SKBs and driver internals */
7457 bnx2x_free_skbs(bp);
7458 bnx2x_free_mem(bp);
7459
7460 bp->state = BNX2X_STATE_CLOSED;
7461
7462 netif_carrier_off(bp->dev);
7463
7464 return 0;
7465}
7466
7467/* end of nic load/unload */
7468
7469/* ethtool_ops */
7470
7471/*
7472 * Init service functions
7473 */
7474
7475static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7476{
7477 int port = bp->port;
7478 u32 ext_phy_type;
7479
7480 bp->phy_flags = 0;
7481
7482 switch (switch_cfg) {
7483 case SWITCH_CFG_1G:
7484 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
7485
7486 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
7487 switch (ext_phy_type) {
7488 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
7489 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
7490 ext_phy_type);
7491
7492 bp->supported |= (SUPPORTED_10baseT_Half |
7493 SUPPORTED_10baseT_Full |
7494 SUPPORTED_100baseT_Half |
7495 SUPPORTED_100baseT_Full |
7496 SUPPORTED_1000baseT_Full |
7497 SUPPORTED_2500baseX_Full |
7498 SUPPORTED_TP | SUPPORTED_FIBRE |
7499 SUPPORTED_Autoneg |
7500 SUPPORTED_Pause |
7501 SUPPORTED_Asym_Pause);
7502 break;
7503
7504 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
7505 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
7506 ext_phy_type);
7507
7508 bp->phy_flags |= PHY_SGMII_FLAG;
7509
7510 bp->supported |= (SUPPORTED_10baseT_Half |
7511 SUPPORTED_10baseT_Full |
7512 SUPPORTED_100baseT_Half |
7513 SUPPORTED_100baseT_Full |
7514 SUPPORTED_1000baseT_Full |
7515 SUPPORTED_TP | SUPPORTED_FIBRE |
7516 SUPPORTED_Autoneg |
7517 SUPPORTED_Pause |
7518 SUPPORTED_Asym_Pause);
7519 break;
7520
7521 default:
7522 BNX2X_ERR("NVRAM config error. "
7523 "BAD SerDes ext_phy_config 0x%x\n",
7524 bp->ext_phy_config);
7525 return;
7526 }
7527
7528 bp->phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
7529 port*0x10);
7530 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->phy_addr);
7531 break;
7532
7533 case SWITCH_CFG_10G:
7534 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
7535
7536 bp->phy_flags |= PHY_XGXS_FLAG;
7537
7538 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
7539 switch (ext_phy_type) {
7540 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7541 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
7542 ext_phy_type);
7543
7544 bp->supported |= (SUPPORTED_10baseT_Half |
7545 SUPPORTED_10baseT_Full |
7546 SUPPORTED_100baseT_Half |
7547 SUPPORTED_100baseT_Full |
7548 SUPPORTED_1000baseT_Full |
7549 SUPPORTED_2500baseX_Full |
7550 SUPPORTED_10000baseT_Full |
7551 SUPPORTED_TP | SUPPORTED_FIBRE |
7552 SUPPORTED_Autoneg |
7553 SUPPORTED_Pause |
7554 SUPPORTED_Asym_Pause);
7555 break;
7556
7557 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7558 BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
7559 ext_phy_type);
7560
7561 bp->supported |= (SUPPORTED_10000baseT_Full |
7562 SUPPORTED_FIBRE |
7563 SUPPORTED_Pause |
7564 SUPPORTED_Asym_Pause);
7565 break;
7566
7567 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7568 BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
7569 ext_phy_type);
7570
7571 bp->supported |= (SUPPORTED_10000baseT_Full |
7572 SUPPORTED_1000baseT_Full |
7573 SUPPORTED_Autoneg |
7574 SUPPORTED_FIBRE |
7575 SUPPORTED_Pause |
7576 SUPPORTED_Asym_Pause);
7577 break;
7578
7579 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
7580 BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
7581 ext_phy_type);
7582
7583 bp->supported |= (SUPPORTED_10000baseT_Full |
7584 SUPPORTED_1000baseT_Full |
7585 SUPPORTED_FIBRE |
7586 SUPPORTED_Autoneg |
7587 SUPPORTED_Pause |
7588 SUPPORTED_Asym_Pause);
7589 break;
7590
7591 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7592 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
7593 ext_phy_type);
7594
7595 bp->supported |= (SUPPORTED_10000baseT_Full |
7596 SUPPORTED_TP |
7597 SUPPORTED_Autoneg |
7598 SUPPORTED_Pause |
7599 SUPPORTED_Asym_Pause);
7600 break;
7601
7602 default:
7603 BNX2X_ERR("NVRAM config error. "
7604 "BAD XGXS ext_phy_config 0x%x\n",
7605 bp->ext_phy_config);
7606 return;
7607 }
7608
7609 bp->phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
7610 port*0x18);
7611 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->phy_addr);
7612
7613 bp->ser_lane = ((bp->lane_config &
7614 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
7615 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
7616 bp->rx_lane_swap = ((bp->lane_config &
7617 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
7618 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
7619 bp->tx_lane_swap = ((bp->lane_config &
7620 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
7621 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
7622 BNX2X_DEV_INFO("rx_lane_swap 0x%x tx_lane_swap 0x%x\n",
7623 bp->rx_lane_swap, bp->tx_lane_swap);
7624 break;
7625
7626 default:
7627 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
7628 bp->link_config);
7629 return;
7630 }
7631
7632 /* mask what we support according to speed_cap_mask */
7633 if (!(bp->speed_cap_mask &
7634 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
7635 bp->supported &= ~SUPPORTED_10baseT_Half;
7636
7637 if (!(bp->speed_cap_mask &
7638 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
7639 bp->supported &= ~SUPPORTED_10baseT_Full;
7640
7641 if (!(bp->speed_cap_mask &
7642 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
7643 bp->supported &= ~SUPPORTED_100baseT_Half;
7644
7645 if (!(bp->speed_cap_mask &
7646 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
7647 bp->supported &= ~SUPPORTED_100baseT_Full;
7648
7649 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
7650 bp->supported &= ~(SUPPORTED_1000baseT_Half |
7651 SUPPORTED_1000baseT_Full);
7652
7653 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7654 bp->supported &= ~SUPPORTED_2500baseX_Full;
7655
7656 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
7657 bp->supported &= ~SUPPORTED_10000baseT_Full;
7658
7659 BNX2X_DEV_INFO("supported 0x%x\n", bp->supported);
7660}
7661
7662static void bnx2x_link_settings_requested(struct bnx2x *bp)
7663{
7664 bp->req_autoneg = 0;
7665 bp->req_duplex = DUPLEX_FULL;
7666
7667 switch (bp->link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7668 case PORT_FEATURE_LINK_SPEED_AUTO:
7669 if (bp->supported & SUPPORTED_Autoneg) {
7670 bp->req_autoneg |= AUTONEG_SPEED;
7671 bp->req_line_speed = 0;
7672 bp->advertising = bp->supported;
7673 } else {
7674 if (XGXS_EXT_PHY_TYPE(bp) ==
7675 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) {
7676 /* force 10G, no AN */
7677 bp->req_line_speed = SPEED_10000;
7678 bp->advertising =
7679 (ADVERTISED_10000baseT_Full |
7680 ADVERTISED_FIBRE);
7681 break;
7682 }
7683 BNX2X_ERR("NVRAM config error. "
7684 "Invalid link_config 0x%x"
7685 " Autoneg not supported\n",
7686 bp->link_config);
7687 return;
7688 }
7689 break;
7690
7691 case PORT_FEATURE_LINK_SPEED_10M_FULL:
7692 if (bp->supported & SUPPORTED_10baseT_Full) {
7693 bp->req_line_speed = SPEED_10;
7694 bp->advertising = (ADVERTISED_10baseT_Full |
7695 ADVERTISED_TP);
7696 } else {
7697 BNX2X_ERR("NVRAM config error. "
7698 "Invalid link_config 0x%x"
7699 " speed_cap_mask 0x%x\n",
7700 bp->link_config, bp->speed_cap_mask);
7701 return;
7702 }
7703 break;
7704
7705 case PORT_FEATURE_LINK_SPEED_10M_HALF:
7706 if (bp->supported & SUPPORTED_10baseT_Half) {
7707 bp->req_line_speed = SPEED_10;
7708 bp->req_duplex = DUPLEX_HALF;
7709 bp->advertising = (ADVERTISED_10baseT_Half |
7710 ADVERTISED_TP);
7711 } else {
7712 BNX2X_ERR("NVRAM config error. "
7713 "Invalid link_config 0x%x"
7714 " speed_cap_mask 0x%x\n",
7715 bp->link_config, bp->speed_cap_mask);
7716 return;
7717 }
7718 break;
7719
7720 case PORT_FEATURE_LINK_SPEED_100M_FULL:
7721 if (bp->supported & SUPPORTED_100baseT_Full) {
7722 bp->req_line_speed = SPEED_100;
7723 bp->advertising = (ADVERTISED_100baseT_Full |
7724 ADVERTISED_TP);
7725 } else {
7726 BNX2X_ERR("NVRAM config error. "
7727 "Invalid link_config 0x%x"
7728 " speed_cap_mask 0x%x\n",
7729 bp->link_config, bp->speed_cap_mask);
7730 return;
7731 }
7732 break;
7733
7734 case PORT_FEATURE_LINK_SPEED_100M_HALF:
7735 if (bp->supported & SUPPORTED_100baseT_Half) {
7736 bp->req_line_speed = SPEED_100;
7737 bp->req_duplex = DUPLEX_HALF;
7738 bp->advertising = (ADVERTISED_100baseT_Half |
7739 ADVERTISED_TP);
7740 } else {
7741 BNX2X_ERR("NVRAM config error. "
7742 "Invalid link_config 0x%x"
7743 " speed_cap_mask 0x%x\n",
7744 bp->link_config, bp->speed_cap_mask);
7745 return;
7746 }
7747 break;
7748
7749 case PORT_FEATURE_LINK_SPEED_1G:
7750 if (bp->supported & SUPPORTED_1000baseT_Full) {
7751 bp->req_line_speed = SPEED_1000;
7752 bp->advertising = (ADVERTISED_1000baseT_Full |
7753 ADVERTISED_TP);
7754 } else {
7755 BNX2X_ERR("NVRAM config error. "
7756 "Invalid link_config 0x%x"
7757 " speed_cap_mask 0x%x\n",
7758 bp->link_config, bp->speed_cap_mask);
7759 return;
7760 }
7761 break;
7762
7763 case PORT_FEATURE_LINK_SPEED_2_5G:
7764 if (bp->supported & SUPPORTED_2500baseX_Full) {
7765 bp->req_line_speed = SPEED_2500;
7766 bp->advertising = (ADVERTISED_2500baseX_Full |
7767 ADVERTISED_TP);
7768 } else {
7769 BNX2X_ERR("NVRAM config error. "
7770 "Invalid link_config 0x%x"
7771 " speed_cap_mask 0x%x\n",
7772 bp->link_config, bp->speed_cap_mask);
7773 return;
7774 }
7775 break;
7776
7777 case PORT_FEATURE_LINK_SPEED_10G_CX4:
7778 case PORT_FEATURE_LINK_SPEED_10G_KX4:
7779 case PORT_FEATURE_LINK_SPEED_10G_KR:
7780 if (bp->supported & SUPPORTED_10000baseT_Full) {
7781 bp->req_line_speed = SPEED_10000;
7782 bp->advertising = (ADVERTISED_10000baseT_Full |
7783 ADVERTISED_FIBRE);
7784 } else {
7785 BNX2X_ERR("NVRAM config error. "
7786 "Invalid link_config 0x%x"
7787 " speed_cap_mask 0x%x\n",
7788 bp->link_config, bp->speed_cap_mask);
7789 return;
7790 }
7791 break;
7792
7793 default:
7794 BNX2X_ERR("NVRAM config error. "
7795 "BAD link speed link_config 0x%x\n",
7796 bp->link_config);
7797 bp->req_autoneg |= AUTONEG_SPEED;
7798 bp->req_line_speed = 0;
7799 bp->advertising = bp->supported;
7800 break;
7801 }
7802 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d\n",
7803 bp->req_line_speed, bp->req_duplex);
7804
7805 bp->req_flow_ctrl = (bp->link_config &
7806 PORT_FEATURE_FLOW_CONTROL_MASK);
7807 if ((bp->req_flow_ctrl == FLOW_CTRL_AUTO) &&
7808 (bp->supported & SUPPORTED_Autoneg))
7809 bp->req_autoneg |= AUTONEG_FLOW_CTRL;
7810
7811 BNX2X_DEV_INFO("req_autoneg 0x%x req_flow_ctrl 0x%x"
7812 " advertising 0x%x\n",
7813 bp->req_autoneg, bp->req_flow_ctrl, bp->advertising);
7814}
7815
7816static void bnx2x_get_hwinfo(struct bnx2x *bp)
7817{
7818 u32 val, val2, val3, val4, id;
7819 int port = bp->port;
7820 u32 switch_cfg;
7821
7822 bp->shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7823 BNX2X_DEV_INFO("shmem offset is %x\n", bp->shmem_base);
7824
7825 /* Get the chip revision id and number. */
7826 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7827 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7828 id = ((val & 0xffff) << 16);
7829 val = REG_RD(bp, MISC_REG_CHIP_REV);
7830 id |= ((val & 0xf) << 12);
7831 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7832 id |= ((val & 0xff) << 4);
7833 REG_RD(bp, MISC_REG_BOND_ID);
7834 id |= (val & 0xf);
7835 bp->chip_id = id;
7836 BNX2X_DEV_INFO("chip ID is %x\n", id);
7837
7838 if (!bp->shmem_base || (bp->shmem_base != 0xAF900)) {
7839 BNX2X_DEV_INFO("MCP not active\n");
7840 nomcp = 1;
7841 goto set_mac;
7842 }
7843
7844 val = SHMEM_RD(bp, validity_map[port]);
7845 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7846 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7847 BNX2X_ERR("BAD MCP validity signature\n");
7848
7849 bp->fw_seq = (SHMEM_RD(bp, func_mb[port].drv_mb_header) &
7850 DRV_MSG_SEQ_NUMBER_MASK);
7851
7852 bp->hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
7853 bp->board = SHMEM_RD(bp, dev_info.shared_hw_config.board);
7854 bp->serdes_config =
7855 SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config);
7856 bp->lane_config =
7857 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
7858 bp->ext_phy_config =
7859 SHMEM_RD(bp,
7860 dev_info.port_hw_config[port].external_phy_config);
7861 bp->speed_cap_mask =
7862 SHMEM_RD(bp,
7863 dev_info.port_hw_config[port].speed_capability_mask);
7864
7865 bp->link_config =
7866 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
7867
7868 BNX2X_DEV_INFO("hw_config (%08x) board (%08x) serdes_config (%08x)\n"
7869 KERN_INFO " lane_config (%08x) ext_phy_config (%08x)\n"
7870 KERN_INFO " speed_cap_mask (%08x) link_config (%08x)"
7871 " fw_seq (%08x)\n",
7872 bp->hw_config, bp->board, bp->serdes_config,
7873 bp->lane_config, bp->ext_phy_config,
7874 bp->speed_cap_mask, bp->link_config, bp->fw_seq);
7875
7876 switch_cfg = (bp->link_config & PORT_FEATURE_CONNECTED_SWITCH_MASK);
7877 bnx2x_link_settings_supported(bp, switch_cfg);
7878
7879 bp->autoneg = (bp->hw_config & SHARED_HW_CFG_AN_ENABLE_MASK);
7880 /* for now disable cl73 */
7881 bp->autoneg &= ~SHARED_HW_CFG_AN_ENABLE_CL73;
7882 BNX2X_DEV_INFO("autoneg 0x%x\n", bp->autoneg);
7883
7884 bnx2x_link_settings_requested(bp);
7885
7886 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
7887 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
7888 bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
7889 bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
7890 bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
7891 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
7892 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
7893 bp->dev->dev_addr[5] = (u8)(val & 0xff);
7894
7895 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, 6);
7896
7897
7898 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7899 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7900 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7901 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7902
7903 printk(KERN_INFO PFX "part number %X-%X-%X-%X\n",
7904 val, val2, val3, val4);
7905
7906 /* bc ver */
7907 if (!nomcp) {
7908 bp->bc_ver = val = ((SHMEM_RD(bp, dev_info.bc_rev)) >> 8);
7909 BNX2X_DEV_INFO("bc_ver %X\n", val);
7910 if (val < BNX2X_BC_VER) {
7911 /* for now only warn
7912 * later we might need to enforce this */
7913 BNX2X_ERR("This driver needs bc_ver %X but found %X,"
7914 " please upgrade BC\n", BNX2X_BC_VER, val);
7915 }
7916 } else {
7917 bp->bc_ver = 0;
7918 }
7919
7920 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7921 bp->flash_size = (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
7922 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7923 bp->flash_size, bp->flash_size);
7924
7925 return;
7926
7927set_mac: /* only supposed to happen on emulation/FPGA */
7928 BNX2X_ERR("warning rendom MAC workaround active\n");
7929 random_ether_addr(bp->dev->dev_addr);
7930 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, 6);
7931
7932}
7933
7934/*
7935 * ethtool service functions
7936 */
7937
7938/* All ethtool functions called with rtnl_lock */
7939
7940static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7941{
7942 struct bnx2x *bp = netdev_priv(dev);
7943
7944 cmd->supported = bp->supported;
7945 cmd->advertising = bp->advertising;
7946
7947 if (netif_carrier_ok(dev)) {
7948 cmd->speed = bp->line_speed;
7949 cmd->duplex = bp->duplex;
7950 } else {
7951 cmd->speed = bp->req_line_speed;
7952 cmd->duplex = bp->req_duplex;
7953 }
7954
7955 if (bp->phy_flags & PHY_XGXS_FLAG) {
7956 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
7957
7958 switch (ext_phy_type) {
7959 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7960 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7961 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7962 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
7963 cmd->port = PORT_FIBRE;
7964 break;
7965
7966 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7967 cmd->port = PORT_TP;
7968 break;
7969
7970 default:
7971 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
7972 bp->ext_phy_config);
7973 }
7974 } else
7975 cmd->port = PORT_TP;
7976
7977 cmd->phy_address = bp->phy_addr;
7978 cmd->transceiver = XCVR_INTERNAL;
7979
7980 if (bp->req_autoneg & AUTONEG_SPEED)
7981 cmd->autoneg = AUTONEG_ENABLE;
7982 else
7983 cmd->autoneg = AUTONEG_DISABLE;
7984
7985 cmd->maxtxpkt = 0;
7986 cmd->maxrxpkt = 0;
7987
7988 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
7989 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
7990 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
7991 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
7992 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
7993 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
7994 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
7995
7996 return 0;
7997}
7998
7999static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8000{
8001 struct bnx2x *bp = netdev_priv(dev);
8002 u32 advertising;
8003
8004 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
8005 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
8006 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
8007 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
8008 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
8009 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
8010 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
8011
8012 if (cmd->autoneg == AUTONEG_ENABLE) {
8013 if (!(bp->supported & SUPPORTED_Autoneg)) {
8014 DP(NETIF_MSG_LINK, "Aotoneg not supported\n");
8015 return -EINVAL;
8016 }
8017
8018 /* advertise the requested speed and duplex if supported */
8019 cmd->advertising &= bp->supported;
8020
8021 bp->req_autoneg |= AUTONEG_SPEED;
8022 bp->req_line_speed = 0;
8023 bp->req_duplex = DUPLEX_FULL;
8024 bp->advertising |= (ADVERTISED_Autoneg | cmd->advertising);
8025
8026 } else { /* forced speed */
8027 /* advertise the requested speed and duplex if supported */
8028 switch (cmd->speed) {
8029 case SPEED_10:
8030 if (cmd->duplex == DUPLEX_FULL) {
8031 if (!(bp->supported &
8032 SUPPORTED_10baseT_Full)) {
8033 DP(NETIF_MSG_LINK,
8034 "10M full not supported\n");
8035 return -EINVAL;
8036 }
8037
8038 advertising = (ADVERTISED_10baseT_Full |
8039 ADVERTISED_TP);
8040 } else {
8041 if (!(bp->supported &
8042 SUPPORTED_10baseT_Half)) {
8043 DP(NETIF_MSG_LINK,
8044 "10M half not supported\n");
8045 return -EINVAL;
8046 }
8047
8048 advertising = (ADVERTISED_10baseT_Half |
8049 ADVERTISED_TP);
8050 }
8051 break;
8052
8053 case SPEED_100:
8054 if (cmd->duplex == DUPLEX_FULL) {
8055 if (!(bp->supported &
8056 SUPPORTED_100baseT_Full)) {
8057 DP(NETIF_MSG_LINK,
8058 "100M full not supported\n");
8059 return -EINVAL;
8060 }
8061
8062 advertising = (ADVERTISED_100baseT_Full |
8063 ADVERTISED_TP);
8064 } else {
8065 if (!(bp->supported &
8066 SUPPORTED_100baseT_Half)) {
8067 DP(NETIF_MSG_LINK,
8068 "100M half not supported\n");
8069 return -EINVAL;
8070 }
8071
8072 advertising = (ADVERTISED_100baseT_Half |
8073 ADVERTISED_TP);
8074 }
8075 break;
8076
8077 case SPEED_1000:
8078 if (cmd->duplex != DUPLEX_FULL) {
8079 DP(NETIF_MSG_LINK, "1G half not supported\n");
8080 return -EINVAL;
8081 }
8082
8083 if (!(bp->supported & SUPPORTED_1000baseT_Full)) {
8084 DP(NETIF_MSG_LINK, "1G full not supported\n");
8085 return -EINVAL;
8086 }
8087
8088 advertising = (ADVERTISED_1000baseT_Full |
8089 ADVERTISED_TP);
8090 break;
8091
8092 case SPEED_2500:
8093 if (cmd->duplex != DUPLEX_FULL) {
8094 DP(NETIF_MSG_LINK,
8095 "2.5G half not supported\n");
8096 return -EINVAL;
8097 }
8098
8099 if (!(bp->supported & SUPPORTED_2500baseX_Full)) {
8100 DP(NETIF_MSG_LINK,
8101 "2.5G full not supported\n");
8102 return -EINVAL;
8103 }
8104
8105 advertising = (ADVERTISED_2500baseX_Full |
8106 ADVERTISED_TP);
8107 break;
8108
8109 case SPEED_10000:
8110 if (cmd->duplex != DUPLEX_FULL) {
8111 DP(NETIF_MSG_LINK, "10G half not supported\n");
8112 return -EINVAL;
8113 }
8114
8115 if (!(bp->supported & SUPPORTED_10000baseT_Full)) {
8116 DP(NETIF_MSG_LINK, "10G full not supported\n");
8117 return -EINVAL;
8118 }
8119
8120 advertising = (ADVERTISED_10000baseT_Full |
8121 ADVERTISED_FIBRE);
8122 break;
8123
8124 default:
8125 DP(NETIF_MSG_LINK, "Unsupported speed\n");
8126 return -EINVAL;
8127 }
8128
8129 bp->req_autoneg &= ~AUTONEG_SPEED;
8130 bp->req_line_speed = cmd->speed;
8131 bp->req_duplex = cmd->duplex;
8132 bp->advertising = advertising;
8133 }
8134
8135 DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_line_speed %d\n"
8136 DP_LEVEL " req_duplex %d advertising 0x%x\n",
8137 bp->req_autoneg, bp->req_line_speed, bp->req_duplex,
8138 bp->advertising);
8139
8140 bnx2x_stop_stats(bp);
8141 bnx2x_link_initialize(bp);
8142
8143 return 0;
8144}
8145
8146static void bnx2x_get_drvinfo(struct net_device *dev,
8147 struct ethtool_drvinfo *info)
8148{
8149 struct bnx2x *bp = netdev_priv(dev);
8150
8151 strcpy(info->driver, DRV_MODULE_NAME);
8152 strcpy(info->version, DRV_MODULE_VERSION);
8153 snprintf(info->fw_version, 32, "%d.%d.%d:%d (BC VER %x)",
8154 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION,
8155 BCM_5710_FW_REVISION_VERSION, BCM_5710_FW_COMPILE_FLAGS,
8156 bp->bc_ver);
8157 strcpy(info->bus_info, pci_name(bp->pdev));
8158 info->n_stats = BNX2X_NUM_STATS;
8159 info->testinfo_len = BNX2X_NUM_TESTS;
8160 info->eedump_len = bp->flash_size;
8161 info->regdump_len = 0;
8162}
8163
8164static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8165{
8166 struct bnx2x *bp = netdev_priv(dev);
8167
8168 if (bp->flags & NO_WOL_FLAG) {
8169 wol->supported = 0;
8170 wol->wolopts = 0;
8171 } else {
8172 wol->supported = WAKE_MAGIC;
8173 if (bp->wol)
8174 wol->wolopts = WAKE_MAGIC;
8175 else
8176 wol->wolopts = 0;
8177 }
8178 memset(&wol->sopass, 0, sizeof(wol->sopass));
8179}
8180
8181static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8182{
8183 struct bnx2x *bp = netdev_priv(dev);
8184
8185 if (wol->wolopts & ~WAKE_MAGIC)
8186 return -EINVAL;
8187
8188 if (wol->wolopts & WAKE_MAGIC) {
8189 if (bp->flags & NO_WOL_FLAG)
8190 return -EINVAL;
8191
8192 bp->wol = 1;
8193 } else {
8194 bp->wol = 0;
8195 }
8196 return 0;
8197}
8198
8199static u32 bnx2x_get_msglevel(struct net_device *dev)
8200{
8201 struct bnx2x *bp = netdev_priv(dev);
8202
8203 return bp->msglevel;
8204}
8205
8206static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
8207{
8208 struct bnx2x *bp = netdev_priv(dev);
8209
8210 if (capable(CAP_NET_ADMIN))
8211 bp->msglevel = level;
8212}
8213
8214static int bnx2x_nway_reset(struct net_device *dev)
8215{
8216 struct bnx2x *bp = netdev_priv(dev);
8217
8218 if (bp->state != BNX2X_STATE_OPEN) {
8219 DP(NETIF_MSG_PROBE, "state is %x, returning\n", bp->state);
8220 return -EAGAIN;
8221 }
8222
8223 bnx2x_stop_stats(bp);
8224 bnx2x_link_initialize(bp);
8225
8226 return 0;
8227}
8228
8229static int bnx2x_get_eeprom_len(struct net_device *dev)
8230{
8231 struct bnx2x *bp = netdev_priv(dev);
8232
8233 return bp->flash_size;
8234}
8235
8236static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
8237{
8238 int port = bp->port;
8239 int count, i;
8240 u32 val = 0;
8241
8242 /* adjust timeout for emulation/FPGA */
8243 count = NVRAM_TIMEOUT_COUNT;
8244 if (CHIP_REV_IS_SLOW(bp))
8245 count *= 100;
8246
8247 /* request access to nvram interface */
8248 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
8249 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
8250
8251 for (i = 0; i < count*10; i++) {
8252 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
8253 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
8254 break;
8255
8256 udelay(5);
8257 }
8258
8259 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
8260 DP(NETIF_MSG_NVM, "cannot get access to nvram interface\n");
8261 return -EBUSY;
8262 }
8263
8264 return 0;
8265}
8266
8267static int bnx2x_release_nvram_lock(struct bnx2x *bp)
8268{
8269 int port = bp->port;
8270 int count, i;
8271 u32 val = 0;
8272
8273 /* adjust timeout for emulation/FPGA */
8274 count = NVRAM_TIMEOUT_COUNT;
8275 if (CHIP_REV_IS_SLOW(bp))
8276 count *= 100;
8277
8278 /* relinquish nvram interface */
8279 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
8280 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
8281
8282 for (i = 0; i < count*10; i++) {
8283 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
8284 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
8285 break;
8286
8287 udelay(5);
8288 }
8289
8290 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
8291 DP(NETIF_MSG_NVM, "cannot free access to nvram interface\n");
8292 return -EBUSY;
8293 }
8294
8295 return 0;
8296}
8297
8298static void bnx2x_enable_nvram_access(struct bnx2x *bp)
8299{
8300 u32 val;
8301
8302 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
8303
8304 /* enable both bits, even on read */
8305 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
8306 (val | MCPR_NVM_ACCESS_ENABLE_EN |
8307 MCPR_NVM_ACCESS_ENABLE_WR_EN));
8308}
8309
8310static void bnx2x_disable_nvram_access(struct bnx2x *bp)
8311{
8312 u32 val;
8313
8314 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
8315
8316 /* disable both bits, even after read */
8317 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
8318 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
8319 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
8320}
8321
8322static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, u32 *ret_val,
8323 u32 cmd_flags)
8324{
8325 int count, i, rc;
8326 u32 val;
8327
8328 /* build the command word */
8329 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
8330
8331 /* need to clear DONE bit separately */
8332 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
8333
8334 /* address of the NVRAM to read from */
8335 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
8336 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
8337
8338 /* issue a read command */
8339 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
8340
8341 /* adjust timeout for emulation/FPGA */
8342 count = NVRAM_TIMEOUT_COUNT;
8343 if (CHIP_REV_IS_SLOW(bp))
8344 count *= 100;
8345
8346 /* wait for completion */
8347 *ret_val = 0;
8348 rc = -EBUSY;
8349 for (i = 0; i < count; i++) {
8350 udelay(5);
8351 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
8352
8353 if (val & MCPR_NVM_COMMAND_DONE) {
8354 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
8355 DP(NETIF_MSG_NVM, "val 0x%08x\n", val);
8356 /* we read nvram data in cpu order
8357 * but ethtool sees it as an array of bytes
8358 * converting to big-endian will do the work */
8359 val = cpu_to_be32(val);
8360 *ret_val = val;
8361 rc = 0;
8362 break;
8363 }
8364 }
8365
8366 return rc;
8367}
8368
8369static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
8370 int buf_size)
8371{
8372 int rc;
8373 u32 cmd_flags;
8374 u32 val;
8375
8376 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
8377 DP(NETIF_MSG_NVM,
8378 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
8379 offset, buf_size);
8380 return -EINVAL;
8381 }
8382
8383 if (offset + buf_size > bp->flash_size) {
8384 DP(NETIF_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8385 " buf_size (0x%x) > flash_size (0x%x)\n",
8386 offset, buf_size, bp->flash_size);
8387 return -EINVAL;
8388 }
8389
8390 /* request access to nvram interface */
8391 rc = bnx2x_acquire_nvram_lock(bp);
8392 if (rc)
8393 return rc;
8394
8395 /* enable access to nvram interface */
8396 bnx2x_enable_nvram_access(bp);
8397
8398 /* read the first word(s) */
8399 cmd_flags = MCPR_NVM_COMMAND_FIRST;
8400 while ((buf_size > sizeof(u32)) && (rc == 0)) {
8401 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
8402 memcpy(ret_buf, &val, 4);
8403
8404 /* advance to the next dword */
8405 offset += sizeof(u32);
8406 ret_buf += sizeof(u32);
8407 buf_size -= sizeof(u32);
8408 cmd_flags = 0;
8409 }
8410
8411 if (rc == 0) {
8412 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8413 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
8414 memcpy(ret_buf, &val, 4);
8415 }
8416
8417 /* disable access to nvram interface */
8418 bnx2x_disable_nvram_access(bp);
8419 bnx2x_release_nvram_lock(bp);
8420
8421 return rc;
8422}
8423
8424static int bnx2x_get_eeprom(struct net_device *dev,
8425 struct ethtool_eeprom *eeprom, u8 *eebuf)
8426{
8427 struct bnx2x *bp = netdev_priv(dev);
8428 int rc;
8429
8430 DP(NETIF_MSG_NVM, "ethtool_eeprom: cmd %d\n"
8431 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
8432 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
8433 eeprom->len, eeprom->len);
8434
8435 /* parameters already validated in ethtool_get_eeprom */
8436
8437 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
8438
8439 return rc;
8440}
8441
8442static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
8443 u32 cmd_flags)
8444{
8445 int count, i, rc;
8446
8447 /* build the command word */
8448 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
8449
8450 /* need to clear DONE bit separately */
8451 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
8452
8453 /* write the data */
8454 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
8455
8456 /* address of the NVRAM to write to */
8457 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
8458 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
8459
8460 /* issue the write command */
8461 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
8462
8463 /* adjust timeout for emulation/FPGA */
8464 count = NVRAM_TIMEOUT_COUNT;
8465 if (CHIP_REV_IS_SLOW(bp))
8466 count *= 100;
8467
8468 /* wait for completion */
8469 rc = -EBUSY;
8470 for (i = 0; i < count; i++) {
8471 udelay(5);
8472 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
8473 if (val & MCPR_NVM_COMMAND_DONE) {
8474 rc = 0;
8475 break;
8476 }
8477 }
8478
8479 return rc;
8480}
8481
8482#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
8483
8484static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
8485 int buf_size)
8486{
8487 int rc;
8488 u32 cmd_flags;
8489 u32 align_offset;
8490 u32 val;
8491
8492 if (offset + buf_size > bp->flash_size) {
8493 DP(NETIF_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8494 " buf_size (0x%x) > flash_size (0x%x)\n",
8495 offset, buf_size, bp->flash_size);
8496 return -EINVAL;
8497 }
8498
8499 /* request access to nvram interface */
8500 rc = bnx2x_acquire_nvram_lock(bp);
8501 if (rc)
8502 return rc;
8503
8504 /* enable access to nvram interface */
8505 bnx2x_enable_nvram_access(bp);
8506
8507 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
8508 align_offset = (offset & ~0x03);
8509 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
8510
8511 if (rc == 0) {
8512 val &= ~(0xff << BYTE_OFFSET(offset));
8513 val |= (*data_buf << BYTE_OFFSET(offset));
8514
8515 /* nvram data is returned as an array of bytes
8516 * convert it back to cpu order */
8517 val = be32_to_cpu(val);
8518
8519 DP(NETIF_MSG_NVM, "val 0x%08x\n", val);
8520
8521 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
8522 cmd_flags);
8523 }
8524
8525 /* disable access to nvram interface */
8526 bnx2x_disable_nvram_access(bp);
8527 bnx2x_release_nvram_lock(bp);
8528
8529 return rc;
8530}
8531
8532static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
8533 int buf_size)
8534{
8535 int rc;
8536 u32 cmd_flags;
8537 u32 val;
8538 u32 written_so_far;
8539
8540 if (buf_size == 1) { /* ethtool */
8541 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
8542 }
8543
8544 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
8545 DP(NETIF_MSG_NVM,
8546 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
8547 offset, buf_size);
8548 return -EINVAL;
8549 }
8550
8551 if (offset + buf_size > bp->flash_size) {
8552 DP(NETIF_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8553 " buf_size (0x%x) > flash_size (0x%x)\n",
8554 offset, buf_size, bp->flash_size);
8555 return -EINVAL;
8556 }
8557
8558 /* request access to nvram interface */
8559 rc = bnx2x_acquire_nvram_lock(bp);
8560 if (rc)
8561 return rc;
8562
8563 /* enable access to nvram interface */
8564 bnx2x_enable_nvram_access(bp);
8565
8566 written_so_far = 0;
8567 cmd_flags = MCPR_NVM_COMMAND_FIRST;
8568 while ((written_so_far < buf_size) && (rc == 0)) {
8569 if (written_so_far == (buf_size - sizeof(u32)))
8570 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8571 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
8572 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8573 else if ((offset % NVRAM_PAGE_SIZE) == 0)
8574 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
8575
8576 memcpy(&val, data_buf, 4);
8577 DP(NETIF_MSG_NVM, "val 0x%08x\n", val);
8578
8579 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
8580
8581 /* advance to the next dword */
8582 offset += sizeof(u32);
8583 data_buf += sizeof(u32);
8584 written_so_far += sizeof(u32);
8585 cmd_flags = 0;
8586 }
8587
8588 /* disable access to nvram interface */
8589 bnx2x_disable_nvram_access(bp);
8590 bnx2x_release_nvram_lock(bp);
8591
8592 return rc;
8593}
8594
8595static int bnx2x_set_eeprom(struct net_device *dev,
8596 struct ethtool_eeprom *eeprom, u8 *eebuf)
8597{
8598 struct bnx2x *bp = netdev_priv(dev);
8599 int rc;
8600
8601 DP(NETIF_MSG_NVM, "ethtool_eeprom: cmd %d\n"
8602 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
8603 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
8604 eeprom->len, eeprom->len);
8605
8606 /* parameters already validated in ethtool_set_eeprom */
8607
8608 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
8609
8610 return rc;
8611}
8612
8613static int bnx2x_get_coalesce(struct net_device *dev,
8614 struct ethtool_coalesce *coal)
8615{
8616 struct bnx2x *bp = netdev_priv(dev);
8617
8618 memset(coal, 0, sizeof(struct ethtool_coalesce));
8619
8620 coal->rx_coalesce_usecs = bp->rx_ticks;
8621 coal->tx_coalesce_usecs = bp->tx_ticks;
8622 coal->stats_block_coalesce_usecs = bp->stats_ticks;
8623
8624 return 0;
8625}
8626
8627static int bnx2x_set_coalesce(struct net_device *dev,
8628 struct ethtool_coalesce *coal)
8629{
8630 struct bnx2x *bp = netdev_priv(dev);
8631
8632 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
8633 if (bp->rx_ticks > 3000)
8634 bp->rx_ticks = 3000;
8635
8636 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
8637 if (bp->tx_ticks > 0x3000)
8638 bp->tx_ticks = 0x3000;
8639
8640 bp->stats_ticks = coal->stats_block_coalesce_usecs;
8641 if (bp->stats_ticks > 0xffff00)
8642 bp->stats_ticks = 0xffff00;
8643 bp->stats_ticks &= 0xffff00;
8644
8645 if (netif_running(bp->dev))
8646 bnx2x_update_coalesce(bp);
8647
8648 return 0;
8649}
8650
8651static void bnx2x_get_ringparam(struct net_device *dev,
8652 struct ethtool_ringparam *ering)
8653{
8654 struct bnx2x *bp = netdev_priv(dev);
8655
8656 ering->rx_max_pending = MAX_RX_AVAIL;
8657 ering->rx_mini_max_pending = 0;
8658 ering->rx_jumbo_max_pending = 0;
8659
8660 ering->rx_pending = bp->rx_ring_size;
8661 ering->rx_mini_pending = 0;
8662 ering->rx_jumbo_pending = 0;
8663
8664 ering->tx_max_pending = MAX_TX_AVAIL;
8665 ering->tx_pending = bp->tx_ring_size;
8666}
8667
8668static int bnx2x_set_ringparam(struct net_device *dev,
8669 struct ethtool_ringparam *ering)
8670{
8671 struct bnx2x *bp = netdev_priv(dev);
8672
8673 if ((ering->rx_pending > MAX_RX_AVAIL) ||
8674 (ering->tx_pending > MAX_TX_AVAIL) ||
8675 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
8676 return -EINVAL;
8677
8678 bp->rx_ring_size = ering->rx_pending;
8679 bp->tx_ring_size = ering->tx_pending;
8680
8681 if (netif_running(bp->dev)) {
8682 bnx2x_nic_unload(bp, 0);
8683 bnx2x_nic_load(bp, 0);
8684 }
8685
8686 return 0;
8687}
8688
8689static void bnx2x_get_pauseparam(struct net_device *dev,
8690 struct ethtool_pauseparam *epause)
8691{
8692 struct bnx2x *bp = netdev_priv(dev);
8693
8694 epause->autoneg =
8695 ((bp->req_autoneg & AUTONEG_FLOW_CTRL) == AUTONEG_FLOW_CTRL);
8696 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) == FLOW_CTRL_RX);
8697 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) == FLOW_CTRL_TX);
8698
8699 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
8700 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
8701 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
8702}
8703
8704static int bnx2x_set_pauseparam(struct net_device *dev,
8705 struct ethtool_pauseparam *epause)
8706{
8707 struct bnx2x *bp = netdev_priv(dev);
8708
8709 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
8710 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
8711 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
8712
8713 if (epause->autoneg) {
8714 if (!(bp->supported & SUPPORTED_Autoneg)) {
8715 DP(NETIF_MSG_LINK, "Aotoneg not supported\n");
8716 return -EINVAL;
8717 }
8718
8719 bp->req_autoneg |= AUTONEG_FLOW_CTRL;
8720 } else
8721 bp->req_autoneg &= ~AUTONEG_FLOW_CTRL;
8722
8723 bp->req_flow_ctrl = FLOW_CTRL_AUTO;
8724
8725 if (epause->rx_pause)
8726 bp->req_flow_ctrl |= FLOW_CTRL_RX;
8727 if (epause->tx_pause)
8728 bp->req_flow_ctrl |= FLOW_CTRL_TX;
8729
8730 if (!(bp->req_autoneg & AUTONEG_FLOW_CTRL) &&
8731 (bp->req_flow_ctrl == FLOW_CTRL_AUTO))
8732 bp->req_flow_ctrl = FLOW_CTRL_NONE;
8733
8734 DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_flow_ctrl 0x%x\n",
8735 bp->req_autoneg, bp->req_flow_ctrl);
8736
8737 bnx2x_stop_stats(bp);
8738 bnx2x_link_initialize(bp);
8739
8740 return 0;
8741}
8742
8743static u32 bnx2x_get_rx_csum(struct net_device *dev)
8744{
8745 struct bnx2x *bp = netdev_priv(dev);
8746
8747 return bp->rx_csum;
8748}
8749
8750static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
8751{
8752 struct bnx2x *bp = netdev_priv(dev);
8753
8754 bp->rx_csum = data;
8755 return 0;
8756}
8757
8758static int bnx2x_set_tso(struct net_device *dev, u32 data)
8759{
8760 if (data)
8761 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
8762 else
8763 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
8764 return 0;
8765}
8766
8767static struct {
8768 char string[ETH_GSTRING_LEN];
8769} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
8770 { "MC Errors (online)" }
8771};
8772
8773static int bnx2x_self_test_count(struct net_device *dev)
8774{
8775 return BNX2X_NUM_TESTS;
8776}
8777
8778static void bnx2x_self_test(struct net_device *dev,
8779 struct ethtool_test *etest, u64 *buf)
8780{
8781 struct bnx2x *bp = netdev_priv(dev);
8782 int stats_state;
8783
8784 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
8785
8786 if (bp->state != BNX2X_STATE_OPEN) {
8787 DP(NETIF_MSG_PROBE, "state is %x, returning\n", bp->state);
8788 return;
8789 }
8790
8791 stats_state = bp->stats_state;
8792 bnx2x_stop_stats(bp);
8793
8794 if (bnx2x_mc_assert(bp) != 0) {
8795 buf[0] = 1;
8796 etest->flags |= ETH_TEST_FL_FAILED;
8797 }
8798
8799#ifdef BNX2X_EXTRA_DEBUG
8800 bnx2x_panic_dump(bp);
8801#endif
8802 bp->stats_state = stats_state;
8803}
8804
8805static struct {
8806 char string[ETH_GSTRING_LEN];
8807} bnx2x_stats_str_arr[BNX2X_NUM_STATS] = {
8808 { "rx_bytes"},
8809 { "rx_error_bytes"},
8810 { "tx_bytes"},
8811 { "tx_error_bytes"},
8812 { "rx_ucast_packets"},
8813 { "rx_mcast_packets"},
8814 { "rx_bcast_packets"},
8815 { "tx_ucast_packets"},
8816 { "tx_mcast_packets"},
8817 { "tx_bcast_packets"},
8818 { "tx_mac_errors"}, /* 10 */
8819 { "tx_carrier_errors"},
8820 { "rx_crc_errors"},
8821 { "rx_align_errors"},
8822 { "tx_single_collisions"},
8823 { "tx_multi_collisions"},
8824 { "tx_deferred"},
8825 { "tx_excess_collisions"},
8826 { "tx_late_collisions"},
8827 { "tx_total_collisions"},
8828 { "rx_fragments"}, /* 20 */
8829 { "rx_jabbers"},
8830 { "rx_undersize_packets"},
8831 { "rx_oversize_packets"},
8832 { "rx_xon_frames"},
8833 { "rx_xoff_frames"},
8834 { "tx_xon_frames"},
8835 { "tx_xoff_frames"},
8836 { "rx_mac_ctrl_frames"},
8837 { "rx_filtered_packets"},
8838 { "rx_discards"}, /* 30 */
8839 { "brb_discard"},
8840 { "brb_truncate"},
8841 { "xxoverflow"}
8842};
8843
8844#define STATS_OFFSET32(offset_name) \
8845 (offsetof(struct bnx2x_eth_stats, offset_name) / 4)
8846
8847static unsigned long bnx2x_stats_offset_arr[BNX2X_NUM_STATS] = {
8848 STATS_OFFSET32(total_bytes_received_hi),
8849 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
8850 STATS_OFFSET32(total_bytes_transmitted_hi),
8851 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
8852 STATS_OFFSET32(total_unicast_packets_received_hi),
8853 STATS_OFFSET32(total_multicast_packets_received_hi),
8854 STATS_OFFSET32(total_broadcast_packets_received_hi),
8855 STATS_OFFSET32(total_unicast_packets_transmitted_hi),
8856 STATS_OFFSET32(total_multicast_packets_transmitted_hi),
8857 STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
8858 STATS_OFFSET32(stat_Dot3statsInternalMacTransmitErrors), /* 10 */
8859 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
8860 STATS_OFFSET32(crc_receive_errors),
8861 STATS_OFFSET32(alignment_errors),
8862 STATS_OFFSET32(single_collision_transmit_frames),
8863 STATS_OFFSET32(multiple_collision_transmit_frames),
8864 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
8865 STATS_OFFSET32(excessive_collision_frames),
8866 STATS_OFFSET32(late_collision_frames),
8867 STATS_OFFSET32(number_of_bugs_found_in_stats_spec),
8868 STATS_OFFSET32(runt_packets_received), /* 20 */
8869 STATS_OFFSET32(jabber_packets_received),
8870 STATS_OFFSET32(error_runt_packets_received),
8871 STATS_OFFSET32(error_jabber_packets_received),
8872 STATS_OFFSET32(pause_xon_frames_received),
8873 STATS_OFFSET32(pause_xoff_frames_received),
8874 STATS_OFFSET32(pause_xon_frames_transmitted),
8875 STATS_OFFSET32(pause_xoff_frames_transmitted),
8876 STATS_OFFSET32(control_frames_received),
8877 STATS_OFFSET32(mac_filter_discard),
8878 STATS_OFFSET32(no_buff_discard), /* 30 */
8879 STATS_OFFSET32(brb_discard),
8880 STATS_OFFSET32(brb_truncate_discard),
8881 STATS_OFFSET32(xxoverflow_discard)
8882};
8883
8884static u8 bnx2x_stats_len_arr[BNX2X_NUM_STATS] = {
8885 8, 0, 8, 0, 8, 8, 8, 8, 8, 8,
8886 4, 0, 4, 4, 4, 4, 4, 4, 4, 4,
8887 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
8888 4, 4, 4, 4
8889};
8890
8891static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
8892{
8893 switch (stringset) {
8894 case ETH_SS_STATS:
8895 memcpy(buf, bnx2x_stats_str_arr, sizeof(bnx2x_stats_str_arr));
8896 break;
8897
8898 case ETH_SS_TEST:
8899 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
8900 break;
8901 }
8902}
8903
8904static int bnx2x_get_stats_count(struct net_device *dev)
8905{
8906 return BNX2X_NUM_STATS;
8907}
8908
8909static void bnx2x_get_ethtool_stats(struct net_device *dev,
8910 struct ethtool_stats *stats, u64 *buf)
8911{
8912 struct bnx2x *bp = netdev_priv(dev);
8913 u32 *hw_stats = (u32 *)bnx2x_sp_check(bp, eth_stats);
8914 int i;
8915
8916 for (i = 0; i < BNX2X_NUM_STATS; i++) {
8917 if (bnx2x_stats_len_arr[i] == 0) {
8918 /* skip this counter */
8919 buf[i] = 0;
8920 continue;
8921 }
8922 if (!hw_stats) {
8923 buf[i] = 0;
8924 continue;
8925 }
8926 if (bnx2x_stats_len_arr[i] == 4) {
8927 /* 4-byte counter */
8928 buf[i] = (u64) *(hw_stats + bnx2x_stats_offset_arr[i]);
8929 continue;
8930 }
8931 /* 8-byte counter */
8932 buf[i] = HILO_U64(*(hw_stats + bnx2x_stats_offset_arr[i]),
8933 *(hw_stats + bnx2x_stats_offset_arr[i] + 1));
8934 }
8935}
8936
8937static int bnx2x_phys_id(struct net_device *dev, u32 data)
8938{
8939 struct bnx2x *bp = netdev_priv(dev);
8940 int i;
8941
8942 if (data == 0)
8943 data = 2;
8944
8945 for (i = 0; i < (data * 2); i++) {
8946 if ((i % 2) == 0) {
8947 bnx2x_leds_set(bp, SPEED_1000);
8948 } else {
8949 bnx2x_leds_unset(bp);
8950 }
8951 msleep_interruptible(500);
8952 if (signal_pending(current))
8953 break;
8954 }
8955
8956 if (bp->link_up)
8957 bnx2x_leds_set(bp, bp->line_speed);
8958
8959 return 0;
8960}
8961
8962static struct ethtool_ops bnx2x_ethtool_ops = {
8963 .get_settings = bnx2x_get_settings,
8964 .set_settings = bnx2x_set_settings,
8965 .get_drvinfo = bnx2x_get_drvinfo,
8966 .get_wol = bnx2x_get_wol,
8967 .set_wol = bnx2x_set_wol,
8968 .get_msglevel = bnx2x_get_msglevel,
8969 .set_msglevel = bnx2x_set_msglevel,
8970 .nway_reset = bnx2x_nway_reset,
8971 .get_link = ethtool_op_get_link,
8972 .get_eeprom_len = bnx2x_get_eeprom_len,
8973 .get_eeprom = bnx2x_get_eeprom,
8974 .set_eeprom = bnx2x_set_eeprom,
8975 .get_coalesce = bnx2x_get_coalesce,
8976 .set_coalesce = bnx2x_set_coalesce,
8977 .get_ringparam = bnx2x_get_ringparam,
8978 .set_ringparam = bnx2x_set_ringparam,
8979 .get_pauseparam = bnx2x_get_pauseparam,
8980 .set_pauseparam = bnx2x_set_pauseparam,
8981 .get_rx_csum = bnx2x_get_rx_csum,
8982 .set_rx_csum = bnx2x_set_rx_csum,
8983 .get_tx_csum = ethtool_op_get_tx_csum,
8984 .set_tx_csum = ethtool_op_set_tx_csum,
8985 .get_sg = ethtool_op_get_sg,
8986 .set_sg = ethtool_op_set_sg,
8987 .get_tso = ethtool_op_get_tso,
8988 .set_tso = bnx2x_set_tso,
8989 .self_test_count = bnx2x_self_test_count,
8990 .self_test = bnx2x_self_test,
8991 .get_strings = bnx2x_get_strings,
8992 .phys_id = bnx2x_phys_id,
8993 .get_stats_count = bnx2x_get_stats_count,
8994 .get_ethtool_stats = bnx2x_get_ethtool_stats
8995};
8996
8997/* end of ethtool_ops */
8998
8999/****************************************************************************
9000* General service functions
9001****************************************************************************/
9002
9003static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
9004{
9005 u16 pmcsr;
9006
9007 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
9008
9009 switch (state) {
9010 case PCI_D0:
9011 pci_write_config_word(bp->pdev,
9012 bp->pm_cap + PCI_PM_CTRL,
9013 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
9014 PCI_PM_CTRL_PME_STATUS));
9015
9016 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
9017 /* delay required during transition out of D3hot */
9018 msleep(20);
9019 break;
9020
9021 case PCI_D3hot:
9022 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9023 pmcsr |= 3;
9024
9025 if (bp->wol)
9026 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
9027
9028 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
9029 pmcsr);
9030
9031 /* No more memory access after this point until
9032 * device is brought back to D0.
9033 */
9034 break;
9035
9036 default:
9037 return -EINVAL;
9038 }
9039 return 0;
9040}
9041
9042/*
9043 * net_device service functions
9044 */
9045
9046/* called with netif_tx_lock from set_multicast */
9047static void bnx2x_set_rx_mode(struct net_device *dev)
9048{
9049 struct bnx2x *bp = netdev_priv(dev);
9050 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
9051
9052 DP(NETIF_MSG_IFUP, "called dev->flags = %x\n", dev->flags);
9053
9054 if (dev->flags & IFF_PROMISC)
9055 rx_mode = BNX2X_RX_MODE_PROMISC;
9056
9057 else if ((dev->flags & IFF_ALLMULTI) ||
9058 (dev->mc_count > BNX2X_MAX_MULTICAST))
9059 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9060
9061 else { /* some multicasts */
9062 int i, old, offset;
9063 struct dev_mc_list *mclist;
9064 struct mac_configuration_cmd *config =
9065 bnx2x_sp(bp, mcast_config);
9066
9067 for (i = 0, mclist = dev->mc_list;
9068 mclist && (i < dev->mc_count);
9069 i++, mclist = mclist->next) {
9070
9071 config->config_table[i].cam_entry.msb_mac_addr =
9072 swab16(*(u16 *)&mclist->dmi_addr[0]);
9073 config->config_table[i].cam_entry.middle_mac_addr =
9074 swab16(*(u16 *)&mclist->dmi_addr[2]);
9075 config->config_table[i].cam_entry.lsb_mac_addr =
9076 swab16(*(u16 *)&mclist->dmi_addr[4]);
9077 config->config_table[i].cam_entry.flags =
9078 cpu_to_le16(bp->port);
9079 config->config_table[i].target_table_entry.flags = 0;
9080 config->config_table[i].target_table_entry.
9081 client_id = 0;
9082 config->config_table[i].target_table_entry.
9083 vlan_id = 0;
9084
9085 DP(NETIF_MSG_IFUP,
9086 "setting MCAST[%d] (%04x:%04x:%04x)\n",
9087 i, config->config_table[i].cam_entry.msb_mac_addr,
9088 config->config_table[i].cam_entry.middle_mac_addr,
9089 config->config_table[i].cam_entry.lsb_mac_addr);
9090 }
9091 old = config->hdr.length_6b;
9092 if (old > i) {
9093 for (; i < old; i++) {
9094 if (CAM_IS_INVALID(config->config_table[i])) {
9095 i--; /* already invalidated */
9096 break;
9097 }
9098 /* invalidate */
9099 CAM_INVALIDATE(config->config_table[i]);
9100 }
9101 }
9102
9103 if (CHIP_REV_IS_SLOW(bp))
9104 offset = BNX2X_MAX_EMUL_MULTI*(1 + bp->port);
9105 else
9106 offset = BNX2X_MAX_MULTICAST*(1 + bp->port);
9107
9108 config->hdr.length_6b = i;
9109 config->hdr.offset = offset;
9110 config->hdr.reserved0 = 0;
9111 config->hdr.reserved1 = 0;
9112
9113 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
9114 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
9115 U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0);
9116 }
9117
9118 bp->rx_mode = rx_mode;
9119 bnx2x_set_storm_rx_mode(bp);
9120}
9121
9122static int bnx2x_poll(struct napi_struct *napi, int budget)
9123{
9124 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
9125 napi);
9126 struct bnx2x *bp = fp->bp;
9127 int work_done = 0;
9128
9129#ifdef BNX2X_STOP_ON_ERROR
9130 if (unlikely(bp->panic))
9131 goto out_panic;
9132#endif
9133
9134 prefetch(fp->tx_buf_ring[TX_BD(fp->tx_pkt_cons)].skb);
9135 prefetch(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb);
9136 prefetch((char *)(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb) + 256);
9137
9138 bnx2x_update_fpsb_idx(fp);
9139
9140 if (le16_to_cpu(*fp->tx_cons_sb) != fp->tx_pkt_cons)
9141 bnx2x_tx_int(fp, budget);
9142
9143
9144 if (le16_to_cpu(*fp->rx_cons_sb) != fp->rx_comp_cons)
9145 work_done = bnx2x_rx_int(fp, budget);
9146
9147
9148 rmb(); /* bnx2x_has_work() reads the status block */
9149
9150 /* must not complete if we consumed full budget */
9151 if ((work_done < budget) && !bnx2x_has_work(fp)) {
9152
9153#ifdef BNX2X_STOP_ON_ERROR
9154out_panic:
9155#endif
9156 netif_rx_complete(bp->dev, napi);
9157
9158 bnx2x_ack_sb(bp, fp->index, USTORM_ID,
9159 le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
9160 bnx2x_ack_sb(bp, fp->index, CSTORM_ID,
9161 le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
9162 }
9163
9164 return work_done;
9165}
9166
9167/* Called with netif_tx_lock.
9168 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
9169 * netif_wake_queue().
9170 */
9171static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9172{
9173 struct bnx2x *bp = netdev_priv(dev);
9174 struct bnx2x_fastpath *fp;
9175 struct sw_tx_bd *tx_buf;
9176 struct eth_tx_bd *tx_bd;
9177 struct eth_tx_parse_bd *pbd = NULL;
9178 u16 pkt_prod, bd_prod;
9179 int nbd, fp_index = 0;
9180 dma_addr_t mapping;
9181
9182#ifdef BNX2X_STOP_ON_ERROR
9183 if (unlikely(bp->panic))
9184 return NETDEV_TX_BUSY;
9185#endif
9186
9187 fp_index = smp_processor_id() % (bp->num_queues);
9188
9189 fp = &bp->fp[fp_index];
9190 if (unlikely(bnx2x_tx_avail(bp->fp) <
9191 (skb_shinfo(skb)->nr_frags + 3))) {
9192 bp->slowpath->eth_stats.driver_xoff++,
9193 netif_stop_queue(dev);
9194 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
9195 return NETDEV_TX_BUSY;
9196 }
9197
9198 /*
9199 This is a bit ugly. First we use one BD which we mark as start,
9200 then for TSO or xsum we have a parsing info BD,
9201 and only then we have the rest of the TSO bds.
9202 (don't forget to mark the last one as last,
9203 and to unmap only AFTER you write to the BD ...)
9204 I would like to thank DovH for this mess.
9205 */
9206
9207 pkt_prod = fp->tx_pkt_prod++;
9208 bd_prod = fp->tx_bd_prod;
9209 bd_prod = TX_BD(bd_prod);
9210
9211 /* get a tx_buff and first bd */
9212 tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
9213 tx_bd = &fp->tx_desc_ring[bd_prod];
9214
9215 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
9216 tx_bd->general_data = (UNICAST_ADDRESS <<
9217 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
9218 tx_bd->general_data |= 1; /* header nbd */
9219
9220 /* remember the first bd of the packet */
9221 tx_buf->first_bd = bd_prod;
9222
9223 DP(NETIF_MSG_TX_QUEUED,
9224 "sending pkt %u @%p next_idx %u bd %u @%p\n",
9225 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_bd);
9226
9227 if (skb->ip_summed == CHECKSUM_PARTIAL) {
9228 struct iphdr *iph = ip_hdr(skb);
9229 u8 len;
9230
9231 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
9232
9233 /* turn on parsing and get a bd */
9234 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9235 pbd = (void *)&fp->tx_desc_ring[bd_prod];
9236 len = ((u8 *)iph - (u8 *)skb->data) / 2;
9237
9238 /* for now NS flag is not used in Linux */
9239 pbd->global_data = (len |
9240 ((skb->protocol == ntohs(ETH_P_8021Q)) <<
9241 ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
9242 pbd->ip_hlen = ip_hdrlen(skb) / 2;
9243 pbd->total_hlen = cpu_to_le16(len + pbd->ip_hlen);
9244 if (iph->protocol == IPPROTO_TCP) {
9245 struct tcphdr *th = tcp_hdr(skb);
9246
9247 tx_bd->bd_flags.as_bitfield |=
9248 ETH_TX_BD_FLAGS_TCP_CSUM;
9249 pbd->tcp_flags = pbd_tcp_flags(skb);
9250 pbd->total_hlen += cpu_to_le16(tcp_hdrlen(skb) / 2);
9251 pbd->tcp_pseudo_csum = swab16(th->check);
9252
9253 } else if (iph->protocol == IPPROTO_UDP) {
9254 struct udphdr *uh = udp_hdr(skb);
9255
9256 tx_bd->bd_flags.as_bitfield |=
9257 ETH_TX_BD_FLAGS_TCP_CSUM;
9258 pbd->total_hlen += cpu_to_le16(4);
9259 pbd->global_data |= ETH_TX_PARSE_BD_CS_ANY_FLG;
9260 pbd->cs_offset = 5; /* 10 >> 1 */
9261 pbd->tcp_pseudo_csum = 0;
9262 /* HW bug: we need to subtract 10 bytes before the
9263 * UDP header from the csum
9264 */
9265 uh->check = (u16) ~csum_fold(csum_sub(uh->check,
9266 csum_partial(((u8 *)(uh)-10), 10, 0)));
9267 }
9268 }
9269
9270 if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb)) {
9271 tx_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb));
9272 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
9273 } else {
9274 tx_bd->vlan = cpu_to_le16(pkt_prod);
9275 }
9276
9277 mapping = pci_map_single(bp->pdev, skb->data,
9278 skb->len, PCI_DMA_TODEVICE);
9279
9280 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9281 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9282 nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL)? 1 : 2);
9283 tx_bd->nbd = cpu_to_le16(nbd);
9284 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
9285
9286 DP(NETIF_MSG_TX_QUEUED, "first bd @%p addr (%x:%x) nbd %d"
9287 " nbytes %d flags %x vlan %u\n",
9288 tx_bd, tx_bd->addr_hi, tx_bd->addr_lo, tx_bd->nbd,
9289 tx_bd->nbytes, tx_bd->bd_flags.as_bitfield, tx_bd->vlan);
9290
9291 if (skb_shinfo(skb)->gso_size &&
9292 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
9293 int hlen = 2 * le16_to_cpu(pbd->total_hlen);
9294
9295 DP(NETIF_MSG_TX_QUEUED,
9296 "TSO packet len %d hlen %d total len %d tso size %d\n",
9297 skb->len, hlen, skb_headlen(skb),
9298 skb_shinfo(skb)->gso_size);
9299
9300 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
9301
9302 if (tx_bd->nbytes > cpu_to_le16(hlen)) {
9303 /* we split the first bd into headers and data bds
9304 * to ease the pain of our fellow micocode engineers
9305 * we use one mapping for both bds
9306 * So far this has only been observed to happen
9307 * in Other Operating Systems(TM)
9308 */
9309
9310 /* first fix first bd */
9311 nbd++;
9312 tx_bd->nbd = cpu_to_le16(nbd);
9313 tx_bd->nbytes = cpu_to_le16(hlen);
9314
9315 /* we only print this as an error
9316 * because we don't think this will ever happen.
9317 */
9318 BNX2X_ERR("TSO split header size is %d (%x:%x)"
9319 " nbd %d\n", tx_bd->nbytes, tx_bd->addr_hi,
9320 tx_bd->addr_lo, tx_bd->nbd);
9321
9322 /* now get a new data bd
9323 * (after the pbd) and fill it */
9324 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9325 tx_bd = &fp->tx_desc_ring[bd_prod];
9326
9327 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9328 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping) + hlen);
9329 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb) - hlen);
9330 tx_bd->vlan = cpu_to_le16(pkt_prod);
9331 /* this marks the bd
9332 * as one that has no individual mapping
9333 * the FW ignores this flag in a bd not marked start
9334 */
9335 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO;
9336 DP(NETIF_MSG_TX_QUEUED,
9337 "TSO split data size is %d (%x:%x)\n",
9338 tx_bd->nbytes, tx_bd->addr_hi, tx_bd->addr_lo);
9339 }
9340
9341 if (!pbd) {
9342 /* supposed to be unreached
9343 * (and therefore not handled properly...)
9344 */
9345 BNX2X_ERR("LSO with no PBD\n");
9346 BUG();
9347 }
9348
9349 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
9350 pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq);
9351 pbd->ip_id = swab16(ip_hdr(skb)->id);
9352 pbd->tcp_pseudo_csum =
9353 swab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
9354 ip_hdr(skb)->daddr,
9355 0, IPPROTO_TCP, 0));
9356 pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
9357 }
9358
9359 {
9360 int i;
9361
9362 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9363 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
9364
9365 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9366 tx_bd = &fp->tx_desc_ring[bd_prod];
9367
9368 mapping = pci_map_page(bp->pdev, frag->page,
9369 frag->page_offset,
9370 frag->size, PCI_DMA_TODEVICE);
9371
9372 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9373 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9374 tx_bd->nbytes = cpu_to_le16(frag->size);
9375 tx_bd->vlan = cpu_to_le16(pkt_prod);
9376 tx_bd->bd_flags.as_bitfield = 0;
9377 DP(NETIF_MSG_TX_QUEUED, "frag %d bd @%p"
9378 " addr (%x:%x) nbytes %d flags %x\n",
9379 i, tx_bd, tx_bd->addr_hi, tx_bd->addr_lo,
9380 tx_bd->nbytes, tx_bd->bd_flags.as_bitfield);
9381 } /* for */
9382 }
9383
9384 /* now at last mark the bd as the last bd */
9385 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_END_BD;
9386
9387 DP(NETIF_MSG_TX_QUEUED, "last bd @%p flags %x\n",
9388 tx_bd, tx_bd->bd_flags.as_bitfield);
9389
9390 tx_buf->skb = skb;
9391
9392 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9393
9394 /* now send a tx doorbell, counting the next bd
9395 * if the packet contains or ends with it
9396 */
9397 if (TX_BD_POFF(bd_prod) < nbd)
9398 nbd++;
9399
9400 if (pbd)
9401 DP(NETIF_MSG_TX_QUEUED,
9402 "PBD @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u"
9403 " tcp_flags %x xsum %x seq %u hlen %u\n",
9404 pbd, pbd->global_data, pbd->ip_hlen, pbd->ip_id,
9405 pbd->lso_mss, pbd->tcp_flags, pbd->tcp_pseudo_csum,
9406 pbd->tcp_send_seq, pbd->total_hlen);
9407
9408 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %u bd %d\n", nbd, bd_prod);
9409
9410 fp->hw_tx_prods->bds_prod =
9411 cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + nbd);
9412 mb(); /* FW restriction: must not reorder writing nbd and packets */
9413 fp->hw_tx_prods->packets_prod =
9414 cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1);
9415 DOORBELL(bp, fp_index, 0);
9416
9417 mmiowb();
9418
9419 fp->tx_bd_prod = bd_prod;
9420 dev->trans_start = jiffies;
9421
9422 if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) {
9423 netif_stop_queue(dev);
9424 bp->slowpath->eth_stats.driver_xoff++;
9425 if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)
9426 netif_wake_queue(dev);
9427 }
9428 fp->tx_pkt++;
9429
9430 return NETDEV_TX_OK;
9431}
9432
9433/* Called with rtnl_lock */
9434static int bnx2x_open(struct net_device *dev)
9435{
9436 struct bnx2x *bp = netdev_priv(dev);
9437
9438 bnx2x_set_power_state(bp, PCI_D0);
9439
9440 return bnx2x_nic_load(bp, 1);
9441}
9442
9443/* Called with rtnl_lock */
9444static int bnx2x_close(struct net_device *dev)
9445{
9446 struct bnx2x *bp = netdev_priv(dev);
9447
9448 /* Unload the driver, release IRQs */
9449 bnx2x_nic_unload(bp, 1);
9450
9451 if (!CHIP_REV_IS_SLOW(bp))
9452 bnx2x_set_power_state(bp, PCI_D3hot);
9453
9454 return 0;
9455}
9456
9457/* Called with rtnl_lock */
9458static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
9459{
9460 struct sockaddr *addr = p;
9461 struct bnx2x *bp = netdev_priv(dev);
9462
9463 if (!is_valid_ether_addr(addr->sa_data))
9464 return -EINVAL;
9465
9466 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9467 if (netif_running(dev))
9468 bnx2x_set_mac_addr(bp);
9469
9470 return 0;
9471}
9472
9473/* Called with rtnl_lock */
9474static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9475{
9476 struct mii_ioctl_data *data = if_mii(ifr);
9477 struct bnx2x *bp = netdev_priv(dev);
9478 int err;
9479
9480 switch (cmd) {
9481 case SIOCGMIIPHY:
9482 data->phy_id = bp->phy_addr;
9483
9484 /* fallthrough */
9485 case SIOCGMIIREG: {
9486 u32 mii_regval;
9487
9488 spin_lock_bh(&bp->phy_lock);
9489 if (bp->state == BNX2X_STATE_OPEN) {
9490 err = bnx2x_mdio22_read(bp, data->reg_num & 0x1f,
9491 &mii_regval);
9492
9493 data->val_out = mii_regval;
9494 } else {
9495 err = -EAGAIN;
9496 }
9497 spin_unlock_bh(&bp->phy_lock);
9498 return err;
9499 }
9500
9501 case SIOCSMIIREG:
9502 if (!capable(CAP_NET_ADMIN))
9503 return -EPERM;
9504
9505 spin_lock_bh(&bp->phy_lock);
9506 if (bp->state == BNX2X_STATE_OPEN) {
9507 err = bnx2x_mdio22_write(bp, data->reg_num & 0x1f,
9508 data->val_in);
9509 } else {
9510 err = -EAGAIN;
9511 }
9512 spin_unlock_bh(&bp->phy_lock);
9513 return err;
9514
9515 default:
9516 /* do nothing */
9517 break;
9518 }
9519
9520 return -EOPNOTSUPP;
9521}
9522
9523/* Called with rtnl_lock */
9524static int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
9525{
9526 struct bnx2x *bp = netdev_priv(dev);
9527
9528 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
9529 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE))
9530 return -EINVAL;
9531
9532 /* This does not race with packet allocation
9533 * because the actual alloc size is
9534 * only updated as part of load
9535 */
9536 dev->mtu = new_mtu;
9537
9538 if (netif_running(dev)) {
9539 bnx2x_nic_unload(bp, 0);
9540 bnx2x_nic_load(bp, 0);
9541 }
9542 return 0;
9543}
9544
9545static void bnx2x_tx_timeout(struct net_device *dev)
9546{
9547 struct bnx2x *bp = netdev_priv(dev);
9548
9549#ifdef BNX2X_STOP_ON_ERROR
9550 if (!bp->panic)
9551 bnx2x_panic();
9552#endif
9553 /* This allows the netif to be shutdown gracefully before resetting */
9554 schedule_work(&bp->reset_task);
9555}
9556
9557#ifdef BCM_VLAN
9558/* Called with rtnl_lock */
9559static void bnx2x_vlan_rx_register(struct net_device *dev,
9560 struct vlan_group *vlgrp)
9561{
9562 struct bnx2x *bp = netdev_priv(dev);
9563
9564 bp->vlgrp = vlgrp;
9565 if (netif_running(dev))
9566 bnx2x_set_client_config(bp);
9567}
9568#endif
9569
9570#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
9571static void poll_bnx2x(struct net_device *dev)
9572{
9573 struct bnx2x *bp = netdev_priv(dev);
9574
9575 disable_irq(bp->pdev->irq);
9576 bnx2x_interrupt(bp->pdev->irq, dev);
9577 enable_irq(bp->pdev->irq);
9578}
9579#endif
9580
9581static void bnx2x_reset_task(struct work_struct *work)
9582{
9583 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task);
9584
9585#ifdef BNX2X_STOP_ON_ERROR
9586 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
9587 " so reset not done to allow debug dump,\n"
9588 KERN_ERR " you will need to reboot when done\n");
9589 return;
9590#endif
9591
9592 if (!netif_running(bp->dev))
9593 return;
9594
9595 rtnl_lock();
9596
9597 if (bp->state != BNX2X_STATE_OPEN) {
9598 DP(NETIF_MSG_TX_ERR, "state is %x, returning\n", bp->state);
9599 goto reset_task_exit;
9600 }
9601
9602 bnx2x_nic_unload(bp, 0);
9603 bnx2x_nic_load(bp, 0);
9604
9605reset_task_exit:
9606 rtnl_unlock();
9607}
9608
9609static int __devinit bnx2x_init_board(struct pci_dev *pdev,
9610 struct net_device *dev)
9611{
9612 struct bnx2x *bp;
9613 int rc;
9614
9615 SET_NETDEV_DEV(dev, &pdev->dev);
9616 bp = netdev_priv(dev);
9617
9618 bp->flags = 0;
9619 bp->port = PCI_FUNC(pdev->devfn);
9620
9621 rc = pci_enable_device(pdev);
9622 if (rc) {
9623 printk(KERN_ERR PFX "Cannot enable PCI device, aborting\n");
9624 goto err_out;
9625 }
9626
9627 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9628 printk(KERN_ERR PFX "Cannot find PCI device base address,"
9629 " aborting\n");
9630 rc = -ENODEV;
9631 goto err_out_disable;
9632 }
9633
9634 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9635 printk(KERN_ERR PFX "Cannot find second PCI device"
9636 " base address, aborting\n");
9637 rc = -ENODEV;
9638 goto err_out_disable;
9639 }
9640
9641 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9642 if (rc) {
9643 printk(KERN_ERR PFX "Cannot obtain PCI resources,"
9644 " aborting\n");
9645 goto err_out_disable;
9646 }
9647
9648 pci_set_master(pdev);
9649
9650 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9651 if (bp->pm_cap == 0) {
9652 printk(KERN_ERR PFX "Cannot find power management"
9653 " capability, aborting\n");
9654 rc = -EIO;
9655 goto err_out_release;
9656 }
9657
9658 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9659 if (bp->pcie_cap == 0) {
9660 printk(KERN_ERR PFX "Cannot find PCI Express capability,"
9661 " aborting\n");
9662 rc = -EIO;
9663 goto err_out_release;
9664 }
9665
9666 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
9667 bp->flags |= USING_DAC_FLAG;
9668 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
9669 printk(KERN_ERR PFX "pci_set_consistent_dma_mask"
9670 " failed, aborting\n");
9671 rc = -EIO;
9672 goto err_out_release;
9673 }
9674
9675 } else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
9676 printk(KERN_ERR PFX "System does not support DMA,"
9677 " aborting\n");
9678 rc = -EIO;
9679 goto err_out_release;
9680 }
9681
9682 bp->dev = dev;
9683 bp->pdev = pdev;
9684
9685 spin_lock_init(&bp->phy_lock);
9686
9687 INIT_WORK(&bp->reset_task, bnx2x_reset_task);
9688 INIT_WORK(&bp->sp_task, bnx2x_sp_task);
9689
9690 dev->base_addr = pci_resource_start(pdev, 0);
9691
9692 dev->irq = pdev->irq;
9693
9694 bp->regview = ioremap_nocache(dev->base_addr,
9695 pci_resource_len(pdev, 0));
9696 if (!bp->regview) {
9697 printk(KERN_ERR PFX "Cannot map register space, aborting\n");
9698 rc = -ENOMEM;
9699 goto err_out_release;
9700 }
9701
9702 bp->doorbells = ioremap_nocache(pci_resource_start(pdev , 2),
9703 pci_resource_len(pdev, 2));
9704 if (!bp->doorbells) {
9705 printk(KERN_ERR PFX "Cannot map doorbell space, aborting\n");
9706 rc = -ENOMEM;
9707 goto err_out_unmap;
9708 }
9709
9710 bnx2x_set_power_state(bp, PCI_D0);
9711
9712 bnx2x_get_hwinfo(bp);
9713
9714 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
9715 printk(KERN_ERR PFX "FPGA detected. MCP disabled,"
9716 " will only init first device\n");
9717 onefunc = 1;
9718 nomcp = 1;
9719 }
9720
9721 if (nomcp) {
9722 printk(KERN_ERR PFX "MCP disabled, will only"
9723 " init first device\n");
9724 onefunc = 1;
9725 }
9726
9727 if (onefunc && bp->port) {
9728 printk(KERN_ERR PFX "Second device disabled, exiting\n");
9729 rc = -ENODEV;
9730 goto err_out_unmap;
9731 }
9732
9733 bp->tx_ring_size = MAX_TX_AVAIL;
9734 bp->rx_ring_size = MAX_RX_AVAIL;
9735
9736 bp->rx_csum = 1;
9737
9738 bp->rx_offset = 0;
9739
9740 bp->tx_quick_cons_trip_int = 0xff;
9741 bp->tx_quick_cons_trip = 0xff;
9742 bp->tx_ticks_int = 50;
9743 bp->tx_ticks = 50;
9744
9745 bp->rx_quick_cons_trip_int = 0xff;
9746 bp->rx_quick_cons_trip = 0xff;
9747 bp->rx_ticks_int = 25;
9748 bp->rx_ticks = 25;
9749
9750 bp->stats_ticks = 1000000 & 0xffff00;
9751
9752 bp->timer_interval = HZ;
9753 bp->current_interval = (poll ? poll : HZ);
9754
9755 init_timer(&bp->timer);
9756 bp->timer.expires = jiffies + bp->current_interval;
9757 bp->timer.data = (unsigned long) bp;
9758 bp->timer.function = bnx2x_timer;
9759
9760 return 0;
9761
9762err_out_unmap:
9763 if (bp->regview) {
9764 iounmap(bp->regview);
9765 bp->regview = NULL;
9766 }
9767
9768 if (bp->doorbells) {
9769 iounmap(bp->doorbells);
9770 bp->doorbells = NULL;
9771 }
9772
9773err_out_release:
9774 pci_release_regions(pdev);
9775
9776err_out_disable:
9777 pci_disable_device(pdev);
9778 pci_set_drvdata(pdev, NULL);
9779
9780err_out:
9781 return rc;
9782}
9783
9784static int __devinit bnx2x_get_pcie_width(struct bnx2x *bp)
9785{
9786 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9787
9788 val = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
9789 return val;
9790}
9791
9792/* return value of 1=2.5GHz 2=5GHz */
9793static int __devinit bnx2x_get_pcie_speed(struct bnx2x *bp)
9794{
9795 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9796
9797 val = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
9798 return val;
9799}
9800
9801static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9802 const struct pci_device_id *ent)
9803{
9804 static int version_printed;
9805 struct net_device *dev = NULL;
9806 struct bnx2x *bp;
9807 int rc;
9808 int port = PCI_FUNC(pdev->devfn);
9809 DECLARE_MAC_BUF(mac);
9810
9811 if (version_printed++ == 0)
9812 printk(KERN_INFO "%s", version);
9813
9814 /* dev zeroed in init_etherdev */
9815 dev = alloc_etherdev(sizeof(*bp));
9816 if (!dev)
9817 return -ENOMEM;
9818
9819 netif_carrier_off(dev);
9820
9821 bp = netdev_priv(dev);
9822 bp->msglevel = debug;
9823
9824 if (port && onefunc) {
9825 printk(KERN_ERR PFX "second function disabled. exiting\n");
9826 free_netdev(dev);
9827 return 0;
9828 }
9829
9830 rc = bnx2x_init_board(pdev, dev);
9831 if (rc < 0) {
9832 free_netdev(dev);
9833 return rc;
9834 }
9835
9836 dev->hard_start_xmit = bnx2x_start_xmit;
9837 dev->watchdog_timeo = TX_TIMEOUT;
9838
9839 dev->ethtool_ops = &bnx2x_ethtool_ops;
9840 dev->open = bnx2x_open;
9841 dev->stop = bnx2x_close;
9842 dev->set_multicast_list = bnx2x_set_rx_mode;
9843 dev->set_mac_address = bnx2x_change_mac_addr;
9844 dev->do_ioctl = bnx2x_ioctl;
9845 dev->change_mtu = bnx2x_change_mtu;
9846 dev->tx_timeout = bnx2x_tx_timeout;
9847#ifdef BCM_VLAN
9848 dev->vlan_rx_register = bnx2x_vlan_rx_register;
9849#endif
9850#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
9851 dev->poll_controller = poll_bnx2x;
9852#endif
9853 dev->features |= NETIF_F_SG;
9854 if (bp->flags & USING_DAC_FLAG)
9855 dev->features |= NETIF_F_HIGHDMA;
9856 dev->features |= NETIF_F_IP_CSUM;
9857#ifdef BCM_VLAN
9858 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
9859#endif
9860 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
9861
9862 rc = register_netdev(dev);
9863 if (rc) {
9864 dev_err(&pdev->dev, "Cannot register net device\n");
9865 if (bp->regview)
9866 iounmap(bp->regview);
9867 if (bp->doorbells)
9868 iounmap(bp->doorbells);
9869 pci_release_regions(pdev);
9870 pci_disable_device(pdev);
9871 pci_set_drvdata(pdev, NULL);
9872 free_netdev(dev);
9873 return rc;
9874 }
9875
9876 pci_set_drvdata(pdev, dev);
9877
9878 bp->name = board_info[ent->driver_data].name;
9879 printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx,"
9880 " IRQ %d, ", dev->name, bp->name,
9881 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
9882 ((CHIP_ID(bp) & 0x0ff0) >> 4),
9883 bnx2x_get_pcie_width(bp),
9884 (bnx2x_get_pcie_speed(bp) == 2) ? "5GHz (Gen2)" : "2.5GHz",
9885 dev->base_addr, bp->pdev->irq);
9886 printk(KERN_CONT "node addr %s\n", print_mac(mac, dev->dev_addr));
9887 return 0;
9888}
9889
9890static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9891{
9892 struct net_device *dev = pci_get_drvdata(pdev);
9893 struct bnx2x *bp;
9894
9895 if (!dev) {
9896 /* we get here if init_one() fails */
9897 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
9898 return;
9899 }
9900
9901 bp = netdev_priv(dev);
9902
9903 unregister_netdev(dev);
9904
9905 if (bp->regview)
9906 iounmap(bp->regview);
9907
9908 if (bp->doorbells)
9909 iounmap(bp->doorbells);
9910
9911 free_netdev(dev);
9912 pci_release_regions(pdev);
9913 pci_disable_device(pdev);
9914 pci_set_drvdata(pdev, NULL);
9915}
9916
9917static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
9918{
9919 struct net_device *dev = pci_get_drvdata(pdev);
9920 struct bnx2x *bp;
9921
9922 if (!dev)
9923 return 0;
9924
9925 if (!netif_running(dev))
9926 return 0;
9927
9928 bp = netdev_priv(dev);
9929
9930 bnx2x_nic_unload(bp, 0);
9931
9932 netif_device_detach(dev);
9933
9934 pci_save_state(pdev);
9935 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
9936
9937 return 0;
9938}
9939
9940static int bnx2x_resume(struct pci_dev *pdev)
9941{
9942 struct net_device *dev = pci_get_drvdata(pdev);
9943 struct bnx2x *bp;
9944 int rc;
9945
9946 if (!dev) {
9947 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
9948 return -ENODEV;
9949 }
9950
9951 if (!netif_running(dev))
9952 return 0;
9953
9954 bp = netdev_priv(dev);
9955
9956 pci_restore_state(pdev);
9957 bnx2x_set_power_state(bp, PCI_D0);
9958 netif_device_attach(dev);
9959
9960 rc = bnx2x_nic_load(bp, 0);
9961 if (rc)
9962 return rc;
9963
9964 return 0;
9965}
9966
9967static struct pci_driver bnx2x_pci_driver = {
9968 .name = DRV_MODULE_NAME,
9969 .id_table = bnx2x_pci_tbl,
9970 .probe = bnx2x_init_one,
9971 .remove = __devexit_p(bnx2x_remove_one),
9972 .suspend = bnx2x_suspend,
9973 .resume = bnx2x_resume,
9974};
9975
9976static int __init bnx2x_init(void)
9977{
9978 return pci_register_driver(&bnx2x_pci_driver);
9979}
9980
9981static void __exit bnx2x_cleanup(void)
9982{
9983 pci_unregister_driver(&bnx2x_pci_driver);
9984}
9985
9986module_init(bnx2x_init);
9987module_exit(bnx2x_cleanup);
9988
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 8e68d06510a6..4bf4f7b205f2 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -14,39 +14,46 @@
14#ifndef BNX2X_H 14#ifndef BNX2X_H
15#define BNX2X_H 15#define BNX2X_H
16 16
17/* compilation time flags */
18
19/* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21/* #define BNX2X_STOP_ON_ERROR */
22
17/* error/debug prints */ 23/* error/debug prints */
18 24
19#define DRV_MODULE_NAME "bnx2x" 25#define DRV_MODULE_NAME "bnx2x"
20#define PFX DRV_MODULE_NAME ": " 26#define PFX DRV_MODULE_NAME ": "
21 27
22/* for messages that are currently off */ 28/* for messages that are currently off */
23#define BNX2X_MSG_OFF 0 29#define BNX2X_MSG_OFF 0
24#define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */ 30#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
25#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */ 31#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
26#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */ 32#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
27#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */ 33#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
28#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ 34#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
29#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ 35#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
30 36
31#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ 37#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
32 38
33/* regular debug print */ 39/* regular debug print */
34#define DP(__mask, __fmt, __args...) do { \ 40#define DP(__mask, __fmt, __args...) do { \
35 if (bp->msglevel & (__mask)) \ 41 if (bp->msglevel & (__mask)) \
36 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \ 42 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
37 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ 43 bp->dev?(bp->dev->name):"?", ##__args); \
38 } while (0) 44 } while (0)
39 45
40/* for errors (never masked) */ 46/* errors debug print */
41#define BNX2X_ERR(__fmt, __args...) do { \ 47#define BNX2X_DBG_ERR(__fmt, __args...) do { \
42 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \ 48 if (bp->msglevel & NETIF_MSG_PROBE) \
43 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ 49 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
50 bp->dev?(bp->dev->name):"?", ##__args); \
44 } while (0) 51 } while (0)
45 52
46/* for logging (never masked) */ 53/* for errors (never masked) */
47#define BNX2X_LOG(__fmt, __args...) do { \ 54#define BNX2X_ERR(__fmt, __args...) do { \
48 printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \ 55 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
49 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ 56 bp->dev?(bp->dev->name):"?", ##__args); \
50 } while (0) 57 } while (0)
51 58
52/* before we have a dev->name use dev_info() */ 59/* before we have a dev->name use dev_info() */
@@ -60,7 +67,7 @@
60#define bnx2x_panic() do { \ 67#define bnx2x_panic() do { \
61 bp->panic = 1; \ 68 bp->panic = 1; \
62 BNX2X_ERR("driver assert\n"); \ 69 BNX2X_ERR("driver assert\n"); \
63 bnx2x_disable_int(bp); \ 70 bnx2x_int_disable(bp); \
64 bnx2x_panic_dump(bp); \ 71 bnx2x_panic_dump(bp); \
65 } while (0) 72 } while (0)
66#else 73#else
@@ -71,164 +78,412 @@
71#endif 78#endif
72 79
73 80
74#define U64_LO(x) (((u64)x) & 0xffffffff) 81#ifdef NETIF_F_HW_VLAN_TX
75#define U64_HI(x) (((u64)x) >> 32) 82#define BCM_VLAN 1
76#define HILO_U64(hi, lo) (((u64)hi << 32) + lo) 83#endif
84
77 85
86#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
87#define U64_HI(x) (u32)(((u64)(x)) >> 32)
88#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
78 89
79#define REG_ADDR(bp, offset) (bp->regview + offset)
80 90
81#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 91#define REG_ADDR(bp, offset) (bp->regview + offset)
82#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
83#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
84 92
85#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 93#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
94#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
95#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
96
97#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
86#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 98#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
87#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 99#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
88#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val) 100#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
101
102#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
103#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
89 104
90#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 105#define REG_RD_DMAE(bp, offset, valp, len32) \
91#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 106 do { \
107 bnx2x_read_dmae(bp, offset, len32);\
108 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
109 } while (0)
92 110
93#define REG_WR_DMAE(bp, offset, val, len32) \ 111#define REG_WR_DMAE(bp, offset, valp, len32) \
94 do { \ 112 do { \
95 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \ 113 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
96 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 114 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
97 offset, len32); \ 115 offset, len32); \
98 } while (0) 116 } while (0)
99 117
100#define SHMEM_RD(bp, type) \ 118#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
101 REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type)) 119 offsetof(struct shmem_region, field))
102#define SHMEM_WR(bp, type, val) \ 120#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
103 REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val) 121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
104 122
105#define NIG_WR(reg, val) REG_WR(bp, reg, val) 123#define NIG_WR(reg, val) REG_WR(bp, reg, val)
106#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) 124#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
107#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val) 125#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
108 126
109 127
110#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++) 128#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
111 129
112#define for_each_nondefault_queue(bp, var) \ 130#define for_each_nondefault_queue(bp, var) \
113 for (var = 1; var < bp->num_queues; var++) 131 for (var = 1; var < bp->num_queues; var++)
114#define is_multi(bp) (bp->num_queues > 1) 132#define is_multi(bp) (bp->num_queues > 1)
115 133
116 134
117struct regp { 135/* fast path */
118 u32 lo; 136
119 u32 hi; 137struct sw_rx_bd {
138 struct sk_buff *skb;
139 DECLARE_PCI_UNMAP_ADDR(mapping)
140};
141
142struct sw_tx_bd {
143 struct sk_buff *skb;
144 u16 first_bd;
120}; 145};
121 146
122struct bmac_stats { 147struct sw_rx_page {
123 struct regp tx_gtpkt; 148 struct page *page;
124 struct regp tx_gtxpf; 149 DECLARE_PCI_UNMAP_ADDR(mapping)
125 struct regp tx_gtfcs;
126 struct regp tx_gtmca;
127 struct regp tx_gtgca;
128 struct regp tx_gtfrg;
129 struct regp tx_gtovr;
130 struct regp tx_gt64;
131 struct regp tx_gt127;
132 struct regp tx_gt255; /* 10 */
133 struct regp tx_gt511;
134 struct regp tx_gt1023;
135 struct regp tx_gt1518;
136 struct regp tx_gt2047;
137 struct regp tx_gt4095;
138 struct regp tx_gt9216;
139 struct regp tx_gt16383;
140 struct regp tx_gtmax;
141 struct regp tx_gtufl;
142 struct regp tx_gterr; /* 20 */
143 struct regp tx_gtbyt;
144
145 struct regp rx_gr64;
146 struct regp rx_gr127;
147 struct regp rx_gr255;
148 struct regp rx_gr511;
149 struct regp rx_gr1023;
150 struct regp rx_gr1518;
151 struct regp rx_gr2047;
152 struct regp rx_gr4095;
153 struct regp rx_gr9216; /* 30 */
154 struct regp rx_gr16383;
155 struct regp rx_grmax;
156 struct regp rx_grpkt;
157 struct regp rx_grfcs;
158 struct regp rx_grmca;
159 struct regp rx_grbca;
160 struct regp rx_grxcf;
161 struct regp rx_grxpf;
162 struct regp rx_grxuo;
163 struct regp rx_grjbr; /* 40 */
164 struct regp rx_grovr;
165 struct regp rx_grflr;
166 struct regp rx_grmeg;
167 struct regp rx_grmeb;
168 struct regp rx_grbyt;
169 struct regp rx_grund;
170 struct regp rx_grfrg;
171 struct regp rx_grerb;
172 struct regp rx_grfre;
173 struct regp rx_gripj; /* 50 */
174}; 150};
175 151
176struct emac_stats { 152
177 u32 rx_ifhcinoctets ; 153/* MC hsi */
178 u32 rx_ifhcinbadoctets ; 154#define BCM_PAGE_SHIFT 12
179 u32 rx_etherstatsfragments ; 155#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
180 u32 rx_ifhcinucastpkts ; 156#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
181 u32 rx_ifhcinmulticastpkts ; 157#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
182 u32 rx_ifhcinbroadcastpkts ; 158
183 u32 rx_dot3statsfcserrors ; 159#define PAGES_PER_SGE_SHIFT 0
184 u32 rx_dot3statsalignmenterrors ; 160#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
185 u32 rx_dot3statscarriersenseerrors ; 161
186 u32 rx_xonpauseframesreceived ; /* 10 */ 162/* SGE ring related macros */
187 u32 rx_xoffpauseframesreceived ; 163#define NUM_RX_SGE_PAGES 2
188 u32 rx_maccontrolframesreceived ; 164#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
189 u32 rx_xoffstateentered ; 165#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
190 u32 rx_dot3statsframestoolong ; 166/* RX_SGE_CNT is promissed to be a power of 2 */
191 u32 rx_etherstatsjabbers ; 167#define RX_SGE_MASK (RX_SGE_CNT - 1)
192 u32 rx_etherstatsundersizepkts ; 168#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
193 u32 rx_etherstatspkts64octets ; 169#define MAX_RX_SGE (NUM_RX_SGE - 1)
194 u32 rx_etherstatspkts65octetsto127octets ; 170#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
195 u32 rx_etherstatspkts128octetsto255octets ; 171 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
196 u32 rx_etherstatspkts256octetsto511octets ; /* 20 */ 172#define RX_SGE(x) ((x) & MAX_RX_SGE)
197 u32 rx_etherstatspkts512octetsto1023octets ; 173
198 u32 rx_etherstatspkts1024octetsto1522octets; 174/* SGE producer mask related macros */
199 u32 rx_etherstatspktsover1522octets ; 175/* Number of bits in one sge_mask array element */
200 176#define RX_SGE_MASK_ELEM_SZ 64
201 u32 rx_falsecarriererrors ; 177#define RX_SGE_MASK_ELEM_SHIFT 6
202 178#define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
203 u32 tx_ifhcoutoctets ; 179
204 u32 tx_ifhcoutbadoctets ; 180/* Creates a bitmask of all ones in less significant bits.
205 u32 tx_etherstatscollisions ; 181 idx - index of the most significant bit in the created mask */
206 u32 tx_outxonsent ; 182#define RX_SGE_ONES_MASK(idx) \
207 u32 tx_outxoffsent ; 183 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
208 u32 tx_flowcontroldone ; /* 30 */ 184#define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
209 u32 tx_dot3statssinglecollisionframes ; 185
210 u32 tx_dot3statsmultiplecollisionframes ; 186/* Number of u64 elements in SGE mask array */
211 u32 tx_dot3statsdeferredtransmissions ; 187#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
212 u32 tx_dot3statsexcessivecollisions ; 188 RX_SGE_MASK_ELEM_SZ)
213 u32 tx_dot3statslatecollisions ; 189#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
214 u32 tx_ifhcoutucastpkts ; 190#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
215 u32 tx_ifhcoutmulticastpkts ; 191
216 u32 tx_ifhcoutbroadcastpkts ; 192
217 u32 tx_etherstatspkts64octets ; 193struct bnx2x_fastpath {
218 u32 tx_etherstatspkts65octetsto127octets ; /* 40 */ 194
219 u32 tx_etherstatspkts128octetsto255octets ; 195 struct napi_struct napi;
220 u32 tx_etherstatspkts256octetsto511octets ; 196
221 u32 tx_etherstatspkts512octetsto1023octets ; 197 struct host_status_block *status_blk;
222 u32 tx_etherstatspkts1024octetsto1522octet ; 198 dma_addr_t status_blk_mapping;
223 u32 tx_etherstatspktsover1522octets ; 199
224 u32 tx_dot3statsinternalmactransmiterrors ; /* 46 */ 200 struct eth_tx_db_data *hw_tx_prods;
201 dma_addr_t tx_prods_mapping;
202
203 struct sw_tx_bd *tx_buf_ring;
204
205 struct eth_tx_bd *tx_desc_ring;
206 dma_addr_t tx_desc_mapping;
207
208 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
209 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
210
211 struct eth_rx_bd *rx_desc_ring;
212 dma_addr_t rx_desc_mapping;
213
214 union eth_rx_cqe *rx_comp_ring;
215 dma_addr_t rx_comp_mapping;
216
217 /* SGE ring */
218 struct eth_rx_sge *rx_sge_ring;
219 dma_addr_t rx_sge_mapping;
220
221 u64 sge_mask[RX_SGE_MASK_LEN];
222
223 int state;
224#define BNX2X_FP_STATE_CLOSED 0
225#define BNX2X_FP_STATE_IRQ 0x80000
226#define BNX2X_FP_STATE_OPENING 0x90000
227#define BNX2X_FP_STATE_OPEN 0xa0000
228#define BNX2X_FP_STATE_HALTING 0xb0000
229#define BNX2X_FP_STATE_HALTED 0xc0000
230
231 u8 index; /* number in fp array */
232 u8 cl_id; /* eth client id */
233 u8 sb_id; /* status block number in HW */
234#define FP_IDX(fp) (fp->index)
235#define FP_CL_ID(fp) (fp->cl_id)
236#define BP_CL_ID(bp) (bp->fp[0].cl_id)
237#define FP_SB_ID(fp) (fp->sb_id)
238#define CNIC_SB_ID 0
239
240 u16 tx_pkt_prod;
241 u16 tx_pkt_cons;
242 u16 tx_bd_prod;
243 u16 tx_bd_cons;
244 u16 *tx_cons_sb;
245
246 u16 fp_c_idx;
247 u16 fp_u_idx;
248
249 u16 rx_bd_prod;
250 u16 rx_bd_cons;
251 u16 rx_comp_prod;
252 u16 rx_comp_cons;
253 u16 rx_sge_prod;
254 /* The last maximal completed SGE */
255 u16 last_max_sge;
256 u16 *rx_cons_sb;
257 u16 *rx_bd_cons_sb;
258
259 unsigned long tx_pkt,
260 rx_pkt,
261 rx_calls,
262 rx_alloc_failed;
263 /* TPA related */
264 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
265 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
266#define BNX2X_TPA_START 1
267#define BNX2X_TPA_STOP 2
268 u8 disable_tpa;
269#ifdef BNX2X_STOP_ON_ERROR
270 u64 tpa_queue_used;
271#endif
272
273 struct bnx2x *bp; /* parent */
225}; 274};
226 275
227union mac_stats { 276#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
228 struct emac_stats emac; 277
229 struct bmac_stats bmac; 278
279/* MC hsi */
280#define MAX_FETCH_BD 13 /* HW max BDs per packet */
281#define RX_COPY_THRESH 92
282
283#define NUM_TX_RINGS 16
284#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
285#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
286#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
287#define MAX_TX_BD (NUM_TX_BD - 1)
288#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
289#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
290 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
291#define TX_BD(x) ((x) & MAX_TX_BD)
292#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
293
294/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
295#define NUM_RX_RINGS 8
296#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
297#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
298#define RX_DESC_MASK (RX_DESC_CNT - 1)
299#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
300#define MAX_RX_BD (NUM_RX_BD - 1)
301#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
302#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
303 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
304#define RX_BD(x) ((x) & MAX_RX_BD)
305
306/* As long as CQE is 4 times bigger than BD entry we have to allocate
307 4 times more pages for CQ ring in order to keep it balanced with
308 BD ring */
309#define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
310#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
311#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
312#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
313#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
314#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
315#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
316 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
317#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
318
319
320/* This is needed for determening of last_max */
321#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
322
323#define __SGE_MASK_SET_BIT(el, bit) \
324 do { \
325 el = ((el) | ((u64)0x1 << (bit))); \
326 } while (0)
327
328#define __SGE_MASK_CLEAR_BIT(el, bit) \
329 do { \
330 el = ((el) & (~((u64)0x1 << (bit)))); \
331 } while (0)
332
333#define SGE_MASK_SET_BIT(fp, idx) \
334 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
335 ((idx) & RX_SGE_MASK_ELEM_MASK))
336
337#define SGE_MASK_CLEAR_BIT(fp, idx) \
338 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
339 ((idx) & RX_SGE_MASK_ELEM_MASK))
340
341
342/* used on a CID received from the HW */
343#define SW_CID(x) (le32_to_cpu(x) & \
344 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
345#define CQE_CMD(x) (le32_to_cpu(x) >> \
346 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
347
348#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
349 le32_to_cpu((bd)->addr_lo))
350#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
351
352
353#define DPM_TRIGER_TYPE 0x40
354#define DOORBELL(bp, cid, val) \
355 do { \
356 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
357 DPM_TRIGER_TYPE); \
358 } while (0)
359
360
361/* TX CSUM helpers */
362#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
363 skb->csum_offset)
364#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
365 skb->csum_offset))
366
367#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
368
369#define XMIT_PLAIN 0
370#define XMIT_CSUM_V4 0x1
371#define XMIT_CSUM_V6 0x2
372#define XMIT_CSUM_TCP 0x4
373#define XMIT_GSO_V4 0x8
374#define XMIT_GSO_V6 0x10
375
376#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
377#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
378
379
380/* stuff added to make the code fit 80Col */
381
382#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
383
384#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
385#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
386#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
387 (TPA_TYPE_START | TPA_TYPE_END))
388
389#define BNX2X_RX_SUM_OK(cqe) \
390 (!(cqe->fast_path_cqe.status_flags & \
391 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
392 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
393
394#define BNX2X_RX_SUM_FIX(cqe) \
395 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
396 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
397 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
398
399#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
400 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
401 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
402
403
404#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
405#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
406
407#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
408#define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
409#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
410
411#define BNX2X_RX_SB_INDEX \
412 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
413
414#define BNX2X_RX_SB_BD_INDEX \
415 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
416
417#define BNX2X_RX_SB_INDEX_NUM \
418 (((U_SB_ETH_RX_CQ_INDEX << \
419 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
420 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
421 ((U_SB_ETH_RX_BD_INDEX << \
422 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
423 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
424
425#define BNX2X_TX_SB_INDEX \
426 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
427
428
429/* end of fast path */
430
431/* common */
432
433struct bnx2x_common {
434
435 u32 chip_id;
436/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
437#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
438
439#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
440#define CHIP_NUM_57710 0x164e
441#define CHIP_NUM_57711 0x164f
442#define CHIP_NUM_57711E 0x1650
443#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
444#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
445#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
446#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
447 CHIP_IS_57711E(bp))
448#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
449
450#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
451#define CHIP_REV_Ax 0x00000000
452/* assume maximum 5 revisions */
453#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
454/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
455#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
456 !(CHIP_REV(bp) & 0x00001000))
457/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
458#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
459 (CHIP_REV(bp) & 0x00001000))
460
461#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
462 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
463
464#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
465#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
466
467 int flash_size;
468#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
469#define NVRAM_TIMEOUT_COUNT 30000
470#define NVRAM_PAGE_SIZE 256
471
472 u32 shmem_base;
473
474 u32 hw_config;
475 u32 board;
476
477 u32 bc_ver;
478
479 char *name;
230}; 480};
231 481
482
483/* end of common */
484
485/* port */
486
232struct nig_stats { 487struct nig_stats {
233 u32 brb_discard; 488 u32 brb_discard;
234 u32 brb_packet; 489 u32 brb_packet;
@@ -244,13 +499,53 @@ struct nig_stats {
244 u32 pbf_octets; 499 u32 pbf_octets;
245 u32 pbf_packet; 500 u32 pbf_packet;
246 u32 safc_inp; 501 u32 safc_inp;
247 u32 done; 502 u32 egress_mac_pkt0_lo;
248 u32 pad; 503 u32 egress_mac_pkt0_hi;
504 u32 egress_mac_pkt1_lo;
505 u32 egress_mac_pkt1_hi;
506};
507
508struct bnx2x_port {
509 u32 pmf;
510
511 u32 link_config;
512
513 u32 supported;
514/* link settings - missing defines */
515#define SUPPORTED_2500baseX_Full (1 << 15)
516
517 u32 advertising;
518/* link settings - missing defines */
519#define ADVERTISED_2500baseX_Full (1 << 15)
520
521 u32 phy_addr;
522
523 /* used to synchronize phy accesses */
524 struct mutex phy_mutex;
525
526 u32 port_stx;
527
528 struct nig_stats old_nig_stats;
529};
530
531/* end of port */
532
533
534enum bnx2x_stats_event {
535 STATS_EVENT_PMF = 0,
536 STATS_EVENT_LINK_UP,
537 STATS_EVENT_UPDATE,
538 STATS_EVENT_STOP,
539 STATS_EVENT_MAX
540};
541
542enum bnx2x_stats_state {
543 STATS_STATE_DISABLED = 0,
544 STATS_STATE_ENABLED,
545 STATS_STATE_MAX
249}; 546};
250 547
251struct bnx2x_eth_stats { 548struct bnx2x_eth_stats {
252 u32 pad; /* to make long counters u64 aligned */
253 u32 mac_stx_start;
254 u32 total_bytes_received_hi; 549 u32 total_bytes_received_hi;
255 u32 total_bytes_received_lo; 550 u32 total_bytes_received_lo;
256 u32 total_bytes_transmitted_hi; 551 u32 total_bytes_transmitted_hi;
@@ -267,97 +562,117 @@ struct bnx2x_eth_stats {
267 u32 total_multicast_packets_transmitted_lo; 562 u32 total_multicast_packets_transmitted_lo;
268 u32 total_broadcast_packets_transmitted_hi; 563 u32 total_broadcast_packets_transmitted_hi;
269 u32 total_broadcast_packets_transmitted_lo; 564 u32 total_broadcast_packets_transmitted_lo;
270 u32 crc_receive_errors;
271 u32 alignment_errors;
272 u32 false_carrier_detections;
273 u32 runt_packets_received;
274 u32 jabber_packets_received;
275 u32 pause_xon_frames_received;
276 u32 pause_xoff_frames_received;
277 u32 pause_xon_frames_transmitted;
278 u32 pause_xoff_frames_transmitted;
279 u32 single_collision_transmit_frames;
280 u32 multiple_collision_transmit_frames;
281 u32 late_collision_frames;
282 u32 excessive_collision_frames;
283 u32 control_frames_received;
284 u32 frames_received_64_bytes;
285 u32 frames_received_65_127_bytes;
286 u32 frames_received_128_255_bytes;
287 u32 frames_received_256_511_bytes;
288 u32 frames_received_512_1023_bytes;
289 u32 frames_received_1024_1522_bytes;
290 u32 frames_received_1523_9022_bytes;
291 u32 frames_transmitted_64_bytes;
292 u32 frames_transmitted_65_127_bytes;
293 u32 frames_transmitted_128_255_bytes;
294 u32 frames_transmitted_256_511_bytes;
295 u32 frames_transmitted_512_1023_bytes;
296 u32 frames_transmitted_1024_1522_bytes;
297 u32 frames_transmitted_1523_9022_bytes;
298 u32 valid_bytes_received_hi; 565 u32 valid_bytes_received_hi;
299 u32 valid_bytes_received_lo; 566 u32 valid_bytes_received_lo;
300 u32 error_runt_packets_received; 567
301 u32 error_jabber_packets_received; 568 u32 error_bytes_received_hi;
302 u32 mac_stx_end; 569 u32 error_bytes_received_lo;
303 570
304 u32 pad2; 571 u32 rx_stat_ifhcinbadoctets_hi;
305 u32 stat_IfHCInBadOctets_hi; 572 u32 rx_stat_ifhcinbadoctets_lo;
306 u32 stat_IfHCInBadOctets_lo; 573 u32 tx_stat_ifhcoutbadoctets_hi;
307 u32 stat_IfHCOutBadOctets_hi; 574 u32 tx_stat_ifhcoutbadoctets_lo;
308 u32 stat_IfHCOutBadOctets_lo; 575 u32 rx_stat_dot3statsfcserrors_hi;
309 u32 stat_Dot3statsFramesTooLong; 576 u32 rx_stat_dot3statsfcserrors_lo;
310 u32 stat_Dot3statsInternalMacTransmitErrors; 577 u32 rx_stat_dot3statsalignmenterrors_hi;
311 u32 stat_Dot3StatsCarrierSenseErrors; 578 u32 rx_stat_dot3statsalignmenterrors_lo;
312 u32 stat_Dot3StatsDeferredTransmissions; 579 u32 rx_stat_dot3statscarriersenseerrors_hi;
313 u32 stat_FlowControlDone; 580 u32 rx_stat_dot3statscarriersenseerrors_lo;
314 u32 stat_XoffStateEntered; 581 u32 rx_stat_falsecarriererrors_hi;
315 582 u32 rx_stat_falsecarriererrors_lo;
316 u32 x_total_sent_bytes_hi; 583 u32 rx_stat_etherstatsundersizepkts_hi;
317 u32 x_total_sent_bytes_lo; 584 u32 rx_stat_etherstatsundersizepkts_lo;
318 u32 x_total_sent_pkts; 585 u32 rx_stat_dot3statsframestoolong_hi;
319 586 u32 rx_stat_dot3statsframestoolong_lo;
320 u32 t_rcv_unicast_bytes_hi; 587 u32 rx_stat_etherstatsfragments_hi;
321 u32 t_rcv_unicast_bytes_lo; 588 u32 rx_stat_etherstatsfragments_lo;
322 u32 t_rcv_broadcast_bytes_hi; 589 u32 rx_stat_etherstatsjabbers_hi;
323 u32 t_rcv_broadcast_bytes_lo; 590 u32 rx_stat_etherstatsjabbers_lo;
324 u32 t_rcv_multicast_bytes_hi; 591 u32 rx_stat_maccontrolframesreceived_hi;
325 u32 t_rcv_multicast_bytes_lo; 592 u32 rx_stat_maccontrolframesreceived_lo;
326 u32 t_total_rcv_pkt; 593 u32 rx_stat_bmac_xpf_hi;
327 594 u32 rx_stat_bmac_xpf_lo;
328 u32 checksum_discard; 595 u32 rx_stat_bmac_xcf_hi;
329 u32 packets_too_big_discard; 596 u32 rx_stat_bmac_xcf_lo;
597 u32 rx_stat_xoffstateentered_hi;
598 u32 rx_stat_xoffstateentered_lo;
599 u32 rx_stat_xonpauseframesreceived_hi;
600 u32 rx_stat_xonpauseframesreceived_lo;
601 u32 rx_stat_xoffpauseframesreceived_hi;
602 u32 rx_stat_xoffpauseframesreceived_lo;
603 u32 tx_stat_outxonsent_hi;
604 u32 tx_stat_outxonsent_lo;
605 u32 tx_stat_outxoffsent_hi;
606 u32 tx_stat_outxoffsent_lo;
607 u32 tx_stat_flowcontroldone_hi;
608 u32 tx_stat_flowcontroldone_lo;
609 u32 tx_stat_etherstatscollisions_hi;
610 u32 tx_stat_etherstatscollisions_lo;
611 u32 tx_stat_dot3statssinglecollisionframes_hi;
612 u32 tx_stat_dot3statssinglecollisionframes_lo;
613 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
614 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
615 u32 tx_stat_dot3statsdeferredtransmissions_hi;
616 u32 tx_stat_dot3statsdeferredtransmissions_lo;
617 u32 tx_stat_dot3statsexcessivecollisions_hi;
618 u32 tx_stat_dot3statsexcessivecollisions_lo;
619 u32 tx_stat_dot3statslatecollisions_hi;
620 u32 tx_stat_dot3statslatecollisions_lo;
621 u32 tx_stat_etherstatspkts64octets_hi;
622 u32 tx_stat_etherstatspkts64octets_lo;
623 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
624 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
625 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
626 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
627 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
628 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
629 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
630 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
631 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
632 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
633 u32 tx_stat_etherstatspktsover1522octets_hi;
634 u32 tx_stat_etherstatspktsover1522octets_lo;
635 u32 tx_stat_bmac_2047_hi;
636 u32 tx_stat_bmac_2047_lo;
637 u32 tx_stat_bmac_4095_hi;
638 u32 tx_stat_bmac_4095_lo;
639 u32 tx_stat_bmac_9216_hi;
640 u32 tx_stat_bmac_9216_lo;
641 u32 tx_stat_bmac_16383_hi;
642 u32 tx_stat_bmac_16383_lo;
643 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
644 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
645 u32 tx_stat_bmac_ufl_hi;
646 u32 tx_stat_bmac_ufl_lo;
647
648 u32 brb_drop_hi;
649 u32 brb_drop_lo;
650
651 u32 jabber_packets_received;
652
653 u32 etherstatspkts1024octetsto1522octets_hi;
654 u32 etherstatspkts1024octetsto1522octets_lo;
655 u32 etherstatspktsover1522octets_hi;
656 u32 etherstatspktsover1522octets_lo;
657
330 u32 no_buff_discard; 658 u32 no_buff_discard;
331 u32 ttl0_discard; 659
332 u32 mac_discard;
333 u32 mac_filter_discard; 660 u32 mac_filter_discard;
334 u32 xxoverflow_discard; 661 u32 xxoverflow_discard;
335 u32 brb_truncate_discard; 662 u32 brb_truncate_discard;
663 u32 mac_discard;
336 664
337 u32 brb_discard;
338 u32 brb_packet;
339 u32 brb_truncate;
340 u32 flow_ctrl_discard;
341 u32 flow_ctrl_octets;
342 u32 flow_ctrl_packet;
343 u32 mng_discard;
344 u32 mng_octet_inp;
345 u32 mng_octet_out;
346 u32 mng_packet_inp;
347 u32 mng_packet_out;
348 u32 pbf_octets;
349 u32 pbf_packet;
350 u32 safc_inp;
351 u32 driver_xoff; 665 u32 driver_xoff;
352 u32 number_of_bugs_found_in_stats_spec; /* just kidding */
353}; 666};
354 667
355#define MAC_STX_NA 0xffffffff 668#define STATS_OFFSET32(stat_name) \
669 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
670
356 671
357#ifdef BNX2X_MULTI 672#ifdef BNX2X_MULTI
358#define MAX_CONTEXT 16 673#define MAX_CONTEXT 16
359#else 674#else
360#define MAX_CONTEXT 1 675#define MAX_CONTEXT 1
361#endif 676#endif
362 677
363union cdu_context { 678union cdu_context {
@@ -365,345 +680,191 @@ union cdu_context {
365 char pad[1024]; 680 char pad[1024];
366}; 681};
367 682
368#define MAX_DMAE_C 5 683#define MAX_DMAE_C 8
369 684
370/* DMA memory not used in fastpath */ 685/* DMA memory not used in fastpath */
371struct bnx2x_slowpath { 686struct bnx2x_slowpath {
372 union cdu_context context[MAX_CONTEXT]; 687 union cdu_context context[MAX_CONTEXT];
373 struct eth_stats_query fw_stats; 688 struct eth_stats_query fw_stats;
374 struct mac_configuration_cmd mac_config; 689 struct mac_configuration_cmd mac_config;
375 struct mac_configuration_cmd mcast_config; 690 struct mac_configuration_cmd mcast_config;
376 691
377 /* used by dmae command executer */ 692 /* used by dmae command executer */
378 struct dmae_command dmae[MAX_DMAE_C]; 693 struct dmae_command dmae[MAX_DMAE_C];
379 694
380 union mac_stats mac_stats; 695 u32 stats_comp;
381 struct nig_stats nig; 696 union mac_stats mac_stats;
382 struct bnx2x_eth_stats eth_stats; 697 struct nig_stats nig_stats;
698 struct host_port_stats port_stats;
699 struct host_func_stats func_stats;
383 700
384 u32 wb_comp; 701 u32 wb_comp;
385#define BNX2X_WB_COMP_VAL 0xe0d0d0ae 702 u32 wb_data[4];
386 u32 wb_data[4];
387}; 703};
388 704
389#define bnx2x_sp(bp, var) (&bp->slowpath->var) 705#define bnx2x_sp(bp, var) (&bp->slowpath->var)
390#define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL)
391#define bnx2x_sp_mapping(bp, var) \ 706#define bnx2x_sp_mapping(bp, var) \
392 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 707 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
393 708
394 709
395struct sw_rx_bd {
396 struct sk_buff *skb;
397 DECLARE_PCI_UNMAP_ADDR(mapping)
398};
399
400struct sw_tx_bd {
401 struct sk_buff *skb;
402 u16 first_bd;
403};
404
405struct bnx2x_fastpath {
406
407 struct napi_struct napi;
408
409 struct host_status_block *status_blk;
410 dma_addr_t status_blk_mapping;
411
412 struct eth_tx_db_data *hw_tx_prods;
413 dma_addr_t tx_prods_mapping;
414
415 struct sw_tx_bd *tx_buf_ring;
416
417 struct eth_tx_bd *tx_desc_ring;
418 dma_addr_t tx_desc_mapping;
419
420 struct sw_rx_bd *rx_buf_ring;
421
422 struct eth_rx_bd *rx_desc_ring;
423 dma_addr_t rx_desc_mapping;
424
425 union eth_rx_cqe *rx_comp_ring;
426 dma_addr_t rx_comp_mapping;
427
428 int state;
429#define BNX2X_FP_STATE_CLOSED 0
430#define BNX2X_FP_STATE_IRQ 0x80000
431#define BNX2X_FP_STATE_OPENING 0x90000
432#define BNX2X_FP_STATE_OPEN 0xa0000
433#define BNX2X_FP_STATE_HALTING 0xb0000
434#define BNX2X_FP_STATE_HALTED 0xc0000
435
436 int index;
437
438 u16 tx_pkt_prod;
439 u16 tx_pkt_cons;
440 u16 tx_bd_prod;
441 u16 tx_bd_cons;
442 u16 *tx_cons_sb;
443
444 u16 fp_c_idx;
445 u16 fp_u_idx;
446
447 u16 rx_bd_prod;
448 u16 rx_bd_cons;
449 u16 rx_comp_prod;
450 u16 rx_comp_cons;
451 u16 *rx_cons_sb;
452
453 unsigned long tx_pkt,
454 rx_pkt,
455 rx_calls;
456
457 struct bnx2x *bp; /* parent */
458};
459
460#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
461
462
463/* attn group wiring */ 710/* attn group wiring */
464#define MAX_DYNAMIC_ATTN_GRPS 8 711#define MAX_DYNAMIC_ATTN_GRPS 8
465 712
466struct attn_route { 713struct attn_route {
467 u32 sig[4]; 714 u32 sig[4];
468}; 715};
469 716
470struct bnx2x { 717struct bnx2x {
471 /* Fields used in the tx and intr/napi performance paths 718 /* Fields used in the tx and intr/napi performance paths
472 * are grouped together in the beginning of the structure 719 * are grouped together in the beginning of the structure
473 */ 720 */
474 struct bnx2x_fastpath *fp; 721 struct bnx2x_fastpath fp[MAX_CONTEXT];
475 void __iomem *regview; 722 void __iomem *regview;
476 void __iomem *doorbells; 723 void __iomem *doorbells;
724#define BNX2X_DB_SIZE (16*2048)
477 725
478 struct net_device *dev; 726 struct net_device *dev;
479 struct pci_dev *pdev; 727 struct pci_dev *pdev;
480 728
481 atomic_t intr_sem; 729 atomic_t intr_sem;
482 struct msix_entry msix_table[MAX_CONTEXT+1]; 730 struct msix_entry msix_table[MAX_CONTEXT+1];
483 731
484 int tx_ring_size; 732 int tx_ring_size;
485 733
486#ifdef BCM_VLAN 734#ifdef BCM_VLAN
487 struct vlan_group *vlgrp; 735 struct vlan_group *vlgrp;
488#endif 736#endif
489 737
490 u32 rx_csum; 738 u32 rx_csum;
491 u32 rx_offset; 739 u32 rx_offset;
492 u32 rx_buf_use_size; /* useable size */ 740 u32 rx_buf_use_size; /* useable size */
493 u32 rx_buf_size; /* with alignment */ 741 u32 rx_buf_size; /* with alignment */
494#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ 742#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
495#define ETH_MIN_PACKET_SIZE 60 743#define ETH_MIN_PACKET_SIZE 60
496#define ETH_MAX_PACKET_SIZE 1500 744#define ETH_MAX_PACKET_SIZE 1500
497#define ETH_MAX_JUMBO_PACKET_SIZE 9600 745#define ETH_MAX_JUMBO_PACKET_SIZE 9600
498 746
499 struct host_def_status_block *def_status_blk; 747 struct host_def_status_block *def_status_blk;
500#define DEF_SB_ID 16 748#define DEF_SB_ID 16
501 u16 def_c_idx; 749 u16 def_c_idx;
502 u16 def_u_idx; 750 u16 def_u_idx;
503 u16 def_t_idx; 751 u16 def_x_idx;
504 u16 def_x_idx; 752 u16 def_t_idx;
505 u16 def_att_idx; 753 u16 def_att_idx;
506 u32 attn_state; 754 u32 attn_state;
507 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 755 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
508 u32 aeu_mask; 756 u32 aeu_mask;
509 u32 nig_mask; 757 u32 nig_mask;
510 758
511 /* slow path ring */ 759 /* slow path ring */
512 struct eth_spe *spq; 760 struct eth_spe *spq;
513 dma_addr_t spq_mapping; 761 dma_addr_t spq_mapping;
514 u16 spq_prod_idx; 762 u16 spq_prod_idx;
515 struct eth_spe *spq_prod_bd; 763 struct eth_spe *spq_prod_bd;
516 struct eth_spe *spq_last_bd; 764 struct eth_spe *spq_last_bd;
517 u16 *dsb_sp_prod; 765 u16 *dsb_sp_prod;
518 u16 spq_left; /* serialize spq */ 766 u16 spq_left; /* serialize spq */
519 spinlock_t spq_lock; 767 /* used to synchronize spq accesses */
520 768 spinlock_t spq_lock;
521 /* Flag for marking that there is either 769
522 * STAT_QUERY or CFC DELETE ramrod pending 770 /* Flags for marking that there is a STAT_QUERY or
523 */ 771 SET_MAC ramrod pending */
524 u8 stat_pending; 772 u8 stats_pending;
525 773 u8 set_mac_pending;
526 /* End of fields used in the performance code paths */ 774
527 775 /* End of fileds used in the performance code paths */
528 int panic; 776
529 int msglevel; 777 int panic;
530 778 int msglevel;
531 u32 flags; 779
532#define PCIX_FLAG 1 780 u32 flags;
533#define PCI_32BIT_FLAG 2 781#define PCIX_FLAG 1
534#define ONE_TDMA_FLAG 4 /* no longer used */ 782#define PCI_32BIT_FLAG 2
535#define NO_WOL_FLAG 8 783#define ONE_TDMA_FLAG 4 /* no longer used */
536#define USING_DAC_FLAG 0x10 784#define NO_WOL_FLAG 8
537#define USING_MSIX_FLAG 0x20 785#define USING_DAC_FLAG 0x10
538#define ASF_ENABLE_FLAG 0x40 786#define USING_MSIX_FLAG 0x20
539 787#define ASF_ENABLE_FLAG 0x40
540 int port; 788#define TPA_ENABLE_FLAG 0x80
541 789#define NO_MCP_FLAG 0x100
542 int pm_cap; 790#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
543 int pcie_cap; 791
544 792 int func;
545 /* Used to synchronize phy accesses */ 793#define BP_PORT(bp) (bp->func % PORT_MAX)
546 spinlock_t phy_lock; 794#define BP_FUNC(bp) (bp->func)
547 795#define BP_E1HVN(bp) (bp->func >> 1)
548 struct work_struct reset_task; 796#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
549 struct work_struct sp_task; 797/* assorted E1HVN */
550 798#define IS_E1HMF(bp) (bp->e1hmf != 0)
551 struct timer_list timer; 799#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
552 int timer_interval; 800
553 int current_interval; 801 int pm_cap;
554 802 int pcie_cap;
555 u32 shmem_base; 803
556 804 struct work_struct sp_task;
557 u32 chip_id; 805 struct work_struct reset_task;
558/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 806
559#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) 807 struct timer_list timer;
560 808 int timer_interval;
561#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) 809 int current_interval;
562 810
563#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) 811 u16 fw_seq;
564#define CHIP_REV_Ax 0x00000000 812 u16 fw_drv_pulse_wr_seq;
565#define CHIP_REV_Bx 0x00001000 813 u32 func_stx;
566#define CHIP_REV_Cx 0x00002000 814
567#define CHIP_REV_EMUL 0x0000e000 815 struct link_params link_params;
568#define CHIP_REV_FPGA 0x0000f000 816 struct link_vars link_vars;
569#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \ 817
570 (CHIP_REV(bp) == CHIP_REV_FPGA)) 818 struct bnx2x_common common;
571 819 struct bnx2x_port port;
572#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) 820
573#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f) 821 u32 mf_config;
574 822 u16 e1hov;
575 u16 fw_seq; 823 u8 e1hmf;
576 u16 fw_drv_pulse_wr_seq;
577 u32 fw_mb;
578
579 u32 hw_config;
580 u32 board;
581 u32 serdes_config;
582 u32 lane_config;
583 u32 ext_phy_config;
584#define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
585 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
586#define SERDES_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
587 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
588
589 u32 speed_cap_mask;
590 u32 link_config;
591#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
592#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
593#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
594#define SWITCH_CFG_ONE_TIME_DETECT \
595 PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
596
597 u8 ser_lane;
598 u8 rx_lane_swap;
599 u8 tx_lane_swap;
600
601 u8 link_up;
602 u8 phy_link_up;
603
604 u32 supported;
605/* link settings - missing defines */
606#define SUPPORTED_2500baseT_Full (1 << 15)
607
608 u32 phy_flags;
609/*#define PHY_SERDES_FLAG 0x1*/
610#define PHY_BMAC_FLAG 0x2
611#define PHY_EMAC_FLAG 0x4
612#define PHY_XGXS_FLAG 0x8
613#define PHY_SGMII_FLAG 0x10
614#define PHY_INT_MODE_MASK_FLAG 0x300
615#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
616#define PHY_INT_MODE_LINK_READY_FLAG 0x200
617
618 u32 phy_addr;
619 u32 phy_id;
620
621 u32 autoneg;
622#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
623#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
624#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
625#define AUTONEG_PARALLEL \
626 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
627#define AUTONEG_SGMII_FIBER_AUTODET \
628 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
629#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
630
631 u32 req_autoneg;
632#define AUTONEG_SPEED 0x1
633#define AUTONEG_FLOW_CTRL 0x2
634
635 u32 req_line_speed;
636/* link settings - missing defines */
637#define SPEED_12000 12000
638#define SPEED_12500 12500
639#define SPEED_13000 13000
640#define SPEED_15000 15000
641#define SPEED_16000 16000
642
643 u32 req_duplex;
644 u32 req_flow_ctrl;
645#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
646#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
647#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
648#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
649#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
650
651 u32 advertising;
652/* link settings - missing defines */
653#define ADVERTISED_2500baseT_Full (1 << 15)
654
655 u32 link_status;
656 u32 line_speed;
657 u32 duplex;
658 u32 flow_ctrl;
659
660 u32 bc_ver;
661
662 int flash_size;
663#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
664#define NVRAM_TIMEOUT_COUNT 30000
665#define NVRAM_PAGE_SIZE 256
666 824
667 u8 wol; 825 u8 wol;
668 826
669 int rx_ring_size; 827 int rx_ring_size;
670 828
671 u16 tx_quick_cons_trip_int; 829 u16 tx_quick_cons_trip_int;
672 u16 tx_quick_cons_trip; 830 u16 tx_quick_cons_trip;
673 u16 tx_ticks_int; 831 u16 tx_ticks_int;
674 u16 tx_ticks; 832 u16 tx_ticks;
675 833
676 u16 rx_quick_cons_trip_int; 834 u16 rx_quick_cons_trip_int;
677 u16 rx_quick_cons_trip; 835 u16 rx_quick_cons_trip;
678 u16 rx_ticks_int; 836 u16 rx_ticks_int;
679 u16 rx_ticks; 837 u16 rx_ticks;
680 838
681 u32 stats_ticks; 839 u32 stats_ticks;
840 u32 lin_cnt;
682 841
683 int state; 842 int state;
684#define BNX2X_STATE_CLOSED 0x0 843#define BNX2X_STATE_CLOSED 0x0
685#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 844#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
686#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 845#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
687#define BNX2X_STATE_OPEN 0x3000 846#define BNX2X_STATE_OPEN 0x3000
688#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 847#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
689#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 848#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
690#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 849#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
691#define BNX2X_STATE_ERROR 0xF000 850#define BNX2X_STATE_DISABLED 0xd000
851#define BNX2X_STATE_DIAG 0xe000
852#define BNX2X_STATE_ERROR 0xf000
692 853
693 int num_queues; 854 int num_queues;
694 855
695 u32 rx_mode; 856 u32 rx_mode;
696#define BNX2X_RX_MODE_NONE 0 857#define BNX2X_RX_MODE_NONE 0
697#define BNX2X_RX_MODE_NORMAL 1 858#define BNX2X_RX_MODE_NORMAL 1
698#define BNX2X_RX_MODE_ALLMULTI 2 859#define BNX2X_RX_MODE_ALLMULTI 2
699#define BNX2X_RX_MODE_PROMISC 3 860#define BNX2X_RX_MODE_PROMISC 3
700#define BNX2X_MAX_MULTICAST 64 861#define BNX2X_MAX_MULTICAST 64
701#define BNX2X_MAX_EMUL_MULTI 16 862#define BNX2X_MAX_EMUL_MULTI 16
702 863
703 dma_addr_t def_status_blk_mapping; 864 dma_addr_t def_status_blk_mapping;
704 865
705 struct bnx2x_slowpath *slowpath; 866 struct bnx2x_slowpath *slowpath;
706 dma_addr_t slowpath_mapping; 867 dma_addr_t slowpath_mapping;
707 868
708#ifdef BCM_ISCSI 869#ifdef BCM_ISCSI
709 void *t1; 870 void *t1;
@@ -716,264 +877,164 @@ struct bnx2x {
716 dma_addr_t qm_mapping; 877 dma_addr_t qm_mapping;
717#endif 878#endif
718 879
719 char *name; 880 int dmae_ready;
881 /* used to synchronize dmae accesses */
882 struct mutex dmae_mutex;
883 struct dmae_command init_dmae;
720 884
721 /* used to synchronize stats collecting */ 885 /* used to synchronize stats collecting */
722 int stats_state; 886 int stats_state;
723#define STATS_STATE_DISABLE 0
724#define STATS_STATE_ENABLE 1
725#define STATS_STATE_STOP 2 /* stop stats on next iteration */
726
727 /* used by dmae command loader */ 887 /* used by dmae command loader */
728 struct dmae_command dmae; 888 struct dmae_command stats_dmae;
729 int executer_idx; 889 int executer_idx;
730 890
731 u32 old_brb_discard; 891 u16 stats_counter;
732 struct bmac_stats old_bmac;
733 struct tstorm_per_client_stats old_tclient; 892 struct tstorm_per_client_stats old_tclient;
734 struct z_stream_s *strm; 893 struct xstorm_per_client_stats old_xclient;
735 void *gunzip_buf; 894 struct bnx2x_eth_stats eth_stats;
736 dma_addr_t gunzip_mapping;
737 int gunzip_outlen;
738#define FW_BUF_SIZE 0x8000
739
740};
741 895
896 struct z_stream_s *strm;
897 void *gunzip_buf;
898 dma_addr_t gunzip_mapping;
899 int gunzip_outlen;
900#define FW_BUF_SIZE 0x8000
742 901
743/* DMAE command defines */ 902};
744#define DMAE_CMD_SRC_PCI 0
745#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
746 903
747#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
748#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
749 904
750#define DMAE_CMD_C_DST_PCI 0 905void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
751#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT) 906void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
907 u32 len32);
908int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
752 909
753#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 910static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
911 int wait)
912{
913 u32 val;
754 914
755#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 915 do {
756#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 916 val = REG_RD(bp, reg);
757#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 917 if (val == expected)
758#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 918 break;
919 ms -= wait;
920 msleep(wait);
759 921
760#define DMAE_CMD_PORT_0 0 922 } while (ms > 0);
761#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
762 923
763#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 924 return val;
764#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 925}
765 926
766#define DMAE_LEN32_MAX 0x400
767 927
928/* load/unload mode */
929#define LOAD_NORMAL 0
930#define LOAD_OPEN 1
931#define LOAD_DIAG 2
932#define UNLOAD_NORMAL 0
933#define UNLOAD_CLOSE 1
768 934
769/* MC hsi */
770#define RX_COPY_THRESH 92
771#define BCM_PAGE_BITS 12
772#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
773
774#define NUM_TX_RINGS 16
775#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
776#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
777#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
778#define MAX_TX_BD (NUM_TX_BD - 1)
779#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
780#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
781 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
782#define TX_BD(x) ((x) & MAX_TX_BD)
783#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
784 935
785/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 936/* DMAE command defines */
786#define NUM_RX_RINGS 8 937#define DMAE_CMD_SRC_PCI 0
787#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 938#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
788#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
789#define RX_DESC_MASK (RX_DESC_CNT - 1)
790#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
791#define MAX_RX_BD (NUM_RX_BD - 1)
792#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
793#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
794 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
795#define RX_BD(x) ((x) & MAX_RX_BD)
796 939
797#define NUM_RCQ_RINGS (NUM_RX_RINGS * 2) 940#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
798#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 941#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
799#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
800#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
801#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
802#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
803#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
804 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
805#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
806 942
943#define DMAE_CMD_C_DST_PCI 0
944#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
807 945
808/* used on a CID received from the HW */ 946#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
809#define SW_CID(x) (le32_to_cpu(x) & \
810 (COMMON_RAMROD_ETH_RX_CQE_CID >> 1))
811#define CQE_CMD(x) (le32_to_cpu(x) >> \
812 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
813 947
814#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 948#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
815 le32_to_cpu((bd)->addr_lo)) 949#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
816#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 950#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
951#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
817 952
953#define DMAE_CMD_PORT_0 0
954#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
818 955
819#define STROM_ASSERT_ARRAY_SIZE 50 956#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
957#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
958#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
820 959
960#define DMAE_LEN32_RD_MAX 0x80
961#define DMAE_LEN32_WR_MAX 0x400
821 962
822#define MDIO_INDIRECT_REG_ADDR 0x1f 963#define DMAE_COMP_VAL 0xe0d0d0ae
823#define MDIO_SET_REG_BANK(bp, reg_bank) \
824 bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
825 964
826#define MDIO_ACCESS_TIMEOUT 1000 965#define MAX_DMAE_C_PER_PORT 8
966#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
967 BP_E1HVN(bp))
968#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
969 E1HVN_MAX)
827 970
828 971
829/* must be used on a CID before placing it on a HW ring */ 972/* PCIE link and speed */
830#define HW_CID(bp, x) (x | (bp->port << 23)) 973#define PCICFG_LINK_WIDTH 0x1f00000
974#define PCICFG_LINK_WIDTH_SHIFT 20
975#define PCICFG_LINK_SPEED 0xf0000
976#define PCICFG_LINK_SPEED_SHIFT 16
831 977
832#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
833#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
834 978
835#define ATTN_NIG_FOR_FUNC (1L << 8) 979#define BNX2X_NUM_STATS 39
836#define ATTN_SW_TIMER_4_FUNC (1L << 9) 980#define BNX2X_NUM_TESTS 8
837#define GPIO_2_FUNC (1L << 10)
838#define GPIO_3_FUNC (1L << 11)
839#define GPIO_4_FUNC (1L << 12)
840#define ATTN_GENERAL_ATTN_1 (1L << 13)
841#define ATTN_GENERAL_ATTN_2 (1L << 14)
842#define ATTN_GENERAL_ATTN_3 (1L << 15)
843#define ATTN_GENERAL_ATTN_4 (1L << 13)
844#define ATTN_GENERAL_ATTN_5 (1L << 14)
845#define ATTN_GENERAL_ATTN_6 (1L << 15)
846 981
847#define ATTN_HARD_WIRED_MASK 0xff00 982#define BNX2X_MAC_LOOPBACK 0
848#define ATTENTION_ID 4 983#define BNX2X_PHY_LOOPBACK 1
984#define BNX2X_MAC_LOOPBACK_FAILED 1
985#define BNX2X_PHY_LOOPBACK_FAILED 2
986#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
987 BNX2X_PHY_LOOPBACK_FAILED)
849 988
850 989
851#define BNX2X_BTR 3 990#define STROM_ASSERT_ARRAY_SIZE 50
852#define MAX_SPQ_PENDING 8
853 991
854 992
855#define BNX2X_NUM_STATS 34 993/* must be used on a CID before placing it on a HW ring */
856#define BNX2X_NUM_TESTS 1 994#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
857 995
996#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
997#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
858 998
859#define DPM_TRIGER_TYPE 0x40
860#define DOORBELL(bp, cid, val) \
861 do { \
862 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
863 DPM_TRIGER_TYPE); \
864 } while (0)
865 999
866/* PCIE link and speed */ 1000#define BNX2X_BTR 3
867#define PCICFG_LINK_WIDTH 0x1f00000 1001#define MAX_SPQ_PENDING 8
868#define PCICFG_LINK_WIDTH_SHIFT 20
869#define PCICFG_LINK_SPEED 0xf0000
870#define PCICFG_LINK_SPEED_SHIFT 16
871 1002
872#define BMAC_CONTROL_RX_ENABLE 2
873 1003
874#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 1004/* CMNG constants
1005 derived from lab experiments, and not from system spec calculations !!! */
1006#define DEF_MIN_RATE 100
1007/* resolution of the rate shaping timer - 100 usec */
1008#define RS_PERIODIC_TIMEOUT_USEC 100
1009/* resolution of fairness algorithm in usecs -
1010 coefficient for clauclating the actuall t fair */
1011#define T_FAIR_COEF 10000000
1012/* number of bytes in single QM arbitration cycle -
1013 coeffiecnt for calculating the fairness timer */
1014#define QM_ARB_BYTES 40000
1015#define FAIR_MEM 2
875 1016
876/* stuff added to make the code fit 80Col */
877 1017
878#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG 1018#define ATTN_NIG_FOR_FUNC (1L << 8)
879#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG 1019#define ATTN_SW_TIMER_4_FUNC (1L << 9)
880#define TPA_TYPE(cqe) (cqe->fast_path_cqe.error_type_flags & \ 1020#define GPIO_2_FUNC (1L << 10)
881 (TPA_TYPE_START | TPA_TYPE_END)) 1021#define GPIO_3_FUNC (1L << 11)
882#define BNX2X_RX_SUM_OK(cqe) \ 1022#define GPIO_4_FUNC (1L << 12)
883 (!(cqe->fast_path_cqe.status_flags & \ 1023#define ATTN_GENERAL_ATTN_1 (1L << 13)
884 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \ 1024#define ATTN_GENERAL_ATTN_2 (1L << 14)
885 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG))) 1025#define ATTN_GENERAL_ATTN_3 (1L << 15)
1026#define ATTN_GENERAL_ATTN_4 (1L << 13)
1027#define ATTN_GENERAL_ATTN_5 (1L << 14)
1028#define ATTN_GENERAL_ATTN_6 (1L << 15)
886 1029
887#define BNX2X_RX_SUM_FIX(cqe) \ 1030#define ATTN_HARD_WIRED_MASK 0xff00
888 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ 1031#define ATTENTION_ID 4
889 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
890 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
891 1032
892 1033
893#define MDIO_AN_CL73_OR_37_COMPLETE \ 1034/* stuff added to make the code fit 80Col */
894 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
895 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
896
897#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
898 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
899#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
900 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
901#define GP_STATUS_SPEED_MASK \
902 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
903#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
904#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
905#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
906#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
907#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
908#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
909#define GP_STATUS_10G_HIG \
910 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
911#define GP_STATUS_10G_CX4 \
912 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
913#define GP_STATUS_12G_HIG \
914 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
915#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
916#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
917#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
918#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
919#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
920#define GP_STATUS_10G_KX4 \
921 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
922
923#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
924#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
925#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
926#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
927#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
928#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
929#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
930#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
931#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
932#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
933#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
934#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
935#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
936#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
937#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
938#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
939#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
940#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
941#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
942#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
943#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
944#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
945#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
946
947#define NIG_STATUS_XGXS0_LINK10G \
948 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
949#define NIG_STATUS_XGXS0_LINK_STATUS \
950 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
951#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
952 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
953#define NIG_STATUS_SERDES0_LINK_STATUS \
954 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
955#define NIG_MASK_MI_INT \
956 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
957#define NIG_MASK_XGXS0_LINK10G \
958 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
959#define NIG_MASK_XGXS0_LINK_STATUS \
960 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
961#define NIG_MASK_SERDES0_LINK_STATUS \
962 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
963
964#define XGXS_RESET_BITS \
965 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
966 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
967 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
968 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
969 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
970
971#define SERDES_RESET_BITS \
972 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
973 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
974 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
975 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
976 1035
1036#define BNX2X_PMF_LINK_ASSERT \
1037 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
977 1038
978#define BNX2X_MC_ASSERT_BITS \ 1039#define BNX2X_MC_ASSERT_BITS \
979 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1040 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
@@ -987,12 +1048,20 @@ struct bnx2x {
987#define BNX2X_DOORQ_ASSERT \ 1048#define BNX2X_DOORQ_ASSERT \
988 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT 1049 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
989 1050
1051#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1052#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1053 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1054 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1055 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1056 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1057 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1058
990#define HW_INTERRUT_ASSERT_SET_0 \ 1059#define HW_INTERRUT_ASSERT_SET_0 \
991 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 1060 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
992 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 1061 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
993 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 1062 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
994 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) 1063 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
995#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 1064#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
996 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 1065 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
997 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 1066 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
998 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 1067 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
@@ -1009,7 +1078,7 @@ struct bnx2x {
1009 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 1078 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1010 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 1079 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1011 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 1080 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1012#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ 1081#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1013 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 1082 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1014 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 1083 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1015 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 1084 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
@@ -1026,7 +1095,7 @@ struct bnx2x {
1026 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 1095 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1027 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 1096 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1028 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 1097 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1029#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 1098#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1030 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 1099 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1031 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 1100 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1032 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 1101 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
@@ -1035,42 +1104,44 @@ struct bnx2x {
1035 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 1104 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1036 1105
1037 1106
1038#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
1039 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
1040 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
1041
1042
1043#define MULTI_FLAGS \ 1107#define MULTI_FLAGS \
1044 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ 1108 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1045 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ 1109 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1046 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ 1110 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1047 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ 1111 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1048 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE) 1112 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
1049
1050#define MULTI_MASK 0x7f
1051 1113
1114#define MULTI_MASK 0x7f
1052 1115
1053#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
1054#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
1055#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1056 1116
1057#define BNX2X_RX_SB_INDEX \ 1117#define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1058 &fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX] 1118#define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1119#define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1120#define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1059 1121
1060#define BNX2X_TX_SB_INDEX \ 1122#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1061 &fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]
1062 1123
1063#define BNX2X_SP_DSB_INDEX \ 1124#define BNX2X_SP_DSB_INDEX \
1064&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX] 1125(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1065 1126
1066 1127
1067#define CAM_IS_INVALID(x) \ 1128#define CAM_IS_INVALID(x) \
1068(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) 1129(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1069 1130
1070#define CAM_INVALIDATE(x) \ 1131#define CAM_INVALIDATE(x) \
1071x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE 1132 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1072 1133
1073 1134
1135/* Number of u32 elements in MC hash array */
1136#define MC_HASH_SIZE 8
1137#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1138 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1139
1140
1141#ifndef PXP2_REG_PXP2_INT_STS
1142#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1143#endif
1144
1074/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */ 1145/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1075 1146
1076#endif /* bnx2x.h */ 1147#endif /* bnx2x.h */
diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h
index 3b968904ca65..e3da7f69d27b 100644
--- a/drivers/net/bnx2x_fw_defs.h
+++ b/drivers/net/bnx2x_fw_defs.h
@@ -8,191 +8,390 @@
8 */ 8 */
9 9
10 10
11#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\ 11#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
12 (0x1922 + (port * 0x40) + (index * 0x4)) 12 (IS_E1H_OFFSET? 0x7000 : 0x1000)
13#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\ 13#define CSTORM_ASSERT_LIST_OFFSET(idx) \
14 (0x1900 + (port * 0x40)) 14 (IS_E1H_OFFSET? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
15#define CSTORM_HC_BTR_OFFSET(port)\ 15#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
16 (0x1984 + (port * 0xc0)) 16 (IS_E1H_OFFSET? (0x8522 + ((function>>1) * 0x40) + ((function&1) \
17#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\ 17 * 0x100) + (index * 0x4)) : (0x1922 + (function * 0x40) + (index \
18 (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4)) 18 * 0x4)))
19#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\ 19#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
20 (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4)) 20 (IS_E1H_OFFSET? (0x8500 + ((function>>1) * 0x40) + ((function&1) \
21#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\ 21 * 0x100)) : (0x1900 + (function * 0x40)))
22 (0x1400 + (port * 0x280) + (cpu_id * 0x28)) 22#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
23#define CSTORM_STATS_FLAGS_OFFSET(port) (0x5108 + (port * 0x8)) 23 (IS_E1H_OFFSET? (0x8508 + ((function>>1) * 0x40) + ((function&1) \
24#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id)\ 24 * 0x100)) : (0x1908 + (function * 0x40)))
25 (0x1510 + (port * 0x240) + (client_id * 0x20)) 25#define CSTORM_FUNCTION_MODE_OFFSET \
26#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\ 26 (IS_E1H_OFFSET? 0x11e8 : 0xffffffff)
27 (0x138a + (port * 0x28) + (index * 0x4)) 27#define CSTORM_HC_BTR_OFFSET(port) \
28#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\ 28 (IS_E1H_OFFSET? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
29 (0x1370 + (port * 0x28)) 29#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
30#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\ 30 (IS_E1H_OFFSET? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
31 (0x4b70 + (port * 0x8)) 31 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
32#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function)\ 32 (index * 0x4)))
33 (0x1418 + (function * 0x30)) 33#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
34#define TSTORM_HC_BTR_OFFSET(port)\ 34 (IS_E1H_OFFSET? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
35 (0x13c4 + (port * 0x18)) 35 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
36#define TSTORM_INDIRECTION_TABLE_OFFSET(port)\ 36 (index * 0x4)))
37 (0x22c8 + (port * 0x80)) 37#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
38#define TSTORM_INDIRECTION_TABLE_SIZE 0x80 38 (IS_E1H_OFFSET? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
39#define TSTORM_MAC_FILTER_CONFIG_OFFSET(port)\ 39 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
40 (0x1420 + (port * 0x30)) 40#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
41#define TSTORM_RCQ_PROD_OFFSET(port, client_id)\ 41 (IS_E1H_OFFSET? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
42 (0x1508 + (port * 0x240) + (client_id * 0x20)) 42 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
43#define TSTORM_STATS_FLAGS_OFFSET(port) (0x4b90 + (port * 0x8)) 43#define CSTORM_STATS_FLAGS_OFFSET(function) \
44#define USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\ 44 (IS_E1H_OFFSET? (0x1108 + (function * 0x8)) : (0x5108 + \
45 (0x191a + (port * 0x28) + (index * 0x4)) 45 (function * 0x8)))
46#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\ 46#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
47 (0x1900 + (port * 0x28)) 47 (IS_E1H_OFFSET? (0x31c0 + (function * 0x20)) : 0xffffffff)
48#define USTORM_HC_BTR_OFFSET(port)\ 48#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
49 (0x1954 + (port * 0xb8)) 49 (IS_E1H_OFFSET? 0xa000 : 0x1000)
50#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port)\ 50#define TSTORM_ASSERT_LIST_OFFSET(idx) \
51 (0x5408 + (port * 0x8)) 51 (IS_E1H_OFFSET? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
52#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\ 52#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
53 (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4)) 53 (IS_E1H_OFFSET? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) : \
54#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\ 54 (0x9c8 + (port * 0x2f8) + (client_id * 0x28)))
55 (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4)) 55#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
56#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\ 56 (IS_E1H_OFFSET? (0xb01a + ((function>>1) * 0x28) + ((function&1) \
57 (0x1400 + (port * 0x280) + (cpu_id * 0x28)) 57 * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \
58#define XSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000 58 0x4)))
59#define XSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10)) 59#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
60#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\ 60 (IS_E1H_OFFSET? (0xb000 + ((function>>1) * 0x28) + ((function&1) \
61 (0x141a + (port * 0x28) + (index * 0x4)) 61 * 0xa0)) : (0x1400 + (function * 0x28)))
62#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\ 62#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
63 (0x1400 + (port * 0x28)) 63 (IS_E1H_OFFSET? (0xb008 + ((function>>1) * 0x28) + ((function&1) \
64#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\ 64 * 0xa0)) : (0x1408 + (function * 0x28)))
65 (0x5408 + (port * 0x8)) 65#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
66#define XSTORM_HC_BTR_OFFSET(port)\ 66 (IS_E1H_OFFSET? (0x2b80 + (function * 0x8)) : (0x4b68 + \
67 (0x1454 + (port * 0x18)) 67 (function * 0x8)))
68#define XSTORM_SPQ_PAGE_BASE_OFFSET(port)\ 68#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
69 (0x5328 + (port * 0x18)) 69 (IS_E1H_OFFSET? (0x3000 + (function * 0x38)) : (0x1500 + \
70#define XSTORM_SPQ_PROD_OFFSET(port)\ 70 (function * 0x38)))
71 (0x5330 + (port * 0x18)) 71#define TSTORM_FUNCTION_MODE_OFFSET \
72#define XSTORM_STATS_FLAGS_OFFSET(port) (0x53f8 + (port * 0x8)) 72 (IS_E1H_OFFSET? 0x1ad0 : 0xffffffff)
73#define TSTORM_HC_BTR_OFFSET(port) \
74 (IS_E1H_OFFSET? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
75#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
76 (IS_E1H_OFFSET? (0x12c8 + (function * 0x80)) : (0x22c8 + \
77 (function * 0x80)))
78#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
79#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
80 (IS_E1H_OFFSET? (0x3008 + (function * 0x38)) : (0x1508 + \
81 (function * 0x38)))
82#define TSTORM_RX_PRODS_OFFSET(port, client_id) \
83 (IS_E1H_OFFSET? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) : \
84 (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))
85#define TSTORM_STATS_FLAGS_OFFSET(function) \
86 (IS_E1H_OFFSET? (0x2c00 + (function * 0x8)) : (0x4b88 + \
87 (function * 0x8)))
88#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET? 0x3b30 : 0x1c20)
89#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET? 0xa040 : 0x2c10)
90#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET? 0x2440 : 0x1200)
91#define USTORM_ASSERT_LIST_INDEX_OFFSET \
92 (IS_E1H_OFFSET? 0x8000 : 0x1000)
93#define USTORM_ASSERT_LIST_OFFSET(idx) \
94 (IS_E1H_OFFSET? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
95#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
96 (IS_E1H_OFFSET? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \
97 (0x5450 + (port * 0x1c8) + (clientId * 0x18)))
98#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
99 (IS_E1H_OFFSET? (0x951a + ((function>>1) * 0x28) + ((function&1) \
100 * 0xa0) + (index * 0x4)) : (0x191a + (function * 0x28) + (index * \
101 0x4)))
102#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
103 (IS_E1H_OFFSET? (0x9500 + ((function>>1) * 0x28) + ((function&1) \
104 * 0xa0)) : (0x1900 + (function * 0x28)))
105#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
106 (IS_E1H_OFFSET? (0x9508 + ((function>>1) * 0x28) + ((function&1) \
107 * 0xa0)) : (0x1908 + (function * 0x28)))
108#define USTORM_FUNCTION_MODE_OFFSET \
109 (IS_E1H_OFFSET? 0x2448 : 0xffffffff)
110#define USTORM_HC_BTR_OFFSET(port) \
111 (IS_E1H_OFFSET? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8)))
112#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
113 (IS_E1H_OFFSET? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \
114 (0x5448 + (port * 0x1c8) + (clientId * 0x18)))
115#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
116 (IS_E1H_OFFSET? (0x2408 + (function * 0x8)) : (0x5408 + \
117 (function * 0x8)))
118#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
119 (IS_E1H_OFFSET? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
120 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
121 (index * 0x4)))
122#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
123 (IS_E1H_OFFSET? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
124 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
125 (index * 0x4)))
126#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
127 (IS_E1H_OFFSET? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
128 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
129#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
130 (IS_E1H_OFFSET? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
131 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
132#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
133 (IS_E1H_OFFSET? 0x9000 : 0x1000)
134#define XSTORM_ASSERT_LIST_OFFSET(idx) \
135 (IS_E1H_OFFSET? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
136#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
137 (IS_E1H_OFFSET? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))
138#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
139 (IS_E1H_OFFSET? (0xa01a + ((function>>1) * 0x28) + ((function&1) \
140 * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \
141 0x4)))
142#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
143 (IS_E1H_OFFSET? (0xa000 + ((function>>1) * 0x28) + ((function&1) \
144 * 0xa0)) : (0x1400 + (function * 0x28)))
145#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
146 (IS_E1H_OFFSET? (0xa008 + ((function>>1) * 0x28) + ((function&1) \
147 * 0xa0)) : (0x1408 + (function * 0x28)))
148#define XSTORM_E1HOV_OFFSET(function) \
149 (IS_E1H_OFFSET? (0x2ab8 + (function * 0x2)) : 0xffffffff)
150#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
151 (IS_E1H_OFFSET? (0x2418 + (function * 0x8)) : (0x3b70 + \
152 (function * 0x8)))
153#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
154 (IS_E1H_OFFSET? (0x2568 + (function * 0x70)) : (0x3c60 + \
155 (function * 0x70)))
156#define XSTORM_FUNCTION_MODE_OFFSET \
157 (IS_E1H_OFFSET? 0x2ac8 : 0xffffffff)
158#define XSTORM_HC_BTR_OFFSET(port) \
159 (IS_E1H_OFFSET? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
160#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
161 (IS_E1H_OFFSET? (0x2528 + (function * 0x70)) : (0x3c20 + \
162 (function * 0x70)))
163#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
164 (IS_E1H_OFFSET? (0x2000 + (function * 0x10)) : (0x3328 + \
165 (function * 0x10)))
166#define XSTORM_SPQ_PROD_OFFSET(function) \
167 (IS_E1H_OFFSET? (0x2008 + (function * 0x10)) : (0x3330 + \
168 (function * 0x10)))
169#define XSTORM_STATS_FLAGS_OFFSET(function) \
170 (IS_E1H_OFFSET? (0x23d8 + (function * 0x8)) : (0x3b60 + \
171 (function * 0x8)))
73#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 172#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
74 173
75/** 174/**
76* This file defines HSI constatnts for the ETH flow 175* This file defines HSI constatnts for the ETH flow
77*/ 176*/
78 177#ifdef _EVEREST_MICROCODE
79/* hash types */ 178#include "microcode_constants.h"
80#define DEFAULT_HASH_TYPE 0 179#include "eth_rx_bd.h"
81#define IPV4_HASH_TYPE 1 180#include "eth_tx_bd.h"
82#define TCP_IPV4_HASH_TYPE 2 181#include "eth_rx_cqe.h"
83#define IPV6_HASH_TYPE 3 182#include "eth_rx_sge.h"
84#define TCP_IPV6_HASH_TYPE 4 183#include "eth_rx_cqe_next_page.h"
184#endif
185
186/* RSS hash types */
187#define DEFAULT_HASH_TYPE 0
188#define IPV4_HASH_TYPE 1
189#define TCP_IPV4_HASH_TYPE 2
190#define IPV6_HASH_TYPE 3
191#define TCP_IPV6_HASH_TYPE 4
192
193/* Ethernet Ring parmaters */
194#define X_ETH_LOCAL_RING_SIZE 13
195#define FIRST_BD_IN_PKT 0
196#define PARSE_BD_INDEX 1
197#define NUM_OF_ETH_BDS_IN_PAGE \
198 ((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8))
199
200
201/* Rx ring params */
202#define U_ETH_LOCAL_BD_RING_SIZE (16)
203#define U_ETH_LOCAL_SGE_RING_SIZE (12)
204#define U_ETH_SGL_SIZE (8)
205
206
207#define U_ETH_BDS_PER_PAGE_MASK \
208 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
209#define U_ETH_CQE_PER_PAGE_MASK \
210 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
211#define U_ETH_SGES_PER_PAGE_MASK \
212 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
213
214#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
215 (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
216
217
218#define TU_ETH_CQES_PER_PAGE \
219 (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
220#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
221#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
222
223#define U_ETH_UNDEFINED_Q 0xFF
85 224
86/* values of command IDs in the ramrod message */ 225/* values of command IDs in the ramrod message */
87#define RAMROD_CMD_ID_ETH_PORT_SETUP (80) 226#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
88#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85) 227#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
89#define RAMROD_CMD_ID_ETH_STAT_QUERY (90) 228#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
90#define RAMROD_CMD_ID_ETH_UPDATE (100) 229#define RAMROD_CMD_ID_ETH_UPDATE (100)
91#define RAMROD_CMD_ID_ETH_HALT (105) 230#define RAMROD_CMD_ID_ETH_HALT (105)
92#define RAMROD_CMD_ID_ETH_SET_MAC (110) 231#define RAMROD_CMD_ID_ETH_SET_MAC (110)
93#define RAMROD_CMD_ID_ETH_CFC_DEL (115) 232#define RAMROD_CMD_ID_ETH_CFC_DEL (115)
94#define RAMROD_CMD_ID_ETH_PORT_DEL (120) 233#define RAMROD_CMD_ID_ETH_PORT_DEL (120)
95#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125) 234#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
96 235
97 236
98/* command values for set mac command */ 237/* command values for set mac command */
99#define T_ETH_MAC_COMMAND_SET 0 238#define T_ETH_MAC_COMMAND_SET 0
100#define T_ETH_MAC_COMMAND_INVALIDATE 1 239#define T_ETH_MAC_COMMAND_INVALIDATE 1
240
241#define T_ETH_INDIRECTION_TABLE_SIZE 128
101 242
102#define T_ETH_INDIRECTION_TABLE_SIZE 128 243/*The CRC32 seed, that is used for the hash(reduction) multicast address */
244#define T_ETH_CRC32_HASH_SEED 0x00000000
103 245
104/* Maximal L2 clients supported */ 246/* Maximal L2 clients supported */
105#define ETH_MAX_RX_CLIENTS (18) 247#define ETH_MAX_RX_CLIENTS_E1 19
248#define ETH_MAX_RX_CLIENTS_E1H 25
249
250/* Maximal aggregation queues supported */
251#define ETH_MAX_AGGREGATION_QUEUES_E1 (32)
252#define ETH_MAX_AGGREGATION_QUEUES_E1H (64)
253
106 254
107/** 255/**
108* This file defines HSI constatnts common to all microcode flows 256* This file defines HSI constatnts common to all microcode flows
109*/ 257*/
110 258
111/* Connection types */ 259/* Connection types */
112#define ETH_CONNECTION_TYPE 0 260#define ETH_CONNECTION_TYPE 0
261#define TOE_CONNECTION_TYPE 1
262#define RDMA_CONNECTION_TYPE 2
263#define ISCSI_CONNECTION_TYPE 3
264#define FCOE_CONNECTION_TYPE 4
265#define RESERVED_CONNECTION_TYPE_0 5
266#define RESERVED_CONNECTION_TYPE_1 6
267#define RESERVED_CONNECTION_TYPE_2 7
268
113 269
114#define PROTOCOL_STATE_BIT_OFFSET 6 270#define PROTOCOL_STATE_BIT_OFFSET 6
115 271
116#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 272#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
273#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
274#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
275#define ISCSI_STATE \
276 (ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
277#define FCOE_STATE (FCOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
117 278
118/* microcode fixed page page size 4K (chains and ring segments) */ 279/* microcode fixed page page size 4K (chains and ring segments) */
119#define MC_PAGE_SIZE (4096) 280#define MC_PAGE_SIZE (4096)
120 281
121/* Host coalescing constants */
122 282
123/* IGU constants */ 283/* Host coalescing constants */
124#define IGU_PORT_BASE 0x0400
125
126#define IGU_ADDR_MSIX 0x0000
127#define IGU_ADDR_INT_ACK 0x0200
128#define IGU_ADDR_PROD_UPD 0x0201
129#define IGU_ADDR_ATTN_BITS_UPD 0x0202
130#define IGU_ADDR_ATTN_BITS_SET 0x0203
131#define IGU_ADDR_ATTN_BITS_CLR 0x0204
132#define IGU_ADDR_COALESCE_NOW 0x0205
133#define IGU_ADDR_SIMD_MASK 0x0206
134#define IGU_ADDR_SIMD_NOMASK 0x0207
135#define IGU_ADDR_MSI_CTL 0x0210
136#define IGU_ADDR_MSI_ADDR_LO 0x0211
137#define IGU_ADDR_MSI_ADDR_HI 0x0212
138#define IGU_ADDR_MSI_DATA 0x0213
139
140#define IGU_INT_ENABLE 0
141#define IGU_INT_DISABLE 1
142#define IGU_INT_NOP 2
143#define IGU_INT_NOP2 3
144 284
145/* index numbers */ 285/* index numbers */
146#define HC_USTORM_DEF_SB_NUM_INDICES 4 286#define HC_USTORM_DEF_SB_NUM_INDICES 4
147#define HC_CSTORM_DEF_SB_NUM_INDICES 8 287#define HC_CSTORM_DEF_SB_NUM_INDICES 8
148#define HC_XSTORM_DEF_SB_NUM_INDICES 4 288#define HC_XSTORM_DEF_SB_NUM_INDICES 4
149#define HC_TSTORM_DEF_SB_NUM_INDICES 4 289#define HC_TSTORM_DEF_SB_NUM_INDICES 4
150#define HC_USTORM_SB_NUM_INDICES 4 290#define HC_USTORM_SB_NUM_INDICES 4
151#define HC_CSTORM_SB_NUM_INDICES 4 291#define HC_CSTORM_SB_NUM_INDICES 4
152 292
153/* index values - which counterto update */ 293/* index values - which counterto update */
154 294
155#define HC_INDEX_U_ETH_RX_CQ_CONS 1 295#define HC_INDEX_U_TOE_RX_CQ_CONS 0
296#define HC_INDEX_U_ETH_RX_CQ_CONS 1
297#define HC_INDEX_U_ETH_RX_BD_CONS 2
298#define HC_INDEX_U_FCOE_EQ_CONS 3
299
300#define HC_INDEX_C_TOE_TX_CQ_CONS 0
301#define HC_INDEX_C_ETH_TX_CQ_CONS 1
302#define HC_INDEX_C_ISCSI_EQ_CONS 2
303
304#define HC_INDEX_DEF_X_SPQ_CONS 0
156 305
157#define HC_INDEX_C_ETH_TX_CQ_CONS 1 306#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
307#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
308#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
309#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
310#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
311#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
158 312
159#define HC_INDEX_DEF_X_SPQ_CONS 0 313#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
314#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
315#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
316#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
160 317
161#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
162#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
163 318
164/* used by the driver to get the SB offset */ 319/* used by the driver to get the SB offset */
165#define USTORM_ID 0 320#define USTORM_ID 0
166#define CSTORM_ID 1 321#define CSTORM_ID 1
167#define XSTORM_ID 2 322#define XSTORM_ID 2
168#define TSTORM_ID 3 323#define TSTORM_ID 3
169#define ATTENTION_ID 4 324#define ATTENTION_ID 4
170 325
171/* max number of slow path commands per port */ 326/* max number of slow path commands per port */
172#define MAX_RAMRODS_PER_PORT (8) 327#define MAX_RAMRODS_PER_PORT (8)
173 328
174/* values for RX ETH CQE type field */ 329/* values for RX ETH CQE type field */
175#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0) 330#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
176#define RX_ETH_CQE_TYPE_ETH_RAMROD (1) 331#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
177 332
178/* MAC address list size */ 333
179#define T_MAC_ADDRESS_LIST_SIZE (96) 334/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
180 335#define EMULATION_FREQUENCY_FACTOR (1600)
336#define FPGA_FREQUENCY_FACTOR (100)
337
338#define TIMERS_TICK_SIZE_CHIP (1e-3)
339#define TIMERS_TICK_SIZE_EMUL \
340 ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
341#define TIMERS_TICK_SIZE_FPGA \
342 ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
343
344#define TSEMI_CLK1_RESUL_CHIP (1e-3)
345#define TSEMI_CLK1_RESUL_EMUL \
346 ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
347#define TSEMI_CLK1_RESUL_FPGA \
348 ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
349
350#define USEMI_CLK1_RESUL_CHIP \
351 (TIMERS_TICK_SIZE_CHIP)
352#define USEMI_CLK1_RESUL_EMUL \
353 (TIMERS_TICK_SIZE_EMUL)
354#define USEMI_CLK1_RESUL_FPGA \
355 (TIMERS_TICK_SIZE_FPGA)
356
357#define XSEMI_CLK1_RESUL_CHIP (1e-3)
358#define XSEMI_CLK1_RESUL_EMUL \
359 ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
360#define XSEMI_CLK1_RESUL_FPGA \
361 ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
362
363#define XSEMI_CLK2_RESUL_CHIP (1e-6)
364#define XSEMI_CLK2_RESUL_EMUL \
365 ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
366#define XSEMI_CLK2_RESUL_FPGA \
367 ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
368
369#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
370#define SDM_TIMER_TICK_RESUL_EMUL \
371 ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
372#define SDM_TIMER_TICK_RESUL_FPGA \
373 ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
374
375
376/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
181#define XSTORM_IP_ID_ROLL_HALF 0x8000 377#define XSTORM_IP_ID_ROLL_HALF 0x8000
182#define XSTORM_IP_ID_ROLL_ALL 0 378#define XSTORM_IP_ID_ROLL_ALL 0
183 379
184#define FW_LOG_LIST_SIZE (50) 380#define FW_LOG_LIST_SIZE (50)
381
382#define NUM_OF_PROTOCOLS 4
383#define MAX_COS_NUMBER 16
384#define MAX_T_STAT_COUNTER_ID 18
385#define MAX_X_STAT_COUNTER_ID 18
185 386
186#define NUM_OF_PROTOCOLS 4 387#define UNKNOWN_ADDRESS 0
187#define MAX_COS_NUMBER 16 388#define UNICAST_ADDRESS 1
188#define MAX_T_STAT_COUNTER_ID 18 389#define MULTICAST_ADDRESS 2
390#define BROADCAST_ADDRESS 3
189 391
190#define T_FAIR 1 392#define SINGLE_FUNCTION 0
191#define FAIR_MEM 2 393#define MULTI_FUNCTION 1
192#define RS_PERIODIC_TIMEOUT_IN_SDM_TICS 25
193 394
194#define UNKNOWN_ADDRESS 0 395#define IP_V4 0
195#define UNICAST_ADDRESS 1 396#define IP_V6 1
196#define MULTICAST_ADDRESS 2
197#define BROADCAST_ADDRESS 3
198 397
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
index b21075ccb52e..d3e8198d7dba 100644
--- a/drivers/net/bnx2x_hsi.h
+++ b/drivers/net/bnx2x_hsi.h
@@ -132,6 +132,12 @@ struct shared_hw_cfg { /* NVRAM Offset */
132#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008 132#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
133#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009 133#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009
134#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a 134#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a
135#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1023G 0x0000000b
136#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1033G 0x0000000c
137#define SHARED_HW_CFG_BOARD_TYPE_BCM957711T1101 0x0000000d
138#define SHARED_HW_CFG_BOARD_TYPE_BCM957711ET1201 0x0000000e
139#define SHARED_HW_CFG_BOARD_TYPE_BCM957711A1133G 0x0000000f
140#define SHARED_HW_CFG_BOARD_TYPE_BCM957711EA1233G 0x00000010
135 141
136#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000 142#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
137#define SHARED_HW_CFG_BOARD_VER_SHIFT 16 143#define SHARED_HW_CFG_BOARD_VER_SHIFT 16
@@ -313,6 +319,7 @@ struct shared_feat_cfg { /* NVRAM Offset */
313 319
314 u32 config; /* 0x450 */ 320 u32 config; /* 0x450 */
315#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 321#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
322#define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
316 323
317}; 324};
318 325
@@ -502,28 +509,41 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
502}; 509};
503 510
504 511
505/***************************************************************************** 512/****************************************************************************
506 * Device Information * 513 * Device Information *
507 *****************************************************************************/ 514 ****************************************************************************/
508struct dev_info { /* size */ 515struct dev_info { /* size */
509 516
510 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 517 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
511 518
512 struct shared_hw_cfg shared_hw_config; /* 40 */ 519 struct shared_hw_cfg shared_hw_config; /* 40 */
513 520
514 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 521 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
515 522
516 struct shared_feat_cfg shared_feature_config; /* 4 */ 523 struct shared_feat_cfg shared_feature_config; /* 4 */
517 524
518 struct port_feat_cfg port_feature_config[PORT_MAX]; /* 116*2=232 */ 525 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
519 526
520}; 527};
521 528
522 529
523#define FUNC_0 0 530#define FUNC_0 0
524#define FUNC_1 1 531#define FUNC_1 1
532#define FUNC_2 2
533#define FUNC_3 3
534#define FUNC_4 4
535#define FUNC_5 5
536#define FUNC_6 6
537#define FUNC_7 7
525#define E1_FUNC_MAX 2 538#define E1_FUNC_MAX 2
526#define FUNC_MAX E1_FUNC_MAX 539#define E1H_FUNC_MAX 8
540
541#define VN_0 0
542#define VN_1 1
543#define VN_2 2
544#define VN_3 3
545#define E1VN_MAX 1
546#define E1HVN_MAX 4
527 547
528 548
529/* This value (in milliseconds) determines the frequency of the driver 549/* This value (in milliseconds) determines the frequency of the driver
@@ -619,7 +639,9 @@ struct drv_port_mb {
619#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000 639#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
620#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000 640#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
621 641
622 u32 reserved[3]; 642 u32 port_stx;
643
644 u32 reserved[2];
623 645
624}; 646};
625 647
@@ -642,6 +664,11 @@ struct drv_func_mb {
642#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 664#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
643#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 665#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
644 666
667#define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
668#define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
669#define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
670#define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
671
645#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 672#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
646 673
647 u32 drv_mb_param; 674 u32 drv_mb_param;
@@ -671,6 +698,11 @@ struct drv_func_mb {
671#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 698#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
672#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 699#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
673 700
701#define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
702#define FW_MSG_CODE_LIC_RESPONSE 0xff020000
703#define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
704#define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
705
674#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 706#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
675 707
676 u32 fw_mb_param; 708 u32 fw_mb_param;
@@ -696,7 +728,13 @@ struct drv_func_mb {
696 u32 iscsi_boot_signature; 728 u32 iscsi_boot_signature;
697 u32 iscsi_boot_block_offset; 729 u32 iscsi_boot_block_offset;
698 730
699 u32 reserved[3]; 731 u32 drv_status;
732#define DRV_STATUS_PMF 0x00000001
733
734 u32 virt_mac_upper;
735#define VIRT_MAC_SIGN_MASK 0xffff0000
736#define VIRT_MAC_SIGNATURE 0x564d0000
737 u32 virt_mac_lower;
700 738
701}; 739};
702 740
@@ -713,6 +751,92 @@ struct mgmtfw_state {
713 751
714 752
715/**************************************************************************** 753/****************************************************************************
754 * Multi-Function configuration *
755 ****************************************************************************/
756struct shared_mf_cfg {
757
758 u32 clp_mb;
759#define SHARED_MF_CLP_SET_DEFAULT 0x00000000
760 /* set by CLP */
761#define SHARED_MF_CLP_EXIT 0x00000001
762 /* set by MCP */
763#define SHARED_MF_CLP_EXIT_DONE 0x00010000
764
765};
766
767struct port_mf_cfg {
768
769 u32 dynamic_cfg; /* device control channel */
770#define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
771#define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
772#define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
773#define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
774
775 u32 reserved[3];
776
777};
778
779struct func_mf_cfg {
780
781 u32 config;
782 /* E/R/I/D */
783 /* function 0 of each port cannot be hidden */
784#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
785
786#define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
787#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
788#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
789#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
790#define FUNC_MF_CFG_PROTOCOL_DEFAULT\
791 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
792
793#define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
794
795 /* PRI */
796 /* 0 - low priority, 3 - high priority */
797#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
798#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
799#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
800
801 /* MINBW, MAXBW */
802 /* value range - 0..100, increments in 100Mbps */
803#define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
804#define FUNC_MF_CFG_MIN_BW_SHIFT 16
805#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
806#define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
807#define FUNC_MF_CFG_MAX_BW_SHIFT 24
808#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
809
810 u32 mac_upper; /* MAC */
811#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
812#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
813#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
814 u32 mac_lower;
815#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
816
817 u32 e1hov_tag; /* VNI */
818#define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
819#define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
820#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
821
822 u32 reserved[2];
823
824};
825
826struct mf_cfg {
827
828 struct shared_mf_cfg shared_mf_config;
829 struct port_mf_cfg port_mf_config[PORT_MAX];
830#if defined(b710)
831 struct func_mf_cfg func_mf_config[E1_FUNC_MAX];
832#else
833 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
834#endif
835
836};
837
838
839/****************************************************************************
716 * Shared Memory Region * 840 * Shared Memory Region *
717 ****************************************************************************/ 841 ****************************************************************************/
718struct shmem_region { /* SharedMem Offset (size) */ 842struct shmem_region { /* SharedMem Offset (size) */
@@ -747,14 +871,349 @@ struct shmem_region { /* SharedMem Offset (size) */
747 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 871 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
748 872
749 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 873 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
750 struct drv_func_mb func_mb[FUNC_MAX]; /* 0x684 (44*2=0x58) */ 874 struct drv_func_mb func_mb[E1H_FUNC_MAX];
875
876 struct mf_cfg mf_cfg;
751 877
752}; /* 0x6dc */ 878}; /* 0x6dc */
753 879
754 880
881struct emac_stats {
882 u32 rx_stat_ifhcinoctets;
883 u32 rx_stat_ifhcinbadoctets;
884 u32 rx_stat_etherstatsfragments;
885 u32 rx_stat_ifhcinucastpkts;
886 u32 rx_stat_ifhcinmulticastpkts;
887 u32 rx_stat_ifhcinbroadcastpkts;
888 u32 rx_stat_dot3statsfcserrors;
889 u32 rx_stat_dot3statsalignmenterrors;
890 u32 rx_stat_dot3statscarriersenseerrors;
891 u32 rx_stat_xonpauseframesreceived;
892 u32 rx_stat_xoffpauseframesreceived;
893 u32 rx_stat_maccontrolframesreceived;
894 u32 rx_stat_xoffstateentered;
895 u32 rx_stat_dot3statsframestoolong;
896 u32 rx_stat_etherstatsjabbers;
897 u32 rx_stat_etherstatsundersizepkts;
898 u32 rx_stat_etherstatspkts64octets;
899 u32 rx_stat_etherstatspkts65octetsto127octets;
900 u32 rx_stat_etherstatspkts128octetsto255octets;
901 u32 rx_stat_etherstatspkts256octetsto511octets;
902 u32 rx_stat_etherstatspkts512octetsto1023octets;
903 u32 rx_stat_etherstatspkts1024octetsto1522octets;
904 u32 rx_stat_etherstatspktsover1522octets;
905
906 u32 rx_stat_falsecarriererrors;
907
908 u32 tx_stat_ifhcoutoctets;
909 u32 tx_stat_ifhcoutbadoctets;
910 u32 tx_stat_etherstatscollisions;
911 u32 tx_stat_outxonsent;
912 u32 tx_stat_outxoffsent;
913 u32 tx_stat_flowcontroldone;
914 u32 tx_stat_dot3statssinglecollisionframes;
915 u32 tx_stat_dot3statsmultiplecollisionframes;
916 u32 tx_stat_dot3statsdeferredtransmissions;
917 u32 tx_stat_dot3statsexcessivecollisions;
918 u32 tx_stat_dot3statslatecollisions;
919 u32 tx_stat_ifhcoutucastpkts;
920 u32 tx_stat_ifhcoutmulticastpkts;
921 u32 tx_stat_ifhcoutbroadcastpkts;
922 u32 tx_stat_etherstatspkts64octets;
923 u32 tx_stat_etherstatspkts65octetsto127octets;
924 u32 tx_stat_etherstatspkts128octetsto255octets;
925 u32 tx_stat_etherstatspkts256octetsto511octets;
926 u32 tx_stat_etherstatspkts512octetsto1023octets;
927 u32 tx_stat_etherstatspkts1024octetsto1522octets;
928 u32 tx_stat_etherstatspktsover1522octets;
929 u32 tx_stat_dot3statsinternalmactransmiterrors;
930};
931
932
933struct bmac_stats {
934 u32 tx_stat_gtpkt_lo;
935 u32 tx_stat_gtpkt_hi;
936 u32 tx_stat_gtxpf_lo;
937 u32 tx_stat_gtxpf_hi;
938 u32 tx_stat_gtfcs_lo;
939 u32 tx_stat_gtfcs_hi;
940 u32 tx_stat_gtmca_lo;
941 u32 tx_stat_gtmca_hi;
942 u32 tx_stat_gtbca_lo;
943 u32 tx_stat_gtbca_hi;
944 u32 tx_stat_gtfrg_lo;
945 u32 tx_stat_gtfrg_hi;
946 u32 tx_stat_gtovr_lo;
947 u32 tx_stat_gtovr_hi;
948 u32 tx_stat_gt64_lo;
949 u32 tx_stat_gt64_hi;
950 u32 tx_stat_gt127_lo;
951 u32 tx_stat_gt127_hi;
952 u32 tx_stat_gt255_lo;
953 u32 tx_stat_gt255_hi;
954 u32 tx_stat_gt511_lo;
955 u32 tx_stat_gt511_hi;
956 u32 tx_stat_gt1023_lo;
957 u32 tx_stat_gt1023_hi;
958 u32 tx_stat_gt1518_lo;
959 u32 tx_stat_gt1518_hi;
960 u32 tx_stat_gt2047_lo;
961 u32 tx_stat_gt2047_hi;
962 u32 tx_stat_gt4095_lo;
963 u32 tx_stat_gt4095_hi;
964 u32 tx_stat_gt9216_lo;
965 u32 tx_stat_gt9216_hi;
966 u32 tx_stat_gt16383_lo;
967 u32 tx_stat_gt16383_hi;
968 u32 tx_stat_gtmax_lo;
969 u32 tx_stat_gtmax_hi;
970 u32 tx_stat_gtufl_lo;
971 u32 tx_stat_gtufl_hi;
972 u32 tx_stat_gterr_lo;
973 u32 tx_stat_gterr_hi;
974 u32 tx_stat_gtbyt_lo;
975 u32 tx_stat_gtbyt_hi;
976
977 u32 rx_stat_gr64_lo;
978 u32 rx_stat_gr64_hi;
979 u32 rx_stat_gr127_lo;
980 u32 rx_stat_gr127_hi;
981 u32 rx_stat_gr255_lo;
982 u32 rx_stat_gr255_hi;
983 u32 rx_stat_gr511_lo;
984 u32 rx_stat_gr511_hi;
985 u32 rx_stat_gr1023_lo;
986 u32 rx_stat_gr1023_hi;
987 u32 rx_stat_gr1518_lo;
988 u32 rx_stat_gr1518_hi;
989 u32 rx_stat_gr2047_lo;
990 u32 rx_stat_gr2047_hi;
991 u32 rx_stat_gr4095_lo;
992 u32 rx_stat_gr4095_hi;
993 u32 rx_stat_gr9216_lo;
994 u32 rx_stat_gr9216_hi;
995 u32 rx_stat_gr16383_lo;
996 u32 rx_stat_gr16383_hi;
997 u32 rx_stat_grmax_lo;
998 u32 rx_stat_grmax_hi;
999 u32 rx_stat_grpkt_lo;
1000 u32 rx_stat_grpkt_hi;
1001 u32 rx_stat_grfcs_lo;
1002 u32 rx_stat_grfcs_hi;
1003 u32 rx_stat_grmca_lo;
1004 u32 rx_stat_grmca_hi;
1005 u32 rx_stat_grbca_lo;
1006 u32 rx_stat_grbca_hi;
1007 u32 rx_stat_grxcf_lo;
1008 u32 rx_stat_grxcf_hi;
1009 u32 rx_stat_grxpf_lo;
1010 u32 rx_stat_grxpf_hi;
1011 u32 rx_stat_grxuo_lo;
1012 u32 rx_stat_grxuo_hi;
1013 u32 rx_stat_grjbr_lo;
1014 u32 rx_stat_grjbr_hi;
1015 u32 rx_stat_grovr_lo;
1016 u32 rx_stat_grovr_hi;
1017 u32 rx_stat_grflr_lo;
1018 u32 rx_stat_grflr_hi;
1019 u32 rx_stat_grmeg_lo;
1020 u32 rx_stat_grmeg_hi;
1021 u32 rx_stat_grmeb_lo;
1022 u32 rx_stat_grmeb_hi;
1023 u32 rx_stat_grbyt_lo;
1024 u32 rx_stat_grbyt_hi;
1025 u32 rx_stat_grund_lo;
1026 u32 rx_stat_grund_hi;
1027 u32 rx_stat_grfrg_lo;
1028 u32 rx_stat_grfrg_hi;
1029 u32 rx_stat_grerb_lo;
1030 u32 rx_stat_grerb_hi;
1031 u32 rx_stat_grfre_lo;
1032 u32 rx_stat_grfre_hi;
1033 u32 rx_stat_gripj_lo;
1034 u32 rx_stat_gripj_hi;
1035};
1036
1037
1038union mac_stats {
1039 struct emac_stats emac_stats;
1040 struct bmac_stats bmac_stats;
1041};
1042
1043
1044struct mac_stx {
1045 /* in_bad_octets */
1046 u32 rx_stat_ifhcinbadoctets_hi;
1047 u32 rx_stat_ifhcinbadoctets_lo;
1048
1049 /* out_bad_octets */
1050 u32 tx_stat_ifhcoutbadoctets_hi;
1051 u32 tx_stat_ifhcoutbadoctets_lo;
1052
1053 /* crc_receive_errors */
1054 u32 rx_stat_dot3statsfcserrors_hi;
1055 u32 rx_stat_dot3statsfcserrors_lo;
1056 /* alignment_errors */
1057 u32 rx_stat_dot3statsalignmenterrors_hi;
1058 u32 rx_stat_dot3statsalignmenterrors_lo;
1059 /* carrier_sense_errors */
1060 u32 rx_stat_dot3statscarriersenseerrors_hi;
1061 u32 rx_stat_dot3statscarriersenseerrors_lo;
1062 /* false_carrier_detections */
1063 u32 rx_stat_falsecarriererrors_hi;
1064 u32 rx_stat_falsecarriererrors_lo;
1065
1066 /* runt_packets_received */
1067 u32 rx_stat_etherstatsundersizepkts_hi;
1068 u32 rx_stat_etherstatsundersizepkts_lo;
1069 /* jabber_packets_received */
1070 u32 rx_stat_dot3statsframestoolong_hi;
1071 u32 rx_stat_dot3statsframestoolong_lo;
1072
1073 /* error_runt_packets_received */
1074 u32 rx_stat_etherstatsfragments_hi;
1075 u32 rx_stat_etherstatsfragments_lo;
1076 /* error_jabber_packets_received */
1077 u32 rx_stat_etherstatsjabbers_hi;
1078 u32 rx_stat_etherstatsjabbers_lo;
1079
1080 /* control_frames_received */
1081 u32 rx_stat_maccontrolframesreceived_hi;
1082 u32 rx_stat_maccontrolframesreceived_lo;
1083 u32 rx_stat_bmac_xpf_hi;
1084 u32 rx_stat_bmac_xpf_lo;
1085 u32 rx_stat_bmac_xcf_hi;
1086 u32 rx_stat_bmac_xcf_lo;
1087
1088 /* xoff_state_entered */
1089 u32 rx_stat_xoffstateentered_hi;
1090 u32 rx_stat_xoffstateentered_lo;
1091 /* pause_xon_frames_received */
1092 u32 rx_stat_xonpauseframesreceived_hi;
1093 u32 rx_stat_xonpauseframesreceived_lo;
1094 /* pause_xoff_frames_received */
1095 u32 rx_stat_xoffpauseframesreceived_hi;
1096 u32 rx_stat_xoffpauseframesreceived_lo;
1097 /* pause_xon_frames_transmitted */
1098 u32 tx_stat_outxonsent_hi;
1099 u32 tx_stat_outxonsent_lo;
1100 /* pause_xoff_frames_transmitted */
1101 u32 tx_stat_outxoffsent_hi;
1102 u32 tx_stat_outxoffsent_lo;
1103 /* flow_control_done */
1104 u32 tx_stat_flowcontroldone_hi;
1105 u32 tx_stat_flowcontroldone_lo;
1106
1107 /* ether_stats_collisions */
1108 u32 tx_stat_etherstatscollisions_hi;
1109 u32 tx_stat_etherstatscollisions_lo;
1110 /* single_collision_transmit_frames */
1111 u32 tx_stat_dot3statssinglecollisionframes_hi;
1112 u32 tx_stat_dot3statssinglecollisionframes_lo;
1113 /* multiple_collision_transmit_frames */
1114 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
1115 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
1116 /* deferred_transmissions */
1117 u32 tx_stat_dot3statsdeferredtransmissions_hi;
1118 u32 tx_stat_dot3statsdeferredtransmissions_lo;
1119 /* excessive_collision_frames */
1120 u32 tx_stat_dot3statsexcessivecollisions_hi;
1121 u32 tx_stat_dot3statsexcessivecollisions_lo;
1122 /* late_collision_frames */
1123 u32 tx_stat_dot3statslatecollisions_hi;
1124 u32 tx_stat_dot3statslatecollisions_lo;
1125
1126 /* frames_transmitted_64_bytes */
1127 u32 tx_stat_etherstatspkts64octets_hi;
1128 u32 tx_stat_etherstatspkts64octets_lo;
1129 /* frames_transmitted_65_127_bytes */
1130 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
1131 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
1132 /* frames_transmitted_128_255_bytes */
1133 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
1134 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
1135 /* frames_transmitted_256_511_bytes */
1136 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
1137 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
1138 /* frames_transmitted_512_1023_bytes */
1139 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
1140 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
1141 /* frames_transmitted_1024_1522_bytes */
1142 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
1143 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
1144 /* frames_transmitted_1523_9022_bytes */
1145 u32 tx_stat_etherstatspktsover1522octets_hi;
1146 u32 tx_stat_etherstatspktsover1522octets_lo;
1147 u32 tx_stat_bmac_2047_hi;
1148 u32 tx_stat_bmac_2047_lo;
1149 u32 tx_stat_bmac_4095_hi;
1150 u32 tx_stat_bmac_4095_lo;
1151 u32 tx_stat_bmac_9216_hi;
1152 u32 tx_stat_bmac_9216_lo;
1153 u32 tx_stat_bmac_16383_hi;
1154 u32 tx_stat_bmac_16383_lo;
1155
1156 /* internal_mac_transmit_errors */
1157 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
1158 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
1159
1160 /* if_out_discards */
1161 u32 tx_stat_bmac_ufl_hi;
1162 u32 tx_stat_bmac_ufl_lo;
1163};
1164
1165
1166#define MAC_STX_IDX_MAX 2
1167
1168struct host_port_stats {
1169 u32 host_port_stats_start;
1170
1171 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1172
1173 u32 brb_drop_hi;
1174 u32 brb_drop_lo;
1175
1176 u32 host_port_stats_end;
1177};
1178
1179
1180struct host_func_stats {
1181 u32 host_func_stats_start;
1182
1183 u32 total_bytes_received_hi;
1184 u32 total_bytes_received_lo;
1185
1186 u32 total_bytes_transmitted_hi;
1187 u32 total_bytes_transmitted_lo;
1188
1189 u32 total_unicast_packets_received_hi;
1190 u32 total_unicast_packets_received_lo;
1191
1192 u32 total_multicast_packets_received_hi;
1193 u32 total_multicast_packets_received_lo;
1194
1195 u32 total_broadcast_packets_received_hi;
1196 u32 total_broadcast_packets_received_lo;
1197
1198 u32 total_unicast_packets_transmitted_hi;
1199 u32 total_unicast_packets_transmitted_lo;
1200
1201 u32 total_multicast_packets_transmitted_hi;
1202 u32 total_multicast_packets_transmitted_lo;
1203
1204 u32 total_broadcast_packets_transmitted_hi;
1205 u32 total_broadcast_packets_transmitted_lo;
1206
1207 u32 valid_bytes_received_hi;
1208 u32 valid_bytes_received_lo;
1209
1210 u32 host_func_stats_end;
1211};
1212
1213
755#define BCM_5710_FW_MAJOR_VERSION 4 1214#define BCM_5710_FW_MAJOR_VERSION 4
756#define BCM_5710_FW_MINOR_VERSION 0 1215#define BCM_5710_FW_MINOR_VERSION 5
757#define BCM_5710_FW_REVISION_VERSION 14 1216#define BCM_5710_FW_REVISION_VERSION 1
758#define BCM_5710_FW_COMPILE_FLAGS 1 1217#define BCM_5710_FW_COMPILE_FLAGS 1
759 1218
760 1219
@@ -793,7 +1252,7 @@ struct doorbell_hdr {
793}; 1252};
794 1253
795/* 1254/*
796 * doorbell message send to the chip 1255 * doorbell message sent to the chip
797 */ 1256 */
798struct doorbell { 1257struct doorbell {
799#if defined(__BIG_ENDIAN) 1258#if defined(__BIG_ENDIAN)
@@ -849,8 +1308,10 @@ struct parsing_flags {
849 u16 flags; 1308 u16 flags;
850#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 1309#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
851#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 1310#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
852#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS (0x3<<1) 1311#define PARSING_FLAGS_VLAN (0x1<<1)
853#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS_SHIFT 1 1312#define PARSING_FLAGS_VLAN_SHIFT 1
1313#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1314#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
854#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 1315#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
855#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 1316#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
856#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 1317#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
@@ -874,6 +1335,12 @@ struct parsing_flags {
874}; 1335};
875 1336
876 1337
1338struct regpair {
1339 u32 lo;
1340 u32 hi;
1341};
1342
1343
877/* 1344/*
878 * dmae command structure 1345 * dmae command structure
879 */ 1346 */
@@ -901,8 +1368,10 @@ struct dmae_command {
901#define DMAE_COMMAND_SRC_RESET_SHIFT 13 1368#define DMAE_COMMAND_SRC_RESET_SHIFT 13
902#define DMAE_COMMAND_DST_RESET (0x1<<14) 1369#define DMAE_COMMAND_DST_RESET (0x1<<14)
903#define DMAE_COMMAND_DST_RESET_SHIFT 14 1370#define DMAE_COMMAND_DST_RESET_SHIFT 14
904#define DMAE_COMMAND_RESERVED0 (0x1FFFF<<15) 1371#define DMAE_COMMAND_E1HVN (0x3<<15)
905#define DMAE_COMMAND_RESERVED0_SHIFT 15 1372#define DMAE_COMMAND_E1HVN_SHIFT 15
1373#define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1374#define DMAE_COMMAND_RESERVED0_SHIFT 17
906 u32 src_addr_lo; 1375 u32 src_addr_lo;
907 u32 src_addr_hi; 1376 u32 src_addr_hi;
908 u32 dst_addr_lo; 1377 u32 dst_addr_lo;
@@ -952,72 +1421,107 @@ struct double_regpair {
952 1421
953 1422
954/* 1423/*
955 * The eth Rx Buffer Descriptor 1424 * The eth storm context of Ustorm (configuration part)
956 */
957struct eth_rx_bd {
958 u32 addr_lo;
959 u32 addr_hi;
960};
961
962/*
963 * The eth storm context of Ustorm
964 */ 1425 */
965struct ustorm_eth_st_context { 1426struct ustorm_eth_st_context_config {
966#if defined(__BIG_ENDIAN) 1427#if defined(__BIG_ENDIAN)
967 u8 sb_index_number; 1428 u8 flags;
1429#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1430#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1431#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1432#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1433#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1434#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1435#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1436#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1437#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1438#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
968 u8 status_block_id; 1439 u8 status_block_id;
969 u8 __local_rx_bd_cons; 1440 u8 clientId;
970 u8 __local_rx_bd_prod; 1441 u8 sb_index_numbers;
1442#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1443#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1444#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1445#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
971#elif defined(__LITTLE_ENDIAN) 1446#elif defined(__LITTLE_ENDIAN)
972 u8 __local_rx_bd_prod; 1447 u8 sb_index_numbers;
973 u8 __local_rx_bd_cons; 1448#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1449#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1450#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1451#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1452 u8 clientId;
974 u8 status_block_id; 1453 u8 status_block_id;
975 u8 sb_index_number; 1454 u8 flags;
1455#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1456#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1457#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1458#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1459#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1460#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1461#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1462#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1463#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1464#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
976#endif 1465#endif
977#if defined(__BIG_ENDIAN) 1466#if defined(__BIG_ENDIAN)
978 u16 rcq_cons; 1467 u16 bd_buff_size;
979 u16 rx_bd_cons; 1468 u16 mc_alignment_size;
980#elif defined(__LITTLE_ENDIAN) 1469#elif defined(__LITTLE_ENDIAN)
981 u16 rx_bd_cons; 1470 u16 mc_alignment_size;
982 u16 rcq_cons; 1471 u16 bd_buff_size;
983#endif 1472#endif
984 u32 rx_bd_page_base_lo;
985 u32 rx_bd_page_base_hi;
986 u32 rcq_base_address_lo;
987 u32 rcq_base_address_hi;
988#if defined(__BIG_ENDIAN) 1473#if defined(__BIG_ENDIAN)
989 u16 __num_of_returned_cqes; 1474 u8 __local_sge_prod;
990 u8 num_rss; 1475 u8 __local_bd_prod;
991 u8 flags; 1476 u16 sge_buff_size;
992#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
993#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
994#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
995#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
996#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
997#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
998#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
999#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
1000#elif defined(__LITTLE_ENDIAN) 1477#elif defined(__LITTLE_ENDIAN)
1001 u8 flags; 1478 u16 sge_buff_size;
1002#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0) 1479 u8 __local_bd_prod;
1003#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0 1480 u8 __local_sge_prod;
1004#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
1005#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
1006#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
1007#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
1008#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
1009#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
1010 u8 num_rss;
1011 u16 __num_of_returned_cqes;
1012#endif 1481#endif
1013#if defined(__BIG_ENDIAN) 1482#if defined(__BIG_ENDIAN)
1014 u16 mc_alignment_size; 1483 u16 __bd_cons;
1015 u16 agg_threshold; 1484 u16 __sge_cons;
1016#elif defined(__LITTLE_ENDIAN) 1485#elif defined(__LITTLE_ENDIAN)
1017 u16 agg_threshold; 1486 u16 __sge_cons;
1018 u16 mc_alignment_size; 1487 u16 __bd_cons;
1019#endif 1488#endif
1489 u32 bd_page_base_lo;
1490 u32 bd_page_base_hi;
1491 u32 sge_page_base_lo;
1492 u32 sge_page_base_hi;
1493};
1494
1495/*
1496 * The eth Rx Buffer Descriptor
1497 */
1498struct eth_rx_bd {
1499 u32 addr_lo;
1500 u32 addr_hi;
1501};
1502
1503/*
1504 * The eth Rx SGE Descriptor
1505 */
1506struct eth_rx_sge {
1507 u32 addr_lo;
1508 u32 addr_hi;
1509};
1510
1511/*
1512 * Local BDs and SGEs rings (in ETH)
1513 */
1514struct eth_local_rx_rings {
1020 struct eth_rx_bd __local_bd_ring[16]; 1515 struct eth_rx_bd __local_bd_ring[16];
1516 struct eth_rx_sge __local_sge_ring[12];
1517};
1518
1519/*
1520 * The eth storm context of Ustorm
1521 */
1522struct ustorm_eth_st_context {
1523 struct ustorm_eth_st_context_config common;
1524 struct eth_local_rx_rings __rings;
1021}; 1525};
1022 1526
1023/* 1527/*
@@ -1088,9 +1592,9 @@ struct xstorm_eth_extra_ag_context_section {
1088#if defined(__BIG_ENDIAN) 1592#if defined(__BIG_ENDIAN)
1089 u16 __reserved3; 1593 u16 __reserved3;
1090 u8 __reserved2; 1594 u8 __reserved2;
1091 u8 __agg_misc7; 1595 u8 __da_only_cnt;
1092#elif defined(__LITTLE_ENDIAN) 1596#elif defined(__LITTLE_ENDIAN)
1093 u8 __agg_misc7; 1597 u8 __da_only_cnt;
1094 u8 __reserved2; 1598 u8 __reserved2;
1095 u16 __reserved3; 1599 u16 __reserved3;
1096#endif 1600#endif
@@ -1368,7 +1872,13 @@ struct timers_block_context {
1368 u32 __reserved_0; 1872 u32 __reserved_0;
1369 u32 __reserved_1; 1873 u32 __reserved_1;
1370 u32 __reserved_2; 1874 u32 __reserved_2;
1371 u32 __reserved_flags; 1875 u32 flags;
1876#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1877#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1878#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1879#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1880#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1881#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
1372}; 1882};
1373 1883
1374/* 1884/*
@@ -1478,11 +1988,19 @@ struct xstorm_eth_st_context {
1478 u32 tx_bd_page_base_hi; 1988 u32 tx_bd_page_base_hi;
1479#if defined(__BIG_ENDIAN) 1989#if defined(__BIG_ENDIAN)
1480 u16 tx_bd_cons; 1990 u16 tx_bd_cons;
1481 u8 __reserved0; 1991 u8 statistics_data;
1992#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1993#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1994#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1995#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1482 u8 __local_tx_bd_prod; 1996 u8 __local_tx_bd_prod;
1483#elif defined(__LITTLE_ENDIAN) 1997#elif defined(__LITTLE_ENDIAN)
1484 u8 __local_tx_bd_prod; 1998 u8 __local_tx_bd_prod;
1485 u8 __reserved0; 1999 u8 statistics_data;
2000#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
2001#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
2002#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
2003#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1486 u16 tx_bd_cons; 2004 u16 tx_bd_cons;
1487#endif 2005#endif
1488 u32 db_data_addr_lo; 2006 u32 db_data_addr_lo;
@@ -1559,7 +2077,7 @@ struct eth_tx_doorbell {
1559struct ustorm_def_status_block { 2077struct ustorm_def_status_block {
1560 u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES]; 2078 u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
1561 u16 status_block_index; 2079 u16 status_block_index;
1562 u8 reserved0; 2080 u8 func;
1563 u8 status_block_id; 2081 u8 status_block_id;
1564 u32 __flags; 2082 u32 __flags;
1565}; 2083};
@@ -1570,7 +2088,7 @@ struct ustorm_def_status_block {
1570struct cstorm_def_status_block { 2088struct cstorm_def_status_block {
1571 u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES]; 2089 u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
1572 u16 status_block_index; 2090 u16 status_block_index;
1573 u8 reserved0; 2091 u8 func;
1574 u8 status_block_id; 2092 u8 status_block_id;
1575 u32 __flags; 2093 u32 __flags;
1576}; 2094};
@@ -1581,7 +2099,7 @@ struct cstorm_def_status_block {
1581struct xstorm_def_status_block { 2099struct xstorm_def_status_block {
1582 u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES]; 2100 u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
1583 u16 status_block_index; 2101 u16 status_block_index;
1584 u8 reserved0; 2102 u8 func;
1585 u8 status_block_id; 2103 u8 status_block_id;
1586 u32 __flags; 2104 u32 __flags;
1587}; 2105};
@@ -1592,7 +2110,7 @@ struct xstorm_def_status_block {
1592struct tstorm_def_status_block { 2110struct tstorm_def_status_block {
1593 u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES]; 2111 u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
1594 u16 status_block_index; 2112 u16 status_block_index;
1595 u8 reserved0; 2113 u8 func;
1596 u8 status_block_id; 2114 u8 status_block_id;
1597 u32 __flags; 2115 u32 __flags;
1598}; 2116};
@@ -1615,7 +2133,7 @@ struct host_def_status_block {
1615struct ustorm_status_block { 2133struct ustorm_status_block {
1616 u16 index_values[HC_USTORM_SB_NUM_INDICES]; 2134 u16 index_values[HC_USTORM_SB_NUM_INDICES];
1617 u16 status_block_index; 2135 u16 status_block_index;
1618 u8 reserved0; 2136 u8 func;
1619 u8 status_block_id; 2137 u8 status_block_id;
1620 u32 __flags; 2138 u32 __flags;
1621}; 2139};
@@ -1626,7 +2144,7 @@ struct ustorm_status_block {
1626struct cstorm_status_block { 2144struct cstorm_status_block {
1627 u16 index_values[HC_CSTORM_SB_NUM_INDICES]; 2145 u16 index_values[HC_CSTORM_SB_NUM_INDICES];
1628 u16 status_block_index; 2146 u16 status_block_index;
1629 u8 reserved0; 2147 u8 func;
1630 u8 status_block_id; 2148 u8 status_block_id;
1631 u32 __flags; 2149 u32 __flags;
1632}; 2150};
@@ -1664,20 +2182,21 @@ struct eth_dynamic_hc_config {
1664 * regular eth FP CQE parameters struct 2182 * regular eth FP CQE parameters struct
1665 */ 2183 */
1666struct eth_fast_path_rx_cqe { 2184struct eth_fast_path_rx_cqe {
1667 u8 type; 2185 u8 type_error_flags;
1668 u8 error_type_flags; 2186#define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
1669#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<0) 2187#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
1670#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 0 2188#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
1671#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<1) 2189#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
1672#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 1 2190#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
1673#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<2) 2191#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
1674#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 2 2192#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
1675#define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<3) 2193#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
1676#define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 3 2194#define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
1677#define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<4) 2195#define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
1678#define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 4 2196#define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
1679#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x7<<5) 2197#define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
1680#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 5 2198#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2199#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
1681 u8 status_flags; 2200 u8 status_flags;
1682#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 2201#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
1683#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 2202#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
@@ -1692,11 +2211,13 @@ struct eth_fast_path_rx_cqe {
1692#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 2211#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
1693#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 2212#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
1694 u8 placement_offset; 2213 u8 placement_offset;
2214 u8 queue_index;
1695 u32 rss_hash_result; 2215 u32 rss_hash_result;
1696 u16 vlan_tag; 2216 u16 vlan_tag;
1697 u16 pkt_len; 2217 u16 pkt_len;
1698 u16 queue_index; 2218 u16 len_on_bd;
1699 struct parsing_flags pars_flags; 2219 struct parsing_flags pars_flags;
2220 u16 sgl[8];
1700}; 2221};
1701 2222
1702 2223
@@ -1710,6 +2231,23 @@ struct eth_halt_ramrod_data {
1710 2231
1711 2232
1712/* 2233/*
2234 * The data for statistics query ramrod
2235 */
2236struct eth_query_ramrod_data {
2237#if defined(__BIG_ENDIAN)
2238 u8 reserved0;
2239 u8 collect_port_1b;
2240 u16 drv_counter;
2241#elif defined(__LITTLE_ENDIAN)
2242 u16 drv_counter;
2243 u8 collect_port_1b;
2244 u8 reserved0;
2245#endif
2246 u32 ctr_id_vector;
2247};
2248
2249
2250/*
1713 * Place holder for ramrods protocol specific data 2251 * Place holder for ramrods protocol specific data
1714 */ 2252 */
1715struct ramrod_data { 2253struct ramrod_data {
@@ -1739,15 +2277,20 @@ struct eth_rx_bd_next_page {
1739 * Eth Rx Cqe structure- general structure for ramrods 2277 * Eth Rx Cqe structure- general structure for ramrods
1740 */ 2278 */
1741struct common_ramrod_eth_rx_cqe { 2279struct common_ramrod_eth_rx_cqe {
1742 u8 type; 2280 u8 ramrod_type;
2281#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2282#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2283#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
2284#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
1743 u8 conn_type_3b; 2285 u8 conn_type_3b;
1744 u16 reserved; 2286 u16 reserved1;
1745 u32 conn_and_cmd_data; 2287 u32 conn_and_cmd_data;
1746#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 2288#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
1747#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 2289#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
1748#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 2290#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
1749#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 2291#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
1750 struct ramrod_data protocol_data; 2292 struct ramrod_data protocol_data;
2293 u32 reserved2[4];
1751}; 2294};
1752 2295
1753/* 2296/*
@@ -1756,8 +2299,7 @@ struct common_ramrod_eth_rx_cqe {
1756struct eth_rx_cqe_next_page { 2299struct eth_rx_cqe_next_page {
1757 u32 addr_lo; 2300 u32 addr_lo;
1758 u32 addr_hi; 2301 u32 addr_hi;
1759 u32 reserved0; 2302 u32 reserved[6];
1760 u32 reserved1;
1761}; 2303};
1762 2304
1763/* 2305/*
@@ -1787,11 +2329,6 @@ struct spe_hdr {
1787 u16 reserved; 2329 u16 reserved;
1788}; 2330};
1789 2331
1790struct regpair {
1791 u32 lo;
1792 u32 hi;
1793};
1794
1795/* 2332/*
1796 * ethernet slow path element 2333 * ethernet slow path element
1797 */ 2334 */
@@ -1802,6 +2339,7 @@ union eth_specific_data {
1802 struct eth_halt_ramrod_data halt_ramrod_data; 2339 struct eth_halt_ramrod_data halt_ramrod_data;
1803 struct regpair leading_cqe_addr; 2340 struct regpair leading_cqe_addr;
1804 struct regpair update_data_addr; 2341 struct regpair update_data_addr;
2342 struct eth_query_ramrod_data query_ramrod_data;
1805}; 2343};
1806 2344
1807/* 2345/*
@@ -1824,10 +2362,13 @@ struct eth_tx_db_data {
1824 2362
1825 2363
1826/* 2364/*
1827 * Common configuration parameters per port in Tstorm 2365 * Common configuration parameters per function in Tstorm
1828 */ 2366 */
1829struct tstorm_eth_function_common_config { 2367struct tstorm_eth_function_common_config {
1830 u32 config_flags; 2368#if defined(__BIG_ENDIAN)
2369 u8 leading_client_id;
2370 u8 rss_result_mask;
2371 u16 config_flags;
1831#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 2372#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
1832#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 2373#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
1833#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 2374#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
@@ -1840,17 +2381,32 @@ struct tstorm_eth_function_common_config {
1840#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4 2381#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
1841#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5) 2382#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
1842#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5 2383#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
1843#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3FFFFFF<<6) 2384#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
1844#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 6 2385#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
1845#if defined(__BIG_ENDIAN) 2386#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
1846 u16 __secondary_vlan_id; 2387#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
1847 u8 leading_client_id;
1848 u8 rss_result_mask;
1849#elif defined(__LITTLE_ENDIAN) 2388#elif defined(__LITTLE_ENDIAN)
2389 u16 config_flags;
2390#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2391#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2392#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2393#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2394#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2395#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2396#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2397#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2398#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
2399#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
2400#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
2401#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
2402#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
2403#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
2404#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
2405#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
1850 u8 rss_result_mask; 2406 u8 rss_result_mask;
1851 u8 leading_client_id; 2407 u8 leading_client_id;
1852 u16 __secondary_vlan_id;
1853#endif 2408#endif
2409 u16 vlan_id[2];
1854}; 2410};
1855 2411
1856/* 2412/*
@@ -1868,7 +2424,7 @@ struct eth_update_ramrod_data {
1868struct mac_configuration_hdr { 2424struct mac_configuration_hdr {
1869 u8 length_6b; 2425 u8 length_6b;
1870 u8 offset; 2426 u8 offset;
1871 u16 reserved0; 2427 u16 client_id;
1872 u32 reserved1; 2428 u32 reserved1;
1873}; 2429};
1874 2430
@@ -1925,15 +2481,55 @@ struct mac_configuration_cmd {
1925 2481
1926 2482
1927/* 2483/*
2484 * MAC address in list for ramrod
2485 */
2486struct mac_configuration_entry_e1h {
2487 u16 lsb_mac_addr;
2488 u16 middle_mac_addr;
2489 u16 msb_mac_addr;
2490 u16 vlan_id;
2491 u16 e1hov_id;
2492 u8 client_id;
2493 u8 flags;
2494#define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2495#define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2496#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2497#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2498#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2499#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2500#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2501#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2502};
2503
2504/*
2505 * MAC filtering configuration command
2506 */
2507struct mac_configuration_cmd_e1h {
2508 struct mac_configuration_hdr hdr;
2509 struct mac_configuration_entry_e1h config_table[32];
2510};
2511
2512
2513/*
2514 * approximate-match multicast filtering for E1H per function in Tstorm
2515 */
2516struct tstorm_eth_approximate_match_multicast_filtering {
2517 u32 mcast_add_hash_bit_array[8];
2518};
2519
2520
2521/*
1928 * Configuration parameters per client in Tstorm 2522 * Configuration parameters per client in Tstorm
1929 */ 2523 */
1930struct tstorm_eth_client_config { 2524struct tstorm_eth_client_config {
1931#if defined(__BIG_ENDIAN) 2525#if defined(__BIG_ENDIAN)
1932 u16 statistics_counter_id; 2526 u8 max_sges_for_packet;
2527 u8 statistics_counter_id;
1933 u16 mtu; 2528 u16 mtu;
1934#elif defined(__LITTLE_ENDIAN) 2529#elif defined(__LITTLE_ENDIAN)
1935 u16 mtu; 2530 u16 mtu;
1936 u16 statistics_counter_id; 2531 u8 statistics_counter_id;
2532 u8 max_sges_for_packet;
1937#endif 2533#endif
1938#if defined(__BIG_ENDIAN) 2534#if defined(__BIG_ENDIAN)
1939 u16 drop_flags; 2535 u16 drop_flags;
@@ -1941,42 +2537,42 @@ struct tstorm_eth_client_config {
1941#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0 2537#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
1942#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1) 2538#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
1943#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1 2539#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
1944#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2) 2540#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
1945#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2 2541#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
1946#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3) 2542#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
1947#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3 2543#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
1948#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4) 2544#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
1949#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4 2545#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
1950#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
1951#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
1952 u16 config_flags; 2546 u16 config_flags;
1953#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0) 2547#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
1954#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0 2548#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
1955#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1) 2549#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
1956#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1 2550#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
1957#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2) 2551#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
1958#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2 2552#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
2553#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
2554#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
1959#elif defined(__LITTLE_ENDIAN) 2555#elif defined(__LITTLE_ENDIAN)
1960 u16 config_flags; 2556 u16 config_flags;
1961#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0) 2557#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
1962#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0 2558#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
1963#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1) 2559#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
1964#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1 2560#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
1965#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2) 2561#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
1966#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2 2562#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
2563#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
2564#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
1967 u16 drop_flags; 2565 u16 drop_flags;
1968#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0) 2566#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
1969#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0 2567#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
1970#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1) 2568#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
1971#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1 2569#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
1972#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2) 2570#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
1973#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2 2571#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
1974#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3) 2572#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
1975#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3 2573#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
1976#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4) 2574#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
1977#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4 2575#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
1978#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
1979#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
1980#endif 2576#endif
1981}; 2577};
1982 2578
@@ -1992,103 +2588,119 @@ struct tstorm_eth_mac_filter_config {
1992 u32 bcast_drop_all; 2588 u32 bcast_drop_all;
1993 u32 bcast_accept_all; 2589 u32 bcast_accept_all;
1994 u32 strict_vlan; 2590 u32 strict_vlan;
1995 u32 __secondary_vlan_clients; 2591 u32 vlan_filter[2];
2592 u32 reserved;
1996}; 2593};
1997 2594
1998 2595
1999struct rate_shaping_per_protocol { 2596/*
2597 * Three RX producers for ETH
2598 */
2599struct tstorm_eth_rx_producers {
2000#if defined(__BIG_ENDIAN) 2600#if defined(__BIG_ENDIAN)
2001 u16 reserved0; 2601 u16 bd_prod;
2002 u16 protocol_rate; 2602 u16 cqe_prod;
2003#elif defined(__LITTLE_ENDIAN) 2603#elif defined(__LITTLE_ENDIAN)
2004 u16 protocol_rate; 2604 u16 cqe_prod;
2005 u16 reserved0; 2605 u16 bd_prod;
2006#endif 2606#endif
2007 u32 protocol_quota;
2008 s32 current_credit;
2009 u32 reserved;
2010};
2011
2012struct rate_shaping_vars {
2013 struct rate_shaping_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
2014 u32 pause_mask;
2015 u32 periodic_stop;
2016 u32 rs_periodic_timeout;
2017 u32 rs_threshold;
2018 u32 last_periodic_time;
2019 u32 reserved;
2020};
2021
2022struct fairness_per_protocol {
2023 u32 credit_delta;
2024 s32 fair_credit;
2025#if defined(__BIG_ENDIAN) 2607#if defined(__BIG_ENDIAN)
2026 u16 reserved0; 2608 u16 reserved;
2027 u8 state; 2609 u16 sge_prod;
2028 u8 weight;
2029#elif defined(__LITTLE_ENDIAN) 2610#elif defined(__LITTLE_ENDIAN)
2030 u8 weight; 2611 u16 sge_prod;
2031 u8 state; 2612 u16 reserved;
2032 u16 reserved0;
2033#endif 2613#endif
2034 u32 reserved1;
2035}; 2614};
2036 2615
2037struct fairness_vars {
2038 struct fairness_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
2039 u32 upper_bound;
2040 u32 port_rate;
2041 u32 pause_mask;
2042 u32 fair_threshold;
2043};
2044 2616
2045struct safc_struct { 2617/*
2046 u32 cur_pause_mask; 2618 * common flag to indicate existance of TPA.
2047 u32 expire_time; 2619 */
2620struct tstorm_eth_tpa_exist {
2048#if defined(__BIG_ENDIAN) 2621#if defined(__BIG_ENDIAN)
2049 u16 reserved0; 2622 u16 reserved1;
2050 u8 cur_cos_types; 2623 u8 reserved0;
2051 u8 safc_timeout_usec; 2624 u8 tpa_exist;
2052#elif defined(__LITTLE_ENDIAN) 2625#elif defined(__LITTLE_ENDIAN)
2053 u8 safc_timeout_usec; 2626 u8 tpa_exist;
2054 u8 cur_cos_types; 2627 u8 reserved0;
2055 u16 reserved0; 2628 u16 reserved1;
2056#endif 2629#endif
2057 u32 reserved1; 2630 u32 reserved2;
2058}; 2631};
2059 2632
2060struct demo_struct { 2633
2634/*
2635 * per-port SAFC demo variables
2636 */
2637struct cmng_flags_per_port {
2061 u8 con_number[NUM_OF_PROTOCOLS]; 2638 u8 con_number[NUM_OF_PROTOCOLS];
2062#if defined(__BIG_ENDIAN) 2639#if defined(__BIG_ENDIAN)
2063 u8 reserved1;
2064 u8 fairness_enable; 2640 u8 fairness_enable;
2065 u8 rate_shaping_enable; 2641 u8 rate_shaping_enable;
2066 u8 cmng_enable; 2642 u8 cmng_protocol_enable;
2643 u8 cmng_vn_enable;
2067#elif defined(__LITTLE_ENDIAN) 2644#elif defined(__LITTLE_ENDIAN)
2068 u8 cmng_enable; 2645 u8 cmng_vn_enable;
2646 u8 cmng_protocol_enable;
2069 u8 rate_shaping_enable; 2647 u8 rate_shaping_enable;
2070 u8 fairness_enable; 2648 u8 fairness_enable;
2071 u8 reserved1;
2072#endif 2649#endif
2073}; 2650};
2074 2651
2075struct cmng_struct { 2652
2076 struct rate_shaping_vars rs_vars; 2653/*
2077 struct fairness_vars fair_vars; 2654 * per-port rate shaping variables
2078 struct safc_struct safc_vars; 2655 */
2079 struct demo_struct demo_vars; 2656struct rate_shaping_vars_per_port {
2657 u32 rs_periodic_timeout;
2658 u32 rs_threshold;
2080}; 2659};
2081 2660
2082 2661
2083struct cos_to_protocol { 2662/*
2084 u8 mask[MAX_COS_NUMBER]; 2663 * per-port fairness variables
2664 */
2665struct fairness_vars_per_port {
2666 u32 upper_bound;
2667 u32 fair_threshold;
2668 u32 fairness_timeout;
2085}; 2669};
2086 2670
2087 2671
2088/* 2672/*
2089 * Common statistics collected by the Xstorm (per port) 2673 * per-port SAFC variables
2090 */ 2674 */
2091struct xstorm_common_stats { 2675struct safc_struct_per_port {
2676#if defined(__BIG_ENDIAN)
2677 u16 __reserved0;
2678 u8 cur_cos_types;
2679 u8 safc_timeout_usec;
2680#elif defined(__LITTLE_ENDIAN)
2681 u8 safc_timeout_usec;
2682 u8 cur_cos_types;
2683 u16 __reserved0;
2684#endif
2685 u8 cos_to_protocol[MAX_COS_NUMBER];
2686};
2687
2688
2689/*
2690 * Per-port congestion management variables
2691 */
2692struct cmng_struct_per_port {
2693 struct rate_shaping_vars_per_port rs_vars;
2694 struct fairness_vars_per_port fair_vars;
2695 struct safc_struct_per_port safc_vars;
2696 struct cmng_flags_per_port flags;
2697};
2698
2699
2700/*
2701 * Protocol-common statistics collected by the Xstorm (per client)
2702 */
2703struct xstorm_per_client_stats {
2092 struct regpair total_sent_bytes; 2704 struct regpair total_sent_bytes;
2093 u32 total_sent_pkts; 2705 u32 total_sent_pkts;
2094 u32 unicast_pkts_sent; 2706 u32 unicast_pkts_sent;
@@ -2097,9 +2709,31 @@ struct xstorm_common_stats {
2097 u32 multicast_pkts_sent; 2709 u32 multicast_pkts_sent;
2098 u32 broadcast_pkts_sent; 2710 u32 broadcast_pkts_sent;
2099 struct regpair broadcast_bytes_sent; 2711 struct regpair broadcast_bytes_sent;
2100 struct regpair done; 2712 u16 stats_counter;
2713 u16 reserved0;
2714 u32 reserved1;
2101}; 2715};
2102 2716
2717
2718/*
2719 * Common statistics collected by the Xstorm (per port)
2720 */
2721struct xstorm_common_stats {
2722 struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
2723};
2724
2725
2726/*
2727 * Protocol-common statistics collected by the Tstorm (per port)
2728 */
2729struct tstorm_per_port_stats {
2730 u32 mac_filter_discard;
2731 u32 xxoverflow_discard;
2732 u32 brb_truncate_discard;
2733 u32 mac_discard;
2734};
2735
2736
2103/* 2737/*
2104 * Protocol-common statistics collected by the Tstorm (per client) 2738 * Protocol-common statistics collected by the Tstorm (per client)
2105 */ 2739 */
@@ -2117,20 +2751,17 @@ struct tstorm_per_client_stats {
2117 u32 rcv_multicast_pkts; 2751 u32 rcv_multicast_pkts;
2118 u32 no_buff_discard; 2752 u32 no_buff_discard;
2119 u32 ttl0_discard; 2753 u32 ttl0_discard;
2120 u32 mac_discard; 2754 u16 stats_counter;
2121 u32 reserved; 2755 u16 reserved0;
2756 u32 reserved1;
2122}; 2757};
2123 2758
2124/* 2759/*
2125 * Protocol-common statistics collected by the Tstorm (per port) 2760 * Protocol-common statistics collected by the Tstorm
2126 */ 2761 */
2127struct tstorm_common_stats { 2762struct tstorm_common_stats {
2128 struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID]; 2763 struct tstorm_per_port_stats port_statistics;
2129 u32 mac_filter_discard; 2764 struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2130 u32 xxoverflow_discard;
2131 u32 brb_truncate_discard;
2132 u32 reserved;
2133 struct regpair done;
2134}; 2765};
2135 2766
2136/* 2767/*
@@ -2143,6 +2774,16 @@ struct eth_stats_query {
2143 2774
2144 2775
2145/* 2776/*
2777 * per-vnic fairness variables
2778 */
2779struct fairness_vars_per_vn {
2780 u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2781 u32 vn_credit_delta;
2782 u32 __reserved0;
2783};
2784
2785
2786/*
2146 * FW version stored in the Xstorm RAM 2787 * FW version stored in the Xstorm RAM
2147 */ 2788 */
2148struct fw_version { 2789struct fw_version {
@@ -2160,8 +2801,10 @@ struct fw_version {
2160#define FW_VERSION_OPTIMIZED_SHIFT 0 2801#define FW_VERSION_OPTIMIZED_SHIFT 0
2161#define FW_VERSION_BIG_ENDIEN (0x1<<1) 2802#define FW_VERSION_BIG_ENDIEN (0x1<<1)
2162#define FW_VERSION_BIG_ENDIEN_SHIFT 1 2803#define FW_VERSION_BIG_ENDIEN_SHIFT 1
2163#define __FW_VERSION_RESERVED (0x3FFFFFFF<<2) 2804#define FW_VERSION_CHIP_VERSION (0x3<<2)
2164#define __FW_VERSION_RESERVED_SHIFT 2 2805#define FW_VERSION_CHIP_VERSION_SHIFT 2
2806#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2807#define __FW_VERSION_RESERVED_SHIFT 4
2165}; 2808};
2166 2809
2167 2810
@@ -2169,15 +2812,9 @@ struct fw_version {
2169 * FW version stored in first line of pram 2812 * FW version stored in first line of pram
2170 */ 2813 */
2171struct pram_fw_version { 2814struct pram_fw_version {
2172#if defined(__BIG_ENDIAN)
2173 u16 patch;
2174 u8 primary;
2175 u8 client;
2176#elif defined(__LITTLE_ENDIAN)
2177 u8 client; 2815 u8 client;
2178 u8 primary; 2816 u8 primary;
2179 u16 patch; 2817 u16 patch;
2180#endif
2181 u8 flags; 2818 u8 flags;
2182#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 2819#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2183#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 2820#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
@@ -2185,8 +2822,34 @@ struct pram_fw_version {
2185#define PRAM_FW_VERSION_STORM_ID_SHIFT 1 2822#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2186#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 2823#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2187#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 2824#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2188#define __PRAM_FW_VERSION_RESERVED0 (0xF<<4) 2825#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2189#define __PRAM_FW_VERSION_RESERVED0_SHIFT 4 2826#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2827#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2828#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2829};
2830
2831
2832/*
2833 * a single rate shaping counter. can be used as protocol or vnic counter
2834 */
2835struct rate_shaping_counter {
2836 u32 quota;
2837#if defined(__BIG_ENDIAN)
2838 u16 __reserved0;
2839 u16 rate;
2840#elif defined(__LITTLE_ENDIAN)
2841 u16 rate;
2842 u16 __reserved0;
2843#endif
2844};
2845
2846
2847/*
2848 * per-vnic rate shaping variables
2849 */
2850struct rate_shaping_vars_per_vn {
2851 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
2852 struct rate_shaping_counter vn_counter;
2190}; 2853};
2191 2854
2192 2855
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 370686eef97c..4c7750789b62 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -22,7 +22,8 @@
22#define INIT_ASIC 0x4 22#define INIT_ASIC 0x4
23#define INIT_HARDWARE 0x7 23#define INIT_HARDWARE 0x7
24 24
25#define STORM_INTMEM_SIZE (0x5800 / 4) 25#define STORM_INTMEM_SIZE_E1 (0x5800 / 4)
26#define STORM_INTMEM_SIZE_E1H (0x10000 / 4)
26#define TSTORM_INTMEM_ADDR 0x1a0000 27#define TSTORM_INTMEM_ADDR 0x1a0000
27#define CSTORM_INTMEM_ADDR 0x220000 28#define CSTORM_INTMEM_ADDR 0x220000
28#define XSTORM_INTMEM_ADDR 0x2a0000 29#define XSTORM_INTMEM_ADDR 0x2a0000
@@ -30,7 +31,7 @@
30 31
31 32
32/* Init operation types and structures */ 33/* Init operation types and structures */
33 34/* Common for both E1 and E1H */
34#define OP_RD 0x1 /* read single register */ 35#define OP_RD 0x1 /* read single register */
35#define OP_WR 0x2 /* write single register */ 36#define OP_WR 0x2 /* write single register */
36#define OP_IW 0x3 /* write single register using mailbox */ 37#define OP_IW 0x3 /* write single register using mailbox */
@@ -38,7 +39,37 @@
38#define OP_SI 0x5 /* copy a string using mailbox */ 39#define OP_SI 0x5 /* copy a string using mailbox */
39#define OP_ZR 0x6 /* clear memory */ 40#define OP_ZR 0x6 /* clear memory */
40#define OP_ZP 0x7 /* unzip then copy with DMAE */ 41#define OP_ZP 0x7 /* unzip then copy with DMAE */
41#define OP_WB 0x8 /* copy a string using DMAE */ 42#define OP_WR_64 0x8 /* write 64 bit pattern */
43#define OP_WB 0x9 /* copy a string using DMAE */
44
45/* Operation specific for E1 */
46#define OP_RD_E1 0xa /* read single register */
47#define OP_WR_E1 0xb /* write single register */
48#define OP_IW_E1 0xc /* write single register using mailbox */
49#define OP_SW_E1 0xd /* copy a string to the device */
50#define OP_SI_E1 0xe /* copy a string using mailbox */
51#define OP_ZR_E1 0xf /* clear memory */
52#define OP_ZP_E1 0x10 /* unzip then copy with DMAE */
53#define OP_WR_64_E1 0x11 /* write 64 bit pattern on E1 */
54#define OP_WB_E1 0x12 /* copy a string using DMAE */
55
56/* Operation specific for E1H */
57#define OP_RD_E1H 0x13 /* read single register */
58#define OP_WR_E1H 0x14 /* write single register */
59#define OP_IW_E1H 0x15 /* write single register using mailbox */
60#define OP_SW_E1H 0x16 /* copy a string to the device */
61#define OP_SI_E1H 0x17 /* copy a string using mailbox */
62#define OP_ZR_E1H 0x18 /* clear memory */
63#define OP_ZP_E1H 0x19 /* unzip then copy with DMAE */
64#define OP_WR_64_E1H 0x1a /* write 64 bit pattern on E1H */
65#define OP_WB_E1H 0x1b /* copy a string using DMAE */
66
67/* FPGA and EMUL specific operations */
68#define OP_WR_EMUL_E1H 0x1c /* write single register on E1H Emul */
69#define OP_WR_EMUL 0x1d /* write single register on Emulation */
70#define OP_WR_FPGA 0x1e /* write single register on FPGA */
71#define OP_WR_ASIC 0x1f /* write single register on ASIC */
72
42 73
43struct raw_op { 74struct raw_op {
44 u32 op :8; 75 u32 op :8;
@@ -87,10 +118,6 @@ union init_op {
87#include "bnx2x_init_values.h" 118#include "bnx2x_init_values.h"
88 119
89static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val); 120static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
90
91static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
92 u32 dst_addr, u32 len32);
93
94static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len); 121static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len);
95 122
96static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data, 123static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
@@ -107,9 +134,6 @@ static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
107 } 134 }
108} 135}
109 136
110#define INIT_MEM_WR(reg, data, reg_off, len) \
111 bnx2x_init_str_wr(bp, reg + reg_off*4, data, len)
112
113static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data, 137static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
114 u16 len) 138 u16 len)
115{ 139{
@@ -124,11 +148,117 @@ static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
124 } 148 }
125} 149}
126 150
151static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
152{
153#ifdef USE_DMAE
154 int offset = 0;
155
156 if (bp->dmae_ready) {
157 while (len > DMAE_LEN32_WR_MAX) {
158 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
159 addr + offset, DMAE_LEN32_WR_MAX);
160 offset += DMAE_LEN32_WR_MAX * 4;
161 len -= DMAE_LEN32_WR_MAX;
162 }
163 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
164 addr + offset, len);
165 } else
166 bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
167#else
168 bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
169#endif
170}
171
172static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
173{
174 if ((len * 4) > FW_BUF_SIZE) {
175 BNX2X_ERR("LARGE DMAE OPERATION ! addr 0x%x len 0x%x\n",
176 addr, len*4);
177 return;
178 }
179 memset(bp->gunzip_buf, fill, len * 4);
180
181 bnx2x_write_big_buf(bp, addr, len);
182}
183
184static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
185 u32 len64)
186{
187 u32 buf_len32 = FW_BUF_SIZE/4;
188 u32 len = len64*2;
189 u64 data64 = 0;
190 int i;
191
192 /* 64 bit value is in a blob: first low DWORD, then high DWORD */
193 data64 = HILO_U64((*(data + 1)), (*data));
194 len64 = min((u32)(FW_BUF_SIZE/8), len64);
195 for (i = 0; i < len64; i++) {
196 u64 *pdata = ((u64 *)(bp->gunzip_buf)) + i;
197
198 *pdata = data64;
199 }
200
201 for (i = 0; i < len; i += buf_len32) {
202 u32 cur_len = min(buf_len32, len - i);
203
204 bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
205 }
206}
207
208/*********************************************************
209 There are different blobs for each PRAM section.
210 In addition, each blob write operation is divided into a few operations
211 in order to decrease the amount of phys. contigious buffer needed.
212 Thus, when we select a blob the address may be with some offset
213 from the beginning of PRAM section.
214 The same holds for the INT_TABLE sections.
215**********************************************************/
216#define IF_IS_INT_TABLE_ADDR(base, addr) \
217 if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
218
219#define IF_IS_PRAM_ADDR(base, addr) \
220 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
221
222static const u32 *bnx2x_sel_blob(u32 addr, const u32 *data, int is_e1)
223{
224 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
225 data = is_e1 ? tsem_int_table_data_e1 :
226 tsem_int_table_data_e1h;
227 else
228 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
229 data = is_e1 ? csem_int_table_data_e1 :
230 csem_int_table_data_e1h;
231 else
232 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
233 data = is_e1 ? usem_int_table_data_e1 :
234 usem_int_table_data_e1h;
235 else
236 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
237 data = is_e1 ? xsem_int_table_data_e1 :
238 xsem_int_table_data_e1h;
239 else
240 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
241 data = is_e1 ? tsem_pram_data_e1 : tsem_pram_data_e1h;
242 else
243 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
244 data = is_e1 ? csem_pram_data_e1 : csem_pram_data_e1h;
245 else
246 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
247 data = is_e1 ? usem_pram_data_e1 : usem_pram_data_e1h;
248 else
249 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
250 data = is_e1 ? xsem_pram_data_e1 : xsem_pram_data_e1h;
251
252 return data;
253}
254
127static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data, 255static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
128 u32 len, int gunzip) 256 u32 len, int gunzip, int is_e1, u32 blob_off)
129{ 257{
130 int offset = 0; 258 int offset = 0;
131 259
260 data = bnx2x_sel_blob(addr, data, is_e1) + blob_off;
261
132 if (gunzip) { 262 if (gunzip) {
133 int rc; 263 int rc;
134#ifdef __BIG_ENDIAN 264#ifdef __BIG_ENDIAN
@@ -143,64 +273,59 @@ static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
143#endif 273#endif
144 rc = bnx2x_gunzip(bp, (u8 *)data, len); 274 rc = bnx2x_gunzip(bp, (u8 *)data, len);
145 if (rc) { 275 if (rc) {
146 DP(NETIF_MSG_HW, "gunzip failed ! rc %d\n", rc); 276 BNX2X_ERR("gunzip failed ! rc %d\n", rc);
147 return; 277 return;
148 } 278 }
149 len = bp->gunzip_outlen; 279 len = bp->gunzip_outlen;
150#ifdef __BIG_ENDIAN 280#ifdef __BIG_ENDIAN
151 kfree(temp); 281 kfree(temp);
152 for (i = 0; i < len; i++) 282 for (i = 0; i < len; i++)
153 ((u32 *)bp->gunzip_buf)[i] = 283 ((u32 *)bp->gunzip_buf)[i] =
154 swab32(((u32 *)bp->gunzip_buf)[i]); 284 swab32(((u32 *)bp->gunzip_buf)[i]);
155#endif 285#endif
156 } else { 286 } else {
157 if ((len * 4) > FW_BUF_SIZE) { 287 if ((len * 4) > FW_BUF_SIZE) {
158 BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len*4); 288 BNX2X_ERR("LARGE DMAE OPERATION ! "
289 "addr 0x%x len 0x%x\n", addr, len*4);
159 return; 290 return;
160 } 291 }
161 memcpy(bp->gunzip_buf, data, len * 4); 292 memcpy(bp->gunzip_buf, data, len * 4);
162 } 293 }
163 294
164 while (len > DMAE_LEN32_MAX) { 295 if (bp->dmae_ready) {
165 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, 296 while (len > DMAE_LEN32_WR_MAX) {
166 addr + offset, DMAE_LEN32_MAX); 297 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
167 offset += DMAE_LEN32_MAX * 4; 298 addr + offset, DMAE_LEN32_WR_MAX);
168 len -= DMAE_LEN32_MAX; 299 offset += DMAE_LEN32_WR_MAX * 4;
169 } 300 len -= DMAE_LEN32_WR_MAX;
170 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len); 301 }
171}
172
173#define INIT_MEM_WB(reg, data, reg_off, len) \
174 bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 0)
175
176#define INIT_GUNZIP_DMAE(reg, data, reg_off, len) \
177 bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 1)
178
179static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
180{
181 int offset = 0;
182
183 if ((len * 4) > FW_BUF_SIZE) {
184 BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len * 4);
185 return;
186 }
187 memset(bp->gunzip_buf, fill, len * 4);
188
189 while (len > DMAE_LEN32_MAX) {
190 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, 302 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
191 addr + offset, DMAE_LEN32_MAX); 303 addr + offset, len);
192 offset += DMAE_LEN32_MAX * 4; 304 } else
193 len -= DMAE_LEN32_MAX; 305 bnx2x_init_ind_wr(bp, addr, bp->gunzip_buf, len);
194 }
195 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len);
196} 306}
197 307
198static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end) 308static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
199{ 309{
200 int i; 310 int is_e1 = CHIP_IS_E1(bp);
311 int is_e1h = CHIP_IS_E1H(bp);
312 int is_emul_e1h = (CHIP_REV_IS_EMUL(bp) && is_e1h);
313 int hw_wr, i;
201 union init_op *op; 314 union init_op *op;
202 u32 op_type, addr, len; 315 u32 op_type, addr, len;
203 const u32 *data; 316 const u32 *data, *data_base;
317
318 if (CHIP_REV_IS_FPGA(bp))
319 hw_wr = OP_WR_FPGA;
320 else if (CHIP_REV_IS_EMUL(bp))
321 hw_wr = OP_WR_EMUL;
322 else
323 hw_wr = OP_WR_ASIC;
324
325 if (is_e1)
326 data_base = init_data_e1;
327 else /* CHIP_IS_E1H(bp) */
328 data_base = init_data_e1h;
204 329
205 for (i = op_start; i < op_end; i++) { 330 for (i = op_start; i < op_end; i++) {
206 331
@@ -209,7 +334,30 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
209 op_type = op->str_wr.op; 334 op_type = op->str_wr.op;
210 addr = op->str_wr.offset; 335 addr = op->str_wr.offset;
211 len = op->str_wr.data_len; 336 len = op->str_wr.data_len;
212 data = init_data + op->str_wr.data_off; 337 data = data_base + op->str_wr.data_off;
338
339 /* carefull! it must be in order */
340 if (unlikely(op_type > OP_WB)) {
341
342 /* If E1 only */
343 if (op_type <= OP_WB_E1) {
344 if (is_e1)
345 op_type -= (OP_RD_E1 - OP_RD);
346
347 /* If E1H only */
348 } else if (op_type <= OP_WB_E1H) {
349 if (is_e1h)
350 op_type -= (OP_RD_E1H - OP_RD);
351 }
352
353 /* HW/EMUL specific */
354 if (op_type == hw_wr)
355 op_type = OP_WR;
356
357 /* EMUL on E1H is special */
358 if ((op_type == OP_WR_EMUL_E1H) && is_emul_e1h)
359 op_type = OP_WR;
360 }
213 361
214 switch (op_type) { 362 switch (op_type) {
215 case OP_RD: 363 case OP_RD:
@@ -222,7 +370,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
222 bnx2x_init_str_wr(bp, addr, data, len); 370 bnx2x_init_str_wr(bp, addr, data, len);
223 break; 371 break;
224 case OP_WB: 372 case OP_WB:
225 bnx2x_init_wr_wb(bp, addr, data, len, 0); 373 bnx2x_init_wr_wb(bp, addr, data, len, 0, is_e1, 0);
226 break; 374 break;
227 case OP_SI: 375 case OP_SI:
228 bnx2x_init_ind_wr(bp, addr, data, len); 376 bnx2x_init_ind_wr(bp, addr, data, len);
@@ -231,10 +379,21 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
231 bnx2x_init_fill(bp, addr, 0, op->zero.len); 379 bnx2x_init_fill(bp, addr, 0, op->zero.len);
232 break; 380 break;
233 case OP_ZP: 381 case OP_ZP:
234 bnx2x_init_wr_wb(bp, addr, data, len, 1); 382 bnx2x_init_wr_wb(bp, addr, data, len, 1, is_e1,
383 op->str_wr.data_off);
384 break;
385 case OP_WR_64:
386 bnx2x_init_wr_64(bp, addr, data, len);
235 break; 387 break;
236 default: 388 default:
237 BNX2X_ERR("BAD init operation!\n"); 389 /* happens whenever an op is of a diff HW */
390#if 0
391 DP(NETIF_MSG_HW, "skipping init operation "
392 "index %d[%d:%d]: type %d addr 0x%x "
393 "len %d(0x%x)\n",
394 i, op_start, op_end, op_type, addr, len, len);
395#endif
396 break;
238 } 397 }
239 } 398 }
240} 399}
@@ -245,7 +404,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
245****************************************************************************/ 404****************************************************************************/
246/* 405/*
247 * This code configures the PCI read/write arbiter 406 * This code configures the PCI read/write arbiter
248 * which implements a wighted round robin 407 * which implements a weighted round robin
249 * between the virtual queues in the chip. 408 * between the virtual queues in the chip.
250 * 409 *
251 * The values were derived for each PCI max payload and max request size. 410 * The values were derived for each PCI max payload and max request size.
@@ -315,7 +474,7 @@ static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
315 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} } 474 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} }
316}; 475};
317 476
318/* register adresses for read queues */ 477/* register addresses for read queues */
319static const struct arb_line read_arb_addr[NUM_RD_Q-1] = { 478static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
320 {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0, 479 {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
321 PXP2_REG_RQ_BW_RD_UBOUND0}, 480 PXP2_REG_RQ_BW_RD_UBOUND0},
@@ -375,7 +534,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
375 PXP2_REG_PSWRQ_BW_UB28} 534 PXP2_REG_PSWRQ_BW_UB28}
376}; 535};
377 536
378/* register adresses for wrtie queues */ 537/* register addresses for write queues */
379static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { 538static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
380 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, 539 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
381 PXP2_REG_PSWRQ_BW_UB1}, 540 PXP2_REG_PSWRQ_BW_UB1},
@@ -424,6 +583,10 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
424 w_order, MAX_WR_ORD); 583 w_order, MAX_WR_ORD);
425 w_order = MAX_WR_ORD; 584 w_order = MAX_WR_ORD;
426 } 585 }
586 if (CHIP_REV_IS_FPGA(bp)) {
587 DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
588 w_order = 0;
589 }
427 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order); 590 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
428 591
429 for (i = 0; i < NUM_RD_Q-1; i++) { 592 for (i = 0; i < NUM_RD_Q-1; i++) {
@@ -481,7 +644,20 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
481 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); 644 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
482 645
483 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); 646 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
484 REG_WR(bp, PXP2_REG_WR_DMAE_TH, (128 << w_order)/16); 647
648 if (CHIP_IS_E1H(bp)) {
649 REG_WR(bp, PXP2_REG_WR_HC_MPS, w_order+1);
650 REG_WR(bp, PXP2_REG_WR_USDM_MPS, w_order+1);
651 REG_WR(bp, PXP2_REG_WR_CSDM_MPS, w_order+1);
652 REG_WR(bp, PXP2_REG_WR_TSDM_MPS, w_order+1);
653 REG_WR(bp, PXP2_REG_WR_XSDM_MPS, w_order+1);
654 REG_WR(bp, PXP2_REG_WR_QM_MPS, w_order+1);
655 REG_WR(bp, PXP2_REG_WR_TM_MPS, w_order+1);
656 REG_WR(bp, PXP2_REG_WR_SRC_MPS, w_order+1);
657 REG_WR(bp, PXP2_REG_WR_DBG_MPS, w_order+1);
658 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
659 REG_WR(bp, PXP2_REG_WR_CDU_MPS, w_order+1);
660 }
485} 661}
486 662
487 663
@@ -564,6 +740,72 @@ static u8 calc_crc8(u32 data, u8 crc)
564 return crc_res; 740 return crc_res;
565} 741}
566 742
743/* regiesers addresses are not in order
744 so these arrays help simplify the code */
745static const int cm_start[E1H_FUNC_MAX][9] = {
746 {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START,
747 XCM_FUNC0_START, TSEM_FUNC0_START, USEM_FUNC0_START, CSEM_FUNC0_START,
748 XSEM_FUNC0_START},
749 {MISC_FUNC1_START, TCM_FUNC1_START, UCM_FUNC1_START, CCM_FUNC1_START,
750 XCM_FUNC1_START, TSEM_FUNC1_START, USEM_FUNC1_START, CSEM_FUNC1_START,
751 XSEM_FUNC1_START},
752 {MISC_FUNC2_START, TCM_FUNC2_START, UCM_FUNC2_START, CCM_FUNC2_START,
753 XCM_FUNC2_START, TSEM_FUNC2_START, USEM_FUNC2_START, CSEM_FUNC2_START,
754 XSEM_FUNC2_START},
755 {MISC_FUNC3_START, TCM_FUNC3_START, UCM_FUNC3_START, CCM_FUNC3_START,
756 XCM_FUNC3_START, TSEM_FUNC3_START, USEM_FUNC3_START, CSEM_FUNC3_START,
757 XSEM_FUNC3_START},
758 {MISC_FUNC4_START, TCM_FUNC4_START, UCM_FUNC4_START, CCM_FUNC4_START,
759 XCM_FUNC4_START, TSEM_FUNC4_START, USEM_FUNC4_START, CSEM_FUNC4_START,
760 XSEM_FUNC4_START},
761 {MISC_FUNC5_START, TCM_FUNC5_START, UCM_FUNC5_START, CCM_FUNC5_START,
762 XCM_FUNC5_START, TSEM_FUNC5_START, USEM_FUNC5_START, CSEM_FUNC5_START,
763 XSEM_FUNC5_START},
764 {MISC_FUNC6_START, TCM_FUNC6_START, UCM_FUNC6_START, CCM_FUNC6_START,
765 XCM_FUNC6_START, TSEM_FUNC6_START, USEM_FUNC6_START, CSEM_FUNC6_START,
766 XSEM_FUNC6_START},
767 {MISC_FUNC7_START, TCM_FUNC7_START, UCM_FUNC7_START, CCM_FUNC7_START,
768 XCM_FUNC7_START, TSEM_FUNC7_START, USEM_FUNC7_START, CSEM_FUNC7_START,
769 XSEM_FUNC7_START}
770};
771
772static const int cm_end[E1H_FUNC_MAX][9] = {
773 {MISC_FUNC0_END, TCM_FUNC0_END, UCM_FUNC0_END, CCM_FUNC0_END,
774 XCM_FUNC0_END, TSEM_FUNC0_END, USEM_FUNC0_END, CSEM_FUNC0_END,
775 XSEM_FUNC0_END},
776 {MISC_FUNC1_END, TCM_FUNC1_END, UCM_FUNC1_END, CCM_FUNC1_END,
777 XCM_FUNC1_END, TSEM_FUNC1_END, USEM_FUNC1_END, CSEM_FUNC1_END,
778 XSEM_FUNC1_END},
779 {MISC_FUNC2_END, TCM_FUNC2_END, UCM_FUNC2_END, CCM_FUNC2_END,
780 XCM_FUNC2_END, TSEM_FUNC2_END, USEM_FUNC2_END, CSEM_FUNC2_END,
781 XSEM_FUNC2_END},
782 {MISC_FUNC3_END, TCM_FUNC3_END, UCM_FUNC3_END, CCM_FUNC3_END,
783 XCM_FUNC3_END, TSEM_FUNC3_END, USEM_FUNC3_END, CSEM_FUNC3_END,
784 XSEM_FUNC3_END},
785 {MISC_FUNC4_END, TCM_FUNC4_END, UCM_FUNC4_END, CCM_FUNC4_END,
786 XCM_FUNC4_END, TSEM_FUNC4_END, USEM_FUNC4_END, CSEM_FUNC4_END,
787 XSEM_FUNC4_END},
788 {MISC_FUNC5_END, TCM_FUNC5_END, UCM_FUNC5_END, CCM_FUNC5_END,
789 XCM_FUNC5_END, TSEM_FUNC5_END, USEM_FUNC5_END, CSEM_FUNC5_END,
790 XSEM_FUNC5_END},
791 {MISC_FUNC6_END, TCM_FUNC6_END, UCM_FUNC6_END, CCM_FUNC6_END,
792 XCM_FUNC6_END, TSEM_FUNC6_END, USEM_FUNC6_END, CSEM_FUNC6_END,
793 XSEM_FUNC6_END},
794 {MISC_FUNC7_END, TCM_FUNC7_END, UCM_FUNC7_END, CCM_FUNC7_END,
795 XCM_FUNC7_END, TSEM_FUNC7_END, USEM_FUNC7_END, CSEM_FUNC7_END,
796 XSEM_FUNC7_END},
797};
798
799static const int hc_limits[E1H_FUNC_MAX][2] = {
800 {HC_FUNC0_START, HC_FUNC0_END},
801 {HC_FUNC1_START, HC_FUNC1_END},
802 {HC_FUNC2_START, HC_FUNC2_END},
803 {HC_FUNC3_START, HC_FUNC3_END},
804 {HC_FUNC4_START, HC_FUNC4_END},
805 {HC_FUNC5_START, HC_FUNC5_END},
806 {HC_FUNC6_START, HC_FUNC6_END},
807 {HC_FUNC7_START, HC_FUNC7_END}
808};
567 809
568#endif /* BNX2X_INIT_H */ 810#endif /* BNX2X_INIT_H */
569 811
diff --git a/drivers/net/bnx2x_init_values.h b/drivers/net/bnx2x_init_values.h
index bef0a9b19d68..63019055e4bb 100644
--- a/drivers/net/bnx2x_init_values.h
+++ b/drivers/net/bnx2x_init_values.h
@@ -57,6 +57,7 @@ static const struct raw_op init_ops[] = {
57 {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0}, 57 {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
58 {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0}, 58 {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
59 {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0}, 59 {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
60 {OP_WR_E1H, PRS_REG_FCOE_TYPE, 0x8906},
60 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff}, 61 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
61 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff}, 62 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
62 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff}, 63 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
@@ -74,23 +75,27 @@ static const struct raw_op init_ops[] = {
74 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f}, 75 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
75 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f}, 76 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
76 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f}, 77 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
77#define PRS_COMMON_END 46 78#define PRS_COMMON_END 47
78#define PRS_PORT0_START 46 79#define SRCH_COMMON_START 47
79 {OP_WR, PRS_REG_CID_PORT_0, 0x0}, 80 {OP_WR_E1H, SRC_REG_E1HMF_ENABLE, 0x1},
80#define PRS_PORT0_END 47 81#define SRCH_COMMON_END 48
81#define PRS_PORT1_START 47
82 {OP_WR, PRS_REG_CID_PORT_1, 0x800000},
83#define PRS_PORT1_END 48
84#define TSDM_COMMON_START 48 82#define TSDM_COMMON_START 48
85 {OP_WR, TSDM_REG_CFC_RSP_START_ADDR, 0x411}, 83 {OP_WR_E1, TSDM_REG_CFC_RSP_START_ADDR, 0x411},
86 {OP_WR, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400}, 84 {OP_WR_E1H, TSDM_REG_CFC_RSP_START_ADDR, 0x211},
87 {OP_WR, TSDM_REG_Q_COUNTER_START_ADDR, 0x404}, 85 {OP_WR_E1, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400},
88 {OP_WR, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419}, 86 {OP_WR_E1H, TSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
87 {OP_WR_E1, TSDM_REG_Q_COUNTER_START_ADDR, 0x404},
88 {OP_WR_E1H, TSDM_REG_Q_COUNTER_START_ADDR, 0x204},
89 {OP_WR_E1, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419},
90 {OP_WR_E1H, TSDM_REG_PCK_END_MSG_START_ADDR, 0x219},
89 {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff}, 91 {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
90 {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff}, 92 {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
91 {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff}, 93 {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
92 {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff}, 94 {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
93 {OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x80}, 95 {OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x2},
96 {OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34},
97 {OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35},
98 {OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x7c},
94 {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff}, 99 {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
95 {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f}, 100 {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
96 {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff}, 101 {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
@@ -109,9 +114,12 @@ static const struct raw_op init_ops[] = {
109 {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, 114 {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
110 {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, 115 {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
111 {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, 116 {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
112 {OP_WR, TSDM_REG_TIMER_TICK, 0x3e8}, 117 {OP_WR_E1, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
113#define TSDM_COMMON_END 76 118 {OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8},
114#define TCM_COMMON_START 76 119 {OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1},
120 {OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa},
121#define TSDM_COMMON_END 86
122#define TCM_COMMON_START 86
115 {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20}, 123 {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
116 {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32}, 124 {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
117 {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020}, 125 {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
@@ -143,9 +151,14 @@ static const struct raw_op init_ops[] = {
143 {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8}, 151 {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8},
144 {OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4}, 152 {OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4},
145 {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6}, 153 {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6},
146 {OP_WR, TCM_REG_PHYS_QNUM0_0, 0xd}, 154 {OP_WR_E1, TCM_REG_PHYS_QNUM0_0, 0xd},
147 {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x2d}, 155 {OP_WR_E1, TCM_REG_PHYS_QNUM0_1, 0x2d},
148 {OP_ZR, TCM_REG_PHYS_QNUM1_0, 0x6}, 156 {OP_WR_E1, TCM_REG_PHYS_QNUM1_0, 0x7},
157 {OP_WR_E1, TCM_REG_PHYS_QNUM1_1, 0x27},
158 {OP_WR_E1, TCM_REG_PHYS_QNUM2_0, 0x7},
159 {OP_WR_E1, TCM_REG_PHYS_QNUM2_1, 0x27},
160 {OP_WR_E1, TCM_REG_PHYS_QNUM3_0, 0x7},
161 {OP_WR_E1, TCM_REG_PHYS_QNUM3_1, 0x27},
149 {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1}, 162 {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1},
150 {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1}, 163 {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1},
151 {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1}, 164 {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1},
@@ -162,23 +175,75 @@ static const struct raw_op init_ops[] = {
162 {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1}, 175 {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1},
163 {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1}, 176 {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1},
164 {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1}, 177 {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1},
165#define TCM_COMMON_END 126 178#define TCM_COMMON_END 141
166#define BRB1_COMMON_START 126 179#define TCM_FUNC0_START 141
180 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0xd},
181 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x7},
182 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x7},
183 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x7},
184#define TCM_FUNC0_END 145
185#define TCM_FUNC1_START 145
186 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x2d},
187 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x27},
188 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x27},
189 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x27},
190#define TCM_FUNC1_END 149
191#define TCM_FUNC2_START 149
192 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x1d},
193 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x17},
194 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x17},
195 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x17},
196#define TCM_FUNC2_END 153
197#define TCM_FUNC3_START 153
198 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x3d},
199 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x37},
200 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x37},
201 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x37},
202#define TCM_FUNC3_END 157
203#define TCM_FUNC4_START 157
204 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x4d},
205 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x47},
206 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x47},
207 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x47},
208#define TCM_FUNC4_END 161
209#define TCM_FUNC5_START 161
210 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x6d},
211 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x67},
212 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x67},
213 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x67},
214#define TCM_FUNC5_END 165
215#define TCM_FUNC6_START 165
216 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x5d},
217 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x57},
218 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x57},
219 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x57},
220#define TCM_FUNC6_END 169
221#define TCM_FUNC7_START 169
222 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x7d},
223 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x77},
224 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x77},
225 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x77},
226#define TCM_FUNC7_END 173
227#define BRB1_COMMON_START 173
167 {OP_SW, BRB1_REG_LL_RAM, 0x2000020}, 228 {OP_SW, BRB1_REG_LL_RAM, 0x2000020},
168 {OP_WR, BRB1_REG_SOFT_RESET, 0x1}, 229 {OP_WR, BRB1_REG_SOFT_RESET, 0x1},
169 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
170 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
171 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_2, 0x0},
172 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_3, 0x0},
173 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
174 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
175 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_2, 0x0},
176 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_3, 0x0},
177 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0}, 230 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0},
178 {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220}, 231 {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220},
179 {OP_WR, BRB1_REG_SOFT_RESET, 0x0}, 232 {OP_WR, BRB1_REG_SOFT_RESET, 0x0},
180#define BRB1_COMMON_END 139 233#define BRB1_COMMON_END 178
181#define TSEM_COMMON_START 139 234#define BRB1_PORT0_START 178
235 {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0xb8},
236 {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 0x114},
237 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
238 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
239#define BRB1_PORT0_END 182
240#define BRB1_PORT1_START 182
241 {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0xb8},
242 {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 0x114},
243 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
244 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
245#define BRB1_PORT1_END 186
246#define TSEM_COMMON_START 186
182 {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0}, 247 {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0},
183 {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0}, 248 {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0},
184 {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0}, 249 {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -222,106 +287,247 @@ static const struct raw_op init_ops[] = {
222 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18}, 287 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18},
223 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc}, 288 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc},
224 {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20}, 289 {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20},
225 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, 290 {OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
291 {OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138},
292 {OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
226 {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, 293 {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
227 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2000, 0x1b3}, 294 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2000, 0xb2},
228 {OP_SW, TSEM_REG_FAST_MEMORY + 0x2000 + 0x6cc, 0x10223}, 295 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x1},
229 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, 296 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x23c8, 0xc1},
230 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1000, 0x2}, 297 {OP_WR_EMUL_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x0},
231 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, 298 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x23c8 + 0x304, 0x10223},
232 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, 299 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x1000, 0x2b3},
233 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x810, 0x4}, 300 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
234 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1fa0, 0x4}, 301 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x1000 + 0xacc, 0x10223},
235 {OP_SW, TSEM_REG_FAST_MEMORY + 0x4cf0, 0x80224}, 302 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1000, 0x2},
236 {OP_ZP, TSEM_REG_INT_TABLE, 0x8c022c}, 303 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8},
237 {OP_ZP, TSEM_REG_PRAM, 0x3395024f}, 304 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c18, 0x4},
238 {OP_ZP, TSEM_REG_PRAM + 0x8000, 0x2c760f35}, 305 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa000, 0x2},
239 {OP_ZP, TSEM_REG_PRAM + 0x10000, 0x5e1a53}, 306 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
240 {OP_ZP, TSEM_REG_PRAM + 0x18000, 0x5e1a6b}, 307 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad0, 0x0},
241 {OP_ZP, TSEM_REG_PRAM + 0x20000, 0x5e1a83}, 308 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
242 {OP_ZP, TSEM_REG_PRAM + 0x28000, 0x5e1a9b}, 309 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3b28, 0x6},
243 {OP_ZP, TSEM_REG_PRAM + 0x30000, 0x5e1ab3}, 310 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x810, 0x4},
244 {OP_ZP, TSEM_REG_PRAM + 0x38000, 0x5e1acb}, 311 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
245#define TSEM_COMMON_END 202 312 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x40224},
246#define TSEM_PORT0_START 202 313 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5008, 0x4},
247 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x16c}, 314 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x4cb0, 0x80228},
248 {OP_SW, TSEM_REG_FAST_MEMORY + 0x4000 + 0x5b0, 0x21ae3}, 315 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5018, 0x4},
249 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1370, 0xa}, 316 {OP_ZP_E1, TSEM_REG_INT_TABLE, 0x940000},
250 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x13c0, 0x6}, 317 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5028, 0x4},
251 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1418, 0xc}, 318 {OP_WR_64_E1, TSEM_REG_INT_TABLE + 0x360, 0x140230},
252 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1478, 0x12}, 319 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5038, 0x4},
253 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1508, 0x90}, 320 {OP_ZP_E1, TSEM_REG_PRAM, 0x30b10000},
254 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, 321 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5048, 0x4},
255 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x820, 0x10}, 322 {OP_ZP_E1, TSEM_REG_PRAM + 0x8000, 0x33c50c2d},
256 {OP_SW, TSEM_REG_FAST_MEMORY + 0x820 + 0x40, 0x21ae5}, 323 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5058, 0x4},
257 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2908, 0xa}, 324 {OP_ZP_E1, TSEM_REG_PRAM + 0x10000, 0xbc6191f},
258#define TSEM_PORT0_END 213 325 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5068, 0x4},
259#define TSEM_PORT1_START 213 326 {OP_WR_64_E1, TSEM_REG_PRAM + 0x117f0, 0x5d020232},
260 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x45b8, 0x16c}, 327 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5078, 0x2},
261 {OP_SW, TSEM_REG_FAST_MEMORY + 0x45b8 + 0x5b0, 0x21ae7}, 328 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
262 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1398, 0xa}, 329 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
263 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x13d8, 0x6}, 330 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x6140, 0x200224},
264 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1448, 0xc}, 331 {OP_ZP_E1H, TSEM_REG_INT_TABLE, 0x960000},
265 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x14c0, 0x12}, 332 {OP_WR_64_E1H, TSEM_REG_INT_TABLE + 0x360, 0x140244},
266 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1748, 0x90}, 333 {OP_ZP_E1H, TSEM_REG_PRAM, 0x30cc0000},
267 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, 334 {OP_ZP_E1H, TSEM_REG_PRAM + 0x8000, 0x33df0c33},
268 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x868, 0x10}, 335 {OP_ZP_E1H, TSEM_REG_PRAM + 0x10000, 0xdce192b},
269 {OP_SW, TSEM_REG_FAST_MEMORY + 0x868 + 0x40, 0x21ae9}, 336 {OP_WR_64_E1H, TSEM_REG_PRAM + 0x11c70, 0x5c720246},
270 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2930, 0xa}, 337#define TSEM_COMMON_END 276
271#define TSEM_PORT1_END 224 338#define TSEM_PORT0_START 276
272#define MISC_COMMON_START 224 339 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20},
273 {OP_WR, MISC_REG_GRC_TIMEOUT_EN, 0x1}, 340 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x2000, 0x16c},
341 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x4000, 0xfc},
342 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb000, 0x28},
343 {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b60, 0x0},
344 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb140, 0xc},
345 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1400, 0xa},
346 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32c0, 0x12},
347 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1450, 0x6},
348 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3350, 0xfa},
349 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500, 0xe},
350 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8108, 0x2},
351 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1570, 0x12},
352 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x9c0, 0xbe},
353 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
354 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x820, 0xe},
355 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x20234},
356 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2908, 0x2},
357#define TSEM_PORT0_END 294
358#define TSEM_PORT1_START 294
359 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2348, 0x20},
360 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x25b0, 0x16c},
361 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x43f0, 0xfc},
362 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28},
363 {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b64, 0x0},
364 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb170, 0xc},
365 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1428, 0xa},
366 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3308, 0x12},
367 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1468, 0x6},
368 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3738, 0xfa},
369 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538, 0xe},
370 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8110, 0x2},
371 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x15b8, 0x12},
372 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0xcb8, 0xbe},
373 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
374 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x858, 0xe},
375 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20236},
376 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2910, 0x2},
377#define TSEM_PORT1_END 312
378#define TSEM_FUNC0_START 312
379 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b60, 0x0},
380 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000, 0xe},
381 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31c0, 0x8},
382 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
383 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5080, 0x12},
384 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
385#define TSEM_FUNC0_END 318
386#define TSEM_FUNC1_START 318
387 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b64, 0x0},
388 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038, 0xe},
389 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31e0, 0x8},
390 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5010, 0x2},
391 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12},
392 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
393#define TSEM_FUNC1_END 324
394#define TSEM_FUNC2_START 324
395 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b68, 0x0},
396 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070, 0xe},
397 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3200, 0x8},
398 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5020, 0x2},
399 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5110, 0x12},
400 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4010, 0x20248},
401#define TSEM_FUNC2_END 330
402#define TSEM_FUNC3_START 330
403 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b6c, 0x0},
404 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8, 0xe},
405 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3220, 0x8},
406 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5030, 0x2},
407 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5158, 0x12},
408 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4018, 0x2024a},
409#define TSEM_FUNC3_END 336
410#define TSEM_FUNC4_START 336
411 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b70, 0x0},
412 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0, 0xe},
413 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3240, 0x8},
414 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5040, 0x2},
415 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12},
416 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4020, 0x2024c},
417#define TSEM_FUNC4_END 342
418#define TSEM_FUNC5_START 342
419 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b74, 0x0},
420 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118, 0xe},
421 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3260, 0x8},
422 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5050, 0x2},
423 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12},
424 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4028, 0x2024e},
425#define TSEM_FUNC5_END 348
426#define TSEM_FUNC6_START 348
427 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b78, 0x0},
428 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150, 0xe},
429 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3280, 0x8},
430 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5060, 0x2},
431 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5230, 0x12},
432 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4030, 0x20250},
433#define TSEM_FUNC6_END 354
434#define TSEM_FUNC7_START 354
435 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b7c, 0x0},
436 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188, 0xe},
437 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8},
438 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5070, 0x2},
439 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5278, 0x12},
440 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4038, 0x20252},
441#define TSEM_FUNC7_END 360
442#define MISC_COMMON_START 360
443 {OP_WR_E1, MISC_REG_GRC_TIMEOUT_EN, 0x1},
274 {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911}, 444 {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911},
275 {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0}, 445 {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0},
276 {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424}, 446 {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424},
277 {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0}, 447 {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0},
278 {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209}, 448 {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209},
279#define MISC_COMMON_END 230 449 {OP_WR_E1, MISC_REG_SPIO, 0xff000000},
280#define NIG_COMMON_START 230 450#define MISC_COMMON_END 367
451#define MISC_FUNC0_START 367
452 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
453#define MISC_FUNC0_END 368
454#define MISC_FUNC1_START 368
455 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
456#define MISC_FUNC1_END 369
457#define MISC_FUNC2_START 369
458 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
459#define MISC_FUNC2_END 370
460#define MISC_FUNC3_START 370
461 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
462#define MISC_FUNC3_END 371
463#define MISC_FUNC4_START 371
464 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
465#define MISC_FUNC4_END 372
466#define MISC_FUNC5_START 372
467 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
468#define MISC_FUNC5_END 373
469#define MISC_FUNC6_START 373
470 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
471#define MISC_FUNC6_END 374
472#define MISC_FUNC7_START 374
473 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
474#define MISC_FUNC7_END 375
475#define NIG_COMMON_START 375
281 {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1}, 476 {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1},
282 {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1}, 477 {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1},
283 {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1}, 478 {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1},
284 {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1}, 479 {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1},
285 {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1}, 480 {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1},
286#define NIG_COMMON_END 235 481#define NIG_COMMON_END 380
287#define NIG_PORT0_START 235 482#define NIG_PORT0_START 380
288 {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000}, 483 {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000},
289 {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x26}, 484 {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28},
290 {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0}, 485 {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0},
291 {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4}, 486 {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4},
292 {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1}, 487 {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1},
293 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0}, 488 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0},
489 {OP_WR_E1H, NIG_REG_LLH0_CLS_TYPE, 0x1},
294 {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30}, 490 {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30},
295 {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1}, 491 {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1},
296 {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1}, 492 {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1},
297 {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1}, 493 {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1},
298 {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1}, 494 {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1},
299#define NIG_PORT0_END 246 495#define NIG_PORT0_END 392
300#define NIG_PORT1_START 246 496#define NIG_PORT1_START 392
301 {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000}, 497 {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000},
302 {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x26}, 498 {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28},
303 {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0}, 499 {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0},
304 {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4}, 500 {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4},
305 {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1}, 501 {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1},
306 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0}, 502 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0},
503 {OP_WR_E1H, NIG_REG_LLH1_CLS_TYPE, 0x1},
307 {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30}, 504 {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30},
308 {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1}, 505 {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1},
309 {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1}, 506 {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1},
310 {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1}, 507 {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1},
311 {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1}, 508 {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1},
312#define NIG_PORT1_END 257 509#define NIG_PORT1_END 404
313#define UPB_COMMON_START 257 510#define UPB_COMMON_START 404
314 {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20}, 511 {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20},
315#define UPB_COMMON_END 258 512#define UPB_COMMON_END 405
316#define CSDM_COMMON_START 258 513#define CSDM_COMMON_START 405
317 {OP_WR, CSDM_REG_CFC_RSP_START_ADDR, 0xa11}, 514 {OP_WR_E1, CSDM_REG_CFC_RSP_START_ADDR, 0xa11},
318 {OP_WR, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, 515 {OP_WR_E1H, CSDM_REG_CFC_RSP_START_ADDR, 0x211},
319 {OP_WR, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04}, 516 {OP_WR_E1, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
517 {OP_WR_E1H, CSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
518 {OP_WR_E1, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04},
519 {OP_WR_E1H, CSDM_REG_Q_COUNTER_START_ADDR, 0x204},
320 {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff}, 520 {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff},
321 {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff}, 521 {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff},
322 {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff}, 522 {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff},
323 {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff}, 523 {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff},
324 {OP_ZR, CSDM_REG_AGG_INT_EVENT_0, 0x80}, 524 {OP_WR, CSDM_REG_AGG_INT_EVENT_0, 0xc6},
525 {OP_WR, CSDM_REG_AGG_INT_EVENT_1, 0x0},
526 {OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34},
527 {OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35},
528 {OP_ZR, CSDM_REG_AGG_INT_EVENT_4, 0x1c},
529 {OP_WR, CSDM_REG_AGG_INT_T_0, 0x1},
530 {OP_ZR, CSDM_REG_AGG_INT_T_1, 0x5f},
325 {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff}, 531 {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff},
326 {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f}, 532 {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f},
327 {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff}, 533 {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff},
@@ -340,19 +546,29 @@ static const struct raw_op init_ops[] = {
340 {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, 546 {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
341 {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, 547 {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
342 {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, 548 {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
343 {OP_WR, CSDM_REG_TIMER_TICK, 0x3e8}, 549 {OP_WR_E1, CSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
344#define CSDM_COMMON_END 285 550 {OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8},
345#define USDM_COMMON_START 285 551 {OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1},
346 {OP_WR, USDM_REG_CFC_RSP_START_ADDR, 0xa11}, 552 {OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa},
347 {OP_WR, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, 553#define CSDM_COMMON_END 444
348 {OP_WR, USDM_REG_Q_COUNTER_START_ADDR, 0xa04}, 554#define USDM_COMMON_START 444
349 {OP_WR, USDM_REG_PCK_END_MSG_START_ADDR, 0xa21}, 555 {OP_WR_E1, USDM_REG_CFC_RSP_START_ADDR, 0xa11},
556 {OP_WR_E1H, USDM_REG_CFC_RSP_START_ADDR, 0x411},
557 {OP_WR_E1, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
558 {OP_WR_E1H, USDM_REG_CMP_COUNTER_START_ADDR, 0x400},
559 {OP_WR_E1, USDM_REG_Q_COUNTER_START_ADDR, 0xa04},
560 {OP_WR_E1H, USDM_REG_Q_COUNTER_START_ADDR, 0x404},
561 {OP_WR_E1, USDM_REG_PCK_END_MSG_START_ADDR, 0xa21},
562 {OP_WR_E1H, USDM_REG_PCK_END_MSG_START_ADDR, 0x421},
350 {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff}, 563 {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff},
351 {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff}, 564 {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff},
352 {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff}, 565 {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff},
353 {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff}, 566 {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff},
354 {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46}, 567 {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46},
355 {OP_ZR, USDM_REG_AGG_INT_EVENT_1, 0x5f}, 568 {OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5},
569 {OP_WR, USDM_REG_AGG_INT_EVENT_2, 0x34},
570 {OP_WR, USDM_REG_AGG_INT_EVENT_3, 0x35},
571 {OP_ZR, USDM_REG_AGG_INT_EVENT_4, 0x5c},
356 {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1}, 572 {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1},
357 {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x1f}, 573 {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x1f},
358 {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff}, 574 {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff},
@@ -374,9 +590,12 @@ static const struct raw_op init_ops[] = {
374 {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0}, 590 {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0},
375 {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, 591 {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
376 {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, 592 {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
377 {OP_WR, USDM_REG_TIMER_TICK, 0x3e8}, 593 {OP_WR_E1, USDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
378#define USDM_COMMON_END 317 594 {OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8},
379#define CCM_COMMON_START 317 595 {OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1},
596 {OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa},
597#define USDM_COMMON_END 486
598#define CCM_COMMON_START 486
380 {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32}, 599 {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32},
381 {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020}, 600 {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020},
382 {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020}, 601 {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020},
@@ -401,23 +620,28 @@ static const struct raw_op init_ops[] = {
401 {OP_WR, CCM_REG_XX_INIT_CRD, 0x3}, 620 {OP_WR, CCM_REG_XX_INIT_CRD, 0x3},
402 {OP_WR, CCM_REG_XX_MSG_NUM, 0x18}, 621 {OP_WR, CCM_REG_XX_MSG_NUM, 0x18},
403 {OP_ZR, CCM_REG_XX_TABLE, 0x12}, 622 {OP_ZR, CCM_REG_XX_TABLE, 0x12},
404 {OP_SW, CCM_REG_XX_DESCR_TABLE, 0x241aeb}, 623 {OP_SW_E1, CCM_REG_XX_DESCR_TABLE, 0x240238},
624 {OP_SW_E1H, CCM_REG_XX_DESCR_TABLE, 0x240254},
405 {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1}, 625 {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1},
406 {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2}, 626 {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2},
407 {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8}, 627 {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8},
408 {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8}, 628 {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8},
409 {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4}, 629 {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4},
410 {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4}, 630 {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4},
411 {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x9}, 631 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
412 {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x29}, 632 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
413 {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0xa}, 633 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
414 {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a}, 634 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
415 {OP_ZR, CCM_REG_QOS_PHYS_QNUM2_0, 0x4}, 635 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
416 {OP_WR, CCM_REG_PHYS_QNUM1_0, 0xc}, 636 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
417 {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x2c}, 637 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
418 {OP_WR, CCM_REG_PHYS_QNUM2_0, 0xb}, 638 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
419 {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x2b}, 639 {OP_WR_E1, CCM_REG_PHYS_QNUM1_0, 0xc},
420 {OP_ZR, CCM_REG_PHYS_QNUM3_0, 0x2}, 640 {OP_WR_E1, CCM_REG_PHYS_QNUM1_1, 0x2c},
641 {OP_WR_E1, CCM_REG_PHYS_QNUM2_0, 0xc},
642 {OP_WR_E1, CCM_REG_PHYS_QNUM2_1, 0x2c},
643 {OP_WR_E1, CCM_REG_PHYS_QNUM3_0, 0xc},
644 {OP_WR_E1, CCM_REG_PHYS_QNUM3_1, 0x2c},
421 {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1}, 645 {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1},
422 {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1}, 646 {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1},
423 {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1}, 647 {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1},
@@ -433,8 +657,80 @@ static const struct raw_op init_ops[] = {
433 {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1}, 657 {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1},
434 {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1}, 658 {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1},
435 {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1}, 659 {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1},
436#define CCM_COMMON_END 373 660#define CCM_COMMON_END 547
437#define UCM_COMMON_START 373 661#define CCM_FUNC0_START 547
662 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
663 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
664 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
665 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
666 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0xc},
667 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0xb},
668 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x7},
669#define CCM_FUNC0_END 554
670#define CCM_FUNC1_START 554
671 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
672 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
673 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
674 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
675 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x2c},
676 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x2b},
677 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x27},
678#define CCM_FUNC1_END 561
679#define CCM_FUNC2_START 561
680 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x19},
681 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a},
682 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x17},
683 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x17},
684 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x1c},
685 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x1b},
686 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x17},
687#define CCM_FUNC2_END 568
688#define CCM_FUNC3_START 568
689 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x39},
690 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a},
691 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x37},
692 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x37},
693 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x3c},
694 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x3b},
695 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x37},
696#define CCM_FUNC3_END 575
697#define CCM_FUNC4_START 575
698 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x49},
699 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a},
700 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x47},
701 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x47},
702 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x4c},
703 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x4b},
704 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x47},
705#define CCM_FUNC4_END 582
706#define CCM_FUNC5_START 582
707 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x69},
708 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a},
709 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x67},
710 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x67},
711 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x6c},
712 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x6b},
713 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x67},
714#define CCM_FUNC5_END 589
715#define CCM_FUNC6_START 589
716 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x59},
717 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a},
718 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x57},
719 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x57},
720 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x5c},
721 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x5b},
722 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x57},
723#define CCM_FUNC6_END 596
724#define CCM_FUNC7_START 596
725 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x79},
726 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a},
727 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x77},
728 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x77},
729 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x7c},
730 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x7b},
731 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x77},
732#define CCM_FUNC7_END 603
733#define UCM_COMMON_START 603
438 {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32}, 734 {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32},
439 {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020}, 735 {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020},
440 {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020}, 736 {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020},
@@ -457,20 +753,23 @@ static const struct raw_op init_ops[] = {
457 {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40}, 753 {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40},
458 {OP_WR, UCM_REG_TM_INIT_CRD, 0x4}, 754 {OP_WR, UCM_REG_TM_INIT_CRD, 0x4},
459 {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20}, 755 {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20},
460 {OP_WR, UCM_REG_XX_INIT_CRD, 0xc}, 756 {OP_WR, UCM_REG_XX_INIT_CRD, 0xe},
461 {OP_WR, UCM_REG_XX_MSG_NUM, 0x20}, 757 {OP_WR, UCM_REG_XX_MSG_NUM, 0x1b},
462 {OP_ZR, UCM_REG_XX_TABLE, 0x12}, 758 {OP_ZR, UCM_REG_XX_TABLE, 0x12},
463 {OP_SW, UCM_REG_XX_DESCR_TABLE, 0x201b0f}, 759 {OP_SW_E1, UCM_REG_XX_DESCR_TABLE, 0x1b025c},
464 {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0xa}, 760 {OP_SW_E1H, UCM_REG_XX_DESCR_TABLE, 0x1b0278},
761 {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0x10},
465 {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7}, 762 {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7},
466 {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf}, 763 {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf},
467 {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10}, 764 {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10},
468 {OP_ZR, UCM_REG_N_SM_CTX_LD_4, 0x4}, 765 {OP_ZR_E1, UCM_REG_N_SM_CTX_LD_4, 0x4},
766 {OP_WR_E1H, UCM_REG_N_SM_CTX_LD_4, 0xd},
767 {OP_ZR_E1H, UCM_REG_N_SM_CTX_LD_5, 0x3},
469 {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3}, 768 {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3},
470 {OP_WR, UCM_REG_PHYS_QNUM0_0, 0xf}, 769 {OP_WR_E1, UCM_REG_PHYS_QNUM0_0, 0xf},
471 {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x2f}, 770 {OP_WR_E1, UCM_REG_PHYS_QNUM0_1, 0x2f},
472 {OP_WR, UCM_REG_PHYS_QNUM1_0, 0xe}, 771 {OP_WR_E1, UCM_REG_PHYS_QNUM1_0, 0xe},
473 {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x2e}, 772 {OP_WR_E1, UCM_REG_PHYS_QNUM1_1, 0x2e},
474 {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1}, 773 {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1},
475 {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1}, 774 {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1},
476 {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1}, 775 {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1},
@@ -488,8 +787,56 @@ static const struct raw_op init_ops[] = {
488 {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1}, 787 {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1},
489 {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1}, 788 {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1},
490 {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1}, 789 {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1},
491#define UCM_COMMON_END 426 790#define UCM_COMMON_END 659
492#define USEM_COMMON_START 426 791#define UCM_FUNC0_START 659
792 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0xf},
793 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0xe},
794 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
795 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
796#define UCM_FUNC0_END 663
797#define UCM_FUNC1_START 663
798 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x2f},
799 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x2e},
800 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
801 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
802#define UCM_FUNC1_END 667
803#define UCM_FUNC2_START 667
804 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x1f},
805 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x1e},
806 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
807 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
808#define UCM_FUNC2_END 671
809#define UCM_FUNC3_START 671
810 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x3f},
811 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x3e},
812 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
813 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
814#define UCM_FUNC3_END 675
815#define UCM_FUNC4_START 675
816 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x4f},
817 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x4e},
818 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
819 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
820#define UCM_FUNC4_END 679
821#define UCM_FUNC5_START 679
822 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x6f},
823 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x6e},
824 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
825 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
826#define UCM_FUNC5_END 683
827#define UCM_FUNC6_START 683
828 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x5f},
829 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x5e},
830 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
831 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
832#define UCM_FUNC6_END 687
833#define UCM_FUNC7_START 687
834 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x7f},
835 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x7e},
836 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
837 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
838#define UCM_FUNC7_END 691
839#define USEM_COMMON_START 691
493 {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0}, 840 {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0},
494 {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0}, 841 {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0},
495 {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0}, 842 {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0},
@@ -533,87 +880,196 @@ static const struct raw_op init_ops[] = {
533 {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e}, 880 {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e},
534 {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10}, 881 {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10},
535 {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20}, 882 {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20},
536 {OP_WR, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, 883 {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
884 {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138},
885 {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388},
537 {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, 886 {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
538 {OP_WR, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, 887 {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
539 {OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x102}, 888 {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
540 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1020, 0xc8}, 889 {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
541 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1000, 0x2}, 890 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5000, 0x102},
542 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1e20, 0x40}, 891 {OP_WR_EMUL_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x0},
543 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3000, 0x400}, 892 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1020, 0xc8},
544 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2400, 0x2}, 893 {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x1},
545 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2408, 0x2}, 894 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1000, 0x2},
546 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2410, 0x6}, 895 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2000, 0x102},
547 {OP_SW, USEM_REG_FAST_MEMORY + 0x2410 + 0x18, 0x21b2f}, 896 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57e8, 0x4},
548 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b68, 0x2}, 897 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8020, 0xc8},
549 {OP_SW, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x21b31}, 898 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57d0, 0x5},
550 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b10, 0x2}, 899 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8000, 0x2},
551 {OP_SW, USEM_REG_FAST_MEMORY + 0x2c30, 0x21b33}, 900 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x57d0 + 0x14, 0x10277},
901 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3760, 0x4},
902 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1e20, 0x42},
903 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3738, 0x9},
904 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x400},
905 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3738 + 0x24, 0x10293},
906 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c00, 0x2},
907 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x42},
908 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2c00 + 0x8, 0x20278},
909 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400},
910 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2},
911 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2},
912 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x2027a},
913 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x20294},
914 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2},
915 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2},
916 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027c},
917 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x20296},
918 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2},
919 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x20298},
552 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, 920 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
553 {OP_SW, USEM_REG_FAST_MEMORY + 0x10c00, 0x101b35}, 921 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027e},
922 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x10029a},
554 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0}, 923 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
555 {OP_SW, USEM_REG_FAST_MEMORY + 0x10c40, 0x101b45}, 924 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028e},
556 {OP_ZP, USEM_REG_INT_TABLE, 0xb41b55}, 925 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002aa},
557 {OP_ZP, USEM_REG_PRAM, 0x32d01b82}, 926 {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc20000},
558 {OP_ZP, USEM_REG_PRAM + 0x8000, 0x32172836}, 927 {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xc40000},
559 {OP_ZP, USEM_REG_PRAM + 0x10000, 0x1a7a34bc}, 928 {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029e},
560 {OP_ZP, USEM_REG_PRAM + 0x18000, 0x5f3b5b}, 929 {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x368, 0x1302ba},
561 {OP_ZP, USEM_REG_PRAM + 0x20000, 0x5f3b73}, 930 {OP_ZP_E1, USEM_REG_PRAM, 0x311c0000},
562 {OP_ZP, USEM_REG_PRAM + 0x28000, 0x5f3b8b}, 931 {OP_ZP_E1H, USEM_REG_PRAM, 0x31070000},
563 {OP_ZP, USEM_REG_PRAM + 0x30000, 0x5f3ba3}, 932 {OP_ZP_E1, USEM_REG_PRAM + 0x8000, 0x33450c47},
564 {OP_ZP, USEM_REG_PRAM + 0x38000, 0x5f3bbb}, 933 {OP_ZP_E1H, USEM_REG_PRAM + 0x8000, 0x330e0c42},
565#define USEM_COMMON_END 498 934 {OP_ZP_E1, USEM_REG_PRAM + 0x10000, 0x38561919},
566#define USEM_PORT0_START 498 935 {OP_ZP_E1H, USEM_REG_PRAM + 0x10000, 0x389b1906},
567 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1400, 0xa0}, 936 {OP_WR_64_E1, USEM_REG_PRAM + 0x17fe0, 0x500402a0},
568 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1900, 0xa}, 937 {OP_ZP_E1H, USEM_REG_PRAM + 0x18000, 0x132272d},
569 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1950, 0x2e}, 938 {OP_WR_64_E1H, USEM_REG_PRAM + 0x18250, 0x4fb602bc},
570 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1d00, 0x24}, 939#define USEM_COMMON_END 790
571 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3000, 0x20}, 940#define USEM_PORT0_START 790
572 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3100, 0x20}, 941 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0},
573 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3200, 0x20}, 942 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0},
574 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3300, 0x20}, 943 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0xa},
575 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3400, 0x20}, 944 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9500, 0x28},
576 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3500, 0x20}, 945 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1950, 0x2e},
577 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3600, 0x20}, 946 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9640, 0x34},
578 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3700, 0x20}, 947 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d00, 0x4},
579 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3800, 0x20}, 948 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3080, 0x20},
580 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3900, 0x20}, 949 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d20, 0x20},
581 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3a00, 0x20}, 950 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3288, 0x96},
582 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3b00, 0x20}, 951 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5440, 0x72},
583 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3c00, 0x20}, 952 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
584 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3d00, 0x20}, 953 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x20},
585 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3e00, 0x20}, 954 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5100, 0x20},
586 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3f00, 0x20}, 955 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3100, 0x20},
587 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2400, 0x2}, 956 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5200, 0x20},
588 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b78, 0x52}, 957 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3200, 0x20},
589 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4e08, 0xc}, 958 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5300, 0x20},
590#define USEM_PORT0_END 521 959 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3300, 0x20},
591#define USEM_PORT1_START 521 960 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5400, 0x20},
592 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1680, 0xa0}, 961 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3400, 0x20},
593 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1928, 0xa}, 962 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5500, 0x20},
594 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1a08, 0x2e}, 963 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3500, 0x20},
595 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1d90, 0x24}, 964 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5600, 0x20},
596 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3080, 0x20}, 965 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3600, 0x20},
597 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3180, 0x20}, 966 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5700, 0x20},
598 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3280, 0x20}, 967 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3700, 0x20},
599 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3380, 0x20}, 968 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5800, 0x20},
600 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3480, 0x20}, 969 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3800, 0x20},
601 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3580, 0x20}, 970 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5900, 0x20},
602 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3680, 0x20}, 971 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3900, 0x20},
603 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3780, 0x20}, 972 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a00, 0x20},
604 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3880, 0x20}, 973 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a00, 0x20},
605 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3980, 0x20}, 974 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b00, 0x20},
606 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3a80, 0x20}, 975 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b00, 0x20},
607 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3b80, 0x20}, 976 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c00, 0x20},
608 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3c80, 0x20}, 977 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c00, 0x20},
609 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3d80, 0x20}, 978 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d00, 0x20},
610 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3e80, 0x20}, 979 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d00, 0x20},
611 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3f80, 0x20}, 980 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e00, 0x20},
612 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2408, 0x2}, 981 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e00, 0x20},
613 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52}, 982 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f00, 0x20},
614 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4e38, 0xc}, 983 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f00, 0x20},
615#define USEM_PORT1_END 544 984 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b78, 0x52},
616#define CSEM_COMMON_START 544 985 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c10, 0x2},
986 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc},
987 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52},
988 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc},
989#define USEM_PORT0_END 838
990#define USEM_PORT1_START 838
991 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0},
992 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0},
993 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1928, 0xa},
994 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x95a0, 0x28},
995 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1a08, 0x2e},
996 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9710, 0x34},
997 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d10, 0x4},
998 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3100, 0x20},
999 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1da0, 0x20},
1000 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x34e0, 0x96},
1001 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5608, 0x72},
1002 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5080, 0x20},
1003 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3080, 0x20},
1004 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5180, 0x20},
1005 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3180, 0x20},
1006 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5280, 0x20},
1007 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3280, 0x20},
1008 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5380, 0x20},
1009 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3380, 0x20},
1010 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5480, 0x20},
1011 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3480, 0x20},
1012 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5580, 0x20},
1013 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3580, 0x20},
1014 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5680, 0x20},
1015 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3680, 0x20},
1016 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5780, 0x20},
1017 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3780, 0x20},
1018 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5880, 0x20},
1019 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3880, 0x20},
1020 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5980, 0x20},
1021 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3980, 0x20},
1022 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a80, 0x20},
1023 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a80, 0x20},
1024 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b80, 0x20},
1025 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b80, 0x20},
1026 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c80, 0x20},
1027 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c80, 0x20},
1028 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d80, 0x20},
1029 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d80, 0x20},
1030 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e80, 0x20},
1031 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e80, 0x20},
1032 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f80, 0x20},
1033 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f80, 0x20},
1034 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52},
1035 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c20, 0x2},
1036 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc},
1037 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52},
1038 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc},
1039#define USEM_PORT1_END 886
1040#define USEM_FUNC0_START 886
1041 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4},
1042 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4010, 0x2},
1043#define USEM_FUNC0_END 888
1044#define USEM_FUNC1_START 888
1045 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4},
1046 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4020, 0x2},
1047#define USEM_FUNC1_END 890
1048#define USEM_FUNC2_START 890
1049 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4},
1050 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4030, 0x2},
1051#define USEM_FUNC2_END 892
1052#define USEM_FUNC3_START 892
1053 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4},
1054 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4040, 0x2},
1055#define USEM_FUNC3_END 894
1056#define USEM_FUNC4_START 894
1057 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4},
1058 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4050, 0x2},
1059#define USEM_FUNC4_END 896
1060#define USEM_FUNC5_START 896
1061 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4},
1062 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4060, 0x2},
1063#define USEM_FUNC5_END 898
1064#define USEM_FUNC6_START 898
1065 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4},
1066 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4070, 0x2},
1067#define USEM_FUNC6_END 900
1068#define USEM_FUNC7_START 900
1069 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4},
1070 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4080, 0x2},
1071#define USEM_FUNC7_END 902
1072#define CSEM_COMMON_START 902
617 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0}, 1073 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
618 {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0}, 1074 {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
619 {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0}, 1075 {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -658,50 +1114,106 @@ static const struct raw_op init_ops[] = {
658 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30}, 1114 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30},
659 {OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe}, 1115 {OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe},
660 {OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, 1116 {OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
661 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x5000, 0x42}, 1117 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x5000, 0x42},
662 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, 1118 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11480, 0x1},
663 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1000, 0x2}, 1119 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
664 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2000, 0xc0}, 1120 {OP_WR_EMUL_E1H, CSEM_REG_FAST_MEMORY + 0x11480, 0x0},
665 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3070, 0x80}, 1121 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1000, 0x2},
666 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4280, 0x4}, 1122 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x1000, 0x42},
667 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240}, 1123 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2000, 0xc0},
668 {OP_SW, CSEM_REG_FAST_MEMORY + 0x25c0 + 0x900, 0x83bd3}, 1124 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x7020, 0xc8},
1125 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3070, 0x80},
1126 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x7000, 0x2},
1127 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x4280, 0x4},
1128 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0},
1129 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240},
1130 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0},
1131 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a2},
1132 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4070, 0x80},
1133 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x5280, 0x4},
1134 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6280, 0x240},
1135 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b88, 0x2002be},
669 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff}, 1136 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
670 {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c00, 0x103bdb}, 1137 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002aa},
1138 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002de},
671 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0}, 1139 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
672 {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c40, 0x103beb}, 1140 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ba},
673 {OP_ZP, CSEM_REG_INT_TABLE, 0x5f3bfb}, 1141 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ee},
674 {OP_ZP, CSEM_REG_PRAM, 0x32423c13}, 1142 {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x6e0000},
675 {OP_ZP, CSEM_REG_PRAM + 0x8000, 0xf2148a4}, 1143 {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x6f0000},
676 {OP_ZP, CSEM_REG_PRAM + 0x10000, 0x5f4c6d}, 1144 {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002ca},
677 {OP_ZP, CSEM_REG_PRAM + 0x18000, 0x5f4c85}, 1145 {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x1002fe},
678 {OP_ZP, CSEM_REG_PRAM + 0x20000, 0x5f4c9d}, 1146 {OP_ZP_E1, CSEM_REG_PRAM, 0x32580000},
679 {OP_ZP, CSEM_REG_PRAM + 0x28000, 0x5f4cb5}, 1147 {OP_ZP_E1H, CSEM_REG_PRAM, 0x31fa0000},
680 {OP_ZP, CSEM_REG_PRAM + 0x30000, 0x5f4ccd}, 1148 {OP_ZP_E1, CSEM_REG_PRAM + 0x8000, 0x18270c96},
681 {OP_ZP, CSEM_REG_PRAM + 0x38000, 0x5f4ce5}, 1149 {OP_ZP_E1H, CSEM_REG_PRAM + 0x8000, 0x19040c7f},
682#define CSEM_COMMON_END 609 1150 {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402cc},
683#define CSEM_PORT0_START 609 1151 {OP_WR_64_E1H, CSEM_REG_PRAM + 0xb430, 0x67e00300},
684 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0}, 1152#define CSEM_COMMON_END 981
685 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1900, 0x10}, 1153#define CSEM_PORT0_START 981
686 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1980, 0x30}, 1154 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0},
687 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2300, 0x2}, 1155 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0},
688 {OP_SW, CSEM_REG_FAST_MEMORY + 0x2300 + 0x8, 0x24cfd}, 1156 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10},
689 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3040, 0x6}, 1157 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8500, 0x40},
690 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2410, 0x30}, 1158 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1980, 0x30},
691#define CSEM_PORT0_END 616 1159 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8700, 0x3c},
692#define CSEM_PORT1_START 616 1160 {OP_WR_E1, CSEM_REG_FAST_MEMORY + 0x5118, 0x0},
693 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0}, 1161 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4040, 0x6},
694 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1940, 0x10}, 1162 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2300, 0xe},
695 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1a40, 0x30}, 1163 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30},
696 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2310, 0x2}, 1164 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6},
697 {OP_SW, CSEM_REG_FAST_MEMORY + 0x2310 + 0x8, 0x24cff}, 1165 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30},
698 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3058, 0x6}, 1166#define CSEM_PORT0_END 993
699 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30}, 1167#define CSEM_PORT1_START 993
700#define CSEM_PORT1_END 623 1168 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0},
701#define XPB_COMMON_START 623 1169 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0},
1170 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10},
1171 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8600, 0x40},
1172 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1a40, 0x30},
1173 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x87f0, 0x3c},
1174 {OP_WR_E1, CSEM_REG_FAST_MEMORY + 0x511c, 0x0},
1175 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4058, 0x6},
1176 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2338, 0xe},
1177 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30},
1178 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6},
1179 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30},
1180#define CSEM_PORT1_END 1005
1181#define CSEM_FUNC0_START 1005
1182 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0},
1183 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2},
1184#define CSEM_FUNC0_END 1007
1185#define CSEM_FUNC1_START 1007
1186 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0},
1187 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2},
1188#define CSEM_FUNC1_END 1009
1189#define CSEM_FUNC2_START 1009
1190 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0},
1191 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2},
1192#define CSEM_FUNC2_END 1011
1193#define CSEM_FUNC3_START 1011
1194 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0},
1195 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2},
1196#define CSEM_FUNC3_END 1013
1197#define CSEM_FUNC4_START 1013
1198 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0},
1199 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2},
1200#define CSEM_FUNC4_END 1015
1201#define CSEM_FUNC5_START 1015
1202 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0},
1203 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2},
1204#define CSEM_FUNC5_END 1017
1205#define CSEM_FUNC6_START 1017
1206 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0},
1207 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2},
1208#define CSEM_FUNC6_END 1019
1209#define CSEM_FUNC7_START 1019
1210 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0},
1211 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2},
1212#define CSEM_FUNC7_END 1021
1213#define XPB_COMMON_START 1021
702 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20}, 1214 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20},
703#define XPB_COMMON_END 624 1215#define XPB_COMMON_END 1022
704#define DQ_COMMON_START 624 1216#define DQ_COMMON_START 1022
705 {OP_WR, DORQ_REG_MODE_ACT, 0x2}, 1217 {OP_WR, DORQ_REG_MODE_ACT, 0x2},
706 {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3}, 1218 {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
707 {OP_WR, DORQ_REG_OUTST_REQ, 0x4}, 1219 {OP_WR, DORQ_REG_OUTST_REQ, 0x4},
@@ -720,8 +1232,8 @@ static const struct raw_op init_ops[] = {
720 {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c}, 1232 {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
721 {OP_WR, DORQ_REG_REGN, 0x7c1004}, 1233 {OP_WR, DORQ_REG_REGN, 0x7c1004},
722 {OP_WR, DORQ_REG_IF_EN, 0xf}, 1234 {OP_WR, DORQ_REG_IF_EN, 0xf},
723#define DQ_COMMON_END 642 1235#define DQ_COMMON_END 1040
724#define TIMERS_COMMON_START 642 1236#define TIMERS_COMMON_START 1040
725 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2}, 1237 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
726 {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c}, 1238 {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
727 {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1}, 1239 {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
@@ -730,8 +1242,11 @@ static const struct raw_op init_ops[] = {
730 {OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1}, 1242 {OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1},
731 {OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1}, 1243 {OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1},
732 {OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1}, 1244 {OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1},
733 {OP_WR, TM_REG_PCIARB_CRDCNT_VAL, 0x2}, 1245 {OP_WR_E1, TM_REG_PCIARB_CRDCNT_VAL, 0x1},
734 {OP_WR, TM_REG_TIMER_TICK_SIZE, 0x3d090}, 1246 {OP_WR_E1H, TM_REG_PCIARB_CRDCNT_VAL, 0x2},
1247 {OP_WR_ASIC, TM_REG_TIMER_TICK_SIZE, 0x3d090},
1248 {OP_WR_EMUL, TM_REG_TIMER_TICK_SIZE, 0x9c},
1249 {OP_WR_FPGA, TM_REG_TIMER_TICK_SIZE, 0x9c4},
735 {OP_WR, TM_REG_CL0_CONT_REGION, 0x8}, 1250 {OP_WR, TM_REG_CL0_CONT_REGION, 0x8},
736 {OP_WR, TM_REG_CL1_CONT_REGION, 0xc}, 1251 {OP_WR, TM_REG_CL1_CONT_REGION, 0xc},
737 {OP_WR, TM_REG_CL2_CONT_REGION, 0x10}, 1252 {OP_WR, TM_REG_CL2_CONT_REGION, 0x10},
@@ -741,24 +1256,37 @@ static const struct raw_op init_ops[] = {
741 {OP_WR, TM_REG_EN_CL0_INPUT, 0x1}, 1256 {OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
742 {OP_WR, TM_REG_EN_CL1_INPUT, 0x1}, 1257 {OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
743 {OP_WR, TM_REG_EN_CL2_INPUT, 0x1}, 1258 {OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
744#define TIMERS_COMMON_END 661 1259#define TIMERS_COMMON_END 1062
745#define TIMERS_PORT0_START 661 1260#define TIMERS_PORT0_START 1062
746 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2}, 1261 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
747#define TIMERS_PORT0_END 662 1262#define TIMERS_PORT0_END 1063
748#define TIMERS_PORT1_START 662 1263#define TIMERS_PORT1_START 1063
749 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2}, 1264 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
750#define TIMERS_PORT1_END 663 1265#define TIMERS_PORT1_END 1064
751#define XSDM_COMMON_START 663 1266#define XSDM_COMMON_START 1064
752 {OP_WR, XSDM_REG_CFC_RSP_START_ADDR, 0xa14}, 1267 {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614},
753 {OP_WR, XSDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, 1268 {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424},
754 {OP_WR, XSDM_REG_Q_COUNTER_START_ADDR, 0xa04}, 1269 {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600},
1270 {OP_WR_E1H, XSDM_REG_CMP_COUNTER_START_ADDR, 0x410},
1271 {OP_WR_E1, XSDM_REG_Q_COUNTER_START_ADDR, 0x604},
1272 {OP_WR_E1H, XSDM_REG_Q_COUNTER_START_ADDR, 0x414},
755 {OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff}, 1273 {OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff},
756 {OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff}, 1274 {OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff},
757 {OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff}, 1275 {OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff},
758 {OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff}, 1276 {OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff},
759 {OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20}, 1277 {OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20},
760 {OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20}, 1278 {OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20},
761 {OP_ZR, XSDM_REG_AGG_INT_EVENT_2, 0x5e}, 1279 {OP_WR, XSDM_REG_AGG_INT_EVENT_2, 0x34},
1280 {OP_WR, XSDM_REG_AGG_INT_EVENT_3, 0x35},
1281 {OP_WR, XSDM_REG_AGG_INT_EVENT_4, 0x23},
1282 {OP_WR, XSDM_REG_AGG_INT_EVENT_5, 0x24},
1283 {OP_WR, XSDM_REG_AGG_INT_EVENT_6, 0x25},
1284 {OP_WR, XSDM_REG_AGG_INT_EVENT_7, 0x26},
1285 {OP_WR, XSDM_REG_AGG_INT_EVENT_8, 0x27},
1286 {OP_WR, XSDM_REG_AGG_INT_EVENT_9, 0x29},
1287 {OP_WR, XSDM_REG_AGG_INT_EVENT_10, 0x2a},
1288 {OP_WR, XSDM_REG_AGG_INT_EVENT_11, 0x2b},
1289 {OP_ZR, XSDM_REG_AGG_INT_EVENT_12, 0x54},
762 {OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1}, 1290 {OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1},
763 {OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f}, 1291 {OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f},
764 {OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff}, 1292 {OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff},
@@ -779,9 +1307,12 @@ static const struct raw_op init_ops[] = {
779 {OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, 1307 {OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
780 {OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, 1308 {OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
781 {OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, 1309 {OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
782 {OP_WR, XSDM_REG_TIMER_TICK, 0x3e8}, 1310 {OP_WR_E1, XSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
783#define XSDM_COMMON_END 694 1311 {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
784#define QM_COMMON_START 694 1312 {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
1313 {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
1314#define XSDM_COMMON_END 1111
1315#define QM_COMMON_START 1111
785 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6}, 1316 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
786 {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5}, 1317 {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
787 {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa}, 1318 {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
@@ -820,13 +1351,27 @@ static const struct raw_op init_ops[] = {
820 {OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120}, 1351 {OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120},
821 {OP_ZR, QM_REG_QVOQIDX_17, 0x4}, 1352 {OP_ZR, QM_REG_QVOQIDX_17, 0x4},
822 {OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101}, 1353 {OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101},
823 {OP_ZR, QM_REG_QVOQIDX_21, 0x4}, 1354 {OP_ZR_E1, QM_REG_QVOQIDX_21, 0x4},
824 {OP_WR, QM_REG_WRRWEIGHTS_5, 0x1010101}, 1355 {OP_WR_E1H, QM_REG_QVOQIDX_21, 0x0},
825 {OP_ZR, QM_REG_QVOQIDX_25, 0x4}, 1356 {OP_WR_E1, QM_REG_WRRWEIGHTS_5, 0x1010101},
826 {OP_WR, QM_REG_WRRWEIGHTS_6, 0x1010101}, 1357 {OP_WR_E1H, QM_REG_QVOQIDX_22, 0x4},
827 {OP_ZR, QM_REG_QVOQIDX_29, 0x3}, 1358 {OP_ZR_E1, QM_REG_QVOQIDX_25, 0x4},
1359 {OP_WR_E1H, QM_REG_QVOQIDX_23, 0x4},
1360 {OP_WR_E1, QM_REG_WRRWEIGHTS_6, 0x1010101},
1361 {OP_WR_E1H, QM_REG_QVOQIDX_24, 0x2},
1362 {OP_ZR_E1, QM_REG_QVOQIDX_29, 0x3},
1363 {OP_WR_E1H, QM_REG_WRRWEIGHTS_5, 0x8012004},
1364 {OP_WR_E1H, QM_REG_QVOQIDX_25, 0x5},
1365 {OP_WR_E1H, QM_REG_QVOQIDX_26, 0x5},
1366 {OP_WR_E1H, QM_REG_QVOQIDX_27, 0x5},
1367 {OP_WR_E1H, QM_REG_QVOQIDX_28, 0x5},
1368 {OP_WR_E1H, QM_REG_WRRWEIGHTS_6, 0x20081001},
1369 {OP_WR_E1H, QM_REG_QVOQIDX_29, 0x8},
1370 {OP_WR_E1H, QM_REG_QVOQIDX_30, 0x6},
1371 {OP_WR_E1H, QM_REG_QVOQIDX_31, 0x7},
828 {OP_WR, QM_REG_QVOQIDX_32, 0x1}, 1372 {OP_WR, QM_REG_QVOQIDX_32, 0x1},
829 {OP_WR, QM_REG_WRRWEIGHTS_7, 0x1010101}, 1373 {OP_WR_E1, QM_REG_WRRWEIGHTS_7, 0x1010101},
1374 {OP_WR_E1H, QM_REG_WRRWEIGHTS_7, 0x1010120},
830 {OP_WR, QM_REG_QVOQIDX_33, 0x1}, 1375 {OP_WR, QM_REG_QVOQIDX_33, 0x1},
831 {OP_WR, QM_REG_QVOQIDX_34, 0x1}, 1376 {OP_WR, QM_REG_QVOQIDX_34, 0x1},
832 {OP_WR, QM_REG_QVOQIDX_35, 0x1}, 1377 {OP_WR, QM_REG_QVOQIDX_35, 0x1},
@@ -853,36 +1398,169 @@ static const struct raw_op init_ops[] = {
853 {OP_WR, QM_REG_QVOQIDX_52, 0x1}, 1398 {OP_WR, QM_REG_QVOQIDX_52, 0x1},
854 {OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101}, 1399 {OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101},
855 {OP_WR, QM_REG_QVOQIDX_53, 0x1}, 1400 {OP_WR, QM_REG_QVOQIDX_53, 0x1},
856 {OP_WR, QM_REG_QVOQIDX_54, 0x1}, 1401 {OP_WR_E1, QM_REG_QVOQIDX_54, 0x1},
857 {OP_WR, QM_REG_QVOQIDX_55, 0x1}, 1402 {OP_WR_E1H, QM_REG_QVOQIDX_54, 0x4},
858 {OP_WR, QM_REG_QVOQIDX_56, 0x1}, 1403 {OP_WR_E1, QM_REG_QVOQIDX_55, 0x1},
859 {OP_WR, QM_REG_WRRWEIGHTS_13, 0x1010101}, 1404 {OP_WR_E1H, QM_REG_QVOQIDX_55, 0x4},
860 {OP_WR, QM_REG_QVOQIDX_57, 0x1}, 1405 {OP_WR_E1, QM_REG_QVOQIDX_56, 0x1},
861 {OP_WR, QM_REG_QVOQIDX_58, 0x1}, 1406 {OP_WR_E1H, QM_REG_QVOQIDX_56, 0x2},
862 {OP_WR, QM_REG_QVOQIDX_59, 0x1}, 1407 {OP_WR_E1, QM_REG_WRRWEIGHTS_13, 0x1010101},
863 {OP_WR, QM_REG_QVOQIDX_60, 0x1}, 1408 {OP_WR_E1H, QM_REG_WRRWEIGHTS_13, 0x8012004},
864 {OP_WR, QM_REG_WRRWEIGHTS_14, 0x1010101}, 1409 {OP_WR_E1, QM_REG_QVOQIDX_57, 0x1},
865 {OP_WR, QM_REG_QVOQIDX_61, 0x1}, 1410 {OP_WR_E1H, QM_REG_QVOQIDX_57, 0x5},
866 {OP_WR, QM_REG_QVOQIDX_62, 0x1}, 1411 {OP_WR_E1, QM_REG_QVOQIDX_58, 0x1},
867 {OP_WR, QM_REG_QVOQIDX_63, 0x1}, 1412 {OP_WR_E1H, QM_REG_QVOQIDX_58, 0x5},
868 {OP_WR, QM_REG_WRRWEIGHTS_15, 0x1010101}, 1413 {OP_WR_E1, QM_REG_QVOQIDX_59, 0x1},
869 {OP_WR, QM_REG_VOQQMASK_0_LSB, 0xffff003f}, 1414 {OP_WR_E1H, QM_REG_QVOQIDX_59, 0x5},
870 {OP_ZR, QM_REG_VOQQMASK_0_MSB, 0x2}, 1415 {OP_WR_E1, QM_REG_QVOQIDX_60, 0x1},
871 {OP_WR, QM_REG_VOQQMASK_1_MSB, 0xffff003f}, 1416 {OP_WR_E1H, QM_REG_QVOQIDX_60, 0x5},
872 {OP_WR, QM_REG_VOQQMASK_2_LSB, 0x100}, 1417 {OP_WR_E1, QM_REG_WRRWEIGHTS_14, 0x1010101},
873 {OP_WR, QM_REG_VOQQMASK_2_MSB, 0x100}, 1418 {OP_WR_E1H, QM_REG_WRRWEIGHTS_14, 0x20081001},
1419 {OP_WR_E1, QM_REG_QVOQIDX_61, 0x1},
1420 {OP_WR_E1H, QM_REG_QVOQIDX_61, 0x8},
1421 {OP_WR_E1, QM_REG_QVOQIDX_62, 0x1},
1422 {OP_WR_E1H, QM_REG_QVOQIDX_62, 0x6},
1423 {OP_WR_E1, QM_REG_QVOQIDX_63, 0x1},
1424 {OP_WR_E1H, QM_REG_QVOQIDX_63, 0x7},
1425 {OP_WR_E1, QM_REG_WRRWEIGHTS_15, 0x1010101},
1426 {OP_WR_E1H, QM_REG_QVOQIDX_64, 0x0},
1427 {OP_WR_E1, QM_REG_VOQQMASK_0_LSB, 0xffff003f},
1428 {OP_WR_E1H, QM_REG_WRRWEIGHTS_15, 0x1010120},
1429 {OP_ZR_E1, QM_REG_VOQQMASK_0_MSB, 0x2},
1430 {OP_ZR_E1H, QM_REG_QVOQIDX_65, 0x4},
1431 {OP_WR_E1, QM_REG_VOQQMASK_1_MSB, 0xffff003f},
1432 {OP_WR_E1H, QM_REG_WRRWEIGHTS_16, 0x1010101},
1433 {OP_WR_E1, QM_REG_VOQQMASK_2_LSB, 0x100},
1434 {OP_WR_E1H, QM_REG_QVOQIDX_69, 0x0},
1435 {OP_WR_E1, QM_REG_VOQQMASK_2_MSB, 0x100},
1436 {OP_WR_E1H, QM_REG_QVOQIDX_70, 0x4},
1437 {OP_WR_E1H, QM_REG_QVOQIDX_71, 0x4},
1438 {OP_WR_E1H, QM_REG_QVOQIDX_72, 0x2},
1439 {OP_WR_E1H, QM_REG_WRRWEIGHTS_17, 0x8012004},
1440 {OP_WR_E1H, QM_REG_QVOQIDX_73, 0x5},
1441 {OP_WR_E1H, QM_REG_QVOQIDX_74, 0x5},
1442 {OP_WR_E1H, QM_REG_QVOQIDX_75, 0x5},
1443 {OP_WR_E1H, QM_REG_QVOQIDX_76, 0x5},
1444 {OP_WR_E1H, QM_REG_WRRWEIGHTS_18, 0x20081001},
1445 {OP_WR_E1H, QM_REG_QVOQIDX_77, 0x8},
1446 {OP_WR_E1H, QM_REG_QVOQIDX_78, 0x6},
1447 {OP_WR_E1H, QM_REG_QVOQIDX_79, 0x7},
1448 {OP_WR_E1H, QM_REG_QVOQIDX_80, 0x0},
1449 {OP_WR_E1H, QM_REG_WRRWEIGHTS_19, 0x1010120},
1450 {OP_ZR_E1H, QM_REG_QVOQIDX_81, 0x4},
1451 {OP_WR_E1H, QM_REG_WRRWEIGHTS_20, 0x1010101},
1452 {OP_WR_E1H, QM_REG_QVOQIDX_85, 0x0},
1453 {OP_WR_E1H, QM_REG_QVOQIDX_86, 0x4},
1454 {OP_WR_E1H, QM_REG_QVOQIDX_87, 0x4},
1455 {OP_WR_E1H, QM_REG_QVOQIDX_88, 0x2},
1456 {OP_WR_E1H, QM_REG_WRRWEIGHTS_21, 0x8012004},
1457 {OP_WR_E1H, QM_REG_QVOQIDX_89, 0x5},
1458 {OP_WR_E1H, QM_REG_QVOQIDX_90, 0x5},
1459 {OP_WR_E1H, QM_REG_QVOQIDX_91, 0x5},
1460 {OP_WR_E1H, QM_REG_QVOQIDX_92, 0x5},
1461 {OP_WR_E1H, QM_REG_WRRWEIGHTS_22, 0x20081001},
1462 {OP_WR_E1H, QM_REG_QVOQIDX_93, 0x8},
1463 {OP_WR_E1H, QM_REG_QVOQIDX_94, 0x6},
1464 {OP_WR_E1H, QM_REG_QVOQIDX_95, 0x7},
1465 {OP_WR_E1H, QM_REG_QVOQIDX_96, 0x1},
1466 {OP_WR_E1H, QM_REG_WRRWEIGHTS_23, 0x1010120},
1467 {OP_WR_E1H, QM_REG_QVOQIDX_97, 0x1},
1468 {OP_WR_E1H, QM_REG_QVOQIDX_98, 0x1},
1469 {OP_WR_E1H, QM_REG_QVOQIDX_99, 0x1},
1470 {OP_WR_E1H, QM_REG_QVOQIDX_100, 0x1},
1471 {OP_WR_E1H, QM_REG_WRRWEIGHTS_24, 0x1010101},
1472 {OP_WR_E1H, QM_REG_QVOQIDX_101, 0x1},
1473 {OP_WR_E1H, QM_REG_QVOQIDX_102, 0x4},
1474 {OP_WR_E1H, QM_REG_QVOQIDX_103, 0x4},
1475 {OP_WR_E1H, QM_REG_QVOQIDX_104, 0x2},
1476 {OP_WR_E1H, QM_REG_WRRWEIGHTS_25, 0x8012004},
1477 {OP_WR_E1H, QM_REG_QVOQIDX_105, 0x5},
1478 {OP_WR_E1H, QM_REG_QVOQIDX_106, 0x5},
1479 {OP_WR_E1H, QM_REG_QVOQIDX_107, 0x5},
1480 {OP_WR_E1H, QM_REG_QVOQIDX_108, 0x5},
1481 {OP_WR_E1H, QM_REG_WRRWEIGHTS_26, 0x20081001},
1482 {OP_WR_E1H, QM_REG_QVOQIDX_109, 0x8},
1483 {OP_WR_E1H, QM_REG_QVOQIDX_110, 0x6},
1484 {OP_WR_E1H, QM_REG_QVOQIDX_111, 0x7},
1485 {OP_WR_E1H, QM_REG_QVOQIDX_112, 0x1},
1486 {OP_WR_E1H, QM_REG_WRRWEIGHTS_27, 0x1010120},
1487 {OP_WR_E1H, QM_REG_QVOQIDX_113, 0x1},
1488 {OP_WR_E1H, QM_REG_QVOQIDX_114, 0x1},
1489 {OP_WR_E1H, QM_REG_QVOQIDX_115, 0x1},
1490 {OP_WR_E1H, QM_REG_QVOQIDX_116, 0x1},
1491 {OP_WR_E1H, QM_REG_WRRWEIGHTS_28, 0x1010101},
1492 {OP_WR_E1H, QM_REG_QVOQIDX_117, 0x1},
1493 {OP_WR_E1H, QM_REG_QVOQIDX_118, 0x4},
1494 {OP_WR_E1H, QM_REG_QVOQIDX_119, 0x4},
1495 {OP_WR_E1H, QM_REG_QVOQIDX_120, 0x2},
1496 {OP_WR_E1H, QM_REG_WRRWEIGHTS_29, 0x8012004},
1497 {OP_WR_E1H, QM_REG_QVOQIDX_121, 0x5},
1498 {OP_WR_E1H, QM_REG_QVOQIDX_122, 0x5},
1499 {OP_WR_E1H, QM_REG_QVOQIDX_123, 0x5},
1500 {OP_WR_E1H, QM_REG_QVOQIDX_124, 0x5},
1501 {OP_WR_E1H, QM_REG_WRRWEIGHTS_30, 0x20081001},
1502 {OP_WR_E1H, QM_REG_QVOQIDX_125, 0x8},
1503 {OP_WR_E1H, QM_REG_QVOQIDX_126, 0x6},
1504 {OP_WR_E1H, QM_REG_QVOQIDX_127, 0x7},
1505 {OP_WR_E1H, QM_REG_WRRWEIGHTS_31, 0x1010120},
1506 {OP_WR_E1H, QM_REG_VOQQMASK_0_LSB, 0x3f003f},
1507 {OP_WR_E1H, QM_REG_VOQQMASK_0_MSB, 0x0},
1508 {OP_WR_E1H, QM_REG_VOQQMASK_0_LSB_EXT_A, 0x3f003f},
1509 {OP_WR_E1H, QM_REG_VOQQMASK_0_MSB_EXT_A, 0x0},
1510 {OP_WR_E1H, QM_REG_VOQQMASK_1_LSB, 0x0},
1511 {OP_WR_E1H, QM_REG_VOQQMASK_1_MSB, 0x3f003f},
1512 {OP_WR_E1H, QM_REG_VOQQMASK_1_LSB_EXT_A, 0x0},
1513 {OP_WR_E1H, QM_REG_VOQQMASK_1_MSB_EXT_A, 0x3f003f},
1514 {OP_WR_E1H, QM_REG_VOQQMASK_2_LSB, 0x1000100},
1515 {OP_WR_E1H, QM_REG_VOQQMASK_2_MSB, 0x1000100},
1516 {OP_WR_E1H, QM_REG_VOQQMASK_2_LSB_EXT_A, 0x1000100},
1517 {OP_WR_E1H, QM_REG_VOQQMASK_2_MSB_EXT_A, 0x1000100},
874 {OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2}, 1518 {OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2},
875 {OP_WR, QM_REG_VOQQMASK_4_LSB, 0xc0}, 1519 {OP_WR_E1, QM_REG_VOQQMASK_4_LSB, 0xc0},
876 {OP_WR, QM_REG_VOQQMASK_4_MSB, 0xc0}, 1520 {OP_WR_E1H, QM_REG_VOQQMASK_3_LSB_EXT_A, 0x0},
877 {OP_WR, QM_REG_VOQQMASK_5_LSB, 0x1e00}, 1521 {OP_WR_E1, QM_REG_VOQQMASK_4_MSB, 0xc0},
878 {OP_WR, QM_REG_VOQQMASK_5_MSB, 0x1e00}, 1522 {OP_WR_E1H, QM_REG_VOQQMASK_3_MSB_EXT_A, 0x0},
879 {OP_WR, QM_REG_VOQQMASK_6_LSB, 0x4000}, 1523 {OP_WR_E1, QM_REG_VOQQMASK_5_LSB, 0x1e00},
880 {OP_WR, QM_REG_VOQQMASK_6_MSB, 0x4000}, 1524 {OP_WR_E1H, QM_REG_VOQQMASK_4_LSB, 0xc000c0},
881 {OP_WR, QM_REG_VOQQMASK_7_LSB, 0x8000}, 1525 {OP_WR_E1, QM_REG_VOQQMASK_5_MSB, 0x1e00},
882 {OP_WR, QM_REG_VOQQMASK_7_MSB, 0x8000}, 1526 {OP_WR_E1H, QM_REG_VOQQMASK_4_MSB, 0xc000c0},
883 {OP_WR, QM_REG_VOQQMASK_8_LSB, 0x2000}, 1527 {OP_WR_E1, QM_REG_VOQQMASK_6_LSB, 0x4000},
884 {OP_WR, QM_REG_VOQQMASK_8_MSB, 0x2000}, 1528 {OP_WR_E1H, QM_REG_VOQQMASK_4_LSB_EXT_A, 0xc000c0},
885 {OP_ZR, QM_REG_VOQQMASK_9_LSB, 0x7}, 1529 {OP_WR_E1, QM_REG_VOQQMASK_6_MSB, 0x4000},
1530 {OP_WR_E1H, QM_REG_VOQQMASK_4_MSB_EXT_A, 0xc000c0},
1531 {OP_WR_E1, QM_REG_VOQQMASK_7_LSB, 0x8000},
1532 {OP_WR_E1H, QM_REG_VOQQMASK_5_LSB, 0x1e001e00},
1533 {OP_WR_E1, QM_REG_VOQQMASK_7_MSB, 0x8000},
1534 {OP_WR_E1H, QM_REG_VOQQMASK_5_MSB, 0x1e001e00},
1535 {OP_WR_E1, QM_REG_VOQQMASK_8_LSB, 0x2000},
1536 {OP_WR_E1H, QM_REG_VOQQMASK_5_LSB_EXT_A, 0x1e001e00},
1537 {OP_WR_E1, QM_REG_VOQQMASK_8_MSB, 0x2000},
1538 {OP_WR_E1H, QM_REG_VOQQMASK_5_MSB_EXT_A, 0x1e001e00},
1539 {OP_ZR_E1, QM_REG_VOQQMASK_9_LSB, 0x7},
1540 {OP_WR_E1H, QM_REG_VOQQMASK_6_LSB, 0x40004000},
1541 {OP_WR_E1H, QM_REG_VOQQMASK_6_MSB, 0x40004000},
1542 {OP_WR_E1H, QM_REG_VOQQMASK_6_LSB_EXT_A, 0x40004000},
1543 {OP_WR_E1H, QM_REG_VOQQMASK_6_MSB_EXT_A, 0x40004000},
1544 {OP_WR_E1H, QM_REG_VOQQMASK_7_LSB, 0x80008000},
1545 {OP_WR_E1H, QM_REG_VOQQMASK_7_MSB, 0x80008000},
1546 {OP_WR_E1H, QM_REG_VOQQMASK_7_LSB_EXT_A, 0x80008000},
1547 {OP_WR_E1H, QM_REG_VOQQMASK_7_MSB_EXT_A, 0x80008000},
1548 {OP_WR_E1H, QM_REG_VOQQMASK_8_LSB, 0x20002000},
1549 {OP_WR_E1H, QM_REG_VOQQMASK_8_MSB, 0x20002000},
1550 {OP_WR_E1H, QM_REG_VOQQMASK_8_LSB_EXT_A, 0x20002000},
1551 {OP_WR_E1H, QM_REG_VOQQMASK_8_MSB_EXT_A, 0x20002000},
1552 {OP_ZR_E1H, QM_REG_VOQQMASK_9_LSB, 0x2},
1553 {OP_WR_E1H, QM_REG_VOQQMASK_9_LSB_EXT_A, 0x0},
1554 {OP_WR_E1H, QM_REG_VOQQMASK_9_MSB_EXT_A, 0x0},
1555 {OP_WR_E1H, QM_REG_VOQQMASK_10_LSB, 0x0},
1556 {OP_WR_E1H, QM_REG_VOQQMASK_10_MSB, 0x0},
1557 {OP_WR_E1H, QM_REG_VOQQMASK_10_LSB_EXT_A, 0x0},
1558 {OP_WR_E1H, QM_REG_VOQQMASK_10_MSB_EXT_A, 0x0},
1559 {OP_WR_E1H, QM_REG_VOQQMASK_11_LSB, 0x0},
1560 {OP_WR_E1H, QM_REG_VOQQMASK_11_MSB, 0x0},
1561 {OP_WR_E1H, QM_REG_VOQQMASK_11_LSB_EXT_A, 0x0},
1562 {OP_WR_E1H, QM_REG_VOQQMASK_11_MSB_EXT_A, 0x0},
1563 {OP_WR_E1H, QM_REG_VOQPORT_0, 0x0},
886 {OP_WR, QM_REG_VOQPORT_1, 0x1}, 1564 {OP_WR, QM_REG_VOQPORT_1, 0x1},
887 {OP_ZR, QM_REG_VOQPORT_2, 0xa}, 1565 {OP_ZR, QM_REG_VOQPORT_2, 0xa},
888 {OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08}, 1566 {OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08},
@@ -893,8 +1571,12 @@ static const struct raw_op init_ops[] = {
893 {OP_WR, QM_REG_CMINTVOQMASK_5, 0x80}, 1571 {OP_WR, QM_REG_CMINTVOQMASK_5, 0x80},
894 {OP_WR, QM_REG_CMINTVOQMASK_6, 0x200}, 1572 {OP_WR, QM_REG_CMINTVOQMASK_6, 0x200},
895 {OP_WR, QM_REG_CMINTVOQMASK_7, 0x0}, 1573 {OP_WR, QM_REG_CMINTVOQMASK_7, 0x0},
896 {OP_WR, QM_REG_HWAEMPTYMASK_LSB, 0xffff01ff}, 1574 {OP_WR_E1, QM_REG_HWAEMPTYMASK_LSB, 0xffff01ff},
897 {OP_WR, QM_REG_HWAEMPTYMASK_MSB, 0xffff01ff}, 1575 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_LSB, 0x1ff01ff},
1576 {OP_WR_E1, QM_REG_HWAEMPTYMASK_MSB, 0xffff01ff},
1577 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_MSB, 0x1ff01ff},
1578 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_LSB_EXT_A, 0x1ff01ff},
1579 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_MSB_EXT_A, 0x1ff01ff},
898 {OP_WR, QM_REG_ENBYPVOQMASK, 0x13}, 1580 {OP_WR, QM_REG_ENBYPVOQMASK, 0x13},
899 {OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f}, 1581 {OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f},
900 {OP_WR, QM_REG_VOQINITCREDIT_0, 0x140}, 1582 {OP_WR, QM_REG_VOQINITCREDIT_0, 0x140},
@@ -910,15 +1592,29 @@ static const struct raw_op init_ops[] = {
910 {OP_WR, QM_REG_BYTECRDINITVAL, 0x8000}, 1592 {OP_WR, QM_REG_BYTECRDINITVAL, 0x8000},
911 {OP_WR, QM_REG_BYTECRDCOST, 0x25e4}, 1593 {OP_WR, QM_REG_BYTECRDCOST, 0x25e4},
912 {OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff}, 1594 {OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff},
913 {OP_WR, QM_REG_ENBYTECRD_LSB, 0x7}, 1595 {OP_WR_E1, QM_REG_ENBYTECRD_LSB, 0x7},
914 {OP_WR, QM_REG_ENBYTECRD_MSB, 0x7}, 1596 {OP_WR_E1H, QM_REG_ENBYTECRD_LSB, 0x70007},
1597 {OP_WR_E1, QM_REG_ENBYTECRD_MSB, 0x7},
1598 {OP_WR_E1H, QM_REG_ENBYTECRD_MSB, 0x70007},
1599 {OP_WR_E1H, QM_REG_ENBYTECRD_LSB_EXT_A, 0x70007},
1600 {OP_WR_E1H, QM_REG_ENBYTECRD_MSB_EXT_A, 0x70007},
915 {OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0}, 1601 {OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0},
916 {OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff}, 1602 {OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff},
917 {OP_WR, QM_REG_FUNCNUMSEL_LSB, 0x0}, 1603 {OP_WR_E1, QM_REG_FUNCNUMSEL_LSB, 0x0},
918 {OP_WR, QM_REG_FUNCNUMSEL_MSB, 0xffffffff}, 1604 {OP_WR_E1H, QM_REG_BYTECRDPORT_LSB_EXT_A, 0x0},
1605 {OP_WR_E1, QM_REG_FUNCNUMSEL_MSB, 0xffffffff},
1606 {OP_WR_E1H, QM_REG_BYTECRDPORT_MSB_EXT_A, 0xffffffff},
1607 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_0, 0x0},
1608 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_1, 0x2},
1609 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_2, 0x1},
1610 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_3, 0x3},
1611 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_4, 0x4},
1612 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_5, 0x6},
1613 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5},
1614 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7},
919 {OP_WR, QM_REG_CMINTEN, 0xff}, 1615 {OP_WR, QM_REG_CMINTEN, 0xff},
920#define QM_COMMON_END 829 1616#define QM_COMMON_END 1411
921#define PBF_COMMON_START 829 1617#define PBF_COMMON_START 1411
922 {OP_WR, PBF_REG_INIT, 0x1}, 1618 {OP_WR, PBF_REG_INIT, 0x1},
923 {OP_WR, PBF_REG_INIT_P4, 0x1}, 1619 {OP_WR, PBF_REG_INIT_P4, 0x1},
924 {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1}, 1620 {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
@@ -926,20 +1622,20 @@ static const struct raw_op init_ops[] = {
926 {OP_WR, PBF_REG_INIT_P4, 0x0}, 1622 {OP_WR, PBF_REG_INIT_P4, 0x0},
927 {OP_WR, PBF_REG_INIT, 0x0}, 1623 {OP_WR, PBF_REG_INIT, 0x0},
928 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0}, 1624 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
929#define PBF_COMMON_END 836 1625#define PBF_COMMON_END 1418
930#define PBF_PORT0_START 836 1626#define PBF_PORT0_START 1418
931 {OP_WR, PBF_REG_INIT_P0, 0x1}, 1627 {OP_WR, PBF_REG_INIT_P0, 0x1},
932 {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1}, 1628 {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
933 {OP_WR, PBF_REG_INIT_P0, 0x0}, 1629 {OP_WR, PBF_REG_INIT_P0, 0x0},
934 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0}, 1630 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
935#define PBF_PORT0_END 840 1631#define PBF_PORT0_END 1422
936#define PBF_PORT1_START 840 1632#define PBF_PORT1_START 1422
937 {OP_WR, PBF_REG_INIT_P1, 0x1}, 1633 {OP_WR, PBF_REG_INIT_P1, 0x1},
938 {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1}, 1634 {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
939 {OP_WR, PBF_REG_INIT_P1, 0x0}, 1635 {OP_WR, PBF_REG_INIT_P1, 0x0},
940 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0}, 1636 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
941#define PBF_PORT1_END 844 1637#define PBF_PORT1_END 1426
942#define XCM_COMMON_START 844 1638#define XCM_COMMON_START 1426
943 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32}, 1639 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
944 {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020}, 1640 {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
945 {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020}, 1641 {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
@@ -971,14 +1667,18 @@ static const struct raw_op init_ops[] = {
971 {OP_WR, XCM_REG_TM_INIT_CRD, 0x4}, 1667 {OP_WR, XCM_REG_TM_INIT_CRD, 0x4},
972 {OP_WR, XCM_REG_XQM_INIT_CRD, 0x20}, 1668 {OP_WR, XCM_REG_XQM_INIT_CRD, 0x20},
973 {OP_WR, XCM_REG_XX_INIT_CRD, 0x2}, 1669 {OP_WR, XCM_REG_XX_INIT_CRD, 0x2},
974 {OP_WR, XCM_REG_XX_MSG_NUM, 0x1f}, 1670 {OP_WR_E1, XCM_REG_XX_MSG_NUM, 0x1f},
1671 {OP_WR_E1H, XCM_REG_XX_MSG_NUM, 0x20},
975 {OP_ZR, XCM_REG_XX_TABLE, 0x12}, 1672 {OP_ZR, XCM_REG_XX_TABLE, 0x12},
976 {OP_SW, XCM_REG_XX_DESCR_TABLE, 0x1f4d01}, 1673 {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02ce},
1674 {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0302},
977 {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf}, 1675 {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
978 {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7}, 1676 {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
979 {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb}, 1677 {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb},
980 {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe}, 1678 {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe},
981 {OP_ZR, XCM_REG_N_SM_CTX_LD_4, 0x4}, 1679 {OP_ZR_E1, XCM_REG_N_SM_CTX_LD_4, 0x4},
1680 {OP_WR_E1H, XCM_REG_N_SM_CTX_LD_4, 0xc},
1681 {OP_ZR_E1H, XCM_REG_N_SM_CTX_LD_5, 0x3},
982 {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4}, 1682 {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4},
983 {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1}, 1683 {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1},
984 {OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1}, 1684 {OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1},
@@ -1000,28 +1700,116 @@ static const struct raw_op init_ops[] = {
1000 {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1}, 1700 {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
1001 {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1}, 1701 {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
1002 {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1}, 1702 {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
1003#define XCM_COMMON_END 904 1703#define XCM_COMMON_END 1490
1004#define XCM_PORT0_START 904 1704#define XCM_PORT0_START 1490
1005 {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1705 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1006 {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1706 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1007 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1707 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1008 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0}, 1708 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1009 {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2}, 1709 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1010 {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2}, 1710 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1011 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1711 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1012 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1712 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1013#define XCM_PORT0_END 912 1713#define XCM_PORT0_END 1498
1014#define XCM_PORT1_START 912 1714#define XCM_PORT1_START 1498
1015 {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1715 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1016 {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1716 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1017 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1717 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1018 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0}, 1718 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1019 {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2}, 1719 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1020 {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2}, 1720 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1021 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1721 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1022 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1722 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1023#define XCM_PORT1_END 920 1723#define XCM_PORT1_END 1506
1024#define XSEM_COMMON_START 920 1724#define XCM_FUNC0_START 1506
1725 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1726 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1727 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1728 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1729 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1730 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1731 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1732 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1733 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1734#define XCM_FUNC0_END 1515
1735#define XCM_FUNC1_START 1515
1736 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1737 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1738 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1739 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1740 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1741 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1742 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1743 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1744 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1745#define XCM_FUNC1_END 1524
1746#define XCM_FUNC2_START 1524
1747 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1748 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1749 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1750 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1751 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1752 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1753 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1754 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1755 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1756#define XCM_FUNC2_END 1533
1757#define XCM_FUNC3_START 1533
1758 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1759 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1760 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1761 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1762 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1763 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1764 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1765 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1766 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1767#define XCM_FUNC3_END 1542
1768#define XCM_FUNC4_START 1542
1769 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1770 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1771 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1772 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1773 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1774 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1775 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1776 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1777 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1778#define XCM_FUNC4_END 1551
1779#define XCM_FUNC5_START 1551
1780 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1781 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1782 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1783 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1784 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1785 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1786 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1787 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1788 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1789#define XCM_FUNC5_END 1560
1790#define XCM_FUNC6_START 1560
1791 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1792 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1793 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1794 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1795 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1796 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1797 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1798 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1799 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1800#define XCM_FUNC6_END 1569
1801#define XCM_FUNC7_START 1569
1802 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1803 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1804 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1805 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1806 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1807 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1808 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1809 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1810 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1811#define XCM_FUNC7_END 1578
1812#define XSEM_COMMON_START 1578
1025 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0}, 1813 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
1026 {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0}, 1814 {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
1027 {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0}, 1815 {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -1065,157 +1853,402 @@ static const struct raw_op init_ops[] = {
1065 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18}, 1853 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18},
1066 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc}, 1854 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc},
1067 {OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66}, 1855 {OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66},
1068 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, 1856 {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
1857 {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18300, 0x138},
1858 {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
1069 {OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, 1859 {OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
1070 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4}, 1860 {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4},
1071 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, 1861 {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18340, 0x0},
1072 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x55d8, 0x2}, 1862 {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18340, 0x5},
1073 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x48}, 1863 {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
1074 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, 1864 {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
1075 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1000, 0x2}, 1865 {OP_WR_EMUL_E1H, XSEM_REG_FAST_MEMORY + 0x11480, 0x0},
1076 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5128, 0x92}, 1866 {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
1077 {OP_WR, XSEM_REG_FAST_MEMORY + 0x5378, 0x0}, 1867 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3d00, 0x4},
1078 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5380, 0x24d20}, 1868 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x11480, 0x1},
1079 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5428, 0x44d22}, 1869 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3000, 0x48},
1080 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1518, 0x1}, 1870 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x28a8, 0x4},
1081 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1830, 0x0}, 1871 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
1082 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1838, 0x0}, 1872 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2080, 0x48},
1083 {OP_SW, XSEM_REG_FAST_MEMORY + 0x1820, 0x24d26}, 1873 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1000, 0x2},
1084 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2}, 1874 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9020, 0xc8},
1085 {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ad8, 0x24d28}, 1875 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3128, 0x8e},
1086 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b08, 0x4}, 1876 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9000, 0x2},
1087 {OP_SW, XSEM_REG_FAST_MEMORY + 0x1f50, 0x24d2a}, 1877 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3368, 0x0},
1878 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86},
1879 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202ed},
1880 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2000, 0x20},
1881 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ef},
1882 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0},
1883 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1518, 0x1},
1884 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20321},
1885 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1830, 0x0},
1886 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x40323},
1887 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1838, 0x0},
1888 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ac8, 0x0},
1889 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f3},
1890 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ab8, 0x0},
1891 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2},
1892 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3010, 0x1},
1893 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4},
1894 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x4040, 0x10},
1895 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f5},
1896 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x100327},
1897 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2},
1898 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4},
1899 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x83b0, 0x20337},
1088 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0}, 1900 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
1089 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c00, 0x104d2c}, 1901 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f7},
1902 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100339},
1090 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, 1903 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
1091 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c40, 0x84d3c}, 1904 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80307},
1905 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80349},
1092 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000}, 1906 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
1093 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c60, 0x84d44}, 1907 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030f},
1094 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x3000000}, 1908 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80351},
1095 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c80, 0x84d4c}, 1909 {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xa90000},
1096 {OP_ZP, XSEM_REG_INT_TABLE, 0x814d54}, 1910 {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xac0000},
1097 {OP_ZP, XSEM_REG_PRAM, 0x35774d75}, 1911 {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130317},
1098 {OP_ZP, XSEM_REG_PRAM + 0x8000, 0x36525ad3}, 1912 {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x368, 0x130359},
1099 {OP_ZP, XSEM_REG_PRAM + 0x10000, 0x27266868}, 1913 {OP_ZP_E1, XSEM_REG_PRAM, 0x344e0000},
1100 {OP_ZP, XSEM_REG_PRAM + 0x18000, 0x5e7232}, 1914 {OP_ZP_E1H, XSEM_REG_PRAM, 0x34620000},
1101 {OP_ZP, XSEM_REG_PRAM + 0x20000, 0x5e724a}, 1915 {OP_ZP_E1, XSEM_REG_PRAM + 0x8000, 0x38840d14},
1102 {OP_ZP, XSEM_REG_PRAM + 0x28000, 0x5e7262}, 1916 {OP_ZP_E1H, XSEM_REG_PRAM + 0x8000, 0x38240d19},
1103 {OP_ZP, XSEM_REG_PRAM + 0x30000, 0x5e727a}, 1917 {OP_ZP_E1, XSEM_REG_PRAM + 0x10000, 0x3e711b35},
1104 {OP_ZP, XSEM_REG_PRAM + 0x38000, 0x5e7292}, 1918 {OP_ZP_E1H, XSEM_REG_PRAM + 0x10000, 0x3e971b22},
1105#define XSEM_COMMON_END 1000 1919 {OP_ZP_E1, XSEM_REG_PRAM + 0x18000, 0x1dd02ad2},
1106#define XSEM_PORT0_START 1000 1920 {OP_ZP_E1H, XSEM_REG_PRAM + 0x18000, 0x21542ac8},
1107 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1400, 0xa}, 1921 {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0d0, 0x47e60319},
1108 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1450, 0x6}, 1922 {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8d0, 0x46e6035b},
1109 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5388, 0xc}, 1923#define XSEM_COMMON_END 1688
1110 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5388 + 0x30, 0x272aa}, 1924#define XSEM_PORT0_START 1688
1111 {OP_SW, XSEM_REG_FAST_MEMORY + 0x55e0, 0x772ac}, 1925 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x10},
1112 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5600, 0x7}, 1926 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc},
1113 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1500, 0x0}, 1927 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c20, 0x1c},
1114 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1508, 0x1}, 1928 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24a8, 0x10},
1115 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3020, 0x2}, 1929 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1400, 0xa},
1116 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3030, 0x2}, 1930 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2528, 0x1c},
1117 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3000, 0x2}, 1931 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1450, 0x6},
1118 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3010, 0x2}, 1932 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2608, 0x1c},
1119 {OP_WR, XSEM_REG_FAST_MEMORY + 0x3040, 0x0}, 1933 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3378, 0xfc},
1120 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3048, 0xc}, 1934 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x26e8, 0x1c},
1121 {OP_SW, XSEM_REG_FAST_MEMORY + 0x3048 + 0x30, 0x272b3}, 1935 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b58, 0x0},
1122 {OP_WR, XSEM_REG_FAST_MEMORY + 0x30b8, 0x1}, 1936 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x27c8, 0x1c},
1123 {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x272b5}, 1937 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x10031b},
1124 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b18, 0x42}, 1938 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa000, 0x28},
1125 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d28, 0x4}, 1939 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1500, 0x0},
1126#define XSEM_PORT0_END 1019 1940 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa140, 0xc},
1127#define XSEM_PORT1_START 1019 1941 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1508, 0x1},
1128 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1428, 0xa}, 1942 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3000, 0x1},
1129 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1468, 0x6}, 1943 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5020, 0x2},
1130 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x53c0, 0xc}, 1944 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5030, 0x2},
1131 {OP_SW, XSEM_REG_FAST_MEMORY + 0x53c0 + 0x30, 0x272b7}, 1945 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x2},
1132 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5620, 0x772b9}, 1946 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5010, 0x2},
1133 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5640, 0x7}, 1947 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x5040, 0x0},
1134 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1504, 0x0}, 1948 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x5208, 0x1},
1135 {OP_WR, XSEM_REG_FAST_MEMORY + 0x150c, 0x1}, 1949 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
1136 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3028, 0x2}, 1950 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2035d},
1137 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3038, 0x2}, 1951 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1},
1138 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3008, 0x2}, 1952 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42},
1139 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3018, 0x2}, 1953 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x2032b},
1140 {OP_WR, XSEM_REG_FAST_MEMORY + 0x3044, 0x0}, 1954 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4},
1141 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3080, 0xc}, 1955 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42},
1142 {OP_SW, XSEM_REG_FAST_MEMORY + 0x3080 + 0x30, 0x272c0}, 1956 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4},
1143 {OP_WR, XSEM_REG_FAST_MEMORY + 0x30bc, 0x1}, 1957#define XSEM_PORT0_END 1720
1144 {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x272c2}, 1958#define XSEM_PORT1_START 1720
1145 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4c20, 0x42}, 1959 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3be0, 0x10},
1146 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d38, 0x4}, 1960 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc},
1147#define XSEM_PORT1_END 1038 1961 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c90, 0x1c},
1148#define CDU_COMMON_START 1038 1962 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24e8, 0x10},
1963 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1428, 0xa},
1964 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2598, 0x1c},
1965 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1468, 0x6},
1966 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2678, 0x1c},
1967 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3768, 0xfc},
1968 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2758, 0x1c},
1969 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b5c, 0x0},
1970 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2838, 0x1c},
1971 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032d},
1972 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28},
1973 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1504, 0x0},
1974 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa170, 0xc},
1975 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x150c, 0x1},
1976 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3004, 0x1},
1977 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5028, 0x2},
1978 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5038, 0x2},
1979 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5008, 0x2},
1980 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5018, 0x2},
1981 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x5044, 0x0},
1982 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x520c, 0x1},
1983 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
1984 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x2035f},
1985 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1},
1986 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42},
1987 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033d},
1988 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4},
1989 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42},
1990 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4},
1991#define XSEM_PORT1_END 1752
1992#define XSEM_FUNC0_START 1752
1993 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0},
1994 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28b8, 0x100361},
1995 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
1996#define XSEM_FUNC0_END 1755
1997#define XSEM_FUNC1_START 1755
1998 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0},
1999 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28f8, 0x100371},
2000 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
2001#define XSEM_FUNC1_END 1758
2002#define XSEM_FUNC2_START 1758
2003 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0},
2004 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x100381},
2005 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe},
2006#define XSEM_FUNC2_END 1761
2007#define XSEM_FUNC3_START 1761
2008 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0},
2009 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2978, 0x100391},
2010 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe},
2011#define XSEM_FUNC3_END 1764
2012#define XSEM_FUNC4_START 1764
2013 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f0, 0x0},
2014 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29b8, 0x1003a1},
2015 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5128, 0xe},
2016#define XSEM_FUNC4_END 1767
2017#define XSEM_FUNC5_START 1767
2018 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f4, 0x0},
2019 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29f8, 0x1003b1},
2020 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5160, 0xe},
2021#define XSEM_FUNC5_END 1770
2022#define XSEM_FUNC6_START 1770
2023 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f8, 0x0},
2024 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a38, 0x1003c1},
2025 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5198, 0xe},
2026#define XSEM_FUNC6_END 1773
2027#define XSEM_FUNC7_START 1773
2028 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7fc, 0x0},
2029 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a78, 0x1003d1},
2030 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe},
2031#define XSEM_FUNC7_END 1776
2032#define CDU_COMMON_START 1776
1149 {OP_WR, CDU_REG_CDU_CONTROL0, 0x1}, 2033 {OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
2034 {OP_WR_E1H, CDU_REG_MF_MODE, 0x1},
1150 {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000}, 2035 {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
1151 {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d}, 2036 {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
1152 {OP_WB, CDU_REG_L1TT, 0x20072c4}, 2037 {OP_WB_E1, CDU_REG_L1TT, 0x200033f},
1153 {OP_WB, CDU_REG_MATT, 0x2074c4}, 2038 {OP_WB_E1H, CDU_REG_L1TT, 0x20003e1},
1154 {OP_ZR, CDU_REG_MATT + 0x80, 0x20}, 2039 {OP_WB_E1, CDU_REG_MATT, 0x20053f},
1155#define CDU_COMMON_END 1044 2040 {OP_WB_E1H, CDU_REG_MATT, 0x2805e1},
1156#define DMAE_COMMON_START 1044 2041 {OP_ZR_E1, CDU_REG_MATT + 0x80, 0x2},
2042 {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055f},
2043 {OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
2044#define CDU_COMMON_END 1787
2045#define DMAE_COMMON_START 1787
2046 {OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
1157 {OP_WR, DMAE_REG_CRC16C_INIT, 0x0}, 2047 {OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
1158 {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1}, 2048 {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
1159 {OP_WR, DMAE_REG_PXP_REQ_INIT_CRD, 0x2}, 2049 {OP_WR_E1, DMAE_REG_PXP_REQ_INIT_CRD, 0x1},
2050 {OP_WR_E1H, DMAE_REG_PXP_REQ_INIT_CRD, 0x2},
1160 {OP_WR, DMAE_REG_PCI_IFEN, 0x1}, 2051 {OP_WR, DMAE_REG_PCI_IFEN, 0x1},
1161 {OP_WR, DMAE_REG_GRC_IFEN, 0x1}, 2052 {OP_WR, DMAE_REG_GRC_IFEN, 0x1},
1162#define DMAE_COMMON_END 1049 2053#define DMAE_COMMON_END 1794
1163#define PXP_COMMON_START 1049 2054#define PXP_COMMON_START 1794
1164 {OP_SI, PXP_REG_HST_INBOUND_INT + 0x400, 0x574e4}, 2055 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50565},
1165 {OP_SI, PXP_REG_HST_INBOUND_INT + 0x420, 0x574e9}, 2056 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50609},
1166 {OP_SI, PXP_REG_HST_INBOUND_INT, 0x574ee}, 2057 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x5056a},
1167#define PXP_COMMON_END 1052 2058 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x5060e},
1168#define CFC_COMMON_START 1052 2059 {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056f},
2060#define PXP_COMMON_END 1799
2061#define CFC_COMMON_START 1799
2062 {OP_ZR_E1H, CFC_REG_LINK_LIST, 0x100},
1169 {OP_WR, CFC_REG_CONTROL0, 0x10}, 2063 {OP_WR, CFC_REG_CONTROL0, 0x10},
1170 {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff}, 2064 {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
1171 {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a}, 2065 {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
1172#define CFC_COMMON_END 1055 2066#define CFC_COMMON_END 1803
1173#define HC_COMMON_START 1055 2067#define HC_COMMON_START 1803
1174 {OP_ZR, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4}, 2068 {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
1175#define HC_COMMON_END 1056 2069#define HC_COMMON_END 1804
1176#define HC_PORT0_START 1056 2070#define HC_PORT0_START 1804
1177 {OP_WR, HC_REG_CONFIG_0, 0x1080}, 2071 {OP_WR_E1, HC_REG_CONFIG_0, 0x1080},
1178 {OP_ZR, HC_REG_UC_RAM_ADDR_0, 0x2}, 2072 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2},
1179 {OP_WR, HC_REG_ATTN_NUM_P0, 0x10}, 2073 {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10},
1180 {OP_WR, HC_REG_LEADING_EDGE_0, 0xffff}, 2074 {OP_WR_E1, HC_REG_LEADING_EDGE_0, 0xffff},
1181 {OP_WR, HC_REG_TRAILING_EDGE_0, 0xffff}, 2075 {OP_WR_E1, HC_REG_TRAILING_EDGE_0, 0xffff},
1182 {OP_WR, HC_REG_AGG_INT_0, 0x0}, 2076 {OP_WR_E1, HC_REG_AGG_INT_0, 0x0},
1183 {OP_WR, HC_REG_ATTN_IDX, 0x0}, 2077 {OP_WR_E1, HC_REG_ATTN_IDX, 0x0},
1184 {OP_ZR, HC_REG_ATTN_BIT, 0x2}, 2078 {OP_ZR_E1, HC_REG_ATTN_BIT, 0x2},
1185 {OP_WR, HC_REG_VQID_0, 0x2b5}, 2079 {OP_WR_E1, HC_REG_VQID_0, 0x2b5},
1186 {OP_WR, HC_REG_PCI_CONFIG_0, 0x0}, 2080 {OP_WR_E1, HC_REG_PCI_CONFIG_0, 0x0},
1187 {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a}, 2081 {OP_ZR_E1, HC_REG_P0_PROD_CONS, 0x4a},
1188 {OP_ZR, HC_REG_PBA_COMMAND, 0x2}, 2082 {OP_WR_E1, HC_REG_INT_MASK, 0x1ffff},
1189 {OP_WR, HC_REG_INT_MASK, 0x1ffff}, 2083 {OP_ZR_E1, HC_REG_PBA_COMMAND, 0x2},
1190 {OP_WR, HC_REG_CONFIG_0, 0x1a82}, 2084 {OP_WR_E1, HC_REG_CONFIG_0, 0x1a80},
1191 {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24}, 2085 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS, 0x24},
1192 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2086 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
1193 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2087 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
1194 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2088 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
1195#define HC_PORT0_END 1074 2089#define HC_PORT0_END 1822
1196#define HC_PORT1_START 1074 2090#define HC_PORT1_START 1822
1197 {OP_WR, HC_REG_CONFIG_1, 0x1080}, 2091 {OP_WR_E1, HC_REG_CONFIG_1, 0x1080},
1198 {OP_ZR, HC_REG_UC_RAM_ADDR_1, 0x2}, 2092 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2},
1199 {OP_WR, HC_REG_ATTN_NUM_P1, 0x10}, 2093 {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10},
1200 {OP_WR, HC_REG_LEADING_EDGE_1, 0xffff}, 2094 {OP_WR_E1, HC_REG_LEADING_EDGE_1, 0xffff},
1201 {OP_WR, HC_REG_TRAILING_EDGE_1, 0xffff}, 2095 {OP_WR_E1, HC_REG_TRAILING_EDGE_1, 0xffff},
1202 {OP_WR, HC_REG_AGG_INT_1, 0x0}, 2096 {OP_WR_E1, HC_REG_AGG_INT_1, 0x0},
1203 {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0}, 2097 {OP_WR_E1, HC_REG_ATTN_IDX + 0x4, 0x0},
1204 {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2}, 2098 {OP_ZR_E1, HC_REG_ATTN_BIT + 0x8, 0x2},
1205 {OP_WR, HC_REG_VQID_1, 0x2b5}, 2099 {OP_WR_E1, HC_REG_VQID_1, 0x2b5},
1206 {OP_WR, HC_REG_PCI_CONFIG_1, 0x0}, 2100 {OP_WR_E1, HC_REG_PCI_CONFIG_1, 0x0},
1207 {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a}, 2101 {OP_ZR_E1, HC_REG_P1_PROD_CONS, 0x4a},
1208 {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2}, 2102 {OP_WR_E1, HC_REG_INT_MASK + 0x4, 0x1ffff},
1209 {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff}, 2103 {OP_ZR_E1, HC_REG_PBA_COMMAND + 0x8, 0x2},
1210 {OP_WR, HC_REG_CONFIG_1, 0x1a82}, 2104 {OP_WR_E1, HC_REG_CONFIG_1, 0x1a80},
1211 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24}, 2105 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
1212 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2106 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
1213 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2107 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
1214 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2108 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
1215#define HC_PORT1_END 1092 2109#define HC_PORT1_END 1840
1216#define PXP2_COMMON_START 1092 2110#define HC_FUNC0_START 1840
1217 {OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38324}, 2111 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2112 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0},
2113 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2114 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2115 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2116 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2117 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2118 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2119 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2120 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2121 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2122 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2123 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2124 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2125 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2126#define HC_FUNC0_END 1855
2127#define HC_FUNC1_START 1855
2128 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2129 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1},
2130 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2131 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2132 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2133 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2134 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2135 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2136 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2137 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2138 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2139 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2140 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2141 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2142 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2143#define HC_FUNC1_END 1870
2144#define HC_FUNC2_START 1870
2145 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2146 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2},
2147 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2148 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2149 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2150 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2151 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2152 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2153 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2154 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2155 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2156 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2157 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2158 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2159 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2160#define HC_FUNC2_END 1885
2161#define HC_FUNC3_START 1885
2162 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2163 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3},
2164 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2165 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2166 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2167 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2168 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2169 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2170 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2171 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2172 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2173 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2174 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2175 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2176 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2177#define HC_FUNC3_END 1900
2178#define HC_FUNC4_START 1900
2179 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2180 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4},
2181 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2182 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2183 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2184 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2185 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2186 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2187 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2188 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2189 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2190 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2191 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2192 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2193 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2194#define HC_FUNC4_END 1915
2195#define HC_FUNC5_START 1915
2196 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2197 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5},
2198 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2199 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2200 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2201 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2202 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2203 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2204 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2205 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2206 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2207 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2208 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2209 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2210 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2211#define HC_FUNC5_END 1930
2212#define HC_FUNC6_START 1930
2213 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2214 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6},
2215 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2216 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2217 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2218 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2219 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2220 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2221 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2222 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2223 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2224 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2225 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2226 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2227 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2228#define HC_FUNC6_END 1945
2229#define HC_FUNC7_START 1945
2230 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2231 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7},
2232 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2233 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2234 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2235 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2236 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2237 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2238 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2239 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2240 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2241 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2242 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2243 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2244 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2245#define HC_FUNC7_END 1960
2246#define PXP2_COMMON_START 1960
2247 {OP_WR_E1, PXP2_REG_PGL_CONTROL0, 0xe38340},
2248 {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1},
1218 {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10}, 2249 {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
2250 {OP_WR_E1H, PXP2_REG_RQ_ELT_DISABLE, 0x1},
2251 {OP_WR_E1H, PXP2_REG_WR_REV_MODE, 0x0},
1219 {OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff}, 2252 {OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff},
1220 {OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff}, 2253 {OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff},
1221 {OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff}, 2254 {OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff},
@@ -1231,6 +2264,7 @@ static const struct raw_op init_ops[] = {
1231 {OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff}, 2264 {OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff},
1232 {OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff}, 2265 {OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff},
1233 {OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff}, 2266 {OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff},
2267 {OP_WR_E1H, PXP2_REG_PGL_INT_XSDM_1, 0xffffffff},
1234 {OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff}, 2268 {OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff},
1235 {OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff}, 2269 {OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff},
1236 {OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff}, 2270 {OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff},
@@ -1245,9 +2279,11 @@ static const struct raw_op init_ops[] = {
1245 {OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff}, 2279 {OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff},
1246 {OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff}, 2280 {OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff},
1247 {OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff}, 2281 {OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff},
1248 {OP_WR, PXP2_REG_PGL_INT_XSDM_0, 0xffff5330}, 2282 {OP_WR_E1, PXP2_REG_PGL_INT_XSDM_0, 0xffff3330},
1249 {OP_WR, PXP2_REG_PGL_INT_XSDM_1, 0xffff5348}, 2283 {OP_WR_E1H, PXP2_REG_PGL_INT_XSDM_0, 0xff802000},
1250 {OP_WR, PXP2_REG_PGL_INT_USDM_0, 0xf0003000}, 2284 {OP_WR_E1, PXP2_REG_PGL_INT_XSDM_1, 0xffff3340},
2285 {OP_WR_E1H, PXP2_REG_PGL_INT_USDM_0, 0xf0005000},
2286 {OP_WR_E1, PXP2_REG_PGL_INT_USDM_0, 0xf0003000},
1251 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8}, 2287 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8},
1252 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8}, 2288 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8},
1253 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8}, 2289 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8},
@@ -1257,6 +2293,7 @@ static const struct raw_op init_ops[] = {
1257 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4}, 2293 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4},
1258 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0}, 2294 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0},
1259 {OP_WR, PXP2_REG_RD_START_INIT, 0x1}, 2295 {OP_WR, PXP2_REG_RD_START_INIT, 0x1},
2296 {OP_WR, PXP2_REG_WR_DMAE_TH, 0x3f},
1260 {OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40}, 2297 {OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40},
1261 {OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808}, 2298 {OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808},
1262 {OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803}, 2299 {OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803},
@@ -1321,58 +2358,103 @@ static const struct raw_op init_ops[] = {
1321 {OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004}, 2358 {OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004},
1322 {OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440}, 2359 {OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440},
1323 {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440}, 2360 {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440},
2361 {OP_WR_E1H, PXP2_REG_RQ_ILT_MODE, 0x1},
1324 {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1}, 2362 {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
1325#define PXP2_COMMON_END 1200 2363 {OP_WR_E1H, PXP2_REG_PGL_CONTROL0, 0xe38340},
1326#define MISC_AEU_COMMON_START 1200 2364#define PXP2_COMMON_END 2077
2365#define MISC_AEU_COMMON_START 2077
1327 {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16}, 2366 {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
1328#define MISC_AEU_COMMON_END 1201 2367 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
1329#define MISC_AEU_PORT0_START 1201 2368 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
1330 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000}, 2369 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
1331 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef}, 2370 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_NIG_0, 0xf0000000},
2371 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
2372 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
2373 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
2374 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_0, 0xf0000000},
2375 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
2376 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
2377 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
2378 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_NIG_1, 0xf0000000},
2379 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_PXP_1, 0x0},
2380 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_PXP_1, 0x10000},
2381 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_PXP_1, 0x5014},
2382 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
2383 {OP_WR_E1H, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00},
2384 {OP_WR_E1H, MISC_REG_AEU_GENERAL_MASK, 0x3},
2385#define MISC_AEU_COMMON_END 2096
2386#define MISC_AEU_PORT0_START 2096
2387 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000},
2388 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000},
2389 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef},
2390 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff55fff},
1332 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff}, 2391 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff},
1333 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0x500003e0}, 2392 {OP_WR_E1, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0x500003e0},
2393 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0xf00003e0},
1334 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0}, 2394 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0},
1335 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000}, 2395 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000},
1336 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5}, 2396 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5},
1337 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000}, 2397 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000},
1338 {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x14}, 2398 {OP_ZR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x14},
1339 {OP_WR, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000}, 2399 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x7},
1340 {OP_WR, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555}, 2400 {OP_WR_E1, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
1341 {OP_WR, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555}, 2401 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4, 0x400},
1342 {OP_WR, MISC_REG_AEU_ENABLE4_NIG_0, 0x0}, 2402 {OP_WR_E1, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
1343 {OP_WR, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000}, 2403 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5, 0x3},
1344 {OP_WR, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555}, 2404 {OP_WR_E1, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
1345 {OP_WR, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555}, 2405 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5, 0x1000},
1346 {OP_WR, MISC_REG_AEU_ENABLE4_PXP_0, 0x0}, 2406 {OP_WR_E1, MISC_REG_AEU_ENABLE4_NIG_0, 0x0},
1347 {OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0}, 2407 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6, 0x3},
1348 {OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3}, 2408 {OP_WR_E1, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
1349 {OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7}, 2409 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6, 0x4000},
1350#define MISC_AEU_PORT0_END 1221 2410 {OP_WR_E1, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
1351#define MISC_AEU_PORT1_START 1221 2411 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7, 0x3},
1352 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000}, 2412 {OP_WR_E1, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
1353 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef}, 2413 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7, 0x10000},
2414 {OP_WR_E1, MISC_REG_AEU_ENABLE4_PXP_0, 0x0},
2415 {OP_ZR_E1H, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x4},
2416 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0},
2417 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3},
2418 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7},
2419#define MISC_AEU_PORT0_END 2128
2420#define MISC_AEU_PORT1_START 2128
2421 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000},
2422 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000},
2423 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef},
2424 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff55fff},
1354 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff}, 2425 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff},
1355 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0x500003e0}, 2426 {OP_WR_E1, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0x500003e0},
2427 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0xf00003e0},
1356 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0}, 2428 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0},
1357 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000}, 2429 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000},
1358 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5}, 2430 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5},
1359 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000}, 2431 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000},
1360 {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x14}, 2432 {OP_ZR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x14},
1361 {OP_WR, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000}, 2433 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x7},
1362 {OP_WR, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555}, 2434 {OP_WR_E1, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
1363 {OP_WR, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555}, 2435 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4, 0x800},
1364 {OP_WR, MISC_REG_AEU_ENABLE4_NIG_1, 0x0}, 2436 {OP_WR_E1, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
1365 {OP_WR, MISC_REG_AEU_ENABLE1_PXP_1, 0x55540000}, 2437 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5, 0x3},
1366 {OP_WR, MISC_REG_AEU_ENABLE2_PXP_1, 0x55555555}, 2438 {OP_WR_E1, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
1367 {OP_WR, MISC_REG_AEU_ENABLE3_PXP_1, 0x5555}, 2439 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5, 0x2000},
1368 {OP_WR, MISC_REG_AEU_ENABLE4_PXP_1, 0x0}, 2440 {OP_WR_E1, MISC_REG_AEU_ENABLE4_NIG_1, 0x0},
1369 {OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0}, 2441 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6, 0x3},
1370 {OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3}, 2442 {OP_WR_E1, MISC_REG_AEU_ENABLE1_PXP_1, 0x55540000},
1371 {OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7} 2443 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6, 0x8000},
1372#define MISC_AEU_PORT1_END 1241 2444 {OP_WR_E1, MISC_REG_AEU_ENABLE2_PXP_1, 0x55555555},
2445 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7, 0x3},
2446 {OP_WR_E1, MISC_REG_AEU_ENABLE3_PXP_1, 0x5555},
2447 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7, 0x20000},
2448 {OP_WR_E1, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
2449 {OP_ZR_E1H, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x4},
2450 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0},
2451 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3},
2452 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7},
2453#define MISC_AEU_PORT1_END 2160
2454
1373}; 2455};
1374 2456
1375static const u32 init_data[] = { 2457static const u32 init_data_e1[] = {
1376 0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0, 2458 0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
1377 0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440, 2459 0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
1378 0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0, 2460 0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
@@ -1464,4905 +2546,12215 @@ static const u32 init_data[] = {
1464 0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000, 2546 0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000,
1465 0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000, 2547 0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000,
1466 0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff, 2548 0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff,
1467 0x00000200, 0x00000001, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 2549 0x00000200, 0x00000001, 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20,
1468 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00088b1f, 0x00000000, 2550 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
1469 0x51fbff00, 0x03f0c0cf, 0x3130ef8a, 0x22b1c430, 0x3b0143f8, 0x02ecdd01, 2551 0xffffffff, 0xffffffff, 0x00000000, 0x00007ff8, 0x00000000, 0x00003500,
1470 0xdc406ec4, 0x19b7c404, 0x23dfd348, 0xf1476080, 0x03343031, 0x032f3731, 2552 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20, 0x00002000, 0x000040c0,
1471 0x423f2483, 0x4d5011fc, 0x02ef9025, 0xa40cdb15, 0x77280475, 0xf2c060fb, 2553 0x00006180, 0x00008240, 0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540,
1472 0x77629812, 0x056c1144, 0x58c8f22c, 0x4dde4d11, 0x44af950c, 0xe340ff40, 2554 0x00012600, 0x000146c0, 0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0,
1473 0xfca8b235, 0x6d081948, 0x8b5f150b, 0x95051f26, 0xd0849577, 0xe76964eb, 2555 0x0001ea80, 0x00020b40, 0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40,
1474 0x00607a36, 0x2726b9d6, 0x00000400, 0x00088b1f, 0x00000000, 0x7dedff00, 2556 0x0002af00, 0x0002cfc0, 0x0002f080, 0x00031140, 0x00033200, 0x000352c0,
1475 0xd554780b, 0x333ef0b5, 0x64ccce67, 0x093c991e, 0x20f264af, 0xf09c0682, 2557 0x00037380, 0x00039440, 0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740,
1476 0x93a8a808, 0x07be3040, 0x0e22a5e4, 0x27902018, 0xf5e8bd48, 0x620c19bf, 2558 0x00043800, 0x000458c0, 0x00047980, 0x00049a40, 0x00008000, 0x00010380,
1477 0x2f06d6b4, 0x93a45a2a, 0xb6968a80, 0x6c1a06c1, 0x822203b4, 0x6b06f5bf, 2559 0x00018700, 0x00020a80, 0x00028e00, 0x00031180, 0x00039500, 0x00041880,
1478 0x368b6d7b, 0x2062a28a, 0xa5ebd8b9, 0xaffadaf7, 0x99def6b5, 0x91332673, 2560 0x00049c00, 0x00051f80, 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80,
1479 0xfebffdaa, 0x5fa7f7df, 0xf7b3ecdd, 0xf5ed7bd9, 0xb3ef6b5e, 0xa66e6547, 2561 0x0007b100, 0x00083480, 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280,
1480 0x97d8ce5d, 0x9be507f8, 0x232c630a, 0xa1bbd65a, 0xed58cc9c, 0x9ef8731e, 2562 0x000ac600, 0x000b4980, 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780,
1481 0xec66c65c, 0x4f2e44b1, 0x12ab7a87, 0xf4dd42b6, 0x4fda9d92, 0x7af5e56f, 2563 0x000ddb00, 0x00001900, 0x00000028, 0x00000000, 0x00100000, 0x00000000,
1482 0x9743f773, 0xb9fb3b40, 0x05053d99, 0x589bb1eb, 0x6c276309, 0xf2f5ff8c, 2564 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
1483 0xaf3b72fa, 0x5feeb6d6, 0x557fa0cc, 0xe1d995a7, 0x661d13fd, 0x3cd7d63f, 2565 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
1484 0xc01984a5, 0x3eefbb50, 0xbf8c046d, 0xdbb4ac22, 0x0a7f50bd, 0xcafb421e, 2566 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
1485 0xfb18730e, 0x33bbb9f7, 0x4ec64e03, 0x5798da36, 0x937ef843, 0xd8c453d9,
1486 0x59eef0aa, 0xaadfa023, 0x04cf8a5d, 0xaadaacf3, 0x8c9f2e44, 0x19b095cf,
1487 0xe9dea886, 0x1cb1de60, 0xcd192f86, 0xf358eb4b, 0xe30bcc24, 0x0b45b532,
1488 0x4dbe70b8, 0xc515d79a, 0x0f46c9cf, 0xb5eb23cd, 0xf03cc2cf, 0x144fdd5e,
1489 0xceb12e1f, 0x30ed82c4, 0xf67de9ff, 0xb89ddb85, 0xa15af5be, 0x258ebf4b,
1490 0xab1d717b, 0x2cdaadc2, 0xaad5c227, 0x8e8a2f2d, 0xcd33bd57, 0xfc96d708,
1491 0x7b5d4161, 0x91b2796c, 0xb4616f31, 0x7f318abe, 0x0fe113bb, 0x47c7b36b,
1492 0x29641f9f, 0x9deacf44, 0x45b5e666, 0x442c67c7, 0x17cccdcf, 0x2eb2bc41,
1493 0xb74f4f97, 0xdd231e33, 0x7788a4d6, 0x7df3c013, 0x024d8741, 0xf843df4f,
1494 0x7bf64ca0, 0xfeb0abd6, 0xa3cc99e4, 0x26fef10c, 0x1ed85b0b, 0x900bbd67,
1495 0x1630a619, 0xb7822664, 0xc26f058e, 0x50d4cfb2, 0x5fc3c005, 0xeb002b24,
1496 0xefe14fbd, 0xd4bccf5f, 0x9ad1beff, 0xe9bae91f, 0xe6ed92ca, 0x7496b15c,
1497 0xfa7f2fac, 0xb5321801, 0xbf10cfc2, 0x88ade22a, 0x43321e16, 0xca576bbb,
1498 0x7abc07c4, 0xc72d95fc, 0x4d93dcf9, 0xa678fa06, 0xa9ea1927, 0xf0635333,
1499 0xb89cf4eb, 0x4e01d440, 0x827fa9ab, 0x6958cf9a, 0xedf88db6, 0xe48d6c8e,
1500 0x38cb8ee6, 0x3b64775c, 0x7fa821c3, 0x08b85f17, 0x42f05aea, 0xc07c1c4f,
1501 0x859626cc, 0xa6c4d065, 0x466f6e0d, 0x941f023c, 0xf8517ce5, 0xa6f5941e,
1502 0x2814c2fe, 0x21a52b57, 0xc446cbc4, 0x330e9423, 0x3b75c06b, 0xd4f08cac,
1503 0x7b64a63c, 0xfba78748, 0xb94f0173, 0xb7ef71d1, 0x1f316434, 0xca840f63,
1504 0xc070ea43, 0xf7102e6f, 0x3cb78462, 0xf7802a12, 0x42c8ef73, 0x9034da7c,
1505 0x1afcfd03, 0xf3445fcc, 0x1f1e20b7, 0x9d8c7415, 0xcd3856df, 0xaf3dbf30,
1506 0x5dbf30ca, 0x2781f983, 0x2b5d089f, 0x8e3c07e6, 0xec07ec60, 0x96df9a5a,
1507 0x6fe68eb7, 0x619558d6, 0xf981a4fe, 0xd3ef38c3, 0x2e6fe609, 0xfeb8d8bc,
1508 0xf5c655bc, 0xcffd7c6b, 0xf989e685, 0x3ffd6893, 0xfaf8f362, 0xebe2eef3,
1509 0xfab8c2b7, 0xf803ddf9, 0xefbc476f, 0xdb7f804d, 0xeb8dd379, 0xae31afcf,
1510 0x7fe7cadf, 0x988b7421, 0xfff349df, 0xd7c2dd82, 0xcd377f9f, 0xf836b56f,
1511 0xcd64d03c, 0x23086a49, 0x7fe17b5f, 0x802ca0c3, 0x5942a679, 0xbc18ca94,
1512 0x47961dff, 0x2923b878, 0xfff61e78, 0xcdf8093c, 0x2c0bd519, 0xb94151bc,
1513 0x5d3c13af, 0xf6896bb9, 0xb2a5783d, 0x064beb93, 0xc00c74fa, 0xb3f3ba77,
1514 0xf000ffcf, 0xf628ee56, 0x8f24bd99, 0x265bdf0c, 0xe66f5296, 0x902c60f8,
1515 0xfa85db3d, 0x673d9029, 0x59f9353c, 0x4645e826, 0xe3e20e30, 0x13962d65,
1516 0x5af93a3d, 0x5f58c5b1, 0x25d63619, 0x24c8a5dc, 0xd8ca8650, 0xf79806d8,
1517 0x0623e804, 0xd07df27a, 0x647e5847, 0xdda2b761, 0x15f400f8, 0xb572f4d3,
1518 0x4272e89e, 0xb13ff8e5, 0xf8f241c5, 0x1ad5a6f9, 0x1c7847cb, 0x7cdd6480,
1519 0x1156f621, 0x58be73ac, 0x04b9e127, 0xcf5f15f5, 0x6bdaaefc, 0xdc02c4c0,
1520 0x4ef78669, 0xd416225b, 0xf0b0b75b, 0xfe3059bd, 0xb6ee0f6d, 0xf8ff4904,
1521 0xae489a47, 0xc81348d9, 0x968582f5, 0xef747bf7, 0x64d8ec2d, 0x8de50919,
1522 0x9bf3e341, 0xd3f58cab, 0x84c5b096, 0xc2a57976, 0x5bfc615a, 0x72ed8c1a,
1523 0x54b13f9e, 0xdf31674e, 0xf0c5a07c, 0x06575c54, 0xe1e82fd1, 0x3ebb00eb,
1524 0x87da246b, 0x53df14db, 0xfb05bf50, 0x1e3a444d, 0xe2f9f0d6, 0x07be2965,
1525 0x997860d8, 0xdf40930a, 0x78dd8577, 0x743cb557, 0xfe183291, 0x7e1c979e,
1526 0xebc184d3, 0x56fb8588, 0xdc3a21e6, 0x7cf8ceba, 0x7d762849, 0x3bea0f9c,
1527 0xd03ed34b, 0xbf6daf3d, 0x1d03ed32, 0x9cef54bf, 0x0cafa86d, 0xbfe868df,
1528 0x4312cb62, 0x9596b2fb, 0x9adbf686, 0x4bea1b57, 0xfa1a7742, 0xbd6ebadf,
1529 0x8696fda1, 0x37ed0dfb, 0xd4326d57, 0x6e3e0c6f, 0x6160bfe8, 0x795da1ab,
1530 0xfa0e6569, 0x305af537, 0xfde03867, 0xacacefd4, 0xb1f2894d, 0x1b8ff3e4,
1531 0xd93ca8b3, 0x3d72a5e8, 0xbfc82bca, 0xeb2f1f69, 0xa0e496db, 0xffbe4b9c,
1532 0x8d90d2c8, 0xdfcb1272, 0xcb18f2b1, 0x6837c8c7, 0xf3d91287, 0x5005851a,
1533 0x6e14fbee, 0x77f3e48f, 0xec65fe84, 0x1ab7921e, 0xcd63cb8d, 0x50cbc3f3,
1534 0x48b46a5e, 0xf1338361, 0xa15dacb8, 0x46d63075, 0x830cace3, 0x9ae81854,
1535 0x77b3806f, 0xafe699bf, 0x22e3e743, 0x2581f7b4, 0x791fce0a, 0xf186fb39,
1536 0x297f8f08, 0x48333bd5, 0x5636f62f, 0x22a07da4, 0x7e5402fe, 0xca90b8dc,
1537 0x2a418d13, 0xa2ac683f, 0x06c6fdf2, 0xd71a7b2a, 0x636ef951, 0x8d63ca88,
1538 0xbefe54cd, 0xb7ca85b1, 0xf950b71b, 0x9530c6db, 0x54fd1ba7, 0xb5a9f00e,
1539 0x43fd10bf, 0x432b07f6, 0x0ebd9717, 0xcdc816fe, 0x7737e919, 0xe11afaf2,
1540 0x4bc22737, 0xe213dd2c, 0x434c858f, 0x89292dd1, 0xc4c923d3, 0xf9c8182a,
1541 0xfaf6e303, 0x8abaf296, 0xe008032a, 0x0397fbd3, 0x860d22e3, 0xde3d357d,
1542 0xf683bb41, 0xd93365ef, 0x99f9163f, 0x1e9706ef, 0xd423401f, 0x8474bf37,
1543 0x35fd029f, 0x7e72f14a, 0x9cbc0af9, 0x8dddbc39, 0x964d747a, 0xa4c1f3c9,
1544 0x6dabebc4, 0x7538f5cf, 0x1a77d4f0, 0x945a67eb, 0x7a0fee0a, 0x478ee793,
1545 0x3e78f07e, 0x65ba4028, 0x59c72951, 0x3e79a593, 0x617ec348, 0x95db0f5a,
1546 0xf105fc42, 0xb6fbf508, 0x4e3448e1, 0x760e8e14, 0x1f27de1c, 0xff713f3b,
1547 0xfea17c84, 0x9a3f4349, 0x473e5975, 0xff856abb, 0x1401897f, 0xc72ea953,
1548 0x87376fad, 0xf3e217ac, 0xe0f9865d, 0xf58caf3d, 0x8a1bccbe, 0x427654ff,
1549 0xa4a807f2, 0xacde22a3, 0x18f769de, 0xa18a75f5, 0xdc39df5e, 0xf8dfd063,
1550 0x3657900f, 0x5ed15153, 0xe8b608d5, 0x0acd9d53, 0xf90bb7c0, 0xaf52e806,
1551 0xb6b57ef0, 0x8f082d1e, 0xcd3474ce, 0x3d8bc4bf, 0xb1bd685b, 0x3c6c9df0,
1552 0xc4d555ec, 0xcf9b57f0, 0xe38811dc, 0xf0ae7f97, 0xc4c6a538, 0x0b665ffd,
1553 0x584e51b9, 0x873dc856, 0x07399bf8, 0x0b7143f0, 0xcbaba3cc, 0xe9afc071,
1554 0x7acf678f, 0x8dafdc4d, 0x526ad79d, 0x757f09ce, 0xc2ce8ebb, 0xb1e2c775,
1555 0xb43ff3ae, 0xcc8dc520, 0xdf894780, 0x6ac04a5d, 0xed57f182, 0xf9434f7c,
1556 0x2a12d8fa, 0xc4dce7fc, 0xbf0c19f8, 0x2384eb33, 0x7b35ceba, 0xad5fe45c,
1557 0xede224d9, 0x79c6eb10, 0x13134e97, 0x74bd017f, 0x62e58070, 0x26dfa826,
1558 0x5dee326a, 0xfe4d51da, 0xa42c87d5, 0x89f53fa1, 0xfd04a5b9, 0xaded5583,
1559 0x3ce01f9a, 0x88154cc5, 0x4dec53af, 0xbd1d24f7, 0xd11a4c8a, 0xa366b6e9,
1560 0xa6fe00df, 0xa6fe0ea1, 0xcd9cbea1, 0x7638c4c9, 0xb80b66f9, 0x434eb4be,
1561 0x879328fb, 0x3582b0e8, 0x7afb446c, 0xfcd263bc, 0x3f0e904b, 0xf104b27f,
1562 0x479a14bb, 0x8f1e22a6, 0xd6ff1e12, 0xfbe257f9, 0x1bcf0713, 0x7c98dbe5,
1563 0xed43c080, 0x8e1fc54e, 0x991737c3, 0xfe4abf38, 0x4ff080da, 0x2dcdfa89,
1564 0x4d6bf531, 0x6b724a8a, 0xe3a46666, 0x642d8f29, 0x5f76a64a, 0x7a12f004,
1565 0x026beade, 0x12a3fafe, 0xbb226d98, 0x74c0991e, 0x04a8fefd, 0xf2af79e9,
1566 0x013472fa, 0xc04c8d4c, 0x06d80b3c, 0xd04d3be2, 0x60f08ad7, 0x1aa59cbc,
1567 0x728f59d6, 0x9dd8e30d, 0xb7df0c1d, 0xf1da637b, 0xc637681f, 0x8e1bb232,
1568 0x2776c6b1, 0x87f219b0, 0xbe7c67cb, 0x180fc842, 0x4c3be222, 0xebdfa17b,
1569 0x662339b6, 0x34d94bf0, 0xce2077b5, 0xc878c3c8, 0xfe91813d, 0x645e52f3,
1570 0xaff787ad, 0xb5847913, 0x4b0d94ef, 0xa97fc21d, 0x84b61b3f, 0xb57574d3,
1571 0xa97e435f, 0x12c3bb3f, 0xf40df49e, 0x989617a0, 0x279b9519, 0xca236094,
1572 0xd49bc4ad, 0x3c3d517f, 0xcb97a3ca, 0xfef431ad, 0x03a470da, 0xec70753d,
1573 0x482d8252, 0xbe3858f7, 0x8359f8f6, 0xadfadfc6, 0x68305f8e, 0xf0f19dfc,
1574 0x631c7a78, 0x0337a4dd, 0xfee80cc9, 0xa8f3dd9f, 0x8ff7444c, 0x85233e41,
1575 0x58f84fe8, 0x4b79e344, 0xb8f8cbac, 0x59e5ebaa, 0x81575718, 0xfe05eb7f,
1576 0x485ac95d, 0x294c448f, 0xb335cfc2, 0x55de0e88, 0xfea6bf5d, 0xff783aab,
1577 0xfd4ed66a, 0x3119bf31, 0xe1927bac, 0x7def293d, 0x9cd49ec2, 0x1d11612d,
1578 0x790b763f, 0xe087bf00, 0x106bcf93, 0xb26bcc3e, 0xb6a79a6e, 0xcf30cd3d,
1579 0xf6735f80, 0xf9d11662, 0x376ab53d, 0xd9ed77f1, 0x019e68cb, 0x6afe067b,
1580 0xfc6a1b44, 0xa3b80691, 0xc0334fe3, 0x3a7f1d1b, 0xcfc72bcd, 0xca72039a,
1581 0x2be513f5, 0xc293cb42, 0xb7a7804d, 0x91f7c1ac, 0x9b5cb25f, 0x76415f73,
1582 0x04f1fa5a, 0x744fc7d4, 0x1d34df6c, 0xea09fae8, 0x9b975c39, 0x739eb9b9,
1583 0x92174c86, 0x7c853afe, 0x18bfa030, 0x43f1afe8, 0xb7e8c7b4, 0x8c0af851,
1584 0x28f59a3f, 0x3746dfa8, 0x8e50f518, 0xef84dd33, 0x3e33ace5, 0x019ea2f7,
1585 0x521b95bd, 0x9f5ce263, 0x6fcfc709, 0x9f4f3e36, 0xc73aba51, 0xd3516e07,
1586 0x2798a533, 0xba505f4a, 0xb187a47b, 0x7957d40b, 0xe2d299fd, 0x79ff50e1,
1587 0x1532bad3, 0x7ff4d5fc, 0x86ce2d2b, 0x91b2d3ba, 0xca15abd7, 0xb7cc592b,
1588 0x89be8594, 0xcac0081e, 0x6294728d, 0x0a9cfc06, 0xccbf9b1c, 0x5fb47a8b,
1589 0x9e8478e3, 0xd3d19f80, 0x39467e38, 0xfc46ed8f, 0xd67a98e4, 0xc3f973a3,
1590 0x052bff17, 0xe62f4643, 0x1e0f013d, 0xf483c1b6, 0xbed34781, 0x8ebfc21c,
1591 0x5f2533f5, 0xf305b14c, 0x4b938e10, 0x167f7ec7, 0xeaa27d3c, 0x5b0dc500,
1592 0x71f9fe44, 0xf46eb710, 0x326f55bb, 0x3364e3f2, 0x0965d7cf, 0x378ceebf,
1593 0xfd487937, 0xa195959e, 0x53eae0ea, 0x9fc8ddfb, 0x5f1c5f7d, 0xd6237e8c,
1594 0x13d08653, 0x32a359f5, 0xa3139254, 0x749e667e, 0xc14aa3e2, 0x5b378847,
1595 0xb6cf3466, 0x7e510942, 0xc0b5fa44, 0xbf5c1e01, 0x7f31aa12, 0x8edfc179,
1596 0xe0d6e3a7, 0x775866d5, 0x83c85985, 0xbdb0b98b, 0xf08f2ab7, 0xf6836e96,
1597 0x6b3d688c, 0xe809cee9, 0x0398a4e7, 0xc37be2d7, 0xc6cd9f97, 0x43d98e7a,
1598 0xb4a2dbf8, 0x00f8470c, 0xc3cfb48f, 0x569d82f6, 0xdcc93168, 0xcf26f64f,
1599 0x69ce2219, 0x1f4acc6b, 0x55cf2fca, 0xde718b83, 0xf7bebdfc, 0xf1fc619b,
1600 0xf70f9a95, 0x9bafc65b, 0xccf88e99, 0xc03d7132, 0x72f390ee, 0xf82f5f3d,
1601 0xf8aacfae, 0x77ded0fd, 0x8435a7bb, 0xda0b33ed, 0xb519afd1, 0xfdc3ebce,
1602 0x42873e80, 0x7a35f7ef, 0xe7282f29, 0x1c95dd1d, 0x9e49bbb1, 0xf3c8373f,
1603 0xd07d633a, 0x3b7a5f7c, 0x7fbc707b, 0x9c42f8f6, 0x1d0f949e, 0x67d9e82d,
1604 0x725dfbe6, 0xb42cd1be, 0x7391fd1f, 0xcc5fef9d, 0x7fda74ae, 0xba037410,
1605 0x925e9084, 0xfbdf402e, 0x121b5f10, 0x78bef7d3, 0x6b6e5df4, 0x5db946c8,
1606 0x659f6815, 0xe625e781, 0xafd883e0, 0x21f76166, 0x50decd0b, 0xe927fc88,
1607 0x70d0d4ce, 0x740353d4, 0xfc21497f, 0x7c717667, 0xb7361fd6, 0xcb1e7ee2,
1608 0x40b7ae0a, 0x42ca99fb, 0xa22627ca, 0xfe75f8f3, 0x017cbd74, 0xfce2b7dd,
1609 0x9a8ebbe3, 0xef493e10, 0x49de44c7, 0xffecadca, 0xbdfa598c, 0x0f76be62,
1610 0xfc55f7cd, 0x166eb457, 0x7c780b8d, 0x80dfcf56, 0xff9c76c7, 0x1fe166c7,
1611 0x3b63c60f, 0x3c073ff6, 0x3c1739ee, 0x939de87e, 0xcfe30799, 0x7f093b32,
1612 0x87329f2b, 0xbea4b0ad, 0xf52fd2d9, 0x333c335f, 0x5e5627aa, 0xd71fb0d4,
1613 0x8549f2b9, 0x6bb2acf8, 0xc26c35c5, 0xf96378e0, 0xe3e910c2, 0xd903b8d8,
1614 0x5ab2f912, 0x7f13178e, 0xff07b354, 0x734e4cc3, 0xf54ef498, 0xbffb634e,
1615 0x9b30f945, 0x24ce04f2, 0xf1b1b79e, 0xf1d0b2f1, 0xe248be47, 0x8b26717c,
1616 0x619e1c91, 0xd0f7c429, 0xbb608bee, 0x33fca2e6, 0xdc6291db, 0x314cac9f,
1617 0x6e8e4fec, 0x4ff21930, 0xc9b1f3b1, 0x5fec4cca, 0x6730e42a, 0x6fb0c99d,
1618 0xee321b97, 0xa737e5eb, 0x5a63ea1a, 0x9ffa1846, 0xd0cf25b7, 0xbe7c2e3e,
1619 0x9d82fda1, 0xf1f50d13, 0xfa1b17ed, 0x6659d85f, 0xae4717a8, 0x749ff432,
1620 0x3ea18e78, 0x4326fba5, 0x2f6fa9ff, 0xd45fb435, 0x7ed0cab3, 0x0c6bc7c9,
1621 0xeffb4bf5, 0x2c8ff432, 0x00ac38a9, 0xff025efd, 0xe086f314, 0x67c8a857,
1622 0x99acfe07, 0xfc0e4f90, 0xa8c4d0b9, 0x2bc867dd, 0xa673f81e, 0xf81f9f1f,
1623 0xfb1f8973, 0xe7cb3295, 0x5952e2f1, 0xdb19b0ce, 0x0be05553, 0xc0d96fb4,
1624 0x569a9817, 0x7203f28d, 0x39454235, 0x0fc3a7fb, 0x469d0215, 0x46482cac,
1625 0x34f20d3b, 0xbd373d42, 0x27ef8394, 0x962da792, 0x290f1b96, 0xac7ded83,
1626 0x38e590be, 0x5bade655, 0xbad37de8, 0x65a7616c, 0xb230f17d, 0x5f9f9233,
1627 0x7a1c5333, 0xe3d70366, 0x86a43667, 0xdf9efef9, 0x0fe75c39, 0x24e8399e,
1628 0x9efdcefe, 0xaf01db93, 0x892cebd3, 0x7f2901da, 0x323f22f9, 0x7945582a,
1629 0xe3fe418f, 0xb8f59ea2, 0x1ff573ce, 0x99c6fd63, 0xff021e92, 0x05d1d709,
1630 0xf1f68972, 0x27da1483, 0x7161e35a, 0x36b6eff7, 0x16770f36, 0x4b2e7e0c,
1631 0xdce1cd65, 0xb40f30fb, 0xe159f14f, 0x1fd86dfd, 0xbc587bec, 0xb5ea26d7,
1632 0xbd454d21, 0xebe22b56, 0x521e71d8, 0x7e466f4b, 0xdd96a1d8, 0xc5d14eac,
1633 0xdc5a0dd3, 0xd077c7bc, 0x0473c089, 0x0d80efaa, 0xcf5fefe6, 0xff306d7c,
1634 0x0ca78b1a, 0xf4ee6beb, 0x9af21d12, 0x7ae1667b, 0x5dc13a73, 0x73fbd9d7,
1635 0xc056a780, 0xd4f08b53, 0xa714fda9, 0xb0a8bff5, 0x879c5cb6, 0x5f66bb8f,
1636 0x487e432e, 0xd51ce704, 0x72057c42, 0x738e3770, 0x4ed09aa7, 0xf28e7ddf,
1637 0x638d5eb0, 0xf2ec065f, 0xf15bed52, 0x137072c7, 0x9eb44a78, 0xe196d0ff,
1638 0x9d39b728, 0xc0a89fa5, 0x60e039b7, 0x9f22a726, 0xd1bef632, 0xebef623f,
1639 0xf344d0fc, 0x7689557e, 0xf1157def, 0x0631f7ce, 0xc7231dc1, 0xe46f75de,
1640 0xebe9a417, 0x4c17e7af, 0x10950012, 0x306c14bc, 0xe5e2db88, 0x95f6738b,
1641 0x2427561e, 0xbdefe786, 0x377881ce, 0x4bfd5e46, 0x7c8f5ec7, 0xb311fb77,
1642 0xb2845562, 0xc84178c1, 0xe677b2eb, 0xf0e8a664, 0xe5b1b5b3, 0xaf27556a,
1643 0xf7f012a3, 0x9ff72a9b, 0x5c3635b6, 0xe380595d, 0x3d7a4c7a, 0xca13dd90,
1644 0xd27988dd, 0x8c2f870e, 0x9327acfa, 0x702b58f0, 0xbe0a6c90, 0xf4bcfc89,
1645 0xd7ca6ec2, 0xe97c88e6, 0x297e7168, 0x2ae3be76, 0x97f847cf, 0x8c2958da,
1646 0x16cda7fb, 0x34b277f2, 0x08e28798, 0x5a5b9d07, 0x0a6c0636, 0x93db2fb4,
1647 0x0c53f5c6, 0xd0c6e15c, 0xa20a1bd5, 0xc71c02f3, 0x3dbc1e51, 0x7f3859c1,
1648 0x4451c22e, 0xe11276f2, 0xe84d48fb, 0x473c9dcf, 0xd21beb79, 0x43c6c4fe,
1649 0xf0e2fd09, 0xa7e485fd, 0x7e4dffe6, 0xa1c3fa31, 0x0c3fa8a2, 0xd058b2eb,
1650 0xeb8c594e, 0x8b55d9d2, 0x95d6dce5, 0xaeda1964, 0x92416e3e, 0x32407389,
1651 0x9ae1230f, 0x57f2e169, 0xe618d1ef, 0x4e51ead3, 0x54d9f0e3, 0xbb88628b,
1652 0x3138adbf, 0xede6553f, 0x7887bda4, 0xe5c2e311, 0x33a3e24e, 0x0bfbd6de,
1653 0x877c7327, 0xc8f7c086, 0x04322375, 0x0f887d5e, 0x16f1c789, 0xbc069ea3,
1654 0xb5e2e2fa, 0x326af006, 0x57ca75e0, 0x95fc95e0, 0xa98f9daf, 0x9cefee34,
1655 0xa5dff816, 0xde703304, 0x5bbc3753, 0xbab0f982, 0x086b9f79, 0x679ed7d7,
1656 0xe7e9b32e, 0x981ef991, 0x9cf383c7, 0x9aafe1be, 0xe825a7d0, 0x39ed3667,
1657 0x35cf192f, 0x93f38ad4, 0xfd5af6a7, 0x3e5f8e8a, 0x1e70f2fd, 0x1b4fa5ea,
1658 0xf2c7ccaf, 0x5bcf2a54, 0xf53bda9e, 0xa9d5f210, 0xb12d1c9f, 0x9ea738c0,
1659 0xd2a25a3f, 0x60d85b3e, 0xef2f6a7f, 0x203b412e, 0x7c03daf3, 0xdfaf8b67,
1660 0xfcfe0b56, 0x4aafebda, 0xc8d5e788, 0xef1ca707, 0xebfae096, 0x0f09675c,
1661 0x7cb9db0f, 0x6da1923c, 0xd32332c4, 0x17fa10f4, 0x4fc1a45a, 0x5b8788db,
1662 0x75265822, 0x7971fbb7, 0x23bbb7ce, 0xfa7bba58, 0xbd7618fd, 0xe201fe05,
1663 0x67b1f3d5, 0xbe1fd63f, 0x33e504f2, 0x1ab017d9, 0x80916380, 0x3b59f7e3,
1664 0x3a04a91e, 0xf37d2efc, 0x7e86e423, 0xf685eb01, 0xa0dff19b, 0x1e818e87,
1665 0xdc6c80f2, 0x7cfb72a4, 0xb512a553, 0x191ff853, 0xe9187947, 0x8a3545d3,
1666 0xeea5aec1, 0xd3f94199, 0x6429af3e, 0x61a47581, 0xbff81a56, 0x66ceeb4f,
1667 0xc5cec0df, 0x3883bf96, 0x9d9d7de5, 0x0952acfa, 0x67df30a9, 0x7fac8f42,
1668 0xd3f1127d, 0x178a65e6, 0xfefb18f1, 0xcb5eeb63, 0x727a099f, 0xf3879dd8,
1669 0x6efc8267, 0x90027916, 0xa7cf0537, 0x80f22c3d, 0x877b866b, 0x9ae3ede9,
1670 0x8252f323, 0x46defaba, 0x89d6dfbe, 0x7ca15ee7, 0xed7b9c41, 0xfaa2cc6a,
1671 0x2a5e8d4b, 0xe9638d23, 0x434b66f9, 0x7bdf9e0a, 0x3342c2cd, 0x77bf97c1,
1672 0xe51bff78, 0x1ddb42e0, 0x699b2fbf, 0x33d6f187, 0xd6f8cf3a, 0x13ddefbd,
1673 0x1df00e9a, 0x1929a4f8, 0xd2a740ed, 0xa61c478e, 0x23fdbe2a, 0xcb5d4f51,
1674 0x75a54f48, 0x306e742a, 0x3611cbad, 0xb7d3fce9, 0x765edc2c, 0x72de785b,
1675 0xb442da2a, 0x7fa5b32f, 0xef413fd7, 0x0fea0cc7, 0x7b9e1f81, 0xa98f9d8e,
1676 0x4ecf94fd, 0x7c30def4, 0xbfb9fc6f, 0xad4c77d7, 0x2a89f3a0, 0x66a77fb7,
1677 0x903eb667, 0xcfebfbcb, 0x79e1f497, 0xfa7238ce, 0xbdef3117, 0xc7f74e16,
1678 0x64768d72, 0x8fdb9597, 0x1df316ff, 0xa392dc68, 0x9651bf3f, 0xffe8dfc0,
1679 0x335ff2a6, 0xe488ff68, 0x68f596be, 0x3f72bcfc, 0x11fc49e5, 0x3619af8e,
1680 0x577d470e, 0xca04b2b1, 0x97ae4e19, 0xe50eb0d2, 0xeb9c550c, 0x689cfc66,
1681 0x2b56455a, 0xe28e5f9e, 0x5a73af81, 0x1c16bf4f, 0x7dc3dfcf, 0x7c0fb4df,
1682 0x29ebf20a, 0x7fee39a4, 0xfd11b6cc, 0xaa825b67, 0xbc52f486, 0x9d22578f,
1683 0x3a238cf6, 0xec958fd9, 0x5c3a464f, 0xde4cf2cb, 0x2dec1f28, 0x9c627a05,
1684 0xb6f14fb4, 0xa73ee8b1, 0xe340bf9c, 0x23e595f8, 0xc877e04a, 0xea5a05e7,
1685 0x784fdc0c, 0x82581ec4, 0x7e113247, 0x678c165b, 0x478cde0f, 0x5debedd2,
1686 0xf4e0154d, 0x3b40b5ed, 0xba360bd4, 0xfe00369b, 0x4704a6f6, 0x6b9796e2,
1687 0x30e9a3bd, 0xb970a7b6, 0x68e8d828, 0xd1c8b942, 0xe61f3c3c, 0x5f22e7f4,
1688 0x503dd40d, 0xdbabaf1f, 0xaf2aea62, 0xbed575cb, 0xc843e7fc, 0x5c5d75a7,
1689 0xd6f006be, 0xfea0ac59, 0x7e135f3c, 0xf4398392, 0x547fddfb, 0xbe341382,
1690 0xedc85d8f, 0x4a07dc98, 0x81f62ed0, 0x828b58b2, 0x1e04767a, 0xff47cb60,
1691 0x6cca9bba, 0xdca54fd6, 0x59dbc8df, 0xea04607c, 0x76605353, 0x35e7d239,
1692 0x18f7970b, 0x72b1efbc, 0x2d6bdd3e, 0xf985659d, 0x63d01e1e, 0x46ba5f7c,
1693 0x81b669e8, 0xc15eedeb, 0x9b369fbb, 0xc9c01a42, 0x79e83876, 0x553f388d,
1694 0x4c81cef3, 0xd4f8d7dc, 0xc9e22acf, 0x7b085cc5, 0x5b5f8f11, 0xb946822e,
1695 0xef907fa8, 0xcc7c819b, 0x21d57c45, 0xd937505c, 0x847ce9ba, 0x87f69ee5,
1696 0xff3718cc, 0x73c1e2d8, 0xbeb9d58e, 0xa2fe78fd, 0x0fae5f7a, 0xc3bde555,
1697 0x9d577c79, 0xd1399ed2, 0xbacbe519, 0x21d94dce, 0xfb27f7c0, 0x95f2477f,
1698 0x61ec878f, 0xa38edafc, 0xd79e105a, 0xa1a7bc75, 0x4524fd61, 0xda3e81fa,
1699 0xb877bdb7, 0x9c12f92f, 0x3c6657ef, 0xa7803859, 0x14ee96d1, 0xc3c979fd,
1700 0xa0fde7a0, 0x3d035fcf, 0xd021e58f, 0xf3d07eff, 0xd7f8be47, 0xaf3fd44c,
1701 0xccd7c25a, 0xcd9e71c1, 0xe15e60f7, 0xc1f84f53, 0xb4ff5089, 0x3d6f8c60,
1702 0x6b3e57d4, 0x7fbc600e, 0x96716d44, 0x6083ff40, 0x9dfde847, 0xc2f4eaff,
1703 0xdb0583f3, 0xf471bd33, 0xd36795dd, 0x60981f99, 0x7cef997b, 0x36078f94,
1704 0x976c9bfa, 0xbeb9f802, 0xea18ac55, 0x0d93795a, 0xa99365e4, 0x1f62d1fd,
1705 0xc73867d5, 0xce597f81, 0xf2b187e5, 0x278e52a6, 0x71b4dfaa, 0xdfdc0cd3,
1706 0x8a7bbb5b, 0xc89a7c82, 0x7d9d56de, 0xc825ce8e, 0x6b263e7a, 0xd4aaef80,
1707 0xaa59e510, 0xce84fece, 0x271acc33, 0x61fe68f3, 0x1f2dc68c, 0x8edd7886,
1708 0x13177c7b, 0xbdf843c9, 0x68b2f6c2, 0xabc1f51d, 0xd0be02a9, 0x41334d8d,
1709 0x0cb11fbe, 0xdcf1fbb4, 0xe12b9aa0, 0x523c2167, 0xfb26aafc, 0x099a6e2f,
1710 0xcd76ea41, 0x36867e38, 0x02afdfd0, 0x249abe1f, 0xfc682beb, 0x6293fd41,
1711 0xf1c997fa, 0xf3c2e3eb, 0xb75a3d88, 0x2ff57f41, 0x59fbe8d6, 0x3b68ff88,
1712 0xc727978d, 0x56f0475f, 0xf6f3370f, 0xbf65e850, 0x4dcfa51a, 0xeb4dfdda,
1713 0xdaaf6f01, 0x97a8a57d, 0xa465affa, 0x7cff916f, 0x49b87e3a, 0xb3aad9e8,
1714 0x39fd3157, 0x58b49b92, 0x90c75cba, 0xde3ee76e, 0xa2f186f9, 0x7a604ce3,
1715 0x7e047ffa, 0x6fb7584d, 0xedd762bf, 0x03ce90b3, 0xc510b3f3, 0xf35b55f3,
1716 0x07a75859, 0x5f1c3ffe, 0x027f0e17, 0x5ffe6638, 0x61ac6386, 0x451c28be,
1717 0xfefef806, 0x80259470, 0x02b7d663, 0x959dac47, 0x67617ee5, 0x0d5452fb,
1718 0xbdb63bf7, 0x8ffda564, 0x96c85374, 0xceba7687, 0x5b7a7644, 0xbf1f8b6a,
1719 0xc6b6d8bf, 0x1ee1e74b, 0x722a04b1, 0xdd0a7fc1, 0xabfda269, 0x6ebe796d,
1720 0xf6dadfdc, 0x26be792f, 0x8b3d349c, 0x071662ec, 0x3c5b6d81, 0x087e2aff,
1721 0xa3efef8d, 0x3e3b44e9, 0xf646c532, 0xe59cdb72, 0x9f4fff94, 0xda1c7673,
1722 0x0a7e9d49, 0x66531d91, 0xf3353f93, 0x3c26d6be, 0x149191ef, 0x2ffd1c78,
1723 0x74dad425, 0x76bc7878, 0x58667fae, 0xbe6066db, 0xcf595b68, 0x73938c38,
1724 0x803e702e, 0xfcf5abaa, 0xff311311, 0xbc1adc73, 0xbb780ad6, 0x1bf22aca,
1725 0xf2852c29, 0xc9051562, 0x6dd2c2a8, 0x5a253ed0, 0xa7caf87f, 0x3191cf29,
1726 0xefc860af, 0xaf814b18, 0xa67a3abc, 0xf641ffa9, 0x461afeb9, 0x8bf47179,
1727 0x172feff5, 0x027d7d7e, 0xb4e81dff, 0xad1ce11c, 0xd4c21cf4, 0xd1e75d61,
1728 0xd45f18d9, 0x139955ae, 0xe46d496c, 0x8bffdc77, 0xfd6207f1, 0x22de595a,
1729 0x7c44acfc, 0xf3958cf1, 0x25ff80e5, 0xe40fadfc, 0xb3f0a37e, 0x1ea2ed2a,
1730 0x9e506e73, 0xfe13ec17, 0xfc62df4f, 0x37d61268, 0xd769978c, 0xee7ce904,
1731 0xe5deb172, 0xd1334a5b, 0x7fdca9bf, 0xd963ad23, 0xf7e4d9e6, 0x84bcdf2f,
1732 0x784a7bce, 0x9bfc632a, 0x51265acf, 0x1d112bbe, 0xfd221fa4, 0x273f5899,
1733 0xde157bd1, 0x41cfa256, 0x58edafcf, 0xe67cc36e, 0xf67fa8c4, 0x7367c42a,
1734 0xf1a6dca0, 0xb31e09ef, 0x1b6d38f3, 0xb6005f7e, 0x399650ff, 0xb957d715,
1735 0xdf092329, 0x716b623f, 0xf91e5ca2, 0x61d7d7e2, 0xf093f43f, 0x9529ccbc,
1736 0x9eb2a5fb, 0xb72b9e08, 0x55e93f70, 0xe1accf31, 0xeff3661f, 0x1879c4ab,
1737 0xe97ca696, 0xec7efc48, 0xa69d9879, 0xaf903bb2, 0x9d7810ef, 0x873e0b62,
1738 0x155793f5, 0x5ea79f12, 0xc7cdd079, 0x79d79e37, 0xd3a5c44c, 0xee4dc3fb,
1739 0xbfdf3a74, 0x71e5e1db, 0x23ac1946, 0x653e4fed, 0x7f1e8ea9, 0xaf8978b1,
1740 0xc528fe31, 0x47d7a438, 0x702ce0f1, 0x0579f82f, 0x7e48df23, 0xa6f3eafb,
1741 0x2dff066d, 0x69f4de7a, 0x8b4edbf2, 0xacf5e5b8, 0x724be6c8, 0x51ef6c31,
1742 0xdebd4e31, 0xbf416e99, 0x16bcc030, 0xf5ae4b8c, 0x16eb9cc5, 0x11aedae7,
1743 0x7dc209fa, 0xfa0daefa, 0xaf15f619, 0xcfac669f, 0x37eb1bf6, 0x7effc454,
1744 0xee374d8b, 0xdf169fdb, 0xf0299e75, 0xb10ca726, 0x002d82de, 0x3bbd6eb4,
1745 0xae127f54, 0x9bcb4777, 0x26fe7d6e, 0xb0584f36, 0x4f212345, 0x900eee34,
1746 0xbca43c0f, 0x9d688580, 0x99dda94f, 0xc0a0b8fa, 0xb579ce22, 0x12f33aff,
1747 0x36c391a0, 0x9fea266c, 0xe7eb955e, 0x4afefbbe, 0x4b18ebf1, 0xcefc0de4,
1748 0x168bcc78, 0x2853ee2f, 0xff285a2f, 0x4edb3f51, 0xa5bf03df, 0xf7a1935c,
1749 0x3900c7c7, 0x5d33ae10, 0x5f3c8663, 0x9bacf73a, 0xb79ec5fa, 0xe7cdfbff,
1750 0xcec73c24, 0xe23e5ec7, 0x16007bc6, 0xf9d1366c, 0x5c8b85ab, 0xa4889df4,
1751 0x6338ec6f, 0xe171a8b6, 0x84ff844e, 0xb8f4b774, 0x74e6ff71, 0x4af299bb,
1752 0x6de3edb1, 0x5f8b37ca, 0xbaf31a17, 0x43fd9ea7, 0x57d60461, 0x375cf4ab,
1753 0xd8e2972e, 0x638c36f1, 0x5f719d37, 0x3fbe7a49, 0xaefba033, 0x86fdb7a9,
1754 0xe3cf20a4, 0x4903be18, 0x2f128fc4, 0xea70f089, 0x7e16edf0, 0xd164327e,
1755 0x28c6d7e7, 0xef9439fe, 0xa7b2a4db, 0xd1a77ce2, 0x7be71364, 0xc44c9ed5,
1756 0xfda5dd57, 0x2f2ab714, 0x41eee87e, 0x7ef160bd, 0x23e0e29f, 0xe97b0710,
1757 0x3c775efb, 0xfc1bfdfb, 0xc4ec10ee, 0x8fb71b02, 0x12f3edb1, 0x17f8a39c,
1758 0xecdf8741, 0x9bd1e4ff, 0xd013e087, 0x6f30733c, 0xd551ef35, 0x3aaef983,
1759 0xdbc90f4b, 0x3718affc, 0x76fc7f11, 0xa0f29dbf, 0xe9da160b, 0xf9d888fe,
1760 0x8f3dab4e, 0x9df30cde, 0xff707806, 0x00a8f4ff, 0x66f4f1e1, 0xf6fb83d5,
1761 0x983ae7f3, 0x54ffd74d, 0x08f9f1c7, 0x0cce99df, 0xba701f3a, 0x49df3e2b,
1762 0xfb655d3c, 0x45c57986, 0xf209fcc6, 0x8eadca1f, 0x3c57feff, 0xc70abbfe,
1763 0xd7e1c29e, 0xd53a8b9f, 0x8f1c9f91, 0x7c1f72ae, 0x1cf18b4c, 0x2ee80955,
1764 0x775eb71e, 0xb180acb0, 0x0c8eb261, 0xa075f30e, 0x7071e39e, 0xfb24f104,
1765 0xdd7cd43f, 0x8577dc4c, 0x03f11fba, 0x9d5bf9ef, 0x7762bfd4, 0xe8cfc211,
1766 0x059ab9bb, 0x3b01e64e, 0x74a399f4, 0x54f00db3, 0x43407dd2, 0x6475857f,
1767 0xc46bfad0, 0x6ef0b1fb, 0x68fd8bb3, 0xe4ca87bb, 0xc23ffdb7, 0xba3a4a7b,
1768 0x49f8bc93, 0xfc6a4756, 0x5d9a0073, 0x60039c31, 0xf1e50f6a, 0x3cf06632,
1769 0x473eff6b, 0x87894db8, 0x3bfcf59f, 0x2abb18af, 0x8d46b7e5, 0x11ad7d90,
1770 0xe6abf5f6, 0x5bdf10ef, 0x9ac492be, 0x355df46d, 0xbfe013e0, 0xb41717fe,
1771 0x7af9403d, 0x1cac9dfe, 0xf31164a7, 0x47fae9b7, 0xe33cf26c, 0x833d7cc3,
1772 0xbd70e7de, 0xfb033a02, 0x4cf6a667, 0x01bff250, 0x7e316e1f, 0xeb6b5267,
1773 0xf43d4429, 0x15fc1284, 0xedfeadd2, 0x77ac4c9e, 0xfc9279bc, 0x67c573ae,
1774 0x7f3205ee, 0xeed0d114, 0x3a5dddac, 0xb57f286c, 0x9d40e306, 0x7de28c7e,
1775 0xf187c516, 0x5abcc3c6, 0x2c11d9cd, 0xdd143694, 0x126859b2, 0x9fdf33c7,
1776 0xdf8099e8, 0x6e3ac1ef, 0x2ff5039d, 0x3fccf462, 0x69e9fc2a, 0x574cffdc,
1777 0x730d41d9, 0xdd376a6c, 0x214bf0bf, 0xf214bf2f, 0x33dff1d2, 0x74fa46ae,
1778 0xdcf269bc, 0x97e3ab93, 0xc1b21624, 0x7b5bd77b, 0x8efe827e, 0xebf6cbac,
1779 0x869d2fc1, 0x72e36afc, 0x66b5e523, 0x7d397c51, 0xfe26e6d2, 0xc476f61c,
1780 0xc7ce798d, 0xff23e951, 0x7f271fb7, 0xccd3a3a1, 0x61cd93f0, 0xa0e6828b,
1781 0xc1ff8a33, 0x2a3d70e3, 0x96a21de5, 0xde425c0b, 0xe57bdf91, 0x951e59f7,
1782 0xc2b5c7fc, 0x3c65ec7f, 0xfb11a87e, 0xf02a7fac, 0x1afe39d3, 0x5c600b3b,
1783 0x3f8f27f7, 0x78fc8539, 0xdf2d9fa3, 0xbdf67e93, 0xa55e39eb, 0x38a362de,
1784 0xf266647f, 0xaf296bfd, 0xf687ab2c, 0x207f24b1, 0x03d3c4ff, 0xd47a0a97,
1785 0xe819359c, 0x46a7a51a, 0xdfcf94f4, 0xd2127b07, 0xfa5cc39d, 0x377d0171,
1786 0x51f31b73, 0x66b6e33e, 0xe4e90b07, 0x3e51e3b6, 0xc63dc76f, 0x798967f9,
1787 0x3e38925b, 0xf877c43b, 0x91dfaa1d, 0x37d5145a, 0xae075f80, 0xabcbfd4f,
1788 0x79498f14, 0x95dce390, 0x7ee1f7c4, 0xadf357f1, 0x2bb67db2, 0x76a5deba,
1789 0x2f24b7d3, 0x27de437e, 0x24999f8a, 0xc5e58947, 0x92f215f3, 0x4d05f84e,
1790 0xf97b46ea, 0x9f1ff09c, 0x68aa6c3b, 0xdb7fc38b, 0xe73d7c6d, 0xec01a867,
1791 0xdb844177, 0x32fd44b3, 0x15f9c553, 0x3c589781, 0x3fc7e7a4, 0xd056b2ff,
1792 0x7f8ca6a5, 0x22f78ccf, 0xca0c3e60, 0xd78c1f6c, 0xd10ce65b, 0xef22cbf3,
1793 0xcd493ee2, 0xca2f56f3, 0xf6f3ef6f, 0xf49bcc2a, 0x6aad6f3e, 0xc7a60e73,
1794 0x1e8d6fe6, 0xebfd6f7f, 0xf42bf49f, 0xbecd3b63, 0xf3c1de31, 0x845dd927,
1795 0x93bd019f, 0x68d83fc0, 0x3b3c7273, 0x792d9e38, 0x5ba78f5c, 0xb1ff788d,
1796 0x33748790, 0xd7a0b644, 0xfe7905a6, 0x90bb39e9, 0x5b87900f, 0x4eec2f90,
1797 0x2c7efe03, 0xafa969fc, 0xc6575f1e, 0x7ee1a78e, 0x6ff6886c, 0xc91f7e3b,
1798 0x4b7a79c6, 0xb56fdfe3, 0x6309f05b, 0xea6eff46, 0xfb42af4c, 0x678aede8,
1799 0x9ff68b0c, 0xe7bfceda, 0x061ddb35, 0xf02cdbbf, 0x7638e521, 0x3cc40f9e,
1800 0x90cfa81d, 0xc31ece2e, 0x03e4bb3e, 0x7ae4d7a9, 0xfd911da4, 0x67f82f7e,
1801 0x8ccfe0ba, 0xfc1f3e26, 0xca9ac2b3, 0xdeff01ed, 0x7841eb9d, 0x9da2b21e,
1802 0x78f34160, 0xaddd67a0, 0x16f7d18c, 0x33fc1f62, 0xbb2df047, 0x07e81d6e,
1803 0x7e16fe92, 0xd738875f, 0xd407fd28, 0x7a9d134f, 0x0e1c43b8, 0x55f5c2b3,
1804 0x70927e8c, 0x7cfc3ac0, 0x138d171c, 0x8edc6fb5, 0xb58f42a9, 0x6322ef8a,
1805 0xfe7fe6e5, 0x569b911f, 0xe9025e71, 0xbcdf4f10, 0xc96eec25, 0x0562fedb,
1806 0xc04c6bf8, 0x624fc3e9, 0x1ce7ba4a, 0xb0bd40b0, 0x37cb414b, 0x82855720,
1807 0x45bc70df, 0x18f8a3e3, 0xf032e49d, 0x3e2a3fdf, 0x0366df0a, 0xa3a2dff0,
1808 0x2e2494e7, 0xf32a19c7, 0xc3fedf13, 0x80381fc2, 0x00d4efdf, 0xdf34505d,
1809 0x969bf01a, 0xbf4763dc, 0x43e66de7, 0xfb74e9bf, 0x8c78d312, 0xbf70b75f,
1810 0x6e2f4065, 0xbd07ebe6, 0x6d7a8ed6, 0x477edbcc, 0x2167d411, 0x5bce30fd,
1811 0xd379f8c4, 0xe3185776, 0x198f2925, 0xe0667b73, 0xa39d473e, 0xf75dbd61,
1812 0x277fa07c, 0xca8dcff4, 0x35ca0d75, 0x82b53bcc, 0x2b4eb3b7, 0x8b160fdd,
1813 0x47bec62f, 0xeff226f3, 0x7ae24c6e, 0xd234f50d, 0x6ec21ca9, 0x4afdc03b,
1814 0x798cc86e, 0xe4c657d4, 0x957dc44e, 0xa2c14943, 0xa67ef035, 0x29983738,
1815 0x26669bce, 0x126b72f1, 0x0e99cbd7, 0x5c1d065e, 0x79ba67bf, 0xef79d8ff,
1816 0x54defd12, 0xed7f064c, 0x7c3c8204, 0x38af9f30, 0x327e88cb, 0xed42bf4f,
1817 0x8002cdff, 0x9997456f, 0x4d3b07f2, 0xea24fac1, 0xfb1d12a7, 0x0f8b3d4c,
1818 0x1ef10123, 0xf3128ba5, 0xb167d493, 0xa3ea34fe, 0xfcf20d9b, 0x3be3825d,
1819 0x9190afb8, 0xfafcbfd8, 0x027e7d7c, 0xb7c26b7f, 0xfa496fe2, 0x8c80bccb,
1820 0x307f25bf, 0x6bad20f6, 0xbfce4cea, 0x6177afa0, 0xbafa0afc, 0xebc91a68,
1821 0x6bbc780f, 0x719178e3, 0x4f66667c, 0xc0b7c61d, 0xbc9ef487, 0xe4f729f7,
1822 0xe41e749b, 0xf537248d, 0xb7f0e5db, 0x5bc9c526, 0x6869a88d, 0x8487fba2,
1823 0x42f795dd, 0xafdf6a8d, 0x19be3aa8, 0xfee1c555, 0x60c59269, 0x7d443a17,
1824 0xd3971277, 0xa5115551, 0xd88dfa00, 0x015143ba, 0xfced119e, 0x0688f77c,
1825 0x0c9ff746, 0xf0e61bcc, 0x95870d8e, 0x70a28adb, 0x17669b37, 0xe69e0079,
1826 0x09af874c, 0xe0ce699e, 0xcd77080b, 0x039d08b1, 0x5bac7a9d, 0xd32978c5,
1827 0xf205ffe9, 0x6bd7849b, 0xbcc08cf6, 0x8718e3bd, 0x9fc065b3, 0x79e6c9ef,
1828 0x3c0aefc9, 0xc9fb09b7, 0x4efdd30e, 0x336f6e4e, 0xa6db19ef, 0xfd26673f,
1829 0xccd7e858, 0x72e3ee28, 0x614f799e, 0xb8ba03db, 0xb03f3cb1, 0x0f979f03,
1830 0xbf11371b, 0x307fcfb7, 0xc73ee2a2, 0x154d5b0b, 0xf6fc38e1, 0xa75394b6,
1831 0x2eb8d7ff, 0xc957ff09, 0x4967ec87, 0x1def9a1a, 0xb7060f82, 0xa5ed443f,
1832 0x84dfa64f, 0xd06cd6f0, 0x48f16e18, 0x033a67bc, 0x239f1027, 0xc4155bda,
1833 0x9f8e63c9, 0xae0e7828, 0xce798aba, 0xaef6d203, 0x7bc1cb6b, 0x7cee6a97,
1834 0x79ef072e, 0x38c0f092, 0x98d6ef84, 0x0fd28b73, 0x67e11ff9, 0x67033b94,
1835 0xcebafc70, 0xb7bfb44d, 0x5fbf0772, 0xcfbae127, 0x9eb02f11, 0xd5bfc8f5,
1836 0x5478bfc0, 0x8dfb0147, 0x6859acf4, 0x6a26efa3, 0x63fe7176, 0x18f0b41b,
1837 0x8eefb7ac, 0xe47da098, 0xa61f7edd, 0xed77abef, 0xf0e99656, 0x4c26b235,
1838 0xb9e77bfb, 0x97227ee4, 0x4bed11f7, 0xb38f886a, 0x63e43e1c, 0x71d92fcc,
1839 0xfdcecf3f, 0x1e52deaa, 0x425af49f, 0xafd0bd63, 0x87c93737, 0xbabd3bdf,
1840 0xdefa0afb, 0x35bcf5d0, 0x7ca3b8a2, 0x6f7ac0f3, 0x40f9c229, 0xdf20f339,
1841 0x835fde80, 0x2726f2f5, 0x1a9fbe43, 0x77a9c743, 0x3bf6be73, 0xc31ef2dc,
1842 0x63d7c889, 0x81aedc1d, 0xeebf205d, 0xf3c38590, 0xdd74e33c, 0x75c8149a,
1843 0x87f7e064, 0x54f18611, 0x86bb454a, 0x387608f9, 0xbd5bf095, 0x37d683b5,
1844 0x7bf71772, 0x92b577aa, 0x82fd4a3c, 0x7b7bc0f8, 0x457be2a7, 0x47040fc4,
1845 0x943b93e9, 0x927fd0e3, 0xbcf3ccc3, 0xc7ec775b, 0xf019887b, 0xd02fc60b,
1846 0xce4affbe, 0xe96e2a3f, 0xce3dc80d, 0x59e7c453, 0x097b93a6, 0xbff91c77,
1847 0x1e77e118, 0xe5c83eeb, 0x6fefc23f, 0xe921fc12, 0xf5c1c330, 0x21c7a48f,
1848 0xe300e80d, 0xa24bca1c, 0xa23ca471, 0xfa11ccfc, 0xc68ce4c9, 0x090e1249,
1849 0xd9472ee7, 0xb8298e15, 0x775a6eee, 0xe09556ed, 0x0502d72e, 0x3b7c75ab,
1850 0xfbf9c1cf, 0xb57782c0, 0xf9be781e, 0x9f0947e7, 0x3f0a2db5, 0x5472dac7,
1851 0x3e7a879b, 0xe319acf4, 0xff19ab9d, 0x51cf747b, 0x7757cfd2, 0x76d7bc70,
1852 0x736f56ec, 0xf728f946, 0x74c581e4, 0x95bb751f, 0xe9923fa1, 0x788cde0c,
1853 0x024fc418, 0x25cf520f, 0xf4871392, 0xf91a4253, 0xe421e029, 0xf520dc62,
1854 0xdf1156e4, 0xfe7f2730, 0x515d624f, 0x41ac10fd, 0xf927947c, 0xdf50d80e,
1855 0x3ce8544d, 0xe933b487, 0xf51e3833, 0x37bdc4f0, 0xd287e64f, 0xb25f8c98,
1856 0x63bee8e7, 0xe2b7d018, 0x5d04bbfd, 0x3f8479e1, 0x37687967, 0x74b1dc25,
1857 0x6bf081fb, 0x1351f0e2, 0x476b1fc2, 0xfac05f24, 0xf73db19a, 0x41ec89a4,
1858 0x86d6c86d, 0x98af26fb, 0x75df90e6, 0xf09b8160, 0xdf90b357, 0x67f9bc63,
1859 0x84d4af5c, 0x777f749c, 0x256e704d, 0xdba543ed, 0xc50fb87d, 0x79b50782,
1860 0xf774c1ae, 0xce9fbf3e, 0xcedd5c31, 0x8f4060e5, 0x4bfa73b6, 0x1fd72efd,
1861 0xcfc7375d, 0xec858d2c, 0x6dbc51a9, 0x7d08f24d, 0xdfe5cc10, 0x3ccd7fa3,
1862 0x7b1666f7, 0x88b3d29f, 0xcf5b5a8f, 0x2faadc21, 0xd35fbb79, 0xf2c727ef,
1863 0xd7baf557, 0xac2ed10a, 0xa54c3aca, 0xb7a0ff3e, 0x7d057b57, 0x8be5149e,
1864 0xa7985f48, 0xc93b727a, 0x0d07f54d, 0x0ace6f24, 0xc79c67ae, 0xd6307a8c,
1865 0xb4772a5f, 0xdefdc2cf, 0x9e2a1ff2, 0x5ed89626, 0xde7850ac, 0x2fada3f3,
1866 0xc19cf1bb, 0xe26bbdc0, 0x0e1bf03c, 0x3bbdffce, 0x97c4e101, 0xfe50da0d,
1867 0xc78d57e2, 0x74296f22, 0x7dc0808f, 0x1719aeef, 0xd2e7887d, 0x7e532677,
1868 0x375dd3e7, 0xc021f9dc, 0x72e3bbdd, 0x4de943b2, 0xfe9fe201, 0xf70fbb0c,
1869 0xa97e20df, 0xebee8050, 0xe3765fdb, 0x3f27e4fe, 0xda2270ba, 0x9c050fb7,
1870 0x5e667f27, 0xe7b97887, 0x865e9f99, 0x2561d5ed, 0xef6cf50d, 0x15fe1fce,
1871 0x8ed570f5, 0x9a9f8a7a, 0x0d4bf47e, 0xe14d39f7, 0x677cfe56, 0x7dfb07b2,
1872 0x65d37db2, 0xf6a6ef88, 0xb93f6a26, 0x07ea95bd, 0x4be9f99e, 0x33f68dff,
1873 0xbf61f6e0, 0x4fdb3f93, 0xaa09a974, 0x04f0defc, 0xeee8fd7c, 0xa19f5cfd,
1874 0xb07287bf, 0xc919eb90, 0x3f7f92d7, 0x8bd6e679, 0xc6bbfaf4, 0x60a5181c,
1875 0x1f5661ff, 0x7d07d79e, 0x15fbfa4e, 0xc4ed533b, 0xce9cadf7, 0xaf74d5e6,
1876 0xd73e7943, 0xdc61883b, 0x72febaf7, 0x91477d07, 0x4afb10e1, 0x293f1176,
1877 0xbcc3ed0a, 0x6d05e972, 0x217dba4d, 0x9457bf49, 0x1756a3d9, 0x8b379f45,
1878 0xb8939b79, 0xf514f93d, 0xd539c430, 0xac1efc65, 0x5f6c7f4f, 0xd6b5fe48,
1879 0xd76bf743, 0x34be7114, 0x9a3d393b, 0xb7e57e45, 0x39630ee0, 0xcf02e41e,
1880 0x8eeb40d5, 0xfadf292f, 0x1a6fd913, 0xbed357c2, 0x784752da, 0x0e7f11f9,
1881 0x8ee7c658, 0x354b06a2, 0x1b592f3c, 0xe91c5e3f, 0x3dfd3274, 0x663a2376,
1882 0xde92f28f, 0xe8c6fab1, 0x5511d2fc, 0x27dc26c1, 0x906d6ab8, 0xe17ea9ee,
1883 0x5ee937e3, 0x2ac667e3, 0x30df8893, 0x2f76847f, 0x6a79a4e4, 0x70078f31,
1884 0x7114ef9e, 0x17a987a3, 0x32aff1eb, 0x75fb49d5, 0x6a97a4fd, 0xdc5d859b,
1885 0x5b19e221, 0x6bde367f, 0x2f39ef0a, 0xc09bedd6, 0xd5274e7b, 0x8fe7b3fb,
1886 0x5a143b47, 0xabc87648, 0xa527bc11, 0x09a161fe, 0xa1e2e8b7, 0xf51738d8,
1887 0xca77e61b, 0xe77ea59d, 0xe3296894, 0xdd3c58df, 0x3877da25, 0xea277efd,
1888 0x16e79dc7, 0x7a09d687, 0x2cf4aa3f, 0xed0e3e47, 0x2f907bb3, 0x29eb2eeb,
1889 0x3bb1ebd4, 0x0b4e9e04, 0x41dfc13e, 0x64cdb8a0, 0xb5df110a, 0xa4dad05d,
1890 0xe77bb60c, 0x44757f09, 0xba41e2a7, 0xc73ad88c, 0x9bf03f40, 0x7f686bd6,
1891 0xe4252ac6, 0x7eae76cf, 0x11e61c6d, 0xaf586e81, 0x495d98eb, 0x833b03f8,
1892 0xe75d6cfe, 0x73840eec, 0x3eb5fa64, 0x3f0797dc, 0xe77d1664, 0xa0a6c351,
1893 0xda3a3efc, 0xad246fbf, 0x1e786143, 0x384b51f3, 0xa3f7ed0b, 0x787d0ae3,
1894 0x582ea63e, 0x0af24359, 0x2f7d2d7e, 0xfe40dc15, 0x26f79d6b, 0xc6a7ed1f,
1895 0x853ef9ca, 0x1be054fc, 0xab8b1dfa, 0x7c2cbbf1, 0x7920ec3f, 0x2dccebaf,
1896 0x9eaef845, 0x9e60f3e9, 0x8fc494ed, 0xf4dd2d2c, 0xf7a7183b, 0x27485958,
1897 0x03eeaf97, 0xf80266bf, 0xafc17b35, 0x3fdf8099, 0x1571d9fa, 0x0d7a71c6,
1898 0x5deab779, 0xcdef74b9, 0x7f8ed129, 0x2d7ddd5e, 0xe21195b5, 0xcfe11acb,
1899 0xc5fd5ba6, 0x26e8ebb7, 0xfa5894fd, 0xf6e4ee3f, 0xe727bce8, 0x00463d12,
1900 0x239f103d, 0xa26e9ab6, 0x863485f5, 0x8aaabbeb, 0xbe01ea45, 0x229ab6ab,
1901 0xfa884f97, 0x3de3b131, 0x4f7114e9, 0xf518a05a, 0xa702f95b, 0xca87af4f,
1902 0xbb26fc93, 0x2c628fce, 0x92e31930, 0x845d338f, 0xaf4e1df7, 0x7e0c87f4,
1903 0xd3b8e0cf, 0xe1f8c3ee, 0x04d0969a, 0xaf0e87dc, 0xf2885a4f, 0x49d47a08,
1904 0x781eebfb, 0xb6d6e31f, 0xb8f3b64b, 0xf9d689b5, 0xc247a77d, 0xe301b937,
1905 0x5ac0fcdc, 0xbe5c7f6e, 0xe5d6fb78, 0x2ee7e94e, 0xbef3c62e, 0x3e9d7375,
1906 0xff36af8c, 0xe38a5942, 0x746c85d7, 0x705d6e39, 0xf2579bed, 0x5fdf8038,
1907 0xbaa2fc23, 0x347d1bf4, 0x7a7e20ff, 0x4e8ddb8f, 0x4ebaaf4e, 0x1c642f6e,
1908 0x5e217a8b, 0x29ca5ede, 0x6b8c63ea, 0x39497f24, 0x3c79573d, 0xfc90096d,
1909 0x2375869c, 0xe1f00e3f, 0x630f9c0b, 0xff8934e3, 0x8bc2f8d8, 0xef7506c2,
1910 0x8f7d0776, 0xe69af52f, 0x3d451c0c, 0x6476d754, 0xd0abb123, 0xdc2f7543,
1911 0x3f94385f, 0x78f95365, 0x3d2b9036, 0x1359e0df, 0x432a44d7, 0xc0df3a4e,
1912 0xc6df5fb8, 0x1d8e8fef, 0x4f42b7ef, 0xbf4a7c49, 0xcf82f319, 0xc29ff943,
1913 0xfa227d7e, 0xcf29d5fd, 0xfc0d8457, 0xdf0535e7, 0x44f17dc3, 0xf7be56fa,
1914 0x7226f34d, 0x63efa97c, 0x99f325e9, 0x45d98eb8, 0xecb5fb89, 0x0c48f117,
1915 0x3e0b14ff, 0x80e7037e, 0x07724f75, 0xbea0b917, 0xd3f99928, 0x7e8bdf00,
1916 0x29f7e569, 0xc42fed8c, 0x655aaa78, 0x5797cc21, 0xf584b4ef, 0xa1f736e7,
1917 0xf5ef040f, 0x33216cb9, 0x3bb95df0, 0x0671c1e8, 0xcbbd87ee, 0xc1e1e74e,
1918 0x7282994d, 0x481ed23b, 0xf7e06575, 0x4f743d89, 0x1e0e63ec, 0x311ff44f,
1919 0xc5cbcf87, 0xe87bbe7b, 0xacce84f7, 0xea7ca7cd, 0x61fc2f3b, 0xede01fcf,
1920 0x1a3e7b53, 0xd493cfad, 0x55364cd9, 0xad3c6f97, 0x2b67dfc4, 0x167d7176,
1921 0xf3f65bcd, 0x438be5bc, 0x63eb41e7, 0xf3d1fbf2, 0xfdf9b1b3, 0x6fa878e8,
1922 0xfbf263eb, 0x6f5c5d07, 0xf9e7df47, 0xf14c77fd, 0xc7bd6fbf, 0x8bafdc65,
1923 0xc5cfbf6d, 0x8f23abf9, 0xe3ff45cb, 0xe4fd184a, 0x115d6be5, 0x396b8fbc,
1924 0x63bf463c, 0x311427b9, 0xf9ae51b9, 0xcdfc323e, 0xbe5f81b5, 0xe807d844,
1925 0xbe474ea7, 0xff68790c, 0xd0f42831, 0xff57ce92, 0x72f4f18c, 0xc3a6d995,
1926 0xbe6d4b38, 0x13fbf843, 0xba673a1f, 0x7e56ed51, 0x744c86e7, 0x6a2d86e6,
1927 0xf455bca0, 0xf374f57c, 0xfabe72df, 0x57302bb0, 0x7fd21bf2, 0x5f5cedd1,
1928 0x9756fec8, 0xe467373c, 0xd01377b7, 0x665dc739, 0x3ababe46, 0xc698b029,
1929 0x4194fdbd, 0x7a569caf, 0xf201fe9e, 0x7bfe6ae3, 0xd7efb147, 0x8afaf98a,
1930 0xc53ee9bb, 0xc97fd5be, 0xebaebf26, 0xff51b7d5, 0x817bcad5, 0x7b862c3b,
1931 0xfc932b81, 0xf7efc4d5, 0xfba14f4d, 0x73c186ce, 0x1ab82782, 0xf6fe41e1,
1932 0xdbf9eba7, 0x2ce78c9b, 0xba01b5ea, 0x921ef7d0, 0xcb946c2e, 0x23ae8f48,
1933 0x36a58f44, 0x701bdd3f, 0xf0403f9b, 0x4c8e4a2d, 0x5ff018f1, 0xf7dd37f4,
1934 0xf6e42958, 0xfdfe2d1d, 0x3e09f7e2, 0x8dfb283c, 0x4efafce0, 0x1e7aab36,
1935 0xff234ccb, 0x2ce42c3e, 0x71cbde2c, 0xbc421ffb, 0x18795e80, 0x8e7400f1,
1936 0xcaf5e8a4, 0xe7ba7ee4, 0x374a6fa2, 0xae7d1f7d, 0x80ac66f8, 0x8e784bd6,
1937 0xd1385e73, 0xf0b56f7a, 0xb5df0075, 0x47af48b9, 0x87bfebc6, 0x5b80b9ff,
1938 0x493be5ca, 0x142cbc46, 0xe091fbeb, 0x87974a93, 0xfd7c1be7, 0x3bce38d9,
1939 0xb8f1f1a9, 0x768f8a28, 0x7fb583c2, 0x6fd01a71, 0x6d35d83e, 0x12a7e122,
1940 0x938a0f9f, 0x49ff228a, 0x5c6b6dfb, 0x0bc5ed0c, 0xfdc9be72, 0x963f8f3c,
1941 0x885a0bcf, 0x57d96eff, 0xc2bd6de0, 0x3145e77f, 0x2b6844c3, 0xdf2f32c7,
1942 0x7fce980f, 0x203ecaaf, 0x195c8797, 0xcec4fc51, 0xc09b0c7b, 0xc4bb779e,
1943 0xe63e40f7, 0x1f16f7c3, 0x8b75ccfd, 0xf43df0d7, 0xef4e385b, 0x1fc8479d,
1944 0x0a45a63b, 0xda719c5b, 0xc7b6c8b5, 0x6b3b6894, 0xadc17ee0, 0xbbe99acf,
1945 0x9ea66398, 0x2d7f7047, 0xfc99a6f4, 0x3dde3fa8, 0xfa2bbe83, 0xffa30ef4,
1946 0x45d0527a, 0x20309f7e, 0x830b783f, 0xc5eff079, 0xcb9ce6dc, 0x3ee629e5,
1947 0x14164af6, 0xfb13fbbf, 0xe103427d, 0x893df079, 0xe73c87eb, 0x7ce6e995,
1948 0xf38269f3, 0xebfb8a19, 0x3ee327da, 0xc4bed45d, 0xf1f1d3ee, 0x474e6edc,
1949 0xf6fea769, 0x304aaef9, 0xe77175df, 0xba7cf393, 0xb3bafe3c, 0xd58edcdc,
1950 0x461becc7, 0xb3e795c7, 0xa49fa85a, 0x2cd9fd77, 0xd2eb2e7a, 0x37be8a8f,
1951 0xfd8bc68a, 0x13e6472e, 0xa7beff25, 0x9efd1b30, 0xf224db11, 0x78099e86,
1952 0x687bd0bf, 0x06df412f, 0xf52f60af, 0xfe4b8800, 0x9aa17879, 0xd8efe517,
1953 0x9d5f0075, 0xd51effd4, 0x4fb8b704, 0x217642ef, 0xf821177d, 0xe59df179,
1954 0xf25aee74, 0x854f546f, 0x71adbc78, 0xa7319e3f, 0x18b3ff41, 0x13a4b0fb,
1955 0xb204c1ec, 0xfc0e74cb, 0x12378bf8, 0x5f32571f, 0x17d1e926, 0xe93f74ad,
1956 0x120bb5d7, 0x4b421b9e, 0x8adefc2c, 0x6bc7ba74, 0x86ff988e, 0x981fee2e,
1957 0xfbfe7e6c, 0xf5e67e55, 0x03dff264, 0xca05fb21, 0xa5fa855d, 0x00cc8eb2,
1958 0x3162e9f5, 0xf00fbe0a, 0xb64a2a5f, 0xf2859834, 0xb7ffef26, 0x961670b3,
1959 0xbcf9174d, 0x04ae5e58, 0xa7070e54, 0x30d62cf3, 0x6c9bfb0a, 0xff9c663d,
1960 0x58da7991, 0x4fa01fbc, 0xdf89f249, 0x74fba3fb, 0xf3f303ad, 0x9dd64bba,
1961 0x0eefc32e, 0x7dc5bbd4, 0xa366360f, 0x4673ebdf, 0x057da13e, 0x616cda51,
1962 0x0701ddfa, 0xcdba448b, 0x8c00fbf8, 0x614f9bbe, 0x3dfc112d, 0xff17be8c,
1963 0x1e1c518b, 0x76fc0fbd, 0xef2194f7, 0xc7b6370b, 0x2a9e17dc, 0x7e634ae0,
1964 0xad221fba, 0x635f78c2, 0x42ad7386, 0x3016e13f, 0xc444cf3e, 0x0b61ff43,
1965 0x6f0bef63, 0xe1fc7051, 0x1b73e341, 0x5f7a463b, 0xbeb20489, 0x93de8b4c,
1966 0xdf8920b4, 0x22eff44b, 0x115b9c8e, 0x6f015728, 0xafd88bf3, 0xe8de50fc,
1967 0xe1177e09, 0x4370f1bf, 0x17d40d6d, 0xe3c6cebe, 0xc9c530f7, 0x185dea9e,
1968 0xefcadd7f, 0x3efe2d6b, 0xec361d67, 0xf0c78a3c, 0xc9b51707, 0x2b2ace78,
1969 0xb17d718c, 0xd48fb443, 0x7f18bda8, 0x3fdf1100, 0x95f74bcf, 0x74f38bd4,
1970 0x9a7987f8, 0xc333f3d6, 0x67d30768, 0x7ac46ff4, 0xee8cfdff, 0x19f79059,
1971 0x408ec76d, 0xbf4afa9f, 0x87da0325, 0xe23e64cf, 0x03bed149, 0xebcf9dff,
1972 0xdf889797, 0x5d47c08d, 0x2733ca9b, 0xc6fa9b13, 0x5cfcc1b0, 0x18bb35df,
1973 0x73f954f3, 0x297f13a7, 0xba0a2f82, 0x7c51ff14, 0x3f68c22f, 0x972bbeb5,
1974 0x1c17dfce, 0x719e51f6, 0xd4e1a981, 0x1bdf5c1e, 0x13effe3c, 0xc84cc6fb,
1975 0x7918d4f3, 0xafca24b9, 0xe72c5ed4, 0x7accfb97, 0x3ce046be, 0xfc44a0f0,
1976 0xc7bd12c4, 0x1662ece5, 0x6671c3fd, 0xbd25c744, 0xbdb45332, 0x3fdf0b72,
1977 0xf646aa9b, 0x225e1ca3, 0x4e5162ca, 0xe2330166, 0x7f73c4ab, 0x5177ce13,
1978 0xf21a68e0, 0xaf9b74fd, 0x9f46af19, 0xb86150bb, 0x4e9cc4af, 0xffb17ebe,
1979 0x3d8af52d, 0xfb67e799, 0xddbab3dc, 0xdf997dba, 0x30df85ba, 0xb98d8d96,
1980 0x24f7ff67, 0x3bffa517, 0xdb18dc91, 0x4066e463, 0x7d3f313f, 0x7dfb18b7,
1981 0xff3f3ce1, 0xc05e6a6e, 0x7e3e7cf8, 0xe71f97d7, 0x15d0ec77, 0x0b8e8ccb,
1982 0x78416472, 0x6ec77f62, 0x2ab7f48e, 0xa2d6fe8c, 0x8522fa7f, 0xa7b0c0ec,
1983 0xc1ccbf6b, 0xe25ce67c, 0xb12ebacb, 0x43fc0f3f, 0xfd89e3df, 0xe34efaf9,
1984 0xd77d7cfe, 0x74337b92, 0x9d75f3fb, 0xcf3fb55f, 0x5bbfeeed, 0xd30f74c2,
1985 0xd604afbf, 0x165e7982, 0x7107c2fb, 0x9462783f, 0x3cc5aeee, 0xe35073af,
1986 0x3107f4fb, 0x4bcba37f, 0xfcf070cc, 0x340b8ce8, 0xe5573e7a, 0x2129f2fb,
1987 0x0b92f927, 0x665defc4, 0x7e41d998, 0x1fe7847e, 0xeb3e22c2, 0xb40d7e16,
1988 0x47fca06f, 0xa465dc8c, 0x6547ca31, 0xf2963cdc, 0x8abb0b3a, 0x0d3e6327,
1989 0x7fe533f4, 0x7a5eddbb, 0x98b0617f, 0x395723f2, 0x8af3a46f, 0x6aad5df5,
1990 0x7adf4ea5, 0xf5f78d93, 0x9a5df9c4, 0xfa29e482, 0xe019a5df, 0x489e7a27,
1991 0xa7dfcb0f, 0x9bbe62ac, 0x7de2e597, 0x9d774001, 0x3194b79d, 0x53fb4f7e,
1992 0x5d2b9d0a, 0x76483ce5, 0x630ed578, 0xd45b943f, 0x6bafd57b, 0xcd537f74,
1993 0x467c41ae, 0x5de52d72, 0xa1b517de, 0x3ee0afd4, 0xe611df4f, 0x77fa436b,
1994 0xc05b8cc4, 0xe04f98ed, 0xa5e858b3, 0x3666f349, 0x24e53ee1, 0x565f9713,
1995 0x7fc91be9, 0xe7917377, 0xc7551d84, 0xfe50cad3, 0x63eb9f40, 0x067dfcb3,
1996 0xc4531fd4, 0x717ab1f8, 0x2e03f08a, 0x137d6153, 0x0a7d76a3, 0xa683f5e3,
1997 0xbddd332e, 0x3c9ce02f, 0x9fdc4720, 0xd24a7a90, 0xc6e5ef03, 0x92cb5df3,
1998 0x63c87e85, 0x184f4879, 0xc157f89f, 0x8d2a73cc, 0xbca1521f, 0xf407cc44,
1999 0x84df210e, 0x9dfa364c, 0x034a8d8f, 0xfa1b79e9, 0xa03e508d, 0xfd7f4904,
2000 0x46642abc, 0x1ac45ebc, 0x1726b86e, 0x03b758f5, 0xb07c05e9, 0x4d1fcf52,
2001 0x5bbd922c, 0xb509f031, 0xe8c4a6f7, 0x3d12a61d, 0xc238304c, 0xa5ad7669,
2002 0xc42bf47d, 0x6e53a273, 0xc9d51fb4, 0x3fb4618f, 0x87c01fea, 0xf52fddb1,
2003 0x93ea3309, 0x8f05f65c, 0xf43feed3, 0xfb0f8c1d, 0x8c5fc22c, 0xa1dd4ba1,
2004 0x641f8b93, 0xbe49fa51, 0x983598ba, 0xca1f00b3, 0xf75e792f, 0x2a5ba462,
2005 0xfc8c51fa, 0x892c69a7, 0xe64d8be4, 0x57c907f9, 0xa2255e92, 0x4fa484f6,
2006 0x7841cb0e, 0x53b4ed2f, 0xa462e9de, 0x58bdd013, 0x4aed2f8c, 0x6af4e4c4,
2007 0xb0174879, 0x7ec1e61b, 0x97aa665e, 0xe4c933e8, 0x614cfa27, 0xdba434be,
2008 0xd7ddf6cf, 0xe8eb7084, 0xe3192db0, 0x80e80545, 0x3ed8357c, 0xe463db18,
2009 0x94bbe259, 0x2c9fc979, 0x9c394665, 0x670d04e1, 0x8dcafba2, 0xa0b363f7,
2010 0x7b94f08a, 0x6f8fdd06, 0x41b1d232, 0xc8ae7845, 0x444bf632, 0xa7a41ccf,
2011 0x89690fb4, 0x6ae529e9, 0xa9d39db7, 0xfa84e81e, 0xd2afd266, 0x34813867,
2012 0x25ccade7, 0xc53bb0fb, 0xfaf584db, 0xc5f4851a, 0xcbdf6ee4, 0x106fcf58,
2013 0x337eb9ed, 0xafd683ee, 0xde53ede5, 0x7ac0cc0a, 0x5ede3ac1, 0xc9b04f7c,
2014 0xaddfe385, 0x2fd8bdd0, 0xcbc7727c, 0x47be1ed8, 0xcfca5fbc, 0xe06fd6e1,
2015 0xf9847fef, 0x3cf10bde, 0x7c0ccb44, 0x9739ae3e, 0xf0b00eff, 0xfc172e67,
2016 0xe3695bb2, 0xc83c20f7, 0xc8715dc7, 0xce28c496, 0x65cafee1, 0x6f979d62,
2017 0x3f4cebe5, 0x1785557e, 0x37b2a9f8, 0x2d95d740, 0x1109c164, 0x3372ef58,
2018 0xf1f9f204, 0x10bc1be4, 0x0d288f28, 0x500aa744, 0x72fbf49d, 0xc0b67cd3,
2019 0xc7ef9e78, 0x92fa79ef, 0xf329bc79, 0x35ffb8e5, 0xfb4f675b, 0x469e7992,
2020 0x654ccbf6, 0x09ef3f7c, 0x91a3f917, 0x7c8298c7, 0xfec0b88f, 0x57faf289,
2021 0xbd9037e4, 0xe64722ba, 0xa5d47bf3, 0x97f15f30, 0x178acd9f, 0xcc9e7f07,
2022 0x62c7e4ed, 0xaf3e4f1f, 0xbdfdf30a, 0xf4cbc8dd, 0x30e9ad7d, 0xe19853d5,
2023 0xb9ddab1e, 0xfe7aaebc, 0x28f35f7a, 0x06b35dfc, 0x36ca8435, 0xcc7da15b,
2024 0x679fe0eb, 0xffe14627, 0x2830d93f, 0x00800092, 0x00000000, 0x00088b1f,
2025 0x00000000, 0x7dedff00, 0x45947c09, 0xf37f78b2, 0x093215cd, 0x87213b93,
2026 0x98884013, 0x861c2184, 0x4109264b, 0xe8098414, 0x720d7282, 0xeb22dc85,
2027 0x97f75763, 0xd9110441, 0x73d6f8dd, 0x0160763d, 0x18896151, 0xc3824830,
2028 0x12a20882, 0x75040411, 0x0844ae22, 0xf1e20c49, 0xabaf2e1e, 0xbe667bba,
2029 0xfc38666f, 0xddbf7ffb, 0xdb2e23f7, 0xaaefafa9, 0xeaeaeaea, 0x084c8eaa,
2030 0x908238b9, 0xadc4b45b, 0x9680a1cf, 0xc8401bfe, 0xd5fa25dc, 0x3f02242b,
2031 0x213c6376, 0x33fe1277, 0x192d7aec, 0xf01dc844, 0x289085bb, 0x2afda4b3,
2032 0x9fdefe83, 0xd328bff4, 0xf3bfcf72, 0xc84d94a3, 0x3a558caf, 0xd50a1dd2,
2033 0x8459ece8, 0x9c9b359c, 0x7c84be9a, 0xcce2392e, 0x7d690903, 0x965cff76,
2034 0x64beceef, 0x47e696be, 0xb048d4d0, 0xefde62df, 0x13d2e27c, 0x977cdfda,
2035 0x918f0bee, 0xfd22ed0d, 0xa43a6a57, 0xae9a1a27, 0x232f7e57, 0x41e93d1e,
2036 0xf2ad7948, 0xe271257b, 0xe57acaf7, 0x91d99277, 0x845efd06, 0xf69f8a1f,
2037 0x5907cb67, 0xcfff6932, 0xe6147fbc, 0xb9346c57, 0x97129a65, 0xc193d5ae,
2038 0x1e7ce1eb, 0x4e157f34, 0xc8fba793, 0x64246f17, 0x6cc89752, 0xbb9095d2,
2039 0xe67e8ecc, 0xf99c4238, 0x146529e6, 0xe1e9cebf, 0x5c5025d6, 0x4c396536,
2040 0x6308fdb4, 0x8bce9b96, 0x4cc588d8, 0x79f12df1, 0x9f0c0d4a, 0x3c52471f,
2041 0x4832f8c3, 0xe699e006, 0x14d1f53b, 0x8448e3ee, 0x93881bf1, 0x88c23e00,
2042 0x4252112b, 0xbf1846ac, 0x42475e1f, 0x2179adff, 0x57ccaef1, 0x1f027de1,
2043 0xd36244cf, 0x47137f41, 0xa775f12b, 0xfbd22169, 0xfbf2bb4e, 0xcb1388af,
2044 0xc2ac9a4f, 0x24c9b12f, 0xe0aed7de, 0xca1cbb93, 0x9e041372, 0x3cf1ab47,
2045 0xc515fccc, 0x01309d2f, 0x54d24c7c, 0x58c9e3fd, 0xb30d6f0a, 0x1cf6c5ae,
2046 0xb852178f, 0xbac12eb3, 0x4b44c002, 0xfdb409d7, 0x926c404a, 0x3d22ae8f,
2047 0xab189d58, 0xe707e9ed, 0x93761991, 0xee389e0f, 0x1499a0d8, 0xcfe5d22e,
2048 0x06913c03, 0x29837ffa, 0xd210c53f, 0xb2f80994, 0x18262574, 0x52d47107,
2049 0xde92d3b8, 0xd814da35, 0x132b488f, 0xfdb4e313, 0xdb4bf8fd, 0x3e066911,
2050 0xb0cf20b8, 0x2a383267, 0x53f552f3, 0xc131b4e2, 0x5acf37fa, 0x91787809,
2051 0xa38e81e1, 0xadf943de, 0x2b5f7d73, 0x2a7210e5, 0x942468ce, 0xa67467de,
2052 0x1f5f52e5, 0xea2ee63e, 0x4a95ed86, 0xd0b6efae, 0xc764836f, 0x52cf3023,
2053 0xf8cf5b8d, 0xa13a6aa9, 0x6f3f96ed, 0xf748adb0, 0xf8d43fcd, 0x2d23f008,
2054 0xc93bffa2, 0x1d7ad2d0, 0xeaeb1752, 0x0bdefc74, 0xddca2ce8, 0x2b17451f,
2055 0x9185ef5d, 0xdd60278e, 0xe8b8c3b7, 0xa309697a, 0xaf8e86eb, 0x01932245,
2056 0x74e2549f, 0x7e02ca2d, 0x04eba3bc, 0x951297ca, 0x81d1c953, 0x351856fd,
2057 0x5e1fb764, 0x757d78db, 0x096655b9, 0x9989f7c7, 0x4dc7ff60, 0xdf30d5b6,
2058 0xae293d16, 0xe96c78a5, 0x9a48d3c2, 0xa01bfad2, 0xcf2840fc, 0x70e0edea,
2059 0xabe5868b, 0xbee517db, 0xdd9236ac, 0x545fac74, 0xf29bb213, 0x4369e597,
2060 0x4bb68b95, 0x147fd2a6, 0xa2dbed2f, 0x453e0156, 0xbce67dbd, 0xdd1c604f,
2061 0x802df64d, 0xcd35d98f, 0xfb5f877a, 0xe01f30ed, 0x579b1d13, 0x454b187b,
2062 0x45ccfb7f, 0xef1e209f, 0xbcdd20f2, 0xdb0160f0, 0xe1f6fdb1, 0x1fd21e4c,
2063 0x72c3ac0d, 0xc5cb0ebe, 0xae53ab7a, 0x04a64937, 0x63f9468d, 0x5aa0b941,
2064 0xc67a957f, 0x17ef844f, 0x4ebac4d3, 0xfb42d089, 0x64535953, 0x1fbec35a,
2065 0xa64248a5, 0x64b2c91b, 0x21a33f9a, 0x7175e501, 0x1997b3a4, 0x0cd23ce9,
2066 0x0ce489fb, 0x5f862f97, 0xe4b4bf8a, 0xd93e312b, 0xa9ed6fc7, 0xf6cf384d,
2067 0x81a63f55, 0x786f2ebc, 0xa875e507, 0x191f3979, 0x48f38516, 0xd6e0fb60,
2068 0xd9391b6a, 0x059787d3, 0x428f3666, 0x0f40acb9, 0x313664f2, 0x7ea7e81b,
2069 0xc3d3fba4, 0x57b95c28, 0x6f285c47, 0x93901a6c, 0x9c63c397, 0x7e2c435d,
2070 0x72612df2, 0xf0c96217, 0x688e49c1, 0xdc5c9c05, 0xb53e514d, 0xff22bbaa,
2071 0x147d45ba, 0x1ccee9f9, 0xf963dc05, 0xebf94510, 0x7015f26b, 0x536e67ef,
2072 0x35c1bf94, 0xc2770141, 0x9e3f202f, 0xca4e5d97, 0xbfae37a7, 0xde7f515b,
2073 0xbf4859be, 0x895ebe3a, 0x4994d6d3, 0xd05b30f1, 0x80686e9f, 0x670e52c7,
2074 0x68a3ded5, 0xb725b89f, 0xe1cfcb44, 0x69bb31fc, 0xf94258ee, 0x897d6fa3,
2075 0x67221fa2, 0xd28e30ca, 0xa18912ed, 0x46a73eac, 0x7bcc4fb9, 0x37170946,
2076 0x992cbe3c, 0xf407ea04, 0xdb4b4327, 0xac5d2129, 0xf5a8dfa0, 0x11519e84,
2077 0xdd0fc8b1, 0x57c63748, 0x79303e6a, 0x074861f1, 0xf4f5e83e, 0x3e3e01b0,
2078 0x19ebe2f0, 0xb9d5f109, 0x7b8e07b7, 0xee3a36de, 0x18fc40f4, 0x10fc9512,
2079 0x43f25166, 0x1f928678, 0x7e4aac22, 0xe4ab9ae8, 0xa3be3507, 0x20fe4a6c,
2080 0x105ffa1e, 0x568cc77c, 0xbca94df2, 0xefe00f72, 0x5f9e7872, 0x1fe90abf,
2081 0xf0a987a0, 0x1af01e3a, 0xff6bc3ee, 0x2625b6dd, 0x61df660b, 0xe478041c,
2082 0x197620f8, 0x046c52e5, 0x3e561dea, 0xcca7a14e, 0x107ae288, 0xd69fa76f,
2083 0xf7d613bd, 0xa049c932, 0x967fd09e, 0xdcd3bae4, 0xc639df14, 0xd520a02a,
2084 0xa2b3ec6f, 0xd32c1ca8, 0xdf21b3bb, 0xefc1ef4f, 0x417bd2ad, 0xa7411ef5,
2085 0x7281c439, 0xa61f0025, 0x2f50f427, 0x3f40ff80, 0xff8411ed, 0xed077ea8,
2086 0x5179f256, 0x7234b93a, 0x06a4be20, 0x0d911dc9, 0x72106cd3, 0x3fb171d6,
2087 0x157ca366, 0x4a0da2f8, 0xe84772fe, 0x817da28f, 0x448f211f, 0x255206bb,
2088 0xab7f0227, 0x50c913e4, 0xa9371de2, 0x223ff841, 0x35e80bd8, 0x416f9bc4,
2089 0x0899037e, 0xbc4de94a, 0xd30f723f, 0x06a48d4b, 0xb242b2e9, 0x7f69972e,
2090 0x4be975f2, 0x7f4ba508, 0x64ffd533, 0xa69b42d8, 0xd18d77c0, 0x773ec329,
2091 0xfe60b91d, 0x3f5a06ea, 0xc5f95d61, 0xbff2d098, 0x5b8d8dfc, 0x281f549d,
2092 0x2464f4d9, 0x5afaf4a1, 0xa56f135b, 0x2ed6cbf5, 0xb4d1b48d, 0x7d44eb45,
2093 0x3c976bea, 0x7f6415da, 0xed8a3f7e, 0x264274df, 0x7c153f90, 0x795fa72a,
2094 0xd7ac1c6c, 0xccead6ef, 0xb9522d32, 0xd036e0de, 0x375151f5, 0x46c92c7f,
2095 0x8fc199b8, 0x54f8037c, 0x5e4a1b9f, 0x82de327a, 0x5933a3fb, 0x3ba90893,
2096 0x62b4d099, 0x81463fcd, 0x3a49567e, 0xd4b8c196, 0x1fffa0f5, 0x595afee8,
2097 0x77d4cf2b, 0xe11e720d, 0xb5d05aeb, 0x6fb1eeb2, 0xcdf848e4, 0x557e07a3,
2098 0xbd062f97, 0x3b67ea8e, 0x89bb3c84, 0x45eb04dc, 0xe2b883e0, 0xdf93ef50,
2099 0x99bb2178, 0xf66badc2, 0x787e4a47, 0xc421e422, 0xaced674f, 0x0969bcbf,
2100 0xaa36874d, 0xfe5e90d7, 0xcf585cf5, 0x9ee12f52, 0x5a581a4a, 0x0e4773a6,
2101 0xb654aca5, 0x687a874a, 0xaebfc6d9, 0x33c533fb, 0x5eb06639, 0xdd2fdb4f,
2102 0x43c7f6f8, 0xa6bfbe40, 0xa6cb1d8b, 0x7de29261, 0xffa4a974, 0xe8f8e516,
2103 0xdbfaf250, 0xfb164b7a, 0x8fb460fe, 0xedafa51e, 0x40ac93d4, 0xeed4147c,
2104 0x414c7bd4, 0x3cdb52e8, 0x1e02648a, 0xdd03d27e, 0x9121debf, 0xf820f484,
2105 0xa476f55c, 0xe909e383, 0xa5e4e9c8, 0x5cfabd5b, 0x412bf4c9, 0x2bbe7527,
2106 0x0afa8cca, 0xca7a87b4, 0xf6ff1b1b, 0xf14fc526, 0xcc2b0627, 0xf76ff8bf,
2107 0x4e3cc245, 0x5f18ab69, 0xde34b0bf, 0xd62dfb46, 0x98cde339, 0x2fc5efb2,
2108 0x6df91afe, 0x8ebf87de, 0xd93fa827, 0x38b93492, 0xdf9824cf, 0xc4efe79c,
2109 0x0e25cdf9, 0x17e2bbe4, 0x9fe83b64, 0xf464b5e7, 0x45d6416b, 0x175b3441,
2110 0x15d356a7, 0x4a77e74d, 0xf38044cf, 0x8b5aeca0, 0x517bd287, 0x28dafc18,
2111 0x8402ffd6, 0x9d191bcf, 0xf86b45ba, 0xdf4ba2ba, 0x3cd75f9f, 0x39f404d2,
2112 0x004b6a9d, 0x6892af3d, 0xd21f1c9d, 0xfcaeda45, 0xa3026161, 0x8568b10f,
2113 0xa8f2a47c, 0xf943be00, 0x2c2d9d26, 0x5c8f515b, 0xbff5f74c, 0xc74ff790,
2114 0xd0f405dd, 0xf5c1f153, 0xa668caf2, 0x269fd327, 0x7e5fc7e2, 0xf7ad9beb,
2115 0xf5b28f35, 0xabbbd62d, 0x7fe43468, 0x1fad887b, 0x839c97a8, 0x602772e3,
2116 0x243bcefe, 0xe2060794, 0xd7aeb60e, 0x56baf8e8, 0xa13e0be6, 0xb9c2d6e3,
2117 0x842fcbc7, 0xf14e6f9d, 0x27dcc8f3, 0x7dbf3d68, 0x8bfa12be, 0xac4f6c0c,
2118 0xfd7c79db, 0xf7cd1cdf, 0xc9febe5d, 0xcf4171f3, 0x5b73eabf, 0xeeb5ce99,
2119 0xe95eb0cf, 0x605a74fa, 0x30eceabd, 0x761b33ef, 0x5d377c7d, 0xc56a6727,
2120 0x4fca553a, 0xde2d3af5, 0xa7f236fc, 0xa99e9d7a, 0xe83e3b7d, 0xeded7d3a,
2121 0xb0664f78, 0x2bbffa75, 0xe6fe053f, 0xa7e52b46, 0xf0a18790, 0x728796a8,
2122 0xa9f105b4, 0xe7f48796, 0xc8141910, 0x04ef827f, 0x5abc95bf, 0x1dc81d7e,
2123 0xbe0a5f2f, 0xe0a5f2f3, 0x957cf53b, 0x5be753f8, 0xf9472ce1, 0xf0edbec4,
2124 0xcf4a64a8, 0x6ac906b2, 0x3dbd60b0, 0xd93c5300, 0x35231b70, 0xfd63927b,
2125 0xae0a9761, 0xa9b79555, 0xbcaabb60, 0xa9570543, 0x5c70bbca, 0xf4bbf565,
2126 0x5b81e504, 0x10f75e51, 0x3d804671, 0xad7651a1, 0xa76ca8a6, 0xeb465e63,
2127 0x47486fb7, 0x12697b7d, 0xc474dbb3, 0xfc8197e9, 0x4477376a, 0x75fc5346,
2128 0xb373f184, 0xca3223bd, 0xdcd32ecf, 0xf5fca320, 0xdae8c8b8, 0xaa1af620,
2129 0x3cfd2249, 0x62fe5424, 0x4d90bf66, 0xef408b69, 0xa0ad91af, 0x3c5ecd0b,
2130 0xcef41229, 0xe31e86f6, 0x73efd327, 0x43baa1f6, 0x903db9da, 0x49b4039e,
2131 0x38b3fe94, 0xe710b63f, 0x7ce8c353, 0xa2943566, 0xa57b3e3e, 0x4d735e92,
2132 0x9ccf510b, 0x1efd04fb, 0xe12fdf44, 0xaf3f14ed, 0x2b212fcc, 0x1d289f91,
2133 0x297760f5, 0x77cca359, 0x2ecffb70, 0x48fde7c1, 0x87b9c53f, 0x3942d5cb,
2134 0xb064fc73, 0x0995ec57, 0x836749f0, 0xdcef788c, 0x9e08b920, 0xa83d986b,
2135 0x3ca07482, 0x8569f813, 0x2d0fa0f5, 0x7cb75a6f, 0x5a01e83a, 0xf1eb6ca4,
2136 0xda68e7ec, 0xaf58f5ba, 0x71bf00ed, 0x0938ed24, 0x08ed3fb2, 0x64dda1b3,
2137 0x00cb8447, 0x3f7c6ff4, 0xa3b401ed, 0xce30ac18, 0x67df1df6, 0x3fb4df03,
2138 0x79062864, 0xecca9ed5, 0xbf1a4b23, 0xe57266cf, 0x5b57a461, 0x37e99eb4,
2139 0x99fdff0d, 0x06fae704, 0xf7d82b3a, 0xf9e38477, 0x30cdf2ad, 0xbff6c117,
2140 0xfd30e41f, 0xd0a9f372, 0x61f20713, 0x19bc9904, 0x704517c6, 0x07db953e,
2141 0xed3175ff, 0xa76ebcbf, 0x2fcd167e, 0x6ca7eb78, 0x37db0fd8, 0x4da67d33,
2142 0x5dd2b847, 0xad1e68f2, 0x61c616d7, 0x056eefe7, 0x160db77d, 0x9e423747,
2143 0xab70d98e, 0x4f0c14d3, 0x5e21a53f, 0xd13f10ae, 0xfbe47a31, 0x48fc7d7f,
2144 0x2bf28236, 0x609465c2, 0x767e3fde, 0x0ec1e41c, 0x98a9f203, 0xc5da99ef,
2145 0x6e5c7fa8, 0xfe62fdde, 0x4ae2f85d, 0xafb92de7, 0x7ff6de64, 0xe21f7a71,
2146 0x5d7aa8fb, 0xe379f204, 0x8c6f08fd, 0xaf78e2b0, 0xfeabdf90, 0x337dd1af,
2147 0xe5e47ba5, 0x7fc7fde7, 0xa68779f1, 0x9ce9befb, 0xc3b066ee, 0x13f5be55,
2148 0xe56aef8e, 0x537fa6dc, 0xba7a17be, 0x3890befa, 0xf0a5a225, 0x744f0e70,
2149 0xd2e79e4a, 0xc388f77d, 0xd2113a79, 0xdd475048, 0xcad38f27, 0x2a4b24c3,
2150 0xde132828, 0x7a071dec, 0x8aa932cb, 0x4737eca8, 0x6476d3b7, 0x940c474d,
2151 0x2d0e242b, 0x217217bb, 0x3c91df1e, 0x15f9d768, 0xb4852db1, 0x9a8ed482,
2152 0x3bdd6902, 0x97b42547, 0x923f2184, 0x9e3df57a, 0x0d11f516, 0x1de8019d,
2153 0xce2b00a5, 0xbe9f5a77, 0x8bc20722, 0xa293d8e9, 0x313f7f2f, 0xcfccd63a,
2154 0x58bd1d7d, 0xc46fd33e, 0xfbe8727d, 0x66f8e55c, 0x4ba76699, 0xf36f41dd,
2155 0x8c15c71b, 0x291e0093, 0x3ca6de9e, 0x7bfaa463, 0xd1d1dc12, 0x618fecf1,
2156 0x72ef2df4, 0x141b63e2, 0xe694d01b, 0xa9563f7f, 0xec193627, 0xae0d5b24,
2157 0xad4fd0b5, 0x1b4ddef2, 0xa1dbcecb, 0xef13d0f1, 0x421e0453, 0x3efaabf1,
2158 0x1be80665, 0x667c6103, 0x74c6f8c5, 0x29631bb1, 0xf3d47a9c, 0xd5f1a495,
2159 0xd75b942f, 0x60fa073d, 0x2b7fd33d, 0xf57bb386, 0xda326d8a, 0x0c1ada0f,
2160 0xb18e892e, 0xde177eb8, 0x1b56b4c7, 0x9eb7dc09, 0xab48eba6, 0x55fe04bd,
2161 0x371c0df3, 0xcd67075b, 0xea86a746, 0xee5896d5, 0xb24d908f, 0x3fd31e61,
2162 0xcd31173c, 0x9ede7682, 0x5e76feb1, 0xab37fdef, 0xedcf9017, 0xedef54c0,
2163 0xcce2f20a, 0x65ef04fd, 0x6d23b689, 0x1cbf9642, 0x23a3ce50, 0xa9e3d186,
2164 0xb4167b68, 0xf294dcd7, 0x2857b414, 0x06e9ec37, 0xcec859f8, 0xc40c2359,
2165 0x64e94619, 0x56b5ef90, 0xde95c9f9, 0x9cf196bf, 0xfbc2e9fd, 0xfa6567a2,
2166 0x692dedda, 0x741eecec, 0xa5bf67f3, 0x988ef4ed, 0xd3daf78a, 0x93bcec0c,
2167 0xbbb87f7e, 0x6f5f5d07, 0xf81189e9, 0xeabdd74b, 0x4e70ade0, 0xabad928a,
2168 0x32b17f69, 0x217c0919, 0xce1b1bc6, 0xe7be23e6, 0x0246b0bd, 0x8fbe22f9,
2169 0x7fd1d258, 0xb1f54d01, 0xf8c53f8c, 0xf4741446, 0xf0f932af, 0xe7e466de,
2170 0xd716b319, 0xb4c3b093, 0xec0979c1, 0xeb0e7024, 0x3db7c84b, 0x5e1f786d,
2171 0x20ec4611, 0xdb35bef7, 0x7ce146ba, 0xb66f782c, 0xb7acacd0, 0x04fcd3f0,
2172 0xa0571f28, 0xe91787bc, 0xc76658ac, 0x4341fb29, 0xe2767e9c, 0x0f5bad32,
2173 0x1fb281f6, 0x77e9c4f4, 0x9d05fc0f, 0x5cefd3b7, 0x4f4b4f7e, 0x22cc27b4,
2174 0xcc27b456, 0x9c4e1e5a, 0x3aa2e77e, 0xbd350e3e, 0x56fa71cf, 0x96896944,
2175 0x2242abce, 0xdb954bf6, 0x9f764ffe, 0x23ff1eaf, 0x70e36eb0, 0x779fb87e,
2176 0xab5c1a34, 0x9dcb03d3, 0xb8f6618b, 0x3dc51bf4, 0xc5cf07bf, 0x25e5b70b,
2177 0x8aed2090, 0x1b07e2b4, 0xa5e1f971, 0x7983d682, 0x9230fc56, 0x6f07fab8,
2178 0x66f982cf, 0x81cede05, 0x5fe81a7c, 0x4df1163f, 0xb091c44f, 0x97a95e7e,
2179 0xf13d8347, 0xd19abd95, 0x678c83ab, 0x9f679f03, 0xf5f22d38, 0x5b626e8d,
2180 0xa29e8415, 0xdb347c5c, 0x459f0117, 0xa8788159, 0x074cf7cb, 0x2469b87e,
2181 0xefeb05b1, 0xc42f9c2f, 0x19a2ebb8, 0x18762b7e, 0xdb405ed0, 0x011455ed,
2182 0x71733ddf, 0x74959b3d, 0x8d863cfb, 0x4f36eea3, 0x76d3f41a, 0x083ff72b,
2183 0xe173df41, 0xe018f68e, 0x30b449c3, 0xda4187e5, 0xb7ecc92a, 0xbe94ae3e,
2184 0xd6ac3f15, 0x102bd3f9, 0xae74ebef, 0xc576befe, 0x22f3643d, 0xe6def519,
2185 0x95fefc83, 0x62eee3db, 0x499a4cac, 0x97b02ed5, 0x68495734, 0x41dbbbc7,
2186 0xdeba22c8, 0x14b87aef, 0x97d34ded, 0x8234bebe, 0xca907f7f, 0x0912bb8d,
2187 0x77a699b9, 0x09da56cf, 0xb70596a6, 0x3f7839a7, 0xfa0748d3, 0xa85f4cf9,
2188 0xfb702fb2, 0xe541e383, 0x17e02ff7, 0xc60fd72a, 0x0e43bb72, 0xbd7901c9,
2189 0x3d39e960, 0xf8a109a8, 0xc3ca85ba, 0x8b905a9e, 0xab5b4c46, 0x157e98cd,
2190 0xf604fb6b, 0x8eb1f3a5, 0xb6ee414f, 0x52e4c87f, 0x4c73cae7, 0x418f2f9e,
2191 0x2ef2c73b, 0xd78dff6c, 0xd3ea3b58, 0x3e3efe41, 0x8fc51c71, 0xeb5a2fe1,
2192 0x9b878a12, 0xc0d3353c, 0x35e84525, 0x905aac8f, 0x127e8b11, 0xefc041d6,
2193 0x32deafb1, 0x7133ec1a, 0x00db86af, 0x5cf22b7f, 0x62b18f78, 0xe7f41771,
2194 0x0fcdd232, 0x0d8f7ae4, 0x3fb81a79, 0xb16ea1bd, 0xd76d1ba6, 0x0dd3b0dc,
2195 0x35cb0efe, 0x6b3da0df, 0xf984cdf9, 0x287ef17f, 0x6919fb3e, 0x4c13f13b,
2196 0x171d2f78, 0x50d44aee, 0xbd46ee38, 0x17ea0975, 0xe0a95f4c, 0x2c976834,
2197 0x7e0a1c7f, 0x8264fb64, 0x16b13e7e, 0x087daf94, 0x0b92bfb3, 0x0f945f14,
2198 0x8fc40c60, 0x2dab5aef, 0x92fc9f68, 0xd0fb29db, 0xce8ea1f3, 0x4f8a2be7,
2199 0x6a1ecb80, 0xebe3051a, 0xabac48d8, 0xb7d89169, 0x912df292, 0xea337780,
2200 0x13aba7bb, 0x16e31531, 0x6bd947fb, 0x3f41a36b, 0x9999229e, 0x43d7095f,
2201 0x10121f05, 0x4c9e1456, 0x8bbf9c98, 0xa8539feb, 0xe3a30dd8, 0xd35887bd,
2202 0x46dddea0, 0xf8a1a912, 0x3b50529f, 0x5299f710, 0xe7ec145d, 0xe30542a0,
2203 0x8bfa5087, 0x72ea2758, 0x81af41a7, 0xc98db8f5, 0x11758a83, 0x6bbbb44e,
2204 0xecffb03a, 0x7b1ebe38, 0xd22e3f31, 0xfd60d893, 0xbde8ec54, 0xa062e80a,
2205 0xa5e303fc, 0x9b98ca72, 0xd19cfa83, 0x7f3fe748, 0x8a5b987b, 0xd9a7a3f4,
2206 0xfa034fd6, 0x1c9484fc, 0x4a3a97f4, 0xd80447e5, 0xb8693c71, 0xeb47419e,
2207 0x7d5cc306, 0x54ebdc1b, 0xfb30dc50, 0xee0ccbce, 0x2d6761c6, 0x7978d383,
2208 0x777066e2, 0xdbddff51, 0xc743fec0, 0x621fcbcb, 0x1f011f70, 0x45b3e566,
2209 0xce0c63f9, 0x1927f911, 0x7fb4483c, 0x1843c18a, 0xd3c9fc7c, 0x0f4139b7,
2210 0x8ffae289, 0xaee783d5, 0x6b7b378a, 0xde96fdfc, 0xf3726389, 0x772b1874,
2211 0x98cc9d3a, 0x08cbf400, 0x5e55fe5e, 0x02c5e85e, 0x493ea27f, 0x266f5e0c,
2212 0x80bf37af, 0x64e129eb, 0x5bf31879, 0xba524675, 0xbde86eee, 0xc617ca1a,
2213 0xd03a7345, 0xdaf80676, 0xed11f411, 0x244b7e89, 0xe9b497a6, 0xbbd89d98,
2214 0xfdb1c66f, 0x30f3f684, 0xd293d3f6, 0x909bda15, 0x81f80fd2, 0xf39681f2,
2215 0x80f81681, 0x7c6c5590, 0xc028ddb4, 0x3fa3b9b9, 0xbeedbff8, 0xfba7cb40,
2216 0xcbe6adc6, 0xcddf3807, 0x81cec25f, 0x703d511d, 0xce1118bf, 0x403244f4,
2217 0x380f8f39, 0x8b89de1e, 0xd2f4f362, 0x7ec24125, 0xa63c7096, 0xc84d7a78,
2218 0xff79faba, 0x97e78f9e, 0xbd1fb79e, 0xd7e4326c, 0xcd9ab0df, 0xd60bd187,
2219 0x85ea3447, 0x3bda2b8f, 0x3f5558bd, 0x98702e97, 0xac0f746f, 0x311848ff,
2220 0xdab277e2, 0x9b3d2f5b, 0xc7a0abe9, 0x27ca2f96, 0x74ff6127, 0x85f78cde,
2221 0x952a5c65, 0xe3d26f2f, 0x64ad6bfd, 0xef3cbf43, 0xe00ec73c, 0x79f334f3,
2222 0x5d3cd99a, 0x87257e0a, 0x88eed23a, 0x2f63e408, 0x65edbdfe, 0x14f6f0e6,
2223 0x7b582372, 0xd1422720, 0xd34bfdc5, 0x85538c45, 0x559e2f4f, 0x84f813e3,
2224 0x32f58df5, 0xc6297c95, 0xf5a87af9, 0xfb33fe9d, 0xcaf563cb, 0x08e9437f,
2225 0xc945a7fa, 0xe975e5d7, 0x7d327b9a, 0xae8036f5, 0xf3f3e717, 0xfdc71939,
2226 0x0a485286, 0x7cce0fec, 0xfec37562, 0xfb80d9b9, 0xfd92e7fe, 0x505c5c54,
2227 0xaefc20ff, 0x47b6173e, 0x1bec09e9, 0x7b40fb6a, 0x06c9b59c, 0x0967e5f7,
2228 0x550edffa, 0x6fc033d9, 0x57c9b373, 0x295fb7cf, 0x4cf111e1, 0xc3b40cbf,
2229 0xe68a7dd0, 0xb868300f, 0x018dd73c, 0x5c203d79, 0xf0d57705, 0xe0c8c4fd,
2230 0x293b0e04, 0x2034f14c, 0x3187e459, 0x3f513af8, 0x51bf958c, 0x5f70e794,
2231 0xa208fe55, 0xfdb28784, 0xb0a9e624, 0x20ff7031, 0x78d8a0f4, 0x2e43ce0b,
2232 0x4be010d0, 0x80d53803, 0xc196f5be, 0xa08d7a05, 0xce94a853, 0x3dd82ab3,
2233 0xf0bc6a7e, 0x977e6033, 0xbb40f2e8, 0x047615ca, 0x4761568f, 0x3a348f68,
2234 0xc768aee5, 0xadf605eb, 0xf747788c, 0x32bf5a78, 0x3a7a75bc, 0xff0a1f85,
2235 0x256cfd0c, 0x258fd31b, 0xa54c998b, 0x575a95e3, 0x23df41d8, 0x16a35625,
2236 0x4aedc4e9, 0xe94bf770, 0xcbc77db1, 0x6eb3240f, 0xc18e30ec, 0xee54ae5c,
2237 0xe3bbf1f8, 0x369fffb0, 0x7dfae159, 0xf7b3c370, 0xb838be81, 0x4c8fff61,
2238 0x5fa1304f, 0x60f718ac, 0xdfa29bf0, 0x380deb73, 0x370dc1fe, 0x43f281cc,
2239 0x01e86a3f, 0x84fc377c, 0x9988097b, 0x9237c6f6, 0xb91f281d, 0x25392c9f,
2240 0xd5c19c41, 0x7c5e45ea, 0x7e8f43fc, 0x231f141e, 0xcc2e3e19, 0xc5b4fc05,
2241 0x41e65c1d, 0x8b0a62a3, 0xe9f5e067, 0xb9fd03b9, 0x2b17493b, 0x23db5dd8,
2242 0x3b6a3b58, 0x3a22d1e4, 0x787dfa3f, 0x9f811d07, 0x07e23fde, 0x3e4c1523,
2243 0x29448f38, 0x926302e0, 0x39a17ca2, 0x4b7f915d, 0xfc8a0de2, 0x14fd2d5b,
2244 0xc18c98f0, 0x5bb7f28a, 0xf8f014f3, 0xe5155bdc, 0x0a456c8b, 0x56bb9fb8,
2245 0xdeffbe51, 0x21fe657a, 0x721d0322, 0x41775a8e, 0x1b4bf03a, 0xb507359a,
2246 0x7482ed54, 0x1d0cb7f0, 0x90ec3b6a, 0xc1776a1f, 0x15876177, 0xce30f0fa,
2247 0x3b2ec22f, 0xf4b93649, 0x89afedc1, 0x959e9a5a, 0x649f283c, 0xafed1d8d,
2248 0x078e61c9, 0x473d29e2, 0x2814aa91, 0xb0ec0237, 0x33850894, 0xfc01fece,
2249 0x32a73aad, 0x2051dc7b, 0xbbbbc80c, 0x788ed022, 0xf1b55754, 0xce43ea38,
2250 0xc3a39054, 0xe62b263b, 0x8707e23d, 0x6479de62, 0xf74e8abe, 0xf342e02a,
2251 0x6fe5146f, 0xc8ac5c49, 0xa8f2d5bf, 0x2b8f4e8a, 0xcfaddbe0, 0x4ab4e8aa,
2252 0x1597a745, 0x1bbf82f9, 0x076c7db8, 0x3a68b5d8, 0x0054d3cc, 0xa5b9b874,
2253 0xdb91e903, 0x74005354, 0x16b4721a, 0x6dc035e9, 0x3bf1002f, 0x2ed56f68,
2254 0x5cf4dd48, 0x4efef503, 0xee9035cf, 0xb023e7a6, 0xcea9ed8f, 0xb56f74c0,
2255 0x5bbfbf15, 0x7be98b9d, 0x3f4c36d5, 0x698d1ea8, 0xd31db553, 0x2c5aeada,
2256 0x9ebab9bf, 0xf862d7d9, 0x0bf1473e, 0x38368c76, 0x9cbca253, 0x0db2f28a,
2257 0x5f2850ce, 0x177066ef, 0x0c29930e, 0xebe5648e, 0xf2829a9f, 0x8cf83f74,
2258 0x30bf81c4, 0xd824cf4b, 0xdd3409ec, 0x8186e70b, 0x5a89b8be, 0xe4a7688d,
2259 0xb1eb9031, 0x525fbc31, 0x4296c632, 0x5ec5d2c8, 0xc18431f8, 0x2307eb28,
2260 0x1bc1f8b3, 0xe21b6b61, 0xc61edfab, 0x97c6f7f2, 0x4173818c, 0xf330fae9,
2261 0x29747e97, 0xc0528daf, 0xe649f595, 0x88e8fd2f, 0x7654c97e, 0xe5091492,
2262 0x36c3d09f, 0x20438e48, 0x1e8dca7f, 0x1aa627f4, 0x6c2bfa30, 0x8044b16c,
2263 0x85e0ea5d, 0xcf8011de, 0x672edc83, 0x3374fd23, 0xeda79a69, 0xff7d83a7,
2264 0x124f4aa8, 0xef2941e9, 0x56b76853, 0xf413bd63, 0x3a6de724, 0x413ffc02,
2265 0x51007662, 0xa604ddee, 0x6edfb4af, 0x21e0f3c0, 0xc60e6d8d, 0x9f024811,
2266 0x149f718b, 0x11c2f7f3, 0x7489df22, 0xf9128f6b, 0xe5538e1c, 0x1d60a927,
2267 0x5f19df2b, 0x05fe748d, 0x904ff9f1, 0xca7c6a0b, 0x97a66609, 0xa0a96db9,
2268 0x50f808c7, 0xe41cad91, 0xdb3ca1c7, 0x83ef30f5, 0x17930376, 0xf5d708f6,
2269 0x0db33768, 0xfecfd3bc, 0xc3a09d55, 0x1f00777a, 0xddc4fdc3, 0x3515ca32,
2270 0x604a5ffe, 0x15f22afa, 0x0aefbb9c, 0x21cd73c7, 0x1cde290d, 0x387b5e84,
2271 0x0974ce1d, 0x277df76e, 0xf9fbed81, 0x6e37cb13, 0x85cf7b81, 0xbb74d861,
2272 0x93ea37bd, 0xf31255ed, 0x3aa96903, 0x560df2cb, 0x33f4128e, 0xd1bf029f,
2273 0xf70d8dfc, 0xcb4c3f9d, 0xdc30b67f, 0xb9967b8a, 0x6eefe20f, 0x8c5a785e,
2274 0x69bff511, 0x61f35213, 0xfdc29e1f, 0x6847a79a, 0x59bdd1e3, 0xd337a51b,
2275 0xfa9b6676, 0x2418a32d, 0xf48b6373, 0x4e2e1451, 0xa41977b9, 0xd71f3d25,
2276 0x595dd5c3, 0x40cb6be6, 0x22a72f0d, 0x5bca2063, 0x74d5fbcf, 0xc916335c,
2277 0xe51e7616, 0xf4adb8fb, 0x045de2aa, 0xf1e21fbf, 0x78091447, 0xf1cbdede,
2278 0xe5edea2d, 0xe0482af8, 0x245922f7, 0xb8aca2eb, 0x0125b8f7, 0xbda63dee,
2279 0xbdc42bdf, 0xeb9f3288, 0x59eb1fbf, 0x75eba5bf, 0xb9104f2e, 0x9d812fbc,
2280 0x89e90f9b, 0x9d55ee0d, 0x277db377, 0x87b9f27b, 0x67f9d206, 0xe8359837,
2281 0x7ca33457, 0xb3a1d00b, 0x4751d39e, 0x4dfd61ea, 0xecfcce74, 0x96261230,
2282 0x5e1fc7f8, 0x36b67f6e, 0xf7fc0b99, 0x7b1e01e7, 0x9cfeff81, 0x005351db,
2283 0x8fd8b0fb, 0xbba83dc5, 0x03ef98ba, 0x77bf2855, 0x78422f57, 0xd313b54f,
2284 0xf9cbd5bd, 0xf983503e, 0xc33f55ef, 0xdf1701f7, 0xf7e3d607, 0x98c9ea86,
2285 0x6076a8ee, 0xbd8ba63a, 0x1df4e402, 0x47c60746, 0x81acfdbe, 0x675e7dc0,
2286 0x47e30183, 0xf1788ae8, 0x538858b9, 0x58579832, 0xd495e302, 0x1f978afb,
2287 0xb3fb7e54, 0x0b7ed8bb, 0x99e378fd, 0x2ebd3f40, 0x241d3f34, 0xdf390e5c,
2288 0xd0743945, 0x07d6e42c, 0x7808b60c, 0xa2ad833f, 0xf72807fc, 0xbe78da0e,
2289 0xed833f73, 0x601c9f3c, 0xefc043b0, 0x944ab831, 0x73dac03f, 0x063df80a,
2290 0x4df288d7, 0x7831760c, 0xa21fd3ed, 0xd223cc5c, 0x056f586e, 0x2091f4c6,
2291 0x79cd0b62, 0xdd9d61bb, 0x24733892, 0x826333ac, 0x56fcf905, 0x00dde2cb,
2292 0xa558c98f, 0xcdba1305, 0xa861efd4, 0xa45b1f97, 0x53237a85, 0xea187dee,
2293 0xb8f9ea8d, 0xe8debfd6, 0x061ed7cc, 0x9575ac78, 0x236bf416, 0xbe81c5c8,
2294 0xf22c0476, 0xe2213ec5, 0xd836faf0, 0xaeca3f71, 0x247ee3b7, 0x477f9cf0,
2295 0x9c3352d1, 0xb325ea03, 0x43b8e304, 0x404f06f2, 0x05c5630c, 0x1e291aba,
2296 0xe13c12ea, 0x2b3ce98b, 0xf0821e01, 0xd97f8b63, 0x109dd5fd, 0xc2383f64,
2297 0x2be807e5, 0x23ffb445, 0x3f835d74, 0x4bc70442, 0x88ccc365, 0x755e7899,
2298 0x189e8044, 0x0490f5c3, 0x2dfe6948, 0xbfcb1d3c, 0xef6c941f, 0x30f8bc82,
2299 0x03b79f81, 0x1861cde5, 0x73279507, 0xe40238d9, 0xcb9f328d, 0xdf62239b,
2300 0xb2e2c01a, 0x8b0d49cb, 0x7c4cbee7, 0xb8dc405f, 0x84a71e2a, 0xa5b1eed4,
2301 0x6f178b07, 0x2e2f1a0a, 0xfd031bfc, 0xb0b9f96d, 0x93cf930b, 0xc3d17641,
2302 0xb9686760, 0xab971dfb, 0xcca0f0a1, 0xe0e285ff, 0xf90e2389, 0xbc3c5423,
2303 0xf9c08be0, 0xb6f3b0d5, 0xea9fe196, 0x81c4c69f, 0x8823bf20, 0x6794ab1c,
2304 0xcf212f87, 0x97f1f2d4, 0x6693bb92, 0xfdc1a794, 0x98b91043, 0xcb54e30a,
2305 0xc93e6745, 0x7505fb80, 0x0a68f42a, 0xd3de213b, 0xed0c23b9, 0x8e31f514,
2306 0x0fd0448c, 0x83be3bf3, 0xeb122d78, 0x371c3c41, 0xf6846e39, 0xbff33d25,
2307 0x2dcdf110, 0x753f7d5e, 0x7923c62c, 0xfb0a7bf5, 0x9efdf7e9, 0xf20b1d49,
2308 0xdec9bbad, 0x1921da1f, 0xc85d1fcc, 0xbef1508f, 0x3ed91343, 0xff92981f,
2309 0x8e5838b7, 0xae7a369f, 0xf4e74dda, 0x62bf86ce, 0x57d9ccdc, 0x56c1c79a,
2310 0x265dba5c, 0xb68f8a46, 0x0dc4110d, 0xe52d1be7, 0xd4969a3f, 0x2b8c36c9,
2311 0x4d07bad2, 0x5bd7f08c, 0xe974ff98, 0xcadc08a6, 0x5c1b364b, 0x92fd6963,
2312 0xd1b327ad, 0x0ea1f5af, 0xbe730fbc, 0x22d75922, 0x13d93cfa, 0x1b594fc1,
2313 0x353e4edc, 0xad87e991, 0x8327c2db, 0xbf5a56bd, 0x25deed13, 0x707493b5,
2314 0x4dca2a0f, 0x3e21d44c, 0xa7b43968, 0xb8965f3b, 0xe41eeb1e, 0xfc2caf7f,
2315 0x665f5bb7, 0x7a92a976, 0xc60c2b9d, 0x36b5feb7, 0x3929c788, 0x4dfb406a,
2316 0xf46ffae5, 0x4d82c740, 0x1f01231b, 0xd932f595, 0x550fbcad, 0x97ac41c6,
2317 0xe3f006dd, 0x7f472baf, 0x23370a6e, 0x1e3c1b5c, 0xfafe72e8, 0xb71a9ba5,
2318 0x4b0a293a, 0x12297f5f, 0x374e29e2, 0xbc048dad, 0x192f76d3, 0xf7101487,
2319 0x25e8fb50, 0x134e1ee3, 0x134b03c6, 0xeb237155, 0xcb71b863, 0x3fdfc83d,
2320 0x274787c9, 0xf3c6f3a3, 0x5e5c422f, 0x2f33e6eb, 0xfecb78c2, 0xf045ee79,
2321 0xc23b26cf, 0xad0f60cc, 0xc630e57c, 0x7f7a8935, 0x627a6449, 0xe12fcbdb,
2322 0x31db6a3d, 0x35b7afa6, 0x6dbe429e, 0x78c7ed7b, 0xd85af388, 0x0efe8858,
2323 0x2414b70b, 0x02e72090, 0xbadf0291, 0x4d1e20ae, 0x755daf4d, 0xfc8fd0bb,
2324 0xe837a52c, 0x9638dea1, 0x171672da, 0x2bf1e164, 0xfdc7821b, 0xd4abc405,
2325 0x1c3f1c4d, 0x3a75e2ec, 0x415c85ab, 0x4a21cadc, 0x4057bec7, 0x728f0dbf,
2326 0xf4e0fe7f, 0x50bf0b3b, 0x2a26353a, 0xd7ce56e3, 0x9fcbf9cd, 0x262eaf21,
2327 0xfb8adc64, 0xe226f00a, 0xda24570a, 0x6c3c82f6, 0xc62afcdd, 0xc6dd0109,
2328 0x6db689d2, 0xf1069f3c, 0x8eba2d98, 0xc1efdce9, 0x25acf70c, 0xfd70478d,
2329 0x10f96db4, 0x8f08f6e3, 0xde236bef, 0x258f161f, 0x89ae79f1, 0x1c2ef160,
2330 0x030f10ff, 0x3bf4d0f7, 0x7c617b8f, 0x4261e22c, 0x4c5cc1c5, 0x2df6ceec,
2331 0xbe58ef1e, 0x2b8f38e6, 0xca4bd1f1, 0x5f353a05, 0xe048be32, 0xb8780cc1,
2332 0x2bae3fc9, 0x3791bc78, 0x0bd38ffe, 0x5cf107e8, 0x0a2db8de, 0x3a58430f,
2333 0x83c88242, 0x1e2c55b6, 0xe3ff7d4c, 0x3843cfa3, 0xd152ffaf, 0xf433cc59,
2334 0xd3ad9239, 0x6aff8dcb, 0xd12673f1, 0x127388a2, 0x10bd6a78, 0x26a78e5c,
2335 0x67eafdb1, 0x00b6b7eb, 0x092536fd, 0x66badbf4, 0xe62b7e85, 0x05754adb,
2336 0xafadef90, 0x960c77b0, 0x3942eed5, 0x141796ae, 0xf760b62f, 0x98937d0d,
2337 0x67a8aa9c, 0xe6eb44fb, 0xb6899708, 0x6df7fad3, 0x1b15cfc8, 0x8fb0f59a,
2338 0xbaff59ef, 0xb317f99e, 0x84fb03f5, 0xadfc6fcb, 0x8d99db7f, 0x09fa1b72,
2339 0xbce1d742, 0xe086ca9f, 0xf86e54fd, 0xa94fd146, 0xfccf56b3, 0xdfdd2e8d,
2340 0x126dad69, 0x49ba77b4, 0x7269a607, 0x6df996ba, 0x24b7fba9, 0x4abdf8e9,
2341 0xa8f7d70d, 0xc83f47bc, 0x9c271e61, 0x51c3735b, 0xc5e6b63e, 0x35a45da3,
2342 0x6965af55, 0x7fff842f, 0x935bfbdb, 0xbfac8d72, 0x371f1851, 0xd6e8c62e,
2343 0x8073f5d0, 0xaf513fbf, 0x00fff677, 0x8707cfee, 0x78e3dfa1, 0x4dbefcc9,
2344 0x6827bc0a, 0xdf3537dd, 0x5f781d92, 0x91912ad0, 0x65279512, 0xf0a59acd,
2345 0x0fef6aed, 0x477d16ca, 0xa19d1de0, 0x78102e8b, 0xefeae7df, 0xb3a29a13,
2346 0x70b7602d, 0xfa6d812c, 0x829ad6a6, 0x597216ae, 0x0edcef3f, 0x67b012d7,
2347 0xdec0b88c, 0xba4a18b7, 0x4daae158, 0xfccfddca, 0xbeaa79be, 0x31ae9877,
2348 0x83ddf4b9, 0xe7909fbc, 0xdc82481e, 0x867b8837, 0x8ac730e4, 0xf71081a4,
2349 0xc01beecf, 0xe4f915f3, 0x3fa6c7b7, 0x3081e780, 0xe71573f4, 0x27f58d99,
2350 0x9fac60e3, 0xb93dc537, 0x34af7e9d, 0x79f8877f, 0x8f9f8932, 0xf28ac4ac,
2351 0xf50f7e4b, 0xfb25cff8, 0xfb8a49b3, 0x08b9ef58, 0x63efabbf, 0x8cee7f85,
2352 0xec276597, 0x0dbf85a3, 0xc608781b, 0x03961751, 0xc31fd8e3, 0x980641fd,
2353 0xf1401f6f, 0xf5cb7673, 0x5b3fe039, 0x9eefb5e4, 0x88bcbd47, 0x338963db,
2354 0xafd876f3, 0xd7bd848a, 0xdcf961e9, 0xd9febbde, 0x3ac3b7de, 0xa1c1fe14,
2355 0xa2c56de4, 0x421f9137, 0xda12cbe6, 0xa6e4c939, 0xbd3f22b4, 0x072e4df9,
2356 0x397efdc4, 0xa78b0bf7, 0xf68dc8d3, 0xbc5791f9, 0xba46e611, 0xcec4d97e,
2357 0xe976dbc5, 0x09af1d99, 0xa78f21cf, 0x7c02de3a, 0x81da2c55, 0x762626f8,
2358 0x6c96396e, 0x1d31fee6, 0x0eae5099, 0x6eb027ce, 0x7da184b6, 0xd1eb4136,
2359 0x2ab8e95b, 0x8bf4128e, 0x33c7c638, 0xd40be9a8, 0x70e6bff7, 0x37e67ad7,
2360 0xd7c3c6a1, 0xf1aa1149, 0xc60c37bf, 0x2231f02f, 0xfdc2d49c, 0x958f9d30,
2361 0x98aac7cf, 0x814fd78f, 0x6ff74bd6, 0xebf0a2d7, 0x5b2af312, 0xdffc49d4,
2362 0x1c5d6ad3, 0xe311df7c, 0x97dbdf56, 0x840f7698, 0x2ae4a37d, 0x02a7fafd,
2363 0x3e01c46f, 0x871eaa59, 0x7ee32d3a, 0x17efea1d, 0xf67dc492, 0x7fae3b2f,
2364 0x69bd7bb7, 0xf9153b55, 0xbbed1633, 0x713f7ba2, 0x75bff71f, 0xdeea17ff,
2365 0xf66ec1ef, 0x8e946ecc, 0x29fcdfe3, 0x9df108f3, 0x1105eddb, 0xbe51c718,
2366 0xc8156135, 0x7e470fe5, 0xc2f60f14, 0xf71231fd, 0x1cb4bde7, 0xf7bb52b9,
2367 0x717bd567, 0x393f625c, 0x5846ed51, 0x3a9f076d, 0xa7bc31e2, 0xdb2dfc1e,
2368 0xb05e8637, 0xf2c9b91d, 0xc231edf3, 0x32ec230e, 0xd4cf3b6a, 0xefe4666e,
2369 0xec29bfe9, 0x9417fcca, 0xac472e7c, 0xffdc83d1, 0x17ee7cb9, 0xd65d3347,
2370 0xe2877b40, 0xce89bda1, 0xb0475ee6, 0xc23de51d, 0x7b8e2e98, 0x73134e80,
2371 0x88863f99, 0x5b942a5b, 0x7a049c9f, 0xfb8c934e, 0x7ddfc2d7, 0x2ce7b7f4,
2372 0x34a8f481, 0x131ca277, 0x5eeb1774, 0x86a543f0, 0x14e7b1f9, 0x097fd058,
2373 0x57d811e4, 0x0d34746b, 0x299ee742, 0x3c600bf9, 0x0e3afded, 0x8abf024f,
2374 0x669dff2d, 0x09aebd41, 0xb39779cf, 0xbffd80df, 0xd73b105b, 0xe8393cb2,
2375 0x298977fb, 0x6aceff4c, 0xbbfbb0d6, 0x7aeb92f9, 0x347973b0, 0x39acaa88,
2376 0xe0192ee9, 0x559f963a, 0x2892e51e, 0x8c38359c, 0x851bdfe5, 0x88d3df71,
2377 0xf3fb0747, 0xa60af00c, 0xc1624ce9, 0xf1b11674, 0xba3ae5f7, 0x9cfeb44b,
2378 0x83f32306, 0x309e9e25, 0xfa10ec9f, 0xcc6eceef, 0x3bb7d3be, 0xf37ddf93,
2379 0x19fc7295, 0x726eff9e, 0xef9849fe, 0x67b66ee9, 0xdd1bed21, 0x704fe2b4,
2380 0x21a2dcde, 0x1a9df7a0, 0x9bb41bfc, 0x24df7a8a, 0x8dd8bfe7, 0x3124dbd6,
2381 0x23674aff, 0x1d22a78f, 0xb6f6fef1, 0xd60b93d7, 0x02af7b40, 0xae3c815f,
2382 0x29be462d, 0x935c3332, 0x457cec91, 0xca5da5eb, 0xf857d20e, 0x5c87c2f7,
2383 0x86e117ec, 0xfdba4f3f, 0xbeef3a61, 0x073dfa1a, 0x02d8e5c6, 0xf74beae3,
2384 0xff8c1373, 0x40a71e05, 0xdee0d2aa, 0x068bde6c, 0xc79bec0d, 0xbf03bca8,
2385 0xa7e0e3eb, 0xb94fd34d, 0xdce7f63f, 0xfc19bb1f, 0x927a69ba, 0xe7482dca,
2386 0x842560fc, 0x64c8e7f2, 0x95f2235b, 0x883bf82e, 0x21e726ef, 0xb4ebb31e,
2387 0xd7678fb8, 0xfae7227b, 0x377f65d1, 0xb59a1f16, 0x5848cbe5, 0xef666d4f,
2388 0xed126cbc, 0x73b71c6a, 0x0736efee, 0xb26ef5e7, 0xe7cc24ed, 0x01c764f5,
2389 0xa3feb76c, 0x753f04ff, 0x7fde3eda, 0x4f1d4bb4, 0xf102950d, 0xa37f9dea,
2390 0xe39fcd9e, 0xd3545379, 0x69bfa80a, 0x2cc0774b, 0x2c7ee2c9, 0x0527e804,
2391 0xe7b33fc3, 0x0c74378d, 0xf8d17380, 0xff50728b, 0x3fef3131, 0xf38b3a0a,
2392 0x286ba70e, 0xcf9287ba, 0x80cc78de, 0x442e1377, 0xe22f5c82, 0xbafa9376,
2393 0x6fd0079e, 0xe04caf7f, 0x27ca23dd, 0x498efe0a, 0x48807a66, 0xf8f51ab3,
2394 0xc6a6cf5e, 0x36ce7aaf, 0xce7a1d21, 0xe4e5e5a1, 0x507a15eb, 0xff1fe0d6,
2395 0x2c58a7fc, 0x92412f0f, 0x42aac8bb, 0x629af7b8, 0x4c36f9dc, 0xb9b99a61,
2396 0x66bdee10, 0x207b4a24, 0x1f49699d, 0xe25df705, 0x232b38dc, 0xecb00f6f,
2397 0xca116b58, 0xc4583ce1, 0x814bfb7e, 0x1eee1c31, 0x39a170bc, 0x92df0146,
2398 0x7f28ac98, 0x2287a5ab, 0x8dc64c7f, 0x9faf7c8a, 0xefbfb5bc, 0x47c0777b,
2399 0xc3b07747, 0x9ca079d3, 0xb4656b21, 0x396d66db, 0x148ddb74, 0x4eeeb71e,
2400 0x9b036c2b, 0xcdb8fe78, 0x4fd82e05, 0xb00a5de1, 0x3ee4b463, 0xa09fd4fa,
2401 0x5f7b2d31, 0x74611e63, 0xebfc6b28, 0x799b6028, 0x3da1e6c3, 0x8c9de036,
2402 0xd5dfc135, 0x52c1f610, 0x65e9ecc2, 0xbbf6d41b, 0x550ecc95, 0xe54faca7,
2403 0x3c827fd1, 0x0ef5bbea, 0x6e97f833, 0x3763fc1a, 0x64d6e790, 0x284bbc65,
2404 0xbff2f17e, 0x1fe03964, 0x17e6a1e7, 0xe9120761, 0x6e2c83b8, 0xc5e56ae1,
2405 0xf85e403f, 0xe57917c5, 0x31fb9e98, 0xc41278f1, 0x3f1f0f47, 0x628e4b4f,
2406 0x5aaf67e5, 0xd0b8ef0a, 0x13c4277c, 0x4b9db291, 0x85efaec1, 0xf32b3617,
2407 0x2996941f, 0x95d387e0, 0x65bccaf0, 0xad43f5fe, 0x66fa8abb, 0xefca83bd,
2408 0x39d8278a, 0x639f7024, 0x992ee8eb, 0x6fdb0554, 0x4a31fe44, 0x7853f40b,
2409 0xc70bed83, 0xfef47aba, 0xc96527fe, 0xbb3b4f4c, 0x7ddff1ed, 0x6de27607,
2410 0xce46fd04, 0x5cfb3146, 0x8d29dd76, 0x177ae406, 0xb36caf86, 0xec7e0347,
2411 0x4ee1c5ed, 0x9cac83f0, 0x24fe811f, 0x866ce17d, 0xbfedc9e7, 0x7843d1b7,
2412 0xbf09efe5, 0x03ff0f57, 0xd13f379c, 0x46fb1468, 0xff9589bb, 0x6cede48f,
2413 0xeb67c8df, 0x83d03a63, 0x974261cb, 0xe252e566, 0xeeb0cb95, 0xbf003e60,
2414 0xf78edcf6, 0xd37b009f, 0x5a3eb63e, 0x29e3fb89, 0x4cd8bfb8, 0x95a3ebfe,
2415 0x7e77b2d4, 0x427dec2d, 0x7218bf71, 0xd1aeecbd, 0xbf8dfbc3, 0x2279baf4,
2416 0x843bdf99, 0xc7071f5e, 0xdca93e50, 0x3b1afcc6, 0x4aefae1b, 0x804bd6fc,
2417 0x068cf69e, 0x6dc05af9, 0x3bfdfc0d, 0xd8a17c55, 0x17b58837, 0xf78b13fa,
2418 0x3ae80f3e, 0x541fa026, 0xc6fd16a3, 0x092ce816, 0x6fea9751, 0xfc5886b9,
2419 0x68dbebfa, 0xe62df940, 0x73666ed1, 0x3e78dbed, 0x8171de1a, 0xc3ea3174,
2420 0x87fd8a35, 0x58ba73ee, 0xec455810, 0x6370ec5e, 0xe1d03e42, 0x199c44b0,
2421 0x309a9839, 0x35fb9bce, 0x27fc244d, 0xffeb4331, 0x6fd0b6ae, 0xf3bc6cef,
2422 0x3e87d07a, 0xcee7bbae, 0x24fbf401, 0xe29b9778, 0xfb7740f7, 0x81df9834,
2423 0x73f4255f, 0xfa91fc2a, 0x77f7acfc, 0xf307e50b, 0x65dd80c6, 0xfe83312a,
2424 0xfa665e3c, 0xad8b7916, 0x2a37212b, 0xe868a6a5, 0x09e4f5ff, 0xbce99287,
2425 0x01fd1613, 0x3df569f5, 0x5bea95f3, 0x26b0f285, 0xebede81b, 0x6e7f1625,
2426 0x31577c65, 0x9393ccec, 0x7d508e40, 0xf28ff41e, 0x1ef89dfa, 0xe6dcfa81,
2427 0xe7d5abd5, 0xf38dabef, 0xedcbd00f, 0x7071c96d, 0x7877388e, 0xcfd40912,
2428 0xcd56f27d, 0x021f5477, 0xdc36b479, 0xa6aef8c5, 0x6fce94ad, 0xb364dac1,
2429 0xf6e78a13, 0xa2d6f162, 0xdba7f0fc, 0xcbf3437e, 0x83370a5e, 0x9d30bdda,
2430 0x818de138, 0xa37aab85, 0xdeafbbbd, 0xd006eaf2, 0xa1d65eaf, 0xe06bf45d,
2431 0xbd7f0a1d, 0xd81706f9, 0x2c69e783, 0x8cf7847f, 0xf9193ac9, 0x060bd4ed,
2432 0x1fe75fdc, 0x2bfb81e9, 0xa50b23ac, 0x4254a9cf, 0xfcdeb4cc, 0x5db193d7,
2433 0xaf7625f9, 0x02537f3b, 0xfa0aa1c6, 0x8610bcb6, 0xd9c591f1, 0xf4dcbdb5,
2434 0x47449edb, 0xbc1c4a54, 0x975ae7ff, 0xf054f144, 0xc01f4fd2, 0x537f36be,
2435 0x47cbd21c, 0x61fbe0e7, 0xb60f4367, 0x84be39ce, 0xef05fedc, 0x0653120f,
2436 0x87895f82, 0xeece77bf, 0x7db8720f, 0xd977cd4e, 0x7e32ffbc, 0xd840c3ce,
2437 0x67cff058, 0xdca24cf1, 0x628d14a8, 0x4f942d3f, 0x3e076c54, 0xf9e037ad,
2438 0xb82c35b2, 0x0a486a9d, 0x8c2b57db, 0x49ec2adf, 0x507e8b15, 0x322b13d8,
2439 0xe7bbde09, 0xbff4b12c, 0x71f7a697, 0xd9c4a7fc, 0x4a7cc387, 0xfadf1f6a,
2440 0xf9f1e21e, 0x7e813ffb, 0x3bd89af7, 0x7c31ef6f, 0x6f02ff0b, 0xbe0ec67b,
2441 0xf429570e, 0x476db6cb, 0x7f781db2, 0x382bfc77, 0x3c6d9f0f, 0x25a654f2,
2442 0xc7cc7ec8, 0x658cec2b, 0x60fede30, 0x4b8db487, 0xb473b3f1, 0x5efc1d7f,
2443 0xeeaff44b, 0x53646cf7, 0xb6dbbc36, 0x07698200, 0x46cff2fa, 0x3ec36537,
2444 0x4437fc2b, 0x14cccedc, 0x4a947fee, 0xfbc44352, 0x0b8949cc, 0xdf83ef1a,
2445 0xe7de3aaf, 0x19f78b3c, 0x7de333fe, 0x0c9f393a, 0xef1e0988, 0x5fcf04f2,
2446 0x43d96a42, 0x43ee5c72, 0x077f0dd8, 0x67bc5658, 0x8899e5c9, 0xc0da18f3,
2447 0xb943ffec, 0x6364ab1f, 0x88432e71, 0x7aa7b59b, 0xe5640597, 0x89119054,
2448 0x113ae237, 0xc606fdef, 0x7be13425, 0x0e9337cd, 0xacc46d4c, 0x1ba29485,
2449 0x8ec491d3, 0x855228e9, 0x835268e9, 0x16a46de9, 0x09a4b1d3, 0x8dc7d253,
2450 0xff78c7ef, 0xf3adc67e, 0x0cffb034, 0x6f5c1498, 0xbfaf837b, 0x5243e04b,
2451 0x9578afbc, 0xd84518f8, 0xf121c5fb, 0x7e819292, 0xea2f0258, 0x9c31bfbf,
2452 0x119db078, 0x80f651b0, 0xef0594f3, 0x0d880a4f, 0xc42bc2e1, 0xa1c7ae47,
2453 0x2532f665, 0xe0e9025e, 0x1bd4854c, 0x19ee4607, 0x2b038ca7, 0x5e718719,
2454 0x5cec39fd, 0xe26ff2c0, 0xb1f79de5, 0x2824507c, 0x82ca45fc, 0x5c71fe71,
2455 0xef190f72, 0xb187261d, 0x6ef17ab8, 0x4230e4c9, 0xb5bf809a, 0xcf9438ce,
2456 0xde297a8b, 0x392530f3, 0x355ca00e, 0x142d23ba, 0x16670b7f, 0xb1c6ffa2,
2457 0xdb8dcb38, 0x7e3c5f25, 0xd75b0a4b, 0xc4aaa547, 0x8f1e743e, 0x77dfa7e4,
2458 0xbfafba7f, 0x04e7e82b, 0x3f755bac, 0x3c3ac46f, 0xf6313fd0, 0x2cfcf3c2,
2459 0xde6cafbe, 0xaadb343c, 0xaccd7e81, 0xdd67dfdf, 0x32cd3f77, 0x424edaa7,
2460 0x821496f9, 0x5da44deb, 0xf02dece2, 0x893bc45d, 0xbf33edef, 0xbe26eadf,
2461 0x531faa38, 0x5ca1671c, 0xd693c6a5, 0x571d0e5f, 0x5c46c4b6, 0x655be47a,
2462 0x2e3a993c, 0x3df7b68b, 0xee52abcc, 0xd3fc0b98, 0xfe91f516, 0xcaefea2c,
2463 0x1dc6acb8, 0x687114fb, 0xe3781d62, 0x1c593ad0, 0x438850da, 0xbff1f48b,
2464 0x7c134388, 0x10c3d62c, 0x72c34388, 0xf281cc37, 0x813a3fc3, 0x4e236871,
2465 0xda1c7878, 0x9a1c6511, 0x159ffbed, 0xb1de2687, 0xbd85b058, 0xdb80bfa7,
2466 0xfd060077, 0x5f7894e2, 0xc4579f86, 0xdf7ca4b9, 0xdf9eecdb, 0x041bff49,
2467 0xa7ec907e, 0xe859f9f8, 0x0fe0122f, 0x0cb5c279, 0x0fe01dc6, 0x09aff2a9,
2468 0x568277fd, 0xe9fbf506, 0x2bcfca93, 0x5c219f7c, 0xcbc7997f, 0xaec0fcc0,
2469 0x8f51a0b5, 0x1782d1fa, 0xfe82b3ee, 0x64d520b4, 0xf2b77945, 0x514be43e,
2470 0xfccf3c9e, 0x9b7ac473, 0xdea09cbf, 0xac4f3de5, 0xeff0d833, 0x404bac23,
2471 0x3e7bcafd, 0x0814f6e7, 0xebfb84d3, 0xdd1d514d, 0x536ddee1, 0xf4158663,
2472 0x5b220fbb, 0x71b14256, 0x5e9f0ce1, 0x0e98797d, 0x9603aff5, 0x74888298,
2473 0xf3b13adf, 0xf99e4275, 0x3af98335, 0x7bb136b3, 0xf6a39c85, 0xdc0b4882,
2474 0x84fbb02b, 0xefc12d41, 0x4ae7c7a9, 0xc08a7b8a, 0xcb16c9f7, 0x7fb8255d,
2475 0x6a10f760, 0xbfb8bd3b, 0x2985b22e, 0xdd423fee, 0x0ef38b67, 0x1e89efdd,
2476 0x118d7bf6, 0xc48337fd, 0xf7233dd3, 0xf663bdf0, 0xf3c0e48e, 0xa6c61dd0,
2477 0x4fabe034, 0x53731c63, 0xcb6e20e3, 0xce39416a, 0xf17ceae3, 0xbca06f40,
2478 0x073ef114, 0x20e32da5, 0x54deea1e, 0xa3d40547, 0x067b30d3, 0x9947def9,
2479 0xc5f27b99, 0xa7682dd7, 0xb7f54caf, 0x3bbff3d3, 0x1e2f5ea2, 0x59e3058d,
2480 0x5095bf9c, 0x8d0338af, 0x15f3c60c, 0x8a674ff2, 0xdbf98729, 0x4adefeaa,
2481 0xdfe5576c, 0xf167a95b, 0xad89a50d, 0x59b3af4c, 0xfa6e2cad, 0x959dfde7,
2482 0x9553ddcb, 0xf428b626, 0xe621b255, 0xbea6ec8a, 0xfdae5df9, 0x5a7f6c36,
2483 0x7e0a87d5, 0x98e8b198, 0x3a66cf82, 0xb5f9959b, 0xaf7838d2, 0x1567d28c,
2484 0x35b3c7d0, 0x0b14d469, 0xf01801f8, 0xf7cbbf5d, 0x77f11a7b, 0xcf09baa2,
2485 0x9f5e628b, 0xd8451f55, 0xc651ed53, 0xa979f067, 0x704f8bfd, 0xdc1399bf,
2486 0xf704e66f, 0xfdc1399b, 0xbf704e5a, 0x7c87e116, 0x4c8aa242, 0xe47f5074,
2487 0x828f8137, 0xc23723f8, 0xc8fe90f7, 0x0a71c7e4, 0xb7e7647f, 0xe47f0b08,
2488 0x91e7a95d, 0xec9bbb8f, 0xc43b436f, 0x9ffbd1e6, 0x23f943bb, 0xeeca9fbf,
2489 0xa5503e93, 0x22f3d29f, 0xb4f1a9fa, 0x0bd95e50, 0x37ac59df, 0xcb879010,
2490 0xf1a6d924, 0xb0f18fbf, 0x16ce5377, 0x1dfc28a5, 0x8b7f962a, 0x0f7e17f8,
2491 0xd0196f39, 0xdf7ca04f, 0xd7405ec1, 0xe71d53c7, 0x1dfd9952, 0xab2e87df,
2492 0x5fbfb033, 0xbf21cfc7, 0xebf139e0, 0x718181d4, 0x77e6a114, 0x53d34e76,
2493 0xe55e7499, 0xef153b91, 0x8af18b22, 0xfa718979, 0x5f8cb9da, 0xc50ef2c9,
2494 0xf6db6b3a, 0x63e02f48, 0x9c167ef1, 0xa904275b, 0xe8c69f1f, 0x5287cf42,
2495 0xa4bfed1a, 0x7d0f9d8a, 0xffb9adf4, 0x3ec7a013, 0x509dca13, 0x2cf3d5f5,
2496 0xf10fb1df, 0xd2173ea1, 0x0b4d7679, 0x3b9fcf32, 0x6bf5abbf, 0x4e217437,
2497 0x715097e0, 0x9b250751, 0x2d77c605, 0x4b5e96bd, 0xd2d7a5af, 0xf4b5e96b,
2498 0xbd2d7a5a, 0xaf4b5e96, 0x6bd2d7a5, 0xf4e5ffe9, 0xfffd007f, 0x8000c102,
2499 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2500 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2501 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2502 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2503 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2504 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2505 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2506 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2507 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2508 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2509 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2510 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2511 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2512 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2513 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2514 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2515 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2516 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2517 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2518 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2519 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2520 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2521 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2522 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2523 0x00008000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2524 0xffffffff, 0xffffffff, 0xffffffff, 0x00002000, 0x000040c0, 0x00006180,
2525 0x00008240, 0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600,
2526 0x000146c0, 0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80,
2527 0x00020b40, 0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00,
2528 0x0002cfc0, 0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380,
2529 0x00039440, 0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800,
2530 0x000458c0, 0x00047980, 0x00049a40, 0x00008000, 0x00010300, 0x00018600,
2531 0x00020900, 0x00028c00, 0x00030f00, 0x00039200, 0x00041500, 0x00049800,
2532 0x00051b00, 0x00059e00, 0x00062100, 0x0006a400, 0x00072700, 0x0007aa00,
2533 0x00082d00, 0x0008b000, 0x00093300, 0x0009b600, 0x000a3900, 0x000abc00,
2534 0x000b3f00, 0x000bc200, 0x000c4500, 0x000cc800, 0x000d4b00, 0x000dce00,
2535 0x000e5100, 0x000ed400, 0x000f5700, 0x000fda00, 0x00105d00, 0x00000028,
2536 0x00000000, 0x00100000, 0x00000000, 0x00000000, 0xffffffff, 0x40000000,
2537 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2567 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2538 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2568 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2569 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8,
2570 0x00000000, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2571 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, 0x40000000,
2539 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2572 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2540 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2573 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2541 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2574 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2542 0x40000000, 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x65e21f09,
2543 0x63e62860, 0x88237860, 0xcc2b4e2a, 0xfe9942ce, 0x0c0cccf3, 0x32f88117,
2544 0xe2055f10, 0xe9a48cd3, 0xb045e2b7, 0x30327377, 0x7df90358, 0x9b8b5a40,
2545 0xc8014181, 0xb3e201b6, 0x204bfe40, 0xadc40afe, 0xdc0c0c3c, 0x6a0c0c5c,
2546 0xc4042c40, 0xcdf8bcb6, 0xff2023b7, 0xaf951b9f, 0x17ca83cd, 0x3fafc6e6,
2547 0x7cbf0789, 0x6c790106, 0xf928b3f8, 0x4620e1f1, 0x2d43749f, 0xca86aeac,
2548 0x6065522f, 0xe7c40df8, 0x681ae2a1, 0x10aac5f2, 0x03329cfa, 0x7e1ab243,
2549 0xc80853b3, 0x000c060f, 0x4022bae9, 0x00000400, 0x00088b1f, 0x00000000,
2550 0x7dedff00, 0xd554780b, 0x733ef0b5, 0x27bcce66, 0x20212793, 0xf0841e4c,
2551 0x04242074, 0x11093a8c, 0x5076c403, 0xc2ab16fe, 0x25786784, 0x5ae5a911,
2552 0xc0133bff, 0x51b91688, 0x7e2da5a8, 0x68bc104e, 0x01226f69, 0x903a4483,
2553 0xbd08a5c0, 0x168b6ad1, 0xe088786d, 0x7e929205, 0xcfe956de, 0xe7dad6bf,
2554 0x9939cccc, 0x77e8f881, 0xbf41ffbf, 0xdecfb3ba, 0xd7b5ef67, 0xcfb5ef5e,
2555 0x30733d1e, 0xd7632776, 0x73941ff1, 0x4158c645, 0xf81d0ca4, 0x614b3ce2,
2556 0xc18b72ec, 0x6c64cc65, 0xe8431eca, 0x68afa84e, 0xd7588214, 0x3633301d,
2557 0x5b2bb181, 0xec46bd79, 0xb41b78dc, 0xb645d7b3, 0xd3b60a03, 0x8c8563a6,
2558 0xfe31379d, 0xb1d76f4f, 0x9916c634, 0xe3457579, 0x7e3839c1, 0x9991ab55,
2559 0x2df3fde1, 0x2beb07a2, 0x26410877, 0x27befb40, 0x7f180ca5, 0x32685071,
2560 0xe3bea0bb, 0x6765c959, 0x2f81cd6c, 0x0abce0ae, 0x4dfa9f5c, 0x7c2125cc,
2561 0x8d75a5ef, 0xb0696c66, 0x8c066a79, 0xe09774b3, 0x4b3cc1d6, 0x3ba10ab7,
2562 0x2173e027, 0xcbb8c228, 0x2b995a76, 0x9d70c38f, 0x8eb4bcd1, 0xbcc02f95,
2563 0x83670899, 0xe647b5e4, 0xa9f3f053, 0x72b981bf, 0xaf15f523, 0x5ef03cc0,
2564 0x3704aff5, 0xc75ab12e, 0xff304d7c, 0xd9e67d95, 0x7d70d92f, 0x3dae5275,
2565 0x7b951d7a, 0x834b1d71, 0x1b54d28d, 0x2d28d5c2, 0x6f191d1a, 0xcc4dced9,
2566 0x6b828a65, 0x5f00f64b, 0xfcb6bb54, 0xf054cfd4, 0xd3cc652c, 0x83f84364,
2567 0x9131ccd2, 0x22422de7, 0xbe38a963, 0xb19f1aa8, 0x99173d00, 0x6778843b,
2568 0xf477766d, 0xaa755dbe, 0xa2656df7, 0x781c6efc, 0x87de45fe, 0x2a4efd67,
2569 0xa9d3f937, 0x45dfb1fc, 0x9fc4fe70, 0xfd4fe547, 0x73fe7a6e, 0x2f95117f,
2570 0xbe543df8, 0xb2a72fe8, 0x7ea5efd1, 0x5367f92f, 0xa3efc3b9, 0xafeaffe7,
2571 0x7f15f2a2, 0x85ff3d2d, 0xbf95357f, 0xf9e807f4, 0x53d7f9bf, 0x04fb8cd9,
2572 0x16ff6ee5, 0x83f8f72a, 0xff75efd4, 0xf9f72a4e, 0x33f9e89b, 0x13283f88,
2573 0x3d3ace3c, 0x19424fec, 0xb0790273, 0xceb7af64, 0x59e4f500, 0xd7c03ebc,
2574 0x7e012750, 0x3a802c06, 0xdaa0dfec, 0xb4233ace, 0xdbc55a0f, 0x6b9c0687,
2575 0x743ed04c, 0x6ecf6f1d, 0x4331aef0, 0xde66f67b, 0xb0d83c3e, 0xc3ed02c6,
2576 0x51f6f3b7, 0xac6b9d4d, 0x85aa3ed0, 0x721adfb7, 0xfd41b5ae, 0xcf5e0ed6,
2577 0xb5aef4ef, 0x5dff3d43, 0xd5d89f5e, 0xef01d6b0, 0xdfc73c4f, 0xd9bde2d7,
2578 0x60cf9ce0, 0xee0736af, 0x4207e8f2, 0xc23e725d, 0x1cbd8cdc, 0x77d516f8,
2579 0xded4dc1b, 0x47aef81a, 0x92ea093f, 0x058fda9b, 0xc7bed47c, 0x53f6a5e0,
2580 0xbed42581, 0xfb52f247, 0x6a4ac095, 0x4b50dd7f, 0x87eeaced, 0x54bafed4,
2581 0x7549ed4b, 0xcfbea8eb, 0x8c196d00, 0xe33dd4e5, 0xcdfd0009, 0x511b7c11,
2582 0x6aeb747e, 0x12ca18ab, 0xf91d287d, 0xcd8149e9, 0x5d80fe46, 0xf27bba23,
2583 0x7c83c916, 0xc29bfcd7, 0x994cc497, 0xbeb052d6, 0x05a7e5e8, 0xd827e71a,
2584 0x71825baf, 0xce3e6fb2, 0xaa4563b8, 0xab1dc671, 0x1209c652, 0x8dfe963c,
2585 0xb26c7cd3, 0x4b639e1a, 0xa15e7195, 0x5bfd1c71, 0x8ab7b8d7, 0xb5bcf0d5,
2586 0x35e7195c, 0x7fa9271a, 0x1b7eecf0, 0xc64423f0, 0xe036fdd9, 0xd9c69327,
2587 0xf5a4e34f, 0x77fc9e0f, 0xe4e3548a, 0x8ca553bf, 0xce7841d3, 0xbb38dfe8,
2588 0x86ac99df, 0xcaa59de7, 0x9c682738, 0x575bfd21, 0xd58aeffe, 0xb96efcf0,
2589 0x69efce32, 0x8dfeac9c, 0x357de7b3, 0x3f79ecfd, 0xa27f3f4c, 0xb7fb7271,
2590 0xd40f82ae, 0x41f053f4, 0x102e7e98, 0x6ff6479e, 0xa81f3d9c, 0x07cf67e9,
2591 0x33f9fa61, 0x7fb633c1, 0xa3f82aeb, 0xfe0a7e9a, 0xcf9fa618, 0xfdf19e09,
2592 0xd3f5e783, 0x7ebcfc6a, 0x511f8c3a, 0xfb0a7840, 0x33c4cf07, 0x3c4cfc6a,
2593 0x8d8fc613, 0xbfdc99c6, 0xa33f5e71, 0x67ebcfc6, 0x1549f8c2, 0xf4775d70,
2594 0xcf135d6f, 0xf133f1aa, 0x433f186c, 0x19529e08, 0x8ce3061e, 0xbece3f89,
2595 0xecfc6a8b, 0x33f1c8bb, 0x3a27d3be, 0xce90dda0, 0xe4ce08dc, 0x0080de0b,
2596 0xa814faed, 0x30f4b0bb, 0x3d3bc81f, 0xf8d1ddea, 0x84405772, 0xc4aefb76,
2597 0xa2bb4ff1, 0x58e96ff5, 0x8263975c, 0x3877654e, 0x7aaa2d8b, 0x4a925952,
2598 0x6454a73f, 0xb369eaa8, 0xf4f554b2, 0xdeaa4707, 0x5e3058cf, 0x7cbc1f55,
2599 0x643eaab2, 0x7deaa955, 0x55d3e3d7, 0xeeeb59ed, 0x3673d555, 0xcf554f7c,
2600 0x554f3cdd, 0x54badbcf, 0xedc8de35, 0xd1f5552b, 0xd5531ebb, 0x51acb6c7,
2601 0x4f6dddd5, 0x3be3eaab, 0x3f8d539e, 0x54cff8e1, 0xb777c2f5, 0xa745eaa9,
2602 0x3fbd555e, 0x1a6bdcf9, 0x3ce6c6fb, 0x8bae4a3f, 0xc95acf68, 0x910e33ce,
2603 0x192d5ec8, 0xa3faa262, 0x7f546c43, 0x70df0ef4, 0x8fe3ec27, 0x6bd005f0,
2604 0x5bbe4a8f, 0x2fec319d, 0x4b1d39d8, 0x63a7d2c7, 0xd7db7d45, 0x80ce801b,
2605 0x5e874a2e, 0x650d3dcb, 0x3727ae8d, 0xe8dfca11, 0x2e916a4a, 0x4474151f,
2606 0xd591567f, 0x8d58dd22, 0xfd70e88c, 0x0297c2b0, 0x54f87451, 0xcaf39726,
2607 0x6a194fb8, 0x3eef51d3, 0x0066f756, 0x9993f2f5, 0x664cbc60, 0x9bc287ec,
2608 0xbc0e40a1, 0x3a68f99f, 0x09268bda, 0xf9e8d0ec, 0x347f9825, 0xf9c01fcd,
2609 0x6fcce3eb, 0xcd522dca, 0x52aace6f, 0x60966fcd, 0x4f63277e, 0xe7961dd7,
2610 0xffde9137, 0xe6987091, 0xa6ad6537, 0xac4bd7f9, 0x25bf354a, 0xf2037f3c,
2611 0x7f38f3c1, 0xe7f58c41, 0x3faf564e, 0xfd7aa96b, 0xcfff5f12, 0xf3c84eea,
2612 0x3ffd685b, 0xf5f04e17, 0xd7c63d67, 0xa371846f, 0xf18477e7, 0x5ff9c41f,
2613 0x69bf338e, 0xfd7ab178, 0xebd5cbd9, 0x5ff9f237, 0x9e4f7bad, 0xfff346df,
2614 0xaf8f7842, 0x9a71fb3f, 0x75ac68df, 0x38c9a13b, 0x441b52d4, 0x2fe600b9,
2615 0x050c801b, 0xc6444cf3, 0xde0c6248, 0xd164285f, 0x016a3c3e, 0x9ffe83ba,
2616 0xd0de8059, 0x72ed977e, 0xd017ac16, 0x6996af0e, 0x4aaec17a, 0x657819e9,
2617 0x57f72b41, 0xc333f818, 0xad2bbe00, 0x11fd9fbd, 0x7db05de0, 0xa025c91c,
2618 0x2def8674, 0x23529794, 0xe6307c72, 0xe413321d, 0x877bd329, 0x9a863bdc,
2619 0x2fd7683c, 0x1f630466, 0x60d85e3a, 0xc515df38, 0xa8b78b6f, 0xea824beb,
2620 0x097702ba, 0x81940912, 0x0b579652, 0x7f079ef3, 0x7ddd8180, 0x2c6dec06,
2621 0xb9b0313f, 0x0e7e785e, 0x452605fc, 0xed1d55f3, 0xabbd79cb, 0x73d61d3e,
2622 0xc3704abe, 0x0d81ec88, 0x3a196395, 0x7bcf0172, 0x77ef0039, 0x852ff298,
2623 0x7273e9d6, 0x003617f8, 0x7ff1477f, 0xb0bbc88d, 0x0ee08517, 0x7fbfe790,
2624 0xba054573, 0x83d7d0bc, 0x5e577def, 0xc92de2f7, 0xde98f7aa, 0xa9cdef44,
2625 0x1ea20c4c, 0xc36ceef8, 0x3b552eb9, 0xf1c03f30, 0xdd0fec91, 0xf1eebacf,
2626 0xdfb99e82, 0x75d7eea7, 0x8dd1eac0, 0xbb4b7285, 0x3dbec181, 0x8719a550,
2627 0x1f7f6879, 0xa878e192, 0x973edd56, 0x5fd42539, 0x9fab5773, 0xe3b40657,
2628 0xcf00f800, 0xf81c793c, 0xe6f844e7, 0xd7f36dcb, 0x7daa021b, 0x0a947a02,
2629 0xa22cf6e5, 0xbd0f5a02, 0x3fb7dd9f, 0x434041d0, 0xfb588107, 0xf9f7fffe,
2630 0xae7d8dff, 0x3e492d69, 0x8ad70517, 0xe7c969a6, 0xdb2dfaa2, 0x5f555339,
2631 0xd55fbc12, 0x4a96f17f, 0x86c2fb55, 0xf9f6aa25, 0xd5561feb, 0xa4ff032b,
2632 0x75773fea, 0xa1fdaa9d, 0xed54a7da, 0xab3d540f, 0xfbefdfaa, 0x77ffaaa9,
2633 0xdaaa3767, 0x864b0385, 0x46a8dc62, 0x881d0df2, 0x8df7aef1, 0xa1109b6c,
2634 0x2fae855b, 0xfca9d3f8, 0xb2a2efd4, 0xc830e50e, 0x5e3edd75, 0x1cab6cd6,
2635 0xa15bf28a, 0xb50c4ff3, 0x69fe5043, 0x672b55e9, 0x6325d0fb, 0x88bed083,
2636 0x2e596717, 0xf3ca2f30, 0x19db816e, 0xb213f3ca, 0x0d6c675e, 0x8972d7f1,
2637 0xd7f2dff3, 0x3f229606, 0xb942972c, 0xe3f8b6b5, 0xd68126b2, 0x1a36d8c1,
2638 0x10704967, 0xfbd17918, 0xf382ad9a, 0xe69141d2, 0x6e1f46af, 0xdec1da12,
2639 0x3f9c3a0d, 0xbee43ed4, 0xe78f0831, 0xc1c01d19, 0xdf49535a, 0x2797f25d,
2640 0xfe23d39f, 0xf05e54bc, 0xbcf2a6cf, 0x39e547df, 0x6795157f, 0x7654b5fc,
2641 0xf95357f9, 0xe5403f91, 0x2a7aff29, 0x5037f03f, 0x85bfd279, 0x83fbdfca,
2642 0x7bf15e54, 0xf4e854a8, 0xb57d96ff, 0xf2bdb8e8, 0xffafb8df, 0x16afbd1e,
2643 0x23c3939d, 0x0d06ebef, 0x55794abc, 0x61797027, 0xf31676e4, 0x788e2958,
2644 0xc3078955, 0x94571448, 0xf0ddc1e3, 0xd3f62777, 0x1831e537, 0xcfe8eaef,
2645 0x7b8e3173, 0xb191a4f5, 0xd3ebf8cc, 0x3c5c5fee, 0x46ee80b0, 0x3858b7f8,
2646 0x72aa015e, 0xdcec1e36, 0xf3dd7b11, 0x92cf5d78, 0x7726fdf0, 0x3c355c74,
2647 0xc072e22e, 0xd16af1cd, 0xdacf7b71, 0x847c722e, 0xb3efbb76, 0xc6b5e847,
2648 0x718b93d8, 0x2347f662, 0x36c63d43, 0x055871cb, 0x575e015f, 0x3a7ff5f0,
2649 0xfda04e3e, 0x1f1f105b, 0x47e0a5dd, 0x32bff0c4, 0x574aafc5, 0xae90439d,
2650 0x7bf4cab6, 0x027865b5, 0xe7191d1b, 0xd38b9d6e, 0x7ef04df5, 0x0e4be8f5,
2651 0xa657f3b4, 0xf2e79ceb, 0x456fe3e3, 0x16d3a653, 0xaab4a76d, 0x841b57eb,
2652 0x70371e72, 0x831acc25, 0x3ce9d1f2, 0x2c728397, 0x9c654a9d, 0xf392e995,
2653 0x0bf6325c, 0x2576f872, 0xea7e5f12, 0x6fbf5137, 0xe3788e1a, 0x6168e044,
2654 0x247de167, 0xf1d9ebd1, 0x3ba5c7fb, 0x8c245ffd, 0xc336b0c7, 0x985f6867,
2655 0xd1d7ffe0, 0xaa7a63ee, 0x34d6e32b, 0xade30189, 0x6a977cf8, 0xa5cf783e,
2656 0x67ae94e4, 0xf5be88dd, 0x7f42bcec, 0xa0e7ca20, 0x1079489d, 0xbf6d53b3,
2657 0x35eaaa24, 0x2a9d03ad, 0x00ff067b, 0x04cac739, 0x72c1d23d, 0xf5ba2c99,
2658 0xc002f5b6, 0x2e9d0937, 0xf78147a4, 0x92ea615b, 0xafa42e7c, 0xcdb9dfb5,
2659 0x681b3d85, 0x60f85abd, 0xf5ea66ff, 0x265fe1f1, 0x1bd47d5e, 0x22d7fe83,
2660 0xd01ea3fd, 0x999f3f71, 0x43e40e02, 0xdc701e96, 0x6cc3fc4b, 0x9ae0fc61,
2661 0x5513cc19, 0xff01c657, 0x5f6d47ad, 0xa4bbbe72, 0x76bbfee3, 0xbcf2cdde,
2662 0xf55fc337, 0xe2a7b7ae, 0xac78b5ba, 0xe4b3fd6e, 0x5314fca3, 0xefc151e1,
2663 0x59bbd124, 0xee97f984, 0x7f212d3c, 0x7204305d, 0xb903787f, 0x5b7e17df,
2664 0x646b79fa, 0xd8f72b9d, 0xf95fbec9, 0x0bd79cac, 0x779c4eb0, 0xf13c915e,
2665 0x0515e835, 0xa67c6807, 0xd3d88c2b, 0x5e6d7e4a, 0x27f232cb, 0x0901663e,
2666 0xc51792e3, 0x9fb44286, 0x4a353697, 0x32f3801e, 0xbe2395d3, 0x1c77b32e,
2667 0xb5fb51f9, 0x9f08944f, 0x899f6760, 0x6cec1386, 0x6cec1d55, 0xbb117d55,
2668 0x51f30d37, 0xc01b368b, 0xaa75a7c5, 0x9d115fda, 0x5662ee34, 0xc9768f5b,
2669 0xeffc96d9, 0xf0fb86dc, 0x88850bfa, 0x3cd079df, 0xf8f10928, 0xcbf1e136,
2670 0xdf04bfce, 0xde77df1f, 0xf26add08, 0x561e328e, 0xc13c14ec, 0x44737418,
2671 0x7d0ad796, 0x5f8641fd, 0xc59c0f89, 0xdea4417a, 0xa17fa9ad, 0xfe657fa9,
2672 0x4bba014d, 0x24f7ec8b, 0xe91677d1, 0x38f906ad, 0x5fb7c221, 0x3ef4fc79,
2673 0xa37f77e3, 0xf3560fe3, 0xc5ff8c0d, 0x4e7e3a37, 0xfa8df81f, 0x77e3be82,
2674 0x59631d9b, 0xc4a9d902, 0x3a71815f, 0x1fe9bbf2, 0xd2136bda, 0xc0a69fc9,
2675 0x39ddd638, 0xd9a38c41, 0x14e99dcd, 0x54bf07d7, 0x6024f30f, 0x0edf907f,
2676 0xf9f016e6, 0x2cd37ed3, 0xf8ca8794, 0xe55eb776, 0xe914267f, 0x7b28fe35,
2677 0x61f00737, 0x38a6a793, 0xfcedd41b, 0x5b6b666f, 0xe30b7c4c, 0x04e8fca8,
2678 0x2ffe45d6, 0x9e7aa78c, 0xa1d59a38, 0xa8f44a1a, 0x6d154f9f, 0x9c4b6f14,
2679 0x9c4e28c6, 0xfad7ae5c, 0xd2c315f7, 0x4740e0a2, 0x32c9ea1b, 0xcfa6e01c,
2680 0x67fde014, 0xf08cf4cb, 0xc5ff8012, 0xbc593380, 0x01f9c216, 0x39df155e,
2681 0x65f540f2, 0xe7aabc11, 0x4d19e700, 0xe50f207c, 0xb8b31246, 0x53801e71,
2682 0xdbd1eed5, 0x0e1e2853, 0xa3e517f2, 0xc989d4cd, 0xaaef9c7f, 0xf4ebaf0a,
2683 0x190b23e9, 0xfc385085, 0x942fa601, 0x83ef8bf7, 0xd313bfaa, 0x8f04d9d4,
2684 0xd8361c7a, 0x6f8f2d19, 0x8309fd95, 0xe9133bc1, 0xad6870aa, 0xa717f388,
2685 0xaec872bb, 0x3a214b68, 0xca5d5acc, 0x685d42ce, 0x9cf78460, 0x39ef1c0d,
2686 0xf71e3a3d, 0x0e09675c, 0x268cb183, 0x9c833016, 0x301cad02, 0x8259c78c,
2687 0x5ae49fb2, 0xcd3cc3a3, 0x7829a07a, 0x54a7adaf, 0xa73610b7, 0xfc609b09,
2688 0x3e3de96f, 0x67c1c63d, 0xe375d2fa, 0x9ae161f0, 0xa5a0c18e, 0xb8211b19,
2689 0x05080b41, 0xc2de8e87, 0xdf184a43, 0x790f4185, 0xd72ed46c, 0xdaed0859,
2690 0x2faf0b06, 0xae9417d7, 0x988ff787, 0x5d71cbbc, 0x891ce4cc, 0x4a162b79,
2691 0xb7c6f5a2, 0x0724024f, 0xb6f2b815, 0x4cb54d77, 0x2814fe40, 0x1ecc3fcf,
2692 0x24255bb6, 0xa5361dae, 0x6ed0921e, 0x2dbcb6f5, 0xa2bb7fa1, 0xd76a6de9,
2693 0xa1ca1d61, 0x07535dc9, 0xd4f88981, 0xf4d2b2ba, 0x4b5e3011, 0xd60eba65,
2694 0xb2badcf5, 0x4f75ea43, 0x1c51d35b, 0x775eb759, 0x77dd66b7, 0xcfdd70df,
2695 0x5d2eefe9, 0x75ffdc5f, 0x8b3fbec2, 0xa25199f8, 0xeefe510b, 0xf0282da4,
2696 0xec99bb78, 0xc69c7941, 0x1287f638, 0x7e718437, 0xe850eb8a, 0xa14f7947,
2697 0x9174789b, 0x79239ccd, 0x1f4d503e, 0x6d9ef4c7, 0x7a4bd708, 0x4054894f,
2698 0x787b25eb, 0x2ee7cf86, 0x2dd08fcb, 0xd1f2f9b3, 0xe61832be, 0x57e702fd,
2699 0xb2519ae0, 0x7802cc52, 0x21ec6177, 0xd49eb235, 0x2e7301d5, 0x03d533ac,
2700 0x7be177d8, 0xcf7c66be, 0x8427bb31, 0x32262647, 0x4620be5f, 0xaf995ee8,
2701 0xdf1e4dfe, 0x05d4afaf, 0xed5c90d7, 0x08bc7012, 0xe869743d, 0x43d387a1,
2702 0x87a269eb, 0x9cd3b6ea, 0x4aeb5a1e, 0xdbaa9e91, 0x85d1a704, 0x8719eaeb,
2703 0xebeffcfb, 0x61ea97e6, 0x7b5a879f, 0x1d0107ea, 0x69655818, 0x7af09985,
2704 0xb3ebe118, 0xca7c323f, 0x6fede2ba, 0x1facd1c3, 0x707d468d, 0xe61ee75c,
2705 0xe94de08a, 0xd12f4977, 0x7c906c3e, 0x295e90ef, 0xcb823aea, 0x3be8ed7f,
2706 0x1c5bb40e, 0x883defc7, 0xc1663bef, 0xf322b90e, 0x535f1c36, 0x1a67e78a,
2707 0x64381d60, 0xa009eb02, 0x1f1f13dd, 0xf8c25f9c, 0xf84d3968, 0x9e1d61d1,
2708 0xa7e72abf, 0x5ec8cf80, 0x7ee56a19, 0x1e7ac7ee, 0x5e9bfb3f, 0xef6e4b94,
2709 0x2abf1ea6, 0x5c4fd0b9, 0xa9fea3a7, 0x5e8e8e58, 0xf7ea3aff, 0x055e5437,
2710 0xfb287c11, 0x4813d0a9, 0x5fe62b4a, 0x577c5996, 0x6493f4d5, 0x4f1a8acd,
2711 0x9fa36f79, 0x7f8017b9, 0xde63b137, 0x81ff2823, 0xf543fe7e, 0x198318de,
2712 0x47f4a6f1, 0x3fb58cfa, 0x14331ef0, 0xd05c79f0, 0xa563b9bf, 0x7f617688,
2713 0xf650b5f7, 0xacad0b8f, 0xbf7835f6, 0xac4a0130, 0x01f5cb27, 0x2f107d72,
2714 0x75b94fb3, 0x946f3c02, 0x6e9effb8, 0x7a92e390, 0x3bcc48e7, 0x3db81ba5,
2715 0x923e9c58, 0xb7c2bee4, 0x2484be88, 0x58021b32, 0xe964f566, 0x3e14df70,
2716 0x42e8f7d6, 0x594a5076, 0x0dce977a, 0x61f98fcf, 0x9ff037dd, 0xbd108fa6,
2717 0xd1d1ecb1, 0xfcbf5d06, 0x5276b898, 0x6c3b1f57, 0xec9521b4, 0x42f78da3,
2718 0xaf447abd, 0xc6b5fb84, 0x8ddb7d5a, 0xe169efce, 0x13ed763f, 0x577bfa07,
2719 0x8f2c6afe, 0x5078f715, 0xff51dbc6, 0xb14f7a6c, 0x30ab68a3, 0x3ec0cfbe,
2720 0xd70bf0e2, 0x7d92548d, 0x3c890774, 0x3e80c7dc, 0x55a7f509, 0x777e73a0,
2721 0xebb3fa46, 0x8477e7c0, 0xb1b05696, 0xb72bf950, 0x3ff04c6f, 0xe98faff4,
2722 0xed1e747d, 0x9a79e318, 0x3b6d6b42, 0xd33199d6, 0xf985c3bd, 0xa29e753e,
2723 0x2ca1a130, 0x42489509, 0xc533cd26, 0x0e4f69a4, 0xb2fe51e8, 0xe71e4cec,
2724 0x945f3062, 0x44f40e9f, 0x7c3658f9, 0x3395d924, 0x65dd2af2, 0x48bdfbf2,
2725 0x731b7eac, 0xfae44426, 0xeefdd734, 0xd1dd9532, 0xfd3946e0, 0xe245dfd6,
2726 0x7f1e2d6b, 0x7d7ce065, 0x9775efd4, 0x63c5f4e5, 0x67584ba9, 0xa7c5f577,
2727 0xfc5a5f16, 0xc95fc3c6, 0x52597729, 0xf1693c0c, 0x46ff0c72, 0x06368f3c,
2728 0x9de20203, 0x4b98e9e3, 0x78188160, 0x29d2ec52, 0xa4683176, 0x9dd90f76,
2729 0x68f0c977, 0x4f17d6f1, 0xd2bb8a9e, 0x411ff022, 0x4e91e87c, 0x884aefdc,
2730 0xdb0304ff, 0xdd0ceb81, 0x6ab7f949, 0x434c1fb9, 0xf93bb579, 0x8375e150,
2731 0xf087707c, 0x386301bd, 0x6d55fd7d, 0xb83dde7f, 0x14a0dd72, 0xfb9803c4,
2732 0xd4671f1c, 0xf1b8c374, 0x7da4cd61, 0xdba8fc07, 0x587e3993, 0xcbbf6f32,
2733 0xd0d769a9, 0x0abd768d, 0x3e1bfcdd, 0x3f17d498, 0x30ecdd0a, 0x067276c8,
2734 0x1e788c1b, 0x02426fbb, 0x78da2dc5, 0x4f4b5ede, 0xc37a4f13, 0x47f4c8e3,
2735 0x5f3025f4, 0xfb33b9f8, 0x569bc86b, 0xf25166d0, 0x7be8b866, 0x51bc9623,
2736 0x7976fff6, 0x81676e9f, 0x4b03a283, 0x74c25ffd, 0xff591993, 0xda275c21,
2737 0x20d883e7, 0x8318e75c, 0x7969cb8b, 0xcb75e19d, 0xe58a09e7, 0xb64d8bf9,
2738 0x7acb8e10, 0xf8c297f4, 0x5cf8a2cf, 0xc08a4a40, 0xb3fb9061, 0xdb8cb521,
2739 0x79d20f5d, 0xbb0bc01c, 0xf1c08d6e, 0xa7a08307, 0xc70c9578, 0x80a69de5,
2740 0x57ac2b78, 0xf511fdf4, 0xf8e125d6, 0x3e9f5a58, 0x4a7a8b94, 0xdadbdedb,
2741 0xd0ed8d51, 0x93f5116f, 0x71865fe1, 0x9ea7a007, 0x6dc18d37, 0x8a48e231,
2742 0x4a6c093d, 0x83e15cf2, 0x6505513b, 0x92dfa5f7, 0x1c7af1d6, 0xa5b74b5f,
2743 0x1da159e0, 0xbbd7a5aa, 0x7c1ccf58, 0x4553a5ae, 0x7a597eaf, 0x30a9ec50,
2744 0x74d4845d, 0xd003d0a1, 0xfa42ffc7, 0xf1f09ee8, 0x9efe68f3, 0x169bd098,
2745 0xbd810f4b, 0xeca293a7, 0xb3f678e8, 0x48273762, 0xc7da333e, 0x595d797a,
2746 0x9e1d2e79, 0xf25dba8f, 0x62b9f058, 0x0fccdc4f, 0x80e01d60, 0x91cc7d02,
2747 0x83a4ddf1, 0xc0dbe006, 0xf288214a, 0x63d621e6, 0xaa1ef9c0, 0xc9fca835,
2748 0x8f9ee639, 0xe6fd087e, 0x3d270dd4, 0xbf28c3e4, 0x38f3ef48, 0xffcf3d44,
2749 0x5c9ebcb3, 0xaee6bff4, 0xd1fc6836, 0x39e3a224, 0x23ecfe4e, 0x09303be8,
2750 0x4d4aedc7, 0x76f94d1a, 0xfced7f55, 0xe3b43aca, 0x91abdf6a, 0xee78b2e3,
2751 0xf7851dca, 0x83b71251, 0x131ef0c2, 0x6f80bc39, 0x6aebac1d, 0xd3e088db,
2752 0x2954e831, 0x8e5d267d, 0xef52393e, 0x3b38d37a, 0x955f6318, 0x3f7c1479,
2753 0x7c153ac8, 0x0e8b1e7e, 0xffdc7d8b, 0x910e6dd6, 0x2f1dacbd, 0xec8ca7a7,
2754 0x81269cb0, 0x4de5deec, 0x2af9ba25, 0xa3fb9bfb, 0xa6efec7d, 0xf2de3483,
2755 0xfedc8396, 0x3b23aa6e, 0xf70b797e, 0xa43ec047, 0xc80463f3, 0x15cbb268,
2756 0x7983d33f, 0xb79815a2, 0xbd21ede4, 0xf3d5cf0b, 0x78d235fe, 0xf21ca9f1,
2757 0xc0ff7913, 0xa7e8b5c4, 0xa85afd86, 0xbab5fb47, 0x9576c2ba, 0x6c281b5f,
2758 0x5b5f91bf, 0x05385f53, 0x8fe05afd, 0xcdc15245, 0xe4b663f9, 0x797fa1ba,
2759 0x41ade4c4, 0x02e2533e, 0x6abffdda, 0xfd202572, 0xbdfb253d, 0x23cf57d3,
2760 0xfc3cde7b, 0xa37990da, 0x7df2de51, 0x76e24c7f, 0x7be88a4b, 0x3eebc70c,
2761 0xcf172d74, 0x7fb4d4cb, 0xbcf911ba, 0x1ec3ce4d, 0x5d9157f7, 0x13dfeca3,
2762 0xa777b712, 0xa077688f, 0xc14f7ffd, 0xcfe81cef, 0xbcf3d65c, 0x4922a5cf,
2763 0x18f66f65, 0xd7027aee, 0x1e8094ad, 0xf16ee511, 0x82938e84, 0x8ffcbe23,
2764 0x808f77c8, 0x7b5d9df2, 0x5bd70d3b, 0x81d872d3, 0x7e84bef8, 0x5bc9c610,
2765 0x8f30d3da, 0x77f9a2b8, 0x9e7bf40e, 0x7b5db897, 0x40e9df59, 0x1ef96ebf,
2766 0x5fc9dbb0, 0x003da50a, 0x32d4ba78, 0x3e69f0bf, 0xbf5a298d, 0x85f57fe1,
2767 0x76edbb11, 0xeb282053, 0x284e253b, 0xefa1875c, 0x663d116c, 0xedfb5f47,
2768 0x4dacd1f2, 0xcc0fb815, 0x0f861ee0, 0xec83acf5, 0x09962539, 0x21cf0a92,
2769 0xbf2b901d, 0xefbde96e, 0xe7162236, 0xda0251ba, 0x0c14be3d, 0x8db69592,
2770 0x9188375b, 0x73d950be, 0x12ef7b5a, 0x1b77dd73, 0x7aa3b9ca, 0xd6b37686,
2771 0xfdd163fe, 0x9f7fe387, 0xd6bcbc25, 0xfdc56d92, 0x59d320da, 0x54ef4b4d,
2772 0x166a97e4, 0x6f7e0efa, 0x3a22dd55, 0x7246ec43, 0xf85bdd77, 0x9b7753fd,
2773 0xd8f485c1, 0x34d876dd, 0x22adeb16, 0x4e6a99c5, 0x3a428f14, 0x2866d2ba,
2774 0xbcd7bc47, 0xf903b1f9, 0x57cfd15b, 0xde7a44da, 0x9e9676dd, 0x695ee32b,
2775 0x7a851e4d, 0xfdc759a5, 0x9f238ebc, 0x7fdf915b, 0x326aed7d, 0x7eb297f9,
2776 0xaaa7618d, 0xddad4eec, 0x6e19e53a, 0xb5494e47, 0xec579c93, 0xf8fa3ecb,
2777 0x67675b14, 0x6b1f425f, 0x4919f0f4, 0x616ef3b6, 0xd8af31e3, 0x19792d7a,
2778 0x9b7765f2, 0xe286b9d5, 0xe88edc1e, 0xb9f4f8ee, 0xb8fcf819, 0xee9c7148,
2779 0xf1d1226b, 0x86cb03a1, 0xf1a2d976, 0xf5fb4f5c, 0x5f3fc0d9, 0x3ffd0fd9,
2780 0x07716c3b, 0xf77a7d70, 0xd63daf28, 0x78e504be, 0x97432841, 0x4320658e,
2781 0xec35f457, 0xe27d93c4, 0x7f91d7f7, 0xa67a9857, 0xddcd18a2, 0xfe425a7a,
2782 0x057920df, 0x2687e923, 0x8075f22b, 0x73c20e95, 0x561655cc, 0x53d4f48a,
2783 0xa0db9cc7, 0x9d51cf75, 0x30fb04ce, 0x1ba64761, 0xf955edb7, 0xa692f35c,
2784 0x4a332906, 0xbf912c5e, 0x0860bb3b, 0x7a8a490c, 0xcb91a4fe, 0x97870bab,
2785 0xeef248be, 0x161b237d, 0x362dbf43, 0x5bb57d72, 0x85d8cc0a, 0xe8e8cefd,
2786 0x238ec1fb, 0xf3c11c6f, 0xba4e4b10, 0x28bea1c6, 0x6ffa7231, 0x3d6afe3d,
2787 0x3d690b9e, 0x76f478c5, 0x83a8a57b, 0x1733f779, 0xabbd3f8f, 0x1c23ff23,
2788 0x649e63b7, 0x461de75c, 0x1ff6672e, 0xc74795d5, 0xe7cbf605, 0x1a356e1c,
2789 0x4661fc68, 0x8ed7ca91, 0x23cf2696, 0x19e5f3be, 0x75ceef91, 0x915c3bd5,
2790 0xef629578, 0xb5f77a4c, 0xcfe06319, 0x4e749749, 0xbbd76edc, 0xaf5c44db,
2791 0x896302eb, 0x07fb5f42, 0xf88f1bc6, 0x7fdbc657, 0x70078f89, 0x54be421c,
2792 0xf41a0ff0, 0xbea1a347, 0x849f53bf, 0xf82813df, 0xcca1d657, 0x9e626aef,
2793 0x8eb11b46, 0xc41bb5e7, 0x8f52314d, 0x54ef91f4, 0x7449cef8, 0x29e486f9,
2794 0x1810f4e5, 0x870bf582, 0xec57642d, 0x4b11f596, 0xf88a1caf, 0xbe69f653,
2795 0x0513eb91, 0xcff3789e, 0xca54e191, 0xafd74b2f, 0xa2015c1a, 0xc5023d9b,
2796 0x90815c19, 0xfb053b29, 0xe739d365, 0x37d8de48, 0xbd87f707, 0xd6ffa6ab,
2797 0x8ace9d2e, 0x214df1f2, 0xfde0d291, 0x74c34fb4, 0xfa226fa6, 0x88c93d6b,
2798 0x7cee978f, 0x58cdc798, 0x728e9068, 0xc84181c8, 0x9c3fc8b7, 0x0503437f,
2799 0x35b52728, 0xf8441dae, 0xaf90390d, 0xbe027822, 0x41b6b2c1, 0xb25d7a42,
2800 0xe58b978a, 0x6c9647ef, 0x2e7f11f1, 0x15395ada, 0x98d5a7ed, 0x28bd40f4,
2801 0x59d32bd3, 0x4ebcf032, 0x85df6caf, 0xdd3897e1, 0xd4d96c5e, 0x7d02f38e,
2802 0x63e233fd, 0xcfb3eb72, 0xbd0ab823, 0xa06edc5e, 0xde90aa71, 0xad74f8a3,
2803 0xde7bafbc, 0x693ef4e5, 0x7bf4a1bb, 0x0149eeb0, 0xec38c4e6, 0x443bedfe,
2804 0x91fbdf94, 0x9f39339e, 0x70be9ea3, 0x63eb69f8, 0xeb4ecfa8, 0x777bc618,
2805 0x39aaac4b, 0x1a3a2f8a, 0xeff1575f, 0x33759dd2, 0x95dcae28, 0xa66ba024,
2806 0xf782adf0, 0x1a7b92dd, 0x34b7fff1, 0xdfc65ffc, 0x81ff87df, 0xfe649b7e,
2807 0xfc0e54df, 0xb7128f0f, 0xce380a27, 0x79f6296e, 0xfd8d57a1, 0x5710b73b,
2808 0x23ef1eae, 0x72355f57, 0x0d91dbff, 0x73df57f3, 0x30effc95, 0x6cdd327c,
2809 0x26e8532a, 0x7b71f053, 0xf8839753, 0x3d22bc02, 0xf289bd93, 0xb82b24b6,
2810 0x8f45884d, 0x967c946b, 0x72236f8a, 0x5f5fe14d, 0x5853c21b, 0xed16bb56,
2811 0x008ae4e4, 0xc145e9d1, 0xf4093437, 0xe7e445da, 0x67e17218, 0x333e5e32,
2812 0x1be754f8, 0x32c1c2fb, 0xc0abae90, 0x69f3a2e3, 0xee27055b, 0xdaeed28f,
2813 0xf782fdca, 0x9e573e65, 0xf915ffbf, 0x53f78c3e, 0xeface27d, 0x933eb91b,
2814 0xdcceb04c, 0x4c67d720, 0x60be2528, 0xc819e9ba, 0x8f404b6f, 0x8f4a2f7d,
2815 0x1034345d, 0x38782abd, 0x67fbd32b, 0xcfdd7c89, 0xc41e70c9, 0x5be12998,
2816 0x7a0947ce, 0x5af9c0bd, 0x8bbf3814, 0xc3c5fe38, 0xdd11a793, 0xee9b13df,
2817 0x246aed97, 0x772c4cfa, 0xb3b9438e, 0x2736ef49, 0x8f258e8e, 0xec765483,
2818 0x49f909f8, 0xf7c8c748, 0x0aa0f8f1, 0xa0c580f9, 0x7fd020ff, 0x7429fed4,
2819 0x1d717400, 0xd73ca5f1, 0x379285d2, 0x5bb2f053, 0x669b7793, 0x601a78e2,
2820 0x25def2e2, 0xfa78a9cb, 0xf3ef2be5, 0x2bf87dbb, 0xe6a054cd, 0x456fdc2f,
2821 0x13717c4e, 0xe2679b3e, 0xfa644fed, 0x780ede4e, 0xe4a0627a, 0xeb720b5a,
2822 0xe766d809, 0xa63e48f8, 0x595f9e49, 0xa09348c7, 0xf368dbca, 0x6f830629,
2823 0x9f0a2984, 0x8d73f798, 0x334bd08e, 0xd81cfce3, 0x43cf946e, 0x5f765538,
2824 0xc6912981, 0x40c1ea77, 0x967fd405, 0x0361d959, 0x0ceeeeb8, 0xe1718c54,
2825 0x5981db77, 0xbae264f7, 0x853e829c, 0x53ace5d6, 0xdf20ce8e, 0x7c50b71d,
2826 0x3ddb3f24, 0x974cfc8a, 0xf7c71f3b, 0xeca4fbc8, 0x6b75bc67, 0xfdbc5cf5,
2827 0x21e3279c, 0xcad76e55, 0x2e26418f, 0xf9657a37, 0xf83fe5a1, 0x526f9317,
2828 0x3b242fb7, 0x6d8c9d90, 0x326fde07, 0xff5179f0, 0x00d4bf40, 0x23ddfeff,
2829 0xdcec27ef, 0xc343c41c, 0xa39d2376, 0x31d7f850, 0xf18e9bcb, 0xe48a4713,
2830 0xaeb8c176, 0x7e1a6c59, 0xe8f2efbf, 0xd651bfc8, 0x26e1ff5f, 0x7ea26fba,
2831 0x7da19187, 0x57ef209f, 0x0c162cc2, 0xbaf9f109, 0xb1e80763, 0xd3fe2894,
2832 0xee89eb07, 0x5103bf80, 0xd93437fc, 0x2d806e97, 0xdbfac1fe, 0xc0b74cca,
2833 0x8ccc993c, 0xa82aea16, 0x347c006f, 0x96047924, 0xb675f548, 0x0fe3f181,
2834 0x2e4d303f, 0xbf04f3c3, 0x6fbe7a32, 0xc438a54a, 0x1c2cb00f, 0x28b22b50,
2835 0x1d99bdbe, 0xb1f955f3, 0xb0738e46, 0x69469036, 0x9ce2f8aa, 0x2f8a2e9d,
2836 0x507c8d3e, 0x79fe719d, 0x8da6ae1c, 0x078beb9f, 0x678c8a47, 0x17c4e790,
2837 0x115ade29, 0xcf857ffd, 0xc925379e, 0x3011ebfb, 0x1dd0aefe, 0x93da29f2,
2838 0xe31d7e4a, 0x2f8a762e, 0xb0ee8907, 0xc23e309e, 0x742a1b7f, 0x61e2b1e5,
2839 0xafb64cbb, 0xf23487a7, 0xb17db589, 0x4bd031f7, 0x48b7f835, 0x29976af2,
2840 0x54d81eca, 0xc78d2671, 0x439d19cd, 0xe39e447e, 0xffee35c5, 0xe1f28e18,
2841 0x947efcb7, 0x80294671, 0xfdc0aae7, 0xe4d33975, 0xda9d90f1, 0xfc1d9084,
2842 0xd1cf9add, 0xf37f0173, 0x2f951d73, 0x3cb7b3fe, 0x56d9ed13, 0x032c1b9d,
2843 0x5c93ebcc, 0x41650f70, 0x9373d013, 0x2a9b9f85, 0x9079b769, 0x1305bbfe,
2844 0x13e99b9d, 0x19ea2f8f, 0xd7da0bb2, 0x411f01b6, 0xb184bbb5, 0xef57844e,
2845 0x0ad0f3a6, 0xd89ec77e, 0x63df4794, 0x37dc1be9, 0xcbc55b8a, 0xb6af16df,
2846 0x894adc50, 0xf4f71593, 0xb5649d10, 0x61f8ea65, 0x5e8f3e29, 0xd792af5e,
2847 0xbef1926d, 0x226be8fb, 0xb2c2b1ea, 0xef68b586, 0xef7d1867, 0x2e4ddd23,
2848 0x1339db56, 0x3b76da84, 0x4634d7d2, 0x1fc2827e, 0x20ec5dc9, 0x4f12a986,
2849 0xcfd07976, 0x73c17c9a, 0x04a9fd10, 0x77f8132f, 0x24f3e192, 0x58ff70e7,
2850 0x07b8478a, 0x13fc29c6, 0xe328bc23, 0x2a5a3eec, 0xd2919da0, 0x46b82659,
2851 0x2defa5f7, 0xe04e77e8, 0x5f701ee7, 0xe8687f15, 0x6196462f, 0x2fe9487c,
2852 0xbd5cb99a, 0x429be7cd, 0xafa34fa1, 0x349de717, 0xa98ed83b, 0x81558997,
2853 0x84f10c76, 0xd184b3d7, 0x02ba8378, 0x27818eb4, 0x9658257d, 0xf7048948,
2854 0x3a210be4, 0x96a0312f, 0x5b9231d1, 0xfb25df3a, 0x4eda96e1, 0xf771f701,
2855 0xef0443d1, 0x5e0ecee0, 0x9af57cca, 0xb814ffac, 0xa27f644a, 0xd5c38e44,
2856 0x8e9f9e5f, 0xecd181fe, 0xa338c12b, 0x12fa8eb2, 0xbf9e3a5f, 0x3ce782dc,
2857 0xe73fc426, 0x14966691, 0x8cc1373f, 0xaeecee7e, 0x5a7b4823, 0xf8ed39bf,
2858 0xb48fda19, 0xdd1ddcd5, 0x80a57c72, 0xc1e5b5f4, 0x22b37ed8, 0x71c8b62f,
2859 0x14f3a8c4, 0x7ad1cd83, 0x9ac932b9, 0xc28f2515, 0x9e722672, 0x9e7cb762,
2860 0x6f7aa6c2, 0xa46613cc, 0x27834ea7, 0xdf2b9f07, 0xdf2abce1, 0x71f8a01b,
2861 0x961ebe0a, 0x9e68d3f7, 0x1086e749, 0xe3a04e4f, 0xbfb1cd57, 0xd6685987,
2862 0xd3977ac9, 0xf4e4eb0b, 0xb688eb82, 0xb999a633, 0xe3cdbd5e, 0x74e7a29b,
2863 0x9c788452, 0x476c1454, 0x1e589dba, 0xbffa4768, 0x5274c985, 0x4b44e9ce,
2864 0x939bf7ef, 0xa1e93a64, 0xe0260a7b, 0xe43145f7, 0xdb998563, 0xa59d2977,
2865 0x0fc03f44, 0x857ce177, 0x03456a83, 0x339cd0a5, 0xf0f8ef50, 0x9e7822f2,
2866 0x4769e45f, 0xbc7a737a, 0xa8db8e22, 0xc9ba7277, 0xb8c49ef4, 0xe4aa7d77,
2867 0x38d02b5e, 0xe0c736df, 0xa7e416ab, 0x4a7e11d1, 0x5a47e391, 0xc3229cba,
2868 0x1cf193e5, 0x43df1e7f, 0xa74a4f38, 0x33f783ce, 0x4c25b9e0, 0x055c4e46,
2869 0x96f912fa, 0xd2f9d275, 0x09672aa4, 0xe5a0ddf2, 0xf9f7016e, 0x016fbd25,
2870 0x3c76b3ee, 0x350c9f45, 0xbffe8879, 0x6268deb2, 0xf2ff8d26, 0xb5db99b0,
2871 0x7e512b1b, 0x8499f2bf, 0xf0a5d5f2, 0xd6f1d1e5, 0xf3745179, 0xf83a5f74,
2872 0xa07458a7, 0x3a5a7f95, 0xb50bc888, 0xadbc03fc, 0xedc3fbe5, 0x55ce94dc,
2873 0x6a1b9722, 0x7f6f1779, 0x0d0dc8fa, 0x3de98f1e, 0x097ae0cf, 0xf39105e9,
2874 0x74f4f1db, 0xae1ff9a3, 0x31cd1ba7, 0xd4ceb4f4, 0x9f3c1bf3, 0x744da2bb,
2875 0x5f225c61, 0xf6ba8f3e, 0x4f3a24f1, 0xe09362f0, 0xd1439746, 0x502244d3,
2876 0x6127b2bf, 0x4a15bb2c, 0x6ae78078, 0xb2250302, 0x08c759cf, 0x24d633ca,
2877 0x1bac70ca, 0xdbb7fa41, 0x51e600a9, 0x256063eb, 0x91d3fa01, 0x684b181d,
2878 0xf310783a, 0x988b6b2c, 0xb77000cf, 0x80f3f1b7, 0x485bd62f, 0x7e3eef9f,
2879 0x400f37f5, 0x1d71e73d, 0x0e047f1d, 0x4ab673a6, 0x03b145de, 0xe8590e3a,
2880 0xb32f703c, 0x7754d1b8, 0xf8790d8b, 0x21fbec02, 0xe8d983c4, 0xe2281fcb,
2881 0x77aec439, 0xf1eca38a, 0xccbfd6de, 0xe48ae439, 0x7d0e9a97, 0xdf6d185e,
2882 0x14a9f929, 0x3996f7d1, 0x963fdfca, 0x77cb9677, 0x055fb9cd, 0x9c5e309e,
2883 0x5da27f1c, 0x2375f04f, 0x48bf687c, 0x10fb861e, 0xe3d648f8, 0xfb94de32,
2884 0x0adbba0f, 0xbe80fa4e, 0x98393c5e, 0x7b5be1c7, 0xef7768cd, 0x214ef932,
2885 0xf4b7899d, 0xf6a9f9d0, 0xe811deb6, 0xf9fc834f, 0x1ef79f08, 0x9d149b3f,
2886 0xeb12feff, 0x3f5a24fb, 0x729f5bc4, 0x1f4b5e3e, 0xda167dda, 0x184dfe0e,
2887 0x50c07c4b, 0xb086054e, 0xf567fa20, 0x17adc663, 0x31672371, 0x341dc517,
2888 0x999fb479, 0x8e65ffbc, 0x4c679fe2, 0xde21bfde, 0x4efc1e71, 0x05f9d603,
2889 0x989ec7d6, 0xdb478f9f, 0xf53ac2be, 0x18fb9896, 0x215afda2, 0xe60567af,
2890 0x537cf0fd, 0x3852e18b, 0xef231ddf, 0x8091fb07, 0xdd4a05e3, 0x9fb87d27,
2891 0x6bdcd81f, 0x4efa1f11, 0x0091da27, 0xb3b6227f, 0x97ba4aa2, 0x50f060c7,
2892 0x3ad5f47e, 0x5bbd7e7e, 0x1e31b8b0, 0x6491dcd6, 0x33f87941, 0xfb1d2f93,
2893 0x9d5dd48f, 0x09fa7183, 0x3cdd5e9d, 0x41be53d2, 0xe753b216, 0x8e09eaf7,
2894 0xdfda315a, 0xcfeb12fe, 0xe7dcc4b1, 0xc790fb3e, 0xa1f7c5d7, 0xf462e7df,
2895 0x3e9c7bfc, 0x45d651f9, 0xfb83f6f1, 0x3cc5c93e, 0x4f81f552, 0x7ead3fc8,
2896 0x5b9b48c3, 0x0488c6f6, 0x252be3a4, 0x4b89edb1, 0x1eb75afe, 0x967199ec,
2897 0xcb9b922c, 0x23dd2759, 0x61e9a2b0, 0x5e4a3eb7, 0x71d3f62a, 0x8e056743,
2898 0x6440bc7f, 0xbd774075, 0x580389ee, 0x94ac390c, 0x097b45bf, 0xfd1f7f60,
2899 0x9f9bd4d2, 0x9de6d283, 0x338fb4fb, 0x42a11c53, 0xb3cc8763, 0x88f73d70,
2900 0x8fbc325c, 0xbcbce005, 0xe0e74ed7, 0xcf7f8f2e, 0x5c4b1f81, 0x7e5df96e,
2901 0xb0ffcf00, 0xbf3047ce, 0x8d8bf816, 0x718aa8fc, 0xd9d7e5ef, 0x3b76fc23,
2902 0xdbb0418f, 0x70e13f5f, 0xe68aff41, 0x144094f6, 0xa1e7b4fe, 0xc7d7911e,
2903 0x6e745df4, 0x98bfed84, 0x563ef786, 0x829c3bec, 0xec37fdeb, 0xaedfc318,
2904 0xf44d5d58, 0x9f22d533, 0x1960caa3, 0x8bfa0f28, 0x0573ed07, 0x5dc7c70f,
2905 0xf77a821c, 0xd23b1c4a, 0x75ebf72f, 0xf6801a4f, 0xca14854d, 0x55bf1589,
2906 0xbc2d2bfc, 0x3b373b37, 0x58f7e243, 0xb6af9f6a, 0xebdf3d70, 0xf000b336,
2907 0x068d23e9, 0xc4eeaefa, 0xcacc3fb5, 0x64f8fd87, 0x06b9c1ab, 0x85eaadf8,
2908 0x309bc1f6, 0x48ce395e, 0x5c4f97f1, 0xcba41ca1, 0xf3f02fc5, 0x7d6c9fb8,
2909 0xc8f30d24, 0xb5f409ff, 0xdc58e01c, 0x55e7a068, 0xe7a7df8d, 0x5bba6517,
2910 0xe52a42fc, 0x3c744f97, 0xaceb869d, 0xdf93fbfa, 0x966ffe41, 0x41c6a39c,
2911 0xa0977cb9, 0x74b7773a, 0x575559bb, 0xbacad2f2, 0x8f391099, 0x7e7802e7,
2912 0xe79af969, 0x89f57780, 0xc2d2fe5b, 0xdd6f8bed, 0x2eaeeb07, 0xaefb25e8,
2913 0x8c8588fd, 0x44db5fa8, 0x71a1dfd2, 0xadd6f5ff, 0x77f29f50, 0xd31f9bbd,
2914 0xb239274d, 0xece5c4c8, 0x70fa7d94, 0xff719cbe, 0x615776dd, 0x08797cfc,
2915 0xdbd200e4, 0xe18a9f94, 0x79f479bc, 0x5cde6d54, 0xf36b8fc9, 0x029c78e6,
2916 0xf2cdf1e5, 0x1c3f0ae6, 0x49cf84b3, 0x1fb7dd12, 0x45f279e1, 0x2f6e45c7,
2917 0xfc4e44dd, 0xe3d6e116, 0x107b1efe, 0x6427dde3, 0xf6b89c6c, 0xafbc3ac9,
2918 0x012293e1, 0x93ec2033, 0x58f2c66b, 0x2287707c, 0x659cf02f, 0xef5f645e,
2919 0xd7092f71, 0x5dbe0d91, 0x1ceab0f4, 0xd5e5ff68, 0x49f0f98d, 0x419eff0b,
2920 0xfcb4cf2b, 0x67928ff2, 0x0f0ee315, 0x7ca9d809, 0xcd4bcb19, 0xe568ae5c,
2921 0x14a7581b, 0xe4e55a87, 0xa5c0a2f4, 0x5fc57785, 0x3f3058b3, 0xf5177e1a,
2922 0x94efa15b, 0xf8acbe50, 0x260b2e6b, 0x50fea37f, 0x3f8635b2, 0xf095fa04,
2923 0x07d42815, 0xfd408fd1, 0xdb46fd8f, 0x0025c95c, 0x96673ad2, 0x2772e515,
2924 0x416b7fe8, 0x6a313e24, 0xe50e8357, 0x376fd845, 0xc577fda8, 0x72b2c95f,
2925 0x795a31ba, 0xddfc98fd, 0x5df3bc4f, 0x3c4af8ca, 0xf184bea4, 0xb91273ef,
2926 0x839ca6fd, 0x3967eb5c, 0x933e3df8, 0xd26bc3bf, 0xc8f0eff1, 0xfcf5c4a7,
2927 0x83fdc8d8, 0x5c5574bc, 0x29bf09f0, 0x792def07, 0xf7a4efd2, 0x53a7f29f,
2928 0x8bbf23f9, 0x79fc67ca, 0x135efc39, 0xc7c8fe46, 0xd18d2c87, 0xe49b04e7,
2929 0xb093cdbc, 0xd062d7de, 0xe55623e1, 0xf497a03c, 0xd8d2c2db, 0x567bfdf2,
2930 0xe4a5e13d, 0xa087fbf9, 0xc1f1f1dd, 0x097dd1ef, 0x83e26b1f, 0x6e6f250b,
2931 0x13f37d2c, 0xc9379f99, 0x32c7e5fa, 0xfd900d7f, 0x9e729047, 0x4f78d1e6,
2932 0xff773f30, 0xc31dfcac, 0xa9abfd4f, 0xf3cad3bc, 0x8ff76923, 0xf0073b7f,
2933 0x3f036e75, 0xa4ce749f, 0x6cf3bf23, 0x85bcadad, 0xfd8ef0e0, 0xde76511f,
2934 0xf1dc329d, 0xfd6355d6, 0x057e726a, 0xdea072eb, 0x876fd30a, 0x5c3e1e3a,
2935 0xfa432df4, 0x695d66eb, 0xe846afd8, 0x2315ddcc, 0x79209b8f, 0xff84ac6b,
2936 0x5f28219e, 0xed02fd95, 0xfefa2a31, 0xe72b228c, 0x7ce38fcb, 0xa65ab6ff,
2937 0xcf25dbdb, 0xfa9e3e6a, 0x195fc37e, 0xf2b43f3d, 0xb4ffe678, 0x8c02f9ca,
2938 0xce4894df, 0xdb9d7c70, 0xd635dedb, 0x78997118, 0x8e16bf7e, 0x9e9c6c5b,
2939 0xa500f1b4, 0xcf01e254, 0x65044da0, 0x7049d5a6, 0x1803e36b, 0x07158d27,
2940 0x8f2b4ff8, 0x3c7ba61f, 0x9f15d5a2, 0xcef8272f, 0x6c9b7dd0, 0x7bf3a336,
2941 0x0e9b8a03, 0x60643c62, 0xd90eb059, 0xcb513ea5, 0xc63301a7, 0xba7cb249,
2942 0xa4dbcc34, 0xa33f0275, 0x6a9781bd, 0xd69d22a5, 0x4f5d21d6, 0xf168e9f0,
2943 0x412c3a13, 0x54e67141, 0x660266e7, 0x0bfeef39, 0xda82f3c2, 0x1db718b5,
2944 0x797fbcb4, 0x9f7936f7, 0x84d9bc95, 0xc3c206ed, 0xa63fed84, 0xed84d6fc,
2945 0x2885eb77, 0x35693efe, 0x878bff50, 0xff250e97, 0xaa39ce38, 0x26dc794e,
2946 0xfc417bc4, 0xadc710f3, 0x8879f8df, 0xb8a8d6e3, 0xab8af54a, 0x5a77c724,
2947 0x39f8feb9, 0x9f0169e6, 0xe4a05f3f, 0xfe291b69, 0x9a6a5bb6, 0x40887986,
2948 0x43ce8eb5, 0x0bdcf386, 0xf08f79f8, 0x86ef98fb, 0xe2af3fe7, 0xc181eef9,
2949 0xf6df2967, 0x03e79999, 0x6461db3f, 0xf25d2798, 0xefe51376, 0xb1d72cb6,
2950 0xc364f758, 0x9cf9064c, 0xefcf018e, 0x7ca3fee0, 0x081df653, 0x08fdc24b,
2951 0xf9b5c3e7, 0x8bae193f, 0xe9723e72, 0x4869e6ce, 0x93cb1927, 0x563fbc04,
2952 0xeaebeb81, 0xbf506f91, 0xe5f7975e, 0x6f55fa66, 0xb55fa18b, 0xe0d3b57a,
2953 0x6f52da31, 0x641b5fae, 0x2ab5eafa, 0x78e406e7, 0x6247e637, 0xd633cbec,
2954 0x34ce713e, 0x738857db, 0x3149adfa, 0xf7ca9ce3, 0x6c490d9e, 0xfc18ccee,
2955 0x37cc98f0, 0x743dcdba, 0x4da5230e, 0x4a972988, 0x17c94924, 0xc545b08d,
2956 0x35f2b5c7, 0xd8dd7e06, 0xd0aec47f, 0x3e35ec21, 0x668ac731, 0x9c73e000,
2957 0xf2719f0a, 0x9533bf0c, 0xe4a27d90, 0xd49a2e15, 0x6c77dbf6, 0x6dcf3f4a,
2958 0xc4b78fb8, 0x6c53db91, 0x297f0282, 0xc5594bf6, 0x2572f154, 0x1b529e4e,
2959 0xaffbf010, 0x3f230f14, 0xafb26862, 0x7afd00ce, 0x36f73126, 0xe83c27a8,
2960 0x9779412c, 0x883ee554, 0xcbfadda1, 0x0fcaf7f2, 0x395efa33, 0x65f5ef9c,
2961 0x7883bd91, 0x4f0efe8f, 0xfaca0fd1, 0x6bdd6f40, 0xb2cd70e3, 0x7d6f40dd,
2962 0xcf317c83, 0x58be3fd6, 0xf769708c, 0x81ef1b2d, 0x7fd98d4a, 0xb0feac45,
2963 0xd9fdd5cf, 0xbc720de7, 0xa4f9bfbf, 0xf5f0bd46, 0xf17de5e2, 0xbc2c44f2,
2964 0xe5d0a86c, 0x009479e1, 0xe963b8b3, 0x7fb62d9d, 0x8b7edc78, 0x9edc462d,
2965 0xfebf24dd, 0x49773fe2, 0xe2560f18, 0x507b61cf, 0x9e575793, 0xf909b757,
2966 0xb49597e8, 0xb7fb235f, 0x64e7e0fb, 0x8fcdf6ff, 0x025779f3, 0xdc7f2279,
2967 0xbf6f9f25, 0xf7fb95ba, 0xa4fd7322, 0x39a8e018, 0x6841606a, 0x606f8abf,
2968 0x882116fb, 0x3d5f0bf7, 0x8bea853a, 0x192c09f7, 0xe9e02409, 0x160cefc4,
2969 0x425e3e30, 0x8f754e91, 0x7d47a275, 0x7972784f, 0xea9eaa92, 0x3e13df55,
2970 0xaa967660, 0xa46fa07d, 0xd5507daa, 0x96fd5578, 0xe13df55a, 0x457f4143,
2971 0xd30333d7, 0xd7b3fd55, 0x0faaabdf, 0x13df506b, 0xcbadf8ae, 0xdf0cf5e4,
2972 0x2f7d4f32, 0x61084877, 0xbca163be, 0x38e40bdd, 0x52e088c5, 0xc4cb38d5,
2973 0xbbf0470d, 0x57de9b8a, 0x7448dad4, 0x68afbdaa, 0x7d754ed9, 0x46fb89ec,
2974 0x5e0cf3f1, 0xc675373a, 0xdc5f8ea6, 0xc3035f74, 0x1abed6bf, 0x6afbd5d3,
2975 0x886e5976, 0x7a9e6b37, 0x6f7c999f, 0x766f168c, 0xbfff7ab7, 0xed19bc69,
2976 0x0c193c6a, 0xe31d8b3e, 0x44abad80, 0x5cb2defa, 0x4bee4e7d, 0xed93ddc4,
2977 0xcaeee231, 0xcf376abd, 0x0dffb4a7, 0xd04664f3, 0x173c0634, 0x8536e455,
2978 0x48e627f3, 0xaf2b5d9c, 0x75e41294, 0x2af29d8e, 0x5ad3bc91, 0xff21df86,
2979 0x2b708bde, 0xf7588979, 0x05ce6880, 0xbe71c68e, 0x4d0afdea, 0xd240e7f8,
2980 0xae76f983, 0x51ec0b07, 0x8739507a, 0x78c1e8a2, 0x897928e3, 0x4870a578,
2981 0x0f44b8a4, 0xc86257e6, 0xbfdb6ff1, 0x7be93ea6, 0xf6dbf38e, 0xe0bf2882,
2982 0x5047bdfb, 0xefde039e, 0xedd9f5c5, 0x888527a0, 0xd589fc9e, 0xf3d3fc41,
2983 0x3c38311b, 0x48be7233, 0xe1689fc9, 0x0f7cd62d, 0x87b9a6d9, 0xb73c7eb4,
2984 0xb9dae63b, 0xdf2c3d5e, 0xd7235143, 0x7a76346b, 0x8fee7acd, 0x6d15bde2,
2985 0x8d5ff651, 0xe7fd4edd, 0x106a4be8, 0xf70b46ee, 0x8105eaab, 0xa67d78f4,
2986 0x6e3ef340, 0x71f6a52a, 0x5c6a92f6, 0xacb930f7, 0x2a5e58c1, 0xed443bdd,
2987 0x5efb1892, 0x6e765582, 0x7896cf2f, 0xddfd2fff, 0x0ee60ad4, 0x9bbe44a5,
2988 0xd3be7162, 0x3d83c6d7, 0x140ece79, 0x3bf55f8b, 0x9a1fc42a, 0x3f1d0ade,
2989 0x43e70f63, 0xfaf9fbe8, 0x66e7aecc, 0x109ebee0, 0xdb1e78dd, 0x1d602a75,
2990 0x57c7829b, 0xa02256f1, 0x8d6cad93, 0x038bea19, 0x18f78a2e, 0x8fb25fc0,
2991 0xcbddf08f, 0xc7c24cf6, 0xd3219398, 0x789f6858, 0xe3107bca, 0x58b3b9c3,
2992 0x06ed8a12, 0x7f0530d6, 0x55b0291f, 0x5ab31bce, 0x19abfdfa, 0xe8a52b25,
2993 0x5ba94073, 0xe2f3a61f, 0xf87579ca, 0x28fc4167, 0x9e47dff7, 0x4338f3f3,
2994 0xe32f654d, 0x98e5297e, 0xc578ec60, 0xccbbf96c, 0x5ddef587, 0x5a63dfb8,
2995 0xbddee8ba, 0x5b1c8ac5, 0x9defa3a0, 0xe1f793ef, 0x0f3cadbe, 0xbf5daecc,
2996 0xce46162e, 0x0cf8c1fd, 0x2cf173f9, 0xb3bbdd3b, 0xbe932db8, 0x815e668b,
2997 0x6d351be2, 0xbf497b6f, 0x44e0984c, 0x01f3d37f, 0x4b7ef013, 0x039701c4,
2998 0x952efbea, 0x95efd37b, 0xa77ca7d7, 0x8372f20a, 0x78bbf015, 0x81a1dd6b,
2999 0x2f7bde30, 0xa18fba31, 0xf240acf0, 0x37168981, 0xcb85edda, 0x05cfba04,
3000 0xbdd1f40f, 0x6d862314, 0x7e3b8e8b, 0xb78bcb2a, 0xe5a078fe, 0x9c297404,
3001 0x2a48f952, 0xfda768ec, 0x5dfc54c2, 0x95fdc2a8, 0xa338648f, 0x7b2a9bea,
3002 0xde11bb07, 0x80cb530b, 0xe760fe4e, 0x85d74cf0, 0xd9bbfcf4, 0x543fca4e,
3003 0xd20f24d8, 0x9d2d8569, 0x80ae37ee, 0xf400bdad, 0xdfa3fd35, 0x9f2e51eb,
3004 0x05f7cbb2, 0x5c5cb2e4, 0x77c3b267, 0x2accf89e, 0xaf10339f, 0x0fb68d8d,
3005 0xe539f4a3, 0xacdbba47, 0xf9586994, 0x3fe53666, 0xfbb4f795, 0xdf9f9cfa,
3006 0xf0ec9873, 0x57fdc79c, 0xfade81fa, 0x93ddeb1c, 0x1db97f3f, 0xfc52bdc6,
3007 0x17082197, 0x677e8fe0, 0x4ebfb941, 0x296dc719, 0x3f2762b9, 0x3f717986,
3008 0xf9e3936e, 0xbb6d9d93, 0xebb7dd71, 0x0e516b42, 0xa9fef9be, 0x28671c64,
3009 0x3eb8e078, 0xf5d573f8, 0x4570bee4, 0xbf7abee4, 0xf9f0a70b, 0xef2bbf0b,
3010 0x8bc79b9b, 0x500df7bb, 0x0eed8bc5, 0xbfb86fbe, 0xc0937fd4, 0xcfd9f1ef,
3011 0x937c564b, 0x9055fef7, 0x05824f7f, 0xe577e844, 0xc00fde4d, 0x66a87f21,
3012 0x13a270ff, 0xb3cb839f, 0x51e7acc9, 0xb6e4e75c, 0x87efa77f, 0xf2792b27,
3013 0xb93cea0b, 0xe2a59f0f, 0xf43d23b5, 0xb5f7701d, 0x63796fde, 0x43a95bf0,
3014 0xfbf0fbc9, 0x837ec3f0, 0xf87e1f7c, 0xec5342bc, 0x7197f0fb, 0x89f120ca,
3015 0xc52f0fdf, 0xe12fe03a, 0xe907f9ef, 0xc166c1fc, 0xb04c798d, 0xcfef5483,
3016 0x87ded3c8, 0xf17fefcf, 0xe3df93c9, 0xc91f33ee, 0x1e194adf, 0x5dff1b5f,
3017 0xcf3c0e82, 0xdeea7803, 0x51377fc0, 0x777fcf7b, 0x05b7e739, 0x4ba085eb,
3018 0x553bfba0, 0xd6650bed, 0x6776085e, 0x3cec9328, 0x3dc477cd, 0x5c5f6c5e,
3019 0x041befcc, 0xded34fbb, 0x754fe0a0, 0xf961ec4f, 0xfe1671f7, 0xf237d658,
3020 0x64f32fbd, 0x590f31f8, 0xaf591692, 0xf9147fa2, 0xe16050b9, 0x1abee9f7,
3021 0xed463ef9, 0xbb95e7fa, 0x36f3cf09, 0x761c6e08, 0xd067aff1, 0x078053f7,
3022 0x2f995e95, 0x837e73af, 0x6ff3e740, 0xb2a98f76, 0xeeb845ee, 0xaef6becc,
3023 0x50587ef6, 0x5f842e6f, 0xc6b1f990, 0x49afe1c8, 0x885f7466, 0xba25ec90,
3024 0x125dc780, 0xf83b0f94, 0x0de10b39, 0xe627c923, 0xf2937b05, 0xe44e6574,
3025 0x85058143, 0xcffaa3eb, 0x30fbe1af, 0xf842e7c2, 0x12c98efb, 0xc74cdbf9,
3026 0xca3b6dfd, 0xd223d01d, 0x4e10dac9, 0xf2b126b7, 0x67bc0731, 0x20f06aea,
3027 0x342e58cb, 0x2cdcb085, 0x3e7bbbc7, 0xaffc1134, 0x846cbe0b, 0x2a18a27f,
3028 0xe79af927, 0xee93341b, 0xcaf9e3af, 0x167f328d, 0xaefa06b1, 0xa26b3260,
3029 0x527598b2, 0xa1eb0779, 0xac5f83d2, 0xe03da364, 0x798cb2a6, 0x6aca9ca9,
3030 0x0d672ca9, 0x712b7e54, 0xc002625e, 0x51359d35, 0x39e402bd, 0x32890bdd,
3031 0xf74de319, 0xeecec89a, 0xac1cd37e, 0x0e6af800, 0x38bcb918, 0x577d2560,
3032 0x08466073, 0x1fddf9e3, 0x7bf85cd9, 0xa7b176a0, 0xbf48e29a, 0xf7f93ab6,
3033 0xbdd52e34, 0x2bb935dc, 0x78e3f77b, 0x7c7f421f, 0xbaad9e90, 0xafe27ba7,
3034 0x7a8f907f, 0xe1ade260, 0xe81cf27b, 0xcb6d5fcf, 0xcafe3f26, 0x9446dd40,
3035 0x5219d5d3, 0x7ab7e23d, 0x95ee8598, 0x05d3cee9, 0x415b2824, 0xe9fde3fe,
3036 0x05efe06f, 0xff26d940, 0xf901c05e, 0xde10f57e, 0xdab60eaf, 0x951e7f21,
3037 0x95377e1d, 0x5445fc47, 0xa87bf51e, 0x397f31df, 0x5efdc795, 0x9d1eaf2a,
3038 0x77c7df4f, 0x839e9fa7, 0xc87427bf, 0x19a4f951, 0xb28fe1f4, 0x44fc2e7c,
3039 0xfdf4eb08, 0x45aec0c8, 0xd508fdf8, 0xd7d67f41, 0xd19dd2f9, 0x555352ed,
3040 0x92ea1db8, 0x7008fdfc, 0x629e93d2, 0xea4527a8, 0x118dfdf8, 0xbc199ce3,
3041 0x57f3065e, 0xfb5220bf, 0x303f7811, 0xc72bd618, 0x2e094ca3, 0x03461f2e,
3042 0x74e18cbd, 0x7c65df83, 0xea99d5d8, 0x69762310, 0x4e5c13e5, 0xedc0be54,
3043 0xec67cace, 0x9eeef7f2, 0xef0d2132, 0x89cb511d, 0xf94c45f9, 0xbded13fd,
3044 0xea2c45a5, 0x83b9983e, 0xe60f2475, 0xd3f756ae, 0x4ce807ca, 0x95aad3bf,
3045 0x643a1f0b, 0x8d9733fb, 0x97faefc1, 0x1d93b1cf, 0xa76ec976, 0x763f7a73,
3046 0x0164a475, 0x44fbd5bc, 0x0ab413ca, 0xb5b07640, 0xeab8de7f, 0xced0136e,
3047 0xd7a7159d, 0xbeb1b8a6, 0xaefc49fa, 0x4ff352e2, 0x233aa4a7, 0xf4ec59f5,
3048 0xdda007c6, 0xddf56eb9, 0x2ffac0f7, 0xb8c0bd23, 0xfc0d5b97, 0x12939b1e,
3049 0xded32efd, 0x0b21af4c, 0x763f7bea, 0xa6ff3c33, 0x99bbf5e0, 0xbddbfbfc,
3050 0x2b41be99, 0xa7deab47, 0x1afd61df, 0x6bf133ef, 0x00dc2fbe, 0x8a7bed7e,
3051 0x7efbdb5c, 0xa77f0dee, 0x6dead976, 0xcea27243, 0x37d32c15, 0x658279d1,
3052 0x921e5fab, 0xa5cdf603, 0xe88d96e2, 0x7835ef77, 0xf942ef12, 0x71e06cd5,
3053 0xec904366, 0x89af4f80, 0x02466f34, 0x0609fbd7, 0x7c249f6e, 0x3d446a68,
3054 0x1382f603, 0x6bdcafbf, 0xa439f0e6, 0xc112572e, 0xc2c3ebc9, 0x86f1f1ef,
3055 0xf7b97025, 0xb25eb5e9, 0xd76e7ba7, 0x8082efd3, 0xc4faa07c, 0x6884523b,
3056 0x226f67bb, 0x8af3de7f, 0xcc52fd48, 0xf1e8c49e, 0x2f1debb5, 0xdcd7b7cf,
3057 0xc53f1aa3, 0xd653dfc0, 0xe36f9da3, 0x9de51324, 0x496e289e, 0xb2ebfcc3,
3058 0x207bfe12, 0x8abc3245, 0xa3f1357d, 0xe1a3dba9, 0xeeff289b, 0x26e4ceb0,
3059 0x557079fa, 0x7dfa38e2, 0xe297a742, 0xe71e73fb, 0x38f269f5, 0xe08e4520,
3060 0xdcb9e772, 0xf20cd153, 0x28657c39, 0x79e417b7, 0x8afd608f, 0xf510a7a1,
3061 0x24aab886, 0x33de0030, 0x9f495e3c, 0xd5d719f7, 0x6f34b005, 0xe1036468,
3062 0xcdcdc2f9, 0xa13df70c, 0x8a176cf9, 0xefe69499, 0xaf6d7c53, 0xd813a641,
3063 0xfe51998f, 0xa96736d7, 0xd7e60137, 0x391db939, 0x4245ac7d, 0x467a607b,
3064 0xf5f9d906, 0xcc1cc1a5, 0x308cf70f, 0x3a627c53, 0x9f80258c, 0xc5886c72,
3065 0xd412fe83, 0xcf58893d, 0xa7fd4c98, 0x86591d8f, 0xc658f87a, 0xb78c74f7,
3066 0x9e2bc7af, 0x5fc0658e, 0xc21fda0e, 0x8969cf57, 0x963eafbe, 0xf92a74b1,
3067 0xbd382315, 0x6c78cb1f, 0xd22bf62a, 0xc2cbee05, 0xf289a176, 0x70278fae,
3068 0x0c5d3f3d, 0x09efc71d, 0xcef819ef, 0x566ff471, 0xc77ec826, 0x622b9018,
3069 0x5c981fc4, 0x9f8edcd4, 0xde7b15cb, 0xeaea829e, 0xb73ff28e, 0x26f1e963,
3070 0x2f7aa196, 0x03ae3d9d, 0xccdf32cb, 0xe8731032, 0xf88e3caf, 0x70f55a9e,
3071 0x01ffd607, 0x88e3cafe, 0x55c992e7, 0x9f37fbf4, 0xa3e5dfdd, 0x7024e93c,
3072 0x7dc463d4, 0x4b09f622, 0x781af7e2, 0x485f5092, 0xdf7db86b, 0x7b244fb3,
3073 0x39751582, 0xea6e5c74, 0x33aafe90, 0x9e90d2bb, 0x38f207eb, 0x976715cb,
3074 0xfdf2ea83, 0xf322ff02, 0x57624541, 0xc561d21a, 0x9e0261be, 0xe1e2bd3b,
3075 0x56a04a76, 0x3061e7e4, 0xff2694cb, 0xd51678ee, 0x93fceec9, 0xfcf5ebc0,
3076 0xf3d676ee, 0x23ed237d, 0x2f10cf8c, 0xe30f0f3d, 0xeabe0170, 0xb92f5ef1,
3077 0xb983c33f, 0x52abf748, 0x87f21ee9, 0xfc24a72c, 0xe3302469, 0xae3e50d2,
3078 0xe276ca68, 0xef06cdf3, 0x15f71a4c, 0x96e389c1, 0x3c966cef, 0x2a4fd236,
3079 0x90f41e3b, 0x7ba7eed6, 0x3e32e687, 0xd126dcdf, 0x9aba0663, 0x03fcd2db,
3080 0xeecd2e81, 0x8ff7c832, 0x4d6bdea9, 0xfa9f74e0, 0x4fba66cb, 0x87ce1976,
3081 0xee81ab65, 0xab365d95, 0xf1443245, 0x3dd6b2cb, 0x577cafd4, 0xcbc5e533,
3082 0x2f64ecf3, 0xeb0d634f, 0xdf2d5f28, 0x53e3e457, 0xc9add3b0, 0x65003fcf,
3083 0xbe399fc5, 0x3efc53d8, 0x0f83f9b5, 0xbb2f91d9, 0xfc53960a, 0x942143e7,
3084 0xf8bd001a, 0x0ee76650, 0xc92e1ff4, 0x0fd68ef6, 0x0b1dfad1, 0xa2a7335c,
3085 0xdfd7d149, 0x38e8b660, 0xb03f168a, 0xdef11b1d, 0xa24d45a3, 0xd131ef13,
3086 0xfe0a23fa, 0x953f78b4, 0xc7db2290, 0x3f706320, 0x20eca69b, 0xfa71933f,
3087 0xd6017b20, 0x987dc971, 0xd39ab3ee, 0x6279efc4, 0x8a14a13d, 0xb3f06b03,
3088 0x8cda1f41, 0xd60549f7, 0x02fee819, 0x5c02fe1f, 0x8dfdac52, 0xec4a27ba,
3089 0xeb2d3f5b, 0x5bcf3ecb, 0x7a775fb9, 0x1b9f28bd, 0xdbcfb751, 0xb3247f97,
3090 0x26fbe31f, 0xeed27df0, 0xcfd002c7, 0xdf8217e4, 0xafa97287, 0xdfa5e85f,
3091 0xfed9b883, 0xdffff828, 0xc7a90a29, 0x00008000, 0x00088b1f, 0x00000000,
3092 0x7dedff00, 0xc554780b, 0x3d9cf0d9, 0xcd8dcd7b, 0x09c246fd, 0xb8094404,
3093 0x9fb1dc24, 0x4a34021b, 0x414045d0, 0x2dc8d812, 0x088d9242, 0x59b6b696,
3094 0x5a4062e4, 0x7da5aac1, 0x2c142ea8, 0x11a0d05a, 0x86ec5d43, 0xba8b4508,
3095 0x8ad45cb1, 0x14178026, 0xb16d0042, 0xfbdfad1f, 0xbb2733be, 0x6a2364e7,
3096 0xffefefd5, 0x27a3cbff, 0x9cccce73, 0x997ef799, 0x6318c399, 0xb17fc39f,
3097 0x50dff876, 0x261d8ac6, 0xd8c21b27, 0x4fab569c, 0x8a6c61c9, 0xef74676b,
3098 0xa79cc624, 0x18564c0d, 0xedfd2e6b, 0xd543262f, 0x8ad79b24, 0xcb7693f7,
3099 0xcd942f0e, 0x3b58eef1, 0xdaf4b7b4, 0xd5f6c468, 0x512c490f, 0x6724ac62,
3100 0x618b126f, 0x9b0e576c, 0x7783cae5, 0xd0daefe1, 0x950ed135, 0x6cdb1992,
3101 0xfb622577, 0x1b32dee7, 0x1ec60f58, 0x87f5e78c, 0xe3db99bd, 0xfd5098b6,
3102 0x687f5841, 0xd5b23ca8, 0x467f58c0, 0xe8c79c3f, 0xb318a30f, 0xebdfca86,
3103 0xaf94d048, 0xa9a198bd, 0x68fac85f, 0x0759179e, 0xb38f9e68, 0xdfca6817,
3104 0xa9ad1b4f, 0xa4529d7f, 0x3fe84f29, 0xa27f5341, 0xbca6b263, 0xeb8ac8d6,
3105 0x63675e61, 0x8f4b5e8c, 0xd8463cd0, 0xb787040d, 0x478702d3, 0x683b584b,
3106 0x8576c572, 0xa98d5957, 0x7dec35a3, 0x9c38da0f, 0x819c5d58, 0x4eec630d,
3107 0xffa899f5, 0x58df0143, 0x7be0d599, 0xdd46a303, 0xb5bc046f, 0x160d941f,
3108 0x42f32fc0, 0xcec614bb, 0x1a17768b, 0xbe207a0b, 0x7f7e01d8, 0xdfdf8d91,
3109 0xded1f025, 0xc335e0df, 0x816b5bb8, 0xde85fa26, 0x660c56e3, 0xdd7e1843,
3110 0x8259b28d, 0x730370f2, 0x17dd7be3, 0x1059cccd, 0x5163071a, 0xde76bdfc,
3111 0xe64e3abf, 0x8defe68c, 0xaedff7e7, 0xec62e245, 0x5d2b5a9d, 0x82cf0e7f,
3112 0xc0633e38, 0x691fa0cc, 0x34f8cc74, 0x06f6b7a0, 0xfa016ec9, 0x366c6cac,
3113 0xed17f8e3, 0x316549cc, 0x5ea7e15d, 0x31a6d78f, 0x5aabfa05, 0xd52ab2dc,
3114 0x1f6ef401, 0x682bf752, 0xe303555f, 0xb1a91200, 0x965bab0f, 0xbb62d8cb,
3115 0x6716f442, 0x7f43f981, 0xbff4feef, 0xf0073ccf, 0xd4b3fe3b, 0xfd07e47c,
3116 0xffb559f3, 0x17e8f4fc, 0x27f77f3c, 0x83f63f7f, 0xd3ff6a2f, 0x65fbdecf,
3117 0xc6eef3d8, 0x932ebb3f, 0x30746129, 0xace1cccc, 0xe90cb7af, 0x3b3ffa0a,
3118 0x358f1fea, 0xb2497f43, 0xe01d997b, 0x27cd7edc, 0xc51e0cd9, 0xcc34bf0e,
3119 0x37e2131d, 0x095ffb7d, 0xb1bc037e, 0xfb338018, 0x15b7cd81, 0x0ddf06e9,
3120 0x924b63e5, 0x5e906b7d, 0x669ac15d, 0x95b1f718, 0xe06b1c7d, 0x0ec7e53d,
3121 0x86f7338e, 0x2f3cb1f2, 0x24cbfbc3, 0x2cfb8307, 0x3a446acd, 0x5703899d,
3122 0x2b2ef868, 0xd31674e0, 0xf9d02dd2, 0x7c61adfb, 0xb6a96b33, 0x96d5ee5c,
3123 0x61fce387, 0xd899cf1e, 0xbc30fab4, 0xeffcc4fb, 0x047c2f89, 0xce3b8be5,
3124 0x5376e54e, 0xfac85dc7, 0xbfb4f58c, 0x81fa2d1f, 0x32008e39, 0xb7b2f1c5,
3125 0x9fcf34ac, 0xf89183e1, 0xf2266f3f, 0x4f82dbe3, 0xd6c4c4cf, 0x6707c049,
3126 0x6f070e14, 0xd2e1cc8d, 0xed056013, 0x6e2777ab, 0xdfc0b822, 0xb3ee5451,
3127 0xa4c7cb19, 0xde17b240, 0xfb07265b, 0x28cffbe2, 0x1d630fad, 0x4668e2ef,
3128 0x53b491ed, 0x10fa7c04, 0x30f3148c, 0xe7801f01, 0x69d946cc, 0xf1f0441b,
3129 0x29a3e0ea, 0xa8d0fe8f, 0x43af7f29, 0xa2f6be5b, 0xb4c85cb6, 0xdaac8bed,
3130 0x8e02cbf2, 0xfbdaece3, 0x96d34fdf, 0x1e3a55df, 0x1d8bf2e2, 0xf3c30dca,
3131 0x259521cc, 0xcfe00e2c, 0x179c66ec, 0xb864f78c, 0xc11e2b1c, 0x3adb78e1,
3132 0x21cbe7c9, 0x5f9e6afc, 0xecab1cc7, 0xdaf74879, 0x418bf0fb, 0xe82b9a7a,
3133 0xed3aee67, 0x19dfebf3, 0xbc019e35, 0xe325d84e, 0x207f78fb, 0x4e78881b,
3134 0x419f738c, 0xc744f03e, 0xc37d420d, 0x46b9ede4, 0xabd9ff78, 0xe3990e6c,
3135 0x3b21cb81, 0x3938ff1f, 0xe7c011c6, 0x058768fe, 0xd3da2d6e, 0x8fe51527,
3136 0x37cf5eda, 0x52dc800f, 0x9c7be1fa, 0x99af4867, 0x25d20559, 0x28fa021b,
3137 0xe4c2c81d, 0xf6878f8c, 0xceb71dcf, 0x3be04772, 0xef955ce0, 0x77c8259c,
3138 0x35f4e63f, 0x1ec8cda6, 0x352c71c7, 0x9c20b26d, 0x8fc427eb, 0xb999fa03,
3139 0x5b9df38c, 0x3064ac0a, 0x647b99bf, 0x25cce782, 0x44498f92, 0xf435e72f,
3140 0xbea0f022, 0x5e71f00f, 0x329a5fc7, 0xfdd12850, 0xecc62683, 0x678ebef0,
3141 0x1466df25, 0x648d53d9, 0xbb6d542f, 0x337047c2, 0xef1117b2, 0x2a8f816e,
3142 0xa81e2323, 0x0658fe04, 0x4bd4e7f5, 0x178fae34, 0xa8067c5b, 0x261db55f,
3143 0xae3fcf08, 0x2824f931, 0x3328dc7f, 0xbeb10fce, 0x7db550be, 0x7c2f2f3b,
3144 0xf82d96fc, 0xff3c5dbc, 0x2db8fb78, 0xa2b5bef8, 0x9062ef7f, 0x6ddf504b,
3145 0x3e6b5664, 0x0259b75c, 0x63b7a076, 0x4757f651, 0xe8ed3d21, 0x3e0cf0f3,
3146 0xc618c524, 0xab59c74f, 0x85d0e109, 0x9f03b69f, 0x2be575c5, 0xa0f1d237,
3147 0x50b9f4ae, 0x839039aa, 0x9267e372, 0x95d2ab63, 0xa974f54e, 0xc17cedd2,
3148 0xd9b3d01f, 0x1bca1035, 0x1d38f5f4, 0x1fd635ac, 0xb9e715b9, 0x3bfea642,
3149 0xb71009e7, 0xdc2d4902, 0x28c8f7d1, 0xdabe5e78, 0x32efe884, 0x33f3aecf,
3150 0x6ce6fcd1, 0x673274e7, 0xa453e4a9, 0xcfd5f3ae, 0x98bccbb3, 0xa63d956b,
3151 0xcebafceb, 0x218fd383, 0xf1104876, 0xa2d1be75, 0x9dd1fda0, 0xab5d3b7e,
3152 0xff411b64, 0x675adbb6, 0x238c0732, 0x2575bb7e, 0x907688c8, 0x179fa8c1,
3153 0xec5ddfac, 0x2d39be05, 0x4a6f7971, 0xf95874e6, 0x5926ea74, 0x6953f50a,
3154 0x4073f40e, 0x15e3bbbd, 0x81a56382, 0xc1fa09eb, 0x4e0f4e38, 0xc606bcd8,
3155 0x856de601, 0x32679fa6, 0xe361c937, 0x8604b4ab, 0x3b41fa69, 0x7c9fbc26,
3156 0x1c19cfde, 0x9fa85e4f, 0xf1da5daa, 0x9a839954, 0xfb0954f1, 0x0ce7ed48,
3157 0x9fea078e, 0xf784f1c1, 0x3c769cf3, 0x66a09655, 0x769d553c, 0x9f27e895,
3158 0xae55d3f7, 0x73f634f8, 0xb64e7d55, 0x2b4f0c31, 0xfb1631af, 0x0f4dd822,
3159 0xbff973c4, 0x7ecd9b70, 0x557eac32, 0xeca6bc7d, 0x9fb74c69, 0x859fa30c,
3160 0x3bc807f8, 0x032418b6, 0x314ad3c8, 0xfbb291c4, 0xa3d47881, 0x011faf49,
3161 0x5b559a0b, 0xa748cc3b, 0xfcfa5d8c, 0x865861f3, 0xcf1c653f, 0x38450394,
3162 0x1d93469f, 0xf00cfd59, 0x71e017bf, 0xf5f061c6, 0x7fddf986, 0x119b83e9,
3163 0x4dbb313e, 0x7940f709, 0xab45e3ad, 0xdb5fe302, 0xe5f62a68, 0x67dddea1,
3164 0x5f261d9d, 0xfdb93ad7, 0xeb019ccd, 0xfba181e4, 0x8f5f8331, 0x0cf17b43,
3165 0x5e2316b3, 0xd6031ad7, 0x587061c1, 0x3eaa2a0b, 0xc5765c02, 0x5fd744cb,
3166 0xb54b2e1b, 0x01e15170, 0xf085d9f0, 0x535b58f1, 0xffbb4ed0, 0x6871e39a,
3167 0x360d15a7, 0x9ca7a44a, 0x9721e912, 0xabaff39f, 0x0d7f2644, 0x08525626,
3168 0xf441bbf0, 0xfa0ad677, 0xdbf06ae9, 0xd885091c, 0xbc71c6ee, 0xd2f978dd,
3169 0x9e50c9a1, 0xca993dfc, 0x4d99eeaf, 0xe2600d72, 0x27bc0008, 0xbf258d4f,
3170 0x3863fa0e, 0x9fa8a9be, 0xe126d481, 0xa937682d, 0xe005f258, 0x308e377d,
3171 0xf3e70f1d, 0x796d4e49, 0x0cb6b172, 0x335f91fd, 0xafbda5d5, 0xe28759da,
3172 0x07de9363, 0xb1458c17, 0xfed1cf8c, 0x6632fa11, 0x1f6b5ef0, 0x11d9d718,
3173 0xebcd0766, 0xeca9dfd2, 0xb6c0c6bd, 0xa7337b62, 0xb28d9ffb, 0x84e796fa,
3174 0x443dfbd3, 0x030e4db7, 0x37fb6133, 0x9bd43e2c, 0xbb33db7f, 0x77a08b17,
3175 0xd198ed43, 0x35e34690, 0xdcfeb832, 0xfd8c51d4, 0x067bfcff, 0x8ffa0cb6,
3176 0xfb76651b, 0x27bfb422, 0x4231f85e, 0xef072dde, 0x2f2dfd0f, 0x256c728b,
3177 0x3f2148bb, 0x58b7f54d, 0xab2a1f5a, 0x340c967e, 0x34fa4419, 0x9e3d1076,
3178 0x81e9f7f7, 0xe68d8ce3, 0xa07f3c78, 0x2f6e1ed9, 0x047fa234, 0xd01fc676,
3179 0xa36b823f, 0xb5fd7fb0, 0x00bf2a76, 0x035e0e7e, 0x4ff90ab5, 0xd3fb6b7b,
3180 0x075ac5f5, 0x8ed7f75d, 0x5a81eba0, 0xb97bd527, 0x07ae98b6, 0x75745d6b,
3181 0xf9f025c7, 0xec5db918, 0x920afe79, 0xdbafe073, 0x88e28612, 0x3e20066b,
3182 0x793e3bcf, 0x0af0b7f2, 0xafd3a8cf, 0xacf5c116, 0x735771d4, 0x3ff9fc98,
3183 0x3f074fcd, 0x7fc71728, 0xef5d7f39, 0xb73d542f, 0x70179763, 0x87a9e0b4,
3184 0xfbcc18e2, 0x0a5d7194, 0xadcae1ca, 0x709ce32b, 0x0e3bb305, 0x9f29e1f5,
3185 0x3e891c5c, 0xfa54134a, 0x2848c670, 0xabe718e7, 0xefb89e8f, 0xbfabe406,
3186 0x51d9356d, 0x7ec0785f, 0xae7e80b1, 0xf89db86e, 0xbc6dca12, 0x1939ef7c,
3187 0xfe5a8dcb, 0x87bbf059, 0xa2589452, 0xb74e4cbb, 0xdba44c81, 0x8def2dea,
3188 0xb0f23a47, 0xfad3d20e, 0x8bfef876, 0xbd4f7a00, 0xbd7e8e5c, 0xffcab9fe,
3189 0x9eae411e, 0xc9cefb86, 0xab57f871, 0xafaef119, 0x0e34815f, 0x41313c7c,
3190 0x3670f1f0, 0x156ded1c, 0x4c97cc1e, 0xf73f2cfc, 0xa86d419b, 0x39fcb7bf,
3191 0xcaebca4e, 0x67ebe7af, 0xa507fa3f, 0x176cfe7b, 0x6bd7af74, 0x200c234a,
3192 0x7e7e8a15, 0xe20534ad, 0xb9fda346, 0xacf244c9, 0x1f6fc772, 0xd3da35fb,
3193 0x7d1c5a6f, 0xf69bb415, 0xe505191d, 0x494d3b85, 0x311a7c25, 0x2f084a52,
3194 0x696ff81e, 0x0b0f087e, 0x5667d99e, 0x77fbf206, 0xb1f08427, 0x99936770,
3195 0x8f0aec0d, 0x7326faa2, 0xbc044c6b, 0x478db7d4, 0xfb9f96be, 0x7ef119a7,
3196 0xa58905ea, 0xe78044e6, 0x6e717da6, 0xa3c22701, 0xde2753c0, 0x803df574,
3197 0x1553a417, 0x57e7fa4f, 0xc67a7027, 0xa23c94fe, 0x00ff27e7, 0xcb78a9f0,
3198 0x57f9c0e2, 0x1c67793c, 0x6303e3ce, 0xdfeba70d, 0xc2714cac, 0xde4c2b7b,
3199 0xf95d3b14, 0x96478afd, 0x6fcdbd10, 0xc8c29259, 0x1ba670ee, 0xd33cd046,
3200 0x37737e71, 0xcdf9a54e, 0xbba26e63, 0x2ec8df8a, 0x353e2bb4, 0x119de2b2,
3201 0xc175e2f8, 0x066c1f17, 0xfbf3046d, 0xef73c840, 0xcb8fb2eb, 0xca183bcd,
3202 0xdcaa25c9, 0xfca88b64, 0xe9e395a9, 0xe08304f1, 0x70f2e02b, 0x6f72dd7a,
3203 0x51f3f110, 0xfd153396, 0xbf030f47, 0x7d21f797, 0x2dcafd0e, 0x7e3952e3,
3204 0xed4cbdb8, 0xc2290ec0, 0x683f58fb, 0xac3b7f22, 0x273cfb1d, 0xe2c5fef4,
3205 0x28ee30fd, 0x07f3e409, 0xd36edc29, 0x095fefcf, 0xbf028e3c, 0xafa30b20,
3206 0xfce6fe30, 0xe73565be, 0x7ddf956f, 0xf9f18a93, 0xff388727, 0x7cccbb60,
3207 0x9520571a, 0x914d379e, 0x58581e48, 0x6f5f1220, 0xd6be0931, 0x04e9573e,
3208 0x38c46dc6, 0x60bd2746, 0x7f0409ff, 0x3de787b2, 0xe4c2ed08, 0x17df07a1,
3209 0x953fb5d7, 0xfe0be76f, 0x3ff9057f, 0x6cffc43a, 0xeefbe723, 0xf097adf5,
3210 0x3df26957, 0x57e46bf6, 0x82af4fe0, 0xe1726afc, 0xdede3fbc, 0xf456e47c,
3211 0x3e55eb1b, 0x3d4fcad5, 0xbd3c569f, 0xcf53e88f, 0xefd71fa7, 0xa7c8894b,
3212 0xb4a5f73b, 0xd3e245e6, 0xaa7e56ef, 0x2754fbf0, 0xd879553f, 0xf2f51c1d,
3213 0x250481f0, 0xdf843ca2, 0x2bac3621, 0xa774a9fd, 0xdf82dbd2, 0xb942f557,
3214 0x2a9749d3, 0xa5d275dd, 0xf9fa774a, 0x7fa7e16a, 0x158047fe, 0xb90df9e2,
3215 0xf7da1863, 0x45b8c153, 0x03054dbc, 0x6b1f34a3, 0x4d5f11a5, 0xfef3e311,
3216 0xb7184983, 0x79c21241, 0xf4bff54d, 0x0df7be19, 0xdfa2f313, 0x2dcf767b,
3217 0xab57da0a, 0x990ead92, 0xe68f84e4, 0x5eec8efd, 0xb00f7189, 0x8e51aaa3,
3218 0xdb47f74c, 0xddb96ed1, 0x32709eea, 0x7f448411, 0x8dcbe489, 0x07b2656b,
3219 0x2e3c79ad, 0xf2611ae1, 0x9efa5fa1, 0x2be345c1, 0xfd5e1829, 0xf73d1a23,
3220 0xb93dd1cf, 0x2157c606, 0x8c3f87c6, 0xc2ceddd7, 0x0f5faa7e, 0x46bbce5d,
3221 0xa1c5440a, 0xe3b12c3f, 0xddb87061, 0xefe32da7, 0xfd4252bf, 0x777eae5e,
3222 0x5f4df47c, 0x3aba05df, 0x1b787e0e, 0xba7c8d5e, 0xcb3cf4e1, 0xa9e8e1cf,
3223 0x031fc894, 0x615c9bbc, 0x44bad57e, 0xbddef72e, 0xcce280bb, 0xec0ff785,
3224 0x2e6de5c1, 0x423cd7c5, 0x2af79e7e, 0xa8af503d, 0x03f9eef6, 0xe8efe445,
3225 0xe822d3c7, 0xdec22ffc, 0x5a563b3d, 0x9ddf0327, 0x3f641d65, 0xd8dac779,
3226 0x6f7e08d6, 0x7ea7624d, 0xd430f260, 0x86afea4b, 0x4f13b0f8, 0x329e276b,
3227 0x7f0aea0e, 0xe5571dfc, 0xc3effca0, 0xe109f915, 0x1d6b62d9, 0xcf308aef,
3228 0x4adc047b, 0x46667ef6, 0x3f937639, 0xb8f084c7, 0xb1acac69, 0x28947f63,
3229 0x2b0144e4, 0xec9571c0, 0x246e2ebd, 0xec80e3e2, 0x3d5c01b0, 0xf76673fe,
3230 0x11c3cbc0, 0xf5fb47fb, 0x0f31c984, 0x67e278e1, 0x3e05e636, 0x45c44578,
3231 0xf51391e0, 0x44e5741a, 0x225f7dfd, 0x9bbc078f, 0x4eb82768, 0x2534292e,
3232 0x1af37bc3, 0x6f3183ec, 0xbfea2191, 0xf3d0a89b, 0xad4ed14c, 0xebc95197,
3233 0xd5ed99b5, 0x23dfe691, 0x6a5f53b9, 0xdefb35f0, 0x0fe8cd3b, 0xabe16fff,
3234 0xc0d8fef0, 0x8d5f8c18, 0x746e4895, 0xfc4663a5, 0x63fc1e70, 0xfbcf13f4,
3235 0x7cf2bc79, 0x02c38f09, 0x735db93c, 0x8d764493, 0xf87ae74a, 0xabe0273e,
3236 0x28a8ffbe, 0x9db913fb, 0x8557c2a4, 0x6abc7eab, 0xd757907d, 0x1bfbcb86,
3237 0x293f071b, 0x2fc23e61, 0x55d00dd9, 0x8cd5b1b5, 0x5c69e77c, 0x667f426f,
3238 0x65fbc2ba, 0x29a0d746, 0x6ef37461, 0xdbde91a2, 0x267a3f9c, 0xb585c7d2,
3239 0x77f38616, 0x871739ce, 0x8315f37a, 0xc8d1b5e3, 0xe4caaf7f, 0xc707778f,
3240 0xafdad6bf, 0xef0c6b1f, 0x39c68737, 0x84d0b2b9, 0x654669ea, 0x8c352993,
3241 0x4c4dde8e, 0xfdeae7a0, 0xf2854a8c, 0x1a3ef062, 0x16e7f787, 0xd5e49bca,
3242 0xc344c707, 0xf13519f3, 0xc02afe9c, 0x8e72a6f0, 0xbea68f26, 0x5347cf47,
3243 0xe535a24a, 0x3dad45d9, 0x96252e11, 0x044762c0, 0xa926f4fa, 0xf535f9f4,
3244 0x37e81382, 0x5ffedd02, 0xab1617a7, 0x9355a17a, 0xa92ebecf, 0x8d485e8b,
3245 0x2d1617a4, 0x0f115253, 0xd165be6a, 0x2252e34b, 0xb5c385e9, 0x1472df3c,
3246 0xcf5e19e4, 0x70bd014e, 0x985e9875, 0xd13a2362, 0xba482bb7, 0xf1505e8c,
3247 0x99cb1df4, 0x2217a8c3, 0x24f8f5f0, 0xd9b85ead, 0xe17a4e5f, 0x533229e6,
3248 0x497df3c2, 0x56eefec2, 0x4ca6142f, 0x11c9b2a7, 0x106e811d, 0x3a17189e,
3249 0xf8eef22a, 0x3f0fd41e, 0xbc13b24e, 0x3ba27af4, 0x39799e39, 0x04bffe39,
3250 0x2f8e555f, 0xbd912a9a, 0x18ee95d7, 0xe9a2efd1, 0x16ade512, 0x7c72e1ed,
3251 0xf1c81951, 0xae45d61c, 0x0eae50ba, 0xbcab9709, 0xeb9bb57d, 0xce634f01,
3252 0xf9e14b2f, 0x0e4cebad, 0x35bfd42b, 0x85876724, 0x271fd9cb, 0x2b672375,
3253 0xe0bd9cb8, 0x45f1e82f, 0x4263cb71, 0xcafc82be, 0x8ba04475, 0x9ad1a569,
3254 0x06270375, 0x19ef29ff, 0x64578fe4, 0x27bc878a, 0xc1c1fdf4, 0xf6821a7f,
3255 0x0f1c61ff, 0x49b7efe0, 0x9f80ef5c, 0xe058fd71, 0xdc39a2fb, 0x2edaae5e,
3256 0x1baafc13, 0x6f57bf38, 0x3d0e2893, 0x3333ff3e, 0xf0f6ede5, 0x971a86b8,
3257 0xf0bff156, 0x9955d695, 0xc4937cf8, 0xfc0acce3, 0xcd87cb0b, 0xbf242c73,
3258 0xad06fe64, 0xe96250ff, 0x4aed8fd8, 0x3639277e, 0xec8bfc91, 0x7e89556f,
3259 0x3ed36e16, 0x16ac72af, 0xe48057fe, 0xf6bd5576, 0x5fc15ef9, 0xde40e573,
3260 0x7bcf9833, 0xd244764d, 0x4ebd6a67, 0x9bfc5478, 0x780168f0, 0xf0eaf90c,
3261 0x44dfddb8, 0x0baf9379, 0x5ffcfd07, 0x3e46e554, 0xf6fc821b, 0x7249c19e,
3262 0xcf32fbc3, 0xdf59ce3b, 0xfe3c3537, 0x8ba0bafc, 0x55ee0c57, 0x9aaf58e9,
3263 0x6fe73fe7, 0xca1a8704, 0x306cf5a5, 0x37f36efa, 0xa76bf568, 0x48506f3e,
3264 0xecd6975f, 0x43cb6e94, 0x5abcf3b8, 0xf8fd6f85, 0xb65e780c, 0xd437f414,
3265 0x716f9d9f, 0xc5a8fc63, 0x517241d6, 0x05cfcfa5, 0xe053fcbf, 0xc74644e3,
3266 0x8d3bd258, 0x2ef89d92, 0x087ae360, 0x728362f0, 0x8fbfc8f3, 0x5bb07817,
3267 0xde392f88, 0xe427803c, 0x517ef1db, 0xddf6e7ae, 0xee39ff0c, 0x4c9bfbff,
3268 0x91a2aed8, 0xa0236baf, 0x8c3be986, 0x84a61447, 0x1b4f73e1, 0x92adefa7,
3269 0xe0f86e83, 0xe7c197df, 0xdaa8f065, 0x9f165f23, 0x4f3e5c2a, 0xc0827e12,
3270 0x582d8b6b, 0xfc798052, 0x3363923d, 0x53c7f656, 0xbae4e15c, 0xd8df843e,
3271 0x3d578e64, 0x80dfa3dd, 0xf2d4a6eb, 0xfa201c24, 0x7636c5f4, 0x6f6f7d42,
3272 0xcb855f6e, 0xa3be351d, 0xbe6abf5e, 0x1482c3cc, 0x66f352af, 0x83f76523,
3273 0x7257a889, 0xa44f5a25, 0x4660cfe6, 0x40dfd7c4, 0xbe9313ff, 0x66967fa0,
3274 0xecedebe7, 0xe13b7dea, 0x6e5136e9, 0xb4761ace, 0xa17be014, 0xbae0764e,
3275 0xca0c5bb4, 0x9e506b91, 0xe43131ac, 0x4d070b8f, 0xa3df2e4e, 0xbf949f49,
3276 0xfa84c272, 0x82731cb0, 0x09ffc798, 0xc4271bd7, 0x3d02de78, 0x2898c4ec,
3277 0x093a1fab, 0xd1c53fde, 0x9cf30e34, 0xacb48753, 0xe4ee38c4, 0x2391fb22,
3278 0x32d5cf88, 0xaf1e7c43, 0xeb3f222b, 0xe2243bce, 0x6f0037af, 0x94ea7ed8,
3279 0xe047239c, 0xc97565bd, 0x75295314, 0x0d3cdf26, 0x6507a5ca, 0x66f50287,
3280 0x831b18df, 0xfd09d7f1, 0x830ee665, 0xae0b194f, 0x6957f8c4, 0x71531dcd,
3281 0xe7a015dc, 0xe15d1f30, 0x8a97196f, 0xb5128de5, 0xe6dd78f7, 0xe09d2054,
3282 0x21e67386, 0x5079fef0, 0xd9eec10f, 0xb679ebc8, 0x754c0e48, 0x27aff3cd,
3283 0x8b6f3879, 0x598970c4, 0x2b58ec10, 0x8567d7ef, 0xa11b837e, 0x63e7943d,
3284 0x4b77ec7b, 0x90d3cdfc, 0xd49c618f, 0xfdb2c47e, 0x41e72f28, 0x82cc783b,
3285 0xfea0ee5b, 0xb128df6e, 0x62afe834, 0x47cfce44, 0x4d077f60, 0xb47e7c0e,
3286 0x671457e9, 0x4bef099f, 0xcb67fe87, 0x9d68e3ad, 0x3b258fd7, 0xb92abbad,
3287 0x5677f099, 0x9b4b19f0, 0x47baf64a, 0x6f3daa62, 0x3edb8f0c, 0xe89bdc96,
3288 0x65d2de78, 0xad5e70ab, 0x031ce4de, 0x5a39d5d1, 0xe0127897, 0xf43b06ed,
3289 0x83c79984, 0xcc27bd9b, 0xb37261ad, 0xf10fb939, 0x42c69ce5, 0x3aea2f92,
3290 0x6e32f70a, 0xb4adb467, 0x36987ad1, 0xef1b3d93, 0xd0b4af37, 0x5c1df6fd,
3291 0xb567b4bf, 0xdc7e83be, 0xcc4d1b07, 0xbe5c630b, 0x88c3cfb1, 0x9bb60fc7,
3292 0xdfe4de88, 0xcd8e4898, 0x5be3c1df, 0xbf791bcd, 0x72e36c1f, 0x5337e8ad,
3293 0x9ebca3c7, 0x42c9f20f, 0xafcad3f3, 0x1e02ca79, 0x89b75d47, 0x9557cbf4,
3294 0x53e45d53, 0x5f1455cf, 0x7aef4eec, 0x77aa8c58, 0x5ebe31f2, 0x7335955e,
3295 0x196fd203, 0x03068c4f, 0x087d3fbb, 0x2c6569f5, 0x46d53bc3, 0xa712c3fb,
3296 0x96c7ca07, 0x8a7e77fa, 0x6a515ff4, 0xde1e2073, 0xbf23f847, 0x78a44dac,
3297 0x395f3cea, 0xab3e79c1, 0xdfcf3821, 0x356fa5a0, 0x2ddd386e, 0x9eb86733,
3298 0xce6688aa, 0x7f477ab0, 0xef0a7402, 0xf928d599, 0xdb96126c, 0x42192ff6,
3299 0x6b8d3b65, 0x6bfbd0a9, 0x8f8e8963, 0x4adcf0fe, 0x7799d3a4, 0x6eed0c4b,
3300 0x42af75e6, 0x41bd57bd, 0xd6bd7052, 0xfb79bbfc, 0xc71ed0f9, 0x9c57f47d,
3301 0x15ae809e, 0x8deafba4, 0xfd53f7eb, 0xfd82922d, 0x4e54dd1f, 0x57854276,
3302 0x4b7cf466, 0xa001f91b, 0xd30f2897, 0x905395ec, 0x5857abee, 0x57d798ec,
3303 0xc7a547e9, 0x661f9136, 0xc9a0c756, 0xb2516ed0, 0xe50e9112, 0xdea75269,
3304 0x78f17a44, 0xedb57d39, 0x25903930, 0x7c8f4f2e, 0x6f4a825d, 0x90dbd232,
3305 0x6f35bd10, 0xfd23322c, 0xebe3e07d, 0x5e908a11, 0x571f1e91, 0x262c2ae3,
3306 0xe9523edc, 0x07e80ab1, 0xe8e5f4e5, 0xd3fa3bb1, 0x02f81dd3, 0xcee47eb4,
3307 0x771a3695, 0x37ddaad1, 0xc47ce52f, 0xab459c70, 0x8179487e, 0xff1e4679,
3308 0xeb88e156, 0xd24f30da, 0x2e0f1c65, 0x997fa733, 0xf1c6e8f1, 0x10d8e48b,
3309 0x96e803fd, 0x01bac59b, 0xe5039443, 0x5698c4d3, 0x31e304a3, 0x51187525,
3310 0xe14f0f3f, 0xc23979fa, 0x3325eb0a, 0x67281f5a, 0xacee081a, 0xa3d7c297,
3311 0x876476e6, 0xa67b63c7, 0xb06efea8, 0x189fde27, 0x5851e50d, 0xff404db6,
3312 0x5745a26e, 0x60a061ee, 0xbc516313, 0x5eca2a9c, 0x4c9d0328, 0x479f54cc,
3313 0xd12f72f3, 0xebcd1bde, 0xc79f500f, 0xead5f2f0, 0x7f5e18f3, 0x99e7a334,
3314 0x7013b129, 0x14cf573d, 0x237c66bb, 0xfd0d4951, 0x62d957fa, 0x6eb489a8,
3315 0x9a8a6fa7, 0xaf146787, 0xf4fff976, 0x5cb5e606, 0xf90098d6, 0xe9d34e07,
3316 0x867b30d6, 0x13ca7589, 0xa4b23d04, 0xae0bb238, 0x2f01bfc7, 0x26818c13,
3317 0x06b06f6c, 0xb0573f08, 0xfbf7f615, 0xf65222e3, 0xdd05e7e0, 0x56a86bfb,
3318 0x6ff30fde, 0x4b632725, 0xc524ae81, 0xe590f94e, 0x46db994b, 0xed4b94eb,
3319 0xcc49bf68, 0xaf9cf869, 0xfbe17657, 0xefa8f1d5, 0x802e32ef, 0x7c2131b4,
3320 0x1fa91b5c, 0x07675c75, 0xb798bc5b, 0xfd618ef4, 0x74e0c26b, 0xf08ae916,
3321 0xe22264b4, 0x098daced, 0xac728bbc, 0x8447fcfa, 0xeaf1b3d7, 0xd64e5173,
3322 0x95d74f3d, 0xa4febc4d, 0x78272b94, 0x64b3bde1, 0x6814a4e7, 0xd0c73163,
3323 0x28baeaba, 0xbee5debe, 0xed17b764, 0x5a73a023, 0x32cde497, 0x76317f93,
3324 0x5f0ce488, 0xd043315f, 0xb114b1f5, 0xaeb2d94e, 0x0ded05a6, 0x4196c3f0,
3325 0x0ba5cf7d, 0x4c4f8c66, 0x9199b7f4, 0x401baaee, 0xcb15e26e, 0x68dd5798,
3326 0xf75a4676, 0x56452a76, 0xf59a17e3, 0xfab2fbc0, 0xb9424cad, 0xafcb873c,
3327 0xc7e3bb45, 0x39517961, 0xbd6ff7b7, 0x0438e766, 0x69ab9941, 0xb1675e25,
3328 0x8a687dd6, 0x74517ea3, 0x4edc25fa, 0xd449ab2e, 0x03ad6794, 0x75c20e6c,
3329 0xfef5da99, 0xa7b9e44c, 0xe30fd0b3, 0xde04d38d, 0xa5ada7a7, 0xb774f7bc,
3330 0x44e73d76, 0x026332ff, 0x2246bb8e, 0xb8e6093d, 0xf066ed82, 0x6c35c219,
3331 0x7dc0385d, 0x67d0a35c, 0x97ce5c95, 0xb4a97f0a, 0xdd17af82, 0xc2666597,
3332 0x7f71f2df, 0x84d8fd6a, 0xa3f71421, 0x7f1efef5, 0xcfeb098b, 0x137e0258,
3333 0x4ec97bf7, 0xda0ea598, 0x86e60ceb, 0xe3c61b8d, 0xe755fa45, 0x3ee50d35,
3334 0xf5edc3ae, 0x10ed09be, 0x5d668f98, 0x6d0a8ce9, 0x5b46acb9, 0xf733afd6,
3335 0x3b3908a5, 0x7e400d80, 0x19229adb, 0xf944ff89, 0x5791d674, 0xefae0a03,
3336 0x194b6d74, 0x0747eb4a, 0x295ca1a1, 0xf9dca9bb, 0xe6a81cdc, 0xc78c07fb,
3337 0x25cf895b, 0x26e5dfe2, 0xe310bda7, 0x0fdc5529, 0x35cf819e, 0x7d7806eb,
3338 0xcb5dcb2a, 0xfee14d7f, 0x6b9b72da, 0xc12dc531, 0xc13cc54f, 0x98d3a358,
3339 0x307c4790, 0x7b3c922d, 0xabffd05b, 0x8c15b40c, 0x25121fab, 0xe4dfa5e0,
3340 0xcf8c3e1e, 0xb963fbf5, 0xfd53e317, 0x0aef000a, 0x779e05ca, 0xaef2209d,
3341 0xb33e8037, 0x5c9fb5c1, 0xc7f48d3f, 0x176e66d5, 0x2aac7c8b, 0x6b8f9c4f,
3342 0x7a13b1f3, 0xe50cf81e, 0xd61b0dce, 0xdb99ff92, 0x1ebf99c7, 0x8d9f77c6,
3343 0xddbeffbf, 0xcea98fdc, 0x35f24fdb, 0xf4f229d5, 0x36ce4269, 0xe7559c82,
3344 0x454df80f, 0x64fe87b9, 0x37bd1e49, 0x87bd73bd, 0x14a4e493, 0x1cf86318,
3345 0x78aa57e4, 0x0a599def, 0x41652bc1, 0xcef384bd, 0x6865de62, 0x6819ff37,
3346 0xd7abef0a, 0x533ebdaf, 0x56ebf491, 0x541d2067, 0xf58ab5a5, 0xdfcf5faa,
3347 0xe7fe82fc, 0xf7d41ca2, 0xebe7d30f, 0xec4ced04, 0xf144b847, 0xde2e3540,
3348 0xad917e9d, 0x30dc8d06, 0xf234a3d9, 0xad7f4265, 0xd0e899bc, 0x471b99ca,
3349 0x9f3cd1f4, 0x79a01ce4, 0x40b8b93e, 0x1aea9e53, 0xcb7fa9ad, 0xd94d22b4,
3350 0xa6bd7692, 0x49b94dbe, 0x7fee8e53, 0xac7ea6ab, 0x73cd36e3, 0x4ecf4bcb,
3351 0x662e0093, 0x0dd5b7ab, 0xde03a870, 0xd2109118, 0xace2031b, 0xaa287eb4,
3352 0x6c7e46c0, 0x004b60dd, 0x832ea4e9, 0xbcb0d3ef, 0x002d24b4, 0x6c7b58fd,
3353 0xf5c216b7, 0x0c6f92f7, 0x62ac73c6, 0x7755f61d, 0xf95e8d33, 0x2be70665,
3354 0xaa657af5, 0x5c1a687b, 0x9929b6f3, 0xf068048c, 0x358fc42a, 0x6bbb718a,
3355 0x7437df17, 0x91cfea35, 0x64967ea1, 0xc54a0e15, 0xaf3b7776, 0x91b3bf23,
3356 0xbd42fbd9, 0x91bf62cd, 0xda999777, 0x1ab635e5, 0xfdfc619c, 0x0f2e5487,
3357 0xb98d721e, 0x32f8898e, 0x0deac3ea, 0xf7e8cdc7, 0x689bfb57, 0xd720e1dd,
3358 0x16f7da71, 0x9af42fba, 0xd70a23b1, 0x1f553d3d, 0xc2e23d79, 0x6bcd3354,
3359 0x65e390bf, 0x7f61644b, 0x2aa4f8f3, 0x7676cb97, 0x1b8c6404, 0x93e36954,
3360 0xf20d397a, 0xded76359, 0x7140223a, 0x11d3900d, 0x0f5545fd, 0x3cd6dc80,
3361 0x3af6859f, 0x7943275f, 0x9ae39023, 0x4553d3e7, 0xcb006b3c, 0x6fc275c3,
3362 0xe7110cb8, 0x1e0cdbf7, 0x5dc37ebf, 0x087f7044, 0xc21216e3, 0x0e2f0f53,
3363 0x69c1cbc7, 0x15bf9a87, 0x7bd7d2f8, 0x6be3832a, 0x3a723747, 0xceedca90,
3364 0x1f3052cd, 0x15c7a885, 0x033af445, 0x2014a5d7, 0x0ab6fe1e, 0x67b2a8fd,
3365 0xf4fa8625, 0xd12f4daf, 0xae33263a, 0xa438c24f, 0x6954bf58, 0x7fa19652,
3366 0x40e0f400, 0x31baa6fb, 0xaaafe340, 0xfbc2682f, 0xce3c8d55, 0xf1e069e2,
3367 0x4ad66acb, 0x6ee6dd7e, 0x2a6f75c6, 0x5207efa7, 0xc7bf1a15, 0xbd44ef0d,
3368 0xf9f160de, 0x2b7fc424, 0x76ca57c5, 0x941d6c4b, 0x4eb6af37, 0x3d2f648b,
3369 0xe2fde02f, 0xf5c3336a, 0x1ed095e6, 0x6b3fb1e7, 0x3be319bf, 0xca253b65,
3370 0x5bea7867, 0xd6be62a6, 0xd0c4d8b3, 0x77c7508e, 0x7e482b26, 0x84739be4,
3371 0xc787391f, 0xcc5cde2d, 0xee790fed, 0x9d57147b, 0xc8fc255e, 0x0e281739,
3372 0xf08566f4, 0xb8f2e723, 0xd43bf4c7, 0x8e968ebc, 0xd3d53a55, 0xf56e9e9f,
3373 0xe955faf4, 0xa76a4773, 0xf508319d, 0x1c7be03a, 0x1fdef1fa, 0x4c27ca32,
3374 0x426cd4bb, 0x2af7bf3f, 0x281ee3bb, 0x2b7d940f, 0x9ace5e31, 0x95c1f3f9,
3375 0x5f2e249b, 0x3e715b94, 0x86667599, 0x020239fb, 0x53c4014f, 0x43a94e32,
3376 0x357e468a, 0x1ca37b06, 0x0175c1ca, 0xc1a7c700, 0xf949dfcf, 0x065f2e25,
3377 0x69b6973e, 0xd6bd184d, 0xcaa2b908, 0xe66601bd, 0x017189de, 0xc6067d63,
3378 0xf8987717, 0xd16c963e, 0x1d3edf5f, 0xb5c127e3, 0x65ffbc4d, 0x7fcb5571,
3379 0x94fe10c9, 0x75c11673, 0x5da3c8a2, 0x8a5034bf, 0x744ec8f3, 0x6f315307,
3380 0x12a47d99, 0xef5d5af5, 0x1fd0f397, 0xabc3d751, 0x91e6f471, 0x13bc6c1f,
3381 0x32bb6be6, 0xdb69f08a, 0xf48edeb3, 0x243beb6b, 0x57de5235, 0x2a2e7abd,
3382 0x53fc0dcc, 0x5d37b17d, 0xbda4f2d5, 0x6dfd68a7, 0x78dcffb5, 0x698b8fe2,
3383 0xf76d5f74, 0x81ee3127, 0xf32cff62, 0x065e9127, 0x911c6cb9, 0xc2a7aa1f,
3384 0x68e75d41, 0xf085bbeb, 0x3c1de775, 0x7ad8c1bf, 0x654667ea, 0xfd0e548b,
3385 0x9a7262dc, 0x47de0062, 0x709b4c7a, 0xd5d71732, 0xc1c1b8f3, 0xa5c52b5a,
3386 0x53b5ad5e, 0x469b5839, 0x156bd7e5, 0xec915eba, 0x34e104fa, 0xbe9ac5f5,
3387 0xace6b708, 0xa7985d87, 0x44d07b3c, 0xaecc60f0, 0xc17de7d9, 0xea3c532f,
3388 0x5f5f0342, 0xe67f8ea2, 0x4ee60cc5, 0x8a6371e4, 0x0bfd2c57, 0xc54739c9,
3389 0xf7e8f1b9, 0x5b6cae0c, 0xd2cf6585, 0xee9d694f, 0x282fa03b, 0xe3c8d1ef,
3390 0x2d8d55a7, 0xf4b9ceb4, 0xb3f50262, 0x1e31d0c3, 0x82fbccf9, 0xde3beb44,
3391 0x4e673c69, 0xd288fae5, 0x7c451b3a, 0x3c5a4879, 0x1fe3c1c1, 0xe5f8e06c,
3392 0x8245d579, 0xfaae9a1e, 0xc3e21c47, 0xf5a154ba, 0x6407d522, 0x19acb38a,
3393 0x8f6711d3, 0x6e317720, 0xde93eb8d, 0xf494eb12, 0xbd99a7cf, 0xc07d717d,
3394 0xfde44334, 0x50b48ecf, 0x75d71f7e, 0xc7f53297, 0x3f83d7f7, 0xca88eb43,
3395 0x8ca745fc, 0x6ef9ad78, 0x196acff2, 0xfdf0c1fd, 0x320fe806, 0x34bdfbcd,
3396 0xae564b7e, 0x85d6ef26, 0x98335bfe, 0xaeaa7802, 0x20173003, 0xd7455f9d,
3397 0x2af7ddf6, 0xa8d637c8, 0x2f51878e, 0xf2067eb0, 0x5abcaa27, 0xe84b273b,
3398 0xee0cacad, 0x89a7173f, 0x2fc2b2fd, 0x4267ff02, 0xe27ff71a, 0x5f8d32f6,
3399 0x7e4fbfa4, 0xc7ec5591, 0x7978001e, 0xafb8c23a, 0xc2e318cc, 0x1d6cd976,
3400 0xfa0337d1, 0xcfd2ba46, 0x1f1a4673, 0xd3cfca97, 0x28f39f91, 0xacfc4ece,
3401 0x464877ef, 0xcfb40ce1, 0x5fb37756, 0xefc12aeb, 0xc1181b55, 0x8121b3cb,
3402 0x6d8674e0, 0x7a018d70, 0xd8e3033c, 0xd678f40c, 0x878e8ae5, 0xaedd67f6,
3403 0x109884e8, 0x886f57ff, 0x73ab76a2, 0x872c4a6f, 0xf7a08d72, 0x2b22c6f6,
3404 0x06e679c2, 0xfbea77ce, 0x4f4c09de, 0x6a1a3e44, 0xde6330ea, 0x2dbfa7ae,
3405 0xa1bbed0e, 0x222727bb, 0x4e3775ff, 0x779f3a77, 0xb445d2d5, 0xb87f155e,
3406 0xd0a1627e, 0x3a7b9e63, 0xd57ca11e, 0xdbf44652, 0xd5afebb4, 0xfeedbfc8,
3407 0x9e6bca68, 0x7a4d13d9, 0x3cd3ecf0, 0xd4c679af, 0xaa60eb4a, 0xf476cb77,
3408 0x7c2f3d07, 0x9ff230fc, 0xa1459767, 0xdeffbd78, 0xb6aeb873, 0xad1d7fd2,
3409 0xfedca8c3, 0xd541f2dd, 0xfec8bbd2, 0xd71fcb51, 0x37285d5a, 0x2e5c8ddb,
3410 0x867c6c2c, 0x9785d9ec, 0xfcc20c2e, 0xff3d99ef, 0x98e50c3d, 0x86178fe7,
3411 0xe7ec3ed1, 0xe7c30c2f, 0x6ba2e79e, 0xef25d922, 0x8e38f066, 0x0e731faa,
3412 0x9ef13519, 0x73fe8209, 0xc62bac56, 0xb6864d73, 0xaf84714c, 0xd7da1b1b,
3413 0x8617fb40, 0x389b1e1e, 0x8addac37, 0x392fdf20, 0xf46c65a4, 0x747a309c,
3414 0xb8d49866, 0xd38ad7d1, 0xa11fb130, 0x34132e33, 0xd5843ed0, 0x6f3f2341,
3415 0xa1f242a0, 0x8a7600ff, 0x4bd91dbe, 0xe44f6f67, 0x5d1832e7, 0x1d220613,
3416 0xf697dedc, 0x75af3387, 0x3d986e5f, 0xa0683d34, 0xfcd3ddf5, 0xefd90096,
3417 0xefad2341, 0x99a4ed56, 0xcd883ee7, 0x5dc42291, 0x0e3ebffa, 0xfe3eb6e5,
3418 0x6ec6b3d2, 0x2fef0898, 0x08ecc15d, 0x063c7d3f, 0xfb9db17e, 0xf8d75992,
3419 0xd07c128c, 0x5c95ed8a, 0xa7c71d83, 0xb78899da, 0x3efc0886, 0xb3f39d2d,
3420 0x822b47ca, 0x8ac7c206, 0x2e6b18e0, 0xe789275c, 0x7136a00d, 0xff0ae8df,
3421 0x1f18ade4, 0x96e97158, 0x9ef081e8, 0x626e8715, 0xdbbf20f7, 0x62fb58c7,
3422 0xb7df4bbb, 0xd10bcd4e, 0x4a7dfe89, 0x2127d73a, 0x7eb2207b, 0xfbfc178b,
3423 0xd8b9e95d, 0x3d6cfff4, 0x52757e07, 0xabf250fa, 0x07b8f067, 0xfaf5abf7,
3424 0x6abb9541, 0x7e04e3bf, 0x53ddcabb, 0xff80bf64, 0x5c77724b, 0x7af542ba,
3425 0x922527fa, 0x4a687c5f, 0xb5d312a2, 0x87463eff, 0x6baf2121, 0xe69daaff,
3426 0x59f73af1, 0xf2717fd1, 0x8a6796fc, 0x90a493e4, 0x4971e75d, 0xa9649f7c,
3427 0xd4f587c9, 0xf0a70571, 0xa754e9b8, 0xaa86f289, 0x87daa7fd, 0x3c1dcf9d,
3428 0x8bdaa8af, 0x74185daa, 0x94ec38f1, 0x15f9fc21, 0x106beec9, 0xf588ef5e,
3429 0xf247432d, 0xf6b98cfb, 0xcb747fa1, 0x7e2312cd, 0x4aa2f617, 0x527b7a9f,
3430 0x1ddf6f5d, 0xba0a371e, 0x5b2bf954, 0x9eaa17c7, 0xba7a11aa, 0x2274f51a,
3431 0x34cfe9ea, 0x5fbeb776, 0xf4aed3d0, 0x08c76c64, 0x1b0e43be, 0xeefc915d,
3432 0x375fa213, 0x3dae0fe2, 0xe2162f83, 0x7058b378, 0xdd8bfa19, 0xb0974fe9,
3433 0x5e7bba63, 0x5f9fc693, 0x08d78f8e, 0x7c577ffc, 0x9c3feabc, 0xbeed3b8f,
3434 0xba23ce6e, 0x7ef0a332, 0xb928dba4, 0x7c885826, 0xc51367f7, 0x4af5f5c9,
3435 0xff063e85, 0xfbbf4355, 0xf406ccb2, 0xdc153c77, 0x578bafff, 0xe4bf235e,
3436 0xd5d69925, 0x0eff042c, 0x1705b3ed, 0x44ad74ed, 0x33ae183b, 0xfe50b5b6,
3437 0x76854660, 0x831875fc, 0xe477f6c5, 0x32fc7ad0, 0x44e29636, 0x3b78fe65,
3438 0x4baf23ee, 0x86f5a7ae, 0xb2b2adde, 0xedfebc35, 0x8f2b7d6a, 0xf74d2d9b,
3439 0x6b79e72d, 0xab2fbe8d, 0x5af3dbd1, 0xc45a3ffd, 0x03b3ba7d, 0x71b26f9e,
3440 0x26407279, 0x78c6aefe, 0x998cd5d1, 0x4bd5f5d5, 0xdaa39c79, 0x23f68cbf,
3441 0x1fe78957, 0x4714831a, 0x5417fca2, 0x9f5fe53d, 0x9cc87c82, 0xd54f7cda,
3442 0x2724c396, 0x849f79f5, 0x3c8f2e06, 0xf3c8b295, 0x7d68930c, 0xa7d8a363,
3443 0x223728aa, 0xcc5c61dc, 0x863ee0a7, 0xce3fe413, 0xf325fdd8, 0x17f84e3c,
3444 0x7fb3cf31, 0xf972a65f, 0x63754f3c, 0x84fd098b, 0xde7be5cb, 0xc38cef49,
3445 0x97b09c50, 0x7b5fc791, 0xc63b25f9, 0xf5897a97, 0x4757c37e, 0xc77ff5f1,
3446 0xdf2224e6, 0x9f6978ab, 0xfed9e1c4, 0xd88527e6, 0xa331d86e, 0x3e11d71d,
3447 0xbfe2e6ff, 0xad32f264, 0x6c7f18d3, 0x25fa3471, 0x4516c7ed, 0x879f3c23,
3448 0xb9e3e22b, 0xe3118c37, 0x78a1e589, 0x7bd205f2, 0xb2788b77, 0x6c5ef411,
3449 0x6fa32e28, 0xd72153f7, 0x8adf30ea, 0xe79bb974, 0xddd2ebfd, 0x57f953d7,
3450 0x13ff69bd, 0xbcc279c3, 0xc63a019e, 0x9800cfb8, 0x9f95e62c, 0x302b628c,
3451 0xec9753cf, 0xe6f8997e, 0xf9050657, 0x7e53da06, 0x2153bbc8, 0x55a1883d,
3452 0x020cc3cc, 0x7da563dd, 0x8f944979, 0x2fe04ab9, 0xf452fc1d, 0x5334610f,
3453 0x403c8f30, 0x450663e4, 0x7ff62331, 0xe6bdc99f, 0x34ffcc4a, 0x88cb1d19,
3454 0x93891de8, 0x85e6bb62, 0x77cf2724, 0x3521f9ab, 0x7e5dddef, 0x0cf7c248,
3455 0xf945f4e2, 0x3094e620, 0x81e6ae1f, 0x4a2ecdd8, 0x511f2d4e, 0x7967e743,
3456 0x9d37d8b2, 0x8b4a29ff, 0xa5719f90, 0x6bef6131, 0xfa6b81f3, 0xfa744d3f,
3457 0x6b80f355, 0x71e9bfd2, 0xd5efdc2b, 0xfc487b8d, 0xa3f214f9, 0x3a77f9fe,
3458 0xffb560b7, 0xb3bde902, 0x0e71161d, 0x938f2b45, 0x2f144dfb, 0x58fe0b38,
3459 0xdd3e9872, 0xddfbc69e, 0xfa222feb, 0x8d8e086f, 0xc487fac6, 0xa687d5fd,
3460 0xde7b464c, 0xfa3a341b, 0x7fb848d2, 0x0e3410d5, 0x1be4fb45, 0x7a694bc4,
3461 0xa359f984, 0xf3d23eb8, 0xbfe09c51, 0xe70e0cb8, 0x5fb937a2, 0xf3cc59e5,
3462 0x1d75761f, 0x73cf0d70, 0x914acfef, 0x6a77f8d4, 0x6ec8fca4, 0xecbd2ebe,
3463 0x2df68976, 0xc8fcd97f, 0x7fb6c68c, 0x8fa23f2b, 0x219ddf3b, 0x790322f2,
3464 0xdd23b9dc, 0xa84bf34e, 0xfb885c19, 0x7ef9d49e, 0x901f7083, 0x43e6edf9,
3465 0xedf9efaf, 0x352fdff6, 0x837cdd02, 0xcb7d97fd, 0x96fc2ffd, 0xf52fbffb,
3466 0xdb7f85db, 0xcbffdcb7, 0x8fff72df, 0xff07d244, 0xf5ebe6af, 0xfe7d78f9,
3467 0xb7979f5e, 0x8bd734bc, 0xd695eecf, 0x6ae00476, 0x4d35db8d, 0x8c687902,
3468 0xbd4562df, 0xe7923259, 0xb58f56af, 0xa14936fa, 0xaf0abe3c, 0x3fdc5991,
3469 0xf39de7b3, 0x6ce356e2, 0x226c7067, 0x3246bbc6, 0xdacf6ff2, 0x198b1e78,
3470 0xd798e9ed, 0x37e99a82, 0x67521d81, 0x7d079c8b, 0xf7f0a7af, 0x4b1bd1ba,
3471 0xc8af0ab2, 0xfed5a64c, 0x59f648ce, 0xdb2f88ad, 0x17c5191b, 0xbf495199,
3472 0xa4abde89, 0xe3d3fda3, 0x2e3f7e45, 0x689b9cc0, 0x4dce4a5c, 0x928f6e74,
3473 0x407be383, 0xae1367e4, 0xf18397ef, 0x03b004e4, 0x1eb78f31, 0xa7e479f3,
3474 0xfa9ea9da, 0xdc99ddbe, 0xc4c07a4f, 0xef305ce8, 0x11dd7c95, 0xbd9156b3,
3475 0x0ee1e6a6, 0xcb27029a, 0x8dc3ca25, 0x62bff1c1, 0xce6de408, 0x449c4411,
3476 0x3f296dfb, 0xdfc8eaf8, 0x7bd377f5, 0x86fecd14, 0x6187f466, 0x29ee771c,
3477 0xb19dfa20, 0x6fed2477, 0x091ae4f0, 0x46fc5dce, 0x43780711, 0x38d431c4,
3478 0x7a8f9a80, 0xde3fc45b, 0x3f4ab8c1, 0xa1584f3c, 0xc34caceb, 0x5a9e77bf,
3479 0x159cfe57, 0x203d3f49, 0xf78fb8f1, 0x29f71e15, 0x84fa3b30, 0xccac7faf,
3480 0x0f2c78e4, 0x1a83bcf0, 0xcc4279c7, 0x7287e0a7, 0x687602c0, 0x6681aac1,
3481 0xab05ebd4, 0x3af0a2b2, 0xa433e9c8, 0xcfa7bc00, 0xf15069d9, 0xee8e8917,
3482 0x89f114ca, 0x8f941d03, 0x9797467b, 0xd7c99ddf, 0x7165e41b, 0x64ceeefc,
3483 0xafb3be54, 0x8b9a3971, 0xcbb1ae3d, 0x6541f291, 0x38e2f7e0, 0xb8f8ebcb,
3484 0x05977855, 0x4f7c2294, 0x558ebedb, 0xc8afcd78, 0x79b8a229, 0xb455b9e5,
3485 0x85d2e9bf, 0x1c52d7fd, 0xffa0accc, 0x1b55b330, 0xc5909b4f, 0xa0cfe7e3,
3486 0xbb708dc1, 0x6ffe48ce, 0xa24675c1, 0x1b32849f, 0x2609a7f9, 0x7960c726,
3487 0xf283b712, 0xb08a938b, 0x93c4a6cc, 0x407f97fd, 0x179b9f89, 0x5c256f8a,
3488 0xe11938b7, 0xa8bcb974, 0x22bb271a, 0xa44bf9d9, 0x179aafdf, 0x88783aad,
3489 0xf3aa7bd6, 0xe6a2e152, 0x8bcbbb37, 0x3c12ebaa, 0xd6689fc5, 0x1d8c7851,
3490 0x58ae31e3, 0xaccda7b0, 0xcb4b37ee, 0x0b4de509, 0x7ca39f76, 0xf51f9aa9,
3491 0x3b239cd4, 0xb199da1a, 0x3fa0017d, 0x4364e41d, 0xee9bcf2d, 0x1a7bfb12,
3492 0xae78fe61, 0xfe601ff6, 0xfcc3f578, 0xb50bfef1, 0xa81ae9fd, 0x6f75d075,
3493 0x7aba08ed, 0xcf28e7fc, 0x36a642fa, 0x8f99d75f, 0x084d5d93, 0x1d7cb0af,
3494 0x3af9f595, 0x63c78a39, 0xee303f70, 0xb41cf21f, 0xf42efc92, 0x7f42f797,
3495 0xee2d6fe0, 0x6aee385e, 0xd18597cc, 0x61d3bb45, 0xdb6c73c3, 0xe61b0e5d,
3496 0x4e9a0ac9, 0x6a847ed1, 0x15ce9063, 0xa6073ce8, 0x775f1ce1, 0x21b42feb,
3497 0xd79b2f7c, 0x79fffc6a, 0xd7932fad, 0x32f905ba, 0xf23f2439, 0x26e7065d,
3498 0xda701ebc, 0x87c986e6, 0x179e2ed5, 0x9bdb9d59, 0x5741eff8, 0x6139f8ef,
3499 0xe628adfd, 0xeb848a71, 0xf7e16d72, 0x79e2c89f, 0xb98904ac, 0xe4b1c922,
3500 0xbcb8df9e, 0xef648e4e, 0xf402bfb7, 0xc3d03578, 0x5abdf9ee, 0x71b4ae89,
3501 0x73c5d5b6, 0xdbb9e17a, 0xac2c37de, 0x69c38f2f, 0x974c6ce2, 0xde2eeb4f,
3502 0x40d8a336, 0x7bc2e2e7, 0xeb5f51b3, 0xd8cc62e3, 0xb9f5cd91, 0xe4739c53,
3503 0x582364cd, 0x5bdabc97, 0x173877cc, 0x362f4fea, 0xf3509e90, 0x46c5f96b,
3504 0x99f40b56, 0xa3e4d4bf, 0xb1b15abc, 0xff0b9e8d, 0x3f3d8570, 0x3bc9e513,
3505 0x8c76cd07, 0x60e3e9a3, 0x752de28e, 0xa3bda1bd, 0x6d7da252, 0x373fd65d,
3506 0xf8c38d36, 0xaeb660d9, 0x1bd42c6e, 0xe3b06b9c, 0xe5cbe57a, 0x3d85f2e1,
3507 0x219f8fa3, 0xa1fda15d, 0x2f5fa38f, 0xb0bd7ef0, 0xbf43ee97, 0x8fd43932,
3508 0x2f4f4eda, 0xbe94f68f, 0xbf7f2e30, 0x71456fe8, 0xc45ceafe, 0xa1818967,
3509 0x3c5158de, 0xd61b9ac6, 0x234f595f, 0x7986af5f, 0xbcf0a4bd, 0xe9dfcf1e,
3510 0x3caa79f3, 0x8cfa682b, 0x083efff6, 0x95f51972, 0xffc78d27, 0x3c285e0b,
3511 0x34227280, 0x1f9fae4e, 0x37bf534c, 0x7c6788e0, 0xd14fb45e, 0xb8a247bb,
3512 0x27c97e5b, 0xcca1a37b, 0x7fb4f15c, 0x773073de, 0xef939e39, 0xc50e3129,
3513 0x971e3afd, 0xc22799d4, 0xd7e4d07c, 0xf5c7ae2a, 0x075305fc, 0xa67e20b7,
3514 0x9d689a96, 0xa6d7e4de, 0xaae539d1, 0xba982b9e, 0x7c289ee9, 0xf3a25fde,
3515 0x56bf261a, 0x4f9f063c, 0x88c01ed8, 0xb3889b38, 0x3c193907, 0x7c88d278,
3516 0xfbb24572, 0x0537c827, 0xa89e4493, 0xa9e3eb94, 0xc62649fe, 0x7e8d46ed,
3517 0x1bface6c, 0xf3d479c5, 0x7d711204, 0x2f485e42, 0x7d01ec15, 0x57d21b15,
3518 0x7a9eaeff, 0xe09da7b4, 0x2be83579, 0x24c24f1c, 0x62ef4f9e, 0x77fc08bf,
3519 0x93ba7fa7, 0xc467a8bb, 0x529983f9, 0xad7d575a, 0x38673c60, 0x9d12e5da,
3520 0xfd1dd683, 0xcfec26bd, 0xb6ec6ef8, 0x76fd04d7, 0xf1a9aebb, 0xfd13c9bb,
3521 0x787fe7b9, 0x57f8489e, 0xf548be6a, 0x7b09fac7, 0x215ebd57, 0x7b7fbbfc,
3522 0xd12a013f, 0x1209fb88, 0x9827ef22, 0xbda12f59, 0xd827eea4, 0x3b856667,
3523 0xab3d7093, 0x73e44fd8, 0xefb41d91, 0x7aad6fd7, 0x7bce893c, 0xa0cc6dc0,
3524 0x9f485af7, 0x43fd8157, 0x63ff92f6, 0xe7ad3f1e, 0x1aabb1eb, 0xd496fbb5,
3525 0x5f616ceb, 0x50f9858f, 0x77ac459e, 0x91ce2f1d, 0xef21c508, 0x21c78632,
3526 0x59304a3d, 0xe3eb475d, 0x5c4d1779, 0x6438bbb2, 0x75a0eb35, 0x9215d5b3,
3527 0xb7c3f503, 0x91ec971d, 0xddaf5da5, 0x83cb9327, 0x42496e69, 0x706ad5fb,
3528 0xf8bad255, 0x6c7ef817, 0x66fa7c3d, 0x413c7971, 0x331e31e4, 0x6c787a73,
3529 0x5bfb4494, 0xe21c1f70, 0xf817b1f9, 0xf2c7973e, 0x35173ef9, 0x5feea16f,
3530 0xb79432b9, 0xea6ffda0, 0x1f7517be, 0x780fba8b, 0x00a886d2, 0x99f707da,
3531 0x1db8d3ea, 0x3c3a25eb, 0xf3d193dc, 0x6f3f0b28, 0xf8ce3f5d, 0x28c3c2ac,
3532 0xf37f0f87, 0xac88d176, 0x25a67108, 0xaffc2fc2, 0x98fb2eac, 0x30bffb54,
3533 0xfec6a86b, 0xfedeb2a7, 0x16f2a6ff, 0x6f9f0141, 0x32abde70, 0xe6f8ddbf,
3534 0xfc72df67, 0x7b247cfa, 0x4b88b976, 0xd9e7e9e9, 0x68bf552c, 0xbac34bbf,
3535 0xfae43fec, 0x8e524ebb, 0x2f6bb9d2, 0x542573f1, 0xcb175a39, 0xe4215ffb,
3536 0x547d7aa7, 0x914ceb5c, 0x884f5fe3, 0xe764b3e7, 0x0193a472, 0xc8f1b4db,
3537 0x78daf581, 0x098dd5e4, 0x40e0f29a, 0xc17ea686, 0xe79ade81, 0x69578343,
3538 0x237f0f9e, 0xd91e535f, 0x7f534a3a, 0xb46387f4, 0x68755ae7, 0x5ed791e3,
3539 0x2fb749bc, 0x2bf047d2, 0x6f0dca04, 0xad9d6457, 0xa15997a9, 0x8d56579d,
3540 0x96bd5e76, 0x2fcee826, 0x78e6fde1, 0x53ebf3b5, 0x025f9da7, 0xbef2d3e6,
3541 0xd4cd3e7e, 0xecf7a153, 0x61b1f7f5, 0x738a07bb, 0xa99f686d, 0xc1db99fb,
3542 0x6411786e, 0xffb69fdf, 0x9cd7d696, 0x06eda279, 0x79e6cf3a, 0x0379e199,
3543 0x5963dbed, 0xa3e3de80, 0x34162873, 0x661ef4c8, 0x1c9b0c0c, 0x9d1afe76,
3544 0xe9f28f4c, 0x911258a9, 0xf8b69e0b, 0x82fda04a, 0xe106275d, 0x7bf692fe,
3545 0xfbcb3e78, 0x31f14484, 0x841d6de6, 0x60584bdf, 0xa89dfc8c, 0xbcb8b2d7,
3546 0x9a3bbd3b, 0xdb49ebd6, 0xbf52669a, 0x3098b7f5, 0xdbd6a69f, 0xa849fc2f,
3547 0x3d3df7c7, 0x5e77d12e, 0x71e17c70, 0x27bbf54d, 0xfae71fa7, 0x89a3416f,
3548 0xb059efce, 0x9e3b676d, 0x0de0bd57, 0xe65b9d0b, 0xf48e76d9, 0x3b53d16a,
3549 0x469ece08, 0xd5a8bd99, 0x8273da57, 0x5db8f1b7, 0xe9154375, 0xff932841,
3550 0xf91f5d55, 0x9dcbecbc, 0xa9f0bb67, 0x00bcbb3d, 0xfccf85c2, 0x1ee30e2e,
3551 0xc6b7051f, 0xedbedf91, 0xeee9cf8b, 0xfd702e72, 0x173c2fea, 0x03fc23f8,
3552 0x2cc5cbe4, 0xdbcab9dd, 0xa9f7c512, 0xf7c2c302, 0xe8e087f9, 0xf1de78e5,
3553 0x6e7823e9, 0x3fa7e9fd, 0x5bc7047e, 0x8f0baff9, 0xadf498fc, 0xc3728ecd,
3554 0x3a61c4f3, 0x976d5bf7, 0x40e5cd90, 0xa3bfe3fb, 0xdfdbd2f3, 0xb7b038b4,
3555 0x641f3df6, 0xefb77d23, 0xe3052cfc, 0x8cf78b5c, 0xe2f078a3, 0xf0be8b67,
3556 0xb7486b7b, 0xe3e17ebe, 0x3e7375f2, 0xcd5f16b1, 0x38d9cd0d, 0x6f8033ce,
3557 0x9e75f38c, 0xc55f5cf3, 0xc456cdcf, 0x23dbcef9, 0xe5df8b9f, 0xc986e73c,
3558 0xed0f7e37, 0x2e7e069e, 0x75cf65cc, 0xbc78043e, 0x6fe04bfa, 0xbe716afb,
3559 0x9dfc6449, 0x4f003fc1, 0xb9ed6c8e, 0xcc369fce, 0xf8d7f47d, 0xdbb121ac,
3560 0x5f039d73, 0xb9ea6e02, 0x72ccfffb, 0x3e46ce8e, 0x74f7fa7c, 0xade2368e,
3561 0x3a73c144, 0x7f46cd3e, 0x075343ee, 0xb1d72b9d, 0xefc762c7, 0x73d82d37,
3562 0xfda7f894, 0x64b71e59, 0x76fbfce2, 0xe7e3f9d6, 0x8a988b95, 0x3f2c4b67,
3563 0x1fc05a0f, 0xe2568bcf, 0x1738bee8, 0x7ab1d39a, 0xe777745e, 0xeeca2f44,
3564 0xf89cf5cd, 0x96d5401e, 0x9fb99abf, 0x3497c21a, 0x7fe9f682, 0x2adbf9e1,
3565 0xbfc2ec1c, 0x96dbc4eb, 0x7771e7c8, 0xf02f8f9e, 0x73c3f885, 0x35cf3a3c,
3566 0x5435f287, 0x08b28e96, 0x137da0f2, 0xbdbd2f3f, 0xeea9fd1b, 0xd6caaa0f,
3567 0x6798a9f1, 0xf2a1fc77, 0xffc6e5e9, 0x3333e155, 0x8bd0d15b, 0x97d3a70a,
3568 0x75f1cb22, 0xb6bfef82, 0x62ece3fd, 0xf48fdcff, 0x66d0d558, 0x44d9fbe6,
3569 0xf7cc547e, 0xf4dfd834, 0x6427a4fd, 0xd557e3b2, 0xd71c9337, 0x6eea8bcb,
3570 0xb39b6df2, 0x7153bac5, 0xa7e9c14e, 0xefb87d63, 0xdddef4ea, 0xf6effd7c,
3571 0xfa17b336, 0x19edbfdb, 0x721b8f33, 0xe13d41fe, 0xe9ff1b0b, 0x91069b27,
3572 0xdd66eedc, 0x8f78bd77, 0x3df91fc7, 0x34e7ed9e, 0xade859ef, 0x72efff27,
3573 0xe8c8fbef, 0xfbfb05bc, 0x3bf7c828, 0x4ffb847e, 0x17ffbc23, 0x176126d9,
3574 0x22eb13ae, 0x3f03de41, 0x9ee02bbf, 0x3cf5cbd6, 0x9d1999c2, 0xe3be1083,
3575 0x2725917e, 0xaf979f01, 0x7fa8ec95, 0x4c18af67, 0x9ccf9274, 0x89652744,
3576 0xfa937bfc, 0xe6cf1cf7, 0x1ab6fc7a, 0xc3fa4313, 0x280cded3, 0xb624eb7f,
3577 0x3197fb86, 0xe7425313, 0x6ead56d1, 0x0abc2389, 0xef3d533f, 0x3e66a2b6,
3578 0x39fd07c9, 0xdeac9538, 0x2d6fe78c, 0x2dcfcb58, 0xa38b9fd4, 0xcf5dab97,
3579 0x85fb5a89, 0x956df672, 0x81cc1cef, 0x07e7377c, 0xd7e456b1, 0x4a68f0ae,
3580 0xb3ca05be, 0x07a4c80f, 0x2eb0b854, 0xebcbfddf, 0x7f3cf881, 0x973f2fa0,
3581 0xb152515c, 0x3c1e9cde, 0xdd19282e, 0x597ef1c3, 0x19b87ba2, 0xb19beae5,
3582 0xb596c7b8, 0x7c50345d, 0x36595980, 0x59d9938e, 0x537db876, 0x60a7b26e,
3583 0x16cbc4de, 0x58fc51a5, 0xeb0addff, 0x1eff20da, 0x157bf683, 0x5f9c8965,
3584 0xeff3763a, 0x1e46b1ef, 0xeb32b6bf, 0x9c778c32, 0xe0a5d652, 0x95ae5411,
3585 0xc53dfe26, 0x4714f1ed, 0x91456db8, 0xba5fcf19, 0xf69e21ad, 0x93af30b5,
3586 0xe2a8cfbe, 0xc1456db1, 0xf7e834fe, 0x871cfab6, 0x269fc5ac, 0xaea0bc1e,
3587 0xc9dbc54d, 0x64ede0cb, 0xbe01bc24, 0x7a13f734, 0xeec5f169, 0xe94cf6e6,
3588 0x62fafb1d, 0x0d7ceefe, 0x77631eff, 0x340e92f2, 0x35c5094a, 0xe33a338b,
3589 0xef4829b5, 0x250ed617, 0x55f1e9bc, 0xc3d9affc, 0x7b337f71, 0x05ce962b,
3590 0x66c3eb2e, 0x6ff184dd, 0xd953f389, 0xa316262f, 0x8bd01ade, 0xb56bfdf3,
3591 0x82d9fe3c, 0x787ecff1, 0xca9dba6e, 0xf3fc4587, 0xe13fc628, 0x3fc626fa,
3592 0x7c527ae1, 0x33e5433f, 0xd7a20020, 0x7f38bdc1, 0x8925ee0d, 0x34e2ddf8,
3593 0xff8a4bb4, 0x73f38b25, 0x61637d7e, 0xce878d0c, 0xa3fef9cb, 0x7bd1bebf,
3594 0x3a37630d, 0x69b4f1b5, 0xb4f1b453, 0x663915f2, 0x736fd7f4, 0xa3d4d68d,
3595 0x0f5abc88, 0x925e98ba, 0x337e79a8, 0xbfcc34be, 0xf0a5ee2f, 0x1f7147f8,
3596 0x4b5bbd4d, 0x2a5bdfb5, 0xb3c668bf, 0x62dbd985, 0x26b3309f, 0x87bfc219,
3597 0xf1ca4402, 0x3e6de762, 0x416e3a31, 0x60e4fc7a, 0x5e7284b2, 0xaf150f8f,
3598 0x080037b3, 0x1b39dfa0, 0xbd97940c, 0x55e3b66b, 0xaeeccf3c, 0x7bf7f8a7,
3599 0x467bae4e, 0x39805df3, 0xbf84994f, 0xa1fb2763, 0xf232c568, 0x607dca3b,
3600 0xcb88022f, 0xa23ef45f, 0x467e3196, 0x0f91594b, 0x80bec90e, 0xe2727844,
3601 0x4fbd83f7, 0x7e47eff0, 0x0ed86208, 0x2b7677fa, 0x1287c71f, 0x53e5815b,
3602 0xfdfbb7b6, 0x6675e600, 0x0679bae2, 0x307c8dc4, 0xd3e2e499, 0x2cfa4332,
3603 0xe744c3bd, 0x587ede39, 0x31f4efa6, 0xc5533f29, 0xd9cbe62b, 0x1dfe1613,
3604 0x04a00e9b, 0x71f8b7a8, 0x8f9f7d0b, 0xcfcb0328, 0x11adf40e, 0xf2f48874,
3605 0xc6733c61, 0xfe7960d3, 0x6496a3e0, 0x82119f5a, 0xce106f9b, 0xfae09bd7,
3606 0xa3a02f51, 0x06f9e68f, 0x3bbafc91, 0x0f47f899, 0x2e6693df, 0xef48bc9f,
3607 0xea2e4852, 0x26d996ed, 0xc7df7d07, 0xa3a486cb, 0x96b93a5c, 0xf40f477f,
3608 0x3f5f1c4a, 0xabd134f3, 0x46939efa, 0xef8e3c65, 0xe90e5d64, 0x0ad6dbaf,
3609 0x06f4137f, 0xfae3efaf, 0x46ecbd6a, 0x275bc3bb, 0xaf9db9b9, 0x4db78fa5,
3610 0x688b9ede, 0xd68db1fd, 0x6809dcaf, 0x9dca3cc5, 0x2ec9533b, 0x5bec2998,
3611 0x2ddbc696, 0x3b3a73b6, 0x0f4fa07f, 0xea7ad7dc, 0xea01e010, 0x75f3a7b4,
3612 0xacc6a705, 0x3747861b, 0x1dec369d, 0xffb803f6, 0xfbef44f1, 0xc8dbc046,
3613 0x5ee6f76c, 0xac329f18, 0x4473c6cd, 0xfc4fface, 0xf50fbf1c, 0x83930ed1,
3614 0x97e974d8, 0x0c4ed3b3, 0xeb835d8d, 0xf2eb67c2, 0x3f042704, 0x5bf8293c,
3615 0x8b6fcfd5, 0xa7036cf2, 0x2482f63f, 0x34c46bbe, 0x9e217872, 0xe4872a43,
3616 0x2b872aa5, 0xc7fadd85, 0x3e6edc5e, 0x60a5d6c5, 0x4fa005bd, 0x3b3cfef1,
3617 0xb72a4bb7, 0x7ee7eff1, 0x4c9c7c84, 0xf5c31a7d, 0xe4167cf2, 0xea014e7a,
3618 0x77dd0949, 0xc0388b45, 0x409fbe3a, 0xb9e7f72f, 0xe06ffb7d, 0xa3003bfd,
3619 0x7cffe45d, 0x8f1b1ae6, 0x3c6deb71, 0xff97ac9e, 0xb9b7e84c, 0x3d7a7de2,
3620 0xbbe85730, 0x377d3ab9, 0xce8e71cf, 0x0edca91d, 0xb2b945ef, 0xc2efab4e,
3621 0x9a44a9e6, 0x872f3ce7, 0x873f3cf7, 0x769d7bcb, 0x08fda30d, 0x3d59dc2a,
3622 0x77b4d3fc, 0x791c61c5, 0xc33283fe, 0x78aa1cef, 0x823e66a8, 0xb02cc7f7,
3623 0x8f18ed0a, 0x062e31bc, 0xa1f0ba70, 0x2dc7ecbf, 0xa06b944a, 0x7efef3f3,
3624 0x9427b3bf, 0xa4b2f37b, 0x6f7efdfc, 0xd570aecf, 0x829bf1c3, 0x6ef9131b,
3625 0x9863076a, 0x377f85bb, 0xc91eac3a, 0x0901fffb, 0x00d0a8f5, 0x0000d0a8,
3626 0x00088b1f, 0x00000000, 0x3bedff00, 0xe5557469, 0x73dcfbb5, 0xe1dc8487,
3627 0xc2040464, 0xc06e49b9, 0x612f4865, 0x1213d41e, 0xde0d4b22, 0x00c10580,
3628 0x86120137, 0x7c07504c, 0x0040e3e2, 0xaa1a4583, 0xf50af8a5, 0x22d28342,
3629 0xb04a0834, 0xc141170c, 0xd6de8ba7, 0xa44f7d6a, 0x40932861, 0xd2bb6a52,
3630 0xf7b79457, 0x3b939df7, 0xed83a404, 0x58b593af, 0x9ef37efb, 0x77f7bdbf,
3631 0x52015000, 0xaaa8e601, 0xd08eceb5, 0x092bd00c, 0x72c06e60, 0xd80e35b6,
3632 0x37fc0ddf, 0xbb746b7f, 0x01e5e696, 0xf7473754, 0xa41c5fe3, 0xbfe6cc01,
3633 0xff5616a1, 0xd845cc41, 0x766f3d12, 0xe890eadc, 0x556679a4, 0x086e17eb,
3634 0xa1e6ca0c, 0x840cfada, 0x9f12a24d, 0x6e0f351b, 0xca7a01b8, 0x7773948e,
3635 0xde0bc361, 0xc5c2221b, 0x002300c9, 0x5c78174a, 0x439c1cfe, 0x2186f77f,
3636 0xb09e7468, 0x39cd23c0, 0x098a6584, 0x68c79cf0, 0xb1c6994f, 0x477f788d,
3637 0x617c67e2, 0xc1864ef6, 0x15483f08, 0x3a6f3c54, 0xeba236e1, 0x71eb15be,
3638 0xdf8841e7, 0x11f8137a, 0xcbbf5b9e, 0xfe3e47e9, 0x695dc5fe, 0x88772b04,
3639 0x66084410, 0xdcf015bf, 0x2f65f582, 0x56fb833f, 0xdaf78d6c, 0x88e2bbb0,
3640 0x3c7008bf, 0x252b7c0f, 0xe3d7971c, 0xe070c341, 0x71dd8445, 0x8428f23d,
3641 0xdfd982fd, 0x513de68f, 0xd927efe1, 0xd187faa3, 0xf4cc4fbe, 0xee3f7cff,
3642 0x04b6c4fb, 0x9248caaf, 0x44e1a682, 0x84041489, 0x7b7f0bd5, 0x04fc8cd2,
3643 0x9e8f83f1, 0xf2b8014a, 0xb6c408ba, 0x817f24ec, 0xcfdc4a9c, 0x703d05eb,
3644 0x5d29b89e, 0x22f6c4ca, 0xeff9ecec, 0x8d4ce7e7, 0x4fc4e59f, 0xd599e914,
3645 0xf3a50e1f, 0xbe70374f, 0x4d99face, 0xf397a7e3, 0xe7e73573, 0x339f8d4c,
3646 0x7e35788f, 0x4f892bca, 0x9f8d6af2, 0xeace1c0d, 0x3a7537c2, 0x4fc4f5e1,
3647 0xa7155e6c, 0xa60f885c, 0x173f909a, 0x4f508a76, 0x12a80b6d, 0x4485c3da,
3648 0xdf511250, 0x3f8d04ff, 0x7e610a0e, 0xe50ecdce, 0xd29e9106, 0xc49d47b5,
3649 0x453bb9d7, 0x3f2c704e, 0x73eee941, 0xc81f9e44, 0x24d53c25, 0x087942df,
3650 0x408aa5c0, 0xb7fbe12e, 0x825a7df2, 0x79e3e522, 0xde2dfbed, 0x36efc8cd,
3651 0x85c01587, 0x8384f676, 0x227265c1, 0x3a81679b, 0x505f3c00, 0xf8845814,
3652 0xdd3e50db, 0xb2159e90, 0x5905c6cc, 0x87ec5282, 0x7e13200d, 0x24288282,
3653 0x1d2fed75, 0x3e462283, 0x814c3bb5, 0x67ff48cd, 0x3c80d0d6, 0xffaf187b,
3654 0xe913b192, 0x03c835f8, 0xd252bce8, 0xccafc235, 0xfc8cd815, 0x6c4c0879,
3655 0x0cc087df, 0x982708a5, 0xd8713541, 0xba224f60, 0x3fa85990, 0xf1bf35e3,
3656 0x7410e1ed, 0xef82af21, 0x3fae7081, 0x73a55d30, 0xc14d0726, 0x1e0fe87e,
3657 0x090f0732, 0xb2714d08, 0x7c73c245, 0x913c84e3, 0x660cb0e4, 0xf15decf8,
3658 0x21f846db, 0x1326a5bd, 0x8129ebc7, 0x0a28f1d1, 0xdd32f89d, 0x8444470c,
3659 0x4439e28f, 0x5904b4f7, 0x0816f365, 0xa30ccdde, 0x54df8614, 0x2881bf0d,
3660 0x4bc87387, 0x0df76ddc, 0x3547d3d4, 0x069f707c, 0xf1cf5b27, 0x1edf9588,
3661 0xad004f8d, 0xcd6be256, 0x227fef63, 0x71359d20, 0x49f920f6, 0x6e5cb168,
3662 0x39f9afed, 0x48afe1e4, 0xc05f384e, 0xf4f90083, 0x04db06a8, 0xb87b3bb4,
3663 0x1e0d21ff, 0xa5ace8d7, 0xde0bca36, 0xdc5b0212, 0x03e73fb7, 0xd3ad8939,
3664 0x3b0347f7, 0x1026e34d, 0xed6bfc80, 0xb2562dfe, 0xbf5a79bf, 0xb22187ee,
3665 0x5dacde2d, 0x169f912a, 0x41ba6fc0, 0x8b3edad0, 0x13dc2958, 0x7afb25ef,
3666 0xa1ecdad4, 0x5e76277b, 0x5874df2c, 0xef53805c, 0x3e75f9a0, 0x03c03465,
3667 0x0bdbd3df, 0xcbda0a7c, 0xe39de1a4, 0x8e164a8d, 0x8e7f177f, 0x7828e864,
3668 0x452fc133, 0xd7253ede, 0xfce39685, 0x8a728f0a, 0xdcd39ffc, 0xa0fecc0a,
3669 0x58bbf191, 0x28061324, 0x28a37d1c, 0xb858f911, 0x6c9e605b, 0xe636e8ea,
3670 0x50f13a77, 0xd478619f, 0x76f413ec, 0x71bbc148, 0x36ceeeea, 0xb070a3c3,
3671 0xf27c6a2b, 0x9f1a8868, 0x1be91d78, 0x6a71b5a9, 0xd194f488, 0x4a8d9ff1,
3672 0x235b6c6f, 0x42dae3e6, 0x4ba74f3a, 0x65ffef0e, 0x835f19e0, 0x9d75d199,
3673 0xcc5075f9, 0xba6101be, 0x91df665c, 0x5dff223f, 0xe2a48229, 0xfc5f1aba,
3674 0x6117f26a, 0x3d181a7a, 0x8f9d78a1, 0xf1a37cd1, 0x06bfa442, 0x8d55f1f4,
3675 0x67cdf20a, 0xd2af9cea, 0x3f3ab1fc, 0x337f7d70, 0x7d6c4973, 0x4686a6d2,
3676 0x9fa61ed5, 0xbe18b3b5, 0x7c21ee49, 0x295fd339, 0xc42f48ff, 0x4ef906b3,
3677 0x5ca74557, 0x5f8c75d5, 0x6d1131a1, 0xa62337c2, 0xff022ddd, 0x52fc11de,
3678 0x59f949d7, 0x7cd2f811, 0x8b4a67c4, 0x127fbd10, 0xb4ddcf1f, 0x1d1d51ae,
3679 0x90fc036e, 0x5e8227f1, 0x9d299fc6, 0x9be75ef2, 0x6ac7eb85, 0xfee019fc,
3680 0x45e88fa1, 0x7d3972fa, 0xd2fd2881, 0x65bcaef5, 0x14b48aed, 0x2004b38a,
3681 0x68f2c37a, 0xe7fc91f2, 0x9bff3a4b, 0x586f8442, 0xa13dbc1e, 0xa9bf3f59,
3682 0x64abf491, 0x6f2f4eb7, 0xf70bf587, 0xbff216fb, 0xea7c7a21, 0x53f5e8f2,
3683 0x667f73a0, 0xf53a5357, 0xfa43cf17, 0xbcfc69e6, 0x4853537f, 0xbf76fae5,
3684 0x67ac353b, 0xad12b365, 0xed85bf74, 0x6be31b71, 0x93b8de27, 0xbc0fe380,
3685 0x07c7cd1f, 0xb27b79ea, 0xc1af9b7b, 0x4d7ed91e, 0x7764e3e7, 0x7d72bd94,
3686 0xc4fd1df9, 0x4024f37b, 0x161fbd94, 0x4487dba3, 0x437baf9d, 0xa750e58f,
3687 0x1f5efe7e, 0xfc0fb7dd, 0x719f1a30, 0xc7bdbd36, 0x6fe91857, 0x5f1937d4,
3688 0xf9f4fc74, 0xd7a25f45, 0xddaaf3c3, 0x729afa6f, 0x320cdee8, 0xc49a56ff,
3689 0x71c75c21, 0xb56a47bc, 0xbf68a938, 0xbcd00be8, 0xc2cf416e, 0x873d309c,
3690 0xff99169e, 0x8085eb56, 0x196cfd07, 0x04ba56c8, 0xa5628267, 0xcb90f5fb,
3691 0x9c15e8b5, 0x7169f87f, 0x3df70051, 0xc59928b9, 0xadb81f9b, 0x5d87ff8c,
3692 0x6366d37d, 0x0cc250fb, 0x0ef38cab, 0xc1963b3d, 0x7fe93bb7, 0x337a47d7,
3693 0xc9a5ce2b, 0x97e65df9, 0xf6f0250e, 0xbedbf72a, 0xd5af28a5, 0xe7ed996e,
3694 0x5ad2924f, 0x39e13f50, 0x09916c0b, 0x098fef4f, 0x6de7b2bf, 0xfc239f03,
3695 0x4695de96, 0x41ff2ef2, 0x9c4f5149, 0xe2c2be57, 0xab5e7015, 0x7c274a49,
3696 0x658dcffd, 0xb96b30fa, 0x18fbd506, 0x4fd5f83c, 0xcf749dea, 0x1c58146e,
3697 0xcd17f773, 0xbb62e7ef, 0x4bd321b2, 0x30e81ea8, 0x9ce78481, 0x202fdf5e,
3698 0x899dcaa2, 0x3c777baf, 0xbf340f9f, 0x7c7cbaf2, 0x2f9a60fc, 0xfe70cb4a,
3699 0x7017ec39, 0x712adcfc, 0x397840b3, 0x2404dd1d, 0xc097dce9, 0x2b73f0ae,
3700 0xb865816c, 0x7fbb69cf, 0x673a7afa, 0xd29605bd, 0x93d7413a, 0x4e5f198f,
3701 0x3f5cba4b, 0xa1cfcc6e, 0x2dbd3679, 0xca9f2195, 0x157a9d4c, 0x2aefbc04,
3702 0xb5fb7912, 0xb6f91f4d, 0x2f73fae0, 0xaaf163f5, 0x276ca19c, 0xa19d3d7d,
3703 0x3ffb20ec, 0x462ed5f8, 0x3c4bfb5f, 0x51d03b6e, 0x111e569e, 0x315c5427,
3704 0x68387d33, 0x7c231f95, 0x23eb760f, 0x6a2f2ca8, 0xf8a12e4e, 0xe28cf511,
3705 0x45ebd46d, 0x1f126ebb, 0x2645ba36, 0x4ddf43af, 0xea472d1d, 0xf9867ab7,
3706 0xde64e289, 0x6d6eea3e, 0x9cafd154, 0x33822db5, 0xfaf5e159, 0xe8aef9fe,
3707 0x39983938, 0x81d128e1, 0xca30c679, 0xeb7cf453, 0x0733f533, 0xf533f1c9,
3708 0xe3630653, 0x43a74ad4, 0xde7fe725, 0x1c9330e1, 0x9c979a4e, 0x62b938a3,
3709 0xb9f985a3, 0x8ba98d8a, 0x414e29db, 0x5740f17d, 0x2c32927a, 0xda5b9e8c,
3710 0x2beedaa5, 0x07191dec, 0x5dad7fb4, 0xf36a6eb6, 0x6d6fd935, 0x5b129597,
3711 0x2d1b4503, 0xcaabb23e, 0xa0330e21, 0xf1b31cbf, 0xefa42d9d, 0xf3e20b95,
3712 0xe578886c, 0x53931b46, 0x4aa1c3ab, 0x3a77ee38, 0xaf0889cc, 0x6e8c4dba,
3713 0x60cc8657, 0xb8e60881, 0x5397063c, 0xf10d711e, 0xc5f6c649, 0xa3ac2f45,
3714 0x0412e4b4, 0x3d430d26, 0xfd70a6bd, 0x0c5bb6bc, 0x66047e50, 0xf98c5cc5,
3715 0x7ee01cd3, 0x5dbdfaa2, 0x39fc7cd6, 0x41f2aea7, 0xf9f965c8, 0xfcfc98e9,
3716 0x8e1e7474, 0xfe51a61b, 0x30aaffcd, 0xc43b24de, 0x5e6a3d7c, 0xd51e7e44,
3717 0xf2d0c96f, 0xa3c83ceb, 0x9d5aee38, 0xdd829b25, 0x13da3b4a, 0x41b059d2,
3718 0x2e56f860, 0xc4360312, 0xe79920b7, 0xa0976747, 0x5e8caddc, 0x2576c255,
3719 0x37c4b1e5, 0xf8710210, 0x0b0dbef3, 0x1767e4cc, 0x4ca57e6b, 0xdbe91f00,
3720 0xfa6f7899, 0x36c78a02, 0x56be33c6, 0xc7ee78fe, 0xd6bae12f, 0xa229c5a5,
3721 0x5e87d61c, 0xfee03e9a, 0xde149710, 0x67d2fce7, 0x0bdf49d2, 0x4857ee5e,
3722 0x22657871, 0x26e298ec, 0x974cf539, 0x9579e1ed, 0xe6ce9ecb, 0x8083e2f3,
3723 0x2ad970f1, 0x6f01d191, 0x521e02d8, 0x4520fec8, 0xf2d66df2, 0x1cd6acf7,
3724 0xd34a5bfe, 0xfc991ee2, 0x9c5faf37, 0xced171c6, 0xc676a7f8, 0x066ff8bd,
3725 0xf993d5ed, 0x57d13f09, 0x4c66126a, 0x5bb4fb60, 0x328b8ec9, 0xb7701e78,
3726 0xbdd2cb06, 0xea8f09d3, 0x32ef3635, 0x1c47df37, 0xb181e1aa, 0x5429b54d,
3727 0xf3c223f1, 0x0b779b4d, 0xbc796dc9, 0xb924ef12, 0x0e7af282, 0xad98c7ab,
3728 0xa72fb449, 0x76e64ab3, 0x989ffd8c, 0xc1dabfb1, 0x227560fd, 0x15cedbf2,
3729 0xb7fb84c4, 0xbe4cafd1, 0xf0dccf5f, 0x85f3cefa, 0xb99df8f0, 0x49e4afc4,
3730 0xdb1e108f, 0xc8af6645, 0x29c3358c, 0x0e2ed96e, 0xf1a64e7a, 0x57e445c3,
3731 0xc81cefe7, 0x1db2b6e2, 0x617bb21f, 0x56e726be, 0xc7296f2d, 0x33844ef6,
3732 0xf8bdb832, 0x666ba845, 0xe8bf9e6d, 0xabc7d6f2, 0x9c985957, 0x937fd1aa,
3733 0xfa5ea8e3, 0xb56fb65b, 0x79469423, 0x961bf556, 0xcb6fe4a1, 0x97cbfc35,
3734 0x09fd19f6, 0xc5b94fea, 0x543dd125, 0xa95b16a5, 0xb028d55d, 0x6a5d7876,
3735 0xe7e3e93a, 0x4938f7cb, 0x07c4ce4f, 0xb4df743d, 0x52f7882f, 0xc0da887e,
3736 0x97cf93ee, 0x873f367b, 0xc85259ed, 0xacf8e021, 0xc89332c7, 0x82949f2f,
3737 0xd93f1a56, 0x5b5136ec, 0xd4d1a491, 0x62dfcc56, 0x55d1cfed, 0x43fa6b35,
3738 0xe046a5fe, 0xed7aacf2, 0xcf0335b0, 0xffc9a95b, 0xb30ff6ca, 0xa756cfc9,
3739 0x397db287, 0x14d9de4c, 0x04cfc2ff, 0xbcd6df76, 0xba60ebc6, 0xde486bbc,
3740 0x34f35f68, 0xdeecd739, 0x7de924f3, 0xaf3bc90d, 0xdea0beab, 0xaffd611e,
3741 0xbe022a6f, 0xc5e908fe, 0x53cc7899, 0x05b97b79, 0xbcacc7db, 0xbfe6acfd,
3742 0xf790bfb0, 0x4f3c39ab, 0xac6b79e3, 0xbe4adfbe, 0x263f244d, 0xa7f31b0f,
3743 0xadbd1a4d, 0x9270deab, 0x3f6caefc, 0xc1c8eefc, 0x57e61784, 0x5ef44df2,
3744 0xd12d47e3, 0xb3f864ef, 0xe896a1b8, 0xefe98675, 0xdecd73d4, 0xa7d3816a,
3745 0xd66b5bd3, 0xb5c7d7e8, 0x3a345bf5, 0xd7e340ab, 0xbedc7eee, 0x7b227b34,
3746 0xa749fca5, 0xd7c49fcf, 0xbef9faeb, 0x4d6edf46, 0x766a414f, 0xbe487f12,
3747 0x7f5067e4, 0xcd50eb14, 0x2b94e06f, 0xfcb1373b, 0x8e979751, 0xfbe1a7ff,
3748 0x0a4c4942, 0x04d5b1cb, 0x5ded9a73, 0x1a23c5ef, 0xe8ad4f1f, 0xfc82de9e,
3749 0x06f31cfb, 0xbea36e96, 0xd3ce239a, 0xaf3f46f5, 0xfdc95b60, 0x86600eac,
3750 0x9fafed20, 0x304d527b, 0x81273ed3, 0xbf8e87db, 0xf505976e, 0xe81feed3,
3751 0x1c5779a4, 0x37443999, 0x0cd3ff3f, 0x5457ad89, 0x4af3f307, 0x7010108b,
3752 0xebc094e8, 0xec56a782, 0x84e79671, 0x327ffdf5, 0x62ff4e84, 0xa78aeb4e,
3753 0xfa117fae, 0x782cf0cc, 0xd4fdf276, 0x7a16f4fe, 0xd74df3a9, 0xca9c584f,
3754 0x3d5893e2, 0xca7dedad, 0xf6c5e74a, 0x19caf1eb, 0xfec97bca, 0x10faf2f7,
3755 0x5923872c, 0xeeb0f711, 0x0ecff1d7, 0x84f7c343, 0x65e72f7e, 0x2efa3066,
3756 0x1f35b341, 0x85d578fd, 0xa6539150, 0xf5644fb8, 0x08bfbba0, 0xb3d42e8a,
3757 0xbceeddaa, 0xeaad7bc8, 0xa7a611f2, 0x756210d5, 0x1f55b2cb, 0x7d230f16,
3758 0x45c629fc, 0x8c5757e4, 0x3d5c52b5, 0xa1cccb77, 0x0dd3e724, 0xb8badefc,
3759 0x142bc87c, 0x786e9f17, 0x0e666d21, 0x1a282bad, 0x6b65fd89, 0x9e393207,
3760 0x53150f89, 0x1171fdbb, 0x6a358ea8, 0x53c590cb, 0xd1ca3db1, 0x39e89137,
3761 0x8e1624d9, 0x2cfb908c, 0xa54f1690, 0x92eccc78, 0x6a4e0ec8, 0xc2deabfe,
3762 0x933bd2e5, 0x277279eb, 0xa0bafee4, 0x44db3ebe, 0x7e84db7c, 0xc5aee913,
3763 0xd507a018, 0xff1e054d, 0x5c42b1cc, 0x1fd63ccf, 0x4dfb13d7, 0x09aa2709,
3764 0x13c7b6ff, 0x4ddbaa24, 0x883781b3, 0xfb0769ed, 0xa6e851e4, 0xc6287168,
3765 0x9d5cecab, 0xbdf9fa4f, 0xc51eb932, 0xf5e20bee, 0xc76fa4a1, 0x19d63ab4,
3766 0xcb8bef0d, 0xee893a7f, 0x3d5b8ba5, 0xf9f74449, 0x140df1fd, 0x70b79cc7,
3767 0x7fefa57f, 0xd88f77bb, 0x77d88ef7, 0x0c65800d, 0x189901af, 0x6740253f,
3768 0xe3eba4fc, 0x70baeaed, 0xcdd78d22, 0xfaf53db5, 0x5ecd1ffa, 0xd64de257,
3769 0x12f2f0e9, 0xce365864, 0x9e083aa3, 0xe5f0985f, 0xd9c510ae, 0x86c9368d,
3770 0xbd259ef4, 0x86fab6c6, 0x1481eac8, 0x9f9e9313, 0x8050637d, 0x138ab7f2,
3771 0x2cd15dbc, 0x7884a804, 0x22b3ed64, 0x718d9fcd, 0x2221775e, 0xed717d6e,
3772 0x6bff5224, 0x9ecaff5e, 0x56daff38, 0xe037bd81, 0x5e263db0, 0xfca7b77d,
3773 0xf5578bef, 0xe754bffc, 0xa42ef6bb, 0x57cf5bf3, 0x0c5ea20e, 0xedf30bcf,
3774 0x2c3992ea, 0xc4bcbd5e, 0x709b60cf, 0x5628cd6a, 0xbab176e7, 0x5e5a2fef,
3775 0xdc917b10, 0x4ebc0f77, 0xbb48e779, 0xbdbb224b, 0x401164ba, 0x63abad36,
3776 0x5ebb9750, 0xf77bb9df, 0x6aeeb621, 0xa37da0cb, 0xbb01dd70, 0xcee7f98b,
3777 0xf79892f7, 0xbc58ef91, 0x7dd913dd, 0x7451dfc1, 0xd772ebf9, 0xded4abe9,
3778 0x2ffc7445, 0xdee5c53d, 0xd33aded9, 0xfa1ef449, 0x11bef251, 0x9704ef24,
3779 0xb9da7144, 0x5c5fdcf5, 0xf2bd7388, 0xc2fbca20, 0x80698986, 0xa1f6727e,
3780 0x7f512787, 0xa2417ec5, 0xbfbbdcf8, 0xd3f949c4, 0x4eadcdef, 0xbf7ef3ca,
3781 0x0abf7f5e, 0x469fe488, 0x3489838e, 0x0cd0647f, 0xe233ee32, 0x2337ae41,
3782 0x0a039b2e, 0xcfd83bc5, 0xbbd716ea, 0xfe05bab1, 0xfde09725, 0xaf2f7b39,
3783 0xd072e873, 0x1a51adf3, 0x9333079d, 0xfeb4ff38, 0xffbce182, 0xe35d86fc,
3784 0x4d8bbf69, 0xbef08916, 0xfb6164da, 0xc93cc3cf, 0x5b33ef44, 0xed421e79,
3785 0x37d93778, 0x35e637cf, 0x7aa37cf3, 0xbab14581, 0x4167eaba, 0xe7ca3cc4,
3786 0x73a64fb0, 0xa7fa6ae7, 0x853cedeb, 0xef0f37d3, 0x5637a235, 0x99a1138f,
3787 0x4edddbbd, 0x3d56ff9f, 0x37e31dde, 0xa982584e, 0xef9f8993, 0x77565e89,
3788 0xe87e85b9, 0x403f257c, 0xc3ebac7a, 0x0517d43c, 0x079a9287, 0xea3e93e6,
3789 0x9bfba1fa, 0xa5e35bf9, 0x2dfe51b3, 0xdb5daa31, 0x1b3a53d2, 0x7a69e719,
3790 0x99823908, 0xe9d2abe8, 0x535d6b8b, 0xf8a6b082, 0xc421150f, 0xafe88473,
3791 0x9152a4f0, 0xc05e8bef, 0xc69ed964, 0x642091de, 0x061ef601, 0x6a17ff4c,
3792 0xa2b1b075, 0xe519bfbd, 0xf3742a58, 0x96d93e52, 0x2e4d50ef, 0xf9327796,
3793 0x04253e96, 0xc44ffb00, 0x9ea9733b, 0x0e420330, 0xbb3fb637, 0x464d7643,
3794 0xf5ebd5f9, 0x2d63b56a, 0xe65767d5, 0xfffb5a8b, 0x3aa8944a, 0x8afdffc8,
3795 0x530f20ea, 0xffb5943d, 0xf6f5425a, 0x71b477b6, 0xe3425eb8, 0xab402b6d,
3796 0xdbc57d8b, 0x85c7d03f, 0xdb5fb409, 0xe45c7d2a, 0xfdf5e7ed, 0x98daf6b5,
3797 0xe331a5f1, 0x1ff6f12f, 0x504e227e, 0x88f5c273, 0x9ef7b527, 0x7d5a65d2,
3798 0x8336f4c2, 0x93df2cf6, 0x1d17cf54, 0xe7941d67, 0x27947914, 0x7bf0dde9,
3799 0xcd7ffd7d, 0x44af3844, 0x9f78ad50, 0xd9026fc1, 0xda75e7c4, 0xe1ffdd7c,
3800 0xc9bac83c, 0x6f3439bc, 0xcb3cd448, 0xda7de6cd, 0x376ebf75, 0x89e2979b,
3801 0xe77f4fde, 0x9c56e29d, 0x278f5f34, 0x94afef62, 0x8c471e2c, 0x699254ca,
3802 0xb40b239e, 0xe9bc42b8, 0x16615a3b, 0xbb4a038f, 0x99b677f1, 0x32711d43,
3803 0x37e431e2, 0xf9077afe, 0xbe3c0db3, 0x98efb57a, 0xf41fb43e, 0xc757be8e,
3804 0xcc43ef21, 0x3cb3b5af, 0x86fb8ff2, 0xd1bfc8b8, 0xebaf24db, 0xea9f7da5,
3805 0x759dc5ee, 0x67dfbea6, 0xacb74def, 0x409df543, 0x5f71a875, 0x66f3bd71,
3806 0xc93efcf5, 0x01b0da75, 0xb48fc8dd, 0x25effba4, 0xbb0da63c, 0xf9da88bb,
3807 0xaef662b6, 0xefafa3dd, 0x6b3fea1e, 0xa1089e52, 0x6346fb3e, 0x7f611b20,
3808 0xa2130a13, 0x983f0fda, 0x3d844a0c, 0x57b87a4e, 0xd291fb54, 0x53f9a8cc,
3809 0x3515dd67, 0x0d0b6c5e, 0xf69c7966, 0x78ab7cce, 0xc61df3a2, 0x9f3debc1,
3810 0xc7d3fbed, 0x6a1fa28f, 0x5d59126b, 0x2dfeee77, 0x70828f1f, 0xec46805c,
3811 0x74bdfb22, 0x93ca044c, 0x5757eb63, 0xb46eb420, 0x80f135f0, 0xe5c58474,
3812 0x8d1fa8ff, 0xc6a34bc8, 0xfb4567a7, 0x1f756bd3, 0x23180ba5, 0xac7568d5,
3813 0x594f7b2b, 0xbbff5e65, 0xeafd0371, 0xde90b47d, 0xfe903b3b, 0x2d7fa841,
3814 0x38adaca7, 0xe64b23de, 0x05ef4779, 0xe5007966, 0x4acc0b11, 0xa1171e84,
3815 0xbea8b81d, 0xde3f71d2, 0x83474878, 0x74d7d6c2, 0xb8bb5898, 0x5465b4d7,
3816 0xc336aa6f, 0xc754dd80, 0x6e2c1d90, 0x7df9fe2a, 0x67e580e3, 0x63f74282,
3817 0xe7c2a355, 0x4c1ebf8b, 0x1db1b0f5, 0xc53ed8e3, 0x50131c22, 0xe0281f37,
3818 0x31d5d17e, 0x76d7f581, 0x6e0f9b00, 0x54ace2ff, 0x7144aefe, 0x29aefe6f,
3819 0x72888985, 0x86795bb2, 0x2297ebf4, 0xfbbb222c, 0x86f7bde5, 0x5f7a1494,
3820 0x32283418, 0xc59358ff, 0x6a400ddf, 0x5df74ebf, 0x990481ed, 0xc5eac8e4,
3821 0xb7ed0f14, 0xec7c77b1, 0xda90f567, 0x94cdb603, 0xdb3ad5e7, 0x0afec9b3,
3822 0x8907c60e, 0xe307438e, 0xcdbf2ccd, 0x73a1aff4, 0x2bf60e0b, 0xd9537ca4,
3823 0xf3033367, 0x98f7ca63, 0xca589e3d, 0xd25d3ae4, 0xea37fb04, 0xbfbf6c63,
3824 0x4cabf381, 0x872ebbe3, 0x7eef8d72, 0x1a659f8d, 0xdf1067df, 0xc5f2ee91,
3825 0x587b6fc8, 0x29a2c52e, 0xb260fd7b, 0xca5e3e8f, 0x15bf743f, 0x8eaaf7cb,
3826 0xeaf7c638, 0x7c9a1e8e, 0xa1c945bb, 0xb58323bc, 0xdb7dba07, 0x7ae2ce89,
3827 0x5fee2f94, 0x287a0f6e, 0x17519a3f, 0x87f7a5ef, 0x45dd8b6b, 0xab85d7c4,
3828 0xfee6e1b0, 0x8ab5ee8b, 0x74add4df, 0x4a65c844, 0xb8c82e47, 0x2c8ec4df,
3829 0xebed5f06, 0x2e724bdf, 0xcecf18eb, 0x66c8ef29, 0xa95c62e7, 0x23fef8b0,
3830 0xfbffbe3d, 0x20b9c7be, 0x21811b30, 0x75dfca8a, 0x26ef3602, 0xcbfdfc21,
3831 0x54238c4c, 0x1696673c, 0x5b650e7f, 0x6c9b7f22, 0xf8424381, 0x72ff18fb,
3832 0x9da86a91, 0x3be5d7f6, 0x678c7c99, 0x26e5dd70, 0xd543930b, 0x950f5fa1,
3833 0x9092fc70, 0x4eec9ddf, 0xc47ff24d, 0x810995ee, 0xcf6c161d, 0x73977e7f,
3834 0x8fd61c84, 0x43d07366, 0xf919a67e, 0xe6b5f548, 0x00b8e2d5, 0x942667af,
3835 0x9eb5b80c, 0x83b8ebcc, 0xb79febf1, 0x286b4dd3, 0x66cb869f, 0xed879796,
3836 0xb78ef375, 0xb8127f48, 0x6ecadcfe, 0x58912cf7, 0xbf6b167c, 0x959eddba,
3837 0xf9227ffd, 0xcfadbbde, 0xfee11fe0, 0x584a5363, 0x99ef1cbd, 0x87583ca8,
3838 0x7f31eec9, 0xb3b7f9a1, 0xcac7bb6f, 0xcf6b12f8, 0x6db37d7a, 0xb2019dff,
3839 0xf68093f7, 0x2fb47a4f, 0xd9a2de41, 0xdd07f33b, 0xb3af815c, 0x339951f7,
3840 0xddef14ed, 0x9e1ddec4, 0xdece6fd4, 0xf23939bf, 0xf85201bc, 0x1c846afb,
3841 0xa43d50d7, 0xc9852db8, 0x2e9b9751, 0xba7e5d47, 0xfd963ebc, 0x637d1177,
3842 0xd775fdb6, 0xd55762ff, 0x53073deb, 0x793b767c, 0xfee1e3dc, 0x8f285ff6,
3843 0xf7373c7b, 0xfe7af7bf, 0x7e8bff09, 0xe26ec072, 0x5bc3a64f, 0xa3f9872f,
3844 0xb741e3cb, 0x2433d8bf, 0x68241fcc, 0x6f4fd530, 0x9ee98fc7, 0x99fefc6f,
3845 0x67fa0b7e, 0xfff433fc, 0x1292f9c3, 0x78b12f9d, 0x49e50466, 0x5527963e,
3846 0xfc83bd53, 0x4fe818df, 0x15bd59f1, 0x9aa43e58, 0xee4979ba, 0x42d97625,
3847 0xc5259771, 0x3afd216b, 0xbea211ea, 0x48f56bef, 0x2496087d, 0xbd0ddfe8,
3848 0x128cf2cd, 0x43cb4997, 0x30f6f30e, 0x09bdfc7d, 0x0c94d794, 0x18e1c6d2,
3849 0x6c089f1f, 0x472df9fc, 0xcdb25e59, 0xfc20aca3, 0x4c48f05e, 0x74b7173e,
3850 0xfde7e3ef, 0x5747c40d, 0x04bbffb2, 0x5676ad6b, 0xda136b4f, 0xc3b91773,
3851 0xdfb57ff3, 0x8817f271, 0xaca3c877, 0x502f79a1, 0x12352231, 0x16ad79f2,
3852 0x84e6f748, 0x5601cbfb, 0xae58bdd0, 0x6044fd1e, 0x1c3c1df1, 0x1fbe9437,
3853 0x959f7604, 0x35b1dfeb, 0x06c77f44, 0xb3e3175e, 0xfea11dfe, 0xb09de09d,
3854 0xd7bed25c, 0xf92370db, 0x866ce4eb, 0xafdf1173, 0x2e9059b5, 0x22efd757,
3855 0xff477d85, 0xabd6fb42, 0xf2cf1ad0, 0xd7efe8d9, 0x4f3013aa, 0x7b287e45,
3856 0xca3b411c, 0x04f6e171, 0xab986756, 0xa47b8fd7, 0x31f44bb0, 0x3d03d389,
3857 0xfd7dd8d2, 0xe74ba6b8, 0x2cff4097, 0x6fcdc533, 0x1e23355f, 0xeff1f66f,
3858 0x99543925, 0x285f483e, 0xdea45d53, 0x95d0f749, 0x4a97a21d, 0x9d5a5530,
3859 0xb5529a1e, 0xbc188afa, 0xb98fc717, 0xf54cdcef, 0xfe1ec3bd, 0x0dd9714e,
3860 0x5d519dec, 0x10b6936a, 0xa70fd72e, 0x71ed8d3f, 0xe979f719, 0xcef2eefd,
3861 0xa366b367, 0xc05ad01c, 0x00fae2c9, 0x36c1675b, 0xd2b91f7d, 0x96ba42fd,
3862 0x4220fbbf, 0xbb9f3a1e, 0xa28f1ff0, 0x0e29bdfa, 0x09dede98, 0xc78a241b,
3863 0xa58c3975, 0x838a53c7, 0xc8efe0de, 0x6ce8050b, 0x3e725c53, 0x5dfbe78e,
3864 0xb0ef8beb, 0x52cd017c, 0x6cdbaa8d, 0xfcf37998, 0xa5602522, 0xbae9bfad,
3865 0xf68f25e3, 0x06103e4e, 0x791deff2, 0x9b52a35d, 0x952c5633, 0x6a4f44cd,
3866 0xbfe4979c, 0x77666370, 0x7c3043f2, 0x83ce441d, 0x2f4cc90d, 0x1845ba56,
3867 0xb7367a8e, 0xfba4c905, 0x160ee5a8, 0x92d83df7, 0xe313a0c4, 0xf8bfea4e,
3868 0x7983fbca, 0xa7cb871d, 0x63eed5f8, 0x6afb1c58, 0xf563063f, 0x4fb9fcd6,
3869 0xd84b77a1, 0x123ab023, 0x75ca12f9, 0xc7563d75, 0x6eac8378, 0xeec096f7,
3870 0xbf9b293d, 0x75495463, 0xd20e1dec, 0xc22f2c7d, 0x2ec94b25, 0x6cddf45d,
3871 0x8faeff12, 0xf7dacce5, 0x3e4d4eb1, 0x7df9d009, 0x881bef6c, 0xccb67277,
3872 0x3d208bbf, 0x264949c1, 0x5cfc9bb7, 0x393fb66a, 0xe6bde29b, 0x9f54459d,
3873 0x4aea0b9a, 0x13d94770, 0x6ae848dc, 0x77b497a7, 0x2b0f5d31, 0x852173b5,
3874 0xc6855feb, 0x3e8d4ad6, 0x2b5418cb, 0x4772cfa4, 0x377ae6f6, 0x80fe8691,
3875 0x1f0adf7d, 0x40fe3dfc, 0x3f7407bf, 0x2cf535fd, 0xc7d2cfc6, 0x7ce3ddb9,
3876 0x0ffd175e, 0x511f5021, 0x6faceac7, 0x77b0233d, 0x326ebd6d, 0xbd0a0ccd,
3877 0x095422ef, 0xd2f7d296, 0x8598e104, 0x62e38b9d, 0x8cc3ab12, 0x63ebfc62,
3878 0xd39d5952, 0x9830ebce, 0xfd43dc27, 0xbf66ead7, 0x7920f8cb, 0xc51bf7d9,
3879 0x6c4f5e36, 0xdf644f7f, 0xee8add1f, 0x555e5af1, 0x6f62e07b, 0x5f71dbb2,
3880 0xf7e27e89, 0x11e38b71, 0x67c753ca, 0xf197f7f3, 0x9828a6d9, 0xe98bfb2e,
3881 0xea3b3fdc, 0x5f909ba6, 0xc167be7f, 0x8771df2b, 0xae887ae9, 0x40a7ba2c,
3882 0x4d3e90b6, 0x371de504, 0xf06df56e, 0x5064f6b3, 0xf7496c19, 0xa54eca4f,
3883 0xac0310ef, 0x7dc47c7d, 0x8b125eac, 0x655e2c7f, 0x2c5efcd9, 0xc14536cb,
3884 0xcfdfb271, 0x5e1852f1, 0xd1365fb8, 0x24f5e3a5, 0xdfea4ee9, 0x88555f25,
3885 0x7ccaef90, 0x02d7df91, 0xf2c3afbf, 0x25496b1d, 0xbd108ef9, 0x0c17ab4c,
3886 0xe0f48479, 0xa5eadd9a, 0xbe5d3b77, 0x9bde8108, 0x638e72c3, 0x88ba52fa,
3887 0x6c91cbeb, 0x6a0baf37, 0x580e4772, 0xf942ae28, 0x9a7c4d3f, 0x75e44237,
3888 0x3fe50938, 0x4addc980, 0x82995e36, 0x2ae8cf72, 0xde2d5adf, 0x66e2d1ad,
3889 0x66f51fbd, 0xeae9f105, 0x89fd61de, 0x4607b53f, 0x7a9fc4c8, 0xd4dbcf13,
3890 0xd0ead6ff, 0xa38bc99a, 0x47ef62ee, 0x297af660, 0x45be2aff, 0x9355b29e,
3891 0x961ef1cb, 0x5fb60171, 0x4076bbf4, 0xa6809fd3, 0x9c70ff57, 0xe2a21fd5,
3892 0xffa211ac, 0x754fe265, 0xf32b55dc, 0xfe7bda63, 0x19b37a56, 0xd11fd612,
3893 0xb26ff0ea, 0xf5cbe247, 0x55f9f506, 0x44e7ff5a, 0xa64ce7d4, 0xef28e7cf,
3894 0x75e56e3c, 0x156456e7, 0xff107ffd, 0xccbbfccb, 0x3e9a77f0, 0xbc512b06,
3895 0x8042e704, 0xbad0f9c1, 0x9fce1072, 0x469658d8, 0xfc9854f8, 0xa2ad3eec,
3896 0x3be9bc2f, 0xec2f681b, 0x76fcfc81, 0x7a77d2c3, 0x5e538a20, 0x5c285b74,
3897 0xb041b49b, 0x97be40f4, 0x41582d34, 0xb78fb46d, 0xb70f4e48, 0x0ee77a6c,
3898 0xe39d17ec, 0x8f1c7d98, 0x1cac5391, 0x45fc6b0e, 0xd39b787b, 0x70ba30a5,
3899 0xa1ed4dfd, 0xe12bdd06, 0x01ffffa5, 0xd5b93efd, 0xefd023ff, 0xe3781b15,
3900 0x7a6ec8e2, 0x3fbfcc83, 0xf3e7f68f, 0xfa27df80, 0x923afa7e, 0xf397dd20,
3901 0xf4979ba1, 0xfb8592ea, 0x807d4bcd, 0x0125c1d9, 0xf0bcec2f, 0xfee906fd,
3902 0xe199791e, 0xf4d6a37b, 0x39f92e5a, 0xc77e57bc, 0xe699e2fc, 0xe4dd0395,
3903 0x64e903ff, 0xd99f96af, 0x735ff5bc, 0x9510ccbf, 0x80ceb4d3, 0x01a03406,
3904 0x0340680d, 0x0680d01a, 0x0d01a034, 0x1a034068, 0x340680d0, 0x680d01a0,
3905 0xd01a0340, 0xa0340680, 0x40680d01, 0x80d01a03, 0x01a03406, 0x0340680d,
3906 0x0680d01a, 0x0d01a034, 0x1a034068, 0x340680d0, 0x680d01a0, 0xd01a0340,
3907 0xa0340680, 0x40680d01, 0x80d01a03, 0x01a03406, 0x0340680d, 0x055ff01a,
3908 0x328d1fff, 0x800060f6, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00,
3909 0x30001131, 0xee300408, 0xd80ea5ea, 0xabdef271, 0x964d2104, 0x5dbbcce4,
3910 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3911 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3912 0xee017e3f, 0x0014ab55, 0x000014ab, 0x00088b1f, 0x00000000, 0xc5edff00,
3913 0x30001131, 0xee300408, 0xd80ea5ea, 0xabdef271, 0x964d2104, 0x5dbbcce4,
3914 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3915 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3916 0xee017e3f, 0x0014ab55, 0x000014ab, 0x00088b1f, 0x00000000, 0xc5edff00,
3917 0x30001131, 0xee300408, 0xd80ea5ea, 0xabdef271, 0x964d2104, 0x5dbbcce4,
3918 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3919 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3920 0xee017e3f, 0x0014ab55, 0x000014ab, 0x00088b1f, 0x00000000, 0xc5edff00,
3921 0x30001131, 0xee300408, 0xd80ea5ea, 0xabdef271, 0x964d2104, 0x5dbbcce4,
3922 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3923 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3924 0xee017e3f, 0x0014ab55, 0x000014ab, 0x00088b1f, 0x00000000, 0xc5edff00,
3925 0x30001131, 0xee300408, 0xd80ea5ea, 0xabdef271, 0x964d2104, 0x5dbbcce4,
3926 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3927 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3928 0xee017e3f, 0x0014ab55, 0x000014ab, 0xffffffff, 0xffffffff, 0xffffffff,
3929 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000,
3930 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2575 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
3931 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2576 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2577 0x00000000, 0x00007ff8, 0x00000000, 0x00003500, 0x00001000, 0x00002080,
2578 0x00003100, 0x00004180, 0x00005200, 0x00006280, 0x00007300, 0x00008380,
2579 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680,
2580 0x0000f700, 0x00010780, 0x00011800, 0x00012880, 0x00013900, 0x00014980,
2581 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80,
2582 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000,
2583 0x00010001, 0x00000604, 0xccccccc1, 0xffffffff, 0xffffffff, 0xcccc0201,
2584 0xcccccccc, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000,
3932 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2585 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
3933 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2586 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
3934 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2587 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
3935 0x40000000, 0x00088b1f, 0x00000000, 0x62f3ff00, 0x51f86063, 0x408cc10f,
3936 0x7f120cb6, 0x66476028, 0x48107d08, 0xf3e2061f, 0x2fe9a48c, 0xb9b04160,
3937 0x40afec80, 0xa8597833, 0x88a1bee7, 0xcfd2738f, 0x81ae792e, 0x66322ff7,
3938 0xe86067e6, 0x6ff047e4, 0xb3caa3f2, 0x3dd7d3f0, 0xb000c6b4, 0x00eeff4a,
3939 0x0000eeff, 0x00088b1f, 0x00000000, 0x7dd5ff00, 0xc554780b, 0x3d9cf0d9,
3940 0x3764dd97, 0x2485cd9b, 0x200d8410, 0x125c40a2, 0x126e20ee, 0xc3116088,
3941 0x65e28145, 0xb201ae41, 0xdb3f6911, 0x5cbb7ffa, 0xc6d6a444, 0xa0b45b4b,
3942 0x06a2828b, 0x82482459, 0xa5c8ba1b, 0x5835b5b4, 0x0da978aa, 0x24c4dc88,
3943 0x97f4b004, 0x3bef3fca, 0xce7bbb33, 0xf4bc4c6e, 0x7d6f9ffb, 0x7339867c,
3944 0xef3bccce, 0x6779de7d, 0x313b10a2, 0x0ae42775, 0x64246efc, 0x19084c99,
3945 0xbbc32d14, 0x32413cbf, 0x46bcf909, 0x08f39a75, 0x86a1d929, 0xc5f5a46f,
3946 0xd400a41b, 0x0893bb4d, 0xd3484819, 0xcaf7563a, 0xa08e8f0d, 0x4ca764ed,
3947 0x8482d136, 0x4592266d, 0x610b09c8, 0xd60a673f, 0xeab126e7, 0xee7b0de2,
3948 0xd7e7fe82, 0xfd12499a, 0xec8d44fe, 0x4d92fa86, 0xb4488052, 0xad21eebd,
3949 0x5e7fed0b, 0x39260a40, 0x63d37d69, 0x9085339a, 0x6cbfbbe5, 0x5c057182,
3950 0xe2167c67, 0xbfbe00d4, 0x23f63565, 0xadb03ca4, 0xa7ed0bb4, 0x99725abc,
3951 0xebe538e8, 0x038df0a4, 0x9014b9e1, 0x370bbf69, 0x0fb3895b, 0xc10ae183,
3952 0x4b1e7171, 0x6971d3d6, 0xd2a9447f, 0xe3a252ca, 0xf19cfc09, 0x4471c5ad,
3953 0x744bf17d, 0xc55dfa1c, 0xa60b92ab, 0x9e226158, 0xa9bf1d20, 0xf3da692e,
3954 0x32df9836, 0xec4a77ad, 0x0ebe663c, 0x6c0f28f3, 0x006d4ad0, 0x6e6d06d7,
3955 0x0b7f68bf, 0x0f56ff37, 0xd99edad7, 0x6376989e, 0x5147c679, 0x2f5a3bda,
3956 0xb41dc427, 0x6d01fc01, 0xf3e8ff62, 0x908d295a, 0x4cbfd04e, 0xff68969c,
3957 0xb9f1f884, 0xc0615c4c, 0xb8a5093b, 0xead6e962, 0x496dd3d0, 0x0db6ff1a,
3958 0xe9c97e78, 0x81cf98f0, 0x1cbe13e5, 0x73e57f2c, 0xf1bf9c22, 0x29f2c1f5,
3959 0xff9f0b9f, 0xcb1437d6, 0x96373ef5, 0x62c6facf, 0x8657c1b9, 0x9bef3def,
3960 0x9f26e586, 0xe8bf9f07, 0x4be58f9b, 0xfe7c4abe, 0x2c7eef8a, 0xf8fcf8b7,
3961 0x356fab7c, 0x557cdb96, 0xf4e76e58, 0xe00be1da, 0x9b7d3b7b, 0x05f3acb1,
3962 0xbe1bf9f1, 0x017f2c5a, 0xaa65a478, 0xa14cb1db, 0x4d1d4a74, 0x484d941c,
3963 0x32d95946, 0xa633d695, 0xa7b67ab0, 0xf146996a, 0xd69b3d94, 0x2b731d29,
3964 0x6999961b, 0xd652ee7b, 0x58efddde, 0xddeda16e, 0x9ef6b257, 0x93cb6555,
3965 0x27cf7b68, 0x8135fb59, 0xb4c9e5aa, 0xac8d9afd, 0x61b06fbd, 0xf7b695b9,
3966 0xd7ed61ad, 0x6c2b1d87, 0x3efd7eb4, 0x286c2f56, 0xeb42915b, 0x7d598785,
3967 0x0ad56348, 0xc87efd3b, 0x88fdf671, 0x4ceca096, 0x55db1fc0, 0xd2843dd7,
3968 0x52fed7ee, 0xd68c32b7, 0xc47dd735, 0xff66c845, 0x33a56ead, 0x865a87c5,
3969 0xd3fcbbed, 0xc32b5d58, 0x33fcb7f6, 0x6a9dfdf1, 0xec7fb625, 0x9df6c72f,
3970 0xb7b6255a, 0xf6c3eff8, 0xdb0ab53a, 0x601ecb4d, 0xdb0aad75, 0x883d9733,
3971 0x52a1bfef, 0xd2138760, 0x6ea3d97b, 0x966f853f, 0x7d02a9e4, 0x9caa6cd2,
3972 0x28b7404f, 0xaf901ce1, 0x0d322487, 0xc4a7e5e4, 0xa1e6fa89, 0xc83734ab,
3973 0x8343f6e1, 0xc539079f, 0xe7d4265f, 0x0f26b0be, 0xfb0a79fb, 0x3d3f68d1,
3974 0xf0a7efdb, 0x7ebaa19d, 0x2f99df0a, 0xf80e79fa, 0x63b939be, 0x677f6cfd,
3975 0x779e1eb8, 0xaf3f45ca, 0x8ef63f60, 0xaff0abcd, 0xfcf0f523, 0xa7e89175,
3976 0xde95e706, 0xbc767831, 0x1793f14f, 0xfbc767ed, 0xf6123f14, 0x64fd8f53,
3977 0x419e0c75, 0xf5d50c1f, 0xf983e833, 0xd8039fa2, 0xf58e974f, 0xe183e3b3,
3978 0x283e787a, 0x8dbcfd17, 0xd8eb74fd, 0x387d06bc, 0x87cf0f52, 0x473f448b,
3979 0x1d1e9fb0, 0x51e767eb, 0x1e767e3d, 0x28e7e08d, 0x63bbd3f6, 0x4c721af3,
3980 0xc7219f8f, 0x8339f822, 0x63aebf74, 0xa63cecfd, 0x63cecfc7, 0x479cfc11,
3981 0x363bf278, 0xe89f21af, 0x93e433f1, 0x632e7e08, 0x831d053f, 0x1eb4eea7,
3982 0x23a7753f, 0x982551f8, 0xc18ee0d7, 0x1e8cec33, 0x44cec33f, 0x009763f0,
3983 0xeb1de19e, 0x1e8ceea7, 0x2267753f, 0x7846c9f8, 0x5e6c7546, 0xe3d33ec3,
3984 0x1167d867, 0x9e1138fc, 0x08cdcae2, 0xf4fda10f, 0x379fbb6f, 0xcff5e9ce,
3985 0xfe98e71b, 0x8fc47819, 0x21cd57fa, 0x6467002e, 0xa25f994b, 0xd6932575,
3986 0x89ba509d, 0x055fda87, 0xf83f70ec, 0xd32fd1b8, 0xb4ea94f6, 0x58ce3582,
3987 0x02ec5c7b, 0x4d03ec78, 0x18ef7b3a, 0xa7abac99, 0xd9d74e8f, 0x5df1cceb,
3988 0x29acf574, 0x9cf5743d, 0x7dd3ae3b, 0x817665df, 0xd175deae, 0xdbbd5d70,
3989 0xf7dd62d2, 0xd66e07ce, 0x3958f7b5, 0xf5ef5749, 0xf5750fc8, 0xd2ce4fde,
3990 0x2bacfbd5, 0xdd77f5d7, 0x7aba25c6, 0xea9feabf, 0xcb35f9ea, 0x68577575,
3991 0xb05eae8d, 0xff5d71ef, 0x5a7adf03, 0xf87c1f57, 0xe87d5d39, 0xbeeb2f47,
3992 0x35fc7e1f, 0xd9e47d5d, 0xc7ff065d, 0x97d138e6, 0x77f065d7, 0x9a07e8ad,
3993 0xcfe869bb, 0x60b37516, 0x6cddc7fd, 0x28f1ff58, 0x4a0e35cf, 0x07c39fd7,
3994 0x58fdeed4, 0x48ef5cf3, 0x25297f60, 0x4a07244d, 0x8d0c898f, 0x52ad5f6f,
3995 0x527ca3be, 0xef72fddc, 0x9af4b4a3, 0xd1a77a5a, 0xa2a6eff2, 0x3f17c0a5,
3996 0x97e84c95, 0x09526559, 0x1335647c, 0x57d5cbe4, 0x1fde7e0f, 0xe70fdfc3,
3997 0xfd14be31, 0xe656ac3e, 0xeffe1d80, 0x83f3bf65, 0x4f287e1d, 0x93ec3b43,
3998 0xf7f6177e, 0xfde7dfa2, 0x49fc0738, 0xd4fd468b, 0x3a35f1d8, 0x7f1c3f7e,
3999 0xa6bf8c25, 0xbd2df18d, 0x4fc6ea87, 0x375f31ea, 0xc746927e, 0xe8f21077,
4000 0xf1f3dfb2, 0x50bafe29, 0x3dfa50bf, 0x71e96f8e, 0x5abf8e3f, 0xe375f323,
4001 0x7fc64727, 0x69fde412, 0x82507f18, 0xae1ef7f9, 0x728f7f9f, 0x3635fcfd,
4002 0xbd9667ff, 0xc64fc7cd, 0xbd2b3ff9, 0xe3dfe6cd, 0x66fe6ca7, 0xf8ec6fda,
4003 0x37fe08f6, 0xb72ff8c2, 0x9ae5be31, 0xf7f9fa91, 0xbf9fa45c, 0xeaff8d99,
4004 0xf8f8f7b2, 0xab7f1c36, 0x7f9b1ef4, 0x7c7007cf, 0xe5d2b9b3, 0xeee64da0,
4005 0xd00195c9, 0x263dd413, 0x746020d9, 0x2820219c, 0xefd084e9, 0x903d4817,
4006 0xa64e3f0e, 0xffdf477c, 0x1bf29922, 0x6fdcf7f8, 0x12558127, 0x1dd74c19,
4007 0x5767a79c, 0x417ed4cf, 0xcb5d993f, 0xae8433d6, 0xf0a6ae77, 0xff9ed535,
4008 0xef0a43e2, 0x50038dec, 0x274e514f, 0x3e1cddf0, 0xf0ccaf15, 0xb7594841,
4009 0x12bf5489, 0xa4dbaca5, 0x06e4d8fe, 0x411e7fbf, 0x78f8e318, 0xa27a954e,
4010 0xe6fe4631, 0x17d7d5ad, 0x0175f404, 0x09301177, 0xa4c5fd2d, 0xf71d254f,
4011 0x10275d18, 0x447f97ea, 0x594270fd, 0xdc9513f6, 0xf2f1465d, 0x404f5d31,
4012 0x27ae91bd, 0x4cae9da0, 0x14c72e91, 0xb63bf382, 0x7a001ada, 0x0193f17c,
4013 0xbb87d81a, 0x1bf2a7ef, 0x727edf2b, 0x5fc28738, 0xd339e7c6, 0x076fa19f,
4014 0x4c3c53bc, 0x0b2bf3e4, 0x974f1e2d, 0xd59ee4c4, 0x459954b9, 0xf24a6bdf,
4015 0x54ffd0a8, 0xe9b356e2, 0x9d2e7778, 0x5f107aa8, 0xca135cee, 0x5135c939,
4016 0x56e89f39, 0xf4c6358f, 0x8066a93f, 0x93227b4a, 0xdf9feac7, 0x37afa656,
4017 0x44d56ea9, 0x5134d3e9, 0xdda81b22, 0xdf4d3a99, 0x2339c62e, 0xc5fce3a5,
4018 0x6e746578, 0x9e61d39d, 0xeffa63f4, 0x3cd83a1f, 0x34bc3ae8, 0x3f73d617,
4019 0x689b5c90, 0x57bc2a7d, 0xa83d7400, 0xb769f3c1, 0x90d6b9a4, 0x92897878,
4020 0xe11cfd83, 0xca23bceb, 0xcd0c5fa6, 0x83ff878b, 0x29b756dd, 0x461e7e3f,
4021 0xa093a7b8, 0xba76f60a, 0xc67cff47, 0x18fce37c, 0x74e09c5f, 0x407c063e,
4022 0x07c093cb, 0x39c7cf14, 0x2bf5441f, 0xc01383e3, 0x4eb09907, 0xa7307c66,
4023 0x6ffd312a, 0x479ff4e7, 0x29676afc, 0x9ca9f74a, 0xba73b7ee, 0xe7ab5bcf,
4024 0x3cf9b88f, 0x1cc1e1b9, 0x3cf98267, 0xa62547b2, 0x657979f8, 0x2ff91f06,
4025 0x8e89b029, 0xbea5677b, 0xfd0376fd, 0x777e9c3c, 0x7165e846, 0xbf3e5197,
4026 0x011927eb, 0x7c7133d0, 0x31f5e9c1, 0xb5b4d7a7, 0x4cefed8f, 0xe46be1e2,
4027 0xf6b13af4, 0xfb44d579, 0x112f9c6b, 0xf08c6ff0, 0x9bbbe11a, 0xdfa03438,
4028 0x9febf7dd, 0xa627f4cf, 0x28b6b79f, 0xf3cc78e3, 0x1971c1c5, 0x68e463c7,
4029 0xba89e6e1, 0x74c082fa, 0xd6f3fbdd, 0xcfb5d4ce, 0x6ba05aa9, 0xbdf567bf,
4030 0xff4cfaba, 0xdfef744f, 0x5d32ff7d, 0x0f959dfb, 0xcc67daeb, 0x9f574c7f,
4031 0xf74a79ee, 0x1b69d4fe, 0x95b7ed74, 0x9f6ba4bd, 0xae9b763c, 0xa75dd13e,
4032 0xbdda5f7b, 0x9fc43ba0, 0xd9e79abc, 0xbd9b886c, 0x49cf266f, 0xe84c7af1,
4033 0x273ee3bb, 0xebe13f3e, 0x9f29e583, 0xf19f9f0b, 0x1972c50d, 0x176a71e8,
4034 0xf4ac754c, 0x3bb33e3e, 0x07217fe8, 0x6eaea89f, 0x7a8d3fa0, 0xc4e7a8cf,
4035 0x46bd46fb, 0xa7e0b97f, 0x59cf15b4, 0xb0329124, 0xf312cd0b, 0x43f3c457,
4036 0xb2123edc, 0x1a45cb1c, 0xaf45d393, 0x39062e75, 0x7b85a45a, 0xeedada57,
4037 0x9c250497, 0x9eaa9ccf, 0xade7383a, 0xef806bed, 0x05abe439, 0xf3dd4281,
4038 0xe8479b85, 0x47bb3bbe, 0x402af846, 0xff8187b6, 0x04deb65d, 0xb7bc31f6,
4039 0x00fee4db, 0x1319fbaf, 0x09db5bc0, 0xdf59eaed, 0x0ae38cd8, 0xcb0cb9e0,
4040 0x5869be53, 0xb079f09e, 0x8f9bee3c, 0x255f31e5, 0xfbbe8d96, 0xe7d8fcb1,
4041 0xdf23f2c7, 0xf03f2c6a, 0xc4796155, 0x77cb16b7, 0x0f2c017d, 0xf96336fb,
4042 0x65882f8e, 0xcb16af83, 0x4b1b9f26, 0xfc312f21, 0x0c73bdd2, 0x277d08bf,
4043 0xce29e1f4, 0x5f80672f, 0x73c5f112, 0xa938be7a, 0x185f2256, 0x0e91a1f5,
4044 0x6df77d46, 0xf4dd21f9, 0x9443f0fd, 0x7a06b9de, 0xde8f6cf7, 0x397d221f,
4045 0x0e4dd3bd, 0xf7a70f06, 0x45780623, 0x041281a9, 0x7e6665bd, 0x595b711e,
4046 0xabc453dc, 0x7b8b3249, 0x337578f2, 0xbc0377fd, 0x10fb04a7, 0xbf6b5fda,
4047 0xe21bdbff, 0xcc47adcc, 0x3db5e484, 0xdafd233f, 0x9bf103c4, 0xc9ff0ebe,
4048 0x14af0cc9, 0xda84b1aa, 0xbed73587, 0xeac59aee, 0x423b010a, 0xb8d8ae82,
4049 0xc05fa46f, 0x78fb7665, 0x7f31374d, 0x6657bad3, 0x776f08f8, 0xf2894e4d,
4050 0xd2dcd7ab, 0x95f833bb, 0xd8099a1f, 0xe9b01233, 0xf5a7e5f1, 0xb57c51c1,
4051 0xf4f68f35, 0xfc2fffde, 0xda8fa7b4, 0xa48743d3, 0x735fc7af, 0x24f75d31,
4052 0x008e2f58, 0x6df41c3e, 0x1ba1b0f8, 0xf81061f0, 0x5adff69d, 0xe92a4d73,
4053 0x66e7ed17, 0x13af9393, 0xde4e9ebe, 0xd37e0854, 0x1334537e, 0xcbae9eb9,
4054 0xf24dcf65, 0x5dcff020, 0x6f4a7e8d, 0x6bab6eff, 0x49d61385, 0x7612fe67,
4055 0x75fa17c2, 0xe7c1eb73, 0x59aeb0ed, 0x1c726392, 0x3e9b6c2f, 0x0e79838b,
4056 0x547fac5b, 0x56b7afab, 0xdc596349, 0xa53a99c4, 0x8769e83f, 0xd02f78e3,
4057 0x8a58399b, 0x68e4967e, 0xf019e38e, 0x79c9805e, 0x81ea1a75, 0xbe0b3e33,
4058 0xd1c37df7, 0x38513f56, 0xf427c86a, 0x2b89107b, 0xbf7edb3d, 0x2e56be4d,
4059 0x228f1068, 0x580bf521, 0xffd1252f, 0x7e80f4af, 0x7e8bac15, 0x6fd941bd,
4060 0x579e1ebe, 0xdfa3c6eb, 0x1b1ec539, 0xfcb6d77c, 0xe084e428, 0x3f374a5f,
4061 0x2fb8a7f8, 0xfbd0e494, 0xbaba696d, 0x43b3b6b7, 0x3fc1c7e7, 0x2d1cd1c0,
4062 0x8b47c029, 0x2b355b38, 0x8512d5b6, 0x322c066f, 0xf6259f81, 0xa34b62de,
4063 0x968fa1e6, 0x7f4148ec, 0x7c63c978, 0x1a4fcd9f, 0x4359fbe0, 0x29970779,
4064 0x51fd3154, 0xb44c470b, 0x89af0f7e, 0x3559aefd, 0xff5fd10b, 0xdd71f894,
4065 0x1aae5a77, 0x796a7e0c, 0xa6e68370, 0x989cfb74, 0xffbe82c6, 0x2f63bc9c,
4066 0x57b7918c, 0x7be70d64, 0xffbd6acf, 0xbab1d74a, 0xeac75d3a, 0xa4c973ea,
4067 0x9a17d82c, 0x974aa4fb, 0xd5aeb8d4, 0x7656ffb5, 0x91e77ce0, 0x876055ca,
4068 0xbc29a93f, 0x71e0047d, 0xb0c1fae7, 0x9b459c4e, 0x29fea973, 0x03487cdf,
4069 0xe3a6f939, 0x0bef802f, 0xf315c7e2, 0xe407db8a, 0x59bc5878, 0xd8120772,
4070 0xf76e5abd, 0x3bfa5e84, 0x1eb31fc0, 0x23e7cd3f, 0x3f9adfea, 0x65c32932,
4071 0x4339e945, 0xc1921cf6, 0xa49f008e, 0x5be2f946, 0xd7139ff7, 0xd7bfdfff,
4072 0x1d12bbfe, 0x4ffed37f, 0xdefc5e83, 0x0715effa, 0xf044c5ff, 0xb22c3a0b,
4073 0x17c01c34, 0xbe096e1d, 0x14dcb853, 0x7c60714d, 0x725ab9aa, 0xc4fbe999,
4074 0x2c8e9c4d, 0x3d601fa6, 0x6a5afcd9, 0xe1bd413e, 0x1f3a6e20, 0x552e7f2b,
4075 0xd123d9ef, 0x3b4ae175, 0xfe51a771, 0x9953e954, 0x692ad1ca, 0xe5a24580,
4076 0x7f739ae2, 0x9bf68379, 0x88099214, 0xa1853374, 0xdd97f701, 0xac776069,
4077 0x03b411e4, 0x257ec7b0, 0xd1a70a23, 0x0578103e, 0x8d8397ec, 0x61b6463b,
4078 0x9d75a6fc, 0x9955718c, 0x919bf75c, 0x0f782f54, 0xeda2f952, 0xb405f0ad,
4079 0x5d7095af, 0x04b07adf, 0x24eaf3eb, 0x6beb4192, 0x60f9ec93, 0x26dcd2af,
4080 0x63373c5d, 0x4e7e3eac, 0x5806eefc, 0xf3e6cfff, 0x1c00c405, 0x53bd790b,
4081 0x7de1ba59, 0x5c4c5ffa, 0xee67b66c, 0x93f14278, 0x771f4d3d, 0x723f285f,
4082 0xed3ae200, 0x06ed6dca, 0x9463900d, 0xf59b85db, 0x21b78175, 0x09e64a4a,
4083 0x6236c9b0, 0xadb5bc03, 0x67c1dbc7, 0x8cdfef63, 0x7c71d81c, 0xce64f11a,
4084 0xc935e3d1, 0xb5abc7a9, 0x066f018f, 0xf4b8a6bc, 0x3a66a2f8, 0xa9af0890,
4085 0xfae87b43, 0x7af1bef9, 0x6fb3e017, 0x57f49f14, 0xa262c966, 0x56767007,
4086 0x46ffc8c2, 0x85b5c979, 0x55f7f825, 0xf8658199, 0xf5052b95, 0x5f870e40,
4087 0xb3becd9a, 0x60c8bc82, 0x2f285d55, 0x3b046910, 0x391f256e, 0xf2268e80,
4088 0xb7d2b909, 0x37de3a6d, 0x59d1df71, 0xc075abf4, 0x1f23d7cf, 0xe9fc5d20,
4089 0x0f22b024, 0x00e5d1e4, 0x59f416bb, 0xbae9b39c, 0x711f55f1, 0xcdfea6ce,
4090 0x96073e6b, 0xf7b0168f, 0x0091fb9b, 0xe1831bac, 0x884e590b, 0xeba1cf67,
4091 0x1fffaa34, 0x80265ad5, 0x9517fc3f, 0x55eecfad, 0xab772c35, 0x47ffae26,
4092 0x79f201ff, 0x00ffa99a, 0xd0e6a5f1, 0x50d5cb26, 0xbf3195af, 0x75569bc0,
4093 0x14df8c2d, 0xb35c1952, 0xf64f182d, 0xc768abd6, 0xc48f669b, 0x9f311a7c,
4094 0x163c90a6, 0xa1cdd9e2, 0xc4f7ec4f, 0xdaa69dd8, 0xbb05ae27, 0xb12994f7,
4095 0x628cfbff, 0xc87e6efa, 0xfa3d38ba, 0xf509d28c, 0xe83da3e7, 0xb6262a3c,
4096 0x9becbf22, 0x77ce337b, 0x9a724847, 0xf2a5dc29, 0x0fe83f1d, 0x537f86fb,
4097 0xee24de98, 0x58b333f1, 0x5f563ce8, 0xabd4888c, 0x7ec32afe, 0xc3c45d25,
4098 0xcac0e2be, 0x8c87e8b9, 0x0292490e, 0xc108ebfa, 0x0fc8467e, 0x7f32c094,
4099 0xe3a28350, 0x0921c1c7, 0x91b836f1, 0x90d37e60, 0x61f6fa23, 0xae218a8d,
4100 0x9f819016, 0x3fd29c46, 0x6d7c13af, 0xd7c05927, 0x25965e4f, 0x5b9a4ff0,
4101 0x1d396b88, 0x977679bf, 0xf9a78022, 0xd046ec02, 0x363cb2f2, 0x8ff7fad1,
4102 0x9e87f30a, 0xc6fed8d2, 0x816d7353, 0x6fbe9465, 0xb8c72dce, 0xf13f17c4,
4103 0xbfb44f74, 0x5287a315, 0xdc83684d, 0x75cfb0a9, 0x1295c4df, 0xd552031a,
4104 0xfe252cb9, 0x82bfc17d, 0x771f059f, 0x09ec9b9e, 0xb2671824, 0xe294fcca,
4105 0x8d247db9, 0x5bb4d7c2, 0x4da57422, 0x747b969a, 0xe9630ef1, 0x0173cb27,
4106 0x79ed6f1e, 0x2594ec0d, 0xfa0fd894, 0x3ca3b14c, 0x2ff72d34, 0x1fb5bc83,
4107 0x3bf46153, 0x27dfaebf, 0x48723e31, 0x2cefb271, 0x9e813355, 0xe42c732d,
4108 0xd6379639, 0xf00a5279, 0x55b8c97b, 0xcba7de14, 0x9f37684c, 0xbf085d52,
4109 0x7961317f, 0xa2ff7c71, 0x61b204eb, 0x5cfc8c4d, 0x95248a54, 0x0ea92bf6,
4110 0xe3c33fec, 0xd77e0092, 0x8769ffbf, 0x4be690fd, 0x1763a466, 0xdf10f71e,
4111 0xfad95575, 0xfeea8371, 0xd0f58152, 0x0b944cfc, 0x9ceec797, 0xf5f2ed4d,
4112 0x09ef14b5, 0xffe146fc, 0x98e87ba5, 0x9b749e14, 0xb892f909, 0xd5074edd,
4113 0x7e225e77, 0x8883947e, 0xa225845c, 0x51ea8e0c, 0x53852429, 0x681c3ea8,
4114 0x5a6585b1, 0xf3a7cfa6, 0x6231fd86, 0x2835fd61, 0x40fb2367, 0x7ca1aeb8,
4115 0x4d821839, 0xaef587f4, 0xafd0bfd8, 0x84af2f42, 0x67ed36b8, 0x604a63e5,
4116 0x9d67ed05, 0x357498d2, 0xcedcf32d, 0xba412062, 0x5003f4e2, 0x2e27cd57,
4117 0xf6b1210a, 0xf1169f5c, 0x0ed0a847, 0x78c64af8, 0xd38e9180, 0xf4f2f822,
4118 0xf3fce952, 0x09bcb60f, 0x892b8b6e, 0x6fdae78d, 0xca593b41, 0x4fb0eaed,
4119 0x17d0014d, 0xee237c24, 0x112d799b, 0x17d3a0fd, 0xc4686ec3, 0xef61ae7c,
4120 0x54a87833, 0x41fde1b9, 0x7d723c11, 0xa136fdc2, 0x8284863f, 0x2eaeb085,
4121 0xb5ee1508, 0x3e0bf1d1, 0xa71b7262, 0x15d20e3f, 0xaf6f8f5b, 0x307c8c37,
4122 0x90e54c20, 0x1d1fa5d3, 0x23a0f0bf, 0x52f68752, 0x7019ea95, 0xc99eb916,
4123 0x1b30389c, 0x7f38bdf7, 0xe42af119, 0x05e728d9, 0x9af6bbf7, 0x0c885c19,
4124 0x8a4438e3, 0x09ece1c2, 0x392de87a, 0x1157f415, 0xeb8503c5, 0x696f2e73,
4125 0x60e30217, 0x6e864ffe, 0x65df224a, 0x7e99b25d, 0xc62f631d, 0x20d99ec9,
4126 0xd85ed477, 0x7b150f01, 0x8f4c682e, 0x11de9185, 0x0172a7be, 0x10b909df,
4127 0x6fe46efc, 0xe82b0f21, 0x189ea657, 0x4760249f, 0xce082965, 0xeb61d52e,
4128 0xe157801c, 0x1a7f1337, 0x3a9663c6, 0x78eb38d8, 0x24d2ca5e, 0xd7fa7677,
4129 0x25ef5fe8, 0xc4c40913, 0x8b4abc39, 0x7bd17a06, 0x8c812349, 0x8d9f80ef,
4130 0xad59f871, 0xcfc78a76, 0xebf3c86c, 0xfe02bff4, 0x87fe1180, 0x5ff8519c,
4131 0x421456b7, 0xe70efe9d, 0xef9bd2c4, 0x15f90a13, 0xb6b43af2, 0x9cb52f72,
4132 0x2719f271, 0x0c80a197, 0x4f978a78, 0xccf41932, 0x23f33088, 0x817a728c,
4133 0xf6f9a3cf, 0xefc0de96, 0x0ea7b2f9, 0xf7def7e0, 0x2fe83745, 0xc63249df,
4134 0x6bf32053, 0x2bd81765, 0xb3a190d2, 0xda76f107, 0xf5c4e8cf, 0x9f9f057a,
4135 0xd4f94b54, 0x9e05fb0e, 0x0affd07d, 0x41ff5b07, 0xc7f41e40, 0x7bf3c545,
4136 0x852b0b90, 0xa7e2192d, 0x1879c27d, 0x45c832a7, 0x3560725b, 0xce9079f0,
4137 0x9f8cec17, 0xa5ab99da, 0x5879e1b6, 0x52f0634d, 0xa23f07e9, 0x06c260eb,
4138 0x8fb820ab, 0xe59f35da, 0x602d74af, 0x729fd6f9, 0x50c27e7d, 0x3eca545e,
4139 0x0aa97986, 0xbe0b9bf1, 0x2a00dc3d, 0xaa4e5fc4, 0x1f008fee, 0x9c6eb196,
4140 0xb883ae47, 0x72276a24, 0xa2e4a095, 0x722fa470, 0x9fc6bda2, 0xbfb49fb0,
4141 0x22cef1dc, 0xd52e77a0, 0xcaf71089, 0x91247f05, 0xc22aa85c, 0x3ef9adfd,
4142 0x5f07e710, 0x407f7ce1, 0x18cdf3a3, 0xbcb1a2df, 0xd4ce2a85, 0xdbf0092e,
4143 0x4e3b7294, 0xc4a2e9b6, 0x8634fcfc, 0x08bae367, 0x52f30608, 0x8d41fd78,
4144 0xb8e94928, 0xbec3f16e, 0xc164dfb2, 0xb8958b75, 0xbae7a082, 0xbe1e2c68,
4145 0x86ad724a, 0x16952ffa, 0x78f9e40b, 0xfefd6cad, 0x2e49c8e8, 0xbf62be85,
4146 0xd61f35a1, 0x3bcf949e, 0xa6fdf469, 0x57bdad91, 0xba5a0ce2, 0xcb737e31,
4147 0x27c12f30, 0xb56e8215, 0x496e8eaa, 0xa1888f10, 0xad148adb, 0x4dc5f80f,
4148 0xd60bb252, 0x240b4d29, 0xe164a706, 0xff9053f3, 0x1e127122, 0xf2d42857,
4149 0x6f423f10, 0x86acf9d3, 0xfb0dc052, 0xf92fd0fa, 0x89b0359d, 0x8f1bfabe,
4150 0x81c433a5, 0xed8e67b3, 0xaf67710c, 0x491ba5bd, 0xf3a60710, 0xcbf3001b,
4151 0x40d32b56, 0x79df65cf, 0x30f40edc, 0xd7f62dc2, 0x4bfb07f0, 0x586c656f,
4152 0x7125fe83, 0xe7cf7ab3, 0x05094eb0, 0x60e39978, 0x2a49cff0, 0xb7d58acb,
4153 0x132cfa4f, 0xef5a2515, 0xec4bc914, 0xffe7cba3, 0x89daefb5, 0xbd7be9a3,
4154 0x59372635, 0x9fe3f5a4, 0xd6e671d1, 0x3f105d58, 0x8cf65478, 0x773fb803,
4155 0x70975f3b, 0x01295d1d, 0x959f8b1c, 0xf079d3c8, 0x43fb611d, 0x1f943f1c,
4156 0xd98ecf3a, 0x2ef3a037, 0xd3c506d3, 0xb52559b5, 0x7212e710, 0x2ca7c999,
4157 0x4ba082f4, 0xea9bd026, 0xe5465205, 0x8dce2634, 0xdc6166af, 0xe8527f0a,
4158 0xbf02fff7, 0x31437ed1, 0x1ba09dca, 0x48f4c3e9, 0x4c75c812, 0xfeb9aabc,
4159 0x14fcabbd, 0x9fffbf8e, 0xb68429f3, 0x496943ff, 0xf53e3901, 0xdc535fc0,
4160 0x00f60f90, 0x977acf5b, 0xeebce2a4, 0x8ff77ee2, 0xb46a9e38, 0xd79872b2,
4161 0x637fbedd, 0x6fa2379c, 0x8efb67ef, 0x8ffaa80b, 0x4b6a2fdd, 0x1479c32f,
4162 0xfd7793a2, 0x8562ecbe, 0x7e30eb9d, 0xeb6349bf, 0x1bd505e6, 0xc0275cb4,
4163 0x806ff9e3, 0x5f5f14e7, 0xf161aa9c, 0xacdf011e, 0xf81a01ea, 0x9908ffdc,
4164 0x1fed9849, 0xb95f4ca9, 0xb7c5126d, 0x08d1e387, 0x179e01f7, 0x3257e739,
4165 0xe933c1fa, 0xb953f758, 0x601684f7, 0xff08c71c, 0x52bcba9c, 0xf3987fc8,
4166 0x29eb84b0, 0xaa01ff78, 0x3ff73d3f, 0x68e80e74, 0x9f319f9c, 0x171f18c4,
4167 0x43c8b37e, 0x983c4d9b, 0x27171297, 0xfb1cfd0a, 0x9e8bc637, 0x797af8d5,
4168 0xfb021930, 0xbef96725, 0x621b9c3a, 0xcb04ebfb, 0x14925072, 0x1e968b9f,
4169 0xb926052a, 0xc61b72a3, 0x33f8c5eb, 0xf833f8f8, 0xaae15438, 0xe633c7c0,
4170 0xf36217ab, 0xdc68b6dc, 0xc7421e6f, 0x89e3a393, 0x39731671, 0x7a0be314,
4171 0xe72abe0a, 0x7f515d74, 0xd3235bb2, 0x0c498703, 0x9ff88c7d, 0xca2b3bf7,
4172 0xa1cf0447, 0xfd039c5f, 0x51736738, 0xec271769, 0xc28e545f, 0xcfe269fc,
4173 0xe16af961, 0x1bb7581c, 0x36a4def1, 0xd8257376, 0xfee2689f, 0xb9717b5c,
4174 0x03c89a1d, 0x94f2c2a8, 0x67e07552, 0x191b87c0, 0xb9de2c1f, 0xb79075e5,
4175 0xb2bfadf2, 0x569dbc83, 0xbc60b2aa, 0xb41e9b45, 0x29c57ec3, 0xbd076fc5,
4176 0xe4c03a78, 0x8aefc8ce, 0x305bec59, 0xe0f6157e, 0x9f3fcbcc, 0xc5f9fc00,
4177 0x7a01d526, 0x1cd9bbde, 0x547c5336, 0xd0fc30d4, 0x7f5651fa, 0xade2f108,
4178 0xfe5dc3d5, 0x9cb2afe2, 0xe7969f6c, 0x9d7185f3, 0xd3f1b15f, 0x2f0f9052,
4179 0x1d7dc169, 0xfe3077e3, 0x97dc74a5, 0xc6a5a99b, 0x11be0bb7, 0x8d6f05eb,
4180 0x3c469be0, 0x7f7c665f, 0x172fd73e, 0xfe72bf05, 0x0120f811, 0x9de457a6,
4181 0xd28ff3eb, 0x7f8dd9fa, 0x62fd4bb2, 0xbfcb09f5, 0xf3de0d68, 0xdb672eec,
4182 0xe71360fe, 0x0177e8c3, 0xcb59cefc, 0xac4230f3, 0xed86a45c, 0xb4591710,
4183 0xecf5c541, 0xbfcf2da2, 0xbdd834f0, 0xabaecdf7, 0xb70bff69, 0x38777fec,
4184 0xa6dc2fad, 0xd3678e66, 0x763149b0, 0x5a7c0bda, 0xf943a510, 0xb39afdf6,
4185 0x40fe7b3f, 0x0b1e947a, 0x48d1edb7, 0x947c78ff, 0x8c68f704, 0x09740dff,
4186 0x7d852d1e, 0xbfe7796e, 0xe9fba035, 0xbc8112dd, 0x6e7c38cc, 0xd2fb8fd8,
4187 0x23a42780, 0x6e8453a7, 0x94bdf786, 0x39e7682e, 0xefed8c9d, 0x3fe40e69,
4188 0x5dce0fe8, 0x757e7e51, 0xfccfc517, 0x982ecc0f, 0xef57fcff, 0x4e3cc3b3,
4189 0xaf8c952a, 0x05983fd7, 0xeabe6476, 0xc96072cf, 0xe67fcf9e, 0xf36fc847,
4190 0x8b28fd0e, 0x99d2fd30, 0x9dfcd1c5, 0xd6737e61, 0x9bf386dd, 0x77c83c4b,
4191 0x65cbd7f3, 0xa8babf10, 0x12dbb190, 0xb94fc5c8, 0xce7c9c5c, 0x27f8fb8c,
4192 0xb8531ec1, 0xccc8effc, 0xa2f721cf, 0x9f11fd7d, 0x58fcb50b, 0x18e3c8bf,
4193 0x1e22cd13, 0x2c72b54c, 0xa87c6ebf, 0xe673e801, 0xc436772a, 0xf144bd01,
4194 0x57487c73, 0xa1f2bf68, 0x3f5cd931, 0x7f189539, 0xc39e04b7, 0x3baa0dfb,
4195 0x1df75f29, 0x1d1792b9, 0x9f1f297f, 0xfb0c9dc2, 0x12b327c6, 0x305f87c7,
4196 0xd611624b, 0xa303f3a0, 0x7de4cdf2, 0xbe4cc3e3, 0x2607bc85, 0x0bf6858e,
4197 0xc0fc9987, 0x53c7e077, 0xd8d9c2b8, 0x848a67be, 0xc3da80fa, 0x51bd7244,
4198 0x6fad72e5, 0xe1427c17, 0x897fc056, 0xfb610bf0, 0x7e7927bc, 0xe927dcfb,
4199 0xc1763177, 0xe3d9e30b, 0x3b7213fb, 0x6617f84f, 0x7593fcbd, 0x5bc6129d,
4200 0x22c47e8c, 0xd3c2f035, 0x3e54af20, 0xda2edf41, 0xbcc196a2, 0xfbdeab3f,
4201 0x9ca90fee, 0x7214167c, 0x469fd7aa, 0xdaff9d39, 0xa34fe47e, 0xdc167e9c,
4202 0x4e50959f, 0x73c7edb7, 0xfa72f1b7, 0x053fab3f, 0xf01bd6fe, 0x5b61f427,
4203 0xc3ea3478, 0x4fc410e1, 0xb7090fa0, 0x13fe46c3, 0xadf8277c, 0xddc595fc,
4204 0xf844ef41, 0x845df052, 0xc5df052f, 0xf0ead1e5, 0x083f3717, 0x589f01a2,
4205 0x75828ed6, 0xf6c5c586, 0xcb39ae13, 0x819693e2, 0x67d6fd6c, 0x43f582ad,
4206 0xb020c726, 0xec4613fb, 0xa427ecfc, 0xbef9fe6d, 0x963e9dcb, 0x65075fa3,
4207 0x895f042f, 0x1090e3a5, 0x16fbd383, 0x7d40f409, 0xf76396e0, 0x930b640b,
4208 0xbd1f9df7, 0x2c780856, 0xca97ee6a, 0xae1babf8, 0xb5fc445b, 0x054cefd5,
4209 0xea1ada7d, 0xad4f7989, 0x4494e507, 0xe25fa5e7, 0xfb857df4, 0x491bcd5b,
4210 0xadf94c95, 0xdfa0b499, 0xc168dfe0, 0xbe38b67c, 0xe67f3330, 0xe803e2bb,
4211 0x2978f80f, 0x5134b1a9, 0xf9f09a3c, 0x5ff3784e, 0x0baf1f68, 0xbf81306d,
4212 0x9346dd7e, 0x24be4fce, 0x1480baf8, 0x784f5f00, 0x20652933, 0x2ecaf3ee,
4213 0x0dee5738, 0x093cd39d, 0xf38c95f2, 0xdfc1fe87, 0xe0716fea, 0xc1a86fb8,
4214 0xdbdcf07b, 0xeb0216e7, 0x6aad3a85, 0x3b382261, 0xeb383125, 0x7cba338e,
4215 0x6a29785f, 0x618b85b6, 0x61237a7f, 0x3a38f671, 0xde0eb613, 0xaa7f704c,
4216 0x7ab32435, 0xa347db35, 0x2462fca0, 0xf699777c, 0xd79f231a, 0x057b6ed4,
4217 0x8455e7ce, 0xb6898724, 0x1a8d2857, 0x36b78bf0, 0x363d064d, 0xcbce29c0,
4218 0x894ffa3b, 0x16febfe1, 0x77b9e705, 0x00331bf8, 0x6acfe72f, 0xddd5f604,
4219 0x60ec5afb, 0x0a87ceef, 0x9adadf91, 0x191f76d7, 0xfee9eb05, 0x78a77f00,
4220 0x4eabf63a, 0x9447d5d6, 0x5c00ba78, 0x4b8dcc13, 0xfef0095d, 0xf7d9858a,
4221 0xdb3e4bef, 0xbf2c3b2b, 0x7afc8587, 0x7c41bf70, 0x378700ff, 0x13b37e46,
4222 0x6592efc9, 0xf7986cce, 0xd99efa92, 0x7f25cf80, 0xe2253b50, 0x963e2dab,
4223 0xee15b4df, 0xadf90017, 0x7d7bf2a1, 0x50d6fc8c, 0xff8bcdf9, 0xfbe5ae6e,
4224 0x202ddf95, 0xfbe009bf, 0x90af9f09, 0x51d0fcdf, 0x1afcdf94, 0x4acef9fd,
4225 0x2bf27b4b, 0xf2c29a75, 0x04d65c60, 0x00f01afa, 0x795bb2f9, 0x038c387e,
4226 0x37c2fc72, 0x24bce394, 0x4a7fef06, 0x20ec978e, 0x4f128798, 0x4bc7266f,
4227 0x4b1ca8ea, 0xc7267740, 0xcb09ea4b, 0x6fc83407, 0x65f9389f, 0xd98457df,
4228 0xbcdadef7, 0xc741dcdf, 0x2eab702b, 0x20bf7d0b, 0x6283cf2a, 0xb685f9e5,
4229 0xc760f9e4, 0x970779e4, 0x3da72a67, 0xeae8095c, 0x63f3e90a, 0xb27618de,
4230 0xe5f03b7a, 0x275c659f, 0x0f79e21d, 0x7276197f, 0x3fc5f020, 0xff8a1e00,
4231 0x9a6f9c3d, 0xbfec7e7c, 0xe853f874, 0xabec9547, 0x03ec35fa, 0x12a8de2e,
4232 0x351587d0, 0x328fd147, 0x5f85bfae, 0x0b875c65, 0x7e5ed23d, 0x776e61cc,
4233 0x088dca26, 0xc65b792f, 0xf38c3ffb, 0xc1c5ef17, 0x5deab079, 0xc042afb8,
4234 0x407c5ed9, 0xb83da3cc, 0x15debcc4, 0x148032f2, 0xe286dc42, 0xffc5e511,
4235 0xb5cf1947, 0xad5d1595, 0x23e51fbb, 0xaac2cf8e, 0x870812a2, 0x37e7e44f,
4236 0xf7bdaee7, 0x18af9c00, 0x0059c474, 0xe188f4ee, 0xa7ac0f66, 0x416a4a5e,
4237 0x49741679, 0xb974624d, 0xa379fbc4, 0xf031654b, 0x7256b79b, 0x86f1dd80,
4238 0xc1f785ff, 0x8bea7dec, 0x05a3e052, 0x8cc392f5, 0x834e787c, 0xb5295e75,
4239 0x854fc0bf, 0x7eb873a1, 0x245f505b, 0xea0bf7c3, 0xa3c0bc24, 0x9474fc3d,
4240 0x0edc296e, 0x6df8016f, 0xb30b6700, 0xd13e1c6b, 0x3afc55ee, 0xbe9e4bf8,
4241 0xc1972ab4, 0x571704ed, 0x02283bc0, 0xe7194cef, 0x057841d5, 0x3783dbde,
4242 0xc74f4935, 0x679e47b7, 0xb4a110fb, 0xbe6bad0e, 0x97887ee9, 0x4cfae034,
4243 0x90cc8bec, 0xac0b663d, 0xf3e97b6f, 0xc1690995, 0xa1efebbc, 0xf5d7ff7f,
4244 0x0037d91f, 0xece41dff, 0xcbae2a4f, 0xb338a497, 0x1df1dce1, 0xb75d2af0,
4245 0xfb336d34, 0xff313de1, 0xabb73e13, 0xc3710297, 0xf19e58b1, 0xf57ab995,
4246 0x4f6fb18a, 0xbe43b79d, 0x821f7357, 0x294d2179, 0xda274e2c, 0x0b3249dd,
4247 0x587e73fa, 0xf57c34a4, 0x1b49f821, 0x5c03061b, 0xbcf32e27, 0xb1e6cb92,
4248 0xd3ddd689, 0xe7109db9, 0x3802ef28, 0x2fb2249d, 0xe59f377a, 0x927e705d,
4249 0xad6667ae, 0xf8852b4b, 0xa0bcf1b2, 0x83403827, 0xde31a438, 0x11b88738,
4250 0xd0f9718f, 0xbf1611e4, 0xeedff034, 0x273b0724, 0x706a54aa, 0x3ac4f65e,
4251 0x8829f889, 0x8f88db0b, 0xf1e24c6f, 0x1fc20ec8, 0x46b1ce77, 0x11b978c2,
4252 0x971b79ee, 0x6042eaad, 0xf15e6cbe, 0xb579b3f0, 0x78d20f35, 0x8bb58923,
4253 0xbcec420b, 0x3223c576, 0xaf3c83b3, 0xe02bc044, 0x2a5dc233, 0xa7ff422f,
4254 0xfa8cad79, 0x607f2ef7, 0xba479c15, 0xfb84a56b, 0x54f9c62e, 0x009cced4,
4255 0xdf43c0fa, 0xf3693887, 0x69ed0447, 0x00296af3, 0xd73f8c78, 0x4bfb66e9,
4256 0x427bbc7c, 0x7e7351f2, 0x1ea2f4db, 0x3665d20e, 0x849acba5, 0xd5c8a3fa,
4257 0x168e462b, 0x7ab9c604, 0xe20bc6e9, 0xe6e17eba, 0xbfe7ba89, 0x74f1e249,
4258 0x4f6fbf1e, 0x6265489e, 0x47e422bd, 0xaf9093c8, 0x817ce0dd, 0x0702519e,
4259 0x4f00f372, 0x1a7ea18f, 0x4c5e7b27, 0x8f217962, 0x54afa74e, 0xe79e753c,
4260 0x0cbc7085, 0x2399f465, 0x6de7c78f, 0x078a31e9, 0xb6c0fedd, 0xe27c7d24,
4261 0xcc47cebb, 0x9881c843, 0x8c0e519f, 0x21e91bdf, 0xba46c0e2, 0x6721e918,
4262 0x7e40fa9b, 0x5d939121, 0xb9cb77e0, 0xe8d7caa6, 0x5a7772b8, 0xcbf703f6,
4263 0x65a4cf25, 0x7928c955, 0xa8572d16, 0x30ad2f4c, 0x1898b8b1, 0x970e5dff,
4264 0xcb923328, 0x3ec1270e, 0x830ddbe3, 0x0c2f2cad, 0x5c7145f7, 0x9215a78a,
4265 0xe83f809b, 0xfed04fdf, 0xbd926417, 0x712b7f80, 0xd6fdc50f, 0x9e3e7124,
4266 0x5fd2e1e5, 0x582e942e, 0x35a70fc7, 0x83473fff, 0x8ab2ecbf, 0x4f5625fa,
4267 0x153de135, 0xab25ffc4, 0xb93af367, 0xa2b9eacc, 0xfc29d69d, 0x7bfceeae,
4268 0xef566ff2, 0xcdffda2b, 0xb45ebfde, 0x21dac57f, 0x7fb69481, 0xa357f0f5,
4269 0xae7f30fd, 0xbbb548c7, 0x62bbf02f, 0xe529eb62, 0xdcf30d4d, 0x15fe3e44,
4270 0x96ab97ce, 0x8562bf15, 0xb762a23c, 0x67c4f213, 0xdf3b73f0, 0x90f414b6,
4271 0xf7bc26ad, 0x9ba04a01, 0xc0e2cc96, 0xc6a49e82, 0xcbce17dd, 0x2fbba091,
4272 0x246635e4, 0xc192927b, 0x61ab7abf, 0xcd47c814, 0x060c1f3b, 0x0ee80bff,
4273 0x05be14fd, 0xfa50da77, 0x436abced, 0x46705e6c, 0x193d9172, 0x6cdd1af2,
4274 0x3a724adf, 0x14051dc8, 0xadf6b80e, 0xf4d68427, 0x8035b2fb, 0xfb0f6a3a,
4275 0xc1659527, 0x986ba478, 0x9cb8fbc5, 0x2e9ecbe4, 0xb8b9bcf0, 0xe061d1f1,
4276 0x7ed89997, 0xef48693b, 0xe5a13f90, 0x74798fdf, 0x47b5b9e9, 0x3e3ee166,
4277 0xdc90cfdb, 0x6e838c6e, 0x24179c8d, 0x25603f98, 0x6fdc2ec9, 0x7f1c9177,
4278 0x307fcf16, 0x1cccbe31, 0xccffb31c, 0x1fbf45e7, 0x870fe70d, 0x375e5958,
4279 0x710ca79d, 0x89c401b8, 0x33e42165, 0xf55604f4, 0x09177d60, 0xed19f91e,
4280 0x7624f1ff, 0x336585ef, 0x4c87e5d1, 0xd876664f, 0x21f9656f, 0x12706ac9,
4281 0x73e4ede8, 0xbb7a01c4, 0xe0a6bd79, 0xf1c50ef9, 0x3c5fcc03, 0xef002260,
4282 0x01c06a8b, 0xd72d7479, 0x48e7ce2a, 0x4e66bfb4, 0xe3efd17f, 0xc85af39a,
4283 0xcad078cb, 0xb1162fea, 0xd396833c, 0x5af2005a, 0x952d73d3, 0x93b3f9b1,
4284 0xf13f9992, 0x78f14a62, 0x3eb043a0, 0x43f8c099, 0xa2065376, 0xbaa579f4,
4285 0x63f80920, 0xe288e02b, 0xb8ecdd21, 0x3f4bfa17, 0xc3cde14f, 0xafc46ee7,
4286 0x4a901ce2, 0x66fc3bf1, 0x47ee139b, 0x7829317a, 0xcb41c833, 0x839e1316,
4287 0x26b9aade, 0xab6b7d42, 0x257901d3, 0x9305e62f, 0x4c5b3e71, 0xc9ad9f38,
4288 0xa12dd72d, 0xa3e9af70, 0x14f8058c, 0xe92c512b, 0xcec54f20, 0x99f3e97b,
4289 0xacaf4cc9, 0x7a793134, 0xf589d93c, 0x7e3a25c7, 0x8457bc01, 0x4fce24f2,
4290 0x75b0b734, 0x0d29a76b, 0xf275f032, 0x25de7144, 0x3c7f832c, 0xbda08cb2,
4291 0x0353691c, 0xb9538c4e, 0xfd29336d, 0x07661147, 0x08b47d46, 0x0528c3f3,
4292 0xfda08f0e, 0x04a9b5ed, 0x1e7845e6, 0x4f9c8de8, 0xb28d206e, 0x70dfb685,
4293 0x74c2b889, 0xe92f1bbc, 0x2ddcbff3, 0x8d14d18e, 0xb62488a4, 0x78f863c7,
4294 0x00adc4c5, 0xf45894ff, 0x7b018def, 0xe318e14c, 0x49339c30, 0x1bb476e6,
4295 0x2e7b16e9, 0x8dede447, 0x853dfb91, 0xcd58c0fe, 0x66d87805, 0xfb07bf73,
4296 0x9506fe7f, 0x46175a24, 0x6a3ed7d6, 0x61537a39, 0x798c94b9, 0x6d1f947b,
4297 0xadd707c0, 0xfdc3f2ad, 0x62f5d787, 0x81df03fd, 0x7d66b95e, 0x87d80666,
4298 0x511f4e02, 0x7e033e0a, 0x7e32a472, 0x951f5c72, 0x79c9f5c7, 0xbe429fc8,
4299 0x9fa0cf80, 0x46606a5d, 0xe50738a2, 0x9fc0f5cf, 0xfd046cdb, 0xb6779fdb,
4300 0x12b9034c, 0xfce31ce3, 0x2d572c6f, 0x8547b25b, 0x76645f79, 0x4b977466,
4301 0x3c8c635a, 0xc1852bfe, 0x4d5675eb, 0x1bf1009e, 0x2dfb8a9b, 0x162e3c59,
4302 0x639d1fcb, 0x59f043f8, 0x51e58d93, 0xa9297e08, 0xbbae2bfb, 0xe2122e4a,
4303 0x3f1123c8, 0x28cbf04f, 0x61f3187f, 0xd7e61147, 0xe8a5f919, 0x7d015382,
4304 0xb4bf1ed4, 0x089027c5, 0xc8d27605, 0xb992072f, 0xbf26d29f, 0x5e03b65c,
4305 0x6497d696, 0xa4fc5d7f, 0x5b47f396, 0x4cacc3ed, 0x5f9f19ef, 0xa8f66148,
4306 0x41faab4e, 0x5b85e83e, 0x7b902e4c, 0x70b90dca, 0x325d513f, 0x95288efb,
4307 0x4dbea13d, 0x5b667a61, 0x667a8cc8, 0xc1e3cd9b, 0x161cd07d, 0xa78a241f,
4308 0x5c9af211, 0x35ce2c5d, 0x0cfcfc31, 0x1aa0bfe7, 0xe212761e, 0x74607f0b,
4309 0x014b7a1f, 0x9d25189c, 0x1fb93367, 0x00db4a78, 0x6c3dcbf7, 0x7c0d3a2d,
4310 0x04b20c95, 0x35c74f79, 0x38ad77dc, 0xdbfea1ae, 0x2950fbb9, 0x9e0afdd8,
4311 0xd76431e7, 0xd062d2a1, 0x37a65627, 0x29fd71cf, 0x4e60c3ea, 0xf70d0fa0,
4312 0x4c230d15, 0x53ddc54f, 0x1f937c04, 0x77bb8f6d, 0x0635d1a8, 0xef771ac8,
4313 0x98f711d0, 0x7bdc2714, 0x797bc1e3, 0xe1efeee2, 0x67bc60fc, 0xc7927fa6,
4314 0xf83f0562, 0x36dd8695, 0xb3276be0, 0xb2ad41c7, 0xa92bcb2f, 0x23fc09ec,
4315 0x147f0ce4, 0xf7bfc15f, 0x7cf62e79, 0xbe7c2dc3, 0xb614b88f, 0x61a8dd3f,
4316 0x082fe81e, 0xedc82efb, 0x1e6b6f52, 0x5f4b0bd3, 0x5d7c019d, 0xf98ddf38,
4317 0xc8a58fb6, 0x2497fcf8, 0x7409e96c, 0xaf182972, 0x92ceaa0a, 0x3df45293,
4318 0x81f594a2, 0x4eaed4b8, 0xfe3085c9, 0xb5cf56c3, 0x5a513f00, 0x4377c20e,
4319 0x82141786, 0x580db65e, 0x4a760199, 0x1ae14dc0, 0x8516c9bb, 0x6595c043,
4320 0xb0f87c65, 0xd6b5e675, 0xd03bec4e, 0x4f47b53b, 0x417be058, 0x39fd60ff,
4321 0x3e18f746, 0xf947ba00, 0xea1bba40, 0xdc050f02, 0xbff2dede, 0x25c60f87,
4322 0x87e103e2, 0x76ecbf51, 0x1ff78fc0, 0x73b37b97, 0x6fcf2c1d, 0x24778c88,
4323 0x9b25f246, 0xb05d8a72, 0xf9d1597f, 0x3e525887, 0xa067ff3a, 0xff766ee7,
4324 0x04e7f0b0, 0x45cbe4df, 0x234bafd8, 0x2e83de78, 0xe21fb0d8, 0x823cc349,
4325 0x63060eed, 0x744fdff3, 0x59282ea3, 0x72674d60, 0x1bb5efc9, 0xefd09610,
4326 0xc715401c, 0x75d7e81d, 0xe2e8bd45, 0x242725f8, 0x03c5ce09, 0x05c95f2b,
4327 0x019c33ff, 0x8f300fe3, 0xed3ec30f, 0xb951d66b, 0xeb029f30, 0x8fc09ec8,
4328 0xfa59f7af, 0xaf693027, 0x7dbf9977, 0x4fea33a3, 0x97b8fd09, 0xbfc62b77,
4329 0xcbf4cadf, 0xcfb66e8d, 0x163d7a0e, 0x801f610e, 0x1487008c, 0x62ba6a9e,
4330 0x6a1dbd45, 0x11be78a4, 0xd8f4a0e0, 0xf01a9123, 0xee4c8a17, 0xfbf012cc,
4331 0x8015853a, 0x5ffeb9b3, 0x340e20dd, 0x23fbf43e, 0x9178ef00, 0xe7d2eb1f,
4332 0x6cfd1ac7, 0xf588ffe1, 0x148ff086, 0x47e1088a, 0x7874fb41, 0xe0e9f14e,
4333 0x0c8de0f7, 0xfefe305b, 0x5af3ab78, 0x85779737, 0x98bc63ce, 0x572be5c7,
4334 0x4cba5246, 0x5a3f3120, 0x0a4a05bf, 0x2483f8ff, 0x82f18c9c, 0xe7f80516,
4335 0x8e449716, 0xadd9f0c5, 0xf875f543, 0xf68aca8d, 0x46fbded7, 0x2242323b,
4336 0xff1f9b5f, 0x3e83cb4d, 0x47f62fb6, 0x18f7db1f, 0x2bf643de, 0xed0db0e0,
4337 0x1c3bf6cc, 0xb5070f0c, 0x73ed76c4, 0x4dc3ef2e, 0xef10f98d, 0x4bebb3dd,
4338 0xee6fa3b4, 0xf05df2fa, 0x569d871b, 0x8767c408, 0x8a981e9f, 0x39a1d271,
4339 0xf442be78, 0xc6b4fdeb, 0xe473d84a, 0xdfff711f, 0x5b8f0a01, 0x582cf803,
4340 0xf1f671be, 0x0bbfa027, 0xdbc615c7, 0xcd52fc7c, 0xebe20bd3, 0xc81efca5,
4341 0xa7f31203, 0x7e01fb44, 0xd6bbdaef, 0x31105e48, 0x3497d2c7, 0xe820bfa0,
4342 0xb1a9cb78, 0x78fc95a7, 0x98efc0ba, 0x39afbfe0, 0x295edccf, 0x714e97f6,
4343 0xefbd91bc, 0x4ddb3ee3, 0xe02af735, 0x2394dfa7, 0xb8cc7713, 0xe2569ce3,
4344 0xfc6b898e, 0x63f06ac3, 0xc4f4bef6, 0xbf8b8804, 0x2f91e325, 0x9fdb686f,
4345 0x20dea1f2, 0x3377dc27, 0xd0a6f5e2, 0xfdf00abd, 0x97931b38, 0x7e1fc6f6,
4346 0xeb8fe51d, 0xf984de81, 0x9425837f, 0xdf5d231f, 0x8cdbf5dc, 0xf8f17ec6,
4347 0x02de8b6e, 0x6f0e82ef, 0x054e2d9c, 0x0747b47c, 0xa6ee9f23, 0x79d3f3f3,
4348 0xfcfce985, 0xd37b4fd4, 0x3efac0e7, 0x05d60e5f, 0x9feb7a7f, 0x4f3f00cf,
4349 0x0c98e5f0, 0xeac327c6, 0xb620c89e, 0xf88c9d28, 0x74636eea, 0xc0e9fc9b,
4350 0x7e3e5414, 0x6ce700d2, 0x536c38ca, 0x57ef1389, 0xbdfcfc24, 0x954dbed1,
4351 0xea0318ef, 0x8cdf68d2, 0x738a6d76, 0xd7c3de26, 0x6384bdde, 0x2052aadf,
4352 0x5954b3dd, 0x80fbb0aa, 0xe02e9f99, 0x6ff3d231, 0x09b6eca4, 0x19f0db52,
4353 0x67071de9, 0x3d353caf, 0x3fc2bc01, 0x4e10f717, 0x78f686f9, 0xd7cf4db8,
4354 0x7e8d4fe7, 0x5b6ad41b, 0x8ba46472, 0x83e85db1, 0x00a01852, 0x23f83f4b,
4355 0x48596ce3, 0x1a4bd2bf, 0xb579c371, 0x93e449ae, 0xc642bb18, 0xba7e4777,
4356 0xb59ec1cf, 0x97154fc5, 0x1193c44c, 0xf6b52be5, 0x55f02b31, 0x8565529d,
4357 0x6c1babfd, 0x52a45713, 0xb4fe8c3c, 0x5bee0a78, 0x84089a35, 0xce84c6c6,
4358 0x813885ed, 0x1c5d5f38, 0x7c0253da, 0xc0694fb8, 0x05f35375, 0xf8c61bea,
4359 0x15a1b599, 0x6ac3f056, 0x0b8c6533, 0xba23481c, 0x6dc7a073, 0x3daaefcc,
4360 0x9dc13ade, 0x0a73bda0, 0xdc4c9f6b, 0x6768f999, 0x51be3053, 0xf384daba,
4361 0xf6b92d1f, 0x321f8267, 0xd9afdd9d, 0x7f643f5c, 0xe9b78526, 0x1fd434ce,
4362 0xba1f6a63, 0x110941d7, 0x3e2177fc, 0xb929996f, 0x95efa39e, 0x2f585d3a,
4363 0xeb879d9d, 0x655f21b8, 0xed0f1e4c, 0xd75c54e3, 0x2917918c, 0x3cfa6f10,
4364 0xf5802a47, 0x71a92ee1, 0xe4fc1999, 0xe21c6c89, 0x7ac067f0, 0x19f19df3,
4365 0xcf20d603, 0x05d5fa88, 0x75ea186b, 0x3ba5b3eb, 0xbf81efce, 0x36f4b04f,
4366 0x8e51cf09, 0x7f12e471, 0xae94ff0c, 0xfea4f4a6, 0x7650a4d7, 0xe4f1f031,
4367 0xc40932b1, 0x656df1f0, 0x5d881256, 0xb1f3f20f, 0xde2af52d, 0xf8e42037,
4368 0x53bfce66, 0xdee865a7, 0x0ede6fa7, 0x886267f6, 0xfcb841c7, 0xd9cb80fc,
4369 0x3bfd7ccd, 0x1bab93dd, 0xbf308cb7, 0x65a4cfe6, 0x671d2a74, 0x960f4a76,
4370 0x70d2d51f, 0xe5f07318, 0xcf4083ae, 0x618fa0fd, 0x5a2f2b3d, 0x2390fc89,
4371 0xb77f00b9, 0xb7edf4b8, 0xe3d7d50e, 0xe8353fee, 0x74e0db81, 0x0faf1c94,
4372 0x56dfdc84, 0xc710ab2f, 0xe288adb9, 0xbd61fd17, 0x5eaede7f, 0x107cecb8,
4373 0x5bef86dc, 0xb2a4ec2f, 0xefca9436, 0xae1fa16e, 0x7e815722, 0x3f572318,
4374 0x4cd2fc01, 0x01399eed, 0x21fb08bf, 0x54a5f3d6, 0xc83f815e, 0xab8c4cd9,
4375 0xe544b98e, 0x9eba2336, 0xea0be88f, 0xf812b84f, 0x7ad81f39, 0x221df6ea,
4376 0xd4fe83fa, 0x9fdddfc1, 0xb550a318, 0x75700052, 0xd442fe25, 0x2c571857,
4377 0x10450385, 0x8739cbdf, 0x42af1b71, 0x5768a7d7, 0x8c7a679f, 0xd2ae0bfe,
4378 0xf46ffc15, 0x789c4433, 0x7ff08a52, 0x89117cf4, 0x31514e17, 0xa1f8238e,
4379 0xf208f014, 0x38c6453d, 0x21fc7b7e, 0xe29fffc6, 0xe3c2920b, 0xaf48bd7f,
4380 0xe083f08e, 0x4617c103, 0x4347f1fb, 0xfb2da75c, 0xf5f29691, 0x1f7f63f6,
4381 0x7b74f515, 0x6764887e, 0x7363d97a, 0xb5f37960, 0x0fc0d9b7, 0x83f5c499,
4382 0xf89143b0, 0x17c65ad4, 0x29671bfb, 0x05e46fb0, 0xc51790bd, 0x0adf88bb,
4383 0x4d58ac3e, 0x9e397e30, 0x7aa6a5eb, 0x8ef3cf16, 0x12900396, 0xec7a1252,
4384 0xf9675609, 0xb79e822e, 0x5228be70, 0xf7f028f6, 0x49756e5f, 0xb913882e,
4385 0x82703c79, 0x6078c25b, 0x7f823e9c, 0xc75bf6d0, 0xd758014a, 0xa093f519,
4386 0x7fde64f7, 0x7df09f1c, 0xdc9f2357, 0xbee5c290, 0x9ffee93b, 0x03c60bf4,
4387 0x4db53b5d, 0x7b7df157, 0xbe0d9d74, 0x5ed9c82d, 0xfe02bf96, 0xa6f5d035,
4388 0x3bf60a4b, 0xe7ef4535, 0xf05b385c, 0xf20b5c4b, 0xaf798df7, 0x37b4f9c6,
4389 0xc7e124fe, 0x8c5ebf73, 0xf2c2b37b, 0xa6768df9, 0xbfc2bb5d, 0x32abd233,
4390 0x26bfb125, 0xde1c6bf4, 0x8b6dfeb9, 0x5fe9ed6e, 0x53feefa1, 0x2bf457fa,
4391 0xcf1882ec, 0x5adb97a8, 0xbb3d09cf, 0xe309836a, 0xf5f03727, 0xae3c0df2,
4392 0xc3f70cfb, 0xdede3c02, 0xf782d17c, 0xb6550653, 0x63dfe53f, 0xd6d038c3,
4393 0xe97fccdd, 0xfbe2756d, 0xc6324a0f, 0x641c1e29, 0xd74c3d42, 0x3f308526,
4394 0x3e9098a5, 0x85dacfb0, 0x2b56b3ed, 0xe3d432e1, 0x7e40852e, 0xf1959e54,
4395 0xfa6f83c1, 0x0fff4067, 0x5a6deb1e, 0x70e37181, 0x4331f803, 0xa7dc140a,
4396 0x313b334a, 0x6f54dcce, 0xe6aabcc6, 0x03daffba, 0xf9aa277f, 0xf2c17122,
4397 0x39bd5f66, 0x7a044fb2, 0x96fc8c62, 0xcd11790c, 0x0ef3042d, 0x970b4e47,
4398 0x06e97ac0, 0xd602b0d2, 0x7635c3e1, 0xa788dd8e, 0xc6de7ca3, 0xbec8847d,
4399 0x1bcb3d41, 0x79e14929, 0x06fb7123, 0x6fb8250d, 0x15ae48a0, 0xd33ed124,
4400 0x60df667f, 0xf29ce038, 0x7a0c5ff3, 0x7fb1b488, 0xfb6355b0, 0x54872d4c,
4401 0x39327e02, 0x5e309995, 0x423eded3, 0xb764eedd, 0x82fb0ed3, 0xdbaf9fcc,
4402 0xccedc5dd, 0xfcfdfb6f, 0x986296c6, 0xd36ad6c6, 0x47632b4a, 0xe246bb8c,
4403 0x727c4671, 0xbfedc7bc, 0x61a35c84, 0x63c462dd, 0xe2194b71, 0x4fe29bf7,
4404 0x13d6c5c8, 0xebe06ec9, 0xb8ba27ad, 0x3c63dc61, 0x3b32e70e, 0xbf7604fe,
4405 0x326b78ee, 0x6e6ab3ee, 0x5a1bac27, 0x762e2cd2, 0xf3e3110f, 0x78dee760,
4406 0x3c07fc6f, 0xb935b7ae, 0x337d8fe5, 0xd851f763, 0xc51349be, 0x0faa3eeb,
4407 0x3cfd5f7f, 0xfe7e03e6, 0x13cc51f2, 0x4c86f85a, 0xadaf102c, 0x85e7e14e,
4408 0x03f81a03, 0xee3235e5, 0x18b9534f, 0x5625393c, 0x7960acdf, 0x3dd95b34,
4409 0x99afe59f, 0xf7e9e303, 0x927fafe5, 0x4df6f90f, 0xc00e5bcb, 0xbff01fdf,
4410 0x33bfb12c, 0x87cc6fe7, 0x95cb9afb, 0x2eb271c4, 0x9d7fe676, 0x034eb3ad,
4411 0xccda40ff, 0x79605efe, 0x8e6aaa70, 0xd9a5ef59, 0xd31ef155, 0xec492f0b,
4412 0x5f0a097e, 0xe2bf7dec, 0x7d9c06ef, 0xd5f06249, 0xbbf801aa, 0xb79be583,
4413 0xbe39c135, 0x5c6623f2, 0x9f3779bf, 0x4b33fbc3, 0xfcc16eb6, 0x4cad6f60,
4414 0x09d619f6, 0x9b53f3ba, 0x45e430e5, 0xbfb0d455, 0x98eb4023, 0x4c115527,
4415 0xbdb08e7c, 0xb70b3e73, 0x87eebfd6, 0x2feda83c, 0x9dbec1da, 0x0764d869,
4416 0xbf7ed3bc, 0xdc62fcf6, 0xc3e0a979, 0xea5e7b5f, 0x5a72610c, 0x379c3762,
4417 0x37c19cdb, 0x6383c223, 0x78a3faf3, 0x70b9fc64, 0xe067c5cb, 0xd7d9ef3c,
4418 0xe0067b3e, 0xf9d5f45d, 0x0d7f6067, 0xbd60f512, 0x6ff97dea, 0x7c521e78,
4419 0xdff72777, 0x117a5e9a, 0xbd3691cf, 0x6f41766f, 0xbb27f54d, 0xa6ca79c1,
4420 0x82caff6d, 0xfad2deb8, 0x2e77e831, 0xcffd41dd, 0xa2bafb04, 0x83e8326c,
4421 0x1ab1ceb6, 0x66b7b5e9, 0xf380376f, 0xf06f4a73, 0xdfe7237b, 0x2ecf2c82,
4422 0x3aadee72, 0xb8e179f1, 0x93356e73, 0x2061bd6f, 0xd40baa94, 0xdde7bb46,
4423 0x5e3a530e, 0x55fa01df, 0xeaf3cc3f, 0x73efd312, 0xd3a507f8, 0xf3faeccf,
4424 0xe66b17e6, 0xb434fb3c, 0x79b464d5, 0x01dc2dde, 0xc8f389bc, 0x55eeed63,
4425 0xd79b9076, 0x85f3c15e, 0x74f1b740, 0x2e5b4da2, 0xdc738376, 0xbb96d4a7,
4426 0xda836f30, 0x940b8843, 0xf287bfd7, 0x10e3b4d3, 0x3f0969c6, 0x2244dc17,
4427 0x538e763f, 0x98dcf3e2, 0x71c9cec2, 0x3a39c3fc, 0x39f4e3d0, 0xf8c72f3f,
4428 0x6ba39c58, 0xbd5cfceb, 0xefbf07bd, 0x77bb13ba, 0x1a87e378, 0x4a20dfbb,
4429 0x3468692f, 0x3a2dbd0f, 0x00383c09, 0xcf62430f, 0xa73e2683, 0xcc373918,
4430 0x03f405e9, 0xde722fff, 0x6247d693, 0x248f7a5d, 0x1b4d07d0, 0x26d239d8,
4431 0xf53df135, 0xad687ce2, 0x9e62ce81, 0x9087c96d, 0xffe0f6d3, 0xc979f8a6,
4432 0x8bf1d4ee, 0xcbd9d3c0, 0x87f8f589, 0xddbbe976, 0x8c96e36b, 0x607cdaf7,
4433 0xd3f704ef, 0x98f9e51e, 0xcc5acf2c, 0x96f82cf7, 0xbecf4f94, 0x17fde32c,
4434 0x517b82ab, 0x85f51b8f, 0xc23597d8, 0xb78739fb, 0x89d996a2, 0x04a5afb3,
4435 0xb39fb46c, 0x3f21d66f, 0xd51f5457, 0xc0ef8f20, 0x8b1aede6, 0x01f933d7,
4436 0xc71b113b, 0x9eeafb3a, 0x24dbd47c, 0x97f27e71, 0x437a1f5c, 0x56f1c789,
4437 0xb38dd39f, 0xfbc41fd0, 0xef1bdab1, 0x0a9ee28c, 0x50699dfd, 0x4cfa3f31,
4438 0x8d41c590, 0xedcc7fe3, 0x203ee466, 0xcf412f6a, 0x5768fb88, 0x3cf30468,
4439 0xe79626fd, 0x6a7efc69, 0x00d3c32a, 0xee04b387, 0x82d9750b, 0x52b8b9b8,
4440 0xd4cdc32e, 0x6c7b9115, 0xf6f7f85c, 0xe4977922, 0x2f309b91, 0x925de452,
4441 0x50bd5927, 0x613703d4, 0xfe10e51e, 0xdac03fbe, 0xeb4c2161, 0xecf97eb3,
4442 0x2c7efe4d, 0x3320b26f, 0x9cffcfea, 0x829630fa, 0xd5a67ee8, 0xa049fc4c,
4443 0x3ebdf82f, 0x22b27f22, 0x3575e449, 0x9ef7f3b2, 0xfa5f9d6c, 0x77a7bb47,
4444 0x5b73ec2a, 0x552776c2, 0xc6eb4b29, 0x4e2a1da0, 0xfabe2075, 0x03911f6e,
4445 0xc1ffc1fb, 0x76a707f1, 0xa57f1f8a, 0x6ab7faca, 0xe074dfb4, 0x4025be97,
4446 0x09ddbee7, 0x831773e6, 0xa3bf4a13, 0x9e7c14cb, 0xfec1c944, 0x073b995e,
4447 0xd22b1fe2, 0x2c63cc34, 0xdd00b0a6, 0x5e5c658c, 0x72a9aa68, 0xa5c72d1b,
4448 0xcdc875b2, 0x1ebe4ea9, 0x277f6169, 0xffc2d1cc, 0xe7db184e, 0x9682e597,
4449 0xe981d830, 0xecbfcc29, 0xdc31f2da, 0xb4eef1ff, 0x37582ebe, 0x7a4c0d4d,
4450 0x21b7e610, 0xf00933d5, 0xeeb4befb, 0x9b5f946a, 0x34fc0527, 0xfcb1ddc9,
4451 0x8871f8d0, 0xdbf4fc05, 0x61057187, 0xbc18f763, 0xe955943b, 0xa7c01e78,
4452 0xae323f18, 0x03d8bf21, 0x13883d71, 0xf11efbf1, 0xce3a7afe, 0xcc26e3f6,
4453 0xb64a6f8f, 0x59b47bf3, 0x00b608dc, 0x3fc7def0, 0xbef9972f, 0x5f775f96,
4454 0xa7bb2d5c, 0xb89eee3e, 0x08129e83, 0x8bef1839, 0x3b37de33, 0x4f300494,
4455 0xdc7f78d4, 0x307ebe08, 0x40f71bde, 0x5d0fb72a, 0xbddd1748, 0x5fd616db,
4456 0xf03d5beb, 0x09dc1b9c, 0x6b3c5325, 0x4d0c994e, 0x0d73ca8f, 0x3e708fd5,
4457 0x4e7e75f8, 0xc761ffb8, 0x2d7f003d, 0x79435fdc, 0x1dfc177b, 0x072a2d13,
4458 0xbb930ffd, 0xb9a75ec1, 0xacd4ff99, 0xd3cb7bb2, 0xbf4058e8, 0xc98fb834,
4459 0x89c4fa0e, 0x9bfe1b79, 0x3c7bee09, 0xa0499729, 0x92e9721f, 0x5c47ee1b,
4460 0x3dc7cfc9, 0xf6e9326a, 0xca9d7e61, 0xf96fe3f4, 0xefb1633d, 0xb7a04a4d,
4461 0xeb654d9f, 0x552cdb85, 0x9f198557, 0x9f740b3d, 0x70a8f26e, 0x599a9b4f,
4462 0x331c42a9, 0xce4fca35, 0x13e2092b, 0xeecedfef, 0xab5f7f4b, 0x81ebf39a,
4463 0xef66f3d1, 0xc7814600, 0x6fb8e92c, 0xbee38d3b, 0x4d4ce9d5, 0xd5a7818b,
4464 0x99dbe426, 0xeadb720a, 0x91e589e9, 0x1f719a1f, 0xcfa688e9, 0x02f71783,
4465 0xc480fb89, 0x7da2417d, 0x291586fe, 0xe91f1fe0, 0x74e77443, 0xd2ff5c42,
4466 0xf9039ef5, 0xf3a3047f, 0xa67f73fb, 0xff15dfc2, 0x82f48fab, 0xc5f187bf,
4467 0x4cdd73f4, 0x73cddf14, 0xd7f8b9ff, 0x79a3ddb4, 0xdcbc04de, 0x1578db9d,
4468 0x531dd7c8, 0x4dfa41ce, 0xf9bf7cdc, 0x9e3f653c, 0x61250ecb, 0xef3bc23c,
4469 0x4f180acb, 0xe6f687e8, 0x1d972f9b, 0x2a70bd06, 0x8bde09f0, 0xf626c646,
4470 0x8dfe8d5f, 0xe71773e0, 0x0db231f3, 0x493356ed, 0x5cac7966, 0x73ee636e,
4471 0xb37ee273, 0xe209fc9b, 0x98f62b3a, 0xd99fec08, 0xe1778941, 0x87754882,
4472 0x8af6165d, 0xf5942db8, 0xda1fcd21, 0xb95ea54f, 0x17c42569, 0xc8682fe0,
4473 0xfa80faf1, 0x56296e2b, 0x4f2bec0f, 0x79d607ac, 0x5a96c056, 0x58607a7b,
4474 0xdb7e84d8, 0x5f07d537, 0xe281f419, 0x82be2270, 0x605033e0, 0xc43e1fff,
4475 0x8000938b, 0x00008000, 0x00088b1f, 0x00000000, 0x59edff00, 0xe554707b,
4476 0xef773f15, 0xc3cdddde, 0x210366e4, 0x804d8404, 0x85701020, 0x5c7c0188,
4477 0x94422101, 0xd6da0300, 0x02101ba9, 0x16a52d79, 0x9b8cea9d, 0x8e233480,
4478 0xd29dad13, 0x542cce96, 0x2ec4952a, 0x4dd0689a, 0xd15c04ba, 0x63e02711,
4479 0xb46d63a0, 0xec083a2d, 0x98f8a71a, 0xe739ec76, 0x647dd7bb, 0xeffa7471,
4480 0xe5f98617, 0x7cebdfbb, 0xe3cefce7, 0x648a12fb, 0x40a50307, 0x676a733f,
4481 0xf1d31c02, 0xee016bb7, 0x0d1c442a, 0x00f250e0, 0x007f73e6, 0xd63c03c6,
4482 0xe9b6dc06, 0xdb007b5a, 0x2ed8c9ae, 0x95d6c801, 0xfc76edf6, 0x06dbb8fd,
4483 0xbab60173, 0xc00f77f0, 0xf9e9b1f0, 0xffbf8150, 0xbe956be7, 0x16bcea57,
4484 0x373f4d7c, 0xb772b025, 0xecf7000d, 0xb5ddc372, 0x9d701e34, 0x913ac4a2,
4485 0x46383668, 0x9dbac401, 0xef289d7b, 0xb1b0b870, 0xddc3db13, 0x5a64d759,
4486 0x1e17c2cf, 0x40074ec2, 0xf3e36e8d, 0x91bdb05c, 0x35eb8157, 0x87973cf5,
4487 0x33c685c7, 0xd752e6a7, 0x64df0e9b, 0x4e7dcf1d, 0x9aee5bd9, 0xc1ed1d84,
4488 0x508fa459, 0x87df2ca4, 0x43b4ccf2, 0xe47b3ec0, 0xf8ddfefa, 0xcb400e71,
4489 0xcce3376e, 0x987a9cf0, 0xe223df85, 0x8687b43c, 0x817ad35d, 0xb77b17db,
4490 0xff3d69bb, 0x7c4afa5f, 0x470700b9, 0xc4219dc3, 0x2e98be67, 0x4ec1dbe6,
4491 0x05e9e7e3, 0xd0402f2c, 0x39170ab6, 0x9c38e1a8, 0x1b0bf177, 0x9ff6b38f,
4492 0xaab37bd9, 0x222a89a3, 0xfa80031d, 0x3d3b0ac8, 0xa7accf64, 0x676e1400,
4493 0xfdc14105, 0x528297fa, 0x002bfa89, 0x5dfd82af, 0x01f7f1d9, 0xa73ef1db,
4494 0x67f61f67, 0xc6e01de9, 0x421cbbf5, 0x8c00d3ff, 0xdf1372e7, 0xc2b2fdad,
4495 0x65c806bf, 0xea411bbb, 0x0dc077b7, 0x9b7e89b9, 0xfdcb057e, 0xa7f05d43,
4496 0xcb623b2b, 0x53e23945, 0x5cb1f600, 0xf7813909, 0x169ce4b5, 0x7fb4280c,
4497 0xa303ecfc, 0x9f7d2e58, 0x7210e487, 0x67aa7842, 0x0dd7cd3f, 0xee96473e,
4498 0x74f8d2f1, 0x20b3fcb9, 0x9e09f908, 0x55018fe2, 0xd13b3df8, 0xfb855d76,
4499 0x42de0994, 0xe2fb7660, 0xc4da93eb, 0x7cc4aaf3, 0xfb6d7ebf, 0x1db9e40e,
4500 0xa9a2afed, 0x70af1073, 0x7c3d39d3, 0x31bca43e, 0x83d0b67a, 0xe394f517,
4501 0x8cdffd12, 0x52e6fe47, 0xf38c573b, 0x659cf53a, 0x400feca5, 0x8202d0fe,
4502 0x912af7df, 0x00a937b3, 0xcdaf1fe7, 0x9d73c0af, 0xeb6c0db7, 0xd49f71c4,
4503 0xd823ca85, 0xfdf3ceae, 0x5efdc75c, 0xaedd6f7c, 0x739fa899, 0x06b79a5d,
4504 0xe050c1e7, 0x8fa87189, 0xcf346786, 0x007e4923, 0xc445e3e3, 0xfc7df4df,
4505 0x189eda67, 0x58747e47, 0x1db0b8f1, 0x4813e2d3, 0x47f096ee, 0x7978830e,
4506 0x078703f8, 0xf81715e7, 0x543f9276, 0x222eb6f5, 0x8e83cebd, 0x0ce23aed,
4507 0xaf88f81b, 0x0f5c62a1, 0xbb7e1df7, 0x926b5f7c, 0x85753a1d, 0x7dc407e3,
4508 0x0a916b13, 0xfaffd361, 0xf631721f, 0x24c1f91c, 0x1347bf5a, 0xb5e6b33c,
4509 0xd238c0c2, 0x631c1b7b, 0x82c7beb4, 0xd9e26af6, 0x775d778c, 0x9fe3491b,
4510 0x69f9fd36, 0x41710fda, 0xc90f6f81, 0x43e478db, 0xf39d1e47, 0x8009a19f,
4511 0x4f764243, 0xf97b9ebe, 0xf34fe0f8, 0xee3dbf27, 0x8ffef1a0, 0x7415df91,
4512 0x079f0f1e, 0x1f23beed, 0xddf078ed, 0xd875e9de, 0xfc2a53df, 0x1dab47b1,
4513 0xdf5be347, 0x086b34b9, 0x123231f1, 0xd7d4bf8e, 0x86f49138, 0x4d985ffc,
4514 0xf908767e, 0x69f849ef, 0x8a29f905, 0xaffc415e, 0x8e34f6a4, 0xc18e5dc3,
4515 0x3d97ec65, 0x44bf2036, 0x203fb3fe, 0x40fdf5ff, 0x781fd1e3, 0xf3f654fe,
4516 0x419b41ae, 0xf1c600ed, 0xb85edc29, 0x835dda9a, 0x73f6758b, 0x3679f21b,
4517 0x80646bf9, 0x4c0109d7, 0x5029d321, 0xf648aa1b, 0xa3d63cdb, 0xdba7d4cd,
4518 0x55d0dff4, 0x9e2f7c9e, 0x53554723, 0xb54f23fc, 0xb502f225, 0x3fdc2bb7,
4519 0xed0df1e6, 0xc13fa24f, 0x740799a0, 0x2d383bc1, 0x5d4ff9e2, 0x7d6ffe22,
4520 0x4e8afe65, 0x13d6e73c, 0x13f7f72a, 0xce31ca4f, 0x78193c9b, 0xe536e748,
4521 0xe7da0f05, 0xfcc543d8, 0x1b6c5afd, 0x1ae74718, 0xba51165b, 0x38eeaaa9,
4522 0x36bf384a, 0xbc4348b4, 0xa3c1cefe, 0x19f3709a, 0x81eebfc4, 0x29d8675b,
4523 0x42719dee, 0xfdd88a16, 0x67fdfc55, 0xfadb0f50, 0xf219ff51, 0xf9871e06,
4524 0x0e3b5007, 0xc7f6478a, 0xdc8e2b14, 0xbc7c4d5f, 0xda26add8, 0x120b4828,
4525 0xf417da9b, 0x6c01ed6d, 0xc46057df, 0x71bf9789, 0x8d44e2fb, 0x8aafc9d8,
4526 0xde7b2dc8, 0xe28f30fe, 0x98c3b77f, 0x2ee9fc41, 0x0ca14d83, 0xd74f7d3c,
4527 0x4e954f98, 0xdfa992d8, 0xa0fc205d, 0x88bb003c, 0xaadd2d47, 0x5fbb441e,
4528 0xc70d56e8, 0x431f00d5, 0x8a02ed60, 0xb0630137, 0x01bff518, 0xc8031fac,
4529 0xa6894d1e, 0x68daf641, 0x6b1c3736, 0xd63ca1a8, 0x20e83ea4, 0xa4f8da3f,
4530 0x55d0e1f6, 0xffc6ee66, 0x27686153, 0x53ff11c5, 0xed82378a, 0xfb527b4d,
4531 0x7887c21b, 0xa953c35e, 0xb13a9bdf, 0xddb44aed, 0x3a8c5705, 0x997f033b,
4532 0x42b09304, 0x5c711e20, 0xdc70ecd0, 0xd97dbc89, 0x6f4953ed, 0x3f426d07,
4533 0x0fd94f18, 0x2cbf2b55, 0x7e287114, 0x2fec8201, 0xf3474207, 0x9df9ae50,
4534 0x63da5ea5, 0xcff45dbe, 0xfce52def, 0xbaa0f602, 0x65500d12, 0xde9096f8,
4535 0x176f2f51, 0x9937b9e3, 0xfc7411f1, 0xa6cded87, 0x1e91361e, 0x073635d0,
4536 0x079ee553, 0x4fb4edc1, 0x3f3c01fd, 0x903c6bce, 0xd7e96fda, 0xb4d3ae6f,
4537 0x2c7464fb, 0x75287362, 0xfd1e1f9c, 0xa17aa554, 0x73fbf537, 0x5cc09bc0,
4538 0x60133f4b, 0xeb07e902, 0x97b1802b, 0x8ee4678f, 0x344f97a4, 0x329c5751,
4539 0xd7fab1d7, 0x41697c9a, 0x344e28f1, 0xf120d505, 0xc8129365, 0xcfb79503,
4540 0xd7b943ad, 0xe0f0bc5b, 0x3dc7d43f, 0x9bd67ea6, 0xe173e0bc, 0x4a3de6fc,
4541 0xeff38230, 0xfe553479, 0x25baa10d, 0x79233ce3, 0xab53a9b3, 0x6e7e6073,
4542 0xb40e2d80, 0x98de48f9, 0x70e800fa, 0xe74afe50, 0xb94f8b4f, 0x6e46dc8c,
4543 0x5fffdcdd, 0xe22d46ee, 0xf8da7ca0, 0x201bc52b, 0xe27fbbf9, 0xe791b280,
4544 0x60dbecb0, 0xd73cc4f1, 0x56cf3df7, 0x61d3becb, 0xbab7db3a, 0x37d93bf0,
4545 0x6f463ebd, 0xc618ff63, 0x9150577c, 0xfcfa4fe0, 0xbd9d6625, 0x5e303774,
4546 0xcf2cfde8, 0x8362f383, 0x68c079c3, 0x47bca6ab, 0xf149c9ed, 0xcec0ada6,
4547 0xfe2ceefb, 0x500b63c7, 0x690f4b3f, 0xa0e0ac5e, 0x96ad4ae9, 0x95d373f2,
4548 0x4e4d14af, 0xe6ed27ca, 0x3687a5f8, 0x9c5165b4, 0x25e293f8, 0x7f858bf7,
4549 0x40ed4036, 0x829de2a7, 0xc383a3f3, 0x7b202e6f, 0xa5cce714, 0xb77dfcf5,
4550 0x76c2e8cc, 0xaf1cdf74, 0x17ac49ea, 0x2df38b75, 0x7ce352bd, 0xe724be79,
4551 0xbf68350f, 0xfb2f6306, 0x9e97f9f1, 0xc79f9077, 0xc62814ba, 0x47c5a28d,
4552 0xbea00d9f, 0xd270bfcf, 0xa2f84541, 0xa18e93ee, 0x2e03a96f, 0x50885504,
4553 0x3877b03c, 0xdb52bee8, 0x10c72ff3, 0x7d4f45d5, 0x34bd20e0, 0x471c2af4,
4554 0x41a8f61a, 0xb47afe0f, 0xf10745ef, 0x8153a5a8, 0xfdc9a531, 0xe663f71a,
4555 0xc23e7964, 0x092adffe, 0xf933ae7e, 0xe2d3f168, 0xce333aeb, 0xe54f6fac,
4556 0x763046e3, 0x0dfce096, 0x4f1c759d, 0x8e647437, 0xaabc5633, 0x28ead88f,
4557 0x4eefd7ee, 0x1bf9b71d, 0x941c061e, 0xd9e3d317, 0xd3878b51, 0x70f11a60,
4558 0xa26eb238, 0xe97f791d, 0xa844c364, 0x37afa918, 0xe56d7ccc, 0xf5e9cbcb,
4559 0x0e67ef62, 0xf1fe73ca, 0xfc17df1a, 0x48edffe3, 0xe209c9e6, 0x25b7e609,
4560 0x3ed94fe1, 0x8b23e135, 0xc0dbbf69, 0xbdfa44d7, 0x53a39c2d, 0x24335bfd,
4561 0xd85976fc, 0x242a0c19, 0xdbf38d9f, 0x41da106d, 0x3bf58ff6, 0x92f03fb9,
4562 0x981075c2, 0xd4deac71, 0xdfa9bd77, 0x8d5fbc7a, 0x30f54d9b, 0xfae283ea,
4563 0x6ea37b55, 0xbf316fec, 0x3476bd37, 0x0cbcf48f, 0x16599c44, 0xb2c67112,
4564 0xd2279597, 0xd0331cfd, 0x8ddec98f, 0x823c2761, 0x719b97e3, 0xc6277966,
4565 0xdfa46519, 0x30e6c6c7, 0x423d025f, 0xd8bcf4de, 0xfe3a9dd2, 0x2ba8814c,
4566 0xf67acd87, 0xd57b34cb, 0x02a721c4, 0x51e65bd7, 0x359e41bd, 0x8ffda768,
4567 0xe1fe42cf, 0x933dc7fa, 0x397b1ef8, 0xd669bd3b, 0x057b56e9, 0xc3ea8b12,
4568 0x5b91de90, 0xf737e490, 0x3921d860, 0x01a9e61a, 0xbdd27fd2, 0xd2ecc565,
4569 0xdd16f78c, 0x1d5fe38d, 0x6bd1febf, 0xc62def92, 0xe1e272de, 0x597f8a2f,
4570 0x43e29b33, 0x172788a7, 0x7cdd70ab, 0xeb81c3aa, 0x33a77f5a, 0x3f0bf748,
4571 0xadea88f2, 0xf213c4a5, 0x0b72b0cf, 0xfeeb04f1, 0x4afeb4f1, 0xe146192c,
4572 0x8af657f9, 0xe2e5647a, 0xaf77994f, 0x46e7164d, 0x74c98dbd, 0xffeab00f,
4573 0x9d442f96, 0xb16f7d69, 0xa03df10f, 0x6f30ac25, 0x9cbe07bb, 0xc6f28a50,
4574 0x509f3efa, 0x16eb5887, 0x54f5b479, 0x797d5036, 0xa0ceaff1, 0x74bce513,
4575 0x1f0fe5f8, 0x2ea5f6c0, 0xf2e63117, 0xc1d95c71, 0x0da2d37e, 0x721d7115,
4576 0xebbceb18, 0x7c73bd68, 0xc81ee88f, 0xbc40dbba, 0x5137ceb8, 0xb5bb16ff,
4577 0xa9d71b42, 0x9183b06d, 0x3ae499ea, 0xcac75eae, 0x8d864b14, 0x566bfe66,
4578 0x7bc42373, 0x57346e2b, 0x883dc625, 0x6b88dffc, 0x533b38dc, 0x5cec08fc,
4579 0x1b8c8ca0, 0x777b158d, 0xfd5321ba, 0x977ce113, 0xe3dcef5e, 0x24e6de46,
4580 0x1e2a1b78, 0xde84b67a, 0xa13b4e71, 0xffce94b5, 0xafb204d5, 0x9ceb7e75,
4581 0x9e7e4ce7, 0xc601fba7, 0x952ad69d, 0x279b65f5, 0x708baad0, 0x7626f31e,
4582 0xf5483732, 0x17fe8cfe, 0x8d0788cb, 0xb25c7007, 0x7d1da1ff, 0x90438854,
4583 0x421cdcf9, 0x3ce492a1, 0x74e2ffd8, 0x97d91be2, 0xa6fc9dde, 0xb2e5d37d,
4584 0xfdc45150, 0xfb88a6d5, 0x287d8f6b, 0xfe4dee8f, 0x306d6ac3, 0xfcd67ec9,
4585 0x80fe4d7b, 0xefd3dc5d, 0x7c4420a7, 0xd81e0b0a, 0xef2204fa, 0x1a778ad6,
4586 0x334aca0d, 0x7e442ff4, 0x035e4b7c, 0xea6d0b92, 0x33cce2d7, 0xcb1b49ff,
4587 0x5c393fe3, 0x03df9c94, 0x8a18eeb4, 0xc04dad7b, 0x28072471, 0x0b1c62ce,
4588 0xf97b63e4, 0x97ae2ce9, 0x6abb65a2, 0xa9956e38, 0x5b6b7140, 0xc9a9e6ff,
4589 0x05bfe1f9, 0xe91738aa, 0x95aa98a1, 0xa6fec527, 0x9560da1e, 0xbc17cf79,
4590 0x7888140d, 0x27a3f782, 0x47ee19dd, 0x6ddeb5df, 0x3d8273ed, 0xfa974ec9,
4591 0x0dfef9ea, 0x52a6f85f, 0xef9f019c, 0xfd6dc26a, 0xfbe953f5, 0x57cdfea5,
4592 0xd2a4bbf3, 0x02bf9296, 0xd5315f24, 0x7914ef45, 0xefb9bfb0, 0xd460229d,
4593 0x276a7e58, 0x6efdafe7, 0x8ec4e751, 0x84fbf164, 0x07826502, 0xdd653930,
4594 0xb857eea6, 0x55ea688e, 0x583e648d, 0x22dc7af3, 0x1e261e0f, 0x1486b620,
4595 0x487ced83, 0xf3ef5360, 0x16a34f2c, 0x76b63b62, 0x4bbfa26a, 0x3c97d620,
4596 0x00ee002f, 0x39feafc9, 0x52754c3c, 0x87964f73, 0x3eb14bde, 0xc4b1f914,
4597 0xfa8fdc19, 0x99c2f459, 0xcd5b8a22, 0xf50a682f, 0xbbea50c3, 0x679b736d,
4598 0xbde88fc5, 0xe81575e0, 0xda55e1dd, 0xc4b0ed02, 0x4d54d181, 0x1d66efca,
4599 0x5f9bb560, 0xc8d4abaa, 0xcb06dbef, 0xe6ce512b, 0x3b4abafe, 0x78b4f419,
4600 0xb634ba0f, 0x3009eb91, 0x95b65d84, 0x27f0a634, 0xf7290300, 0xb14e506e,
4601 0x8d61631e, 0x03a281df, 0xfde9ca67, 0x6fe4b9a8, 0x7347e4e5, 0x537bc50a,
4602 0x554bbd33, 0x7de27c90, 0x4d7f9aca, 0xafb3f0a1, 0x0b7b7f4d, 0x7bcda3bc,
4603 0x9e1b2ece, 0x4d1aadff, 0x05eb847f, 0x6edd9f51, 0xb7d5cdc6, 0xbc5f5c69,
4604 0xc78d1e05, 0xcca18a1b, 0xfac8bce5, 0xa78cddb9, 0xe352aa2b, 0xf03dcadb,
4605 0x91a11670, 0x635b4eb9, 0x0c0abfae, 0x7575775e, 0x6635b8ea, 0x36a6b69d,
4606 0x56e7fbf5, 0x930c9cdc, 0xc2ea6e39, 0x66c75b9e, 0xb90c7e71, 0x0cdef93c,
4607 0xb475e279, 0xf541c78f, 0x683c0b9a, 0x1c66e3a7, 0x01c92b6d, 0x177e28f7,
4608 0xa3fd9209, 0x53bfbed9, 0x719f8ade, 0x34553bf2, 0x1565ce2d, 0x29cd3f0a,
4609 0x514a7114, 0x9b276ca2, 0xa3ed9c72, 0xed9baf28, 0xe7ec5237, 0x533bc4d7,
4610 0xfc937914, 0xacc27c8e, 0x788aa223, 0x7b974b47, 0x8778a17c, 0x34dfa11a,
4611 0x5fd08ebd, 0x36a2de9a, 0x6ec5c751, 0x5ffef856, 0xc519f58e, 0x958bb5af,
4612 0x14f141a0, 0x2bfdc0f5, 0x54c3d615, 0x62704f88, 0x8f981dff, 0x4d8beea8,
4613 0xb6fd7513, 0xefe2f9b5, 0x9b780124, 0x64f168ec, 0x57e45d85, 0x286b0f8b,
4614 0xdf12cebf, 0x6ede9f29, 0x7755d3e6, 0x850af35e, 0xadaf4b45, 0x2f9ca7e4,
4615 0xb1463146, 0x475e20be, 0x53c7eafb, 0x917d23dc, 0xf32f479f, 0xadc2742e,
4616 0xa72e7eb1, 0x2fd36abf, 0xa839476e, 0x7adefdae, 0xeba5e734, 0x9530bab3,
4617 0x2b581887, 0xf2138fc8, 0xc7e6333b, 0x943ca6d5, 0x47e80363, 0xedfd4d6b,
4618 0x2eadf7cd, 0x0477efc4, 0x7e4c3d57, 0xb3d94675, 0xce2410ff, 0x9d187a4d,
4619 0x85addeb4, 0x090c3de2, 0x9b7ef192, 0x16f0179e, 0xd7b8e016, 0x54af718f,
4620 0x241777bc, 0x933eebe9, 0xb161d7d7, 0x079c764a, 0x25de9501, 0xdc3b03ae,
4621 0x443b6d45, 0x200b88ec, 0xfe81dfc2, 0x4fc45608, 0x9d73fcea, 0x9944723d,
4622 0xeff8e3c5, 0x9061f343, 0x7108ddc7, 0x3b740346, 0x32f042e1, 0xcb22b956,
4623 0x08af6ca9, 0x4baa5485, 0x82f64523, 0x5213a8b3, 0x2473a665, 0xb38763ce,
4624 0xd2a2fd56, 0x0b6011df, 0x3cfd3dd9, 0x0c79d61d, 0x0d4a4bc1, 0x555ca177,
4625 0x93695210, 0x1548601b, 0x39f32ff1, 0x4ddd6016, 0x01b8b77f, 0xfacd9fed,
4626 0xebf8f208, 0xa66a3ce9, 0xaf2d0cf3, 0xeb1615e0, 0x29129f24, 0xf39d7db2,
4627 0x2b11cfdd, 0x6f375e02, 0x03e2fc7d, 0xfbbf8995, 0x9eafc378, 0x2a3d3fa6,
4628 0xd3f70186, 0x665c4ddf, 0x9fb11add, 0x788f86ff, 0xe17dfd3f, 0x5215dfba,
4629 0x7ce8f23c, 0x8781f04e, 0xf60638f8, 0xb23f74e8, 0x7142b8d1, 0x128b8fdc,
4630 0x5c103bbc, 0x2f21b1e5, 0xf2e518ee, 0x43cca5aa, 0xab8d675e, 0xcf7a4ae3,
4631 0xe14e4d43, 0x91e4c1ba, 0x6aab7f25, 0x2af891fc, 0x8944a251, 0x944a2512,
4632 0x44a25128, 0x4a251289, 0xa2512894, 0x25128944, 0x5128944a, 0x128944a2,
4633 0x28944a25, 0x8944a251, 0x944a2512, 0x44a25128, 0x4a251289, 0xa2512894,
4634 0x25128944, 0x5128944a, 0x128944a2, 0x28944a25, 0x8944a251, 0x944a2512,
4635 0x44a25128, 0x4a251289, 0xa2512894, 0x25128944, 0x5128944a, 0x128944a2,
4636 0x28944a25, 0xffe12251, 0x72255300, 0x008000ab, 0x00000000, 0x00088b1f,
4637 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4638 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4639 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4640 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0x00088b1f,
4641 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4642 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4643 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4644 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0x00088b1f,
4645 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4646 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4647 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4648 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0x00088b1f,
4649 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4650 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4651 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4652 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0x00088b1f,
4653 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4654 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4655 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4656 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0x00088b1f,
4657 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4658 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4659 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4660 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0xffffffff,
4661 0xffffffff, 0xffffffff, 0xffffffff, 0x00001000, 0x00002080, 0x00003100,
4662 0x00004180, 0x00005200, 0x00006280, 0x00007300, 0x00008380, 0x00009400,
4663 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, 0x0000f700,
4664 0x00010780, 0x00011800, 0x00012880, 0x00013900, 0x00014980, 0x00015a00,
4665 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, 0x0001bd00,
4666 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, 0x00010001,
4667 0x000e0004, 0xcccccccd, 0xffffffff, 0xffffffff, 0xcccc0201, 0xcccccccc,
4668 0x00100000, 0x00000000, 0x00000000, 0xffffffff, 0x40000000, 0x40000000,
4669 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2588 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2589 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000,
2590 0x00007ff8, 0x00000000, 0x00003500, 0x0000ffff, 0x00000000, 0x0000ffff,
2591 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2592 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2593 0x00000000, 0x00100000, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2594 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2595 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2596 0x00000000, 0x00100000, 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c,
2597 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
2598 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
2599 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2600 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
2601 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
2602 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
2603 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2604 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c,
2605 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
2606 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
2607 0xcdcdcdcd, 0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2608 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c,
2609 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
2610 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
2611 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
2612 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
2613 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
2614 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
2615 0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2616 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c,
2617 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3,
2618 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
2619 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2620 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
2621 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
2622 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
2623 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2624 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c,
2625 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97,
2626 0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c,
2627 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2628 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c,
2629 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
2630 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
2631 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2632 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
2633 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
2634 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
2635 0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
2636 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c,
2637 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
2638 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
2639 0xcdcdcdcd, 0xfffffff3, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2640 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c,
2641 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
2642 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
2643 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
2644 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
2645 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
2646 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
2647 0xcdcdcdcd, 0xffffff97, 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
2648 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c,
2649 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff,
2650 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c,
2651 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2652 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2653 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff,
2654 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c,
2655 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2656 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2657 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff,
2658 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c,
2659 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2660 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2661 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff,
2662 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c,
2663 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2664 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2665 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff,
2666 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c,
2667 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2668 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2669 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff,
2670 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c,
2671 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2672 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2673 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff,
2674 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c,
2675 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2676 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2677 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff,
2678 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c,
2679 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2680 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2681 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000,
2682 0x00070100, 0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000f0280,
2683 0x00010370, 0x00080000, 0x00080080, 0x00028100, 0x000b8128, 0x000201e0,
2684 0x00010200, 0x00070210, 0x00020280, 0x000f0000, 0x000800f0, 0x00028170,
2685 0x000b8198, 0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000,
2686 0x00080100, 0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298,
2687 0x00080380, 0x00028000, 0x000b8028, 0x000200e0, 0x00010100, 0x00008110,
2688 0x00000118, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000,
2689 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc,
2690 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000
2691};
2692
2693static const u32 init_data_e1h[] = {
2694 0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
2695 0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
2696 0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
2697 0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40,
2698 0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0,
2699 0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000,
2700 0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000,
2701 0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000,
2702 0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000,
2703 0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000,
2704 0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000,
2705 0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000,
2706 0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000,
2707 0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000,
2708 0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000,
2709 0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000,
2710 0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000,
2711 0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000,
2712 0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000,
2713 0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000,
2714 0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000,
2715 0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000,
2716 0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000,
2717 0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000,
2718 0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000,
2719 0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000,
2720 0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000,
2721 0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000,
2722 0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000,
2723 0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000,
2724 0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000,
2725 0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000,
2726 0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000,
2727 0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000,
2728 0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000,
2729 0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000,
2730 0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000,
2731 0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000,
2732 0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000,
2733 0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000,
2734 0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000,
2735 0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000,
2736 0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000,
2737 0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000,
2738 0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000,
2739 0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000,
2740 0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000,
2741 0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000,
2742 0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000,
2743 0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000,
2744 0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000,
2745 0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000,
2746 0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000,
2747 0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000,
2748 0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000,
2749 0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000,
2750 0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000,
2751 0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000,
2752 0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000,
2753 0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000,
2754 0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000,
2755 0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000,
2756 0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000,
2757 0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000,
2758 0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000,
2759 0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000,
2760 0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000,
2761 0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000,
2762 0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000,
2763 0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000,
2764 0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000,
2765 0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000,
2766 0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000,
2767 0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000,
2768 0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000,
2769 0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000,
2770 0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000,
2771 0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000,
2772 0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000,
2773 0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000,
2774 0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000,
2775 0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000,
2776 0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000,
2777 0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000,
2778 0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000,
2779 0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000,
2780 0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000,
2781 0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000,
2782 0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000,
2783 0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000,
2784 0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff,
2785 0x00000200, 0x00000001, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2786 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2787 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2788 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2789 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2790 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0x00007ff8,
2791 0x00000000, 0x00003500, 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20,
2792 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20,
2793 0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, 0x00006180, 0x00008240,
2794 0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600, 0x000146c0,
2795 0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80, 0x00020b40,
2796 0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00, 0x0002cfc0,
2797 0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380, 0x00039440,
2798 0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800, 0x000458c0,
2799 0x00047980, 0x00049a40, 0x00008000, 0x00010380, 0x00018700, 0x00020a80,
2800 0x00028e00, 0x00031180, 0x00039500, 0x00041880, 0x00049c00, 0x00051f80,
2801 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100, 0x00083480,
2802 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600, 0x000b4980,
2803 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 0x000ddb00, 0x00001900,
2804 0x00000028, 0x00000000, 0x00100000, 0x00000000, 0x00000000, 0xffffffff,
4670 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2805 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
4671 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2806 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
4672 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2807 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
4673 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2808 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
4674 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2809 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
4675 0x40000000, 0x40000000, 0x00088b1f, 0x00000000, 0x1113ff00, 0x51f86066, 2810 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, 0x00001500,
4676 0x423ec08f, 0xac9d0c0c, 0xc4b462a8, 0x1818990b, 0x12b102fe, 0x3c430333, 2811 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
4677 0x203aded0, 0x2388107d, 0x16181858, 0x2fd610b0, 0x022bd404, 0x2c4062c4,
4678 0x19b7c401, 0x9cdfb348, 0x1f0f680b, 0xc8037f82, 0x3f4024be, 0x1c360fff,
4679 0xfb5f40ad, 0x1819d502, 0x8aa06bfe, 0xf2a26831, 0x9bf13519, 0xcf2684c1,
4680 0x2167c68c, 0x63247fa0, 0x0d75b600, 0x000400f1, 0x00000000, 0x00088b1f,
4681 0x00000000, 0x7dd5ff00, 0xd554780b, 0x673ef0b5, 0xf3399cce, 0x00fde4cc,
4682 0x108f0992, 0x2104e034, 0x0432b445, 0x3b69488c, 0xc514543c, 0xf791e109,
4683 0xb14a3e44, 0x44033bd2, 0x350af808, 0x0380a050, 0xed168d02, 0x06823ca0,
4684 0xfda2901c, 0x5a1bdedb, 0xcb6ab7bd, 0x880b851f, 0x52d11921, 0xf77ac5ea,
4685 0xcc9f7b5a, 0xd0049339, 0x9fdffed6, 0xcfb3767e, 0xd6bdaf7e, 0xf7b5ebda,
4686 0xa441c448, 0x84be421c, 0xfc8471bf, 0xa484205e, 0x83bf52c6, 0xa908a3a6,
4687 0x2d0867d9, 0xc26425cf, 0x5c64633e, 0x136fcd0a, 0x179a2642, 0xbcb19b0f,
4688 0xfbcb3373, 0xdd4f6d0d, 0x01c9cb4a, 0x1349d903, 0x49116f92, 0x1467211a,
4689 0xd146fec2, 0xf321117c, 0xb35b2ccd, 0x426cc8ed, 0x98b797eb, 0x3fb69988,
4690 0x81e0d7b3, 0x429dc2fc, 0xd439d088, 0x67255c1c, 0x8417fed1, 0x45d9b084,
4691 0x47e93bf3, 0xd7b15e5a, 0x5dfa8210, 0xaf34b68e, 0x01f3908d, 0x9864b885,
4692 0xed693bdf, 0x86548405, 0xd16494f6, 0x05bb957a, 0xa9c748b7, 0xc6442cdc,
4693 0x42ef828d, 0xa8bb40c8, 0x5712b66a, 0x97c39b3e, 0x75c5c704, 0xc742dc2c,
4694 0xa912fda5, 0x61daf651, 0xcbb2b5bc, 0xf9cf831e, 0x51c71380, 0xd3cf35f3,
4695 0xdabb6871, 0x2c370497, 0xbe2456b1, 0xf3bf1d30, 0x73e679a0, 0x32df5836,
4696 0x5daecf39, 0x587ee947, 0x9b686547, 0x7983625c, 0x17e7936d, 0x6aabfac4,
4697 0x6bcfd64e, 0x9f74a0c3, 0x3d3e3ca6, 0x95c4201f, 0x1257cb17, 0x60db09e2,
4698 0xea7921fe, 0x63f7d8f0, 0xb3f71124, 0x5c40d9aa, 0x427fac4a, 0x40ddf882,
4699 0x2b8011dc, 0xb5bbb569, 0xa9d176fb, 0x8985b7df, 0xf31f6dbc, 0xc3ef9a79,
4700 0x27a70e5a, 0x4d347e61, 0x499738f0, 0x1309fd74, 0x4ab85389, 0x3246b5fb,
4701 0x7acbdc33, 0x186405ef, 0x888f884d, 0xe25adf38, 0x2ed21fbb, 0x4e9caeb1,
4702 0x3245fe9e, 0xabbd74bc, 0xfbfed604, 0x57f585c4, 0xb03d900d, 0x2aef6baf,
4703 0xcb90ce7a, 0xf90292d7, 0xd0d6bbf9, 0x7926932e, 0x0257c008, 0x614015b8,
4704 0xcb40d07b, 0x4713bbed, 0xe16971ae, 0xc61f3c57, 0x75128c73, 0xcdbce3fb,
4705 0x4d27cba2, 0xaf838a4c, 0x46e679cd, 0x34f3a79e, 0xd211d189, 0x67c64220,
4706 0x8b6f882b, 0x9ba465b3, 0x79b3b7c5, 0x85b6ce2d, 0x38ff3482, 0xe685b834,
4707 0xce4ddf65, 0x4741e05e, 0xa4064916, 0xe98c913e, 0x7000de59, 0x9c5078a4,
4708 0x03ef2573, 0x68c5fa9a, 0x1f4d225e, 0x0107c616, 0x8e012b2e, 0x481ab534,
4709 0x6adbac1d, 0x86a70822, 0x05cf4521, 0x9d5a7035, 0x1b94e14b, 0xb1b577eb,
4710 0x09b8832e, 0x23bc1359, 0xf8526528, 0x1dcdd2e6, 0x23bdf30b, 0xdb4c1c12,
4711 0x00ce2ee7, 0xa5322a78, 0x32f8ed03, 0xc700bf1d, 0xae38046f, 0x3f18fbe7,
4712 0x463792be, 0x6079be37, 0xb37c6eb9, 0x38a7c74c, 0x5df829b9, 0x63853e3e,
4713 0x233f2116, 0x95f1c5df, 0xfc704b81, 0xeb949906, 0x8f74b7c6, 0x7771821f,
4714 0x437e31f5, 0xfafd58de, 0xd7ea5607, 0xbff5b32f, 0x8f9bbc10, 0xfff5c16f,
4715 0xd6cddc82, 0x6c47f03f, 0xafda26fd, 0x37477c76, 0xf700c3fc, 0x5fc07dfd,
4716 0x7e9b7a19, 0xf5aa83fd, 0xf1b137eb, 0xc83e0d5f, 0xf8e1b7c7, 0xd90791af,
4717 0xc52d07fa, 0x3aa64df1, 0x991693b7, 0x21752c72, 0xfd176bc0, 0x074d3a5f,
4718 0x45be71d3, 0x422482d3, 0x901ffb68, 0xc5870881, 0xa850df16, 0xf142c97f,
4719 0x0be316cd, 0x0052b424, 0x38e5afba, 0xa977773d, 0x326d24fc, 0x4bf185b7,
4720 0x10e9f942, 0x96cebf3a, 0x4fbd2f4f, 0x47773be7, 0x42e0dba1, 0x6ed0247a,
4721 0xdf8a5f1e, 0x8841e0c0, 0x1daa7b37, 0x7b3793f8, 0xf22c70da, 0x40599f00,
4722 0xf03d8e70, 0xf1a35e78, 0xbe86bb4c, 0xe7d06c16, 0xbcfa422b, 0x80f1ef3a,
4723 0x160d3424, 0x3a3afc93, 0x8fca19ee, 0x1f93e508, 0xe9047e52, 0x08792359,
4724 0x94d38dce, 0x4b59115f, 0x5f70cb57, 0xfe0c48ce, 0x91583667, 0x7dad2f1e,
4725 0x60832658, 0x640a563e, 0xf24178cd, 0xff9d3e76, 0x089d7c3d, 0x57e022e7,
4726 0xb4f73d6c, 0x47a14cd6, 0xb2779d2c, 0x31a75dae, 0xf5be0462, 0x963d0920,
4727 0x7b2ffb41, 0x87d18f62, 0x4fd3c7fc, 0xfd26ba44, 0xf7d74a44, 0xd87e34ce,
4728 0x733769ae, 0x3f635aef, 0xd3e7de9a, 0xae559f7f, 0x431a77cf, 0xe5ce1146,
4729 0xa36c810a, 0xa7583ffd, 0xf9c7572f, 0x7db1248c, 0x43dde3e6, 0x049992d7,
4730 0xfe91fa59, 0xeb64e7db, 0x497ae7a0, 0xca1f383f, 0x9a4ef704, 0x8dea107f,
4731 0x4b7c7d84, 0xe7b3ef86, 0x90d7ba25, 0x5225f39e, 0x9273f606, 0x25271b9f,
4732 0x08b753e3, 0x7edfe73d, 0x4711ead8, 0xfc475cf4, 0x4e221fbc, 0x968787dc,
4733 0x0697bfe8, 0xf0c7d7e3, 0x3e32dfc0, 0x7be6b4f9, 0xe4aef84d, 0xa97c1ad3,
4734 0xcbaa9e6a, 0xd3ee8457, 0xa1b05fd5, 0xaf3e5754, 0x5e5742b1, 0x2eb0f0d6,
4735 0x447c1a5f, 0x25a1ff57, 0x0fe574cb, 0x95d6add6, 0xab5f2acf, 0xdbe7dfcb,
4736 0xef7faba8, 0x72ba6dcc, 0x0e4570e1, 0xd97e37c8, 0xe1499397, 0x135de17e,
4737 0xf0c42ed9, 0x73f3c558, 0xcf4c0c81, 0x2e985c07, 0xf4a57a03, 0xa9641e2f,
4738 0x0e697b7f, 0xf78ab9d0, 0xd9758d67, 0xf8f12740, 0xf18f4f1d, 0x03780c78,
4739 0xe75f50e7, 0xbc40b579, 0x025df740, 0xefd48f3b, 0x97fce67f, 0x6f48e590,
4740 0xc7a332d5, 0x8b3397ea, 0xe5aa5e81, 0xad9d5e48, 0x58497eef, 0xb21075c0,
4741 0x08a9fb1d, 0xedd0aa51, 0x3cdd20eb, 0x70188e3b, 0x3e105afc, 0xdef3816e,
4742 0xf8c02a5b, 0xa7b23791, 0x78f9870f, 0x25be60e6, 0x4762f915, 0x69f25260,
4743 0xc5e7e009, 0x26605cf4, 0x3e0267a6, 0xca074f4c, 0x5030fd31, 0x607b6987,
4744 0x0327a609, 0x14ff4c41, 0xbdf4c068, 0x7fa62340, 0xf4c06c0c, 0x4c21033f,
4745 0x4c1e033b, 0x14d4f1bb, 0x90f903cd, 0x20226fbc, 0x2e1492e2, 0x3372a97f,
4746 0x5c85f961, 0x2e0bee6e, 0x27defbf1, 0xbc5048fc, 0x2c59beda, 0xa8e83f6c,
4747 0xf3a50893, 0xbbf6c335, 0x44bcb0e7, 0xdd843f90, 0xbbb2f95a, 0xf483d85f,
4748 0x9fc7ef6b, 0xf381dce1, 0x9e030def, 0x8af2247f, 0x0b5dba7b, 0xc047ba0f,
4749 0x86b75e6f, 0xd5fe5276, 0x7c31705f, 0x2e5c06b9, 0x039cf5be, 0x0cc2e8f8,
4750 0xe6fa79d1, 0x1357d7be, 0x34da75ce, 0xe8b7f1f3, 0x851b17f3, 0x741e4c49,
4751 0x0e18cc25, 0x9e74e0f8, 0x96fb0c1e, 0xcfdaa981, 0x79d90cc2, 0x85ea193a,
4752 0x77643d70, 0xd517e222, 0x3fdeb047, 0xf57d1e7b, 0x5ec79b13, 0x47b68a72,
4753 0xdf507b19, 0x0bc4fbf5, 0xe41933e9, 0xbc6ad268, 0x85aae704, 0x40e5f7fe,
4754 0xbcc257e8, 0x6c3fafda, 0x826e9a08, 0xe375bbef, 0x552e76d1, 0x7d7683d7,
4755 0xce449fe3, 0x5941f8a8, 0x6fae09d2, 0x9d9b3556, 0xa89d7e7a, 0x325bfbcb,
4756 0x0dfe3a9d, 0x4af4a0ff, 0x9c120a26, 0x2b1cd5bb, 0x835b24ba, 0x1bb7e740,
4757 0x8bee86f0, 0x6af5605f, 0x47d97694, 0x67dc2d3f, 0xe17df3c7, 0x05efae5a,
4758 0x9fb41b49, 0x70778633, 0xd34ace85, 0x449ce51f, 0x9e32f9a4, 0x39aef553,
4759 0x7cf0ab7b, 0x94126fff, 0xc8ff3ce1, 0xe70458d0, 0x9b786553, 0x76fba1ec,
4760 0x80938881, 0xbf205cef, 0x91acdc77, 0x3208afe3, 0x41acb7ae, 0x79516e7f,
4761 0xf2a79747, 0x9f3f2e8e, 0x3d034b4c, 0x91937e6a, 0xff285e8a, 0x043bcae8,
4762 0x80bbf627, 0xfe04add4, 0xcdef6a7e, 0x700adcf7, 0xc8a5b03c, 0x6873f347,
4763 0xbf4a3f71, 0x6427cd95, 0x3aaf93a0, 0x1fb4057e, 0x755c73d9, 0x51f43d5d,
4764 0x669a870e, 0x85ea13c1, 0xa6459b9f, 0x9f74a9d7, 0x72753a25, 0x7e5c5e5b,
4765 0xf6fe5c64, 0xc6d7fcb8, 0x908a149f, 0xdefdb169, 0x44f2f82d, 0x478043e0,
4766 0xf9bc3109, 0xf467fdda, 0x3fe47fe8, 0x44feffb5, 0xffb4ff87, 0xfda9ffdb,
4767 0xff31ee0f, 0x5ff5bdc9, 0x149e8a6b, 0xdd7b1ce0, 0xe198e78c, 0x7a0839b0,
4768 0x19ab7f82, 0xf637dcf5, 0xd01775fd, 0x26b3e75d, 0x8e7a6262, 0x93bff280,
4769 0xdf767bf5, 0x0ffeb75f, 0x8d0b3f2d, 0xb60b7f69, 0xef80fad2, 0x64c8adbb,
4770 0x184e5eba, 0x2f5d2841, 0xefd1fd78, 0x2e2f2a11, 0x91dee2b0, 0x0f4cbf05,
4771 0x51fb00ad, 0x799fcb2a, 0x08284071, 0xed979e76, 0x1808c311, 0xa3ed40f7,
4772 0xad2fee30, 0xa42d1e84, 0xd61375f3, 0xa305fceb, 0x2ee78a7f, 0x24415e9d,
4773 0xe77e3757, 0xb5241c02, 0xe052f85c, 0xf0e22840, 0xd55ef4a1, 0x8f31e092,
4774 0xfbeaf800, 0x2e8c60b9, 0x0eff2376, 0x5bc88966, 0x77205922, 0xcb53d7c7,
4775 0x5540e2fd, 0xb6ec581e, 0xfd53eac5, 0x37cb3e79, 0xa0fd3166, 0x052feb0d,
4776 0x958d49fa, 0xd597ecf7, 0xcec891ff, 0xac3f58db, 0x53d72d7d, 0x1572e9e3,
4777 0xe6aacba7, 0xa6f6862f, 0x7f32f55f, 0xa65fbefc, 0xafdd0582, 0x10e6cbe0,
4778 0x23b5616c, 0x6bef7a82, 0x6d511edc, 0x9e1ea089, 0x3905c7c5, 0x6944f20f,
4779 0x8ced097f, 0xf404cc07, 0xedd79add, 0x9adfd81e, 0xf33d7ffd, 0x63bdfa33,
4780 0xf80dd59f, 0x0ffaf350, 0x4c6bdf71, 0xdd02d991, 0x2a1ee8bf, 0x1dfad2ff,
4781 0x4d9d7e7b, 0xc61d3f68, 0x55d27648, 0x613565ec, 0xcafc9c53, 0xe03e7de6,
4782 0x98f2019e, 0x3b5447ca, 0x53fb7c5a, 0x45cff162, 0x4417970a, 0x7c88b34f,
4783 0xa9df6f4b, 0x5d39525c, 0xfdabde7b, 0xbecc4a54, 0xc43f7ea4, 0x1ba87be1,
4784 0x2e935fce, 0xf2e83d6d, 0x02ebcc10, 0xf3834b69, 0x13f9b6a8, 0x4aed4419,
4785 0x2e813590, 0xbee032df, 0xa12b9b10, 0x4d4df937, 0x4cc605cf, 0x75de5097,
4786 0xfedfea63, 0xc28b2381, 0x4f86fe7f, 0xe91ce1b2, 0x199e643a, 0x7f39fd42,
4787 0xbf1834ba, 0xa0f5dca3, 0x51eb8ac1, 0xe3a4abc7, 0xf5b10bd5, 0x755c6b5f,
4788 0xaefc753c, 0xcfac9f8d, 0x69f8e174, 0xb8fc7e30, 0x5c753b6a, 0xde7c572a,
4789 0xd886978d, 0x414b96fe, 0x72c3ce19, 0x947ee122, 0x14797a93, 0xcd8841d2,
4790 0x74ed4977, 0x97ca9f90, 0x4a5d3edc, 0xf900f366, 0x6901e60d, 0x5ef1c6d7,
4791 0xfb7fa380, 0x3a520554, 0x305f5c0f, 0x221a16d3, 0x3ca0f9b0, 0x7d414c1f,
4792 0x777be257, 0xe9fdf026, 0x17b87f4c, 0xb81d39fb, 0xf1c6f313, 0x1437c875,
4793 0x85a988d2, 0x1ffd3184, 0x8f9c46f1, 0x90238a8d, 0x98f81aa7, 0x0e11c359,
4794 0xb6245979, 0xe913f87e, 0xcdbf2b38, 0x572ddad7, 0x30e1c53d, 0x580679c5,
4795 0xbe47d066, 0x08ae5da4, 0xa3f364cc, 0xbe5128f8, 0x517f84e5, 0xc79d3a78,
4796 0x103826ff, 0x4a7ad9ef, 0x5d056848, 0x7c73248f, 0xbe184c99, 0x5e265c34,
4797 0xdd3c1d8d, 0x090ef8c0, 0xe83e411e, 0x5fc1fde0, 0x9451e694, 0x245655a7,
4798 0x7802df64, 0x089270e1, 0x91b7638c, 0xd8047588, 0x5af3a551, 0x1b79c1f9,
4799 0xa8ecebcd, 0x3a78f2fa, 0xb14bed53, 0x7e70db71, 0xe2cfdfb4, 0xae2cfdfa,
4800 0xd6aecfdf, 0xbf270aaf, 0x740bddb2, 0x87c058fc, 0xa78ea6fb, 0x7c28f1f0,
4801 0x113f51f2, 0x429dee2d, 0xd616ae0c, 0x22633d15, 0xc0337fb8, 0xf4e14ce8,
4802 0xe8e1c278, 0xb29050a3, 0xd7fe0081, 0xfd353b73, 0xed34daf3, 0x7a415388,
4803 0x99c7cd5e, 0xa1fc6061, 0x9ecff39e, 0xee78cdf5, 0xee6fa8f7, 0xf7a5beab,
4804 0xe6bef6fa, 0x3e75ed63, 0xd55f955f, 0xff5ffebe, 0xf869711e, 0x52829396,
4805 0x30ccaf2f, 0x126b7ed0, 0x1dbdfccf, 0x0f5144bf, 0xf7ebfa51, 0x4af802cb,
4806 0x5832c7f1, 0xa056ddff, 0xf05ee7df, 0xd74996c5, 0x63af9331, 0x14e97366,
4807 0x86264738, 0x526496a6, 0x5abfbf3c, 0x17709b70, 0xbce8ffe9, 0xbaf3e3ee,
4808 0x3a4051bf, 0x21917fb8, 0x6ec5eae4, 0x41fe0b35, 0x09d567cb, 0xd3d088a1,
4809 0x1b4b057e, 0x3e760696, 0x3b4f6e36, 0xeaf1045c, 0x6cde3e21, 0x0c1a4a42,
4810 0x845bed3d, 0xef2957e3, 0x35dede27, 0x2ed1b887, 0xffcf2f16, 0xe463e419,
4811 0x91b921c7, 0x46c1afee, 0x31e416f1, 0xfe8dc583, 0x3037fe90, 0xdc2159fd,
4812 0x2e5047ce, 0xa4040722, 0x573e8bfb, 0xec55d242, 0x33025b30, 0x62f0ced1,
4813 0xd9a60360, 0xce043c8b, 0x412f6961, 0xa05b7f79, 0xdf0fbf1c, 0xd1942edb,
4814 0x176ce4bc, 0x6774d3e6, 0x1f7e0960, 0x3fafaf58, 0x644baf7c, 0xd4225cf5,
4815 0xc3e0367b, 0xea05cf7a, 0x7cf5bed0, 0x3ff301a0, 0xcd31040f, 0x95f3626b,
4816 0x2fe82a96, 0x11a045fc, 0x18fed1eb, 0x41427aff, 0x2f7c3cfe, 0x79b797ab,
4817 0x2dd6084c, 0x777e7939, 0x197fe639, 0x377f6108, 0xb5fde0ec, 0xb30b9412,
4818 0xb3afdd17, 0xce96b863, 0x030fc9d1, 0xe5752beb, 0x3f063aea, 0x6f5750b1,
4819 0x5890def8, 0xfdf30056, 0xe4bbee91, 0xffe0890c, 0x5cbcdfcb, 0x3b0dcfd7,
4820 0x15eae8d6, 0xae89feec, 0x4ddec47c, 0x75bbbcba, 0xeeaf2ebb, 0xca65f54f,
4821 0x5679e9d8, 0x4205f975, 0x2fdb3f28, 0xf4375e79, 0x075cb722, 0x76bca05e,
4822 0x69f87c2d, 0x5c7083c0, 0x4840f545, 0xb3fcb833, 0x3493ec1a, 0x27d838ff,
4823 0xecc82fd1, 0x3b734f54, 0x3e40dad5, 0xe0267f7e, 0xc0bafcc6, 0x0c6fcc18,
4824 0xcffcc24c, 0xdfcc5e02, 0x09bf3123, 0xf00da9e0, 0xda3359f4, 0xe9671087,
4825 0x525b5d7f, 0x923f2043, 0x32f1c68c, 0xa2e637e4, 0x3f709a5d, 0xb3a70543,
4826 0x955687b3, 0x7122a6ac, 0x288beb55, 0x9939511f, 0x4e9adc80, 0xefd6bd79,
4827 0x037f2d77, 0xfef58395, 0x0721b987, 0x258aadf0, 0x0a29c993, 0xcfcda3ef,
4828 0xfae9da39, 0x432c762b, 0x3abcbb7d, 0x6d20bb28, 0xd3fd067e, 0x0dc4d5e5,
4829 0xb6e547c7, 0x4b9eff6d, 0x99f55dc7, 0x0f80da40, 0x0107214b, 0x91b376bf,
4830 0xde58ae72, 0x009cfcdc, 0xd93b34f3, 0xee9d98be, 0x0a79e208, 0xc5710f71,
4831 0x519cdaf0, 0x7f6e7e87, 0xe825f47a, 0x3c87dcdf, 0x2ee92bfb, 0xe50d1a41,
4832 0x8a30c46d, 0xf7d80cd1, 0x78582f1f, 0xe791ec04, 0x80b7201f, 0x6bf1e73f,
4833 0xe74ecbcc, 0x4eeded05, 0x93bb0b06, 0xf36393fb, 0x1d96ff42, 0x9b1b95e6,
4834 0xe5e89d97, 0x52bccd62, 0x772854a4, 0x4ece780a, 0xf04f1824, 0x79fa6df4,
4835 0xb2f30d3d, 0x44af3df5, 0xebc02f3a, 0xc4af0e44, 0xfd42f09e, 0x5e0e3134,
4836 0x6bc37d89, 0x912bcc28, 0xf4230578, 0xebc18333, 0x79fa2999, 0x780d733d,
4837 0x4179d2a5, 0xaf0e54fb, 0xc2f09ed4, 0xbc1c6a7c, 0xd786fb52, 0xd2979858,
4838 0x0df1d45f, 0x8e8b60cb, 0xefc0d82f, 0xfb5729a7, 0xd2ca8c73, 0xfddf4f7d,
4839 0x005150b0, 0xdd40d3f2, 0x3789a4f7, 0x5329f2e8, 0x4ffaea46, 0x9756319b,
4840 0x58a078cf, 0x3b9acf97, 0x7fbed759, 0x795d34f5, 0x191103fa, 0xcb9a8bf4,
4841 0xd6f9e3db, 0x7c2f523d, 0x0728cbab, 0x35d7cec1, 0x4163c99c, 0xbd63ca81,
4842 0x3e8baff0, 0x5b17db86, 0xff436f87, 0x39789fea, 0x1fb40bc7, 0xe0f03d83,
4843 0x55f7f450, 0x13ddfa73, 0xf3be4668, 0x7c8c204a, 0x6fb71f68, 0x8738801d,
4844 0x0381823c, 0xd378df68, 0x82788215, 0x19e6dfea, 0xfceb3ce0, 0xfc13329d,
4845 0x8be69dae, 0xefc8230e, 0x3771d452, 0xa94107cd, 0x8905b881, 0x1f6dea4c,
4846 0xb7f38dff, 0x9ecf07e5, 0x1d2f7e84, 0xb44cbb34, 0x56af09df, 0xf9a7643c,
4847 0xdd98f7da, 0xfbfe2fa4, 0x63f7c92b, 0x97e62706, 0x93f97da9, 0x5f8e8411,
4848 0x00d13bb8, 0x180aa7fc, 0x07f82a44, 0x1f41b3db, 0x05ec791a, 0xfd47fc1d,
4849 0xfedd65f6, 0x230b1e14, 0x43f752df, 0x7ee84f3d, 0x8538c034, 0x56e3e07d,
4850 0xe225db89, 0x067f74f9, 0xa7c0b3af, 0xbfe59569, 0x9697eca3, 0xda6cdfcf,
4851 0xbf9ceb0e, 0xe071d961, 0x1cb767cb, 0x0bbefe38, 0xdbe3a1a7, 0xb9435f54,
4852 0xe7f36bf0, 0x53dcf07f, 0xbd7e22f1, 0x119b9755, 0x70f9dd2e, 0xbdcef6ef,
4853 0x7b53d312, 0x57b7d3c2, 0x18587f42, 0x2eaa8ee3, 0x7bdf84bf, 0xd42eb1ca,
4854 0xd539172f, 0xfdc9b5f9, 0x601d0f80, 0x8545d97e, 0x2fc812e1, 0xbdd1317a,
4855 0xf95faa02, 0x46834bf2, 0xda345ece, 0x2af0be93, 0xddea91f6, 0xc5ea1226,
4856 0x4625d23e, 0x48d2996b, 0x578a50e5, 0x2768965d, 0xf5477fe4, 0x986349fa,
4857 0x12e20abd, 0x62daa59a, 0xbf36ac69, 0xfaca58b0, 0x4d42faea, 0xdfc7c7eb,
4858 0x817d3127, 0x427f07ea, 0xf5e814f8, 0xe84f5506, 0xae703d6b, 0x0cec3ea3,
4859 0xbbaf5af7, 0x728d75dc, 0xd2e51ae5, 0x45ffca35, 0xcf29f7e3, 0x55ea66bf,
4860 0xe058bf9e, 0xd03e074a, 0x76098f45, 0xe064468e, 0x2d0d555f, 0x1adf3f0c,
4861 0x8ff9009d, 0x7d5abeb9, 0x72f8c439, 0x5cd79588, 0x788108a6, 0xd426e2ca,
4862 0x49163f7e, 0xe17c6f79, 0x1fd32356, 0x20ff5a6b, 0x73cf80bb, 0x7ce1a93a,
4863 0x4532e6a4, 0x695f4a28, 0x1bd61346, 0xfe233466, 0xef491915, 0xad8d9f72,
4864 0x8027e54f, 0xce4fc093, 0x3cc5cc6e, 0xf5f227e5, 0x8e1a93f0, 0x9f955f67,
4865 0x02f30adc, 0xf3da54bc, 0xf7905e30, 0xdaeebf13, 0xa9c20746, 0xfe80ce9b,
4866 0xed7e066f, 0x02a63429, 0xf71809dd, 0x4262dd58, 0xa356e439, 0x5eebed8b,
4867 0xbeac4fe6, 0x03f18bbc, 0x17d38d89, 0x538fc7be, 0xe3a2d8d5, 0x16f83d4b,
4868 0xff8c578f, 0xf1919f7e, 0xe2848bef, 0xfc4f4147, 0xafa2f150, 0x5b2e6b7e,
4869 0xdee8f374, 0x767deeef, 0xc6c73ee0, 0x953c7053, 0xa470aa1f, 0x38dbb9f0,
4870 0x627c27ba, 0x38412970, 0x48fb7276, 0xc98d5f3c, 0xc55edc0f, 0x81e3d9f9,
4871 0xb5adde3f, 0x38fb5af7, 0x387156c7, 0xd1040eac, 0xf51d242e, 0x5aaec138,
4872 0x6f07766f, 0x49f0c437, 0xa164d8e6, 0x9d035e62, 0x849525a7, 0x16a6d196,
4873 0xe7f02b98, 0x2af8825c, 0xfe1d24d9, 0xaf3429c8, 0x288db7e3, 0x13069b27,
4874 0xe957f001, 0x615f2faf, 0x6b3af164, 0x4b3bb7f2, 0x927fbce9, 0xb820fbff,
4875 0x6d601dd2, 0xebfda033, 0x63bfaea2, 0xca64dcd2, 0xfcf8132f, 0x72d1b79c,
4876 0xc1e6f8cd, 0xade4014e, 0x76fa89a4, 0x0cb070f1, 0x8abfeba6, 0x1c524cdd,
4877 0x20a197e8, 0xc2317662, 0x612230e5, 0x272ae8dc, 0xadcb47e3, 0x95d7a40e,
4878 0x63ee2239, 0xadb7b713, 0xc81b3b07, 0xfc848a52, 0xeac894cb, 0xb44109cb,
4879 0x4ec199a3, 0x8a7d806b, 0xda4ede60, 0xeb009f31, 0xb8f2041e, 0x4c9fd70b,
4880 0x6f412b22, 0xbedf1aef, 0x164fbe18, 0xfe02cf7d, 0x3b6cca5c, 0xd53d8029,
4881 0xf40a1beb, 0x2c10c1be, 0xcffad174, 0x5085a21a, 0xfd169b2f, 0x39a58931,
4882 0xd3e4d710, 0xff987ff8, 0xf437963b, 0x912ce7cc, 0x5721fce2, 0x5fcb6a86,
4883 0x012f3d10, 0x129ca79d, 0xba909e50, 0x09bd4de3, 0x2bf70f10, 0xb1878f23,
4884 0x2fe93d31, 0x8f4cb9ad, 0xeac721ed, 0xf70537f9, 0x79ba63f4, 0x63f2e3b9,
4885 0xd8d31fa6, 0x2797fdc3, 0x0ec1f8ea, 0x1d8d03a0, 0x11e4b07d, 0xa4355fc1,
4886 0xcabf7e91, 0x6dd6bf7e, 0x601a0cbf, 0xf8f1f77e, 0xb3d5220b, 0x22f78f3c,
4887 0xff744bb0, 0x6cd455df, 0x593bcb3d, 0xf9873fce, 0xc0f9baf3, 0xec045361,
4888 0xce1eef7b, 0xdcfb062c, 0x51e8c66b, 0x3ff5c82b, 0xfdcdf260, 0x5a331cef,
4889 0xedefba69, 0x4b9076ed, 0x9cfa724f, 0xd846a24d, 0x0f8f1f47, 0xaafaed53,
4890 0x55ca8c5d, 0x0f9be046, 0x7f774244, 0x3c1ee697, 0x1c2efa16, 0x8adfb397,
4891 0x9ad80afe, 0xb12cec2f, 0x16bb4d12, 0x679671f7, 0x45eb34ed, 0x57ad8e7c,
4892 0xd668f5c1, 0x5b15fb8b, 0x50f082af, 0xfc19fbd7, 0x787ce69f, 0x14fbe8db,
4893 0xdd7e33f0, 0x5b344ad5, 0xfbf8881a, 0x5a9bc057, 0x8d272f83, 0x00c2e3ae,
4894 0x5854d0df, 0xf2325b4f, 0x6ff8bebf, 0xf466fc77, 0xcdb71606, 0xf386a7f1,
4895 0x86fb15fb, 0xe11d8026, 0x220daffc, 0x21e7ddc8, 0xbf7e921e, 0x81343cd8,
4896 0x73bec55c, 0x2e75db8e, 0xe8095d3a, 0x911d094f, 0xbec00b4b, 0x539e4471,
4897 0x9a9eb3d0, 0x91ed0f2f, 0xb20ed14b, 0xa2388647, 0x1af71e1a, 0x993f7fdf,
4898 0x6379c1d1, 0x20e804b8, 0x04e0a2fa, 0xeed55eff, 0x5ed1c73d, 0x247123b2,
4899 0x710d2f8b, 0x08db473f, 0x908a9fd8, 0x146f1f41, 0x91057266, 0xb0cc46da,
4900 0x8f52e16b, 0x63fd34ed, 0xed57dcfc, 0x31496cbf, 0xbb720539, 0xfa0f1cec,
4901 0xc32b7043, 0x1e89b2cf, 0x33f69d83, 0x7f4041b6, 0xdba72de5, 0xaca98e31,
4902 0xbf409129, 0x472c8f65, 0x9b6d533f, 0xf81da5ab, 0x0f704864, 0x794fe021,
4903 0x14c7f0b8, 0xb28eeb1e, 0xc3fc807d, 0xb8f32fe8, 0x6fbb1a6c, 0xd0aeb187,
4904 0xa0f0f409, 0x5cf203cd, 0xbbcf0ce9, 0x205957e0, 0xfe008e45, 0x7d2ceba8,
4905 0x0e0635c0, 0xd9b0d285, 0x2442a983, 0xa56be50b, 0x4d205112, 0x86648997,
4906 0xffcfeb7c, 0x6c289cc2, 0xa216e9bd, 0xfebfefb0, 0x8de1e01b, 0x8edeb2cd,
4907 0x6fe7d619, 0x0be7d16a, 0xcdfcfa23, 0x4ff3e96f, 0xf74941c0, 0x0c2fb5f7,
4908 0x37f088c4, 0x47fe0085, 0x8588990f, 0x97eaabae, 0x2703d466, 0x9cf0d954,
4909 0x7305f8f8, 0xde47f208, 0xec08b57b, 0xb4bf954b, 0x6f01b8b3, 0xaf2825f8,
4910 0x811fa97a, 0x0dff7273, 0x8cb7b544, 0xff64b900, 0x3ed80ddf, 0x9fed3cfa,
4911 0xe0f8ffd6, 0x947a5fcf, 0xf9f8ffb6, 0x1210497e, 0xdf87d594, 0xef59aabb,
4912 0x41ba1e1f, 0x2161ff3f, 0x664abe7d, 0x2f0bfafa, 0x187e2ac8, 0xdba5df18,
4913 0x17f5c695, 0x907f9697, 0x6e20fd45, 0x8182e400, 0x4455efb1, 0xbf46afd3,
4914 0xe1e9c89f, 0x019dc05c, 0xc88a63e7, 0x85cfeae2, 0x7a0348de, 0x1bc768fa,
4915 0xe74f4069, 0x4fd04b03, 0x6767bd55, 0xd5e79c12, 0xf0e1bfcf, 0xaedf7a40,
4916 0xdc82c6a7, 0x0c21bcf4, 0xd3dfa0f3, 0xf8477be0, 0xf4598e57, 0xc91db9fb,
4917 0xd17def88, 0x30a8457b, 0x7c0e7b43, 0x8ee87c55, 0x383272a3, 0x9de3181c,
4918 0x0fba5dfe, 0x780d9b55, 0x7c2aa65f, 0x038677f7, 0xa2366c1d, 0x8f7aabdd,
4919 0xbe3ea091, 0x7bb456ed, 0x813eed55, 0x8dfec771, 0x5e5718a5, 0x61af1124,
4920 0x664cba24, 0x75ae7a40, 0xb7ec039f, 0x926e7f55, 0xefc81725, 0x78a3fdfa,
4921 0x548c7180, 0x069a28f2, 0xb2cf494e, 0xa9bff022, 0x57ae7bdf, 0x5f7e3edf,
4922 0x78d5915e, 0xddaf9225, 0xc97af8df, 0x37688253, 0x5cb25ea9, 0x7d500f17,
4923 0xfe0651ba, 0x4a0e3f1a, 0xfa739a90, 0x017f0835, 0xeb917f3a, 0x51ce5439,
4924 0xc3cfa2e8, 0x3cb106bf, 0x80952b9c, 0x1bfeb047, 0x851744c8, 0x3234d547,
4925 0x032cd209, 0xe42c7bc1, 0xefefe615, 0x7a0473a0, 0x237dd8e8, 0x84bab7da,
4926 0xc33f5df6, 0xb7c8edfe, 0x07119c3a, 0xb6544dc4, 0xe2ee319a, 0xf2320be3,
4927 0x37e1658d, 0xdc6f101c, 0x145992f1, 0xf1f5b0a9, 0x8362e49e, 0x37e7f003,
4928 0x4e19aecc, 0x571d962e, 0x7b9a2fd1, 0x00f8b78f, 0xafcf49fe, 0x273d94ff,
4929 0x7d678064, 0xe98b9e32, 0xbd8575c9, 0xedaafdc5, 0x42bae452, 0xb3d3c817,
4930 0x5aefdc6d, 0x72f80b9f, 0x06e197d1, 0x6054a979, 0xf4480efd, 0xed7e849e,
4931 0x924bd6cc, 0x076c32de, 0x70653a7c, 0xf852762f, 0x945e25cd, 0xf28ee60b,
4932 0xa48740c9, 0x96fdc59e, 0x51222449, 0xf80cb039, 0xa3cc08ea, 0x59b65efc,
4933 0xb9a2f8c0, 0xe775184f, 0x69e1c400, 0x1a4e57d7, 0x124adfb1, 0xb37cb4c6,
4934 0xf802bcbe, 0xa5578534, 0x95e0fcc2, 0xf0718c3b, 0x5a3ea089, 0x930bfbbd,
4935 0xfd751c76, 0xfaea217f, 0xd1e5973c, 0xfd45fd4c, 0xf70129be, 0xd8c8ffd9,
4936 0xe65f380c, 0xf8e0f699, 0x985cfc55, 0x7e58ea4f, 0xa00c8922, 0xeba3cfe3,
4937 0x9e607382, 0x918e8242, 0x92309f2c, 0xdf93c7ad, 0x0eb03d73, 0x36f277ed,
4938 0x56aaafdb, 0xd61c3221, 0xf20de743, 0x5b47ac37, 0xb3af9aaf, 0xaefd377a,
4939 0x7690ffb5, 0xf7bb5fac, 0x5fae930b, 0xe7a0cf6e, 0x7dd33110, 0x37cdd758,
4940 0x71b4c343, 0xe1bdaa23, 0xbac78724, 0x0267e7bb, 0x720d3dbd, 0xd8071658,
4941 0x8127aa18, 0x032c676f, 0xb7c742ac, 0xc79ddcdc, 0x2ce5a2f2, 0x76b4c83f,
4942 0x54fe86c2, 0x32fa310f, 0x3329ae41, 0x68438f78, 0x37c54ece, 0x29c744d4,
4943 0x12d93d93, 0x1e4f75f2, 0xb09659da, 0x6474fff5, 0x5ebab0dd, 0xbf7518e4,
4944 0x08e10bd6, 0x641d43c6, 0xbd7c41f2, 0x4fc62671, 0x1fb68e12, 0xdd173e07,
4945 0x5a11e547, 0xc1f0a36f, 0x6de3b071, 0x5645cbbc, 0xdd067cd0, 0x1b77e01f,
4946 0x502f5205, 0x4bda8cb8, 0xa3d01be5, 0xd4378ef7, 0x4cdd70d8, 0x6dd6b06e,
4947 0xfa47fb03, 0x0123f943, 0xb930ef5f, 0xdd741e70, 0xe5a34d0f, 0xb983cb19,
4948 0x384bff60, 0x0ede6a1a, 0x8b70efe7, 0xa74bc61b, 0x6127b1b0, 0x7fe700da,
4949 0x023c2906, 0xc5319574, 0x88ec1235, 0xffac1ceb, 0xd0f0d154, 0x46539054,
4950 0x28d27cb2, 0xfb8ed9e2, 0x49c716b3, 0x30499137, 0xf20ef83f, 0xb3d6ed17,
4951 0xc4349107, 0x5d4275f6, 0x3e9f8c21, 0x7064a588, 0x8bcbca06, 0x9eaa7cb8,
4952 0xf7f59f6f, 0xea3f0024, 0x3f01f7e2, 0x201279b3, 0x1b1c8c8e, 0x9fed6a26,
4953 0x0345fd6a, 0xdf50e93c, 0xc124597f, 0x287fe464, 0x5e67fa5f, 0xff857b42,
4954 0x1a824cb2, 0x9cbfec3e, 0xd777cfa4, 0xb1f6c34b, 0x4a12167a, 0x839eadee,
4955 0x11fd7484, 0x7f2d7f7d, 0xec24f5e5, 0x77698c8f, 0xe9d91c80, 0xdb3e476a,
4956 0x46831215, 0x1174f7aa, 0x9dc1f182, 0x6d5df64e, 0x265339df, 0xa2679411,
4957 0x40474fd8, 0xb2630881, 0xf413f5a9, 0x1eb7561f, 0x35ef8129, 0x7ce30da4,
4958 0x1256c26b, 0xdbffc5ec, 0x970b0011, 0x3f29fce6, 0xfdd4ed8a, 0x9037b588,
4959 0xb38fd690, 0x52222da2, 0xeab75a5a, 0xc00a2bd7, 0xd3947704, 0x2b37f04d,
4960 0x72d1b73c, 0x23a3a883, 0xba6ea8eb, 0x275f3242, 0x061d181a, 0xe262bb7f,
4961 0xaf3c9a6d, 0xf83edddf, 0x291309bb, 0x602a8ddd, 0xf55d9fed, 0x972c6fef,
4962 0xae807c62, 0xd76bdb3f, 0xbcb895e4, 0x6b87e68d, 0xf2b8cef2, 0x8cf2b894,
4963 0x567f7cb8, 0xc91ec3bf, 0x1ca9b836, 0x13f7eab7, 0x3a4fca24, 0xa9b32332,
4964 0x309e4f04, 0x226133bc, 0x6a8f8dc4, 0x5a79c0f3, 0x59b82adb, 0x5f830fb8,
4965 0xb9e19bad, 0x832eddcd, 0xaa3adf7f, 0x7688b8ed, 0x7209c12a, 0x27bc2da6,
4966 0xe7687982, 0x330bb4d2, 0xfc3aa4fd, 0xb3ebb601, 0xe9117cff, 0x87fe4d7c,
4967 0x765aef58, 0x8faf9274, 0x6e2bef83, 0x3be0b770, 0x92bd026a, 0x77bf9144,
4968 0x992ff9ec, 0x7c633fdd, 0xf3d333ab, 0x43adf206, 0xb7cb5382, 0xa41f30fc,
4969 0x0e5c65e7, 0x935c7062, 0xb886517f, 0xb787f78d, 0xa9c703be, 0xcb27d175,
4970 0x73fb1e40, 0x20d1d9cd, 0x1f2d809f, 0x217af4f8, 0xd6f18664, 0x7861a18b,
4971 0xc866adff, 0x7a05d111, 0xf016fb7c, 0x75574417, 0xda4ffc22, 0x284007db,
4972 0x9755c5fb, 0x7db53e59, 0x5dc7ec0b, 0x009b7f0d, 0x0e4f1ef7, 0xd2201f68,
4973 0x8355a5fc, 0x487e6227, 0xf7c816fb, 0x3f2c1c53, 0x81807dbc, 0x0921cfb6,
4974 0x76ff6113, 0x8abf193a, 0x3967bfe7, 0xf7e755ff, 0x29cf7f4e, 0x66a90b80,
4975 0x1c0b7dfc, 0xed9f94cf, 0x73b538ec, 0x9d9fdd17, 0x9fc8cc4b, 0x10bc6429,
4976 0xe1ce938f, 0xf20ee78c, 0x8df50953, 0x926b384c, 0xcf68fb62, 0x7f21736e,
4977 0x0f6ea1be, 0xb3e9d79c, 0xff3f900b, 0xac99ec87, 0xfdd2c6a4, 0xfad29a36,
4978 0xe3271593, 0xed1106a7, 0xda8fe99e, 0xda78fe51, 0x0561d6cc, 0x1b534afe,
4979 0x7c2b8fdf, 0x4c4c571d, 0xdf24b91f, 0xdacdfd81, 0x950cf946, 0x240966db,
4980 0x309c80a8, 0x81394655, 0x3341a3aa, 0xdc5537cd, 0xddd27180, 0x335ad2fa,
4981 0xd0a9bfce, 0x26760993, 0x9a693f55, 0xd44cc9ea, 0xdb4d65c8, 0x67cab958,
4982 0x5e69729b, 0x12102e73, 0xad9779c6, 0xbb424dcf, 0xf3eec4bc, 0x743b5fac,
4983 0x573c1afb, 0x9b3ae1a7, 0x68664312, 0x2fffc2a7, 0xf0c93dfd, 0xbef57efd,
4984 0x7507df28, 0xd30ac9dc, 0xec0cca87, 0xf1527e3c, 0x44cb3ae1, 0x39a208cf,
4985 0x4d03279f, 0xa448e068, 0xfdf0d1f6, 0x8c7843ff, 0xa3fdf586, 0xf1daf8f0,
4986 0x84fc71c5, 0xa0bb8df2, 0x67259aff, 0xf30cdc79, 0x5df0a9bf, 0xe98c442f,
4987 0x77b06f8c, 0xd077e804, 0x3e4c0abb, 0xe753b42f, 0x1ad1fb3d, 0xf5d4d794,
4988 0x60787f58, 0x9d99dc12, 0xc5fe795d, 0xecfdb49d, 0xf775591f, 0xa4be5581,
4989 0xae46bde2, 0x11eec618, 0x4fbb29ab, 0xe80a7208, 0x3aeaed77, 0xc4264f24,
4990 0x18afaf8b, 0x609e8228, 0x828ff805, 0xb7432efb, 0x9c18132f, 0x9caa9e60,
4991 0x08bb8843, 0x2953b3d6, 0xf97d86ae, 0xa05e2952, 0xf071b2a4, 0xa75e097c,
4992 0x03d78dfd, 0x7aeae779, 0xfc72610d, 0xefa604a6, 0xd0f10249, 0x8dffcdf9,
4993 0x811adb71, 0x13e21f03, 0xb0bb30b6, 0xc357972a, 0x79f74ee9, 0xe7e3973e,
4994 0xc17e3973, 0x1deea306, 0x3e908a82, 0xbcd89a4f, 0x523eb9aa, 0x9fb0da45,
4995 0xbd7d66aa, 0xd82faa6a, 0x83bf701d, 0x8690f1ca, 0xf9eae5f5, 0xc2f96fe1,
4996 0xa0f77fa4, 0xa361f711, 0x09f1c999, 0x8fb93d23, 0xb5fc7f01, 0xffcde511,
4997 0xc2a2fbe6, 0xf1624061, 0x8b5f00c3, 0x9ff84441, 0xec394916, 0x95c0676f,
4998 0x93307831, 0x02f5a76f, 0x9aaf35bf, 0x361f01cb, 0xffcea22b, 0x64628f78,
4999 0xcce5c37e, 0x4fbd1e9e, 0xc8133b46, 0xffbd5ac1, 0xe7d54539, 0x10ff72d7,
5000 0x129a33d3, 0xa9bedc99, 0xe9077049, 0x2b4d277c, 0x5ff800af, 0xc021699c,
5001 0x3d72e76a, 0x746a42f3, 0xfaadc031, 0x76bb4bbe, 0x7c37d011, 0x74be022f,
5002 0xc7ecd18a, 0x967fd172, 0x0fb3fe00, 0x7cef8c43, 0xfdc0eb48, 0x9dab6098,
5003 0x4f1355c5, 0xefda3ce6, 0x6ee9d5a9, 0xe3533b88, 0x641d4e49, 0x46f5cbfe,
5004 0xf3dc096f, 0xfa63ee0d, 0x574687c3, 0xeb23dc36, 0xd011caf2, 0xd744cbbb,
5005 0x7b2025d6, 0xaaf6b61d, 0x5a9ff85f, 0xfeae7180, 0x23dfa5ca, 0xfdd3d157,
5006 0xbd3d7a2d, 0x61b34493, 0x07ca9b5d, 0xfc742386, 0x6e61d6ce, 0x40cad666,
5007 0x93ad4be3, 0xd54d3dd5, 0x7187bc3a, 0xbdf088c8, 0xff91fede, 0xf0fc7ed1,
5008 0x684bf06f, 0xef681fed, 0x7a43dbd0, 0xfabed9e6, 0x7e674d5f, 0xeff2b892,
5009 0xb093becb, 0xf93fb50f, 0x0825c9eb, 0x37d228d7, 0x3e7a6469, 0xa144779d,
5010 0xb46f4fed, 0xdda77f23, 0xf9fdbde1, 0xbe053654, 0xd194b393, 0xf486f55b,
5011 0x4837606d, 0x57eac89c, 0x768a186f, 0xfedcb184, 0xea40df3b, 0x133ba015,
5012 0xa1390069, 0x696ae4cc, 0x9c63c4d7, 0x5bd267b9, 0xbcb45f40, 0x0dabca1e,
5013 0x82fcdeec, 0x8da2b6b6, 0xecc22f30, 0x02cde5c3, 0x78c53881, 0xdad115fb,
5014 0x3560a889, 0x80cdbc36, 0x55d83f4a, 0x55df63f2, 0xbf79ee3a, 0x3d26efe5,
5015 0xbf2a82dc, 0x7abd31f1, 0x9ff83a70, 0x901c7a54, 0x48cc95e8, 0xe074ae07,
5016 0x3e0c67a7, 0xe02c97b4, 0xb82b1bf7, 0x478eaf9e, 0x3be30df9, 0x281fb70a,
5017 0x2d70aecc, 0x47daa3fe, 0x0f403b54, 0xf294b3be, 0xf37d119d, 0x0aea421d,
5018 0x80f84ed1, 0xd2740dcd, 0xfe70ff83, 0xba53eea6, 0xd8d0f8cc, 0xd10321a5,
5019 0x6497b9c8, 0xcd3697cf, 0xa3ffe2b9, 0x826eb8a2, 0xb40c97bc, 0xbe365c81,
5020 0xf70a91d2, 0xcebf98dc, 0xdb3c46da, 0x662df7e8, 0xfed02f2a, 0x90b871ee,
5021 0x0cc8647f, 0x97928c0f, 0xa2f2d214, 0xfb9436e2, 0x09c4a9a3, 0xc6decefc,
5022 0xa762dffa, 0x3b4246ed, 0xdbba77c6, 0xa2dea42b, 0x2afc5f69, 0xe9725fbb,
5023 0xdfed1da0, 0x734b1297, 0xbe748f80, 0xa77e476a, 0xba53bbfa, 0x8958d5df,
5024 0x1e1db9eb, 0xd5854a45, 0x3d03f715, 0xfb93088b, 0xd86277b1, 0xf46358b9,
5025 0xe9ff00e5, 0x9644d778, 0xe08b7ed3, 0xbc54a231, 0xef0257b7, 0x2ebed536,
5026 0xca486400, 0x8216772b, 0x5864d91d, 0xf7428f74, 0x34b0c4a7, 0x576d08fa,
5027 0x04e6c033, 0x9cc4c293, 0x7de7fd3f, 0x5ed1ff34, 0xaba7de23, 0x266139d8,
5028 0xa2fad1d8, 0xa2fbf8ff, 0x7975bf74, 0xbcbabfba, 0xbf9f45bf, 0x814f6cd7,
5029 0x36942cfb, 0xd8cf70dd, 0xb73baa64, 0xf4d7ce8d, 0x354dc99a, 0xd9b37211,
5030 0xe81980f7, 0x071e8c5d, 0x3a729978, 0xe17c8046, 0xc044fd6f, 0x559250f7,
5031 0x072f80ff, 0x9992e7e8, 0xf3efb3c1, 0x9eec289b, 0x6967551d, 0xc36d94da,
5032 0x597a68fd, 0x6f8c0908, 0x045d194f, 0xf7e130e7, 0x97183c4f, 0x265367e5,
5033 0x4cfefc4d, 0x68437ed3, 0xded79c19, 0x5c27bc72, 0x856bcf4b, 0xb87177e6,
5034 0x8b47d557, 0x53445ee0, 0x3061a4d2, 0xc90be92f, 0x0abbfb0b, 0x17c8d13a,
5035 0x3fe2cdcb, 0x115a3f76, 0x2d89efe2, 0x7b873a07, 0xf8e9e39b, 0x0cf8bee3,
5036 0xe8532ee3, 0xc9cfc030, 0xee376656, 0xfda21652, 0x43ae6fda, 0x44b8d5bf,
5037 0x60b5d709, 0xa0242d80, 0x9f20991d, 0x3932260c, 0xcb41611a, 0xffb986cf,
5038 0x0b4e0e3a, 0x9ab930b6, 0xbbe033ec, 0xc1400b31, 0xd5fbb902, 0x700f18a9,
5039 0xc9a7f376, 0x5b6e01e3, 0xbb0270ef, 0xccbdf5a2, 0x8369e78f, 0xada4bbf7,
5040 0xbd0172df, 0x6262db1f, 0x765448f3, 0xfb8f7ec1, 0x837280c2, 0xc81f1224,
5041 0x67b24d0d, 0x6b91d018, 0x8012cef3, 0x59a9d9eb, 0x517fd622, 0x37184e20,
5042 0x7c1a4971, 0x5e48205f, 0xfdfa3f46, 0xa26bf753, 0x05c99939, 0x7f782b86,
5043 0x4db4d8fa, 0x3e3dcf18, 0xc6f7f367, 0x8d3b7f42, 0xd2846f78, 0x3e703dc7,
5044 0xc0f5d0d4, 0xbcb66a7c, 0xb38cc693, 0x628a4484, 0xa3fcdbef, 0xaab26074,
5045 0x07975c78, 0xf2c16c7c, 0x3bed3cba, 0x78f03d1e, 0x1b9ba533, 0x166078a9,
5046 0xaf2097c8, 0x35ea4ff7, 0x1e5e293e, 0xc54af555, 0x6d3b3c4d, 0x08f3d768,
5047 0x329d3f94, 0x4e47c84b, 0x27ac6599, 0xf3616dfd, 0x3f105cef, 0xd02dfbeb,
5048 0x60f10e5f, 0xea2b853c, 0x0ee2a62c, 0x69cf0080, 0x9fc599b2, 0xf51f73d1,
5049 0x44a9f5a0, 0xffd1aef7, 0x3a51fde5, 0xb2f0077e, 0xc72bddf3, 0xd9b5ae01,
5050 0x8f40231d, 0x0cfe5ff0, 0x56b65eed, 0xb9b4f766, 0x0d9e64bd, 0x992a7be8,
5051 0x83e3105b, 0xcfe3377e, 0xd1baebf1, 0x63f16462, 0xc7ec5129, 0xd7f4656a,
5052 0x4df6f5c4, 0xf7a82c4b, 0x99094a6d, 0x955fd261, 0x573f54ce, 0x2a63b705,
5053 0x7b415e3b, 0x4e09090e, 0x2e296bf0, 0xe55d2746, 0x3fcf11b3, 0x882831da,
5054 0xd1e3bdf9, 0xf1db65af, 0x8040c35c, 0x83f30b53, 0x0eeddcd9, 0x3b47df58,
5055 0x7d60394e, 0xb80c3be5, 0x27d0f2ee, 0x620af369, 0xf049bd74, 0xfaf3c15d,
5056 0x46b59d0a, 0xc768fb4f, 0x6d7369a7, 0x730a4f4c, 0x706f417b, 0x2f1952f9,
5057 0xc65c2858, 0x751d9839, 0xf7c453dc, 0x386de232, 0x4f6f6b5b, 0x6af3b0b5,
5058 0x0dc9859c, 0x7ad0d6e3, 0x7c618788, 0x1ebe29cf, 0x57a32079, 0xf8fc6d3b,
5059 0xb4441be7, 0x26ac56a3, 0xff3d6768, 0xf46c81fc, 0x903cee6b, 0x5f53473d,
5060 0x6f8c3f8d, 0xf1616d9f, 0xa7f1a41f, 0xe20d251e, 0x7378d83d, 0x2007cabc,
5061 0x3b86909f, 0x1e38fa3c, 0xbd4d130a, 0xa7c40dae, 0xefd58a0c, 0x01dcff2a,
5062 0x5a736a71, 0xb413110d, 0xa70678f7, 0xebcbbc80, 0x2f77f7c7, 0x45a123c7,
5063 0x5ac93d40, 0xfa3e4510, 0x1134f9b5, 0x4d3e5a6c, 0xe324f7f7, 0xf0e3d1d3,
5064 0x19d813ee, 0x6b933ce1, 0xf5c8126d, 0x5e182b69, 0xa2207f45, 0xc435ddfc,
5065 0xf9522f52, 0xb0cace45, 0xb14aff01, 0x01acb8b0, 0xbf58f959, 0x1a679efb,
5066 0x4999e7bb, 0x8a7e30ea, 0x1f51db38, 0x38863fee, 0x580d0e41, 0x41911c98,
5067 0x830c1bdc, 0x7a3c9820, 0xf10151ea, 0x8e7c03c4, 0xa9ea0a88, 0x3f185f14,
5068 0xfa33e477, 0xf952f0e6, 0xa02ad0a8, 0x92db371c, 0x862bf5c8, 0xa3c2d757,
5069 0x3c62ffd9, 0x778ea05a, 0x12e478bd, 0x5be1f5c8, 0x1fc2761f, 0x845fb828,
5070 0xf0a771fb, 0x3628a67e, 0xb880af7c, 0xf1dd1d8d, 0xcd9fb464, 0xfd04de54,
5071 0xf62bb541, 0x62ea515b, 0x76b6e07e, 0xdface790, 0x7c5cf052, 0x05cb6c5c,
5072 0xcede3a79, 0x11367748, 0x533801ce, 0x1f94bd61, 0x5797fb30, 0x9d71fbc6,
5073 0xe21b8f01, 0x44880607, 0xcfdf3e02, 0x35ef8b90, 0xdd380bf6, 0x59dc182b,
5074 0xbb1e631c, 0xb12b5c0f, 0x075942fb, 0x1772c912, 0x5f4cc7c8, 0xcb8eface,
5075 0x78b52e0d, 0x225346ff, 0x7ea987b3, 0x69ecbef7, 0x9f4f41a4, 0xcbad5daa,
5076 0x537e174e, 0x0659ce0c, 0x85049f3e, 0x41ee4fdf, 0x35c00ae7, 0xff510c6d,
5077 0x4b3e4036, 0x14fe37cd, 0xae957bcf, 0xbd9d7b55, 0x736b9bc0, 0x7abb9213,
5078 0x8be031dd, 0xb8e7efd7, 0xfdd5e57f, 0x025dff1c, 0x9e7a0e7e, 0xb4c39776,
5079 0xe6ab39e9, 0xae12203d, 0x21cac7b2, 0x11695ece, 0x2575fb78, 0xde5c4877,
5080 0x3ee7f1c2, 0x3caaef06, 0xf1ba266d, 0xe293f3b4, 0x629087fa, 0xdfad4b9b,
5081 0x5bfa1138, 0x83e79237, 0x5f83d41f, 0xbea369e7, 0x6f29043f, 0x029a990f,
5082 0xc9f07fd6, 0x1a9fc741, 0xe1ef3b1c, 0xa97807fc, 0xf7aafee7, 0x44de34a6,
5083 0x3f3ab2c7, 0xf50778c5, 0xf4a7f6fc, 0x24e22f7e, 0xff5fe3e7, 0x761e841d,
5084 0x261693ca, 0xc90096df, 0xf9003d51, 0x17a97fb2, 0x9ca825e3, 0xb7cc21f1,
5085 0x338eddf3, 0xe7796847, 0xf78fcfb4, 0x7d6e3c03, 0x31e83678, 0xfa03b7e0,
5086 0x501b37f1, 0x055a55ce, 0x462d6f86, 0x7f1517a4, 0x7f1c9d2a, 0x7f788312,
5087 0x3090e9b0, 0x5445ec1a, 0x9bbecd3f, 0xd5b165ee, 0x31c70173, 0x533fdfea,
5088 0xeccad953, 0xe2fcfe56, 0xffd0798d, 0xf9c0810e, 0xc3ff26bf, 0xbfa8b9b4,
5089 0x4f36907c, 0x65a2aed3, 0x691f8b1d, 0x470af636, 0xfa606ad9, 0x1e7dc1dc,
5090 0x43e70be0, 0xca4b1618, 0x906ad0a5, 0x45cbcb57, 0x8546efd4, 0xbe43ef4a,
5091 0x2026533d, 0x5c587787, 0xd3cd1e6c, 0xe42f1083, 0xbf81ffa7, 0x7e77936a,
5092 0x3347ca29, 0xd5c41b15, 0xce2fcf9e, 0x5795fb44, 0x061c0276, 0x926537bc,
5093 0x149ef80b, 0xadb4b8c6, 0x2091b6b5, 0x83efadd7, 0x63693ecf, 0x782f5cfb,
5094 0x7e67df83, 0x5bb5a271, 0xf930b4e5, 0xe4cac32e, 0x867bf541, 0xb79dc995,
5095 0x0026db05, 0xda961c3a, 0xfaf720ad, 0xd013e789, 0xe6d7894b, 0x0f7089da,
5096 0x129ddea3, 0x4d3da170, 0xfc7f6949, 0x4dbf2826, 0x223b38c2, 0xe3033fb5,
5097 0x894eae76, 0xfc850bdd, 0x6f680523, 0x1beacc7b, 0x14e3a562, 0xf3b27971,
5098 0x10859de0, 0xe1ce38d7, 0xe824c9fa, 0xed0973e7, 0x8a9ee33a, 0xf8004db6,
5099 0xd9903e7d, 0x08e895b9, 0x9376b9ed, 0x9e93ad95, 0x92ef286f, 0xfbf237c3,
5100 0x1d9eb40a, 0x5a16f1ba, 0xb8de4153, 0xfd18f458, 0x24694c6c, 0x7d549f80,
5101 0x9282bb40, 0x872025e2, 0x4a96084c, 0x271cb718, 0x71e04c87, 0xf4a4881d,
5102 0xfbc7317b, 0xe1777421, 0x558a2dfd, 0xc7265ff5, 0xaeb792e4, 0xa3e090cc,
5103 0x8a88af2a, 0x1399ed0f, 0xc6085a67, 0x1e8cafd3, 0x9e2ec117, 0x0a7af942,
5104 0xf160cbde, 0xb32ff9a2, 0x466120fb, 0x3ffeddb7, 0xa8fd1da9, 0x7e56ad93,
5105 0xfc33d7ae, 0xb7186d21, 0xb0900940, 0xd6cf68fd, 0xfd5057de, 0xf27f6a86,
5106 0xad8f6672, 0x7c17f6e1, 0xdf9696f9, 0xb2ed556d, 0x467e75cb, 0xf0bedc75,
5107 0xc6aac2ab, 0x804b4453, 0xd507a31e, 0x4a4f8a78, 0x8cfa2f00, 0x5778e0a7,
5108 0x78f572db, 0xd195bf0a, 0x4f1d37c9, 0x913588f1, 0x11f44bc5, 0x471f114f,
5109 0x911999d1, 0xda4b5ed0, 0x7d04eeb7, 0x7e84c5bc, 0x6f2d29db, 0xcbce11fe,
5110 0x43090a29, 0x5cbc56dc, 0x5f4d35e1, 0x75def80e, 0xc056cce1, 0xef7775c3,
5111 0xb03f3377, 0xd7885e5e, 0x7cabb60f, 0x1b73cb97, 0x1fa7d7ad, 0x29bef5a8,
5112 0xcbe54eb9, 0x5187ae7e, 0xb9c072fa, 0x23d383b3, 0xd1c41250, 0xdd6dcbc5,
5113 0x1c9c7ef2, 0xd19eff11, 0x9d6f69a4, 0x61a47bc1, 0xa87100b3, 0xde0919af,
5114 0x63ee0dd3, 0x85b56dfa, 0xc3ea93f1, 0x2ca9fdec, 0xe3ed1793, 0xf22315e4,
5115 0xf9e57f0d, 0xfd114497, 0xdc00af04, 0x27e5a653, 0x5faefd40, 0xd50e901b,
5116 0x85b690f7, 0x2a74fc98, 0x94c88c5f, 0x79c1b7ce, 0xa13ce30c, 0x3d741bf7,
5117 0x31f18fd9, 0x5ae837ee, 0x9706fccd, 0x6033e3cc, 0x330ecaf3, 0xb7197ffb,
5118 0xf14aafff, 0xae8332fd, 0xc64ff16b, 0x1e75dda3, 0xd65a61f1, 0xc71bb7a0,
5119 0xbfccbdec, 0x78af0554, 0xcc05fbb3, 0x8fb1a7df, 0xae523bc1, 0xce18a906,
5120 0x5ce25ca5, 0x15d97c0e, 0x16fdd0a4, 0xbbf9eb4d, 0x802882c3, 0x4ead213c,
5121 0xac7ec0b1, 0x012717aa, 0x45eb05bd, 0x5bb88f7c, 0xd7e7e00e, 0x29ffce25,
5122 0x8e3042c8, 0x77f3d69a, 0x96fed57b, 0xa9023111, 0x9574b028, 0xdbd49a53,
5123 0x57f6a8b9, 0xc653ac6f, 0x4034be83, 0x25ecbb44, 0xe01333d9, 0x8f29297a,
5124 0xbd645c40, 0x1261aebd, 0xbf1c472b, 0xb17a8e64, 0x1312dbfc, 0x092b88d8,
5125 0xfcdbd9f8, 0xdb878edc, 0x3838c6bc, 0xe3f3d9c6, 0x88cb3ee3, 0xa0e6686f,
5126 0x6f92719e, 0x69733e73, 0xbfbf2e4d, 0xaeaee0c0, 0x067f597f, 0x4b007137,
5127 0x9e280e07, 0x303ffb09, 0xa04d8651, 0xd223b329, 0x07fce095, 0xef053b7e,
5128 0xb7cfc513, 0xc023841e, 0xbdecd5ab, 0xff3aaf8f, 0xddff79f8, 0xcce9c69a,
5129 0x5f780193, 0x3df194e6, 0x17d96baf, 0x705cb972, 0xd6a1fe2d, 0x07f806fb,
5130 0x1b578bd3, 0x13adbc78, 0x97bc08f9, 0x04a77f08, 0x9e08aef7, 0x79d5a1df,
5131 0x06d5aeb0, 0xc27e1f7c, 0xef9e1b74, 0xfbd987b5, 0xdb4b3576, 0xad9ce1b3,
5132 0xf7c76e2d, 0x0de1e36b, 0xfe5495b3, 0x49cdeb43, 0x1c6ef821, 0x79fbd069,
5133 0x3cb3fa7a, 0xd3e03645, 0x37aec8c6, 0x654338e9, 0xd7c858df, 0x02ee8d2e,
5134 0x91e3b579, 0x5e404af7, 0xd26f539b, 0x2792a7c5, 0xd2227ef4, 0x65768490,
5135 0x5effa4d2, 0x5dae39be, 0x2351bf0f, 0xd97ae3e2, 0x7be80c37, 0xd3f9839c,
5136 0xef88a549, 0x01db75fc, 0xe1ce1a9e, 0xeed3cee7, 0xee7d03ef, 0xef67ad2f,
5137 0xf77aef59, 0x2fec02f7, 0xbe6ad7dd, 0x7df617bf, 0xb7f60f2b, 0xf2b7cf63,
5138 0x1bd77f60, 0x3f403d1b, 0x0f9f153b, 0xefa73cfc, 0xa39ca2f0, 0x0b5c45c6,
5139 0x275d172f, 0xe6fa2e5e, 0xe7aaf2f0, 0xcaa6c05a, 0x5ced5f49, 0x9ead3f83,
5140 0x218af87d, 0x34bf4668, 0x3d98ffc3, 0xf077fcec, 0x0a2cb95c, 0xabe8f7e0,
5141 0xae5c51bf, 0x104850cc, 0xc54513ec, 0xe8aed8ed, 0xdc809173, 0xf179caa4,
5142 0x9f09f870, 0x4f36f3ff, 0x5f879c02, 0xce5aeed7, 0x4fa128eb, 0x43b9fc99,
5143 0x6bbb3370, 0x1dd5c598, 0x9d82752a, 0xd9885cf5, 0xb1f76b5d, 0x422bea77,
5144 0x5df0446f, 0x09c156f3, 0x8ec541fa, 0xeef01c0f, 0xae4e2690, 0x448ce819,
5145 0x9deceff5, 0x40729d0b, 0xb79d1bbc, 0x6b78e415, 0x7a06544a, 0xf1172da8,
5146 0x295ab3dd, 0xb5bcf18a, 0x241dc429, 0xf5ea5f20, 0x6c2e352d, 0xba465793,
5147 0xdecad4d9, 0x7d934ca1, 0x0f11fdb9, 0x6dfbe3fb, 0xb7edfd2a, 0xf800fe79,
5148 0x7ad3f31b, 0x8b576c5a, 0xc32ff91b, 0x617fe636, 0xccd97fe5, 0x6e3502e4,
5149 0xce8ff544, 0xf3eef1e7, 0xf83bbc79, 0xf81a236d, 0x9b56df82, 0xd5b6fd57,
5150 0x88322f10, 0xe5b56df9, 0x8d687edd, 0xae5b56df, 0xe889178d, 0x93234df8,
5151 0x310b0d77, 0x25d2864e, 0x579163c6, 0x88ced505, 0x74a7e9f4, 0x0c6464b0,
5152 0xf0fdd57f, 0x12b87f97, 0x3cfcf3e2, 0xf01ab2ee, 0x61c60477, 0x5fc04c46,
5153 0x355f14c3, 0x4b6a2efc, 0x7d7374e4, 0x37e8c8f6, 0xedf1df4c, 0xe3c7573f,
5154 0xb3aead74, 0x02ad5d7b, 0x75b8c3a3, 0xf189ebc5, 0xcf5569f6, 0x4bdf16bb,
5155 0xdf1f5fb6, 0xabfdeb53, 0xfdb65ef9, 0xbef7c39f, 0x47fffb29, 0x3034c6ae,
5156 0xe87b3e05, 0xd083df87, 0xad8312a4, 0x4c9477fb, 0xae3fe1d7, 0x437062d9,
5157 0x21cd4ddc, 0xaaf21bbb, 0x7fde323f, 0x94f64958, 0xfde3c800, 0x5710d588,
5158 0xfedae831, 0xb77b62c4, 0xfb573d5f, 0xb151785e, 0x61bf5f9e, 0xa7d934fb,
5159 0x02e2d3c1, 0x82f7e02a, 0x24148ab7, 0xa9f638da, 0x7eb7e676, 0x9fefbf83,
5160 0x88069321, 0x6eda7893, 0x14467bc5, 0xa62e306b, 0x6e9dead8, 0x9afc0d1f,
5161 0x83d9efc1, 0x0b8812f7, 0xc618d67e, 0x1ac13efb, 0x5727de1b, 0xff6a23ed,
5162 0xa97ea96f, 0xcd73e06b, 0xcd73e275, 0xf1cf8c37, 0xe3ab17ed, 0x61dfaf5d,
5163 0x06918503, 0xb3f1e3df, 0xf17d76af, 0xef765581, 0x91d23b72, 0x5eb9ef07,
5164 0x11e8ff2f, 0xf1b92987, 0x4dc41d5e, 0xfc559c42, 0x74f7a87e, 0x6b70b954,
5165 0x97a1fb9f, 0xc57eb707, 0x3c96b8fd, 0x0de2a4f8, 0x8f4f7ac1, 0x3e81e4f7,
5166 0xeccecabb, 0x0ccd9b2e, 0x0c0b372f, 0x13e07b1f, 0xe2a3efbf, 0xf5fb01d5,
5167 0x7ad43bd9, 0x78fe6aff, 0x2d7c2ed4, 0x69fc077b, 0x886c90f1, 0x7d767be2,
5168 0xfe9ec7f2, 0x5977162e, 0x517a86dc, 0xef8090f4, 0xf6f3ab33, 0xd63b31b7,
5169 0xd45c39ef, 0x1cb8fbef, 0xfcf0e398, 0xf10a9ec1, 0x8f028a49, 0x59028c3b,
5170 0x2f28e40e, 0x0da9378b, 0xda8fb8b3, 0x70e304a5, 0xb511fbd4, 0xc809532d,
5171 0xbecd0b6d, 0x55fb433f, 0x8682d9ef, 0x4fa3b004, 0x75a72023, 0x37f2cbbe,
5172 0x401f7d9b, 0x3b697fb9, 0xa69bfdda, 0xa138c79d, 0x5d3f2fa2, 0x3a5df609,
5173 0xa40bb45f, 0xd3f7f498, 0xc7c60e1d, 0x50ead4d4, 0x7b41ebe1, 0xfb950778,
5174 0xa7f2de40, 0x5f609c78, 0x56cded50, 0xe1da1b57, 0x6732f76b, 0xad81915f,
5175 0x9fda3c87, 0x8ef6d1f9, 0xe415fc2f, 0x9042e6c3, 0xb7de8b57, 0xe3a8fda1,
5176 0x138c2c91, 0xbbeacc78, 0x1f6af80c, 0xe40bba15, 0x0e3a1ccb, 0x7b1dadc8,
5177 0x79842aee, 0xe0a17d77, 0xccecbaba, 0x24f5d0bf, 0xcaf88999, 0x665dd1ed,
5178 0x9f022786, 0x666ad76f, 0xba1e0a9f, 0xdd03bf91, 0x38368f6d, 0xd1ecc746,
5179 0xa5407cf1, 0x08fbeeff, 0x1ff414b3, 0xbd61fcab, 0xeaa39d91, 0xeece77f9,
5180 0x3c16f1e2, 0x2a75aeae, 0x79e0d78b, 0xf8554f1b, 0xe3bb6f3e, 0x9cf3ac1c,
5181 0xdec7fa5d, 0xe24cbec3, 0x2fd8e7fd, 0xe36939c4, 0xdfe0add5, 0x53897b01,
5182 0x37b2bc46, 0xa1dfe610, 0xf9f20578, 0x09b6d16d, 0x839d7409, 0x01b7229b,
5183 0x165f0fbc, 0x53a0bbd9, 0x92f78b7f, 0xde360413, 0x57da27a0, 0x8afb050f,
5184 0xc36fedf3, 0x9d1abad6, 0x5b92e0c5, 0x870ef668, 0xd52241b8, 0xc578c3e5,
5185 0x3c5918ef, 0xda2b21df, 0xabb29a09, 0xbb691273, 0x684cf7ce, 0x03e789af,
5186 0xcb241a6a, 0x606f8e31, 0x0ed01fcb, 0xe82bdf6f, 0x93a6a6e0, 0xf7e6361c,
5187 0x6095b609, 0x296dc9ac, 0x0e6e77ec, 0x7f041fbd, 0x5f1ab4bd, 0x46f52486,
5188 0x7572088f, 0x7b411970, 0xa72690e4, 0xc395fb08, 0x0eba44e3, 0x1f08cfff,
5189 0xddaa9f9e, 0x64a9843d, 0x7a095f6c, 0xfdacb495, 0xc7ec20f6, 0xb6b144de,
5190 0xd68bfa00, 0x12b27c32, 0x5a739f38, 0x95bf2d06, 0x9c1a73e6, 0x7aea3fe8,
5191 0x0de30ab5, 0x439d7483, 0xa167597a, 0xdce5c583, 0xa520e3c8, 0xfc115643,
5192 0xb85ad2d2, 0x5341440d, 0xd29671ef, 0x129c43f6, 0xc38e7de2, 0xd4f00b37,
5193 0x5902f9ca, 0x9c7f4162, 0x6d78625d, 0x8bdef25f, 0x55bfcf10, 0x1d4fef66,
5194 0x34e37c3d, 0x96addfb4, 0xc6ab5ed0, 0x74e02e51, 0x47de13dc, 0xe0725e31,
5195 0xbf303fa1, 0xfa0b1d0d, 0x3f0c8c97, 0xf829d5a4, 0xc87fe07e, 0xfd0b8c3e,
5196 0x80c47d76, 0xe9e728fe, 0xaeb92667, 0xebc4b7ad, 0x891ccb29, 0x622e295f,
5197 0x3d9be399, 0x3fdbe24f, 0x55f78eae, 0xd7a210f5, 0x63e87acf, 0x5c7572f1,
5198 0x0ee4befb, 0xf542ee35, 0x504f1177, 0xcc526f17, 0xbe8a21c7, 0xef0b6abf,
5199 0x50a3c78f, 0xf205c439, 0xd70ada4e, 0x8ebf8832, 0xdfa098fe, 0x09978d46,
5200 0x9738b316, 0xbde0a8a0, 0x88d20cab, 0x48fd3271, 0x1ed01044, 0xd3b6e2c6,
5201 0xb6865e21, 0x8818ef5b, 0xee216ffd, 0x41f20306, 0xa4abbe17, 0xfdd055c6,
5202 0xd3243a41, 0xc13f1e64, 0x566b37f0, 0x70e2085a, 0x9f7edcfd, 0x7f1f2b35,
5203 0x3f135567, 0x33feecc1, 0x7d4f882d, 0x10aa53de, 0xd6253df9, 0x1710d36f,
5204 0x4d7ff3de, 0x693e6bb5, 0xe2e3ed67, 0xaa38542c, 0xfc2a1671, 0xf14c7bd4,
5205 0x79314c70, 0x57bc02df, 0x7dd425e3, 0x0d8fdeee, 0x55d82ecc, 0x1cbbe221,
5206 0x155d7f6a, 0xdc83679f, 0x626adc50, 0xefd712f8, 0xaefbeea6, 0x67c63321,
5207 0x96bd7df3, 0xdfbeaa1c, 0x23bf9475, 0xd7bf8c75, 0xc21665de, 0x399f8006,
5208 0xc9381b3a, 0xee4784f6, 0x5d817b84, 0xdc3668f6, 0x78dcdc2b, 0xa7cc24ff,
5209 0xfe424f46, 0xc3ff84b5, 0x5ba243f2, 0x89e19ee1, 0x1e58b3a7, 0x908b2e70,
5210 0x49848e33, 0xe07f82c1, 0xe3d73a5c, 0x022e1a77, 0xfb486b1c, 0xd3b436ca,
5211 0x146973f0, 0xa26463e3, 0x44ecc429, 0x13ffdc2e, 0x631dec99, 0xbdc0fe5b,
5212 0xdfde506d, 0x5a2df684, 0x627bf88e, 0xee5678c8, 0xfa4dfb62, 0x029c59db,
5213 0x13d33dff, 0x1fd1e3b9, 0x4df8035e, 0x462b85e5, 0xc740989f, 0xe1b420bf,
5214 0xee27593b, 0xe00161f8, 0x8ffd85eb, 0xe2b9060e, 0x77f7b94e, 0x72731ee1,
5215 0x7ec8c239, 0xa34de5f7, 0xf9409acf, 0xb3ad1fc3, 0xff69124b, 0xcbc79333,
5216 0xe0ef3089, 0x51eef8f3, 0xc4bfdf2a, 0x4bee4c19, 0x2015e89c, 0x3363f17e,
5217 0x1f54b3a3, 0xe2063dfb, 0x3ddc219b, 0x12d7235c, 0xc4113bf6, 0x7b804ae7,
5218 0x68eff108, 0x6b5e12dc, 0xf7f73900, 0x780ce881, 0xfefd5552, 0x38f7a107,
5219 0xc604828b, 0x5c19a6c7, 0x141f01c3, 0x29cdf1b1, 0x2bc6c4b7, 0xfbf17048,
5220 0x70a375c5, 0x51ba86dc, 0x28f4c7a0, 0xd072d1b7, 0xe5a09e93, 0x97297bc3,
5221 0xd67afb78, 0x938ef35e, 0xa974e01b, 0x2fbc03f4, 0x04eb38b4, 0xc27647be,
5222 0x0ef03c48, 0xfb93304e, 0x0739e8f5, 0x273c7dfb, 0x3b4fc591, 0x40704c37,
5223 0xffdb107e, 0xfd0848bb, 0xb06653bc, 0x21df597b, 0xb4edf56d, 0xfa199dde,
5224 0xcbb963df, 0x277fcfa5, 0xc29f9f5f, 0xebbe07e3, 0x1eff7fd6, 0x0f804a89,
5225 0xffa31fdf, 0x441797dd, 0x0be0094f, 0x2f8c27e5, 0x2aee3c0a, 0xf9c20845,
5226 0x2c81e37e, 0xc61a9ef5, 0xf5c0bdb3, 0x7fbf3f11, 0x91aa6701, 0x8586e3ae,
5227 0x1bdc9dec, 0x93928833, 0xf92bfc04, 0xf07bbe08, 0xa729f711, 0xf4789bc0,
5228 0xd713a97b, 0xf419e2af, 0x1f7c3b75, 0xe2e0cf9d, 0xd2538321, 0x418eefd8,
5229 0x6b2309d9, 0x84b1fc1b, 0x7d684e7c, 0x3e2c6ff3, 0xf184bc62, 0xd7ab0277,
5230 0x4ff86665, 0xfefc524f, 0xe21ede53, 0x27c89caa, 0x4abfdc2d, 0x8be85df0,
5231 0x78d8d2a3, 0xfa8b0f1c, 0x5bc01629, 0x7cbb5df5, 0x1bf6e127, 0x7069a64a,
5232 0xe794103e, 0xfd54bc54, 0x3c380348, 0x7f327e28, 0x1f872671, 0x06f7f091,
5233 0xcfda8932, 0xadc61374, 0x04bafcf1, 0xde2a6f46, 0xb5ec7fae, 0x5f00a737,
5234 0xc03f5c12, 0x3bb2ee7e, 0x74f9bd61, 0x804999ac, 0x78d829bf, 0xf449e707,
5235 0x247927bb, 0x8c5d8798, 0xb09a1b18, 0xbf7f307c, 0x4fa4fa6c, 0xfe1a4866,
5236 0x61adfb45, 0xfdf55afd, 0x459ba3c2, 0x68337e9a, 0x7e9a49bf, 0xf2c2689f,
5237 0xbfe5fbbe, 0xe7e92147, 0xaf8fb6a7, 0xf3f5ea4f, 0x7c7dabec, 0x14f7f53d,
5238 0x4df87326, 0xf329e356, 0x640f71f5, 0x7e615b8c, 0xc39c7d6c, 0x8edf1c9b,
5239 0x306dff5b, 0x09250be8, 0x2844a70f, 0x1a524c3d, 0xf408dbeb, 0xd0fa461b,
5240 0x802ff5d0, 0x7e652e2e, 0xb6fbbf80, 0xd989e078, 0x97a519d0, 0x7ba309dd,
5241 0xe7c547ce, 0x3c5179ee, 0xf1543c06, 0xdd9e7e38, 0x30bdfc78, 0xa16d7206,
5242 0xaaa407f2, 0x9d48423c, 0x0d70eb80, 0x2283ad88, 0x87528961, 0x22b37ff3,
5243 0x33bdf388, 0xff8c19f1, 0x3be49319, 0x799af302, 0x3dec27d3, 0xa1d28c93,
5244 0xf9d10720, 0xfd484d1e, 0x355f377f, 0xe1dc796e, 0xbd82373b, 0xe3ee9bb4,
5245 0x5fed5ce8, 0xf234d395, 0x2af73b15, 0xf2be5545, 0x19642900, 0xe57cb832,
5246 0xacd678c2, 0xf10dcb80, 0x8af91aaa, 0x44d547c9, 0xeece07bd, 0xa060fced,
5247 0x987abe5e, 0xb76ebc60, 0x271a557c, 0xede3cd5f, 0xc42092a7, 0x93d936c5,
5248 0x805e2c42, 0x162d39ce, 0x8db4dbff, 0xb74d8dc9, 0x82419cb8, 0x33d31672,
5249 0xe87bf166, 0x6bde4cb9, 0x77c98fba, 0xbaea1ce3, 0x6b78fa2c, 0x133567ee,
5250 0xb8b12f2a, 0x99abb40c, 0xa5d97d9d, 0xb53576f4, 0xf202ffde, 0x007f0832,
5251 0x00007f08, 0x00088b1f, 0x00000000, 0x7de5ff00, 0xd5547c09, 0x73b9f8b9,
5252 0x64cacb67, 0x109848df, 0x424e3b08, 0x875b3612, 0xe22948b0, 0x3cb888b0,
5253 0x4240b21c, 0x3eb44196, 0xc33fedad, 0x0d220222, 0xc168d46d, 0x2a14180e,
5254 0x0431a0d8, 0xa4587049, 0x141a87d0, 0x2f1f682d, 0x48145840, 0xad88a0c6,
5255 0xbefbffcb, 0xef726e73, 0xf6b42264, 0xfa7fb6ff, 0xef7397b3, 0x6df3be59,
5256 0x39ce5be7, 0xd78deec3, 0x1ec658b1, 0xacc630b4, 0x98eb458c, 0xb19436b3,
5257 0x96eff0ef, 0x95e5e7ae, 0x6289e63a, 0xa31574ac, 0x47d7e5e7, 0x7a83cfa6,
5258 0x4c8c7697, 0x66e783cf, 0x92d433b3, 0x50e158cd, 0x2fa18a7b, 0x7b46f963,
5259 0x9b19933a, 0xbeb45e64, 0xcc9eba19, 0xd393f516, 0x5b09fb18, 0xcf074c74,
5260 0x48ce9151, 0xc8673fac, 0x287a2967, 0x0379f8b3, 0xfd8c611c, 0xc28f675e,
5261 0x19b98cf7, 0x718535c2, 0x4398a6b8, 0xf870f2bd, 0xa5c340f7, 0xfe8c8196,
5262 0x1c7183be, 0x4b6f6726, 0x1155630c, 0x67971fb5, 0xa35cf631, 0xe2b6e6c9,
5263 0xec1496d7, 0x11deb18f, 0x043086e7, 0x543ce185, 0x39e814f0, 0x4cb2d13c,
5264 0x040bf4f0, 0xc65e630f, 0x68e0ba72, 0x94ae8437, 0xb1e0a97a, 0x00d17eb3,
5265 0xc7be24a7, 0x06895ab1, 0x6a5383f3, 0x1257e3fc, 0x33d38fd4, 0x63265877,
5266 0xea97981b, 0x1ce75efd, 0xb3c6e381, 0xb8e1894a, 0x112b6c2b, 0x96e0dd4f,
5267 0xbf30c901, 0x1ec977d9, 0x0ae60c13, 0x7ace1f09, 0xd4fb3d61, 0xba7f1804,
5268 0x2af67f18, 0xac0884c7, 0x78e25d37, 0x00ffc2f0, 0xfbe219fe, 0xa9b2c6f4,
5269 0x3198e00c, 0x13ba70c1, 0xa66ff83e, 0x0181ba65, 0xc2a6b39c, 0x7bd7737b,
5270 0x61d2209c, 0x2cffd28e, 0x6c39bb6d, 0x387267cd, 0x10191696, 0xd5ee735f,
5271 0x09669f7e, 0x42173e8b, 0x077c076d, 0x60603af3, 0x79f68f34, 0xe609b3cc,
5272 0x82cc56f1, 0x3347f7f5, 0x43b7e036, 0x7fe86533, 0xcd716c62, 0xf4bf283a,
5273 0xbf2a60dc, 0x83cf7b15, 0xf3fbf147, 0xa09e54e9, 0x6e504683, 0xb3ce99ff,
5274 0x9cd01529, 0x5494d773, 0x9040ff18, 0x467ef7e8, 0x9d83e3ef, 0x5ea1d355,
5275 0x99bef0fc, 0x04d3e0cb, 0x0aede323, 0xde9ff7f9, 0x9ce54614, 0x191eacfb,
5276 0x6c109cba, 0x30f7d375, 0xaa09b6c9, 0xd130c91e, 0x53e361f7, 0xccbef7f9,
5277 0xe7df851e, 0x23fb5185, 0x0b5e2199, 0x47f2f78c, 0x01fbe883, 0x0eb9b3e9,
5278 0x595b5120, 0x52e91ea8, 0xe336689e, 0xc940c873, 0x3df0083b, 0x5f8c5221,
5279 0x353de7c6, 0xca226b73, 0xdf5c84cd, 0x6850c75c, 0x670e6897, 0xfe1f1137,
5280 0x8879f90c, 0x34aadc6d, 0x5f16afe4, 0x150f9a8a, 0xf8574f3a, 0xcf96826f,
5281 0xc51e7e40, 0xfa9f0af6, 0x87c2a7f3, 0xea0b3e1a, 0xb97f33e2, 0xd7009e57,
5282 0xb18f924a, 0x97721f20, 0xe38e747c, 0xe3fe2727, 0xf8bf24f6, 0xdca2c527,
5283 0xc2777f88, 0xd0f24b57, 0xb9e9b99b, 0xcb83e501, 0x8708b3cb, 0xc56cd751,
5284 0xdb247df7, 0x33c20b60, 0x0c7666ca, 0x0a372eeb, 0x783ac97c, 0x2e1dd991,
5285 0x3943d3fc, 0x45fe7589, 0xb8e0e747, 0xb3b43bfc, 0xb82ec8b3, 0xa4adfc60,
5286 0x7870569f, 0xb88b4836, 0xd09763bc, 0x5768b94f, 0x41b7ccae, 0x0678df3b,
5287 0x2ffa8778, 0xc4967ec4, 0xfe18dddb, 0x82b87995, 0x4f81ee41, 0x611d9966,
5288 0x1dd39846, 0xb724f911, 0xebf73277, 0xb38f8011, 0xc2136706, 0xae643c77,
5289 0xed7e1191, 0xf757a146, 0x74285f20, 0xc7f4e052, 0x7a0f794f, 0xfe1e7fcd,
5290 0x57a2e978, 0x133e0273, 0x2b2a22d8, 0x79e1bdf3, 0xae5e0ff6, 0x69bdf983,
5291 0x147c9df0, 0x6fcdebe4, 0xeb3736cc, 0x20cdf382, 0xbc3d12eb, 0xd992ff77,
5292 0xb3e00736, 0x051f8168, 0xb32e772e, 0xcebeb19b, 0x8a9659ec, 0xe06af674,
5293 0xcfe88fca, 0x7f174c58, 0x5eeb31c5, 0x2afb3154, 0x3d56b6ec, 0x57a487ad,
5294 0xcf50c2d8, 0xab9f6866, 0x99c4e5e7, 0x50a59eb1, 0xdce8f76e, 0x3c6f1806,
5295 0x347375e8, 0xefe74fbe, 0x38230b59, 0xc20b3147, 0x90011559, 0xbbaaf7c2,
5296 0xd1c03dd2, 0xd95bfeac, 0x7ddf041d, 0x0fa4c1c5, 0xc16032aa, 0x83efc2cb,
5297 0x896efbe9, 0xd62ee38f, 0xd355b8d1, 0xeaa8feb9, 0x53b8f16f, 0x54ceb271,
5298 0x8daaf7e4, 0xd04884f6, 0x5b328923, 0xa47a0b54, 0xf0ca152a, 0xeec65d8c,
5299 0xf4c47d43, 0xc3d3e1f6, 0x78fbf0ba, 0x11deb8d8, 0x84b71fc0, 0x96fe75f3,
5300 0x2af9ccb5, 0x29b563d6, 0xd57587d3, 0x00008a8b, 0xd4305eb0, 0x596efe83,
5301 0x6286f50d, 0xac2f507f, 0x83763d7b, 0x68a7c476, 0xac608c47, 0x9f11d858,
5302 0x8299dd6e, 0x9b27c476, 0xa9e4a677, 0xd8945fea, 0xbfd71c1c, 0xbc656f7d,
5303 0x66ec67ca, 0xa0926f18, 0xf98724fb, 0x50eb8494, 0xe77b44fc, 0x1a7c85fa,
5304 0x0235bf61, 0xef9061f5, 0xb47ba445, 0xf90e77d1, 0x6261bd8a, 0xa3ae199b,
5305 0x1a5d72be, 0xf7876faf, 0x1bc8efe5, 0xdb7e0357, 0xdbfe3862, 0xbe041976,
5306 0x2dff9e5b, 0x0c34af94, 0x3c61ab60, 0x0231bc17, 0xd71cbbff, 0x853d702a,
5307 0xbfce333f, 0x57112854, 0x55d98983, 0xfc1b60eb, 0xc5d99457, 0xd04ced2f,
5308 0xe88421b7, 0x1b372e5b, 0x75caff91, 0x70875d92, 0x59ec1c2c, 0xa7e97526,
5309 0xe8af4512, 0x132972d8, 0x262cede9, 0x9827bcbe, 0xfdf0966d, 0x80c5f4e9,
5310 0x9af352af, 0xa18f5c66, 0xd70901de, 0xb407a41c, 0x53ed885f, 0xbcb3e3bb,
5311 0xad54e00e, 0xb4dba5f7, 0xc6642f70, 0x0784efae, 0xd7cbc937, 0xc414e706,
5312 0xb730596b, 0xcd4b2e43, 0xf03f0839, 0xf017b79d, 0x2649afa9, 0xc0c426be,
5313 0xbe8a79f8, 0xdc7ce6a9, 0xb3c7d55e, 0x09e7be04, 0xca35e5ba, 0x0b3c135e,
5314 0x5a7bbce3, 0x2d4addb0, 0xfbc74b1d, 0x3952ea0e, 0x1ea38e1e, 0x4dc152af,
5315 0xa7054e7a, 0xa25cbddc, 0x7d45eef7, 0xc63f3fe0, 0xeba935be, 0x4ab689dd,
5316 0xe709f236, 0xf495667b, 0x0797d066, 0x4ca15d05, 0xe62499f3, 0xf5f23466,
5317 0x14ef9fdb, 0xd08eaefc, 0x8eba3971, 0xbe412dbc, 0xbcbeb98e, 0xb3fef529,
5318 0xdff56de4, 0x06ec6f29, 0x8267c1d7, 0xf8083b98, 0xd8ca5ab3, 0xfab27a8b,
5319 0x465b6636, 0x37ebb55f, 0x088673ac, 0xc035fd7c, 0x85987403, 0x9d7906ff,
5320 0xad3f7d1d, 0xfc97607b, 0x9cd9f516, 0x776ec201, 0x2424bb70, 0x9b19f38b,
5321 0x61fd3cc0, 0x1ca2610a, 0x23d9b932, 0x1eb91f03, 0x006765ce, 0xf8fb311f,
5322 0x32f5f2fb, 0xe51375d9, 0xa865d8bf, 0x659431db, 0x5cc80582, 0xd53f4417,
5323 0xa633f512, 0x24fee371, 0x6e4c4728, 0x7016464e, 0x6674bc3d, 0x9c0208eb,
5324 0xd058b1e8, 0xdfe1f163, 0x67c5bd50, 0x7d827979, 0x57942f60, 0x799921d7,
5325 0xa1c761a0, 0x2f2c7a99, 0x28b125d8, 0x104cf718, 0xd501a397, 0xc955663a,
5326 0x304f20e3, 0x75f8aab3, 0x4d4896c8, 0xa26d5879, 0x0d4dfea6, 0x33df357d,
5327 0xdf3583bc, 0xd4ca1c47, 0xc79bb394, 0x3c8fea68, 0x8f29ab9e, 0xa9a2996e,
5328 0x0cc2f63f, 0xbe47f94d, 0x99f535bb, 0x103cdedb, 0xe82050f0, 0x8a0ff8af,
5329 0x5ae5bafe, 0x2c3da69e, 0xe8095ec7, 0xb15fc85a, 0xc80b3582, 0x2d07193f,
5330 0xc896fdd4, 0x8da20e6b, 0xf5a95856, 0x6b54164f, 0x1b0dc5cb, 0x5609408d,
5331 0x2fbed1ec, 0x0f2da2d9, 0x43a79e88, 0x011b3abe, 0xf820c9fe, 0x428b1447,
5332 0x2ec9eff9, 0x44efa7f1, 0x00758fe1, 0x7e8098df, 0x33dface9, 0x7d234737,
5333 0xdf03cc0d, 0x7e05b03b, 0xf5c1be07, 0x03d0e3a3, 0x8523e43a, 0x3278fede,
5334 0x1ee96bc5, 0x3dd2d564, 0xee96a064, 0xdd2d3661, 0xd2d28d7b, 0xa5aec23d,
5335 0x2d64d47b, 0x5a1c63dd, 0xd1cdc7ba, 0xa9c13dd2, 0x91527ba5, 0x8bc9ee96,
5336 0xf3ef74b4, 0xa9ae96b0, 0xbe5a85ee, 0xc503e3f0, 0xb95b4b4e, 0x8e9eafd8,
5337 0xe0fcd4e9, 0x40ca9a28, 0xfcaff4cf, 0x7fffa6b9, 0x45a43f36, 0x92353f0a,
5338 0x7e477e45, 0x645fbd86, 0x46ff7776, 0x7f6a6bd1, 0x65d39f42, 0xefa4f67f,
5339 0xd3cbd9ba, 0x47a09c78, 0xdc9ad97b, 0xf5272f65, 0x982797cc, 0x4bd689bb,
5340 0xf08746b6, 0x70e165dd, 0xa357c15c, 0xd59bbb19, 0x13dfb01a, 0xc0146750,
5341 0x03e7027b, 0x9acbdfe3, 0xe65cfde9, 0x5993a7a3, 0x63ccf88c, 0x30167a36,
5342 0xe8a73d07, 0x1e22b79c, 0x392dcd4a, 0xceaf6fa8, 0x42527a3b, 0x21448ea0,
5343 0x2f23dfd0, 0x4ea75a6e, 0xd999cc57, 0xd6b18fda, 0xb44ce70a, 0x16e33ba7,
5344 0x568d6676, 0xbc6f2de1, 0x7a8f5034, 0xa1b60e56, 0xa777943d, 0xde6cf644,
5345 0x3739fc97, 0xfe43af92, 0x2b0f65cf, 0xfe14ab78, 0x1e43f707, 0xbb0ab48e,
5346 0xc943399e, 0x7059b3be, 0xb8fe805d, 0x9182ff3d, 0x82582eec, 0x2e80d7f5,
5347 0x4f4e24db, 0x4dda2ba4, 0x7cccf4c3, 0x9843ca0d, 0x27ccfc93, 0x7892a0f4,
5348 0x1fb1833f, 0xa0dbda17, 0x75234a02, 0x8e394e34, 0x3cd4f007, 0xaa20cccb,
5349 0xe98126ac, 0x9afb4207, 0xf12ca225, 0xbce1fe32, 0x454cdfc9, 0x4d2b6d78,
5350 0x4858af64, 0x4ccd923e, 0xe3dc91c4, 0x493ef0dc, 0xed090d06, 0xbfc01bd6,
5351 0x6b942488, 0x2198c3e6, 0xfaf99ce2, 0x934c157e, 0x51f8539d, 0x0a2f7c26,
5352 0x1dbfdeb4, 0x9595edc9, 0x40efc715, 0xcdef297a, 0x84b3377a, 0xf7825ea2,
5353 0xeb31b92a, 0xb0f11d99, 0x533dc2a2, 0xc8d9ff5d, 0xf1e7ea48, 0x4e2d8bde,
5354 0xdf723ef8, 0x720428a2, 0xd9739067, 0x10a1658f, 0xe9458962, 0x069ad46f,
5355 0x1ec3fb99, 0x919afd19, 0xd4e7f5c7, 0x2dd1a471, 0x0bd8f2da, 0x0f42b2da,
5356 0xc177f376, 0x82650728, 0x00f14caf, 0x195eaa97, 0x67c0f63a, 0x0fdcf165,
5357 0x84c1be63, 0x1b90a377, 0x0de49d53, 0xc130f902, 0x0a61925c, 0x9ccc0c2b,
5358 0xedeb7480, 0x6e5da0b4, 0xd0ebd44c, 0x2ff2603f, 0xf800ce6c, 0x78a69e53,
5359 0x7eb555fd, 0x17ea03f9, 0x48d86bb0, 0xdff11236, 0x41e02f09, 0x1a3a7802,
5360 0x46ae36e2, 0xcdcc9c78, 0x613603cb, 0xb3fea7b9, 0x7a59becd, 0x0b6cc110,
5361 0xbc3fc67f, 0x447e9674, 0xa3af7af7, 0x64e3075d, 0xd93db8eb, 0x8e5cde9d,
5362 0x6bb3e93a, 0x01646c81, 0xb0d553e8, 0x7fd4e3ff, 0x25793e9c, 0x51e22ba9,
5363 0x6fc092ee, 0xcd698787, 0xf8009612, 0xc75aac2e, 0x092e3f90, 0x8f325c38,
5364 0x24d7b1c3, 0xb5e8a7aa, 0x10022c97, 0x875a1af3, 0x62f04407, 0x0eb72f7a,
5365 0x6bd2f2e5, 0x2fae88bd, 0xf1474efe, 0xa3cc41b8, 0x610cf9c3, 0x8c3efa5e,
5366 0x26f950b5, 0x67281514, 0xdbf12b30, 0xbb23e608, 0x2b5cf411, 0xd972b9ea,
5367 0x2820bbf9, 0xbe764e5f, 0xe84e7a44, 0x4fc174fd, 0xaf7e8ae9, 0xddc7fbd6,
5368 0xf8a48d3e, 0xad0b6f4a, 0x54ce4223, 0x3af82674, 0x7f91448e, 0xe768e209,
5369 0x544db4e5, 0xc688303e, 0x587c1429, 0x8d88ec98, 0xc5ebd154, 0xf5336b8a,
5370 0x7802f92a, 0x5bbf28ec, 0x4d66822a, 0xa397bd50, 0x32071e38, 0xa18fd5df,
5371 0x2175f9ff, 0xe047b436, 0xf97ec68d, 0x4729c90f, 0x5b97bc01, 0x9a3af5ac,
5372 0xf50ea567, 0x24efd962, 0x33c01cf6, 0x66b97180, 0x7035e2fd, 0x9848a96d,
5373 0xf9f40135, 0x0fdc917b, 0x1c7cc971, 0xe28433b6, 0x8cc98531, 0x853f4385,
5374 0x7c91a7af, 0x0bd0c40d, 0xcc32b1c2, 0x8c2f7683, 0xdd95151b, 0xf1ff1e1d,
5375 0x35df43df, 0xb733f49b, 0x1ef543bf, 0xdd9973f4, 0x7bc7556e, 0x19bb0b56,
5376 0xe39213fc, 0x3b9fd160, 0x7aff7197, 0x84fb8f30, 0x296ae6b2, 0x62f5e7ad,
5377 0x9a651a20, 0x014c02f5, 0x36ce5718, 0x16ae5c93, 0x47acc472, 0xe18fe8ad,
5378 0x3a184673, 0x8f0e9cfd, 0x1cfbb187, 0x24fd7a2a, 0x3f0baf8a, 0x6a78e289,
5379 0x077b7337, 0x2a19f5e3, 0x31af387f, 0x251bec9f, 0xec2edfbe, 0x9503f6c9,
5380 0x27e8c1b9, 0xbe388a57, 0x058a9fb0, 0xfa682d2b, 0x4ad78e4d, 0x3e91587d,
5381 0xfe7de2f9, 0x535dad4a, 0xf649c5b8, 0x24ecf5cf, 0x09c514c0, 0x49a4edfd,
5382 0xd96f4251, 0xefc60658, 0x3b49accf, 0x307a8c18, 0x1e305995, 0x9abf249f,
5383 0xf11428b1, 0x871cace0, 0x4f543df2, 0x67afeb72, 0x1a87041e, 0xe245b9e9,
5384 0xe7f774f4, 0xd92db4f1, 0xb2dcefdc, 0x7f5a63b7, 0x58cbe7e8, 0xdda52f8e,
5385 0x6a06b197, 0x38e828f7, 0xd8cb5f7c, 0x6e7e40e4, 0xc977c091, 0x7a8b2096,
5386 0x8dab2a7d, 0x0d5d94d0, 0x7af51609, 0x2c28f640, 0x4c146caa, 0x7e2ba721,
5387 0x72d0d653, 0x768ac430, 0xca017381, 0xbfc1fb49, 0x3a250f86, 0xff5072f8,
5388 0xf9c7183d, 0x02b6e113, 0x9f743b3c, 0xffd355cd, 0x80bd28d1, 0xffa7af9b,
5389 0x2d765c30, 0x1e87975c, 0xe1c29d8b, 0xd5c239fa, 0x8b1d3de6, 0x8cb805f4,
5390 0xe476b86a, 0x3f9ff8f2, 0xa1fc9e9e, 0x88f564f0, 0x87df35a7, 0xc0c61da7,
5391 0x74126cf0, 0x6e80f97b, 0xfac027b2, 0xcfc849b4, 0x1aef0c3f, 0x6b6dfc3f,
5392 0x15618d9e, 0xe1137780, 0x9635be2f, 0x7f021672, 0xe04e22b5, 0xc6fa12ce,
5393 0xfd03ba06, 0x7a468fba, 0xead40f50, 0x2c54d459, 0x96d814e7, 0x46af3cc0,
5394 0x5da0fb38, 0xfe21eae4, 0x7f8091f2, 0x7014a247, 0xef881ffe, 0xf5e48f7b,
5395 0x89ff75c1, 0xf28626e3, 0x09ebe0af, 0x1339ad4b, 0xe6fa37fb, 0xf59cb0db,
5396 0x1a1ad9b9, 0xef1d7fa0, 0xf27e57ff, 0x3caff4a1, 0xc81a8ddf, 0x01d247e3,
5397 0xfb209419, 0x9ac7cdd5, 0x7f9cc3c7, 0x9d27a595, 0x79e30ffa, 0x79fe36b9,
5398 0x762c7bd9, 0x778be71a, 0x4b97df51, 0x876fc367, 0xbdf24bb2, 0x97f31433,
5399 0xd7cd2746, 0x6d8991f5, 0xbce7600c, 0x9942f821, 0x057f329f, 0x151fb0ee,
5400 0xee0091f4, 0x5a2613b0, 0xf5103e0c, 0x97a07595, 0x5e71a3b0, 0xacdc0eb4,
5401 0x6ca071e7, 0x57f7d13d, 0x1c50c6a3, 0x27c88768, 0x291b46fa, 0x870fe95e,
5402 0xff8f9a21, 0x9bf7b5c4, 0x8d3f62fb, 0x33e78a06, 0x4cfc4b7d, 0xdbd717e0,
5403 0x9427877a, 0x8ef266f8, 0x4763a450, 0x753c0b78, 0xa76a06d1, 0x7287bd43,
5404 0x8c9e4d71, 0xc8fdae7a, 0xc55916e7, 0xccb472e7, 0xb9ac6be3, 0xbff42c79,
5405 0x30599336, 0xd62a1cbe, 0xad23d0df, 0xe87f0845, 0x249b9fa8, 0x4af6fc55,
5406 0xadda8994, 0x6d62fa35, 0x09ab9fd0, 0xf78a051c, 0xb1b118b7, 0x85970782,
5407 0xeb3ca1e3, 0xe866e800, 0x4760d1a7, 0x2b68e578, 0x7700a7d7, 0x1e0fbc3d,
5408 0x1f25b9f4, 0x78c167bf, 0x87dabb7d, 0x833d3859, 0x439e61b3, 0xb3de5f91,
5409 0x97b3c014, 0xdf081cc4, 0x3f5cd183, 0xc455702b, 0xfc02fd71, 0xf114321e,
5410 0x7ca3ac9a, 0x66fae3ea, 0x96e3dfc2, 0x8c25967e, 0x79c76ef0, 0x299b46f9,
5411 0xed1d56ee, 0xf9c6898c, 0x1e1cd818, 0x8c766cf7, 0x32587c27, 0x07002356,
5412 0xf0bd9106, 0xc38bc133, 0xb21cf358, 0x168cb20b, 0xf594475c, 0x8ede8bf9,
5413 0xcd37685e, 0xd076e68d, 0xd742b7f9, 0xc0abbae0, 0x2c02b677, 0xb957633a,
5414 0x8498e6d0, 0x9ccf9978, 0xe78e502b, 0x551e0157, 0xc0de7efc, 0x16bc2dfb,
5415 0xaa51bccc, 0x36eea376, 0x6bc2bb62, 0x760bcce1, 0x5e20f9f7, 0x5f187cef,
5416 0xf18ac6cf, 0x33fc156f, 0xea07fa33, 0x7c9f9b31, 0x8bf3f86d, 0x8d8f5c79,
5417 0x4995bc45, 0x7bb4462d, 0xabf98ed7, 0xb3e9ed11, 0x4de61615, 0x4679beff,
5418 0x9c6aaf31, 0xccd77ace, 0x3ca51f34, 0x5b24f917, 0xc250df3d, 0xf88ad9c3,
5419 0x4931e0eb, 0xfeaec783, 0xd8f06afb, 0x1a74ffbd, 0xc0c56cff, 0xa43ff4eb,
5420 0x1aadfe87, 0xedfabbf8, 0xedb6e347, 0x04297bcb, 0x779f7bf8, 0x31bb73e9,
5421 0x64c7bb1e, 0x373ca131, 0x3f22e6d4, 0xbc0edd5e, 0xd0f4fc04, 0xff28af9e,
5422 0xa326d0f8, 0x3768c70d, 0x02dae6f8, 0xcc7eefe8, 0xea8dd6e2, 0xa746167a,
5423 0xdffd9d11, 0x0b1ef59b, 0x03cd95c6, 0x375c16f5, 0xb3d9accc, 0x4cd7f894,
5424 0x3f8944fa, 0x8b4efd28, 0xccfa3592, 0x5fd9f425, 0x9047cef5, 0x5f3aedde,
5425 0x89da1e7d, 0xb70f3f03, 0x41117f92, 0x3f12ba76, 0x892383d0, 0x3989ad76,
5426 0xde4de618, 0xa3ba758e, 0x82dfbfa1, 0x411c62b8, 0xc4e3561e, 0x2293fb78,
5427 0x5064ffee, 0xa54dbc73, 0xeb45d697, 0xb09d987f, 0xb35f8fd2, 0xcbd17c3f,
5428 0xc47583d7, 0x2bf372af, 0xb58bbf08, 0xc55c7918, 0x5e67f64a, 0x94e3c1d6,
5429 0xacfc520f, 0x05fbfe95, 0xbfd02392, 0xe11de252, 0x9ae2ace8, 0xd68c36bd,
5430 0x5e10fceb, 0x28b7ffce, 0x8a819fca, 0x6ac43d26, 0x162f9e65, 0x310e9671,
5431 0xdaf37687, 0xda1ff414, 0xa3ab1e45, 0x46e83f71, 0x4fecae78, 0xf37fcf74,
5432 0x9f6869d1, 0x79e33e83, 0x5a30a6ab, 0x624df227, 0x9106279c, 0x9123b17f,
5433 0x7ab57fdb, 0xcaa6786f, 0x77bc7c1e, 0x685f736e, 0x7f656977, 0x5dcbda1d,
5434 0x0efbcdfa, 0x39dae7f6, 0x574df888, 0x39e9e83f, 0xd7489718, 0xdcebb0d9,
5435 0x31eaaffa, 0x16b650de, 0xef1801ec, 0xa469e812, 0xc4feae93, 0x705f5c70,
5436 0xcb3f5c6c, 0x9fc893ea, 0xd1f10fcc, 0x60b293fe, 0xea05ba5b, 0x4d8fd7e5,
5437 0xf33fbe47, 0x5c14a0e4, 0x58c74e0f, 0xdc4f3053, 0x192024fe, 0x69ba79e6,
5438 0x6abf7f00, 0x17d470e4, 0x9c436b61, 0xadfc009e, 0x95fcf7e8, 0x14767226,
5439 0xcc48ef3a, 0x7c406b68, 0x7e93320c, 0xf6450507, 0xdf21fe53, 0x17786b0c,
5440 0x473f159e, 0xa15ac7c1, 0x3ffe954f, 0x79517a16, 0xd299fac2, 0x31ef7082,
5441 0x1ccffd11, 0xc38d7bd1, 0xf1b21ed1, 0xd08556f1, 0x0730f978, 0x29cbc80b,
5442 0x8e9d8eb1, 0xbc470eb4, 0x2832ebe7, 0xe443ba0f, 0x7c5956e5, 0xe41eb8e1,
5443 0x194ad9eb, 0xbe62afea, 0xf8d508f0, 0xd7b28df9, 0xfbddf448, 0x4d5ff90e,
5444 0xabe90c61, 0xfc8c337b, 0xa69bd773, 0x018f684d, 0x6821ddfe, 0x91371e17,
5445 0xc9afb2df, 0xfb617644, 0xd7f21089, 0x42c3f1fc, 0x3f48297d, 0x44499bd7,
5446 0xdf64f6df, 0x0c8edcf3, 0x680f9862, 0x891cea3f, 0xd1694274, 0x9ec3e3c5,
5447 0xd5cd7680, 0xda2f20a6, 0x60f4f035, 0x6acdd07c, 0x9efde9e2, 0x347e8610,
5448 0xa8643d3c, 0xe0f17549, 0x1082a0b3, 0xfda99bed, 0x01ce2943, 0x4a1f1fa8,
5449 0xb143fe83, 0xbbd52b7d, 0x9379d7da, 0x1221c785, 0xd48978c5, 0x5fb7326f,
5450 0x8d39f499, 0xef89fd03, 0x65ddf4cd, 0x79a48e72, 0x36c61c7c, 0x61679806,
5451 0xa0bcb6a5, 0xf62e5b5a, 0x5b25cb68, 0x745f65b4, 0x814fd114, 0x7f73e15b,
5452 0x70c4a4bc, 0x87c142bb, 0xd2769f3f, 0x61f03af3, 0xcbf1013c, 0x571d391a,
5453 0x929aba0f, 0x0f2de387, 0x9753e4d6, 0x3e279d34, 0x9fd8376c, 0x77c075c1,
5454 0x9136c0d4, 0xd50360fe, 0xf8ffb6fe, 0xe7adf3dd, 0xbcf5be45, 0x26dadf26,
5455 0x160c2ef4, 0x5084f18e, 0xe11c359b, 0xad4ba1d8, 0x3d5f22f5, 0xbe7c4419,
5456 0x21cbf716, 0x401baddf, 0x054452f0, 0xf0b3cfc6, 0xfd08cff1, 0x54c5e677,
5457 0x642d33ca, 0x4b4fa4b5, 0x44bef399, 0x5887e78c, 0x57ff9073, 0xcdfb02d9,
5458 0x27baf8fe, 0x34e3d386, 0x7d8ac6b3, 0x6fcc564d, 0x80bfe114, 0x74fd4504,
5459 0xdfbe20f6, 0xd175f48f, 0xd481137a, 0xd8ccf7c9, 0xf3ff9655, 0x0d0077cb,
5460 0x3655fe11, 0x67ae3877, 0xde7c2c17, 0x91593f60, 0x9f3245be, 0x8875fa07,
5461 0x2f120bc7, 0xd942fa2b, 0xdf00b12f, 0x989e7ccb, 0x518f2fa7, 0xc7ae38fc,
5462 0xf75e925c, 0xd693e830, 0xf2386b08, 0xb4aaeb53, 0xb79825c8, 0x66c6b088,
5463 0x3aecf0aa, 0xd026bcc0, 0x0946d65f, 0xf0ddbf63, 0xf39223b5, 0x085d6fa3,
5464 0x8eaf2bad, 0xf6ab996b, 0x8635ff13, 0xc58f91db, 0x16a6ff70, 0x40ec826d,
5465 0x5a74e078, 0xcab4e820, 0xf931fce6, 0x16f57e4b, 0xf412f754, 0xb95f7bf3,
5466 0x2f295ffb, 0x0fc55eb5, 0x8a4edeb0, 0x385de3e5, 0x374b7464, 0xfb4a5f91,
5467 0x82eb7c9a, 0x70bf6ec8, 0xae3a4a68, 0x82eb4543, 0x155f5122, 0x8b135e1d,
5468 0x8db8c8f6, 0x3ae2c58f, 0x6269b055, 0x9fe2533a, 0x482a3e2a, 0x3da3a7b1,
5469 0xb6567be4, 0xd5453f60, 0x4ab5c132, 0x167e695f, 0x36ab9fde, 0x24549d90,
5470 0xdbd73ae0, 0x2f788e19, 0x11bd33d2, 0xef4e7ef0, 0xf03b270c, 0x2ffc9959,
5471 0xbd40f9ff, 0x00ccfa63, 0xfa0b3278, 0x00b48be2, 0x47547bfc, 0x66082a74,
5472 0x36e75724, 0xb9edfcf2, 0x587de764, 0x157f056e, 0xaaad77f7, 0x0eb70e2c,
5473 0x73f78eed, 0xddf12766, 0x051f3102, 0x28e3feaf, 0xbc476d78, 0xe871fda2,
5474 0x2768c9b9, 0x91929eb8, 0xc6ded933, 0x8e47e42b, 0x72789a6b, 0x075fbe2c,
5475 0xd7158076, 0xdcefbec7, 0x4ad4eb83, 0x909da199, 0xcb1694d7, 0x57d76a86,
5476 0xdef22fb4, 0xa3ae159e, 0x90d31df7, 0x6d5b4e9f, 0xfb2a99b1, 0xcfc11dee,
5477 0x5fc974fe, 0xec70b7f7, 0x818d68af, 0xdff057e0, 0xfd93630e, 0x41e21953,
5478 0xedef6f3e, 0x7a157ea3, 0x2116fd28, 0x81fe15be, 0x2c63577a, 0x7c795f82,
5479 0x99d535b1, 0x0fc00b63, 0xe3037ff3, 0x61d57f62, 0xdcbfcc76, 0xbccab8e8,
5480 0xc8aae93b, 0xafd399ad, 0x8a54f9f5, 0xea8eeadf, 0xe9e99369, 0x50535bca,
5481 0xfd61f2de, 0x5f3a7f46, 0xfe449df2, 0xe315b285, 0x4aebf9d5, 0xf2f1c3ee,
5482 0xf874984f, 0xadcf75bd, 0x3f2e09c3, 0x529e01fa, 0x7b75f102, 0xa6c52faa,
5483 0xfbac1fc2, 0x7ccacf24, 0x1c137054, 0xe4307fe0, 0xa054f6ff, 0xbfee4a9b,
5484 0xf50f7210, 0x63e2462d, 0x5fc470fb, 0x7e2d7ce7, 0xcdf8b5f3, 0x3e2318f7,
5485 0xcd273666, 0x9323e0a7, 0xfc17df0e, 0x28e9a7fa, 0xc7abad9f, 0x235abcd3,
5486 0x8e51c3ed, 0xffa0535a, 0x59e7dda1, 0xe7986bf0, 0x6799efd0, 0xabd11065,
5487 0xfa4679c7, 0x33df679e, 0xed58c8cf, 0xadeacf3c, 0x5c5fa8e1, 0xfb8664bb,
5488 0x8ec95cc3, 0xd97963b5, 0x768614b2, 0x05d0f589, 0xd5e912fa, 0xb8a068d6,
5489 0x30ef22a1, 0x83f20dde, 0x35a1f88e, 0x28f4fad7, 0x0b656f5a, 0x575bd9c6,
5490 0x51e7788f, 0x95aeb728, 0xb407682d, 0x81fc72e6, 0x0f50ebdc, 0xa638a6b4,
5491 0xc18f7951, 0x39fa14b2, 0x0fb7f953, 0x0c0bf225, 0x73f34656, 0xbe3b45ac,
5492 0xfd45e01d, 0xcd997805, 0xcd034aed, 0xa7cad57f, 0x7777e256, 0xfe964df5,
5493 0xa7eb40d6, 0x6b45cf16, 0x321c8d64, 0x73c695bd, 0x8ac93afd, 0x0cf050f3,
5494 0xc67d349a, 0x607c2eb0, 0x2eb0d679, 0xfd94b8bc, 0xeb3d626c, 0x9f885bd4,
5495 0xc05d7cbe, 0xafa8ea7d, 0xa77d3f70, 0x57affb3c, 0xdfc67a7e, 0xd04db89e,
5496 0x16ef5fd3, 0x7ca9cbab, 0x5cbaa15f, 0x4a37a7e2, 0xbac3befd, 0xfc502d3b,
5497 0x78e77774, 0x02796f1c, 0xaf5c4a6f, 0xd68949fd, 0xd5bd3cd5, 0xabc17e88,
5498 0x155c78e3, 0x8ff301fc, 0x683b0e49, 0xb67a793e, 0xef8994dc, 0x994f546d,
5499 0xdcb7f427, 0x8ef46b04, 0xa077ae60, 0xaaa364de, 0x0557e8ac, 0xfe44479e,
5500 0xc3fe7942, 0xad64f3fe, 0xb38aacff, 0x201b123f, 0xf7299ece, 0xc608ed7d,
5501 0x64c976db, 0xf30eba37, 0x7d7d8575, 0xf06de9e5, 0x1a4f7cbe, 0xe6555bed,
5502 0xf6c78fef, 0x7de12b86, 0x21db7de1, 0xcbc63063, 0x72a31af2, 0xf48a2fc9,
5503 0xaffbc405, 0xfe94fcc4, 0xe12df4da, 0x2df6d5d3, 0xa19f096b, 0x86bc8fe2,
5504 0x164fb42b, 0x5596e7f0, 0x534cfb7a, 0x79fa2e4c, 0xcc4a7ff9, 0x55f3c1d5,
5505 0x06b5cf41, 0x506b0beb, 0xc899764e, 0x3c3b6f6f, 0xdbed8747, 0xe789170e,
5506 0x9e7a7643, 0xe382933d, 0x7f38eb87, 0x14bde32b, 0x7ca5edcb, 0x7fe7a9dd,
5507 0x8dfefa84, 0xaa65d4b8, 0x2ebe69f8, 0x6dc4fc93, 0x845cdf06, 0x95f1ec1b,
5508 0xe943efb8, 0x2b58d5e7, 0xebb6d1c1, 0x0fa8f3fc, 0xce4dacce, 0xb6d23544,
5509 0xcc70c06b, 0x189db7fb, 0x3fe78e91, 0xb04c9eda, 0x66d81ea1, 0xfc443eb0,
5510 0x86cc2ab6, 0x87f4ae72, 0xac7e60e3, 0x1cc8d76d, 0x4edbb3f4, 0x4ca17870,
5511 0x73d4377e, 0xa50efee3, 0xf59d70df, 0x8c8fb857, 0x7940c9fd, 0xa4dfc5b4,
5512 0x1abfa1c5, 0x5f9c0c6e, 0xbb5dfb40, 0xc1296a7f, 0xf1e3ecad, 0x7d95efb7,
5513 0xd17efe3d, 0xf80bd07c, 0x2b7fdfde, 0x702b9562, 0x1fbf917f, 0xdc7e40c7,
5514 0xfa62beca, 0xbdf5a5ab, 0x2677cb64, 0x0fb13d4d, 0xbe031a88, 0x571e40f2,
5515 0xc3c65c53, 0xe52b5fe3, 0x5f42f980, 0x3ec7cf2c, 0xdcedf213, 0x4f5d1516,
5516 0x1e3e98eb, 0xc8da7af0, 0x7f99f1cc, 0xaf973fbf, 0xbacc57de, 0x73a777fb,
5517 0x00b9953d, 0x32d5e9d7, 0xa1fd47ed, 0x7b7f9dfe, 0xf3e88480, 0x4effb099,
5518 0x3e705cc3, 0x5ab3fb3d, 0x067c1578, 0xfe057d89, 0xfe22cdf5, 0x991bf03e,
5519 0x9bee51d9, 0xcfe41e0c, 0x3f9f8d90, 0x67f20f7d, 0x6a92c1a3, 0xed017ca5,
5520 0x64bb6573, 0xb75c7f4f, 0x2f84cf1a, 0xd76575c4, 0xd34e3a08, 0x92ecbfe9,
5521 0xd6dfee29, 0xf3162570, 0xe50fd003, 0x4f4d5d3b, 0x7b7f90d9, 0x4e312382,
5522 0xeffa61fe, 0xa1f8bf66, 0x6db67bc8, 0xfa8e973c, 0x6260f41d, 0xfa67ca1c,
5523 0xff9e46d7, 0x7da1c96c, 0x273f1bbf, 0x73ddbcbb, 0x7349ec95, 0x940f6ca3,
5524 0x671a1c57, 0x4df061fc, 0xf007c2d0, 0x1478450c, 0x3eadcb38, 0xbd737f3a,
5525 0x5d84ffbc, 0x1cf14b85, 0xd1f9e608, 0x94682fbe, 0x582add69, 0x40ac7b2f,
5526 0x7e030997, 0xed082fb1, 0x8a24a7d1, 0x6f924e0b, 0xd40e70fe, 0x4ca4f05f,
5527 0x1f1bbde5, 0x7480d0fa, 0xbca06f5d, 0x99a682e1, 0xfc57da46, 0x122cc494,
5528 0x37d9ab8d, 0x12972c50, 0x09f6dd5c, 0x680fedf8, 0x7d0b76cb, 0xe37ef7e0,
5529 0xa2fb198a, 0x9267a9f1, 0x017efbb5, 0xcb103bfc, 0xdfe047cf, 0x126bfe96,
5530 0x416d0e91, 0x5ca3358c, 0x5fc85bea, 0x3e7e5e61, 0xd9d76db3, 0xeb97a414,
5531 0x5e292f8d, 0xb01c93d9, 0xf33fbe46, 0xfc8938ce, 0x5cdf81d2, 0x5008e699,
5532 0x6fc8b67f, 0x13b8316f, 0xb7dd3ed1, 0xe38f2af1, 0xae71e2ec, 0xee67fb1e,
5533 0xf26f1e20, 0x2c1c5106, 0x0532d6ab, 0x3cec01e5, 0x36b93fcc, 0x09b198ad,
5534 0x0dbb41ca, 0xabab4456, 0x05c9287f, 0xaaa141ca, 0xb61e455f, 0xb2947c88,
5535 0xd8b661bf, 0x6feca397, 0xf83bf650, 0x77eca1c3, 0x3bf62d98, 0x78eb1dbc,
5536 0xc19e0e28, 0xd9385f3a, 0x5ffb7eb1, 0xe2cfda7a, 0x3fd1efbf, 0x4f9fee6e,
5537 0xcbecad5b, 0x47146088, 0x8dfac237, 0xcd86c395, 0xabf51778, 0xfe4c98e1,
5538 0xef23ded0, 0xf1f5aac5, 0x38737d0a, 0xd72f31c6, 0xd1fe4419, 0xc316f947,
5539 0xa98dcf91, 0x862597a4, 0xca0bae76, 0xb375def8, 0x338eaede, 0xe7c71d3f,
5540 0x9d2e22bb, 0xfb7ab7af, 0xb7afcc21, 0x688cf259, 0x148e1b8f, 0x367e464c,
5541 0xf919e7c4, 0x54e6b9f8, 0x9e844ba4, 0xa3457ff8, 0x05b36e32, 0x7bf257fb,
5542 0x2cc71161, 0x598577c8, 0xbf3fbeb3, 0x4a83f227, 0xdf33af7e, 0x7be33f17,
5543 0xe33b7bf3, 0x8bf71d38, 0xff71bbe7, 0x3b7bf2cf, 0x5265fe91, 0x30f1a4cb,
5544 0x8ef88ac4, 0x6ebdf9c0, 0xfcb1bcf3, 0x567147de, 0x9ceb7f9e, 0xbdf90f6f,
5545 0x58dffd6e, 0xff7baf7e, 0xbaf7e43d, 0xf9837ff5, 0x797ecebd, 0x50f96f7e,
5546 0x5b3fed1d, 0xe3c4dc7e, 0xffbe66e4, 0x65e424c3, 0x668277b9, 0x74f284ff,
5547 0x184909b3, 0x275e5f27, 0xbcfe464f, 0xa0b3c96c, 0x78221a7c, 0xb064c83c,
5548 0xd43f464f, 0x85191114, 0x711ff97c, 0xabaf3469, 0x3f888b11, 0xc87982af,
5549 0x722d89cf, 0xef797960, 0xca649902, 0xd6177f2f, 0xd57cf324, 0x7758b368,
5550 0x87e4b7df, 0xf3fbfe52, 0x3d1e5538, 0xed00fb2c, 0xce0d648b, 0x8fbf283e,
5551 0x127f405b, 0x7c50b79f, 0x7f3928c6, 0x76217187, 0xbb639f82, 0x601ce41a,
5552 0x3ea5c951, 0x2eec28de, 0x33ea126f, 0xa7a2ab37, 0xe10ae1ab, 0x2a478959,
5553 0x47cc5ddf, 0xa5794778, 0x7a09b8c3, 0x706f7d2b, 0xb573a00e, 0xbb4e8e02,
5554 0x6ea18fe0, 0x6a69a73c, 0x8ff286fa, 0x34df7aed, 0x36d4eb8c, 0xfc6a21ca,
5555 0xb973c526, 0x9cfe4dc8, 0xd8e556f2, 0x57e617ae, 0x7ca0064b, 0xc37c9b96,
5556 0x7b7dee11, 0xf51c36fe, 0x92a6d5ca, 0x0b7ef83e, 0xdc75a7d4, 0xe7572be8,
5557 0xaaf3fd5d, 0xf381f1d1, 0x969a5bad, 0xdb1c2225, 0xf6005e30, 0x3fc3f955,
5558 0x663a73a7, 0xea0dff66, 0x837a060f, 0x99868afc, 0x93b438f2, 0x01db003e,
5559 0xf8bb59ca, 0xcc959bfa, 0x2d37983c, 0x0e60fa6f, 0xdb3cabd2, 0x32974168,
5560 0x6de78338, 0x16cdb383, 0x45a6ff5c, 0xe2303e71, 0xed869b3a, 0xdd214627,
5561 0x3031c41e, 0x7b73b9cf, 0xb7f01bbd, 0x854f0ff0, 0x27dfc033, 0xafda4afa,
5562 0xb1f9ba51, 0x2f3c3b70, 0xc714dde8, 0x0723c4fc, 0x1794ffdc, 0xf6b7f8af,
5563 0xfe754950, 0x3fdfd3e0, 0x6ef88d31, 0x7982c1b3, 0x1316d77f, 0xaf2b9f9d,
5564 0x33f3a62b, 0xcbc53e50, 0xfe867f8f, 0xbb41ab95, 0xe97c2f4e, 0xad2b58a9,
5565 0xb124ee0b, 0x941f11ee, 0x849d9cd7, 0xc1f857f8, 0x8f8e1dbf, 0xb55de5fb,
5566 0xaf633cf2, 0x7b15dfee, 0x5dff5943, 0xfb884f75, 0x3fc85a01, 0x845faff0,
5567 0xb19a3232, 0xfddaf199, 0x983e0ad1, 0xa3f48627, 0xf0c373bc, 0x54be5053,
5568 0x92e16ff3, 0xbf8a4f0a, 0xff9b51d3, 0x3dac37bb, 0xb06defaf, 0x7574b02e,
5569 0xb3b50f3b, 0x177e0836, 0xf06a5f7c, 0x955ca386, 0xdcd8346e, 0xfb74baf0,
5570 0x973e2f0b, 0xc3667245, 0xfb64ac75, 0x818e1f5b, 0x430ec972, 0x8d3e54f4,
5571 0xde754950, 0x61ff05cd, 0xc3a1405e, 0x32ded7c2, 0xf7f1875a, 0xa2ec88bf,
5572 0xbd8ec947, 0xfc5e7446, 0x76be31f1, 0xbbf291af, 0x3da974fe, 0xef2b7245,
5573 0xbbec86fc, 0x2c48f64f, 0x3e00352e, 0xee15be37, 0x3a227814, 0xd2753a0a,
5574 0x92beafcd, 0xe4e8577f, 0xde3b3dff, 0xfd85f242, 0x3f023ca1, 0xc606f2bf,
5575 0xd9323ffb, 0xaf45fe70, 0xf38e103c, 0xc45faf38, 0x63c37af9, 0xb71876b1,
5576 0xb58ee0c8, 0x2fbf93d0, 0xc467fe7a, 0xfe8e0b6f, 0xcc7fdb8c, 0xfca3a09e,
5577 0x7bf29ba5, 0xd0efeb85, 0x0da2ffe8, 0x85ffae3c, 0x11de4d9e, 0x0b8e2e40,
5578 0x937e72bd, 0xe7d9f289, 0xf6860f31, 0xdf327bcb, 0xa7eec7b7, 0xdf629078,
5579 0xe54d2780, 0xfe1e842f, 0x894ebc43, 0xfc359b7f, 0x3378f35a, 0x64d3e7d2,
5580 0x25ea1c7b, 0x05bbd317, 0xa0efa43e, 0xc4e8f95f, 0x1e1f4e38, 0x6076a33f,
5581 0xf7c78e8f, 0x40d9bf58, 0x3b5550f1, 0x8f966e71, 0x1f18a0ff, 0x7cc60ee0,
5582 0x5658f9ca, 0xd44fc814, 0xe7c67427, 0x29e7359b, 0xcb9be4bb, 0x2e2acd7b,
5583 0x7bbc8adf, 0xefc64fa6, 0xf2e31f9f, 0x3292ed83, 0x1c6f2e09, 0x4b3bdf7d,
5584 0x27cfce1a, 0x75c9037b, 0xb5c8418d, 0x27c2bbf6, 0xee9eb700, 0x05f85021,
5585 0xfc248ffb, 0xbad2d517, 0x1dd8d26d, 0xbc2f1c2e, 0xdc8a7f7b, 0xfff2102e,
5586 0x7f38bc7e, 0xad9fe425, 0xf3a1b98f, 0xcf06a545, 0xbca1cf8b, 0xbef7e09e,
5587 0x90376e94, 0xdb717e5d, 0x06ef0ffe, 0xab58b939, 0x7f56a9c8, 0xd169cbfa,
5588 0x7f116fab, 0xc5e9cbfa, 0x0362b7da, 0xb78ee9ca, 0x2eee0ec8, 0xfab9ffa7,
5589 0xdfdfc153, 0xe8a7f0fc, 0xe8f09ec3, 0xe3ab0faf, 0x21f501ad, 0x9f531dfc,
5590 0xa5f0537b, 0x6fc29df0, 0xeb2e5f0b, 0x93a77a83, 0xebbe152f, 0xef854be4,
5591 0xd73bedba, 0xfbffcfe0, 0xe00df85b, 0x60faec72, 0xb3d01252, 0xc9fb91b4,
5592 0x9620eed0, 0x5a764f01, 0x41e558c6, 0x55db6f3c, 0x6b95f8f6, 0xfddbeafd,
5593 0xfabf0eca, 0x22f2bf4e, 0x821efabf, 0x3f61b4ab, 0xbcc96fdf, 0xa586fa9a,
5594 0xdd161dcc, 0xf31e0e75, 0xcfd02b58, 0xf4f3c6df, 0xb8f0258f, 0xb8c62fa9,
5595 0x891ff682, 0xe13e2a7d, 0xb43bb467, 0x354e54fb, 0x5b7fa4ca, 0xf8f3813c,
5596 0x3c9209e0, 0x3fb0f4b4, 0x4d3b895e, 0x1e534394, 0x2a3a3806, 0x60a0fc79,
5597 0x94e19dc9, 0xbb4c69cf, 0x850ae31d, 0x2c31f987, 0x73143f65, 0xaa09f5db,
5598 0x98170efd, 0x319be9fb, 0x4258d64f, 0x35828bf1, 0x0fcd7a5a, 0x0be2907d,
5599 0xf7b4abf3, 0xad7c2900, 0xd68b0bc4, 0xc42fbf6b, 0x1ee8847b, 0x47da4a85,
5600 0xfb46b0b4, 0x0e7c89dd, 0x41273c7c, 0x2c1909d8, 0xf9bde443, 0x57a11239,
5601 0x6f43ca27, 0x21cbfca7, 0x1da5f299, 0xbde1328d, 0xfb449b63, 0x863b9869,
5602 0xf99ca5e4, 0xf8299f48, 0x60f284b9, 0x5cdf59ec, 0x73dffd7a, 0xa52a851e,
5603 0xff0f1ff5, 0xd52f3c2d, 0x8ddf489f, 0x4e7f9de5, 0xaf7598f9, 0x104f7e3f,
5604 0xdf6a1fed, 0x35f74613, 0x9dbd37b5, 0x85e528f2, 0x07ba364c, 0x9497cf61,
5605 0x6a5f6b7f, 0xd57d422a, 0xcafdcc9e, 0x0e5f4d65, 0x39657ae7, 0xc098df3f,
5606 0x34744dcf, 0x94f28dfe, 0xca268d1d, 0x84f6b933, 0x7ae11f90, 0x9cfc8823,
5607 0x292fa6f6, 0x9acffcbe, 0x3788b94f, 0x3cf187b7, 0xbfb8bb4f, 0xf47bb5c4,
5608 0x2d87980b, 0x446bdbab, 0x9bfc65bf, 0xdf5d90df, 0x67b72afe, 0x1eded0da,
5609 0x5bae7883, 0x7dc44e33, 0x4d0ecca8, 0x0db77b45, 0xb1912385, 0x9d5dcfa1,
5610 0x081a1eea, 0x5e50df4f, 0xf3f146f5, 0xfc18ffd2, 0xb9dfb448, 0x63cc31b4,
5611 0x5fde7096, 0xf518fc9d, 0xd79e1ec1, 0xb17be657, 0x1fd90976, 0xc1f79bd7,
5612 0xfddfee04, 0xe4b799ef, 0x9f7991bd, 0xef4e6ffd, 0x98d43c62, 0xba2e5ddd,
5613 0xcf1379f3, 0xb30f6d17, 0xc837bc11, 0xffc486ef, 0x157f7465, 0xfd7e1ee8,
5614 0x6ffbf779, 0xe99eef3e, 0xa0ae787e, 0xf3e305bb, 0x21bf37ae, 0x3d5efef8,
5615 0xe87fe137, 0xfd3b15fc, 0x6fd7c67d, 0x91c3a257, 0xee9efb88, 0x5f02bc38,
5616 0x274e74b9, 0xcd12c3c5, 0x4d9fee74, 0x8e87e28d, 0x33618ef5, 0x57877586,
5617 0x25fe1bf1, 0x31273ed1, 0x07feaba6, 0xa619efb3, 0x7d57779e, 0x58d1be3e,
5618 0x379d3f7b, 0xfca50b29, 0xc18f6e2c, 0x36cc2f76, 0xf713fe71, 0x990f1c3c,
5619 0xa606307b, 0x738347f2, 0xe739c23e, 0xc0ac9fce, 0xca2fb4b2, 0x35e718ba,
5620 0xdc4725af, 0xc710b08b, 0xfb3b352f, 0x72f9aa60, 0x2f4073b2, 0x511c47b4,
5621 0x1ccb9e3c, 0xe1011cc3, 0x37ce6b77, 0x994bf62a, 0xea3aa1b0, 0xbe517ad2,
5622 0x645ed5e4, 0xb8e9b57f, 0xe026d87f, 0xb767e0bd, 0x1a8e7917, 0x5c58ff31,
5623 0xcea8d473, 0x7389963f, 0x3fe3fea9, 0x23f3c891, 0x87f6be9f, 0x8bf748ab,
5624 0xa3a7d45f, 0x5d2256bd, 0xdd5d79a2, 0x98ae747a, 0xff9c0adf, 0x14be1d43,
5625 0xb4abcc23, 0xc791af76, 0xf4fcc523, 0x9beff4be, 0x79ae9b5f, 0xaabb9d12,
5626 0x8e7ce897, 0xeeacaed2, 0x93b424e8, 0xe8226a8b, 0xa7dc473e, 0xca9dcfc2,
5627 0x7860fb7e, 0x8eb2493f, 0x4bf7dbf8, 0xd21bf689, 0xe9dfb41f, 0xbee0f08e,
5628 0xcaee936a, 0x676899b1, 0x8ce7e30f, 0x438307d6, 0xbbc77e0f, 0xc41b5f02,
5629 0xbf780779, 0x07c7df12, 0x4ff1f6f3, 0xfedf68eb, 0x9409b90b, 0x7bdd543f,
5630 0x72075291, 0x36b26494, 0x49b8c0b4, 0x0f28bd15, 0xb9d13dbc, 0x5f71f105,
5631 0x18e52e94, 0x421ce1c1, 0x8e6f80e7, 0x753f21ba, 0xf818b306, 0x9e7e527e,
5632 0x4f85867d, 0xb5d850a5, 0xee9d9933, 0x3983b8e1, 0x6d7bdea9, 0xd7da3b46,
5633 0x336e61ef, 0xa3f7ee93, 0x0f3177f7, 0x5e61ef3d, 0xac2fffaa, 0x5f0aca85,
5634 0x17de3f02, 0x3cf1f9cd, 0x8e8160a6, 0x47dc226f, 0x3f278643, 0xfe9ef80c,
5635 0x94fe80cc, 0x76e2ad2f, 0x9ee0f5f0, 0x574bfc2e, 0xf210f3a2, 0x2fe4c77b,
5636 0x7e82af9e, 0xf12f6674, 0x91ee7283, 0x7c11884d, 0xdb72fdf1, 0x0f99d1dc,
5637 0xe2bf450d, 0x5bd24156, 0x509fdced, 0x2edc0dce, 0xd9ef01e4, 0x343a0489,
5638 0xa7bdf95b, 0x3dbd2acc, 0xc793ca02, 0xe59fb4c9, 0x20d6e08f, 0x4331fc7f,
5639 0xd9a5f716, 0xd134fda9, 0x3371d4ef, 0x7a82f797, 0xc96ebe93, 0x9327f3c2,
5640 0x8afd6b7b, 0x5c6f449f, 0x29cf011e, 0x7fefb4fd, 0x88f59aca, 0xb543a9d7,
5641 0x2cb4cdfe, 0x38bdbd6d, 0x2a962466, 0x4b845ee9, 0x193fc289, 0xfdab06cc,
5642 0x1d3e6513, 0xd118af53, 0xe493ec17, 0x597482bc, 0xb9d9db7c, 0xcf4ede74,
5643 0x4d111ede, 0xbcd1cff7, 0xe6f02b5a, 0x55cec646, 0xa179e998, 0x20ecc2c2,
5644 0xc4569ff7, 0x8552f3d3, 0x55b7de95, 0xf8e7a40c, 0x90dfc724, 0x9f95053e,
5645 0x670fd1e9, 0xee34e955, 0x9acf8203, 0x9d1d5e75, 0xd124d85f, 0x82079a7e,
5646 0x8ef1739a, 0xa73607ac, 0x61739c52, 0x0c41ed43, 0x1d78141f, 0xf39c9093,
5647 0x883a2d0f, 0xc06bb2cf, 0x158023e9, 0x24a61c12, 0xa763eb94, 0x7ac6df67,
5648 0xe37b1be6, 0xd05183a9, 0x1b0af9ff, 0xc549f5c1, 0xac5e7a28, 0xb3dc13b0,
5649 0xa4961c92, 0x67d2a46c, 0x6db73fc4, 0x824fa53b, 0x12ad13fa, 0xb63f2bad,
5650 0xe4078f33, 0xd7c0daab, 0xb304ea85, 0xdc74e50d, 0x1e1b19b0, 0x9df7a864,
5651 0x1dc70889, 0xe2278a53, 0xcd46d338, 0xeeb47ba3, 0x7bf19afc, 0x58dc2695,
5652 0xe9f988dc, 0x247bcbdd, 0x3acbcbe2, 0xff18edeb, 0xa649ff75, 0xde0740fc,
5653 0xe3fe80d3, 0xe32f7e71, 0xe2d3d7e2, 0x362f3f50, 0x5fd0e358, 0x79f62ddf,
5654 0xe97a045c, 0xc5eceb55, 0x9cce7fed, 0x25bfd2a7, 0xfabaecaf, 0xf2fbf411,
5655 0xea1b48c9, 0xe2918bbd, 0x28b6467e, 0x9b48f504, 0x19623bc8, 0xd65015ef,
5656 0x5833d45d, 0xebcc18be, 0x9492bce7, 0xe382728b, 0x7a5d8d59, 0x6795fd28,
5657 0xed6a3efa, 0x6d4b6f1a, 0x41cf47e1, 0xe747b2f9, 0x723ac036, 0x61b6d599,
5658 0x135dd6dc, 0x066dfb4a, 0x87e0fa4a, 0x7c3d6f89, 0xd56488bf, 0xeb6c3c63,
5659 0xd1121b2b, 0x392dd80e, 0xfa823ee6, 0xffaf037b, 0xe48fd3d2, 0x53e7c2ed,
5660 0x823eaf65, 0xa08a4f78, 0x2b9ff376, 0x36fc8c1e, 0x5d5efd6c, 0xa9bfbc22,
5661 0x7c52d4e6, 0xc2a240ce, 0x926d8cf7, 0x8cdd778c, 0x865d4ba8, 0x1fb898af,
5662 0xfbc0b06e, 0xed9ff5d0, 0xf4107703, 0x08e2ed6b, 0x525757ca, 0x671bd7bb,
5663 0xc10f7fbe, 0x7bc04ee1, 0x8cf3dd35, 0xb8f03edc, 0x5c9f2237, 0x51b40e76,
5664 0x7ee1cd7e, 0xd973e916, 0xf5c36b19, 0x0ee75ea0, 0x4ff5831f, 0x76087bf2,
5665 0xc70d1cd6, 0xeabd11fd, 0xed082c0c, 0xad1f0c95, 0x56c9654b, 0x259659bc,
5666 0x64eb7f3f, 0xd7927946, 0xa53f5237, 0x99e61b66, 0x42bf5e8b, 0x13f61cf1,
5667 0xfc8feb66, 0x4fcbc751, 0xfd13b04c, 0xc17e368a, 0x2a0ecdcb, 0x2a77643b,
5668 0x0f945fdd, 0xfbf40c76, 0x5877588c, 0x47d270cb, 0x2ed672c4, 0x9f013f7c,
5669 0x3abdf02d, 0xfb809dd5, 0x0af594c3, 0x219f99d6, 0x839ba37f, 0xef739bed,
5670 0xf775a149, 0xa519d706, 0xfc8c679f, 0x46f5bd7e, 0xb66e1ebe, 0xf42778f0,
5671 0x4fe514bf, 0x64931759, 0xae1d5869, 0x6c98cf73, 0x3e37accb, 0xfee2ddce,
5672 0x2af813ae, 0x430d6c41, 0xf8ffba42, 0xe9ffc636, 0xfbf23dfe, 0x15675799,
5673 0xf941ecf7, 0x4fc3a4e9, 0xe619bf2e, 0xe003f82d, 0x83013820, 0xf2a7f50c,
5674 0xe38b2c3e, 0xb669d233, 0x2e2b7e61, 0x33dd116a, 0xd307f0a1, 0xdda0477b,
5675 0x995bfab0, 0xffb94bce, 0x7f714a1a, 0x4ddf787f, 0x7af471e2, 0x639e07c0,
5676 0x7bf07772, 0x5ac31a9f, 0xf403fe5e, 0x9bdc58df, 0x0dbbc6e2, 0xf756fefc,
5677 0xdc5df174, 0x5778dd27, 0xa27dc92c, 0x7601eb89, 0xd38d304f, 0x7e6cf068,
5678 0x8f4fbf1a, 0x85c7f6a7, 0xde671d9c, 0x955f707b, 0x7ba467db, 0x1822ab39,
5679 0xb55367dd, 0xfdc50064, 0xe07dbfea, 0xbda186df, 0x639f84b2, 0xacf0caab,
5680 0x55ff7dc4, 0x70e34cbf, 0x1724de48, 0x260e2fb6, 0xdd355d3d, 0x4071809e,
5681 0xba10b4e7, 0xfba7ba57, 0x28323f5e, 0x09ec89e7, 0x0ae78f88, 0xfdf533fa,
5682 0xca4e7f41, 0x57748c3d, 0x3a73d1f2, 0x8ecc22f3, 0x21de5bf7, 0x6e15770a,
5683 0xbb7e420e, 0x14e828a3, 0x178f6bc6, 0xb8c30d2d, 0x7e4e1de3, 0x359b273f,
5684 0x8f3eaed1, 0xfb24e7f9, 0x5657e461, 0xdeedd8a0, 0x1ed3c47c, 0xbdce999f,
5685 0xa847f901, 0x7f8544ed, 0xbe77aafe, 0x8ddaed87, 0x92e35ee2, 0xb6cda6af,
5686 0x6bf1faaa, 0xf27edfe7, 0x37bf330c, 0x7644cea9, 0x8ec27dc1, 0xb3bc9972,
5687 0xad5a0ed1, 0xf607fe73, 0xe9f85aef, 0xa277b470, 0x17fbf067, 0x09be31db,
5688 0x7a0a4f75, 0xff7c649d, 0x98517ba0, 0xb2f11bc8, 0x0f28d1f3, 0x9ec7a7bf,
5689 0x07e58850, 0x1f70d886, 0x99e45390, 0x7c44b958, 0xf9c2d272, 0x146364e4,
5690 0xe33e8fdf, 0x30e9d3da, 0xab8e938f, 0x7a848f6f, 0x79f81b27, 0xcc3cbf8e,
5691 0x2f9619cf, 0x60d2913b, 0x7baf3eed, 0xd97bf297, 0x0bf85def, 0x93da6f3a,
5692 0xaa5bddfc, 0xd21987dd, 0xce15fedb, 0xb5c67a33, 0x1287a849, 0x2d9f4a4b,
5693 0xdbdabd44, 0x2fbe2df9, 0x2394b637, 0xff77ca3e, 0x7fda0a7b, 0xda5ebbed,
5694 0xaf9e1071, 0xdeba9d19, 0xade97df8, 0x67618fa9, 0xd72f9ec2, 0xae403d03,
5695 0x34edea9f, 0x717e06f6, 0x63a6f04d, 0xe6864bbb, 0xf6378849, 0x1bb31b8b,
5696 0x5cdc6d3f, 0x115fa12f, 0x4f4e58dc, 0xe11c33d9, 0xc37928b8, 0xa71e1ef1,
5697 0xc97e8fd8, 0x188f0de2, 0x72c7f78a, 0x1f3ff5fe, 0x8ac5a048, 0xaed0327d,
5698 0xe71656a4, 0x27143c97, 0x025faff6, 0x0ddea9ef, 0xcbce57be, 0xac344495,
5699 0x66f44b1d, 0xee166f5e, 0xf74feceb, 0xfd7e5d32, 0x5fb574a5, 0x0eecffe5,
5700 0x9d3f9f2f, 0xa9bcc6e7, 0x7bf7df87, 0xe4068a09, 0x71266db3, 0x51f38f8e,
5701 0xc104d6db, 0xda8f9c67, 0xa8f00eb6, 0x9cf3b6e5, 0x8736ada0, 0x6bdbedf6,
5702 0x501ed073, 0x6b999fe4, 0x36677ee9, 0xda3876b0, 0xc23d8add, 0xf4e9b51c,
5703 0x8e9b53de, 0x3c75ebf5, 0xbb8ca73f, 0x7e24e5f0, 0xeb9998df, 0x0f2f85c5,
5704 0x94c6fba1, 0xcf37af7e, 0x4d46d501, 0x5b479079, 0xef9bd69e, 0xeffdf85b,
5705 0xcbf1f73b, 0x93c61ec2, 0x40f79d85, 0xbd73de76, 0xf2f05255, 0xfa0e5260,
5706 0xaaf28ca3, 0x0be07bbb, 0xbd21ae05, 0xf30b3fb9, 0xbbceb863, 0xbbfae23f,
5707 0xf331c33e, 0x6fd72836, 0xb6fb2348, 0xe9f8e74d, 0x79e71c30, 0x3ebaafbe,
5708 0x9cf947c2, 0xfdb967fa, 0x5de62e5b, 0x424ce11f, 0xc2a17a7d, 0xffee2f16,
5709 0xe96c3b26, 0x98e11589, 0x61dfaff7, 0xd5f8c0c8, 0x63fb3527, 0xad3e2f91,
5710 0x37ee9878, 0x75e3bc1c, 0x6e94a3ca, 0x1c7de07d, 0x8336d2f7, 0xd2acdd0d,
5711 0x8b5c5ebb, 0x56e948f6, 0x5be716b9, 0xe53f75ba, 0xbed52fc7, 0x71fb8e15,
5712 0x9144d42f, 0x53f08c1f, 0x1cf7fafe, 0x2ff8fe0f, 0xabc464f6, 0xc91591f7,
5713 0x7f78b5ee, 0x5a2d90c9, 0x3c7d17bc, 0xedea10e9, 0x18cff50b, 0x1fbc56f5,
5714 0xa6fdfb56, 0xeff96d06, 0xe4abaf3d, 0xd4e39091, 0xdcc85c74, 0xdda9f507,
5715 0xb5645feb, 0x3f18edb3, 0x9727bce8, 0xdae8edcb, 0xbb379475, 0x6e6e78fe,
5716 0xe9da853c, 0xa379ab9e, 0xe231b7f8, 0xe6b65efe, 0xdbc424e8, 0x5a2427bc,
5717 0x36bde6ef, 0xcfea00e0, 0x9aee3b53, 0x93d9cf42, 0xe8f91f09, 0xd67ee085,
5718 0x061bc946, 0x8e28cb65, 0x9e6ac2ef, 0xee5bca17, 0x8d69ee77, 0x2af8fedf,
5719 0x0d05f7ed, 0xbcc2bf7b, 0x79f99176, 0x3f741f8a, 0xfba1e3c7, 0x605e177f,
5720 0xac2dcfe4, 0x2814cef9, 0xcca851be, 0xda63fdc3, 0x264dc01f, 0xfff0fff0,
5721 0x4daee346, 0xe1ea3d47, 0x651b5531, 0x731957c4, 0x2349643e, 0x021bc5bf,
5722 0x8137cfe3, 0xeb4992dd, 0x4ae7cd21, 0x8f3a2f75, 0x5059ef0e, 0xda03de26,
5723 0xe4eb839c, 0x1b30ba95, 0x9cd69fdf, 0x02d57683, 0x21f9d328, 0x0bce2956,
5724 0xf1fee87b, 0xcd06d505, 0x1ec5e07d, 0x7255996d, 0xef14b0fb, 0xfa470ed3,
5725 0x92bb50b7, 0xa57ada2d, 0x91e39f30, 0xfb51ffb8, 0x5b7cc5de, 0x2b7da45f,
5726 0xefd498df, 0xb1547b15, 0x0e38958f, 0xe460b228, 0x7237bb97, 0x04b77a3d,
5727 0x0c3b45f3, 0xafb234ed, 0x420e3b3c, 0x2878aab9, 0xdff54fd9, 0xca5bfdf2,
5728 0x0caad4f9, 0x279e3a7b, 0x88375aab, 0xb25bbfe6, 0x7a863ea7, 0xd859ba60,
5729 0xe1ee8c57, 0xa44e2aaf, 0x1c23fbf5, 0x2ced0132, 0xf729ef6e, 0xeea227f5,
5730 0x18e371c2, 0xb53f8fbf, 0xb37a8bd6, 0x3fae29ea, 0x81563b14, 0x4f675f3b,
5731 0xb36e75c1, 0xcdebe9d9, 0x23a56ff7, 0x09bff9dc, 0x4557bc22, 0xfce8c2f8,
5732 0x0dd4517f, 0xc59ba7ad, 0xabcca0fa, 0x7dd07255, 0x293d4ae8, 0x9cdbeb99,
5733 0xa28bfb5c, 0x0b39c51e, 0x6fab1d72, 0x3c147c01, 0x1fa2b3ad, 0xbb6789dd,
5734 0x13ef1d3d, 0x94175d68, 0xcc9cf089, 0x47367ae0, 0xf6061bdc, 0x3c137dbb,
5735 0x9a759383, 0x32706578, 0xc163a7b7, 0x5af1c27f, 0x5438f227, 0xfc839658,
5736 0xe6a9c079, 0x19e53c1e, 0x302be02b, 0xa3f4fe3a, 0xd274f000, 0x7bc7027b,
5737 0xad12fdeb, 0xa21f3047, 0x83afce5f, 0x2ad00e28, 0x4e8503d6, 0xb4d92fc0,
5738 0x54bd09ce, 0x21f80ab5, 0x2da1ed15, 0x6afa835b, 0x0be286f8, 0x3ebe2eec,
5739 0x7c704554, 0x4c393d56, 0x6f82e5d8, 0xbf120c9e, 0x6cedc0c7, 0xec51fd65,
5740 0x3d3e6570, 0xef40e1d9, 0x7c2ac961, 0xe999d3f9, 0x7dead93d, 0x5e74fe94,
5741 0xd2986e60, 0x0bc1550a, 0x5c067825, 0x6b7d91d2, 0xde0892ce, 0x2a7ad581,
5742 0xb259d51f, 0x8da6ee51, 0x11f179dd, 0x7e7857d4, 0xebf47907, 0x39bbbeef,
5743 0xa951f707, 0x7dc472fe, 0xeb0fc8ca, 0xef183799, 0xd894afd9, 0xa03acd69,
5744 0x8fdfe32d, 0xb9fabb63, 0xf89efd5e, 0xdcfd9ff7, 0x69d8c159, 0xf85d8590,
5745 0xebc347ec, 0x4665fbd5, 0xb93c7236, 0x5f4f308e, 0x597677d2, 0x0467ef8d,
5746 0xcbfcee1f, 0x6e3023ab, 0x687dae31, 0xe9679e2f, 0xd3ef53a7, 0x5ed660ed,
5747 0xa3b4efb8, 0xee17ad31, 0x2438eb4b, 0xf0033987, 0x038056f5, 0x572ff1e3,
5748 0x5ed9e998, 0xf0652ac3, 0x8f99da2b, 0x6bba67f6, 0x5f902ccc, 0x73b934ba,
5749 0x739319ff, 0x3ba5f7d4, 0xa4ec7d68, 0x9fa9a5d3, 0xc77787e8, 0x569dfe3f,
5750 0x87f913d6, 0xebf715e3, 0x06b75e20, 0x740a4cb5, 0xe04aafde, 0xafbeda6d,
5751 0xe0e33f68, 0x943a8dc6, 0x3a35c1f7, 0x26b93acd, 0xca43ec59, 0xd7089964,
5752 0x61417db4, 0x438f4859, 0xe6082db2, 0xccfc6ae7, 0xd7e00ce8, 0xfb11e3f9,
5753 0x8702fdc7, 0xa7842d93, 0xf25a86dd, 0x365f772b, 0xbb29fdd3, 0x8125958c,
5754 0x23eccce0, 0xd8ebc405, 0x5f6833f3, 0x5e157fca, 0x7a87b5c7, 0x588e3173,
5755 0xbb1c78c3, 0x7d71bf1b, 0xd185b1d4, 0x710ef739, 0x1b63a80e, 0xa01ebca3,
5756 0x77dc49e2, 0x8b7df203, 0x80d63f7a, 0xe32f1d86, 0x28de5efa, 0x72e4fed1,
5757 0xf7118b7d, 0x221aba5b, 0x65bfcc64, 0xae3dc558, 0x59b0cb7a, 0x9c38392a,
5758 0x17e7e7ac, 0x07beecc6, 0xc972bdc7, 0xec87e748, 0xef747c07, 0x11c695c0,
5759 0x3cefbebd, 0x6c156bce, 0x7b3bde0a, 0x5f119938, 0xd0c1f3f8, 0xf29ac16d,
5760 0x8899d958, 0xd4cd34f2, 0x002da0f2, 0xc4528add, 0x7aa370fa, 0x89fff3cc,
5761 0xe8a63b1e, 0x8eaca731, 0x74a46487, 0x817163d3, 0xc962d8f4, 0x5ef8871a,
5762 0x871694dc, 0xd87c5cf4, 0x8f481310, 0xac38076d, 0x007f7720, 0x7b67c3f9,
5763 0x9bb1e81d, 0x0eac7a54, 0xbf0058f4, 0x3ae52924, 0x5ff3cc7a, 0x51db6f23,
5764 0xe798058f, 0x1fae14f0, 0xbc363d14, 0xb1e914f1, 0xcd3a75e1, 0x29feda39,
5765 0x5263d3d7, 0x2c68accc, 0x01216c1b, 0x89f106f8, 0x27c47779, 0xd41c713e,
5766 0x9629f967, 0xfd9f4bbf, 0xecfa7af8, 0x8abf08bf, 0x3afc5b3e, 0x3ba37f23,
5767 0xdfe231df, 0xfd18bbc5, 0x26e2cfce, 0x3716cfae, 0xcf0fbe31, 0xec0d8f4f,
5768 0xff18c7a6, 0x6f2f165d, 0x7d486aef, 0x2fe85ee6, 0x99b06ed3, 0x97667ea1,
5769 0xeb56cb5e, 0x1e94fcb5, 0x1ba1daf4, 0x0baf6bd3, 0xaafa06bd, 0x7f51ea2f,
5770 0x6a35b0be, 0xf763977f, 0x5edbf3e8, 0x5b78f943, 0x4701f3a6, 0x9dfebe45,
5771 0x90b3e7d1, 0x1e11eaaf, 0x4235d390, 0xdc2adb5e, 0x03f8ffd4, 0xdb657e7c,
5772 0xca0f5a24, 0x57bdb8eb, 0xf07b235e, 0x31a4e180, 0xff3ed15f, 0xe18926e2,
5773 0xa6e9b2d1, 0xfef1a7ca, 0x8192f630, 0xd4e53889, 0x143f150c, 0xf8a12a8c,
5774 0x999e8161, 0xc96ddf71, 0xb73fbe28, 0x7b959444, 0xf53b0ba2, 0xcdbedfa0,
5775 0xf7e9fb86, 0x7bcffc34, 0xdcf7134e, 0xf2417b4d, 0xdd5ffde0, 0x712a7bcf,
5776 0x97fbed38, 0xcba77cc5, 0xf61f842d, 0xde73e06e, 0xe5e3fb2f, 0x8d4bc090,
5777 0x478bc5ac, 0xe517880a, 0x8782ad5c, 0x565bb7e2, 0xf8a75c60, 0x32fc8959,
5778 0x782b79ff, 0x761f76ea, 0x909dff23, 0xdb62f7ee, 0xd25bbf35, 0x144477ed,
5779 0x7fcdfb3c, 0x323fa2bb, 0x37bc08d8, 0xf482f81b, 0xfc4ffb87, 0xb8c7421e,
5780 0x3d6a71fe, 0xc3c09afc, 0xe371ca88, 0x2e99add1, 0xd5f98afc, 0x804c1ff7,
5781 0xb71f67f9, 0x6303fdd2, 0x9ee898c7, 0x3e41adbe, 0x9f0a6fd2, 0x3e70fa19,
5782 0xecfd116b, 0x4b945c4e, 0x241a74fb, 0x2e13da0b, 0x37bf106f, 0x082df805,
5783 0xf67fecaa, 0x478124ea, 0x689efd0b, 0x006f5883, 0x4e57e8ef, 0xc01fd652,
5784 0x88cfca3b, 0xd7074e46, 0x2c874e16, 0xe567e3c6, 0xf30d92d5, 0xf70de5ea,
5785 0x8a3e711b, 0x50bf85de, 0xfc545d35, 0x27f357a9, 0x7bad547d, 0x34fbe225,
5786 0x1887e553, 0xfc06993f, 0x0cd891be, 0xfc3df7fe, 0x5f77eddb, 0x2f7bf3ae,
5787 0xa78e1f72, 0xf44788ed, 0xdc7d12f3, 0xbac2f26e, 0xddf5d610, 0xf06b77a5,
5788 0x6bb9fe38, 0x249abf9c, 0x3b01c62b, 0xefc354f1, 0xf056cf6d, 0x788afc84,
5789 0x63279c6f, 0xf8837e79, 0xf9bf1fdd, 0xb5083ee2, 0x9d37171c, 0x906ffde2,
5790 0xbcc02c6c, 0x7fdfe47b, 0x927b6f90, 0x2d1f435f, 0xe413beff, 0x2efb823b,
5791 0x77e24ddc, 0x34231a19, 0x7dfec279, 0x35b01db8, 0xfd1cf808, 0x1b06c3e8,
5792 0x2fe0a7de, 0x3d62b1ef, 0xaadf7b43, 0x420f97ca, 0xb12e3180, 0x28ceccc5,
5793 0x76e5f470, 0x6edf5aa5, 0xb331620f, 0xbfee7ab2, 0x4f5ba09f, 0x1e528df6,
5794 0x5ea1e386, 0x54f1806c, 0x7d7f2cf9, 0xd7e5f8af, 0x0fc6579b, 0xce32979c,
5795 0xd87e7bdf, 0xfe799ac5, 0xd0245f02, 0x26dfe179, 0x9fa9bc63, 0x7bdf57a4,
5796 0xfe6fdcae, 0x3b3fe84f, 0xfee7a625, 0xf685bc59, 0x4efb2937, 0x0e3cfd94,
5797 0xf3fb130b, 0xae33fe6f, 0xfcec57e3, 0x8e9641fc, 0xae33707d, 0x3a06b90f,
5798 0x88e57ac7, 0x573fe281, 0x2e7bf026, 0xbf7b7f6f, 0xedf2f51e, 0xff0114a8,
5799 0xe44b67b7, 0xaec51d1f, 0x6d1da347, 0x80257da6, 0x1f9811bf, 0x1ca9a8c9,
5800 0x333ee78f, 0xe19678b7, 0x17de36d3, 0x6dd20efd, 0x7bf74c9c, 0xc6a3db34,
5801 0xc0fa3ae3, 0x71819659, 0xa9ef5877, 0x1621e67d, 0xd8c6f583, 0x18fdc863,
5802 0xb1f9f75d, 0xe8c70099, 0x0acdb223, 0x0fefa6f5, 0xf77cc50d, 0xe63af5c0,
5803 0x0c6be154, 0x73c32cf3, 0xed5ba33e, 0x22ee1133, 0x2e305fb0, 0x71b8d45f,
5804 0x2e439e19, 0x7b512f5a, 0x2939db97, 0xbdb3e61c, 0x4349b3fa, 0x3d401f50,
5805 0x9eb5c6ec, 0x48d573d7, 0xcf394c36, 0x24675c6f, 0xefc3517d, 0x91eed86f,
5806 0xebf79998, 0xdbbf4331, 0x2cfb43d7, 0xd05b638a, 0x7cd5720e, 0x5cdffb46,
5807 0xdfb52700, 0xccc5cfc6, 0x94567687, 0xa9fb9a97, 0x12f5e2bf, 0x457323c3,
5808 0x543af8db, 0xc360c474, 0x9f7b75ef, 0x2a74f5a5, 0x8a90978c, 0x02778eeb,
5809 0x884739c5, 0xffc77b7d, 0xed5df90f, 0xd58fd38c, 0x2feb92fc, 0x9fbf2989,
5810 0x4f9f57ab, 0x97d3e8eb, 0x2db10bef, 0x3f414631, 0x498a8cef, 0x7d5f11d5,
5811 0x71b4e746, 0xf013935f, 0x179c547d, 0x8cea3fdb, 0x409f7d51, 0x4f3f2b2f,
5812 0x8e30d05b, 0x321551ce, 0x9aa39d07, 0x8fdb9a36, 0xc828feef, 0xde33fb83,
5813 0xe37af835, 0xe23ffdfb, 0xb6dcd3bf, 0xb6dfeb9d, 0x1fda16e4, 0x307f1e7b,
5814 0xb65c6009, 0x717d265e, 0xce819b7e, 0x7018c90d, 0xe76dfc44, 0xf5fec5f6,
5815 0x5bf3dfbc, 0x7e361db8, 0x70931dc3, 0x59b05dbd, 0xf5c46739, 0xce3fe2b3,
5816 0x62f388b7, 0xfc8d1b95, 0x5fefacde, 0xac3d1477, 0xbf911efc, 0xfceb2d9e,
5817 0xc92f6cfd, 0xffad594f, 0x2ed0ccf9, 0xefe9043f, 0xb9f88afd, 0xa18188fc,
5818 0xb99d221f, 0x4f8ff944, 0xef871d70, 0x3b251ba3, 0x3a2a3b9e, 0x1d90f26e,
5819 0xdf7799ed, 0x393d71cf, 0x3afba261, 0x1cf055ce, 0xef9328f6, 0xf781bf2f,
5820 0xe3351c9f, 0x97e03cce, 0x05ef8479, 0x3be1116c, 0x473f336b, 0x2ab47597,
5821 0xe7ae3e76, 0x7fdc7813, 0x9cccb541, 0x89f0fd2a, 0x37799f64, 0x1ee8175f,
5822 0x598e856b, 0xb8f9cac6, 0xe562de9e, 0xd9bad8fa, 0x2fcde740, 0x760cfd08,
5823 0x5103dd3e, 0xac5d6bbc, 0xe2ff4551, 0xf8b175a6, 0xc42b2853, 0xe265b439,
5824 0x91b17a9c, 0x47bc538f, 0x8d546cb2, 0xf4a3f4a3, 0xdbc5dc6b, 0x67f135a5,
5825 0x2317fd4f, 0x2fcf347c, 0xfc27a88c, 0x7e36e9fb, 0x7a8cfd0f, 0xee155aff,
5826 0xaef51817, 0x8c72974c, 0x2d35333a, 0x0f643ef0, 0xd31fcf8f, 0x747f7e69,
5827 0x35825fd4, 0x6cba91f9, 0xdfa07790, 0x4edc0d6d, 0x653ecbab, 0xb2a2cb2c,
5828 0x5cbbe505, 0x27cb85c4, 0x75f57df0, 0xa3974719, 0x92cd4fbc, 0xdb981f88,
5829 0x29dfc469, 0x8accbb07, 0x5905a779, 0x6802fdbc, 0xf758728f, 0xd04b972c,
5830 0x1fd4560f, 0x830017ff, 0x8000007b, 0x00008000, 0x00088b1f, 0x00000000,
5831 0x7cedff00, 0x55537c7b, 0x393ef0b6, 0x526d3479, 0xa0fa5b42, 0xb4db4e50,
5832 0x9494b14d, 0x27457897, 0x880b5a3c, 0x46107006, 0xf4228206, 0xbd185499,
5833 0x35fde338, 0x9c414415, 0x0e7c570b, 0x42d2d37a, 0x1429a2c1, 0x20d5b16c,
5834 0xb47441d2, 0x3bd15ef6, 0x0f8afea3, 0x52d25a04, 0x8ef4f987, 0x6b5adfa3,
5835 0xa126d39f, 0xdf7ef515, 0x37f5375f, 0xef6758b3, 0xbdeb1fb3, 0xce275ef6,
5836 0x620a3b5d, 0xd67318e3, 0x319e920a, 0x6abd54d6, 0xc614f273, 0x2c8ba68a,
5837 0x67e7c242, 0xf01192b4, 0x2c7133e6, 0xd3e3b187, 0x1939db3f, 0x74339dda,
5838 0x7ff41d26, 0xc637d357, 0xf3ec6064, 0x991cc64a, 0x5ea5b388, 0x698459c0,
5839 0x8c09e2c2, 0x060e313d, 0xead8ca99, 0x0c0599e6, 0xeccddf9e, 0xf8bfb19b,
5840 0x7981f436, 0x47a20d5d, 0x2e9c0027, 0xc60dba8e, 0xc680f77d, 0x7e3b280a,
5841 0xfdda8e83, 0x153da007, 0x4faed8e0, 0xdcbfc004, 0xe86e61a5, 0xc89771b0,
5842 0xb2fff418, 0xc5f7a05e, 0x90597ee7, 0x3adaf804, 0x2983aac1, 0xad9aef8f,
5843 0x1efec24d, 0xd9bc61c0, 0xbc6869cf, 0x7f78fbb5, 0xc5e433f8, 0xf186b633,
5844 0xe2a635bf, 0x632e599b, 0x65a7cce5, 0x69efd0e9, 0x115da7cd, 0xf87bedbc,
5845 0x1827b15f, 0xc60fad2f, 0x4bb6d9cb, 0x6f403462, 0x750ef3f0, 0xef386dd7,
5846 0xb4f41bfa, 0xb637d9ee, 0xeb8f5e9c, 0x5c30d06e, 0xef1bece7, 0xba02ef8f,
5847 0x963351ae, 0x8e90693c, 0x0cc788e5, 0x559d8eb1, 0xb31fa4da, 0x1c75909e,
5848 0x3b8c6719, 0x63fc0d7b, 0x3df49b12, 0xb8dcee90, 0x628d8c91, 0x740b5dcc,
5849 0xb67e0049, 0xf00f360a, 0x4765b8a5, 0xf3d616bc, 0x02fdfe3d, 0xf11db6f0,
5850 0xb6d73c22, 0xbd2fd408, 0xad62c38d, 0x60aff16d, 0x0aafc51f, 0xb0696aa6,
5851 0xb9ce32bf, 0x7df10271, 0xbfef3373, 0xb5e015b1, 0xac5f8fc3, 0x0ac6bedd,
5852 0x65dd4a70, 0x72b864ad, 0xb17e651c, 0x739c782d, 0x8e857cb2, 0x2c1a2f97,
5853 0x10bba46a, 0xaf7e4569, 0xadbcb817, 0xdc799bbf, 0xacc94f20, 0x87406042,
5854 0x9013e644, 0xbd29c0df, 0x86fce41d, 0xcb55903e, 0xf17edd20, 0x1d5b0475,
5855 0x6c99c740, 0x3b3e1064, 0x7fa82922, 0xa83529be, 0xecc4a6fd, 0x52b9f6a0,
5856 0xdf3e105e, 0xff505d72, 0x4199d605, 0xe7d3adf8, 0x685ff506, 0xdb84185b,
5857 0xeb8d4998, 0xba5cad6f, 0x999073f8, 0x041d2b57, 0x70287a15, 0xd8c54e86,
5858 0xee0bc13f, 0xa036ec9b, 0x19288ccf, 0x3e397367, 0xd8d1f002, 0x06ddb37e,
5859 0x20919d74, 0xc7016ce3, 0x05f69593, 0xe538ffbc, 0xfb785bfd, 0x2dfb4a35,
5860 0xd2a27dbc, 0xafc72b7e, 0xf1eed467, 0x03776adc, 0x8ed1ebfe, 0xb6f8096a,
5861 0x138aebe4, 0xfde9a023, 0xa77745aa, 0x45583f02, 0x18d36306, 0x0034875b,
5862 0xed182ed6, 0x351a4a78, 0x7ff4aed8, 0xe357b255, 0xd14bdef3, 0x63226cb9,
5863 0x51dfc80d, 0xe6321f3f, 0x716779a3, 0x1159b2d2, 0x33ea1f06, 0x0cf4d08b,
5864 0x631a51e8, 0x0db18d82, 0x906f4831, 0x0477a213, 0x89a55f41, 0x8995ebe0,
5865 0x94a8df04, 0x63336ad8, 0x821695ed, 0xf4ad2b27, 0x74e554fc, 0xda576f82,
5866 0x5953be08, 0xd2a3b048, 0xe290504e, 0x9f1872d8, 0xa23eb1ed, 0xd5b87a41,
5867 0xfcc2cf23, 0x7e40cff8, 0xd4c64286, 0x1722acec, 0xcabf79d0, 0x65f48ad6,
5868 0x6ce98c6c, 0x5ef3e0d4, 0x815243a1, 0x46a7bade, 0x0f40eb58, 0xf37a0f8c,
5869 0x4617a04c, 0x11bac1a7, 0xe59c6168, 0xbb43524b, 0xbad69d71, 0x029fda11,
5870 0xf587ab73, 0xda991ad4, 0x1cc9f602, 0x34f1100f, 0xf7aa8d0e, 0x7fec0552,
5871 0x1ff5045f, 0x0236c603, 0x196825fa, 0x7de0f7c3, 0x1ffd8116, 0xdfd81163,
5872 0x684024fc, 0x10e1adaf, 0x37f48224, 0x43cde741, 0xe2e09efb, 0xd555d8eb,
5873 0xee304921, 0x5c7ca9ae, 0x29f13158, 0x8119cc5f, 0x499fb2f6, 0xb8394c23,
5874 0x005abd1f, 0x83d5e881, 0x2bb009df, 0x45034f59, 0xdb24f402, 0x01d4c113,
5875 0xbd4d757a, 0xe09f0829, 0x3fea0c4d, 0x6a0a59b1, 0x8259f3cf, 0xb49f27da,
5876 0x3b53e106, 0xbff507a6, 0x105b43f6, 0x61575d7e, 0xcfebff50, 0xfef083d9,
5877 0x618fd81c, 0x94defe78, 0x9ff50428, 0x703ade0b, 0x89aac67c, 0x232df33e,
5878 0x1bf79e83, 0x1b869d38, 0x78358177, 0xb71f855c, 0x7f1e0f4e, 0xdc782da1,
5879 0x3d87cb1f, 0x906a27a0, 0x13d07aff, 0x4f41fb84, 0x0de720d4, 0xbf8827a0,
5880 0xd0827a08, 0xcf827a0b, 0x209e820f, 0x827a04de, 0x13d011f8, 0x4f419bc4,
5881 0x3d051e10, 0xa357e7c1, 0xef3cbb57, 0x53de7949, 0xed8cbcf2, 0x8d5d3a20,
5882 0xefcb6f2e, 0xdfbf23bf, 0x079bef81, 0x30bcb0e5, 0xc835f543, 0xf398ccf3,
5883 0x87582eda, 0x01575d6d, 0x6f7d4dc6, 0x8246ac8a, 0xc9cf0e6e, 0x5aab8c4a,
5884 0x9456d962, 0x5bdf7b5f, 0xa70fc42a, 0xfb42b69b, 0x78ffe696, 0x4dfddb07,
5885 0xcdf184a2, 0x459fcdeb, 0x5f3d38e3, 0x2c753247, 0x3459f7be, 0xdf654bc6,
5886 0x42b7c230, 0xb9c5fa3b, 0xe5f3228d, 0xb57bbaa0, 0x5663ded8, 0xe3168f70,
5887 0xa3437b33, 0x5a52f916, 0x6fed48df, 0xedc1357a, 0xed41d5f5, 0xb00fec26,
5888 0x4689ed54, 0x56685e7a, 0xff51f3c6, 0xc3f73332, 0x6f8fea17, 0x5bd61ebe,
5889 0x562ab8de, 0x3697f584, 0xd77f17bc, 0xe2ffd00f, 0x1c721791, 0x0b797ef0,
5890 0x1c18678c, 0x2345bcaf, 0x65fd7ce3, 0x1882c6e6, 0x621a1ba0, 0x87acfcb0,
5891 0xc01b676d, 0xd736942e, 0x577c6195, 0xc343b96a, 0x5ebd3e80, 0x01d710b1,
5892 0x71062a7f, 0x9189995b, 0x7ef1e87f, 0x8c177d15, 0xc4f79afb, 0x7a87e82d,
5893 0xe3478f5b, 0xd04dbdbc, 0xabbf803f, 0xb11c7953, 0xfc4b553a, 0x1e3a69eb,
5894 0x16fb412d, 0x774e71ef, 0xfff68fb5, 0x02f78cba, 0x8b377a24, 0x5afa2e3c,
5895 0xc6507c45, 0x9a33a173, 0x4619ed8a, 0x97a757dc, 0xaa7f77cf, 0x579b9fc4,
5896 0x9ff5c6ad, 0x55365c4a, 0xae05fb24, 0xf1def01a, 0xc2b6ebf3, 0x30bd4a52,
5897 0xf7f210ee, 0xbb6e3ca8, 0x69bf471c, 0x1a3ed43e, 0x30aa7ee8, 0x807c8f36,
5898 0xaa636fdc, 0x6815fa8a, 0xe80ae61d, 0x8c9069d7, 0x160fcf28, 0xbf911ba6,
5899 0xe7c423af, 0x0eb5bb85, 0x7c4d2580, 0x47534ebe, 0x675dca34, 0xe31164d3,
5900 0x7fbc6551, 0x901de791, 0xb9be01ef, 0x9e454f89, 0x338e036a, 0xfcfe3fc8,
5901 0xbd1354fe, 0xdef3ca77, 0x7f603b92, 0x2b28969d, 0xcb5da5f2, 0xa5fd708a,
5902 0xbe7160e8, 0xa46ae4d6, 0xfddf3283, 0x2d7a3f32, 0xbfabe22a, 0xbbf72359,
5903 0xf5058ea3, 0xd57e70d3, 0xe4c7af06, 0x3bfbf339, 0x73d97fa0, 0xbef8c322,
5904 0x8f11534c, 0x20fcc7fb, 0x9d32dd68, 0xf8be34cb, 0x2d7900f8, 0x1bd0196b,
5905 0x8b79c903, 0xf11227a2, 0xa763e153, 0x4aebe445, 0x2c1879d4, 0x8eb1acb9,
5906 0xced41ae4, 0x4d3907ad, 0xff20ea8e, 0xdccffc97, 0xfc0ad54f, 0xfb2559b9,
5907 0xb5c7154d, 0x3e2fd100, 0x7853fb27, 0x1f00999f, 0x00146c0b, 0x4fa614d7,
5908 0x917c4155, 0x21e6362c, 0xb6a9753f, 0xff9854a6, 0xc87ec97d, 0x6489f142,
5909 0x553e43b4, 0x66e0d97e, 0x7efed023, 0xdbce24f4, 0x047904df, 0xd11e5bcc,
5910 0x9073ef3c, 0x282b7ecf, 0x7fb7ac08, 0x5ce28697, 0x00833b10, 0xe99acd71,
5911 0x94be5f5c, 0x8844d31c, 0x54abcb17, 0xc832afb4, 0x5f98f4bf, 0x62eef6c9,
5912 0x28adea63, 0x452765a7, 0x2be60453, 0x9d7fd4de, 0x86837881, 0x57a72af2,
5913 0xff30fab0, 0x255a326b, 0x9deacfc0, 0x9d379869, 0xe2d3eaad, 0x3e21677b,
5914 0xcbcf9c7f, 0xa7cb4f50, 0xd4519f73, 0x193da3bc, 0x57e60960, 0xafc8cfe2,
5915 0x3a99f242, 0x8c75c7fc, 0xf21539fd, 0xb26f8c1a, 0x37c63659, 0x048ce2f9,
5916 0x7f995fd2, 0x1710276c, 0x13f5a612, 0xdfa809ac, 0x3cd2d45b, 0xab6f77dc,
5917 0x71f484c6, 0xc62a1db5, 0x22ca7b75, 0xafd82aad, 0xa251c373, 0x815fef63,
5918 0xf65710ce, 0x33ca3226, 0x67a7197b, 0x6797336f, 0x44f04697, 0x9e20fbe0,
5919 0xe0845e34, 0x5ea682a9, 0xd9347f77, 0x510ac621, 0xcb2dd7fe, 0x68bc6150,
5920 0x80337203, 0x57b91447, 0xf5c0a5fc, 0x977546fc, 0x7bde1238, 0xe7fdc343,
5921 0x48d353df, 0x9968e7ee, 0x46f5f103, 0xc62bf92b, 0x887de8aa, 0x52fe28a7,
5922 0x67c435fc, 0xc7254f14, 0x147e497a, 0x6d50bc3f, 0xab8e04d2, 0x821bdfbc,
5923 0x0580f32b, 0xe0ede3e1, 0xf8c0def1, 0xa6fc7923, 0x1e740f8c, 0x6afe7481,
5924 0x70fc958a, 0x91f042ca, 0xa41577a4, 0xf59e8a77, 0x01cd5c80, 0x3810cab9,
5925 0x1d76cabf, 0x728073a3, 0x00e741d6, 0xde7cd105, 0xf11f9c02, 0xd2130e48,
5926 0xedffda04, 0xdb5e9c69, 0xa7d8a864, 0xc4b66913, 0x698d8034, 0xa469318e,
5927 0xb792261f, 0x408cb2f5, 0x35d0927c, 0xf75d7d84, 0xf06e7e27, 0xda3dc815,
5928 0x08575f99, 0xfe203992, 0x6ed3fd29, 0x69c34b2d, 0x18161d6c, 0xbd7188af,
5929 0xc5d9e451, 0x1b95b2bb, 0x303992f4, 0x7fc3b2fe, 0x72c567a0, 0x279e117b,
5930 0xd8e0fe40, 0x27992f10, 0x8f627bc3, 0x4fd73c16, 0x73577396, 0x73d3ee30,
5931 0x0519f379, 0xffc9c60f, 0xf5e72694, 0xc8a7fcb2, 0x10ed58f2, 0xabdf683c,
5932 0xee1355bf, 0x90782e5e, 0x8784bf07, 0x45e4621b, 0x99a2bf62, 0xbf47f41e,
5933 0x8ef29404, 0x2fa4719d, 0xb9fb08d4, 0x2fffde4d, 0x0263bed5, 0xc684e7ec,
5934 0xc2f98a9b, 0x2b08f289, 0x418cbf8e, 0x64f60180, 0x7820eb39, 0xd879ca3a,
5935 0xc7bb8347, 0x81ff3c62, 0xf8c56743, 0x8d537aa7, 0x2e66ed11, 0x3cc264db,
5936 0xff514805, 0x9f1fe4fd, 0x0b8830cf, 0x5f0aff90, 0xcbecd31b, 0x073f00d2,
5937 0x749c493c, 0xefa5fbe5, 0x3e468e1f, 0xd0e6ff76, 0xda19db92, 0x3bb23e9d,
5938 0x1a551525, 0xa8c41c9c, 0x906d32c3, 0xe0bf0abf, 0x1f1052df, 0x90630f61,
5939 0x42cf622e, 0x177ffbd2, 0xabb1fa19, 0xf3a151f1, 0xac7e642f, 0x21f6e16d,
5940 0xdd0abf94, 0xa21e676f, 0x5daff81f, 0x23a617c4, 0xffca147b, 0x0407f1ab,
5941 0xcd363971, 0xe431d38e, 0xdb8ab26b, 0x2035e4ab, 0x3beeb02f, 0x0bada398,
5942 0x8fa892e0, 0x32e72434, 0x7ccb969f, 0x167980fa, 0xdfff5258, 0x9a44e9f1,
5943 0xe91a7b63, 0xfd4869ad, 0x32c7d50c, 0xe2aefac9, 0x67a43c6f, 0x3579fac1,
5944 0xf85664bd, 0x8e7f802f, 0x7fa4d10d, 0x625d7f0a, 0xd5f7e903, 0xad18f3cf,
5945 0xf059bcab, 0x847f52f8, 0x10b00a5e, 0x884363e0, 0x1afc2a3e, 0xf6291ece,
5946 0xfb96b4ec, 0xa27df763, 0x8ff2f307, 0x1309df05, 0xceeca7da, 0xd282640c,
5947 0x8eaae3ff, 0x38c0f7b1, 0xf0e4cf1f, 0x0159c634, 0xad922db8, 0xa49e23b4,
5948 0x3f7ee373, 0xa167b216, 0xf858fe7f, 0x9e385be7, 0x5f1095a0, 0x04cb3096,
5949 0xef0d69f8, 0xc57dd8af, 0xecbc7fde, 0x4fd439da, 0xbee06f60, 0x47a25c60,
5950 0xa782fddf, 0x256a4406, 0x5f5c6a98, 0x0aa7acea, 0x27f9e0d3, 0x43cf4dbf,
5951 0x05d6d87e, 0x2e7e878f, 0x3ce22275, 0xebf1baef, 0x9caacd3e, 0xfc0679c1,
5952 0xf44b9cd4, 0xfd53f15c, 0xb25a1965, 0x2833ab53, 0x69922fde, 0x1ec98b6d,
5953 0x87f829f1, 0x08fa4f7e, 0x5fa0ce55, 0xc8793fe9, 0xefa008e0, 0x4c3bf079,
5954 0x3f67801b, 0x97e81296, 0x3479ed8e, 0xa451f913, 0xb9e2e775, 0x3feab9e3,
5955 0x2edfa0a4, 0x2670f3da, 0xb67b8dc5, 0x5ffc6264, 0xa668f354, 0x0728f08d,
5956 0x4e6a1fe5, 0xd703ee87, 0x101adeed, 0xf26526a7, 0xc47979f8, 0x1f8c7cb1,
5957 0xf1735de7, 0xcbf41321, 0x4260adf8, 0xeb35f831, 0xddfd0878, 0x77970b0a,
5958 0xec8233b6, 0x43678c31, 0x2f65d7be, 0x3d7d45a8, 0xb34cf965, 0x74bfe31a,
5959 0x056bd135, 0x804b6cf3, 0x6088f676, 0xfd8163aa, 0xff6356c7, 0x6d049b55,
5960 0xb1fa1c62, 0x97987991, 0xd247d2e9, 0x247cee3a, 0xaf9f1daf, 0x9f3f8078,
5961 0x7534f3a7, 0x694f38e2, 0x37a475ad, 0x278c34f6, 0xd2ebf595, 0xcadef4b5,
5962 0xcbc5026d, 0x4f193cca, 0xee0757c6, 0xfdce9753, 0x8db29b32, 0x32adcfec,
5963 0xe07e6e5f, 0x611237bd, 0x1d6349dc, 0x7f6874c6, 0x66b389e7, 0x139f3c1f,
5964 0xf3073e73, 0xe3ad0c86, 0x77dc62d9, 0xfb8ace8d, 0x2c9b9298, 0xdfff6026,
5965 0xe11c7ccc, 0x3d5607ca, 0xf2768c5b, 0x73ca08e9, 0x13adf594, 0x83e61524,
5966 0xbf6fabc7, 0xee76e913, 0x778a0889, 0x256755d7, 0xdfc81fb0, 0xa5ff02f7,
5967 0x41f6c64c, 0x05f08efe, 0xd825dfc8, 0x44ca81e2, 0x94aa5fc2, 0x5ca5b208,
5968 0xb899d6be, 0xbc6e193d, 0x4b9790c9, 0x3ca64760, 0x7c41e302, 0xcd9c6f38,
5969 0xcaf40e92, 0xb35e5f18, 0x0657de45, 0x4ee79fbc, 0x98748d9d, 0x769ee5b2,
5970 0xd2e31d0c, 0x56f2fe79, 0xa82923e7, 0x381f6bc7, 0xb4317cf3, 0xe7b74aaf,
5971 0xbb11fbe1, 0x7e3e512e, 0x15e1e5bc, 0x1aa2ef48, 0xbc9fdf1d, 0x644f73ef,
5972 0xe78b3c26, 0x286a6f75, 0x3aed763f, 0x8016fcf3, 0x47bb6d77, 0x3fef281b,
5973 0x7113bf76, 0xba7f533d, 0x97470d9e, 0x8f67ae9f, 0xd53e90a6, 0xfce59e80,
5974 0x3d733d7c, 0xdcf44550, 0x15ff6e9c, 0x8d39dbca, 0xebf5053b, 0x240df65c,
5975 0x8136eef7, 0x5fd8a1f8, 0xf2a5fde5, 0xde554bfe, 0xce02336d, 0xc6432f15,
5976 0xd63ef486, 0xc62665f2, 0x979b97b5, 0x47dc088d, 0xfb023c28, 0x35864c86,
5977 0xda7dbd03, 0x69a7db2b, 0xd856e91d, 0x8f1534df, 0xabdb4367, 0xbdb255d2,
5978 0xcf0ffc85, 0xc5ff1433, 0x0f78b43a, 0xf82ad651, 0xaa3ef122, 0x6af3a6f9,
5979 0xd81257ba, 0x7de741a7, 0xe01a7d8c, 0xe75b8777, 0xc713a0d5, 0xe3da0f51,
5980 0x31543f6b, 0xbdbf805f, 0xf9922bae, 0xc81de602, 0x114f6023, 0x4b7f1fc0,
5981 0xd87d9052, 0xe7042e9e, 0x36aef013, 0x15f21fa0, 0x2dfc65ef, 0x9f8835d9,
5982 0xfb3e72d7, 0xc47c408f, 0x389849cf, 0xe71e906d, 0xd173ba5b, 0x70f42b2e,
5983 0xb926ed1e, 0xf87e6b29, 0x99f44092, 0x7b9d5e7b, 0xdb1cfa75, 0x7c8b9dd3,
5984 0x9ae9af3d, 0x5f947986, 0xfc8b95db, 0xedc2be71, 0x93a54ffe, 0x11f8bcf2,
5985 0x05d800d8, 0x3ca260a7, 0xa1ec5f2f, 0x927fdcbc, 0x96cee5e7, 0xfb7764dd,
5986 0x88b9f95b, 0x9051d54b, 0x1508e780, 0xeed1da67, 0xfcf227f5, 0x21b7c609,
5987 0xcba466bd, 0x97dd53fe, 0xdfec10b2, 0xe1390189, 0xd439da79, 0xe38e2d73,
5988 0xc17b432d, 0x1d58a372, 0xf501778c, 0xd8af9e1e, 0xe519ba90, 0xd4679cff,
5989 0x6fa3b424, 0x49ddfee5, 0x45af68e7, 0x638a4499, 0x7f0069e0, 0x11e1f607,
5990 0x1e282d99, 0x80b6628a, 0x74ad2e7e, 0xa7bfc52b, 0x74c7ba44, 0xc67ae78d,
5991 0x2b3d728e, 0x9b4c74df, 0xa35e3018, 0x7894f76c, 0x7f6bde70, 0x345d7d27,
5992 0xf023b991, 0x14f597bd, 0x2031b0e7, 0x7a2f80ff, 0xf283c139, 0xdca8f7e0,
5993 0x178bc81a, 0x87fee64d, 0x7ef1d21d, 0xa454d289, 0x6af31f87, 0x4c794fa0,
5994 0xc00c6647, 0x2b89df23, 0x4e4f98ed, 0x2be01c02, 0xf2cf9702, 0x23991d45,
5995 0xd0495cf1, 0xa4bcf0ab, 0x77b786bc, 0x54bc78aa, 0xf7dfc69e, 0x7b57dc0f,
5996 0xde821653, 0x9cbdb6f5, 0x5be02772, 0x9c35be0d, 0x7c4cbe0f, 0xb99eda0e,
5997 0x46efe608, 0x5cf74d9f, 0x5ed08be5, 0xdc151b75, 0xf78c71c9, 0xb5cd9ee9,
5998 0x5baae508, 0xbc15e0af, 0x5c64105d, 0xe5c15f79, 0x8c8547f7, 0xb4859237,
5999 0x0a4ff487, 0x3dca35c1, 0x58ff3c9c, 0xb517fefe, 0x7bc22cf7, 0xcf3af9b7,
6000 0x57f44ac9, 0xd218692f, 0xf0e07f55, 0x697fa459, 0xb33bf70b, 0x39ee1c0e,
6001 0xd872f288, 0xb1e6f748, 0xe3e254e6, 0xdbbd96c6, 0x375ca126, 0xada073f2,
6002 0xff3fef0d, 0xc3a7ea3b, 0x57183163, 0xe69eb759, 0xebca2f9d, 0x1e39eb66,
6003 0xdfb3b725, 0xb2847c72, 0x3c71dfaf, 0x6b7fb796, 0xa75a17fe, 0xfb81f0ff,
6004 0x9fa05e50, 0x17a5e29b, 0xa2605e40, 0x73d94392, 0x1bf59e30, 0xfce0563b,
6005 0xab3afdce, 0x09e7c25b, 0x95be30b3, 0xa4dcfccc, 0x14f6fc78, 0x4754a7cc,
6006 0x1df9edf7, 0xd7efbb9e, 0x2ba139d3, 0x12a5db86, 0x3dda7ab1, 0xf7bb3f24,
6007 0xb5f701fc, 0xf6e74f4f, 0x1edcd1c5, 0xa0c9ef15, 0xfe579ef3, 0x940ad9f1,
6008 0xd7717c83, 0xd7fe7c1e, 0xe90abd5a, 0x8db5a9d4, 0x4cfd01b8, 0xa9e286a7,
6009 0x3e2f1962, 0x13d7cb1d, 0xf24055d5, 0x653db713, 0x4948c811, 0xe0b7fdec,
6010 0xdb8be7ba, 0xce7f479f, 0x0ce8eaf6, 0xa03efceb, 0xbe77bc2b, 0x2da7434e,
6011 0x35467dfe, 0xb0b76bca, 0x38b3c57d, 0xd7ef1d7e, 0xf44edfad, 0x3165d776,
6012 0x31fa0f9c, 0x16ea9f3c, 0x3f3d0476, 0x1737b75f, 0xfb0bade3, 0xa5dc53e7,
6013 0x97a293e8, 0x20bab525, 0x293fc7fd, 0xf963f31e, 0x8666e4cf, 0xc2e9fc80,
6014 0xcffc6791, 0x85f5e806, 0x0b4f8d06, 0xb1d62a34, 0xa7af784d, 0xf24963e8,
6015 0xbfb8854d, 0xe6755512, 0x278bc03a, 0xbd40ad77, 0x1167af3c, 0x2defd089,
6016 0x2e0f3f15, 0x885aaa69, 0xf5b87b76, 0x7c799b14, 0x9f913979, 0xd66e5f97,
6017 0xa9cf027b, 0x9547e143, 0x3d5b7a4c, 0x42baff88, 0x19473e47, 0xb7ad2def,
6018 0x670ee30c, 0x9fc3f70c, 0x3306ff40, 0xee6661c4, 0x086e56a7, 0x1cdcbfee,
6019 0xda9dcf43, 0xcbb44cae, 0xcccbf8ca, 0xd4cf6e26, 0x9fe8995d, 0x7923df43,
6020 0x82f57b47, 0xa4aaf640, 0xf7433849, 0xf8d248c7, 0x44967a41, 0xee623db8,
6021 0x9c487cd0, 0xc601f326, 0x77ac87fa, 0x9b7a0d25, 0x8d29c61e, 0x7f468aec,
6022 0x8aec6655, 0xff6f73c6, 0xc8d59151, 0xc6538bec, 0x4f9c1b4f, 0xbd8b8fc9,
6023 0xa87e9b1a, 0x183b60f9, 0x7fc5adef, 0x32622903, 0x3514deb8, 0xcc7cd147,
6024 0xe50d35d4, 0xf05768b6, 0x534fb87b, 0x9bfa3e80, 0xc607c777, 0x75c7bfa1,
6025 0x8677de53, 0x1ff7a6f4, 0x1ca0a69f, 0x26d8a894, 0x20bee73c, 0xc0617bf0,
6026 0x82f85ee9, 0xf25e5e7c, 0xca244337, 0x65cb85cf, 0x01fec7a4, 0xd928fb3b,
6027 0x6762bf07, 0x15c70d59, 0x7076cb3b, 0xeecec07c, 0x3762b8e2, 0x42a3fe95,
6028 0x1d0a4fde, 0x9077a94f, 0xe6ed93c7, 0x6e7abaa2, 0x7f7e4537, 0x4c6b76c7,
6029 0xfce27f3c, 0x19d32b5a, 0x95d3b412, 0x123577e4, 0x19c5b1fa, 0x76a579ca,
6030 0xa0e27e90, 0x7499fa3e, 0xbbf509a0, 0x10f940c8, 0x070d15c4, 0x59791cf1,
6031 0x07ef15bc, 0x9caee943, 0x7cc5c777, 0x7cf906b3, 0x8af1d6ab, 0x7269ef19,
6032 0x82afc8ba, 0x74bf90b6, 0xb8a3aabe, 0xb7d357aa, 0x965fed07, 0xf61af1d6,
6033 0x6c76d32b, 0xea4b029e, 0xe3b574d1, 0x943cd091, 0x5c43b257, 0xbb39fd5e,
6034 0x39527ce9, 0xe6577f2f, 0x5ea70323, 0x7025f28d, 0x7cde3939, 0x57b46de8,
6035 0xf2748efe, 0x03e45703, 0xa3478fcd, 0xe210f9dd, 0x5c407714, 0xbdaae1fc,
6036 0x14b50f74, 0xde011fef, 0x7f7829b9, 0xa62edffd, 0x0b6d8838, 0xbcf28e78,
6037 0xa50f1833, 0x2fb5ca0b, 0x24dc8f48, 0x9ba5dfc7, 0xeace9608, 0x061d2270,
6038 0x8b8045f0, 0x21ebf801, 0x667f4878, 0x1e6266f7, 0x08d61dfa, 0xc6ca3d01,
6039 0xbc534efa, 0xd0c3407a, 0xbf046c3f, 0x28e1f849, 0x1d532baa, 0xc718bf00,
6040 0x9bfa22fd, 0xca0ee8d2, 0x7587fceb, 0x60f0df74, 0xb82997cb, 0x8ba6bf7f,
6041 0x96d295f2, 0x9e31e397, 0x344b358d, 0x78dff83e, 0xdc3d8fba, 0xb6318f12,
6042 0xe54cbcf2, 0x94eb94cd, 0x28fed172, 0x5f45cbcf, 0x54bfae26, 0xf6c5c8e8,
6043 0xd453b458, 0x7111701f, 0x1328fb46, 0x2d60ddb8, 0x5089f922, 0x706745be,
6044 0x25f60bbb, 0x8f11ee97, 0xb15978f2, 0x605f6427, 0x79f1d7bc, 0x261fb70e,
6045 0x5e14fce5, 0x31bb462d, 0xa4d99d84, 0x41564dd8, 0x06644d79, 0x3ef2b75f,
6046 0x30f3cb8d, 0xd2be776a, 0x83969b9d, 0x7bf249ef, 0x7d2cf601, 0x1da13ed0,
6047 0xf23b2449, 0xf61e26a0, 0x60bcf255, 0x14af08dd, 0x802aaf2f, 0xfaad6cee,
6048 0x2fca029e, 0x19ee9b99, 0x8575d742, 0x7f39997e, 0xd2f3e44b, 0xbcfc3d92,
6049 0x9f8682f4, 0xf2bd832f, 0x3b5afda1, 0xf500aaa7, 0x72b8eeef, 0xdcb9e06d,
6050 0xb35fc6d5, 0x5b5f1833, 0x30905551, 0x6c979e84, 0x8a3ed1d8, 0x1d17e10d,
6051 0xd2f105d5, 0x7595cf95, 0xeb2bd05f, 0x1519a59c, 0x55a58f48, 0xae00a305,
6052 0xf4b9f88d, 0xd0befbe0, 0xdfa1f3a2, 0xf9d2fa06, 0x575f8de9, 0x5c3f9d04,
6053 0xe662bc6d, 0xe1c2f3a1, 0xcb0a1fd6, 0xcc69df04, 0x57e818a3, 0xe819e91d,
6054 0x2f7cc04d, 0xb4fbfeca, 0x9e78a04a, 0x871aad15, 0xac7301f9, 0x6b7e871a,
6055 0x0c0178b8, 0xdd1568e5, 0x8209ba49, 0x0eb0ae1e, 0xffa50f41, 0xbcfc191d,
6056 0xaf5945e1, 0x7d2fcf46, 0x9fb420e6, 0x19456c96, 0x5c28a8c0, 0x8945e623,
6057 0xda183c23, 0x7203be53, 0x036394ed, 0x5f7cab43, 0xbb522858, 0x586459ab,
6058 0x8d12caa7, 0x57d80c9e, 0xf54edb21, 0x7798f37b, 0xa9791506, 0x3d7f7ebb,
6059 0x4d7fcfb4, 0xd195bc9c, 0x37e50f7d, 0x330e9105, 0x5fb055c6, 0x4ef43f39,
6060 0x7e701859, 0x37f647b7, 0xfc814433, 0x14525f40, 0x5dced39d, 0x503cbe5a,
6061 0x10853b4e, 0x72fa79ba, 0xf5f1bf29, 0x6dd206e5, 0x15516bc9, 0xbcc80e74,
6062 0xcc049653, 0xaf0672f3, 0x696af89f, 0xb8979d06, 0xd27bf32e, 0x27dbf17c,
6063 0xd7588f31, 0x80af7906, 0x407ea7e3, 0x2f906675, 0x0dd09c62, 0xcc1ce9f9,
6064 0x66cc1df5, 0x61387b43, 0xae7be514, 0x7ac30203, 0xae8b6733, 0x9d9bef06,
6065 0x8c78ae9a, 0xbf34b673, 0xec3f45af, 0x569efc3a, 0x92abbcc2, 0x2637f5c9,
6066 0x05d7d215, 0x5bbf40ec, 0x01f59cde, 0x93f2b5da, 0x5cb0d4fc, 0x3fdd1efd,
6067 0xce14b9e2, 0x48d4da57, 0xcc658df7, 0xd65f7247, 0xf6ff9c10, 0x075d0e27,
6068 0xa76cb2f4, 0xd3ee7c14, 0x225fcf3c, 0xb72f0ab2, 0xce9f148b, 0x73a04c4d,
6069 0x38f7c1d8, 0xf7626d7d, 0xdb6e7843, 0x0558269b, 0xd237aa18, 0x26e309bd,
6070 0xc73f2677, 0x85f57ded, 0x7ce86b29, 0xeb0533c4, 0x73e57ba4, 0xec8fb9fc,
6071 0xeb018b50, 0xebcadb99, 0x59237a17, 0xbbe211d1, 0x23f20c63, 0x92ded52b,
6072 0xb6967181, 0xf1eb9def, 0xaf8e59de, 0x57b1f743, 0x253e6fbe, 0xbacae9c7,
6073 0xf32727e7, 0x21e618f3, 0xf3976a39, 0xda0a9b62, 0x4cd3ee03, 0x77528299,
6074 0x046befc7, 0x9c3e8f7e, 0x17bd617e, 0xbd623bd6, 0x72fdc217, 0x7bd6245d,
6075 0x5ca2fe21, 0x5ef58917, 0xbdeb1cf8, 0xeb926f10, 0x0bdeb122, 0x42f7ac71,
6076 0x8bae5478, 0xa54b853c, 0xbfd2eef8, 0x3edb9e61, 0xfc721f10, 0x3e084c74,
6077 0xe9ffb83a, 0x1f182118, 0x33ff502d, 0xcdfe9775, 0x1675839d, 0xf0dfd926,
6078 0x9ce50b3a, 0xb670b3ab, 0xb1f20779, 0x3c24c275, 0x69266747, 0xb74bea04,
6079 0x56ffe7cc, 0x1da02fdb, 0xe47d1160, 0x64c4e797, 0x78bb408f, 0xba62e4f2,
6080 0xd38feb87, 0x93bc3e91, 0x7ec3e8ee, 0x9e6f98ae, 0xeb06cc3f, 0x265a66e6,
6081 0xfc029a6f, 0xe4106998, 0x44fb7238, 0x059f72bb, 0xbadd99fc, 0xdb9a8a6a,
6082 0x994e130b, 0xc6ad962f, 0xe925d771, 0xaa1e6327, 0x1dfc734b, 0x5fe855c7,
6083 0x19ad7a30, 0x48d76fe7, 0xeabc601f, 0xf3cf13fe, 0xa501fa95, 0x33a927df,
6084 0xdef099f5, 0x26fa4b5c, 0x2819ebcc, 0x4dbc8a1f, 0x3e501acb, 0x6128aa6c,
6085 0x4933d923, 0x67d5fb8d, 0x92cefdf2, 0x4f80fdf8, 0x6063a92b, 0xcce45f7c,
6086 0xdb77cc38, 0x949fbe65, 0xe64a7ef9, 0xcdd1d63b, 0x3a3af351, 0x87475884,
6087 0x20ea10f0, 0xdd2fbfcc, 0x7149931e, 0xd20a5f72, 0x984ba95d, 0xedc67a87,
6088 0xf5d20a4f, 0x27c72c90, 0x99d3fb64, 0xefe24f66, 0x54acf8f1, 0x96e81fae,
6089 0x7d9473cf, 0xbe0def2a, 0xfb05e7cf, 0x6ffee12d, 0x5f645510, 0x5b38e543,
6090 0x788efb96, 0xbd4abde3, 0x3739c608, 0x261fdc88, 0x41dffaab, 0x6f1c93bb,
6091 0x90c23694, 0x78a3b3f9, 0x09bd36bf, 0xdb6f6c4d, 0xddce7437, 0x296190fb,
6092 0x30314fbf, 0x3da11efc, 0xe04d4271, 0xe51fe979, 0x908fc079, 0x9a2cba5e,
6093 0x3923f61f, 0x423f01c6, 0x144e66f9, 0x9bf923dd, 0xa4fca2bf, 0x09aa75b7,
6094 0xe1dfd4e5, 0x715fa031, 0xc4ffe3fd, 0xb7f0bfa3, 0x6cf5417e, 0xa4bf6ffe,
6095 0x722db73a, 0xcdebe1bd, 0x87589d72, 0xbde7c464, 0x60159f85, 0x1c32adbf,
6096 0x3cfc23b4, 0x686f814f, 0x681de66c, 0x51509ecf, 0x8dd8a2fe, 0x98597d50,
6097 0xf78e5239, 0x676831ec, 0xc4ec5f40, 0x597d01b7, 0xc1798316, 0x12917da0,
6098 0x132ea87e, 0xcd598bed, 0xb4420bed, 0xb733662f, 0x7da3882f, 0x05f68841,
6099 0x417da39f, 0xe20bed1c, 0x47105f68, 0xed1082fb, 0xebff3e0b, 0xd3a75e52,
6100 0x3f29810b, 0x5c5035c7, 0x7f8ebebf, 0x8dbeb27f, 0xafaddbdf, 0xac0ea816,
6101 0x94dfe607, 0x509d4439, 0xe4275c93, 0xa2f741dd, 0x15a2c3ae, 0xd6017859,
6102 0x6dcf09bd, 0xd0277d35, 0x051ab82f, 0xcf84956b, 0xb63ad297, 0x60fd4eb4,
6103 0xd3af3e39, 0x2fe85558, 0xa3c72f5a, 0xad692bdf, 0x2735ff23, 0xbfcb4da1,
6104 0x9e181197, 0x71d12f1f, 0xe11728fd, 0x3fba24e9, 0xae5ffb26, 0xad73a0eb,
6105 0x0a417ad2, 0x35c08efc, 0x7fc512fd, 0xf2b9fdca, 0x57b94bdd, 0xca0ead2f,
6106 0x6ebc6c9f, 0x4aff718b, 0x9e406579, 0xc3277cab, 0x74d56fc4, 0xc08afe3f,
6107 0xd7ab8562, 0x36b49573, 0xaffac66e, 0xb4767bd0, 0x16d75424, 0x44febf72,
6108 0x95d75ca6, 0x6f30f2c7, 0xf5627c2e, 0x5f30c381, 0xe51d76ff, 0x774f609d,
6109 0x409efea1, 0x9cba0439, 0xb9d3d368, 0xb23be7db, 0xde1f1046, 0xf6489914,
6110 0xb7d90c72, 0xf2811a75, 0x3597b031, 0xc2ecdef8, 0xceaec8bb, 0xfc8abb06,
6111 0x93eee454, 0xca2d7b54, 0x1209bae7, 0x1d7cb9f9, 0x93c697bb, 0x9200c5eb,
6112 0x146fe5de, 0x57c02a3c, 0x2f7d2b31, 0x86c812b4, 0xc6af50f1, 0x75d608f0,
6113 0xaebc64ad, 0x75a39143, 0x8eef943b, 0x577d10c6, 0xd95cf4c8, 0xb06fc7fa,
6114 0x1d2ee36e, 0x56490f3f, 0xe4803af1, 0xe7bebcad, 0xf5e0e66e, 0x8b4d9872,
6115 0xdabd2f94, 0x511dcf05, 0x79f85263, 0xe380948f, 0xa1a53aaf, 0x84fce33a,
6116 0x8a0e9905, 0xfd50e64f, 0x43bbe086, 0x1f9afefc, 0xeb83878a, 0xec684e37,
6117 0x3b573df4, 0x73d925ca, 0x9553c107, 0xbb150445, 0xf63fd4ad, 0x88dcbdb6,
6118 0x0cbbe7f3, 0x62b7a456, 0x83a8ae07, 0xa950e48c, 0x100b1c83, 0xc0cc0aeb,
6119 0xda0c5363, 0x44ec8967, 0xb273aab2, 0x1bfffb84, 0x3f200eff, 0xe30f2da1,
6120 0xfc7974a6, 0x43fd92d3, 0x9a2d9fe4, 0xbc3df1b9, 0xf40eda4f, 0x080dc02c,
6121 0x6d7b2f18, 0x6dbfc622, 0x1a46a982, 0x78ee8eca, 0x5c97eb08, 0x7184c166,
6122 0xf6e44159, 0xbf1878fc, 0x8ad52d20, 0xccd5dc76, 0x403f2de3, 0x3debf7ce,
6123 0x55dfc0a2, 0xce9c63c7, 0xea9596f9, 0x351ccee8, 0xacbe7cf8, 0x5fadbd4f,
6124 0xabe3faf1, 0x38b563c7, 0xade99bbe, 0xc8f8f275, 0x8cd7f9f7, 0x914cb8a5,
6125 0x8486fe9b, 0xef9b941a, 0x7cbbff65, 0xcc1a7bf9, 0x1cd33b03, 0xaff38dff,
6126 0xa1e97d58, 0xd0e7da78, 0xd3a9507e, 0x4a83f50f, 0xabfff37c, 0xcaedff3e,
6127 0x54ef820a, 0x51d8206e, 0x51f6a6e9, 0x735cfc59, 0xfc0ab8b8, 0x10d65c43,
6128 0xbf4294f1, 0xe4aae221, 0xae3ca9ac, 0x89473cc2, 0xa388aeab, 0x0155df40,
6129 0x75bb3efa, 0x608f9de4, 0x6b53b3dc, 0xeb0090c5, 0xc81bd7a8, 0x4d64643e,
6130 0x529e2a1d, 0xf8a069e8, 0x27e99fab, 0x2cb3fce1, 0x1fbc6ae9, 0x0425989f,
6131 0x3fa80be5, 0x1fd46fb8, 0xea3fa884, 0x39e7b880, 0x14f6a82d, 0x29b82f1e,
6132 0xbf13d05e, 0x5d815737, 0x662efc01, 0x3d2bb20a, 0x31857621, 0x1d70affb,
6133 0x9d795a6b, 0x3a5f5297, 0x93d7c00b, 0x5e33b086, 0x46c6676e, 0x3ce1f77a,
6134 0x54919d63, 0xc3427caf, 0x16c4eee5, 0x9ab82f5e, 0x8ff7f9d9, 0x689bda57,
6135 0xb15defa4, 0x01fc9f7d, 0xa8f5dffa, 0xcd9ee281, 0xfda66b49, 0xf8cdec4f,
6136 0x7f0f4e2c, 0xe7de6fa5, 0x22731f20, 0x905cf7f9, 0xee2859bb, 0x7e924555,
6137 0x8ed97e40, 0x6bac57df, 0x8ed0f211, 0x77d9d1cf, 0x6a9d3ae1, 0x27167ebe,
6138 0x3baa27df, 0xbf42f78a, 0x2b64f8ce, 0x1263cfe6, 0xffac308f, 0xe61577ca,
6139 0x64ecbda0, 0xbf7be9db, 0x5dc73a8d, 0x39c5e7c8, 0x7b9d0215, 0x5897faca,
6140 0x95b35518, 0x153591f8, 0x2708bef9, 0xe6e473a3, 0x2e8f98c5, 0xf1c10a8a,
6141 0x8dce8b1e, 0x6c78e55f, 0xd2827b48, 0x1cc9e32e, 0x2f356777, 0xd2e573c6,
6142 0xf3e9bd7a, 0x91cffaa0, 0x39abb841, 0x6079f4c9, 0x03fe2a7d, 0x822daecf,
6143 0x93dc059a, 0x078e0837, 0x85e53f70, 0x2e39f917, 0x5abf23eb, 0x7d112595,
6144 0x7ccebd47, 0x737dff28, 0x902e748d, 0x87915b10, 0x472c09e7, 0x52fd8a9a,
6145 0x17147d34, 0x96ab7ef6, 0x8be8b3bf, 0xef202dbe, 0x7f95be7f, 0xcfca117f,
6146 0x7b970b3c, 0x0db0d997, 0x8c4ce6f9, 0x7ad82088, 0xa616e289, 0xdef19bb6,
6147 0x3a0af214, 0x3f7d08b7, 0xb7efc2dd, 0x656b3753, 0x90ff813a, 0x8e337ae4,
6148 0xc674d9bb, 0x948befaa, 0x266ccae9, 0x866d3ff8, 0xfcffc64a, 0x0113e638,
6149 0x7fd86dfd, 0x6b5f9db0, 0xf77bef2b, 0x26f8fbbe, 0xca1f3cb3, 0xf1461ad7,
6150 0xa0f7e873, 0x06625a9f, 0x2e5033ea, 0x53d38b9e, 0xf7583f9e, 0x6ba0ebcf,
6151 0x7f3d72f5, 0xf83fbd68, 0x8ae7f43b, 0x725f7b9f, 0x52bf1d50, 0xf9d4aff7,
6152 0xcd2f3127, 0xe027b4a7, 0xda88baed, 0x3847a1db, 0x2193f303, 0x659376e8,
6153 0x91647fe6, 0x17d9b8de, 0xfee7c1ea, 0x810de8a8, 0xe486727c, 0x66593737,
6154 0xfbca7bd1, 0xb1661be5, 0x26e3262f, 0xaccc38e5, 0x14e7ff22, 0xd9021bd9,
6155 0xa28f5e11, 0xec1a77bc, 0x9ff7ce3c, 0x7e11f760, 0x0bfef608, 0xc19fe7a0,
6156 0x08fc21de, 0xff3e1dec, 0xc21dec04, 0xf803f02e, 0x03f053fc, 0x61dc9708,
6157 0xe57a829c, 0x5f62ae6a, 0x3b3dd704, 0xd3bfe302, 0x97968733, 0x9e2a598b,
6158 0xdd0ea5bf, 0xe9e596ae, 0x6f9c8df4, 0x4f3377bd, 0xdfc92a4d, 0x86178c26,
6159 0xd7b7eefb, 0x5afbedc8, 0x37bc1cf9, 0xb2e7e389, 0x473cfc34, 0xf7c69ec5,
6160 0x3af066d7, 0x2b8ec539, 0x1fc82af9, 0x63acaf8d, 0x29d79c9c, 0x55663cfd,
6161 0x0a48f7d0, 0xfde1639c, 0x5f313e48, 0x0d4c7947, 0x44a74f90, 0x172a19f2,
6162 0x1d385a9f, 0x772e3acc, 0xa09768c9, 0x9e82727f, 0xe361c6e2, 0x51ef90b0,
6163 0x394f90ae, 0x32c64b1e, 0xf3e1988f, 0xf7aca363, 0x7e3f3a3f, 0x943150d8,
6164 0x3ff998fd, 0x3e80ffdd, 0x8affef06, 0x8e876b7d, 0xf7db873f, 0xca2bbd40,
6165 0xc1f610cf, 0xb81f603a, 0xb164dcfc, 0x1d4cb78d, 0x05483bfe, 0xebe0cdae,
6166 0x6a83e456, 0xc5ee3094, 0xee0fa57d, 0x91fd6067, 0xcb5bfb21, 0x94225ee8,
6167 0x13df018f, 0x05fafb29, 0x1ba147ae, 0xa38a3e58, 0xa81994c7, 0xc590fbce,
6168 0x4769efc4, 0x0762b97d, 0xf645feb4, 0xf1507f13, 0x6ec51a7a, 0xc4173c0f,
6169 0x82730b95, 0x513339ec, 0xfd23ad9c, 0x7bbc41f2, 0x4f7830d0, 0xb7f7eca9,
6170 0xcbf63eb2, 0x6fffb5f9, 0x8ff65f3c, 0x73dfa3ee, 0xefcd3ff0, 0x9bc460d1,
6171 0x6eee0eb1, 0xcc253bf9, 0x9e5ad5af, 0xcf21ab37, 0x7d2f7bf6, 0xae01f782,
6172 0xaa3c4467, 0x9733e262, 0xd3fc5097, 0x7e6131a6, 0xc7e9f1be, 0x9dbca24f,
6173 0x7424126d, 0xd826fed9, 0x3ba7e636, 0xf43d1e8d, 0xe7e2682f, 0x45eb6b27,
6174 0xfcff048f, 0x696efe42, 0xfa1a33f6, 0x234d699e, 0xfe3977af, 0x6bca7af4,
6175 0xcf207acf, 0xc40b7186, 0xbcf1da07, 0xfe39e4be, 0xfb2512bb, 0x1efc5adc,
6176 0xa05aa4af, 0x97c9537c, 0xaf75e4cb, 0x6c7909d9, 0x30483dd0, 0x14bccc5e,
6177 0x06d4955f, 0x086b2f3f, 0xb5ef7fce, 0x94d77c0c, 0xf9c8ebc7, 0x3f62acbd,
6178 0xdcab8caf, 0xfac1a7c4, 0xe3c6bfeb, 0x76d8be79, 0x0353e539, 0xf8ca17c7,
6179 0xca2fc019, 0xfacaf6e7, 0x62e8fc95, 0x85e29b12, 0x2e313afd, 0x50efe495,
6180 0xc8aedf81, 0x1f485bae, 0x8c268a8f, 0x8b34b6b3, 0x7967a46e, 0x7d377eab,
6181 0xf4e78537, 0x3df3a446, 0xc26ff7e4, 0x273c267b, 0x83b67c84, 0xce83a6e4,
6182 0x6fad99e5, 0xb697dd0d, 0x4fe84de8, 0x683f479d, 0xfd06efc7, 0x57860587,
6183 0x7cefcaf8, 0xd78679ac, 0xcddfc199, 0x229afdf8, 0x5f006217, 0x436bef91,
6184 0xc33e2af8, 0x8d35f3f3, 0xdedf2823, 0xf568b4f8, 0x39785ca1, 0x17be157f,
6185 0x3ce8db88, 0x7c48f805, 0xdd4cfd9e, 0x07289193, 0x05fdf8fb, 0xfdf101c8,
6186 0x77ce2eec, 0xc443db6d, 0x2cb57f77, 0xf7fc2d07, 0xf8ea4a49, 0x17e81079,
6187 0xf1abc9f9, 0x5f7c6aff, 0x7c83db20, 0x3889c671, 0xe5ef778c, 0xe988adf3,
6188 0x9a07bf2e, 0x20bb993e, 0x7975f515, 0x26c6eee1, 0x07891980, 0xce621999,
6189 0x51db3a53, 0x5cb9e04b, 0x79d79e9b, 0xca045103, 0x4bfae433, 0x53dd4ce9,
6190 0x5e47af68, 0xfe31f143, 0xf79c0445, 0x60cf3f00, 0xb23bd09e, 0xd8cbc0fb,
6191 0x7e8e946f, 0x55bca58f, 0xa2e5d3e7, 0x9bf2e45f, 0x715bedaf, 0xafddc60f,
6192 0x433ee8ea, 0x45dff1b0, 0xe3fd6d28, 0xc84f7887, 0x416df29a, 0xff209bbf,
6193 0xfe2941ae, 0x37b602ae, 0xe8067a68, 0x3fa6ed80, 0x165d7bd1, 0x9e92875e,
6194 0x71848370, 0xcc65c6ec, 0x943e9911, 0xe764679d, 0x8729ef95, 0x3986c38d,
6195 0x2fe2506f, 0x12331ee6, 0x7df94cf5, 0xad0ec505, 0x3c5bbf95, 0x7529df71,
6196 0x96afd22c, 0x714c8eff, 0x389fd82b, 0x7922df3a, 0x38aee73b, 0xbf9782a2,
6197 0x468ab944, 0x0e68fab9, 0xc7db2ff6, 0x3c0683fb, 0xdf871919, 0x4f286b29,
6198 0x7937d01b, 0xa3df867c, 0x05f3bb40, 0x0ea6c581, 0xab6a2f61, 0x421e8f37,
6199 0x2e214a6e, 0xca8745c3, 0xb829b38f, 0x768377df, 0xf8f7c264, 0x9726567d,
6200 0x662cf72f, 0x0d5ffdc1, 0x40d8f92a, 0x947e067e, 0x19e660ea, 0xc972df29,
6201 0xd5ced2e7, 0x51273a26, 0xed538dfc, 0xf299b33d, 0x43972332, 0x63dfa335,
6202 0xb68d54e9, 0xef380d6e, 0x4e979ce8, 0x6fc59fdf, 0xdc70faf4, 0xb58205be,
6203 0x44e69a06, 0x5f2efcf1, 0x0bdb2f65, 0xb8a86fed, 0xf30e7ddf, 0x17fd1137,
6204 0xff419397, 0x93cfcfc6, 0x7f3c8d0b, 0x9adca8f3, 0xa61df489, 0xdd94eb1b,
6205 0x2bd52d76, 0x1d291ced, 0x677c0268, 0xefd90e71, 0x73f1df23, 0x5a65bef4,
6206 0xf33bf3f2, 0xae51cbec, 0x4f1b2e77, 0xd208afed, 0xe33f7863, 0x7da48e2e,
6207 0xcfc85cec, 0x4c2e771b, 0x5967f6a4, 0xdf1a955f, 0xd9fbe6ab, 0x3a04d8f9,
6208 0x39d38dff, 0xbef1b372, 0xd8c7be58, 0xc24b6a99, 0x0527d37a, 0x71bbb2fb,
6209 0x1a0609bc, 0xe24590ef, 0xc6cb12f7, 0xe907b63f, 0x8a9a4634, 0x7e0fdb76,
6210 0x7ff00def, 0x4dd86c7f, 0xf71732f5, 0xc705b99f, 0xe4057d2f, 0x37f7c60f,
6211 0xebbe8318, 0x66efbe57, 0xc5b4df6a, 0xb0bf40c6, 0xbcb5d791, 0xeaf6e464,
6212 0x3373cea0, 0xe4725fbc, 0xebb45cb3, 0xdafb07fe, 0xdaee3193, 0x243af02f,
6213 0xde2e5777, 0x87a89647, 0xce6faf8e, 0x4f4bf1e6, 0x8c52d44b, 0x63fa84e7,
6214 0xe252df54, 0xe7435dbd, 0xd9bf7254, 0x866e3cd9, 0xed1f747e, 0xdfc827de,
6215 0x05a6f8bb, 0x752b5bde, 0xb8fb3dcd, 0x6b34951c, 0x92e47be8, 0x51ff46fa,
6216 0x59d43fc4, 0xf55d7c51, 0x783ee897, 0xe8074bf6, 0x3fef02de, 0x473a08de,
6217 0x3b39dfe6, 0xaae63b65, 0x395ec917, 0x77f9ca9b, 0x19e2f55f, 0xd28fbdc2,
6218 0xf15d34ef, 0x27731d5d, 0x5f4912ab, 0x29e6b193, 0xa5f4bdb4, 0x206e23b6,
6219 0xbda1e961, 0x2ee7e8d1, 0x2345d474, 0x55dc61dd, 0x5e7c11da, 0x2b883dfc,
6220 0x7d05b5c7, 0x6ef2e69f, 0x02ebc4b9, 0x845fc8bb, 0xff80bff6, 0x6f7f3f00,
6221 0xd91dfcb6, 0xf25aecb5, 0x14b1f5ff, 0xa6fac157, 0x13b77e05, 0x0f4bffea,
6222 0x0dde7e5c, 0xbb073ded, 0x96f5c79f, 0xd515f77d, 0xf557b123, 0xdae6b754,
6223 0x73f93eff, 0xcd7fbde5, 0x7fa871e6, 0x583ddedf, 0x2fffea97, 0xf347159d,
6224 0x22997db7, 0xe36839e1, 0xf10f7437, 0xfa7cb69b, 0x8737e6de, 0xd0fc2767,
6225 0xb7281177, 0x75c0cc9e, 0x92bf8879, 0xac503bfc, 0xfc218655, 0x3c74de3a,
6226 0x1179d705, 0xba754df8, 0x72f73f12, 0xbee9cb7a, 0x8007f101, 0x8786cebe,
6227 0xb8ffa12f, 0x4d9cff1a, 0x61bd6f8b, 0x2b43d90a, 0xf58b95aa, 0xe87ffdd1,
6228 0xfb7c037b, 0xc4e3e04f, 0x86bfc11f, 0x70ff342d, 0xff88bbfc, 0x081d3e00,
6229 0xa6e5dfe1, 0xeb1dffbb, 0x6c535968, 0x8128f7d0, 0x08fdf374, 0x7c0915ba,
6230 0xdb66dffc, 0xf4bed19a, 0x0f617c1c, 0xdf2309d6, 0x2eb0966e, 0x330a72ed,
6231 0x7d30f7e2, 0x697f282b, 0xaed099d3, 0x407db495, 0xeb97e3fa, 0x80cfe029,
6232 0x06cfce7e, 0x2fc83afe, 0x55d9b6c9, 0xa2e9f46b, 0xf4efe907, 0xa2942c2c,
6233 0x7a19f9e9, 0x8c72e1ee, 0x2ddfc3f4, 0xdd8e7a73, 0x97c10c26, 0x9e34ecde,
6234 0xd1467927, 0xff6bcbbe, 0x00c0e3c2, 0x91d3097e, 0x6e28674f, 0x0a4f8e1c,
6235 0xeff24c1d, 0xadf00d88, 0x685feb96, 0x87f0177f, 0x7e653fee, 0xf7f0ff21,
6236 0xceb85cd4, 0x20cf8e68, 0x0d80f85c, 0xd5fc0f61, 0xfce3ca3a, 0x83c9f721,
6237 0xd79079fc, 0xa9ea855d, 0xf4e1cfbc, 0xabd3d143, 0xd2a7ffad, 0x52d92fe7,
6238 0x7428bc90, 0x6876f9ea, 0xcf1c6e3b, 0x9f67fef5, 0x3504da3f, 0x7f3a0f8b,
6239 0xf3c78c34, 0x4133a6c7, 0x7eca8fe7, 0xda73e47b, 0xf922fd9e, 0xeff2cdc7,
6240 0x0bda84ac, 0xd0983be5, 0xd7938ef5, 0x7f7f94eb, 0xd1a0e7a1, 0x7a718063,
6241 0x79216f5e, 0xd19c3676, 0x7b6a79e2, 0x9efa21fd, 0xf41fd14e, 0xf5809e13,
6242 0x2c78bcf7, 0xce36ec97, 0x275f0433, 0x33cf978c, 0xc79e875b, 0x682970d5,
6243 0x57b7529e, 0x57ab754b, 0xda82ef99, 0x778e3b76, 0x7eff83a1, 0xd0ef05e1,
6244 0xf1a6a9e7, 0x615cf91a, 0x2fe0873b, 0xbcfe01ed, 0x1b4db053, 0xc30c2a3f,
6245 0x30c30c30, 0x0c30c30c, 0xc30c30c3, 0x30c30c30, 0x0c30c30c, 0xc30c30c3,
6246 0x30c30c30, 0x0c30c30c, 0xc30c30c3, 0x30c30c30, 0x0c30c30c, 0xc30c30c3,
6247 0x30c30c30, 0x0c30c30c, 0xc30c30c3, 0x30c30c30, 0xc1b7ff0c, 0x8dca0bff,
6248 0x8000e737, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x20000131,
6249 0x22b0030c, 0xb0131302, 0x14e7ff1b, 0x93c9084d, 0x26ebaf39, 0x6db6db63,
6250 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
6251 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xf6db6db6, 0x10192fc7,
6252 0x8000dcb1, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x20000131,
6253 0x22b0030c, 0xb0131302, 0x14e7ff1b, 0x93c9084d, 0x26ebaf39, 0x6db6db63,
6254 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
6255 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xf6db6db6, 0x10192fc7,
6256 0x8000dcb1, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x20000131,
6257 0x22b0030c, 0xb0131302, 0x14e7ff1b, 0x93c9084d, 0x26ebaf39, 0x6db6db63,
6258 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
6259 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xf6db6db6, 0x10192fc7,
6260 0x8000dcb1, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x20000131,
6261 0x22b0030c, 0xb0131302, 0x14e7ff1b, 0x93c9084d, 0x26ebaf39, 0x6db6db63,
6262 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
6263 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xf6db6db6, 0x10192fc7,
6264 0x8000dcb1, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x20000131,
6265 0x22b0030c, 0xb0131302, 0x14e7ff1b, 0x93c9084d, 0x26ebaf39, 0x6db6db63,
6266 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
6267 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xf6db6db6, 0x10192fc7,
6268 0x8000dcb1, 0x00008000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
6269 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 2812 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
6270 0xffffffff, 0x00100000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff,
6271 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 2813 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
6272 0xffffffff, 0xffffffff, 0x00100000, 0x00000000, 0xfffffff3, 0x314fffff, 2814 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
6273 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 2815 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
6274 0xfffffff1, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 2816 0xffffffff, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
6275 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 2817 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
6276 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 2818 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
6277 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 2819 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
6278 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 2820 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
6279 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 2821 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8,
6280 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 2822 0x00000000, 0x00003500, 0x00001000, 0x00002080, 0x00003100, 0x00004180,
6281 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 2823 0x00005200, 0x00006280, 0x00007300, 0x00008380, 0x00009400, 0x0000a480,
6282 0xfffffff5, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 2824 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, 0x0000f700, 0x00010780,
6283 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 2825 0x00011800, 0x00012880, 0x00013900, 0x00014980, 0x00015a00, 0x00016a80,
6284 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 2826 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80,
6285 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 2827 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, 0x00010001, 0x00000604,
6286 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 2828 0xccccccc5, 0xffffffff, 0xffffffff, 0xcccc0201, 0xcccccccc, 0xcccc0201,
6287 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 2829 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201,
6288 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 2830 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201,
6289 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 2831 0xcccccccc, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000,
6290 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 2832 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
6291 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 2833 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
6292 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 2834 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
6293 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 2835 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
6294 0xfffffff3, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 2836 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000,
6295 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 2837 0x00007ff8, 0x00000000, 0x00003500, 0x00100000, 0x00000000, 0x00100000,
6296 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 2838 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6297 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 2839 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6298 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 2840 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6299 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 2841 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6300 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 2842 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6301 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 2843 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6302 0xffffff97, 0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 2844 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6303 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 2845 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6304 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 2846 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6305 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 2847 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6306 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 2848 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6307 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 2849 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6308 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 2850 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6309 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 2851 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6310 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 2852 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6311 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 2853 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6312 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 2854 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6313 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 2855 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6314 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 2856 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6315 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 2857 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6316 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 2858 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
6317 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 2859 0x00000000, 0x0000ffff, 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c,
6318 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 2860 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
6319 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 2861 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
6320 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 2862 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
6321 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 2863 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
6322 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 2864 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
6323 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 2865 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
6324 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 2866 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
6325 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 2867 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c,
6326 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 2868 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
6327 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 2869 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
6328 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 2870 0xcdcdcdcd, 0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
6329 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 2871 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c,
6330 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 2872 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
6331 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 2873 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
6332 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 2874 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
6333 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 2875 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
6334 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 2876 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
6335 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 2877 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
6336 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 2878 0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
6337 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 2879 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c,
6338 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 2880 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3,
6339 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 2881 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
6340 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 2882 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
6341 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 2883 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
6342 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 2884 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
6343 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 2885 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
6344 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 2886 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
6345 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 2887 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c,
6346 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 2888 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97,
6347 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 2889 0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c,
6348 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 2890 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
6349 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 2891 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c,
6350 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 2892 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
6351 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 2893 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
6352 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 2894 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
6353 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 2895 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
6354 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 2896 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
6355 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 2897 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
6356 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 2898 0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
6357 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 2899 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c,
6358 0x000a0000, 0x000700a0, 0x00028110, 0x000b8138, 0x000201f0, 0x00010210, 2900 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
6359 0x000f0220, 0x00010310, 0x00080000, 0x00080080, 0x00028100, 0x000b8128, 2901 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
6360 0x000201e0, 0x00010200, 0x00070210, 0x00020280, 0x000f0000, 0x000800f0, 2902 0xcdcdcdcd, 0xfffffff3, 0x31afffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
6361 0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000b8280, 0x00080338, 2903 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c,
6362 0x00100000, 0x00080100, 0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 2904 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
6363 0x000e8298, 0x00080380, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 2905 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
6364 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 2906 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
6365 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000 2907 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
2908 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
2909 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
2910 0xcdcdcdcd, 0xffffff97, 0x058fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
2911 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c,
2912 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff,
2913 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c,
2914 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2915 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2916 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff,
2917 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c,
2918 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2919 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2920 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff,
2921 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c,
2922 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2923 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2924 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff,
2925 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c,
2926 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2927 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2928 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff,
2929 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c,
2930 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2931 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2932 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff,
2933 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c,
2934 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2935 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2936 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff,
2937 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c,
2938 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2939 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2940 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff,
2941 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c,
2942 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2943 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2944 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000,
2945 0x00070100, 0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000f0280,
2946 0x00010370, 0x00080000, 0x00080080, 0x00028100, 0x000b8128, 0x000201e0,
2947 0x00010200, 0x00070210, 0x00020280, 0x000f0000, 0x000800f0, 0x00028170,
2948 0x000b8198, 0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000,
2949 0x00080100, 0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298,
2950 0x00080380, 0x000d0000, 0x000000d0, 0x000280d0, 0x000b80f8, 0x000201b0,
2951 0x000101d0, 0x000c81e0, 0x000002a8, 0xcccccccc, 0xcccccccc, 0xcccccccc,
2952 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc,
2953 0x00002000
2954};
2955
2956static const u32 tsem_int_table_data_e1[] = {
2957 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x19d9b38a, 0x22717618,
2958 0xa70143f8, 0xa4303332, 0x10267103, 0x97e204af, 0xaf0c0c8c, 0x2fd78918,
2959 0xcf608621, 0x38606610, 0x4206c402, 0x22450c0c, 0xa07af108, 0xfe407b9a,
2960 0xb698a842, 0x76c30328, 0x3bf781d1, 0x34957035, 0x24a458a6, 0x458d5d82,
2961 0xa0d7191e, 0x4494efc9, 0xd012d7e5, 0x4538d03f, 0x513f9509, 0x547f4201,
2962 0x342fa684, 0xf95049f9, 0xa57f5039, 0x77376129, 0x001e542e, 0x61aa8a92,
2963 0x00000360
2964};
2965
2966static const u32 tsem_pram_data_e1[] = {
2967 0x00088b1f, 0x00000000, 0x7dedff00, 0xd554780b, 0x733ef0b5, 0x49999cce,
2968 0x204e4cce, 0x30840909, 0x43511879, 0x7c061e1c, 0x201276f4, 0x06bf2ae5,
2969 0x0ea2a17c, 0x2de42108, 0xebf8fea5, 0x092132fd, 0xf636c544, 0xda2f45a2,
2970 0x05a855e1, 0xa180d03b, 0x4a00ee05, 0x7836daa1, 0xf5ab15bd, 0x62a2968e,
2971 0x96ad2248, 0xbfcb17fe, 0x24fbdad6, 0x00664e73, 0xbbf7bdcb, 0x9fa7efd7,
2972 0xece7d9dd, 0xebdaf7b3, 0x7b5ad7b5, 0x5d8a3ded, 0x19d7ea62, 0xa0ff873b,
2973 0xc631b3ec, 0x9f2c19ae, 0x23a57cc8, 0x6ad8cbd7, 0x3127d43b, 0x0f623c16,
2974 0x5b18926d, 0xb59fda32, 0x71ca0d30, 0xbc20be69, 0xebe16767, 0xc654c612,
2975 0x9b4aadff, 0xe8f2c994, 0xf073b9f9, 0xf30f81dc, 0x58564b19, 0x63026530,
2976 0xafcc6c2b, 0x8fba830f, 0xfc9c0fb1, 0x7ff8739b, 0xf61b24c1, 0xbf874233,
2977 0xaf3edfa1, 0x814f682d, 0xedcdb37e, 0x1215494e, 0xd5db1993, 0x140bd2c4,
2978 0x9c9abac6, 0x49b4fe54, 0x60282f4f, 0x26534f6c, 0x7935f7d5, 0x8d348ca9,
2979 0x9a07e7a5, 0xb34f547c, 0xf7e3d7f5, 0x2b7c8e23, 0xce0d1595, 0x68ae5adf,
2980 0x060b7182, 0x64cc7feb, 0xf9e00541, 0xafeec2a3, 0x5f9aef80, 0x8512989f,
2981 0x802c99f2, 0xf7e86536, 0x45fb2ecf, 0x8ce1b4fe, 0x387c3d65, 0x6844da7f,
2982 0xe139b127, 0x87459c22, 0xe25c6b34, 0x77b19f71, 0xcdc032a4, 0x6991802d,
2983 0xb9b58c99, 0x4f2e6ffa, 0x44f5cc65, 0x0b9a7fb6, 0x5d0cdde6, 0x2eec648c,
2984 0xde0c1056, 0xf81ffd00, 0xe80525b8, 0x614976a1, 0x4b26cd78, 0xd012cd15,
2985 0x7ccedd8b, 0xa538709b, 0xd41479a2, 0xde60eefb, 0xe383bdc7, 0x9880c5dc,
2986 0x46ccd8e9, 0x32a864e5, 0xa5dd87e8, 0xe2e53686, 0x15c5fd87, 0x2fb712e3,
2987 0xd517f839, 0xf6f1a6eb, 0x078d328f, 0x7f13b9df, 0xcbe07597, 0xaef7d77d,
2988 0x78842332, 0xe11f9853, 0xc657753b, 0xde25c7ba, 0x7d8f163e, 0xc70aab2a,
2989 0x8e1567a1, 0x66dcfc0b, 0x367b74e7, 0xb18d4a17, 0x16663835, 0x9c62b563,
2990 0x03d95a29, 0x3000b258, 0xb58cb5e7, 0xdda0bd20, 0x3abf6894, 0xdf4ae00f,
2991 0x852a4b33, 0x0af1fa7a, 0xf2115e69, 0x10cf41a1, 0xb1259ff5, 0x9ef81d8a,
2992 0x70ca92cd, 0xe71f3b1c, 0x8b50fe86, 0xe86ee007, 0xec9eddca, 0x6194fde5,
2993 0x48553fbb, 0x3858b5f3, 0x7a4fd4bd, 0xdf038c17, 0x38c0f7a7, 0xa56b3ef0,
2994 0xfe69bac4, 0xe1a614de, 0x32c67e78, 0x70a6a440, 0xa8d99099, 0x7867e424,
2995 0xfc8165ae, 0x3f2e3364, 0x8be635a7, 0x9f737e00, 0xd0d47cd4, 0x783579ab,
2996 0x69c85a3f, 0x266aa076, 0x01b630f3, 0x530593d0, 0x7ca8dd1e, 0xb3918d10,
2997 0xcda37331, 0x9663fa28, 0x997b9f99, 0x9cf286d7, 0xcf3f341b, 0xbfd7376f,
2998 0x2769dccd, 0xdc3f82ae, 0x8e4e7dcc, 0xc0e38f33, 0x12cf00d4, 0x6fc0ef21,
2999 0xadbf2c6a, 0x5a19626d, 0x91396241, 0x5dce1c96, 0xb7687a89, 0xf7c073e4,
3000 0x907b602f, 0x6ef890ef, 0x05d7a8bd, 0x0d5d8555, 0x1e282025, 0x958afc7f,
3001 0x1fba406e, 0x101b6567, 0xbf4a0dff, 0x0d7c03aa, 0xa43faa8d, 0x17bf6d0d,
3002 0xd7db1118, 0x4e03be2b, 0x99bfbf18, 0xf8c3d6f9, 0x197aec4b, 0xec3c97d6,
3003 0xd798bd25, 0x7e472d1e, 0xea05d31d, 0xfbf0772a, 0x2767808b, 0xecf001c2,
3004 0x97f4e3e4, 0xdfedfea3, 0xb9f5b12b, 0x77ef0e38, 0x165ceec9, 0xe70c4dcc,
3005 0xfc4ecc73, 0xbc0b40b4, 0x267ee582, 0x02c62729, 0x83cc3d9a, 0xcaa968f4,
3006 0x54394efb, 0xe9f7c69f, 0xf9ccf583, 0x00033233, 0x6618d657, 0xb3a557a2,
3007 0x7af50731, 0x1cb84575, 0x25c3e2f9, 0x12c0acaf, 0x00ae9cf0, 0x2a388fbe,
3008 0xea7ec75e, 0xa21636e6, 0xe870edc8, 0x7b1afe34, 0x7237d647, 0x1fa50f11,
3009 0xd06fc02b, 0x1865306d, 0xff4595f2, 0xc60fbfc3, 0x989cba8a, 0x172a17ee,
3010 0xe20a3f60, 0xf59fcb8d, 0x0f4207fd, 0xf8261e81, 0x957ecbbc, 0xb63c305f,
3011 0xc17e7afe, 0x09500144, 0x13f0cbc1, 0x4552a2c6, 0x663dbd1c, 0xa561e977,
3012 0xff3c3138, 0x7404f3d9, 0x001a7cd2, 0x7527c8b7, 0x1cb4356e, 0xa7753df0,
3013 0xe075f23d, 0x5275ba93, 0xdb7501c8, 0xefbd173e, 0x11ebcb5d, 0xe9f5cab7,
3014 0x0a83a846, 0x7f74706c, 0xb3e47afb, 0x8f5b329d, 0xf5858edd, 0x09ccf418,
3015 0xc49b3b01, 0x174ae7d7, 0xdbadd6af, 0x5f7e1f7f, 0x2e60e5d5, 0xf76eafe8,
3016 0x87af9ba2, 0x76c3a2fa, 0x36ea4d86, 0xa123ab35, 0xd7c438be, 0x0e32bea5,
3017 0x4c97705f, 0xa79f4beb, 0xa076e33b, 0x2726c9cf, 0xd0f182f3, 0xb8ceeee2,
3018 0x3aadf80d, 0xbf1cbdb4, 0xf92adeab, 0x7753ed10, 0x85943a6e, 0x9721faf3,
3019 0xc92d9af3, 0x0fe06bcc, 0x29d13bfe, 0xef0ebe47, 0x193cc097, 0x7588bbf4,
3020 0xac3ea394, 0xad14f4db, 0x4ebe0633, 0xce34e936, 0x10fe1c80, 0xeaef81c6,
3021 0x387c925f, 0x0b1b7ac5, 0xeef63ca0, 0xa0d9cd76, 0xd59afce1, 0x6bce3742,
3022 0x16ed8aa5, 0x72ede685, 0x75be1179, 0xafbc396a, 0xad4ebb5e, 0x9adf918c,
3023 0x70cdc32d, 0x111fc9ad, 0x717d8f38, 0x6f0bec12, 0x1abd60e1, 0x45ea01f5,
3024 0xaec6a425, 0xa9496f6b, 0x2d9adf44, 0xf89af332, 0xf83dd388, 0xedd68caf,
3025 0x5f375ee0, 0x06dd05b7, 0xdba0aaf4, 0x51d05d69, 0x67892fe9, 0xe91b7c7f,
3026 0x2074f000, 0x255ca09e, 0xc0dcf3e0, 0xdfe8154a, 0x2e3a67e3, 0xcbe217bb,
3027 0xc79b3b0e, 0xcd39ac60, 0xac0afd9b, 0x7b2a1da3, 0xef99ed10, 0xd3fd86b6,
3028 0x966dbd60, 0x8025b302, 0xaa05b65b, 0xce15baf8, 0x857f75c4, 0x946f6f58,
3029 0x15af34bc, 0x809fc059, 0x25e98ef7, 0xc049641b, 0xcaf5869e, 0x4b9e3c1f,
3030 0xfd43dcfd, 0xfe4fd0a8, 0xcbd1fb85, 0xd1fa98a7, 0x7e8cabcb, 0x493f5016,
3031 0x474fd717, 0x786675f9, 0x7e8dabca, 0xcf1fa8ea, 0xff4bcdc5, 0x78660dc6,
3032 0xfd4b51be, 0xb1f34ea4, 0xbaeb8680, 0xedd607e0, 0xb6bde197, 0xe3c27535,
3033 0xca2f962c, 0xdcf1c61e, 0x7cb12520, 0xc9253291, 0xfea987c4, 0xf43aa661,
3034 0x2cbad3a4, 0xe3df8ff4, 0x4754b924, 0x4a17a4aa, 0x9e093a47, 0xa46a4687,
3035 0x2eba1e17, 0x87ae3970, 0x4bda3638, 0xab81a90f, 0x0d7c38f5, 0x132c4a70,
3036 0x320fb04b, 0x695fbe87, 0x1b2878e7, 0x7df0b675, 0xd6c1bef8, 0xf50a985f,
3037 0x3fe95b36, 0x959e3ce2, 0x24969db8, 0x976c46b3, 0xdef6e0e4, 0x0d92dcca,
3038 0xb53c18c1, 0x4bfa068f, 0xdbb6fd83, 0x5fc89903, 0x0ebf4bcf, 0x18adbf22,
3039 0xfc7d92ad, 0x22aff342, 0x2b8fd041, 0x22665747, 0xc82a1d3e, 0x2af8ec77,
3040 0xe3445f8c, 0x7ff1c06f, 0x477c6098, 0xf8d314de, 0xd32a9cce, 0xc6154ef8,
3041 0x26df7e07, 0x07c625bd, 0xd8c75dfc, 0xa1bfcd4b, 0x55391df1, 0xb44afe34,
3042 0x4fc7634f, 0x27ff181a, 0x5bbb8c12, 0x90d2ebe2, 0x675de7f9, 0xb54e7f9e,
3043 0x9f2afe79, 0xdfe95eff, 0x3449f8c4, 0xefcd7dff, 0x54e7f9f1, 0x783bf9f3,
3044 0x7be303bf, 0x107ff006, 0xd1247fe7, 0x306ff3fc, 0xad4c7fcf, 0x3e0efe79,
3045 0x0fa52ffe, 0x8d1af8c5, 0x13e6abff, 0x6a63fe7c, 0x11d57c69, 0xa91f21f0,
3046 0xc91a92a3, 0xed06cf9e, 0x94748234, 0xdcb1ca9f, 0xf2976eee, 0x250f0f08,
3047 0x3cfbbe71, 0x1b4df809, 0x042c77d4, 0xacfa0512, 0xcd7cf05e, 0x503552d6,
3048 0xde83de24, 0x5d40285b, 0x5f1325d0, 0xd08ed5b3, 0x6f6f0065, 0xfac41c97,
3049 0x0b5fd582, 0x71deb4c9, 0xb9cc007f, 0xc3ff3e08, 0xc7d6e3d3, 0x2e5acbce,
3050 0x889fb0ec, 0xc388e49a, 0x63632c13, 0x6bbe011b, 0x67f09d25, 0x1e804fd4,
3051 0x3f3fa065, 0xe58a3d00, 0x381fc287, 0xa9967a0e, 0x4cd372b1, 0x6f7741df,
3052 0xeebcc116, 0x509ff010, 0x2c4fbe38, 0xff884295, 0x507a9fcf, 0xb0b4fd45,
3053 0x3e901923, 0xa0834708, 0x476eff53, 0xf844bd68, 0xee7e22f4, 0xec645124,
3054 0x5fbec277, 0xe9b866b4, 0xd42cb9bb, 0x1fed0996, 0xb46f3558, 0x67bff30e,
3055 0x4c82638e, 0x947f9f7e, 0x8d98e48d, 0x318f81b2, 0xfb29f3a7, 0x39dca828,
3056 0xefb26ec7, 0xeb980aef, 0xeb9954f7, 0xdd90f6bd, 0x62c6f686, 0x7e83ad89,
3057 0xbf346def, 0xdbb1c637, 0x8c7b0986, 0x0647778f, 0x2c5ef787, 0x9d63e027,
3058 0xce9f7ae8, 0x69e035bf, 0x22cec478, 0xd3465eb4, 0xc1678fd1, 0x02d7b274,
3059 0x15b79f3a, 0x4eecfbde, 0x73c0057f, 0xe132c3df, 0x747f0ad3, 0x06dfb25f,
3060 0xcd745c76, 0xe768ed1f, 0x8563e75a, 0xd665feff, 0xea2ae8f9, 0xeb4179fb,
3061 0x5627ce73, 0x2ae86a7e, 0xa63c7e1d, 0xeff85d5d, 0xe18f1f87, 0xb32d9aaf,
3062 0xa1c5f54c, 0x17ed4cbb, 0x7a6799ad, 0xb163b0bf, 0xed03fde9, 0xf3ea9a0f,
3063 0xda9b0f82, 0xd9acbfdf, 0xc6defef4, 0xefef4cc7, 0x54ca7aa9, 0xacf02bbf,
3064 0x739dfda9, 0x4bde99d6, 0x898f16fb, 0x8c0d5e92, 0xf2bb42c9, 0x7e43076d,
3065 0x90ddf834, 0x329a8f87, 0xe4d93ca9, 0xe519b2a5, 0xb6dfe414, 0xeb0d979b,
3066 0x63d18de7, 0xed0ff6ec, 0x4f28398d, 0xe2b7be56, 0xf0dfcad3, 0x75bc546f,
3067 0xc16b28c8, 0xd73d475f, 0xe367d627, 0xf8648f79, 0x2e49cb07, 0xb72e556b,
3068 0xcab23bb5, 0x55ae5fd0, 0x718d8523, 0x79018afc, 0x0f344b0e, 0x3a745686,
3069 0xd5b80dd2, 0x137cd744, 0x65fb3d9c, 0x651ebf1a, 0xffdff417, 0xb2df1565,
3070 0x1c883ea1, 0x1c75b9cc, 0xc87fe3c2, 0xa574f086, 0xd3dbfad3, 0x71f86334,
3071 0x4157f105, 0x734d47e5, 0x14d13ca8, 0x5378f2a0, 0x341f9515, 0x6d195235,
3072 0x7be5465a, 0xdf2a414d, 0xf2a76a6d, 0x541d4db7, 0x435a6b1e, 0x429a6fe5,
3073 0xf936f654, 0x2bf01ca9, 0x26993d0c, 0xff614aec, 0xf5410ac3, 0x322e62d3,
3074 0xf24dddfc, 0x7944cbe8, 0x5e7dad3c, 0xe9f37688, 0x72c60e63, 0xcacbe313,
3075 0xcaf1090f, 0x545764fc, 0x4c394086, 0x95defa1c, 0xb2e4e9c4, 0xf40c19b1,
3076 0xfd9763c6, 0x88bf37c0, 0x861b0aea, 0xb37c87df, 0x05fa71dc, 0x75e915df,
3077 0x7f313a21, 0xa06cf17f, 0xfee789c7, 0xedfb04bd, 0xd70a75c1, 0xad3283cb,
3078 0xc1b22c97, 0xc18af487, 0xfd3fad1b, 0xbe5e853b, 0xa54efe00, 0xceebf81b,
3079 0xd8bb7f41, 0xa7ff53a6, 0x414c1d3b, 0x0e49ee3c, 0xf4eaa861, 0x5c1e0de1,
3080 0xda6496ef, 0xf071e3f4, 0xe1759460, 0x5d8b5d5c, 0xf5ccba27, 0x0cd21dd3,
3081 0xa6f2bf1e, 0xd67c86dc, 0x0bc7eba4, 0x5499fe90, 0xc92cfd1a, 0xe4e3f554,
3082 0x3af8871f, 0xf89535b5, 0x6a36fc14, 0x470d1ff7, 0xe1067ea2, 0x87bf64e8,
3083 0xc917c9ef, 0x337ef2ff, 0x7144fe53, 0xfec7b626, 0x0ee7ae39, 0xf91ceff8,
3084 0x8dd50af7, 0x72c21b7e, 0x3e3571d0, 0x0f1a6adf, 0x3e1af3be, 0xf3bcb9f1,
3085 0x4ec2abf1, 0xbdf9f8c4, 0x71f90638, 0xf7acdd2e, 0x86f54d53, 0xb4dd2cae,
3086 0x201fe00e, 0x524aacf7, 0x056a5f90, 0x5a29f4f7, 0x1df004bb, 0x2e8979b1,
3087 0x576f120d, 0x01aa8ce7, 0xcb4df22f, 0xb17bd71d, 0x2f1a8765, 0xe9b2716e,
3088 0x125157b0, 0x9f235fc3, 0x8e22a87e, 0x8d1c3f9d, 0x368bd427, 0x67334f6e,
3089 0x24fe83d0, 0x667a0ccb, 0x6d3409bb, 0x07e43f00, 0x753138c1, 0x21c59fa3,
3090 0x75bc7f7b, 0xedc6c7b2, 0x05b8eb64, 0xf85174b2, 0xb47adfab, 0xc56de71c,
3091 0xa7d77d63, 0x0be4806a, 0x883257fe, 0x47bf0347, 0x3205156c, 0xe5bd5ff4,
3092 0x3f27b27d, 0x1f0b07b2, 0x1ade8f39, 0x7996bf0a, 0xde663922, 0xe38dd641,
3093 0x5a7117cc, 0xdf3befe0, 0xe3f17581, 0xe30cecd7, 0xb42cecf0, 0x8303818a,
3094 0x3fa8364c, 0x3bf36a20, 0xfb3e286b, 0x41db8db1, 0x0785580b, 0xd62ac29d,
3095 0xe0768251, 0x819b6629, 0xdec53a78, 0xa18c4cf0, 0x25590cd3, 0x6ed03cfa,
3096 0x7ec043b6, 0xad17d535, 0xd92bd731, 0x33d40cec, 0x2cedab95, 0x4cfcd124,
3097 0x3ac8a7ef, 0x3588bbf5, 0xb9f5c0ae, 0xdfe3cec5, 0x8ca675f3, 0x5eeaf802,
3098 0xe304be7e, 0xdcc8b7e2, 0x1be2308f, 0xf871878b, 0x54ebc3ab, 0x7dffbc3f,
3099 0xae3bc4e7, 0x687df867, 0xc10fae05, 0x936f929d, 0xbf7e2877, 0x7856fc2c,
3100 0x487bf58d, 0x51c0459c, 0x1b8a45b7, 0xf057bd37, 0x3f8fc1b7, 0xec36f312,
3101 0x1eb197fa, 0xca37f763, 0x332aae22, 0x4a7ee919, 0x296d0677, 0xefe29ef4,
3102 0x5f0e1dc1, 0xacefcc0b, 0xf22962ad, 0xc50fd817, 0x59dda62c, 0xf79e805b,
3103 0xd257af48, 0xa11299be, 0x7b58107d, 0x357dd894, 0x8c53c939, 0x83376371,
3104 0xf71f35f5, 0x241482d5, 0x9aaee158, 0x6e318ac9, 0xfa00fa0d, 0x7e53d27b,
3105 0x4bba8258, 0x9fd864eb, 0x971cd323, 0xf5cd7977, 0xf703fc06, 0x8a32c67d,
3106 0x558f251f, 0x308c782c, 0x9f6e1fd4, 0xe42fbe25, 0x1f13de11, 0xa1c5887b,
3107 0xb9116a74, 0xe9461918, 0xf297f019, 0xf0e35fd0, 0xda007c53, 0xfb79d52f,
3108 0x5f07117a, 0x88d976fa, 0x9789e761, 0x15819c35, 0xdd4c7868, 0x519fd388,
3109 0x25e26858, 0xac2f55e8, 0xf57a31b6, 0x07e05b65, 0xa3d40f48, 0xe3049f08,
3110 0x04f86204, 0x563d571c, 0xf85a0fce, 0x23866fe1, 0xfbf4998d, 0xe5e05b11,
3111 0xcdfc7078, 0xe90e67fd, 0x687fe0ff, 0xfa4305ff, 0xfebc75ff, 0xb6de5eeb,
3112 0x54fc082b, 0x3da7e3fd, 0x63ecccc0, 0x07c323a5, 0xd4ddaf74, 0xfcb941e6,
3113 0x907a0948, 0x64871fae, 0xf2b3f7da, 0xe4315d81, 0x2549afd3, 0x47c43fc4,
3114 0xe27c5f27, 0x3eb7b466, 0xc9d764df, 0x88e2dfbf, 0xeb298038, 0xf973173b,
3115 0x9f78e2d8, 0x8a7e57d7, 0x65d0d9fc, 0x9bd517d6, 0xd2f0ce9f, 0xfe1415fa,
3116 0x87fc846f, 0x287f8dfa, 0x81ac7b47, 0xb3de93f5, 0x9fe3877e, 0xc2f64619,
3117 0xe865353c, 0xaebf637b, 0xa1a5e041, 0x654f89f3, 0xf9289612, 0x55f6d68b,
3118 0x5cf80fc2, 0x9367fb16, 0x33e464d9, 0xc42c1f03, 0xe5f900fd, 0x8e318be7,
3119 0x35f1b3d3, 0xcb14548f, 0x9def5c9f, 0xfdf03f0e, 0xcb137a9f, 0xc5e82f53,
3120 0xb0db7b58, 0xc25dbcef, 0xcbc3d97f, 0x83c47b5a, 0x75dafd71, 0x1e105f76,
3121 0xf0db6ed7, 0xae30e783, 0x77c3b6f2, 0xb35ff419, 0x5cdfd5ed, 0xed9af507,
3122 0x7c99b4f6, 0x31949a1a, 0xf8069748, 0x4184d96f, 0xe4ff543a, 0x8e3bd555,
3123 0xd8747f3f, 0xb66a3d20, 0xb8d957ef, 0x1a98f8a1, 0xb546afde, 0xbf097438,
3124 0x867e8e5f, 0x2a17f2fc, 0x7de3fdd2, 0x1b911b12, 0x5eeb9f07, 0xf1197b25,
3125 0x74147444, 0xa59ba01a, 0x05d0037d, 0x2741abf5, 0x4263fbeb, 0x6f3fb1de,
3126 0x4bf3f111, 0x907dc53f, 0x387c3adf, 0xbe97aaff, 0x7c79c1e9, 0xbe7234a8,
3127 0xc32dbe7e, 0xd956e30f, 0x953a1983, 0x0bd579fc, 0x5b7e22df, 0x195bf474,
3128 0xfe60bf14, 0x0ad91b2c, 0xdf9c2cc1, 0xd3b7b5c2, 0x80592afc, 0x79eaaef8,
3129 0xabd702b9, 0x633614cf, 0x78b91c7b, 0x87c5c844, 0x80f1c1eb, 0x0b887df9,
3130 0xbc0bee07, 0x06de5321, 0x7c520f63, 0x7ec65be4, 0xf5425b0e, 0x4e9c9ccf,
3131 0xefc315b3, 0x96279585, 0xecae375f, 0x1c9cfa46, 0x71811fed, 0x04a606df,
3132 0x73a43e05, 0x747cafd0, 0x1f4e08fa, 0xc44a55e6, 0xa7efa077, 0xdf6c73e2,
3133 0x8abbf76d, 0x73b1df4d, 0x2fe383b9, 0xdc03e315, 0x7ecf6849, 0x1f7f1198,
3134 0xac62b37f, 0xc5576037, 0x7c8c57f0, 0xf8df7973, 0x436f9718, 0x66b343de,
3135 0xbd3ffbe0, 0xbf07e5c9, 0xe0057b43, 0xf7a08c8a, 0x48936ffb, 0x2458381f,
3136 0xb46f5c9e, 0xbf36b90b, 0xe004f837, 0x1ddd7056, 0x7fec17e0, 0xec9fe118,
3137 0xf0d5cad8, 0x6cbe8c5d, 0x433cf1c0, 0x76e433fb, 0x87ff9091, 0xb3fcb314,
3138 0x13ee5cb5, 0xc2411bfb, 0xf43dad4f, 0x5e50e783, 0x1f713e41, 0xbd9b76ba,
3139 0xc9fde702, 0xb9bf83d6, 0x93e4e41b, 0x66a721b0, 0xd39569fd, 0xb0d71daa,
3140 0x09fa7278, 0x93c413a6, 0x571e7853, 0xf128b54e, 0xfe957ff1, 0x82f7f034,
3141 0x3e867f05, 0xab47844c, 0xf15ebc3e, 0xfaad3e12, 0xc9bdfe10, 0x9ff2864a,
3142 0xbf0677c1, 0x6ea8ff55, 0x019dea0c, 0x6ef834be, 0xbe0d2f80, 0x342f121b,
3143 0x3e886fe1, 0xf00cd8c3, 0x7feec549, 0x99fcc72d, 0x5f7c3dda, 0x843bbe14,
3144 0x9f93c075, 0x871d61bb, 0xd6c5a546, 0xd87a9643, 0xa96fded2, 0x07da5857,
3145 0x4b46f52c, 0x0bf710fb, 0x3caa0ebb, 0x6a62254f, 0x82ce5f6f, 0xef538c6e,
3146 0xd21e2995, 0xc0af3007, 0xb9ada4bc, 0x6863cc21, 0x5338f173, 0x02baba7f,
3147 0xde9f57f5, 0xb07b41ef, 0x73e3c5df, 0x9efd157d, 0xec3b18d4, 0xe9323dfd,
3148 0xcd8868df, 0x822fe788, 0x8bf44187, 0x79ef44b2, 0xacba7ddc, 0xf8c32ce5,
3149 0xc3ec874a, 0xe682cd90, 0xdfb83d3b, 0xff27b7df, 0x7cf03996, 0xb69911e1,
3150 0xfed0faf3, 0xfb34414e, 0x3f18ac95, 0x7c1623ed, 0xa38c06e6, 0xdafee1ef,
3151 0xbb165582, 0xbe22ad82, 0xaa96d4a8, 0xbfc117a8, 0x8fbcc0fa, 0x5abbf9c0,
3152 0xd6b557f4, 0xdef8defc, 0x37abe3f0, 0x8407df9a, 0xf9167fdf, 0xf1d2ed1d,
3153 0xbbf73c6c, 0x09378f19, 0x2e5d3afd, 0xe00e65ba, 0xccb0efbf, 0xef4e5f90,
3154 0xa7ff0991, 0x737df2b7, 0x8b5f9f8a, 0x7a4fda7c, 0x0f53c0cd, 0x589a85ca,
3155 0xfcecf4ef, 0xd023c95d, 0x3bd776a4, 0x6504ffc5, 0x0bb7aecf, 0x97f5867f,
3156 0x8779cadf, 0x753f6d0d, 0x2bf68b9f, 0x69b9f6fa, 0xef6fb17f, 0xc11e732f,
3157 0x8f876efa, 0xfdf6fef2, 0xa7f918b9, 0x0aa3b96f, 0x68df56f5, 0xecb667ee,
3158 0x947173fd, 0xa256c9d6, 0xee76e5db, 0xf3de9ee7, 0x6949efef, 0x70acc258,
3159 0x4c97dffd, 0x9f86b771, 0xd65e28ba, 0x25cff7b7, 0xa5fbf6b1, 0xec5ea7ce,
3160 0xd9b9f623, 0x5f081d9c, 0x697fdf2a, 0x1bb5d9f8, 0xa20f319a, 0x00fabf73,
3161 0xcffa9fbc, 0x3ea3145f, 0xedc1dbec, 0xf47b5e9a, 0x9b27dc05, 0xb962b6d0,
3162 0x8bd5e81d, 0x64fb8142, 0x0b2f3f6d, 0xf2f0f16a, 0x2f01c505, 0x8f7f1f16,
3163 0x9fff48f8, 0xf6890f80, 0xb8f76bbf, 0xe7094e43, 0xdef797fd, 0xcfb03d41,
3164 0xcc697c41, 0x337093f7, 0x9a171dd9, 0x6e57d577, 0x62e452de, 0xbff2bde6,
3165 0xedbbff39, 0x2acf825e, 0x7cf94307, 0xdf5443ef, 0xbc11f6e6, 0x9befc917,
3166 0xdf746abf, 0x5cf77401, 0xfe87de78, 0xc8fdd2c7, 0x3aee827d, 0xfc3499e6,
3167 0xdf0417f3, 0x2773d597, 0x3dd39bfe, 0xfb0dfcd1, 0xaf9b71fc, 0x6ce30f23,
3168 0x3ac3fd68, 0xb767b9ad, 0xf1efd863, 0xb475b3b1, 0x2fb16517, 0x846f8569,
3169 0x191ffdca, 0x5e3127f7, 0x3c899a37, 0xd10fee6d, 0xad0c1d96, 0x8f649568,
3170 0x6e0ada2a, 0x6ebe2b27, 0xf1e5e03f, 0x28fbe72b, 0x384d8787, 0xf67ac016,
3171 0x438a3e0d, 0x56c2fc5b, 0xb025f989, 0x6f2b9553, 0x8a7e8c3c, 0xe22dac7d,
3172 0x7df2a628, 0xf88a572c, 0x4d575da2, 0x64568bfe, 0xe6bcbbae, 0xe7f443ba,
3173 0x677e1c64, 0x9c610b26, 0x80e2be59, 0xf265f98e, 0x50498578, 0x208eb177,
3174 0x4c8e09fa, 0xc47ff7f3, 0xb898d364, 0x11ebda2c, 0xbe7fd7b0, 0x07c50375,
3175 0xfef8bd4e, 0xcd6fd8cd, 0x04e664cf, 0x756ef4bc, 0x8df208b3, 0xffd15212,
3176 0xfd94eea8, 0x523c8f3c, 0x3ecc6b72, 0xd62761a0, 0x704dd8fc, 0x8470ef55,
3177 0xd5f7c266, 0x4c5f7ebb, 0x7ef2f6eb, 0x2f8363b2, 0x3d4f3c4a, 0x7dc62d18,
3178 0x0e716abe, 0xf1a74ac0, 0xf77f8f2a, 0x839e4eec, 0x85b4bafe, 0x875649e7,
3179 0x623bb4ef, 0xaac64bf2, 0xf11da376, 0x1287f051, 0x7c20a9e5, 0x8679f9b1,
3180 0x43f3da9d, 0x65d7c389, 0x65be610f, 0xbded96f5, 0x3ea87718, 0xd9a1f0e6,
3181 0x53e5b0d7, 0xfd4f6b8a, 0x944f36f1, 0xe4d92cfc, 0xf7f10e77, 0xd744c8b6,
3182 0xb23acefa, 0xf44ea15b, 0x8fc70fad, 0x2fc85c7b, 0xdef1f9a9, 0x6140415d,
3183 0x7b364fcd, 0xb271ae30, 0xfc87937b, 0x8fe72dbe, 0xeff10cb7, 0xd79d8fc2,
3184 0x7f893bbf, 0xb774fd80, 0xb78ff16a, 0x15fb270c, 0xb7892be0, 0x4df065df,
3185 0x5ecfb6cd, 0xcf63f8c0, 0x405e4f8e, 0xfaff6b78, 0xfed017c7, 0x3a5cfb64,
3186 0xbc3443ee, 0xbf14aff8, 0x2a5bbe31, 0x87f7aee4, 0xd5ee299b, 0xf6357e0b,
3187 0xc3f7bbd6, 0x7a3ff41c, 0x0325ffb7, 0x7ba5e4fd, 0xf9c08fa7, 0x7539dd2e,
3188 0xbf238b04, 0x1b7c8946, 0x9bb888ba, 0x3b075e95, 0x7c9d920f, 0x7e8de80a,
3189 0x1ebf80ca, 0x0ff1e3ae, 0xb7d3f0af, 0x0e6f8fc6, 0x6f3bcbf1, 0x936be5bd,
3190 0x50fbb4b0, 0x3fd05c0d, 0x78e8137f, 0x6fd045f5, 0x5fc263eb, 0x53bf4f89,
3191 0xe9d007f8, 0x57f0aabb, 0xeb3efd04, 0xe7fdf85c, 0xf0e75df0, 0xe479fe84,
3192 0xc466f022, 0xfd57ef4f, 0x3728abcf, 0xf1447e3b, 0x4cdba410, 0xb6ef6898,
3193 0xee3072cf, 0xffbd91fc, 0xef579e3e, 0xad1fd1d0, 0xc916fbde, 0xa3ceef4f,
3194 0x22649f14, 0x06cbd98e, 0x93b8f1fe, 0xd86b85c8, 0xbd7ee6e8, 0xfdfa3fc0,
3195 0x173d0f5e, 0x63e73dfe, 0xe44fefc3, 0xf2a9bfef, 0xae23023c, 0x1df1b75b,
3196 0xd20f3fe1, 0x74829a4b, 0x71bcff7a, 0x3a0f0368, 0x6c7261e2, 0x5c7e2afc,
3197 0x29ce2065, 0xadc465e8, 0x5053e206, 0x4578c6cf, 0xc58b7a48, 0xebbd07d1,
3198 0xd7abdc78, 0x199fce6e, 0x678f0fa4, 0xa72adafd, 0x638b8ba1, 0x2ffe085d,
3199 0xea889f8b, 0x0c73c535, 0x8d9cf53c, 0xab4fc7af, 0x37fa9e3c, 0x902c87ef,
3200 0x9f21fbac, 0x75d63f22, 0xf3f2afbe, 0xcbbcfc04, 0xc8b7bec0, 0x5179ebf7,
3201 0x8ac878a6, 0xe3d241f0, 0xec617d56, 0x55e15997, 0xd54f5c1c, 0xa275f177,
3202 0xa43b8767, 0x073d3f41, 0xd73f1376, 0x455f7d6f, 0x96d0f33f, 0x9edca89f,
3203 0xeb83f2e2, 0xfe062844, 0x17f6979e, 0xcf1d78f3, 0x338eb63f, 0xd2f1c1cc,
3204 0x38fe27b0, 0x353f5b0d, 0x0c13538d, 0xf37f3cab, 0x549de3fc, 0x7f6277fc,
3205 0x0cedbb27, 0x864ef3f3, 0xf6f119e5, 0xeb133f67, 0x035e71a6, 0xb3ca4bd7,
3206 0x33cfca3e, 0x89237a4c, 0x1e9798f2, 0x9e0ef19d, 0xe20a5b8b, 0x6760f68c,
3207 0xced3e733, 0x428ff07f, 0xbd1e777a, 0x6a75c65b, 0xc637e217, 0xb3792c2e,
3208 0xf41baa71, 0x15bbc942, 0xad5d9093, 0x31f266fa, 0x187e099b, 0x03ae0467,
3209 0x9e0fd0ad, 0x27fcc02f, 0x94f64784, 0x647840cf, 0xe2bba6dd, 0xb5da95e4,
3210 0x36f3ca0a, 0xe6ebb5fa, 0x76766e3c, 0xe9fb17a2, 0x0bc8c2bd, 0x3c4148aa,
3211 0x3b7dd67d, 0x29159d2f, 0x99d679fa, 0xecbe848f, 0xef01f269, 0x581673f3,
3212 0xbdf9106f, 0xd20e7b55, 0xb0aaa2b9, 0xaf80bcc4, 0xe483acc5, 0xaa4766e6,
3213 0xdb335bc8, 0xfe7bd50f, 0x7757da85, 0x2c35f6f2, 0x3cf1ed4c, 0x1f24c446,
3214 0x07762d13, 0x913eefe7, 0xa67b51d7, 0xf6624584, 0x7c13ef71, 0x9ba4d3db,
3215 0xc22d7bf4, 0xa939e1a7, 0x2ea71a6e, 0x8e34dc3c, 0xcceeaed1, 0x93122c75,
3216 0x74a7547f, 0x9dd5bf13, 0x671a3bf9, 0x329abe40, 0xfb890f09, 0x7b82651f,
3217 0x2629ffb0, 0xbffb0778, 0xe6b5c681, 0xe6ce6677, 0x5bacc271, 0xce341979,
3218 0x852654bd, 0xb76f005a, 0x0e25816b, 0x5ee99f68, 0xc32afb9d, 0x285356f3,
3219 0x8761fa3f, 0x8cde50a4, 0x4a759f38, 0x583682d7, 0xd6d39f6f, 0xa303753f,
3220 0x707f813c, 0x2793135c, 0x3e7422c0, 0xe43768d3, 0x208f25bd, 0x15013f1b,
3221 0xf2f80b28, 0x68c11e45, 0xb4f3a516, 0x3cfcdd6b, 0xcd2d18e0, 0x106fdf86,
3222 0xde71be76, 0x40f9c86f, 0x0bc0b9cb, 0x9b4c079d, 0x18e0fa5a, 0x396f631f,
3223 0x798a9d3e, 0x967769e2, 0x83a51f6e, 0xa652c1df, 0xe9737d51, 0x97a82cf8,
3224 0xf5e16fb5, 0xcf8e975f, 0xab957a81, 0x246bd793, 0xb35fabca, 0x60b4c172,
3225 0xe5e825d1, 0x252300db, 0x11bcbd26, 0xe2aa71e9, 0x7a163bdd, 0x5fa14f31,
3226 0x1565f8e5, 0x14f46ed8, 0xed6cb78e, 0xa788eddd, 0x3368b631, 0xefef93ea,
3227 0xea2a73fd, 0x09d32f71, 0xd56b3a3f, 0x68f07e91, 0xe4f3b9ca, 0xc2f359c3,
3228 0xa5d9fe0c, 0x1c227605, 0xd2c7f36d, 0xaae7bc39, 0x1fd13826, 0x6cf2235c,
3229 0x0fc81d9e, 0x7ef1e7e4, 0x75fbe0ee, 0xeb0f2299, 0x29b9a3f4, 0x0fa3cec3,
3230 0x5dbb321a, 0x7d5c0c4a, 0xb3ed3f4a, 0xff7d9df7, 0xc49bcc3e, 0x759c6a7a,
3231 0x37fbf065, 0x93c90a5d, 0xe981ff39, 0x0b5fc469, 0xde217f04, 0xf879319c,
3232 0xcaa0e48b, 0x8874c3cf, 0x8e9a6ef5, 0xb58297f3, 0xbeabb9f2, 0x68169e3c,
3233 0xcf90f781, 0xbc8871df, 0x34be711b, 0x7be33ce6, 0x79eb4788, 0x8a8e8dc6,
3234 0x55977e28, 0xe5072679, 0xa27ce06d, 0xf48591d4, 0x64779eb3, 0x9e2dbf4a,
3235 0x9c5eb11f, 0xf7044c77, 0x3e819d8f, 0x9fef3f1c, 0x830e3bbd, 0x40bd5fdc,
3236 0xe7ca61f5, 0xa526cbd5, 0x215cfc2b, 0x820d05d9, 0x5c6d32af, 0x1887b03f,
3237 0x39f6d3ed, 0xebfa3f24, 0xc9d4df7d, 0x305ec80e, 0xbee6fc93, 0xe630dce4,
3238 0xc23df513, 0xfd8297cf, 0x8f7ca120, 0x711293de, 0x3f3e4879, 0xe7e7c8b7,
3239 0x3cc97b66, 0x6f39df6e, 0xd3fa9457, 0xc8607f45, 0x0f9e0c67, 0xfaf993ee,
3240 0x25e4d7de, 0xe0b34638, 0x2f13b47e, 0xd38f3c76, 0xf017fe7c, 0xf0633baf,
3241 0x811c740f, 0x426734f5, 0xc6708e3a, 0x1cf5a3a1, 0x204711ea, 0x587ddb1b,
3242 0x86056879, 0x4fe7ac5e, 0x42cc1299, 0xdbe9593c, 0x6b3c74a0, 0xec662987,
3243 0x16ec94f9, 0x2f577e83, 0xc32ba5f3, 0x8b1cf44d, 0xe7bd5e70, 0x6dc21b53,
3244 0x527bf1d0, 0x8277bb7c, 0xd667af93, 0x44e632f1, 0xed38816d, 0x5095978b,
3245 0x499f807f, 0x8f5cfc16, 0x14e29af3, 0xfc50c2eb, 0x2fed8f5c, 0x8bfe3f02,
3246 0xc7e18fc1, 0xae3908d5, 0xa0277dc1, 0xb3bc1ff3, 0xdc60f233, 0x3e235972,
3247 0xa649bc5d, 0x9fb42db8, 0x28319599, 0x6daf8bf7, 0x7e076fdc, 0x44bcfc59,
3248 0x9c40b4fc, 0x9c44ff2f, 0xefe6b13f, 0x9209ce55, 0x1e70bd9e, 0x46f4885f,
3249 0xf3f316cd, 0x7fc29dbb, 0xca1cb374, 0x47f715cb, 0xad7f82c8, 0x09ad3ff8,
3250 0x6a905eb9, 0xc7a5676a, 0x299b46e8, 0xea6b3c0f, 0xd7e43f40, 0x6fbcda67,
3251 0x17edfc51, 0x20f18676, 0x293692bf, 0x2498f882, 0x4b7ec34d, 0xfd197c85,
3252 0xb666598d, 0xe68372eb, 0xedf979f3, 0x9779f3e6, 0xb5348c75, 0x9e4d7cbf,
3253 0xa115fde9, 0xafef4d2b, 0x54c132da, 0xcebe171f, 0xaeeafed4, 0x7c7d5332,
3254 0xfb5346e4, 0x9b678789, 0xdf74d7ea, 0xf93f6a6d, 0xfbd37cd8, 0xa6d5a36b,
3255 0xb47fd7f7, 0x5aff54c4, 0xb531ffff, 0xfae42c8f, 0x665340eb, 0x7c98f1f6,
3256 0xaa0f03e3, 0x3f9f1d36, 0x8bd36858, 0xf8679f63, 0x9658c5bd, 0x4e9fd1f8,
3257 0x3aa767a4, 0xd763b2b3, 0x376652f7, 0x4ea99fe9, 0xf0643d73, 0x0bf00e4b,
3258 0x45937f10, 0x6dbc80ef, 0xd5193941, 0x983b4378, 0xe2e46ca1, 0xa7941482,
3259 0xc5f9f1a7, 0x9236d9c9, 0x9d08fab3, 0x0e738f8b, 0x17356dfe, 0xf7482ef9,
3260 0x2e1980a1, 0xa33100ca, 0x9606e60c, 0x29060b0a, 0x28f99cd9, 0xeebad2ef,
3261 0x15bdeb1b, 0xdc9c071f, 0x6178701e, 0xdfd9379d, 0x645fee21, 0x3129731e,
3262 0xa8f590f8, 0x1ef0eea9, 0xd77fe2d6, 0xeb2e7a6d, 0x69754cc7, 0xffca4cd1,
3263 0x3d970449, 0x1b4dfe73, 0xb3d9bf41, 0xcf1a5402, 0xe2d8e6db, 0x9d45f7e6,
3264 0x9de79717, 0xf10bbed0, 0xfb18a5fc, 0x39748a2e, 0x33c6f695, 0x3f56af98,
3265 0xeffc9fb7, 0x3f59872c, 0x237dd60c, 0x97963e78, 0xf9d4279f, 0xda9b6b9f,
3266 0xdf75c26f, 0xb7c2e798, 0x7e606767, 0x7f027642, 0xe7c5c73c, 0xd55342f1,
3267 0x8cf00b4d, 0x2589da09, 0x73b2e783, 0x68e50d22, 0xf9118d7f, 0xe2d8cfd4,
3268 0x759d3de7, 0x047b7f72, 0x13b4682a, 0xcb3f7e34, 0x3d77caa9, 0x2455b298,
3269 0x7f22ce07, 0xbbbabfce, 0xf65f9f84, 0x7c3cf265, 0xf437e09d, 0xf1568e5c,
3270 0x1cadea0c, 0xb9bcd730, 0x3119e143, 0x2e4662b7, 0x661d6fbc, 0xef5469f3,
3271 0xf05ce897, 0x870d8ca3, 0x957fadf6, 0x03d6be09, 0x905e52d7, 0xda1805aa,
3272 0x993cc6e1, 0xf63037c8, 0xbb4b3e11, 0xd6d4fc8d, 0x05ce072b, 0xb55bf231,
3273 0xf7ec6e8a, 0x0858bc33, 0x932d69c6, 0xb473ef4c, 0x010f078e, 0xc99d951c,
3274 0xd6549714, 0x967e4cdc, 0x69e1c99a, 0xd962417d, 0xe3c3c112, 0x0f8e1ee6,
3275 0x42ea83c0, 0x3f73fb3a, 0x869319b7, 0x2a2975f7, 0x9d1ceb9d, 0x8d719e20,
3276 0x5b7ebf01, 0x9709d906, 0x5795e19b, 0x21e0fd3f, 0x89d903cc, 0xfde11637,
3277 0x3d04cb22, 0x4b6df3cd, 0x5dcb7d9b, 0x4de5aed0, 0xb800c999, 0x30d8ca37,
3278 0x0a1c879a, 0x41b7c1c5, 0x1afb802f, 0x535e5b84, 0x15ccf34e, 0x74045e74,
3279 0xd32575c6, 0xe8833156, 0x3863619e, 0x37fc2b4f, 0x7fdcb8b8, 0x790ba5cd,
3280 0xe369bcad, 0x90172c70, 0x9b5e81bc, 0xba97fd86, 0xd311da12, 0xdbf4715c,
3281 0xa8ffee85, 0x087dd39d, 0x136fd94b, 0x61636d76, 0xfa0cbdac, 0xd7ec16f0,
3282 0x8f29cba8, 0x17bf6316, 0x141bbbb2, 0xee617b5f, 0xb432ed85, 0x0cff90c7,
3283 0x39e60c7b, 0xcfbbc70f, 0x31ebd665, 0xeb9e7c7a, 0x4ac9ece2, 0xdde1f76c,
3284 0x12f6b891, 0x1bb271e8, 0xfaf8d5d3, 0x1e82fbee, 0x28caba0d, 0x3ec1302f,
3285 0x5c5d77d1, 0x4ff3adae, 0xc85ddeb4, 0x611bc8ef, 0x14ec07ee, 0xa5583ff2,
3286 0xa756fb4a, 0x58f75d1f, 0x68fbe621, 0x9bc79479, 0xcb519fa8, 0x0f3f20de,
3287 0xe204f9f0, 0xbb5fc0c1, 0xc69e7f85, 0xc5d6f1f7, 0xcda7c05a, 0xd70ecf84,
3288 0x7f9fd845, 0xf328b9fb, 0x815e9e79, 0x0ffbd077, 0xf5b83e92, 0xb38c12bd,
3289 0x39fedfd4, 0x79bffde9, 0xb8e6399c, 0x802f1181, 0x9c716a71, 0x2aff5bde,
3290 0x8a51bae2, 0xbcecb647, 0xab07ee9c, 0x49f4332b, 0x45ce93a3, 0x7d11e766,
3291 0xf872ed4e, 0xc353ce11, 0xd4ec5c78, 0x3087c9ae, 0xd349f32e, 0x73d8bce1,
3292 0x3a5ea759, 0xfe87625a, 0x5a38ed4e, 0x0f5e90a2, 0xf78cde11, 0xa5fee775,
3293 0xe377fd04, 0xdf00c1fc, 0x4bafe339, 0xf9fc16bf, 0xf180f165, 0x525fda78,
3294 0xcf68b3d8, 0xd6a5e00d, 0x2a7ff79c, 0xc412bdf9, 0x13ffe603, 0x463c045e,
3295 0x8bb57bbc, 0xa45a9fc7, 0xc6e31060, 0x54f7522d, 0xff06d38c, 0x4073a317,
3296 0x9256b799, 0xcc3dfe99, 0xd61abc03, 0xb7db0ca1, 0x3e667db1, 0x750b9b1b,
3297 0x111d2bc7, 0x1dd49f7c, 0xed42bca6, 0x4b047758, 0x8fdfb44f, 0x47fa86db,
3298 0x6f2c7efa, 0x86ff02d7, 0x0feb0fe3, 0xfdf2815e, 0x3313058f, 0x4ca12631,
3299 0x62f61df5, 0x852ce21e, 0x7d3a6dee, 0x2275a658, 0x3d739663, 0xa8ceff3f,
3300 0x5eedccfe, 0x9392375a, 0x81e9f38c, 0x15575c5c, 0xf611fa56, 0xf815d5bb,
3301 0xc33ff904, 0x08785dd6, 0xfb1d73be, 0x79e60e6d, 0xeda2f71b, 0x8fd8ad2a,
3302 0xbbfdc6fb, 0x367aef25, 0x9c9f6e34, 0x28dfe5c4, 0xbe3527bf, 0xc961f98d,
3303 0x63a7db8f, 0xae7bebbc, 0x0547ba46, 0x999df9fe, 0x702b9fd0, 0x71854b0f,
3304 0xc66da924, 0x876ea0d7, 0x7bf1e3f7, 0xd02b5b5b, 0x606a5761, 0xbbde0d94,
3305 0x87ad73a5, 0x8dfc3df1, 0x49c965f9, 0x9ef15ae7, 0xe7493538, 0xb902d0f3,
3306 0xba818748, 0x4c77750e, 0x2ba969dd, 0xabcc6ebc, 0x285fe0ee, 0x0f7eb3ef,
3307 0xef07d7bf, 0x337dc333, 0xe50cb7bc, 0xe849353f, 0xb1698d09, 0xdacea1e7,
3308 0x3c49e902, 0xe5c8593e, 0x265f88c4, 0x97e22f78, 0xe291ac85, 0x60f1236b,
3309 0x5bda3e75, 0xb0e654dd, 0xf88d2a7e, 0x51f31e5b, 0xa82ac059, 0xa83acb1c,
3310 0xa98592bc, 0x54dd622c, 0x2a7eb316, 0xb1974c7d, 0x547cc09c, 0x8f1ad9a6,
3311 0xf97d474e, 0xcbe93b0b, 0x1e0f2dc2, 0x0508c918, 0x6aa5ba26, 0x69867e5c,
3312 0x2864a1a5, 0x80388b57, 0x16a9ae71, 0x3545e669, 0xd07d90a0, 0x93ea6423,
3313 0xee20b635, 0x2ab9b29f, 0xe715af3d, 0x3edf6b80, 0x27e47640, 0xaa79f8fe,
3314 0x4b949353, 0xeb3287dc, 0x1ab586c7, 0x73e41be1, 0x1ebbe22a, 0xcdba82e1,
3315 0x1ee74dd9, 0xdfc3cbed, 0x745f7196, 0x45f69d9b, 0xa026506b, 0x0c2ee35e,
3316 0xa7984b35, 0x9f6a515b, 0xf24d7c44, 0xce1a9353, 0x9e0da098, 0x78fac407,
3317 0xebdf906d, 0xc1ca9ebb, 0xf78ff67d, 0xf9eb4dbf, 0x34b9c9f5, 0xa3ceba9f,
3318 0xfb4dc06a, 0xcdca2a76, 0xf603e9c7, 0x6d8dd937, 0x9e0a5f2e, 0x25ffe93b,
3319 0xc0ca8fbf, 0x7e95f7df, 0xc7beec57, 0x745026e1, 0x37af632a, 0xabf95265,
3320 0xbf952f26, 0x1f99d268, 0xf623b91c, 0xe11136a8, 0x11d02f4d, 0xf0f44fde,
3321 0x612663eb, 0x179e7b1e, 0x7692d3e7, 0xd444d57c, 0x77d93e3f, 0x77638c19,
3322 0xf7849f2f, 0xce64b627, 0x95947ca6, 0x1fe704da, 0xc5169e00, 0x71874ce7,
3323 0x6876d35f, 0xd3794197, 0xb89d9317, 0xd696bfae, 0xdf7179a9, 0x3aedfc64,
3324 0x7f4103ee, 0xfea56fab, 0x09bfa2ec, 0x18ff6c4e, 0xf60da3f6, 0x6fd45fb3,
3325 0xc348ef72, 0x189a87f7, 0x7a537dc1, 0xf7f61a67, 0xaf85a2f3, 0xdf84984f,
3326 0xbbdee2db, 0x3499d374, 0x67bb07e6, 0xe61c99e6, 0x737af587, 0x2895e359,
3327 0x9a4ddfff, 0xf904e6d6, 0xab1b7257, 0x4dac5f51, 0x09cdb9ba, 0x3653efc6,
3328 0xf54e93a0, 0x0015dae9, 0x1fae34c7, 0xbc36f200, 0x659ed06f, 0xfc3af8a3,
3329 0x8e5eeba3, 0x8eb8fea0, 0x2d969fbf, 0xfda010f2, 0x9f9fc7cc, 0xad57768e,
3330 0xe962f9c4, 0xd3ee8ced, 0x544f6448, 0xf3a2499d, 0x7afd4679, 0xf31104ba,
3331 0x8fb483d8, 0x43c67552, 0xbe2efae7, 0x1ce9a73f, 0x34fed0e0, 0x95f0ef1a,
3332 0x29f93f06, 0xbb74b36e, 0xf970cfc8, 0xefbb6047, 0x83f98dd9, 0x7c44edbd,
3333 0x0a83d40d, 0xaa23dbe8, 0x6df9ff31, 0x6e7f40d3, 0xb3df0756, 0x658f9829,
3334 0xf47e67bc, 0x89248f87, 0x7e3ab07a, 0xfb4b24fb, 0x4dfea33c, 0xe7856f6a,
3335 0xbac1ae7b, 0x5f2bda13, 0x08ea0638, 0x4b3653df, 0xf18cc37f, 0x6afea11f,
3336 0xbed16572, 0x12bf55f5, 0xaae0ef43, 0x667bd2f3, 0xad6dd3d2, 0x9011fdf0,
3337 0x6ebf5a73, 0xa17eb467, 0xf462f9dc, 0x6eb14ce0, 0xd2b99d55, 0x3a418f44,
3338 0xfee89b14, 0xec65c821, 0xada2eb3e, 0x2173a4df, 0xbcbc9333, 0xe7e4161f,
3339 0x9be6d69c, 0x3fff57f6, 0x1c2b7f1c, 0x4c7004fe, 0x63862ffb, 0x41bc69ac,
3340 0xf04c8a38, 0x51c3e7fd, 0xf28e0096, 0x561c14af, 0xc728c57b, 0xf642bda0,
3341 0xb0f38f2a, 0xb7b236e5, 0x151552fb, 0x369897f3, 0x5204ec85, 0x8eea5e19,
3342 0xf146f1f6, 0x8f7799ae, 0xf3b61e63, 0x995dac2a, 0xe82afa80, 0xed7dc3cc,
3343 0xe07ef16f, 0x740561f9, 0x2754e8d0, 0x177b47ed, 0xfc60d454, 0xb2a73bdf,
3344 0xf1bd4a8e, 0x33ffbc16, 0x3c7fa0a7, 0xb4eb77da, 0x98db17b4, 0x6905ef49,
3345 0x241e97dd, 0x13ee76bb, 0x2c94dadb, 0xcf8d9bd4, 0x052c1da2, 0xce1db5b7,
3346 0xeb9ef78a, 0x5f927bad, 0x542975a2, 0x3f44aec6, 0x850ae428, 0xda3d200f,
3347 0x23d21f34, 0x7b5089f7, 0xc795d41e, 0x8066be6c, 0x6d0d4957, 0x2bf00f59,
3348 0x9afa164f, 0xf5087de1, 0x527fb61f, 0xab3de109, 0xd9bc9a2b, 0x8b49bf78,
3349 0xb7d68fb0, 0xdf31d4ce, 0xb30a9ed8, 0xb0ae5204, 0xf685de37, 0xd7e49afa,
3350 0xe2d79cdb, 0x1f6be07a, 0x267af3ae, 0x8f39b5c0, 0xc55339e5, 0x437f587b,
3351 0x1ea46ccd, 0x7f4af753, 0x5fbcf995, 0x80dff36f, 0x6a92fceb, 0x157fbfc6,
3352 0x879b95e3, 0xefe17819, 0x5c7531bd, 0xc1e6944f, 0xf79834fa, 0xbeb9e786,
3353 0x47fa147f, 0x13e61f7b, 0x1c6e3b24, 0x8c324f9f, 0x2710f78d, 0xf5a3cf8f,
3354 0x8beb0435, 0x578fdf07, 0xb1963ce8, 0x671ce3bf, 0x6c1dfda3, 0xdce4f58f,
3355 0x73ffda3c, 0x08be62ce, 0x6966ede6, 0xf150bf7c, 0x38fcc34f, 0xf8bf00f7,
3356 0x8aa8de29, 0x926d0ffd, 0xa93fff79, 0x39b4bbf5, 0x7e64549e, 0xd7302cee,
3357 0x1f37cc1d, 0xb66a9683, 0x592879f9, 0xb387efc4, 0xe457e891, 0x6c3682db,
3358 0x510b0577, 0x908b1579, 0x458e3f5d, 0x86357ea9, 0x38f1f33e, 0x700e9794,
3359 0x997e644d, 0x642b47c7, 0x68163bf4, 0xbf68cd81, 0xfe164c6f, 0x6fde48ca,
3360 0x77c1454b, 0xbe297ba6, 0xc5e519b1, 0x559eafa8, 0x448df14e, 0x3c69a5f2,
3361 0xdee2388e, 0xfbdef382, 0x8f8cf539, 0x3ce46379, 0xbb79e35d, 0xba31b70d,
3362 0x0f61a28f, 0xf78ca3f7, 0x7ef324af, 0x2fc4121b, 0xc15fae41, 0x459f7c79,
3363 0x74b9edcb, 0xd3dfc9cf, 0xda8fb03d, 0x17548218, 0x6dfb9b79, 0x513b7b16,
3364 0x92cfd91e, 0x80f2fe79, 0x18fc235f, 0xce9035f2, 0xe0597fc2, 0xbe6ee832,
3365 0xc7b8c1cf, 0x4dc84fa1, 0xc44aa55f, 0x09834068, 0x05b7e9ea, 0x4a801ee8,
3366 0x35ca9f31, 0x1fe819a5, 0x177fd82c, 0xf570b9c1, 0x0e30352c, 0x23cdc9cf,
3367 0x5d7818bc, 0xfe0ff160, 0xbcf131d8, 0x9ec332f1, 0xc303fc36, 0x09fab01f,
3368 0x71bfbe89, 0x43a27eec, 0xed296679, 0x7b237edb, 0xc0eb0d96, 0x4fbc7e6d,
3369 0x78af38ca, 0x9feecec4, 0x6439445d, 0xb3f9f033, 0x550f7e2e, 0x7543dc48,
3370 0x0c3f9bd8, 0xff919bbf, 0xbe5815c5, 0xa86b0ce6, 0x7b3b5fb7, 0x1ff266f4,
3371 0x7986b094, 0xee14a717, 0xc67519ff, 0xbf14c8ce, 0xc9bf7817, 0x8fdd06fd,
3372 0xefee5370, 0x9d78bce8, 0x573a0dfb, 0x4ed3aa7e, 0xb9377279, 0xf7b169c2,
3373 0xbb94dc67, 0xf87ced37, 0x2387fc31, 0x79c3de02, 0x6804e49f, 0xe19f915c,
3374 0x4b9d20df, 0x35bdfc4e, 0x471ae33f, 0x61f23759, 0x5dd7e0b7, 0x8345205a,
3375 0x21766db2, 0xacda4fc9, 0xbfde4e49, 0x94247f39, 0xc57c44cc, 0xff0647cc,
3376 0x5905ef59, 0xe873f12a, 0x386ae089, 0xafad3363, 0xa884f783, 0x8af6beb4,
3377 0x26774378, 0x907afa7b, 0xd1ac5997, 0xe26ffb4e, 0xc916957e, 0x313d476b,
3378 0xdfb96fcb, 0x5551e447, 0x2df0f588, 0x6a051f91, 0xe63f55f1, 0x7d3f3175,
3379 0x63ee2dd7, 0x8f602c61, 0xfd023f97, 0xaddaf49a, 0xdbf5cc33, 0xeb75cc2b,
3380 0x1e46863d, 0x7a4d2bcc, 0x5d3dec76, 0x87e812d3, 0xa5db351b, 0xcd1a0fc5,
3381 0xae2303f1, 0xc3f98757, 0xe3c2cfb4, 0x7c9dd37a, 0x8b88b2fc, 0x341a2ff6,
3382 0xb8861d75, 0x3de19f51, 0xae35d3f6, 0x845e306f, 0x574d04f7, 0x436dfb8c,
3383 0xef939f22, 0x6457a47b, 0x7dfdfb8a, 0x54af7499, 0x1ce99257, 0x386711ab,
3384 0x494de05d, 0x3b7f0f3d, 0xad70d8d6, 0x54afa818, 0x07c89d1a, 0x5e79b32b,
3385 0x871f20d5, 0xc754f14c, 0xfdee351a, 0x80fd0372, 0xe273c15e, 0xdb6fb12e,
3386 0xd8f5f8ae, 0x5ec38478, 0xda7f23a1, 0x5edd65dd, 0xab55e5e0, 0xabc72cee,
3387 0xbf305a0b, 0x4694ec17, 0x822bebed, 0xed3b4fe0, 0xaf78c3be, 0xf36dd3af,
3388 0xacdc7ae2, 0xab3f68d9, 0xeb49d325, 0x56a90aef, 0xe8d2f5c7, 0x685519d7,
3389 0x3cb5a73e, 0xe0897fd2, 0x669fc153, 0xbe631fb4, 0x6f3fea8f, 0x0dda8d3c,
3390 0xe0eaffb9, 0x756714b5, 0xff946d79, 0x746816a4, 0x5fc19a8f, 0x6b9c7ed6,
3391 0x24fdb894, 0xba427fc2, 0xd794a3db, 0xdfc5abd6, 0xbb497e5f, 0xb9eebcc4,
3392 0xea777896, 0xf8230a6f, 0xe0f514bd, 0x8f902eb9, 0xab8c3497, 0xabfd3e8d,
3393 0x47c92f52, 0xe1afcf06, 0x2da2db72, 0x5fbcf277, 0x89693df3, 0x4bc0d1f8,
3394 0x47283c22, 0x4fdc51fe, 0xfab1601f, 0x563529c6, 0x68e1bed0, 0x138a6d85,
3395 0x5cdc514f, 0x3e28b74f, 0x6bf95fe2, 0x075c4e15, 0x9ccad39a, 0xa6df9fb8,
3396 0xd1725378, 0x33223c3e, 0xeab59b8c, 0xca31b966, 0x4f7ef1c7, 0x8898e380,
3397 0x27df5a8b, 0x380bc825, 0xc7f5d627, 0xeddb5ff7, 0x009f0f3f, 0x491e68de,
3398 0x7a8e8a79, 0x7873b641, 0xed7dc593, 0xc44dfa89, 0xe7ec4f1f, 0x8abbe0f7,
3399 0xca8e749c, 0x38ab5e3a, 0xf00ad72f, 0x9adb9da0, 0xbee3e30d, 0xc9d157b8,
3400 0xc49b1e8e, 0xa17c319c, 0xf7a24ea4, 0x3c34b5a7, 0x135ac7bb, 0xa7819df0,
3401 0x1f552ed7, 0x97fc2c07, 0x978a5bfe, 0x5fdff0c7, 0x6bdff1e3, 0x1ce973c8,
3402 0x2d7bd8fe, 0xbfbe5495, 0xc8d78567, 0xdb6677af, 0xc04bed4c, 0xa371e0b7,
3403 0x032a1cef, 0x50311cd6, 0xf1870607, 0x71cf513a, 0x74e22e7f, 0x714fb60e,
3404 0x55bca77f, 0xc39d3aa1, 0xebfcef83, 0xf74f6a34, 0xcea1d4d9, 0xf6aa3f07,
3405 0xb0e98d4e, 0x4bd59f3e, 0x6f00ddd3, 0x7e01f749, 0x9d33a61e, 0xf88b5eff,
3406 0x8def0ade, 0x1bf74e1e, 0x29953a3d, 0xc23ffcc7, 0xece83fdf, 0x1c62f24e,
3407 0xfc5873b7, 0xcc7883df, 0x742fe46d, 0x28c8fd88, 0x4fa44bed, 0xff51ebe5,
3408 0x8ff264ee, 0x99a7e286, 0xb16177df, 0xc1ee0637, 0x77642250, 0xc3bb0ad4,
3409 0x2e64bf18, 0xf287aff3, 0xeed624d5, 0xca70fb04, 0x15dff8c0, 0x47802dfb,
3410 0x9f96fb80, 0x4ffb455d, 0xc2af7f46, 0x33ed84b2, 0x92c5a232, 0x13fc097c,
3411 0xcefba666, 0x42d19cea, 0xd97b1fdc, 0xf88e9816, 0xcd16386e, 0x1be77ac0,
3412 0xbc1ec927, 0x72ee1e10, 0x7b9a7d73, 0x479f6195, 0xeb38d8d4, 0xe7a5edd2,
3413 0x8b570f3d, 0xfd1890f1, 0x72b78836, 0x7e90ebc2, 0xe8af3fa1, 0xe92be31f,
3414 0x3ae9f12d, 0x2c919f48, 0xf47cfc38, 0x89c161c9, 0x22a12e9c, 0xe7dc7f4e,
3415 0x5d937983, 0xf59b741f, 0x8afeffc9, 0x130d37cc, 0xd29f80d1, 0xbef3c4a1,
3416 0xde2cef78, 0xe3c4bb8f, 0x693fad35, 0x1d457b0a, 0x4987c316, 0xfa84e82c,
3417 0x4be88e2d, 0x7518ff68, 0x0e2dfde3, 0xcfec69e0, 0x90c8e5c9, 0xf1b9dadf,
3418 0xedc736e5, 0xc74df9e1, 0xf7dc1e22, 0x03e38e98, 0xbfc33bbe, 0x3ac77ba7,
3419 0x3f8664bb, 0x6e62309d, 0x83680e40, 0x0fda1a74, 0xfc86abd7, 0x95793983,
3420 0xed3fc85b, 0xfee32ee3, 0x8c67a1b5, 0x6b725eef, 0x8b8fa697, 0x7af39c86,
3421 0xe408e509, 0xcb2e10ea, 0xbdf8cb39, 0x5ee2b577, 0x0f711e9b, 0xdfc207e2,
3422 0xaff73a60, 0x3eb07b8d, 0xf7c81c28, 0xd6af3f23, 0xde0effe5, 0xca8ec343,
3423 0x27fa6f94, 0xfdc29fdd, 0xd4bfb343, 0x31b9ee23, 0x66b6a5fc, 0x36736f71,
3424 0x4936e7e7, 0xf6167fba, 0xf74a363b, 0xf0646718, 0xa738d3f5, 0xf4a332c7,
3425 0x1f065a7b, 0x7fb3e225, 0x7a80f211, 0x8f97182f, 0xe32fe255, 0xeeb007f9,
3426 0xb5ec6305, 0xd0151ff9, 0x98079bb9, 0x0f97e28f, 0x60b327b4, 0x5f3b5e0c,
3427 0x732f9f88, 0x29db8c42, 0x456679ee, 0x7c835e7c, 0xb9d1e7ce, 0x0fdc3e3c,
3428 0xe8fe70a7, 0x7779f714, 0xc464fe2a, 0xe175a253, 0xf65e80c4, 0x2b1f2327,
3429 0x99bc1c5f, 0xc79af5c6, 0xfbf457bd, 0xe2cabfb3, 0x8f0004f7, 0x7b607f42,
3430 0x1762c7a7, 0xf0feb25d, 0x419bd69b, 0xbd234fbc, 0x43fae972, 0x48fe80bf,
3431 0xf2c2fa23, 0xe2bb41ee, 0x57bf30c5, 0xb6c3c5ed, 0xd0e3eb19, 0xe5c840ad,
3432 0xdd0ae995, 0x84557643, 0xda89fbaf, 0xf7130c65, 0x5a3c0b0a, 0x8fcb4be1,
3433 0x08b71fcf, 0xf196d43a, 0x9ef1917b, 0x942f9c76, 0xafe83e39, 0xd20b4ca7,
3434 0xbc8bbff3, 0xdad17187, 0xfe2f0e1d, 0x0ecf524e, 0x85ea1557, 0xaa8e1d9e,
3435 0xfa50daf5, 0x9bf42df9, 0xff8cec2c, 0x64bffae9, 0x2fe27fae, 0x4ba01f71,
3436 0xad1c7ba6, 0x76e93dfd, 0xfa0377d3, 0xe5dd813b, 0x2d33fa10, 0x9ec5d399,
3437 0xab4dd7c7, 0xf023dd5c, 0x67c08f76, 0x1e57b89a, 0xae2721d6, 0x39bb4643,
3438 0x0094fde2, 0xef3f7b8b, 0xfa570863, 0xecf03ae0, 0xfbf632b2, 0x7d3bf8e1,
3439 0x742b8a41, 0x839236fe, 0xf294f6fd, 0xfbf58138, 0x8c67c162, 0xc9e8ed99,
3440 0xfd12bcd3, 0xd258611e, 0x807edf71, 0x4f7e61de, 0xb2770af0, 0xc5a2cfb0,
3441 0xf73f92f7, 0x48a3f524, 0x0f1c50af, 0x0dbf366c, 0x0a7e88f3, 0x9e4c5b76,
3442 0xbd16bde6, 0xbe678563, 0x13b7cf9b, 0xa3f637f5, 0xdde38b45, 0x5bac60ff,
3443 0x86d3bcc6, 0x49e0e59b, 0x26c71f0f, 0x25974bc6, 0x6eba0f1a, 0xebe30c77,
3444 0xe60bcf31, 0x479e127a, 0xc80b39e8, 0xfaee00e3, 0xfc6fc5fb, 0x59ce7888,
3445 0x13d2b03d, 0x5da00763, 0xb095eb4e, 0xc6553bc3, 0x5d844bf7, 0x8274fa88,
3446 0x90770b16, 0x6d974906, 0xf12b5f5c, 0x43cc35f5, 0x9b897efc, 0x2fb419fa,
3447 0x4fb11db8, 0x389d6bcc, 0x8daafa3f, 0x21bd92b5, 0xe9c864f0, 0x6e9c8b4e,
3448 0xec357cf5, 0x77e275b4, 0xf17e912d, 0x614ae1f4, 0xf31c95af, 0x95bcc78f,
3449 0x1f342acb, 0xdd25a1fa, 0x9e600fb3, 0xfc1ee14e, 0x39419a61, 0x8cfc142e,
3450 0xc18dcdfd, 0x6e3cefdf, 0xe6f7dd93, 0x857f0457, 0x7cc0d8c7, 0xebd18def,
3451 0x7ae1eeff, 0x2dfc1d2b, 0x5fd38394, 0x785ebd11, 0x9e00e2ac, 0xba05aac3,
3452 0xf830caa3, 0x6f3c33a3, 0xe1ed0bb9, 0xf687cc63, 0x9e786f74, 0x47f01c6d,
3453 0x3f6e1aef, 0xd5f9e80e, 0x97a05f1c, 0x2f97a8c3, 0x2e4fe63b, 0xc296ba82,
3454 0x7365eef5, 0x2967bf19, 0x5fa10eec, 0xf489e86d, 0xe2a7fadb, 0x727d6f3e,
3455 0xe62bb363, 0x2efb40f9, 0xa83b9f68, 0xdf516a6f, 0xf3db1378, 0x79925323,
3456 0xc71e7b3e, 0xe664f4cb, 0xaf3c0174, 0xdc6506e6, 0xb2f57cc7, 0xaf7809dc,
3457 0x40a4a1fa, 0x7ef812d1, 0x0e3e0cf2, 0x2e8472eb, 0x47878dcb, 0x4433afae,
3458 0xe44328dc, 0xf124676f, 0xe70a4572, 0x979d24f7, 0x1f9ce9f7, 0xe3f13c32,
3459 0xbb44cb4c, 0x3bd71b3e, 0xb7c6978f, 0x914bae4b, 0x8b3ced2e, 0xdfc6b24f,
3460 0x17494baf, 0x06db6af7, 0x3fc1b5f5, 0xc677c427, 0xfc6265f8, 0x89986745,
3461 0x8d29167f, 0xce8b37c4, 0x8637c428, 0x3fe2245c, 0x1aeeff63, 0x14c6e047,
3462 0x9fa3f79c, 0x209c6315, 0xdf0f6577, 0xdfdfc237, 0x7cb136b9, 0x4181eb18,
3463 0x9df3d06f, 0x3d00cf18, 0xad0a693f, 0xfc8bcf43, 0x31a72e53, 0xf08ffa76,
3464 0xbb3b1df7, 0x8e6bccaf, 0x7ac0eba1, 0x8cfee3e9, 0x85195d75, 0x89e9c049,
3465 0x7298d5e7, 0xcaedfaa9, 0xf1787604, 0x5e1da97f, 0xe4813dd2, 0x578101f6,
3466 0xc466be23, 0x7897f0b1, 0x8ab3bdb9, 0x1a7931f0, 0xffc06f97, 0x22ff8156,
3467 0x1a7fff8e, 0x643dffc0, 0x79707427, 0x4bd688c9, 0xf45f24f9, 0x453bf19d,
3468 0xa0df27b9, 0x293dce7c, 0xa9df7fdc, 0xbe409ffb, 0xbbf2255c, 0xa888cf27,
3469 0x407b58de, 0x2ad17efc, 0x1af9c0fb, 0x591bc7ca, 0x0ecdfbcb, 0x189497ef,
3470 0x8596d1f9, 0xf9802cc7, 0xf9f15767, 0x9bb14dac, 0x5875a7d6, 0x485f2e87,
3471 0xbb2dfae1, 0x6015222a, 0x4a376b7f, 0x1237f40a, 0xf809877f, 0x0b236466,
3472 0xd0fefec5, 0x4f1f1f48, 0x07a485f3, 0xd3e7068a, 0xa4559b6e, 0xcf695e83,
3473 0xa0b5f648, 0x3606a4c8, 0xbed79f23, 0xf2fca11b, 0x2b76efc9, 0x9e5fc7e8,
3474 0xcf82dfea, 0x6578f98d, 0xbefd247d, 0xce1cbbf9, 0x32f7610e, 0x71e1cd16,
3475 0xfe0427ff, 0x887b0bd7, 0x23dfa61d, 0x94fdb8d2, 0xe9ac7cb1, 0xff0ce777,
3476 0xfa73fd07, 0xb599693d, 0x70a78a33, 0xbcb196fd, 0x834bec90, 0x57e7a61f,
3477 0xd3e7c46c, 0x01315c47, 0x5fc897ef, 0x77f05115, 0xd6ba7fa5, 0x94fef716,
3478 0xc01f4243, 0xcec7f63c, 0x6b7242e3, 0x9d27b3b4, 0x67936f9f, 0x0ddbb7c4,
3479 0x3e7d2c3e, 0x0fba6eed, 0xb86555b1, 0xffe064ef, 0x378ad4f2, 0xe1919e11,
3480 0x46e11275, 0x49c4678c, 0xcfca39f0, 0x9cf9aa07, 0x5cf9425e, 0x82cc63b6,
3481 0x556cf958, 0x2ceb3e89, 0xe86e13bf, 0xae14de8b, 0xad48efc7, 0x71f203f8,
3482 0x1453d77d, 0x91bc59b7, 0x424c1eff, 0xfe245cfc, 0x78cdde60, 0xf80d5dcf,
3483 0xa3ef7817, 0xeec89614, 0xf7c39dad, 0x72b76adf, 0x2aad657e, 0x1b5703dd,
3484 0x7f411ede, 0x7ea3d462, 0xd5a76e1f, 0x2d2edd6c, 0xa8ebc18c, 0x27e510da,
3485 0xe436ee5c, 0x2b19eb89, 0xd8dc63df, 0xc876fc05, 0x9eeaedc5, 0xff07ee52,
3486 0x7ac9083f, 0x0080006b, 0x00000000, 0x00088b1f, 0x00000000, 0x7dd5ff00,
3487 0xd5947c79, 0x6779f0b9, 0xcc93324f, 0x2133df64, 0x61262201, 0x01161212,
3488 0xa0084933, 0x24584e08, 0x81ec36c8, 0x8bf628ac, 0x0c197e95, 0x6f62e452,
3489 0xb90556ac, 0xda544076, 0x1a080962, 0x88b0e834, 0x148d6ad0, 0x43b05b05,
3490 0x921088a5, 0x6f16b629, 0x79e7bd69, 0x799939ce, 0xf8b0ccdf, 0xabbf7ed1,
3491 0x9cce1c7f, 0xf3cf6cf7, 0x273f679c, 0x2d675a5d, 0x2ba42229, 0xcae6c229,
3492 0x9dbde424, 0x91488ee3, 0xe9769884, 0x55ae503d, 0xd034496d, 0x7483b5f6,
3493 0x4eda16b6, 0x62909b88, 0x8e35a242, 0x12cfd0dd, 0x92adb26b, 0x49eab108,
3494 0xc848d9a1, 0xeec4f1b0, 0xf0b7e5a6, 0xafad095f, 0x425cf5a4, 0xc1d334ee,
3495 0x293fa0e2, 0xc9089874, 0x9c709b36, 0xc3211578, 0xac39090b, 0x34432e25,
3496 0x8be0bb21, 0x89ac8411, 0xe399c472, 0xb10f1e60, 0xf196fed1, 0x4258f7f4,
3497 0x5b891a6a, 0x6cd5f3a2, 0xf423adda, 0x76847277, 0x6524224a, 0xd6f384bb,
3498 0x2d2cdf6c, 0x5e67bfa0, 0x075fb5d8, 0xa19357df, 0x7ab3f461, 0xd03b8d89,
3499 0x7180cf62, 0xf61c7b49, 0x9654eb13, 0xbd70b884, 0xe9b7c6c3, 0x0e38b9ac,
3500 0xbff4a3ee, 0x079f4ab6, 0x5666cfec, 0x9b3577e3, 0xa64feeb6, 0x626a91f3,
3501 0xefc56fee, 0xe6c5dff6, 0xff89e8d7, 0x675864fb, 0xa2e75b2e, 0xc4baff5c,
3502 0x2aaad7fe, 0xdfb4cd73, 0x5b08f8da, 0xb38b6d0b, 0x7ac18738, 0x0f3aa78d,
3503 0x61918851, 0xa73a3ca7, 0x77febfd1, 0xd1848475, 0x58c3877e, 0x15b352ff,
3504 0x47563ae1, 0xcebbf85c, 0xe3a56395, 0x8e17ee1d, 0x49b9bde3, 0xa4e01e35,
3505 0x2773270d, 0x3793f9d3, 0xb454956d, 0xe6411b1e, 0x23d6023a, 0x5cc7bbd6,
3506 0x062e6156, 0x1c227438, 0x706936ea, 0x473a15fd, 0xff5cf2f6, 0x2acc5377,
3507 0xf4c0f79c, 0xfa5e74cf, 0x7c6fd3fb, 0x6ba9f884, 0xb06dec95, 0x748fd6de,
3508 0xac00f2d3, 0x7893533f, 0xf6102642, 0x3e7b33df, 0xefe959d2, 0xfc337613,
3509 0xa9deedd5, 0xaecb4059, 0x1a4ba352, 0x303c780c, 0xaeace807, 0x24c24f4d,
3510 0x06739fc0, 0xa74943c0, 0x78841e02, 0x42be81d3, 0xe80233e1, 0x3aaa08a8,
3511 0x67a47f77, 0xfa64e667, 0xdd346b7d, 0x8ee811bf, 0xd91883ed, 0xbec10fef,
3512 0xc7e902e2, 0xafe60cb9, 0x801db708, 0x28515173, 0xac085ad9, 0x23ee18f3,
3513 0x31c19cb6, 0x79953d70, 0x0ab3d6c1, 0x618b89e7, 0x378d12f3, 0xe713e61d,
3514 0xd64d4e2b, 0xff7f4292, 0xfa578e26, 0x4efd87bb, 0xfcf239fa, 0x6de256eb,
3515 0x75c259ab, 0x55a7a107, 0x53dacf80, 0xa7a30f1e, 0x93d00d4e, 0x8fa0bf58,
3516 0xc6693657, 0x56e39e07, 0x6bc70eb3, 0x1d706b35, 0xa27e00cf, 0xe765a968,
3517 0x065599f2, 0x198ff237, 0xf9488f63, 0xebf72f14, 0xabbe503c, 0xed0b5f9a,
3518 0xf9b326ef, 0x0f54aad7, 0xa3ed7d40, 0xf882d246, 0xf0093fb4, 0x123d303c,
3519 0xa55b52f1, 0x38e9eb73, 0xb126bf4f, 0x26e8cbba, 0xceb59ff4, 0x1fa10ba9,
3520 0xbdb30d89, 0x1e737804, 0xf5334dd2, 0x3d2b27a5, 0xfbfa56f6, 0xce763684,
3521 0xdb6a1e04, 0xdd015d18, 0x5c39bc23, 0xcb74f0fd, 0xc7c08dce, 0xa333289a,
3522 0x00274a07, 0x616d9aef, 0x3606b3e6, 0xe804b7d7, 0x37ab22d2, 0xcf9927b4,
3523 0x35ebf8e6, 0x83a00ff0, 0x8648c4ed, 0x75f075d2, 0xee72a1be, 0x19d43c02,
3524 0x14b587bc, 0xfa4f43b5, 0xa2875cf0, 0x5fa69adb, 0x843b380d, 0x47896590,
3525 0x55e714b0, 0x47ed8fdb, 0xc70eff7c, 0xd250cbfb, 0xba730ff1, 0xc36a29a9,
3526 0xb67358f3, 0x71b1cf11, 0xc667e33c, 0x4d7e7253, 0xbf7c13c8, 0x8a9c71eb,
3527 0x6ab1b688, 0x9f8af70a, 0x1216e64a, 0x912e5f9a, 0x8e8da388, 0x83a6c5f7,
3528 0xbe00f391, 0xe355bf57, 0x7ed8c37e, 0xd0fe704f, 0x1c028db5, 0x4751bde9,
3529 0x46f7ec82, 0xe39e23c7, 0x86bde012, 0x7b6bbec3, 0x513f88f9, 0x8b6d717a,
3530 0xbdff01b2, 0xc3ca7db8, 0xeeeba27f, 0x53625ada, 0x38b4d903, 0x717c7e90,
3531 0x942db661, 0x64d5627e, 0xbef144bc, 0xe460edaa, 0xcbefda48, 0xd42e0c5f,
3532 0x7cdd7ed3, 0x535e179d, 0x1e5c0137, 0x9dc7657d, 0x96e35ed0, 0x778f8062,
3533 0x3fe9fb6d, 0x6f57cf81, 0x9308006d, 0xa3bc5f96, 0x54efd2f3, 0xf7eccdee,
3534 0xf866516d, 0x9f17cbee, 0xdde013bc, 0xed82d6d2, 0x8cdc5e17, 0xecaf03f5,
3535 0xe9bffb78, 0x488eb577, 0xe1777c1b, 0x9788fdb5, 0x0ec6a75a, 0xd7450dfb,
3536 0xcfdceccf, 0x849b64f8, 0x31548de7, 0x5ae825fe, 0xaf97efd0, 0x28111dcc,
3537 0x8ed56a1f, 0x4fbe0954, 0x925edbd0, 0x9ca05e50, 0x688c3778, 0xdffee8c2,
3538 0x9681a5a3, 0xfbe5ea15, 0x2ce780b5, 0xd908cfc6, 0xa7b5e42c, 0x6f7efe84,
3539 0x75e6c449, 0x3eaeee70, 0x26e78d98, 0x1d1dd182, 0x31c7c0c7, 0x434438c0,
3540 0x0fbeb0ec, 0xb2db6fd3, 0xa547ce8e, 0x924efb34, 0x47779c70, 0xce05bedf,
3541 0x8c2f58bd, 0xda0f3937, 0x9e41532b, 0xf2d7df88, 0x670dae75, 0xe722edf2,
3542 0xc6653537, 0x7c5e50b5, 0xf00aac35, 0x0ef3af53, 0x72fc00b0, 0x5b471d19,
3543 0x6daebf18, 0x37adae5b, 0xe71c7f62, 0xa0a7ca13, 0xe9e7a3cc, 0xf49f3d1c,
3544 0x0edfadab, 0xc97ef981, 0x193864f8, 0x3e98fb0e, 0xf0048ceb, 0xd46dc88b,
3545 0x7f5c20d6, 0x9629dac1, 0xae87db02, 0x4947e760, 0x2316b9b7, 0xb73b1b87,
3546 0x532bbbc9, 0xf4b7c8ad, 0xfa01feb6, 0xb3b57253, 0xbf7f44c5, 0xa6d3857b,
3547 0xe6f774a6, 0x536363f9, 0x1c95fd68, 0xabd20869, 0xd8f2625a, 0xea79c465,
3548 0xe7c8ca9a, 0x2d23bd74, 0x9bc75cec, 0x428ee689, 0x342a9e3f, 0xf8446344,
3549 0xd5af90fb, 0x7af2e5ad, 0x31275b2b, 0x98a7d2f8, 0x8ef19fb0, 0x683aff68,
3550 0xeb11a33f, 0xf2fbf4be, 0xaaba3e40, 0x755a3e50, 0x820bdeb8, 0xfe57117f,
3551 0x7f3f3cec, 0x139b7aa0, 0x475e35e8, 0x8fe3234b, 0xfbfc7495, 0x9695a52c,
3552 0x1f197f38, 0x7095dace, 0x74ed0f5a, 0x762dd79c, 0x8b6c8efc, 0x50afc991,
3553 0xe39eb07c, 0xbbc919ff, 0xb5cce818, 0x740ccc37, 0x77a77f5d, 0x5c1f2040,
3554 0xb07c616b, 0xf74dd39b, 0xef2f465e, 0xd82e54aa, 0x6e5bbbdf, 0xa8740cdf,
3555 0xff03c794, 0x8695762b, 0x2edc9b8e, 0xc92f0199, 0xf0cb269b, 0x55baf547,
3556 0xe5d657a0, 0x5f814348, 0x7fcbed48, 0xd7ad1b75, 0xbd41bc53, 0x9f3f377e,
3557 0xef854f54, 0x172bdbeb, 0xb1297cc2, 0x12d4d977, 0x536347ea, 0x96bebd68,
3558 0x7ff9c314, 0x37becd26, 0x9121f705, 0x4f20ac97, 0xf20d5ea9, 0xf50f2e34,
3559 0x56e77af1, 0x8e49bfd4, 0x85bdcb8e, 0x27d7afa8, 0xf9c1b4ce, 0xf627c3ea,
3560 0xaf7d42ae, 0x0b6e1ade, 0x684fdfa3, 0xfa601e97, 0xf5b0918e, 0x4fa87648,
3561 0xc3748f70, 0xf8092e7a, 0x39db5288, 0xdeefe607, 0xda2e27a3, 0x71dedefe,
3562 0xbd05cf28, 0xa3d75e98, 0x98d68f5c, 0x2fcbd025, 0xe7c9db36, 0x65982554,
3563 0x05bc22b1, 0x67b66b3c, 0x5c9ce0aa, 0x9ff0ede2, 0x43cb9e35, 0x42dd69fa,
3564 0x2d67d20f, 0xf563dbd7, 0x030782f6, 0x28f427f0, 0x82fc1d25, 0xa6f27fd3,
3565 0x621c1243, 0xaeee7e25, 0xba069e26, 0xa937bbbe, 0xa8f9253c, 0x7c8fdd5f,
3566 0x6c8e957f, 0xb78efa91, 0x8a8bf383, 0xf0014718, 0x46e98ac9, 0xaa7f205b,
3567 0xc2abb708, 0x423cf402, 0xfa2a451c, 0x1378f9dd, 0xd875ffc2, 0xacbd1077,
3568 0x63967fb7, 0x22bbc02b, 0xa7ed0c21, 0xf95d5a7b, 0x5d6d1fa4, 0xe7055e15,
3569 0x2363f292, 0xed334df2, 0xdf8bbf4f, 0xe445f232, 0xd705a4b3, 0x6662d9b5,
3570 0x8a38c4e3, 0x64b5811a, 0x39305639, 0xdb05b266, 0x3f7c7dcf, 0x29cfa607,
3571 0x4c9d0150, 0xf4f4da35, 0x92dfa7bb, 0xb8dd23e6, 0xf384c0a8, 0xec715ce2,
3572 0xd8af662e, 0x5388ee80, 0x7d56fa83, 0x9c1dc3a3, 0xd71d18ae, 0xf40bfd53,
3573 0x88574a70, 0x2676fab7, 0xddb8227f, 0x50227c07, 0x4ae715df, 0xd7e05b9c,
3574 0xde823740, 0xd1bdb9c4, 0xcfcdd9f3, 0x7fdd3747, 0xde9a7d20, 0x6eb97464,
3575 0xda14b595, 0x731055d7, 0xb4aabda0, 0xf870ac83, 0x62fadd68, 0x11c61b84,
3576 0xe2ce2e7c, 0xa8fc0b38, 0x35d1cb7e, 0x2f9cb648, 0xf8f9bfd5, 0x67e96b80,
3577 0xcf1b0d06, 0x07708ee0, 0x82818fd2, 0xa58854db, 0x4473f80b, 0x12df5c93,
3578 0xdcb93fe5, 0x65facef8, 0x7c01a4ae, 0xa8f2fd09, 0x0b4ff9ca, 0x45292fd7,
3579 0xa626f490, 0xaf03c65f, 0x25b07e07, 0x24fc0dc2, 0x77389e3e, 0x97cf5905,
3580 0xbc099cfc, 0x3e233b0a, 0x1c9f7d92, 0x5324f4cd, 0x8b2efb34, 0x0bf60197,
3581 0xcaab079e, 0x43a88679, 0x8fd101cb, 0xc5db0bae, 0x1fed7a7a, 0xfc6f5b03,
3582 0xacb603a3, 0xffa7c00b, 0x0856dd5c, 0xef5ace78, 0xfa37ccd1, 0x48f211e7,
3583 0x7eb03f49, 0x9fb05b90, 0xdfd0dcca, 0x76e7eeb5, 0xcb9e829c, 0x633af9f8,
3584 0xf2ddf821, 0x68eae718, 0x45159f5a, 0xff1431ec, 0x23d1deb3, 0xdf1c913d,
3585 0x6b43b000, 0x8fa5c434, 0xdd6abc06, 0xfe3c00de, 0xfb40f00d, 0x2e0c98f5,
3586 0x2d073d35, 0x68e2ce31, 0x8cab9e3a, 0xc7a03cd8, 0x0bf29f7e, 0x53c49738,
3587 0x81a4fc0c, 0x8e012378, 0x239c982f, 0x757abbe0, 0xa9d43a67, 0xf30f931d,
3588 0xecc11b3c, 0xb551df27, 0xc785207b, 0x47f78365, 0x2e7ae923, 0xb9b2c8af,
3589 0xdfa738e8, 0xdf9efdfc, 0xed2fafd3, 0x19cd22f9, 0x0deb57c0, 0xc626832a,
3590 0x4896ef5f, 0xbe105b55, 0xc99a233b, 0x09dbccd3, 0x68b804e9, 0xaeb7a87c,
3591 0x8027b308, 0xbec567df, 0xe96b84d2, 0xca570df3, 0x9e603b88, 0xfa1fda06,
3592 0x4b195c35, 0x8c8243dc, 0xf903c74b, 0x992570d0, 0x3cd862b8, 0x315437c0,
3593 0xfbf8ce4c, 0xed1713a7, 0xaa455a7f, 0xe7fbad83, 0xbb5f0cd1, 0xac1f1909,
3594 0xd7df077d, 0xfcec7eee, 0x6e4836fa, 0xaf160fb0, 0x14d47930, 0xcfe98ba4,
3595 0x362d2fa0, 0x48aa3cbb, 0x8f943fe0, 0x4e34460d, 0x647b5035, 0xf467971e,
3596 0xa028cd3b, 0xcf199757, 0xc39f93a1, 0x7defed79, 0xc589fe03, 0x4518621a,
3597 0xb06f99c7, 0xbfa14e1d, 0x2638c9ff, 0xc2c4c412, 0x83c4a687, 0xd5984b1c,
3598 0xbd2273a8, 0x7e83318d, 0xea51912a, 0xa5ae236f, 0x8f50690f, 0x74a27a45,
3599 0xac718ba0, 0x3a00ba04, 0xf5983a04, 0xe26be320, 0x5e7e5cfb, 0x59f87495,
3600 0x8ecf7c08, 0xf181cb29, 0x358e512c, 0x5e0fdf48, 0x6ebff192, 0xf3f2fbc9,
3601 0x4dcba740, 0xdf4897b6, 0x70e13ffe, 0xd4e829ef, 0x2e5a2c91, 0xea3a47ff,
3602 0x9def1da3, 0x675d3e04, 0xa0d47a30, 0x76d6ec57, 0x283ec579, 0xd945060e,
3603 0xf073c29f, 0x739651c3, 0x02482694, 0xe3d71dfd, 0x03bf00dc, 0x0363db9d,
3604 0x151adce9, 0xeba2740d, 0x10c38bc5, 0x490bc7ef, 0xd1f1c935, 0x31f11471,
3605 0x01d760df, 0x1dd817dc, 0x5159beb8, 0x0cb3629e, 0x6feab9fe, 0xf871bf6f,
3606 0xf9e7e7af, 0x61d28eb4, 0x83b07390, 0xc31543c3, 0x64e9c6f8, 0xd3a7af46,
3607 0x282ef549, 0xf692d107, 0xd78fdd3b, 0x007d790b, 0xd59e2eff, 0x797e700f,
3608 0xa77d9f3a, 0x3e33e79c, 0x7b18eccf, 0xf68bc007, 0x4f00e8f3, 0x41b9876f,
3609 0xeafca64f, 0x8f13a700, 0x155f9025, 0x1f0006f9, 0xf8a629ec, 0x5759fba2,
3610 0x013f4bea, 0xde9f64fc, 0x7d7ac5bc, 0xd7c27dbc, 0x97e59df5, 0xa1afca8d,
3611 0x49f5f932, 0x885f9334, 0x1d12ba27, 0x11b2abd3, 0xea17483f, 0x5bcfc71b,
3612 0xf4ee0c61, 0x51a3789c, 0x1cf2794e, 0xaffd7c01, 0x8f826e1c, 0xe3970e9c,
3613 0xf7f7c5d1, 0xeb473f25, 0xde4ccda3, 0x30e97cd9, 0xe0e8e9ce, 0xc7ed5f78,
3614 0x239e3747, 0x0c4e6fbd, 0xa8fbb7a5, 0x442ba0be, 0xf587ac7c, 0x734bb1f4,
3615 0x73857f3d, 0x8980f0dc, 0x22bbdc80, 0xa1f22be6, 0x97ca937f, 0x4e8f0674,
3616 0x87afd41d, 0x27d1f01f, 0xd4951a51, 0xd5a02274, 0x71c5621c, 0x9e3328c8,
3617 0x3e5eb0b3, 0xf38989a2, 0xef3947c3, 0xc8af8e29, 0x0e734918, 0x36236af0,
3618 0xa3e737e8, 0x29b34caf, 0x1b325c9d, 0xcf2a2a5c, 0xd19caaae, 0x79efe031,
3619 0xbbea28f8, 0x019e74a7, 0xed20c6ad, 0xcf0bcf3a, 0xb9f6fe4a, 0x74bb533f,
3620 0xeeef1cf4, 0x74c9faec, 0xa7677fba, 0xd8e706da, 0x1faff2b9, 0xa5bd030c,
3621 0x4feb6b53, 0xd7aeae50, 0x991a3ec0, 0x254a767e, 0xefc5ff87, 0xc187edc9,
3622 0x540f0c31, 0x133a409f, 0x5854e0fc, 0xeba13e64, 0xfd3c4259, 0x51e7ee81,
3623 0xef4a17c3, 0x10f725f2, 0x181627ca, 0x7dfd22a7, 0xe85dc0f1, 0x9c485e6f,
3624 0xb9e62fc8, 0xe40c7fb4, 0xcad60ba3, 0xe55a8beb, 0xc9cf25f5, 0xdffebdeb,
3625 0x4effb972, 0x98635394, 0x0ba8ba5c, 0x863e3ede, 0x9777e3d1, 0xee5083c7,
3626 0xf9c795f6, 0xe395a728, 0xaee5c3de, 0x1e42cb90, 0x84315c37, 0xe388c718,
3627 0x7c1c5c5c, 0xf5f1f7fd, 0xa3315c37, 0x3fdbef7c, 0xd53ae516, 0x813bf0c4,
3628 0x892b86cf, 0x0ba8bbf8, 0x2fdfd07d, 0x8ca3c715, 0xc22e7cdf, 0xdf85fe7f,
3629 0x19efd057, 0xd0921889, 0xfb927b5e, 0xe0f9cc6b, 0xf2033a87, 0x39d9e29d,
3630 0xa5edbc8e, 0x48f79c4b, 0x3f4d00d2, 0xf72b7d3f, 0x82e0e941, 0xd59f8037,
3631 0x716298c6, 0x3064c1de, 0x73e82bcc, 0x5115c3ce, 0xb0ffdf20, 0x50213cb2,
3632 0x6bf5eaff, 0x447d98e8, 0xaf265188, 0xcd9e4288, 0x2bf2a76b, 0x0188f51f,
3633 0xef9f9740, 0xb9f4819b, 0x81e2d890, 0xe9f67b6e, 0xf7ffd1d3, 0x5898e51d,
3634 0x3cd714cf, 0xa92fd32d, 0x65e7a090, 0x4a7f9f32, 0x5467d307, 0xf516bb06,
3635 0x9ab13b15, 0x64a4d1e3, 0x130a96f2, 0x168fad0d, 0x5a1e2075, 0x2337c51f,
3636 0xfeba7f41, 0xf324bcd1, 0x9e70899d, 0x1aaf30f4, 0x113b90d8, 0x361196ca,
3637 0x9225942b, 0xc1d6c343, 0x34963cf0, 0x2af7c2a6, 0xf4cd5783, 0x7882ba25,
3638 0x63e62fe8, 0xafaf1375, 0xce797a9e, 0x68ddf822, 0xe3af73c2, 0xf05578eb,
3639 0xc031032f, 0xcf46f5be, 0xe24f1897, 0x8accaba5, 0x1faba876, 0x9c3fbb41,
3640 0xd79811b4, 0x82e4bc68, 0x59899acd, 0xf9987a82, 0x0211e7b2, 0x52e8cd7c,
3641 0xb6be460d, 0xf49af913, 0x7be062fe, 0x03e68f94, 0xaed90d1f, 0x2efea0f1,
3642 0x5f3452f8, 0x4be70b5f, 0x21c18449, 0xbe71d886, 0x23169b1f, 0xae338a5f,
3643 0x86ffa090, 0x97c8f1c8, 0xb4f001e2, 0x46bc663d, 0x1ce267c6, 0x95427af2,
3644 0x94e49ebc, 0x14e40dd7, 0xe3c903ca, 0x0636fc48, 0xf01c91ed, 0xd8cb683b,
3645 0xce1e99f9, 0xeb0dd5d6, 0x1139fba3, 0x937ffaa3, 0xbb7245fb, 0x475a3eb5,
3646 0x4f150fd0, 0xa8c1e62d, 0x61889c07, 0x2e67c07a, 0x90fb5768, 0xfee09eff,
3647 0x1de3a983, 0xdf8a1a15, 0x07c972fb, 0x8f9e5a76, 0xef869e73, 0xac691c67,
3648 0xaaf5a5ab, 0x879e49f7, 0xe6250596, 0x9f14ed9a, 0x6c9b666b, 0x1afad28f,
3649 0x576d2313, 0x22f51e9c, 0xb698f202, 0xa225566f, 0xfc01a3ff, 0x6bff74ad,
3650 0x3a006f40, 0x5ed04fe8, 0x1ac87aa6, 0x79b7ed03, 0xcebcd99d, 0xdf2a7e0a,
3651 0xfa07f058, 0x16f31116, 0x5c3ce412, 0xe28ce7a5, 0x53a845f5, 0xbe9c4a3c,
3652 0xe15befc4, 0x2f562cf7, 0x1e760a19, 0x83ab2ffb, 0xcff02832, 0xfddce8e4,
3653 0xa51d3d61, 0xcf5a38da, 0x7f43631a, 0x617ce131, 0x9f879898, 0x73fe91bb,
3654 0xbc05ed80, 0x64f1dd9e, 0x978c3c45, 0xca7e504b, 0xd62c0dce, 0xca187f4c,
3655 0x73c0edcc, 0xfff1077b, 0xfb95e307, 0x8dbc47c7, 0xceef6de1, 0x61d8f166,
3656 0x387ecf1a, 0x597923d7, 0x8774cbc0, 0xa511fe54, 0xed8342d7, 0x802b1ee0,
3657 0x7d86a1d4, 0xde3f350f, 0x708ff302, 0x7c03147c, 0xf281946c, 0x0cb65a03,
3658 0x59ccd9b7, 0xf8156fb8, 0x42b5ba97, 0x40a3d91e, 0x92ad4dae, 0x7d00ff5c,
3659 0xe11a8c60, 0xe53197f3, 0x7794d751, 0x3ab22a4d, 0xd6acce50, 0xf3f7fcc9,
3660 0x65ff9963, 0xecd8ec5c, 0x2c079458, 0x962837de, 0xdba009f2, 0x7c03921c,
3661 0xe71ce022, 0xa55d77c3, 0xce750ebf, 0x9cfcede5, 0xd10fb34f, 0xcfcb3ea2,
3662 0x8eabe0bb, 0x669e7670, 0x74069210, 0x22349532, 0xba563dff, 0x7dfbcf14,
3663 0x7805a5c4, 0xe0c65a7d, 0x653dd62c, 0x98af5cbc, 0xa7d790e6, 0x0ef52957,
3664 0x7fbc7b3a, 0x794e19de, 0x3fa164fb, 0x8feb978e, 0x55cffeb3, 0x84b5ca0b,
3665 0xcdbeeb97, 0x54f83f00, 0x03f81c6d, 0xfa33243b, 0x8c243bc1, 0x195434fb,
3666 0x6c6fe0dc, 0x5bf16768, 0xefd05ab2, 0x7e80c7bc, 0x31da5653, 0xbedf571e,
3667 0x80145a53, 0xb75a94af, 0x207cfc04, 0xc8275185, 0x9c77ae2f, 0x83f7bad0,
3668 0x52c4fcbf, 0x9e74e24a, 0xe1df3c83, 0x143be410, 0x34cee9fa, 0x28fff987,
3669 0x3c7fa315, 0x03611cd5, 0xaaad79bd, 0x6b85fd10, 0xbf324d23, 0xf655baee,
3670 0xf84ef80a, 0xcafe4509, 0x6c693d74, 0x43a7fe63, 0xcc8d8cc8, 0x76e6e43f,
3671 0xd32c7672, 0x6afb68cb, 0xce294ff4, 0x410c5c6d, 0x333711b9, 0x5580fd07,
3672 0xe045051d, 0x07f2a587, 0xb1d9d3fd, 0xe55fec56, 0xd5ff402c, 0x1819c6dd,
3673 0xd8e86817, 0xf46859ac, 0x82c3cfd3, 0x044822ee, 0x5faf5dd0, 0xfd1e9768,
3674 0x8e555742, 0xd57d001f, 0x44f93cea, 0x7bf8974e, 0x84b2f928, 0xe65b5de3,
3675 0xc288b198, 0x9d03e7a5, 0xaa3bec0d, 0x5ebe2040, 0xfe416bdb, 0x904c99a7,
3676 0x252eafcf, 0x367b27c8, 0x17c8bf33, 0x687bea96, 0xb52d590b, 0x8eee1f22,
3677 0x5ff08b1e, 0x7a843c66, 0x4a26f548, 0x7e7c014f, 0xbd7956d9, 0xb2fb3086,
3678 0xba1f7b76, 0xf8247e44, 0x796efd55, 0xe4cd923f, 0xb9c38db7, 0x42d1f380,
3679 0x054a6d87, 0x96cabd2c, 0x6244ecc5, 0xfc5e3e07, 0x0bfb8ebe, 0x85cf9967,
3680 0x597b8b01, 0xd41e96ba, 0x66af3a63, 0xcdf198e7, 0x928f3e62, 0xfd73179f,
3681 0x9d0d4ee7, 0xcfafd0a7, 0x3f561314, 0x2750eaa4, 0x2debfcaa, 0x1e84fde2,
3682 0xc0a9f825, 0x4270e957, 0x3b3a5386, 0x8fddf020, 0xd37c03f4, 0x25ce91f1,
3683 0xc68954c8, 0xef605df1, 0x51f3e48c, 0x5d01707a, 0x370654b9, 0xa91aefd0,
3684 0x0188e511, 0xae5a65f4, 0x57c89c93, 0xa976a8df, 0x4823de01, 0x327b94e3,
3685 0x4676bf81, 0x9d289c00, 0x9fa40e1c, 0xdf49e216, 0x08e8c929, 0xbf2cbbdb,
3686 0x82474a0e, 0x653e7bef, 0xba04c0fa, 0x02a71863, 0x3cb40902, 0x3a412d24,
3687 0x5a7c6719, 0xad7ffd03, 0x78d3f662, 0xfac0d6e2, 0xfc72cc2a, 0xd7944b8f,
3688 0xa1f6b2ef, 0xdbff8c0f, 0xe4273c39, 0x82eddbc8, 0xdf39116f, 0x995724ca,
3689 0xe1f8fb7d, 0x8eaec087, 0x10392268, 0x9d1aa3df, 0xf8907fad, 0x2dec4f49,
3690 0xc4f7c3f7, 0xf7c3f106, 0xafbeb968, 0xc3faafa0, 0x27ace617, 0xe7143a7e,
3691 0xa8d20ee1, 0x9370a44e, 0x8ef161de, 0x28fe803b, 0x90370c3d, 0x486fd05c,
3692 0x8973f311, 0x6de821f3, 0xc545af28, 0x20cafa71, 0xa35f4019, 0xbfd0c3db,
3693 0x19d00779, 0x3e02dba5, 0x42df90ae, 0xde196f2f, 0xa532ae87, 0x78e3942c,
3694 0x1f1c84de, 0x7f9ed922, 0x72f41324, 0x01e5ea17, 0x87131474, 0x11d288fc,
3695 0x723ecf9e, 0xa0aede52, 0xe3ef8133, 0x252cdf5c, 0x535f488d, 0x3d2c5655,
3696 0x2f4ecc95, 0x40d54e37, 0x3326f7ff, 0x74031b3a, 0xcbdf0598, 0x20dca4e9,
3697 0x90e92baf, 0x9c0aa8ce, 0xa1974957, 0xe8032ce8, 0x98c7c84c, 0xa8d9d3eb,
3698 0x674e5bb8, 0x826ee2a3, 0xdadf04ce, 0x372e6619, 0x96aedc82, 0xf90c0e50,
3699 0xea05bb20, 0x5132eb03, 0xb169dccf, 0x46f6c41d, 0x69d45ed6, 0x42de4357,
3700 0x9ede0ad6, 0x7a8728e9, 0xa76d1343, 0x671f1743, 0x2bd90d79, 0xa3c17b59,
3701 0xe04d078d, 0xfeb172c7, 0x46b97e6f, 0xdddb491d, 0xd2ff786b, 0x37a872d6,
3702 0xbffd65ac, 0x60c87880, 0xb77287c8, 0xadb7efc0, 0xb331b4cf, 0x25b7e994,
3703 0xa53bbf7c, 0x5fb1075d, 0xe4b7eb2b, 0xa09c21b0, 0xd6f4ccfd, 0x4b3ef93b,
3704 0xc67db136, 0x78f77e7e, 0x458ba52b, 0x5fea173e, 0x43b554e7, 0xb085af91,
3705 0xd6a54b3f, 0x51c72854, 0xdda50bb6, 0xeeab5b60, 0x5b61e2c7, 0x714d14e8,
3706 0xe2217fcc, 0xaeaf1048, 0x9a67d00c, 0x245d98e2, 0x268f8bbe, 0x8d911fa8,
3707 0x4437b426, 0x2cf3cb9c, 0x850ec091, 0x50bf423d, 0x5971af71, 0x8c2fa88d,
3708 0x2ef110cb, 0x9d3e66af, 0xafdbe0b7, 0xaff306c6, 0x3d31c734, 0xbf8f3ce5,
3709 0xddabdf8b, 0x13bf2e2c, 0xe0192488, 0x7057f87a, 0x3c42775e, 0x1727098b,
3710 0x65780e19, 0x727e27f5, 0x6a5add60, 0x35512fbc, 0xcc205c6a, 0x23cc25d2,
3711 0x3c49d49a, 0xd77d9151, 0x3c434e3f, 0x8407963a, 0xa2dc5feb, 0xc2203cc3,
3712 0xc134d9f9, 0xc7f5469e, 0xe3953df3, 0x4fe0a369, 0xe010c843, 0xde38d34f,
3713 0x3d5033ee, 0xab72e518, 0x5e37c156, 0x21b1be40, 0x6f2dfea4, 0x6a95f057,
3714 0xae62ef3e, 0x3e252f77, 0x49ce4bd4, 0x6fcf2c6e, 0x8d777a60, 0x35ea38f1,
3715 0x9e991b3d, 0xa8bc4b59, 0xcb752cf7, 0x36cd42f9, 0x4daebd79, 0x97686f5e,
3716 0x5cf27bd7, 0x86cf4f38, 0x4fe0a1ba, 0x03ee7eab, 0x0b56dff4, 0xf396e2fe,
3717 0x32564217, 0x20ecf2fe, 0xed28e7f4, 0xeef76a70, 0xa1f8c38b, 0xe82d6679,
3718 0x58227305, 0x98da82be, 0x64c07c87, 0x14383b40, 0x39da501f, 0x8320ef42,
3719 0x2a0f9f82, 0xcf000c69, 0xc6777800, 0x921edb5d, 0x21f02bb7, 0x39fb91ec,
3720 0x7c50a63e, 0x93bf3cc3, 0x1cf768ec, 0x31f0ca5b, 0xe902b8cd, 0x0c65d3e1,
3721 0xba2ec21f, 0xaec83b79, 0x90762efe, 0xce2e5fd2, 0xb09a7755, 0x8768ad4f,
3722 0x29800036, 0xf37bae9f, 0x9fa00bc4, 0x358eef8a, 0xc04d3893, 0x2a563c79,
3723 0x9e4e8ff7, 0xe4287a70, 0x2b0f6e3b, 0x93e00bfb, 0xffa1c474, 0xd8412eb0,
3724 0xe9fc6c45, 0xf2eaff3c, 0xe8a8ccca, 0x89bdd96b, 0x009a619d, 0xc68f6cff,
3725 0x4e760917, 0xe70955cf, 0x4825ba85, 0xffdfc91c, 0x87c41878, 0xf9dfcefb,
3726 0x3f03dfbd, 0xe302217b, 0x3257977f, 0xa6f2ef7b, 0x7c079881, 0x0549c791,
3727 0xde1c961c, 0xce17b6f6, 0x1c31d35b, 0x7f7246af, 0x1db687bd, 0xe2633bd5,
3728 0x3caa0e41, 0x2c57463a, 0x1df6219e, 0x42e96fda, 0xc03ba6fe, 0x0a4face4,
3729 0xfa4ebcc7, 0xb8c080fb, 0xe302524e, 0x7e0e42c3, 0x2d6afdcc, 0x17d8a5bd,
3730 0xc4b42bf3, 0x3d60b3d8, 0xc1bac31f, 0x1691f43f, 0xbbf835f9, 0xa548ce21,
3731 0xee89492e, 0xa3881ebb, 0x3881bd6f, 0xc99e2dba, 0xf694a583, 0x62cd3f30,
3732 0xcef9802f, 0x79e1b8f3, 0x1f3a771e, 0x2350e2c9, 0x5f1f19e3, 0xe44dfbca,
3733 0xf110f9e5, 0xd9ddf16e, 0x35618366, 0x9b1feb5d, 0x36756189, 0xf567f125,
3734 0x339f988d, 0x67abed8b, 0x39f305af, 0xf8aabf45, 0x8eb0a5d2, 0x18c71621,
3735 0x9eb61728, 0xa9fa05d1, 0xa83f607b, 0xf57db04f, 0xcc52b184, 0xb95f1557,
3736 0x3ce01e34, 0xec788bc3, 0x75108fad, 0x33df8e07, 0xc24ff19a, 0xfc7510fd,
3737 0x5b8a85fc, 0xa55e2f5d, 0xe6cefb8c, 0xefb889e3, 0x9914362c, 0x73bee3cd,
3738 0x0a4d640c, 0x91db9f6d, 0x48d5ecc0, 0xdc5900d7, 0x537115d7, 0x87417771,
3739 0xb8fe693d, 0x889bc6e9, 0xfe20fe9b, 0x7f4dc796, 0x6e241f10, 0xbfa78caa,
3740 0xb6417a0e, 0x980f0f1f, 0xd42adc19, 0xcfe0e5b5, 0x6090bcbc, 0xe901731e,
3741 0xd028ecf7, 0x89688eb3, 0x137c8adb, 0xe1ebe3f5, 0x22a1ce2d, 0x39df9956,
3742 0xd603589c, 0x968ce49f, 0x0ee351d5, 0xa94c0fc8, 0x4ff5964e, 0xfb27ec6b,
3743 0x9069a33e, 0x55d33dac, 0xad67ab28, 0x7df643bd, 0x5932d6ff, 0x7773e07d,
3744 0xcdbfbecb, 0xbf56593d, 0x7e40ff0c, 0x767e46a6, 0x65fbb6fb, 0x1d1c97fd,
3745 0xddca7e82, 0x9712fe5c, 0x287733bd, 0xfac0a373, 0xcbe6daf3, 0xc91e23c6,
3746 0x45f6d123, 0x23174f1c, 0x85893dd9, 0x3f9fcc9d, 0x6c997db8, 0x2d751afc,
3747 0x47194fe2, 0xc3be242c, 0x96ea3f98, 0x37d21e6c, 0x7db4b8ae, 0x9ebbf633,
3748 0xfafc227e, 0xb14de207, 0x24c91748, 0x92b3d199, 0x70bd8c1e, 0x05197b80,
3749 0xa3b3c064, 0x20f4648a, 0x1b851bc3, 0x6f2ea9fa, 0xd1de6137, 0x700ba392,
3750 0x3944fa3d, 0xe559843d, 0x239110f4, 0x4d9307a7, 0xe1a8ff8e, 0xe12bfc72,
3751 0xe9cbb16d, 0xffe97881, 0xcc7780d7, 0xfcbd3978, 0x1ddce0ab, 0x1c81e3cf,
3752 0xd90e43be, 0x37088c5b, 0xec243f96, 0xa3b73d7b, 0xcfdcac49, 0x7fa7f425,
3753 0x1578f3c6, 0xd5f8471f, 0xb42e48d7, 0x66e37bcb, 0x9ee93dc3, 0x1bcfb04c,
3754 0x38f3f309, 0x41c50954, 0x7bf884fd, 0x80a13f28, 0x67ae54eb, 0xfa3b10d6,
3755 0xfc4117a5, 0x2b67969b, 0x677fa297, 0x1d69f189, 0x9938bff4, 0xc4d563e9,
3756 0x7afdfc8d, 0xdc256ff1, 0x01252f40, 0x1c25547e, 0x63c90ea5, 0xe5c33e02,
3757 0x10e93240, 0xf2c9c072, 0x12fee5f8, 0x00b2f102, 0x5ef4253e, 0x9f80be31,
3758 0x7c625fe0, 0xe059f83d, 0x19f8281c, 0x45e391c9, 0x63815fe9, 0x181a1860,
3759 0xc092b12f, 0xafd28af8, 0x50a7f7e2, 0xa7ce92bb, 0x216cc8ce, 0xcc436f14,
3760 0x15d7f476, 0xf099ce93, 0xa0a7f0bb, 0xd236e17f, 0x29085feb, 0x8f13ae9f,
3761 0xbc92e29d, 0x8df667cf, 0x2eb88ac3, 0xbfe7c305, 0x49479da7, 0xe4f7c456,
3762 0x01c60737, 0x2ff5f51d, 0x45be4eda, 0x7cab51c7, 0x3f7e8131, 0x4f7f5fe1,
3763 0xee7ee2f2, 0x48c7f623, 0x4f519e80, 0xcccec6da, 0x952eff04, 0x3250918b,
3764 0x5769143f, 0xf41ad9ea, 0x4ee8aaff, 0x486bde80, 0xd3329c40, 0x75758edf,
3765 0xe68dfadf, 0xc13afcbb, 0x2cbd9dcc, 0xfe70935f, 0xd0c3ec27, 0x7d7c98f6,
3766 0x330b8c0b, 0x82fbfa25, 0xc0dc75c0, 0x037e453a, 0x7884e3dc, 0x9f2a26c6,
3767 0xb04bcf51, 0x17515ea2, 0x3b13ea7e, 0x99d4567c, 0x36d7a81e, 0x0301a8e8,
3768 0x7aebf8f6, 0x936c9716, 0x4c3fcbeb, 0xa12ef960, 0xa8f3c0e1, 0xf5cc7614,
3769 0x47911df4, 0x16e01135, 0x944b3eb0, 0x9f803fe3, 0x9ef49da4, 0xfefe5493,
3770 0xcc2eea15, 0xaedcbc13, 0xf54efbc6, 0x1fc85da3, 0xf1aaf7ea, 0xe8777508,
3771 0x756f3ef1, 0x93d441fb, 0x03299aba, 0x85c97aa2, 0xe6b33a66, 0xec57f01a,
3772 0x207d9437, 0x4c5e8df2, 0x9f33fce0, 0x2be607e4, 0x8af83e51, 0xdaf60f8c,
3773 0x4a79bdad, 0x93e304af, 0x28dcea15, 0x9bdae7b8, 0xa5f1a287, 0x8fc00e4f,
3774 0x720f1f72, 0x1a37e43b, 0x5d025b47, 0xd4ce99d7, 0x0abc6067, 0x64e1c775,
3775 0xc90acf80, 0x12b47106, 0xa87fbb3d, 0x35b72f57, 0x0375d806, 0x203b521f,
3776 0xc57a795e, 0xbf70d183, 0x503b8c59, 0x393de152, 0xf67d7642, 0x9f8822fd,
3777 0xa3adb2cd, 0x667ad9b5, 0x2f7e6657, 0xcf4593c2, 0x763a3bd7, 0xafdb4b3f,
3778 0x7dfef311, 0xe3fa3516, 0x0c64d562, 0xaf5885d0, 0x7e2857b8, 0x70cefb87,
3779 0x5efc4d7f, 0xf21be2d2, 0x071f2d00, 0xaff62cfa, 0x37dca4af, 0x87e8d1a4,
3780 0x6e9c7d7b, 0xdd45e80d, 0x443f2606, 0x6b31159e, 0x30ad7cf0, 0xaa75f3b0,
3781 0x3d9bb0bf, 0xeabfb026, 0x9851ecc3, 0x9a91f5e7, 0x17f95d80, 0x82ca3db3,
3782 0xdea2b3fb, 0xfaccc2b9, 0xde7cf375, 0xa1969f15, 0x12d7165d, 0x7ce8cf3c,
3783 0x6a9fb302, 0x7964a8af, 0x0f1ab546, 0x5ed50be6, 0x913e61d1, 0x148ffdf8,
3784 0xfe01ae0e, 0xd9f3fcfa, 0x0b5d6163, 0x7c0d6d88, 0x046d60bf, 0x21e80571,
3785 0x8958af22, 0x7c71efff, 0x44345bd7, 0xe7ef1833, 0xddf5ae3a, 0x0754ff5b,
3786 0x9d12efbd, 0x5c71cec8, 0xa5ebcb39, 0xe1c60576, 0x2585df94, 0x6cfc8a4a,
3787 0xecafde2f, 0x5bdb07cd, 0x61ae409a, 0xb15fd7e7, 0xebb3f2cb, 0x57e87f69,
3788 0x228c657f, 0x4b8f9b3f, 0xfd1ab3c7, 0xe0a16079, 0x6604bdff, 0x9e43d4df,
3789 0xdfc090d7, 0xe7f8fd19, 0x5b79e589, 0x7f3848de, 0xe3576f3f, 0x1f9fe3fd,
3790 0x12df8d51, 0x12c3dd64, 0xc506dc19, 0xdc5cf069, 0xcdf621ee, 0xdf17e641,
3791 0xe205fb89, 0x7d729c7e, 0x73bccbbb, 0xc6c3fd60, 0x72aeff30, 0xec89419c,
3792 0xddeeb13b, 0xf51f0cd1, 0x607c536f, 0x9fcb08fe, 0x5ded1ddd, 0x2cc0fc8c,
3793 0x8e7cf3c7, 0x7b77dde7, 0xcbbef1d3, 0x0e7ecc5d, 0xcd570f45, 0x4f8007ce,
3794 0x42374ed4, 0xaa19192e, 0x01cc9469, 0xf47aebe7, 0x4abb87e0, 0x70bed786,
3795 0xc57e21d7, 0xffdf42b8, 0xc63539f2, 0xc63cbff1, 0x1bb12dcf, 0xf77c80a5,
3796 0xebf3092f, 0xa12ad97f, 0x49df3f9e, 0x2fe51348, 0xa0d6b6f3, 0xa5f8b85e,
3797 0x03629821, 0x7ca4afbf, 0x21225e64, 0xfe72d277, 0x775c796a, 0x7e3efae1,
3798 0x7f281239, 0x94469117, 0x969f8b17, 0xeb26abf7, 0x837a0cff, 0x3e8cde32,
3799 0xcf176a4f, 0xf77ae44e, 0xf8143250, 0x7d2f03fd, 0x86b48ba5, 0x94f3ffa6,
3800 0x806b669f, 0xecb01aaf, 0xb963366a, 0x28bed13c, 0x39a5c291, 0x089d59d1,
3801 0x188f8cfe, 0x5ed72e3c, 0x2e00f266, 0x7e008e4f, 0xd33ca12d, 0xd8f164cf,
3802 0x723dc21f, 0x9ebd0f0a, 0xd47575c9, 0x7093c9ca, 0xff846e95, 0x8e79af30,
3803 0x2d8de505, 0xf63de811, 0x63c6e317, 0x222fd75e, 0x75bf00ec, 0xc197eea5,
3804 0x556eb08f, 0x0d71fa38, 0xce0f167a, 0x82aa5eda, 0xedb703fb, 0x1f83f696,
3805 0x5563a1a3, 0x37efdc0e, 0x8f31c35a, 0x5e63aa20, 0x6c639326, 0xc716d89e,
3806 0x2c67c04e, 0xeba36bdc, 0x4ee9975a, 0xe99a7c64, 0xf61cf539, 0x3ff5923d,
3807 0xebb39ee1, 0x21ef1aa8, 0xbcb0d65e, 0xe18441fa, 0xc12be455, 0x5cfa81dc,
3808 0x241b8517, 0x939ef5d5, 0x8da3c936, 0x301c77c4, 0xa8fb50ce, 0xc8267e27,
3809 0x30699f9b, 0xaebbd34e, 0x20ca9277, 0xcce4231e, 0xfcccc94c, 0x9d5f5c42,
3810 0x2c7fc441, 0xe9c5539e, 0x53d70661, 0xf8304667, 0x74b627ce, 0x81bf77e8,
3811 0xd1e8aa44, 0x56de5999, 0xd1abfb8c, 0x116f405a, 0x7ad08971, 0x4e7f7042,
3812 0x7626cbfd, 0x0df2521f, 0x682e4180, 0x79d6b909, 0x43f9c3db, 0x97e600fd,
3813 0x0ec4d925, 0xb7fab071, 0xf8866e07, 0xc59c3e87, 0x321f2959, 0xef277bc0,
3814 0xfba63c82, 0x1856fa5e, 0xdc42bf7b, 0x0bdb3687, 0xc3617ee0, 0xcc42d4e4,
3815 0xc3e9385f, 0xb5ba0877, 0xaf3c74de, 0x5448bf94, 0x38987e06, 0xa50d1eef,
3816 0xaa64faf3, 0x3ffad16f, 0xbd581b12, 0x8ab1779f, 0x3d2407d6, 0xbc83eace,
3817 0x4b6ea0e7, 0x0d1efa7a, 0xf42b63dc, 0xfad3562e, 0xac2da484, 0x324b060e,
3818 0xcfd26f85, 0xf1d171ee, 0x3eb8582f, 0x3de2f363, 0x0737fad0, 0x84fd02aa,
3819 0x7f189263, 0xbec610ba, 0xe64990bb, 0xe778064e, 0x873eff04, 0x5cf42f7f,
3820 0x9fd15fb1, 0xf7ef0624, 0x4b7b9719, 0x92d03df9, 0x8c36b208, 0x915c95c5,
3821 0x3a870f14, 0xec5c6206, 0xcb346240, 0xf17b35df, 0x8e31109d, 0x4f18a780,
3822 0xe40cbbcc, 0xc9f311b0, 0xe2f964aa, 0x79d27e5c, 0xd93ce356, 0x727f7676,
3823 0xe0016a72, 0xc34de28f, 0xbc01a6f1, 0x30d77b89, 0xf91f25ae, 0x43f010fd,
3824 0xbf4aba1f, 0x5baff4cf, 0x38572749, 0x616d2c9d, 0x259f40f1, 0x24a9e90b,
3825 0x513bbf82, 0x04c7df24, 0x4931bf0e, 0x5ecfb616, 0x384824bc, 0x63870b4f,
3826 0xe4c077aa, 0x77df9bbc, 0xcf5b1278, 0x0077dead, 0x7ef0ecbe, 0xdbf6a1c4,
3827 0x30fdb0b6, 0x473d017c, 0xa4f75ea3, 0xab0bbc6c, 0xd387fd14, 0x8dfb0903,
3828 0x3ffec2ce, 0x100defe4, 0x5fb7a5b2, 0x3fd33e66, 0xf7152f41, 0x4eeb89e4,
3829 0xed17e812, 0xc6df0fbd, 0xf7faadee, 0xdf114f79, 0xd3ef99a7, 0x96e9f6cc,
3830 0xee392bd1, 0xea6a9f4b, 0xf0bdc74b, 0xb72f1def, 0x3b278f90, 0x83c6c1e7,
3831 0x2f0a1d73, 0x316e93a3, 0x2a758a3d, 0x670bd9e0, 0x3c04fac5, 0xbf637ce1,
3832 0x8a5d395c, 0x9d42da75, 0x38efccef, 0x57eb295f, 0xbfcb30f7, 0x5d395625,
3833 0x54ceedd7, 0xf45bdc41, 0xee3e0a3b, 0xcb5fbf38, 0x98e3c499, 0x443524a9,
3834 0xa4c2dcde, 0x30fea0b8, 0xe7695dfc, 0x3e5858f5, 0xefded2b2, 0xc275b389,
3835 0x25d7343d, 0xa47a7f76, 0x71013fc2, 0x7f465d92, 0x917cbf3f, 0xf87177d7,
3836 0xf8aff5f5, 0x91677ef0, 0xab35ecbe, 0x9bff908d, 0xebf20ef4, 0x07b2a8a2,
3837 0xf57d6933, 0xdfc8fd86, 0xbeca528b, 0x7cfca4ca, 0xac0386cd, 0xafb2f6fd,
3838 0xe93d41fa, 0xd897ab20, 0x4f7e035f, 0xc67bc1c8, 0x88f5f924, 0x7159261f,
3839 0x0ab9755e, 0xd5eadfdf, 0xa3d1de5f, 0x1ae022fe, 0xabd22caa, 0x9fc5831a,
3840 0x81e97b5a, 0xc38609c5, 0xa790ad3f, 0xaf78edc4, 0xf7c76646, 0xaffbb244,
3841 0x86fefb3d, 0x4f9e19f7, 0xf004fe72, 0x35d110d0, 0x1fd69327, 0xe30cf88d,
3842 0xea9d9250, 0xb0c7e021, 0xba2cc99a, 0x9d6ba95e, 0xb225f403, 0x20d066cc,
3843 0x075fb95c, 0xf0a2f4de, 0x9fedeb7b, 0xa6c2923d, 0x463ac071, 0xf0d03e70,
3844 0x435f37f6, 0x82e1b2dc, 0xe1ea06d1, 0x0f0d8e88, 0xa235be82, 0x30dfd7e3,
3845 0x5feecc39, 0x008f7588, 0x7dfd1dbf, 0xd71ebb78, 0xb6e3a23f, 0xc8fdf045,
3846 0x016476df, 0xe53e8c9d, 0xd0b60169, 0x148defb3, 0x2fcdfdf9, 0x186f99ae,
3847 0xe0248e32, 0x54aa27f1, 0xde3c2145, 0x8ab8f060, 0x71dd51f9, 0xd178d6c7,
3848 0xdfbf27b9, 0x8c76f542, 0xe1265e83, 0x8bd3f036, 0x7f4ac57b, 0xba4ac9e0,
3849 0x68fbfa3f, 0x80415d1f, 0x85725cde, 0x7a01ffda, 0xc8b12978, 0x2486e5ea,
3850 0xe615f7d9, 0xb8fb594c, 0xed64dbc4, 0x640b5977, 0x233909f5, 0xb44fdf64,
3851 0xf7eaca95, 0xf64bbf0e, 0x52bda57d, 0xb4f02f56, 0x721fbec9, 0x7ede5da4,
3852 0x0f01a89c, 0x076d2785, 0x6b3e2ca1, 0xd0e2b747, 0xa1078df3, 0x0617f11c,
3853 0xf43fa50e, 0x076d2b8e, 0x0fe177e1, 0x1157de55, 0x6ae9d1fe, 0xdc175ba3,
3854 0xa1a89a0f, 0x8bc925e5, 0x62ad44fc, 0x305e55f7, 0x6f01bb39, 0x094abee2,
3855 0x122943f8, 0x625ee62a, 0x3167b2f7, 0x4049d87f, 0x19a7f00c, 0x9de3f426,
3856 0xfabe36d4, 0x4ec7167b, 0xda37be03, 0x77db2557, 0x6ca715c9, 0xa964a5df,
3857 0x65cb4f02, 0xc3f30af5, 0x25c7efb2, 0xdfb592ae, 0x815c7d65, 0xf56527a7,
3858 0x0a0db689, 0xe0566d3c, 0x76b267e9, 0xdc1ddf41, 0xf836f53f, 0xca396895,
3859 0x780e59db, 0x0fbcf3b8, 0xb3bc31f1, 0x74f01cb5, 0xc436c9c7, 0x51c79157,
3860 0xe872ec0e, 0x5083c691, 0x05fda87a, 0x27340efd, 0xd9a87962, 0xc3a9fe8a,
3861 0x1e5839cd, 0xefe1b669, 0x8e1e6abf, 0x76cdfbe5, 0x3cd37f2c, 0x66cecb1e,
3862 0xcd6d9607, 0xaefdf86d, 0xdfe676e6, 0xd7bde98a, 0x807e069f, 0x1eb7956e,
3863 0x27643eee, 0x7e044ec7, 0xedee1dd9, 0xaea3fa86, 0x2fc089e8, 0xa1130007,
3864 0xcbcf9c78, 0x3df629b1, 0x0dbf94c9, 0x91756649, 0xb2a6d057, 0x5e1e8017,
3865 0x09e331b2, 0x8f211a4d, 0x9a2472ad, 0xa06eac2d, 0xe6364475, 0x613c655b,
3866 0x55e4254f, 0x60772510, 0x7bd4227d, 0x90fb58c2, 0x4113198d, 0xf1ceff0f,
3867 0xbc9f7b60, 0x20e492c0, 0xcf57e0f1, 0xbfe04d5b, 0xa0757639, 0x8c71e009,
3868 0xa4ecb1fb, 0x968f3b40, 0x2d029aa5, 0x0a93d9c8, 0x3d9444bd, 0xc9f1d2aa,
3869 0xdb6fb071, 0xbe43cc34, 0x7e804b5b, 0xdecc4b27, 0x4ff5df15, 0x1317f9e1,
3870 0x1d4f68f5, 0x6117d957, 0x7be493de, 0x64bce001, 0x7b8410e3, 0x0e97c98f,
3871 0xb1b45bf0, 0x7ce3d590, 0x80b6482f, 0x67c196ba, 0x8982c6fa, 0x0a5bdcae,
3872 0xe0c1059f, 0x666c9d53, 0x9ec7b6fa, 0xa8807a06, 0xd7b4af1f, 0x5e3e79c1,
3873 0xa2fbc76a, 0x767a1cc7, 0xbc261d7e, 0xf63440e7, 0xfe0169e2, 0x5ac9b39c,
3874 0x2e1537ec, 0xf35f819e, 0x739e357e, 0x29553c25, 0x3a470f4c, 0x46733b01,
3875 0xc705da04, 0xb7deec55, 0x14ccfbf2, 0x0c5d1f66, 0xeb77ee0f, 0xa6cbdbc7,
3876 0x87babdd4, 0x22b3d78e, 0x71ee870c, 0xac7d440c, 0x7bc251a7, 0x1be73db5,
3877 0xbd76b12f, 0xe304838d, 0x5fe13392, 0x8ed5fdb4, 0x31faff07, 0x15b3fefd,
3878 0x21943611, 0xbf0841e6, 0xb3c7f9fb, 0x3fa80c63, 0x569c9ecd, 0x26717206,
3879 0x31cd738f, 0xdc31e269, 0xe0e8b1a5, 0xc685ba09, 0x82143582, 0xa56c7164,
3880 0xa9cc9e0e, 0x06be5d4e, 0x4fd965ca, 0xf0ada2ea, 0x35ced77e, 0xd1d6c6a0,
3881 0xfc8c5c23, 0x3341fbcf, 0x26dcd75d, 0x73d995b5, 0x6bdaae5c, 0x433f2a6e,
3882 0x9e71efd0, 0x8081432f, 0x87166af6, 0xc597e8b7, 0x325b74e9, 0x91e4138f,
3883 0xa7df763c, 0x1db00e37, 0xf66ba4e8, 0xc4420307, 0x5cede409, 0xc744fc7f,
3884 0xbbbe55e6, 0x4ecde620, 0x71fe7a61, 0xd04ca51d, 0x7267ef27, 0xabeabf20,
3885 0xfee98b47, 0x2acc3bf3, 0xadcfc38c, 0xb87803db, 0xa8f1cedc, 0x9e70ed25,
3886 0x7de6b8a6, 0x8a4ab986, 0x93d79a7b, 0x734eb697, 0x2cbca079, 0x03ca3af2,
3887 0x5f70e5e5, 0x45c8396b, 0x7c451f21, 0xcd5cd3d0, 0xf22372f9, 0x4dcd43d3,
3888 0xecdc3f58, 0xf348f2c2, 0x5b97ce5a, 0xe6fdfdb1, 0x765f38e7, 0x0dbcbe73,
3889 0xae68ef7f, 0x66edf2c2, 0x28969627, 0x7e016fc7, 0xcc4e0d53, 0x83777bef,
3890 0xeb7c409e, 0xf31e8772, 0x7889e80e, 0xc858f9e1, 0xbde3d1a7, 0x8d5e653b,
3891 0xd2f7cf92, 0x25f7df43, 0xf4f300fe, 0xbe80c3e6, 0x9e9a1198, 0x09ab118e,
3892 0x92dfd2f8, 0xbe82269b, 0x356acc7d, 0x657d3e81, 0xa5f21363, 0x49ab7663,
3893 0x24dfeb4b, 0x9ddacc3f, 0xd69e9356, 0xc3e37bff, 0x3565ddac, 0xdffad185,
3894 0xeacfbf93, 0xc482c26e, 0xe7c8cd29, 0x0874894b, 0x21b947ce, 0x17150c73,
3895 0x1e975e54, 0x2e317382, 0x3818de71, 0x56c97517, 0xacbb8fa4, 0x7d410eab,
3896 0x0d66ce42, 0x1bb6c55c, 0xbf43560b, 0x0d4ad8b2, 0xba931bf4, 0x1bf4357c,
3897 0x26a4fd9b, 0xdcf8dfb0, 0x7ea1ab9d, 0x06b36d8f, 0xce3ad3f4, 0xa238c4c7,
3898 0x9f05da2e, 0x835e7916, 0x0f281c3b, 0x281ddbf2, 0xca5c040f, 0x063e56a6,
3899 0x7686c77e, 0x3ac12cc9, 0xc1bd4aa6, 0xab91c86f, 0x291af787, 0xfe7a8ebf,
3900 0xba2ad309, 0xdfa806cf, 0x5627f581, 0x9dfe5add, 0x97d71292, 0xe7e09f7f,
3901 0xe43de41d, 0xb1d09f65, 0x001e32f7, 0x7de314b8, 0x2bbe1334, 0xd0269c49,
3902 0x3cb89ab3, 0x6d25095f, 0x3bebcedf, 0xd9579c85, 0xdfd0a7fb, 0x7db85373,
3903 0xd83f97d9, 0xfcf41d60, 0x8439ee2b, 0xa1fce768, 0x7b2cc530, 0xb08ea15f,
3904 0xcbd7557b, 0x31e6531b, 0x9629f32b, 0xf6c3b691, 0x1479becc, 0xc7bd84b5,
3905 0xae4fcca2, 0xad5eec27, 0xd7b94f32, 0xfc670aae, 0x0d780ab4, 0x2989e3a5,
3906 0x6564f921, 0xe135f14a, 0x910f6f20, 0xb094bd97, 0xf93eec3c, 0x5b1f3c35,
3907 0x8ce22fb9, 0xf25def63, 0xfee56cfc, 0xddf45d04, 0xbf832b5f, 0xea9fc186,
3908 0x7d600b77, 0x044d7315, 0xfc8156fc, 0xf06be3e7, 0xbb3f251f, 0xfa727c55,
3909 0x9f763adc, 0x6b1f2fbf, 0xc7c2094a, 0xb2975e44, 0xdc2a7a14, 0x3efc831b,
3910 0xec060f78, 0x9c123bfc, 0x3d97402d, 0x55afbe65, 0xb2c68760, 0x2dbb93f7,
3911 0xbbf035ce, 0x03f963a4, 0xbcf6af22, 0xd04bf5ca, 0xf94a9edb, 0x6ebbf215,
3912 0x8cf41610, 0xe075a3ac, 0x8e2c4367, 0xe48fd0f5, 0xef817578, 0x1fca8730,
3913 0xe1cb9a7d, 0xe59125be, 0xfe6cf655, 0x0fde86e6, 0x0a8f050a, 0xdc2f28f5,
3914 0x3c3cb85f, 0x9767e502, 0xfef03c44, 0x3c69576b, 0x695d2dea, 0xb7940d3a,
3915 0x4aee2eda, 0x2be3801b, 0xa4aee3ed, 0xef3606e1, 0xfe50f1d8, 0x115ce926,
3916 0x790fbdc8, 0xcebb613e, 0xe037e435, 0x86111e1f, 0x257bfa71, 0x41c0116f,
3917 0x1d775769, 0xcd66559d, 0xd35f6bef, 0xfd818dfd, 0x3d519ed5, 0xacddbf06,
3918 0xf4db5dbd, 0xed3c8135, 0x09574d91, 0xbcdf8fe4, 0x9d19ddfd, 0xc2bd056f,
3919 0x322402d9, 0x13ea8bac, 0xfcbd7eb4, 0xb5124ba4, 0xec0333d3, 0x66bfe1f2,
3920 0x54bc4a79, 0xde7de7da, 0x92e65b4b, 0x7a95c3e7, 0x44df318a, 0xfbc48ded,
3921 0x9ef62aaa, 0x7a57c882, 0xd4f3db8f, 0x829b3f5e, 0x74ceb87e, 0xfdfebd99,
3922 0x823ce74f, 0xf30c207c, 0xff6d5e33, 0xfad60e3c, 0x9fb8ce87, 0xd3f565bc,
3923 0x6bf98377, 0x5f679812, 0x565974db, 0xed7ee2ef, 0x2fbb2d56, 0x354ffb54,
3924 0xc72a25ca, 0xc89e22d6, 0x0103dd01, 0xfdb495f2, 0x83de17b9, 0x04abbf29,
3925 0x1d7ca180, 0xfb4ec939, 0x887b7255, 0x9d587790, 0x95c48fdb, 0xe271eac2,
3926 0x7ab31ffb, 0xa9fef89a, 0x4f3a7649, 0xe7689265, 0x75e36ffd, 0x33d58797,
3927 0x647ff7c5, 0xbb589bdf, 0x498ed37e, 0x3f05ce70, 0xdfcaa537, 0xddfca201,
3928 0xcd7c5a92, 0x3b791a7c, 0xdde2ffe7, 0xdfef8a9f, 0x9c01f115, 0x730936d3,
3929 0x6a576ae7, 0x317f5fd1, 0xf03f2dba, 0x7791507d, 0x613728e3, 0xebdd541e,
3930 0x0b80b703, 0x1e3a6d53, 0x44ca7a0f, 0xa154ff9e, 0xe59c6236, 0xc7c67af2,
3931 0x8b79e943, 0xe194de9b, 0x7f3b4fab, 0x9103178f, 0x4f4bbe74, 0x90f7b024,
3932 0xee313bb3, 0xe995383f, 0x22bef0f1, 0xf915e7dc, 0xc459b15c, 0xec71f60e,
3933 0x5dec611b, 0xc89db3c8, 0xc1bf175f, 0x1b75d7fc, 0x9b3ca20e, 0xffa2b6af,
3934 0x673f5c68, 0x47c42a71, 0x30039d4c, 0x36f4ddee, 0x673fc39e, 0xcb9c7998,
3935 0xcf081b97, 0x5fe17dd1, 0x97f81d7a, 0xbfe13bfe, 0x180dea9b, 0x8613dae7,
3936 0xc6826cf6, 0x1c41b3ab, 0x577b24f3, 0xdb872172, 0xe23fced0, 0x7887ff7d,
3937 0xc59daa3d, 0x959e4469, 0x54a1f798, 0x8f038313, 0x7e4dd487, 0x43c4147f,
3938 0x224afe04, 0xb7f81b48, 0x1c6c1e29, 0x83c0360f, 0x2e3fb780, 0x0665fb42,
3939 0xbd956b8e, 0x1ee02b5f, 0xe92b1cea, 0x195bac43, 0x3c665827, 0x5df80c54,
3940 0x81799376, 0xbe38d297, 0xfbcc5e35, 0x410673fb, 0xb8f028b9, 0x5dde2fb2,
3941 0xc4d771a9, 0x5ffdbcbb, 0xdc25778c, 0x8f2d6594, 0x7f7f297b, 0x2ff55521,
3942 0x36ffe385, 0xc6ecea7f, 0xb9f6b2fd, 0xc86f474d, 0xa0fc2adf, 0xabbf2eff,
3943 0x7a4eb7f0, 0xe20a896d, 0x7c7b4a32, 0x6be3ba5a, 0xdf7bbfa0, 0x09ee47fc,
3944 0x00f57c58, 0x90793fcc, 0x51abe5ef, 0x11ecfb7f, 0x355f4f4a, 0xa9d43f32,
3945 0xad6a5ffd, 0x63e97d79, 0xb11515f6, 0xecd5d007, 0x20b48fa6, 0xcd5366af,
3946 0xea3c5822, 0x309e9cef, 0x81f2847f, 0xc6d1032a, 0x555ff3d2, 0xae73dec5,
3947 0x344bc082, 0x6d271e96, 0x1e21a49f, 0xd2b5af78, 0x31e8f1a8, 0xb7bf241e,
3948 0xb9efe7aa, 0x7652c352, 0x576d557f, 0xb4d37e63, 0x748e2ce1, 0xef0db1bf,
3949 0xf238ce25, 0x6847a5e8, 0x2aed593b, 0xe2b77966, 0x54efd19e, 0xfa1f1337,
3950 0x7e612a7b, 0x1dc78954, 0xee316b97, 0x61f7eca8, 0x4d63f32a, 0xbf2c4b52,
3951 0x4fcb2f60, 0xee91e713, 0x90be88ef, 0xbbc3c1e5, 0x5a8d95a6, 0xd07cc0cf,
3952 0xfea3f63f, 0x557c30d1, 0x61afe03e, 0x9f46748c, 0x1b03d7ef, 0xfd82fe9a,
3953 0x5958fc95, 0xe9dfa8de, 0x4823e6b3, 0x3c5f422f, 0xbac1ecd5, 0xab350fd2,
3954 0x6e303fe4, 0xee2fe233, 0x5e472816, 0x66189fb5, 0x95f6eefd, 0x9d84abb0,
3955 0x04dbb4a5, 0xb5ef10bf, 0xc3fc140d, 0x777b11f0, 0xbccac351, 0x15ff3934,
3956 0xd9f2957c, 0x7f8c3482, 0x006ff9ca, 0x7ff6c61f, 0xd3f61f17, 0xfc0da37d,
3957 0xeca95535, 0xdd25737d, 0xf93226d7, 0x7577a4a9, 0x19f51ab9, 0x3a0bbd25,
3958 0x19becfbf, 0x20b375fd, 0x31d74f56, 0xfbc241ab, 0xff5f2752, 0xba0643e1,
3959 0xa7b6ae84, 0xe8f7b2b4, 0xfbee926e, 0xe9b381ca, 0x9677df30, 0x9c33a403,
3960 0xf8665bdd, 0x47d69458, 0xbb4d2e8e, 0xb7951cb6, 0x17f18bff, 0xbe73ff64,
3961 0xca241c9b, 0xd473057b, 0xd39f362a, 0x213ef2c8, 0xcdc7acef, 0x675579ee,
3962 0xd37be2b6, 0x122fb864, 0x7dd2c8f8, 0xc58eb26a, 0x01493437, 0x117508ef,
3963 0xe92327cf, 0xb1464bef, 0xf9943877, 0x4f3cf598, 0x37719973, 0xbe5213de,
3964 0x3df22407, 0xca78f9eb, 0x7f448177, 0xf9582f71, 0x34c6d02e, 0x90ad7f7e,
3965 0xf838b214, 0x3753f9b5, 0xff00c9c8, 0x66d5f770, 0xa4b673b4, 0xae47f1fd,
3966 0x6f3c7e51, 0x3e7ee34b, 0xbf6c5d3f, 0xff6c5d0e, 0x6a1749ff, 0xef7c56d3,
3967 0xe2e966e3, 0x3f7dab11, 0x8f9c5bac, 0x96fc73de, 0x78b1cf1e, 0xf967b80f,
3968 0x471ef8ab, 0xe30437cf, 0xc3f3d740, 0x6bb17494, 0xbacfa33d, 0xaf144c5b,
3969 0xd0b94f23, 0xb8e2303f, 0x0dbfef13, 0x990edf7b, 0x90e0a4c6, 0x16eb0d43,
3970 0x1bd0827a, 0xdf80fcfc, 0x1d79e153, 0x6e37ca37, 0xaff1be36, 0xfb886b8a,
3971 0x4f5add32, 0xdb9009f1, 0xbe82c37b, 0x8d257d97, 0xef50edc9, 0x9ca25a6e,
3972 0x534f0057, 0xef15df38, 0xd9a8566f, 0x3b97b93b, 0x589fe8d5, 0xfedf83f1,
3973 0xdf6b79f2, 0x58fa95f1, 0x5072f983, 0x0d9446fb, 0x5f2f962a, 0xbcc56e58,
3974 0xc07bb02c, 0x17fc215f, 0x5847efca, 0xd1d3c2cb, 0x69d51ede, 0xc73cf587,
3975 0x5f0a13d6, 0x123e4d0d, 0xa87ceef8, 0x15f61bf9, 0x9c07e79b, 0xbde9098f,
3976 0x9cf99676, 0x1bef8fc1, 0x6dff8ba5, 0x3524fffa, 0xfe544971, 0xa66e49e6,
3977 0x57a6124f, 0x589d22ce, 0x2c3e21ce, 0x4fe5849d, 0x2c3627cf, 0xaef61217,
3978 0x670ca1f9, 0x8de83a49, 0x0fbe1f5a, 0xbff5e97b, 0x4cfbe2e7, 0x856c8e77,
3979 0xe55ba89c, 0x55ea56b7, 0x8fbe053d, 0xd8ff03a7, 0x2b74f7f3, 0x7b1bffca,
3980 0x94507aa7, 0x107a4a7d, 0x4a6ff6bf, 0xc4beecd5, 0x5e5107c9, 0x1f599a54,
3981 0xfdf98632, 0xe2642627, 0xcdf3f1f9, 0x6f82cd84, 0xef2afc42, 0xdfc58a8c,
3982 0x77f84a97, 0x2abdda79, 0x8b79623c, 0xa86add32, 0x79ed66ef, 0x44b71675,
3983 0xc22379eb, 0x8b72fb58, 0x67ddf21b, 0xcb9e2f13, 0xaeed90b9, 0xbd13bff6,
3984 0x7bf9d880, 0x127ebe06, 0xc3a8bfed, 0x89b6f2c0, 0x9bf61b37, 0x1049760f,
3985 0xe997f73b, 0xee0fbcec, 0xe0fdf8c7, 0xe15fb932, 0x267ede21, 0xe013aca3,
3986 0xfb74bbf1, 0x0d7ce0f7, 0xf75cee8e, 0x53f81154, 0xc2fc0454, 0x18788c5f,
3987 0x5fa228e3, 0x11ecb598, 0xc4876ef8, 0xfb5d8bf2, 0xd2dde2f4, 0xfc7f40f8,
3988 0x55f28ca1, 0x74daddf0, 0xc1429fc6, 0x942efe15, 0x261d8823, 0x8306d5f2,
3989 0x427e886e, 0xed06ef82, 0x437d5890, 0x577bd8fa, 0xe977d11b, 0xcc33fd02,
3990 0xec31fcea, 0x108eb063, 0xbfffac23, 0xd219bdf8, 0xef710e98, 0x55e82f25,
3991 0x4a7c5fa0, 0x27dc31c5, 0x63b53df8, 0xed4d3ca1, 0x40ff2851, 0xcf2851ed,
3992 0xca147b50, 0x0a3da9cf, 0x362ba2e5, 0x14971c78, 0xce7fd867, 0xbbf83ce8,
3993 0x33a62f1b, 0xc32679b9, 0xc75b29d9, 0x63ae1d3e, 0xc7f3a587, 0xec75d14f,
3994 0x82ad93d8, 0xe0a12cfb, 0x6fefb3d1, 0xf820cee9, 0x93dfcdec, 0x6ccbe782,
3995 0xefe7f3e4, 0xcfdca0d6, 0x2e46f76f, 0x3daef80e, 0xc878875d, 0x123673db,
3996 0xf736efc6, 0xd12ed5c2, 0xb1524ead, 0x330bfb7a, 0x0b9d5def, 0x0277b0fb,
3997 0xeef9e8fe, 0xfdbf3280, 0xfb863fb7, 0x8c7c741b, 0xbe48f6c7, 0x532f4067,
3998 0x6fb943ee, 0xffba2fb1, 0xc77fd075, 0x13b07e9e, 0x3b086fca, 0xfbd8fb2f,
3999 0xbbf77db8, 0xaf7bd70a, 0xf70457de, 0x56fdee12, 0xf41f341d, 0xc229464c,
4000 0x99d056bb, 0xba71b788, 0xaefaf812, 0x1e395ae7, 0x0017ef11, 0x3c82b50f,
4001 0xfa091aba, 0x5b8f2560, 0xfeceefb6, 0x1cb9ef10, 0x3bf81351, 0xe5a38381,
4002 0xc19d4ee7, 0xf3289dce, 0x801ce9f6, 0xcefb1daf, 0x9cfbc365, 0xf0d93f14,
4003 0x4abf5b77, 0x17f32fef, 0x66f88de6, 0xfd0fd023, 0xe02eff1e, 0x02b9b20c,
4004 0x0d33f3e2, 0x2d85dffb, 0xa99f36cd, 0xdcfcf880, 0x9430e944, 0x6399acf3,
4005 0xf22f2e21, 0x94e4179a, 0x74a3861e, 0xf512ad8f, 0x2e6052b8, 0xdca17201,
4006 0xe71fc110, 0x46287215, 0x98971f56, 0x2efefb22, 0x7dac966b, 0xb2edce42,
4007 0x26fbdef6, 0xdffe21b6, 0x7c3c01fb, 0x465e20fd, 0x8efec1f7, 0x7dec4bd9,
4008 0xc73dbcdd, 0xd69dbeef, 0x0d3cbd27, 0xc1db63df, 0x2aed27db, 0xd623bfc7,
4009 0xa3a9e143, 0xe1f9d48a, 0x14f33f8f, 0x13b0a60c, 0x78bdf76a, 0xbe67de18,
4010 0x1d709dae, 0xfbd420fb, 0xd2bfa2a1, 0xf2fca03e, 0x072fc0c7, 0x0cd53ebf,
4011 0x231da1f1, 0x790649be, 0xefc19994, 0x21bb7187, 0x9ef4dd14, 0x61fac90f,
4012 0x2528fde0, 0x28f210dd, 0x4e5643a7, 0x01eec63a, 0xfb3f2cdd, 0xb433f013,
4013 0xf0245dc3, 0xfd2a08ef, 0xb6758365, 0xff041f0f, 0xb86a07ce, 0x3f7bd109,
4014 0x5bfc316b, 0xb277a7ed, 0x4963f370, 0x0bbbf8b1, 0xee7ae0f4, 0xc1959b3f,
4015 0x76a4ace2, 0x454963ff, 0xe2b276fe, 0xb27bec8c, 0xab235a52, 0xd794ceaf,
4016 0x09ae97d7, 0x0f4a1fec, 0x3cdcfc5b, 0xee0f339d, 0xff4149f1, 0x7aef626e,
4017 0xd85f3962, 0xecf904b7, 0xf14bfdb9, 0xbf2ab9ef, 0x81e3a7af, 0x08716fdf,
4018 0xd3f82af9, 0xcf7b350c, 0x4cbed957, 0xb5bb67cc, 0x614a7df3, 0x6f5c798f,
4019 0x69fbb930, 0x93275394, 0x7f4c19eb, 0xc9e1b4bd, 0x710d7c1f, 0x9eccbda4,
4020 0x726164ba, 0x17f77f23, 0xcc7bf82a, 0x7d19c383, 0x2abd9be5, 0x53d327b8,
4021 0xbc82e11d, 0x26a586ed, 0xdc1bb7cc, 0xa189f7cf, 0xfc1f9080, 0x1a7fd0f4,
4022 0x0efe7d28, 0xc805bf2e, 0xb9d01ee1, 0x8cf1fd68, 0x49872843, 0xb86fcb2e,
4023 0x9c7cfb55, 0xbfa864ea, 0x317e3194, 0xcb8fe807, 0x55cf422b, 0x57a463c3,
4024 0x021f017e, 0xc0fd40b8, 0xf0fbdf4f, 0x1e33f069, 0xfc02fc65, 0x0f513307,
4025 0x7ee51bb0, 0x1ef63685, 0x0bbd9598, 0x4242f222, 0x87658ff1, 0x5760755a,
4026 0xf1fe6ade, 0xc4f9f5f2, 0x8f1409b1, 0x3e597b0d, 0xfe8ee5f7, 0x6f802451,
4027 0xf0d7e128, 0xb7cf0a9c, 0xa87777a8, 0x5079c3c7, 0x70164bde, 0xb201e626,
4028 0x181e78f7, 0x20c9b7fd, 0xa7d81f97, 0x50f44161, 0x1155acf3, 0x833cc06b,
4029 0x8e51e9f7, 0x98f7f589, 0xf7d91f39, 0x5cd2e8d7, 0x220aae56, 0xa01ea94f,
4030 0xa03d058d, 0xf5bb4252, 0x65097de3, 0x258fff00, 0xe216b1e2, 0x3a2f9810,
4031 0xbf070d85, 0x899df11b, 0xe04d1cc4, 0x6ec27afb, 0x5a6fb69d, 0x3f57d07f,
4032 0x63ff3dd9, 0x69f2198a, 0x879e1646, 0x1f8ef0e9, 0x16c7ef85, 0x43f81a47,
4033 0xeb78f126, 0x175f16c7, 0x8f1fd5e8, 0x6fc0908e, 0x0d5fc749, 0x7d7d8be3,
4034 0x35a475ac, 0xed17fa06, 0xfbd3be83, 0x42bda25d, 0x0274b2bd, 0x11678bc4,
4035 0x5efcd77c, 0xc9a3d335, 0x0b3cec3b, 0x7520dabe, 0xc73be346, 0x32bb9319,
4036 0xa684ff68, 0xab3da11f, 0x51ba27cc, 0x6ed7ba3d, 0x77b126de, 0x4e8c6c32,
4037 0xfc5d47eb, 0x7f3a74c9, 0x41efb53d, 0xdf6babaf, 0x28a6ef8f, 0x7b5ef9ed,
4038 0xbc2fe94a, 0x7fe83f8e, 0xca6fb100, 0x0080005b, 0x00000000, 0x00088b1f,
4039 0x00000000, 0x58adff00, 0xe554700b, 0xdef73e15, 0x66cd927d, 0x421b22f3,
4040 0x260ddde2, 0x9b709601, 0xf51e4357, 0x8ca4109a, 0x6388376d, 0xfadea56a,
4041 0x59092040, 0xd6a27509, 0x0071a6e1, 0x3b634ea9, 0xb33088a3, 0x2331e1d2,
4042 0x3054d353, 0x32d740a3, 0x5da96255, 0x66d42d8b, 0x88d46b98, 0xf1a6c935,
4043 0xa1986655, 0x5ef7fce7, 0xd6086f76, 0xe6ccdd3a, 0xe73effec, 0x9cff8f3b,
4044 0xaa36c01f, 0x5cfb0195, 0x8bdff016, 0xed2bf1f6, 0x8ca2c020, 0x06ac43b0,
4045 0x27c8f2d8, 0xfb0dbd7f, 0x990dedd4, 0x47f18b63, 0x475f8e3e, 0x5c8054b3,
4046 0x000ea580, 0xd4c0154f, 0xbee8b4fe, 0xf097f500, 0xd9b00350, 0x80453f87,
4047 0x9c944e8f, 0x8ff1c6ed, 0x8703b0de, 0x9f1b275d, 0xdb107c9e, 0xf9a7f65b,
4048 0x059e349c, 0xef8d3e6a, 0x38aa8d2b, 0x6a7e3ee1, 0x27073ba4, 0xfb4ba60e,
4049 0xbdc3fc71, 0xc61fcfa5, 0xafe786f6, 0xaecd8897, 0xd9883c5d, 0x0d885fd8,
4050 0x3e6dffea, 0xfd7e075b, 0xfd2e75dc, 0x92e0e15c, 0xf8d0379f, 0xce896cc1,
4051 0xcb39a569, 0x75ec2e00, 0xf00e50cb, 0x7dcac419, 0x731f00c5, 0x1b8f18ea,
4052 0xcf87f3b7, 0xb3c03c73, 0xe494a50e, 0x37fbb8de, 0x7947ab7f, 0xe77e0f9a,
4053 0xdfc865e9, 0x40b93386, 0x5cf2c0fb, 0x787e0186, 0x1a728b98, 0x9708b5e7,
4054 0x60085abc, 0x067158fa, 0xb4f89284, 0xdefb721f, 0xe2b81977, 0xd32073b7,
4055 0xca1aeed2, 0x965fbdf7, 0x8e83b76c, 0xd9c3dc31, 0x7d0eff68, 0x65798608,
4056 0x09d5f109, 0x0808039a, 0x97847298, 0x9c085400, 0x13ff840c, 0x65ff864e,
4057 0xa490dcfa, 0xf8cf222d, 0x1941e0e8, 0x6cfce0f0, 0x702bf970, 0x97e3a2b9,
4058 0xdf74a278, 0xad66c44e, 0xcd500598, 0xbd592df6, 0x8b7fc924, 0x15e9b230,
4059 0x977a7fdc, 0xef627253, 0x0cee1bb8, 0xa73eae87, 0xeb64cc55, 0x053eb9d7,
4060 0x7fb2765b, 0xadbfcf53, 0x51c810ed, 0x27d15f5c, 0xb48fde56, 0xafcbd0db,
4061 0x0c35e1fc, 0x8f2781f7, 0xee78669e, 0x3a1de079, 0xe98794f7, 0xb8eb4e0f,
4062 0x23683827, 0xd6fdcc39, 0x56c0a6b9, 0xc73efc49, 0xc7fb35f8, 0xae5b399e,
4063 0x4763fee0, 0xda039716, 0x7c425df3, 0x67c459ec, 0xfe7e3d32, 0xa783a461,
4064 0xf15732fe, 0x476fcd5c, 0xcfdb34cf, 0x1c738f6c, 0xe483b793, 0x829bfec0,
4065 0x9e228de1, 0x09903603, 0x4b9dd1bf, 0x422d7e18, 0x9ff48328, 0xdfcac8f8,
4066 0xfdcd3e4c, 0xfdccfe4d, 0xa43d79cd, 0xc261c42f, 0xc2cf2f11, 0xa24539fe,
4067 0x6f09ae45, 0x43d33cbc, 0x3fd63efd, 0x14ed8591, 0x9fa36b7b, 0x1736dfa8,
4068 0xbf9073d8, 0xea4e36b6, 0x42afd603, 0x0531a316, 0x2ffc3bc7, 0xd841b81b,
4069 0xab767685, 0x93906761, 0x5a3f236d, 0xdf5dba03, 0x8bc7fb5a, 0x76e0179c,
4070 0xfa03b018, 0xf7be39cb, 0xe3a42ec7, 0x13b4bf03, 0xbe10e87e, 0x4e5fb431,
4071 0xbcbf877d, 0x4db96af8, 0xa58d804a, 0x5f831bc6, 0x22ca09b5, 0xcf84cfb8,
4072 0x014bf2a3, 0x1b39119e, 0x8508579b, 0xa5c70f34, 0x3a81da18, 0x90fa94e8,
4073 0x787c4b9f, 0xe1dfe12f, 0x1f939588, 0xf12eeb98, 0xe71feb0a, 0x7d23af4e,
4074 0x1e562d83, 0x647d474e, 0x40cb803a, 0x65c52b9a, 0x0cfd43c4, 0x23015c58,
4075 0x9518f1fe, 0x1d849ce8, 0x8f9106da, 0xfd37ea46, 0xaaa4ed13, 0x7a0c8f99,
4076 0xfc93f392, 0x0195db5b, 0xb2aacfdd, 0x2cc0c8f9, 0xc327f1fe, 0x4060fb0f,
4077 0xd617fdd0, 0x7ae710b8, 0x59006703, 0x64df7f20, 0x3cb937b4, 0x54e30131,
4078 0x0552ebc2, 0x18febfe4, 0xf5db01ea, 0x44abd8b6, 0x07a1ebd1, 0x310759f5,
4079 0x6b21bf7d, 0x8f70e6fc, 0xfc1c703b, 0xa91c598b, 0x8dbbd433, 0xd1e9008b,
4080 0xee8cfd05, 0xd102e2e4, 0xa314c16f, 0x446cf832, 0x97467611, 0x15d19843,
4081 0x25746110, 0x0aba33f4, 0x19bd1806, 0xa2c28ce2, 0xf8b01f58, 0x58df13ff,
4082 0xdf6f921a, 0x5a465fc7, 0x66441b75, 0xc32987f3, 0x078dafce, 0xaf9af546,
4083 0x500ac78f, 0x6baf8cfc, 0x8cbf32e1, 0x8b89b9d9, 0xd711ec93, 0x27ea21b9,
4084 0xdb1a08da, 0x5c3206e7, 0x1046e7dc, 0x066ed46d, 0xbe5bb599, 0x9ab51e22,
4085 0xb3425362, 0xbb3cd2e0, 0x70345c9d, 0xab2c25e9, 0x185afa93, 0xd4db5910,
4086 0x149f201b, 0x27d6afff, 0x559f1114, 0x889f4d69, 0x03b22218, 0xc61b61bd,
4087 0xa6caaad7, 0x2f6c62ee, 0xb7a93c08, 0xed2a9beb, 0xfbd39e12, 0x8c72f08b,
4088 0xee0c2eab, 0x2845c46e, 0xa916a016, 0x0396f6e2, 0xb85395fa, 0x54ff225f,
4089 0x10f100dc, 0x40b9e373, 0xc256d0fe, 0x3e2dbfee, 0x3aef3f5d, 0xda00f494,
4090 0xe62ba777, 0x2de71115, 0x74792dbd, 0xe8776e0f, 0x2b9bbefb, 0x65057e2e,
4091 0xae39e272, 0x383ca48a, 0xadb1baae, 0x4f776271, 0x57ee7920, 0x5020af38,
4092 0x9af3ed7d, 0xfc488afc, 0x4804ab80, 0x3dc605cf, 0x2f58383d, 0xef9d3c49,
4093 0xe96be763, 0x383ddd25, 0xbc3fa4f4, 0xa44bf690, 0x90b5f6eb, 0xd24dcff0,
4094 0x94b90135, 0x27f667c6, 0x1a38bf7a, 0x1f137dc3, 0xaeb8c1e0, 0xd394a031,
4095 0x56bc5db9, 0xf87a8954, 0x0779da69, 0x4fb4dfe9, 0x0772950e, 0x4327dbca,
4096 0xbeecc1d4, 0xaf2577c1, 0x77da4e2a, 0x0fdc5ee2, 0x870aa871, 0x5c38ed9b,
4097 0x493916d3, 0x6fe956b4, 0xa73a11c6, 0x12e9f89e, 0xbe91d6a6, 0x38cf3327,
4098 0x37fe603e, 0x2333b75f, 0x313f1d2e, 0xde8170fc, 0x7f8a430c, 0xf8b89d75,
4099 0x1e303ff9, 0x247b4d76, 0xec7f5e9a, 0x26f06e99, 0x3ab30afd, 0xfd30dc4b,
4100 0x19c86eac, 0x85bcd813, 0xc6fcd2f7, 0x14c52333, 0xd1186f6f, 0x42dc30fa,
4101 0x02d9f8e2, 0x7b8ddedd, 0xfb82fe41, 0x8b42f73a, 0xb8c74a80, 0x1088f9bf,
4102 0x9b5ca275, 0xda304f29, 0x743fb62a, 0xd0649da1, 0x8f93d97c, 0xe437ad72,
4103 0x83fe1cea, 0x6d3a8303, 0x1bbc92a3, 0xefd7fe0c, 0xca66fbb9, 0xed4436fb,
4104 0xdf8ef8c9, 0x36e891f6, 0x90fdbbe2, 0x21229fb5, 0xac65dfc9, 0xabbca0ef,
4105 0xeb37f298, 0xfc782ebc, 0xba97145f, 0x9bfdac86, 0x4c39e902, 0x063dc60f,
4106 0x9f78be46, 0xa3e48731, 0x71f379bc, 0xb289d447, 0x2ddbde6d, 0xe85da8f9,
4107 0xdd1c5891, 0x5bb328f3, 0xc9ec3e73, 0xfa623666, 0xc01d86e7, 0xc71360f2,
4108 0x329c07a5, 0x81e963e9, 0x62df963c, 0x0af2ce5e, 0xcecc138c, 0x1c262297,
4109 0x990bddda, 0xcf1e4153, 0x9978e179, 0xcbf37944, 0x6f78655b, 0x333f9241,
4110 0x0e116f6f, 0x3ed03b37, 0x1f01efa6, 0x50357de5, 0xae0374f6, 0x87653eab,
4111 0x834f8e28, 0x0be98fae, 0xebbfcb3c, 0x64fd2b86, 0x231cc207, 0x4f31f86e,
4112 0x2dc3c14f, 0x253101ce, 0x75f135cf, 0x2b4b7a1a, 0xa78cb2cb, 0xeb2cf34b,
4113 0xd6836a33, 0x0f1caaf5, 0xd69c50d5, 0x8bca67d7, 0xc341f32c, 0x306f1c3f,
4114 0x5deedbe0, 0xb7ec8a71, 0x66feb3d1, 0x657b29c2, 0x53be6585, 0xff102638,
4115 0x2cda9f0d, 0x8426fc7a, 0xce51d39b, 0x0f31b7da, 0xc6ea73c1, 0x4d6ee3ad,
4116 0x7ee75a05, 0xa01f253b, 0x7b6b44fd, 0xf987b4c0, 0x1ed53f30, 0xae7b7892,
4117 0x50f649e0, 0x782c0b03, 0x0aebc4cf, 0xf3071efe, 0x6ee1ba87, 0xd86e5fc6,
4118 0x9b5e7b8a, 0xc57cf715, 0x7ac1738a, 0x1185ce2b, 0xf5d7ce2b, 0xa80d7158,
4119 0x778adc56, 0x5fe659d4, 0x6964dfdf, 0x655aee97, 0xba30bf99, 0x7c5ed2da,
4120 0xfccb76e8, 0x59770325, 0x6d0e97c6, 0xf69b8cb4, 0xdfff5335, 0x619e6d88,
4121 0x5ff03c5f, 0x53caffa2, 0x99ce590f, 0x888077a9, 0x6bd6f840, 0x5703bb00,
4122 0xedfabdeb, 0x578af07e, 0x0f029deb, 0xf5339de5, 0xa7fa453f, 0xffe86f38,
4123 0xc629d233, 0x17bd37b9, 0xfd37271e, 0xcf1e9a6e, 0xb886845a, 0xb06d7a4c,
4124 0xcfeb7ab3, 0x3a737662, 0x1ee303c5, 0x18f71b0b, 0xecc1dfac, 0xdbd3ec21,
4125 0x493a5c52, 0x5ce2ac71, 0xaaf899b8, 0x512722d2, 0xd0b9a84c, 0xf3419cdf,
4126 0x387d1065, 0xfaf0339f, 0x36072d5e, 0x7b613f8b, 0x5bcf126e, 0x03215ed4,
4127 0x8a5fd727, 0x4b30b1f6, 0xbf9e0ec5, 0x6ae718da, 0x55a27bf5, 0x052d8376,
4128 0xf35ac697, 0xfe3108fe, 0x316ffc4c, 0xe7cc08ea, 0x3cf941c1, 0x05f68aef,
4129 0xa45fcb66, 0xafcb025d, 0xbd6f9614, 0xa27629ce, 0x22f15c6b, 0x9e4aeb8a,
4130 0xb8882f32, 0xc892f24d, 0xeb4e33f2, 0x2412a123, 0x6a565d18, 0x754cab66,
4131 0x30a39618, 0xd19f290f, 0xfb187aaa, 0x2f46ad3e, 0x1253e97b, 0x18838a54,
4132 0xdf394717, 0xfb5c4ab6, 0x45c7dd66, 0xca2d6f74, 0xff501790, 0x3c8ef795,
4133 0xabe30b94, 0x412a8bc6, 0xb1c43ea0, 0xda63e1fa, 0xdf8a5964, 0x7bb3b0ee,
4134 0x6a7a8c0a, 0x599381ad, 0x9c61dd4f, 0xac5b8a3b, 0x76bdf8c7, 0x478675e8,
4135 0xd59c7fbb, 0x926f689f, 0x7bbff70f, 0xea82a7be, 0x252b9049, 0xeb370ebd,
4136 0x7fe102ab, 0x7acd47b9, 0xdbf35af4, 0x752c17fd, 0xefd61c2e, 0xafef6b97,
4137 0xca4d7b32, 0xfa3fefad, 0x77bb1a58, 0x6c2b1f46, 0x7fdc9a22, 0x36bfed92,
4138 0x3ec596f2, 0xbbf9ecee, 0xa47eeec5, 0xd7196bbe, 0x05eca672, 0x3476bf28,
4139 0x100fc57f, 0xce2389bf, 0x5133aa1a, 0xa60fdf5f, 0x13dac1d4, 0xbce9cba5,
4140 0x3fe72eff, 0x5b23be19, 0x905b60e3, 0xd6fcf394, 0x6dadac73, 0x299d18d5,
4141 0x9a9759a7, 0x287bf1d4, 0xa67ea1b3, 0x6cd239b8, 0x41232cef, 0xb91f6f3d,
4142 0xdd136e71, 0x0e8523bf, 0xf44b4e9b, 0x4bad7e76, 0x4958af6f, 0xecf76134,
4143 0x8474baa0, 0x7b439903, 0xf9f79d18, 0x516e0701, 0x403ca797, 0xa69a2672,
4144 0x2977a73e, 0x288ad1c8, 0x2a664c9e, 0x873f520f, 0x167e5fc9, 0xf284b3e3,
4145 0xfabc0bff, 0x7018c06b, 0xad6ddf60, 0x7a4fd794, 0x647fbb75, 0x2aad2ddf,
4146 0x199952e2, 0x40eb4ade, 0x917bd8d6, 0x8ef9afc9, 0xd52f7542, 0x4eb70921,
4147 0x263907b7, 0x74198eff, 0x28d4d537, 0x1d064bdf, 0x384afbe5, 0x4edd87f2,
4148 0x7e601fd8, 0x315e5320, 0xfba9cc7d, 0x8bc00d81, 0x711defe3, 0x3cf6473e,
4149 0xbca67917, 0x9633b305, 0xcefc57ff, 0x6138a319, 0x14e4bfbe, 0xe10b3f8b,
4150 0xec979cfa, 0x4c9fceac, 0xbfc86b17, 0xb2afbd3b, 0xa0a6ebbc, 0x40e4c032,
4151 0x8c7e2849, 0xdbee751e, 0x2a4dfcc9, 0x7ffe9d5a, 0x103b677d, 0xa68c7564,
4152 0x3bc691e7, 0x8b77299b, 0x7b9338f0, 0x4813977a, 0xe37b89ce, 0xbbd8854f,
4153 0x7c445492, 0xdf3af28e, 0x7ca6bf26, 0x7dc91ca6, 0xcd6edcbe, 0x7be4a2f7,
4154 0xf212f6d6, 0x7f51c403, 0x3bb813c7, 0xfeb2cf57, 0x9aabe90c, 0xa09da7bd,
4155 0xa231b638, 0xf525a7bf, 0x3bc0ffde, 0x0f61b7a4, 0x5ad7638b, 0xcece533f,
4156 0x0f0cc313, 0x2487f394, 0xa79c8a5f, 0x7eef2983, 0x3ecfc713, 0xbebf1215,
4157 0x38c2897c, 0x3c4cdf7b, 0xc448b177, 0x5ec79df5, 0xd276473f, 0x33ffd469,
4158 0x739da9df, 0x9acc7eb0, 0x6f1a7ded, 0xc97c9485, 0x6f9fae69, 0x04c7aeb3,
4159 0x886cfc99, 0x0af291fc, 0x5e2927bc, 0x8be4f79b, 0x69c19d46, 0x4d78b1af,
4160 0x6efd91e7, 0x5f7654e3, 0x7d05ef99, 0x5447de1c, 0x2cdd2b97, 0x79d70b8e,
4161 0x17cfb224, 0x74e306d1, 0x34e4d8ff, 0xa33c2ef6, 0x54e79d8e, 0xd93b253e,
4162 0x1e5356f2, 0x6f83b9d5, 0x27ea32ac, 0x36a91efd, 0xce9ab2ec, 0x1943fe27,
4163 0x32a93eec, 0x4571abf8, 0x0cbade58, 0x177f4154, 0x1e19de30, 0x7752cd7b,
4164 0xa2bf07fd, 0x17f0846b, 0x000017f0
4165};
4166
4167static const u32 usem_int_table_data_e1[] = {
4168 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x33ab678a, 0x32ea7830,
4169 0x31e9c830, 0x43d24c30, 0xb712d388, 0x9fa65173, 0x8181859d, 0x81b98813,
4170 0x5f881798, 0xbc303231, 0xff5e2466, 0x3b046147, 0xe181804b, 0x0b6f9013,
4171 0x32089fa4, 0xb2075c30, 0x0371033f, 0x88073f90, 0x35b10057, 0x480fbf90,
4172 0xa3e204df, 0x1845fc40, 0x095ff9bf, 0x42156fc8, 0xe3443fe5, 0xafc4159f,
4173 0xf980825f, 0xb1e40472, 0xe42269e1, 0x0a6dc7c7, 0xde040ef4, 0x67ca86a6,
4174 0xe0606553, 0xaac58a07, 0x91dbf843, 0x6281f3e4, 0xf610aaec, 0x8606396b,
4175 0x1db9405f, 0x7dcdd86a, 0x0dff9403, 0x9a86ab94, 0xf1b90003, 0x03685054,
4176 0x00000368
4177};
4178
4179static const u32 usem_pram_data_e1[] = {
4180 0x00088b1f, 0x00000000, 0x7dedff00, 0x45547809, 0xbedd70b6, 0xe9d3bb7d,
4181 0x84849d25, 0x1674b090, 0x26c43510, 0x630a0840, 0x944c2127, 0x615151a8,
4182 0x8408ec44, 0xf9707d90, 0x37d7d470, 0xdf95012c, 0x3e30eb89, 0x0e0c1a74,
4183 0x1036a0c3, 0xc6c06a30, 0x680e8300, 0x8cc08378, 0x364584cb, 0x5c710921,
4184 0x7f9e6466, 0xbb75539d, 0x48e9bdef, 0x9bdffc74, 0x3f6fef37, 0x556ea2bf,
4185 0x5b3aaa9d, 0xaa753a9d, 0x42049462, 0x1be426ae, 0x71f4d1f8, 0x10921091,
4186 0x69f2bb4e, 0xb910963a, 0x96bfca27, 0xff6e0d56, 0x401904fa, 0x5be6b9c8,
4187 0x4254e65c, 0xc1513d3c, 0x39f969ab, 0x4cdf9e7f, 0xbcb60bcb, 0x7cd230ef,
4188 0x08d116f5, 0x16ed86e5, 0x4ab9df6c, 0xd6be43f0, 0x55d8fedc, 0x45bddf34,
4189 0x68286b24, 0x2066ceb2, 0x889c8439, 0xb467ec22, 0x2122481b, 0xad961665,
4190 0x1663bd5e, 0x62de57f4, 0xfeda1626, 0x81e8b344, 0x82b582fc, 0xaafed09f,
4191 0x4a665b5f, 0xf9e6f0a6, 0x45c58085, 0x371f6bf3, 0x2c84ecb9, 0xa381feda,
4192 0x19c846c3, 0x9971145f, 0x81e51e70, 0xfc2a424c, 0xd324a71b, 0x041b15f6,
4193 0xafc281b7, 0x13be7558, 0x2cd157c6, 0xbc29170d, 0xe25675ca, 0xfefac91a,
4194 0x6d7f4086, 0x2dbfb0c7, 0x57f40652, 0x136ee17e, 0x929e6111, 0xd355da07,
4195 0x95bcc071, 0x1af8cf7e, 0x18446b89, 0xa1bfd59f, 0x357ad1fd, 0x986e0b2f,
4196 0x78818d62, 0xaf9d1c61, 0x60bfa659, 0x9bd5f983, 0xf3d5d846, 0xf30add28,
4197 0x36aff0a8, 0xf8c1b14d, 0x32ca9b56, 0xd72af0c3, 0x515c493d, 0x4cadf1aa,
4198 0x9555e81f, 0x3e33d3eb, 0x054f19a2, 0x06c05925, 0x6e9bf678, 0x7efe151c,
4199 0x7a458858, 0x3513ae57, 0xf1e529f0, 0xfd3efcbb, 0xbc83c527, 0x9b5feecd,
4200 0x02dba61a, 0x2bb7fd27, 0xa71eb74c, 0x1ceec742, 0x7d257c35, 0xc741e80c,
4201 0x6273e8d3, 0x092f84fa, 0x2e7ca7d3, 0xbe33d3a4, 0xf4ae9891, 0xb3fbf1b9,
4202 0x574c5cbe, 0x3e983cf9, 0xd4c22bef, 0x7ac12bef, 0x31d37c6b, 0xf179f26d,
4203 0x72be8bfb, 0xeaf9d74c, 0xdf7afbf0, 0xf8374c42, 0xb2fefc64, 0x01a6396f,
4204 0xbe4da74e, 0xfb369895, 0xab6f58fc, 0x2da61d6f, 0x5f7e00be, 0x98e7f1c1,
4205 0x748cf248, 0x710f0efe, 0xb8937252, 0x449e4f62, 0x2c2571f3, 0xce53389f,
4206 0xa27cd133, 0x3e29e697, 0x7982ab92, 0xae4f9a66, 0x1f43e563, 0x3451f924,
4207 0xe566543f, 0xf93c2b69, 0x6b4f9a16, 0x5623e564, 0x34d1f9c9, 0xcacfc23f,
4208 0xcc10db2f, 0x65fcd2b7, 0xd59e5601, 0x346c0a4a, 0xf964159f, 0x029ebdec,
4209 0xb767cd3b, 0x87ce7cb3, 0xe6838172, 0x7b583a73, 0x1203de3d, 0x6d284d99,
4210 0x3c8b959e, 0x6f3441c6, 0x37137722, 0xa37c8bc5, 0xe28138c7, 0xf9617241,
4211 0x5827f976, 0xc2e4c9be, 0x367976f2, 0x1e4b3796, 0x572a3f2c, 0xc9b37961,
4212 0x917fe583, 0x56fcc5ef, 0xa6e58bc9, 0xfac37ffa, 0x2c5e4d5b, 0x865faa4f,
4213 0xc64916f9, 0x1beacbf2, 0x498b7eb1, 0x9627f2c6, 0x9933d2fc, 0xef04fb96,
4214 0x8b67c053, 0x49396f05, 0x2409fe07, 0x69fe5095, 0xe074c810, 0xc98107d7,
4215 0x20fcd1c6, 0x605dca13, 0x200bce57, 0x001bf8af, 0x1f17b2f9, 0xcf384549,
4216 0xc2891c21, 0xc70e2f11, 0x03573bbd, 0x5cbbbdc7, 0xd422f381, 0x1fe96c5b,
4217 0x2beec09c, 0x5dd9e3b5, 0x0579c0a1, 0x37fbd8e1, 0x26eff72f, 0xbbf3c76a,
4218 0x0b4e052a, 0xdfed89c2, 0xd3ed3678, 0xbed367e2, 0x20767e10, 0x37fa127e,
4219 0xb577ec9e, 0x377ec9f8, 0x70779f84, 0x07fa833c, 0x5abbd367, 0x377a6cfc,
4220 0xe03f9f84, 0x6ff48678, 0x69efd95e, 0x5efd93f1, 0x221f3f08, 0xc1fed49c,
4221 0x8b5f7e69, 0x43f7e69f, 0xe104f9f8, 0xbcdfef0c, 0xe2d41ec6, 0x10c1ec67,
4222 0x3f113a7e, 0x4e0ff697, 0x7e2d41f3, 0xf0860f9a, 0x678e25f3, 0x35e6ff54,
4223 0x3f1690f6, 0xf0850f63, 0x33800443, 0xd9e37fba, 0x3f1691fa, 0xe10a3f5b,
4224 0xc67082c7, 0x393c6ff5, 0x93f16b1f, 0x3f0871f3, 0x42670871, 0xfd6ce0ff,
4225 0xad9f8b58, 0x93f0871f, 0xf5267082, 0x7f395e6f, 0xe727e2d6, 0x64fc21cf,
4226 0x3e3c9c20, 0xd8e1421e, 0xf2d386fb, 0x2d3f1689, 0x33f0849f, 0xf214e10a,
4227 0x4e045cf1, 0x7e2d09ee, 0xf0844f72, 0xae708393, 0x969c1fe9, 0xb4fc5a13,
4228 0xe7e1089c, 0x5d73846a, 0x7b95e6ff, 0xdc9f8b52, 0xa33f0c93, 0xc1b496f7,
4229 0x40d7437a, 0x4c9b48b7, 0x08f1ee38, 0x64e8beb4, 0x26e9d179, 0x8a888760,
4230 0x3dda417d, 0xdb6fad22, 0x08fd9b10, 0xf919db51, 0xec78c037, 0xdb52fad4,
4231 0xd1b93119, 0xd62bbb1a, 0xc7c9a713, 0xea6b2517, 0x69a49427, 0xbf4e07ca,
4232 0xc83e534c, 0xa7c9ad9b, 0xa9a95f94, 0x5f2ea43f, 0xf0b61f93, 0x54fd4d5a,
4233 0x3e4d26f9, 0x344ff97d, 0xde3787f5, 0x64bf29a5, 0xfca68565, 0x4d02ff52,
4234 0x3f75f2fe, 0x151fd4d3, 0xbf29a458, 0x4d11e5a2, 0x13e0e8f9, 0x3d98fc9a,
4235 0x8fea6acf, 0x29a35f6b, 0xbd787f1f, 0xc7427ca6, 0x529e4d26, 0x72e279c2,
4236 0xcf81179e, 0x07ebb309, 0x0b9ed099, 0x37984dda, 0x4ed0db25, 0x5ccbda0f,
4237 0x4d1d29c7, 0x006baf06, 0x8486814d, 0xc979dbae, 0x507497e5, 0xa577df3a,
4238 0xfd2712f7, 0x7bc99f7e, 0xfd823385, 0x902fe949, 0x065d4824, 0xcbe5f548,
4239 0xf97fc624, 0x1c461729, 0x0d6beda1, 0x696223dd, 0xf790cbbe, 0xf1f94094,
4240 0x7c80c159, 0x3a922d19, 0x266d17a8, 0x4b2ff768, 0x564179cd, 0x21f2e7f1,
4241 0x3084ee54, 0x3792e5dc, 0xe78aec09, 0xc193dfeb, 0x421868ce, 0xc84c95e7,
4242 0x82f784af, 0x3f6d0672, 0x4bc92ca4, 0xd44d99e1, 0x6ff7570e, 0x6267fda2,
4243 0xffd04dff, 0x37fa3efa, 0xfa6ae5a7, 0xae5a1a8f, 0x44ca3fe9, 0x3b5277fb,
4244 0xef10feb3, 0x4ae9129f, 0x0e115e42, 0xa1e6ff61, 0x32ffd8e5, 0xa88fdd13,
4245 0xf50e8ffb, 0xf1f20cdf, 0x109ff43a, 0x5769fe61, 0xb43fe76a, 0x137f3b42,
4246 0xfaf6ff9b, 0xa3fef33f, 0x0a6ffe71, 0x1ff3667f, 0x6fe6c15a, 0xfd437066,
4247 0xdff8423b, 0xa77ff309, 0x4fa7f9af, 0x587fced4, 0x66fe7695, 0xf5bbffd6,
4248 0x36ff7927, 0xe13dffec, 0xb0ff9b24, 0x64dfec2a, 0x7f81baf6, 0x75d1294c,
4249 0x193fda7e, 0x40d1154c, 0x0fda1760, 0x28e323a4, 0xb0f21313, 0xb8e38690,
4250 0xdbf19a2f, 0xdf94d117, 0x88c8bf50, 0x9aa7e21f, 0x6a43ee8c, 0x6e542cb8,
4251 0x1e8133c8, 0x1fba72c2, 0x3a87cb99, 0xfe4445a7, 0xfd994f26, 0x3b78e9c3,
4252 0xf219445b, 0xe49a9e73, 0x6b577d07, 0x40967726, 0xc209233b, 0x1e9e4ff7,
4253 0x2f3d46b5, 0x51b73a7d, 0x91a1d13a, 0x391e362f, 0xa3ac8c9f, 0x26042be3,
4254 0x9fce1718, 0x421dfba0, 0xe94711f7, 0x93d2027e, 0x7e8fed12, 0x43f74e3f,
4255 0x9b96a4c4, 0x64476c7a, 0x7419fbcf, 0xe512b7fc, 0xde79c1e7, 0xe1452281,
4256 0x4ffe1919, 0xd0357dd0, 0x95a36e63, 0x1e3c3f22, 0x6f9c1f3a, 0x5fe0a977,
4257 0xd2bc7023, 0xf6f1b7f6, 0xe147c604, 0x36b272cf, 0x0f72511f, 0xb79f28a2,
4258 0x67035e32, 0x4d2ff106, 0x5f6feda2, 0xb42243b1, 0x74a141ce, 0x97e002c8,
4259 0xc4122407, 0x0247647d, 0x40cce4c9, 0x0c9d7be1, 0xa5d36dfe, 0x382a1de3,
4260 0x4f28a4b3, 0xaccf1d09, 0xef1c45fb, 0xbcb6af0c, 0x63d5bb63, 0xcae9a2c8,
4261 0x494224cf, 0xb6b97b7e, 0x6d3a8efc, 0xda85cefe, 0x098f9d3c, 0x5952b5d6,
4262 0x874e9dff, 0xd0aef3ce, 0x69c4e9bc, 0x9b2f367e, 0x35925cbd, 0x686d8474,
4263 0x034f2f0e, 0x13c413b4, 0x5def4fb6, 0x2681f29f, 0x0ea56f3f, 0xff8be71e,
4264 0xddffff4f, 0xc96daff4, 0x1aae3f8b, 0x9ae07557, 0x7aaae3f8, 0xd46eeb95,
4265 0x67fbe7e4, 0x5bcfea68, 0x9f29aa59, 0x535f38db, 0x4ff97b3e, 0xf952f935,
4266 0x3bfd4d7e, 0xca6bd617, 0x587ba8ef, 0xf97b7e53, 0x0cfc9ae3, 0xf5352fef,
4267 0x5abe9b6f, 0x9f6c2e53, 0xd703ac3f, 0x41b0ef4d, 0xa3fc0fe0, 0x299f0099,
4268 0xfbf0acfc, 0xa6125f29, 0x4c2e7c67, 0x530f41eb, 0x8d786efd, 0x4a6bb5a5,
4269 0x573e8187, 0x54a4fff8, 0xa5f41437, 0xfaf59f9e, 0xf4a7cf57, 0xcec91297,
4270 0x812ad250, 0xd63ac094, 0xe55eedc5, 0xcebe39fb, 0xd308b211, 0xcb93132a,
4271 0xf2834daa, 0xc1f20389, 0xbeb67511, 0x808092e1, 0xcde020f3, 0xa5ba004c,
4272 0x4d4bb5d0, 0x38cd74d7, 0xb110eecf, 0xc9901aff, 0x94dcb009, 0xff40326c,
4273 0x37a1b6c1, 0x78f1828f, 0x25be6336, 0xb3aded01, 0xe3f8a2be, 0x095fc046,
4274 0xd37ca7a6, 0xf3e13d31, 0x57dc7a62, 0x5f51e98e, 0xbe1da61d, 0xec7e9885,
4275 0xd0fd3193, 0x3fd31cb7, 0x3d311af9, 0xe9895bec, 0xd31f9f41, 0x53079f4e,
4276 0x55ff4f85, 0xf0ca3ae8, 0x73d74edf, 0x328eba6a, 0x3878d938, 0xf1851f5d,
4277 0x939bb046, 0xa71918c1, 0x563c47b2, 0xe02eabf4, 0x896a70fe, 0xef2b3f31,
4278 0xd705317b, 0x7f8b768e, 0x9ee1e824, 0x011b7f91, 0xc39ee47e, 0xed480174,
4279 0xfa7a7e7b, 0xe20789f5, 0xccbdfb41, 0x3187174f, 0xd12dcbbd, 0x0316af0c,
4280 0xd4d92229, 0xa2fe1b5e, 0xcc4caefb, 0xb41c491b, 0xb46fbbf7, 0x6d4b8047,
4281 0xc5efc041, 0xfed8baf0, 0x3bc01645, 0x39d7ecf1, 0xa4328e90, 0x4db8bb31,
4282 0x0494bb44, 0x7e03705f, 0xecd67a43, 0x6d3f024e, 0x139370f7, 0xb8a7bdd7,
4283 0x9fc15a9f, 0xfe0af2cc, 0xafe10e1e, 0x97f10931, 0x14bfc5f1, 0x3ba788fe,
4284 0x6151a6eb, 0xbe139dfc, 0x39ca7f1d, 0x1bbfbe89, 0xe277e344, 0x0544aecb,
4285 0x0943edaf, 0xe02de7ed, 0xa7bf0a7f, 0xc01892f9, 0xd93ec873, 0x87f7f662,
4286 0x4e80e74e, 0x6abc30b6, 0x3d9ebc1d, 0xeec0382f, 0x7064905f, 0x67808f1e,
4287 0xa40ead25, 0x3b6a6d3a, 0xef9b45a9, 0x028a1469, 0x62b8cf68, 0xfd028da6,
4288 0xcf1e74eb, 0x84993d00, 0x416702a9, 0x3c79c992, 0xe4c3e91e, 0xca2c437a,
4289 0x145f19fd, 0xc7a1fbd6, 0xf09c17d1, 0x31c99a38, 0xf9501eda, 0xf5df7a4d,
4290 0xe353e4fb, 0x37e04c5f, 0x17d2ad23, 0xd144bf60, 0x0381bfff, 0xbcc46232,
4291 0x2036b702, 0xe02be6ca, 0x7f4d06fb, 0x394b9db4, 0xed26fbc3, 0x48c1e4db,
4292 0x4afc284e, 0xf0468a97, 0xbe038d49, 0xf6b538b5, 0x5f26ac51, 0xa9c832db,
4293 0x1fe097b1, 0x72928f54, 0x577c08c1, 0xcba6d9c5, 0xd02e5b68, 0x538255f1,
4294 0x6055f80a, 0x3aa3aaf5, 0xf0175e4c, 0xaf5be2cb, 0x46cd4172, 0x7c7eaf9c,
4295 0x1a377e94, 0xbf8f7d8d, 0xafb9ec52, 0x6c7c8224, 0xcabb7ae1, 0x240afcc0,
4296 0xf9c0764a, 0x1d924917, 0x6871d937, 0xd07e10b6, 0x51fb470f, 0xf33815e5,
4297 0xd6b752fd, 0xcf91957e, 0xbf981acf, 0x6eefdf40, 0xe2e137e8, 0xb0d9abf8,
4298 0x5bcc0a7f, 0x969ac78f, 0xca2f26f3, 0x272ffd15, 0xbf05478c, 0x6ec96295,
4299 0x58afc291, 0xd5f70477, 0xc47924a7, 0x17a2df03, 0x96df8f7b, 0x9aaac274,
4300 0xa1da4cb7, 0x7972bb9f, 0xdb75c447, 0x9f5f5407, 0x1e44bdfe, 0xa05cba01,
4301 0xa0e354b5, 0xe4310516, 0xbbf5ed84, 0x618b2b9a, 0xfb0d3efd, 0xe72faa15,
4302 0x38071290, 0x6349cb1d, 0xe7e7d80e, 0xf008a188, 0x87fc8e74, 0x4e8a8c63,
4303 0xe2134467, 0x47efda89, 0xf6a3e3d5, 0xed4f26bb, 0x8cbe4d77, 0xe70894dc,
4304 0x494f65d9, 0xfce02fc4, 0x127fe534, 0x79f7489d, 0xec01aea4, 0x5b12c59d,
4305 0x1272efd7, 0x5f1d0a63, 0xe5cfabf5, 0x79fcd294, 0xca23d991, 0x38fcec79,
4306 0xc08afe36, 0x9687936a, 0x731e6b1f, 0xda0455eb, 0xfd601bfb, 0xee08b791,
4307 0xf8deaeb5, 0xd7e3aefd, 0x87b1578f, 0xf30b9d7a, 0x13af5471, 0x7648fe3c,
4308 0x8533e711, 0x4e8c631f, 0x45237f8d, 0x9744bf97, 0x7fcba31f, 0x401f796f,
4309 0x295ef234, 0xe38c537a, 0xfec37c98, 0x2376304e, 0xf86f7f3f, 0x5fe0bd49,
4310 0x1fc283f2, 0xd13393ac, 0x8507e63b, 0xfc6bd19f, 0x5f824757, 0x5b4beafd,
4311 0x2a9faa65, 0x41da795e, 0x6d3a7ea8, 0x53744c6c, 0x5dad57fa, 0x383e00ea,
4312 0xc01d9465, 0x62fda7cf, 0xbe823f91, 0xf0a8d7bb, 0x8026c783, 0x49fe0dff,
4313 0xff599fe1, 0xaeb0f5e8, 0x7256b17f, 0x9d6d5fa2, 0xf2a66839, 0xbf3cd35a,
4314 0xfe616498, 0x3b2fcb08, 0x45be422f, 0xbf159fcb, 0x85d13a7e, 0x314e52fa,
4315 0x8838ffa0, 0xd34d7ff6, 0xdd605327, 0x28dd25af, 0xd076fa67, 0xb87157ff,
4316 0x629a953e, 0x46e3977a, 0xb3da113e, 0xa3f36d5f, 0xfc0745e7, 0x06fd03ab,
4317 0xdce5fafa, 0xda332f8e, 0x1afea007, 0xfe83c64f, 0xfc41f052, 0x5f178ecc,
4318 0xfc0b2e7d, 0x7e9b67a7, 0x785410ef, 0x27ace452, 0xaf57fb30, 0x97d6fabb,
4319 0xd50e549d, 0x4f62a3f6, 0xfef85ab8, 0x55a595a3, 0x1571d052, 0xab5593d5,
4320 0x3f4cb725, 0xc2f4bd57, 0x3f82cf8b, 0xf7668ff3, 0xf2bf0a70, 0xaf075da5,
4321 0x8dcaf9a4, 0x366280d2, 0x18909b0d, 0xfd2d4ba6, 0x9876617f, 0x779b150e,
4322 0xd8a35c99, 0xc2e307f7, 0xb8dca8f4, 0xf54644c3, 0x604147c6, 0x16c3a987,
4323 0x23812e81, 0x12fec053, 0x09bbfd5f, 0xbb7a7ee8, 0x46a60640, 0x5deae7c0,
4324 0x9e019f68, 0x4e9c8e90, 0xeae9ba21, 0x80ba52d7, 0xa4e8573e, 0xfae22f2f,
4325 0x32b9e004, 0x7e5f9f91, 0xfe84e21d, 0xfcc37664, 0xdbbe5fcb, 0x6938f301,
4326 0xfd7c63ac, 0x0f44d2dc, 0x925cb7ed, 0xb2989d13, 0xdfcfe5ef, 0x6f36fc8b,
4327 0xcc89bdff, 0x6419e58f, 0x1e49b5c0, 0xbb9bf304, 0x5f9c16ea, 0xdf22f119,
4328 0x96273f95, 0xdcfc7e80, 0x46368a48, 0x8d4f8b90, 0xb9380ecc, 0x74b81a86,
4329 0xb2e9277e, 0xff337183, 0x14fc6221, 0x3f453f21, 0x2e7cbdd9, 0xfcc382d4,
4330 0x4e8c51e7, 0x5c0d196f, 0xaf15a8ae, 0x65a6d7e6, 0x339f40ed, 0xe1033c43,
4331 0x1896a5bc, 0xe10f8e65, 0xdc570a1b, 0xd190385f, 0x398cb887, 0xc3b51dbc,
4332 0xd43be00a, 0x963c976f, 0xf23b4d2c, 0xffb86a4d, 0x74ff787b, 0x3f60d1dc,
4333 0xbc8c4c9d, 0x2928180f, 0x71d74f72, 0xe4a97f15, 0xd37bc99b, 0x15be4cc3,
4334 0x58dff779, 0x397fe504, 0xda07e4c0, 0xc748fac1, 0xe5881c15, 0xa809a63b,
4335 0x1824cc0f, 0x249bae49, 0x72dad72e, 0xb8e84f85, 0x8a8c428d, 0x1c7e005f,
4336 0xa6ed1fe2, 0x3b68a7b2, 0x85acbe95, 0xe1bd1cfe, 0x8f3b7229, 0x9009ffcb,
4337 0xf2c3cbff, 0xb931564f, 0x95bedbef, 0x92553f11, 0x4167c5ff, 0xca7ca95e,
4338 0xa957902e, 0xe9fde604, 0x3f83b686, 0x69f272a1, 0xad539140, 0x69cbd4fe,
4339 0x097ba6f9, 0x4e5ea7f0, 0x475c1d3f, 0xfd29ca22, 0x074e511e, 0xea97fc77,
4340 0x0e7f054f, 0x153fab49, 0x1e17d87d, 0xb7f0faf5, 0x53e21746, 0xefe90faf,
4341 0xcde9c900, 0x29df0a7f, 0xdbf156fc, 0x77a061ea, 0xf0a97c42, 0x152f885d,
4342 0x57cfd3be, 0xf97d3f8b, 0xd199f061, 0xf6bc9571, 0x4a1494fe, 0xc156aacf,
4343 0xbb61766d, 0x78a790dd, 0xbfb330f2, 0x00ca7771, 0xcbafde75, 0x3df57407,
4344 0xae897cba, 0xaf9757be, 0xb3f7d5d3, 0x9b4b487d, 0x041f2089, 0x45a5f535,
4345 0xfc738644, 0xee226dee, 0x98e8bbbb, 0xaefb681b, 0x997ea90d, 0x16a583ea,
4346 0x4eefbfb6, 0xfe803530, 0x3b7672ea, 0x616f20e2, 0x92aeb5fe, 0xcaac476e,
4347 0x2ad23c3e, 0xf0edfea2, 0xfb48a293, 0x22d16a13, 0x5f483a9e, 0xa3bcece5,
4348 0x5d0db450, 0x46977e08, 0x81ae0dd1, 0x39b7f539, 0xaba1bce0, 0xe986fd35,
4349 0xb7dcfbf4, 0xe85f0c45, 0xc164768a, 0x31ec88b8, 0x0bed520e, 0x99f9114e,
4350 0xb33e7489, 0x60fed95b, 0x5d9d0ace, 0x5f205641, 0x31eed994, 0xf6a45e81,
4351 0x9fad51fc, 0x0577f19e, 0x4abe5787, 0x57b4ae5b, 0x4d158df6, 0xdf2f72da,
4352 0x5c495667, 0xa3268c5f, 0x308f3ed9, 0xafd7093f, 0x0de66285, 0xbbfe29d3,
4353 0xf80488f6, 0x4455a7a5, 0x106cf7fc, 0x226fe0fc, 0x4dca0272, 0xbd46e90d,
4354 0x2ce9e0a6, 0x6fa985c8, 0xcb7673bd, 0xd00f3947, 0x3f5b552a, 0x9a77fac8,
4355 0xc7fadd9e, 0xfe406f11, 0x3f4343d5, 0x17ebbd20, 0x79e0b76c, 0x3b76d76e,
4356 0x6d76afc6, 0x01f437db, 0x7666bfc8, 0xb6bb38c3, 0xfc05997f, 0x5cc8b5d3,
4357 0x6bab7a0e, 0x2cd7db08, 0x5665f6de, 0x4b93ae07, 0x90bf6e90, 0xa7aabed8,
4358 0x858febf5, 0x59d29001, 0xddbffac1, 0xda9dfe8a, 0xa7182dd7, 0xcbedb5db,
4359 0x87edaf1c, 0x3f0d4f9b, 0x93b2efbf, 0x7c609be9, 0xba7cecb1, 0x2f098df6,
4360 0xabfed3d4, 0x6698779b, 0x3782f2d3, 0xfa059eff, 0xb3136bb0, 0x8ea53a6b,
4361 0x7a7ce1e7, 0x8bedd2cd, 0x4ee78a24, 0x42648a10, 0x4df0d47e, 0x09199cbe,
4362 0x7f477f2f, 0xf1f17f53, 0x7c18ffda, 0x53ef1808, 0x47f76ad5, 0xbfef3009,
4363 0xe801fc7e, 0xe466ed81, 0x9fbe654b, 0xeed1ea06, 0x0fbcd8b8, 0xfdc7bcc3,
4364 0x085bcd2b, 0x5fde67f6, 0xfbd393fe, 0xe385c921, 0x6f41cbd3, 0x1f76df3e,
4365 0xbbb25fe6, 0xe4fdbc71, 0x7fa681f7, 0xa26fba31, 0x7c5c7774, 0xe4ff39de,
4366 0xee9beef3, 0x74e2cf6f, 0x8c7de277, 0xe38eff37, 0xee7aaefb, 0xf3a1ffd6,
4367 0xb373ec57, 0x8f3da4a1, 0x693a6f8e, 0x316183b4, 0x2f67a123, 0x8799c484,
4368 0x8c0065fc, 0x8ae7e257, 0x332df1fa, 0x048ffdb1, 0x5fb4c6e7, 0xf7c08b72,
4369 0x743f6c75, 0xae1fb73d, 0xf6865c1f, 0x661ef5e8, 0x496313af, 0x8858de49,
4370 0x46e39aff, 0x3ec9273f, 0x2dfc85ec, 0xbb5e7893, 0x20577c2f, 0xe3da811e,
4371 0xda2d0fd7, 0x0de9f603, 0x33418d83, 0xfa408f4b, 0xcf7f83be, 0x665feed5,
4372 0xdbf9b578, 0xb7f36ba6, 0x82b77870, 0xbffb4571, 0x83f044b5, 0xf21a535f,
4373 0x39f80254, 0x1112b9a5, 0xa9138804, 0x84fb0a5b, 0xedb44a5b, 0x767ec367,
4374 0xf38f185c, 0xe153bca3, 0xa46a21fc, 0x61b8f880, 0x24fa8885, 0xf840532a,
4375 0xc612b925, 0x28627e13, 0x173c01c9, 0xf35f198f, 0x0dce0633, 0xf1cf9df3,
4376 0xd0ea4655, 0xbe1721de, 0x0e6266f9, 0xda0973f8, 0x843df34b, 0xf5ed475c,
4377 0x304289b2, 0x3ce5ca9a, 0xb2639123, 0x9029cfc1, 0xa73f1aa3, 0x1fbf0f36,
4378 0x5ce18625, 0xfc5f7eac, 0x7fa743f8, 0x347ffca6, 0x90cdda83, 0xf33bb9e2,
4379 0xaafb29d7, 0x1e195b3b, 0x7f04ab6b, 0x5055f21a, 0x7c539f52, 0x85fe626d,
4380 0x06383f3f, 0xe7ef2ae5, 0x7ed862a3, 0xcced032f, 0xf6676e5a, 0xf018aec8,
4381 0xa6b4f46f, 0x02b1f3f3, 0x3f023787, 0xadfbe7ef, 0x3ef9c03f, 0x0b26bb4d,
4382 0xfdd8228d, 0x78fd1ba4, 0x590b64f2, 0xee0e211b, 0xa7e29303, 0x1ffdc3a8,
4383 0xa01cc4fc, 0xa3cdfb23, 0x54e2634d, 0xdd715b74, 0x6f566369, 0xa8efc03a,
4384 0x1fe83cea, 0xefec2fc5, 0x2dfbaf00, 0x224a531d, 0x971cf7cc, 0xfeb7e2df,
4385 0x6eb5f78a, 0x00954d6a, 0x164d372f, 0x9fa6e735, 0x75bef898, 0xe303190c,
4386 0x1aeb7e2a, 0xcba004c7, 0xf70dd11e, 0xcf5b6ab3, 0xce11bc9b, 0x04f8f48f,
4387 0x97dfe8f8, 0xcf8065dc, 0x42c7ff63, 0x8fb59f60, 0x4264e79f, 0x6e2674bc,
4388 0x4fe03de5, 0x75e382fa, 0x7489d9aa, 0x4f38b9be, 0x66fda04a, 0xc3473b36,
4389 0xaf325691, 0xad16153f, 0xc11c1071, 0x92f529da, 0x23bd58ab, 0xa44d6726,
4390 0x128a2ff9, 0xfb8579f8, 0x9fe15cbe, 0x3f796e8f, 0x61f307b7, 0xeecc993d,
4391 0x6be6f5d5, 0x53d1f282, 0xdf41f824, 0xf309fec3, 0xe03eecc5, 0x972b033e,
4392 0x597a626f, 0x9e3d7be1, 0xcf0ccdd3, 0x3c05ff4a, 0xf0ccd23f, 0xc159e0a3,
4393 0x4abc7eaf, 0xaeafaa7d, 0x6e21fb56, 0x32fd1968, 0xad3587ac, 0x4140d382,
4394 0x4c3b18d5, 0x2db58720, 0x67e04b8f, 0x7062e19f, 0xa5907ae9, 0x6a9dd73e,
4395 0x6debe766, 0x02cd57d9, 0x056cf93e, 0x7b684bb5, 0x0ef39ccf, 0x19f77758,
4396 0xbdc1efdc, 0x915df949, 0x7d16fdac, 0x79cf81f5, 0x1aa364ed, 0xf38e2a6e,
4397 0x093caae6, 0x57b726dc, 0xaa0690ed, 0x39aa69f8, 0xef95cb0e, 0x6cae55c9,
4398 0xc3fb4ef8, 0x998fc871, 0x6787c409, 0x3ef1da06, 0xb175edda, 0x03cb0f8c,
4399 0x4f984c3b, 0x7f4afac5, 0x797a3f4a, 0x8dac569a, 0xd05d99fb, 0x52f01831,
4400 0xe3de0e6c, 0x9da7c08e, 0xbbe40e9c, 0xca1e13ae, 0x8bff59b7, 0x947b89d6,
4401 0x2a43a275, 0x6c89c551, 0xa73d3335, 0x4606275a, 0xd416275a, 0x1d0206bb,
4402 0x1f4b6c16, 0xe0b24208, 0x48c4c2ed, 0x3efbc4eb, 0x88785e76, 0x9aecdfdf,
4403 0x2b89d746, 0x34c4eb54, 0xbe89f20b, 0xc4acdf9d, 0x9d645d61, 0x5ff6e850,
4404 0x87de6fac, 0x7c822275, 0xd76b366f, 0x4b5b5b89, 0x75b89d71, 0x57b9a89a,
4405 0xb17cdeb1, 0x712f2275, 0xb725e606, 0xbcff0235, 0x43e1edcf, 0xfa0ebe3c,
4406 0x34e2f581, 0xde84ffe8, 0x7a5f46eb, 0xeafeb1fd, 0x3c26fff5, 0xc17d7a2b,
4407 0x781eec2d, 0xc8243e6f, 0x50660bcf, 0x3f002ebd, 0xe0bebd32, 0xd317ee0e,
4408 0xd012d9e9, 0x7ad563b3, 0xf1afb596, 0xb6a175b2, 0x3317f525, 0x1a4ff969,
4409 0xad147725, 0xdeb093ff, 0xddeb51cd, 0x1377a0d3, 0x72dde822, 0x6b3f77a6,
4410 0x53f6831d, 0x88fbf35f, 0xcfaa5beb, 0xf811dc32, 0xab4cfa63, 0xb1ce9ee6,
4411 0xdccbbfd1, 0x4fb2f20c, 0x4fbb73c4, 0x77b01db8, 0x82c6eff4, 0x144a7a9f,
4412 0xa71c4f1b, 0x5c8fa767, 0x81ea993b, 0x9ecc3982, 0x2220deae, 0x999a6afe,
4413 0x4464d7fc, 0x3f345dfb, 0x26affb25, 0x636e57c8, 0x06746fe7, 0xfa2a79c5,
4414 0x68ebee57, 0xe5703f00, 0x0fcf016a, 0xf019ce21, 0xb3e38f39, 0xfb895dcc,
4415 0x80fc7d15, 0xe6ad17e2, 0xaeb7e6f5, 0x3ea9ff46, 0xe33aa0ae, 0xafb0d3da,
4416 0x3a333628, 0xfc166f14, 0x1ce153ab, 0xfdcf575b, 0x541b9e30, 0xc7dfb407,
4417 0x15cef9f0, 0x619b9983, 0xe89ef55f, 0x8dceb48e, 0xfca5e3d1, 0x7ecbc41f,
4418 0xffb1978a, 0x17d2f1ef, 0x8f7da81e, 0x3e3d64fe, 0xbd7145c6, 0x82c64d92,
4419 0xf0627e1c, 0xdf915ea0, 0x642e3111, 0x35c3e3ce, 0xa20bfef7, 0x67dabe98,
4420 0xdc4036f0, 0xe2c35cae, 0xdaade647, 0xe6912bb8, 0x68c80667, 0x5bcf4770,
4421 0x43875da9, 0x0bb37eeb, 0x7599f5d7, 0x1388051b, 0xfdefcb9c, 0xc71ffb94,
4422 0x58ee12f7, 0x5a79d748, 0xd9b6767f, 0xfb9fe70b, 0x37a8dd2d, 0x105dbe15,
4423 0x3a97ecc5, 0xc9638e3e, 0x7d7193dd, 0x289c116a, 0x5b0b418f, 0xe09d28af,
4424 0x09b6871d, 0x74e14e5f, 0x16887e61, 0x4a5ac746, 0x29e79037, 0x8ebf3cad,
4425 0x2bb781d9, 0x77e080f9, 0x7757a009, 0x085dec48, 0x9c0bc481, 0x11f5aa08,
4426 0x12f2d5ce, 0x76de7455, 0x5afff184, 0xfc1f8dc1, 0x43efbff4, 0x9ef93ee7,
4427 0xe5fd31d9, 0x0b4f0577, 0x6fde7474, 0x831e2f69, 0x1b8233e7, 0x8d68c7df,
4428 0xe38573c5, 0x079dec8d, 0xcbd3b799, 0x5c3bec05, 0x8dcabf2a, 0x1f887030,
4429 0x9c60b22d, 0xc69bf61e, 0xbded32ec, 0xd7135940, 0x4ee35df3, 0xda3b496a,
4430 0x3178e163, 0x802637ef, 0xb5182457, 0xc8dd5c71, 0xfc003fe7, 0x02dfcdd7,
4431 0x3139249f, 0xa76ef46e, 0xeec9ddf2, 0xdb7cf06f, 0x33439c90, 0x5b3f7e29,
4432 0xdd79e22e, 0xc1d7066d, 0x1e6fa089, 0xcbc80891, 0x0f257b67, 0xb8ac075b,
4433 0x3bee94ee, 0x4a5ef786, 0x2911ec59, 0x2fad887d, 0xfe78f8c7, 0x0f6dd744,
4434 0x604844f8, 0x4dfbc41c, 0x7428ef73, 0xec64df81, 0x2e70a5fe, 0xf3817376,
4435 0xe7a041e0, 0x93bdecc3, 0x700bcba3, 0x4ff7769f, 0xc3b79405, 0xfed06e94,
4436 0x07a96996, 0xef7ed20f, 0xe7809e58, 0x093d335c, 0xd7b9c2b7, 0xdba2bdcc,
4437 0xbecdeb45, 0x73836ec1, 0x4523a9af, 0xe7e155e2, 0x7e8ed20e, 0x3f75999a,
4438 0x5dc605bd, 0x3143d74e, 0x85fdd215, 0x4abf2103, 0xb2b5f6c0, 0xb29034d7,
4439 0xf3cafb4e, 0xffb4b1a6, 0xd00f5a32, 0xd58abb5e, 0xdc126dab, 0xd65b7a10,
4440 0xcbea38fa, 0x1f0126b2, 0xf6a76896, 0xeb83146f, 0xdb70a28f, 0x34f6d157,
4441 0x03da0f3f, 0x5bd8a6dc, 0x96ab3ce1, 0xe7db138e, 0x6479e3d6, 0x8b476d19,
4442 0x4fd37b49, 0x55fcde11, 0x447b8102, 0x8fa9b9e5, 0xbdbc02e5, 0x0fca1b92,
4443 0xc625f8ed, 0xfda2cc8d, 0x67f0a20d, 0xe8851d8b, 0x70407b57, 0x83233be2,
4444 0x5d7e9033, 0x70686130, 0x64fd0d3c, 0x42e9d718, 0x71d51834, 0x1616c908,
4445 0xb0b65cdf, 0xd5e601be, 0x1aa42721, 0x9bceaf90, 0x4e3f1d60, 0xf6a5edf1,
4446 0x8b1331eb, 0x8f93686f, 0x7a543a99, 0x1d25bc74, 0x969cd8f5, 0x9f2f3c3c,
4447 0xbcf04a4b, 0xeccf5bdc, 0x2d4b2391, 0x30ec017e, 0xbe1439c9, 0xe3352db7,
4448 0xd897cef7, 0xa439d3fa, 0x27a1fd03, 0xee044957, 0x955e2d39, 0xf1d00cfe,
4449 0xf90906e4, 0x424e7c4d, 0x25ef363d, 0x5b6b27e6, 0xbc9ee0c5, 0xcfdec4c7,
4450 0x9f9a7281, 0xff651bf7, 0x6563d5ab, 0x53d40aae, 0x2bd4bd7a, 0x7aa9efee,
4451 0x2f6cb013, 0x14cf757d, 0x741557d4, 0xeb4601dd, 0x3706afa5, 0xaf52bfa0,
4452 0x4d896aaf, 0x10d953d1, 0x3d5a5237, 0xe04ad664, 0xc0583be3, 0xb5f07b76,
4453 0x75869fcf, 0xe04ecab7, 0xf9d18d4b, 0x82f8c08c, 0x6cccbc80, 0xc839f8dd,
4454 0x0b4cf941, 0x0273bbbe, 0xb37200e8, 0x59c59e22, 0xdf114bf9, 0xbce51c4a,
4455 0x573e5a95, 0x7867b5ce, 0xaf51e245, 0xe256e55f, 0xf43bd551, 0xda57e510,
4456 0x822d9dcf, 0xfe4022df, 0xc77beec8, 0xe389de62, 0x83edc85a, 0xe7e47615,
4457 0x5f9ff743, 0xeb3afc0a, 0xbd808141, 0x036f644e, 0x2b3587ac, 0x65f81705,
4458 0xdac83de7, 0x61eda3cf, 0xc97e87dc, 0xb7f28af8, 0x66bff80b, 0xb1bbe3d5,
4459 0x02e0937e, 0x975687f8, 0x2e513da2, 0x9bcb048b, 0x81fee08e, 0x5f1853ae,
4460 0x898b26d4, 0x4b35ffc0, 0x95304ecc, 0xf8523e14, 0x17bf08f2, 0x59dca24d,
4461 0x9f76d337, 0xde849000, 0x174e28fc, 0xf029eb42, 0xf8ccad49, 0x924bc8ec,
4462 0xe2e6d81b, 0xc3eec97c, 0xabebe49e, 0x532ddcf8, 0xd73cc106, 0xb68638b2,
4463 0xb0260555, 0x05fa4e23, 0xcdef8f3c, 0xb6a6c497, 0x7cbe14a3, 0xfafa604e,
4464 0xbda87162, 0xa5f38ef8, 0xa9947fc2, 0xb5595f71, 0x0f702257, 0x5e8fcf57,
4465 0xc42b7029, 0x4cbe940b, 0x5bc743e7, 0xda3f70d0, 0x691e0aeb, 0x65f2113e,
4466 0xa1ef1646, 0x91b543c8, 0xe77d05c5, 0x37fae9f1, 0x7961ec5b, 0x4adc5910,
4467 0xbbfbf690, 0x9c602f0d, 0x47f5b9dc, 0xe6fb47ae, 0x8007ca0d, 0x12760dff,
4468 0x1f87fdc4, 0xb34550f5, 0x4238c1e8, 0x66e73063, 0x895dbed5, 0xc57ca897,
4469 0xd8aef88e, 0xd317f664, 0x8f5b15f6, 0xf5f9e165, 0xe78c6ea2, 0x680bd790,
4470 0x23b9131f, 0x546fee0b, 0x86dc5918, 0x64582ede, 0xb3aa7e61, 0x83a759af,
4471 0x63ac26dd, 0x045569ef, 0x2acc936e, 0x16fdeebf, 0xe787a949, 0x33a53229,
4472 0xf18693dc, 0x5271dfa9, 0xfece35e2, 0x455ff186, 0x5cf6848b, 0x9d8dbac5,
4473 0x71577f10, 0xdcfb8cd8, 0x31e775da, 0x95e0b89e, 0xae1df097, 0x135116da,
4474 0xee2bd57f, 0xe7889d69, 0xd5cd351b, 0xf341bf18, 0x1351ce78, 0x77ff1c88,
4475 0xca9cf8b1, 0x956db657, 0x372b0a29, 0xef81daff, 0x75afb572, 0x7593bde0,
4476 0xd8771edf, 0xf029ce2b, 0x39c6b7f0, 0x507f819d, 0x45adfac6, 0xd644e71b,
4477 0xc746bd31, 0x9ee91397, 0x7adec841, 0x21e7f3e9, 0xa6ecf70e, 0xf1879f4f,
4478 0x67e7fd56, 0x061c43cf, 0x82716ed9, 0xfebb523d, 0x54638c7d, 0x30b2edda,
4479 0x37f3affb, 0xcff8c6bf, 0xdd9a3fce, 0xdb73ad00, 0x6f60a1c9, 0x6bfc6e74,
4480 0xde75c422, 0xfd10adb3, 0x296cf739, 0xf8224818, 0xf814940b, 0xf88fdfd6,
4481 0xdabd3d53, 0x5e30db9a, 0x37a51ce4, 0xdc5087e8, 0xc59aa05a, 0xbc78ba01,
4482 0x71c886da, 0xd3e2bdbe, 0x61be6f9a, 0x66c5e812, 0x345c1766, 0xa500ed4e,
4483 0xa0fd15e3, 0xb98786df, 0xbf4c893e, 0x4a0ff073, 0xfa3a63a7, 0xf73cde7d,
4484 0x5942cf57, 0x719f7c73, 0xe07ec16a, 0x0e23894d, 0x169d3c58, 0xbf4d9b90,
4485 0xa040b8c5, 0xf40bb15b, 0xc143e7f3, 0xea4a7c2f, 0xf743ff46, 0x5bde3336,
4486 0x0876d8ab, 0xcb73a7e5, 0x25d38c7e, 0x93b79e3c, 0xfe2c7e84, 0x6a7afb92,
4487 0xbe2cec9b, 0xe21fe38d, 0xfc0e5cdf, 0x18dce3ce, 0x6ff12b1f, 0x0dbdc57d,
4488 0xefe34e8f, 0xbcf8b02a, 0x780fa6ea, 0x5e98591c, 0xe9d02e42, 0x13c6b7c8,
4489 0x0270782a, 0xe3abc61e, 0x17c72338, 0x397de286, 0xa07e80bd, 0x9a7143a7,
4490 0xe2183f34, 0x21c2fcf6, 0x741f4112, 0x9ff166ae, 0x1ef6929d, 0x2c3e9868,
4491 0xad15d3ae, 0xff7f5393, 0x362f39e2, 0x9f8aeffe, 0x269768d8, 0xd3c151ae,
4492 0xf5910bd9, 0xf0b44178, 0x9a93dd8f, 0x05efe823, 0xc02747e4, 0x1311f979,
4493 0x7c5e7bc1, 0x37dca4ff, 0xb3b4fee2, 0x0b8c45eb, 0xa1b4086c, 0x8bebd71e,
4494 0xa24e7e1a, 0xd12def1f, 0xb4d54f4c, 0xece275b0, 0x46dfbb26, 0xeb7d9ce1,
4495 0x9ae7e435, 0x324c470d, 0xdd7bb785, 0x2b8b1366, 0xeb03f260, 0xfe355f84,
4496 0xc8ef2fb3, 0xdfcdbd42, 0x33f7d215, 0xdb53f79b, 0xda9fb91a, 0xfd35e70d,
4497 0x9301ca54, 0xfef176d3, 0xb73d18ce, 0xed33bc01, 0x133a5ecc, 0xdd228b10,
4498 0x2d12998b, 0x2373fdf1, 0xf5d373f3, 0xb257df12, 0x4494f7b3, 0x5fda3447,
4499 0x0f73d8f7, 0xd4800cc7, 0x8b127184, 0xc55c79eb, 0xa024ee43, 0xb5fb62f7,
4500 0x14bbc604, 0xc7daabf0, 0x012f4e4b, 0x2a4a4dbb, 0x673eab19, 0x1a6fc651,
4501 0x157e2060, 0x17b1effd, 0x27fd840d, 0x6183ca31, 0x7da7d71c, 0xaff58469,
4502 0xf7fcc7dd, 0x0cb1c2e4, 0x746edef8, 0x70a78aee, 0x6e0b27db, 0xe6f6bd70,
4503 0xe43f067b, 0xdf68f04f, 0x7a588485, 0xdb8f5f98, 0xdda0f680, 0x2ad27410,
4504 0x4f696ec4, 0x8bac0dc2, 0x18898cb8, 0xe8718f02, 0xa6a2f88f, 0x073abdc1,
4505 0xd429e6a1, 0xef351b73, 0x1ae4c424, 0x9026ef75, 0xbd741903, 0x557e71b1,
4506 0xf67672fc, 0x03b70a6f, 0xcd8863df, 0xbec0f524, 0xb45eec2b, 0xefe49e1b,
4507 0x48dfd058, 0x23886788, 0x3bf56ed1, 0xcd5fb42e, 0x5fb410fb, 0xa3d63e4d,
4508 0x1917c7cd, 0x5f5a478f, 0xa638f9e2, 0x43c43688, 0xd941a16c, 0x4f0f15af,
4509 0x363b8f0c, 0x5083b881, 0xe30d9d7e, 0xc978a9c0, 0x6cd879ea, 0xf1d371da,
4510 0x4c44f469, 0x606c8766, 0x777cd4e3, 0xf3809712, 0xd3bf68f7, 0xdbf26af1,
4511 0xaa3c79a3, 0xdf411891, 0x09daa2d9, 0x068f7fc7, 0x7b8c4bdf, 0x7d022487,
4512 0xcb57df08, 0xc411ee04, 0xfed079f0, 0xe09df535, 0x6bfd601d, 0x4ec190e1,
4513 0x2bbf7df5, 0xccb7faf8, 0xe81ef25a, 0x75619c9b, 0x313bc818, 0xbde26489,
4514 0xa801d6d5, 0xe616d29f, 0x2f346393, 0xcabe3234, 0x6e504158, 0x9c59ba32,
4515 0x8d12590a, 0x8a39a8f6, 0xb86c96c8, 0x296444c7, 0xf3f17a1b, 0x22d725f3,
4516 0x5c650503, 0xb68d794e, 0x37ceed6b, 0x0844a5cc, 0xbf851140, 0x31f3da37,
4517 0xa370dff4, 0x1a30c937, 0x74b7de3e, 0xda9460e7, 0x6823c14b, 0xb5ddee10,
4518 0xe90b0867, 0x089af781, 0xf01777b9, 0x4f286378, 0xbacf7082, 0xf7943a31,
4519 0xdf7d5144, 0x67f2c698, 0xba5defa3, 0x3fbbc29c, 0x346ce4a6, 0x79ca278c,
4520 0x05779e19, 0x17fe70e3, 0x71945f5b, 0x98ea6c8e, 0xf9963d12, 0xcf1de14d,
4521 0x3dd0f6e1, 0xd7875c6a, 0x107c94da, 0xcd2511f7, 0x55af51fb, 0xb963f607,
4522 0x1d34f201, 0x2531df16, 0xeb109625, 0x930b4ba3, 0xfd78852e, 0x9d0324d2,
4523 0x974780e7, 0x60fb82ee, 0xa23c3c61, 0xb0d183c1, 0x499ed77c, 0xdf2c3c6a,
4524 0x7f487605, 0xbac030f1, 0x89f2e97c, 0xe5379ffd, 0xc42b788b, 0xf019e43b,
4525 0x87f1a5dd, 0xa15fe86d, 0x47ae0b3f, 0x3eeace1c, 0xfb2abfee, 0xc5270a11,
4526 0x5fcc2e3a, 0xaf853b4a, 0x749be2fa, 0xbd8cbce2, 0x9fe5a7af, 0x0327ab62,
4527 0x7ab70de0, 0xe1c6d9f6, 0xf63ef1fc, 0x3dd7af54, 0xaf984c79, 0x063bcd89,
4528 0xb32ef7ee, 0xaaca35de, 0xcd4ecbf2, 0xd1a6205b, 0x2c8166f1, 0x93e78424,
4529 0x8cb650b0, 0xf04cf3a0, 0x7ace3018, 0x063bd599, 0xef4c71fa, 0x8495d20e,
4530 0x31de009a, 0x0b961882, 0x6d86bfa5, 0x50debf6c, 0x622ff06a, 0xc002bde7,
4531 0x8747f30b, 0x19ba3f8e, 0x411cb47f, 0x3d69a8fe, 0xa5a3f8c2, 0x0bf81f3e,
4532 0x9f60cdce, 0x47ba48df, 0x79afdd03, 0x48d0a9b4, 0xb5987ff9, 0xf28521bb,
4533 0x14d64485, 0x788a5f16, 0xaf8c31fd, 0xf8f87d17, 0x45f57994, 0x693dc6df,
4534 0x7ec2668f, 0xcf01af72, 0x85bc14bb, 0x8b2b07ec, 0xf7641c23, 0x6a7e834e,
4535 0xc3763b73, 0xf9ed37f4, 0x70db8c0f, 0x0769bdec, 0xa34c77b4, 0xfb857214,
4536 0x08bbdc6d, 0xa46dcbdf, 0x319000f3, 0x75865ba4, 0x307c6fbd, 0x03e109f9,
4537 0xc04c9eec, 0x979411c7, 0x109efcf5, 0xffbc3b95, 0xdecacc3a, 0x65679865,
4538 0xac07e7fb, 0x1d994f22, 0xc7b7b096, 0xdaadfb04, 0x9fac0625, 0x7aa66900,
4539 0xdeb04bfe, 0x26a35603, 0xa7a14e5e, 0x93544fc2, 0x877de15a, 0x3def588c,
4540 0xb389fe5a, 0x29e0a9a6, 0x11f31eed, 0x4a0c9cf7, 0xdd779d87, 0xe52aeb0d,
4541 0xed351b9f, 0xc0164946, 0xf81f529b, 0x687d1233, 0xae8c45bb, 0x17b05671,
4542 0x205cee36, 0x7f42f9c2, 0xef039ae9, 0x39fad1c7, 0x89b75256, 0xa189cfb6,
4543 0x79e3e429, 0xa7cf207e, 0x43fd34b0, 0xdfa041b7, 0xebbf7357, 0x171e56b3,
4544 0x065e7460, 0xcb3c53ef, 0x29313af1, 0x4505d71a, 0x8066c16e, 0x3f236b73,
4545 0x4eeb4ebf, 0x14dd0033, 0x1b763639, 0x68ba7682, 0x065d19a5, 0xc7786388,
4546 0xec6de747, 0x7b5cef5b, 0xa7bfbb29, 0xa732feff, 0xafb6f7f3, 0xaf75eabf,
4547 0x4ba065f7, 0x63c75475, 0xcd7cd137, 0xf9e19fa5, 0xcd6b22e0, 0x3b73ea55,
4548 0xff1faa7d, 0x3a4e173b, 0xfcec3ec0, 0xc9145cca, 0x32b0eece, 0x6f8f77fb,
4549 0xec53b63a, 0xe815242e, 0x413df564, 0x5768a633, 0x1e5508fd, 0xc63651d0,
4550 0x656afac1, 0x75aba4fe, 0x147f03f7, 0x42bd7e64, 0xf41238d2, 0x5fd58e64,
4551 0xe5c38b8c, 0x481718e9, 0x51f662be, 0xce0ffd14, 0x79f90a97, 0x73b0e798,
4552 0x397f2c27, 0xe3938d31, 0x2a4c7ea0, 0xda23cfc2, 0xe272b9f7, 0x5de82365,
4553 0xf08a9e92, 0xe574a20a, 0xd1da0903, 0x30cb92e4, 0xa890ab9e, 0xbe3a31ec,
4554 0x6fc6749c, 0xba964753, 0x9feff327, 0x6cfaf301, 0xd61319c4, 0x66b8d7f3,
4555 0xec6b27b8, 0xe8374694, 0x5dffdfed, 0x3c5233bc, 0xe31b78c5, 0x12be3dc7,
4556 0xeb339c37, 0x12ef9af1, 0xbd5dd896, 0x9fc7abf1, 0x3e0adf1e, 0xfbcb78f5,
4557 0xce393dd0, 0x7a3f1bd5, 0x5074287c, 0xc7c7acf0, 0x8a6ff03b, 0xcd3277af,
4558 0x3bdacef8, 0x77df8646, 0xdec8b9a8, 0xfda0f46d, 0x43c7c85a, 0x4fb457ed,
4559 0x6eec120b, 0xe29e1ec6, 0x78f0c4c2, 0xe3d578f5, 0xe3bf8731, 0x7c446242,
4560 0xe0377447, 0x0161f28b, 0x7ed04c1c, 0x7099b60b, 0x578248ff, 0x06fc7513,
4561 0x47be061d, 0x17973577, 0xd6392f05, 0x00b19dba, 0xe78a9ccf, 0xa57f57d7,
4562 0x5b0b67b5, 0x7f069ca7, 0x778c4e40, 0x8941f809, 0x5f384a98, 0x15f2d51d,
4563 0xd535971f, 0xa8eaf9cf, 0x9198af8e, 0x0bcacf13, 0x74f2ba9d, 0x85507e82,
4564 0x56f3f4ef, 0xf815ebf8, 0x9e37a130, 0xb2cafe14, 0x993bfb71, 0x387b060c,
4565 0x31b1b5eb, 0x6b499fa0, 0xc3bf445c, 0x2125c3f8, 0x914f9c38, 0x0de2050f,
4566 0xffa6777d, 0x9daa7a03, 0x3f2a82ae, 0x5bd10cc0, 0xa7a08b60, 0xc4993e14,
4567 0xc88935e9, 0x347fc03b, 0x12ff1889, 0x5553f7b2, 0x99e657f3, 0x9e605242,
4568 0x4c5d58af, 0x8679f3bf, 0x47cd4de6, 0xde44fba0, 0x1b28c4ff, 0xdd20b7de,
4569 0xfc21b3c6, 0x32bbe1a7, 0x3c2e29b2, 0x27d7890e, 0xb308eb43, 0x7be266d7,
4570 0xe42f14b6, 0x1c786b1b, 0xc4609b5e, 0x38f85677, 0x928badce, 0x79ed4e21,
4571 0xec073bd1, 0xdec2b3b8, 0x319f9c2c, 0x37d60238, 0x2d67f97d, 0x9ca06b3b,
4572 0x7ac32bd6, 0x2295fc7c, 0x6f742ff3, 0xa4d7fb33, 0x52876df6, 0x4075c671,
4573 0x70899f91, 0x900af15f, 0x8c0a60b7, 0xca586afb, 0x7cfdba68, 0xf2fbee39,
4574 0xd08db25a, 0x299eaecf, 0x4f9f9718, 0x5fb0463c, 0xe7af7cf5, 0xeb3f3d6f,
4575 0x8fec37f9, 0xfb0a1ee8, 0x2fcaef90, 0xe2169d8a, 0x6f94c39b, 0xc29beb54,
4576 0x1e7f942f, 0x8d75bc05, 0x3019e4fd, 0xfd8df7ab, 0x37d6112c, 0xdb0f0ec5,
4577 0xa0c79e1b, 0xb8f65f5e, 0xbbff8762, 0xf034fbcd, 0xcf7491a3, 0x2369f682,
4578 0xefb8065d, 0xf3cdb6fe, 0xec577c0c, 0x2bed8b93, 0xe1ba4ec8, 0x8b337ca5,
4579 0x206021d3, 0xbcabdef8, 0x753d4040, 0xa096e907, 0x24ea3bbf, 0x9675fecd,
4580 0x07e3fba5, 0xfeb03ce0, 0xf2078c12, 0x889a9442, 0x715c59ed, 0x31efbf03,
4581 0xe0047bb2, 0xda85cef5, 0x64d8f8f6, 0xcd5df84e, 0xafb6058f, 0x48e9659f,
4582 0xa5b47b80, 0xbebeb6b2, 0x7a1e657f, 0xb576fab8, 0x78219dfc, 0xb2add8b7,
4583 0x31b55e0b, 0xde34263b, 0x03bbf877, 0xf006df14, 0xea5eb4d7, 0xff02247f,
4584 0x2a37a92a, 0xaf18d32e, 0x99b62fb2, 0xff7a47a7, 0xc147e943, 0xaed24cf7,
4585 0x916ff3e0, 0xe89a2fde, 0xc37dfb65, 0x79cd4153, 0x746692bb, 0x2ebb464f,
4586 0x1da02023, 0x33c8155d, 0xf3d8d6cc, 0xcbdbbf6c, 0x2977879e, 0x0ef37ea0,
4587 0xea07cf66, 0xd5505f71, 0xab37f6cc, 0x99398ce1, 0xed13240f, 0x15bed0fc,
4588 0xe1aaa0e2, 0x1e563f9d, 0xe9e6ab84, 0xd7feac8d, 0x87a685b6, 0xe9df6033,
4589 0x34dc924d, 0x86a1e2bf, 0x6a3fba28, 0x42162548, 0x5d7f47f7, 0x1594d0f1,
4590 0xe2ca54b9, 0xc589023c, 0x426d837c, 0x5fc9f7ff, 0x01b078af, 0x7f74c9f6,
4591 0xed5363d5, 0x8f92fb5b, 0xe21736e3, 0xeafdafb1, 0x5f2531fd, 0x077e54db,
4592 0xa27bfd3d, 0x7fc0315c, 0xf47df30f, 0xc2ef0bb5, 0x92e581fd, 0xde21430b,
4593 0xbba7226b, 0xa9fdced9, 0x3acf7656, 0xed9af45f, 0x5d6fdf20, 0xe27e0118,
4594 0xc31e4677, 0x7f2b597d, 0xafaf716f, 0x8523ed1c, 0x6676718e, 0x697b5fd7,
4595 0x15f6039b, 0x03fb8dd7, 0x673f0fde, 0x9d99ef64, 0xec6935cd, 0x856c87d8,
4596 0x495f0071, 0xd044da29, 0xeec713cb, 0x7ceb0c3c, 0x5843eb5f, 0xd0047bff,
4597 0xfec2e4ff, 0x69df3c44, 0xbf00e5de, 0xdf7e59cd, 0x5b735cfc, 0xad345de2,
4598 0x0707f8de, 0xf9d2a7ec, 0xdb19cefc, 0xaa9b7df1, 0xcbbe222d, 0xbc4dfb40,
4599 0xcdc7fc1d, 0x611e73b3, 0xd7a944dd, 0xd5dfc23f, 0x49bfec50, 0xaf9fb251,
4600 0x12df8a87, 0xbab8e1df, 0x1c58f459, 0x73c0edbd, 0x2c9ed27b, 0xc9107a06,
4601 0x1a3e1c3d, 0x0bb44ec9, 0xfd0df9f9, 0x7ef784ed, 0x9bccf3b7, 0x7cdd9fcd,
4602 0x73913215, 0xd802e5c9, 0xcc01de47, 0xb0f4c739, 0xfd5dbf62, 0xa93fd695,
4603 0x5bf31fb7, 0x21492f47, 0xdef60f88, 0x1fc9b77b, 0xec2ecec9, 0x9ed1129e,
4604 0xc471e424, 0xf496f657, 0x4cfef0a9, 0x2706dbf6, 0xcec83bf4, 0xf9b6b1f8,
4605 0xa51f7c33, 0x856f0486, 0xd1669af2, 0xa6df2419, 0x1efc979f, 0x57545efe,
4606 0xbe02e4ab, 0x15dd6aed, 0x16f90595, 0xb55dfd11, 0x0e5e26fb, 0x2ad9d67c,
4607 0xb5213be1, 0x80713edb, 0xf7d6501e, 0x7ef656ce, 0x31eb5748, 0xedc0aefc,
4608 0x1cbf896c, 0x068d9dd6, 0xb9dcbfb6, 0xd0566ffb, 0xe85e6f0b, 0xad7dc789,
4609 0xb6f73eb2, 0x052f117f, 0xbfe43176, 0x44bfdb55, 0xe200789c, 0x24630a9f,
4610 0x3b610a22, 0xfcfad7b5, 0x27625921, 0x7ce9d7bd, 0x08c5f758, 0x37c735eb,
4611 0xfc08cfed, 0xefbf5fae, 0x6a7b73b5, 0xf786c908, 0xc42e5af5, 0xcdbde257,
4612 0x1173ab56, 0x5d985ffa, 0xccf3b5d2, 0xfbe15313, 0xdbdd915e, 0xdf2220bf,
4613 0x72bdb5bf, 0x8d4d8758, 0xd7a406f7, 0x77ce8317, 0x7feb41be, 0xf99a2bb1,
4614 0xcbee8da3, 0xc206f7d5, 0x5f1cfdf5, 0xae7664c1, 0xbbc32725, 0xeedbdf38,
4615 0x2ef5eeec, 0xb47613d5, 0x80a7bb3b, 0xeab11dfa, 0xc5f40988, 0x53c97b20,
4616 0xac040f4c, 0xe4991780, 0x6fda10a7, 0x07c93479, 0x27aeeafe, 0xdba3884e,
4617 0x0060c7b2, 0x9b5d8cba, 0xeb2ef18a, 0xfcdfb9f9, 0x5529a340, 0xf3e65fa5,
4618 0x9253a373, 0xf54e343c, 0xf4c1d93d, 0x155da9c0, 0xf93d42bf, 0x1e193347,
4619 0x1bfc5d61, 0x4d9b67d7, 0x500dd4f2, 0xf701a8ef, 0xbf773b1b, 0x69de1bbe,
4620 0x35d87f9b, 0x0399d61a, 0x5eb40f20, 0x0df5decb, 0xf2db2f10, 0x6aef4121,
4621 0x68a9534e, 0x41befda0, 0x760fcc5c, 0xe0fb80c0, 0x7890ff90, 0xfb9e61e2,
4622 0xf9bf6ced, 0xe6831ec6, 0xfe0de99c, 0x765be83e, 0x33b7c189, 0x3da6d43f,
4623 0xb7a0f1f9, 0x6fbdd907, 0x8f6b1e00, 0x5c383477, 0x6299bf61, 0xb0384d27,
4624 0xfa28ea69, 0x0d6709cf, 0xebb7204e, 0xe6111ac0, 0x48453aeb, 0xd97a40ac,
4625 0x2ede144d, 0xce37bc35, 0x1c747832, 0x2a9c816f, 0xef2ba7f8, 0xff3499a3,
4626 0x0e31bb46, 0xfc14a4e2, 0xfa50f32b, 0x67880577, 0xc9450db5, 0xfc5be9b3,
4627 0xe69c4ab7, 0xde512718, 0x9cbe4727, 0xcfbcf76a, 0x3b4641f8, 0x68aed4f6,
4628 0xf33647b4, 0x95248c75, 0x29fc030e, 0xa782fa74, 0xeafa78ca, 0x075f3cff,
4629 0xf2bbf494, 0x25c97af5, 0x77f0df23, 0x30725cfa, 0xb1e21d2a, 0xeff1d25a,
4630 0x55e2a8a1, 0xa93e03cf, 0x87f8d602, 0x060c3a5a, 0xb3554fb8, 0x67c5884d,
4631 0xd769fa42, 0x18ccf886, 0x396bfe40, 0x2b8e504c, 0xf994fdd6, 0xe1bea8ef,
4632 0x79e157ef, 0x3f0fc834, 0xd0241e97, 0xeaeb4274, 0xdf8829c5, 0x2ae403a0,
4633 0x372a278c, 0x9a35d690, 0xdfe75f80, 0xfc79d2c3, 0x4afe777c, 0xd967ca2f,
4634 0x67a7162a, 0x38e2a475, 0x257e71ce, 0x8864e886, 0x1bb068e3, 0x4fc9f134,
4635 0xdd3dbe70, 0xf41b64fc, 0xd62bf94b, 0x6cafcb41, 0x1819fc79, 0xa7afc2ae,
4636 0x5384249b, 0xff3dad1e, 0x7830744e, 0x7e300e5b, 0xe524d09f, 0x1349fbc3,
4637 0x7f04e264, 0x6b4d1bf0, 0x6fdfd045, 0x32a73f00, 0xfd758739, 0xac47aed4,
4638 0xeef5833f, 0xdf808188, 0x9489b379, 0xc5c9546f, 0x6aafd5ce, 0x5d62b7e4,
4639 0x6ff454fd, 0xa009c477, 0x55b915e7, 0xe4d9bef0, 0xffe506be, 0x4ffc9d7a,
4640 0x418bed66, 0x27bd6858, 0x593ffcb9, 0x7e9fe544, 0x158a6d8a, 0x5366ce00,
4641 0x26b4f7e4, 0xff1fbe39, 0xf1eaf485, 0x92757a5e, 0x1de7ed83, 0x9affb4e9,
4642 0x3f707aeb, 0xe71f1a1f, 0x2b27279b, 0x002a937c, 0x05291bfe, 0x145f0033,
4643 0x68cfc0af, 0xcdbe82b7, 0x8277c34b, 0x22e3f37a, 0x234ddce5, 0xa6bd61b7,
4644 0x06f7afc8, 0xe4ce4f18, 0x5f60c5ba, 0xc8cb17c7, 0xef05a7a7, 0xaeba38b0,
4645 0x8e79069d, 0x394617a0, 0x42f91e98, 0x11de6af2, 0x920e3def, 0x4e5d7c0c,
4646 0x2f306a77, 0x02704ab2, 0xd772947d, 0xe09fbe2a, 0x4aef94f0, 0xfde37bfe,
4647 0xbdfcbd2f, 0xb8718e55, 0x6420999e, 0xad9f8473, 0x47c84467, 0x6b8620b9,
4648 0xe6de4193, 0x27ec75d3, 0xb4ec75aa, 0xaafc88d4, 0xce3ee1e0, 0xb2c45fef,
4649 0xfce70f79, 0x3f6c0d31, 0x173f37c4, 0x81468c13, 0x3028b5c9, 0xfe011779,
4650 0x5e575de9, 0x5d7f7c83, 0xdcafbe64, 0x33f91ab0, 0xf789c8b6, 0xba349e41,
4651 0x9199b12d, 0xd31fb1f4, 0x817f6b9d, 0x63e02bfb, 0xe4befb90, 0x80e41ca0,
4652 0x3f7fe044, 0xfd157fe5, 0x7ca03e14, 0xa54384f1, 0xa17cf427, 0x7829df9c,
4653 0xff3bacd9, 0xf5c1c8fb, 0x7d5d4f3c, 0xf328a1c4, 0x3e74def9, 0xbfce8bdb,
4654 0xcb0e7461, 0xd15bd017, 0x9c818f13, 0xce5beb8d, 0xac4e316c, 0x6cd1f0d7,
4655 0xe468fb8c, 0xde0140e7, 0xe7dd685f, 0x39d7d9fc, 0xf7ab32ce, 0xe0fe3575,
4656 0x1995d1bc, 0x6e428fe6, 0x6b582ed7, 0x8df473c6, 0xbcb3c984, 0xbeafda33,
4657 0x5234e9a7, 0xfaa29403, 0x09e7d01d, 0x21070ab8, 0x22685aef, 0xf83f7419,
4658 0x4ee96a45, 0x71f9a788, 0x8a3c5cbb, 0x49a363ce, 0xee1d769e, 0x00d7dc0b,
4659 0x0d8a6bfc, 0x88af884e, 0xf00538f5, 0x004ba043, 0xeb2f70e4, 0xfbba4c67,
4660 0xbaafdc72, 0x1f4063dc, 0x52f4e01c, 0xa1e0abe8, 0x2faef5af, 0x9862daba,
4661 0x72f0245c, 0x99791ebd, 0x4f034dcb, 0x6447ae2f, 0x41c9e411, 0x18448bbc,
4662 0x07a644ff, 0x22647a43, 0xcfbe73c1, 0xf3e47a75, 0x7c8f5e1f, 0xb923d1ae,
4663 0x08f5111d, 0xff9445fd, 0x68b9a684, 0x91c392cf, 0x862959ed, 0xb009c7ad,
4664 0x097ad28e, 0xa1fbfb32, 0x52df3807, 0xc438c48e, 0xc63326c6, 0xc87a2b5d,
4665 0xc3e48d31, 0xc0753bdf, 0xa6b50bba, 0x824f0f79, 0x9324d7f3, 0x4f83ce0b,
4666 0xf748dd4b, 0xdcc374d3, 0x2251fc88, 0xe823bd00, 0x0b7e0223, 0x99834ff9,
4667 0x456c5ddf, 0x48505939, 0xb9dd1d70, 0x55f23c76, 0x009a7179, 0x2eb15b7c,
4668 0xb8f28056, 0xe8034ec9, 0xe31e652b, 0xc6481a17, 0x94839418, 0x8c1c9518,
4669 0xc044eb97, 0x6f78b0d7, 0xc84b1492, 0xff4f3165, 0xb9b7ed58, 0x7ed5e684,
4670 0xf65f9a1b, 0x9736fc5d, 0x65c9fcfd, 0x73c9b7e0, 0x8cc64678, 0x65cdff43,
4671 0xac0ce690, 0x6f4a8913, 0xfb8ecc5d, 0xcb52fcbe, 0x40e443fd, 0xacec7f2f,
4672 0xc7f42e75, 0xd47c024e, 0x06789f24, 0x153be1c0, 0x366eed11, 0x2f5c018e,
4673 0xd2090f90, 0x9d494063, 0x4512fe08, 0x87035cef, 0x1ed428ae, 0x1433ce01,
4674 0x85bd0379, 0xce3c6ee7, 0x7655fc01, 0x91fbd7f4, 0x931f208f, 0x2b47d61d,
4675 0xdf110d8a, 0xc633be11, 0x67ea83f6, 0xd6f5fad2, 0xf8f0e59f, 0xe9e5115f,
4676 0x3d9518ce, 0xd1f164f4, 0xc10e7644, 0x9bbbe5de, 0x45abf1f7, 0x192ef7ee,
4677 0x615f7e10, 0x4324d9b4, 0x10f1293c, 0x4f155397, 0x410ab42c, 0xfea7c43b,
4678 0x746e760d, 0x0337fdbf, 0xb7fabfa6, 0xb054a292, 0x6e0c5be7, 0x7c41196a,
4679 0x7b83ca05, 0x267bc118, 0x616efe01, 0x23cd9b5e, 0x8843bf81, 0x3da0f7e2,
4680 0xdc8df3da, 0x681ba1ee, 0x3356e2f9, 0xaebdcdfe, 0x1eefe53c, 0xb21ef1b8,
4681 0x7dacdf82, 0xb8c48e4f, 0x1ba3634d, 0x858d6ce4, 0x51635fc1, 0x6062bbea,
4682 0x1cebeebd, 0x64c2e27d, 0xfe29f7f4, 0x41dd89c5, 0xd692f011, 0xe0b032ed,
4683 0xb18fd635, 0x957ce09b, 0xc700f5f3, 0x9b3de6fb, 0x73c75844, 0x862e3726,
4684 0x764bcefd, 0xf3c00aef, 0x76b51395, 0x0ea158de, 0xb9246eff, 0x493ee086,
4685 0x0ef88f91, 0x9a4c03b2, 0x1e1dc3d8, 0x9e573d50, 0xfd80ecf2, 0x11094c64,
4686 0xae2a9e00, 0x5f2017e7, 0xb8478064, 0xbdfc006e, 0x08b7fe4e, 0x7bcd9c39,
4687 0xf79005f2, 0x0593ed01, 0xfe6f6657, 0xeefb095e, 0x04fe2cb1, 0x07ecaae8,
4688 0xb2f6fd87, 0x534fe0c9, 0x618d6fea, 0xaf2afc7a, 0xc45c00b7, 0x422f3e74,
4689 0xfba613bf, 0xa929e0db, 0x9b72e5f1, 0xcf9aa5c9, 0x52f0827c, 0xc79c643a,
4690 0x3cdec3a0, 0x62d9f748, 0x4f2bdfb1, 0x656e3105, 0x70c11d60, 0x07ed219e,
4691 0x521a7ed0, 0x1d002ed7, 0x0b79ef37, 0x7db83bc7, 0x5cb94b27, 0x80f6e26d,
4692 0x367dae32, 0xe3ee5eb6, 0xe70dd1e7, 0x7af97ad8, 0x92e3178c, 0xe4347994,
4693 0x28ea9379, 0x6f1095fc, 0x78efb633, 0x4263b79b, 0x016f36f1, 0x77a76abd,
4694 0xd3de06ec, 0xf7120dfb, 0x247a451e, 0xf1db642e, 0x08177b95, 0xce5627a0,
4695 0x5037ec8c, 0xee4ac5f4, 0xb5c55577, 0x5aa317bc, 0xc696a72f, 0xfa54d359,
4696 0x4cf76948, 0x3365ae38, 0x53796b8f, 0x52d46ed3, 0x0cd3f00b, 0x8c10e79b,
4697 0x3f7bf95b, 0xd1dff9eb, 0x0ab1f651, 0x0c9d52be, 0xdcc7af5f, 0x8dce0fb8,
4698 0xca4e4f00, 0x912debc7, 0x9c13c3e3, 0x306f6e06, 0x8ced217e, 0x6a1e605f,
4699 0xb702ebbb, 0x78f2ae3b, 0x4f8c8c0b, 0xc93e453e, 0xdf01b7f5, 0xdb922f8e,
4700 0x1087ff80, 0x8c4527ce, 0x1efcf44f, 0x7ce38ced, 0xef004dd2, 0xb1bde163,
4701 0x3ff1fa08, 0x067cd863, 0xff23e7b4, 0x0af87950, 0x3a949bd7, 0x4923c251,
4702 0xc38c54e7, 0x7e995584, 0x69eb931f, 0x7a737e03, 0xd39e504a, 0x07664ead,
4703 0xa0fe32a5, 0x426705ed, 0x2ffe9e58, 0x4f842ce7, 0x00008000, 0x00088b1f,
4704 0x00000000, 0x7dedff00, 0xd554780b, 0xb3dae8b9, 0x64932667, 0x6f264c92,
4705 0x80849af2, 0x3c870108, 0x4e3d2878, 0x0f78601e, 0x02483508, 0x48042bc3,
4706 0xd2d04132, 0x20196f1e, 0x83548086, 0xa96a1ea5, 0x5af11e0e, 0xd528368a,
4707 0xf09d8360, 0x41d0582a, 0x396b42d1, 0x0a8a2341, 0xf41ea009, 0xfffde3d0,
4708 0xcccdad7f, 0x228899de, 0xb9eefbf6, 0x62ecfd37, 0xdaf6bded, 0x8fdffaff,
4709 0xfb0cd7b5, 0x33d6c60f, 0x2a1d76c6, 0x8cb96c96, 0x794bfbc5, 0xc5a398cb,
4710 0x8cf3d8cc, 0xff40b595, 0x9dbbfc2b, 0x7463cfb1, 0x1630258c, 0x2b18916b,
4711 0xa46fac64, 0x598dfa85, 0x187ae4ae, 0x15d236bf, 0x79c0496d, 0x26090e74,
4712 0xecc27e19, 0xf8743065, 0x99997af2, 0xc4bf5e71, 0xd5acc664, 0xbc232296,
4713 0x2ec6b537, 0x7efe60b9, 0x0b78ce91, 0x0b1703cd, 0x79d22da0, 0x2d73c0d7,
4714 0x66a38ed1, 0x6792cf78, 0x269d2dc2, 0xc15f7f46, 0xb12db57f, 0x35bbbeaa,
4715 0x2039d2c5, 0xff825fd0, 0x0eff8148, 0xc61b1331, 0xc5bf0d58, 0x2caec896,
4716 0x6b57cc0b, 0x0e6878ea, 0xf37eebf4, 0x92c191b9, 0x805eb86c, 0x7943f9e3,
4717 0x81cd7391, 0xd62adef5, 0x55c39b79, 0xcff187a2, 0xc66eb946, 0xf08e47e7,
4718 0xa1e193ee, 0x7d9e65e1, 0xa40b687a, 0xb0517dfa, 0xd996365e, 0xae3f41b7,
4719 0x4347b583, 0x8744f637, 0x47fa1a23, 0xa784b1cd, 0xb4743f5b, 0x62fac2e7,
4720 0xe7c24c9c, 0x38f95f01, 0xe5778b1f, 0xde23073b, 0xe00ccb96, 0x61e90178,
4721 0x8e3d36be, 0xdf04759a, 0x53873351, 0x4884c3a1, 0x5d0b28c7, 0x4f5ef467,
4722 0xd7801b31, 0x95d04c37, 0x579e8379, 0x4cc5a75a, 0xcf1baee3, 0x307d309f,
4723 0x7fdb599e, 0xe813f8bd, 0x32dff1bb, 0xf029dde1, 0xd617dd1e, 0xef09f3fd,
4724 0x95e0ba26, 0x61f7533a, 0xdb51f009, 0x5864db26, 0x9664a0c2, 0xd8c719db,
4725 0x0eadfb9a, 0x5a2783e4, 0x8c187b24, 0xb3660e67, 0x25643224, 0xdff9d622,
4726 0xb7610cc7, 0xac170b40, 0x6293ce30, 0xde436ef4, 0x43337fd9, 0x02b1dc38,
4727 0xc3e8068e, 0x05165d73, 0x0df50730, 0x459feaec, 0xf861f182, 0x6a4b982f,
4728 0x80976f69, 0x30466b70, 0xdee00197, 0x3f1326d7, 0xe118d13e, 0x7ff9830d,
4729 0xe1e2e3bb, 0xb9cfd099, 0x82cb875f, 0x339609bf, 0x43a8f891, 0x395a0afa,
4730 0x0f4034da, 0x8472edf7, 0x2df1865d, 0x5843d111, 0xfb45630c, 0x9ad9f988,
4731 0xbc0f307e, 0x047b4d67, 0x3f4d6fad, 0xe22c8f90, 0xff917b83, 0x591947f7,
4732 0x04bf5c0a, 0x86e38372, 0x46378eb3, 0x74e80565, 0x59d3f5a9, 0xeefd617b,
4733 0xd76f3e48, 0x91fd2bde, 0xe3fb957f, 0x97b5cc56, 0x2c5633e6, 0xf38a7ebb,
4734 0x1d5fd729, 0xe2345ef0, 0x8234b19b, 0x0727e897, 0x378abbe0, 0x1cafc70b,
4735 0x7475a7a5, 0xae3b08b1, 0x60e8c5bb, 0x29cf2748, 0x5e0adfce, 0x746f04eb,
4736 0x709e15b5, 0x389efac1, 0xe7c76691, 0x852f5abb, 0xb37de0eb, 0x230f5c63,
4737 0xeef4e5dd, 0xe22e6768, 0x1dcdd2f3, 0xe75eb8b9, 0xd2ef8446, 0xaeacf791,
4738 0xdf5aebdc, 0x7d64df63, 0x49b9bd6e, 0x3fc9e98a, 0xda903e5a, 0x8690bfda,
4739 0xd4309c90, 0xe60c9e5b, 0x6eeb035d, 0x49b43c1c, 0x634f4246, 0xc64f9436,
4740 0x06672c2a, 0x313de805, 0x12ddb9c6, 0x188e5f24, 0x2f5c0ee7, 0x8f3527be,
4741 0xde1cf9d6, 0x5e74721f, 0x5d7741be, 0xf4297ceb, 0xaf447d3a, 0x5a9eb15a,
4742 0x0327d993, 0xe1976cfc, 0x3e450e93, 0x0bc27bb3, 0xf08bd8f4, 0x27ed8a79,
4743 0xbfcf485c, 0x106bed9a, 0xc5bf7a1f, 0xeff04519, 0x11b1f7c7, 0xbd719273,
4744 0xff1d236b, 0xf6fe8665, 0x83f38c55, 0x127f6114, 0xbf73b716, 0xe4f50235,
4745 0x9fd718c4, 0xba81be71, 0xd09cb38b, 0x753bf02f, 0x781db973, 0x92fbac4d,
4746 0x97a8e09e, 0x58ebfe71, 0xaf425fff, 0xfe1d07bf, 0x05074c16, 0x7d04a33f,
4747 0x507e2147, 0x3feb7721, 0xf00530e9, 0x4f528123, 0x8f9cf6b5, 0x840c8eb1,
4748 0x07f77db7, 0xbe603bfd, 0x983e57ba, 0xf75bf285, 0xb7111872, 0x639be5f4,
4749 0x17cf8f90, 0x7316f2b1, 0xc9fa7d4f, 0x3ebb7aca, 0x4b4eb187, 0x1ad5e936,
4750 0xbeb237e6, 0xda974fa8, 0x14fa41f5, 0x47fba620, 0x3809fe0c, 0x994291ff,
4751 0xbbbe02ad, 0xc49e1f64, 0xa569e842, 0xb3256d7d, 0x7fd807cf, 0xf00e7a8e,
4752 0x4177643f, 0xcda5e10c, 0x3b58fa4a, 0x6acac8fe, 0xef4e697b, 0x1a191df3,
4753 0xbb45ee5e, 0xb0673121, 0xe588497d, 0xb4572576, 0x081d28a0, 0xa317b9e7,
4754 0x74b81ebc, 0x68adef2e, 0xb73a7806, 0x0f7ccdeb, 0xe639cbf0, 0x9407f65f,
4755 0x6ccd4f9f, 0xa1c76a1b, 0x8aafe56f, 0x0fdbc80a, 0xffb5f046, 0xd1a3a5e0,
4756 0x613f1836, 0x4f78bee7, 0xc07efe10, 0xe55e9ff4, 0x2f7c2cdf, 0x7d30fc23,
4757 0x07a47f47, 0x44d9c3fb, 0x7613b41b, 0x7ce7881f, 0x3a43a890, 0xeb7a172f,
4758 0x64697877, 0x2b09be60, 0x948f88ea, 0x1365ed7e, 0xf505c6f3, 0x9a237ef5,
4759 0x66cbdabe, 0x5f7185e6, 0x49e2a258, 0x7d61f47f, 0x537c7f50, 0x2baf69bc,
4760 0xf4323b78, 0xefda066c, 0xf9a1e1f3, 0x77188464, 0x09323ec9, 0x4609a3fd,
4761 0xc4258e5f, 0x34bcc638, 0x57aebb4e, 0xa5ecba57, 0x1be1defa, 0x96ae646f,
4762 0xf4347c10, 0x99c37bea, 0xd97ae407, 0xa1d90356, 0x32fe57a3, 0xf7e81f2d,
4763 0x658316c1, 0xfab3e035, 0x7ed2fbd7, 0x87abf70e, 0xe8245986, 0xe5f3607f,
4764 0xfc2f1f20, 0x75c4ecb5, 0x5965b07f, 0x3f683ce2, 0x01ac7e06, 0x356e1638,
4765 0xadeaf5d0, 0xb3f5d2f7, 0xfe174f82, 0xea10613a, 0xd7fba3f9, 0xab3ae227,
4766 0x87f6b1ff, 0x1a762fa8, 0x4286832d, 0xb243b35b, 0xc5c90697, 0x55c2a7e2,
4767 0x563a9dfd, 0xd650eb8d, 0xd5d724cd, 0xa78036fb, 0xddf7562a, 0x6afd97fc,
4768 0x95fc05ff, 0xf204d8aa, 0x09dd2657, 0xbc2baeeb, 0xbee27e44, 0xc7641183,
4769 0xc99668ff, 0xfd0df01f, 0x02df3fcf, 0xe87f92fd, 0x0843e4ed, 0xf42d1f3e,
4770 0xa4c96332, 0xbc4caa87, 0x4f5bb25f, 0x944944fe, 0xf186f84c, 0xff70d1e6,
4771 0x1f78c45f, 0x37e40de8, 0x34da8f26, 0x8e8dc612, 0x13f43031, 0x78b7c5ff,
4772 0x7efd0302, 0xbbfd65fb, 0x29eb411d, 0xd003cd66, 0x06622911, 0x1e8775cd,
4773 0xd49897af, 0x8ce747d7, 0x6e768b3b, 0x5d7d45b4, 0x58869b91, 0x0141ffe0,
4774 0xf077dffe, 0xc3c647a3, 0xc88eaafa, 0x86bb0fdc, 0xe10d797e, 0x5f9d23d7,
4775 0xcf01d8ad, 0x3958151d, 0x8683e57a, 0x11abe414, 0xfd0d5b12, 0x9584ae0f,
4776 0x0b879285, 0xbca36fe8, 0x80efa033, 0xda277d00, 0xa3ed5d17, 0xb11e4c38,
4777 0xe11f6af4, 0xee7ae6ff, 0x11d1e5eb, 0x6bf7a46b, 0x6e56a0f5, 0x383d2fbe,
4778 0x0c81e861, 0x4fb5144f, 0x4ec9fb63, 0x7ab45fae, 0x14f7ab51, 0xd6f0b4b8,
4779 0xf4a9d65e, 0x1b58d0dd, 0x3de80b8d, 0x1bbde923, 0x8d1d5f18, 0x815f110d,
4780 0x797c265d, 0xae29e986, 0x0de1bf03, 0xb66b971c, 0x480115c5, 0x48ec960d,
4781 0xcc33e7d4, 0xee50b7ae, 0xb03b7f32, 0x1ebd8194, 0x8759a3b4, 0xe24ba37a,
4782 0x106edaf4, 0x0373f62d, 0x623bcff1, 0xbcb1edfd, 0xc50ff10f, 0x8a2bd98d,
4783 0xfeb07bd9, 0x84f31330, 0xf7bd91e7, 0xf302f218, 0xa2e31cbf, 0x8c458d71,
4784 0xdcb19dc7, 0x601ecbef, 0x7e6059d3, 0x87592036, 0x70265af4, 0x25a576b1,
4785 0x7bf813b7, 0x6a64cadd, 0xe7c45fd1, 0x68237b3c, 0xce4bef5d, 0x6b772821,
4786 0x7a5a7c05, 0xfe155b64, 0xf60ff676, 0x87141687, 0x56d1d3d6, 0xe8a7ad3d,
4787 0xe81919d1, 0x7edfbc6f, 0xcfea0677, 0x3f5e01f7, 0x3dbd3fda, 0x84fcebe6,
4788 0x3e3c8587, 0x8c44ec28, 0x267f2388, 0xc7d804e4, 0xb5fd13b1, 0xbfba4e95,
4789 0xb539656e, 0xa0ae571b, 0x59b1ddfb, 0x91e8fef4, 0x81b3fbcf, 0x641b9d7e,
4790 0x8c0b03b2, 0xf0b1fece, 0x8e934ede, 0xeaf7d1e2, 0xccbb65cd, 0x5c519d78,
4791 0xf1d1e0b3, 0x142e50db, 0xf563ba38, 0xd6deeeb4, 0x3ebd6d99, 0x3acb5dfd,
4792 0x5d1ed1a2, 0x0077c7e5, 0x7e01893b, 0x32bb219c, 0xc71809ad, 0x38e22474,
4793 0xbfefe4b7, 0xee808283, 0x956ff40c, 0xeccafff7, 0x6216b6c8, 0xa106c39c,
4794 0x7044b45c, 0x7385a37b, 0xd9f395a0, 0xc13695da, 0xfda80307, 0xef61f858,
4795 0xa10a9da3, 0xcf116e57, 0x6e3b361d, 0x6630f7c1, 0xd6937f26, 0xda3bfa81,
4796 0x42708791, 0xf78050bc, 0xcbd52587, 0xdbf90906, 0xf80df5c2, 0x771fdca5,
4797 0x2c71c48e, 0x044d21de, 0xf9130c7a, 0x05f2de9b, 0xb4de385a, 0xe6d0f972,
4798 0xc9569411, 0xf95a9423, 0x6b16fe7a, 0x6c77e551, 0x2a11cc2d, 0xcad5b07f,
4799 0xc3b266f5, 0x7ada4721, 0xd702bb97, 0xf3191ebb, 0xdecce524, 0x51a49a0f,
4800 0x3f98ed2d, 0xaef52949, 0x634afcc2, 0x3d0e56ac, 0xc95798e1, 0x3d12e976,
4801 0xefd12e30, 0x1c02322a, 0xe912625b, 0x7eac497d, 0xc0abd215, 0x1745a3a5,
4802 0x4af08fec, 0x4307904a, 0x047e85f2, 0x79470d09, 0x9ae51f1b, 0x5f9df843,
4803 0xc368c6bf, 0x464793fc, 0x025672fd, 0x38fe013e, 0xa422207b, 0x228f773f,
4804 0x1f7152b7, 0x4f05e934, 0x050f0819, 0x1662fd4f, 0xd4f05bc2, 0x28297a1d,
4805 0x6ac87f4e, 0x3d9dfc20, 0xe29338b0, 0xac6193e6, 0x79cf565f, 0x545f051b,
4806 0x60bf7c09, 0xab77cd0c, 0x5baffbc5, 0x7f82774f, 0xd3d2a893, 0x8109adab,
4807 0xed5d4c7c, 0xb3d3d245, 0xfc3edcac, 0xb072df4a, 0x57f3e00f, 0xf11d99f3,
4808 0xad99f8be, 0xc17ba794, 0x077632d8, 0xc74ea7ae, 0xffb00f30, 0xfb07cbe0,
4809 0xdf387fa0, 0x83fd1436, 0xd91fcfab, 0x7fd788de, 0x2286cd55, 0x1bbc53fe,
4810 0x7c07cc25, 0xf84cde1e, 0x185b7cfa, 0x5a4b055b, 0xec65ac74, 0xb9bfa04f,
4811 0xaf50c746, 0x6f0dd768, 0xb192e832, 0x237419f5, 0xff51fd38, 0xc6077429,
4812 0x143d2232, 0x50fe21ba, 0xf6dfed9f, 0xc0afc112, 0x46c625b5, 0xccfc5bf8,
4813 0x27c8b1ce, 0x12ac6a7d, 0xb81467e6, 0xb89dabbe, 0xf7f3f681, 0x3f666fd6,
4814 0x69fa465f, 0x6ed6a7ed, 0xf63b30ce, 0x86bbfe90, 0xf8231cfd, 0x0f4237f0,
4815 0x41ed98db, 0x23b253cc, 0x68f7ca3a, 0xf82a52e9, 0x7a2f2831, 0x791d7ac4,
4816 0x2b5661d1, 0x179b57bd, 0x7ae46edd, 0x66cad9b4, 0x87e5094f, 0x9b757809,
4817 0x17688dba, 0x90a4dbe3, 0x99a8e97a, 0x9bd025eb, 0x9f7241ff, 0x86af5a1a,
4818 0xc419efc0, 0x7c3bcddb, 0x5e54717b, 0xba244e6c, 0x0fcf805d, 0x7814f854,
4819 0xe0aaf054, 0x88a631b3, 0xf0bb65f8, 0x70c4b733, 0x9970297c, 0x8e7194e3,
4820 0x7a5f380b, 0x0bfafa2f, 0xff806781, 0xbf1fc232, 0xeaf2a99c, 0xbe3d3e4a,
4821 0x0b1923de, 0xca302cd0, 0xb9c665bf, 0x5c601956, 0x7f6648f7, 0x1531fa12,
4822 0x77d42296, 0x3b7b6ad6, 0xcf1bdde6, 0xe366bcf1, 0x4d5de652, 0x7ffe30f3,
4823 0xa3ca6cae, 0xe69dde22, 0x5941769e, 0x532bd81f, 0x15c1215c, 0xf635f711,
4824 0x45ca06ea, 0x9337dc72, 0x10b8f48b, 0x731b7b74, 0xc7210980, 0x4379c5f7,
4825 0xaf0739d0, 0xb7ce8b5f, 0xe5e57889, 0xcd472998, 0x0cb56fc2, 0x4b5dd009,
4826 0xdf91becf, 0xc4f78f51, 0x09716dcb, 0x61b2f13d, 0x1e806e82, 0xec22c9d7,
4827 0xa4ceeca1, 0xdf3defb8, 0x442e293f, 0x54fe1fbe, 0xab13f4fe, 0x84dfafed,
4828 0x5326be70, 0x4fc4f49c, 0x27988c3b, 0x0ad2f256, 0x812feebc, 0x773f40a3,
4829 0x56a3a97d, 0x26d75eb9, 0x55dc63e5, 0xf90aefb4, 0x5fed5dc7, 0xa5dc7f92,
4830 0xf7958ff1, 0x89ec03de, 0x365a31f2, 0xdc5fff13, 0x9978e3c2, 0x146dfed9,
4831 0x643ee1c0, 0xf11b5e60, 0xb40ff92f, 0xc45fe85e, 0x633fc716, 0xe16f78a4,
4832 0xf98617e1, 0x08cc52e0, 0xe105b31d, 0xc111d62b, 0x8af8416c, 0xfaaab32b,
4833 0xaa3ece09, 0xd9e549f1, 0xae29fbaa, 0xa9fbaa81, 0x7eaa79d5, 0xaaadfd7a,
4834 0xb76099f1, 0x9e59fb82, 0x7df1aa71, 0xfaaaa69b, 0x56ef9afd, 0x871e678d,
4835 0x39d6073f, 0xa6f3ac5f, 0xe35573cd, 0x61f24f99, 0x2081647d, 0xc7dbc7f3,
4836 0xc8fac21c, 0xb88f917c, 0x3558bbd9, 0x756682df, 0x08f0815e, 0x956aab78,
4837 0xb78863d8, 0xd5fbeacd, 0x531b1b6d, 0x55e45da1, 0x758c5f5f, 0x53f9090f,
4838 0x3af7fd7d, 0xe3f432e7, 0xcea7197f, 0xbe935dd3, 0x45ae9b9e, 0xc70fbb5f,
4839 0x7f2288ef, 0x79e1e167, 0xc9614724, 0xdb86fa6a, 0x7f16be22, 0x9aac0391,
4840 0xafbff0fb, 0x5d945fc1, 0xfc5a0fcd, 0xc1f759e9, 0xceab8054, 0xac7dd92b,
4841 0xb516fe27, 0xb538256e, 0xede2d3f8, 0xbcea718f, 0xd748dace, 0x971bd45e,
4842 0x0ccb975a, 0xbc65f3f3, 0xf5a978fe, 0x6c4721d3, 0x7ef97941, 0x5fe5e6bd,
4843 0x97910b8d, 0xcb7ac2ef, 0xd41bec2d, 0x817df65b, 0x8b030878, 0xb27a0063,
4844 0xd5d37611, 0x20784afa, 0x5bd5af0f, 0xfb7a0b4a, 0xcfa4716f, 0x35a97503,
4845 0x98b0f4f0, 0xaf089db7, 0xef18b752, 0xb7bc1172, 0xe1232020, 0xa75f333f,
4846 0xe1e00f32, 0x7c679c3d, 0xe3123591, 0xeffb9da7, 0xb58078a1, 0x073d73c5,
4847 0x1f1e0f24, 0xfe9297e4, 0xa67fc16c, 0x48fc3d90, 0x704fc3d8, 0x321ec53e,
4848 0x57bf959f, 0xe6dec3d8, 0xbd16ea51, 0x995ed2b5, 0x58dd2fea, 0xcfa1097f,
4849 0xd1dff18d, 0x23d27cae, 0x0f8c69ff, 0xbdee0f8e, 0x3af51074, 0x1e3c3de0,
4850 0x051519d6, 0xd80a52f6, 0x8c8b7fcb, 0x3eeb7926, 0x826f7b2c, 0xb64d170b,
4851 0xa06e6b18, 0x7785a2be, 0xab9ac994, 0x6de3d20f, 0x365eda92, 0x23ff71e6,
4852 0x1dfb9e31, 0x2fdccc93, 0xe9d62c1d, 0xeeebf8d6, 0x82971e26, 0x05b75434,
4853 0xe38381f9, 0x3bfc68a3, 0x71834511, 0x5c455b3d, 0xd12598df, 0x89251afb,
4854 0x312dfaec, 0x9dff74c5, 0x6c5ca2b8, 0x0ef789fb, 0xda089f46, 0x8f0e6ce6,
4855 0x5013ec4d, 0xc710ffe6, 0x4c5b6217, 0x8b78e0ed, 0x0658efc8, 0x448fbd22,
4856 0xa35e6838, 0x29fcab2c, 0xe78bcda5, 0x99a7447e, 0x2a937e29, 0xe8463c7f,
4857 0x8717cc31, 0x26393091, 0xe40c4e8c, 0xea3c998b, 0xe45e31b8, 0xdc7a2589,
4858 0x5dbc7481, 0xbcb7b1d0, 0x658063b1, 0x4439bc3f, 0x1c97d8de, 0x1f6c6f32,
4859 0x78637943, 0xd2eb8f52, 0x0e918fe6, 0x3c80d691, 0xaabf8c4c, 0xdf50d26f,
4860 0x3c756634, 0xe3f91e32, 0x127f6ca8, 0x13c77f41, 0xb6e00439, 0x7c7675d9,
4861 0xb616e464, 0x0bfa1c3a, 0x2fca363d, 0x8afe2019, 0xefc80bca, 0x4e2cf892,
4862 0xd33e13ff, 0xfc3fb810, 0xe63b671d, 0x634ffb93, 0xcdff5456, 0x1a24b9ac,
4863 0x2c2d88fd, 0x2552bc64, 0xd17c66f8, 0x3ce5195e, 0x25f81ba1, 0xe2aa3d04,
4864 0xbdbf8a75, 0xbc36e900, 0xf50975db, 0x4807a289, 0xb45c6195, 0xb27e475f,
4865 0xe896f9f6, 0x07c42592, 0x9279d0de, 0xe387334e, 0x29738442, 0x57783fce,
4866 0xcdf51187, 0xce6f4542, 0xd03d31d7, 0xbf414ef7, 0xbaf0b73b, 0xd5f2bb34,
4867 0x5fe2b257, 0xa19f9a31, 0x2d38583e, 0x87798bca, 0x1e596d85, 0x5129cb82,
4868 0x76ddc55e, 0x85fd89cc, 0x8c160505, 0x657f1d73, 0xe40199d2, 0x77ae319a,
4869 0xa28cecf4, 0xc67ec807, 0xaa629d53, 0xb34eabe0, 0xfd04e08d, 0xe81221bc,
4870 0xaacb70b0, 0xe12fb8bd, 0x54677fad, 0x7721388f, 0xa6c9c30f, 0xe4567203,
4871 0x1567ab61, 0xaf30f879, 0xf3134c77, 0xf784be78, 0x9def029a, 0xd69876de,
4872 0x3cc0c273, 0xae97e026, 0xd0d9773d, 0x304c6d4f, 0x457f89d9, 0xec94eb9d,
4873 0x878c807a, 0x410ebbbe, 0x6916d19b, 0x58eb0f59, 0xafdc6463, 0x11d845d5,
4874 0x1dcd13ff, 0xf897e27a, 0xf1e23d6e, 0xf467410d, 0x4fcfc9ed, 0x39274460,
4875 0x96e9c755, 0x44fbe369, 0xbff9d472, 0xc1dd0497, 0xebc34c6b, 0x58df2313,
4876 0x7cce036e, 0xc70fd376, 0xdea247e9, 0x1679637b, 0xdd365bf4, 0xfc8f4e35,
4877 0xa7c6fa9d, 0xcfea2059, 0xf7e72a6f, 0x69f1bd07, 0x6d77f436, 0xdfefc19a,
4878 0x5ecfbc46, 0x38f774dc, 0x74bfebcc, 0xf9f02f55, 0x12422097, 0xc395bfae,
4879 0xe2a1f574, 0x92bc5f0b, 0x7c06665f, 0x4fedb38f, 0x3aced027, 0xc3b7fa95,
4880 0x237faaa0, 0xdf8098c7, 0x62be0bc6, 0x0764d1f1, 0x8dfa09c6, 0x3f68fbd7,
4881 0x23e4ce8c, 0x1ac4defc, 0x8037c82c, 0xe55f4dad, 0xc07f7cf7, 0x4bf9a9ae,
4882 0x02b63072, 0x2cd92de8, 0x566b27c4, 0xda385730, 0x5ddd40fd, 0xcceeebc7,
4883 0xe057ef89, 0x03dfde51, 0xdead202e, 0x16d70c1a, 0xab81479a, 0x0798686b,
4884 0x9fb149e5, 0x525d5c0a, 0xf498e3f7, 0x0f2fd9fe, 0x75ba404e, 0x48677545,
4885 0x7090dfd0, 0x95d8e890, 0x64b8fdd0, 0x381bea0f, 0x5a6ccf1d, 0xef03ce36,
4886 0xce3b28d9, 0x1986dca0, 0x2692bef9, 0x3de0538c, 0x3cb8260f, 0xbe03cf58,
4887 0xef90fbb3, 0x87a48dd2, 0x79d40b4a, 0x67c16e89, 0xdeb813cb, 0x5cd61d1f,
4888 0xd2f80c7f, 0xab624bbd, 0xcafbbc60, 0x89da2325, 0x8da76d89, 0x76eb680e,
4889 0xbea2369d, 0xcc3ec3aa, 0x18c5b753, 0x12796f52, 0xd43f6164, 0xf481f07e,
4890 0xe3c40ffe, 0x12f985be, 0xd9eee255, 0xfb1a3b1d, 0x55c1ccf7, 0xa8f77632,
4891 0x5d91a39d, 0x0fed9d2a, 0x759b3b60, 0x9a16401c, 0x7e5592e1, 0x48eacce9,
4892 0x595b5f95, 0xcfeaa71f, 0x80ea066e, 0x915ecf5c, 0x181f8eaa, 0xcf00abc4,
4893 0x43f8160c, 0xe82e56fd, 0x83792338, 0xccadf71f, 0x1d3c1970, 0x6c4df341,
4894 0x22b7a55b, 0x9d92f5dc, 0xd987afd4, 0x7c99b9f0, 0x3dead085, 0xd1b0f5c1,
4895 0x51893cad, 0x7f226e57, 0x80fb02bf, 0xd91a8ad7, 0x0f10936b, 0x6eefba46,
4896 0x5bbee895, 0x4b5777dc, 0xec961d4a, 0xe3016cee, 0x46c73dcc, 0xe110b6d3,
4897 0xcef02bdf, 0x4b3b2f2e, 0x7afc28fc, 0x36e55d65, 0x7d70b3b0, 0x06dbfa6d,
4898 0x8ff6779c, 0x45971624, 0x50eceaeb, 0xafdd51e1, 0x19f757ac, 0x9e6030eb,
4899 0xf50af67a, 0xc209e1f5, 0x83620e9e, 0x25469e50, 0x2f927a48, 0xfd24ffd1,
4900 0x007cd7ed, 0xf3b2e3df, 0x83e004f6, 0xea8fa31a, 0x2ecb8f50, 0xe1f72bea,
4901 0xb9231d7a, 0xe4807f03, 0x5cf92258, 0x8a587063, 0x95ae8fd0, 0xb2676f88,
4902 0x2b217f20, 0x72fa9e30, 0x093dfecf, 0x135a5fdc, 0xf54e5cee, 0x65923db0,
4903 0xd52a5c1b, 0x07e8f43b, 0xe74291ae, 0x70259643, 0x418d7879, 0xf5700ef4,
4904 0xbb452647, 0xd78c677e, 0xffedef03, 0xf41e39c7, 0x03e7fbef, 0xee50d81f,
4905 0x2f19bdb9, 0xf024cdec, 0xebffd12f, 0x9394b72f, 0x68c5bf7e, 0xec2efd21,
4906 0x1c2fa290, 0xa1db51bf, 0x288769f1, 0x79b498fe, 0x8bd405c3, 0x791d7d39,
4907 0x07be011b, 0x1ffbf9c3, 0x71792ddc, 0xee5d4e1f, 0x499fd241, 0xdef81ec0,
4908 0x47a164ba, 0xacfbd55b, 0x21af5092, 0xa5c84cc3, 0x1498a6f7, 0x1e90776e,
4909 0xbac57c94, 0x497e80af, 0x69a9bde2, 0xe257c236, 0xd70916e2, 0xab3cce9d,
4910 0x45cf8ed0, 0xb40c2c21, 0x97cfedd7, 0xbe7f5a4a, 0xe4f9fc9b, 0x7bc5230e,
4911 0x9df8dbac, 0xe73d73f2, 0xfcd432ff, 0x53aa7cb0, 0x2bf2e207, 0xb9a798d1,
4912 0xafdf4f67, 0x9b24dfdd, 0xc1b771d4, 0xc7bb8ea2, 0x9feb500f, 0xdeb57689,
4913 0xafa23c99, 0xc714feea, 0x3bfdd520, 0xfd55f2cb, 0x54dbcee9, 0x2f2aefe3,
4914 0x92c3f551, 0x00f269c7, 0xe44abcea, 0x255e7500, 0xa3ceaeca, 0x7dfe1d84,
4915 0x317804b9, 0x2e1d3c9a, 0xc81343c0, 0xc06b08c6, 0x368a0c8e, 0x22367151,
4916 0x6d8cdc3f, 0x1f30d0d3, 0x1f5349f2, 0x1d87871e, 0x07d937be, 0x766298f3,
4917 0xf104b098, 0x1c5bc95b, 0x9a007307, 0xf03a9ea8, 0x39bfb57e, 0x17db8532,
4918 0xb825f5a5, 0x36844f5e, 0x2a5b19f7, 0x14fd67f7, 0x1822989f, 0x345e8bf7,
4919 0xc4a45f91, 0xe93ccac9, 0x50074569, 0xefdee47f, 0x6b09baa0, 0x27cc1665,
4920 0x7914693e, 0xbef917d4, 0x0ed6dcdb, 0xbe48239d, 0xfae44cef, 0xe2ce17e0,
4921 0x5d7f38b1, 0x9459581b, 0x1aefcda7, 0xd7593eb1, 0xf68d1ed6, 0x5df3886c,
4922 0x02ebe623, 0xd39d85d7, 0x5d604777, 0x722d77e5, 0x72cafdc8, 0x1febcf22,
4923 0xf2bd7a14, 0x547c40de, 0xafa02c34, 0xf5f2772b, 0x92374e55, 0x46c2c13e,
4924 0x7a0dbd28, 0x2ade67ba, 0xf28c1ed8, 0x03ba803e, 0xdc6ab7f4, 0x2e3c69ec,
4925 0x8dbd00aa, 0x5cfa0c72, 0x91ad3f7d, 0x73e80bf4, 0x010bf5d5, 0x15fb9e7d,
4926 0x19c2773c, 0xe8f65f7a, 0x3f375e14, 0xfc212ae1, 0x88f002ff, 0x7a2ff27e,
4927 0xf3e38de0, 0x167af85a, 0x37441f69, 0x2929b8ed, 0xb67c7fdc, 0x433d7d17,
4928 0xc949f5d0, 0xd4ca879f, 0xbe208ced, 0x8d72699d, 0x7a47ccef, 0xf588de7c,
4929 0x4bdfca89, 0xdfeced0c, 0x7ed30fda, 0x03cee33d, 0xd28fb889, 0x912072dd,
4930 0x18d5df01, 0x8fd0ab6c, 0xa3b0be07, 0xead753df, 0x5b6bf823, 0x7af1dbf2,
4931 0x4764ab6d, 0x75deec55, 0x93ad0c61, 0xbd623475, 0xe05ec9ef, 0x76e44cca,
4932 0x8da26064, 0x985c07e7, 0xc3e7c113, 0xf9095ebc, 0xc212f400, 0xcd625bb5,
4933 0x9d727fd0, 0xb79d6429, 0xff7be052, 0x57c5233a, 0xae3cf035, 0x41fa60e3,
4934 0x68f909a3, 0xc24bac27, 0x1e9b1c75, 0x372ff389, 0x142ff430, 0xfba5cef8,
4935 0x4ffae14f, 0x070087ce, 0x2f99afae, 0x2e4fbe13, 0x05c87917, 0x58cfea06,
4936 0xdd7e2464, 0x46bdff37, 0xac9defcc, 0x4bdcfbe1, 0xf9467c16, 0x248b19be,
4937 0x8a993f65, 0xd57e159f, 0x7f96a7f2, 0xf569f07b, 0x98e9f1f5, 0x3a7cabc4,
4938 0xd03ced04, 0xf212747d, 0xce218fcf, 0xb2b9f946, 0xf00490cf, 0xec5a3766,
4939 0xb06bafb8, 0x11207dec, 0x7e3ec4f5, 0x56cd687f, 0xdb1beb89, 0xa98728dd,
4940 0x1eb6464d, 0xae44cbfd, 0xbd206697, 0xdd69710a, 0x7bc52452, 0x4bd46cfe,
4941 0x0ef7ca59, 0x13be5606, 0xae7a71f3, 0x94bf066f, 0x107d75bc, 0x39129adf,
4942 0x707a2abf, 0x76b99190, 0xa5bfde52, 0xe79814cf, 0xdbaf0359, 0xfaf98864,
4943 0x331eedf5, 0x089fda05, 0xe027997e, 0x0af7fa50, 0xcd4f67fe, 0x344efc20,
4944 0x5b8fbc71, 0x75c0abe1, 0x8b5d1934, 0x84fee112, 0xd06bb78c, 0xbf6535ce,
4945 0x42f94b9a, 0xa73b2366, 0x46fbe7c4, 0x1965b07e, 0xe6fc37ac, 0xf863a208,
4946 0xe4168d9e, 0x057ef0e3, 0x7c10ae49, 0xcbeeb4a7, 0x3902e636, 0x4d9cbbaa,
4947 0xb29fd2ad, 0xf691acf7, 0x185db721, 0x39727243, 0xcf2bae99, 0xf9114a2d,
4948 0x53dfb12a, 0x9e825fc9, 0x0bc88fd6, 0xc0f0538c, 0x215e1770, 0xd114f3c2,
4949 0x3652d96b, 0x37d1a794, 0xd667fad2, 0xc0e6931c, 0x1c19773c, 0xd6167306,
4950 0x77c7cacf, 0x537ee0e6, 0x71fd5cc6, 0xb9899d9f, 0xcfdfb88c, 0xcaff7d42,
4951 0xb1bfea64, 0x63ed46d2, 0xd0cfe726, 0x5fdf4cde, 0x4df68fdf, 0x2cea3fa6,
4952 0x1d74f786, 0xb6be0831, 0x3a94be10, 0x9936a5d0, 0xa5fee099, 0x35d5125d,
4953 0x5d67f815, 0x715cc3ee, 0xdf15fd8c, 0x5da9ef07, 0x3be926f1, 0x3185f57b,
4954 0xad0d1718, 0x7d88dd39, 0xc6cf8af7, 0x0a713fa0, 0xf5f907ec, 0x4b27dfe0,
4955 0x198e47a8, 0xc55d7f71, 0xf3cd2b65, 0x0c7baeac, 0x15e797ca, 0xa74dea89,
4956 0x93182f5a, 0x08627db8, 0x9f5816ca, 0x1895d703, 0xb771f84b, 0xfa71d50d,
4957 0x4ab8f0e6, 0xc0fb43f0, 0x1e91a32f, 0xd7b615a6, 0x0fe7c36f, 0x77e50cc9,
4958 0xb477717d, 0x3dfe8425, 0xfeb2f301, 0x6ad81d7c, 0x3d1b97ef, 0x5cf0ecfd,
4959 0xfef42eb9, 0x9f0557a8, 0x3e29a602, 0x11293fc0, 0x55ff99e5, 0xac6292c2,
4960 0x22f8f714, 0xdb2b8e40, 0xb1eace4a, 0xbbd897ad, 0xbd8c78ea, 0xf7b7e41b,
4961 0xb4df87c6, 0xf4f9c3ad, 0xe201f641, 0x07e41646, 0x54c8dc61, 0xbcf0f7ef,
4962 0x924e7a52, 0xaf3ac42b, 0x1f4741ca, 0xd57a0366, 0xf3ba0135, 0x5207df91,
4963 0x5af77e7b, 0x298fca1b, 0xb451fba2, 0x8ebfac13, 0x8f5a8ce2, 0x93d9ffda,
4964 0x4f78e5cc, 0x77eb9732, 0x12f1d513, 0xa3ef45c4, 0x145c431c, 0xa0df858d,
4965 0x9d7b4978, 0xca1325e2, 0x1077bc15, 0x10f9e7d0, 0x2e4e1f70, 0x3df908fe,
4966 0x9f133583, 0xe473e033, 0x3f3aed2f, 0x9153f613, 0xd72819eb, 0x5cadbfc8,
4967 0x1ef3b5ae, 0x0cfa2e4f, 0xfb8759e1, 0x8de842b5, 0x6b3ac557, 0x97c23337,
4968 0xf095b37b, 0x766d8e74, 0x9e5f0316, 0xfeb03803, 0x4674e5df, 0xc67d62c6,
4969 0x9ab48ce5, 0x6ea07a03, 0xb73d0473, 0xdc6a672e, 0x2447e81c, 0xdf3fbe71,
4970 0x3c42625a, 0xe5ccdacf, 0x29df794f, 0x94388cdf, 0xb74342a7, 0xd3f70ed1,
4971 0xa3474eda, 0xfbb857df, 0xc39438ce, 0x47fce0de, 0xed775f12, 0xe3c67b8a,
4972 0x87f85df7, 0xfea54cf9, 0x33ed5ee6, 0x0578dd52, 0x7f6dfe23, 0x28756ff1,
4973 0x22dbe7c7, 0xcf37682d, 0xa0f489ed, 0x257aeffe, 0x2893abcc, 0x80c4f0ee,
4974 0xe8673b5e, 0xe5fe4498, 0xfe82d96e, 0x8f95fb9d, 0x7479451f, 0x9e8618bf,
4975 0xb6d25b1e, 0xbdda02f6, 0x67b1b69a, 0x9f6843f5, 0x1e553ff9, 0x47dc576a,
4976 0xffd2917e, 0x89c9a578, 0x9ebcf47a, 0xad2589eb, 0xbbbf902f, 0x21a5cae4,
4977 0xb73ef758, 0xa186bfe7, 0xf1ff735e, 0x67d430d2, 0x1a5c3fee, 0x2fddf786,
4978 0xf287d645, 0xc8a55657, 0x5ec57f44, 0xabd71d66, 0x0b1f43f2, 0x686ac8fe,
4979 0x9bfdc32e, 0xd9a6c785, 0xdcab7f31, 0xa3a7ec2f, 0x6f85fafd, 0x082dc695,
4980 0xafc1ae7a, 0x05ebc32f, 0xe7234ac7, 0x4765f107, 0x2fc941b2, 0x075e575e,
4981 0x0587eaef, 0x3afc71e5, 0x5b8c3847, 0x7df3d7e7, 0x1792d5b4, 0x5ff00be3,
4982 0xdf91cfb4, 0xce28b5d4, 0x04fc9ebb, 0x05c1f8e7, 0x5f67efd8, 0x62b5436f,
4983 0xe413903a, 0xebf0cd27, 0x47c0617c, 0x3e616de5, 0xfafdeff2, 0xfe17d4d3,
4984 0x1f0bacd3, 0x21496544, 0xde0333f2, 0x5c7a8d18, 0xbf81a79b, 0xf15b8428,
4985 0x5dea2ab7, 0x36bf08e9, 0xfcbb337f, 0x690fca0e, 0x7e5937f3, 0x01626ebd,
4986 0x4d79e7d6, 0x937f9d74, 0xf145e509, 0xbb7e9143, 0x67ffc842, 0x8a7e9c49,
4987 0x75f8355c, 0x7f069744, 0xda0729b1, 0x2efee2f3, 0x1df8a730, 0x9ddb4347,
4988 0xd08f30db, 0x48aee570, 0x1c355dac, 0x3bf0ca9f, 0xb14b2e8e, 0x773e1fa9,
4989 0xf4d30ee5, 0x68bf00dc, 0x8927b7df, 0x9f80cbeb, 0x3deeda10, 0x9ff9e427,
4990 0x27b6ff65, 0xffcfcd5d, 0x20ff6d5f, 0x9499df0e, 0x4cf87140, 0x71e1279e,
4991 0x286ed6b8, 0xf79958fa, 0x9ee7415d, 0xf92cf8fa, 0x932f1037, 0xc9377e3e,
4992 0xdad2e346, 0x1c51c4a6, 0x9c5a7c7d, 0xfe73dccd, 0xcebb7abe, 0x7e73db9a,
4993 0x7b738fc5, 0x184c071c, 0x3ef838e7, 0x8934f731, 0x7e2ad5f6, 0x9129db9f,
4994 0x30aeee3f, 0x029c7178, 0xcf1a7f97, 0x18774eab, 0xc052e1bc, 0xc7fc543f,
4995 0x12edf7ab, 0x49fc57dd, 0x3bf46fc5, 0x5a771e79, 0x98ffbf01, 0x093275c9,
4996 0x70be41eb, 0x92385eba, 0x79cc675f, 0x77fa1520, 0x246250fd, 0x549fc2ff,
4997 0x6feb54f8, 0xfbeb6c5e, 0xb7e4fbb5, 0xe454fe08, 0x1f23432c, 0x108afd8a,
4998 0xfb43aa78, 0xfbf6871d, 0xae5f950b, 0xf7ec179d, 0x8e7a24b9, 0x6f05f3d1,
4999 0xe2a19de9, 0xfe6295f3, 0xa0fd207f, 0x2feff34d, 0x99d37842, 0xf6b9f69f,
5000 0x85bb5766, 0xfddbd37f, 0xcf286f88, 0xf89d8403, 0x4e73c967, 0x790cfff2,
5001 0xf617eabe, 0xe1dd9df2, 0xc9c1a2e4, 0xdeb97f48, 0xf7f2845f, 0xfac84367,
5002 0x7f8115f4, 0x7c557388, 0xa8dd207c, 0x5dc8b8c3, 0x4d03f3cd, 0x29d7b6b1,
5003 0xd32c397e, 0x1025ebfe, 0xb6ffa207, 0xda85b2f8, 0xa193f41a, 0x31ccf99d,
5004 0x9997ea03, 0x9bf86ad5, 0xcf8b7730, 0xa2f2cd2f, 0x4ac95cdf, 0xd954af29,
5005 0xfdc16b16, 0x2d094dcc, 0x3cae5107, 0xb6db64db, 0x06ebf1e0, 0x9e26f18a,
5006 0xa58eab6f, 0xe34c93fd, 0x6bd65407, 0x5fb57dfd, 0x13c89b70, 0xfc1fe6f5,
5007 0xeb9c3da1, 0xc9324395, 0x97e61d79, 0xd8cc616e, 0x7b82f5c6, 0x4de53845,
5008 0xb8435e30, 0x79215c3e, 0xad77004d, 0xdea1f718, 0xaa27f94f, 0xb390c1a7,
5009 0x51131b6d, 0x5d43992e, 0xea7daa3f, 0xda9bd22d, 0x9775923a, 0xad5d0ba8,
5010 0xb0930d1b, 0x64f10b5f, 0x3697fa12, 0x3fc464db, 0x47daa7c0, 0x1705f8a6,
5011 0xf147bd0f, 0xbcddcce7, 0x7ea3d3fe, 0xd78e34d4, 0x0d3ec48f, 0x76721e6d,
5012 0xa903c1e6, 0x8dd76bb6, 0x198f5aea, 0xe1e8ae30, 0x8efc687f, 0xf3ab269f,
5013 0x9e7a998c, 0x936ccdc7, 0xca9f982c, 0xbe1c7814, 0xeafc822e, 0x1f9f7f31,
5014 0xa140fa87, 0x1c29f9d3, 0x7e4fe7af, 0x045b445a, 0x84b7aefe, 0x70febac3,
5015 0xa99bf972, 0xd9336fbc, 0x91e5b9f0, 0xdff43df4, 0xbc4489ef, 0xdc5a01fe,
5016 0x09d2f997, 0xa47cc87d, 0x1fe5c294, 0x93cfe1ec, 0x2fde1ed1, 0xb07ad2f2,
5017 0x7c815187, 0x9b39f68e, 0xc209ae78, 0xee63ca14, 0xa6fdf5e6, 0xea38d714,
5018 0x6d9b32ff, 0x41d0ff23, 0x8017e779, 0x345f31af, 0xf58b1608, 0x5822e7e7,
5019 0x9a8bd603, 0x92af5c12, 0x6752fd1c, 0xe7823943, 0xd9e4cea9, 0x88fb2369,
5020 0xce7ac328, 0x2649b010, 0xf7c0d7da, 0x74140c47, 0x1638814c, 0xcd0049eb,
5021 0x0f37ac34, 0x219d7512, 0xf38f4c11, 0xad70683f, 0x48eb19bf, 0x2afb7aed,
5022 0xdc7b0212, 0xf59ea894, 0xebc1c925, 0x499d4ae2, 0x56f78fa9, 0x3df09267,
5023 0xaf0e1f7c, 0x727d892b, 0xfd893d4a, 0xae4549d0, 0x19ea2335, 0x6949adc6,
5024 0x0bedbbec, 0xf9e759eb, 0xdab9c63b, 0xc047cf3a, 0xa13f3ce3, 0x1fae2bae,
5025 0xe9f13cf0, 0x0e27adb7, 0xb8376648, 0xa3f1c5fe, 0xf620bb85, 0x5bc52262,
5026 0x68cff8ff, 0x976db3b2, 0x75761ec8, 0xe53f3187, 0x9e783b1d, 0xef7f8dbd,
5027 0x5b7105d3, 0xbd9d9042, 0x7b5bf843, 0xff884adb, 0x234bf977, 0xb0bd7c71,
5028 0x4f8eebe3, 0xd3bf13bb, 0xb4f5f8f2, 0x1e31872f, 0xebf2ed87, 0xb96fd10b,
5029 0x22f97481, 0xcdfd4429, 0x93edc114, 0x4b9e8e56, 0xe7a4f9e6, 0x947f3992,
5030 0x97f1e49c, 0xa3af397b, 0x705e8458, 0x0f491997, 0x944f4c1e, 0x5279fc94,
5031 0xeecb3aa8, 0x951bb26e, 0x3fda248b, 0x9675dd7b, 0xb76176d6, 0xb2e9f934,
5032 0x7b37a431, 0xd5075bcb, 0x33f755cd, 0xe13ec452, 0xdd7f3cc1, 0xf5a16c9c,
5033 0x1687eb5a, 0xaca64ba1, 0xe1d206ff, 0x5bf7ca68, 0xf3eaed67, 0x27bfcefd,
5034 0xdc9c8421, 0xfb3ff9c0, 0x4397e79e, 0x381ba7e9, 0xefc4df7f, 0xf93fff17,
5035 0xf79fe79e, 0x6467e33d, 0xfff43d28, 0x6d003eea, 0x2fbb5f9d, 0x0fef5b40,
5036 0x83c0bc3b, 0x1b4ad6f7, 0x9ad07dba, 0x972c5fa2, 0x63eb5540, 0x1da1329f,
5037 0xd792309d, 0x9a95d6c1, 0xc0a55bbc, 0x5f0500fe, 0x1c7953a7, 0xe0bdc961,
5038 0x673c0389, 0x71a5fc38, 0xc91b2798, 0x0aee0e28, 0xa630f5e7, 0xa14ca4b7,
5039 0x9496f6fd, 0x9b37a0a9, 0xe95ef97a, 0x6f5f3141, 0xad3d2476, 0x214a70e8,
5040 0x943c8eff, 0xea2596bf, 0xbe569652, 0x6de996df, 0xbde95329, 0x87f414b6,
5041 0xebf3f662, 0xd8e63ed1, 0xb2d9704a, 0x683c52a6, 0x1ef842cb, 0xeb5ef511,
5042 0x9859feb8, 0x5f82b68f, 0x8dc0f588, 0x78a41758, 0x94e342d6, 0xc3eccdf7,
5043 0xc0c47de1, 0x7adfac24, 0x99fbe66e, 0x5542f358, 0xc188ef3d, 0xa24739d7,
5044 0xea275e7a, 0x5f3aa3eb, 0x825993ee, 0xb9bf0189, 0x67542cbb, 0xffe46d7c,
5045 0x5bbfc01e, 0x65bdf5e2, 0x1f643e16, 0xc700cdc6, 0xc4f93db2, 0x8ef733bf,
5046 0xc6054bfc, 0x1cfc391d, 0xa5711e90, 0x109c17c8, 0x5f250ef9, 0xdeb5d4a0,
5047 0x53927911, 0xb6817f98, 0xd021f303, 0x37747d4a, 0xa1493eda, 0x1223c7ec,
5048 0x8e790fcf, 0xbe50fcf2, 0x7837ded1, 0xc0b464df, 0xaf1f1ceb, 0x9ef9285b,
5049 0xf93d62ed, 0x617d963f, 0x37e697e0, 0x9da2360e, 0x8f4c6fcf, 0xc38876c0,
5050 0xef12c3ab, 0x753bf98c, 0xf142fd0a, 0xee1f7251, 0xd43bac8f, 0x17bd754d,
5051 0x99fe7534, 0xff748c7d, 0x99c7e0b8, 0x97f5187d, 0x41afd3f5, 0x946631f7,
5052 0x4f550e45, 0x18b884aa, 0xc4d39ce1, 0x5df056e1, 0xe095b3e9, 0xe81f4e7b,
5053 0xaf36c46e, 0xf284ab3a, 0x1a1735ed, 0x5f737fd1, 0x76f074b9, 0x6d1997ca,
5054 0xeacc4f18, 0x2edde750, 0x96fdf2a5, 0x7bfc482f, 0x3d58cf4c, 0x63f9c7c5,
5055 0xd63fc4f5, 0x5f8a70ca, 0x9b2606ad, 0xfb853fb1, 0xf1657945, 0xd367d825,
5056 0xcc1fc962, 0x5d8b643b, 0x83c81b90, 0x4f2ec759, 0xab5d3c40, 0xd3e4aabe,
5057 0x4639331e, 0x6dbf3d22, 0xc8f6b57d, 0xaa57da71, 0x8bc14bac, 0xaded2752,
5058 0x73ecaabe, 0xaa7d9770, 0xd6e197da, 0xfcc18f77, 0xd39efe63, 0xd2cfb146,
5059 0xa8159c92, 0xbeefe6bf, 0xa5577540, 0xbfaeeace, 0x3c357e40, 0xe490e747,
5060 0x4053f903, 0xc95aee4f, 0x022fafeb, 0xc2b6d83c, 0xd7001dfa, 0x6c7eb0cb,
5061 0x78fd60db, 0x039595fd, 0xb4adf5a8, 0xe577bb53, 0x6ddd6a08, 0xeb5ea817,
5062 0x7f63d3ea, 0x1ef3d524, 0xfaf39d97, 0x5247f7a8, 0x93ef5b5f, 0xc6be7823,
5063 0xdf40c87d, 0x988fb82b, 0xb5177f48, 0xf8c4c9cd, 0xae63f3e0, 0x0ebb844c,
5064 0x7c416deb, 0x0f61de71, 0xce3173c7, 0x58e1ed3b, 0x3f6fcb67, 0x2ffdc46b,
5065 0x11bf7a75, 0x710061f3, 0x744d6e2a, 0xf7c0baef, 0x8515b6f7, 0x59af7e23,
5066 0xfffd6b17, 0x536fb175, 0x202afb17, 0xf247a49f, 0x56c73a9c, 0xc2390f6c,
5067 0x89e90417, 0x4f5e4e75, 0x4d939759, 0x99c9b872, 0x683f3b1d, 0x9e3286be,
5068 0xcd8eb0bf, 0x3ebe0f09, 0xf340cd35, 0xa09cf15b, 0x156fef10, 0xea06ecfa,
5069 0x213ed6ed, 0x47f3b6fc, 0x48ddf44d, 0x9985eefb, 0xea5fc41d, 0xb2badc7c,
5070 0xfdf899f9, 0x1844e7bd, 0x75f3c7eb, 0xd31c7caa, 0xcb7ae3d4, 0xd32ccdcb,
5071 0xce29c239, 0xbb40ceea, 0x319bcdad, 0xb706777d, 0x7e548eeb, 0x9527835e,
5072 0xea3d608d, 0xde657f72, 0xfc6072b7, 0xd91d328c, 0x973ea50b, 0x2b67a657,
5073 0x56f33f81, 0x9754bc18, 0xa69fd32b, 0x6c6e22fb, 0x22a5e4b0, 0x623a9f9f,
5074 0x57da84b4, 0xaa7b2f6d, 0xb79e1b29, 0x5c7648d7, 0x77eab5d6, 0xa3edad95,
5075 0x16fd6953, 0xf124e519, 0x53efa320, 0xf8f3d67b, 0xd63cef7e, 0xe30a54dc,
5076 0x82ce8e58, 0x679b51f6, 0xbf433e43, 0xef879b44, 0x4bbbf612, 0x48c1cfd8,
5077 0x8f9c04db, 0x73ca4bfb, 0x4d29fe5a, 0xaf36be95, 0xfdca905f, 0xbcb286aa,
5078 0xdf483975, 0xf6863a09, 0xd8aca1a4, 0x9f341394, 0xe34f552e, 0x60fac11e,
5079 0x907d707c, 0x75b501d7, 0xe5cf4541, 0x06317fb7, 0xf409bdf1, 0x7731da35,
5080 0xe41faf32, 0x087452bf, 0x4e0046f5, 0xc94dbebe, 0x8eb7bf57, 0x0c5d7c65,
5081 0xf679cbf7, 0xcb9f9448, 0xdee9f09b, 0x139fc448, 0xb5ea1eec, 0xcc6b3923,
5082 0xe8268fa8, 0x1dfbf10b, 0x5aba53b7, 0xd27ac267, 0x8f57af9d, 0xf209efc3,
5083 0x863d0fa7, 0x615e9f78, 0x7780fda0, 0x063e5ebe, 0x2ff62baf, 0xd5d6fa7f,
5084 0x807f7811, 0xe1b70f64, 0xbc62b2fd, 0x0f877e3f, 0x226ce933, 0xdcfa0742,
5085 0x8f53a47f, 0xc998f372, 0xf00a9d95, 0x75114fe6, 0xa76e0aa6, 0x314db7a7,
5086 0xaa4fee30, 0xf4bee6ec, 0x741f29cf, 0xea9f2da9, 0xefb87147, 0xaf603721,
5087 0x1d80f7f2, 0xb1d80a8b, 0x4abf6aef, 0xcf842d53, 0x218ec05b, 0xbc29d63c,
5088 0xbfa5af3e, 0x37bfd04e, 0x1e9bd4bb, 0xe783fb46, 0x4a7ca0a8, 0xb8ed3dc9,
5089 0xc33ef30d, 0xf0975fd1, 0xf95e9590, 0x6fd0a96f, 0x73f8bdb1, 0x7af80af7,
5090 0xfad537dd, 0x2d33a9cf, 0x521ffd4d, 0x97f11267, 0xe2526f52, 0x9e04d7b5,
5091 0xa175f695, 0x77f3be37, 0x435c680c, 0x0d60c77e, 0xacc31dfd, 0x44873a16,
5092 0x80e18ef9, 0x8ced1591, 0xe2b3fdc7, 0x93af26bb, 0x8f03a4fc, 0x37f1b5fd,
5093 0x935df8f1, 0x80672784, 0x76463c3d, 0xae8f395e, 0x9e63edae, 0xfbe16d6f,
5094 0x435b6bc0, 0x9912eb9f, 0x297bedc6, 0x33ea87ac, 0x98ed7f62, 0xe44ea25d,
5095 0x596d7a30, 0x4fbcb798, 0x74b79c1f, 0xca09fcdb, 0xc52f5dbe, 0x663cea7b,
5096 0x3acb796f, 0x6afc3be5, 0xd1df8ec9, 0xd31e775c, 0x7ee1f7c1, 0x4be63cdb,
5097 0xce3aeaa9, 0xad0b1481, 0xd125dcbf, 0x9d264cb9, 0xe7f686b3, 0x425922bf,
5098 0x9a3eebed, 0xbc75e5ca, 0x6d3c83a8, 0xf4f1fce4, 0x8bed12ad, 0x90edefc7,
5099 0xc2bf4fee, 0x3a79b7bf, 0xa36f7f8f, 0xef943dd4, 0xd40e6e68, 0x3b3be83d,
5100 0xe51bfbe5, 0xfbe51a7b, 0x239b29cd, 0x07e23ce8, 0xdcc92d0d, 0x5f10f5ef,
5101 0xf61e2bfe, 0x30d0f580, 0x5e4a1f56, 0xfd16a777, 0xbb8d2a6b, 0x476f71e1,
5102 0x29ff086a, 0x7848e309, 0x5ed499cf, 0xa9b385e3, 0xfa8178ea, 0x46e178da,
5103 0x4bee3dd5, 0xdd7a3765, 0x8df94203, 0x2dfe7037, 0x9bfcf3df, 0x4d6dd143,
5104 0x15f3e878, 0x1d44d32b, 0x380e735d, 0x245df1eb, 0x924debb7, 0x51b72fed,
5105 0xf540dd3d, 0x36af4574, 0x73f9f145, 0x7b4a7cc5, 0xb3d71a47, 0xf9d0864d,
5106 0xdc62a9b2, 0x2831d946, 0xcf41da0d, 0x8397f3a8, 0xcbf9d45b, 0xe7d55a5b,
5107 0xa9f50c85, 0x3fc903cf, 0xa61f3ea4, 0x1f3eafd0, 0xf509f866, 0x3b2330f9,
5108 0xdcc3e7d4, 0x7cfaa1f6, 0xab741f98, 0x5fb797f3, 0x5ef9aa9e, 0x77cfcbd3,
5109 0x7e0dce02, 0x4f34c4ae, 0x4e8d2e73, 0x844d2e73, 0xcd1a5ce6, 0xde622839,
5110 0xcd1f4f2c, 0xf5ea34f9, 0x971eb159, 0xb8f5fd7b, 0x44d8fa67, 0x386fae3d,
5111 0x5948f73e, 0x6dfa384e, 0xffd377ca, 0x97ccf821, 0xf48b9ae6, 0x5b1ead71,
5112 0xb1d57c87, 0xf3032c2a, 0x29d5ae2e, 0x83f03c72, 0xbe8921eb, 0x9d5e2f9b,
5113 0xe67bfb42, 0x3f250c35, 0xc8398f29, 0x638caa4f, 0x5873cf21, 0xd6f5c69f,
5114 0x33037adc, 0x6ccbe0c6, 0xd0a81d46, 0x5b124d73, 0x798dedcf, 0x3561f022,
5115 0xbb587ce3, 0xd53458ee, 0x59dd85bd, 0xaac151c4, 0xb9d217eb, 0x5d73da0d,
5116 0x318b586a, 0xbc59e605, 0x41e49da1, 0x628bce7b, 0x9e62dc87, 0x7df516da,
5117 0x8170db37, 0x1d6789ce, 0xee33b446, 0x86fdf556, 0xb32f5134, 0x8dca3b33,
5118 0x1328beeb, 0x02c597fa, 0x4836732f, 0xce0fac16, 0xb84f686b, 0x0ef3fa0b,
5119 0x296f14c9, 0xce3d6178, 0x73a5c9e1, 0xea1e2fd2, 0x45f3fe47, 0xc7092d9b,
5120 0xbc79a2b9, 0xc35de920, 0x9c657af1, 0x5f9e386b, 0x0a327dd6, 0xa761f1bf,
5121 0x5fc8eb2f, 0x08681f00, 0x36166df9, 0x3bcf3824, 0xc44960c7, 0xdd878b3c,
5122 0xa6714c93, 0x75957b88, 0xc7104dbb, 0xe21f6346, 0xe93ebe54, 0x46e8892b,
5123 0xfc1bad26, 0xf80f7c22, 0x9ac7143f, 0xfa156998, 0xcd6d673f, 0x3afae889,
5124 0x5f90301f, 0x2c477731, 0x1b7315f9, 0xfe788c4a, 0xb15ddcc1, 0x79967fb4,
5125 0xae31c71c, 0xba78e855, 0x3260ff21, 0x25b73bcc, 0xe9ab2ecb, 0x17138aa7,
5126 0xe8569d37, 0xba0d79d6, 0x1ba28675, 0xfd754bd0, 0x17e134e5, 0xfbb17a08,
5127 0xbdfbe8e3, 0xfa07a58a, 0x62efbe61, 0x0efd387d, 0xc038cf45, 0x5a64f5c3,
5128 0x29de2abc, 0x8e3573eb, 0x2fba73a3, 0xba24286d, 0xf655e969, 0xe386f3df,
5129 0xafec55f7, 0x8dfd0c51, 0xf66cbeca, 0x5b3eb854, 0xb955f2e2, 0xfa196c66,
5130 0x7d0a6f39, 0x8b88baf8, 0x045c618e, 0x189bfc7e, 0x2dff4117, 0x05fd1711,
5131 0x4f6822e3, 0x6d045c62, 0x4fff38a7, 0x00603391, 0x4293d7e2, 0xd55e4ebe,
5132 0x3193cbf3, 0xdff6569f, 0x80ea166f, 0xb53c12e7, 0x33a74693, 0xf6a1d936,
5133 0xa9a7cba7, 0x830ee9fd, 0xed324c65, 0x81f5e26b, 0x54dbceb9, 0x66de99e3,
5134 0x1b073cc4, 0x4eb81f90, 0xc466c7f6, 0x098cc73c, 0x3ff1aa71, 0xf5554a6c,
5135 0x0c5fa02f, 0xeb294df0, 0x777ebaab, 0x7f5520c5, 0x424065ce, 0x95af723e,
5136 0xe22ce79f, 0x2794ca24, 0x9f0dea06, 0xfa4f0fd6, 0xe9fbc011, 0xd7dd0311,
5137 0xeba143d2, 0xca3acdfc, 0x0cdbcedf, 0x3b79836b, 0x5c91e79b, 0x8a227c7d,
5138 0xdc6987ce, 0x08daff91, 0x61de9fe8, 0xa764fda0, 0xc21ee21b, 0xef4faaf3,
5139 0xefc68848, 0x328d5cf2, 0xb59e91f3, 0xe6559e90, 0x4558692d, 0xc7307fbf,
5140 0xf947661b, 0xf3dfb39f, 0xfdc7d2b8, 0x0645b401, 0xecb8e3e5, 0x3f4449f5,
5141 0x7b77e107, 0x3fc5e538, 0x058f3034, 0x1d79cbfc, 0x250fae1c, 0xb3fd80d6,
5142 0xfff4efe1, 0x6e71c011, 0x0e957362, 0x48f928fd, 0xe7cbe902, 0x5b7c8665,
5143 0xe740d4b1, 0x4b7a2f09, 0x267d8ade, 0x7a72a5e5, 0x1d3bf4cb, 0xcd187b6c,
5144 0x4381bacf, 0xdff2dc60, 0x5eb93d84, 0xffa8b9e4, 0xf5dec1fb, 0x8f913f82,
5145 0x8e658c3e, 0xe7960258, 0x963a3e1b, 0x009e7540, 0x7043bd3e, 0x3bd4bfdd,
5146 0xbd83a5fb, 0x3bcaa8fa, 0xfddaf484, 0x5a572409, 0xb91a77bc, 0x1ca0f2de,
5147 0x197d0148, 0x9dfe3390, 0x3d833cd5, 0xaafa4ed1, 0x55f50520, 0xe50306e7,
5148 0x11de9915, 0xcf70ebcd, 0xef2b1f13, 0xc6dbd4e9, 0x4d9d7c20, 0xe11df459,
5149 0xd9320ddc, 0x3e3fe43b, 0xebe3cbde, 0xe30bb28d, 0xe4934f75, 0xcb5d78c2,
5150 0x0e96cb37, 0x9815dfa7, 0xd9193885, 0x4f9c0f53, 0xa50775e1, 0x3f0f78bf,
5151 0x74159fd7, 0x0e0da7e8, 0x7f03475e, 0x5f9f325f, 0x26bc7739, 0xf0a74ffb,
5152 0x878ba668, 0xf7e0c6fa, 0xcb8f6738, 0xb36767c4, 0x0325879b, 0xedd13f3d,
5153 0xe823f61d, 0x73d13c7f, 0x70fd8f46, 0xebc454d7, 0x0c86dd12, 0xabba1efc,
5154 0x6e87bded, 0x7a3ee783, 0x312760d6, 0xfa40915f, 0x45f6f163, 0x7df75f99,
5155 0x3ef05810, 0x48e8cf3c, 0x4b9f0091, 0x30632d6c, 0x3980b07f, 0xf8e21d85,
5156 0x79e0edb1, 0x9e26cb0c, 0x30af78d7, 0x67ee3d6a, 0x5bc9a79b, 0x13be27bc,
5157 0xa92e905c, 0xa2ed84fc, 0xf9c74f3f, 0xf3c73d9b, 0xd2a7f059, 0xfbf16eff,
5158 0x57de8a1e, 0x6b0d75f4, 0x7fa9f3a6, 0xf04d9e94, 0x34bc922c, 0x9a4f0eae,
5159 0x65551506, 0xcd6af1e1, 0x8a5e6133, 0xe9606d47, 0xdd80fc82, 0x6e7a36e9,
5160 0x47d9f1b1, 0x32176d91, 0x669f5f3f, 0x6f0647dc, 0xa7ab3f95, 0x6cb2a9bd,
5161 0xfcd2b06d, 0x57ee3b06, 0xb4e4285c, 0xfaf259b6, 0x6ec83af8, 0x2cf3102e,
5162 0x6b537610, 0x23d87a9f, 0xa05a1d8d, 0x59acb3b1, 0x5e01576d, 0x815b973a,
5163 0x33a70b57, 0xb0f08a32, 0xcf9f99b8, 0x1ef2e551, 0x4b70449c, 0x0f64a076,
5164 0x67321678, 0xe3ae2c69, 0x6b8f1e19, 0xabaed3e1, 0x9d62bc07, 0xecabb85a,
5165 0x01727c17, 0xda0a3dff, 0x8759a9df, 0xbfad0f42, 0xcaa5d0a6, 0xd55bf1c3,
5166 0xdf3d1126, 0x3207eabf, 0xf0aa07da, 0xff816b0b, 0x4e779ea9, 0x70b67d42,
5167 0xacdfe813, 0xfc28ff00, 0x44b598b4, 0x31d4bf23, 0xd496235f, 0x7e5afacf,
5168 0xcf0b3238, 0xe7463a65, 0x7d585547, 0x80b174fd, 0x1fdfcf42, 0x8041fb2a,
5169 0xbe78b5af, 0x17af5d16, 0x11d44c6f, 0xd3c039e8, 0xfa64a782, 0x9c6827ae,
5170 0x243d7f88, 0x8f1ed54f, 0xd5cbeb11, 0xdc3e7e7a, 0xeb74e0b5, 0x5d29eff9,
5171 0xfc5ede13, 0xf70aefa4, 0xf9bde907, 0x4262fd59, 0x9d6529e9, 0x72bd08ef,
5172 0xb7aefb4d, 0xbec8c5df, 0x8f984827, 0x575f4de9, 0x00bebb09, 0x67b43ced,
5173 0xe740bf36, 0xe9bfbe2e, 0xd55f3a05, 0xda02ecf8, 0xf3667097, 0xf7f087bc,
5174 0x98ecce23, 0xe17d7647, 0x775d8a63, 0x85fd8319, 0x9e73cd92, 0xafc85ff8,
5175 0xdd5384cf, 0x4bbf6ab8, 0x47a039c4, 0x336d9c61, 0x136c9bd7, 0xd10ba3d7,
5176 0xfd92e5fe, 0xddc709bb, 0x09bae557, 0x3ae83ef9, 0xe6fbc5d9, 0x07b77eb9,
5177 0xb7efbde6, 0x2d0f7691, 0x79e3e2d9, 0xed0f8b67, 0x7f3ded5f, 0x0bbf4539,
5178 0xeb791f25, 0x87bd8ac7, 0x577aedee, 0x97ca0642, 0xf2b5f3b0, 0xfa0b0cd6,
5179 0xfc2ec205, 0x173df1b3, 0x14fe4df1, 0x4dbbf7c7, 0x6defcf1c, 0xdc6f78e0,
5180 0xd3e297d1, 0x92fa9b77, 0x8eeef51f, 0xf9ef847e, 0xe4df01eb, 0x7ed4db47,
5181 0x1be01354, 0x37c404e3, 0xbf7735c0, 0xcedbe04d, 0xf1c4ddf1, 0x76f036cc,
5182 0x7abc0f7e, 0xfbf4fce8, 0x8ecc3dfe, 0xe187c17e, 0x3e97f23e, 0x99d329dc,
5183 0xa59f8a67, 0xb19f39f8, 0x1fd1c7e6, 0xa8bdf053, 0xea087fbf, 0x7f8d8a97,
5184 0x2fbc468a, 0x2393c9da, 0x1ccdf03d, 0x076fe849, 0x2fd57fde, 0x0848cb2a,
5185 0x21be8bf2, 0x9398ea5d, 0xe1d723f6, 0x82436479, 0xbf2b3df6, 0xe7dda65b,
5186 0xc8f9e36c, 0x99376630, 0xed349e10, 0x18b9afef, 0xbcfe7bee, 0xf75985df,
5187 0xab771c90, 0x12634f7e, 0x9cf019f3, 0xd122d602, 0xe5da967e, 0x188ba34b,
5188 0x4f5a3f9e, 0xe0cdac70, 0xbc2bbd76, 0xb2fc833b, 0xef1c613d, 0xf3aaf19d,
5189 0x6fdd2789, 0xb457f98f, 0xf9f847fb, 0x763c93c4, 0x1a4e67ca, 0x2ab93431,
5190 0x2e0bae88, 0xab8973f3, 0xf2e6032e, 0xc6fdf7f1, 0x0587bed2, 0xcea853cd,
5191 0x496d055f, 0xbe5ef8f0, 0xc19b5bbf, 0xb8539be3, 0x973c3ca6, 0x9d7efc49,
5192 0xea8d1738, 0x539b80b4, 0x373a4ee1, 0xc98254ef, 0x8bbacfce, 0xeffdf3a1,
5193 0xa6707a16, 0x13ed20f9, 0xcc3c7987, 0xbfd6e78a, 0xab014069, 0x8b3c7530,
5194 0xe4ecf021, 0xe935eef7, 0x837f6b70, 0x7773e445, 0x13d7157d, 0xd51d009e,
5195 0x23b9b9e7, 0x9a3fe742, 0x87255e05, 0x610cea83, 0xbc047730, 0x3619e7ff,
5196 0x6fec5d7e, 0x9e805b67, 0x85cf3d51, 0x0f33ae53, 0xa6b60f3f, 0x2b7dfe18,
5197 0x7a848ce3, 0xfaa9d643, 0x7f7e4635, 0xc9c4c67b, 0xf631469b, 0xf7ac0306,
5198 0xf194bf45, 0x8c4e7f38, 0x4d75f717, 0xaca373c6, 0xaf89ead8, 0x4799eaa6,
5199 0x3326dbc7, 0x79c43bd6, 0xfe049351, 0xbe608fa6, 0xdf7de018, 0x89b9f561,
5200 0xbe74f977, 0x93af009b, 0x21ba5cf1, 0xcd9cfe78, 0x38f78160, 0x8c3ca4cb,
5201 0x7f566a4f, 0x64f77833, 0x94de4f94, 0x8e9d7d06, 0x9e63f9c3, 0xf989988f,
5202 0x2cc3c079, 0xe72fdb3d, 0x5e237a71, 0xed1b56dc, 0x2a5ee8f3, 0x25147ed1,
5203 0x7bd0af2f, 0x4f2f2068, 0xe0299c74, 0xa29a7983, 0x686379f1, 0x50ce1d7a,
5204 0x8a16e8e2, 0xf90897af, 0xe5c8a25c, 0x9e5cb50e, 0x7e823a45, 0xc8893dc6,
5205 0x0b453357, 0x6bf9a4eb, 0x73947bc4, 0xf064cfd3, 0x0c99e97c, 0xfe387f5e,
5206 0xccc7df2d, 0x45469cfc, 0xf8c36b3e, 0x27fbcafc, 0xc333b68b, 0xf02bf34a,
5207 0x1ff1f368, 0x7e43596c, 0xccb7f552, 0x1be907c7, 0xc6497baa, 0x7a88f9ee,
5208 0x49c25fe9, 0x5b1a66ee, 0x7b9bd5fa, 0x1dce538e, 0x037e60ac, 0x55300faf,
5209 0x6cb4741d, 0x2b2c73a6, 0x9afbfe24, 0x1e51455d, 0x6be60c5d, 0x8ada440c,
5210 0xe973f31f, 0xfbe709de, 0xee632b3b, 0x607e849b, 0x4f51b445, 0x7f31ece7,
5211 0x40565654, 0xc91636ef, 0x04214e74, 0x6eb19382, 0x7feb06b6, 0x23b0ffbc,
5212 0xa24bb28d, 0x51d7b3ff, 0x02bb4d1f, 0x43fea7f4, 0x0f101d93, 0xf7101d75,
5213 0x7cf4c3d9, 0x8f8203d7, 0xfde73f3d, 0x37f7285f, 0xe53afef3, 0xffde16fe,
5214 0xe8bf3299, 0x5fdcd46f, 0x4bffb9a5, 0x627c4fde, 0xfa0f64cb, 0xa59cc5af,
5215 0xe8956e2b, 0x05ca3577, 0xf6ac559f, 0x742b7e11, 0xcc5b797b, 0x6b82ba7c,
5216 0x74ce2b8f, 0x211fa396, 0xa1467547, 0xe5909e9d, 0x75bb4728, 0x2b2bba6b,
5217 0x53c5da13, 0xd6118f24, 0xc97b8ecd, 0x45ea4c6e, 0xbe0b971f, 0xf9f1b22d,
5218 0x3cc37c14, 0xbf0b3303, 0x847e3cfd, 0x4f35412b, 0xf3c0f5fe, 0x798f5b6b,
5219 0x3ccf5d46, 0xbaf52cba, 0x89e83f14, 0x385dc76c, 0x2e1ed69f, 0x063da9f9,
5220 0x35ec50f3, 0xeae1fdf1, 0x987c8c96, 0xbb73c97f, 0xefd0aa33, 0x1d40fe12,
5221 0x3c7cc3da, 0xc3db82e7, 0xf24fdb8f, 0xdabb707d, 0xbf30638d, 0x3db06d0f,
5222 0xce05e9ac, 0xd89d4c8a, 0xd791b047, 0xab3b9ec5, 0xd12e7a47, 0x0c799cb5,
5223 0x52adfbed, 0x1127dfe8, 0xe5ea9dcf, 0x66e68e77, 0x90d43d72, 0xeb8398e3,
5224 0x3464c92c, 0xe84d64be, 0x9b7f9a73, 0x8572edc9, 0x86f37bb0, 0x806c9945,
5225 0xaee3c2e7, 0xaabfb835, 0x1e564b6a, 0xa56785e6, 0xfcc92f17, 0x376abcda,
5226 0xf1b6abcf, 0xd5856abc, 0x37941cbf, 0xedb33a7b, 0x633a5361, 0x914dffe3,
5227 0x78591033, 0xe94c2cb6, 0x74b939bf, 0x617bcf14, 0x4713dd7f, 0x39b9461e,
5228 0xfe60f084, 0x08e0f87c, 0x591d0bd4, 0xe80b3a91, 0x7369598b, 0xacfe469e,
5229 0xda03fe1c, 0x1614532f, 0xcf0e7fd5, 0xcc5f13cf, 0x42ae734a, 0xe63c7138,
5230 0x5f465c43, 0x0eb05dc2, 0xed32abd7, 0x890d7553, 0x4efc8574, 0xe9e1e059,
5231 0xebe10b4c, 0xfd199010, 0xe50e0514, 0x2fe7e0fd, 0x9d7cc3f7, 0xe28653ab,
5232 0xb4be4e77, 0x85996da2, 0xd2fbf781, 0xbf048f5c, 0xfac753bf, 0x4df1a863,
5233 0xc05878e1, 0x06e90db1, 0xcc9473ad, 0xdef1411c, 0x5548d2d4, 0x3884da7f,
5234 0xd7ce08e6, 0xf5554b4e, 0xaafa2bcb, 0x7f3ddfc6, 0xc4feea90, 0x7d417f30,
5235 0xbbdbbf90, 0xe7e1e49f, 0x4545458f, 0xbfbcbee0, 0x36f67db7, 0xd7745efe,
5236 0x7d1db253, 0xb67b45da, 0x03478dbd, 0xb39fc45f, 0x8da43ca0, 0x1d1f66f2,
5237 0xd73f1992, 0xae0fa1c2, 0xfe639d0f, 0x1077f147, 0x2907ab7a, 0xcb12eef1,
5238 0x801dfa7e, 0x3a0f5d1b, 0x41ea2998, 0xed0f2c79, 0xb7fac5e1, 0x67576f28,
5239 0xb73bebe6, 0x8b4f9f9b, 0x057f53e7, 0x3e077efc, 0x65e1fe88, 0x4bb5e50f,
5240 0xfd534f5a, 0xeb932aac, 0xa5b4bae9, 0xdd8bf47a, 0x181da2d0, 0x062afa03,
5241 0xcedfc5f8, 0x7dc2ef06, 0xdc51596c, 0x953cbf5f, 0x2be438b1, 0x9439e79e,
5242 0x53bf4b18, 0x8ca9a4bc, 0x8e5dd7ae, 0x975ff9a0, 0xcd4fb4fd, 0x754492f3,
5243 0x95a98988, 0xc6bf71ab, 0xee4f08a1, 0xc4ef7832, 0x8651dddf, 0xc5dbab78,
5244 0x944c91f7, 0x0a5828df, 0x19734d6d, 0x66513f3d, 0x17f02487, 0xfb7097c6,
5245 0xbe6d113b, 0x46e0f715, 0x2bbb47ad, 0x7ffd7d1b, 0x18c67a85, 0xe6267a45,
5246 0x7ef4ddf2, 0x3d1365f7, 0x88f425df, 0x35c383a1, 0xae93b2fa, 0x59f0fc2b,
5247 0x77eab666, 0x4f090c7f, 0x91f7f1e9, 0xc68c1d0d, 0x903cbb8f, 0xafbd655a,
5248 0xfa77f80e, 0xc2435b5d, 0xfa5fb4a7, 0x42c978d5, 0x0f46886e, 0x1e1faa5f,
5249 0xa9e842c3, 0xf111efab, 0x5fea1848, 0x72ccbf68, 0x3012da44, 0x63d0e99e,
5250 0x4d99885d, 0xffe44fb4, 0x0538cd00, 0x00800076, 0x00000000, 0x00088b1f,
5251 0x00000000, 0x7dc5ff00, 0xd554780b, 0x399ef0b5, 0x66491e67, 0x99212726,
5252 0x4ce21024, 0xe010245e, 0x0f080424, 0x860240cb, 0x084013a7, 0xbc80e834,
5253 0x2b101025, 0x0337e95e, 0x60d22049, 0x45405283, 0x68b0503b, 0xaaf8ff6d,
5254 0x0131f5a9, 0xe94a0fe4, 0x7ab7bd60, 0x52036b6f, 0xe08d4504, 0xb16dcfed,
5255 0xbdad6bfe, 0x3267324f, 0xfdeded41, 0xbe3ef9ff, 0x3ef6759d, 0x7af6b1fb,
5256 0xb30fb5ef, 0xcb5d8aca, 0x0afb188b, 0x9318137f, 0xbb302e8e, 0xda663286,
5257 0xb1ecc67d, 0xb2816631, 0x96bea23c, 0x046b4f31, 0x2e4995ac, 0x19236323,
5258 0x3950b6fc, 0xfbc1db0b, 0x631f77cc, 0x576ec64e, 0x4a6dff18, 0xb1832c65,
5259 0xed04dfbf, 0x0fde7b53, 0x852ea01b, 0x968bc0b1, 0xbbf861e0, 0xc72fb65f,
5260 0x89e1f505, 0xec39faac, 0x55670e47, 0xcddfa1d9, 0xda15b29d, 0x39559b31,
5261 0x9ff806ec, 0x6f82ff34, 0x8ba77f39, 0x12b7ffcf, 0xfdfd84db, 0xb084c276,
5262 0x7ed5e607, 0x921188ff, 0x31dfa7ab, 0x63b5332e, 0x5675d74a, 0xd7bad8ca,
5263 0x603b5c12, 0xc1fb337d, 0x5ebb8033, 0xba0f04b5, 0xa43339e9, 0x68396960,
5264 0x8e75fa80, 0x8c2f7cae, 0x5c7afe5f, 0x7e830d88, 0x19938f5f, 0xae52f38c,
5265 0xa5e20c6f, 0x1541f5fc, 0xf24c0706, 0xa0cc8b15, 0x3c9ba4dd, 0x5f79f163,
5266 0xaf5e8df3, 0xf9c60256, 0x18a7cefc, 0xadbbbdf1, 0x5529b5fc, 0x22624086,
5267 0xc954d774, 0x16c608d8, 0x9b0d9b5f, 0x6b92d8c2, 0x5afb04f1, 0x75abf3f8,
5268 0xdf705369, 0x49866eae, 0x6c963ac3, 0x017d0c36, 0x765cc5d6, 0x30f00f35,
5269 0xada2c073, 0x5339e60c, 0x677ad232, 0xd60a490e, 0x71dbd343, 0x73e0c7bf,
5270 0x664861d6, 0x3db97a6c, 0xd6f18460, 0xdfa8535c, 0x1a2e6bda, 0x64b5ed6f,
5271 0xb35dd782, 0xdae4b952, 0xb96e7a60, 0x801e6466, 0x1c035e97, 0xdb273c00,
5272 0x3fd70ab7, 0x4a96feb3, 0x35b7cf1c, 0x8b67d4a3, 0x82b317a4, 0x92f40574,
5273 0xb3d6dcbe, 0x05f6fafe, 0x2fe85530, 0xb2f44bc5, 0x88f2ca14, 0x0e8265fa,
5274 0x56b6f1a2, 0xa537ffec, 0x5f411a97, 0x3ca16c4b, 0x54c1e023, 0x856ea717,
5275 0x71495cf9, 0x6cbc414d, 0x6fe38078, 0x6e5bc983, 0x786ef987, 0xcec2a0c4,
5276 0xd9473bb0, 0x32f00cad, 0xb33addea, 0x176e822f, 0x5cc61b5c, 0xd739feb0,
5277 0x7dbca972, 0xae336fa0, 0x79b5f17f, 0xa8c34f02, 0x2364d664, 0x46d8c51b,
5278 0x4e1757dc, 0xb3ef9928, 0x7517df98, 0x85eed3a3, 0x6538bff1, 0xb88bfaa2,
5279 0x5530252f, 0x9c09e04f, 0x51682997, 0x2ebcc00f, 0x8140589a, 0x9f73b8ad,
5280 0xdf000591, 0x41f4a14b, 0xb07b5d09, 0x291de59d, 0x92ed8ed8, 0x04a92798,
5281 0x2deb09f1, 0x057c63e0, 0xc2192eff, 0xfd42f7f9, 0x965b3327, 0x81e0731b,
5282 0x86552a74, 0x9cf27e75, 0xbe7824c4, 0x4e1bfd6a, 0x95ab1e58, 0x5029640e,
5283 0xcc10d1bf, 0x3d8c4937, 0xe2f6fb22, 0xd85a3eba, 0xd0656ffa, 0xf3cb7cee,
5284 0x0d57dc0e, 0x2872adaf, 0x0569fb0f, 0xee60067c, 0x6552cdad, 0x26c346d0,
5285 0xa1ed0d54, 0xa39e8d6f, 0xb5f57ce9, 0xaba7a26c, 0x2fa19675, 0xdd031d20,
5286 0x415af3e2, 0xfd2177ef, 0xacea6943, 0xe9c8f414, 0x5aeba35f, 0x5aadcb99,
5287 0x0030625b, 0xbff99bf3, 0xf500fe80, 0xf2a85f6b, 0x2bba444e, 0x5079a830,
5288 0x32fc11ac, 0xe0f83a53, 0xcf83e458, 0x787ad452, 0x579af93e, 0xc1f3d73c,
5289 0xc674fe4b, 0xbc4b19f2, 0xd5c690b6, 0xe822dfe8, 0xdff484dd, 0x2d83de8f,
5290 0xd9fffe05, 0x77ff9edf, 0xdb90f3f8, 0x6be216f7, 0x7fca1c9a, 0x3b4b052c,
5291 0x94e4d1d1, 0xe7e9192a, 0xb3cfcb9b, 0xd59e7e42, 0x7db5cfc9, 0xb7f0cfc8,
5292 0x04d787e4, 0xd85a543f, 0x2e22de1d, 0x7bdb67df, 0x3d97ebfa, 0xea0b9ce9,
5293 0x7819743f, 0xf343ff7f, 0xca5bf0fe, 0x86fd7ffd, 0x42afff72, 0x79cb47ee,
5294 0x9ca1fd06, 0xc2d5ecff, 0xf781ea20, 0xd405e819, 0xb824af7b, 0x403d0b0e,
5295 0x313e227a, 0xd03d2378, 0x5fe77b90, 0x7f03d0fb, 0xa3fdbc43, 0x3fa3407a,
5296 0xfe345f8d, 0x9a21f8d0, 0x987e347f, 0xf13503fe, 0x401fdc5e, 0x1fe461cc,
5297 0xae0cf039, 0x5095d6a3, 0xf1a97c8c, 0x0c17dad1, 0xf4bd67c4, 0x1e9be083,
5298 0x0bebd13e, 0x3e341f8d, 0x56a6f8d1, 0x28b2c3f0, 0xb526387e, 0xde163c3e,
5299 0x15f6eedb, 0xf87b53b9, 0xd173cd63, 0x7a4fa17a, 0xcb4f4862, 0xd218ea52,
5300 0x91942d53, 0x83e964f4, 0xdfdd8a9e, 0x126e9e8e, 0x9e8ebfed, 0x6a66dc2a,
5301 0x4f483ff7, 0x3191ee15, 0xfbb269e9, 0x5c57689f, 0xa97dfbad, 0xb573e60b,
5302 0xbbace414, 0xbfa6de87, 0x90ddb8c5, 0x7e915763, 0x3af9e23a, 0x8303cc3b,
5303 0x2beed8f5, 0xd4788756, 0x67db52e8, 0x86580ecd, 0xb6e50074, 0x9c2aef6c,
5304 0xa07c476f, 0x9337fd68, 0x96cfb477, 0x53d9b094, 0xd61dfb84, 0xecbeffe9,
5305 0x72dfb5c5, 0xdfdc6b9f, 0xddf86e4c, 0xd17b74ff, 0x272d8eef, 0x7d9dff02,
5306 0x7f0e599d, 0x94f047f6, 0xf61e33d7, 0x660287e7, 0xcbf22f61, 0xfead32bc,
5307 0x191e2d37, 0x3dfc03e5, 0x30f04696, 0xc381e12b, 0x0ae1d381, 0x87f4e798,
5308 0x5803ebbb, 0xa27c793f, 0x0c798fe8, 0x8ffda7ac, 0x6e15bc0f, 0xc2defd26,
5309 0x94ebeff1, 0xe02343bd, 0x11ed8052, 0xbc145970, 0xc877b79f, 0x7ea14c9d,
5310 0xa0af9c82, 0xc209437f, 0x7e827f5a, 0x55f8e799, 0xc52cf3c0, 0x3ec076c0,
5311 0xf0394bad, 0x6b9455c6, 0x7066066d, 0xfd81e045, 0x04c9ebde, 0x20c578ba,
5312 0x7b08ffe0, 0xf85b1972, 0xb84f8702, 0xc812d4ff, 0xbe02fd15, 0x9b7408d7,
5313 0x091e0d5a, 0x66535bfa, 0x7bbb6608, 0x5b84fbe3, 0x7cdaabd3, 0xdfea5540,
5314 0x6f94e667, 0x6d1a3ef7, 0xbd367ef4, 0x8b7cb21f, 0x678fe7f1, 0x7b0c609e,
5315 0x1f820ff8, 0x63134a2a, 0x4b779fd6, 0x01d7ff1c, 0x4787c6d6, 0xc1fd6073,
5316 0x5975fc18, 0x1a3617f4, 0xd6ff3e05, 0x36167482, 0x6bfef86b, 0x327be20b,
5317 0x8274dd63, 0x13e30374, 0x7fdc7ffc, 0x7cc936f5, 0x7c289eb9, 0x6fbd68dd,
5318 0x2057c0c6, 0x372cbf6a, 0x6ee9f7c0, 0xbef3d0b9, 0xe87eff4b, 0x4ef5fb46,
5319 0xdd05f1af, 0xd8e8d4ae, 0x44f7a3a3, 0x99f44bd9, 0x02506298, 0xbd6b8f40,
5320 0x2fe8cd71, 0xa9a7f0f4, 0x8e14f10a, 0x87a9e3d3, 0x1555ccff, 0x448fb236,
5321 0xe42eeb7b, 0xbbb1af5f, 0x6ec7e73d, 0x029e66ba, 0xd29a2bc0, 0x41d27ef8,
5322 0x8d80aecb, 0x09ea82e8, 0x77988dce, 0x46b63f34, 0xf8a3e3c1, 0xc91ff057,
5323 0x8007d40f, 0x6f943ca7, 0xaecd6729, 0xb3513a08, 0x313e9e39, 0xa7946ab0,
5324 0x8edc49e1, 0xd2f3670c, 0xfaa06d9b, 0x1fbe6cb2, 0xe386511e, 0xa7a0f023,
5325 0x2bfa109f, 0x3c26eb11, 0xd6d1482d, 0x0335505d, 0xe64e15d6, 0x73b2d3f5,
5326 0x7b320577, 0x66fee8e0, 0x05541764, 0xcffb228a, 0x5d78833f, 0xcde6f020,
5327 0xeb06741e, 0x4b507935, 0x11f44284, 0x8b507940, 0x4de861f4, 0xbdd9e91f,
5328 0xf51033e8, 0x8374c7be, 0xbf7ab3f7, 0x9f7a89ef, 0xcdbe5299, 0x66df62fb,
5329 0x656bed44, 0x4456bed4, 0x1c1a35c1, 0x4d5fc9d4, 0xdb692f2e, 0x7984e8d5,
5330 0xe40475dc, 0xe7a48b2c, 0x77cf4451, 0x8efd1a29, 0xbb7a833e, 0x08cb9e87,
5331 0xf62add9e, 0x1766302d, 0x942a9fea, 0xe07b63c3, 0x08872839, 0x19e55b1e,
5332 0xc6afa91e, 0x3db942ed, 0x3f6b49bf, 0x6c2fda9e, 0x99bbfad0, 0x647db5ea,
5333 0xd154ef81, 0xc3b90abe, 0x60ce1302, 0xf857eafd, 0x3d07f5fb, 0x0fc86e67,
5334 0xd978512d, 0xa207051f, 0x1afeefda, 0xf510d6fd, 0xfaa8e6fe, 0x5f7828e6,
5335 0x7fa4dc14, 0x0352f17f, 0xa062e1f1, 0x6888dc07, 0x8fa68cbe, 0xedbbb387,
5336 0x6e7d6e9c, 0xa77d91b0, 0xf5e9abe3, 0xe0fc7e1c, 0xa2a6aacc, 0xd6fb3808,
5337 0xdff700aa, 0x2697480d, 0x73207fc6, 0x83d01203, 0xf9b90fa9, 0xb2e8be83,
5338 0xf3df5a20, 0x9fe13ffa, 0x332f6819, 0x4c725d9d, 0x92edc3d2, 0x6745ef36,
5339 0x43e11636, 0x42a9ae0d, 0x5efa7a7f, 0x9fc0bafd, 0xaac2f015, 0xbb08cc8a,
5340 0xcaa0b028, 0xad4eb113, 0xbf2f94fd, 0xe7bc7092, 0x1d5417b3, 0x499afa82,
5341 0x983abca1, 0x2f324d67, 0xa84a5f41, 0xf889d7af, 0x255794cd, 0x9acbea2f,
5342 0x86de50f8, 0xb27588a2, 0x675c7cd6, 0xed12fdfb, 0xf61ea04f, 0x98b4f007,
5343 0x8f0a2381, 0x331e64ee, 0xc4fa81cb, 0xc24f4dc4, 0x97eec77b, 0x7e9ea136,
5344 0x273f537f, 0x39c943fa, 0x963ceedc, 0x19739378, 0x7709edc0, 0xdf6dbc90,
5345 0xa3ca993e, 0x975b6792, 0xd9dbd8c2, 0x856caaab, 0x78489f58, 0x69707d3a,
5346 0xefa016d5, 0x7a2ed933, 0x38ac97df, 0xdeded0db, 0x5d876261, 0xe2952f38,
5347 0x5a778b48, 0x7ce0778a, 0xa2710cb6, 0x47e4b9fd, 0xa0325355, 0x934692dd,
5348 0xa754768a, 0xf9c2c951, 0x364c76f9, 0x06d2fd63, 0xa16e0651, 0xffbff5f2,
5349 0xed01dea4, 0xa8371ebb, 0xcdfda107, 0x35beb45f, 0x4d15e00c, 0xd16e2a39,
5350 0x2807e06b, 0x7db9ce30, 0xd0128283, 0x757107e5, 0xf6f16627, 0xb8afdb0c,
5351 0xab3d3aee, 0xca4bdb14, 0x017f6856, 0x7cfda39e, 0xa0e901e1, 0xb0e5e701,
5352 0x49601bc7, 0x1464be17, 0x68d0b9cf, 0xee7c6209, 0xfb77cd9c, 0x9f671c3e,
5353 0x767d2d09, 0x1872e0c1, 0x1d9f0f00, 0x3d2ab7bc, 0xc45b9f03, 0xb49bdefe,
5354 0xd8b0f018, 0xa43f4dd8, 0x7127964f, 0x7becb3f8, 0x3ac30eab, 0x88323c2e,
5355 0x722b57e2, 0x80d95d3c, 0xcf5cc2af, 0x107e58e7, 0xebd6f5c7, 0x40ee977f,
5356 0x97d7fe3b, 0xbe913897, 0xd6f426fe, 0x3896d76b, 0x55d84497, 0x89913fcb,
5357 0xbb375e0e, 0x5f7ce236, 0x40681f8f, 0xa0e81b3f, 0x97c9c61f, 0xe805bf0a,
5358 0x31f3d379, 0xcd7fabec, 0xdabf6896, 0xde3a907f, 0x6deba3a5, 0xdfc8a7a4,
5359 0x93f6d800, 0xa002bbad, 0x365bcfdb, 0x8e500fb1, 0x7147ee6d, 0xc84ca5db,
5360 0x82e26781, 0xf4b157e8, 0xf8c8fcd6, 0x8a1f374d, 0xd80c7ff6, 0x847faf09,
5361 0xfdf7e8f6, 0x761ff031, 0x7eddeb66, 0x401ec385, 0xbb43e2e3, 0x78fdc65d,
5362 0xb85ff65f, 0xfe5bde0f, 0xc0f489b8, 0x3753c7f2, 0x40b8e177, 0x8b571837,
5363 0x1c82d75e, 0xf4638f13, 0x878197c5, 0xfe742aab, 0xbf24c3ca, 0xfccbe2fb,
5364 0x75543c9f, 0x5f37d6c8, 0x7cb850ae, 0xc9b8f29a, 0x62b4fc8b, 0xa0665da4,
5365 0xfe3d264f, 0xcfc461c6, 0x2571f58a, 0x8af89816, 0x5fb42dc7, 0x407b769d,
5366 0xc39f7a81, 0x5941272e, 0xd6e5c39a, 0xed171cbc, 0x64c4b973, 0x0d95096b,
5367 0x82bd6f18, 0x2f800de1, 0xcf787a6d, 0x23e71868, 0x1a379c16, 0xc3c577f0,
5368 0x0bcaf4e9, 0x991dc512, 0x826791ec, 0xb8c95cbc, 0xf93da89c, 0xfc2279bc,
5369 0xc56eb2b9, 0x5707f40c, 0x3ae74d05, 0xf18e0f85, 0xf9ac75d8, 0xea186973,
5370 0xa273fd57, 0xf3d62704, 0x49d61adf, 0x35b6a372, 0xdaebfbf6, 0xe467cff4,
5371 0x0c2e53d8, 0x2e431861, 0x2bb10c01, 0x067ca675, 0x03615c4b, 0x96f582fe,
5372 0xbcd037ef, 0x82926c57, 0x79779816, 0x3e2f1e3f, 0x37fd87ef, 0x0a03bad3,
5373 0x73762bc0, 0x1982b3bd, 0xf3f85682, 0x29ebfd96, 0xc84c797e, 0xe606c599,
5374 0x20fefa45, 0x3f42cd4e, 0x71e3f97f, 0x4f15df84, 0x47b7faac, 0x2dcebde0,
5375 0xfd225333, 0x174825ea, 0x9accbf1c, 0x87cfd3dc, 0x859fbe5b, 0x63fe5ff4,
5376 0x3d618ff0, 0x2fd8922b, 0xbf71b816, 0xb65cb232, 0xb62b769e, 0xdbcf9fde,
5377 0x7e0d7f81, 0x2407e2f4, 0xd17b075a, 0x78107a42, 0xdbc4895d, 0x669386d2,
5378 0x5bff1173, 0xdafb0a71, 0x39bc7285, 0xe7fbc12c, 0x11b25ea0, 0x119d02fe,
5379 0xb03bf271, 0x23920caf, 0x8d5f5c3e, 0x6cc770d1, 0x8ccba7ea, 0x8733bd7c,
5380 0x441b43c7, 0xbd4b38b9, 0x0fcfe29d, 0x6eadd45a, 0x4a348fde, 0xbbfc03cc,
5381 0x3978635a, 0x2fd981c6, 0x5957142d, 0x89e710d7, 0xe23f9073, 0x5dfa0e79,
5382 0x9cd93327, 0xfa72fd8c, 0x72e2e35b, 0x2bbf9e03, 0x3b5af3c3, 0x49b58b97,
5383 0x97ae6f80, 0xffe8463d, 0x872bfc33, 0xac3197f7, 0xf1eefde7, 0x85f53d0d,
5384 0xfd5f10c3, 0x3ce355e6, 0xdf112e7e, 0x2c1e3202, 0xe7eefb43, 0xabf408d2,
5385 0x6c703f17, 0xbbd9ca0a, 0xf0562d9e, 0xf8bfc5d5, 0xbb89e91d, 0xa2773ec4,
5386 0x037a8f9d, 0x7ca167e0, 0x45cb8732, 0x42e3c49f, 0x687c0a4f, 0xd7d5adfb,
5387 0xf1e2603e, 0x28e79079, 0xfcb76a40, 0xb5adfa9e, 0x67289d87, 0x8d345f6b,
5388 0x94fc7942, 0x2d92ff98, 0x0bbfc703, 0x94c4b3f4, 0x5a5ea0a8, 0x46699813,
5389 0x818b4d78, 0x52f79ee0, 0x3f1e90b3, 0x81c9786e, 0x5c41f274, 0x4ff50f28,
5390 0xf538fad7, 0xe1402e20, 0x1b8fb971, 0xfc620ef2, 0xb612a966, 0xe97ea01b,
5391 0x94649cc6, 0x212befd3, 0xdfbfd633, 0xec2236ea, 0x08f19451, 0x04e1e47b,
5392 0xab220c7f, 0xca0fd055, 0xbe06b599, 0x399e6b9f, 0xf186ce66, 0xfdc3937e,
5393 0xfe7e4f9b, 0xf38c7cbb, 0xf38566d4, 0x7ec07f51, 0x3c400fe7, 0xfd206d3f,
5394 0xc919f6bb, 0x67ac3713, 0x7ee2d7bf, 0x16ad7f03, 0x85f6bcfb, 0xba45ee97,
5395 0x5dfb8b5f, 0x805e9bd2, 0xf3d38f6e, 0x614c0ee7, 0x48e3fdfc, 0x02be9a17,
5396 0x8c94c1b8, 0x9f0e3a71, 0x02fce1ce, 0xf3f82bcf, 0x4bc91140, 0x67682390,
5397 0x5f7bd346, 0xd8b1fbfb, 0x2c5b25bf, 0x163f5724, 0xc0f9dbfb, 0xbfdc0e8b,
5398 0xec7e7e4f, 0xd4a39e04, 0xd8da073e, 0x05ee8315, 0xfae1d63e, 0xb27f341d,
5399 0x7ae1d623, 0xefeb3d1d, 0x6fc173a6, 0x9f5f18eb, 0xb275deb6, 0x2f56bf58,
5400 0xd62cbfde, 0x7c0986b9, 0xf38830bd, 0xe427e097, 0xb4c7b457, 0xf992f9f5,
5401 0x267d1afb, 0xffb972e7, 0x99ff2137, 0xfc40ead2, 0x9ca2fee0, 0x98f1fa01,
5402 0x01b90947, 0x16793e4d, 0x5fb11fe6, 0x73b3fcda, 0xae403cf9, 0x7b929279,
5403 0xc8d3b1f6, 0xb73ac656, 0x78e5c84c, 0x9698db3c, 0xfbf806d5, 0x892bfc18,
5404 0x23957a71, 0x46e8d3c6, 0x67fcaf1b, 0xdd70d355, 0xfb087fd0, 0x3f7dc6d7,
5405 0x3f632090, 0x1fce33ef, 0xbe35fcda, 0x345faf2c, 0xed81d8ad, 0x14e7b13e,
5406 0xdd39bae1, 0x542ae766, 0x802ed07a, 0x066d3df7, 0x159f4f8a, 0xc6d9fcfe,
5407 0x8a4b1c97, 0x25dde87a, 0xd93f8de6, 0x1a9e7bd9, 0x33d045fd, 0xfb7cb3cd,
5408 0x6b0869fc, 0x4ba68df3, 0x7d1a6f0d, 0x64a9cdb2, 0xe9d344af, 0x66b3ccba,
5409 0xb9fa2f1c, 0x807cb766, 0xffe415f1, 0xf2e3c654, 0x6e78ec0d, 0x9f863e84,
5410 0xd1ea8d8d, 0xd79c9a0f, 0x14baf3f4, 0x2fc225cf, 0x43703a0b, 0x5366e736,
5411 0xc72977bf, 0xfde039b7, 0x74c3e731, 0x87d9abfe, 0x92117f37, 0xf48e3112,
5412 0x5224bb82, 0x7cb9adcf, 0x96b6e89c, 0xbfa1b785, 0xdf81f8b3, 0xf48d1ccd,
5413 0xce8994f9, 0x4e37165b, 0xbddda336, 0xa39df0ea, 0x35cfdf70, 0xa9763d71,
5414 0x6893e461, 0x7a6b9f37, 0x116779d8, 0x653e57be, 0xbc5f3c2c, 0xf5f698ab,
5415 0x4cf0b883, 0x91eebb84, 0x6f7841d8, 0x9b91e1dc, 0xce3c0217, 0xae12537e,
5416 0x5243fdef, 0x3a08d8c5, 0xcd94ca58, 0x934ed10b, 0x8be41513, 0xab3c85f7,
5417 0x5a7df137, 0x517fe82e, 0x45f3e72e, 0xebcb7f62, 0x7cf1f3eb, 0xc800ebbc,
5418 0x8d63c051, 0xc21ad5d9, 0x234d5f71, 0xd81d7fbb, 0x74c9e908, 0xd2764d4e,
5419 0x66b3334a, 0x6b73d094, 0x693f3c06, 0xeb83df0a, 0xbd8f7939, 0x58e20b78,
5420 0x096a3eba, 0x5f896fb7, 0xf1a5aec0, 0x3168edbb, 0x2e82658f, 0xded3fba3,
5421 0x1ebb40ef, 0xff989ee5, 0xe6a786a5, 0x74babea1, 0xd7192f24, 0x71abe1ff,
5422 0x7cdf684d, 0x4c72e268, 0xaeec1feb, 0x11f691f3, 0x183a5bd8, 0x0c1d2aec,
5423 0x6f5e75f4, 0xbc256d8f, 0xb7ab9bdc, 0xad3a34ab, 0x18979f59, 0xcbd01799,
5424 0x0a43fefe, 0x9cf7ff9d, 0x644e8cbf, 0x7742e431, 0x880fd5dc, 0x3c6c67ca,
5425 0xcf18fada, 0xf9f2f84d, 0x2ddfda30, 0xeb02c516, 0x8e748f3c, 0x4a2f4be7,
5426 0x72b7eedc, 0xe2ff3fba, 0x77fa2088, 0xe1c0ffcb, 0x2086ade5, 0xdf1edd1e,
5427 0xf6c25db5, 0x4beec0cb, 0xb3d84433, 0x03cd77bb, 0x545767f2, 0x680cb6df,
5428 0xcf08e57f, 0x5b6a8077, 0x227b1d94, 0x1db7d5c3, 0x5fb6cffb, 0x61c0b8b5,
5429 0x532adf0d, 0x9e1adf11, 0x75e67f35, 0x92b287a0, 0xea7dbc1e, 0xebf6495f,
5430 0xca8fbf65, 0x1f670ccf, 0x6c74871c, 0x5f91544f, 0xb0f6dd7e, 0xfbf70034,
5431 0xe8ebe285, 0x25b58e97, 0x9fb7c82a, 0xb9d137fa, 0x1d7f65e6, 0x6b7eda95,
5432 0x5f9bb171, 0x3ef7a768, 0xcaf11b6d, 0x35ef7838, 0xd790a25b, 0x35f731c9,
5433 0xeee3bf3a, 0xf0d3a3f5, 0x8faeb6b9, 0xabfbe3ee, 0x23a3fbcd, 0x5d703a77,
5434 0x7bf58fed, 0x6bee0c65, 0xf682a242, 0xdf910ad9, 0x971f6171, 0x89ad170f,
5435 0xfd80ce4f, 0x8e7fb8bd, 0x5c9c8193, 0x1e773ed6, 0xaafe5f3e, 0x5cfb4141,
5436 0x81cab57d, 0xcb3f8df1, 0x4b050e9d, 0xf3842f78, 0xca128391, 0x6c95b1a3,
5437 0x1b1fb60e, 0xfa0b9992, 0xd3833319, 0x72cb98c9, 0x3e780f10, 0xb714e786,
5438 0x714f1eb8, 0xc3f5f80b, 0xbf658dfc, 0x0d0ef1e2, 0x35df9aef, 0x04dbac4e,
5439 0x2e7447ec, 0xf197979e, 0x7fee1fe7, 0x77f6167e, 0xc14990e9, 0xc87a7f79,
5440 0x06affd44, 0xe308c97f, 0xfdc23c5d, 0xdce38410, 0xdfdcc7c8, 0xfdcadd58,
5441 0x26f5da8d, 0x37b1398f, 0xb447963d, 0x9e0ebf43, 0x55dc70b9, 0x3a34de82,
5442 0xebe1ed5d, 0x0d7a0d5b, 0xb74d1bd7, 0x1b75ac49, 0xe8ebe9e2, 0xedd29bf7,
5443 0x135e90df, 0xe87cb758, 0xe8bed7a6, 0xf913e044, 0xa355e91d, 0xf8fbd587,
5444 0x6b727a39, 0x3ba444f1, 0x79343e8d, 0x0ac49812, 0x9bd66f50, 0xdde60159,
5445 0x2af18c04, 0x9b2a81ca, 0x7f7284cb, 0x05674a4e, 0x1e4965a2, 0xb952a797,
5446 0xfd4463d1, 0x79216f53, 0x526f2d11, 0xdffcb8f2, 0xed074483, 0x2a14f28b,
5447 0xfc8eac4d, 0x8584ad07, 0x5cfd440c, 0x9ffc9095, 0x5372682e, 0x65b383de,
5448 0xb8d57f98, 0x54727be4, 0xede506c6, 0xe488f0e6, 0x97a82691, 0x5d9a1feb,
5449 0x9e457001, 0x445e6067, 0xa70e97bf, 0xc0f5c40d, 0x8c1e5773, 0x97c53dbb,
5450 0xb33ae583, 0x67f7e48d, 0x9b61ae86, 0xcfed3ddc, 0xff7f6abc, 0xb81eaed7,
5451 0xd4b2c4d3, 0xcd198422, 0xcaef2b5b, 0xe3e60cf3, 0x612f9fe8, 0xe2f291ac,
5452 0x5dfbff02, 0xe7e043b4, 0xdefec2b5, 0x8969e82a, 0xfdc216d5, 0xcba64d64,
5453 0xa80576dd, 0xca26a67e, 0x04b30748, 0x872adc1d, 0x42fdf1da, 0xb05ca0d6,
5454 0xffb3e992, 0x3a377eab, 0x05d995a7, 0x87a03fad, 0x3eb04ccf, 0x900367a0,
5455 0x196026d7, 0x06b12003, 0x95e197e4, 0xd85ffdff, 0x75807d6f, 0x6b9e11c6,
5456 0x067b9414, 0x057e33e6, 0x63826d65, 0x3c33c618, 0x3643d92f, 0x3f0dc7d8,
5457 0x5fba204f, 0x5217ec25, 0xa65f98c6, 0x74b0f5f0, 0x8f7fde7e, 0xfd0fb7a0,
5458 0x5817372c, 0xf47613fb, 0xb1e61953, 0x1b37ce2a, 0x78c6bdf1, 0x0b836b2a,
5459 0x81deb4f9, 0xbf27c576, 0x09145490, 0xc8dd846b, 0x7e0aa50e, 0xa0134297,
5460 0x785dc3be, 0x8d4bf510, 0x6ecb97a0, 0x606f7e46, 0xfaf2858b, 0x5963f5d8,
5461 0x995c03f7, 0xfe8a8b7d, 0xb767e5e4, 0x7d832ee7, 0x0ed8c0b2, 0xe854e758,
5462 0x6aa60cb3, 0x73a25802, 0x03f520de, 0x3c0701f5, 0x387ee6df, 0xf319d38b,
5463 0xfdb47ae2, 0x6bdef0d1, 0xb468603f, 0x66568d2f, 0x90b1ff42, 0xff9057ed,
5464 0x8c997db4, 0xfff03dce, 0x9c791786, 0x75818363, 0xf9af18c3, 0x8d780ad0,
5465 0x4f6a5f21, 0x267641be, 0x27405bb0, 0x19dff657, 0x1d95ff5b, 0xffd76330,
5466 0x98d83d6c, 0x315ff427, 0x037b262b, 0xadfd0697, 0x4b266d10, 0xd7192e35,
5467 0x91556a93, 0x9e3c361e, 0x1d867a43, 0xa0f44dd9, 0xfbfb63b5, 0x736c9d11,
5468 0x55ff844b, 0xcc4cb06d, 0x4feb69d3, 0xda338b79, 0x5c74a992, 0x97e7a74b,
5469 0x94ab7c9e, 0x3fbe1bcb, 0x369a7f33, 0x7e83f289, 0x6d4a883a, 0xbd041b1e,
5470 0xe2be7869, 0xc93e7815, 0xbb06d5f5, 0x397dfc99, 0x79489850, 0x0b121d8c,
5471 0xe4f73c02, 0x57e2131c, 0x6d74e78a, 0x57323749, 0xc459bc0c, 0xe2b9c47e,
5472 0xded22b99, 0x68c2780f, 0xf517cfd7, 0x51c90509, 0xe6df7cf5, 0xb7cfe589,
5473 0xf3819cad, 0x75fdabb6, 0x4c776ce3, 0x92ba20e9, 0x5f38cb2e, 0xeb0304cb,
5474 0x352be787, 0x3b987dfa, 0xc69b0f57, 0xd5f24e7f, 0xbf7a3e34, 0x4dfd0999,
5475 0xfcff478b, 0x17a13cb5, 0xe461590a, 0x9fc2f63e, 0x0d7c4acd, 0x78ef79da,
5476 0x9875e780, 0xedc5d058, 0xafc7b435, 0xb7442c78, 0xde04e3db, 0x21e9a50c,
5477 0xa6589f68, 0x47925fc7, 0x957eaf8f, 0x7aa4fc7a, 0xab4878f5, 0x67d5d6ce,
5478 0xeaeb06f8, 0xd12cac07, 0xc6eb03c1, 0xb4dfdaea, 0x760e9269, 0xdae9a607,
5479 0xd6cd34e7, 0x0b2d79c1, 0xed07ed75, 0x2faba25b, 0xd5d6ae0c, 0x41b2390f,
5480 0xfd6d0f07, 0xe1fb5d17, 0xf5755b6d, 0xba1da1c5, 0x0f1d11fa, 0xe191e0e9,
5481 0x47ed7547, 0x57507bbf, 0x69f3a63f, 0x8bb8fd5d, 0x9be0e9cf, 0xb5d65ebb,
5482 0xa8ed709f, 0xdec89e0e, 0xb72fb5d2, 0x4f074efe, 0xd743fe56, 0x0ff496fe,
5483 0x5d53f574, 0xa7eaeb1f, 0xc1d55c17, 0x097d9877, 0xea97c8f9, 0xcdef74df,
5484 0x8e1fae62, 0x9f9e3a07, 0x00435462, 0xfc85f3db, 0x8c977410, 0xdaed13fa,
5485 0x7485965c, 0x1f1a593a, 0x336bba22, 0x4457e8a8, 0x63f927eb, 0x65e307af,
5486 0x8a8325ec, 0xb044ac71, 0xf188e4eb, 0x70563c92, 0x7ee07b00, 0x4e0e8a95,
5487 0xdaeba6f5, 0x74bb55a7, 0x02be19f5, 0x9580fd5d, 0x581e0eaa, 0x7f6ba657,
5488 0x0e8f26d3, 0x752a0776, 0xbc9a73ed, 0xa5af383a, 0xd07ed75a, 0xbeae9f3e,
5489 0x5752b830, 0x9d48e43f, 0xbada1e0e, 0x787ed749, 0x5f57405b, 0xd5d26a1c,
5490 0xd168e88f, 0xfbc323c1, 0xbf47ed74, 0x8fd5d41b, 0xaba23ce9, 0x55b1771f,
5491 0xd5dcdf07, 0xe13f6ba6, 0x4f07485a, 0xed752764, 0x7467adcb, 0x3de564f0,
5492 0xd25bfb5d, 0xa7eaeacf, 0xeae92eba, 0x7a647b35, 0xe7fae7c1, 0xa9993ec2,
5493 0xfdee97fe, 0x430f24c0, 0x673c08fa, 0xa05deb50, 0xb9b3f2ff, 0x2d13073e,
5494 0xc67b424e, 0xc945f94b, 0x7207a098, 0x2060312b, 0x5b9542ba, 0x149ef143,
5495 0x52a453d2, 0x0347985c, 0xde81de7a, 0xf68ddb93, 0x9d8f426d, 0x88d5f995,
5496 0x7d676e6f, 0x30387d1f, 0x944db65d, 0x0de563aa, 0xc79f3f7e, 0xfbe50e39,
5497 0xa2a7e436, 0x14ecf11f, 0xb157b3b4, 0xe79c36c0, 0xb128a964, 0x71a8e313,
5498 0x568538fa, 0x645eb54e, 0x77dd8472, 0xb325ae32, 0xfcfe06e4, 0x2665eb54,
5499 0x57e8888f, 0xb00c2fc4, 0xfd110dfe, 0x807e083f, 0x8b7f3e0c, 0x6c0af81f,
5500 0x0afc87a4, 0xe9fdbbc1, 0xbbf1ef04, 0x2fe7dca8, 0xbf51f2a0, 0xfdfbf54a,
5501 0xe13f0465, 0xf41c10f7, 0xd0795257, 0x87e7a5ef, 0x3f04d5fc, 0x96317e09,
5502 0xc64fc047, 0x77f069f2, 0xf019feb1, 0x85fe117f, 0xab65403f, 0x3f9e89bf,
5503 0xf8216fe7, 0x823eff05, 0x520fe97f, 0x423fe6d9, 0x56fecbe5, 0xdfc57faa,
5504 0xfe6bf046, 0x7f21c110, 0xfd47c107, 0xfb8f8261, 0x84f825df, 0x0eca93bf,
5505 0xdf2a45ff, 0xfd5177f4, 0x8235ff29, 0x6f53f67b, 0xf3e346ff, 0x65571123,
5506 0x215c4ec2, 0x70a587e8, 0x273970fb, 0xd042b605, 0xa81269ad, 0xfa3fb457,
5507 0x3cc41fe7, 0x574891d6, 0xa7574405, 0x1efd8dbe, 0x25697fed, 0x9bf719d0,
5508 0x3c781bd7, 0x22efd346, 0xefd3405f, 0x7f70f735, 0xbbd81175, 0x43ffff18,
5509 0xaf3fb71c, 0xd00a99d4, 0xc431ab8e, 0x5d2f68ab, 0xd933fba9, 0xafcf0c47,
5510 0x78ee4581, 0x476072c5, 0x0356df84, 0xfde11bef, 0x18b45999, 0x4c3ac356,
5511 0x332a2e74, 0x357c048f, 0x37efa076, 0x0f561fa8, 0x7fc80634, 0xd1f305b6,
5512 0xa07dbb6f, 0x7ef48c2f, 0x09d96ea5, 0xd2a28fc2, 0x4b4ce0b9, 0xc63e7528,
5513 0x144a4e49, 0x1f0bebdf, 0x785e44eb, 0x5daff59f, 0xbc3b44ca, 0x0f92eff2,
5514 0xc9b4e7f7, 0x83718d5e, 0x1fb9f20f, 0x51be41fa, 0xe81e5e57, 0xfcf3873b,
5515 0x76eebd8b, 0x2ff0a023, 0xe4ff59df, 0xbf1eeedd, 0x3d7456f9, 0x62ae5ec1,
5516 0x29e5132e, 0x6e1bcf32, 0xe636eae8, 0x0b3e7823, 0xa67b7950, 0xd75c63ef,
5517 0xd8241602, 0x1592d637, 0xf3d15d6b, 0x03908bfa, 0xea37c97f, 0xbe59feca,
5518 0xf2f3e4ff, 0x8f4ebcd0, 0xd71f25b9, 0x616bcda5, 0x3fe68b96, 0x813d758b,
5519 0xabcbfbf3, 0xe4305f9f, 0xff8fa6f4, 0x61b0ba01, 0x31da0598, 0xc7a8df3c,
5520 0xafa81cc4, 0xf940cfbf, 0xd45d1ad9, 0xdf104060, 0xbca06cdb, 0x013a1efd,
5521 0x2bbf40fa, 0xf1ee8ba5, 0x0f249d01, 0x23193a42, 0x4f60cc05, 0xf306369e,
5522 0xbc5e740d, 0x84718ccc, 0x1f402915, 0xc1d37dd9, 0x409f715a, 0x95f40e7b,
5523 0xfa7dfd89, 0x8805d1ab, 0x8daf75af, 0xeabe2171, 0xe80fb08d, 0xa929be27,
5524 0x8b851f3c, 0x50dc697e, 0x5932578a, 0x34ce3155, 0xde5b12d3, 0xe9c41f8e,
5525 0xa9ba74e7, 0xe9fd4832, 0x074a55cf, 0x1d2b7df1, 0xc373f7c4, 0x48d70ffa,
5526 0x47d3ef30, 0x947dd12f, 0xf4dff35e, 0xc46e6166, 0x9db5d7bc, 0x2189e29d,
5527 0xfe8be7bf, 0xcc91ba34, 0x5b01df76, 0xe9babce4, 0xfbae1c78, 0xc740492f,
5528 0x17c74439, 0x9670fcf0, 0x1f3895c5, 0x09404eca, 0x1fbee9da, 0x2dffe42b,
5529 0x4b952a61, 0x15ca9799, 0xb748edb0, 0x332ec0de, 0x6b357be2, 0xcb6be7a5,
5530 0x1d2274ee, 0xc8fa372f, 0x99835e2f, 0xcb9e78b7, 0x01d22aba, 0x6d35b76f,
5531 0xd01d2379, 0xd765a737, 0xcecf8c64, 0x037e2e0e, 0x8643aacb, 0x0a87980b,
5532 0xe70b317c, 0x6ba869d5, 0x2fe30fec, 0xe362667c, 0x4b3e7800, 0xdec1fbe2,
5533 0xc9a1fbe2, 0x0375e88d, 0x941bcc1f, 0xd0f2eb8a, 0xa54724ba, 0xb66a0f8e,
5534 0xa5218f32, 0x9bbe1f27, 0xfaeeca2f, 0x5f9400d3, 0x07c51772, 0x4966bdd6,
5535 0xcd5e7dc6, 0xf0603db8, 0xcd0ff168, 0xe744600e, 0x1578b177, 0xe8247ddb,
5536 0x8c81a3fa, 0x0323fae8, 0x3d258438, 0xf2cb29f6, 0xf4e497a5, 0xc675ebe8,
5537 0x9e218667, 0xe2d79f40, 0xd07f577c, 0x8dd8adba, 0x85983f72, 0x69e989f6,
5538 0xd6ef5a8b, 0x55f615e9, 0xeb5c4f42, 0x3b8f1341, 0x50cbcf45, 0xd0bfe276,
5539 0x5998b11e, 0x8039cf00, 0xe428d9af, 0xe266fee7, 0x2d447aab, 0x7926c7c6,
5540 0x557cfc5d, 0x3169ffdf, 0xb92f8edf, 0xf5801c3f, 0xf7a49c60, 0x594f5c38,
5541 0x21c67be2, 0x3464e1b9, 0x9c41cece, 0x98f1b57f, 0xed1333ad, 0x7de3fbf7,
5542 0xd5fdc03f, 0x3f9a3de2, 0x30fee1d9, 0x8d99ee97, 0xf74354bd, 0xe858c637,
5543 0x22addf7e, 0x196b760e, 0xaadd838f, 0x47c6bdc5, 0xe2a2bdc5, 0xec7c6c2f,
5544 0x97269838, 0xefc95319, 0xd07f642d, 0x17f14fd6, 0xd2f60e4d, 0x3090b0ab,
5545 0x145da5c5, 0xcb8ee8af, 0x1e799b14, 0xad306b8d, 0xe4e42cc7, 0x4f972f4e,
5546 0xd569fbda, 0xfce8c2e0, 0xd5cb2b08, 0x0e8a11f9, 0xae97581e, 0x26d37f6b,
5547 0x1ddeae97, 0xe7d5d028, 0x383aa934, 0xd74ca5af, 0x8f3ed07e, 0x560c2e0e,
5548 0x390fdaea, 0x43c1d5e2, 0xed75ab5b, 0x74f9b787, 0x95a1c5f5, 0x1d11faba,
5549 0x64783a75, 0xfdae9378, 0xba0377e8, 0x4d9d31fa, 0x1771faba, 0xcdf0745b,
5550 0xed74fb5d, 0xea0b5c27, 0xa7b227ea, 0xd6e5f574, 0x64f07567, 0xf6ba57e5,
5551 0x74fd0b8f, 0xeebb7a4b, 0x49d754f9, 0x0bd37bdd, 0xc7e0e8ce, 0x0f919f71,
5552 0x0f899816, 0xe9efaa66, 0x10f267de, 0xe39b938a, 0x1dfdb3f8, 0x3ca3146f,
5553 0x170c6fdc, 0x6e3e9f23, 0xf96374ec, 0xb5b5c184, 0xce49d01f, 0xd61489f8,
5554 0xbc58abce, 0x3341cb15, 0x5d5318b6, 0x0f731fb0, 0x393d456c, 0xe8dda6a4,
5555 0xd2e87804, 0x889d5bb3, 0x290635f7, 0xd1bdf10d, 0x88e58f5d, 0x74a513cd,
5556 0xb0d91fa8, 0xe8e51eb8, 0x8b33e6e8, 0x007496d1, 0xfe3187cf, 0x3e887b25,
5557 0x69186637, 0xc6471bde, 0xcedcde53, 0x9d1936b1, 0x9c3b9d96, 0xdc0f180d,
5558 0x09a4a3b9, 0xbf606dcb, 0x358ccd07, 0xe58efd81, 0x83dfb00e, 0x3c6c8be0,
5559 0xe424e7f3, 0x53a6e547, 0xbf2e78e9, 0xaa47d27d, 0x4a15c551, 0xbf438f73,
5560 0x22f1a9cd, 0x3b9a515f, 0x4efb7411, 0xdf8049e4, 0x1730923f, 0xe1a370f3,
5561 0xad788717, 0x72f7c805, 0xbaed1b8b, 0xac06fd5e, 0xfe017efa, 0x927afd66,
5562 0x1e785fb1, 0xad216f33, 0xf7e1eb80, 0xde5a8c0b, 0x715be53a, 0xb04a1c53,
5563 0x9e41123f, 0xf0e98f35, 0xcabc00ad, 0xee819d4a, 0x26fb8b09, 0xf8a6aa18,
5564 0x26aff5ee, 0x2e9c03c4, 0xe451dbde, 0xfe802bcb, 0x9ca0606c, 0xf497a08b,
5565 0xd04700a5, 0xefc05ec7, 0xf99edcb9, 0x0630ee98, 0xa60b9064, 0x1555789f,
5566 0x516c79c6, 0x7b97393c, 0x223b7acd, 0xdc8de44f, 0xf7146057, 0x68a8e65f,
5567 0xc057dcff, 0xfe23dcf5, 0xe7cff38b, 0xf35dff62, 0x329e03cf, 0x0f988696,
5568 0xf54d99e4, 0x611a98aa, 0xb17567aa, 0xf19bc8fc, 0x6fbc0612, 0xee92763a,
5569 0x702aafaf, 0xd4325e11, 0xff775a16, 0x646fd0a5, 0x33ae4d9c, 0xda403e60,
5570 0xce033ae6, 0xaaf14d2f, 0xacc78e78, 0xbcfddd4e, 0x997f4db4, 0xa7e41e7f,
5571 0xb155efc9, 0x46ba699d, 0x222b218f, 0x925aaafb, 0x47cc62c8, 0xfc9d6d2b,
5572 0x7aafa8fc, 0x759bc947, 0x625a3794, 0xd111e173, 0xeab6c5e3, 0x7bf63103,
5573 0x66efd895, 0x9b7c7e87, 0xe4203e76, 0x718555f4, 0xf7f8213d, 0x6b0e24ee,
5574 0x5c5ddcfd, 0xf9c37692, 0xce7463ee, 0x30cdc1a9, 0xf9a9e20e, 0xd715bb7a,
5575 0x0b798cdf, 0xe9182fa4, 0x547e2789, 0xa1876070, 0xa2f63ef7, 0xc4fca047,
5576 0xce8fa412, 0x83f03d60, 0xa2acd8bd, 0xdefb645d, 0xdeea0372, 0x89475674,
5577 0x1591b637, 0x1bb0f21d, 0x4f5aafcc, 0x3d3e6987, 0x97d9329d, 0x62faf941,
5578 0x1c3d351f, 0xafa66fbd, 0xc872d272, 0xd979e2ee, 0x67fe4e1b, 0xef022f9c,
5579 0x557c123f, 0xe4245ac6, 0x95acb193, 0x4c2cf1ca, 0x175877e5, 0xc8a61e95,
5580 0x2a624e58, 0x4bcc1595, 0x475614e5, 0xa16b2565, 0xa56b1a72, 0x530b0672,
5581 0x950afe09, 0x5f90a65e, 0x36f41b35, 0x97997396, 0x8eac79ca, 0x1d229fca,
5582 0x59ab3e03, 0x590bc10b, 0xc06d952b, 0xfaa5787f, 0x586f9065, 0x0df202be,
5583 0xe9fcd7cb, 0x2efc8654, 0xbf47cae6, 0xe3ca80bf, 0x13ca957e, 0x3b2a32fe,
5584 0xf76a1efc, 0xca92bfa6, 0x952f7e53, 0x54d5fda7, 0x6a3efd86, 0x257fb6f7,
5585 0xebf8ef95, 0xff37fca8, 0xf5df2a26, 0x77fca807, 0x7995137f, 0x39764666,
5586 0xcf15082b, 0x7e67fc06, 0x60b8f660, 0x3c0aaf1f, 0x5318f31e, 0xff70530b,
5587 0x4df18664, 0x2231c55b, 0x48cb9b0a, 0x5c9addf7, 0x289dd947, 0x3b734f07,
5588 0x27669ecd, 0x72d6d03b, 0x613e619c, 0x4a53a19b, 0x793cbd80, 0xd6b98ee4,
5589 0xaf93d042, 0x150486b0, 0xadbba5e1, 0x309e07a0, 0x027eeb85, 0x960bc7f5,
5590 0xce82b5cc, 0xfb7f6b1a, 0x4c39a7e3, 0xb38e63f5, 0xdfe0057a, 0x1bb1591e,
5591 0x3ce130af, 0x57bede50, 0xe62e7ab0, 0xf2155feb, 0x00c37c02, 0xb7ad2de5,
5592 0xb16f3105, 0x3168e5b8, 0x7531b62a, 0x37d412b6, 0x1e28ed11, 0xe8bb57d0,
5593 0xc7bded7a, 0xe2129d6a, 0x64cff9a1, 0x9cccb37e, 0x9dc63150, 0x7e35fb22,
5594 0x7499f1b3, 0xdb23f183, 0xdfd06e19, 0x9fcf228e, 0xfffccf50, 0xfa68f3a6,
5595 0xec757d36, 0x062efa59, 0x7e438aeb, 0xe5c4983e, 0xa5d8174d, 0x0b34dfe8,
5596 0x364b79b8, 0xb507a9d9, 0xcbefb37c, 0x5e307f54, 0xf081d2bd, 0x378a5c96,
5597 0xe2792734, 0x637db10b, 0xcc9dc936, 0x63794604, 0x8a13d53b, 0xe3ef822b,
5598 0xb2fcb90b, 0x7285fcdd, 0xefe5ca27, 0xae8f0ccb, 0x3bfefa6f, 0xde00b71d,
5599 0x05468d5c, 0xe6f12df7, 0x7e512a77, 0xa3cb3704, 0x18e32124, 0x12792fd5,
5600 0xaa9da6fd, 0xf61f3e39, 0x0ea200f5, 0x1b26aced, 0xfd9959d9, 0xc377c542,
5601 0xcf328d78, 0x6f968aff, 0x9cb90bb3, 0xc34bda37, 0xc0b76e74, 0x4478c2ea,
5602 0xd9b0f25f, 0xf3c2caef, 0x6fbc6764, 0x287e0331, 0x4a676a7c, 0xa7732823,
5603 0xa313db83, 0xf6483a9f, 0x27c8b344, 0xd2314c6d, 0x256c49f7, 0x445203ce,
5604 0xc87336bf, 0x36f8e785, 0xb163e0a3, 0x3207e69e, 0xf7b75f29, 0xefba5d3c,
5605 0x9855d915, 0x6e1c8447, 0xee817116, 0x3ff446f1, 0xcdc44520, 0x4a90966c,
5606 0x4bfa69e3, 0x3fc76f1b, 0x914ede36, 0x678da927, 0x9f5fa51f, 0xf5a61cdd,
5607 0xa1fd85d9, 0xd713b78d, 0xe30f2317, 0xf5c3c76b, 0x5a378e45, 0x25bb3ebf,
5608 0x4bb3eb4c, 0x1ee95edc, 0xf1ec476f, 0x4f671afa, 0x569cfe54, 0x72e42fce,
5609 0x7632cc15, 0xd33ff60e, 0x09f9e9c2, 0xd9c5d313, 0x7e7a0937, 0xa69788b2,
5610 0x992e5c09, 0xcfba669c, 0x7179d133, 0x6db5d217, 0x9dce91b7, 0xc827296c,
5611 0x4ed3927e, 0x40fc8931, 0x9fcf8ad6, 0x02f7f030, 0x7998e6a9, 0xe1fc7b2b,
5612 0x7111b9f9, 0xceb534e3, 0x134ff980, 0xe30c1d9d, 0x3314b6ec, 0x6296dfad,
5613 0xfca1c60d, 0xcd809955, 0xdb8004c1, 0x0b1b7c8b, 0x954e3d61, 0xc5338bf3,
5614 0x92f3007c, 0xdfa1aad2, 0x84ff7d08, 0x772663a0, 0xee22abba, 0xc45b3cd7,
5615 0xaf8d49ed, 0x7237e7a3, 0x41ff5f30, 0x4f31e7f0, 0x8f0c6ba7, 0xdc3e9c93,
5616 0x5987fc9f, 0xd07bc60f, 0xc0fd3e8f, 0x77820ae0, 0xf5f3a58c, 0x4ec787d3,
5617 0xd6627f41, 0x8246698e, 0xe303ac0d, 0x2c76b31f, 0xccf3e234, 0xdffb461c,
5618 0xf24cd675, 0xd58ed675, 0x4cbffda2, 0xc665f6c1, 0x6e30cfc0, 0x91ef7650,
5619 0x8c8b8c04, 0x00373fb5, 0xcec6d3cb, 0xa07df88d, 0x1bf6155b, 0x5bbcd734,
5620 0xb228ed92, 0x36c81eab, 0x44f59fa1, 0x99bf3f21, 0x9e263cc3, 0xbf25e187,
5621 0xf091fc7e, 0xfbb2bc31, 0x72aed69d, 0xb4f6c63c, 0x9cb1c729, 0xdaf15214,
5622 0xf0e8ab32, 0x4a72c71e, 0xcd02aeb8, 0x5b77cad9, 0x3159638e, 0xe204f7dc,
5623 0x46f7f0f7, 0xc614fc95, 0x6e6fbac9, 0xd93bda3c, 0x0f27435b, 0x44d65c50,
5624 0x94f6c2f7, 0x18249b79, 0x6bcb8f6f, 0x27b43d45, 0xf248db25, 0x256ea935,
5625 0x3c6073ad, 0x51ee75c3, 0x45c9717c, 0xbec97724, 0x11ec137f, 0xe7eeffdc,
5626 0x33f9fcf1, 0x151afe82, 0xf88935af, 0x027ca140, 0x9acbb09b, 0x151d2799,
5627 0x04f76ca1, 0xc7b72e31, 0xc078e5c3, 0x6c52fdc6, 0x58ec0dbe, 0xec6992ba,
5628 0x95594fd9, 0x60c779f5, 0xb2bf60de, 0x10b28768, 0xa6bc5fed, 0x0fe8308a,
5629 0xc61d5dfe, 0xe6dda1f5, 0x36be38a4, 0xfa14b97f, 0x9c33a08b, 0xcf5b6cff,
5630 0x67b8da7b, 0x237e7ac4, 0x1f1ef4e4, 0xef9b4fef, 0x463728db, 0x465dbcd2,
5631 0xe6248f9c, 0x4630eb03, 0x1da227cc, 0xde7bafad, 0xf7e74d4c, 0xdf8c3d4d,
5632 0x392e6543, 0x8b0efd62, 0x1e912ad7, 0xbf482a34, 0xf948d576, 0x2fdb76fc,
5633 0x7a3f0f29, 0x790a171d, 0x7287eabc, 0x365fa188, 0xe430f54d, 0x1e2a1fcb,
5634 0x0164abb2, 0x0edc29cb, 0x624fc793, 0xcaf588a6, 0xdda89329, 0xf18f6834,
5635 0x096569c5, 0x74ebd22a, 0x70a0dad6, 0x2e78e03f, 0x318f2fcc, 0x2cb75e5d,
5636 0x9faac7e0, 0xf0bb72ab, 0x7b4b592a, 0xf745da01, 0x9dbca72c, 0x3ad30d86,
5637 0x05e9be70, 0xa193dbeb, 0xdf39fbde, 0xe3cc5677, 0xcb760372, 0x8cdfbcba,
5638 0x9e470095, 0x30f4fb5f, 0xbdae83d0, 0x43365746, 0x847682a5, 0xaefae131,
5639 0xecbf983c, 0x2c1bfae0, 0x4637365c, 0x5d17ba3c, 0xfb6bfc09, 0x4b9c1f63,
5640 0x1c6d94f8, 0xb54bacef, 0x89f7c6de, 0x84fe8de8, 0x6d81eaf1, 0xbebd1f31,
5641 0x7de20a42, 0x7b777b4a, 0x1afb8a96, 0x96d94fbd, 0xb8795dae, 0xca4675fe,
5642 0x2bc68f0f, 0xb9b711d8, 0xa4d6ce91, 0xa73c3d50, 0xe8cc6f7c, 0x8a47eee9,
5643 0xe3f7eb05, 0xca3fdaeb, 0xbe78bb82, 0x7a79fea9, 0x059bc94a, 0x500714a5,
5644 0xebeb36f9, 0xf7ea36f3, 0x283a6315, 0x1654d3c7, 0xfdbfb90c, 0x394b4e7e,
5645 0xbd6cc158, 0xbba355f7, 0xe5b17ecc, 0xce421bfc, 0xd3282667, 0xa7ce500a,
5646 0xf3fec91a, 0x23531aa6, 0x8329defd, 0xf09cfeb9, 0x37e48d92, 0xf74ac0fb,
5647 0x3850d4d6, 0x49c4ed01, 0x3ec9185f, 0xd1d4e37f, 0x3941a787, 0x9b4b37f9,
5648 0x0ce4ddb0, 0x86ed0e78, 0xc47d74be, 0x84b7649d, 0x5f5f910b, 0xed93a166,
5649 0x4c3b1fa8, 0x2da7bdf4, 0x26536c9f, 0x4cabfee1, 0x6d29dcc5, 0xdc6215dc,
5650 0x5e029b5f, 0x996ea792, 0x51e7e41d, 0xf6d2bfd7, 0x2865c789, 0xf036577f,
5651 0xbad57bb5, 0x9997d23a, 0xf142cc45, 0xd22af0ee, 0x19e31bc7, 0xa56ccbf2,
5652 0xcf08bbf5, 0x4664ecbe, 0xeab66fe8, 0xf3c62d32, 0xce676119, 0x44d35451,
5653 0x3f95552c, 0x73e7f2b7, 0x9f3d0f15, 0x73f87aab, 0x6feff71b, 0x3f610253,
5654 0x2d9b77f4, 0xddfd85d9, 0xfd797aa6, 0x9fd50b35, 0x172fff02, 0x171ac158,
5655 0xb7ae5050, 0xf3f2345c, 0xd13c5f2f, 0xa4ada37b, 0x2bf385c3, 0x36fdd235,
5656 0x3ee893b0, 0x4bc54ef2, 0x32f791f7, 0xf822065f, 0x64d9d2e5, 0x629cbf47,
5657 0x2f4b7ba4, 0xbf0c8c7b, 0x91a81403, 0x41423df9, 0x67572f47, 0x3654f9d2,
5658 0xebf71322, 0x43b256bb, 0x0fa0f11a, 0xe7f757db, 0xf6e642fa, 0x2951bec3,
5659 0x6161ded4, 0x074895c9, 0x3bca6587, 0x1e78e1ff, 0x650f943f, 0x735ed107,
5660 0x5df9e8d6, 0xe9c49d2e, 0xf20a6541, 0x25550cc1, 0xcddfafba, 0xf88ba354,
5661 0x7d87de9e, 0x2cee75a5, 0x1fa2bb7d, 0x55546bc2, 0x93a18ce2, 0x6fa5f517,
5662 0x8cf83c73, 0xb3be4794, 0x9befbc54, 0xd7c70874, 0xe0b07cf8, 0xf4ae4d4f,
5663 0xf52a4396, 0xa49a4f63, 0x306800ee, 0xbffc800c, 0x51cf0ccf, 0x74cb242e,
5664 0xa9706adf, 0xf586521c, 0xe8867df0, 0x4fe0b077, 0xcf9e88f9, 0xe1e90ef2,
5665 0xeeff0447, 0x1fb92163, 0xe8c2dbf6, 0x8b406a5c, 0x3e781dbe, 0xd1639406,
5666 0x22abfc7c, 0xd48f1683, 0x9e17a1e1, 0xd9d7b17d, 0x5c40aeb3, 0xc8cbad3e,
5667 0x5de425d7, 0x3d2b6dae, 0xd56455cf, 0x2d62f385, 0x07fae36f, 0x40c1921c,
5668 0x352afd85, 0x7801cece, 0x71264046, 0x49859337, 0xbadd7c5e, 0x2b5c451b,
5669 0xebd19d7a, 0x44b065bb, 0xf1cccbeb, 0xca6ec979, 0x326ec990, 0x18c2006d,
5670 0xbdb0d78e, 0xa3716e3b, 0xd4fb3b3d, 0xe6439060, 0x182b567b, 0xe4233e0f,
5671 0x892be992, 0x56fdd7d3, 0xda5357a2, 0xfbc8828c, 0x4f86972a, 0xf318333a,
5672 0x7ababfbd, 0x4f8f1072, 0xe5a3fe11, 0x7f455fdc, 0xf9f53a63, 0xc62ee386,
5673 0xe9c7e547, 0x5c270df3, 0x1f951feb, 0x1f951397, 0x3f574437, 0x95111959,
5674 0x2a2e371f, 0x075cae3f, 0xae982f4f, 0x9d533f6b, 0x2d6f83a3, 0x7daeaefb,
5675 0x5d4ee795, 0xbbca9cfd, 0x79b7f574, 0xf3c1d6ef, 0xb5d7efab, 0xd7abe05f,
5676 0xe5777fd5, 0x20f5740f, 0x8bc6622f, 0xf74a3c31, 0x613dd386, 0x3016a0fa,
5677 0x3d8637bc, 0x57722920, 0xf471fea4, 0x1e4c5fe1, 0x71e3f7c2, 0x3b093fcd,
5678 0xc4591c78, 0x838b595f, 0x7c5ab1e2, 0x9a763436, 0xb722fd15, 0xbd434d45,
5679 0xf5cb7ece, 0x74380b06, 0xdf89cb71, 0x1b76a4ab, 0xfce9b292, 0xb3b051e3,
5680 0xef30f97d, 0xe927cf20, 0x1c6b001f, 0x500ddbe3, 0xd7febb42, 0x2237cccc,
5681 0x9e2c1e62, 0x3cb585c7, 0xe64f3107, 0x8bf3e049, 0x61f7cfe3, 0xfd1f313c,
5682 0x0f952b38, 0x4173b53a, 0xf6bf6195, 0xf2807332, 0xed834b11, 0x036f9866,
5683 0xc51447c8, 0xc74e5e12, 0xbd4db838, 0x7aaa3de1, 0xb3dd3a7f, 0x050d2db1,
5684 0x3aa5d04c, 0x3d1fd1e4, 0x7cdbef02, 0xe314e28c, 0x11ffec87, 0x433ce1c6,
5685 0xbb3f345c, 0xf7bcf1cc, 0x74b97ff6, 0x9265e518, 0x45f5ee93, 0xb1dda7d7,
5686 0x6e37f3f9, 0xd177bf50, 0x765bdef7, 0xdf6ff7a3, 0xa231b674, 0xcbf9afbe,
5687 0x13ccfeb6, 0x66590741, 0xad55fdfd, 0xfae10ef4, 0x3358dd7d, 0x49272fc5,
5688 0x604399be, 0xfec6cfbc, 0xe1db7bf5, 0xbe2b4fbd, 0x3bfd1db8, 0xe7c5ee78,
5689 0xfaf08ed0, 0x2c95e669, 0x04399e7c, 0xb3d47fec, 0xbe662c71, 0xadd05f9c,
5690 0x45d3569c, 0x99aa79fe, 0x6b4e43e2, 0xb0f3fce7, 0xf1516def, 0xcbf46682,
5691 0x447baf01, 0x8f8b447c, 0x59fa2ddf, 0xe9494a21, 0x660e73a4, 0x527dd00d,
5692 0xc5ec5ecd, 0x86328e0f, 0x936ca37e, 0xc5ca442f, 0xc53354f6, 0x4cc52407,
5693 0x3292e779, 0x2823be8a, 0xe78fa381, 0x985b7637, 0xd4f68cfc, 0x900f1451,
5694 0xce286342, 0xa885b360, 0x2fb6bf3f, 0x77dfdeaa, 0xbcd3cf5a, 0x759feefa,
5695 0xc7704f3f, 0x1e6a2718, 0x47d61e38, 0xccc0738f, 0xdcb9dfb8, 0xf1be331a,
5696 0x0d8990e2, 0x5f915243, 0x82dd773b, 0xd8bbfafc, 0x312b5972, 0x81183e8f,
5697 0x6486879f, 0xfe605d13, 0x5c62307c, 0x848f97cc, 0xdee80281, 0x6aa0c104,
5698 0x71425a06, 0xa13c7083, 0x6acd9a07, 0xa087d93a, 0xf71f70fe, 0x0a7e7e09,
5699 0x51fc8d68, 0x03ef87e1, 0x51f2c63e, 0xda7642bf, 0x843fe07e, 0xa8bbf09f,
5700 0xa80bfa0c, 0xa957e83c, 0x8cbf90fe, 0x1efd27e0, 0x2bf88f82, 0xefda7ca9,
5701 0xf8cfe7a5, 0x85fe09ab, 0xab6547df, 0x7f3d257f, 0xf0475fce, 0x044dfe0b,
5702 0x42ed12ff, 0x9a27cf19, 0xdfd97ca8, 0xf8aff542, 0x9afc11f7, 0xc865483f,
5703 0x1f9e847f, 0x7c12b7f5, 0xf046dfdc, 0xe0887f09, 0x95077f0e, 0xf4c3fa6f,
5704 0x5dff94fc, 0x2758afde, 0xfc672278, 0x45b49780, 0x79da1746, 0xcc968b69,
5705 0x6f7800ae, 0x6df74cb5, 0x4be40b9d, 0x1e2e8007, 0xf7f26555, 0x5234aef6,
5706 0x2bb347dc, 0x486cd6f7, 0xb9faa72a, 0x1592df54, 0xbed9764f, 0x77ba66a5,
5707 0xedc55b6d, 0x46ccb659, 0x32c56ded, 0x72ba3fd5, 0xcd8dd92e, 0xae300538,
5708 0x07818c32, 0x25bb6326, 0xfbdf9246, 0xefbae2a2, 0x6f79fd89, 0x45efcc88,
5709 0x2253891d, 0x5b6b21cf, 0xbaf07493, 0x7ce50cb6, 0x25dcdd04, 0x989b61c6,
5710 0xc49df91c, 0x33bdf64f, 0x79d602af, 0x0f7be497, 0xfba7c8e5, 0x3403cdcf,
5711 0xcbb5a331, 0xc8e4fc8c, 0xbea7ad89, 0x4b3fe4d4, 0xdbf8893f, 0xbf84caab,
5712 0x69c6eabd, 0x2c5fe8b9, 0x137be992, 0xcfe48b69, 0xbfe99fd1, 0x997ba640,
5713 0xc53255b6, 0xa322d903, 0x5a46c7c0, 0x7305ff77, 0xe9b95ea9, 0x9dd1c514,
5714 0x27878eab, 0xf802dda3, 0x387da3ca, 0x4fdf8494, 0xd77110ca, 0x94f1297d,
5715 0x9f3d1637, 0xf8bbff2f, 0x19f80cd9, 0x5f3f1315, 0xa3cfc2c6, 0x7f75fee2,
5716 0x68857df1, 0x31df693c, 0xcf7c547d, 0xc791b03b, 0xa5dba3ef, 0xe62ab888,
5717 0x4ff7d174, 0x1f92656a, 0x81f059fb, 0xc59d807c, 0x7de3dd32, 0xb3ead264,
5718 0x733e6007, 0x114a7c8a, 0xc855039e, 0x26c65147, 0x6ffef257, 0x893f235a,
5719 0xbaf40574, 0xb76849ea, 0x99fa617d, 0x05fb287c, 0x7f18ed5c, 0x9fde8fb5,
5720 0x8df313e1, 0xc5b217a5, 0x447bf63c, 0x81e614fc, 0xaadb3b71, 0xf9c785dd,
5721 0x504559b8, 0x657accef, 0x77fd5e2a, 0x9832edcd, 0x2c5feca0, 0x2cf1c7af,
5722 0x893f4ddf, 0x3c06a5e3, 0x38c578da, 0x53c537de, 0x69157dd6, 0xf75deeb1,
5723 0x4ebf0f25, 0x12288e0e, 0xb00674f7, 0x1f072801, 0x9c527531, 0xcb86703a,
5724 0xd326a641, 0x71e8b87d, 0x98fbcafa, 0x6193f028, 0xd10de7e1, 0xf6eb4def,
5725 0xee54025b, 0xa2aff4f7, 0xb2c9a83c, 0x233d0ef8, 0xc4c37b7f, 0x0dcb6578,
5726 0x421e63ce, 0x36840bf9, 0x7e8988be, 0x7ef2a732, 0x9b9fbc8c, 0x27827ad9,
5727 0x0dc094da, 0x8b7601ce, 0x5157507e, 0x95c2c45e, 0x3de11abb, 0xca265bfb,
5728 0xbe4bb355, 0x7e77245d, 0xe47f912b, 0x3aacb634, 0x62dfd116, 0x1ced1eb1,
5729 0x8a35f302, 0x88f39ee4, 0x91f01af4, 0xbdadf022, 0xd1c450b7, 0x6f7ebb1f,
5730 0x1445e512, 0xfb438c6f, 0x12b32f6f, 0x214cd81d, 0x7f0238a5, 0x0eff0336,
5731 0xebfcf44e, 0x1e5acc8b, 0x28e26d80, 0xfc64473c, 0x51ca30be, 0x3eabf798,
5732 0xd1deff07, 0x0fa677a2, 0x17fc7807, 0x383f9d32, 0x7bf3c597, 0x52367fd0,
5733 0x226bcf7e, 0xb59df85e, 0x2c3f7415, 0x4ff44b1d, 0x78054fd1, 0x86a666fc,
5734 0x8d9f7df0, 0xaf9bc1fc, 0xed22e7c9, 0xec152412, 0x4645dc6f, 0x5d71e5f1,
5735 0xd83eeeb2, 0xf6fa8b98, 0xfa12ffb0, 0xfa9de9b5, 0xfe426976, 0xe8da473b,
5736 0x1f769d1e, 0xdee5f9cf, 0x13d272c2, 0x1fff24f1, 0xe7e26553, 0x076d4ac7,
5737 0x2b76ddb0, 0xa27e84bb, 0x4155817d, 0x8ceed039, 0x1b6ab927, 0xf3f64f11,
5738 0xd6a3ccf6, 0x659fc04e, 0xda0a3be4, 0xbe2d032b, 0x7ebb1803, 0xbcc668b4,
5739 0xc72431f4, 0x5c03be7b, 0x2f077a06, 0x733c1037, 0xbda6920f, 0xe9df48d8,
5740 0x63345fda, 0xb68c804f, 0x5b979a16, 0x7cf30652, 0x35786ec0, 0x9c760dda,
5741 0x63b418fb, 0xd0e01ea0, 0x9401df70, 0x7529e947, 0xcd5748ed, 0x292ba3b6,
5742 0x429a5d0e, 0xabe4d572, 0x689ca10b, 0x91ac4b56, 0xc9f1adfc, 0x1afbe5b7,
5743 0x3afef711, 0x7ebafffe, 0x4df3e2fb, 0xfaef9c85, 0x7e68038a, 0x9a7f747e,
5744 0x60c6ff5f, 0x90a37efe, 0xe6b381e7, 0x70bf7298, 0x65279728, 0x5661ef22,
5745 0xaf7d254a, 0x53a0567d, 0xa1d3fca6, 0x9bd80fdc, 0x867ca76a, 0xc2166ebd,
5746 0x016079f8, 0x2ba40fd7, 0x29b29e88, 0x086cd54e, 0x3c1c812b, 0x70b90d0f,
5747 0x97e09c5f, 0xd17bffe1, 0xa418d0bc, 0x7d05d8ef, 0x393df871, 0x17e747e8,
5748 0xc57b4ad8, 0xd77ec9ab, 0x1f78d0e2, 0x439bbf1f, 0xa09820ae, 0x7d236af6,
5749 0xbdfa261f, 0xf0f4bb9b, 0x787a6b84, 0xe77fd322, 0x87aadca5, 0xf87a2b27,
5750 0x6e472153, 0x9f3fd749, 0xfdc3d2ea, 0x338c1c17, 0x1415fbf2, 0x828ed2af,
5751 0xc60ef7e1, 0x200806c5, 0xfca16a47, 0x6b9d01a0, 0x3f341e48, 0xbff88338,
5752 0x7c7d1aff, 0x6dd59d38, 0x9c603649, 0x59dcff5a, 0xefd68674, 0x073fd1ac,
5753 0xfc60e83c, 0x7dd209ec, 0x3c9f70c5, 0x387fe614, 0xe657e79f, 0x7869de48,
5754 0x5a0263e4, 0xfdf915bb, 0xdb8fbe76, 0xfe0b5f64, 0x4adb16bf, 0xa0af2853,
5755 0xb5f7c2cc, 0xf77c58ab, 0xdf8525a6, 0xbcb35edb, 0xa67f0dc9, 0xfba6cc8d,
5756 0xfedd6dd8, 0x2be48fb5, 0xe291be3b, 0x646b7bff, 0x8676aefa, 0x85eb4035,
5757 0xc5d15c75, 0x5cba34a9, 0x6049cfc0, 0x587aba3d, 0x3d3d15cf, 0xa874443c,
5758 0x31f90bad, 0xe45eb110, 0xfb4440c3, 0x72fb86f7, 0x8fc8dd71, 0x72e3cf91,
5759 0x0f744d3b, 0x2fa7ac59, 0x42e4d4be, 0xd68f3899, 0x10bed2f2, 0x69796a63,
5760 0x695e451b, 0x878f439b, 0x5127aa2f, 0xf08be11c, 0x0c5f789c, 0x0fbe453e,
5761 0xc7be73e4, 0x87bc3b72, 0xfae7bd7c, 0x1e38a9e2, 0xc44081ca, 0x084e1bf7,
5762 0xed87fc3a, 0xbb2896ca, 0x3fbfecfb, 0xaec8cf59, 0xeb0a1cac, 0x8e781dac,
5763 0xdf174fdf, 0xf4213ab7, 0xe9c094be, 0xebbcafa6, 0x56bc9efa, 0x8a5bae2b,
5764 0x12bbe3ca, 0x020daf85, 0x57fbda5f, 0xd3c26c94, 0x6b728e95, 0x4262785f,
5765 0x1f21323e, 0xb32a7bf1, 0x4c6ecfca, 0x3a5b1955, 0xf879b9f4, 0x7759887d,
5766 0x02cd2d9d, 0xd7d0f378, 0xb3d3fc38, 0xa6800c2f, 0x2dfcfd1f, 0xf67c3f0e,
5767 0xf9154c8b, 0xe1e73ff2, 0xe21c23f7, 0xaf9b45dc, 0xa1fade36, 0xb758dedc,
5768 0x238f1ce9, 0xbf3a5ec8, 0xc97a77ac, 0xa52cffcf, 0x07e781cb, 0x9cbb52eb,
5769 0xd7206e4b, 0x40ba6dd7, 0xe9860c71, 0x5f30a351, 0x9f129188, 0x57c7e5ad,
5770 0x1de3f3ea, 0xd7c4d58e, 0x50501616, 0x3d59c5de, 0x7d7e7e74, 0x73e68ba8,
5771 0xf9ab531b, 0x0f2bb9f9, 0x5dd667f7, 0x5ff69886, 0x8f9150e3, 0x68df42ca,
5772 0xf2f2265c, 0x768994e7, 0x7117f8ca, 0x9e8cdb9c, 0xfffbd446, 0x2a51663a,
5773 0xbf2d098a, 0x3dcf4869, 0xe6df43b7, 0x0face4fe, 0x24575c0c, 0x53f178f2,
5774 0xcf345dc3, 0xea0038c8, 0xe5f6be85, 0x3d53d088, 0x38a1e2fb, 0x87b27d67,
5775 0xe5d28bef, 0x92fb82d8, 0x5adce5d4, 0x7bfaf7d4, 0x3e144fed, 0xcd32875a,
5776 0x7e90967e, 0xda7f0ebf, 0x607968fe, 0x1e5706f5, 0x87172bd9, 0x609fe2e8,
5777 0xf6bcbbe8, 0x718df4d8, 0xa7360d4a, 0x648e297b, 0x300b514a, 0xeffeb84f,
5778 0xe9bccc52, 0xb74e8273, 0xbee9e238, 0x4cc3bd75, 0x1ddabdf7, 0x61da183b,
5779 0xc236db56, 0x89a3854b, 0x835c9e61, 0xb7d2b59b, 0x82f2a20f, 0x790bec1b,
5780 0x659f2a7d, 0x8e4d54c3, 0xc6d67e71, 0xdc94aabb, 0x772a2e30, 0xa3affff2,
5781 0xf2477aaf, 0xec1f9e34, 0xb07e5330, 0x8bae6894, 0x26dc1f95, 0x5c768dec,
5782 0x83ae0a57, 0xf5b4c9c7, 0xaf3c5d58, 0x9c639f11, 0xd1f2eccc, 0xada2e3ff,
5783 0x87ec4dbb, 0xaae2ded6, 0x25ef2863, 0xf942eab3, 0xff73c52a, 0x4147f51d,
5784 0xc6d49c84, 0x89a87e7f, 0xae1b0bdf, 0x2b35fcf0, 0x7eb317d7, 0x7f19886b,
5785 0xf3543abf, 0xbf19beb7, 0xdb32f469, 0x3461f3c8, 0x336b9ebe, 0x981ed07b,
5786 0x7ca74b6b, 0x8040b99d, 0xda239317, 0xbf3e677f, 0xe9ab29bf, 0x1bbf4748,
5787 0xdfc5e137, 0x4c36f801, 0xf6f4f117, 0x6bdd1354, 0x3cc0db7a, 0xe74652e8,
5788 0x49bd7a23, 0xb79a7193, 0x80db38ce, 0x31d8786c, 0xcbe504be, 0x13728ee1,
5789 0x3b0067de, 0xca186e21, 0x46eea599, 0xbf30efbc, 0x7fbe98a6, 0xd77fc5a2,
5790 0x49303d09, 0xddb039f2, 0x9a3f6367, 0xde6c4155, 0x7fdf4595, 0x88dff114,
5791 0xbb44fd76, 0xaca26ed3, 0xc03efa2e, 0x45e8e515, 0x83f68b9f, 0xf1a21af2,
5792 0xf912fb89, 0x72698bff, 0x8b3bf502, 0xe123b3b2, 0x949d89ed, 0xa9e9af6f,
5793 0xcdf23ea6, 0xf2130db6, 0x714fe351, 0x7cc7109e, 0x6493c456, 0xf37b72f0,
5794 0x3f4fd3c8, 0x37b1eced, 0xa43d0877, 0xd05093f5, 0x2209954a, 0x78a0c4ef,
5795 0x2564fe88, 0x75801e90, 0xfb197d36, 0x61dcf89e, 0x716d8e5c, 0xf6c74b6f,
5796 0x3a6ab915, 0x79d14bfa, 0x51eef5de, 0xf57fc8e9, 0xaafd3553, 0xaff9235a,
5797 0x7bff9ddd, 0x75b42f3c, 0xb9e45898, 0xc669747c, 0xe41bb573, 0xfdc59bed,
5798 0xc7476dc8, 0xbcbe3158, 0xc61256cd, 0xb66dd9f3, 0xbb721294, 0x478f3c6c,
5799 0xf1b36f6b, 0xca9b3abc, 0x1b36d5e3, 0xf2d37bcf, 0x27ddda6f, 0xbb5a0f08,
5800 0xfef8c3e1, 0xff7e54d9, 0x520d5e21, 0x1bd938bb, 0xb8acbcc0, 0x66f64614,
5801 0xc77f959c, 0xc8c0a12f, 0xf9fc31ac, 0xea266182, 0x49665b67, 0x9b54ec98,
5802 0xd87642ec, 0x4e925e96, 0x0df11272, 0xbbdbd6e3, 0x19f745f1, 0x6b7c0856,
5803 0xf3b7d4fd, 0xa9bede75, 0x08c56e72, 0x8bbd13b4, 0xd9b74e90, 0xbf315896,
5804 0xde97b254, 0xc3f5bfb0, 0xca7cba0c, 0x7994fe9e, 0xd815bfa2, 0x512f649f,
5805 0x8b133fb0, 0xfa0cfffd, 0xbbfebcc5, 0x819815e7, 0x60e3df46, 0x9e4fbb4c,
5806 0x68cf4b1e, 0x439c55a5, 0x0ff7bf44, 0xfacd95db, 0x93d82578, 0x75830d0f,
5807 0x3b9e66d5, 0x709e9131, 0x5e31b27b, 0xd849177c, 0xdbc2b285, 0x3df91a37,
5808 0x637bed4d, 0x27289d9a, 0x73d0f1e9, 0xc3ef8a7f, 0x31c78555, 0xc518daae,
5809 0xf9f9a257, 0xba63a9ea, 0x67a8107b, 0xc6dec23d, 0x8f48ed12, 0x3895cf19,
5810 0x8efc6b5f, 0x3f28ba77, 0xf77f9aaa, 0x2918a6c4, 0xf400c25f, 0xddad744b,
5811 0x8a4af9df, 0x115d7f69, 0xab486afb, 0x6dbf8951, 0xa32c42a1, 0xf3bf7bf9,
5812 0xf3f22154, 0xfadd69fe, 0x6d75c156, 0xf7e5ca48, 0x564e4f17, 0x5fc3d962,
5813 0x71c25f77, 0xa4ddc76e, 0xcf5c9d67, 0x3fbebffe, 0xaf34e8d1, 0x66debd44,
5814 0x97f7fbd0, 0x50fddc85, 0x9afd8ff0, 0xdbbcf74c, 0x22ef7c8b, 0xde8c98bd,
5815 0xfb07d46a, 0xbf9366eb, 0x501e0324, 0x30dfeeef, 0xc0af2a2d, 0x08b0fef7,
5816 0x326b2e7e, 0x1aa677d3, 0xbf208fc0, 0xa31f6a2e, 0xb7eda7f1, 0xf9abdb06,
5817 0xbfb69a39, 0x216cd313, 0x764bb791, 0xb9653387, 0xb398e501, 0xd9f067da,
5818 0xec987db1, 0xfddabe8d, 0xad3bc84c, 0xb7fb0dbd, 0x3c4afce1, 0x8c4c7bfc,
5819 0x6b24aef2, 0xec7fffec, 0x810f0a30, 0xcbac2b1f, 0x82aa7471, 0xeec24afd,
5820 0xe8f9146d, 0xd5a94af5, 0x94bef113, 0x149d6a54, 0x7df52f41, 0x874a87c4,
5821 0x942bdb77, 0xfce5a7e7, 0x60af684b, 0xbe4d9f5e, 0x20471ddc, 0x675e20ff,
5822 0x47e36a2f, 0x9cf7bb9f, 0xbe3a73b3, 0xbd9294aa, 0xbb018f28, 0x4307ec00,
5823 0x489bd2d2, 0x3f7c9a3f, 0x743c034e, 0xfca167bd, 0x3f05f7db, 0xec7e0a76,
5824 0xd8056e4b, 0xb7dcba51, 0x4bc71d95, 0x2527401e, 0xf5274889, 0x39dd4699,
5825 0x8b16568c, 0x5fb0c675, 0xfc8f87f2, 0x90cbf646, 0x17ec31e1, 0xcf224fb4,
5826 0xf12ed1cf, 0xb445c844, 0xec313c4b, 0xf0a36697, 0xe779c4df, 0xadab9369,
5827 0xfa70f013, 0xcefa44e6, 0xdbb469cd, 0xfb3ec04a, 0xdc5cd9e9, 0xee865994,
5828 0x3b0853ef, 0x760c1191, 0x5e7077da, 0x1abbcc55, 0x1cd6ffff, 0x883f1bc9,
5829 0xffd197e7, 0xfb75f2ab, 0x40b80719, 0xfbc76cbc, 0x1f744570, 0xf9d632ae,
5830 0xe9baf7da, 0x88974504, 0x601e11c3, 0x5be22217, 0x5176e2bd, 0xa30c3a71,
5831 0xe6fde774, 0xfdbf6ef4, 0xdae281ba, 0x882c7d3b, 0xb5bfb9df, 0x7b571f4c,
5832 0xed99e443, 0xcf88ca5c, 0x86b41676, 0x53495fd0, 0xabc9c519, 0x73f6fa3c,
5833 0xe3bfa32a, 0xddbf8fac, 0xcf4535e6, 0xd6ebbe97, 0xc06fac5f, 0x9714d5ee,
5834 0x8b8f15eb, 0xfad1c38a, 0xf2943f50, 0x46adbc78, 0x6f655f9f, 0x7ddf419e,
5835 0x12aeac66, 0x34cce7d7, 0xda8f8c32, 0xcff3a3ab, 0x1ecf0202, 0x9e1a5a12,
5836 0xd878efb5, 0x7bfc8d8a, 0x540981a4, 0xe1c1e5af, 0x3a2705f7, 0x5b65d67b,
5837 0x2c53e62f, 0xd881ace2, 0xf189daeb, 0x2e57cc46, 0x83c4830a, 0x302e70fe,
5838 0xa30d464e, 0xbac299ef, 0x8705e775, 0xd0356f77, 0x03e147ff, 0x3c26ed71,
5839 0x9813cfe8, 0x5afb40cf, 0x807f3fa3, 0x68e0ea75, 0xecebfebb, 0xb3bbc3f9,
5840 0x58ff7e63, 0x5038b52b, 0x7610f8af, 0x383a4800, 0x6ca77c5c, 0xf68a1b28,
5841 0x2378ad8d, 0x4c95c3ed, 0x0acaf79e, 0xa1bb9f62, 0x0ddf8f9d, 0x327c8a9a,
5842 0xa679fd12, 0xf302cefb, 0x6f9f94c8, 0x3573e328, 0xa672f3f4, 0xd7c4622b,
5843 0xb1307896, 0xbcfff04a, 0x1fa0f78a, 0x8c00b167, 0xdf1063df, 0xbdc4969f,
5844 0x26062da4, 0xd514cc23, 0xb5e4f3ca, 0xe9043cef, 0x8d7d0f3b, 0x8b077da3,
5845 0xda7bf805, 0x37dfd138, 0x74fbd1ba, 0x7e894d1f, 0x3ae282bf, 0xe17df8da,
5846 0x17efafbd, 0x9dfcb1fd, 0x953e3c91, 0xc35a7449, 0xeba71fb4, 0x2b74ddc5,
5847 0x53b83c93, 0x0f0f4eab, 0x773e7e45, 0xf74a824f, 0x0475b56f, 0x8eb44ba6,
5848 0xf75fd96f, 0x595dd23c, 0x5881defc, 0xdbefe897, 0x117e8bae, 0x9301acf2,
5849 0x1a8e816f, 0xcf91ef81, 0x2e93296c, 0xa10e74c9, 0xbf8bcfbf, 0x35fd1173,
5850 0xf9493d1c, 0xbdc47b3b, 0xa75c6d70, 0x8a0433ea, 0x3c107ef0, 0xd08f118f,
5851 0xdf8ca5ca, 0xf5e6d28f, 0x3504017f, 0x7fe05f6a, 0x00007fe0
5852};
5853
5854static const u32 csem_int_table_data_e1[] = {
5855 0x00088b1f, 0x00000000, 0xe733ff00, 0x51f86062, 0x39fbc10f, 0x716e1819,
5856 0x0143f822, 0xd9433117, 0x1017fa40, 0x606463bf, 0xbc48cf78, 0x040e357e,
5857 0x033b2f7b, 0x3e200ac3, 0xfef03ec0, 0xc95c481a, 0x4ebb3f4d, 0x622ed1d0,
5858 0x067e2ef0, 0x0c023d86, 0x1082590c, 0x54417ffe, 0x08fcddf9, 0x651898b6,
5859 0xf5012976, 0x93320003, 0x038009d3, 0x00000380
5860};
5861
5862static const u32 csem_pram_data_e1[] = {
5863 0x00088b1f, 0x00000000, 0x7dd5ff00, 0xc5547c0b, 0xbddcf8d5, 0xeecddd8f,
5864 0x21079b26, 0x086e3c21, 0x4bc60a22, 0x9bade102, 0x88b46204, 0x7d608a89,
5865 0x8420182d, 0x96d22247, 0xedf7ed7e, 0x5ab11062, 0x68db151b, 0x34105db1,
5866 0x060b28da, 0x2df0980c, 0xaa5694a0, 0xd1f58df1, 0x90cbc8a0, 0xf87e8784,
5867 0xce7feb69, 0x7bbbb999, 0x7c486eef, 0xfefdfbf4, 0x730ecfe9, 0x3399dee7,
5868 0x9ce735e7, 0xc92b3339, 0x210cb102, 0xbbf81be4, 0x22ad909c, 0xa46c6421,
5869 0xe5a22aec, 0x79fc4218, 0x8126c08e, 0xafaed090, 0x4234908e, 0x54cd364e,
5870 0xec84d9ad, 0x2e8473ce, 0x0327eda7, 0x6d2b0185, 0x76f6de2f, 0x4beb44a2,
5871 0xb41289b6, 0xf1d9765b, 0x4275cefb, 0xd6d5ea00, 0xd12607b6, 0x9136f77a,
5872 0x935da06c, 0xd242d390, 0x23623909, 0x61754fec, 0x559dbe7d, 0x7ddfac97,
5873 0xd9578c2b, 0xfa76256c, 0xd12691fd, 0x9b65f503, 0xe3a10084, 0x8f71d92d,
5874 0xb7f68032, 0xed042020, 0x7a6fad2a, 0x845d5150, 0xfdebb5dc, 0x212776c4,
5875 0xa2367c27, 0xca8f382a, 0xaa4228e0, 0x064a5b02, 0x1aabefd0, 0xfb42cd05,
5876 0xaa775aaf, 0x6aabe013, 0x69102f92, 0x1c1a8b7f, 0xc6c11d44, 0x78c086fe,
5877 0xbc703b7b, 0x1830f26d, 0x3bebf2af, 0x3cc22215, 0xb77c0f65, 0xf301c284,
5878 0xe13dc7d6, 0x74f1c7ab, 0x9a792e7c, 0x5bdf478e, 0xc1a09cfa, 0x885a9714,
5879 0xdce8e017, 0x84fd9f61, 0x52b7e613, 0x9e8aee19, 0x30ed9cc7, 0x7ac0aa8f,
5880 0xf009c4a5, 0x8fe657ad, 0xa8b7f48a, 0xf846f7e1, 0x7bfa73ea, 0xe5cddaa3,
5881 0xe9451f09, 0x8abd48f0, 0xf6904f10, 0x5280a44b, 0xf9e4497e, 0xd2324207,
5882 0x4883517b, 0x7fa45b54, 0xfa42794a, 0x9b7fffd1, 0xc1e293fe, 0x6c0aeadf,
5883 0x6dd08eca, 0x16681b99, 0x3769dba1, 0x5dd4a3a7, 0x5ebfdd10, 0xa0f4003e,
5884 0xdcf9d4f0, 0xcbe43e58, 0x4fad72c0, 0xd6fdbc45, 0x7acb0237, 0x1fcf869f,
5885 0x72c78df3, 0xe583cf9d, 0x58a57c1f, 0xf8657c06, 0x6cdf06de, 0xbcfa372c,
5886 0x5f49fcf8, 0xbe0d9625, 0x8cfe7c1a, 0x8d96056f, 0x7f3e3f3e, 0xcb06b7ce,
5887 0xcb0eafa0, 0x5a2f40ad, 0xf802f936, 0x035f76de, 0x20becd96, 0x6be9df3e,
5888 0x8e7ef2c6, 0xa4c9c4c7, 0x4878a250, 0x253710f4, 0xee99493b, 0x3d699429,
5889 0xd3d58ca5, 0x2a17f66f, 0xa5ee9eb4, 0x01978a75, 0x5685438b, 0xc3501f5a,
5890 0x92ff07da, 0x7d68d914, 0x0fb59fb0, 0x6453dfbd, 0x75a1f5a7, 0x3af87dac,
5891 0xad02517f, 0xf6b00f0f, 0x45431b8b, 0x38bf5a0e, 0x5b73dac8, 0xd693b148,
5892 0x9eac4373, 0xec53c077, 0x36bcf5a2, 0xc0f82f56, 0xeb489c5f, 0xfbeced05,
5893 0x51011d89, 0x61d2c675, 0x4edeacab, 0xf9d6ad28, 0x1348f4af, 0xef515d68,
5894 0x8fc51a24, 0x948f5aff, 0x7b21f149, 0xbfe43db0, 0x149bdb09, 0xe1bfb60f,
5895 0x76fac0af, 0x87ed8bd9, 0x5d584bfd, 0x17fb62f1, 0xbd629ffe, 0xbb63f659,
5896 0xd58fa56d, 0x0fb63f15, 0xfb06b958, 0xb00729df, 0x07cad47d, 0x12a77db1,
5897 0x5687f6c0, 0x4a99e63d, 0xf782b5eb, 0xb48fc0b7, 0xc03924ac, 0x328cc14f,
5898 0x05ab4fca, 0xf7f81b32, 0x28e980bf, 0x54ceae5f, 0xfeb70e50, 0x9009e0ad,
5899 0x834bfc5f, 0x7f27fcfa, 0xffdf8d95, 0x6991fb11, 0xfdef623f, 0xde3abde4,
5900 0xabde4fd0, 0x0d3f7a95, 0xbdad5ef0, 0x7d6cfd6f, 0x9e11a275, 0x7ef4ab57,
5901 0xae3c20b6, 0xef2bcdbe, 0x7846c9b5, 0xf7ac5b5e, 0x49e113b3, 0x4d3c1bee,
5902 0xd3f11b6f, 0x3f1876f4, 0x7e9e117b, 0xcc67837d, 0x8cfc463b, 0x9f8c2779,
5903 0x664fd803, 0x7a69fadf, 0xa69f88c7, 0x79f8c277, 0xa835e71b, 0xf31af36f,
5904 0x633f11ae, 0xe7e30dde, 0xbb278423, 0xff6cfd6f, 0xed9f88d0, 0x73f1861f,
5905 0xa0b9fb14, 0xf82af36f, 0x829f88c8, 0xe9f8c28f, 0xea2e7ec6, 0x3fdb3f5b,
5906 0xfb67e232, 0x7cfc6147, 0xd25cfd89, 0xfc1579b7, 0x829f88c3, 0x63f1847f,
5907 0xd19fa011, 0xf9a7837d, 0x9a7e2353, 0xc7e30d3f, 0xed8cfd81, 0x8fe33c1b,
5908 0xfe33f118, 0x693f1848, 0x427dd002, 0x3e69fadf, 0xf34fc462, 0x067e3091,
5909 0xfa533f61, 0x47f1af36, 0x7f19f88d, 0xe19f8c34, 0x2a42af38, 0xa10f00f7,
5910 0xee7ab8fd, 0x2349e767, 0x0c9e767e, 0xec52e7e3, 0x27ed1a67, 0x267ef7a7,
5911 0x33f11a76, 0x9f8c33b1, 0x95cfd8f1, 0x6767eb7d, 0x3b3f11a7, 0x29f8c33b,
5912 0xdd5cfc44, 0xec4d79b7, 0x6267e232, 0xfe4fc317, 0x89c5355b, 0x85ae9db4,
5913 0x993f489a, 0x08f1e1d4, 0x59ba2eb4, 0x046b745d, 0xb75112ec, 0x479b4837,
5914 0x1b3bdfa4, 0x457ef393, 0xa28eeda2, 0x8b979872, 0x76d1635a, 0x04f8d247,
5915 0xec939d83, 0x53d43149, 0xde18074b, 0xd43657ef, 0xf67fded0, 0x4cf686c5,
5916 0x9ea19e6f, 0xf0d13955, 0x229aa0fe, 0x8ac87d43, 0x67ef0cab, 0xd435affb,
5917 0xd8fcd673, 0x7505fef0, 0x17ed0d73, 0xda1957d6, 0x332c0a2f, 0xfc3647d4,
5918 0x4bfde187, 0xda197782, 0x95fe6d2f, 0xe8747da1, 0x7f3d4321, 0xf78663ff,
5919 0x306db6c7, 0xf83b8fb4, 0x427da18c, 0x7d4356fb, 0x269db1d2, 0x3ee9cf3b,
5920 0x45d79232, 0xecc27be0, 0xed054cfe, 0xc14b90bd, 0x89c032ba, 0xd76efc76,
5921 0xa530f57c, 0x76e7b2af, 0x17d28d35, 0xbae84a68, 0xf2a0385e, 0xfcfa76c2,
5922 0x17bd13a7, 0x9ff3e9ba, 0xdd4bde2a, 0xca53ec71, 0x80c9020f, 0x6940b552,
5923 0x6647bf6e, 0xf59458fc, 0xf443f0f5, 0xf74b6afb, 0xb75a64f0, 0xc0f58588,
5924 0x2c107fbf, 0x2209a7c8, 0x12f781a9, 0x82fd04ac, 0x9e0bb27b, 0xebf147f0,
5925 0x0e54419a, 0x6bbf4885, 0xd8066f64, 0xbe561b19, 0x643b07ee, 0xaf3a20f5,
5926 0x213c8401, 0x0ff21ebc, 0x9a0fdfa3, 0xfda5e19f, 0xa76a1559, 0xd0af8f47,
5927 0xf8e147f1, 0x73fe300d, 0x1d6f8c3d, 0xbe30de3a, 0x61a5706d, 0xc7429b7c,
5928 0x607b5377, 0x7c7c7be5, 0x8489844a, 0x87bc2f3c, 0x57075be3, 0x28f7f8e2,
5929 0x1e895fd4, 0x7e3c213f, 0x2ecbc833, 0x9c6c7f18, 0x689d0ff9, 0x2ae0ff9c,
5930 0x3615fce3, 0x0f2b3dff, 0x7013f1f1, 0x43857bfe, 0xab83fe6c, 0xacadfcd8,
5931 0x89f8f0df, 0x87effc61, 0xd3dabff9, 0x1b2673fc, 0xb1643fe7, 0x3656fe71,
5932 0x8f2b1bfe, 0x389df1f3, 0x71c29bfe, 0x8b21ff36, 0xeac57c71, 0x947f80d5,
5933 0x009a84ac, 0xa40c9f1d, 0xb03fa98a, 0xca071d0b, 0xa9942911, 0x30b5f909,
5934 0x69f8e114, 0x2fb7e302, 0xa1bf2812, 0x73e3f1be, 0xad9aa012, 0x9c5dfa80,
5935 0x163517d7, 0xb097a02a, 0xf32bfa9d, 0xcd15a838, 0x5937f222, 0x405c0d6b,
5936 0x166cede1, 0x58af50fd, 0xfa00253b, 0x6e4adaaf, 0x24ef832b, 0x9fe78212,
5937 0x86c9723e, 0xcb9979e8, 0x91f27579, 0x0b7928f6, 0x644551fb, 0x6f850d44,
5938 0xd8c1301a, 0xea63fd48, 0x5fea1107, 0x0cfd407c, 0x13f25942, 0x11f78d99,
5939 0xdea097f5, 0x6825fd4e, 0x7e256427, 0x2b7bbb47, 0xc65fc283, 0x6258ffe1,
5940 0xcdf1faf2, 0xe54fc042, 0x8f9f8bf3, 0xb6f53f46, 0xf48a0e15, 0xfc731c08,
5941 0x9d3a86a9, 0xd4e81f97, 0xd81ac3bd, 0x557e2020, 0x8a3957c0, 0xafb72126,
5942 0x8eb8a2c9, 0x252effbc, 0xfd45267b, 0xf723c40d, 0xb2dfefa7, 0xa6e4185c,
5943 0x58f4cee3, 0xe13ad8f3, 0x5ca0b2c9, 0x78cb2c93, 0x1a6dae42, 0x481ed32d,
5944 0xb8fe47b9, 0xebdc6a3d, 0x99f58d4a, 0xa77ac665, 0x142d91ec, 0x8172ceae,
5945 0xcefda7ac, 0xd76c6d9a, 0x525a71c7, 0x78f99d18, 0xbe0ce965, 0xc1e65059,
5946 0x79d23763, 0xab7d9bb6, 0xbb7d53c3, 0xa0585d4c, 0x011fbfa7, 0xf0d3faba,
5947 0xd9bb1fbd, 0xcef0cdbc, 0x329e6d96, 0x73d9cf3a, 0xb7f000c4, 0xefbffe19,
5948 0xb92c7872, 0xb0f35cb4, 0xf3b12c4c, 0xa37fc331, 0xa09f3cd7, 0x4df0eb0c,
5949 0x8ce7e695, 0xfa708e6f, 0x41fc0c7f, 0x1fc0a3cb, 0x9cc3fe14, 0x957a223f,
5950 0xd5b547f1, 0xa1f8033b, 0x209151fb, 0xdcbf395d, 0x5e65f9c0, 0x082f919d,
5951 0xc740caf1, 0xbc85b305, 0xc1f1455f, 0x0b07ce2c, 0x737c8dea, 0x99cbf10b,
5952 0xe372e871, 0x6777f5da, 0xfbf3b1a8, 0x4dcdf390, 0xfc46eff7, 0xd193cec4,
5953 0xa74e56e9, 0xed8c6a5b, 0xdeba7037, 0xbb3ae9c2, 0xa997c1fe, 0x563f20fa,
5954 0x7bc83203, 0x7a742ff5, 0xe9e81bb6, 0xc334f4e5, 0xe7a72b79, 0xf4673fad,
5955 0xcedbc334, 0x7f5ed9e9, 0x63432646, 0x77c335e1, 0xf9988adb, 0x39cf4028,
5956 0xacf4f8fe, 0x3d4c2e6e, 0x497cf51c, 0xc3d4caf0, 0xa8b67251, 0x5f50dca1,
5957 0xf0d1b818, 0x39fa82fe, 0x7579f686, 0xb7ed0d0b, 0x50c3b9af, 0xb9ffe39f,
5958 0x56dbfde1, 0xdfb434ac, 0xa1af7352, 0x07caa6fd, 0xbd1bf50d, 0x9fde1a8f,
5959 0xa1bd7b35, 0xd3d9667d, 0x4aebf686, 0xe5ea18b7, 0xf7861d9e, 0x870b5d85,
5960 0xeabae3b4, 0x887f63fd, 0x4567be27, 0x3beb353e, 0xf61e2f5d, 0x88fcf8a9,
5961 0xc796046f, 0x3f3e1a7c, 0xe58f1be1, 0x74dfd04a, 0x60ecb05d, 0x7343f565,
5962 0xe2a3b886, 0xdac89f1e, 0xbdb3d060, 0x7dfd43e9, 0x7fa3deb3, 0x14ecf159,
5963 0x902c5cbd, 0xbb075832, 0x3fad1db8, 0x49d7c53f, 0xb942ee42, 0xb930ac5c,
5964 0xb335bc5d, 0x3d422488, 0x4e26bc34, 0xcf2c267c, 0x33e70141, 0x00c72eaf,
5965 0x91fa82e7, 0xe036f826, 0xf9030b38, 0x1a8be786, 0xebbe1926, 0x7c222dd8,
5966 0x27c6414b, 0xb65672c0, 0x85f002c7, 0xeebe0ef6, 0xb3d78012, 0x4beb02d7,
5967 0xe7b43f73, 0xa9a57c3a, 0x73c02587, 0x7cc79619, 0xe23cb1b3, 0xd87962f3,
5968 0xc7e58957, 0xdb2c1abe, 0xfcb02b7d, 0xf2c7e7c8, 0x2c1adf03, 0xc3abeeff,
5969 0x1eafa0f2, 0x017c77cb, 0x35f2df2c, 0x2f86f960, 0xaf9b6588, 0x9f4ecb19,
5970 0x5e5d4b07, 0x4865f8a2, 0xe8bf1466, 0x8fd74ffa, 0x9cbf38c7, 0xc7897e00,
5971 0x7c8c1b17, 0x41ae5471, 0x43eb30be, 0xfacc1d33, 0xc3f2bbef, 0xdbb30b58,
5972 0x443f2fbe, 0xa2659de8, 0xf46f4e77, 0xbd146226, 0x0cdc5ac7, 0xfbef4e1e,
5973 0xf638de00, 0xb8b025fa, 0x83b28bf7, 0xff160e3c, 0x6a7a71e5, 0x2ff8b201,
5974 0xbe96bb1f, 0x52f686db, 0xe3e80460, 0x77fe23d3, 0x4fb7c438, 0x6752b41f,
5975 0x99f9e7aa, 0x1e23d7e9, 0x86fd0788, 0x28ba01f9, 0xdbb6c7e4, 0xed5e1813,
5976 0xe84a5216, 0x05ef717a, 0x47736a4f, 0x29225d61, 0x2b407df0, 0x97e9c577,
5977 0xdf80a0da, 0xeb5af0de, 0xfa1722fa, 0x57d8f23b, 0xb58e5005, 0x61343b30,
5978 0x30f688af, 0x01a13d09, 0xdefac37e, 0xdc4065aa, 0xc502fbb8, 0xc071eb8d,
5979 0x9f9fc469, 0xf8220bd6, 0xa8e297bb, 0xbab3d70d, 0xb0dfc40c, 0xf667862f,
5980 0xe9bd7f01, 0x39f0dec9, 0xdfe03037, 0xf4decf82, 0x8b7a6f57, 0x9ae7d478,
5981 0x76bbfce9, 0x2bf7925d, 0x50d4f415, 0x80f4ffe6, 0xc7bf7d6f, 0xf0254f0c,
5982 0xf3bed8f1, 0xceba5771, 0x09836dc7, 0x906de71d, 0xe9ffda17, 0x80930ba6,
5983 0xb41fb42e, 0x71b7bbbb, 0xba17b9fb, 0xf636cc9e, 0x2fe5cd57, 0x42925fdc,
5984 0xb8e94b84, 0x4921452e, 0xbd161d74, 0x1bf4442b, 0xf83f76b4, 0x5a1cbbe3,
5985 0xd8fe0aad, 0x2a435789, 0xdbf468f4, 0x227fef4f, 0x659bfc11, 0xe1f71619,
5986 0xcbd47438, 0xb76cc125, 0x680fda33, 0xd74fd636, 0xf441a509, 0xeba4d493,
5987 0xc075812f, 0x0c3c3eed, 0x960672f4, 0x32cb3f7a, 0x54e1f714, 0x23d33fa4,
5988 0x67a8c98d, 0xf86cf84e, 0x470d0fde, 0xe044fd4f, 0xd09f2268, 0xdf1481ef,
5989 0x7efcf4e4, 0x9d20728f, 0x485e2055, 0xc02fe45a, 0xffd3b37f, 0xfd0a19be,
5990 0xfbd7584a, 0x7e8a0ead, 0xbcf0a5eb, 0xfd1e30d1, 0x32f7d54e, 0xe59ebbe1,
5991 0x7447224d, 0xdb74a77e, 0x175bf7c2, 0x46ddd835, 0x50d930bb, 0x74ce6eaf,
5992 0xf844ec1b, 0x95c21807, 0xb77c0482, 0x975db398, 0x7c035ce4, 0xe3043f74,
5993 0xf605df80, 0xbb5b12de, 0x4c5155e2, 0xe72f80da, 0x5ef9d78e, 0xd53ef59d,
5994 0x915fc74f, 0xf917c809, 0x1055429a, 0xa0ae8fe9, 0xb7eb42c4, 0xa6dcdaf3,
5995 0xbd61d345, 0xf6616e3a, 0x4b290578, 0x92b37f04, 0x7c4015d4, 0x94b124f2,
5996 0x249e5c82, 0x47e6246f, 0xa2fbe1c9, 0xbedcf082, 0x531768c6, 0x5f50d97f,
5997 0xcfac6f50, 0xc3a6d727, 0xb5fcf2be, 0xa0080932, 0xafed8c2f, 0x168e4c88,
5998 0xb0d59a90, 0xd995afbe, 0x4dd7363a, 0xdf0a2ca4, 0x2f1e1792, 0x1feb4398,
5999 0xd31ecc8b, 0xa61745f7, 0x82abf830, 0x6d0f15eb, 0xff29a4ff, 0xe879aa06,
6000 0xb0d581f7, 0x09b7f95e, 0x963526da, 0x7e16df7e, 0xfafabc33, 0xcb3fb31f,
6001 0x20d258e1, 0xec710278, 0x0ebe6e80, 0x4d2e7aeb, 0x08e21b72, 0xe2a3d42a,
6002 0x9f99df0c, 0x9f8188d2, 0x36bd17ee, 0x1fe31fa9, 0xa904a7f0, 0x9f7ef15b,
6003 0xfa6233fe, 0xfec6934f, 0xa40ffd80, 0xfa1817fd, 0xf8507f57, 0x3fc0c587,
6004 0x4bff5e2a, 0xbb76785e, 0xaa93ea9f, 0x12248fcd, 0x971e3eba, 0x4a35d2ea,
6005 0xee9bc5df, 0x1f3a044e, 0xc089fc93, 0x6203c7af, 0x7ace2069, 0xe9d25735,
6006 0x100a71ed, 0xd27f82c7, 0x733c4ffe, 0x5ff7fa1f, 0x18dd926c, 0x86b06a9f,
6007 0x971e54ac, 0x4e9c2d36, 0x887eb172, 0x2539efd5, 0xc8d9bd42, 0x3d4f557f,
6008 0x0af90e92, 0xbc785394, 0xecf68426, 0x969f8dd2, 0xba44bae0, 0xdfcc8e51,
6009 0x52e7f8c1, 0x51cdff50, 0x29db6292, 0x5777e89c, 0x3754bc73, 0x4c4a77dd,
6010 0xa3b57f84, 0xbf7e6c3f, 0xd7a5db92, 0x23b4ae49, 0xe32704d4, 0x87d038c8,
6011 0x80483e3a, 0x0be2a5d9, 0x1c42e78f, 0x2be363b2, 0x9e144289, 0x1d3a3974,
6012 0x3b8ffdbc, 0x6df59ed5, 0x68b39527, 0xaf5f47fb, 0x4f6e66d4, 0xb172b0b7,
6013 0x449c4a1c, 0xf5e2e0f5, 0x8fa7e6b2, 0xc4fb3f17, 0x5c418f93, 0x76ab3df0,
6014 0xd17fed01, 0x33bf2fb3, 0x6d17d691, 0xb3a6d391, 0xf4853869, 0xe9aa5d08,
6015 0x22f22b7f, 0xfe7aa874, 0x84bd4565, 0x4a65ff3d, 0xb68b1e84, 0x25c856ec,
6016 0x0e28f8b1, 0x9dda56ee, 0x3c12e871, 0x81f60254, 0x153fc2f8, 0x5df1fba0,
6017 0x1d9fe902, 0x5feb9f07, 0xf01ff5c6, 0x74e47484, 0xf4cdd30a, 0x0ba5357e,
6018 0x4e9d6be8, 0x5cb1f6e6, 0xea7f40bf, 0xe7e7e428, 0x54fc5276, 0xc1aaddfe,
6019 0xbb9f2bfc, 0x71e61133, 0x7c61aa54, 0xe9ddf8fd, 0xa56e3a1e, 0x63774fec,
6020 0xfe579ec9, 0x6fc827e1, 0x49ff5e0b, 0x8867c63a, 0x6b82d327, 0xe6133f8f,
6021 0x4cdd6f37, 0xe27cdf9c, 0x7cabbe45, 0xfd032c5c, 0x4a44b9f7, 0x8b91c4b7,
6022 0xe3b31283, 0x06a06e8e, 0x51df9d18, 0x7e60acba, 0xe6221bca, 0x07721129,
6023 0x09fff901, 0x10b50b9f, 0x8db9feb0, 0xa4b369d1, 0xcad461fb, 0x8dd7e68c,
6024 0x7d01b4f7, 0xf4f20c4e, 0x6a8b7d87, 0x3e39f922, 0xbf686f84, 0xfad3ebe2,
6025 0x5550fa33, 0xa3bfc05b, 0x3c317ceb, 0x64dbf787, 0xf0d73d8f, 0x3b26f91d,
6026 0x3e72fe32, 0x013b853e, 0xe9a3e7d6, 0x4954edf1, 0xdaf87416, 0x457f1448,
6027 0xf79337c9, 0xf932f78d, 0x503de5d6, 0x67ed0a5e, 0x03f262df, 0x47fac1df,
6028 0xc7f50ae1, 0x0bd7ddf6, 0x24ac0fa8, 0x37ae4f14, 0x8dae5cca, 0x509f3aed,
6029 0x292125b8, 0xffa05f8a, 0xee3fc414, 0x4b5fcc57, 0x97d28bbf, 0x625e30d5,
6030 0xdcba7f6c, 0xfff2e02e, 0xc8ffc826, 0x7593fc88, 0xb67bee4c, 0x17a8fc9f,
6031 0x2781cb17, 0xa579031f, 0x4157e9f2, 0x9832e55e, 0x7b8d67f7, 0x9531f9df,
6032 0xba82cf93, 0xa7f51a9c, 0xb72b4e59, 0xe4f1258e, 0x46a733f4, 0x7d29cae2,
6033 0x9d4e571e, 0xffc7c8ed, 0xc753fa57, 0xfc2657df, 0x27b0fae9, 0x61f59a3c,
6034 0x3e22a4bd, 0xfe90facd, 0x620a45bd, 0x3be74ff9, 0xfeaadf9d, 0xe80864b4,
6035 0xea5f309d, 0x4be6177c, 0xe262ef9d, 0x99fc06a1, 0x18865fdb, 0x816b8510,
6036 0xf032fead, 0x809a6c23, 0x87617e72, 0x6ceef305, 0xbff40463, 0x584bd446,
6037 0x1ee2dd7f, 0x8ce8760b, 0xf67c2f49, 0xededf273, 0xbe5aefff, 0x307b63e0,
6038 0x861ca03b, 0x74d14be0, 0xe0c2d71c, 0x02403eac, 0x781f5143, 0x7f28b2c4,
6039 0xf7970e79, 0x9ad83e17, 0xec2c780f, 0x8ed4951a, 0xfa30727a, 0x6f5cd593,
6040 0x49abf69c, 0xb74f4fa0, 0x78bfa0e4, 0x8ae8bf7a, 0x34f7ff97, 0x209fefa7,
6041 0xaecb463e, 0xa44ea48d, 0xba45d6fc, 0x6ff06ed1, 0x714d91b4, 0xcba6aff6,
6042 0x5f7e2f4c, 0x01fd007c, 0xdbdb4f1f, 0xd8e2ca4b, 0xf9f2b7b1, 0x25f3d8ce,
6043 0xb7178fae, 0xbd80b7ac, 0x8b46f174, 0x41bfefc1, 0x479d7ce6, 0x67af80f2,
6044 0xc6bbb1ec, 0x8bf71e00, 0x5649e41a, 0xbc529cb7, 0xf342fc71, 0xb07fa1fc,
6045 0xdd93eeb7, 0xca2f4fc8, 0x0f01dbc1, 0x11b49e2f, 0xa1db2fd8, 0x078a2dd4,
6046 0x830a9de7, 0x4661c773, 0x2f0a1f97, 0x50ce5d85, 0x3673c411, 0x58dbe412,
6047 0xf3e4133a, 0xb0240dd3, 0x2de81b32, 0xc1237ab2, 0xca0a57bc, 0x77c327af,
6048 0xa35ed35f, 0xe6c2f3e4, 0xe8127f2d, 0x045b4b7b, 0x2fb685b7, 0xe015da95,
6049 0x64e6ea97, 0x68d8f411, 0x74ffcf55, 0x147d725f, 0x4b27ddff, 0x13bd9788,
6050 0xf009bc5f, 0x2143a672, 0x79efcfb0, 0x68f31ba9, 0x23e4b4cf, 0xaf34f5bf,
6051 0xb2e47de7, 0x43f412a9, 0x3a665f10, 0x304c6a8e, 0x7b1527d4, 0x335c0007,
6052 0xb5cbedac, 0x2bb77838, 0xa1fdeecc, 0xb2b7b3e4, 0x96fbf2cf, 0xb15ebf2e,
6053 0xfeef8a2c, 0xfdbf2b1e, 0xb2efc9e3, 0x987f6a95, 0x9cd6b2f7, 0x65cf80fe,
6054 0xc5fb917f, 0x7d67abe3, 0xccdc2fcc, 0x9abb65f3, 0x1a5efca8, 0x544dbf25,
6055 0x01c4e37e, 0xe581fa5f, 0xdf9059f7, 0x2bbdf038, 0xf2e8fa33, 0x0872db9b,
6056 0xc9b737e5, 0x7933c862, 0x7d76e655, 0xf42bf28f, 0xea0d3ebb, 0xa388e6b2,
6057 0x100f01af, 0xe3ccdcc7, 0xc80e30fc, 0x71b8a4b1, 0x63957d9e, 0x8e59bfdf,
6058 0x98236d97, 0x6f4b1317, 0x76cbc726, 0x80163950, 0x978e4cee, 0xce3952b5,
6059 0x11df958e, 0xbecbf231, 0xdf621a5f, 0xff673757, 0x5e3a66ee, 0x6cd6479e,
6060 0x88bcfdf4, 0x968d8f3c, 0x70914967, 0xbcf231be, 0xbcf26fbf, 0x9533cb8d,
6061 0x1c5aa1d3, 0xc62d6aba, 0x2717acfc, 0x1e7c6d1c, 0x226ff2f8, 0x5baf49fa,
6062 0xeafb5d98, 0x8063a384, 0x7870a62f, 0x743a7086, 0x7fd8fcfa, 0xd347c4c9,
6063 0x5f8a4e41, 0xe42dfbaa, 0x28d92f35, 0x4b87d013, 0x1fa10e9b, 0xe8ab8e6a,
6064 0xbe399576, 0x7311eba2, 0x8351659c, 0xc7c79eb1, 0x11db172f, 0xa89af25e,
6065 0x77c38a6d, 0xb9c13d79, 0xe71deebf, 0xbd9c0898, 0x79f47dc5, 0x3e9706f4,
6066 0x970a31af, 0x1f24d197, 0x8f1489e2, 0xbffe2f28, 0x2a87188a, 0x90c0bc2b,
6067 0xeb913fef, 0xc2bafcc9, 0x944b0862, 0xf80e3e43, 0xec77f551, 0xb1b27d83,
6068 0x303cd507, 0xb44d27a7, 0x7a9fc17a, 0xf28ddeda, 0x0965d3ac, 0xbc0dcba7,
6069 0xd407179f, 0x55bf0114, 0x586e0b37, 0x5f43aa77, 0xbd86b9e2, 0x02517e8f,
6070 0x55b0b47c, 0x0f915b70, 0xe7e0294f, 0x17f5d095, 0xe5bf29f8, 0x0bbdda14,
6071 0xf8450b5b, 0x010ee17e, 0xc37bd213, 0xb6e95f4f, 0x59e3d388, 0x7009df80,
6072 0x8d75b376, 0x57b7a7c3, 0xfc037e4b, 0x5b9d8fc5, 0x56e0c59d, 0xde046aad,
6073 0xe77861b1, 0x3eaf3888, 0xbde3abc2, 0x98977837, 0xe4daf8e8, 0x220f1833,
6074 0xf27dc92d, 0x5c6dbe6b, 0xa1b49aaa, 0xa7c7a67f, 0xf3bd17ee, 0x951b8864,
6075 0x8e31920a, 0xedf18ddb, 0x8fffa01f, 0xf83fd7ce, 0x6eba2117, 0x09f1b9fd,
6076 0x67c9f7c4, 0xba00cd0e, 0x24517a2c, 0xce974a36, 0xe1091746, 0x0140483e,
6077 0x8935543a, 0x48f78c1e, 0x5ceb82a1, 0x65a8f8d1, 0x42ecd8f8, 0xd5b5583d,
6078 0xbf4e981a, 0x49fedaaf, 0x9d33d82e, 0xcbef7577, 0x19ffbf02, 0xf898e501,
6079 0x1f6173db, 0xfb624aa8, 0x6efc663b, 0xd8fad854, 0x1b31c3b1, 0x606841e4,
6080 0x82aa8be7, 0x946b64b3, 0x457bfc3d, 0x7be971c6, 0x7fe6d798, 0x30bcc05a,
6081 0x5cfa2f80, 0xd36f9e8b, 0x4bf334f1, 0x00e59aaa, 0x6aaa539c, 0x7109d2d8,
6082 0x5683aa92, 0x1baad75c, 0xb75c614e, 0xa8b3f378, 0x459bab7f, 0xe31c9f83,
6083 0x2188369f, 0x4d57f82b, 0x4ece304b, 0x1eb087eb, 0xe9a71f8c, 0xb45a8fcd,
6084 0x1fbb75b9, 0xa7f9e4e4, 0x529cf112, 0xf444a6db, 0x1fce1b53, 0x47f18a1f,
6085 0xd79ef783, 0xf9c13d1f, 0x318a6fe3, 0x521a479e, 0xf0a54fd1, 0xb1c59415,
6086 0xff7cc3d7, 0x807fe7ec, 0xd6c76978, 0xf000fecf, 0x99d7fe2e, 0xe282fc3f,
6087 0xbbb2ec91, 0x3f55ff41, 0x9bc636f3, 0x728eeff4, 0xf4f9d5bd, 0xeba71853,
6088 0x41aacf7c, 0x47ad9d6f, 0xaabc4307, 0xe997cb73, 0x6f2c9f60, 0xd6f6869d,
6089 0xfdc56df2, 0x40fb1c49, 0x036f812f, 0x9a13887d, 0x69b7b5e9, 0xf38060ef,
6090 0x6c37a524, 0x0be38609, 0x5e2c25c1, 0x42b8f2a3, 0x6c78fc63, 0xe9a11c4c,
6091 0x8ca66bba, 0x54d65281, 0xc27887d2, 0x978e945b, 0x8d7e81f6, 0x89ef6fcc,
6092 0x1fe1277e, 0xd5b24e94, 0x9bcfbf48, 0x31f1fde6, 0xed4a6b68, 0xea109e31,
6093 0x78f4de03, 0xc78a1bef, 0xdaf9056d, 0xdf8c27fa, 0xd3a6dd00, 0xfb3e7689,
6094 0x938860f9, 0x6fbb931f, 0x56d57dc5, 0x5797ee2b, 0xf28bbeb5, 0x75edb9d3,
6095 0x8f0937b4, 0xf09276bb, 0xf1938b1f, 0x8dead3dc, 0xe087162e, 0x853887f8,
6096 0x79cf889a, 0xb1f1823c, 0x29e8a71e, 0x7585713e, 0x6523cf28, 0x1b259471,
6097 0x298857df, 0x8f8c23ee, 0xd13df3ac, 0x1b83c749, 0x3a2e30f0, 0x0e3f16de,
6098 0x72cb8e14, 0x20fd017a, 0xa78e16ce, 0x8840fad1, 0x778404af, 0xd07d1c49,
6099 0xe9c59eb9, 0xfe63653a, 0x2c3e8449, 0xa26456fe, 0xdecf3eb3, 0xe0dea7d6,
6100 0xc9f8b6ff, 0x6c79c587, 0xbe3a9e2c, 0xe7c7af8e, 0xb7ef8559, 0x98215a5f,
6101 0x802a6ff7, 0x1d34971f, 0x513f2052, 0xf9f4c75f, 0xbc3b7076, 0xf31119e3,
6102 0xf707576b, 0xeb371ea2, 0xde70a58b, 0x3fbc0e21, 0x6d2ef0e3, 0xc744eb66,
6103 0x49c05756, 0xb3d8e9fb, 0x6979f903, 0x4fc521e3, 0xf0d7dbfb, 0x46fcc2bc,
6104 0x4eb03f26, 0xefe0a204, 0x2e776e78, 0xbb322f8b, 0xddce3cdf, 0xd3a79e56,
6105 0xea9c7f12, 0x718653c6, 0x0a83f916, 0xff3e97cb, 0xcf242778, 0x44efe82c,
6106 0x5f204c9b, 0x2c5044f2, 0x593fb78d, 0xdc799569, 0x74958eba, 0x25f3c4bd,
6107 0x449e762e, 0xde30514c, 0xfe35dcb1, 0x941a5260, 0x507e0a8a, 0x5fb64aed,
6108 0x5a9ffb5b, 0x36bbd006, 0xc78c06f9, 0xebf099d6, 0xc217734e, 0xd4f71339,
6109 0xaec031b2, 0xec937d66, 0x5fe018b1, 0xafed2aee, 0xd1573852, 0x275ce07e,
6110 0xef3c3491, 0x94962622, 0xb7447cc2, 0x138f6dc5, 0x659d9307, 0x17851bc4,
6111 0x9f3c6dd9, 0x57cebe42, 0x9f7d1fa1, 0x6dadb175, 0x3dba361f, 0xc495f002,
6112 0xaf0bd5f7, 0xbbbce377, 0x580d051a, 0xd563aa9c, 0x05f2ce9d, 0xdae8dd60,
6113 0x2e4b949a, 0x87890fc5, 0xfe0e27ae, 0xbddc685c, 0xaad1f41b, 0xa649e244,
6114 0xaab14672, 0x4e70398a, 0xc84db467, 0xf53d3e01, 0x5fb48bea, 0x60488b7b,
6115 0xa9cbbf8b, 0x92790be7, 0xe41cce41, 0x010bcc7e, 0x3526fe56, 0x5f39a702,
6116 0xe92bc084, 0xd3bc7391, 0x39c62744, 0xd113af4e, 0xc5c9159f, 0xfccc9bbf,
6117 0xf8001273, 0x88b27af9, 0x4a1a79c3, 0xc142bf78, 0x7f05da3c, 0x4420be79,
6118 0xf1a21d18, 0xf46a5a95, 0x89edeb17, 0x436fb0b9, 0xc8369efc, 0xfde0ae4b,
6119 0x9e332bf5, 0xe7e2a1f3, 0xcf52fb07, 0x7e6cffd3, 0x7fd07ec9, 0xa8f9de15,
6120 0x36cffbd7, 0xdb32039e, 0xe42f08ef, 0x7bb9500d, 0xe7b5884c, 0x5c1e5b2b,
6121 0xb1e0f90d, 0x0464f3fb, 0x91541be4, 0xa1f20d04, 0x077df6cd, 0xf1c84de8,
6122 0xe0271271, 0xd97d67b1, 0x87db7e0b, 0x98f26eff, 0x0b57e2f3, 0x2e8dfbc1,
6123 0xf058dfdc, 0x3f51db97, 0xf88c3359, 0xfc46abb5, 0xf198463a, 0x4bb3c468,
6124 0xb28de233, 0x787ce079, 0x3c6f1a4e, 0xb3c6655f, 0x0e1da844, 0xd0404af6,
6125 0xf931fe80, 0x11ebcd0f, 0xa6fcdeee, 0x8f5f1b34, 0x5fe95e38, 0xa99d2d99,
6126 0x533b806c, 0x985ca10a, 0x19cb28e5, 0x83dfe012, 0xf12b02d2, 0x7e85cd2b,
6127 0x8f9f0649, 0x73bec150, 0x00891c80, 0x047286af, 0xcf402827, 0x6e07c83b,
6128 0x7c85a7a0, 0xd919be42, 0x2cef3d33, 0x5cd0e97f, 0xe03ad5fa, 0xae514bdf,
6129 0x14a939d8, 0x06cda812, 0xb0dcd539, 0x367d076e, 0xf38242b5, 0x18ad44e6,
6130 0xddcce706, 0xc7903e58, 0x451aefde, 0x182c5f30, 0xfa0e9b3a, 0x291e7aa9,
6131 0x80f7fd03, 0xfc033dd2, 0xccedfbdb, 0xaec8b94f, 0xa5ff3ea0, 0x9cafdf5d,
6132 0xa9cb97fa, 0xc8b5763c, 0xebc39c2a, 0xbb64d96a, 0x22cdea00, 0x4eaef79e,
6133 0xc608bbae, 0x19916cef, 0xc0b6155c, 0xb7c7e005, 0x741eb8ca, 0xf3c64c56,
6134 0xadbb612c, 0x7613ed85, 0x78927cb5, 0xef3e947b, 0x22f87e6c, 0x6a3c3388,
6135 0x793fbf89, 0x9df2cdbd, 0xfaf0d4fc, 0x3f9314db, 0xe58dbd71, 0x94303c4f,
6136 0xf96963ce, 0x330ebe69, 0xe9c49879, 0xabfcd2fc, 0x5adbfe70, 0xe74f3fa8,
6137 0xfcde2251, 0x3ce84ba3, 0x312dbc27, 0xd33c4afd, 0xa3b3a4e7, 0x0efef03c,
6138 0x3e0065a2, 0x02214c26, 0xf784f3c8, 0x8febee08, 0x7e8f99a9, 0x94898bd5,
6139 0x4c5f29cf, 0x0b7ca16d, 0x89c3ae7a, 0x36d8fbf6, 0xc997c0c9, 0xc17bbd53,
6140 0x90771ccf, 0x771dbea0, 0x9e3ed8d0, 0xa71c4404, 0xd27cf8dd, 0xc6bd6331,
6141 0x1233f7c6, 0xf7f03a49, 0x8445afda, 0x689babab, 0xbb7ed177, 0xfde0062a,
6142 0xe1675d02, 0xbf2d1494, 0xade34b16, 0x8c6d2bf3, 0x08551e2f, 0xce8f2fae,
6143 0xc13ee277, 0x9855f99e, 0xcfc5fd27, 0x9de243bd, 0x4bd28bbb, 0xddff6c49,
6144 0xa7814493, 0x604abd7c, 0x8ccbaef8, 0x4bd297de, 0xbe758f9d, 0x7339f9d6,
6145 0x5e37827e, 0xcec38ade, 0xf9a29dec, 0xfc050423, 0x01025db2, 0xe5de76bc,
6146 0x9b5fe435, 0x2bb93f4b, 0x6ea9e00b, 0xb676833e, 0x1e7e25ad, 0x225b06d4,
6147 0xf2eefbf3, 0x8d7c84af, 0x04a1529f, 0xbf73d8fd, 0x5aafd16b, 0x88534103,
6148 0xe6ead9eb, 0x79a7b9e0, 0xe201b236, 0xe65d52b0, 0xfbe02eb5, 0x53572be2,
6149 0xb32b1f78, 0x951f9d20, 0xbfdf8435, 0x2f8c1084, 0x077e4c48, 0xa3eb20ce,
6150 0xda357fcf, 0xb46d9b0a, 0x1b9b66df, 0x6af54ffb, 0xfdafc002, 0xc1127ff3,
6151 0x673ae99e, 0xe00e3a45, 0xddfe8ffe, 0xaf66369b, 0x6cf762dd, 0x9527fe05,
6152 0x9a1f2869, 0x48ad5137, 0x14a07385, 0x4fe271ef, 0xe29a5dba, 0xc28dbaa5,
6153 0xe0b4e293, 0x78f110be, 0x979eb754, 0x517bf840, 0x024240f2, 0x5d05bc81,
6154 0x422d0a9f, 0x7ff945c8, 0x0219cd8c, 0x92a5233f, 0x60829bce, 0x5fd63627,
6155 0x3e11d49b, 0x907986c7, 0x200b2f94, 0xde609df9, 0x415a2403, 0xd59ebaff,
6156 0x64aaf3f5, 0xd566fa82, 0x96a05283, 0x6a4eb3f6, 0x24fc43b7, 0xc116a3db,
6157 0xa48a7356, 0x41baf9e2, 0x1d1e4c95, 0x87278f39, 0xec2a15ed, 0xde25ffa3,
6158 0xef8e2f16, 0x8b757ce6, 0xe03efbdd, 0xf77f773b, 0x346b301e, 0x7b4f1b3b,
6159 0x79f686d9, 0x3b706f58, 0xbbaf84ac, 0xfb653e13, 0x397424c6, 0x71e863e6,
6160 0xa0deb37a, 0x08a6f072, 0x44a9f572, 0x87943cf0, 0x4f40affe, 0x1fd288c9,
6161 0x682c9d7c, 0xb68bd9ae, 0x2f6a389b, 0x57a4e3f0, 0x8c73ecf0, 0xc077191e,
6162 0x7ef00b5b, 0xe661fd57, 0x2a21d187, 0xa33e9c8f, 0xec173854, 0xfda1d70e,
6163 0x937d265f, 0x3fa63e56, 0xcf9cb5da, 0xe5d5f8cc, 0x79ef2cda, 0x56bdb42b,
6164 0x488035ec, 0x84438f30, 0x0e6a1c08, 0x2203a3e8, 0x855df7d8, 0x5c285f94,
6165 0x28ee411b, 0x0d9f26bf, 0xb37c095c, 0x3b0ae5b6, 0x5e77c7c8, 0xebf4423f,
6166 0x7fe3b8a8, 0x7681de88, 0x08983f96, 0xfbba5878, 0x423f5f2c, 0x5d30e748,
6167 0xc7447ca9, 0x37be7443, 0x172eb9f3, 0x394070b5, 0x009b9d87, 0x104288fa,
6168 0xeb256b09, 0xe8a760dc, 0xd86d75f6, 0x7cc64d9e, 0x366ee5ef, 0xdbacad5e,
6169 0xe60d9ae5, 0xd455dcbb, 0x2efb7cff, 0xffa8e7d5, 0x5d2f9512, 0x7fa3752d,
6170 0x214e7d56, 0x81efd481, 0x7a3a16af, 0x455f01ba, 0xf8b17ef6, 0xd472081a,
6171 0xf9cbffef, 0xcf9e6cdc, 0x3e646a3d, 0xc5f78893, 0x0a17aa76, 0x64cfacee,
6172 0xcade417c, 0x7e0be688, 0xf927b1de, 0x1be54f1e, 0x7918c7dc, 0x84f1c936,
6173 0x96c72a16, 0xe4d63958, 0x4827bc32, 0xbea0756b, 0x59f5cb33, 0x076aaf3e,
6174 0xa24dfbc3, 0x9f3067f7, 0x60f74b6a, 0x955cbbe0, 0xc0a74ea4, 0xe88b36e6,
6175 0x54b69007, 0xbb123ac3, 0xdc59fbbe, 0x7a07af8a, 0xa668529c, 0xb3e74d7c,
6176 0x0bbdeec9, 0xcdd6a5e4, 0x58384afc, 0xa3707604, 0x3c377bcd, 0x12d85077,
6177 0x88c75ce0, 0x838b3650, 0xd4720c84, 0x4c38dc93, 0x490c1172, 0xe9f93eb8,
6178 0xd08174fa, 0xf6c53c33, 0xd52f0664, 0x0c7f6016, 0xb06c202c, 0xf9f304a5,
6179 0xf3b2e606, 0xd8f303f8, 0xd84f59fd, 0x91b9bad9, 0xd97a07af, 0x075b2b68,
6180 0xe2259378, 0x777de6b7, 0x885401b8, 0x7bb26e0b, 0x6cfe831e, 0x479c1ea5,
6181 0x02689b96, 0x292ca3e5, 0x53fec028, 0x605562ca, 0xd6c240f1, 0x7f692813,
6182 0x42d5d359, 0x20b28f58, 0x07de0097, 0x9c8e263b, 0xefe5dab4, 0x8e6ac717,
6183 0xb95ba3b1, 0xe853ec1c, 0xb3a7537c, 0x3c70e43c, 0xf80f8286, 0x80dd74ed,
6184 0x9cfced93, 0x93f835e5, 0x7ecd9e19, 0xe60c1015, 0xddfaf125, 0x29ec910a,
6185 0x2df8f7e8, 0x86c59df0, 0x68838f7e, 0x078bd041, 0xce5ceced, 0x035b416a,
6186 0xdd48dff5, 0x40b7b836, 0x2607ebe7, 0xf449ab5f, 0xa729c495, 0xa517c173,
6187 0xf026fe7c, 0xd3e4e75b, 0x0ce157c3, 0x7e3307ba, 0xbc8688f3, 0xcd6e9d47,
6188 0x766e81b2, 0xeb447388, 0x7e829761, 0xa090a77b, 0xb9d39f81, 0x0a706050,
6189 0x2a179e36, 0x5c2fe319, 0xfdfae9cf, 0xe9bcd82b, 0x8ff1f307, 0x6c567bc6,
6190 0xd1e00d9a, 0x1b9f0fe1, 0x31eb9d32, 0xc8c9fb9f, 0x3263c709, 0x4cab4f31,
6191 0xc852bb81, 0xda0716e9, 0x4c89d555, 0xd0fccdae, 0x79c2941f, 0x7c50cbce,
6192 0xedf4097d, 0x8324d72f, 0xcb7fed1e, 0xafa044e1, 0x825d0f19, 0xd83ef47f,
6193 0x1c9bfab7, 0x2f5b7f77, 0x94063233, 0x91999d83, 0xfea58199, 0xc529debc,
6194 0x26a5ef8d, 0x6bb8cf7c, 0x46dbe580, 0x026a6bf1, 0xf7a4efed, 0x283c778d,
6195 0xf718ddee, 0xf8604fae, 0x3c7457ae, 0x672049aa, 0xc496ba91, 0xb32779ce,
6196 0x8cdc1c7b, 0xb67d6b9e, 0x7e8a4972, 0x467683cf, 0xf2b9e23f, 0x6b025046,
6197 0xf909b265, 0xf465c59a, 0xe8aa5c7c, 0x1992fd18, 0x8df5bf5c, 0xff7d872e,
6198 0x9c6484dc, 0xd3b5d9ef, 0x7274bc70, 0xc5387d97, 0x8b32fceb, 0x939af106,
6199 0x089eff73, 0x66e6ff47, 0x3c1015b5, 0x1ab35a62, 0x16ffaefc, 0x9409b9bd,
6200 0x54f5694e, 0x3e32a511, 0x74a3b900, 0x13f712b9, 0xe6e258e7, 0x604d8ddf,
6201 0x76a7f57e, 0x919b8e37, 0x22bcb831, 0x103eba3f, 0x23f3a4e9, 0x8accc395,
6202 0x61739131, 0x24a63f94, 0x2ea791c4, 0x7ec33499, 0xd30fae80, 0x7d75fe38,
6203 0x1a43cbac, 0xefec19c8, 0xa8fd5195, 0x7f2873d3, 0x90e31d35, 0xfcb427f8,
6204 0xf3b04bf9, 0xa114a713, 0xbff2a3be, 0x0465e506, 0xd076dfd3, 0xc7f151a7,
6205 0x0777d6ae, 0x87debec1, 0x05c679ff, 0x90ff3bfb, 0x3fa05dba, 0x4df2fd8f,
6206 0x7c11e417, 0x87164bf8, 0x1fe4d5b8, 0x9e981379, 0xcd94260f, 0xe6dd7982,
6207 0x378167fb, 0x0ac92f8a, 0x90b15fb6, 0xf3c6bb2e, 0xbcf3c683, 0xf3e6824b,
6208 0x77ec7ebb, 0x8e3f1489, 0xc3a708fe, 0x4af5c6c2, 0x7be30a96, 0x8f3d0217,
6209 0x58efff71, 0x4367bb13, 0xe36e6787, 0xa27c0568, 0xf958b47f, 0xcc9b76be,
6210 0x74cf05d6, 0x72f2a7d8, 0xdce199bc, 0xfd81cbb7, 0x44447bcd, 0x1d0e64bf,
6211 0xafd5056b, 0x679616de, 0xbcc79e6b, 0x3812d50f, 0x5eef3f2f, 0x785dfd01,
6212 0x9d7497ff, 0x07b8aef2, 0xf3ccb3f7, 0x603fdf34, 0xfba4b73e, 0xfd380b49,
6213 0xe517882b, 0xa20f262f, 0x9b3bed85, 0xf7a77ae3, 0xfe6038e7, 0x3f7025f7,
6214 0x838c80a3, 0xfbad877c, 0x2f9d2687, 0x9f83aacf, 0xf3c13ed7, 0x08f98f33,
6215 0x5412b396, 0xe5ba2e76, 0xabe012f5, 0xf05bcda5, 0xab6f96be, 0x1cb4966f,
6216 0x8931fc4f, 0x1f6a1de8, 0x21fe07ae, 0x3760c15e, 0x467f5d2e, 0xc32c7e61,
6217 0xf9fccdc3, 0xdc5f30cd, 0x72f76527, 0x3e58bcdc, 0xcb9f7d1b, 0x7cc609d3,
6218 0xf9f08eeb, 0x258f3673, 0x9f481f7c, 0x679f999f, 0x5e78b025, 0xd5f2c6c5,
6219 0x6b94e803, 0xe60e8f5b, 0xdf300ae7, 0x3317e75a, 0x65202c3f, 0x14429925,
6220 0x8d7e5bdd, 0xa9f4ea70, 0xe7c39ba8, 0xfbe0cfe3, 0xe710196f, 0xcc0f8de9,
6221 0xdb94eef4, 0x9a7c8307, 0xc3d9dde9, 0x09adf0f9, 0x50afdd6c, 0xffa0253d,
6222 0xd5b291e6, 0xe3bb28ee, 0xefb75498, 0x1b372017, 0xad46df19, 0x7b38cca7,
6223 0x79f5c645, 0x0fed4b99, 0x1d210cf7, 0xbdfec026, 0xe9ef0fd5, 0x79f11ce3,
6224 0xe01261b4, 0x13cb14b9, 0xd86d32be, 0xfcfb48b0, 0x4224cf47, 0x046bb53c,
6225 0xa74b78c1, 0xc7ef08cb, 0xf3c22209, 0x62c3a731, 0xef5feda9, 0xd8d9ce83,
6226 0x47097986, 0x9af1e6be, 0xf1a5adaf, 0xbe4ff9e6, 0x9f7e11fe, 0x6e5cadca,
6227 0x36e1ff74, 0x5b5bb74e, 0xdcf3bed8, 0x0f48e575, 0x0720fdf3, 0x16497704,
6228 0x1c1bcaed, 0xcdfd00ad, 0x5da799f4, 0x6bf41c71, 0xfdc89d0c, 0x98bd2f9c,
6229 0x2f51534f, 0x4cc27c62, 0x9b870abf, 0x35abcde5, 0xea2d6fe8, 0xe55dcf41,
6230 0xafae7a60, 0x63cf31f3, 0x7a80934e, 0x82ff0ccf, 0x0f572b8d, 0x367f3020,
6231 0x8479d8bf, 0xe19ea206, 0x55e7d4f3, 0x473c3441, 0xd38fb31a, 0xce89397e,
6232 0x72d85cab, 0x2ec1e63b, 0x2c27f3a5, 0x1bf183de, 0x5e1d7e1d, 0xc44a3cf3,
6233 0xf106d90e, 0x068215d6, 0xdef636fa, 0x5ee18f16, 0xbb0d39a8, 0x8efd0207,
6234 0x21abed48, 0x2fc47bfe, 0xf5d6ffa0, 0xb445c101, 0xfb808d6b, 0xafd23d5e,
6235 0xf4ede585, 0x051ac74c, 0x58aa39ee, 0xe3a5c427, 0x6d42fa82, 0x59de9458,
6236 0x1b52b818, 0x88378066, 0x1a8b1c79, 0xa7cf0dca, 0xb8fa8c38, 0x35237937,
6237 0x74d2f3f1, 0x4de5d2f9, 0x870abf97, 0x52ffe2ca, 0x36565f60, 0xd107e9e8,
6238 0xf67aa0cf, 0xc38b076a, 0x7d23703c, 0x67a3e965, 0x79fc710c, 0xe67d19e3,
6239 0x79f1d389, 0xc503eb4f, 0xcedf4183, 0xedf51872, 0x3e8f9df7, 0xf42e5d0f,
6240 0xc2e599f9, 0xfe3d7f8c, 0x1983a665, 0xd81700ff, 0x1d5a07fb, 0x9004bb81,
6241 0xbfa70677, 0x76708ed5, 0x70691466, 0x7c00e59e, 0xd2dcf540, 0xfd631fcc,
6242 0xb96cb126, 0xee34fd03, 0xf3f16907, 0x0ff6c26d, 0xfec463b7, 0x1e301196,
6243 0xc8341311, 0x2cb3170b, 0xbce95b35, 0x1cb421c4, 0x9ac1e905, 0xeb9fe708,
6244 0xe1132f8a, 0x7e5a86de, 0xc2d6ba3e, 0xfde96dce, 0x75b071ad, 0x39772f49,
6245 0x683b56ca, 0x6b5f27ff, 0x78b0702b, 0x3819fa2f, 0x93ee114f, 0xd8317ea4,
6246 0xcc132fb3, 0x234bcd4f, 0x0ebe817b, 0xf20f19e2, 0x85238cfd, 0xfb655f9f,
6247 0x0b2ff46c, 0x796acd4a, 0xf908d55e, 0xa6077dfd, 0x5a703dc1, 0x6ccee592,
6248 0xf1c27f5a, 0x5967ab3a, 0xa9bb64ce, 0x8378edff, 0xce5a47d5, 0xa7f5a50c,
6249 0x3ab26f1c, 0x0551086c, 0xade3b4f3, 0x3051fe69, 0x3fdf9b8e, 0xf20919e0,
6250 0x5f985920, 0x3051ed2b, 0xa3efacfe, 0x2c06a2af, 0x00cfaff8, 0xba9f82ff,
6251 0x0e4fe8b2, 0x7915ef88, 0xbf1fd854, 0xfdb6821f, 0xe3a97bbe, 0xf0587455,
6252 0x01280a5e, 0x3e385bff, 0x2690ba75, 0x23c848cf, 0x48cf4124, 0xe5d877d8,
6253 0xdd0136f0, 0x5db40ff3, 0xf4d47206, 0xf00bdfc6, 0xac21ccfe, 0x28ca7c9f,
6254 0xc9e6df70, 0x8fad0617, 0xe5dbbfde, 0xf401dc28, 0x3b4064a1, 0xe4dd5041,
6255 0xd4176a66, 0xc95e3f52, 0x68c47f01, 0x7e713787, 0x6ca12d7b, 0xc0d9f237,
6256 0x8e1fd310, 0x8fd0bdb2, 0x2da4572e, 0xa77c4fa5, 0x4110aee4, 0x3564a63f,
6257 0x720b9c1f, 0x9cecdff8, 0x60f1e0ac, 0xf0e6dbfe, 0x3f6c20fd, 0xe9fb01dd,
6258 0x9235afa0, 0x71e74fe1, 0x238f1605, 0xfe510569, 0xfd079f05, 0x37dc2a7e,
6259 0xf6c1ce32, 0x44bce95b, 0x13461f58, 0x887ccb15, 0x6a00e413, 0x49df58bd,
6260 0x417f0782, 0xcec87ffb, 0x035b74fc, 0x2c5dc431, 0x5f7eb64e, 0x7dd992e8,
6261 0x5af0722d, 0xa709e3d0, 0x78f41b88, 0x848ae3d7, 0xfb9218f9, 0xb09fb847,
6262 0xde0042cf, 0x1b80e4a7, 0x17ddd9e2, 0x1206ea49, 0xd38bafe9, 0x21f7ef5b,
6263 0xe208bd45, 0xcc5ca31d, 0x90aa78be, 0xf768fe60, 0xfb002571, 0xb659294c,
6264 0xfabf689a, 0xef7b072b, 0xcfa2a4d6, 0xd6c11e81, 0x8fe30204, 0x440d45db,
6265 0x353f874a, 0x1f81d9e6, 0x288e0336, 0xeeac521e, 0x94bfa03b, 0x6cde1433,
6266 0xfc41ee7c, 0x24e8ea4a, 0x5789df8a, 0xbfb85539, 0xf07b29e1, 0x7b9fcc2a,
6267 0x24f782d6, 0x72b4566d, 0xad3e6fa8, 0xf35e21ba, 0x01307654, 0x05acf3e7,
6268 0xa139b3e7, 0x1465e2fb, 0x608d5fee, 0x20e4bf7e, 0xe4052d92, 0x83bd48a8,
6269 0x32704f3e, 0xc2cab87d, 0x938a68e4, 0x0243cfc9, 0xde0f3f1d, 0xd1f9442b,
6270 0xbaba1bf3, 0x7e8879d9, 0xc089b7d7, 0xbae509c7, 0xc1121e3f, 0x465c9e8f,
6271 0xec9cfd70, 0x3a2a0394, 0x1ce71e9f, 0x08cbff4a, 0xfb2e1f5b, 0x5fc63160,
6272 0x82de0529, 0xebd80bdf, 0xf052f7e4, 0x39cb987d, 0xed214c9f, 0x53e7ac22,
6273 0x442d11ce, 0x9cfcbbc7, 0x9f3d7714, 0x527dfbc6, 0x7d125220, 0x2aacf0af,
6274 0x1215df01, 0xad3b7ae3, 0xc438e4be, 0xa66d8b7b, 0x235eb0e7, 0xf4091e3c,
6275 0xb1b734d7, 0xaf93a47d, 0xe0c9834f, 0x3d1abce8, 0x1c4d3e6e, 0x0bda28f5,
6276 0x78068aa5, 0xbcf4e2d9, 0x7e44fb0b, 0x2f9e26ea, 0x8fa4f33e, 0x388d3fe5,
6277 0x72f18097, 0xe04e9fca, 0xebeb8b8b, 0xef3a76fc, 0xfeb1878b, 0xaf410f81,
6278 0x5a78f85c, 0xf7f9e82a, 0x4bd1beb9, 0xbf80ef9d, 0xbf8c49dc, 0xe44697dc,
6279 0xc49214b3, 0x0de446c6, 0xd9fa0ef8, 0x8a6e0729, 0xa92f7e7b, 0x0fd9d4a8,
6280 0x4ed041e6, 0x36d32fbe, 0x1f4ce41b, 0xe32701e7, 0x7ab9736b, 0x10ddb2e5,
6281 0xce7ff707, 0x03a98bd6, 0x5a1e61ce, 0x62488fd8, 0xd6ad567c, 0xf203375d,
6282 0xc6329c62, 0xf9f9d3bb, 0xc97e68ab, 0x9d17e28c, 0xcc9d3aef, 0xa7f9d68f,
6283 0x989bc778, 0x39fc5fdf, 0x126cee21, 0xfe7507b6, 0xf8cfccb9, 0x6cfdb2f0,
6284 0x7f8de89d, 0xa9eedd3c, 0xf8631ea0, 0x9be33f66, 0xf81fca22, 0xf03d10fb,
6285 0x966f998f, 0x5f37caf5, 0x967e0227, 0x779f16b7, 0x67d9a59f, 0x973393cc,
6286 0xf3f11c13, 0x624d9f28, 0xa943b1fc, 0xe82e51fb, 0x1a2dab8b, 0x15ca03e8,
6287 0x3e52d759, 0xdfa091df, 0x03935a7b, 0xd3122df5, 0xac5a5b3f, 0x38b67fa8,
6288 0x678c5ebd, 0x68f3b065, 0x43b6f244, 0xc036b41e, 0xf3df46a6, 0x8d93a57c,
6289 0x13439413, 0xf41d828e, 0xf1ff4617, 0x8dc1e757, 0x82b32430, 0x31cc61d1,
6290 0x0d98bd65, 0x8f853be9, 0x00bd7f00, 0x577e833a, 0x73c1587d, 0x2b0f4bfe,
6291 0xd85f17a8, 0xc4097af5, 0xcb7cf48d, 0x2f5f3b71, 0xef051a29, 0x9c7b3e33,
6292 0x8ebd63eb, 0x27a0e7a9, 0x4ea6f74d, 0x997f4c20, 0x032d3def, 0xb48dc9fe,
6293 0x9d03ef9b, 0xd61e4545, 0xb5db6b9d, 0xcc16a069, 0x0ace81f7, 0xfff6855d,
6294 0x699e83cc, 0x7dce352e, 0x6e1f9ca0, 0xc1db6d20, 0x4fdf3525, 0x6de7d749,
6295 0xaf93ff30, 0x2f881484, 0x919a9506, 0x9aeebeec, 0xba3fd01c, 0xc51fe1dc,
6296 0x11c3f05b, 0xbf68fb86, 0x5fbef3e4, 0x08bdd893, 0xbfee0aed, 0xefb09afc,
6297 0x7add7c82, 0xdde2c9d3, 0xbb9fcb79, 0x7e61f409, 0xb9f707a5, 0x9f98934a,
6298 0xb2121bfc, 0x34bd00e5, 0x41c8e309, 0x2a3e2d59, 0x5223de44, 0x0f3808d9,
6299 0x425fb3b5, 0xb9af8c3e, 0xc138efbc, 0xf7ba90ae, 0x26e377c3, 0xde83e5e6,
6300 0x955e8e76, 0x0e98eb0a, 0x74ab8537, 0x87023393, 0xbe5ed70e, 0x39ae68ce,
6301 0xe1fcc0ef, 0xcd43d03b, 0xe0d88e87, 0x820f9d7b, 0xfd18a7ad, 0xe801f8a3,
6302 0xe107e11f, 0x78eba836, 0x87e707f8, 0xfc6dff2f, 0xf159fd40, 0xfe00fc3c,
6303 0xe2f7e260, 0xe689ff87, 0xfdaf6a07, 0xaf6519d3, 0xa7961505, 0x3e75d7a5,
6304 0xc428e458, 0x608534f7, 0x65d905be, 0xe2dfbf67, 0xf038c64d, 0x46366ef3,
6305 0x064787d7, 0x76e22f83, 0xe37930a5, 0x0e8f5df7, 0x8e576809, 0x66e10aa6,
6306 0xa206e3b4, 0xbe38d43e, 0x804111c8, 0x1730ac7b, 0xcbec0b37, 0xc5c82a50,
6307 0x10f4eb68, 0xc756fff0, 0x1f605965, 0xe72639e6, 0x1f6d7f00, 0x5815fcb1,
6308 0xa80fb6b2, 0x1aa37e7c, 0xbd749fb1, 0xab7797b7, 0xc5c43f8f, 0x0f72e1f8,
6309 0x7a014f3b, 0x5d0e1a3b, 0x005903ff, 0xcb34210e, 0xf5038df2, 0xe83b4b75,
6310 0xe2838073, 0x9a40b775, 0xb4283ec0, 0xc18ad278, 0x9217ebce, 0xd6aece00,
6311 0xbc43072f, 0x9fcb7a68, 0xd3bc020f, 0xcd267df5, 0xb664cfb8, 0x477b75a3,
6312 0x7b742bf7, 0xd088a248, 0xb76826ed, 0xb86ee7f0, 0xafd61b1f, 0x71cf0d90,
6313 0xbd5a743e, 0x57e5c3c8, 0xce98f3a2, 0x690d71e7, 0xd7c8b843, 0x99337cdf,
6314 0xc70667d2, 0x24fdf4c7, 0xed0b9094, 0xf14d5c84, 0xfc44b570, 0xab9c7449,
6315 0x1c7c8135, 0x8cd727c5, 0xefe1d637, 0x3f48f4b2, 0x5e6fbdbd, 0xe299261f,
6316 0xdcb7dff1, 0xabe763ef, 0xe763eaff, 0x150e2767, 0xa82c12fd, 0xb9d933e3,
6317 0xc3c33759, 0x7afe257e, 0xc98b88f5, 0x7b4b44f1, 0xdc1b9c2e, 0x5c2bf3bd,
6318 0xfcecf71f, 0x13b01dea, 0x08971c27, 0x3c4e01e4, 0xf709263e, 0xe067c73d,
6319 0x6fde9d3e, 0x0e4da7f5, 0xff239ec2, 0xef82f7e8, 0x1478f0a3, 0xe586cf80,
6320 0x3d0f1d8b, 0x3d9dfd0c, 0x3ce8912c, 0x3bc512f3, 0x2569e20c, 0x7df87efc,
6321 0xf497b302, 0x5efc7df6, 0x5972ffe6, 0x9b6b7ef8, 0x625efdc4, 0xd5f3a28d,
6322 0xe524f354, 0xf57ae845, 0x52e3d2b1, 0xe07d2c6e, 0x0f9d63ef, 0xdc6793cf,
6323 0x579fa95b, 0x23f8e3ae, 0xf3c3df7b, 0xdd345700, 0x7e7d8121, 0x3c488645,
6324 0xa95ee351, 0x2a3e0f52, 0x8b8f71ee, 0x76eae5e7, 0x1fa7deca, 0xf706919e,
6325 0x7a988859, 0xe5b2dd55, 0xb7a85c95, 0x71cf7189, 0x457bf19b, 0xf0121dcb,
6326 0x262e17ff, 0x3f8dbd1f, 0x27ca62f1, 0x09dd0297, 0x040af3b3, 0x7d332394,
6327 0x7dfcecf7, 0x9ea8fb6a, 0xfd13ddf1, 0xb17874cd, 0x2ff708a3, 0x9987a37a,
6328 0x79d1776f, 0x42fce9fa, 0x6a7e9e74, 0xb9f1ed8f, 0x2f92feb1, 0xbf3aeb03,
6329 0x913eb756, 0xce9cf60a, 0x1952d3a7, 0xf1d84cdf, 0x46712a70, 0xdbc665e8,
6330 0x66fd395f, 0x0ce66d11, 0x826dcffa, 0xe17d42e6, 0xcf906d27, 0x9c61c652,
6331 0xda0956f5, 0xcfe7841f, 0x59b1d79b, 0xd7bc28e2, 0xd97bd7ba, 0xa0ca1587,
6332 0x15ebcd6e, 0x7c0e17dc, 0x4aa75e6d, 0x7049d40f, 0xb48958ad, 0x6e31e99c,
6333 0x9970eba7, 0x2936fce9, 0x04f479c3, 0xcc0f99a7, 0xb9f6eaf0, 0xc5394f7e,
6334 0xda14b4c7, 0x216ab5df, 0x1d662fce, 0x69e978e6, 0x5e69edfd, 0x7ffc4d47,
6335 0xd7d4d8e6, 0xc93dbd00, 0xe66e999b, 0x947f5d76, 0x587900c0, 0xf91ec1fa,
6336 0xf48e95c2, 0x10a7392d, 0x0f1bec0f, 0xa24f93b4, 0x7d3221d6, 0x9ddbf208,
6337 0x27acf66e, 0xce7a5b7e, 0x11a9bc42, 0x1f9b93be, 0xeddf0074, 0xb01cea90,
6338 0x59c533af, 0xf1449b5e, 0xa2d3f535, 0x74bcf1eb, 0xc84085bb, 0xa9cb5a6c,
6339 0xa84710bd, 0x9f30483e, 0x7765a8ba, 0x4be9f031, 0x51fa1b52, 0x7909675d,
6340 0x6cceca30, 0x8075a96e, 0xc69cd61d, 0x4bed03ce, 0xcdbc8626, 0xbf191247,
6341 0x3d3e1f36, 0xfda713c3, 0x8ebf6f00, 0x7172d278, 0xfc61765d, 0x058d64a3,
6342 0xd0553fe7, 0xbb034e5e, 0x0f7646e5, 0xb8eb5763, 0xbc28d397, 0xa324b79d,
6343 0x7cd6999e, 0x4a6e1dcf, 0xf33fe088, 0x1cf779f1, 0xdf40db41, 0xac35512b,
6344 0xe3645497, 0x7fb8f8be, 0x1d375ea5, 0xd194afda, 0x2e2699bf, 0x751e2096,
6345 0x03c84332, 0xd0a7717f, 0xa77e12be, 0xc6ce5fcd, 0x2a7f6e21, 0x4c6f9ff8,
6346 0xbf8d1d4f, 0xf5eaa26d, 0x6bf7f00b, 0x5b4fc988, 0x6eccedbe, 0x3e5f6d2b,
6347 0xc77cc053, 0xe22cee69, 0x929fe28f, 0xf99e9435, 0xfa5b2f94, 0x5f5f0117,
6348 0x673c6a57, 0x41ccb335, 0x63f1d102, 0xc2c32dc1, 0xb5e78fb3, 0x7efc0b76,
6349 0x57e72e59, 0x359f7e71, 0x5df0d53b, 0x66766139, 0xdd9136f5, 0x7ec85257,
6350 0xaf975127, 0xbc39711f, 0x37c7fb8a, 0x700cb37a, 0x0d28874c, 0x693334fd,
6351 0xd75dda28, 0xe5c76d9c, 0xe0fc5cb9, 0x78e89bad, 0xf2611a3f, 0xabc5c56b,
6352 0xd8322f90, 0xc84cca7e, 0x6f41122e, 0x66bbdf1a, 0x471eb1bc, 0x27abcf8e,
6353 0xb3307d74, 0x9bfdc455, 0xcf148599, 0xd3b18902, 0x18beadbf, 0x865ed167,
6354 0xe7b5d078, 0x04bbf83c, 0x83e2fa31, 0x2fa4efd2, 0x3832a05e, 0xd2f5ca9e,
6355 0x0fdfee44, 0x6f408322, 0x1f1b134c, 0xa2ea3e06, 0x0e35a6eb, 0x8eebe91f,
6356 0x5097efee, 0x21be0639, 0x8f18691d, 0x032e769d, 0x7f7449f3, 0xa847ac3f,
6357 0xb1c5a25d, 0xcc4bee97, 0x1307dc31, 0x76512bd6, 0xfdf05c89, 0xd46992ed,
6358 0x00f2551e, 0x9fc481be, 0xe30cfa8f, 0x70902592, 0x8cc1f102, 0xa9e71853,
6359 0x8affa896, 0x4c13f3eb, 0x097fd1cf, 0x30f91129, 0x9c7a2bdb, 0xdba49ad9,
6360 0x093e4653, 0x97af1bc7, 0xf3a3ee31, 0x13e00949, 0x117affe4, 0xf1bd3ae3,
6361 0x6f7e3e8d, 0xfaa212fc, 0x0f384928, 0xfbf970bf, 0xbcf2fcb6, 0xc8c327ce,
6362 0x89f0beb0, 0xbf3a1fce, 0xa609d8c4, 0xeb4f5078, 0xe9894bcd, 0xd69edf88,
6363 0xc847979b, 0xb37bd7a8, 0x3126766b, 0x744aee3d, 0x5d577f63, 0x7609d334,
6364 0x11eb958d, 0xc70add7d, 0x9f19eab5, 0x573edcbc, 0x6aa3fd82, 0x11d91fd0,
6365 0x60f1e83a, 0xae972f9d, 0x9cff1821, 0x6756f5ce, 0x56078b2b, 0x7003154f,
6366 0xe5b8a284, 0x9d5987c1, 0xd3a2cbdd, 0x27ce6af7, 0x096ed285, 0x1af3777e,
6367 0xbe20d04d, 0xc4f1e1e4, 0x8094e719, 0xafab1d9a, 0xc75fba74, 0x0bbf07bf,
6368 0x23c6bfde, 0x1c4ba804, 0x3baecfa3, 0x188aecc7, 0xcfbc2a7b, 0x891e62ab,
6369 0xeb4e5f99, 0x86421f74, 0x0aed3bfc, 0x76fce921, 0x6f7dfe85, 0x1e064e74,
6370 0x65ee7a06, 0x1d80aef7, 0xe2be740f, 0x3afd849c, 0xccf18c93, 0xbf791db3,
6371 0xbf93df41, 0xcdafbe6f, 0xc6de9f3c, 0x17f746ff, 0x8fa0ffb8, 0xcec4957b,
6372 0x27d79bc7, 0xd75e9c7d, 0x99bdfe23, 0xe293c37e, 0x3eba7ddb, 0xd73fc18e,
6373 0xafd13dd7, 0xebad7d37, 0xbeb77fc5, 0xd7d7fbd6, 0xb35c7d13, 0x8fc9ef1e,
6374 0xeaf2f5d4, 0xdf8c16f5, 0xfafee14c, 0x9e2f1e14, 0x6ce2c499, 0xeedeb8b3,
6375 0x0166dcfa, 0xb3282ebb, 0x6eff30fd, 0x36a1c627, 0xd0f662ef, 0x724e3c9b,
6376 0x9c6220b7, 0x16b1eee4, 0x17d4dbd4, 0x4b7987ca, 0x808c8445, 0x2c01dcfd,
6377 0x8528df4e, 0x6bef50ca, 0x6f738112, 0xefdfeaaf, 0xfd04dff1, 0x70f1fddf,
6378 0xa3c62d4b, 0xc7e06d43, 0x7093cb8f, 0xaad92c5f, 0xb3bafc62, 0x03f78ad5,
6379 0xd9f8ed75, 0xf9fa196e, 0x5ae0689c, 0x0d6ad4be, 0x1e814bef, 0x101e2699,
6380 0xaba33f21, 0x59fde09b, 0x8a876793, 0x429b3fc1, 0x0e216ada, 0xf9615130,
6381 0x3d3c66e8, 0xcc31f7ca, 0x7de114fb, 0x9f665689, 0x7644bb15, 0xfb4f580f,
6382 0xe60acd12, 0x2fb6f757, 0xa0967851, 0x2fb3169d, 0xd2f4ccd1, 0x9897ddb7,
6383 0xdf87b808, 0x9ff9d367, 0xc3d227eb, 0x8566c4fe, 0xbf7567ed, 0xbfb0132e,
6384 0xb8b4b1c9, 0xf6dea371, 0x4aec7629, 0x1d3dc0f0, 0x4deff99b, 0xc035d8ec,
6385 0xfcf6e6a3, 0x777b6e7e, 0xcda4a811, 0x984ad78d, 0xb9e3c6f7, 0x19a0b8e1,
6386 0x66ff1caf, 0xc8156e7c, 0x07c4072a, 0xe0a9b45b, 0xbfb8f517, 0x71c1edd3,
6387 0x5d478afa, 0x491f364e, 0x6f9f00f0, 0x03c0323e, 0xfc003fe3, 0xab59710a,
6388 0x93f015fb, 0x9d3e1c77, 0x8abcfb80, 0xa4bf0547, 0xb1a6d93b, 0xef8c8973,
6389 0x03c39983, 0x9abd0fb0, 0x84e6f9f3, 0x4c8ebfee, 0x61afde8b, 0x39fa33fb,
6390 0x60855aff, 0xc2df883e, 0x78cc41f2, 0xeb66e41b, 0xebc4e6b5, 0xa69c89c3,
6391 0x35f2f18a, 0x7f9662b5, 0x807e7e60, 0xf03977f3, 0x7147ed01, 0x8956b833,
6392 0xaeff8465, 0xcef58128, 0xbfe5af5c, 0xc67b4387, 0x1cd565df, 0xed2a3396,
6393 0x67d278e3, 0x40efc057, 0x3b96f96b, 0x2f70dc73, 0xf2ca5083, 0xb2f92c3c,
6394 0xc493c846, 0xd6953a52, 0x0ecb922b, 0xb883f526, 0xe40d73b1, 0x479e4333,
6395 0x2f445a5e, 0x0ad747dc, 0x2e245e5b, 0xbf12b0eb, 0x3d70ec1d, 0x79e79fcf,
6396 0xfbebb52c, 0x3eecedd1, 0x86fe8aea, 0x850e4e73, 0xbfbf477e, 0x9a3deade,
6397 0xa14cf984, 0x7dd29544, 0x78698ef9, 0x76e2907f, 0x3e477ce3, 0xf803293f,
6398 0xd9f5c281, 0xff5c31ff, 0xc82e0f1b, 0x3a71816f, 0x062c8eb6, 0x087231fd,
6399 0xd08b599c, 0x7c41aa87, 0xbc120f6e, 0x01fff12f, 0x512809c2, 0x00008000,
6400 0x00088b1f, 0x00000000, 0x5bb5ff00, 0xd554740d, 0x79bfff9d, 0xbe4cdef3,
6401 0x21264cdf, 0x012f0842, 0x1c424242, 0x61f08062, 0xc4443e1d, 0x602a0320,
6402 0x43e196eb, 0x9a1af909, 0x7ab76eba, 0x2904930e, 0xb693db02, 0xb654e56e,
6403 0x28bb560e, 0x82609d89, 0x04ec2681, 0x6eb50314, 0x5b604040, 0x6a445477,
6404 0xbb8d3243, 0xb29eec54, 0xf7bdffff, 0x60c33325, 0x392dd9e9, 0xddf73739,
6405 0x7ffdeefb, 0xf75ffefc, 0x595c003e, 0xc9a00392, 0xe7b73aa6, 0x001aa802,
6406 0x6dbcdc64, 0xa0556052, 0x324e4018, 0x63240a6d, 0xd4da669b, 0x668a6d86,
6407 0x9aa9e362, 0x70805ace, 0x6c14b2ce, 0xf2ce70b4, 0xc6efbc29, 0xc34b9656,
6408 0xfdec32c1, 0x45f38a5d, 0xe1d90a9c, 0xfec49e0f, 0x39148ffb, 0x42ff63b7,
6409 0xa4096a62, 0xe7f2ac01, 0x3fb08535, 0x1b1fe2d5, 0x69ceba44, 0x1a6d2c9e,
6410 0xfe2dd7c0, 0x7be32089, 0x68529bc9, 0xf005c97d, 0xbab63b1d, 0x22948f06,
6411 0xd5d02e7d, 0x60a300f1, 0x08a976b7, 0xeb82a900, 0x05f6f1e9, 0x58074c2b,
6412 0x8eff1339, 0xf19217d8, 0x53d22679, 0x741b9fce, 0xb405fee0, 0x30cf41bf,
6413 0x5dad901d, 0xeff6024a, 0x96eff63a, 0x8fb81851, 0xdf9313f7, 0xbf8b6122,
6414 0xa2fd7fd4, 0xbfc3efc9, 0xdb9f6807, 0x792bb669, 0xc43674cd, 0xebf999f6,
6415 0xeb119946, 0x3e7c1fc3, 0x65092f8d, 0x9015d59d, 0xf33efd8a, 0xd8ab2147,
6416 0xf4677f07, 0xe327e67a, 0x45ce337b, 0x8175c73f, 0xd62d9fe8, 0x0cbf072d,
6417 0xa1998f28, 0x61b379e8, 0x5c641fe7, 0xe8e5f677, 0x14b40be7, 0x3467e307,
6418 0xf8cebe8c, 0xbd70aa43, 0x6f5f2b7a, 0x34bc9de8, 0xcd9bfd40, 0xbb945328,
6419 0x8e50cbaa, 0x77fa75ed, 0x66fb4017, 0x700f979c, 0xb595b360, 0xeb6b4e53,
6420 0xcdcefe88, 0xe0152008, 0xd62ce6d0, 0x98c69aaa, 0x561a729c, 0x3ec44943,
6421 0x90c7df1a, 0x2e39d0e3, 0x82a1a9c7, 0x5f60e6e7, 0xafc055e9, 0x4b39f08f,
6422 0xb80869c8, 0x9534879c, 0xf1fa79c9, 0xc411dd9f, 0x132c9647, 0x25fc11e8,
6423 0x17a089e8, 0x0a93f48c, 0xd97d51ec, 0xd5cf8fd0, 0xdfeb8597, 0x714fd621,
6424 0x075a8e8e, 0xa113f8fc, 0x85f643bf, 0x71f212bd, 0x05657247, 0x9e5693f1,
6425 0xd96eb517, 0x427ab13b, 0xd3cbe1c1, 0x209fc890, 0xc69fa69e, 0x33f988f1,
6426 0x00923e1c, 0xfa26ff94, 0x4cb34039, 0x62eb3476, 0x6f27f3f4, 0xc99bb7a6,
6427 0x9b9e4a13, 0xe5ebf8e3, 0xcb457369, 0xb4517d33, 0xd1dc333c, 0x2ab51cf2,
6428 0x79b76e5a, 0xa632e5a2, 0xf8d47272, 0x51a54dd8, 0x99df71fd, 0xd73f3515,
6429 0x3faa2f37, 0xa8e2db7e, 0x979b13f9, 0xed27f547, 0xfcd47afa, 0xa8daff42,
6430 0x55bda2f1, 0x29ffa4b7, 0x79a8fa81, 0x57d35e24, 0xcef6ffe8, 0xf3ed46ef,
6431 0x2fffd6b7, 0x9c7ff463, 0xd234d97c, 0xf447fa17, 0xf24a838b, 0xd99f0936,
6432 0x93f25690, 0xafb7aeb6, 0xbe976849, 0xe88fba79, 0x67062df0, 0x2b3d8e13,
6433 0x6bf225bb, 0x26d45063, 0x4c5b1bf4, 0xfefe4950, 0x6ad326fb, 0x9d88f277,
6434 0xb624d71f, 0x982af3fe, 0xf3d1ec13, 0xcc8f1796, 0x14d3da33, 0xf88da61f,
6435 0xf45bafd9, 0x3df210a6, 0x147ee655, 0xf269ebfd, 0xa7a417af, 0x8a997214,
6436 0x8a78a7c3, 0xed59bc59, 0x0e06d6c6, 0xb4db1ea9, 0x5faebf11, 0x505ce547,
6437 0x98ff2ffd, 0x3b213fe8, 0xdffa465f, 0x86dc8125, 0x89bb56bf, 0xc361f3ec,
6438 0x9a7ae96f, 0x21ae822d, 0x048fa5e4, 0xd0d3d66c, 0xfad0c3e7, 0x9dafccf1,
6439 0x4805a6ff, 0xce55e7ff, 0xb2ff318f, 0x099f6bf0, 0xfe4fd6bf, 0xbc647f2c,
6440 0x528fcf72, 0x7ce75c74, 0x440a2c01, 0xe42c29c8, 0x58d06604, 0x75cd99bc,
6441 0x876aa176, 0xbfae18f2, 0x44d87df2, 0x13fcacfb, 0xef7c8a6c, 0xdec29acf,
6442 0xb326b3fb, 0x59360576, 0x1815e728, 0xaca56ccb, 0x5db0941f, 0xe40a0bda,
6443 0xe4f32c01, 0xf794242a, 0x03a679c0, 0xa292b4b7, 0xc107bdf1, 0x3fff90ad,
6444 0x14dacdfb, 0xcebc379a, 0x4fdd4fdb, 0x8a815d38, 0x7dff61b6, 0x44c94f9b,
6445 0x53be107f, 0xf711f162, 0xf773d2b1, 0xa69e6323, 0x3c167338, 0xbea0ce57,
6446 0xad938396, 0x600bac67, 0x1733f28f, 0xe3a60854, 0x160bbe3a, 0x4748cbff,
6447 0x4561b23d, 0x8f77d4fd, 0xb0647e62, 0x3fad8fea, 0xc7ab79c6, 0x9c52c684,
6448 0xa7f550be, 0xc3f3d27c, 0x20afd0bb, 0x3d124b6f, 0x118cb619, 0xff5f9c39,
6449 0x638d0a79, 0x867a65bc, 0xcbe7167d, 0xd8fb7e4c, 0x71bcc67b, 0x6da3b9b6,
6450 0x5c72e724, 0xf88de664, 0xb00a5a33, 0xa9549f94, 0x177e9ffe, 0x0a1384e9,
6451 0xcbc0cf5b, 0xfa978146, 0x24547d5c, 0x8653ea5e, 0xf08a32f1, 0xccb2ff52,
6452 0x3bbea6ec, 0x97280fc1, 0xde770233, 0xfb5ed77d, 0x9e1d4eae, 0xb88c7cef,
6453 0x9f2711d1, 0x8c746e20, 0x6e229f7b, 0xd90dffa8, 0xfde8953d, 0xa9c7e778,
6454 0xc1f75a1e, 0x507ba35b, 0x06fd9f0a, 0xc738f7c9, 0x9d0c10fb, 0xbdba7e65,
6455 0x1d21f750, 0x3b5c0ff3, 0x5d5cf94b, 0x60b745bb, 0x742d8aff, 0x7f9a79ec,
6456 0x5f9a0250, 0x4e604c17, 0xf25daeab, 0x5578e027, 0x31d6db67, 0x596aafd8,
6457 0xc3614656, 0xbbc10a9b, 0xe4bf7c68, 0x4bf1c46f, 0x1725839b, 0x87bae027,
6458 0x75a25dae, 0x75f10e07, 0xe60e6f2f, 0xb0300e53, 0xb407cd7f, 0x05bb4d5e,
6459 0xb1bf2812, 0xb431d505, 0xa0149b5f, 0x3f032afd, 0xcafd6950, 0xa04d9697,
6460 0x6f7aa6f4, 0x1109c4cf, 0xc0e06b7e, 0x39475549, 0x60ffb655, 0xc65798a1,
6461 0xe19f97c3, 0xa37fe0d7, 0x1cdf27bf, 0x6ff13fe9, 0xf093d91f, 0xf216bfbf,
6462 0xbe35d55f, 0x7e89c489, 0x8979e3a5, 0x84d595f9, 0x5b870ba7, 0xda4bfb7f,
6463 0x4ebfe0ef, 0xd940dc24, 0xdc1bc9ad, 0xeb17163e, 0xf9703ec4, 0x429dd53d,
6464 0x452e53f2, 0xff3e73fb, 0x435dcd90, 0x2a9861fb, 0xc48444d8, 0xd0db87e4,
6465 0x93e4801e, 0x43ecc89b, 0x6bab0e4e, 0xd1ef9e90, 0xacc7a404, 0xd8b5d585,
6466 0xf31766df, 0x97feacf2, 0xafa46f73, 0xf26666c3, 0x2781e6b1, 0xed186fd2,
6467 0x3a471a7e, 0xa67de68e, 0x4ebc7086, 0x6e12acbf, 0x53bf82eb, 0xdbdfa475,
6468 0x5742e1f9, 0x3602f79c, 0x9314afee, 0xd94f72bb, 0x4bd47d88, 0xf089218d,
6469 0xce92707e, 0x2f9b58f2, 0x48ebe8c4, 0xf98f89d0, 0x3d377e07, 0xefdeb114,
6470 0x26131f11, 0x7eebf48c, 0x428961f1, 0xc3fd7b72, 0xc8ca7312, 0xe4cc81f3,
6471 0x3a5c7f4a, 0x3a78bc78, 0xf6997dd5, 0xd1603dad, 0x13be191b, 0x77c2419c,
6472 0x3d139257, 0x6d5be135, 0xf7c48b2c, 0xbaee8cc3, 0x4889d92e, 0x65ceba87,
6473 0x3f36069e, 0x906a49c5, 0x08fae73b, 0x66e6b267, 0xc1ff8478, 0xa54710fd,
6474 0xa3fa37f4, 0xcfcf3695, 0xe4e67f49, 0xbc48c4e0, 0x394299d5, 0xcfe9128d,
6475 0xc2373cd3, 0x9f64e4fe, 0x7920e8de, 0x7d653ba6, 0x898a7f44, 0x0f4065eb,
6476 0x8e29daa5, 0x50f5c66d, 0xdfc1031e, 0xb7fc92a5, 0x92b3ae76, 0xa6c77fdd,
6477 0x55593d31, 0xff61ae9f, 0xbe47d4db, 0x4aeea9b7, 0x996dabb2, 0x0d764089,
6478 0xef8676d9, 0x01d784bf, 0xbd5457b2, 0xb8a01e02, 0x36f0203a, 0xff981630,
6479 0x708fdca5, 0x37be5326, 0xa3c8cc9e, 0x676f3cd1, 0x08c5c94f, 0xae0e077e,
6480 0x4a7d1274, 0x321f7f22, 0xf7635e39, 0xc3814ffd, 0x9b6b4da7, 0xe1c446e7,
6481 0x15bf79d8, 0x00e43478, 0xab165f66, 0x8cf13107, 0xdb3adf87, 0x1fe433bc,
6482 0x0bbbb69f, 0x899b0fc8, 0xaea3c230, 0xe703a5c6, 0xcde907ff, 0xc85c7f98,
6483 0x1a3c5555, 0x214df5c9, 0x33754557, 0xeb61a339, 0xfcc3c764, 0xed71a9e5,
6484 0xdfc10bec, 0xbd68dcb6, 0x2abbcec7, 0xbe4c53f8, 0xe744b5ac, 0xcdd99961,
6485 0xfa661ea0, 0x060de637, 0x77fd71af, 0x8bbf7e7d, 0x05773cec, 0xaf67e7c3,
6486 0x11ca9614, 0xcdb38eeb, 0xffe22ffb, 0x8a0f0313, 0x0ee88b2f, 0xdeb1f0c5,
6487 0xf892fee6, 0xc83bf236, 0x4e12dc76, 0x4e07d440, 0x3eb0ef11, 0xabe33028,
6488 0x24e89083, 0xf226deff, 0x19b83360, 0xa9c0924e, 0x05d77ab3, 0xfc8d9abf,
6489 0x6098f535, 0x9b53763b, 0x8139ca24, 0x9ccd608d, 0x228c9b2a, 0x52c565c2,
6490 0x0c8c88af, 0xf6ed53c7, 0xbd20b77b, 0xf327c107, 0xfeba39ba, 0x92e49705,
6491 0x37deeb22, 0xbdd7e2ab, 0x644d3dbb, 0xeea97fd7, 0xad34199d, 0xfafed351,
6492 0x1d8277fa, 0x1822e8f3, 0xdb27a3ce, 0xa0544675, 0x102fe380, 0x7b33f44c,
6493 0xf09f54c4, 0x1a7e4fdb, 0x922bf9e5, 0xa553ce29, 0x0dab0281, 0x78eec4a0,
6494 0xda365b66, 0x3fce04d7, 0xefe89bf5, 0x0c679e5e, 0x4e6fd3d7, 0xfa277966,
6495 0x93d59921, 0x4625a09a, 0x1f98656f, 0xd88d3a41, 0xe0f1eaa3, 0xc9532fb1,
6496 0xf5dab6ef, 0x84bd277f, 0xf940cb8f, 0xa439825b, 0xd5d8e2da, 0x3163ca01,
6497 0xcedc790f, 0x9dac6bcf, 0xfb8fcb92, 0x5017755b, 0xb4d04f7c, 0x7d8472a9,
6498 0x3625d815, 0x85d8f6af, 0xc7f3151c, 0x5277a62b, 0x9afd718b, 0x74a9fd8e,
6499 0xfe7d53ac, 0xed4a74d4, 0x0a9ecd8b, 0x4cfbce3b, 0xa56f93da, 0xbf9b70bc,
6500 0x0813e484, 0xbc51a5e6, 0x9f06629d, 0x7a46f4b9, 0x594abbbc, 0xcbb75591,
6501 0x5d29dace, 0xbca06c77, 0xfce41bd4, 0x0e0a1ed2, 0xeb027615, 0xd936740f,
6502 0xbfef3d69, 0xff268f75, 0x56032fb4, 0xf578ff91, 0x7dfcc98b, 0xfe699833,
6503 0xe04dbb1a, 0xf3a26fdc, 0xdce27da7, 0x130be06a, 0x3fec679b, 0xacae73a5,
6504 0x838a0e21, 0x0fc847cd, 0x58597424, 0x12f0951e, 0x61747970, 0x38e7477e,
6505 0x8a01ef87, 0x70368343, 0x9ade384a, 0x4f796618, 0xbfa2dbb8, 0x9adc9128,
6506 0x55bcec81, 0x214af5e5, 0xf27f7202, 0xbf6373c8, 0xe8e7ae84, 0xe170898c,
6507 0x6097b8a2, 0x933b866e, 0xc29de523, 0x73b46ee8, 0x0626b53c, 0x9794c94d,
6508 0x9178044f, 0x274235d1, 0x3a0d7db0, 0x6f7f990b, 0x9e97c355, 0x34ba3074,
6509 0x702141c2, 0x926ba13a, 0x412dfe4e, 0x123e3173, 0x93e9dd34, 0x5bcba46e,
6510 0xda178982, 0x611bf7cd, 0xaec98ed8, 0x7d2389bd, 0x6b42da2b, 0xf835c71e,
6511 0x20b33e16, 0x0e4fa23b, 0xfde47ca6, 0x3ef7ece7, 0x9d9b25b3, 0x5464f917,
6512 0x29b61275, 0x6753e276, 0x74d7a27c, 0x39729465, 0x494e5138, 0x3c3e3e56,
6513 0x4c9e711f, 0xcf3e64fd, 0x1692d169, 0x017b32e7, 0x2f2317b2, 0x5e0a5c7b,
6514 0xb5ed0bba, 0xb4ee07ff, 0xdfabe462, 0x1689e474, 0x35fbf79c, 0xf620fc81,
6515 0x179ea94f, 0xfc6f9f09, 0x298eed66, 0x155b6fe4, 0x9df90567, 0x2c87ef90,
6516 0xd1557dff, 0x1dd847b7, 0x09338764, 0x78fbb1bf, 0x90fe37cf, 0x83c1dbf2,
6517 0xc9d56e92, 0x887386ef, 0x4faebaee, 0xdee7f255, 0x7cb21f83, 0xe7ba6e76,
6518 0xafea3b35, 0x3e61b3bc, 0x342675c9, 0x2ebf9137, 0x20417912, 0xa193fb8b,
6519 0x362ff9d3, 0xb4e1e844, 0x7b0837b0, 0xea7c51c6, 0x987af612, 0x3b6c4eea,
6520 0x4f1e1e7a, 0xba8877eb, 0x01af78d8, 0xb9218c8e, 0xac9bc237, 0x7e378e1d,
6521 0x59c222f3, 0x6aeb59d1, 0x77fcc457, 0x7abf3ced, 0xbdf3ced7, 0x379ee9f5,
6522 0x3dd53e49, 0xc4a9a91f, 0x0e40c5e7, 0xac0193d5, 0x7e38b58f, 0x637ed864,
6523 0x0e6bc9ec, 0x7bdf34ab, 0x415f9819, 0x43496f7d, 0xdb3bedfd, 0x3e0d7939,
6524 0xa49d40ef, 0x9e709e51, 0x8a1d87d7, 0x6fcd0c7b, 0x84b57338, 0x2201d8fc,
6525 0xdab9e902, 0xe48e3d5d, 0x979ff886, 0x06d67648, 0x7619afcc, 0x8a764c5a,
6526 0xfe1317ef, 0xc85fa8cb, 0xdaab72fc, 0x65d998b7, 0x2ec80987, 0x1eccff11,
6527 0xc51aff10, 0xed0d62e3, 0x893fbd81, 0x9f6b79d9, 0x58f2c5c9, 0x5913ebf4,
6528 0xd403de7f, 0xa05bed6f, 0x21373b31, 0x5ec94b9e, 0x3ad84783, 0xa4898001,
6529 0x91dc093a, 0xf60503e7, 0xc337a654, 0xf6174e5f, 0xd3d0281b, 0x9247c89c,
6530 0x47d9472c, 0x7de49c44, 0x3f5d4711, 0x9e67c7fa, 0xfb4f839d, 0x44d09c44,
6531 0xfdc73c7c, 0xac45b7fe, 0xd66b7faa, 0xc7ca16d2, 0xf1b32d7f, 0x227ce2c3,
6532 0x44727028, 0xdc504f9c, 0x6f3f51d0, 0x69d7738a, 0x1fa177d8, 0x34daee9d,
6533 0xf2aa729f, 0xa947cd45, 0xcc0ee59d, 0xce7154a7, 0x0aa3beaa, 0xc222f337,
6534 0x7b91fb5f, 0xf7e4cc8b, 0xaefaf3ce, 0x07f0cbfd, 0x9e1ca2af, 0x8ff28c38,
6535 0x1d90a713, 0xafcc3f86, 0x8dd640c6, 0xe19283e3, 0x4bde7647, 0x97681c78,
6536 0x4848fa47, 0xfa9b021d, 0x9fdbe919, 0x9fdf61f1, 0x474acaee, 0x78711e79,
6537 0x9e51d2b2, 0xccbf2783, 0x38ecb324, 0x9bab11fd, 0x115755db, 0x0f3da7e1,
6538 0x3838cd4b, 0x73f3a735, 0xf44b3294, 0xced18af9, 0x3071e74e, 0x243b07df,
6539 0x9acb1756, 0x76e6ea9f, 0xfe62a5d9, 0x2b7c1973, 0x11bf9366, 0x828f81e7,
6540 0x1fc2e7f8, 0xa263cfd4, 0x2be528fb, 0x7b1eb718, 0xaf398956, 0x3c2264db,
6541 0xe092e86d, 0xe57bc827, 0x1771d8ee, 0xc46a5bcb, 0xf73b1b3a, 0xfa831b1c,
6542 0x7a297aac, 0x2be50d5e, 0xc03c9cec, 0x169acfea, 0x499f3a25, 0x78cb7917,
6543 0x0b794f18, 0x07f989e2, 0x16bd0cc5, 0x8745efc4, 0x6b4c90a7, 0x09cb899f,
6544 0xcbb32afd, 0xb4bf9142, 0x28fee3ce, 0xccfc057c, 0x8e06f66e, 0xb3dd22a6,
6545 0xb49d725a, 0x1f332cc7, 0xcb99d59f, 0xfd980ce2, 0x445432f2, 0x90b3cbb9,
6546 0xd73ed3e5, 0x47942ce9, 0xa093f0a5, 0x8daef3f1, 0x914aaf82, 0x47f46dcf,
6547 0xfc133dd3, 0x86cfb44d, 0xa83392bd, 0x1280f9d3, 0x8af3af37, 0x9d766a75,
6548 0x7bc7463c, 0x79e881b5, 0x6f1f215e, 0xfdf3f467, 0xd58136c0, 0x347ce2e9,
6549 0xf9d87207, 0xd5adef78, 0x7857bf53, 0xac4a717e, 0x166f8c63, 0xf243a9b8,
6550 0x7e35bf48, 0xa9b84fd9, 0x3ca97c94, 0x35e485bf, 0x033af748, 0xa0fe3a2f,
6551 0xf90bd63c, 0x617813ac, 0xb5fbe17c, 0xdd3f25bb, 0x19dfad2b, 0x81a3ff4d,
6552 0x0f090b35, 0x6caab8b1, 0x5b7e5851, 0xca549b05, 0x5571636f, 0x66978c35,
6553 0x2c58e295, 0xd23cea9e, 0x79e6e84d, 0xee95fff9, 0xcec8256a, 0x59ffaa7d,
6554 0xfe88fa72, 0x74a96ff6, 0x7da378fe, 0x1956fd70, 0xfd7c1138, 0x6f3cfcb5,
6555 0x4c327fe0, 0x945dfa66, 0x50758b7e, 0xa6dd3e74, 0x3218fb72, 0x0362f3f3,
6556 0x2fefb13f, 0x3df8f914, 0x57b580bb, 0xa54f3f3a, 0xbec1dff3, 0xad6054a1,
6557 0x3fc51169, 0xf0884fea, 0x79d2fb3b, 0xeb35b89d, 0xbe53efe3, 0xe29b4f7e,
6558 0x6a0e4cc4, 0x8a6e2ac6, 0xdf6335d3, 0x11109cca, 0x79d2da57, 0xdb4f79fd,
6559 0x74098da3, 0xe48af0ce, 0xec1bf324, 0xd423fbfa, 0xce48b5f7, 0xb1fef889,
6560 0x6777a1be, 0x92b23e93, 0xde7ad3a6, 0x5a8bbbee, 0xc5ec7fb1, 0x75919c3b,
6561 0xe73b31e5, 0x0ab19eef, 0xa3fd9b8b, 0x41567e93, 0x3dae80e7, 0x0ffb8ecc,
6562 0x9d92aebd, 0x904ab60f, 0xcb1d1b85, 0x8f9afa3a, 0x27039cea, 0xe7c64a55,
6563 0x43549fb7, 0x5c0f915f, 0xc82b72c1, 0x559b49ce, 0x1ddc6baa, 0xca21a89f,
6564 0x90fa5e8f, 0x75553f9d, 0x548fcc4a, 0x3afd96ed, 0xfbb479fe, 0x5470950d,
6565 0xa8c122d7, 0x8571c8dc, 0xa3bf938d, 0xdc2da7fe, 0x5cf81a7f, 0xe068f02b,
6566 0x5aebc0d3, 0x6dd667e1, 0x63e3c68b, 0x1a3adae0, 0x65b47fdf, 0xcd794a8d,
6567 0xfdf1cda3, 0x36afe18c, 0xfe88fd50, 0xe8aec37f, 0x71871b79, 0x387e63e8,
6568 0x1bf59fd6, 0x42842c38, 0x7050e1c2, 0xe23338ed, 0xaac9eafe, 0x5ee71071,
6569 0xb7111de4, 0x3379b88d, 0x7e740eb9, 0xf3bc52ae, 0x6eac2b66, 0xb7ff66f0,
6570 0xab93891a, 0xbb0b2702, 0x53f4c0fe, 0x80b3d5d1, 0x9e025bf6, 0x92ef921a,
6571 0xf28d24ae, 0xb7108ae0, 0x165dc5db, 0xfa225fbf, 0x2dce2c4c, 0xd216c081,
6572 0x0b61e0ff, 0x243c773f, 0x84087cb1, 0xe420db1f, 0x77c841bd, 0x6359d603,
6573 0xe62f294a, 0x82c6f475, 0xa528c73d, 0x6bcf13af, 0x254d1f8e, 0xee062f39,
6574 0xb8071667, 0x65f4319f, 0xe31b89c4, 0xa49bf861, 0x0b2eeaef, 0xf708f7d0,
6575 0x5f733f09, 0xe919fa0b, 0xbc1fbb46, 0xc5e1892d, 0x8de9c1d7, 0xed758b8d,
6576 0x0e4df3d1, 0x890e5f9e, 0x11cf36bc, 0x308aafad, 0x7ae31524, 0xe9d9758b,
6577 0x99f56f67, 0x12deff69, 0xf5d3dd89, 0x3cd3e3ea, 0x9c38f471, 0xdd7c8b57,
6578 0xf3a52fe8, 0xd01f9c2d, 0xeb23939a, 0x9e0e9df1, 0x94cd577f, 0x88ff247d,
6579 0x696965fa, 0x65fadc6e, 0xbfe703a6, 0xe76ebd9d, 0xc5fac8d4, 0x709f27b5,
6580 0x1facbdf8, 0x7f929455, 0x64fee168, 0x4dd71ca0, 0x581c7ca3, 0xb16deb7e,
6581 0xf0cea9f8, 0xef288e22, 0x427087ba, 0xdd25d9f6, 0xfcc1384d, 0xcd126eff,
6582 0x437aba32, 0x627597fe, 0x97e5c63c, 0xc303f82d, 0x9c09f1dd, 0xa8db946f,
6583 0x5180f578, 0xc17dd407, 0x79e34df3, 0xeac4399d, 0x892eba81, 0xc8fdb6e1,
6584 0xa45c9cb5, 0x8ffbb077, 0xfdb06b39, 0xa38f0707, 0x1f02f3ed, 0x572077d1,
6585 0xf371ad5b, 0x2dbf61ca, 0x5276616d, 0x593284a7, 0xf31071de, 0x3f5819bb,
6586 0xd58cfa9c, 0x1247ed0f, 0xf6b9d356, 0x38cf5ac0, 0xd4f42bed, 0x3f2c8d00,
6587 0xac2d846d, 0x3225fca5, 0xf1a0db9f, 0x131e4aef, 0x4ffa8ef1, 0xc31fae21,
6588 0x8d2b5fb9, 0x5b7c17e7, 0xfa374b67, 0xd4afc303, 0x1757bc0a, 0x294ad9ef,
6589 0x539e6c57, 0x3308ec2b, 0x62df1678, 0x0e9d9bf3, 0x9c08bf91, 0x644a9c36,
6590 0x71e0eaf9, 0x5d33a359, 0x474feb94, 0x7986fe53, 0x739c5e7a, 0x2e04cfcc,
6591 0x65fdc5fb, 0xe4ccb943, 0x5bc99a66, 0xf9421f23, 0x9e0cbc31, 0xbe53f64c,
6592 0x8df8745f, 0xf57fd23c, 0x69179c5e, 0x0f3fa877, 0xcfc7aefb, 0x481b5c70,
6593 0xc6327762, 0x6fc3bef8, 0x359c264c, 0x9f32fa9c, 0xbe5ae5eb, 0x7d39b8ea,
6594 0xbc492b46, 0xbc49358e, 0x8730ed8e, 0xf27ea952, 0xfedd941e, 0x7a1a7d08,
6595 0x476117fe, 0xfaf5e660, 0xface871e, 0x171c5d0d, 0xe2de6ea6, 0x79f82bfe,
6596 0xbff6c28d, 0xe21e7c61, 0x1ae22be5, 0x7ba85d10, 0xb86612af, 0x31349ef3,
6597 0x8727bc7a, 0xbbe32332, 0x451dd68f, 0x06a1af7e, 0x02491f98, 0xc7e8b3f2,
6598 0xdef7547c, 0xe5812e77, 0x76f2c74b, 0x95bf3054, 0xadf90327, 0x4d554e27,
6599 0xf90f8c8a, 0x27e7990e, 0xca2c8724, 0xfbe59e56, 0xc234390b, 0x73ef5172,
6600 0xce92bf1c, 0x527580e5, 0x6c71d937, 0xf9ab749d, 0x05b7436e, 0x7bd81ce8,
6601 0x13bec2c1, 0x81bddab9, 0x85f0e1d5, 0x19f91267, 0xa76e78f0, 0x1bc389f6,
6602 0xabf3d126, 0xcede3787, 0xc6a52fce, 0x23e5f8a8, 0x2f28b2fa, 0xe3a9933a,
6603 0x99f76d78, 0xc2ad604c, 0x647ea7e8, 0xc1d77afc, 0x4f60d7e3, 0x90a73b02,
6604 0x00e38f20, 0x5bad4426, 0xcb16fed3, 0x653a6a23, 0x8c1e2457, 0xf0703ef7,
6605 0xc223eafc, 0x9013f101, 0x6dcf4c5c, 0x7ce9adbc, 0xad53d19d, 0x1b1e9804,
6606 0xde3e145a, 0x2fcc5bca, 0xb03e1d19, 0x36fe88fb, 0xf7e6bf3a, 0x02bcec1a,
6607 0x18fb3267, 0x6ff4282a, 0xe8affec7, 0xc875ca11, 0xdcfe026f, 0x9b83eec2,
6608 0x11a7c77a, 0x5f7a87ee, 0x178bc477, 0x083dd0ef, 0x97227a92, 0xe3b117d7,
6609 0x39f8327b, 0xdcf389c2, 0xeb989d8f, 0x9fcf1499, 0xaf1e60f9, 0xef2125b7,
6610 0xbc516576, 0x3217b4fb, 0xdecf39f8, 0xe209df6c, 0x812dbfa7, 0xdbf5a7dd,
6611 0xfce8b9f8, 0xe9cdc7fd, 0xa5db7714, 0xaa3f1469, 0x405fde0b, 0x2fd8f8f7,
6612 0x782b7e63, 0xd61bdd90, 0x742db4b6, 0x2ea3a1c5, 0xc5f1fb83, 0xc8fbfc6a,
6613 0x7bf8c5db, 0xf510cce0, 0xee130ed1, 0xa2855ef7, 0x8679676d, 0xf436f92b,
6614 0xff0bf7bf, 0x8512c0fb, 0x81ef25e5, 0x077bf0ae, 0x54b03f7e, 0x85fbd1f8,
6615 0x1e5a5e5f, 0xed9727ed, 0x7ee9a786, 0xbe2b9960, 0xac487e1f, 0x6c5c1cbf,
6616 0x451607dd, 0xe4487bcf, 0xa3b90f77, 0x10ca4f9f, 0xf21f37fe, 0x3006ffc9,
6617 0xebbe901e, 0x5c58130b, 0xc4ca6fbd, 0xb1c179b8, 0xfdeec0cd, 0xbffdc57b,
6618 0xc286f7a1, 0x3abc59f7, 0x35fe73d1, 0x09dbf31b, 0x5ee71790, 0x195e246b,
6619 0xd720fef6, 0xa82fb8b7, 0x868d38d5, 0xe560afde, 0x652e7913, 0x90b17de8,
6620 0x04def57f, 0xaf9ef22d, 0xea8b6036, 0xd36f3b7b, 0xf9f8462e, 0xf46f816a,
6621 0x73c8e6fd, 0x67b29d8a, 0x0bdd0671, 0x3e59fb58, 0xb8b01c8d, 0x08e57c85,
6622 0x112c72be, 0x6dcae8f1, 0x77e2e26b, 0x8fbb3f84, 0x6b077dfb, 0xcc2d0a7b,
6623 0x92036aee, 0x6aa3ee9f, 0xac9ebc83, 0xc9ebc05d, 0x579e76fc, 0xf25078ae,
6624 0xbee624bb, 0x067d134e, 0x795a967e, 0x327036fc, 0x1f812f2c, 0x7e78a71a,
6625 0xb1e788bf, 0x7d049a38, 0x779ce90b, 0xd2724ba5, 0x78b171f7, 0xea6abe5a,
6626 0x6f9ee45b, 0x9bc41f86, 0x16327e42, 0xf0cf3f47, 0x1a632b7c, 0x4c570bab,
6627 0x144f75c1, 0xb8439a7e, 0xdd89bba9, 0xdb7a14ec, 0x413bec9b, 0xbf66bef1,
6628 0x5fdf07b8, 0x792219d8, 0xf7cb02f4, 0x5b7d6dfa, 0xcc1e79eb, 0x836bc1ee,
6629 0xdefa4e09, 0xc92bb6b5, 0xf6fd4099, 0x54c9c486, 0xcec9761f, 0xb457ec24,
6630 0xf2405c9f, 0xdfe328ac, 0x61a9d465, 0xb4ae6f96, 0x5e92b679, 0xa27b3897,
6631 0x3a0dbfee, 0x58f3866f, 0x0902f6bf, 0xe76fe327, 0xe0c85e6f, 0xf8feaef1,
6632 0x719399e7, 0xcf36e9ab, 0xf07ba26e, 0xba5557ad, 0x7e4ef326, 0x4eba6163,
6633 0x6f3674f3, 0x16cf4b49, 0xe8357e3a, 0xee343b0f, 0x367f155f, 0x6f8b23cb,
6634 0x86907bed, 0x50976f83, 0x73d03cde, 0xc08d44bc, 0xfa3d7f77, 0x6bfa38e7,
6635 0x5bb09300, 0x69256b33, 0xb86fc8b9, 0x8fbb7b1d, 0x41b9d266, 0x316fd93f,
6636 0x295267b5, 0xbdb6d62e, 0xf2913a97, 0x1ade0e8c, 0x92e95deb, 0x87303cd9,
6637 0x894a1ff2, 0x4669efa4, 0x5f0095df, 0xff942007, 0xf1c894c0, 0xfb6fffa6,
6638 0xae38413f, 0xeca286b5, 0x561390df, 0x47563eed, 0x7bb0b61e, 0x8927ba75,
6639 0x92ea9efc, 0x2c0cf5c0, 0x674ec86e, 0x78f0bdd2, 0xf0ccc54a, 0x10cdf508,
6640 0x9ee9db34, 0xeff32836, 0xff99b2cc, 0x9ff62e9e, 0xd0f60e61, 0xc53396f7,
6641 0xe82ce2bd, 0x06bef363, 0x40bad661, 0x0f3b5333, 0xb72dac9c, 0x32a3ef06,
6642 0x901038af, 0x4cc1ff49, 0x9592edb3, 0xf1007f7d, 0x37223df4, 0xe4325c33,
6643 0x13fdd321, 0x962f5eff, 0x8f02eb9f, 0xefdc5c33, 0xdf412a50, 0x80439659,
6644 0x09df77dd, 0x1def7121, 0x58d98f9f, 0xd77dd1a7, 0x893b689d, 0x367e1e4c,
6645 0x23f10e7f, 0x7427e3c7, 0x2c33531f, 0x293e88d0, 0x9eba6998, 0x0c7ceb74,
6646 0x375b0266, 0xe0785d75, 0xfb91b2c9, 0xdbd76742, 0x50bbe8e7, 0xdf62e5c9,
6647 0xc9ad3a8d, 0x04975641, 0x7ec3fdcd, 0x39200f2c, 0x66626d73, 0xf777c8c6,
6648 0x3df601e0, 0xf777ec45, 0xcce5eec4, 0x8cb4ef91, 0xfaf73fef, 0xc426eb97,
6649 0xd5872ac7, 0x4a3e2329, 0xd07739ad, 0xcd39e0f9, 0x8d399893, 0x996d03be,
6650 0xfb3116c8, 0x53bcb1a7, 0x5c092ae0, 0xe4bfc4e5, 0x07fbbe32, 0x389f1786,
6651 0x8265f6bf, 0x9252ae9f, 0x91587c30, 0x43881dae, 0x5fa19dab, 0xe159efa7,
6652 0xe53af9a9, 0x566d5bb7, 0x166fe527, 0x846937a2, 0xff2b26de, 0x7ef8c1ee,
6653 0x4d8e562b, 0x663e8328, 0xcb2b4e7f, 0x628fd78b, 0x6b8f34f7, 0xb27fbf9c,
6654 0xfd10a678, 0x1bcca78f, 0xd16ef945, 0xb164e62f, 0x30e51bfc, 0xe98390c7,
6655 0x80e7ffc6, 0x3c91977c, 0x817fff63, 0x802a2fc1, 0x72134681, 0x48d7f834,
6656 0x5c6f143f, 0xbf431fa8, 0xd9722379, 0x57f9c891, 0xf18f4be8, 0xec9d5dec,
6657 0x836f9634, 0xcf05ffbf, 0x10785073, 0x00107850
6658};
6659
6660static const u32 xsem_int_table_data_e1[] = {
6661 0x00088b1f, 0x00000000, 0x94f3ff00, 0x51f86066, 0x257bc08f, 0x799c1819,
6662 0x8968c550, 0x1819390b, 0x0bf1030e, 0xda005620, 0xc0c5caeb, 0xfdc406e0,
6663 0x88013c40, 0x3eb100bf, 0x01830337, 0xd902a710, 0x736e6852, 0x17ba0264,
6664 0xd8815d88, 0x32bf881d, 0x637c3030, 0x767ede20, 0x623da021, 0x2039fe08,
6665 0xfd04b2fb, 0xf0d83ffc, 0xdafa655d, 0xc0c2a817, 0x2a83a310, 0x8fc68b16,
6666 0x466fc1d3, 0x027c9a3c, 0x8f113f1a, 0x5473717e, 0x2a019d7e, 0x8188c93f,
6667 0x9a920f61, 0x6efc037a, 0x81afc741, 0x3100df7a, 0x74769a00, 0x0003685d,
6668 0x00000000
6669};
6670
6671static const u32 xsem_pram_data_e1[] = {
6672 0x00088b1f, 0x00000000, 0x7de5ff00, 0x45547809, 0xbedd70b6, 0x4e9def4b,
6673 0x62585908, 0x81511007, 0x05e42ce9, 0x62d9b1c4, 0x970621f4, 0x66854611,
6674 0x44749ecb, 0xf9d1c1c6, 0x153610d3, 0xc713309d, 0x60ec44e0, 0x81a0d050,
6675 0x60241009, 0x3cc0ea03, 0x64ffe31d, 0xb83066dc, 0xc5a4c6b0, 0xfcb8df0d,
6676 0x4dd54e75, 0x11d37bdf, 0x7fef999c, 0xca3fbff3, 0xfb5ba957, 0x539cead9,
6677 0x2c922aa7, 0x4222e910, 0xab9f83be, 0x409bf908, 0x4d171908, 0x69e5a909,
6678 0x24e05295, 0xbfa2e024, 0xe1521366, 0xd3cb4254, 0x43b29909, 0x48955f0e,
6679 0xc8428df3, 0x7da6f34c, 0x6eef2c56, 0x53b0f960, 0xfe5a11f1, 0xd3cd1371,
6680 0x8ee6033e, 0xe5a0ae87, 0xd9221d91, 0xb28edd08, 0x21124899, 0xfd842dc7,
6681 0x0e7cd364, 0x96568521, 0x3fdc68ad, 0xb717da07, 0xf6958999, 0x68bbb157,
6682 0x5f3415c6, 0x50264874, 0x32d362a5, 0x97cd1065, 0xc8168484, 0xf3664cf7,
6683 0x4314ee0b, 0x1efd689b, 0xcdd24757, 0x574e420e, 0x2147885b, 0x91d9c6a4,
6684 0x4268d374, 0xf2db434a, 0xb3695da0, 0x581135e0, 0x5397a6c7, 0x045b5d61,
6685 0x4843d9af, 0xf13b66d9, 0xf873628c, 0xde3bfe8e, 0xa2af862a, 0x3ae98be5,
6686 0x88b7ed09, 0x1111e6d4, 0x78a75fc6, 0x9df8519c, 0x38e376ae, 0x0b62be6a,
6687 0xabb6871d, 0xc2f0567c, 0xc44d2b12, 0xefc742df, 0xf59d6dde, 0xb7d60384,
6688 0x84e9194c, 0xa056ad75, 0xde68515e, 0xe607ab4e, 0xd1e4a8d7, 0x4686d2f2,
6689 0xb47470a5, 0x03cdb2bf, 0x1faaf3f4, 0x94d7ec9e, 0xd5d3d31b, 0x46467884,
6690 0xf884a5f3, 0x44bf685a, 0xc733290a, 0x407fbf44, 0x081909e2, 0x63c48bfd,
6691 0x214ff689, 0x4783df89, 0x5e14afe8, 0x844ebdc1, 0xc5b78aab, 0x27bbfa6e,
6692 0x6eb3b78a, 0x9229478e, 0x4d5feda3, 0xd03c021f, 0x9c02d4f9, 0xcf96ba68,
6693 0x4c9135cf, 0x2eff6892, 0xe903711f, 0x351eb7f5, 0x3cc995ad, 0x185ac742,
6694 0xc693e31c, 0xee42bcd3, 0x7e425e20, 0x37c722bd, 0x241fe695, 0x6f3039fe,
6695 0x062fe4d1, 0x92d2113c, 0x4abbf402, 0xfd60b320, 0xd349813f, 0x94a955f2,
6696 0x6bdc293e, 0x213ce5a7, 0x89ee7c0a, 0xf27c2f90, 0xa7ec74fe, 0x6851fb08,
6697 0xdfcfc33f, 0x572f3b8f, 0xaf3b8fd7, 0x0aa7ed58, 0x585db1fb, 0x1379b53f,
6698 0x2bc9f3f4, 0x1bb9fb55, 0xd85d71fb, 0x4f57dcba, 0xeae7cfd4, 0x7e27ec72,
6699 0x69f897aa, 0x07a5517d, 0x6913e1d2, 0x3e39a3b9, 0xa5a27ef3, 0x812bc98b,
6700 0x4b949dff, 0x971174b4, 0x61d1d36b, 0x97412fbc, 0x8fb93da7, 0x30f3ce5f,
6701 0x7c82cb88, 0x50520ca9, 0x641a4c2e, 0x35dcf9c1, 0xe17281c8, 0x4bfe09ae,
6702 0x301e74dc, 0x79a54936, 0x7723ffc5, 0xf3a6ba0c, 0xa40a4814, 0xc6a4131e,
6703 0x8332d5f2, 0x5fc1e4c3, 0xdb463c8f, 0x91914c07, 0x4ebf34f1, 0xac38f498,
6704 0x21311363, 0xa9226c7c, 0x33367a82, 0x3ab4f941, 0xa089e73d, 0x866b4e06,
6705 0xd10bfc52, 0xfec8d77e, 0x2dafa014, 0xd020e6e4, 0x94a1aadb, 0xf21107c9,
6706 0x70a6f074, 0x87eda250, 0x3c00a616, 0x6fe50acd, 0x1d0af8ed, 0xff8e347f,
6707 0x03bf8c1c, 0x77d71fc6, 0x5cb0f37c, 0xb496f8dd, 0x16f8dd62, 0xe94f8e85,
6708 0x9db9377d, 0x37e14f8f, 0x83e79081, 0xe6f8e1b7, 0x7f1c62b4, 0x758a42b5,
6709 0xc77adbe3, 0xfdd6017f, 0x1feb7f52, 0xfebf4136, 0xfafd52b4, 0xc3feb615,
6710 0xdf1f1164, 0x63ffeb86, 0x7f5b2170, 0xbf5b295a, 0x3bdbf599, 0xfe17abbe,
6711 0x8fbac1af, 0xe1feb7f4, 0xbfebf513, 0x7ebf5ca8, 0x6dff1b33, 0x77c7c152,
6712 0x04eff8e0, 0x2ffad9cb, 0x15f1c72a, 0x740bdfb3, 0x55b60ca4, 0x64f8e885,
6713 0x64886508, 0x4c3e5194, 0x42102547, 0x6191d7db, 0x6cbb8708, 0xb0beee8c,
6714 0x44737a51, 0x51091de5, 0xacf2a28e, 0x597cd392, 0xe40524f3, 0xb953962c,
6715 0x754f88b7, 0x74889b61, 0xa1ccea4d, 0xbb7ce98b, 0xe420c4db, 0x195dd617,
6716 0x23bf7112, 0x9da00b73, 0xfdf0c244, 0x6cc787a3, 0x98cbaed4, 0x8f95aa2e,
6717 0x88f8ea77, 0x993827cd, 0xf3a2aa8c, 0x3044069b, 0x4e3f9a2e, 0xf2a128e5,
6718 0x472a7df3, 0xd3213d21, 0x0ff7e8f1, 0x8a259ca9, 0xb1966f96, 0xde483c7d,
6719 0x72049518, 0x971cfd82, 0x2f8fbc18, 0xff004211, 0xa1ddd62f, 0x545a7c80,
6720 0x8f40a76b, 0xf1c023ce, 0x0e6dd914, 0x9e10146d, 0x2dcf801e, 0xfc848ac8,
6721 0x9535a295, 0x7ea8b682, 0x6dddae80, 0x8532b424, 0x76b05fd6, 0x5d3750de,
6722 0xccb3adff, 0x1fec2299, 0x84d837c4, 0x9b064c7c, 0xd5990972, 0x4c1e4eba,
6723 0x92ccb733, 0xb4d4efdf, 0xe7d7ed9f, 0xe7d62d6f, 0x6c90e5bb, 0x44a37d02,
6724 0xdfb48d20, 0xe5f4abdb, 0x42f138ea, 0x1f2bc302, 0x6c4927ef, 0x9a43b7be,
6725 0x88dd9f09, 0xd66e39d7, 0xe04f9d56, 0x7184991e, 0x481cecbf, 0xb103ff10,
6726 0xd6cddf9e, 0x1cef9c6d, 0xa02be2d9, 0xb77399f3, 0xce34f088, 0xdd9f73bf,
6727 0xd34b1a67, 0x20654ffa, 0x8c7ae341, 0xd4bb9ff3, 0xea371eb8, 0xc682f361,
6728 0x8c4e8cef, 0x9b6814f4, 0x4d43e034, 0x6b968abd, 0xa1a87c06, 0x33cdb2af,
6729 0xd092f975, 0xa2fd5d6c, 0xf2ba79fa, 0xba25b545, 0xee6b05f2, 0x05e7e5d0,
6730 0x9fd5d6ef, 0xae9974bb, 0xfbaaf6fc, 0x16b7e574, 0x67e5d3af, 0xeaebd7fb,
6731 0x51ab32df, 0x2bec2e57, 0xe513a8b9, 0x54a2ffaa, 0x36df2bd0, 0x9547a013,
6732 0x387e55de, 0xe9829d59, 0xa60f6ae9, 0x294f80cb, 0xb3769bff, 0xde71b034,
6733 0x2aefc045, 0x55c84e9c, 0x464fc069, 0xd3c237ba, 0x67f4df48, 0x487dac70,
6734 0x5205cb4d, 0x87ae7200, 0xf7eacfef, 0x120e5c73, 0x72d31cb2, 0xf96df185,
6735 0xc4c9d4f6, 0xc8f0f905, 0xfdff472a, 0xd7011692, 0x1e8b4041, 0xd4a37808,
6736 0x70ebc3aa, 0xf6bb3cdd, 0x257e388b, 0x0078eef0, 0x0132c155, 0x307c21f8,
6737 0x3031c6ed, 0xcc72df1f, 0xfdc40db7, 0x7f3aabb7, 0xc01287c0, 0x93d300af,
6738 0x3d30b3d5, 0xf4c7ed5e, 0x4c62eac3, 0xc2aeafdf, 0x297ab3b4, 0x83ab47a6,
6739 0x7aa5fe98, 0x54efa60d, 0x56fa62d7, 0x7fa63d75, 0xda610eae, 0x54c3ed5d,
6740 0x395edba5, 0x4af5c899, 0x1dd3ffae, 0xf967f302, 0x7bfa445a, 0x37a3f207,
6741 0xacf1f805, 0xa0918be3, 0xcb7d9f37, 0xef2f404c, 0x7a465e0f, 0xc4ae17e8,
6742 0x61457a87, 0xac870a88, 0x1b56e5be, 0x44d593c3, 0x1b9509f2, 0xa4fc5df7,
6743 0xcc68fe77, 0xda01244b, 0x9d33bc87, 0x411dfa31, 0xc3e75f10, 0xc645f113,
6744 0x71f140de, 0xe5bfd1fc, 0xf8e7bf40, 0x283b653e, 0xc2497ee2, 0x5f01784f,
6745 0xfee1b81a, 0xe5c1d913, 0xf7e079f2, 0x7e1540f1, 0xa684691d, 0xd2370413,
6746 0x3356d9df, 0xed8e0091, 0xfda110f6, 0x84f43d9c, 0xc5bbf60b, 0x87f72629,
6747 0xa6a0e031, 0x6ee92d15, 0x689f7687, 0xd6cfe7d3, 0x282df90a, 0x37713d37,
6748 0x72ba018d, 0x011c3fbb, 0x54c14ff8, 0x8a7167ed, 0x0070fee2, 0x45f18fc2,
6749 0x29d23c73, 0xdeb0dbb5, 0xfd1e7b3f, 0x479d13f5, 0xb680f92b, 0xf8645b47,
6750 0x3e91edf9, 0x533e96f8, 0xed4f000a, 0x9fb017f2, 0xefbfe8db, 0x12bf4186,
6751 0x037ed5e6, 0xfcd0622d, 0xacdef823, 0xf3b68f1b, 0xb43136a8, 0x255e9feb,
6752 0x27a55c72, 0x0bfeda2a, 0xce3b403a, 0xfdcbd6ea, 0xd03e5d78, 0xedd6ea96,
6753 0xe50bf003, 0x482c527b, 0x9ce52f40, 0xc7247a7a, 0xefce811a, 0xf461e088,
6754 0x157ab026, 0xefc54e96, 0x00ec3241, 0xae7e603d, 0x5b9e6f4a, 0xf972a5de,
6755 0xe4c87fd4, 0x9aff287e, 0xda272ace, 0xc4c0951f, 0x780bf344, 0xd96b7e6e,
6756 0xa7779074, 0x5e1f6c4c, 0x605c0a48, 0xda931494, 0x3e43d01c, 0xa07ca626,
6757 0xffc98ffb, 0xec696576, 0x05261181, 0x8d60b3e7, 0xfaa41f7e, 0x545f2e93,
6758 0x9217cfaf, 0xce80921b, 0x1264eb0b, 0xf51f8012, 0xc62689e5, 0x6aa4450f,
6759 0x2b0fec15, 0xdf313db8, 0x74c1a44d, 0x1ebb157e, 0xe74799cb, 0xc989b971,
6760 0x2ebed56f, 0x2ff36049, 0x7c54696d, 0xd683fcb4, 0x415c9fac, 0x15687da0,
6761 0x3b8219f8, 0x4f26ef04, 0xd0fdfc5f, 0xabe71bf9, 0xec7d1fee, 0x8a8f3e7c,
6762 0x142f82cd, 0x6f191f63, 0x13fef812, 0x035e3844, 0x99e8d6eb, 0xa8387337,
6763 0xf28679f9, 0xeffe430a, 0xa244b7a6, 0x8223b7a3, 0x40d366ff, 0x5fa05f46,
6764 0xf1445209, 0xa7fd23ff, 0x9e7fe9f4, 0xb13fdc69, 0xffb421ff, 0x15ff5d1c,
6765 0x47fed4ff, 0xddff99f4, 0xd8affab1, 0x906775b5, 0xe7d29bca, 0xba11761e,
6766 0x6a929cff, 0xff14bc93, 0xba569be5, 0x4a4e0e80, 0xf3d01741, 0x1f9890a9,
6767 0x3f57618a, 0x3e0f4bd7, 0x0f760087, 0x3ffb4afc, 0x3303f4fd, 0x62f97f60,
6768 0x7b46ec93, 0x6c39b366, 0xd95afca6, 0x8c9d325a, 0x9631fcc5, 0x0889fd5f,
6769 0x7d3d36f9, 0x70f53e96, 0x28c7f812, 0x3f7d70a5, 0x6552fa8c, 0xb07947d3,
6770 0x044804ff, 0x0ed8ccf9, 0x80973fc6, 0x129e71f2, 0xce9cb7d7, 0x00f0f513,
6771 0xf5a04b87, 0xf0444f81, 0xe64e924d, 0x2fd434a7, 0xc84f7ae6, 0x4e3c4ce4,
6772 0x6ff23c55, 0x5e40dfe4, 0x2120f0aa, 0xbb88f7a6, 0x760b1b1e, 0x7fd3576b,
6773 0x9c0d04b8, 0xdb3b3e54, 0xe7f1e0b2, 0xe3cbfd3d, 0x45876e6e, 0x9db085db,
6774 0x6beb8da7, 0x972d2ced, 0x63f02ec3, 0xdeca3796, 0xbe5cfd20, 0x1f2789f5,
6775 0x6df23b05, 0xda62f7b3, 0x97d6d97f, 0xe6813cfe, 0x89c9b6cb, 0x1c32d9d3,
6776 0x2f145242, 0x696ffa01, 0xa50f1466, 0xf1497fbf, 0xefdf618c, 0xa3e2884d,
6777 0x857edb6c, 0x8f0be98c, 0x95fb2d29, 0xbc0c474e, 0x03cb1cb4, 0xf5dc4abd,
6778 0x3f78028d, 0xc9204fb5, 0xd9e031e9, 0x07ea12f8, 0x23c42700, 0xde2f53c7,
6779 0x1403f50c, 0x55cf202f, 0x97cb193c, 0xfd037973, 0x3d234679, 0xf83cfb3f,
6780 0x7b31df7d, 0xcfc5fd61, 0x7582e9de, 0x18aa909c, 0x32b63f5d, 0x2dc747c9,
6781 0x6e498396, 0xe2f7d94c, 0x7a433f0d, 0x67fd7a2b, 0xf35ecc49, 0x6f709aa5,
6782 0xfac2a60a, 0x8cdc3516, 0x7e242beb, 0xc7e2bba4, 0x8f9002c4, 0x7f244b9f,
6783 0xb8be0c5b, 0x717c6458, 0xb4552362, 0xd04efae8, 0xa0fd076d, 0x6d0c5bff,
6784 0x1dc57f42, 0x67fff804, 0x2c9affaa, 0x16e7fcc6, 0x4dafa786, 0xb54f9eaa,
6785 0x36bd2d3c, 0xfc00eead, 0x4bea1e9c, 0x80573f06, 0x0f0e4148, 0xafda3be1,
6786 0x64b4faf8, 0x91e21f86, 0xaa3b7872, 0xef814c07, 0xf643bf50, 0xdaeac759,
6787 0xa3d2ef91, 0xe3e12fe3, 0x60db79d3, 0x44913eff, 0xac625b8a, 0xf2a8a66f,
6788 0x35c7dd3d, 0x6fe1a5f4, 0xf74defc6, 0xf956fe31, 0x1f33343d, 0x837b3fca,
6789 0x83b40ff1, 0x2bce91fd, 0xfbe58c9c, 0x1e50126f, 0x16384998, 0x9cc9375f,
6790 0x2ae5f5af, 0x4b79d09d, 0x5e869c42, 0x8404ffa0, 0x0ab7fa3f, 0x8d3b68eb,
6791 0x78c00cbc, 0xa9fdbeae, 0xf9c45b7c, 0xf9ea23df, 0xbe30349f, 0x0abf5fef,
6792 0x2e573ee2, 0x147c9e87, 0x67f295f8, 0x2afc03d0, 0xcfbac017, 0xf3fc1f34,
6793 0x9c9f294f, 0x54f95169, 0x7c8d3f2f, 0x5c7dbc5a, 0xb33d3e4c, 0x9f362336,
6794 0xf931efd2, 0xd3e32d74, 0x53f25bff, 0xc03e5f85, 0xfc28f2ef, 0x1fd87954,
6795 0xf0f28d1c, 0xe1079323, 0xf4879469, 0xd3920de7, 0xba54fe97, 0xf4ade953,
6796 0x408b8a99, 0xa5d2f4ee, 0x74bd774a, 0x1f5dd2a9, 0x7e0e88ff, 0xa004f2c6,
6797 0x05274a05, 0x0de48fbb, 0x6f2cf8a6, 0xb440e767, 0xa790cbdd, 0x36e1f270,
6798 0x1e5f6a46, 0x87cda89c, 0x4316f90c, 0x5f219f7d, 0x37efa860, 0xf50cabe4,
6799 0xd03fcc43, 0x48215076, 0x7d5d6107, 0x3a093979, 0x57b72fc1, 0x87affb44,
6800 0x6d1579ce, 0x1e9cd3df, 0xb079520a, 0xeaeccad2, 0x156540c8, 0x771eafc8,
6801 0x790095c4, 0x7b6bd32b, 0x78ae220a, 0xac787e8d, 0xdbf9445d, 0x5af92219,
6802 0x1f94457f, 0x9d7f106a, 0xe672bfa4, 0x3a269c67, 0x3d8296d2, 0xc17a2b59,
6803 0xecb85d44, 0x3cb81716, 0x5f87da7a, 0x5f7e8b3f, 0xe3c45874, 0x6b9b1e8b,
6804 0x048bcc2c, 0xc6aa527d, 0x8249382e, 0x7e089dbf, 0x1f6676c3, 0xd06b5c2c,
6805 0xa45ac82b, 0x12c7428b, 0xd522e405, 0xfbd7dfe7, 0x977d194d, 0x1b8afef2,
6806 0x7b6ae5f4, 0x3b023938, 0x5f49b4ad, 0xce76e7ee, 0x67bd2a93, 0x17940c90,
6807 0x7d80c060, 0x34ebe5cd, 0xb3f5f471, 0x0e7bfc28, 0xe5e80489, 0xf088bb6c,
6808 0xceccdb3f, 0x20704909, 0x89254df2, 0xe1535ca0, 0xa17c05d4, 0xba772ff4,
6809 0xe735fc76, 0x7ca55a1e, 0x7f63bbe7, 0x9daed347, 0x03dc8f6f, 0xa66f5df9,
6810 0xd6fa4bbd, 0x8acfb29f, 0x7d9ed9fe, 0xe94f3c4e, 0xda6afbd9, 0x6ddf903d,
6811 0x7b3cc2f6, 0x16397df6, 0xb967a7e8, 0x56e418b9, 0x7f8a50cf, 0xfdecd69a,
6812 0xee276c72, 0x6f102b93, 0xd30a8baf, 0x76ffda73, 0x94844854, 0xfff60aae,
6813 0x33f4767d, 0xa2b79e04, 0xef67a07f, 0xc77e3997, 0x953d6f3f, 0xc7a4dcfc,
6814 0x876d6649, 0x7f33c5f9, 0xf8cf6073, 0xb9c19627, 0x657eeb6f, 0xf29f2d01,
6815 0x416337c2, 0x676cf61e, 0xdcb74d7a, 0x05ce01b9, 0xeef352fe, 0xb9c29932,
6816 0x1062981b, 0x862bb995, 0x623a0e4c, 0xf41be5c1, 0x3c285c7b, 0x067ffd3e,
6817 0xf79e021e, 0x433bb795, 0xfdd60116, 0x4177d1d5, 0x2333ec0e, 0x3debaa5d,
6818 0xf50cb2d3, 0x3badf38e, 0xf5f66241, 0x0b759cff, 0x77590be1, 0x8daff486,
6819 0x07a25def, 0x83e462f1, 0xf7be74be, 0x756fcc2e, 0x17be717a, 0xff33ef48,
6820 0x83ffd7c5, 0xe29dbef1, 0x75fe75dd, 0xaf8bfd57, 0x1fbc7fbb, 0xeef1c39e,
6821 0xc0f57386, 0xfce0df0b, 0xab9ca87e, 0xf7e717fd, 0xeaafd6fe, 0x79307fe7,
6822 0xf5a0c8de, 0x03ad49f3, 0x2a6b8b14, 0xa0ce1c0e, 0x72187fa5, 0x3be61e30,
6823 0x18c39f99, 0x125fb7e7, 0xc164fdb0, 0x891d7684, 0xc75db817, 0x5cc1a1ec,
6824 0xa4bc187f, 0xc190f510, 0x7a641e43, 0x83a9e483, 0xa43fbe73, 0xcc62f02d,
6825 0xcb7cc902, 0x95f7790f, 0x0bb7af3c, 0x1f10277f, 0x4e0e411c, 0xa043f7fb,
6826 0x22190e9f, 0x534afea2, 0x745f5bd4, 0xe5efb3e5, 0xb97ece8a, 0x67b7a3c6,
6827 0x76f512f2, 0xdfde54cf, 0x3fe6c234, 0x428421cd, 0x87930e14, 0xfc1126fe,
6828 0x962f939c, 0x79f34089, 0xec02bfc4, 0x7d0ea984, 0x19c18f7f, 0x580fc68c,
6829 0x16bb6964, 0xaf16dffc, 0xd25dfd80, 0x62794265, 0x0e9016c9, 0x984bd546,
6830 0x1ee4dd7f, 0x719e7007, 0x7733aec5, 0xfa97f013, 0x528f1614, 0x5fdefcc0,
6831 0x44ddf77f, 0xf0e2e388, 0xaeffa22b, 0x036eff03, 0x7ae8db09, 0x18244917,
6832 0x4efe0097, 0xf3afbc81, 0xf0f3ea77, 0x68a4e3f3, 0xdfabe73f, 0xb3fe1d1f,
6833 0xee945dd3, 0xdbb0a7df, 0x1c08e90d, 0x53dad25e, 0xe0ced6ff, 0x84857815,
6834 0x6ef3b186, 0x2e7340b1, 0xeccca974, 0xd97f5dee, 0xccf6059e, 0x71d19ea4,
6835 0xa0471f8c, 0xfae0197e, 0x89e259e5, 0x1f803af3, 0x79e1c787, 0x19d121d7,
6836 0x0b6bde2b, 0x819eb3b7, 0xf69a5073, 0x115a9134, 0x41127df4, 0xc9b05dff,
6837 0x88c53642, 0x4d94483b, 0xe39c5cfc, 0x3988fe8d, 0xe36787e0, 0xe34da22f,
6838 0x9aeb78b4, 0xdb1a4a7e, 0xf3f00f17, 0xe21ce6be, 0xd82f851f, 0x2ddf0075,
6839 0x82bcced6, 0x923b7c18, 0x81c66fc3, 0xbe9ed0af, 0x04d1bdac, 0x93597e7c,
6840 0x969e7749, 0x3dfd7326, 0xbcc26493, 0x3ab01c66, 0x872f01b3, 0xd9c42f44,
6841 0x513fda05, 0x83ce31fc, 0xfe84f08c, 0x9b7a8fc1, 0xed7846ec, 0x00165b91,
6842 0x6c7cf75c, 0xed676021, 0x62cb6a56, 0x0a4ff3cd, 0xd222e79b, 0xf4d8e772,
6843 0x4ef83d7f, 0x278471ea, 0x44d2bd83, 0xd2fbaf90, 0x3e3a411f, 0x408499bb,
6844 0x037d831e, 0x336ce172, 0x8280fdc1, 0xd3b041e4, 0xa55fbf28, 0x692fdfb5,
6845 0xec0cf6db, 0x82ed9523, 0x95cb5c1b, 0xfe02a752, 0xbc5b40b9, 0xc33b7208,
6846 0xba21c6a3, 0xe1a4dcc7, 0x0964db8b, 0xc2707be1, 0xdc615b9e, 0x0214bb4f,
6847 0xc5ef9afb, 0xfee40b88, 0xc859eda7, 0xebadfd07, 0xdae4d5f7, 0xc3f412a9,
6848 0x1e919ae4, 0x74db3746, 0xff442bf9, 0x19afe020, 0xde25cee6, 0x96fbf818,
6849 0xcb05d9d3, 0x67ffd0b7, 0x550dedf2, 0x02c5f9be, 0x2cbd1f0d, 0x23557db3,
6850 0xc96392df, 0x2782c5b7, 0x78bee019, 0xc064f0ef, 0xf2c3e2eb, 0x6df258c0,
6851 0xdf3b356b, 0x8fc78e7a, 0xf952b4f6, 0x7c8d23f6, 0x2df2a56b, 0x8b7ff9c6,
6852 0xcf5ffaac, 0xff42df23, 0x15b7fc3d, 0xf58c5be4, 0x53f0e41e, 0xf6d8dbe5,
6853 0xc6df2863, 0x71749ab6, 0xdccbcf96, 0x7cafd99f, 0x04de0613, 0xd921d4fa,
6854 0x3f418f6b, 0xf6feb95b, 0x819f8f1c, 0x7dce4071, 0xdce503f5, 0xe72a173b,
6855 0xace09bfe, 0x3bc5b9ca, 0xf69fc608, 0xe72643a5, 0x72a6ef16, 0x647a004e,
6856 0x5ef16e72, 0x0638fcc2, 0x8faa36f9, 0xbf58237c, 0x07dacc32, 0xb91fd2da,
6857 0xe997f68d, 0x5a16bd93, 0xef2a333f, 0xdde569c6, 0xbbc9fd57, 0xef261743,
6858 0x47797076, 0x9030d8e5, 0xf0fa46af, 0x74e3ebb6, 0xd13f8cf7, 0x97e07bfc,
6859 0x673c4557, 0xcec4dd7a, 0xfe34fe05, 0x57d03644, 0x33e6c281, 0xd7f46142,
6860 0xfec41d5d, 0xd6c8bca7, 0xf160e157, 0x4cad95bb, 0x166cac3f, 0x6bfa1e42,
6861 0xf0af84de, 0xaf64a8bc, 0x7e699240, 0x27d599a6, 0x24e7a94f, 0x86867a64,
6862 0x96e6161e, 0xa1777fa1, 0xbfe02c44, 0x9de4732d, 0x2cb63d02, 0xcb7bf997,
6863 0xc392f7f8, 0xdfc0ab9d, 0xc05eb259, 0xee353273, 0xecbf8d50, 0xbede5e73,
6864 0xc681fd0c, 0x3c19f373, 0x33c6664e, 0xc631a842, 0x66d97fb9, 0xa71a7e7d,
6865 0x276299e7, 0x26bc8bc2, 0xe0c5377a, 0x2f5eb51f, 0x38710e9c, 0x9fb88935,
6866 0xc289c2f6, 0x17de93cd, 0xd3d3144e, 0x70a29233, 0xae957929, 0xf5ffbb37,
6867 0xae3370aa, 0x9677f55b, 0x83fa7ef1, 0x3ee70a83, 0x2770e7eb, 0xd2728424,
6868 0x95ab8f08, 0x16683f5e, 0xba50a7c4, 0xfc133941, 0x0d7188a3, 0xd62e9305,
6869 0x8eb843dd, 0xed564fd3, 0x8c7029a4, 0x7de2133d, 0xfeaddce1, 0x6e21978e,
6870 0x9e5bdc6f, 0xaf4ed84c, 0xc3f66098, 0x6b16dbf9, 0x4aa0e504, 0x87408d87,
6871 0xf0f7ae14, 0xaa0cf67e, 0x61768c9a, 0x3d06e09b, 0x22b61024, 0xae14035c,
6872 0x20242f70, 0x2806fc31, 0x1dff023d, 0x8305ff5c, 0x03c15ee3, 0x753c80fe,
6873 0xd0bc02bf, 0x0ced59fa, 0x8090812f, 0x1126c978, 0xd657bbf4, 0xc030de0b,
6874 0xe111adaf, 0xfa67caa7, 0x49e2d0e3, 0x2c52bf43, 0x9a4ac5fa, 0xd78cb2fd,
6875 0xfdae619b, 0x8cf3d033, 0x88d264a7, 0x7dffa6e0, 0x279f3d1f, 0xa788c3fe,
6876 0xb6bc39c7, 0x001d3c02, 0xbbd308b7, 0x3de15fc2, 0x203cb515, 0x9cf07505,
6877 0xefb9e8f2, 0x1538d785, 0x20c7405e, 0x89e7dadf, 0x136c2f90, 0xbef480c8,
6878 0x307385eb, 0xec97bf2d, 0x7ffac63d, 0x1892f04c, 0xba60beeb, 0x8b9e87ee,
6879 0x7f82dd29, 0x36ba3fbd, 0xe151a9c2, 0xe7a726fb, 0xaf23593f, 0xef3d0164,
6880 0x49cf9015, 0x3ceebc7b, 0xf4c2bf6b, 0x4a562d88, 0x91dd74f7, 0xa377b2c3,
6881 0xd83cafa7, 0xf60be1ce, 0xd01ef683, 0x8810b0a5, 0xc16cdc0f, 0xc79c2f38,
6882 0x6a9fa630, 0x2b56f3e5, 0x76537819, 0x7987fdff, 0x47e9fdff, 0x8c0c7e6a,
6883 0x6dcd7107, 0xd151bc74, 0x83fb8cf1, 0x6f9ff76a, 0x3972af5d, 0x4baef7f7,
6884 0xc687e71d, 0x074804c1, 0x878d55e2, 0xc7f82239, 0xe5cfa0c8, 0xae3e920b,
6885 0xd6e5c22c, 0x1fffdc3f, 0x927fafbf, 0x4e7bc6e2, 0xefd5ba77, 0x02cfa46e,
6886 0x41e7e137, 0x7d84df13, 0x3b1f53ff, 0x9136caf7, 0xff611323, 0xa0132c98,
6887 0x915f4fab, 0xe9f96fd1, 0x79671654, 0x2507abfd, 0xcf5cdd70, 0xf5c8a162,
6888 0xb3b404e3, 0xc7ae875e, 0x216e1e83, 0xbf0891be, 0x954fb82c, 0xc53b54d1,
6889 0x733af943, 0x5206a873, 0xe24894ef, 0x936f009f, 0xeb780244, 0xe2980df0,
6890 0x3f3bf9a0, 0x32e01922, 0xb601faa3, 0x06443ccf, 0xbe09bd42, 0x8cc66881,
6891 0x8decfd6f, 0xc63ce91b, 0x3d7a22bf, 0x83ccdeb4, 0xfaa1070e, 0x1306a8f4,
6892 0x35e06bf1, 0xc06a8481, 0x43fe346f, 0xef308ddf, 0x40efaa62, 0x7b717efc,
6893 0xf20b8d63, 0x0fb6020d, 0x2e79fd04, 0xf5ad9eba, 0x0e5de49f, 0x83d68172,
6894 0xac0d026e, 0xf049a05e, 0x616a4842, 0xe5053afb, 0x17809346, 0x0486b6bd,
6895 0x86fd6162, 0xaddfb42c, 0x367db40d, 0x3db45fec, 0xc9f4dbf4, 0xdc82371b,
6896 0xf6c4f3a1, 0xb63ceccd, 0x00f3b690, 0x81dd34bf, 0x083495fd, 0x1419ee04,
6897 0xa97db337, 0x0bd915f8, 0xd7fbade5, 0x9d3b7ee3, 0x0e9a978e, 0x2a7850fb,
6898 0x12c8d7de, 0x6d8f78dc, 0x5fc450fa, 0x23f8610f, 0x1c984389, 0xdb9e7813,
6899 0xf7deaa3d, 0xe430f32b, 0x32ef4283, 0xe7ed0065, 0xd303b94f, 0x9f57484d,
6900 0x7da7a028, 0xa7ede148, 0xc79d7ef0, 0xfdcc1c29, 0xecd4e940, 0xe1e6cd8b,
6901 0xdb617ed8, 0x5a7f8c24, 0xfcf00a44, 0xa678c67e, 0xa576be6f, 0xbafe0435,
6902 0x10c8e4d7, 0x4af07ef8, 0xdeef7e33, 0xf770e4ca, 0xcff44ed0, 0x0990689e,
6903 0x69a82fdc, 0x9c5e5110, 0xbcf19668, 0x464c7c5a, 0x95b45db9, 0x1b071fe9,
6904 0x4027bf58, 0x393f036f, 0xd17cd394, 0xfbdb8116, 0xf6ab4e4c, 0x9d9ba167,
6905 0xb772abbb, 0xcfbbaf82, 0x4cb7543e, 0xca359201, 0x8f2e0adb, 0x02a4a94b,
6906 0xddca3342, 0x7577380a, 0xe31a5f01, 0x3b511c83, 0xfc20e806, 0xe575d215,
6907 0x3b01322b, 0x2ba0f846, 0x6a7de60f, 0xee7e80af, 0x0f82edf1, 0xdf8bbdce,
6908 0xff508732, 0xfb9bcd0e, 0xde5fd80b, 0x55081336, 0xa0780e3d, 0x1cd72a72,
6909 0xe86fcbf9, 0x5baf53f7, 0xd2841220, 0xbb843ccd, 0xbd99df1a, 0x6471c589,
6910 0x04975ebf, 0xd4c92cf7, 0x8a072801, 0xd7e245ea, 0x825389c8, 0xb29fc6ef,
6911 0x8dadc1fd, 0x6a56cce3, 0x3d7f610b, 0xd1f2666a, 0xd88649b3, 0xccd2b208,
6912 0x0fb534e4, 0x64b2fe30, 0x4524baf7, 0x7b250743, 0xf48925d7, 0x071e2afb,
6913 0x2bfb0351, 0xb0a2576d, 0x09f64a71, 0x38cd46ee, 0xbf6a3f6a, 0x6ed66eca,
6914 0xf6965ef8, 0xcc097fd7, 0xb9f9d70f, 0xd8c2f202, 0xfbf19f4f, 0x3ff727e9,
6915 0x7409d5cf, 0x89afb95e, 0xfb9ca418, 0xdae1f4c1, 0x55350073, 0xde7215e3,
6916 0x069f1130, 0xb17fb97e, 0xdf069f11, 0xdf28e3ad, 0xd75dfc53, 0x02ac8426,
6917 0x15298fe4, 0x037798d9, 0xff72579f, 0x7654e573, 0xf19ad3be, 0xfbe00afa,
6918 0xd202d9e9, 0x95fa0903, 0xafa88901, 0xb8ce2079, 0x2fb59b28, 0x1f81eda2,
6919 0xfe33d75b, 0x03c272a4, 0x61b2a472, 0x6fd61e5d, 0x7fd03c12, 0xd43ce36b,
6920 0x45738a47, 0xc74de582, 0x6e2a3f50, 0x7c08963b, 0x0eb6f94c, 0x89ca81f4,
6921 0x71c83766, 0xfe551f95, 0x05c78d7e, 0x0c7b8b13, 0x0067e3c4, 0xcbec0df3,
6922 0x4c2be2d7, 0x199a07ae, 0x1972063f, 0x55b6bebf, 0x085e1586, 0x9f3f237f,
6923 0x55f8ccd8, 0x3ce6ec7c, 0xb45ca7b8, 0x1ca7c589, 0x80a2986c, 0x24227d3e,
6924 0x97d37ee0, 0x6ade99bf, 0x811aefe4, 0x543f7bed, 0x5bf954bf, 0x73fa63e5,
6925 0x4e578c1d, 0xb5ee14f9, 0x867af919, 0x3be7f2dc, 0x7faf7ce9, 0xce87ae96,
6926 0xef8fca77, 0xe46a7576, 0x4127cd24, 0x716250be, 0xa95caa3c, 0xd7bc5890,
6927 0x619f9e0f, 0x7acd1bfc, 0x734ac8ff, 0x6e6b8b3c, 0xcfee9192, 0xf87d9fc7,
6928 0xf3f902ec, 0x7ceaf942, 0x2f8ea9fc, 0xb3f7d5ee, 0xb19bd392, 0xd70a6ebf,
6929 0x1feb8530, 0xb8c09f9a, 0x3e9f8fb1, 0x53f00336, 0x39d287b6, 0x93b357d0,
6930 0x49ce4184, 0x4aafdc21, 0xc61f455b, 0x9ce14abf, 0x3e5a9d1b, 0x653e7166,
6931 0x9e9139cf, 0x439bb74a, 0xd2fb69d3, 0xc58c1f9d, 0x11e58bb8, 0x3e0a438c,
6932 0x60e5f5cd, 0x83e058e7, 0x1bc58952, 0x00c2e519, 0xe8673b0b, 0x059f6dda,
6933 0xb33613eb, 0x2da5fd7b, 0xcd66c8b7, 0x22cd84b9, 0x1cf0f5ab, 0x18e94830,
6934 0xfcc255ee, 0xd5c9f7b4, 0x2daea338, 0xb6944e4c, 0x960768c9, 0x0dd6de6e,
6935 0x6fa5a371, 0x15dfd199, 0xc609fcd8, 0x6e794fc1, 0x0253fa2b, 0xfceea26d,
6936 0xdebc4fac, 0x866c3166, 0x0ad6b378, 0xf9a3ef3c, 0x896f9863, 0xbe7ab71d,
6937 0xe7b2b2b8, 0x520ceef6, 0xfefd9610, 0x97c81729, 0x5c9b1dd3, 0xf9b7b718,
6938 0xfb65e3fb, 0xdcb5e7c4, 0x79f1bdf7, 0xca17e1a7, 0x862d1338, 0x03cdc6f8,
6939 0xf3a48f50, 0x718829cb, 0x97abd1ce, 0x037cfd6f, 0x6d778fc4, 0xe601b33f,
6940 0xa7edfe5b, 0x887e201b, 0x7ee2b3ec, 0x08fa7817, 0xedaadfc6, 0x7ee1627e,
6941 0x614f2d8f, 0xdbf772dc, 0xd6f42f66, 0x1a44f7bd, 0x6f758fc4, 0xfc092afb,
6942 0x4ef64b96, 0x92eebf43, 0x4992531d, 0x4d42fd8c, 0x17436e81, 0xc46d3710,
6943 0x83d6c1d7, 0x31f4e718, 0xbfc837c5, 0x96cb78de, 0xeabf160a, 0xcd9671e1,
6944 0xfbd3e3b1, 0xdeb655c4, 0x2095fd78, 0xfe995bf7, 0xcaf8de78, 0x7f1e2837,
6945 0x6bf80174, 0xb102fd56, 0xfc31f7f1, 0x76e21e32, 0xbcfbf8f5, 0x8fe3d175,
6946 0x80eb5942, 0xc32be37e, 0x35370017, 0xc5927dfe, 0xbe016d57, 0xc60cfed9,
6947 0xa6de02b3, 0xf9ff607b, 0x0dee0d3c, 0x7323949c, 0x5ed93ef0, 0x09e21bb3,
6948 0x89bef74b, 0xe3bdd3fc, 0x1343f475, 0x4dde871e, 0xdc587f7a, 0xd9d7c0b0,
6949 0x997164e4, 0xb710fe1c, 0x77e171e9, 0xe8c99f1e, 0xecdb8d58, 0xa7735e2f,
6950 0x6ad9e985, 0xd3457e5c, 0x31fe3cbb, 0x17212f8a, 0x7bec74f0, 0x70a811ef,
6951 0x1c397370, 0x1d8e3f8d, 0xa71bdb17, 0xf805f1ce, 0x37a87d83, 0x87e698be,
6952 0xe8dfa264, 0x1e43124d, 0xb8b23774, 0x7f596ee5, 0x1f8a33df, 0xcdbc8f16,
6953 0x0ba1a7c8, 0xdf3e438b, 0x7c287ffc, 0x33f28236, 0xba9c2fb0, 0xc72d8ebe,
6954 0xff7ce0df, 0x5967df77, 0xb3ef1828, 0x63d027fc, 0x0531eb45, 0x3b5ee0ec,
6955 0x8bb7af9b, 0x9ebbd5fb, 0x759e3116, 0x9441cb55, 0x517946e3, 0xc458ef09,
6956 0x0b71ef98, 0xd8dbc3d7, 0xddb5d13e, 0x7ed07219, 0x46ec0eba, 0x3e6cae7a,
6957 0xe09c40a6, 0xaf7f9bcb, 0xc629f3b0, 0x844fb03f, 0x7aeff334, 0x1658ff76,
6958 0xf8fccd6f, 0xe33e71c6, 0x63da04e3, 0xfe68138f, 0x594e3744, 0x3b7145b0,
6959 0x69de3fce, 0xf40b77c9, 0xe983ba77, 0xc45ba783, 0xb9f758fc, 0x66fbe4de,
6960 0x743d7bef, 0x4177c4bf, 0x101dec9c, 0xfd4365d1, 0xf7338972, 0x4844b8ad,
6961 0xa9ef8c15, 0x81e3c659, 0x014de97e, 0xaf38d77c, 0x95df3025, 0x9f8d5f00,
6962 0x09fb7647, 0x4a72a5e8, 0x15f83641, 0x4946f28c, 0x06909134, 0xf99c4bff,
6963 0xef3c1ec9, 0x7c010f08, 0x2138cd1e, 0x19efbf43, 0x49ef54fc, 0x9d325564,
6964 0xc1417bdf, 0x4bf68cbb, 0x6860febe, 0xff6fb381, 0xaf7fde6a, 0x552bf3a8,
6965 0xc147239a, 0x582f212e, 0xdc41be31, 0x17f7c567, 0xb8ac1b02, 0xbe3b83de,
6966 0xebf5127c, 0x9d84cdc7, 0x85eb50fb, 0x9b915fd2, 0xc76271f5, 0x06fe1b97,
6967 0xa63433fa, 0xa06d17e3, 0x686ec1f5, 0xd39da3b6, 0x2c6e3db3, 0x5e8a45f8,
6968 0xc80667b8, 0xa33b22b3, 0x92e7a2c7, 0xbfb43543, 0xfe5903e3, 0x78a1d6f8,
6969 0xbb6cbfdf, 0x0f0ce313, 0x0955d8ee, 0x73f752fb, 0x52fb0276, 0xcf5c0bf7,
6970 0x1fbf867f, 0xb47b2f54, 0x4425c6f1, 0x71ef68f2, 0x959e4194, 0xfc107de3,
6971 0x047ce1c9, 0x38b6aafe, 0xf541ffbc, 0x1f3f5d5f, 0xbcbb91cb, 0x41c1c748,
6972 0x784bdeec, 0x6303c810, 0x4afcb53d, 0x8f7e30eb, 0x4473b698, 0x489407eb,
6973 0x0ed7cb21, 0x03a4f262, 0x656b5feb, 0xf796affc, 0xcfd597ed, 0xd5d30eb7,
6974 0xf257db53, 0xf48c41f7, 0xe055b37b, 0x2e6fc1fe, 0x45fef589, 0xf7e3f98c,
6975 0x6824099f, 0x9b653d02, 0x8225df15, 0xdf10f37b, 0xe76153be, 0x30aee55a,
6976 0x87b23fbe, 0x5b72e3cb, 0x1943df18, 0xf501e7c4, 0x9d2c4f21, 0x56bbe2cf,
6977 0xde04acbb, 0xc178a9c7, 0x577c03e9, 0xf8f2fcec, 0x8e21b2ef, 0xd4718ecd,
6978 0x1cfc2f15, 0x1cc2a0e9, 0x10fc039e, 0x1b2666d9, 0x1db7cf81, 0xed7e034e,
6979 0x0969c392, 0x575e73df, 0xbc3662d1, 0x71d6c01f, 0x0afebaba, 0xdeace7b8,
6980 0x47ed2ca7, 0x656b3cce, 0x585fe87e, 0x78ad4b7d, 0x677fadae, 0xacf574e7,
6981 0xaf57b82c, 0xc4b52fd6, 0xad6b8b96, 0x4f763ff2, 0x5ee7d1d8, 0x40eb5ae2,
6982 0x923a63d0, 0x4953efc0, 0xe7906ef5, 0x87d39ba5, 0x80e09f80, 0xee77bd55,
6983 0xe8fd8389, 0x7b41ec80, 0x3eed521a, 0x9bdab273, 0xff008d25, 0x892ca8cd,
6984 0xf1a7a3ae, 0x0441c293, 0xb3ad0ee2, 0x0dbdc962, 0xa3c23b56, 0xc5f662d4,
6985 0x0cf8d7ba, 0xc107d7a7, 0xc6c71fe8, 0xc750fe03, 0x5087203d, 0x79b70f0e,
6986 0x2ed43f58, 0x9b65ef82, 0xdee96767, 0xb16a90c5, 0x8453e51e, 0x53a90967,
6987 0x5bf235b2, 0x6964af1d, 0x05949676, 0xeaffa5df, 0x8a3157a5, 0x444c1267,
6988 0x30e250bd, 0xbaa97526, 0x5c9204fb, 0x29f80160, 0x892dc0a4, 0xc8b52a40,
6989 0x82d236ef, 0x5baa83a9, 0x2aa8fdec, 0x64f27202, 0x0417bbef, 0xeebc28d3,
6990 0x1c1fb946, 0xe9c5c84a, 0x13dfff70, 0xafc0d6e7, 0xf9c2eacd, 0xc22aa598,
6991 0x3774c5e4, 0xd04223e8, 0xf4a3be4f, 0x9f9d5354, 0x7f48f405, 0x0cff707c,
6992 0x3f3a0f4d, 0xafe5fb97, 0x74a20f40, 0xfb59deca, 0x50d50931, 0x28f84310,
6993 0x132755fa, 0x9ad83ef6, 0xded688b7, 0x6fe72bf8, 0x728fdc12, 0x3fa241cc,
6994 0xb1079a11, 0x26b6f20a, 0x385cdbee, 0x49b87447, 0xbb42f418, 0x34ed8483,
6995 0x4e968c75, 0x95dff96b, 0x3a1af34d, 0x97d44f75, 0xca82f91b, 0x2db8c335,
6996 0xefda3f08, 0x3f7e8667, 0xd9fbf433, 0xc2abf5f7, 0xe8d96029, 0x5609f785,
6997 0xb8701756, 0x1c2cf1b1, 0xa33e146e, 0x62337de0, 0x79f979b2, 0xc6d5c238,
6998 0xfa866367, 0x6c83af14, 0x07a708e9, 0x2045f6e2, 0xd624966e, 0x577bb013,
6999 0xa69f6c08, 0x4d0e053f, 0x20b6e23b, 0xc7c7de1f, 0xf4636419, 0xef5bdeae,
7000 0xe78adf5b, 0x5bea7d1a, 0x8b6fabfb, 0xdfd9df5d, 0xe731ec7c, 0x4ce543f3,
7001 0xfe6f0be5, 0x7b61ce09, 0x829b8de5, 0x6f274732, 0x9c28d906, 0x7f8fe22a,
7002 0x985f89db, 0xa21968de, 0xe80d9fc7, 0x6d8fd295, 0x11bbfe84, 0xcbd1fdef,
7003 0x9a0ebe3c, 0x75d2a477, 0x3f8f94fd, 0x639d89b5, 0xf984b6df, 0xe7b9a8dd,
7004 0xf2b7fa83, 0x14b53ffa, 0x18e0ffa1, 0xb6e9177f, 0xde17a67a, 0xe788af76,
7005 0xfdde7dcd, 0xff285f81, 0x0854bedc, 0xbd63d385, 0xe09a4463, 0x3e5cd47e,
7006 0x205df1be, 0xade4f13f, 0x0bbd6311, 0xbd4ce8c4, 0x6f7c6557, 0xe0292160,
7007 0xbfe93def, 0x91bab26f, 0xd61e410e, 0x4bee8e8e, 0x8e9475c1, 0x74a49f41,
7008 0x70ece70c, 0x3ce3063d, 0xf38b0a5c, 0xe78a18e8, 0x3b3caa63, 0xe1c4f1eb,
7009 0xd34deafe, 0x78b817bd, 0x5e3927bc, 0x73a5af23, 0x2b7bdd36, 0x0537b235,
7010 0xee7c95e4, 0xa6a1e232, 0x1e8d42af, 0xea9ca68f, 0x10ccc8a1, 0x277284a6,
7011 0x9c810a45, 0xa405dc93, 0x9958f408, 0x5f5aa7d1, 0x57acbc49, 0xfe8d7c6f,
7012 0x878801bb, 0x3be2e5d2, 0xd728c93c, 0xe00b05ed, 0xf5cae893, 0xe97d1dfa,
7013 0xad95b821, 0x9dd606bb, 0x353d77de, 0xfa8bd78a, 0xf7de84f3, 0x3f302c69,
7014 0xd379ecd1, 0x0ffbf303, 0xa51f8099, 0x27bc7c2f, 0x677e1443, 0xde318343,
7015 0x3e9b8c43, 0xdf57c612, 0x9d535c45, 0x2bade782, 0x2b897bf8, 0xfe6147aa,
7016 0xe59efe7e, 0xa60f6aaa, 0xde2cfc2a, 0xcfc77c5a, 0x6ff58232, 0x24fc7371,
7017 0xfc7c389a, 0x52592fa8, 0xd01cf0aa, 0xc30aaeea, 0x086459fb, 0xda6027dd,
7018 0x9f845aee, 0x87e826e2, 0x6f31f5a4, 0xe54d3c86, 0x0f88d1fa, 0x8a455dc9,
7019 0xddbe7968, 0xcdc020ff, 0x7ba419ea, 0x329cd01f, 0x03df7bec, 0xf5a7a5ec,
7020 0x72262e4c, 0x27c2327a, 0x65ef6151, 0x9fd474aa, 0xe3c3555e, 0xf6ae1f74,
7021 0xdfc35a62, 0x7781aa81, 0x3d48147f, 0xedc81f98, 0x470a1ac4, 0xdf08fef8,
7022 0x73aa6b37, 0x972cfcb1, 0xaaa68957, 0x25c032fd, 0x66ff3081, 0xc90c9062,
7023 0x14042c21, 0xc482527e, 0x9cf57903, 0xe6c69dd0, 0x7441e9cd, 0xdc77864b,
7024 0x5e008f3c, 0x26cb0eea, 0x4b8b93f0, 0x681f25af, 0xe59c59e8, 0x99bf078b,
7025 0xb00bf0e8, 0x78003dff, 0x4759f3a5, 0x96ef85e7, 0xc9587a72, 0xd39abef1,
7026 0x1f407dc3, 0xd3907d34, 0xfae8afc5, 0x65e35f21, 0xe6d601f7, 0xc4b778b3,
7027 0xc77f130c, 0xf1b44c2c, 0x16def164, 0x2275d0a2, 0xc5307a8f, 0x5bc8ea77,
7028 0xfb17a466, 0xa113e268, 0x43bbadfc, 0x82c91dec, 0xe337d854, 0x272377d5,
7029 0xe367e27a, 0xc4b0d545, 0x991373df, 0xf311d1dd, 0xef1ac67d, 0xefd80b01,
7030 0xeec7cdfd, 0xa4afa5f5, 0xd9ebd9e3, 0xfe01c5bd, 0x688bd982, 0xf54f51de,
7031 0x8ce5026f, 0xde741d2e, 0xc67d1a45, 0xbffd8fde, 0x51cd7ed4, 0x7be7c51b,
7032 0xe45141b0, 0xb87ebaff, 0x614be015, 0xc73f01ed, 0x2a4172c3, 0xf1c3fff0,
7033 0x8735fdb1, 0x83d2326d, 0x1d32fb2b, 0x3ec9d73d, 0x989ee76c, 0x3afba3a9,
7034 0xa612772e, 0x577dd04e, 0x6defcce5, 0xb12eef4c, 0xbcc2cffb, 0xc5d1ce92,
7035 0xbc4a7e51, 0xa9dcb621, 0xdc209591, 0xc319afdf, 0xa6705ce4, 0x3eabf4c2,
7036 0xa7c98472, 0x6f32e4b3, 0x645f4350, 0xf03d4114, 0xee8a998b, 0xc035c1dd,
7037 0x7e5e941f, 0x057ee9cd, 0xc54d01f0, 0x4dd20a11, 0xda1374c2, 0x5f38aba9,
7038 0x68f9cfdd, 0x87a3e72d, 0xc2467f80, 0xdf8cae3b, 0x051de224, 0x8b8d48fb,
7039 0xc0258fbd, 0x8d49b4ff, 0xe85cfe6d, 0xb32de6af, 0x350fe700, 0x11752f92,
7040 0x977e29e4, 0xef8f307b, 0xedeb06ea, 0xbbf1589e, 0x9293ed4b, 0xc95e14ec,
7041 0xdfbf8676, 0xfe2167d4, 0x316f6e2c, 0xd8724bac, 0x19afaed0, 0x658e2969,
7042 0xbdecd81f, 0x53b74ef0, 0x9fc80f78, 0x817f6bd0, 0x666ea17b, 0x37fdc20e,
7043 0x06399f70, 0x33b18cfd, 0x04864079, 0xff0d08c9, 0xdcf7f1d7, 0x46482788,
7044 0xf2c0e469, 0xf808f38b, 0x7ff2fa77, 0x136ff23f, 0x02357f93, 0x780c57df,
7045 0x5531f755, 0xd78049fe, 0xb9e77d01, 0xdd5ca2f2, 0xcb997b3d, 0x3cbd636f,
7046 0x4f9d9dbb, 0x2fc46f11, 0x70a72df4, 0xce6bb3ca, 0x09c49495, 0x5d95efbd,
7047 0x461d6315, 0xf61277b9, 0x9225903f, 0x5905df1f, 0x191e78a8, 0x8fe4f20f,
7048 0x3fa5fe2c, 0xaf1d40fd, 0xee315ce8, 0x72e785f3, 0xae299f71, 0x20fe45cf,
7049 0xd8d78de0, 0x7e1a2749, 0x9dbc02e6, 0xa3e7e7a8, 0xe208720d, 0xbc6ff652,
7050 0x14d9a1e7, 0x88370b9e, 0xd7fefeec, 0x6a277ddf, 0xb6481be2, 0xf53af507,
7051 0xa113b43d, 0x73da5d3b, 0x58dfc2ec, 0xf62fa07d, 0x3614cfb7, 0x6bdfb6c4,
7052 0x53d057e0, 0x1e801f29, 0x4881f54a, 0x5f85f418, 0x08bdf15b, 0x68dc1f35,
7053 0x540ef98f, 0x195a7dbe, 0xddbe67d0, 0xc4a42777, 0xfafe8091, 0x8ea1e6fe,
7054 0xa67c1c7b, 0x28f64e70, 0x70a5b38f, 0x9ff3a99f, 0xe3b273b1, 0x2c421fdc,
7055 0x78db94fd, 0x729fa7b9, 0x21678b17, 0xeae5d8ee, 0x3b714e7c, 0x7b46e170,
7056 0xfd8c7968, 0xefbf217c, 0x479f90b7, 0xd53ff8a8, 0xba3137ab, 0x3f2ffb51,
7057 0xdfe18a37, 0x53c26740, 0x3eae9063, 0x7fa3243d, 0x4aea784d, 0xf2a52f7c,
7058 0x97eb059c, 0x415fde8b, 0x4d79161c, 0xf3bbba44, 0x873c38f0, 0xc3bc32ea,
7059 0xb7f387b8, 0x2b9e169a, 0x8599e9d5, 0xec0a05a1, 0x2ae785cb, 0xde211e91,
7060 0x1397ee11, 0x934bf6f2, 0x13574e24, 0x6991fda0, 0xa2bd69cb, 0x64bf464e,
7061 0xfd12b062, 0xef768d84, 0xdae431fd, 0xe747bb1e, 0x2cea2837, 0x2389fec7,
7062 0xe7351248, 0x7bf90bf5, 0xd8e745e1, 0x1dc4847b, 0xcf402924, 0xe944de5c,
7063 0x6c6eff52, 0xcbe18997, 0xf857deb8, 0x5de95f3a, 0xd67e84ef, 0x5eb663fb,
7064 0x7517cfbe, 0xf5d61ae6, 0xd6b1f1bb, 0x44cf5d15, 0xdfce5f6c, 0x31372df9,
7065 0x9fe5abbc, 0xf4d5f1f3, 0xb82cf578, 0xf84a4361, 0xa185903b, 0xff78153b,
7066 0x3e21b0a8, 0xb3acd041, 0x5d56fea8, 0xfd61495c, 0xaaff7c3c, 0x329e61a8,
7067 0x7a47235f, 0xecfc14f1, 0xa22349a5, 0x81fcfa78, 0x1dcb699e, 0x1c14afb0,
7068 0xfe3b3e03, 0xe79cc564, 0xf0cbf409, 0x8e095276, 0x72b942ad, 0x3dd62ba7,
7069 0x788dcf94, 0x1b78e7ab, 0x35a32411, 0x97c54672, 0x4df1fdb1, 0xf9c17765,
7070 0xecf5f1f4, 0xe5fe8f75, 0x1a7c6c4c, 0x3076e8e1, 0x71e9a9f8, 0x2ffb2fba,
7071 0xeb978e08, 0x85fa9be2, 0x0abfc723, 0xd53bf527, 0x1c0eacab, 0xa37bb097,
7072 0x0417b9f5, 0x8cf8e8bf, 0xbe2a4e3e, 0x7e41eb91, 0x7c093951, 0x07c9ea7a,
7073 0xe5db6ac6, 0x840d27db, 0x85ed4871, 0x6fdd8f9d, 0xfd41a7f7, 0x21ef64e0,
7074 0xd15bca0f, 0x5dd7435b, 0x7768f712, 0xdfab5718, 0x935656bf, 0x4a5fc12b,
7075 0xc12b87ed, 0x05b5436f, 0xe6a8a3d4, 0x847d05e0, 0x7ac5f156, 0x83926a17,
7076 0x5656b3f9, 0x95bfa157, 0x0dc48258, 0xf8c23d7e, 0x42cc9c92, 0xd0e497ff,
7077 0xec8a01eb, 0x4dbf8377, 0x6591f7e1, 0x3d26bfc9, 0xc4d9ec1b, 0xbe06a08c,
7078 0xbc583957, 0xc594dac4, 0xb7438841, 0x38719f80, 0xeace37fa, 0xa517fbec,
7079 0xdd280385, 0xda7dcfa9, 0xe5cbe846, 0xfe8216c4, 0xbbf4d1b4, 0x74891e76,
7080 0x4c7dbade, 0xe2c9170f, 0x890f73c2, 0x8715bf70, 0x7282fd07, 0xc3973578,
7081 0xdc2eedcb, 0x645d567f, 0x8ea0fb42, 0x0b7ec3fb, 0x8b84307e, 0x84327684,
7082 0x257d40dd, 0xb0eb882e, 0xd0447ac2, 0x7798c3db, 0x22328bc2, 0x4025b13e,
7083 0x04789e3e, 0xe1200fc8, 0xf687a055, 0x0bbcea4c, 0xfd58a7be, 0x5fbf01b3,
7084 0x151c76a4, 0xe05a0fc0, 0x5ce004bf, 0x3c33062f, 0x62e3feb4, 0xa5ea0324,
7085 0x12b7a2d1, 0xc4117a58, 0xe735fb41, 0xce1dec2b, 0x9bec5e68, 0x64a968bf,
7086 0xfaf86f38, 0x2ff96d12, 0x0762beac, 0xf656fbec, 0x07e24d7e, 0x9ab9ca02,
7087 0x01773f5e, 0x71a9dbde, 0xd23d7f30, 0x21d5d005, 0x959f4fb6, 0xe809713c,
7088 0xf5951b3f, 0x5e1e6ea2, 0x76e25e5d, 0x53a5134d, 0xf4ab8bf0, 0x99f24231,
7089 0xae2e8e80, 0x78b5dfa5, 0xc15fa18c, 0x39fa2338, 0x47e7504f, 0x157a45c7,
7090 0xfdb0e5cf, 0x7b0f40d6, 0xa0ff3604, 0x0fecced5, 0xaf011412, 0x93c255b3,
7091 0x3c7cb056, 0xddf07f51, 0x3f55b7cf, 0xf2c15937, 0xcc0b966e, 0xc66ae767,
7092 0x5f6eccf9, 0xe5fe01dd, 0x0ba9edd9, 0xb6659ce0, 0x208ff2e5, 0x0e4723dd,
7093 0xfc4e41d8, 0xf9a3bd8c, 0xca2f23d3, 0xbc778a20, 0x43ef11b1, 0x71f9ce3f,
7094 0x80c8890e, 0x2b713f7f, 0xc21e4fcc, 0x5e27cdf5, 0xc1916f9e, 0x1c2dbd7e,
7095 0x9a3af9ba, 0xd0c5fdbb, 0xcd5a6075, 0x09791439, 0x716fe6d0, 0x5a2fa1e7,
7096 0x7de6d76d, 0xbb59e599, 0xdff81c28, 0xb82c90c1, 0x2dbae8ae, 0x9d750708,
7097 0xa3e226b4, 0xfdfc4e17, 0xbd2e1520, 0x7adfb6eb, 0xfb0bf82d, 0x2db36f93,
7098 0x71623e63, 0x465e6cb9, 0x45067d38, 0xc3915ef0, 0xf2e807b7, 0x1daf8761,
7099 0x12dca4f8, 0x21869349, 0x5f2184df, 0x4a2ffa29, 0x78f870a2, 0x8192ffa8,
7100 0x018e8f00, 0xbe67a417, 0xd5fce9ca, 0x83f7def4, 0xbe99d113, 0x66c1f986,
7101 0xb55b7a70, 0x9b8c4de3, 0x7b30f8fc, 0xf442a90f, 0xfa0f7f5c, 0x4b1244bf,
7102 0x57d355ef, 0x2de61fb9, 0x9d1f7a87, 0xc48673ad, 0xd5a33de0, 0x667af78e,
7103 0xfd3a8b64, 0xc0b6467b, 0xc63ad7e3, 0x4bd3a4de, 0xeeba7057, 0x11c40fdb,
7104 0xb059fb18, 0x55da3274, 0x24f7153b, 0x0dc1ff90, 0x4c16ce8c, 0x671089f5,
7105 0x808d613c, 0x1ff188fe, 0x87901276, 0x09e2ea0b, 0xb82f839c, 0xbc16717b,
7106 0xe1d95097, 0x3904eb69, 0xe0bc1219, 0xef164b47, 0x9d25f8c8, 0xd807c3d7,
7107 0x3bf90c3e, 0x9f0e9e60, 0x2bf1a1c7, 0x1955c977, 0xdbeba06e, 0x0b903e1d,
7108 0xbdf26ef3, 0x922d780d, 0x76b5fbc2, 0x3cdbbcc8, 0xf31f40b9, 0x4c3eac5a,
7109 0x51b2442d, 0x224f36b9, 0x15934816, 0xdf215922, 0xece7d4fe, 0x3bad86b0,
7110 0xec2c46d9, 0x80afe1fb, 0xacdf2e4e, 0xa63dd6e8, 0x51ff9f45, 0x119f3e9b,
7111 0x0eb3e7d6, 0x80b7f3e9, 0x87d1a31a, 0xe765ec0e, 0xd86765dc, 0x05e7c13d,
7112 0x7fc083d8, 0x37b9466a, 0x073daca5, 0x3ccf4dce, 0xf94134eb, 0xfd986f9e,
7113 0xc562d916, 0xbff6cbf7, 0x44b62363, 0xbad4c778, 0xd8cfca11, 0xffc0725a,
7114 0xfc63eb44, 0x4735dd03, 0xf3b1fd82, 0x0cced532, 0xcec49c61, 0x7b9c596f,
7115 0x04398b64, 0x7667b1e7, 0xd02cf53f, 0x832d99dd, 0x5e79ef51, 0xdfa09a08,
7116 0xaf0c7de0, 0x9d2e6c13, 0xacdb29fc, 0x3846ebb7, 0x73d53e99, 0xf10b994a,
7117 0xebd4974f, 0x48697dd7, 0x64ed1f9f, 0xd13e67f2, 0x73874f7c, 0x14aacf66,
7118 0x48278ba0, 0x5983fbcc, 0x9f7f264e, 0xed515a7e, 0x33bf916c, 0xd1493c46,
7119 0xa27b4f7b, 0x064b3fe7, 0xc0001c43, 0x7bf45862, 0xb55c6199, 0x7cb96fff,
7120 0xfa7ee44f, 0xc222abc8, 0xb17574e7, 0x57b89cee, 0xa6f6ad3f, 0x33ecd54c,
7121 0x93fbf585, 0xb85ea1e6, 0xd6be693f, 0x3072db2e, 0x738856e9, 0xdfe12cd9,
7122 0xfd9f2a4f, 0x121343e4, 0x02d8bbe1, 0x1f7285f3, 0x2f2d1fd8, 0xd51ea0b9,
7123 0x71b5333f, 0xe3f54523, 0xf66aa652, 0x974a1fd7, 0xbb4aefbd, 0xe5767c19,
7124 0x1d78dc16, 0x835977c5, 0x656a85e8, 0xfbff372d, 0x837b8018, 0xcb5cf78c,
7125 0xbef8c9b7, 0x0af1a079, 0x359413f4, 0xef879ebf, 0xe79fade8, 0x48e57985,
7126 0x44cc40a4, 0x904dc0d7, 0x81df6c9e, 0xfd95d5ef, 0x3c914eb5, 0x7d3d5f30,
7127 0x3f437a50, 0x7280d517, 0xf01e006e, 0x54f8c32d, 0xae11bbf5, 0x7b7d2125,
7128 0x17febe23, 0x33fa37a7, 0x63778b4a, 0x83d301bd, 0xca4877f8, 0xa3b95297,
7129 0x3fca2fb1, 0x38f8c5ac, 0x542838e3, 0xb0d0e735, 0x1f90797f, 0x271f7cad,
7130 0xc7872582, 0x79670e8f, 0xe80f377c, 0x197fd60b, 0xfb81ea99, 0x7c90378d,
7131 0xc2179f48, 0xe322890f, 0x6c3bf46b, 0x775f23b5, 0xfc9f3bb9, 0xf343d01d,
7132 0x18c73c18, 0x767befc4, 0xdef8c279, 0x0ff7faa0, 0x5f2cdcba, 0xf8c56eda,
7133 0x2b1f338a, 0x4196cf28, 0x7fd4175c, 0xd1326ad6, 0xb6cce67d, 0x4e219301,
7134 0xbd85abb0, 0x65ba7b2f, 0x7be564c0, 0xff2347f6, 0x31d6fbaa, 0x6fee95f8,
7135 0x1b7d384f, 0x15df009c, 0x79328e2c, 0x55465540, 0xeda93c0c, 0x0caa9512,
7136 0xb7221fb0, 0x991bbc3b, 0x720e93be, 0x053facff, 0xdc79f9ed, 0xae37b17f,
7137 0xd7e819e0, 0xe8faeb49, 0xe24384bf, 0x0fafa046, 0xee5def44, 0xb5f3d1e1,
7138 0xbc7ed985, 0x30564a4f, 0x4481663b, 0x4fd512c2, 0x1fbc8017, 0x8394798b,
7139 0x8c041a0b, 0x56b85a2b, 0xef781ebf, 0x0377fb54, 0x5e2fe18a, 0x9138870d,
7140 0x1b8b4c16, 0xb025e5f4, 0xfe30b87f, 0x4bcfcf03, 0x70e5f49b, 0xbdf41093,
7141 0xccefe6f2, 0x39f6e0b1, 0x7be7d751, 0x1f93a9c9, 0x8f8fca32, 0x5f5c02c4,
7142 0x909b5819, 0x702afdf2, 0x42ca6e77, 0xa59ee20a, 0x66165213, 0x04183be1,
7143 0x1645a7f6, 0xb2657412, 0x8003bc3c, 0xc9fc83ac, 0xf5825bde, 0x9487ef69,
7144 0xa1e1254d, 0x613ae8ae, 0xf272da7d, 0x5963c306, 0xe31e10bb, 0x8237de8a,
7145 0x95eb6a75, 0x3797f5f3, 0x837e759b, 0x84f3880a, 0xefd69538, 0x797ebacc,
7146 0x37dd1cfc, 0xe7e29589, 0x1bb95ee1, 0xfc5634ba, 0xa70e51f9, 0x4c2e6f87,
7147 0x15fcbe05, 0x388381e8, 0x3da97320, 0x0271c20a, 0x8e85b803, 0xcdeacb63,
7148 0x72ce7963, 0xf9d4ff96, 0x10fd5e55, 0x7ec9376a, 0x2058573c, 0xf70cbc16,
7149 0xfdba669a, 0x17fc025f, 0x12697c98, 0x246fa7f2, 0x652e47c6, 0xb3247feb,
7150 0x18aad2ea, 0xc78aa9f6, 0x782d0adf, 0xcddc17be, 0x76673df6, 0x3bfad644,
7151 0xee4c5de3, 0xc4e81dc4, 0x0ec8fe78, 0xae11ef01, 0x3de18e17, 0x78d7f5bb,
7152 0x29cfd808, 0x17206f14, 0x05640bd7, 0xdd9563bc, 0x978ef33a, 0x36d97f00,
7153 0x5a2a77d4, 0x0e158927, 0x77d33f5c, 0x708d55ec, 0x773c98ce, 0x33d02654,
7154 0x1bdcf75d, 0x83cbbbe0, 0x183aa5e3, 0x0f2ca41d, 0x0d1e2fa6, 0xf1dc17e3,
7155 0x18dbf012, 0x4d3fde1b, 0x2672b0a6, 0xf406ba60, 0xb1921497, 0xca77e41f,
7156 0xf8264f74, 0xb1761f5a, 0xc49a0671, 0xcf4133b9, 0x84f964ca, 0x46df057b,
7157 0xb875ae24, 0xc93364fe, 0x77c2f987, 0x602d13d0, 0x887963cf, 0x554a79e1,
7158 0x3c9f8c06, 0x4a89a59c, 0x5e82e318, 0xcedef151, 0xb89673e2, 0x25e3ca09,
7159 0x4e4a4d5f, 0xe95feda0, 0x952d86a2, 0x510caf53, 0x03b0e1f5, 0x623210f4,
7160 0xf5cfab14, 0x2c1925e1, 0x4d313dee, 0xbd5857d5, 0x9717d91e, 0x75f3f205,
7161 0xe67f17a6, 0x9c41c5f0, 0xec4a15da, 0x1c49dbb8, 0x3673814f, 0xfff8d212,
7162 0xc0beb303, 0x73811c7b, 0xecd2122e, 0x9b2ef007, 0xbcb37e36, 0x17be00f8,
7163 0x303a415c, 0x45a2b80e, 0x857a6f1f, 0x2ab8f62d, 0x99ce079d, 0x42ed1048,
7164 0xc0271f0a, 0xce0ab227, 0x057b8271, 0xce06aff4, 0x19a82429, 0x412e703f,
7165 0x679def9f, 0xad13f612, 0xdaf5f447, 0x247ac4be, 0xe305d3b7, 0x713bbb74,
7166 0x939c08bf, 0xafba9db0, 0x414c84f4, 0xdd6fea99, 0xc3de561e, 0xeb55a3df,
7167 0xcf75fdab, 0x977df852, 0x55dbf608, 0x8511054d, 0x9feda3cb, 0xbcb39fa0,
7168 0x45c23f7d, 0x7c2887a5, 0x81a824ec, 0x474d524f, 0xfb7944d8, 0x584d0fe7,
7169 0x4a52fa3d, 0x1f38075a, 0xf6ae2707, 0xa2e5a44d, 0xf6d7c749, 0x473e5eec,
7170 0x49b0f2f1, 0x2bc8fee4, 0xa89d4f57, 0xbdfaf3c9, 0xbe3f83ed, 0x47b3ca1a,
7171 0x1ecbf6b3, 0xcb0feaba, 0xa25ca8a5, 0x702b48eb, 0x4316f26a, 0x63f341de,
7172 0xa1b77934, 0x9e50d13c, 0x610fc862, 0xe19cbbf5, 0xc84bd134, 0x5ca687da,
7173 0x03dfc12d, 0x81cf0d4a, 0xc56bfb9b, 0xefe1abbc, 0xb364562b, 0xd95817bf,
7174 0x3859782e, 0x655f8313, 0xa76cf9ef, 0xc03460b2, 0x9065e3a1, 0x826de503,
7175 0x4770f41b, 0xe630b6cb, 0xd3479da1, 0x7bdd85ae, 0x86396f2a, 0x7fedfaed,
7176 0xf8f90994, 0x63ef51fe, 0x15c5f3bd, 0x78fae991, 0x19e2fef3, 0x26fe088f,
7177 0x3be8b8d7, 0xdedb5dbd, 0x37bdfe8c, 0x53ba472a, 0x8e51077d, 0x067fee1a,
7178 0x288e3e60, 0xbc70a89f, 0x7c59d47f, 0x31ddf0b7, 0xdb6047ed, 0x64f92fb7,
7179 0x7f91e819, 0x0e3138ad, 0xfb782af4, 0xdf8df610, 0x614ba10a, 0xf8947a1f,
7180 0x6f71852f, 0x3f78b8af, 0x547d913c, 0xde0c7cee, 0x87cffdb5, 0x7f0d5ee6,
7181 0xb3a8eeef, 0xa9fc2873, 0x52ae239e, 0x81d1c7c4, 0x4292f89d, 0xcb195c66,
7182 0x6a1ced0f, 0x5db7f9a2, 0xe2fe59eb, 0x2f20c7ce, 0xed632dc4, 0x150e74c7,
7183 0x2c3260dd, 0x726dfc47, 0x3ff7e6c7, 0xcea33972, 0xbee1eeef, 0xa42e0097,
7184 0x7037ed9c, 0xe542d0bd, 0xd3d29ce9, 0x7851375b, 0x1d85f9cc, 0xaea6dce5,
7185 0xfa65af1b, 0xe200b070, 0xbc39928d, 0xb9443f71, 0x90dea12e, 0x42607b0a,
7186 0xb4ce9f14, 0x17ee0f0e, 0x036d5597, 0xce79207d, 0x1a2fdc68, 0xb8acbe9c,
7187 0x4374d171, 0xe2b34b22, 0x8bae4cdc, 0x961fbc26, 0xf5138f7c, 0x77f15fa5,
7188 0x21df29ae, 0x5e38387d, 0xbb3173de, 0xf3173dec, 0x4e741c2b, 0x11de7ec3,
7189 0x222deb7c, 0x056824a4, 0x50d896bc, 0x91b5b90f, 0xd72a15ca, 0xebbcf8eb,
7190 0xfe8a5dd6, 0x5fc15b82, 0xfbbe1a3b, 0x47461352, 0x0cbafcf5, 0xed44779a,
7191 0xbe99bab0, 0xda7bed54, 0x5cac8d75, 0xe9755b95, 0x5fbabdac, 0x71b0d725,
7192 0xe9757f92, 0x5d875846, 0x8bf5e762, 0xb8dc8d66, 0x1bfff70c, 0x1fc0e2b2,
7193 0x82a5f3e2, 0xc961fcdd, 0x9fe81330, 0x861a7e2a, 0xd172befb, 0x73f29ff2,
7194 0xbd4f1516, 0x5b1c65f6, 0xea9102f7, 0x3fbd740f, 0xfd71fb72, 0xcb189f54,
7195 0x3e99b30e, 0x4cd74591, 0x5225f034, 0xfef838e7, 0x694e083f, 0x147feeb0,
7196 0xbc777f4e, 0xf73ef4f4, 0xbe61325e, 0xe84f4b15, 0xb870bdef, 0xcb0856ff,
7197 0xf79ad9c9, 0xb077e848, 0xfa76bf33, 0xce69c7c7, 0x53dce7e7, 0xbaa77a81,
7198 0x77cffb1e, 0x64dfc3e5, 0x51a7f234, 0x8efa3c2f, 0x3ff82d65, 0x282d2a8e,
7199 0x4b5e8f8f, 0x51c5fef0, 0xaa941efe, 0xa2fce6d7, 0xd3b015ec, 0x4889c536,
7200 0xbe09f71f, 0x7dc78054, 0xfee01e94, 0xa28f1ab6, 0xf175c7ee, 0x4085f5a1,
7201 0xc68f370f, 0x881eef73, 0x4b7a848c, 0x2eb8df99, 0xf0ed13be, 0x371ef1ba,
7202 0x07d0099d, 0x5b3231e2, 0x5d4fff41, 0xbab3a306, 0x3ef0cb92, 0x2097a505,
7203 0xe8cd9fb6, 0x41266eae, 0x766ea1bb, 0x959bd20a, 0x9f30ac84, 0xa927e8fe,
7204 0x10a3c586, 0x7b5637c9, 0x638c1d6e, 0x767b117e, 0x41378ee7, 0x456b5d8f,
7205 0x8950163d, 0xc9b51de7, 0x074a5f38, 0xaa5748c5, 0xd49bf67d, 0x0f68fdd0,
7206 0x5feed17a, 0xc3cdf4ed, 0xeed2fff9, 0x5837f981, 0x264b1ac9, 0x05643598,
7207 0x1f3e49ca, 0xc608fb52, 0x7ae5cc2f, 0x67c57be1, 0xfc7fa09d, 0xff504e3c,
7208 0xec0fa52e, 0x9584f9f0, 0x7ed7bfcf, 0xf9a9ec0c, 0x6277b2f7, 0x3e699ac9,
7209 0x9d05f9fd, 0xb9f8126b, 0xc47d4ff9, 0x87e37409, 0xffe82e76, 0xff709cbf,
7210 0xbb2f7fc6, 0xb4824acf, 0xfb68a8fd, 0xc1df81fb, 0xf9b22e5f, 0x27bb6a93,
7211 0xf7a0fbd6, 0x44bf71c7, 0xed3e23ed, 0xc638ea78, 0xf8bda97e, 0xc28bc000,
7212 0x8cf70c3d, 0x7f64bf22, 0xdf38c097, 0xa0f22544, 0xa9cf9695, 0xefe1e316,
7213 0x3a97fb88, 0x7ceabd71, 0xae4726e7, 0xa1847f44, 0xcaf6e3ff, 0xab67f01c,
7214 0x57b90ff6, 0x5c21ef63, 0x845e6894, 0xb411f87b, 0xe77cfaa3, 0xeed1b1f6,
7215 0xb35be424, 0xdc6f5eb6, 0xcc3047be, 0x4795d39f, 0x7e6f0090, 0x28af1e7e,
7216 0x5ef83991, 0x2ade6194, 0xba73773c, 0x08c2e953, 0xc0fdddef, 0x1ce9513b,
7217 0x97fafd0a, 0xc64e119a, 0xf4fdd5fe, 0x1fe52b11, 0x82f5774a, 0x7f5af480,
7218 0xc7f71db7, 0x49e46b1e, 0xefb8d7bc, 0x7777c46a, 0x4103cd89, 0xb5528f5a,
7219 0xf633cf1d, 0x9e8cf3b1, 0x81239d91, 0x9ae9ba9f, 0xdd3f147d, 0x418d8aaf,
7220 0xd5049d41, 0x37155e8f, 0xef77fd02, 0xb3f586be, 0x89dececc, 0xbdc30806,
7221 0xaadfe0c4, 0x81f39fc1, 0x002fbd89, 0x6b458f7f, 0xd1bdc377, 0xbca8cce2,
7222 0x180281e8, 0x573d4dbf, 0x38e097f2, 0x3df0dab7, 0xe0934a81, 0xb2abbd03,
7223 0x67bc32f4, 0xd1dff840, 0xa568e551, 0x99a3da89, 0x34afbe51, 0x31723fbd,
7224 0x491293f3, 0xf5a347e3, 0xb03b045e, 0x03b6b2dc, 0x49bb51ef, 0x6843eff4,
7225 0x6b95a5fc, 0xf3037ccf, 0xf8356caf, 0x83fe0c11, 0xa53d2d52, 0xf504e947,
7226 0x531f907e, 0x775bde09, 0xbf3dbcf2, 0x018efd03, 0xf030ce7e, 0xd6d77b00,
7227 0xc042dd99, 0xc9381aaf, 0xed0996f4, 0x0ec1078d, 0x18efcf8f, 0x700dcb0a,
7228 0x9ef19f3f, 0x75f6f8c9, 0xaa95d822, 0x6bb1a3be, 0x8c61bd2f, 0x4df76536,
7229 0xf1864ec1, 0xf013e13a, 0xc9f6c48d, 0xf74803ff, 0x800023ad, 0x00008000,
7230 0x00088b1f, 0x00000000, 0x7dc5ff00, 0xd554780b, 0x733ef0b5, 0x9992bcce,
7231 0x9264cce4, 0x0927de4c, 0x27010084, 0xd4500421, 0xe6a2bc21, 0xa2d101da,
7232 0x3c2438b5, 0xa0992112, 0xf7ad8b95, 0x24844032, 0x111a0804, 0xa284e028,
7233 0x17edaf62, 0x04c0622c, 0x16c45407, 0x6b5ec5fb, 0x46f7f6d5, 0x485ca008,
7234 0x6c5cb046, 0xad7bfcb5, 0x67324fbd, 0xde952892, 0x1e9f7cde, 0xecfbd9f6,
7235 0xaf6b5ac7, 0xa5b3def7, 0x90d74b32, 0x44b44849, 0xc8485488, 0xbb11a6c2,
7236 0xfe840957, 0x5b6673b9, 0x862a7909, 0x83c9e03c, 0x33c8abb2, 0x72599086,
7237 0x9e3c8c71, 0xb1722390, 0xf7878e59, 0xda1e9181, 0x08e3f88e, 0x55c84499,
7238 0xe075bbf8, 0x24203693, 0x625dbfbe, 0x8d7e4d76, 0x0e76e865, 0x83a7fd03,
7239 0xd8b6d090, 0x8f986ec0, 0xd1796024, 0x0d2df46f, 0x613a3f38, 0x7687df3a,
7240 0xfe600666, 0x40c9a415, 0x4a5909b2, 0xd2220602, 0x8fe22676, 0xda4fa029,
7241 0x173e962c, 0x2512356f, 0x55dfe097, 0x40655ffa, 0x6ccd265b, 0xe0a54b5e,
7242 0x90862111, 0xfb13a425, 0xdb57b259, 0x1234e96e, 0x2afad2b4, 0xc3460913,
7243 0x5f5b55b3, 0x0f38424d, 0xa355db5f, 0x44d27fa6, 0x36db8508, 0x3b662133,
7244 0xf99dc9cc, 0xe87f9d38, 0xb76bbd6d, 0x6869c842, 0x870fd492, 0x38e2d88e,
7245 0xa8947380, 0x568675c3, 0xd3760745, 0x48eb7675, 0xb70a3ec5, 0xc0f2364d,
7246 0x59ecfa6c, 0x0d8738a9, 0x9d8c7043, 0x3c20663d, 0x2b990e1b, 0x6e7f1402,
7247 0x55708759, 0xd5895fdf, 0x40cbb963, 0x7d695a2a, 0x5fda6ad1, 0xf57d7f5e,
7248 0x7c2f163d, 0x70165337, 0xbbe780de, 0x0d64cf00, 0x3ded077e, 0x71a8fc74,
7249 0x777ea9ec, 0xcdfb5f67, 0xfe14df0c, 0x952dff30, 0x27802d51, 0x0493b922,
7250 0x04759407, 0x63cf2ee9, 0x0fefd2f0, 0xfd7e7405, 0x5849f40d, 0x31ad7f7b,
7251 0x97b62cf0, 0xe5a0ade7, 0xb9e69f43, 0x489c281a, 0xd03e7bae, 0x5173d2c1,
7252 0xf1c1d00a, 0xff5f3f73, 0xf17f5a5b, 0xa4628353, 0x36800bf5, 0x090f1e28,
7253 0xe7684ade, 0x3c8a37bf, 0x352ddf4b, 0xbb8c3710, 0x8088c0f4, 0x807bf69f,
7254 0xb0feb196, 0x1a59c715, 0x90b6dde3, 0xa5f4b3f6, 0x40a51778, 0xf03eaaf2,
7255 0xdf5073c2, 0x4b3d7661, 0xc51a5dfb, 0xa1e971e8, 0xbe7efc14, 0xf014bbd9,
7256 0xfc0c6c93, 0x7be92fc7, 0xf5d19af2, 0x245c7d2c, 0xff3045c1, 0x0166ad8b,
7257 0x75849dda, 0xad27d2c5, 0xed5d6013, 0xbfb63c74, 0xefd21692, 0xb227d54e,
7258 0x9d387175, 0xe91a30da, 0x8d9e8b79, 0x60283fe7, 0xcf7a93fb, 0x3e5a248c,
7259 0x6bbe72f9, 0xf5eaad15, 0x4a068218, 0x4b4dbe7f, 0x84b1904e, 0x5d94eb94,
7260 0x38722700, 0xe2abe71a, 0x7171b7c3, 0x1efbd429, 0x124eec7c, 0xf4fef433,
7261 0x310919b5, 0x0f6bd3f5, 0xfd03a509, 0x6ac8af6f, 0x7b71d20d, 0x44ba47da,
7262 0xe45275ac, 0x5990fa53, 0x833d6edb, 0x8f43a86b, 0xfb5af4fb, 0xb44af587,
7263 0x5bfc1f1f, 0xf0dd2784, 0xbc017eea, 0xc1c59787, 0x747f14ca, 0x8943bebd,
7264 0x7ac8af08, 0x0bbbd5b3, 0x13f553f8, 0x0af1f3ff, 0xf9086f84, 0xc78a6919,
7265 0x1de7467d, 0xbbefd134, 0x5f7159b7, 0xb4a63c65, 0xf77e0175, 0xb69d70db,
7266 0x0ad16e69, 0x58991de5, 0x314571be, 0x86c71539, 0xaf940925, 0xa4ffa44c,
7267 0x49122efd, 0xdf00a9ad, 0xeda36ce7, 0x869cbccf, 0x24645cf8, 0xcfba2675,
7268 0xebc32349, 0xa7ca1699, 0x8dca7c28, 0xc967c85d, 0xe804087f, 0x85abb685,
7269 0x20e94b76, 0xe1030549, 0x034b7c06, 0x395840b7, 0xb5abce8b, 0xff742445,
7270 0xfaa7ca10, 0xcfd59fd6, 0x693f80c7, 0x337f27be, 0x57e8e16a, 0x63ee2df9,
7271 0x59c4a8ba, 0x51f9fa63, 0x18e7ac47, 0x12c3f3e3, 0x44677e01, 0xf29972ef,
7272 0x8fc4c5b7, 0x0492b1fc, 0x478ea9f1, 0xbbe32df9, 0xe177c626, 0xfc0d7519,
7273 0x8ad241f7, 0x380ab37c, 0xf77c60d2, 0xc777ca31, 0x0977cd0e, 0xb807c9a9,
7274 0xb8b7eefa, 0xf803ce00, 0x2aefe72f, 0x8c0d131e, 0x58f8df0f, 0xfd792440,
7275 0xeadd7870, 0xcfa0e73e, 0x06e242e8, 0xc0fbe7fe, 0x806e5264, 0x516487b2,
7276 0x4eb0ecf8, 0xad027ef9, 0x0dc449f7, 0x93ba337c, 0xfbe85bb8, 0x87e2669d,
7277 0x2826a6fe, 0xc0d38fd8, 0x792f42e8, 0x2fad3e48, 0xea0cee2a, 0x13c49f60,
7278 0xb5bdf819, 0xd3bff593, 0x802bbf4a, 0xaefc04ef, 0xa9137bef, 0xbefb0a8d,
7279 0xe91990f8, 0x6b41f2e8, 0xd0f288c0, 0xfda3619b, 0x48d1fc25, 0x873dbd60,
7280 0x7be7c8ac, 0x2b6e64f4, 0x4910ef6d, 0x73e22b4d, 0xd827f62d, 0x27e9f132,
7281 0x680429c5, 0x053db857, 0xab2132b6, 0x65575f91, 0xf283de76, 0x81519f76,
7282 0xd6d97c7d, 0x74ca1cb5, 0xe5a7e23c, 0xdb05652f, 0xcd4ff6f9, 0xef7d09ff,
7283 0x0c5c58f3, 0xa07cdeba, 0xa3f8a317, 0x6f144c7b, 0x42c7c433, 0x5679d28f,
7284 0xe06459a5, 0xfe32d3c7, 0xb4bdfef4, 0x3d7ed9fc, 0x9fde0231, 0x64973a9d,
7285 0x2a27cd0d, 0x5d93fa03, 0x64baf461, 0xd55cb6af, 0xdafb2daa, 0x9b54e5b4,
7286 0x1a2671d5, 0x2aeba6f7, 0xb1a327a5, 0x3a16d3e6, 0x46abe35f, 0x967f9be4,
7287 0xe03699bd, 0x31d0ba0b, 0xe331a380, 0xe02f58fc, 0x0173fdb9, 0x1b4a469e,
7288 0xbe0c799d, 0x9b2eafb0, 0x79c867e7, 0xfe97cf43, 0x47087499, 0x93c189b7,
7289 0x9b1f07f1, 0xee57dd12, 0xf5d08ecf, 0x251d9a2f, 0xee37c6af, 0xa045f1d2,
7290 0x891ce0af, 0x9f6deb6f, 0x5db16309, 0x5989f225, 0x579d1db4, 0xb7c656c5,
7291 0x18ce9297, 0x54d50fd8, 0x145131af, 0x78636c3e, 0x2a1b5258, 0x367fd20a,
7292 0xc2464bdb, 0x25afa53c, 0x1d7fe00f, 0x87a61bf4, 0xb1d366dd, 0x72cd7bf6,
7293 0x368e06b7, 0x96d7d94d, 0xed877724, 0xff7c2597, 0x60904513, 0x7af94b3d,
7294 0x6f782f7e, 0x9955f803, 0xe8530cba, 0xfd7eb7f8, 0xc5efca05, 0x75c6ca2b,
7295 0xdbd70b8f, 0x1757c88c, 0xf7c5ea3f, 0x399b6faf, 0xcdb7d71f, 0xcfdc00ac,
7296 0x9e9014ec, 0x025aa717, 0x5bcffa26, 0x5b9f4c6d, 0x8413bf4c, 0x848c7081,
7297 0x331dd9db, 0x6747409d, 0xdfcf1b09, 0x59e4e4ca, 0x9b2bc299, 0xcefe81b5,
7298 0xebbe31b6, 0x33f33adb, 0x778b4fe0, 0x67902e8a, 0x1aeac3a4, 0x7d3ca04e,
7299 0xf40b42e4, 0x0a6e2977, 0x6bbcdf6d, 0x7be22cba, 0xfd8013d1, 0x6f3bb923,
7300 0x5da5efa5, 0x78df5013, 0xcd91a763, 0x0e7a66d3, 0xd7eb71d6, 0x92c7ea22,
7301 0x2f41788e, 0x47b8366b, 0x76557ec2, 0xf0033b3c, 0xb2567672, 0x42ffdb0e,
7302 0xc3c03220, 0xde0122b6, 0x0f24162f, 0xad8acfec, 0x72e1a595, 0x11136cd9,
7303 0x1e32535f, 0xe0b2e84b, 0xe407ba7e, 0xba4ed554, 0xd9fc607f, 0xaf7fbd1f,
7304 0x3d3f7c23, 0x6174445c, 0xbfc77672, 0x5fc13d20, 0x34f808b0, 0xeef5c583,
7305 0xbab4632b, 0x80726a2f, 0x5d5e2e5f, 0xa20f2393, 0x8bedf7bf, 0x8e1f741d,
7306 0x4d836426, 0xb0755720, 0xfd1aed31, 0xdfbd2876, 0x0373ab92, 0xe22e4ddc,
7307 0x133e967e, 0xa0bf548d, 0xa025f07c, 0x1a78788f, 0x97d23e10, 0x877ded0f,
7308 0xcd926bae, 0xc7a053fb, 0x07cee20c, 0xb9212bbc, 0x005baa98, 0xc80fd462,
7309 0xb7d3230e, 0x6defa624, 0x81cf2789, 0xfb8ea0be, 0x1e2fe84b, 0x1b1ec2f9,
7310 0xc3e7b7ed, 0x5c018eaf, 0x8fcfd3ab, 0xbbecf905, 0xa14185f2, 0x0bb4b5eb,
7311 0x2e2dafc8, 0xf17a010f, 0x0b22cfb5, 0xacf9faf2, 0x40e4c5cf, 0x6afebae4,
7312 0xcfb67a63, 0x4e7ec211, 0x6dfed9db, 0xdcfa31b6, 0x002a22be, 0x23bb75fc,
7313 0xff498660, 0x7c94fbbd, 0xc538a545, 0xe189a573, 0x57e7b4d9, 0x3be8116e,
7314 0xa1c3c820, 0xd1fdb0ac, 0x202f315b, 0xdb3e71d2, 0xf2c7ed93, 0x912e29fe,
7315 0xfcf659d6, 0xe00b2eac, 0x4177a6d4, 0x2bab8b7b, 0xd9f7d606, 0xb031539e,
7316 0x223d8abe, 0xf022bbae, 0xbcc2c279, 0xbaf0be7e, 0xc00dfde0, 0x4b04388b,
7317 0x6cf87f38, 0x0584a5cf, 0x98395416, 0x1c1c2c7c, 0x29e4472e, 0x5bb7809d,
7318 0x3978616f, 0x00630bf7, 0x3339def8, 0xfc615f95, 0xc9959cf6, 0x263693b3,
7319 0x4d69091f, 0x57d37907, 0x07573fbe, 0x6648ffe3, 0x5a1877eb, 0xfe3f61d3,
7320 0xe7eda0b7, 0x091d3ac1, 0x595ede50, 0xf9434147, 0x5e17b9d1, 0xff7e0749,
7321 0xa4afb3d9, 0x2fcd8597, 0x79f53bf2, 0x9aedc6de, 0x26dda7a6, 0x51195e3a,
7322 0xc2a60bc7, 0xe32e6578, 0x485fc027, 0xdf7774dd, 0xcf62c9be, 0xab64f6f0,
7323 0xaf60f91b, 0x1d00a8cb, 0x56f5dfaa, 0x804db944, 0xfe426217, 0x062ed657,
7324 0xdb9fd08d, 0xfa01cc3d, 0x447dfab6, 0x4638aeff, 0x809b424f, 0x5e746976,
7325 0x77f1f908, 0x2d4ef7e6, 0x7f9e293e, 0x32ae7801, 0x10a58e85, 0xc0030fa4,
7326 0x916d50cd, 0xac253e40, 0x7a15f461, 0xbffa8744, 0x0169d921, 0x4e6b767e,
7327 0x6e8ead54, 0xcc544744, 0xa7f54258, 0x6c5ce4b4, 0x74662fef, 0x81204fef,
7328 0x590c0235, 0x96bf2023, 0x3a9c5e99, 0xb40dc891, 0xd33b3df8, 0xb5c49c57,
7329 0xbc46cc55, 0x507fe00b, 0x05caa1e1, 0x8fe01fa0, 0xd21304e7, 0xa02ed08f,
7330 0x5aea289e, 0x43bf41e7, 0x5d9e53d1, 0x3d1953b5, 0x49ff95f5, 0xe76454f4,
7331 0x9e803bf4, 0x93d20abc, 0x3d3834d3, 0xbbf90229, 0x07bf13da, 0x0e44acec,
7332 0xef9c4daf, 0x31311e84, 0x19050abf, 0xf794b7ac, 0x04b26a57, 0x2e1f9045,
7333 0x30aef9fd, 0xd507627b, 0x494ec16f, 0x3e9e7d02, 0x57ccd653, 0xb3a46f10,
7334 0xe8daec0b, 0x8f942609, 0x999d75eb, 0x8e24afa0, 0x7407d9aa, 0xaf2f3891,
7335 0x67da0d60, 0x079036a9, 0xbfd15b20, 0xd3d8a2b0, 0x2fa6171d, 0x2fa80874,
7336 0xc6ea3f54, 0x99db53f7, 0x661be07e, 0xd7d77d40, 0xcf01f826, 0x00431ed5,
7337 0x817aa0f4, 0x1bfc01f9, 0xefd80acc, 0x156536cd, 0xbff34fd0, 0x5d3f2e29,
7338 0xf9806f47, 0xd7497a13, 0xbd009fae, 0x3ed05855, 0xb605b66f, 0x7776822d,
7339 0x03bb61e7, 0xf8d9137f, 0xdf8e09c3, 0x7a8adf9c, 0x0a6df37a, 0xfc7003f3,
7340 0x2772cf35, 0xa81f40d9, 0xe6e7eed3, 0x9d927716, 0x52b5efbe, 0xcaf1d0c0,
7341 0x8788cd1a, 0x99c19164, 0xfc989ac4, 0x4c17c819, 0x8984f700, 0x4f4d311c,
7342 0xb7d3bea3, 0x80a729cf, 0x6faf3272, 0xd0e3a4ce, 0x3cf35879, 0x9f79a099,
7343 0x3c7e5a6a, 0x024fd28a, 0xc46e87f8, 0xebd07e26, 0x564c61a3, 0x4f70c376,
7344 0x9244e8e9, 0x86cef6a1, 0xcac39369, 0xf7ff7dbc, 0x69f6efff, 0xfb7728a9,
7345 0x54da61ea, 0xb765ab1e, 0x9d6bce99, 0xa25ebfb5, 0x4da9aefa, 0xd7fbdf60,
7346 0x8a9d3edf, 0x1d415ee8, 0x377aceff, 0x44cca9f8, 0xfcf85e33, 0xf5fe88a4,
7347 0xa28b7fb4, 0x02565fb6, 0xa0553dfd, 0x73aedf96, 0xd26df9d3, 0x9043fb6b,
7348 0xa0a1eff2, 0x4f8be78e, 0xdc9c686a, 0x3d5017af, 0xdf1f6021, 0xfbac1faf,
7349 0x06e9b4a8, 0x7cb4563a, 0x577200c9, 0x873ef395, 0xe447fa80, 0xef897d7e,
7350 0x57ccefd7, 0xba3d5187, 0xbf47a348, 0xdabe4764, 0x24b60335, 0x6f903fb5,
7351 0x10f31efb, 0x3ea8e7d0, 0xfa8ec072, 0x4733f9c8, 0xeccf7d68, 0x514b1cbf,
7352 0x79b2dda0, 0xaefaf7a0, 0xbeb74848, 0xa04062bd, 0xfbe26b74, 0xc0f1ca85,
7353 0x9e9fa170, 0x9d39941e, 0x0744fcda, 0x8c21df74, 0xd57d23f7, 0x714ddfa4,
7354 0x3ee71299, 0xb7ef8f62, 0xfdd7231b, 0x0fd99d91, 0x6de2dcbe, 0x1effd039,
7355 0xd09e8081, 0x61327b90, 0x9f4dda01, 0xfb0c2c24, 0x29edb2ae, 0x5ee56784,
7356 0xfc70a0fd, 0x1c222ec8, 0xecbe0fab, 0x2e71be06, 0xa84f2020, 0x37f50290,
7357 0x854572d2, 0x5241340e, 0x2f7f9818, 0x35cc8fac, 0x7d74e190, 0x409bd041,
7358 0x977bda8f, 0x375846ff, 0xafa04ffd, 0xa1167bb6, 0xd73edd3c, 0x30992164,
7359 0x0865b2cf, 0x0dca3907, 0x2dc86870, 0xaa71824e, 0x4590cd67, 0x1c7aa7a8,
7360 0x7a3f57d4, 0xd30c405f, 0xf4da1b03, 0x14e7a025, 0x57ee7d51, 0xf669de74,
7361 0x745c4bdb, 0xfb88a71f, 0xe5a61ff2, 0xf1f0432d, 0x6e4c1c47, 0xff1e0ad4,
7362 0x5fd10af7, 0x6ffdc247, 0x6f4c6d19, 0x683768bc, 0xed17affc, 0xd9377e12,
7363 0xc81539df, 0x15d4b0e7, 0x8fb4fa0d, 0xfb073fb8, 0xca2c7899, 0xc62788b3,
7364 0x152b1c8f, 0x1c992bf4, 0x806feb5d, 0xda12c9fa, 0x7aea442f, 0xa9edc612,
7365 0x081ab877, 0x7e5007df, 0x9eed0f34, 0xabde71f9, 0x5c454740, 0x3839ed4f,
7366 0xaf2cbf33, 0x7faaef5f, 0x0d581ad6, 0x3caad4fc, 0xf4fc0251, 0x24f9094b,
7367 0xa73a8531, 0xff2a7ed2, 0x1b7ec76a, 0x7151bda2, 0xe6f5fe74, 0x81d03d40,
7368 0x76c445bf, 0x20a6d98e, 0x73d9f3f4, 0x2fd016d6, 0x02268ef5, 0x15cd4c74,
7369 0x1c9887f4, 0xf2d0a21e, 0x497cff54, 0xa1117900, 0xbf054ccf, 0x0e2bda11,
7370 0xf3162bf4, 0x529c31fd, 0x6e1319c1, 0x71abda85, 0xf1cdfafd, 0xf048e6af,
7371 0x747bd552, 0x9de7e626, 0xc08a3736, 0xe86d64f8, 0xcafc0e98, 0x7a024e8e,
7372 0x80ab5570, 0xbee554e3, 0x65bb0064, 0xdfdb2b49, 0x50676e3e, 0x5e83a5f8,
7373 0xcd171d91, 0x465acbf5, 0x58f3a4ef, 0x45f9c00a, 0x68424f86, 0xbdb86b3b,
7374 0xd5d98ab2, 0xf7033fbc, 0xbf715787, 0x58849511, 0xd54e363f, 0x67f35633,
7375 0x71f27b13, 0x6e9d08b7, 0x2f99e011, 0xeab6fc68, 0xe31c7a73, 0x4347b13b,
7376 0x86ff6033, 0xff817d28, 0x6b309b68, 0x7d749bd9, 0x728fc6db, 0xa4e60a81,
7377 0xc01624e4, 0x148a4a7b, 0x9f6d85ee, 0x21ba00cf, 0x6bf70425, 0xb114db75,
7378 0x400dc78a, 0xae8c485f, 0xc4fa8169, 0x3e517207, 0xfc1f1f83, 0xb87077ff,
7379 0xff985926, 0x9fdab9ce, 0x8c1e50f9, 0x26f659ef, 0x0a263f8c, 0x148915e3,
7380 0x3e3b5637, 0xe57fc0eb, 0x4047f924, 0x954b3afe, 0x1a8f9802, 0x89d78a37,
7381 0x43cacc0f, 0xbb658e3e, 0xa6ef704b, 0x6ce3bbcf, 0xdf6a2eb8, 0xe17cc095,
7382 0x0ddb807d, 0x4e274760, 0x7187c9ad, 0xcf044e21, 0x84a0a49e, 0xcf2a68fe,
7383 0x6d3a059f, 0xaf00ca33, 0x3eb7b6d2, 0x6a5b7900, 0xe822ad22, 0x4b7a113f,
7384 0xf35dcc56, 0x2f7b6e80, 0x38f5d99c, 0x03eeebcc, 0x47e22f2e, 0x7adc8fab,
7385 0xcfcbd30b, 0x80ad1b3d, 0xf39bb91e, 0xb23faa6d, 0x982fc138, 0x47a9191d,
7386 0xb5a7123e, 0xffcafa4b, 0xcd923d70, 0xf7e74fcf, 0xf77f186c, 0xb7afbb71,
7387 0xc80c62e2, 0xf47d55af, 0x517fe546, 0xb6529ebf, 0xd813fa27, 0x45767d67,
7388 0xb5223e84, 0x840538b0, 0xdaef90d9, 0xe2fe3c0c, 0xff07ce76, 0xf9072d87,
7389 0xa2e7f1cf, 0x173740fd, 0x97a8cd5b, 0x10433649, 0xb2fb55e6, 0x8013a031,
7390 0x7578720f, 0x818ab8f0, 0x39ec6bc7, 0x0714280a, 0xfbe41e0c, 0x2cf497fe,
7391 0x781312ae, 0x5e5a39e1, 0xc789387a, 0xeff6085d, 0xf08d183f, 0xc4a51a5e,
7392 0x7f4bff42, 0x9e20471d, 0x03c74bd2, 0x7b37cf3c, 0x4d780a7f, 0xc9feb236,
7393 0xc585466b, 0x36398279, 0x0096870a, 0xe54effd3, 0xba0682ea, 0x17d016ee,
7394 0x3546dfa0, 0xd9d6c2fe, 0xc58521bb, 0x0119400f, 0xfb9eacbb, 0xcab8d5e9,
7395 0x2b87e661, 0x5393f1e7, 0x033d17b3, 0xa15ab4a1, 0xb4ec04a6, 0xd0530dcb,
7396 0x89fcbd6f, 0xaf2cf859, 0x17dbfad3, 0xaf7c1a91, 0x3f5527c6, 0x19711977,
7397 0xefdcfe98, 0x7d51d43f, 0x8a93a946, 0x12667e41, 0x03c83579, 0x37b14fc5,
7398 0xe96b3e81, 0x81789413, 0x93b69942, 0x80511dea, 0x3ab575ef, 0x5afe5b94,
7399 0xa9da1b9d, 0x1c56f2f4, 0x57fd23f3, 0x5097f31c, 0x1c600750, 0xe7ab59f5,
7400 0xdfde7efe, 0xc20ba22a, 0xe7b02753, 0x192a593a, 0xfdab7e4c, 0x4c6bead5,
7401 0x4e6f4053, 0xfb3fa1d3, 0x173dc1b2, 0x1cf6c5fd, 0xb5ad53c4, 0xd584aea6,
7402 0x6cba5ee3, 0xfeb0790e, 0x96298966, 0x3f03b144, 0xfa6388ed, 0x16dc2445,
7403 0x91cb6936, 0x80ca9071, 0xbc4e5cb6, 0x59b29223, 0x7dfc20dc, 0x9767e707,
7404 0xbc39321b, 0xbbe0065d, 0xa557faea, 0xd2e9b832, 0xad2b33d8, 0x41d02e78,
7405 0x3285f816, 0xaafcc9e1, 0xff382574, 0x021d9bac, 0x7cc447d2, 0x9e8c6d6b,
7406 0x0fccf5fc, 0x3fcef7f9, 0xe367de72, 0x763ef812, 0x56be213b, 0x5e301b2e,
7407 0x12fead7a, 0xdf6b4393, 0xf1ff95f6, 0xe7b32df6, 0x2fc645eb, 0xa97c8c88,
7408 0x396b664c, 0x0b9eb825, 0xd50b7bc2, 0xf51d601b, 0x91f00162, 0x705977a9,
7409 0x2987d51d, 0x55f5a11f, 0x83a5758f, 0xee2eaf5c, 0x80bc81ca, 0x6cc2f848,
7410 0xd19f9525, 0x6a0e6576, 0x50de808f, 0x0d878da7, 0xd3ba038c, 0xeec1e31c,
7411 0x2defb539, 0xccfb5f90, 0xbfe8bf28, 0xff61188e, 0xbe44cc1f, 0x3bc589f6,
7412 0xbe3ee21c, 0xe7aee0a8, 0x618f4133, 0xbb55547a, 0xc4f405b1, 0xf8b0dab2,
7413 0x51affc1a, 0x75236f1b, 0x93bbf476, 0x8afbed66, 0x0ddf111d, 0x2135bf88,
7414 0xbc18b65e, 0x53bf6123, 0xf1f18439, 0x023a950b, 0x5d172df8, 0x5d48408b,
7415 0xf3f56b30, 0xaf86560b, 0xfe550e69, 0xcf0072b8, 0x7801e57d, 0x9e00e576,
7416 0x1bc475cb, 0xe0154fde, 0x2977e299, 0x9785f3c7, 0x9e00e427, 0x909befcf,
7417 0xa2de7803, 0xbec3726f, 0x4b7b2599, 0xd3dd8e00, 0x415fa83d, 0xd1f613bc,
7418 0x7de3d2b5, 0xf464f37d, 0xf390df78, 0x5bf8c7fc, 0x8b8f9286, 0x95a1e6fa,
7419 0x92830e8f, 0xcca0fc0a, 0x3946fc64, 0xfa837f09, 0xf4464cf3, 0xeafe1c7f,
7420 0x1bcc46d2, 0x3f511768, 0x2c3bfb51, 0x3f41b379, 0xd381fc3a, 0xee8617e5,
7421 0x8afc0adf, 0xe0fcffc5, 0x02ed5167, 0xe48cbf55, 0xfbe63fc7, 0xfdc3b37a,
7422 0xd83bfd99, 0xb8ffaaa7, 0x0531b782, 0x77bd312e, 0xfe62e08f, 0x27f456e3,
7423 0x97cc7757, 0x69fc5fc1, 0xab8ff980, 0xff47ce5f, 0xf5e06571, 0xdfc80a60,
7424 0x7b064176, 0x27cf72a4, 0xfd2c8b31, 0x73b52f76, 0x886e809b, 0xfa471b49,
7425 0xa62a7034, 0x3ef382dc, 0x768ef30d, 0xf7400c84, 0x23fed4d5, 0x52d54974,
7426 0x5bf418e8, 0x17a820ed, 0xed69b614, 0xb8054a41, 0x031eedee, 0xededddf2,
7427 0x75f80042, 0x999bc182, 0xa48d720a, 0xe40718ca, 0xc3976cfb, 0xe8f301dd,
7428 0x03bb6b8f, 0xa33cb08e, 0x48b16dae, 0xe27a5dbf, 0x6d9f8196, 0x267e72b3,
7429 0xf3fb7f21, 0x21a05b0e, 0x73f86f4c, 0x9509e980, 0x4491be6a, 0xd7c51282,
7430 0x0fee39a2, 0xefc0df01, 0x3efc1183, 0xa3c6acbc, 0x3cfc4097, 0xde1dee22,
7431 0x1f8e2fae, 0xf4d6f716, 0x95f26a43, 0x5bdc6d42, 0x7667ef5b, 0x2b0fdd33,
7432 0x57e9fa0a, 0xbf4a83c5, 0xed1fdcd5, 0x16b938ab, 0x26d7d7e8, 0x2f5f60c8,
7433 0x5dfa3175, 0xe32fed4a, 0x9dfb81d8, 0x0dfa52b4, 0xed4377e3, 0xe4228fff,
7434 0x7bff47d1, 0x3b5068f2, 0xf8df74fd, 0xebabdf6c, 0x7df7fd57, 0xd8176ceb,
7435 0x57588cbe, 0xe91adda4, 0xceed5777, 0x5f87e56b, 0xafc3f045, 0xa1f88ffe,
7436 0x7e287e29, 0xfc6b8da8, 0x7ff0fcdd, 0x4cf1be39, 0x3a31d3c7, 0x332a2aca,
7437 0xd7a64efd, 0xe2f135b9, 0xcdc5a219, 0xcb22a6e2, 0xbb8c8897, 0xdc78332b,
7438 0xd7e7ed9d, 0x5f11165f, 0x5c3e3c55, 0x417561d5, 0x62cb0ad3, 0xc646cf8c,
7439 0xfb241f4f, 0x228a0066, 0x614ba8e3, 0x7b7f671f, 0x9e3f353c, 0x5ce947c5,
7440 0xa14f2132, 0xdfcb58a8, 0x8a5cb75f, 0xbbe186f3, 0x021a8f38, 0x49b5d083,
7441 0xd87b13f2, 0x99e35bfb, 0xcf3afd3e, 0x481a71e7, 0x6ca1e41d, 0xc1bb46b2,
7442 0x58ea718e, 0x9c4a51be, 0x78fc4a67, 0x9e1cefe0, 0x744fbf07, 0xe8cf2e14,
7443 0xf89f915b, 0xe02e2cab, 0x471faa7f, 0xf7077fed, 0x9d2b5e83, 0xddaf1bdf,
7444 0x7fe57df7, 0x572fbed2, 0xe37bfbc7, 0x6c295b76, 0x2081fb34, 0x38809efd,
7445 0xba40e653, 0xa19faa1d, 0xbc7977e8, 0xee3c5967, 0xcc58f73b, 0xfe46bd9f,
7446 0x3a185d12, 0xb222fe05, 0x7f80a8df, 0x2825fc13, 0xb8931b17, 0x022aeebd,
7447 0x2ebe4338, 0x0c7d6be4, 0xb4349cff, 0xb7d8d8fe, 0xd8fe99ff, 0xe907fe57,
7448 0x9ec8378f, 0xeeceb08d, 0x901cee29, 0x74aceb6f, 0xbe1760fe, 0x768cf2c0,
7449 0xee7d1998, 0x925d1810, 0xe4d77115, 0xaf13d977, 0x867b9fe5, 0x2efff79c,
7450 0xa7fd6cff, 0xc4bfcff1, 0xe8751f80, 0x2f2cfc7e, 0xcdd3b8b7, 0x776469e3,
7451 0x07db7f98, 0xfbf466f9, 0xeabe7c23, 0x2e5c9dfb, 0x47dc125a, 0xff9c1f81,
7452 0xb12264d0, 0x6429e554, 0x63dab17c, 0x7542f8c1, 0xa97bcb2b, 0xff208c7e,
7453 0x69ff06ae, 0x6715f81e, 0x26f7d011, 0x0027bcd9, 0xb23eebcf, 0xf058c5f8,
7454 0xa026cfbb, 0xc87cf5df, 0xbd967fca, 0x7bef509d, 0x19e30bac, 0x61cfb3cd,
7455 0xd5d155de, 0x0a4b6b4b, 0x47e8be71, 0x4d491870, 0x1afe9e38, 0xd596f2cf,
7456 0x783e95e7, 0x7fafd1bb, 0x11e582be, 0x196e1cfb, 0x5faa11fc, 0x44e95a3c,
7457 0x7ef5533f, 0x8915b4a6, 0x27e43d6c, 0xd54f48a9, 0x83e4a7fb, 0x9ab494ff,
7458 0x2dcf41f3, 0xed05a3fa, 0x268ff3bd, 0xfcc49e63, 0x9859ef38, 0x7030b5af,
7459 0x19a5e81b, 0x77d01c74, 0x2dbbefcf, 0xf2ade61f, 0x3fe02dbf, 0x58b7eda7,
7460 0x62717eb5, 0x95ddf962, 0xfea8a7cf, 0xb7f410f3, 0x6243ef85, 0x359a2a69,
7461 0xf757bec8, 0xc3a8a27b, 0x607f13fe, 0xcab938c2, 0x89e8b60f, 0xcfdd94d7,
7462 0xcf10fe47, 0x3c1cfbde, 0x167db15f, 0x65e14fcb, 0xf0aa7f0b, 0xfe98ecdc,
7463 0x1fc79807, 0xcbeba5e2, 0x4b05930b, 0x75eb3c78, 0x7887fbc1, 0x8032cf16,
7464 0x8a314e7d, 0x2be8967e, 0x92ce7f4c, 0x5647480d, 0x3e30dfba, 0xf408e943,
7465 0xcea1c9f8, 0x9d74b1a9, 0x93839ac3, 0xaf87be01, 0xd24f10e8, 0x9f1813ac,
7466 0x78d81589, 0xf55d8dd9, 0x22ffc023, 0xa03377bf, 0x8b926952, 0xc937d421,
7467 0x404e49e6, 0x2e4d7a7f, 0x7bfc578c, 0xec93cb3d, 0x42bf4688, 0xcc52fa73,
7468 0xc8f9ec93, 0x489cfe88, 0xfd3ea0f9, 0x45e63564, 0x27fdb566, 0xfbac09c6,
7469 0xd4dc0d05, 0x0b04f8e7, 0x3bf95f8b, 0xcd6e6067, 0x57f20764, 0x188fe3a9,
7470 0x25ea969f, 0x56a43ce0, 0x8199d6ef, 0xe822ad7f, 0x2cde1ce7, 0x195f00eb,
7471 0xf7a62f3c, 0x7ac75ff0, 0xe3514ed1, 0xd7960102, 0x0b5aefa4, 0xaab497f6,
7472 0xe03f16eb, 0x574dbf63, 0x85fd079d, 0xd2cfd1aa, 0xcf804d11, 0xaf65b467,
7473 0x339689be, 0x838c64ea, 0x925a1ef5, 0xba557e81, 0xac83e1ce, 0xe5813d33,
7474 0x18133921, 0xd11d48bd, 0xd267903a, 0xd182e266, 0x32dd6b33, 0xcb8779f8,
7475 0x25b9d212, 0x70025bc1, 0x807ce68d, 0xb8c288ac, 0x7e6255a2, 0x8f8aeb11,
7476 0x44e7017e, 0x03f3f176, 0x9e8f0f47, 0x7abdfe8d, 0x5fb80049, 0xc9bcb1b6,
7477 0x73da0939, 0x3ef0fd07, 0x59a7f98a, 0xe4c9ff1d, 0xfa0b1d17, 0x3e8cf497,
7478 0x0b477aa4, 0x587711f8, 0x7b6f98bd, 0xc4506d73, 0xfddc9938, 0x66128964,
7479 0xf2656ccf, 0xb32f7aa4, 0x97ed23bf, 0x5523936f, 0xd2395a09, 0xe927fe57,
7480 0xae122b27, 0x5a212ed3, 0x4f522e7b, 0x06dfb489, 0xfd11dbe8, 0xa8afa50d,
7481 0xfdc52779, 0xd9bd30e3, 0x7e43eaaa, 0xb14e5e4d, 0x4c4b8d85, 0xdb27feda,
7482 0xcc8f9665, 0xd61274f3, 0x9024ab28, 0xd046ff57, 0x0be6a72f, 0x5e598bf9,
7483 0xf9475f8f, 0x97c4265f, 0x284f309a, 0x01050485, 0x045d66fd, 0x7c844bbe,
7484 0xe3ddfa21, 0xef385909, 0x2755c49d, 0x04547f22, 0xf219b798, 0x352f304c,
7485 0x8c116db0, 0xc705b773, 0xc99e4331, 0x70154838, 0x3a7e036f, 0x11c582b5,
7486 0x05dca992, 0xc61e4dfa, 0x973cd0e8, 0xf9a89be5, 0x87fe6a24, 0x0e62870a,
7487 0x8b11e4df, 0xd5ef8132, 0x4017de0b, 0x1817a9cf, 0x981bfc7c, 0x46d9a11f,
7488 0x6e5a68f5, 0xf9851cae, 0xf584bd7e, 0x21d0afef, 0x80f9aa5d, 0x7615c3cd,
7489 0x226fe53e, 0xf9cdefea, 0x4064bf2c, 0x5c044a1e, 0x6e943cd5, 0xf603b7ab,
7490 0xe4c8b26d, 0xa2379aa8, 0xfe1849d2, 0xde3a66fc, 0xbfa60ef6, 0x70185717,
7491 0xb795bd1d, 0xb7b1ffa3, 0xce404752, 0x191bb717, 0xb78c45dd, 0x0481ae7d,
7492 0x60295fa1, 0x8e79fcc6, 0x5fd36fff, 0xc1735e29, 0x65747bbf, 0x0a6eb8c9,
7493 0x7a5637e3, 0x166bd9f0, 0xd7c8455a, 0x01e68731, 0xf89cda47, 0x49a43ba3,
7494 0x4a135790, 0xecc92817, 0x54a0fe70, 0x37a072a2, 0x9431f43e, 0x9c7c4c5f,
7495 0x76878795, 0xd1fdb409, 0xd8a51da7, 0x9931681e, 0x98253f90, 0xeb96fd4b,
7496 0x40646f90, 0xc0a7c6be, 0xd748aa87, 0x0bf44eda, 0xc856f971, 0x669921f8,
7497 0x94bf300c, 0x77b1fe82, 0xee513293, 0xf6b3725b, 0xaa7d4277, 0xb469fd11,
7498 0xddfde91e, 0xbd5853e1, 0x524ef0c2, 0x836f2cad, 0x9f81f974, 0x05399bbd,
7499 0xb055d2fd, 0xf4fea81f, 0x057bc5a6, 0xe8417af0, 0xe0fb0e5c, 0x9affe9dd,
7500 0xe17df407, 0x01864fc0, 0xa06999bf, 0xfc20f97a, 0xe32771e5, 0x4b7abd2f,
7501 0x79fb409d, 0x1215e2dc, 0xe883f969, 0x95203379, 0x14dc6e7c, 0x200d1c03,
7502 0xe04417fe, 0x7f1cf177, 0x5f4c39b6, 0x08f34db4, 0xc6b9f790, 0xef11e6cc,
7503 0xbfa8dc95, 0x7708e778, 0x11aff5d3, 0x94433eb8, 0x143bb458, 0x8eec1625,
7504 0xc21e2ba5, 0xef916fbc, 0x9bad49e7, 0x7f97d045, 0x4df8f2b7, 0xe5a1b0d2,
7505 0xf6115df0, 0x1254fa85, 0x8b663ad9, 0x8fa018ca, 0x6fe342b5, 0x3de0934a,
7506 0x31e9b3a3, 0x5f210a2b, 0x4d74667a, 0x22cdc621, 0xf7d2c7df, 0x23656179,
7507 0x14d4b76b, 0x3d28974a, 0x61decd3b, 0xf3cb9700, 0xfb0e593f, 0xbbf27977,
7508 0xc2be431f, 0xd6e27abb, 0xe24d3ec3, 0x1f2a4371, 0x32c7bf01, 0x286e2c6c,
7509 0x031a9d6f, 0xef866ce5, 0xe30048db, 0xd873a5d4, 0x483bc139, 0x6d176d67,
7510 0x57a9d337, 0xece8c2ba, 0xbe5b4536, 0x2e5b5723, 0xff1179e5, 0xbfbed2e2,
7511 0xc0248493, 0x7e26f7ff, 0xfdfc223d, 0x1beecd8f, 0x0aaffe61, 0x3fd28f2c,
7512 0x87a8c889, 0xe83f043a, 0x495fa305, 0x5926e7e6, 0xb9cfdfbe, 0x44caf31d,
7513 0x7b09f582, 0x0f21bb4d, 0x8b07f55f, 0x93b47ebc, 0xc8ec3298, 0x84ae508f,
7514 0xe8379e04, 0x390918c0, 0x7e664cb0, 0x40d6da51, 0x5f3039fb, 0x5824b841,
7515 0xa016e474, 0xd21342eb, 0x298a5175, 0x28e0e80a, 0x3f1f23a7, 0x55d2a387,
7516 0x903c4491, 0x9e8740bf, 0xf577cf03, 0xfff011f2, 0x78233ffa, 0x29908a4e,
7517 0xf231e612, 0x855908b1, 0xbd39a7e5, 0xedf9551e, 0x6fc849bf, 0x701ab4df,
7518 0x16bf895f, 0x439f805b, 0x5fd6991b, 0xf3851c6c, 0xdd03f753, 0x091cc3bd,
7519 0xfde672e8, 0x44983a4a, 0x2acaccae, 0x38f862bd, 0x410fe401, 0x738d523d,
7520 0xbefa99a5, 0x4977c373, 0x74bb9fbc, 0x8a4cde2c, 0xdc9d1c78, 0x3f7cc465,
7521 0xbfb42f5e, 0xf7e025f5, 0xdc4cc4f1, 0xb7887b74, 0x3446e80b, 0x4ba014b8,
7522 0xdae5ce95, 0x9d29bf43, 0x79c9eb04, 0xbb73d704, 0xe4f58655, 0x6b9c3252,
7523 0xae3ba7c7, 0xf461fa00, 0xefb1462e, 0xfb792aef, 0x3e8c2926, 0xec55f7e8,
7524 0xf7ed68fb, 0x3dbdfa4e, 0xfa18fbec, 0xefc0de7d, 0x72220909, 0xbff3e76e,
7525 0xee89e79d, 0xba829ab1, 0x917fd0b1, 0x13bf45d2, 0xc3f7d813, 0xe07be862,
7526 0x7cdab9fb, 0x65d1320c, 0x88de3cc2, 0xc2998bfc, 0xd7404963, 0xdaaa99b7,
7527 0x6fff68bb, 0xd4ccfc71, 0xf380bf79, 0xcbcd6f66, 0x57fc0379, 0xbfba2625,
7528 0x055f60b2, 0x7ad202d7, 0xb19f78a7, 0xddfee365, 0x2d5ff401, 0x69d8477a,
7529 0x69be82f9, 0xdc4cb2d8, 0xe3133b17, 0xc55fce07, 0xa00ebabf, 0x3ea7a003,
7530 0xb798883a, 0x67722f8a, 0xedac262b, 0x3c087aa4, 0x9084bd55, 0xac9f961a,
7531 0x8baff5a4, 0x530ccb12, 0x0bd030cd, 0xe3f4aade, 0x7b699dbe, 0x9e97f312,
7532 0x04bef24f, 0xc37b9df3, 0x3412e9e7, 0x011fce76, 0xdf3a207e, 0xce5ffd5f,
7533 0x06bfd557, 0x667ee7e4, 0x0ee7e4d0, 0x71d47fb5, 0x8957a07d, 0x82dbc790,
7534 0x39beb6f9, 0xab9c1716, 0x68be41f0, 0x5079c621, 0x30243aaf, 0x982fd57d,
7535 0xad741eb8, 0xe984bc79, 0xfa7d554b, 0xbd0f2692, 0xbbcd9f39, 0xfa829979,
7536 0x6b02abd6, 0x984f9fef, 0xd78b363e, 0x5eb1942f, 0x6e6f57cd, 0xe6b5fe61,
7537 0xd0284797, 0x50a3d52f, 0xae58931e, 0xfe3265a7, 0x91493cda, 0x44dc0cfd,
7538 0xafcfe848, 0xfa67a2de, 0xab9d76df, 0x0c41f308, 0xf1623f54, 0x869fc65b,
7539 0xfd23f1b3, 0xaa275f70, 0xc3f30076, 0x41ff95f5, 0xb259b87e, 0x7f693897,
7540 0xe9dcf30b, 0x17982cfa, 0xfa51c7f3, 0x2049d1dc, 0x1866ac4d, 0x91b7cde8,
7541 0xd974f79a, 0x68069f48, 0xa534773f, 0x7d0d6ccf, 0x8cf19d1a, 0x22bcc21f,
7542 0x1d2441f9, 0x6578c566, 0xd6d9a7e8, 0xd06ac7fa, 0x2e8ddb37, 0xf2ca7f96,
7543 0x40f922e9, 0x48167cd8, 0x510e3e6c, 0x0738f9c4, 0xecb5cf9b, 0x4cfa7093,
7544 0x0c3f6c24, 0x25125fb5, 0xf416b7e2, 0x9b1f97ef, 0xbd6023bd, 0x2d66fb7d,
7545 0xcc062fb3, 0x7d20b45b, 0x8b2f73dd, 0x99a2f837, 0x43b8835c, 0x167f1d12,
7546 0x7a9eff1f, 0xfcf78746, 0x4b7480d0, 0xf9841fa7, 0xb3f5e6cf, 0xdf30abda,
7547 0xfd34f668, 0xff0d2ec9, 0xe7bc2375, 0x1c7376f2, 0x02d87af9, 0x71b54a73,
7548 0xb3f7b985, 0xa4ddc6b8, 0xbdf30f46, 0x9fb68e67, 0x73f1a4b9, 0x7b9a9fc8,
7549 0x54fdf6bf, 0xc9b9df67, 0x788f1011, 0xbde1db83, 0x7ec0bf74, 0xf17e337a,
7550 0x7e94658e, 0xaf34fc47, 0xd303fc00, 0x6cf72a13, 0xb7e7e5a6, 0x9bf2c28f,
7551 0xd1f83f09, 0x2bbf50bb, 0x20d3cb07, 0x08ec0c19, 0x6f208fd8, 0x3dbdee8a,
7552 0x86fb8e93, 0x8cbbf799, 0xa33bdbe5, 0x68b3cdbc, 0x2cd8e73b, 0xc69c1bcc,
7553 0x42ef4df9, 0x0dc77f56, 0xfa1a9656, 0xb97e8280, 0x79a15169, 0xf227ff40,
7554 0x790050ff, 0x78b2d3ac, 0x51d5e0b9, 0xf8437e50, 0x4dd81e7c, 0x0916553d,
7555 0xcc9d5fe0, 0x73a399fc, 0x0a48e085, 0xde766997, 0x575b157f, 0xc90bc169,
7556 0x15a63fb0, 0xbb467eb3, 0x4367d4a6, 0x2c45dd3b, 0x629b24f7, 0xfbaa1f80,
7557 0xfb93996c, 0xe49eb807, 0x15fefbe1, 0x71b527f7, 0x498f5fb4, 0x3d12c170,
7558 0xfb413f13, 0x39d85894, 0x533b8f2c, 0x54e87f02, 0xdc73cb37, 0x02ac8aba,
7559 0xcdeb647d, 0xad0d696e, 0x7a226a9f, 0xce946b90, 0x9b7a011f, 0xf4f3e13b,
7560 0x8b2e2018, 0x3a55ce96, 0xf7d2a59a, 0xd31d2d34, 0xe713f9fd, 0xcfe76ff8,
7561 0xf7363a1a, 0x7a50f1d3, 0x1d579d39, 0xb49bbfee, 0x9c6faaf2, 0x39187d88,
7562 0x01fc50ee, 0x67f9c2fe, 0x715afcff, 0xb642a5bf, 0xc7ec3658, 0x6e3f7526,
7563 0x7418f803, 0x24fe789d, 0xc28d7043, 0xe8439b03, 0xd2fcea15, 0x305927c0,
7564 0x27f05e70, 0xfb1d7aa9, 0x9b1d8073, 0x77e9ebca, 0x9fef626e, 0x05ff1d17,
7565 0xd96b7fe4, 0x350a767c, 0xbd709f8c, 0xab7fb55a, 0x69b6f5d5, 0xc5145bd7,
7566 0xc13b7bce, 0xe93e814f, 0xf37d51fc, 0xa83c06be, 0x3971f1eb, 0xb1e4c73d,
7567 0xeedae81a, 0xfd2395b6, 0x5ff89f7c, 0xa0e87d06, 0xe6187bc5, 0xefe75479,
7568 0x2163fb00, 0x925c6371, 0xce6bc7d2, 0x9d42fd30, 0xaa9c246f, 0x919fe087,
7569 0x4f8489eb, 0x513ade3f, 0x77cf539f, 0x1af7adf5, 0x21eaa9d7, 0x3fd6830e,
7570 0x1cfee764, 0x00dff73b, 0x2e3c8145, 0xd02e5125, 0x04baa7eb, 0x894a27d4,
7571 0x6970f909, 0x76df9309, 0x5437d30b, 0xfed43f39, 0x8216f5b8, 0x2974a9fc,
7572 0xd8c9e7e1, 0x30e922ba, 0x823d7491, 0xd9499e76, 0x39f600b6, 0xff4a25e8,
7573 0xcc2d4bfc, 0xa9c57bcf, 0xf1aef5ca, 0xcafbd720, 0xd77ae403, 0xf337e078,
7574 0xa3fc6d44, 0x2ff30af4, 0x7c10afda, 0x193eba96, 0x5edd720f, 0xf81e35d2,
7575 0xeeb1add6, 0x1f9f012f, 0x361f98eb, 0x24fa8e12, 0xbc5fea9d, 0xdc8cfa26,
7576 0xe95c6a3f, 0x94d78b4d, 0x1fdfbe34, 0x2ce84171, 0x38ae4682, 0xcdeff799,
7577 0xf4a63a04, 0xf2897288, 0xc157abc7, 0x837f8398, 0x532c721c, 0x092d9bf9,
7578 0x2e08dbf8, 0x8f8c3dc7, 0xdb758b9c, 0x0d1c5893, 0x8710f2e1, 0x572e74cb,
7579 0xd110ee2f, 0x9dcd3f9f, 0xdcb834fb, 0x24f5c77d, 0x8dd7fb80, 0x5f097172,
7580 0xa53a45d7, 0xd17fb420, 0xe2c67a8a, 0x1e31cbb7, 0x8eab6231, 0x72726128,
7581 0x734a2064, 0xbde8c47f, 0x4c794d76, 0xfda6b26b, 0x9a596d0d, 0x28e0fcfa,
7582 0xe3b8fd4d, 0xf8f29a05, 0xed351bce, 0xac507c27, 0xbaea4f29, 0xa6fed35d,
7583 0xca6b674f, 0xac123014, 0x0283b9fb, 0x7dd74ed9, 0xcd3ee873, 0x7dbdfff7,
7584 0x0b8871c6, 0x33f6e29e, 0x733bbbf1, 0xa8161c29, 0x4ca57c74, 0x08505fdb,
7585 0x07c0450a, 0x4682dfd8, 0x853cd796, 0xdfbc2e42, 0x7d5a4d85, 0x6d56f162,
7586 0xf37da2b9, 0x0395e05a, 0x8a6a21f3, 0x646c88e1, 0x7934c43e, 0x75e80ebe,
7587 0x2fd51276, 0x91c63040, 0x1ac7c838, 0x1b7fdf6a, 0xb0c873fe, 0x6b3fc36f,
7588 0x7a80d5bf, 0x7fb7e2fd, 0xafa41455, 0xfe2d4e8c, 0xff168acd, 0xfc5ab9d1,
7589 0xfc5a5d5b, 0xe2d44ec7, 0xe2d6e6df, 0x8b44ae3f, 0x168f78ff, 0xb57389ff,
7590 0x6af24ff8, 0xa1529ff1, 0x8d5a7fc5, 0x2b19df16, 0xf4ccf8b4, 0xffbda83f,
7591 0x2aff0224, 0x7baeccff, 0x149ee228, 0xd185d11d, 0x0b474a81, 0xe798153c,
7592 0xc7e9bc32, 0xe922719a, 0x3a8dda81, 0xda8b87bc, 0x6b85db71, 0xbdca0fa7,
7593 0x491a5fd0, 0xf1244f1f, 0xb13b183c, 0xeef9455f, 0x40f8127e, 0xf2a15ea4,
7594 0x1e3970ad, 0xc50eff6e, 0x27c806cf, 0x290f0f6e, 0x361ec09f, 0x43c3dbf7,
7595 0x9087e9d1, 0x53fa838d, 0xee8bfa23, 0x2e3cd995, 0xe049abc1, 0xf225fd5f,
7596 0x04e90fbb, 0x7ef9d227, 0xe3a1eb08, 0x1a35187f, 0x203f18fd, 0x7fcfd441,
7597 0x74871908, 0x712007b0, 0x13e73e99, 0x5ce59f05, 0x7ee42f5e, 0xdbd9a70e,
7598 0x16a97006, 0x300919bd, 0x9e276a6e, 0xe227221f, 0x855ee9ae, 0x976fe093,
7599 0x7f06e908, 0x98f67d3b, 0x519c7d19, 0x289b87f9, 0x9678308e, 0x5172154d,
7600 0x30a3157f, 0xfbeca80f, 0xb2a5ca02, 0xcecf61ff, 0x4707a624, 0x50acd73e,
7601 0xf5c4d9e1, 0xfc0fa600, 0xe3c29277, 0x416bc433, 0xe064b9b8, 0xe63fb4fb,
7602 0xf319feff, 0x4925d193, 0xec78ec57, 0xf80cf10a, 0xa241f386, 0x8c73cd89,
7603 0xe8574c44, 0x8bc4d1fb, 0x49c7dffa, 0x7aee3859, 0xd632b289, 0xb7e828ef,
7604 0xefa3c60b, 0x045c5ba7, 0xd3a2bdfc, 0xabffd045, 0xc32b0996, 0xf55bac1f,
7605 0x7a72a5eb, 0xcc2563d8, 0xe7e1157f, 0x2729114b, 0x3d157c85, 0x94ed0f3b,
7606 0xf0bb32b6, 0x18ceab98, 0x792a2eb6, 0xed7e706d, 0xc81cf4db, 0x96133d2f,
7607 0x5ee14e0f, 0x3f1c9833, 0xa8e2cc9e, 0x6e9a566b, 0x0f497886, 0xbe3d078f,
7608 0xf80cdc92, 0xe6172514, 0x417dc181, 0x0defb0b6, 0xb61f5a0e, 0x498b24df,
7609 0x3c5bd653, 0xdac65978, 0x17483595, 0xd1af7e7a, 0x6487d4ba, 0x217f986f,
7610 0x4c4f8f9a, 0x1027227e, 0xbfd2f2ae, 0x5812a74f, 0x674b28af, 0x9feaf634,
7611 0xdc0146ae, 0xa93d38aa, 0xe93a35f3, 0xdeed6138, 0x2557f4e1, 0xfe601a77,
7612 0x741c50ef, 0xea413c42, 0x56bde074, 0xffb8e975, 0x37f0e4ef, 0x908217ee,
7613 0xe0946ff7, 0xd2f4268c, 0xd28e3cd9, 0xf477dae9, 0x6b25e204, 0x7e44cfc7,
7614 0xb8d7b066, 0x1e4f05a8, 0xeca1677e, 0xea9e041d, 0x2e94e8d3, 0x61a3f387,
7615 0x9e0edcc9, 0x3e002640, 0xca0f9906, 0xf66587a7, 0x59e3c3cd, 0x3fc3c1be,
7616 0x4c7f9824, 0xa2bfd056, 0x13c4f87e, 0x1b1bf217, 0xc6cbe109, 0x50037495,
7617 0xa561b71b, 0xa8737889, 0xa835221c, 0x3710251f, 0xfe6351d2, 0xfd395709,
7618 0xebf052ce, 0x3787b05c, 0x0d53ff8c, 0x1f45ad94, 0x61b94055, 0x90ad8be4,
7619 0xb981642b, 0x23bf3038, 0xa2b66700, 0xef7cfd46, 0xef07686a, 0x425f3e21,
7620 0xacf9d3df, 0x821ed31f, 0x0f63d1f6, 0x51f50a7d, 0x9b29a096, 0x3f75177e,
7621 0x45b04971, 0xb253855c, 0x4856d3e9, 0x8e28a17b, 0x4f47dfe6, 0xc646fd64,
7622 0xbb2d1203, 0x93217dd9, 0xb1678f09, 0x1faaec73, 0xbbb2de3e, 0xc6f818a9,
7623 0x53fd6d30, 0x96711e1c, 0x41678e97, 0xe7612a7d, 0x93fd7957, 0x7966debc,
7624 0xe598b3a9, 0xdfbe681c, 0xb58ffbcc, 0x50bf18e8, 0xb1b78f08, 0xdebc4dfa,
7625 0x093bd6ac, 0xfab1a78f, 0xb46f5e7a, 0xba12fcb0, 0xafdf35ad, 0xdc27e3e3,
7626 0x30de23af, 0x89cc74fa, 0xfa30de22, 0x35da97b0, 0x9d85bd65, 0x25a79523,
7627 0xfb53be6b, 0x1b8f9c7d, 0xf34b3933, 0x28d8699d, 0x34cefb6d, 0x710f2394,
7628 0x0b521b38, 0xf9eaf534, 0xb3a7226c, 0x276b3276, 0xf4d46e39, 0x6251517b,
7629 0x999fff61, 0xcbadd2a4, 0x90fb7404, 0xe2112b35, 0xb99581b4, 0x1f0144a0,
7630 0x3f994fe1, 0x6674789d, 0xcb054acd, 0xb8bfdc99, 0x2c44e566, 0x0b74a6ef,
7631 0x74accff5, 0x2d277961, 0x53f9f42b, 0x58950fda, 0x07ed1b64, 0x7ed34fca,
7632 0xed14f9e0, 0xd24f9e07, 0x337ea0f1, 0x9bca0efd, 0xde507f68, 0xe58dd2b0,
7633 0xb04b2bf5, 0x83d2bf5c, 0xe72b75e5, 0x95f1f3e2, 0x59ae7c5e, 0xbbf58159,
7634 0x3beb8593, 0x22485f7f, 0x93bbb9e3, 0xdde7f7c7, 0x16dcf1ab, 0xd476e0c3,
7635 0x32ffce01, 0x8988e788, 0xa5c63fd1, 0x8f5b1ad2, 0xe719bd80, 0x6a48f861,
7636 0x5b7ac1ac, 0xfd471b09, 0x24fc388e, 0x331d88b5, 0x5950fc64, 0x230df98d,
7637 0x7317cb09, 0xc45289fa, 0x9fc25fcf, 0xbcff4214, 0xabe5ab94, 0x71f91199,
7638 0x9923b3ea, 0xb0e279d9, 0xc72c371a, 0x8413d134, 0xcb8b5e7c, 0x33b1e78b,
7639 0xa9ced0ae, 0xe57b1cbd, 0x5f80a216, 0xbfab54bf, 0x6815a7da, 0x4af144f4,
7640 0xa533b635, 0x6769a7de, 0xda699470, 0x5cc92d95, 0xa47804eb, 0x1b1875b0,
7641 0xbd101157, 0xe3379b0b, 0x999367b8, 0xebd74bbd, 0x3efbff47, 0xeb97ad81,
7642 0x7ccbcf4d, 0xe446a6bd, 0xac6c23ab, 0xd7eb1398, 0xff3c3f01, 0xafdc58ab,
7643 0x43a33dcf, 0x1248dfff, 0x46be01d0, 0xf50cf153, 0x96174863, 0x4aee006f,
7644 0x1144f9cb, 0x848e3ca1, 0x7aa4bed0, 0xb3257fd3, 0x6633d0b8, 0x79a50b88,
7645 0x23f9679f, 0x392b9441, 0xaa391f1c, 0x8a55b8fe, 0x4e9da7f4, 0x7b56fb46,
7646 0x5b8d449e, 0x2516b2ae, 0x33d13e82, 0xb44f7e44, 0x169bbef3, 0x27463850,
7647 0xfaa7c5cd, 0x1ba2bd7e, 0x55e57cf4, 0x4cefaf0e, 0x77c601e7, 0x6afce8c2,
7648 0x0bbfa532, 0x0c83bf79, 0x2c3d5219, 0x1af0f684, 0x941fcabd, 0xfd0fe058,
7649 0xe62c5765, 0x2127b473, 0xc199447c, 0xde95b9e7, 0x7fa9249b, 0xf997e29d,
7650 0xe49be432, 0xbdb67cf0, 0x34dd972b, 0xc75fea4d, 0x5fb614e8, 0xf22b4973,
7651 0xce875cfb, 0xa735ecc5, 0x0f33bec6, 0x79c3726b, 0x7114715f, 0x48c42e41,
7652 0x5ee784d2, 0xc889bfc5, 0xb7a3c47f, 0x17ea8511, 0x40807251, 0x2fda873e,
7653 0x8fe276e1, 0xc2fcbf38, 0x2de70d32, 0x94f7aba6, 0xf9af51b9, 0x90c97642,
7654 0xb345f2cf, 0x4f123f1e, 0x6573eb6a, 0x4a5e07d7, 0x47f68b97, 0x517a60bb,
7655 0x5f784db9, 0x204bb89b, 0x83ce02a9, 0x99d9a7e5, 0x5adfaa7e, 0xe0e3fc44,
7656 0x2e37aed0, 0xa5dae005, 0xc2a9d01c, 0x8aabb69e, 0x3f06ec33, 0x0b8008d4,
7657 0x2e5873c0, 0x5f2171c2, 0xab95deef, 0x14ee4e10, 0x6935e786, 0x7cf9dc2a,
7658 0xf70ddb88, 0x566a2dbb, 0x3aed5bed, 0x7f15e7d7, 0x3b6bea0f, 0x8bd3cc45,
7659 0x9885e784, 0x286263f7, 0x3346cba2, 0xa79d0cff, 0xc129e61b, 0xbe00e3bc,
7660 0x58b3d704, 0x5ce00436, 0x5ad08f66, 0x31a97182, 0x971e123a, 0x53339f52,
7661 0x277aff18, 0xb467c659, 0x0b4dde73, 0xef9785c6, 0xc31eba47, 0x122c4fd7,
7662 0xbb7093cb, 0x5abf7095, 0xf0676a83, 0x3e28ea3c, 0xa0fbbedf, 0x2f3cb146,
7663 0x0adce90b, 0xd9431779, 0x614c3f11, 0x3b7ef2f1, 0xe806a282, 0xf309bc67,
7664 0x7cd41a1b, 0x055de514, 0x13e96bf3, 0x9c4c51f2, 0xd959d74e, 0xfaea043d,
7665 0xbe30a656, 0xa3e392b9, 0x22ecc4d7, 0x27e4db88, 0x6f9f9d84, 0x58fb472f,
7666 0xb6f4f38d, 0xd552fcb3, 0x49c950ff, 0x060df7a0, 0x221dde87, 0xdb2a77c6,
7667 0x0ef760ef, 0xf7893c76, 0x14bed235, 0xde7287a0, 0x6b4ebcbe, 0xe3d82f0f,
7668 0x0ca51b59, 0xc117bbb4, 0x03d9ab7d, 0x3b48eded, 0xae14b1fb, 0x3e48babf,
7669 0x354e71c4, 0xa28b1f66, 0x126435f3, 0x2297bf3c, 0x6ef784be, 0x09b3ed53,
7670 0x79243bee, 0x488fbeec, 0x6a92bfbc, 0x15ef3840, 0x5a5b8f08, 0x8ef7fe90,
7671 0xef7ffb67, 0x0e778b91, 0x93dcfda7, 0x7ea6e0c1, 0xcb064f77, 0x0607dd33,
7672 0x4adf7d15, 0xf960c948, 0xdc38bb3c, 0x9b9f33bf, 0x5573e5ac, 0xa2c75d6d,
7673 0x3b77e415, 0x8f7bde81, 0x0f2625fd, 0xef0847f7, 0x833f7f2d, 0x0de607cd,
7674 0x74fbf479, 0xa70bcf9f, 0x12297d83, 0xfaeeb79f, 0xda698cf4, 0x7bc85d79,
7675 0x3676e12f, 0x579856af, 0x4264f04f, 0x3ab47e78, 0x83c57daf, 0xfd7cef9f,
7676 0x9133e77a, 0x5068a7ce, 0x26fd1d38, 0x0c33ed38, 0xf80f9f3e, 0x0de3fe7c,
7677 0xc0c0ef76, 0xd3d4ebfa, 0xefc04476, 0x807bcec5, 0x7ef9d35d, 0x847a0290,
7678 0x63013bb3, 0xad7e1c4c, 0x0b3e9c85, 0xa171df39, 0x1f7c444d, 0xa4bcc04d,
7679 0xfbd58956, 0xab028bec, 0x8ebafd28, 0x7900c82c, 0x88d0fd60, 0x86f8c5f7,
7680 0x4b8b37c8, 0x97d8eb65, 0x870a0c2c, 0xe47f5e18, 0xb7f61944, 0x012303fe,
7681 0xf5cb507e, 0xab72f5f4, 0x5501ee09, 0x02e508e1, 0x4219f4fa, 0x2e505c8b,
7682 0x58a4c2fc, 0xc74f1906, 0xb114dbc6, 0xd4f1d46f, 0x973529a7, 0x3785ddf9,
7683 0xdea3c844, 0xbc3df934, 0xa15367af, 0x3bf73c84, 0x4b59bfc3, 0xef82172f,
7684 0xe8c9dc25, 0x7a0a94c5, 0xe63a7094, 0x13ecb47b, 0x03cdbf42, 0xb8bc19f8,
7685 0x4647df7e, 0x840c22d2, 0x2f4e25d3, 0xf5d4faea, 0xdeb6f3ab, 0xd6f300bc,
7686 0xf1301f01, 0x7a9d5498, 0xd5f21e2f, 0x60f72e58, 0x2627285d, 0x7d0f2c4b,
7687 0xdd7884bc, 0x3c46f134, 0xc78fb027, 0x0c93439b, 0x7e43de83, 0xfd7f1f0b,
7688 0x04ecff95, 0xaedfd5fb, 0x44d9f3c7, 0x45de72ea, 0x8ef7c8e9, 0x52bdf784,
7689 0xfb812a7a, 0xb89c8e67, 0xdd7a0318, 0x847aa94d, 0x0fc04df3, 0x115c3e41,
7690 0xff7f304b, 0x18b217c4, 0x5393ff46, 0x7497ae45, 0xfe5e4276, 0x979602c6,
7691 0x807ae16c, 0x057744e5, 0xf132dfcc, 0x4c2146c7, 0x1aa5e6ce, 0x868dbbf1,
7692 0xf68b8250, 0x4910ebe7, 0x2e81f510, 0xefab47bc, 0xe0cc91dc, 0x05485d50,
7693 0x47dc1e4c, 0x9ad7eeca, 0x3e30aa9c, 0x807de74b, 0xf91a8fbe, 0xf50e5c85,
7694 0xacbc7485, 0x32adeffe, 0x78d467c3, 0xa6c59f76, 0xe193bfc9, 0x8158aefe,
7695 0xafb43de0, 0x7935eaa4, 0xe8649ffa, 0x9d9dbf78, 0x65f9bfa0, 0x5b09f309,
7696 0x40990f83, 0xc5f757af, 0x86dd54d3, 0xfdf8eb76, 0xe626ebaa, 0x805ce006,
7697 0x4a7fc74a, 0x61527af5, 0xbc5f747d, 0xa7577a84, 0x47c22a67, 0xc97c87ce,
7698 0xef13a431, 0x0685210d, 0xae4be419, 0x6fd9a74e, 0xea6f1c2d, 0xa8a5ea93,
7699 0x69c23cef, 0x62f79559, 0x39e0898b, 0x62b32ba3, 0xd3152f41, 0x25cf3d54,
7700 0x6cff1c03, 0xe1fa8399, 0x8d2d37d9, 0xf57cf1e1, 0xb3da9a79, 0x797f4341,
7701 0x0333cba1, 0xde222fda, 0x2e8fa0b5, 0xe735166a, 0x7df2cfae, 0x144af0be,
7702 0xf5e98609, 0x87de270b, 0x5e1647e7, 0xaa412189, 0xe7e59d27, 0x3cf2ce7d,
7703 0x654f7f9f, 0xaf81b2f2, 0x75ea4b67, 0x08aefbea, 0x0ff3b97e, 0x7e3195cf,
7704 0xf700eff9, 0x00cba12a, 0x8de36e7c, 0xfe3cc17f, 0x0f4ed4d3, 0x3ad37ce6,
7705 0x6c3048e3, 0x5776be9c, 0x7e9eb84c, 0xff3828bc, 0x105af5fe, 0xfda9a70e,
7706 0x4c70cdff, 0xbfb1c0d1, 0x1c0d2cff, 0x839ff607, 0x995e9fe3, 0x8ffd2dfb,
7707 0x457fa21e, 0x7efeff33, 0x3db8e187, 0x8f9ecb47, 0x68e5fba6, 0x57f6f570,
7708 0xb0ed5f21, 0x272fef11, 0x78c5ad6d, 0x0417e89e, 0x3f2d99cf, 0x90c7e5fc,
7709 0xb77cb687, 0xf46305c1, 0x5cf343ea, 0x6187c883, 0x7dc3f644, 0x6f73ea3e,
7710 0x27ae366a, 0x0a49bdf2, 0x666f90c8, 0x55e495ca, 0x9d65e80a, 0x1fb8d581,
7711 0x549fc84c, 0x6fdab83f, 0x9ea88a6d, 0xad7dc567, 0x10d0dbde, 0x7c00eded,
7712 0xe6a5167f, 0x8237f91d, 0x67f2ad1f, 0x85eecca2, 0xa21da1b3, 0xe225b1fa,
7713 0x91a3bf45, 0xe5e40878, 0xdf7865e7, 0x53fefe00, 0xafc006ca, 0xe3d98e2d,
7714 0xb723ff45, 0x3b9836f7, 0x7e30ae9d, 0xe954fbf7, 0xd6fce4fa, 0xfe333908,
7715 0x4c82e7fd, 0xe61efcce, 0xfe762551, 0xf2132cb2, 0xbdf8bb08, 0xe3018a3d,
7716 0xf0c78505, 0xd532afbe, 0x8c8baf5e, 0x40d9a75f, 0xeefd55ff, 0x044f9031,
7717 0x9646c23a, 0xcd1e5dbf, 0x89bfe5ca, 0x907573c3, 0xf0079fc2, 0xec5d156e,
7718 0xe119379e, 0xa1af917a, 0x1d31b4d7, 0xe1cbd9e0, 0x75fdb17a, 0x62ee57bc,
7719 0x7fc470dd, 0xc13f6bf9, 0x25f6a17b, 0x0ea77cf3, 0x729fca2b, 0xee08aba3,
7720 0xcc97db2d, 0x2956ccf4, 0xa6105318, 0x2d4bae77, 0xbe7abe46, 0xf40eb86e,
7721 0x7fae1572, 0xa360fce6, 0x4293efea, 0x2ebbf045, 0xbf830be7, 0xdfb7f945,
7722 0xa267bf8c, 0x1165f03b, 0xd1b76fde, 0x1782f788, 0x65b9181f, 0xcaafad2e,
7723 0xa59e61d1, 0xe71980ee, 0xdd81a173, 0x82df03af, 0x903aae9c, 0x52c3bf82,
7724 0x3cc21d1e, 0x5728aaa9, 0xca41c40e, 0xf784dc0f, 0x30da9f7a, 0xe5f81d32,
7725 0x1d2578c9, 0x40dd35ef, 0x7dd74e81, 0x7b0463b2, 0xcf013f5f, 0x463759ad,
7726 0x5ff3077b, 0xf22472a8, 0xc97d9efe, 0x006d3df9, 0xd726919f, 0x2d3e5a6e,
7727 0xeb9c58b8, 0x82b66878, 0x9e171671, 0x9cb72bdf, 0xdbef1afb, 0x7ee4fe6a,
7728 0x481def82, 0x161daab7, 0x97395e39, 0xa10cfb33, 0x387bf079, 0xdc386be5,
7729 0xab9f2c0d, 0x839f975c, 0x8df70e65, 0xe65cf711, 0xab7831a5, 0x242753cf,
7730 0xca8c2fbc, 0x67c874ff, 0x88d8753e, 0xe36a7674, 0xaaaf3c68, 0x614e578e,
7731 0x797dd322, 0x058caed2, 0x634b8ebc, 0x0d7caafc, 0xf7d52fb3, 0x25cdbae5,
7732 0x8750e780, 0xbd2bf988, 0xe2062872, 0xb53b6a1c, 0x769eb7dc, 0x65d77f11,
7733 0xc411f25f, 0x0227a537, 0xcd7ba4f4, 0xf7d5f28a, 0xe037719a, 0xf1217cf3,
7734 0xfe5c8347, 0xce4efd80, 0xea230ed1, 0x321fbdbd, 0xfdc074bb, 0x3a509649,
7735 0x7be81fdc, 0x58f9052d, 0x17685a6f, 0xeccd93d3, 0xbd77b55e, 0x2c3c7813,
7736 0x9647df89, 0xe5d9fa04, 0xf410730e, 0xf8c4fa33, 0x71ec9f86, 0xd1c3fbe2,
7737 0xf436fc04, 0x53854019, 0xdfc4efd8, 0xfc4d2095, 0x7efc4efb, 0x0477ba79,
7738 0xd9e5e5f0, 0x7c0b7fb4, 0x2eed8ddf, 0x806f7967, 0xe64bfd32, 0xbf6325e3,
7739 0x7c0cde69, 0x64e17c2f, 0xc4d0a7bf, 0xdeb13beb, 0xc04ef467, 0x4ad1fc75,
7740 0xe759065a, 0x55bbdef5, 0x7887169c, 0xe14de754, 0x245efa8c, 0x98d26a5c,
7741 0x23c2a47e, 0xf0fb2e92, 0x03f32df9, 0x97c009bf, 0x363c33b4, 0x3e30348c,
7742 0xf51a3f52, 0xa51b525a, 0xd55a13c9, 0xf761cec1, 0x9e22b06c, 0xa7eef57b,
7743 0xde851e41, 0xaf7613d5, 0xc008d515, 0xf07130bf, 0xe78e72fd, 0xb3d65709,
7744 0x2f73a27c, 0x6f9f4d9c, 0x678af381, 0x5515e735, 0x24ed1f3f, 0x1628fc06,
7745 0x96531297, 0x116cf4c7, 0x377ec7e7, 0xc15ea367, 0x6ff207df, 0x847e8918,
7746 0x00e50653, 0xc3518efe, 0x55d01d18, 0x1ef18bbd, 0x9f5b137f, 0x7a8e5f7a,
7747 0x7c244def, 0xd9b2d35a, 0xef1091ef, 0xf2877003, 0xf024a249, 0xffde1a60,
7748 0xa2ff0155, 0xa618afa0, 0x3f919b73, 0x185ca0d4, 0xe196cf78, 0xe83f7e5b,
7749 0x3fbcb6ff, 0xeb3ae09d, 0x9018fe5d, 0xccca9fab, 0x53d8a3de, 0x6c8bae50,
7750 0x69a7789d, 0x4f6bc812, 0xd63c5a5b, 0x54fc3f23, 0x9f2af560, 0xa07eb01b,
7751 0xda07e817, 0xa78ebed1, 0x3219bf31, 0x8ca7b809, 0x8f900df8, 0x9f27caa6,
7752 0x3ce0e920, 0x894db76d, 0xaeec7a01, 0xbd83b6cf, 0x1253665c, 0xc2e8c20a,
7753 0x73c106f7, 0x37dc0aa4, 0x5f7e013c, 0xfc163dc2, 0x5aecfb75, 0x7ce4417f,
7754 0x35d29a5e, 0x77febc2f, 0xedff4c69, 0x8a28fbe2, 0xdf9063c3, 0x2fbc4279,
7755 0x77af78e6, 0xfb416f79, 0xe2dda231, 0x1e9cb1ad, 0xbd37de22, 0xf798affa,
7756 0x4f7b43b1, 0x78f8cfdc, 0xf8371e9f, 0x19e01b85, 0x15baf985, 0xab9f199b,
7757 0xe734bb78, 0xf3c65651, 0x1e5a53d5, 0x58e3dfc7, 0x0e7a7bb0, 0xf10b7c61,
7758 0x82e3d2a0, 0xe80e7774, 0xa26da171, 0x62a2fb0c, 0xa9f388ab, 0xdb4c9a97,
7759 0x5b33fbe8, 0x55dfa8f5, 0x499cf9f0, 0xde20c6f5, 0x28192224, 0xde48cfdc,
7760 0xb75fd418, 0x891ddff1, 0xf76d0758, 0x0830549e, 0xcf0c4c7c, 0x41ec9f08,
7761 0x1d5de0e8, 0xfc0169e2, 0xa3cc197e, 0xe4bf4045, 0x03ef3499, 0x76a6ee50,
7762 0xdbffde3b, 0x59f78954, 0x8cfbc244, 0xb9f48bc9, 0x8547af98, 0x2a38e467,
7763 0x9e017b3c, 0xdf1d2fa0, 0xf7cf728e, 0x4b140894, 0x425fb48e, 0xc74a7a7b,
7764 0x826f8ff4, 0xdea99bf7, 0xcd9c80a2, 0x400fedfa, 0xf889d5ce, 0x1d65267b,
7765 0x422409d9, 0x58dd835e, 0x189ccef6, 0xac9c985d, 0x7e31166f, 0x766c3f52,
7766 0x7f6c42cc, 0xafa04ef1, 0xa12b8a93, 0xe8ddac20, 0x8178bef4, 0x9be55f06,
7767 0xe3031aff, 0x71ea3454, 0x7a5e2a5d, 0xff909ce9, 0xbfa34536, 0x843537a8,
7768 0xea78aafd, 0x83c06fa3, 0xddb44f4a, 0x1f32e95d, 0xa8fc8fc7, 0xe45bd33b,
7769 0x164e841a, 0x85c7493d, 0xf15ab6fe, 0x1d6bc2fe, 0x1f478557, 0xc6bef9be,
7770 0x5771e032, 0x75bffa26, 0x4c984aef, 0x6669b27d, 0x72e3ec3a, 0xdfc02f2a,
7771 0x3e842e50, 0x3b247bc6, 0x6b0f788c, 0x0f25e6f9, 0x1fe578c0, 0xdf50751a,
7772 0x58e6787d, 0x5e04579c, 0x07d29c29, 0xccdef7a3, 0x0c2bba50, 0xc09f547e,
7773 0x27aeadfd, 0x0f38de6c, 0x7de14f6a, 0x1499bd24, 0x607c619f, 0xbbd33a76,
7774 0x80d97b68, 0xc3eecdf4, 0x1caf5be9, 0x62395eb1, 0xa411efbd, 0xe2f2e26f,
7775 0x647c167a, 0x05fbc1d4, 0x0391dc4f, 0x86eeb5fe, 0x6eaeb8a9, 0xec2c7bbb,
7776 0xda74eeaf, 0x72fc20ff, 0x9d7413c1, 0xceb0df79, 0x6be23326, 0x43da75c8,
7777 0xac37c8bb, 0x50e9c7d3, 0x4969e75d, 0x2bdfc189, 0xf012283b, 0x3cd2f897,
7778 0x65626f1b, 0x9f289dfc, 0x6f83d19e, 0x31e63473, 0xfbb3b4f6, 0x403e55c9,
7779 0x7a46bbc7, 0x743d21d0, 0x265b2b17, 0x106d7d02, 0xed8bc865, 0x5bf7186e,
7780 0xeeaf1df8, 0x7a0ca28d, 0x83317742, 0x2807e51f, 0x3dd3bbb7, 0xb0f96277,
7781 0xea8f7f1e, 0xdf5fd354, 0x1de173c7, 0xfae0857a, 0x42e71b3c, 0xf817ce99,
7782 0x3dcb851a, 0xe3d55f4c, 0x9eebebfa, 0xff7a83aa, 0xfcf01bd6, 0xacf940c3,
7783 0xa3457385, 0x4487d9a8, 0xdf3c7052, 0xaf782913, 0xca670a83, 0x1ec07361,
7784 0xe501e152, 0xe1fa6339, 0xa0e7e3e2, 0xf7602f41, 0x067e7120, 0x7262c9f0,
7785 0x0081ce02, 0x28f3831f, 0x48abc943, 0x47a913fe, 0xaf8fbcfd, 0x6571f968,
7786 0x3e18efc4, 0x125e5118, 0x469637c1, 0xd44557d4, 0xe77cf953, 0xe4e7fe60,
7787 0x2b5f2d0c, 0xfd5470e3, 0x041bbda0, 0x24cb43b4, 0xcff600c5, 0x7c98534b,
7788 0xe988972e, 0xec97dc16, 0x44994b7c, 0xf0058d6a, 0xb70865de, 0xb57f6893,
7789 0x472d3b46, 0xdb443e31, 0xcac21895, 0xe755bf2a, 0x878701f3, 0x7ecefcfa,
7790 0xe321d281, 0x8fa41f15, 0x28af181f, 0x757eb310, 0x83abec02, 0xbe95da22,
7791 0x21fc99b7, 0xf2da5d5f, 0x97ee03a2, 0x30bcc6cd, 0x7091fd75, 0x14bb6dec,
7792 0xd7ebbf03, 0xe780dc73, 0xe3dacb93, 0xb2fed18a, 0x7b850687, 0xda9f5f0f,
7793 0x15d48f5f, 0x6f5c2b33, 0xe1315d26, 0xd65aa3bf, 0xd8256976, 0x7e7e14b3,
7794 0x9f8f8c31, 0x062f88ea, 0xd7fcb2bb, 0x7e70c5c9, 0xdaa196d6, 0x1acfcafd,
7795 0x341cdf61, 0xe7a23fa2, 0xf83ab9ed, 0x0aede7be, 0xf78e5cfe, 0x3e9cf5b8,
7796 0xc7e30e95, 0xfee7b4e8, 0x5b6fdc0d, 0xd764fbae, 0x0fffc0cd, 0x09ae6625,
7797 0xeb9737f3, 0x7e1ed00a, 0x079a1f51, 0x7e7aa6f3, 0xaa57e41d, 0x1432d8fd,
7798 0xf071af96, 0x0fe02eec, 0x15a636a7, 0x39e95b00, 0xdfed0238, 0xe5c70f9e,
7799 0x247f68c8, 0xbc2f80b9, 0x339657a8, 0xdaeac57b, 0x1fdfd99d, 0xc671038c,
7800 0x8a13839e, 0xf3d05fc0, 0x2d2f9b21, 0xb680ffa3, 0xa51e43f3, 0x4e8c6fda,
7801 0xdd7904d9, 0xb47ad7e4, 0x3afa1e23, 0xb9ee113b, 0x1e0c3188, 0x41bb019f,
7802 0x1abcd79b, 0xabdeade7, 0x2c57691d, 0x4f961e20, 0xa97f611b, 0xda4773f7,
7803 0x69a41589, 0xd030976d, 0xb88aa45e, 0xfb009fc9, 0x456bfd5a, 0xef64bf79,
7804 0xbef6a355, 0x9fdf3f62, 0x65c7e426, 0xa0363f74, 0xfcc029bf, 0xa0e2757b,
7805 0x65efd771, 0x9e3ae264, 0xbcdbfe8e, 0x9ebc30ae, 0x49c911d4, 0x40d27ae1,
7806 0xc182ce4c, 0xe9cbc6ec, 0xb40d9f60, 0x1fa2cf17, 0xbefc3ca3, 0x6ed03230,
7807 0xc01c593c, 0x0d93bdbc, 0xc09efe22, 0x918ddaf5, 0x97bfabdf, 0x2c20c9e0,
7808 0x6772191f, 0x3764dfed, 0xc2abe76b, 0xc77fccd3, 0xe2fdb222, 0xca37160c,
7809 0x6e245afd, 0x7a1df7d8, 0xdd13bf3c, 0x1f96c5f2, 0xebb67d00, 0xe3054ce5,
7810 0x0b7bf82b, 0xf988a0e4, 0xa7edbd7f, 0x39041e62, 0x1e1c7073, 0xd793eb23,
7811 0x938c4507, 0x4a5db4f4, 0xed0a7880, 0xbec6e307, 0x405ca78e, 0xe3cd43bf,
7812 0xfaf10cd1, 0x08eef9fc, 0x1f8f28bf, 0xc99cb4f7, 0xf94efe01, 0xb019a3e0,
7813 0xe2be733f, 0x15756cf7, 0xf9d1fd01, 0x1bdefea1, 0xa5fa8cb8, 0xf41c5da9,
7814 0x19f5aafe, 0xcfe3eb86, 0x8bf20325, 0xf7c467d6, 0x095ab3cf, 0x7ece4019,
7815 0xb4c51e5b, 0xc3570b83, 0x4dbd33fd, 0xb77f0b82, 0xb9445db9, 0x3a3da0b5,
7816 0x4cbc50a0, 0x72c1611b, 0xee764ef9, 0xf9388663, 0x2e6ff07d, 0x7fa220de,
7817 0xf2cb48f3, 0x6798f5f7, 0xe58327a1, 0x5de7f461, 0xc6147c3c, 0xdc14fc59,
7818 0xc4ff4312, 0x6fd00dfb, 0x8102d3e5, 0xcc884a9f, 0x779818bf, 0x144f35d1,
7819 0xc05de607, 0x6907e5f9, 0x466d15bf, 0x3c0faff4, 0x1bc840ef, 0x21f7fd09,
7820 0xbc6f0ee5, 0x9f6d28ef, 0xf96062db, 0x3e35667f, 0x0ef685d5, 0xd0f3b209,
7821 0xa74f073d, 0x877d1e03, 0xb1fd07fe, 0xd20fed43, 0x0e3cf2ce, 0x57dfb066,
7822 0xd2fafdcc, 0xda419e9d, 0x8b3cf237, 0x327f7abd, 0x5b47b1e8, 0xe83f232e,
7823 0x6cfcc83d, 0xfc4ff643, 0x0aefe666, 0x570fd19a, 0x0edf2ad8, 0x83ea84fb,
7824 0xeedf5eb0, 0xd377b3b5, 0xbd55f9b2, 0x6f95aa02, 0x0bf705b8, 0xdff08fec,
7825 0xc9f75203, 0x53a71e5e, 0x791a47f3, 0x3f9a8dbe, 0x4493e6a2, 0x27cd43ce,
7826 0x7c614c69, 0xf3c32f23, 0x945bd001, 0xe77ecfce, 0x68cf2233, 0xc8a1bca8,
7827 0x71910773, 0x8ae24182, 0x46c0af2c, 0xc6a06e30, 0xbe540d17, 0x31d647c3,
7828 0xd06537b3, 0x227bfd7a, 0xc5434fda, 0x1c75d51b, 0x79865139, 0x8b2f5556,
7829 0xb0bfafe8, 0xbce3cf5f, 0xe9438c21, 0xc8617c4f, 0x7ece7e44, 0xcb47c95f,
7830 0x5937def0, 0xd28efcd2, 0xe71e1c57, 0xd9f07233, 0x978fb923, 0xe47b7ed2,
7831 0xf5e80332, 0x4a0b13fa, 0x9de8de40, 0xd7980665, 0xa6c51391, 0x4d9bc04c,
7832 0xb6b37dc2, 0x53b71d5d, 0x3ffffe86, 0x1f012a80, 0x00008000, 0x00088b1f,
7833 0x00000000, 0x7db5ff00, 0x55945c0b, 0xe779f8da, 0x380c2b9d, 0xa5117280,
7834 0x380a0ee1, 0xdb95902a, 0x9784268e, 0x4d32d45a, 0xe5450757, 0xdb698032,
7835 0xcbbaeee7, 0x5acd4d78, 0xb5aca8dd, 0xbcc0c1be, 0x1a163b60, 0x25a3b614,
7836 0xb68b9599, 0x3f9b5b99, 0x0286f328, 0xffb9f562, 0xcffebf6d, 0x3af39cf3,
7837 0x7e988ef3, 0xbf67dfbb, 0xde73877e, 0x73ce7d73, 0x9339cf3f, 0x196e39a6,
7838 0x9eb19fd3, 0xcadb2d1c, 0xc87b3b18, 0x630d81bc, 0xf7fc07ec, 0xacf2c653,
7839 0x18036312, 0x319abafb, 0x3e57deaf, 0x7c81fb3f, 0x02d8c196, 0x316358e6,
7840 0x33235a43, 0xbfd191af, 0x1d1fb01f, 0xf281ee9b, 0x988357f9, 0x5dafc237,
7841 0xb63d14f4, 0x94357f9b, 0x3d424779, 0x3677af13, 0x4f285204, 0x1872f1c0,
7842 0x9de912cb, 0x6edf2d22, 0xebf69cb2, 0xa613c2bf, 0xc53557ca, 0xf9a74e58,
7843 0x47f8e5f2, 0x636ffc0c, 0x98c91646, 0x97627f93, 0xdb74fc5e, 0x913f485c,
7844 0x5856091c, 0x9ed48557, 0xb10c0f7f, 0xef57ba26, 0x2d3ae330, 0x63f29bcc,
7845 0x5e608ceb, 0xd5ae71bf, 0xf5a46abb, 0x2566e0f8, 0x6bd6f9b8, 0x5d7c3826,
7846 0x38137d1d, 0xe8e0aac6, 0x05413feb, 0x4ffbebc7, 0xaebff1a1, 0xff49bb4e,
7847 0xbfd06f43, 0x5f7f3555, 0xee3449bf, 0x0b0d0caa, 0xa4f486cd, 0x5e00cdc1,
7848 0xcb235500, 0x1d80cc65, 0x795654c1, 0x66ad19c7, 0x75257b5f, 0x6cb171b1,
7849 0x946f7c14, 0xfdf0dc0b, 0x25ae6592, 0x985d5219, 0xa1dbb186, 0x705ecebd,
7850 0x086bf417, 0x41708f0b, 0x89ac133f, 0xc2efaeb4, 0x28301516, 0x08f06eff,
7851 0x838f15d9, 0xfcc42a2c, 0xf2c541aa, 0xe37f1c7a, 0xb5f70c73, 0x0fc7c8ca,
7852 0xfc332fd9, 0xba30eece, 0x777ea193, 0x7996c7cb, 0x06dfce30, 0x3ee0e639,
7853 0xc909f32b, 0x3ee19779, 0x6dc726b3, 0x3d8c2185, 0x0dac616e, 0x50f6daf3,
7854 0x725eaf5c, 0x405de7fc, 0x06afec0f, 0x77c90f56, 0x25aa4726, 0xcabed7c3,
7855 0x01f9a7aa, 0x68b2c435, 0xa50d5f5c, 0x08574d55, 0x8916d6ce, 0xaf7ca5d6,
7856 0x77043d62, 0x8851e586, 0x7d2b5a93, 0x16a4726f, 0x71e6fa66, 0xccf7ffad,
7857 0x9fd00d2e, 0x433fff61, 0xdadd9e11, 0x906dfb9e, 0x60e45a7a, 0x11aef87f,
7858 0xf0763974, 0x50ed5937, 0xfaed895e, 0xdbd8f631, 0xf30ca9e5, 0x9c2c9e86,
7859 0xffb7c1f7, 0xe90ed591, 0x6fcbfb77, 0x50edf2c3, 0x6ef90adf, 0xcda54f7d,
7860 0x6624bfaf, 0xf9466971, 0x0fb16ad2, 0xf7dbe581, 0xf3881caf, 0xdcc1d068,
7861 0xa59c61c3, 0x474f2365, 0x9fd83a20, 0xb5b8478e, 0xec3d58e8, 0x54d35747,
7862 0xe54af919, 0x43058c27, 0xf619bb3e, 0x83d9f207, 0xfb035b99, 0x93ffb953,
7863 0x955fb8e9, 0x068b7a39, 0xbc341296, 0xbe02bdcd, 0x2d18e507, 0x2c53e212,
7864 0xeccf5f1f, 0xfb62258c, 0xb7dc08bc, 0x2a310637, 0x41f997ff, 0x6bdbc71d,
7865 0xbc7bc0fc, 0xabc601b2, 0x47efdb90, 0xa17c003e, 0xf2a5f11e, 0x668e6fa3,
7866 0x4f46b158, 0x78cfee24, 0xd0f8171c, 0x369fa2c7, 0xac0ee16b, 0xfbe0fdd7,
7867 0x2de8b06b, 0xf5c0e1c9, 0xb68c62b8, 0x68cfc47a, 0xbf14c277, 0xaacd7d7d,
7868 0x4ff0f6a1, 0x221dbc42, 0xa07bbae6, 0x22587167, 0x470ee5fe, 0x30d2a87c,
7869 0x3643f207, 0x077a8009, 0xe66165e2, 0xe9ebcc94, 0xd415b18a, 0x7b56dbdf,
7870 0x57c735b3, 0x336993ff, 0xd07d1d33, 0xc12a6221, 0x0479ef53, 0x6153d9e7,
7871 0x7d856db6, 0x827e0bf8, 0x334f2f76, 0x5850e578, 0x56bcce8f, 0x193a3c02,
7872 0x0075bb3c, 0xd9b57fac, 0x73ae1ef1, 0xd7e343fa, 0x183a5e60, 0x788c5d61,
7873 0x8b9ed459, 0x726d12fb, 0x3be3807c, 0x22db8e8d, 0x06978961, 0xc1fb523b,
7874 0x08c2b356, 0x98566f0e, 0xfce7d859, 0x797c7cf9, 0x54b841a6, 0x36f4b808,
7875 0x7c43f626, 0x5fad7aed, 0x74f98316, 0xca095869, 0xdf312e87, 0x988f2073,
7876 0x712e9f1f, 0x4117d31f, 0x63bad2fd, 0xeb7eb9fa, 0xeecc60af, 0xfc7eb8c9,
7877 0x301fb88b, 0xffd785fe, 0xa1afddf8, 0xf76fceab, 0xc004b0a5, 0xad22e913,
7878 0xc71dbbeb, 0x9df58b66, 0xd63ff5c5, 0x87a713db, 0x073d3975, 0x887f9cf4,
7879 0x527b69f5, 0x5d7d6c7e, 0xc27cb69a, 0xa5927d8b, 0xaed7de3e, 0x7e58f1a2,
7880 0x497be02c, 0x9908d85d, 0xe20a59e3, 0x061ba959, 0xa55bc3f1, 0x8b3e051f,
7881 0x5debbf05, 0x1413e02a, 0x5af2859a, 0xfe328f81, 0xccf800a9, 0xe1e4f6d6,
7882 0x0b2f663c, 0xea7e70d3, 0xbe51fc26, 0x1eaa59cf, 0x30e22577, 0x1bf5cfcc,
7883 0x66f34dc9, 0x2b86ff3c, 0xf21ebdcc, 0xbf95cd06, 0x21bd454c, 0xbd436353,
7884 0xf0104b61, 0xfd8c1180, 0x8bcfec59, 0xe18c1fc0, 0xcb16be54, 0xfb7883a3,
7885 0xee3567e8, 0x70bed095, 0xe1e1336c, 0x9b6695cb, 0x3115630c, 0x8530ac60,
7886 0x47aecc79, 0xe63d7fb8, 0x61dbfb1f, 0x1de2839d, 0xfeb0f151, 0xb89a1139,
7887 0x1c3cd0bf, 0x9c032743, 0xc70e68d8, 0xc207b840, 0xe8b30a7f, 0x36c65fb0,
7888 0xa7ee9068, 0xe652f858, 0xa78e9c4b, 0xc70ebb32, 0xa839907b, 0xbd2ef1de,
7889 0x1c1d019d, 0x3060f407, 0x8b9887ef, 0x373067ca, 0x979933a5, 0xb59cffea,
7890 0x03a15e53, 0xfd39ffc0, 0x8d9ffe39, 0xb26f0992, 0xc7be01e2, 0x2f06b382,
7891 0x7e4c7585, 0x6199352e, 0x0803359f, 0xf79b373e, 0xb1c38964, 0x1db8eacd,
7892 0xf05bdfd7, 0xd0354bed, 0x25e8c68f, 0x27c6bbfc, 0x78100dc6, 0xa27ce3f8,
7893 0x09e397ad, 0x06398390, 0xd8af70e0, 0xe5ed7bd2, 0x8cbd7093, 0xfe9e4859,
7894 0x9e5fd04c, 0xb3fd666c, 0x6dd97c71, 0xa5d8b9c0, 0xbe42468f, 0xd6cc8c60,
7895 0x5bde3cc3, 0xbede48ce, 0x13765c37, 0x869f20ae, 0x7e8bf7f6, 0xba998d27,
7896 0xcbd41faa, 0xdb3dbeff, 0x20c1690b, 0x7eed97dd, 0x7fbe35f8, 0x4830aaed,
7897 0xcba92427, 0x2d36b227, 0x065275c2, 0xf3f1fb94, 0xf5d5b3fb, 0xe198e00e,
7898 0x2328db98, 0x0f8ccdfd, 0x18267fe9, 0x90d843b2, 0xbd1f641f, 0x9de9eb28,
7899 0x0ddf4574, 0xef10d8f3, 0xb2fb8b98, 0x67afbef8, 0x2d33bd23, 0xca2468fb,
7900 0x5d7ca3a9, 0x00dd025f, 0xd5d3b206, 0x7e80d120, 0x883e80ce, 0xb7a073f9,
7901 0xdaa17a61, 0xd045e94a, 0x577bf0b3, 0x9ef28db5, 0xec72c2f8, 0xcbdaee77,
7902 0x4e06475a, 0x6df0852b, 0x36b7c089, 0x8c13578d, 0xb255b4f4, 0x625c7ca1,
7903 0x0c1b1b6a, 0x1f525bf0, 0x671d836f, 0x569e4d65, 0xb7b17e9c, 0x75b71f30,
7904 0xad45e1c1, 0x055c5698, 0x6cbd078c, 0x1ff85cae, 0x7f5d0788, 0x7dda72f9,
7905 0x7ab67e50, 0xbe7f8d14, 0x77e34eda, 0xfa501756, 0x37e3bc7e, 0x4b7b0f38,
7906 0x15846b47, 0xe132e577, 0x1d0d7dcb, 0xe7c858da, 0xd23b25d9, 0xe676dde1,
7907 0x6d3d0376, 0xb5b971d6, 0xd216e419, 0x29cc98e5, 0x50ca3e2f, 0xc71e38ae,
7908 0x509c1ef1, 0xdcfd879a, 0x8b48aa3f, 0x9efa1ef5, 0x1f7888b1, 0x8f0cddde,
7909 0xbf5f0059, 0x7844b6f4, 0xfd634978, 0xae59ea19, 0x0be93223, 0x2a985abd,
7910 0x727bdff4, 0x7b05db88, 0x626f78bb, 0xc5b7f214, 0xb8546b3a, 0x0ceb5f1f,
7911 0xbb9d6be0, 0x97f68f6f, 0x9ee19d77, 0xbe433eef, 0x4be705f4, 0x5e6733b0,
7912 0x8e65be40, 0x76fee1b6, 0xf404bb09, 0xcf9460c9, 0x47417a95, 0xdf3057c0,
7913 0x14e6c419, 0xd5f73e42, 0x1748b1d8, 0x7caa1e38, 0x7949df0a, 0x5f84b9f5,
7914 0x6de37d5b, 0xecffccf7, 0x725fc805, 0x903a5c6b, 0xa7989753, 0x575c4deb,
7915 0xfa86d99d, 0x0da49a63, 0xea784a5a, 0x934c3a26, 0xc0a5daac, 0xfabc7657,
7916 0x303fc0e2, 0x1b181bd4, 0xdadfdf05, 0xe77c4c14, 0xd4ed9d2d, 0x22ff6c52,
7917 0x53caff6f, 0x09b2fcbf, 0x462b27d3, 0x3ef112fc, 0x5ae09c3e, 0x21d2fbfc,
7918 0x63436788, 0xbfa01b61, 0x5e486f5d, 0x99631653, 0xc4560735, 0x6d867cc0,
7919 0x840cd0e9, 0xb49d7874, 0x21a1d312, 0xf8658705, 0x95bc5efe, 0x21b231e6,
7920 0x72458e5e, 0xecfee819, 0xa87fa4a7, 0x9a8c92f5, 0x320763cb, 0x44327e9f,
7921 0x7dc05cf2, 0x62721959, 0xb63fc904, 0xdbd9fa91, 0x99e3f532, 0x7cd00eb4,
7922 0x7a45de70, 0xb70bc91b, 0xecf116ab, 0x46cd2392, 0xeba17afa, 0x4bdfdc79,
7923 0xca1b488e, 0x571a7d8f, 0xff589de8, 0xf9d69694, 0x50b1dd46, 0x35fbe41d,
7924 0xbe0998ea, 0x21ef0c57, 0xd83159b9, 0xc1dc70ca, 0x805bdd2f, 0xdc6ca9f0,
7925 0x38fd4b5b, 0xea09368d, 0xd2bdec95, 0x8d94728a, 0xc464b667, 0x7f9e46af,
7926 0x86dd9c62, 0xf6a4b572, 0x2b6f9e5b, 0x58217ca4, 0x3fac5a13, 0xcf69eb8f,
7927 0xdac53909, 0x117f88b3, 0xfb7d5aca, 0xc67c04f5, 0x5de39bef, 0x3ecc8b31,
7928 0xe97206f9, 0x8c59d202, 0x1b6fb79e, 0xe08e333b, 0x49728b72, 0x3d39e7e9,
7929 0x4e509973, 0xacfcb9ea, 0xf8817e07, 0x17fffd01, 0xd1c8aff6, 0x6cca5958,
7930 0x3ec77584, 0xb4adb067, 0xd338fade, 0x3921adfb, 0x5575e8aa, 0x89585f42,
7931 0x36fda055, 0x804e43b3, 0xb90be671, 0x0cd6b4cb, 0x319e43d4, 0xa409b5db,
7932 0xa3de81d7, 0x4c667921, 0x0658bd40, 0x4fd12f3d, 0xdf8733cf, 0x366b3c92,
7933 0xfdb143db, 0x2fefd6ad, 0x3157f9e6, 0x444b424f, 0x31c85748, 0xf23de03b,
7934 0xa127764e, 0xeb0357aa, 0xe790701b, 0x6dfa1213, 0x7aba055a, 0xfa958252,
7935 0x7c11f801, 0xca19e761, 0x243ca509, 0xb841e39b, 0x47fa48c3, 0xe1a2c454,
7936 0x9af0fc8b, 0x1123bd69, 0x5bffeb0e, 0xbfa84af6, 0x1bb33ffd, 0xbe7025f1,
7937 0x3fdc0945, 0xb9890bf1, 0x97578834, 0x45af54f5, 0x8febbed7, 0x34a5aed0,
7938 0xed7686c3, 0xd821e43e, 0xf49ea84f, 0xe61096a9, 0x99697a42, 0x7d46e91c,
7939 0xa7b42dec, 0x88661e90, 0x7c4626f6, 0x40c665ba, 0x0d0387e2, 0xf35c1800,
7940 0xaf6f034a, 0x2641f45b, 0x963cbff6, 0xc94ac7e4, 0xf48136bd, 0xcbe49935,
7941 0x6a8fc149, 0x6533bcc2, 0x9cb9af28, 0x939c70c2, 0x61569760, 0xa22092bd,
7942 0x7b309abb, 0x7dd7f20c, 0xdf132dff, 0x790e19ab, 0xf225f133, 0xb64cd4c7,
7943 0xfe4184c7, 0x351fb161, 0x67faeeb5, 0x69c9bfb1, 0x3281aeb4, 0xe2f5445b,
7944 0xe99f3f79, 0xfdc73b78, 0xdbd45ac1, 0x20c50241, 0x4e285efc, 0x2a07c866,
7945 0x44cec613, 0xf7ec52bc, 0x28df82e9, 0x630363fd, 0xfc63ea2e, 0xf5f98cdf,
7946 0x07aba426, 0x201d4c4b, 0x92c9d839, 0xbf682115, 0xbd90e83e, 0x1e5bd406,
7947 0xd35fb3c8, 0x7fb0120b, 0xb3c24cfb, 0xf27ec562, 0xbdb843ce, 0xeb6463dd,
7948 0x7d847f49, 0xdf1ebccd, 0x22633c2a, 0x52c7edfc, 0xf397a703, 0xd7482f38,
7949 0x714a3b07, 0xe34d55de, 0xcaedfc23, 0x8757f319, 0xf18bdd12, 0x23db562e,
7950 0x5ea1274e, 0x32a94050, 0xc14e329e, 0xea5da314, 0x818df68f, 0x4239aaf4,
7951 0x7832ad0f, 0x4dfd21a7, 0xa31e3937, 0x642eca71, 0x7fd8bea1, 0x9c3f5a4a,
7952 0x32fbf77f, 0x253d3c43, 0x3214f5f6, 0x45a7c46c, 0x4c2f8421, 0x8ebf1de4,
7953 0xf41cfd20, 0xc737c21a, 0xde5286ef, 0xccc7b7a1, 0x1c5cfc47, 0xca71f84c,
7954 0x729fbfc2, 0xcd7e1186, 0x87f95dfa, 0xaa7be00c, 0x78784f50, 0x3f2645aa,
7955 0xca96dfcf, 0xb9c03d5e, 0x67d5ca6b, 0xd75da053, 0x3772afb2, 0xe2beda43,
7956 0x3f9438f3, 0x4c5456b3, 0xcab376c2, 0xfc8fdd96, 0x3d7446f9, 0x441069cb,
7957 0x35b6e1cc, 0xd711bec1, 0xd5ca7fd9, 0x03cbe47c, 0xcfcf9dcb, 0x0983f287,
7958 0xcf88678e, 0x112bdbe8, 0x7d6f951e, 0x73fa8711, 0x7b2bf377, 0x6dfd215a,
7959 0xfa79e388, 0xf8dee2be, 0xb099d8d5, 0xb0b52abf, 0xb73f805f, 0xc45e3a27,
7960 0xbce355ef, 0xa2eed829, 0xe11f2dae, 0x9add96c6, 0xa5a17dde, 0x76849f7e,
7961 0x254b5060, 0x0b3bb2a5, 0x7929d1e7, 0x8444a543, 0xb00be823, 0x6f168bee,
7962 0xb9e21868, 0xb7cbc3d0, 0x5347d7ab, 0x077e148b, 0x91ee5768, 0xb3d226ed,
7963 0x6f9c7add, 0x2872fd60, 0x58b77aa7, 0xbc3cc65e, 0xa9e9ac3c, 0x7b7ef8bb,
7964 0x179fb0bd, 0xc56f2476, 0xf7b4befd, 0x3b7f1495, 0x7ebd3038, 0x17fd7cbe,
7965 0x8e00bf11, 0x8744a117, 0x5060d5f8, 0x3b5d7fd9, 0xd5f85462, 0xbdd523b5,
7966 0x762f8fde, 0x6cc1be09, 0x88c9dc9e, 0x2e4f76f7, 0x9f0a55ea, 0x164f4660,
7967 0x9e696fd9, 0x1457b42c, 0x3d0ac33e, 0xf6ee5429, 0x7dfd60a4, 0x7d9acf68,
7968 0x8aed96e3, 0xfdcf5dad, 0x364d2e8e, 0xc56e87e6, 0xcdefd2bc, 0x59ba97d6,
7969 0xbba7caaf, 0x09d3f9d5, 0x73b69fdc, 0x83b15ea7, 0x30476165, 0x568fb2ab,
7970 0x5c11afae, 0xe057aafe, 0x2e6c68f2, 0xafe00dfa, 0xe7379a04, 0xddb93be3,
7971 0x23b86fbc, 0x62a9f916, 0x830bef9f, 0x51ca067c, 0xaf256f3e, 0xde7021c0,
7972 0x20bafe2b, 0x967bfd16, 0x4e508d44, 0x3f88516c, 0x2f9c4d2b, 0xbe81d4ad,
7973 0x4976819a, 0x5ad3c8c9, 0xd16c57b4, 0x1c1f5ac5, 0x6e1e6c16, 0xb85d3a44,
7974 0x1fd1b865, 0x1f6e561f, 0xf30ad879, 0x6b5db8bc, 0xd4af29c3, 0x7d429fba,
7975 0xd976e56c, 0xddf462e3, 0x17fa8768, 0x628f07cd, 0xb85b05bd, 0xbf69429f,
7976 0x744e7370, 0x873cdfb1, 0x33c3576e, 0x0fcea3d3, 0x07e7526b, 0xf391aea2,
7977 0xdc376f3f, 0x3c8fceab, 0xfd9fceac, 0x10d3a3cb, 0xd7644aed, 0x87ea3253,
7978 0x461fe79f, 0xdf6e71b9, 0xdfe4a11b, 0x15b8a2f9, 0x9b85def5, 0x7d8670d5,
7979 0x701f5093, 0x2e48936d, 0xe903ba96, 0x65ba6fa3, 0xd7e2b96c, 0x93c7f34b,
7980 0xd56ae632, 0xbf5f5fc6, 0xd9a67993, 0x74b48fd1, 0x23d3c8f1, 0xe1defd7d,
7981 0x7b47a4d9, 0x1bdc7027, 0xdb3329d1, 0x165f68ad, 0xeedfe28d, 0x7d963a5c,
7982 0x6d882205, 0xf88f9638, 0x4484f457, 0xf5e8b6f2, 0x2f9177d4, 0x3199ec77,
7983 0x0569d281, 0xcfc50f04, 0xf245b0b2, 0x32de4086, 0xfcede38a, 0xc19b92cd,
7984 0x32aee7bc, 0xc541fca8, 0x58f3d41b, 0xbefea350, 0xdfc0e9b0, 0xc4bfe825,
7985 0xe51e92f8, 0x4316c956, 0xfdcb1f80, 0x65e1ea0e, 0xd9d918e7, 0x183f7565,
7986 0xcd73f2fa, 0xbae1d657, 0xb8fae19b, 0x07d3e78a, 0xf806634f, 0x857efef8,
7987 0xfea11233, 0x32b5359d, 0x3982adc2, 0x9224b31e, 0x860de99d, 0x7d002c79,
7988 0x9069f509, 0x2baeb4b7, 0x0db9fb9b, 0x4cce54f1, 0xb5857e50, 0xbe1ca2e5,
7989 0xe36218d2, 0x5cb6b0fe, 0x4217e40b, 0xc256e11e, 0x9c7c1236, 0x8e657fc8,
7990 0xf9bf762f, 0xe7f93ee2, 0x8fae46d9, 0x03deb53b, 0xd6728708, 0xff70ed4e,
7991 0x6139ebfc, 0x51c3275d, 0xcf6808df, 0xaf0fe46c, 0xdf69eb32, 0x307e9aaa,
7992 0xec577ff8, 0x512ec500, 0x59ff6dfc, 0xe21070f6, 0xfec96af5, 0xd4c651bc,
7993 0xf115a7bd, 0x724cd4b8, 0xce5ae1fe, 0xd9d06bcf, 0x6cd7fd02, 0xf37d274a,
7994 0x829ec961, 0x4c9b65eb, 0x1e810764, 0xdb3abf18, 0x3e81d7a7, 0x9fa132e8,
7995 0xbdc834b8, 0xe70fbf15, 0x8ccd79f6, 0xde17d214, 0xe45e3c92, 0x3867aec3,
7996 0xe64cd4bd, 0x64f353f8, 0x0cff7d0c, 0xfa831aa7, 0x6a4bd722, 0x3d72a536,
7997 0x60f3e656, 0xfe210bbf, 0xe62f1358, 0xf34ac035, 0xc9f5f452, 0x8973c716,
7998 0x5e2ceb7e, 0xf4247a01, 0x995bfc5f, 0x95829fa1, 0x3c92dc44, 0xaa7217af,
7999 0x8dc99367, 0x52d3eefe, 0x3f9e2b61, 0x13dfb35c, 0x1dcfdf39, 0xea26df6b,
8000 0x58bc5f91, 0x4ffd7933, 0x3567bc71, 0x7ef195d6, 0x53dbb7f0, 0xbd3fcf50,
8001 0xf70234c9, 0xce70d4e9, 0x72c773b7, 0x25d801bf, 0xee90adf6, 0xfca8d449,
8002 0xb9127bab, 0xd13fb09d, 0x3ce9e94a, 0xc90c47ee, 0x0cff242e, 0xf1f115ec,
8003 0x17ec75c0, 0x85f58aed, 0xc7d27e47, 0xb0f8147c, 0x4e7f7c71, 0x5c91223f,
8004 0x58a4f584, 0x7bfb9f20, 0x4e75f913, 0xeca2f90b, 0x0e51e00b, 0xbfc15bc9,
8005 0x49fc459e, 0x27f014c4, 0x51fc2fbb, 0x60c3c7e3, 0x7f1098ef, 0x1f683f00,
8006 0x327afc15, 0xf011f693, 0xe7a1f087, 0xf00dd349, 0x285f6d47, 0xe5a9adeb,
8007 0x5da047f6, 0x3270f801, 0xa0bcefd1, 0x0427ac26, 0x3c14b7cf, 0x8e775a60,
8008 0x205a39ff, 0xe6c9e41e, 0x4befe434, 0xea1b20a4, 0x7f844bdd, 0x467cc97b,
8009 0x8b658df3, 0x68d7a424, 0x0ec895e6, 0xec266d66, 0x003d27ef, 0xfc3a3f73,
8010 0xf32355e9, 0x58637b97, 0x8f7f2a98, 0x3f554631, 0xfaaf12cf, 0xba746f7e,
8011 0xeb78fbea, 0x627e5570, 0xfaaa1dda, 0xa8c6d9f7, 0x351b3ff2, 0xb27f555e,
8012 0x6f2ab27d, 0xce2d1667, 0x60baa5bf, 0x6f1fda24, 0x5e921757, 0xd1970810,
8013 0x5baf8386, 0xea46206d, 0x00b453b4, 0x0efdd1bf, 0x7c87892e, 0x14d33aff,
8014 0xe8c7e02d, 0xe25783d8, 0xd5a2602d, 0x43eff105, 0x80495e0f, 0x305d747c,
8015 0xc8c5dfcf, 0x67581f1e, 0x9332e29e, 0x093630bf, 0xeaed3ce0, 0xf66843a2,
8016 0xca7cb27d, 0x75a478fc, 0x3ff33267, 0x7566d8b7, 0xe53d6184, 0x547f52bb,
8017 0xefb52152, 0xfcf9ccbe, 0x393fb827, 0x760a7aff, 0xb18fc917, 0xac6c341c,
8018 0x5be74cd1, 0x78bba8cc, 0x7c0cafcd, 0x8633b253, 0x6a96b9fe, 0xc22d67d8,
8019 0xb7a948cb, 0xc1e942da, 0xdf4a68ea, 0x62b2b6ad, 0x756b6780, 0xab87a51a,
8020 0xa47e546d, 0x1fa5147a, 0x3d29db56, 0x69405d5a, 0xa521755b, 0xb34f2812,
8021 0xb36c6f90, 0x3c21d5ad, 0x33b0da5c, 0xd9fe3e30, 0xe1f2df17, 0x519d96ad,
8022 0xff2a15f6, 0x4dcf64ca, 0xb20d75a2, 0x945b9f90, 0xa9ffda1f, 0xe8d1f915,
8023 0xf5e1236c, 0xd59b7368, 0x48f3cd98, 0x99977567, 0xebca1357, 0xf5ebfd69,
8024 0xfe470cf7, 0xa669da30, 0x50bd497a, 0xbdeb0b2f, 0xf2c5a317, 0xca1b7a45,
8025 0x3f04e7cb, 0x901cd10e, 0x5e909c71, 0xc834367e, 0x144ef9c0, 0x5df85fa8,
8026 0xf5d5a3f1, 0x8706f1f2, 0x9df3a22f, 0xc4cdb3c1, 0x15b9147f, 0xc18de11b,
8027 0xd12ec5f9, 0xe6887953, 0x2efd15b8, 0x09ded55d, 0x84e3af88, 0x67a71f9c,
8028 0xa60f3869, 0x94f92209, 0x1adf7f27, 0xcdc5f90b, 0x398c70d2, 0xdc286718,
8029 0x96a1f642, 0x6feb31d3, 0xb6b8fae2, 0xa815f4ad, 0xd6323c77, 0x15a11eb6,
8030 0x81258fbd, 0x5557959e, 0xf2728190, 0xf448db38, 0x31d43f3d, 0x6a6df10f,
8031 0x46bdd006, 0x13f40920, 0xfc4c105d, 0x6a7f7bb3, 0x53cdea0e, 0x0cbdd60c,
8032 0x292ca2e8, 0x4a7ef087, 0x648e6b3f, 0x445dfcc1, 0xaca25327, 0x9e1b257b,
8033 0x194ce49e, 0x71bfc777, 0xd2493d2e, 0x7ca9c7fa, 0xc31e3922, 0x5c1455f9,
8034 0xf5f9f3d2, 0xebf89e90, 0xb3f12b24, 0xc9190701, 0x21f19edf, 0x7fd15fc4,
8035 0x61f918b5, 0xeb073586, 0x427ae9c5, 0xfba0ee31, 0x5dc52d7b, 0x07d0cd40,
8036 0x2f1efcfc, 0x8c78f0b5, 0x9a1bbc40, 0x554de5cc, 0xaa038f12, 0x291a368c,
8037 0xcf9cb96d, 0x30a24e28, 0xd036ed09, 0x5794fb1e, 0xdcb99383, 0xe7a35f8b,
8038 0x49643afe, 0x107b6530, 0x8c2ef253, 0x2c7da907, 0xecee5148, 0xc7a64e00,
8039 0xe87f9476, 0x5492e3f7, 0xdf58edf5, 0x11d99df7, 0x9dfb4a9c, 0xbf7e9375,
8040 0x43c62b4a, 0xdcc0597c, 0x7e4084b8, 0xb87245fe, 0xfb411e72, 0x137f62fc,
8041 0x324993d9, 0x71e037e0, 0xfc87b06c, 0x8e26757f, 0x9e1a49ef, 0x77f869d6,
8042 0x93e8107d, 0x790c1f90, 0x3efa773c, 0x1e49e1d9, 0x0599ed40, 0xa87bcbdb,
8043 0xd0f30c7d, 0x28f7ca78, 0x9d435ef4, 0x304f2041, 0xfa6b2d1d, 0xe498db84,
8044 0x7d211f31, 0xf91f0177, 0x775f8fda, 0xf52e8705, 0x6c4aa7df, 0x376ff66f,
8045 0xed29da96, 0xd86a962b, 0xffc411d7, 0x922a5f08, 0xb7377634, 0x5095df37,
8046 0x7a6d604f, 0xbb4a6b94, 0xbeefc013, 0x05ff7806, 0x27a61ff8, 0xf8e1ef81,
8047 0xc3df019f, 0xf7c06ff4, 0xf014fcb0, 0x81db4c3d, 0x97f961ef, 0x9d30f7c0,
8048 0x1b243336, 0x69aaa4e9, 0x855afb0c, 0xff873af7, 0x3189ddf9, 0xd9cbe37d,
8049 0x9ed76e24, 0xfbfbef88, 0x7c71277f, 0xdf37713a, 0xd7906eb7, 0xfe019fa8,
8050 0xdf84b2ad, 0x87776e58, 0xef9e73f0, 0xd77eb8d2, 0x5ff3c31d, 0x3fa8e926,
8051 0xc66d86bb, 0xe9a5dff6, 0xe649ef29, 0xf85ba372, 0xa8ff012f, 0xc31e657f,
8052 0x7aaa4a86, 0x814d24ee, 0xdef98fbb, 0x23c7cc9d, 0x1c3d44fc, 0x0fde31f1,
8053 0x84ad2b3f, 0xf178819f, 0x249ba085, 0x58bbc703, 0x27c8f1e4, 0xbe744ca3,
8054 0xe3b5f30a, 0xc49d7479, 0xfc3af1f1, 0xe77b70d4, 0x7e84fc3a, 0xe7804e08,
8055 0x093fa412, 0x35251fc0, 0x45b77988, 0xe082fc86, 0xa0b3a2dc, 0x3227efff,
8056 0x6bdb1600, 0x84ce8f7a, 0x10c8d8f2, 0xe41d9e2b, 0xd45e6e3d, 0xebb8ff17,
8057 0x35ff5ddf, 0xffaf547a, 0x738b75ba, 0x375d5b93, 0x97e413f1, 0xf07d3f88,
8058 0x1fc82187, 0x33f87c72, 0x849ed926, 0x264b74fd, 0xbb81fa2d, 0x022f1c4d,
8059 0x1a5dfbd7, 0x3f055fc7, 0x18fc40be, 0xbac3fd80, 0xb9eb7d12, 0x80a0ff36,
8060 0x14642df5, 0x8fb8110f, 0x5bf15f0a, 0x39c91dd7, 0x2601b83e, 0x041efc92,
8061 0x71fd1bf2, 0xc70b649e, 0x676701f3, 0x81f9426f, 0xffea0272, 0xfafdc341,
8062 0x56bedf0a, 0x2673c92e, 0x39f8a867, 0x67b07b43, 0xcbe881bf, 0xaf2561ab,
8063 0x43825da1, 0x8f59d9f9, 0xf6f5f325, 0xa0d64f4e, 0x9df5d4de, 0x27f145d9,
8064 0xa14e7b03, 0x59b5d67d, 0x6d3db8c7, 0x3c81249f, 0x057e8f9b, 0x8dc5fa2b,
8065 0xa17b6e74, 0xd43d991a, 0x853e5cf3, 0xf3d56176, 0xe8023332, 0x9dbfe7e4,
8066 0x60b2f886, 0x7a82cebf, 0x4fcdcac7, 0x3b7c461f, 0x515928d3, 0xc23577de,
8067 0x457ea1b2, 0x04db884d, 0x8f21f3f5, 0xf59a17f5, 0x8f1f2b6e, 0x18a74cf4,
8068 0x65536bef, 0xefa5fa02, 0x70475e79, 0xc783b05e, 0x79b3bc31, 0x9f639d09,
8069 0x0a2c4b71, 0xcbcbe5da, 0x9fd0635a, 0x3364a2f8, 0x39a73b40, 0xefda3cff,
8070 0xcd983b65, 0x3d8afe8b, 0xb2be7421, 0x7f1d46a0, 0xa4dee250, 0x64a27d47,
8071 0xacbcba8b, 0x9d879d4e, 0x6ceb7e21, 0x3c33c750, 0x15e22c92, 0xf270d9d2,
8072 0x9384d633, 0xd3f0a01e, 0xf631d91b, 0x324f9cc5, 0xfa244df6, 0xdffde549,
8073 0xe6697dc6, 0xdf22c9f9, 0xdf4bf901, 0xe0517df2, 0xbf9ca952, 0x4f6cb0c7,
8074 0x99dfc636, 0x55c7682c, 0xca157f36, 0xa82cee30, 0xcfa27efd, 0x538a6537,
8075 0xbb24d75a, 0x2d15be10, 0x3e3197a6, 0x31ef72af, 0xe10435bd, 0x01e908fe,
8076 0x1ad732f7, 0x1abcbfb4, 0x3c236b0d, 0x15ff236a, 0x202cf7b3, 0xc9b370bf,
8077 0x6f3de742, 0x133ada7e, 0x66257bf3, 0xdc1c7dc2, 0xe0b2784e, 0x75ce9979,
8078 0xb93e6a19, 0x71913c3e, 0x3d9f715f, 0x16bf68fd, 0x3ee3bee2, 0x3ee3bec3,
8079 0xd89fb8cb, 0xe6ef443e, 0xccedc278, 0xfef9db33, 0x2f9efb2a, 0xdf93d06f,
8080 0xf3ef96b8, 0x3fd7cf3d, 0xa078441b, 0x680f0263, 0xe16ccfdf, 0xbfdfaefb,
8081 0xf1103f5a, 0x0f0036b7, 0xf0d70d9a, 0x1d77e700, 0x7fec041e, 0x07cbf0a9,
8082 0xfee041e2, 0x44f82bdf, 0x10fa3c9e, 0xfe2cd9c6, 0xf1571f05, 0xef0ecd73,
8083 0xaa0478ac, 0x11ff1a9c, 0x392cdd9a, 0x049635fa, 0xb421bd72, 0xc0f909b0,
8084 0x86bb09f1, 0xfc099c53, 0x9c524633, 0xddefc11b, 0x053dfd5f, 0x7e3bbfe9,
8085 0xe23796f2, 0x703aff69, 0xc161dd1d, 0x96ee7e5c, 0x1b9512dc, 0x538006bc,
8086 0xa451f01e, 0x81b6f643, 0x07ba91ce, 0x31e8f43c, 0x693f77c8, 0x48f6e1b6,
8087 0x951f6e76, 0x1277bcb7, 0x31ac86fd, 0x9fb2aecf, 0x8e537d84, 0x6f7e15f6,
8088 0xefcafb00, 0x7cb24e3c, 0x4f3eed44, 0xcaf5a04e, 0xb266db1a, 0x9598ea83,
8089 0xe3af63ce, 0xbdf88cf7, 0xa1ba07e2, 0xf7c0163e, 0xeb9efc7d, 0x2835cc61,
8090 0xb14be90c, 0xb47e14b3, 0x0f4bf850, 0x1b44763d, 0x03aceb81, 0xb5bee3b8,
8091 0x8fea1f00, 0xdb9d3d7e, 0x8dd1f92a, 0xf1167fa8, 0xce78e00a, 0x469f68b5,
8092 0xd332fc46, 0x0f029d7c, 0x605f112b, 0x07d9659d, 0x775f5142, 0x6ce1fe0a,
8093 0x497f210e, 0x8f98db19, 0xe30655f8, 0x9bc0fb79, 0x487bedb2, 0xde19bfcf,
8094 0x655bfa28, 0x3fdebaa3, 0x250c9f90, 0x03f9927e, 0xfc69dfe0, 0x37c7c73b,
8095 0x7e8ce4f2, 0xcbdc0718, 0x6e90fdac, 0x52d7246f, 0xfb290337, 0x36ee9bf5,
8096 0xcfcaad32, 0x33e5516f, 0xfaaad13d, 0xaaac9ac3, 0x69bdc3ef, 0x0f23efaa,
8097 0x9cf954db, 0xfaaa51b6, 0xabb49fb7, 0x17b477f2, 0x75dfeaa8, 0xef9550ae,
8098 0xfcf580cd, 0xbdd739c8, 0xfeaa92d1, 0xd549ab78, 0x042a683f, 0x6169899f,
8099 0x335ef2aa, 0xfa8dd387, 0xeea6cfbd, 0x7f6fb157, 0xffdd4a36, 0xdfbabb64,
8100 0x6d87dd5b, 0xa0b52720, 0xb9076f6f, 0xd04ee989, 0x6fa0b5cb, 0x8e5e8037,
8101 0x2f4157f9, 0x7a03d4c7, 0x06bf9639, 0x1be6397a, 0xfcc72f41, 0x3023b03e,
8102 0x405d54df, 0x85d59be9, 0x78337e54, 0x0f718ab5, 0x888f718b, 0xc4db1971,
8103 0xe04dfee5, 0x7f68a1f2, 0xc36fb454, 0x3c3e49f6, 0xd64828ac, 0x1d3a055c,
8104 0x8f5e7e13, 0xc5f65ae7, 0xd768f9ed, 0xb32fbcf7, 0xcc2740ad, 0xdd5c3ee1,
8105 0x0452e51f, 0xec2faf3f, 0x0efd00f9, 0x2d137b95, 0xaeb06e78, 0xf8a3e3e9,
8106 0xb651abbd, 0x6c1ddd22, 0xfb142afa, 0x141578b9, 0x9e4291bc, 0x77f9de41,
8107 0xf0f5f946, 0xc7d5e31d, 0x964501ef, 0xe48794e4, 0x2524c5d4, 0x0e7ba6ef,
8108 0xf47b0d85, 0xb6fe74ed, 0xefbfbe87, 0x6fbfa9d1, 0xb77d55af, 0xf73c7d60,
8109 0xcec9bad5, 0xf4a4d0be, 0xcefaa5e7, 0xfa8ec924, 0xefed85f1, 0xb738c1ac,
8110 0x11453d8a, 0xde567e78, 0xde722c70, 0xd2ffc08f, 0xc8195dbe, 0xa19a2bd7,
8111 0xbfafb33f, 0xc89d668a, 0x933bf9f3, 0x2387e4f6, 0x18906edf, 0x6c8b928a,
8112 0x950dc523, 0x913bd537, 0xcda7952f, 0x4e39e1d4, 0xf61647b7, 0x73c38f3f,
8113 0xc7d7185a, 0xe742573c, 0xf27fbf41, 0xe31fba1c, 0xde5bba69, 0xbb71c509,
8114 0xdf869ef1, 0xc2913efe, 0x5227daf5, 0x8b87bdf8, 0x6284ef8d, 0xcf3ac5fc,
8115 0x5aee1c3b, 0xa0ffad2f, 0x4a4377c8, 0x69926ef0, 0x3557a5fd, 0x7f4a0fb4,
8116 0xd4c8a6cf, 0xe4a6f8cf, 0x71d75c10, 0x8dcf1f0f, 0xce3005c1, 0x62a2a4f8,
8117 0xe891ff9c, 0xe9323919, 0xdc6fdc75, 0x3d62643d, 0x8e7813ea, 0xf5dd97de,
8118 0x55b7e89a, 0x9fbdf7c4, 0xf22b7af4, 0x110523db, 0x880649c3, 0xb8533b7a,
8119 0x77af919d, 0x389ca124, 0x1f92b66e, 0x62414579, 0x41efee08, 0xe0bcb14c,
8120 0x97cbf265, 0x8ef1f235, 0x1142da5b, 0x8e378eef, 0x516f5194, 0x71c3abfa,
8121 0x6facf8fd, 0x4fb45cdf, 0x335aee25, 0x3fdbe3f6, 0xb14eee5e, 0xee23bb50,
8122 0x3f50d363, 0x4c169e3a, 0x9eab45fa, 0x37977b9f, 0x78f6fd70, 0xecad6c4b,
8123 0x16e15e77, 0xa69dd1fb, 0x6aed7da1, 0x337a89d2, 0x9eaa99eb, 0x9d57ef8e,
8124 0x77163e7a, 0x57a853c7, 0xe9945f3b, 0xb7538eee, 0x7fd71228, 0x7e7a8b76,
8125 0x4ece0225, 0xd232379d, 0xcd9d5f0f, 0x4cc6e8d7, 0xd0acde78, 0x53f69589,
8126 0x69e3c7d9, 0x1e3b2f5c, 0x390befcd, 0x5e13d4f7, 0x5b7de4fb, 0xb11dea3c,
8127 0x4ee3c1ff, 0x2ad7666f, 0x5d9f80fa, 0xd3aed0c4, 0x68e62415, 0x3f727c12,
8128 0x79fec52b, 0x97b400ca, 0x040ec90a, 0x3f210f64, 0xfdc3ea08, 0xedfeff90,
8129 0xb7b71c59, 0xd440f411, 0x134d8c83, 0xaf4afef0, 0xe604080d, 0xe745bbdb,
8130 0x198bf616, 0x4205d2f5, 0x756b3d2f, 0xbe78cae4, 0xeb435cb8, 0x81dd8272,
8131 0x825d8a71, 0x13da5ddf, 0x07d233ff, 0xb416cb0e, 0x70f1ee67, 0xc0d9d63d,
8132 0x4f4ad2f5, 0xa346effc, 0xb3a0ddde, 0x535a0559, 0x2fd0ac5c, 0xf5bd08ce,
8133 0x3d1ef2cc, 0x25fb27d9, 0x5ff434f6, 0xce89b4d2, 0x7e842bab, 0x90372151,
8134 0xb370b09e, 0xbd002f5a, 0xdf2f9545, 0x0837a81e, 0x5d47907f, 0x7277d8ae,
8135 0x21fd35ea, 0xd011ed1d, 0x0e90a34b, 0xdcad53a2, 0x93ec266f, 0x28b69925,
8136 0x5a75f7a4, 0x4fc504eb, 0xdaaaf080, 0xce297aff, 0xb20ceddb, 0xf4b0bd91,
8137 0xf76b824d, 0xe90edc37, 0x8f04668e, 0xdbe1c66e, 0xbbf1c4dd, 0x8db9274a,
8138 0x95d01ed8, 0xee4a33fa, 0xba87a8e5, 0x2f89437a, 0xf4805631, 0xb70678b0,
8139 0x0be8ed37, 0x850bf485, 0x29f9140e, 0x5bbfba71, 0xf9872edb, 0x54e487f1,
8140 0x138e77ae, 0x424b3b71, 0x06bf246c, 0x9d9eb91a, 0x8e19e257, 0xec1030f8,
8141 0x9f9f8368, 0x2dd9a07a, 0x52babd61, 0xe45717ee, 0x45ad64f3, 0x7e2bfd87,
8142 0x4cfce522, 0xb7895fe9, 0x16ff69bf, 0xebecdfe8, 0x0fdde01f, 0xdb257de1,
8143 0x6e39f246, 0x6d2f72b2, 0xb2a3d111, 0x6f808b9e, 0x1f451fe8, 0x739bee0a,
8144 0x7e7c81cb, 0xf746ddfe, 0xf943f2cc, 0x5c45f23c, 0x4f107e73, 0xbf72a4c7,
8145 0x0e54cacc, 0x2a9166b7, 0x549beb7c, 0xc854d8fb, 0xf23aa7b7, 0x42dca953,
8146 0xdae4b9f8, 0xa88c807d, 0xeef83ef6, 0xbdf88fe2, 0x0f402bbb, 0xbe7e7fc8,
8147 0xa926b248, 0xe78e22f4, 0xe308bc55, 0x468c4e1f, 0x6decb838, 0xce789169,
8148 0xce6be9ce, 0xc9359352, 0xec2e4fdf, 0xc4db0c2f, 0xd1529c73, 0x4a52c4be,
8149 0x4b1c15f7, 0xd7e8ad23, 0x487a42af, 0x07fe39b8, 0xdbfc3de2, 0xc956f882,
8150 0xde7e360c, 0xa6ddf81e, 0x417b3d45, 0x09c45d00, 0x4875ad3c, 0xfb598e74,
8151 0xb9fb96bd, 0xd7e44966, 0x790a107a, 0x57a8b7bc, 0xa3e28632, 0x9d2c841e,
8152 0x17f4d503, 0xe9fdafe7, 0xb101ea7c, 0xdc4507fe, 0x279d21c0, 0x8730fd1e,
8153 0xcdf9f82a, 0x73a1e60c, 0x8dac59e2, 0x95c113d2, 0xb9d4bd7b, 0xd1da306b,
8154 0xe40c3a9f, 0xb55da9ff, 0x6bf90435, 0xc1655b16, 0x93202373, 0xbc8c3fed,
8155 0x78119eb1, 0xbdc4a4be, 0x9edcfb2a, 0xf11ab85a, 0x51ec1ce0, 0xdbeb88f4,
8156 0x97b27f97, 0x1f3a69e2, 0x43da7d7d, 0x1e9bed0c, 0x5b28778a, 0xee9a3c34,
8157 0x5b58b855, 0x7f6fae5a, 0xf654fd95, 0xaaacca0f, 0x0cb5857d, 0x674cf802,
8158 0xe95eb93d, 0xc0a9fbe6, 0x33d74e39, 0xf2094115, 0xe050f88b, 0xaf702b3e,
8159 0x3dc48b64, 0x674745a0, 0x5787fd40, 0x4fa8ac69, 0x37efb75e, 0x89af1fd9,
8160 0x4886f27f, 0x68dea764, 0xfa7d94bf, 0x742fb8b9, 0x3bb78c32, 0xfc9973f9,
8161 0xfbdbff7d, 0x63aa4df5, 0x3bc92a7f, 0x1b749f4b, 0xa237a748, 0x034b39cb,
8162 0x4e8037e8, 0x0da5d1af, 0x3fdbf3fe, 0xa250d2c7, 0x9d7f6547, 0x517fb056,
8163 0xd884b5fe, 0xfdfaecdc, 0xe7163b44, 0xb128d653, 0xa15ba417, 0x7bb276d7,
8164 0x700bf703, 0xe0f28ec5, 0x553a00f3, 0x7c46f1f6, 0x277be14b, 0xbb9e5cf4,
8165 0xfce9931e, 0x7bc90bf0, 0x2c7c82c8, 0xd7dd38fd, 0xb17fea52, 0x23f06dbc,
8166 0x6317cfd0, 0xcf427a78, 0xbc94f9e3, 0xe5fb883d, 0xb83188be, 0x485ffd70,
8167 0x9e5163e9, 0xc7fd217f, 0xa51f3cfd, 0x467e62b7, 0xe40b58d4, 0x3f14e84f,
8168 0x87c10ade, 0x3c7fdcdd, 0x5471f6e3, 0x32ef624f, 0x2ff5bf7f, 0xcf5bf225,
8169 0xf38e9601, 0x5cfb1f8b, 0x9f940241, 0x70e255fa, 0xac5b5f3a, 0x62e50fee,
8170 0xb8fff93c, 0xd5f776dd, 0x86515d1e, 0xf26b9c6f, 0x5e65dc6c, 0xf64c9c5e,
8171 0xad808941, 0xdb9d3c3d, 0xcf7e6ea9, 0xbd379150, 0xfb375f87, 0x0bcf27fb,
8172 0x7cb5ee7f, 0xfe7193fa, 0xb6c0eaf2, 0x9fb05227, 0x0b2bbd12, 0xab9f1bef,
8173 0xca1c43fd, 0x8f6d92f5, 0xb99e90a7, 0xda0a5d6d, 0x9f5b250b, 0x3e53b148,
8174 0x8af641d8, 0x73bbaf96, 0xaf2f1df7, 0xeb6bd3f7, 0x3f9eb9d3, 0x0f2078cb,
8175 0x4309cdf5, 0x3f46ad2f, 0x24aff278, 0xd6f44c8b, 0xe0e51ab6, 0xef8e34ec,
8176 0x7c48c6ac, 0xa2fde199, 0xbefed8fe, 0x47c7e43a, 0x15d2bed2, 0x34ecbd43,
8177 0x3663c12d, 0x82886f73, 0x64ad6cef, 0xf5fe67a9, 0x6139d307, 0x1f492ad1,
8178 0x5be51fdd, 0xe3b470d8, 0x68c2d3b2, 0x0ed7731e, 0xd9f2c56f, 0x04f978cb,
8179 0x38f1bb83, 0x9e9cf3f6, 0x804067e2, 0x9bc7f825, 0x3b71a767, 0x8906ce6a,
8180 0x9c656bf4, 0x6b2367e4, 0x9d99d7fd, 0x39f3e426, 0xe521f137, 0x65a4db1e,
8181 0x868ddec7, 0x1d6a0f7e, 0xf7c1a677, 0x499ccfa3, 0x2e333e42, 0xda067cfc,
8182 0xc77ac919, 0xeeb8a50b, 0xcb8a06ad, 0x958aceca, 0x88fea0a3, 0x8d3cc747,
8183 0x45659ce9, 0x3fa2942f, 0x3871b375, 0xf3e56f0f, 0x35592c5b, 0x53be3f68,
8184 0x845cd0fb, 0x8c67b9db, 0xae2f1fa4, 0x3f628d4d, 0x02bfef62, 0x614d6ffb,
8185 0xfbd8076c, 0x7b02ee98, 0xed4bef1f, 0xfca68eae, 0x94adab1f, 0xbf1ce9b2,
8186 0x1f385b16, 0x237f51b9, 0x02b78ec1, 0x0b5ec91f, 0x78fe81fd, 0x107f6f46,
8187 0xa43c99d7, 0xb13aeb62, 0x3f6864ae, 0x0f7f15dc, 0xdd7b21c2, 0x5aa8ad23,
8188 0xe7e3498e, 0x5f1c1f7a, 0xf1fa471b, 0x4a978eb2, 0xb486fbe1, 0xded8d9c2,
8189 0xd932e5b8, 0x3f34efef, 0x5de11b3e, 0xd7c0d5b2, 0xee7dd627, 0x17a89499,
8190 0xfbd77fa0, 0xaba7b23a, 0xb4bc74b6, 0x1b79d20e, 0xe3fbd11e, 0x77aeadfb,
8191 0xcdcf9896, 0x7046eae8, 0xd5d39ff8, 0x3f447113, 0x32ae815b, 0xaaba75fe,
8192 0xe09cb65a, 0xe15a5af7, 0x9fc834ea, 0x90e2b9d3, 0xffa5ce9e, 0xb5dcf084,
8193 0x2bf8225f, 0xbf6955fc, 0x9bdb8d32, 0x06cf1ae5, 0x7f04efd2, 0x3a2c16fd,
8194 0xe681ef84, 0xdfa829b3, 0xe334db7e, 0xafbdd747, 0xd233bf9a, 0x7ff5f004,
8195 0x734942c7, 0x1b448ef5, 0xc4572fac, 0xdf7e07dd, 0xce51a69d, 0xe05e48f1,
8196 0xae2fc93f, 0xd62602a2, 0x92e51c2f, 0x7b420de4, 0xf3dee9aa, 0x379450da,
8197 0xad52fb12, 0xfd2fb21f, 0xe68dede4, 0x12b4b37b, 0xf8fad1fb, 0x3527edee,
8198 0xee43f7aa, 0xbd520f68, 0x8ecd71c7, 0x9d3d3280, 0x2ad4c4a3, 0xbf18f6f1,
8199 0x4e9cd5d3, 0xc5e7fdf1, 0x7daea27d, 0x3f712f60, 0xdefd9309, 0xdcdf3835,
8200 0x367c8599, 0x6f95bd70, 0x387e1276, 0x4cbf1e9b, 0xf8d364f6, 0x9bacdaf3,
8201 0xb6c0ffaf, 0xe2677a4e, 0x173daebc, 0x7d2ea2ed, 0x43ee167b, 0x9f9c5be5,
8202 0xa0e14fff, 0xd5ae9794, 0x649dbf73, 0x4f2efb21, 0x79f648be, 0x9f6e61d7,
8203 0x4cbf3657, 0x85b7b4fc, 0x34aa47fb, 0xe851f96d, 0xd1d4584f, 0x37acfc8a,
8204 0x954bdb9a, 0xe8ff9ee2, 0xb5072144, 0xff78713d, 0x9f3892e0, 0x7c34ec55,
8205 0xb5e90037, 0x5271e34a, 0x305650dc, 0x0b8f73c3, 0x3e50cf48, 0x1afc697b,
8206 0xee73f3c4, 0x3f902301, 0x8ff5907e, 0xfda7f24a, 0x9322d829, 0xe2ab297e,
8207 0xc3adaf9a, 0x14c0f32d, 0xc1abe8a6, 0x2adef8aa, 0x6467f5bd, 0xe7e11eef,
8208 0x3843555e, 0x3937b13d, 0x3aac553d, 0xebf68fa0, 0x9e82afef, 0xc26f3d14,
8209 0x7441fe9f, 0xfb64cff9, 0xa33f217f, 0x5fd86ffb, 0x24b73f74, 0xbeb97a89,
8210 0x8b733e73, 0x640bafb0, 0x24d55efa, 0x62ef3c33, 0x1e7421d1, 0x5236c05f,
8211 0xe604e09c, 0xb17a4d19, 0x7c29fdb6, 0x9fe26587, 0x371891e4, 0x9d2e7a05,
8212 0x3907e71b, 0xe8ae3092, 0x70124684, 0xf64f64f5, 0xe9396793, 0x968d4e5c,
8213 0x3d639225, 0xa7a4c131, 0x315e9f8c, 0xfa7f5fcb, 0x4fedc487, 0x26f487e8,
8214 0xf7e1eee6, 0x593dbc40, 0x4c64effe, 0x22f053fb, 0x93cc8b92, 0x9c6fcd3d,
8215 0xa71e74fc, 0x9dcf0571, 0x89549f81, 0xf93ccdf3, 0x0ed167fb, 0x9f9fbc5a,
8216 0xc4d09deb, 0xc9714a7f, 0xc258af78, 0x1efcbbfb, 0xbb307337, 0x7327e91d,
8217 0xa95fdd00, 0x8c312dda, 0x366cab2f, 0x4d7f456c, 0x123daea5, 0xd35d79f1,
8218 0xe7c47a27, 0xccef3c2a, 0xb97ff7e4, 0xf742daff, 0x8c2cabb9, 0x534557e4,
8219 0x47e8a7ea, 0xa5cc38ab, 0x18f68568, 0xb7c8e9d9, 0xc6f2bc71, 0x3b97643d,
8220 0x72ec9799, 0x6f1a8367, 0xf6fba37a, 0x5ba7e7a3, 0x8c62ef55, 0x63e9ccdf,
8221 0x9ac3c61a, 0x43f939a9, 0xd54747c7, 0xc9bbdffa, 0xb5f0e74f, 0x51ab9dcb,
8222 0x904ee98f, 0x4a8ef86c, 0x156b9077, 0x14ae47ea, 0xbf74d7ae, 0x017b2bbd,
8223 0xf67717f1, 0x077c4cd4, 0xe3b1eb86, 0xcad26ed7, 0xdf19f37e, 0xdd7ffdc2,
8224 0x1f64ac41, 0x1063bbed, 0x29fdc7ee, 0x39e90585, 0xd1cc7ef4, 0x234fd0bb,
8225 0xae04e9ee, 0x9f0a68e3, 0xdff411cf, 0x3de6f864, 0xf3963631, 0x3c26e633,
8226 0x62f7156a, 0xa516f894, 0x578116fd, 0x8917ecd7, 0xc46e9dfb, 0x04bcf05f,
8227 0xbcf132e3, 0x229dd304, 0x4bcf137e, 0x88aaff30, 0x12f3c4df, 0x12f3c72c,
8228 0xf88a37cc, 0xc12f3c4d, 0x60979e3c, 0xdf88a6fa, 0xa553823c, 0x1ae6b3b8,
8229 0xa4568bc4, 0xfcbe81b5, 0xfc80f089, 0x13fd7540, 0x3f3a92e1, 0x8bfaa250,
8230 0x5c6b9bd2, 0xb4a7e819, 0xfdc57908, 0x1d83eb94, 0x2af840bf, 0x15cf0ef7,
8231 0xe90fbd3c, 0x8cf85c68, 0xbd5f4859, 0xf90c0dfd, 0xc774aed0, 0xf877ac32,
8232 0x9b493df0, 0xe89a3f88, 0xc3c4f8fc, 0x05f75543, 0x5c8da4c7, 0x31f90d95,
8233 0x6bdc4966, 0x50ac38de, 0x5cf0fbb1, 0x5b28a5bc, 0x0582f9cb, 0xd93ce4f5,
8234 0x2ce38c59, 0x448d318e, 0xd53c3bfe, 0x1fba78f1, 0xb81fcebf, 0xa1f50930,
8235 0x53f59d56, 0x3eba97f4, 0x9bb431d2, 0x529abf14, 0xe63a90cf, 0x3e376c19,
8236 0x08d5712d, 0x0c881fec, 0xcf5d9cf9, 0x767e701a, 0xdfc4b04d, 0x916ab08d,
8237 0xf6233c0f, 0xeb95ac7b, 0x55bd5ec5, 0x76768e1b, 0x78fe98d0, 0xf62ada7e,
8238 0xdfd8b0f7, 0xf17f6223, 0x969c69bc, 0x8a61379f, 0x2a984de7, 0xd2c75a71,
8239 0x274a5f0a, 0x21c4f6f8, 0xddbf157c, 0x1a3ee504, 0x9ea1c4f3, 0xd7c099f0,
8240 0x919f0407, 0x79eb0ad2, 0x2fdd0f3b, 0xb4fe172c, 0xa0be714e, 0xe76953ac,
8241 0x9dc7cf6b, 0x67f38c32, 0x13dc4fd6, 0x185cc41b, 0x8de53af7, 0x7507f218,
8242 0xce3df9b9, 0xc8db4029, 0xfc1bd8bf, 0x73459dfc, 0x7af2993a, 0x295bd514,
8243 0xe1159afc, 0x0718296d, 0x49e825df, 0x76f72bc9, 0xde40462b, 0xafab8bec,
8244 0x8296d298, 0x925df571, 0x54788349, 0x3f7f95b1, 0x22ade82e, 0xbca7f441,
8245 0xc4f46087, 0xef743ee1, 0xef0e237f, 0x7b37ad89, 0xef7e7017, 0x98f2f7e5,
8246 0x84e30537, 0x29cf253a, 0xdfad878c, 0x8c41f939, 0x79d4ed87, 0x8efcc25e,
8247 0xc41f539d, 0x694ed878, 0xff8b29cf, 0x389e01f7, 0xdfad978c, 0xf7e44539,
8248 0xf36614bc, 0x3b5eebcb, 0x2bf5df85, 0xf1883ea6, 0xee0d13b3, 0x2f88d5c3,
8249 0x6578e47f, 0x0cf7bdda, 0x99bca7c2, 0x7763ebeb, 0x1af8bdef, 0x21bde3ca,
8250 0x55ff6e74, 0x7bc13c7a, 0x1b2bf365, 0xf6bacf10, 0xd60e88e8, 0xd2f27c37,
8251 0x819ea9af, 0x689b2b9e, 0x6ba364f0, 0x979dd5e4, 0x2771c01f, 0xc1be7b06,
8252 0xcc869ffc, 0x8c4c79a6, 0xeefc74e0, 0x3107a290, 0xef6bbd9e, 0xee90c7ee,
8253 0xfc63f626, 0x132ef5de, 0xebd94fed, 0xaed0e3e9, 0x9b690aef, 0xee57fd8d,
8254 0xfdf3f034, 0xbde8a3d7, 0xee749e88, 0xb21d2e6f, 0xabe50e31, 0xdb1dcde6,
8255 0xc67e8d7e, 0x6f3a269d, 0xfae70aa9, 0x9b5c995d, 0xdfed08fb, 0x80fedbcb,
8256 0xa261def3, 0xf452cff3, 0x74be40ad, 0x17bf325b, 0x66afcffe, 0xc9e43ee3,
8257 0xca7ee85b, 0x0d267537, 0xdeb8e1c2, 0x83ef0fde, 0xc8eb8eb8, 0xf9152cce,
8258 0x7c1113d2, 0xf9edc13e, 0x37fd7fb4, 0x2d7ca1c6, 0xfde5f88b, 0xf289ef38,
8259 0xced097c6, 0xf7f0af61, 0x00efcecd, 0xf3bb41b8, 0x0e8a3af5, 0x4211daed,
8260 0xa53bb6f7, 0xddf1b38d, 0xaf3d570c, 0x48da69d7, 0xa7d574f0, 0x76bdf7f2,
8261 0xb0c3a740, 0xf95526de, 0xb257faf9, 0xb0bd0ed0, 0xa3d92273, 0xf42b9e0a,
8262 0x78175652, 0xafdf8c2f, 0x337f132c, 0xfd998b8b, 0xf6174afc, 0x02f5df3d,
8263 0xd0bfb5f3, 0xc8fba3a0, 0x0ab606a5, 0x7a1571e3, 0xb7bd8b28, 0xa657d700,
8264 0x7d414da9, 0xfb6474a5, 0xf38ba46c, 0x868c6626, 0x39081f7a, 0x7cb8d655,
8265 0x37bdea32, 0x431dcf9a, 0x56fa1f38, 0x4db7e1d0, 0x79ffb726, 0xb7fa605f,
8266 0x50fd666a, 0x7cffcbeb, 0xdc9efa91, 0x138f7a07, 0x70cab3ed, 0x414e3fce,
8267 0x5fe006fd, 0xfce10fb7, 0x7552ce62, 0x3c218cfd, 0xdf52b10e, 0x4ef2829e,
8268 0x887d3fe9, 0xda83eb85, 0x2a277a76, 0x5944ddb0, 0xfc5d9bf0, 0xa35969de,
8269 0x1df741d4, 0x3e91a410, 0x5d199678, 0xe9d38c6e, 0x73a21f6b, 0xbde03ec5,
8270 0x34f12182, 0x8983595e, 0x07972dee, 0x7ea287b5, 0x0f690ce4, 0xeba7bd45,
8271 0x8bde994d, 0xafebedc4, 0x1be09ff4, 0x9617f14f, 0x5376747a, 0x72c1e35f,
8272 0x885e2ed0, 0x3e28037f, 0xeb40921b, 0xe60a692e, 0xed2da4f7, 0xf0386f74,
8273 0xd3ae211e, 0x5d8f47e2, 0xfa472f4d, 0x87b3e7db, 0x57ff0bc4, 0xf74dd107,
8274 0x438cbf3f, 0xb0d3283c, 0x785e7855, 0x15f7e241, 0x15f74f20, 0xc773882e,
8275 0x41ccefb2, 0xbe173f88, 0x771d1275, 0xe7c4ed49, 0x88aabbcc, 0xdae9743f,
8276 0x4349cf89, 0xae7c417f, 0x367dac2b, 0xd0f32df2, 0x4c7bfc35, 0x4fbc6cfb,
8277 0xc8886173, 0xf724660f, 0x40daee07, 0xcca264fc, 0xcbd818e3, 0x0bf70b3a,
8278 0x142f7871, 0xed6c6270, 0x3bb26a89, 0x8fd45674, 0x424a8762, 0xd6fbd7ff,
8279 0xa9e8fb2f, 0x3777598b, 0xf0967d22, 0x9f406277, 0xf50d786a, 0xf49119be,
8280 0xdc204dce, 0xfebe7394, 0x805f7fe1, 0x710a64fb, 0xe7821cac, 0x64ed19d5,
8281 0x93b60057, 0xb6f95efe, 0x6ecbec81, 0xe436cf5d, 0xc7661d5f, 0xa9cf58e3,
8282 0x2d935b6f, 0xf6fa7de1, 0x9bdf3c56, 0x7be3dca0, 0x575be385, 0x9efccbc6,
8283 0x7c273882, 0xbe03ec4e, 0xf88b5881, 0x7e7df121, 0x0ff5e9a7, 0xb574df91,
8284 0x0e9f1225, 0x4df3a7a4, 0x0a7bd34f, 0xbbae4127, 0x93ffecfc, 0x79d0af45,
8285 0xc38c74fc, 0x3f7f5f30, 0xa9fbf7b5, 0x0db20764, 0x8f88e57e, 0x207cea35,
8286 0xbd2f105c, 0x11703a2a, 0x5ba78fdc, 0x63a3bbf8, 0x821de8db, 0x9029f96b,
8287 0x07f2fd97, 0xf501f203, 0xea3b5ef1, 0x2f51c70f, 0xf60e3840, 0x7dbb209e,
8288 0x5d938f37, 0xf28d7209, 0x9ce9837b, 0xe41bb358, 0xb72e7f56, 0x87945e50,
8289 0xaabf91b6, 0xce81af6b, 0x9f345637, 0x03f5c38d, 0xa65f923e, 0x488df9bc,
8290 0x12bfe7b4, 0xc7c80376, 0xd94b8a48, 0xf6891cdb, 0xd4ee5287, 0x7c445278,
8291 0x0ff2167c, 0xf642bca5, 0x553dd0a6, 0x39de8da9, 0x4de70af8, 0x632f21f5,
8292 0x9c3ad19e, 0xd67ba712, 0x0a6bdfcc, 0x8213b7dc, 0xa07f019f, 0xbc572777,
8293 0x0a05fdc9, 0x7c15283f, 0x679620e5, 0x28b7fa70, 0xde7843e7, 0x07df7483,
8294 0xe140789f, 0xf9116c7b, 0xb10f8e73, 0xf68ab872, 0x37f72fd4, 0xb7b8b8f1,
8295 0x3212b33a, 0xdaf59db0, 0xfc6b8f7d, 0x5fc7d128, 0x13440f90, 0x8ba1581f,
8296 0xbd957584, 0x3abbd124, 0xe796b3a5, 0x50b67543, 0xe7bd08fb, 0xae718259,
8297 0x15e7ebe6, 0x43154788, 0x34ca9c38, 0xdb2eeedc, 0xcf39d126, 0x3f3f1d05,
8298 0x71437e03, 0x2dc70bf4, 0x9bfa47cf, 0xef42bfdf, 0xacdf1f6f, 0x5beeebff,
8299 0x1f9e5a2f, 0x979d07d5, 0x3ad4dd2d, 0x5fdf5d80, 0x3f36a3a9, 0xb97d7ad2,
8300 0x260bef32, 0x75639e65, 0x31e1fc03, 0xbe3e797d, 0xf8d0b8fb, 0xaf83c2af,
8301 0xc1b342fb, 0xe017728b, 0x77b5e74b, 0xf2a45d5f, 0xbfacdeab, 0x73a6e652,
8302 0x3fcd1b8f, 0xde4a7530, 0x0ad71413, 0x744f55f4, 0x37e37406, 0x024363de,
8303 0x452511fc, 0x157bd1b7, 0xfcdba28e, 0x298111fd, 0x1a81ca30, 0x5170d98a,
8304 0xdb38740a, 0x943c07d6, 0xb94389fa, 0x8131f55f, 0x962703c7, 0x231aff3f,
8305 0xe86d8e3f, 0xc7df1b80, 0xfff043b8, 0x718fbe5b, 0xb7af304f, 0x574164df,
8306 0xbffef74b, 0x7bb83f93, 0x3f3a79b5, 0x18b33067, 0x9d1adef8, 0xefdfd5b9,
8307 0xb7b889fb, 0xe996f780, 0xee9a79fe, 0x1949fdc7, 0x49fcd721, 0x04646fa4,
8308 0x574af9d3, 0x6f9215d3, 0x16392ddd, 0x6ae9073c, 0xde919b73, 0x5ff9feaa,
8309 0xbb872891, 0xb8a6be5a, 0xcfefaeb0, 0x3ad8bc52, 0xb077b711, 0xb55bc449,
8310 0xbcb04359, 0x7cabe0bb, 0xa45eb7ac, 0xf7027f3e, 0xe2a92ba7, 0x9f7bf02f,
8311 0x1cd0d667, 0xdd6b3f7c, 0x3e30d953, 0x45cc6e33, 0x7376007e, 0x9f0dca38,
8312 0xf51ac11f, 0xe88bf163, 0x72d24847, 0xe8a6023f, 0xe24a4847, 0xa3cc047e,
8313 0xf453011f, 0xfa396023, 0x7e8f3011, 0x1fa3cc04, 0x47e8f301, 0x08fd14c0,
8314 0xb88dfe58, 0x8c0dd12f, 0xcd39fb8b, 0x6097f7c4, 0x6fc030fc, 0x78bf7889,
8315 0x777f3d49, 0xa04bef07, 0x7e2ebbfc, 0xcfc451a6, 0xf9d13678, 0xd95ed55f,
8316 0xf7845b86, 0x18295c2a, 0x0873d347, 0x7b553ffd, 0x2b72db24, 0x79a74f96,
8317 0xf9c96bac, 0xd7961674, 0x5ef86ceb, 0xdf13e016, 0xe2895acf, 0xea5aca98,
8318 0x2e355fc9, 0xcdc53f6a, 0x0c483557, 0x0cd3acfd, 0x90ae4edc, 0x9d0474a1,
8319 0x5d1e9297, 0xfb236861, 0x64bb7ca5, 0x5c9fbff5, 0xf132ea35, 0x78dce509,
8320 0x2ac4ff01, 0xb16b263c, 0x79dace4a, 0x69fe13fc, 0x9137c5f5, 0x17a7e21e,
8321 0x64f3c02d, 0xa7bf972c, 0x60151b7b, 0x374846e0, 0x6b2a7f8f, 0xe306b3d9,
8322 0x0e356ea6, 0xe2a1e5ea, 0xbf3878fc, 0x4cf0518f, 0x30bdeef1, 0x0346ef5e,
8323 0xd2bb29e9, 0xbf113b1d, 0xe4ece90e, 0xdfb4396f, 0xe9d67644, 0x7f2aa94d,
8324 0x883c9e4b, 0x758b1dfc, 0xe1efc912, 0xb60f0ea9, 0x1e60a7bb, 0x89ee59f9,
8325 0x563a210e, 0x5a90d0f0, 0x81f21af8, 0xf25699c5, 0xd819e56f, 0x113fa82f,
8326 0x53eca557, 0xde894ade, 0x36622e4d, 0xc7305fba, 0x5389dfce, 0xc39b75de,
8327 0x82839c78, 0x49378b57, 0x364eddfc, 0x5b3ce088, 0xcb4e73c0, 0xc74ef47b,
8328 0x5778833c, 0xbfcfc34e, 0x78f3d763, 0xc2f8f986, 0x8177be11, 0x7c9327d8,
8329 0xca1dbb7d, 0xe283c11d, 0x8d6f7eb8, 0x8e8bfec2, 0x373e28e8, 0x14beea2f,
8330 0x71f9c907, 0x7920c714, 0x0c3fca67, 0xa9fe31fd, 0xa438638e, 0xeb841c2b,
8331 0x253c456e, 0xd2838eff, 0x9425d523, 0x251c7e2a, 0xff7bb06e, 0xfc707b1b,
8332 0x6efe2abc, 0xc5ef0dec, 0x3f7df505, 0xf027b94c, 0x0e29c619, 0x1f1ff5c0,
8333 0xc4dbef89, 0xe1b6677e, 0xf6a2f3fa, 0x44aabdd3, 0x933fffd1, 0xfee0cf0b,
8334 0x0b9943d8, 0xcc39e1db, 0x3e678046, 0x3f42402e, 0xf78ec7b9, 0x4bf67a53,
8335 0xbe5f8a16, 0x5a6e6f8e, 0x5521f18d, 0x6bbd1249, 0x31b41f9d, 0xcffa122f,
8336 0x21b7884f, 0xe26aaedf, 0x482ed67e, 0xe5dfbef9, 0x18aaf7a6, 0x826a3f7f,
8337 0x53fbb7d8, 0x3a1f7f1c, 0x513e57c0, 0xcb7755d0, 0x7bb71e15, 0x1d6c3f73,
8338 0xf8c73fbd, 0x0ff41f7b, 0xe87135e6, 0x2ac7f260, 0x10dbd378, 0x26f115b5,
8339 0x9bb78324, 0x0e98eb35, 0xcd2906f5, 0xfc80cc61, 0xabcbe2ec, 0x7d9d6923,
8340 0xf894c5fb, 0x98bf40f6, 0xbffd7f3f, 0xb0ff6b88, 0x47a5117a, 0xda5297ab,
8341 0xefa2ed56, 0xcb6e1720, 0x6a7f35b8, 0xfe1f464a, 0xf6b46654, 0xf40ab923,
8342 0x01d6fdcd, 0x6ba053fe, 0xdf5d1f8d, 0x773612d3, 0x351dea2d, 0x128f7a7a,
8343 0x98978ce3, 0x32d80f89, 0x2aa3f4fa, 0xdf933370, 0x469997b5, 0xa6c7fc20,
8344 0xf0356a25, 0x490ccefd, 0x74865e75, 0x3a43eb82, 0x44e914c1, 0x7cefe7eb,
8345 0x9c240f51, 0x1700f5cd, 0xda2601e9, 0x81cb35d7, 0xeef8487f, 0x3fc5458f,
8346 0x0ff0062e, 0xa61e5830, 0x062d55fb, 0x8946877a, 0xc90b1cb7, 0xf07d11d5,
8347 0x27e70f13, 0x3b3c8383, 0x657fbee8, 0x1ef3c510, 0x3afc71d2, 0xc9c78eb4,
8348 0xfe42b315, 0x7cf5d0de, 0xcccbee85, 0xf539e88b, 0xef3fa807, 0x33e93309,
8349 0xe416626b, 0x257c3bfe, 0xe0106507, 0x4b2c6b9d, 0x9be0b8c3, 0x03bbcaa5,
8350 0xd021ded7, 0x271cf78b, 0xaa6a77f0, 0x5953fe84, 0x54fa216c, 0x6a5661ee,
8351 0xb06b1d3d, 0x1e10ff5e, 0xf465a1ef, 0xcd71c8ce, 0xa9eefe40, 0x13e3b3a0,
8352 0x1b9fc912, 0xc5e3d2b9, 0x93ee7b7e, 0x71da7de8, 0x831dfcc1, 0xf3a14d3c,
8353 0xaefef815, 0x7d47df86, 0x9029df11, 0x5fb95f71, 0x93ef77c4, 0x05b169eb,
8354 0x7fb95b21, 0xb3fbbf98, 0x00fe1252, 0xb74b6ef1, 0x1fdde03b, 0x374aeef1,
8355 0x08f59c2b, 0xcae981f2, 0x27d68ffb, 0xa6a07cf1, 0xf7788874, 0xcf7fe387,
8356 0xf90da364, 0x3e70cd59, 0x04d29aff, 0xac948fee, 0xb98e51cb, 0x1c68c37e,
8357 0x833fbbdf, 0x1fb2bbe9, 0xa72e3bca, 0x43bf1c43, 0x9ef811be, 0xe152b3cb,
8358 0x4fd8f98c, 0x27af9f26, 0x43e3f399, 0xb93c8633, 0xc838e10d, 0xf87a839a,
8359 0xb96151dc, 0xac47e012, 0x800cb996, 0xa69be87f, 0x69d66e77, 0xbc602bdd,
8360 0x2f715a41, 0x3df82b5f, 0x82341974, 0x90f5dbea, 0x217a7a2f, 0x8abca3b3,
8361 0x6c5ef465, 0x879f9192, 0x29863b43, 0x946469ba, 0x85fb8c83, 0xfef1fa8a,
8362 0x7b98a28b, 0xd9fd4485, 0x673c4a35, 0x020efe2e, 0xb6173f23, 0xed411d0f,
8363 0xdede1a5d, 0xb6f485ae, 0x51defe44, 0x9d036acf, 0x3e3d1683, 0xa4e3e498,
8364 0xedfbeab1, 0x38f067df, 0x985d2505, 0xf9d15569, 0x74e955dc, 0xd577389e,
8365 0x43d40a8c, 0x74c10d1c, 0x81f3af1f, 0x9df0bb97, 0xbdd972f1, 0x6bb413e0,
8366 0x216f1d32, 0x5920b95f, 0x0a85ef67, 0x477c1f73, 0x0e31718f, 0x6f4be4cf,
8367 0xed70dca2, 0xbaef8a39, 0x4c80ffdd, 0xfc67efed, 0x8ab6647d, 0x9f7903bf,
8368 0x1a36b2eb, 0xb46fbffa, 0x0ef27e44, 0xf50e2593, 0x5fb122ba, 0x14ff82ad,
8369 0x829c19ad, 0x787df576, 0x9c87dece, 0x3d793291, 0xf76dfbe5, 0x635d9530,
8370 0x990ddf10, 0x25b7bd7c, 0x6bc5eff2, 0xa1891d0d, 0xa9bcea98, 0x8d86da90,
8371 0x65f118fd, 0xdfcb0252, 0x25fc708c, 0x987633f7, 0x97ce9798, 0xae0933eb,
8372 0xf1d3d60e, 0x6ea3ae38, 0x63a3ad28, 0xde8e258c, 0x8aef10bf, 0xfe70b7ce,
8373 0x8f8631d4, 0x1ed2ca73, 0xe9c19e12, 0x9d17df07, 0xebf4b627, 0xba9f2ba5,
8374 0x5bcdea1d, 0x927ba466, 0x4a999ff3, 0x1abcca76, 0xb247ee99, 0x45f7ea0d,
8375 0xe2749e41, 0x0bdf02fc, 0x14177c0d, 0xa0f11cf7, 0x78448378, 0x9b4adb74,
8376 0x7bdfcf1e, 0x009e8136, 0xdecd8bdf, 0x8a0bd424, 0x0adb266d, 0x43778fa9,
8377 0xe5b807bf, 0x8ccbbbe2, 0x592126fc, 0x6e38ab8e, 0x7a22c6d1, 0xc33833a7,
8378 0xdbb0fe41, 0xfd441ec0, 0x4e4c8ee7, 0xbc00933f, 0xb683cef4, 0x9fed063d,
8379 0xaf1c193d, 0x525b8526, 0x269784cc, 0x3bbbf786, 0x9c149674, 0x936ac75f,
8380 0x499ef506, 0x027e382b, 0x23b518dd, 0x059fbe30, 0x111efd21, 0xd72d67ed,
8381 0x7e42d616, 0x90ed8810, 0xe19bc470, 0x0e8f9f84, 0xf119fc73, 0xd86fdcef,
8382 0xf39fe428, 0xf3e26c36, 0xb4cffb12, 0x9ef0e36d, 0xf8fab9e5, 0xa0571811,
8383 0xc3a3c3e0, 0xfd325ac6, 0x8901e0f1, 0x73d61ff6, 0x6d8de518, 0xccc8dcd8,
8384 0x007e5401, 0x58d263f1, 0xe421c52f, 0xe7864ec9, 0x8cd1bdf8, 0x197be9e2,
8385 0xb5ded7a7, 0x0a6fe25a, 0x01f8509f, 0xef1d83e0, 0xadfb2ac7, 0x2bff85f0,
8386 0x43e0043d, 0x1be1457c, 0xf0517f0a, 0x8133e14b, 0xc01b3578, 0x6a08f77c,
8387 0xe14cfc4f, 0xcd0eb863, 0x517f1f08, 0x76b759f6, 0xadfc868c, 0xe4f39f62,
8388 0x40dfbb8b, 0x49989438, 0x1706b96f, 0x12e091b3, 0xf84d67a7, 0x47caea3e,
8389 0x402cf70a, 0x416dfc7c, 0x331fea3c, 0x18f7d44b, 0x7d48be7f, 0x52ce717f,
8390 0x59c5fdf5, 0x843e3f4b, 0x5086a77e, 0xbfdc04c7, 0xf33dbf53, 0xfe50a7e2,
8391 0x90bdbf9f, 0x8becedcc, 0xb8e1cff5, 0x3cc482cb, 0x96bcf9da, 0xdcbe49e9,
8392 0xfc30f426, 0x9732fb87, 0x8a2d3a71, 0xf28a3b0f, 0x29c22e6f, 0x611fdf0b,
8393 0x89bfcf04, 0xf62539fd, 0xf73568a7, 0x24b8743b, 0x5dcc43f2, 0xad74e825,
8394 0x97f25efa, 0x383dac31, 0xf97f77d1, 0xc4a4dfcb, 0xf72b5d21, 0xf96b1d95,
8395 0xe969667d, 0x1c5fd261, 0xae50fbca, 0x96a1f780, 0xcf7bf2b6, 0xc4fbeaed,
8396 0x3d76d9c1, 0xb71829f9, 0x1da6e6a3, 0x1b35f1e4, 0xb28a0b25, 0xbc5e5162,
8397 0x57dd5256, 0xdf93247b, 0xd0cc6b17, 0xfa0bbf72, 0x1f38949c, 0x7c04be3f,
8398 0x15cfee83, 0x5fae1c6f, 0xe747c7e0, 0x6979f28a, 0xf2954a1a, 0x571e0cc6,
8399 0x03448c1a, 0x4b4faefd, 0x7e27cfd0, 0xa8bf2567, 0xda6e7f52, 0x37e83588,
8400 0x7f01bb98, 0xfed7c79d, 0x6a5a9937, 0x26f428df, 0xfcf80de7, 0xfc2a38b5,
8401 0x379a0ef3, 0xaf65d3d9, 0xdf157aee, 0xdcfb2fbd, 0x6ca67240, 0xcf5f3898,
8402 0xa54ee770, 0x9f7e63f3, 0xf7ec52aa, 0x845f5db8, 0xd5509da2, 0x8671dfc8,
8403 0xcad303b4, 0xef642565, 0x1e80da57, 0xf78fafc2, 0xcfd5f77e, 0xd95fb943,
8404 0x9f41ab15, 0xa59df888, 0xc8afc6ca, 0xdefca0ef, 0x2abb6052, 0x6e50fbe9,
8405 0xff985abf, 0xede411ef, 0x549d11d7, 0xb97b7335, 0xf215ef6a, 0x5fed579b,
8406 0x63e8e91d, 0x13dfd7fd, 0xe8e2abb1, 0xcb86d8ab, 0x06fe0f74, 0x4c9eeaf1,
8407 0xedc3eef1, 0x538a76ec, 0x2b8a32d7, 0x2ebbf6ba, 0x8d1fe4ee, 0xacdaac8f,
8408 0x5ea078a1, 0x9e1fb5ad, 0xfb8b75c7, 0xbef58151, 0xd776e4cd, 0x7c23a025,
8409 0x41bba377, 0xee9df3a6, 0xabbfee06, 0x15ba786c, 0x8256a5ef, 0x5ec30ce1,
8410 0xd9543fbb, 0x7fa33328, 0x1fc61adc, 0x9e78dc45, 0xe842bbe5, 0x8f52981d,
8411 0xf987af64, 0x34bd82f4, 0xc73e6fc0, 0x1b955e05, 0x2fb4b93c, 0x0387fe62,
8412 0x96d29df4, 0x2b9ee9a7, 0xfd22ebd4, 0x8cc18fe4, 0x1cf5939f, 0x6e7679c5,
8413 0x5ae74919, 0x953d9ea5, 0x086c77e4, 0x0b9578a6, 0xe9bdf53a, 0x53bc6253,
8414 0xafee3c99, 0xb124e313, 0xe932abfd, 0xa44f38a7, 0x3a920bc7, 0x68b4e38e,
8415 0x6dc05a77, 0xa54ba09d, 0x23a7a97e, 0x9fea0934, 0xd298fa6d, 0xd4bf512e,
8416 0x728596dc, 0x30636cf3, 0xdb3d63dd, 0xb7fc87f8, 0x9e4bbc60, 0x3f25fd31,
8417 0x74b292fa, 0x88b63f7c, 0x08eeb8fb, 0x43c4cf71, 0x886ce9eb, 0xacbed095,
8418 0x9d5ef110, 0x6a87af8d, 0xff5d7e88, 0x4d5defde, 0xb15deebf, 0xfea046ef,
8419 0xbd576c62, 0xd5bff62b, 0xff28a57f, 0xe3142a44, 0xb9c5e8f4, 0x101dff30,
8420 0xe13ba08b, 0xcc3d9d8f, 0x7fde10fa, 0xdff01f65, 0xffbd030d, 0x668fb439,
8421 0xec8239ff, 0x0ffdfc4f, 0x21f37fcc, 0x3d9b2f3f, 0xe895f052, 0xd7f41cf6,
8422 0xfd73c477, 0x2816b9c1, 0x0e5a4011, 0xf802e5f8, 0xe61add39, 0x2cd0fc80,
8423 0x02753f6e, 0xe187ebfe, 0xe58e3cc8, 0xf877d814, 0x35eb8c9e, 0x4cec8e7e,
8424 0xbde0a6f0, 0x4f114ebe, 0xa6f70ce0, 0x17bf4044, 0xa7389e05, 0xdffc5378,
8425 0xf56e74a9, 0x45cd3c52, 0xdf873f11, 0x1ce79fd1, 0xc475ebc1, 0xdee8ba5b,
8426 0x8610dec6, 0x8de6aafa, 0x8ac3c210, 0x0d5b4c57, 0xa8d2767e, 0x5f0fae2c,
8427 0xad77f3d4, 0x7cf8db5d, 0x5237434a, 0x7e05173f, 0xa46d0697, 0xf7129df9,
8428 0x3cf54b83, 0xf463a1df, 0x0ecf7c9e, 0x85cf6efe, 0x387db698, 0xe91d85ce,
8429 0x11da6714, 0x44d05eef, 0x497c79df, 0x17834ed9, 0x477e75e7, 0x2a03dd08,
8430 0x3a66edf8, 0x33adec5f, 0xceffc848, 0xcf74600f, 0x00fd7ce1, 0x25e7d792,
8431 0xcf37f92b, 0xfd411fbf, 0xa52f5595, 0xc0652cfb, 0x84ef5026, 0xb5f500b4,
8432 0xc7cff5f3, 0x7e42fd21, 0x6c1de62d, 0x215fece3, 0x260f6e9d, 0xcec2f33b,
8433 0x9ffba47f, 0xe06928f7, 0x9fb289b9, 0x59e9f7ca, 0x2e986edc, 0xcb2b34e0,
8434 0x832dcfc2, 0xd026cf3d, 0x037d38fa, 0x002ec99c, 0x7177a27a, 0x239a794e,
8435 0xeca7e825, 0xca3b108d, 0x379d0ef7, 0x87040fe5, 0x30bbf160, 0xf3c2ec8c,
8436 0x2ec822db, 0xfa9a2d07, 0x932dbf39, 0x389543e2, 0xaba84993, 0x12663ed1,
8437 0x2de4f37c, 0x706ef459, 0xe1c5305d, 0xbb7e3d94, 0x644ee286, 0xbd9777ae,
8438 0xc8926f3a, 0xa69cf1db, 0x56bf57ec, 0x49fe45e0, 0x29d48e25, 0xe3c568f8,
8439 0xb8c3f577, 0x9967f65b, 0x68aee3e2, 0x20639c79, 0x0964765c, 0x45efba3e,
8440 0xe0275ba2, 0x502efe39, 0x2f0388b9, 0x2cfdc9df, 0x7aee6be5, 0x51e3f88e,
8441 0xdf38c31d, 0x43a79e8b, 0xb4fee1fd, 0xded7c7e8, 0xa1cbf546, 0x41ff6f3e,
8442 0x9b67cd28, 0x0392e28e, 0xdb96ebf7, 0xa5ff94ef, 0xd01e65f6, 0x0738fa03,
8443 0x1edac2be, 0x40f91cfb, 0xa2e6c983, 0xd7b71e52, 0xe02cf3a9, 0xc44c19f7,
8444 0xc4c33a1f, 0xf35689ef, 0x35f281f8, 0x71477f13, 0xd2a7c70a, 0xee85a61d,
8445 0x36e9cfbe, 0x115cfe0b, 0x7487eb61, 0x41fb0158, 0xbf1f09f7, 0xb375ee8b,
8446 0x7da8eb3f, 0x131e7ae0, 0xe1d1aeed, 0xdcff1e6e, 0x4bef9039, 0x24a9abe7,
8447 0x38c23a77, 0xc97cc35e, 0xe30ced4e, 0x60480529, 0xe3858ddc, 0x0f18e743,
8448 0xd29ddfd9, 0x743b4a1e, 0x52d95dbc, 0x5e177bf1, 0x44e2371e, 0x77c44d9c,
8449 0xa1b43677, 0x38fc81be, 0x5ea50477, 0xeff5f843, 0x931e0386, 0xc593d77d,
8450 0x7f129be5, 0x93d6ef43, 0x47a3d35f, 0x7a10ea7e, 0xfae1b39f, 0x7ba033df,
8451 0xc5120def, 0xe959ff1d, 0x94ffc447, 0xcacf0e73, 0xe39d125d, 0xa47aaf97,
8452 0x7cbef114, 0x4899a6d1, 0xca3aca0f, 0xed00acb5, 0xa6490eaf, 0x3f5d80f9,
8453 0xf5c64a67, 0xfdf029e3, 0x513fd04c, 0x8067228e, 0x59654ed6, 0x6d953d15,
8454 0xab9cfe84, 0x4e340da4, 0xf27762bc, 0xc27029f5, 0x638c1f73, 0x3701fc54,
8455 0xcf32bf5a, 0x57a7cd1b, 0x788ea1f0, 0xe346efeb, 0x13247f7e, 0xfdf2b93f,
8456 0x3fe17ec8, 0x2fd1b7a2, 0xe1fd2a59, 0x11d4127d, 0xc8839fa1, 0x046e30cf,
8457 0x3cc0bb6f, 0x8087e853, 0xd5a6e37c, 0x1a43f3a9, 0x468cf9d4, 0x45ab3e75,
8458 0xabbdb79d, 0xe3159fce, 0x3b42702a, 0x6c3def18, 0xd01ff717, 0x4bfbc60e,
8459 0x1e630768, 0xd14c60ed, 0xb472c60e, 0x768f3183, 0x0ed1e630, 0x1db9eab6,
8460 0xc1da298c, 0x8c359e58, 0xcb59c9c3, 0x0fb090fd, 0x9f8f3a76, 0x026efca1,
8461 0x8fa885d8, 0xbd220e96, 0xa8be7d0e, 0xedfff437, 0x478805d5, 0xd44710a6,
8462 0xc38c1cb0, 0x83135b6a, 0x93e203f5, 0x664c239c, 0xafb437f4, 0xd506bb3e,
8463 0x63b30e90, 0xe257d610, 0xbe962a96, 0xd6efbf43, 0xe7fadcbe, 0x227df29f,
8464 0xfbf287bf, 0xbef86543, 0x2e7e4cbb, 0x391dff23, 0xf7afb19b, 0x8ce303a3,
8465 0x22f895fe, 0x368e8abb, 0x53fe5c12, 0x7c8313d7, 0x461dabfe, 0x2bf5677a,
8466 0x4d931f71, 0xe77ea8b7, 0xde79daf1, 0xcb9d1293, 0x9c2c3ddc, 0x061ef7da,
8467 0x790fbbfd, 0xd0f3a4aa, 0x9f77ef59, 0x4906de78, 0xa6dce383, 0x276470e7,
8468 0x1c6f1164, 0x4ea77fca, 0xf51531cc, 0xa7f9bf73, 0xf85483bb, 0x787b7433,
8469 0x0c35efc0, 0xd61fd554, 0x7bf01094, 0xbfd4430d, 0xf2c0f023, 0x4f676803,
8470 0x555230dd, 0x6bd20aef, 0x28d5ca36, 0x85c597e2, 0x27c40577, 0x4f7eaa86,
8471 0xa7ae896f, 0xbfa871e3, 0xc90c6f64, 0xb7986283, 0xf388a47d, 0x49c7a581,
8472 0xb7c435ae, 0x3dfa256b, 0xde4279b2, 0xf96aa5b0, 0xe7e5a25b, 0x3646f87a,
8473 0xbdce83ea, 0x84fef451, 0x16258f82, 0x811b0f66, 0x596dbcf1, 0xde1fb45e,
8474 0xf117397f, 0x8dae42aa, 0x781bdfc3, 0xc36f7254, 0xc217a78b, 0x01de44f7,
8475 0x38d63fdf, 0x2f0f112a, 0x3a39ce1e, 0xb17ce00a, 0x4b7ba641, 0xe46f3a71,
8476 0xff0fb308, 0x209674e2, 0x8ddaffdc, 0xf41bfdfc, 0x3ee1c95b, 0x18dda8fc,
8477 0xf6649411, 0x87c15bad, 0x41def4db, 0xaf5d704b, 0x02af4899, 0xd3e49a3d,
8478 0xe932c395, 0x2463256f, 0x62b9e917, 0x4b7dca9d, 0x85a73d65, 0x78d2c83d,
8479 0xef8a8fbf, 0x640fd317, 0xce1d6159, 0x1938a6ea, 0x61a6b8f9, 0x63a40c5b,
8480 0xc3758e8c, 0xa8efe006, 0xef8a7f25, 0x227d9497, 0xf8ef8c33, 0xd09ee6ba,
8481 0xdccf503b, 0x824db3ad, 0x5f1be3fc, 0x6595fba6, 0xed1eb75a, 0xb51d92d2,
8482 0x5ee68f74, 0x82d26ef1, 0x9f6445ed, 0xc88b642f, 0xc4a73cce, 0x94780b9d,
8483 0x58b6958c, 0x823dde60, 0x7788946f, 0xf1f7942b, 0xefe76cae, 0xb8503f3e,
8484 0xf5e77e87, 0x902f5165, 0x9c3f7a5e, 0xfd00379a, 0xf6c91e4d, 0x1f4cf763,
8485 0xc03fa0c4, 0xad57a987, 0x75703e94, 0x9fb9d908, 0xa184afe0, 0xb008c8bc,
8486 0xf1e43f77, 0xbbf8bd19, 0xef78f148, 0x2a7fdbd2, 0x3adbc3ee, 0xc00a87da,
8487 0x7823519f, 0x909dc33c, 0xdf568e16, 0x171aa9f7, 0xe9f7c2ac, 0xa08e8fcc,
8488 0x7c1869bf, 0x607f97ee, 0xfeaaa252, 0x0d0c0f43, 0xbe1187a0, 0x742e74ef,
8489 0xb44e2aa7, 0x4acb9962, 0xe4f1f4f7, 0xd21cbfce, 0x13678465, 0xd82bed54,
8490 0x78bd5f14, 0x45ba3bfe, 0x7a6d7f84, 0x344a97b4, 0xba7d6e3c, 0xb79443a3,
8491 0x442c3953, 0x25b79745, 0x72e53eda, 0x83e3c751, 0x3a7b1f85, 0x97d89dfe,
8492 0x168d845c, 0xc9efe2e3, 0xa1c1ffa1, 0x54da3bd6, 0x3fc22271, 0xfdc69154,
8493 0x36ae1543, 0x01df9e3d, 0x00b1b5fc, 0xfc8dca92, 0x6fa8085d, 0xf9e70d8c,
8494 0x7fae2365, 0xc3fb0f2f, 0x0f2ac877, 0x2f4845cb, 0xf12bdf81, 0x0f9c027d,
8495 0xe94273fa, 0xbfde719d, 0xcfc157e8, 0xc09438c0, 0xb5f1b27e, 0xdf7a1c9f,
8496 0x9aa3de8f, 0x89efc85a, 0xf9933d3b, 0x3c00fbbd, 0x15fdf853, 0xfd12cf7c,
8497 0x43be1fdb, 0x5dbbd678, 0x00b76367, 0xf73b4a8f, 0xdfe20677, 0xbe0f5802,
8498 0x51a0b86f, 0x5e25b9b2, 0xfff2e10f, 0xf482dc01, 0x00800036, 0x00000000,
8499 0x00088b1f, 0x00000000, 0x5bcdff00, 0x6595580d, 0xf3be7e9a, 0x700e01c7,
8500 0x0427e540, 0x094a880f, 0x44101df6, 0x18293b53, 0x54da1595, 0x021f44a2,
8501 0x9a2824fe, 0x2edb52ed, 0x4c7350c7, 0x4a976867, 0x57a3ab1b, 0xb5accd39,
8502 0x8cce9a98, 0x7e927bbb, 0xa772b268, 0xa9aeae69, 0x66b663b5, 0x3b448dae,
8503 0xb5b4d45d, 0xdfbefdcf, 0x23bef9c7, 0xb5cced4c, 0xd7175c3f, 0xfff79e73,
8504 0xe7defe7d, 0xbbf79e7d, 0xc89132a3, 0x1befe24d, 0xffe56ffe, 0xd5a212ec,
8505 0x441f9d07, 0xabe5a30a, 0xae0decfb, 0x60fd65cb, 0xcbf5c5da, 0xc32a63f1,
8506 0x9c284a23, 0xd70770c7, 0x4d5dc69b, 0x27b53edb, 0x97f1ca03, 0x3463fc69,
8507 0x284a83c3, 0x1e3c5ca4, 0xca8d9055, 0x0c61d689, 0xf1c0d11f, 0x3f685d3b,
8508 0xaf214bb0, 0xa09d9a22, 0xd41eb974, 0x62bbdeb7, 0xc8614d3e, 0xf5e6cc63,
8509 0x11741c2d, 0x1b8d1295, 0xe6e5c27f, 0x1487fd7e, 0xbbf70f75, 0xca21d065,
8510 0x10e41d5b, 0x6a21acfb, 0xf9bdf867, 0x9dc1d117, 0xefeb269d, 0x60f37865,
8511 0xbb17e8ba, 0xe87a21ce, 0x6e88b9f4, 0x7645c274, 0x798dfed3, 0xa22ff1f5,
8512 0x71ff4c53, 0x1af6e9e3, 0x0a27510f, 0x7f0cb8b2, 0x8fb90257, 0x86688ca8,
8513 0xccfa349a, 0xb2efc264, 0xf21e786f, 0xa3d3a0f0, 0x512162ed, 0x8f0c6890,
8514 0xc7ad22eb, 0xd2593c03, 0xb8e92bd9, 0x48cbe9ce, 0x99dfe22d, 0x3bfa56c9,
8515 0x3728297c, 0x61d869c6, 0xa3d31f23, 0x3d363eca, 0x8c68e3c2, 0xc8b43e83,
8516 0x345f036b, 0x1bcdbc7d, 0x4c46e7c7, 0xce4db4fd, 0xb9f6e274, 0xd809461b,
8517 0x574def10, 0x8361beb9, 0xf0c426bd, 0xa467ef83, 0x7d1cb057, 0x7a39c9b0,
8518 0xc1f10f3e, 0xa97353dd, 0x80957818, 0x5b8c1fa7, 0xbc5cf214, 0x26d506af,
8519 0x37fad1e8, 0xf9dae4ef, 0xe3b627e7, 0xfe788bc9, 0x92874d96, 0x559c782b,
8520 0xf72ade9b, 0x6ddd13e6, 0xde54dad3, 0xf76539ff, 0xe5e82f5e, 0x86a53ddd,
8521 0x52015dc7, 0xd8ee5f30, 0xdc419554, 0xdeebe5ae, 0x79e3bdc7, 0xe99c1bbd,
8522 0x8f9f9636, 0x3b276d7f, 0x2759cfcb, 0xe24cbd05, 0x7e52f1b3, 0x18953ecf,
8523 0x3f7964ea, 0x9e2050ab, 0x5fda57cb, 0x5b718298, 0x75888e3a, 0xbd1db2ac,
8524 0xb5fff305, 0xc32de79b, 0x99bda1bc, 0x4e0d5798, 0x86dabcc4, 0xd15a2909,
8525 0xb35afcc8, 0x75d044a3, 0x99f7076f, 0xa8817448, 0xba7b7c1a, 0x9ff02dc3,
8526 0x59a13076, 0x6475f7d4, 0x0ed9fc0a, 0x1d3d809f, 0xbbbca285, 0xddf92bc8,
8527 0xc75fefd9, 0x50e704f3, 0x7c079b61, 0x783a14f3, 0x092a77fd, 0xa8029c6a,
8528 0xf7c17866, 0xff04b327, 0x5d88790c, 0xa27eaccf, 0x5e7c9326, 0x26a6e839,
8529 0x455efc93, 0xae7c16a9, 0xbed2cb3b, 0xa9679bca, 0x52f33abf, 0x3e35fd4b,
8530 0xaebf05bf, 0xfda5ba70, 0x1655eaf5, 0x6b8ac6fc, 0x0417ed2c, 0x9bf05816,
8531 0xed2d6baa, 0xb069ae6f, 0x68badfd4, 0x56bea5a5, 0x97c16b5b, 0xd2dbb8ac,
8532 0x0db6b6fe, 0x7900fa96, 0x7272c41d, 0x63e3f994, 0xf313ffba, 0xd7cef005,
8533 0x7ccc7827, 0xd6d7399d, 0xdc8c33d6, 0x32dc861e, 0x07f5de7f, 0xe47c839e,
8534 0x321ca4d8, 0x53cb100c, 0xf513eaaf, 0x305614d9, 0x2cbd9b0f, 0xbb6c4dc8,
8535 0x8999fad8, 0x31f33ec7, 0x7ffd730f, 0xf6c1c8b1, 0x63b4e660, 0xbf19e3a5,
8536 0x916fbfc9, 0xccc8ed83, 0x067d8e2b, 0x19ff0dfc, 0x5dc4df89, 0xf6fef067,
8537 0xf20a2c37, 0x995e673a, 0x3d654dbf, 0xea9d37a4, 0x7cb23453, 0x0e4ddf62,
8538 0x30c06fb9, 0x31e023cb, 0x17c04796, 0x0a9b1e59, 0x79665e88, 0x50ebec04,
8539 0x3b2ff945, 0xde3c042a, 0x8df01011, 0x4f016a8e, 0xf808d474, 0x02458eab,
8540 0x1343bafe, 0xb1d37efd, 0x3a77c042, 0x6ff944da, 0x7c05da3b, 0xca2823af,
8541 0xa11557df, 0x8202bcff, 0x0339c2dd, 0xf6ed5df9, 0x2e7ced84, 0xf9e711d0,
8542 0xfacabb21, 0xeed804ad, 0xdf14dd33, 0xd863aa68, 0x449146d9, 0x91c465e8,
8543 0x8bf9867a, 0x37edc39f, 0x741d476a, 0x1b8f18c6, 0x381f13df, 0x3442bb07,
8544 0x31267bd6, 0x1fc07e5a, 0x03e504f8, 0x2539f505, 0x3ebd9fcc, 0xf9f053ed,
8545 0x4dc692e6, 0xae376c29, 0x09cdaafc, 0x46db7939, 0x8f93862b, 0xb23e5d5e,
8546 0x638c141d, 0x29b8177e, 0xf0269298, 0x0e618b80, 0x88eec397, 0x0177de3f,
8547 0x81e43e60, 0xb963e508, 0xb670cdde, 0xf10a793b, 0xe5c394f9, 0x142f2176,
8548 0xc27ac870, 0xb41e5c78, 0xa9e745a5, 0xdf61241a, 0x84716d66, 0x1c921f60,
8549 0xc895b614, 0x7225c9f6, 0xdcb3e05e, 0xe5857e3d, 0x478b5664, 0x327ef20d,
8550 0x2255deb8, 0x0cec07da, 0xf73dfc9f, 0x514c229b, 0xd444a130, 0xbd72f58b,
8551 0xa0d54758, 0xcff40146, 0xef4e3524, 0x41f596ef, 0x6bc59ff4, 0x30c15f80,
8552 0x9c79f184, 0x7689d600, 0x185db289, 0xce7c14e3, 0xf49b24f3, 0x9642fec5,
8553 0xdf65fb83, 0x9f6152e9, 0xe44ed273, 0x3f31eec1, 0xfeb9f9c6, 0xdbd9d4a6,
8554 0x9a9fcc23, 0x26bfef38, 0xf34a5f32, 0xff9402b4, 0xc13f194a, 0x4c17e60f,
8555 0xc4935319, 0xe7c6c4f6, 0x39f630e4, 0x3f062f96, 0xf41bba0c, 0x48dbe58d,
8556 0x4f891afc, 0x1aa9fcb1, 0xf41bd28c, 0x512f991a, 0xff9505fe, 0x754cbe7b,
8557 0x7ac6ecf4, 0x2adc5ae2, 0x7c6df3d6, 0xe69fbdba, 0x869370a5, 0x80cbdf41,
8558 0x5eb4f267, 0x5d2351e8, 0x9a0bcf35, 0xe0c5ed79, 0x0bbb6c4f, 0x03e3b423,
8559 0x779c56f7, 0x6d273e7d, 0x8b5ff9e5, 0xa0a73a67, 0x33f1e03c, 0xf6eae61f,
8560 0x84da8fa2, 0x2937673d, 0xea54fe08, 0xb45b9aac, 0x9597f85c, 0x36bfab1e,
8561 0x8d9aabef, 0xe8de7798, 0xcd95ff18, 0x6bd1ce32, 0xa6af71f5, 0xf56e312e,
8562 0x6bbb6b58, 0xdaf0bf75, 0x5df96b02, 0xcbafdd7e, 0x91d83ca3, 0xbae5524a,
8563 0xcbf09b68, 0xdc72bd2a, 0xe3af9d6c, 0x099a767d, 0x80e691be, 0x77f17af1,
8564 0x7bd600ae, 0x7e050535, 0xbc04850d, 0x9c62c28e, 0x01d0d9eb, 0x09c891bf,
8565 0x9fddc5bc, 0x5e9162eb, 0x87ded76d, 0x8e49f3df, 0xeb852936, 0xfbb5e333,
8566 0x89bd17a1, 0xe1add437, 0xce96e6f9, 0x63bf402d, 0x2fe13e95, 0x178f731c,
8567 0xdfe40bfe, 0x8fd51699, 0x17fed957, 0xf97adaf0, 0x897c007c, 0x160287cf,
8568 0x7cf857f6, 0xe16d7e00, 0x79bf4206, 0xa61c853e, 0xaffd1b7d, 0x4721cef3,
8569 0xf7f6c8e9, 0x1b3f29ba, 0xbc9cb1ab, 0x92a93a96, 0x55a70192, 0xa5afbf62,
8570 0x8c24d866, 0x7c580973, 0xff3860b8, 0xe8bf90ca, 0x31c8f37c, 0x1b3a646a,
8571 0xa7a58d74, 0x813fe741, 0x470dcfae, 0xc4955ed7, 0x3ee03639, 0x313d9ab0,
8572 0xf6944d6a, 0x89387020, 0xd77e5932, 0xa087b21d, 0x89631f8f, 0xd25f1859,
8573 0xbfa50a89, 0xef5f5ebe, 0x16341d47, 0x53a7a6f4, 0xba5df944, 0xcfb736cc,
8574 0xd65cfb10, 0x7dfa215e, 0x88bda719, 0x092f9c75, 0x820f644f, 0x99d5da3e,
8575 0xf9e7833c, 0x0abb59e4, 0xeec5bbff, 0xd742a6db, 0x4fabb35f, 0x55f4b8f1,
8576 0xe842ee6f, 0x86a393d3, 0xb8b467bd, 0x7b8d1d25, 0x357957c6, 0xc8ef38bd,
8577 0xf5299a5b, 0x85e81490, 0x8d8f3e71, 0xf2c2bb63, 0xe125cbbb, 0x7975e748,
8578 0x12a7db02, 0x49d85ed1, 0x4fdc7f83, 0x4e3cd9e0, 0x0fc8ec39, 0x7e3f8413,
8579 0x9ef0252e, 0x9256f31f, 0xbf659fc5, 0x81add857, 0xb38e92d1, 0x3323e269,
8580 0x73ecaf19, 0x07eb8852, 0x1b5da52a, 0xdd85b8f0, 0xd1b57aac, 0xa9dcfb01,
8581 0x4cb88bdb, 0xf498f7be, 0x4097de3f, 0x26fc933e, 0xf059a616, 0x4b12f524,
8582 0x7c8a94fb, 0xe06a7d4b, 0xa8fd4b32, 0x3e0b12ea, 0xa58666a6, 0x39a2c67d,
8583 0xbb4b3c16, 0x7b3ed2d6, 0x6e0b42c5, 0x596ca1d8, 0x8b6d3944, 0xb5c7fd2d,
8584 0xcfb4b52f, 0xa961de0b, 0x44e060a7, 0xd6aff721, 0xb2df8ffb, 0xe4cf5ace,
8585 0x2f4395b5, 0x928fdfe4, 0xe614fbab, 0xd967b55f, 0x84e5e87c, 0xebac7bae,
8586 0xc7657fb1, 0xa29d9039, 0xffa628d0, 0xddab3ed5, 0xe2b4caab, 0x8bff5e95,
8587 0xaf5cdd60, 0x9fb2eed5, 0xb29e40a7, 0xf2961cdb, 0xddba25b1, 0xc453429c,
8588 0xf8dbf87d, 0xe1665daf, 0x2ebd2c7f, 0xfe038796, 0xb49bb730, 0x97072ac3,
8589 0x3072ac86, 0x1cab69f9, 0xe558f714, 0x5623f2e0, 0xad87f039, 0x67da5072,
8590 0x13b28395, 0xf6983956, 0x0c0e558e, 0xd7e58cf9, 0x3e5588f4, 0xe5345348,
8591 0x8aebf08f, 0x89f956b3, 0xbf510fe5, 0x8f3cdfe0, 0xfde68f42, 0x185afcf9,
8592 0xfe21afc3, 0x77e1bd30, 0x4e4f0ece, 0x67d55e01, 0xf7cf10a7, 0xabcfbe98,
8593 0xf279b727, 0x74ee9ed9, 0xd0257568, 0x3aae5d73, 0x0d5ca4b3, 0x87881df4,
8594 0x198fafdd, 0x5a59c7ff, 0x1a2fda03, 0x0bae59f5, 0x4dafd1f2, 0x39e97dc2,
8595 0x1ddd8495, 0xe7c72097, 0x4758b27b, 0xa87b1ef0, 0xd271d793, 0x3ec0a5d6,
8596 0x2b6b2737, 0xa2f6ffd1, 0x07708536, 0xfe82a0a3, 0x971cfff5, 0x1c7ebc0b,
8597 0x151e7b89, 0x2416ca45, 0x7d62ed45, 0x7af39736, 0xf7e896d6, 0xb9eb9514,
8598 0x1912fadf, 0xbd5248b7, 0x290f112e, 0x20e200a2, 0xadc8bd7c, 0x8e3d062f,
8599 0x3d024fc7, 0x9b2a6dba, 0x7d388a38, 0xf067d829, 0xa53d3b55, 0xfe113f48,
8600 0x7fee8e5e, 0x4eff5365, 0x0ed273ac, 0x97ab9cb2, 0x30e4dc86, 0xd3f27dd1,
8601 0xdc5e0b5e, 0x7f696993, 0xa59f11f9, 0xb42e1fde, 0xa9f697d4, 0x44ecbc16,
8602 0xb4fda585, 0x7c160277, 0xd2daa47a, 0x35b38afe, 0x229c7c16, 0x5f7fafef,
8603 0xe3e92f92, 0x7de44563, 0xba9fdfd6, 0xf788ab7b, 0xe1ad7bc9, 0x23d7534f,
8604 0x4ce23701, 0xdec71cba, 0x404c5c87, 0xfec5cff0, 0xb183ce2f, 0x6b47e96e,
8605 0x294fbaf7, 0xdd3f51c9, 0xff0db3f0, 0x01558295, 0xfdc3b9f3, 0xfba2f9e4,
8606 0x6d7f86f3, 0x8bd3cdf8, 0x721ce27d, 0x26cabc6e, 0xc911c1e4, 0xc7d79c82,
8607 0xfdf7b0d1, 0xbde44be7, 0xc6fd7621, 0x9fe762ba, 0xed95ec5e, 0x729f71f5,
8608 0xc335edd3, 0x5cba33f9, 0x735f1c2d, 0xb8f9f214, 0x79677d53, 0x9e7f7fde,
8609 0xb3cfa4ce, 0x2e5cde84, 0xb3675fd7, 0x31a3f889, 0x52a991cf, 0x7f380d5e,
8610 0x7e3bfb0e, 0xe37deea2, 0x1fd87876, 0x21ddbc79, 0x9fc708e2, 0x2c1b515b,
8611 0x01443f80, 0xef8e338c, 0x7c0fe003, 0xae1fdc0a, 0xfd176a99, 0xbd4897cf,
8612 0x1265da8b, 0x24807976, 0x5dda07ff, 0x0c317ee2, 0x181c85bf, 0xcc7c41fb,
8613 0x62e32051, 0x398b8880, 0x062e321c, 0x4031711c, 0xfe50c5c4, 0xf02a875c,
8614 0x02151d83, 0x2023be7f, 0xd51d23f0, 0xa3bcfe02, 0x721b9446, 0xe32f4b13,
8615 0x1ff0663e, 0xa373886a, 0xe71e4620, 0xe5f927df, 0xd9aceb5b, 0x6f9c5bc3,
8616 0x24a56aa3, 0xa6dbcf4a, 0x2dc8794a, 0x3b407495, 0xed48ffe8, 0x2945ecaa,
8617 0x900ea788, 0x47fbc52f, 0x53ff86e2, 0x6ee830f4, 0xfaa357dc, 0x2461f526,
8618 0xbfee34bd, 0xd0acfba6, 0x8c7d58bb, 0xba58dbd5, 0xbdeb3f8b, 0x8d7bde59,
8619 0xa7ae85f8, 0xbd0c5f06, 0x16a45276, 0x605425f6, 0xef7d06ab, 0xd1eab24f,
8620 0xbe92a5f5, 0x8623d003, 0x74de7ca7, 0x7687ce1b, 0x5607f0af, 0x90ccb6e8,
8621 0xec87e6d3, 0xf3e27ce2, 0xed37e3d6, 0x7db779b7, 0x6eef9ea8, 0xe215bfbc,
8622 0x201d9d5c, 0xda5f1f71, 0x737684a5, 0xf5a086bf, 0x2521147c, 0xfae46fae,
8623 0xe35fb817, 0x33f3d896, 0xf221d620, 0xe6b5bc2c, 0x72fd6b2e, 0x33c91efd,
8624 0x632760ba, 0x96570af3, 0x4aa0e7ea, 0x5f7237ea, 0xdd105ee2, 0xa1572e97,
8625 0x873829f1, 0xcbb4af70, 0xce3846b8, 0x21f3af74, 0x8a2a3fce, 0x0a133d33,
8626 0x746e4e71, 0x177c13a8, 0xcf41a1cb, 0x9e833ca1, 0xeae7184f, 0xe23f753f,
8627 0x8bc7cf8b, 0x7fcf057b, 0xbe76e823, 0xff40aecf, 0x7a08f287, 0x3b41f3fb,
8628 0xe73e99d9, 0xba09c60f, 0x7e3b627e, 0x94cfbe4b, 0x5f28b877, 0xb015c941,
8629 0xa8c6fb1f, 0x65d661c1, 0xfb222d40, 0xe1bf588f, 0x99ee3250, 0xfcc8cf2d,
8630 0xbd33cb44, 0x7b2605e9, 0x10ea5cd8, 0xa6dbbbfb, 0xff2294b5, 0x8b9ddf60,
8631 0x5f1dde7b, 0xce00a686, 0xb12de3d7, 0x77b219fb, 0x47211533, 0x613fbc03,
8632 0xb115aaef, 0x0497b63f, 0x989b7b3d, 0x02ce3c9b, 0x34068f0a, 0x96da00f2,
8633 0x2307c10a, 0xae10d00f, 0xb9b8fb10, 0x8133b973, 0xde76449b, 0x8be0955b,
8634 0x392207e6, 0xc7fe08b4, 0x9b827948, 0xde315506, 0x886706f7, 0xcd281e71,
8635 0xc6d0fe93, 0x1fe16bed, 0x3934f65e, 0x53888741, 0xa74b138e, 0xf3ca943f,
8636 0x1d3c1320, 0xbadfdd13, 0xe7b08a0d, 0xc02ba0eb, 0x9ec22bb7, 0x5d67f81b,
8637 0xf1255e3a, 0x3c49373b, 0x516cf4e2, 0x117ee452, 0x013ec02f, 0x6bdc1fb1,
8638 0x05f1e9f7, 0xfb1003ec, 0x18ec3940, 0xe031d870, 0x61c063b0, 0xc76100c7,
8639 0x6a94be50, 0x43e71172, 0xacd2a33e, 0xaa6e8327, 0xc825f934, 0xe4719867,
8640 0x91edcc33, 0x23d730cf, 0x47ae619f, 0x238cc33e, 0x8f6e619f, 0x4719867c,
8641 0x1edcc33e, 0x8e330cf9, 0x3db9867c, 0x7ae619f2, 0xf5cc33e4, 0x719867c8,
8642 0xedcc33e4, 0xd730cf91, 0x58aededf, 0xb3b71df2, 0x35dc86f9, 0xf21348ee,
8643 0xa6af3631, 0x7efe720f, 0x3977d7e2, 0xa3e7c1f3, 0xebb7212b, 0xc954135a,
8644 0xc96aaee7, 0x3e491b77, 0x3e0ad7f7, 0x7892ebdf, 0x1de19a95, 0x1e422fc6,
8645 0xe640b2a1, 0x47910011, 0x011e4400, 0x4a847910, 0x0023cc87, 0x72808f22,
8646 0x910011e4, 0x1e440047, 0x04791001, 0x0011e440, 0x3f404791, 0x910011e4,
8647 0xf2394047, 0x23c88008, 0xaf24fca0, 0x6304f903, 0x0ba3f05d, 0x963cf72c,
8648 0xcf3dcb43, 0x47e1c16b, 0x8fc3db9b, 0x8fc3d736, 0x8fc3d736, 0xa3f0e336,
8649 0x47e1edcd, 0xa957719b, 0xfc17e84f, 0xf83f7369, 0xb8bc66d3, 0x6212f82b,
8650 0xfaefd744, 0x91808bdd, 0xc571e524, 0x41ec67cb, 0x4f7c8c5a, 0x4dc95e24,
8651 0x545cf955, 0x192b8b5c, 0x844b06d7, 0x7ea14fde, 0xf22df81b, 0x2d37ccb7,
8652 0xcde4214c, 0x14c8bf8b, 0x513e46f5, 0xfddf31fc, 0xe7f84907, 0x5d7245dd,
8653 0xbc957f46, 0x7da34076, 0x5dbe1f14, 0x3b46fcec, 0xeb4d2f61, 0x1f9b0be0,
8654 0xbdff7cf9, 0x2cad929e, 0x8a6d7b4f, 0xb2f74ff0, 0x1870b59f, 0xf74b34bb,
8655 0xf6daf69b, 0x7ee04b1f, 0xba8a0dfd, 0xe89e8787, 0x09673ea0, 0x0256d4e8,
8656 0xd4c2623f, 0xd47f3d54, 0x71616336, 0x3c46dd74, 0x0044ed8f, 0xfd99e779,
8657 0x79e26ae4, 0xb907fd66, 0xb9cfe19a, 0x7e811fa4, 0x0e4dcfb8, 0x263d812a,
8658 0xaa7cbef9, 0xe0b4ff3c, 0x5c4d19da, 0xdb5f793e, 0x77f8668c, 0x8fdfb209,
8659 0x7416489f, 0xb2a361bc, 0x99fbcec7, 0xbb028fb9, 0xbe855db9, 0xbcfbc9ee,
8660 0xaf3126ae, 0xce6cd5d7, 0x75caefbf, 0xa45f70f9, 0x88a66548, 0x3c842bc5,
8661 0xde37419d, 0x1fd88bdf, 0xc43ef89b, 0x1d3d5765, 0x24d0fdef, 0xa93dad1f,
8662 0x91cd7c16, 0x2687ef2c, 0x1f855b39, 0xeec4172c, 0x16adce21, 0xf5abe59d,
8663 0x9a95b7f2, 0x9e784bcf, 0x0bbf7756, 0x35359bf4, 0x6c346ab5, 0x275251ff,
8664 0x36a6ee40, 0xebc31a6c, 0xd50142d2, 0xdabd03ee, 0x93f8125e, 0xe2170235,
8665 0x27d62e53, 0x4149c3ce, 0xa4c89c25, 0xdbb821b8, 0xebf19a36, 0xe99c1b83,
8666 0x548fbf68, 0xf89303b8, 0x7449767f, 0xc274455f, 0x5e40af16, 0x499477a8,
8667 0x7c72d8fe, 0x57e2f20f, 0x58f9049d, 0x613af0e0, 0x8dfd626f, 0xec0f77d8,
8668 0xec2adc7f, 0x21d39f54, 0x3fdd3afc, 0xb5caf06a, 0x29d1b67e, 0x43868ffc,
8669 0x3ea07fec, 0xde30dfc6, 0xa1dfb043, 0x1f8e7186, 0x720d4ebc, 0xb7dacb55,
8670 0x7383bbc5, 0xa9bda179, 0xf2e7d72c, 0x0152dff7, 0x0aed90bf, 0x0dfb29ec,
8671 0xb9654e77, 0x52f4d86b, 0x915dee32, 0x6fe101e0, 0xa1f1b67c, 0x905f1964,
8672 0x9d2689f9, 0xa6fc464e, 0x9347e759, 0x03e5eefe, 0xa96c5bb6, 0xf186ee71,
8673 0x2bd7815e, 0x3f588afc, 0x9bfbc891, 0x82bf5c99, 0xb195b3f7, 0x361adbe5,
8674 0xfec5d267, 0xae6fe1a2, 0xb95de7d2, 0xb7de29d1, 0x3890a0ac, 0xac86560f,
8675 0xfee957ed, 0xada7aae7, 0xca983fe5, 0xa1f2277e, 0xdfa9df86, 0xdbd4ee93,
8676 0x7bdebc34, 0xda7bf0b3, 0x5075c89c, 0x07e906dd, 0x4d0a7ed1, 0xb5cf8050,
8677 0x775e33c5, 0xc32aa028, 0xba9bcdc8, 0x931f343f, 0x0c173d32, 0xb23b0826,
8678 0x8112f070, 0x299832df, 0x8583ade0, 0x19b11cb2, 0x4aa473e6, 0xe3c7dd09,
8679 0x41fba5bf, 0x265e0f37, 0x198207ea, 0x58078e42, 0x14c5318e, 0x165d3edd,
8680 0xd6117a50, 0x36d4ef9e, 0xf9fae18d, 0x95f849bb, 0xe25fc3d7, 0x9ff0458a,
8681 0x7907a14a, 0x6f9f1855, 0x0f21346f, 0x9756b07a, 0x1203d67b, 0xec202376,
8682 0x1082e559, 0xd22c93de, 0x6fc0dbf6, 0xe0b5fe43, 0xebf00729, 0x57cb8a83,
8683 0xe215ee24, 0x77c86cfe, 0x27d41eac, 0x8f26f1ea, 0xc50d278c, 0x5e58b09b,
8684 0xc5b5051a, 0x47afae01, 0x9d12f06c, 0xa4aa4cb1, 0x77df5922, 0x91bc5b50,
8685 0x353fbdcf, 0xb367511e, 0xb3f57e09, 0x8a07b79f, 0x32aa274a, 0x94db27a0,
8686 0xe8bead92, 0x9f289e7a, 0xba665033, 0xf5d52f27, 0x032ef58a, 0xdf758ef7,
8687 0xc341909f, 0x6c0605f8, 0xbf433a64, 0x772253ea, 0xfeea4c29, 0x64a814a9,
8688 0xbe92d6d6, 0x79fe244f, 0x3c758b9d, 0xdff6d0f7, 0xfa08f16e, 0xd4fcfc08,
8689 0x45838b35, 0xac1d867f, 0x77d01c53, 0xadbe0ec3, 0xb7a0e768, 0x3cc8eead,
8690 0xa8b135f0, 0xc5be05df, 0x6db6e7d2, 0x3127db3d, 0x24cb721d, 0x5d5ceaff,
8691 0x80b8f14e, 0xd3dc4e42, 0xb9e48b1a, 0xee5f0e42, 0xf11f9112, 0xb19fb889,
8692 0x6fe00fef, 0xf497430f, 0xc36fe932, 0xa4b9f63f, 0xff080c7f, 0xe04fef18,
8693 0x7f87031f, 0x18ff080c, 0x818ff0e5, 0x0e063fc3, 0xfc3818ff, 0xc7f84063,
8694 0x16d87f28, 0xf33f7538, 0x685b51f3, 0xd39661ff, 0xee6b47c7, 0x51ef9e32,
8695 0x238f92ea, 0x63fb1348, 0x627611b9, 0x7cb13ec8, 0x72a3cbb9, 0xf4fdb4b4,
8696 0x547e5b21, 0x7cb69a9e, 0xdc29f3ba, 0x841fd983, 0x945b6b3e, 0x9194dc70,
8697 0x3b89ece5, 0x3cbe8412, 0xd84b8f71, 0x89d73add, 0x5179dc97, 0xfedbbe7a,
8698 0x27694eb7, 0x3c7c13c3, 0x78b6e2ee, 0x89ff7615, 0xac1c9af2, 0x1548b137,
8699 0xd9c0197c, 0xb256f88e, 0xa5f28796, 0x4ce5e274, 0x57ff576e, 0x7ea2e7af,
8700 0x173cd1cd, 0x11c36fec, 0x1f4ce6ff, 0x21136bfa, 0xaf1e0daf, 0xeac5fe0b,
8701 0xbce2a98d, 0x7190cfad, 0x9140965c, 0x31f83307, 0xdfc64cbb, 0x80ef79fa,
8702 0x127bf417, 0xc0b9c813, 0x2df24ed2, 0xb88cdf56, 0x2b5c6c62, 0x72795f1a,
8703 0x22e23e4b, 0xf4ed49a3, 0xc42f4c5d, 0xd1255c3d, 0xfc6c4ab8, 0x5d5f4863,
8704 0x19e78964, 0x7e994d70, 0xa9efd74f, 0xd4f743cd, 0xf01979a2, 0xbc541fe7,
8705 0x79373f88, 0x674eb77c, 0x89cfa9bc, 0x3f348817, 0x62cae7cd, 0x8afbffbc,
8706 0xbdf80f77, 0x56ec2fde, 0xebc2781d, 0x2151da69, 0xc429b6f4, 0xfac8d470,
8707 0xdec1e4bd, 0x5f619f9c, 0xeb0b80e1, 0x5c06f26c, 0xa77f2669, 0x98094bb1,
8708 0xf819fddf, 0x8e3265ed, 0x07d7c758, 0xf5b6efd0, 0x88a5ae79, 0x83dbb25b,
8709 0x746b6ef7, 0x71fa3139, 0x625ef13b, 0x0cbd3e7e, 0x7de7eab9, 0xbe616ec1,
8710 0x4bf8d312, 0x7e69be31, 0xb5fc2f6e, 0x62496595, 0xef2f06bc, 0x2bd00f3b,
8711 0x1074c9d6, 0xcedfea74, 0x3cc4f9e3, 0xe18dee82, 0x7ac55390, 0xf1834ef0,
8712 0x1390dec5, 0xe8dd2cf3, 0x6d7ef117, 0xdb479c9b, 0x862aea92, 0xbaf0e73f,
8713 0x1e7ecc72, 0xb2e41dcb, 0xd1fa970e, 0x0fc2bd62, 0xa53a626e, 0x634cffc1,
8714 0x3173d7bf, 0xf5f41abd, 0x5aa57537, 0x07aec6fd, 0xad4fe09d, 0xf2c4ae7e,
8715 0x8e5d31e1, 0xcabc6e97, 0x08efe845, 0x533ef0b8, 0x6ffde9d3, 0x22b7e36b,
8716 0xfddb523f, 0xf18f3388, 0x4fd265ed, 0x46740c7d, 0x3c3f383c, 0xfa53ef01,
8717 0xf78bc6d7, 0x2edeb5b6, 0x7a21dfb1, 0x81f4c43f, 0x11ade25f, 0x093966f4,
8718 0x535afde2, 0xd1bf95b7, 0x718924f5, 0x841bba9b, 0x68732dfe, 0x1d79af2e,
8719 0xa0985e3b, 0x596a5d30, 0x3f9c15ef, 0xf2172d5e, 0x5ba1e673, 0x793ec573,
8720 0x9273a09d, 0xd8879bea, 0x908dcb04, 0xea7e436b, 0x1b3ea54b, 0x932c1df3,
8721 0x65839cf1, 0xbfe9c7c3, 0xb69b4f4d, 0x71005035, 0x15524cbc, 0xd4f5dbe5,
8722 0x5f434fd0, 0x6538f56b, 0xa405b6e3, 0x9f0dec99, 0x0dcf6ddf, 0xdd019f43,
8723 0xf9d62c9e, 0x917cf4c9, 0xf7baf14c, 0xe5d67e74, 0xe31ef55b, 0x7557dc61,
8724 0x139bafbd, 0x28b6b09e, 0xb798deda, 0x83f64d2e, 0x5ece43fc, 0xf682e9d5,
8725 0xdd7b44eb, 0xa376e99e, 0xec6ec871, 0xbb0e94db, 0x79115fb1, 0xa5db75ab,
8726 0x99eeb75f, 0xfadf1124, 0xdf8775f7, 0x9ddb85b8, 0x3d77787b, 0xabac6bf6,
8727 0x44ed2c29, 0xb053fb33, 0x73f4cb1b, 0x7b58b3bf, 0xc7a4cca7, 0xccf77f4d,
8728 0xe2c5e844, 0xdf99ff1e, 0x1877d892, 0x67bde6f6, 0x0cf6f17e, 0x357cf45f,
8729 0xcb74b1f6, 0x3c1b38bf, 0x7dc9ba66, 0x2a5c2d6e, 0x5f8139de, 0x6e357fb8,
8730 0x81de4454, 0xffc25dda, 0x2b1df834, 0xbfac0d07, 0x1ca89e8d, 0xc91ffc18,
8731 0xe50d726f, 0x0dff24e7, 0x60721b7e, 0x13e0dbf0, 0xf9359ce1, 0xffbac6fd,
8732 0xb17bafa0, 0xeb5fbf2e, 0x4578b77a, 0xd0996b9e, 0x23573cf7, 0xafaf5ee4,
8733 0x0f96b26d, 0x643bc9f1, 0x2f4337df, 0x9f247a06, 0x6539b606, 0x45df721c,
8734 0xb9c5ca7c, 0xb963ac6f, 0xd66c6f1e, 0x74cb86e3, 0x94f9983f, 0x6a665e54,
8735 0x53e484f7, 0xffafb3e3, 0x627dcfeb, 0x6d8ed27f, 0xe2fe138f, 0x82fd9ed2,
8736 0x1e5bb55f, 0xbb71e674, 0x7719729c, 0x6df3b21c, 0xe7e22f7e, 0x76ecb78b,
8737 0xca73ff42, 0xe562dd25, 0x077f4ebd, 0xe715d06b, 0xf73a628f, 0x7bb0f68c,
8738 0xf59e79fb, 0xf193e36b, 0x6798c6ae, 0xe394b95e, 0x34d4b6c6, 0xd6d8d7cc,
8739 0xabdc03f0, 0xab1fbb0c, 0xa5e3a777, 0xf1e52c3e, 0xafa797a0, 0x15d77352,
8740 0x332f9c5d, 0xc972ace0, 0x79311fb7, 0x3b258ef1, 0xe227e7b1, 0x049ac41d,
8741 0x82e5f915, 0xf3084882, 0x6eb18e42, 0xbc45db17, 0x89682987, 0x14758a7c,
8742 0x02ff7c90, 0xf3269498, 0xef8ce91f, 0x305765e1, 0xd84bb7cc, 0x2107d3a8,
8743 0xe8d3d434, 0x1ff61948, 0xf246b76b, 0x34f90c2b, 0x53b589c6, 0xc96fed23,
8744 0xe9dfdc77, 0x525e3d3c, 0x79bae6a8, 0x4e1ffade, 0xfa3f1152, 0x12ba7db6,
8745 0x6869be64, 0x15ac2cbf, 0xb7ecc369, 0x4683de40, 0x55776fde, 0xbdfb30fa,
8746 0xebac0f28, 0x7bd6f189, 0x25d23f28, 0x15a723f3, 0xdfb8b73e, 0xe2f1b5e9,
8747 0x2fb199bd, 0x5dff3e23, 0x9477e7df, 0x8b71e9a7, 0xc9fc1248, 0xff5d04ba,
8748 0xf94712c3, 0x71b95302, 0x46f49fde, 0xf64cd292, 0xfd36c3f9, 0x76c8a43c,
8749 0x1f6f8311, 0x9c73884f, 0x649d3aec, 0xca7c822b, 0xd6fd19f5, 0xed93d53b,
8750 0xe29b73b0, 0xf66efbc4, 0x8e23369b, 0x154c1cd4, 0xdadb99f1, 0xe0eccf4b,
8751 0x98db6e71, 0x5ebf0aad, 0xe997f3f7, 0x7d712ff6, 0x6869e6c3, 0x0bcf23bf,
8752 0x53d9be3f, 0x2dfc42e3, 0x2b817bb1, 0xf2bdf85f, 0xabe4601e, 0x03542bd6,
8753 0xfb0e5bfd, 0xbdb2bd08, 0x66f38050, 0xffe90ef9, 0x16d1b7cf, 0x75c73be4,
8754 0x82cbccd6, 0xa8a9d87d, 0x176927f0, 0x7ee351db, 0x6923b6c6, 0x72cecd4a,
8755 0x962bebd0, 0x32ff1e3b, 0xec76b19c, 0x7b8027a7, 0x817fb127, 0xa03d60fd,
8756 0xb4b9564b, 0x4fbb278f, 0xa28af925, 0xbf53fcf4, 0xc2e4317f, 0x23359bc8,
8757 0xf20a33ee, 0xf90e9751, 0x63f3d268, 0x0ae7bb9b, 0x4df779bc, 0x4e973be2,
8758 0x647be634, 0x0f5583d3, 0x733e5907, 0xb5347a75, 0x7e01bdce, 0x713d8ad1,
8759 0xe35ee2a9, 0xfd9ae60c, 0xf7dda6d0, 0xce5eef8b, 0xdf178eee, 0x177a54bd,
8760 0x3ef2a654, 0xf54aed97, 0xc2e74ddb, 0xddfeba2b, 0xf2d73ad1, 0x8f334afd,
8761 0x7ff1e5e9, 0xde2893df, 0xa5df192f, 0x8ed6e55c, 0xfbe34ec1, 0xf93ee994,
8762 0x68964a5d, 0x3e361bef, 0x1d33c06f, 0xd3073bf2, 0xd4373677, 0xd696ff72,
8763 0x6718c903, 0x956f43d5, 0xd7108533, 0x1a7c037a, 0x8766cefa, 0xf9a6cefc,
8764 0x77bfe1a1, 0x3e435c81, 0x4b211c57, 0x50b6f17e, 0xb543f08a, 0xef90b930,
8765 0xfc24bcd6, 0x6a76b3dc, 0xf86eb9c7, 0x44794625, 0x94d9c3a7, 0x7ff05cae,
8766 0x7247dee5, 0x9c7c6e71, 0xbdbaf124, 0x7612feb7, 0x4e327b48, 0x120edffa,
8767 0x50636dfe, 0xf7c6cbfa, 0x1baa4453, 0xe573f0f7, 0x95bc6289, 0xc63877fa,
8768 0x10bfd8ba, 0xa83b1fe5, 0xf7c0eb1a, 0x77e79035, 0xf066e11d, 0x47f65df3,
8769 0x4578ef91, 0xbb77bf97, 0x7bc4f3ec, 0xf8045622, 0x1d76ef15, 0xd11e4248,
8770 0xecaac3f0, 0xf0ec05ef, 0x7e290e97, 0x4589c39c, 0x863dc427, 0x6ac978f4,
8771 0x75b794af, 0xcbce733f, 0x2afc2d1e, 0x08e2d251, 0xd7e386bb, 0x34dfba1d,
8772 0x2fdc1f84, 0xfb2d65ee, 0xd2d05fa4, 0x05f84a73, 0x7c619f86, 0xdf6ab747,
8773 0x1827e129, 0x941f56fd, 0x283d6974, 0x6d0a1bcb, 0xa025bc46, 0xacbee014,
8774 0xd9727c08, 0x38364bfd, 0x25e6f8cc, 0xbd000a1b, 0x5fa43c7a, 0x0b5be5f8,
8775 0x33ee257f, 0x71f51bad, 0xe69a7719, 0x4636994b, 0xe5c5c77e, 0xefe83de3,
8776 0x5adfdcb3, 0x50fbca0f, 0x8b6135b8, 0xdabb1778, 0x6cec00e3, 0x7cf388f5,
8777 0x10ad9b57, 0x4a03c9ef, 0x8ee7f082, 0xc6b9efea, 0x3c4dfaac, 0xd45904e2,
8778 0x13cb6bdf, 0xa7f2b8ef, 0x14193cf1, 0x8cbaef14, 0xfc2e67ef, 0x18a547e3,
8779 0xe45c767f, 0x97802200, 0x096c7b4e, 0x53b325f2, 0xf8a0a522, 0x951f87a5,
8780 0x00e44678, 0x60de50e2, 0xe9ca92f7, 0x695c467f, 0xaf8962be, 0x6568adbf,
8781 0xe0eb4120, 0x6b8c9779, 0xfe7c8bf4, 0x8e52698c, 0x7be31cc6, 0x5f51ee24,
8782 0x303dc478, 0xf89b5463, 0x228a8bae, 0x147768a5, 0x823e587d, 0xf084265f,
8783 0xc93c8c3e, 0x983ccf32, 0xa8ef121f, 0x30df32dc, 0xf02e9fd0, 0xb431ce30,
8784 0xda2dd4ff, 0x5dd1cac7, 0xa0fde4d3, 0x63e64e26, 0x399c546f, 0x9b9300ff,
8785 0xfa0b5da7, 0x8bdbe4d5, 0xdef1e3fd, 0xbf03be4e, 0x0d6de7a0, 0xbe8e797f,
8786 0x9efd1caf, 0xd324bae7, 0x0253fd03, 0xe5ddf101, 0x1ac7457d, 0xfd03ff31,
8787 0xd0fe426e, 0xa738c778, 0xabde413f, 0xe716a92e, 0x5073e2ab, 0x563fb71d,
8788 0x1de30b64, 0x16e403ff, 0xc7726579, 0x78b6d9f8, 0x395b1ef1, 0x3817cafa,
8789 0x9fedb267, 0xfef0a6f6, 0x5152ffb3, 0x07eb8361, 0x26f63cce, 0x3dc1bac3,
8790 0x7d8fb1fb, 0xf6235ac9, 0xfaa07271, 0x7e24c694, 0x56e3dbc0, 0xe645f9e5,
8791 0xfbbd1ff5, 0x5b34e48b, 0xfa175d74, 0x78733ccf, 0xc45ba02a, 0xb51ce7a5,
8792 0xcc5638cb, 0xfa642e7a, 0x6e70bbc4, 0xc17ee827, 0x5ee10b63, 0xef68e738,
8793 0x1cdf583b, 0x7dc677bc, 0x6f3cedc1, 0x97c8e73e, 0x1af78a93, 0x64df9d30,
8794 0x1ac0ed47, 0xef4a3cfd, 0x0579bdf4, 0xed57c9ce, 0x73037884, 0x963ff052,
8795 0x1fc16f7f, 0x699ce3c1, 0x2a36def2, 0x4d3826bf, 0x072863e8, 0x3ed338fa,
8796 0xd0b53bfc, 0x638f4534, 0xfc1a7e49, 0xf063f832, 0xdd33a0c3, 0x14a5e270,
8797 0xf8b7d045, 0x3fae9287, 0xe2fd7410, 0x4b5626f8, 0xd70fe4ba, 0x7ffefa0a,
8798 0xfbc8eba3, 0x0d85df93, 0xde1eefed, 0x7f659e5f, 0xda5ffd3f, 0xeff7d09f,
8799 0xd613bfbc, 0x8677a5fd, 0x4e4127e3, 0x7f09b21e, 0x28bdf62a, 0x97b09215,
8800 0x1104f6f5, 0xe412d537, 0x276c06f7, 0x349d825f, 0xeab8e3ec, 0x8afc3148,
8801 0x638f4493, 0x8f5b115d, 0x5a78ff28, 0xb19390be, 0x7c4b2274, 0x9488e137,
8802 0x54ed6fc1, 0x76dd3b02, 0x8733c8c0, 0x7a565f61, 0x42edde44, 0xf27416c8,
8803 0xa1a9ddf8, 0xde78cb9d, 0x448b9bee, 0xd102e51e, 0x1f382394, 0x7f082457,
8804 0x84953bb4, 0x9daeeadd, 0xe796fc28, 0xc2e7b6bf, 0x4dafed5f, 0x6edbf910,
8805 0xfc3b647f, 0x3e09eecf, 0x7f4dc835, 0xf844d0a1, 0x6e05c1ab, 0x02f74f31,
8806 0xb7bb0769, 0x83f7c8e7, 0xf209fa14, 0x48ae8f48, 0xeec17910, 0xc42c81dd,
8807 0xd24c3ecf, 0x2e1f434e, 0xb873cbb1, 0x19cb8f3b, 0xd4d4ac3e, 0x62bc6336,
8808 0x6d48eeb9, 0x797bb3c2, 0x3602f894, 0xb27e5c99, 0x6be4493d, 0xe2317d0d,
8809 0xa782e3d5, 0xc64e8276, 0xebefb677, 0x5dd065f2, 0x0eefc809, 0x721bfa0d,
8810 0xbba75a36, 0xb794af72, 0xabc7f7a1, 0x1e3fbc49, 0x77c04bcb, 0xaa71f56a,
8811 0x32be740f, 0xeb12fb45, 0x7ccb5cee, 0x92fd63b1, 0x1df127fe, 0x95fe30e1,
8812 0xd38f42b3, 0xd45fdfe8, 0xf523b493, 0xed16f7c6, 0x282defd6, 0x79153632,
8813 0xdc47213b, 0x9abef7ff, 0x8dd80ab8, 0xc125df82, 0x4fff1c6e, 0x80efb0fb,
8814 0xbcf215bc, 0x296bc4f0, 0xfdfebda2, 0x1f5fe189, 0x83947ff7, 0xdde4e273,
8815 0xfc058caf, 0xad26a92a, 0x70f5d782, 0x70f3e7ed, 0x159fbd74, 0xbccddf11,
8816 0x8e65fb5f, 0xfbdfb788, 0xeff7908a, 0x02ffceba, 0xb38b7a5f, 0x000040d0
8817};
8818
8819static const u32 tsem_int_table_data_e1h[] = {
8820 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x33b3af8a, 0x21716830,
8821 0x9f0143f8, 0x38606664, 0x8167c40d, 0x81859798, 0x818997c1, 0x78898fc1,
8822 0x10c533fd, 0x0611416c, 0x5e203b06, 0xf0c0c42e, 0xce21044e, 0x10c0ce28,
8823 0x20c0ca2d, 0xafe10a2b, 0x6266d204, 0x40ff71d4, 0x4c194663, 0x089207b1,
8824 0x79161336, 0x268ccc64, 0xca8520ef, 0x7fa02167, 0x2517f1a0, 0x22acbe54,
8825 0x8a846e84, 0x9793457f, 0x432bca83, 0x094df5fd, 0x502ab9bb, 0x1aa00079,
8826 0x03605f82, 0x00000360
8827};
8828
8829static const u32 tsem_pram_data_e1h[] = {
8830 0x00088b1f, 0x00000000, 0x7dedff00, 0xd554780d, 0x733ee8b5, 0x49999cce,
8831 0x21264cce, 0x61021309, 0x40a02092, 0x200c7e18, 0xf7f09d78, 0x803aa568,
8832 0x07515a56, 0x43f21081, 0xbd1f5202, 0x24266bed, 0x1bd568c1, 0xab45a8fa,
8833 0x68a90076, 0x62348ed1, 0xa80740a8, 0x0db6a85c, 0xc7f42ad6, 0xc405ad1b,
8834 0x96aa4490, 0x6bb94abe, 0xe64fbdad, 0x4019939c, 0x6f5fb7bd, 0x6fd697bf,
8835 0x67d9cfb3, 0xdfd7b5ef, 0xb5ed6b5e, 0x897628f7, 0xec650ee5, 0xc75dfe02,
8836 0x319902d8, 0xf4a27576, 0x0d0ebbc1, 0x07f8adfe, 0xccdd2832, 0x2862b12f,
8837 0x2f6e2cfd, 0xfc707281, 0xd65e9618, 0xf37e18c9, 0x959905f1, 0x3271e632,
8838 0xb09417f1, 0xdaf2f5ee, 0x6d87b2b7, 0xd5b28428, 0x6cc653f7, 0x67aaed8c,
8839 0x44f66181, 0xff57873b, 0x91c17e2e, 0xfa4870cb, 0x877560cb, 0xbb87c187,
8840 0xb6e2e7a4, 0x8ef58c89, 0x7e2d8161, 0x5dde0718, 0xcffd059b, 0x316dec61,
8841 0x704605e6, 0x8a50b85c, 0x4b8231df, 0xe73af8fb, 0x0ee76842, 0x00c55fad,
8842 0x7334cf5e, 0xb9a26d7b, 0xf50d18ee, 0xa5fa8991, 0x6ca603da, 0x881de00c,
8843 0xed5c03f0, 0xd79a4ef5, 0x81bdeb8f, 0xb6305761, 0xf547dea7, 0x2a7ef57d,
8844 0xe923f5e3, 0x00fa81f9, 0xb05873d5, 0xeac7f090, 0x66ca2c36, 0x8536f1ac,
8845 0x7412c7dd, 0x8c3d66f9, 0xfea24577, 0x222cd1a7, 0xa4fee4c3, 0x00423bb0,
8846 0x132bc36b, 0xbca13a32, 0x7f41db1f, 0x28018d0f, 0x3fda26c6, 0xdce5f6bc,
8847 0xcb181399, 0xdc91eafb, 0xbde00399, 0x46c616c4, 0xd2ad78e3, 0x9df031bc,
8848 0xdbd1fbca, 0xeb6325eb, 0xed9a0f88, 0x65afdfc9, 0xf2cf0212, 0x7e60ac0e,
8849 0x0f6bf437, 0x07013be7, 0x04c644b7, 0xb8c3065b, 0x186bec48, 0x111b32fb,
8850 0x370e0089, 0x8c799761, 0xf342d0ed, 0x5f1cbbf0, 0x91230a48, 0x299c40c3,
8851 0x2cab658c, 0x470a4b1c, 0x2b71c103, 0x4b0733fe, 0x0f4bd53f, 0x7ef571f2,
8852 0xe711b2f4, 0xcee4e507, 0xde2c5b30, 0x77fbe197, 0xe862d242, 0xe7c5d9bf,
8853 0x736302f3, 0x1249bc70, 0x12b9610b, 0x2dfa1299, 0x312732c7, 0xe5c60aee,
8854 0x6173bae1, 0x547e8416, 0xc785985f, 0xfc837ef0, 0x6c8ca6fb, 0x1b7f9b9a,
8855 0xda9443f1, 0x474ddb1b, 0x88b6fcb8, 0xedc7033d, 0x23ed883d, 0xf6c3163e,
8856 0x39b6682f, 0x3b44b45b, 0x6e499e1d, 0x968b685b, 0x16c82fe8, 0xe5d3fa9b,
8857 0xbe72764d, 0x81def9d3, 0xda9c809f, 0xc228fbe1, 0x3705983b, 0xbdebc127,
8858 0x07a5be62, 0x3c06415d, 0xa3542ead, 0xafa9242e, 0x39eb0cb5, 0x0640594b,
8859 0xe5eb4e1a, 0x0703b8f3, 0x3bcc49c9, 0x37c003e7, 0xfec01d94, 0x08e3e60c,
8860 0xda03a8b0, 0x826b79ab, 0x1f4f5065, 0x1b02d5cc, 0x3672631c, 0xcdc473c9,
8861 0x97a1c3fa, 0xfc13c7da, 0x00df1748, 0x0604ef5d, 0x41dba832, 0x78020ca1,
8862 0xa83b8f1a, 0xe5dc8fff, 0xfd33b143, 0xf1f553bb, 0x3e414b71, 0xa61fd74e,
8863 0x83beabb2, 0x63faeeca, 0x0f1aa654, 0x26c6d124, 0x60df8c03, 0x5dca2741,
8864 0x075d12a1, 0xffee37fd, 0x218ff32a, 0x878823f8, 0x2d16cd74, 0x4e665e42,
8865 0xf815cd59, 0xe12b7c45, 0x8e6ef9bc, 0xbdb3c45f, 0x866d0950, 0x2ad9cf32,
8866 0x786d1aad, 0xfc40740e, 0xb87c1e97, 0x2ea4f101, 0x855ce365, 0x4f9c2f28,
8867 0x97c89f11, 0x5f381abb, 0x284efd62, 0x029539af, 0xef1c5def, 0x53a9dada,
8868 0xc06099df, 0x5c82c29f, 0x28bf39ae, 0x78c77ff0, 0x7b343a80, 0xbde82645,
8869 0xbc077fbc, 0x9e7d268e, 0x906b95c1, 0x9e2adea1, 0x30ddebac, 0xabd27e23,
8870 0x5079edc0, 0x97cfac1f, 0xf8897ff9, 0xfa04dcd8, 0xd57eeb09, 0x21fbc2af,
8871 0x70e0f5a2, 0xca545cc5, 0x1ee7cb5b, 0x62bc6092, 0xa8fde3f9, 0x29d487de,
8872 0xf41a776f, 0x6042c165, 0x86c622bc, 0x2f3f35ae, 0x30eb988c, 0xf3042d80,
8873 0x3f316e2f, 0xd9dcce3f, 0x2e19d227, 0x80906e48, 0xbd5af37e, 0x849a45ec,
8874 0xf58dde95, 0x0dd9ae2c, 0xf427a175, 0xdc99e4ba, 0xadf98119, 0x900592be,
8875 0x449269c6, 0xefc56c78, 0x141e8f80, 0x7e96fde5, 0xac9952f4, 0x02ef50d9,
8876 0xf4c983de, 0xd654be58, 0x56bc748b, 0xfd8bde9a, 0xe6312ba6, 0x54bf90d5,
8877 0xfb6b13e2, 0xf1a14934, 0xa08e94d3, 0x14deeb8c, 0xb6adeebe, 0x9e51c6f7,
8878 0x03f99756, 0x028f5c11, 0x4cdf9251, 0x5e50b358, 0x363c013f, 0x9363c389,
8879 0xf5189c68, 0xdb2beb03, 0xbc38e122, 0xfa57d5df, 0x0d4a4459, 0x2d191fe7,
8880 0x1698ec62, 0x3cfec4ce, 0x709ca492, 0x58d3e826, 0xb36ff451, 0xc372eaa1,
8881 0x7513abfb, 0x7c739ddf, 0x4379c7c8, 0x772bf4cd, 0x7f2015d6, 0xb3628654,
8882 0x7a4e7f91, 0x0edeba7e, 0xf602def3, 0x9ff80282, 0x61e50ce4, 0xea8b353f,
8883 0xf30aa386, 0xe303a2e3, 0x1eb7b26e, 0x39824b07, 0x5ff48859, 0x0175cccb,
8884 0x67dbde05, 0xf03b712a, 0x01f27da5, 0xac5c57b2, 0xc9c7eb8e, 0x07b43291,
8885 0xef83239c, 0x455ef0ca, 0xdee78079, 0x75c32b60, 0xbccc39c4, 0x9b3c83ce,
8886 0xb9b64aea, 0x5ccf4a9e, 0xf8ca5caa, 0x84069efa, 0xb267fc22, 0x995fe228,
8887 0xf841281c, 0xf3e6bc1e, 0xaa67847e, 0x84a5d7c4, 0xde72e2fe, 0xbfb5ef47,
8888 0x00361dc8, 0xf972b79f, 0xee4afb5f, 0x8f8809b0, 0x73979a56, 0x0b926ac6,
8889 0x7323f115, 0x13b90ff9, 0xf878ebdf, 0x961bcf7b, 0xf4979a05, 0x5027f393,
8890 0x6f3e363f, 0x9f9ea3f7, 0x7e3dbcf1, 0x366bd41d, 0x6df7a44b, 0x9f845cfb,
8891 0x3d7947ee, 0xd88356ee, 0x5013ccfe, 0x3ad57c07, 0x8a9c1e3a, 0x665e7bf8,
8892 0x0b3d085b, 0x4ecfa86d, 0x3b68f6e8, 0x78bb97af, 0xfef366b5, 0x8afbf1db,
8893 0x7d430776, 0xf97bb35c, 0xbea1530d, 0x619db0fc, 0x0d6d9a93, 0xafa820ea,
8894 0xac314a88, 0xf4e74cf7, 0xa392ec89, 0x8f7da0db, 0x66f723a7, 0x271dd70d,
8895 0xb8008ff3, 0x37b91ddd, 0x46571f01, 0xdf8d9b9f, 0x0290ee55, 0xc7983140,
8896 0xf07943b6, 0x5253cd5d, 0x5c7c01c0, 0xf99d3db5, 0x89e5f60d, 0x1d7e3936,
8897 0x93cc19ca, 0x59cbbf41, 0x4fa46ceb, 0xaa0db6cd, 0xd39f40df, 0xdf9923f5,
8898 0x3cd7a891, 0x77c0e305, 0x02959f2b, 0x3695c538, 0xef753f6e, 0xaadc2d76,
8899 0xd41afce1, 0xd79c6ee1, 0x5bb62a3d, 0xcbbc5d1e, 0x36f847e5, 0x7de1b3ab,
8900 0xd59ba3e5, 0xa85e8372, 0x640a3eda, 0xa6d700c9, 0x24e181e2, 0x0f01237a,
8901 0x8953c133, 0xedd6867a, 0xa5768aa8, 0x2daa7cfe, 0x6ab1f893, 0x5fea6cbb,
8902 0xd7e47ba7, 0xc887ec8c, 0x55e1375e, 0x2f6adba7, 0xa08eebe3, 0xa0af59db,
8903 0x6a5bd2a3, 0x1f2f5fec, 0x50383a44, 0xfca97b5f, 0xca8fbd56, 0xa27ef58d,
8904 0xbf8843cf, 0xc64edc11, 0x97d760e7, 0x827b2f21, 0xc3ec0bcc, 0xcb06e6b2,
8905 0x0acf50ec, 0xa2ee7af1, 0xc8bfe4b0, 0xec12f5fc, 0x04e0c5de, 0x7afdfac1,
8906 0xf63b0150, 0x8abc3521, 0xa6fc6005, 0x04ce08ff, 0x528ff77b, 0x4afa8638,
8907 0xb82b85b6, 0x287cc5dc, 0xfac5eb77, 0x13f25db3, 0xa9e7d61e, 0xba1f6fa4,
8908 0x2cab74ad, 0x6366b989, 0xf7fbfcbd, 0xbb3f5215, 0xfa151fa9, 0x3f74be29,
8909 0x364fb7b9, 0x7b7b93f5, 0x01cfde85, 0xf2ed27ea, 0xf6e879fa, 0xdcf0cc6b,
8910 0xf3f7a95e, 0xb9e3f532, 0xdee579bc, 0xcf0ccd31, 0xcfd4d51d, 0xd20145c0,
8911 0x3fceb2b7, 0xb43bd60c, 0x8e647717, 0x5341fa37, 0xc0dfd36d, 0x520dc5f5,
8912 0x8ca3e465, 0x792669c9, 0x99660cca, 0x0ce603ea, 0x09cfb532, 0x0fde9915,
8913 0x8595785c, 0x89ef352f, 0x408ea251, 0xf68b43a1, 0xf49520f1, 0x2720d94e,
8914 0x20f77fc1, 0xddcef48d, 0xe04784d7, 0xa2b08e3a, 0x1ab7737f, 0xea4deb1e,
8915 0xcc4874c7, 0x86dfa587, 0x3dfdf5a5, 0x9e9c1ec2, 0xb7f0f1ff, 0x5b5afbe0,
8916 0xa84cf0ef, 0xfb2b6bbf, 0xbcf9e233, 0x3269ffd0, 0x6976c3ab, 0xeffa460e,
8917 0xadd2c29e, 0x5b5e0311, 0x48bf0086, 0xec5b7e89, 0xa3f21f61, 0x901a9364,
8918 0x510fd73f, 0xfa041b19, 0x1fdb1d74, 0x9ee73581, 0xc43ee521, 0x2ffd03bf,
8919 0x8c2af8e3, 0x77c69a3f, 0xb77c60d8, 0x8ef8f92d, 0xf1a6c9a2, 0xa615059d,
8920 0x8c2a9df1, 0x6991f20f, 0x9df18973, 0xad6617e4, 0x8ef8d273, 0xff1a0a82,
8921 0x9855951e, 0x1beb4fc6, 0xc60da07f, 0xfee3621d, 0x17f9bf4a, 0x7f9e635d,
8922 0xfe79a541, 0xa17f9f2a, 0x9f8c532d, 0x5a2ff346, 0x2ff3e5e7, 0x77f3e4a8,
8923 0xc6fb7ef0, 0x7fe1f4f7, 0x263f8e04, 0xe28ef8c5, 0x0ff9e669, 0xdfcf36ad,
8924 0x671fc7c1, 0x6be313cb, 0x75f8fe34, 0xa1ff3e3e, 0xeabe34d5, 0x8f900708,
8925 0xbab4fcd4, 0x8343da28, 0x240dfb41, 0x72a4181d, 0xbb93f724, 0xe38222a4,
8926 0x77ce34ee, 0xbf01a51f, 0xca7d0969, 0x9e29eba2, 0x74f052b2, 0x35328ed5,
8927 0x07bc5a3c, 0x00997f7b, 0x4cbb6975, 0x3a36cd7c, 0xbc0057a2, 0xf932eddd,
8928 0x5e374b3b, 0x3d69951b, 0x1808fee5, 0xfe7c7190, 0xd98f6fc7, 0xb5979c62,
8929 0x3f6ad65c, 0xab9069d1, 0x9d3efd3e, 0xf803ac8d, 0x535e4836, 0x69e804fd,
8930 0x06dea674, 0x49e58c7d, 0xf3c0338c, 0xb38f4077, 0x7ffdfd11, 0xd1b5eee8,
8931 0x0a2faf30, 0x1c284ff8, 0x48d627df, 0x47ffc451, 0xa8a9561b, 0xa6b596cf,
8932 0x07d3d1a3, 0x53a0ad47, 0xd9076eef, 0x3f4f8055, 0x1216e7e2, 0xbf7ec645,
8933 0x24870bef, 0x6f967bb0, 0x6efa601a, 0xfb368b11, 0xfb92fda0, 0xc2f10f17,
8934 0xe85d6ffc, 0x1f932f18, 0x91b7cc18, 0x1b7cb31c, 0xdb0b4ef8, 0xa1f3d836,
8935 0xbb42cb72, 0x52f94fc9, 0xb5bf5cd8, 0xb6ef5cc2, 0xcf18ed47, 0xb1215eea,
8936 0x6defd0cd, 0xff8b7675, 0x6159c7c3, 0x08f112cb, 0x8117de3e, 0xe8f07986,
8937 0xe3c72c36, 0xf5d12f63, 0x56ff2f76, 0x6bf6a787, 0x90547076, 0xe8399d7e,
8938 0x0e48b347, 0x2f6177f9, 0xde15b79f, 0x60ceeddb, 0xfdb9e008, 0xd3e132ab,
8939 0xbee77f0a, 0xec0da0f4, 0x7f4dced1, 0x6e7da3b2, 0xfe158f9d, 0xe75ad63b,
8940 0x7d7155e3, 0x3eb11c58, 0x5aec988f, 0x2f6dacbd, 0x818efadb, 0x9f626a9f,
8941 0xe18efadb, 0xf3edaabb, 0xd115f54c, 0x2fda992f, 0xf4d8b4df, 0x0aeb597e,
8942 0x2d25fbd3, 0xc5f54cab, 0xda9aaf91, 0xc1b6b1df, 0xbab6fef4, 0x6fef4d7b,
8943 0xaa60d8ad, 0xb0fc297f, 0x0b2dfda9, 0x4bde9b37, 0xed0c56fb, 0x1e1abd24,
8944 0xeb76879a, 0x59f90771, 0xf2ebbf3a, 0x16ec0a70, 0xdd834f2c, 0xca036582,
8945 0x6dbfc829, 0xb76b2f37, 0x35ea1e2c, 0xed2761f8, 0x4f280575, 0xe2b7be56,
8946 0xf0dfcad3, 0x1d6c9f97, 0x8c6acbd2, 0x3dbf4143, 0x24393f16, 0x1f1ea0f4,
8947 0xdcb956ac, 0x9bccef56, 0xb57ffe8e, 0x975e1f1a, 0x93ec4fc4, 0xf34498e7,
8948 0xe7a56860, 0x5b80dd20, 0xdaab780d, 0xb3826c5e, 0xe34cbf6b, 0x05d944af,
8949 0x0a5f37fd, 0x88f5c71d, 0x2c160fc5, 0x04f08318, 0xf6f5437f, 0xbb7f5a1c,
8950 0x7d6ce7ea, 0x0bf88ec7, 0x7eaa7951, 0xea279521, 0x53be54c3, 0xdbe5415f,
8951 0x765475f5, 0xf2a5afd6, 0x9508facd, 0xa16fabbf, 0xadf537f2, 0xdfab1e54,
8952 0xf5ebe544, 0xebbb2a51, 0x7cea5483, 0x4327a7db, 0xfe156ec2, 0xb7224805,
8953 0xe45cc55b, 0x96b8bedc, 0xacf1e50f, 0xb470d1f6, 0x031ecfcb, 0xc6a61722,
8954 0x521f9597, 0xc90595e2, 0x028f28ae, 0x7ff4079d, 0x74e34aef, 0x1cd8d972,
8955 0xdee37a06, 0xc01fbe2b, 0x15d41338, 0x47df8596, 0x49dcf303, 0x107f05fa,
8956 0x3a2975e9, 0xc96f60b1, 0x89c7a07c, 0x8a5afe47, 0x456c86fd, 0x28385edc,
8957 0xe2c97ad3, 0xaf48035b, 0xe9378a4f, 0x402fbf27, 0xa39339b9, 0x00a3afe3,
8958 0xb2df04e3, 0xb39fa979, 0x20a60e6d, 0x47a4f71e, 0xf67d2431, 0xae0f56f0,
8959 0x727dab77, 0xb31f18d4, 0xc2b13596, 0x4f9866a8, 0x7eb9bb6d, 0xc39a55b6,
8960 0x8cfe69e3, 0x5f20c69b, 0x50efa379, 0xa547d15c, 0x9f6acfde, 0xfee8e34a,
8961 0x4991db38, 0x217e0a7c, 0x86affbb5, 0x093f5523, 0x1fd8da38, 0x2e287700,
8962 0xb93f8a17, 0x0f94ce5f, 0xb1bb8c54, 0x708ff63d, 0x7fc0773d, 0x6591d017,
8963 0x7ef5d50a, 0xc472636b, 0xef9f1631, 0xdf078d30, 0xfb9f75f9, 0xf8c5d142,
8964 0xf4276155, 0x9b6a8279, 0x0e443e8f, 0x6a2b95f2, 0xa699fbd6, 0x5e7b6d7a,
8965 0xe00eb4d4, 0x59ee403f, 0x3ae0a485, 0xa8b82d58, 0x245ad147, 0xec8c6f80,
8966 0xf126fce7, 0x4ece3576, 0xbe47ec35, 0x54e2fc69, 0xa56cb63f, 0x3be15af9,
8967 0xabd87f5d, 0x5c7e245c, 0x3bbd9f25, 0xffc8bed9, 0x48bef996, 0xd3db8db5,
8968 0xa0f119cc, 0x117ccabf, 0xe18bc60f, 0x0fc3eb4f, 0x8e304df9, 0xb3f7aea1,
8969 0x4def6a22, 0xd9764eb6, 0x1d6c9db8, 0x7b8c45b7, 0xdcadfc29, 0xce367471,
8970 0x95c78adb, 0xb4abefed, 0xffc0a31f, 0xd478134a, 0x0e463bf1, 0xdfc0c8b5,
8971 0x22dfdb95, 0x3d94f27b, 0x176bfc32, 0xe1fd5bd1, 0xb7147cd7, 0x611de7d5,
8972 0x9dce381d, 0xff67f17d, 0x7585bf2d, 0xed97ddf1, 0xf62cbe3c, 0x70387437,
8973 0xf506d0d3, 0x6776a225, 0x9bc5155b, 0x3d75dddf, 0x594b6fd9, 0x644e83c8,
8974 0x452d6b05, 0xb30cf03b, 0x9d3c41cd, 0x267aaf61, 0x43b4e818, 0x974e4956,
8975 0x10ed98b4, 0xf54d5fb0, 0xf5cc9be5, 0x173f3672, 0x46f94cf5, 0x344a8b3b,
8976 0x47fbd33f, 0x7fe12f65, 0x8f5bab39, 0x9da373eb, 0xe9ddb3ef, 0xe83e4a65,
8977 0x1e179adb, 0xff38c52b, 0x7ebe648f, 0x1593f1ea, 0xab8edc59, 0x31566d8c,
8978 0xb687ffbe, 0xca9c5f09, 0x7ae8fbf0, 0xcf221f5c, 0xfe6d814b, 0xa4fdf8fe,
8979 0xd5e15bf0, 0x717eefd7, 0xcd47011c, 0xbc692976, 0x892cbf77, 0x63f39ff5,
8980 0xbaa5e286, 0x5be7d76e, 0x22c9afea, 0x19332c1e, 0xebc67ee9, 0xe832d88c,
8981 0xf38e207d, 0x3408e9db, 0x72c2fcc2, 0xf64c98e8, 0x1984bc44, 0x30e585da,
8982 0x5e92ef3d, 0x93bb4729, 0xb412f129, 0x21ed6123, 0x3f05553e, 0x129e69c8,
8983 0x31bb778c, 0x67718bbe, 0xd60b6797, 0xe62bbbd7, 0x16b51c62, 0xf7f401f5,
8984 0x61f66780, 0xb2709fdc, 0xf81078d6, 0xef33e1d7, 0xe6fcb82f, 0x75ea3a7a,
8985 0x00f877d4, 0x8c02f9f7, 0x23e954e2, 0x01dcedcd, 0x1f6cfd73, 0x5f7ce29e,
8986 0xf71c589c, 0x0cb8b5c7, 0x4ac9b3e3, 0x54bf9f57, 0x871afe84, 0x5a64ec1f,
8987 0x7978d6ff, 0x7e2295fb, 0xf4f8e6bf, 0x89175981, 0x939ed547, 0xceb0d458,
8988 0x2abd2ad4, 0x39ed61f2, 0x6a7f9e85, 0xd587eabd, 0xf357a0d6, 0x929a70e5,
8989 0xc228f5c3, 0x6138c127, 0xe3809f03, 0xf9ca35ea, 0x7c3f0b08, 0x99b2386a,
8990 0x918fbf49, 0xe0c9f9c3, 0xfbfdd4f8, 0xe23ff5fa, 0x61ffb4bf, 0x909ffafd,
8991 0x179affac, 0x8115d99e, 0x87f2a2f5, 0x3300f6df, 0xd69577b3, 0xbdd000dc,
8992 0x07b35b7a, 0x1294f2e5, 0xdf5d20f1, 0xa273ca8d, 0x52a1f849, 0xa82ef9d1,
8993 0x3fc4a549, 0x9fa747c4, 0xe80de6fe, 0xcdb47fc7, 0x7eff25ee, 0x00ee23bb,
8994 0xb6d95ca6, 0x76c7cb82, 0x7ebc5bc7, 0x9fc8fbcf, 0x7d66edb5, 0xb7e4f951,
8995 0x7eb4fd73, 0x1bff8445, 0xe561ff27, 0x8d9c7f13, 0xeb2d58f6, 0xfd67bd25,
8996 0x973fc70e, 0x62c2f645, 0x7bffa335, 0x56b21f7d, 0xedb6a5e0, 0x3ee3ef9b,
8997 0xe7db6d44, 0xe9a1724e, 0xfad1bf24, 0x07f0855d, 0xd9dc556e, 0xc49baf14,
8998 0xe9bf2126, 0xee516178, 0x3c2fc80f, 0x9cf18256, 0xf65e27ae, 0x7c8da348,
8999 0xd9dff5ca, 0xfdef92d8, 0xae5a9fd8, 0x1a3f41ba, 0xcedd6eed, 0x3f0bb7f3,
9000 0xab2f0f66, 0xee0f71ed, 0xb66f541f, 0xf55cbed3, 0xffbf5b33, 0x8e57c608,
9001 0x4057023b, 0xbccf55ff, 0x5035faf4, 0x9ece7aaf, 0x434f973d, 0xf4137293,
9002 0xd6ff85a9, 0xa3d04f8e, 0xa92f47f2, 0xcf8d0fb8, 0xa0959ebf, 0xfb73d54b,
9003 0x3fa63655, 0xf6c4663e, 0x125a9dab, 0x9adec4fa, 0xfc86fe8d, 0xe91579c2,
9004 0x893eeeff, 0x824c2c0d, 0x912fcdcf, 0x22788cdd, 0xf57a0a7a, 0xbed2cfd1,
9005 0x7a42e816, 0x6b2f42d1, 0xfe4269bb, 0xa78c5fb1, 0xfb3f7f03, 0xf977dc63,
9006 0x7880238d, 0x2ef678a8, 0xa4e7ce0f, 0xfcf9c752, 0xcc5ce6b1, 0x47b0a8b3,
9007 0xf254bd72, 0x7f8f15e7, 0xf96ff885, 0x52e4afd1, 0xf305833c, 0x443b646c,
9008 0xcb9e70f2, 0xe699bd1e, 0xc4c2ce59, 0xc98f1587, 0xa1f0ff94, 0x973ce6c2,
9009 0x16de4e44, 0x8b727272, 0x4e859283, 0xfb8242e2, 0xd1caaf10, 0x5bcf146d,
9010 0xaf92f145, 0x6c47fbe8, 0x743fd535, 0x2bb57a72, 0x4b0c1fba, 0x9f7f9189,
9011 0xe903a7b8, 0x70487a74, 0x6b81c620, 0xf8111299, 0xbf402e90, 0x0359d1f2,
9012 0x5f989d39, 0x81df1529, 0xcf819ffe, 0x3d877db1, 0x7d312ae8, 0x26142ec7,
9013 0xc6235fc6, 0xd0d3b807, 0x0b993dbe, 0xf99260f6, 0x3d25d865, 0x0cc1d46e,
9014 0x7790667c, 0xdc4fff2e, 0x975de5cb, 0x39bce8ff, 0xd783fef8, 0x77e11cb8,
9015 0x5c00bf68, 0x7ef481f1, 0xe9124dff, 0x278b0707, 0xec27f393, 0xefcdce42,
9016 0xf002fcad, 0xf71eb82b, 0x938e0df1, 0xfb207445, 0x7c237cb6, 0x38abd46f,
9017 0xbf7fa7ae, 0x172f1cba, 0x8af7e0fa, 0xfa100fc8, 0xf5ca3d80, 0x243f6a40,
9018 0x7b75edc2, 0xa08ffbf4, 0x46bc82fc, 0xf6bf28fc, 0xbdffce10, 0xff5f071d,
9019 0x7bcdc832, 0xcd6e5d31, 0xb72ad57a, 0x66af3b15, 0x3df6e4c9, 0xca92c02d,
9020 0x2a4f3c2d, 0xf1275ab7, 0xaf5bdff3, 0xed5478ea, 0xebaabd66, 0xb4f854c9,
9021 0x8acdc9ea, 0xd56af09f, 0x1af7f093, 0x8fcfed2b, 0xfcea1f3a, 0x9a83f957,
9022 0xfa8fa8a1, 0xc3e754f8, 0xf9d53e3e, 0xd13c5fb0, 0xfbeb4784, 0x18dc605f,
9023 0xfbb425f8, 0x81f3b3d7, 0xf87bd5ae, 0x777c2cbe, 0xaf80eb08, 0x5ad37720,
9024 0x1b67e50f, 0x3d4b51eb, 0xb41f6966, 0xf69643d4, 0xcebd4b61, 0xe3ca3ed2,
9025 0x5507ed69, 0x37139f9e, 0x63afb7b5, 0xb1c63711, 0xc714caf7, 0xd79801ee,
9026 0x3b3df7c3, 0xc291a30a, 0x6f5b5e44, 0xf51eba8e, 0xd7b78f59, 0xaf62f683,
9027 0x7aefc78b, 0x4c9ebd42, 0xd6f69d83, 0x71f4991e, 0x49cd9467, 0x05824fe6,
9028 0x64ebf44d, 0xb8f3dea9, 0xddda0f7c, 0x592cde30, 0x718b582b, 0xf2995698,
9029 0xdc369667, 0x8cfcc1e2, 0x37c53d9e, 0xcbe7842e, 0x9b7cc88e, 0xf2541230,
9030 0x29dc7e0c, 0x9a687916, 0xf7c7fb84, 0xec97fd13, 0xd2dd7ee1, 0x73f393fb,
9031 0x5caef8a5, 0xdea2a35b, 0x6dec7f04, 0xde83bee3, 0x96a3c54f, 0x17ae7be7,
9032 0xfdfdcf7c, 0xefcc27ca, 0xb03e22c3, 0x71fbe74c, 0xcff71c6c, 0xae77e519,
9033 0x96777a16, 0x85c6fa3c, 0xc39e8740, 0x39be4332, 0x3a2647bb, 0xf7c1dd9c,
9034 0x3ece29ef, 0x97b5f905, 0xaf8e9df4, 0x118f942e, 0xd750f5a9, 0xfd2fbff3,
9035 0xdea9341a, 0xef92dbf5, 0xebb5d942, 0xb117f0f8, 0x051bc2fe, 0xdbfd65bf,
9036 0xa2e7d8cf, 0x7d9e8d7d, 0xec87da6e, 0x82f3fbd9, 0xb77d61af, 0xf6708023,
9037 0x0973fbec, 0x3acf51f2, 0xb1ea0547, 0x1fdc219e, 0xe7fbdc6d, 0x3f5a4e92,
9038 0x937e789b, 0x67c3fb9d, 0x4df5fcf7, 0x984b1b29, 0xfb07da15, 0xa87f69d2,
9039 0x8a2ec7f6, 0xfdecf5ab, 0xced1a973, 0x59f3acff, 0x7b1bf629, 0x4ee16cdc,
9040 0xef932f84, 0x38bed4d3, 0xe6036b65, 0x57edb463, 0x19fbc097, 0x825f393f,
9041 0x2767b1fa, 0xedba7bb7, 0x7ee38f9d, 0x2fed77da, 0xbd03b3ae, 0x063851ba,
9042 0x3f529a81, 0x92d11e9e, 0xc53ce5e1, 0x1f172f0b, 0xe0c7ff3b, 0xf57da243,
9043 0xa8ee3dea, 0xff79c253, 0xa2dfcde5, 0x20e7d83e, 0xfbe7d4be, 0xec81ac5e,
9044 0xfbcd4b91, 0xbcdd3fe8, 0xcce5f8a5, 0x7c1ff7bb, 0xf26377de, 0xe5fdd5db,
9045 0xef9f3fa0, 0xcfea9bbd, 0xef0403b8, 0x57bbf265, 0xfd1c7955, 0x9ffe741f,
9046 0x813bee98, 0xcf4b9eee, 0xf83fec7b, 0xfdd353bc, 0xee82edc8, 0xa947cc5e,
9047 0x8279c9fd, 0xb9ea93ef, 0xce87ff1b, 0xefd7b75f, 0x315a05b3, 0xbd1d3b2f,
9048 0xe1e73c01, 0xe182df9e, 0xce46fbc1, 0x28dda2f7, 0x2b4bfd8b, 0xfb95117c,
9049 0xf3c4b27d, 0x1e10d9d6, 0x4fc263cf, 0xd710f342, 0x272b454f, 0xd6d154bb,
9050 0x94ccdd93, 0xf0104740, 0x7755df72, 0x87d72806, 0xc6163f8d, 0x0169e0fa,
9051 0xfc5b578a, 0x058926c5, 0x9557b025, 0x187f3eab, 0x48fb16fd, 0x4251dc5b,
9052 0xde585be5, 0x7690e223, 0x67f26aaf, 0xbae6d1b4, 0x3bae6fcb, 0xc64e7f44,
9053 0x58fa77e1, 0xf2d1e314, 0x98bc0795, 0x538f26cf, 0xbb2ea618, 0xfd046b58,
9054 0xfccf8706, 0x73f422fd, 0xb45bf10d, 0xb060e3db, 0xad8efbfd, 0xf3383f14,
9055 0x60375bf4, 0xca2f55bf, 0xe97809cc, 0x7166e1de, 0xaa251be4, 0xd9523fa2,
9056 0xbe290726, 0x174bc4a2, 0x750bf618, 0x87eab17b, 0x72ab826e, 0x173a23a7,
9057 0xf5dcafbe, 0xb75a1287, 0x3d92f5d7, 0x0a5a791b, 0x3be1a36c, 0xb03f704b,
9058 0xbe7e4952, 0xe79511e4, 0x4eed751b, 0xbc7e885f, 0x6be79db4, 0xb16ec656,
9059 0x28790c3b, 0xdebb541b, 0xf228f88e, 0x2cf94494, 0x4f319f08, 0xbb57b750,
9060 0x7c38929e, 0xe628f6ed, 0x7f6e567d, 0x11e31bae, 0x011cc795, 0xb76b1b74,
9061 0xeff14fbf, 0xc67c3f19, 0x977e49d3, 0xfb43f26c, 0x65db7ff9, 0xb6caeba2,
9062 0xa15bb21a, 0x195df44e, 0x27d6fe13, 0x7eaa4ff4, 0x1e1777b8, 0xd1faa894,
9063 0x778c1e93, 0xe6d8ee9c, 0xfb703f21, 0xfd31e3c5, 0xbdd8bdfc, 0xc2fbdfc2,
9064 0x54e3e449, 0xfc69defe, 0x3f51d807, 0xf37e2d55, 0xc76401f6, 0xc9a59c02,
9065 0xfe74c7f6, 0xc3e67aa9, 0xd95e31c7, 0xc7bdf3b5, 0xbfeaee11, 0xb471e9fd,
9066 0x973ed943, 0x6a2df717, 0xc535fe9f, 0xdeeff477, 0xa25c7954, 0x2927a9fb,
9067 0xfe0dd63e, 0xbdd6f636, 0xfa0164f7, 0xfdcfdd23, 0xe7fd1725, 0xd1677b35,
9068 0xcf358ff9, 0x92c818cf, 0x225eb1c8, 0x232f46ff, 0xdba5673e, 0x6483b6c1,
9069 0xba019f2f, 0xe7d2bfa3, 0x786ac7c7, 0xfc2fc47c, 0xe3c91df7, 0xf5fcfda1,
9070 0x5e3705b6, 0x6db8f98b, 0x83aa00f6, 0xafedfa4b, 0x5ec73d01, 0x88771d06,
9071 0x0bec4cf8, 0xcfdbf517, 0x5e803fe0, 0xfc742de7, 0xf7d96db0, 0x6d77c11e,
9072 0xedfa5203, 0x9fc0cbf1, 0xa23d6f1e, 0x940e9d06, 0xa03f9db7, 0x6fd20978,
9073 0xfbb84c2e, 0x300b0f99, 0xdeca7d5e, 0xb1e53b7b, 0xd17875ef, 0xfbdcad4f,
9074 0xf753c906, 0x9e2947f3, 0xb3dc44c9, 0xf1fdf59b, 0xa1c894f8, 0xcdc27dab,
9075 0x07417dfd, 0x3df8078c, 0xfdf85cf4, 0x78f5af9c, 0x4038aa40, 0xe4f3c1d0,
9076 0xcd7038f4, 0x7e15bf13, 0xd26e8275, 0x5bd7a464, 0xeb5f8d17, 0x1e22f078,
9077 0x5ce31926, 0x7d2ee3c9, 0xdd0b2e71, 0x5f56f8f4, 0x83ea0b1c, 0x95119e31,
9078 0x371648de, 0xe3ccdeed, 0x7376dd63, 0x4e824dfe, 0xd535ee3c, 0xe8d38e61,
9079 0x2f254df3, 0x6a5edcba, 0x4f149f1e, 0xbb08d0a3, 0xbabe3fba, 0xdfae4e3e,
9080 0xde5c776f, 0xfdca757e, 0x7592a594, 0xc736e53f, 0xbc3f68d5, 0x57ca32a5,
9081 0x0c79e5e8, 0xc8b9befa, 0x5a7aec17, 0xfac978a6, 0xefd241d8, 0xefa1fd56,
9082 0xade159b7, 0x6caef013, 0xd747ebe7, 0x8354774e, 0xec0eba7e, 0xb95ebe26,
9083 0xfd152de3, 0x7fdb43cf, 0x8b3b72a4, 0x1fae11cb, 0xba7cc351, 0xc25fdd9e,
9084 0xdf3c7ae3, 0x37ce3ad9, 0xa93edc1c, 0x9c7c93dd, 0x9bef1dda, 0xc48aa9c6,
9085 0x79ff9e54, 0x2b4ef1f1, 0xbfb05bc1, 0x3a761dd3, 0x263a73cf, 0xbfb649cf,
9086 0x1761d8bb, 0x2f2b41f6, 0xbca51d61, 0xbcfca3ee, 0xd357c4c5, 0xcd7a0f28,
9087 0xc5bf39d1, 0x406b8c73, 0x6c4ed1ac, 0xda7ce06b, 0xf9827ff6, 0xa3b6ef48,
9088 0xfd71965f, 0x35f885da, 0xafa58bd8, 0x8370cdd5, 0x5dfd287e, 0xabb22268,
9089 0x3a4cef55, 0x0fc13366, 0x75c40ce3, 0xc1fa09a1, 0x9fcc7dfc, 0xcf647842,
9090 0x8f0839ec, 0x5d79b5ec, 0xed52f249, 0xcaf2885a, 0x5eed7ef5, 0xc338de73,
9091 0x4fd086f3, 0x5e7a95f7, 0xf1032851, 0xcdc761f4, 0x328674bc, 0x775917bc,
9092 0xd9bd094e, 0xf1601f55, 0x081cfc11, 0x7e456bd6, 0x839ec570, 0x560f51b3,
9093 0x2fe624c4, 0xada473c4, 0x763f3724, 0xa573f264, 0x515db351, 0xd457e7b9,
9094 0xb78db2be, 0x6a3162af, 0x8c45e78f, 0x6c4d5bf6, 0xe11ec582, 0xf223ddfc,
9095 0x95cfaa42, 0xff21b8b2, 0x9f8267eb, 0x26bdeaba, 0xf08d5f3d, 0xd61afb41,
9096 0xc4d4e341, 0xd1c69806, 0x9b9cd5db, 0x46afea6a, 0xab7e20e9, 0xf42ff739,
9097 0xeabe4fbc, 0xd487847d, 0xe09be7fd, 0x853ff44e, 0xeb2427c5, 0xb73d1a7f,
9098 0xe6fa87e6, 0xde6378f3, 0x882cbd02, 0xe88cfea2, 0xd3ca73e7, 0xbf808da2,
9099 0x3ff85a23, 0xdcf81f50, 0x625f0b1b, 0x326cde78, 0x709f59e5, 0x0f047c88,
9100 0x047cf0f3, 0x7583622d, 0xcb6d11f8, 0xf28c6986, 0x8c3b4e0d, 0x5e2c06f9,
9101 0x6f447a82, 0x25bdefd7, 0x7e30611f, 0x1650aa02, 0xde631670, 0x8d07ac3f,
9102 0xb05b3cf3, 0x9f9ba8fe, 0xbd602c93, 0x60ff31fb, 0x0a03f0ab, 0xdc58ce31,
9103 0xa7e4bcff, 0x3d99273d, 0xd0d56ca3, 0x9cb36300, 0xa02a6723, 0x296fb32f,
9104 0x0bdf2e7b, 0x3d9b1966, 0xb3d0f313, 0x971b2c9f, 0x4b58f507, 0xcbff7f27,
9105 0x500571b2, 0xe2eae63f, 0xca24abef, 0xbe5b57d3, 0x7da2333b, 0x137d3d06,
9106 0xa4d4a660, 0x409cb3a7, 0xdfa133cf, 0x1f99717d, 0x557a1ef3, 0xc216678e,
9107 0x73264376, 0x7ed60dfc, 0x75fa1cf7, 0x0d9d6d43, 0xb7be5fa8, 0x7499cff7,
9108 0x23f30fde, 0x6b1e9cf0, 0xe11d22f2, 0x170be4d1, 0xe6b3afc9, 0x74fce999,
9109 0xec5c3b95, 0xdf363a04, 0x23ce9239, 0xde31523e, 0x26e37e89, 0x70f3b791,
9110 0x3f21be5f, 0x93b57897, 0x44f9f7ef, 0x0fd9d75e, 0x2eb2330a, 0x7d6a1fa2,
9111 0x0628278b, 0x5e947ab8, 0xf9efb7da, 0x31dbadf8, 0x99eb130f, 0xc499d649,
9112 0x7be94bf7, 0xf3053e6b, 0x2d9f1366, 0x78867c15, 0xfaf21a73, 0x9511cb97,
9113 0xc55bda07, 0x8bd337fa, 0xd52297f3, 0x9f5185f2, 0xb4c74f1c, 0xd3c45cf0,
9114 0xcf299ce7, 0x7a45ce75, 0x6675cf5a, 0xe0374339, 0xe7e57977, 0xfaee500a,
9115 0xad4a69ce, 0xeb3f4879, 0xf4a64fb9, 0x19f992da, 0xcfb9c45b, 0x710f7054,
9116 0x71c36f85, 0xdfe27e8a, 0x7fe41879, 0x803552ec, 0xd763a4a9, 0xa4280c4e,
9117 0x45de789f, 0x3c2be0ad, 0x1ee74eae, 0xcfb466ee, 0x8290e3db, 0xdcf7d7e8,
9118 0x60bb25e5, 0xe4b9d2f0, 0x17a4f75f, 0xa93f30c6, 0xda7e6be7, 0x427b040f,
9119 0xb21f3942, 0xf2ee2327, 0x647e9c90, 0xcc8fd391, 0xb71e6972, 0xbdbf82e7,
9120 0x8af3fa93, 0xcfd0c0fe, 0xee9f9c4d, 0xdf7af991, 0x3827ef53, 0x7ec8b086,
9121 0x772f1fb4, 0x853bafbc, 0x03e8281d, 0x1186fff8, 0x66c740ff, 0x3a43afac,
9122 0xc74a4c8e, 0xb47464e6, 0xe49dc79e, 0xfd87df0c, 0x443f2c9c, 0xe7ad72e7,
9123 0xc9129970, 0xe9593c43, 0x3eb4ab5b, 0xb9d25b8c, 0x3b27de7b, 0xd8dfa746,
9124 0x4e88e3b5, 0x843e7a06, 0xf3dd8c70, 0xd6e10dbe, 0x291df8e9, 0xc14c1db9,
9125 0x8ffbabc0, 0xd3b0bb97, 0xbed24e16, 0xf5296d64, 0x82d9f807, 0xf3f018e3,
9126 0x9fbfd614, 0xe14f3f1a, 0x3f032fbc, 0x7e0e5ecf, 0x4aaf3f74, 0xee1571c8,
9127 0xff9d015b, 0x5b9f9fe8, 0x96cee304, 0x15d3e235, 0xef8a64db, 0x79b9fb42,
9128 0x5fb909b9, 0x3f6ea531, 0xf15c579e, 0xb4fc4498, 0x7fbf9c54, 0xb7bf9c4f,
9129 0x2f9603e6, 0xbd9e908c, 0x94605e74, 0x76d546f4, 0x09c3f3f3, 0x3ca02afe,
9130 0x89ef715f, 0x15805f7e, 0x213567ff, 0x365d4bd7, 0xfd02bde3, 0x66ceb7e4,
9131 0x9bcf2bca, 0xf90fd7d1, 0xff9b3efd, 0xfdd38a0d, 0x6e30cecc, 0x27b25414,
9132 0x131f11c6, 0x6fd899a5, 0xbd2f9099, 0xcd6ba1bf, 0xc4615e76, 0xb8b03e7c,
9133 0xf03e7cc5, 0xf9f3568a, 0xcc9b11c0, 0x8caf03e7, 0x8e07cf9a, 0x54de3eda,
9134 0xc6bb131f, 0xfb6c7ed4, 0x5c7d5374, 0xf6a6f3fc, 0x37cf0e13, 0xf8eeafd5,
9135 0xa4fda9b2, 0xde9a7763, 0x34ace94f, 0x6a7a9fbd, 0x6d7ea9b5, 0xda9abfef,
9136 0xfd7197c7, 0xe47ea075, 0xfa9e6354, 0xcdaa5581, 0x0d57cf8b, 0x8c4b79b7,
9137 0xfe8373cf, 0x834b2c12, 0xd2a767e8, 0x579c33b3, 0xf7ae354e, 0xd26ecc65,
9138 0xe69c333f, 0xe225c7ba, 0x2fc00510, 0x2e01fc40, 0xbc815cb3, 0x1e40bae5,
9139 0xb5a6ebf2, 0x83c7870c, 0x40cb0c56, 0xcb390279, 0x9c9e5d75, 0x93bb63e5,
9140 0xb1ebe32b, 0x003eec9e, 0x2ef910b5, 0xb29bf942, 0xe32ff738, 0xfe32173d,
9141 0xc2a5443f, 0x5e4a1122, 0x7c860167, 0xf5f75d6f, 0x8f8adef5, 0x27c78b80,
9142 0x04f0fe1d, 0xdc3f2cc5, 0x4c55f0df, 0x92f80c50, 0x76a675bd, 0x499cff0e,
9143 0xef89f7c6, 0xdfcc9342, 0xa5d5342d, 0x7f2973e5, 0x765c1528, 0x4f5192df,
9144 0xe7b37e80, 0x7f52a62d, 0x96d0bcde, 0x06f05f34, 0xc3f467d7, 0xc9ff3ca3,
9145 0x80dddf60, 0xfd933974, 0xf79843ea, 0x2f5172b6, 0x0e79e3f9, 0xd4487eb3,
9146 0x3a2f3df9, 0xb3d68f3c, 0xebdeb8d1, 0x4196dae7, 0x9a6dd621, 0xf3e3b2ef,
9147 0x61af3173, 0xfd3f0a70, 0xc79f3101, 0x96a323eb, 0xa7306322, 0x41793ce9,
9148 0xda3676bc, 0x9e454361, 0xe4b643f6, 0x2e5553f9, 0x440caebe, 0x82f68d45,
9149 0xc13ed2a6, 0x79dff299, 0x55abf530, 0xff21570e, 0xa3b639de, 0x0ea39f94,
9150 0x3f7e78f8, 0x77d75b87, 0x21e85a05, 0x60055fd4, 0xfb0bf9b6, 0x517033c3,
9151 0xbc214e68, 0x05b2ca6f, 0x4af7aa34, 0xebf8de74, 0xbed03320, 0xc1326fe9,
9152 0x0a6074d7, 0x5aa915e5, 0x27464598, 0x7e44c9e6, 0xf0efbe82, 0xe44df661,
9153 0xd55d36bf, 0x9188de77, 0x3a85ab3f, 0x370fdfb0, 0xa6dc69da, 0x7de992e9,
9154 0xeabad681, 0xde51c010, 0x4bf14e96, 0xe40dd365, 0x0e3ea97f, 0x12e3d34f,
9155 0x3c112c1b, 0xe1eece3c, 0x7c3c00f8, 0x2670f105, 0x4d91f858, 0xafbc349f,
9156 0xbce950c9, 0x711490e8, 0xfc3a6d8e, 0x3a2691c1, 0xc3308de7, 0xf6fc6f2d,
9157 0x3f9843aa, 0x807a7cf2, 0x2e3ea4a4, 0x779e6ae8, 0x1bfcf673, 0x1aed04bf,
9158 0x1e19935f, 0xc277f0f9, 0x91f34f1a, 0x7824d1a3, 0xf006e9d7, 0x957e436f,
9159 0xf9a6cd37, 0x2f7a0a16, 0x3ae37a07, 0xe685b3e3, 0x6d73fd10, 0x9d6be70c,
9160 0x07a10ec7, 0x8579719e, 0xf97396fc, 0xf51d2df3, 0x73d204c4, 0x73ffd86d,
9161 0x73f694ae, 0xdd892b9b, 0x517ba975, 0x1c7617aa, 0xca0e52c2, 0xd427ee01,
9162 0xcfda370d, 0xe27f1fa0, 0x72cdf832, 0xb04bd7c6, 0xe1d94bdf, 0x65a04ab5,
9163 0xeda5e178, 0x90cfb434, 0x0cfb750f, 0xe71479e6, 0x9e8b0bf9, 0xa3f5e837,
9164 0x4499e6c9, 0xed8ebfaf, 0x9e397e4e, 0xbd027ed4, 0x8e64764e, 0x65ff5c9a,
9165 0xd47a71a4, 0xf946557a, 0x97f62985, 0xedc9696c, 0xdfeb54c6, 0xa290fca5,
9166 0xc07ee681, 0x847f216e, 0xdfb4ab95, 0xcd83f675, 0x3cc70ef7, 0xf288ad21,
9167 0x93f55383, 0x04c976bf, 0x22bfcf81, 0x9dfc741e, 0xf015e0b3, 0xeba4d7f9,
9168 0xd3e03564, 0x4b27c266, 0xf47b0cbb, 0x32bb9fd3, 0x16ea179f, 0xe0758778,
9169 0x16075a2d, 0xf18a59bc, 0x7f379597, 0xa7c0eb44, 0x39a1671e, 0x0fc7a08e,
9170 0x21df9c60, 0xfc17ba9e, 0x3b7dc44d, 0xf8d95e29, 0x17ba08fc, 0xaeba66af,
9171 0x749cea4f, 0x117072ee, 0x2ecce7d1, 0x3ce11047, 0x66e3c593, 0x3a4d7667,
9172 0xf799f184, 0x19670fea, 0xd9e67ce9, 0xe876a5a3, 0xa3ceccef, 0xf7e90aa5,
9173 0x9ddee9a8, 0x2abf0b9a, 0x3f5e7f45, 0x77c7d0df, 0xd3ebe4ce, 0x3f3f8275,
9174 0x5e301e29, 0x0a51fb4f, 0xbbed187b, 0x9b54bc3e, 0x499c15cf, 0xf114b37f,
9175 0x0eb97800, 0x43d3aee9, 0x332b878f, 0xdc60663a, 0xfc0bf7b6, 0x2e8da93e,
9176 0xe352a71e, 0xcd769875, 0xe35b879c, 0xc475a658, 0x3b50ef28, 0xd2c711d6,
9177 0xc41bd9d3, 0x7676a7ed, 0x5fb1e7e7, 0x7eef29ef, 0x06f567ac, 0xd0c7873e,
9178 0x06afe765, 0xbb7c03bd, 0x71fade71, 0xf7e94fe8, 0xd98af96b, 0xe0b1c2c8,
9179 0xe25e61bf, 0x2dcb8a58, 0xe607efc0, 0x71c41eda, 0xf37325a5, 0x6c5c8196,
9180 0x8794a8f2, 0x1c08cca9, 0xf37c23f6, 0xecef8214, 0x17df9961, 0x85b9cf32,
9181 0xfc67bf9f, 0xfd9b921e, 0xa7d4beb4, 0xc3e3e7e9, 0x2afeb885, 0x1a516cac,
9182 0x85a707d4, 0xd732c0ef, 0x10fc31d6, 0xf63ae77c, 0x609c029b, 0xd0bfc1e9,
9183 0xcabb3abd, 0x3f71fb42, 0xe4b777ba, 0xc7fac2df, 0x7e85ebfd, 0x48efcbd0,
9184 0xef31c775, 0xebbefeac, 0xec7c6166, 0xba3aae3b, 0x82fe05f7, 0xe7f41f4e,
9185 0x32cadf0a, 0x6a691c61, 0xa16b9cf3, 0xe3f7876e, 0xcd69fbf0, 0x577ed04d,
9186 0xaf1f3866, 0x534b71c2, 0xc10f0f9a, 0xb5bca33a, 0xcd29b4fa, 0xfe663011,
9187 0xe3cbcd35, 0x10b85aed, 0xf757d4e9, 0xa86ddd42, 0x85752d3b, 0xd579f5d7,
9188 0xe50bfc1c, 0xc3dcae95, 0xd9ca2def, 0x1bdf8f33, 0xee8f3ed7, 0x134e6b8d,
9189 0x9a63447a, 0x58563cf1, 0xf88bdf0e, 0x195e92ea, 0x8f48e5ce, 0x2f78a67b,
9190 0x59c39ee2, 0x06e3c51d, 0x62eec1e1, 0xbc78cbb4, 0x52f580b3, 0x8aebc7a9,
9191 0x61ca8058, 0x48e5442c, 0x55e54ad6, 0x68e5462c, 0x096541d6, 0xc032a5eb,
9192 0xe39632bc, 0x6cca8059, 0x59d1dd5b, 0x667f4fa8, 0x7c3a7d27, 0x8303aafb,
9193 0x44de9118, 0xc78d66b7, 0x656bd6e9, 0xdcbc1ad9, 0x3f50f828, 0x348d5557,
9194 0xdb62be03, 0xe87ec8f3, 0xdef63212, 0xf7045b26, 0xf9a3d963, 0x9c5abcf4,
9195 0x7e3eae47, 0xf7cdec80, 0x60f3c982, 0xbb8bc05f, 0x963ed33e, 0x3ed67f59,
9196 0x41be11aa, 0x39405f7e, 0x41708959, 0xa0ece6dd, 0x75f69773, 0x3ee907b1,
9197 0xb4ec67b8, 0x18555abf, 0xbd43b32a, 0xa061776a, 0x7a8720c1, 0x6655703e,
9198 0x96bc772c, 0xf5888f38, 0xdf825a71, 0x286fb657, 0x77fb7dc0, 0xf5a71ff7,
9199 0x85e987fe, 0xb69a9f34, 0x4dd86aa3, 0xca2a7efb, 0x7d39bbcd, 0x97d93af6,
9200 0x0640aecd, 0xfde9779e, 0x4b6fbf39, 0x94f7dfc7, 0xdf71975e, 0x283d70e4,
9201 0x5ee9b042, 0xf951f7a9, 0x953f7a8b, 0xb2f7ab3f, 0x4700f820, 0x04da9dec,
9202 0x30ce4f9c, 0x7bfbca2f, 0x432bd8de, 0x7cbe6227, 0xe601bf91, 0xcefd98d7,
9203 0xded013fd, 0x7401c80c, 0x75eeec0b, 0xf3b42513, 0xcf29f37c, 0xbc6d1ee5,
9204 0x4f008ff3, 0xe67012a3, 0x6b2fb8c0, 0xa02bb53b, 0x24fcfebc, 0xe5ffce27,
9205 0x0fcd36ec, 0xddc61bf5, 0x247dc5ec, 0x02e36fe8, 0xfa2ecfea, 0xf6c4ef1b,
9206 0x5a3f62f7, 0xa2fd9fa2, 0x677bbd7e, 0x543fbe36, 0xebee08cf, 0xb1b2da73,
9207 0xbd1f7fbf, 0x13f195ec, 0xba477ee9, 0x17caca2f, 0x66cb9fd7, 0xe6cbb041,
9208 0x41602b9e, 0xd393c7a0, 0xf942aeeb, 0xd1bfd357, 0xa0fd04ec, 0xa255d614,
9209 0xb7a6f0be, 0x1f413b34, 0x9d01b06c, 0xa59f54bc, 0xcc70095d, 0xb181fae4,
9210 0xa432e696, 0xc62bb03b, 0xae8fe1e3, 0xfa82399b, 0x7efe1ae3, 0xd79160e6,
9211 0xf7e3ed00, 0xed0b31bd, 0x918a6ab2, 0x66e6b630, 0xa479f746, 0xce2a37b2,
9212 0xc1a8b3a5, 0xba61fbae, 0x42a7e49f, 0x4c3ed089, 0xbd0f39c5, 0x5cfefcbf,
9213 0xfd8873a6, 0xfde8d3fb, 0x7e74abe1, 0x679c520a, 0xdf2273cd, 0x881c15c3,
9214 0xd763beed, 0xb8f60fe7, 0x57d5f113, 0xcc3e288f, 0xffe7d043, 0x49ffcd28,
9215 0xef1ef135, 0xf7d81cf5, 0x7fd1059e, 0xea26923e, 0xb7922791, 0x2fb4b34f,
9216 0x34cfebd2, 0x1fd69ccf, 0x12b8ef9e, 0x57b42775, 0xeafa3bce, 0x9b06df08,
9217 0x7d2cbfa5, 0xfc69e7fc, 0xb45942aa, 0x5052f7df, 0x723bd031, 0xabef19a8,
9218 0x78ef454d, 0x9b9b2fda, 0xae23fbe0, 0x5fad1950, 0xbf5a3337, 0x0602ee50,
9219 0xe34f183d, 0xb9c555fe, 0x247a2651, 0x7a6250e8, 0xd2e4127e, 0x7cbb4fb8,
9220 0xfe745dc7, 0xe7e69e24, 0x3f08b0fd, 0xb168f557, 0xfff67f69, 0xe169f1c3,
9221 0xc7014b28, 0x1c33bfcc, 0x3fe49a57, 0xd368c701, 0x387efff3, 0x6380a466,
9222 0x1c153ff6, 0x2f457b56, 0x2bda2fff, 0xcabda357, 0x9d6c41e3, 0xf7fdce8d,
9223 0xe52a2a64, 0xc99369ef, 0xe195204e, 0xdf68eea7, 0xcd779f2f, 0x8b1c7bfc,
9224 0x615f9db1, 0xd478ca2d, 0x11671157, 0x857f87ee, 0x0fcf03f7, 0x8683a02b,
9225 0x1f693a64, 0x5434bfdb, 0xfe05fb85, 0x5435e585, 0x546eeb7a, 0x587a5f70,
9226 0xefb438ef, 0x4fd96b36, 0xde933337, 0x2fbad08b, 0xb6bb22ad, 0x9b279be3,
9227 0x6078df71, 0x68c3dd5a, 0x93914b07, 0x24a787cd, 0xd6f5cf7b, 0xd14fd32f,
9228 0xce9d14ba, 0x293f42ae, 0x0ec68aea, 0xb59a3d20, 0xf0a3d200, 0x2296d19b,
9229 0xdaf72ba8, 0xaf000d02, 0xbedd1992, 0x1e57e005, 0x4d764e18, 0xb61ff514,
9230 0x6e89407f, 0xfa9dfcc1, 0x1bb7c500, 0xa5b47d85, 0xf317ae69, 0x3099ed98,
9231 0x7ae5204b, 0xd097dd7b, 0x7534d75e, 0xae0a73bd, 0x01968107, 0x01f75e5e,
9232 0xb1164f5c, 0x78a66722, 0xb46feb0f, 0x1af20d81, 0x6fe97eea, 0xbab79f32,
9233 0xd70d383e, 0x8c95d5f9, 0xf7087f7f, 0xd2cc9e89, 0xfbdfc2f1, 0x4f5c750d,
9234 0x7d448694, 0xeb7bcc26, 0xf7df5c63, 0xd1ebaba6, 0x44f987de, 0xc31b8ec8,
9235 0x630e93e7, 0xf4fe007b, 0xbeb44571, 0xf17d6146, 0x0a71fbe0, 0xf7d2f79d,
9236 0x6c639c83, 0xed841fb4, 0xc2ea7ee9, 0x742fda22, 0x388163ce, 0x69e703e6,
9237 0x09517f7c, 0x3b3cc4ce, 0x04bf1f77, 0x8aa6ce29, 0xa26d12fd, 0xad205f39,
9238 0x99b45be9, 0xfcda369e, 0x5ccc39dc, 0x9dc0b077, 0x60ec8f74, 0x2681be4b,
9239 0xb00687f6, 0x1457e841, 0x6c3622db, 0xca85da07, 0x76df7851, 0xec811e31,
9240 0x0c58faa4, 0x31e31691, 0x0c1d3f2b, 0x3282c09b, 0x6486a38f, 0x698e3bf4,
9241 0x07947ce1, 0x66e2269f, 0x8dbf7883, 0x36ff61a1, 0x8ff14fcb, 0xf5efb47c,
9242 0xb379c6fa, 0x4a91fe29, 0x889a22be, 0xec36dee7, 0xce9af7a2, 0x19100738,
9243 0xc68e6ff4, 0x6f6b81f3, 0xd779f7e2, 0x947ee1ee, 0xe8b27efe, 0x9c4536b7,
9244 0x327ae413, 0xd63df9c2, 0x485edb39, 0x0e7cacf7, 0x75f356e9, 0x6b4fc31b,
9245 0xdfb9c7e2, 0x53b7b166, 0x158da1e5, 0x5f9f4dfe, 0xf218fc23, 0xc2ce902d,
9246 0xd2ea597f, 0x4fbe6ee9, 0xa247bf42, 0x4f4dc847, 0xa8c44ab9, 0xea098345,
9247 0xe9853739, 0x3172821e, 0x654df29f, 0x2c1fe8b9, 0x8225ffdd, 0x79c6d973,
9248 0x5e4bde2a, 0xe13171be, 0x52ebc745, 0xa7f07f8b, 0x8d1709d6, 0xb4f6e9a7,
9249 0xfee81fee, 0x484fd580, 0x47e7fdf5, 0xcc3a27ee, 0x3ed195f6, 0x3c1affef,
9250 0xe07586cf, 0x67de20b6, 0x473ffba5, 0xf98eecec, 0x73655cf8, 0x2ec3f9f0,
9251 0x54560f7e, 0xd87583dc, 0xdf859c5f, 0x7f3e29cd, 0x3b2f9625, 0xedea1a63,
9252 0x7a3e3f97, 0x4a0ff903, 0x8d3cc34c, 0xfff70a33, 0xe7633af4, 0x0bf38a64,
9253 0x7eef5fbc, 0xb867ee95, 0x74f7f0be, 0xfdc6bd3e, 0x3f639d2a, 0x3ca766d3,
9254 0xb15debbb, 0x1dfde36c, 0xcdee17d7, 0x747e18be, 0x8088e1ff, 0x7bd170f7,
9255 0x571a6105, 0xb70473e4, 0x53d2174a, 0xe7cd6f7f, 0x3e98ecd8, 0xa669e513,
9256 0x2ff9e926, 0xcd97c88d, 0xfc9387f3, 0xe89bcf64, 0xf39bfde4, 0xc791b24d,
9257 0x47cfeeae, 0xef59ff3a, 0xf1235925, 0xe0a9ef73, 0x19b405aa, 0x3dc4d1d7,
9258 0xef3d2a25, 0x0e86f116, 0x54f6fb1f, 0xac799790, 0x75fb4ece, 0xfd177ee2,
9259 0x4179975e, 0x2242fdcb, 0xd6242aff, 0x5e4437c3, 0xa7e63cd5, 0x376817ef,
9260 0x75bf51d9, 0x6e60fb88, 0xf1bb6162, 0x425ea67c, 0xb6bd26bf, 0x7eb98e60,
9261 0xb75cc873, 0xe7a8a3de, 0xdeb4fccd, 0x89ef153f, 0x999dfbd3, 0xd3ec3f42,
9262 0xb03c5d3e, 0x67507e2f, 0x71e81f8e, 0x43cc1abf, 0x1e18fda6, 0xe4e59bf7,
9263 0xbb8f4fe3, 0x56a37f68, 0x16e33753, 0xc5b3ea0c, 0xc6967cf0, 0x8bc60df5,
9264 0x59a29ef0, 0x6f1f7e8a, 0x80e7bf54, 0xf909cbbe, 0x0ddc6336, 0x5ee930f3,
9265 0xdf1e70ab, 0xa0721157, 0x0ece19c7, 0x5e6467f3, 0x4db5bf84, 0xba9ee9b2,
9266 0x13b895fb, 0x00fee0f9, 0xf04ac3cf, 0x6f14d471, 0x49a936d5, 0xebebb7ef,
9267 0x9e0af407, 0x3ee0724f, 0x01f7d02f, 0xc635e825, 0x887b3423, 0xf4f776ea,
9268 0xf2f23f0e, 0xe3661b03, 0x988d1055, 0xca760c1f, 0x6957da3b, 0x03db767d,
9269 0x621ef187, 0xc7e6dbb7, 0xb341b8f5, 0xa357bed1, 0xefeb49cf, 0x8bdaa97a,
9270 0xebf7a4fc, 0xae0854ee, 0x06515ab3, 0xabff08bb, 0xda334fe0, 0x87df31af,
9271 0x9e37dff5, 0xddfaed46, 0x0a7075bf, 0x131d59c5, 0x17bc016d, 0xb1ac1d5c,
9272 0xcfc9243f, 0x936f1bec, 0x549fb492, 0x77494ff8, 0xf507a77b, 0x7c96b743,
9273 0x2dc8ba3f, 0x3fc2fb89, 0xb22c3ca5, 0x5f33c3c4, 0xefc71e1f, 0x8a1bcea5,
9274 0x8a3e490b, 0x2b6f20dc, 0xccf59dc7, 0xe47c93f0, 0x2e1c7cf2, 0xabda8db7,
9275 0x6c379e4e, 0x152da7be, 0x4978ea3f, 0xc8e50785, 0x37e78c5d, 0x7f719986,
9276 0x43c52dce, 0x4e32d794, 0xb8afba49, 0x51a1e056, 0xcabf1009, 0xb89c86d7,
9277 0x4f64340e, 0x7ffee277, 0x28cfe2b3, 0x88f0fb44, 0xd66e30cc, 0x8dcb35e4,
9278 0xfb88b65e, 0x6dbae745, 0x7559ef49, 0xeeff92da, 0xbe6e5dce, 0x9fecb44e,
9279 0x52dee742, 0xd46809f1, 0xa5a5d910, 0xf3ef178a, 0x5e1ced96, 0x04fc8a57,
9280 0xfc54dfbd, 0x177eef71, 0x61993dff, 0x659f3a4e, 0x9c49af1d, 0x78026bc3,
9281 0x1a6dced0, 0x6c7841dc, 0xd178a89a, 0xd3f9768e, 0x5ed0d398, 0xef489cc9,
9282 0x78d96acf, 0xa5359026, 0x4f1d3be0, 0x9f6db9d7, 0x16c2ff8d, 0x0df9cbfe,
9283 0xfc0dcbc5, 0xff193ab7, 0x983c875d, 0xde37e1c3, 0xf264a9ab, 0xbc2b3ffd,
9284 0xde3e7e7a, 0x9fcc6e87, 0x845f052a, 0x1c8e8dc7, 0xec0c3e9a, 0x303abedd,
9285 0x86d78c38, 0x73fb8e7a, 0xd133a771, 0x647dd1be, 0x75429376, 0xdf07df3a,
9286 0x6cf7f105, 0x39fdc4da, 0xc1f3a835, 0x45beaa8f, 0x9f585e63, 0xbb2ccaef,
9287 0xda51e717, 0xab9f8071, 0xf9a1cb69, 0xadef8b57, 0x9c3dc6f0, 0x2f1ee39f,
9288 0x82c71995, 0x77dfc03f, 0xf348eb68, 0x2db71c63, 0xd639db8b, 0xf5bbceef,
9289 0xb156873c, 0xfb49d1df, 0xf8333912, 0x3bbbd47a, 0xfea3fc9d, 0xf7e069f8,
9290 0x8dec5869, 0x94367bbe, 0xd51dd938, 0xc7d0eec2, 0x82c45d2f, 0x2f4bbbf8,
9291 0x2716b1a5, 0x843b87d8, 0x2df6321c, 0x780a5fb1, 0x7c6fb804, 0x3fed1471,
9292 0x04bdfde9, 0xcfb612cb, 0x912cedcd, 0x3fc0cfe4, 0x6fba6631, 0x39d9c6ad,
9293 0xbe47f51c, 0x46edde1c, 0x6758e33f, 0x5edbd62e, 0xe0f64d3d, 0x73f0f0a5,
9294 0x51c2bf81, 0x571e7dba, 0x35d6718d, 0xf45d95cf, 0xc6355d7c, 0x50fe0c43,
9295 0xe9b36f02, 0xa17ebf79, 0x1fe8bf3f, 0x8d392be3, 0xa09ae9c9, 0x4c8b3e4f,
9296 0x0a7d18b8, 0x25d23de8, 0x1fd39a3a, 0xde60f9f7, 0x607fd764, 0x09ef27d1,
9297 0x9f4ffd7a, 0xae26366f, 0x40e53f01, 0xf188e789, 0x9fbc5bde, 0x6fc794f7,
9298 0x15b27f5a, 0xcb3553f6, 0x2c6987c0, 0x8dfa84e2, 0xd167ce8e, 0xfaebd3fe,
9299 0xc7c11bfb, 0x39fd8c9a, 0xf2e91cb9, 0xb928bd5b, 0xedcb7edc, 0x3c0efc21,
9300 0xbee0f716, 0xfc628bc7, 0xe81fd8b6, 0x76b6b3be, 0x3d4fe199, 0x96145c0c,
9301 0x4e825ac3, 0xebe1fbfd, 0x60ff2e8f, 0x0b728e4e, 0x4a3947f9, 0x6bfdcb5f,
9302 0xdfe8cf5d, 0xcfb47915, 0xee8f1f66, 0xc8ac4e77, 0x75724393, 0x05f44308,
9303 0x7bbdf96b, 0xa2ff0b6f, 0xd39fdc5a, 0x18c7dfa5, 0xde33691c, 0x5a76f5bb,
9304 0x87fd1441, 0xe5f787b7, 0xed1ae609, 0xf0576aaf, 0x1bbef0df, 0x7ca65476,
9305 0xc1bc0fd5, 0x9a2fee0c, 0x712ea7fd, 0x3fee8eaf, 0xffdf8b35, 0x7f398362,
9306 0x1dd24b37, 0x91ffb0f3, 0x72af749d, 0xa75f2e6e, 0xcc7f73f5, 0xf64259d7,
9307 0x54abe0b7, 0x0f39f77c, 0x83d40f97, 0xad7ca491, 0x0dbf9e9a, 0x70c460eb,
9308 0x53cee84e, 0xcf1ce8c3, 0x78a01612, 0x749692e6, 0xbde03116, 0xf9e4f1ed,
9309 0xbe848b35, 0x4ef7136f, 0x5e7cd1b3, 0xf3e7be09, 0x1c975b68, 0xbe0c9eee,
9310 0xfb89b70e, 0x6094dbc5, 0xd529e23a, 0x078fa13a, 0x3ca74b04, 0x6f07f387,
9311 0xe6fd71a0, 0xfa257f71, 0xb26ff17d, 0xc0037df8, 0xd827d0a3, 0x9b1e1bfe,
9312 0xe2bebe49, 0xb3faacf9, 0x24feb4cc, 0x9e933ef0, 0x927d767f, 0x927d0979,
9313 0xf251ef4d, 0x3a78ced0, 0x7b75efc6, 0xce6db0fa, 0xdb742496, 0xaaf4e424,
9314 0x3fee851c, 0x76e7151b, 0xb976aa40, 0x639ee259, 0x7c2b4781, 0xf9c9c5d9,
9315 0xfe0ca5e3, 0x7e74f57d, 0x1bde334f, 0xb285f38f, 0x75fd0020, 0xf422d74d,
9316 0x6fe25ffc, 0x7ab49c62, 0xbf8fc3a7, 0xd3b5d7cf, 0xa27a8155, 0x62a3a76b,
9317 0x7e9fd68b, 0x3b663cbb, 0x4ccf99f7, 0xf58c7fbf, 0x705174a0, 0x5fd1cfc2,
9318 0x3ee99768, 0x927f6b49, 0xecf34dc7, 0xec29e7d3, 0xb9b9afb0, 0xe74ecd3e,
9319 0xf117b174, 0x572ad475, 0x1d3c8547, 0x2d90f215, 0x75876bee, 0x92eb89c9,
9320 0x0217eede, 0x2cc393df, 0xe7c17de9, 0xb12e02dd, 0x76bc3c2e, 0x04c3fb06,
9321 0x08ce7dfc, 0x7eda19c5, 0x7ec02f13, 0xdc78cabb, 0x16fdfac0, 0x998c67c1,
9322 0x3349eaed, 0xb9e612fd, 0xc5e498b0, 0xfdbd7c7d, 0xb7bf18a4, 0xd3b9fff8,
9323 0xdbc5ecfb, 0x807bbfc8, 0xf49a2eff, 0x81eb8a53, 0x61b4170d, 0xc18fd15e,
9324 0x5ff8338e, 0x1de8b2bf, 0x0baf3c2b, 0xefc4da78, 0xeb8d3287, 0xf55d2b61,
9325 0x779f4c75, 0x1cb300f6, 0xd7ff82c8, 0x9647328a, 0xb9743c68, 0x7d7c591c,
9326 0x5cc4f9e6, 0x49d2e24f, 0x1e5859cf, 0xbcaf7003, 0x90e6fc43, 0x95dcef88,
9327 0x31ef3e19, 0xe9da3df0, 0xbb097eb4, 0x6fdc4dbc, 0xa889dba9, 0x466bc74f,
9328 0x0e0223b8, 0x4ad7d71b, 0xf30d7d72, 0xe2a7bf10, 0xf6127ea6, 0x262bb706,
9329 0x166dfc0a, 0xb25f51e7, 0x3fb226b1, 0x39749e04, 0x9661951d, 0x7f8ca2d3,
9330 0xacdd390e, 0xa4727cf2, 0x787d325f, 0x9427ed1e, 0x71c16387, 0x4572c798,
9331 0x5fa00b48, 0xff31da5a, 0x0cf1e600, 0x943f83df, 0xe1e39093, 0xbfb19f82,
9332 0x2dfc0645, 0xf09b70c8, 0x7f8cf9f7, 0xf877bb0e, 0xdf37d631, 0x7d7a0cdb,
9333 0xe5c68655, 0x942ffc00, 0x9a7f8a83, 0xe00e86f9, 0xa06aae39, 0x9d0caa3b,
9334 0x8b62da3f, 0x3ed0b9d7, 0x6802c63e, 0x16c7775f, 0x7f00c6db, 0xf6e26f74,
9335 0xdf9e9f63, 0x7a05f1c8, 0xf97a8639, 0xf4c1638a, 0x275f50d1, 0x458ae3f8,
9336 0x14e7df8c, 0xcfd14773, 0xce44f5d6, 0x7033bd4d, 0x7a6577df, 0xf0cb835d,
9337 0x3b7dafbc, 0xe84c2fb4, 0x37d46a9b, 0x7df6d4fe, 0x8d3a466b, 0xe209eb87,
9338 0x733a5665, 0x979e00ba, 0xee32230a, 0x4574be6b, 0xe7bc78e1, 0x785a50fd,
9339 0x7ef86af4, 0x0e3e1cd2, 0xaf44776b, 0xd2ff1248, 0x88ae75f5, 0x7c8ae54f,
9340 0x5e34dcef, 0x45f42c7e, 0xc1f39783, 0x9ebcbdaf, 0xcf1e49eb, 0x17ef11ea,
9341 0xdcef5cc8, 0x2edc9657, 0xc67c6589, 0xb24063f8, 0x1963e3c6, 0x6f9ee239,
9342 0xeb5f425b, 0x7c4273fc, 0x2edf8fa7, 0x9cfcb5e6, 0xe59fe264, 0xcdf11d4a,
9343 0x3d0a73f2, 0x1522e5d7, 0x79fbe9ff, 0x78e11d9b, 0xbe7bd406, 0xc60961fe,
9344 0xe9ef0a0d, 0xf848fbe2, 0x5253407b, 0x1ebe87cb, 0x3d06f4e8, 0x0df186df,
9345 0x2713f3d0, 0x18f43ad3, 0x9c85975f, 0x1ff4ec1a, 0xb659efe0, 0xd4555c75,
9346 0xdf6ba060, 0xfee0197a, 0xd95d758c, 0x57c4c980, 0x89d79ea7, 0xa3ef2ccf,
9347 0x25e1d852, 0xbc3b577f, 0xc93c63b4, 0x578112ed, 0xc7a6de3d, 0x507b18b5,
9348 0x13f731f8, 0xe4cd277e, 0xdff80df2, 0x9a3ff021, 0x7dbbffe3, 0xec95bff8,
9349 0x2f2e5684, 0xa52b9db9, 0xfa2f9262, 0xa4ddff4e, 0x52afd3c2, 0x2f78e77e,
9350 0x13ffe7f7, 0xc9555084, 0x00008000, 0x00088b1f, 0x00000000, 0x7dd5ff00,
9351 0xd5d47c79, 0xcefdf8b5, 0x3324b677, 0x5f64ccc9, 0x25849308, 0x2126126a,
9352 0x26504109, 0xc5116109, 0xfb094049, 0x515983b0, 0x2fb5696c, 0x4a444103,
9353 0x505d8bdf, 0xd101da94, 0x101ac55a, 0x83b06034, 0x6795622c, 0x05b054a4,
9354 0x2108ee3b, 0xf16b43c9, 0x3dde5a57, 0x999bdee7, 0x006677ef, 0x7e7ebe7d,
9355 0xdeb8ff0f, 0xdef7cbb9, 0xfb3dce73, 0x3ab3c9bd, 0x21094b25, 0x0b62a21b,
9356 0x99941c48, 0xc84b125e, 0xbd3e0988, 0xe90844dd, 0x95242448, 0xa423aefe,
9357 0x475aea0b, 0x2423c932, 0xbd389ead, 0xbed19eb4, 0xfad2d25f, 0x8637f865,
9358 0xc94ad310, 0xfe9e30b9, 0xd3b694be, 0x3a166ddf, 0x9ed03130, 0x1609ebcc,
9359 0xd025213b, 0x820d27cf, 0x936f36f9, 0xb4be74b4, 0x62908976, 0x2f13365a,
9360 0x4b8c0ac9, 0x99efb073, 0x01695e1c, 0xbb48dfed, 0xac849191, 0x59e754d3,
9361 0x14996812, 0xbfa568e3, 0x07bab06d, 0x4fea7ec0, 0xda667cf9, 0x2ea9c465,
9362 0x7b8e9bad, 0xb4cceac2, 0x63f60624, 0x24692d97, 0x53989087, 0x366d9d6c,
9363 0xfb05d732, 0x174cfe23, 0xc63f240c, 0x15b211f5, 0x93289bd7, 0xab46c423,
9364 0x2f7e87d0, 0xd6ee7569, 0x7d6052f5, 0x6ee23649, 0x49496da7, 0x84d3bdc4,
9365 0x2291d7fd, 0x7048d7da, 0x87ab493f, 0x059f5d6c, 0xde7179f3, 0x36d71caa,
9366 0xf92abdf8, 0xfa56a2ba, 0x9f06ce7b, 0xb71d3e76, 0x0266b377, 0x2bcc53ec,
9367 0x0916d1ca, 0x8c7dd1c7, 0x7d89fd80, 0x9289fba8, 0x5bae0f10, 0xb345d3f4,
9368 0x5bf685fd, 0x4cc6f385, 0x6d0df060, 0x2f6c77ff, 0x0cc265ff, 0x1afd6f58,
9369 0x0148313d, 0x75613ff8, 0x4d7002dd, 0x0122df6b, 0xa68c3e6c, 0xf02c3474,
9370 0x29a30fdd, 0x76b0153d, 0x87f3853b, 0x79474a7a, 0xb48a3a01, 0xb295fafe,
9371 0xa0f0e173, 0xe23d1afa, 0x2c9e8b69, 0x5e0bcf6d, 0xdf5c6adf, 0xcb068b22,
9372 0x2cd756a3, 0xc7634f80, 0xfbc07ac3, 0xe81f6db2, 0xcef857dd, 0xee91c2b5,
9373 0xe296957f, 0xb25daebd, 0x4ae92818, 0xe81392ed, 0xe8d6bea0, 0x6fd47805,
9374 0xd64b7467, 0xa183bde8, 0xa7c3bede, 0xf7e9eda1, 0xfd321d3b, 0x0efb6eb9,
9375 0x7c105169, 0x12bdebd3, 0x59a86bac, 0x1e9f2b9c, 0xfe8a95cf, 0x4578510f,
9376 0x1c3bba51, 0x5a463c45, 0x3c9b9776, 0xb76f8512, 0xfd0f5dce, 0x1c6353ba,
9377 0xf5efda1e, 0x488fe31d, 0x779adcf4, 0xae507c1a, 0x314d6cd3, 0xd775f6d2,
9378 0x41ad1deb, 0xbad36774, 0x6b38c176, 0x8ab1d982, 0x206eca7e, 0x9c131645,
9379 0x47fe2577, 0xc5cecfdc, 0xa32c4b6e, 0xe08a4223, 0x316e3c5c, 0x82893d63,
9380 0xf7d28cbb, 0xd75b1d61, 0xe1e8c24e, 0x836b9c52, 0x23e3bf05, 0x3ade3a0e,
9381 0x3a979d81, 0x7e891fba, 0x2ef36eaf, 0x623927dc, 0x6fa7b843, 0x75bbf097,
9382 0xb9e0b7db, 0x73bb3ace, 0x2ffa1ebf, 0x2451a525, 0x1b9cce98, 0xd5efcf83,
9383 0x426235f0, 0xade81ebb, 0xf2a1f38e, 0x3e936e5f, 0xafdfda0a, 0xa3c2322d,
9384 0xfdb6f36e, 0x647bf469, 0xb60cb129, 0x13fdbf63, 0x06b5f7d9, 0x607fc412,
9385 0x9d6c799d, 0x8ff8828b, 0x3e187fd8, 0xaf585bf4, 0x41d754e9, 0x487c87c6,
9386 0x6afd628f, 0x7e7076bc, 0x3c4f4e38, 0x93debbf8, 0x1df3a76b, 0xf9c68ece,
9387 0x73805f04, 0xa5f9c35c, 0x6213d686, 0x5a0eb9e8, 0x9e6f588f, 0x82d3a2b5,
9388 0x3842e870, 0xe2d66c34, 0xaef4abfa, 0xce83cb41, 0xb9f9efc3, 0xfbda6d79,
9389 0xfdfd3f7a, 0x83bf2fe7, 0x936869f8, 0x48cfc09c, 0x3bfa3bdb, 0xbfac01f2,
9390 0x21124991, 0xb7fb0893, 0x7a3bf771, 0xd27dfd3b, 0x86bf862e, 0x0bb43b5d,
9391 0xccfa014c, 0x1cdafb3a, 0x7686b3a0, 0x00928903, 0x582eee7f, 0x054e9a8f,
9392 0x8ddf043c, 0x0998cf84, 0x0f128f8c, 0xcf485f3d, 0x731aacee, 0x8a5f6f80,
9393 0x353a30d3, 0x2dbbdfb1, 0x1fa01eac, 0x974007f7, 0xd78ed155, 0x15545ce0,
9394 0x02568e49, 0xfb863ceb, 0x7064a848, 0x754f5e0c, 0x997e647e, 0x85e5cf18,
9395 0x63599fd6, 0x7eaf9c0e, 0xf7c7cfbe, 0xfc995e02, 0x49dfb1f0, 0xb03f2bb6,
9396 0xd2de356e, 0x0ff612ad, 0x01174f43, 0x26b96a7e, 0xe3e82fd6, 0x0ab59bd7,
9397 0xeab061f9, 0x55833e71, 0x08dbeb8b, 0x7e72a1f8, 0xcb9d8ea3, 0x5e8cab8d,
9398 0xc7d31fe4, 0x9f28911d, 0xfbd0cf36, 0x99a43ca0, 0x87ed0f5f, 0xd7f7d8d2,
9399 0x43773469, 0x136add7d, 0x3a7c4569, 0xa044d68d, 0x4bc4589b, 0x6bdead7d,
9400 0xfcfcf3a0, 0xeabfc645, 0x012f263d, 0xba9ee83e, 0x8491c610, 0x8053c728,
9401 0xfd41f737, 0x7a50e61d, 0x6f63d3b2, 0x6a4fbfa7, 0xe04ce767, 0xa451f281,
9402 0x04bf212b, 0xf4f0035c, 0xc08dce2a, 0x0b38a5c7, 0x2cee5be7, 0x33dd7780,
9403 0x738fde51, 0x132eb7d9, 0xa2ab4ba0, 0xea91d4de, 0xa818d8fd, 0x00ffc1d7,
9404 0x52a76c1d, 0x83ae94ad, 0x765d33af, 0x6efb075f, 0xeb0ffa30, 0x4f4b6a28,
9405 0x8eb9e1f6, 0x2b75b744, 0x98fb4cdf, 0xa57743ea, 0x38a581bc, 0xa56cbaaf,
9406 0x78e52e3c, 0x9bcbc01f, 0xd41f8cac, 0x79e3b715, 0x19b8fbac, 0x0269b1cf,
9407 0x53a667e3, 0xc84d7e4a, 0xb2beb84f, 0xc557c701, 0x29938fb4, 0x257eabdc,
9408 0x64495a59, 0x2244b97e, 0x9fa7902e, 0x3b103e6d, 0xe97be00f, 0x8dfb8cb2,
9409 0x6c9dfb62, 0xfba8e765, 0xa4700a19, 0x093d66f7, 0x9d6bdfb3, 0x4b8ef88f,
9410 0x0e3af780, 0x95edeeeb, 0xf4a13f23, 0xce2679e2, 0xdcf7fc01, 0xf83f29f6,
9411 0x7bbbae84, 0x9b9418db, 0xa42ead09, 0x28c4be9f, 0x3f4a56c7, 0x20993209,
9412 0x6aafbc51, 0x8a3b103f, 0xb9fcfb8e, 0x8f204561, 0x9e75f117, 0x095e517d,
9413 0xebfd5970, 0xf6866e17, 0x0f14af3a, 0x99fbbc7c, 0xf813fd5f, 0x4d6dd2fc,
9414 0xd69149a0, 0xf7a77ee7, 0xef1a7ed3, 0x33fbf616, 0xf7e81671, 0xdf0f93f9,
9415 0x6d6ef00c, 0xb3f6c56f, 0xfac16e4f, 0xe17ebf6b, 0xf207ffd5, 0x80eb15de,
9416 0xdc5f677e, 0x77a9788f, 0xdfb09d6b, 0x71bd7448, 0x27c67ec7, 0x39c3ae41,
9417 0x4bfc65a8, 0xdfa0b5d0, 0x773d7fcf, 0xa87cb064, 0x12195d97, 0x38364ff4,
9418 0x5e50929e, 0x14389ca0, 0x7451b445, 0xd2d3afff, 0x792acb48, 0xe01d7ef9,
9419 0x33f18739, 0x790921aa, 0x7f431bed, 0xcc4c7dbf, 0x2f3bd416, 0xcf0833dd,
9420 0x3ba30c4d, 0xcf918f3a, 0x88798463, 0xf33ea096, 0xa875e676, 0xcd2952d7,
9421 0xce1249fa, 0x1ba6e873, 0x17b9c2b6, 0x6af985eb, 0x3abda1f2, 0xf889e403,
9422 0xe75f1d7d, 0xdf2668ba, 0x537e71ce, 0x075a6157, 0xa3e7b9e5, 0x8d3f016a,
9423 0x2b10ff7a, 0xd18f2fc0, 0x265643f1, 0x97dbea87, 0x384d1aeb, 0x9779e71e,
9424 0xf32829f2, 0x94fa79e9, 0x6bda579e, 0xf0e1e5db, 0x3e32dfbd, 0x60ca4d19,
9425 0x7d66d31f, 0x62fc0120, 0x75759af2, 0x58e7d708, 0x7052c53b, 0x760ae97b,
9426 0xfb74d47e, 0xcfc4d5a4, 0x69b73b0f, 0xec33aabb, 0x8e0cb7c8, 0x53fa41c1,
9427 0xab7752da, 0xcb7efe99, 0xa643b70a, 0xccf7b774, 0xb4e971b1, 0x695cebfe,
9428 0x2cabd238, 0x31ec7931, 0x561a77e1, 0xe88f9256, 0xcfc9dfb9, 0x68859275,
9429 0xe00a2c6f, 0xb44b4aa9, 0x1f7f8426, 0x7586b5f2, 0x636f5e5c, 0xbec624eb,
9430 0x1c6629cc, 0x16d1ba67, 0x671d0758, 0x2fbd6132, 0x907ccef3, 0x945a9e8f,
9431 0xae3d768f, 0x5fe0acf7, 0x3b3053c4, 0xa81fc03f, 0x7a06e6de, 0x7b33d24d,
9432 0xb563f805, 0xf2e6f419, 0x4092d623, 0xdacd1499, 0x6d9270d5, 0x3bae9db4,
9433 0x7ec4e6df, 0x857899e4, 0x07c48afc, 0x37fe391b, 0x40c5fe4a, 0x513d9e67,
9434 0xc6eba016, 0x1443fd9b, 0x53870976, 0x9e9ba70f, 0x0e5e8c3d, 0xd81e3469,
9435 0x37ada1df, 0x4295696c, 0xae50f1e5, 0x4875a79f, 0xda4bc016, 0xfe051ae6,
9436 0x0ab75ea8, 0x5c86caf4, 0xf7f514a9, 0xbfbfe58e, 0x291bd68e, 0xb8dea0de,
9437 0xaa4f9f8b, 0xc6ff42a7, 0xf085ea8e, 0x8984f4bd, 0xfd42590e, 0xad3a5c68,
9438 0x1293d637, 0x071bff38, 0xe3a4f738, 0x94f2243e, 0xd529e41d, 0x269e41ab,
9439 0xde3ea3e6, 0xfa86dee8, 0x73d5c937, 0xf510b7b9, 0x9994c6f5, 0x215f380e,
9440 0x2acf627c, 0xed1af7d4, 0xda288ed1, 0x7487527f, 0x4c77d337, 0x7247ad84,
9441 0x77927d42, 0x73d61794, 0x9447c05e, 0xf039aeba, 0x06dd9efd, 0xafeda1e2,
9442 0xf28f19ef, 0xf98bd05c, 0x75ca0325, 0x8122d69b, 0xc5ae7e5e, 0x4c1a3e49,
9443 0x9cb81fc8, 0xdbacf011, 0x7381a59e, 0xc3b79e72, 0x97127b3f, 0xc36bb487,
9444 0x67d21f42, 0x13dbd73d, 0x7bc2ce0c, 0xf427f082, 0x641d3528, 0xd35e18db,
9445 0xe0941f36, 0x73f1ab10, 0x6be252cb, 0x65bbeba2, 0xa637c6b3, 0x19abf500,
9446 0xe957f7c8, 0x742956c9, 0xc63621be, 0x5de2aa2f, 0xab27c085, 0xc11c99a6,
9447 0xda2aa9fc, 0xd20a89a9, 0x157108f3, 0x26763d83, 0xcff08cc9, 0xeac3d9b7,
9448 0x79f6a165, 0xb74fda14, 0x480a79b6, 0x155d6d36, 0x92e70b5d, 0xf21363f2,
9449 0x0f1d0b4d, 0x51d6fdf6, 0xbefb324f, 0xb14de715, 0x8ef9d859, 0x83371577,
9450 0xb5c7203f, 0xb331c982, 0x8e7edc23, 0x3e1e855a, 0x740350a7, 0x00e4d532,
9451 0xafe7f2bb, 0x6e91f348, 0xc260543c, 0x38af7179, 0x2bd99136, 0xe23ba00e,
9452 0xd5bea2d6, 0x86f2ecd8, 0xc7462ba7, 0x02ff548d, 0x15d29c3d, 0x83b1ade2,
9453 0xf7611fc9, 0xd6089f03, 0x12b9c577, 0x35f816e7, 0x37a08dd0, 0xf5af6e71,
9454 0xf3f0f67c, 0x1ff743d1, 0xbde69f4c, 0xafd72e8c, 0xfb4397b2, 0x09622afa,
9455 0x76d557b6, 0x1f0e1d90, 0x8c9fdbad, 0x823cc2f1, 0xbab06dcf, 0xbd60da66,
9456 0xab58df5b, 0xd4be0125, 0x21a1f7b8, 0x8ccfd257, 0xd19f365a, 0xa60de31b,
9457 0xb705231f, 0x0f4b08b9, 0x9598e7f0, 0xf723fde1, 0xcf4c4cda, 0x65fab6fb,
9458 0x7c05a49e, 0x5f32fd09, 0xe36bdf76, 0x08a525fa, 0xe992b992, 0xebc04997,
9459 0x8d6c1f81, 0x113f02f1, 0x7af5267e, 0x099cfcdc, 0x233b0abc, 0x7ff59629,
9460 0x359b9f98, 0xbc63dfbc, 0xf05fb20c, 0xee35d83c, 0x591c880f, 0xdf71880e,
9461 0x7c4bdf95, 0x3523c847, 0x41fac0fd, 0xaa7ec16e, 0x6bf722f3, 0x38edcfdb,
9462 0xe1ef3d15, 0xe016abe7, 0xbc627a08, 0xe700effb, 0x19c47159, 0xeb3ff14f,
9463 0x27a40677, 0x0437db92, 0x2d3ad0ec, 0x806c18f1, 0x1fd79d57, 0x78a6b784,
9464 0x6cd7be36, 0x1cf4c8f4, 0x6f778a5c, 0x153c7987, 0x3d03e1c4, 0x5f9487f6,
9465 0xbe24b9c0, 0x4d27e012, 0x700b1fc4, 0xdbbac5b4, 0xaee53e91, 0x3b53a84c,
9466 0xf3be00a6, 0x9fb30c48, 0xbd90defa, 0x2e3c2943, 0x3efffd18, 0xc2e7ae8a,
9467 0x87871c8a, 0xef7a73ce, 0x99ff779f, 0xfbbf3ef6, 0x7ec101b3, 0xeca346ac,
9468 0xea07c6d2, 0x6da9123d, 0xbb77c30f, 0x986fcc6c, 0xbbf08375, 0xbadea1f5,
9469 0x0c99ca22, 0xfb159f7e, 0xa4af93ca, 0xac5d37cf, 0x3f20de24, 0x0f1d135c,
9470 0x8e2e9ae3, 0xe643dfc3, 0x7c81f3a5, 0x4e98ba68, 0x77d9c33c, 0x30fc6f80,
9471 0xc0dbf19e, 0x3f6c4cf8, 0xf3fa51ad, 0x3c45e5fa, 0x422ed7c3, 0x1f6b8426,
9472 0xb5f6cf1a, 0xdf9d9b2b, 0x17924dbe, 0x2bc583ec, 0x82993ecc, 0x19fd3174,
9473 0x16c5a5f4, 0x0b134f8f, 0xb1f287fc, 0xa9c68861, 0xcc8f6a46, 0xf68cf2e3,
9474 0x7a068ed3, 0x1cf058f5, 0x9c39f9ba, 0xd7faf1d7, 0xac589fe0, 0x74d1c625,
9475 0xc746f99e, 0xfbfa74e1, 0xb1b1a627, 0xde162620, 0xe409253b, 0x66acf258,
9476 0x32122ff4, 0xa9fa02d6, 0x97cb4644, 0x0fa4ae63, 0x458f5169, 0xf074a27a,
9477 0x2faef16f, 0x1d021d04, 0xf187bacc, 0x49ffd135, 0x17f3869b, 0x1fbe1d25,
9478 0xc6efdf01, 0xe80afc57, 0xd738c1ec, 0x7bde703f, 0x5ff82bce, 0xfa7fe48f,
9479 0xe5d3a071, 0x2453c766, 0xc389bc74, 0x4bb0b7bd, 0xdef1fe0f, 0x44c8ffe5,
9480 0xf5f3b47d, 0x1ba7c093, 0x0c9f268c, 0x5d2ec57a, 0x03ec5fb7, 0x339c62e4,
9481 0xf38e9e3a, 0xfada383c, 0x9209a529, 0xfdc77f4c, 0xde144ed2, 0xbc191b77,
9482 0x5b778ddf, 0xee9113e3, 0x757d82e7, 0xb38f68c1, 0xfbe8bd01, 0x2632e3f1,
9483 0x3243f005, 0x74bc4acc, 0x997881be, 0x01ea746f, 0x2e9c0bfe, 0x38ace75c,
9484 0x8145895f, 0xf2f93c87, 0x078ed70d, 0xd3eb9f99, 0x730e5fe0, 0xb872861e,
9485 0xd1fa10fc, 0xa31a74f2, 0x6499d3db, 0xaf284ee9, 0x771d25a7, 0x8bd79b3a,
9486 0xef087d78, 0x37eac497, 0x5d3dba72, 0xbfa9fac0, 0xceff2773, 0x62cef1bb,
9487 0xe71d1380, 0x5ebe03d3, 0xbe82f28d, 0x8dd6f94c, 0x7c5e8cf1, 0x55be60d6,
9488 0xf80437dc, 0xc5096f61, 0xfacfdd1b, 0x13ccbef2, 0x19f657c0, 0x57ed5b2c,
9489 0xbe64dfc7, 0xc72d6fae, 0x958e541c, 0xe4d8e42a, 0x10c72678, 0x7a25744f,
9490 0x420d5fa6, 0xc87d20fc, 0x1b9f8ed7, 0xe9dc19a2, 0x478da979, 0x77cbe579,
9491 0x86f7f105, 0x044e7678, 0xad1d393f, 0x38dfe3c4, 0xfbc79c1f, 0x6616f1c9,
9492 0x32fa39ef, 0xb6d39e61, 0xbbff78f0, 0x8b1f1fad, 0x1967be81, 0x53c4e6fa,
9493 0xea93bb7a, 0xc422fa0d, 0x09eb0c87, 0x7cf34fb1, 0xdcf3857f, 0x8099b774,
9494 0xef866bfc, 0x589e2225, 0x7d97297c, 0x3d4f7297, 0x1f86afd4, 0x52a7d5f0,
9495 0xf4c9243e, 0x563c3643, 0x1aa71676, 0x16f3c16d, 0xee4fcfd5, 0xfa8f860f,
9496 0xbe38a7bb, 0xda4bc6d6, 0x0e8f014f, 0x737180e2, 0x3cc2f9de, 0x79c9d29b,
9497 0xa1a3d18b, 0xbb2dcd72, 0xbb7ec3d7, 0xea06f07f, 0xbef4a7bd, 0x30a66d21,
9498 0x13df7aed, 0xf681488f, 0x3d91bfb9, 0x778e7a7a, 0x62ff7575, 0xbbbfdd1a,
9499 0x39c0764b, 0xd7ffdf76, 0x7f4023a3, 0xc039d2e9, 0x75f2a0ac, 0xd1f61683,
9500 0x53b4f4cc, 0xcffc251a, 0x47694f7d, 0x46f1c33c, 0x33a40af5, 0xf14e0fc1,
9501 0x6212e5b8, 0x159fba41, 0xea15bb1d, 0x6e4be5fe, 0x7ce63885, 0xa4ec38e2,
9502 0xeeecfff0, 0x5e77e889, 0x2fc89c44, 0x1f7479e6, 0x05d3f306, 0x45f594eb,
9503 0xfd3aca6d, 0x92efd222, 0x73bfd547, 0xf865707f, 0x78d1daf8, 0xd39d27a6,
9504 0xcfdf6f87, 0x7cbdbfdb, 0x837881be, 0x7c8080f4, 0xd5dfc02d, 0x39021ef3,
9505 0xd390125c, 0x5d373e42, 0x8f308a8c, 0xb73f7f09, 0xdffafc38, 0xe9a37ce6,
9506 0x79e515a2, 0xfc04f8e8, 0xd8666a9d, 0xe9b5e04f, 0xc4f12a62, 0x3f42ea07,
9507 0xc0cb8c0c, 0x2c002a76, 0xf804c69f, 0x0b03f080, 0x2240fe3a, 0xdfb454c6,
9508 0xac7ae61e, 0x52fc00a5, 0xa7bc801f, 0x278f76f8, 0x12e9faaf, 0x3a97dde7,
9509 0xa01d9b44, 0x283ef573, 0x07f59c3d, 0xe24fb9f1, 0xae7809cd, 0xf0619186,
9510 0x73a7415d, 0x0715507e, 0xf72ffef2, 0xeb072657, 0x0e7efd63, 0xa897b33d,
9511 0x2dc85524, 0xf36b92a2, 0x2b1ca83a, 0x0862bd40, 0xf68f8d30, 0xb93e474d,
9512 0x80923890, 0x19f77b8e, 0xf81fd132, 0x5899e52d, 0x3ccf14cf, 0x1337d31d,
9513 0xf0d70e50, 0x64e94fef, 0xe8c68dfa, 0xe2fea1d4, 0x124b7624, 0xee4c989a,
9514 0xa5a2a152, 0x1d449bf5, 0x47d68788, 0x3048cdf3, 0x26ffae9e, 0xeef9925e,
9515 0x06573814, 0xec0caef8, 0x65029bc8, 0x1d8748eb, 0x4b9231ca, 0xf0c1d6cb,
9516 0x67348e3c, 0xd18d7f40, 0x89fd332f, 0xc60920ae, 0xbab1ef8b, 0x4cd7d799,
9517 0x116730bd, 0xe3326efc, 0x75f3d7f9, 0x7ca0490c, 0x246df60c, 0xc1b7d846,
9518 0xe31cfbe4, 0x54f4bc4b, 0xf52ed1d8, 0x03f41364, 0x02769344, 0xce9935df,
9519 0x16b3607b, 0x1ea09162, 0xbbe0b965, 0x337f008f, 0x90c33479, 0x009f5dbf,
9520 0xade96f7e, 0x28ffc0c5, 0xf3802d3f, 0xeb5db11f, 0xf05e7d43, 0x5f5f1b27,
9521 0xa94fe72b, 0xfec24054, 0x7e9fce65, 0xfc8c5e6a, 0xf6b88129, 0x14da7f03,
9522 0x53f9013b, 0x7ae37132, 0x156827e2, 0xa5d1267c, 0x6ad727ac, 0x23c87c55,
9523 0xdd52fac1, 0xe48ddfca, 0xc907ca14, 0x1cb94ae7, 0x2e4a768f, 0x157423f8,
9524 0x44f51cec, 0xb4fd78b1, 0x9aceb668, 0xbff31b04, 0xfdb8b145, 0x2101f4d5,
9525 0x017ad5ff, 0xb5da5629, 0x413d368d, 0xb512553f, 0x7ea187a8, 0xf4c09350,
9526 0xd03df783, 0x5f21f72e, 0x0bfdc13e, 0xaab82753, 0x77df14b4, 0x4ea391e6,
9527 0x724b2e5a, 0xba5026d7, 0xb9a47e99, 0x6bd69ea1, 0x3ef922df, 0xb18e165a,
9528 0xf8a76dd4, 0xecdb3b5d, 0x6beb4d58, 0x3dd48ccd, 0x97d40689, 0xda69c808,
9529 0x829345be, 0xf02691fe, 0xb47e52c7, 0x4011e216, 0xda098317, 0x593f54d3,
9530 0xb6e3a46b, 0xd658b7ac, 0xd58fc1db, 0x85fc0e37, 0x65888b7d, 0x3e73092b,
9531 0x4773d12e, 0xd424fcf1, 0x4e255e29, 0x6df7e26f, 0xab0e7bf0, 0x3b05298f,
9532 0xe9cbfd90, 0xfc0b0ca4, 0x4f2cb937, 0x5cb3a9a0, 0x39eb4897, 0x4fe81d63,
9533 0x8c4f9c26, 0xe7e1df10, 0x5ce05470, 0xaf217b60, 0xb87cea0f, 0xcbe6092a,
9534 0xaeee0e23, 0x58239c0b, 0x50fe85ac, 0xe0f1ccca, 0x09237c73, 0x2af983fc,
9535 0xde23f303, 0x43b6f2c6, 0x76bc59b3, 0x1fb7d684, 0x5e28f9ce, 0xd332f216,
9536 0x43be5525, 0xe8c8bfe9, 0x0edbb038, 0xb0c97520, 0x43cb52ef, 0x91fdf0ad,
9537 0x81e277ae, 0x52368daf, 0xd6cb40fe, 0x92c38732, 0x80d6fb83, 0x2747a9ff,
9538 0x0e3393e4, 0x11606b73, 0x9cd5fbf4, 0x96d6a696, 0xfb0c5edf, 0xec0992eb,
9539 0x5c1ca22f, 0xc1359329, 0x8be787f2, 0x09fbfa88, 0x207fbfcc, 0x21379c61,
9540 0x74f82e28, 0x7283d702, 0x8ff02e49, 0x2cfdf3a0, 0xf9775bd0, 0xbfce919b,
9541 0xff9f9db2, 0x75c39c3b, 0x3e72efa8, 0x8badf820, 0x274cc5e7, 0xa7c01d4e,
9542 0x01f28a2b, 0xbe563f5a, 0x34c0f90c, 0xdfdfc6e2, 0xa6f060ab, 0x7cc1d788,
9543 0xf5282653, 0xca5c3b8d, 0xb55ab4fa, 0x9ebf423e, 0x74eef814, 0x46bdb2b7,
9544 0x941397e8, 0xeface5fa, 0x9ca2b25f, 0xe1ba7e4d, 0x97f040f2, 0x8225d54f,
9545 0xe793b0df, 0x184a74bb, 0xf9e26a1f, 0x921d4d2e, 0xa9a5df22, 0x8903de73,
9546 0x8d2ef941, 0x77cb571d, 0x09c8fa61, 0xf83f779d, 0xa32c4fd5, 0x39dfa63b,
9547 0x0e22f3c0, 0x51445e42, 0x73ccfe80, 0x52909f98, 0x33d1fa33, 0xd00e312c,
9548 0x8a69d7ab, 0x2eb8afd0, 0xfff0acd6, 0xace55fae, 0x9fc27e82, 0xa65cf228,
9549 0x3b734819, 0x641d53f3, 0x8fcc5cf9, 0xb4f6e5e4, 0x7e124137, 0xc7e835e1,
9550 0xc4df9d52, 0x24f28278, 0xfa2e6671, 0x0b3b6b0b, 0x4b5fc18b, 0xb1fa12e5,
9551 0x1c7609bd, 0x442eeb5f, 0xa62dd73f, 0x683f18e9, 0x5da2dcea, 0xcfd00a68,
9552 0xc5dd055f, 0xbba01890, 0x4ed1ff7e, 0xdc8ffa03, 0xa06bebb2, 0xafbd7aaf,
9553 0x12e92880, 0x77248f7f, 0xebbc7096, 0x17d35c2a, 0x1ef4b851, 0xfec03bd5,
9554 0xe2058aa3, 0x563dc5eb, 0x1ada83e4, 0x4d7efc82, 0xd97e4139, 0x4ff985bb,
9555 0xbd2eb33e, 0x9afef815, 0xaa72826a, 0xe10e36c7, 0x0f788cbf, 0xa5b8e93b,
9556 0x053d299b, 0xb6bbfff1, 0xa4f5eb29, 0xfd78f91d, 0x44ba10f6, 0x56f824be,
9557 0x3acbb103, 0x52ec6b88, 0x9883278e, 0x7870777c, 0x3abe7217, 0xadb18efc,
9558 0xae1f6f10, 0x2c85fc61, 0xa0d7a474, 0xf2cb34fd, 0xbab01469, 0xe92ba5a7,
9559 0x33e6bd47, 0x8cc73b32, 0xf9f0967f, 0x84bd7cd5, 0x6b3745eb, 0x1450a1a9,
9560 0x7f6873d0, 0x74d41fac, 0xc09a29ca, 0x38f98b3a, 0xbe095fa1, 0x5e55f02a,
9561 0xa5194846, 0x39139bb3, 0x3649b3be, 0x8fce9be0, 0x46412e74, 0xf7e70d8b,
9562 0x8a343d80, 0x83d28f7f, 0xa3cae807, 0x7e817a31, 0x28cd4ad7, 0x47a08c4f,
9563 0xe4bd72d3, 0xf2fafe46, 0xf40c8f52, 0x4f349231, 0xf80b35b9, 0xf00c576c,
9564 0x15274a1f, 0xfa018989, 0xccbe2569, 0x8e82921d, 0xfadbbdb0, 0x123a5866,
9565 0x1ef7dffc, 0x11260bd3, 0xefd1bfaa, 0xf4c4ff3a, 0x12d28397, 0xc7aa13a4,
9566 0xe5fd041d, 0xafb30d4d, 0x406dd226, 0x128b2abf, 0x9453e3ff, 0x10f689f5,
9567 0x013cc0fa, 0xbd3c3f67, 0xa4cf585a, 0xa73f655c, 0xc9445fe0, 0x25c8b2bf,
9568 0x743f0766, 0xbfb05ef8, 0x5c925663, 0x8d520788, 0x4c3831cf, 0xf13ea5bc,
9569 0xd7dbf73b, 0xdbf18627, 0x3db8eaf7, 0xc6b3a2a0, 0x6ce767c3, 0x147a0120,
9570 0xd246e2e7, 0xf850a72c, 0xf163bf49, 0x0e811b91, 0x19945d29, 0x3be81e49,
9571 0xc3f998a4, 0x7410f9c4, 0x1b6bca57, 0x240d9d04, 0x6ece8103, 0x7f4288ea,
9572 0x6f408de8, 0xf90b7e94, 0x0b9e42bc, 0x2cb5bdbd, 0xa4b2be84, 0x39eb941c,
9573 0xae424f40, 0x8f1c970f, 0x7a0597df, 0xf6f507bb, 0x436a7a20, 0x3d28927a,
9574 0x4427bfa1, 0x55db2a5e, 0x7ef026f4, 0xe5a3eb9c, 0x85ed19a4, 0x4e4cd1a9,
9575 0x3d99aafa, 0xd224d94f, 0x8c35ebdb, 0x1388aade, 0x289cade9, 0xa8d2a4e9,
9576 0x91e9abac, 0xa4a3517e, 0x9bd23737, 0xd1234e9a, 0x37a040db, 0xafe32f21,
9577 0x137b6f4e, 0xff33ff4d, 0xedbd285a, 0x76b92c4d, 0x6c7c137a, 0xd2a59447,
9578 0xa97c7204, 0xf8617284, 0x50ad41d1, 0x8590da1f, 0xab0ee7fa, 0x37b600e3,
9579 0x2ee2f6b3, 0x0ef90ca7, 0x7b782b39, 0xea12ab96, 0x3b692b4d, 0x38e4ba9d,
9580 0x741887cb, 0x5c2f6b3f, 0x0cc07cdd, 0x1b0f2f7e, 0xb5f3f7bf, 0xf76d2c72,
9581 0xcbe3e5ae, 0xdea12adb, 0xff8d8eb4, 0xc328e20c, 0xdbca8f20, 0xb75fbf0a,
9582 0xccc1cb21, 0x8ef7a657, 0x21ddfbe1, 0xe3803ced, 0x25b8d8da, 0x04d18d87,
9583 0xcfa66ced, 0x39f7ccde, 0x67db3366, 0x4cb747c2, 0xa7bf83b0, 0xd8fa83cf,
9584 0x52fa9aa7, 0xec1173e4, 0x2da972d4, 0xc0f1ca03, 0xbbc064bf, 0xcd9c9d63,
9585 0xe95b68e2, 0x644abe27, 0x7f110e7e, 0x75773882, 0x55f37e90, 0x8a13f322,
9586 0x8236497e, 0xcc7912fa, 0x8888768c, 0x211ef98f, 0xd84f9c12, 0x148b8c23,
9587 0xd39f1b2f, 0xf8c3fa8c, 0xe64e2281, 0xdfa7ced7, 0xc5fcbc2d, 0x987e70b8,
9588 0xbd32247f, 0xdb8f0ce5, 0x7a97df8b, 0x077f3c59, 0xc01a4910, 0xd626f755,
9589 0x2b0844ad, 0xbc03290f, 0x46cc7ab2, 0xa8ebc7e9, 0xd344bf91, 0x7080f5ac,
9590 0xff3094cb, 0xf1177268, 0xae86c5c5, 0xf896bc7f, 0x087f2cf4, 0x55b8bfd7,
9591 0x8443f98f, 0x383bb5f3, 0xc1e8c8fe, 0x72a7ce78, 0x7124a53c, 0x19387dbb,
9592 0x0eea7c0e, 0x8d3bb78e, 0xa7263acd, 0xfe2a74db, 0x7a049191, 0xfa88a6cf,
9593 0xc55db2b8, 0xeff2965f, 0xf87ae62e, 0xfe87d232, 0x1eb94fc2, 0xd313667e,
9594 0xed22efc3, 0x7dec2fe8, 0x0d9de98c, 0x2f407b74, 0xbe4abccb, 0xb28cf750,
9595 0xacaed0de, 0x0eb15237, 0xa87537f3, 0xf31e4ef8, 0x6a6ef6c3, 0xdbff0528,
9596 0xa28f47d2, 0xe0a977df, 0x9f255e33, 0xc67ee421, 0x1eb91e67, 0x7b6a3ffd,
9597 0xd4e9d85d, 0x0929be3e, 0x999690e3, 0xcc37a0f5, 0x0f796189, 0xf91f29b2,
9598 0xf688d982, 0xa0be2472, 0x5e8483b6, 0x7f0fae42, 0x3204a85e, 0xe0823ec2,
9599 0x5fef82ef, 0xb6525ec1, 0xec23f0ab, 0x3f1c1995, 0xe1fe2853, 0x76127f3b,
9600 0x9f8632d2, 0x0875c4a9, 0x5ddef3f0, 0x6ec23f0c, 0x9276e6fa, 0x93b60e53,
9601 0xad75bd84, 0xefda92f6, 0xcf5bce2e, 0xdacf6100, 0x026d9ed1, 0xddfe5340,
9602 0x13c4f7b0, 0xefd02455, 0x68710b58, 0x72f54175, 0x66b57fa5, 0xc852e9d2,
9603 0xae88cc9f, 0x46e017b8, 0xffd1133a, 0xec2c90d8, 0x34ff3627, 0xe175cf9e,
9604 0xdb38accb, 0x29c4fc95, 0x836b86f3, 0x6d5ee3ec, 0x43d82c5f, 0xfc2497bd,
9605 0x61add42e, 0xf18151e2, 0xe87c710b, 0xf7bebbf7, 0x4f73e067, 0xf13c60c4,
9606 0x2ecc97c2, 0x2879b0bc, 0xe39f15e6, 0x87015771, 0x799f8725, 0x70e70fd5,
9607 0x10e182e5, 0xbc93aebf, 0x6da6ed5f, 0x9fee8c23, 0xd3adf9c3, 0xbe8cf4f8,
9608 0xec445c58, 0xd3dfb23b, 0xff4f7c83, 0x7dbf931a, 0x89e63452, 0x0487dfd2,
9609 0x273687c7, 0xf081f8b3, 0xf93909c7, 0xe56f5e47, 0xa35a9ef7, 0x3f98fec4,
9610 0xf3bc52e2, 0x1fff8029, 0x57e0fd61, 0xfc87477a, 0x10e6fc1c, 0x9952a4b7,
9611 0xd742dba4, 0x6df9f105, 0xdf9f10d7, 0xc5e4c499, 0xb08b4a39, 0xe73645be,
9612 0x33bdf08b, 0x86790e3c, 0xc4ceb1c7, 0xbed6b8b2, 0x7cacfefe, 0x2267979b,
9613 0xbf45d1c4, 0xae8c5b8f, 0x3ede9435, 0x35ae216c, 0x1fd83e54, 0xde633431,
9614 0xafb62ccf, 0xcc563dde, 0xfee31513, 0x0e7e5494, 0xd5acf1d6, 0x85ca1875,
9615 0x347bca6d, 0xd41fb0bd, 0x7abed837, 0xbe2958a3, 0xeaa4a7f7, 0xdecf8073,
9616 0x67c47ee9, 0xa8a47d7f, 0xdefe70bb, 0x5fc8fc9b, 0x345bf709, 0x2918f3f0,
9617 0xf8b5760e, 0x3c8e3a97, 0x1e6f9c5b, 0xa6c59e47, 0x1c79b322, 0xac918e79,
9618 0x73eda74d, 0xffd1933b, 0x33d634be, 0xf6471144, 0x78a37cc4, 0xdec7a0be,
9619 0xec388101, 0x0e20df63, 0x3be9397b, 0x4e5ec38f, 0x5587130a, 0x025fe9c7,
9620 0xc01741bd, 0x0616ddc3, 0xbeb92ab7, 0x17a0fc12, 0x8fcc1216, 0x8fd9242e,
9621 0xec3d068c, 0x91788e88, 0xfa3d326f, 0x744b786a, 0xe15d8869, 0xf6268ebf,
9622 0xbaa4fda0, 0x6a3a8a6d, 0x877941e6, 0x14d34be9, 0x673407e3, 0x5c0ffa2b,
9623 0x3da2bd79, 0xa8a453cb, 0x51bbace7, 0x5b707fd1, 0xf43ea285, 0xfd145bd1,
9624 0x28d6f3af, 0x7fe017ea, 0xc8c9af90, 0x66786ed7, 0x92fc6286, 0xf52c5e37,
9625 0x7cb9b6c1, 0x8b72e56e, 0x795d9c78, 0x02fdcca5, 0x9f6fc8fb, 0xf89798af,
9626 0x0a549f24, 0xeff64971, 0x87bb2c5c, 0xc58bb0b1, 0xdc758607, 0x684ef8a5,
9627 0xa32ed25c, 0x9121d5de, 0xf8d0a4c7, 0x87ced2e4, 0x8ade42d7, 0xffa17f5a,
9628 0xa0c5b572, 0x3e6344ef, 0xa99f5aa4, 0xa027364a, 0xd24691de, 0xe9ab5d18,
9629 0x0f0fd4c2, 0x4851f7b8, 0xba323c86, 0x0a174158, 0xa1f851fc, 0x76c2eb7f,
9630 0x2d35e633, 0xd2016379, 0x494521a3, 0x25765117, 0x2ae4c45d, 0x50ecc2e9,
9631 0x995c41d2, 0xf0d40e92, 0x74953ab6, 0xbff4fc41, 0x7e3bc02b, 0xd46e9282,
9632 0x7d222ef0, 0xd80f3187, 0xdf00392b, 0xeb2f786a, 0xbafb82d8, 0x3cb8be9a,
9633 0x3917c799, 0x741f877c, 0x6e109ab6, 0xf8493f2c, 0xeedc0c03, 0xbf4a0926,
9634 0x56abd098, 0x8dbd7325, 0xf2fc23cf, 0xda0f256b, 0xb871fdf1, 0x2fa65f32,
9635 0x66f9ec0b, 0xae43fcc2, 0xc3139207, 0xf7f117fa, 0x0145fe48, 0xff5ca9d7,
9636 0xff2c23ac, 0xf31478e6, 0xbd5c7d0b, 0x8b42fd0c, 0xd1ea3349, 0x73c66ae7,
9637 0xfb07a1ff, 0x0219e1a9, 0x529d353f, 0xf904957d, 0x1aa2ef5f, 0x142726b2,
9638 0xe4a7529e, 0x533dc333, 0x81e429d2, 0x5013dd9b, 0x84e857fa, 0x12bf3052,
9639 0x5f98b0fa, 0x31f04fc0, 0xfc01af31, 0x540e7032, 0x2ae48d7c, 0xc7f6a2f1,
9640 0x963031c0, 0xec5bc706, 0xa33e3824, 0xfc04c3f6, 0x84fed42f, 0xacc0e178,
9641 0x3a07b856, 0x3f44e2dc, 0x9ae9095f, 0xff0bbf09, 0xae21fa0b, 0x887efd23,
9642 0x2aea7288, 0x1e29ddf1, 0x5678ffc9, 0xc4575c68, 0x3e182989, 0x3c1d33fa,
9643 0x800fb25a, 0x1decd475, 0x1474089a, 0x9c7497ea, 0x23ce857c, 0xa1e2fa6b,
9644 0x2824155f, 0x5f7dc507, 0x9fb8fc97, 0x81f3893b, 0x8dddfbe0, 0x4cdc7da4,
9645 0xf95307f4, 0xf3250b18, 0xb50e915b, 0x7f45adde, 0x04ee86b1, 0x048ebde8,
9646 0x02b33bc5, 0x439758ed, 0x479ad7eb, 0xc2c53933, 0x3e5809f3, 0x4ffce128,
9647 0xed9191d8, 0x16fae535, 0x49661698, 0xc105f7f4, 0x7586b8eb, 0xb8097c8a,
9648 0x90710a27, 0xd7042981, 0xc76c95d3, 0x4fa21bdf, 0x6e84ebbd, 0xc1995dc5,
9649 0x9e936e7a, 0xb760361a, 0x716064bf, 0xfea576cd, 0xf4c29d1c, 0xe070c8e0,
9650 0xbb2a59f9, 0x8f7a6ae6, 0x4aeacfc8, 0xf7d628b6, 0x362b9c60, 0xc06f7e85,
9651 0x92a7ff49, 0x4abe3026, 0xc43cc6ee, 0xde321d0b, 0x89bc6aa7, 0x3dc687f1,
9652 0x9ea11e32, 0x17de034e, 0x0071da5e, 0x16eea5f5, 0x7ea880ca, 0x7e85b672,
9653 0xe015f079, 0x246fdaaf, 0x31e4417b, 0x7ee1490d, 0x10520288, 0xf105079c,
9654 0xf1b094fd, 0x27fcfeff, 0x93e73b65, 0x1c5e7255, 0xcfeda3dc, 0x65f6d16b,
9655 0x47e104d6, 0xb8af8fbd, 0x73aa525d, 0x70a14f0d, 0x632ba0fb, 0x2557cc23,
9656 0x034e1e77, 0x1c90acf8, 0x631b7f10, 0x0d1bf760, 0x734772f2, 0xf4379d90,
9657 0x7105d95e, 0xee2bd3ce, 0x69fdc1b1, 0x4950ef31, 0xa8f0f783, 0x0ffef185,
9658 0x36ee218b, 0xd69eb1cb, 0x9d981b66, 0x18bdf599, 0x5f3d0e5f, 0xfbb3d3bf,
9659 0x66ecba5f, 0x67d057bc, 0x976fd195, 0x40b19320, 0xe2bd6217, 0x1df8a2de,
9660 0xfe4353ee, 0x4c7df8a6, 0xbbf0df6b, 0xb14a6969, 0x187bde2b, 0xbc37d953,
9661 0xbb8014d9, 0x4c6ad7c8, 0xfd05afd4, 0xeac8c7a8, 0x7a8b99c4, 0x3b230ae4,
9662 0x3db8a75f, 0xb0b06a76, 0xe0e67da7, 0x28c6a83c, 0x93e61c67, 0xb01323bd,
9663 0x38b4bf3b, 0x5fb8ace3, 0xc2c79b0b, 0xf9e1e9e6, 0xabde2bc3, 0xb12d7b40,
9664 0x531e7c35, 0xbbd30a43, 0x8aca2feb, 0xad7aa63c, 0xea91f30f, 0xbf15ea2f,
9665 0xe2e1487f, 0xf3ea0431, 0x071a0ccf, 0x1c405beb, 0x82ffa16b, 0x13c43175,
9666 0x3c8897a4, 0x7c3d3566, 0x68dff1cd, 0x30ed12d5, 0xbaec0fbc, 0xfe57bf52,
9667 0x5fbd8729, 0x468a48f3, 0x1e61a1e4, 0x3037b531, 0xf7eea79e, 0x7cea29ef,
9668 0xe7de3f33, 0xdb37cfec, 0x77c57e53, 0x962f1a19, 0x1bc1f22b, 0xd71878e9,
9669 0x2aac7178, 0x4bcf9c1f, 0x029bb3e7, 0xe0916679, 0x5b3275ff, 0x91e42357,
9670 0xceff07c5, 0x9df029e8, 0xe6179e04, 0xf8f3858f, 0xf78c876c, 0xa23d9f9d,
9671 0xcc35b099, 0x5c393bba, 0xe2d44fae, 0x47c1b939, 0x7cc25b9c, 0xf713f45f,
9672 0x3c7dc419, 0x5576faf5, 0xfac0e7f8, 0x7e658c47, 0x2f3cf561, 0x758af870,
9673 0x7c31b2ef, 0xf14abe34, 0x2c28f981, 0xcd97774f, 0x83f918bf, 0x4fe78945,
9674 0x763ad992, 0xc4cfe2dd, 0xcc899cfc, 0x0f448eae, 0x7fdd58f7, 0x9a6e3d45,
9675 0x48d57209, 0xb259b6a9, 0xabb79d04, 0xee0043d1, 0xa1af02b2, 0xbb63d770,
9676 0x63f3f798, 0x7e7edcec, 0x61539d8c, 0xa8fe7c0f, 0xf401f98c, 0xa0a49b40,
9677 0x09cffb3c, 0xde7c0b8b, 0x3ffea126, 0x4ac84ddf, 0x6de677ca, 0xe2fa63ab,
9678 0x7531c353, 0x9fbf7e07, 0x547997f2, 0xcb4cddde, 0xf1546bf9, 0x08576e61,
9679 0x8370bc39, 0x1b21deca, 0x3cc64bfe, 0x279466cf, 0x1cae7f8b, 0xa4db74bf,
9680 0xea7be0cf, 0x4afa3638, 0x71fcfda9, 0x4bcbd70a, 0x83c82949, 0x42fa9fbb,
9681 0x7c8f6b1f, 0x7e50ce1e, 0xf030683b, 0xdd96235d, 0x2f2c162d, 0x41bb38a6,
9682 0xdd53e83e, 0x7bd7c0bd, 0xbaf061df, 0xc9817f50, 0x39bcb80b, 0x84b9f812,
9683 0x9330cef2, 0x841f79c5, 0x2e14ec7b, 0xfb930306, 0x35fddc72, 0x5e957193,
9684 0x7e118ba4, 0xca2b1ccb, 0xd00a4723, 0xe373c27f, 0x13fc0027, 0xc2718b9f,
9685 0x7b97d6be, 0xc37f069f, 0xe8d155fa, 0x581a35ff, 0x7b67399c, 0xc0ec06b9,
9686 0xfb4976eb, 0xd4d1dfc1, 0xde172ab9, 0xa3d93017, 0xae213f31, 0x93165e73,
9687 0x093bec73, 0x801daead, 0x57b804cf, 0x3eb5d747, 0xf8c29bcb, 0x1a83d338,
9688 0x257bcc39, 0x3dc07ffb, 0x321bcf6b, 0xa0bc83de, 0xd7fcf965, 0x915f8613,
9689 0x0edf050f, 0x29baf7d6, 0x40d0c8dc, 0xc976fafd, 0x77c58ba7, 0x515e3024,
9690 0x3497dabf, 0x6fd1e413, 0xe9ef18b4, 0x52efd75f, 0x23ae202b, 0xc94cd0e4,
9691 0x5c47fcc2, 0xc44e9d9f, 0xaa17163f, 0x9d3274e5, 0x6333b1eb, 0x13e77c18,
9692 0x9b8c2647, 0x1ab12461, 0x5666947a, 0xfee097b6, 0xd05674ea, 0x237c4407,
9693 0xde111eb2, 0xb4f8d3ef, 0x94c7dd99, 0x24c086fa, 0x72a7c167, 0x3a37f385,
9694 0xc69dc995, 0x4b8fcc21, 0xc4271106, 0x1d5f1ad3, 0x72ec05ba, 0xdb8b3443,
9695 0x8464be52, 0x810e56f7, 0x5efba6bc, 0x7b144af6, 0xc7dc433f, 0xe10b38b6,
9696 0x4d53637e, 0xb7de1146, 0xef87d93a, 0xfce8f420, 0x297e7899, 0x4ca891bf,
9697 0xb6d373bc, 0xce94b55b, 0x3ea8d31b, 0x366beb46, 0x0b55bced, 0xfdb2e4f7,
9698 0xfeb4358b, 0x58b7a6fc, 0x4ffef5fb, 0xa6f2fea1, 0xc8bdac13, 0xf5a658bf,
9699 0x613e9b63, 0xa4d060ed, 0x4d97f211, 0xe87ab7dd, 0x5cad67fc, 0xf1f871df,
9700 0xdee36a1e, 0x7f609aa1, 0x8ca99be2, 0x628d9d5f, 0x9166cefd, 0xef0035b9,
9701 0x5ffdf0dc, 0x24f0d548, 0xc52c368d, 0x9278c57e, 0x22dc7e12, 0xbf196e3e,
9702 0x86263a87, 0xf1628bac, 0xc52c4f29, 0xa1cec1c3, 0x989b5f18, 0xf370e36a,
9703 0x62253be3, 0x314f011e, 0x5deef89f, 0xbe599720, 0x9e706d5a, 0x7f1cddfa,
9704 0xf06b3bf4, 0xec9c833b, 0x464d66fe, 0xe28fe021, 0xa6f1cb4d, 0x7b89bc05,
9705 0xb5af30df, 0x70fff900, 0xbc1f5bf0, 0x0567fb44, 0x93a6add6, 0xa7c65496,
9706 0xb8b2b597, 0x07359f62, 0x0c4c69e9, 0x58a2f77f, 0x1c638fb9, 0x5aa66f0e,
9707 0x01073df9, 0xbf0964af, 0x98e1cad3, 0x93521fe1, 0xfdf7cdff, 0x77cf5f30,
9708 0x7c20efbd, 0x8afde139, 0x6dd71d83, 0xb1b1fb65, 0xcf4a54bc, 0x1ef3d436,
9709 0x7677cc56, 0x197c6a95, 0x5fb0903d, 0x7f8e0e5b, 0x2077bf90, 0x7182f3de,
9710 0x3f4c0559, 0xdc55bd05, 0x9b9e27d3, 0xb4ffb049, 0x3b7e3eff, 0xd81b37bb,
9711 0x7cc5ade7, 0x4fbe169f, 0x57a7db0b, 0x78e4af41, 0x7354e65f, 0xc3f71d28,
9712 0xbcbe7fbf, 0xe29f3e22, 0x0f9b879c, 0xbc2475ce, 0xf1aefc1c, 0x82a9d622,
9713 0x559c3f67, 0x84f013eb, 0xf2e38df3, 0xd6297494, 0xf3a472f9, 0xbf2df59d,
9714 0x35c6ce57, 0xf7e580fc, 0xae92bb12, 0x6965761b, 0xc62e7e20, 0x2ecf03e5,
9715 0x3ebdf809, 0x6076e54b, 0x9088c906, 0x352e778f, 0x7f0cbfbc, 0xbd81db57,
9716 0xacef9656, 0x26f407f6, 0x109cba3a, 0xeecf3a47, 0xf9528f6f, 0xb29e202f,
9717 0x171814d3, 0xfaca2f90, 0xbf0634c8, 0x1f4bff50, 0x362d2fde, 0x7768bc54,
9718 0x31eebb50, 0xbfc06dcd, 0xee2ae38b, 0x98f5a2c9, 0xc06ddd34, 0x2bd38bbf,
9719 0xfca2c8be, 0x67a69cdc, 0xbe2a1bf5, 0x63fa86c8, 0x8c7fd67a, 0xf7e045f3,
9720 0x6dbfa3c4, 0x8f406a6c, 0xb3b34d88, 0x1a9553fb, 0x5fabff7c, 0x019df97f,
9721 0xd70117f5, 0x41b16548, 0x4e2e1cd3, 0xe8269c95, 0xca13c581, 0x90ed7fe0,
9722 0x7cedc4f7, 0xe76156bf, 0xfbb2c6f7, 0xfefbbdb7, 0xb227f786, 0x6919dcd3,
9723 0x314d5d74, 0x68b273dd, 0xfbcc757d, 0x9c92af18, 0x3f010f54, 0x6642dd87,
9724 0xdd4af5d1, 0x2fa05deb, 0x461cbb91, 0xfb95c22d, 0x314de07d, 0x5e57bf0a,
9725 0xe97dcdfd, 0x582e33ec, 0x07ce48c7, 0xfafd5e9a, 0x3673882b, 0xc039359d,
9726 0x73b23e2d, 0x6fa03dd3, 0xf37cec8d, 0xd987266b, 0xeeb10f7d, 0xa3d7e091,
9727 0x187597bf, 0x3b23fd70, 0xfd045baf, 0x33a1fd47, 0xa6e4e807, 0x6056be53,
9728 0x5efbbd0b, 0x1fde574e, 0x798aecfd, 0x4de3118c, 0xe89f1e02, 0x1499e809,
9729 0x7833371e, 0xab7cc25c, 0x6b63c49e, 0x2b97a8fd, 0xbd50d3ef, 0x17a6e31d,
9730 0xfc03b448, 0xb35ee2f8, 0xb2785fda, 0xfe8fee9a, 0x5d1f537e, 0x3cde9041,
9731 0x3291a2e6, 0x9cbd4092, 0x4af51558, 0x7fa2aa63, 0xd14b2595, 0x3ae53e3e,
9732 0x7b44fb45, 0x293ea2a1, 0xffa2a477, 0x45728e6d, 0x89b2f6fd, 0xced5fe8a,
9733 0xd0bd456a, 0x3fe8aed7, 0xb28748fc, 0x019138fd, 0x1d27450f, 0xf92ca007,
9734 0xc76e89d8, 0x07cd33d2, 0x25f91ca0, 0x5fda8703, 0xf6c5e37a, 0xf0bbf003,
9735 0xc7efaa97, 0x34e9ff08, 0x87d5e4d9, 0x68a693f7, 0xf25e7969, 0x35913f23,
9736 0x2d8c7eec, 0xe02f7dd6, 0x198fdc4d, 0x8a52fe03, 0xe7b9aa84, 0x59f0bdd9,
9737 0x12765fcc, 0x69fc0310, 0x7cfd19ba, 0xcfcd7527, 0xbdc599ff, 0xbbdf0007,
9738 0xb156afa9, 0xdd1731ef, 0x93977d8a, 0x2d3c2a65, 0x2cabd457, 0x1ff4503f,
9739 0xd14ab29f, 0x90fed13e, 0x2b0f4f0a, 0x3639b7ea, 0x45b4f0a9, 0x28dfa785,
9740 0x70edfbda, 0x157abfee, 0x1cb44efc, 0x04aaefed, 0xa67cdc3c, 0xd651f10f,
9741 0x780956d5, 0x3b64f1ba, 0xe7d8abe2, 0x597604aa, 0x00f9a47a, 0x7f6a3e94,
9742 0x5ad7b8c1, 0xd83cb052, 0xd5ff4762, 0x2c5c96e1, 0xf038b48f, 0x94b7dff7,
9743 0x8b56f961, 0x6cffcb13, 0x57658099, 0xf6cb0b8b, 0xbfec7696, 0xf983a5b3,
9744 0xdffbe2bf, 0x7e001815, 0xbf8d1e81, 0x3c56ee11, 0xe434d8f7, 0xfed13d9f,
9745 0x26afa81e, 0x9636de77, 0x81e78d32, 0xcc9d8089, 0xcee9a3cb, 0xbf94e9d1,
9746 0xac1c85ed, 0x41fe4092, 0x0859c6bb, 0xb4e1f87a, 0x0ed13f05, 0x5581e420,
9747 0x958b14ae, 0x8eb48dd5, 0x643186c8, 0x199c4fc1, 0x25105e74, 0x70584c18,
9748 0xa37bd41b, 0xb4defb58, 0xf279b705, 0x637107fe, 0xe17e4867, 0x7130b4e1,
9749 0xd8cfe7e3, 0x39cfe0cd, 0x19a86976, 0xfb8c71e0, 0x50a49cb5, 0xe5968f37,
9750 0xc81d42da, 0xbd2a93d9, 0xe4539444, 0xde61b7f2, 0x0ee38d76, 0x45be6fcc,
9751 0x6b7e8047, 0x8aef6624, 0x99d3db7e, 0x9b7bd0bd, 0xe3a9ed01, 0xbc22e71a,
9752 0x3df52717, 0x49ee7001, 0xa9ca3efb, 0x265f735e, 0xed3bafc0, 0xd89eac7b,
9753 0x08e484f7, 0x7c18ebaa, 0xf7bb4fde, 0xd9cf86bb, 0xf85092b4, 0x5859a6f4,
9754 0x1ce7c0dc, 0xaf007a80, 0x3676af1f, 0xdcac9c60, 0x71f61839, 0xe76065cc,
9755 0xfbc665d7, 0x2ceb4413, 0xbfc823b9, 0xc3ae9753, 0xa2e15371, 0x6739f81b,
9756 0xd5ce78c8, 0x9d287cf0, 0x27481fd9, 0x8f4e6760, 0xb8e0bb41, 0x5737dd86,
9757 0x9d267ff7, 0x1173d9c9, 0x0dfd83de, 0x94c57b87, 0xd377e786, 0x44577af9,
9758 0xaebdd4e1, 0xf58fa8a1, 0x9f784b36, 0xf34cf7b7, 0x706ed679, 0xdc609070,
9759 0x1ffc2672, 0xf3be7f6d, 0x91febf9e, 0x457f7ff6, 0x8865038c, 0xdf847ae5,
9760 0x7679de0c, 0xa7f511bc, 0x2a0335d9, 0xe4ce2e40, 0x6639b071, 0xc386126d,
9761 0x3c3d56b4, 0x54d0b89d, 0x904296b8, 0xd6a84e2c, 0x4b4553c3, 0x85af9633,
9762 0x0f41aef2, 0x9f09e1eb, 0x6b1dbcfa, 0xa06d8d41, 0xf904b847, 0x0b68ff9f,
9763 0x95dcd75d, 0x73d99db2, 0xeb3aae5c, 0x871e51be, 0x3ce3dfa0, 0x010286af,
9764 0xd367d5ed, 0xfb7f8525, 0x61af0e59, 0xcc7f5ce9, 0x1eecf927, 0x609c7f51,
9765 0xeefb9c38, 0x448747d9, 0xdb282388, 0x2ef8feb9, 0xfd56e77f, 0xeef883ee,
9766 0xc7ef1c73, 0x413294f5, 0xe4c19c9f, 0x17ed4140, 0xfee84bab, 0x1a2d3a0b,
9767 0x6dcfd38c, 0xb8780dd8, 0xa8f1c1d0, 0x9e701d23, 0xbde678a6, 0xaa4d398f,
9768 0x9357a17b, 0x4b2e8e97, 0x2cbcb065, 0x832abbf6, 0x5f5965e5, 0x45c8255b,
9769 0x2d7d1f21, 0x6e3f394b, 0xb07a3e46, 0x0fd62565, 0x3cb078b7, 0xf38eb2d2,
9770 0x7f6c36e3, 0xce51e5ab, 0x1f9cbd8f, 0x77bf833f, 0xf962d4b6, 0xcb1b8b6a,
9771 0x33dce307, 0x3e226e00, 0xc6e8d539, 0x9b43d1bc, 0x5fe2040c, 0x980d3a17,
9772 0xc44f4097, 0x40278f13, 0xef018dde, 0x6ff3a9f5, 0x9fbe7cd4, 0xb7df421e,
9773 0x189e9c58, 0xfa033794, 0xf4c8c0e2, 0xcdd88c74, 0xedfe97c0, 0x0f9057f1,
9774 0xcddbb31d, 0xa4b74fa0, 0x38bca277, 0x759bb4e6, 0xbc79eeb4, 0xedbbb593,
9775 0xafad0366, 0xdac7df4a, 0x1473763d, 0x7c7eafad, 0x12f76b1f, 0xf83f220c,
9776 0xc7c86bf8, 0x107489ca, 0x31a547ce, 0x17152c6b, 0x1f975e54, 0x3e317384,
9777 0x3858de65, 0x3d725f17, 0xd57da27d, 0xca4fa841, 0xab85a2dd, 0xe1534edf,
9778 0x9157181a, 0x7185ad50, 0xaf963363, 0x06e37181, 0x1e0dac3d, 0xc76f2137,
9779 0xeadfa81a, 0xfd05a2d8, 0xc7ce4bf4, 0x2ea23cc4, 0x169f05da, 0x3ac360f9,
9780 0x0a0f285d, 0x0f285c3a, 0xa62a5c04, 0x7e003f56, 0xc90ea6c7, 0xa63ac122,
9781 0x71c1fd4a, 0x846ba5c8, 0xbf2922f7, 0x8efe98de, 0xd71d1579, 0xb11bf504,
9782 0xa65593fe, 0x6f7f94ef, 0xdf230f4d, 0x0ef3f04e, 0xbbf21ef2, 0x3bd9e84f,
9783 0x5c035f1d, 0x9b9ef04a, 0x24b5df19, 0xe3fa336e, 0x3d833641, 0xb69e7204,
9784 0x1965e70f, 0x6453fb97, 0xcef876e7, 0xc3f9918b, 0xabfcfccb, 0x68444dee,
9785 0x4f61fce7, 0x4bd985ba, 0x06875dfc, 0xd07e86d2, 0xa997e5ab, 0xf9d5a1f3,
9786 0x59ff2216, 0x4f515f9d, 0xa1307bd8, 0xdeecce79, 0xb39e486e, 0x19a2abb0,
9787 0x5e05ad3f, 0x78f8e943, 0x0957cf3a, 0xabc9c385, 0x3864e1c0, 0x87ec8438,
9788 0x2eef3178, 0x74c6ff24, 0xdeacf11c, 0xb2277117, 0x3f8936f7, 0x5d04feec,
9789 0x8dafee84, 0xe0cb5fc1, 0xb3bbf54f, 0xb9aae780, 0xab7e0266, 0xc7f3fe60,
9790 0x351ff02b, 0xf8aefb5f, 0x0db9b4e5, 0x5080fdec, 0x1c39763e, 0xc2f7131f,
9791 0x53d0a5d5, 0xe41a3ee1, 0x343bc201, 0x4befe760, 0x80674776, 0xf7d1567e,
9792 0xd0ec0695, 0xf37ef604, 0x9cdb9b22, 0xe922e141, 0xc8817e59, 0xf1a33dc3,
9793 0xb6f416fc, 0xc9e6cdb4, 0xb0832fa8, 0x4ac767a0, 0x7e3fe0eb, 0x878aead6,
9794 0xafd72471, 0x3a077e0f, 0x7a699e52, 0xa17f9306, 0x5fe45125, 0xfaf96ef6,
9795 0x8a2fde9a, 0x792a8f04, 0x41ee1fb4, 0x418b285c, 0x112dd9f9, 0xdb3fbc1f,
9796 0x7a849e5d, 0xbd00f74b, 0xdaefca16, 0x301eee2e, 0xdb57e704, 0x65a9ddc7,
9797 0x71ddf646, 0xd0eca013, 0x079d1fbb, 0x0691e0fe, 0xcdbc938c, 0xc7270ff3,
9798 0xb7c3fcb0, 0xc980fdf9, 0x004a5e1f, 0xf65938f9, 0xa1481525, 0x1bf77676,
9799 0x05ec2ab3, 0xdd36f6a1, 0xefd858ef, 0x976eecd5, 0x6006cbb1, 0xf5dfdb55,
9800 0x9022bf2b, 0xe56a3de7, 0xe3f90225, 0xbc7b73ff, 0xa4f5132b, 0x9533e4ab,
9801 0x415b79f5, 0x897318ff, 0x228e39e5, 0x9525ce2c, 0x9bf2c9bd, 0xdbb6a978,
9802 0xbda868e7, 0xa76a1d9e, 0xa5fd92cf, 0xd421ef50, 0xd809cf5e, 0x374ec2eb,
9803 0x45bf9610, 0x3806f7ed, 0xddb9e717, 0x8f13314e, 0x7c3f2179, 0xc87dce6f,
9804 0x9f30a217, 0x8f8ef9e3, 0x7fad6112, 0xc5fc4ae9, 0xbd00f62b, 0x22be5937,
9805 0xf5fa79c1, 0xc120bf2b, 0x7375bcef, 0x8e9b773f, 0xffaa43dd, 0x8a728ca7,
9806 0x8075b5ca, 0x9af27aa7, 0x7920eefe, 0xabffda4b, 0x28c3de1f, 0x3586abff,
9807 0xb4f5bc81, 0x7ed2764c, 0x223edcd5, 0xac76f91e, 0x32927b73, 0x289ed646,
9808 0xeacbbffa, 0x13ff4403, 0xbbf49d93, 0x9da2a9d5, 0xd78ebf8f, 0x6c76ee89,
9809 0x0df312cf, 0x6b337565, 0x72f8cb6f, 0x8231e832, 0xe0cc6fbf, 0x47bf91f2,
9810 0x63fdf944, 0xcc578919, 0x73b651bf, 0x1fde2079, 0xc4e1faaa, 0x6e70a398,
9811 0xb5cc25db, 0x875fbfab, 0xb673fbfe, 0xf7e082f6, 0x8e9e454a, 0x798cd2ab,
9812 0x0d2f0d53, 0x22740add, 0x81278f9b, 0xe3c5d2de, 0x09b255f1, 0x36172ee3,
9813 0x491ebe30, 0xf2bc5bef, 0x42be0515, 0xc0fbf9da, 0xdfa49818, 0x6493ff3b,
9814 0xa0f33ef6, 0xe80bcc2e, 0xde0c7ce0, 0xc37b847b, 0x212bff22, 0x5ec13887,
9815 0x8a39784e, 0x71f953bd, 0xc5dbf217, 0x767f332f, 0x2803a6c3, 0x76cbe6df,
9816 0xc89d27f4, 0xf00abf76, 0x0d7731e9, 0xcaf838c1, 0x3f5d7157, 0xdc785bb2,
9817 0x182f2fab, 0xe143879e, 0xc0abfbff, 0x4afff7ff, 0xfc82eff8, 0xbb73e032,
9818 0x4dbed0a3, 0x0ef5fad6, 0x649e6b88, 0xe79e5cef, 0xfaed2b70, 0xf815df10,
9819 0xd3b30667, 0xdc583ae2, 0x8965e446, 0xc333feef, 0x1e74eccc, 0x79a8691f,
9820 0x47c4346b, 0xc4c6fe04, 0x77f07690, 0x38383c53, 0x07801c1e, 0x9c40ef01,
9821 0x0acb8e84, 0xb0aed79e, 0x23dc050f, 0x7d35639d, 0xe3ab7588, 0x0e997706,
9822 0xef7e0096, 0x847986fa, 0xb0b4cfdf, 0xcc7eb4f9, 0xf011fc13, 0x1e00c4ca,
9823 0xef940375, 0x46bc5180, 0x22b9280d, 0xffed95de, 0xc35778cb, 0xf3d65d4d,
9824 0xf7fa9838, 0xff3403a1, 0xbffc70ab, 0xdd9d5fe6, 0x3ed15fbc, 0xd71be577,
9825 0x7e157fe4, 0x1f957fd1, 0xf5ff9236, 0x16ee992f, 0x2fc9bba0, 0xfc40d12e,
9826 0xffbdf6e6, 0x8b013bc8, 0x5e303bf7, 0xcbdf0f74, 0xf6ffa317, 0x9e947dfe,
9827 0x7e6668be, 0x3ffb53a9, 0x43f3d9d7, 0x45f663e9, 0xe8833899, 0x77caf66a,
9828 0x669f2074, 0x5c22cd53, 0xa70d6a7c, 0xa127cc27, 0x48d6a07c, 0xfcf40974,
9829 0xf7b2d6d7, 0x10216ba5, 0xe7d2c363, 0xb593eda6, 0xc7ef07c4, 0x3eb49b56,
9830 0x9487c603, 0xfc0d61f7, 0x686a597d, 0xcac5ee2a, 0x9ef3194e, 0x716328ee,
9831 0x76a619a5, 0xfd38dfbc, 0xf7f3eac8, 0xe35dd9c1, 0xba796129, 0x9fd27ee2,
9832 0x5e24df34, 0x37e406b4, 0x1e259ff8, 0xc3ae5c87, 0x5c7aa438, 0xfe7600ed,
9833 0xcb12cb26, 0xf2c3d837, 0xa479c4d7, 0x28623bfb, 0xf0f37962, 0xb3756ace,
9834 0x00b437ce, 0xa8fd8ff4, 0xad95347f, 0x353c002a, 0x303e958d, 0xc0f40414,
9835 0xa25f95a6, 0xc7e6a37e, 0xfd5af2ea, 0x1cb7ef50, 0xfa117a41, 0x1f16a9e2,
9836 0xa97ed5d6, 0x8c7e6359, 0x5f919c71, 0xd470bd32, 0x1189e725, 0x6f6f6ff6,
9837 0xd84b3b09, 0x4e3b6a5d, 0x5ef10bf0, 0x0b00fb5c, 0x77c6bb93, 0x5a8ffbd8,
9838 0x4034be56, 0x5f057729, 0xef767ca5, 0x4a5fe400, 0x87c41bfe, 0xc55ffdb1,
9839 0xdf740387, 0x4dff00ec, 0x6f7b066d, 0xf5f74d5d, 0xaa7e4c29, 0x94ae5de9,
9840 0xd3519f51, 0x3bf3a0bb, 0x7fd05b9d, 0xd2c60b37, 0x926acc75, 0xc9d59ef0,
9841 0xd7bc1e97, 0xddd09748, 0xe29d33fe, 0x486fbc3d, 0xe072a1f7, 0xbe23b463,
9842 0x5d201cb5, 0x33feecd1, 0xa84f47c3, 0xc0a0bd1c, 0xbd1ca84f, 0x5fc4aff0,
9843 0xf9cffd98, 0xf0907276, 0xc8bb7f3c, 0x6b239ff3, 0x26dcf7d8, 0x790a0796,
9844 0x765ebd68, 0x56696c2f, 0x4d7fbe1b, 0xe058b20d, 0xc9f6cb23, 0x778b3d64,
9845 0xde835368, 0xbe26ea2b, 0xe0494777, 0x9bf9624f, 0xf7b3464b, 0x9a79d43e,
9846 0x91b3ff22, 0xb4cbbb8f, 0x54788f4b, 0xe62443bd, 0xd443bf51, 0x67fc7a38,
9847 0xf7e7ff18, 0x0fefd58b, 0xf9e4ca0d, 0x88a4459f, 0xccafc7c5, 0x5e407aa7,
9848 0x7b8df906, 0xbda0b52e, 0xf4399793, 0x01193c3f, 0x8665177c, 0x99a5d7e8,
9849 0x94b3d657, 0xfa62ffed, 0xf0dbcd90, 0x4a6f913d, 0xe72c861f, 0x38b75824,
9850 0xf9e7fd27, 0x679e0315, 0xef713ef1, 0xbdf1e7f2, 0x09afde8f, 0xe6ae87c6,
9851 0xcdd3199f, 0xf4dd03ae, 0x4cd5b7b1, 0x94ea3ef1, 0x2304fd07, 0xdef1bb8f,
9852 0x9cb788dc, 0x0a4c8190, 0x5864ba0f, 0x841bd0b7, 0x0be0111e, 0xcf0b7efc,
9853 0xfe56b8f7, 0xdc4bfff1, 0xe9b3dc43, 0x4e4af9d1, 0x13defc80, 0xef1df615,
9854 0x2b9a99d5, 0x60f9ffbe, 0xe0357b9c, 0xbfe70a69, 0x2ad01de2, 0x7bdbbd99,
9855 0x3f464ba1, 0xfd1f8ac5, 0xdb8fb7e1, 0xeb57e743, 0x2f964d67, 0xd247ae50,
9856 0x2c349bd7, 0xd2a8beaf, 0x605af98e, 0x42df80ff, 0xfdd431f8, 0x7e2bd90f,
9857 0xf776899e, 0xac272ee8, 0x9eb651e7, 0x5a6af848, 0xbf0a5ff9, 0x37efa449,
9858 0xccb12bed, 0x7f1f3a0f, 0xfd0494cc, 0x06353e5b, 0x74ad7df0, 0x0ecd7ff1,
9859 0x8f132c98, 0xbe70e544, 0x257a65e4, 0x2ce5fa61, 0x1ce585d2, 0x9ba587d2,
9860 0xf9eabcb0, 0x42e581c4, 0x65d3cf7e, 0x0991bf77, 0x1f5d55fe, 0xfe7b53be,
9861 0xe1e7bfa5, 0x8f37503b, 0xa95c836a, 0xad9fcaef, 0x0b7aafd6, 0x0d38fefb,
9862 0xbfeec7f8, 0x0f51da67, 0xb377b6b8, 0xd3ce71bd, 0xddfc6199, 0xb32e59ff,
9863 0xee97157b, 0x5a4def65, 0x363218d8, 0x2574fb11, 0x09f9e167, 0x2de4cdf0,
9864 0x5c426f82, 0x0d03ff2b, 0x932fcb8b, 0x7505eff0, 0xc47835f8, 0x796517f2,
9865 0x62efa865, 0x560df9ed, 0x717904af, 0xfb58a323, 0x5dfe2b72, 0x8fc4d9cf,
9866 0x3c2e72e7, 0x3dc32b65, 0x0b963b09, 0x54d4fbf8, 0xe896cee3, 0x469d45f8,
9867 0xfc4dcf96, 0x05bf6083, 0xb1849f60, 0xf206cb77, 0xe3367438, 0x542ac3f7,
9868 0x0fce05fe, 0x3315ec1a, 0xe172d206, 0x48192740, 0xad987ee9, 0x20cffd6b,
9869 0x86b7606f, 0xcfafbdc0, 0xe300fe46, 0x2fdc622b, 0xe83a15ec, 0xf2c482f7,
9870 0x0cfb3d8e, 0xa4d4bde2, 0xcbbd3f60, 0xfd03195e, 0xa8b6146c, 0x2b80451f,
9871 0x572abdfc, 0xe44c7b18, 0x1d030db1, 0x0485fd11, 0x417a25df, 0x819cf562,
9872 0x4d7dbe3f, 0x3d30fa1e, 0xc2fe87a0, 0x7d80ceee, 0x6213d30c, 0x92fff582,
9873 0xcd21afdf, 0x5f0f1099, 0x034184f2, 0x547bc67a, 0x833dc31c, 0x167b533f,
9874 0x2ed4d3ca, 0xd42ff285, 0x03f2852e, 0xf942976a, 0xa14bb511, 0x10b1745c,
9875 0xbe2224de, 0xd862ce81, 0xa83b888f, 0x903f9bd7, 0xbb06cdc9, 0x1d62867b,
9876 0x8eb8f4fb, 0x3f5dac17, 0xc75d19fd, 0x6907bb0b, 0x244bbee0, 0xfbeef478,
9877 0xfe95e65b, 0x7f888d3e, 0xf107dba8, 0xd2ec17ef, 0xe82fdca2, 0x0e2ec7f0,
9878 0x503157ea, 0x77f3e38f, 0xf30b1c7f, 0xe1fa58f7, 0x56e894ea, 0xbd586b27,
9879 0x845e57e2, 0x39dd836b, 0xcf4bf603, 0x4fd838f7, 0x7e1fc741, 0xe83af70a,
9880 0xeda718fc, 0x8236fa95, 0x87dea67e, 0x5f62df7a, 0x61ebff74, 0xb3bb0bfc,
9881 0xdf942761, 0xf65e7610, 0x437977b1, 0xf70abbf7, 0xafa1bb73, 0xdc2bee18,
9882 0x9b0e597e, 0x2f60da27, 0xc57f7847, 0x38fed0f5, 0x812ba71c, 0xae7b6faf,
9883 0xf111f3d5, 0x50f001ee, 0x4ba3c83b, 0x560fa0b1, 0xc76678f3, 0xe36f41ae,
9884 0x322397fd, 0x385fbf81, 0x773ca6cc, 0x1278e13f, 0xbd3efe65, 0xc2f5f00b,
9885 0xc1074fbe, 0x3f14a07b, 0xc9efe083, 0x60e068fe, 0xfe7dfe45, 0x031fafc8,
9886 0xf1fda1fa, 0x274e15ef, 0x6e20aa5b, 0xffb8d33f, 0xb6696c10, 0x882a83e5,
9887 0x914dcfdb, 0xcf39430e, 0xe20e359e, 0x79df22f5, 0x61f96e41, 0x3ab74a38,
9888 0x2b8f51aa, 0x2412e607, 0x318d2a17, 0x216051fc, 0xf515e287, 0x8ae929f1,
9889 0x39ed13fe, 0xb949f68a, 0xfbda2837, 0x8638a1ef, 0x06cf7e07, 0x4365f478,
9890 0x83ee8d1c, 0xa7b57dfd, 0xca77cc64, 0x96fc7ddf, 0xf27d681b, 0x7be077d3,
9891 0xf6f02f6f, 0xf12b3bc9, 0x52f59bef, 0x22a9ea78, 0xa1eca675, 0xc9833f8d,
9892 0xfd42f654, 0xc30f27be, 0xd8dfd0bb, 0x2760885e, 0x97a611d4, 0xd417b246,
9893 0x9be50276, 0x39be053f, 0x16a9a5ec, 0x617f0fc8, 0x2069d7e4, 0xe40fb697,
9894 0xfb7066ef, 0xf4fd1221, 0xfec9139f, 0x29fdf076, 0xbf88fd35, 0xc9ca2d6f,
9895 0xa13dd8c7, 0x3ed7ca6f, 0x7686be01, 0xafdb87b9, 0xcff954bc, 0x6f1de986,
9896 0x9efe03df, 0x94dc32a3, 0xb5bfbfe8, 0x0e5ffe18, 0xb8593dd0, 0x04d481e5,
9897 0xfa03ddfc, 0xa7f72370, 0xeb90367d, 0x1ffbf553, 0xb40e2d48, 0x281f1593,
9898 0xa5fb93fa, 0x9afa8ab5, 0x437d652c, 0xf1e0daf9, 0xc5b1f491, 0xbbd3ce8f,
9899 0x9f9ee1f3, 0x3aeff614, 0x8127aff6, 0x4b7d87f3, 0xba7edf90, 0xbdfe197f,
9900 0x46ff7559, 0x01f81f3a, 0xb3904717, 0x974d4f82, 0xeac23bd9, 0xef8abff6,
9901 0xefdbbe39, 0x8f6147bd, 0x332f5e79, 0x9c5efbf9, 0x13a0af5b, 0xf9eefb3b,
9902 0xe8ff0f4d, 0xed2b882b, 0x79d57661, 0x051f932b, 0xc0d33ebb, 0x161e8bdf,
9903 0xc0abe8cd, 0x3dc0d7e2, 0x7e06ff9a, 0x00334c2b, 0x0000334c, 0x00088b1f,
9904 0x00000000, 0x18adff00, 0xf514707b, 0x7bdbdbf9, 0x79724b92, 0x71211240,
9905 0xc220572f, 0x4849ac91, 0x92ea4903, 0xf03ea410, 0xa2a21900, 0x799e0fae,
9906 0x2a93a84a, 0x028d361d, 0xd6d36d52, 0x4f4e2a2a, 0xd1954a2c, 0x2562bc34,
9907 0x40569478, 0x2f2a7b1d, 0x419cca69, 0xee421923, 0x8cc38a8c, 0xbf7dfa1d,
9908 0x5eddcddd, 0xc9a75502, 0xf6fbbf1f, 0xcfdef8f7, 0x05048af0, 0x571a0192,
9909 0x02a62a26, 0xc8dc8280, 0x00b5fb71, 0xbb4c6176, 0x94e00b3d, 0x157004c9,
9910 0xa5029fd0, 0x30276100, 0xf0efdd38, 0xbdbf423d, 0x225f1c91, 0x9e5eef7e,
9911 0x77dc2323, 0x4055a560, 0x5dfd12f8, 0x361b5d17, 0x709563df, 0xd480197f,
9912 0x0fb91ce1, 0x1d300ad0, 0xe7f015df, 0x32a3a458, 0xe784db92, 0xf716faee,
9913 0x2412fc55, 0x828f9d20, 0x76048f4e, 0x15798f80, 0x0624279e, 0x8df3c49f,
9914 0x22b07847, 0x3810033f, 0x8ec7077e, 0x004ab339, 0x814fd396, 0x815877be,
9915 0xc005bf67, 0xefb42bef, 0xdf97cbcb, 0x6f084904, 0xf286f4b1, 0x4970fbd8,
9916 0x90e30343, 0xaadced7e, 0x9d5bb7bf, 0x78c9feb4, 0xff1e01ae, 0xb5fbc782,
9917 0xd7ef6410, 0x7b7dc0ed, 0xf5f97ecc, 0x0dfbd39f, 0x0af78cbb, 0xbef4c485,
9918 0x0a03f4a9, 0xb3ecf12f, 0xb6adf089, 0xf9aaf8ab, 0xb1bc3f6f, 0x837af918,
9919 0x69f86d17, 0x64c4df68, 0xd98fe2f0, 0x91aca428, 0x8cdc6c72, 0xe145a48f,
9920 0x5cfc7dc1, 0x47379d3f, 0x1b4fe672, 0x44906f29, 0xb561c913, 0xbab7c54b,
9921 0x80059be2, 0x9b7756f8, 0xe02bb801, 0x1083c8d9, 0xdba0a783, 0xa33bf3e6,
9922 0x2a5d87f4, 0x5fdd058f, 0xaaf2cea7, 0x01d12b6b, 0x405e2aed, 0xa67a41bb,
9923 0x47496071, 0x139f307c, 0xac72e1b7, 0xe492a33b, 0x80838c74, 0xb89ec850,
9924 0x2df48ed5, 0xefa39f54, 0x1fc5484e, 0xc2667999, 0xcbd340b3, 0x2f77d2c2,
9925 0x516f7872, 0x4889a2f7, 0x75df1c01, 0x1cd431ef, 0x0c3c152c, 0x2c5062df,
9926 0x296397a4, 0xa466ecbe, 0xddcf1e73, 0x1c12f3ed, 0xff10e019, 0xae048ab1,
9927 0x3fef638d, 0x7cebef42, 0xb2f8b31d, 0xb35f189b, 0x37a87d5d, 0x5fc29a4e,
9928 0x8f29184a, 0xd0cd5ca8, 0x5797eba7, 0x59ec86dd, 0xd7e6afdf, 0x1d31bace,
9929 0x5c04b8f5, 0x16fba436, 0x610c0d1e, 0xdfe6cb78, 0xe03126e6, 0x5f2819ef,
9930 0xf44a982e, 0x2d0584fa, 0x68cfde02, 0xd39835f9, 0x5667e462, 0x8fd74efd,
9931 0xf491cf2e, 0xf9abf8a8, 0x7c84a0f2, 0x98e76d0e, 0xaa88351d, 0x9f94369d,
9932 0xc462c3fb, 0x45e410df, 0xefa9e90e, 0xe492703a, 0x03aeb1d8, 0xce8016cc,
9933 0xad6c5d75, 0x7c033bb7, 0xd98fe33e, 0x838d09af, 0xc1a55bf8, 0x74775f8c,
9934 0x1c7fca3f, 0x3032cbbc, 0xf802e70c, 0x13bf7d93, 0xbf359f90, 0x62d8f2f8,
9935 0x794376a2, 0xb207f30a, 0xf4a3abb9, 0x9c015817, 0x5b647f48, 0xc32b7f82,
9936 0xa27eaa23, 0xfeff6dd9, 0x719a2749, 0x0b1dffbf, 0x1583db33, 0x1cfe0f4f,
9937 0x12db35e1, 0x53fb9c98, 0xfda2c941, 0x0afd93ad, 0x8a6e581e, 0xdc9334f4,
9938 0x6dc5133b, 0xf3f9ffb8, 0x81dd5f93, 0x2757caf0, 0xf926448a, 0xdf845091,
9939 0xefa011b3, 0x3dd8b33b, 0xcbbc5590, 0x5fe4ff34, 0x729bf69e, 0x4d397fda,
9940 0xfeba3c24, 0x90ef3ece, 0x35f5e500, 0x685df204, 0xa538e782, 0xd70f84cf,
9941 0xe69c769a, 0x36ad3ed0, 0x75e92779, 0x397fb3d5, 0x54fc865e, 0xd3f37cbd,
9942 0x95be9033, 0x7a058d1f, 0x11d7aa27, 0xe42920f1, 0x51e038a5, 0x9f2680e3,
9943 0xff0eedda, 0xa57131a7, 0x00c523be, 0xf9657637, 0x47898d3f, 0x18caa0b5,
9944 0x1f98e7ee, 0x35fe69d5, 0x20df978d, 0x4843d47d, 0xb110938d, 0xf2155d92,
9945 0x2171449c, 0xc98d84f2, 0x3ecede3f, 0x2ecc4c10, 0x53204ceb, 0x034c2f7c,
9946 0xaff9267b, 0xfc2fcaac, 0x9bade4c4, 0x42fd3650, 0x93ffeeaa, 0xb58b4c16,
9947 0x37869ecf, 0xdb373ec9, 0x380e7d98, 0x3c67f980, 0x290b7f9e, 0xfb32fcec,
9948 0x861fcc57, 0x45cb4bf3, 0xc0c51730, 0xee28905e, 0x4509b615, 0xacdae00f,
9949 0x964a65e9, 0xadfc442f, 0x9eedf8ea, 0xb73c98f7, 0xf08a783c, 0xfd32761e,
9950 0xdcaa7bc1, 0xc4d41cc3, 0xf665a9e6, 0x7bff342f, 0x7dcfe0c1, 0x97c89ccf,
9951 0xddbefdf1, 0xed01f353, 0xd83e5ef9, 0x67ca1cf7, 0xfa783130, 0x0f3b5c61,
9952 0xf28e387f, 0x75bd3c62, 0xe01a5f2d, 0x478d4e01, 0x7e07c475, 0xbbeb913f,
9953 0xe181f640, 0xde87c584, 0xfc98d34d, 0x326f79aa, 0x6fdc3fe9, 0x4e9e2fa4,
9954 0x3e9d7dfd, 0x9cfd7dfd, 0xebeaadd9, 0x9f9835bc, 0xcc9fdf8a, 0xefac1811,
9955 0xe60a4f9f, 0xbbe938a7, 0x8a973d4b, 0xd5bd8c70, 0x6fd44fd0, 0x37e31d8d,
9956 0xc35357d2, 0xbec06d89, 0x713f142b, 0x5fb8c80d, 0x26a6f997, 0xd1d9f037,
9957 0x766916ce, 0x6669e906, 0x82b73bca, 0xb48bd76a, 0x743b7df8, 0xe5fd0058,
9958 0x67f5a9a4, 0x3a075c76, 0x63916f7e, 0xca72afe3, 0xf7ea6974, 0x254abf8f,
9959 0x3f1c51e4, 0x3ab272ef, 0x339ba267, 0x90d973b3, 0x5f70e74d, 0x281da00c,
9960 0x0db1369d, 0xdf7991e9, 0x57bc6e35, 0x93e40d67, 0x64f7e81f, 0x07df665e,
9961 0x9196f7b8, 0xc81cc1be, 0x8a4ff567, 0x3bac3815, 0xa0c563c2, 0xbe50f284,
9962 0xe2571606, 0x02d865e3, 0x47489d35, 0xfdd77d05, 0xb8a4ed11, 0xe9d4d4ca,
9963 0xc65e251c, 0xbd3407c1, 0x9a99a715, 0x8ff1463a, 0xe91f68db, 0x5e0e836b,
9964 0x7f355ff5, 0xc6726996, 0xd6c7cf84, 0x5c5a0d33, 0x15d9270f, 0xdb2fe91e,
9965 0xb8407a87, 0x40381ccc, 0xb43d7a2b, 0x42673ea0, 0xcbaf7d40, 0x6729bf18,
9966 0x78f9612c, 0x33238b2a, 0xe7aef535, 0x68f4809a, 0xeb857ca7, 0xd3c82e26,
9967 0xb08813fa, 0x99970255, 0x5b3b1456, 0xad8f8367, 0xad89a073, 0xad9da173,
9968 0x5b074037, 0x5b20826f, 0x0da04a61, 0xeb5ffc58, 0x0c3cc3ea, 0xa26e5d3f,
9969 0x18bc5c7c, 0x87f3469a, 0x2ebc9ab5, 0xea8c0f2f, 0x1e5c3f25, 0x64ce4073,
9970 0x2e4e5d74, 0x9d98f213, 0x91b172eb, 0x073de23d, 0xad6933f8, 0x877b1080,
9971 0x99de925c, 0xe0998205, 0x5c18902a, 0x51e51dfd, 0xb2cd921a, 0x54b91477,
9972 0x8f276e8d, 0x9171726a, 0xea8d8f0d, 0x605baf6b, 0xcc37aeb0, 0xff1499d0,
9973 0x7213ea47, 0x84e2ce88, 0x0c052fca, 0x21f77e11, 0x6be3199f, 0xb3655171,
9974 0xf74ee107, 0xe3199f49, 0x65597168, 0x6ac44591, 0xdf63f5b3, 0x4765846c,
9975 0x1fa03e52, 0x3bc831d9, 0x87bc3e50, 0xfa54d287, 0x7ca7e39e, 0x101fe369,
9976 0x07654fc9, 0xadd59040, 0x17e45568, 0xaeef357e, 0xba7aa971, 0x4b3f26d9,
9977 0x0f6f587e, 0xc3c80924, 0x0cead69a, 0xac1b87ca, 0x8c9fbbea, 0x89bea615,
9978 0x1e21b172, 0x2f94617b, 0x081c57dc, 0xb9a13887, 0x47a51dc5, 0xf01dffc7,
9979 0x784af9fe, 0xafca650f, 0x09bf29b9, 0xc61beb22, 0xb3bb796b, 0x97c44cb3,
9980 0xa3170e90, 0xa9389423, 0x26dc85b9, 0xde97b7cb, 0xf6aa270b, 0x7b6c97b6,
9981 0x75ed747a, 0xd3ddbb4b, 0xb70f7e47, 0x8027b37e, 0x433f86ef, 0x5def78c4,
9982 0xce8fbcb7, 0x39429a35, 0x5f97a845, 0x92b69c26, 0xcaf6e83d, 0x209692a1,
9983 0xf8126ddf, 0xca0fccad, 0x9675c35d, 0xe1ef6a27, 0xca1ef8a5, 0xabe7d8a3,
9984 0x4a0fb2c2, 0xd20e9a6a, 0x57b72a5a, 0x39e10ee1, 0xf236f442, 0xffa46591,
9985 0xac8f94c1, 0x9c7f319f, 0x169ddaa0, 0x1ff7baa7, 0x0abc7879, 0xdfc620fa,
9986 0xbc5ff71a, 0x8f8c2ff0, 0x914e438d, 0x7bed978e, 0x7dea99a6, 0xcab0cfdd,
9987 0xdd11c433, 0xd97666ef, 0x773b3c02, 0x5f3a52cd, 0x878f51f1, 0x3d75efe2,
9988 0x832a36a1, 0xc627ddc3, 0xd7aff6ab, 0x3f70dfe9, 0x6e7c4f24, 0xa6487b47,
9989 0xa7ca8b3c, 0xef37683e, 0xab7f21b7, 0x60d07ea9, 0xf6abf185, 0x58ff7a95,
9990 0x561fe47f, 0x19f03bea, 0xa95df885, 0xcb62bfd1, 0x5d91377d, 0xfb1bf4ad,
9991 0x6cafbd41, 0xf6d5ced4, 0x1f13d7f8, 0xe78ddbb5, 0xccafa91a, 0xeb0cfaa7,
9992 0x75d50f31, 0xaa5bfb71, 0xd8d95f58, 0x1ffefc65, 0x2495f637, 0x81bf2d60,
9993 0xd72e4756, 0x4e7f10ce, 0xfd59e7d6, 0xf56de436, 0x8ba2cdf3, 0xc8a76ce0,
9994 0xf5d1ebe2, 0xb61e7b10, 0xd15b31a4, 0x46e575fd, 0xc3c7d58e, 0x364bdffd,
9995 0x7828e889, 0xbdd58329, 0x7ab3af58, 0xd9881d03, 0x86ca016b, 0x3d7bfb43,
9996 0x426b9225, 0xe777af3c, 0xff4f5489, 0x67049d75, 0xf4fa512c, 0xdf9abe7a,
9997 0x3ea56551, 0x93ec7ee9, 0xef210ec8, 0x37bc72e9, 0xfc05b0fd, 0xaa043fb8,
9998 0x9ace863e, 0xf33e5d58, 0xe49e4ec8, 0xfd518fcf, 0x026996d9, 0x0e1e4621,
9999 0xa3080c61, 0x4d36f5f4, 0xa979097f, 0xf144fd86, 0xe4fdc32a, 0x7ec35cd2,
10000 0x2b69239b, 0x0a4501e1, 0x8e284b7a, 0x48a4efab, 0x20f70c53, 0x5fb8ff84,
10001 0x437189ae, 0x64c39cd2, 0x15ce15cf, 0x3690de6c, 0x9e78d0b7, 0x5f13cb5f,
10002 0x87b833b6, 0x657f957c, 0xe675e836, 0x7e9e1180, 0x10921db4, 0x39a8e3af,
10003 0x00a16e6e, 0xc13625d5, 0xd5ca5df8, 0x4c0262ec, 0x861bcc30, 0x961ceee5,
10004 0x0945d92b, 0xf720c8fc, 0x1ea1b978, 0x3434dd58, 0x422a29c1, 0x7d630f54,
10005 0xd467f946, 0x259fe518, 0x7e3de51b, 0xd9de5185, 0x5f79464d, 0xab9462dd,
10006 0xcdca315b, 0xe1a671b3, 0x4af6c4fc, 0xf3793c03, 0xd7f3860d, 0xe01817f8,
10007 0x376fdba9, 0x71d69f9c, 0xa0bf61af, 0x5f61956b, 0xd9cbb3b7, 0xd581b5c1,
10008 0x0266f671, 0xa0ec15d3, 0x0643f0e8, 0xff7af17c, 0x12aaf831, 0x47a5ce51,
10009 0x48c2de51, 0x1484703b, 0x6f1878a0, 0x57faf107, 0xaadff4e2, 0x93f793e5,
10010 0xee4e3ece, 0x8f412f3a, 0xa0bcda7f, 0xb1fac2dc, 0x55690a7f, 0xcb567489,
10011 0xaf2d3e6b, 0x644df6c1, 0xa973e024, 0x0f1418b0, 0x3c2b1c52, 0xbb22abe9,
10012 0x1d350e2c, 0xe4a0f644, 0x32557b6c, 0x7040979d, 0x4b47538d, 0x5296fe74,
10013 0x72b1cc0e, 0x8f366742, 0xa171ca8b, 0xe327cad2, 0xfd6fb2e1, 0x54ecc96d,
10014 0xcfa7c33a, 0x3552b87d, 0x1c97cc6f, 0x47918e60, 0x4f9ea945, 0x5d5e8cbc,
10015 0x089cfaee, 0x52b07deb, 0xfbb26fbd, 0xd5a3dcdb, 0x9e66e237, 0xab325fd5,
10016 0x32710ec7, 0x6add1f9b, 0x7d90e60f, 0x5f90c99f, 0x317cc5c9, 0x56051268,
10017 0x36a171bf, 0x8c4c2a62, 0x6e52f251, 0x9f512f9b, 0xcd2aed86, 0x8bf21727,
10018 0x465e2be7, 0xa2542bbe, 0xb7f4c5b6, 0x99de5727, 0x739e794b, 0xbbc22fad,
10019 0x973ccfef, 0x9fcc7943, 0xf7a2ed2c, 0x1921e787, 0xd9c617c8, 0x48504990,
10020 0x1c43ca04, 0xd1ce2feb, 0xfc623323, 0xe585a376, 0xadfad02b, 0xe939353b,
10021 0x0d12d6fd, 0xb13e2f6f, 0x9df8e302, 0x3c98875d, 0xb407336a, 0x7449ad3e,
10022 0x4df7fbe1, 0xbf521670, 0xa8915209, 0xff7ae9f6, 0x3eff9e35, 0x57ef5579,
10023 0x36be772f, 0x07d0dfb3, 0x51b48ec3, 0xf3f18de7, 0xeadf28ac, 0x258fbdfb,
10024 0xfbd3fcb0, 0x1f9b3658, 0x641fdf46, 0x9b3b8173, 0xc7d8303e, 0x1b1f2ddd,
10025 0xe51eeeec, 0x287ec313, 0x8f19623d, 0x64f687fc, 0xe503b9cd, 0xadb77e77,
10026 0xd450fa84, 0x4c6e7f57, 0x627a1c9f, 0xf7c26cf2, 0xc73cf9bf, 0x1759e8e8,
10027 0x9d34f364, 0x4eebd3cf, 0x2eb43832, 0x3e78d6c4, 0x5f55bef5, 0x3c837fad,
10028 0xc227ea33, 0x9b47118d, 0xd479d4c3, 0xd667beba, 0xc3ca4ab8, 0xb356d93d,
10029 0xe1524eba, 0x0abb52ac, 0x6b4b99cf, 0x48dce2d8, 0x070f6b7d, 0xd0f68712,
10030 0x9785d57b, 0x7744f8ac, 0x50f56c86, 0xb9195a5d, 0x482b7340, 0xe379b10f,
10031 0x41d954d2, 0x062c39df, 0x9d1952b3, 0x383fa893, 0x035e526b, 0x2f25018c,
10032 0xf53e71fe, 0xaa498301, 0xf8be27dd, 0xe9057cdc, 0x97c5257e, 0x0a40f74c,
10033 0x94e76359, 0xfa859cfa, 0xc253ea62, 0xf0cd750e, 0xcc8f8c70, 0x478a75b8,
10034 0xd3d7578d, 0x9af5ef8a, 0xe47126da, 0x80dacf0f, 0x07e8a7e6, 0x4317d512,
10035 0x1faa6cfb, 0x70920198, 0xdb6eccff, 0xe3cf640b, 0x5faa6690, 0x7d635ab0,
10036 0xb65be141, 0x7d09c500, 0x11ee933e, 0xfbc5e57e, 0x6c2d7be9, 0x2898300e,
10037 0xd77f9094, 0xf5601d27, 0x595c89d7, 0x15f9b0f2, 0x7a3f1448, 0x6eb6d8f7,
10038 0x3991e752, 0xafff120b, 0x0f12b873, 0x6a4233eb, 0xe1cda95d, 0xf9abbe74,
10039 0x43df19c7, 0x7c406d9b, 0x7c1a5f9e, 0x4ee6cbca, 0xd9d10e62, 0xd6e9526b,
10040 0xd3f9d5e9, 0x73be88f9, 0xe7d5bb65, 0xd779d149, 0x07e44986, 0xce754728,
10041 0x2f7773c7, 0x7dfee518, 0x7cb2beba, 0x558f88f3, 0x2dbcea4d, 0x07f6f7aa,
10042 0x8ede914f, 0xbb1c5938, 0x3e78fddc, 0x611ff7eb, 0xef3e40f2, 0xf862fe22,
10043 0x9989e25c, 0x3eef9e0b, 0xf85794f1, 0xb385fce1, 0xf878f9d5, 0x02398b85,
10044 0x77dfafde, 0xc9d924e8, 0x6e3c1cf0, 0x831b6d8e, 0x68ea657d, 0x0acc6bf3,
10045 0x4d92f531, 0x6cc13fbf, 0x9f218fbc, 0xfc8bacfc, 0x5d89eb11, 0xf9421f5a,
10046 0x9eb6e292, 0xb1d9772f, 0xe2df454f, 0xb8b36f42, 0x8ec9784d, 0xcb0a73d7,
10047 0xa15cfa5b, 0x44bcc38d, 0x599b963a, 0x76afe73c, 0xbba7648a, 0xd482f6d0,
10048 0x04a59ad7, 0xeb8e3f36, 0xe4dbd76f, 0xd65ec947, 0x4199507c, 0x3be76ffd,
10049 0x957d6837, 0x6ba64f9a, 0xf09d39f6, 0x64de1f13, 0x358a5796, 0x4dec4afa,
10050 0x3321d53c, 0xf9d5e140, 0x788f3681, 0x8fd66dec, 0x775717fd, 0x1c70ea99,
10051 0x00001c70
10052};
10053
10054static const u32 usem_int_table_data_e1h[] = {
10055 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x33a98f8a, 0x32e8f430,
10056 0x31e8a430, 0x43d4dc30, 0xcf12d388, 0xbf4ca2e1, 0x83030b30, 0x038b1028,
10057 0x7f1024b1, 0xf8606463, 0x7ebc48ce, 0xbb04115e, 0x81818045, 0x070fc80f,
10058 0x1905ffd2, 0x330b3e18, 0xf903f030, 0x6dfc80b3, 0x88087c40, 0x376280c3,
10059 0x2067f480, 0x02c40fbe, 0x17cdf822, 0x417f2024, 0x07ff9508, 0x1042ff8d,
10060 0x61637ebf, 0x0496f2fc, 0x4de1b1e4, 0x0f8cdc04, 0xef40a77f, 0x6a87e040,
10061 0x557d7ca8, 0xa02b0606, 0x843a8758, 0x7e4908ff, 0x40cc5016, 0x93e6c215,
10062 0x05506067, 0x61ab1ff2, 0x281f9737, 0x5f9406af, 0x00073506, 0x15e5ac6f,
10063 0x00000368
10064};
10065
10066static const u32 usem_pram_data_e1h[] = {
10067 0x00088b1f, 0x00000000, 0x7dedff00, 0x45147809, 0xf4f570da, 0x73264cf4,
10068 0x10909264, 0xa70930ae, 0xe15c380a, 0x1084ca30, 0xa8ea2416, 0x1388a888,
10069 0x2e421081, 0xf57175d1, 0x11c3a7fb, 0x9e375941, 0x1d47facb, 0xa22cdc10,
10070 0x60188806, 0xb200c1c0, 0x1761bb8a, 0xc363d715, 0x01921a0d, 0xe5c58f15,
10071 0xeaadf7ab, 0x44ceee99, 0xeff3eba2, 0xe3fdfb7e, 0x575453e3, 0xef555bf5,
10072 0x5dbd6f5d, 0x71024a31, 0x02e426f6, 0xf211c6fc, 0x4908488c, 0xe36d9689,
10073 0x1749c7c3, 0x92cde442, 0x8840ad6b, 0x343dbaf0, 0xfb21046e, 0x33010956,
10074 0x587687ad, 0xd3f5a109, 0xcc07d735, 0xd43eb419, 0x9afac1ec, 0xbee7ac1c,
10075 0x48c3aefa, 0x8aafa5eb, 0x761ba846, 0xdb34729c, 0x37372908, 0x7d05723d,
10076 0x24557e1e, 0xc450e9ab, 0xb240c535, 0x471e3908, 0xad196fd8, 0x685212a7,
10077 0x55d2d561, 0x3cc2673b, 0xc4cc1a8a, 0x6e94e142, 0x15ed7b99, 0xaf773eb4,
10078 0xe94ba044, 0x77534ada, 0x10179f5a, 0x68bea0ea, 0x4e3887c7, 0x545278db,
10079 0x4f908837, 0x35c471fd, 0x4d1dd680, 0xe7d137a9, 0x130d81c5, 0x7af17fa1,
10080 0xfda06dc1, 0x7e766b8b, 0xeb8bf004, 0x8522bea5, 0x4ad6bf3f, 0xd8d9035c,
10081 0x63ac0817, 0xdf30b5ce, 0xc4483fd2, 0xe745eb4c, 0xc01136ef, 0xe4dab191,
10082 0x8ff8c3b5, 0x18765c9a, 0x51c716a7, 0x7bfa59f0, 0xaf7d0e3a, 0x0dc165ec,
10083 0x10332b4b, 0x75a7cc1f, 0xf3fa658b, 0xa5575836, 0xbfbc3fa9, 0xf41341e5,
10084 0xd8281b9b, 0xfcc1716c, 0xc2269956, 0x99566b3c, 0xe145070a, 0x517dafcd,
10085 0x2be3af33, 0xa9f574fb, 0xa7e5f5da, 0x735a8a7e, 0x884c5eb4, 0xf306cea7,
10086 0x1fae980e, 0x547e7d1c, 0xcf7a4448, 0x2b8915af, 0x529f0a2e, 0xefcb9f1e,
10087 0x1f027fd2, 0xd607b76c, 0xb5e94466, 0x8eff09c0, 0x93acebd2, 0xce18cfd3,
10088 0xca57c352, 0x740e8047, 0x277ed53e, 0xd3f98f96, 0xefc27cb0, 0xe53dbc42,
10089 0x4ae5881f, 0x3f9f1bbf, 0x658d1fed, 0xe583df8d, 0x5849feb3, 0xec5efc06,
10090 0x1d3fdab7, 0x1f7e35cb, 0x5fc17f3e, 0xbfad6584, 0xf3af9f02, 0xbd72c42f,
10091 0x2fe7c65f, 0x596197fb, 0x72c6afe7, 0x96257fa3, 0xf600fef5, 0xd7e9ccdb,
10092 0xe7c3afe0, 0x580dfd5b, 0x2c21fd06, 0x62f7f877, 0xd5e382b9, 0x8c724d91,
10093 0x0f0e2f14, 0x20715271, 0x1c9ef949, 0xbc93d689, 0x433a9eac, 0x7ad131ce,
10094 0x29d68faa, 0x8497ba9e, 0xdeb4cc72, 0xa7b582bd, 0xc7c6403f, 0xccba7ad1,
10095 0x785733da, 0x3d685bc6, 0xf7b59ab3, 0xc7c791af, 0x00ff7ad3, 0x7d74bf6b,
10096 0xd695bc68, 0xed63ad2f, 0xd7248243, 0x4243eb46, 0x9f6c3eac, 0xeb4ed727,
10097 0x3d589ac3, 0xd73923eb, 0xcd59eb41, 0x2db1fdec, 0x5a04dca1, 0xed661b1f,
10098 0x166f9d57, 0x67f8315d, 0x459be4b3, 0xf2032d28, 0x1bb18f14, 0x777c9bad,
10099 0x97c53713, 0x1c63d53c, 0xc923f143, 0xbe4bbed8, 0x4c1bdb1d, 0x27bfb632,
10100 0x56fb6217, 0x27ed8029, 0xdf6c72e5, 0xfb600a6a, 0xac42f2b7, 0xb610a507,
10101 0xb12b2adb, 0xc214d07f, 0x87caf4f6, 0xd4877db0, 0xcaeeed8c, 0x877db1c7,
10102 0x1fdb19a9, 0x99e3525b, 0x0b0feb40, 0x2f81a7be, 0x22be0b17, 0xadf807d2,
10103 0xf94bcd2e, 0xd3204aad, 0x0117bf81, 0xaaf6d253, 0x47d4266e, 0x7ace3f9b,
10104 0x6f38145e, 0xe17a8176, 0x20650f0b, 0x8e11e79c, 0x1788e144, 0xc9f59387,
10105 0xac9c0d68, 0x38148a4f, 0xa58e11eb, 0x7f367073, 0x9f3b5632, 0x38158a4f,
10106 0x149192af, 0xeb73bd8e, 0xb65bfaca, 0x2b7f3e76, 0xc0ece051, 0x6e7624f9,
10107 0xb4c70d3e, 0x163869f8, 0x389bcfc1, 0xcdce949f, 0x2d71f467, 0x8f1f467e,
10108 0xe109a7e0, 0x9c1ceb74, 0xfc5ae386, 0xe08f1c34, 0xd38403e7, 0x1aeb73ab,
10109 0x9f8b427d, 0xf82227d1, 0xc9f88c39, 0xad9c1ce8, 0xd9f8b5a7, 0x9f823a7a,
10110 0xbf4e10cf, 0x6c6badce, 0x633f16ab, 0xf9f8235b, 0x4975d702, 0x6d6ce0e7,
10111 0x6b67e2d5, 0xdf3f046b, 0x9dc19c21, 0x36d8d75b, 0xb6c67e2d, 0x1263f045,
10112 0xced0ce00, 0xa5f827cd, 0x2fc13f16, 0x4049f823, 0x373b2338, 0x5a73ec9f,
10113 0x8b9f64fc, 0xe10d27e0, 0x9c1ce98c, 0x7e2d39e0, 0xf822e782, 0x573840c9,
10114 0xd95d6e76, 0x93f1695f, 0x3f0455fd, 0xf7400a97, 0x421f3e1c, 0x863bd8e1,
10115 0x2d3be3b3, 0x177c767e, 0x9c70cfc1, 0xcf9f1e4f, 0xf55ce045, 0xae7e2d0f,
10116 0x3f0447fa, 0x726708d9, 0xf8ece0e7, 0x3b3f1687, 0x4fc111fe, 0x9aebae1e,
10117 0xaaebadce, 0x5cfc5a0b, 0x67e18175, 0xdcbad1d4, 0x6d4eda04, 0xafa45ba3,
10118 0xf1ef3b8c, 0x3a2eb408, 0xba745d59, 0xa22df809, 0x26908fe2, 0xb7df488f,
10119 0xf61c4fad, 0x25fb5110, 0x75826fe3, 0xa697a9d9, 0x46124bf6, 0xa0fc6bc7,
10120 0xa6924f44, 0xbba93c9e, 0x378a7fa6, 0x75ded353, 0xf69aa5fa, 0x9a61be6e,
10121 0xb1a28f7a, 0x2abdfe9a, 0xbdea6bc6, 0xe9ad5e17, 0xa0df219f, 0x7659f7a9,
10122 0xbf7fa6ab, 0xed353bea, 0x6b165603, 0x2c092fda, 0xab2fd4d0, 0xffa6a5fd,
10123 0x9a45bae0, 0x1e1bcbf6, 0x0d0fb4d2, 0x0fa9a63d, 0xa6b4fbdf, 0xd5a6c8ff,
10124 0x0751f69a, 0xc7da69d7, 0xd4d46f34, 0x55b938af, 0xf0caffd3, 0xb8fa9a1b,
10125 0xf4d2dfaf, 0x1e7394a7, 0x45d78cbf, 0xfb820b90, 0x099bb902, 0xdd90c5fd,
10126 0x77537584, 0xd827db1b, 0x29475d0b, 0x9f064ddd, 0x812d0bab, 0xfdda84e6,
10127 0x0345ee9c, 0xdc5f299a, 0xc037d63b, 0x6bdf9f49, 0x8cee5df2, 0x7e509fe1,
10128 0x941a4811, 0xfa94032e, 0xc62507f6, 0x9c7be3af, 0xbe887fef, 0xf7086e5f,
10129 0xbff5a44f, 0xc002721b, 0xd4082fdf, 0x157ca7eb, 0xe80a922f, 0x1e266f17,
10130 0x3307dfe0, 0x55979eb2, 0x17acbcfc, 0x0a215395, 0x4be49977, 0x5d643f03,
10131 0xf832bbe5, 0xe8bd5529, 0xf213baba, 0x486ef0a2, 0xefdf4bee, 0xa3e69855,
10132 0xea26ccf0, 0x37c7abe7, 0xe107f1d1, 0xcfc075f8, 0x94fc619b, 0x339be3f6,
10133 0x8fc66b47, 0x8cd22f4b, 0xe3a2671f, 0xafbea93b, 0x4f8f98fc, 0x90963289,
10134 0x38c7c26d, 0x08bd39be, 0x44d07fc7, 0xf1ea3df7, 0x87e323e3, 0x3a7bfd60,
10135 0x58e67f5a, 0x8bd3faed, 0xb137ebb5, 0x7955bff5, 0x8f1f8f8c, 0x385b7feb,
10136 0x5e9fd6c6, 0x666fd6cc, 0x3be32370, 0x826ff822, 0xd1d7bff5, 0x6b64fbfa,
10137 0x44bbdfd7, 0x1b337ebb, 0xa795afff, 0x1c36f8f9, 0x34e143ff, 0x12ef7f5b,
10138 0xf664df1c, 0x4c7f81b9, 0x022be23d, 0x93d27c74, 0xc0aeae2a, 0x281c742e,
10139 0xa6512607, 0x2149e427, 0x6f71e713, 0x73b7e33c, 0x50df94f1, 0x9cf8c91f,
10140 0xa3e6a804, 0xce329cfb, 0xe7d7f3fb, 0x616f4098, 0xccefdd3b, 0xdd9d53e1,
10141 0x937f2220, 0x7e81cc27, 0x0dadbe74, 0xd9f50ca2, 0x00195c4f, 0x266e58fd,
10142 0x3de17877, 0xf3c10923, 0x5e0e4f63, 0xbe975ead, 0x1d2d539c, 0x17c8d66f,
10143 0x9e3c8f9b, 0xf3a0ac0c, 0x182603cb, 0xa71fad19, 0x98d829fb, 0x12fba61e,
10144 0x74484f28, 0x28fcfa3c, 0x01916fdd, 0xc4a9b96a, 0x79ec88f7, 0xff9d2fb7,
10145 0x3cfca234, 0x51dbceb8, 0x233c28a4, 0x1af1ffc3, 0x98f40021, 0xf9f74d53,
10146 0x372ff92a, 0x170ef933, 0x02d58108, 0xff7d2bc7, 0x813efe66, 0x33f851f9,
10147 0x8f9dec9d, 0x47b35c77, 0xedfdd070, 0x9c0d64ca, 0x6960485b, 0xb6ff7d1a,
10148 0x62253b15, 0xe828be00, 0xe5f800b5, 0x7084897e, 0x429cda9f, 0xa0667106,
10149 0x064e7df0, 0xd2e9e6ff, 0x9c1566d1, 0xc79c5299, 0xf333e74b, 0x7be7113e,
10150 0xdedb4f8b, 0x31eac3bc, 0xcae5a10c, 0x494225cf, 0xb6915b7e, 0x6d0af6fd,
10151 0xda858efd, 0xee0f5d3a, 0xfd640bf3, 0xba1cba73, 0xeb233bce, 0xf5a70ba6,
10152 0xd66dbc59, 0xd0d64932, 0x4d736e91, 0x133dbc59, 0x4f104ed0, 0xf69f7ef8,
10153 0x681f29fd, 0xea5773ea, 0xf8be71e0, 0xdffff4ff, 0x86f2ff4d, 0x5547c59c,
10154 0x9bad2af3, 0xaaa8f8bc, 0xebdafcdf, 0x8179f535, 0xe7fd345b, 0xb4d02cae,
10155 0xa79ea9cf, 0xecb59f69, 0x40bd4d2e, 0xffd34fbe, 0x9a95858e, 0x962bdbf6,
10156 0x2b6fda6b, 0xbf53547a, 0x4d5bf7c5, 0xafa79bff, 0x3b0bb4d2, 0x466ef5e6,
10157 0xddebe9bb, 0xf4fe928d, 0x7c026607, 0xc2b3f0a6, 0x69fd27ef, 0x77ea7e58,
10158 0x7a095961, 0xc377ea98, 0xaf965616, 0xfa0de82e, 0x13ffe15c, 0xe83a4552,
10159 0xeb3f3d4b, 0x4f9eaff5, 0x2c47afe9, 0x4b29433f, 0x3b05e204, 0x64fdc6d6,
10160 0xdc37f9e5, 0x0ce782ce, 0xc9898965, 0x6ec6c965, 0xea0389e3, 0xb615fea1,
10161 0x3a92e18e, 0x2041d701, 0x74029a4a, 0x976d41eb, 0x347dae9a, 0x29d96cf3,
10162 0x2065f8e2, 0xdcc06393, 0x60187778, 0xfa6350fc, 0x3e61838d, 0xdeb1d79e,
10163 0x56fe8290, 0xe2d27f8b, 0x7f00fda3, 0xfa4f2c5e, 0xdc7963a7, 0xa8f2c3ef,
10164 0xc3cb08bf, 0x9b2c0afe, 0xfcb10bfd, 0xf9632fc4, 0x96197f91, 0x6357f57f,
10165 0x12bfd079, 0x01fcf7cb, 0x1efd5b2c, 0xfd3e152c, 0x18eba14f, 0xae9cbfc3,
10166 0x3ae9a8df, 0xf364e0c6, 0x187d74e1, 0x6fc31be6, 0xc8ce0fee, 0xe23f9548,
10167 0xdb718c99, 0x4ece3c05, 0xc71624c8, 0xa62f63e5, 0x6fd09ae0, 0x3d040c09,
10168 0xb7e0767c, 0x7d4e21fd, 0x4a2520f6, 0xd3ebc746, 0x3c43afd3, 0xeffa0f10,
10169 0x974a0185, 0x96edf6e4, 0x8b578678, 0xc3224c81, 0xefde5908, 0x839df705,
10170 0x49246eb0, 0x7dc07ef0, 0x5c063dbd, 0x7e020bea, 0xc5d7862f, 0x004373f6,
10171 0xffa7f1de, 0x18e5059e, 0xe307f303, 0x4bf4451b, 0x3779e849, 0x67a237e0,
10172 0x8834eecd, 0x99fb86f7, 0x9af7689c, 0x4fe2d6ae, 0xbf835abe, 0x55fc11e5,
10173 0xfafe21a7, 0xc28ffb9e, 0x8784f11f, 0x8a3830dc, 0xef846fbf, 0x1e729fc7,
10174 0x36ef1fa3, 0xf883f8d1, 0xc1552db2, 0xa13a536b, 0xf811fce3, 0x5b3fc29f,
10175 0xf001203f, 0x1173811c, 0x7faf08fa, 0xe8fa0e9c, 0x16c9d034, 0x0e9f7785,
10176 0xcfbdd9de, 0x5fefc03b, 0x47ca2690, 0x2959e063, 0x6432eb4b, 0x6a4fda9b,
10177 0x56cfd6d0, 0xd0ea930b, 0x4c25719f, 0xd7fa0c1d, 0x40951f29, 0xa961a64f,
10178 0x669059c0, 0x7d2871c2, 0x4faf5c98, 0xd4ffb944, 0x7efd871f, 0x047479ea,
10179 0x7a8f3a27, 0x0fbe8472, 0x4fa17f2c, 0xe43bfdc7, 0x2617e353, 0xa091b388,
10180 0x97fc0e74, 0x05fffa38, 0x46237838, 0xcb702bac, 0x7cd944eb, 0xaf5f3c39,
10181 0xe7be8f19, 0x2f06ce52, 0x3c9f7e64, 0x8571c918, 0xa8a9a95f, 0x48d61881,
10182 0xac8b5be0, 0x35128ff5, 0x6e86f2f5, 0x825fc6b2, 0x4a3d507f, 0xf023048a,
10183 0x9f67094b, 0x996da336, 0x0bf7e740, 0x3e816208, 0xd2bf5810, 0xcf9366b8,
10184 0x78b2fc05, 0xe82e15da, 0xd5eb8d59, 0x2fd28fcf, 0x3c7528c3, 0xd9e2f9ff,
10185 0xe431bd7b, 0xdbd72763, 0x57160625, 0x03b27120, 0x9a48d7ce, 0x8ec1b8ec,
10186 0xf045b353, 0x3a3b7183, 0x0a0f0a8e, 0x2901799c, 0x995ff5ac, 0x5818b65c,
10187 0xee3f40bc, 0x94dc619f, 0x6cafe38b, 0xb089fefd, 0xcb1e3d6e, 0x7c98ce1a,
10188 0xbff45728, 0x151e28ac, 0xf442fefc, 0xeba459fe, 0x843dae2a, 0x9293eafb,
10189 0xeffeffdc, 0xe7ed8bd1, 0x6e3b4b6f, 0x265bad55, 0x9dce304d, 0xc440f9a3,
10190 0x5487f375, 0x5b7a9f5f, 0x5d010f22, 0xaa5ed3ce, 0x828f5079, 0xfea2b218,
10191 0xf3f59dfa, 0x9f7ec1f3, 0xf7053cda, 0xd789b32b, 0x22ca4101, 0xfe059d52,
10192 0x986269f9, 0x4d3a7804, 0xae18ecfe, 0xd139d3a2, 0xfea1f484, 0xfcf561fb,
10193 0xa9aeffa8, 0x535dff53, 0xa437242f, 0xe178f9c2, 0x08091213, 0xfb4d3eb8,
10194 0x7089d171, 0x2a8a92e7, 0x4b1677f0, 0xe9dfaecc, 0x541ec624, 0xf6be979f,
10195 0xad01564c, 0x7f32277f, 0x9def3944, 0x377b7547, 0xb75c5eda, 0xeda1e4ca,
10196 0x4f87ea47, 0xfbc082bb, 0x3fb02a81, 0x7b82abf2, 0x7e3dabad, 0xf5fce87f,
10197 0xa1fc55f3, 0x7ccee776, 0x82b5a51e, 0xcf831027, 0x67c646ac, 0x30f63f0a,
10198 0x8df1353a, 0x70faba01, 0xae9c7d5d, 0xbde5a3fe, 0xfbc8d10b, 0x00df442f,
10199 0x6f930a63, 0xc609dfd8, 0x8ff3f230, 0x0ed69f86, 0x149ff0fe, 0x9cad4f7e,
10200 0x7ee3f851, 0xdb7df852, 0x2c4a7fcd, 0xbdafa5f8, 0xfaa659b4, 0x2795f8a9,
10201 0xa7ea841d, 0x54eac653, 0xc97fa537, 0xe00ea5da, 0xd9469383, 0x2a7cfc01,
10202 0xc40a4e20, 0x8c8b77d0, 0x3daff702, 0x6fe20136, 0xff0a4ff0, 0x5f0f75d3,
10203 0x7387710b, 0xc627256b, 0x21cd6ad5, 0xb2d39533, 0x64f979fa, 0xb10fd608,
10204 0x446783fa, 0xf96837a8, 0x4f77f8b3, 0x5f50baa6, 0x180c3dca, 0xffa10e3f,
10205 0xd8e6b65f, 0xe5fbb044, 0xa6728c24, 0xffc60f7f, 0x53ed093a, 0x7da12981,
10206 0x53e46e3b, 0x2bf67de1, 0x8cf87faf, 0xf27280e8, 0x7427d009, 0x03f184e7,
10207 0xdc457bfd, 0x68dbbf9f, 0xf3f182ef, 0xe8146451, 0x242f0531, 0xf179fcc0,
10208 0x408667b5, 0xcd65b51c, 0x85410edb, 0xcede452f, 0x6e7acdd6, 0xbd63abab,
10209 0x51e54ad9, 0x7e2a47ed, 0xef81ab85, 0x2cac8243, 0xc80e4291, 0x255929ab,
10210 0xb8fa65b9, 0x5fe7a5e4, 0x9ae21a78, 0xfddd981f, 0x2ff9fc28, 0x2c6f7eed,
10211 0x20dfcfad, 0xcb67c975, 0x51a909b0, 0xffd394fa, 0xd28b0e17, 0x6ed378a3,
10212 0x7b306b93, 0x945240fe, 0xec37f32e, 0xedc19134, 0xb75b91f1, 0x8b6cd4d3,
10213 0x43ba9f41, 0x130fc113, 0x04cefb5f, 0x43b53ff4, 0x62335d20, 0x6ed573e0,
10214 0x4f00d3f4, 0xaf4e4f48, 0xfd74fd08, 0x405d29cb, 0xa5e9ebaf, 0xf41537ef,
10215 0x0b830a4b, 0xbf9412f9, 0xf90ade5f, 0xbb357f48, 0x2f450f01, 0xf580eddf,
10216 0x3056309c, 0x69667f3e, 0x5f8e87aa, 0x4ea9c924, 0xa2f3d92c, 0xfc8e7f67,
10217 0xcfff7737, 0xcb5c5953, 0xb680cdd3, 0xeb06ee4a, 0x1373539c, 0xf890b3ae,
10218 0x9e8b0f90, 0x2fa0bd11, 0x499234bf, 0xc9c8621b, 0x4e4e5cb7, 0xa5c4a6ac,
10219 0xcd413ceb, 0xfce9e610, 0xc5ac0c59, 0x185dfa38, 0x5f39fb37, 0xb0e8f50b,
10220 0xa31c65fe, 0xc0d19357, 0xeaf52ef5, 0xe6bbfcd5, 0xd3a026c1, 0x5d3cbda7,
10221 0x9ca5fce1, 0x0f8e6518, 0x2b8502e1, 0xcaebcfee, 0xc65c44e8, 0xf51efe2c,
10222 0x39e172cb, 0x3c926ff4, 0xf79a2196, 0xe88c85c8, 0xf1f0f7f8, 0xc1e3bce9,
10223 0x1a913a9f, 0x40305f7b, 0xb502ec52, 0x533e2aeb, 0xff933bc9, 0xbc99cb35,
10224 0xb81ff22b, 0x7fb4127e, 0x11c98071, 0x92f607bc, 0x15d42bce, 0x154e77db,
10225 0x49983f50, 0xaf9c9628, 0x6b9cb891, 0x42fcf5db, 0x12146fe7, 0xe3037c54,
10226 0xd01d2124, 0x827c2a9f, 0xa3d2afbe, 0xa3ae30e5, 0x8e455c3d, 0xf07d72e7,
10227 0x6b03e825, 0x1a901f54, 0xf63a07a6, 0x53c4657b, 0xe1781489, 0x2a5f9069,
10228 0xe40bb2af, 0xfac2f257, 0xf8df5b3f, 0x6e54adde, 0xe453ab3e, 0xf557ab56,
10229 0xf1b45b72, 0x54f804e7, 0xf59fb72f, 0xe53120ac, 0x298f3e96, 0xff9b3db7,
10230 0xc1557a25, 0xd5a4ba63, 0xec9e8aab, 0x3d7a9f08, 0x42e8c5b9, 0x24f5eabc,
10231 0x59201dfd, 0xe151f9ed, 0x8aff8543, 0x0ded2c5f, 0xa7c228fa, 0xf8461f0a,
10232 0xfd43e154, 0xd478b5ba, 0x9e7c63b7, 0xcb778bf2, 0x507b13bb, 0x050496ba,
10233 0xef85d9b7, 0xc53a81ed, 0x0b6d8797, 0xe8f4f7aa, 0x7407aea2, 0x7f5d3af5,
10234 0xd5eeae8f, 0xeae9f7f5, 0x01feba15, 0x68694fb6, 0x87e41134, 0xb4bfa690,
10235 0x9f90c888, 0xe22ede16, 0x9d1b41b9, 0xbf7d1573, 0x40467d6d, 0xa961faa6,
10236 0xc3dbed85, 0xd02aa629, 0xb0ce6d67, 0x16ea0923, 0xf36b7f16, 0x2a891d86,
10237 0x5050f1ff, 0x1cdc7d44, 0xed629320, 0x8bc7a85f, 0x1d266bf4, 0x90f3b3b5,
10238 0x10c778b6, 0xb44f2f18, 0xf8842fa5, 0x86e8b54c, 0x95d98e23, 0x5ce03b37,
10239 0xe7d82da2, 0xf9f4e9ba, 0x2c883f9c, 0x18f6422d, 0x0df6a9bb, 0x54fc8927,
10240 0x95f900b6, 0xb3fe902b, 0x311f6c82, 0x7e6c457b, 0x15efe62e, 0x8131eeda,
10241 0xfffea4de, 0x5f5c7561, 0xa3545381, 0xc29c1e7b, 0x2fed9ef9, 0xdb68d78b,
10242 0xfa3f7c7d, 0x0fdf0a5f, 0x7ed94325, 0x0838b090, 0xe279bbd7, 0x53a6eba0,
10243 0x15edb43a, 0xd9cdf009, 0x387488a0, 0x40085ebb, 0x29c88a5c, 0x24653f28,
10244 0xc14efa8c, 0xc7c80b57, 0x50f58e80, 0x671fabcb, 0x94bb4fdd, 0xc870fe6c,
10245 0xcb65a5ff, 0x6ffa0fe6, 0xef6bfa83, 0xda487fa7, 0x61ddcff7, 0xb6df73c1,
10246 0x27cc761d, 0x4efedb6e, 0xdf50fdfa, 0x3cc37662, 0x357c76db, 0x6da8f804,
10247 0xf408b991, 0xb62f5b58, 0xfdbc59ff, 0x68cd21ab, 0xfd20973f, 0x8b13256a,
10248 0xfeff04d7, 0x4a05d089, 0x0ff02aba, 0xf9727e78, 0x20804b56, 0x7cb2affc,
10249 0x3d6e9fb6, 0xbf9cfc65, 0x6fa64ecd, 0xb225f984, 0x6df2ec73, 0xa4af9e63,
10250 0xefd697e3, 0xeda2cd34, 0x377fafb9, 0x3791f304, 0x55a7bf32, 0xce167e6a,
10251 0x6f4937b1, 0x9e28922e, 0xba38415b, 0x299d7213, 0xc5b6572e, 0x1877cbc2,
10252 0x3e2cea97, 0x7ed892de, 0x1f1fdff4, 0x9511e602, 0x3881ed04, 0xcdfdd601,
10253 0x3e821f27, 0xbe4661d8, 0x59fbd654, 0x23fa255d, 0xa9f75b17, 0xd07c31ff,
10254 0xa10b75d9, 0xce3bacce, 0xeebdeff4, 0xce172447, 0xed072f4f, 0xbdfb7cf9,
10255 0xeec97f58, 0x9276f9c6, 0xfe9a07df, 0x237df8c3, 0xe2e3bba5, 0xbfd9feeb,
10256 0xa63bbaf9, 0x72661ffb, 0x1f213bba, 0xeff5fcac, 0x543f7e70, 0x1ffdcdcf,
10257 0xbf8af7ca, 0x9b78366e, 0xa6fce872, 0x383b6a93, 0x9ca4b716, 0x73a907dd,
10258 0x745f5ee6, 0xfc4af981, 0xbf3f51fc, 0xefb62695, 0x997ce093, 0x126e4b8e,
10259 0xed8f7ef8, 0xfee5ae93, 0x0b3db5c5, 0xd6bd2fd1, 0x6277fcc3, 0x46737af4,
10260 0x6cd89e40, 0xc943c637, 0xa83e83b0, 0xaf2574df, 0x7f8bf76b, 0xa0478814,
10261 0xe9b5f9fe, 0x9f82f693, 0x634f5d7a, 0x43caccc8, 0xe0ebbe50, 0xf76b47cf,
10262 0xb4f8b733, 0x6ba79bf5, 0x787137eb, 0xa2b9c0d3, 0x0af34fe3, 0x4a7f8801,
10263 0x81489ebd, 0x4734a878, 0xf9008222, 0x614b1524, 0x579370df, 0xb03dfefb,
10264 0xc5191dcf, 0x82b8bce3, 0x114e70f9, 0x7c405037, 0x4442b75c, 0x4837127d,
10265 0xd1def840, 0x1e1de612, 0x00b37833, 0x47c3f9cf, 0x8192fd95, 0xe77ac373,
10266 0x92157c71, 0xc877f40a, 0xb2170bf9, 0x4bee20b3, 0xe79a5fd0, 0xea1ae421,
10267 0x0b6617b7, 0x63c878a1, 0x61391231, 0x0543c418, 0x0f135872, 0x77e1d6d5,
10268 0xce146a55, 0xc477fac5, 0xf9753f8f, 0x87ffca37, 0x433fea25, 0x2cf3e789,
10269 0xb3eca7ae, 0x3c3208ee, 0x81089796, 0x90abe44c, 0xb0cf3ea4, 0xfdff1999,
10270 0x28e181ed, 0x1ebf3957, 0x7ff6c09c, 0xa0bbf023, 0x9e67ee72, 0x10095d95,
10271 0xec1b38f7, 0x72d1cfc3, 0xfc18be1d, 0xbbef9fbc, 0x007902fe, 0x209b6cb4,
10272 0xffe08b54, 0xfbc63093, 0xb21609e4, 0x5cbe4636, 0x8739498b, 0x207dc0af,
10273 0xa02cc4fc, 0xa5cdfb23, 0xa92426af, 0x9ae2b6e8, 0xed21c653, 0xc3bf00e9,
10274 0x7e4bce31, 0x3cfb096c, 0x4b7eebc0, 0x8c6f44f3, 0xcb83fef5, 0xdf1bfe6f,
10275 0x376377e0, 0xc0243304, 0x44130dcb, 0x39eaf9cd, 0x87e3f713, 0xaf30e193,
10276 0x3b2637fc, 0xf65d00c6, 0x4ef86e8a, 0xc6783cac, 0xce718be4, 0xc027c7a4,
10277 0xc90073c7, 0x3cf8085d, 0x810b2bf2, 0xfc3bd6fd, 0xe41067dc, 0xadc20f61,
10278 0x4ce207bd, 0x0b8b3366, 0x713b30cd, 0xe7e6379e, 0xdc742948, 0xa1cef541,
10279 0x9dd5f470, 0x46019ff7, 0x5124246b, 0x7e94f7b0, 0xbf584bdd, 0x59672643,
10280 0x113ff5ac, 0x733ae2c7, 0xd1defb89, 0xdd1fbfc2, 0x0f6d7e72, 0x327b078d,
10281 0xd8e77d81, 0xca09af9e, 0x4249d9c7, 0xec3df400, 0x2f9eb09f, 0xc779bda0,
10282 0x1be5dac0, 0xf8565e98, 0x11e78f5e, 0xf8cacf1c, 0x0c7d7953, 0xcf052f97,
10283 0xf3f57e0a, 0x7d53fa55, 0x8f1d4e35, 0xe861aeb8, 0xcb0f60cb, 0x40d38282,
10284 0x9b199541, 0xe587204d, 0x104a8f0d, 0xc5c5bf8f, 0x307b52e0, 0x3bfe7d44,
10285 0xe1ceccc3, 0x315d871b, 0xf3e4f813, 0xa12fd415, 0x9f667bef, 0x7ddd8071,
10286 0x13fee0c7, 0xff29077c, 0xbf6b2451, 0xe87d5f47, 0x904f1677, 0x703370d4,
10287 0xe496379e, 0xb93e1048, 0xd4a764ad, 0x334fc555, 0xaed849cc, 0xe25eef3c,
10288 0xe9cf061a, 0xf90f3878, 0x3c813311, 0x4d7541f2, 0x6ddbfdf8, 0x0f8c8915,
10289 0x9a76ea8b, 0xfd819eb0, 0x7194f195, 0x3534f2f4, 0x341f9b5f, 0x27b9b72b,
10290 0x1cdf25e0, 0x831dc7ba, 0x95982f4f, 0x681f8873, 0x6f943c27, 0xb22ffc87,
10291 0x7628f713, 0xaaf259a2, 0x34de49f2, 0xd9573933, 0xecb1ae89, 0x574a82c4,
10292 0x82c3a057, 0x82ba7ded, 0x43f82c90, 0x3b2c6a5e, 0x9d9faef1, 0xbfcfbe2b,
10293 0x4a9b6d23, 0x2ae5c4ed, 0x82d5313b, 0x6f7fa27c, 0x7693b983, 0xffdba142,
10294 0x2ef37d63, 0xf21889d8, 0x4fe38bbd, 0x82d313b1, 0xa6276805, 0xdf35154d,
10295 0xf3336c5f, 0x76877178, 0x16f52722, 0x6b6e4bac, 0x9779fe0c, 0xf3efc3fb,
10296 0x07183c3c, 0x5cb7c5ec, 0x46edebff, 0x371d7a47, 0xa13b2335, 0x7845ffd7,
10297 0x02faf456, 0x339b2fea, 0x4121f162, 0x0b705e7e, 0xf002ebd5, 0x0bebd323,
10298 0x3171e76e, 0x82f59e9d, 0xd6a11d9e, 0x32fdecb3, 0xe50bb31f, 0x99bf190d,
10299 0xad6fdb41, 0xb471dc96, 0xbd51adff, 0xbbd6a59b, 0x77a476df, 0xfdde988b,
10300 0xfd1c383c, 0xf7d68ea7, 0x54b7d731, 0xc775f59f, 0x33e98fe0, 0x77ef9aac,
10301 0x737d0c8e, 0x979026d0, 0xd73c4477, 0x80fdc63b, 0x1cdf437d, 0xe9eaf101,
10302 0xbbe44671, 0xad9e9cbe, 0x813c527e, 0x36772fe2, 0xd74ba7f3, 0xb2bf888b,
10303 0x65ff267a, 0x45c042b5, 0x7d8713eb, 0xfcfa8263, 0x8e7ceced, 0x473f20ae,
10304 0xeff9ff45, 0x3c415734, 0x012afe78, 0x1f2117cf, 0x9739f01a, 0x3dd0b3e3,
10305 0xfa2bf71f, 0xf1e5833c, 0x72e4d58e, 0xd3f18784, 0xdf3fde52, 0x72f8c61c,
10306 0xf704effe, 0x1f3ed22a, 0xd5efb4a1, 0x319f60a7, 0xdcf756bf, 0x11cf1cbd,
10307 0x718b5fa8, 0x6d3ad2d4, 0x4ff71e7b, 0x41a188e6, 0xf57f609b, 0xcb1dd127,
10308 0x22fd29de, 0x27fa29f8, 0xe29fb3f1, 0x874fc467, 0x9dc1799f, 0xa1fe5f18,
10309 0xe3e3d178, 0xbf5c7167, 0x4023230c, 0x3c198f1e, 0xb7e45fa8, 0x9923cc44,
10310 0xcd3f68fd, 0x7137043d, 0xe0c779be, 0x5f3c82ab, 0x9be58cb9, 0xb0d9adcc,
10311 0x67d6953b, 0x10a191d4, 0x52bb9e96, 0xf6238f6b, 0xfcc5debf, 0x020d8a82,
10312 0xe1ce15e4, 0x051509df, 0x1b7bc51e, 0xed485f6e, 0x6b3fed3d, 0xe707d998,
10313 0x612dfba3, 0xff0a9fd4, 0xf263892e, 0xe3cf88b4, 0x04f0f748, 0x820d53b4,
10314 0x6432e513, 0xd28b7661, 0x6893ee09, 0x44d5f31c, 0x8f16174e, 0x2c746068,
10315 0xb90374a7, 0xf5e4189e, 0xde0fe63a, 0xcec33c16, 0x253b82b5, 0x40852f76,
10316 0xb9df5192, 0xd8acff71, 0xcb673847, 0x77d15549, 0xffc621fb, 0x3e37056b,
10317 0xfeffd008, 0x4076fa19, 0xe99fc557, 0x3c157d2c, 0x79d1d12d, 0x7f29a5bf,
10318 0x08d79e38, 0x23a7bc6e, 0x0be78898, 0xbdd9ab47, 0xfe718f13, 0xec05cbd7,
10319 0x60f7d43f, 0x87130f5c, 0x1649d37c, 0x71c3ebcc, 0xa67f9933, 0xd6508efd,
10320 0xd0fd01e4, 0xd272953c, 0x34597e84, 0x34e7ccbf, 0x249fdd83, 0x5f79b518,
10321 0x9ffb9461, 0xdfdbfe00, 0xc5a49f07, 0xdbb97da1, 0xf6369ec9, 0xf4191132,
10322 0xf90932fb, 0xeb8366e8, 0x2fd06cbd, 0xe404490f, 0x237df3e3, 0x05d19fdf,
10323 0x8fe445da, 0x97867782, 0x80a48841, 0x829126e5, 0x3a5d98fb, 0x2bffc7c2,
10324 0x019ed7b5, 0x83f0487c, 0xf80189fd, 0x7baa6cae, 0xe20b9e67, 0x2ff62326,
10325 0x1bb1f385, 0xbdef9d73, 0xce5c7407, 0xbc395bee, 0x69f7172c, 0xa025df77,
10326 0xf4a41d9c, 0x4d373802, 0x3def78cd, 0x97dbbf3a, 0xd739e0a5, 0x34ca4f0c,
10327 0xb19af738, 0x68bb744f, 0xd9d759bf, 0x364e706d, 0x7c48a065, 0x4edcbc2a,
10328 0x334e309a, 0x9baee2a3, 0xa88a4e40, 0x547b843d, 0xf3fb828a, 0x46bd42ba,
10329 0x65cbf7c0, 0x9d2ba99f, 0x33cad35f, 0xfc7411a6, 0xd00fda42, 0xfac35e5d,
10330 0xdc11af95, 0x185baa90, 0x64f5147c, 0x2f011ae1, 0xfea268aa, 0x1b831c6f,
10331 0x9b70a388, 0xb4fbe86a, 0x07de173e, 0xa7126bb8, 0x395679c1, 0x3fbe279d,
10332 0x25cf12ba, 0xb47be90b, 0xb9ad3499, 0xabcde10b, 0x6f7c0811, 0xe33a3454,
10333 0x6f00d191, 0xf686e49f, 0x16fe77f7, 0xd2664af3, 0xf851baf1, 0x3ce6c4b3,
10334 0x2fddab8c, 0x93bef138, 0xee517dd9, 0x91dcb8da, 0xb9d87d81, 0xef9440b4,
10335 0xfcea8c7e, 0x96164184, 0xb0b85d07, 0xd5d60ab2, 0x1864a72c, 0x98ce9f90,
10336 0xa51f8ec0, 0xff51f6f8, 0xe58988f5, 0x47ca343d, 0xfd2acd4c, 0x07d2d939,
10337 0x437671e5, 0x3999ea0e, 0xe7e78bc4, 0x8fe64abe, 0x096a5a1c, 0x4987e008,
10338 0xde7874ce, 0xcf8cd4b8, 0x76625f5b, 0x3357b5a7, 0xd44f43c6, 0x87be0448,
10339 0xe7d35c5a, 0x89e3a029, 0x139e12f5, 0xa848cf8b, 0xc4bee6cf, 0x358d64e2,
10340 0x5a89ee0c, 0x9f72dfa6, 0xe82269b9, 0x956bb9ed, 0x1ead6573, 0xa315742b,
10341 0xc2c67a9e, 0x5f5e92f4, 0x5154f5e9, 0x76d8aaf5, 0xb1899ee8, 0x2acf50ed,
10342 0xc0ecaf16, 0x9b13973e, 0x4186a7a2, 0x6941495e, 0x812b99af, 0x89676f9f,
10343 0x2da14dde, 0x76093e5f, 0xf78ec4b7, 0x9d199503, 0x3f8c094f, 0x19ffe808,
10344 0x825f0dc1, 0xb0cd143c, 0xc73ffde0, 0x47201e81, 0xdcf1922b, 0x805030b3,
10345 0x2ef25778, 0xf2d4aee7, 0x7dce72bb, 0x1e244f8b, 0xb22afdb5, 0xdfaa8f12,
10346 0xf945fffb, 0x47738e96, 0x08b01083, 0xe7b43f50, 0xeeb023e7, 0xe42d79c4,
10347 0x3b0ac1fe, 0xf7fbf5f2, 0x7c0a599d, 0x8101f33b, 0x644edf80, 0xc3d8155f,
10348 0x0b8295b2, 0x1f73b3e2, 0xa5cfef60, 0xdfbcc3ef, 0x2fe32dff, 0x902ee7ca,
10349 0x479ab283, 0x35ff60f7, 0xbfe00b82, 0xfd00aabf, 0x24592289, 0x10e6bed8,
10350 0xbda823ee, 0x46a3fcc2, 0x39054c59, 0x76625b28, 0xc2b779c2, 0x1e7f0a4f,
10351 0x9351dfe2, 0x1b90f738, 0x00e77be9, 0x14be0c48, 0x7b110ba7, 0x2e53fc0a,
10352 0xf43b7e33, 0x1106e492, 0xb27f38b9, 0xfe1567ef, 0x46ff8113, 0xb1aff944,
10353 0xfc04d726, 0xe0202278, 0xf02e7cb9, 0xefe7f02f, 0xb10cf895, 0x8ba8fda9,
10354 0x0f9ea7f1, 0xe51ff1db, 0x0af3d03b, 0xa8fc2a7f, 0x46c3c3e7, 0x7de60d32,
10355 0xae0b52f7, 0xcb6ab723, 0xce4c85b4, 0xb7273cf0, 0x9054beea, 0xcb2342eb,
10356 0x5af050fb, 0x4279646a, 0x44f5e6ed, 0x675ba9a5, 0x479ba7e6, 0x2a3d8b37,
10357 0x63cb220f, 0xde71d109, 0xe63cff5c, 0x775e9dd3, 0x6ff45ae8, 0x003e51b6,
10358 0x93b7affc, 0x0243ee10, 0xeb8a8fa8, 0x1be60f45, 0x3759431a, 0x4aeff6aa,
10359 0x57fcc4fe, 0xe2ef88ec, 0x3e40e68d, 0xf378bf7d, 0x8e782191, 0xdff988bd,
10360 0xfd013af2, 0x0f372263, 0x8a3def81, 0x438f2c8d, 0x613c17ef, 0x96f0fb61,
10361 0xe0e9d62d, 0xecb509b7, 0xbae2af5e, 0x2ab3259b, 0x45b0fbbe, 0xb9e1fa52,
10362 0x0ce94c8a, 0xfcc355df, 0x294af7d4, 0xbf2d1bf9, 0xdc57fc67, 0x573fa120,
10363 0x15a1bb5c, 0x0f8af3f2, 0x5bbf719a, 0xf3067b5e, 0x795f738f, 0xd63fdd89,
10364 0xb2f26a20, 0xd543e5da, 0x51ce788a, 0x798a5f56, 0xe78eb41c, 0x3c75651d,
10365 0xe607e8ff, 0x657fcceb, 0xa29966fb, 0xdfa6fe70, 0xb09ef039, 0xfc0eb5a6,
10366 0xfbf6a54e, 0xe5db13f3, 0xe72dd53f, 0x9cd74ff9, 0x631fa820, 0x0a7d3fe7,
10367 0x947b80ff, 0x27fcda2c, 0x1bf4cb52, 0xac56679d, 0x7e2213ef, 0x3e5f4bd7,
10368 0x2dbbf90b, 0x167b3f1b, 0x8ff25de6, 0xbc859fcf, 0x09d00a0c, 0xbaf94a7e,
10369 0x51df3177, 0x85a0ef79, 0xff7e83ef, 0x6d17cc3b, 0x06ecc0fd, 0x4fdbad68,
10370 0xd1ff83a4, 0x549be1ba, 0x67bd03c8, 0x77c61e7b, 0xb73579ee, 0x6f15892b,
10371 0x6ff025e3, 0xaaf913a0, 0xd635ba7a, 0xc8fe6237, 0xd0774a69, 0xb6bc9113,
10372 0x2f9652ba, 0x6cf9e2e8, 0x07e763eb, 0xab5fcbb7, 0x2bbaf1bf, 0x33d63f41,
10373 0x79a2e13f, 0x3d28076c, 0x1d04ef2f, 0xc57cf3d7, 0x37be6bba, 0xfc34ed8f,
10374 0x2bebd283, 0xf01f368b, 0xcf39facb, 0xf56d0d3d, 0xb1e61dc9, 0x3f813a85,
10375 0xd1b8ff25, 0x83c431e2, 0x117c6d1c, 0x7e8107f3, 0xd7d02ef9, 0xbc43a65f,
10376 0xc614a4f8, 0xbb7844b8, 0x2b7bbf19, 0xca3efede, 0xfbabeb53, 0xf097bf31,
10377 0x1256e03c, 0x4d7cb1f9, 0x5f2a031e, 0x6ff96763, 0x1f900e9c, 0x73e072e7,
10378 0xf8c7079e, 0xeb8fc95a, 0x6c6e2f28, 0xe38b267c, 0xd2e8bcf1, 0x3cf21f35,
10379 0x84dd28b3, 0x43af40d1, 0xa8779bdf, 0x7809c1e0, 0xfbcea518, 0x18879d8c,
10380 0xd1d4fbc9, 0x7a09e80d, 0x49d7923c, 0xbf213deb, 0x1fbc202f, 0x75b88f2b,
10381 0x6d17cb15, 0x93dfb495, 0xf2c4e946, 0xebc64740, 0xb9d036e4, 0xad8bcffc,
10382 0xa9e287e3, 0xc34bbc5f, 0x5abe0a37, 0xefd6c7ce, 0x7f85e3d3, 0xd9ab7bee,
10383 0x82fbfe82, 0xfbe1e39b, 0x2643fa82, 0xf18bdf82, 0xddf2957d, 0xb5b78f12,
10384 0x7f3113ac, 0x11aeaab0, 0x7f5ebbf5, 0x1473f194, 0xe38b7cfd, 0x6b2ade99,
10385 0x65a3f660, 0xa3603da3, 0xd8de5a70, 0xb65d7c82, 0xf20990fe, 0x6ed4f6b1,
10386 0x03bcb132, 0x3f604726, 0xb7f9aa02, 0x0873bcbc, 0x9f7e73ea, 0x859c7e91,
10387 0x60f29c7c, 0xd7ca71ec, 0x338cd19f, 0x3933ae5f, 0xef1f176d, 0x66e7a353,
10388 0x1369f780, 0xad3ea3f3, 0xfac52713, 0x78b6e6be, 0xababef89, 0x3b50fc99,
10389 0xd93af78a, 0xa24e3dd9, 0xb2fd1e23, 0x0fa3ec7b, 0xf780fdc2, 0x47984dd8,
10390 0xe792b8b1, 0x3b97fc5d, 0xd8bde80d, 0xf981357e, 0xaafc052e, 0xd392f7f6,
10391 0x939fc047, 0xd423bcd2, 0xfcca30e7, 0x240c5d4d, 0xb7bf3ea0, 0xfb0aea4f,
10392 0x7b946253, 0xcdae3cc2, 0x7608cafc, 0xe2cfc9b1, 0x91fce4fb, 0xc9bcf0be,
10393 0x4c9ddce8, 0x104d36e1, 0x6d9a10dc, 0x7e0cf7cf, 0xd1e0ce24, 0x39095fde,
10394 0xb3beb0f8, 0x89fa036e, 0x49c84376, 0xa5bb10bb, 0xb8370d29, 0xa632e22e,
10395 0xe63cea62, 0x8fe43faf, 0xe7df0beb, 0x5b750839, 0xa8db9fa1, 0x61216fb9,
10396 0xff7751b4, 0x97d03902, 0xe71b1fda, 0x675e2557, 0x70a6ff67, 0x875ef19b,
10397 0x12a441c4, 0xdd8577d8, 0xe3c4fe87, 0x5f7e0f0e, 0x21037f46, 0xc48921df,
10398 0xc1f7d5bb, 0xf73571d0, 0x3571d04c, 0xb68f44f5, 0x78c93c9e, 0x49bd9634,
10399 0x2898f3e6, 0x890f10da, 0x2fee0679, 0xa5fbf27b, 0x989de746, 0x6821dc42,
10400 0x7986c6bf, 0x64bc54e3, 0x366c3af5, 0xfce9bced, 0x61227a34, 0x606cb350,
10401 0x773cd4f3, 0xeb809712, 0xd39f68f7, 0x7fea6af9, 0xcdf6e789, 0xefa08c48,
10402 0x844d716c, 0x06acffe3, 0xde8c4bdf, 0x4cc254a4, 0x4e93cc26, 0x483fbe13,
10403 0xe3a0ebe0, 0x213bfa6b, 0xd7c6c07a, 0x9d3d21c2, 0x2f06efea, 0xc6b076e7,
10404 0xfa0a3dea, 0x0577ab26, 0xa766fa26, 0xc3a39e09, 0x0bb05b69, 0x85cca7ea,
10405 0xad08e4b9, 0xaf8cd50b, 0x2820aefa, 0x2cc37d37, 0x892c858f, 0x1cd53f47,
10406 0x30cb6447, 0xc88a1ef8, 0x251830d2, 0x5c9fcfc0, 0x94140c8b, 0x35e51971,
10407 0x3c305efa, 0x128730de, 0x289a0ea1, 0x9ef143fc, 0xaafc61cf, 0x86697deb,
10408 0x793cb0a1, 0x946caee9, 0x62204bda, 0xeff4a868, 0x4b257bde, 0x9f7b81f9,
10409 0x0ddfec88, 0xa95ab876, 0xdf0ec553, 0x47c7576b, 0xaa389eea, 0x5933abef,
10410 0xbfd8785d, 0x424f5974, 0x0af04b1e, 0x7107d056, 0x3cf14bce, 0xeb84942c,
10411 0x517d98bf, 0x4d7039e6, 0x11f8c4f3, 0xf70a9e2c, 0x47b3f68a, 0x7b46c7be,
10412 0xd4a6d6bc, 0xf0bfb843, 0xbd47efd6, 0x1fb75a56, 0xa7500ddb, 0xe6e4ef65,
10413 0x29123d89, 0x79d5ac56, 0x5f809769, 0xa066905b, 0x5ac4bceb, 0xc1a8dbbd,
10414 0x3c1a13c3, 0xa63d1718, 0x3f63c3c3, 0x3c970f08, 0xa1e218fc, 0x7ca6ebb3,
10415 0xe94ad031, 0x80c72537, 0x3a8d37f7, 0x0bf8c368, 0x1ed059fd, 0x3aab3871,
10416 0xd9568ef8, 0x6e3850a7, 0x97f0a380, 0x57c29ef2, 0x1f4df11d, 0xdd94bce2,
10417 0x9fe5a7eb, 0x0c67ab02, 0xf56b1bc0, 0xe0a5b31c, 0xeebbf1fa, 0xef02be29,
10418 0x5f28e484, 0x386f9b13, 0x635c277c, 0x55bc73bd, 0x929daf15, 0xa4cc40b3,
10419 0x5905cdf3, 0x4f5d1918, 0xd2d942ca, 0xc533ae9f, 0xec3cc063, 0x126fab1a,
10420 0x1e98e38c, 0x48f5510e, 0x70df005d, 0xa38e8c41, 0x76d547c8, 0x2aaf8fb6,
10421 0xb1160430, 0xe00160f3, 0x59a3f945, 0xc6611fc7, 0x90870d1f, 0x8782ca3f,
10422 0x54347f18, 0xe7e78f8e, 0xae8fb06a, 0x40a1e126, 0x57d699f7, 0x28bd8cf2,
10423 0x55c358df, 0x485f283d, 0xfcbcfaf2, 0x33af104b, 0xcf87d262, 0x4757594b,
10424 0x9bdeadf4, 0xd820f0f9, 0xe033ee67, 0x37829879, 0x2b62dfa5, 0x661cb3cb,
10425 0xfc03cdf7, 0xde6e8f95, 0xb8dbe403, 0xd798cff7, 0xc377d8e1, 0x31df784e,
10426 0x15c85295, 0xdf7ab71d, 0xb7bfbc22, 0x4003ae9a, 0x0cb09026, 0x7c63bd76,
10427 0xe089f930, 0x419efc03, 0x28438f80, 0x77f8eb2f, 0xf0ee5445, 0x56deda3b,
10428 0x03c3bf76, 0x52079656, 0xc979156d, 0x7d94b0fc, 0xffb04d67, 0xc0625f2a,
10429 0x0e5029fe, 0x097faf52, 0x1ab6abf6, 0x0a74f935, 0xa27e155d, 0xf70ad49a,
10430 0xe8955c44, 0x9fe5ae5b, 0x0aa66b24, 0x23def29e, 0x4d9de27e, 0xaed46519,
10431 0xbb06ef3b, 0xd0a7f94a, 0x53d3b2aa, 0xc0164b06, 0x287f845b, 0x0fa2c67f,
10432 0x3037ef7d, 0xfe038c1e, 0x0b5d86c2, 0xe8773844, 0xe0b35d2c, 0x3fda3a1e,
10433 0x362a4acb, 0x12b3f7d2, 0x64f50968, 0xebcaef5e, 0xe7d9583d, 0xa041b723,
10434 0xb8f157cf, 0x9e562bec, 0x5e746037, 0xbc5cf70a, 0x9d9af1c2, 0xa0bb4566,
10435 0xa291adc8, 0x8db5ce0f, 0x333b7cfc, 0xba00699c, 0x0c6c7229, 0x6a76421b,
10436 0x2e8d32b4, 0xbc39e403, 0xe179f7e5, 0xbd23b0bc, 0xec25f573, 0xf3fd3fbb,
10437 0x1f9f3e46, 0xdd7f5fed, 0x46e0fbee, 0x5c696fc0, 0xd03723f3, 0x9f25d97a,
10438 0x91769c63, 0xf50aecb5, 0xd4be9e79, 0xf3adffcf, 0x1fe01c27, 0x9e6d7eb6,
10439 0xfecfcb14, 0xdffccaca, 0xf8e9febd, 0x2177e29e, 0xab2740a9, 0x63342fbf,
10440 0x55d57e89, 0x8e80f2a8, 0xec0931b2, 0x99c595ab, 0x2bbee9c6, 0xaec7ce54,
10441 0x5fb8b10a, 0xe833e816, 0xdd8335df, 0xf335fe57, 0x7fe8e28f, 0xc794ee70,
10442 0x32dec9cf, 0x69db16fa, 0x3b08b7bf, 0xa84acd6f, 0x93ef8468, 0xcf033988,
10443 0xf688732b, 0xe4acafbe, 0x8f3809ea, 0x479c0c84, 0xbdae9c6e, 0x40346cab,
10444 0xcc0c9f7b, 0x2a23cc57, 0x23ce8cbf, 0x78c10fab, 0x29701916, 0x194d85e6,
10445 0xb79ff948, 0xeccc0e7f, 0x426711b7, 0x764fef54, 0xa09de2dd, 0xddaa5bf1,
10446 0xfedfc7a0, 0x5623bc4e, 0x3675c5fe, 0xfd7b9fc6, 0x03e42f5e, 0xde3cf1e8,
10447 0xbbb12c25, 0x8f5be3da, 0x15fe3d4f, 0x98f1eabc, 0x427b91f3, 0xe93c0c52,
10448 0xbf3d12f1, 0xba00ac0c, 0xd1140de4, 0xd074297e, 0xcbf689e3, 0x5f6f7e87,
10449 0xf9c1fb42, 0x08c2b8ab, 0x43372f76, 0x457fdc20, 0xc22f36ff, 0x257fcc1f,
10450 0x3748ed5d, 0xe3db5e3d, 0x979f93d1, 0x1edf5d1a, 0x37e617c0, 0x3e400fb9,
10451 0xc24da359, 0x1c684971, 0xbc7be751, 0x04e4f102, 0xbbef1e1c, 0xaa40c71b,
10452 0x5762aef8, 0xff2888e2, 0xeb5afb8c, 0x2705e6e7, 0x39ff029e, 0x04b7c12b,
10453 0xcc44a6e2, 0x8a3a3cc0, 0x3e5ac3bf, 0xcd6bfce3, 0xf8a13e40, 0x0c43b6d4,
10454 0x664fde07, 0x5d4e79ed, 0xf4cf8ebb, 0xecf857eb, 0xa6307815, 0x3e14be3d,
10455 0x7ee3689b, 0x13d27779, 0x5b21e4fc, 0xde802446, 0x98a4c126, 0x075188f1,
10456 0x9c3811bd, 0x051f915f, 0x773c8be2, 0xf427f9f6, 0x8eb51357, 0x1cc0f8aa,
10457 0x2d9b77d1, 0xf852fe86, 0xb74e4ae3, 0x13bc892b, 0x12574be2, 0x7d9117e3,
10458 0xfd744640, 0xde3c6cb3, 0x80f483d2, 0xbab2ee75, 0xaf997ed8, 0xea6eb233,
10459 0xb3dd0256, 0x71d9f8f9, 0x834efc36, 0x112d8d84, 0xbde267fc, 0x2929b235,
10460 0xf7890f3a, 0x8415e927, 0xf03371f9, 0x178a5cbe, 0x9d1ac172, 0x609b42c7,
10461 0xf85c7bc4, 0xc6d74e3c, 0xb6df90c9, 0x003df44e, 0xf6116ceb, 0x19f5c10d,
10462 0xeec1fd43, 0x6f3fdbe9, 0xed0655d8, 0xf6215fb4, 0x2f9ff3e3, 0x7843b8b2,
10463 0x3ab039bb, 0x94ff63a3, 0x07da358a, 0xe1b22e45, 0x41cbc8bb, 0xcc22c2ce,
10464 0x53cfc83b, 0xc2299c76, 0x3887a0fd, 0xe1465c97, 0x113b3eed, 0xa973f9f3,
10465 0x7a7e81ba, 0xb7f3d7be, 0x90279f9e, 0x4f784cf0, 0x363fc7cf, 0xdff1400f,
10466 0x90737c22, 0xeeca8df2, 0xf942fc29, 0x5d1b79e7, 0x6388db77, 0xfdbb814f,
10467 0x53cf88ce, 0xfe29eec1, 0xf10fd479, 0x3afd00bc, 0xff15d3f2, 0xf7cd937c,
10468 0xc233f412, 0x99fbe87a, 0xf8065d03, 0xcd90fe7e, 0x573c32f3, 0xed8b96fc,
10469 0x232ec837, 0x3be74819, 0xcea1d393, 0x593ef040, 0xf6808179, 0x961276ec,
10470 0x2bdbbc60, 0x76becd24, 0xc9fc25a6, 0x587e70fd, 0x99ed0039, 0x14fabe0f,
10471 0x8f967df1, 0x13bfc55c, 0x0fee1819, 0x163bbefb, 0x43c7df6a, 0xbde8acc2,
10472 0xbed09f9d, 0x6e0092dd, 0x877c0a73, 0xfb6b205b, 0xd657c7eb, 0x7fab87a1,
10473 0x63df9caf, 0xbb22f704, 0x9fc2fe55, 0x8d8fcc6c, 0x7e2df7cc, 0x37c5018f,
10474 0xc1b3d5d8, 0xc50f024b, 0xf4a55fe0, 0x8c7b25c5, 0xe6f5a3c3, 0xb1e9e6ed,
10475 0xc65117ee, 0x833df051, 0xfcf82934, 0x65ff1636, 0xc01c58fb, 0x734844f0,
10476 0x7d94af4e, 0xdfd013c3, 0xa0275beb, 0x97525d7f, 0xf1a59863, 0xb83ed9f3,
10477 0xf70f9f9d, 0xfaff405d, 0xafcfcc9d, 0x42fdc4ab, 0xf7db3d49, 0x5cef82ac,
10478 0x0c89f3ba, 0xb23fff42, 0xa9bc859f, 0x9047b852, 0x53e087b5, 0xacd53ef5,
10479 0x897db27f, 0xf611b969, 0xc934bea3, 0x5abfeb4d, 0xf747155e, 0xc419554d,
10480 0x29bee842, 0x27cb57f1, 0xb54d18ae, 0x20479273, 0xb2af5889, 0xfefce98d,
10481 0xcb57f939, 0xe36596aa, 0xaede2bbe, 0x2476cfda, 0x2e6de71f, 0xfb4763c4,
10482 0xbc12c7d8, 0x3c5576c9, 0xb3ff4f42, 0xe004ae71, 0x7f7ce5bf, 0x59c2f57d,
10483 0x0cb06fb8, 0xf90e9f38, 0xee9cd961, 0xb38f3b2e, 0xdcf7d95a, 0x00f4d6e5,
10484 0x456ba9e8, 0xd9e60b9f, 0xfef9c6f6, 0x6b7e4710, 0xb7dc11e0, 0x8ebdf905,
10485 0x5e45fcfb, 0x65fabe75, 0x5f67e676, 0x03a3497d, 0x8cd71df6, 0x677e0bfc,
10486 0xeec8da7e, 0x6d196b4d, 0x4fb9f8d2, 0x032ef2da, 0xd1494af8, 0xce7e8227,
10487 0x20ebb11e, 0xec8efbd8, 0x780ed444, 0xe403b004, 0x3c54fefc, 0xeddfaa07,
10488 0x0b65d880, 0x74fd6eff, 0x9dea637d, 0xf0dd2cb4, 0xb7ec0717, 0xcfccedb2,
10489 0xc26c6d3b, 0x5e4a747b, 0x079ef115, 0x6dea6e3a, 0x9fae5f10, 0x1b10f595,
10490 0x076d4e26, 0x43afbf09, 0x8caf07f1, 0x2edc0393, 0xbc4d712a, 0xbd5c63df,
10491 0xda38b1e8, 0xf7a785fb, 0x0f9e3e66, 0x1b922174, 0xd92325dd, 0x3f227e85,
10492 0x5dbfa1e7, 0x0ef0af70, 0xfebd795e, 0x40af1bf3, 0x4276a266, 0xd7c93f00,
10493 0x98ef0585, 0xb7fc563e, 0xe36b5f71, 0x527f7a97, 0x83e33bb1, 0x20f49743,
10494 0x8dd71780, 0x5ec21df8, 0xe94de623, 0xf0bccdfd, 0xcafc0ec4, 0x363f9147,
10495 0x02b1f7d6, 0x19d9873d, 0x7fd7965f, 0x94aef78e, 0xb834d091, 0x5eaca6ff,
10496 0xf7c88674, 0x6f25e9e9, 0x6ac1dfc3, 0xe02e4a0b, 0xeee0b6df, 0x6f5021b8,
10497 0x561e3110, 0x65f64efe, 0x41ad67c0, 0x291fef09, 0x01cc7edf, 0xf3b140fa,
10498 0x2f7641ad, 0x08f05b49, 0xb6e0573e, 0x065f2436, 0x818367f6, 0xed773fed,
10499 0xfa0ad6f9, 0x67f3f5e1, 0xabdf7193, 0xff9d69d8, 0x7377c4ab, 0xbe2462ed,
10500 0x896ff6ab, 0xf2007d98, 0x2412f2a7, 0x7f510a22, 0xfe9d9db5, 0x93b12c88,
10501 0x823af6f6, 0x8231e27f, 0x77edeb9c, 0xfb3adf04, 0xfb9d88fd, 0x30c8bd8f,
10502 0xe1afc7b8, 0xfc7cf27c, 0x756833ee, 0x0cf8c22e, 0x76da4ff3, 0x14d8fa7d,
10503 0x644fbe78, 0x179ffddf, 0xd8dfef91, 0xb377bf31, 0x2af78d4d, 0x6eb9d7a4,
10504 0xd1b75a67, 0xc776e7fe, 0xd1b578b3, 0xbbfa997d, 0x00ff6883, 0x3ba857c7,
10505 0xbb92f73b, 0x3f3b7dc3, 0xb70cffda, 0x45eaffbb, 0xb8d2f790, 0xc35044f0,
10506 0x990e6bfd, 0xb30c5f40, 0x7a625f7b, 0x7a0acea0, 0x7be32640, 0x516e3a10,
10507 0xfc0f193c, 0x4e24ae15, 0x757bc3c8, 0x7400c1af, 0x0336b119, 0xf1d664f3,
10508 0x7579c173, 0x950ca6d5, 0xcfc7997e, 0x724a4e95, 0xf9ea927a, 0x03d30770,
10509 0x3f177727, 0x03f2fa87, 0xc317e933, 0x983b263e, 0x9264dbbd, 0x7e87aca7,
10510 0xefb80d87, 0xeb67b5d8, 0x6e0fb81e, 0x50d741de, 0x41a737b0, 0x86bc281e,
10511 0x20aaeb7d, 0x23e1b6cf, 0xbf5416b0, 0x0d1029af, 0xc46ddc74, 0x0764e2c5,
10512 0x8dffb80c, 0x278917c4, 0x29f9d619, 0xf6dbbfd7, 0x50e7341a, 0xa43df8db,
10513 0x39d9da1f, 0x8b3b7ed4, 0x3bdc6d53, 0x944ef93e, 0xd001df43, 0x9b47e5ff,
10514 0x68ae1cab, 0x97f14d5c, 0x38d81cc6, 0xe7fd3065, 0x13831698, 0xb03aedc8,
10515 0xbaf5845a, 0x25db524e, 0x13fe7690, 0x1a89f785, 0x0616b6de, 0x0de3ce8f,
10516 0xff055390, 0x3c3f02d4, 0x35b7d688, 0xbf209319, 0xb2bfc14a, 0x577c650e,
10517 0xb2acf11d, 0x367928a1, 0x577c4f7e, 0xb87cf7b9, 0xa0f72893, 0xb6ce5f23,
10518 0x3f195a7b, 0x3f50e9c8, 0xfd1e3bb9, 0x9edc4d92, 0xde82b491, 0x4e853f80,
10519 0x7f660e09, 0x3474f994, 0xbfa73c7e, 0xbe50fe52, 0x64b9275e, 0x1f7e1be4,
10520 0xc50e4ba0, 0xae3c81f5, 0x77f83e86, 0xae79545a, 0x47c00ef1, 0xd47e368b,
10521 0xc0306cd0, 0xdb6558f7, 0x66bc4485, 0x6dfe93a4, 0x758ccf84, 0x070d7fc8,
10522 0x7171ca09, 0xbe2c5ded, 0xf83d4247, 0x5e7858bd, 0xcfc3f20d, 0xb409bbad,
10523 0xb55c131c, 0x37e207b8, 0x8ab900e4, 0x0dca89e2, 0x26d51594, 0xf779d7e0,
10524 0x3f2e72b0, 0xd2b79dff, 0x5859f287, 0xfafbf2c3, 0x7cd8323a, 0x4312bf38,
10525 0xfbc8777c, 0x7fdb8e78, 0x022fde65, 0xa9fad2df, 0x611bc7fa, 0x975fca5c,
10526 0xdeee203a, 0x3053e8f0, 0x4f5f855d, 0x4e1091ad, 0x7cf6bc51, 0xd74e72fc,
10527 0x7e300f57, 0x1a46b31f, 0x8d31f70f, 0xe2138991, 0xacd6dbc5, 0x6f7f4115,
10528 0x60ce7e03, 0xfd760e72, 0xac87eee4, 0x773b04bf, 0x2e2040c8, 0x8a44c9bd,
10529 0x62e4a836, 0x34d7aad7, 0x5b5c5bf2, 0xdfe30539, 0xe80249cd, 0x156e4579,
10530 0xb9326fbc, 0x5ffca327, 0x09ff93ab, 0x0e39fdec, 0xb9c79746, 0x893e3ffc,
10531 0x947d3fca, 0x005126b8, 0xb14c9b38, 0xf69ae9ef, 0xa22ff923, 0xd3b68f57,
10532 0x6c1cd3ab, 0x43e8ef5f, 0xe6bb2fc7, 0x23ebee2c, 0xf37ce3f3, 0x6f8504f8,
10533 0x7fc00432, 0x5f60a535, 0x2bc517c0, 0xaffa33f0, 0x32736fa0, 0xf6a1bef1,
10534 0x3948b8fc, 0x6dc8d397, 0xf229af54, 0x7a022beb, 0x58a84d67, 0x72767e0c,
10535 0x7a7c8cbe, 0x4ef5f04a, 0x14ed76a2, 0xbd0c73c8, 0xf4c1d130, 0xa7c939c8,
10536 0xfdbcafb9, 0xe077483c, 0x63ba22eb, 0x1a917583, 0x51f409c1, 0x6c355dda,
10537 0xc394b15f, 0xf52b9e53, 0x2ff78d1f, 0x9783c5da, 0x333d983a, 0x7fb056c1,
10538 0x2233d980, 0x20b9478c, 0x83bbab86, 0x76a3cdbc, 0x1d9556ec, 0x2355253b,
10539 0xf8782abf, 0x73f7e735, 0x57dd6c89, 0x829679f1, 0x673aa7ef, 0xa3041ba2,
10540 0x145ae4c0, 0x008bbc98, 0xb1eed4ff, 0xafef9193, 0xf3f7cd89, 0xfe42afd7,
10541 0xc4e49c4c, 0x371e48ef, 0x83892dba, 0x00e3e962, 0xfed6bb96, 0xc059f706,
10542 0x1df720c7, 0xc81141c9, 0xffc18901, 0x2affca01, 0x407c29fa, 0x8745e2f9,
10543 0xf9e84f4a, 0x53df3942, 0x7749b2f0, 0xeb8e783e, 0xba5e46f9, 0x5153c83a,
10544 0xe9a3f3d6, 0xce8ed2dc, 0x473a306f, 0xade80be5, 0x81df89e8, 0x2c74a59c,
10545 0x9c12fd67, 0x8faa9f38, 0x485e6167, 0xaa273f35, 0xf329e3e3, 0x42f5c03e,
10546 0x353ce747, 0x1c5fdf56, 0xd748f3ba, 0xe47f28a0, 0xc176bf71, 0xb39e335a,
10547 0x9e4c206f, 0x01f15de5, 0x4e9e77f5, 0x294c7523, 0x3e808faa, 0x3856891f,
10548 0x42d77504, 0xc74be913, 0xb051973d, 0x7e6df20b, 0x0fe724d6, 0x60d8eba6,
10549 0x835ea792, 0x64f701fb, 0xdf393f80, 0x6f7884e0, 0x4029c7a2, 0x0343023c,
10550 0xd8fb8720, 0xb8fbc338, 0xab7dc32f, 0xf41c3dcb, 0x2f4e69c1, 0x1e0abe85,
10551 0x1d77b23a, 0x025fb5d1, 0xede3a73f, 0x26f23d7a, 0x38e79b97, 0x47ae2f1e,
10552 0xc9e41164, 0x448b7c41, 0xd3367f98, 0x923d1183, 0xd01cf04d, 0x9e55c7c1,
10553 0x509ff52b, 0x5212388f, 0x74647a54, 0x423d4c73, 0x3fe5317f, 0xf41ccd65,
10554 0xd8c1c967, 0x027a6cfe, 0x6029c7b3, 0x14bf6947, 0xd33dfd99, 0x503edcd3,
10555 0xc57cc48e, 0x8c6635ea, 0xc87a2be3, 0x878c9531, 0x00eacfbf, 0xa6bd0bbb,
10556 0x095e0efa, 0x2669b3e7, 0x9f179c17, 0xf748c292, 0x5cc37453, 0x15e1fc8d,
10557 0xf431de80, 0x85f88111, 0x2c9ed7fc, 0x51062efe, 0x11e4164e, 0xd6bba3b4,
10558 0x2abe428e, 0x8014cfca, 0x136b8b6f, 0x9a4f6805, 0xbe8034e0, 0x6a31d652,
10559 0x49fc88a1, 0x824460e5, 0xe4a31e8a, 0xd5f0110a, 0x2697d93b, 0xd6fdd225,
10560 0x4cfd57af, 0xd0f1bf1d, 0x68b48afa, 0x1fd686fc, 0x7ceb75b4, 0x213726fc,
10561 0x3fe420f0, 0xe4f0eadc, 0x5635b8c0, 0x59942e6f, 0xce302b5d, 0x88bcd9db,
10562 0xe52fcb1f, 0x0e444e3c, 0xcecb8bb4, 0x5c6175ac, 0xa7cc1a76, 0xa7f1fbac,
10563 0x73de1c00, 0x66efd311, 0xf5c2e8f3, 0x2088f902, 0x2b78ba3d, 0x28978844,
10564 0x384ee77a, 0xf6a14594, 0xa1ae7008, 0x2de81bc8, 0x3c95a7f0, 0xd95b8808,
10565 0x401f6e31, 0xc27a823e, 0x5a3ea8b0, 0x79886f91, 0x04c2f15f, 0x9faa4fdb,
10566 0x9beff049, 0x477ca97f, 0x2d3ca228, 0xebe9504c, 0xa70ff3c7, 0x7608f3b2,
10567 0x7cdddfaf, 0xb916e78c, 0x4ba034ff, 0xa1867ef4, 0xf90c9366, 0x5c43c4a6,
10568 0xb1fe554e, 0x76421410, 0x56fd63c8, 0x874a1e20, 0x2c456fb6, 0xde3ffb9f,
10569 0xcfe01949, 0xd4dc1837, 0x0bfc8233, 0x6f770794, 0xd4a7df82, 0x73127bf1,
10570 0x091e6d1a, 0x1c421de2, 0xa3da8eff, 0x1d18e73d, 0xdb4f5f4e, 0xf8cd0717,
10571 0x72dafdb7, 0xe0afbf94, 0x1598efc6, 0xe7790efc, 0xd79881f1, 0x8376ac69,
10572 0x30b6ad9c, 0x2c2dabf8, 0xa2dab76e, 0x004ae7bc, 0x79d1ddbb, 0x1ec2f67b,
10573 0xe253ff18, 0x90e1d98d, 0x0cc9f808, 0xc92c0cbb, 0x0c678d8d, 0x72b75c13,
10574 0xf1c75f0e, 0x46ef69bf, 0xd679ec11, 0xb0c5ea84, 0xf763d9ef, 0x6bfa00bd,
10575 0xdfd6b66c, 0xf3f0211b, 0xf704c9e1, 0x249c8a4b, 0xe09d9337, 0x6c1e24da,
10576 0x1a0a80f6, 0x13b3d27b, 0x5e0995f6, 0x553c0022, 0x8006cffe, 0x8478ba4b,
10577 0xdfc0ba6b, 0xfb7fe5eb, 0xb4d9c390, 0x7200bc77, 0x8269a5df, 0x9ed41ae0,
10578 0xfec257cf, 0x53cb047b, 0xfb2afa01, 0x5e2fdec2, 0xa5f0013a, 0xfae26ff4,
10579 0x2f9f0afc, 0x74c64217, 0x7718213d, 0x2340f4cc, 0xaa35495c, 0xb9346e48,
10580 0x4799eb54, 0x668f5e10, 0xedd1d719, 0xca072fa0, 0x1c44b663, 0x10c9ec77,
10581 0xad74b7e6, 0x43f69020, 0x401d357a, 0x4557aa3f, 0xdcf40093, 0x9c0df7b4,
10582 0x5da6cf6f, 0xb5f2e4ac, 0xca05fb91, 0x98d98ebc, 0xcfc63cdd, 0x334eaba9,
10583 0xc12079bb, 0xca4bf987, 0x7c72aa3a, 0xfe141569, 0x19cbc84a, 0xce5e71d1,
10584 0xb2930491, 0xd608ffdf, 0x79bd3e57, 0x3ea0f00f, 0xefba907e, 0x7523d230,
10585 0xaf96db21, 0x0040b7dc, 0x4672b17d, 0xa281f8ec, 0xf8f25637, 0xe5ff2aab,
10586 0x4f4f5a94, 0x66b24829, 0xf292f4aa, 0xfcd153de, 0xff3c4d97, 0x7bcd03e5,
10587 0x805a9783, 0x79b2ee9f, 0xe573c0ce, 0xe3ad0bef, 0xd947b77f, 0xbaf82acf,
10588 0x80fcc9c2, 0x1fd70903, 0xc0247383, 0xf1f29393, 0x3cec4b3a, 0x069dcbf2,
10589 0x7e3077ee, 0x5f8c4d21, 0xff6a1d60, 0xb001bfeb, 0x00d7432f, 0x0000d743,
10590 0x00088b1f, 0x00000000, 0x7dedff00, 0xd554780b, 0x733ef0b5, 0xc9332666,
10591 0xe4cc9924, 0x40275e49, 0x21c40a30, 0xeb141021, 0xef0c0124, 0x02415041,
10592 0x8042120c, 0x2a941324, 0x8065bd6d, 0x8d520318, 0x8bd4b45e, 0xd7a5783a,
10593 0x2941b622, 0x84ec1a86, 0x3a0bc157, 0x94b62a28, 0xaa54141b, 0xa5ac4090,
10594 0xd7f97b96, 0x661f7b5a, 0x962264ce, 0xbfefbf62, 0x767e9fff, 0x67d9cfb3,
10595 0xfbd7b59f, 0x649ecfb1, 0x1258c4ab, 0xdd3b3763, 0xd8c67a65, 0xc1b758be,
10596 0x88d8c45a, 0x596edf62, 0xb9786c61, 0xda1eb777, 0x3bbf564c, 0x94061136,
10597 0x6826c733, 0x3dac1dec, 0xa384da0e, 0xb838ce1d, 0xa36adfdf, 0xacfa6e79,
10598 0x8c2db98b, 0xab98950d, 0x97631065, 0x60d6eff0, 0x31d56a9b, 0x0627f306,
10599 0xe306254a, 0x6cb8c436, 0xe961bef8, 0x4001b2f5, 0xf1d66449, 0x03631fac,
10600 0x2b8d0aad, 0x96ee762c, 0xa7563de1, 0x8b79c64b, 0x9ef4ac63, 0x6a771cc6,
10601 0x1d3e7f3d, 0x4e89679f, 0x37c02269, 0x5b18bfec, 0xfb6ddd03, 0x1065254b,
10602 0x6f1467be, 0xc0b67319, 0x056057f8, 0x115970a1, 0x9f7c249e, 0x39ebef44,
10603 0x4acf3bbf, 0x129ceaf0, 0xa8fc324c, 0xe860c7c5, 0x32f5a5f0, 0x02c89fc2,
10604 0x6d000312, 0x2312d6d5, 0xc6bd37bc, 0xfe61b921, 0xf95c629b, 0x0e635cf8,
10605 0x6d0a1c5c, 0x0ab7ce89, 0xe7103b9e, 0xf981653c, 0xf668bf17, 0xfa31349e,
10606 0xd5ff04bb, 0xfa6824b6, 0xef34d69e, 0x7f60bcc9, 0x0d23fe31, 0x4ccfdbfe,
10607 0x3563186c, 0x407b16fc, 0xef8cdf76, 0x3c7535a9, 0x75fa173a, 0xc8caf8bf,
10608 0xae0a4960, 0x6578e017, 0x3dcc417f, 0xa77ae096, 0x9977a4f5, 0xbd27a935,
10609 0xde824a87, 0x4ade8163, 0xb29f7a4f, 0x3b7a0824, 0xfac107db, 0xc24c5de2,
10610 0x135f01e7, 0x85dc3d39, 0xb788c1ae, 0x380332a5, 0x587a455e, 0x538f4cae,
10611 0xa71fce16, 0x2a1e9c2c, 0x38c6e61d, 0x75d2b4ef, 0x96f5ef46, 0xbebc3cb2,
10612 0xdcae8276, 0x16cf8117, 0xee342d59, 0x05fcf1aa, 0x99e287d3, 0xfb6dfdb5,
10613 0xc1efa10f, 0xf784cb7f, 0xc0378845, 0x583f5c7b, 0xf84ebff7, 0x53f91928,
10614 0x203aea67, 0xdb6a3e01, 0x25864564, 0x9c954c0c, 0x5b190b27, 0x89cda0f5,
10615 0x8b5cf07c, 0xf18288e4, 0x6b14c9cc, 0x22564332, 0x75fd9d62, 0x11bb3e7c,
10616 0x8360b85a, 0xa334de71, 0xcef2136f, 0x8c33c01e, 0x380824f3, 0x001fe01a,
10617 0x0555a747, 0x0df749cc, 0x559ff2ec, 0xf851fb82, 0x6a4b982f, 0x80976f69,
10618 0x998aab70, 0xef7000db, 0x1f89936e, 0xf68c6b9f, 0x2ffcc145, 0x607f396d,
10619 0x3ffbf426, 0xc165c3a8, 0x27eb04df, 0x53a8f831, 0x1cad04ba, 0xc3d3ca67,
10620 0xed1c877d, 0x4b7c6190, 0x8b3e5c74, 0x3764ac67, 0x955b3f31, 0x7bc0f30b,
10621 0xd347b556, 0x82e556fa, 0x1f10e47c, 0xd9f8863c, 0x69646b13, 0xe41bbd70,
10622 0x670dc706, 0xcc8cef1d, 0xbba9d209, 0xbbd9cbf5, 0x189efd60, 0x2627af3e,
10623 0xde00c7cb, 0x07175dce, 0x5b8f1f20, 0xca35cf36, 0xd924d8ce, 0xafe91ebd,
10624 0xde66f73e, 0x6f8871c7, 0x5e0832c6, 0x841c9fa2, 0xacde32ef, 0xac72bf1c,
10625 0xc9d1d69e, 0xeeb81da2, 0x2193a316, 0x39c7bc9d, 0xad78ab7f, 0xd9d1bc13,
10626 0x0dd47456, 0x68ee7beb, 0xef9f0386, 0xeb36ed6c, 0xe2cb7de0, 0x75c0bfdd,
10627 0x715d99c9, 0xcf8841ae, 0x063bebee, 0x097a1e91, 0xfc1f77af, 0x741ee6d8,
10628 0x86dbeb55, 0x7d695fcf, 0x49a5bd1e, 0x3fc9ef8a, 0xb5207ce1, 0xca55ffb5,
10629 0xa8613927, 0xcc59bcb7, 0xddd60ab7, 0x93487838, 0xc69e848c, 0xc64f9414,
10630 0x0c9fac2a, 0x2abbd20c, 0xf107b5de, 0x8cd7caac, 0x843ed778, 0x5e93df0b,
10631 0x8fdceb40, 0xf343fcfd, 0xabba0d0a, 0xc8e1e75a, 0xfe13f4eb, 0x6a7ac56b,
10632 0x0cbf164d, 0x866db3f0, 0xf9543a2f, 0x5e13dbec, 0x0e31c7a0, 0x1ba8e3af,
10633 0x8b7bf9e9, 0x43e21563, 0x62bab01f, 0xf8e3fe09, 0x373c563e, 0x21bbd715,
10634 0x858f69c6, 0x30579bf1, 0xb4520fce, 0xdc5879e3, 0x68b63dd6, 0xf15593d4,
10635 0xdf3853ee, 0xb3f3ba0d, 0x02c7685d, 0xdc3ddd2e, 0xd7867c0e, 0x7adddd61,
10636 0xc65ea382, 0xfd62aff9, 0x71f322e7, 0xd9fc3a0f, 0x54e7a21a, 0xf4148cfc,
10637 0x41f8891d, 0xffa5dc85, 0xc414c3a2, 0x3d4a048f, 0x3e73d6dd, 0x10b23ac6,
10638 0x9f1df6de, 0xf980e80e, 0x74f8deea, 0xdd6fca36, 0xb888a26f, 0x7d737ea3,
10639 0xd9f1f23c, 0xc5bd3612, 0x7e9f53d2, 0xa5debcb1, 0x1ffae607, 0xcbd25f6b,
10640 0x44602c35, 0xb2db5d3b, 0xd10fa5c4, 0xe93100a7, 0xc08683dd, 0x60ff9c04,
10641 0x0056cc91, 0x863b75df, 0x7a08b0a7, 0x5adf6d5a, 0xb9955cce, 0xf512fd8c,
10642 0x8ed7f21c, 0x9784f1a1, 0xe3e91b36, 0x9707f1f0, 0x1946bb57, 0xe0ef9f7a,
10643 0x1f74f310, 0xcc213f3c, 0x8131b90f, 0xa23195db, 0x44e94505, 0x8f6ccf38,
10644 0xd2e179f5, 0xe2f78299, 0xcce9e018, 0xbd0b77b6, 0x58672fc0, 0x51d7bee0,
10645 0x30b4be7e, 0x0c267bf4, 0x4570af79, 0x6ede506c, 0xbf6be629, 0x7143b5e5,
10646 0xb09f8c0a, 0x37a27775, 0x30b77f04, 0xf99797fd, 0xcbdf0737, 0x1df4c7d7,
10647 0xec1e9003, 0x0ac9d3f5, 0xec7613b4, 0xa07ce44d, 0x4bce90e8, 0x15fade85,
10648 0x9c111a5e, 0x3ab2c26f, 0x60c2a8d7, 0x9982f6bf, 0xfafb42f9, 0x5f4d1180,
10649 0x5d0b05ed, 0x26c427b7, 0xc3e8fe92, 0xf8fea0fa, 0xbf0b78b6, 0xe0ede2ae,
10650 0x6859d390, 0x239acfbf, 0x62edc9f3, 0x4463b75c, 0x1347fa0a, 0xd6fefe8c,
10651 0xf318e308, 0x75f0b8d1, 0xeddcb9bd, 0x3bdb951a, 0xcc8de37c, 0x1cafc91d,
10652 0x9afdc09f, 0x7999876e, 0xdbefae41, 0x743b2068, 0xd307e2e8, 0x9f7e810a,
10653 0x5758306e, 0x9fab3e02, 0xaff19dd9, 0x487abf70, 0xfe825594, 0x3fbf8aa7,
10654 0x6782f1f2, 0xfbae1764, 0x25f70dd3, 0x73f683cf, 0x801ac7e0, 0x0346c163,
10655 0xf8deaf5d, 0x5a7eba7d, 0x6782e9f0, 0x9ea20692, 0x4d67b43f, 0xfab3ae32,
10656 0x13be1fbf, 0xa356c5f5, 0x6810e075, 0xae48b66b, 0xb1722151, 0xa6b305e8,
10657 0xaac755bf, 0xbaea1d71, 0x7cbee499, 0xbc78015f, 0xba0fdc09, 0x8f65ff6a,
10658 0x7f017fd6, 0xfdc09bc5, 0x61534995, 0xdd4575dd, 0xdeee27e4, 0xfc764d17,
10659 0xfc9916b7, 0xbf90ff01, 0xd08de7fc, 0xbd6ffb2f, 0xc1087c83, 0x5e85a3e7,
10660 0xf48f2c66, 0xf7899550, 0xc9e876cb, 0x958b289f, 0xd07edf09, 0x08c8a313,
10661 0x61a32d39, 0xe7d4f7dc, 0x46eb91e4, 0xf1d1b8c0, 0xe27e8606, 0x268bfcf7,
10662 0xb7efd030, 0xd47fd05e, 0x529eb211, 0x23a3d4e6, 0x9a0cc252, 0xe3a3abeb,
10663 0x08ff479e, 0x1ea3d326, 0xef69332f, 0xee3fee8f, 0xd1bbda34, 0x5575ed56,
10664 0x39439e7e, 0x83941818, 0xf4fefbdd, 0x675878c4, 0xfb9941d5, 0x33d05763,
10665 0x72bae16f, 0x566fde91, 0x0ee7816c, 0xba1cec09, 0x1a4369f8, 0xc4b157f2,
10666 0xd3ff4256, 0x91e5518b, 0xd54622e4, 0x9ce80c37, 0x44f3a417, 0x7dcbc2c7,
10667 0xc5c98b14, 0x11f72e4b, 0xefaf6ffe, 0xef2e59be, 0xfbd2304e, 0xb861f5c3,
10668 0xfa577cfc, 0xbd90c270, 0x6a58de59, 0x17ed8e7f, 0x099eb95b, 0xfae18fd7,
10669 0x1c2b854f, 0xb20bdade, 0x4f8def46, 0x505c6850, 0xfee919ff, 0x3eb38c35,
10670 0x6710884b, 0x7c267d81, 0x29e98779, 0xe1ff03be, 0x641b8e0c, 0x0025ec51,
10671 0x6fb58352, 0x25f5ea0c, 0x5e177716, 0x86e97ecf, 0x0c17e851, 0x43acd2dc,
10672 0x7129d1fd, 0x88366d7a, 0x8283fb16, 0x045fd071, 0xfa131cdf, 0x53a0e200,
10673 0x2efb6816, 0xc31f632b, 0xcc4ca2fa, 0xbb202e6b, 0x041435ef, 0x7e023fe7,
10674 0x8d99c60c, 0x9fc78c25, 0xebffdc09, 0xace8a79b, 0xcbc3ff30, 0xc093cead,
10675 0xa797abcf, 0xf2f2cb52, 0xfbbf4874, 0x6fd06e04, 0xbbbce7c4, 0xa75d69a2,
10676 0xca3e5724, 0xbe02c3e5, 0x62dc7a70, 0x35dbf953, 0x9a2fd420, 0x5f591a5f,
10677 0xd3d36f5f, 0x66a792f8, 0x71dfa164, 0x2ceefdaa, 0x00a7a3d4, 0x41da00de,
10678 0x9bfe23bd, 0x84c785fc, 0xec223e3c, 0x2788bc45, 0x04e4227f, 0xd5b9c7d8,
10679 0xd174eb82, 0xa7cbd5fd, 0xf2f8fb53, 0xc63f7465, 0x12fc4396, 0x4095e237,
10680 0xc9dfa05f, 0x83d932b5, 0x80d746f9, 0x49ef7804, 0xd2e28e93, 0xe52deb8f,
10681 0x9d782cdb, 0xff337c51, 0x509bf1a9, 0xb5cb2e2e, 0xeb6f4758, 0x7576c5bc,
10682 0x7596bc7a, 0xba5da1c4, 0x00c78fcc, 0x7e41c93b, 0x6fbb2f9c, 0x3c6115b2,
10683 0xe38c91d3, 0xc060523c, 0xba060a16, 0xaa3f50b2, 0xe2d57fef, 0x8496c5bc,
10684 0x881b0ef1, 0xcd12d172, 0x9c384eed, 0x1efd05a3, 0xbe08ae5e, 0x88d6a3c8,
10685 0xddc624be, 0xe822af68, 0xb9e27195, 0x38e71613, 0x42dfd11b, 0x03ad277e,
10686 0x38eee5f8, 0x0ebc44e7, 0x6c64c371, 0x3cf0a587, 0x558b29cf, 0xe2538bf0,
10687 0x9a6bb97e, 0xa71e422d, 0x3841bcb7, 0x3c6d671c, 0x4f9e138f, 0x9f355b50,
10688 0xe7ac4730, 0x26ab04ab, 0x30b4a3cf, 0x423ca467, 0xe348cd9b, 0x394e9d52,
10689 0xee5de946, 0xf23fba86, 0x992f98ca, 0x4e281cce, 0xda5b2329, 0x36928f31,
10690 0xf302b7ca, 0xe1098d2c, 0x6335e872, 0x5bafa57e, 0x7185ec97, 0x897701c9,
10691 0x1ed8e011, 0xa5f04c9f, 0x4815fab0, 0x1d6ea1af, 0x9ee87a2d, 0x06a49f68,
10692 0x50a4307b, 0x509047e8, 0x655bca33, 0xa441fbac, 0xfacab0f3, 0xf3054655,
10693 0xf5195e50, 0x9dc969cb, 0x38fe036d, 0xa23a37bd, 0x9b13f75f, 0x6952fbd0,
10694 0xef0a961f, 0x7840c179, 0x93c2fa18, 0xa1de11b3, 0x97a6dc2f, 0x5ff5e242,
10695 0xdf040cd8, 0xb28bbde9, 0x30fe7e29, 0xf4e6e58a, 0xe0a3779c, 0xdf02158b,
10696 0xf3231aaf, 0xdc6233dd, 0x93e9eb55, 0x6b24e7e0, 0xb633f4f4, 0x5d4cbc90,
10697 0xd3d279ed, 0xf429b03f, 0xb7d37f9e, 0xf803ebec, 0xe64ab7fc, 0x7a2fbc40,
10698 0xebe52371, 0x8cb6355e, 0xa9eb82dd, 0x07cc31d3, 0x9bf7d9ec, 0x4fd07d7d,
10699 0xa08654ac, 0xf9f9707f, 0xf11b9b83, 0xb355bffa, 0x34ff8821, 0xe612e3df,
10700 0x3732be05, 0xdabebe13, 0xc056c514, 0x6e1e1692, 0xe843fb19, 0x31d1afaf,
10701 0xebe12bd4, 0x74193786, 0x0dfad8a9, 0x7f4e62ba, 0xdd2a7fd4, 0x488cb181,
10702 0x886e950f, 0x7b67d43f, 0xf046bd36, 0x8f6d70ab, 0x7a2d70e7, 0xe458eb71,
10703 0x36353e93, 0x2a34f309, 0x9da8ff5c, 0x33f686b8, 0x2572e820, 0x8e1ef9fb,
10704 0xe19fb70b, 0xc5897376, 0x5dc71479, 0x15ce7ec9, 0xe847b5fc, 0x8f298561,
10705 0x1d92be60, 0x27de51d4, 0x6c732e9c, 0x9fa3f23d, 0x3f22aeda, 0x8b66c53a,
10706 0x6cdd1f98, 0xd9b47ae4, 0x894ce6c6, 0x04130f20, 0x5d75babc, 0x898bb446,
10707 0xbd44526d, 0xf5c2ca74, 0xafcde812, 0x23d3ee49, 0xf808d5eb, 0xff70ec95,
10708 0x5dfe2dfa, 0xa120aa38, 0x5dba0c7f, 0x3d9d4f80, 0x8f029f14, 0x7c555e2a,
10709 0x884be2fa, 0x3f0b365f, 0xa4bc7b73, 0xb3aee389, 0x169ce3ab, 0x2f664f7c,
10710 0xced13afa, 0xedf8039f, 0xa5c4def8, 0x575f934c, 0xf589eaf3, 0x1438c95e,
10711 0x3ca302cd, 0xbdddb65c, 0xbae300c2, 0xf3c73046, 0xb0af8fd0, 0xb3bea096,
10712 0x31da3b55, 0x8678deff, 0x971b37e7, 0x9a4adf30, 0x73fff187, 0x2a7ca5f7,
10713 0xe965dde2, 0xf5d41769, 0x67eabd81, 0x22e570e7, 0xabd9bd5c, 0x8517286b,
10714 0x17276ff6, 0xd6e891c5, 0x6bf5cf15, 0xebdff184, 0xe2b7ce85, 0xf9d12bf5,
10715 0x390f510e, 0xfc853f12, 0x6b3f944d, 0xe1ee907e, 0x918e2cf4, 0x7b7cb1fe,
10716 0x19dcbc4f, 0x276b2f09, 0xb8f4f2e8, 0x88ed164e, 0xda167764, 0xffbcf3bf,
10717 0xcf527b42, 0x69fc3fbc, 0x56e7e7fc, 0x0ebede3a, 0xa64b7ce1, 0x1fb9e938,
10718 0x5f311877, 0x55a7e6ac, 0x4b5f3d78, 0xb9fa09cc, 0x5a996bf3, 0x9b5d7af5,
10719 0x57718854, 0xe48beec9, 0x7fb6771f, 0x6771fe4d, 0xbeac7f98, 0x4f605ef7,
10720 0xb2d18f94, 0xfcfff885, 0xcbcf1e06, 0x48e9f94c, 0xdfb3c380, 0xf10a7cc0,
10721 0xb40ff92f, 0x679fe85e, 0xf1c7e1cc, 0x1ec9625b, 0x8f30382e, 0xac5f1cf0,
10722 0xbe084a63, 0x4cd19c12, 0xbd97c109, 0x27e9a6dc, 0xc668fab9, 0xabef4ca7,
10723 0xbee69fb9, 0xbd3f7341, 0xcfd340ba, 0x3349bfac, 0xa9597b3e, 0x1de39fa6,
10724 0xafdf19a7, 0x3f4d76e9, 0xcd6ef9b7, 0xb8e6cdf8, 0xe00ea9e7, 0xc3fa0675,
10725 0x7ac52b7a, 0x8f7f5baf, 0x97e639e6, 0x992f58fc, 0xf9fdc82f, 0xb1fb31e6,
10726 0xf229525e, 0x16fbd713, 0xdf9de669, 0xe82fcdac, 0x74bed759, 0x4f9d5fc0,
10727 0xbfa1f872, 0xfef6bd60, 0x848dd6c2, 0xed3e85cf, 0x6a2fc5f5, 0xa687f9fb,
10728 0x4c71c40e, 0x7f442aef, 0x6d76d7ee, 0x748ae2be, 0x55775ef6, 0xd54a8e74,
10729 0x68acd9d2, 0xbf8e1ce9, 0xd85b3c98, 0x37dff87d, 0xa1d62fe0, 0x0aef8be5,
10730 0x6bb07f7f, 0x621b9cf3, 0xcf51c7dc, 0x952eb775, 0xcbebe619, 0xbbb23d79,
10731 0x83fccbf5, 0x7d3c844a, 0xfd3c8f6e, 0xbb10f627, 0x3be9e6a6, 0x2372feb1,
10732 0x97f516fb, 0x3c457fdd, 0x31e58144, 0x8acdff80, 0xf5cba61d, 0x2f307316,
10733 0xd4bfae1f, 0x5ff7f416, 0x83d7a4ec, 0xf055aa75, 0xf7f8b0f4, 0x5aa7085d,
10734 0x9eef18c7, 0x88def04b, 0xff808c80, 0xea9d7c2c, 0x4b87803c, 0x12f8cf38,
10735 0x51c60c5b, 0x4bdcf75b, 0x4b6b0171, 0x480efae4, 0xc43e3a1e, 0xda3d253f,
10736 0x234cff82, 0xe44c68bb, 0x1894d176, 0xbf31c712, 0xd857bf8d, 0x51e6dec5,
10737 0xb5bd18eb, 0xea992ed2, 0x8f585d31, 0xfbd7a089, 0xf683fe26, 0xf91e8be5,
10738 0x4589bed0, 0xf7c27121, 0x7ea1f7bb, 0x26e7bc07, 0x63627bc2, 0x414a6ec1,
10739 0x98d3f9bb, 0xaeb79238, 0x3aefb203, 0xa4de70b8, 0x0506dbc4, 0xf0e12deb,
10740 0x9dd9348e, 0xde7d10fa, 0x66ed6926, 0x43f70163, 0x9db9120a, 0xf8f0b2ad,
10741 0x7be8ac75, 0x4f76fcc2, 0x414f8f13, 0x42dbaa1a, 0x89b1c1fc, 0x5cfe34b1,
10742 0x5c58c974, 0xdf1146cf, 0xf448e637, 0x224946be, 0x5f1e5efb, 0x75d7163a,
10743 0x8e525ec1, 0x3e044ae3, 0x046fa2c7, 0x0e5f736d, 0x0df6228f, 0x13ebf3a8,
10744 0xb6127c61, 0x4d8ed4a5, 0xc83f0ab4, 0xfbd2037a, 0xde93b444, 0x8d65946b,
10745 0x93b6a55f, 0x2ebaf912, 0x0a2acda2, 0x2168c9ca, 0x1e846337, 0x1471fcc3,
10746 0xc2739309, 0xde4d64e8, 0x513188f8, 0x7a258de4, 0xbc7489dc, 0xb7b1d055,
10747 0xcf33b23c, 0x69d507ba, 0xad791e78, 0xd591e799, 0x3c8f733c, 0xc44c63b2,
10748 0x21d2323c, 0x879416c6, 0xf5978985, 0x9bea0673, 0x278e9cc6, 0x1c7f23c6,
10749 0x23cf1d92, 0x31bcc7e8, 0xe2b700f9, 0x91f039d0, 0x4ad81b11, 0x7817f433,
10750 0x1933ca15, 0x2d8b0e20, 0xc3efca08, 0x9f843989, 0xa6fd47c1, 0xfc3fb87c,
10751 0xf31dab98, 0x31a603ca, 0x66ffaa1b, 0x87165cd6, 0x1606c4fe, 0x29596e31,
10752 0x64be39e8, 0x9e728c97, 0x12fc05d4, 0x052b1e81, 0x578e403d, 0x77873d20,
10753 0xeec9bbb9, 0xaa403d08, 0x3da3e30c, 0xc397f23a, 0x57103f9f, 0x7bd230f6,
10754 0xbe722fb0, 0xc385a2e4, 0xfd718c61, 0xbc1fe704, 0xfa88c3ad, 0x37aa8166,
10755 0x0f4c752b, 0xe82a9df4, 0xaf037537, 0x978bb353, 0x9faac92e, 0x867e68c5,
10756 0xb4c160fa, 0x1fe61f58, 0x78e5b416, 0x44972e09, 0xdb4f15f9, 0x17f61761,
10757 0xc56a1d0c, 0x7bf9d778, 0x47927d26, 0x7ae31a2e, 0x513ecf47, 0xcfd900f5,
10758 0xdc5baa44, 0xa2eaf82e, 0x41382145, 0x018daf3f, 0xb0d82c3a, 0x53ee1762,
10759 0x19dfef78, 0xca8e27d5, 0xb270c35d, 0xcb39003b, 0xb3d5b00a, 0x387c028a,
10760 0x2699e695, 0x0d7ef1e6, 0xdf0535ef, 0x01db477b, 0x0351cf5a, 0x5f809af3,
10761 0xa5de773a, 0x98dabfa0, 0xff107264, 0x71d7ba8a, 0x1910fdd9, 0x1d577d0f,
10762 0x2da33682, 0xd606bac6, 0xb8c8cab1, 0x768bab7f, 0x5a27fe20, 0x2fc4f43a,
10763 0xc47a5d89, 0x674159e3, 0xdfc9f1f4, 0x2744624f, 0xe9c75d39, 0x7df0ad96,
10764 0x79b5fd23, 0x751377c0, 0x1902fe42, 0xcc627d78, 0xe0154b3b, 0x2aeb03cc,
10765 0x7f41e9c7, 0x677f8c4f, 0x0ff40e69, 0x4e3f9bae, 0x313dfc0f, 0x732f9dfd,
10766 0x5adfd440, 0x0fefc557, 0xbecbe77c, 0x5bac0fd0, 0x4cdfefc0, 0x59decfbc,
10767 0xf30e3d57, 0xd65eeffb, 0x07fe7c0b, 0x57ef2e64, 0xba51cadb, 0xc67148fa,
10768 0xcf3544b1, 0x1ef80ccc, 0x8eefdb57, 0xa9759da2, 0x41a770f5, 0x8e470f53,
10769 0x8dbf0131, 0x12c57c17, 0x8c0ec8e3, 0xaf1bf413, 0x18fed3f7, 0xf84fc99d,
10770 0x58358ebd, 0x5b006f91, 0xf6152eeb, 0xaed07f7c, 0x724bf969, 0xe80cb632,
10771 0xe256292d, 0x98cb5593, 0x3f768cdb, 0xf1d78758, 0xe1733c3a, 0xd47855fb,
10772 0x0b80f7f7, 0x85b7ab48, 0xe681b5c2, 0x1ceae151, 0x7945e512, 0x0aa7ed52,
10773 0xf5d4a757, 0xb7bf262c, 0x013fbda4, 0xdb19d6e9, 0xff412595, 0x4423a4c5,
10774 0xaea4cec7, 0x48472567, 0xa8e9c0df, 0x38c5727b, 0x19e7bc2f, 0x024ba9d9,
10775 0xf91946fc, 0x8c26933e, 0x8f3de057, 0x58bdb924, 0x73be03df, 0x32ef91f8,
10776 0x4687a48d, 0x27e6d50d, 0xcf9c492c, 0x3a3b459a, 0x30feb9aa, 0x9b67a5f0,
10777 0x78c056c4, 0x236ec5cf, 0x6d8989da, 0x684e8c27, 0x309db6eb, 0xc3aabea2,
10778 0xb753cc3e, 0x6f5118c1, 0x7992486d, 0x0fcc329e, 0xe0399bde, 0xc7dc44a1,
10779 0x45512950, 0x091ddeee, 0xef7fb1a3, 0xf8255c5c, 0x8eb7232d, 0xb966c7c6,
10780 0x76c21fda, 0x8bd8eb0e, 0x2dc3342c, 0x99d2fc6b, 0xbf1a31d5, 0x5dbd5676,
10781 0x0cd39fd3, 0x9eb901d4, 0x1b5d2cb3, 0x5b88303f, 0x2c199e01, 0x6dfa87f8,
10782 0x8ce3a0ba, 0xdc01b5d4, 0x6dc332c7, 0xcc8476f0, 0x856db137, 0xd77086de,
10783 0xbf520e4b, 0x73e0a65e, 0xa10af933, 0xeb437bd5, 0x795ba362, 0x86aea332,
10784 0xd815fbfb, 0x5456bc07, 0x42453e4b, 0xbee9183c, 0xfba255a7, 0x47c7d69e,
10785 0xcf323ee1, 0x26f28952, 0x3c447dc9, 0x1cefec24, 0x51e82b01, 0xf333ce03,
10786 0xa3b312fb, 0xbefe10de, 0xe99cff0a, 0x3f89a7e5, 0xaeaf9f85, 0x7602ba73,
10787 0xc9cfae17, 0xfe80c4fe, 0x64efac35, 0xda9f0687, 0x6d7aacfe, 0x6d32ce7f,
10788 0xf0926a7f, 0x81b207df, 0x93d34f28, 0x55ea3d24, 0xe645ffb5, 0x01f96ffb,
10789 0x6bb2cd9e, 0x8d67f226, 0xa8f54fd1, 0xfa9bb2cd, 0x5eb87dea, 0xc0ee48c7,
10790 0x9639201f, 0x19573e48, 0xf412d69c, 0xe2256ba3, 0xc42c99db, 0x8e09c85f,
10791 0xb3dcbea7, 0xd71268ff, 0xaeccab3b, 0xdb1754a5, 0xc1375929, 0xa77a51a5,
10792 0x55c0fd1e, 0xc8bce452, 0xdedc4963, 0x8a20c5be, 0x2006b807, 0x9f5da293,
10793 0xc2f3ef1a, 0x76fc077b, 0xfbfd17ae, 0x07c08501, 0xb73dca0a, 0xbd85e337,
10794 0x25fe0499, 0xe4037ffa, 0xdfa4e996, 0x495a346f, 0xa43b0bbf, 0x2fe70bea,
10795 0x7c6876b4, 0x3f8a7ec6, 0x7b5fad26, 0xff62f50e, 0xc782ce7e, 0xcc47be01,
10796 0xec8ffdfc, 0x2fb87c90, 0x3ed06ea7, 0xc0299fd2, 0xbadef816, 0x5b47a154,
10797 0x52aefbb5, 0x2e61af50, 0x7a20c27f, 0xe5499a6f, 0x41e92776, 0xbbaa5fc9,
10798 0x4529fa04, 0x0ca6f7bc, 0xbc95f085, 0x75c245a8, 0x0aef3267, 0x463fe3b4,
10799 0xb60a4c21, 0x8fcfed57, 0x79fdc292, 0x65e6124b, 0x148c3b52, 0xe32eb1ef,
10800 0xeba7943f, 0xf2327f39, 0xb0fcf859, 0x0757aa7c, 0x718bf2e3, 0x77b9af98,
10801 0xdc6fbf67, 0xb49b24ef, 0xaac1b771, 0xe7c7bb8d, 0x44cff569, 0x4cef5687,
10802 0xb9a7ee2e, 0x5039c53f, 0x796a7f73, 0x877fa6a1, 0xf8cd66eb, 0x6997a6bb,
10803 0xe3a951fa, 0xda00f2c2, 0x9e4c4afc, 0xeb12bf36, 0xa251e6d0, 0xba7afc0e,
10804 0x9a317804, 0xc06e1dbc, 0x46c81343, 0x47682db1, 0xa899c606, 0x685d1b48,
10805 0x34db60b6, 0x7c8fca24, 0xc787d4d2, 0xbe0751e1, 0x7987ea9f, 0x4c5bf14c,
10806 0x49788a58, 0x8a6295f2, 0x7544d018, 0xd41e1bd5, 0xd3d39bfa, 0xeda95cb8,
10807 0x99f724b1, 0xbc1bac64, 0x7f73a4a8, 0x89f14036, 0xbf719a29, 0xfc89bb68,
10808 0xbe4e3522, 0x9465a71c, 0x0eba409c, 0xf549d07a, 0xaccad613, 0xde7c5798,
10809 0xdba9f228, 0x41dc3ef9, 0x673a1dad, 0x492f7c88, 0x49e0fae6, 0x9c58e957,
10810 0xac0daebf, 0xfad3ca2c, 0xa7588c8f, 0x8f6b6bac, 0xef967b43, 0x7988c8fa,
10811 0x6175e0bb, 0xd15df4e7, 0x55f95f58, 0xff711c8b, 0xf7cc92b2, 0x7a13ec6b,
10812 0x83f7d67d, 0xb0c951f1, 0xb59e7ea0, 0xc32fcbb5, 0x5e8167fb, 0x4a6bf2f3,
10813 0xfa0d3d24, 0x3ccf1359, 0xa7eea699, 0xc1ec6a71, 0x037ec5dd, 0xed6a9fd9,
10814 0x78d339f8, 0x5c7a045c, 0x91a33d7b, 0x1d630bf4, 0x815bcc06, 0x8fdcd75e,
10815 0xd271164b, 0x12e83640, 0xaea381e8, 0x2bb5fbc8, 0xc744f4d3, 0xa232eea3,
10816 0x4f8093c3, 0xec9f97f4, 0xd78e3f81, 0x65ede12b, 0xfa1081e4, 0x4fab8f85,
10817 0xcbf47ee3, 0x07ede8bd, 0x979f7d04, 0x54a80502, 0xe268ae3d, 0xb9a699df,
10818 0xf73f718b, 0x1aafccbe, 0xeb315eb1, 0x7b4312d7, 0x03f687fb, 0xb8cf8fb4,
10819 0xee326f75, 0xecb4f4af, 0x7fc0664d, 0x05650635, 0x1fc0f3fa, 0xea7ff40e,
10820 0x7f04fd5a, 0x3b614b6d, 0x956daf5e, 0x3d92a81c, 0xa18dcedb, 0x468eb275,
10821 0xdf3dffac, 0x93235c0b, 0x5b755fb9, 0x04f3c2b2, 0xda27786e, 0x3e516dfd,
10822 0x00fc849f, 0xdae109fa, 0xe866b121, 0x14dabf3f, 0xa0fbeeb1, 0xd59ef7c0,
10823 0x6ab38a46, 0xc75c79e0, 0x467dccbe, 0x56d3f213, 0xeb849758, 0x0c477c38,
10824 0xc0d4bfce, 0xe150cfd0, 0x3819933b, 0xb0ffeb8e, 0xb81d0212, 0x2652aabe,
10825 0x54b87f7c, 0x9fe723e4, 0xb8c74c6a, 0x77ef96a6, 0x4dd95ddf, 0xab0fbe79,
10826 0x36569fb9, 0x397240df, 0x57f70963, 0xe55af9c2, 0x9f05a7db, 0x386ff386,
10827 0xd7e0f6df, 0xd7e3abea, 0xe6bf20ca, 0xfa07dda3, 0x3e414e8f, 0xeeff01fa,
10828 0xddc5fa65, 0xbb801486, 0x81d5a36f, 0xcb06bdfb, 0x519287be, 0xf7e6ec6f,
10829 0x946cd487, 0xee51feb8, 0x37a5f5c6, 0x091ad919, 0xedd389f9, 0x85374101,
10830 0x14314975, 0xa2fa05ff, 0xbf51ca9e, 0xe9b03087, 0xa73f315b, 0xf067fae7,
10831 0xd71ba96b, 0x6e6ff084, 0x555be732, 0x32340e2f, 0x07aa56f7, 0x0299f4b4,
10832 0xe06cbcf3, 0x312c9cf5, 0xaebf6e5f, 0x5da05331, 0xe4f5cc9f, 0xda87010a,
10833 0x80e4275f, 0xf84ddc65, 0xf8e2689c, 0x5fccb71f, 0x99f8eb81, 0xea30fdd1,
10834 0xef5909d5, 0x6bdda0d7, 0x20e6fbea, 0x07321fca, 0xbc6ae1f9, 0xa7c47bbe,
10835 0xf583ee1b, 0x268faf9a, 0x3e779afa, 0x367e456e, 0x714d0ee7, 0xb53fe047,
10836 0x61c85cf5, 0xd5f03b6e, 0xaad47e85, 0x4ebb29fd, 0x729f691b, 0x2431b9db,
10837 0xe8d2172f, 0x535cfaba, 0xc1cf971a, 0x9aa83f62, 0xadbd04cf, 0x8e082e2f,
10838 0x70c0f153, 0xc2115e77, 0xebd102f3, 0x086c25be, 0x4e3fab4f, 0x73599feb,
10839 0xf30b9a58, 0x1a7065dc, 0xf7ef802c, 0xc62fa7e3, 0x2e6f2ffd, 0x851dcc67,
10840 0xcc4ceffb, 0x03ee1d7d, 0xb03f52b4, 0xeffa953c, 0xdda8572c, 0x84bd7262,
10841 0x4f63ba78, 0xabed2e7d, 0x55ca7ccc, 0x3ce9ef0a, 0x053b1068, 0xa827e44d,
10842 0x36eea1f5, 0x7ee09999, 0xea8936f7, 0xb3fc2a9d, 0x3733a42f, 0xe3df97e8,
10843 0xdac1e0fb, 0xde92ef65, 0x1b9f5473, 0x90d27183, 0xd88d139a, 0xf3fb2cf7,
10844 0x8e2ff418, 0x3e413d83, 0xa59fbf03, 0x0e4fa84a, 0x5ddf711b, 0xcd3b05c5,
10845 0x6baeb2f3, 0xf79dca0c, 0x50ea890d, 0x19cf5bc7, 0x62bdb853, 0x5806ca08,
10846 0xffe0139f, 0xeb813922, 0x3a21b693, 0xdca1df4e, 0xd0fc11af, 0x71d7c37e,
10847 0x32d30f48, 0xf19bede5, 0x4332fdf9, 0xda535eb9, 0xa08d6715, 0xbcc28f87,
10848 0x75c15c98, 0x7f7e1b60, 0xeb9bd1ba, 0xeba6e780, 0xfa9bef22, 0xbe72f92c,
10849 0xff14e482, 0x0ab7e024, 0x60b36fc1, 0x8a36f149, 0x20d1fc83, 0xcadab3cf,
10850 0xadb1eb4e, 0xda47d897, 0x147d8cf8, 0xc6f7c7e2, 0xadb6df87, 0x8372f9c3,
10851 0x59238c7d, 0x71845f88, 0xdfbcd324, 0x994cf3cb, 0x11dc53fd, 0x0e5979d6,
10852 0x03bfc03a, 0xe381d57a, 0xdf91d8a4, 0x767b5207, 0xca0ac3c7, 0xebba298f,
10853 0x6c17b429, 0x8ee28e80, 0x1fd6af5a, 0xe5ca963a, 0xc0aa58e1, 0x7e368a5b,
10854 0x4e493882, 0x1c5271e1, 0xe2438416, 0x14ebf0a7, 0xae50993f, 0x8103bde0,
10855 0xa244af3e, 0x29a96a4f, 0xabe50925, 0x019cf899, 0x857f239f, 0x229ed3af,
10856 0xae42d9f2, 0x235ca067, 0xb972b6ff, 0x3bb79f0e, 0xf38ec4b5, 0x5c7dc6ae,
10857 0x69c6f411, 0xf5daceb1, 0xb3cbe112, 0x3a784ede, 0x4abbd6c3, 0x00cf2f81,
10858 0xa02fb81c, 0x498ae5d3, 0xdb8d7ac0, 0x04b36315, 0xfadd40f5, 0x756e7a18,
10859 0x73eddbff, 0xc2979fa1, 0x6b6cfef9, 0x3cf10999, 0x3f973d7b, 0xfdc77df5,
10860 0x4f28ec33, 0xa32e8645, 0xb467ee03, 0x3f43889d, 0x54c768b0, 0x6f61ca3b,
10861 0x70a86670, 0xf16fbb2e, 0x07e73b49, 0xf5aa6fcc, 0xbf4acf38, 0x78bff111,
10862 0x6dfe2319, 0x3a87fedf, 0x6db3e394, 0x87b45631, 0x78c67667, 0xbe77ff51,
10863 0x49d3e511, 0xe3788714, 0x319daf41, 0x7f224c74, 0xc56c8773, 0xc6f3d1f8,
10864 0x3ca14fe7, 0xa147b67a, 0xb716c7e7, 0xed0e7c3d, 0xd8db4d5e, 0xda7cfad3,
10865 0x954ffe87, 0xf765da87, 0xfed57ad3, 0x0a4dcbe7, 0x7ab3d1ea, 0xb71627ae,
10866 0xeffe4abe, 0xf9dd8be2, 0xb33f0f58, 0x50c36ff3, 0xdb7e79af, 0x99f50c3d,
10867 0x61eef5e7, 0x5af3df78, 0xbf247d4c, 0xf3c697c5, 0xccbdaa40, 0xe4d7a239,
10868 0x5d85a28b, 0x2e6869c8, 0x459d7dc7, 0x3039a787, 0x2fdeab9f, 0x7ed1d5ca,
10869 0x46f7a2fe, 0x3c87e7d9, 0x97d010d7, 0x87a1f5e3, 0x8654c547, 0x41aa65f2,
10870 0x555e37cd, 0xeaef079e, 0x75e48587, 0x19a73a02, 0xe80eadc6, 0x6adafef9,
10871 0x06f187c9, 0xcfe12ff8, 0xb9d53f91, 0x435beed0, 0xfc6b827e, 0xcfd8a1e0,
10872 0x5051ac75, 0xf6f698ad, 0x6697f10f, 0x28fe7404, 0x6de9a3e0, 0xf7f27e51,
10873 0xd413fa03, 0xecd47e17, 0xe6c69f73, 0x34f21148, 0x468cef79, 0xaf9e1e3d,
10874 0x8458bf81, 0xdeaff55b, 0xa3f9e34f, 0x0eab7a8c, 0x345667f7, 0xb5e22b30,
10875 0xfa675e47, 0x0a2f946d, 0x8128efcf, 0x4e7c2675, 0x22b3afe9, 0x8a5faabc,
10876 0x4116dc74, 0x72a6240f, 0xaf9544bf, 0xe88e8086, 0x352810d3, 0x563687f5,
10877 0xab36d7c8, 0x68f7be8e, 0x09ba9b68, 0x170d0bf3, 0x0c198aef, 0x723869ef,
10878 0x3defc33b, 0xa6a5ad3a, 0xe2ee7c5c, 0x063ba66d, 0xfc26f905, 0xb852c77d,
10879 0x0bfa0cde, 0x21dfed91, 0x59fecfa1, 0x8a40f076, 0xff3de44e, 0x1083b6ef,
10880 0x7852079f, 0xe7933e7c, 0x1e7c784f, 0xbd543f6e, 0x092bceac, 0xcbd4f73a,
10881 0x81cfc9a7, 0xb2f49a38, 0xb8d0aa94, 0x7629b68c, 0x4c8faf8a, 0x9e962bb3,
10882 0x3bd3f7f3, 0x3d41b674, 0x39fd57e7, 0xd7b9d78f, 0x938f7184, 0x4cf323ef,
10883 0xaddf6893, 0x5c79ffea, 0x9ee5f912, 0xc70f830a, 0xa60570a9, 0x1dec7cf1,
10884 0x2ccf834e, 0xd544fd05, 0xdf7cbc8f, 0xd57dd121, 0xc7fd54af, 0x77e78b80,
10885 0xf7e50da7, 0x17dc98b7, 0xf71f2ed0, 0xd17ae99b, 0x319d7e08, 0xab8c5ed7,
10886 0x6253baee, 0x5f8407a4, 0xb869f2a9, 0xadbe79df, 0xa3ee37df, 0x53f820df,
10887 0x30acb395, 0x58ed50f9, 0xc7970a5e, 0x85e3b43a, 0xaaffc768, 0xe7c3cff1,
10888 0x496e3b05, 0x3d18e7a5, 0xbd3df43f, 0xfebc522b, 0x0ca790ac, 0x3d817e95,
10889 0x266f0825, 0xd83ed00b, 0x7c6becde, 0xded7971a, 0xb909e7ee, 0xdf3c92b9,
10890 0x3fccf426, 0x52cb9e4b, 0xb5f877ff, 0x5ec3fd97, 0x2cfbc7be, 0x2a4264b5,
10891 0xae5a35e0, 0xfca0940f, 0x6221a7fd, 0xd85d3add, 0x3577886b, 0x699bd9f4,
10892 0xe47c61d4, 0x83f9e6a9, 0x6de504a6, 0xc80e638a, 0x317b3fb4, 0xc7e883c4,
10893 0x4090ba2d, 0xcbfa0d6d, 0xf17cced0, 0x6623d530, 0x6fe16b56, 0x3e2e9cc2,
10894 0x87c724bf, 0x362cf3fe, 0xb34cf28a, 0xb8ac12da, 0xa929b9df, 0x95ca1f65,
10895 0x6cac9377, 0x50bf1d0a, 0x79e26f1d, 0xb46965b8, 0xf98592bf, 0xc3eab303,
10896 0x7fad7efd, 0x1bc8b370, 0xbc27e6f5, 0x7ae66ede, 0x724cbf65, 0xa6f9875e,
10897 0xb633191b, 0x59e0bd71, 0x7524f3c6, 0x7be82b6d, 0xff715aac, 0xf2807d33,
10898 0x835f5450, 0x1edba7a1, 0x6479464f, 0xa93d6d4e, 0x48f785f6, 0x95d7865f,
10899 0x5eb8db6c, 0xa2c8d4f2, 0xc24c348e, 0x93c42d7e, 0x2a5fe829, 0x3bc464ca,
10900 0x57d9a5c0, 0xcf05faa6, 0xf9d2ba8b, 0x1c531ffd, 0x2f47733a, 0x71a6a475,
10901 0xf6248ebc, 0x23acf46f, 0xae9bdbed, 0x548eb95c, 0x80d87ad7, 0xea95c5f1,
10902 0x5ea4cf49, 0xde5127ae, 0xf3cf5b31, 0x926dd9bb, 0xd955f315, 0xc3dd7c6d,
10903 0x7f934757, 0x958fe63d, 0x2a07d476, 0xe14ece9d, 0xe1fb3df8, 0x75b42597,
10904 0xab7a8fe0, 0xfaf5d619, 0x4ddf4b87, 0xa4c57de7, 0x634b73e0, 0x3fe9bbe8,
10905 0xf8831bde, 0xa45a1d7d, 0xf5476bcf, 0xc193f391, 0xa92bf57c, 0xf9167794,
10906 0xc3d83d6a, 0x275e60d8, 0x855bb9fc, 0x70826bbe, 0x3b9af285, 0x29bfdd78,
10907 0xfa8e3dcd, 0x36cbeb3f, 0xa4e89f91, 0xc0abf47c, 0x1a3798d7, 0xbac58b08,
10908 0x59a32ff4, 0x9a91d603, 0x926fdc92, 0xa74cfd1c, 0xf3c11ca0, 0x6ef27f54,
10909 0x623ec855, 0x3ceb0bea, 0x858046f9, 0x7df03bf6, 0x3a083713, 0x8b3c41a6,
10910 0x33402571, 0x03d0eb0d, 0x3f27bd45, 0xfe71e99a, 0x35ee0c47, 0xa97d63d7,
10911 0x4158ef5d, 0x4fb0e042, 0x7759ed89, 0x5ebc9c92, 0xd49fd6ae, 0xf56f79ba,
10912 0x93df0927, 0xea8ff9cf, 0x9cff624d, 0x7762675a, 0xb5f8a8ba, 0x619eb8aa,
10913 0x832c3afc, 0xd2faeb5d, 0xd42392df, 0x4c294c7f, 0x7ada67f8, 0x57bc9ae3,
10914 0xdeff4f88, 0xa96de33a, 0x1efb1fec, 0x0adc07a6, 0x0c322eff, 0xe709a1ee,
10915 0xfaee2993, 0x91c4bfef, 0x26eb6d9d, 0x15d9d87b, 0x7f9402c5, 0xf779e0ec,
10916 0x503dfe36, 0x496fc427, 0x7e767621, 0x57779f0a, 0xfff1195b, 0x18a8c0b6,
10917 0x0a58ff1c, 0x23eac7a7, 0xbfa2a6d3, 0x69e80def, 0x3c630ebf, 0xd016db1e,
10918 0x72dfa117, 0x9a92e90d, 0xd12e891a, 0xcb853edc, 0x7f6121d1, 0xba72a50f,
10919 0xe3c87d95, 0x5e52cf30, 0xbd0ab15f, 0x75e7a9e0, 0xc9997df5, 0x4f4f9a92,
10920 0xd97f5489, 0x637645d1, 0xf68942d6, 0xfadb7ed5, 0x916913cb, 0x5b33f1eb,
10921 0xbfae444f, 0xfd218f94, 0x3b3e5bd9, 0x4b7d8f3c, 0x0f63c89a, 0x5fec79e6,
10922 0xbd695aa5, 0x2521fab6, 0xfaeab2c8, 0xbe1d21af, 0x87408b48, 0x5c7f386b,
10923 0xdf5b77fa, 0x7d5230fd, 0x6fce1af7, 0xe16efe4b, 0xa7e92257, 0xf3bf386b,
10924 0xfd7f9e3b, 0x8aff3c77, 0x77ff18ef, 0xff9844a5, 0x01fdd5ff, 0xf0fff5e1,
10925 0xfbe102fd, 0xcc0ea200, 0x87bde2f7, 0x7e5db5a5, 0xdb714d68, 0x07a04ba7,
10926 0x982f09f5, 0x184e8ed0, 0xab61ebc1, 0x1b7c9947, 0x01bee0a5, 0x832c5f15,
10927 0x41d611c7, 0xc076bce7, 0x30339673, 0xb2f98eca, 0xe0e28c11, 0x8baf334e,
10928 0x6d35bd31, 0xb7c3ed0a, 0x7e0edda6, 0xdf2f5349, 0x174e6d33, 0x762f6171,
10929 0xc9466464, 0xacefa867, 0xd5a5fb61, 0x6aea29d6, 0x0fbe56d6, 0xb495e997,
10930 0x4abde9db, 0xf143fa1a, 0x38f5f87b, 0x246e733f, 0xdb9c94b8, 0x72541e29,
10931 0x4427be10, 0x6e36d7fd, 0xa5e60e40, 0x6217e06d, 0xac71f05d, 0x6b3c520f,
10932 0xfbea71a5, 0xbf87d87e, 0x930309ef, 0xbdeb9eb0, 0x6273ef9e, 0x5d4d6a96,
10933 0x7fc1a0ef, 0x7544ae72, 0x8c0fb93d, 0x0ff3a43f, 0x30473e7a, 0xd077e031,
10934 0x1bd52b36, 0x1ff11adf, 0x26bbfc79, 0xcfbbe75e, 0xc6ec87ca, 0xb8e019b8,
10935 0xf121676f, 0x235dccef, 0xf8c0a83e, 0x2f3f3fa3, 0x295c47a4, 0x454705f2,
10936 0x17cd43be, 0x63adf5a8, 0x1c724f22, 0x76d02ff3, 0x5a043e60, 0x5aee8fa5,
10937 0x4fa527db, 0x84f2fd04, 0xde43f3c4, 0x543f3c43, 0x0bf47468, 0xb8394fdd,
10938 0xb9abe70f, 0x50bf5e7e, 0xc59b3df3, 0x207f0a7a, 0x2fc0a3fb, 0x6c1c6c2d,
10939 0xd85f3b44, 0x6d8d1998, 0xc3a7d3be, 0xca8cef52, 0x7e953aad, 0xb868f891,
10940 0xfdeae758, 0x7bdf545d, 0xffeeac35, 0x3f7c3ec3, 0xc7e0b743, 0xd461f61f,
10941 0xbf572fbf, 0xf8c7dd0a, 0x52395691, 0xc416695d, 0xdce708c5, 0x8ab70e26,
10942 0xa57e59ef, 0x6273df0c, 0xb623576f, 0x6539d505, 0x39af7794, 0x9bfe88d7,
10943 0xbef762e7, 0x665f295b, 0x989e3054, 0xbbcda1dd, 0xfe7832d9, 0x7f8955fd,
10944 0xab1de9af, 0x70b8f8a7, 0xc7f89eac, 0xf14ccb36, 0x64c0cdab, 0x70a7f60b,
10945 0x3ca0a8bf, 0x6cfb0cb1, 0x83f9025a, 0x8495fb05, 0x798283f9, 0xa5d8db30,
10946 0x2ba78849, 0x7cd559d5, 0x739316da, 0xeff3d23a, 0x1ed6b3ad, 0x4dfb423c,
10947 0x78a975d5, 0xbda5eb51, 0x7dd559d5, 0x2ff29e0f, 0x3c34fb35, 0x9831aefa,
10948 0x79dc2c7f, 0x5ff628c2, 0x8273535a, 0x1dc2d875, 0xaafea8e7, 0xf53d5bd6,
10949 0x86afc8e7, 0x929ce8e7, 0xfd79cb6d, 0x81c03b75, 0xdbac2b6d, 0x06fcf009,
10950 0x1b6d8dd6, 0xbfaf1bac, 0x5a8f3cb1, 0xb50772ff, 0x531796bb, 0x93ec085b,
10951 0xedbac366, 0x2edbaa39, 0xdf63d3ef, 0x36f5d524, 0x2895aecb, 0x3f7521ef,
10952 0xfdd787ea, 0xaf9e68e4, 0xd037ecf1, 0x839e0c77, 0x25dfd226, 0x31b3736d,
10953 0xb0eaf83e, 0xaee11b3b, 0x085bbac3, 0x3a759c5f, 0xc66e78cc, 0x8cc39759,
10954 0xf6c2b6f5, 0x0fdc46d3, 0x180fa753, 0x90061f31, 0x4596e3a7, 0x7c73b6cf,
10955 0x895b6fdf, 0xc57bf119, 0xffeb58fa, 0x3dfd8faf, 0xa0acb1f5, 0x291e927c,
10956 0x1b9ce970, 0x34efddb1, 0x13d10fcf, 0x9ebc5dab, 0x5f7fbab2, 0xae75c392,
10957 0x219509be, 0xf39435f3, 0x6c6d85fc, 0xf5e8737f, 0x1e061925, 0x4239e047,
10958 0x41ffde11, 0x8e35dd1f, 0xf41fdd5f, 0x9d57e089, 0xefa2643d, 0x2c77da49,
10959 0xc418eec8, 0x1f343f05, 0x32bcbab7, 0xf7cfbf1b, 0xb9628d1e, 0xc9a75f3c,
10960 0xbab0b1c7, 0xb9796f5c, 0xa73ae599, 0x750bf699, 0x0edda165, 0x7d319fcf,
10961 0xebb71657, 0x9e7e74ce, 0x159d3783, 0xb9f51eb3, 0x7bdf33df, 0x8cfc61fd,
10962 0x0bd91d72, 0x50574eb5, 0x81cb67ae, 0x19960b3f, 0x2b9f547c, 0xfba09fd7,
10963 0xb06c6e22, 0x9f23a416, 0xb4683f1f, 0x3c2d5e62, 0x7f28e63f, 0x3c2fa9a1,
10964 0x1c91a8ef, 0xd52bacb8, 0xe07dd4f1, 0x47db5ab3, 0x086dbe63, 0x051a6e6b,
10965 0xafe90fcf, 0xe9fee2b3, 0xbe3cf59e, 0xf840bbff, 0x3679e139, 0x4bf433e4,
10966 0x71f0f3c2, 0xe20f9ce9, 0x9cfdb9d2, 0x0a2db480, 0x173ea3ce, 0xd2f33fce,
10967 0xf0bf75b5, 0xfdc553fb, 0xd582f286, 0x13be91fd, 0x49ed0c74, 0xa9a97943,
10968 0x397cc87f, 0xdb7f7ce9, 0x4c1f5813, 0xf20fad0c, 0x5d78603a, 0x8573d550,
10969 0x831d7fed, 0xfa075ef8, 0x2798ed1a, 0x0a0fd795, 0x8fd928df, 0xa708237a,
10970 0x7a953fd8, 0x04ec7bf9, 0x70c5d7c6, 0xa7779cff, 0x82b9f944, 0x8aee5f09,
10971 0x81733e81, 0x76bd43dd, 0x0b2affb0, 0xfa09a3ea, 0xc7aefc22, 0xd72e92e3,
10972 0x349eb099, 0x71eaedf5, 0xe1419df8, 0x230e431d, 0x30a8ee5d, 0xd540fed0,
10973 0x7b7d4dee, 0x7f7e18fa, 0xbc68cae3, 0xcc39279f, 0x2f2f5e0a, 0xb7e3ebc5,
10974 0xce9331f8, 0xa0742226, 0x4f0703cf, 0xb66e51ea, 0x1825dc98, 0x114e173f,
10975 0x6e0aa675, 0x9b68efa7, 0xe7e46062, 0xeee6ed69, 0x1f28afcc, 0x4856ddd4,
10976 0xee3b23f5, 0xb414187f, 0xc13b8537, 0x3b5ec58e, 0xdd2f363b, 0x11bcf84a,
10977 0x63c218ec, 0xf4ebc29b, 0x11cff4e1, 0x2ecdeff4, 0xd187a6f5, 0x2b39e0fe,
10978 0x6a529f28, 0x60ae3b4f, 0xfa3867de, 0xc21e12eb, 0x35ff2bd2, 0xd096fd0b,
10979 0x4eb73f8b, 0xfbaf7bf0, 0x39ff5aa7, 0xf4e6a675, 0x63751dff, 0xeb52fe35,
10980 0x76bc6a4d, 0xda81f046, 0x3fed159e, 0x1a037dfc, 0x37df88d7, 0xdf7f22d8,
10981 0xce85bb30, 0x6fbf5129, 0x25646bd8, 0x3f71135b, 0xc9def8ad, 0xa4fc8537,
10982 0xbeff4fbd, 0xf88917f1, 0x278493bd, 0x3c3d806b, 0x3d5e764c, 0xedaeaeaf,
10983 0x6d6f9e73, 0x6bc3fbe1, 0xfb9f235b, 0x77da0372, 0x2728ef78, 0x2b51bd23,
10984 0xd98edbf6, 0x9744ea26, 0xebf796f3, 0x1e96f343, 0xeea49025, 0xbc51f5e3,
10985 0xf663cda7, 0x53acb796, 0x96afcfbf, 0xae1f681c, 0x59b70fb4, 0x35edd7ec,
10986 0xe6fce98f, 0x79e1b97d, 0xb5d3f7cc, 0x69939c75, 0x74ff5a56, 0x36e744b7,
10987 0x1aae7499, 0x86ffb7da, 0xcfb48d64, 0x87610bfb, 0xc83a8bc6, 0x3f9c8dcf,
10988 0x44937e7e, 0x77e0dfdf, 0x9ff74878, 0xc3bfc1bf, 0xff0179f9, 0x7bad470e,
10989 0x5cd7dfa8, 0xd07bac1f, 0x77ea77f7, 0x3677ea39, 0x539d77ea, 0xb9d347d6,
10990 0x5a188fc5, 0xebdfb952, 0x3a7cbe25, 0xe8fdd19d, 0x491f5628, 0x97a68f5e,
10991 0x845e9d3c, 0xdc79aee3, 0x423d297b, 0xe30c3bdc, 0x218f7848, 0x3c85e203,
10992 0x305e2916, 0xe2691465, 0xc787ea05, 0xeeaad70b, 0xcfc0a4f1, 0x6df75c35,
10993 0x6bc6fc91, 0xdfebff38, 0x45affcf1, 0x732adba2, 0x1f17f3e4, 0xbe8490cc,
10994 0xce179ed7, 0xc92f7c7a, 0xa4937aed, 0xd533707c, 0x4f540dd3, 0x536af557,
10995 0xbc7f9f2c, 0x6da9a7c8, 0x0c9b6895, 0x4b65f391, 0x6467fdc4, 0x93e438e7,
10996 0xf36a2f81, 0xb45b8397, 0x5b1bcbf9, 0x0c88e7b5, 0x09cf6bf1, 0x3dafdc29,
10997 0xa028a63f, 0xf8663f3d, 0x31f9ed51, 0xe7b43a23, 0x99fcdcc7, 0x5b98fcf6,
10998 0xcbf9b4ba, 0x1edc2f5b, 0x8fa71df6, 0x9c09479f, 0x995cfa1b, 0xb9d85e69,
10999 0x73b0ba35, 0xcec3a26b, 0x1f3b09ad, 0xe39bcc45, 0x7e7613ed, 0x367d768d,
11000 0xba0dc7ac, 0xefdc7afa, 0x1ea228fa, 0xcf8ccfd7, 0xdfde513d, 0xfa9b7e8c,
11001 0x097ff53d, 0xe1913b3e, 0x71f4815e, 0x875b1caf, 0x22b1d57c, 0x2ef30b2a,
11002 0x726995ee, 0xfb83f022, 0xa7be8951, 0x46995d2f, 0x35e67bfb, 0xa93f210c,
11003 0x4fc93980, 0x1167659a, 0x9cd879cf, 0x3decf5c1, 0x8c6606f5, 0x462997c7,
11004 0x33d0a81d, 0xc35b124d, 0x22658ded, 0xe33561f0, 0xfabb587c, 0xbdd51c70,
11005 0xc859dd85, 0xebaac151, 0x0e79d017, 0xa8bde7e1, 0xc623c676, 0x6316b0d5,
11006 0x68bbcc1a, 0x47c93b6d, 0x1e3079f8, 0xea1cf6b6, 0xb096dae1, 0x7db7f5eb,
11007 0x1ff7f8ca, 0x3c8bf446, 0x2ffbdaad, 0x99ba8864, 0x7e503983, 0x9ac7f7dc,
11008 0x152ccfd0, 0x56bb99f8, 0x709d62b2, 0xd27b435e, 0xb79fd05d, 0x4bb8a65f,
11009 0x71eb0fc5, 0x3a20cf4e, 0xfefcfd57, 0xcfa3f25c, 0x8e0a4a2b, 0xb8f1c773,
11010 0x87bbd241, 0x7659f5e3, 0xe73c70f7, 0x58c3ebac, 0x9d87f6fc, 0xdf9320b8,
11011 0x3e50be00, 0x96566ff9, 0x9def9a1f, 0x6326b06b, 0xeecbc5be, 0x5378a54d,
11012 0x7e2abfc4, 0x6788263c, 0xf10fb0e3, 0x749f5f2a, 0x91fa2249, 0xff02eb69,
11013 0x7e03df08, 0x26b3c510, 0x7e815a66, 0x39a569d0, 0xd7605d19, 0x2ff20643,
11014 0x4092d9ee, 0x0d3dc5fe, 0x1f3c4665, 0x096d9ee1, 0x79969fb4, 0xbe30479d,
11015 0xa279e955, 0x2a5f70a1, 0x4b4f7bcc, 0xd2d6438e, 0xd137e4f1, 0x09d35171,
11016 0x7b277e95, 0x48c9dfa1, 0x69ba03f4, 0x4321ffae, 0x6e8209f8, 0x7d3b41ec,
11017 0x64b157e7, 0xffe62e6f, 0xe99bd7ce, 0xc67a2bf7, 0x37ae5e05, 0xc4d26f2b,
11018 0x2e7de53f, 0xbe7475c7, 0x22daf777, 0xdd385fa2, 0xde67ffca, 0x8afefc70,
11019 0xa1963efd, 0x1fab31ff, 0xc63b739b, 0xb79712c9, 0x96c6ab59, 0xa5f3bfa3,
11020 0x8b6fcfd0, 0xc630e938, 0xbfd7e049, 0xf412718b, 0xd27113df, 0x41271807,
11021 0x49c621fb, 0xe7149ed0, 0x0772aa05, 0xfb7c408c, 0xafb790b5, 0x6378d433,
11022 0xd7e62a69, 0xdde7ffca, 0x5f159d22, 0xa349e3f5, 0xec9b1933, 0xd3d7fad4,
11023 0xebfd69a7, 0x4c75830e, 0xd581da2a, 0x8f705ebc, 0x78cd66eb, 0x988c57a6,
11024 0x857960f7, 0x8f64ebc1, 0x3de62314, 0x6bb04c66, 0x94d9dfc6, 0x32dbe9ae,
11025 0x94f75a15, 0xeb9a7ef2, 0xd40c5777, 0x005ee7f4, 0x5df90cc7, 0x59f92629,
11026 0xc626e22a, 0xac5d398a, 0xf597ec7c, 0x001e53c3, 0x683cbf78, 0xf4e1fba0,
11027 0xb95ae950, 0xee7ca65e, 0xf312f5bc, 0x9b278802, 0x7d7c91e7, 0xce96347e,
11028 0x52dc6991, 0xf43156f8, 0xd0316c4f, 0x0d13b2fe, 0x7cf147f6, 0x925b13eb,
11029 0x3dbbf0e2, 0xfccca377, 0xa4ad77a4, 0xcb79d577, 0xefd0561a, 0x45f5cc26,
11030 0xcc0f5039, 0x567de3dd, 0x4ddfa3ed, 0x4e50665b, 0xbf3ec88e, 0x1273f444,
11031 0x299b377e, 0x8199fe4f, 0x92a7f179, 0xb87075e6, 0x0358933e, 0x8f9b4ff6,
11032 0xe000780d, 0xb9b13338, 0x957e874a, 0xf489307c, 0x43322be7, 0x6258adbe,
11033 0x1787f3a0, 0xc46f27be, 0xd20a933e, 0xfa65bd39, 0x39b60f7d, 0x5d67e68a,
11034 0x6e3021c0, 0x9ea22fe9, 0x5ef2235f, 0x60f5ffd4, 0x9fc11adf, 0x259f47c8,
11035 0x01026730, 0x7f0ff3cb, 0x75449c3a, 0x7d3e209f, 0xffeeb8f9, 0x64c6bbd0,
11036 0x54fefd02, 0xfd27cbe5, 0xc91260f6, 0x4fde3855, 0xf2feb91a, 0x41481ca2,
11037 0x339419bd, 0x3cd5fdfe, 0x41d92383, 0x1a686b7a, 0x6b93adea, 0x6467940d,
11038 0xaf1c677a, 0x7c42bdcb, 0xa4e7beac, 0xf083195e, 0xa1ca6c9d, 0x59ef0cef,
11039 0x43fd932b, 0x7de3e3fe, 0x971fff9c, 0x7bbf18dd, 0xc637249b, 0x737ce1ef,
11040 0xf4e192df, 0x11b3047b, 0xea7a2327, 0xbc69b381, 0x17f6a10e, 0x07bfe4ed,
11041 0xe87686c0, 0x5d0e0da7, 0x9f7f0347, 0x4e7358bb, 0xdfdf4d79, 0x9c23c71d,
11042 0x17efefce, 0x9ce9df8f, 0x9f13223e, 0x3cdbee9d, 0xf9e8152c, 0xb0d76e85,
11043 0xf9ffa007, 0x7a27ef44, 0xfbb46fa4, 0x62ebc43e, 0xfc2cdadd, 0xedb3ba6e,
11044 0x866f47e3, 0xb2f4fee7, 0xbe6241c1, 0xc7f4892c, 0xb30bcda2, 0x21bbe9bf,
11045 0x787dfcc6, 0x2699d1de, 0x2b173e01, 0x9f30632d, 0x84b99f30, 0x51f8e23d,
11046 0x86bcf0b6, 0x73cf1d75, 0xbb145c7c, 0x79b4e306, 0x8f8c7961, 0x8d83f7c5,
11047 0x6fc69299, 0xf5c99838, 0xe71d3cd7, 0x38b7886f, 0xb1a631bf, 0x5edeaa03,
11048 0x220fbf8c, 0xaa80ed07, 0x33586bb7, 0xb3fd6b9d, 0xff34becc, 0xbf47c942,
11049 0x27875223, 0x2af8c354, 0x6b638f2b, 0x51f28c5e, 0xe580aa9c, 0x8e0ff10b,
11050 0xe7813ea1, 0x7e5f1916, 0x0177d90a, 0x8675f00b, 0xc193fb8d, 0xe9c81557,
11051 0xacaa7f69, 0x346c1b1b, 0xfb81c1bf, 0x79081719, 0x7c966dad, 0x25075e7e,
11052 0xcc5f3a3b, 0xd1d85f33, 0xc3d4fb70, 0xa3d9852e, 0x977661f9, 0x2ced6b35,
11053 0x79e74bc0, 0xc386f0ab, 0x25898ae9, 0xe66a2c3c, 0xdcab3efb, 0x08937dbe,
11054 0x1401c96e, 0x02cf01ed, 0x80951ae6, 0xc79178eb, 0x85f0e1e9, 0xbc07abaf,
11055 0x70e19d62, 0xd1ce3957, 0x5b35e5f7, 0xf857c224, 0x847a543a, 0x5d2a71fb,
11056 0xbf1cbcaa, 0xd1126d55, 0xff65d4f3, 0x50fed190, 0x0b586f95, 0x79e42ffc,
11057 0x5d608f95, 0x2dbf5093, 0x38fa0758, 0x2d3f27a7, 0xc8712d62, 0xdfcc7537,
11058 0xd3f72588, 0x473b96fe, 0x4e79e0e4, 0xa9dce987, 0x573f9b0a, 0xeca88097,
11059 0x96fcb47c, 0xe3879f20, 0xbdf44afb, 0x5131fc5a, 0x00e7a067, 0x905ff35f,
11060 0x909ffbe9, 0xf63e2271, 0x7b557c92, 0x3fac46bd, 0xb9f9eb57, 0xd3825772,
11061 0xcbbfe7a3, 0x05784574, 0xdc35af3e, 0x7f5a59d1, 0xe577e839, 0x5bd247c6,
11062 0x098f3aea, 0x7b45733d, 0xc5dc77af, 0x4927dec8, 0x4de9af98, 0x3b09577f,
11063 0x3eed1f3f, 0x7fac9fb4, 0x3c6bce95, 0x3a55eeb5, 0xf2f8d59f, 0xf0b7da7c,
11064 0x8f79fac9, 0x7c4fefe2, 0xd91e65b2, 0xab4f05f9, 0x0c6dde76, 0xd6ca1ff5,
11065 0x5fee7dcf, 0x345f6f90, 0x6ab95d53, 0x41c45b8f, 0x9c6157a0, 0x51eb9eb2,
11066 0xd5eb8eb6, 0x070f6805, 0x0ebc3d91, 0xe55fddc7, 0x3ff90ebe, 0xc9d93ae4,
11067 0x7fb9e7fb, 0xbde613b5, 0x8718a5ff, 0xf56c9697, 0xd5b4bcf3, 0xf6b0f68f,
11068 0xd38e0fde, 0x07c94bef, 0x6a81fbdf, 0x139e19ff, 0x42ce2ee5, 0xbf761339,
11069 0x6598de56, 0xec223b45, 0xdf1b3fc4, 0xc9be20f7, 0xfef8e2bf, 0xf9e389a8,
11070 0xef1cb5e3, 0x51fa5b8d, 0x5351fafc, 0x3eabf23f, 0xf84b92da, 0xf8035cae,
11071 0xd15abf26, 0x804d55fa, 0x101f8c6f, 0x3dd700df, 0x6f81147b, 0x1377c707,
11072 0xcb5b33c7, 0x781ecadb, 0xebf9d2f5, 0x947bfff7, 0xcf84fd03, 0x9ff27ecc,
11073 0xd32adb3e, 0xdfaa6959, 0x7f3dfaa5, 0xa2cfcd66, 0x7be2a67f, 0x3e4080e1,
11074 0xc78a97ea, 0x7887177f, 0x2795b85f, 0x9be07a4f, 0xbce85339, 0xbfefcbfd,
11075 0xce2d27ec, 0xbe93f50a, 0x98ea5d25, 0xd72bf68b, 0xf96639e1, 0xd5a2fb21,
11076 0xdf0b3fdf, 0x7cf0ad07, 0x98731465, 0x464f084c, 0xb9b8eff8, 0xfe8bee19,
11077 0xecdcf72a, 0xbb8e497b, 0x31c7bf34, 0x780df989, 0x916b019e, 0xed4bbf68,
11078 0x257125d2, 0xad2dcf0c, 0x67363827, 0x69df3b71, 0x3f22caee, 0xc714676d,
11079 0x359ba8fb, 0x07a4d1f1, 0x423ff11d, 0x3f20e03f, 0xd79278df, 0x49cef941,
11080 0xab5243c5, 0xff3ae842, 0xb8d73f02, 0x9cc482ea, 0xc09dfc76, 0x622fb4b1,
11081 0xda14f37e, 0x6d055007, 0x5ef8e859, 0x9cdbcfbe, 0xc7a2f3c5, 0x78054d71,
11082 0x1df8939e, 0x1a9e713c, 0x370171d5, 0x3a2ecdc7, 0x9278ef6f, 0xc8cfc1c9,
11083 0x07dfa78b, 0xc1e85bb8, 0xb47d9699, 0xf1e61c8f, 0x7b9e1b32, 0x0501aeff,
11084 0xf1d4c2ac, 0x73c68632, 0xbefe3f52, 0xff5b8749, 0xdf22ac1b, 0xbd92edbb,
11085 0x3a413c27, 0xf381cf6a, 0x8fce4744, 0xfdc59abc, 0xa4e9c929, 0xcc14443a,
11086 0xdfef0d1d, 0xebf0a59e, 0xdb3bff62, 0xed8cf400, 0x7a9c9e79, 0x39f9799d,
11087 0xf0a535b2, 0x67189bef, 0xb21bd424, 0x31afd34e, 0x9e87fbf2, 0x5d793d9d,
11088 0x30ef6306, 0xf43f7ac0, 0xff8f1953, 0x70fbc6e7, 0x3c64d7df, 0xad86ca6f,
11089 0x76eaf89e, 0x78eaf33d, 0x7ac164db, 0x6a673888, 0x1ddfc092, 0x0f1fccc5,
11090 0xa03fefbc, 0x2ef16f3d, 0x1d7fcebf, 0x9e3275e0, 0xe78f9767, 0x2b0629d6,
11091 0x2e55c7bc, 0x52bc6015, 0xc1dbf2b3, 0xc2ecf1db, 0x4246ebc9, 0x70e3a75f,
11092 0x29e780fe, 0x1efe6266, 0xcf5b30f0, 0x9c05c8f6, 0x8f1788de, 0x207da14d,
11093 0xda244b5d, 0xede6a2af, 0x090f7a55, 0x8e89ede6, 0x307c0533, 0x3e1c534f,
11094 0xaf4c8c6f, 0xb8d4b22f, 0xede285ba, 0x173e42c5, 0x45b972ab, 0x6c96972b,
11095 0x8ff44741, 0x45336f01, 0xf9a4eb0b, 0xd47bc46b, 0xd9cdd773, 0x36737e7c,
11096 0xf2ffe38f, 0x598fbe77, 0xaa8ef9f8, 0xf146d67c, 0x4ff7d5f9, 0xb6546d16,
11097 0xe155e68d, 0x7fd7cf09, 0xf91561ba, 0x677fd549, 0xdf443ebe, 0x324c5d50,
11098 0xea225576, 0x4999efa5, 0x5b1a66ee, 0x3d2deb72, 0x15e7a9c7, 0x8180b056,
11099 0xbe440fd7, 0xd1a3d84c, 0xbfce85b2, 0xeff890ac, 0xc4967674, 0xe720757a,
11100 0xbf7cccc7, 0x1ff079e7, 0xc0153df1, 0xef31f817, 0x27fbf8ac, 0x11583fa1,
11101 0x7b63d467, 0x73cfcccc, 0xb102c39e, 0xfd413939, 0xd32258db, 0xfbcc8739,
11102 0xafac64f4, 0x213ac2ad, 0xcce63fef, 0xe894aca0, 0xea36f73f, 0x811769a5,
11103 0x9befa80f, 0xa93884ec, 0xcfb8af73, 0x9df3d236, 0xf67e090f, 0x27fde26e,
11104 0x279bfbd5, 0xab9df3e3, 0xe4bffbd5, 0xf3a89ffd, 0x61e3fe8b, 0xdd8457f7,
11105 0xdfef19ff, 0x272fdcf4, 0x2d8fd17b, 0x715dace5, 0xcfbf4493, 0x1bd423f1,
11106 0x562b0fa0, 0x15cf09fa, 0x2dbc5dba, 0xd0dd7e65, 0xcaab8f2b, 0xed08fd76,
11107 0x327b1c95, 0x92f5ed16, 0x67f5271c, 0x6747ba66, 0x8a68bb43, 0xbac235e4,
11108 0xd91f11d9, 0xe8bd498f, 0xbd091fe5, 0xf9f0a55c, 0x3cc37c54, 0xfe8bb293,
11109 0x9cfe79fe, 0xbb9e63dd, 0x5d9e06ae, 0x66914f08, 0xc0d5f71e, 0x768e5d73,
11110 0xda1fd51e, 0x23f9d7d3, 0x2edc2b84, 0x23b1fe2e, 0xec53f31e, 0xe29df12d,
11111 0x42ac96ca, 0x2ff17f98, 0xa1556477, 0x82fc25ff, 0x768bb43a, 0xdb83173c,
11112 0x3fdbcfc5, 0xb6e5fbe4, 0x60c71bb5, 0x50da001d, 0x0bd358bb, 0xb56cde9c,
11113 0xaf38ffce, 0xb4f2fe1b, 0x58b9e91e, 0xd3c9f2d7, 0x926fe768, 0x59777e22,
11114 0xde3b9e2d, 0x3525efcb, 0xe03f7366, 0x87cefea5, 0xb20b6f10, 0xb291e919,
11115 0x79cf9155, 0xb1e85b7e, 0xe6ff610a, 0x29358b0d, 0x23a2e780, 0x0fb855ee,
11116 0x4e436aab, 0x978de601, 0x963e9667, 0xd6f98dfd, 0x6d6f9e2e, 0x0ad6f9e3,
11117 0x2829605b, 0xf666f671, 0x32998f5b, 0xa9fe0fc1, 0xb220672a, 0x94796cf0,
11118 0x79353fda, 0x0f9e48d4, 0xcfcbfec3, 0xe50c7f1d, 0x83c23f66, 0x83e1f5f9,
11119 0x743f51a3, 0xace8c4e4, 0x25fe47a0, 0x089bee63, 0xb7e1acc7, 0x929a7ed0,
11120 0x7301d8a8, 0xf89efe79, 0x5c325fe2, 0x38dd709b, 0x6e24f31e, 0x2ee93fa3,
11121 0x4dfb8758, 0xbab3f699, 0x91dc63f3, 0x2efff3ea, 0xb666f0f0, 0x3afdda95,
11122 0x0820b380, 0xf07efa87, 0x600697f7, 0xd32b93be, 0x50f7e086, 0x0e4a3227,
11123 0xdf051764, 0xbdc3227f, 0xdf53e11d, 0x06c7527f, 0x6df1c860, 0xd05578e1,
11124 0x0dd200f7, 0xe048d75a, 0xefb890b7, 0x9a3151f6, 0x7609b4fe, 0xe3cd0ce6,
11125 0xf4d74b4e, 0xd3f457a7, 0x72bbbf8c, 0xc4fee6a0, 0xfad0c0a8, 0x77b7bf10,
11126 0xf7cbc97f, 0x46c6c4ef, 0x3fbdfee3, 0x7df9fdb6, 0xcee9fdfc, 0xfa076417,
11127 0x6e770bb6, 0x168f1f7a, 0xb5f40f3e, 0xa1527e53, 0xf69fda7c, 0x839f8ccb,
11128 0xd687d4e1, 0xc0b0ce91, 0x60a52353, 0xeb6dfb7c, 0x7bad8b47, 0xae0577e8,
11129 0xf3e8dd55, 0x287f516c, 0x1f680560, 0x47bfd7cf, 0x0b3abd79, 0x1d99e75f,
11130 0x3c5b9cfc, 0xf012fae7, 0x20f86dfd, 0x40178bfa, 0x97fc83f1, 0x7aa09eb5,
11131 0xae6c9adb, 0x9632ebaf, 0xf64fd1e8, 0x65f68b40, 0x78ade80c, 0x3b409be0,
11132 0xf70dbc1b, 0x72c4e5bd, 0x54c2fdff, 0x8fef9bca, 0xfd9ff9e6, 0xfbf409c9,
11133 0xc69b8bc7, 0x0bbaf5d2, 0xdbff3431, 0xb5f68072, 0xa8935f79, 0x7d31314e,
11134 0xcf5c4ad6, 0xdf4401ff, 0x80006da0, 0x00008000, 0x00088b1f, 0x00000000,
11135 0x7dcdff00, 0xd554780b, 0x399ef0b5, 0x67091e67, 0x99212726, 0xe4c21024,
11136 0x4e010249, 0xaaf08042, 0x9e180903, 0x6831004e, 0x0cfde1d0, 0xaf4a8809,
11137 0x04819bf4, 0xa86c1808, 0x3bd15014, 0x6ad480a4, 0xa6a3ea6f, 0xd004c7d6,
11138 0xa0d2941b, 0xdef6b7fe, 0x22c01b5b, 0xda046a28, 0xfad2de9f, 0x3ef6b5af,
11139 0x82499cc9, 0xbf7b7b72, 0xdbe3ef9f, 0xb3ef6759, 0xd7bdeb1f, 0x6b4cfb5e,
11140 0x7eef2074, 0xff99b185, 0x1b297b72, 0x97dad8c6, 0x1e609e4c, 0x857bd2c0,
11141 0xd35ca0eb, 0xbeb19530, 0x5356b308, 0xd731631c, 0x046c61ef, 0x2c018cc1,
11142 0x64ec728d, 0x435a5031, 0xc3c64fd9, 0x3b43ab33, 0xeaac66ec, 0x37bd147a,
11143 0x3011d8bd, 0xdbbc7d43, 0xc648d8c4, 0xe953ed2c, 0xcbd7c9fd, 0xfc6bfea8,
11144 0xfd631b77, 0xaf54e9dc, 0x438496c3, 0xdb0522f2, 0xb4fda89b, 0xaca843eb,
11145 0xca873ebc, 0x147e7277, 0x84fac3ef, 0x17fa536b, 0x526f1c02, 0x64ac4a71,
11146 0x628d999c, 0xa33b7eec, 0x47ab577f, 0xaba530c7, 0x72d2c8df, 0xe81e625d,
11147 0x44dd76cf, 0x8f74c0e5, 0x6c604ee6, 0xd976a6d6, 0xec51eb8e, 0x8034e1ea,
11148 0xcbddf28b, 0x93debaf2, 0xbab7cd8e, 0x7bfbc287, 0xd03d58ce, 0xe2ca0dbf,
11149 0xc64afab0, 0xdd794d3c, 0x36e51bc7, 0xdb193ad3, 0x6c2ce54c, 0xcbb3ef07,
11150 0xef3865df, 0x6f3e557b, 0x912611b6, 0xb60658cc, 0xbf7ae84f, 0x60c1d00d,
11151 0x6d97815e, 0x77f0c3c1, 0xd4afba51, 0x4db4fd0d, 0x602fe564, 0x6a5b723f,
11152 0x371fe399, 0x38b799ff, 0xfe6271ff, 0x46d896bf, 0xb7d7efec, 0x81e6d6dd,
11153 0x3c3cb579, 0xeee48462, 0xb75ef7ea, 0x76abf795, 0xcf4060dc, 0xb8fa37aa,
11154 0x66fac277, 0xdc208f02, 0xd82dbaf1, 0x99cf4698, 0x5b4b1e29, 0xabea09a3,
11155 0x5ed91d9c, 0xcdf8bf18, 0x6ff210a8, 0x32519bcb, 0x9f7e7183, 0xe917bbe9,
11156 0xa0e6fc58, 0x26139312, 0x464d9af9, 0xd036583e, 0xef3e1f73, 0xf1bdbe6d,
11157 0xd69c6009, 0x535fc911, 0x18814cca, 0x1d5f6fe0, 0x82859397, 0xef5d173f,
11158 0xc84fb043, 0xc4ead5cf, 0xabb74829, 0xb0d2609b, 0x4c9b458e, 0x75825f43,
11159 0xcb43b731, 0xeccc3c02, 0x730b60bf, 0x69995ca2, 0xc48733bd, 0xe9a06b06,
11160 0x06b1eb9a, 0x9ebcabf9, 0xbdaffd46, 0xeb9e97de, 0xc848b672, 0x19f90d87,
11161 0x9f8225e0, 0x197e45ef, 0x1b8725d3, 0xe28f7dd3, 0x80d667fa, 0xbe78c3bc,
11162 0x2885c92d, 0x62fc5d47, 0x80af9155, 0x8596925f, 0xcb4d4dc9, 0xf42a987c,
11163 0x7e25ef1f, 0x71650259, 0xc152fd58, 0x7b789107, 0x65f916ec, 0x48bf68b3,
11164 0x01996509, 0x28ea960f, 0xe7cc0b6d, 0x0a7bbc4a, 0x0efd65e2, 0x16f5bf8e,
11165 0xe603b16f, 0x9371febb, 0x8b619406, 0xa8ec3947, 0x587d4687, 0xf185f56d,
11166 0xc3ebfced, 0x30f01b98, 0x95267ae7, 0x83be01fe, 0xd785feb8, 0x0d3a09e7,
11167 0x8bb992a3, 0xd8c5cccc, 0x1baba406, 0xe9c45427, 0xad77e62c, 0x43e2747a,
11168 0x53b5fe30, 0x88bfaa16, 0xa9802d78, 0xe34f027a, 0x9b412cbc, 0x75e61076,
11169 0x2a02c2d1, 0x7ef169d0, 0xdfa00589, 0x46fa5025, 0xd83d52d0, 0x1481f6ce,
11170 0xb176c16c, 0x805b13cc, 0xe6f584f8, 0x86be31f0, 0x6d4c97ff, 0xfd410fd9,
11171 0x961b33e7, 0x81e03399, 0x86412a74, 0x82fe7e75, 0xbe7824c4, 0x2e5bdd72,
11172 0x94ab1e58, 0x50aaa60e, 0xcc14c1bf, 0x7be280b6, 0x86bdf646, 0xbbd3e07a,
11173 0x08adfe9b, 0xf0dc7dda, 0xaae913a2, 0x0e49b5e3, 0x4d3f6165, 0xcc00cf80,
11174 0x2a5ea9bd, 0x6c342a0d, 0x5da1b29f, 0x73f3adfc, 0xbaaf9f24, 0xba78419e,
11175 0xfa1b6d5a, 0xf031f212, 0xf5d73e2d, 0xae3aeaf1, 0xbefd75d7, 0xcebff056,
11176 0xd73295d7, 0x4c4a955b, 0x6e169030, 0x13bcca6f, 0x4c72ef91, 0xb70b165a,
11177 0x8e8f8d37, 0x32f83945, 0x5d61ab5e, 0x839742f6, 0x8049fc57, 0xa47b2ebc,
11178 0xc7ae81cb, 0xf3aebd75, 0x26af6ebd, 0x2f2fe4fd, 0x79fc3bfe, 0x81d7cd32,
11179 0xe64d307c, 0xec9a6b76, 0x1c9a3e20, 0xff23265f, 0x79fd7b7c, 0xb3cfe856,
11180 0xb6b9fd06, 0xc7f9fd17, 0xf387945b, 0xda967f42, 0x3cde7dd8, 0x3b67dfae,
11181 0x4a2bfaba, 0x834b649f, 0x1334947e, 0xcd47fbb5, 0xf3e3495b, 0xfef3b6f8,
11182 0x6fceb12f, 0xd303fbd2, 0xa46fd4ac, 0x1fd0679e, 0x5f2ff9ea, 0x1da20dcf,
11183 0x5d8188f8, 0x5af7bb40, 0x6161f71f, 0x444ec807, 0x666f04c7, 0xb9927e07,
11184 0xa7e22078, 0x4ee03b07, 0x80ec3bfb, 0xbcba57ce, 0xcba1f2e8, 0xe8fca443,
11185 0x11fd30f2, 0xa421e62d, 0x30e6200f, 0x781c8fca, 0xe951d70e, 0x728f93ee,
11186 0xf811cba9, 0xdd672461, 0x9b9083ec, 0xda31392e, 0x742e5d0b, 0xa6e5d139,
11187 0x52c5c852, 0x3cba1721, 0x1e9a971c, 0x3def0b1b, 0x432be697, 0xb1f2e87c,
11188 0xbb4885e6, 0x313f2bd0, 0xf1a5a7e4, 0xa9f90cd5, 0x7e70ca12, 0x4fc2f5b2,
11189 0x9f916ef3, 0x9dbed24a, 0x8d32b11f, 0x40ff11fb, 0xd6995a7e, 0x0ab15fb3,
11190 0xca7fecf9, 0xfd5ab8af, 0xcc37429b, 0xe8216ae7, 0x7e2eb4d9, 0xe32efe9b,
11191 0xf806437e, 0x46b450d9, 0x5ab675f3, 0xb06b0407, 0x1aacd7dd, 0x01fba8f1,
11192 0x7dee914b, 0x27f4f8bb, 0xfe71ff60, 0xc15bfd3a, 0xedf75fff, 0xd9d11df4,
11193 0xf566df16, 0xdbbd21e4, 0x37bff60c, 0x5bb1f17f, 0x6fe6f3a4, 0x4243e749,
11194 0xfa0ffc6f, 0xd17a878b, 0x1eff8713, 0x862cceba, 0xfc21fb3f, 0x3c67af7b,
11195 0x02fbe7d0, 0xa2f39c0e, 0xd22bccbc, 0x3c1bdbeb, 0xe01fa899, 0x8234b1cf,
11196 0x0f09d987, 0x56db3e02, 0xfe9cf302, 0x007d6758, 0x8f8f27eb, 0x8f33ef11,
11197 0x3fb57589, 0x5b51f691, 0xd60bda3d, 0xaf8dedc0, 0x0d0ef65d, 0x76010b83,
11198 0x1145c184, 0xdede01f0, 0x9533b729, 0x972084fc, 0x54dfe82b, 0xfd15f340,
11199 0x9e65fe09, 0xcf015713, 0xdb1354b3, 0x8aaa7409, 0x55d6f83f, 0x26cd6bd4,
11200 0xe1877266, 0xebc97021, 0xf6fd0149, 0x9fc0499a, 0x37c079b7, 0x0e25fbb8,
11201 0xabf0767f, 0xfa2c8086, 0x8d6c7f05, 0xc9a5b740, 0xbfa091e4, 0x60a64535,
11202 0x7c775a7a, 0x67c9d67f, 0x54c07cfa, 0xd667df1a, 0x1f7b5bf8, 0xa7ef4de9,
11203 0xdb21fbd3, 0xd77f8c2d, 0xf609e678, 0xd29b0fe0, 0x292c5db9, 0x3eb1e98c,
11204 0xf8e25d2a, 0x3eb001bf, 0xd39a3c3e, 0x91e5f7c4, 0xf9d363ed, 0xb3666db8,
11205 0x3763a7c0, 0x559b59f2, 0x1bb2b7c7, 0xb1993df1, 0xbe413e4e, 0x4e09f181,
11206 0xeaca5469, 0x4f5cbe64, 0xb66ebe04, 0x74d32fde, 0x5f0ba63f, 0xd97a0881,
11207 0xabef826e, 0x6ddbe03d, 0x33743f7c, 0xdbb9fd7a, 0x576f82fb, 0x31ec7ce8,
11208 0xec8c7bf0, 0x898cfe25, 0xe001a937, 0xa8deb5c7, 0x742fdc7a, 0x195267c9,
11209 0x88ca2de1, 0x4bf92ea7, 0xc8512b2e, 0xfdf5123f, 0x7afca377, 0xb9ed9dcd,
11210 0x0d7cea3c, 0x5e00e7ef, 0xf7c695d1, 0xdbf7a547, 0xbe23c81d, 0xe5827aa0,
11211 0xca4779b0, 0x3c045363, 0x857e423e, 0x40fe91fc, 0xca78007b, 0x7f16fd42,
11212 0xe30eead6, 0x7f053b93, 0xe5626e7c, 0x26db4fa8, 0x2db23f71, 0xa40f979d,
11213 0x02ccb8f3, 0x754b97c1, 0xc30e8a7e, 0x427f9183, 0x5b095fb8, 0x7e69e137,
11214 0x63cf2ebc, 0xbac066cb, 0x7d78e2da, 0xdda8e355, 0x382e9481, 0x8d75bfb2,
11215 0x2f10cb63, 0x8a07fd9d, 0x997da0ce, 0x40f6f02f, 0x813398e3, 0x1767413c,
11216 0x7fda19d9, 0x50047f01, 0x7f22541f, 0xc7f3ba98, 0xfc6ef484, 0xdf788819,
11217 0xfbc9b963, 0xf7dfddc5, 0x2ccfbc44, 0xbef2b7f1, 0x088cdba0, 0xd04696ba,
11218 0xae0224b5, 0x41a0e1d0, 0x797aeaff, 0xadeef351, 0xeac7982e, 0x5967a0a3,
11219 0x2d4f3f38, 0xad5fb943, 0xed3bfcea, 0x176bf20c, 0x3c274f3f, 0xf9d26ecf,
11220 0xd46ec675, 0x87a865c3, 0x73c176c7, 0x3c110f50, 0x1313ccb3, 0xed66af6e,
11221 0x57757b46, 0x0efede9d, 0xad777f6a, 0xea979fde, 0xcf423a75, 0x42d74465,
11222 0x3ecd5edd, 0x5eabf583, 0x4d1fefe3, 0x9026739f, 0x68791379, 0x81cbc088,
11223 0xd1103808, 0xd837cf7e, 0xf788dab7, 0xd7d44537, 0x23fbc047, 0xfbe33ae0,
11224 0x4898970b, 0x3f02170e, 0xe5222120, 0x9a3f9232, 0x9cfd3bd3, 0x526e7b4e,
11225 0xc833bfc8, 0x0e1af4d5, 0x95f74b1f, 0x706129d5, 0x2e32c2e3, 0xf01a3017,
11226 0x7ff185a5, 0x120373a0, 0x17a583f0, 0x1bd4d9bd, 0xda44e65f, 0x7bff5e7b,
11227 0xfd1933fc, 0x4bf06665, 0xb8464b8e, 0x0ef31245, 0x90d99d54, 0x78750f87,
11228 0xa7ee196d, 0xae33efa7, 0xa2b3f60b, 0x49594d7e, 0xd6c45fb8, 0xd6c27994,
11229 0xf29fb7a9, 0x1c25afd7, 0xd5c6c3ef, 0xbea08765, 0xab285262, 0x5e38cb1a,
11230 0xd094bd82, 0xf889575e, 0x25d794cd, 0x8acbda2f, 0xfad650e8, 0x35883f70,
11231 0x5b3ae365, 0x3e88961e, 0x0fa01a81, 0x732169e0, 0x2eced15b, 0x832b1e66,
11232 0x4c4b5cad, 0xf023c6cc, 0xa587f1de, 0x3fa7688d, 0x85d7d8da, 0x19d1a1fb,
11233 0x3c717f7c, 0x296ba066, 0xee7d2dc0, 0xb2db7d23, 0xc795327d, 0x0eb6cf24,
11234 0xdbffb195, 0x929970f8, 0x8431f58b, 0x0fe9aba7, 0xf9066d95, 0x9bba53f8,
11235 0x538beaf0, 0x6fe8cd5d, 0x8c30b4ef, 0x51a63397, 0x2ee1691c, 0x9c4efe5b,
11236 0x2e21e6cf, 0xfd173ff4, 0x324a6cb0, 0xd5b45bb4, 0xd51fa1a2, 0x7153566e,
11237 0x939dbe7e, 0xa4bf58ad, 0xdb819456, 0x6ff37ca9, 0x4271aa3f, 0x4ca78efb,
11238 0x9fb4235a, 0xdde9ad70, 0xaf2f0061, 0x4490d0cb, 0x33375c6f, 0xb739c615,
11239 0x0250507f, 0x551f3cbe, 0xde2cf6fd, 0xe5fb619e, 0x67a7dc37, 0x497b6215,
11240 0x2fed02dd, 0x9ff473c0, 0x1a90ec2f, 0xa72f384d, 0x4b04da23, 0x4657f0ba,
11241 0x5b0b9cf1, 0xcf8c416d, 0xf77c539d, 0xf671c7ee, 0x67d3d05b, 0xa76e4c17,
11242 0x9f10f009, 0x292cb3b1, 0x04db9f19, 0x2ec6773d, 0x685f3904, 0xb21fe4ee,
11243 0x3962cb27, 0x1da3ff1c, 0x1d618765, 0x441f1e17, 0x195dabf1, 0xc00c849e,
11244 0x1e991df7, 0xa3e79617, 0xf37addb8, 0xe87dd26f, 0xf2f2ffc7, 0x97f21722,
11245 0xd3cb833b, 0xb917d71b, 0x55f98516, 0x89973ecb, 0xbab4de0f, 0xdf7ce037,
11246 0xc2601e8c, 0x41f0367d, 0x2f938c5f, 0xe016fb11, 0xf62f8de7, 0x97fd5fe0,
11247 0x1e5ac7f0, 0x36ef1849, 0xd27ef5f0, 0x00dfb49f, 0x87e33f38, 0xc7c003bb,
11248 0xb236db1f, 0x9b8c28f3, 0x75dc52fa, 0xe07a1309, 0xee20a8b9, 0x535258ab,
11249 0xa6fc7876, 0xfb450e53, 0x841c05df, 0x7b41dfd7, 0x2efdf7dc, 0xf08e1ff0,
11250 0xfdbd0bf3, 0x8023a772, 0x0e27c5ce, 0xf8f48c87, 0xf85ff648, 0xecb7bc2e,
11251 0x81d90b29, 0x6c254f65, 0x8171c0ea, 0x16ae306f, 0x867f2eb9, 0xabd5d685,
11252 0x6523b25c, 0xfbe12925, 0xbfa4c395, 0xe9cb937b, 0x0ecb8719, 0x972ef5e5,
11253 0x9fae55cb, 0xf1653ca6, 0x1f2d3ca2, 0x70d990e9, 0xf53d26c6, 0xcfc461d6,
11254 0x055175f2, 0xf2f89836, 0xaf446ca7, 0xa0238776, 0xe9cfbd42, 0x9ca16390,
11255 0xd6f5c19f, 0x3f2e0ca6, 0xed9312c5, 0x62d65405, 0xcc0af5bc, 0x97c02fa7,
11256 0x77b63e36, 0x29f38c34, 0x0d1bce0b, 0xe1e2bbf8, 0x25e57a7c, 0x4c8ee289,
11257 0x4133c8f6, 0x5c60ae5f, 0x7c9e544f, 0xfe113ad1, 0x5ff562ac, 0x5c1fb049,
11258 0x067cbd51, 0x06570bee, 0xc5dae72d, 0xb16bfc5e, 0x55b3d45c, 0x5bd811fc,
11259 0xfefebd63, 0xfa4ed61a, 0xa229b2a3, 0x4ff6fabe, 0xd5537e30, 0x3ebe7c6c,
11260 0xa17f11c3, 0x7258c30f, 0x5d8a6001, 0x3364b6a9, 0x0572ea58, 0x5dd60ce4,
11261 0xf344c07c, 0x0a51be5f, 0xc5fe60da, 0xf8dc797d, 0xc1f03f63, 0x407f5a20,
11262 0x1ef97805, 0x33967f6e, 0x7f0ed053, 0x1d607ede, 0x0a2f31c5, 0xc4d0b37d,
11263 0xe7e7c8bc, 0xdc54b4a3, 0x2a7b2fef, 0xfcbcf08a, 0xf6ff95e9, 0xbed7bc38,
11264 0xf87c6679, 0xf90ebafe, 0xd999e383, 0xf9fabae3, 0x52f7f364, 0xff8a0e51,
11265 0xb0c9f619, 0xecb1e5de, 0x90d3f3a7, 0x6ea9c96e, 0xf2ddaba5, 0xf3670f2d,
11266 0x86cfb076, 0x21dc2f75, 0xcbd83ad1, 0x2087b236, 0x3e386af3, 0xb49ed497,
11267 0x633db95a, 0xd9f84baa, 0xf5e7d46e, 0x7fbc126d, 0x8525ea0e, 0x0f6817f0,
11268 0x87df978b, 0x3e93257d, 0x2afae1f1, 0x66fba6cc, 0x561d3f53, 0x3317ef94,
11269 0xd9f45c78, 0x2ee7ee0c, 0xa5eed54c, 0x36a3f438, 0xef1a4b6d, 0xe6251a47,
11270 0x4abcfb01, 0x3a32db73, 0x8db9fcc7, 0xb5552be2, 0x27289e51, 0x2f3c4bed,
11271 0x3255bf40, 0xd871ad93, 0x1ae75f2f, 0xf01fd737, 0xcf1943fc, 0x3f5c1c67,
11272 0xbe02c656, 0x6638ce15, 0xfc4bffe8, 0x97f7832b, 0xfdebac3c, 0x5d4df1ce,
11273 0x10c3b9f5, 0x95e77d5f, 0x979e3ce3, 0x19017e48, 0x9fa1168f, 0x0234bcf7,
11274 0x770bd7f7, 0xfa829f1c, 0xf2cff576, 0xe1757c55, 0x7b27df4f, 0xb9d05ab1,
11275 0xb47dfd1d, 0x0cff001f, 0x7e4253ca, 0x0f8f127c, 0xd0f8129d, 0x57d7ade9,
11276 0x38f0b0ee, 0x5475e83d, 0x7f9b9524, 0x3a56fd43, 0x6fa85cda, 0x8cb65f2b,
11277 0x6bfcbd42, 0x5fb43f9c, 0xf8c079b4, 0x167f810f, 0xb4546259, 0x33026b4f,
11278 0x69af08ad, 0xf5dc1130, 0xf22a425e, 0xafb567e3, 0xce4f9138, 0xd0b28547,
11279 0x8bac750e, 0x01711ad2, 0x7dcf8f2a, 0x88d59b56, 0x6a259c71, 0xf504c39b,
11280 0xc464364b, 0x48febea1, 0xfeb1590d, 0x3334a6a3, 0x1d551ec2, 0x1e47b08f,
11281 0xa067f04e, 0xff049aba, 0x6b59bea0, 0xf35cf4e2, 0x3a6b71dc, 0xac55778c,
11282 0xdfe7f3f7, 0x4f78c6cf, 0x365b6a65, 0x77a011da, 0xf3c47f76, 0xc3b226b3,
11283 0x3c939f6b, 0xe8bac351, 0x0de916bd, 0xd04ab5f2, 0xaf4bed79, 0xbf7c843c,
11284 0xd05de916, 0x6f805f9d, 0x17f3d04f, 0xfc614e0e, 0x17c813fd, 0xb802ddba,
11285 0x377182d6, 0x09af872b, 0x25e7803e, 0x8f2079fc, 0x11e826f4, 0xf92337f4,
11286 0xc6fa37bd, 0xb7fb7266, 0xf48db368, 0xe7266c6b, 0x2f1df6fb, 0x9f7e913b,
11287 0x6dfc7f3f, 0x7ca94f3c, 0xbbb2ac01, 0xf817be07, 0x3bf5c2a8, 0x4fe4fe69,
11288 0x9d7ae154, 0xe4efeb5d, 0x556f2173, 0x5f4faf8c, 0xd62c956f, 0xf78bd7af,
11289 0xbc8532e3, 0x97af8130, 0x12f97106, 0x8af284f2, 0x3ebe997e, 0x5f7f1c5f,
11290 0x4ca2cfe7, 0x62699fce, 0x726d4c9d, 0xbe907e22, 0x7f8067a8, 0x4251d63c,
11291 0xcf93406f, 0x0ff3067f, 0xff3e97a3, 0xd00f3152, 0xb8d89e6b, 0x9bb63a2e,
11292 0xce9e8ad9, 0x3933f32f, 0x9add9cdf, 0xf80cda98, 0x59f60cfb, 0xfc006794,
11293 0xa78d872a, 0x5e3e8df3, 0xa6ca4ff1, 0xffa1bae1, 0x8faff610, 0x8fa051fb,
11294 0xc47cfd8c, 0xf3e87cb8, 0xb8b2e5d7, 0x7cb4c166, 0xdcfbb627, 0xeb879191,
11295 0x6697e3e6, 0x07bef4aa, 0xdf7803fd, 0x38a26cd3, 0xafb159f5, 0x15f5bb3f,
11296 0x2ebca2e7, 0xde229f7e, 0xabb27fc3, 0xfe753cfb, 0x9a67e30b, 0xbbf6f167,
11297 0xcfac21a6, 0x752f9237, 0xc9fce9bc, 0xdf902536, 0x55a7c912, 0x38ad6729,
11298 0xdd73e45e, 0x718f397f, 0x5fff9416, 0xff248298, 0x6644ecb5, 0x7f865d98,
11299 0x65d51b0a, 0xb3af361f, 0x51cb7b51, 0xbd75076e, 0xaaebdbaf, 0xc425cf78,
11300 0x79328ff7, 0xf56ac91e, 0xf42736c4, 0x36e3e633, 0xfdd60f3a, 0x42d709c5,
11301 0x95c60c52, 0x082b4a5e, 0x2e6b77b7, 0xadfe209f, 0x70db6d64, 0xc770b3ff,
11302 0x234733fb, 0x42d8fe9f, 0xb70b2fe7, 0x1fa2b64e, 0xe2f0f2be, 0x73ff4851,
11303 0x5d9edc75, 0x04791daa, 0x7573e8fd, 0xe716b98f, 0x53c57be1, 0x85f3c2c6,
11304 0xbe89f3bb, 0x66daa3e7, 0x80f1dc22, 0xbde11ac4, 0x6e478771, 0x71e01bba,
11305 0xb8b1818e, 0x490e8fce, 0xf8c36325, 0x37530961, 0x9b7e8ddd, 0x7ca2a31c,
11306 0x5af4247c, 0x6bd3858d, 0xdaffe097, 0x79cb92ce, 0x364d4d71, 0x1c77979e,
11307 0xf80a7d04, 0x9bbab0a9, 0xebee3842, 0xa80fb489, 0x524b6d82, 0x935b9d1c,
11308 0xcac2b4df, 0xf405c9ec, 0xcf0c9edc, 0x1eda5a4f, 0x7c9cf5c0, 0x19bf91c0,
11309 0x18dd2b71, 0xbbfb88b5, 0xe7e03724, 0xbe3af8d2, 0x0bd479f4, 0x4fec8b3e,
11310 0xfd15bf7f, 0x627fd47c, 0x7f6a97fe, 0xd6ed0f3c, 0x7159a3a5, 0x5e4ffeb8,
11311 0x3f43aa8f, 0xd70b13e7, 0xe0ff7a67, 0xee1c7d7f, 0x65bf8127, 0x32bfc180,
11312 0x1f67c0c0, 0x2db5fd1b, 0x33a7af34, 0xce95fe8d, 0xb2eb15af, 0x04f3c262,
11313 0x99e3f9ba, 0x744796b7, 0x02880fd9, 0x318c5d16, 0xf6ef8c0c, 0x6d8bebf9,
11314 0xd8378fe8, 0xf3ac1b54, 0x3c77e463, 0xe2597a6f, 0xe73b00fb, 0x1e5f8fff,
11315 0xdefdc411, 0xf0e4ffb2, 0x105326b2, 0xec4ea553, 0xfb612ede, 0x25ffe0a5,
11316 0xdbfcc29a, 0x01e7bb3d, 0x9a2bb3db, 0xb4325b6f, 0xe79472bf, 0x12b5403f,
11317 0x9dbed7e1, 0xf7dffeec, 0xc178f567, 0x6bbc74af, 0xebbc434c, 0x39f7d6f8,
11318 0x145f026f, 0xefe17415, 0xf20aff0b, 0x7dfb2f67, 0x3a697e54, 0xe438e8fb,
11319 0x868c4767, 0xe6cbf372, 0x48fea4c7, 0x6ff297f7, 0xac757ee0, 0xfca2a312,
11320 0x48dfe17e, 0xfd978c87, 0x74ea54d5, 0x1365e3d7, 0xf7a16a5e, 0xf11e68be,
11321 0xef7838da, 0xeb86250d, 0xf7cf0f6f, 0x646fa488, 0xebfdc7de, 0x73e22746,
11322 0x7e9f5d7d, 0x9f59d397, 0x1747a7f7, 0x2d5d713b, 0x6d7df64f, 0x4fb7d20c,
11323 0xdafe8a8c, 0x71f79172, 0x13d73f61, 0x4731ed17, 0x2f9d0066, 0x62e3981e,
11324 0xb69737a0, 0xcf879dcc, 0x526ebd97, 0x5ed75fd1, 0xfee2732f, 0xbb720fea,
11325 0xde12c553, 0xe47ce10b, 0x697a84a0, 0x839b296c, 0x6486c7ed, 0xc67e86e6,
11326 0x32fce0cc, 0xc41cb2e6, 0xe0cf9f83, 0x6e33c539, 0x033c5344, 0xbcc5f5fe,
11327 0xe0bfa58e, 0xef1d1071, 0x9c6c7efa, 0x1030f758, 0xf177e243, 0x3f88b8bc,
11328 0x8bc0e4ff, 0x4bbfb0b3, 0xce2a2c87, 0x16438bfb, 0xec157fea, 0xde30cca3,
11329 0x5f7ca3c5, 0x1a547082, 0x7fdf33ca, 0xfbe26aac, 0x1675ca8f, 0x3ba6358f,
11330 0xb587165f, 0x3c1efdc3, 0x2bb8e373, 0xfcea1f05, 0xd7c3caba, 0x1cec0ab7,
11331 0xf89bf7ae, 0x6d359637, 0xc6f5bc43, 0x7f96dfc7, 0xfa8cb333, 0x7b6f93a2,
11332 0x578117e3, 0x5be47f94, 0xed562f9d, 0x71ece7e7, 0x9113f94d, 0xd13e74ff,
11333 0x12604bf5, 0x5a7b41cb, 0x98396563, 0x47301397, 0xca17a86b, 0xed05b714,
11334 0xf6f89cc0, 0x23cf4412, 0x4abf5c59, 0x198f66c5, 0x8d8d51ed, 0x78b747f4,
11335 0xc7d71677, 0x283e6421, 0x7952ccef, 0xa6ab25be, 0x825e857d, 0xed0032e3,
11336 0xb89f5976, 0x49a1ba3f, 0xd9c6e1e9, 0xd975f032, 0x3207b8b8, 0x87bcc634,
11337 0x4478728f, 0xd40b48dc, 0xb333d2cb, 0xccae004b, 0x0ac94cf2, 0xe1d2f7eb,
11338 0x1eb801c4, 0x9f153e78, 0x37de28ff, 0xea246b23, 0xf9f4857f, 0x618ea697,
11339 0xdabad31b, 0xf1dd799f, 0x5ddd2fd1, 0xa585bb70, 0xeb08796a, 0x9ee5e5f3,
11340 0xec1ccf2c, 0x22f9f227, 0xde52b6c6, 0x3f5fe05c, 0xfe04ff44, 0x8f40ed79,
11341 0x2d5f043b, 0xa4212bb2, 0x5cb3ab33, 0xc037f4ee, 0x8c5a6015, 0x259b748c,
11342 0x390ee4f8, 0xe7ef82d4, 0x82f55ab2, 0x03a25c9d, 0x5dedf75f, 0xd80603af,
11343 0xe03fbd05, 0xb02d2f87, 0x136be03e, 0x1046dfb0, 0xb120131d, 0xe998f402,
11344 0x33fd7fb5, 0x60135bf6, 0xe78451ed, 0x10c2f50a, 0xccface0c, 0xd959435f,
11345 0xe30c39c7, 0x1c579e1d, 0xb8e80521, 0xc43ef9fe, 0x1f852bff, 0xc4457cc3,
11346 0xbe541bcf, 0x4b1be61e, 0xe080f6fc, 0xacfc4fb7, 0xf044133a, 0x0bec7673,
11347 0x70f1e619, 0xc461ef94, 0xa9f31afb, 0x946ef5d4, 0xfa271ad7, 0x54ff9f19,
11348 0xac3550d2, 0x3b24fe11, 0x5ee42094, 0xf506dd0a, 0x8db969ad, 0x0ab66f68,
11349 0xc69cb97e, 0xd81c3f68, 0x3fbca36c, 0xea78e376, 0xa69700c3, 0x3ee1aedf,
11350 0xb6cff2f3, 0x3a052e67, 0x38bd40d9, 0xa1539d61, 0xb75822cf, 0xce896005,
11351 0x4f448381, 0xe1380fa8, 0xc7b4b6f9, 0x319f3952, 0x4eb5ca2f, 0xddef1d1f,
11352 0xa34301e8, 0x33b669df, 0x732bee0b, 0xe51501d9, 0x27cba74f, 0xe01bc076,
11353 0xfe6e327b, 0x7fac1f41, 0xeb7ffb99, 0xa613ac4d, 0xfb374eb8, 0x9ff916f7,
11354 0x83016e20, 0xf8b0397e, 0xa2c3d9db, 0xe21c5683, 0x81e2ed96, 0xcaf51ee2,
11355 0x257ae8bf, 0x1f93e59f, 0xf1844b82, 0x93368b96, 0x8cb70aa5, 0x6bb049eb,
11356 0x9feb17c8, 0xc3bb20ca, 0x8590fc66, 0xfa0763b7, 0x4b6cbf12, 0x2b0e8893,
11357 0xd7944d9b, 0x3fb9b338, 0x8cd54373, 0x3a54bee6, 0xf3d327af, 0x2dde474b,
11358 0xd3877ae4, 0x8933e669, 0xe88f2893, 0xea544199, 0xf82f58f3, 0x15f3c74e,
11359 0x1cb3c72f, 0x1e37ddc8, 0x2d5a13cf, 0x3f26e82c, 0x35cfd784, 0xb4afde11,
11360 0x7f91979e, 0xb1304ee6, 0xd14b00be, 0x496dcf9c, 0x01eee666, 0x9f4136bf,
11361 0x73347728, 0x6a0bed87, 0xf88d9ca2, 0xda780b1e, 0x97701f70, 0x2727d768,
11362 0xa74ed0ce, 0x8e813ce7, 0x331594bb, 0x9ddb1d70, 0xbf915a53, 0xc33f5a1c,
11363 0xb14936b8, 0xabcc1f20, 0xee63d230, 0x196c235c, 0x5be915ff, 0x73e378cb,
11364 0x5f08c79b, 0xcb98e9d4, 0x18e9c372, 0xfa0f3f86, 0x363c57e1, 0xdee63f8e,
11365 0x79e01e37, 0x7cc3f861, 0x32292b96, 0x147b6fe1, 0xade017c7, 0xa63cf911,
11366 0x58b788c8, 0x7d4f118f, 0x48f88d4b, 0x9bd71af0, 0xa86e9e58, 0x360df64f,
11367 0x515ff7d4, 0x54078060, 0x1fb4358f, 0x019271b8, 0x334c0b4e, 0x9ba8cfb4,
11368 0x1ab3806d, 0x1fb436ee, 0xa1917fb4, 0xcab8373e, 0xe8e43f50, 0xb43c037a,
11369 0xed0c9fe9, 0x316f3787, 0x7687e7d4, 0xb447ea1a, 0x8f00c0fe, 0xd0c27b6c,
11370 0x8d87f47e, 0xed31fa86, 0xc7ea1acf, 0x00c17c5d, 0xd578e84f, 0xebb6fed0,
11371 0x44f00cc7, 0x7da1aef6, 0x037dfdb1, 0x0ffd593c, 0x93dbfb43, 0xa7ea1bce,
11372 0xd4333fba, 0x6ab9cf4f, 0x7f6a6780, 0xb6afb431, 0xa36546fa, 0x265d2aff,
11373 0xc059aab9, 0xeb4aeae5, 0x71ca3b1c, 0xdff03651, 0x7fc9d610, 0xd29ed0e3,
11374 0x62a5857e, 0x34b264fc, 0xd9f2443e, 0xdf70d26c, 0xe4af6911, 0x8c1ebccf,
11375 0x4c57b1ab, 0x06234f74, 0x361c8ecc, 0x0ec7ac7e, 0xb82ec41b, 0x806aa96f,
11376 0x8649bc13, 0x6ee589f6, 0x2fb27d43, 0x7fdf50c7, 0x07806685, 0xda191754,
11377 0x31e8dc0f, 0x528169c0, 0x3a8cfb43, 0x6ace01af, 0x1fb43728, 0xa867dfb4,
11378 0x30ae0dcf, 0x5a390fd4, 0x3687806d, 0x1fb4346d, 0xd4301cde, 0x0cea87e7,
11379 0x1b5a23f5, 0xb6c8f00c, 0xa3f686fd, 0xea1a0c3f, 0x351fb4c7, 0xd8bb8fd4,
11380 0x74278064, 0xdfda1b34, 0x80643d76, 0x8693b227, 0x33f6c5f6, 0xfab27806,
11381 0xdbfb435b, 0xea1ace93, 0x192fbaa7, 0x64ff75ea, 0xc657ce7a, 0x995fc2e7,
11382 0xf0d9fda9, 0x8792607e, 0x5e047f21, 0x6e356930, 0xa766f6c6, 0xde817f13,
11383 0xd0928f6e, 0x3e52f1bf, 0xf4261c52, 0x04c65f01, 0xe857c44c, 0x5c5057ea,
11384 0xafe29e28, 0x98dc5a64, 0x1f760377, 0xb4e67fe3, 0xfb77f434, 0x295df974,
11385 0xf6f88f5f, 0x6cd1d77e, 0xdb6bf646, 0xa7bca944, 0xd9a3c33c, 0xebf20e3c,
11386 0xd953df6c, 0xf8bfb809, 0xbbf414d9, 0x36c0b257, 0x2964e79c, 0xde1da62f,
11387 0x8c651d3b, 0x54e5e863, 0x6c2de03b, 0x1aa3273e, 0xb26e0a52, 0xbf6a9fdf,
11388 0xfb3bed4c, 0x130df115, 0x587d7fac, 0xbec28fff, 0xadbf0640, 0x05720fc1,
11389 0xfc0fecbe, 0xfc7bc12a, 0xf5ef0449, 0xefdca9bb, 0x09f2a1cf, 0x07f546bf,
11390 0x3f0445fc, 0x1c10f7ed, 0xd95297f4, 0xf3d2f7e8, 0x8272fe43, 0x197ec08f,
11391 0x7fb0a3cb, 0xd859f2c6, 0x73fd6307, 0xf8462fb0, 0x9500fea7, 0x7a3afe4d,
11392 0x81bf82fe, 0xfbfc97e0, 0x3fb9fe09, 0xffb36548, 0xfaaf9528, 0x35fea89b,
11393 0x6fc1337f, 0x870443f8, 0x1f04adfc, 0x7c11b7f3, 0xc121ffc2, 0xa9dbfb6f,
11394 0xa45ff56c, 0x077f1df2, 0x5ff29fd5, 0x9e8bb827, 0x12387f46, 0xf88a9f9f,
11395 0xe37e132b, 0x2c3fc172, 0xcb8bfb9e, 0xe5b02b38, 0x932d6f82, 0x78c10dc0,
11396 0x46ecbf60, 0x891d7bcc, 0x7c43957c, 0xfc56ea75, 0x98fdc8f9, 0xf19f025e,
11397 0x133af4fd, 0x76e8d78f, 0xe817e45e, 0x03c5527e, 0x00bb1f7c, 0x273c5ffc,
11398 0xee28cff8, 0xb6a95eaf, 0x573fa0e4, 0xf0d68a61, 0xf54ae51c, 0x610fc81f,
11399 0x220dde78, 0xb66bdf72, 0xf6c33b83, 0xbef01571, 0x4eafde19, 0x54f9a34d,
11400 0x9d0b56b0, 0x23cccaa3, 0x33dd5c81, 0xf89d77c0, 0x4039807a, 0x98256afb,
11401 0xff38fb8d, 0xf05fdf00, 0xa5ea95f9, 0x547e136f, 0x670fce8d, 0x770942da,
11402 0xa4e4fc61, 0xdebff144, 0xf22551f0, 0x7fad7bc8, 0xfa0a52e3, 0x937fa5e5,
11403 0xd39f487c, 0xc6394716, 0xf8839c13, 0xc839d4be, 0x5263286c, 0x30418e7d,
11404 0xaa393f9f, 0x0a0335ef, 0x759df4ff, 0xeb4fee47, 0x81df47da, 0x9bf0515b,
11405 0x42db98cb, 0xf3cc8d79, 0xb85d5e16, 0xbe08f993, 0xfca8058b, 0x35cf8a5e,
11406 0x0fe62468, 0x8df60905, 0xb4f6a5b5, 0xa579c8ae, 0x207ae20d, 0x50d9906d,
11407 0xb9f5484e, 0x393fbfb1, 0xd3af343c, 0xc6cf6e63, 0xfaf3e975, 0xdf9baa5e,
11408 0x4f1d609f, 0xf4fefce3, 0x4c1757fa, 0xe3f9dd19, 0x0a17c01f, 0xc7686f9a,
11409 0x06a41cf0, 0xafdf0764, 0xf289aef9, 0xa8be75b9, 0xbe2180c0, 0x7944c9b7,
11410 0x027c5dfe, 0xb0fb81fc, 0xf7ba0ef8, 0x01327c07, 0x8c6ab9d7, 0x5f82b014,
11411 0xcc1cda79, 0xf2b9d136, 0x15c62b52, 0x7f03c796, 0x07cef7a4, 0x03fdc56b,
11412 0xd7f039fd, 0x2fcf48ed, 0x073a317e, 0xc6f555f1, 0xabe23718, 0xc0740cc6,
11413 0x923be37d, 0xb857f3c6, 0x0dc697ea, 0x932678a5, 0x4fe30d35, 0xeb3d6d33,
11414 0x7f82e5db, 0x4a59274e, 0xf19fd483, 0x413ee5fc, 0x3d04fbb7, 0x64fbafd7,
11415 0x3ef3048d, 0xdd12ec7d, 0xff36e95f, 0x983c8f8d, 0x55c7c619, 0x78a767cd,
11416 0x5bdfd07a, 0xdf3a7f44, 0xef875648, 0xaf3e12a0, 0x465e3e4e, 0x7c0b12fc,
11417 0x7c7c419c, 0x6719cf01, 0x7731dcd9, 0x280ed941, 0xfbe94109, 0x81f69567,
11418 0xe546988b, 0x72a5e612, 0xf91d9039, 0x6dd81bd6, 0x62af7c45, 0x6d7cf44d,
11419 0xf21762d1, 0x8fb332f1, 0x306bc9f6, 0x7dcf1753, 0x12494759, 0x36ea4bc6,
11420 0xe80495bf, 0x7bb0d39b, 0x676fc632, 0x85be1707, 0xd321d965, 0x055bcc05,
11421 0xce2ef8b9, 0xbd54ddab, 0x7f8c1fb5, 0xb71373f7, 0xb3e787f6, 0xf60f4e24,
11422 0xae87a72e, 0x0dd72237, 0xe499b072, 0xeb43d633, 0x06a59c92, 0xc2d8a839,
11423 0xaef8a63c, 0xb94ef9fc, 0xfbfd5a28, 0xe4bfa8fe, 0x54178a0e, 0x438b61bd,
11424 0xdc62af3a, 0xf479301f, 0x07ee8878, 0xd5f3e230, 0x76c35a2c, 0xfebe0a9f,
11425 0xbe230074, 0x1b04d4fe, 0xff2e82c2, 0x92faa594, 0xecba320a, 0xb9f99575,
11426 0xb0278861, 0x9f89fbe7, 0xcb6d37cf, 0x1fbd434f, 0xc4ff454c, 0xab4dacf2,
11427 0x15d83349, 0xae9f75f6, 0x16a3d738, 0x9c8a871e, 0xede8a997, 0x623fa33f,
11428 0x9e00b2b3, 0xb35c8083, 0xfdcf2851, 0x355724ac, 0x978c5a88, 0xf9baf24d,
11429 0xffb1ac39, 0xadbe62d3, 0xdd71e57f, 0xe307ac00, 0xe1c7dd26, 0xdd16ca76,
11430 0x0de90e35, 0x9a71a317, 0xead19107, 0xed298f1c, 0x37bfe829, 0x8e7efb44,
11431 0x3fe3d1f4, 0x35b2befa, 0xba4c93ed, 0x52f63697, 0x18f7dd05, 0x80fba363,
11432 0xd8b88877, 0x2e3c451d, 0x071e8776, 0x07111f1b, 0xb0c7888b, 0xc5c73df1,
11433 0x98ccbd74, 0xe4f9c166, 0xd7d4ffb2, 0x5d18f14f, 0xabb3760f, 0x8a3690b0,
11434 0x6e29bb57, 0xc99f19d1, 0x4cf8f2b7, 0xd5c53249, 0xee4f42ad, 0xa4fd72f2,
11435 0x0e589fbf, 0x3ec3185b, 0x0d32cec2, 0x00d508fb, 0x324ea80f, 0xd1b81fb4,
11436 0x0b4fa86d, 0x33ea18e4, 0x9c0334ea, 0x686450d5, 0xc7bf683f, 0x4b06e700,
11437 0x1c87ed0d, 0xa1e01af5, 0xf686e54d, 0x867d9bc3, 0x0ad0fcfa, 0xd688fd43,
11438 0xb23c036a, 0xfda1a36d, 0x86030fe8, 0x75ed31fa, 0x1771fa86, 0x84f00c1b,
11439 0xf686fd8e, 0x1a0f5db7, 0x1fb227ea, 0xed8bea1b, 0x93c0333f, 0xda185fd5,
11440 0xd3ec253f, 0x862d49ed, 0x5c4407e7, 0xa4fbaa62, 0x39e9fde1, 0x53f00c67,
11441 0x87946f48, 0x879256f9, 0xf783f596, 0x07fd0055, 0x186b37ac, 0xfda999f3,
11442 0xab2fd0d6, 0x6dfc47ee, 0x52cfe28d, 0x947cb6a4, 0xedcca7db, 0x6d3e5869,
11443 0x7dc16f72, 0x89f8c66f, 0x2acef614, 0xcb05b859, 0x9b363341, 0x9f40dc13,
11444 0xa0b707b9, 0x68a90c98, 0x1e00bb31, 0x16ece4ba, 0x8d61d217, 0xfc444a49,
11445 0xc1ab486f, 0x89a6c472, 0x8fd41252, 0x83585dac, 0xfd71757a, 0x61cb8599,
11446 0xd837a35e, 0xa09dcd89, 0x3e30da0b, 0x6f887b26, 0xe29b0037, 0x8c8c363a,
11447 0x5dbbfca6, 0x37191563, 0xba76bb33, 0xb86e316a, 0x1d41676b, 0xafc0db96,
11448 0xac620e0f, 0x2c7afc0e, 0x1f5f8277, 0x386e8584, 0x945887f3, 0xa9e07553,
11449 0xdfd73c24, 0xcd53e93e, 0xfb0ae1ac, 0xe3013dcd, 0x8b4427d6, 0x737ec7bc,
11450 0x7f426627, 0x0f00ab28, 0xdcfa71f8, 0xbe1dd280, 0x2a3bc436, 0x372a1707,
11451 0xd7bfa1a4, 0xc0c0dfad, 0xc3e227b9, 0xa27805fa, 0xf5fa6dfc, 0x785fb078,
11452 0xc3de63de, 0x9f6e1ce4, 0xf59ae407, 0xd7ca023c, 0x943a2ee2, 0x80c497e0,
11453 0xd31fab9e, 0xf80e5bea, 0x136ad595, 0xf71637dd, 0x4da43056, 0x5f1be071,
11454 0x700f16df, 0x64ef7892, 0x8e0e6f9e, 0x72e380ab, 0x927f8c2e, 0xc61c0096,
11455 0xbf00fb1f, 0xf35d2ce7, 0x0e67dcb1, 0x2c2fa0c8, 0x069a65c5, 0x20b93ce3,
11456 0xfb9d369a, 0x22ff46ac, 0xfc9de44b, 0xfbcc473c, 0xfd0d1cc6, 0xf58b9fa2,
11457 0x8df7ee3c, 0xfd82d8fe, 0x7932a0af, 0x40f98849, 0x579a29cf, 0xcb0ad4c3,
11458 0x8cda3fd7, 0x07c04ef7, 0x8a3b426a, 0xf98737cf, 0xb8732b1b, 0x5af9625f,
11459 0xa5baf8a2, 0x85c5abc6, 0x4c916f8d, 0x4fed3dd5, 0x1065e237, 0x5186af7c,
11460 0x49f8e5bd, 0xac9f4fba, 0x52969835, 0xe786213f, 0x3f884a21, 0x4d05a7ef,
11461 0x923e004b, 0xff7c36e3, 0x9812dfa1, 0x4fbc787f, 0xbe6136ae, 0x6aa6e242,
11462 0x5121e213, 0xbe786af5, 0xc35edcc8, 0xc6e275f9, 0x1e3fa3b5, 0x6af6f381,
11463 0x99610798, 0xc87df3ae, 0x9cb5448e, 0x703262d7, 0xea5ee2dd, 0x1316b755,
11464 0xf43ac3df, 0xe7e76952, 0x3bd5bd5b, 0xa6a9de0b, 0xc502d7bc, 0x4f58478d,
11465 0x07e52be5, 0x23b3e07b, 0xa92fdc39, 0xa3e71a77, 0xc217e7e8, 0x19555c6e,
11466 0x6f425bb7, 0x61cb1fdc, 0xf3fb9fbd, 0xcdd9120b, 0x44dfbbe6, 0x5c3ab1e7,
11467 0xde20e30f, 0xd8b46fea, 0x98f56f11, 0x8bf64167, 0xfa7add91, 0x77073987,
11468 0x4ff3ba9a, 0x89003937, 0xbe40298b, 0x01ac1b3c, 0xadf239fc, 0xca69fa1a,
11469 0xe84ccb83, 0x6ab1240b, 0x4652184a, 0xc3cab496, 0x72bf326e, 0xfa27ff23,
11470 0x64c1f28c, 0x37dd325f, 0xfdd57410, 0x7474ee82, 0xde206627, 0xe579e5df,
11471 0x89dcd3eb, 0x5f9d4748, 0x63fc9fd7, 0x0e8c2f94, 0x2e7e081f, 0xca120d62,
11472 0x44d658eb, 0x46d678e5, 0x075877e5, 0xcaa61e95, 0x1a624e58, 0x4bcc2595,
11473 0x4d5614e5, 0xa06b2965, 0xa26b1a72, 0xa36b0672, 0x5453f612, 0xfb4a997a,
11474 0x57e0d9be, 0x79973960, 0xaac79ca9, 0x7c80bca9, 0x672df80e, 0xcddf040d,
11475 0x066ca89a, 0x841ee03d, 0x953b0971, 0xc59e81af, 0x127f0df2, 0x9bbf2195,
11476 0x97186db9, 0x84f2a1c8, 0x6df2a35f, 0xad95117f, 0x7bb50f7e, 0xe54a5fc7,
11477 0xca97bf29, 0x2a72fed3, 0x6a3efcdb, 0x057f9ef7, 0xabf81f95, 0xff37fca9,
11478 0xf43f2a46, 0x77fca807, 0x59951d7f, 0x06fb4656, 0x9fca1396, 0x3948f40d,
11479 0x81b8f56f, 0x1cb905ae, 0xe63dc78f, 0xa478dc84, 0xfe30cca7, 0x271c94aa,
11480 0x66dc5126, 0xe757bfba, 0xa316c63e, 0xfdcd3e3e, 0x83a24748, 0xe1a554fc,
11481 0xc8bcc304, 0xd4bb5366, 0xcf6b6807, 0xe7b5cff5, 0x8d7f1d82, 0x10d1f6d5,
11482 0x0763ddae, 0xa5b4f47b, 0x5047faad, 0xf378fd2f, 0xced83b5c, 0x3ef78eb1,
11483 0x54c3967b, 0xab04e63f, 0xe6760151, 0x5783df6e, 0xa81e70b2, 0xbc7e93f7,
11484 0x4ce6ee63, 0x27d7279c, 0x500d77b0, 0x853ad5fe, 0x1bf2aff2, 0xa1a3e58e,
11485 0x14ad531d, 0x6b0bdda0, 0xde8af147, 0xebd645da, 0xe9593def, 0xf50f1092,
11486 0x01eda07f, 0xe508c94b, 0xbc2c5c63, 0x1bb7f35f, 0x1937499f, 0xe99dbc3f,
11487 0xcc9dfd26, 0xfee6a4f3, 0x91e7c07f, 0xfaf96dfc, 0x3be8cff8, 0x0a23ac1f,
11488 0x9631bbe5, 0xf00e9feb, 0x55ff719b, 0xcdfae02f, 0x3747e4e9, 0xdf7379ea,
11489 0x31bea993, 0x8ad2bb5a, 0x8a4ce6f0, 0x7ac7d487, 0xfdb173a2, 0x43d274d6,
11490 0xe5187d29, 0xded2edbd, 0x7261dd56, 0xeb97353f, 0x35c2655d, 0x8bea3175,
11491 0x8f0cc9ef, 0xef7e07da, 0x01dbd683, 0x66adee6f, 0xcc529efa, 0xd14a0f84,
11492 0xc937042e, 0xf3a124a3, 0x3a2fd518, 0x5dbafb82, 0x1b3a359a, 0x51107ae8,
11493 0x9d5ffe87, 0x4a5ffe42, 0x7e3e50df, 0xccab6a57, 0xf522d7f3, 0xbe316edd,
11494 0x86d851d9, 0x6f9fadef, 0xa4bc6377, 0xef58fd37, 0xf9e3e40f, 0xb7da2bb7,
11495 0xac3c8190, 0x7e3e7dc8, 0x2e15382b, 0x1e6bf727, 0x17363dcc, 0x8bd543ef,
11496 0xf1add8bc, 0x8adefa66, 0x283ae052, 0x58abf585, 0xb3b26e43, 0x62c72166,
11497 0x523bf53d, 0xfbb8ef28, 0xd7f68d3c, 0xc23cc1a1, 0x88bd74f4, 0x378e745b,
11498 0x2941dfa2, 0xd8a7ae2c, 0xa78d1a42, 0xbc7d33db, 0xf1bdff9d, 0x4f7c8976,
11499 0x28c73c7d, 0xd61cfae3, 0x439f5a36, 0x78fa41f8, 0x3d7d70bb, 0xe37c8de4,
11500 0xf0beb878, 0xd71b46f1, 0xd1b5b0e7, 0xf7121cfa, 0xdbc73a6b, 0xbd78f3d9,
11501 0x2237b38d, 0xf72f4fff, 0xdc13ff0a, 0x180e7643, 0xf9c6c534, 0x330b69f9,
11502 0x92bc039c, 0x1ff3edcb, 0x595f38f2, 0xc97ae36e, 0xfdd2b2e2, 0x8bae89a4,
11503 0x95af91bb, 0x173a663d, 0x26dfe253, 0x3c4e4b3f, 0xa7da24c5, 0xfe7c26b2,
11504 0x17bf89b4, 0x98f6b048, 0x5fd7b367, 0x2c333a34, 0x55a89dae, 0x6b6f309b,
11505 0xe195aba2, 0x6f128039, 0xf12bf5a5, 0xea1460f6, 0xd8098d5f, 0xfe83ec1a,
11506 0x8bdf50c4, 0x974f30b9, 0x15c5e5c6, 0xf9883d6f, 0xd0e58954, 0x9e3e186f,
11507 0xe4cc7c16, 0xb0b2b4f6, 0x791d42fb, 0x5cba1f1c, 0xc36fce47, 0xc6878e60,
11508 0xea2af049, 0x8e3c31cd, 0x3f70fa73, 0x7accc7da, 0xfb83da34, 0x063bd3fc,
11509 0x73bc1097, 0x9c01e52c, 0x0a763c3e, 0xed666bee, 0xd826669c, 0x3e315ac4,
11510 0xdde76b33, 0x929e7c66, 0x1dfe88c1, 0x5fa4ad67, 0x255ced67, 0x14d3ffda,
11511 0x0e645f6c, 0x1ae304fc, 0xed1d0f45, 0xb19b7183, 0x63fa178e, 0xbedcda79,
11512 0x7477bf01, 0x857eca87, 0x73779bee, 0x7d4d039c, 0x0b748ed9, 0x977ec5c6,
11513 0xe697cfcb, 0xe7858f30, 0xee29788d, 0xdb68fe30, 0xfc82bc71, 0x628ea69d,
11514 0x34f76e3c, 0x9cb027ab, 0xc84ad214, 0x9ef56c2d, 0x5b4a72c0, 0xbbba0975,
11515 0x9c361fa5, 0xb861b2c0, 0xdf8877ef, 0x2a8e0fc3, 0x49c60678, 0x68dceefd,
11516 0xb7d277f4, 0xa41e4e84, 0xee85b1b8, 0xf22dedb9, 0xde3049d6, 0x8ed7b75e,
11517 0x7c6f6876, 0x6bf499ba, 0x5a0af56c, 0x866880e7, 0xfaabdceb, 0x6fbfd0a2,
11518 0xef46e714, 0x2c4731f8, 0x7f3479ec, 0xbfe099fe, 0x1ed7aaad, 0x52a0724b,
11519 0xfc2283be, 0x49e67ab4, 0x3b284342, 0x1b8c413c, 0x3d70f5ee, 0x7ef8501e,
11520 0x036f9b19, 0x98ae8ebf, 0x29e8bb9a, 0x7f31b26b, 0xec1bdc1a, 0x50ed1657,
11521 0x883fa217, 0x06116ed7, 0x13bfc1fb, 0x743db8c4, 0x673a2e28, 0x172fe7d0,
11522 0x7c617f42, 0xad9ff386, 0x8fa7bd74, 0xf6160eab, 0x5ed3f041, 0x9f4fef1f,
11523 0xb760ec6f, 0x731b5ef8, 0x923e719b, 0xc3ac0f98, 0xb09f361c, 0xcebeb476,
11524 0x892d3379, 0x30f59fdf, 0xb996af7e, 0x3bf5b0e5, 0x44bb5e6d, 0x22acd076,
11525 0x33343aff, 0x28704bdd, 0x04fba73f, 0x1ac8eb91, 0xdf69e3cc, 0x051f6197,
11526 0x79a699eb, 0xf7e5ca18, 0x55f90f55, 0x78e580b2, 0xe3c987ee, 0xd84b3127,
11527 0x49f8e57a, 0xb41a6ed4, 0xb4e7f8c7, 0xf21a3ea2, 0x54d674eb, 0xc17df2ab,
11528 0x5f984c89, 0xfc866316, 0x4fc05974, 0x9650bf96, 0x71abc6e6, 0xe8392d0d,
11529 0x8cb03d17, 0xd76a8cf2, 0xf9c56b4f, 0x6bace526, 0xef7a8389, 0x2cee9c57,
11530 0xfb0dc79f, 0x790d91ef, 0x002bc9cb, 0xf75f3f0e, 0x07e06119, 0xaf9d7b43,
11531 0x8aa95314, 0xcfb9847e, 0x3059dd8d, 0xedc9d97f, 0x6cb87837, 0xf2f10f6e,
11532 0xf0257c6e, 0xc667d3af, 0xa7c24ce0, 0xb3bc70ac, 0x277ecd0e, 0x1bf113a7,
11533 0xd5e309fd, 0x3e62d880, 0x14894d7d, 0x8ea1fbc4, 0x012cf6ce, 0xa7491ae9,
11534 0xeec75b74, 0x957f5c2c, 0x23dbf299, 0xc47e0af1, 0x67c8699d, 0x1ea9e26b,
11535 0x3abe539e, 0xf6752266, 0x1b04f523, 0xed4df1e9, 0xddc1609f, 0xf8d64f3c,
11536 0xe0be293c, 0x8a429c9d, 0xcc9c6847, 0x0dacfac6, 0x8c62ba46, 0xa278f509,
11537 0xb4a182c6, 0xb4e7a75b, 0xa612c6f8, 0xceaba774, 0x7b7d2977, 0x10f2f3d6,
11538 0xea03b093, 0xf3d41cb4, 0xfff26609, 0x84e609bc, 0xd6f07df0, 0x725f7cc1,
11539 0xe90a2bdb, 0x4ede766f, 0x50b4eff7, 0x13f41f5b, 0x93335d27, 0xa9d6fe7f,
11540 0x834d8f63, 0x96aff272, 0xc9bb61d4, 0xbf46edb0, 0x372be862, 0xbf262c46,
11541 0xe5172da5, 0x3a1655f5, 0xb1f682d9, 0x827142d5, 0x536f9fcd, 0x35fd2127,
11542 0x7d3e7146, 0xb98323dc, 0x25a5fa9d, 0x9a7d25e0, 0x7e46b326, 0x6be3765e,
11543 0x3e3c4e9d, 0xb2c77944, 0xabddaf89, 0xbd935755, 0x3663c94c, 0xadb7c78a,
11544 0x21bc7b24, 0xccbca19a, 0x41ee9b56, 0x1765f678, 0xb37f4333, 0x2165b735,
11545 0x3f091f9e, 0x59aa8e73, 0x69a96226, 0x3f9db9fc, 0xe87aab9f, 0xc3cd5cf9,
11546 0xbf7c2b9f, 0x681aa77f, 0x777f43f3, 0xec6e712a, 0xcbcd4eef, 0xa8dbafeb,
11547 0xffec14fe, 0x47b4efd0, 0xebd45405, 0xfccd170d, 0x4d17ce7c, 0x2955befc,
11548 0xfce37568, 0x4f74cd0a, 0xba24fc0f, 0xf54bbd5f, 0x7deafdd2, 0x088c97cc,
11549 0x3670b57e, 0xc6afd1f9, 0xd5fee99b, 0xe5331eab, 0x642a0581, 0xf0521f7e,
11550 0x29e5abd1, 0x8e967e74, 0xdd7a44c8, 0x643f2763, 0x62441e2b, 0xdc7ef2fb,
11551 0x7fdcc85e, 0x9e2a3fd8, 0x2c6d3bda, 0xe0f914ae, 0xf2f94cb0, 0xe3cf1fdf,
11552 0xf4a1f298, 0xae6bfa20, 0xcbbca30a, 0x3f389385, 0x39454c68, 0xc469a198,
11553 0x987b35f7, 0xdc937666, 0x5740fbd3, 0xc2aee75a, 0x22fa4af7, 0x24d346bc,
11554 0x7d06182e, 0x1ef85351, 0x4ccf83c7, 0x0abbeff9, 0x49befbc5, 0x5d7c7087,
11555 0xf90b07ce, 0x774af5d4, 0x3f51a43d, 0xda49d88e, 0xc306804e, 0xfbff2800,
11556 0xf51cf0ad, 0xf74c9c42, 0xca1706c6, 0x97587521, 0x7e8b27dc, 0x94f90b07,
11557 0x2ce51a8f, 0x7e1190eb, 0x7eefc85c, 0x62fb9216, 0xce8c0dbf, 0x1837facd,
11558 0xc7cec1db, 0x522c7a84, 0x3f0baf8e, 0xdd0f1233, 0x79ebecf0, 0x0aeb5d9d,
11559 0xbad36544, 0x425d7ccc, 0x5b2a65df, 0x2aa679e8, 0x179c6e6b, 0xd70f786b,
11560 0x0c90ffdf, 0xabd02a0e, 0xe31b3cd0, 0x3202333c, 0xac99bba9, 0x37c5f48d,
11561 0x88ab7bad, 0x33ae4573, 0x06db7d72, 0x64bf5c4b, 0x37e4bcf8, 0x37e4cb25,
11562 0x6303d659, 0xe56bc70c, 0x23b79dde, 0xeece875d, 0x59da0433, 0x62a5581f,
11563 0x7a155a5c, 0xc4b5f2c9, 0x3b61ebf9, 0x7125abf1, 0x7df84e46, 0x24da919b,
11564 0x51c50875, 0x841c9eaf, 0x2d77c771, 0x3d48ff84, 0xc7086637, 0x637698f3,
11565 0x8bb8e45e, 0x7c7911d1, 0xdbc8bcc6, 0xc88bf7ae, 0xc888cbe3, 0xa8621be3,
11566 0x888eac9f, 0x171be3c8, 0x6c57c791, 0x4ce7a780, 0x9be3c88f, 0x28ef8063,
11567 0xbed0c7ba, 0x50d8b3cc, 0xb574a73f, 0xef4efea1, 0xaef806fd, 0xed0d87f2,
11568 0x0c6afbe7, 0x78acf7f5, 0xfa0f50c4, 0x73b8c7a2, 0x87ae10f1, 0x6d3c936b,
11569 0x103081f4, 0xfe0f6f78, 0x1dcaa480, 0xd9c7f6e1, 0x56a2fecb, 0x7d29e3d0,
11570 0xe248127f, 0x8f116671, 0x10c47705, 0x9d8d0daf, 0x517dc766, 0x444b4d9a,
11571 0xcd7ecebb, 0x585806ed, 0xc4e6f9c3, 0xdda94b07, 0x3a74d8fa, 0xfc027987,
11572 0xc0e81f6c, 0x77cf20da, 0x6f0017e9, 0xabf79e1c, 0xf5da1285, 0x78a56ebb,
11573 0x583ce76e, 0x5577f529, 0xf3ea2f9c, 0x43f18fdc, 0xecdbee1b, 0x54cf3254,
11574 0xe28e3f1e, 0xe9751eed, 0xc31a96e7, 0xd6451d7e, 0x164be500, 0x30ac5b06,
11575 0x8fd05adf, 0x97849af8, 0x55dda1ec, 0x3de9bb45, 0x127f1ab0, 0x96520fdd,
11576 0xe8160284, 0xbf27eab2, 0xf0e3e1f8, 0x1463e2be, 0x27f878a7, 0x7e21fcbf,
11577 0xc43fc407, 0xc871744d, 0xeefbcf1c, 0x874ba7fd, 0xbac65f51, 0x64625ee8,
11578 0x9b7de27d, 0x26eb7abe, 0x3c16fbf5, 0x37a5dbf8, 0x8ddeff7b, 0xd586b767,
11579 0x597f36f7, 0x613cc7e9, 0x356a907c, 0xcbd5c3de, 0xaabe0bef, 0xf8a56b1a,
11580 0x57c92ce5, 0xe5fcf28f, 0x707affd8, 0x45f7bc3b, 0x717bb5c9, 0xbfcf077f,
11581 0x1da1cf8f, 0x948bf5e1, 0x3cf8a92b, 0xfff80865, 0x58a36768, 0x6f7cf98f,
11582 0x8b7ee10c, 0x41d1589c, 0x2b04f3fb, 0xf65c87c5, 0xee3fa3f9, 0x447358cb,
11583 0xf71ea0bc, 0xf7a760e5, 0x1e88f88a, 0xf4417f2f, 0x92944473, 0x41ce9f3a,
11584 0xf7403d98, 0xb17f7562, 0x8b383c9b, 0x651bee18, 0xae10be45, 0xac125b17,
11585 0x54901f14, 0x4b77e52b, 0x2efa28ea, 0x7d1b04a2, 0x2872473c, 0x68cfb46d,
11586 0xf1451849, 0x86342900, 0x128a0ce2, 0x40defea2, 0x7ee024ba, 0x77dfb8c6,
11587 0x5d682bd9, 0x3acff7bd, 0xeb49f79f, 0x79889c61, 0x1f5878e0, 0xfc41ce39,
11588 0x9bda1c2e, 0xe31ef665, 0x4c86d71b, 0x4af48e3c, 0xbeefb5b3, 0xfdf5e51d,
11589 0x5eb2f59e, 0x307f9e62, 0x86673f0c, 0x605f13a4, 0x6c307f7e, 0x0fe3cc5c,
11590 0xe8038187, 0x60c1079e, 0x42d8066a, 0xb9f88351, 0x6f578d05, 0x3fc892d5,
11591 0x7487f304, 0xe7908dfc, 0x61af023f, 0xc3ec57b9, 0x635c83f7, 0x255f84f9,
11592 0xc800ed3f, 0xfb4fc21f, 0xfd0654dd, 0xfa365439, 0xe43faa35, 0x88f8222f,
11593 0x51f043df, 0xcf95297f, 0xfcf4bdfa, 0xc1397f39, 0xa8fbf53f, 0xa0aff26c,
11594 0xabf82fe7, 0xbfc97e09, 0xa39fe091, 0xe785985f, 0xbe547513, 0xfaa06fea,
11595 0x09fbfcd7, 0xa41fc37e, 0x4a3fe432, 0x9bf98fcf, 0x6fe13e08, 0x7f6df826,
11596 0x7f56e088, 0xf8ef952b, 0x29f9e8db, 0xa30487ff, 0x45fee23a, 0xe03f19d2,
11597 0xd9817125, 0xe25e7e8d, 0x4bb34582, 0x2e57de00, 0xd7617dd3, 0x41d2f97c,
11598 0x34278be0, 0xfb7bf699, 0xee299856, 0xfb95fba3, 0x16c7d62a, 0xaa5cfd53,
11599 0x268d486f, 0x12ff6cbf, 0x571fdd2b, 0x967f7256, 0xbda8552d, 0xfd532f92,
11600 0x92e62b13, 0x538f58df, 0xd92ae700, 0x1931d81c, 0x93322ddb, 0x111fdefe,
11601 0xe3ca4dd7, 0x4f293f76, 0x8faff7e6, 0xcfc20546, 0x629b2b29, 0x7355700d,
11602 0x30e3e072, 0xc62d59be, 0x1c991b61, 0xcfc7ddfe, 0xaf307ff7, 0x90f9d604,
11603 0x03ca4be4, 0xe0717c7c, 0x99d83cdc, 0xc3bdb332, 0xcce4f28a, 0x8d4ed9e8,
11604 0xebcfd3cf, 0xfe224e92, 0xe13269f6, 0x61b69f6f, 0x2fee265a, 0xddf4c816,
11605 0xf205c48c, 0xe99fb857, 0xfba65f37, 0x994acaa4, 0x816c81e2, 0x0363e059,
11606 0xfcdfbbad, 0x0eaf54b9, 0x7471453c, 0x6d13cad7, 0x016fd193, 0x1d11657c,
11607 0x39e2c50e, 0xbb88b26e, 0xa68f8fee, 0xf9c8b6bc, 0xf17bff8c, 0x33f009b3,
11608 0x8cfc47aa, 0x4f3f09ef, 0xfde3fb88, 0x222277c4, 0x977fa4f1, 0x7df109f5,
11609 0x1e06c0f2, 0x376c8fbf, 0x731fcc47, 0x2e3be8ce, 0x8fe93295, 0x23b82c03,
11610 0xf998e31b, 0x7e43dd32, 0xb3aad27c, 0x3f3e6107, 0x91ddf3c8, 0x2c9fed07,
11611 0x8ea18f91, 0xfde52b8d, 0x1f235c0f, 0x7e02be41, 0xda04795d, 0xe93bbf6d,
11612 0x7d94364c, 0x8c16ee03, 0x1f463abf, 0xf989f648, 0x161764f6, 0x80fbbf0a,
11613 0x2b4fc447, 0x651a3df9, 0x13dc9ee5, 0x3805dc7c, 0xb5f52bae, 0x0309f8a9,
11614 0x930edcf7, 0xf97eca05, 0xcf1c3af2, 0x49d24f76, 0xe0212f1c, 0xc7cbc7d1,
11615 0x9e2dbef1, 0x925bbf52, 0xf1bdd3d8, 0x37e1f4de, 0x79f5c1e9, 0x7f513ee2,
11616 0xe0f51fd6, 0x8a7696e3, 0x70ce0753, 0x38b4c83d, 0x3917bfba, 0x27f96f4e,
11617 0x649f8101, 0x886f3f1b, 0xe7476f7c, 0xf02025be, 0xf28cafd8, 0xe2cb26b4,
11618 0xf68cfabb, 0x4627ebdb, 0x726f9bab, 0xd403f31e, 0x1eafa0bf, 0x9fa263ce,
11619 0x1fbca994, 0x0267ef33, 0x44f0475b, 0xe4dc0d45, 0xe88f601c, 0x00fd8fc7,
11620 0x7bbf1f7e, 0x18adeec5, 0x42d77cb7, 0xc90e74b9, 0xcef49bb7, 0x1fda25af,
11621 0x2b0dccb9, 0x17f5878f, 0x9fa97c14, 0x48de6043, 0x79d7565e, 0xec055244,
11622 0xadf0c291, 0x88b8f7bf, 0xe3793fa3, 0x9bca58a1, 0x8510dfc8, 0x663edffe,
11623 0x2c503e27, 0x0c3f3521, 0x7f898a7f, 0xfe7227cf, 0x7aacf2c7, 0x7132805e,
11624 0x32239e14, 0xf519cf7e, 0x75fbcc28, 0xb77f939f, 0xd307c169, 0xfe3c0387,
11625 0x0fe74c9a, 0xfcd1a5ae, 0xcc1ff6fe, 0x86f46794, 0x677e1788, 0x63dd096d,
11626 0xf712c24b, 0x054fb8a7, 0xa626fc78, 0x9f7df085, 0x09c1fb42, 0xe173e5d7,
11627 0x0ab2097e, 0x22ee37f6, 0xb8f2f8a3, 0x6f70d90e, 0x6345cc6d, 0x84bfa07b,
11628 0x76a4dafb, 0xa144bb63, 0x15235dff, 0x7e8ffefa, 0xd7f5d06f, 0x64c5b97d,
11629 0xff49a227, 0x24c9a93f, 0x2a164fcf, 0x76ddb107, 0xfb84bb3b, 0xbb7cc744,
11630 0xc5a07a8a, 0x557a4d15, 0xfe4d1119, 0x6394f6f3, 0x9fc076f6, 0x2a07e46d,
11631 0x6c032bfa, 0xbb1883be, 0xab73edfe, 0x218d25e7, 0x5df5de3d, 0x3bb022e3,
11632 0xf282f978, 0x9decd699, 0x1579899c, 0xd8eefa66, 0x7ab73c7f, 0x2277f86f,
11633 0x307524d3, 0x84ec57cf, 0xe0dfa157, 0x418fb9c0, 0x33ea063f, 0xd7c61cf0,
11634 0x29217a8e, 0xf905babe, 0xb6395eaa, 0x85d0e282, 0x2d57a4f1, 0xea10eabe,
11635 0xc0ad7a89, 0xbadf2e1e, 0xdcaadc9c, 0xd5ce293f, 0xbffe49be, 0xe4dedfa9,
11636 0x2e5c95fc, 0x01c5bd77, 0xb77e7df4, 0x5ebec4fe, 0xdfdfc21e, 0xe079f42a,
11637 0xbd47b5ac, 0xd72866bf, 0xef224517, 0x297c5661, 0x567e7f7d, 0x3cc65da0,
11638 0x2e50cf50, 0x1c12fb47, 0x2fb0cf94, 0x7e30858d, 0xedcf981e, 0xe20ad903,
11639 0x538a74a7, 0xd4da9bd5, 0x0a43d200, 0x2e2e91b9, 0xefe187d8, 0x6ddfd478,
11640 0xf977d20e, 0xfc28be82, 0x63f41e3e, 0x852817d8, 0xe4d5e2dd, 0x6871ebbf,
11641 0x7e008efc, 0x82b687ff, 0xca3a82e0, 0x9b9df4cd, 0x7426f7c8, 0xaedbe118,
11642 0xcc89e11b, 0x629abdf8, 0xac9e11bb, 0x43a1e11a, 0xf6e2bef9, 0xa9f3e324,
11643 0x6fdc236e, 0x9994637e, 0x78a0ffdf, 0x0c147e95, 0xb8c03eff, 0x64017f58,
11644 0x60f7e20c, 0x21afb7fb, 0xe8ff507d, 0x7eff920c, 0xcae2226b, 0x8195b00c,
11645 0xf3e36a71, 0x2d859cc4, 0xaaed7e98, 0x87be2390, 0x2ce746d2, 0x73c30f80,
11646 0xf20b7cfc, 0x9e6ce1ff, 0xdc30d9ff, 0xc8e87937, 0xde1c79ae, 0xcfce9b33,
11647 0x035f562c, 0x28c74efd, 0x36d2ec99, 0x9b75d399, 0x35ba72a6, 0x5779d327,
11648 0x60b44aa2, 0x5d5f3645, 0x4723c61a, 0xc91e299a, 0x3df9e21a, 0xd3fae7f4,
11649 0x2c6241f9, 0xe773439f, 0xfa47dbfe, 0x40d89d97, 0x2afb03e7, 0x788efa64,
11650 0xf9403db2, 0x2bceb053, 0xce963886, 0x39f9f3b7, 0x50d7ac0a, 0x62bceb0f,
11651 0x101f97e4, 0xa2f5f49d, 0xf0c206bc, 0x081a7280, 0xbe699b8f, 0x940788e5,
11652 0x51e7f0d7, 0xba16ed99, 0xd3d62d4f, 0x7aeadc9b, 0x579c48a3, 0xd76c79eb,
11653 0x1e7a98c4, 0xff9106db, 0xe234ecda, 0x24f95ae1, 0x6b5c338a, 0xebed139b,
11654 0x2f418e49, 0x2f5c6c04, 0xde1db960, 0x7bdfb943, 0x1c54e163, 0x2044f50f,
11655 0x16147bec, 0x6dffa7c1, 0xc221b3bf, 0xeffb3f2f, 0xf9186a47, 0x9e208f9d,
11656 0xe39c072a, 0x77c5edf7, 0xb6782cbc, 0x3ea5cf07, 0xcb7aaf9c, 0xcae9af1b,
11657 0xbae3b5bf, 0xbfbc88a5, 0x5af8112b, 0xbfa5f02f, 0x274d457f, 0x2d695d3c,
11658 0x2786f7b6, 0x1327f426, 0x332f13fa, 0xbb3e2ace, 0xec634121, 0x9fdfe799,
11659 0x671d0327, 0x985b3ead, 0xcf9bf00a, 0xcfc39eff, 0x3fa97d9c, 0xec361d34,
11660 0x3df879f3, 0x9d8f598c, 0xa1a296bd, 0x85de26dc, 0x8a70c3df, 0xbe7d1973,
11661 0x092f78fa, 0xf1b5597d, 0x90671e1e, 0x357724bd, 0x01c52f2e, 0x70ef8cbe,
11662 0x5542f9e2, 0xd16b8742, 0xd57ef44d, 0xfbf97bc6, 0x0a353e98, 0x5cb889f3,
11663 0xfbf3d6cd, 0xfdf98d4b, 0xd22ae74e, 0x5016367b, 0xd9442f51, 0xeebe743d,
11664 0x3a26e619, 0x72b4c9dc, 0xceeebe7e, 0x5accfa42, 0x3fd1ea6d, 0xe7aa1d6c,
11665 0xd5be86fb, 0x2bdc4cb8, 0xda245398, 0xc65fe3a9, 0x7b34ee71, 0xf05fa2b6,
11666 0x482cc67f, 0xcf41b740, 0x75d21a7f, 0xadd0ef4f, 0x759cffdc, 0x496dc4de,
11667 0xff278f0c, 0x575f3871, 0xed009c78, 0xf9746f46, 0x3c5d1bac, 0x89ad0714,
11668 0xa8ba70f3, 0x48cdce1d, 0xd70ed897, 0xd7debc96, 0x113e8ddf, 0xf82ab8f8,
11669 0xe42bfd1e, 0x9fc26fd7, 0x4f3d1f4e, 0xcee4c6ac, 0x40e67f22, 0x147c437f,
11670 0xaf6e0236, 0x76fe67a3, 0xc88f7d87, 0x38a5e49a, 0xcb5e2593, 0x9ae67cc1,
11671 0xe63d49bf, 0xe30f6777, 0x6766f37e, 0xaf17dd34, 0xbee95a71, 0x27738b5a,
11672 0xaecd3f43, 0x94bc236c, 0xe618eb38, 0xb3a6d5d1, 0x06edfe26, 0xad715e63,
11673 0xef5e6ef3, 0x9dacb3e2, 0x2e31eba6, 0xb4e7b5cf, 0x8103b418, 0xaf2edfd3,
11674 0xbfe76e58, 0xbd5bd25b, 0xcf1a6e33, 0x295a762b, 0xb18a58af, 0x5794f756,
11675 0xc7c117fc, 0x78beb82d, 0xa78f0f5c, 0xbbb2ebe9, 0x3e23fe79, 0xd59a78c7,
11676 0xafdfa3ed, 0x97ffd7d1, 0x7a2e9ca1, 0x9abb9b7b, 0xac97dea1, 0xacf51b9a,
11677 0x884fbe24, 0x4c272476, 0xffe3ea5f, 0xef85a869, 0x4a953597, 0x8ddb9db3,
11678 0x39eebf59, 0x30f47c3f, 0x9dc92dd3, 0xcdb337ce, 0x97466f3c, 0xd58ab9ef,
11679 0x5cc37e83, 0x7af28925, 0x2fea02e6, 0xffb585c6, 0x1efc5dce, 0x2125acaa,
11680 0xee3fbd3f, 0x07df97b6, 0x2e983df0, 0xa9bde9e2, 0xf59fba16, 0x7079899e,
11681 0xb79919eb, 0x4ec6f5e8, 0x1de3edc6, 0xa2d6ce33, 0x620c6638, 0xb0e43f74,
11682 0x78e762b3, 0xccc3fe46, 0xae60d061, 0xde326caf, 0x9e5d98c7, 0xafb616ff,
11683 0x8f407612, 0x49f55717, 0x91fe520d, 0x6c339be4, 0x3f8dc624, 0x6242559d,
11684 0xdf4a91df, 0x4f6aecbd, 0xf6b0e371, 0xd3fb45f3, 0x1d71c469, 0x2b83ddf4,
11685 0x3e8bb1ea, 0xf287d137, 0x8bf12221, 0x9dff0a74, 0xa07f5d35, 0xfe1167dd,
11686 0x48fc3879, 0x13dd394c, 0xbd57edd0, 0xf578e7a5, 0xbd0986af, 0x38adcba9,
11687 0x1f33b087, 0x4c91345d, 0x1ea7ee5e, 0x67d9f67d, 0xea7e5d5d, 0xf49f610e,
11688 0x8333a27e, 0xf98d1954, 0x549a502a, 0xaca3f10f, 0x60052756, 0xdaffdb9d,
11689 0x27f7fdf3, 0xf01e7975, 0x2fb61260, 0xb072fb71, 0xdf17cc8c, 0x072cba96,
11690 0x34db72e5, 0x946aeedd, 0x9cedbe37, 0xbe7437fb, 0x1bcf0efa, 0x9d90196f,
11691 0x4a517988, 0x59be45ab, 0xe415a65e, 0x3d137dd5, 0x3ff7156e, 0x631b1db7,
11692 0x36f4f8c7, 0xcf0da0a5, 0xf129b777, 0x536db405, 0xde901e78, 0x5e78515e,
11693 0x78f1a29e, 0xbcf0a2b7, 0xa77f3d39, 0x84dbc065, 0x03ddbd0f, 0x8d15af82,
11694 0xd288e3df, 0x5d9da81a, 0xb2f7d2f6, 0xe28cf1ec, 0xff957652, 0xa67450ee,
11695 0x907bd999, 0x2cc3b5d7, 0xe5b61f64, 0xa24db415, 0x146ec9f9, 0x05496d93,
11696 0x1147a449, 0x8d7ef0ef, 0x316f13a3, 0x0a9fc788, 0xd4fdebbc, 0xde75f0b4,
11697 0x417771bb, 0x23f45f49, 0x5f9087bd, 0xec8b29b7, 0x7246ef78, 0xbfb4de14,
11698 0x432661e6, 0x7f57663e, 0x7f450a97, 0x24fec53f, 0xfd8a8147, 0xbfcf5859,
11699 0xe8b6f8bb, 0xef3defe7, 0xfa360cc0, 0x226308de, 0xd494268f, 0x2761f9d3,
11700 0x631cf0fd, 0xfef7f744, 0xbd677edb, 0xfe09de31, 0xbf516fe6, 0x7b9de654,
11701 0xe13d127b, 0x68d6e6fe, 0xbf742fae, 0xfb795651, 0x0f7e66ad, 0x9abeff55,
11702 0xb1ca47ee, 0xdd743c46, 0xb874e303, 0xc838f2aa, 0x7c518555, 0xafae5226,
11703 0xb86e3a9e, 0xd8768147, 0x2c71fc23, 0x0cf4cfd1, 0x2e2973c2, 0xa3dcbadf,
11704 0xebfd444e, 0x1f7f7728, 0xa8a4abbf, 0x30b7ca66, 0x5f12ff01, 0x9243de77,
11705 0xc6cff47a, 0x3574e70d, 0x24685625, 0xb7284ae7, 0xe03f3927, 0x728b953a,
11706 0x1ecba07d, 0x03aeb8ab, 0x1389dce7, 0xbf5ce4c3, 0xbff7a21f, 0x3564e4fe,
11707 0x74df5d7c, 0x6e79c2ff, 0x8f64fde7, 0xff1edc5d, 0xd8c7df6f, 0x40aeb2ea,
11708 0x326cdffb, 0xc391e5ea, 0x86d63eb9, 0x75e0f88b, 0xb3b7ee99, 0xe1b4bea1,
11709 0xd98b3f80, 0xf97a8e5b, 0xdfdf3540, 0x1499b1ca, 0x7eb03987, 0x829e445a,
11710 0x30f0d06f, 0xb3aa2c79, 0x85abbe92, 0x03ed077d, 0x491ae823, 0x3afe9d2f,
11711 0xe7e728ec, 0x27bd3a72, 0x91212a26, 0x89fe4c07, 0x09997e2b, 0xdcab9af5,
11712 0xb039f267, 0x81d91b7d, 0x115ddade, 0xaf6f4ffa, 0xce0aff60, 0x73e280af,
11713 0xa0e75057, 0xfcf6a49f, 0x51976cfb, 0xec7e0498, 0xb1e72eb0, 0x2bf62aa9,
11714 0xab793f09, 0x51af6fc8, 0xb09eed0b, 0x42d8a5f7, 0x3e30a4fb, 0xde25e9a9,
11715 0xc7ae1fe4, 0xefb4439b, 0x4810efd7, 0x9e60d7e8, 0xee5f22a0, 0x7ed0478c,
11716 0x9df0d4a2, 0xdefc7d45, 0x5f39edcf, 0x690b555f, 0x018f281f, 0x0bfc017f,
11717 0x8192ec53, 0xbe2d3764, 0xfcc44e7f, 0x28dadf95, 0x2123f79f, 0x3e42ed9f,
11718 0x0163d37b, 0x2d2e8c76, 0xf027616e, 0x49f008d2, 0x49f20c41, 0x70d98a4d,
11719 0x9b97a3ae, 0xe26f3ac4, 0xbf0f54e7, 0xc1e73f35, 0x39f83de1, 0x9f84c7e8,
11720 0xe2ffa3cf, 0xe89bd309, 0xf07a78bf, 0x62cdea73, 0x53ce27ff, 0xcddc5b4f,
11721 0xd39780ed, 0x3be86213, 0xf87d193f, 0xe8d3df3d, 0x7f8015f7, 0x4cd9ccf7,
11722 0x532cd624, 0x843a77e7, 0x0608c99f, 0xca276f3f, 0xaef31945, 0xd5bddfc2,
11723 0xdf8988e5, 0x3a26f9a3, 0xe0dc06cf, 0x3de3b6bc, 0x87ba3cbc, 0x39d3da57,
11724 0xfe4eb1de, 0xc7a61301, 0x401f08fb, 0x5a38b09d, 0x4460f8b7, 0x31c3103c,
11725 0x19c5f99d, 0xbf6fdbdd, 0xf9f8a261, 0xe20b1f2e, 0x51dc02ef, 0xbddf8c64,
11726 0x76d9f225, 0x7f24612d, 0x429a72bb, 0x6a245fe8, 0x65f1e28c, 0x39fb631e,
11727 0xbddf91a5, 0xeef9c636, 0xe7225af4, 0xebb5df4b, 0x7fd7d627, 0xff8a2acf,
11728 0x22fdc645, 0x3eb47de3, 0x3c8523b4, 0x1854afee, 0xf51cb8f3, 0xd8bbe833,
11729 0x714af860, 0x3314ae7d, 0xa3ac38c3, 0x2dcf323c, 0x21ecf020, 0x59e3a665,
11730 0x92899eff, 0x6bdfe66f, 0xf546dc0d, 0x7e1dbe7a, 0xaba27177, 0x3aca5d6b,
11731 0x117c9f31, 0xbcf40dcf, 0xd7185dae, 0xbce8bcc4, 0xd084d036, 0xc605ce1f,
11732 0xf460ae49, 0xb75857bd, 0xf0e25ce1, 0xfa262d9e, 0xa31f0f1d, 0x1e01a1ef,
11733 0xcc16e78c, 0x5850f147, 0x039ce1bf, 0x238069d6, 0xe4df01f7, 0x93de1fff,
11734 0xa277e3de, 0x278f52f5, 0x61338b75, 0x2fa48007, 0xbdf38b86, 0xfa286ca1,
11735 0x06fe4a41, 0x1495c3a2, 0x72cb5f9e, 0xdbdf3e7a, 0xf7e1fd09, 0x72887e93,
11736 0x01718092, 0x04def866, 0x0f74c8f3, 0xe7c454c0, 0xe5ebea6a, 0x48c79742,
11737 0xccd16dbe, 0xa684798e, 0xea0f6882, 0x600d9b13, 0xf8852efc, 0xee24b74e,
11738 0x283ffd3f, 0x00812bd4, 0x0000812b, 0x00088b1f, 0x00000000, 0x9095ff00,
11739 0x50c34b31, 0x97bf8514, 0x4a36ac46, 0x1056dac1, 0xa8508a09, 0x755a5095,
11740 0x97375433, 0x221d0e8c, 0x38ba383a, 0xfc5d251b, 0x09f9ce01, 0xe6e284fe,
11741 0x482ae0e6, 0x22bf8290, 0x26a697de, 0xcbbd0820, 0x77dde779, 0xddf73dce,
11742 0x2e8dcc2b, 0x5eca7550, 0x75619047, 0x444506d2, 0x9aea1152, 0x47e17536,
11743 0x3cd6a5a4, 0x7c22c128, 0x4c12092e, 0xecbbaa75, 0xfbd45ab2, 0x5ffed246,
11744 0x73e4ec6f, 0x7569fd73, 0x27e7cad2, 0x22ff8eba, 0xba77e898, 0x00839d12,
11745 0xe4e3e1d6, 0x65f68fbd, 0xc8773d13, 0x5f94dcac, 0xd53da3e8, 0x3970079b,
11746 0x3adf376b, 0xdbe20d46, 0x0aa8f38a, 0xa567047b, 0xfd398f74, 0xed34737e,
11747 0xb0a56f2d, 0xef37e657, 0xbf89695e, 0xc21b71a5, 0xc1ec8481, 0xc81447a8,
11748 0xbe0daad1, 0xb9417dcd, 0x3e99cb8b, 0xbf05c593, 0x67eb81f0, 0xf3ba7931,
11749 0x8416bf0f, 0xcb62bcbf, 0x5f1dd7ff, 0x7f74f68d, 0x6b7d238c, 0xbb92f72c,
11750 0x50a8dce1, 0xd9f695f8, 0xf4112ed5, 0x738dbcf3, 0xf3e569f1, 0x742b007e,
11751 0x02505747, 0x00000250
11752};
11753
11754static const u32 csem_int_table_data_e1h[] = {
11755 0x00088b1f, 0x00000000, 0xe24bff00, 0x51f86062, 0x38cfc10f, 0x90981819,
11756 0x770143f8, 0x01684331, 0x21060616, 0x62636620, 0x22676060, 0x072bbf5e,
11757 0x9d877d82, 0x1038e181, 0x781f67df, 0x5e240d7f, 0xbb3f4dcd, 0x2ed1d37e,
11758 0x7e27f062, 0x02af8606, 0x058b0c0c, 0x210b7c21, 0xfccff954, 0x18a47608,
11759 0x02a57665, 0x150003f5, 0x8051b77b, 0x008051b7
11760};
11761
11762static const u32 csem_pram_data_e1h[] = {
11763 0x00088b1f, 0x00000000, 0x7dddff00, 0x45547c79, 0xbedd70b6, 0x97a7774b,
11764 0x42c84274, 0x4010dc20, 0x804d8854, 0x024de3b0, 0x10602a31, 0x66b71c11,
11765 0x04484b0f, 0xd3ce7cde, 0x0831baf9, 0x544e38e8, 0x387c0666, 0xa8d041af,
11766 0x1a0c1a51, 0x166bc3b0, 0x26665419, 0xb8c38e3a, 0x6c8a89bc, 0xfd011242,
11767 0x5f283798, 0x3b75539d, 0x4dba6f7d, 0xe3fbe65c, 0x45a7efcb, 0xeab7badd,
11768 0x9cead9d4, 0x25aaa753, 0xd7a92059, 0xfe197212, 0x48a6f968, 0x51d11908,
11769 0x1fb715b6, 0x04846927, 0x6dd5915e, 0x7fc22102, 0x0ed722b9, 0x16c8e427,
11770 0xf5a56821, 0x21075ec8, 0xd3767eb4, 0x9735a0b4, 0x0e057d90, 0xbb3fde0d,
11771 0x25eb08b5, 0x96e2febb, 0x2ee57b68, 0x65ba8251, 0x8b7729ef, 0x6b2a9093,
11772 0xe963a3f3, 0x225df6f3, 0x228742d9, 0x490b1281, 0x8db8e427, 0xac8bbfb0,
11773 0xaacec0be, 0xddf79b95, 0x3456fd05, 0xf69d895a, 0xe17bb953, 0xbeb4b1d4,
11774 0xe04cb0f0, 0xab6dca95, 0xbeb45e94, 0xa0842828, 0x0fdec0fe, 0x62b69c70,
11775 0x4c1a1152, 0x8dbf69c8, 0xbad057a8, 0x067d39bb, 0xb838be7d, 0x5fde14a3,
11776 0x2d782f5c, 0x9bc5fdf4, 0xfe819df6, 0xfdc83717, 0x92ffda45, 0x0751073a,
11777 0x132fb1b1, 0xa9fcc798, 0x1be56f00, 0x7ad2b132, 0x0a15a5c5, 0xb5491c01,
11778 0xc60bb94a, 0x5d514c7f, 0x1c61ce30, 0xe567c747, 0xfa1c7473, 0x0497b2dd,
11779 0x996d4c2f, 0x9e00f885, 0x59f6ddd6, 0x5e613b4f, 0xf08194ab, 0x0ab5eefd,
11780 0x3830b7bc, 0x0abb15fb, 0x4a566df0, 0x9b4dce01, 0x3b830595, 0xf7525bfa,
11781 0xe3ae0196, 0x7c32f21b, 0xf2e6ed31, 0xd5109fb4, 0x4c5f51da, 0x02721688,
11782 0xda6541dc, 0x17e78e90, 0xf7a41484, 0xa8913a92, 0x29fe8eb6, 0x49e90861,
11783 0xfa17ffff, 0x2683e04f, 0x6e5b7057, 0x7b96bd07, 0x0ed5bfe8, 0x70f39d7a,
11784 0x85ed49fa, 0xe5ebfdb1, 0x0a0740a3, 0x83dfad4f, 0x4cfee3e5, 0x55fbd72c,
11785 0xfc6fdbc4, 0xe0dcb083, 0x27f3e2f7, 0xdcb0a3fd, 0xfcb0d7e4, 0xcb0cbf9d,
11786 0xdf1cbfa0, 0x859fe2db, 0x0fbf56e5, 0xafe33f9f, 0x5fceb2c0, 0xf79fcf8d,
11787 0xbd658bdf, 0x5fcf803f, 0x32c3aff2, 0x72c5afe4, 0x96037fa7, 0xbe20fe0d,
11788 0x0ebf8af7, 0x087f46cb, 0x37f1ef9f, 0x47f61962, 0xf40bdcb0, 0xdfc465a5,
11789 0xff7ee58c, 0xfa0f2c51, 0x43bbf05b, 0x3e5893fe, 0x1eeef1c2, 0x8a248a47,
11790 0x3c46b737, 0xea485c54, 0xa648ad64, 0x5672d4f5, 0x5023bf4f, 0xba7ad0a4,
11791 0x1e29d68f, 0x148d2d7b, 0x57bd6959, 0xb9cf6b35, 0x68db149f, 0xdac0273d,
11792 0x15a23dfb, 0x5fbd69db, 0xb81f6b2d, 0x449c5029, 0xac8303eb, 0x48faaafd,
11793 0xafd683b1, 0xfcf6b10a, 0xd2712930, 0xd5847e7a, 0x25688e0b, 0x682f5a2e,
11794 0x0fc2f566, 0x5a6e2503, 0xdf616c2f, 0x2913398f, 0x31f5a649, 0xc27daced,
11795 0x43d13225, 0x808813eb, 0xd16762f5, 0x2f5a14c4, 0x697ab0f6, 0x1a92d9ef,
11796 0xcaf6ff87, 0xe509732d, 0x4dc0ba85, 0xeb45949a, 0xe20acb4a, 0xcc0cf8a5,
11797 0x26447ac2, 0x48fda0f3, 0x8d26b660, 0xac8575a6, 0x0efff684, 0xfdf6c62c,
11798 0xeded8ab2, 0xbed81581, 0xddb1515f, 0xac7eeab2, 0x6c35941f, 0x20f55b4f,
11799 0xd1507fbe, 0xaae07db0, 0x487eb147, 0xa8fb61f6, 0xf7c5bf55, 0x6c3e290f,
11800 0x50757c7f, 0xffeb489b, 0x00b6f821, 0xbe08d75f, 0xfc07920a, 0xa72cca1a,
11801 0x2046bafc, 0x1e3e40b3, 0xf2a6a606, 0xd14b26b0, 0xfdedbf40, 0x5169f0ba,
11802 0x069dbce0, 0x3ccf05f5, 0xbcfd8b9c, 0xb4c8fd80, 0x7eebb11f, 0xca337c26,
11803 0x6f84cfd0, 0x1a7ef42a, 0x7b1abde0, 0xfbd9faf7, 0x3c2318cd, 0xfbd62cdf,
11804 0x5c7ec269, 0x84d79bdd, 0xf08ce3cb, 0xf7aa5e5c, 0x49fb0873, 0x113c1ee9,
11805 0x9fa1a479, 0xef50bc88, 0x4fd84fe7, 0xa3c1eecf, 0xfd0da329, 0xbd22ca68,
11806 0x4fd8a39f, 0x89faf756, 0xf08d6328, 0x7ef44b28, 0xfa7ec63e, 0x9a5e6f74,
11807 0x1e11bc75, 0xcfdea56b, 0x6e7ba469, 0xefd9faf7, 0xbf67e232, 0xf39f8a2b,
11808 0xee80cf08, 0x6dd8abcd, 0x3bb14fc4, 0xd84b9f8a, 0xebdd95cf, 0x88dbbf67,
11809 0x28eefd9f, 0xe601647e, 0xf37ba435, 0xe2364e2a, 0x8a3938a7, 0xf000b71f,
11810 0x3c1eed0c, 0xf11a7b07, 0x1467b073, 0xcf08193f, 0x33c1ee88, 0x9f88dd31,
11811 0xfc51e989, 0xe8cf08a8, 0x3073f5ee, 0x839f88dd, 0x5cfc51e9, 0xef8cfd89,
11812 0x6626bcde, 0x3133f118, 0x029f8a23, 0x57c8a7ec, 0xda10f087, 0x3f712b8f,
11813 0xf118fa87, 0x144fa873, 0x9fb1633f, 0xbc9fb449, 0xcd29fbae, 0x34a7e231,
11814 0x899f8a27, 0xbbebe788, 0x1ca1cfd7, 0xe50e7e23, 0x0533f144, 0xbdd299fb,
11815 0x35f69579, 0x2fb4a7e2, 0xd2b5cfc3, 0xe8675c50, 0xe915e9da, 0x2ef5d727,
11816 0xbefa04d2, 0xd17561e8, 0xf76025e3, 0x433dba88, 0xbe91359a, 0x294facef,
11817 0xdac49878, 0x0277c535, 0xcad45c7e, 0x926bb58b, 0xec192547, 0xd52d14a8,
11818 0xd651ef50, 0xcf7ef0cb, 0xf6867ef2, 0x1957598c, 0x057cb3da, 0xc5767a86,
11819 0x7dfbc318, 0xf50d8baa, 0x60def7be, 0x70373f78, 0xb79ea1b3, 0xf78627ee,
11820 0x31ced407, 0x61b15fb4, 0xcafda1b1, 0xfd4372e0, 0x377fbaea, 0xf4243fbc,
11821 0x9afda180, 0xed0d87c6, 0x1b8f2343, 0x3f0ec3ea, 0x447f7869, 0xfb4316f3,
11822 0x1bcfa3c8, 0xecb747da, 0x9ec7d434, 0x7f7863dc, 0x437efb7c, 0x6f8bdafd,
11823 0x222fde1a, 0xdbda367f, 0xef0c0fb6, 0x6a7cf24f, 0xf32ebf68, 0xea9d9373,
11824 0x9abf1cf4, 0x2b9045d7, 0x20497e82, 0x357b414b, 0xaeb052e2, 0x3f3272f4,
11825 0x3d40b5c5, 0xd947f946, 0x434d573f, 0xd47fa4be, 0x55ea286e, 0x7d0b4571,
11826 0xbe31d3fe, 0xf9f43c2b, 0x35df154f, 0x0df6389e, 0x648137e5, 0xa05aa942,
11827 0x95afb734, 0x6717bf19, 0x31f81a5f, 0xd2cabefd, 0xd685303e, 0x2145897b,
11828 0x04578f90, 0x49d5da0b, 0xf786a922, 0xfd04ac92, 0x85b9b5a6, 0xe462074f,
11829 0x6a1f5d61, 0xfd1d0867, 0x997d93ae, 0xfaad4768, 0xce760028, 0x5e743e9a,
11830 0x4d7908bd, 0xe81228f8, 0xb3efbf4f, 0xfb47d320, 0xcfd42ab3, 0xa15f1d88,
11831 0xf1c60fe3, 0x870f2023, 0x9d11fc60, 0x1bf6b7c7, 0x96df1865, 0xdf186153,
11832 0x3df1d0a6, 0xf55c3fd4, 0x129f1f19, 0x6f210c61, 0xf8e19f09, 0x1c0a9cd6,
11833 0xfd42ad7f, 0x93f1d8ae, 0xc337e3a2, 0x344bdffc, 0x8c637eff, 0x6c59cff3,
11834 0xe6c2bf9c, 0xb3aafeff, 0x9c24fc7c, 0x59c207ff, 0xc59cff36, 0xd656fe6c,
11835 0x777c746f, 0x302dff14, 0xe304f1fe, 0x19c6f35b, 0xa977dfe7, 0x3656fe71,
11836 0x5f55e9fe, 0x389df1f2, 0x97c2e7fe, 0x977dfe6c, 0xd58af8e2, 0x51fe05e7,
11837 0x83aa93b2, 0x9bd27c74, 0x600cbe2a, 0x940e3a17, 0xd0a95283, 0xe84db210,
11838 0x34fc7087, 0x57dbf189, 0x50df9449, 0x39f0059f, 0x59cd5209, 0xce46fd48,
11839 0x8bea4beb, 0xd87bd014, 0xf9adfd4e, 0x8d79d41c, 0x5937f222, 0xa00e0d6f,
11840 0x8a36b6f0, 0x5bcfa801, 0xfa083e3f, 0xee4acab5, 0x24ef872e, 0x9fe78112,
11841 0x96c87afd, 0xcb9979d8, 0xf1f2b5f9, 0x8b791896, 0x64c581fa, 0x6f853550,
11842 0x88c13012, 0xd427fa8e, 0xf8c7038f, 0x10f7ea43, 0x2a7cffea, 0x9bfef1b3,
11843 0x6f507bfa, 0x3a1efea1, 0x7e1564ce, 0x377bbb47, 0xce5fc293, 0x6244ffe1,
11844 0x1dc9faf2, 0xe5403042, 0x0d9fabf3, 0xeefaff45, 0xe9141d7b, 0x0ecc701d,
11845 0xe9d430f4, 0xa74002bc, 0xe0d6ddf6, 0xabf10116, 0xa1a6be02, 0x77321268,
11846 0x75c5365d, 0xdd7ffbc7, 0xe090e53b, 0xa256e426, 0xfdf419c9, 0x7d0a573b,
11847 0x19dc743c, 0xad80b59a, 0x05b65a43, 0x5b649ae5, 0x73721146, 0xf69950c3,
11848 0xf269a640, 0xe3312d27, 0xd6332f4e, 0xeb1b9467, 0x5b26b2ad, 0xd3ad5c28,
11849 0xf699b204, 0xb196733b, 0xbfa71f5d, 0x99d19525, 0x714e578f, 0xcd1f4592,
11850 0x1e00b284, 0xb3ce907b, 0x1d5bec3c, 0x32b9aa9e, 0x1f1fa089, 0xae8049e8,
11851 0xef7c3481, 0x6f361e27, 0x64b3bc33, 0xe74e569b, 0x18b66b39, 0xc336fe04,
11852 0x875efeff, 0xe5a7c966, 0x626427ba, 0x331f3ce9, 0xccf9b7fc, 0xb0c909f3,
11853 0x615edfce, 0xe6f8ce7e, 0x27ffa738, 0x3cb41fc0, 0xe141fc01, 0xa3f9c63f,
11854 0xfe32af43, 0xa6fab2a8, 0x6fb43f02, 0x95d20914, 0x9cadcbf3, 0x1ad7e65f,
11855 0x9f1082f9, 0x385c740c, 0x3878284b, 0x72660f86, 0xc1b8583e, 0x927737c8,
11856 0x87159c80, 0xdfadb72e, 0xdaa660fc, 0x711f7e79, 0x91fdb9be, 0xce9f887d,
11857 0xba7464f3, 0xcee9d38b, 0xadfb636a, 0x7277ae9c, 0xf0daceba, 0x7d54ebd8,
11858 0x41a89f90, 0xeabde419, 0x2d9e9d3e, 0x38fa7a06, 0xde70cd3d, 0xd779e9c5,
11859 0xcd3d18cf, 0x7a70b6f0, 0x2f386cb6, 0xe19d7e93, 0xf777c335, 0x83e69dbd,
11860 0x81d9ad71, 0x6aacf4f8, 0x2c715a2c, 0xe86579e6, 0x62c715fa, 0xdd496ce4,
11861 0x517d4334, 0xfbc336f0, 0x36cc370b, 0x5dafcfb4, 0xbb9f6864, 0x7d431eee,
11862 0x8667e076, 0x77beeff7, 0xcefda195, 0xed0c87ea, 0x663c57b7, 0xdbe6dfa8,
11863 0xe67f7868, 0xf686cdac, 0x19cfe519, 0xed97a7da, 0x69a7d430, 0x0bef0dbb,
11864 0x6df5177b, 0xf7d575c1, 0xef10199f, 0xf9159bfc, 0x74efacd4, 0xafcc78bd,
11865 0xfee3f3e2, 0xf49e5841, 0x69f9f17b, 0x572c28ff, 0xeba6fe81, 0x2b376582,
11866 0xdd9f1eab, 0x9742f817, 0x6f654f8b, 0xaed9e80e, 0xbefea1f4, 0xbfd1ef59,
11867 0x8a7678ec, 0x48152e5e, 0x6d83ac39, 0x9fd74edc, 0x4ecc2ddb, 0x2c01e420,
11868 0x6e4c2a97, 0x2accee97, 0x47a86e26, 0x133b5606, 0x02424bf7, 0x6d7e67ce,
11869 0x85ce019e, 0xc136ae1b, 0x6af905b7, 0xe1987051, 0xb1ba92f9, 0xecceef86,
11870 0x65be1113, 0x61a3e320, 0xdf7f2b39, 0x7233fa02, 0x10fa6720, 0x00fb5780,
11871 0xd13d8deb, 0x2fe33b9e, 0x006c715b, 0xcb1cb9e0, 0x5859fe93, 0xb0fbf71e,
11872 0xc0afe63c, 0x357f13f2, 0x7bfe2d96, 0x7f6ffcb1, 0xfd0fcb00, 0xdf7cb0eb,
11873 0x51e58b5f, 0xdf2c06ff, 0x7cb107f3, 0xe5875fd7, 0x9610fe3b, 0x2c46fecd,
11874 0x961afd5b, 0xf0c4bcba, 0x18acdf4b, 0x9ff5d17e, 0x724f1fae, 0xfc0d397e,
11875 0xb62f8f12, 0x84e2f918, 0x617c8d5c, 0x3a6687d6, 0xf7dff598, 0x3f2987e5,
11876 0xd0743f12, 0xef44db3b, 0x9de8aebc, 0x7bd0c629, 0xe0c3c58a, 0x05fef4e1,
11877 0x5ec71bc0, 0xfb8b049f, 0x483b1888, 0xfac0b22b, 0x2fef9cb0, 0x3f5807d0,
11878 0xa1aec7c7, 0xbda335dd, 0xfa041c14, 0xffa0dcf8, 0xf9f10819, 0x51294773,
11879 0xcfcf1372, 0x7884bf4c, 0xabe8f180, 0x2e94820b, 0xdbb73a3d, 0xed5e1893,
11880 0xe8465216, 0x80d0f17a, 0x0673bc67, 0xa9225d63, 0x3bd07df0, 0x5fa715cd,
11881 0x7e02836a, 0x8d6bc2bb, 0xe87cabeb, 0xff93f8ef, 0x8a72842c, 0x49a1d985,
11882 0x87b44407, 0x2f69e449, 0xefaa37e0, 0x884cdead, 0x500fb763, 0x931eb83c,
11883 0x02fe2312, 0x3dfc06c5, 0x8cd47144, 0x266d59eb, 0x57ffafe2, 0x81bab303,
11884 0x64f4aebf, 0x039cf857, 0xe017fef3, 0xd5fd2bb3, 0x9a22de95, 0x9d2352fa,
11885 0x21dedb7f, 0x30ab0f05, 0x5be3b7ee, 0xc332b7df, 0x7c8ef813, 0xf3ae96dc,
11886 0xa10e7371, 0xf2e59ce3, 0x8ae1ae72, 0xb44ba064, 0x29e82e9f, 0x3947d7fc,
11887 0xe6cebfa0, 0x6b5bfb1a, 0x21592fee, 0x5c7435c2, 0x6490a297, 0xbe885642,
11888 0x06fd115a, 0xfc004b6f, 0x6f0ebdf1, 0xd8fe0a8d, 0x54463fe9, 0xb7e8d9e8,
11889 0xb4fc3b9f, 0xe59bfc1b, 0xb1f56299, 0xcbd47438, 0xb56e50ca, 0x680fd633,
11890 0xd5cfd634, 0x9c21650a, 0xcb7c9a97, 0x3c075810, 0xd064c7d5, 0xea5899cb,
11891 0x54cf2cfd, 0x7f4a1c70, 0x53ea47a6, 0xf69ccf50, 0x1fbdf0db, 0xfd448e1b,
11892 0x40d1c074, 0x83dfa53e, 0x4bce5d88, 0x39427efc, 0x10282e90, 0xf961248f,
11893 0xecdff02b, 0xfdcbbff4, 0xeb095fa0, 0x2155bf7a, 0x06bd6031, 0xc61bd79e,
11894 0xfaa9dfa3, 0x977c2c1e, 0x7224de58, 0x4a77e75c, 0x7ef837b7, 0x7b3a92f1,
11895 0x4c2ed1b5, 0x1aabd431, 0x760daab3, 0x0c03fc22, 0x02410ae1, 0x6729777b,
11896 0xb9c936bf, 0x2b68f80e, 0xdf80fb04, 0xa55ef605, 0xa9f145ad, 0xc0cd2628,
11897 0xe946739f, 0xfcceaf7c, 0x53a7ea80, 0xe404c96f, 0x50a25c8b, 0x47f47615,
11898 0xa1625057, 0x36bcb9f5, 0x64c961a7, 0xbd4eaf58, 0xf5da2372, 0x1bb948f3,
11899 0x520acdfc, 0xcff1085b, 0x0652c4b3, 0xbc967972, 0x23161ee3, 0x0545e787,
11900 0xcebb99e1, 0x7f531768, 0xb85f50d9, 0x405f58c1, 0x7d874e6e, 0x65eb05f0,
11901 0x5f401412, 0x153fdb18, 0x242d1c99, 0x7d606bd5, 0x75b32f5f, 0x48878e6c,
11902 0x555f54d9, 0xe154fabe, 0x1fff5a6c, 0xf42dc591, 0xa945dd7d, 0x1c589fcc,
11903 0xb468acda, 0x6186d3fd, 0x43cd52b7, 0x81ae0fbf, 0x4bb02af5, 0x3b536ef0,
11904 0xc2bbefd3, 0x5f57866f, 0x2fed3bff, 0xeb2a3873, 0xc7182d04, 0x0249b00e,
11905 0x580377f7, 0x863c960e, 0x5328c2b8, 0x53f37bfd, 0xd3f0311a, 0x4aa7d156,
11906 0x80ff193d, 0xed48253f, 0xf487ef8a, 0xffa9d99f, 0xff6a3fc1, 0x85ff69bd,
11907 0xfd47fe86, 0xeff7fda8, 0x6944ff04, 0x2bfee744, 0x95f17d5f, 0x8b27d500,
11908 0x4ddaffb7, 0x4a78fae8, 0x52f74daa, 0xf6dd2efa, 0x7ce81ba0, 0x81b80a52,
11909 0xc5054f5f, 0xf59c60b2, 0xe0493eea, 0x14e6a2f6, 0xff058e20, 0x7e9ffda4,
11910 0xdfe817fe, 0xf64db57f, 0xceaa7c60, 0x3952b11a, 0x68b0d65c, 0xfac7c932,
11911 0xf6beacc7, 0x8dea110b, 0xfc5bfe46, 0x21d3afec, 0x0a7282df, 0xd044d78f,
11912 0xf5b65d9e, 0x975852b3, 0xca3b48aa, 0x183bf991, 0xea2a62ff, 0x724ad9bf,
11913 0x270a76e7, 0x1c55ddfa, 0xbf0d552f, 0x437442f8, 0xd009fd79, 0x4043d417,
11914 0x5dfcd8bf, 0x974fb705, 0xe3b4ae4a, 0x232714d4, 0x8bd048c9, 0x90485e3a,
11915 0xabe2a7d9, 0x3c43e54f, 0xb7d6ccf2, 0xbe0c42dc, 0x173a7974, 0x7b9ffb9a,
11916 0xb77ac4d4, 0xac5bca95, 0x5bafa41d, 0xabb7236a, 0x2a5cacc3, 0x1f90dc47,
11917 0xecb374b3, 0x4bc7d00d, 0x99fa7c5f, 0xf83e2127, 0x0077ab37, 0x8bc97fed,
11918 0x8637bfaf, 0x90ec97d6, 0x69b326d3, 0x0ef48538, 0xffd154fa, 0xa0e82dee,
11919 0x5f97e2c7, 0xec21d457, 0x1da9fdf9, 0x63b25974, 0x7486429f, 0x684947c6,
11920 0x8ce2d29f, 0xc7d09f43, 0x882760a5, 0x00ad7eaf, 0x15ed4ffd, 0x1c6e4648,
11921 0x1d7e6e7c, 0x13c000ed, 0x2bd393d2, 0xfbd33f4a, 0xa02e9455, 0x32f4cdb7,
11922 0xf40537bf, 0x2fd608cb, 0xfe502de4, 0xe40f697e, 0xf56fbd15, 0x5e2a1e02,
11923 0xf986e15a, 0x19aa909c, 0x60f53f9f, 0xafc746ba, 0x1ee90390, 0x8af3d92c,
11924 0xf21bfddf, 0xffb7c2df, 0x35e31d2d, 0xe0b2cb44, 0x82c8145a, 0x34dfce79,
11925 0x80b9e703, 0x2b0f90f8, 0x41cb129e, 0x91297e1f, 0xe4711db2, 0x93973ce4,
11926 0x71285b13, 0xd04f3ce9, 0x6df30665, 0xdb8311de, 0x87beded0, 0x37f83e80,
11927 0x316a173e, 0x1b4bfd60, 0x921bd7a3, 0xab5197ee, 0xb77f9633, 0x3a066dae,
11928 0x65a3ee9d, 0x15463ec0, 0x1f1c0291, 0xafda65c2, 0x0ca4f6f8, 0x4aa22746,
11929 0xba3bfc85, 0x73c097ee, 0xd659bf78, 0xef86f9ec, 0x8edce5c8, 0xf1f257f1,
11930 0xb049dc29, 0x8f489f5e, 0xb2aab76f, 0xbae807ae, 0x3167c31d, 0x7fe4cef2,
11931 0xde4c43eb, 0x4e0ff975, 0x0bf6832b, 0x823932ef, 0xa43d60ef, 0xb0324570,
11932 0x022ddf7d, 0x892b07ea, 0xadf393c4, 0x63739732, 0x285f99bb, 0x1c9092fc,
11933 0x4e3037c3, 0xf701d22a, 0xa7ac1631, 0xd1e8c7df, 0xddd7182a, 0x8e5d5fb9,
11934 0xd07d7217, 0x6407d26a, 0x8903d313, 0xae00aaed, 0xe0e54b7f, 0xfc824f33,
11935 0xa80d7952, 0x3972bf20, 0xfaf3ffcc, 0x84fdef03, 0x21e7cdca, 0x7a8d6e5d,
11936 0x15b72cd5, 0x7890473b, 0xd3b9fb72, 0x2dcae24b, 0x6e571e7d, 0xcfc82d9d,
11937 0xaaf5afff, 0x990cc78e, 0x0eeaf1e2, 0x327aea3c, 0x7acd3e11, 0xc6a4a772,
11938 0xeff493d5, 0x99d8525d, 0xd43e751f, 0x0bf16ff9, 0x1f417d95, 0xe754f945,
11939 0xea9f28c3, 0x5e29d87c, 0xb9a3c06a, 0xefb0effd, 0xdb62fc01, 0x7518f538,
11940 0x015e6d21, 0x338afee5, 0xb4afcc16, 0x5f70170d, 0x0906d064, 0x3c5b6feb,
11941 0x9d4ec023, 0xcfd5f63a, 0xbbbe467f, 0xcb7df07f, 0x3f3e2957, 0x6ec84019,
11942 0x5f046528, 0xc8e7a58a, 0xeab38330, 0x43f60908, 0xe589a0fd, 0xcff4fe31,
11943 0xbdf76665, 0x61cee1fa, 0xb6a2c780, 0xa82dc9c1, 0x9fa20737, 0xc8f5c559,
11944 0x0c9a80b9, 0x385cf5fa, 0x73c9fd0f, 0xbc574587, 0x38e7c6fc, 0xf8805f7d,
11945 0xb6db2d19, 0xf2915a92, 0x47691b5d, 0xd5b022bb, 0xd9c5b646, 0x9990aadf,
11946 0xf8a1fc9e, 0x3e03fa00, 0x94b7b39e, 0x73b1c796, 0xbbeb9dff, 0x81fffba9,
11947 0xe155e6eb, 0xa7b016cd, 0x316adaae, 0xeb9605c4, 0x0a405d7c, 0xeea7af80,
11948 0x0386bbb7, 0x5e8b0f1e, 0x0aad03c8, 0xe2f8a17f, 0xf9e68df8, 0x8f60ff43,
11949 0x707b2b3d, 0xd0e4d7dc, 0x6bc3c05c, 0xf6046d67, 0xb52b76d3, 0xf9c1e24b,
11950 0xb9c1852b, 0xcba318fb, 0xa297858f, 0x18a46736, 0x095b3de2, 0x3a676df2,
11951 0x73f3e413, 0x2ab82475, 0xb22de817, 0x68353d7a, 0x9414fbe8, 0xef838e5f,
11952 0x635ed12e, 0xc68af3e4, 0xf4082f1d, 0xc16165bd, 0xcbeda163, 0xf80516a4,
11953 0x4531aaa5, 0x54367d04, 0x3d5bf3d5, 0xe1896e43, 0x096567bf, 0xcc6079e7,
11954 0x5e03b76b, 0x08519fce, 0x076801e4, 0xf84f31db, 0xf218787c, 0xbd79a25b,
11955 0x275327ec, 0x410fd0ca, 0x71d3363e, 0xa1927d70, 0xd7c4b63e, 0x6a9ae00b,
11956 0x8de9596d, 0x1c01f783, 0x7c963fef, 0x5b765576, 0xe5d5df7e, 0xc79627d7,
11957 0x9d57ddf0, 0x9e2337e5, 0xa55f2efc, 0x97bcc066, 0x0065e537, 0x21bf973e,
11958 0x57c78cf7, 0xdf99fa2f, 0x03e79db8, 0xf95035b7, 0x7e4626bd, 0xc6fca81b,
11959 0xfcb61389, 0x22fbf2c8, 0x7b3c6fc8, 0x9757cf8c, 0xc7f0fcdf, 0x0df9bf28,
11960 0xca1e4316, 0xefaf9969, 0xe857e509, 0xd41a4b79, 0x8e23af65, 0x403c06be,
11961 0xdf3b739c, 0x40718007, 0xbbe5558e, 0xfc7ff1c9, 0xf978e58b, 0x3379822e,
11962 0xe4cde99d, 0x2a6ef978, 0x9dd002c7, 0x26f2f1c9, 0x9db9c72a, 0x275077e5,
11963 0x2fdf65f9, 0xabefb08b, 0x7b7f731a, 0x40af1d07, 0xfa36bd93, 0x3c87417e,
11964 0x6795888f, 0xcf204955, 0xcf27bb87, 0x533cb8bb, 0x8de7ed39, 0xd86f5743,
11965 0xdaf61f98, 0x2ff513e8, 0x41fe5f03, 0x6de9ff44, 0xff73b30b, 0x70c4fa38,
11966 0x00db8be0, 0x632fca1e, 0xfd5a1d39, 0x74bfec01, 0x9074c6cc, 0xb5839293,
11967 0xec3c81bf, 0x0132adca, 0xe1acb87d, 0xcd53f463, 0xbedd1771, 0x745fc732,
11968 0xc38e623d, 0xbd33a92c, 0x9dbe30a7, 0xbc20b626, 0x77a24fe4, 0xd3be1c5b,
11969 0xe704ebdf, 0x9cf7dae1, 0xece03bc3, 0xcfa42e2a, 0xf4b82ba3, 0x7c2b9579,
11970 0x864a1bbd, 0xe291bc41, 0xf025e511, 0xaa7188a6, 0x8601a2f2, 0x72b70cf3,
11971 0x16d58738, 0x62d84095, 0x80ebe41a, 0x9ee1b55f, 0x368fb043, 0x005aa8e2,
11972 0x31d8f566, 0x57f81f56, 0x51dbd9cf, 0x3cba759e, 0x3964f9c4, 0x5eb5e7ef,
11973 0x6fc0c5d5, 0x07828d55, 0xc8aa9dd6, 0xc6dcf03f, 0x955f8d81, 0x6a2d1f02,
11974 0xe4563c12, 0xf0142fc3, 0xfae94afb, 0x2c34fc0b, 0xbfda05fc, 0x448a9a8b,
11975 0x6ed17ef8, 0xbbe41301, 0xe9774fc2, 0xf7c396b6, 0x04efc022, 0xbad9db38,
11976 0xdbd3e1c6, 0x0180a4ab, 0x2f2792fe, 0x7066c9ae, 0x03b556ab, 0x785111de,
11977 0xaf388b67, 0xe3abc26e, 0x1f782bbd, 0xe3deb852, 0xb8d3fc74, 0x222f18f3,
11978 0xf96e94e1, 0x6e35df37, 0xd19a4555, 0x57e3d35f, 0x2adf455b, 0x6588e219,
11979 0xf38c6482, 0xfbfc63b6, 0x7fffe847, 0xf07fadbe, 0xdd74222f, 0xd3fd7dfa,
11980 0xcfb3ef88, 0xe8153c7f, 0x9135e4b2, 0x5a5d28d8, 0x82245deb, 0x054124fb,
11981 0x41b8b0e8, 0x240e30d4, 0xbba70a45, 0xc351f162, 0x85ddb1f0, 0x4ef1707a,
11982 0xfd32706b, 0x9f2bf17e, 0xd33d83e6, 0xa1fb40fa, 0x3c03886c, 0x931ca02f,
11983 0xec3e4b40, 0xd8962d13, 0xbf198dbe, 0x87c58511, 0xcc76eccf, 0xea107902,
11984 0xc5a9b9d8, 0x35b299a1, 0x557e1ec6, 0x641c5991, 0x15af3b37, 0xbcc04e78,
11985 0xf62f8031, 0x8f9e8edc, 0xe639e673, 0x946e2c97, 0x6afe7083, 0x568edd71,
11986 0x3e2c9b88, 0xad75c56a, 0x8c0beeaa, 0x7f6c96fb, 0x6aef9d91, 0x72fe0d14,
11987 0x4eb53f27, 0xbfc1588c, 0x38c4a86a, 0x8c7fad3c, 0x0bf710f5, 0xb51fa3bf,
11988 0x2bd37b64, 0x25c28a01, 0xc6eb3f2f, 0xdbcd5873, 0xd6afe8dc, 0xa8dc7b7d,
11989 0x7a1a5f93, 0x53a5fb88, 0x97df804e, 0xcd3d2fc8, 0x62b4e4f9, 0x7aebeff2,
11990 0xe14abfa0, 0x638f2c2c, 0xfff947b7, 0x077f2fc5, 0x3b33d571, 0xc01dff3f,
11991 0xf39bf4bd, 0xe28fbbbf, 0x7bb5ec93, 0x3d560f40, 0x438c17ff, 0x5649dfe9,
11992 0x7b9fafae, 0xad78e316, 0xa17ab37f, 0x13a6d6b7, 0x6ac71039, 0x748ff1dd,
11993 0x365653b0, 0x6bbb424d, 0x0c92aee5, 0xd04ec712, 0x60dfe04b, 0x6688e237,
11994 0x38681dba, 0x9e700390, 0x748774a5, 0x21bc68be, 0x38e2c954, 0xd4338f2a,
11995 0x76db8fc7, 0x4c342b8a, 0x70fc69bf, 0x4aaf6528, 0x785f11ba, 0x9af3d297,
11996 0x9eb1d06e, 0x534291c7, 0x70be35be, 0xe941fe16, 0xc6356795, 0x986cbe17,
11997 0x424f9fff, 0x848f435b, 0x374885f1, 0x85c7a7f0, 0xdf2d14db, 0xf3b9720a,
11998 0x00eb8c05, 0x09d326fd, 0x65f8beb7, 0x4fd5c40e, 0x6177edca, 0x15935bbe,
11999 0x3717d7f7, 0xa9e515fd, 0x68dbd775, 0x9f1e127f, 0x3fd1256d, 0xb9e34716,
12000 0x5d5b55aa, 0xe9c12e2c, 0xd50b7100, 0x7c79cf8d, 0x1eb5f182, 0xaf1448b7,
12001 0xc7ed6058, 0x5c594ef3, 0x07eb72a5, 0x83c5310a, 0xeb1d5184, 0xe97a227e,
12002 0x1e00f078, 0xe3c6c646, 0xa287c7e2, 0xdd1338f1, 0x87109e80, 0x68dbc68b,
12003 0x5dc437bd, 0xe35fc282, 0x375b77c5, 0xab5e38b3, 0xe95bcc6c, 0xcf8b13a0,
12004 0x5bd136cd, 0xeb576f9f, 0xf8f35756, 0x069a78ae, 0xcecf768b, 0x29733af8,
12005 0x6d5f7ebe, 0x3ed87e15, 0xbcc13ceb, 0x7c0353ef, 0xb1f0d959, 0xfa8d7902,
12006 0xf7cfa6fa, 0xcfcfb70c, 0x5e622f3c, 0x01d09aee, 0xfd66efd4, 0x61ce0cb1,
12007 0x37f781c4, 0x8d65de1c, 0xb338fd6c, 0xd27415d3, 0xdfecce7e, 0xacbd7c8d,
12008 0x402563fe, 0xf7543bfb, 0x49fcc2b2, 0x7eb04726, 0x3fe06304, 0x7cbed2f3,
12009 0xfe647f16, 0xad9c7980, 0x85563f5c, 0x55538fe3, 0x9c6185ff, 0xc2908125,
12010 0x7dbfacf2, 0x3692d3bc, 0xdd3bfa13, 0xb3c8132c, 0xcb121d3c, 0xae6bede2,
12011 0x5f7ccab5, 0xb9c596b3, 0xe78a3ae9, 0x9cec5c5e, 0x60aa988b, 0x6ba5641c,
12012 0x5f3851d4, 0xa8a5d2b9, 0xacd51fe0, 0x35bcfb62, 0x0266f73f, 0x6e526bbd,
12013 0xad6d78c5, 0x349ebf09, 0x7f9c114f, 0x1f2c4cf1, 0xd66aec0e, 0xc59a293b,
12014 0x574aff00, 0xe14a8659, 0x81fb4d5c, 0xf244a8f3, 0xd11c39e2, 0xf3065a5d,
12015 0x8f163d11, 0x4c7c4e3d, 0x5f139676, 0x8f645e0c, 0xb90cdcf1, 0x7e854c34,
12016 0xa5d9fdf4, 0xd843e6b6, 0xe004d1e8, 0xc7ef892b, 0xc1e2dd17, 0x0bd5b779,
12017 0xaa71605e, 0x3a4f559e, 0x758033cb, 0x72676da4, 0x3f06b93e, 0x5f5d1a24,
12018 0x50b9fc1c, 0xe81f6fbf, 0xa26ed5a5, 0xa33950a5, 0x3cc55558, 0xd4343f38,
12019 0x9f01e426, 0xd7c7f17e, 0xb0f6bf68, 0xa0352048, 0x19e7a9cd, 0x67202969,
12020 0xe608f20e, 0x5f2b0093, 0xa701d1ee, 0xc084cf39, 0x97e7312b, 0x8c4e8927,
12021 0x24db9c7f, 0x922b9fa2, 0x8e3b7eab, 0x0824edf9, 0x65f5f3f0, 0x1cf38709,
12022 0xf0231175, 0xe30bbd7e, 0x98df0bf3, 0x7403f28b, 0x8f57c588, 0xb91fa332,
12023 0x87ceeec1, 0x768d9dfd, 0x492816f7, 0xbc866b40, 0xdfbc79e6, 0x73c6e59e,
12024 0x030c5448, 0xe7ce7f60, 0x82f9faf2, 0xaf98c3d2, 0x7a805be0, 0xf196633e,
12025 0xbed9929c, 0x1fb50897, 0x0a0d7d61, 0xb38908de, 0x19b8dfaf, 0xdecaeee1,
12026 0xb0e8f1d7, 0x3909bd51, 0x04e24e42, 0x97d6263c, 0x65b7e05d, 0x0dc76fe0,
12027 0xb5f8eeff, 0x6bf11a66, 0x75f88d57, 0xcfe3320c, 0xd7975f88, 0xe6ca2f88,
12028 0x6fc36fc1, 0xb9e328f2, 0x7e157faf, 0x1db8d987, 0xff4af1c9, 0x4ce96dca,
12029 0x59dc0365, 0xc2e50452, 0xced9472c, 0xeeff0088, 0x855c1693, 0xe85d795f,
12030 0xf9f264af, 0x77d8f308, 0x1123900e, 0x1ca2f5e0, 0xd00bc9c1, 0xa1f20ef3,
12031 0x2169e807, 0x57cb929f, 0x8ae7a627, 0x9e3f0769, 0x04dabf43, 0xf20d7bfc,
12032 0x955f3b03, 0xb935824a, 0x0f5ea720, 0xbf21dfac, 0x864f3bcd, 0x3bc4f673,
12033 0xaf9c006f, 0x68f960f7, 0x6dbf7b01, 0x1a73c130, 0x7485c8a1, 0xf3554fd0,
12034 0xbfe83949, 0xa9f69547, 0x6cbef7e0, 0x1bbdf167, 0xd3ea0aec, 0xae16eda7,
12035 0x71be2757, 0xb6c7952d, 0xf9c2acb0, 0x36f0b6c0, 0x37a800db, 0xbd6e788a,
12036 0x4af6a52a, 0x2c35bf18, 0xd9e6b833, 0xbfc00382, 0x3d71926f, 0x0e379d68,
12037 0xed44c1cf, 0x4fdb30b7, 0xea7f0b6c, 0xcfa31b9e, 0xb89f1b5b, 0x1b0fe212,
12038 0x31f7f12d, 0xdf2cd857, 0xae8d7fcb, 0xf29d0dbf, 0x58d8562e, 0xfda3c75e,
12039 0x4d963ce8, 0x61d7c73b, 0x39630f26, 0xb82e0f9d, 0x2bbfe701, 0x3a7cfd4c,
12040 0x8ef1528f, 0x79d0871b, 0xc48bfe8e, 0x26d12bf4, 0x47674ecf, 0x1afde080,
12041 0x5fa82fd0, 0x0e2cff6b, 0x44a0b887, 0xf0c45ce0, 0x6fe805ea, 0x7ca6e6bd,
12042 0x50a2f94e, 0xbe030d0b, 0xc14e189d, 0x3eaa0a7b, 0x8fd76824, 0xfc0c9668,
12043 0xd5d7c859, 0x9f1616c2, 0xd8d4791f, 0x3245ba3e, 0x8c4141d9, 0x693d8f1f,
12044 0xf3ab5e7c, 0x03a49bb9, 0x24bfaf9f, 0xd517900a, 0x0fbc4ed6, 0xe6dbb850,
12045 0xda3842f5, 0x2b29c02e, 0xcb125e5a, 0x9bf7ade2, 0x6b0f2c6d, 0x9d7042a3,
12046 0x89c0b8d9, 0x17fb08fb, 0xeb3cc62c, 0xebe67eaf, 0x5edcef1b, 0x664a7e8c,
12047 0x325af5fb, 0xbdfc0519, 0xaf78605a, 0xb7dd8acd, 0x9f9d4bd2, 0xf9d6fe75,
12048 0x92416b3a, 0xcbde5e2f, 0x7bb33b60, 0x120c178a, 0xf6d7f014, 0xa9fc780a,
12049 0x219f01f5, 0x065cdb7f, 0x00d903c8, 0x79e3554f, 0xe16dbbb4, 0xfb5479f8,
12050 0x0fe66e6d, 0x0558103e, 0xa53f1e79, 0x327a09c2, 0xd1ebbf71, 0xa083aadf,
12051 0xab677c2a, 0xa6e78d9d, 0x16c8dbe6, 0xb54ad388, 0x80bb3759, 0x5fae4bff,
12052 0xb27de143, 0xebeb82dc, 0xf08bd946, 0xc1092a07, 0xa73f03f8, 0xd92a7bd5,
12053 0xec7e7b1c, 0xa8e8ad88, 0xa8f7ce8d, 0xeef383cd, 0x000af3e1, 0xffebf7bf,
12054 0xa6bb06e3, 0xe915a2ed, 0x43fb8bd8, 0x6de777fa, 0xd80f4f0c, 0x7be077b5,
12055 0x72869152, 0xbdb9f5e2, 0x39c186f3, 0x18f78a55, 0x5fa0ea39, 0xea91e700,
12056 0xc28e3aa3, 0x20b4ea93, 0x534d125f, 0x031e7a3d, 0xc8c5efe1, 0x04088905,
12057 0xbd741cf2, 0x8885842a, 0x70c1ca8b, 0x7e02339b, 0x9d056a47, 0x4ec10537,
12058 0x66bfac6c, 0x1cf44ce9, 0x5251e61c, 0xe4842cbe, 0x12798279, 0xfd05a890,
12059 0xd756faeb, 0x0853abd3, 0xc7eacbca, 0xed0d60a4, 0x62d49367, 0xae4af887,
12060 0x56c316a6, 0xe2a4aa74, 0x153ebcf9, 0x1c73f304, 0x44a54f79, 0xf42a16ed,
12061 0xef11bf43, 0x1fe7178e, 0xe5f1d76a, 0x2be027fb, 0x7efb70ff, 0x76bc6f30,
12062 0x75f79e36, 0x51e9da1b, 0xb1edc1fd, 0x8efebe52, 0x2bed8cfe, 0x24b5c893,
12063 0xd66f8e36, 0x327dba1f, 0x03cb7c7a, 0x6feef80e, 0xadda4e0c, 0xe08ddf06,
12064 0x13ea8df3, 0x0c8e6ebe, 0xbf427d53, 0x3b0f082f, 0x82eef100, 0x771c990f,
12065 0x038727d2, 0xfbefe022, 0x5f3311ea, 0xb9508d0c, 0x5583ede4, 0x89ecbf38,
12066 0xafbda1d6, 0xd277a8dd, 0x40cf0da6, 0x9bf3973b, 0x7cbacf19, 0xe0bee59b,
12067 0x2b01ef5e, 0x60910b83, 0x1d08871e, 0xa079a870, 0x60888e97, 0x5115b7ef,
12068 0x0eb8503c, 0xb94bf972, 0xe61ebc10, 0x9d7c3ebf, 0x7be4e41d, 0xfa1127af,
12069 0xf27c4c75, 0xde37d171, 0xdcf8f2ce, 0xfb658780, 0x24f5f02e, 0xca8ef482,
12070 0xd8939501, 0xffce8978, 0xe5d77e66, 0x3a0e06a3, 0x0bf9e1e7, 0x28aceb02,
12071 0xbdf0f084, 0x00f26c95, 0xbb7b755e, 0x24b7db86, 0xdff68590, 0xebe10f4a,
12072 0xf8104e51, 0xedd646a4, 0x362daf75, 0x55d2b53e, 0xfb6df19c, 0xa9175535,
12073 0x8793167f, 0xa3b5255d, 0x517556ff, 0x1bdfe7c1, 0x450a617f, 0xf37f01ba,
12074 0xe33b3ded, 0x57c83c6f, 0xe62fffcf, 0xbf3ccab7, 0xfcc76ab5, 0x6bdf12c6,
12075 0x147f542d, 0xe35758ae, 0x7793f150, 0xeb3b0b33, 0x657cfd05, 0x96603d22,
12076 0x6b4b91f7, 0xb498600f, 0x72af790b, 0x3212fc70, 0x98d9f41d, 0x725bb508,
12077 0x05ffcb3b, 0x072abf3e, 0xaddb7bc3, 0x9e4103ed, 0xdfbe8856, 0x16a811d9,
12078 0x8aec058b, 0x1eed04dd, 0x6e63beef, 0x1ee6f794, 0xb3a7f586, 0xf660105d,
12079 0xf4475f26, 0x48d0a7b8, 0x738e80e5, 0x0e7beec4, 0x30f1affa, 0x340e14bf,
12080 0x623a7e81, 0x5e03d5f3, 0x24c6141d, 0x28324f38, 0x28e2cb92, 0x25dc8311,
12081 0x49873392, 0xde74428e, 0xe805aeb0, 0x484036ba, 0x7b02cf0c, 0xd502230a,
12082 0xf4b7602e, 0xb06c242e, 0x06f30465, 0x7bb3e77b, 0xb0177a00, 0xb4dec77b,
12083 0x5bc938b3, 0xcbd11d7c, 0x03f2b623, 0x912cbf00, 0xfbe0b580, 0x42a00dc3,
12084 0x5d88f17c, 0xb27807db, 0x8f386995, 0x0af10f6c, 0x52d98e94, 0xad7d8048,
12085 0xc0aaa5d4, 0xad848ae2, 0xfed25043, 0x45ab27b2, 0xfeecf740, 0x6509cf04,
12086 0x4713fd83, 0xe5d98e6e, 0x6b07161f, 0x1f8764ec, 0x487172e3, 0x31edf3a1,
12087 0x473fe599, 0x7c1439e3, 0xebab6fc0, 0xeb6c9c56, 0x225f2c97, 0x6cf0c290,
12088 0x6080cbf6, 0xd7892f30, 0x6488541f, 0x29bf454f, 0xb0197c00, 0x726fd0d8,
12089 0xef086f10, 0xc7ea4949, 0xbc1145ee, 0x2bfea0eb, 0xf706dda9, 0xa0f2e825,
12090 0xe3a3f9f3, 0xf44af66e, 0x73f8f755, 0x52d3e0f9, 0xe027ff7e, 0xb9dc75b9,
12091 0x2671ab81, 0xef8c39ed, 0x6790d134, 0x51afd3a9, 0x0ecfd036, 0xfd5892f1,
12092 0x810652ed, 0x242ade3d, 0x6a5fc179, 0x7830245d, 0x43cf1b05, 0xccf30c95,
12093 0xa33f3074, 0xfec5eb8d, 0x0f38b949, 0xf3a09d7d, 0x5d71875b, 0xe7a23cd3,
12094 0x8ce74c8e, 0x3290e7cc, 0x9df1a2f3, 0x2b07cc2c, 0x184ee057, 0x40ec2e72,
12095 0xddcaacfb, 0x9ce2439e, 0xb168c993, 0xa6073dc7, 0xfd6f1497, 0x5e427a92,
12096 0xe80a7561, 0x993b8cd9, 0xa3e3307e, 0x3d0c084d, 0x7f63fb04, 0xa3eee390,
12097 0xe66665eb, 0xe8f3298d, 0xd75999fb, 0xdf3fa963, 0xc6e294e0, 0x0925c70b,
12098 0x0c8fcc3f, 0x18df3cb2, 0xf3071dfe, 0xe77beb39, 0xbfc50d3d, 0x1be9e31d,
12099 0x37de1892, 0x6fbc3124, 0xaa7c7450, 0x1d7f20c9, 0x5f21af75, 0x96dfbd62,
12100 0x509e4122, 0x73e50b20, 0xbbd187be, 0xed0d7de3, 0xbb449e96, 0x125036fe,
12101 0x0db265eb, 0x7dc59ef9, 0xdfe0bcf4, 0x994b9ff8, 0xdba7ed48, 0x8d505f38,
12102 0xc29be8c0, 0x7eb0bee0, 0x4e9b8e12, 0x1481da2d, 0x2dca0bcf, 0x9d07885e,
12103 0x1bbef39d, 0xc9cdc88e, 0x78242e6e, 0x0d7ab5f4, 0x157f73f8, 0xd125b77d,
12104 0x5036d27e, 0xf183d545, 0xa525c805, 0x8fb8f5d3, 0x3712db39, 0xc497cfef,
12105 0x925776fc, 0xccc8e107, 0xea748a9c, 0x014e4fa8, 0xa7ccc37f, 0xe6b35e54,
12106 0xb738ef0d, 0x1166f946, 0x6f2cd9e0, 0x1469326d, 0x208add70, 0x7674d2be,
12107 0x975b7ae6, 0x43903497, 0xa72a8fd8, 0x73a7547a, 0x3a6afe3f, 0x4ff13bc6,
12108 0x1ffeff08, 0xc7b847e0, 0xd45ea317, 0x620c88e5, 0x7a0ede7a, 0xd9ce2637,
12109 0x3ed7f4d6, 0xd1f89fb0, 0x60bbcfcf, 0x52efe93f, 0xecf40bbb, 0xecfffbc9,
12110 0x8f863c82, 0x8ef167ee, 0xd7fe4cbb, 0xff4c4923, 0x5e54947f, 0xdbbaf303,
12111 0x2fa175ff, 0xbdc95f86, 0x51645f6c, 0x6f9d3450, 0xae379e34, 0x17cf990c,
12112 0x95df1007, 0xfd78fc52, 0xe71624fe, 0x59bf5459, 0x7c6156c9, 0xae81afdf,
12113 0x797fb927, 0x03dd81b2, 0xa733c3a2, 0x3e02a87e, 0x56c3dfd7, 0x2cdeafbe,
12114 0x9b43f5b3, 0x3e62fb0c, 0x9c33378e, 0xa4fdf887, 0xa22d7ff3, 0x8e9b33df,
12115 0xc3d52f75, 0xf3cb30be, 0xfe63cf35, 0x9c296a47, 0x90ff9fe7, 0xbc34fe80,
12116 0xcf5d3f7f, 0xc5aef77c, 0x3cf333fd, 0xa08fdf3b, 0x90b5dfa1, 0xce7cdbd3,
12117 0xed98616a, 0x3e23cf6f, 0xf94ecf94, 0x0f966118, 0x9e238e6d, 0x00e79c3b,
12118 0xf126343c, 0x3242ab7d, 0x762ef212, 0xfc97ee1e, 0x675ef96d, 0xd3f2b9f8,
12119 0xa4f44f3c, 0x9359609f, 0xdbf3b2a4, 0x814bb7e1, 0xee3596bf, 0xbe657bc0,
12120 0x0caa3eab, 0x84ff729f, 0x6a25e874, 0xe811fe5f, 0xc1827c48, 0xf9b65cee,
12121 0x65fcc2bc, 0xf83b9f86, 0x1f003bf3, 0xeececfb8, 0xa963b90f, 0xdef6217c,
12122 0x8c92f799, 0xa267ebfb, 0x3cd9e4e7, 0x93bef92a, 0x5f333f3e, 0x9b3e70d7,
12123 0x9ada75b7, 0x35ca745e, 0xf872274d, 0xfbcc0779, 0x2166f9d6, 0x8acd2f29,
12124 0xbd3a1fc3, 0xfe107ca2, 0xd3abc225, 0x6ced5e69, 0x2640af3e, 0x84cbf7df,
12125 0x2f9992b8, 0xd76f3aba, 0x80e4b72a, 0xdee99abc, 0xfb3ce09a, 0x3ed893df,
12126 0x2b553ced, 0x9f38bd05, 0xc4f1af94, 0xa5272bd8, 0x81f743da, 0x7c656d1c,
12127 0xe06bd51c, 0x7ebe82bc, 0x7cf5c64b, 0x80cd4bb9, 0x1e90917b, 0x87615e70,
12128 0xe9ef0035, 0x6bf71ce3, 0xf0197f5a, 0x69e5865d, 0x7fd6b97f, 0x82fb4740,
12129 0x10dde78d, 0x441b6dc7, 0xead3be30, 0x71ebc232, 0xc78f0888, 0xa5bbd6c1,
12130 0x1f37f352, 0xdada0e80, 0xc711f98c, 0xd0f8f12f, 0xbc596b25, 0x10ed5e79,
12131 0xdd05f70c, 0xf74ae5c5, 0xf4e6ee3f, 0xf6cc2bbb, 0x9a6ce7bd, 0xdf30f486,
12132 0xfb847267, 0x041bb32d, 0xfa6623d4, 0x775ef7cc, 0xdcedf40a, 0xdf7e1160,
12133 0x11e45e89, 0x6e99bba4, 0x761e1deb, 0xad548dbf, 0xc73f7dc0, 0x4fb80937,
12134 0xde8124b8, 0x8f0777fb, 0x3e737767, 0x822479e6, 0x55d6e17f, 0x98117a6b,
12135 0xf80550ff, 0x3ebf0cdc, 0x6344f9ff, 0x37cf877a, 0xcb48bcd1, 0x829f2cb5,
12136 0xc28be3af, 0x65a97eec, 0xaf2c888f, 0x748bc793, 0xcd7875f8, 0x971528f3,
12137 0xdb6f3e62, 0x09f31106, 0xd7040aef, 0x77cbbdc0, 0x3d7016ad, 0x5d27444d,
12138 0x32fbe84f, 0x63671acb, 0xf68f957e, 0xdb697603, 0xd9170487, 0xde0275b6,
12139 0x9e90937f, 0x94579661, 0x30849e88, 0x74a3cdba, 0x7e6e387b, 0x3fd6915c,
12140 0x78273f76, 0x763fd6bd, 0x3084897f, 0xdd4964af, 0x4af3c334, 0x774f5187,
12141 0x3aa47f25, 0x2e9cde7e, 0xe9fcba6f, 0x9c1eb8f2, 0xa51fb073, 0x5ceca1e0,
12142 0xe863cfc0, 0xfbfd50af, 0xff8b0773, 0x7d1b7a3c, 0xf3c6d965, 0xf984fd86,
12143 0xe6bd18a3, 0x79f1938b, 0xe28375a2, 0xd787a0c1, 0xf87a8c3a, 0x9f47ce87,
12144 0xfa272e87, 0x6272ccfc, 0x0f4cdefe, 0xa6670e3d, 0x001e998b, 0x470df827,
12145 0x07c11c9a, 0x04479c28, 0xc9a07706, 0x66b7708e, 0xfe706896, 0xedd65966,
12146 0x0f811e58, 0x57bd8347, 0xed038cfe, 0x7957ee56, 0x4503e7e3, 0xf76e25ed,
12147 0x41961988, 0x93111e30, 0x2ec790bc, 0x77aa5b66, 0x7d8a79d2, 0xd2183969,
12148 0x9c22bd99, 0x992daee7, 0x143dc220, 0x77bcfc35, 0x379d858d, 0xc3dbfbd3,
12149 0xed97a0f1, 0x8046f28e, 0x9a9fece7, 0xfe2c1d0b, 0xce0afe8c, 0x143dee13,
12150 0x760dbfa8, 0xf304ebf0, 0xc8d20b69, 0x83b7a001, 0xee40a368, 0x72a4743f,
12151 0xffed9c3b, 0x286cbfd1, 0xcbcb56bd, 0x3f9097aa, 0x49b3e2fc, 0x37b25f70,
12152 0x9722b2d9, 0x38e2ffd6, 0xb9ee093d, 0xce5b66f3, 0xfda87ae7, 0xd59cf8ed,
12153 0xef9cb6af, 0x737feb47, 0xd875619c, 0xf87b82a8, 0x0527671c, 0x1e38c306,
12154 0xb5eae7a6, 0x243e41ab, 0xa597f30b, 0xc3c60afd, 0xd5fdfdf5, 0x17e0e694,
12155 0x79f9c87f, 0x17e2aacd, 0x2c67101c, 0x6fd854d6, 0x71be0ade, 0xea5fefcf,
12156 0x161d1578, 0x4a0367bc, 0x1ca7ffc0, 0x485d3a9f, 0xe4357683, 0x7690923d,
12157 0xb483ec35, 0x1dc77c3b, 0x91d87db4, 0x572009e6, 0x5fbcef0d, 0xf68df788,
12158 0xa30cfd65, 0xf3a6e20c, 0x9f6afb39, 0x8afbb1cd, 0xcfa28eed, 0x0c943e81,
12159 0xaa084768, 0xed41dc87, 0xa88d1a86, 0x31f81e4a, 0x81bdbb46, 0x49d7d9f3,
12160 0xcf91e7e5, 0x9f50477a, 0x7df0e53c, 0xfd9be305, 0xda9cd211, 0xf253fe2d,
12161 0x7af8c5ef, 0xd1e3766a, 0xff9f2039, 0x0afdcec5, 0x7af9869a, 0x9ef7a3db,
12162 0x1df7f410, 0x710bc924, 0x9925e236, 0xb71e7481, 0x4abe30b0, 0x4bf18c2b,
12163 0xf7e87cf8, 0x951ee113, 0x1fb60e91, 0x8227e74c, 0xa894369f, 0xf8830e58,
12164 0x9ab01e43, 0x487beb0f, 0xb47de8e8, 0xccedc7ff, 0x11d5b7ef, 0x84675c43,
12165 0x7707d993, 0x275c58b9, 0x0cdd0e49, 0x0be93dfa, 0xdefd01e2, 0xe12294f6,
12166 0xb9e4a67e, 0x0e39f711, 0xf82e3059, 0x40f41cac, 0x4afdbd7c, 0x3a42dd49,
12167 0x74e36bfa, 0x5c7dfbd7, 0x7884af51, 0xb3175cca, 0x222d9e27, 0x7edaf798,
12168 0xfec2094a, 0xadb66a57, 0xcf4fd63a, 0x4faddfe7, 0xa4e41e2e, 0x8929a865,
12169 0xf723f8c0, 0xd2928352, 0x02fa85e3, 0x76c5f03b, 0x43c511c0, 0x0f73d5aa,
12170 0x9e7a97f4, 0xcf8b9bc2, 0xa4afc435, 0xf8a64d0e, 0x5383731d, 0x9e297b85,
12171 0xc06e87b5, 0x2d17bf3c, 0x76d3ff78, 0xea0d3bc5, 0x1ea9cfdb, 0x9b3d0788,
12172 0xf9c24a1b, 0xf9c168bc, 0xbf6a4f6c, 0xfb85396a, 0x8e2c41e1, 0x64883920,
12173 0x2a79054b, 0xcfa1ef56, 0x7d993bc7, 0xe4c2dabb, 0x62a9daa9, 0x8e8171fd,
12174 0x15ef005f, 0xf9e91ca1, 0xeced6d17, 0x5bcf471c, 0xe7e0459a, 0x3fba69a4,
12175 0x0fc1111f, 0x704e571f, 0x94e71d5d, 0xad3a2a83, 0x2176739a, 0xd6ceffdc,
12176 0x2e1f098d, 0x29f2cc9d, 0xefc2efbd, 0xf2701c21, 0xbef836fb, 0x4f9cb5d0,
12177 0xd11693c6, 0x5fc7db46, 0x2e48de24, 0x8c6af7dc, 0x5a633edf, 0xfef127e7,
12178 0x44cf76b5, 0x8c445c78, 0x0da4f0eb, 0xae20a7a5, 0x09344c5c, 0x66c4a9f8,
12179 0xdcf5876a, 0x9ac4f70d, 0xf273c9ee, 0xe4872b75, 0xe8fde6c4, 0xe249fb71,
12180 0x47688de0, 0xc05e2994, 0xf6a70ecb, 0x0d4fd857, 0xdbf2f750, 0xf8cf3de2,
12181 0xa0d67e59, 0x57020e8b, 0x74fe50ff, 0xdaae7cc2, 0xd3b01b50, 0x9fd55f79,
12182 0x087c0ff5, 0xa78ae5fa, 0xbe807ad2, 0xe97a7377, 0xc077cea5, 0xc6649e5f,
12183 0x3a6b9e5f, 0x273ef3e4, 0xf2e89b8b, 0xfd077c06, 0xb78391ec, 0xa41fdbc7,
12184 0xf01f7afc, 0x41270eeb, 0x5917fa7b, 0x672059b6, 0x9dfb38fa, 0xe5cdff8c,
12185 0xf7cb559a, 0x0412efc1, 0xc6eb64be, 0x31175ec4, 0x6eba2e4f, 0xab783327,
12186 0x53e9dad4, 0x29c76f21, 0x3a4e5e63, 0xcb16373f, 0xfc31592f, 0xab5df3a2,
12187 0x3adff993, 0xfeec94ff, 0x284b9e33, 0x06fa92f9, 0x376a24b9, 0x2133fcea,
12188 0xb37dc110, 0x89d98409, 0x99d9fe66, 0x2e8a7f80, 0xade812a8, 0x9873fc4e,
12189 0xbe224ff1, 0xb048fda1, 0xe7f99a0e, 0xe3b72719, 0x25cff212, 0x6569e037,
12190 0xeeb7c953, 0x8dfa34ef, 0x72e67cf9, 0xbe7e23b4, 0xef1c67e7, 0x1bda95bb,
12191 0x4c6f41f3, 0x2f4178b1, 0xbec8ee50, 0x3bbbc299, 0xb5d7bf49, 0x3bea0f3a,
12192 0x7687a624, 0x87a8ad84, 0x3e7d3876, 0xb2658b8c, 0xf24474f3, 0xb6fe40b5,
12193 0x8d4d97b7, 0x7efb27bd, 0x39218fce, 0xd804fa32, 0x3e306f45, 0x00a53518,
12194 0x5921bc6e, 0x185e98f3, 0x0cd9527e, 0xd0b28fbf, 0x9386f455, 0x74067fbe,
12195 0xc753ac07, 0x60b7bc14, 0xf50531d9, 0xdf7babe3, 0x93b8852e, 0x723a179e,
12196 0xc5a5dbcf, 0xc67de183, 0xfd736f6f, 0x6531d7aa, 0xe9a5f41e, 0x84d1d85e,
12197 0xbdf331e9, 0x47c0e5ae, 0xe6ed1df9, 0x49434efb, 0x933d2e2c, 0x0e9bb2a8,
12198 0xf958fd31, 0x885d7083, 0x99d3def9, 0x4fd01b91, 0x5f5de5b8, 0x394f7bfc,
12199 0xdfef987f, 0x77c93afc, 0xf95fe61a, 0x985ef342, 0xbad95102, 0xafaa521d,
12200 0x579ef766, 0xe93f01e7, 0x147f8872, 0x068fa17f, 0xf5ddee19, 0x11e8f5f2,
12201 0x7beec4af, 0xbf705168, 0x7d8497e7, 0x98ebe217, 0x40f4c5cd, 0x6e97cac1,
12202 0x55873807, 0x2e800768, 0xf9993bff, 0x1122bfd7, 0xcdd01e5b, 0x3a9c612b,
12203 0x2725ab24, 0x88f78e84, 0xce083e54, 0x99e9ed75, 0x5fc60c34, 0x5c39f2e8,
12204 0xed486f60, 0x91bbe187, 0x81860a63, 0x5d0e771e, 0x35d603dd, 0x570a6e1d,
12205 0x076736d9, 0x175c3a1c, 0x742cbf39, 0x7ab876cd, 0x2f40efb2, 0xdc7c7e35,
12206 0xfcebdf06, 0x82fa6a10, 0x5f0c41f1, 0xf0741f00, 0xd4377085, 0xf1a43c75,
12207 0xd8ffaf52, 0x97fba17c, 0xf805f25d, 0xc5efee8f, 0x715c4317, 0x73da82f8,
12208 0xd9b9e1c3, 0x2c290b9e, 0xfcfccccf, 0xbe114729, 0xe60855ef, 0x76bd9089,
12209 0xbe3bbbf6, 0xbf2f8c14, 0xb66361ec, 0x073c747d, 0x5ceb957c, 0xf90e4ca9,
12210 0x2343df3d, 0x439fda02, 0x03b8a2a9, 0xa8debced, 0x7f1cbd27, 0xc020b8e4,
12211 0x4b985dfd, 0x68760d9c, 0x6bd807a4, 0x2393ad43, 0x1d3b0f20, 0x7ec1b213,
12212 0xcb8c702c, 0x32bff983, 0xb05be568, 0xabd2bda4, 0x6aade5e2, 0xeba57d87,
12213 0x5bbc03c3, 0x5d5bfc7d, 0xd5ae3f8c, 0xd010f9d8, 0xe870b1eb, 0x099003eb,
12214 0x332210e0, 0xa81d972d, 0x142dc3c7, 0x1c02d76f, 0x04fb0f14, 0x43f600d2,
12215 0x2b4b4591, 0x67b03b01, 0xdb380244, 0x0391fe9a, 0xe1c9a771, 0x78051fdf,
12216 0x5bfbeb27, 0x96fee35e, 0xedd6ded9, 0xd0ffdd21, 0x228925ed, 0xa0abb742,
12217 0xa73c047d, 0xbdc0f4f8, 0x45beb0e0, 0xf53e786c, 0x95ea73f1, 0x8967971a,
12218 0x9f3263ce, 0x19a44dc7, 0x2e9722e1, 0xe9471e5f, 0x63e39533, 0x491261f2,
12219 0x427687ca, 0xfdc014a6, 0x4c902433, 0x15e299c7, 0x7c3127c8, 0x6328d373,
12220 0xa426fe1d, 0xd5d3f477, 0x6375e6fb, 0xffce29ac, 0x7ec3cb43, 0x4dfc6e76,
12221 0x3c173b3f, 0x90189fa6, 0x951dfd60, 0x7b03cecb, 0x2b0e1e18, 0x23b1d7f1,
12222 0x58c79e5c, 0x3ce1f25a, 0xff3dbee4, 0xff7375c4, 0x07be7f9e, 0x53e8e476,
12223 0xc63c8112, 0x2786a731, 0x28ebbee3, 0xef4af915, 0x06b3eab7, 0x49cf6107,
12224 0x87e87dec, 0x15da3c28, 0xcb0d9f00, 0xfe3cced7, 0xe177f404, 0xf3624498,
12225 0x5f154be4, 0x968f887f, 0x0ff17bf2, 0xd29ecc09, 0xfbf10fdb, 0x78b977a8,
12226 0x93d28e7c, 0x1ac4c7fb, 0x5429e743, 0x74172513, 0xc9ca75d0, 0x7e5253b2,
12227 0xdfc0fa67, 0x7e1f3a27, 0x57749e4b, 0xfb0e7ea5, 0x5eb62ef7, 0xc37f0392,
12228 0x35d70cf3, 0xfd8123dc, 0x48a65d7e, 0xaf7198b4, 0x1fa7a957, 0xebd8f713,
12229 0x07bfd932, 0x2a627b9e, 0x111e79e4, 0x2aac6531, 0x7cade3bc, 0x718b37a8,
12230 0xf19ba7cf, 0x1ef85d7b, 0x887ff809, 0x574dc99b, 0x8ab98fe3, 0x4035c9f2,
12231 0xc0ecc277, 0xc8e50142, 0x7bfddf4c, 0xcb47a3fe, 0x4ef8c4e0, 0x1d337f44,
12232 0x8c533b5e, 0xd15d21fb, 0x7bb7ccc3, 0x57033ce9, 0xd97aefc0, 0xd77f0048,
12233 0x83f583cb, 0xebac4cfe, 0xf4d55afc, 0xf3b00f74, 0xd49d3e74, 0xe8cdf183,
12234 0x20f44fdd, 0x997a0ece, 0x19b826f1, 0x75d976fd, 0x633bc4bb, 0x67f47d2a,
12235 0xa3210eba, 0xe4334806, 0x587394d9, 0x8a5bbe67, 0xf9e10976, 0x6df5e6ff,
12236 0x24c778a6, 0xdd5da750, 0x3a8b7f4b, 0xb9f75bbb, 0x95a91d97, 0x952c1d60,
12237 0xc63d3256, 0x1e1d78ed, 0x42ff9d33, 0x44fe11ca, 0xc0f999f0, 0x68aee70c,
12238 0xeb86b27e, 0xfb4f7e81, 0x72b9fef4, 0xe8799c6a, 0xd085b8f8, 0xfbaf38f5,
12239 0xdb8e71eb, 0x4fe7ffc8, 0xa013fc4e, 0x99bc9135, 0xd76e66e9, 0x0c2947f5,
12240 0x00658050, 0xee2193ec, 0xd2879474, 0x60d10a8b, 0x9db7ba5f, 0x379b1a7c,
12241 0xe40af93a, 0xf61e15b7, 0x2dbf112c, 0xdf1228bb, 0x93be0eb0, 0x00731f1b,
12242 0x6a96eddf, 0xf7f45e1d, 0x5324d5a7, 0xacfc4d3c, 0x073c16f8, 0x102162de,
12243 0xfe149b5a, 0x19c400e2, 0xcc128eaa, 0xef0e2f07, 0x3d3e012b, 0x9fa33528,
12244 0x908176d5, 0xceec62c7, 0x038d70c6, 0x34c6b2ec, 0x50e99e76, 0x9be4310a,
12245 0x7d33711e, 0xdcec78dd, 0xbb4e2d54, 0x79f8cc98, 0xf2d2d13a, 0xd74b3fe9,
12246 0x3f00fe51, 0xe30ba7b8, 0xef051324, 0xb76069eb, 0x9feec6dc, 0xf91a6b6c,
12247 0xb7851a7a, 0xd414cef5, 0xd71a9333, 0x84a1e3de, 0x0c3d7d08, 0x16cfb79f,
12248 0x7be85bbc, 0xeb17aaa5, 0xd172f3a5, 0x4df91bef, 0xa193e98f, 0xfd197afd,
12249 0x52e2499e, 0x6755e209, 0xf0028533, 0x2d08f727, 0xf2f7e0ab, 0x38d8d302,
12250 0x01e813c4, 0x933be9fe, 0xdfc50c7b, 0xfaf55174, 0x205dfc00, 0x56dff262,
12251 0xcfbf3aee, 0xce57db4a, 0x733f3010, 0x049b2792, 0x74a7f862, 0xbaf3829d,
12252 0x0c519c39, 0xccbd3d7c, 0xc22c4e78, 0xe519c9ed, 0xdd8c120e, 0x283c1527,
12253 0xedec87d7, 0x5cefe2b7, 0xe604c936, 0x0df9cba7, 0xce67df9c, 0x6ef861ea,
12254 0xa776611a, 0x7237572e, 0xfb81bbf9, 0xb2f9b7cd, 0x1397e30d, 0x81fd0f66,
12255 0x92044fb4, 0x3cb32794, 0xcdeda9a2, 0x2f0edeef, 0x8047bd89, 0x9071bc3e,
12256 0x9715efc9, 0xc8be46ae, 0xc780bc14, 0xfb635e29, 0xe74ca34d, 0x6bf24d14,
12257 0x20330fd6, 0xacec4a3b, 0x307d7427, 0x219449a3, 0x88a3341e, 0x62ed19e2,
12258 0x95dedda3, 0x949918be, 0x525c5f40, 0xa433041f, 0xb0f8be93, 0x8be97bec,
12259 0x32dba957, 0x36f5ca8a, 0x21f46f5d, 0x4c6f407d, 0x009feb12, 0xeba36a3e,
12260 0x1f0e35a6, 0x1e8eebe9, 0x72a52807, 0x0ce07a8c, 0x749e2fcb, 0x86048b31,
12261 0xa201c475, 0x25da847a, 0xd2f638de, 0x619e777e, 0x57aa23ff, 0xb912ec62,
12262 0x25db87f0, 0xaa3da893, 0xbd7c0014, 0xc252be11, 0x90a596e2, 0xc3f102c8,
12263 0x0e302fcc, 0x7f512554, 0xa7e7d716, 0xffa39e99, 0xe43b5212, 0xe8af6cc3,
12264 0x3c09e871, 0x97e6617e, 0x16f23c68, 0x3a42e319, 0x3e02949f, 0x116ffe41,
12265 0x2ba09f71, 0x37c7d1be, 0x14c44bf3, 0x5f92ea1f, 0x577ddcb8, 0xe6ed397e,
12266 0xa4fea1f1, 0x44f8777f, 0x5f9d0fe7, 0x9bcdebcc, 0xa25138a6, 0xb09fe6f5,
12267 0xbc4cf4de, 0x483ebcde, 0x95debd46, 0x992e735d, 0x6e89f9e9, 0x75773b0f,
12268 0xd8270ce5, 0x59921335, 0x6ebe817e, 0x1b5de345, 0xdebc9f18, 0x7d824732,
12269 0x1fd02aa6, 0xd0741db9, 0x5f3ac5e3, 0x60275b2e, 0xd732747c, 0x2c4dad5f,
12270 0x5135585e, 0x8fd1c20c, 0x4f63f092, 0x6fbb3ab0, 0x14efa746, 0xd24527ce,
12271 0xff7e093e, 0xe0af26f4, 0xc693b885, 0x35538de3, 0x668de301, 0x44d7b5bd,
12272 0x1fbce9f7, 0xbbe0bff0, 0x2084ca9b, 0xfd6693f8, 0xb322fd36, 0x53d93a2f,
12273 0xccd89f7c, 0x7326572f, 0xf497d0fd, 0x15da57fd, 0xddbf92a3, 0xefbfd0ae,
12274 0xb065ce8a, 0xc0ffa0a6, 0x3b0193ee, 0xdd7ce81e, 0x2dfb0945, 0x49da3649,
12275 0xfc14ce17, 0xfe4f7d0a, 0x3a1ef9be, 0x1aba7cf3, 0x17f750bf, 0x8fa0ffb8,
12276 0xcec4837b, 0xa7d79bf7, 0xfe23d72e, 0x775e999d, 0xb5e31b24, 0x3d745d3a,
12277 0x5cef09dc, 0x5ba2274f, 0xd75a7a57, 0x3d6aff87, 0xafaff7ad, 0x66b8fa23,
12278 0x7fc89dfd, 0x9af1f5d4, 0xdb8c16cd, 0xfa7ee78c, 0xfe3f1e78, 0x7ee7b705,
12279 0xdffccc99, 0x166d2fb6, 0x32436f58, 0xec0b27db, 0x69fc6273, 0x07665efb,
12280 0xbe2a5cd9, 0x6220a0f7, 0x11c1e47c, 0xd4d7d416, 0xf3061a07, 0x19098a96,
12281 0xbdbdfb04, 0xbd6f7ed8, 0x7d472914, 0x9c0895ef, 0x8c5d13d3, 0x1fdc1e1f,
12282 0x7ffa1db8, 0x968193f0, 0x474f8c1a, 0x1a5ec19a, 0x7ee12059, 0xc5558a59,
12283 0x936b7678, 0x6a3bef15, 0xf6bffddb, 0x97cfd0c9, 0xe52e0bc4, 0x746b26c1,
12284 0xc7f40abf, 0x0888f124, 0xed6d1cf9, 0x1b03ef04, 0x02522b37, 0xd278d97e,
12285 0xfffe035c, 0xc1e58518, 0x6cd4f19b, 0xfbcca75a, 0x2c4d255d, 0xc5c4a5ff,
12286 0xed3a5ff3, 0xefe33457, 0x04904f26, 0xbce90d6f, 0xc992f15f, 0xefd8e9df,
12287 0xd15fb04a, 0x77d1f4c8, 0x0318afdd, 0xde7ca034, 0xd701cba4, 0xbec1244f,
12288 0xed8576c5, 0xcdbfb577, 0x6993d3ed, 0x5d46e371, 0xdeec5fed, 0x7dc1a49b,
12289 0xeff9db23, 0xdbdeec6c, 0x13f3534b, 0xd2df9fbf, 0xd8d30c5e, 0x84b37f5e,
12290 0xbe3c73f9, 0x9a0b8d1b, 0x90e9cbf1, 0x6b481f68, 0xf5041cf4, 0xe7df7095,
12291 0xaae18a82, 0x5d4f8aef, 0x4f1fb66e, 0xb7ef80d2, 0x01a5ef1f, 0xdc79fb1c,
12292 0xbcf56bd0, 0xeec2f605, 0x7092e763, 0x54d1583f, 0x53da4ff0, 0xae765e6c,
12293 0x2841c992, 0xf610606b, 0xeff0f7ab, 0xbfb527b6, 0xec5a7579, 0xbfdb0e7e,
12294 0xd7d9cfd1, 0x47f30428, 0x3f961602, 0x0cdfc662, 0x3b938f0f, 0x2274faf1,
12295 0xbc62a9a7, 0x096f503c, 0x3f3057cb, 0xce4c3c97, 0xfdfe2fff, 0x80006684,
12296 0x00008000, 0x00088b1f, 0x00000000, 0x5bbdff00, 0xd554780d, 0xdceefe99,
12297 0xf26677b9, 0xfc999933, 0x4dc2fe10, 0x00908102, 0x7e100843, 0x502021d4,
12298 0x4540647e, 0x043abaec, 0xa1bf9085, 0x56d3ebb1, 0x4126e1f7, 0x27d3e08a,
12299 0x6796dd6d, 0x57067db5, 0x3b1254b6, 0x770704c1, 0x08a00ec2, 0x80a0db54,
12300 0x11dae3c2, 0x2486a229, 0xec56bb0d, 0x3befdd6e, 0x6664dce7, 0xecfa5c18,
12301 0xf8728376, 0x9cf739ee, 0xfbdf7cef, 0xb3739dfd, 0x330001d3, 0x68776e01,
12302 0xdb00d900, 0x8c802f64, 0xde0820cf, 0x16e91bf4, 0xd305d609, 0x7ae77688,
12303 0xa9dfe0a7, 0xce1a6ba6, 0x2cb0ef91, 0x7a448f35, 0x42d1e986, 0xc639e7a4,
12304 0x699e7a72, 0xf806e286, 0xba5bc867, 0xcfc00e68, 0x03875e9c, 0xd257e9d7,
12305 0x00194876, 0x65049366, 0x528ed859, 0xec373803, 0x65ac0152, 0x3c1daeb8,
12306 0xaa40174e, 0xd21b7405, 0x54fb360d, 0x1e95f1a0, 0xd11a4b6d, 0x87c43d00,
12307 0xa5039a39, 0xd336bed8, 0xbe00b304, 0xadc1fb4d, 0x1ef8aaa4, 0xc5a8ffbe,
12308 0xfb81ce37, 0xec46b7ab, 0x1ff6015a, 0xa40473ba, 0x6c1d7ed1, 0xcf2f25bf,
12309 0xc60285cb, 0x33ffe157, 0xf8c9655f, 0x75f0a6da, 0x2c940f7a, 0x64bf5c04,
12310 0x1a5f8a1c, 0x59994fd6, 0x416dcf63, 0xf49f3d00, 0x9095c9e0, 0xeeaa716e,
12311 0xce34f99d, 0xb6f267d0, 0x21fd4145, 0x69aa725f, 0xce51e90b, 0xc0e96d30,
12312 0x89874ef6, 0xac58bfcd, 0xb7903003, 0x8e0df51a, 0x5335bc81, 0x96fa4d38,
12313 0x4881b2e5, 0x9b7f5239, 0x871e7eee, 0x0f8198c2, 0xddfa471e, 0x3bdc4a07,
12314 0xc290be91, 0x502eb1e5, 0x7a4512d0, 0x363025ba, 0x9d397c82, 0xf7c92f3e,
12315 0x04c0969b, 0x2db4a786, 0xe4bf34e9, 0xca0ef801, 0x3d104243, 0xf16efb80,
12316 0x0216a680, 0x1ce7808c, 0x90004b97, 0x332af82b, 0x2560bad9, 0x8737deb9,
12317 0x1758d5cb, 0x1c856865, 0x3f82a7e4, 0xf5c0f837, 0xc1beb47d, 0x301f10cf,
12318 0x153971c6, 0x4857cfd8, 0xd33cd1f7, 0x0a321e50, 0xfff3d705, 0xa0b014de,
12319 0x3ff8fdfc, 0x325f2fd1, 0xc9897405, 0x2cfd6d3d, 0x33ad88f6, 0x9966ade7,
12320 0x9fe3ab31, 0xecd44c59, 0xbb543ca7, 0xf748ec02, 0xad462f98, 0x37f61d62,
12321 0x9cf91c6e, 0x7d9fde27, 0x8d30b7c2, 0xc7e2f7da, 0xffa783cd, 0x15fbe320,
12322 0xe5019010, 0xd09a2732, 0x31fe5a1f, 0x4aef3fcd, 0x77bff3fc, 0x7db167a4,
12323 0x5f51828d, 0x77227db1, 0x95a35eb8, 0x66f837af, 0xd3e10641, 0xa2d9466c,
12324 0x864d55fc, 0xa2bf6c0a, 0x3a003b9f, 0x0b38e2b7, 0x56adc1c0, 0xe3394ed6,
12325 0x84eb40d8, 0x269022b6, 0x35babc02, 0x1d86b597, 0x0f03394d, 0x7598d4c1,
12326 0x390dde04, 0xe5c7be0e, 0xe93a3d38, 0x5691f3a7, 0xd010284e, 0x5730e586,
12327 0x5d106bc8, 0xf079e906, 0x475b9a4a, 0xbbc9d67a, 0x4b4fb265, 0x98b409ae,
12328 0x14b4d9fd, 0xd30d26d0, 0x715c93a9, 0xb8f42cb4, 0x9e7f66cd, 0xf4f742e1,
12329 0x333ae2e4, 0xeee93ac4, 0x41f37151, 0xe8c4ff00, 0xe2d755f3, 0x67ee1213,
12330 0x0af55a46, 0x454657da, 0xe5fcdc41, 0xbbcbc66f, 0x091ebc0c, 0x8fbf765f,
12331 0xb3fbe3fc, 0xcc7f60ce, 0x2b488af8, 0xfbc547c3, 0x5ee7cff1, 0x6f3ba78a,
12332 0xc99bb7a6, 0x74fea613, 0x2e5fd67e, 0x5e27a74f, 0xe34b999e, 0x8ded99e5,
12333 0x7588e797, 0xe91af2f1, 0xe8c7978b, 0xfd71c9ea, 0xc594b763, 0x33bee3d1,
12334 0xbe7c6e37, 0x1747195e, 0x371658ee, 0x9aeb427e, 0xeee27a38, 0x2f8dc66f,
12335 0xf5c5540e, 0xf9abec97, 0x253ff48b, 0x9e3718d8, 0x1afa6cc4, 0x7d0b4ffd,
12336 0xbfbd6e2f, 0x9dfffe96, 0xcf7e8ff4, 0x7a44bfd0, 0x42fa499f, 0x1c36593f,
12337 0x06b89c9f, 0xf8674bf9, 0xda12eb8d, 0xe9a95ea5, 0x0cbebcc4, 0xf7d82ddc,
12338 0xc895ec8c, 0x51468dbf, 0x6c6fd09b, 0xf9354133, 0x4c981ffd, 0x86d3790f,
12339 0x94e4dced, 0xaacffcd8, 0x14b8a660, 0xe94d6e3b, 0x4da338f0, 0x78d89a77,
12340 0xd37edfc3, 0xd144b5a2, 0xb9974e9f, 0x9b3f453f, 0x707f44ee, 0x21427a41,
12341 0xe964a937, 0xc594af8a, 0xd8bc879d, 0x6a4b213a, 0xd86336c4, 0xa15f6bbf,
12342 0x81a82e52, 0xfe213fbd, 0xbdeec94f, 0x486fffc8, 0x17492320, 0xef3f166e,
12343 0xa696fc37, 0xf8633865, 0xe2334c1a, 0xf14196ad, 0x42e1f073, 0x3fced7e6,
12344 0xf50b4e88, 0xfbe55e7f, 0x115fc631, 0xe153ed7e, 0x9fc97ad7, 0xabfb8659,
12345 0x5d38fcf7, 0x4fce79c3, 0x18c1a582, 0x390b1539, 0x2c1c1981, 0x3ae3ccee,
12346 0x4bb350bb, 0xdff388d9, 0xa16c2ef7, 0x13fbee75, 0x6f7d896c, 0xfe6153b6,
12347 0x6653b671, 0x726c5aed, 0x316bce51, 0x18cb39a6, 0x5db0911d, 0xb2140275,
12348 0x7cbed5cb, 0x0ef28485, 0xe176cfb8, 0xd1480b92, 0xe03ddef8, 0x9fffc855,
12349 0x9d3eb07b, 0xf3cd0dc6, 0x117713c6, 0xa2a2d73e, 0xd7792f29, 0xe8392ba9,
12350 0x936e060f, 0x75c49c58, 0xfbdcf4ac, 0x2927e8c0, 0xdf039cbe, 0xafa8b3d5,
12351 0xf366e035, 0x7222f319, 0x05ccfce3, 0x38992215, 0x12c17e8f, 0x347c8bd8,
12352 0xfa825e52, 0xc11eec69, 0xcd7f5fe2, 0x827fdb1f, 0x1d1a1ee3, 0xfaf14b1d,
12353 0x8a9fcd42, 0xeff7cf48, 0x7d434196, 0x77c5377e, 0x90c0e117, 0xaf87f9c3,
12354 0xc63f53a5, 0xd867a65d, 0x65ef716f, 0xdecfdbf2, 0x73adc633, 0xde9bb82e,
12355 0xd0140a83, 0x67f11b9c, 0x496814b4, 0xe06a352e, 0x3e43dfe7, 0xe6c294e1,
12356 0x59b2f033, 0x5f31a5e0, 0x978b111b, 0xbc21f4c6, 0x71ab7cb0, 0xa6ecccaf,
12357 0x0016dbb1, 0x8159cb94, 0xebfeff3b, 0x234f7d2f, 0x1f3de782, 0xc4346e21,
12358 0x3711efc9, 0x8fbdc61a, 0x3f443711, 0x886b7b2a, 0xfe9e8fdf, 0x79a3eec8,
12359 0xbe35b9ef, 0x7381a5fb, 0x3df2437f, 0x083ef1c9, 0x5f98e783, 0x28d62cef,
12360 0xf0785baf, 0xebca39fa, 0x9a2d3a1a, 0xceabe905, 0x6967f1e8, 0x680921fc,
12361 0xc6c4437c, 0xa743559c, 0x7f61b014, 0xfb63a84d, 0xda6ba468, 0xd8539756,
12362 0x7221dbf0, 0x901ff507, 0x7fd8cd02, 0x7b5eab79, 0xf0b87509, 0x6997ebd5,
12363 0xf957bede, 0xeab657bc, 0x9013cc1b, 0x03feb03e, 0xd3aeaf9a, 0x6fd43602,
12364 0x8ea2339f, 0xa43af5a6, 0x1d57ad20, 0xf34aa1fc, 0x7ab0bf57, 0xb539a53c,
12365 0xc6aa9afb, 0xbebff8c7, 0x0d55a783, 0xf9dd54e5, 0x5c62c5c3, 0x015f0f39,
12366 0xfec63766, 0x369a0737, 0x2ee36398, 0x7b275bfe, 0x2df77e12, 0xe175ff21,
12367 0x271216c2, 0x67ae95fa, 0x7657e625, 0xb872bf33, 0x85fedffd, 0x8bf43bd6,
12368 0x281b8409, 0x837935bf, 0xb1716757, 0x5703ac41, 0x9ea951de, 0x2e54e869,
12369 0x7c65e7c7, 0x77a735fc, 0xf92673af, 0x85b49855, 0x79f13bd5, 0x25940ee2,
12370 0x7e7ae1e5, 0x390fb30a, 0x8f5d406d, 0x069f7cfc, 0xc7663f20, 0xf4855a80,
12371 0x5718970e, 0xcdec0d60, 0x3ebf91bf, 0x67ad99a7, 0xac5f002d, 0xcfda30df,
12372 0x82b1ff44, 0xd528d54f, 0x9515da17, 0xf910db70, 0x7f90d544, 0xc5c3e87f,
12373 0x7def249e, 0x6295fc22, 0x29ef56f2, 0x468fb61f, 0x714a39a9, 0x44d0f1aa,
12374 0xd67a674d, 0x2ebf8ca3, 0x58fb469b, 0x5993f078, 0x3ef998d1, 0x578c7c43,
12375 0x5f86e986, 0x2155387d, 0xe1fcbdb9, 0xcc7a7354, 0xaad2723e, 0xe0f94903,
12376 0xbb49e2f1, 0x5bad0af7, 0x35a2d07f, 0xdcdb7c33, 0x3877c211, 0x44668dd5,
12377 0xcb9b56f8, 0x3f7df163, 0x2c21bbe3, 0xd0e911bb, 0x6bed5a10, 0xddd3e362,
12378 0xb43906a4, 0xc99c2740, 0x23c32f0e, 0x37ae27fc, 0xfe30e28b, 0x756a3fa0,
12379 0x78477efa, 0x55e9a731, 0xdaf898e6, 0x35e68a60, 0x5f3fa44b, 0xfb1882eb,
12380 0xad74d393, 0x99e48b39, 0x61b596e9, 0xae2629fd, 0x6a2d3e97, 0xdb1c5177,
12381 0xbd91f38a, 0x93b13e44, 0x3687b7fc, 0x3beec958, 0x47ae0e9c, 0x481cd755,
12382 0x877a09b7, 0xbb26adea, 0xc29391da, 0x2e31b5eb, 0x09ffef86, 0xaf647daf,
12383 0x3e028eb8, 0x09f77f56, 0x058df5bc, 0xf7297fe6, 0x94c99c23, 0x199215ef,
12384 0xce341cf9, 0xbdaa6a1f, 0x87976b14, 0x7f1373ee, 0x1f7f0a4a, 0x135e3872,
12385 0x7175cdd7, 0xaa693d9c, 0x13105d6a, 0xe5c71387, 0xc399b8d0, 0xceb30072,
12386 0x697001ce, 0xfefc324f, 0x776959c2, 0xde5dfe91, 0xcd87e449, 0x51e118c4,
12387 0x81f29353, 0xd95cb3e3, 0x2e4de3c3, 0x554f5b07, 0xeb920e7c, 0xad39397f,
12388 0x67265ea8, 0xec8d6c34, 0x057f6878, 0x9b3b526a, 0x91def82e, 0xc4f7af1f,
12389 0x38c4d371, 0x56e7a4c5, 0x65879f11, 0xdafd3766, 0x31bfd300, 0x9d723fae,
12390 0xed7c3feb, 0x79d90f2e, 0xcf865afe, 0x5c597f4f, 0xbbccc726, 0x853959ce,
12391 0x12e793f6, 0x5cf45078, 0x2ba47be2, 0x733f1f7e, 0x62b8677a, 0x4c601fce,
12392 0x04e12dd6, 0x16e07d44, 0x83eb0ef1, 0xb57c6649, 0xe4dc521f, 0x1e443bdf,
12393 0xc32f066c, 0x35b82a49, 0xe07af756, 0x7f70f3d7, 0xb04c472d, 0x1d3b4913,
12394 0xf3628c72, 0x04d8b079, 0x8a326cbb, 0x4b158f08, 0x323212bd, 0x9ae25fec,
12395 0xc86d8df6, 0x65d021ef, 0xd7c73f5e, 0x3c91e0c1, 0xfbfd6c52, 0xd5adcd5a,
12396 0x5af9cfbf, 0xeb13cec8, 0xd31139df, 0x16e3357a, 0x96d7e0ea, 0x1f83ad25,
12397 0x53d7c574, 0xc634bb0f, 0xc712705c, 0x12923061, 0x3028e7e0, 0x845c7083,
12398 0xedfa84e1, 0xa555bc39, 0x275649be, 0xf4d733c6, 0x418c76a7, 0xe5cf1b3b,
12399 0xfd0b7440, 0x8df3ca3b, 0xb5fabaa1, 0x44ff2cc9, 0x7ab3247f, 0x497821d2,
12400 0xe6395fd0, 0x7118bc49, 0x91e5d5c7, 0xc9da5fe3, 0xb4bbb6ff, 0x067e92df,
12401 0x7940ca4e, 0x551ccd9c, 0xebec499d, 0x98b3e520, 0xe2e4bc8f, 0x921ad67e,
12402 0xdf5c013c, 0xe28079aa, 0x98e1cdbc, 0x59d8c72e, 0x85c78b95, 0xf217e3fa,
12403 0xaf23cc54, 0x97b4de9a, 0x5d75fce2, 0xcc74ec07, 0xedfe7b53, 0xb4147459,
12404 0x4edbecc8, 0xb4a9fb76, 0xf94ac8a7, 0x54c08ee1, 0x52304f92, 0x77714190,
12405 0x7374198a, 0xf8fc8dd9, 0x50a6e377, 0x33bb0d86, 0x3c253b59, 0xa7e51363,
12406 0x2fdf08fe, 0x0ba0a1ad, 0x8c490e2c, 0xb8b50bee, 0xbfff3e68, 0x3f228f76,
12407 0x9f9b3fb5, 0x45f8be2f, 0x0cdf7f09, 0xacff1a66, 0x1ef029cb, 0xd479d130,
12408 0xd58e717e, 0xc6cc85f7, 0x094feb19, 0x881d902d, 0xeb48d283, 0x164e7651,
12409 0xca7cb0b6, 0x797002f6, 0xa3cf3184, 0x4bc39cf3, 0xbf51e280, 0xf612dc13,
12410 0xb00ca7b7, 0xdba067fc, 0x912f3da2, 0xec815adc, 0x75e55dbd, 0xf602314b,
12411 0x73f0da40, 0xf85b3d63, 0x44e674a7, 0xfc50f0b8, 0xe15b99b3, 0x7958b4b6,
12412 0x877933a7, 0xa6c80f29, 0x34a62275, 0x77d1cfca, 0x1af8cf3e, 0xbad813e6,
12413 0xccc59f06, 0x03abb7cf, 0x62cf1f97, 0x0708397c, 0x84f9c0c5, 0xfc8d44f0,
12414 0x61e1cd9c, 0x3439b0fb, 0xc8dd2eb7, 0x262a7f97, 0x3f3f6860, 0x7b218668,
12415 0xa7f6fb26, 0xb456d30c, 0x8e02f685, 0x3c37d06b, 0x0c7e68b5, 0x62a68e4d,
12416 0xaed3fdf8, 0x1b6d4f8d, 0x748dcec3, 0x8a9ff519, 0xf68bba6d, 0xbd0aedc9,
12417 0x8cbb27a7, 0x728dc1cb, 0xfef2b54a, 0xf388f1a1, 0xf8d3a234, 0x91c5b738,
12418 0xd99f2cba, 0x18bd900b, 0xa5b7d9f9, 0x503be5c8, 0xf43fbdb5, 0xbee29466,
12419 0x1f474d7a, 0x9f71c36b, 0x45160fad, 0x7d50fea8, 0x5f3e13ef, 0xd76abf79,
12420 0xedbbf214, 0xf9057b8a, 0x23fea89f, 0xa8bf0796, 0xec633b68, 0xe40cc60e,
12421 0xd7137e10, 0xfe6f9ff1, 0xfdb9e511, 0xaacd2487, 0xc81dff91, 0xc21bbe23,
12422 0xd7e4ab1f, 0x643e87fd, 0x9913ed79, 0x5eb42bbe, 0x2169a845, 0xb40e75c9,
12423 0x2edf90b6, 0x3041f911, 0xc193fb97, 0x37cf4533, 0x9ec1e8c5, 0x0edc7129,
12424 0x9c51c6f8, 0x3d7b0b0a, 0xb627f54c, 0x2fee475d, 0x44bbf9a4, 0xd7bc6c7d,
12425 0x93474704, 0x35e19bdc, 0x9dc50ed6, 0xe1297980, 0xf59ce4ac, 0x78cc4f21,
12426 0xbf3f266b, 0x02f58ab5, 0x133fbe99, 0x2e47b5bf, 0xe7da76aa, 0xd51e60a5,
12427 0x93ac4195, 0xc8fc491d, 0xd826fd90, 0xa03cdf93, 0x15ff78d2, 0xf5057e60,
12428 0xf5032dbd, 0x685cffb7, 0xde7c7af2, 0xa0c93a85, 0xaf3ce17c, 0xef14bb13,
12429 0x74df1a68, 0xe4a9f3f6, 0xa82806c7, 0x779f7fe1, 0xb9238ed7, 0x532bfe21,
12430 0x803acec8, 0x4ec335f9, 0xf14ec94b, 0x7fc252fd, 0xccc5d139, 0x3dabb72f,
12431 0x765d98cb, 0x12ec8099, 0x01eccff1, 0xb8a0eff1, 0x7b40ea5c, 0x644fef60,
12432 0x63dede76, 0x167cb0f2, 0x4604fafd, 0x744dde57, 0x0722cf7b, 0xe21373b3,
12433 0x35ec8cb9, 0x13cd9472, 0xa634a004, 0xec6f025c, 0xcb954139, 0xf86cf0ce,
12434 0x7ec22dcb, 0x0cb49383, 0x5523ee37, 0x23ece396, 0x5a725e26, 0x7fc7d3c4,
12435 0x9ea793fc, 0xa78f4f99, 0x10e138f3, 0xce9b5271, 0x22a3fefc, 0x3ebe3556,
12436 0xe51b5577, 0xacc96fe5, 0xa738b0ff, 0x1c9c0888, 0x1414e715, 0xcfd43437,
12437 0x75fce26b, 0xf41ed226, 0x5b3cb3a3, 0x556e5216, 0x18f5b4b1, 0xc1bd73b5,
12438 0xce329485, 0x4c73d75f, 0x425e66e1, 0xfa3cebf8, 0xf933128d, 0xcebcf3bd,
12439 0xe072fceb, 0x0e511783, 0xf9461d8f, 0xb8538927, 0xcc3f861d, 0xee4346b3,
12440 0x92fdfd8d, 0xf97e47e1, 0xfa43aa0d, 0x1a61e53a, 0x020363e3, 0x9955e89b,
12441 0x474a78bf, 0xf4c83ec6, 0x7944c9ac, 0x35bed9ca, 0x9cef9499, 0xcc8732fe,
12442 0x45ccebb2, 0xaa773f56, 0x4fc2129e, 0x9c960167, 0x7b7a7049, 0x51f4c2a6,
12443 0x673f896e, 0x84c7da31, 0xb0e9141d, 0xb1f5624b, 0xfd5008ec, 0x547b29dc,
12444 0x80ae83cc, 0xf91e76be, 0xf81e711b, 0x0f1f8808, 0x6cfd41fe, 0x9423e414,
12445 0xdadc60b7, 0x77128cf8, 0x2de4673e, 0xb07bc675, 0xdaf844c5, 0x1fe09614,
12446 0xcfd51651, 0xa3af8fc5, 0xd9e705bc, 0x7c73da1c, 0xe6b5ea34, 0xca7e8485,
12447 0x79b9d85b, 0x75a3d590, 0xfe5c4a6d, 0x38a658f2, 0x42842c0f, 0x57105fca,
12448 0x66284fcc, 0x1c416138, 0x6df6c84f, 0x6fdf3b20, 0xff42f2e2, 0x0373ecca,
12449 0xb79f15e1, 0x34bf7257, 0xcc021570, 0x8f05f67e, 0xb9df91d9, 0x5a6ef96d,
12450 0xf799ae63, 0xf3e50dcf, 0x40730d7b, 0xa90a8d5e, 0xb316f8f0, 0x9cf75afc,
12451 0x54b945c9, 0x0e097f0b, 0x59b5fe7e, 0xe45abeec, 0x4a039b77, 0x2fcefcd2,
12452 0x4081cdc6, 0x69bbad0b, 0x47cec49f, 0x8fc5f76b, 0xd5390bf7, 0x9c7d3eed,
12453 0x83eafd8e, 0x4e42fd09, 0xf3fc50fe, 0x78727c03, 0x1e5390d6, 0xf373b1e4,
12454 0x6756b713, 0x7cf0a67d, 0x8f316de3, 0x38161fd1, 0x906dc06a, 0x7202eb7e,
12455 0x2d547080, 0xf79e76e9, 0xdc7ada42, 0x060306df, 0xb941fe1a, 0xb4e42c3c,
12456 0xed87e041, 0x7fafdf1f, 0xbdd00a4e, 0xc74fc3d3, 0x5e035ff3, 0xdf3e3475,
12457 0x952df9d8, 0xf112f5ce, 0xb0a6dd56, 0xc846b7fc, 0x355f1127, 0x5569f843,
12458 0xe225be29, 0xdd27c1ab, 0xb79e7f84, 0x37f96fff, 0xa6235cf4, 0xec2255a9,
12459 0x1ff6a89c, 0xddaeb724, 0xfb435f7c, 0x4bfbfb11, 0xd0de75f7, 0xcc9864f7,
12460 0xf334bdf4, 0xf8a5eb16, 0xe543bb7c, 0xe6683376, 0x9e06cae7, 0x2c5fdf12,
12461 0xbb25f5f2, 0x357ade79, 0xe74ecd74, 0x833dfdc4, 0x69ad6076, 0xa247c529,
12462 0xa5f8c7c7, 0x5d79324f, 0xa3f73dbd, 0xbf3e501f, 0x637143a4, 0x637507a6,
12463 0xf1c52f15, 0xe7afb1ba, 0x2bad8f8c, 0x1d25f8c5, 0xe8db348f, 0x9297e23c,
12464 0x3fb2cc9b, 0x894777fc, 0xf724dbd6, 0x78ff7c04, 0xe66fe0cf, 0x53725e91,
12465 0xfe7cd167, 0xda4b3bee, 0xfcfe3e91, 0xfd6c770c, 0xf7c5dc79, 0xc2ac64b7,
12466 0xa8ef6ae2, 0x415a7fd4, 0x3d9e85e7, 0x5f7bbecc, 0xfb25597d, 0x20976fef,
12467 0x9e3a1717, 0x1d25ec7b, 0xf07bdde5, 0xfac94ab4, 0x6ad3cec2, 0x85f26bf4,
12468 0x458e58ab, 0xab6a79d8, 0xb78f754a, 0x946af7eb, 0x3e17a7f2, 0x3554e764,
12469 0x3e53e794, 0xd01c9cf6, 0xbac79ff0, 0x4f09515f, 0x8c126d0d, 0x57ed8fc8,
12470 0x41f93f58, 0xe36e3fa2, 0x69c0d4fe, 0x81a5c095, 0x55b70353, 0xd86cffc2,
12471 0x86971c91, 0x9e08da9f, 0xbe70a3ed, 0xabd6da47, 0xd23d0794, 0x137e3f1a,
12472 0x68d399d5, 0xa6e5c73c, 0x9bfdf1dd, 0x33a8f087, 0xefe89d3f, 0x1e04b24a,
12473 0xf098a18b, 0x1aa91838, 0x7fdc4667, 0x1c66ba7e, 0x7947b924, 0x2377c453,
12474 0xbe4cdebe, 0x2a6ba17d, 0x18ff45c5, 0xfe17d585, 0xc6a1ff31, 0x166665e2,
12475 0xf0e2cbc7, 0x569e981f, 0xa22c8f84, 0xaf8256f5, 0x32bce48e, 0x7ca0ea9c,
12476 0xdb944579, 0x25b0b2f1, 0x3f889010, 0x2b878b13, 0x708db821, 0xc2d87fd0,
12477 0x955f29cf, 0xc204de58, 0x72126dbf, 0xbce424df, 0xd1b1eb09, 0xa883ddf4,
12478 0xdd441bc7, 0x9ed279bd, 0x340254e3, 0x93bafe88, 0xe724ecc7, 0xcffdc065,
12479 0x3ff720b2, 0x788cfe86, 0x18f76892, 0xfd241ea9, 0x402d86d7, 0x172c33df,
12480 0x1b7967fe, 0x46e91ffa, 0x323fd03f, 0xef47e195, 0xc6277ce2, 0xf8ce86cf,
12481 0x78b20bf1, 0xf2283a3e, 0x712caae0, 0xb6f4203e, 0x4b520062, 0x9a65be71,
12482 0xb7b00eec, 0xfeb4cc7a, 0x4788a989, 0x5684ff9c, 0xa24be198, 0x8dfda34f,
12483 0x7a0defc8, 0xe18b9d15, 0x35a3a0f8, 0x7f7eb62d, 0xebd78b2b, 0x9d647335,
12484 0xef5310f4, 0x4fcb2aac, 0x377cef5a, 0x31bfc70b, 0xd3d3c366, 0xcf1deb63,
12485 0xe3c2229e, 0xbc7f73f7, 0xf157be82, 0xd2ff71b7, 0x66f38157, 0x2c0efe50,
12486 0x59b7f61f, 0xf8975402, 0x37544f11, 0x90bc212c, 0x3ba586bd, 0x2f582f09,
12487 0xaff3493c, 0xdc3b2ba6, 0xc610eaff, 0xf57e9c69, 0xfc303fa2, 0xf7cf1c9d,
12488 0x911b728d, 0xea307eac, 0x782f8686, 0x6f3c6a7e, 0xfd594730, 0x189610d0,
12489 0x5e8f3b7e, 0x7e47cbcf, 0x98ffbbfb, 0x50db1eb7, 0x9db38f16, 0xf48bc195,
12490 0xede7c91d, 0xe879a4d6, 0xb6971f90, 0x50697b31, 0x3f2c39a2, 0xe0f98439,
12491 0xde37ac6c, 0x1bd594fe, 0x0f6d479d, 0xcab43cb1, 0x35f1ce37, 0x66826a7a,
12492 0xc336cf96, 0x9e52d636, 0x6dff9b13, 0x52eff072, 0x48388a36, 0xeb8813f4,
12493 0xf6f6388d, 0x83fd1bb2, 0x05ea6fe1, 0xbe8337ae, 0xa3749e7d, 0x7617a89f,
12494 0x67ba5b53, 0x8968a53b, 0xb0bd5079, 0x59fccc27, 0x83cc4bdc, 0x6bc04ade,
12495 0x2c29dbd3, 0x293fedcf, 0x184ce83b, 0x51f3fbe5, 0x7e61ef94, 0x1ce4905f,
12496 0xcf8153f4, 0xd9ff715e, 0xf9332154, 0xd6f0e699, 0x8e509bc8, 0xa7fd370c,
12497 0x275402d3, 0xa57e1c94, 0xbb507080, 0xdac5c70f, 0xc7d1ea1f, 0xf00a0fbe,
12498 0x2a60a573, 0xfa31d3bb, 0x657e1ff7, 0xe9ade132, 0xb88b2fed, 0xa917ae7e,
12499 0xcfe73759, 0xd7892568, 0xd78926bf, 0xa8e65dbf, 0xff2eea9d, 0x881bd921,
12500 0xefa1abd1, 0xc08e040f, 0x8bfcebcc, 0x9ba31a59, 0xa61f1cc2, 0xfae2de6e,
12501 0x8f39f96b, 0xa1bfd6c2, 0xf37112bf, 0x880ef135, 0x5f80c42f, 0xf3f86019,
12502 0x7e31369f, 0x7307a7fc, 0x4ebee362, 0xff208ef3, 0xcc0754d7, 0xf902a49f,
12503 0x3a67f45d, 0xdfcbcbd5, 0xea7cb1b3, 0x15aec178, 0xc8157fcc, 0xb1ebfe40,
12504 0xc6266bb7, 0x598d8bc6, 0x254c3f32, 0x1652e439, 0x5f5f0cf3, 0xd619a1c8,
12505 0x8e027388, 0xb9338fe7, 0xeafac15f, 0x89cf64cf, 0xe6add5f5, 0x16dd4dc5,
12506 0xff6473a0, 0xcefb0b05, 0x4deef3e4, 0x2f877eac, 0xdfc9137c, 0x8d37cf80,
12507 0x6f0ec7da, 0x3fcf489a, 0x1a79bc3f, 0x9a94f73b, 0x4e99e2e3, 0xbe52e5fc,
12508 0xc3473674, 0xb3eefafe, 0xfab8bbec, 0x4ff1856e, 0xcb3c6c74, 0xefe7e6c8,
12509 0xec6c47fd, 0x0282437c, 0x1f18038e, 0xe75d6f37, 0xa8bf2ceb, 0x589ec90b,
12510 0x8def183c, 0xb171e6cb, 0x20e05b30, 0x9e987928, 0x175b783b, 0x53f1997a,
12511 0x1e9904ab, 0xde14da9b, 0xcc5bcedf, 0x3a1f193b, 0xbfe274b8, 0xf9bfce83,
12512 0xe73b08bd, 0x3ecc91c0, 0x07152706, 0x6bfd2276, 0x1d72847a, 0x3f80980c,
12513 0xe4fbb0b7, 0x19851396, 0x13c1fb84, 0x8b25672f, 0x3dd26f1b, 0x54e5420a,
12514 0x1243af3e, 0xf3652ffb, 0xe75387f3, 0xb53b3fb9, 0x993137c0, 0x92a1d35f,
12515 0x9092e9d7, 0x34b2a777, 0x45dc7dd9, 0x31bedf31, 0x4fda29fa, 0xdd8d876f,
12516 0xf93af5c7, 0x03c2ea79, 0x1499cd27, 0x99a53b7f, 0x276a4714, 0xbe88bbbd,
12517 0x9cba4003, 0xe46d5afc, 0xac77bb10, 0xec58eb6f, 0x4747c249, 0x32dfc736,
12518 0xe67df935, 0x3bff44b7, 0x7516cee0, 0xae132ed4, 0xc50acef7, 0x1de593b1,
12519 0xe891b49e, 0x7e12ef87, 0x0a95eef8, 0x01de53cb, 0x16f7e14d, 0x95617efc,
12520 0x0977b3f0, 0x22aabcff, 0x57be3fb9, 0x39fab3cc, 0x17ee9278, 0xc7e27b56,
12521 0xbdf22bdd, 0xf361e035, 0xa134bddf, 0xf77de45f, 0xc1f2137a, 0x8b87e16c,
12522 0x70fc88a0, 0xe903e310, 0xc6d8b1bd, 0x29f2ece2, 0x09e69213, 0xd2ffd1c7,
12523 0xc42703f7, 0xfe860477, 0x65df8a9b, 0x91d4ebf1, 0x99392ff3, 0x4141b6ff,
12524 0xe1b1fb92, 0xfdd865f8, 0xe2ef5c3d, 0xc1dea1be, 0x7ff43479, 0xd8a32b15,
12525 0xff432d73, 0x7f73674f, 0xb6cfbb59, 0xb0bef625, 0xa38ce83e, 0x5b91a1fd,
12526 0xfbf8c52e, 0x8c73815a, 0x73d8e601, 0xdf641790, 0xf4d9d9d3, 0xcb2f6b3d,
12527 0x2c0771af, 0xf2bee17e, 0x2cf2bec4, 0xeae97131, 0x7149f5c8, 0x973fbc3c,
12528 0x167ffdce, 0x5b148f6b, 0x07d5fd98, 0x6bdd00a5, 0x3db847d5, 0xb123dfd6,
12529 0xcea2c273, 0x857bec23, 0xb7248bb5, 0x33b1bb87, 0xa3819fc4, 0xcf1e5655,
12530 0xc90cbc0d, 0xfa88e04b, 0x25dfbe29, 0x9e227be2, 0x62cf4226, 0x8f3eff9a,
12531 0xecefa6e4, 0x75a38a6e, 0x30a75fd3, 0x211c3374, 0x9bf2152e, 0x24fa7889,
12532 0xf249d7db, 0xed71fac3, 0x54ff9c14, 0x8479c7f1, 0xd89b869f, 0x1d856fd1,
12533 0x4fd34bed, 0x3baffc51, 0x0fd5ee20, 0x24a28714, 0xf2c01397, 0xcf675ec0,
12534 0x1f9e46f6, 0xfaf57bb3, 0x0f7d8d88, 0x754e1f58, 0x6cee88db, 0x754c994a,
12535 0xa7765864, 0xf3a2bd22, 0xdfaa22f4, 0xeff39457, 0x01d41a3c, 0x3ab68796,
12536 0xbf89277d, 0xb8a6ee95, 0xcf8374fb, 0xd13de19b, 0xe1245dcf, 0xfcf5ff64,
12537 0x972145cf, 0x72d793c6, 0x9d7e1326, 0x5365dfbe, 0x45fd793c, 0xfcf6ae95,
12538 0x9c595f93, 0x8d38d1a9, 0x76d95b8d, 0xe31d1b64, 0xcf4ffc1a, 0x4efe3076,
12539 0x2c318129, 0xb5bd2cbf, 0x0e9a4bef, 0xf29531bd, 0x2723bee9, 0x3831aaa7,
12540 0x7f446def, 0x4d7f449d, 0x6bf61260, 0xad24ad66, 0xb70ef911, 0xb1f77f67,
12541 0xe85f3a1c, 0xa52e3b25, 0xe29dacf6, 0x3bc77d64, 0x779409f6, 0x98d6f174,
12542 0x66586aef, 0x2d1cc0e3, 0x963d37ba, 0x7f1927bf, 0x1e7c8357, 0xddd16880,
12543 0x5bfb6253, 0x40fdaffe, 0x03f30e7a, 0x603f38d1, 0x7bab09c8, 0x8799d59d,
12544 0x9e9eec2d, 0xbf625bee, 0xe1ce2acf, 0x1636697e, 0x73af643d, 0x90b99ee8,
12545 0x3c333352, 0x2219b440, 0x07dd1766, 0xddfe6447, 0xe7e618da, 0x67f58967,
12546 0xe847239b, 0xe239cdbb, 0xf42e727e, 0xc3b771b0, 0xe03d6b00, 0x095b5330,
12547 0x5856d66e, 0x6ca9cb23, 0x65060d2f, 0xc7247fd2, 0xe56cbcec, 0x4c90f2bf,
12548 0x3372c3df, 0x1e4365c3, 0xf163dd32, 0xf712ffef, 0xf1c39953, 0xfdc3db38,
12549 0xf416a50f, 0x040566dd, 0x6df9fdd9, 0xe8f71510, 0x0f31f7c9, 0x37ba37eb,
12550 0x99d30dbb, 0x008f2614, 0xf69f3f1b, 0x4fdb2723, 0x33533974, 0x7f10722c,
12551 0xf4c72452, 0xefadea55, 0xd8073fa3, 0x030df6bc, 0x0f978f7d, 0xc3ba3bdf,
12552 0xdf47bc6f, 0x0f1e4a99, 0x6dd50efb, 0x1d508b4d, 0x1de8da83, 0xe80563f2,
12553 0x56aa7337, 0xfe1ccce6, 0xc07c1f9e, 0xfc48cfbe, 0x7bb69f9e, 0xbbf86725,
12554 0xd27be32f, 0x9a35817d, 0x2eb1f109, 0x1196eacb, 0xbcd6651f, 0x657bec19,
12555 0xe1256fa7, 0x36d482ea, 0x0e624d81, 0xa87964cc, 0x782a55c0, 0x92ff682a,
12556 0x027df8c7, 0xc5d17860, 0x039eb7f9, 0x5238f7ec, 0x2bf7fc2d, 0xad0e2176,
12557 0x8d7e862e, 0x27858fbe, 0xef946a16, 0xdd5a776e, 0x8859cf94, 0x7e61d4df,
12558 0x3bfcac5b, 0x5e6b168a, 0xf1b8fc80, 0x3ca2585d, 0x3d16505b, 0x56dd0ecc,
12559 0xfc272f96, 0xc59b47fe, 0xcf922df7, 0x472bd3b7, 0xf25c1e50, 0x2cb9f9ab,
12560 0xcc79472f, 0xba61e437, 0x7028f7f1, 0xfda1dfff, 0x82fefe27, 0x04546fb1,
12561 0xc8438f03, 0x838390d3, 0xc77144f4, 0xf4327a83, 0x9f2c305c, 0x0e5c295d,
12562 0x52417d0a, 0xc8d5dec8, 0x6ff7135e, 0x01bfefec, 0x8f1a3ec3, 0x00003430
12563};
12564
12565static const u32 xsem_int_table_data_e1h[] = {
12566 0x00088b1f, 0x00000000, 0x277bff00, 0xa3f0c0cd, 0xa5fd811e, 0x79ba1818,
12567 0x8968c550, 0x30327137, 0x303170b0, 0x06710268, 0x2036ded0, 0x17c40edd,
12568 0x1022f880, 0x3033719b, 0x11710214, 0xf2032f10, 0x56dcd093, 0x50c0c4c1,
12569 0x4035c405, 0x3ac4075c, 0xba0c0c8c, 0x1fdbc48c, 0xf0c0c42f, 0xd7c10c42,
12570 0x48606710, 0xff9fa491, 0x54ee1b07, 0xc27dafa1, 0x860c0caa, 0x4662a8ba,
12571 0x5d637c68, 0xa09866fc, 0xf1a29bc9, 0x17e8f0cd, 0x87e540b4, 0xe3f2a219,
12572 0x7618198c, 0x3709a922, 0x7416efc4, 0xf7a802fc, 0x00031025, 0x22037beb,
12573 0x00000368
12574};
12575
12576static const u32 xsem_pram_data_e1h[] = {
12577 0x00088b1f, 0x00000000, 0x7de5ff00, 0xd5547c09, 0x73b9f8b9, 0xc999dee7,
12578 0xac84992c, 0x5d86f12c, 0x48409c04, 0x5876c443, 0x0622b4a4, 0x30a20a97,
12579 0x9037d96c, 0xff69f0fa, 0xa5ab0819, 0x68d06a1a, 0x68304ec1, 0x1a0741b0,
12580 0x01c04830, 0x6a2be2d4, 0x6d8ad3ec, 0x2c3480c5, 0x0dc46486, 0x3ff2d3de,
12581 0xcdce77df, 0x11337bdc, 0xbffbfb6c, 0x4f169fe5, 0xb7fb3dce, 0xe77cef9d,
12582 0x92cc5f3b, 0x407e1240, 0xa1f865c8, 0x211318e9, 0x5d245c64, 0x88fdfd6c,
12583 0xe5227d53, 0xacc8957f, 0x465a48e0, 0x46dbe42a, 0xb213be45, 0xb16feb12,
12584 0x589346b9, 0xc402d348, 0x93df3f45, 0x84592268, 0xf826e7dc, 0x9bce25b3,
12585 0x12126426, 0x6f7168de, 0x25dfa74d, 0xd02425c5, 0xb720fd74, 0x4a76805f,
12586 0xebc3e412, 0x9a56f725, 0x165f5f27, 0xcad9bda1, 0x27e813da, 0xf87c9089,
12587 0xd221107d, 0xe8f89145, 0x024ba4fc, 0x32245ba6, 0x4fce972f, 0x2646df72,
12588 0x73f3223a, 0x9392e427, 0x994efbf4, 0x52efd396, 0x37d5ae42, 0x2d7e5232,
12589 0xe4fe7011, 0x5fec4aeb, 0xfbb56f1d, 0xd717ab36, 0xdfb517eb, 0x5c17dcbb,
12590 0xcb757df0, 0x2d0fd8ed, 0xc39675c1, 0x9e5a14fc, 0xa6265270, 0x3811ff48,
12591 0x351c7005, 0x71d0b4af, 0xf08847bf, 0x84ed37ca, 0xb76abbae, 0x5c2858a4,
12592 0x4296ef26, 0xd2f9a03f, 0x7900213a, 0x211b01d3, 0x9b9d6e14, 0x94e43e59,
12593 0x7cff50bd, 0x2ed3cd3d, 0x8fad2dca, 0xdd7000dc, 0x38ad922d, 0xe609ae4c,
12594 0xadc2aedb, 0x6cf3e599, 0x775a5b2c, 0x2fb42e70, 0x1b10b668, 0x6f74afed,
12595 0x681b8cfe, 0x4488ff3e, 0xb6e94aa0, 0x9a5f7215, 0x41080c2f, 0x224d77c8,
12596 0x8f7fbe38, 0xeb46d818, 0x935ab977, 0x3c70a4ee, 0xca256957, 0x676f3a30,
12597 0x141dd26b, 0x9d81450e, 0x515da153, 0x1201e0a3, 0xdb7bbc9a, 0x5db4a9eb,
12598 0x63c176e9, 0x6e2970a1, 0x386513b0, 0xfa65c39b, 0x0c49bdaf, 0x2f9680fd,
12599 0xe924eba5, 0xa9ead780, 0x37f18444, 0x02338aca, 0xc39573a7, 0xe4896289,
12600 0x71d3b74b, 0x17b2bb68, 0xb12c0f04, 0x407c44cc, 0x6d7b9d97, 0xc0719eb3,
12601 0x43c856fa, 0xb5aeb09d, 0x0fcbd432, 0x5363dfcc, 0xf2757e60, 0xb45e5a54,
12602 0xd3ce4eb9, 0xe1b8bfe0, 0x3558a23a, 0x941daaf3, 0x630fa5ac, 0x89928e7a,
12603 0x84453e76, 0x200e8378, 0x533c8083, 0x857d17c3, 0x7177c438, 0x9feba883,
12604 0x44909242, 0xe8f7dffa, 0xfe5e14af, 0xab844efd, 0x9ca5b78a, 0x5dbc548e,
12605 0xcc43fce0, 0xff6d2ce1, 0xe008fa6a, 0xbaa7ce81, 0x2fe98dd2, 0xad30532b,
12606 0x3f1054a9, 0x68fc038f, 0xdbcf81ba, 0x344c8135, 0x5e5d71d3, 0x8b3606e2,
12607 0x289dee9f, 0x2e7c7cd1, 0xe3dd27cb, 0x596f9413, 0x2e3e9abf, 0x4f03e6f9,
12608 0xbd53226e, 0x979a54e6, 0x87884b7d, 0xd5be6f8e, 0x213c653b, 0xa3df12af,
12609 0xe4d17eb0, 0x12bc002b, 0xa5c94c12, 0x50235978, 0xb5e14239, 0xe1491616,
12610 0xd29526b0, 0xe3d3c533, 0x233d66f7, 0x09ad7c0a, 0xf67bcf90, 0xa7ec74e1,
12611 0x6991fb16, 0xdcae833f, 0x6cdcd24f, 0x73493f5d, 0xea7ed40b, 0xab989fb0,
12612 0xb9f1e7eb, 0xccf9fa39, 0x79fb522d, 0xae89ea1e, 0xd2575bab, 0xf9fa09bc,
12613 0x7ec12bcc, 0x10f1ef92, 0xaa2fad1f, 0xbd5a43f4, 0x34772d22, 0x98798dc6,
12614 0xd268e968, 0x49cfe81e, 0x474b4ab9, 0x3a31d9b1, 0xc6f38a7e, 0xa67df2eb,
12615 0x4fd5d5f5, 0x2ba81dcc, 0xc2359e4f, 0x770e9740, 0x0f3c75fb, 0x91597293,
12616 0x32bee5ef, 0x7d899dca, 0xfbff38ad, 0xee503afb, 0x1be39fdc, 0x86f3a6e6,
12617 0xff8a12b9, 0xf5df65fb, 0x437428ee, 0x149025d7, 0xa4131548, 0x12b5f2c6,
12618 0x7ea4db83, 0x413d0f5f, 0xc29b97db, 0xfe68e343, 0x8ff13088, 0x80bfeeb0,
12619 0x8b78a530, 0xd4054911, 0x9410b18b, 0xb3d36b7f, 0xe06bf19e, 0xa5006eba,
12620 0xefd22117, 0x0297c93a, 0xafe6d8f4, 0xae7d03f0, 0x60532019, 0x54827212,
12621 0x6983fc84, 0x297901fb, 0x4c8b7f00, 0x7c7687e5, 0x123f8e99, 0xf1876fc7,
12622 0xdf197a3b, 0x375b3032, 0x40ad35be, 0xa655be37, 0x08fe53e3, 0xf1f397fb,
12623 0x0872fc29, 0xc72c94f9, 0x05692df1, 0x995afe38, 0x8fc6e814, 0x4bff1ee9,
12624 0x186bf718, 0xfaca313f, 0xd7e8e607, 0x5fa4569f, 0x4fd6ccbf, 0xf8f9f856,
12625 0x417eb831, 0xa7f5b3f0, 0x5bf5b115, 0xe3ddbf58, 0x2fe1babb, 0x875c740b,
12626 0x07facbd0, 0xffafd04d, 0xfafd129a, 0xf77c6c2d, 0x7c7c758a, 0x271f8e07,
12627 0xbfeb63ac, 0x97c704a6, 0xd00f3e2d, 0xa62fdc91, 0x69fb0022, 0xc940ca7f,
12628 0x98bd0328, 0x84278f0e, 0x93df93ca, 0xfb870881, 0x7ddd1863, 0xcde94319,
12629 0x24a79111, 0xee903940, 0xa69c65c3, 0xca271b8b, 0xe3f67f6c, 0x4f98bebe,
12630 0x88b35175, 0x2c6a4d74, 0xbe742181, 0x1fa2cd9d, 0x6e6a8bf2, 0x9fb8880c,
12631 0x98823d32, 0xffbe0849, 0xada8d375, 0xd31975da, 0x7b52d5c5, 0xbaaf869b,
12632 0x3224fbe5, 0xafce82bc, 0x5c608802, 0xe54edf24, 0xf872a134, 0x90c79524,
12633 0x5e98969e, 0x71ca8a72, 0x37cb4c32, 0xe25e982b, 0xa70eef27, 0x9f09fff3,
12634 0xc199bb7f, 0x10997dbb, 0xb97ff800, 0xf20c8971, 0x9db5716c, 0x8f323d02,
12635 0xf0a78e72, 0xf5004b5e, 0x001dba29, 0x5642ee7c, 0x03c3e424, 0x502ebcb7,
12636 0xb6bf2d3d, 0x3dddae8f, 0x853ab024, 0x61b85fd6, 0x5d3700fe, 0x96599cff,
12637 0x4fec2231, 0x84cfdbc4, 0x99fa4c7c, 0xd59909b2, 0x47ea51b4, 0x92cd7733,
12638 0xda69b64e, 0xf3e9f6cf, 0xf9f40a73, 0x9920294e, 0x14299f40, 0xf7ed1d48,
12639 0xb97d0ade, 0x2134ce3a, 0x8f95e19e, 0x830a13f7, 0x5ee9fa54, 0x67c0c748,
12640 0xae75e237, 0xe755b59b, 0x44a0fe53, 0xb71fb842, 0x7fc41225, 0xb9f3d622,
12641 0xf38dbad9, 0xbd592b9d, 0x733e74b9, 0x9e11101f, 0x1db7f9c6, 0xa34d7bb0,
12642 0x99fb5a69, 0x5c682404, 0xf3fe718f, 0xe3d71b96, 0x987f6196, 0x677e37ef,
12643 0xa7a46274, 0x8f89e6f2, 0x53d0d29d, 0x8f47f069, 0x2bb4d29d, 0xcba9986e,
12644 0xeb660617, 0xced7e7ea, 0xae2f95d7, 0x2f95d42e, 0x9744b75c, 0x407fef9f,
12645 0xf2de7f57, 0x7bf2ba15, 0xcaebd62b, 0xd46c14e7, 0x9efb67e5, 0x6bbfd5d4,
12646 0x5cae9d56, 0x4d785038, 0xdf55ca1b, 0xb7a0a935, 0x4021607e, 0xabbd2a8f,
12647 0xea8670fc, 0xa39e902d, 0x2ba40b7a, 0xff294f80, 0xb4b2f69b, 0x6bfceb7c,
12648 0xfebd1adc, 0x069154b4, 0x7ba464fc, 0xf48d3c23, 0x45fa7f4d, 0xb4d487db,
12649 0x20b92044, 0x7ef8bae7, 0x5ebf7eae, 0x647a7130, 0x7e129de7, 0x95d9289e,
12650 0x3bce093a, 0x68687225, 0x7ef7a385, 0x75c05049, 0x13d2d010, 0x5a946f01,
12651 0x6e2b7035, 0x679ba418, 0xc71141c7, 0xa5de032f, 0xe4832ff2, 0x0f200b36,
12652 0x6ed38742, 0xf1f3051f, 0x4cf905ee, 0xff71139a, 0xf69ca8ed, 0xe00929d8,
12653 0x99e98b97, 0xb69859ca, 0x3d30fa57, 0xe9805955, 0x4c0acac9, 0x63972adb,
12654 0x8fd2bc7a, 0xd72a5fe9, 0xcaa7fa61, 0x558f4c6a, 0xc7fa62d6, 0x9da600ca,
12655 0x554c5e95, 0x9396edba, 0xe56f5cb9, 0x81fa0be7, 0x2d7cade9, 0x15bdfd22,
12656 0x0293d1f9, 0xf1c178fc, 0xcbd050e5, 0x48a31c2f, 0x5e1def4e, 0x15e87a46,
12657 0x7a8bc4ae, 0xe2805e45, 0x72cf4fb9, 0x93c30c5b, 0x11a644cd, 0x0fd6372a,
12658 0x60b3d679, 0x24cde624, 0x3c07da1e, 0xfa519d33, 0xe0147ba5, 0x22784aeb,
12659 0x3868f0de, 0xf53fb70f, 0xefd0599f, 0xb640c2f5, 0x71161e5f, 0x67a124bf,
12660 0xefaf803c, 0x95e1370a, 0x6f80d30f, 0xf0aa27ce, 0x34234d6b, 0xb1b8225d,
12661 0x164d0bff, 0xb6380662, 0x847003d8, 0x19e470bd, 0x4b77ec17, 0x53eac453,
12662 0x57877b63, 0xdabd3069, 0x794f59a1, 0xa17f3eb3, 0xcec6985a, 0x1dec4af9,
12663 0xdcae80a3, 0x0086a7d5, 0x553053fe, 0x229a59fb, 0xb9ea38e3, 0x21c63496,
12664 0x2173d29d, 0xcf67fbd6, 0x227eb7a3, 0x1f2268f3, 0xbb01d853, 0xe5741e5c,
12665 0x7c0f4bf3, 0x73973f9b, 0xd22d4f01, 0xc79fb097, 0x07977fd0, 0xcc66bf42,
12666 0x0796fdab, 0x7ae5bf45, 0x1ba8def8, 0xd453b68f, 0xebb43733, 0xa4cd5e9d,
12667 0x15275d5d, 0xdedc196d, 0xab60dc52, 0x38fdcbd6, 0x39bcbe5d, 0x0fb75ab5,
12668 0xef942fc0, 0x06608149, 0x54e129ba, 0xac7665d4, 0x1cfce813, 0x2dfb0526,
12669 0x52bd5817, 0x53ec9b6b, 0x415b0c90, 0xad90580f, 0xd7729dd2, 0x3e5ca99f,
12670 0x3c897bfb, 0xeedce50c, 0x2547f6a2, 0xfcd13130, 0xd05b9e42, 0xe41d3c54,
12671 0x373dd9dd, 0x88b0fea3, 0x10e0bae4, 0xb3aa4053, 0x4f390f40, 0xee80d34c,
12672 0xb83f93cf, 0x03ce6ac6, 0xce324c73, 0xfd3ae167, 0x27f5483e, 0x56bf3e5d,
12673 0xb723cf9f, 0xe79d0125, 0x202448d5, 0xcbea3f00, 0x7e31366f, 0x6b1527c8,
12674 0xc5587f60, 0xdc0b13cf, 0xf28fdcc4, 0x5b4be97b, 0x79d3e6b2, 0xf931302c,
12675 0x0bdf9ead, 0x511e99e3, 0xc193ac14, 0xd371f39e, 0x40dc9fd8, 0x0d607da0,
12676 0xbbfc31d8, 0xa536cf05, 0xebbefe27, 0x55f38dfc, 0x761e8ff7, 0xd28f3e04,
12677 0x881bc106, 0x98548fb2, 0xf8ffbe04, 0xeb097e99, 0x1b99e8d6, 0x435af90c,
12678 0xff90debe, 0x812de9bb, 0x61cde8e8, 0x25306df2, 0xfd02fa32, 0x6587304a,
12679 0x7fd23fdf, 0x6bfe8f4a, 0xf7fda9ff, 0xe967fda7, 0xa7ffaffa, 0xc7b83ff6,
12680 0xfad183fc, 0xc7697d2f, 0x37953f1e, 0x726e2f45, 0x9cffba11, 0x79275735,
12681 0xb64bfe28, 0xe2fb46ad, 0x05dfb319, 0x20367cf4, 0x39440b4e, 0x71369f57,
12682 0x3af125bb, 0xc0f73804, 0x73ffb4af, 0x067cffcf, 0xdcbe5b9c, 0x3cf1b926,
12683 0x590960d3, 0x35969f28, 0xa3274e15, 0xe5827f31, 0x422a7ed7, 0x9f4f59be,
12684 0x4a6dcf45, 0xa51bfb02, 0x87efae14, 0xab2a5f50, 0xd854ebff, 0x1849ca7f,
12685 0x0ed8ccf9, 0x8f18bfc6, 0x1cbe71f2, 0xce9cb3db, 0x72f0f513, 0xa6f2970e,
12686 0xba2a7f9f, 0x69d1fd20, 0x369317b4, 0xed8d93d4, 0x73feb80a, 0x684ce4cc,
12687 0xf91eaaa7, 0xc81ef91e, 0x242e154d, 0xf11ff4c0, 0xe1a32da5, 0xff51dafc,
12688 0x81a0977b, 0x176fca97, 0xfd7f0b82, 0x5cbbd2b2, 0xb1e7e4ee, 0xb600bb48,
12689 0xdeb99a53, 0x12d2c2d6, 0x7b02e429, 0xe49d4969, 0x25cfd3f1, 0xf6799e3b,
12690 0x7e4f3829, 0xa10cf160, 0x78ef17fd, 0x34398fed, 0x4a53bc5f, 0x4049ce98,
12691 0xa7e08a48, 0x3e5bfe9c, 0xa28f8226, 0x2b26bedf, 0x87f7d8a3, 0x297823e2,
12692 0x265079de, 0x63c27aa3, 0xdca0f072, 0x9f8288e6, 0xa0a989e0, 0x7d2f895f,
12693 0xcffe0323, 0x7248101e, 0xd678147a, 0x027a86bd, 0xc9f109c0, 0x3f8dd5f1,
12694 0x8a72fd43, 0x46eb9017, 0xedeb197c, 0xfa05f2e5, 0xa521fb05, 0x065e17ef,
12695 0x2c9ff33b, 0xc143801e, 0x60b9f70b, 0x15cda73d, 0xacb7ce8c, 0xf1d2f24e,
12696 0x927f240b, 0xbdf6531b, 0x229fe9e0, 0xf3bfe5fd, 0x7e7624d3, 0x709aa6f3,
12697 0xc2a7f2af, 0xbe6f173a, 0x4799d713, 0x0587487c, 0x905cc45b, 0xc9985f97,
12698 0xf8519db4, 0xe4c89e64, 0x14ade9e6, 0xa79d74b9, 0x768436e9, 0x81883fd7,
12699 0x58bf686d, 0xfc1e4042, 0x9397b554, 0xc2ff98a5, 0x4e35f0ca, 0xaa7ef554,
12700 0xb7e969f5, 0xe02b6d7e, 0x6f00dce9, 0xcabdd832, 0xe1cfd989, 0xfda65c21,
12701 0x94dcef8a, 0x1444f0cc, 0x476f1673, 0xf0c982f5, 0x4ab7ea1d, 0x5d68db5e,
12702 0x3d39723b, 0x3e32fe32, 0x0c779d3e, 0x93a7e7ec, 0xca304148, 0xaa8836fa,
12703 0xbafba01c, 0xfc34ce86, 0x7ebff8ce, 0x9577e33d, 0xa73303ff, 0xefe7f941,
12704 0x76823e32, 0x79d25fb0, 0xfcb19285, 0xca021de0, 0x45090b07, 0x897af3e3,
12705 0xdcbeb9f3, 0xfe742f48, 0x43562166, 0x3c4e3037, 0x5eed01e2, 0xbdb43579,
12706 0xb8c2ae56, 0xaafd9eae, 0xe5cf9c7c, 0x9522ddc1, 0xe445d707, 0xe4ccd901,
12707 0x977aef40, 0x2258f11f, 0x0a7d9e05, 0xabf297f8, 0x95fe015f, 0x9ffd6172,
12708 0xe3fe1e34, 0x3e6f94dd, 0xab7caa09, 0xbe46ab97, 0x2e35d82d, 0xb27edf2a,
12709 0xdf3a2321, 0xf951efd2, 0xdbe30376, 0x5572d7ff, 0xa8956385, 0x9caaab97,
12710 0x469e0dec, 0x2a269939, 0x9ca35708, 0x92ef3fa4, 0xa8f49eac, 0x7f4aa1d2,
12711 0xbd29bf45, 0x3751e406, 0xd874aa9d, 0x1d2aa74d, 0xe89fb0f6, 0xbf2c68e0,
12712 0xd2826819, 0xf7deee4b, 0x78a3f6a6, 0xf761692d, 0xebddb450, 0xf2f0a790,
12713 0xaa4736e2, 0xa097ef5f, 0xf90c07cd, 0xd7bea1a0, 0xd435cf90, 0x15f219f7,
12714 0x6601fa86, 0x2c3e683f, 0x9087a413, 0x92b4beae, 0xb7609df8, 0xdda22fdb,
12715 0x79ce8bae, 0xd5df6d0d, 0x53f01e98, 0xc6dab0f9, 0x44e18fce, 0xb3c80d79,
12716 0x15d8772e, 0xd31b790f, 0xc372bb7b, 0xfe8d38ae, 0x4445a278, 0x2016dc79,
12717 0x8cf6b4d3, 0x21545f08, 0x6f48dafe, 0xd90ecce5, 0x77eec315, 0x691d126f,
12718 0x59dce1cb, 0x19287a2d, 0xee2b4590, 0xba898172, 0xadd065ab, 0xc5f7e8b3,
12719 0x5aec886f, 0xa735efc4, 0x670dce6a, 0x09f1ff88, 0x6d97dc02, 0x6c2ffc40,
12720 0x4588e761, 0x73d3a21b, 0xe7976f11, 0xdc832658, 0x49fffaa4, 0xed559dad,
12721 0xe1b360a7, 0x9ccdcb7b, 0x3cf1abee, 0x2faf5457, 0xd0f3f1f7, 0x647e5549,
12722 0x1f940c90, 0xf381d070, 0x37bb9738, 0x9d6f2389, 0x75d0f145, 0x37402444,
12723 0xc4445a17, 0x764685c3, 0x89fc495f, 0x24653fc8, 0x854ef28c, 0xc7f00757,
12724 0x50e5deb0, 0xb30feec7, 0x4a55a41e, 0xf479fcf6, 0xb1da68af, 0xfba183e7,
12725 0xfbd2ff20, 0x3d267f69, 0x603e4feb, 0xd76e3b43, 0xbbde2701, 0x337fed74,
12726 0xefc841ed, 0xbef078b5, 0xa357c0f9, 0x56ba8e81, 0x8e400a5a, 0xf7600d75,
12727 0xbffb55f4, 0xfb86dd1a, 0x9fc42ae7, 0x5fceccd3, 0xf3fe5a17, 0x5fb3dc38,
12728 0x02aba168, 0x1d80e0fd, 0x2fe5e1ed, 0xd08ed0db, 0x2cabffb5, 0xb79fe39f,
12729 0xbf7e329e, 0xb324e5d2, 0xe2fcc176, 0x7cba5d98, 0x5667f8df, 0xd373fdc0,
12730 0x2d217941, 0x37cafc9f, 0x763e41a3, 0x4f7a62ed, 0x34f6d4a7, 0xaca41fdc,
12731 0xa242b4ba, 0xe604ee70, 0xf94f4be8, 0xf92672ab, 0xcb834647, 0xb91f6837,
12732 0xff5c785a, 0x021e063f, 0xb49623de, 0x01560338, 0xf8e97dd6, 0x1c1e419f,
12733 0xaa5d20b0, 0xb824fdeb, 0x2b91f502, 0xac067bad, 0xd37ff13b, 0xd5d085ba,
12734 0xbff4bbac, 0xe33fbe39, 0x0f91a8fb, 0xfef9d27a, 0xc3bf31fb, 0x5ef9c1e9,
12735 0xe2ffbd25, 0x77de1b7f, 0xaebbbc51, 0xffc6eebc, 0x1deeebe6, 0xe5cc6fef,
12736 0xfdc37778, 0xdf2bf97b, 0xabbefce0, 0x3ffa3b9c, 0xbeaafd74, 0xf2933bfe,
12737 0x3fad066e, 0x403b548d, 0xe951f8b1, 0x683237a1, 0x1ffaefe9, 0x4ef9838e,
12738 0xc635f7e2, 0x66637df9, 0x7049bee7, 0x25c7436f, 0xef3f0271, 0x3f5273b1,
12739 0x5bf45fae, 0x487a8796, 0x40bffebf, 0x9598827d, 0xfc0fb81a, 0x0f42da5d,
12740 0x319036fa, 0x77907cc7, 0xfaf3c8df, 0x04afe2f3, 0xcaab85e2, 0x1f37697e,
12741 0x7fb53d01, 0x58f5117f, 0xfafea29a, 0xfb1a6baa, 0xceeb225e, 0xf4523f33,
12742 0x09a99be7, 0x14d073fa, 0x844ddfde, 0x8726ffcd, 0x38500810, 0x58f01a4c,
12743 0x2743d802, 0x4088910d, 0x6f8953f3, 0xa61b9c15, 0x7dfdf438, 0xe3c4f700,
12744 0xb7cc7022, 0x7f022dee, 0xc047ab3e, 0x987586fe, 0x33589e50, 0xe183a405,
12745 0xbfcc66b5, 0x038f7263, 0xe1b8cf38, 0x201e4fa5, 0xcaf55760, 0x65cba14c,
12746 0x2faff1f6, 0x05909e5f, 0x03f66fe7, 0x50b778fe, 0x66d17d7d, 0xeba18a12,
12747 0xfe266c5d, 0x8bb078d8, 0xcea4e40a, 0xc3cfaa2e, 0x2293f7cf, 0x7ea95cfd,
12748 0xcff8746f, 0x74a25f4e, 0x2108727f, 0xfbc5217b, 0x53cf662e, 0x6bdf57cf,
12749 0x3f2af061, 0xd903024a, 0xab98b8bd, 0x2c5a3fb9, 0xe97bba31, 0xc2c6bb2f,
12750 0xd76266b9, 0x8fc658c8, 0x904fcc99, 0x881797eb, 0x0071eb12, 0xc58a0e3f,
12751 0xa223b17b, 0xd9df9a33, 0xfade7e76, 0xd297dc0d, 0x549eabb4, 0x93f7a08b,
12752 0xfcf9da30, 0x2db256f5, 0xae427f8a, 0x382ddaa4, 0x988fe8de, 0x367af605,
12753 0x34da62fe, 0x8eb78b56, 0xa3cd67e9, 0x7e01e27b, 0x2bee6a4e, 0xc2f851fe,
12754 0xbbe00ef9, 0x3536d6dd, 0x2edf0a37, 0x633d9890, 0x784ba1c6, 0x52d11ebe,
12755 0x1f3e0267, 0xddd26f51, 0x712dddbb, 0x190c7dfd, 0x719af303, 0x04cce6c8,
12756 0x3d111cbc, 0xde57efe0, 0x8beca9f2, 0x84646f72, 0xf60ff427, 0x8dc95ad6,
12757 0x8293eee3, 0xfbae010b, 0x9c095bce, 0xd5caf6b7, 0xe9e6d1c5, 0x2e79b0b0,
12758 0x46fbc126, 0x83f7ffa7, 0x472ec4ef, 0x579c1268, 0x75f209ea, 0x4823fa4f,
12759 0x481a17c7, 0x9c31e400, 0x5c2e406f, 0x1fb82468, 0x02fc9050, 0xdf946bce,
12760 0xc73da07f, 0xf9de6b0f, 0xca47d81b, 0x9837045a, 0x6dcccba0, 0xcaedd832,
12761 0x9044e39b, 0xea8a19db, 0x751ee90f, 0x6a2f8687, 0xebc23325, 0x39bece70,
12762 0x1d67ee30, 0xcd7d8132, 0x05d86afb, 0x96b3ff72, 0xbd07c8b1, 0x95b7ebad,
12763 0x048a68a4, 0x6ba410fd, 0x6c8c3d23, 0x6fe5d18c, 0x817d7d10, 0xda5866bf,
12764 0xe0a27996, 0x7c66472f, 0x2df2d57a, 0x7c99fff0, 0x6f95577b, 0xc357313e,
12765 0xd1992647, 0x25be46bd, 0x4b6f9347, 0xe0192505, 0xa0ff74be, 0xd2ebc064,
12766 0x68c4a437, 0x25476df2, 0x917b07bb, 0x3576b1fb, 0xbd76f951, 0x5135be46,
12767 0x4fc516f9, 0xf13243a0, 0xf20aedfd, 0xc35ff02d, 0xbe403b7f, 0xbe67a345,
12768 0x6df2a83f, 0x9409cb74, 0x4c9ba36f, 0x2fccff3a, 0x84df28af, 0x9f403bc4,
12769 0xec79223a, 0x0767e851, 0xe45edfd7, 0x0e30367e, 0xb271b9c8, 0x5abfc71b,
12770 0xb5729739, 0x08bfee72, 0x5b9caace, 0x9fa09bba, 0x643a4f6a, 0x5ee96e72,
12771 0xa004e72a, 0x96e72647, 0x8ecc27ee, 0xc36f9063, 0x8237c87b, 0xac42cbf5,
12772 0xfa73797d, 0xfed0f713, 0x8f2578c6, 0x131fd695, 0xb4e37791, 0x6c9c6ef2,
12773 0x90f73846, 0x4eae4777, 0xf2e6edde, 0x81b1ca8e, 0xf48d5f20, 0xfbd169e1,
12774 0x7f1beeff, 0xc0b7f1ba, 0x788a6f2f, 0x898ef50f, 0x35bc17dd, 0xd02674fe,
12775 0xc99906d7, 0x7b971f5f, 0xec7e959d, 0x6cabf27f, 0xec8da57d, 0x1359413d,
12776 0xeacb0fd3, 0x7f4280c5, 0x09739a9d, 0xf70a93ef, 0xe699240b, 0x1faa5a67,
12777 0xfd3e8077, 0x3eb8449c, 0x43433d3d, 0x8bb28b0f, 0x655bced1, 0x94256d73,
12778 0x8999178f, 0xc5b9ec15, 0x4167a98e, 0x66ce2d9f, 0xfe62dff6, 0x544bf55d,
12779 0xf78d33fd, 0x4bcd79e9, 0x7a47ef5e, 0xb0cfabde, 0x78cebc30, 0x1f800846,
12780 0xf67bcf61, 0xe285ca00, 0x15f7fd06, 0xc533fd7c, 0x79178436, 0x8b6cf45b,
12781 0x8c2b3fc2, 0xe1c23a70, 0x83a2e144, 0x0a884053, 0xe9e98a27, 0xb8114919,
12782 0xb6d9be14, 0x85c0ec06, 0x6f780a4f, 0x0ab75c68, 0x55fae337, 0xd176aa38,
12783 0x7e5fde62, 0x33be1d4b, 0x8545c231, 0xdd1e11b3, 0xa3c03770, 0xfff6e64a,
12784 0xfc16320c, 0xa0dd2858, 0x9bfff19c, 0xb90ffe88, 0xdee88713, 0xf2e7ac43,
12785 0xc4f56c7f, 0x3ddd70c9, 0xe182fc13, 0xc976ae3e, 0x37dfe0eb, 0x063298ee,
12786 0x721bd3b6, 0x97b83e2c, 0xa30b6edb, 0xf0e9541c, 0xcd874e23, 0xfafbbe1c,
12787 0x73c24c56, 0x06e0b361, 0x643ca43d, 0x5396b843, 0x2ad1b47a, 0x72fc9f87,
12788 0x1bab872a, 0xf334bbdf, 0xc1e289fd, 0x751fe704, 0xf7b00abf, 0x185b6331,
12789 0x181bca5e, 0x1849325e, 0xb565efed, 0xd7442782, 0x04bcd653, 0xf95582fd,
12790 0x5a1c7f4c, 0x5fa1453c, 0x25fa3473, 0x8acc9c60, 0xbcc59bec, 0xf54b0cde,
12791 0x3f9ec11f, 0x1d47f283, 0xdffd2192, 0x95f7d0b7, 0xf88c45fc, 0x6dc390fa,
12792 0x01d5c007, 0xfd330bf0, 0xdf09742b, 0xe5e5a8cd, 0xae0ebf66, 0xc8ba9f93,
12793 0xa0bf6fe8, 0x1ba51d80, 0xb4cf406e, 0x370a9c7c, 0x43c067a0, 0xf2117ccb,
12794 0x7dde1479, 0x17ae7bd2, 0x7cb4c7ee, 0x04ffb85f, 0xe08b7feb, 0xfdd65121,
12795 0x3bfbe99d, 0xfc6f75d2, 0xbe8191fe, 0x8f85b2df, 0xdefa058e, 0x93df202f,
12796 0x3dfd3896, 0x4dcecc97, 0x0f946ddb, 0x0de61ee0, 0xe955b3c9, 0x1cc21f29,
12797 0x509e70ce, 0x6b927634, 0x57e02161, 0xff4560d8, 0x40c79c30, 0xe56aafa6,
12798 0x491b0ef5, 0xf7b323bc, 0xf9c6fffe, 0x497d37ac, 0xf1828fcd, 0xd3368e40,
12799 0xc64786f1, 0xaa17ee33, 0xeb4ae01d, 0xb1fe5bb2, 0x7ce3a975, 0x7299ff57,
12800 0x28f78ad2, 0xc38d1faa, 0xe0942be4, 0x304d3afc, 0xc2d1fdeb, 0x70ffcf1c,
12801 0x2dfcb2ff, 0xab1493fd, 0x4de2fdee, 0x29f883a2, 0x4af33edc, 0xcb542fc8,
12802 0xec026f78, 0x3ee8931f, 0x8ecf9348, 0x1eff7b8e, 0x5ef1172c, 0xfb37d6e6,
12803 0xd5bdc294, 0x8a67ccad, 0xa0219adc, 0x740ef0fe, 0x70f41e36, 0xf85af12b,
12804 0xfb3cb490, 0x7801717b, 0x5f519067, 0x7ca1593d, 0x5021a63d, 0x7267a905,
12805 0xc02de138, 0x009144d7, 0x7dbd5abe, 0x7bfec326, 0x06495fdf, 0x9ea8ce98,
12806 0x398cfd80, 0x5ea11242, 0x8f11378e, 0x3e9be333, 0x3a76f77f, 0x4547f1bf,
12807 0xcdeb428f, 0x0070ec3c, 0x6cdf0d9f, 0x5c0d3e22, 0x0aa04872, 0x4fe347ec,
12808 0x79076f79, 0x1ef54050, 0x682ff7f0, 0x4172aba9, 0xed80b37e, 0xa9befdcb,
12809 0x1dbf3a2e, 0xbd4e9fb5, 0xad02e40e, 0x6f94dd07, 0xebcaf566, 0xb2b80f05,
12810 0x946cb5e6, 0x0bd46e51, 0x476ca0f8, 0xd6562040, 0xfb4ac06f, 0xb699b1dd,
12811 0x8bfd84cf, 0xeb7e87b6, 0x76f77d3f, 0x9e743b90, 0xdd91bed8, 0x76d1e6cf,
12812 0xfd49f00a, 0x70afec12, 0x5de040b3, 0xdb234142, 0x4a8e0a9f, 0x3a6f281e,
12813 0xbbee24f8, 0xa978e9d3, 0x851fb0e9, 0x8efbe0a6, 0xdf1b82b1, 0x43494dd5,
12814 0x0b05d5b9, 0x01d60686, 0xe05cbeec, 0x51fe7e79, 0x2d37bff5, 0xcf377fcc,
12815 0x43ee42b3, 0x3b2b79fb, 0xf484dd31, 0xfa0ca9f4, 0x6f0a29da, 0x3bf7851f,
12816 0x70e17fdc, 0x9b72c7f6, 0x673c7f66, 0xbff48419, 0xfa2279a8, 0xb9262d4b,
12817 0x633faf78, 0xdf3bd33c, 0x0016d1be, 0x52dbddbb, 0x3f7c3fb8, 0xbf05a37c,
12818 0x7260ee77, 0x1b4073b8, 0x6f4f69da, 0x47bc0896, 0xa22cdaa8, 0x28dd389c,
12819 0xb8b5fde1, 0x9db94245, 0x21e983bf, 0x7eb33787, 0xfd30374f, 0x3b96f26d,
12820 0x9c3ec2a7, 0xefbd4dbf, 0x3d5a7266, 0x0bb9e687, 0x519bfb75, 0xb872aace,
12821 0xa0a3c394, 0x5fef0eba, 0x54b7728d, 0xf20d0fdd, 0x65ee14b6, 0x8435fef1,
12822 0x341a547c, 0x983913fa, 0x0d73863c, 0x12e843d0, 0x51d977d2, 0x46b9c089,
12823 0x2a63b8f8, 0xec2ce7ac, 0x7c7cb4f7, 0xfb85e08b, 0x966382f0, 0x81e3ea00,
12824 0x15fef3f9, 0x2c0f99f6, 0xbfc05044, 0xca83e29d, 0xf84b6ca9, 0xefd18f2f,
12825 0x82b1df67, 0x9fa508a7, 0xd57f08f9, 0x1b73342f, 0x7cc8f3f3, 0xde0926a7,
12826 0x7d29927f, 0xd7e40e50, 0x91a7c48a, 0xef05671b, 0xfdb377ed, 0xfff5adc1,
12827 0xf3ab94cc, 0x6fed9f60, 0xd951f265, 0xddfbe126, 0x447cfcc3, 0xb7e80bcf,
12828 0x6377b859, 0x87a1ac92, 0x931bfdc2, 0x6b20e8a8, 0x15447fb8, 0x285bf77f,
12829 0x0f0a71b3, 0xcd3aee08, 0x6a3f6a38, 0xd65ef2bf, 0x967ed06e, 0x217fd6f6,
12830 0xf9d70fcc, 0xc3720c85, 0xf18f4fd8, 0xfb27e97b, 0xc0d62fdf, 0xb7eced3b,
12831 0xce6e7445, 0x20fa78fe, 0x9a80bded, 0x590c7eaa, 0x57889aef, 0xbfecbf03,
12832 0x06af10c4, 0x28e34ddf, 0xddfc53ff, 0xb9f4ccd2, 0xe42771a6, 0xbbcc4cd2,
12833 0xb8cbdf81, 0x0a6cba3d, 0xca69efbb, 0xf0156778, 0x014cf4ff, 0x7df881e9,
12834 0xd4049f72, 0x4ff014df, 0xed64cfce, 0xe07b69f3, 0x1927a6cb, 0xa179529f,
12835 0xdb293c80, 0xd62a71bc, 0xe81417af, 0x3e6ea9bf, 0xd90525ea, 0xfaf2c122,
12836 0x1527a813, 0x00489f34, 0x5bfca67e, 0xd940fa03, 0xc41b8b04, 0x2a97cab1,
12837 0xfdcdbf9f, 0x3dd58989, 0xcbf8fc0a, 0xf0a2a980, 0x709478b7, 0x65f195bd,
12838 0xdbe33679, 0xb04877b7, 0x73e1abc2, 0x8f956be4, 0xcce3e045, 0xde1f1f08,
12839 0xbe06593c, 0xd0101d3e, 0xc83262ef, 0xedf3e001, 0x31efb702, 0xf96af63d,
12840 0x667a4afc, 0xd85fe529, 0x573e552f, 0xcfc8daf9, 0x3bb6e6ad, 0xddf71e60,
12841 0x4c75c368, 0x3fdefefe, 0x15e4c7de, 0xfe4dd7de, 0x204903fe, 0xccccf31f,
12842 0x6b8547af, 0x81f999a9, 0xcd5798f5, 0x6af5390a, 0xc79867e6, 0x5ede8b46,
12843 0xc712d872, 0x25eb9dfc, 0xf12bfba4, 0xbb3e0f67, 0x5abcfe4a, 0x7f12babe,
12844 0xfb8be3aa, 0x061cfdf5, 0xd9eb8e20, 0x6385275f, 0x77f1c288, 0x5fa0cf8d,
12845 0x4fe7f9d9, 0x143c00cc, 0x0e74a3ef, 0x24e8d5f4, 0xe6739021, 0x455bee00,
12846 0xfd17a24d, 0xaca1cd65, 0x3e5a9ddb, 0xc53ffe66, 0x9e913a2f, 0x0259768a,
12847 0xa2fb69d3, 0x468f1f3d, 0x61958c3f, 0x3ff24ff4, 0x7f65f5cf, 0x83e068db,
12848 0x43f33322, 0x9985ca32, 0x773fa656, 0x82cfb5ec, 0x2c0d09f5, 0xf05140de,
12849 0xb9a2c92e, 0x956698a7, 0x2f787ad4, 0x0c74a7e8, 0x7e6131ef, 0xaaee77da,
12850 0x76c751ff, 0x9a8a2726, 0x2dc400a5, 0xd9d86a28, 0x45a5fe09, 0xff682cc7,
12851 0x14f86f2a, 0xbf27e7fd, 0x2bed03b8, 0xeea2cde5, 0x3f87ad3e, 0xb218835f,
12852 0x535a1f80, 0xd1ffde29, 0x07cc09fc, 0x77dcffb9, 0x7e2b37f4, 0x3f1eff71,
12853 0x6ff16105, 0x7c81739f, 0xcdbad739, 0x0d7d7e85, 0xdb5feedf, 0xb82f7fc3,
12854 0xddeffb9e, 0xb9e09a72, 0xdeffba26, 0x3285f839, 0xbd5683ca, 0xe8691eff,
12855 0x9d25fa83, 0x946e5667, 0xfd6e8ffb, 0x4f17c77c, 0xc779ff83, 0x869e4fae,
12856 0xedfc9779, 0xafc1a7b3, 0xe1b01c88, 0xfcfe57be, 0xabafe87b, 0x6564dbb6,
12857 0xfdb9da74, 0xee77f439, 0x81e2c0fc, 0x9ff73ade, 0xb2ff034e, 0x92979dce,
12858 0x6cb99ec0, 0xef684dff, 0x727bb65d, 0x6fb28932, 0x6fd029a8, 0xadfc2ae0,
12859 0xdc3b788d, 0x9ffd1874, 0x83bc53ce, 0xcbf6ec1c, 0x7f32960c, 0x63fb8557,
12860 0x6ff74636, 0xd97fe1ef, 0x37adfb74, 0x626ffc82, 0xfd15e4fa, 0xf8a5df30,
12861 0xf02afebc, 0x6dfdc8d8, 0xab7cb783, 0xf879e61f, 0xc9abe285, 0x9a2fc780,
12862 0x29faff16, 0xd3ea6b28, 0xe8661fab, 0xfaa7e02a, 0xdeadfbcf, 0x6fc0ac57,
12863 0xfe837ebb, 0xe9bf80af, 0x5f47ec0a, 0x83fbc1a4, 0x2e785233, 0xfde13fec,
12864 0x52bf8c16, 0xe47dffb4, 0xefddcea7, 0x709a9da0, 0xd24ef63f, 0x8dfcc3fd,
12865 0x7adebe05, 0xe4dff327, 0x4eff0078, 0xb9df85c5, 0x6ba3271f, 0x37b3bfd5,
12866 0xacafcebf, 0xfd56ff4c, 0xffeb4bfa, 0x2324fdcc, 0x01b21378, 0xf5be275f,
12867 0x070a823d, 0x11cb9737, 0x7ee8e5bf, 0xcb7eddb4, 0x3e01bc06, 0xf6ea9f61,
12868 0xfef9a64b, 0xf24ed063, 0xf83f347e, 0xefe63ace, 0xdfe929dc, 0xc4f0468f,
12869 0x0d5823df, 0xab81cbfe, 0xd2be5ff3, 0x9c2bbe3a, 0x3452824e, 0x3abc27ae,
12870 0xdf2e8ebe, 0x3fc26d13, 0x916d5ef6, 0x931f7c60, 0x7f044b60, 0xcf681390,
12871 0xf37f3eec, 0xfb7076f5, 0x22f3c77b, 0x09aebffa, 0x6ef9461e, 0x10651f94,
12872 0x7cca2347, 0xbe98d987, 0xf6ccd65e, 0xce5d8e8f, 0xd3f68380, 0xd22f6871,
12873 0x09e35975, 0x7bfb4fd9, 0x32b7e1bd, 0x7c62c7bb, 0x4047fb04, 0x178e9eb3,
12874 0x7e668e0e, 0x6fdeccda, 0x1f1c671c, 0xfa25bca7, 0x9f8de538, 0xf629c6ea,
12875 0xe3b76507, 0x339de3ca, 0xfe82ef7b, 0x3d32b5ce, 0x9c505cf1, 0x587ded16,
12876 0xf7e24d8a, 0xa52cd561, 0x25c628fb, 0x2438b271, 0xf5062ba2, 0xecce65ce,
12877 0x9009b163, 0x5407e8ca, 0x0dfb82b5, 0x0293ccfd, 0xfe72aef8, 0x577cc098,
12878 0xf6357c03, 0x23edc91f, 0x294aafa0, 0x776099b9, 0x391dca30, 0x1a0244c1,
12879 0x4e732f7c, 0x5ef0564b, 0xf01fd424, 0xb4e33c79, 0x647efd04, 0x647d5fb0,
12880 0xe9926b26, 0x0bf23efc, 0x5fb4159e, 0x03c7f5f2, 0xfb3d9d72, 0x87bef357,
12881 0xa9bd9d44, 0x0e3e12cc, 0x8af215e7, 0xc423ef0d, 0xe78c3603, 0x0db4fe50,
12882 0xf7787bd7, 0xdea2cf57, 0x610b6bfd, 0x54f443f7, 0xdca47103, 0xbbd38fac,
12883 0x3ffa7abf, 0xc686af41, 0xa7fcfc74, 0x4f387d69, 0xfcf1da34, 0x762bb5d3,
12884 0xafcfea34, 0xe403383c, 0xd19dbe5a, 0xc98bfe63, 0x5fda2a81, 0xb7cb227b,
12885 0xf18018ef, 0x39778a03, 0xf0f11fd1, 0x60ca97ee, 0xd17cea9f, 0xa4066e0e,
12886 0xffae15f3, 0x3bc786ff, 0xad1495aa, 0x3121725f, 0x2077da2b, 0xe56790c5,
12887 0x7f049ef8, 0x811f38b2, 0x1639ab1d, 0xbd508fdf, 0x79cfd758, 0x07bf7c29,
12888 0x97dfd8e9, 0xf5099bbd, 0xac607905, 0x1fff96a7, 0xe5b7931b, 0x11ceda16,
12889 0x872e5fa9, 0xbabe58f3, 0xad27932f, 0x2ae7ff58, 0x9ef2f39d, 0xebfab2fd,
12890 0xf575036d, 0x3c65f6d4, 0x7e9188de, 0x16fde71f, 0x2c337c37, 0x288d3c5a,
12891 0x3fefc7f3, 0x04df8815, 0x1b4ecb7a, 0x778251c6, 0xbf0fe0f8, 0x5ff76647,
12892 0xc610ae25, 0xe5c7d933, 0x084c4971, 0xe5f4abe3, 0x90fa80f3, 0x17b6d627,
12893 0x2fa5ef00, 0xe7c408d9, 0xe9c57d29, 0xee977c05, 0x57fdaaf9, 0x66efe099,
12894 0xe95ebb47, 0x7482ff2b, 0xcd096a50, 0x3b6578c5, 0x99e2042d, 0x237cec75,
12895 0x43b5f80d, 0x7fc5a50a, 0x695ebdcb, 0x478862d0, 0x52efe7e0, 0x7de18303,
12896 0xb33efabd, 0xd33917a8, 0xdef76365, 0xbdde6cfb, 0x7d77e436, 0x95739edc,
12897 0xefb483cd, 0xe8948bb4, 0x9b4df172, 0x69d977f4, 0xa3b8e5bb, 0x37c73bc7,
12898 0x49e73e61, 0x2018126b, 0x0e3ea8cb, 0x21a8bcf2, 0x0fd83fbd, 0x77d4d90e,
12899 0xec2c4aec, 0x05248747, 0x0687d9cf, 0xfbb5fd28, 0xab4a99cc, 0xaed09662,
12900 0xdd576983, 0x097d79a7, 0x66da27f8, 0x1f7b9345, 0x8f08ecd9, 0x1bc5ab22,
12901 0x07649ded, 0x02deafdf, 0x1b224063, 0x1d43f817, 0x401490f7, 0x4628bc39,
12902 0x0ff4fd61, 0xb8bdf0c8, 0x2d20ef61, 0xd5cd0a1c, 0x29f28f58, 0xd490b3c2,
12903 0xf91a99c8, 0xb8578ead, 0xf198a1dc, 0x3ff9ba3d, 0x8c55e9ba, 0xc88d19e0,
12904 0x7472789a, 0xb33b45c7, 0x2cc0eefa, 0x7e015ae5, 0x9b75c932, 0x6a952045,
12905 0x1218f7e4, 0xd541d4c4, 0xaabf162e, 0x3c9c8082, 0x83471dd3, 0xd7811a60,
12906 0xfdf72803, 0x92190803, 0x1286fa0e, 0xefc0d6eb, 0xf385cd92, 0x082b98b1,
12907 0xddd31793, 0x7e0a7fa0, 0xe94cb91f, 0x61b2aaa9, 0x40f78b10, 0x0d7ef0bc,
12908 0x3f3a5855, 0x4bf5fb97, 0xd5f907a0, 0x27df70b8, 0x620a2a81, 0xbb453370,
12909 0xe2c224eb, 0x463bad99, 0xb48fe7b4, 0xffaf8118, 0x0731ca20, 0x6984fc89,
12910 0xc82ac41e, 0xbfd8aadb, 0x9cfdc365, 0xa0424dc3, 0x241dda1f, 0x63a9a764,
12911 0x969cf9a4, 0x34995dff, 0xf74ba1af, 0x91b97d04, 0x335ca82f, 0xf8441b8c,
12912 0x373f7ed1, 0xa1b9fbf4, 0xadbfcfdf, 0xe54e155f, 0x10e941d6, 0x65756087,
12913 0x8d8dc390, 0xa370e567, 0x710e19f0, 0xc62988d7, 0x11cdefc3, 0x367c31ae,
12914 0xf14fa816, 0x1d26273a, 0xd8f3f4e1, 0xaff06103, 0x04b50925, 0x04abc3ce,
12915 0xc922fe35, 0x11da6875, 0x70f915b7, 0x4e671f3d, 0xf577a30c, 0xfacf7c1d,
12916 0xe8efbc36, 0x5bd6df51, 0xf5e898fd, 0xc7cdbd9d, 0xdf3e751e, 0xbd94ce55,
12917 0x705bfef2, 0x6f2ddb5f, 0xfa9414dc, 0x6273db77, 0x71a5bf68, 0xc36b7fed,
12918 0xb46f4c2f, 0x2fe3d7f6, 0xd295e806, 0xfd60cc4f, 0x7bde2377, 0x7cf997a3,
12919 0x48ef341d, 0x9bbaeba5, 0x9ea53f8f, 0xb3df77dd, 0xe8e3d98c, 0xf50bcff1,
12920 0x77faf0e7, 0xaed1f35b, 0x87e62270, 0x9ee12718, 0xde17a65a, 0xf78890f3,
12921 0x08e23dab, 0x7f942fc1, 0x042e5dee, 0xe2d1e942, 0xe3779122, 0xf8f3ff68,
12922 0x4338c6f8, 0x5d4ca23e, 0x338b4627, 0x7d4ce8c4, 0x5f8c6587, 0xf2e488b0,
12923 0xeffa51f8, 0x933736ed, 0x5c80e687, 0x2fb2323d, 0x3a5237f9, 0xd2927d06,
12924 0x8967dc31, 0x712d3dfc, 0xfabfccc9, 0x3c9d788e, 0xb128a0bb, 0xc536bfb8,
12925 0x2e1be2eb, 0xc724af1d, 0xf9b5e469, 0xbf175da2, 0xa4f24aa5, 0x2e92bc80,
12926 0xca14475e, 0x3ec5f257, 0x5394d144, 0x1999143d, 0xee5136dc, 0x200398a4,
12927 0x5ceecce7, 0x6c7a0f92, 0xb54fa31c, 0xa2309cbe, 0x9b7c6f5b, 0x262c7bfe,
12928 0xe96cf911, 0xc6192512, 0xeb73da09, 0xcae893e1, 0x3d1cf8f6, 0x83bfc1e9,
12929 0xd60abbad, 0x3d73de9d, 0x83c7b255, 0x774e73fa, 0xcc2b1bbc, 0xef28b44f,
12930 0xdfbf302b, 0x2aec044b, 0x39e3e13d, 0xbbf0a013, 0x7e87e810, 0xf4ec6221,
12931 0xc3afe8a1, 0x1075e4f5, 0xf5ca91cf, 0xe3be3c55, 0xf1cf1e2a, 0x737f1e61,
12932 0xa8f38f0d, 0xa9eacfc2, 0xd68238c6, 0xab7facc1, 0xc127e39b, 0x43e3e1c4,
12933 0x529ac97d, 0x3684f781, 0xe2084577, 0x74fe9171, 0xbb69809f, 0xb27e11ab,
12934 0x927da09b, 0x05bcc7d6, 0x6a9534f2, 0xcc1e2247, 0x4f920aee, 0xfbb61fcb,
12935 0xd9b802de, 0x41bc7d14, 0xc340ca4b, 0x9e01b0bd, 0xc93d3d2a, 0xa70262e4,
12936 0x127c2327, 0x53df1664, 0xf4dea3a5, 0xcfee2aaa, 0x83d2a9bb, 0x2b8f1569,
12937 0x84710555, 0x8f294e20, 0xcfc89423, 0x8e145589, 0xbe09fdf0, 0x6655566f,
12938 0x9da67963, 0xa60953ed, 0xc012838a, 0xbb309e25, 0xf49f8267, 0x55cc22cf,
12939 0xfc527e14, 0x7abc8144, 0xe7c3588f, 0x7441e9cd, 0xe1710d9b, 0x2f002794,
12940 0x26486f35, 0x9715e7b8, 0xd63e4cdf, 0xcb38b3d0, 0x3476071b, 0x6013e1d1,
12941 0xe039fbff, 0x2367ce95, 0x59c6179d, 0x9ab0f4e5, 0xa72d7de3, 0xde3cf587,
12942 0x5d382fe7, 0x0fd74a3c, 0x7b0f2af9, 0x1a61b037, 0xc84b8bf3, 0x68b8f130,
12943 0x3bf5a221, 0x8904f38b, 0x3c89d74c, 0x718a60aa, 0x0b31c8ef, 0x247d8bd2,
12944 0x7e508af1, 0x8b0081ec, 0x0a9b9963, 0x1a9c66fb, 0x128272b7, 0xb61f1b37,
12945 0x3e3ccc86, 0x1dcec89c, 0x3de351ad, 0x590e7956, 0xdbdefce1, 0xdcce0e7c,
12946 0xf6bc6043, 0xd20e8851, 0x7b3b97c7, 0x6a3bcd31, 0x7f4dfea9, 0xda5f1eec,
12947 0x5ae7a06a, 0x373f010b, 0xbe7f9d07, 0xf7b1af46, 0xd9080762, 0xa9d8a47f,
12948 0x45074b3c, 0x97f7e283, 0x006c83b5, 0x05730a67, 0xa49b1dec, 0x039054dc,
12949 0xdba2e29b, 0x4cec626d, 0x8e65765f, 0x8d75d1d0, 0xee76c5e4, 0xf4746309,
12950 0x4fe5c35f, 0xdd1c94fc, 0x7cde5577, 0x0bfac31e, 0x30997dda, 0x998ba4af,
12951 0xb709bfc8, 0x553f9745, 0x3887ec92, 0x98a35500, 0x94cff3bc, 0x43d59e99,
12952 0x7539309e, 0xf8f08c81, 0x86467435, 0xbf07d413, 0xe2eb299c, 0x3e03ae19,
12953 0x63710619, 0x02affd19, 0x38a9a07e, 0x89fa4658, 0xf3c26e9f, 0x5fce1aea,
12954 0xda7e730f, 0x11e9f9c0, 0xc40b23e0, 0x677c659f, 0xb0e19e26, 0x58b9549f,
12955 0xfe012ddc, 0xc5549b4f, 0x7187982c, 0x04598f8e, 0x32a89fb8, 0x4317537b,
12956 0x59e2d6be, 0xe31e60a9, 0xed6bfb01, 0xdf7f344a, 0x2ce27d90, 0x6cd7853b,
12957 0x6ac7bf8e, 0xacfe22c7, 0xac014f6e, 0xc188eccb, 0x50d57df3, 0x73b4416b,
12958 0xb33b74c2, 0x2f78508f, 0x4cfa7e84, 0x873ee9cb, 0x66a19981, 0xfdc21666,
12959 0x1d077831, 0xedca7e85, 0xfd218f4c, 0x46b064fd, 0x38f0d40e, 0x93f14471,
12960 0xb0791ae1, 0x0254c872, 0x729e9e76, 0xb83917a0, 0x2ac1c98d, 0x062fef81,
12961 0xf8f156bc, 0x341caadb, 0xc4a35e03, 0x4d7d5ad7, 0xbe7deeb6, 0xb1b8e5c4,
12962 0x3b3b3ade, 0x9e21ad37, 0x59e84fb0, 0x0eb4e14e, 0x3fd914e0, 0xa0e3ba73,
12963 0x3aca20fd, 0x0ceff28c, 0x532083ec, 0x338c3ecc, 0x9e5648b2, 0xe5720f18,
12964 0x4cbf98df, 0x3a827a6f, 0x42c5fe5e, 0x2ef267dc, 0xbffdc78e, 0x213c76a0,
12965 0x2b02ae70, 0xf69de6bd, 0x753fcde9, 0xd74ede01, 0xcdd3fbf2, 0x57fc0052,
12966 0x2eaed74e, 0x4db57cc3, 0xfc4c9c01, 0x882e03e5, 0x69e8b2cb, 0xcf53ef11,
12967 0xd0d3f8c4, 0xcbebefff, 0x7f8d4597, 0xb5ba8ac4, 0x169f2069, 0xef8b5d6d,
12968 0x7bc4ceec, 0xf26ae687, 0xbd415324, 0x96d38d50, 0x0bc58cf7, 0xfb6f5dfa,
12969 0xe8e6de52, 0xf82afde7, 0xca5af415, 0x1eb7a02f, 0x4384e574, 0x7e67ff14,
12970 0xb27d4369, 0x4277f64a, 0x1dab6abe, 0xf8aa905a, 0x1e3ff1e8, 0x0bb4dfb6,
12971 0x76c3c7e4, 0x89483eef, 0xed4bc583, 0xf8ea3e6d, 0x856b60ed, 0x78a7b77b,
12972 0xa78a141c, 0x1bbb3a99, 0xe76b77bb, 0xed621476, 0x97863ca5, 0xbb94bd2b,
12973 0x710c9f98, 0xe7572f47, 0x1f9f9673, 0x07b56d17, 0x03d14656, 0x84f7f116,
12974 0x867df88b, 0xbb672f4a, 0x67462df5, 0x1725ff6a, 0x62f465af, 0xb9e14ba0,
12975 0x9f874851, 0x7f70911d, 0x11bb9e11, 0x5d94b4e3, 0x12fd61b4, 0xf828f3d1,
12976 0x45b79377, 0xdefbd3a4, 0x59f78718, 0x9078861d, 0x09e983a2, 0xb1779a6a,
12977 0xe69fa758, 0xb0ca1605, 0x2c5de79f, 0xf60c7463, 0x93983867, 0x689b5e6f,
12978 0x0396f4e6, 0xb4dd2fed, 0x6fcbd692, 0x264ef463, 0xbed0cbf8, 0x3cf76758,
12979 0x8a0e451c, 0x3717450e, 0x84adbf34, 0x49f873b5, 0x7ffee682, 0x9e8b8f11,
12980 0x45c5917f, 0x493f6e24, 0xf2e73a01, 0xfa9f4229, 0x261db5f8, 0x7ae32f86,
12981 0x133af813, 0x437bd7ba, 0x3efdeb2f, 0x0fd72f5b, 0x1bc6dbf2, 0xf1abf5d6,
12982 0x5915d6d1, 0x5fac04cf, 0x970de3c2, 0xd5de1898, 0x4c1d1bf2, 0x7b69ab0e,
12983 0xa5e22ce5, 0x8f2151fb, 0xb81798ab, 0xcf3e064f, 0x2f171cdb, 0x5f99d668,
12984 0xa7e7473b, 0x1f3b5792, 0x6fe570e3, 0xd02f2f9e, 0x9e3755f0, 0x6baf29fc,
12985 0x86e374f1, 0x3a57533e, 0xbdca1f60, 0x3ee301d6, 0x65f73a5b, 0xbc32fd02,
12986 0xa3fd919d, 0xdd0e502b, 0xcef68ae7, 0xdbc046e5, 0x387ced38, 0xc9fb06de,
12987 0xa37bed48, 0x58e3d18b, 0xbe2b6fb6, 0xdbbbee1f, 0x4451649f, 0xd137977a,
12988 0xe38469f1, 0x59bf0e2c, 0x8e1c70dd, 0x8657547e, 0x7f3a75e3, 0xc8e15ea9,
12989 0x49c2aff1, 0xb0f54efd, 0x18448e99, 0x57f7b097, 0x0aafe3b5, 0x27f1917e,
12990 0xa1defaf0, 0xa2fc824f, 0xf4f812f2, 0x1f3fb3ec, 0xb0f76dad, 0x30bde27d,
12991 0xbabea90e, 0xd83fb57b, 0xdf50797d, 0x0473c93f, 0xadfe6bce, 0xae8aa7a2,
12992 0xa9f630bb, 0x56ae10ce, 0xaeaddfbf, 0x760e186c, 0x20caaad6, 0x40bb54a6,
12993 0x8a6a8bbd, 0x685fd01e, 0x78b46f15, 0xbc39eb54, 0x32b65757, 0x4fd5913b,
12994 0x240f60dc, 0x99c92f8c, 0x333768b1, 0x837af43b, 0x60dcf92c, 0x7bf993a7,
12995 0x5becc967, 0xe7099e97, 0xbf0c84e0, 0x1d6bbe06, 0x4362ffcc, 0xf83f52ca,
12996 0x3ec159ed, 0x22ed0839, 0x81767417, 0x9c8bcd57, 0xf0d4ee94, 0xf58331a3,
12997 0x904252e5, 0x246e1da0, 0x479daefd, 0x2eceab42, 0xd98b846a, 0x12fbc2ea,
12998 0x2ef6e133, 0xeff50f0e, 0x72e5ac64, 0xcddb86b8, 0x197b071e, 0xbb4adf85,
12999 0x35a3f70b, 0x39d898d7, 0xf3c66ac3, 0x40f1b835, 0x8fd6397d, 0x7ac1b0eb,
13000 0x43f3d044, 0xe4427798, 0x7b43111a, 0x238f9009, 0x3ef9008a, 0xf406b424,
13001 0x6d89aed6, 0xd9f7c3f7, 0xe01d5f36, 0xd6d4cbf7, 0x4fd802e3, 0x00c37d73,
13002 0x3fa2b5ce, 0x7ff5a143, 0xa033862d, 0x3a2d1a5e, 0x6bd2cf16, 0xa7daafc0,
13003 0xf16197b9, 0xb1792340, 0xe59afe67, 0xc53dc366, 0xe5b4c3d7, 0x2d946cfb,
13004 0x7bfcf5c6, 0x0b1f0929, 0x74b6ef28, 0xf173c9db, 0x8e51d07d, 0xa00fa44f,
13005 0xbf6c23af, 0x625660be, 0x4dfd99e3, 0x67675579, 0x6aaf2ab6, 0xf3f333c6,
13006 0x57a53d50, 0x74aba7b0, 0x35ecd832, 0xa90d3d01, 0x74b5dfa6, 0x832f4511,
13007 0x72f70671, 0x0fcea11f, 0x3c0007de, 0x6c598bc5, 0xc5d031bf, 0x25fb6ebe,
13008 0xb32a7bfb, 0xaf33c255, 0xa238f962, 0xd1fc60fe, 0xe3edba0f, 0xcdde58ab,
13009 0xd80be572, 0x05a1dc7d, 0xa6d7e8b1, 0xcb7663ce, 0xc3d056da, 0x2ea4b766,
13010 0xd999fb84, 0x0afeebd6, 0x7c293ee9, 0xe2720ec8, 0xe79e2ca7, 0x2abdefdd,
13011 0xfbba69d9, 0xdef8addd, 0xcfdf34fa, 0x04b092e6, 0xb711f7f8, 0x01ebeccc,
13012 0xc405d3e4, 0x0941f3c3, 0x84f7bdce, 0x42de7702, 0x1abef773, 0x628e05b8,
13013 0x5f848f73, 0x82f97403, 0xc368a9ee, 0x7b35db56, 0xd679675e, 0x66fd7bae,
13014 0xb227ae2b, 0x5fae2b5e, 0xf6441f5d, 0xb8eef2c4, 0x912e2cc0, 0x0b498f0a,
13015 0xdb67bad9, 0x7c98fce7, 0xdb39de8b, 0xccafea3a, 0xc7cd887f, 0xa1cf9f08,
13016 0x4ec5ca88, 0xa4e4d787, 0xe1d0ffeb, 0x5eb49d15, 0x669c3589, 0x62fc881e,
13017 0xe8997c81, 0xae8926bb, 0xdf00fcff, 0x438044b0, 0xd2ab9f6b, 0xf4e4df2f,
13018 0xefa726fd, 0xe3bbd337, 0x1ea02718, 0xae024f7d, 0xb3a7066b, 0x47dfbb35,
13019 0x6ff3cc3f, 0xa54b78b0, 0x83eb72a2, 0x49133768, 0x6aac38b4, 0xdfb726fa,
13020 0x0e954e28, 0x0dce3c03, 0x4d1997e3, 0x9fbbf476, 0xf4ea2991, 0x029919f0,
13021 0x1d6b87f7, 0x2f4e877d, 0xd2f5c55d, 0xff80fd9e, 0x859fb181, 0x39e327cb,
13022 0x9eec8f6c, 0xffdff208, 0x85b3a334, 0x293c2853, 0x13ace5dd, 0xfc70def0,
13023 0xf20236a9, 0x1c4d6170, 0x85f3fb81, 0x20fbfc0f, 0xd650c788, 0x81b734aa,
13024 0x1e080c9c, 0x8b25bfb0, 0x467e324b, 0x10e9b5e7, 0xbf2187db, 0xf0e9e604,
13025 0x3d8d0e2a, 0xc8aa43ba, 0xdf5d0370, 0x3c82f0eb, 0xf7877f98, 0x6fe78c03,
13026 0x7b041d0e, 0xf99ebab7, 0x00d928f7, 0x9b41f9ff, 0x312b5317, 0x36b950c7,
13027 0x90ac4cdf, 0x6cc4cb26, 0x73cb7c83, 0x1e4bb05f, 0x18e4eeb6, 0xdfdf6562,
13028 0x72f404b8, 0x5bac835d, 0x3ea0a8f7, 0x3eb37d7f, 0xe7d2119f, 0xe7d11ec7,
13029 0x431a83b7, 0xffc395f1, 0xfda1d4ce, 0x877f0216, 0x0b45f8a6, 0x0cbeb3fa,
13030 0x05fa007b, 0x4dde50da, 0x82c96e2e, 0x5e4fd6fb, 0x9ce09a70, 0xdf9befbf,
13031 0x786d7de2, 0xc9e31d87, 0x0c53fc1f, 0xc07f0189, 0xa15b6d17, 0x04e298bc,
13032 0x2fc577ec, 0x0ec0eada, 0x7a8467b2, 0x5fa00d1e, 0x31bf9ec5, 0x76f0f9bf,
13033 0x6fee004b, 0xdcfbd93f, 0x9f6f400b, 0xfa87ef6c, 0xdf82cbce, 0xd7f9fd04,
13034 0xc4e67c33, 0x272d7db0, 0xde33d286, 0x75cfebbb, 0x1c993bf7, 0x1e6caf69,
13035 0x4e59fb01, 0xb47fb33c, 0x011c1e57, 0x8f0e5cfb, 0x49eaae43, 0xbc7e3c39,
13036 0x274fea9b, 0xe51439d9, 0x0fce70c2, 0xb2058179, 0xd5fa01d7, 0x5390188a,
13037 0x79e5675d, 0xac358fe0, 0x15470f56, 0xf406d7cf, 0x7cf92bdf, 0xf7cd1016,
13038 0x56f7b874, 0xbd00a4d6, 0xbea2433d, 0xf9c35c7b, 0x65e7f9e8, 0xf22fbcf5,
13039 0xd14468f8, 0xc88acfbc, 0x1facb273, 0xbe0025f8, 0x17be4606, 0xfb55c61b,
13040 0xfffbca9f, 0x92fccacc, 0xce1c3813, 0x7d411e55, 0xaddf5ba0, 0x68a77af4,
13041 0x07b579f2, 0xfc23e693, 0xd02d260e, 0x1fb6f39e, 0xfe039a4e, 0xfc660d36,
13042 0xb32553bb, 0x27247d9f, 0x418bbe01, 0x03942798, 0xaf823b1c, 0xd51ea0b9,
13043 0xfd68c767, 0x6f6bf257, 0xecd14ef2, 0xce95dfd7, 0xbb65e3bb, 0xca5e5c19,
13044 0x16fdbdce, 0xa2cdbba0, 0x0715aa07, 0x1479bcef, 0x84b37bc0, 0x764b72ef,
13045 0xbdb7184a, 0xb406eebc, 0xbe371453, 0xffe31533, 0x03df393d, 0x9332caf3,
13046 0x9a0c715c, 0xf480ee18, 0x8c6ecb4c, 0x61fc57af, 0x60566c8d, 0xa3ba7abe,
13047 0xa3f08c74, 0x6dd6541a, 0x15de53c0, 0x7eab3fe8, 0x30b7e237, 0xc46f6fa0,
13048 0x1ba72b53, 0x8b5c33fa, 0x3ebd636f, 0x8ef8fdd3, 0x953964b2, 0x543b1a63,
13049 0xf46aa9c9, 0x038e33d7, 0xa344da37, 0x7703eca7, 0x1dafe01b, 0xfe836fcc,
13050 0xee2cd608, 0xe5883ad7, 0xd0200e31, 0x047fac15, 0x3bc0a299, 0x34c8dbcc,
13051 0xd1b95548, 0x0d1c1d91, 0xda165ff5, 0xf615fd9e, 0xed7e44e7, 0x2e308770,
13052 0x3efe5f62, 0x796143b5, 0xa83aeff5, 0x362d45e5, 0xe4f8f3f4, 0x71f28cbc,
13053 0x4197f805, 0x266c17fd, 0x3ebfdd13, 0x1267d9d9, 0x04762df8, 0x73dcbc59,
13054 0xe4933ec1, 0x8d77d96f, 0x0fdd4172, 0x74afc04f, 0xe9c2fcdf, 0x4b7ec30d,
13055 0xcebf3156, 0x19153ee4, 0xa4f05115, 0x2b904bb6, 0x123ce032, 0xd9e1d7be,
13056 0xa7f2708a, 0xc1723ec3, 0x81f68297, 0x121edcf9, 0x06fdceef, 0xbad275fa,
13057 0xfe2ffa5e, 0xe815b888, 0x73d163eb, 0xe4507bbf, 0xa6516f9e, 0x90f3df0f,
13058 0xb45cec55, 0x66424cd0, 0x842eefaa, 0xe63463fd, 0xb85bbf71, 0xa6ff4059,
13059 0xebf41b45, 0xdaad7881, 0x405087bf, 0x22dfb1aa, 0x60b4c412, 0x10bcbeb3,
13060 0xf81723f6, 0xfc7bb067, 0xb97d7aa2, 0xa4a84efa, 0x1a25b2f1, 0xea20bedc,
13061 0x2ec9bcfa, 0xb36e179a, 0xdbeefce2, 0x35eecb14, 0x7d85e264, 0x89c9bc30,
13062 0xf898bc72, 0xbe3f3bd8, 0x303f960f, 0xd288bbdf, 0x85f2d767, 0x307d45de,
13063 0x7d81077e, 0xf895b16f, 0x1e58635d, 0x0b2017e2, 0x38b29f21, 0xed4eb051,
13064 0x29e2963b, 0x15c03424, 0x53ac2f59, 0x65de4e5b, 0x116e2cf8, 0xbd60a342,
13065 0x64427ef0, 0x2bd6d5eb, 0x692870e1, 0x11ece8b4, 0x0a7fe0a5, 0x974d337e,
13066 0xb97eba2d, 0x8fdd1f3f, 0x69e28d89, 0x0ddcb753, 0x4fcd1b5c, 0xd78738fe,
13067 0x52f33ba6, 0x051f3f81, 0x072fb33d, 0x173d3668, 0x61cc9083, 0x71d2b780,
13068 0xe776c662, 0x256b3cb1, 0x647d4fcb, 0x51e90fe0, 0x1bcefe1b, 0x142c6fde,
13069 0xf7875f73, 0x7db9cf57, 0x71d1763f, 0x69bc9a16, 0xef53e466, 0x5cd7f450,
13070 0xc4ffd6ce, 0x2b6b8a98, 0x557b9ca2, 0x042e3e7c, 0xbfd1bef1, 0xceabed97,
13071 0x7da4b0cc, 0xc5c8b45f, 0xa1ec4fe4, 0x10777c36, 0xbbe02dde, 0x138527c7,
13072 0xc9f02ef8, 0xce04291f, 0x6f1429e5, 0x149f1f20, 0xbf882ac8, 0x7334d995,
13073 0xbf806bc9, 0xa3d418cc, 0x8a269b4a, 0x3f5c0ea5, 0x15eca3d3, 0x99ef7075,
13074 0x18f86f3c, 0xeeba6ba0, 0xff01b779, 0x5b8414bb, 0x41d183aa, 0xfa7f4aca,
13075 0x7e3091d2, 0x80d792ee, 0xe0c546ef, 0x0a64d93b, 0xa63c672b, 0x4a2f40eb,
13076 0x41071921, 0x574ca78e, 0x772d80c6, 0x938d8b93, 0xcde71268, 0x0c6dfd04,
13077 0x243fc7cb, 0x7122b778, 0x2575c46d, 0x369fd85b, 0x7fa0ef82, 0x804ec15a,
13078 0xe78601e5, 0x301915c9, 0x9620f27e, 0xf421c826, 0x8dda3a53, 0xcdea1f77,
13079 0xe504dccb, 0x134bb2f2, 0xfb69e393, 0xc0f41da3, 0xd1d5e54c, 0x1d9eaafe,
13080 0x439e8072, 0xf5670f06, 0x2cb15eb9, 0x27e5f983, 0x10faa9a4, 0x7925d7ab,
13081 0xfc82c763, 0xdbe9877c, 0xb1bc3b9f, 0x837737e0, 0xb80fdd1c, 0xfca9e386,
13082 0x34049da2, 0xd67cbff2, 0xa4def897, 0xf74ba2fc, 0x69c9e21d, 0x0a4b49fd,
13083 0xe3dc610e, 0x7e8ad252, 0xbd41a5c9, 0x310debff, 0xe955c7d1, 0x48a2fcbc,
13084 0x95c751fc, 0xf62fdff5, 0xd13efe21, 0xbfe925ea, 0xf9f4145f, 0x3d78afe6,
13085 0xd9277e33, 0xc7382e6d, 0x077d874d, 0xe4c049e4, 0xe08fae97, 0xa6ddd3a5,
13086 0x153a6fdb, 0x71e2ef96, 0xb572d575, 0x3259ceff, 0xc6139f7f, 0xa92a3a71,
13087 0x79f0a240, 0xb453e5aa, 0x1cb496a3, 0x74a8f844, 0x9d938111, 0x4a7035f8,
13088 0x990d6aaa, 0xfeff8f28, 0x476b4591, 0x72514b5e, 0x3fb3f388, 0xf297ad6f,
13089 0x2fc4126f, 0x3db7f0d7, 0x51df9bb3, 0x89326ccc, 0xbf99dedc, 0x4d04ca76,
13090 0x6eefd79e, 0x21f82fef, 0x648e6794, 0xa47bdfed, 0x072b77f0, 0x5d13e447,
13091 0x53ae5a47, 0xf21ab793, 0xa51f9a0e, 0xe50dbbc9, 0x14f28609, 0xab3fbe43,
13092 0xa50ce1df, 0xda421e89, 0x21fd291e, 0x8eb95dfc, 0x885cd0d4, 0xac41b038,
13093 0xddfc21f8, 0xf64cd2c9, 0x5acb1477, 0xb3730f04, 0xf32bf062, 0x87307bb0,
13094 0x385e4da7, 0xfad0e012, 0x9283c83a, 0xfa0dc166, 0x33b823be, 0xa7687984,
13095 0xd905da68, 0xe092ad3b, 0x6bd76c09, 0xc84dc3ff, 0x3f0f0fcf, 0xe4aef589,
13096 0xeba644ef, 0xf37be0fd, 0x7c9874b3, 0x53df6117, 0xec770ce3, 0x77f23f7c,
13097 0xcef7e8ed, 0x9461ef54, 0xaaf786a7, 0x471f30e5, 0x38545f84, 0x02fc3c3e,
13098 0xf3fc5dc6, 0x40f796a8, 0xfb2fb00d, 0x95e80574, 0x1e9e961f, 0xc4167a07,
13099 0xe3fd846e, 0x2d702171, 0x114f47ec, 0xee30b5df, 0x0e43a5bd, 0x39949fc2,
13100 0x816db52e, 0x1ec31050, 0x3ff08f5d, 0x001b6cee, 0xdae8927f, 0x4f961ad8,
13101 0x1008c36c, 0xfd37626b, 0x39fb4cd0, 0x806da03e, 0xc547e689, 0x43e5661e,
13102 0xfe40b6da, 0xb0dfd8ce, 0x036d51f2, 0x1d1c3744, 0xdb7f111a, 0x3ef9d1dc,
13103 0x1bc9962d, 0x06437e75, 0x4163537b, 0xfb612a8f, 0xb4873c0e, 0xb73ab952,
13104 0x6d8edce8, 0xff731e14, 0x6ef28ed5, 0x3fedc75b, 0x3fb1fa66, 0x92a0fc17,
13105 0x5f71bc39, 0x466ef944, 0xf61521bd, 0x3e08f8c2, 0x0aad699d, 0x2a231bee,
13106 0x905e8276, 0xee24773c, 0xef4e9d1b, 0x9171d8da, 0x9a048bf4, 0x8dac79d2,
13107 0x2ef93375, 0x5b3df09a, 0xd44e83f2, 0xf1e51e9f, 0x21df29ba, 0x5e38387d,
13108 0x8cf5f2c6, 0xa1e7658d, 0xd84dd744, 0xaf5cddcf, 0xd81f59ad, 0xfff0a36e,
13109 0xde0e7a93, 0x39e4f4c8, 0xc4ee5475, 0x37817f82, 0x1cc9e415, 0x8c8f07b0,
13110 0xbfbd55e4, 0x1de68326, 0xcd58f391, 0x36aa6f4c, 0x1d4d782e, 0x55e5572b,
13111 0xaf6b3a4d, 0x55c95bee, 0x8fc93e0c, 0xd615bb5e, 0xff333761, 0x86b3c581,
13112 0x7a815d6e, 0x5f386dc0, 0xc2a6f5e2, 0xe154fcb9, 0xa3e81340, 0x0da67e2a,
13113 0xeb82def6, 0x2a38f7e1, 0xd7f1d49e, 0x142f75f2, 0xf6011ea9, 0xe10fb774,
13114 0xd18af549, 0xe99d72ec, 0x5ae96b15, 0x7c2a1f01, 0x1c6db989, 0x045fff7c,
13115 0x0cffa5a7, 0x7eddfd38, 0xbc7bd3dc, 0xfd0359c7, 0xad3f2e97, 0xe1c38f7f,
13116 0x9210b8fe, 0xf1353392, 0x3877e853, 0xf2eade77, 0x735622fd, 0xc1f735bf,
13117 0xd53fd452, 0xe5ffd8f5, 0x917769a5, 0xd469fc9e, 0xc9ff8f0f, 0x02ec01ba,
13118 0xca20e5c7, 0x263fe3e3, 0x38e42ef8, 0xeaa5678f, 0x5aff59b7, 0x6dce147c,
13119 0x222b11ff, 0x7a54d87d, 0xe6777210, 0xa7aef851, 0x3bbc39db, 0xd464fd57,
13120 0xc786bafd, 0xe079ada1, 0xd1af7c3a, 0x3cf0da45, 0x2826cfee, 0x67cbbb3f,
13121 0x4a72c50f, 0xc81b7e27, 0x8c18c289, 0x41935fc7, 0xcd497df0, 0x0e5811ec,
13122 0xc7f458e7, 0x71c56d99, 0x3a32666a, 0x478c29ac, 0x5dc8217b, 0x746f5b80,
13123 0xecc55494, 0x1decc41f, 0x7f1fbdad, 0xf9f9962f, 0x76db33db, 0xed7a0fbf,
13124 0xb5ea1b06, 0x57bc4280, 0xf1c64ea9, 0x8fec3d28, 0xcd97fdc5, 0xa963e163,
13125 0x5c718781, 0xd603da0f, 0x51f3bd3a, 0xaeccfdce, 0xdb37fcc0, 0x18eb3ac8,
13126 0x5590e638, 0x7cf92f28, 0xe813f548, 0xeb8f3157, 0x5c151f89, 0x721e8270,
13127 0x1edbb634, 0xf9f385e0, 0x17cac202, 0x013f643c, 0x0f05abe7, 0x64b778b1,
13128 0xfd5e4ddd, 0x6b9d093d, 0xf9d3d812, 0x09d86d4f, 0x3b41f070, 0x1ffff417,
13129 0xe41f784e, 0xc3bd887b, 0x7eda7e25, 0x47fda478, 0x9760f7c0, 0x49fcd917,
13130 0x16895da5, 0x58a3f4e7, 0xfd5397ee, 0x9e3b5784, 0x5fb18e3a, 0x036c8e7a,
13131 0x0f70a37e, 0xf0a83bc1, 0x59dfd8cf, 0x4137ce30, 0x46c2ff0e, 0x8a56e7cb,
13132 0x3c292b71, 0xb89dcb7d, 0xf3be755e, 0xa237c392, 0x7fd0c29d, 0x0b2cbdbb,
13133 0x79eae7ec, 0x39a43c88, 0xe45c21ff, 0xf8845e48, 0x573c6101, 0xcfcef8f5,
13134 0x2873c6cd, 0x68b37f21, 0x2bbf75eb, 0xfcc30450, 0x82295d39, 0xe3e6f019,
13135 0x1cb2fef7, 0xeb720b9e, 0x50eb02ff, 0x8000589e, 0x00008000, 0x00088b1f,
13136 0x00000000, 0x7dc5ff00, 0xd5547c0b, 0x73b9f899, 0x3332bcef, 0x49324cc9,
13137 0x9b8f2126, 0x80402107, 0x52024c49, 0x1878431f, 0xa4076b35, 0x438b5b16,
13138 0x921123c2, 0xb175b689, 0x5100cb65, 0x8d042208, 0x41380abc, 0xbb6bba50,
13139 0x060222c1, 0xb6a2d11a, 0x6eb42fea, 0xfdfeed57, 0x58f88845, 0x16544649,
13140 0xefffad5b, 0x99b9cefb, 0x514493b9, 0x67f4ddbb, 0x739ee72f, 0x77cef9cf,
13141 0xcef9f7be, 0xe99a1619, 0xf4662deb, 0xfc3e79f7, 0x33577f87, 0x3034e896,
13142 0x7cd8ca96, 0x96773599, 0xeb47df44, 0x6d67aa25, 0x34967d5b, 0x0bbc02c6,
13143 0x66f536e6, 0x607da1fb, 0x694df9b9, 0xeb88bc22, 0x6330b19f, 0xb56d8c15,
13144 0x993590b2, 0xf4126db1, 0xbbcf0e53, 0x7935e16c, 0x23580d8c, 0xc602b08f,
13145 0x59afc782, 0x1bfbef80, 0x4d065412, 0x08589876, 0x8ee3a1cb, 0x576c3ef0,
13146 0x64c45bd4, 0x7c1807a8, 0x24be786e, 0x0d248477, 0x5e9ac608, 0x87acf792,
13147 0xae47fd76, 0xb2acfde5, 0x41ca0ca9, 0xb8c136a8, 0x575fd0c1, 0xa4c644b2,
13148 0xff1a1639, 0x6c2921cc, 0x66c3fac6, 0x85e0d3e6, 0xbfe1faff, 0x2f1832fa,
13149 0x2719086c, 0x102b13c1, 0x8236c38e, 0x40da6603, 0x813f7de3, 0x9bf187ad,
13150 0x00cf920c, 0x8db74df5, 0xf0e1af0b, 0x67e01858, 0xc9ad0099, 0xe8245ac0,
13151 0xb5e0532f, 0xe8ba70c9, 0xa75e128e, 0xf8a5bb40, 0x3dda950f, 0xcb9c012b,
13152 0x647a1b2c, 0xe1399380, 0x0dbfa83f, 0xeba2f3eb, 0xbfe1b4d0, 0x3479c33f,
13153 0x2db8041d, 0x3d97b851, 0x6dc79fa6, 0x27ad14cc, 0x7eb443b8, 0x2f8e72b6,
13154 0x47858336, 0x510ebc03, 0x84f755b6, 0xf2c7c465, 0x65ccece9, 0xef44f4d0,
13155 0xeb1dbf2c, 0x3c2d593b, 0x5f30ef83, 0xda9ee018, 0x28ccf1d5, 0xeeaaef68,
13156 0x06e9c6c9, 0xa0b1ff97, 0x3ae8b2ef, 0xde5e706b, 0x766659b5, 0x03be8f1a,
13157 0xec077c50, 0x9cec6ed4, 0xd5cfb109, 0x41aa5df4, 0xebc715be, 0x881957c5,
13158 0x04865f1c, 0xc8696ce3, 0xdabae037, 0xb0057814, 0xb31b6a2e, 0xd9e11567,
13159 0xc1c73457, 0xec8983d8, 0xd3e13f56, 0xfe87e95b, 0x2d56751e, 0xe97f4274,
13160 0x9d5baaae, 0xbf1c7ca9, 0x029fa703, 0x6ba50d40, 0x47e1a9ed, 0xd05e976b,
13161 0x1f6cda5c, 0xc4db9db9, 0x9ed916f1, 0xf083de14, 0x17951228, 0xb1d8deff,
13162 0x8853e09e, 0x95d8ee6e, 0xebf84617, 0xe9099b59, 0x9b0b197c, 0x5b178e90,
13163 0xe8112858, 0x4b343162, 0x6d92e782, 0xacc6a666, 0x5f58435f, 0xae1ced66,
13164 0xd3f74a65, 0x4dd22252, 0x74b3f50f, 0xb2ddbebf, 0x01dbac19, 0xd6168df5,
13165 0xa767c36d, 0x4589bebe, 0xe1e08e08, 0xfebacdcf, 0xc3ad1b59, 0xc8632b76,
13166 0xbe6549a7, 0xfe01bbbc, 0xef460bc8, 0xb7cfa01e, 0x7868bac4, 0x35567648,
13167 0x64139e20, 0xb233cd03, 0x03de16ca, 0xb033ecf3, 0x4de75c7a, 0x1ceb762e,
13168 0x64aff678, 0xa12342be, 0x77ae2263, 0x1fd73e3c, 0x7d23d6b5, 0x13f9416c,
13169 0x38373f43, 0x5ee7848d, 0xbe47ab13, 0xfd0d5ca9, 0xa6a5c8c5, 0xfc01ec9b,
13170 0x9726976e, 0xc46f9d60, 0xa86b6675, 0x9e91ed8c, 0x4fe32e12, 0x83bdbbed,
13171 0xa7f337ed, 0x4b7bf9c2, 0xae074243, 0x0cee9453, 0xc4aee88c, 0xf7c00a6f,
13172 0x583c8547, 0x38fdf960, 0x40a3f7a4, 0xa1f7c808, 0x0b972b4e, 0x72fe738a,
13173 0xa77d1f28, 0x455ebbc4, 0xe272e0fa, 0xd812f7e8, 0xf9f2186a, 0xdef5fef7,
13174 0xfcfea197, 0x0cd5263b, 0x46910bf5, 0x4a8f3d60, 0x85e387cc, 0xf787309e,
13175 0xc065bbc1, 0xb2cf08b6, 0x28c213e3, 0x02990edf, 0x38e117db, 0xfbbd1b8f,
13176 0x8965bbe0, 0x423c5fe1, 0xa05e19f5, 0x9194f644, 0x88e861d3, 0x109f7f8d,
13177 0xb95fb7fe, 0x1bdd3eb1, 0xac7bf682, 0x07c81381, 0x09356699, 0x97bf65fb,
13178 0xbba71f19, 0x3bf805c8, 0x824af38d, 0x38495427, 0xfa83974e, 0x58cafe01,
13179 0x699cfd04, 0x80f9a74d, 0x38e1f4dc, 0xf79a3667, 0x32dcdca0, 0xed44ae38,
13180 0xb3fd1b4f, 0xfa7ca032, 0x2aef5289, 0x9bf01aa8, 0x7f404dba, 0x5f4b4dc1,
13181 0xea17a064, 0xc46eea0c, 0xa36e3b0f, 0x11eb6879, 0x06a4b8dc, 0xadb783eb,
13182 0xdae501b8, 0x7289fc48, 0xbbc8c59a, 0x41c9167e, 0x9f51dffa, 0xfa8dd9df,
13183 0x57ac6ba0, 0x2c0f5aa6, 0x9387d03e, 0x7233edb7, 0x198e46fc, 0xb52f4f89,
13184 0xa50ba47f, 0x1c0feb92, 0x94f20827, 0xf242fc69, 0x0f2ca634, 0x18ebe657,
13185 0xfc4e9a3c, 0xdb3f5f1f, 0xf908f811, 0xfffee9a7, 0x8ab96379, 0x9e4845e3,
13186 0xe254b6b1, 0xdbbb8033, 0x6df7df02, 0xe55f1077, 0xf70f50ae, 0x741ebae2,
13187 0x335d3cd1, 0xcb03b27c, 0x3ca8f33b, 0x1c6dc855, 0xe2c6f516, 0xcaf48c29,
13188 0x58b59962, 0xd17de8ca, 0xf67f6876, 0xcf5a6c89, 0xceb666c5, 0x36ce7c02,
13189 0xdb3ffa70, 0xf00a7201, 0x25ee6753, 0x4dfecb39, 0xb518fb62, 0xcb76c16b,
13190 0xb28c9060, 0xb94378a1, 0x385bc3a5, 0x7ffa0ca6, 0xe907676a, 0x8a720601,
13191 0x9a05d8c5, 0xa4f9431c, 0xcdfd9efb, 0x4863c7ac, 0xc7c4b793, 0xd9f4a930,
13192 0x28f2a213, 0x72cfe9d9, 0x30a16055, 0x5677f11d, 0x04e9dc0e, 0x8584b6f9,
13193 0xb0363e48, 0xe36a7a6e, 0x72e5bc81, 0x2ee5c2d7, 0x412e133e, 0x3ac6defe,
13194 0xa2366e49, 0xee4e1a44, 0x3bb900ae, 0xcbb96471, 0xe2297358, 0xdd8b7835,
13195 0x221e788b, 0xd77c857f, 0xc4dd31d6, 0x15d4f0e5, 0x44959961, 0xe89a90f1,
13196 0x115a969b, 0x57c1abd5, 0x1275162d, 0x1f2cfd96, 0xda63ade5, 0x7d41a7bf,
13197 0x943e6150, 0xe61eb69b, 0xbbf780eb, 0xf3f5fd84, 0xf1fa9534, 0x185d3898,
13198 0x852b3f15, 0x9eaacafa, 0x49f2036e, 0xbca2732a, 0xfef0f477, 0xbbe03977,
13199 0xcb8efc32, 0x2defc1cd, 0xe62125ac, 0x56a3aafb, 0x470ba3a2, 0xe933611c,
13200 0x0bae40c3, 0xb3fb4bfa, 0xfea4ec99, 0xf3920ea3, 0xaf3646fd, 0xd1bbda13,
13201 0xbcf5a21e, 0xaefbfa87, 0x219e8f2b, 0x218a3556, 0x8dd74aed, 0xecd65642,
13202 0x9ebcc683, 0x1edf489b, 0xc7c8ab30, 0x77bd5c17, 0x63c61962, 0xedbf2728,
13203 0xf05da952, 0x9fd2f4e0, 0xdfa0fbc2, 0x0dd8e5ee, 0x98bd2294, 0x64dd1fe5,
13204 0x259b7581, 0x05dc88af, 0xdb663670, 0x6787289d, 0x9fd7fee4, 0xbbf2866e,
13205 0x8ccc8d07, 0xfa6fbeeb, 0xb23f963c, 0x1b08689c, 0xd0c6f74f, 0xfafdd2eb,
13206 0xbea76372, 0x2fac3c1c, 0xb872e1df, 0xde278ecf, 0xf40e7ef4, 0xbf373664,
13207 0x9af001d3, 0xdc93329f, 0xf815debc, 0x26e7a467, 0xe224e443, 0xfefb9cd1,
13208 0x73ae00c4, 0x3e1207d7, 0x3d2640cd, 0xc8bf1c25, 0x0bac1757, 0xd8c39d72,
13209 0x857b51eb, 0x47840c59, 0x513d06b0, 0x20e410f9, 0xdef95f01, 0xbfe61a7d,
13210 0x73824e78, 0xd5f1bd35, 0xbda25454, 0xe0b23042, 0x45df6bb6, 0x35da1ebb,
13211 0x0d989c90, 0xfaae00ed, 0x2f6e5c6d, 0xc8893d63, 0xd7604d0f, 0x7f096058,
13212 0xb1f4e2e7, 0xd95225b4, 0x4f6cff0d, 0x708b1eae, 0x7e299f2a, 0xd8b5ff5c,
13213 0xf61d8c6f, 0x1dfb8b90, 0xdb5bf74b, 0xa1f862fa, 0x2ba5d3b1, 0xb4670f07,
13214 0x5de2c5f5, 0x25533ff0, 0xb6ded625, 0xb90f021b, 0x7b0f9152, 0xfc60d34d,
13215 0x88fb3fab, 0xe592f7f4, 0x0a9d90cf, 0xedc058f3, 0x728aab36, 0x4f5dc975,
13216 0x2fcd7bd3, 0x276d9b38, 0xed99e0bf, 0x99765e66, 0x17767ca8, 0x74965bf7,
13217 0xa79c614a, 0xca62e734, 0xbba79434, 0x1b334e8c, 0x3c78d78a, 0x3ff3bdbe,
13218 0xf54c1913, 0xfa3a426d, 0x1bb71213, 0x6489cd9c, 0x89cdaa9f, 0xb7051f68,
13219 0xca2ef35d, 0x64bb25a9, 0x7635ea2f, 0xcd1de1cc, 0xec733cb0, 0xf3f63b22,
13220 0x8034ca61, 0x4cf77da3, 0x65ef4ca7, 0x48f9187f, 0x0d5cf5f1, 0x93dd95ef,
13221 0x67b7e455, 0x97f87177, 0x208f2cb8, 0x99fd5d1d, 0x62b2764c, 0xcfb40160,
13222 0xb1be4dda, 0xceeab7c8, 0x7d70b37d, 0x699d9ede, 0x94bff6a0, 0xe2f11398,
13223 0xef869e5a, 0x1f8a4897, 0x5b7eb4f9, 0x7eac4d43, 0x1325d5be, 0x5dcb4dbf,
13224 0x276bd691, 0xf509babe, 0xe02ee355, 0xce7f1c23, 0xd9ba7feb, 0x692be51d,
13225 0xa61bb6ce, 0x1a8fff62, 0x8377c8bd, 0x3fe7777a, 0x5fe17d11, 0x6dca2577,
13226 0xca6faf8e, 0xc69b6667, 0x2845cd27, 0x6eac973f, 0x630e722e, 0xc9f20fcf,
13227 0x6f97ce4e, 0xb7ee24b9, 0xeceb2566, 0x00fc91dd, 0x87c1b17b, 0x9978b7f8,
13228 0xd33c1f6f, 0x7f430dc1, 0xa159212f, 0x136484fa, 0xe4f949e1, 0xa92ffd8e,
13229 0x3e071768, 0x65ccfa44, 0x27d452be, 0x9559c46a, 0xec2b7484, 0xdb93b605,
13230 0x907f6081, 0x9525b5bd, 0xc63eb23d, 0xfe8933ff, 0x8a7c4e40, 0xb5ffa272,
13231 0x7e224f4f, 0x9fde729b, 0x783afa88, 0x0a9323f1, 0x4977b5f3, 0x5eedbf24,
13232 0x09ba433f, 0x0b66cd76, 0x3772a24b, 0x217ae5e8, 0x26375e7e, 0x751cb91b,
13233 0xab9fa847, 0xb73f3852, 0xd3d118bb, 0x6409e58e, 0x8770ee97, 0x57f408ad,
13234 0x29f65be5, 0xe7587568, 0x675f0b06, 0xfb5fdecb, 0xb0f3a464, 0x658d1ce4,
13235 0x40c7f395, 0x0cb0fcfd, 0xb7bbbce3, 0x83e54420, 0xd432bcd3, 0xbc3ef7d9,
13236 0x74f11f2e, 0xf6c5e8d8, 0x226f6f76, 0xbdddefce, 0x7e711267, 0x9a657bf5,
13237 0x83f87d77, 0x512545b4, 0x2917f139, 0x768c9050, 0xc7b25b82, 0xf7778bca,
13238 0xd0b6987e, 0xd253fdce, 0xe3c3e597, 0xad35dd25, 0xfabfbf18, 0xef2ebe2a,
13239 0x461cd2fd, 0x159ef839, 0xfc8c59f4, 0xf5c1cf7d, 0xcd64d4db, 0x41cce8cf,
13240 0x565833fd, 0xfc701ac6, 0xfcf9391f, 0x1ccea6dd, 0x96ffcbe4, 0xb6dcfdf4,
13241 0x9061664e, 0x24eb0d4b, 0xff990616, 0xcc9e2fde, 0xeefff941, 0x6a7327be,
13242 0xff8be063, 0xd0ce7b4e, 0x9af113c6, 0xd78da65a, 0xd5e3859d, 0xa26fcd7a,
13243 0x66eb619c, 0x26f906fa, 0xdb633f9f, 0x8a3e6db3, 0xd7000ca7, 0xdf6a1d22,
13244 0xf827d40d, 0xcc2eb82c, 0x4e90c612, 0x6ddc976d, 0xbe7cfec6, 0xdfda3742,
13245 0xfd71f7da, 0x927a0ab7, 0xa7e44b0e, 0x24224ada, 0xfcb6bf9f, 0x13d7e8f7,
13246 0x4c98d9d6, 0x72723ff2, 0x30fa2314, 0x4d4cde21, 0x55f50576, 0x5f4e1ada,
13247 0xc81b1f91, 0x2427701f, 0x3f60644e, 0x763d3299, 0x17576f94, 0x9218b425,
13248 0x184e7df0, 0x166767db, 0x2aa177d3, 0x34a1ff4e, 0x0c9e7146, 0xff212cd6,
13249 0x97b72732, 0xe730a6b3, 0x4fee287a, 0x878c76e6, 0x05c9b779, 0xc612feb4,
13250 0x68bc3425, 0x08e901fa, 0x927be5e5, 0xea48e885, 0x947ec892, 0xb1f39d0d,
13251 0xeae891df, 0x8ad75c6e, 0x960d5d28, 0xb57441ff, 0x086f1b49, 0xa254055d,
13252 0x78658f2b, 0xf62552ba, 0x90b3da95, 0x74affd1f, 0x424daf81, 0x6c7e44fe,
13253 0x4016f1e1, 0x46b7ce19, 0xb16357f4, 0x47a8cb77, 0x63f7c6bc, 0xc13b8fe3,
13254 0x25ff45ee, 0x787ced03, 0x40b35a8e, 0x3d6375a5, 0xdaefe8bd, 0x5f485b26,
13255 0xc9e86bde, 0x7d263b43, 0xa401f35c, 0x25f9f48f, 0x6fc86b65, 0x5ea172cb,
13256 0x714b5d40, 0xfdd3e587, 0x7e808edc, 0x9b668e91, 0xba6b3fc8, 0xdb9f9a6b,
13257 0x2fc4d511, 0x15560dc1, 0xaef4e0f5, 0xf76455bc, 0x335e60af, 0xf6c771d1,
13258 0x9c2f18c5, 0xaca2f76b, 0x213c62b3, 0xe7afe705, 0x93a956bb, 0xb5d0f1ec,
13259 0x5d728bcc, 0xbbb6478b, 0x14ff777a, 0x09437ff5, 0xf183f7f9, 0x7a4642c9,
13260 0xcbe5dda3, 0x1ebc0648, 0xa78f1bfa, 0x194297b5, 0xf5894f9e, 0xcbed9f6c,
13261 0x76b94170, 0xdef09583, 0x07ebc1de, 0x49a0801c, 0xfea4a714, 0xeb859258,
13262 0x81f2a1a1, 0x53699be2, 0x0db7f698, 0xb95a99cb, 0x41d92b6d, 0xe7b7ff1a,
13263 0x251c7871, 0xc8b43cfe, 0xf1dcdf2f, 0x47f0027c, 0xa68dc61a, 0xb42117d2,
13264 0xc92e29f7, 0x7cb614cb, 0x648000d0, 0xeb27f162, 0x5b115c67, 0xdfa3ede6,
13265 0x7ac7af5b, 0xf583bfd0, 0x65e83608, 0x02b3ecad, 0xd11d6b1c, 0x60ec057a,
13266 0x7c4961cb, 0x3375e4ff, 0x92fe610b, 0x93f43f18, 0xafc61f56, 0x5e374cac,
13267 0x5c4a7c2c, 0xdfe846ff, 0x77ed6aae, 0x0684cf56, 0xe569960f, 0xb2f9d78f,
13268 0xbea33fa0, 0xf8a9423f, 0x78da0b1e, 0x63383dcf, 0xa8ac86fd, 0xc2f6007d,
13269 0x34cf2827, 0xebed613b, 0x60936d35, 0x43f39b2c, 0x4d5fea13, 0x12dd07df,
13270 0xfcf121d9, 0xbe914b6a, 0x085d7d99, 0xcea575f6, 0x70a5b6be, 0xb2167afb,
13271 0x2425f824, 0xfc2b83bf, 0xb05bed0c, 0xbeb0924b, 0xcff7b5ff, 0xfdf50d3e,
13272 0x7272fe73, 0x6eed8a94, 0x557e8f9f, 0xf242a2f0, 0x0e5fb837, 0x9637c04b,
13273 0x83576e2e, 0xb478a73e, 0x39b73f46, 0x42b8fd05, 0xed6ce30c, 0xa40aa4c7,
13274 0x73a3f077, 0xf96b03be, 0x665f14a3, 0x9fd4454a, 0x65f79f8c, 0x189e3c29,
13275 0x5edaae2c, 0x95effd84, 0xeb0bda18, 0x2da74f8b, 0xcdea7f24, 0xdf3145b4,
13276 0x907e1c35, 0xdfb0d9f0, 0x2f1e2c38, 0x8f09914b, 0xf09e474d, 0x2f78dca1,
13277 0xa84c912c, 0x68adc257, 0x1bd7d6d7, 0xe56422d0, 0x533705e1, 0x899e7d7c,
13278 0x65f9868d, 0xdc177d08, 0x2a68637f, 0x93fe1bce, 0xff0ed5e0, 0x3b139262,
13279 0xb4ec59e6, 0x7b5c514f, 0x99c1e13b, 0xac3c43e0, 0xc0caae2f, 0xcf669a71,
13280 0x1e5c5272, 0x6fac39ec, 0x147bebba, 0x5ae0d7a7, 0x8d58d87f, 0xd8254ef6,
13281 0xb806bf75, 0xabaf93b3, 0x8f5f02f6, 0xfe940f92, 0x465bca10, 0xba2fe390,
13282 0x48b45d39, 0xcbb7d0fe, 0x62c78e29, 0x87b972e3, 0x7d78fdb9, 0x69da898a,
13283 0x514fafef, 0x8457af08, 0xb923a67a, 0x6d7a571c, 0x99075768, 0xabf403ef,
13284 0xeeaedf99, 0xf2e275a3, 0xa552bdcb, 0xddc59378, 0xac24ef7b, 0x7f2142bf,
13285 0x0fbd2986, 0xadfdb8e0, 0x267aef6e, 0x77cb00f8, 0xea1c5095, 0x1e604a68,
13286 0xb0a56fae, 0x5c8ffb57, 0x125b5a53, 0xf75abfb5, 0x01abc239, 0xf50ead0f,
13287 0x93946afe, 0x2724289f, 0x33d22599, 0xf869fa1d, 0xfbf5326b, 0x0ea05b07,
13288 0x86b569fb, 0x420e915b, 0x73b5321d, 0x6374b1cf, 0xe23eef3f, 0xd33b40e8,
13289 0x48636ee8, 0x50bee0c7, 0xf6e2c49c, 0xd3ca1533, 0x09140b43, 0x5d9c45f5,
13290 0x49e31d33, 0x29b8b7e4, 0xf82558de, 0xc1503463, 0x42b10b59, 0x5129e7cb,
13291 0x4ff9e73b, 0x52f82ae7, 0x160c7fb3, 0x319e1f1e, 0xf8e1812f, 0x49c89eec,
13292 0xdd9bc603, 0xe1ed0c3d, 0xc6894ec6, 0xdc7e2c69, 0xd2cbfe84, 0x41dfce4e,
13293 0xfe006fe1, 0x58aed072, 0x76136291, 0x77a70b66, 0x147273d6, 0xbe31f9e2,
13294 0x3b418c9e, 0xb2dfac47, 0xfd69da8a, 0xbc9c4499, 0x4093c451, 0xdafd5213,
13295 0x58cecd14, 0xc26d9e2d, 0x6ee3e0ce, 0x327c7a91, 0xd254b3e2, 0xe7b573c5,
13296 0x9277216e, 0x2166444e, 0xbe8046ff, 0x5db4ae30, 0x6ffb7d9a, 0x2bdb7e61,
13297 0x14d179c6, 0xc93900f3, 0x481ef865, 0x7e5ef011, 0x485983f8, 0x119aac37,
13298 0x9e1d36bf, 0xfd8a3726, 0xd217b404, 0x581dcd6d, 0x316b7e9f, 0xef8c67e9,
13299 0x5ec0bee3, 0x3b0cd781, 0x5679eb8f, 0x9f70f287, 0xff84e92d, 0xf8e2dff6,
13300 0x1f681213, 0xc6d61d23, 0x75cf4c91, 0xb0f2d718, 0x3f51a7d2, 0x32d46a7b,
13301 0x4fdb4784, 0xd9a8fdc2, 0xa9c72425, 0x7c95ec9c, 0xabf9e07b, 0x01e11714,
13302 0x846abcfc, 0xed87df17, 0xf4adfdd1, 0x38a5cde9, 0xe11fee2e, 0x5ba33fb3,
13303 0xeb3538a1, 0xfc8fbddd, 0xf113b37e, 0xb9f87355, 0xd6ff5157, 0xed275858,
13304 0x2dd9c5f7, 0xf1bc4e3f, 0x03a39449, 0xbeeecee7, 0xcefae11b, 0xd6806f21,
13305 0x5c8f6f47, 0xcfb7157d, 0x5367dbdf, 0x23dc8ed1, 0x8fd836e4, 0x5fa127c4,
13306 0xde327f72, 0x45397c8e, 0x960c9fef, 0x2476eeff, 0xf0042f87, 0xef918bed,
13307 0x0dffe141, 0x444f9fd4, 0x20faf5fd, 0x2bffa03c, 0xed5076a3, 0x2bed1b5e,
13308 0x7117fa0f, 0x8ff3c8f6, 0x0f4842d8, 0x14ad3be7, 0xfec45477, 0xe44739cc,
13309 0x8b52444e, 0x284de4eb, 0xbdb7836f, 0xf0032bf7, 0xf7c1d29f, 0xec49143b,
13310 0x3320bc87, 0x73e37fbe, 0x294feec6, 0x5f1e59ae, 0x3e47ca09, 0x6e2265ef,
13311 0x48b92cb4, 0x7c32fbe5, 0x62596a5f, 0x53da1177, 0xb43d094f, 0xabef812c,
13312 0xdd4cb80c, 0xac7baeb8, 0xb429f381, 0x67bfc2ff, 0xb1ab31bf, 0x611d2ffb,
13313 0x299dd76e, 0x609b7436, 0x1f681d9e, 0xe06dbae0, 0xfb8330fb, 0x1dcdc7d5,
13314 0x51938266, 0xc455a079, 0x95fdb5eb, 0x571e3ce3, 0xce51f627, 0x10fc59cc,
13315 0x48b5a96e, 0x9fe8d5cd, 0x8d3f585d, 0xde77d7e2, 0x759e9b3f, 0xf771f4eb,
13316 0xde99acc5, 0x5a94fb6b, 0x7996bbbc, 0x8e5edc4d, 0x600d11c6, 0x94eba8bf,
13317 0x7997d42a, 0xe51ab9cc, 0xd5821abf, 0x16cf0c9a, 0x2ed1a278, 0x73b42419,
13318 0x02775694, 0x16daefae, 0x50a9e903, 0xed87c18b, 0xb8e73c34, 0xd2a91c79,
13319 0xb01ae3cd, 0x471c6154, 0x4518b67b, 0xb7f45fdc, 0xf1ba198a, 0x73f89069,
13320 0x1ea953ad, 0xfd6b5f4e, 0x2d9b18b5, 0x648ba718, 0x7dae281b, 0x479be4c1,
13321 0x22e4e371, 0xb67c0216, 0x55d79a38, 0x9de27af3, 0x9f88d60b, 0xb854afea,
13322 0x64d4c921, 0x376e9f94, 0xe3c6538f, 0xbe9b516d, 0xd21fbf1c, 0xeb97d610,
13323 0x464c6058, 0x883fdf01, 0x7376ef7d, 0x7d6175f9, 0xd7b7c09e, 0x9b567284,
13324 0x8e2caaff, 0x7f364337, 0xcd5767e6, 0x77c83a43, 0x203f2899, 0xabe3c5df,
13325 0x3f821330, 0x44b74aff, 0x6f0711f4, 0x486d1a0b, 0xdf7cad5f, 0x1fc2abee,
13326 0xee55f70f, 0x7c1fa134, 0xab67dc1e, 0xdf689a73, 0x24e352f4, 0x72f5bab7,
13327 0xf7fcb068, 0x9fb967f7, 0x3c8b2ad4, 0xa1c9270e, 0xcb9f275a, 0x48fbc919,
13328 0x83b7be37, 0x68f3809d, 0x6ed0cb95, 0x9da37e99, 0xdc74d1e6, 0xc6e0714a,
13329 0xa839bd15, 0x7aaa9bc7, 0x203f308b, 0xad08bf1e, 0x682fc9a2, 0xff06eb57,
13330 0xd884ed03, 0xc547e476, 0x7efa07ef, 0x3f454ee4, 0xe781cce7, 0xb01d5f50,
13331 0x7f82be92, 0x38c66d3d, 0xb23c91cb, 0x023ac6a3, 0x305db02b, 0xa3f77ba1,
13332 0x70b76879, 0xcbb1a9bb, 0x617681dc, 0x3ecc4b6d, 0x06dffe1b, 0x5b1bbefd,
13333 0x77f14c97, 0x5f7faed6, 0xbbee33bf, 0x6d70fb21, 0x4c5bceb4, 0xefc8b181,
13334 0x9f6877a0, 0x81835cfc, 0x64ebb7f6, 0xb79462ef, 0x7b7aace7, 0xaf839cfc,
13335 0x9addcfd7, 0xc22de13d, 0x0f2c1e75, 0x116f6759, 0x819d73ae, 0x69fb6205,
13336 0xf58675c4, 0xf9d6265d, 0x8b9313dc, 0x3fdf9d70, 0xd708b930, 0xcdb18b79,
13337 0xa8f37c87, 0x1b90f033, 0xe99bedfa, 0xf70a7b27, 0x2e8f913d, 0xc40f1e95,
13338 0xff81e3d1, 0xefa47a3d, 0xc787d246, 0xebd0e106, 0xcd49b743, 0x6b507942,
13339 0x5ea17f31, 0xe361bfc4, 0xc5331678, 0xfa7f8e3b, 0x5047c6e1, 0x64c9740e,
13340 0x1dfd688f, 0x68050257, 0xd57f1d0f, 0x23490de3, 0xed18bff7, 0x07da0aad,
13341 0x455c610c, 0x7b3403f3, 0x9f1e5e32, 0xc779f312, 0x7b42abed, 0x8dc6ebfc,
13342 0x4b3bc5eb, 0xe76e43f8, 0x3cbc95ee, 0x7149dc6e, 0x0b63a6e4, 0x7e27189c,
13343 0xc6e3cc27, 0x52944f4d, 0xfc21b8dc, 0x2de6374c, 0x89c92eb1, 0xdec347fe,
13344 0xdb171337, 0xf82e7ea3, 0x5f236fb5, 0x3f7e8b31, 0x99f09de9, 0xc13b3ac4,
13345 0x71ea157d, 0x42623b9b, 0x7f026fba, 0x9ad4f30f, 0xec49c894, 0x28cdc9b7,
13346 0xb0fca31f, 0xf2d3ffde, 0x4df876a2, 0x74777724, 0xd7946149, 0x5e40a669,
13347 0x9635ea16, 0x8b6b3ce5, 0x6ec7d9f2, 0x77f71b9f, 0xbedbfba3, 0xe4c771ff,
13348 0x4f6ef51b, 0x35edfa22, 0xe5139f32, 0x908776d9, 0xb7c90a67, 0xc2ba778f,
13349 0xb788ff3c, 0xedcc38ff, 0xef2d0684, 0x0add6148, 0xb9e2d7ac, 0xbd70d7be,
13350 0xc777de51, 0xb2d8fbc9, 0x14bd2fb6, 0xf6e3d1f7, 0x0ddb63bf, 0xecc7e7ee,
13351 0x61faeb7f, 0xb96aa5cd, 0x5f5bff7e, 0x327ee21f, 0xb2f2c3f0, 0xeb6afd28,
13352 0x936fd1a0, 0xeb074388, 0xf483df4f, 0x392c3c1b, 0xe65bbed1, 0x0cbbf4e5,
13353 0xc4f32dfc, 0x3acefca1, 0x238979f5, 0xaa697ff1, 0xcb07ff9e, 0xeaf8a0ff,
13354 0x9c9aa915, 0xcdaf7ce4, 0x0fdb8b5f, 0xe24bb3ce, 0xaf37197c, 0x3e353f78,
13355 0x99f9aede, 0x6f0f2a97, 0xe387841c, 0x0ffcb063, 0xc6b78796, 0xfda465e1,
13356 0x0f2caf8c, 0x35f797ff, 0x35b63a1e, 0xb40efd11, 0x594fd1e3, 0xf3c8cfb7,
13357 0xb1fd0023, 0x64b3c5fb, 0x9fef8fbb, 0x7ebd5aca, 0x259d5e1f, 0x5f39e1f6,
13358 0x4c84f33f, 0xf628d6eb, 0x398f1b89, 0xdeb4d8bc, 0x69f684be, 0x6f4ff7e3,
13359 0xe1660763, 0xa3efc552, 0x2e7e432e, 0xd4fdf2f8, 0xbcc1d4d6, 0x5bcc3c85,
13360 0xcbd2aca8, 0x1fec67f9, 0xd66204a6, 0x1c04aabd, 0xdbe86182, 0x725884a2,
13361 0xa9adfbcc, 0x467eaedc, 0x4c78f7e4, 0xa5e61d6c, 0x7cd8726c, 0x0c78cfe8,
13362 0x47e8ff3c, 0x28edfe29, 0xc0aa2d17, 0x32ef91eb, 0x21e5e003, 0x95c92763,
13363 0x8bdda350, 0xdf8b5072, 0x2c7ffd68, 0x592ec1f6, 0xfbd1c7ff, 0x7a65ff81,
13364 0x53cfc78f, 0x755f78da, 0xe01b6edf, 0x8c17c746, 0xdc45f8e8, 0x4a1bca5f,
13365 0x33f523bf, 0x9cbf1d12, 0x95217fea, 0x226fa2e4, 0xa25c2be5, 0x4795b19c,
13366 0x889c60ce, 0x18ab341d, 0x0938c4d7, 0x190dc7e9, 0x5bd26f22, 0x80f29b39,
13367 0xbf9895bd, 0xf3fe06f5, 0xc8ed91f2, 0xe1f5c1be, 0x88df6476, 0xecf5f3eb,
13368 0xfe9dbbc8, 0x7d6748b3, 0x6f947cd3, 0xf001d6be, 0x0bf87fa3, 0xd3b4779e,
13369 0xa773e9ca, 0x2d92e9c4, 0x78a4b94f, 0x7471a7cb, 0x91ffe9f5, 0x8da4b51c,
13370 0xbdfe5764, 0x125fe8e5, 0x723a7e31, 0xa79e213f, 0x7843d55b, 0xd8931c8b,
13371 0x76b8989e, 0xe0cff310, 0xaf010cfb, 0xe123fef6, 0xf34c2c37, 0xfbc1a665,
13372 0x58b35ff7, 0x3e981258, 0x362e5ce5, 0xafb4edf9, 0xf3c9d4d0, 0x30569a5f,
13373 0x184de392, 0x78c12d37, 0x98b66ce2, 0x428189e2, 0xfb5b93cc, 0x27243dba,
13374 0x0e7dbc61, 0xffaf3b43, 0xdebe5e35, 0xfec62815, 0x697a2b83, 0xce7da31f,
13375 0x5587947b, 0xf787f9f9, 0xbc139754, 0x9b704f14, 0x6e25e7f5, 0x0efbe34c,
13376 0xa69fd3da, 0xe28fbbad, 0xf3d7eff9, 0xdba0e2bc, 0x84b8c4e7, 0xa9b70f16,
13377 0xd0afb43d, 0x6f1b9074, 0x0f9f3295, 0xd11669fb, 0x69c1d353, 0x653718a5,
13378 0xb452d69d, 0x6cff2b77, 0xfdefbf27, 0x4f2932bb, 0xe04a68e2, 0x51d7846a,
13379 0xed16be1e, 0x07185cd3, 0x0ff7deed, 0x708a5b5c, 0x0b6ff26b, 0xfda1cdc6,
13380 0x1e3e8716, 0xdf3c2cce, 0x51d1e1bb, 0x1abcdc5a, 0xf045b3f1, 0x55b7b321,
13381 0xef861ece, 0x974f7e35, 0xfa7fd40d, 0x3fb42df7, 0x2d83c9ae, 0x14b01646,
13382 0x24c8e544, 0x74183f91, 0xaec5fc8b, 0x453f3cd9, 0xa9e2ed94, 0xf71df3e1,
13383 0xaf3849cc, 0x37ca6949, 0x4a72c7db, 0xac7dd8f6, 0xea0148bf, 0xd0c4f317,
13384 0xa515874f, 0x22ed8b78, 0x9df3a3b7, 0xc723a226, 0xa7f7c63a, 0x9ed08e80,
13385 0x33d222bf, 0x59e6093d, 0x057dded8, 0x45f8f7e2, 0x3293ad03, 0x97da45fb,
13386 0x78f89249, 0x5b7a1b05, 0xc61c60c7, 0xb895caf9, 0xb39b6a94, 0x36f8b70a,
13387 0xa477fcb9, 0x1737df11, 0xff5578e3, 0x9379e461, 0x5f146cc7, 0x4659cf68,
13388 0xaffd9379, 0x3ee7759b, 0xb6219fe2, 0xf324f29a, 0xf691ff0f, 0x25071c07,
13389 0xe7b4de1d, 0xbe76697d, 0x99ea156f, 0x5735b945, 0x2abe49b8, 0x421cfec7,
13390 0x5569437b, 0x16b0f250, 0x4560cfa3, 0x518ab5f9, 0xbb747f3c, 0x95eb80d3,
13391 0x0662f22b, 0x6275ff8e, 0x6d15fc80, 0xf3cc203f, 0xf7bd8c9a, 0xaca61fa0,
13392 0x842abdea, 0x65d071eb, 0xa9b8c268, 0xf144d231, 0x8a366396, 0x2e1ee6af,
13393 0x282dfd58, 0xd273aee7, 0xd1c0d7fe, 0x6f94b9a5, 0x3d1cf30e, 0x4cef3ccc,
13394 0xcd4879e3, 0x63945e82, 0x33ea0336, 0xe2f33365, 0x3e2d79e8, 0x7ef802e7,
13395 0x3a2153b4, 0x0816985f, 0x9e0e7ae3, 0xc09e596f, 0x3c28b7cf, 0xfe58e23e,
13396 0xdcf12ffa, 0xb7116ec8, 0xfc7c713d, 0xb5f38a1c, 0xfde2122a, 0x51e78b82,
13397 0x3fa6963e, 0xf7c51087, 0xcd47ca09, 0xae47f63f, 0xf60da0bf, 0x7d3918af,
13398 0x0eeead28, 0x3bf6278c, 0x7b7f9402, 0x4cb74b65, 0xbece63fb, 0x18d5aa07,
13399 0xd71b66bf, 0xb9fb4d27, 0xc7ef1e1f, 0xf91e997c, 0xe13ca0ed, 0xfcb0647a,
13400 0x7a4fb20f, 0x57c7f4e2, 0xde984ff6, 0x53b78baf, 0x21b8fde2, 0x7f5c7776,
13401 0x5a2bd923, 0x745549be, 0x3b376e1c, 0xa4287b34, 0xb2a9c7cb, 0x166bf38b,
13402 0x260fff7d, 0x22ff793b, 0x8d6d273f, 0x7d414aba, 0xe28c2ff5, 0x90fe5a73,
13403 0xaa142f96, 0x213d79e2, 0xb7ce8583, 0xe51b5879, 0xdd628d09, 0xb4714492,
13404 0xa7df865e, 0x7c10be63, 0xf2d2ffff, 0xcc5dffa9, 0x39264ebb, 0xbf084aa9,
13405 0x524cf315, 0xf6f0ee10, 0x77de38c5, 0x159e34ec, 0xc8524cf3, 0xcdfe209f,
13406 0xd4fcf3f4, 0x7f7cf5e9, 0x30f41321, 0x390b3396, 0x99e75a5d, 0xcb555f28,
13407 0x4cf2d11f, 0x0954bc34, 0x598e677c, 0x5072879c, 0x92d947cb, 0xfb44ade0,
13408 0x7b0255a7, 0x90d3e71a, 0x784bf220, 0xf90dedbf, 0xaff7a461, 0x8f127f9b,
13409 0x650f2d67, 0x3d206272, 0x5e7a22bd, 0xd11fcb4e, 0x3d6626e8, 0xc71dae09,
13410 0x555f3db8, 0x0c79a26f, 0x71475c34, 0x030681c9, 0xd55fbd43, 0x1874e665,
13411 0x798ede37, 0xfd8dd626, 0xe52b612a, 0xf87a0bd7, 0xd6167b32, 0xbee318b7,
13412 0x2fee5627, 0x7fde03e8, 0x3d276576, 0xa752ac07, 0x33ce893c, 0x950947ce,
13413 0x5eb8e9e3, 0x6af31cb9, 0x90123922, 0x0fed84d0, 0x353950d7, 0xa79606f2,
13414 0x51ae5e7a, 0x8c0c4f40, 0xa096ec8e, 0x2ddb7fbd, 0x99b48cbc, 0x7d3dfa09,
13415 0xe4a84d76, 0x363be81b, 0x2aa36f24, 0x37e2953d, 0xbc50f4f7, 0x72bbe848,
13416 0x0cd91f2e, 0xabc79873, 0x9d9b8a54, 0x3b23c8ca, 0x7f9c5ec0, 0xb3eb07b0,
13417 0x836714cc, 0x53ffa27a, 0x7af1a7a3, 0xcb3faf95, 0x0dfcf072, 0xf9421bd6,
13418 0x1a6f2a76, 0x911babc5, 0xb29ec03f, 0x7073023b, 0x3d49cf5d, 0x9c3f2277,
13419 0x25cff99a, 0x0ee7e748, 0xe510b4fd, 0xb02635cf, 0x379187d3, 0xde5c1969,
13420 0xebed180c, 0x65e7e824, 0xd8fbe07b, 0xf9b6abcf, 0x7cd530b3, 0x1334ca5e,
13421 0xa1601d1e, 0xff28c85f, 0xb9fac552, 0xd1fb72e6, 0x612fc335, 0x2b1ae81e,
13422 0xa0352387, 0x099ec8f8, 0x03be95cc, 0x09235ff3, 0x49a986fb, 0x6aa887e4,
13423 0xcb21fa12, 0x5946b9c4, 0xf82cb7f0, 0x7b2b0ffb, 0xd830150a, 0x2cdcef2e,
13424 0xdedfe70f, 0x686fe718, 0x5ce94dcf, 0xd591cf4e, 0x6e1f4809, 0xd7df91e3,
13425 0x26c93ac0, 0xbdf1186f, 0xfb41db26, 0x2a3b4fb7, 0xafd0bd3d, 0xe52ffb94,
13426 0x26bd5798, 0x71ca5ffb, 0xf64e4d9f, 0xe531fc7a, 0xf52ae94d, 0x21db0337,
13427 0xe5cd6cfe, 0xbbfd7f18, 0xfd0497f5, 0xfefd7c95, 0x7331fb06, 0x225996b8,
13428 0xddf00a39, 0x03c0d6cd, 0x16177eb8, 0xb3fb49bc, 0x7a9e6677, 0x4e2bf303,
13429 0x88cf9919, 0x9c432472, 0x8ebd033f, 0x75cc9ee3, 0xce53f3f1, 0xb113d36d,
13430 0xf2e9c05c, 0x7da6165a, 0xfcb99af5, 0xacf5e3bc, 0xda17a5a7, 0xaa31e35d,
13431 0x71fc31bd, 0x5f2faaad, 0xd72fac5f, 0x7f8e3c88, 0xdfdfeaf2, 0xd20a22c0,
13432 0x7ca7b7e9, 0xfdf62636, 0x2fdf5653, 0x929e8f90, 0xe867de78, 0xfb24e672,
13433 0xd0852dd9, 0x64ff199e, 0xc9ff38a6, 0x55ff13f3, 0x4e4f5ff8, 0xb69f5461,
13434 0x82c7b2df, 0x2d9e22f5, 0x1ef1fa8b, 0x264dc966, 0x30fa49b9, 0x473c8922,
13435 0xb0f1ed37, 0x793bb743, 0x9ada175c, 0x0b439fa0, 0x9a4bc254, 0x42aec0dd,
13436 0x10b72bfe, 0xbe7469ff, 0x0af40ac6, 0x651ca978, 0x5dfa4049, 0xc36ef463,
13437 0xb304e4be, 0x5a6ffa8a, 0x96fa85a2, 0xfe90a67f, 0x33356558, 0xdc4f9427,
13438 0x68654097, 0x44e07247, 0x718c2985, 0xee4235ee, 0x481bf7cb, 0xcc2a567f,
13439 0xd01b798f, 0x9fdf1bae, 0x3b50b0c8, 0x7c5cd298, 0xf1a8ca7f, 0xf28534d5,
13440 0x1aec0538, 0xf488c13f, 0x57e0ab7e, 0xb3cdf059, 0xfb8d0700, 0x7141dc82,
13441 0x05bd5530, 0x632de7cb, 0x70511ce8, 0x629b9cf0, 0x9d8ac1c0, 0xf8bbdf82,
13442 0x3f8d3339, 0xd2017935, 0x28b710ad, 0x6d0e3125, 0x3ea1a7af, 0x6b5f6466,
13443 0x07edaafc, 0x76b45b66, 0xcffb0f8a, 0x3cd9df10, 0xdcb84279, 0x47fca668,
13444 0x7aea5ef1, 0x1fa413ee, 0xaf77af8d, 0x3d7c40bd, 0x3fc5df14, 0x0e75f2a6,
13445 0x98f7c727, 0x391fe42c, 0xea164c61, 0xaf2e359f, 0x17298fea, 0x4bcff903,
13446 0x3b407c46, 0x7d58df28, 0x918950aa, 0xe70f36f3, 0x4be76857, 0xb09f7c01,
13447 0x67c859aa, 0xc8db8cc3, 0x7dfdb5c7, 0xb8c0f5c7, 0x0384eed0, 0x7b7685c6,
13448 0x436ee6ad, 0x4fe370e2, 0x2fbc7151, 0x6eb1971b, 0x04eb9e22, 0x420e815e,
13449 0xe13a3718, 0x5e3d1030, 0x4f7bf227, 0x58f1f2a4, 0xa65f3eb1, 0x40d0e810,
13450 0xfcfa58f9, 0x9da46b98, 0xb6efa82d, 0x20f7135a, 0xe8273ddd, 0x67eda4e2,
13451 0x3cef6885, 0x59e8bf37, 0x92b3eb94, 0x9120b556, 0x893ac75c, 0x757935ef,
13452 0x4acde321, 0x1adc832c, 0xbff581e7, 0x7cd4ff33, 0xd759fcec, 0x5fd442d6,
13453 0x7bc60f20, 0xafc28752, 0x37069fd1, 0xfbd221d2, 0xc1c61d20, 0xbb11d1af,
13454 0x0b1293a1, 0x88bd8177, 0x047ecd4f, 0x91e7884f, 0xf9d1d9ab, 0xb2cf1101,
13455 0x3479f334, 0x6bee0884, 0x9e500f5c, 0x0199e5d9, 0x69d6079f, 0x720fa4de,
13456 0x59ec6c14, 0x76e30630, 0xffb4ef00, 0xede3784b, 0xa7cb2fe5, 0xb58f891e,
13457 0xfb39a5f1, 0x383a9f29, 0xd5f94ed7, 0x693e45d3, 0x7140deb0, 0xc8abf074,
13458 0x96626f1e, 0xa9ddca30, 0xf2d5bec2, 0x3c4a8ffc, 0xc27a193e, 0xb18beeac,
13459 0x59e68793, 0x1dc794ab, 0xb1f3c15a, 0x46e0ed07, 0x9060ec95, 0x0573badb,
13460 0x765ca5ed, 0xd2aedfb7, 0x24a79979, 0x80b43ede, 0x7db3dc51, 0xe45fa8b6,
13461 0x58f76b0c, 0x7cd16948, 0x460ef6f7, 0xc8eedff4, 0x594cfaa7, 0x16fdcb9c,
13462 0x79ed37d7, 0xbf6c4fdc, 0xb7ea88b9, 0x52c78424, 0x87d88f5e, 0xf5fb81df,
13463 0x7f1fb05f, 0xe3f3479f, 0xb0751c78, 0xa38a77fc, 0xb40cea3e, 0x2a2dfd21,
13464 0x8118e5f1, 0x3c4cea5e, 0xbaf40a9e, 0x7a6187b3, 0xfa21735f, 0xe6b2d73b,
13465 0x44050c57, 0x2e905baf, 0x7a078de7, 0xebd1d02d, 0x97054f56, 0x469708db,
13466 0x5a7483af, 0x17379f1c, 0x76fb6308, 0x9b9fe757, 0x32e83fd0, 0x30de797b,
13467 0x978c83cf, 0x2cf0310f, 0x6e3c3854, 0xf6782659, 0xc1c4ff13, 0x137c2973,
13468 0x8ce9a74b, 0xfc48c7f3, 0x90b0ae93, 0x3fca2ca3, 0x4f03594f, 0x7c83b8e2,
13469 0x0bf70f74, 0xdb2dc087, 0xba6e9e89, 0x0517ef99, 0xe3ef5c6d, 0x8c0651be,
13470 0x7f8c5b3f, 0x867fab53, 0x96cddb0b, 0xe1ba1e38, 0x1cff007f, 0xabbb3f51,
13471 0xe6c6f291, 0x8e9e30cc, 0x793473b5, 0xcd53eda9, 0x746fed13, 0x1e6236ce,
13472 0xfd1adcf7, 0x5bbcd0fe, 0x4dd4fef8, 0xccfdf573, 0xa03e1b63, 0x6cd646fc,
13473 0xbbcdfc44, 0x8aff5f45, 0x695f7067, 0x3d2bee0c, 0x0329e22b, 0x47c827c0,
13474 0xb25d4dbf, 0xf3a076f3, 0x292f3f31, 0xcccf38c3, 0x9bbd86b4, 0x8ee8fca1,
13475 0x6dfe5471, 0x747ff7da, 0x1777eb0a, 0x41867951, 0x90c7e7e2, 0x8acf810f,
13476 0x2ebe6f2b, 0x89f5112f, 0x4676f7e8, 0x81093def, 0xced0d9f6, 0xf29f3133,
13477 0xf888673e, 0x5e22c0c0, 0x0724fd7f, 0x55bded4f, 0x8ceaf8a5, 0xe47cc884,
13478 0xff4b1783, 0x90f30cb3, 0x728be467, 0xb0e353d9, 0xc1f4acfc, 0xfd67d47c,
13479 0xd705768d, 0xc79329a1, 0x4b17c7a5, 0xe22763dd, 0x7fd12c79, 0x4d579f23,
13480 0x91322fd9, 0xf154664f, 0xa77bc67e, 0x3b6016b5, 0xf72a79c3, 0x11125a67,
13481 0x19bf1aff, 0xd9a41f84, 0x27217e8d, 0xd9bdf49e, 0xfafd0292, 0xa717922d,
13482 0x26f29fe8, 0x9d9817c5, 0xfbf3a79f, 0x6b8c14f2, 0x3cf1f74f, 0xd8ab6dd5,
13483 0xb6f3b42a, 0xd653e95d, 0x0b74fd40, 0x7a04f5a3, 0xbd206537, 0x2720fe4f,
13484 0xaecc8911, 0x9e8d77a7, 0x3e746b66, 0xc0cf4f43, 0xfefc76a7, 0x8eb5e4cb,
13485 0x7a51ad9e, 0x09ce291e, 0xa0646570, 0x5e96f85c, 0x138e0d8f, 0xe3f18fc7,
13486 0xf027248e, 0x46de562f, 0xbe24ebe1, 0xbfecc2cb, 0x36cbe402, 0xe1c72f8d,
13487 0x1e864cfc, 0x2b943f3a, 0x01d1c779, 0x0b5e29dc, 0xfe38b9e9, 0xc6cbe0d4,
13488 0x50d972d8, 0xd14ff0b8, 0xe7fe50ec, 0x9643f8c6, 0x7cef87a8, 0x170a392c,
13489 0xf1153f8c, 0xf0e1eec0, 0xb99a92ec, 0x867e115c, 0xd268b716, 0x3f587be6,
13490 0x7e04cadf, 0x7183df8e, 0x285bda26, 0xf708371d, 0x3683ac25, 0xdfd0a09f,
13491 0x877e2d73, 0x1df6e609, 0xcfd11d57, 0xba834177, 0x811d5d70, 0x279c236f,
13492 0xe863a10c, 0x3e622d8f, 0xfa065fda, 0x445467f0, 0x37834bd7, 0x234d4f1e,
13493 0xf9f8d1c8, 0xba27e3c4, 0xf8193d6e, 0x0de7ced4, 0xe712f7ce, 0xb89f6f19,
13494 0x5f78fa4d, 0x25cb88b2, 0xc570e347, 0x12c35f58, 0xf38714bc, 0xd5bfe44a,
13495 0x7281bd80, 0x519aa6b9, 0x6ed9243c, 0x669c38a0, 0x27c48c77, 0x48c55f57,
13496 0x632cd54e, 0x9f205ce2, 0xa63d3c5f, 0x931fdeb3, 0xb7516bff, 0xaf7e442f,
13497 0xf0f2ebb7, 0x6e3cec6b, 0x1b935ebf, 0xf502b7ac, 0x887960fc, 0x40adef9e,
13498 0xff7f13b9, 0x1e45cd57, 0x28be4e2f, 0xfbc6b3d1, 0xf9ea0566, 0x0adeeae4,
13499 0x240f5f94, 0x75c5eef9, 0xe3c0c37d, 0xdcf8f1ea, 0xe2d0619a, 0xa74497c5,
13500 0x78347cf1, 0xd811dace, 0xf168e381, 0x0f5273a4, 0x38a64f8f, 0x3c81ff45,
13501 0x4ba067a4, 0x20669a23, 0x1cff3f27, 0x37fc519d, 0xf726ede0, 0x7b9c9aed,
13502 0x18dce498, 0x5cfdd7a1, 0xbe9cf89e, 0x4e1c19bd, 0x021dcbc2, 0x9e85332f,
13503 0x2653bf3d, 0xaf86643f, 0xa16e2b78, 0xb2379f04, 0x8fb1f130, 0x8f76a3f4,
13504 0xa83079d7, 0x63fdb1ba, 0x4bb7d20e, 0xfda3a85e, 0x0cdb31a5, 0x97d18d4c,
13505 0xba09c363, 0xefc641fb, 0x2795d64f, 0xdaea6674, 0xaf9c3a4f, 0x1eed2fab,
13506 0xecbfaba7, 0xb95d32f9, 0xaeaa67a2, 0xab57e4fd, 0x7bcbe574, 0x7fb5d3af,
13507 0xe03df504, 0xccef5bf5, 0xefffbdd1, 0xc79eb31d, 0x232bdcfd, 0x7f7dd3df,
13508 0x5819c446, 0x0c53d7c8, 0xd1a85ff3, 0xdd5ac5ef, 0x74d660f7, 0x0728954b,
13509 0x0dc2dff8, 0x1a7d4f3c, 0xbfb62c60, 0x7b7a6d45, 0x508b2662, 0x58535f7e,
13510 0xcc3376f2, 0x37d7d353, 0xbc20ee1c, 0x013dd97e, 0x0c0bdc63, 0x197d0f48,
13511 0x858c6760, 0x14b0a47f, 0x891bb3cc, 0xfd6cbfff, 0xd7e1588b, 0x47b37f5a,
13512 0x5556febf, 0x62b6febf, 0xbc3bfafd, 0x9a4ff5fa, 0x977f5fa2, 0x29febf4f,
13513 0x4ff5fad5, 0x3fd7ebf5, 0xfd7e9e7d, 0xf5fa0233, 0x5faf551f, 0xfd66ecf7,
13514 0xd72ee77a, 0xe85e6baf, 0x36fdfd36, 0xd1a07471, 0x0b4f2693, 0x7711ddd6,
13515 0x19818e1f, 0xa342e862, 0x7afe85b3, 0xdd1a5fca, 0x78dd13f6, 0x8631f4f1,
13516 0x6fcbbc89, 0x99851f48, 0x7f981740, 0x3f92cc99, 0x1bef3d27, 0xd43a999d,
13517 0x56e4d0be, 0xf58f3eac, 0x6792478f, 0xf094f443, 0x53d44797, 0xa35b2fe8,
13518 0x7448f2fe, 0xfd031afa, 0xa06f834a, 0x4ecdd838, 0x0489c70e, 0x887fb76e,
13519 0x3b439755, 0xe0053368, 0x03e70d7d, 0x3096bfe3, 0xdf1de29e, 0x1c469d63,
13520 0x43d616f7, 0x422cf9cf, 0xea7300cf, 0x642c7dce, 0x7f88937e, 0x8159975c,
13521 0x4ade9171, 0x1617a394, 0xf6837a9c, 0xb94c5eb3, 0x4e327ba4, 0x68c97ee3,
13522 0xb90acec6, 0x26fb87d1, 0x8ab7ee50, 0xa98fa078, 0x9e7c18ee, 0xdacbf115,
13523 0x57e912e9, 0x7e502726, 0x2577ed57, 0xffb54fd2, 0x99759fc3, 0xff1eae3c,
13524 0xc35cb35c, 0x0bb09b6b, 0x5f707db8, 0xbbf54aa6, 0xb276aa60, 0x944ebd43,
13525 0xdf1fd0ff, 0x44d878c7, 0xc2c7b9fe, 0xa29504e1, 0xe3a64c5c, 0xb8eeb474,
13526 0xcbee78fe, 0x4df0e163, 0x22e59850, 0x02cf1fbc, 0x95de1764, 0xdffd4f99,
13527 0xe38880ab, 0xfec38ffd, 0x15684a3d, 0xc07fd1c5, 0x5bf471f4, 0xa38a259a,
13528 0x85e000ff, 0xf5e9c7a7, 0xcad61ea0, 0x33bc05ab, 0x4fbc1db0, 0x184b34f7,
13529 0xfdbafaff, 0x78c3f60d, 0x7887f83f, 0x59a1e2d7, 0x58668740, 0x603fbdd7,
13530 0x8f8bcf14, 0x41928e8b, 0x93fe63a2, 0xf7ab9f91, 0x9fb8db28, 0xd4ebd27a,
13531 0xd1987dc5, 0xbf20e785, 0xbcc2decc, 0xe731b3e5, 0x87bd600c, 0xe9747fbd,
13532 0xbf2fbe28, 0x31676566, 0x4fd88dd1, 0x7ee57bbc, 0x978acb2a, 0x3ef10af2,
13533 0xf7cc572a, 0xc7d43726, 0x8762bbf0, 0x90e463ef, 0xcba7eed1, 0xd959ee57,
13534 0x4678fb43, 0xdad66f71, 0x819c3bac, 0x2fc77898, 0x631d8533, 0x1a673109,
13535 0xfc37a613, 0xe19d33bd, 0xe54ecafa, 0xcb5fac6c, 0x886c979e, 0xcf4146b7,
13536 0xd7ba092f, 0x607b36e0, 0x5eb818bc, 0xe8def412, 0x3ce131ec, 0xe8b5825e,
13537 0xd2b4b8c1, 0xd3fba6e3, 0x1c93716e, 0x83ac41ba, 0x8dd4a0f9, 0x0acc4ae7,
13538 0x5ec5f99e, 0x832fda7a, 0x64bcf726, 0x76efb864, 0x2435c54f, 0xcdc94d4f,
13539 0x8fa06ede, 0xc8b4be1f, 0xaf061819, 0x51ecd3da, 0xc5cac42e, 0x5f8532e7,
13540 0xc64d993e, 0x1e061975, 0x743f93d2, 0x587e6ff2, 0x7e58f3c1, 0xf94603f8,
13541 0xfc396ced, 0x94f14655, 0xf724bcca, 0x2f422c5c, 0x0604ac37, 0xe8f6031c,
13542 0x980b0b4a, 0x66b21f41, 0x98d2d3b2, 0x4369e88f, 0x3ade8be9, 0xf65ecef8,
13543 0xcff462bb, 0xaff8abef, 0x2a3b2c66, 0xf2c7af5f, 0x758fb1fa, 0x1d9a0e62,
13544 0xde537161, 0xe0af1850, 0xaff7184c, 0x3b6357fb, 0x1f798f7c, 0xe01ef0d5,
13545 0x574277b9, 0x26dbdb04, 0xeb077d1e, 0x96ddec13, 0xe12ef802, 0x0055e616,
13546 0xf2dea95f, 0x74f00569, 0xb02f4395, 0xbdf136d4, 0x37ef0a6d, 0xdd26bf7e,
13547 0x43df87be, 0xfb130573, 0x045efca2, 0xd5233f6d, 0x0aada7be, 0xbea156e5,
13548 0x8f8141fe, 0xcfe3fb14, 0x303d63e7, 0xad1668dc, 0xbbd4407f, 0x54f78fec,
13549 0xdd165cf1, 0xff459bf7, 0x97037649, 0xfb132a57, 0x937ebcb6, 0xf56ab7a8,
13550 0x65f6261e, 0xa8ab7d79, 0xde79db37, 0xeeb7b012, 0xfc62b5fb, 0x2c0c5bb4,
13551 0xeecf4310, 0x102c09b9, 0x35c91f43, 0xd1b2bac9, 0x3b25cfce, 0xbeea6467,
13552 0x5bbdfad3, 0x45789b8c, 0x4b3beebe, 0xfb7d38e1, 0xcfa4c9b9, 0x367810ee,
13553 0xeae99565, 0xacfef3b5, 0xf273b45d, 0xaa7b8a76, 0xaaf3dfae, 0xe072849a,
13554 0xdd1ae5ec, 0xb7482d7a, 0xd3f23877, 0xbc21bf71, 0xa3353a12, 0xa788b13c,
13555 0x683d3c53, 0xa553c05c, 0x7b889e72, 0x853959ae, 0x6e807bca, 0x95a1feb1,
13556 0x82ef2a5e, 0x9fcf0ab2, 0xbc2a3f43, 0x60fd0edf, 0x83f42b79, 0x1fa107cf,
13557 0xe3003e7c, 0xf866fd61, 0xa09bcb0e, 0xb7df2c3f, 0x7be547d2, 0xb9535657,
13558 0xca9fa575, 0xa3ce576b, 0x032bdde7, 0xb2b35cf4, 0x8e67ea9e, 0x6bedfae2,
13559 0xb39405e7, 0x9980bcf8, 0xe7a22aa3, 0x80bcb43a, 0xfef0d30e, 0xb8a3cddc,
13560 0xfe65cc1c, 0xfe9c2da7, 0xecc89ee9, 0xa34f9d0d, 0xe7e29bdf, 0xa1b191eb,
13561 0xd55dea99, 0x3bed1c7c, 0xacb10ee6, 0x158c7e4a, 0xea4bf5db, 0x1997ca6a,
13562 0xcceae3cb, 0x256a6213, 0xfe974ebf, 0x13e90894, 0x5f2f58a5, 0xdfc3ccf3,
13563 0xe3101d53, 0x3ecd85c8, 0x8a658e9c, 0xc4f31bbf, 0x9d00deed, 0x08bdcfef,
13564 0x9b1f839d, 0xa62af174, 0xaee2e982, 0xc9d1dbd1, 0x7674ca33, 0x89b17caa,
13565 0xbeb259da, 0x72676ba7, 0xd5daead7, 0xc7bbcd2e, 0xc518f883, 0xb0de61e7,
13566 0xb8c0658a, 0xd337da8b, 0xbac5ebb8, 0xbdf97cc1, 0x3e2407d6, 0x3dbf615f,
13567 0xb5f314ea, 0x3ab9206c, 0x458bc5c6, 0xca032149, 0x9d7ff7c3, 0xc8fafc44,
13568 0x478a0643, 0x0361658e, 0x5078d7ae, 0x813f58d3, 0x127952f5, 0x9728574a,
13569 0xf2c65532, 0x7e422c65, 0xab6fd82e, 0xe49b9d71, 0x285643c0, 0x3c0ecb9f,
13570 0xba91f3ca, 0x8914af49, 0xecd228f5, 0x7c4a6dd8, 0x28dd6f7c, 0xe7f58ff2,
13571 0x9bf7e295, 0xd32a3957, 0x1fe8fed1, 0xe6cc7f21, 0x42dcf339, 0xe32dbfc0,
13572 0xef6a7a4d, 0xc30d55ef, 0x787de39e, 0xf2cdf494, 0xfbfac33e, 0x1fde81b8,
13573 0x2b9c79c6, 0x5e6603f9, 0x08c2a6b1, 0x8c6b09f9, 0x93509c9a, 0xecb63d98,
13574 0xf331624d, 0xabe56478, 0xec090a05, 0x764de100, 0xe7cc746a, 0xea527f2b,
13575 0x22a63cc4, 0x7fb93791, 0x8ce14665, 0x7befd1d1, 0xb3141d04, 0xc5ff924e,
13576 0xfc97836e, 0xe7539f48, 0xdb0b5a77, 0x445e787c, 0x98bcc71e, 0xb5963363,
13577 0xf96b39d1, 0x23c9326f, 0x4cb5c4f9, 0xc123bb05, 0x7b216619, 0xfc265fb4,
13578 0xf9091fd7, 0x067d91f9, 0x68e72fc1, 0xc8f9e1f7, 0xe9c8f9de, 0xd49e6275,
13579 0xfa46ed47, 0xafad3e48, 0x5f7a762f, 0x2e9d000d, 0x22f3683e, 0x6dc50978,
13580 0xbca03f74, 0x1259625b, 0x20f3c1c1, 0x6cbdb993, 0x42c956dc, 0x1b579eb0,
13581 0xbf098702, 0x8321eabd, 0x5da1fca6, 0xee898a63, 0x78831f67, 0x6e5e23b1,
13582 0x43819c2e, 0x1e131617, 0xbf798917, 0x26b1e625, 0x80bfc35b, 0x787cf987,
13583 0x76e2e09f, 0xcfd6efcd, 0xaa92def3, 0x4b7d636f, 0xa0f94c8f, 0x973cf8f1,
13584 0x44c4a7f8, 0xf1daf058, 0x70046e3c, 0xa0fc85be, 0x8829dc20, 0xb69fbe5f,
13585 0xe30a69c4, 0xa97ee039, 0x30f29ab3, 0x7f281827, 0xdf2e9e35, 0xf368f617,
13586 0x6d3d2728, 0xcf44b39e, 0x73df72d1, 0x7fc8530b, 0xaed67ae0, 0x9f16bcf0,
13587 0xf78d8d4f, 0x28e2d7ad, 0x413f5f22, 0xdf783bc0, 0x479e38d8, 0xdb3d6768,
13588 0x24664f30, 0x9590c6bf, 0xc0d7e717, 0x54fd20d2, 0x651f2858, 0xa4e796bd,
13589 0x8f29529e, 0xe7989e1b, 0xba741164, 0xb9efc1d6, 0x3a37e6d0, 0xd1d1cb8b,
13590 0x06ff9c59, 0x86de5a2c, 0x2634a6af, 0xabb6bfff, 0x6d75fc8e, 0xc4406a3f,
13591 0xf4120649, 0x820d47fb, 0x6d9e0614, 0x7dc04aab, 0x1fbe3690, 0x3d75d0d5,
13592 0xd8f2efbf, 0x285f7403, 0x3d22a9f4, 0x75f689d4, 0xfafef4eb, 0xe201fda2,
13593 0x4078f8d7, 0x980fffbc, 0x1e5da133, 0x67e7ffef, 0xcbdf7f09, 0xe9bf714a,
13594 0x938286cc, 0x29b70009, 0xd1b9d18f, 0x74e3f251, 0xa5583bef, 0x26cf786d,
13595 0xcaf7e12b, 0x0fffafc4, 0x97844db2, 0xdf5f12fd, 0xf13b68d0, 0x2e0afec1,
13596 0x7d3ff607, 0x28d186fe, 0x7d2572cf, 0x91ae713e, 0x818b77df, 0xc9df787e,
13597 0xf970f558, 0x0cb23362, 0x5fcf4cdf, 0x8d7b97a1, 0xda4f7b87, 0xd37f9254,
13598 0x4f3d70b3, 0x84b125fe, 0xf74228f8, 0x83b9a3e6, 0x78dc21e3, 0xe180e36e,
13599 0xf4b1f983, 0x452cddf0, 0x66f86dc0, 0x1e8678f2, 0xaf2573ae, 0xe1c75da4,
13600 0xf50b29ba, 0xb4e9f763, 0x0d7c7cd8, 0xc35503ae, 0xf86e2b9f, 0x029a78a6,
13601 0x8b0e54f0, 0xc22ffaa7, 0xf0d301d3, 0xc04cfcf0, 0xf2cf6ff3, 0xd6862efb,
13602 0x6dfb437f, 0x1efe1c67, 0xc509b9eb, 0x33fbc036, 0x2fa79fc2, 0x04c2f68d,
13603 0x05cb3afe, 0xf90b967d, 0x895f25e3, 0x4c9f5f05, 0x0a9d64f9, 0x72c1a94b,
13604 0x2aef42e5, 0x4a7f7a35, 0xfca010d0, 0x79baf67c, 0x4477f958, 0x990385c8,
13605 0x3878b0d2, 0xf4f9e628, 0xa8b9b58b, 0xd57dee67, 0xb42e50cc, 0x5efdfb08,
13606 0xef05a767, 0x88f0d59f, 0x067832e5, 0x5ec5914d, 0x647f972c, 0x8cc3ed51,
13607 0x6de3e067, 0x6d1be38a, 0xabf9ed3c, 0x0fae62ac, 0xcc6567a5, 0xc574dfdb,
13608 0xd42f742b, 0x648572a6, 0x7fc6d7ef, 0xce5e9ebb, 0x7692bf75, 0x5f97a703,
13609 0x4934bd21, 0x1b7e256f, 0xf22941ca, 0xcbee0972, 0xff34029b, 0x43b1e020,
13610 0xeda78a1a, 0xf9b45e82, 0xe0d7f369, 0x90b95c76, 0x9af1c1d6, 0x41c69499,
13611 0x17d35ed1, 0xe1ff4249, 0x5c5f48bc, 0x0f73f0a1, 0xfbad0a15, 0xe95329a6,
13612 0xb101ca5c, 0xdcb91e2f, 0xf83dec34, 0xf76f027d, 0x0f63fc5e, 0x2ea1b5fa,
13613 0xc00bdd23, 0x8dcf5e94, 0x4bf12f78, 0x0c33dd0a, 0xf78d54f4, 0xe2fd3d1c,
13614 0xf3b444f9, 0xf2e2ccde, 0x2e2ccdec, 0xca2e070f, 0xe45e74d5, 0x729c8fc5,
13615 0xce9ffd0c, 0x4d3ec592, 0x039e0f4f, 0xf3c658d9, 0x1ec2eddf, 0x57d8bfb0,
13616 0xa7dbf08f, 0xc52cc4fc, 0xb21fdbd0, 0x46d704cc, 0x0bcd2453, 0xc98f05fd,
13617 0x82ec9bac, 0x6dafba5e, 0x939b9cf0, 0xfca9a1e3, 0x8ef68659, 0xe3df8bbd,
13618 0xe54b3a76, 0x3ee01672, 0xc613ef04, 0xc3ace47e, 0x2f1872fa, 0xc3bdfa3f,
13619 0xa133d7c9, 0xb2a3df82, 0x383f8ae9, 0x24b89ef1, 0xc7fdd189, 0xea36c83f,
13620 0x57ada1ce, 0x2cec1cb9, 0x3b41e9ef, 0x2854e42e, 0xfbb3a72f, 0xfbda0b0e,
13621 0xf2f85f1a, 0x8ad7bcf8, 0x4ed77cfb, 0x39e30e29, 0xd78e8d14, 0x202e0764,
13622 0xbe046edf, 0xafec9c78, 0xc274ff1e, 0xf314b38f, 0x1eb0275c, 0x9586afba,
13623 0x87c89c9b, 0x8e8306c5, 0xe6c9aedf, 0x413da374, 0xf3dd93fd, 0x9abb4163,
13624 0x2c3b97de, 0x7db5cf0c, 0x1276717c, 0xb672a7da, 0x9d79ef66, 0xed8fc788,
13625 0x7c4ec973, 0x0df6b7fb, 0xda0779b1, 0x73f02df3, 0xcb44c7bb, 0x59febc8b,
13626 0x0b317ed8, 0xe97683dc, 0x775976e2, 0xc16dffde, 0xda2e8be7, 0x9d8c7758,
13627 0xf7ca68bf, 0xa2d2bce8, 0xfef4898b, 0xf49f916d, 0x2a4bc8b6, 0x8af0f314,
13628 0xdfd915e7, 0xc6f7fed0, 0xff5dcbc9, 0x972d48f9, 0xd0d98597, 0x6bd4a36f,
13629 0xe36a7f42, 0xb9d0bfd4, 0x7fc0b791, 0xd17f36ef, 0x7758533c, 0xed83b8cc,
13630 0x77595a2e, 0xa8baec4a, 0xbe747704, 0x6b7faa76, 0xf04be7a5, 0xc7874a38,
13631 0x3a05ff68, 0xbfed0e3c, 0x5adfea88, 0xfd25fc59, 0xffa11f8f, 0xd1fc1d3c,
13632 0x7de90b7e, 0x47da89ff, 0x272fc06d, 0x78ef57ba, 0x8eebf30a, 0x7cfee99b,
13633 0x8ab3b876, 0x92fdafce, 0x3bc6b9d1, 0x06f27f8f, 0xb9ddcde6, 0x31c5e4c7,
13634 0xf9918c06, 0x43f461de, 0xf0867321, 0x79ed291e, 0xcd017643, 0x45bdfe27,
13635 0x0f313b09, 0x38ac52ce, 0x58593f51, 0xf135784f, 0x93e48583, 0xfad79716,
13636 0x2672871d, 0xf76a3e46, 0xf62bbc85, 0x0b60ff8d, 0xc0aecc2c, 0x8157f732,
13637 0x9c623773, 0xd961e1ad, 0x7421efc9, 0xc5a23f91, 0xf3f415bb, 0xe3d4300a,
13638 0xe3fe7867, 0x4b03723f, 0x0e7e6e91, 0xdfe300e2, 0x01bd84f2, 0xff0a4f8a,
13639 0x8f6b3eef, 0xf7231bc7, 0xdf2b6456, 0x8b6fdf4c, 0x7f1537d3, 0xeb9ba47a,
13640 0x8f38159b, 0x57e7b946, 0x8e7879b5, 0x1bdc57a9, 0x5bdd92a5, 0xee927e5b,
13641 0xfcd5ab97, 0xfbf175f9, 0xb42ed9ec, 0x7cf8b583, 0xa13fe622, 0xf3c8dfbe,
13642 0xbc6cebef, 0x14fbf75c, 0x4789cf3a, 0xef104a45, 0xdf97b29d, 0xfc24e82b,
13643 0x0f30179e, 0x20e63658, 0x9e04077e, 0x433d77cf, 0x5f9e18f7, 0xa0e89a37,
13644 0xa53f37ee, 0x640ec97b, 0x63acfc8a, 0x7543d20e, 0xde256f66, 0x93207793,
13645 0x4a9d9bdb, 0x8c596277, 0xab36b9fd, 0xfbebe48a, 0xd01b46eb, 0xbaf0d73e,
13646 0x8d85c853, 0x89503c5a, 0x6dfde254, 0xbf7797ef, 0xa0f07a4c, 0xc6e77e95,
13647 0x4a93e870, 0xa3714fba, 0xafa5ee99, 0xcb76343a, 0x2c6fa83c, 0xa8be5032,
13648 0xe09590e1, 0xdf9eb739, 0xa2df84ef, 0x343c6ebe, 0xa80f7e8a, 0xbca116ce,
13649 0x6f04c6ae, 0xd497ee11, 0xdd16fa1d, 0xbee67f27, 0x372839b1, 0x39aaa74f,
13650 0x7dee7f74, 0xf7987480, 0xf86363e9, 0x74c9d6fb, 0xd1b1d25e, 0xae2e1816,
13651 0xf893e9a1, 0x640ea3fb, 0x461ff696, 0x78b58cfc, 0x917940f7, 0xb8b03f76,
13652 0xf9eeac0f, 0xf3151cc8, 0x557f85ac, 0x33ef7f67, 0xfdadf7ba, 0x3d385bcd,
13653 0xcd027df3, 0xb71f8b3f, 0x039de84e, 0xfc7cc8a6, 0x35baa67d, 0x9e26ff02,
13654 0x28675687, 0xd327dfa5, 0xee31bff0, 0x0457d57e, 0x99e7b5de, 0xb7ba1517,
13655 0x1c81ec0e, 0x733a57dc, 0x76f44cdc, 0x3a78e366, 0x578dad2f, 0x0271b807,
13656 0x564e9e9f, 0xfefae227, 0xbaafc859, 0xd4efdc35, 0x3619d7de, 0x477ae357,
13657 0x6f94c98e, 0x248ce033, 0xd6887ee2, 0xce0f2b4e, 0xdfa64ba7, 0xf9903a19,
13658 0xd03bad34, 0x32ba4315, 0xfa41c6fc, 0xfe1bf836, 0x97ef457b, 0xf50d90b3,
13659 0xf266abf4, 0x331c4ed3, 0xf03c1d93, 0x3b773f1a, 0x7b2f1ee4, 0xadef0724,
13660 0x1466fe0c, 0xec81b5c9, 0x376e6ec8, 0xb8dee95b, 0xc9815381, 0x432cff62,
13661 0x81978bdc, 0x6385daf6, 0xd7b46ed6, 0x20fb49e0, 0x43d7b621, 0xe8db8fef,
13662 0xd2780ffe, 0x1d260939, 0x9cefd0f4, 0x7df136b0, 0x677f7d0f, 0xca0c604e,
13663 0xa00b3be9, 0xdf7e3b7f, 0xe42eed47, 0x19612607, 0x78c532fe, 0x766fd499,
13664 0x4bde9720, 0xeff8791f, 0xfa89b47b, 0x9a0faa1e, 0x1e699303, 0x8eb0767f,
13665 0x4df9e661, 0x2f7b7fef, 0x9be4853b, 0x99e03706, 0xbc78bfec, 0xe20c7278,
13666 0x3e385df7, 0x7072e9e2, 0x3e04bf3d, 0x5f90a78c, 0x71d7c5d2, 0x971358fd,
13667 0xc9e3ad27, 0x431ba5ce, 0x569af262, 0xe89b7b1d, 0xdbe8c072, 0x72297a8a,
13668 0xbdf8c8ca, 0x6019606a, 0x6f0a619c, 0xfce36757, 0x9ef1c1a4, 0x686e6fc8,
13669 0xef4f79e5, 0x9cede2fd, 0x273c7605, 0x9ceeb6fb, 0x83f716ac, 0xae31124e,
13670 0x89aaf762, 0xdedc25b5, 0xfe2e0996, 0x8d1b4dfb, 0x554efd2a, 0x14b1bee8,
13671 0x5263384f, 0x8ebdd10f, 0x901827eb, 0x5cbd5a9e, 0xf8da84f6, 0x9afbb4bc,
13672 0xe2977bb4, 0x9cddf2f1, 0x38bbfe02, 0xde2b702c, 0xa99a7dd9, 0x8db36269,
13673 0xc7ab9fee, 0xebca017f, 0x2b3e0d0b, 0xbd25bfcf, 0x379ef430, 0x8efc97d3,
13674 0xf96dffd5, 0xe68cb907, 0x250dead9, 0xc77d5ea2, 0x583efdc9, 0xbbf4953d,
13675 0x7749e7cc, 0xbea066e8, 0x939adff6, 0x0724f54a, 0x7d7891df, 0xf2699d3c,
13676 0x903e086e, 0xfc5fb06e, 0x3dbefa0e, 0x48d5c787, 0x79bde058, 0x7ba2642c,
13677 0x0abe8461, 0xcf018a4a, 0xd4b9f775, 0xbecba444, 0x55e482d6, 0x52e0a798,
13678 0xe862cad3, 0xa32cf824, 0x9e2accf3, 0xbf8c984f, 0x889be273, 0xc903bcf1,
13679 0x3c4238fa, 0xeb4f8f3c, 0xff5b1f9d, 0x772e1cd3, 0x1fb8735b, 0x261cebf8,
13680 0x3c78feec, 0x22583a72, 0x1bd5a0e8, 0xcafc8ab8, 0xb64b76b8, 0x88fa0925,
13681 0xd4f6df7b, 0xcabe533f, 0x85bdfd4e, 0xde3d6235, 0x9214de79, 0x8133e126,
13682 0x37eb8df2, 0xff577973, 0x5dd14d42, 0xfce74cbc, 0x4ddc75a7, 0x70b30fbf,
13683 0xc622cccf, 0x8bad17e5, 0x730b9f46, 0xdf68457c, 0x4ecbb645, 0x6dfa93e4,
13684 0xaad3c132, 0xc3b659b4, 0x8cdbb3fb, 0x0bd5f764, 0x0566ce78, 0x14dd6912,
13685 0xef0098a6, 0x22409567, 0xc5dbb5d9, 0xcdc4e0ef, 0xa2bdda03, 0x1f830d94,
13686 0xc2675f0b, 0x7430c14f, 0xeb40ca70, 0x898130b4, 0xe89347df, 0xecd9c79c,
13687 0xee58adc0, 0xee9e7f03, 0xa06b6e9f, 0xf1e2557b, 0x2012d67d, 0xe6225d7a,
13688 0x7e33e1a3, 0x039f0d1c, 0x9fb44f88, 0xfa41df9e, 0x8ca0f82f, 0xee9ecc14,
13689 0xecfc90fa, 0xbe66c769, 0xbf7c2df1, 0x1518ec19, 0xcbfe6df5, 0x077d47df,
13690 0x98ed0a72, 0x690563da, 0xa36f4e2c, 0xd2fb593f, 0x8c4344dc, 0x976d6cbe,
13691 0xb5a59f69, 0x22e24e70, 0x06fe7f6a, 0xaad3afa4, 0xa62cad37, 0x9a392bdd,
13692 0xaf5fa93f, 0x4d7fcdba, 0x37ea71c4, 0xda5e6918, 0x4c000cba, 0x6cdb8724,
13693 0x81ffa461, 0xabf508ac, 0x7d20d3ad, 0xf4683ae3, 0xcd3eed04, 0x78718a71,
13694 0x2f2fb6bc, 0x861de950, 0x003f164e, 0xdb7f62e3, 0xe69f741c, 0xe1ab8ea5,
13695 0x05bd7063, 0xd719535f, 0xc51e7771, 0x14a70dc7, 0xdd3f064a, 0xf20e4d76,
13696 0x07d81d71, 0x93a88718, 0xbdd06f22, 0x74ccc7a6, 0xe6dd6fef, 0x78e2b7a5,
13697 0x0d99af75, 0xfc77df58, 0x5704899a, 0x9e02badc, 0xf7a38672, 0x8e48bc81,
13698 0x607f0637, 0x6b7f1057, 0x9b8189f3, 0x8b3f00e0, 0xc819c5ee, 0x918cf583,
13699 0xe1cd7f03, 0xef681af1, 0xf37d1134, 0xe706997b, 0xaf9b8ceb, 0xafbe6e33,
13700 0xe66fa230, 0x167cd00d, 0xe0366ebe, 0x5ff785fb, 0xb771845f, 0x69d3f5be,
13701 0xbec97d5e, 0x7d5fc889, 0x30ffd039, 0xfde172f2, 0x2f92cf30, 0x959b6798,
13702 0x79c46bd6, 0xb3764726, 0x27a7982f, 0xb7cf3f57, 0x7e913514, 0xcc88e34f,
13703 0xcc128e30, 0x16fc6ff6, 0x97efd32f, 0x1e9c8d05, 0x746d9b82, 0x8bbfaa2e,
13704 0xc9af8fdf, 0x12ef1801, 0xf440c1e9, 0x6ea557d0, 0x75f48299, 0xfdc4ec9f,
13705 0x97f5be8a, 0x2fbf8cbd, 0x7651b7d7, 0x57d0dda2, 0xf207f1c5, 0x5f78f480,
13706 0x2a06ff8e, 0xefd2371f, 0xfb699da4, 0x3ee89feb, 0xfa466382, 0x3c81e23d,
13707 0x5879c6ff, 0xae517806, 0xe26e5e01, 0xe691ab76, 0xc1eebadf, 0xda1f5875,
13708 0x6fce8936, 0x7ad7d50c, 0x906fd73c, 0x14c87c75, 0xde0bc695, 0x17ee8a3f,
13709 0x120cf0d1, 0x23fd08b6, 0x9e581f0d, 0x978a213b, 0x8f7f38a0, 0x8fbf0276,
13710 0xc433c84b, 0x13d73e4f, 0xe5058e78, 0x19a79e18, 0xcbc55f49, 0x7bbd789f,
13711 0x4fb6ae63, 0x0dc797a9, 0x79afbf71, 0x69795c5b, 0x1658dc9c, 0x5718df57,
13712 0x86f9fa0f, 0xcfd2e2e1, 0xa2cf8e0c, 0x1a21927e, 0x4fb81d1f, 0x56b4bf22,
13713 0x07e84d51, 0xeb8d3e3d, 0x59853ae7, 0xe4be22ae, 0x156a73e7, 0xc32e62d6,
13714 0xac535ef7, 0xb5fd04bf, 0x9ca19398, 0xb410e5c0, 0x94c536ab, 0xc1ab7935,
13715 0xa3c04ab3, 0x9c76bf3d, 0x7dc466a0, 0x15b9558c, 0xca31f743, 0xbf5ffce4,
13716 0x11d67e88, 0xe0ccfc99, 0xb0ff5c0b, 0xf2dc3f4f, 0x3bef1b98, 0x323ca02e,
13717 0x78f1fe6d, 0x61fc381c, 0xe4defd22, 0x5f3a26f3, 0x5295db5e, 0x72587e45,
13718 0x6fbc5864, 0x44fae5cd, 0xe95fafeb, 0x6b1d9c4d, 0xc4deb347, 0xadf7dfd8,
13719 0x4ae1fc3d, 0x7f016bf4, 0x8e463921, 0x5a96399f, 0xdd65fe85, 0xf0ab32ef,
13720 0x5cd1efbc, 0x3ea00e2d, 0xe6f901bc, 0x13e29988, 0x33cc2ffd, 0x2ffdf7e0,
13721 0x9de78bd4, 0xff609f74, 0x7072675b, 0xfe8344fc, 0xcf7f89be, 0x9d54f6e5,
13722 0x57ddcde1, 0x9a3ffca2, 0x2626b79e, 0x28675d0e, 0x31f8bf23, 0xc23e6463,
13723 0x3aff760d, 0xfad503cc, 0x12ab9a39, 0xde47fd1c, 0xe1f28dde, 0x32ecc6cc,
13724 0x47fd2b14, 0xdc1f90c6, 0x4565daff, 0xff6b5f78, 0x945e197d, 0xd5198f0b,
13725 0xe2dfb93b, 0x8bc9eef0, 0xe0e387f6, 0x91ff63fe, 0x3f1895c9, 0xc38d7fe8,
13726 0x278a650b, 0xe610bb40, 0x26fd6a5f, 0x984dd41a, 0x677ece8f, 0x8ee2bf24,
13727 0xf1d20acf, 0xd344957e, 0xa050f7f0, 0xc3cfa11f, 0xd6f34d5e, 0xfde37df2,
13728 0x37ff2d0c, 0xeed30fde, 0x17f78f8b, 0x3ddb59eb, 0xef1c9798, 0x6e618237,
13729 0xdf89a509, 0x4ebfa733, 0xf74bf7d2, 0xdfd66e7f, 0xf6121d9f, 0x71e48580,
13730 0x7ae3f02d, 0x79853f8a, 0x3c9d6fdc, 0xc5ec7eec, 0x6fa76e5c, 0x7e6dfdb5,
13731 0x9ebacc6f, 0x03c53036, 0x626d3d78, 0x70d94f16, 0x9c85e3fe, 0xc37b925a,
13732 0xb1758dfb, 0xa1b1d6f7, 0xaae9e47e, 0x9df9e530, 0xefd32f5e, 0xf5c3c459,
13733 0xf8c8fd55, 0xebdfb5ef, 0xc4ed04f8, 0x00938c54, 0xe45fc9a4, 0xd5e1eb3f,
13734 0xbf1569f0, 0x01fff2a3, 0x949113dd, 0x00008000, 0x00088b1f, 0x00000000,
13735 0x7db5ff00, 0xc5547c0b, 0xbddcf8d5, 0xc3764cfb, 0x083c8426, 0x813bcd84,
13736 0x44902c24, 0x8f2ed4ac, 0x0310f0c4, 0x5850822a, 0x89de4020, 0xc5b0fd60,
13737 0x40802166, 0x151a86d1, 0x260dda2b, 0x22ec1208, 0x760d1201, 0x4a888941,
13738 0xadb45503, 0x202a25f2, 0xd4109204, 0xeb6bfe8f, 0x73339cff, 0xd0820fb3,
13739 0xcfe8fbf6, 0x99dee64e, 0x7de733b9, 0xfd999cce, 0xf7f87bfe, 0x17bec613,
13740 0x62a2d9a5, 0xc963106c, 0x2d9990ff, 0x43b2b194, 0x891ae71a, 0xafdac0b1,
13741 0xf50b999f, 0x398d16ee, 0xf958c2c6, 0x6726d921, 0x659ac630, 0x3e0c4267,
13742 0x08a822ff, 0x8f3797de, 0x33cccb31, 0x9cb3795e, 0xac654ce7, 0xd86ae9ab,
13743 0x671a54e2, 0xfd88c5ba, 0xa1dab69f, 0xc2acc834, 0x57b4f465, 0x4c8b58ca,
13744 0x69de28f3, 0x9932fea8, 0xe1efbfd1, 0xb05752bf, 0x29bcbd4f, 0xbd4bfab2,
13745 0x7f8c5ea7, 0x367fc244, 0x8c5967a6, 0xec57f095, 0x6187ea72, 0x5dde6053,
13746 0x1912e7b5, 0xb2a8d12c, 0xa1325ac7, 0x169df89e, 0x67b58ceb, 0x7e6899e5,
13747 0x67981641, 0x20dbf3b7, 0xb7d2f306, 0xbf9c36c8, 0x2c32fcff, 0xff32c65a,
13748 0xc2e5f983, 0xf33cc2fc, 0x5864f983, 0x59e67906, 0xb2d1e966, 0x3e879858,
13749 0xc48d9d28, 0xa369b616, 0xfc22fda0, 0x6a2fde13, 0x058d3c59, 0x79a93631,
13750 0xe0031ac9, 0xb25abba1, 0x7e79e0ea, 0xf00dc00b, 0x764dbf90, 0x932f005a,
13751 0x311d5692, 0xd3f17d40, 0xe6ba1ef0, 0xcf4ee3c8, 0x9ecbf686, 0xb87ea990,
13752 0x1ad391f6, 0x0d36ebc4, 0x031e21d3, 0xef8bb682, 0xa15f9c31, 0xcb615f98,
13753 0x7c120bd4, 0xd921d96f, 0xf5fec6ea, 0x5f3e2b26, 0x79f341bc, 0x96fad7bb,
13754 0xde301fe0, 0xd392ad92, 0xa92de30d, 0x95df7df6, 0x38b2d0e9, 0xefd5bfe8,
13755 0x99faed79, 0x54b14247, 0x51d60933, 0x8f7df4e8, 0xf986deff, 0x77bf8b94,
13756 0x8c1e6c26, 0x3032e9f8, 0x61f806d6, 0x8630f6ea, 0x1a3dbba5, 0x7cd5d8f1,
13757 0x58f11a36, 0x24fffafe, 0xa7f07eb2, 0x14c5ac94, 0xe0102e7a, 0xf7d89169,
13758 0xabfba42a, 0x69faf3d3, 0xe7087a3f, 0xc71a9d8b, 0x3fbc2b60, 0x746dfb52,
13759 0xb349d23b, 0x1fb9987d, 0x9f1bedfa, 0x08aa0c39, 0x8606dd2c, 0x3ccb8665,
13760 0x4de4f905, 0xd213798d, 0x33f5f6c7, 0xf0dd43b7, 0x00660686, 0xf12304f5,
13761 0x12c7f20b, 0x3e1571af, 0xd9b129d9, 0x99426654, 0x6892f38a, 0x930fdf5e,
13762 0x1e771e88, 0xd09e9dee, 0x69867cdf, 0x21e8dda8, 0x347dda8c, 0xd2356f2c,
13763 0x11ca805b, 0x3660f884, 0xe014259b, 0xaafa092b, 0xe121595a, 0x4d5608f3,
13764 0xa2e610e5, 0xecc605f2, 0xaccf6c46, 0x63338466, 0x7e118343, 0x5eb4f3c4,
13765 0xe6e90abb, 0x9b770267, 0x8e0f4e24, 0x87ace660, 0x3d5ae5bf, 0xa6300793,
13766 0xd841ed65, 0xf33694c9, 0xbde0c3d7, 0x255943e6, 0x43c8bd01, 0xcd5a7c15,
13767 0x8c6fdf88, 0xc6f00df7, 0x17f7e1df, 0xa578e2e5, 0x83a665fb, 0x6a372ef1,
13768 0xed88db98, 0x9da05f81, 0xb5affde6, 0x5a972831, 0xeb009624, 0x3e3a8728,
13769 0xb6a71f2f, 0x52e0bd39, 0x78f0e16f, 0xf04892da, 0x8edb52e8, 0x33fa434d,
13770 0x2c3ad22f, 0x2e7e4e38, 0x11347183, 0xaf38b48b, 0xd04fefc3, 0x82de20c7,
13771 0xeb37c4d5, 0xb6ef945b, 0x64fc7199, 0x78f329d5, 0xa993df78, 0xf1e1db66,
13772 0xcdc6a3f9, 0xf7ca47c8, 0x3f1c2cba, 0x12812b67, 0x97cf3c92, 0x8397dc64,
13773 0xfb3297fd, 0xa5a3a47a, 0x7b733235, 0x0d79fdd1, 0x6b92f7c7, 0xc63dcc81,
13774 0x4cc45fab, 0x6b92d75a, 0xbcfcf441, 0x6f3bb781, 0x9ef174e2, 0xc7c5d385,
13775 0x885fbbe2, 0xaf2dbffa, 0xeaf2beac, 0xef1f0bf2, 0xd6e5c458, 0xa547487b,
13776 0x44ce7b52, 0x88fac4f8, 0xf5ca2d5e, 0xe66695b3, 0x3ad0fdd6, 0xd7b73207,
13777 0x5ddafb77, 0x40f73033, 0x6859b86f, 0x1af59efe, 0xcad9fde9, 0x31c09b88,
13778 0x9e8e07ca, 0xe07ce3f1, 0x89f8fd78, 0x656cfef4, 0x1fc64df2, 0x63f18371,
13779 0x19efe67c, 0xaf9e9e37, 0x20b1554d, 0x9fb5aba0, 0x6cc49ce8, 0x74a7ae7a,
13780 0xbad6ef82, 0xfd2de927, 0x4d83aff0, 0xe163628a, 0x8b9ca37d, 0xbcd97c74,
13781 0xae7c8cc8, 0x74b90609, 0xd8d7f41b, 0x7180ef72, 0x0321c175, 0x5aaf7e91,
13782 0xdf5d68e2, 0x1d105706, 0xb4743b7f, 0x8fc188ec, 0x7d61e454, 0x997c90ed,
13783 0x59fab378, 0x7ae5f392, 0x21d37dfe, 0x9fe44a60, 0xaf42f5db, 0x18bcc9ff,
13784 0xd43553be, 0xf4c98fae, 0xf994c7cc, 0xb33c4336, 0x9430fb26, 0x819b8f03,
13785 0x801f896f, 0x5abd61af, 0x3bbbfec9, 0x9fd81f80, 0x8a1eac75, 0x24f60d6f,
13786 0x471f17b3, 0x09fd70c4, 0x728510dc, 0xa86ac1d1, 0x4aba6f2c, 0xff00b670,
13787 0xf794bae2, 0xe087ace5, 0xc2cd7c8e, 0x16d52691, 0x4f64df7a, 0xccf34bca,
13788 0x78eecfa3, 0x0150e8c7, 0xfd0ee9ff, 0xd9e10823, 0x6e99eead, 0x22d5d285,
13789 0x77c37a07, 0x8fe70c64, 0x4ebf4309, 0x65e7876f, 0xd3e40fd8, 0x27166f23,
13790 0xd329fca1, 0xbce3a4f5, 0xf7f9bc8f, 0xdff79474, 0x861e2a1e, 0x7b4277cf,
13791 0x3db413b2, 0xf1af5665, 0xa1d999e2, 0x9329eb1a, 0xef88e263, 0x3cef9ffc,
13792 0xe7183554, 0x886200d1, 0x5677c085, 0xe5f717be, 0xdb072440, 0x18672853,
13793 0x0b7a97c8, 0xcaf74dda, 0x3eca5728, 0xea04db02, 0xbf5ccd19, 0x4e650c67,
13794 0x67da0c55, 0x7c46cd1f, 0xcd6a6595, 0xc04a582a, 0x1ae736a8, 0xa9901f78,
13795 0x1d1ea337, 0x5f7f843e, 0x0e3cfa8b, 0x440f67fb, 0xe414fdbc, 0x0f247fec,
13796 0x2becfcea, 0x06b2a9f7, 0xdca95ef8, 0x00e51d3e, 0x31e985c8, 0x07d97e30,
13797 0xb5489f5f, 0x309e8b60, 0xd0b74fc4, 0xe3127f3f, 0x37931a3c, 0xfbaae913,
13798 0xe3d777fe, 0xbb2437a3, 0x88e3d71d, 0x5f515bd4, 0xec6708b0, 0xcebc2f4c,
13799 0xba09518d, 0xba01ee01, 0xb6e62e1d, 0x796bb067, 0x6725e930, 0xb943d208,
13800 0x1e51d98a, 0xd40069b2, 0xf32e91db, 0xf5a666d2, 0xd0d79fa7, 0x6c62cb78,
13801 0x4abe708b, 0xcd668ffb, 0xc3f7b34d, 0x04a94887, 0x21ebad4f, 0xa94f679c,
13802 0xf01dbad1, 0x82be21f0, 0xd2cd2f7e, 0x93b065b9, 0x0dc635ba, 0x27d1d012,
13803 0x075bf381, 0x184ffac1, 0xceb815ed, 0x5e4c0fd9, 0xc8e9758f, 0xa472cb40,
13804 0x59ed85cb, 0x06399788, 0xbef8c3fb, 0x161f6f44, 0x3cbc4b06, 0x00349ed4,
13805 0x40de6a95, 0x97966f0e, 0xfcefd796, 0x753c7cf9, 0x54b7fa46, 0x31b7a5c0,
13806 0x49d9006e, 0x67480daf, 0x152e9f30, 0xd0fd402b, 0x15fbe625, 0x25e623e8,
13807 0x279c0ba7, 0x7da10bb5, 0xed49dd61, 0x97f5af22, 0xeae08582, 0x3a7a2ec7,
13808 0x1745db86, 0xdbfefdf7, 0x9d50c05f, 0x44481cdf, 0xba58b5bb, 0x76faeb44,
13809 0x62f9c9d7, 0xbeb8d57d, 0xa27b7a47, 0x12aeb0b5, 0x972d61d7, 0xea7d621f,
13810 0x5a1fc49e, 0x2daa975f, 0x80e2e887, 0xf18fae64, 0x3c6d2bf4, 0xf4051399,
13811 0x3c17505e, 0x9674e65a, 0xe8567488, 0xd1788f84, 0x028e32b1, 0xde42e59f,
13812 0xf014aef5, 0xb676e009, 0xfbe51f02, 0x33e0fc67, 0x8d93dd5f, 0x2abf98f3,
13813 0xa9e5c558, 0x7947e893, 0xefa560bf, 0xfb14ab77, 0x49c931e7, 0x7ebc66f3,
13814 0xdcec11d0, 0xea9d7504, 0xa2f787ea, 0xb2a690dd, 0x2db0dda2, 0x68c06400,
13815 0xf028fec6, 0x07c802f3, 0xdf3d087d, 0x0223cf80, 0x6788ff78, 0xe82ace54,
13816 0x99a1379f, 0x32a5f0e8, 0x6f8655a3, 0x98e0642d, 0x331614c0, 0x67d9d91b,
13817 0x50fdffc7, 0x68f3ac3b, 0xf08ddd8c, 0x1550305f, 0xc3cd21fd, 0xda06623e,
13818 0x1c38e36f, 0xfd17b3af, 0x99933fe0, 0xb1e46435, 0xfbe42acd, 0x94be6699,
13819 0xe3e71225, 0x834d997b, 0xd99fbbdf, 0x2ea9dda9, 0x93fd0dad, 0xc15be853,
13820 0x0e601fbc, 0x39873e7a, 0xdccb9ca9, 0xaca7fed4, 0x1f0aea9d, 0x082ffd00,
13821 0x3e7ff4e5, 0xf9ba265c, 0x327de718, 0x4ae87d30, 0x678cc758, 0x5fc81293,
13822 0xf04419ab, 0x67bcd9b9, 0x8f8e1c48, 0x71dbd8c6, 0x6fdcde9c, 0x7181ac5e,
13823 0xd1377a54, 0x989c9f5f, 0xe1d04834, 0xb689cb0f, 0xcc7f3ede, 0xb8700918,
13824 0x2ef4a04b, 0x63f9315b, 0x3991b2d9, 0xe36d3f00, 0x53fa2764, 0x43ab6cc7,
13825 0x93aa6543, 0xcab36d5e, 0x59dff7a4, 0x50194ccd, 0xc694677f, 0x6b74455a,
13826 0x5d3c3d23, 0xcd7d978c, 0x7800f6fe, 0x586e5d3e, 0xdcf50c1b, 0x790fe021,
13827 0xd0e4d5d1, 0xb3e46abd, 0xcfbef129, 0xfafaa5a7, 0x6ab3774d, 0x3d3be119,
13828 0x61ddb7c3, 0x95d00b84, 0x3ffb962a, 0xfe1b386c, 0x8fe1ecbd, 0x31f9147b,
13829 0x1bb6aaed, 0xd62631e6, 0xf585886e, 0xecfbbf2f, 0x532efc7c, 0xa0c60fb3,
13830 0xb3213a5e, 0x73fef04d, 0xd81b13e0, 0x82565f4b, 0x397e0306, 0xd61ff607,
13831 0x0d3b02bf, 0x16958bcb, 0x5d812f2a, 0x2abbef85, 0x207f54ad, 0x16242f36,
13832 0xc368bf40, 0xed1db515, 0xfa2ceafe, 0x5f410afe, 0x2ab72a6d, 0xbb67f910,
13833 0xb87d4564, 0x2136d0c2, 0xa2b6e010, 0x180ac63e, 0xae4d4566, 0xbe7e9c56,
13834 0xd1072f3b, 0x4558f4b8, 0xd7a5962b, 0xd2076624, 0x8bce417e, 0x3ebbf1c6,
13835 0xddd67cfc, 0xe57cfcf0, 0x85fefa58, 0xbf7d1b4a, 0xca9732b3, 0x3c7b588a,
13836 0x74b5b3b6, 0x20b40eb4, 0x7d10ae36, 0xa1d0dddc, 0xb67a828e, 0xdf21b24d,
13837 0x4e6369dd, 0xab75e027, 0xada9eb86, 0x0f90a7a0, 0x7ccda7c7, 0x7a8661e1,
13838 0xe38e9ec4, 0x30a53fdc, 0x3e99c71b, 0xdb1aa176, 0x631df03d, 0x743c6303,
13839 0x65ba3376, 0xf2fc727e, 0xddd1129b, 0x1ee59565, 0xc71cabb4, 0x7a0fb265,
13840 0x185530d5, 0xe193f7bf, 0x74e0074e, 0x70b8fef9, 0x35cb6794, 0x2f10f096,
13841 0x27e9d639, 0xdcf73ac7, 0xdfade116, 0xdf5c433a, 0xd0e505fe, 0x810e5c67,
13842 0xb7ee74a5, 0x118ca728, 0x976fc456, 0x520043f0, 0xcb8fa881, 0x406f82b4,
13843 0x33bd608e, 0x83c82d80, 0x51abd67a, 0xf00f9013, 0x8f24967b, 0xf57c499c,
13844 0x585fd8d9, 0xe9dbdf3c, 0xdf97f25a, 0x53b2fd42, 0x5e80d0e5, 0x5d5cccba,
13845 0xeabae3af, 0x17b4568c, 0xc0752593, 0xefec10ca, 0x964bbe24, 0x2095ea2c,
13846 0xfabd7647, 0x19e7e0c2, 0x8d8c09da, 0x6c6ff785, 0xf3392409, 0x667ac686,
13847 0x817ff625, 0xc9f97ff7, 0xc26f3f47, 0xd1d289f2, 0x1059428f, 0xcd70421b,
13848 0x70e14dff, 0x5111b3a4, 0x6f180680, 0x6dc941f7, 0xad2c6748, 0x489af0e6,
13849 0x6dc8cf98, 0x50c1aa1d, 0xaa93aa8e, 0xca611cb0, 0xfbc3263d, 0xcd0b58b2,
13850 0x8c434c63, 0x32ec851c, 0x9f97f9d8, 0x6be1bd90, 0x5cd6a487, 0x79983099,
13851 0x92e191ec, 0xa5e222eb, 0x347a74ca, 0x4d563be9, 0xb96fece3, 0x69734ff7,
13852 0xe0e9601d, 0xad6a17bc, 0x8e9c1fa4, 0xcbb3a45a, 0xd92b64f6, 0xe78e79e7,
13853 0xed97bf10, 0x17d45661, 0xff5fc007, 0xa33fb611, 0xac1e75a6, 0xf184193b,
13854 0x07e0019b, 0xe97de01b, 0x93d21ea8, 0x0c2d43a5, 0xc5f43bbf, 0x3e1172bb,
13855 0x6bfb8d65, 0xbd129c69, 0x82d9fd15, 0x515b57fd, 0xccc9b26f, 0xd5f4809a,
13856 0x9abfebc8, 0x1ea2b364, 0x86fda82d, 0xa8f2dbd7, 0x83de079e, 0xe62fdb1a,
13857 0x42b3d976, 0x74f6b12f, 0xb2445b92, 0x7ebe0f16, 0xfdf1af05, 0x644718d6,
13858 0xcfa3d185, 0x416d0f40, 0xf2d488fe, 0xe6136dfe, 0x6e5c1346, 0xe3290f51,
13859 0x0e65ab3c, 0x2d45ea03, 0x20f597d7, 0x603e902f, 0x7c7117fc, 0xc9466f45,
13860 0xac235a52, 0x1d59ea3b, 0xf8b7b397, 0xd603d99d, 0xec54de93, 0x1f6172b8,
13861 0xe8136154, 0xbfb465df, 0x8970f282, 0x6d4cb3d0, 0xe3bb4549, 0x776da333,
13862 0x6071d92c, 0x7f48a8e7, 0x65eb1efd, 0x7175d832, 0x319d765e, 0x17f496e4,
13863 0xe3f6d933, 0x7db56e7a, 0x9fe798a8, 0x03433cc5, 0x1d2c9da2, 0x87f80afd,
13864 0x7858e984, 0x587186d2, 0x447ef1f4, 0xc156eb24, 0xe11d073a, 0x8bb1e3f5,
13865 0x1b05acb7, 0x77a47dfd, 0x3382470e, 0xfb430050, 0xca6e794c, 0x6210f4e0,
13866 0x11dd93d7, 0x5462b03e, 0x337d1785, 0xc20c7bb5, 0x653fd363, 0xdb7684b7,
13867 0xfc5233ff, 0x86de7fc7, 0xfd7fee38, 0x150e624c, 0x2d15d7d2, 0xb4d16bb5,
13868 0xf43dfeef, 0xb54c296b, 0x007b3fa2, 0x71c7adf0, 0x8ec96a66, 0x05db416a,
13869 0x09ccb7da, 0x86f7b923, 0xc741cb86, 0xdfde009c, 0xf7c10000, 0x689dc3ab,
13870 0x55d60da7, 0xe38697bc, 0xdf120557, 0x1b9c68b4, 0xc7fc7162, 0xb2f8d206,
13871 0xe8e1bdfe, 0xe4227d7f, 0x9ee49551, 0xc76df18b, 0xefc32d15, 0xa3bb04d5,
13872 0x535ea1ca, 0x7fda9c38, 0xed192a02, 0x5b609ac4, 0x03d9ca24, 0xfe4994ff,
13873 0xba828cd5, 0xc513e491, 0xd8666a61, 0xfea18322, 0x4d4bc0a0, 0x99feb3ad,
13874 0x4c9e7c50, 0xb8c60ce3, 0xe18bb61e, 0xc345fce3, 0x07a7d9fb, 0x075ed1aa,
13875 0xf089144d, 0x027e6dfb, 0xe3c2d2c5, 0x0871c826, 0xcfb7e15f, 0x19477216,
13876 0xb3e83b1f, 0xffe30ed0, 0x37a92ce6, 0x5fdd7f20, 0x0d00e860, 0x58293ec2,
13877 0xf5bf4263, 0xd6ecbb7e, 0xf7605c81, 0xecfadb65, 0xdf1c5882, 0xbd21c726,
13878 0x937e2be5, 0xf5c2317b, 0xdb3d1ecd, 0xe0237644, 0xba7aed35, 0x1fdf80bb,
13879 0xf8e3fe80, 0xc7fdbca7, 0x9fe71d42, 0x6887480b, 0x43da060f, 0x4de5fe70,
13880 0xf6f29f93, 0x592ce72b, 0x40724417, 0xa552f77c, 0x132fa9ed, 0xa5c84ed0,
13881 0xf2aef952, 0x7a99dcbd, 0xfe8a149b, 0x7189ce8d, 0x0ec205c0, 0x67b9d72d,
13882 0x673e3f21, 0xefa30fb0, 0x474c5d14, 0x6674317b, 0x475c00f2, 0x0e60bbf7,
13883 0x0233db41, 0x805067cf, 0x4c2b9e23, 0xd44c3744, 0x4818bfed, 0xdf04b9f6,
13884 0x62fa3a41, 0xda3b698d, 0x2dad7673, 0xd1d20972, 0x47b240f2, 0xc1dc80ce,
13885 0x0494cf71, 0xfbce1d13, 0xc8fbf175, 0xb4f2676f, 0x5a679f44, 0xe9f7bdb8,
13886 0x85add94a, 0xbccd77f5, 0xf4224cf6, 0x45f55aeb, 0xdb2856d6, 0x1a35fcd7,
13887 0x35bcd1f5, 0xdfb0d3a5, 0xd355a2bc, 0xe2374e11, 0x3a2579f3, 0x6e1cccc1,
13888 0xb76ce353, 0x6742be23, 0x3941cb5e, 0xe4b8b83d, 0x17c18c39, 0xc4efd9c7,
13889 0xdb6997f5, 0x651e10cb, 0x8d167c6f, 0xf37773f6, 0xa15b7bcb, 0x27d9336c,
13890 0x35b2bf60, 0xc3acc577, 0x55ff84c1, 0x017c06a6, 0x671e7d1d, 0xe5f7c1cf,
13891 0xd889dc93, 0x2da692ef, 0x56c6e107, 0x7ddd9add, 0x80fea5b1, 0x40607e84,
13892 0xb295194b, 0xd1e71d33, 0xa483b929, 0xd8238438, 0x4beeb00f, 0x70507766,
13893 0xc98d452a, 0xe9de289e, 0x5a9a3ebb, 0x403b8898, 0x6c9762bf, 0x32dd2033,
13894 0xebe716a7, 0x9e18bedf, 0x7c5bbb53, 0xfc5cc45e, 0x93d37079, 0xab7d2077,
13895 0x37f71b99, 0xd84aee2e, 0xbcbff88e, 0x6f44e5ff, 0xbcbfd83f, 0xfd7cbe7e,
13896 0x00be9097, 0x89e0978e, 0x41abe906, 0x75ffe3e7, 0xfa248aed, 0xfd11ef82,
13897 0x724aed74, 0x8f92f26e, 0x307e425d, 0x066b2bab, 0x95cdbdd2, 0x22967685,
13898 0x95de982f, 0xb25bfe4e, 0x15fd1d2b, 0x3cb0de45, 0x773d2257, 0xfdb112ba,
13899 0x8d67f401, 0xed16ef9e, 0xc4ddaa8e, 0x550e8ee3, 0x6c47d606, 0xee32bac7,
13900 0xb497d6cd, 0x4f53eb55, 0x9fd6fa71, 0x95fcf210, 0x1f8ab457, 0x82bf0b2c,
13901 0x5a3c1459, 0x7046fdb8, 0x8156b3f9, 0x5951c3cb, 0xbf803718, 0xdcde6962,
13902 0xfb857e6f, 0xd94607cd, 0x2aae50a3, 0x6081f9fe, 0x5ea2a7a8, 0xea56f3e5,
13903 0xe7fc1c0a, 0x4bcfe6bd, 0xf7be30a3, 0x1f8f1c46, 0xbcb81955, 0xb97032aa,
13904 0x1594dab4, 0x34abef8e, 0xa2a6c760, 0xee2c72bf, 0x0e078d4b, 0x366d2ae7,
13905 0xf57dc110, 0xe9475ba5, 0x6d976f91, 0xa6f7a51b, 0x639daa8f, 0xde60598e,
13906 0xadaa7697, 0xb52a84b8, 0xd7b449f3, 0x2eca76aa, 0x7af7a307, 0x64bfb41b,
13907 0xdb02723c, 0xe3c6dd2d, 0x65ff4a16, 0xf96db35b, 0xb11ef35e, 0x69be17d3,
13908 0xc8fadf2e, 0x51fadf26, 0xfd0645b4, 0xb946fdeb, 0x8e63eb7d, 0x7fcfd6f9,
13909 0x242cf0f8, 0xf1d902c3, 0xe3f68ca4, 0xa18e735f, 0xc0eaf93e, 0xf78a20c1,
13910 0x8adf967c, 0xadb2f176, 0x3c0770be, 0x3827684a, 0x77a44876, 0xfcfe9d0b,
13911 0x031f3fd2, 0x5f389446, 0x14dd37b2, 0x3aab4731, 0x9df6fae6, 0x86cb35cc,
13912 0x7f95a571, 0x8c72fb8a, 0x5ddbdc67, 0x0fe8b45b, 0x46f77ff9, 0x368ccb7c,
13913 0x1637c60b, 0x7eefe58e, 0xfb2272b4, 0x7cdbc702, 0x71e90732, 0xd224afe1,
13914 0x25f70bc3, 0xd3748dbd, 0x14ce77b1, 0x12e5672a, 0xcbb8943c, 0x6dc916b2,
13915 0x2c79ba82, 0x650fdbeb, 0x6b45ef30, 0xa1f13e75, 0xf3becdfc, 0xfbe35a58,
13916 0xe1d3597e, 0x6bbee1bf, 0xda45fe81, 0xa6d82ea7, 0x396b8bf3, 0xbd3b42df,
13917 0x7e462be8, 0xf7dd5178, 0x5ee2feba, 0x143ac44b, 0xee3990fb, 0x6e4eb864,
13918 0x8edf8202, 0x3d7207ff, 0xc4d76cc4, 0x8dd8f20f, 0x95a9aa3f, 0xcca57e11,
13919 0x8e3988fe, 0x207751fc, 0x0ea967cc, 0xa4d1b1ec, 0x577d6987, 0x78a00eb7,
13920 0x06673c07, 0xb5957e78, 0xbe7ea165, 0xf2b268da, 0x965b5938, 0xa0cbea19,
13921 0x602bf08e, 0x12a704d5, 0xa732cb94, 0xddb79b1b, 0xb3adf4e0, 0x97b76e6a,
13922 0x1187dda8, 0x9dacc51e, 0xbd1e21fa, 0xbac095db, 0x3b41093e, 0xb33fafc4,
13923 0xdcbc9c52, 0x95fc25a8, 0xf3af7d37, 0x0bf8af7e, 0xc4a2ff8a, 0xf4577ee1,
13924 0xb7d20060, 0x3587d846, 0x5b7b9d1b, 0x94eb3d61, 0x0316deb8, 0x6b07a7c9,
13925 0x7b07bcb9, 0x59d71130, 0xd68525b3, 0x8b64a0fd, 0xf6b68759, 0x7fd13d0c,
13926 0xd3d8304d, 0x924764a1, 0x237600bd, 0x733dadd9, 0x12edceb4, 0x372e8fda,
13927 0x4f35c1da, 0xca06f8f3, 0x9f6bb249, 0x527d9030, 0x27db8333, 0xa9c25b35,
13928 0xca705fff, 0xf2576891, 0x913cd4f9, 0x995dedc6, 0x8ce163f7, 0x65f607e6,
13929 0x5e6bdea2, 0xb2ff5d8a, 0xf1113ed9, 0x26b7acad, 0xfb84c7b8, 0xe060ac1d,
13930 0x7af9e92d, 0x007abfa1, 0xff07180e, 0xc56bca52, 0xdda5097d, 0x1f5cf17d,
13931 0xedb04d64, 0x5e28ed10, 0xb19aaf9e, 0xa79827e9, 0x52ca8cf0, 0x7f05e315,
13932 0xd7112d9b, 0xc316e5ff, 0x99d3c468, 0x679e5c51, 0x05f1e04d, 0xdb6c5bf0,
13933 0x5e22ff71, 0xfd7713e5, 0x614ef8a9, 0xf5e685bc, 0x2f8f3665, 0x28f2329a,
13934 0xdab6038e, 0xf5f6fe82, 0xbef9e30b, 0xef36be68, 0x99fb8ff8, 0x3617028f,
13935 0x5f17fb89, 0xbe91243e, 0x9a24f584, 0x1bf59ea1, 0xbe7fc503, 0xc1477a14,
13936 0x2651d007, 0xc72161e9, 0xc67e90c2, 0x19e7e878, 0xa40e1741, 0xfd378b0b,
13937 0x83c7d2f8, 0x09ecff02, 0x04d69f6e, 0x13cd7af3, 0x9fa03729, 0x650ffdfe,
13938 0xfcb535bd, 0x01dfbfbd, 0xde36b074, 0x74fe9e0b, 0x4cced4c0, 0x7f35fdef,
13939 0x8d96c83a, 0x57e728c9, 0xb4560148, 0xfe0857c7, 0x1184b158, 0x0ab1463d,
13940 0x8235f909, 0x008f29b9, 0xc70181e4, 0xc00f71fb, 0x7f0f8bdc, 0xbccf4d72,
13941 0x1678dff5, 0xa89f53ec, 0x9f69f48f, 0x79f18e6d, 0x8a44577f, 0x96c9fbcf,
13942 0xa9f53e51, 0xb4fbb7c9, 0xde3adbbf, 0xd8cf7ea7, 0x67ed3ec9, 0xd4f866d8,
13943 0xc6accc6d, 0xee54b7f9, 0xcde0fb24, 0x97dc574a, 0x65c3d709, 0x3ec8ee9c,
13944 0xa6b1958b, 0xaa6707ba, 0x0dc61e81, 0x0622b238, 0xede387ea, 0xe4751ebc,
13945 0xb1998c6a, 0xf217e2b7, 0x572388fa, 0x347ea163, 0xdfaf117e, 0x7f5fc8c1,
13946 0x4cf17e27, 0x15c52a47, 0x667e218f, 0x8a38ab5d, 0xab47e16e, 0x41892e67,
13947 0x24c92f1e, 0x67ecae39, 0x3f6313dc, 0xbcacfc84, 0x8d9fda57, 0xafbbfde7,
13948 0x7ddff970, 0x2377cb85, 0xfe83291a, 0x32fc12fd, 0x0e04fefa, 0x6f413622,
13949 0xa62ffda4, 0x8bea5cd7, 0x94fc8343, 0x3c618c6c, 0xf012a5af, 0xd370809d,
13950 0x34aee953, 0x32a47953, 0x2bb7ca82, 0xe01f2c2d, 0x4c995ada, 0x2b4ab1e5,
13951 0x395e3f3d, 0x2bf7ca96, 0xa89e546d, 0xadb2a5cc, 0x094a8f32, 0x2879a98c,
13952 0x3758763f, 0x0e2e1068, 0xbd39f075, 0xc6e52f27, 0xcecd4c72, 0xc685f829,
13953 0x5f6c186f, 0x31dd93c4, 0x71714cc4, 0xd35bbcf1, 0x73d222f3, 0xc16615d5,
13954 0xa6c3b87c, 0x9fb416d3, 0x44f532ab, 0x9b4f52ef, 0xb8ebe505, 0xbaaf5e0c,
13955 0x675166d2, 0xfdea3af0, 0x28d760ee, 0xa5550bd4, 0x189aeb46, 0x448eef7c,
13956 0xa157197e, 0x387fa2b5, 0x3e67a7a9, 0xa338f1f2, 0xf47a82d6, 0x2df5a9b0,
13957 0x73ca3df1, 0xdcc2bba9, 0x3457dc2a, 0xe2cc59b4, 0x7c0e383b, 0xc1f50637,
13958 0xbbe187b8, 0xed056e34, 0x679b8d07, 0xe4aefbec, 0x0ffd5df7, 0xe4a2777f,
13959 0x5ef8ddf5, 0xff3a6ef8, 0xbbe7c5ae, 0xe5ec996e, 0x0fb26e2b, 0x11ad83ba,
13960 0xfa955f28, 0x4a9f7c24, 0x33d24271, 0x196e2ce3, 0xe887eff7, 0x070d3cb8,
13961 0xa5e0d2f3, 0x6278956f, 0x675f2f5d, 0x08bba557, 0xb0926af9, 0x59692657,
13962 0xa993c232, 0x98fe2802, 0x1ad77f2d, 0xcde5f505, 0x9dcc28d2, 0xdbcba498,
13963 0x9aae7e46, 0xca161dcb, 0xb75332f5, 0xed0cbe15, 0x5945854e, 0x486adf31,
13964 0x0f1601c4, 0x3cbb3872, 0xfaf51537, 0xd4df9129, 0x484f641c, 0x9bdc7980,
13965 0x254a720a, 0xd9f71988, 0xde490372, 0xca4a1f77, 0xa67f7b44, 0x019fb2ce,
13966 0x3c26a71f, 0x720d5333, 0x4b00e671, 0xfac664a6, 0xb70f5e36, 0xbde097ec,
13967 0x73333d99, 0xc1ffedd2, 0x4934fafe, 0x381f97ed, 0xadf80136, 0xc8b2f734,
13968 0xfb21ec57, 0xe498c7f6, 0x77e28834, 0x9ec7a46e, 0x03d226c9, 0x8e5b8f18,
13969 0x92d53bf2, 0x35a2ed89, 0xff08413d, 0x94d4efee, 0x832d023f, 0xe38af3ee,
13970 0xf3c2d8bc, 0xe3f9fc4a, 0xabd70272, 0x9f3cf1e5, 0xaf422ca9, 0x4ae5b2a7,
13971 0x8f7ca30e, 0x3ff478bc, 0x57edeac1, 0x0277febf, 0x598e1fdf, 0x47f1e5af,
13972 0x6530a114, 0xea53005b, 0xa96bcc0e, 0x3140247d, 0x4e006d46, 0x547ec5a6,
13973 0x24cdfa6f, 0x1b7b4fb5, 0x67bcf7b6, 0xd29f0436, 0xcf7ea4bf, 0x8bc6d66f,
13974 0x2cbd21ef, 0x825c4e65, 0x4da9febf, 0x0bfc510c, 0xa10bf3c2, 0xe38bf206,
13975 0xa057a065, 0x1740a8cf, 0x0ceb33c5, 0xdcc17e9c, 0xc54eb2a0, 0xc0036bdf,
13976 0x50fa85fe, 0x9a3ee3a8, 0x22bed13b, 0x67f51071, 0xef2fec66, 0x2291fea5,
13977 0x1f794e6f, 0x1979518e, 0x0cdae9f3, 0x55938e58, 0x4e4dc2fd, 0xc46bff1c,
13978 0x83a55777, 0x2fd2f59d, 0x2b41815d, 0x8654f1bd, 0xfdde8dfd, 0xa53f5026,
13979 0xfdd8297f, 0x9c920767, 0x8d297a26, 0x2b3e5157, 0x4b6fcdf8, 0x36b0d768,
13980 0xa561ea2d, 0xab9069df, 0x410fbdf8, 0x09f962ce, 0xc0b3d7c8, 0x9ca97f9b,
13981 0x95a7e54d, 0xa67e7a76, 0xf6ca80b2, 0xfe7a0aca, 0x2a4ae579, 0x6535cd67,
13982 0x37949f20, 0xbd6766ad, 0xa5d4bae8, 0x4bef7bb1, 0x3fdf1e9e, 0xe04aecbd,
13983 0x98e9dd76, 0x95bbdffe, 0xbc7277f7, 0x817d8375, 0xdfd024f6, 0x8dc8735a,
13984 0x136e8ced, 0x377abfdf, 0x7773d385, 0x25d7af24, 0x536ea868, 0xffd8adb1,
13985 0xd12d14dd, 0xc6448aeb, 0x2c7889db, 0xdf8d1fd0, 0x3e54e707, 0x19ced28e,
13986 0x2fedcaaf, 0xf225984f, 0xe89f4476, 0xc63d202f, 0x9967d178, 0x9fd3e885,
13987 0x39136a2e, 0x38ebc4df, 0x2ea145dd, 0x708c7dc2, 0x0a731383, 0xdc36be60,
13988 0x3893af57, 0x9f475e3d, 0x5d9fee2a, 0x0e309f47, 0x5ce809c1, 0x7ec7f282,
13989 0xef94a3f4, 0x0b6fbe0a, 0xe08cfd33, 0xa331a2dc, 0x0cb1f8be, 0xaafec580,
13990 0x0f9813de, 0xb266151e, 0xf6489ee0, 0xfe8ac6e3, 0x123fc7e4, 0x6ffd7db8,
13991 0x1f8fbfaf, 0xdd7fd77d, 0xd07ec5ba, 0xe49baead, 0xa44bca09, 0xc3e47e9f,
13992 0x3e4504a5, 0x1391fa70, 0x3f50e76d, 0x35064b74, 0x0dbbb3c6, 0x83ae2e9c,
13993 0x4fa70a5b, 0x056a3e85, 0xbae1447d, 0xe9eb3ce2, 0xdf807f9b, 0xca3196fa,
13994 0xa3c7f0eb, 0xd6bc5722, 0x2f04f7f5, 0xd818c279, 0x487fd017, 0x09f69189,
13995 0x099a2457, 0xce83dd7e, 0x6f02dfcf, 0xe27a159f, 0xa7df1579, 0xdf76e450,
13996 0x305e4973, 0x9e47d523, 0x7a33b433, 0xbf88e90e, 0xf0562adc, 0xf851fa1a,
13997 0x70bf2f29, 0xef53c0ac, 0xee154cec, 0x6b7d75bf, 0xcd1e5074, 0x68339ee0,
13998 0x056d7447, 0x7ffc8003, 0xf40934db, 0x878c12d9, 0xafbe3058, 0x8be8fda7,
13999 0x24b20f60, 0x72bae768, 0xf298ed06, 0x07a664e7, 0x7dcfc9d0, 0x65e90b33,
14000 0x998d21e9, 0x4fad9aec, 0x3b7a431d, 0x505928d7, 0xc23577df, 0xb39f71b2,
14001 0x4034e4c6, 0x63a81cfb, 0x653b65fb, 0x03522527, 0x14fe907b, 0x286b3bdf,
14002 0x777b458b, 0xa33f73e2, 0xb5a5f8fd, 0x71870b12, 0xa2badadf, 0xe7ea1235,
14003 0xf9fcf1b6, 0x7fcf032a, 0x6b3791cf, 0xb47c6307, 0x312f3f96, 0x7bfe50e6,
14004 0x75662ed1, 0xaf65bc63, 0xa5f3fc89, 0x1579be35, 0xeb7cdb05, 0x5cbe2285,
14005 0xbcfbe754, 0x4f37c1a4, 0xc8a24c63, 0xa36148c3, 0x135a5e28, 0x22807642,
14006 0x77e46f4f, 0x397396d9, 0x61d7d8c9, 0x0f95ef18, 0xb9fd137d, 0x8867d791,
14007 0x2fd4077a, 0xa2f1c37f, 0xc94ca5c0, 0x1964882b, 0x23cc0cae, 0x3f719834,
14008 0x8bf9acaa, 0x73f98620, 0x89d3ed01, 0x29975f3f, 0x93636adf, 0xa569fb4c,
14009 0x3097862d, 0xff6cb0cf, 0x84c5ad49, 0xec887f70, 0x6398bb80, 0x6e8bfa3d,
14010 0x6fe44a95, 0x8ddc51b7, 0x52967ad9, 0x60d9bb7c, 0xf65afd46, 0x73adc7fa,
14011 0x625fbeb1, 0xd0e3c406, 0xa593a276, 0x5fb4c9cf, 0xc9f2d0cd, 0x8c89d0f2,
14012 0xbb3c4578, 0xcf3ed006, 0xe23bc432, 0xe78ef019, 0x34e7e41b, 0xbba5f784,
14013 0xb55f7a64, 0xed8b4ab5, 0x7e3939cf, 0xc8e7bc15, 0x45cf08ab, 0x4e7c702f,
14014 0x99feae7c, 0x5d83a400, 0xdf73b21a, 0x79837e82, 0xd03a1f3f, 0x77e3e21e,
14015 0xdf144bd5, 0x6683a3ea, 0xe01d1f5d, 0x07466f3c, 0x67a49fc0, 0x0607466f,
14016 0x4fe41794, 0x8a1a3b8f, 0xf8cfedf6, 0x9db8947c, 0x1f9b9712, 0x10fa59d2,
14017 0xd8884d34, 0x1b2cf647, 0x08955f60, 0xe4cce672, 0x74dc280f, 0x51eeca6a,
14018 0xff034f94, 0xbf9461f4, 0xfb7cf047, 0x444b7fe7, 0x331dd079, 0x18c1db63,
14019 0xae0767c2, 0x90383ba7, 0x923dd3eb, 0x3ae7a253, 0x93be0eb7, 0xf915720d,
14020 0xa3a9bd92, 0xa0f743f8, 0x893e1e07, 0x184f68fb, 0xc92e88ad, 0xe2bafdc6,
14021 0xc13e7796, 0xcc6b27f8, 0x7df8f9b6, 0x462b2fc2, 0x37df10bf, 0xb5e85f80,
14022 0x3f9928df, 0x4bbf7ea0, 0xcb75a58c, 0xf256eb2a, 0x0598eadf, 0xe5eb95ed,
14023 0xaff9233f, 0x686eafc4, 0x01e9f99f, 0x76e7fc8f, 0xf10c7319, 0xe5c0b73b,
14024 0xf71132d3, 0x71c8fa3d, 0x675c40f5, 0x53373f1d, 0x297202d8, 0xf8a5ce94,
14025 0xd13297c8, 0x19d23cfe, 0x472bf1c0, 0xec9501c5, 0x9d3e472d, 0xec94e384,
14026 0x2194e3e2, 0x981c20fd, 0xdc0099fb, 0x28697027, 0x84c4591e, 0x5932695c,
14027 0xe47e96dd, 0x7aed5d48, 0xe9fd7f34, 0x37ec18a7, 0x1d3f845c, 0xb6fa3595,
14028 0x97ca03fb, 0xd25f2411, 0x077f47be, 0x23d32369, 0xd4e5b247, 0xf5afe801,
14029 0xe400cb32, 0xb9e91be3, 0xdac0ada4, 0x38a6e35e, 0xb3ed4cf5, 0xa9f6615f,
14030 0x7c22b9a7, 0xb26c8fda, 0xe51fbcf8, 0x3f79f64e, 0xa7d598e6, 0xd636d99e,
14031 0x9f6dfda7, 0xb7ea7cd8, 0xb4fae7b7, 0x3cabe3bf, 0x2a6f7a9f, 0xf607e7ac,
14032 0x908aeeef, 0xb64fda7c, 0x07c67c18, 0x99f04e0d, 0xf3ec1c9a, 0xe1c8d7bc,
14033 0xef71a374, 0xab8efab6, 0x8cf7b9f8, 0x867f1df5, 0x5bdc77cd, 0xd00ec3c5,
14034 0x4d106a9b, 0x628f413b, 0xc0254af9, 0x86f1ec1d, 0xbfaa08ca, 0xd2a1695a,
14035 0xcf4c9955, 0x52b4ab5f, 0x2c72b1bd, 0x7d800fd5, 0xb026f58f, 0x1d7cb1f7,
14036 0x7e7c7cec, 0x8ab57833, 0xdf131eef, 0xcbbe2e3d, 0x076e16d8, 0xef2e04dc,
14037 0x4427fe8b, 0xafec36ff, 0x6961d0f1, 0x1aeaa66e, 0x90f8edf0, 0x2f8c5a0b,
14038 0xe7b796d8, 0xf3df9fa0, 0x03b6ccae, 0xf3bb305f, 0xea286558, 0x1f3c81a9,
14039 0x3de7af21, 0xed97178c, 0xfee3338f, 0x3fa6c6c7, 0x5df7c09d, 0x33c5328d,
14040 0x117d348e, 0xba5ce384, 0x503ecc06, 0x97a837e8, 0xfaa24dfc, 0x798f7826,
14041 0x82f793f8, 0xcb7a4b61, 0x52eb7a45, 0xd27752bc, 0x86bc8df9, 0xda76dabd,
14042 0xef4bdc57, 0xf5be05df, 0xd6b3bf79, 0xdb19bde7, 0xdab67ee3, 0xc5f77e49,
14043 0x373c6526, 0x97892fb5, 0xc5d23ce8, 0xc7ad6f9d, 0xbdd2be7c, 0x3ee2070b,
14044 0xc9c37160, 0x003fc5b0, 0x7607cbff, 0x2f5ca2a7, 0xf9c5966d, 0x695e3e23,
14045 0x891e72b3, 0x7e24bfcf, 0xca084e6f, 0x218906ed, 0x6ab12e7a, 0x6e2a8fca,
14046 0x39412faa, 0x573c9c5a, 0x9721f143, 0x3c01e22c, 0xccc4b0df, 0xbae67db8,
14047 0x35e7841a, 0x3a3ae0ff, 0xba85f31d, 0xc20ade5b, 0xf9e376ef, 0xdefc2f13,
14048 0xdcedc493, 0xdfb8927b, 0x2df1a974, 0xd1b93f3a, 0xbb8716f5, 0x3feb4dda,
14049 0x50ddea22, 0x649bbc12, 0x35e17f5a, 0x8ca0f099, 0x4c9260f7, 0x4a6e4de3,
14050 0x4ebae130, 0xf2f7f8b9, 0x79fc2c93, 0x9c7cc2fc, 0x3988f1ff, 0x95d93299,
14051 0x3ddf2e3c, 0xca3d6a7c, 0xe80fcc51, 0x047b0fcf, 0xb5f985c7, 0x77c63c8a,
14052 0x0eb5f7e3, 0xcf1fb806, 0x748a381d, 0x274fe280, 0x473dfb71, 0x3d478f6b,
14053 0xa168ca71, 0xdc9af838, 0xf7e21338, 0x3cf89608, 0x57da25f7, 0xdfe46a28,
14054 0x0b6e653b, 0xd53bba42, 0x3b464638, 0x40af1946, 0xbe8fb77c, 0x20e6f0fb,
14055 0x6b38153c, 0x078e388d, 0x7e79fc7f, 0x71e69992, 0x167279dc, 0x92a74bda,
14056 0x68cec903, 0xfcfdf2d5, 0xef6e06e2, 0xaa896a9e, 0x5bf6bd95, 0xba3e05f2,
14057 0xd7845593, 0x688d26ae, 0xf99eb737, 0x7c70d3b4, 0xc7cef9d5, 0x1278ecec,
14058 0x1792eced, 0x54933a64, 0xc308a9a2, 0xe6df9ff5, 0x0102bf3b, 0x3b8d12e7,
14059 0x5e8bcc2c, 0xf8fb9a4b, 0xde7448c6, 0x8589f0ac, 0xf1e0a9f0, 0xc73f3254,
14060 0x9f822a72, 0x5bd92a83, 0xd1ed744f, 0x19ae3cf7, 0xbf3c5ff5, 0xae7e66f6,
14061 0xf9780f62, 0x3cfd0c49, 0xa65c6e4d, 0xf7a3d62a, 0xbf6d137b, 0xfe841a4b,
14062 0x85f91e53, 0x8a26ec40, 0x3c7da08b, 0xa7efe500, 0x7b77e0cf, 0xd879f91b,
14063 0x11737d52, 0x5af5fbee, 0xbe604181, 0x4e34dbbd, 0xd118cfe1, 0xec2a5d4e,
14064 0x7b16f3d4, 0xa3fb8c96, 0xaeb455ab, 0x89d90692, 0x425d98f9, 0x1bde5dde,
14065 0x69d20f73, 0x8cd931c9, 0x5744cdfe, 0x65c7afcc, 0xfb26de90, 0xedc5ccae,
14066 0x129db2dc, 0x7d8ab5d9, 0x8bec2a51, 0x3d8ec273, 0xdb87bab7, 0xf62487b7,
14067 0xcec78c54, 0x45761528, 0x3d79bca9, 0x9ffb2be6, 0x396c2daf, 0xfd89e74c,
14068 0xef16d5cf, 0xba97adf4, 0xbf8aeb7c, 0x9f524ef7, 0xfe82927f, 0x94a7d809,
14069 0xc0a9f12f, 0xacafe2a7, 0x2386b348, 0x5b546fbf, 0x037128a6, 0xa1f95784,
14070 0x6f38857d, 0x95804967, 0x6f9587fc, 0xbfbb5c10, 0x77497ee6, 0x77f5a304,
14071 0xeedf0e33, 0xe5df4e26, 0xc7a9c91a, 0x7023a8fe, 0x5ce4bd3c, 0xa3a8768d,
14072 0x12e48837, 0xf7c1e1e6, 0xfee1cf96, 0xa3630da7, 0x855a9530, 0x29fd140f,
14073 0xa9decdce, 0xbd83976e, 0x2495c3e4, 0x124e776e, 0x4c2b48f9, 0x835fd256,
14074 0xc1ebb9c5, 0x0f6f6e7a, 0x53573b56, 0x6631fe3c, 0xf2714359, 0x4e90a303,
14075 0xf14eae30, 0x123d55ff, 0xeb1fc3c5, 0x063f9091, 0x7911ad9b, 0xf849f55e,
14076 0x0763d53e, 0x48f6330c, 0xc7ba9df8, 0xd73af894, 0x66d433ef, 0x894fce0d,
14077 0x87fb293b, 0x7394fcca, 0xf3e7ff08, 0x8cfcc333, 0xbe01f99e, 0xabff6007,
14078 0x0fb25619, 0xe72867a2, 0x1e482afd, 0x04bcf028, 0x70093ef4, 0xa41d3185,
14079 0x876d929b, 0x40fe7873, 0xcbdf9d1b, 0xc8ebe209, 0x39e3f911, 0x941cbc01,
14080 0x2b35f1cc, 0x9e8bc799, 0x3722a510, 0x85b649df, 0x2fb94325, 0x39322f39,
14081 0x62ce73d3, 0x9cfc07f9, 0x87bcbf85, 0x574f44e7, 0xee510f81, 0x3242b4fd,
14082 0x63d8fbc7, 0xf9cabf9c, 0x2a3e3ea3, 0xe225e0fe, 0xb5b0e613, 0x9e618725,
14083 0x05efe702, 0x78e60d2b, 0x1728be2f, 0xc5a6207e, 0x7297fee2, 0x5cc0be4e,
14084 0xec40e748, 0xe8ccc32b, 0x97cb9597, 0xafff5e28, 0x93795df2, 0xe06ddd6f,
14085 0x4936eff4, 0x9edcffe4, 0x13cf67dc, 0xfe0b463f, 0xb44bb5a8, 0x9dfb5c2f,
14086 0xe6dbc79a, 0xbb5f1449, 0x7cf21e1f, 0x60aed17a, 0xdd9be53c, 0x37da550f,
14087 0xfb1509ab, 0x9fb4a1d6, 0xf7589f77, 0xe2df22fd, 0x8315c6a8, 0xa5a3a0f1,
14088 0x3f8e2b7a, 0x7f68b987, 0xa36b1e7d, 0xd96074f2, 0xee0d377e, 0xfcfe8a18,
14089 0xc51d76c7, 0x6ed76aa1, 0x4f5ca137, 0xb8cd6b67, 0xd8a006cf, 0x5b98fdf9,
14090 0xf2538fdf, 0x0e2ec189, 0xfc04fa47, 0x7ffc46cf, 0x1889b805, 0xe2ff7d7d,
14091 0x3e53f68f, 0xfbc3e752, 0xd0c03d66, 0xff21eaaf, 0xb562a8a8, 0x1c4df686,
14092 0xcb392dac, 0xef055783, 0xf0fade0a, 0x1f16616a, 0x869ac2bc, 0x4be49c20,
14093 0xfd2e4833, 0x77a8664e, 0x0557866f, 0xf8113fee, 0xe5ccd659, 0x15be3f97,
14094 0xe7803c3c, 0xdf48e2a3, 0x313c236e, 0x7f4bc91d, 0xbe19b87a, 0xe1e73080,
14095 0x3aa189ab, 0x54a32ff2, 0x2d469e5c, 0x38be2895, 0xb50fd997, 0xf02b3943,
14096 0xbbd10d53, 0x813cdbc0, 0xf3998fb7, 0xff98e4ee, 0x93bdbc3d, 0x3c9d579c,
14097 0xf5be7ae8, 0xf11bd3e7, 0xfac58965, 0x3a5f4547, 0x1fa3f219, 0x6bf1fb3f,
14098 0xf0ad1e1f, 0xda3c2f3f, 0x5f110657, 0x6e5be1f6, 0x88bd35b8, 0xaa1c607f,
14099 0x716bdf89, 0x60957e53, 0x57cf8021, 0xa6f57d93, 0x2e053782, 0x9deb8a37,
14100 0xc23b72d6, 0xfb4c88f1, 0xee499f98, 0x639466a3, 0xfce8a729, 0xb3fed29b,
14101 0x1f436dd5, 0x1b3e7182, 0x5ad3cbcf, 0xd4a91f9e, 0x3e3c016d, 0xcea459f8,
14102 0x4cfdeb81, 0xfa80994a, 0xbfe933e2, 0xb87af3a6, 0x39f582d6, 0x50cc13e1,
14103 0xe251ad3f, 0x7c446b89, 0x67e549c0, 0x449b6e73, 0x36f624ed, 0x3f9f8ef3,
14104 0x7cfc512a, 0x9c728801, 0x6784cc5f, 0xfeaf3173, 0x46e3cfcc, 0x72df3ed1,
14105 0x1f50f1df, 0x921c50c7, 0x5e778bfb, 0xf42cd1eb, 0x7a7d3bd2, 0xfe15d270,
14106 0xce933f3c, 0xd808161b, 0xb85242da, 0xe7e4ec7f, 0xd33d1536, 0xd19f6c7b,
14107 0x417a4e3b, 0xeafb95c4, 0x7b444f29, 0x3bc3a9eb, 0xe388957e, 0xe91d6814,
14108 0xabfb7e78, 0xd1a3e7da, 0xf1d8289e, 0xb7d92278, 0xa226363b, 0xfdb0529f,
14109 0xaa368957, 0x4fc9da07, 0x7775f352, 0xa5fdb9ee, 0xe77a5e4d, 0x6fdce1d1,
14110 0x9c3fa799, 0x94ee768d, 0x61d79711, 0xe7e13e3c, 0xf387dd12, 0x0eb6d653,
14111 0x64fcdff5, 0x46acef4e, 0xe199724f, 0x73c02df9, 0x75ddca7d, 0x93c7a7c8,
14112 0x43e4d0bf, 0x9a8a5d3b, 0x399f33e0, 0x7ee38737, 0x5cc906f6, 0x0fdbbccf,
14113 0x85cafda5, 0x446d256b, 0xe0b7ea28, 0xea3fe851, 0x1e698252, 0x6a8c368b,
14114 0x57f3e7c5, 0x7453e7f1, 0x3853c6ce, 0xca5ab3ce, 0x10f90237, 0xafc79deb,
14115 0xf1e7e14b, 0xc8966c17, 0x93be57ae, 0xad584cf0, 0x29753af7, 0xd4672f42,
14116 0xce51dc91, 0x755b4e09, 0x1808edf2, 0xbb6a9ff7, 0x39c60529, 0x78b9f4f1,
14117 0x149f3c37, 0xfd152172, 0xfdad049b, 0xeeb885b7, 0x83ca3aed, 0x928f48cb,
14118 0xe8fda1c3, 0x853fc787, 0x0b5582e5, 0xf2885b7f, 0x147eab71, 0xf3e6174f,
14119 0x55592e5b, 0xaadf3f28, 0xc211607d, 0xf5a7abed, 0xaf2f9764, 0xfd670a4d,
14120 0xbe528ff0, 0x8dc7f80c, 0x7a955d82, 0x9a57772a, 0x9eda3ce9, 0xffaa08ca,
14121 0x2542d2be, 0x6be9cd9b, 0x8dcb99b9, 0xe6378d1b, 0x80b3205a, 0xc1b19abd,
14122 0x70632cc0, 0x9c96ce5f, 0x18487002, 0xa37dba5e, 0xa56e1758, 0x4cc4728c,
14123 0x6c643844, 0x4d15a87c, 0xee14d0da, 0x6a77bd67, 0xedf23443, 0x2f1d55b2,
14124 0x537ae216, 0x7f6146f2, 0x142bb6fd, 0xf9ab7837, 0xef08f9f1, 0xbe3aed82,
14125 0xafeeb13e, 0xff0c4e9e, 0x78ef8c2d, 0x7c7e4357, 0x178eb6f9, 0x78b94237,
14126 0x6f5a43f3, 0xf5d5bf7a, 0xfbe14c8e, 0xabe3379d, 0x5fe1c11b, 0x455fabe7,
14127 0x7f6cff13, 0xf9e1ee9c, 0x7caaf977, 0xdf826ad5, 0xd9bc94ba, 0x695f5f48,
14128 0x4fc8d11c, 0x98fca55f, 0x4871dce8, 0xf22bf822, 0x4b3fe955, 0xe558bfc0,
14129 0xc62e3cda, 0x61bf5f23, 0xc3df0419, 0xd113e7cd, 0x69a6fdae, 0xfbae0fce,
14130 0xb7bf2540, 0xebe009a5, 0x52882f7d, 0x71ed6966, 0x965f5856, 0xffe0c738,
14131 0x12a291de, 0x6fdf2cf6, 0x57927fc7, 0x17e8077e, 0x4f9800c7, 0x0ee48b49,
14132 0xe9ae3f40, 0x20ea0bae, 0xfb1233d4, 0xc91e27dc, 0x7a5ee7d8, 0xbdf346f6,
14133 0xe3865959, 0xeee47824, 0x7ca89f6d, 0xbdb963ee, 0x7ee7c03d, 0x03ff3e93,
14134 0x3f69699e, 0x3956b227, 0x4c7980bf, 0x7429cd5d, 0x9682e25e, 0x00ebb1e3,
14135 0x3e3c39d8, 0x7baf64c3, 0x77342e22, 0xf59ca3a6, 0xebd96f5f, 0x251f449d,
14136 0x215f8f4d, 0xf269b63f, 0xcdfa7505, 0x47787fd7, 0x71dbdd27, 0x859ed341,
14137 0xb69754fe, 0x50f11d3d, 0xe79706f6, 0x941c2aff, 0x601b85e7, 0x65e7c021,
14138 0x24e89e92, 0x7144be5b, 0x3c63ae81, 0xfcd6502e, 0xded3c912, 0x29971e16,
14139 0x84e5b557, 0xa2a31c63, 0x59e515a3, 0x93f7046f, 0x09bdc4ca, 0x1e84e2e3,
14140 0xe344f754, 0xd8b70e79, 0x3bfc5627, 0xf90187bc, 0x2ae55cb5, 0xf4a5fca1,
14141 0x2dfb8640, 0xe19f9117, 0x3195fcf9, 0xbfce91eb, 0x8d1a0e72, 0xf4bdf1f2,
14142 0x1c5197bf, 0x66810fef, 0xd911ec99, 0x6fbc2f27, 0x27994e1d, 0xaec530c8,
14143 0x8bc9f409, 0xee5ad72e, 0x38f67b21, 0x1f2b7fdf, 0xbd89f9ce, 0x74a9f9ce,
14144 0x846d61ed, 0x820d78d7, 0x6efb149f, 0x4efe1fca, 0xd138797c, 0x92f91c76,
14145 0x78e215ce, 0x929c0311, 0x7965da24, 0x2d8d1bf6, 0x95cfafc2, 0x93797de9,
14146 0x8e5f70cc, 0x2f289845, 0x53559720, 0xe614e57e, 0x339b471a, 0xf127f6ea,
14147 0x7fa99b5e, 0xfe60c790, 0xb441f816, 0x60139d7f, 0xa6fcc78f, 0xc0492ad3,
14148 0xc33195d5, 0x87e99f4b, 0x4e353d73, 0xf58f4896, 0x9d920644, 0xe9767932,
14149 0x69fb6f3c, 0x83b78ab4, 0x626ec871, 0xae7e1ece, 0xee93ddc6, 0xacc8ef7d,
14150 0x9056043f, 0x8cae645e, 0x89df5e59, 0xe6f5ce1c, 0x06ffdc55, 0xfb17293a,
14151 0x77f2d9ac, 0xbd3da0cf, 0x5fdf10fc, 0xf98aad3c, 0xe8b3f318, 0xe784b6dc,
14152 0x7939f9a3, 0xbc366766, 0x6d2baf67, 0x2a079d10, 0xcc3123df, 0xd66b2b73,
14153 0x5138c76d, 0x0c3da699, 0xd36379e9, 0xe7a45a47, 0x4d77dc72, 0x79abe7e3,
14154 0x724f5cdc, 0x48ccdcbc, 0x2536957f, 0xbbf18c7d, 0x8b5c63d2, 0x924faa96,
14155 0x1b728e7f, 0xb8dc57bf, 0x12f1fc97, 0xbc7f26e6, 0x6e97c1a4, 0x8ffa237a,
14156 0xb70e47df, 0x3233dcf8, 0x8fe72b79, 0x325ee259, 0x93b0e226, 0xbd6bc223,
14157 0x0a4531cf, 0xcee4d83c, 0x74c76875, 0xbc564ac7, 0xc03ba697, 0x23ed16b1,
14158 0x6bb72247, 0x9ddcdfba, 0x8be494b1, 0x34dee333, 0xdb8757bc, 0x6c3793b1,
14159 0xf35ecb51, 0xe3ee2c99, 0x05600eeb, 0xf6ef0807, 0x908f8821, 0xe1a8bca4,
14160 0x9e3ee883, 0x7c607713, 0xf27b9c48, 0x446fc75f, 0x38b8e85c, 0x7bcca9bf,
14161 0x9714546a, 0x7449cc67, 0x19ce2ad4, 0x4a367929, 0x1eb10aff, 0x3d077ec5,
14162 0xfb43fe1d, 0x934fb825, 0xf269f62f, 0xbe4d3ec5, 0x17c9a7d8, 0x62f934fb,
14163 0xec5f269f, 0x7d8be4d3, 0x4fb17c9a, 0x69f62f93, 0x0d3ec5f2, 0x54e2c3e5,
14164 0x11cdff31, 0xd1ea34fb, 0xc1b5e456, 0x10e9fa9e, 0xdf60fabf, 0x2443a7f6,
14165 0x8960fadf, 0x257c4fda, 0x118769f6, 0x2166a3e3, 0x547c789f, 0x2a79df39,
14166 0xe1193ed0, 0xfce79cac, 0x03a9f72a, 0x42934fc8, 0xd9bf90e6, 0xca26fe0b,
14167 0xf6e1caa3, 0xec776c3c, 0x2df8c4d8, 0x140d2724, 0xe0fd3ce7, 0x98739f08,
14168 0xacc793e3, 0xc6307bc5, 0x7e71251b, 0x9e647abc, 0x38c1ffe2, 0x66165b13,
14169 0x307cb9a8, 0x2d9cbda3, 0x77e3e497, 0xc61a4796, 0x24d61ca0, 0xf70ee7db,
14170 0x8339db92, 0x5da3c597, 0x7cb1aad4, 0xc75af18c, 0xbf3a1a07, 0x94f5c4ab,
14171 0x8d25ef76, 0x937ec42f, 0x8ed6e393, 0xfcf5f1c6, 0x969b38be, 0x6cfce035,
14172 0xee8940aa, 0x3516616e, 0xe1c283ca, 0x58266e9c, 0xd6ec7db8, 0x1821d45a,
14173 0x1f18098f, 0xad13798a, 0x04c7cf02, 0x3c0b8f9e, 0xa4d77ee3, 0x85dfbe04,
14174 0x6177ee25, 0xd58de4a9, 0x1f2de4a5, 0x27b4f24e, 0xc4ace11a, 0xe728a6fd,
14175 0xee8b98fc, 0xd0517c33, 0xbe70d26d, 0x7261f2cf, 0x09c3a3de, 0xb73a2e3f,
14176 0x69e22c59, 0x437f629d, 0xcfd2a759, 0xfbf19fd3, 0x0732465c, 0x83b367ee,
14177 0x08764f22, 0x9f5023d8, 0xe49c3079, 0x7a1e7290, 0x07ee18e6, 0xfce27db0,
14178 0x13258462, 0xc44aa3f9, 0xfc9cbb53, 0x48696d1c, 0x239e225b, 0xa57c12e8,
14179 0xd17395d4, 0x6ea1a3a5, 0x284b9cf4, 0x8896d99d, 0x24ba12e7, 0x0dce8a83,
14180 0x4fefe76f, 0x8d2bbe09, 0xf729e315, 0xd15de84e, 0x43ee8788, 0xbcf1a307,
14181 0x7ba326dd, 0x6efb9729, 0x2811de7e, 0x3a96f316, 0xcc19d725, 0xf7747dcf,
14182 0x1e63f71b, 0xf5c6a77d, 0xdb1fd622, 0xcc7ee87d, 0xf694edcf, 0xbf7b319e,
14183 0xc68ae41f, 0x7747ddfc, 0x83f7f0b7, 0x6c18bef6, 0x5e6baaf5, 0xb5ef833b,
14184 0x8fdd0e6b, 0x7553bcf9, 0x489563ce, 0x74e7bf2f, 0xffb3d865, 0xb8adc21c,
14185 0x13eddb99, 0xf4bfecf6, 0xfde5ea1a, 0x3fefda26, 0xe0863c38, 0xf2fcd55d,
14186 0xaeb3a466, 0xbfde3cbd, 0x17a3e1a9, 0x74ed417f, 0x54dc0d74, 0xc1832b9d,
14187 0x9eecd677, 0x1a9af34b, 0xeb1afae8, 0x46388d4f, 0x903a98f3, 0x11d6f3f3,
14188 0xe78fddef, 0xeff6ba01, 0x6ef90479, 0x683000ea, 0xf9bb3e71, 0x7da2a0f9,
14189 0xbfd09329, 0xcdb532ef, 0x5ecbf1c7, 0xf339d1d1, 0x74e17da2, 0xc3dbc72f,
14190 0x9939f963, 0xa8d1d5e1, 0xefaf5567, 0x508bf1da, 0xfda0676c, 0x6e10f29e,
14191 0xb5c915e7, 0xfe110f59, 0x3cf1da5e, 0x81977bce, 0x310b5ff6, 0xc2f502a6,
14192 0xa714091d, 0x5f1fe37f, 0x643c47cc, 0x7ce8dbcb, 0x0675d7cf, 0x94e1c215,
14193 0xcf0036d6, 0x694e38d3, 0x142cdfc8, 0xfcd3c2f5, 0x60517dbc, 0x2fe10e7b,
14194 0xf51a3ab4, 0x47c0d16c, 0xa7bce3a7, 0xa22fd5ca, 0xe65ec3bf, 0xd85dc6f7,
14195 0x7e837005, 0x9435ea17, 0xcbb5daad, 0x3be2e744, 0x78f9eaa5, 0x9ea3893f,
14196 0x5434ebb7, 0xf51d3c13, 0xb4defc49, 0x48e8305d, 0xe7c5b76c, 0x97fa85f9,
14197 0xbd1fd1d3, 0xf254caf8, 0x55fa154b, 0xcea8a5f8, 0x3f1d7cff, 0xfe245ab7,
14198 0x33076666, 0x2e93c57a, 0xebae781e, 0xffd3ccb7, 0xce868362, 0xd8ea1779,
14199 0x560fcc5a, 0xea28a1f8, 0x5f5c5cae, 0x1136aa91, 0x31c296ed, 0x2f91f3ed,
14200 0x3e98182e, 0x27bdda02, 0xe35155f4, 0xff6819ea, 0xa63e68de, 0xbf8f9c11,
14201 0xeb7ae089, 0xd383269b, 0xbfd1bf7b, 0x9992b4fc, 0xd4f04fdf, 0x7be15a7f,
14202 0xad3df0de, 0xb4fd04ab, 0x3f2e10b2, 0xbc7b40ce, 0x7c502e93, 0xbf4ac167,
14203 0x78239273, 0xb699645e, 0x9ef5113d, 0x863ffe32, 0xa85db99b, 0xb7fba76e,
14204 0x454dfbfc, 0xc8e50473, 0xb79e7e6e, 0xa0ea51a8, 0x52082273, 0x8b667baf,
14205 0xe6270ef4, 0x8787f509, 0x07812c88, 0x11b9eb18, 0xa28f3431, 0x079d0306,
14206 0x0f680e2f, 0xc4a93b42, 0xf6841ed4, 0x32ebd74f, 0xe889c3dd, 0x8fc6550b,
14207 0x894f7cf5, 0x34ba1613, 0xdf7f4336, 0x1c60e583, 0x0dfe1972, 0x047578a0,
14208 0x682a27df, 0xcfe7e40a, 0x1e74edcd, 0x263cffdb, 0xc5ecd3ae, 0x2f4d5d8f,
14209 0xe9fb7985, 0x797047a3, 0x10752dd0, 0xe3ff74df, 0x83a468f3, 0x8b5b1522,
14210 0x251795fb, 0xea022e7e, 0xa2e21e74, 0xfa2cf7d8, 0xf48018d6, 0x129bf173,
14211 0xa92ee3e2, 0xfb5ce49d, 0x7c933fee, 0x93b4d2e8, 0xc468fb9c, 0xe8fc937f,
14212 0x8f9f6e0a, 0x447dab72, 0xd91f7f0f, 0x23cf1f3e, 0x7c7589bd, 0x81fff78f,
14213 0xfddaeffe, 0xefa8fded, 0x8f3ccaa7, 0x31a4bd82, 0x8710f8f3, 0x270132f7,
14214 0xae9c36c6, 0x6343ff24, 0x2dd0fd41, 0x166f03e8, 0x98fe5e64, 0xcc5d4fc2,
14215 0xf911a7b2, 0xc7df80b3, 0xc3557603, 0xcdff686b, 0x84fba309, 0xeca6e1fc,
14216 0xfc868633, 0x69e2296d, 0xc0fec986, 0x69538008, 0x17f93b6a, 0x87a4ed40,
14217 0x91d4deca, 0xe9add99f, 0x2bf281d9, 0x8b9f64c5, 0x6db44aed, 0xbc2433eb,
14218 0x15bda0a7, 0xca29fa4d, 0x3997c7f9, 0xbea575bd, 0x884dcfc4, 0x8162ca7d,
14219 0xb25bbc07, 0xe243e916, 0x69ab7e78, 0x6f28fbdf, 0x48e2daba, 0xd3f3fb4e,
14220 0xe8a7a685, 0x404f8a9e, 0xe2bc3baf, 0x7c2c9f00, 0x6601f299, 0xf1881e63,
14221 0xbdbe73fa, 0xfe4bdddf, 0xf5ecdb20, 0xc6b1e91c, 0x170feeb7, 0x0fb74ba4,
14222 0xde68381f, 0x00df903b, 0xda13c5fe, 0xbe877ee8, 0xcba84cfa, 0x7e23f55e,
14223 0x78f6bf75, 0x0fda005f, 0x505d843b, 0x9a7dd432, 0x3c3df7fc, 0xf40ab76f,
14224 0x07f7d51a, 0x6aa57e52, 0x50ade80f, 0x5f50b7ae, 0x51b50714, 0xbf6baadc,
14225 0xd779f68e, 0xc68f9f34, 0x523d03f5, 0xf9b8a67c, 0x7ccbdd20, 0x4c87fd10,
14226 0x94618fd2, 0x39bfb317, 0xe510fd0c, 0x95ca8979, 0xd3f5f228, 0xcf287e51,
14227 0x2277654b, 0xda95f39d, 0x8388fee8, 0x2a25de62, 0x1758cba8, 0xdf3896f3,
14228 0x2f7e66b3, 0x5ede3f96, 0x76edc119, 0x9f740f90, 0x79d79ae7, 0x079140dc,
14229 0x1cae4285, 0x9ca9e7c1, 0x3ecacdff, 0x442d7411, 0x4e47efbe, 0x0b308f24,
14230 0xe282b87f, 0x58463b3a, 0xa7f45d78, 0x89dc7971, 0xd1bd97de, 0x8a9b1e99,
14231 0x3dca2cfd, 0x14791e5f, 0x282f91e7, 0x0e482207, 0xc184d1ac, 0x945e8aba,
14232 0xc2a2fee8, 0xa073ab79, 0x7ea65b39, 0x2d49ee88, 0xe35bbcc0, 0xa7f2f3f5,
14233 0x57b8f1a3, 0xec52f288, 0xe0ed1503, 0x351740fb, 0xe40d1f7c, 0x2ff5e50d,
14234 0x073ab49b, 0x68496ff9, 0x4fdbd6a9, 0xd7f8d9be, 0x58af5b9d, 0x0fde139d,
14235 0xdcad179f, 0x5d883ad2, 0xbda15e3f, 0x72cc2736, 0xde6573fd, 0x3cca0d17,
14236 0x79066827, 0xeaf663c3, 0x734fbc1c, 0x85dffe99, 0xc5f75f07, 0xf51b9d66,
14237 0xf697c02e, 0x56bcee83, 0xbd5f13e1, 0xcc8578d9, 0x371ffb49, 0x597fbf9a,
14238 0x534fb922, 0x57f02d5e, 0xf9d9f13d, 0xa0fdef68, 0xf6be4229, 0x160a25c5,
14239 0x407ba30e, 0x79870bec, 0x4bfc25c7, 0x55839410, 0xa0e23394, 0xbe70f812,
14240 0x28781fb5, 0x0467ffed, 0x329a4fcf, 0xe0d5f382, 0xbdcfc5a9, 0xa39e28c6,
14241 0xe3741d4e, 0x54a621f3, 0x7cb74fce, 0x2062643e, 0x60c8776f, 0xf74fb8c6,
14242 0x5c51bfa1, 0x719d7bb8, 0x306fdf36, 0xdf7848b2, 0xddb6911a, 0x8afbfe3b,
14243 0xe7814738, 0x7efce9be, 0xe387e6b2, 0xbea6a94a, 0x1bd912b8, 0xcfb481a9,
14244 0x9574d5d2, 0x4b775bf4, 0x43f719a6, 0x469cdaba, 0x7ff2b7e4, 0xea184ffc,
14245 0xb396aee1, 0xf5d69794, 0x57ca79dd, 0x06f228db, 0x7c89348f, 0x098b36af,
14246 0x7ee7779f, 0x36ed8391, 0x5713d289, 0xa53171e0, 0x2565fc54, 0xff75e07e,
14247 0x6b8428d1, 0x93e379bd, 0xa60f3019, 0x1ddfa6af, 0x0439ff00, 0xae2787f5,
14248 0xa1ff0960, 0x2b8c4a3c, 0xb8f027c4, 0x57189602, 0xb8f0d788, 0xae31d602,
14249 0x15c62580, 0x15c639f0, 0x05718eb0, 0x015c63ac, 0xc05718eb, 0xf80ae312,
14250 0x8e716bfc, 0x378c1ba3, 0x9234f71e, 0xcf515ffc, 0x88576bf7, 0xd457a1fb,
14251 0x85b7944a, 0x0f5038e7, 0xd3c7975e, 0x5c78f228, 0xb03f685b, 0x456cbf7c,
14252 0x0f79e154, 0x79f30e87, 0x3c628e7a, 0x64af7ca8, 0xe7c16d5d, 0x1b1e69b3,
14253 0x9e3f325b, 0x35ebcf87, 0xac97bc56, 0x309be5bb, 0xb515778c, 0x6adc53d4,
14254 0x2d21f852, 0x6241b9e1, 0xa59d6f18, 0xa9727ee3, 0xd3474f0c, 0xd1d929be,
14255 0xf236baa5, 0x4a778a5f, 0xddf3ef66, 0x90af63e5, 0x9bcbe89c, 0xf9cc1972,
14256 0xc6d5fa3e, 0x4ff0aef3, 0x57d88fc4, 0xf49bca5e, 0x3d9159e5, 0x2d1f65e2,
14257 0x7c64fdc5, 0xe7477f2e, 0xd1c14a4b, 0x93f5281d, 0xcfb7e587, 0x77b2d45c,
14258 0xe29bde3d, 0x77dcdfbf, 0x9f6fcf5e, 0xd8aa6579, 0xcfc51e4f, 0x9d3ee489,
14259 0x7c3f67bf, 0x475ab7af, 0x70e54af6, 0x266a657b, 0x28d86be6, 0x90f472ee,
14260 0x2fadfc81, 0xc4f924b7, 0x21e5b25d, 0xae58f714, 0x6b8f4891, 0xb0ebed92,
14261 0xc5dcc4df, 0x18996f14, 0x567e2261, 0xa4bdf0e8, 0xfdf1c7bc, 0xc50b34f2,
14262 0xec75b2bb, 0xc89e3467, 0xf89282ef, 0xa24abb2d, 0x3217a97b, 0x597b9d2b,
14263 0xf2f7e360, 0x2de8f729, 0x41cf3c60, 0x5be5aba1, 0x282bb224, 0xfb861100,
14264 0x0b9e1c9d, 0x7ba1de5a, 0xc4eb164f, 0xbe2a7e3d, 0x89b51e1f, 0xc12cbfe7,
14265 0xdef0a41b, 0x58abd010, 0xb37d9e82, 0x03db9e1d, 0x3b734487, 0xe38e12df,
14266 0xa1ae3c2f, 0xf0ece13c, 0xa4ed13bb, 0x3e5127ef, 0xf6ef5e03, 0x921f88fd,
14267 0x0cf9bea3, 0x43793547, 0x48addd70, 0xb1e714a7, 0xb2bc7953, 0x9e254a80,
14268 0x762fe4a3, 0x17b83a1f, 0xce5d9fbf, 0xe1bde5ef, 0xfe80bd79, 0xe729adcf,
14269 0xf9145e15, 0x53aa5175, 0x75fcf063, 0x2b46b7d4, 0xfc3b3fae, 0x8af79d10,
14270 0x4e1fe313, 0xe5037bcc, 0x39882d8a, 0xcbee1fb0, 0x733c0354, 0xc6120170,
14271 0x3c365dcd, 0x4873d337, 0xf51e5332, 0xcb73f275, 0x29efcc3a, 0xdee8978f,
14272 0xea809cf0, 0x3f1830ec, 0x8ac63627, 0x89bcbbf2, 0xa0bb5dc7, 0xc3bf78e4,
14273 0x3181f749, 0x14d73f7e, 0x2490b781, 0x4cd489fb, 0x82a9f3cf, 0xae5bba6f,
14274 0x9be1fcf2, 0xe8eb65c7, 0xb06613be, 0x21b1f72a, 0x188ea7de, 0x8559f14a,
14275 0xc21b7a6e, 0x7cdd23b7, 0xbcc3f42e, 0x68352779, 0x6c987c3f, 0x30e10cff,
14276 0xbacaff3f, 0xff675a30, 0xcf2531f1, 0xa63e3fde, 0xabffedc8, 0x2bf7fafc,
14277 0x513ca82b, 0xb6ca92b9, 0x07bd074a, 0xea75f0bd, 0xff55c5ad, 0x8ff5f08e,
14278 0x65bd32ab, 0xe057e900, 0xf6c71e6f, 0x5f02a38b, 0x7af8bcab, 0xa2f04b62,
14279 0xd47f680d, 0x4ffee968, 0x615e77cc, 0x49a03924, 0xaa9e37eb, 0xf148cdc0,
14280 0x18665ed7, 0x909ff08d, 0xc156a71c, 0x926901fb, 0xf200fecf, 0xf90fae09,
14281 0x13e44b04, 0xf3dc57b5, 0x70b02d05, 0x1c07b706, 0x08180f64, 0x8357ebaf,
14282 0x1ef090fc, 0xfc8fb325, 0x3f27e4b8, 0x907971c0, 0xf0b57dce, 0xef2526fc,
14283 0xd7140273, 0x4f23f746, 0x0c9e5c5c, 0xc2ed700d, 0x0b2d0cef, 0xa3e2bca0,
14284 0x475f4e1a, 0xb9bcf237, 0xefc7967c, 0xae5eba6f, 0x163e2104, 0xf339ec0f,
14285 0xfc5fb43c, 0x35d9232b, 0x669723eb, 0x257227fd, 0xc3c38d20, 0x63258131,
14286 0xcacdf27e, 0xe045ee7e, 0x314e66f7, 0x2e5b9f91, 0x7cb2a0ec, 0x72a7f133,
14287 0xed4cb43e, 0xed8f58ea, 0xff3c4d42, 0xbee8cd43, 0xc1aa5396, 0xc1599efc,
14288 0xc4a6a767, 0x58605e51, 0xa887bf15, 0xee896ee7, 0xc8149e03, 0x56c857ef,
14289 0x0cbc95e5, 0xb956dfef, 0x54c1efc5, 0x122bf8d3, 0x73d15c79, 0x6bdb951e,
14290 0xba26b951, 0xbaf6413f, 0xc631a93f, 0x39f45eeb, 0x6ecfbefc, 0x4dff72a7,
14291 0xa087bcde, 0x7e1ccd5f, 0xb33766cf, 0x03fb813c, 0x7100828e, 0xb5e8127f,
14292 0x99fdcf0c, 0xedc9fe07, 0x15429ebc, 0x19ad539d, 0xeb8d5965, 0x42cc79aa,
14293 0x27f73def, 0xe8dcf871, 0x82db9c3e, 0x8369f9ec, 0xe717bfae, 0xce6f2919,
14294 0x669fec12, 0xe34ff7e4, 0xeed08de5, 0x4fe19ce8, 0x0e3840ec, 0x3da264b1,
14295 0x706c68be, 0x11f40496, 0x06f306a5, 0xd4630fe8, 0x46d05f74, 0x71f313b5,
14296 0x7dc5a887, 0xef216a01, 0xd180c861, 0x85a6ded4, 0x96a7c2fa, 0xabea1b31,
14297 0xf3f74628, 0xfef9ebc6, 0x5863f438, 0x4646b862, 0x7c78c83d, 0x3e00e168,
14298 0x4670c2fe, 0x45a5cfbf, 0x3bf25016, 0x2677f0b3, 0xb0bbc518, 0xea68d07f,
14299 0xfef150ef, 0xc3943536, 0x523df8e2, 0xb474eb3d, 0xf1f0ba2f, 0xa71fa4a1,
14300 0x773df04d, 0xe78d327f, 0xb8e5282d, 0x9f0f8b74, 0x429b5a2f, 0xd68b8bfb,
14301 0x3b4529ce, 0x4810dec4, 0xef3b02e7, 0xef0ba97b, 0x9d962f71, 0xf5823f4b,
14302 0x57b74ecc, 0x4a2f7c23, 0xa1fbf996, 0xdffba2c1, 0x8c9e62d2, 0xf2e335dd,
14303 0x774e50eb, 0xf7813dec, 0x4fbf4de4, 0x19d3fea6, 0xad9a8fbf, 0xde6cf7e5,
14304 0x8ea2b8ed, 0x1eeff180, 0xbcbc5127, 0x468e60c3, 0xc0a16efb, 0x5c69f3d7,
14305 0x3f5c2f7e, 0xebfd1134, 0xbddf71bb, 0x5a733d1f, 0x0fde53b4, 0xfc7cc89b,
14306 0xfbc54f9b, 0xfef8d34f, 0xfe38b0fc, 0xae837f3e, 0x4b082e23, 0x4a093b8d,
14307 0x4ec2758d, 0x58b4cf5c, 0xe115b396, 0x378f28f8, 0x9b981876, 0x8d3eb1e8,
14308 0x3d676ae0, 0x3ae38f1d, 0x3ad046ea, 0xa39bc63a, 0x710e5ee9, 0x3312eb7f,
14309 0xe31d4f97, 0x98ce77f9, 0xa9214ddb, 0x1ef07f9c, 0xa502c5d7, 0x3d565767,
14310 0x5bb41b79, 0xe74f4abc, 0x7d3c9735, 0x8b2bf92f, 0xa73a646b, 0xdefb36c9,
14311 0xc4fa0ae3, 0xbff3f38d, 0xdeffd58f, 0xd239c455, 0x8966fe41, 0x955868e8,
14312 0xf1fb8b55, 0x4ec05b3d, 0x46f9f780, 0x05da3c77, 0x758356f9, 0xbdcfd48d,
14313 0xdc01dfac, 0x6b9ef0b2, 0xcf93f146, 0xe01fedd3, 0x2f561777, 0x03507ba4,
14314 0x1714ed53, 0x217e061b, 0x48413fda, 0x69d7003f, 0x7fba5e00, 0x891edd42,
14315 0x34facffe, 0x9cc43cf1, 0x34ba2468, 0x0ee7e430, 0xe711398d, 0xa0ceb1d7,
14316 0x6d319942, 0xe04fa70d, 0x347abd1b, 0x0160339e, 0x4bbfbfc8, 0x6f3974e3,
14317 0x16af3ab5, 0x6d4043ea, 0x6e90429b, 0x4e7d1146, 0x50ebdab6, 0x18f57daf,
14318 0x73728b1b, 0x7c2de6f1, 0x4cff025e, 0x34e746dd, 0x198faabf, 0x0a06798d,
14319 0x4eb64c3d, 0x4de69b38, 0x8449f707, 0x31cf587f, 0xeb1a37d4, 0x2f5c4ea2,
14320 0xf48c3f3c, 0x9b826d31, 0xe5b212f2, 0xbcfdfa12, 0xf74608de, 0xce32f4f2,
14321 0xd41bbdaf, 0x391467a4, 0xa003c8a1, 0xd39e1b07, 0x7ffdf055, 0xf2287f65,
14322 0x7243e006, 0x8a1b9145, 0x4be8517c, 0x74fe3391, 0x7cc01f35, 0x4fea68e7,
14323 0x63914cf2, 0x68d50eb8, 0xf0517c8f, 0x5e30d9ac, 0x81577145, 0xd2f96ce7,
14324 0x8708839e, 0x2dd92302, 0xea31707d, 0x5ad12e09, 0xcff784d6, 0xb7943d56,
14325 0xe3d22977, 0xd063732f, 0xe05b98fe, 0xa7f29e7b, 0x28e7be15, 0x3df4ac17,
14326 0xe56f3947, 0xfc628e9f, 0x0fb00d89, 0x9cfc074b, 0x17b9e5f9, 0xefea863e,
14327 0x8131797e, 0xea97d9fb, 0xaeefc59f, 0x68f3100a, 0xa55af3e7, 0x4c31bd25,
14328 0x0ff881d8, 0x7188b2f1, 0x13185d3e, 0xdff5027c, 0x093f105f, 0xf1c1ffb8,
14329 0x67e04673, 0xe80fc211, 0xae3ae17e, 0x121c3a97, 0xad1623c5, 0xc1ba7c15,
14330 0xe7f47cf7, 0x303dac91, 0xfa8e73ce, 0xa312c7f3, 0x7395af91, 0xfc0df6d3,
14331 0xf2b4b55c, 0x762fd918, 0x872d7ee5, 0x2b5afddf, 0xebf9f95b, 0xcd73df76,
14332 0x2d361981, 0xf7182bc5, 0x1f2516a3, 0xd536f9e1, 0xbbf71992, 0xfcf3c5f3,
14333 0xb9cf920d, 0x1e749cb9, 0xa698da17, 0xa3b63c26, 0xcaf1429d, 0x0a2fd26a,
14334 0xa0dc829d, 0xd5f97c73, 0xbd4bb4a3, 0xf122e8e4, 0xcab2717c, 0x36d777e7,
14335 0xebfdf1a6, 0x181a6476, 0xac725377, 0x3bc90976, 0x9547c50b, 0x47928bf6,
14336 0xc1b8c7af, 0xebf8cda2, 0x33fe9e47, 0x367cf9d3, 0xdc94f98a, 0xe5f7ce40,
14337 0xb79fe155, 0x9fc9bcd3, 0xf7757a2e, 0x033bf8ab, 0x91d57f45, 0x291a299e,
14338 0x9d53d9f6, 0x3ed2f759, 0x55d73f32, 0x693df026, 0xe84167f7, 0xf2379427,
14339 0xeca1b2fb, 0x556cb2c0, 0x65fbf901, 0x9087e056, 0xdfbff3eb, 0x41aff57e,
14340 0x88ecbe3c, 0x47ffbf12, 0xd65563bf, 0x1fc505f8, 0x64772ed0, 0x4f9478d0,
14341 0x5cbfdfee, 0xfb882efa, 0x9704edb1, 0x84df43ec, 0x5ff63cd1, 0xf979b8a5,
14342 0xf66175a1, 0xdd7dd67e, 0xcf110139, 0x2af81728, 0xe0af9b67, 0xaaf95afe,
14343 0xc82cf3dc, 0xbf7fbe33, 0xce22e975, 0x8dbb1b70, 0x4cd5d6f2, 0x5ccf7de5,
14344 0x07e133af, 0xb7cb25f3, 0xbd9d73f2, 0xdc00cb6a, 0xe716eb97, 0x1ddbfcb4,
14345 0xc37ee74f, 0x0c27e065, 0xc8377444, 0xddd3cfb4, 0x6578e3c0, 0xe2b54f0d,
14346 0x7032d8f9, 0x959d919c, 0x8d654473, 0xeb7bd332, 0x1a47cc35, 0x1679e378,
14347 0xfdd136ef, 0xc92e8534, 0xe9f30f56, 0x90697f05, 0x165e7cd7, 0x73ac5574,
14348 0xcaf8e165, 0x72105ffc, 0xd857694c, 0xb79d14f2, 0x645d7685, 0x903efc9f,
14349 0x9eb2fdf1, 0xcecf3813, 0x7f68636d, 0xb7b5d0ab, 0x0d8fe28c, 0x72b79481,
14350 0x7e7be351, 0xdef89f7b, 0x676e74be, 0x24de6274, 0xa6557ff6, 0x13ce19b8,
14351 0xe4a2f1f9, 0x2cd1cf9b, 0x73a735fa, 0x3a7e653b, 0x7da503e7, 0x2823aba1,
14352 0x6f9fda1e, 0x6f9513fa, 0x6f7c7b61, 0xbd474b6c, 0x9031be79, 0x6f9ed3ce,
14353 0x0de73e7c, 0xd765def8, 0x8bc950f8, 0xf3a74ebf, 0x6de5e5f8, 0x73b05ce2,
14354 0xe26738a0, 0x3674f5a2, 0x5fe84944, 0xaffc8a96, 0x417dc6ce, 0xc75fe22a,
14355 0x627bf67f, 0xefbbafb3, 0x264c77ac, 0xf76cbf9e, 0x7fecefb9, 0xf132fc6b,
14356 0x13caa8dc, 0xb7bfe1df, 0x5ddf94ca, 0x4a76f331, 0x48fe763c, 0x0e7803cb,
14357 0x7fc7bd97, 0xfeec0d97, 0x9a3fd167, 0xe481c7ff, 0xadefe27f, 0xf7ebfd60,
14358 0xfcd9bef9, 0x44ae4231, 0x4cbe53b4, 0x1fb70c47, 0xcc48364a, 0x062b7006,
14359 0x680072fa, 0xb3329c4b, 0x231dfde3, 0x2772fef9, 0x2476bfd0, 0x67ca0bc9,
14360 0x1dfe0339, 0x6bc10efd, 0x24b93f7c, 0xe7889dd6, 0x5e453b03, 0x3b884941,
14361 0x7b8c2071, 0xc949d049, 0xb7a2774c, 0xddb2537f, 0x9735794d, 0xbe1d3e44,
14362 0xc95e78c7, 0x23aede68, 0xe745dcc6, 0x189bf638, 0x83aaabda, 0xd2c3a226,
14363 0xbddb0d97, 0x4699d5cf, 0x92fffb72, 0xee1bdf96, 0x53e7c1d8, 0xe34d5418,
14364 0x5df4125c, 0xf34d5018, 0x29ce233b, 0xbd796a17, 0xbee8c343, 0xfc5d9efe,
14365 0x918ba13e, 0x3bf0076d, 0x50a57717, 0x8c4769de, 0xbd136973, 0x452679e7,
14366 0x38dce8af, 0x4cbb0baf, 0xf7282e74, 0x9f695b97, 0x274eb7b1, 0xc2e1dc61,
14367 0x1ee74620, 0x220fd42e, 0xb2417d7d, 0xc2f37c50, 0xbc6903bb, 0x7495caa2,
14368 0xc408a5be, 0x509dda04, 0x76bda2e6, 0x68b9fea1, 0x6fa85fe4, 0x559dbac0,
14369 0xf239ffcf, 0xbbfe4ee9, 0xf95f1710, 0xbef78a7b, 0xeffa528f, 0x54f8289f,
14370 0xe48da7de, 0x923698fc, 0x91a8f3f3, 0x3bde7e66, 0x2c4cf5d0, 0x37f38fad,
14371 0x02fc99c0, 0xafba27e0, 0x39ab8ce7, 0x8a71824c, 0xa86c9a0e, 0xee343bdf,
14372 0x0e09e7c4, 0x7877e281, 0x1785f918, 0xbf240c76, 0x1a68ac1c, 0x348ec2e7,
14373 0xf252d3ca, 0xada1a64d, 0x234c7846, 0xdbcb66f8, 0xe5fee9d2, 0xc7ca40ba,
14374 0x36fc7a29, 0xc89fe515, 0x7a2eeedc, 0x5134f175, 0x4d7ee1b7, 0xa17fcfd1,
14375 0x93e28bc0, 0x89695e4a, 0x8fa5a390, 0xf30031df, 0x651fd970, 0xaabb93ca,
14376 0xfe8f79e6, 0x48e5f970, 0xbc0f4721, 0x025b7c40, 0xc3bf8e74, 0xc2f22c54,
14377 0x71e15f8b, 0x77f5e296, 0xf1f24b3c, 0xde618684, 0x53d725ef, 0x2f70de41,
14378 0x96e5c918, 0xda95bfa7, 0xde7b4317, 0x9a20bdff, 0xe50d0ecf, 0xebe3fb29,
14379 0x22bffb96, 0x8bfd5bff, 0xf407605c, 0x957c1fb3, 0x57f23db5, 0x060d0394,
14380 0xf29e83ab, 0x8d4ebdfc, 0xdf3f296b, 0xd0f92060, 0xaf7e2c19, 0x11e792b5,
14381 0xfa9faf14, 0x3857ca6b, 0x699d2f75, 0x7fece65a, 0xa474aebf, 0x0f8bef86,
14382 0x3e400eb4, 0xe07c052c, 0x3a1f8078, 0xa8fece5f, 0xebfefea1, 0xcb923a99,
14383 0xdc3e3ef5, 0x3ba1f3c3, 0x74bc7307, 0x7a449abe, 0xd39823a7, 0xfc97cc35,
14384 0x5e60ced4, 0xe604a252, 0x3d3998df, 0x91778e74, 0xed29ddff, 0xc343b2a5,
14385 0x14ad15fb, 0xe6e22bbf, 0x482523f9, 0xff7871b3, 0xb436e6cf, 0x671e503b,
14386 0xadd2a68d, 0x1efeb90b, 0xf263a076, 0x7e0a8eef, 0xe870f252, 0xae280177,
14387 0x3ca2d2e9, 0xafbb0bb5, 0xdffae1a4, 0xefe7e08b, 0xae43ca25, 0xfb29291b,
14388 0x540794ec, 0x2b3c25cc, 0x9fb44876, 0xa1f6bc5f, 0xe2fba442, 0x91732d8a,
14389 0x1475941f, 0xfa2e59ab, 0x4c921d49, 0x7ebf01f3, 0xebd4ccc1, 0xf7c0a7bf,
14390 0x197ccaf7, 0x3d27cfdf, 0x6fb6bc03, 0x53b145a4, 0x578c3559, 0x4cda56b2,
14391 0xfc5189df, 0x053ebe4e, 0x83efb84e, 0x3c4a8cf9, 0x57eb46e0, 0xf9a379e6,
14392 0x75e423bc, 0xd7e58c47, 0x1fdf10e3, 0xae4f24c8, 0x4066377e, 0x6dd80fc8,
14393 0xcaa14bf4, 0x0fff3078, 0x38c11751, 0x56790acf, 0x79c3f30c, 0xfdf36e26,
14394 0x3ae4807d, 0x06f0fadf, 0xa36a7adf, 0xc5bd3d6f, 0xdb7d6eb7, 0xdf82deb7,
14395 0x09c0f4cd, 0x073c61fd, 0x879c53b1, 0xcf187f40, 0x8c3fa133, 0xb187f475,
14396 0x9f187f44, 0x758c3fa3, 0x8eb187f4, 0x8925b0fe, 0xa258c3fb, 0x65cf8c3f,
14397 0x4953872b, 0x023f8f2d, 0x2fb46c1e, 0x5df9473f, 0xd10bf00a, 0x421c2d1e,
14398 0x7cc61d76, 0x7e9577e9, 0xd2296d79, 0xfd930cd1, 0xcc4cc8d2, 0x1f5b6ac7,
14399 0xf2fded89, 0x1b464a94, 0x686f188c, 0x3d7e775f, 0x2629219a, 0xaf6c15fb,
14400 0xae952fe4, 0x4f7e8b7c, 0xe5b57daf, 0x78e13f8f, 0xf287b8a2, 0x78454f7b,
14401 0x714cbe4f, 0xf8a33d2e, 0xdfdf559e, 0xf9fedc3d, 0x679ab746, 0x5801fff4,
14402 0x00db8bbb, 0x0000db8b, 0x00088b1f, 0x00000000, 0x7ccdff00, 0xd594740b,
14403 0xe6feefbd, 0x49324995, 0x41e42126, 0x21e4cc20, 0x49389311, 0x47114bc8,
14404 0xa8d53048, 0x684d43c3, 0x4092138c, 0xa3c30480, 0x7b96c4eb, 0xa4401833,
14405 0x51b78d70, 0xa13a3951, 0xe85de94a, 0xb6950a09, 0x1006739c, 0x4e6d8ac5,
14406 0xb6abad5b, 0xa9078838, 0x68349687, 0x69edec57, 0xdff7ffef, 0xbef997df,
14407 0xbc7b5249, 0xacdd77ab, 0x7bfe7ba5, 0xfe3f6fef, 0xeffffdef, 0xfc42108d,
14408 0xfb5bfe85, 0xdaf08c7c, 0x85fdff05, 0x442fdfff, 0x59cf10b9, 0x0e9d3247,
14409 0xd77c2e21, 0x4f5c5bbe, 0x1868ac65, 0x06e6a42a, 0x09a449bb, 0xb8df11b1,
14410 0x5335a884, 0xef0479a7, 0x28c7f651, 0xa4f34c42, 0x885d3108, 0x49f933d1,
14411 0x05fffa82, 0x2c4f377f, 0xa8cac75b, 0xadde0eb3, 0x6ccf3098, 0x548af09b,
14412 0x735dfb1a, 0x4f1a05f0, 0xa24d79d4, 0xea4d8842, 0x35ece71a, 0x59105109,
14413 0x38c1b5ef, 0xbfeb7421, 0x018a60ee, 0x619a1a2e, 0xb1fd7fe8, 0x497b431c,
14414 0xbda1ae68, 0x13d6f96d, 0x962144e6, 0xf4332eed, 0xbc116abb, 0xa7cfabcf,
14415 0xea6e0307, 0xf0d1bbe7, 0x3aea109d, 0x936eb29d, 0xc3fce475, 0xd1d37fd4,
14416 0xe3004f4c, 0x2f0b35ee, 0x8d03b7ed, 0x2b6442a5, 0x4f181d81, 0x179e2a0c,
14417 0x6a56bc68, 0xe8bb53f7, 0x9d38f3b1, 0x2c3b7e2a, 0x2da4e022, 0x9bf3447d,
14418 0xd1e77fa9, 0xc256e0f4, 0xc9c61f4b, 0xf0a776a4, 0x6b78d326, 0x87170ee6,
14419 0x6f359c68, 0xd042bb7e, 0x83ccbb16, 0x215cced9, 0x03c12b36, 0x9f10b34e,
14420 0xab4e1ca4, 0xd98776a6, 0xf443c8bf, 0xfca67cb9, 0xe78455c7, 0x1ecc87cb,
14421 0x0d6d93cc, 0x291295a5, 0xab268385, 0x038cec06, 0xcdfb07fd, 0x63a24175,
14422 0x9cc3ad16, 0xc18fe112, 0x797169fe, 0x35bec88e, 0x0b6d987e, 0x7d84dccd,
14423 0x79eb1cbd, 0x0a3f8041, 0x9dbc62ef, 0x8fe02b31, 0x80945b8e, 0x3ec8faed,
14424 0x77e53a37, 0xea3e7eda, 0x7c0632a5, 0xdb3e65e6, 0xbe5fb6ac, 0x8bb144f6,
14425 0x7bd9d1f6, 0x2c4cdb2c, 0xe874ceb0, 0x01952640, 0xfb19bfbb, 0xffcc18e9,
14426 0x679a7cc5, 0x61663bed, 0x3efffea6, 0x9ab128b0, 0x8bc9f7f6, 0xc13d4f56,
14427 0xdb7ff70f, 0xac7da616, 0x1e6d04b5, 0x3bbe3b2a, 0x7952f368, 0xae41c1eb,
14428 0x65b0755f, 0xb575f831, 0x7d81dee8, 0xbf12b25f, 0xb1d1f0eb, 0xa4e7d950,
14429 0x31eebf75, 0xc4777f31, 0x6bda3f09, 0xa74ff3cd, 0x95077f62, 0xb97b2c12,
14430 0x85adb0ef, 0x7ed47bea, 0x7a32f2d1, 0x74ed5976, 0xa43a3fea, 0x92a7de30,
14431 0xd743bb8f, 0x1b2c7cb2, 0x7cb97373, 0x88213aec, 0xbe11df25, 0xa5744122,
14432 0x3ef01ab5, 0xfcccd67a, 0x1cdc7a39, 0x8749f414, 0x0cba942d, 0x2b17f874,
14433 0xf88ba1d3, 0xa4f88aa7, 0x40df7e8b, 0xd9be6fa5, 0xd40fbfc0, 0xbdf81bc4,
14434 0x88e4e841, 0xcc47bbc6, 0xebcbc030, 0xeffd0d73, 0x945d7e5d, 0xda46943c,
14435 0x0dfff8cd, 0xbb827691, 0x4a5c04b6, 0xc685a022, 0x30b72a7a, 0xf866dd9f,
14436 0x8d2c4bbe, 0x3f9f03f4, 0x678c6fff, 0x4b6d8621, 0x26bf688b, 0xafd107a2,
14437 0xad5e7fc1, 0x6d3d730f, 0xb39720c4, 0x98bf3d73, 0xf2317c4f, 0x47ec55b6,
14438 0xdf089fc5, 0x7f46e815, 0x20e913b9, 0x9d5a1104, 0xb1d68937, 0xa9c908fe,
14439 0x618a5f41, 0x06eb17d0, 0x74b6ba1d, 0x2a628bd4, 0xb4059be9, 0xb0c0ae8f,
14440 0xf8c1dbad, 0x4a1164b7, 0xa22bf7d6, 0xdbfb8527, 0xbc2452b3, 0xac47f505,
14441 0xf875861f, 0x686378c3, 0x816e633f, 0xafb744bc, 0xac0b7da7, 0x3dfeec47,
14442 0x2dfad5f4, 0xde631f75, 0xea3cdaf5, 0xae9f1af8, 0xebdf4bde, 0x9e3d1dd6,
14443 0x72c5c4a3, 0xe1e0f6bd, 0x7e1067d7, 0x4b92f996, 0x439d4720, 0x852dac4b,
14444 0xd34df913, 0x9a0f57fb, 0xf06e3183, 0xb7e629df, 0x8f5683d1, 0xb2f01bf8,
14445 0x0f182bde, 0x8ab87cd1, 0xf9a765f6, 0x3c511d57, 0x03f64541, 0xf146d67e,
14446 0x9acdc627, 0xbe1a6f04, 0xd517f1c6, 0x683f1abe, 0x298fab9d, 0x09cbe841,
14447 0xa7c68978, 0x3f2acf3a, 0x0aeb90fd, 0xc6a2baf2, 0xf2d15515, 0xfe86c9b8,
14448 0xe114fba3, 0x1f18be54, 0x2c6cc74b, 0xe573b3df, 0x2a8e47fe, 0xddf4fd9e,
14449 0xae16633d, 0x1f1fe71f, 0xf214ade1, 0x921f0137, 0x7e527c9f, 0xe34b1eee,
14450 0x7c5efeef, 0x34fc45f5, 0xefdc573b, 0x7af44473, 0x621e9e44, 0x49294b3e,
14451 0x5b48bd48, 0xace5dfa0, 0x3b3d541f, 0x4d243e95, 0xfc94facf, 0x71e7e603,
14452 0xf894e3bb, 0xa57568dc, 0xeb4f8327, 0xd468f68c, 0xd64a4ae2, 0x642d21f9,
14453 0xc0d35d67, 0xc2d333bf, 0x609f8e34, 0x4f4d57e8, 0x76f1d5fb, 0x0ecdcb6c,
14454 0x6ff3beeb, 0xea09a6b7, 0x1a75bd9f, 0xceb12d97, 0x9691d834, 0xec1f66ad,
14455 0xa48f87e3, 0x5f1155a7, 0x9addb87d, 0x7c434f5a, 0x6cbce0f8, 0x96b80451,
14456 0xc58f0bcb, 0x131d0434, 0x625d55f7, 0xfd747c62, 0xaed8f7f7, 0x3674d6fd,
14457 0xb77201b1, 0x156268fd, 0xfb6eb38d, 0x649c2acf, 0xfe4c87cf, 0xffda12ba,
14458 0xdb20ca27, 0x2c1ce173, 0xfc4515f6, 0x6bdbb589, 0x3bf761d3, 0x59ea7cff,
14459 0x56ff7dd8, 0xf8899a6b, 0x273f37e8, 0x3db0a87b, 0x52e23f63, 0x4be3e4ac,
14460 0xfb07c42f, 0x292fff88, 0xf54b1bc2, 0x8a27cc6b, 0x7afb069d, 0xffcc1efc,
14461 0xb79a76cf, 0x0f06f31c, 0x4f5e6064, 0xebcc1ae0, 0xe49f9adf, 0xddfe2bff,
14462 0x7fa57b03, 0xe7b54077, 0xa0328857, 0x3b5ec1db, 0x97abffc3, 0x88473d10,
14463 0x0c19bd43, 0xe2ebd4bf, 0x80b7a872, 0x3914d7eb, 0x46fbbd25, 0x3cd2364a,
14464 0xa0a28581, 0xa3aded9b, 0xdfeb42c0, 0xe079c4a4, 0x3c526c4f, 0xfdd04ee9,
14465 0xced2c9e7, 0x5e8bf4aa, 0xe4234dcf, 0xf3f8e983, 0x68bb31e6, 0x2deff1d3,
14466 0x2f00d922, 0xfa1a67b2, 0x86dd3ad7, 0xae335bf6, 0xc57fb435, 0x6f806255,
14467 0xf436a82f, 0x8b73c3bf, 0xeaabbe01, 0x4bfe862b, 0xf00c4bbc, 0x4346bab2,
14468 0x2d7dbbff, 0x1b7bf686, 0x1bda18d6, 0xf00c1bfd, 0x341e3b57, 0x7bafbff4,
14469 0x2bdda1ab, 0xbbd8169c, 0x171f44e3, 0x885ffde1, 0xbd37282e, 0xd3d0ef9d,
14470 0x5322fe75, 0x7c24d0f7, 0xf48968fb, 0xea517e6f, 0x98fe05dd, 0x487c9265,
14471 0xc3ae17a5, 0xd427b033, 0x0a42259e, 0x38622bfb, 0xdd137c13, 0x7e7dba2f,
14472 0x2eabc9fc, 0xf4ada1a2, 0xe90b06c3, 0x2795f98d, 0xbe0972cb, 0x1b6be5f3,
14473 0xe61fa42d, 0x2af278df, 0xb6951fe0, 0x32fb7235, 0xc345aec1, 0x04376fcb,
14474 0x6ff39d68, 0x81edd9ce, 0xe913f3df, 0x9fc54cf7, 0xbe5b77d8, 0x10ca37dc,
14475 0x93ca23f1, 0x5f288fc4, 0xb36c7e23, 0xfc47bf92, 0xaf4cf288, 0xd47feb87,
14476 0xd9e5c55b, 0x3f972f5e, 0x72e3adee, 0xe5c7d7b8, 0xb81b7b4f, 0x9faf79fc,
14477 0xb7b77bbf, 0x7af7cb83, 0x97feb9bb, 0xfe5c3dbd, 0xf5c037aa, 0x2c2896af,
14478 0x0102b4ff, 0x037b05bd, 0x776f5dfe, 0x77a4cc84, 0xe5eb31c5, 0xf24abd71,
14479 0xdda578ad, 0xa2a95c54, 0x6ebeca89, 0x5c878e11, 0x17c92d86, 0x39f8be89,
14480 0x7a237ed9, 0xea2e22d4, 0xc61fadfc, 0xaf424f7a, 0xc9d33108, 0xffad58fa,
14481 0x69ef52a7, 0x15ee5fae, 0x977a7d7a, 0xd023ffdb, 0xb2f71dfb, 0xec3332fc,
14482 0x24e9f753, 0x24c77a6a, 0x93e3263a, 0x593e5467, 0xc62c4f60, 0x3d816ef9,
14483 0xb27b083b, 0x83ee12c0, 0x4cfbea1e, 0x3d221eb8, 0xc6c12274, 0x11efa97a,
14484 0xca13fb0b, 0x9be182a7, 0x7dc30552, 0xa19b0d9f, 0x3d381777, 0x54576c19,
14485 0x022ecf38, 0xdd722949, 0x4a1e6758, 0xa7cd53c2, 0xf3b045e1, 0x2e6c3937,
14486 0x5f9c09e8, 0xcf314a62, 0x02bcdabb, 0xd7bd52e3, 0xff3fdf46, 0x68990899,
14487 0x5fa8b35d, 0x10a5f32c, 0x87d81728, 0x87923ecd, 0x276f5499, 0x9bd51678,
14488 0x02d7bb65, 0x6c3a7c3a, 0x76a11d86, 0x03db2491, 0x7cc894a6, 0x2c133ada,
14489 0xeca97e34, 0xe72a5897, 0x39c0bc01, 0x3ad0a254, 0x1e1cbafb, 0x02dd21e0,
14490 0x5efee7de, 0x543f7f33, 0x3a1e04e2, 0xfb411e1d, 0xe2052c20, 0xaf1fb94a,
14491 0xd722c133, 0x5fa9f353, 0x432fd178, 0x71d46278, 0x803db2ec, 0x0d4a6e71,
14492 0x8f805a65, 0x20279b6e, 0x9d62f1c7, 0xfb2f17e8, 0xb93acc85, 0xad03fbcd,
14493 0xacffec97, 0xf4376194, 0x4c43f12e, 0x2bd4f829, 0x539961f9, 0xa97083f2,
14494 0x1a1fcab0, 0x4a752cbf, 0xedcafc92, 0x78d29677, 0xafe718be, 0x7fce49e3,
14495 0x97e6e4aa, 0x512cdf10, 0x1fbff5fd, 0xfd2578bf, 0x7bbd5267, 0xf468df22,
14496 0xe347f8d1, 0xd23e6883, 0xb7a340f8, 0x7f345df6, 0x3455f345, 0x4bb02d3f,
14497 0x0f8e833a, 0x49f91329, 0x906874f9, 0x6769dfd7, 0x4fcd16bb, 0x35307cd1,
14498 0x4e7dc93f, 0xfd08a3e4, 0xcf2f8f81, 0xde6ec347, 0xa4fb66c7, 0x8ff1a47c,
14499 0x1f1a4fc6, 0x16223fdd, 0xcb535127, 0x9475eb98, 0xcffc727b, 0x8ab48f40,
14500 0xab33165b, 0xbe45cd38, 0x9efd8984, 0x5bdfa298, 0x501fc4b1, 0x2f73c23c,
14501 0x2e3381fc, 0x7ec5d8ab, 0x4251d7b6, 0xeaa45bf4, 0x9ba233d1, 0x8fb91ced,
14502 0x46b5d001, 0xc2a2f125, 0xd77fecd5, 0x2c7e8c38, 0x88fc232c, 0x17efd4db,
14503 0x0db7c9ff, 0x6a9c58eb, 0x536f6ff4, 0x455be3fd, 0x375f8f3f, 0xf0bdaa33,
14504 0x6f9bf656, 0x6fd633cb, 0x5efd5528, 0xcf4370b7, 0x5c8f08d6, 0x7ecdd89f,
14505 0x572a8d6b, 0x72fd2a59, 0x9f31665d, 0xfc2b58f0, 0xd7f72816, 0x62f3677e,
14506 0x80455bdc, 0x2088afe1, 0x108bb797, 0x1907738f, 0x0977c002, 0x69dc0561,
14507 0x91b6c91f, 0xfb37ad48, 0xf85f803f, 0x39fe59db, 0xc636c738, 0xcf20fbfa,
14508 0x6cefe2a7, 0x5be6807a, 0x0f28b654, 0x71ac9ddf, 0xd2753fb1, 0x1dfecb9e,
14509 0x129ac2e4, 0xc937cf91, 0xfd91e63e, 0x13f6453a, 0x9fb269e5, 0xdec76479,
14510 0xf809fb20, 0x02ad82b6, 0x29762ddf, 0xb7dba2c2, 0xceedfdf6, 0x6d32c245,
14511 0x7b74fb6a, 0xfa67f7f1, 0x4adf7f89, 0x1223539e, 0x60d65651, 0xa7256fbf,
14512 0x6319649b, 0xd5e8b2e3, 0x4ffcc9bc, 0xf322ff8d, 0xa6f9e62d, 0xd786b3c2,
14513 0x786a7c68, 0x7d7812fe, 0x3ebc3269, 0xced82253, 0x595fda8f, 0x5755b88f,
14514 0xde6fd4bc, 0x06441357, 0xa3c6eff1, 0x1bfd1cf2, 0xe313312c, 0xf7b53c4b,
14515 0xe42c28dc, 0x2bdc7f4a, 0xaaf3c002, 0x8fae6a9e, 0xf7898f8e, 0x6bf8616e,
14516 0xd9572f2a, 0xdde821fd, 0x6ba1a5cb, 0x1f12c3c8, 0xbc4bebef, 0xedf9e681,
14517 0xce0f664b, 0xd7669d27, 0xace20f6e, 0x2f3d996f, 0x9d3ffbe0, 0x724a5eca,
14518 0x369f9e25, 0xd3ac39e9, 0x9da8f12e, 0xe39dbec3, 0xce14b963, 0x23c80cb2,
14519 0x5f9829fd, 0x92665ff3, 0xfe27692f, 0xe59367dd, 0x454cfe54, 0x529fe91c,
14520 0x50facfee, 0xc77d1fa3, 0x538d1670, 0xeb26fa41, 0xaf3e38d1, 0xf7de9d78,
14521 0x08d50ed8, 0xc5afbf83, 0x25534623, 0x6b88171e, 0xb03c449e, 0x04558ce6,
14522 0x82147da9, 0x250cf68f, 0x7a35bd08, 0xfa19aae6, 0x114136b6, 0x542f60d3,
14523 0x6193127d, 0x3e9d2e12, 0x09c57588, 0xe38f8e97, 0x700c520b, 0xa1866782,
14524 0x8e55527f, 0x3bd93da1, 0xad3ed0d7, 0x4f00d4ae, 0xe860ddf7, 0xd0b0de9f,
14525 0x6ffa6700, 0xeacff433, 0x35806a58, 0xab25957d, 0x15eeacc4, 0xf767ef86,
14526 0x77f434ac, 0xda1ad607, 0xfb8971cd, 0xbc068f59, 0x4e3405c3, 0xee4e3a9d,
14527 0x7e868dce, 0xaa6dd082, 0xbfc89c80, 0xceeb1267, 0x3acf4428, 0xc87aaac7,
14528 0xd7ff7e69, 0xd734eb8d, 0xbca9925b, 0x7fd465d5, 0x784619b5, 0x4284e391,
14529 0x4e458b43, 0xeace1ea3, 0x8ce018b6, 0xd79bd232, 0x51628fd1, 0x2f82f1cc,
14530 0xae7fbfa2, 0x78d1fe81, 0x84f07e22, 0x69ec9fd0, 0xb37aeb00, 0x8f7b02d5,
14531 0x1f7e82fc, 0xf1e82fc8, 0x1e82fc80, 0xdf417e46, 0x7d05f91f, 0xfa0bf23b,
14532 0x4633b2f6, 0x1b0f97fa, 0x9ef95fe9, 0x5f1afe91, 0xeaa7454e, 0x843f91b0,
14533 0x7f2bf15f, 0x5e374e85, 0x344ff232, 0x37266e7d, 0xf4153927, 0xd7213c50,
14534 0x9dd7a797, 0xfa22f451, 0xf7c04c04, 0x9f4904cc, 0xa04975d0, 0xb319ed57,
14535 0x8ffc1208, 0xc77cfb51, 0x23286fe2, 0xab86f03d, 0xebfa0334, 0x147ae166,
14536 0x9dc5db71, 0x86884f26, 0x7e35115d, 0x7dff0cf5, 0x1a17a465, 0xb6cd5da6,
14537 0xfc463f81, 0xdc9e7073, 0xd9ddeaa5, 0xc0fc7271, 0x127cc142, 0xd839baf8,
14538 0x339ee347, 0xcfd02bf5, 0xb7f44fdf, 0x0bfbfbe3, 0xd47f79bb, 0xcdf7c143,
14539 0x0d931aff, 0xe0b679b8, 0x0c28b073, 0x88492f97, 0x2ce6c5e8, 0xd43b27aa,
14540 0xe39ea655, 0xdf4ed43c, 0xb8c99775, 0x69c7824e, 0xa15178e3, 0x444e22f0,
14541 0xe6ecafc7, 0x6ce3e022, 0x63e01cec, 0xde41e4c0, 0x25756c20, 0xde051f41,
14542 0xbde40b34, 0x9fc217e0, 0x57faa59b, 0x29e46259, 0x5ece73ac, 0xd7abb061,
14543 0x62c2ed06, 0x0d397fc8, 0x8650d170, 0xc7f5ffa1, 0x92f6865c, 0xbda18150,
14544 0x00c78cec, 0x19570f97, 0xe7be57fa, 0xe1d5c035, 0x1bff433a, 0xf00cf92f,
14545 0xef9e456c, 0x239653bf, 0x992e21f3, 0x387e6bdf, 0x6bfa5079, 0xf9afdcf2,
14546 0x49ffa2d5, 0x38711daf, 0xbf357f95, 0x6da3f35c, 0xcfd04084, 0xf6c2d3b6,
14547 0xfa5da660, 0xf62dfec9, 0x6827c8f3, 0x57e6bafe, 0x08a9fe6b, 0x76f57ad4,
14548 0xf693be87, 0x35ebf545, 0x8bf359ff, 0x4c5d8b13, 0xb236eb3f, 0x4b07e0ab,
14549 0xae761338, 0x1a4c4639, 0x4cb9790f, 0xd7a25b9e, 0x7a2badaf, 0xa762c4fe,
14550 0xdc7517e4, 0x7ee2ec17, 0xccfe24df, 0xf57caabf, 0x63beb99f, 0xad67cfe0,
14551 0xbb56f79e, 0xf4f3ebff, 0x1321fc25, 0xf5f352fe, 0x264dfd72, 0xc767c713,
14552 0xd72e5fd7, 0x0bf595af, 0xd921dfc9, 0x37e2f359, 0x1fc83af7, 0xc2c7b678,
14553 0xaf339671, 0xe40c6c5c, 0x5e121fc1, 0xfc9b338c, 0x3e07d07c, 0x0b07ce05,
14554 0xdf3ccdcb, 0x772932a5, 0xcf2cbd11, 0xd242a365, 0xc6c7b47f, 0xe849d479,
14555 0xeda07ccd, 0x8b43f107, 0x510dc655, 0xc9686e22, 0xc0437197, 0x44a21b88,
14556 0x2ff510dc, 0x3e187af7, 0xf0c55bd2, 0x0cbd7af7, 0xe3adeb1f, 0x3ebd07f2,
14557 0x26f8d7ae, 0x79da5f1a, 0xc43fa34b, 0x2f237610, 0x1feb1f8a, 0x6d72f492,
14558 0xd3f6fab0, 0xa24deb16, 0xe08d294e, 0x8f151ef3, 0x3c49e633, 0x7fe41fa0,
14559 0xe6b57eaa, 0x9bc424c2, 0xc92b8547, 0xaae257f9, 0x687c2f7f, 0x973f1f78,
14560 0x949bcb8e, 0x52e4a987, 0xceeb3f3b, 0xd1772cab, 0xb72d18f2, 0x3fe778d1,
14561 0xfc7bb9dd, 0x53c5ab5c, 0xe8d53954, 0x55b5c9a2, 0x5fa11b84, 0xce267982,
14562 0x609c3f53, 0xf3c5a394, 0x077f7e24, 0xbcf2a239, 0x326699cb, 0xfdb2f847,
14563 0x1017f271, 0x4869ef1f, 0x8059e0e4, 0x7dba8fce, 0xd2faf02e, 0x2b7ea06e,
14564 0xd062ac07, 0xb0757d85, 0x44096d1d, 0xd8471b9f, 0xaddb6c9f, 0x3e469f38,
14565 0xe7e4e77f, 0xd13fce4a, 0x6fc26d38, 0xfbdbbac3, 0xab56fd8d, 0xfce8cae7,
14566 0xd53cd54a, 0x878479de, 0x7f351ffd, 0x19f6a1de, 0x6e609fe7, 0x60df1a92,
14567 0x1432a479, 0xb9bf3ba3, 0x8b28ef90, 0xb8b784c0, 0x6dc3d802, 0x6bbe4f16,
14568 0x7869bf22, 0x97e7989b, 0xf7c41bf7, 0xa0fcf962, 0x232ff9e5, 0x6afa0fcf,
14569 0xffb514f9, 0x985980e5, 0x48e0df71, 0x7fa7e70c, 0x4f7b3a6b, 0x7f974b8e,
14570 0x11b79099, 0x309fb889, 0x27ba687a, 0xb4bac930, 0x1b361fd2, 0x684c91ee,
14571 0x11347adf, 0x17cec9e7, 0xf3a69e65, 0x796953c5, 0x3cd7bd3a, 0x1bfbc2cf,
14572 0xe7dbf932, 0x9bdc8f4d, 0x60c7fb58, 0x357aca31, 0x9fbd127e, 0x5f36bd71,
14573 0xa519fe61, 0xab5eb1fd, 0xa47f7853, 0x49e40517, 0x112fd7cb, 0x5a9454a1,
14574 0xb3bfc43e, 0xe5a0e99a, 0xd5425a43, 0xfbbb8fbc, 0xa8e35b56, 0x2da9f84b,
14575 0x48ae71b5, 0x4b3c249e, 0x2a99bfde, 0xac6cb25f, 0x3e5bc784, 0xb38f2376,
14576 0xe65b9e6d, 0xd9edb64f, 0xee6fff00, 0x1e056141, 0x4e3956c2, 0x553e9e34,
14577 0xdcb924e5, 0x6e37b7a8, 0x6f6f5855, 0xf796ad84, 0x6b6f587c, 0x157ed5f0,
14578 0xa6f095ae, 0x5b0e12ed, 0x24953b1d, 0x05c45fb9, 0xd8944fb0, 0x87b1ce0f,
14579 0xf60238d4, 0x40fb1281, 0x6015f43d, 0xd0c02be8, 0xafa18057, 0xa15f4250,
14580 0x65f0a57e, 0xbc888e23, 0x4e4e8d4e, 0xd1a9d790, 0xebc81ff9, 0x75e461e8,
14581 0xd791fdf4, 0xaf23b7d1, 0x5e476fa3, 0xaf230f47, 0xbc8fefa3, 0x5e461e8e,
14582 0x791fdf47, 0xbc8c3d1d, 0xf23fbe8e, 0xe476fa3a, 0xc8edf475, 0xe461e8eb,
14583 0x91fdf475, 0xdfb7d1d7, 0xf218a3df, 0x9a93f73e, 0xeeb5df06, 0x71fcc69d,
14584 0x313bedda, 0x41fbe88f, 0x66bf9ffc, 0x8f9d01cd, 0x6edf01af, 0x48f38aec,
14585 0x49d7f73a, 0xa4849bba, 0xd32348f3, 0xc24d8b79, 0xe7749eb5, 0xf20ffe24,
14586 0x99563529, 0x7c89414f, 0x53e44a0a, 0x529f2250, 0x29f32f93, 0x414f9128,
14587 0x2829f23d, 0x89414f91, 0xe44a0a7c, 0x9f225053, 0x14f91282, 0x0a7c877c,
14588 0x5053e44a, 0x4a0a7c8f, 0x7f5053e4, 0xbc81d68e, 0xf82eb68a, 0xf38679cb,
14589 0xe1a1f11c, 0xc034e73c, 0xfdf597f0, 0xdbeb2fe1, 0xdbeb2fe1, 0x61eb2fe1,
14590 0xfefacbf8, 0xb0f597f0, 0xe58b9e69, 0xfeb37e0c, 0x7acdf83b, 0x703fa8b8,
14591 0x3ba0b11a, 0x35eefdf6, 0xe504e194, 0xdf49c559, 0x15b7ff97, 0x638583c8,
14592 0x0f64ec95, 0x0fadbfd9, 0xd821a8ad, 0x2ba7deaf, 0xd0262316, 0x44d8f39b,
14593 0x04487f37, 0xe8a08f71, 0xd76e4cf3, 0x47fcaaf2, 0x22392f74, 0x535f0fd8,
14594 0x7da5d724, 0x334e11ef, 0x047fad4a, 0xf45fbc9e, 0xd63f5afc, 0x9075ba97,
14595 0xfdc12c9d, 0x8e2d9286, 0x4fc45dd2, 0xfb0a4c07, 0x9fc807a1, 0x5e893a5a,
14596 0xa3fd50aa, 0x27c3a603, 0xa22f70e3, 0xa7ecf145, 0x88b1afa1, 0xe052d633,
14597 0xfe14bba9, 0xb2797642, 0xdf75afea, 0xda3f7b80, 0x1db8b5ba, 0xf22f09e9,
14598 0x8447f3ef, 0xb9e68dad, 0x6b6153e9, 0x9366df87, 0xc3be02fe, 0x80baedb9,
14599 0xe3afdde2, 0x697282ef, 0x0d81fcff, 0xfd51b437, 0x6fba8775, 0x171f8768,
14600 0xcefbbf27, 0xc78c8973, 0xfb29b73b, 0xf99fb4cd, 0x90778487, 0xcb9495fa,
14601 0x8775dff3, 0x9e36b69c, 0xd76b69d7, 0x97d843df, 0x5ce1736d, 0x8835c228,
14602 0x8a7989ff, 0xf0444178, 0x0d7bfb46, 0x4486bbfb, 0x75d7f105, 0x3ffb6307,
14603 0xd751f1d2, 0x7e01b250, 0xff6658e0, 0x59fe3a47, 0x72441f87, 0xec206e41,
14604 0xf24aa756, 0xc3bd6af5, 0x79c51be4, 0x623ecba2, 0x9a6efe03, 0x7b8b5c97,
14605 0xf0b8e26c, 0xe6ef83e4, 0x4e9f6cb5, 0xbd07f2eb, 0xba03dc1e, 0xd3eed3e9,
14606 0x63ef3f0c, 0x82a7d998, 0x70f6c7d7, 0xc509404e, 0x0cee2a13, 0x09529a0c,
14607 0xd5b023be, 0x87fe869a, 0x00ee0784, 0xa0b12899, 0x42afb234, 0x558a6c31,
14608 0xd4e22fc0, 0x91ff1d34, 0x7e0e58e6, 0x0558f129, 0xc58963f8, 0x89be8569,
14609 0xefa237f6, 0x71ff907f, 0x6867bcaf, 0x6b1ec0b5, 0x538b51fe, 0x36eaf5ae,
14610 0x2d1ffb2b, 0xd0ffc947, 0xfcd52bdd, 0x085eed0d, 0x109e1df9, 0xdb91f8ec,
14611 0xb9d42e39, 0x7fbe1de1, 0x783b89f1, 0xfaf89920, 0xf7c39c93, 0xb7e1b954,
14612 0xc94fac28, 0x272ce86f, 0x3f6cb63c, 0x55f3889d, 0xfb0af038, 0x3db7571b,
14613 0x08e3289e, 0xa6d11f32, 0xcf8b49e2, 0x68f4abb4, 0x7d01ef53, 0x3bcb7a48,
14614 0x086eed87, 0xbd6836f7, 0xfb4457ec, 0xb91f9a87, 0x384f1b4e, 0xa45c45df,
14615 0x8bb7f683, 0x5bbbd5a0, 0x89886476, 0xd53ae3fe, 0xcdb35caf, 0x3a7ef7ca,
14616 0xc2ed9044, 0x3f54609a, 0xbacfbef5, 0x9dfac683, 0xa7fe51e5, 0xeed22e7a,
14617 0x7dbcb6e5, 0x7ff66eea, 0x6f9cadba, 0xfd2ada6b, 0x04587121, 0x8bc015f3,
14618 0x3704b14c, 0x947af51d, 0x27e7f849, 0x1f545faa, 0x2ebc658e, 0x7d678b19,
14619 0x8b2c74b2, 0x32c67be1, 0x4c77bcb9, 0x8a5c8bde, 0x3bd10c58, 0x9104ab5c,
14620 0xea99fb4f, 0x7b8ddd0f, 0x2063a092, 0x9479f99d, 0x145319f8, 0xae6a7aab,
14621 0x77053957, 0xdfeadeb3, 0xf5987b8e, 0xcbfd8283, 0xd137e03b, 0xa3f00df8,
14622 0xdc1e41a6, 0xb73f7cb5, 0x6ef9114e, 0x9506c3c8, 0x041e49ff, 0xeb2f0feb,
14623 0x41259ab5, 0xf069afdc, 0xee81361f, 0x03f81c9a, 0xef802de7, 0x57362808,
14624 0xf8279f21, 0x79f1acbc, 0xc7343cb4, 0x8725f1ab, 0xfb8d1f8c, 0x9d2c58a7,
14625 0xd7e045bb, 0xded4bc2b, 0x0ce0188c, 0xf7081195, 0xfdb28509, 0xaf5fd1e4,
14626 0xd3c386d8, 0x343f8c97, 0xaf4c4c99, 0xf6f7f211, 0x70c56043, 0x65e43a6d,
14627 0xcbba52b7, 0x53cf5915, 0x572f0b95, 0x2bc5cee8, 0xf922f955, 0x63f9c74b,
14628 0xe9f923e3, 0x40ff1262, 0xcf095b2b, 0xa4e6b390, 0xa214d7f0, 0xc2e527cc,
14629 0xdb0c435b, 0xe27dd428, 0x73ad0422, 0x7c670a85, 0x9dfdee2f, 0x861f8c85,
14630 0x5e5f962f, 0xbffc2811, 0x8a4d87d0, 0xab57ef85, 0xfc9871f8, 0xefc3951f,
14631 0x831787b7, 0x2385f1ae, 0x1a2dd036, 0x1eedf73f, 0xf08733da, 0xe9215190,
14632 0xb7eb64d7, 0x045179f2, 0xb55f88ad, 0x22fb4a16, 0xafecae2c, 0xc5c43e72,
14633 0xdf6d3e71, 0x89f7aa1f, 0xace1f1a3, 0x7e027690, 0xf48e6bb2, 0x4fc25193,
14634 0xf81c7dc6, 0x27e180c9, 0x8c9f84a3, 0x80c9f87a, 0x860327e1, 0x7e180c9f,
14635 0xc9f84a32, 0xe4c27fa8, 0xd130ff3d, 0xf05369f3, 0xa7c4abf0, 0x4dfaa59f,
14636 0xa7feb415, 0xd79b8f71, 0x11fde7ef, 0x195eb0df, 0x5fc453d7, 0x1f088af6,
14637 0x70b9ecad, 0xe11394d4, 0xbf9db6a7, 0xe205ea7f, 0x17e4958f, 0x3bfd9e42,
14638 0xf14c5095, 0xdcf67cd4, 0x979638da, 0x636ebee7, 0x1b64dbfd, 0x47776d3e,
14639 0xcf7ef9f0, 0x7d4ab4ff, 0xd177ca19, 0x63ba2bb8, 0x4fffd03d, 0xb1d2fa55,
14640 0x0f42f8de, 0xad32e5d3, 0x251def89, 0xbf50b3fa, 0x9ebf0c52, 0xbf9afd41,
14641 0xda3676f1, 0xb6ee381f, 0x1cb70f41, 0xe191d92b, 0x177ef7c2, 0xe1c5b5f8,
14642 0x58cfc1b4, 0xed992dbf, 0x8cba736e, 0x73c712db, 0x47a34bde, 0xb78c8555,
14643 0xb829527d, 0x979ea2bc, 0x25d64108, 0x6e927e86, 0xc5a6f2d1, 0x58e3a311,
14644 0xf3ca7891, 0x0710733b, 0x3e9e1549, 0x217c44d7, 0x8d2b61ce, 0xe3a251c4,
14645 0x6af2e31d, 0x9df88613, 0x50a9ae56, 0xdbcef70c, 0x85abcfc7, 0xd7e1d38b,
14646 0x1138a63f, 0xb8736e6f, 0xb826adee, 0x37158ced, 0x8a7d4532, 0xf04996cb,
14647 0x738a23c8, 0xb9bde83f, 0x1356f584, 0xf78a5268, 0xb72cd50b, 0xcb2a416d,
14648 0xafef96a6, 0xd66a763e, 0x90afb1f7, 0xb67586d7, 0x14b6bd39, 0xdad3df9d,
14649 0xf7f578af, 0xb1b83520, 0x9b0dc642, 0xfc0118e8, 0x6dd9b7dd, 0x2538895b,
14650 0xffb83fb9, 0x13e546b7, 0xc7ea3bed, 0x73ea1ff7, 0xabe0ebc4, 0xf417da11,
14651 0xd52be616, 0xe312bf8d, 0xfea7e6eb, 0x56b5b7ec, 0x2d78f024, 0x1bb7da4e,
14652 0x49d793a5, 0x8d3c6078, 0x5cf1a1ec, 0xbde30f3c, 0x7ab41435, 0xbbdc1eb0,
14653 0x33857820, 0x2b3cc568, 0x7c7095b7, 0xce5bbfdf, 0x6c99dfe3, 0x675f822b,
14654 0xe966da71, 0x3be23dfd, 0x0e1365f0, 0x5ebca9f7, 0x08db87f6, 0x43f0294f,
14655 0x75ffc853, 0x8b57c44c, 0xfeb6feba, 0xd8ffa364, 0xf41598ff, 0x4aed5469,
14656 0x549e1d34, 0xb6e578f9, 0xd7786c5b, 0xf2f166d0, 0x8abf07bb, 0x10df7fef,
14657 0x90f90bbb, 0xad2781c6, 0xae1f826e, 0x93f67e90, 0xeadf9215, 0xb8f94273,
14658 0x21b231e7, 0x3721ef96, 0xbf79fb3a, 0x9c7ef8e3, 0xc4ff03f0, 0x137c63e9,
14659 0x9f70049f, 0x48c06daf, 0x127ac8df, 0x81b6dc78, 0x55bf9616, 0xa9cdbf16,
14660 0x13dec75f, 0xa5e10af9, 0x815ee491, 0xb3fa71fd, 0x1f173fc1, 0xf79b37bf,
14661 0x7be4eb49, 0xe2d71e54, 0x37cc798c, 0xff1ad7cc, 0x79499734, 0xa97be6d6,
14662 0xbdf3c2c2, 0xb4e525f4, 0xdf0b776d, 0x10cd6983, 0x62f9451e, 0x53e4d539,
14663 0x3546d793, 0x7bbad92e, 0xf4ebf089, 0xeeefd90d, 0xcfc12797, 0x2b9d7565,
14664 0x3e127a54, 0xb8ba135f, 0x3d2abbdd, 0x728c729b, 0xee30f18f, 0x9bee5529,
14665 0x37f28616, 0x6bfa4614, 0xc8a536f3, 0xe0ffc0ef, 0xbd2a53b3, 0xf7237fd1,
14666 0xeaa4f157, 0xbd71d68d, 0x1a7b6871, 0x8561c6f4, 0xf71b54f3, 0xe36ebf48,
14667 0xe71c098b, 0xaf8d8ffa, 0xea1ef8fe, 0x8313c9f7, 0x13f7facd, 0x27a9216d,
14668 0x829fc9da, 0xdaa558de, 0xff6286fd, 0x72742b4f, 0x17adf6dc, 0xac5c81af,
14669 0xf8b92a18, 0x0efbc14b, 0xeafcdf41, 0x73be1fc5, 0x5f622b83, 0xdcac7db5,
14670 0x16d66ff9, 0x726f1e87, 0x560abb9f, 0x493cef0a, 0x5ac39c2f, 0x1df229b7,
14671 0xfd8d8f59, 0xd1de8d4f, 0xf242d07c, 0xf088eadb, 0xa9ff4681, 0x78db26fc,
14672 0x5fd24e3e, 0x07c6b7a3, 0x3a35bd1a, 0x9d297bf1, 0xfbadafff, 0x2b5e9533,
14673 0x531dfe54, 0x87456ee5, 0xe58ab6db, 0x056b6ddd, 0xb1fa6bdf, 0x4e3f58cd,
14674 0x7eb8e727, 0xc0b901df, 0x69d022bb, 0xc655b774, 0xa04d0f23, 0xbeec3653,
14675 0x6ad58eb6, 0x8d5db1dc, 0xfcd2ae1f, 0x4c7f62e0, 0xab4e8ea5, 0x6a74939f,
14676 0x5fede97d, 0xfbc5c0ff, 0x4f6c7a93, 0x2b8bfb0c, 0xbd330e87, 0x663e771a,
14677 0xf4bf5375, 0x5f41b74a, 0x389776b7, 0xb15f3711, 0xf90ad073, 0x4d74af4f,
14678 0xea4defca, 0xaf0d60bd, 0xce8a3fb0, 0xa1fd69ee, 0x3cd30ef7, 0x26c4379b,
14679 0x368d1ee2, 0xf252b78f, 0x72776b75, 0xed6be60a, 0x381ff96e, 0x3f7a68cf,
14680 0xc42eee5a, 0x4958794a, 0x2f2e429f, 0xdec9e2dc, 0x3f313858, 0x959595a6,
14681 0x10cf6e92, 0x256f717a, 0xbbe87e2b, 0x03d643c0, 0x93e41e71, 0x41c2f2f3,
14682 0xc63e0bcc, 0x17a46dba, 0xaf25ff71, 0xac7bfc33, 0xbe745c83, 0x213282ef,
14683 0xd23be645, 0x926fde08, 0xcc72b3ef, 0x52afbcb2, 0x0f6a3bda, 0x86a45da1,
14684 0x68ffb1cb, 0x5f9535bd, 0x36a7f1a1, 0x9a9eb44e, 0x57777f6a, 0xa2fa794a,
14685 0xab705dfd, 0x4f029371, 0x6de69db6, 0x078e747e, 0xda2fa471, 0xe64e2da7,
14686 0x4bf7c697, 0x32955acc, 0xe4f37ec9, 0xfdea6839, 0x4da6d40e, 0x7909dfb2,
14687 0xb44e555f, 0x79e3efbb, 0x27997e92, 0xdd90a0b9, 0x6c2eefa2, 0x65fbe588,
14688 0x38b4beda, 0x5efadffd, 0x14cac1e1, 0x4e14fe35, 0x14d93f80, 0x487fcaa7,
14689 0xa25fa8c2, 0xfdecd7ab, 0x21386739, 0x3f9fa745, 0xa1ed56ea, 0x3c81ef08,
14690 0x815c9e8b, 0xfeb9c778, 0x42a6090b, 0x9f5ca7f0, 0xab66ddf6, 0xf40f5ce7,
14691 0xbe18f6dc, 0xd37e4eef, 0xda93c40e, 0xa71cc903, 0xeca7afb9, 0xe71a5ee2,
14692 0xfc596dbe, 0xf3f350de, 0x2ffaa957, 0x8ecb737e, 0xebdff44a, 0x6f8fc276,
14693 0x886cf877, 0x2c0fc5c3, 0xdfb0e5b1, 0x5a01cf2b, 0x22b36ade, 0x0c9efc7c,
14694 0x657211fa, 0x7b07913a, 0xf4af7ab3, 0x624debff, 0xb39bf227, 0x338b7cfb,
14695 0x529e1fa1, 0xc527f03c, 0xdaa3d23e, 0xc7748c79, 0x6fbec587, 0xef68bf41,
14696 0xc6c2e6ef, 0x219fb19a, 0x829dce2f, 0x07ec0bfc, 0xa65e01eb, 0x6e71fca9,
14697 0xab827ce0, 0x2fcf8230, 0xe3481efb, 0xd67f2d0b, 0x194ff88e, 0x0d29a3f8,
14698 0xe6a6d1fc, 0x2c0c76c9, 0x707db862, 0xe9fbbf19, 0x473a6743, 0xfb563db6,
14699 0xef08a044, 0xda3e2578, 0x09dd16ba, 0x7f63a8bf, 0x35ce324c, 0xb640d6d9,
14700 0x1b6d0fde, 0x01df987c, 0xe58c1a5d, 0xce354077, 0x67b83525, 0x7c9f6ab3,
14701 0x3bf5a767, 0xb597eaa1, 0xef0c8b5d, 0x4c69da79, 0xd9ff8d27, 0x5fdf3c50,
14702 0x04e9ded3, 0x95e3feec, 0x4ebdf2e5, 0xd3be4bb5, 0xaefee4c9, 0x5af4e349,
14703 0xbe57b179, 0x3bbdd0fb, 0xbe91b3ba, 0x257aecef, 0x7bace311, 0x4e1567fc,
14704 0xceb7c713, 0x77f1fc60, 0xbbe57b47, 0x27c7f6a3, 0xbe03ff7f, 0x1c767f06,
14705 0xc6790c53, 0xec4982fb, 0xc243fa87, 0xdfb6fc86, 0xbdcfd829, 0xb03d1664,
14706 0xa25f9aeb, 0xc552ffd5, 0xfea4a5c3, 0xcd7fd06c, 0x61b32781, 0x20937e37,
14707 0xf703a6e1, 0xc87a08fe, 0xf48c7cff, 0xfd822dbf, 0xf480d6db, 0x64f7b597,
14708 0x38ec7842, 0x19547f87, 0x46b9f2cf, 0xada4977d, 0xae0bfc8b, 0xd4458dff,
14709 0x6f781d61, 0xdf7e7e04, 0x3d076a12, 0x147f27df, 0x2a138f79, 0x6fdfbdff,
14710 0x87f7cc5e, 0x57e01048, 0x4affdfbc, 0x9a89f202, 0xfe6b561f, 0xb4ef1795,
14711 0xef951e37, 0x870be381, 0xd4231cf9, 0xa77ac978, 0xdf8db7e4, 0x4ace2eb7,
14712 0x6b8abf65, 0xdb212d3a, 0xab5af464, 0xf0e34dfa, 0x2e7cc391, 0xfd243ceb,
14713 0xf3a1ce82, 0x7e6817ec, 0x70bef686, 0xecf3a1dd, 0xaddf6827, 0xd2f1223f,
14714 0xb7d64475, 0x78b49814, 0xc3c9578b, 0x38615979, 0xb4d2c2bf, 0x9b9b00d5,
14715 0x3a505ab6, 0x08c878d5, 0x0abbe5fb, 0x99e7ca7e, 0xb8ea6dae, 0xf3755b04,
14716 0x974d56c5, 0x3ea8daef, 0xa5ef81d7, 0xbbdad73d, 0x50f3c88e, 0x276e2ba8,
14717 0xef5d83df, 0xebeca0b0, 0xdf3db072, 0xc02a6dd7, 0x12af757d, 0x71dcfec7,
14718 0xf4d6fef5, 0x22c6ef75, 0x4629904e, 0x7cdc994e, 0x15666b6f, 0x022e9b8d,
14719 0x7b4b8f7c, 0x9fe5744f, 0xf8c32e3f, 0xafc2620b, 0x5b980220, 0x7909a335,
14720 0xe1490593, 0xf73c6032, 0xd384ba58, 0x0e20afc3, 0x37240ce5, 0xa5f28f21,
14721 0x8af54ae3, 0x30eece21, 0x0a07aff9, 0xdb2ec6ba, 0xc4635c64, 0x5799b906,
14722 0xfa68f925, 0xe2473a49, 0x83b9f51c, 0xd3e981cf, 0x9b9df9ba, 0xa1970c28,
14723 0x837c71df, 0x8c7f60fb, 0x420eff93, 0xf6f5979e, 0x027558c6, 0x3de99797,
14724 0xa425aeaa, 0x9f0363e6, 0xf7f8829b, 0xa12b8e04, 0xbcfdeb6f, 0x4f292aee,
14725 0x979918be, 0xceb14bbd, 0xe4fa27fa, 0x835fdb90, 0xcc72fa75, 0xb8b92545,
14726 0x7def2b17, 0xb7f3515f, 0x50bcbf9a, 0x7a96769d, 0xc8cdb3ce, 0xb4fe4070,
14727 0xd78a89fb, 0x1f52efcb, 0x8ad93c2a, 0xc4737f75, 0x1620efce, 0x73c9c48e,
14728 0xb63a8cd5, 0xd9b17daf, 0x2e283fec, 0xfea2688b, 0x214d0b27, 0xa6ffdfdc,
14729 0x599e73b0, 0x6dfca3d8, 0xc3df2c53, 0xf1bf8e56, 0x964dec39, 0x92a7f7f9,
14730 0xff599f68, 0x8ba078a0, 0xfe2f479b, 0x6ca84fe3, 0x187fdb1a, 0xfe4911fb,
14731 0xb9c3f066, 0x7ef3bad1, 0x9d37f542, 0xb48f7643, 0x8fbf4263, 0x9e7e0fe3,
14732 0xac8a6298, 0xc5c8caef, 0x879d5f17, 0xe9f1ced2, 0x32cdc785, 0x9eb5159e,
14733 0xbe2e192b, 0x98fd4e0f, 0xa61c573e, 0x0b87ce20, 0x0f7a9f8f, 0x7b885beb,
14734 0xd83738ce, 0xf6f597ad, 0x2566b84e, 0x150e7e23, 0x88ac97fa, 0xb540783e,
14735 0xae7d694b, 0x7b08dc9f, 0x2059a6f9, 0x651440ee, 0x07d6883e, 0x425f833f,
14736 0xaa37c6fe, 0x07ed79e4, 0x546fbe39, 0x67065cb1, 0x9be72e41, 0xb69fbf27,
14737 0xe3514aaf, 0xd1ae9259, 0x8ba68b74, 0xe7716f86, 0x8524e9f0, 0xa8f45cf1,
14738 0xc62eefc4, 0xb767e7ef, 0x198a9893, 0xc636fbff, 0xf86ffff3, 0xca7de2fd,
14739 0xfbe373f7, 0xd3ed3afc, 0x77e7d86d, 0x93ed1ffe, 0xbcdfc0f5, 0x3ee361cf,
14740 0xb142fad3, 0x8f37c073, 0x8acfd89b, 0x0a2a37be, 0x66d1eb04, 0x53c71c73,
14741 0xddf271fd, 0xd3cfe901, 0xde9a9fd0, 0x2e175d9c, 0x4e71bf82, 0xaeb16788,
14742 0xeb8869b0, 0x30e5562f, 0xc314ccdf, 0xc27efc99, 0x3f872e12, 0x35bfb66b,
14743 0x4bb223f7, 0x0f048f03, 0xf4e34abf, 0x56a7c129, 0xeddd5f41, 0x95dcfce0,
14744 0xa56029a0, 0x45920679, 0x7f9a31f1, 0xce5ccd60, 0xaa115cb3, 0xb1b06a9e,
14745 0xecf6a29e, 0xca37b41e, 0xf9fdeff6, 0xa3f81ec2, 0xf782f923, 0xae225033,
14746 0xc0f04bd9, 0xff6e0292, 0xf6e7a6a1, 0x97efc824, 0x8193e608, 0xef7c2935,
14747 0x83a7e9e4, 0x0e8ec2d7, 0x11337a0c, 0xf44cab57, 0x19c74187, 0x079f6966,
14748 0xe54f54dc, 0xb1af8a13, 0xc914e31d, 0xe31b86f5, 0x43403a5e, 0x2a91e6c5,
14749 0x3d73faa5, 0xd5cf9c09, 0x638b47e4, 0x7f9c0ecf, 0xded2780a, 0xf2a07f23,
14750 0xc5778699, 0xa667df2b, 0xe8d678aa, 0x6a5bf1a0, 0xa6cf7c9c, 0x377c916c,
14751 0xbd791f7e, 0x33c8fbe0, 0x27782969, 0x71e31cd7, 0x4adfdf01, 0xfd618ff2,
14752 0x3e881b7d, 0xd243ec66, 0x5bde1ce1, 0x997fe24e, 0x7e5a4dab, 0x3463df9f,
14753 0x9a5fa90b, 0x3d17f7b5, 0x2217f7c6, 0xef19333c, 0xe89f9891, 0x3edd67fb,
14754 0x5fbe355b, 0xd2fb65ee, 0xd9def2ac, 0x7a4f34ff, 0x5aa9286f, 0x623b95da,
14755 0x9dfc89fd, 0xf3450efa, 0x7c96cfc3, 0xe4f60b3c, 0xcc6f83dc, 0xa2577944,
14756 0xf69ab92f, 0x1fe344f3, 0x7dc4c316, 0xf7e61990, 0xfe341f34, 0xe5c71671,
14757 0xfcc1bcb7, 0x57aeb7ff, 0x01ffc75b, 0x0934e170, 0x000048d0
6366}; 14758};
6367 14759
6368#endif /*__BNX2X_INIT_VALUES_H__*/ 14760#endif /*__BNX2X_INIT_VALUES_H__*/
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
new file mode 100644
index 000000000000..ff2743db10d9
--- /dev/null
+++ b/drivers/net/bnx2x_link.c
@@ -0,0 +1,4527 @@
1/* Copyright 2008 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/pci.h>
20#include <linux/netdevice.h>
21#include <linux/delay.h>
22#include <linux/ethtool.h>
23#include <linux/mutex.h>
24#include <linux/version.h>
25
26#include "bnx2x_reg.h"
27#include "bnx2x_fw_defs.h"
28#include "bnx2x_hsi.h"
29#include "bnx2x_link.h"
30#include "bnx2x.h"
31
32/********************************************************/
33#define SUPPORT_CL73 0 /* Currently no */
34#define ETH_HLEN 14
35#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
36#define ETH_MIN_PACKET_SIZE 60
37#define ETH_MAX_PACKET_SIZE 1500
38#define ETH_MAX_JUMBO_PACKET_SIZE 9600
39#define MDIO_ACCESS_TIMEOUT 1000
40#define BMAC_CONTROL_RX_ENABLE 2
41#define MAX_MTU_SIZE 5000
42
43/***********************************************************/
44/* Shortcut definitions */
45/***********************************************************/
46
47#define NIG_STATUS_XGXS0_LINK10G \
48 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
49#define NIG_STATUS_XGXS0_LINK_STATUS \
50 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
51#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
52 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
53#define NIG_STATUS_SERDES0_LINK_STATUS \
54 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
55#define NIG_MASK_MI_INT \
56 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
57#define NIG_MASK_XGXS0_LINK10G \
58 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
59#define NIG_MASK_XGXS0_LINK_STATUS \
60 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
61#define NIG_MASK_SERDES0_LINK_STATUS \
62 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
63
64#define MDIO_AN_CL73_OR_37_COMPLETE \
65 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
66 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
67
68#define XGXS_RESET_BITS \
69 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
71 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
72 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
73 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
74
75#define SERDES_RESET_BITS \
76 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
77 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
78 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
79 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
80
81#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
82#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
83#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
84#define AUTONEG_PARALLEL \
85 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
86#define AUTONEG_SGMII_FIBER_AUTODET \
87 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
88#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
89
90#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
91 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
92#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
93 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
94#define GP_STATUS_SPEED_MASK \
95 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
96#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
97#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
98#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
99#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
100#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
101#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
102#define GP_STATUS_10G_HIG \
103 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
104#define GP_STATUS_10G_CX4 \
105 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
106#define GP_STATUS_12G_HIG \
107 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
108#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
109#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
110#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
111#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
112#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
113#define GP_STATUS_10G_KX4 \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
115
116#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
117#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
118#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
119#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
120#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
121#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
122#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
123#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
124#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
125#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
126#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
127#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
128#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
129#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
130#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
131#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
132#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
133#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
134#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
135#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
136#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
137#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
138#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
139
140#define PHY_XGXS_FLAG 0x1
141#define PHY_SGMII_FLAG 0x2
142#define PHY_SERDES_FLAG 0x4
143
144/**********************************************************/
145/* INTERFACE */
146/**********************************************************/
147#define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
148 bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \
149 DEFAULT_PHY_DEV_ADDR, \
150 (_bank + (_addr & 0xf)), \
151 _val)
152
153#define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
154 bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \
155 DEFAULT_PHY_DEV_ADDR, \
156 (_bank + (_addr & 0xf)), \
157 _val)
158
159static void bnx2x_set_phy_mdio(struct link_params *params)
160{
161 struct bnx2x *bp = params->bp;
162 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
163 params->port*0x18, 0);
164 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
165 DEFAULT_PHY_DEV_ADDR);
166}
167
168static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
169{
170 u32 val = REG_RD(bp, reg);
171
172 val |= bits;
173 REG_WR(bp, reg, val);
174 return val;
175}
176
177static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
178{
179 u32 val = REG_RD(bp, reg);
180
181 val &= ~bits;
182 REG_WR(bp, reg, val);
183 return val;
184}
185
186static void bnx2x_emac_init(struct link_params *params,
187 struct link_vars *vars)
188{
189 /* reset and unreset the emac core */
190 struct bnx2x *bp = params->bp;
191 u8 port = params->port;
192 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
193 u32 val;
194 u16 timeout;
195
196 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
197 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
198 udelay(5);
199 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
200 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
201
202 /* init emac - use read-modify-write */
203 /* self clear reset */
204 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
205 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
206
207 timeout = 200;
208 do
209 {
210 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
211 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
212 if (!timeout) {
213 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
214 return;
215 }
216 timeout--;
217 }while (val & EMAC_MODE_RESET);
218
219 /* Set mac address */
220 val = ((params->mac_addr[0] << 8) |
221 params->mac_addr[1]);
222 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
223
224 val = ((params->mac_addr[2] << 24) |
225 (params->mac_addr[3] << 16) |
226 (params->mac_addr[4] << 8) |
227 params->mac_addr[5]);
228 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
229}
230
231static u8 bnx2x_emac_enable(struct link_params *params,
232 struct link_vars *vars, u8 lb)
233{
234 struct bnx2x *bp = params->bp;
235 u8 port = params->port;
236 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
237 u32 val;
238
239 DP(NETIF_MSG_LINK, "enabling EMAC\n");
240
241 /* enable emac and not bmac */
242 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
243
244 /* for paladium */
245 if (CHIP_REV_IS_EMUL(bp)) {
246 /* Use lane 1 (of lanes 0-3) */
247 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
248 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
249 port*4, 1);
250 }
251 /* for fpga */
252 else
253
254 if (CHIP_REV_IS_FPGA(bp)) {
255 /* Use lane 1 (of lanes 0-3) */
256 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
257
258 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
259 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
260 0);
261 } else
262 /* ASIC */
263 if (vars->phy_flags & PHY_XGXS_FLAG) {
264 u32 ser_lane = ((params->lane_config &
265 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
266 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
267
268 DP(NETIF_MSG_LINK, "XGXS\n");
269 /* select the master lanes (out of 0-3) */
270 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
271 port*4, ser_lane);
272 /* select XGXS */
273 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
274 port*4, 1);
275
276 } else { /* SerDes */
277 DP(NETIF_MSG_LINK, "SerDes\n");
278 /* select SerDes */
279 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
280 port*4, 0);
281 }
282
283 /* enable emac */
284 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
285
286 if (CHIP_REV_IS_SLOW(bp)) {
287 /* config GMII mode */
288 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
289 EMAC_WR(EMAC_REG_EMAC_MODE,
290 (val | EMAC_MODE_PORT_GMII));
291 } else { /* ASIC */
292 /* pause enable/disable */
293 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
294 EMAC_RX_MODE_FLOW_EN);
295 if (vars->flow_ctrl & FLOW_CTRL_RX)
296 bnx2x_bits_en(bp, emac_base +
297 EMAC_REG_EMAC_RX_MODE,
298 EMAC_RX_MODE_FLOW_EN);
299
300 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
301 EMAC_TX_MODE_EXT_PAUSE_EN);
302 if (vars->flow_ctrl & FLOW_CTRL_TX)
303 bnx2x_bits_en(bp, emac_base +
304 EMAC_REG_EMAC_TX_MODE,
305 EMAC_TX_MODE_EXT_PAUSE_EN);
306 }
307
308 /* KEEP_VLAN_TAG, promiscuous */
309 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
310 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
311 EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
312
313 /* Set Loopback */
314 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
315 if (lb)
316 val |= 0x810;
317 else
318 val &= ~0x810;
319 EMAC_WR(EMAC_REG_EMAC_MODE, val);
320
321 /* enable emac for jumbo packets */
322 EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE,
323 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
324 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
325
326 /* strip CRC */
327 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
328
329 /* disable the NIG in/out to the bmac */
330 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
331 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
332 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
333
334 /* enable the NIG in/out to the emac */
335 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
336 val = 0;
337 if (vars->flow_ctrl & FLOW_CTRL_TX)
338 val = 1;
339
340 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
341 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
342
343 if (CHIP_REV_IS_EMUL(bp)) {
344 /* take the BigMac out of reset */
345 REG_WR(bp,
346 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
347 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
348
349 /* enable access for bmac registers */
350 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
351 }
352
353 vars->mac_type = MAC_TYPE_EMAC;
354 return 0;
355}
356
357
358
359static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
360 u8 is_lb)
361{
362 struct bnx2x *bp = params->bp;
363 u8 port = params->port;
364 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
365 NIG_REG_INGRESS_BMAC0_MEM;
366 u32 wb_data[2];
367 u32 val;
368
369 DP(NETIF_MSG_LINK, "Enabling BigMAC\n");
370 /* reset and unreset the BigMac */
371 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
372 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
373 msleep(1);
374
375 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
376 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
377
378 /* enable access for bmac registers */
379 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
380
381 /* XGXS control */
382 wb_data[0] = 0x3c;
383 wb_data[1] = 0;
384 REG_WR_DMAE(bp, bmac_addr +
385 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
386 wb_data, 2);
387
388 /* tx MAC SA */
389 wb_data[0] = ((params->mac_addr[2] << 24) |
390 (params->mac_addr[3] << 16) |
391 (params->mac_addr[4] << 8) |
392 params->mac_addr[5]);
393 wb_data[1] = ((params->mac_addr[0] << 8) |
394 params->mac_addr[1]);
395 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
396 wb_data, 2);
397
398 /* tx control */
399 val = 0xc0;
400 if (vars->flow_ctrl & FLOW_CTRL_TX)
401 val |= 0x800000;
402 wb_data[0] = val;
403 wb_data[1] = 0;
404 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
405 wb_data, 2);
406
407 /* mac control */
408 val = 0x3;
409 if (is_lb) {
410 val |= 0x4;
411 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
412 }
413 wb_data[0] = val;
414 wb_data[1] = 0;
415 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
416 wb_data, 2);
417
418
419 /* set rx mtu */
420 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
421 wb_data[1] = 0;
422 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
423 wb_data, 2);
424
425 /* rx control set to don't strip crc */
426 val = 0x14;
427 if (vars->flow_ctrl & FLOW_CTRL_RX)
428 val |= 0x20;
429 wb_data[0] = val;
430 wb_data[1] = 0;
431 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
432 wb_data, 2);
433
434 /* set tx mtu */
435 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
436 wb_data[1] = 0;
437 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
438 wb_data, 2);
439
440 /* set cnt max size */
441 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
442 wb_data[1] = 0;
443 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
444 wb_data, 2);
445
446 /* configure safc */
447 wb_data[0] = 0x1000200;
448 wb_data[1] = 0;
449 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
450 wb_data, 2);
451 /* fix for emulation */
452 if (CHIP_REV_IS_EMUL(bp)) {
453 wb_data[0] = 0xf000;
454 wb_data[1] = 0;
455 REG_WR_DMAE(bp,
456 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
457 wb_data, 2);
458 }
459
460 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
461 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
462 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
463 val = 0;
464 if (vars->flow_ctrl & FLOW_CTRL_TX)
465 val = 1;
466 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
467 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
468 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
469 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
470 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
471 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
472
473 vars->mac_type = MAC_TYPE_BMAC;
474 return 0;
475}
476
477static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags)
478{
479 struct bnx2x *bp = params->bp;
480 u32 val;
481
482 if (phy_flags & PHY_XGXS_FLAG) {
483 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:XGXS\n");
484 val = XGXS_RESET_BITS;
485
486 } else { /* SerDes */
487 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:SerDes\n");
488 val = SERDES_RESET_BITS;
489 }
490
491 val = val << (params->port*16);
492
493 /* reset and unreset the SerDes/XGXS */
494 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
495 val);
496 udelay(500);
497 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET,
498 val);
499 bnx2x_set_phy_mdio(params);
500}
501
502void bnx2x_link_status_update(struct link_params *params,
503 struct link_vars *vars)
504{
505 struct bnx2x *bp = params->bp;
506 u8 link_10g;
507 u8 port = params->port;
508
509 if (params->switch_cfg == SWITCH_CFG_1G)
510 vars->phy_flags = PHY_SERDES_FLAG;
511 else
512 vars->phy_flags = PHY_XGXS_FLAG;
513 vars->link_status = REG_RD(bp, params->shmem_base +
514 offsetof(struct shmem_region,
515 port_mb[port].link_status));
516
517 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
518
519 if (vars->link_up) {
520 DP(NETIF_MSG_LINK, "phy link up\n");
521
522 vars->phy_link_up = 1;
523 vars->duplex = DUPLEX_FULL;
524 switch (vars->link_status &
525 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
526 case LINK_10THD:
527 vars->duplex = DUPLEX_HALF;
528 /* fall thru */
529 case LINK_10TFD:
530 vars->line_speed = SPEED_10;
531 break;
532
533 case LINK_100TXHD:
534 vars->duplex = DUPLEX_HALF;
535 /* fall thru */
536 case LINK_100T4:
537 case LINK_100TXFD:
538 vars->line_speed = SPEED_100;
539 break;
540
541 case LINK_1000THD:
542 vars->duplex = DUPLEX_HALF;
543 /* fall thru */
544 case LINK_1000TFD:
545 vars->line_speed = SPEED_1000;
546 break;
547
548 case LINK_2500THD:
549 vars->duplex = DUPLEX_HALF;
550 /* fall thru */
551 case LINK_2500TFD:
552 vars->line_speed = SPEED_2500;
553 break;
554
555 case LINK_10GTFD:
556 vars->line_speed = SPEED_10000;
557 break;
558
559 case LINK_12GTFD:
560 vars->line_speed = SPEED_12000;
561 break;
562
563 case LINK_12_5GTFD:
564 vars->line_speed = SPEED_12500;
565 break;
566
567 case LINK_13GTFD:
568 vars->line_speed = SPEED_13000;
569 break;
570
571 case LINK_15GTFD:
572 vars->line_speed = SPEED_15000;
573 break;
574
575 case LINK_16GTFD:
576 vars->line_speed = SPEED_16000;
577 break;
578
579 default:
580 break;
581 }
582
583 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
584 vars->flow_ctrl |= FLOW_CTRL_TX;
585 else
586 vars->flow_ctrl &= ~FLOW_CTRL_TX;
587
588 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
589 vars->flow_ctrl |= FLOW_CTRL_RX;
590 else
591 vars->flow_ctrl &= ~FLOW_CTRL_RX;
592
593 if (vars->phy_flags & PHY_XGXS_FLAG) {
594 if (params->req_line_speed &&
595 ((params->req_line_speed == SPEED_10) ||
596 (params->req_line_speed == SPEED_100))) {
597 vars->phy_flags |= PHY_SGMII_FLAG;
598 } else {
599 vars->phy_flags &= ~PHY_SGMII_FLAG;
600 }
601 }
602
603 /* anything 10 and over uses the bmac */
604 link_10g = ((vars->line_speed == SPEED_10000) ||
605 (vars->line_speed == SPEED_12000) ||
606 (vars->line_speed == SPEED_12500) ||
607 (vars->line_speed == SPEED_13000) ||
608 (vars->line_speed == SPEED_15000) ||
609 (vars->line_speed == SPEED_16000));
610 if (link_10g)
611 vars->mac_type = MAC_TYPE_BMAC;
612 else
613 vars->mac_type = MAC_TYPE_EMAC;
614
615 } else { /* link down */
616 DP(NETIF_MSG_LINK, "phy link down\n");
617
618 vars->phy_link_up = 0;
619
620 vars->line_speed = 0;
621 vars->duplex = DUPLEX_FULL;
622 vars->flow_ctrl = FLOW_CTRL_NONE;
623
624 /* indicate no mac active */
625 vars->mac_type = MAC_TYPE_NONE;
626 }
627
628 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
629 vars->link_status, vars->phy_link_up);
630 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
631 vars->line_speed, vars->duplex, vars->flow_ctrl);
632}
633
634static void bnx2x_update_mng(struct link_params *params, u32 link_status)
635{
636 struct bnx2x *bp = params->bp;
637 REG_WR(bp, params->shmem_base +
638 offsetof(struct shmem_region,
639 port_mb[params->port].link_status),
640 link_status);
641}
642
643static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
644{
645 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
646 NIG_REG_INGRESS_BMAC0_MEM;
647 u32 wb_data[2];
648 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
649
650 /* Only if the bmac is out of reset */
651 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
652 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
653 nig_bmac_enable) {
654
655 /* Clear Rx Enable bit in BMAC_CONTROL register */
656 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
657 wb_data, 2);
658 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
659 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
660 wb_data, 2);
661
662 msleep(1);
663 }
664}
665
666static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
667 u32 line_speed)
668{
669 struct bnx2x *bp = params->bp;
670 u8 port = params->port;
671 u32 init_crd, crd;
672 u32 count = 1000;
673 u32 pause = 0;
674
675 /* disable port */
676 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
677
678 /* wait for init credit */
679 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
680 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
681 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
682
683 while ((init_crd != crd) && count) {
684 msleep(5);
685
686 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
687 count--;
688 }
689 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
690 if (init_crd != crd) {
691 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
692 init_crd, crd);
693 return -EINVAL;
694 }
695
696 if (flow_ctrl & FLOW_CTRL_RX)
697 pause = 1;
698 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, pause);
699 if (pause) {
700 /* update threshold */
701 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
702 /* update init credit */
703 init_crd = 778; /* (800-18-4) */
704
705 } else {
706 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
707 ETH_OVREHEAD)/16;
708
709 /* update threshold */
710 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
711 /* update init credit */
712 switch (line_speed) {
713 case SPEED_10:
714 case SPEED_100:
715 case SPEED_1000:
716 init_crd = thresh + 55 - 22;
717 break;
718
719 case SPEED_2500:
720 init_crd = thresh + 138 - 22;
721 break;
722
723 case SPEED_10000:
724 init_crd = thresh + 553 - 22;
725 break;
726
727 case SPEED_12000:
728 init_crd = thresh + 664 - 22;
729 break;
730
731 case SPEED_13000:
732 init_crd = thresh + 742 - 22;
733 break;
734
735 case SPEED_16000:
736 init_crd = thresh + 778 - 22;
737 break;
738 default:
739 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
740 line_speed);
741 return -EINVAL;
742 break;
743 }
744 }
745 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
746 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
747 line_speed, init_crd);
748
749 /* probe the credit changes */
750 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
751 msleep(5);
752 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
753
754 /* enable port */
755 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
756 return 0;
757}
758
759static u32 bnx2x_get_emac_base(u32 ext_phy_type, u8 port)
760{
761 u32 emac_base;
762 switch (ext_phy_type) {
763 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
764 emac_base = GRCBASE_EMAC0;
765 break;
766 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
767 emac_base = (port) ? GRCBASE_EMAC0: GRCBASE_EMAC1;
768 break;
769 default:
770 emac_base = (port) ? GRCBASE_EMAC1: GRCBASE_EMAC0;
771 break;
772 }
773 return emac_base;
774
775}
776
777u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
778 u8 phy_addr, u8 devad, u16 reg, u16 val)
779{
780 u32 tmp, saved_mode;
781 u8 i, rc = 0;
782 u32 mdio_ctrl = bnx2x_get_emac_base(ext_phy_type, port);
783
784 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
785 * (a value of 49==0x31) and make sure that the AUTO poll is off
786 */
787 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
788 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
789 EMAC_MDIO_MODE_CLOCK_CNT);
790 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
791 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
792 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
793 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
794 udelay(40);
795
796 /* address */
797
798 tmp = ((phy_addr << 21) | (devad << 16) | reg |
799 EMAC_MDIO_COMM_COMMAND_ADDRESS |
800 EMAC_MDIO_COMM_START_BUSY);
801 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
802
803 for (i = 0; i < 50; i++) {
804 udelay(10);
805
806 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
807 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
808 udelay(5);
809 break;
810 }
811 }
812 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
813 DP(NETIF_MSG_LINK, "write phy register failed\n");
814 rc = -EFAULT;
815 } else {
816 /* data */
817 tmp = ((phy_addr << 21) | (devad << 16) | val |
818 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
819 EMAC_MDIO_COMM_START_BUSY);
820 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
821
822 for (i = 0; i < 50; i++) {
823 udelay(10);
824
825 tmp = REG_RD(bp, mdio_ctrl +
826 EMAC_REG_EMAC_MDIO_COMM);
827 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
828 udelay(5);
829 break;
830 }
831 }
832 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
833 DP(NETIF_MSG_LINK, "write phy register failed\n");
834 rc = -EFAULT;
835 }
836 }
837
838 /* Restore the saved mode */
839 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
840
841 return rc;
842}
843
844u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
845 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val)
846{
847 u32 val, saved_mode;
848 u16 i;
849 u8 rc = 0;
850
851 u32 mdio_ctrl = bnx2x_get_emac_base(ext_phy_type, port);
852 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
853 * (a value of 49==0x31) and make sure that the AUTO poll is off
854 */
855 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
856 val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
857 EMAC_MDIO_MODE_CLOCK_CNT));
858 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
859 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
860 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
861 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
862 udelay(40);
863
864 /* address */
865 val = ((phy_addr << 21) | (devad << 16) | reg |
866 EMAC_MDIO_COMM_COMMAND_ADDRESS |
867 EMAC_MDIO_COMM_START_BUSY);
868 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
869
870 for (i = 0; i < 50; i++) {
871 udelay(10);
872
873 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
874 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
875 udelay(5);
876 break;
877 }
878 }
879 if (val & EMAC_MDIO_COMM_START_BUSY) {
880 DP(NETIF_MSG_LINK, "read phy register failed\n");
881
882 *ret_val = 0;
883 rc = -EFAULT;
884
885 } else {
886 /* data */
887 val = ((phy_addr << 21) | (devad << 16) |
888 EMAC_MDIO_COMM_COMMAND_READ_45 |
889 EMAC_MDIO_COMM_START_BUSY);
890 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
891
892 for (i = 0; i < 50; i++) {
893 udelay(10);
894
895 val = REG_RD(bp, mdio_ctrl +
896 EMAC_REG_EMAC_MDIO_COMM);
897 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
898 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
899 break;
900 }
901 }
902 if (val & EMAC_MDIO_COMM_START_BUSY) {
903 DP(NETIF_MSG_LINK, "read phy register failed\n");
904
905 *ret_val = 0;
906 rc = -EFAULT;
907 }
908 }
909
910 /* Restore the saved mode */
911 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
912
913 return rc;
914}
915
916static void bnx2x_set_aer_mmd(struct link_params *params,
917 struct link_vars *vars)
918{
919 struct bnx2x *bp = params->bp;
920 u32 ser_lane;
921 u16 offset;
922
923 ser_lane = ((params->lane_config &
924 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
925 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
926
927 offset = (vars->phy_flags & PHY_XGXS_FLAG) ?
928 (params->phy_addr + ser_lane) : 0;
929
930 CL45_WR_OVER_CL22(bp, params->port,
931 params->phy_addr,
932 MDIO_REG_BANK_AER_BLOCK,
933 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
934}
935
936static void bnx2x_set_master_ln(struct link_params *params)
937{
938 struct bnx2x *bp = params->bp;
939 u16 new_master_ln, ser_lane;
940 ser_lane = ((params->lane_config &
941 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
942 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
943
944 /* set the master_ln for AN */
945 CL45_RD_OVER_CL22(bp, params->port,
946 params->phy_addr,
947 MDIO_REG_BANK_XGXS_BLOCK2,
948 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
949 &new_master_ln);
950
951 CL45_WR_OVER_CL22(bp, params->port,
952 params->phy_addr,
953 MDIO_REG_BANK_XGXS_BLOCK2 ,
954 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
955 (new_master_ln | ser_lane));
956}
957
958static u8 bnx2x_reset_unicore(struct link_params *params)
959{
960 struct bnx2x *bp = params->bp;
961 u16 mii_control;
962 u16 i;
963
964 CL45_RD_OVER_CL22(bp, params->port,
965 params->phy_addr,
966 MDIO_REG_BANK_COMBO_IEEE0,
967 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
968
969 /* reset the unicore */
970 CL45_WR_OVER_CL22(bp, params->port,
971 params->phy_addr,
972 MDIO_REG_BANK_COMBO_IEEE0,
973 MDIO_COMBO_IEEE0_MII_CONTROL,
974 (mii_control |
975 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
976
977 /* wait for the reset to self clear */
978 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
979 udelay(5);
980
981 /* the reset erased the previous bank value */
982 CL45_RD_OVER_CL22(bp, params->port,
983 params->phy_addr,
984 MDIO_REG_BANK_COMBO_IEEE0,
985 MDIO_COMBO_IEEE0_MII_CONTROL,
986 &mii_control);
987
988 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
989 udelay(5);
990 return 0;
991 }
992 }
993
994 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
995 return -EINVAL;
996
997}
998
999static void bnx2x_set_swap_lanes(struct link_params *params)
1000{
1001 struct bnx2x *bp = params->bp;
1002 /* Each two bits represents a lane number:
1003 No swap is 0123 => 0x1b no need to enable the swap */
1004 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1005
1006 ser_lane = ((params->lane_config &
1007 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1008 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1009 rx_lane_swap = ((params->lane_config &
1010 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1011 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1012 tx_lane_swap = ((params->lane_config &
1013 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1014 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1015
1016 if (rx_lane_swap != 0x1b) {
1017 CL45_WR_OVER_CL22(bp, params->port,
1018 params->phy_addr,
1019 MDIO_REG_BANK_XGXS_BLOCK2,
1020 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1021 (rx_lane_swap |
1022 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1023 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1024 } else {
1025 CL45_WR_OVER_CL22(bp, params->port,
1026 params->phy_addr,
1027 MDIO_REG_BANK_XGXS_BLOCK2,
1028 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1029 }
1030
1031 if (tx_lane_swap != 0x1b) {
1032 CL45_WR_OVER_CL22(bp, params->port,
1033 params->phy_addr,
1034 MDIO_REG_BANK_XGXS_BLOCK2,
1035 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1036 (tx_lane_swap |
1037 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1038 } else {
1039 CL45_WR_OVER_CL22(bp, params->port,
1040 params->phy_addr,
1041 MDIO_REG_BANK_XGXS_BLOCK2,
1042 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1043 }
1044}
1045
1046static void bnx2x_set_parallel_detection(struct link_params *params,
1047 u8 phy_flags)
1048{
1049 struct bnx2x *bp = params->bp;
1050 u16 control2;
1051
1052 CL45_RD_OVER_CL22(bp, params->port,
1053 params->phy_addr,
1054 MDIO_REG_BANK_SERDES_DIGITAL,
1055 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1056 &control2);
1057
1058
1059 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1060
1061
1062 CL45_WR_OVER_CL22(bp, params->port,
1063 params->phy_addr,
1064 MDIO_REG_BANK_SERDES_DIGITAL,
1065 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1066 control2);
1067
1068 if (phy_flags & PHY_XGXS_FLAG) {
1069 DP(NETIF_MSG_LINK, "XGXS\n");
1070
1071 CL45_WR_OVER_CL22(bp, params->port,
1072 params->phy_addr,
1073 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1074 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1075 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1076
1077 CL45_RD_OVER_CL22(bp, params->port,
1078 params->phy_addr,
1079 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1080 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1081 &control2);
1082
1083
1084 control2 |=
1085 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1086
1087 CL45_WR_OVER_CL22(bp, params->port,
1088 params->phy_addr,
1089 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1090 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1091 control2);
1092
1093 /* Disable parallel detection of HiG */
1094 CL45_WR_OVER_CL22(bp, params->port,
1095 params->phy_addr,
1096 MDIO_REG_BANK_XGXS_BLOCK2,
1097 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1098 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1099 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1100 }
1101}
1102
1103static void bnx2x_set_autoneg(struct link_params *params,
1104 struct link_vars *vars)
1105{
1106 struct bnx2x *bp = params->bp;
1107 u16 reg_val;
1108
1109 /* CL37 Autoneg */
1110
1111 CL45_RD_OVER_CL22(bp, params->port,
1112 params->phy_addr,
1113 MDIO_REG_BANK_COMBO_IEEE0,
1114 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1115
1116 /* CL37 Autoneg Enabled */
1117 if (params->req_line_speed == SPEED_AUTO_NEG)
1118 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1119 else /* CL37 Autoneg Disabled */
1120 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1121 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1122
1123 CL45_WR_OVER_CL22(bp, params->port,
1124 params->phy_addr,
1125 MDIO_REG_BANK_COMBO_IEEE0,
1126 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1127
1128 /* Enable/Disable Autodetection */
1129
1130 CL45_RD_OVER_CL22(bp, params->port,
1131 params->phy_addr,
1132 MDIO_REG_BANK_SERDES_DIGITAL,
1133 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1134 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
1135 if (params->req_line_speed == SPEED_AUTO_NEG)
1136 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1137 else
1138 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1139
1140 CL45_WR_OVER_CL22(bp, params->port,
1141 params->phy_addr,
1142 MDIO_REG_BANK_SERDES_DIGITAL,
1143 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1144
1145 /* Enable TetonII and BAM autoneg */
1146 CL45_RD_OVER_CL22(bp, params->port,
1147 params->phy_addr,
1148 MDIO_REG_BANK_BAM_NEXT_PAGE,
1149 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1150 &reg_val);
1151 if (params->req_line_speed == SPEED_AUTO_NEG) {
1152 /* Enable BAM aneg Mode and TetonII aneg Mode */
1153 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1154 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1155 } else {
1156 /* TetonII and BAM Autoneg Disabled */
1157 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1158 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1159 }
1160 CL45_WR_OVER_CL22(bp, params->port,
1161 params->phy_addr,
1162 MDIO_REG_BANK_BAM_NEXT_PAGE,
1163 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1164 reg_val);
1165
1166 /* Enable Clause 73 Aneg */
1167 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1168 (SUPPORT_CL73)) {
1169 /* Enable BAM Station Manager */
1170
1171 CL45_WR_OVER_CL22(bp, params->port,
1172 params->phy_addr,
1173 MDIO_REG_BANK_CL73_USERB0,
1174 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1175 (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1176 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1177 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));
1178
1179 /* Merge CL73 and CL37 aneg resolution */
1180 CL45_RD_OVER_CL22(bp, params->port,
1181 params->phy_addr,
1182 MDIO_REG_BANK_CL73_USERB0,
1183 MDIO_CL73_USERB0_CL73_BAM_CTRL3,
1184 &reg_val);
1185
1186 CL45_WR_OVER_CL22(bp, params->port,
1187 params->phy_addr,
1188 MDIO_REG_BANK_CL73_USERB0,
1189 MDIO_CL73_USERB0_CL73_BAM_CTRL3,
1190 (reg_val |
1191 MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));
1192
1193 /* Set the CL73 AN speed */
1194
1195 CL45_RD_OVER_CL22(bp, params->port,
1196 params->phy_addr,
1197 MDIO_REG_BANK_CL73_IEEEB1,
1198 MDIO_CL73_IEEEB1_AN_ADV2, &reg_val);
1199 /* In the SerDes we support only the 1G.
1200 In the XGXS we support the 10G KX4
1201 but we currently do not support the KR */
1202 if (vars->phy_flags & PHY_XGXS_FLAG) {
1203 DP(NETIF_MSG_LINK, "XGXS\n");
1204 /* 10G KX4 */
1205 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
1206 } else {
1207 DP(NETIF_MSG_LINK, "SerDes\n");
1208 /* 1000M KX */
1209 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
1210 }
1211 CL45_WR_OVER_CL22(bp, params->port,
1212 params->phy_addr,
1213 MDIO_REG_BANK_CL73_IEEEB1,
1214 MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
1215
1216 /* CL73 Autoneg Enabled */
1217 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1218 } else {
1219 /* CL73 Autoneg Disabled */
1220 reg_val = 0;
1221 }
1222 CL45_WR_OVER_CL22(bp, params->port,
1223 params->phy_addr,
1224 MDIO_REG_BANK_CL73_IEEEB0,
1225 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1226}
1227
1228/* program SerDes, forced speed */
1229static void bnx2x_program_serdes(struct link_params *params)
1230{
1231 struct bnx2x *bp = params->bp;
1232 u16 reg_val;
1233
1234 /* program duplex, disable autoneg */
1235
1236 CL45_RD_OVER_CL22(bp, params->port,
1237 params->phy_addr,
1238 MDIO_REG_BANK_COMBO_IEEE0,
1239 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1240 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
1241 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
1242 if (params->req_duplex == DUPLEX_FULL)
1243 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1244 CL45_WR_OVER_CL22(bp, params->port,
1245 params->phy_addr,
1246 MDIO_REG_BANK_COMBO_IEEE0,
1247 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1248
1249 /* program speed
1250 - needed only if the speed is greater than 1G (2.5G or 10G) */
1251 if (!((params->req_line_speed == SPEED_1000) ||
1252 (params->req_line_speed == SPEED_100) ||
1253 (params->req_line_speed == SPEED_10))) {
1254 CL45_RD_OVER_CL22(bp, params->port,
1255 params->phy_addr,
1256 MDIO_REG_BANK_SERDES_DIGITAL,
1257 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
1258 /* clearing the speed value before setting the right speed */
1259 reg_val &= ~MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK;
1260 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1261 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1262 if (params->req_line_speed == SPEED_10000)
1263 reg_val |=
1264 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
1265 if (params->req_line_speed == SPEED_13000)
1266 reg_val |=
1267 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
1268 CL45_WR_OVER_CL22(bp, params->port,
1269 params->phy_addr,
1270 MDIO_REG_BANK_SERDES_DIGITAL,
1271 MDIO_SERDES_DIGITAL_MISC1, reg_val);
1272 }
1273}
1274
1275static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1276{
1277 struct bnx2x *bp = params->bp;
1278 u16 val = 0;
1279
1280 /* configure the 48 bits for BAM AN */
1281
1282 /* set extended capabilities */
1283 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
1284 val |= MDIO_OVER_1G_UP1_2_5G;
1285 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1286 val |= MDIO_OVER_1G_UP1_10G;
1287 CL45_WR_OVER_CL22(bp, params->port,
1288 params->phy_addr,
1289 MDIO_REG_BANK_OVER_1G,
1290 MDIO_OVER_1G_UP1, val);
1291
1292 CL45_WR_OVER_CL22(bp, params->port,
1293 params->phy_addr,
1294 MDIO_REG_BANK_OVER_1G,
1295 MDIO_OVER_1G_UP3, 0);
1296}
1297
1298static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1299 u32 *ieee_fc)
1300{
1301 struct bnx2x *bp = params->bp;
1302 /* for AN, we are always publishing full duplex */
1303 u16 an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1304
1305 /* resolve pause mode and advertisement
1306 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1307
1308 switch (params->req_flow_ctrl) {
1309 case FLOW_CTRL_AUTO:
1310 if (params->mtu <= MAX_MTU_SIZE) {
1311 an_adv |=
1312 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1313 } else {
1314 an_adv |=
1315 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1316 }
1317 break;
1318 case FLOW_CTRL_TX:
1319 an_adv |=
1320 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1321 break;
1322
1323 case FLOW_CTRL_RX:
1324 case FLOW_CTRL_BOTH:
1325 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1326 break;
1327
1328 case FLOW_CTRL_NONE:
1329 default:
1330 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1331 break;
1332 }
1333
1334 *ieee_fc = an_adv;
1335
1336 CL45_WR_OVER_CL22(bp, params->port,
1337 params->phy_addr,
1338 MDIO_REG_BANK_COMBO_IEEE0,
1339 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, an_adv);
1340}
1341
1342static void bnx2x_restart_autoneg(struct link_params *params)
1343{
1344 struct bnx2x *bp = params->bp;
1345 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
1346 if (SUPPORT_CL73) {
1347 /* enable and restart clause 73 aneg */
1348 u16 an_ctrl;
1349
1350 CL45_RD_OVER_CL22(bp, params->port,
1351 params->phy_addr,
1352 MDIO_REG_BANK_CL73_IEEEB0,
1353 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1354 &an_ctrl);
1355 CL45_WR_OVER_CL22(bp, params->port,
1356 params->phy_addr,
1357 MDIO_REG_BANK_CL73_IEEEB0,
1358 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1359 (an_ctrl |
1360 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
1361 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
1362
1363 } else {
1364 /* Enable and restart BAM/CL37 aneg */
1365 u16 mii_control;
1366
1367 CL45_RD_OVER_CL22(bp, params->port,
1368 params->phy_addr,
1369 MDIO_REG_BANK_COMBO_IEEE0,
1370 MDIO_COMBO_IEEE0_MII_CONTROL,
1371 &mii_control);
1372 DP(NETIF_MSG_LINK,
1373 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1374 mii_control);
1375 CL45_WR_OVER_CL22(bp, params->port,
1376 params->phy_addr,
1377 MDIO_REG_BANK_COMBO_IEEE0,
1378 MDIO_COMBO_IEEE0_MII_CONTROL,
1379 (mii_control |
1380 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1381 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1382 }
1383}
1384
1385static void bnx2x_initialize_sgmii_process(struct link_params *params)
1386{
1387 struct bnx2x *bp = params->bp;
1388 u16 control1;
1389
1390 /* in SGMII mode, the unicore is always slave */
1391
1392 CL45_RD_OVER_CL22(bp, params->port,
1393 params->phy_addr,
1394 MDIO_REG_BANK_SERDES_DIGITAL,
1395 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1396 &control1);
1397 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
1398 /* set sgmii mode (and not fiber) */
1399 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1400 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1401 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
1402 CL45_WR_OVER_CL22(bp, params->port,
1403 params->phy_addr,
1404 MDIO_REG_BANK_SERDES_DIGITAL,
1405 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1406 control1);
1407
1408 /* if forced speed */
1409 if (!(params->req_line_speed == SPEED_AUTO_NEG)) {
1410 /* set speed, disable autoneg */
1411 u16 mii_control;
1412
1413 CL45_RD_OVER_CL22(bp, params->port,
1414 params->phy_addr,
1415 MDIO_REG_BANK_COMBO_IEEE0,
1416 MDIO_COMBO_IEEE0_MII_CONTROL,
1417 &mii_control);
1418 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1419 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1420 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1421
1422 switch (params->req_line_speed) {
1423 case SPEED_100:
1424 mii_control |=
1425 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
1426 break;
1427 case SPEED_1000:
1428 mii_control |=
1429 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
1430 break;
1431 case SPEED_10:
1432 /* there is nothing to set for 10M */
1433 break;
1434 default:
1435 /* invalid speed for SGMII */
1436 DP(NETIF_MSG_LINK, "Invalid req_line_speed 0x%x\n",
1437 params->req_line_speed);
1438 break;
1439 }
1440
1441 /* setting the full duplex */
1442 if (params->req_duplex == DUPLEX_FULL)
1443 mii_control |=
1444 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1445 CL45_WR_OVER_CL22(bp, params->port,
1446 params->phy_addr,
1447 MDIO_REG_BANK_COMBO_IEEE0,
1448 MDIO_COMBO_IEEE0_MII_CONTROL,
1449 mii_control);
1450
1451 } else { /* AN mode */
1452 /* enable and restart AN */
1453 bnx2x_restart_autoneg(params);
1454 }
1455}
1456
1457
1458/*
1459 * link management
1460 */
1461
1462static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1463{
1464 switch (pause_result) { /* ASYM P ASYM P */
1465 case 0xb: /* 1 0 1 1 */
1466 vars->flow_ctrl = FLOW_CTRL_TX;
1467 break;
1468
1469 case 0xe: /* 1 1 1 0 */
1470 vars->flow_ctrl = FLOW_CTRL_RX;
1471 break;
1472
1473 case 0x5: /* 0 1 0 1 */
1474 case 0x7: /* 0 1 1 1 */
1475 case 0xd: /* 1 1 0 1 */
1476 case 0xf: /* 1 1 1 1 */
1477 vars->flow_ctrl = FLOW_CTRL_BOTH;
1478 break;
1479
1480 default:
1481 break;
1482 }
1483}
1484
1485static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
1486 struct link_vars *vars)
1487{
1488 struct bnx2x *bp = params->bp;
1489 u8 ext_phy_addr;
1490 u16 ld_pause; /* local */
1491 u16 lp_pause; /* link partner */
1492 u16 an_complete; /* AN complete */
1493 u16 pause_result;
1494 u8 ret = 0;
1495 u32 ext_phy_type;
1496 u8 port = params->port;
1497 ext_phy_addr = ((params->ext_phy_config &
1498 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1499 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1500
1501 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1502 /* read twice */
1503
1504 bnx2x_cl45_read(bp, port,
1505 ext_phy_type,
1506 ext_phy_addr,
1507 MDIO_AN_DEVAD,
1508 MDIO_AN_REG_STATUS, &an_complete);
1509 bnx2x_cl45_read(bp, port,
1510 ext_phy_type,
1511 ext_phy_addr,
1512 MDIO_AN_DEVAD,
1513 MDIO_AN_REG_STATUS, &an_complete);
1514
1515 if (an_complete & MDIO_AN_REG_STATUS_AN_COMPLETE) {
1516 ret = 1;
1517 bnx2x_cl45_read(bp, port,
1518 ext_phy_type,
1519 ext_phy_addr,
1520 MDIO_AN_DEVAD,
1521 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
1522 bnx2x_cl45_read(bp, port,
1523 ext_phy_type,
1524 ext_phy_addr,
1525 MDIO_AN_DEVAD,
1526 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1527 pause_result = (ld_pause &
1528 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
1529 pause_result |= (lp_pause &
1530 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
1531 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1532 pause_result);
1533 bnx2x_pause_resolve(vars, pause_result);
1534 }
1535 return ret;
1536}
1537
1538
1539static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1540 struct link_vars *vars,
1541 u32 gp_status)
1542{
1543 struct bnx2x *bp = params->bp;
1544 u16 ld_pause; /* local driver */
1545 u16 lp_pause; /* link partner */
1546 u16 pause_result;
1547
1548 vars->flow_ctrl = FLOW_CTRL_NONE;
1549
1550 /* resolve from gp_status in case of AN complete and not sgmii */
1551 if ((params->req_flow_ctrl == FLOW_CTRL_AUTO) &&
1552 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1553 (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
1554 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1555 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1556 CL45_RD_OVER_CL22(bp, params->port,
1557 params->phy_addr,
1558 MDIO_REG_BANK_COMBO_IEEE0,
1559 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1560 &ld_pause);
1561 CL45_RD_OVER_CL22(bp, params->port,
1562 params->phy_addr,
1563 MDIO_REG_BANK_COMBO_IEEE0,
1564 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1565 &lp_pause);
1566 pause_result = (ld_pause &
1567 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1568 pause_result |= (lp_pause &
1569 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1570 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
1571 bnx2x_pause_resolve(vars, pause_result);
1572 } else if ((params->req_flow_ctrl == FLOW_CTRL_AUTO) &&
1573 (bnx2x_ext_phy_resove_fc(params, vars))) {
1574 return;
1575 } else {
1576 vars->flow_ctrl = params->req_flow_ctrl;
1577 if (vars->flow_ctrl == FLOW_CTRL_AUTO) {
1578 if (params->mtu <= MAX_MTU_SIZE)
1579 vars->flow_ctrl = FLOW_CTRL_BOTH;
1580 else
1581 vars->flow_ctrl = FLOW_CTRL_TX;
1582 }
1583 }
1584 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1585}
1586
1587
1588static u8 bnx2x_link_settings_status(struct link_params *params,
1589 struct link_vars *vars,
1590 u32 gp_status)
1591{
1592 struct bnx2x *bp = params->bp;
1593 u8 rc = 0;
1594 vars->link_status = 0;
1595
1596 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1597 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1598 gp_status);
1599
1600 vars->phy_link_up = 1;
1601 vars->link_status |= LINK_STATUS_LINK_UP;
1602
1603 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1604 vars->duplex = DUPLEX_FULL;
1605 else
1606 vars->duplex = DUPLEX_HALF;
1607
1608 bnx2x_flow_ctrl_resolve(params, vars, gp_status);
1609
1610 switch (gp_status & GP_STATUS_SPEED_MASK) {
1611 case GP_STATUS_10M:
1612 vars->line_speed = SPEED_10;
1613 if (vars->duplex == DUPLEX_FULL)
1614 vars->link_status |= LINK_10TFD;
1615 else
1616 vars->link_status |= LINK_10THD;
1617 break;
1618
1619 case GP_STATUS_100M:
1620 vars->line_speed = SPEED_100;
1621 if (vars->duplex == DUPLEX_FULL)
1622 vars->link_status |= LINK_100TXFD;
1623 else
1624 vars->link_status |= LINK_100TXHD;
1625 break;
1626
1627 case GP_STATUS_1G:
1628 case GP_STATUS_1G_KX:
1629 vars->line_speed = SPEED_1000;
1630 if (vars->duplex == DUPLEX_FULL)
1631 vars->link_status |= LINK_1000TFD;
1632 else
1633 vars->link_status |= LINK_1000THD;
1634 break;
1635
1636 case GP_STATUS_2_5G:
1637 vars->line_speed = SPEED_2500;
1638 if (vars->duplex == DUPLEX_FULL)
1639 vars->link_status |= LINK_2500TFD;
1640 else
1641 vars->link_status |= LINK_2500THD;
1642 break;
1643
1644 case GP_STATUS_5G:
1645 case GP_STATUS_6G:
1646 DP(NETIF_MSG_LINK,
1647 "link speed unsupported gp_status 0x%x\n",
1648 gp_status);
1649 return -EINVAL;
1650 break;
1651 case GP_STATUS_10G_KX4:
1652 case GP_STATUS_10G_HIG:
1653 case GP_STATUS_10G_CX4:
1654 vars->line_speed = SPEED_10000;
1655 vars->link_status |= LINK_10GTFD;
1656 break;
1657
1658 case GP_STATUS_12G_HIG:
1659 vars->line_speed = SPEED_12000;
1660 vars->link_status |= LINK_12GTFD;
1661 break;
1662
1663 case GP_STATUS_12_5G:
1664 vars->line_speed = SPEED_12500;
1665 vars->link_status |= LINK_12_5GTFD;
1666 break;
1667
1668 case GP_STATUS_13G:
1669 vars->line_speed = SPEED_13000;
1670 vars->link_status |= LINK_13GTFD;
1671 break;
1672
1673 case GP_STATUS_15G:
1674 vars->line_speed = SPEED_15000;
1675 vars->link_status |= LINK_15GTFD;
1676 break;
1677
1678 case GP_STATUS_16G:
1679 vars->line_speed = SPEED_16000;
1680 vars->link_status |= LINK_16GTFD;
1681 break;
1682
1683 default:
1684 DP(NETIF_MSG_LINK,
1685 "link speed unsupported gp_status 0x%x\n",
1686 gp_status);
1687 return -EINVAL;
1688 break;
1689 }
1690
1691 vars->link_status |= LINK_STATUS_SERDES_LINK;
1692
1693 if (params->req_line_speed == SPEED_AUTO_NEG) {
1694 vars->autoneg = AUTO_NEG_ENABLED;
1695
1696 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
1697 vars->autoneg |= AUTO_NEG_COMPLETE;
1698 vars->link_status |=
1699 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1700 }
1701
1702 vars->autoneg |= AUTO_NEG_PARALLEL_DETECTION_USED;
1703 vars->link_status |=
1704 LINK_STATUS_PARALLEL_DETECTION_USED;
1705
1706 }
1707 if (vars->flow_ctrl & FLOW_CTRL_TX)
1708 vars->link_status |=
1709 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1710
1711 if (vars->flow_ctrl & FLOW_CTRL_RX)
1712 vars->link_status |=
1713 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1714
1715 } else { /* link_down */
1716 DP(NETIF_MSG_LINK, "phy link down\n");
1717
1718 vars->phy_link_up = 0;
1719 vars->line_speed = 0;
1720 vars->duplex = DUPLEX_FULL;
1721 vars->flow_ctrl = FLOW_CTRL_NONE;
1722 vars->autoneg = AUTO_NEG_DISABLED;
1723 vars->mac_type = MAC_TYPE_NONE;
1724 }
1725
1726 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x \n",
1727 gp_status, vars->phy_link_up, vars->line_speed);
1728 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x"
1729 " autoneg 0x%x\n",
1730 vars->duplex,
1731 vars->flow_ctrl, vars->autoneg);
1732 DP(NETIF_MSG_LINK, "link_status 0x%x\n", vars->link_status);
1733
1734 return rc;
1735}
1736
1737static void bnx2x_set_sgmii_tx_driver(struct link_params *params)
1738{
1739 struct bnx2x *bp = params->bp;
1740 u16 lp_up2;
1741 u16 tx_driver;
1742
1743 /* read precomp */
1744
1745 CL45_RD_OVER_CL22(bp, params->port,
1746 params->phy_addr,
1747 MDIO_REG_BANK_OVER_1G,
1748 MDIO_OVER_1G_LP_UP2, &lp_up2);
1749
1750 CL45_RD_OVER_CL22(bp, params->port,
1751 params->phy_addr,
1752 MDIO_REG_BANK_TX0,
1753 MDIO_TX0_TX_DRIVER, &tx_driver);
1754
1755 /* bits [10:7] at lp_up2, positioned at [15:12] */
1756 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
1757 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
1758 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
1759
1760 if ((lp_up2 != 0) &&
1761 (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) {
1762 /* replace tx_driver bits [15:12] */
1763 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
1764 tx_driver |= lp_up2;
1765 CL45_WR_OVER_CL22(bp, params->port,
1766 params->phy_addr,
1767 MDIO_REG_BANK_TX0,
1768 MDIO_TX0_TX_DRIVER, tx_driver);
1769 }
1770}
1771
1772static u8 bnx2x_emac_program(struct link_params *params,
1773 u32 line_speed, u32 duplex)
1774{
1775 struct bnx2x *bp = params->bp;
1776 u8 port = params->port;
1777 u16 mode = 0;
1778
1779 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
1780 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
1781 EMAC_REG_EMAC_MODE,
1782 (EMAC_MODE_25G_MODE |
1783 EMAC_MODE_PORT_MII_10M |
1784 EMAC_MODE_HALF_DUPLEX));
1785 switch (line_speed) {
1786 case SPEED_10:
1787 mode |= EMAC_MODE_PORT_MII_10M;
1788 break;
1789
1790 case SPEED_100:
1791 mode |= EMAC_MODE_PORT_MII;
1792 break;
1793
1794 case SPEED_1000:
1795 mode |= EMAC_MODE_PORT_GMII;
1796 break;
1797
1798 case SPEED_2500:
1799 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
1800 break;
1801
1802 default:
1803 /* 10G not valid for EMAC */
1804 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", line_speed);
1805 return -EINVAL;
1806 }
1807
1808 if (duplex == DUPLEX_HALF)
1809 mode |= EMAC_MODE_HALF_DUPLEX;
1810 bnx2x_bits_en(bp,
1811 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
1812 mode);
1813
1814 bnx2x_set_led(bp, params->port, LED_MODE_OPER,
1815 line_speed, params->hw_led_mode, params->chip_id);
1816 return 0;
1817}
1818
1819/*****************************************************************************/
1820/* External Phy section */
1821/*****************************************************************************/
1822static void bnx2x_hw_reset(struct bnx2x *bp)
1823{
1824 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1825 MISC_REGISTERS_GPIO_OUTPUT_LOW);
1826 msleep(1);
1827 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1828 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1829}
1830
1831static void bnx2x_ext_phy_reset(struct link_params *params,
1832 struct link_vars *vars)
1833{
1834 struct bnx2x *bp = params->bp;
1835 u32 ext_phy_type;
1836 u8 ext_phy_addr = ((params->ext_phy_config &
1837 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1838 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1839 DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port);
1840 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1841 /* The PHY reset is controled by GPIO 1
1842 * Give it 1ms of reset pulse
1843 */
1844 if (vars->phy_flags & PHY_XGXS_FLAG) {
1845
1846 switch (ext_phy_type) {
1847 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
1848 DP(NETIF_MSG_LINK, "XGXS Direct\n");
1849 break;
1850
1851 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
1852 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
1853 DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
1854
1855 /* Restore normal power mode*/
1856 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1857 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1858
1859 /* HW reset */
1860 bnx2x_hw_reset(bp);
1861
1862 bnx2x_cl45_write(bp, params->port,
1863 ext_phy_type,
1864 ext_phy_addr,
1865 MDIO_PMA_DEVAD,
1866 MDIO_PMA_REG_CTRL, 0xa040);
1867 break;
1868 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
1869 /* Unset Low Power Mode and SW reset */
1870 /* Restore normal power mode*/
1871 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1872 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1873
1874 DP(NETIF_MSG_LINK, "XGXS 8072\n");
1875 bnx2x_cl45_write(bp, params->port,
1876 ext_phy_type,
1877 ext_phy_addr,
1878 MDIO_PMA_DEVAD,
1879 MDIO_PMA_REG_CTRL,
1880 1<<15);
1881 break;
1882 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
1883 {
1884 u16 emac_base;
1885 emac_base = (params->port) ? GRCBASE_EMAC0 :
1886 GRCBASE_EMAC1;
1887
1888 /* Restore normal power mode*/
1889 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1890 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1891
1892 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1893 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1894
1895 DP(NETIF_MSG_LINK, "XGXS 8073\n");
1896 bnx2x_cl45_write(bp,
1897 params->port,
1898 ext_phy_type,
1899 ext_phy_addr,
1900 MDIO_PMA_DEVAD,
1901 MDIO_PMA_REG_CTRL,
1902 1<<15);
1903 }
1904 break;
1905
1906 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
1907 DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
1908
1909 /* Restore normal power mode*/
1910 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1911 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1912
1913 /* HW reset */
1914 bnx2x_hw_reset(bp);
1915
1916 break;
1917
1918 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
1919 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
1920 break;
1921
1922 default:
1923 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
1924 params->ext_phy_config);
1925 break;
1926 }
1927
1928 } else { /* SerDes */
1929 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
1930 switch (ext_phy_type) {
1931 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
1932 DP(NETIF_MSG_LINK, "SerDes Direct\n");
1933 break;
1934
1935 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
1936 DP(NETIF_MSG_LINK, "SerDes 5482\n");
1937 bnx2x_hw_reset(bp);
1938 break;
1939
1940 default:
1941 DP(NETIF_MSG_LINK,
1942 "BAD SerDes ext_phy_config 0x%x\n",
1943 params->ext_phy_config);
1944 break;
1945 }
1946 }
1947}
1948
1949static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
1950{
1951 struct bnx2x *bp = params->bp;
1952 u8 port = params->port;
1953 u8 ext_phy_addr = ((params->ext_phy_config &
1954 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1955 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1956 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1957 u16 fw_ver1, fw_ver2;
1958
1959 /* Need to wait 200ms after reset */
1960 msleep(200);
1961 /* Boot port from external ROM
1962 * Set ser_boot_ctl bit in the MISC_CTRL1 register
1963 */
1964 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
1965 MDIO_PMA_DEVAD,
1966 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
1967
1968 /* Reset internal microprocessor */
1969 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
1970 MDIO_PMA_DEVAD,
1971 MDIO_PMA_REG_GEN_CTRL,
1972 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
1973 /* set micro reset = 0 */
1974 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
1975 MDIO_PMA_DEVAD,
1976 MDIO_PMA_REG_GEN_CTRL,
1977 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
1978 /* Reset internal microprocessor */
1979 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
1980 MDIO_PMA_DEVAD,
1981 MDIO_PMA_REG_GEN_CTRL,
1982 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
1983 /* wait for 100ms for code download via SPI port */
1984 msleep(100);
1985
1986 /* Clear ser_boot_ctl bit */
1987 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
1988 MDIO_PMA_DEVAD,
1989 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
1990 /* Wait 100ms */
1991 msleep(100);
1992
1993 /* Print the PHY FW version */
1994 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
1995 MDIO_PMA_DEVAD,
1996 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
1997 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
1998 MDIO_PMA_DEVAD,
1999 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2000 DP(NETIF_MSG_LINK, "8072 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
2001}
2002
2003static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
2004{
2005 /* This is only required for 8073A1, version 102 only */
2006
2007 struct bnx2x *bp = params->bp;
2008 u8 ext_phy_addr = ((params->ext_phy_config &
2009 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2010 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2011 u16 val;
2012
2013 /* Read 8073 HW revision*/
2014 bnx2x_cl45_read(bp, params->port,
2015 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2016 ext_phy_addr,
2017 MDIO_PMA_DEVAD,
2018 0xc801, &val);
2019
2020 if (val != 1) {
2021 /* No need to workaround in 8073 A1 */
2022 return 0;
2023 }
2024
2025 bnx2x_cl45_read(bp, params->port,
2026 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2027 ext_phy_addr,
2028 MDIO_PMA_DEVAD,
2029 MDIO_PMA_REG_ROM_VER2, &val);
2030
2031 /* SNR should be applied only for version 0x102 */
2032 if (val != 0x102)
2033 return 0;
2034
2035 return 1;
2036}
2037
2038static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2039{
2040 struct bnx2x *bp = params->bp;
2041 u8 ext_phy_addr = ((params->ext_phy_config &
2042 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2043 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2044 u16 val, cnt, cnt1 ;
2045
2046 bnx2x_cl45_read(bp, params->port,
2047 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2048 ext_phy_addr,
2049 MDIO_PMA_DEVAD,
2050 0xc801, &val);
2051
2052 if (val > 0) {
2053 /* No need to workaround in 8073 A1 */
2054 return 0;
2055 }
2056 /* XAUI workaround in 8073 A0: */
2057
2058 /* After loading the boot ROM and restarting Autoneg,
2059 poll Dev1, Reg $C820: */
2060
2061 for (cnt = 0; cnt < 1000; cnt++) {
2062 bnx2x_cl45_read(bp, params->port,
2063 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2064 ext_phy_addr,
2065 MDIO_PMA_DEVAD,
2066 0xc820, &val);
2067 /* If bit [14] = 0 or bit [13] = 0, continue on with
2068 system initialization (XAUI work-around not required,
2069 as these bits indicate 2.5G or 1G link up). */
2070 if (!(val & (1<<14)) || !(val & (1<<13))) {
2071 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
2072 return 0;
2073 } else if (!(val & (1<<15))) {
2074 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
2075 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
2076 it's MSB (bit 15) goes to 1 (indicating that the
2077 XAUI workaround has completed),
2078 then continue on with system initialization.*/
2079 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
2080 bnx2x_cl45_read(bp, params->port,
2081 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2082 ext_phy_addr,
2083 MDIO_PMA_DEVAD,
2084 0xc841, &val);
2085 if (val & (1<<15)) {
2086 DP(NETIF_MSG_LINK,
2087 "XAUI workaround has completed\n");
2088 return 0;
2089 }
2090 msleep(3);
2091 }
2092 break;
2093 }
2094 msleep(3);
2095 }
2096 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
2097 return -EINVAL;
2098
2099}
2100
2101static void bnx2x_bcm8073_external_rom_boot(struct link_params *params)
2102{
2103 struct bnx2x *bp = params->bp;
2104 u8 port = params->port;
2105 u8 ext_phy_addr = ((params->ext_phy_config &
2106 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2107 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2108 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2109 u16 fw_ver1, fw_ver2, val;
2110 /* Need to wait 100ms after reset */
2111 msleep(100);
2112 /* Boot port from external ROM */
2113 /* EDC grst */
2114 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2115 MDIO_PMA_DEVAD,
2116 MDIO_PMA_REG_GEN_CTRL,
2117 0x0001);
2118
2119 /* ucode reboot and rst */
2120 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2121 MDIO_PMA_DEVAD,
2122 MDIO_PMA_REG_GEN_CTRL,
2123 0x008c);
2124
2125 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2126 MDIO_PMA_DEVAD,
2127 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2128
2129 /* Reset internal microprocessor */
2130 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2131 MDIO_PMA_DEVAD,
2132 MDIO_PMA_REG_GEN_CTRL,
2133 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2134
2135 /* Release srst bit */
2136 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2137 MDIO_PMA_DEVAD,
2138 MDIO_PMA_REG_GEN_CTRL,
2139 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2140
2141 /* wait for 100ms for code download via SPI port */
2142 msleep(100);
2143
2144 /* Clear ser_boot_ctl bit */
2145 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2146 MDIO_PMA_DEVAD,
2147 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2148
2149 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2150 MDIO_PMA_DEVAD,
2151 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2152 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2153 MDIO_PMA_DEVAD,
2154 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2155 DP(NETIF_MSG_LINK, "8073 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
2156
2157 /* Only set bit 10 = 1 (Tx power down) */
2158 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2159 MDIO_PMA_DEVAD,
2160 MDIO_PMA_REG_TX_POWER_DOWN, &val);
2161
2162 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2163 MDIO_PMA_DEVAD,
2164 MDIO_PMA_REG_TX_POWER_DOWN, (val | 1<<10));
2165
2166 msleep(600);
2167 /* Release bit 10 (Release Tx power down) */
2168 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2169 MDIO_PMA_DEVAD,
2170 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
2171
2172}
2173
2174static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
2175{
2176 struct bnx2x *bp = params->bp;
2177 u8 port = params->port;
2178 u16 val;
2179 u8 ext_phy_addr = ((params->ext_phy_config &
2180 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2181 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2182 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2183
2184 bnx2x_cl45_read(bp, params->port,
2185 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2186 ext_phy_addr,
2187 MDIO_PMA_DEVAD,
2188 0xc801, &val);
2189
2190 if (val == 0) {
2191 /* Mustn't set low power mode in 8073 A0 */
2192 return;
2193 }
2194
2195 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
2196 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2197 MDIO_XS_DEVAD,
2198 MDIO_XS_PLL_SEQUENCER, &val);
2199 val &= ~(1<<13);
2200 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2201 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
2202
2203 /* PLL controls */
2204 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2205 MDIO_XS_DEVAD, 0x805E, 0x1077);
2206 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2207 MDIO_XS_DEVAD, 0x805D, 0x0000);
2208 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2209 MDIO_XS_DEVAD, 0x805C, 0x030B);
2210 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2211 MDIO_XS_DEVAD, 0x805B, 0x1240);
2212 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2213 MDIO_XS_DEVAD, 0x805A, 0x2490);
2214
2215 /* Tx Controls */
2216 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2217 MDIO_XS_DEVAD, 0x80A7, 0x0C74);
2218 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2219 MDIO_XS_DEVAD, 0x80A6, 0x9041);
2220 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2221 MDIO_XS_DEVAD, 0x80A5, 0x4640);
2222
2223 /* Rx Controls */
2224 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2225 MDIO_XS_DEVAD, 0x80FE, 0x01C4);
2226 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2227 MDIO_XS_DEVAD, 0x80FD, 0x9249);
2228 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2229 MDIO_XS_DEVAD, 0x80FC, 0x2015);
2230
2231 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
2232 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2233 MDIO_XS_DEVAD,
2234 MDIO_XS_PLL_SEQUENCER, &val);
2235 val |= (1<<13);
2236 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2237 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
2238}
2239static void bnx2x_bcm807x_force_10G(struct link_params *params)
2240{
2241 struct bnx2x *bp = params->bp;
2242 u8 port = params->port;
2243 u8 ext_phy_addr = ((params->ext_phy_config &
2244 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2245 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2246 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2247
2248 /* Force KR or KX */
2249 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2250 MDIO_PMA_DEVAD,
2251 MDIO_PMA_REG_CTRL,
2252 0x2040);
2253 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2254 MDIO_PMA_DEVAD,
2255 MDIO_PMA_REG_10G_CTRL2,
2256 0x000b);
2257 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2258 MDIO_PMA_DEVAD,
2259 MDIO_PMA_REG_BCM_CTRL,
2260 0x0000);
2261 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2262 MDIO_AN_DEVAD,
2263 MDIO_AN_REG_CTRL,
2264 0x0000);
2265}
2266
2267static void bnx2x_ext_phy_set_pause(struct link_params *params,
2268 struct link_vars *vars)
2269{
2270 struct bnx2x *bp = params->bp;
2271 u16 val;
2272 u8 ext_phy_addr = ((params->ext_phy_config &
2273 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2274 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2275 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2276
2277 /* read modify write pause advertizing */
2278 bnx2x_cl45_read(bp, params->port,
2279 ext_phy_type,
2280 ext_phy_addr,
2281 MDIO_AN_DEVAD,
2282 MDIO_AN_REG_ADV_PAUSE, &val);
2283
2284 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
2285 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
2286
2287 if (vars->ieee_fc &
2288 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
2289 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
2290 }
2291 if (vars->ieee_fc &
2292 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
2293 val |=
2294 MDIO_AN_REG_ADV_PAUSE_PAUSE;
2295 }
2296 DP(NETIF_MSG_LINK,
2297 "Ext phy AN advertize 0x%x\n", val);
2298 bnx2x_cl45_write(bp, params->port,
2299 ext_phy_type,
2300 ext_phy_addr,
2301 MDIO_AN_DEVAD,
2302 MDIO_AN_REG_ADV_PAUSE, val);
2303}
2304
2305static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2306{
2307 struct bnx2x *bp = params->bp;
2308 u32 ext_phy_type;
2309 u8 ext_phy_addr;
2310 u16 cnt;
2311 u16 ctrl = 0;
2312 u16 val = 0;
2313 u8 rc = 0;
2314 if (vars->phy_flags & PHY_XGXS_FLAG) {
2315 ext_phy_addr = ((params->ext_phy_config &
2316 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2317 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2318
2319 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2320 /* Make sure that the soft reset is off (expect for the 8072:
2321 * due to the lock, it will be done inside the specific
2322 * handling)
2323 */
2324 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
2325 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
2326 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
2327 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
2328 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
2329 /* Wait for soft reset to get cleared upto 1 sec */
2330 for (cnt = 0; cnt < 1000; cnt++) {
2331 bnx2x_cl45_read(bp, params->port,
2332 ext_phy_type,
2333 ext_phy_addr,
2334 MDIO_PMA_DEVAD,
2335 MDIO_PMA_REG_CTRL, &ctrl);
2336 if (!(ctrl & (1<<15)))
2337 break;
2338 msleep(1);
2339 }
2340 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n",
2341 ctrl, cnt);
2342 }
2343
2344 switch (ext_phy_type) {
2345 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2346 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2347 break;
2348
2349 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
2350 DP(NETIF_MSG_LINK, "XGXS 8705\n");
2351
2352 bnx2x_cl45_write(bp, params->port,
2353 ext_phy_type,
2354 ext_phy_addr,
2355 MDIO_PMA_DEVAD,
2356 MDIO_PMA_REG_MISC_CTRL,
2357 0x8288);
2358 bnx2x_cl45_write(bp, params->port,
2359 ext_phy_type,
2360 ext_phy_addr,
2361 MDIO_PMA_DEVAD,
2362 MDIO_PMA_REG_PHY_IDENTIFIER,
2363 0x7fbf);
2364 bnx2x_cl45_write(bp, params->port,
2365 ext_phy_type,
2366 ext_phy_addr,
2367 MDIO_PMA_DEVAD,
2368 MDIO_PMA_REG_CMU_PLL_BYPASS,
2369 0x0100);
2370 bnx2x_cl45_write(bp, params->port,
2371 ext_phy_type,
2372 ext_phy_addr,
2373 MDIO_WIS_DEVAD,
2374 MDIO_WIS_REG_LASI_CNTL, 0x1);
2375 break;
2376
2377 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2378 DP(NETIF_MSG_LINK, "XGXS 8706\n");
2379
2380 msleep(10);
2381 /* Force speed */
2382 /* First enable LASI */
2383 bnx2x_cl45_write(bp, params->port,
2384 ext_phy_type,
2385 ext_phy_addr,
2386 MDIO_PMA_DEVAD,
2387 MDIO_PMA_REG_RX_ALARM_CTRL,
2388 0x0400);
2389 bnx2x_cl45_write(bp, params->port,
2390 ext_phy_type,
2391 ext_phy_addr,
2392 MDIO_PMA_DEVAD,
2393 MDIO_PMA_REG_LASI_CTRL, 0x0004);
2394
2395 if (params->req_line_speed == SPEED_10000) {
2396 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
2397
2398 bnx2x_cl45_write(bp, params->port,
2399 ext_phy_type,
2400 ext_phy_addr,
2401 MDIO_PMA_DEVAD,
2402 MDIO_PMA_REG_DIGITAL_CTRL,
2403 0x400);
2404 } else {
2405 /* Force 1Gbps using autoneg with 1G
2406 advertisment */
2407
2408 /* Allow CL37 through CL73 */
2409 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
2410 bnx2x_cl45_write(bp, params->port,
2411 ext_phy_type,
2412 ext_phy_addr,
2413 MDIO_AN_DEVAD,
2414 MDIO_AN_REG_CL37_CL73,
2415 0x040c);
2416
2417 /* Enable Full-Duplex advertisment on CL37 */
2418 bnx2x_cl45_write(bp, params->port,
2419 ext_phy_type,
2420 ext_phy_addr,
2421 MDIO_AN_DEVAD,
2422 MDIO_AN_REG_CL37_FD,
2423 0x0020);
2424 /* Enable CL37 AN */
2425 bnx2x_cl45_write(bp, params->port,
2426 ext_phy_type,
2427 ext_phy_addr,
2428 MDIO_AN_DEVAD,
2429 MDIO_AN_REG_CL37_AN,
2430 0x1000);
2431 /* 1G support */
2432 bnx2x_cl45_write(bp, params->port,
2433 ext_phy_type,
2434 ext_phy_addr,
2435 MDIO_AN_DEVAD,
2436 MDIO_AN_REG_ADV, (1<<5));
2437
2438 /* Enable clause 73 AN */
2439 bnx2x_cl45_write(bp, params->port,
2440 ext_phy_type,
2441 ext_phy_addr,
2442 MDIO_AN_DEVAD,
2443 MDIO_AN_REG_CTRL,
2444 0x1200);
2445
2446 }
2447
2448 break;
2449
2450 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2451 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
2452 {
2453 u16 tmp1;
2454 u16 rx_alarm_ctrl_val;
2455 u16 lasi_ctrl_val;
2456 if (ext_phy_type ==
2457 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
2458 rx_alarm_ctrl_val = 0x400;
2459 lasi_ctrl_val = 0x0004;
2460 } else {
2461 /* In 8073, port1 is directed through emac0 and
2462 * port0 is directed through emac1
2463 */
2464 rx_alarm_ctrl_val = (1<<2);
2465 /*lasi_ctrl_val = 0x0005;*/
2466 lasi_ctrl_val = 0x0004;
2467 }
2468
2469 /* Wait for soft reset to get cleared upto 1 sec */
2470 for (cnt = 0; cnt < 1000; cnt++) {
2471 bnx2x_cl45_read(bp, params->port,
2472 ext_phy_type,
2473 ext_phy_addr,
2474 MDIO_PMA_DEVAD,
2475 MDIO_PMA_REG_CTRL,
2476 &ctrl);
2477 if (!(ctrl & (1<<15)))
2478 break;
2479 msleep(1);
2480 }
2481 DP(NETIF_MSG_LINK,
2482 "807x control reg 0x%x (after %d ms)\n",
2483 ctrl, cnt);
2484
2485 if (ext_phy_type ==
2486 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){
2487 bnx2x_bcm8072_external_rom_boot(params);
2488 } else {
2489 bnx2x_bcm8073_external_rom_boot(params);
2490 /* In case of 8073 with long xaui lines,
2491 don't set the 8073 xaui low power*/
2492 bnx2x_bcm8073_set_xaui_low_power_mode(params);
2493 }
2494
2495 /* enable LASI */
2496 bnx2x_cl45_write(bp, params->port,
2497 ext_phy_type,
2498 ext_phy_addr,
2499 MDIO_PMA_DEVAD,
2500 MDIO_PMA_REG_RX_ALARM_CTRL,
2501 rx_alarm_ctrl_val);
2502
2503 bnx2x_cl45_write(bp, params->port,
2504 ext_phy_type,
2505 ext_phy_addr,
2506 MDIO_PMA_DEVAD,
2507 MDIO_PMA_REG_LASI_CTRL,
2508 lasi_ctrl_val);
2509
2510 bnx2x_cl45_read(bp, params->port,
2511 ext_phy_type,
2512 ext_phy_addr,
2513 MDIO_PMA_DEVAD,
2514 MDIO_PMA_REG_RX_ALARM, &tmp1);
2515
2516 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1):"
2517 "0x%x\n", tmp1);
2518
2519 /* If this is forced speed, set to KR or KX
2520 * (all other are not supported)
2521 */
2522 if (!(params->req_line_speed == SPEED_AUTO_NEG)) {
2523 if (params->req_line_speed == SPEED_10000) {
2524 bnx2x_bcm807x_force_10G(params);
2525 DP(NETIF_MSG_LINK,
2526 "Forced speed 10G on 807X\n");
2527 break;
2528 } else if (params->req_line_speed ==
2529 SPEED_2500) {
2530 val = (1<<5);
2531 /* Note that 2.5G works only
2532 when used with 1G advertisment */
2533 } else
2534 val = (1<<5);
2535 } else {
2536
2537 val = 0;
2538 if (params->speed_cap_mask &
2539 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2540 val |= (1<<7);
2541
2542 if (params->speed_cap_mask &
2543 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2544 val |= (1<<5);
2545 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
2546 /*val = ((1<<5)|(1<<7));*/
2547 }
2548
2549 bnx2x_cl45_write(bp, params->port,
2550 ext_phy_type,
2551 ext_phy_addr,
2552 MDIO_AN_DEVAD,
2553 MDIO_AN_REG_ADV, val);
2554
2555 if (ext_phy_type ==
2556 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
2557 /* Disable 2.5Ghz */
2558 bnx2x_cl45_read(bp, params->port,
2559 ext_phy_type,
2560 ext_phy_addr,
2561 MDIO_AN_DEVAD,
2562 0x8329, &tmp1);
2563/* SUPPORT_SPEED_CAPABILITY
2564 (Due to the nature of the link order, its not
2565 possible to enable 2.5G within the autoneg
2566 capabilities)
2567 if (params->speed_cap_mask &
2568 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
2569*/
2570 if (params->req_line_speed == SPEED_2500) {
2571 u16 phy_ver;
2572 /* Allow 2.5G for A1 and above */
2573 bnx2x_cl45_read(bp, params->port,
2574 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2575 ext_phy_addr,
2576 MDIO_PMA_DEVAD,
2577 0xc801, &phy_ver);
2578
2579 if (phy_ver > 0)
2580 tmp1 |= 1;
2581 else
2582 tmp1 &= 0xfffe;
2583 }
2584 else
2585 tmp1 &= 0xfffe;
2586
2587 bnx2x_cl45_write(bp, params->port,
2588 ext_phy_type,
2589 ext_phy_addr,
2590 MDIO_AN_DEVAD,
2591 0x8329, tmp1);
2592 }
2593 /* Add support for CL37 (passive mode) I */
2594 bnx2x_cl45_write(bp, params->port,
2595 ext_phy_type,
2596 ext_phy_addr,
2597 MDIO_AN_DEVAD,
2598 MDIO_AN_REG_CL37_CL73, 0x040c);
2599 /* Add support for CL37 (passive mode) II */
2600 bnx2x_cl45_write(bp, params->port,
2601 ext_phy_type,
2602 ext_phy_addr,
2603 MDIO_AN_DEVAD,
2604 MDIO_AN_REG_CL37_FD, 0x20);
2605 /* Add support for CL37 (passive mode) III */
2606 bnx2x_cl45_write(bp, params->port,
2607 ext_phy_type,
2608 ext_phy_addr,
2609 MDIO_AN_DEVAD,
2610 MDIO_AN_REG_CL37_AN, 0x1000);
2611 /* Restart autoneg */
2612 msleep(500);
2613
2614 if (ext_phy_type ==
2615 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
2616
2617 /* The SNR will improve about 2db by changing the
2618 BW and FEE main tap. Rest commands are executed
2619 after link is up*/
2620 /* Change FFE main cursor to 5 in EDC register */
2621 if (bnx2x_8073_is_snr_needed(params))
2622 bnx2x_cl45_write(bp, params->port,
2623 ext_phy_type,
2624 ext_phy_addr,
2625 MDIO_PMA_DEVAD,
2626 MDIO_PMA_REG_EDC_FFE_MAIN,
2627 0xFB0C);
2628
2629 /* Enable FEC (Forware Error Correction)
2630 Request in the AN */
2631 bnx2x_cl45_read(bp, params->port,
2632 ext_phy_type,
2633 ext_phy_addr,
2634 MDIO_AN_DEVAD,
2635 MDIO_AN_REG_ADV2, &tmp1);
2636
2637 tmp1 |= (1<<15);
2638
2639 bnx2x_cl45_write(bp, params->port,
2640 ext_phy_type,
2641 ext_phy_addr,
2642 MDIO_AN_DEVAD,
2643 MDIO_AN_REG_ADV2, tmp1);
2644 }
2645
2646 bnx2x_ext_phy_set_pause(params, vars);
2647
2648 bnx2x_cl45_write(bp, params->port,
2649 ext_phy_type,
2650 ext_phy_addr,
2651 MDIO_AN_DEVAD,
2652 MDIO_AN_REG_CTRL, 0x1200);
2653 DP(NETIF_MSG_LINK, "807x Autoneg Restart: "
2654 "Advertise 1G=%x, 10G=%x\n",
2655 ((val & (1<<5)) > 0),
2656 ((val & (1<<7)) > 0));
2657 break;
2658 }
2659 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2660 DP(NETIF_MSG_LINK,
2661 "Setting the SFX7101 LASI indication\n");
2662
2663 bnx2x_cl45_write(bp, params->port,
2664 ext_phy_type,
2665 ext_phy_addr,
2666 MDIO_PMA_DEVAD,
2667 MDIO_PMA_REG_LASI_CTRL, 0x1);
2668 DP(NETIF_MSG_LINK,
2669 "Setting the SFX7101 LED to blink on traffic\n");
2670 bnx2x_cl45_write(bp, params->port,
2671 ext_phy_type,
2672 ext_phy_addr,
2673 MDIO_PMA_DEVAD,
2674 MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
2675
2676 bnx2x_ext_phy_set_pause(params, vars);
2677 /* Restart autoneg */
2678 bnx2x_cl45_read(bp, params->port,
2679 ext_phy_type,
2680 ext_phy_addr,
2681 MDIO_AN_DEVAD,
2682 MDIO_AN_REG_CTRL, &val);
2683 val |= 0x200;
2684 bnx2x_cl45_write(bp, params->port,
2685 ext_phy_type,
2686 ext_phy_addr,
2687 MDIO_AN_DEVAD,
2688 MDIO_AN_REG_CTRL, val);
2689 break;
2690 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2691 DP(NETIF_MSG_LINK,
2692 "XGXS PHY Failure detected 0x%x\n",
2693 params->ext_phy_config);
2694 rc = -EINVAL;
2695 break;
2696 default:
2697 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2698 params->ext_phy_config);
2699 rc = -EINVAL;
2700 break;
2701 }
2702
2703 } else { /* SerDes */
2704/* ext_phy_addr = ((bp->ext_phy_config &
2705 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >>
2706 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT);
2707*/
2708 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
2709 switch (ext_phy_type) {
2710 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2711 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2712 break;
2713
2714 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2715 DP(NETIF_MSG_LINK, "SerDes 5482\n");
2716 break;
2717
2718 default:
2719 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
2720 params->ext_phy_config);
2721 break;
2722 }
2723 }
2724 return rc;
2725}
2726
2727
2728static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2729 struct link_vars *vars)
2730{
2731 struct bnx2x *bp = params->bp;
2732 u32 ext_phy_type;
2733 u8 ext_phy_addr;
2734 u16 val1 = 0, val2;
2735 u16 rx_sd, pcs_status;
2736 u8 ext_phy_link_up = 0;
2737 u8 port = params->port;
2738 if (vars->phy_flags & PHY_XGXS_FLAG) {
2739 ext_phy_addr = ((params->ext_phy_config &
2740 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2741 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2742
2743 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2744 switch (ext_phy_type) {
2745 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2746 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2747 ext_phy_link_up = 1;
2748 break;
2749
2750 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
2751 DP(NETIF_MSG_LINK, "XGXS 8705\n");
2752 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2753 ext_phy_addr,
2754 MDIO_WIS_DEVAD,
2755 MDIO_WIS_REG_LASI_STATUS, &val1);
2756 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2757
2758 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2759 ext_phy_addr,
2760 MDIO_WIS_DEVAD,
2761 MDIO_WIS_REG_LASI_STATUS, &val1);
2762 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2763
2764 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2765 ext_phy_addr,
2766 MDIO_PMA_DEVAD,
2767 MDIO_PMA_REG_RX_SD, &rx_sd);
2768 DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd);
2769 ext_phy_link_up = (rx_sd & 0x1);
2770 break;
2771
2772 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2773 DP(NETIF_MSG_LINK, "XGXS 8706\n");
2774 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2775 ext_phy_addr,
2776 MDIO_PMA_DEVAD,
2777 MDIO_PMA_REG_LASI_STATUS, &val1);
2778 DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2779
2780 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2781 ext_phy_addr,
2782 MDIO_PMA_DEVAD,
2783 MDIO_PMA_REG_LASI_STATUS, &val1);
2784 DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2785
2786 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2787 ext_phy_addr,
2788 MDIO_PMA_DEVAD,
2789 MDIO_PMA_REG_RX_SD, &rx_sd);
2790 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2791 ext_phy_addr,
2792 MDIO_PCS_DEVAD,
2793 MDIO_PCS_REG_STATUS, &pcs_status);
2794
2795 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2796 ext_phy_addr,
2797 MDIO_AN_DEVAD,
2798 MDIO_AN_REG_LINK_STATUS, &val2);
2799 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2800 ext_phy_addr,
2801 MDIO_AN_DEVAD,
2802 MDIO_AN_REG_LINK_STATUS, &val2);
2803
2804 DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x"
2805 " pcs_status 0x%x 1Gbps link_status 0x%x\n",
2806 rx_sd, pcs_status, val2);
2807 /* link is up if both bit 0 of pmd_rx_sd and
2808 * bit 0 of pcs_status are set, or if the autoneg bit
2809 1 is set
2810 */
2811 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
2812 (val2 & (1<<1)));
2813 /* clear LASI indication*/
2814 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2815 ext_phy_addr,
2816 MDIO_PMA_DEVAD,
2817 MDIO_PMA_REG_RX_ALARM, &val2);
2818 break;
2819
2820 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2821 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
2822 {
2823 if (ext_phy_type ==
2824 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
2825 bnx2x_cl45_read(bp, params->port,
2826 ext_phy_type,
2827 ext_phy_addr,
2828 MDIO_PCS_DEVAD,
2829 MDIO_PCS_REG_LASI_STATUS, &val1);
2830 bnx2x_cl45_read(bp, params->port,
2831 ext_phy_type,
2832 ext_phy_addr,
2833 MDIO_PCS_DEVAD,
2834 MDIO_PCS_REG_LASI_STATUS, &val2);
2835 DP(NETIF_MSG_LINK,
2836 "870x LASI status 0x%x->0x%x\n",
2837 val1, val2);
2838
2839 } else {
2840 /* In 8073, port1 is directed through emac0 and
2841 * port0 is directed through emac1
2842 */
2843 bnx2x_cl45_read(bp, params->port,
2844 ext_phy_type,
2845 ext_phy_addr,
2846 MDIO_PMA_DEVAD,
2847 MDIO_PMA_REG_LASI_STATUS, &val1);
2848
2849 bnx2x_cl45_read(bp, params->port,
2850 ext_phy_type,
2851 ext_phy_addr,
2852 MDIO_PMA_DEVAD,
2853 MDIO_PMA_REG_LASI_STATUS, &val2);
2854 DP(NETIF_MSG_LINK,
2855 "8703 LASI status 0x%x->0x%x\n",
2856 val1, val2);
2857 }
2858
2859 /* clear the interrupt LASI status register */
2860 bnx2x_cl45_read(bp, params->port,
2861 ext_phy_type,
2862 ext_phy_addr,
2863 MDIO_PCS_DEVAD,
2864 MDIO_PCS_REG_STATUS, &val2);
2865 bnx2x_cl45_read(bp, params->port,
2866 ext_phy_type,
2867 ext_phy_addr,
2868 MDIO_PCS_DEVAD,
2869 MDIO_PCS_REG_STATUS, &val1);
2870 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
2871 val2, val1);
2872 /* Check the LASI */
2873 bnx2x_cl45_read(bp, params->port,
2874 ext_phy_type,
2875 ext_phy_addr,
2876 MDIO_PMA_DEVAD,
2877 MDIO_PMA_REG_RX_ALARM, &val2);
2878 bnx2x_cl45_read(bp, params->port,
2879 ext_phy_type,
2880 ext_phy_addr,
2881 MDIO_PMA_DEVAD,
2882 MDIO_PMA_REG_RX_ALARM,
2883 &val1);
2884 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x->0x%x\n",
2885 val2, val1);
2886 /* Check the link status */
2887 bnx2x_cl45_read(bp, params->port,
2888 ext_phy_type,
2889 ext_phy_addr,
2890 MDIO_PCS_DEVAD,
2891 MDIO_PCS_REG_STATUS, &val2);
2892 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
2893
2894 bnx2x_cl45_read(bp, params->port,
2895 ext_phy_type,
2896 ext_phy_addr,
2897 MDIO_PMA_DEVAD,
2898 MDIO_PMA_REG_STATUS, &val2);
2899 bnx2x_cl45_read(bp, params->port,
2900 ext_phy_type,
2901 ext_phy_addr,
2902 MDIO_PMA_DEVAD,
2903 MDIO_PMA_REG_STATUS, &val1);
2904 ext_phy_link_up = ((val1 & 4) == 4);
2905 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
2906 if (ext_phy_type ==
2907 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
2908 u16 an1000_status = 0;
2909 if (ext_phy_link_up &&
2910 (
2911 (params->req_line_speed != SPEED_10000)
2912 )) {
2913 if (bnx2x_bcm8073_xaui_wa(params)
2914 != 0) {
2915 ext_phy_link_up = 0;
2916 break;
2917 }
2918 bnx2x_cl45_read(bp, params->port,
2919 ext_phy_type,
2920 ext_phy_addr,
2921 MDIO_XS_DEVAD,
2922 0x8304,
2923 &an1000_status);
2924 bnx2x_cl45_read(bp, params->port,
2925 ext_phy_type,
2926 ext_phy_addr,
2927 MDIO_XS_DEVAD,
2928 0x8304,
2929 &an1000_status);
2930 }
2931 /* Check the link status on 1.1.2 */
2932 bnx2x_cl45_read(bp, params->port,
2933 ext_phy_type,
2934 ext_phy_addr,
2935 MDIO_PMA_DEVAD,
2936 MDIO_PMA_REG_STATUS, &val2);
2937 bnx2x_cl45_read(bp, params->port,
2938 ext_phy_type,
2939 ext_phy_addr,
2940 MDIO_PMA_DEVAD,
2941 MDIO_PMA_REG_STATUS, &val1);
2942 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
2943 "an_link_status=0x%x\n",
2944 val2, val1, an1000_status);
2945
2946 ext_phy_link_up = (((val1 & 4) == 4) ||
2947 (an1000_status & (1<<1)));
2948 if (ext_phy_link_up &&
2949 bnx2x_8073_is_snr_needed(params)) {
2950 /* The SNR will improve about 2dbby
2951 changing the BW and FEE main tap.*/
2952
2953 /* The 1st write to change FFE main
2954 tap is set before restart AN */
2955 /* Change PLL Bandwidth in EDC
2956 register */
2957 bnx2x_cl45_write(bp, port, ext_phy_type,
2958 ext_phy_addr,
2959 MDIO_PMA_DEVAD,
2960 MDIO_PMA_REG_PLL_BANDWIDTH,
2961 0x26BC);
2962
2963 /* Change CDR Bandwidth in EDC
2964 register */
2965 bnx2x_cl45_write(bp, port, ext_phy_type,
2966 ext_phy_addr,
2967 MDIO_PMA_DEVAD,
2968 MDIO_PMA_REG_CDR_BANDWIDTH,
2969 0x0333);
2970
2971 }
2972 }
2973 break;
2974 }
2975 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2976 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2977 ext_phy_addr,
2978 MDIO_PMA_DEVAD,
2979 MDIO_PMA_REG_LASI_STATUS, &val2);
2980 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2981 ext_phy_addr,
2982 MDIO_PMA_DEVAD,
2983 MDIO_PMA_REG_LASI_STATUS, &val1);
2984 DP(NETIF_MSG_LINK,
2985 "10G-base-T LASI status 0x%x->0x%x\n",
2986 val2, val1);
2987 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2988 ext_phy_addr,
2989 MDIO_PMA_DEVAD,
2990 MDIO_PMA_REG_STATUS, &val2);
2991 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2992 ext_phy_addr,
2993 MDIO_PMA_DEVAD,
2994 MDIO_PMA_REG_STATUS, &val1);
2995 DP(NETIF_MSG_LINK,
2996 "10G-base-T PMA status 0x%x->0x%x\n",
2997 val2, val1);
2998 ext_phy_link_up = ((val1 & 4) == 4);
2999 /* if link is up
3000 * print the AN outcome of the SFX7101 PHY
3001 */
3002 if (ext_phy_link_up) {
3003 bnx2x_cl45_read(bp, params->port,
3004 ext_phy_type,
3005 ext_phy_addr,
3006 MDIO_AN_DEVAD,
3007 MDIO_AN_REG_MASTER_STATUS,
3008 &val2);
3009 DP(NETIF_MSG_LINK,
3010 "SFX7101 AN status 0x%x->Master=%x\n",
3011 val2,
3012 (val2 & (1<<14)));
3013 }
3014 break;
3015
3016 default:
3017 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
3018 params->ext_phy_config);
3019 ext_phy_link_up = 0;
3020 break;
3021 }
3022
3023 } else { /* SerDes */
3024 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
3025 switch (ext_phy_type) {
3026 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
3027 DP(NETIF_MSG_LINK, "SerDes Direct\n");
3028 ext_phy_link_up = 1;
3029 break;
3030
3031 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
3032 DP(NETIF_MSG_LINK, "SerDes 5482\n");
3033 ext_phy_link_up = 1;
3034 break;
3035
3036 default:
3037 DP(NETIF_MSG_LINK,
3038 "BAD SerDes ext_phy_config 0x%x\n",
3039 params->ext_phy_config);
3040 ext_phy_link_up = 0;
3041 break;
3042 }
3043 }
3044
3045 return ext_phy_link_up;
3046}
3047
3048static void bnx2x_link_int_enable(struct link_params *params)
3049{
3050 u8 port = params->port;
3051 u32 ext_phy_type;
3052 u32 mask;
3053 struct bnx2x *bp = params->bp;
3054 /* setting the status to report on link up
3055 for either XGXS or SerDes */
3056
3057 if (params->switch_cfg == SWITCH_CFG_10G) {
3058 mask = (NIG_MASK_XGXS0_LINK10G |
3059 NIG_MASK_XGXS0_LINK_STATUS);
3060 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
3061 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3062 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3063 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3064 (ext_phy_type !=
3065 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
3066 mask |= NIG_MASK_MI_INT;
3067 DP(NETIF_MSG_LINK, "enabled external phy int\n");
3068 }
3069
3070 } else { /* SerDes */
3071 mask = NIG_MASK_SERDES0_LINK_STATUS;
3072 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
3073 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
3074 if ((ext_phy_type !=
3075 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
3076 (ext_phy_type !=
3077 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
3078 mask |= NIG_MASK_MI_INT;
3079 DP(NETIF_MSG_LINK, "enabled external phy int\n");
3080 }
3081 }
3082 bnx2x_bits_en(bp,
3083 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3084 mask);
3085 DP(NETIF_MSG_LINK, "port %x, is_xgxs=%x, int_status 0x%x\n", port,
3086 (params->switch_cfg == SWITCH_CFG_10G),
3087 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3088
3089 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
3090 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3091 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
3092 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
3093 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3094 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3095 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3096}
3097
3098
3099/*
3100 * link management
3101 */
3102static void bnx2x_link_int_ack(struct link_params *params,
3103 struct link_vars *vars, u16 is_10g)
3104{
3105 struct bnx2x *bp = params->bp;
3106 u8 port = params->port;
3107
3108 /* first reset all status
3109 * we assume only one line will be change at a time */
3110 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3111 (NIG_STATUS_XGXS0_LINK10G |
3112 NIG_STATUS_XGXS0_LINK_STATUS |
3113 NIG_STATUS_SERDES0_LINK_STATUS));
3114 if (vars->phy_link_up) {
3115 if (is_10g) {
3116 /* Disable the 10G link interrupt
3117 * by writing 1 to the status register
3118 */
3119 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
3120 bnx2x_bits_en(bp,
3121 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3122 NIG_STATUS_XGXS0_LINK10G);
3123
3124 } else if (params->switch_cfg == SWITCH_CFG_10G) {
3125 /* Disable the link interrupt
3126 * by writing 1 to the relevant lane
3127 * in the status register
3128 */
3129 u32 ser_lane = ((params->lane_config &
3130 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3131 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3132
3133 DP(NETIF_MSG_LINK, "1G XGXS phy link up\n");
3134 bnx2x_bits_en(bp,
3135 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3136 ((1 << ser_lane) <<
3137 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
3138
3139 } else { /* SerDes */
3140 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
3141 /* Disable the link interrupt
3142 * by writing 1 to the status register
3143 */
3144 bnx2x_bits_en(bp,
3145 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3146 NIG_STATUS_SERDES0_LINK_STATUS);
3147 }
3148
3149 } else { /* link_down */
3150 }
3151}
3152
3153static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
3154{
3155 u8 *str_ptr = str;
3156 u32 mask = 0xf0000000;
3157 u8 shift = 8*4;
3158 u8 digit;
3159 if (len < 10) {
3160 /* Need more then 10chars for this format */
3161 *str_ptr = '\0';
3162 return -EINVAL;
3163 }
3164 while (shift > 0) {
3165
3166 shift -= 4;
3167 digit = ((num & mask) >> shift);
3168 if (digit < 0xa)
3169 *str_ptr = digit + '0';
3170 else
3171 *str_ptr = digit - 0xa + 'a';
3172 str_ptr++;
3173 mask = mask >> 4;
3174 if (shift == 4*4) {
3175 *str_ptr = ':';
3176 str_ptr++;
3177 }
3178 }
3179 *str_ptr = '\0';
3180 return 0;
3181}
3182
3183
3184static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
3185{
3186 u32 cnt = 0;
3187 u16 ctrl = 0;
3188 /* Enable EMAC0 in to enable MDIO */
3189 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
3190 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
3191 msleep(5);
3192
3193 /* take ext phy out of reset */
3194 bnx2x_set_gpio(bp,
3195 MISC_REGISTERS_GPIO_2,
3196 MISC_REGISTERS_GPIO_HIGH);
3197
3198 bnx2x_set_gpio(bp,
3199 MISC_REGISTERS_GPIO_1,
3200 MISC_REGISTERS_GPIO_HIGH);
3201
3202 /* wait for 5ms */
3203 msleep(5);
3204
3205 for (cnt = 0; cnt < 1000; cnt++) {
3206 msleep(1);
3207 bnx2x_cl45_read(bp, port,
3208 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
3209 ext_phy_addr,
3210 MDIO_PMA_DEVAD,
3211 MDIO_PMA_REG_CTRL,
3212 &ctrl);
3213 if (!(ctrl & (1<<15))) {
3214 DP(NETIF_MSG_LINK, "Reset completed\n\n");
3215 break;
3216 }
3217 }
3218}
3219
3220static void bnx2x_turn_off_sf(struct bnx2x *bp)
3221{
3222 /* put sf to reset */
3223 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, MISC_REGISTERS_GPIO_LOW);
3224 bnx2x_set_gpio(bp,
3225 MISC_REGISTERS_GPIO_2,
3226 MISC_REGISTERS_GPIO_LOW);
3227}
3228
3229u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3230 u8 *version, u16 len)
3231{
3232 struct bnx2x *bp = params->bp;
3233 u32 ext_phy_type = 0;
3234 u16 val = 0;
3235 u8 ext_phy_addr = 0 ;
3236 u8 status = 0 ;
3237 u32 ver_num;
3238
3239 if (version == NULL || params == NULL)
3240 return -EINVAL;
3241
3242 /* reset the returned value to zero */
3243 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3244 ext_phy_addr = ((params->ext_phy_config &
3245 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3246 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3247
3248 switch (ext_phy_type) {
3249 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3250
3251 if (len < 5)
3252 return -EINVAL;
3253
3254 /* Take ext phy out of reset */
3255 if (!driver_loaded)
3256 bnx2x_turn_on_sf(bp, params->port, ext_phy_addr);
3257
3258 /* wait for 1ms */
3259 msleep(1);
3260
3261 bnx2x_cl45_read(bp, params->port,
3262 ext_phy_type,
3263 ext_phy_addr,
3264 MDIO_PMA_DEVAD,
3265 MDIO_PMA_REG_7101_VER1, &val);
3266 version[2] = (val & 0xFF);
3267 version[3] = ((val & 0xFF00)>>8);
3268
3269 bnx2x_cl45_read(bp, params->port,
3270 ext_phy_type,
3271 ext_phy_addr,
3272 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2,
3273 &val);
3274 version[0] = (val & 0xFF);
3275 version[1] = ((val & 0xFF00)>>8);
3276 version[4] = '\0';
3277
3278 if (!driver_loaded)
3279 bnx2x_turn_off_sf(bp);
3280 break;
3281 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3282 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3283 {
3284 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3285 ext_phy_addr,
3286 MDIO_PMA_DEVAD,
3287 MDIO_PMA_REG_ROM_VER1, &val);
3288 ver_num = val<<16;
3289 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3290 ext_phy_addr,
3291 MDIO_PMA_DEVAD,
3292 MDIO_PMA_REG_ROM_VER2, &val);
3293 ver_num |= val;
3294 status = bnx2x_format_ver(ver_num, version, len);
3295 break;
3296 }
3297 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3298 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3299
3300 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3301 ext_phy_addr,
3302 MDIO_PMA_DEVAD,
3303 MDIO_PMA_REG_ROM_VER1, &val);
3304 ver_num = val<<16;
3305 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3306 ext_phy_addr,
3307 MDIO_PMA_DEVAD,
3308 MDIO_PMA_REG_ROM_VER2, &val);
3309 ver_num |= val;
3310 status = bnx2x_format_ver(ver_num, version, len);
3311 break;
3312
3313 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3314 break;
3315
3316 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
3317 DP(NETIF_MSG_LINK, "bnx2x_get_ext_phy_fw_version:"
3318 " type is FAILURE!\n");
3319 status = -EINVAL;
3320 break;
3321
3322 default:
3323 break;
3324 }
3325 return status;
3326}
3327
3328static void bnx2x_set_xgxs_loopback(struct link_params *params,
3329 struct link_vars *vars,
3330 u8 is_10g)
3331{
3332 u8 port = params->port;
3333 struct bnx2x *bp = params->bp;
3334
3335 if (is_10g) {
3336 u32 md_devad;
3337
3338 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3339
3340 /* change the uni_phy_addr in the nig */
3341 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3342 port*0x18));
3343
3344 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3345
3346 bnx2x_cl45_write(bp, port, 0,
3347 params->phy_addr,
3348 5,
3349 (MDIO_REG_BANK_AER_BLOCK +
3350 (MDIO_AER_BLOCK_AER_REG & 0xf)),
3351 0x2800);
3352
3353 bnx2x_cl45_write(bp, port, 0,
3354 params->phy_addr,
3355 5,
3356 (MDIO_REG_BANK_CL73_IEEEB0 +
3357 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3358 0x6041);
3359
3360 /* set aer mmd back */
3361 bnx2x_set_aer_mmd(params, vars);
3362
3363 /* and md_devad */
3364 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3365 md_devad);
3366
3367 } else {
3368 u16 mii_control;
3369
3370 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3371
3372 CL45_RD_OVER_CL22(bp, port,
3373 params->phy_addr,
3374 MDIO_REG_BANK_COMBO_IEEE0,
3375 MDIO_COMBO_IEEE0_MII_CONTROL,
3376 &mii_control);
3377
3378 CL45_WR_OVER_CL22(bp, port,
3379 params->phy_addr,
3380 MDIO_REG_BANK_COMBO_IEEE0,
3381 MDIO_COMBO_IEEE0_MII_CONTROL,
3382 (mii_control |
3383 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
3384 }
3385}
3386
3387
3388static void bnx2x_ext_phy_loopback(struct link_params *params)
3389{
3390 struct bnx2x *bp = params->bp;
3391 u8 ext_phy_addr;
3392 u32 ext_phy_type;
3393
3394 if (params->switch_cfg == SWITCH_CFG_10G) {
3395 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3396 /* CL37 Autoneg Enabled */
3397 ext_phy_addr = ((params->ext_phy_config &
3398 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3399 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3400 switch (ext_phy_type) {
3401 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3402 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
3403 DP(NETIF_MSG_LINK,
3404 "ext_phy_loopback: We should not get here\n");
3405 break;
3406 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3407 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8705\n");
3408 break;
3409 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3410 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8706\n");
3411 break;
3412 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3413 /* SFX7101_XGXS_TEST1 */
3414 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3415 ext_phy_addr,
3416 MDIO_XS_DEVAD,
3417 MDIO_XS_SFX7101_XGXS_TEST1,
3418 0x100);
3419 DP(NETIF_MSG_LINK,
3420 "ext_phy_loopback: set ext phy loopback\n");
3421 break;
3422 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3423
3424 break;
3425 } /* switch external PHY type */
3426 } else {
3427 /* serdes */
3428 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
3429 ext_phy_addr = (params->ext_phy_config &
3430 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK)
3431 >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT;
3432 }
3433}
3434
3435
3436/*
3437 *------------------------------------------------------------------------
3438 * bnx2x_override_led_value -
3439 *
3440 * Override the led value of the requsted led
3441 *
3442 *------------------------------------------------------------------------
3443 */
3444u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
3445 u32 led_idx, u32 value)
3446{
3447 u32 reg_val;
3448
3449 /* If port 0 then use EMAC0, else use EMAC1*/
3450 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3451
3452 DP(NETIF_MSG_LINK,
3453 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
3454 port, led_idx, value);
3455
3456 switch (led_idx) {
3457 case 0: /* 10MB led */
3458 /* Read the current value of the LED register in
3459 the EMAC block */
3460 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
3461 /* Set the OVERRIDE bit to 1 */
3462 reg_val |= EMAC_LED_OVERRIDE;
3463 /* If value is 1, set the 10M_OVERRIDE bit,
3464 otherwise reset it.*/
3465 reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
3466 (reg_val & ~EMAC_LED_10MB_OVERRIDE);
3467 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
3468 break;
3469 case 1: /*100MB led */
3470 /*Read the current value of the LED register in
3471 the EMAC block */
3472 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
3473 /* Set the OVERRIDE bit to 1 */
3474 reg_val |= EMAC_LED_OVERRIDE;
3475 /* If value is 1, set the 100M_OVERRIDE bit,
3476 otherwise reset it.*/
3477 reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
3478 (reg_val & ~EMAC_LED_100MB_OVERRIDE);
3479 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
3480 break;
3481 case 2: /* 1000MB led */
3482 /* Read the current value of the LED register in the
3483 EMAC block */
3484 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
3485 /* Set the OVERRIDE bit to 1 */
3486 reg_val |= EMAC_LED_OVERRIDE;
3487 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
3488 reset it. */
3489 reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
3490 (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
3491 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
3492 break;
3493 case 3: /* 2500MB led */
3494 /* Read the current value of the LED register in the
3495 EMAC block*/
3496 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
3497 /* Set the OVERRIDE bit to 1 */
3498 reg_val |= EMAC_LED_OVERRIDE;
3499 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
3500 reset it.*/
3501 reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
3502 (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
3503 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
3504 break;
3505 case 4: /*10G led */
3506 if (port == 0) {
3507 REG_WR(bp, NIG_REG_LED_10G_P0,
3508 value);
3509 } else {
3510 REG_WR(bp, NIG_REG_LED_10G_P1,
3511 value);
3512 }
3513 break;
3514 case 5: /* TRAFFIC led */
3515 /* Find if the traffic control is via BMAC or EMAC */
3516 if (port == 0)
3517 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
3518 else
3519 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
3520
3521 /* Override the traffic led in the EMAC:*/
3522 if (reg_val == 1) {
3523 /* Read the current value of the LED register in
3524 the EMAC block */
3525 reg_val = REG_RD(bp, emac_base +
3526 EMAC_REG_EMAC_LED);
3527 /* Set the TRAFFIC_OVERRIDE bit to 1 */
3528 reg_val |= EMAC_LED_OVERRIDE;
3529 /* If value is 1, set the TRAFFIC bit, otherwise
3530 reset it.*/
3531 reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
3532 (reg_val & ~EMAC_LED_TRAFFIC);
3533 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
3534 } else { /* Override the traffic led in the BMAC: */
3535 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3536 + port*4, 1);
3537 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
3538 value);
3539 }
3540 break;
3541 default:
3542 DP(NETIF_MSG_LINK,
3543 "bnx2x_override_led_value() unknown led index %d "
3544 "(should be 0-5)\n", led_idx);
3545 return -EINVAL;
3546 }
3547
3548 return 0;
3549}
3550
3551
3552u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
3553 u16 hw_led_mode, u32 chip_id)
3554{
3555 u8 rc = 0;
3556 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3557 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3558 speed, hw_led_mode);
3559 switch (mode) {
3560 case LED_MODE_OFF:
3561 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3562 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3563 SHARED_HW_CFG_LED_MAC1);
3564 break;
3565
3566 case LED_MODE_OPER:
3567 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
3568 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
3569 port*4, 0);
3570 /* Set blinking rate to ~15.9Hz */
3571 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3572 LED_BLINK_RATE_VAL);
3573 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3574 port*4, 1);
3575 if (!CHIP_IS_E1H(bp) &&
3576 ((speed == SPEED_2500) ||
3577 (speed == SPEED_1000) ||
3578 (speed == SPEED_100) ||
3579 (speed == SPEED_10))) {
3580 /* On Everest 1 Ax chip versions for speeds less than
3581 10G LED scheme is different */
3582 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3583 + port*4, 1);
3584 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3585 port*4, 0);
3586 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3587 port*4, 1);
3588 }
3589 break;
3590
3591 default:
3592 rc = -EINVAL;
3593 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3594 mode);
3595 break;
3596 }
3597 return rc;
3598
3599}
3600
3601u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
3602{
3603 struct bnx2x *bp = params->bp;
3604 u16 gp_status = 0;
3605
3606 CL45_RD_OVER_CL22(bp, params->port,
3607 params->phy_addr,
3608 MDIO_REG_BANK_GP_STATUS,
3609 MDIO_GP_STATUS_TOP_AN_STATUS1,
3610 &gp_status);
3611 /* link is up only if both local phy and external phy are up */
3612 if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
3613 bnx2x_ext_phy_is_link_up(params, vars))
3614 return 0;
3615
3616 return -ESRCH;
3617}
3618
3619static u8 bnx2x_link_initialize(struct link_params *params,
3620 struct link_vars *vars)
3621{
3622 struct bnx2x *bp = params->bp;
3623 u8 port = params->port;
3624 u8 rc = 0;
3625
3626 /* Activate the external PHY */
3627 bnx2x_ext_phy_reset(params, vars);
3628
3629 bnx2x_set_aer_mmd(params, vars);
3630
3631 if (vars->phy_flags & PHY_XGXS_FLAG)
3632 bnx2x_set_master_ln(params);
3633
3634 rc = bnx2x_reset_unicore(params);
3635 /* reset the SerDes and wait for reset bit return low */
3636 if (rc != 0)
3637 return rc;
3638
3639 bnx2x_set_aer_mmd(params, vars);
3640
3641 /* setting the masterLn_def again after the reset */
3642 if (vars->phy_flags & PHY_XGXS_FLAG) {
3643 bnx2x_set_master_ln(params);
3644 bnx2x_set_swap_lanes(params);
3645 }
3646
3647 /* Set Parallel Detect */
3648 if (params->req_line_speed == SPEED_AUTO_NEG)
3649 bnx2x_set_parallel_detection(params, vars->phy_flags);
3650
3651 if (vars->phy_flags & PHY_XGXS_FLAG) {
3652 if (params->req_line_speed &&
3653 ((params->req_line_speed == SPEED_100) ||
3654 (params->req_line_speed == SPEED_10))) {
3655 vars->phy_flags |= PHY_SGMII_FLAG;
3656 } else {
3657 vars->phy_flags &= ~PHY_SGMII_FLAG;
3658 }
3659 }
3660
3661 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
3662 u16 bank, rx_eq;
3663
3664 rx_eq = ((params->serdes_config &
3665 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
3666 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
3667
3668 DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq);
3669 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
3670 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) {
3671 CL45_WR_OVER_CL22(bp, port,
3672 params->phy_addr,
3673 bank ,
3674 MDIO_RX0_RX_EQ_BOOST,
3675 ((rx_eq &
3676 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
3677 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
3678 }
3679
3680 /* forced speed requested? */
3681 if (params->req_line_speed != SPEED_AUTO_NEG) {
3682 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3683
3684 /* disable autoneg */
3685 bnx2x_set_autoneg(params, vars);
3686
3687 /* program speed and duplex */
3688 bnx2x_program_serdes(params);
3689 vars->ieee_fc =
3690 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3691
3692 } else { /* AN_mode */
3693 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3694
3695 /* AN enabled */
3696 bnx2x_set_brcm_cl37_advertisment(params);
3697
3698 /* program duplex & pause advertisement (for aneg) */
3699 bnx2x_set_ieee_aneg_advertisment(params,
3700 &vars->ieee_fc);
3701
3702 /* enable autoneg */
3703 bnx2x_set_autoneg(params, vars);
3704
3705 /* enable and restart AN */
3706 bnx2x_restart_autoneg(params);
3707 }
3708
3709 } else { /* SGMII mode */
3710 DP(NETIF_MSG_LINK, "SGMII\n");
3711
3712 bnx2x_initialize_sgmii_process(params);
3713 }
3714
3715 /* init ext phy and enable link state int */
3716 rc |= bnx2x_ext_phy_init(params, vars);
3717
3718 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3719 (NIG_STATUS_XGXS0_LINK10G |
3720 NIG_STATUS_XGXS0_LINK_STATUS |
3721 NIG_STATUS_SERDES0_LINK_STATUS));
3722
3723 return rc;
3724
3725}
3726
3727
3728u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
3729{
3730 struct bnx2x *bp = params->bp;
3731
3732 u32 val;
3733 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
3734 DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n",
3735 params->req_line_speed, params->req_flow_ctrl);
3736 vars->link_status = 0;
3737 if (params->switch_cfg == SWITCH_CFG_1G)
3738 vars->phy_flags = PHY_SERDES_FLAG;
3739 else
3740 vars->phy_flags = PHY_XGXS_FLAG;
3741
3742 /* disable attentions */
3743 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
3744 (NIG_MASK_XGXS0_LINK_STATUS |
3745 NIG_MASK_XGXS0_LINK10G |
3746 NIG_MASK_SERDES0_LINK_STATUS |
3747 NIG_MASK_MI_INT));
3748
3749 bnx2x_emac_init(params, vars);
3750
3751 if (CHIP_REV_IS_FPGA(bp)) {
3752 vars->link_up = 1;
3753 vars->line_speed = SPEED_10000;
3754 vars->duplex = DUPLEX_FULL;
3755 vars->flow_ctrl = FLOW_CTRL_NONE;
3756 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
3757 /* enable on E1.5 FPGA */
3758 if (CHIP_IS_E1H(bp)) {
3759 vars->flow_ctrl |=
3760 (FLOW_CTRL_TX | FLOW_CTRL_RX);
3761 vars->link_status |=
3762 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
3763 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
3764 }
3765
3766 bnx2x_emac_enable(params, vars, 0);
3767 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
3768 /* disable drain */
3769 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
3770 + params->port*4, 0);
3771
3772 /* update shared memory */
3773 bnx2x_update_mng(params, vars->link_status);
3774
3775 return 0;
3776
3777 } else
3778 if (CHIP_REV_IS_EMUL(bp)) {
3779
3780 vars->link_up = 1;
3781 vars->line_speed = SPEED_10000;
3782 vars->duplex = DUPLEX_FULL;
3783 vars->flow_ctrl = FLOW_CTRL_NONE;
3784 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
3785
3786 bnx2x_bmac_enable(params, vars, 0);
3787
3788 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
3789 /* Disable drain */
3790 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
3791 + params->port*4, 0);
3792
3793 /* update shared memory */
3794 bnx2x_update_mng(params, vars->link_status);
3795
3796 return 0;
3797
3798 } else
3799 if (params->loopback_mode == LOOPBACK_BMAC) {
3800 vars->link_up = 1;
3801 vars->line_speed = SPEED_10000;
3802 vars->duplex = DUPLEX_FULL;
3803 vars->flow_ctrl = FLOW_CTRL_NONE;
3804 vars->mac_type = MAC_TYPE_BMAC;
3805
3806 vars->phy_flags = PHY_XGXS_FLAG;
3807
3808 bnx2x_phy_deassert(params, vars->phy_flags);
3809 /* set bmac loopback */
3810 bnx2x_bmac_enable(params, vars, 1);
3811
3812 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
3813 params->port*4, 0);
3814 } else if (params->loopback_mode == LOOPBACK_EMAC) {
3815 vars->link_up = 1;
3816 vars->line_speed = SPEED_1000;
3817 vars->duplex = DUPLEX_FULL;
3818 vars->flow_ctrl = FLOW_CTRL_NONE;
3819 vars->mac_type = MAC_TYPE_EMAC;
3820
3821 vars->phy_flags = PHY_XGXS_FLAG;
3822
3823 bnx2x_phy_deassert(params, vars->phy_flags);
3824 /* set bmac loopback */
3825 bnx2x_emac_enable(params, vars, 1);
3826 bnx2x_emac_program(params, vars->line_speed,
3827 vars->duplex);
3828 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
3829 params->port*4, 0);
3830 } else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
3831 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3832 vars->link_up = 1;
3833 vars->line_speed = SPEED_10000;
3834 vars->duplex = DUPLEX_FULL;
3835 vars->flow_ctrl = FLOW_CTRL_NONE;
3836
3837 vars->phy_flags = PHY_XGXS_FLAG;
3838
3839 val = REG_RD(bp,
3840 NIG_REG_XGXS0_CTRL_PHY_ADDR+
3841 params->port*0x18);
3842 params->phy_addr = (u8)val;
3843
3844 bnx2x_phy_deassert(params, vars->phy_flags);
3845 bnx2x_link_initialize(params, vars);
3846
3847 vars->mac_type = MAC_TYPE_BMAC;
3848
3849 bnx2x_bmac_enable(params, vars, 0);
3850
3851 if (params->loopback_mode == LOOPBACK_XGXS_10) {
3852 /* set 10G XGXS loopback */
3853 bnx2x_set_xgxs_loopback(params, vars, 1);
3854 } else {
3855 /* set external phy loopback */
3856 bnx2x_ext_phy_loopback(params);
3857 }
3858 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
3859 params->port*4, 0);
3860 } else
3861 /* No loopback */
3862 {
3863
3864 bnx2x_phy_deassert(params, vars->phy_flags);
3865 switch (params->switch_cfg) {
3866 case SWITCH_CFG_1G:
3867 vars->phy_flags |= PHY_SERDES_FLAG;
3868 if ((params->ext_phy_config &
3869 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ==
3870 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) {
3871 vars->phy_flags |=
3872 PHY_SGMII_FLAG;
3873 }
3874
3875 val = REG_RD(bp,
3876 NIG_REG_SERDES0_CTRL_PHY_ADDR+
3877 params->port*0x10);
3878
3879 params->phy_addr = (u8)val;
3880
3881 break;
3882 case SWITCH_CFG_10G:
3883 vars->phy_flags |= PHY_XGXS_FLAG;
3884 val = REG_RD(bp,
3885 NIG_REG_XGXS0_CTRL_PHY_ADDR+
3886 params->port*0x18);
3887 params->phy_addr = (u8)val;
3888
3889 break;
3890 default:
3891 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
3892 return -EINVAL;
3893 break;
3894 }
3895
3896 bnx2x_link_initialize(params, vars);
3897 bnx2x_link_int_enable(params);
3898 }
3899 return 0;
3900}
3901
3902u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
3903{
3904
3905 struct bnx2x *bp = params->bp;
3906 u32 ext_phy_config = params->ext_phy_config;
3907 u16 hw_led_mode = params->hw_led_mode;
3908 u32 chip_id = params->chip_id;
3909 u8 port = params->port;
3910 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
3911 /* disable attentions */
3912
3913 vars->link_status = 0;
3914 bnx2x_update_mng(params, vars->link_status);
3915 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3916 (NIG_MASK_XGXS0_LINK_STATUS |
3917 NIG_MASK_XGXS0_LINK10G |
3918 NIG_MASK_SERDES0_LINK_STATUS |
3919 NIG_MASK_MI_INT));
3920
3921 /* activate nig drain */
3922 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3923
3924 /* disable nig egress interface */
3925 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
3926 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
3927
3928 /* Stop BigMac rx */
3929 bnx2x_bmac_rx_disable(bp, port);
3930
3931 /* disable emac */
3932 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3933
3934 msleep(10);
3935 /* The PHY reset is controled by GPIO 1
3936 * Hold it as vars low
3937 */
3938 /* clear link led */
3939 bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id);
3940 if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
3941 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
3942 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
3943 /* HW reset */
3944
3945 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3946 MISC_REGISTERS_GPIO_OUTPUT_LOW);
3947
3948 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3949 MISC_REGISTERS_GPIO_OUTPUT_LOW);
3950
3951 DP(NETIF_MSG_LINK, "reset external PHY\n");
3952 } else {
3953
3954 u8 ext_phy_addr = ((ext_phy_config &
3955 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3956 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3957
3958 /* SW reset */
3959 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3960 MDIO_PMA_DEVAD,
3961 MDIO_PMA_REG_CTRL,
3962 1<<15);
3963
3964 /* Set Low Power Mode */
3965 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3966 MDIO_PMA_DEVAD,
3967 MDIO_PMA_REG_CTRL,
3968 1<<11);
3969
3970
3971 if (ext_phy_type ==
3972 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
3973 DP(NETIF_MSG_LINK, "Setting 8073 port %d into"
3974 "low power mode\n",
3975 port);
3976 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3977 MISC_REGISTERS_GPIO_OUTPUT_LOW);
3978 }
3979 }
3980 }
3981 /* reset the SerDes/XGXS */
3982 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3983 (0x1ff << (port*16)));
3984
3985 /* reset BigMac */
3986 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3987 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3988
3989 /* disable nig ingress interface */
3990 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
3991 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
3992 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
3993 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
3994 vars->link_up = 0;
3995 return 0;
3996}
3997
3998/* This function should called upon link interrupt */
3999/* In case vars->link_up, driver needs to
4000 1. Update the pbf
4001 2. Disable drain
4002 3. Update the shared memory
4003 4. Indicate link up
4004 5. Set LEDs
4005 Otherwise,
4006 1. Update shared memory
4007 2. Reset BigMac
4008 3. Report link down
4009 4. Unset LEDs
4010*/
4011u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4012{
4013 struct bnx2x *bp = params->bp;
4014 u8 port = params->port;
4015 u16 i;
4016 u16 gp_status;
4017 u16 link_10g;
4018 u8 rc = 0;
4019
4020 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
4021 port,
4022 (vars->phy_flags & PHY_XGXS_FLAG),
4023 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
4024
4025 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
4026 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
4027 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
4028 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
4029
4030 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
4031 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
4032 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4033
4034
4035 /* avoid fast toggling */
4036 for (i = 0; i < 10; i++) {
4037 msleep(10);
4038 CL45_RD_OVER_CL22(bp, port, params->phy_addr,
4039 MDIO_REG_BANK_GP_STATUS,
4040 MDIO_GP_STATUS_TOP_AN_STATUS1,
4041 &gp_status);
4042 }
4043
4044 rc = bnx2x_link_settings_status(params, vars, gp_status);
4045 if (rc != 0)
4046 return rc;
4047
4048 /* anything 10 and over uses the bmac */
4049 link_10g = ((vars->line_speed == SPEED_10000) ||
4050 (vars->line_speed == SPEED_12000) ||
4051 (vars->line_speed == SPEED_12500) ||
4052 (vars->line_speed == SPEED_13000) ||
4053 (vars->line_speed == SPEED_15000) ||
4054 (vars->line_speed == SPEED_16000));
4055
4056 bnx2x_link_int_ack(params, vars, link_10g);
4057
4058 /* link is up only if both local phy and external phy are up */
4059 vars->link_up = (vars->phy_link_up &&
4060 bnx2x_ext_phy_is_link_up(params, vars));
4061
4062 if (!vars->phy_link_up &&
4063 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18)) {
4064 bnx2x_ext_phy_is_link_up(params, vars); /* Clear interrupt */
4065 }
4066
4067 if (vars->link_up) {
4068 vars->link_status |= LINK_STATUS_LINK_UP;
4069 if (link_10g) {
4070 bnx2x_bmac_enable(params, vars, 0);
4071 bnx2x_set_led(bp, port, LED_MODE_OPER,
4072 SPEED_10000, params->hw_led_mode,
4073 params->chip_id);
4074
4075 } else {
4076 bnx2x_emac_enable(params, vars, 0);
4077 rc = bnx2x_emac_program(params, vars->line_speed,
4078 vars->duplex);
4079
4080 /* AN complete? */
4081 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
4082 if (!(vars->phy_flags &
4083 PHY_SGMII_FLAG))
4084 bnx2x_set_sgmii_tx_driver(params);
4085 }
4086 }
4087
4088 /* PBF - link up */
4089 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
4090 vars->line_speed);
4091
4092 /* disable drain */
4093 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
4094
4095 /* update shared memory */
4096 bnx2x_update_mng(params, vars->link_status);
4097
4098 } else { /* link down */
4099 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", params->port);
4100 bnx2x_set_led(bp, port, LED_MODE_OFF,
4101 0, params->hw_led_mode,
4102 params->chip_id);
4103
4104 /* indicate no mac active */
4105 vars->mac_type = MAC_TYPE_NONE;
4106
4107 /* update shared memory */
4108 vars->link_status = 0;
4109 bnx2x_update_mng(params, vars->link_status);
4110
4111 /* activate nig drain */
4112 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
4113
4114 /* reset BigMac */
4115 bnx2x_bmac_rx_disable(bp, params->port);
4116 REG_WR(bp, GRCBASE_MISC +
4117 MISC_REGISTERS_RESET_REG_2_CLEAR,
4118 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
4119
4120 }
4121
4122 return rc;
4123}
4124
4125static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
4126{
4127 u16 val, cnt;
4128
4129 bnx2x_cl45_read(bp, port,
4130 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4131 phy_addr,
4132 MDIO_PMA_DEVAD,
4133 MDIO_PMA_REG_7101_RESET, &val);
4134
4135 for (cnt = 0; cnt < 10; cnt++) {
4136 msleep(50);
4137 /* Writes a self-clearing reset */
4138 bnx2x_cl45_write(bp, port,
4139 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4140 phy_addr,
4141 MDIO_PMA_DEVAD,
4142 MDIO_PMA_REG_7101_RESET,
4143 (val | (1<<15)));
4144 /* Wait for clear */
4145 bnx2x_cl45_read(bp, port,
4146 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4147 phy_addr,
4148 MDIO_PMA_DEVAD,
4149 MDIO_PMA_REG_7101_RESET, &val);
4150
4151 if ((val & (1<<15)) == 0)
4152 break;
4153 }
4154}
4155#define RESERVED_SIZE 256
4156/* max application is 160K bytes - data at end of RAM */
4157#define MAX_APP_SIZE 160*1024 - RESERVED_SIZE
4158
4159/* Header is 14 bytes */
4160#define HEADER_SIZE 14
4161#define DATA_OFFSET HEADER_SIZE
4162
4163#define SPI_START_TRANSFER(bp, port, ext_phy_addr) \
4164 bnx2x_cl45_write(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, \
4165 ext_phy_addr, \
4166 MDIO_PCS_DEVAD, \
4167 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 1)
4168
4169/* Programs an image to DSP's flash via the SPI port*/
4170static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4171 u8 ext_phy_addr,
4172 char data[], u32 size)
4173{
4174 const u16 num_trans = size/4; /* 4 bytes can be sent at a time */
4175 /* Doesn't include last trans!*/
4176 const u16 last_trans_size = size%4; /* Num bytes on last trans */
4177 u16 trans_cnt, byte_cnt;
4178 u32 data_index;
4179 u16 tmp;
4180 u16 code_started = 0;
4181 u16 image_revision1, image_revision2;
4182 u16 cnt;
4183
4184 DP(NETIF_MSG_LINK, "bnx2x_sfx7101_flash_download file_size=%d\n", size);
4185 /* Going to flash*/
4186 if ((size-HEADER_SIZE) > MAX_APP_SIZE) {
4187 /* This very often will be the case, because the image is built
4188 with 160Kbytes size whereas the total image size must actually
4189 be 160Kbytes-RESERVED_SIZE */
4190 DP(NETIF_MSG_LINK, "Warning, file size was %d bytes "
4191 "truncated to %d bytes\n", size, MAX_APP_SIZE);
4192 size = MAX_APP_SIZE+HEADER_SIZE;
4193 }
4194 DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]);
4195 DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]);
4196 /* Put the DSP in download mode by setting FLASH_CFG[2] to 1
4197 and issuing a reset.*/
4198
4199 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4200 MISC_REGISTERS_GPIO_HIGH);
4201
4202 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
4203
4204 /* wait 0.5 sec */
4205 for (cnt = 0; cnt < 100; cnt++)
4206 msleep(5);
4207
4208 /* Make sure we can access the DSP
4209 And it's in the correct mode (waiting for download) */
4210
4211 bnx2x_cl45_read(bp, port,
4212 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4213 ext_phy_addr,
4214 MDIO_PCS_DEVAD,
4215 MDIO_PCS_REG_7101_DSP_ACCESS, &tmp);
4216
4217 if (tmp != 0x000A) {
4218 DP(NETIF_MSG_LINK, "DSP is not in waiting on download mode. "
4219 "Expected 0x000A, read 0x%04X\n", tmp);
4220 DP(NETIF_MSG_LINK, "Download failed\n");
4221 return -EINVAL;
4222 }
4223
4224 /* Mux the SPI interface away from the internal processor */
4225 bnx2x_cl45_write(bp, port,
4226 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4227 ext_phy_addr,
4228 MDIO_PCS_DEVAD,
4229 MDIO_PCS_REG_7101_SPI_MUX, 1);
4230
4231 /* Reset the SPI port */
4232 bnx2x_cl45_write(bp, port,
4233 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4234 ext_phy_addr,
4235 MDIO_PCS_DEVAD,
4236 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
4237 bnx2x_cl45_write(bp, port,
4238 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4239 ext_phy_addr,
4240 MDIO_PCS_DEVAD,
4241 MDIO_PCS_REG_7101_SPI_CTRL_ADDR,
4242 (1<<MDIO_PCS_REG_7101_SPI_RESET_BIT));
4243 bnx2x_cl45_write(bp, port,
4244 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4245 ext_phy_addr,
4246 MDIO_PCS_DEVAD,
4247 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
4248
4249 /* Erase the flash */
4250 bnx2x_cl45_write(bp, port,
4251 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4252 ext_phy_addr,
4253 MDIO_PCS_DEVAD,
4254 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4255 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
4256
4257 bnx2x_cl45_write(bp, port,
4258 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4259 ext_phy_addr,
4260 MDIO_PCS_DEVAD,
4261 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4262 1);
4263
4264 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4265 bnx2x_cl45_write(bp, port,
4266 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4267 ext_phy_addr,
4268 MDIO_PCS_DEVAD,
4269 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4270 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD);
4271
4272 bnx2x_cl45_write(bp, port,
4273 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4274 ext_phy_addr,
4275 MDIO_PCS_DEVAD,
4276 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4277 1);
4278 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4279
4280 /* Wait 10 seconds, the maximum time for the erase to complete */
4281 DP(NETIF_MSG_LINK, "Erasing flash, this takes 10 seconds...\n");
4282 for (cnt = 0; cnt < 1000; cnt++)
4283 msleep(10);
4284
4285 DP(NETIF_MSG_LINK, "Downloading flash, please wait...\n");
4286 data_index = 0;
4287 for (trans_cnt = 0; trans_cnt < num_trans; trans_cnt++) {
4288 bnx2x_cl45_write(bp, port,
4289 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4290 ext_phy_addr,
4291 MDIO_PCS_DEVAD,
4292 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4293 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
4294
4295 bnx2x_cl45_write(bp, port,
4296 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4297 ext_phy_addr,
4298 MDIO_PCS_DEVAD,
4299 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4300 1);
4301 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4302
4303 bnx2x_cl45_write(bp, port,
4304 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4305 ext_phy_addr,
4306 MDIO_PCS_DEVAD,
4307 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4308 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
4309
4310 /* Bits 23-16 of address */
4311 bnx2x_cl45_write(bp, port,
4312 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4313 ext_phy_addr,
4314 MDIO_PCS_DEVAD,
4315 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4316 (data_index>>16));
4317 /* Bits 15-8 of address */
4318 bnx2x_cl45_write(bp, port,
4319 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4320 ext_phy_addr,
4321 MDIO_PCS_DEVAD,
4322 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4323 (data_index>>8));
4324
4325 /* Bits 7-0 of address */
4326 bnx2x_cl45_write(bp, port,
4327 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4328 ext_phy_addr,
4329 MDIO_PCS_DEVAD,
4330 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4331 ((u16)data_index));
4332
4333 byte_cnt = 0;
4334 while (byte_cnt < 4 && data_index < size) {
4335 bnx2x_cl45_write(bp, port,
4336 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4337 ext_phy_addr,
4338 MDIO_PCS_DEVAD,
4339 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4340 data[data_index++]);
4341 byte_cnt++;
4342 }
4343
4344 bnx2x_cl45_write(bp, port,
4345 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4346 ext_phy_addr,
4347 MDIO_PCS_DEVAD,
4348 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4349 byte_cnt+4);
4350
4351 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4352 msleep(5); /* Wait 5 ms minimum between transs */
4353
4354 /* Let the user know something's going on.*/
4355 /* a pacifier ever 4K */
4356 if ((data_index % 1023) == 0)
4357 DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
4358 }
4359
4360 DP(NETIF_MSG_LINK, "\n");
4361 /* Transfer the last block if there is data remaining */
4362 if (last_trans_size) {
4363 bnx2x_cl45_write(bp, port,
4364 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4365 ext_phy_addr,
4366 MDIO_PCS_DEVAD,
4367 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4368 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
4369
4370 bnx2x_cl45_write(bp, port,
4371 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4372 ext_phy_addr,
4373 MDIO_PCS_DEVAD,
4374 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4375 1);
4376
4377 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4378
4379 bnx2x_cl45_write(bp, port,
4380 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4381 ext_phy_addr,
4382 MDIO_PCS_DEVAD,
4383 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4384 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
4385
4386 /* Bits 23-16 of address */
4387 bnx2x_cl45_write(bp, port,
4388 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4389 ext_phy_addr,
4390 MDIO_PCS_DEVAD,
4391 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4392 (data_index>>16));
4393 /* Bits 15-8 of address */
4394 bnx2x_cl45_write(bp, port,
4395 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4396 ext_phy_addr,
4397 MDIO_PCS_DEVAD,
4398 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4399 (data_index>>8));
4400
4401 /* Bits 7-0 of address */
4402 bnx2x_cl45_write(bp, port,
4403 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4404 ext_phy_addr,
4405 MDIO_PCS_DEVAD,
4406 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4407 ((u16)data_index));
4408
4409 byte_cnt = 0;
4410 while (byte_cnt < last_trans_size && data_index < size) {
4411 /* Bits 7-0 of address */
4412 bnx2x_cl45_write(bp, port,
4413 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4414 ext_phy_addr,
4415 MDIO_PCS_DEVAD,
4416 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4417 data[data_index++]);
4418 byte_cnt++;
4419 }
4420
4421 bnx2x_cl45_write(bp, port,
4422 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4423 ext_phy_addr,
4424 MDIO_PCS_DEVAD,
4425 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4426 byte_cnt+4);
4427
4428 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4429 }
4430
4431 /* DSP Remove Download Mode */
4432 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_LOW);
4433
4434 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
4435
4436 /* wait 0.5 sec to allow it to run */
4437 for (cnt = 0; cnt < 100; cnt++)
4438 msleep(5);
4439
4440 bnx2x_hw_reset(bp);
4441
4442 for (cnt = 0; cnt < 100; cnt++)
4443 msleep(5);
4444
4445 /* Check that the code is started. In case the download
4446 checksum failed, the code won't be started. */
4447 bnx2x_cl45_read(bp, port,
4448 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4449 ext_phy_addr,
4450 MDIO_PCS_DEVAD,
4451 MDIO_PCS_REG_7101_DSP_ACCESS,
4452 &tmp);
4453
4454 code_started = (tmp & (1<<4));
4455 if (!code_started) {
4456 DP(NETIF_MSG_LINK, "Download failed. Please check file.\n");
4457 return -EINVAL;
4458 }
4459
4460 /* Verify that the file revision is now equal to the image
4461 revision within the DSP */
4462 bnx2x_cl45_read(bp, port,
4463 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4464 ext_phy_addr,
4465 MDIO_PMA_DEVAD,
4466 MDIO_PMA_REG_7101_VER1,
4467 &image_revision1);
4468
4469 bnx2x_cl45_read(bp, port,
4470 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4471 ext_phy_addr,
4472 MDIO_PMA_DEVAD,
4473 MDIO_PMA_REG_7101_VER2,
4474 &image_revision2);
4475
4476 if (data[0x14e] != (image_revision2&0xFF) ||
4477 data[0x14f] != ((image_revision2&0xFF00)>>8) ||
4478 data[0x150] != (image_revision1&0xFF) ||
4479 data[0x151] != ((image_revision1&0xFF00)>>8)) {
4480 DP(NETIF_MSG_LINK, "Download failed.\n");
4481 return -EINVAL;
4482 }
4483 DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
4484 return 0;
4485}
4486
4487u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
4488 u8 driver_loaded, char data[], u32 size)
4489{
4490 u8 rc = 0;
4491 u32 ext_phy_type;
4492 u8 ext_phy_addr;
4493 ext_phy_addr = ((ext_phy_config &
4494 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4495 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4496
4497 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
4498
4499 switch (ext_phy_type) {
4500 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4501 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4502 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
4503 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
4504 DP(NETIF_MSG_LINK,
4505 "Flash download not supported for this ext phy\n");
4506 rc = -EINVAL;
4507 break;
4508 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
4509 /* Take ext phy out of reset */
4510 if (!driver_loaded)
4511 bnx2x_turn_on_sf(bp, port, ext_phy_addr);
4512 rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr,
4513 data, size);
4514 if (!driver_loaded)
4515 bnx2x_turn_off_sf(bp);
4516 break;
4517 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4518 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
4519 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
4520 default:
4521 DP(NETIF_MSG_LINK, "Invalid ext phy type\n");
4522 rc = -EINVAL;
4523 break;
4524 }
4525 return rc;
4526}
4527
diff --git a/drivers/net/bnx2x_link.h b/drivers/net/bnx2x_link.h
new file mode 100644
index 000000000000..714d37ac95de
--- /dev/null
+++ b/drivers/net/bnx2x_link.h
@@ -0,0 +1,168 @@
1/* Copyright 2008 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17#ifndef BNX2X_LINK_H
18#define BNX2X_LINK_H
19
20
21
22/***********************************************************/
23/* Defines */
24/***********************************************************/
25#define DEFAULT_PHY_DEV_ADDR 3
26
27
28
29#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
30#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
31#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
32#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
33#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
34
35#define SPEED_AUTO_NEG 0
36#define SPEED_12000 12000
37#define SPEED_12500 12500
38#define SPEED_13000 13000
39#define SPEED_15000 15000
40#define SPEED_16000 16000
41
42
43/***********************************************************/
44/* Structs */
45/***********************************************************/
46/* Inputs parameters to the CLC */
47struct link_params {
48
49 u8 port;
50
51 /* Default / User Configuration */
52 u8 loopback_mode;
53#define LOOPBACK_NONE 0
54#define LOOPBACK_EMAC 1
55#define LOOPBACK_BMAC 2
56#define LOOPBACK_XGXS_10 3
57#define LOOPBACK_EXT_PHY 4
58
59 u16 req_duplex;
60 u16 req_flow_ctrl;
61 u16 req_line_speed; /* Also determine AutoNeg */
62
63 /* Device parameters */
64 u8 mac_addr[6];
65 u16 mtu;
66
67
68 /* shmem parameters */
69 u32 shmem_base;
70 u32 speed_cap_mask;
71 u32 switch_cfg;
72#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
73#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
74#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
75
76 u16 hw_led_mode; /* part of the hw_config read from the shmem */
77 u32 serdes_config;
78 u32 lane_config;
79 u32 ext_phy_config;
80#define XGXS_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
81 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
82#define SERDES_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
83 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
84 /* Phy register parameter */
85 u32 chip_id;
86
87 /* phy_addr populated by the CLC */
88 u8 phy_addr;
89 /* Device pointer passed to all callback functions */
90 struct bnx2x *bp;
91};
92
93/* Output parameters */
94struct link_vars {
95 u8 phy_link_up; /* internal phy link indication */
96 u8 link_up;
97 u16 duplex;
98 u16 flow_ctrl;
99 u32 ieee_fc;
100 u8 mac_type;
101
102#define MAC_TYPE_NONE 0
103#define MAC_TYPE_EMAC 1
104#define MAC_TYPE_BMAC 2
105 u16 line_speed;
106 u32 autoneg;
107#define AUTO_NEG_DISABLED 0x0
108#define AUTO_NEG_ENABLED 0x1
109#define AUTO_NEG_COMPLETE 0x2
110#define AUTO_NEG_PARALLEL_DETECTION_USED 0x3
111
112 u8 phy_flags;
113
114 /* The same definitions as the shmem parameter */
115 u32 link_status;
116};
117
118/***********************************************************/
119/* Functions */
120/***********************************************************/
121
122/* Initialize the phy */
123u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);
124
125/* Reset the link. Should be called when driver or interface goes down */
126u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars);
127
128/* bnx2x_link_update should be called upon link interrupt */
129u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);
130
131/* use the following cl45 functions to read/write from external_phy
132 In order to use it to read/write internal phy registers, use
133 DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
134 Use ext_phy_type of 0 in case of cl22 over cl45
135 the register */
136u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
137 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val);
138
139u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
140 u8 phy_addr, u8 devad, u16 reg, u16 val);
141
142/* Reads the link_status from the shmem,
143 and update the link vars accordinaly */
144void bnx2x_link_status_update(struct link_params *input,
145 struct link_vars *output);
146/* returns string representing the fw_version of the external phy */
147u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
148 u8 *version, u16 len);
149
150/* Set/Unset the led
151 Basically, the CLC takes care of the led for the link, but in case one needs
152 to set/unset the led unnatually, set the "mode" to LED_MODE_OPER to
153 blink the led, and LED_MODE_OFF to set the led off.*/
154u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
155 u16 hw_led_mode, u32 chip_id);
156#define LED_MODE_OFF 0
157#define LED_MODE_OPER 2
158
159u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port, u32 led_idx, u32 value);
160
161u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
162 u8 driver_loaded, char data[], u32 size);
163/* Get the actual link status. In case it returns 0, link is up,
164 otherwise link is down*/
165u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars);
166
167
168#endif /* BNX2X_LINK_H */
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
new file mode 100644
index 000000000000..0263bef9cc6d
--- /dev/null
+++ b/drivers/net/bnx2x_main.c
@@ -0,0 +1,10294 @@
1/* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2008 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
26#include <linux/vmalloc.h>
27#include <linux/interrupt.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/dma-mapping.h>
34#include <linux/bitops.h>
35#include <linux/irq.h>
36#include <linux/delay.h>
37#include <asm/byteorder.h>
38#include <linux/time.h>
39#include <linux/ethtool.h>
40#include <linux/mii.h>
41#ifdef NETIF_F_HW_VLAN_TX
42 #include <linux/if_vlan.h>
43#endif
44#include <net/ip.h>
45#include <net/tcp.h>
46#include <net/checksum.h>
47#include <linux/version.h>
48#include <net/ip6_checksum.h>
49#include <linux/workqueue.h>
50#include <linux/crc32.h>
51#include <linux/crc32c.h>
52#include <linux/prefetch.h>
53#include <linux/zlib.h>
54#include <linux/io.h>
55
56#include "bnx2x_reg.h"
57#include "bnx2x_fw_defs.h"
58#include "bnx2x_hsi.h"
59#include "bnx2x_link.h"
60#include "bnx2x.h"
61#include "bnx2x_init.h"
62
63#define DRV_MODULE_VERSION "1.45.6"
64#define DRV_MODULE_RELDATE "2008/06/23"
65#define BNX2X_BC_VER 0x040200
66
67/* Time in jiffies before concluding the transmitter is hung */
68#define TX_TIMEOUT (5*HZ)
69
70static char version[] __devinitdata =
71 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
72 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
73
74MODULE_AUTHOR("Eliezer Tamir");
75MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver");
76MODULE_LICENSE("GPL");
77MODULE_VERSION(DRV_MODULE_VERSION);
78
79static int use_inta;
80static int poll;
81static int debug;
82static int disable_tpa;
83static int nomcp;
84static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
85static int use_multi;
86
87module_param(use_inta, int, 0);
88module_param(poll, int, 0);
89module_param(debug, int, 0);
90module_param(disable_tpa, int, 0);
91module_param(nomcp, int, 0);
92MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
93MODULE_PARM_DESC(poll, "use polling (for debug)");
94MODULE_PARM_DESC(debug, "default debug msglevel");
95MODULE_PARM_DESC(nomcp, "ignore management CPU");
96
97#ifdef BNX2X_MULTI
98module_param(use_multi, int, 0);
99MODULE_PARM_DESC(use_multi, "use per-CPU queues");
100#endif
101
102enum bnx2x_board_type {
103 BCM57710 = 0,
104 BCM57711 = 1,
105 BCM57711E = 2,
106};
107
108/* indexed by board_type, above */
109static struct {
110 char *name;
111} board_info[] __devinitdata = {
112 { "Broadcom NetXtreme II BCM57710 XGb" },
113 { "Broadcom NetXtreme II BCM57711 XGb" },
114 { "Broadcom NetXtreme II BCM57711E XGb" }
115};
116
117
118static const struct pci_device_id bnx2x_pci_tbl[] = {
119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 },
123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E },
125 { 0 }
126};
127
128MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
129
130/****************************************************************************
131* General service functions
132****************************************************************************/
133
134/* used only at init
135 * locking is done by mcp
136 */
137static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
138{
139 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
140 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
141 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
142 PCICFG_VENDOR_ID_OFFSET);
143}
144
145static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
146{
147 u32 val;
148
149 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
150 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
151 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
152 PCICFG_VENDOR_ID_OFFSET);
153
154 return val;
155}
156
157static const u32 dmae_reg_go_c[] = {
158 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
159 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
160 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
161 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
162};
163
164/* copy command into DMAE command memory and set DMAE command go */
165static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
166 int idx)
167{
168 u32 cmd_offset;
169 int i;
170
171 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
172 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
173 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
174
175 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
176 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
177 }
178 REG_WR(bp, dmae_reg_go_c[idx], 1);
179}
180
181void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
182 u32 len32)
183{
184 struct dmae_command *dmae = &bp->init_dmae;
185 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
186 int cnt = 200;
187
188 if (!bp->dmae_ready) {
189 u32 *data = bnx2x_sp(bp, wb_data[0]);
190
191 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
192 " using indirect\n", dst_addr, len32);
193 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
194 return;
195 }
196
197 mutex_lock(&bp->dmae_mutex);
198
199 memset(dmae, 0, sizeof(struct dmae_command));
200
201 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
202 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
203 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
204#ifdef __BIG_ENDIAN
205 DMAE_CMD_ENDIANITY_B_DW_SWAP |
206#else
207 DMAE_CMD_ENDIANITY_DW_SWAP |
208#endif
209 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
210 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
211 dmae->src_addr_lo = U64_LO(dma_addr);
212 dmae->src_addr_hi = U64_HI(dma_addr);
213 dmae->dst_addr_lo = dst_addr >> 2;
214 dmae->dst_addr_hi = 0;
215 dmae->len = len32;
216 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
217 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
218 dmae->comp_val = DMAE_COMP_VAL;
219
220 DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
221 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
222 "dst_addr [%x:%08x (%08x)]\n"
223 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
224 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
225 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
226 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
227 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
228 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
229 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
230
231 *wb_comp = 0;
232
233 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
234
235 udelay(5);
236
237 while (*wb_comp != DMAE_COMP_VAL) {
238 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
239
240 /* adjust delay for emulation/FPGA */
241 if (CHIP_REV_IS_SLOW(bp))
242 msleep(100);
243 else
244 udelay(5);
245
246 if (!cnt) {
247 BNX2X_ERR("dmae timeout!\n");
248 break;
249 }
250 cnt--;
251 }
252
253 mutex_unlock(&bp->dmae_mutex);
254}
255
256void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
257{
258 struct dmae_command *dmae = &bp->init_dmae;
259 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
260 int cnt = 200;
261
262 if (!bp->dmae_ready) {
263 u32 *data = bnx2x_sp(bp, wb_data[0]);
264 int i;
265
266 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
267 " using indirect\n", src_addr, len32);
268 for (i = 0; i < len32; i++)
269 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
270 return;
271 }
272
273 mutex_lock(&bp->dmae_mutex);
274
275 memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
276 memset(dmae, 0, sizeof(struct dmae_command));
277
278 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
279 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
280 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
281#ifdef __BIG_ENDIAN
282 DMAE_CMD_ENDIANITY_B_DW_SWAP |
283#else
284 DMAE_CMD_ENDIANITY_DW_SWAP |
285#endif
286 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
287 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
288 dmae->src_addr_lo = src_addr >> 2;
289 dmae->src_addr_hi = 0;
290 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
291 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
292 dmae->len = len32;
293 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
294 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
295 dmae->comp_val = DMAE_COMP_VAL;
296
297 DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
298 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
299 "dst_addr [%x:%08x (%08x)]\n"
300 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
301 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
302 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
303 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
304
305 *wb_comp = 0;
306
307 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
308
309 udelay(5);
310
311 while (*wb_comp != DMAE_COMP_VAL) {
312
313 /* adjust delay for emulation/FPGA */
314 if (CHIP_REV_IS_SLOW(bp))
315 msleep(100);
316 else
317 udelay(5);
318
319 if (!cnt) {
320 BNX2X_ERR("dmae timeout!\n");
321 break;
322 }
323 cnt--;
324 }
325 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
326 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
327 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
328
329 mutex_unlock(&bp->dmae_mutex);
330}
331
332/* used only for slowpath so not inlined */
333static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
334{
335 u32 wb_write[2];
336
337 wb_write[0] = val_hi;
338 wb_write[1] = val_lo;
339 REG_WR_DMAE(bp, reg, wb_write, 2);
340}
341
342#ifdef USE_WB_RD
343static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
344{
345 u32 wb_data[2];
346
347 REG_RD_DMAE(bp, reg, wb_data, 2);
348
349 return HILO_U64(wb_data[0], wb_data[1]);
350}
351#endif
352
353static int bnx2x_mc_assert(struct bnx2x *bp)
354{
355 char last_idx;
356 int i, rc = 0;
357 u32 row0, row1, row2, row3;
358
359 /* XSTORM */
360 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
361 XSTORM_ASSERT_LIST_INDEX_OFFSET);
362 if (last_idx)
363 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
364
365 /* print the asserts */
366 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
367
368 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
369 XSTORM_ASSERT_LIST_OFFSET(i));
370 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
371 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
372 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
373 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
374 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
375 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
376
377 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
378 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
379 " 0x%08x 0x%08x 0x%08x\n",
380 i, row3, row2, row1, row0);
381 rc++;
382 } else {
383 break;
384 }
385 }
386
387 /* TSTORM */
388 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
389 TSTORM_ASSERT_LIST_INDEX_OFFSET);
390 if (last_idx)
391 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
392
393 /* print the asserts */
394 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
395
396 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
397 TSTORM_ASSERT_LIST_OFFSET(i));
398 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
399 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
400 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
401 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
402 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
403 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
404
405 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
406 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
407 " 0x%08x 0x%08x 0x%08x\n",
408 i, row3, row2, row1, row0);
409 rc++;
410 } else {
411 break;
412 }
413 }
414
415 /* CSTORM */
416 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
417 CSTORM_ASSERT_LIST_INDEX_OFFSET);
418 if (last_idx)
419 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
420
421 /* print the asserts */
422 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
423
424 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
425 CSTORM_ASSERT_LIST_OFFSET(i));
426 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
427 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
428 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
429 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
430 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
431 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
432
433 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
434 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
435 " 0x%08x 0x%08x 0x%08x\n",
436 i, row3, row2, row1, row0);
437 rc++;
438 } else {
439 break;
440 }
441 }
442
443 /* USTORM */
444 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
445 USTORM_ASSERT_LIST_INDEX_OFFSET);
446 if (last_idx)
447 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
448
449 /* print the asserts */
450 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
451
452 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
453 USTORM_ASSERT_LIST_OFFSET(i));
454 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
455 USTORM_ASSERT_LIST_OFFSET(i) + 4);
456 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
457 USTORM_ASSERT_LIST_OFFSET(i) + 8);
458 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
459 USTORM_ASSERT_LIST_OFFSET(i) + 12);
460
461 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
462 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
463 " 0x%08x 0x%08x 0x%08x\n",
464 i, row3, row2, row1, row0);
465 rc++;
466 } else {
467 break;
468 }
469 }
470
471 return rc;
472}
473
474static void bnx2x_fw_dump(struct bnx2x *bp)
475{
476 u32 mark, offset;
477 u32 data[9];
478 int word;
479
480 mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
481 mark = ((mark + 0x3) & ~0x3);
482 printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
483
484 for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
485 for (word = 0; word < 8; word++)
486 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
487 offset + 4*word));
488 data[8] = 0x0;
489 printk(KERN_CONT "%s", (char *)data);
490 }
491 for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
492 for (word = 0; word < 8; word++)
493 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
494 offset + 4*word));
495 data[8] = 0x0;
496 printk(KERN_CONT "%s", (char *)data);
497 }
498 printk("\n" KERN_ERR PFX "end of fw dump\n");
499}
500
501static void bnx2x_panic_dump(struct bnx2x *bp)
502{
503 int i;
504 u16 j, start, end;
505
506 BNX2X_ERR("begin crash dump -----------------\n");
507
508 for_each_queue(bp, i) {
509 struct bnx2x_fastpath *fp = &bp->fp[i];
510 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
511
512 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x) tx_pkt_cons(%x)"
513 " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n",
514 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
515 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
516 BNX2X_ERR(" rx_comp_prod(%x) rx_comp_cons(%x)"
517 " *rx_cons_sb(%x) *rx_bd_cons_sb(%x)"
518 " rx_sge_prod(%x) last_max_sge(%x)\n",
519 fp->rx_comp_prod, fp->rx_comp_cons,
520 le16_to_cpu(*fp->rx_cons_sb),
521 le16_to_cpu(*fp->rx_bd_cons_sb),
522 fp->rx_sge_prod, fp->last_max_sge);
523 BNX2X_ERR(" fp_c_idx(%x) fp_u_idx(%x)"
524 " bd data(%x,%x) rx_alloc_failed(%lx)\n",
525 fp->fp_c_idx, fp->fp_u_idx, hw_prods->packets_prod,
526 hw_prods->bds_prod, fp->rx_alloc_failed);
527
528 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
529 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
530 for (j = start; j < end; j++) {
531 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
532
533 BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
534 sw_bd->skb, sw_bd->first_bd);
535 }
536
537 start = TX_BD(fp->tx_bd_cons - 10);
538 end = TX_BD(fp->tx_bd_cons + 254);
539 for (j = start; j < end; j++) {
540 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
541
542 BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
543 j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
544 }
545
546 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
547 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
548 for (j = start; j < end; j++) {
549 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
550 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
551
552 BNX2X_ERR("rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
553 j, rx_bd[1], rx_bd[0], sw_bd->skb);
554 }
555
556 start = 0;
557 end = RX_SGE_CNT*NUM_RX_SGE_PAGES;
558 for (j = start; j < end; j++) {
559 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
560 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
561
562 BNX2X_ERR("rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
563 j, rx_sge[1], rx_sge[0], sw_page->page);
564 }
565
566 start = RCQ_BD(fp->rx_comp_cons - 10);
567 end = RCQ_BD(fp->rx_comp_cons + 503);
568 for (j = start; j < end; j++) {
569 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
570
571 BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
572 j, cqe[0], cqe[1], cqe[2], cqe[3]);
573 }
574 }
575
576 BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_x_idx(%u)"
577 " def_t_idx(%u) def_att_idx(%u) attn_state(%u)"
578 " spq_prod_idx(%u)\n",
579 bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
580 bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
581
582 bnx2x_fw_dump(bp);
583 bnx2x_mc_assert(bp);
584 BNX2X_ERR("end crash dump -----------------\n");
585
586 bp->stats_state = STATS_STATE_DISABLED;
587 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
588}
589
590static void bnx2x_int_enable(struct bnx2x *bp)
591{
592 int port = BP_PORT(bp);
593 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
594 u32 val = REG_RD(bp, addr);
595 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
596
597 if (msix) {
598 val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
599 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
600 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
601 } else {
602 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
603 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
604 HC_CONFIG_0_REG_INT_LINE_EN_0 |
605 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
606
607 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
608 val, port, addr, msix);
609
610 REG_WR(bp, addr, val);
611
612 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
613 }
614
615 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
616 val, port, addr, msix);
617
618 REG_WR(bp, addr, val);
619
620 if (CHIP_IS_E1H(bp)) {
621 /* init leading/trailing edge */
622 if (IS_E1HMF(bp)) {
623 val = (0xfe0f | (1 << (BP_E1HVN(bp) + 4)));
624 if (bp->port.pmf)
625 /* enable nig attention */
626 val |= 0x0100;
627 } else
628 val = 0xffff;
629
630 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
631 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
632 }
633}
634
635static void bnx2x_int_disable(struct bnx2x *bp)
636{
637 int port = BP_PORT(bp);
638 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
639 u32 val = REG_RD(bp, addr);
640
641 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
642 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
643 HC_CONFIG_0_REG_INT_LINE_EN_0 |
644 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
645
646 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
647 val, port, addr);
648
649 REG_WR(bp, addr, val);
650 if (REG_RD(bp, addr) != val)
651 BNX2X_ERR("BUG! proper val not read from IGU!\n");
652}
653
654static void bnx2x_int_disable_sync(struct bnx2x *bp)
655{
656 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
657 int i;
658
659 /* disable interrupt handling */
660 atomic_inc(&bp->intr_sem);
661 /* prevent the HW from sending interrupts */
662 bnx2x_int_disable(bp);
663
664 /* make sure all ISRs are done */
665 if (msix) {
666 for_each_queue(bp, i)
667 synchronize_irq(bp->msix_table[i].vector);
668
669 /* one more for the Slow Path IRQ */
670 synchronize_irq(bp->msix_table[i].vector);
671 } else
672 synchronize_irq(bp->pdev->irq);
673
674 /* make sure sp_task is not running */
675 cancel_work_sync(&bp->sp_task);
676}
677
678/* fast path */
679
680/*
681 * General service functions
682 */
683
684static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
685 u8 storm, u16 index, u8 op, u8 update)
686{
687 u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8;
688 struct igu_ack_register igu_ack;
689
690 igu_ack.status_block_index = index;
691 igu_ack.sb_id_and_flags =
692 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
693 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
694 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
695 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
696
697 DP(BNX2X_MSG_OFF, "write 0x%08x to IGU addr 0x%x\n",
698 (*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr);
699 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack));
700}
701
702static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
703{
704 struct host_status_block *fpsb = fp->status_blk;
705 u16 rc = 0;
706
707 barrier(); /* status block is written to by the chip */
708 if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
709 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
710 rc |= 1;
711 }
712 if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
713 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
714 rc |= 2;
715 }
716 return rc;
717}
718
719static inline int bnx2x_has_work(struct bnx2x_fastpath *fp)
720{
721 u16 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
722
723 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
724 rx_cons_sb++;
725
726 if ((fp->rx_comp_cons != rx_cons_sb) ||
727 (fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) ||
728 (fp->tx_pkt_prod != fp->tx_pkt_cons))
729 return 1;
730
731 return 0;
732}
733
734static u16 bnx2x_ack_int(struct bnx2x *bp)
735{
736 u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8;
737 u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr);
738
739 DP(BNX2X_MSG_OFF, "read 0x%08x from IGU addr 0x%x\n",
740 result, BAR_IGU_INTMEM + igu_addr);
741
742#ifdef IGU_DEBUG
743#warning IGU_DEBUG active
744 if (result == 0) {
745 BNX2X_ERR("read %x from IGU\n", result);
746 REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0);
747 }
748#endif
749 return result;
750}
751
752
753/*
754 * fast path service functions
755 */
756
757/* free skb in the packet ring at pos idx
758 * return idx of last bd freed
759 */
760static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
761 u16 idx)
762{
763 struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
764 struct eth_tx_bd *tx_bd;
765 struct sk_buff *skb = tx_buf->skb;
766 u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
767 int nbd;
768
769 DP(BNX2X_MSG_OFF, "pkt_idx %d buff @(%p)->skb %p\n",
770 idx, tx_buf, skb);
771
772 /* unmap first bd */
773 DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
774 tx_bd = &fp->tx_desc_ring[bd_idx];
775 pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
776 BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
777
778 nbd = le16_to_cpu(tx_bd->nbd) - 1;
779 new_cons = nbd + tx_buf->first_bd;
780#ifdef BNX2X_STOP_ON_ERROR
781 if (nbd > (MAX_SKB_FRAGS + 2)) {
782 BNX2X_ERR("BAD nbd!\n");
783 bnx2x_panic();
784 }
785#endif
786
787 /* Skip a parse bd and the TSO split header bd
788 since they have no mapping */
789 if (nbd)
790 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
791
792 if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
793 ETH_TX_BD_FLAGS_TCP_CSUM |
794 ETH_TX_BD_FLAGS_SW_LSO)) {
795 if (--nbd)
796 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
797 tx_bd = &fp->tx_desc_ring[bd_idx];
798 /* is this a TSO split header bd? */
799 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
800 if (--nbd)
801 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
802 }
803 }
804
805 /* now free frags */
806 while (nbd > 0) {
807
808 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
809 tx_bd = &fp->tx_desc_ring[bd_idx];
810 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
811 BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
812 if (--nbd)
813 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
814 }
815
816 /* release skb */
817 BUG_TRAP(skb);
818 dev_kfree_skb(skb);
819 tx_buf->first_bd = 0;
820 tx_buf->skb = NULL;
821
822 return new_cons;
823}
824
825static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
826{
827 s16 used;
828 u16 prod;
829 u16 cons;
830
831 barrier(); /* Tell compiler that prod and cons can change */
832 prod = fp->tx_bd_prod;
833 cons = fp->tx_bd_cons;
834
835 /* NUM_TX_RINGS = number of "next-page" entries
836 It will be used as a threshold */
837 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
838
839#ifdef BNX2X_STOP_ON_ERROR
840 BUG_TRAP(used >= 0);
841 BUG_TRAP(used <= fp->bp->tx_ring_size);
842 BUG_TRAP((fp->bp->tx_ring_size - used) <= MAX_TX_AVAIL);
843#endif
844
845 return (s16)(fp->bp->tx_ring_size) - used;
846}
847
848static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
849{
850 struct bnx2x *bp = fp->bp;
851 u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
852 int done = 0;
853
854#ifdef BNX2X_STOP_ON_ERROR
855 if (unlikely(bp->panic))
856 return;
857#endif
858
859 hw_cons = le16_to_cpu(*fp->tx_cons_sb);
860 sw_cons = fp->tx_pkt_cons;
861
862 while (sw_cons != hw_cons) {
863 u16 pkt_cons;
864
865 pkt_cons = TX_BD(sw_cons);
866
867 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
868
869 DP(NETIF_MSG_TX_DONE, "hw_cons %u sw_cons %u pkt_cons %u\n",
870 hw_cons, sw_cons, pkt_cons);
871
872/* if (NEXT_TX_IDX(sw_cons) != hw_cons) {
873 rmb();
874 prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
875 }
876*/
877 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
878 sw_cons++;
879 done++;
880
881 if (done == work)
882 break;
883 }
884
885 fp->tx_pkt_cons = sw_cons;
886 fp->tx_bd_cons = bd_cons;
887
888 /* Need to make the tx_cons update visible to start_xmit()
889 * before checking for netif_queue_stopped(). Without the
890 * memory barrier, there is a small possibility that start_xmit()
891 * will miss it and cause the queue to be stopped forever.
892 */
893 smp_mb();
894
895 /* TBD need a thresh? */
896 if (unlikely(netif_queue_stopped(bp->dev))) {
897
898 netif_tx_lock(bp->dev);
899
900 if (netif_queue_stopped(bp->dev) &&
901 (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
902 netif_wake_queue(bp->dev);
903
904 netif_tx_unlock(bp->dev);
905 }
906}
907
908static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
909 union eth_rx_cqe *rr_cqe)
910{
911 struct bnx2x *bp = fp->bp;
912 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
913 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
914
915 DP(BNX2X_MSG_SP,
916 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
917 FP_IDX(fp), cid, command, bp->state,
918 rr_cqe->ramrod_cqe.ramrod_type);
919
920 bp->spq_left++;
921
922 if (FP_IDX(fp)) {
923 switch (command | fp->state) {
924 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
925 BNX2X_FP_STATE_OPENING):
926 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
927 cid);
928 fp->state = BNX2X_FP_STATE_OPEN;
929 break;
930
931 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
932 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
933 cid);
934 fp->state = BNX2X_FP_STATE_HALTED;
935 break;
936
937 default:
938 BNX2X_ERR("unexpected MC reply (%d) "
939 "fp->state is %x\n", command, fp->state);
940 break;
941 }
942 mb(); /* force bnx2x_wait_ramrod() to see the change */
943 return;
944 }
945
946 switch (command | bp->state) {
947 case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
948 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
949 bp->state = BNX2X_STATE_OPEN;
950 break;
951
952 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
953 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
954 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
955 fp->state = BNX2X_FP_STATE_HALTED;
956 break;
957
958 case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
959 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
960 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
961 break;
962
963 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
964 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
965 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
966 bp->set_mac_pending = 0;
967 break;
968
969 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
970 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
971 break;
972
973 default:
974 BNX2X_ERR("unexpected MC reply (%d) bp->state is %x\n",
975 command, bp->state);
976 break;
977 }
978 mb(); /* force bnx2x_wait_ramrod() to see the change */
979}
980
981static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
982 struct bnx2x_fastpath *fp, u16 index)
983{
984 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
985 struct page *page = sw_buf->page;
986 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
987
988 /* Skip "next page" elements */
989 if (!page)
990 return;
991
992 pci_unmap_page(bp->pdev, pci_unmap_addr(sw_buf, mapping),
993 BCM_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
994 __free_pages(page, PAGES_PER_SGE_SHIFT);
995
996 sw_buf->page = NULL;
997 sge->addr_hi = 0;
998 sge->addr_lo = 0;
999}
1000
1001static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
1002 struct bnx2x_fastpath *fp, int last)
1003{
1004 int i;
1005
1006 for (i = 0; i < last; i++)
1007 bnx2x_free_rx_sge(bp, fp, i);
1008}
1009
1010static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
1011 struct bnx2x_fastpath *fp, u16 index)
1012{
1013 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
1014 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
1015 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
1016 dma_addr_t mapping;
1017
1018 if (unlikely(page == NULL))
1019 return -ENOMEM;
1020
1021 mapping = pci_map_page(bp->pdev, page, 0, BCM_PAGE_SIZE*PAGES_PER_SGE,
1022 PCI_DMA_FROMDEVICE);
1023 if (unlikely(dma_mapping_error(mapping))) {
1024 __free_pages(page, PAGES_PER_SGE_SHIFT);
1025 return -ENOMEM;
1026 }
1027
1028 sw_buf->page = page;
1029 pci_unmap_addr_set(sw_buf, mapping, mapping);
1030
1031 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
1032 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
1033
1034 return 0;
1035}
1036
1037static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
1038 struct bnx2x_fastpath *fp, u16 index)
1039{
1040 struct sk_buff *skb;
1041 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
1042 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
1043 dma_addr_t mapping;
1044
1045 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1046 if (unlikely(skb == NULL))
1047 return -ENOMEM;
1048
1049 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1050 PCI_DMA_FROMDEVICE);
1051 if (unlikely(dma_mapping_error(mapping))) {
1052 dev_kfree_skb(skb);
1053 return -ENOMEM;
1054 }
1055
1056 rx_buf->skb = skb;
1057 pci_unmap_addr_set(rx_buf, mapping, mapping);
1058
1059 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1060 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1061
1062 return 0;
1063}
1064
1065/* note that we are not allocating a new skb,
1066 * we are just moving one from cons to prod
1067 * we are not creating a new mapping,
1068 * so there is no need to check for dma_mapping_error().
1069 */
1070static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
1071 struct sk_buff *skb, u16 cons, u16 prod)
1072{
1073 struct bnx2x *bp = fp->bp;
1074 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1075 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1076 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
1077 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1078
1079 pci_dma_sync_single_for_device(bp->pdev,
1080 pci_unmap_addr(cons_rx_buf, mapping),
1081 bp->rx_offset + RX_COPY_THRESH,
1082 PCI_DMA_FROMDEVICE);
1083
1084 prod_rx_buf->skb = cons_rx_buf->skb;
1085 pci_unmap_addr_set(prod_rx_buf, mapping,
1086 pci_unmap_addr(cons_rx_buf, mapping));
1087 *prod_bd = *cons_bd;
1088}
1089
1090static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
1091 u16 idx)
1092{
1093 u16 last_max = fp->last_max_sge;
1094
1095 if (SUB_S16(idx, last_max) > 0)
1096 fp->last_max_sge = idx;
1097}
1098
1099static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
1100{
1101 int i, j;
1102
1103 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1104 int idx = RX_SGE_CNT * i - 1;
1105
1106 for (j = 0; j < 2; j++) {
1107 SGE_MASK_CLEAR_BIT(fp, idx);
1108 idx--;
1109 }
1110 }
1111}
1112
1113static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
1114 struct eth_fast_path_rx_cqe *fp_cqe)
1115{
1116 struct bnx2x *bp = fp->bp;
1117 u16 sge_len = BCM_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
1118 le16_to_cpu(fp_cqe->len_on_bd)) >>
1119 BCM_PAGE_SHIFT;
1120 u16 last_max, last_elem, first_elem;
1121 u16 delta = 0;
1122 u16 i;
1123
1124 if (!sge_len)
1125 return;
1126
1127 /* First mark all used pages */
1128 for (i = 0; i < sge_len; i++)
1129 SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));
1130
1131 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
1132 sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1133
1134 /* Here we assume that the last SGE index is the biggest */
1135 prefetch((void *)(fp->sge_mask));
1136 bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1137
1138 last_max = RX_SGE(fp->last_max_sge);
1139 last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
1140 first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
1141
1142 /* If ring is not full */
1143 if (last_elem + 1 != first_elem)
1144 last_elem++;
1145
1146 /* Now update the prod */
1147 for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
1148 if (likely(fp->sge_mask[i]))
1149 break;
1150
1151 fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
1152 delta += RX_SGE_MASK_ELEM_SZ;
1153 }
1154
1155 if (delta > 0) {
1156 fp->rx_sge_prod += delta;
1157 /* clear page-end entries */
1158 bnx2x_clear_sge_mask_next_elems(fp);
1159 }
1160
1161 DP(NETIF_MSG_RX_STATUS,
1162 "fp->last_max_sge = %d fp->rx_sge_prod = %d\n",
1163 fp->last_max_sge, fp->rx_sge_prod);
1164}
1165
1166static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1167{
1168 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
1169 memset(fp->sge_mask, 0xff,
1170 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1171
1172 /* Clear the two last indeces in the page to 1:
1173 these are the indeces that correspond to the "next" element,
1174 hence will never be indicated and should be removed from
1175 the calculations. */
1176 bnx2x_clear_sge_mask_next_elems(fp);
1177}
1178
1179static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
1180 struct sk_buff *skb, u16 cons, u16 prod)
1181{
1182 struct bnx2x *bp = fp->bp;
1183 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1184 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1185 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1186 dma_addr_t mapping;
1187
1188 /* move empty skb from pool to prod and map it */
1189 prod_rx_buf->skb = fp->tpa_pool[queue].skb;
1190 mapping = pci_map_single(bp->pdev, fp->tpa_pool[queue].skb->data,
1191 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1192 pci_unmap_addr_set(prod_rx_buf, mapping, mapping);
1193
1194 /* move partial skb from cons to pool (don't unmap yet) */
1195 fp->tpa_pool[queue] = *cons_rx_buf;
1196
1197 /* mark bin state as start - print error if current state != stop */
1198 if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
1199 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
1200
1201 fp->tpa_state[queue] = BNX2X_TPA_START;
1202
1203 /* point prod_bd to new skb */
1204 prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1205 prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1206
1207#ifdef BNX2X_STOP_ON_ERROR
1208 fp->tpa_queue_used |= (1 << queue);
1209#ifdef __powerpc64__
1210 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
1211#else
1212 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
1213#endif
1214 fp->tpa_queue_used);
1215#endif
1216}
1217
1218static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1219 struct sk_buff *skb,
1220 struct eth_fast_path_rx_cqe *fp_cqe,
1221 u16 cqe_idx)
1222{
1223 struct sw_rx_page *rx_pg, old_rx_pg;
1224 struct page *sge;
1225 u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
1226 u32 i, frag_len, frag_size, pages;
1227 int err;
1228 int j;
1229
1230 frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
1231 pages = BCM_PAGE_ALIGN(frag_size) >> BCM_PAGE_SHIFT;
1232
1233 /* This is needed in order to enable forwarding support */
1234 if (frag_size)
1235 skb_shinfo(skb)->gso_size = min((u32)BCM_PAGE_SIZE,
1236 max(frag_size, (u32)len_on_bd));
1237
1238#ifdef BNX2X_STOP_ON_ERROR
1239 if (pages > 8*PAGES_PER_SGE) {
1240 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
1241 pages, cqe_idx);
1242 BNX2X_ERR("fp_cqe->pkt_len = %d fp_cqe->len_on_bd = %d\n",
1243 fp_cqe->pkt_len, len_on_bd);
1244 bnx2x_panic();
1245 return -EINVAL;
1246 }
1247#endif
1248
1249 /* Run through the SGL and compose the fragmented skb */
1250 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
1251 u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));
1252
1253 /* FW gives the indices of the SGE as if the ring is an array
1254 (meaning that "next" element will consume 2 indices) */
1255 frag_len = min(frag_size, (u32)(BCM_PAGE_SIZE*PAGES_PER_SGE));
1256 rx_pg = &fp->rx_page_ring[sge_idx];
1257 sge = rx_pg->page;
1258 old_rx_pg = *rx_pg;
1259
1260 /* If we fail to allocate a substitute page, we simply stop
1261 where we are and drop the whole packet */
1262 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1263 if (unlikely(err)) {
1264 fp->rx_alloc_failed++;
1265 return err;
1266 }
1267
1268 /* Unmap the page as we r going to pass it to the stack */
1269 pci_unmap_page(bp->pdev, pci_unmap_addr(&old_rx_pg, mapping),
1270 BCM_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1271
1272 /* Add one frag and update the appropriate fields in the skb */
1273 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
1274
1275 skb->data_len += frag_len;
1276 skb->truesize += frag_len;
1277 skb->len += frag_len;
1278
1279 frag_size -= frag_len;
1280 }
1281
1282 return 0;
1283}
1284
1285static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1286 u16 queue, int pad, int len, union eth_rx_cqe *cqe,
1287 u16 cqe_idx)
1288{
1289 struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
1290 struct sk_buff *skb = rx_buf->skb;
1291 /* alloc new skb */
1292 struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1293
1294 /* Unmap skb in the pool anyway, as we are going to change
1295 pool entry status to BNX2X_TPA_STOP even if new skb allocation
1296 fails. */
1297 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
1298 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1299
1300 /* if alloc failed drop the packet and keep the buffer in the bin */
1301 if (likely(new_skb)) {
1302
1303 prefetch(skb);
1304 prefetch(((char *)(skb)) + 128);
1305
1306 /* else fix ip xsum and give it to the stack */
1307 /* (no need to map the new skb) */
1308#ifdef BNX2X_STOP_ON_ERROR
1309 if (pad + len > bp->rx_buf_size) {
1310 BNX2X_ERR("skb_put is about to fail... "
1311 "pad %d len %d rx_buf_size %d\n",
1312 pad, len, bp->rx_buf_size);
1313 bnx2x_panic();
1314 return;
1315 }
1316#endif
1317
1318 skb_reserve(skb, pad);
1319 skb_put(skb, len);
1320
1321 skb->protocol = eth_type_trans(skb, bp->dev);
1322 skb->ip_summed = CHECKSUM_UNNECESSARY;
1323
1324 {
1325 struct iphdr *iph;
1326
1327 iph = (struct iphdr *)skb->data;
1328 iph->check = 0;
1329 iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
1330 }
1331
1332 if (!bnx2x_fill_frag_skb(bp, fp, skb,
1333 &cqe->fast_path_cqe, cqe_idx)) {
1334#ifdef BCM_VLAN
1335 if ((bp->vlgrp != NULL) &&
1336 (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1337 PARSING_FLAGS_VLAN))
1338 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1339 le16_to_cpu(cqe->fast_path_cqe.
1340 vlan_tag));
1341 else
1342#endif
1343 netif_receive_skb(skb);
1344 } else {
1345 DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
1346 " - dropping packet!\n");
1347 dev_kfree_skb(skb);
1348 }
1349
1350 bp->dev->last_rx = jiffies;
1351
1352 /* put new skb in bin */
1353 fp->tpa_pool[queue].skb = new_skb;
1354
1355 } else {
1356 DP(NETIF_MSG_RX_STATUS,
1357 "Failed to allocate new skb - dropping packet!\n");
1358 fp->rx_alloc_failed++;
1359 }
1360
1361 fp->tpa_state[queue] = BNX2X_TPA_STOP;
1362}
1363
1364static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
1365 struct bnx2x_fastpath *fp,
1366 u16 bd_prod, u16 rx_comp_prod,
1367 u16 rx_sge_prod)
1368{
1369 struct tstorm_eth_rx_producers rx_prods = {0};
1370 int i;
1371
1372 /* Update producers */
1373 rx_prods.bd_prod = bd_prod;
1374 rx_prods.cqe_prod = rx_comp_prod;
1375 rx_prods.sge_prod = rx_sge_prod;
1376
1377 for (i = 0; i < sizeof(struct tstorm_eth_rx_producers)/4; i++)
1378 REG_WR(bp, BAR_TSTRORM_INTMEM +
1379 TSTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,
1380 ((u32 *)&rx_prods)[i]);
1381
1382 DP(NETIF_MSG_RX_STATUS,
1383 "Wrote: bd_prod %u cqe_prod %u sge_prod %u\n",
1384 bd_prod, rx_comp_prod, rx_sge_prod);
1385}
1386
1387static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1388{
1389 struct bnx2x *bp = fp->bp;
1390 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1391 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1392 int rx_pkt = 0;
1393 u16 queue;
1394
1395#ifdef BNX2X_STOP_ON_ERROR
1396 if (unlikely(bp->panic))
1397 return 0;
1398#endif
1399
1400 /* CQ "next element" is of the size of the regular element,
1401 that's why it's ok here */
1402 hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
1403 if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
1404 hw_comp_cons++;
1405
1406 bd_cons = fp->rx_bd_cons;
1407 bd_prod = fp->rx_bd_prod;
1408 bd_prod_fw = bd_prod;
1409 sw_comp_cons = fp->rx_comp_cons;
1410 sw_comp_prod = fp->rx_comp_prod;
1411
1412 /* Memory barrier necessary as speculative reads of the rx
1413 * buffer can be ahead of the index in the status block
1414 */
1415 rmb();
1416
1417 DP(NETIF_MSG_RX_STATUS,
1418 "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
1419 FP_IDX(fp), hw_comp_cons, sw_comp_cons);
1420
1421 while (sw_comp_cons != hw_comp_cons) {
1422 struct sw_rx_bd *rx_buf = NULL;
1423 struct sk_buff *skb;
1424 union eth_rx_cqe *cqe;
1425 u8 cqe_fp_flags;
1426 u16 len, pad;
1427
1428 comp_ring_cons = RCQ_BD(sw_comp_cons);
1429 bd_prod = RX_BD(bd_prod);
1430 bd_cons = RX_BD(bd_cons);
1431
1432 cqe = &fp->rx_comp_ring[comp_ring_cons];
1433 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1434
1435 DP(NETIF_MSG_RX_STATUS, "CQE type %x err %x status %x"
1436 " queue %x vlan %x len %u\n", CQE_TYPE(cqe_fp_flags),
1437 cqe_fp_flags, cqe->fast_path_cqe.status_flags,
1438 cqe->fast_path_cqe.rss_hash_result,
1439 le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
1440 le16_to_cpu(cqe->fast_path_cqe.pkt_len));
1441
1442 /* is this a slowpath msg? */
1443 if (unlikely(CQE_TYPE(cqe_fp_flags))) {
1444 bnx2x_sp_event(fp, cqe);
1445 goto next_cqe;
1446
1447 /* this is an rx packet */
1448 } else {
1449 rx_buf = &fp->rx_buf_ring[bd_cons];
1450 skb = rx_buf->skb;
1451 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1452 pad = cqe->fast_path_cqe.placement_offset;
1453
1454 /* If CQE is marked both TPA_START and TPA_END
1455 it is a non-TPA CQE */
1456 if ((!fp->disable_tpa) &&
1457 (TPA_TYPE(cqe_fp_flags) !=
1458 (TPA_TYPE_START | TPA_TYPE_END))) {
1459 queue = cqe->fast_path_cqe.queue_index;
1460
1461 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1462 DP(NETIF_MSG_RX_STATUS,
1463 "calling tpa_start on queue %d\n",
1464 queue);
1465
1466 bnx2x_tpa_start(fp, queue, skb,
1467 bd_cons, bd_prod);
1468 goto next_rx;
1469 }
1470
1471 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
1472 DP(NETIF_MSG_RX_STATUS,
1473 "calling tpa_stop on queue %d\n",
1474 queue);
1475
1476 if (!BNX2X_RX_SUM_FIX(cqe))
1477 BNX2X_ERR("STOP on none TCP "
1478 "data\n");
1479
1480 /* This is a size of the linear data
1481 on this skb */
1482 len = le16_to_cpu(cqe->fast_path_cqe.
1483 len_on_bd);
1484 bnx2x_tpa_stop(bp, fp, queue, pad,
1485 len, cqe, comp_ring_cons);
1486#ifdef BNX2X_STOP_ON_ERROR
1487 if (bp->panic)
1488 return -EINVAL;
1489#endif
1490
1491 bnx2x_update_sge_prod(fp,
1492 &cqe->fast_path_cqe);
1493 goto next_cqe;
1494 }
1495 }
1496
1497 pci_dma_sync_single_for_device(bp->pdev,
1498 pci_unmap_addr(rx_buf, mapping),
1499 pad + RX_COPY_THRESH,
1500 PCI_DMA_FROMDEVICE);
1501 prefetch(skb);
1502 prefetch(((char *)(skb)) + 128);
1503
1504 /* is this an error packet? */
1505 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1506 /* do we sometimes forward error packets anyway? */
1507 DP(NETIF_MSG_RX_ERR,
1508 "ERROR flags %x rx packet %u\n",
1509 cqe_fp_flags, sw_comp_cons);
1510 /* TBD make sure MC counts this as a drop */
1511 goto reuse_rx;
1512 }
1513
1514 /* Since we don't have a jumbo ring
1515 * copy small packets if mtu > 1500
1516 */
1517 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1518 (len <= RX_COPY_THRESH)) {
1519 struct sk_buff *new_skb;
1520
1521 new_skb = netdev_alloc_skb(bp->dev,
1522 len + pad);
1523 if (new_skb == NULL) {
1524 DP(NETIF_MSG_RX_ERR,
1525 "ERROR packet dropped "
1526 "because of alloc failure\n");
1527 fp->rx_alloc_failed++;
1528 goto reuse_rx;
1529 }
1530
1531 /* aligned copy */
1532 skb_copy_from_linear_data_offset(skb, pad,
1533 new_skb->data + pad, len);
1534 skb_reserve(new_skb, pad);
1535 skb_put(new_skb, len);
1536
1537 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1538
1539 skb = new_skb;
1540
1541 } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
1542 pci_unmap_single(bp->pdev,
1543 pci_unmap_addr(rx_buf, mapping),
1544 bp->rx_buf_use_size,
1545 PCI_DMA_FROMDEVICE);
1546 skb_reserve(skb, pad);
1547 skb_put(skb, len);
1548
1549 } else {
1550 DP(NETIF_MSG_RX_ERR,
1551 "ERROR packet dropped because "
1552 "of alloc failure\n");
1553 fp->rx_alloc_failed++;
1554reuse_rx:
1555 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1556 goto next_rx;
1557 }
1558
1559 skb->protocol = eth_type_trans(skb, bp->dev);
1560
1561 skb->ip_summed = CHECKSUM_NONE;
1562 if (bp->rx_csum && BNX2X_RX_SUM_OK(cqe))
1563 skb->ip_summed = CHECKSUM_UNNECESSARY;
1564
1565 /* TBD do we pass bad csum packets in promisc */
1566 }
1567
1568#ifdef BCM_VLAN
1569 if ((bp->vlgrp != NULL) &&
1570 (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1571 PARSING_FLAGS_VLAN))
1572 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1573 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1574 else
1575#endif
1576 netif_receive_skb(skb);
1577
1578 bp->dev->last_rx = jiffies;
1579
1580next_rx:
1581 rx_buf->skb = NULL;
1582
1583 bd_cons = NEXT_RX_IDX(bd_cons);
1584 bd_prod = NEXT_RX_IDX(bd_prod);
1585 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1586 rx_pkt++;
1587next_cqe:
1588 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1589 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1590
1591 if (rx_pkt == budget)
1592 break;
1593 } /* while */
1594
1595 fp->rx_bd_cons = bd_cons;
1596 fp->rx_bd_prod = bd_prod_fw;
1597 fp->rx_comp_cons = sw_comp_cons;
1598 fp->rx_comp_prod = sw_comp_prod;
1599
1600 /* Update producers */
1601 bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1602 fp->rx_sge_prod);
1603 mmiowb(); /* keep prod updates ordered */
1604
1605 fp->rx_pkt += rx_pkt;
1606 fp->rx_calls++;
1607
1608 return rx_pkt;
1609}
1610
1611static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1612{
1613 struct bnx2x_fastpath *fp = fp_cookie;
1614 struct bnx2x *bp = fp->bp;
1615 struct net_device *dev = bp->dev;
1616 int index = FP_IDX(fp);
1617
1618 DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1619 index, FP_SB_ID(fp));
1620 bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0);
1621
1622#ifdef BNX2X_STOP_ON_ERROR
1623 if (unlikely(bp->panic))
1624 return IRQ_HANDLED;
1625#endif
1626
1627 prefetch(fp->rx_cons_sb);
1628 prefetch(fp->tx_cons_sb);
1629 prefetch(&fp->status_blk->c_status_block.status_block_index);
1630 prefetch(&fp->status_blk->u_status_block.status_block_index);
1631
1632 netif_rx_schedule(dev, &bnx2x_fp(bp, index, napi));
1633
1634 return IRQ_HANDLED;
1635}
1636
1637static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1638{
1639 struct net_device *dev = dev_instance;
1640 struct bnx2x *bp = netdev_priv(dev);
1641 u16 status = bnx2x_ack_int(bp);
1642 u16 mask;
1643
1644 /* Return here if interrupt is shared and it's not for us */
1645 if (unlikely(status == 0)) {
1646 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1647 return IRQ_NONE;
1648 }
1649 DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status);
1650
1651#ifdef BNX2X_STOP_ON_ERROR
1652 if (unlikely(bp->panic))
1653 return IRQ_HANDLED;
1654#endif
1655
1656 /* Return here if interrupt is disabled */
1657 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1658 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1659 return IRQ_HANDLED;
1660 }
1661
1662 mask = 0x2 << bp->fp[0].sb_id;
1663 if (status & mask) {
1664 struct bnx2x_fastpath *fp = &bp->fp[0];
1665
1666 prefetch(fp->rx_cons_sb);
1667 prefetch(fp->tx_cons_sb);
1668 prefetch(&fp->status_blk->c_status_block.status_block_index);
1669 prefetch(&fp->status_blk->u_status_block.status_block_index);
1670
1671 netif_rx_schedule(dev, &bnx2x_fp(bp, 0, napi));
1672
1673 status &= ~mask;
1674 }
1675
1676
1677 if (unlikely(status & 0x1)) {
1678 schedule_work(&bp->sp_task);
1679
1680 status &= ~0x1;
1681 if (!status)
1682 return IRQ_HANDLED;
1683 }
1684
1685 if (status)
1686 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
1687 status);
1688
1689 return IRQ_HANDLED;
1690}
1691
1692/* end of fast path */
1693
1694static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1695
1696/* Link */
1697
1698/*
1699 * General service functions
1700 */
1701
1702static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1703{
1704 u32 lock_status;
1705 u32 resource_bit = (1 << resource);
1706 u8 port = BP_PORT(bp);
1707 int cnt;
1708
1709 /* Validating that the resource is within range */
1710 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1711 DP(NETIF_MSG_HW,
1712 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1713 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1714 return -EINVAL;
1715 }
1716
1717 /* Validating that the resource is not already taken */
1718 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1719 if (lock_status & resource_bit) {
1720 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1721 lock_status, resource_bit);
1722 return -EEXIST;
1723 }
1724
1725 /* Try for 1 second every 5ms */
1726 for (cnt = 0; cnt < 200; cnt++) {
1727 /* Try to acquire the lock */
1728 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8 + 4,
1729 resource_bit);
1730 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1731 if (lock_status & resource_bit)
1732 return 0;
1733
1734 msleep(5);
1735 }
1736 DP(NETIF_MSG_HW, "Timeout\n");
1737 return -EAGAIN;
1738}
1739
1740static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
1741{
1742 u32 lock_status;
1743 u32 resource_bit = (1 << resource);
1744 u8 port = BP_PORT(bp);
1745
1746 /* Validating that the resource is within range */
1747 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1748 DP(NETIF_MSG_HW,
1749 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1750 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1751 return -EINVAL;
1752 }
1753
1754 /* Validating that the resource is currently taken */
1755 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1756 if (!(lock_status & resource_bit)) {
1757 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1758 lock_status, resource_bit);
1759 return -EFAULT;
1760 }
1761
1762 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8, resource_bit);
1763 return 0;
1764}
1765
1766/* HW Lock for shared dual port PHYs */
1767static void bnx2x_phy_hw_lock(struct bnx2x *bp)
1768{
1769 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1770
1771 mutex_lock(&bp->port.phy_mutex);
1772
1773 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1774 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1775 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1776}
1777
1778static void bnx2x_phy_hw_unlock(struct bnx2x *bp)
1779{
1780 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1781
1782 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1783 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1784 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1785
1786 mutex_unlock(&bp->port.phy_mutex);
1787}
1788
1789int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1790{
1791 /* The GPIO should be swapped if swap register is set and active */
1792 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1793 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ BP_PORT(bp);
1794 int gpio_shift = gpio_num +
1795 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1796 u32 gpio_mask = (1 << gpio_shift);
1797 u32 gpio_reg;
1798
1799 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1800 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1801 return -EINVAL;
1802 }
1803
1804 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1805 /* read GPIO and mask except the float bits */
1806 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1807
1808 switch (mode) {
1809 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1810 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1811 gpio_num, gpio_shift);
1812 /* clear FLOAT and set CLR */
1813 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1814 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1815 break;
1816
1817 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1818 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1819 gpio_num, gpio_shift);
1820 /* clear FLOAT and set SET */
1821 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1822 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1823 break;
1824
1825 case MISC_REGISTERS_GPIO_INPUT_HI_Z :
1826 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1827 gpio_num, gpio_shift);
1828 /* set FLOAT */
1829 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1830 break;
1831
1832 default:
1833 break;
1834 }
1835
1836 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1837 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_GPIO);
1838
1839 return 0;
1840}
1841
1842static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1843{
1844 u32 spio_mask = (1 << spio_num);
1845 u32 spio_reg;
1846
1847 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1848 (spio_num > MISC_REGISTERS_SPIO_7)) {
1849 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1850 return -EINVAL;
1851 }
1852
1853 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1854 /* read SPIO and mask except the float bits */
1855 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1856
1857 switch (mode) {
1858 case MISC_REGISTERS_SPIO_OUTPUT_LOW :
1859 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1860 /* clear FLOAT and set CLR */
1861 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1862 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1863 break;
1864
1865 case MISC_REGISTERS_SPIO_OUTPUT_HIGH :
1866 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1867 /* clear FLOAT and set SET */
1868 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1869 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1870 break;
1871
1872 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1873 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1874 /* set FLOAT */
1875 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1876 break;
1877
1878 default:
1879 break;
1880 }
1881
1882 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1883 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_SPIO);
1884
1885 return 0;
1886}
1887
1888static void bnx2x_calc_fc_adv(struct bnx2x *bp)
1889{
1890 switch (bp->link_vars.ieee_fc) {
1891 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1892 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1893 ADVERTISED_Pause);
1894 break;
1895 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1896 bp->port.advertising |= (ADVERTISED_Asym_Pause |
1897 ADVERTISED_Pause);
1898 break;
1899 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1900 bp->port.advertising |= ADVERTISED_Asym_Pause;
1901 break;
1902 default:
1903 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1904 ADVERTISED_Pause);
1905 break;
1906 }
1907}
1908
1909static void bnx2x_link_report(struct bnx2x *bp)
1910{
1911 if (bp->link_vars.link_up) {
1912 if (bp->state == BNX2X_STATE_OPEN)
1913 netif_carrier_on(bp->dev);
1914 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
1915
1916 printk("%d Mbps ", bp->link_vars.line_speed);
1917
1918 if (bp->link_vars.duplex == DUPLEX_FULL)
1919 printk("full duplex");
1920 else
1921 printk("half duplex");
1922
1923 if (bp->link_vars.flow_ctrl != FLOW_CTRL_NONE) {
1924 if (bp->link_vars.flow_ctrl & FLOW_CTRL_RX) {
1925 printk(", receive ");
1926 if (bp->link_vars.flow_ctrl & FLOW_CTRL_TX)
1927 printk("& transmit ");
1928 } else {
1929 printk(", transmit ");
1930 }
1931 printk("flow control ON");
1932 }
1933 printk("\n");
1934
1935 } else { /* link_down */
1936 netif_carrier_off(bp->dev);
1937 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
1938 }
1939}
1940
1941static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1942{
1943 u8 rc;
1944
1945 /* Initialize link parameters structure variables */
1946 bp->link_params.mtu = bp->dev->mtu;
1947
1948 bnx2x_phy_hw_lock(bp);
1949 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1950 bnx2x_phy_hw_unlock(bp);
1951
1952 if (bp->link_vars.link_up)
1953 bnx2x_link_report(bp);
1954
1955 bnx2x_calc_fc_adv(bp);
1956
1957 return rc;
1958}
1959
1960static void bnx2x_link_set(struct bnx2x *bp)
1961{
1962 bnx2x_phy_hw_lock(bp);
1963 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1964 bnx2x_phy_hw_unlock(bp);
1965
1966 bnx2x_calc_fc_adv(bp);
1967}
1968
1969static void bnx2x__link_reset(struct bnx2x *bp)
1970{
1971 bnx2x_phy_hw_lock(bp);
1972 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
1973 bnx2x_phy_hw_unlock(bp);
1974}
1975
1976static u8 bnx2x_link_test(struct bnx2x *bp)
1977{
1978 u8 rc;
1979
1980 bnx2x_phy_hw_lock(bp);
1981 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
1982 bnx2x_phy_hw_unlock(bp);
1983
1984 return rc;
1985}
1986
1987/* Calculates the sum of vn_min_rates.
1988 It's needed for further normalizing of the min_rates.
1989
1990 Returns:
1991 sum of vn_min_rates
1992 or
1993 0 - if all the min_rates are 0.
1994 In the later case fainess algorithm should be deactivated.
1995 If not all min_rates are zero then those that are zeroes will
1996 be set to 1.
1997 */
1998static u32 bnx2x_calc_vn_wsum(struct bnx2x *bp)
1999{
2000 int i, port = BP_PORT(bp);
2001 u32 wsum = 0;
2002 int all_zero = 1;
2003
2004 for (i = 0; i < E1HVN_MAX; i++) {
2005 u32 vn_cfg =
2006 SHMEM_RD(bp, mf_cfg.func_mf_config[2*i + port].config);
2007 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2008 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2009 if (!(vn_cfg & FUNC_MF_CFG_FUNC_HIDE)) {
2010 /* If min rate is zero - set it to 1 */
2011 if (!vn_min_rate)
2012 vn_min_rate = DEF_MIN_RATE;
2013 else
2014 all_zero = 0;
2015
2016 wsum += vn_min_rate;
2017 }
2018 }
2019
2020 /* ... only if all min rates are zeros - disable FAIRNESS */
2021 if (all_zero)
2022 return 0;
2023
2024 return wsum;
2025}
2026
2027static void bnx2x_init_port_minmax(struct bnx2x *bp,
2028 int en_fness,
2029 u16 port_rate,
2030 struct cmng_struct_per_port *m_cmng_port)
2031{
2032 u32 r_param = port_rate / 8;
2033 int port = BP_PORT(bp);
2034 int i;
2035
2036 memset(m_cmng_port, 0, sizeof(struct cmng_struct_per_port));
2037
2038 /* Enable minmax only if we are in e1hmf mode */
2039 if (IS_E1HMF(bp)) {
2040 u32 fair_periodic_timeout_usec;
2041 u32 t_fair;
2042
2043 /* Enable rate shaping and fairness */
2044 m_cmng_port->flags.cmng_vn_enable = 1;
2045 m_cmng_port->flags.fairness_enable = en_fness ? 1 : 0;
2046 m_cmng_port->flags.rate_shaping_enable = 1;
2047
2048 if (!en_fness)
2049 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2050 " fairness will be disabled\n");
2051
2052 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2053 m_cmng_port->rs_vars.rs_periodic_timeout =
2054 RS_PERIODIC_TIMEOUT_USEC / 4;
2055
2056 /* this is the threshold below which no timer arming will occur
2057 1.25 coefficient is for the threshold to be a little bigger
2058 than the real time, to compensate for timer in-accuracy */
2059 m_cmng_port->rs_vars.rs_threshold =
2060 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2061
2062 /* resolution of fairness timer */
2063 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2064 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2065 t_fair = T_FAIR_COEF / port_rate;
2066
2067 /* this is the threshold below which we won't arm
2068 the timer anymore */
2069 m_cmng_port->fair_vars.fair_threshold = QM_ARB_BYTES;
2070
2071 /* we multiply by 1e3/8 to get bytes/msec.
2072 We don't want the credits to pass a credit
2073 of the T_FAIR*FAIR_MEM (algorithm resolution) */
2074 m_cmng_port->fair_vars.upper_bound =
2075 r_param * t_fair * FAIR_MEM;
2076 /* since each tick is 4 usec */
2077 m_cmng_port->fair_vars.fairness_timeout =
2078 fair_periodic_timeout_usec / 4;
2079
2080 } else {
2081 /* Disable rate shaping and fairness */
2082 m_cmng_port->flags.cmng_vn_enable = 0;
2083 m_cmng_port->flags.fairness_enable = 0;
2084 m_cmng_port->flags.rate_shaping_enable = 0;
2085
2086 DP(NETIF_MSG_IFUP,
2087 "Single function mode minmax will be disabled\n");
2088 }
2089
2090 /* Store it to internal memory */
2091 for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
2092 REG_WR(bp, BAR_XSTRORM_INTMEM +
2093 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
2094 ((u32 *)(m_cmng_port))[i]);
2095}
2096
2097static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func,
2098 u32 wsum, u16 port_rate,
2099 struct cmng_struct_per_port *m_cmng_port)
2100{
2101 struct rate_shaping_vars_per_vn m_rs_vn;
2102 struct fairness_vars_per_vn m_fair_vn;
2103 u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
2104 u16 vn_min_rate, vn_max_rate;
2105 int i;
2106
2107 /* If function is hidden - set min and max to zeroes */
2108 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2109 vn_min_rate = 0;
2110 vn_max_rate = 0;
2111
2112 } else {
2113 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2114 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2115 /* If FAIRNESS is enabled (not all min rates are zeroes) and
2116 if current min rate is zero - set it to 1.
2117 This is a requirment of the algorithm. */
2118 if ((vn_min_rate == 0) && wsum)
2119 vn_min_rate = DEF_MIN_RATE;
2120 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
2121 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
2122 }
2123
2124 DP(NETIF_MSG_IFUP, "func %d: vn_min_rate=%d vn_max_rate=%d "
2125 "wsum=%d\n", func, vn_min_rate, vn_max_rate, wsum);
2126
2127 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2128 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2129
2130 /* global vn counter - maximal Mbps for this vn */
2131 m_rs_vn.vn_counter.rate = vn_max_rate;
2132
2133 /* quota - number of bytes transmitted in this period */
2134 m_rs_vn.vn_counter.quota =
2135 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2136
2137#ifdef BNX2X_PER_PROT_QOS
2138 /* per protocol counter */
2139 for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++) {
2140 /* maximal Mbps for this protocol */
2141 m_rs_vn.protocol_counters[protocol].rate =
2142 protocol_max_rate[protocol];
2143 /* the quota in each timer period -
2144 number of bytes transmitted in this period */
2145 m_rs_vn.protocol_counters[protocol].quota =
2146 (u32)(rs_periodic_timeout_usec *
2147 ((double)m_rs_vn.
2148 protocol_counters[protocol].rate/8));
2149 }
2150#endif
2151
2152 if (wsum) {
2153 /* credit for each period of the fairness algorithm:
2154 number of bytes in T_FAIR (the vn share the port rate).
2155 wsum should not be larger than 10000, thus
2156 T_FAIR_COEF / (8 * wsum) will always be grater than zero */
2157 m_fair_vn.vn_credit_delta =
2158 max((u64)(vn_min_rate * (T_FAIR_COEF / (8 * wsum))),
2159 (u64)(m_cmng_port->fair_vars.fair_threshold * 2));
2160 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
2161 m_fair_vn.vn_credit_delta);
2162 }
2163
2164#ifdef BNX2X_PER_PROT_QOS
2165 do {
2166 u32 protocolWeightSum = 0;
2167
2168 for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++)
2169 protocolWeightSum +=
2170 drvInit.protocol_min_rate[protocol];
2171 /* per protocol counter -
2172 NOT NEEDED IF NO PER-PROTOCOL CONGESTION MANAGEMENT */
2173 if (protocolWeightSum > 0) {
2174 for (protocol = 0;
2175 protocol < NUM_OF_PROTOCOLS; protocol++)
2176 /* credit for each period of the
2177 fairness algorithm - number of bytes in
2178 T_FAIR (the protocol share the vn rate) */
2179 m_fair_vn.protocol_credit_delta[protocol] =
2180 (u32)((vn_min_rate / 8) * t_fair *
2181 protocol_min_rate / protocolWeightSum);
2182 }
2183 } while (0);
2184#endif
2185
2186 /* Store it to internal memory */
2187 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2188 REG_WR(bp, BAR_XSTRORM_INTMEM +
2189 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2190 ((u32 *)(&m_rs_vn))[i]);
2191
2192 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2193 REG_WR(bp, BAR_XSTRORM_INTMEM +
2194 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2195 ((u32 *)(&m_fair_vn))[i]);
2196}
2197
2198/* This function is called upon link interrupt */
2199static void bnx2x_link_attn(struct bnx2x *bp)
2200{
2201 int vn;
2202
2203 /* Make sure that we are synced with the current statistics */
2204 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2205
2206 bnx2x_phy_hw_lock(bp);
2207 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2208 bnx2x_phy_hw_unlock(bp);
2209
2210 if (bp->link_vars.link_up) {
2211
2212 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2213 struct host_port_stats *pstats;
2214
2215 pstats = bnx2x_sp(bp, port_stats);
2216 /* reset old bmac stats */
2217 memset(&(pstats->mac_stx[0]), 0,
2218 sizeof(struct mac_stx));
2219 }
2220 if ((bp->state == BNX2X_STATE_OPEN) ||
2221 (bp->state == BNX2X_STATE_DISABLED))
2222 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2223 }
2224
2225 /* indicate link status */
2226 bnx2x_link_report(bp);
2227
2228 if (IS_E1HMF(bp)) {
2229 int func;
2230
2231 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2232 if (vn == BP_E1HVN(bp))
2233 continue;
2234
2235 func = ((vn << 1) | BP_PORT(bp));
2236
2237 /* Set the attention towards other drivers
2238 on the same port */
2239 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2240 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2241 }
2242 }
2243
2244 if (CHIP_IS_E1H(bp) && (bp->link_vars.line_speed > 0)) {
2245 struct cmng_struct_per_port m_cmng_port;
2246 u32 wsum;
2247 int port = BP_PORT(bp);
2248
2249 /* Init RATE SHAPING and FAIRNESS contexts */
2250 wsum = bnx2x_calc_vn_wsum(bp);
2251 bnx2x_init_port_minmax(bp, (int)wsum,
2252 bp->link_vars.line_speed,
2253 &m_cmng_port);
2254 if (IS_E1HMF(bp))
2255 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2256 bnx2x_init_vn_minmax(bp, 2*vn + port,
2257 wsum, bp->link_vars.line_speed,
2258 &m_cmng_port);
2259 }
2260}
2261
2262static void bnx2x__link_status_update(struct bnx2x *bp)
2263{
2264 if (bp->state != BNX2X_STATE_OPEN)
2265 return;
2266
2267 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2268
2269 if (bp->link_vars.link_up)
2270 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2271 else
2272 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2273
2274 /* indicate link status */
2275 bnx2x_link_report(bp);
2276}
2277
2278static void bnx2x_pmf_update(struct bnx2x *bp)
2279{
2280 int port = BP_PORT(bp);
2281 u32 val;
2282
2283 bp->port.pmf = 1;
2284 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2285
2286 /* enable nig attention */
2287 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2288 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2289 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2290
2291 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2292}
2293
2294/* end of Link */
2295
2296/* slow path */
2297
2298/*
2299 * General service functions
2300 */
2301
2302/* the slow path queue is odd since completions arrive on the fastpath ring */
2303static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2304 u32 data_hi, u32 data_lo, int common)
2305{
2306 int func = BP_FUNC(bp);
2307
2308 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2309 "SPQE (%x:%x) command %d hw_cid %x data (%x:%x) left %x\n",
2310 (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
2311 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2312 HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
2313
2314#ifdef BNX2X_STOP_ON_ERROR
2315 if (unlikely(bp->panic))
2316 return -EIO;
2317#endif
2318
2319 spin_lock_bh(&bp->spq_lock);
2320
2321 if (!bp->spq_left) {
2322 BNX2X_ERR("BUG! SPQ ring full!\n");
2323 spin_unlock_bh(&bp->spq_lock);
2324 bnx2x_panic();
2325 return -EBUSY;
2326 }
2327
2328 /* CID needs port number to be encoded int it */
2329 bp->spq_prod_bd->hdr.conn_and_cmd_data =
2330 cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
2331 HW_CID(bp, cid)));
2332 bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
2333 if (common)
2334 bp->spq_prod_bd->hdr.type |=
2335 cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
2336
2337 bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
2338 bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
2339
2340 bp->spq_left--;
2341
2342 if (bp->spq_prod_bd == bp->spq_last_bd) {
2343 bp->spq_prod_bd = bp->spq;
2344 bp->spq_prod_idx = 0;
2345 DP(NETIF_MSG_TIMER, "end of spq\n");
2346
2347 } else {
2348 bp->spq_prod_bd++;
2349 bp->spq_prod_idx++;
2350 }
2351
2352 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2353 bp->spq_prod_idx);
2354
2355 spin_unlock_bh(&bp->spq_lock);
2356 return 0;
2357}
2358
2359/* acquire split MCP access lock register */
2360static int bnx2x_lock_alr(struct bnx2x *bp)
2361{
2362 u32 i, j, val;
2363 int rc = 0;
2364
2365 might_sleep();
2366 i = 100;
2367 for (j = 0; j < i*10; j++) {
2368 val = (1UL << 31);
2369 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2370 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2371 if (val & (1L << 31))
2372 break;
2373
2374 msleep(5);
2375 }
2376 if (!(val & (1L << 31))) {
2377 BNX2X_ERR("Cannot acquire nvram interface\n");
2378 rc = -EBUSY;
2379 }
2380
2381 return rc;
2382}
2383
2384/* Release split MCP access lock register */
2385static void bnx2x_unlock_alr(struct bnx2x *bp)
2386{
2387 u32 val = 0;
2388
2389 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2390}
2391
2392static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2393{
2394 struct host_def_status_block *def_sb = bp->def_status_blk;
2395 u16 rc = 0;
2396
2397 barrier(); /* status block is written to by the chip */
2398
2399 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2400 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2401 rc |= 1;
2402 }
2403 if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
2404 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
2405 rc |= 2;
2406 }
2407 if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
2408 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
2409 rc |= 4;
2410 }
2411 if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
2412 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
2413 rc |= 8;
2414 }
2415 if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
2416 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
2417 rc |= 16;
2418 }
2419 return rc;
2420}
2421
2422/*
2423 * slow path service functions
2424 */
2425
2426static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2427{
2428 int port = BP_PORT(bp);
2429 int func = BP_FUNC(bp);
2430 u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_FUNC_BASE * func) * 8;
2431 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2432 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2433 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2434 NIG_REG_MASK_INTERRUPT_PORT0;
2435
2436 if (~bp->aeu_mask & (asserted & 0xff))
2437 BNX2X_ERR("IGU ERROR\n");
2438 if (bp->attn_state & asserted)
2439 BNX2X_ERR("IGU ERROR\n");
2440
2441 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
2442 bp->aeu_mask, asserted);
2443 bp->aeu_mask &= ~(asserted & 0xff);
2444 DP(NETIF_MSG_HW, "after masking: aeu_mask %x\n", bp->aeu_mask);
2445
2446 REG_WR(bp, aeu_addr, bp->aeu_mask);
2447
2448 bp->attn_state |= asserted;
2449
2450 if (asserted & ATTN_HARD_WIRED_MASK) {
2451 if (asserted & ATTN_NIG_FOR_FUNC) {
2452
2453 /* save nig interrupt mask */
2454 bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
2455 REG_WR(bp, nig_int_mask_addr, 0);
2456
2457 bnx2x_link_attn(bp);
2458
2459 /* handle unicore attn? */
2460 }
2461 if (asserted & ATTN_SW_TIMER_4_FUNC)
2462 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2463
2464 if (asserted & GPIO_2_FUNC)
2465 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2466
2467 if (asserted & GPIO_3_FUNC)
2468 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2469
2470 if (asserted & GPIO_4_FUNC)
2471 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2472
2473 if (port == 0) {
2474 if (asserted & ATTN_GENERAL_ATTN_1) {
2475 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2476 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2477 }
2478 if (asserted & ATTN_GENERAL_ATTN_2) {
2479 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2480 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2481 }
2482 if (asserted & ATTN_GENERAL_ATTN_3) {
2483 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2484 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2485 }
2486 } else {
2487 if (asserted & ATTN_GENERAL_ATTN_4) {
2488 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2489 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2490 }
2491 if (asserted & ATTN_GENERAL_ATTN_5) {
2492 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2493 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2494 }
2495 if (asserted & ATTN_GENERAL_ATTN_6) {
2496 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2497 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2498 }
2499 }
2500
2501 } /* if hardwired */
2502
2503 DP(NETIF_MSG_HW, "about to mask 0x%08x at IGU addr 0x%x\n",
2504 asserted, BAR_IGU_INTMEM + igu_addr);
2505 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, asserted);
2506
2507 /* now set back the mask */
2508 if (asserted & ATTN_NIG_FOR_FUNC)
2509 REG_WR(bp, nig_int_mask_addr, bp->nig_mask);
2510}
2511
2512static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2513{
2514 int port = BP_PORT(bp);
2515 int reg_offset;
2516 u32 val;
2517
2518 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2519 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2520
2521 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2522
2523 val = REG_RD(bp, reg_offset);
2524 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2525 REG_WR(bp, reg_offset, val);
2526
2527 BNX2X_ERR("SPIO5 hw attention\n");
2528
2529 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
2530 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
2531 /* Fan failure attention */
2532
2533 /* The PHY reset is controled by GPIO 1 */
2534 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2535 MISC_REGISTERS_GPIO_OUTPUT_LOW);
2536 /* Low power mode is controled by GPIO 2 */
2537 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2538 MISC_REGISTERS_GPIO_OUTPUT_LOW);
2539 /* mark the failure */
2540 bp->link_params.ext_phy_config &=
2541 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2542 bp->link_params.ext_phy_config |=
2543 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2544 SHMEM_WR(bp,
2545 dev_info.port_hw_config[port].
2546 external_phy_config,
2547 bp->link_params.ext_phy_config);
2548 /* log the failure */
2549 printk(KERN_ERR PFX "Fan Failure on Network"
2550 " Controller %s has caused the driver to"
2551 " shutdown the card to prevent permanent"
2552 " damage. Please contact Dell Support for"
2553 " assistance\n", bp->dev->name);
2554 break;
2555
2556 default:
2557 break;
2558 }
2559 }
2560
2561 if (attn & HW_INTERRUT_ASSERT_SET_0) {
2562
2563 val = REG_RD(bp, reg_offset);
2564 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
2565 REG_WR(bp, reg_offset, val);
2566
2567 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
2568 (attn & HW_INTERRUT_ASSERT_SET_0));
2569 bnx2x_panic();
2570 }
2571}
2572
2573static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
2574{
2575 u32 val;
2576
2577 if (attn & BNX2X_DOORQ_ASSERT) {
2578
2579 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
2580 BNX2X_ERR("DB hw attention 0x%x\n", val);
2581 /* DORQ discard attention */
2582 if (val & 0x2)
2583 BNX2X_ERR("FATAL error from DORQ\n");
2584 }
2585
2586 if (attn & HW_INTERRUT_ASSERT_SET_1) {
2587
2588 int port = BP_PORT(bp);
2589 int reg_offset;
2590
2591 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
2592 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
2593
2594 val = REG_RD(bp, reg_offset);
2595 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
2596 REG_WR(bp, reg_offset, val);
2597
2598 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
2599 (attn & HW_INTERRUT_ASSERT_SET_1));
2600 bnx2x_panic();
2601 }
2602}
2603
2604static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
2605{
2606 u32 val;
2607
2608 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
2609
2610 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
2611 BNX2X_ERR("CFC hw attention 0x%x\n", val);
2612 /* CFC error attention */
2613 if (val & 0x2)
2614 BNX2X_ERR("FATAL error from CFC\n");
2615 }
2616
2617 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
2618
2619 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
2620 BNX2X_ERR("PXP hw attention 0x%x\n", val);
2621 /* RQ_USDMDP_FIFO_OVERFLOW */
2622 if (val & 0x18000)
2623 BNX2X_ERR("FATAL error from PXP\n");
2624 }
2625
2626 if (attn & HW_INTERRUT_ASSERT_SET_2) {
2627
2628 int port = BP_PORT(bp);
2629 int reg_offset;
2630
2631 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
2632 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
2633
2634 val = REG_RD(bp, reg_offset);
2635 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
2636 REG_WR(bp, reg_offset, val);
2637
2638 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
2639 (attn & HW_INTERRUT_ASSERT_SET_2));
2640 bnx2x_panic();
2641 }
2642}
2643
2644static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2645{
2646 u32 val;
2647
2648 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
2649
2650 if (attn & BNX2X_PMF_LINK_ASSERT) {
2651 int func = BP_FUNC(bp);
2652
2653 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
2654 bnx2x__link_status_update(bp);
2655 if (SHMEM_RD(bp, func_mb[func].drv_status) &
2656 DRV_STATUS_PMF)
2657 bnx2x_pmf_update(bp);
2658
2659 } else if (attn & BNX2X_MC_ASSERT_BITS) {
2660
2661 BNX2X_ERR("MC assert!\n");
2662 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
2663 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
2664 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
2665 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
2666 bnx2x_panic();
2667
2668 } else if (attn & BNX2X_MCP_ASSERT) {
2669
2670 BNX2X_ERR("MCP assert!\n");
2671 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
2672 bnx2x_fw_dump(bp);
2673
2674 } else
2675 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
2676 }
2677
2678 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
2679 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
2680 if (attn & BNX2X_GRC_TIMEOUT) {
2681 val = CHIP_IS_E1H(bp) ?
2682 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
2683 BNX2X_ERR("GRC time-out 0x%08x\n", val);
2684 }
2685 if (attn & BNX2X_GRC_RSV) {
2686 val = CHIP_IS_E1H(bp) ?
2687 REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
2688 BNX2X_ERR("GRC reserved 0x%08x\n", val);
2689 }
2690 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
2691 }
2692}
2693
2694static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2695{
2696 struct attn_route attn;
2697 struct attn_route group_mask;
2698 int port = BP_PORT(bp);
2699 int index;
2700 u32 reg_addr;
2701 u32 val;
2702
2703 /* need to take HW lock because MCP or other port might also
2704 try to handle this event */
2705 bnx2x_lock_alr(bp);
2706
2707 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2708 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
2709 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
2710 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
2711 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
2712 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
2713
2714 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
2715 if (deasserted & (1 << index)) {
2716 group_mask = bp->attn_group[index];
2717
2718 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
2719 index, group_mask.sig[0], group_mask.sig[1],
2720 group_mask.sig[2], group_mask.sig[3]);
2721
2722 bnx2x_attn_int_deasserted3(bp,
2723 attn.sig[3] & group_mask.sig[3]);
2724 bnx2x_attn_int_deasserted1(bp,
2725 attn.sig[1] & group_mask.sig[1]);
2726 bnx2x_attn_int_deasserted2(bp,
2727 attn.sig[2] & group_mask.sig[2]);
2728 bnx2x_attn_int_deasserted0(bp,
2729 attn.sig[0] & group_mask.sig[0]);
2730
2731 if ((attn.sig[0] & group_mask.sig[0] &
2732 HW_PRTY_ASSERT_SET_0) ||
2733 (attn.sig[1] & group_mask.sig[1] &
2734 HW_PRTY_ASSERT_SET_1) ||
2735 (attn.sig[2] & group_mask.sig[2] &
2736 HW_PRTY_ASSERT_SET_2))
2737 BNX2X_ERR("FATAL HW block parity attention\n");
2738 }
2739 }
2740
2741 bnx2x_unlock_alr(bp);
2742
2743 reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8;
2744
2745 val = ~deasserted;
2746/* DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
2747 val, BAR_IGU_INTMEM + reg_addr); */
2748 REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val);
2749
2750 if (bp->aeu_mask & (deasserted & 0xff))
2751 BNX2X_ERR("IGU BUG!\n");
2752 if (~bp->attn_state & deasserted)
2753 BNX2X_ERR("IGU BUG!\n");
2754
2755 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2756 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2757
2758 DP(NETIF_MSG_HW, "aeu_mask %x\n", bp->aeu_mask);
2759 bp->aeu_mask |= (deasserted & 0xff);
2760
2761 DP(NETIF_MSG_HW, "new mask %x\n", bp->aeu_mask);
2762 REG_WR(bp, reg_addr, bp->aeu_mask);
2763
2764 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2765 bp->attn_state &= ~deasserted;
2766 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2767}
2768
2769static void bnx2x_attn_int(struct bnx2x *bp)
2770{
2771 /* read local copy of bits */
2772 u32 attn_bits = bp->def_status_blk->atten_status_block.attn_bits;
2773 u32 attn_ack = bp->def_status_blk->atten_status_block.attn_bits_ack;
2774 u32 attn_state = bp->attn_state;
2775
2776 /* look for changed bits */
2777 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
2778 u32 deasserted = ~attn_bits & attn_ack & attn_state;
2779
2780 DP(NETIF_MSG_HW,
2781 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
2782 attn_bits, attn_ack, asserted, deasserted);
2783
2784 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
2785 BNX2X_ERR("BAD attention state\n");
2786
2787 /* handle bits that were raised */
2788 if (asserted)
2789 bnx2x_attn_int_asserted(bp, asserted);
2790
2791 if (deasserted)
2792 bnx2x_attn_int_deasserted(bp, deasserted);
2793}
2794
2795static void bnx2x_sp_task(struct work_struct *work)
2796{
2797 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task);
2798 u16 status;
2799
2800
2801 /* Return here if interrupt is disabled */
2802 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2803 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
2804 return;
2805 }
2806
2807 status = bnx2x_update_dsb_idx(bp);
2808/* if (status == 0) */
2809/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
2810
2811 DP(BNX2X_MSG_SP, "got a slowpath interrupt (updated %x)\n", status);
2812
2813 /* HW attentions */
2814 if (status & 0x1)
2815 bnx2x_attn_int(bp);
2816
2817 /* CStorm events: query_stats, port delete ramrod */
2818 if (status & 0x2)
2819 bp->stats_pending = 0;
2820
2821 bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, bp->def_att_idx,
2822 IGU_INT_NOP, 1);
2823 bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
2824 IGU_INT_NOP, 1);
2825 bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
2826 IGU_INT_NOP, 1);
2827 bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
2828 IGU_INT_NOP, 1);
2829 bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
2830 IGU_INT_ENABLE, 1);
2831
2832}
2833
2834static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2835{
2836 struct net_device *dev = dev_instance;
2837 struct bnx2x *bp = netdev_priv(dev);
2838
2839 /* Return here if interrupt is disabled */
2840 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2841 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
2842 return IRQ_HANDLED;
2843 }
2844
2845 bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, 0, IGU_INT_DISABLE, 0);
2846
2847#ifdef BNX2X_STOP_ON_ERROR
2848 if (unlikely(bp->panic))
2849 return IRQ_HANDLED;
2850#endif
2851
2852 schedule_work(&bp->sp_task);
2853
2854 return IRQ_HANDLED;
2855}
2856
2857/* end of slow path */
2858
2859/* Statistics */
2860
2861/****************************************************************************
2862* Macros
2863****************************************************************************/
2864
2865/* sum[hi:lo] += add[hi:lo] */
2866#define ADD_64(s_hi, a_hi, s_lo, a_lo) \
2867 do { \
2868 s_lo += a_lo; \
2869 s_hi += a_hi + (s_lo < a_lo) ? 1 : 0; \
2870 } while (0)
2871
2872/* difference = minuend - subtrahend */
2873#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
2874 do { \
2875 if (m_lo < s_lo) { \
2876 /* underflow */ \
2877 d_hi = m_hi - s_hi; \
2878 if (d_hi > 0) { \
2879 /* we can 'loan' 1 */ \
2880 d_hi--; \
2881 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2882 } else { \
2883 /* m_hi <= s_hi */ \
2884 d_hi = 0; \
2885 d_lo = 0; \
2886 } \
2887 } else { \
2888 /* m_lo >= s_lo */ \
2889 if (m_hi < s_hi) { \
2890 d_hi = 0; \
2891 d_lo = 0; \
2892 } else { \
2893 /* m_hi >= s_hi */ \
2894 d_hi = m_hi - s_hi; \
2895 d_lo = m_lo - s_lo; \
2896 } \
2897 } \
2898 } while (0)
2899
2900#define UPDATE_STAT64(s, t) \
2901 do { \
2902 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
2903 diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
2904 pstats->mac_stx[0].t##_hi = new->s##_hi; \
2905 pstats->mac_stx[0].t##_lo = new->s##_lo; \
2906 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
2907 pstats->mac_stx[1].t##_lo, diff.lo); \
2908 } while (0)
2909
2910#define UPDATE_STAT64_NIG(s, t) \
2911 do { \
2912 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
2913 diff.lo, new->s##_lo, old->s##_lo); \
2914 ADD_64(estats->t##_hi, diff.hi, \
2915 estats->t##_lo, diff.lo); \
2916 } while (0)
2917
2918/* sum[hi:lo] += add */
2919#define ADD_EXTEND_64(s_hi, s_lo, a) \
2920 do { \
2921 s_lo += a; \
2922 s_hi += (s_lo < a) ? 1 : 0; \
2923 } while (0)
2924
2925#define UPDATE_EXTEND_STAT(s) \
2926 do { \
2927 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
2928 pstats->mac_stx[1].s##_lo, \
2929 new->s); \
2930 } while (0)
2931
2932#define UPDATE_EXTEND_TSTAT(s, t) \
2933 do { \
2934 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
2935 old_tclient->s = le32_to_cpu(tclient->s); \
2936 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
2937 } while (0)
2938
2939#define UPDATE_EXTEND_XSTAT(s, t) \
2940 do { \
2941 diff = le32_to_cpu(xclient->s) - old_xclient->s; \
2942 old_xclient->s = le32_to_cpu(xclient->s); \
2943 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
2944 } while (0)
2945
2946/*
2947 * General service functions
2948 */
2949
2950static inline long bnx2x_hilo(u32 *hiref)
2951{
2952 u32 lo = *(hiref + 1);
2953#if (BITS_PER_LONG == 64)
2954 u32 hi = *hiref;
2955
2956 return HILO_U64(hi, lo);
2957#else
2958 return lo;
2959#endif
2960}
2961
2962/*
2963 * Init service functions
2964 */
2965
2966static void bnx2x_storm_stats_init(struct bnx2x *bp)
2967{
2968 int func = BP_FUNC(bp);
2969
2970 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func), 1);
2971 REG_WR(bp, BAR_XSTRORM_INTMEM +
2972 XSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2973
2974 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func), 1);
2975 REG_WR(bp, BAR_TSTRORM_INTMEM +
2976 TSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2977
2978 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func), 0);
2979 REG_WR(bp, BAR_CSTRORM_INTMEM +
2980 CSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2981
2982 REG_WR(bp, BAR_XSTRORM_INTMEM +
2983 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
2984 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
2985 REG_WR(bp, BAR_XSTRORM_INTMEM +
2986 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
2987 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
2988
2989 REG_WR(bp, BAR_TSTRORM_INTMEM +
2990 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
2991 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
2992 REG_WR(bp, BAR_TSTRORM_INTMEM +
2993 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
2994 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
2995}
2996
2997static void bnx2x_storm_stats_post(struct bnx2x *bp)
2998{
2999 if (!bp->stats_pending) {
3000 struct eth_query_ramrod_data ramrod_data = {0};
3001 int rc;
3002
3003 ramrod_data.drv_counter = bp->stats_counter++;
3004 ramrod_data.collect_port_1b = bp->port.pmf ? 1 : 0;
3005 ramrod_data.ctr_id_vector = (1 << BP_CL_ID(bp));
3006
3007 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
3008 ((u32 *)&ramrod_data)[1],
3009 ((u32 *)&ramrod_data)[0], 0);
3010 if (rc == 0) {
3011 /* stats ramrod has it's own slot on the spq */
3012 bp->spq_left++;
3013 bp->stats_pending = 1;
3014 }
3015 }
3016}
3017
3018static void bnx2x_stats_init(struct bnx2x *bp)
3019{
3020 int port = BP_PORT(bp);
3021
3022 bp->executer_idx = 0;
3023 bp->stats_counter = 0;
3024
3025 /* port stats */
3026 if (!BP_NOMCP(bp))
3027 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
3028 else
3029 bp->port.port_stx = 0;
3030 DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx);
3031
3032 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
3033 bp->port.old_nig_stats.brb_discard =
3034 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3035 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
3036 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
3037 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
3038 &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
3039
3040 /* function stats */
3041 memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
3042 memset(&bp->old_tclient, 0, sizeof(struct tstorm_per_client_stats));
3043 memset(&bp->old_xclient, 0, sizeof(struct xstorm_per_client_stats));
3044 memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
3045
3046 bp->stats_state = STATS_STATE_DISABLED;
3047 if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx)
3048 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3049}
3050
3051static void bnx2x_hw_stats_post(struct bnx2x *bp)
3052{
3053 struct dmae_command *dmae = &bp->stats_dmae;
3054 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3055
3056 *stats_comp = DMAE_COMP_VAL;
3057
3058 /* loader */
3059 if (bp->executer_idx) {
3060 int loader_idx = PMF_DMAE_C(bp);
3061
3062 memset(dmae, 0, sizeof(struct dmae_command));
3063
3064 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3065 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3066 DMAE_CMD_DST_RESET |
3067#ifdef __BIG_ENDIAN
3068 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3069#else
3070 DMAE_CMD_ENDIANITY_DW_SWAP |
3071#endif
3072 (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
3073 DMAE_CMD_PORT_0) |
3074 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3075 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
3076 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
3077 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
3078 sizeof(struct dmae_command) *
3079 (loader_idx + 1)) >> 2;
3080 dmae->dst_addr_hi = 0;
3081 dmae->len = sizeof(struct dmae_command) >> 2;
3082 if (CHIP_IS_E1(bp))
3083 dmae->len--;
3084 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
3085 dmae->comp_addr_hi = 0;
3086 dmae->comp_val = 1;
3087
3088 *stats_comp = 0;
3089 bnx2x_post_dmae(bp, dmae, loader_idx);
3090
3091 } else if (bp->func_stx) {
3092 *stats_comp = 0;
3093 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
3094 }
3095}
3096
3097static int bnx2x_stats_comp(struct bnx2x *bp)
3098{
3099 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3100 int cnt = 10;
3101
3102 might_sleep();
3103 while (*stats_comp != DMAE_COMP_VAL) {
3104 msleep(1);
3105 if (!cnt) {
3106 BNX2X_ERR("timeout waiting for stats finished\n");
3107 break;
3108 }
3109 cnt--;
3110 }
3111 return 1;
3112}
3113
3114/*
3115 * Statistics service functions
3116 */
3117
3118static void bnx2x_stats_pmf_update(struct bnx2x *bp)
3119{
3120 struct dmae_command *dmae;
3121 u32 opcode;
3122 int loader_idx = PMF_DMAE_C(bp);
3123 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3124
3125 /* sanity */
3126 if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
3127 BNX2X_ERR("BUG!\n");
3128 return;
3129 }
3130
3131 bp->executer_idx = 0;
3132
3133 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3134 DMAE_CMD_C_ENABLE |
3135 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3136#ifdef __BIG_ENDIAN
3137 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3138#else
3139 DMAE_CMD_ENDIANITY_DW_SWAP |
3140#endif
3141 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3142 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3143
3144 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3145 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3146 dmae->src_addr_lo = bp->port.port_stx >> 2;
3147 dmae->src_addr_hi = 0;
3148 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3149 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3150 dmae->len = DMAE_LEN32_RD_MAX;
3151 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3152 dmae->comp_addr_hi = 0;
3153 dmae->comp_val = 1;
3154
3155 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3156 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3157 dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
3158 dmae->src_addr_hi = 0;
3159 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
3160 DMAE_LEN32_RD_MAX * 4);
3161 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
3162 DMAE_LEN32_RD_MAX * 4);
3163 dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
3164 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3165 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3166 dmae->comp_val = DMAE_COMP_VAL;
3167
3168 *stats_comp = 0;
3169 bnx2x_hw_stats_post(bp);
3170 bnx2x_stats_comp(bp);
3171}
3172
3173static void bnx2x_port_stats_init(struct bnx2x *bp)
3174{
3175 struct dmae_command *dmae;
3176 int port = BP_PORT(bp);
3177 int vn = BP_E1HVN(bp);
3178 u32 opcode;
3179 int loader_idx = PMF_DMAE_C(bp);
3180 u32 mac_addr;
3181 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3182
3183 /* sanity */
3184 if (!bp->link_vars.link_up || !bp->port.pmf) {
3185 BNX2X_ERR("BUG!\n");
3186 return;
3187 }
3188
3189 bp->executer_idx = 0;
3190
3191 /* MCP */
3192 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3193 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3194 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3195#ifdef __BIG_ENDIAN
3196 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3197#else
3198 DMAE_CMD_ENDIANITY_DW_SWAP |
3199#endif
3200 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3201 (vn << DMAE_CMD_E1HVN_SHIFT));
3202
3203 if (bp->port.port_stx) {
3204
3205 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3206 dmae->opcode = opcode;
3207 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3208 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3209 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3210 dmae->dst_addr_hi = 0;
3211 dmae->len = sizeof(struct host_port_stats) >> 2;
3212 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3213 dmae->comp_addr_hi = 0;
3214 dmae->comp_val = 1;
3215 }
3216
3217 if (bp->func_stx) {
3218
3219 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3220 dmae->opcode = opcode;
3221 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3222 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3223 dmae->dst_addr_lo = bp->func_stx >> 2;
3224 dmae->dst_addr_hi = 0;
3225 dmae->len = sizeof(struct host_func_stats) >> 2;
3226 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3227 dmae->comp_addr_hi = 0;
3228 dmae->comp_val = 1;
3229 }
3230
3231 /* MAC */
3232 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3233 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3234 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3235#ifdef __BIG_ENDIAN
3236 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3237#else
3238 DMAE_CMD_ENDIANITY_DW_SWAP |
3239#endif
3240 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3241 (vn << DMAE_CMD_E1HVN_SHIFT));
3242
3243 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
3244
3245 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
3246 NIG_REG_INGRESS_BMAC0_MEM);
3247
3248 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3249 BIGMAC_REGISTER_TX_STAT_GTBYT */
3250 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3251 dmae->opcode = opcode;
3252 dmae->src_addr_lo = (mac_addr +
3253 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3254 dmae->src_addr_hi = 0;
3255 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3256 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3257 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
3258 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3259 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3260 dmae->comp_addr_hi = 0;
3261 dmae->comp_val = 1;
3262
3263 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
3264 BIGMAC_REGISTER_RX_STAT_GRIPJ */
3265 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3266 dmae->opcode = opcode;
3267 dmae->src_addr_lo = (mac_addr +
3268 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3269 dmae->src_addr_hi = 0;
3270 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3271 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3272 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3273 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3274 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
3275 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3276 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3277 dmae->comp_addr_hi = 0;
3278 dmae->comp_val = 1;
3279
3280 } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
3281
3282 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
3283
3284 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
3285 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3286 dmae->opcode = opcode;
3287 dmae->src_addr_lo = (mac_addr +
3288 EMAC_REG_EMAC_RX_STAT_AC) >> 2;
3289 dmae->src_addr_hi = 0;
3290 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3291 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3292 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
3293 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3294 dmae->comp_addr_hi = 0;
3295 dmae->comp_val = 1;
3296
3297 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
3298 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3299 dmae->opcode = opcode;
3300 dmae->src_addr_lo = (mac_addr +
3301 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
3302 dmae->src_addr_hi = 0;
3303 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3304 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3305 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3306 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3307 dmae->len = 1;
3308 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3309 dmae->comp_addr_hi = 0;
3310 dmae->comp_val = 1;
3311
3312 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
3313 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3314 dmae->opcode = opcode;
3315 dmae->src_addr_lo = (mac_addr +
3316 EMAC_REG_EMAC_TX_STAT_AC) >> 2;
3317 dmae->src_addr_hi = 0;
3318 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3319 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3320 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3321 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3322 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
3323 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3324 dmae->comp_addr_hi = 0;
3325 dmae->comp_val = 1;
3326 }
3327
3328 /* NIG */
3329 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3330 dmae->opcode = opcode;
3331 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
3332 NIG_REG_STAT0_BRB_DISCARD) >> 2;
3333 dmae->src_addr_hi = 0;
3334 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
3335 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
3336 dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
3337 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3338 dmae->comp_addr_hi = 0;
3339 dmae->comp_val = 1;
3340
3341 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3342 dmae->opcode = opcode;
3343 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
3344 NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
3345 dmae->src_addr_hi = 0;
3346 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3347 offsetof(struct nig_stats, egress_mac_pkt0_lo));
3348 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3349 offsetof(struct nig_stats, egress_mac_pkt0_lo));
3350 dmae->len = (2*sizeof(u32)) >> 2;
3351 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3352 dmae->comp_addr_hi = 0;
3353 dmae->comp_val = 1;
3354
3355 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3356 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3357 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3358 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3359#ifdef __BIG_ENDIAN
3360 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3361#else
3362 DMAE_CMD_ENDIANITY_DW_SWAP |
3363#endif
3364 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3365 (vn << DMAE_CMD_E1HVN_SHIFT));
3366 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
3367 NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
3368 dmae->src_addr_hi = 0;
3369 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3370 offsetof(struct nig_stats, egress_mac_pkt1_lo));
3371 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3372 offsetof(struct nig_stats, egress_mac_pkt1_lo));
3373 dmae->len = (2*sizeof(u32)) >> 2;
3374 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3375 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3376 dmae->comp_val = DMAE_COMP_VAL;
3377
3378 *stats_comp = 0;
3379}
3380
3381static void bnx2x_func_stats_init(struct bnx2x *bp)
3382{
3383 struct dmae_command *dmae = &bp->stats_dmae;
3384 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3385
3386 /* sanity */
3387 if (!bp->func_stx) {
3388 BNX2X_ERR("BUG!\n");
3389 return;
3390 }
3391
3392 bp->executer_idx = 0;
3393 memset(dmae, 0, sizeof(struct dmae_command));
3394
3395 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3396 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3397 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3398#ifdef __BIG_ENDIAN
3399 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3400#else
3401 DMAE_CMD_ENDIANITY_DW_SWAP |
3402#endif
3403 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3404 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3405 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3406 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3407 dmae->dst_addr_lo = bp->func_stx >> 2;
3408 dmae->dst_addr_hi = 0;
3409 dmae->len = sizeof(struct host_func_stats) >> 2;
3410 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3411 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3412 dmae->comp_val = DMAE_COMP_VAL;
3413
3414 *stats_comp = 0;
3415}
3416
3417static void bnx2x_stats_start(struct bnx2x *bp)
3418{
3419 if (bp->port.pmf)
3420 bnx2x_port_stats_init(bp);
3421
3422 else if (bp->func_stx)
3423 bnx2x_func_stats_init(bp);
3424
3425 bnx2x_hw_stats_post(bp);
3426 bnx2x_storm_stats_post(bp);
3427}
3428
3429static void bnx2x_stats_pmf_start(struct bnx2x *bp)
3430{
3431 bnx2x_stats_comp(bp);
3432 bnx2x_stats_pmf_update(bp);
3433 bnx2x_stats_start(bp);
3434}
3435
3436static void bnx2x_stats_restart(struct bnx2x *bp)
3437{
3438 bnx2x_stats_comp(bp);
3439 bnx2x_stats_start(bp);
3440}
3441
3442static void bnx2x_bmac_stats_update(struct bnx2x *bp)
3443{
3444 struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
3445 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3446 struct regpair diff;
3447
3448 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
3449 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
3450 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
3451 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
3452 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
3453 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
3454 UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf);
3455 UPDATE_STAT64(rx_stat_grxcf, rx_stat_bmac_xcf);
3456 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
3457 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived);
3458 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
3459 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
3460 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
3461 UPDATE_STAT64(tx_stat_gt127,
3462 tx_stat_etherstatspkts65octetsto127octets);
3463 UPDATE_STAT64(tx_stat_gt255,
3464 tx_stat_etherstatspkts128octetsto255octets);
3465 UPDATE_STAT64(tx_stat_gt511,
3466 tx_stat_etherstatspkts256octetsto511octets);
3467 UPDATE_STAT64(tx_stat_gt1023,
3468 tx_stat_etherstatspkts512octetsto1023octets);
3469 UPDATE_STAT64(tx_stat_gt1518,
3470 tx_stat_etherstatspkts1024octetsto1522octets);
3471 UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
3472 UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
3473 UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
3474 UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
3475 UPDATE_STAT64(tx_stat_gterr,
3476 tx_stat_dot3statsinternalmactransmiterrors);
3477 UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
3478}
3479
3480static void bnx2x_emac_stats_update(struct bnx2x *bp)
3481{
3482 struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
3483 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3484
3485 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
3486 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
3487 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
3488 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
3489 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
3490 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
3491 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
3492 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
3493 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
3494 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
3495 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
3496 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
3497 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
3498 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
3499 UPDATE_EXTEND_STAT(tx_stat_outxonsent);
3500 UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
3501 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
3502 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
3503 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
3504 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
3505 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
3506 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
3507 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
3508 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
3509 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
3510 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
3511 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
3512 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
3513 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
3514 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
3515 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
3516}
3517
3518static int bnx2x_hw_stats_update(struct bnx2x *bp)
3519{
3520 struct nig_stats *new = bnx2x_sp(bp, nig_stats);
3521 struct nig_stats *old = &(bp->port.old_nig_stats);
3522 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3523 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3524 struct regpair diff;
3525
3526 if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
3527 bnx2x_bmac_stats_update(bp);
3528
3529 else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
3530 bnx2x_emac_stats_update(bp);
3531
3532 else { /* unreached */
3533 BNX2X_ERR("stats updated by dmae but no MAC active\n");
3534 return -1;
3535 }
3536
3537 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
3538 new->brb_discard - old->brb_discard);
3539
3540 UPDATE_STAT64_NIG(egress_mac_pkt0,
3541 etherstatspkts1024octetsto1522octets);
3542 UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
3543
3544 memcpy(old, new, sizeof(struct nig_stats));
3545
3546 memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
3547 sizeof(struct mac_stx));
3548 estats->brb_drop_hi = pstats->brb_drop_hi;
3549 estats->brb_drop_lo = pstats->brb_drop_lo;
3550
3551 pstats->host_port_stats_start = ++pstats->host_port_stats_end;
3552
3553 return 0;
3554}
3555
3556static int bnx2x_storm_stats_update(struct bnx2x *bp)
3557{
3558 struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
3559 int cl_id = BP_CL_ID(bp);
3560 struct tstorm_per_port_stats *tport =
3561 &stats->tstorm_common.port_statistics;
3562 struct tstorm_per_client_stats *tclient =
3563 &stats->tstorm_common.client_statistics[cl_id];
3564 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3565 struct xstorm_per_client_stats *xclient =
3566 &stats->xstorm_common.client_statistics[cl_id];
3567 struct xstorm_per_client_stats *old_xclient = &bp->old_xclient;
3568 struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
3569 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3570 u32 diff;
3571
3572 /* are storm stats valid? */
3573 if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
3574 bp->stats_counter) {
3575 DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
3576 " tstorm counter (%d) != stats_counter (%d)\n",
3577 tclient->stats_counter, bp->stats_counter);
3578 return -1;
3579 }
3580 if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
3581 bp->stats_counter) {
3582 DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
3583 " xstorm counter (%d) != stats_counter (%d)\n",
3584 xclient->stats_counter, bp->stats_counter);
3585 return -2;
3586 }
3587
3588 fstats->total_bytes_received_hi =
3589 fstats->valid_bytes_received_hi =
3590 le32_to_cpu(tclient->total_rcv_bytes.hi);
3591 fstats->total_bytes_received_lo =
3592 fstats->valid_bytes_received_lo =
3593 le32_to_cpu(tclient->total_rcv_bytes.lo);
3594
3595 estats->error_bytes_received_hi =
3596 le32_to_cpu(tclient->rcv_error_bytes.hi);
3597 estats->error_bytes_received_lo =
3598 le32_to_cpu(tclient->rcv_error_bytes.lo);
3599 ADD_64(estats->error_bytes_received_hi,
3600 estats->rx_stat_ifhcinbadoctets_hi,
3601 estats->error_bytes_received_lo,
3602 estats->rx_stat_ifhcinbadoctets_lo);
3603
3604 ADD_64(fstats->total_bytes_received_hi,
3605 estats->error_bytes_received_hi,
3606 fstats->total_bytes_received_lo,
3607 estats->error_bytes_received_lo);
3608
3609 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts, total_unicast_packets_received);
3610 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
3611 total_multicast_packets_received);
3612 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
3613 total_broadcast_packets_received);
3614
3615 fstats->total_bytes_transmitted_hi =
3616 le32_to_cpu(xclient->total_sent_bytes.hi);
3617 fstats->total_bytes_transmitted_lo =
3618 le32_to_cpu(xclient->total_sent_bytes.lo);
3619
3620 UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
3621 total_unicast_packets_transmitted);
3622 UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
3623 total_multicast_packets_transmitted);
3624 UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
3625 total_broadcast_packets_transmitted);
3626
3627 memcpy(estats, &(fstats->total_bytes_received_hi),
3628 sizeof(struct host_func_stats) - 2*sizeof(u32));
3629
3630 estats->mac_filter_discard = le32_to_cpu(tport->mac_filter_discard);
3631 estats->xxoverflow_discard = le32_to_cpu(tport->xxoverflow_discard);
3632 estats->brb_truncate_discard =
3633 le32_to_cpu(tport->brb_truncate_discard);
3634 estats->mac_discard = le32_to_cpu(tport->mac_discard);
3635
3636 old_tclient->rcv_unicast_bytes.hi =
3637 le32_to_cpu(tclient->rcv_unicast_bytes.hi);
3638 old_tclient->rcv_unicast_bytes.lo =
3639 le32_to_cpu(tclient->rcv_unicast_bytes.lo);
3640 old_tclient->rcv_broadcast_bytes.hi =
3641 le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
3642 old_tclient->rcv_broadcast_bytes.lo =
3643 le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
3644 old_tclient->rcv_multicast_bytes.hi =
3645 le32_to_cpu(tclient->rcv_multicast_bytes.hi);
3646 old_tclient->rcv_multicast_bytes.lo =
3647 le32_to_cpu(tclient->rcv_multicast_bytes.lo);
3648 old_tclient->total_rcv_pkts = le32_to_cpu(tclient->total_rcv_pkts);
3649
3650 old_tclient->checksum_discard = le32_to_cpu(tclient->checksum_discard);
3651 old_tclient->packets_too_big_discard =
3652 le32_to_cpu(tclient->packets_too_big_discard);
3653 estats->no_buff_discard =
3654 old_tclient->no_buff_discard = le32_to_cpu(tclient->no_buff_discard);
3655 old_tclient->ttl0_discard = le32_to_cpu(tclient->ttl0_discard);
3656
3657 old_xclient->total_sent_pkts = le32_to_cpu(xclient->total_sent_pkts);
3658 old_xclient->unicast_bytes_sent.hi =
3659 le32_to_cpu(xclient->unicast_bytes_sent.hi);
3660 old_xclient->unicast_bytes_sent.lo =
3661 le32_to_cpu(xclient->unicast_bytes_sent.lo);
3662 old_xclient->multicast_bytes_sent.hi =
3663 le32_to_cpu(xclient->multicast_bytes_sent.hi);
3664 old_xclient->multicast_bytes_sent.lo =
3665 le32_to_cpu(xclient->multicast_bytes_sent.lo);
3666 old_xclient->broadcast_bytes_sent.hi =
3667 le32_to_cpu(xclient->broadcast_bytes_sent.hi);
3668 old_xclient->broadcast_bytes_sent.lo =
3669 le32_to_cpu(xclient->broadcast_bytes_sent.lo);
3670
3671 fstats->host_func_stats_start = ++fstats->host_func_stats_end;
3672
3673 return 0;
3674}
3675
3676static void bnx2x_net_stats_update(struct bnx2x *bp)
3677{
3678 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3679 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3680 struct net_device_stats *nstats = &bp->dev->stats;
3681
3682 nstats->rx_packets =
3683 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
3684 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
3685 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
3686
3687 nstats->tx_packets =
3688 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
3689 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
3690 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
3691
3692 nstats->rx_bytes = bnx2x_hilo(&estats->valid_bytes_received_hi);
3693
3694 nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
3695
3696 nstats->rx_dropped = old_tclient->checksum_discard +
3697 estats->mac_discard;
3698 nstats->tx_dropped = 0;
3699
3700 nstats->multicast =
3701 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi);
3702
3703 nstats->collisions =
3704 estats->tx_stat_dot3statssinglecollisionframes_lo +
3705 estats->tx_stat_dot3statsmultiplecollisionframes_lo +
3706 estats->tx_stat_dot3statslatecollisions_lo +
3707 estats->tx_stat_dot3statsexcessivecollisions_lo;
3708
3709 estats->jabber_packets_received =
3710 old_tclient->packets_too_big_discard +
3711 estats->rx_stat_dot3statsframestoolong_lo;
3712
3713 nstats->rx_length_errors =
3714 estats->rx_stat_etherstatsundersizepkts_lo +
3715 estats->jabber_packets_received;
3716 nstats->rx_over_errors = estats->brb_drop_lo +
3717 estats->brb_truncate_discard;
3718 nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo;
3719 nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo;
3720 nstats->rx_fifo_errors = old_tclient->no_buff_discard;
3721 nstats->rx_missed_errors = estats->xxoverflow_discard;
3722
3723 nstats->rx_errors = nstats->rx_length_errors +
3724 nstats->rx_over_errors +
3725 nstats->rx_crc_errors +
3726 nstats->rx_frame_errors +
3727 nstats->rx_fifo_errors +
3728 nstats->rx_missed_errors;
3729
3730 nstats->tx_aborted_errors =
3731 estats->tx_stat_dot3statslatecollisions_lo +
3732 estats->tx_stat_dot3statsexcessivecollisions_lo;
3733 nstats->tx_carrier_errors = estats->rx_stat_falsecarriererrors_lo;
3734 nstats->tx_fifo_errors = 0;
3735 nstats->tx_heartbeat_errors = 0;
3736 nstats->tx_window_errors = 0;
3737
3738 nstats->tx_errors = nstats->tx_aborted_errors +
3739 nstats->tx_carrier_errors;
3740}
3741
3742static void bnx2x_stats_update(struct bnx2x *bp)
3743{
3744 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3745 int update = 0;
3746
3747 if (*stats_comp != DMAE_COMP_VAL)
3748 return;
3749
3750 if (bp->port.pmf)
3751 update = (bnx2x_hw_stats_update(bp) == 0);
3752
3753 update |= (bnx2x_storm_stats_update(bp) == 0);
3754
3755 if (update)
3756 bnx2x_net_stats_update(bp);
3757
3758 else {
3759 if (bp->stats_pending) {
3760 bp->stats_pending++;
3761 if (bp->stats_pending == 3) {
3762 BNX2X_ERR("stats not updated for 3 times\n");
3763 bnx2x_panic();
3764 return;
3765 }
3766 }
3767 }
3768
3769 if (bp->msglevel & NETIF_MSG_TIMER) {
3770 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3771 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3772 struct net_device_stats *nstats = &bp->dev->stats;
3773 int i;
3774
3775 printk(KERN_DEBUG "%s:\n", bp->dev->name);
3776 printk(KERN_DEBUG " tx avail (%4x) tx hc idx (%x)"
3777 " tx pkt (%lx)\n",
3778 bnx2x_tx_avail(bp->fp),
3779 le16_to_cpu(*bp->fp->tx_cons_sb), nstats->tx_packets);
3780 printk(KERN_DEBUG " rx usage (%4x) rx hc idx (%x)"
3781 " rx pkt (%lx)\n",
3782 (u16)(le16_to_cpu(*bp->fp->rx_cons_sb) -
3783 bp->fp->rx_comp_cons),
3784 le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
3785 printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u\n",
3786 netif_queue_stopped(bp->dev)? "Xoff" : "Xon",
3787 estats->driver_xoff, estats->brb_drop_lo);
3788 printk(KERN_DEBUG "tstats: checksum_discard %u "
3789 "packets_too_big_discard %u no_buff_discard %u "
3790 "mac_discard %u mac_filter_discard %u "
3791 "xxovrflow_discard %u brb_truncate_discard %u "
3792 "ttl0_discard %u\n",
3793 old_tclient->checksum_discard,
3794 old_tclient->packets_too_big_discard,
3795 old_tclient->no_buff_discard, estats->mac_discard,
3796 estats->mac_filter_discard, estats->xxoverflow_discard,
3797 estats->brb_truncate_discard,
3798 old_tclient->ttl0_discard);
3799
3800 for_each_queue(bp, i) {
3801 printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
3802 bnx2x_fp(bp, i, tx_pkt),
3803 bnx2x_fp(bp, i, rx_pkt),
3804 bnx2x_fp(bp, i, rx_calls));
3805 }
3806 }
3807
3808 bnx2x_hw_stats_post(bp);
3809 bnx2x_storm_stats_post(bp);
3810}
3811
3812static void bnx2x_port_stats_stop(struct bnx2x *bp)
3813{
3814 struct dmae_command *dmae;
3815 u32 opcode;
3816 int loader_idx = PMF_DMAE_C(bp);
3817 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3818
3819 bp->executer_idx = 0;
3820
3821 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3822 DMAE_CMD_C_ENABLE |
3823 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3824#ifdef __BIG_ENDIAN
3825 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3826#else
3827 DMAE_CMD_ENDIANITY_DW_SWAP |
3828#endif
3829 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3830 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3831
3832 if (bp->port.port_stx) {
3833
3834 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3835 if (bp->func_stx)
3836 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3837 else
3838 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3839 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3840 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3841 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3842 dmae->dst_addr_hi = 0;
3843 dmae->len = sizeof(struct host_port_stats) >> 2;
3844 if (bp->func_stx) {
3845 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3846 dmae->comp_addr_hi = 0;
3847 dmae->comp_val = 1;
3848 } else {
3849 dmae->comp_addr_lo =
3850 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3851 dmae->comp_addr_hi =
3852 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3853 dmae->comp_val = DMAE_COMP_VAL;
3854
3855 *stats_comp = 0;
3856 }
3857 }
3858
3859 if (bp->func_stx) {
3860
3861 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3862 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3863 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3864 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3865 dmae->dst_addr_lo = bp->func_stx >> 2;
3866 dmae->dst_addr_hi = 0;
3867 dmae->len = sizeof(struct host_func_stats) >> 2;
3868 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3869 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3870 dmae->comp_val = DMAE_COMP_VAL;
3871
3872 *stats_comp = 0;
3873 }
3874}
3875
3876static void bnx2x_stats_stop(struct bnx2x *bp)
3877{
3878 int update = 0;
3879
3880 bnx2x_stats_comp(bp);
3881
3882 if (bp->port.pmf)
3883 update = (bnx2x_hw_stats_update(bp) == 0);
3884
3885 update |= (bnx2x_storm_stats_update(bp) == 0);
3886
3887 if (update) {
3888 bnx2x_net_stats_update(bp);
3889
3890 if (bp->port.pmf)
3891 bnx2x_port_stats_stop(bp);
3892
3893 bnx2x_hw_stats_post(bp);
3894 bnx2x_stats_comp(bp);
3895 }
3896}
3897
3898static void bnx2x_stats_do_nothing(struct bnx2x *bp)
3899{
3900}
3901
3902static const struct {
3903 void (*action)(struct bnx2x *bp);
3904 enum bnx2x_stats_state next_state;
3905} bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
3906/* state event */
3907{
3908/* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
3909/* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
3910/* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
3911/* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
3912},
3913{
3914/* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
3915/* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
3916/* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
3917/* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
3918}
3919};
3920
3921static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
3922{
3923 enum bnx2x_stats_state state = bp->stats_state;
3924
3925 bnx2x_stats_stm[state][event].action(bp);
3926 bp->stats_state = bnx2x_stats_stm[state][event].next_state;
3927
3928 if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
3929 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
3930 state, event, bp->stats_state);
3931}
3932
3933static void bnx2x_timer(unsigned long data)
3934{
3935 struct bnx2x *bp = (struct bnx2x *) data;
3936
3937 if (!netif_running(bp->dev))
3938 return;
3939
3940 if (atomic_read(&bp->intr_sem) != 0)
3941 goto timer_restart;
3942
3943 if (poll) {
3944 struct bnx2x_fastpath *fp = &bp->fp[0];
3945 int rc;
3946
3947 bnx2x_tx_int(fp, 1000);
3948 rc = bnx2x_rx_int(fp, 1000);
3949 }
3950
3951 if (!BP_NOMCP(bp)) {
3952 int func = BP_FUNC(bp);
3953 u32 drv_pulse;
3954 u32 mcp_pulse;
3955
3956 ++bp->fw_drv_pulse_wr_seq;
3957 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3958 /* TBD - add SYSTEM_TIME */
3959 drv_pulse = bp->fw_drv_pulse_wr_seq;
3960 SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
3961
3962 mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
3963 MCP_PULSE_SEQ_MASK);
3964 /* The delta between driver pulse and mcp response
3965 * should be 1 (before mcp response) or 0 (after mcp response)
3966 */
3967 if ((drv_pulse != mcp_pulse) &&
3968 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3969 /* someone lost a heartbeat... */
3970 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3971 drv_pulse, mcp_pulse);
3972 }
3973 }
3974
3975 if ((bp->state == BNX2X_STATE_OPEN) ||
3976 (bp->state == BNX2X_STATE_DISABLED))
3977 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
3978
3979timer_restart:
3980 mod_timer(&bp->timer, jiffies + bp->current_interval);
3981}
3982
3983/* end of Statistics */
3984
3985/* nic init */
3986
3987/*
3988 * nic init service functions
3989 */
3990
3991static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
3992{
3993 int port = BP_PORT(bp);
3994
3995 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
3996 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
3997 sizeof(struct ustorm_def_status_block)/4);
3998 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
3999 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4000 sizeof(struct cstorm_def_status_block)/4);
4001}
4002
4003static void bnx2x_init_sb(struct bnx2x *bp, int sb_id,
4004 struct host_status_block *sb, dma_addr_t mapping)
4005{
4006 int port = BP_PORT(bp);
4007 int func = BP_FUNC(bp);
4008 int index;
4009 u64 section;
4010
4011 /* USTORM */
4012 section = ((u64)mapping) + offsetof(struct host_status_block,
4013 u_status_block);
4014 sb->u_status_block.status_block_id = sb_id;
4015
4016 REG_WR(bp, BAR_USTRORM_INTMEM +
4017 USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4018 REG_WR(bp, BAR_USTRORM_INTMEM +
4019 ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4020 U64_HI(section));
4021 REG_WR8(bp, BAR_USTRORM_INTMEM + FP_USB_FUNC_OFF +
4022 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4023
4024 for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
4025 REG_WR16(bp, BAR_USTRORM_INTMEM +
4026 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4027
4028 /* CSTORM */
4029 section = ((u64)mapping) + offsetof(struct host_status_block,
4030 c_status_block);
4031 sb->c_status_block.status_block_id = sb_id;
4032
4033 REG_WR(bp, BAR_CSTRORM_INTMEM +
4034 CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4035 REG_WR(bp, BAR_CSTRORM_INTMEM +
4036 ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4037 U64_HI(section));
4038 REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
4039 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4040
4041 for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
4042 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4043 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4044
4045 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4046}
4047
4048static void bnx2x_zero_def_sb(struct bnx2x *bp)
4049{
4050 int func = BP_FUNC(bp);
4051
4052 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4053 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4054 sizeof(struct ustorm_def_status_block)/4);
4055 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4056 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4057 sizeof(struct cstorm_def_status_block)/4);
4058 bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM +
4059 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4060 sizeof(struct xstorm_def_status_block)/4);
4061 bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
4062 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4063 sizeof(struct tstorm_def_status_block)/4);
4064}
4065
4066static void bnx2x_init_def_sb(struct bnx2x *bp,
4067 struct host_def_status_block *def_sb,
4068 dma_addr_t mapping, int sb_id)
4069{
4070 int port = BP_PORT(bp);
4071 int func = BP_FUNC(bp);
4072 int index, val, reg_offset;
4073 u64 section;
4074
4075 /* ATTN */
4076 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4077 atten_status_block);
4078 def_sb->atten_status_block.status_block_id = sb_id;
4079
4080 bp->def_att_idx = 0;
4081 bp->attn_state = 0;
4082
4083 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4084 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4085
4086 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4087 bp->attn_group[index].sig[0] = REG_RD(bp,
4088 reg_offset + 0x10*index);
4089 bp->attn_group[index].sig[1] = REG_RD(bp,
4090 reg_offset + 0x4 + 0x10*index);
4091 bp->attn_group[index].sig[2] = REG_RD(bp,
4092 reg_offset + 0x8 + 0x10*index);
4093 bp->attn_group[index].sig[3] = REG_RD(bp,
4094 reg_offset + 0xc + 0x10*index);
4095 }
4096
4097 bp->aeu_mask = REG_RD(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4098 MISC_REG_AEU_MASK_ATTN_FUNC_0));
4099
4100 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4101 HC_REG_ATTN_MSG0_ADDR_L);
4102
4103 REG_WR(bp, reg_offset, U64_LO(section));
4104 REG_WR(bp, reg_offset + 4, U64_HI(section));
4105
4106 reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
4107
4108 val = REG_RD(bp, reg_offset);
4109 val |= sb_id;
4110 REG_WR(bp, reg_offset, val);
4111
4112 /* USTORM */
4113 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4114 u_def_status_block);
4115 def_sb->u_def_status_block.status_block_id = sb_id;
4116
4117 bp->def_u_idx = 0;
4118
4119 REG_WR(bp, BAR_USTRORM_INTMEM +
4120 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4121 REG_WR(bp, BAR_USTRORM_INTMEM +
4122 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4123 U64_HI(section));
4124 REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4125 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4126 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(func),
4127 BNX2X_BTR);
4128
4129 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4130 REG_WR16(bp, BAR_USTRORM_INTMEM +
4131 USTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4132
4133 /* CSTORM */
4134 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4135 c_def_status_block);
4136 def_sb->c_def_status_block.status_block_id = sb_id;
4137
4138 bp->def_c_idx = 0;
4139
4140 REG_WR(bp, BAR_CSTRORM_INTMEM +
4141 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4142 REG_WR(bp, BAR_CSTRORM_INTMEM +
4143 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4144 U64_HI(section));
4145 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4146 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4147 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(func),
4148 BNX2X_BTR);
4149
4150 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4151 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4152 CSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4153
4154 /* TSTORM */
4155 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4156 t_def_status_block);
4157 def_sb->t_def_status_block.status_block_id = sb_id;
4158
4159 bp->def_t_idx = 0;
4160
4161 REG_WR(bp, BAR_TSTRORM_INTMEM +
4162 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4163 REG_WR(bp, BAR_TSTRORM_INTMEM +
4164 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4165 U64_HI(section));
4166 REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4167 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4168 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(func),
4169 BNX2X_BTR);
4170
4171 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4172 REG_WR16(bp, BAR_TSTRORM_INTMEM +
4173 TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4174
4175 /* XSTORM */
4176 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4177 x_def_status_block);
4178 def_sb->x_def_status_block.status_block_id = sb_id;
4179
4180 bp->def_x_idx = 0;
4181
4182 REG_WR(bp, BAR_XSTRORM_INTMEM +
4183 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4184 REG_WR(bp, BAR_XSTRORM_INTMEM +
4185 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4186 U64_HI(section));
4187 REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4188 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4189 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(func),
4190 BNX2X_BTR);
4191
4192 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4193 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4194 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4195
4196 bp->stats_pending = 0;
4197
4198 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4199}
4200
4201static void bnx2x_update_coalesce(struct bnx2x *bp)
4202{
4203 int port = BP_PORT(bp);
4204 int i;
4205
4206 for_each_queue(bp, i) {
4207 int sb_id = bp->fp[i].sb_id;
4208
4209 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4210 REG_WR8(bp, BAR_USTRORM_INTMEM +
4211 USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4212 HC_INDEX_U_ETH_RX_CQ_CONS),
4213 bp->rx_ticks/12);
4214 REG_WR16(bp, BAR_USTRORM_INTMEM +
4215 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4216 HC_INDEX_U_ETH_RX_CQ_CONS),
4217 bp->rx_ticks ? 0 : 1);
4218
4219 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4220 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4221 CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4222 HC_INDEX_C_ETH_TX_CQ_CONS),
4223 bp->tx_ticks/12);
4224 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4225 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4226 HC_INDEX_C_ETH_TX_CQ_CONS),
4227 bp->tx_ticks ? 0 : 1);
4228 }
4229}
4230
4231static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
4232 struct bnx2x_fastpath *fp, int last)
4233{
4234 int i;
4235
4236 for (i = 0; i < last; i++) {
4237 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
4238 struct sk_buff *skb = rx_buf->skb;
4239
4240 if (skb == NULL) {
4241 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
4242 continue;
4243 }
4244
4245 if (fp->tpa_state[i] == BNX2X_TPA_START)
4246 pci_unmap_single(bp->pdev,
4247 pci_unmap_addr(rx_buf, mapping),
4248 bp->rx_buf_use_size,
4249 PCI_DMA_FROMDEVICE);
4250
4251 dev_kfree_skb(skb);
4252 rx_buf->skb = NULL;
4253 }
4254}
4255
4256static void bnx2x_init_rx_rings(struct bnx2x *bp)
4257{
4258 int func = BP_FUNC(bp);
4259 u16 ring_prod, cqe_ring_prod = 0;
4260 int i, j;
4261
4262 bp->rx_buf_use_size = bp->dev->mtu;
4263 bp->rx_buf_use_size += bp->rx_offset + ETH_OVREHEAD;
4264 bp->rx_buf_size = bp->rx_buf_use_size + 64;
4265
4266 if (bp->flags & TPA_ENABLE_FLAG) {
4267 DP(NETIF_MSG_IFUP,
4268 "rx_buf_use_size %d rx_buf_size %d effective_mtu %d\n",
4269 bp->rx_buf_use_size, bp->rx_buf_size,
4270 bp->dev->mtu + ETH_OVREHEAD);
4271
4272 for_each_queue(bp, j) {
4273 for (i = 0; i < ETH_MAX_AGGREGATION_QUEUES_E1H; i++) {
4274 struct bnx2x_fastpath *fp = &bp->fp[j];
4275
4276 fp->tpa_pool[i].skb =
4277 netdev_alloc_skb(bp->dev, bp->rx_buf_size);
4278 if (!fp->tpa_pool[i].skb) {
4279 BNX2X_ERR("Failed to allocate TPA "
4280 "skb pool for queue[%d] - "
4281 "disabling TPA on this "
4282 "queue!\n", j);
4283 bnx2x_free_tpa_pool(bp, fp, i);
4284 fp->disable_tpa = 1;
4285 break;
4286 }
4287 pci_unmap_addr_set((struct sw_rx_bd *)
4288 &bp->fp->tpa_pool[i],
4289 mapping, 0);
4290 fp->tpa_state[i] = BNX2X_TPA_STOP;
4291 }
4292 }
4293 }
4294
4295 for_each_queue(bp, j) {
4296 struct bnx2x_fastpath *fp = &bp->fp[j];
4297
4298 fp->rx_bd_cons = 0;
4299 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4300 fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
4301
4302 /* "next page" elements initialization */
4303 /* SGE ring */
4304 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
4305 struct eth_rx_sge *sge;
4306
4307 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
4308 sge->addr_hi =
4309 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
4310 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4311 sge->addr_lo =
4312 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
4313 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4314 }
4315
4316 bnx2x_init_sge_ring_bit_mask(fp);
4317
4318 /* RX BD ring */
4319 for (i = 1; i <= NUM_RX_RINGS; i++) {
4320 struct eth_rx_bd *rx_bd;
4321
4322 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
4323 rx_bd->addr_hi =
4324 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
4325 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4326 rx_bd->addr_lo =
4327 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
4328 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4329 }
4330
4331 /* CQ ring */
4332 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4333 struct eth_rx_cqe_next_page *nextpg;
4334
4335 nextpg = (struct eth_rx_cqe_next_page *)
4336 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4337 nextpg->addr_hi =
4338 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4339 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4340 nextpg->addr_lo =
4341 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4342 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4343 }
4344
4345 /* Allocate SGEs and initialize the ring elements */
4346 for (i = 0, ring_prod = 0;
4347 i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
4348
4349 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
4350 BNX2X_ERR("was only able to allocate "
4351 "%d rx sges\n", i);
4352 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
4353 /* Cleanup already allocated elements */
4354 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
4355 bnx2x_free_tpa_pool(bp, fp,
4356 ETH_MAX_AGGREGATION_QUEUES_E1H);
4357 fp->disable_tpa = 1;
4358 ring_prod = 0;
4359 break;
4360 }
4361 ring_prod = NEXT_SGE_IDX(ring_prod);
4362 }
4363 fp->rx_sge_prod = ring_prod;
4364
4365 /* Allocate BDs and initialize BD ring */
4366 fp->rx_comp_cons = fp->rx_alloc_failed = 0;
4367 cqe_ring_prod = ring_prod = 0;
4368 for (i = 0; i < bp->rx_ring_size; i++) {
4369 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4370 BNX2X_ERR("was only able to allocate "
4371 "%d rx skbs\n", i);
4372 fp->rx_alloc_failed++;
4373 break;
4374 }
4375 ring_prod = NEXT_RX_IDX(ring_prod);
4376 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4377 BUG_TRAP(ring_prod > i);
4378 }
4379
4380 fp->rx_bd_prod = ring_prod;
4381 /* must not have more available CQEs than BDs */
4382 fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
4383 cqe_ring_prod);
4384 fp->rx_pkt = fp->rx_calls = 0;
4385
4386 /* Warning!
4387 * this will generate an interrupt (to the TSTORM)
4388 * must only be done after chip is initialized
4389 */
4390 bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
4391 fp->rx_sge_prod);
4392 if (j != 0)
4393 continue;
4394
4395 REG_WR(bp, BAR_USTRORM_INTMEM +
4396 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
4397 U64_LO(fp->rx_comp_mapping));
4398 REG_WR(bp, BAR_USTRORM_INTMEM +
4399 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
4400 U64_HI(fp->rx_comp_mapping));
4401 }
4402}
4403
4404static void bnx2x_init_tx_ring(struct bnx2x *bp)
4405{
4406 int i, j;
4407
4408 for_each_queue(bp, j) {
4409 struct bnx2x_fastpath *fp = &bp->fp[j];
4410
4411 for (i = 1; i <= NUM_TX_RINGS; i++) {
4412 struct eth_tx_bd *tx_bd =
4413 &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
4414
4415 tx_bd->addr_hi =
4416 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
4417 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4418 tx_bd->addr_lo =
4419 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
4420 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4421 }
4422
4423 fp->tx_pkt_prod = 0;
4424 fp->tx_pkt_cons = 0;
4425 fp->tx_bd_prod = 0;
4426 fp->tx_bd_cons = 0;
4427 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4428 fp->tx_pkt = 0;
4429 }
4430}
4431
4432static void bnx2x_init_sp_ring(struct bnx2x *bp)
4433{
4434 int func = BP_FUNC(bp);
4435
4436 spin_lock_init(&bp->spq_lock);
4437
4438 bp->spq_left = MAX_SPQ_PENDING;
4439 bp->spq_prod_idx = 0;
4440 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4441 bp->spq_prod_bd = bp->spq;
4442 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4443
4444 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
4445 U64_LO(bp->spq_mapping));
4446 REG_WR(bp,
4447 XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
4448 U64_HI(bp->spq_mapping));
4449
4450 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
4451 bp->spq_prod_idx);
4452}
4453
4454static void bnx2x_init_context(struct bnx2x *bp)
4455{
4456 int i;
4457
4458 for_each_queue(bp, i) {
4459 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
4460 struct bnx2x_fastpath *fp = &bp->fp[i];
4461 u8 sb_id = FP_SB_ID(fp);
4462
4463 context->xstorm_st_context.tx_bd_page_base_hi =
4464 U64_HI(fp->tx_desc_mapping);
4465 context->xstorm_st_context.tx_bd_page_base_lo =
4466 U64_LO(fp->tx_desc_mapping);
4467 context->xstorm_st_context.db_data_addr_hi =
4468 U64_HI(fp->tx_prods_mapping);
4469 context->xstorm_st_context.db_data_addr_lo =
4470 U64_LO(fp->tx_prods_mapping);
4471 context->xstorm_st_context.statistics_data = (BP_CL_ID(bp) |
4472 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
4473
4474 context->ustorm_st_context.common.sb_index_numbers =
4475 BNX2X_RX_SB_INDEX_NUM;
4476 context->ustorm_st_context.common.clientId = FP_CL_ID(fp);
4477 context->ustorm_st_context.common.status_block_id = sb_id;
4478 context->ustorm_st_context.common.flags =
4479 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT;
4480 context->ustorm_st_context.common.mc_alignment_size = 64;
4481 context->ustorm_st_context.common.bd_buff_size =
4482 bp->rx_buf_use_size;
4483 context->ustorm_st_context.common.bd_page_base_hi =
4484 U64_HI(fp->rx_desc_mapping);
4485 context->ustorm_st_context.common.bd_page_base_lo =
4486 U64_LO(fp->rx_desc_mapping);
4487 if (!fp->disable_tpa) {
4488 context->ustorm_st_context.common.flags |=
4489 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
4490 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
4491 context->ustorm_st_context.common.sge_buff_size =
4492 (u16)(BCM_PAGE_SIZE*PAGES_PER_SGE);
4493 context->ustorm_st_context.common.sge_page_base_hi =
4494 U64_HI(fp->rx_sge_mapping);
4495 context->ustorm_st_context.common.sge_page_base_lo =
4496 U64_LO(fp->rx_sge_mapping);
4497 }
4498
4499 context->cstorm_st_context.sb_index_number =
4500 HC_INDEX_C_ETH_TX_CQ_CONS;
4501 context->cstorm_st_context.status_block_id = sb_id;
4502
4503 context->xstorm_ag_context.cdu_reserved =
4504 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4505 CDU_REGION_NUMBER_XCM_AG,
4506 ETH_CONNECTION_TYPE);
4507 context->ustorm_ag_context.cdu_usage =
4508 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4509 CDU_REGION_NUMBER_UCM_AG,
4510 ETH_CONNECTION_TYPE);
4511 }
4512}
4513
4514static void bnx2x_init_ind_table(struct bnx2x *bp)
4515{
4516 int port = BP_PORT(bp);
4517 int i;
4518
4519 if (!is_multi(bp))
4520 return;
4521
4522 DP(NETIF_MSG_IFUP, "Initializing indirection table\n");
4523 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4524 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4525 TSTORM_INDIRECTION_TABLE_OFFSET(port) + i,
4526 i % bp->num_queues);
4527
4528 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
4529}
4530
4531static void bnx2x_set_client_config(struct bnx2x *bp)
4532{
4533 struct tstorm_eth_client_config tstorm_client = {0};
4534 int port = BP_PORT(bp);
4535 int i;
4536
4537 tstorm_client.mtu = bp->dev->mtu + ETH_OVREHEAD;
4538 tstorm_client.statistics_counter_id = 0;
4539 tstorm_client.config_flags =
4540 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
4541#ifdef BCM_VLAN
4542 if (bp->rx_mode && bp->vlgrp) {
4543 tstorm_client.config_flags |=
4544 TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE;
4545 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
4546 }
4547#endif
4548
4549 if (bp->flags & TPA_ENABLE_FLAG) {
4550 tstorm_client.max_sges_for_packet =
4551 BCM_PAGE_ALIGN(tstorm_client.mtu) >> BCM_PAGE_SHIFT;
4552 tstorm_client.max_sges_for_packet =
4553 ((tstorm_client.max_sges_for_packet +
4554 PAGES_PER_SGE - 1) & (~(PAGES_PER_SGE - 1))) >>
4555 PAGES_PER_SGE_SHIFT;
4556
4557 tstorm_client.config_flags |=
4558 TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING;
4559 }
4560
4561 for_each_queue(bp, i) {
4562 REG_WR(bp, BAR_TSTRORM_INTMEM +
4563 TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
4564 ((u32 *)&tstorm_client)[0]);
4565 REG_WR(bp, BAR_TSTRORM_INTMEM +
4566 TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
4567 ((u32 *)&tstorm_client)[1]);
4568 }
4569
4570 DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
4571 ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
4572}
4573
4574static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4575{
4576 struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
4577 int mode = bp->rx_mode;
4578 int mask = (1 << BP_L_ID(bp));
4579 int func = BP_FUNC(bp);
4580 int i;
4581
4582 DP(NETIF_MSG_RX_STATUS, "rx mode is %d\n", mode);
4583
4584 switch (mode) {
4585 case BNX2X_RX_MODE_NONE: /* no Rx */
4586 tstorm_mac_filter.ucast_drop_all = mask;
4587 tstorm_mac_filter.mcast_drop_all = mask;
4588 tstorm_mac_filter.bcast_drop_all = mask;
4589 break;
4590 case BNX2X_RX_MODE_NORMAL:
4591 tstorm_mac_filter.bcast_accept_all = mask;
4592 break;
4593 case BNX2X_RX_MODE_ALLMULTI:
4594 tstorm_mac_filter.mcast_accept_all = mask;
4595 tstorm_mac_filter.bcast_accept_all = mask;
4596 break;
4597 case BNX2X_RX_MODE_PROMISC:
4598 tstorm_mac_filter.ucast_accept_all = mask;
4599 tstorm_mac_filter.mcast_accept_all = mask;
4600 tstorm_mac_filter.bcast_accept_all = mask;
4601 break;
4602 default:
4603 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4604 break;
4605 }
4606
4607 for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
4608 REG_WR(bp, BAR_TSTRORM_INTMEM +
4609 TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
4610 ((u32 *)&tstorm_mac_filter)[i]);
4611
4612/* DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
4613 ((u32 *)&tstorm_mac_filter)[i]); */
4614 }
4615
4616 if (mode != BNX2X_RX_MODE_NONE)
4617 bnx2x_set_client_config(bp);
4618}
4619
4620static void bnx2x_init_internal(struct bnx2x *bp)
4621{
4622 struct tstorm_eth_function_common_config tstorm_config = {0};
4623 struct stats_indication_flags stats_flags = {0};
4624 int port = BP_PORT(bp);
4625 int func = BP_FUNC(bp);
4626 int i;
4627
4628 if (is_multi(bp)) {
4629 tstorm_config.config_flags = MULTI_FLAGS;
4630 tstorm_config.rss_result_mask = MULTI_MASK;
4631 }
4632
4633 tstorm_config.leading_client_id = BP_L_ID(bp);
4634
4635 REG_WR(bp, BAR_TSTRORM_INTMEM +
4636 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4637 (*(u32 *)&tstorm_config));
4638
4639/* DP(NETIF_MSG_IFUP, "tstorm_config: 0x%08x\n",
4640 (*(u32 *)&tstorm_config)); */
4641
4642 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4643 bnx2x_set_storm_rx_mode(bp);
4644
4645 stats_flags.collect_eth = 1;
4646
4647 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port),
4648 ((u32 *)&stats_flags)[0]);
4649 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port) + 4,
4650 ((u32 *)&stats_flags)[1]);
4651
4652 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port),
4653 ((u32 *)&stats_flags)[0]);
4654 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port) + 4,
4655 ((u32 *)&stats_flags)[1]);
4656
4657 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port),
4658 ((u32 *)&stats_flags)[0]);
4659 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port) + 4,
4660 ((u32 *)&stats_flags)[1]);
4661
4662/* DP(NETIF_MSG_IFUP, "stats_flags: 0x%08x 0x%08x\n",
4663 ((u32 *)&stats_flags)[0], ((u32 *)&stats_flags)[1]); */
4664
4665 if (CHIP_IS_E1H(bp)) {
4666 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4667 IS_E1HMF(bp));
4668 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4669 IS_E1HMF(bp));
4670 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4671 IS_E1HMF(bp));
4672 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4673 IS_E1HMF(bp));
4674
4675 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
4676 bp->e1hov);
4677 }
4678
4679 /* Zero this manualy as its initialization is
4680 currently missing in the initTool */
4681 for (i = 0; i < USTORM_AGG_DATA_SIZE >> 2; i++)
4682 REG_WR(bp, BAR_USTRORM_INTMEM +
4683 USTORM_AGG_DATA_OFFSET + 4*i, 0);
4684
4685 for_each_queue(bp, i) {
4686 struct bnx2x_fastpath *fp = &bp->fp[i];
4687 u16 max_agg_size;
4688
4689 REG_WR(bp, BAR_USTRORM_INTMEM +
4690 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
4691 U64_LO(fp->rx_comp_mapping));
4692 REG_WR(bp, BAR_USTRORM_INTMEM +
4693 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
4694 U64_HI(fp->rx_comp_mapping));
4695
4696 max_agg_size = min((u32)(bp->rx_buf_use_size +
4697 8*BCM_PAGE_SIZE*PAGES_PER_SGE),
4698 (u32)0xffff);
4699 REG_WR16(bp, BAR_USTRORM_INTMEM +
4700 USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
4701 max_agg_size);
4702 }
4703}
4704
4705static void bnx2x_nic_init(struct bnx2x *bp)
4706{
4707 int i;
4708
4709 for_each_queue(bp, i) {
4710 struct bnx2x_fastpath *fp = &bp->fp[i];
4711
4712 fp->bp = bp;
4713 fp->state = BNX2X_FP_STATE_CLOSED;
4714 fp->index = i;
4715 fp->cl_id = BP_L_ID(bp) + i;
4716 fp->sb_id = fp->cl_id;
4717 DP(NETIF_MSG_IFUP,
4718 "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n",
4719 bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
4720 bnx2x_init_sb(bp, FP_SB_ID(fp), fp->status_blk,
4721 fp->status_blk_mapping);
4722 }
4723
4724 bnx2x_init_def_sb(bp, bp->def_status_blk,
4725 bp->def_status_blk_mapping, DEF_SB_ID);
4726 bnx2x_update_coalesce(bp);
4727 bnx2x_init_rx_rings(bp);
4728 bnx2x_init_tx_ring(bp);
4729 bnx2x_init_sp_ring(bp);
4730 bnx2x_init_context(bp);
4731 bnx2x_init_internal(bp);
4732 bnx2x_storm_stats_init(bp);
4733 bnx2x_init_ind_table(bp);
4734 bnx2x_int_enable(bp);
4735}
4736
4737/* end of nic init */
4738
4739/*
4740 * gzip service functions
4741 */
4742
4743static int bnx2x_gunzip_init(struct bnx2x *bp)
4744{
4745 bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
4746 &bp->gunzip_mapping);
4747 if (bp->gunzip_buf == NULL)
4748 goto gunzip_nomem1;
4749
4750 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4751 if (bp->strm == NULL)
4752 goto gunzip_nomem2;
4753
4754 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4755 GFP_KERNEL);
4756 if (bp->strm->workspace == NULL)
4757 goto gunzip_nomem3;
4758
4759 return 0;
4760
4761gunzip_nomem3:
4762 kfree(bp->strm);
4763 bp->strm = NULL;
4764
4765gunzip_nomem2:
4766 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4767 bp->gunzip_mapping);
4768 bp->gunzip_buf = NULL;
4769
4770gunzip_nomem1:
4771 printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
4772 " un-compression\n", bp->dev->name);
4773 return -ENOMEM;
4774}
4775
4776static void bnx2x_gunzip_end(struct bnx2x *bp)
4777{
4778 kfree(bp->strm->workspace);
4779
4780 kfree(bp->strm);
4781 bp->strm = NULL;
4782
4783 if (bp->gunzip_buf) {
4784 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4785 bp->gunzip_mapping);
4786 bp->gunzip_buf = NULL;
4787 }
4788}
4789
4790static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
4791{
4792 int n, rc;
4793
4794 /* check gzip header */
4795 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
4796 return -EINVAL;
4797
4798 n = 10;
4799
4800#define FNAME 0x8
4801
4802 if (zbuf[3] & FNAME)
4803 while ((zbuf[n++] != 0) && (n < len));
4804
4805 bp->strm->next_in = zbuf + n;
4806 bp->strm->avail_in = len - n;
4807 bp->strm->next_out = bp->gunzip_buf;
4808 bp->strm->avail_out = FW_BUF_SIZE;
4809
4810 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4811 if (rc != Z_OK)
4812 return rc;
4813
4814 rc = zlib_inflate(bp->strm, Z_FINISH);
4815 if ((rc != Z_OK) && (rc != Z_STREAM_END))
4816 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
4817 bp->dev->name, bp->strm->msg);
4818
4819 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4820 if (bp->gunzip_outlen & 0x3)
4821 printk(KERN_ERR PFX "%s: Firmware decompression error:"
4822 " gunzip_outlen (%d) not aligned\n",
4823 bp->dev->name, bp->gunzip_outlen);
4824 bp->gunzip_outlen >>= 2;
4825
4826 zlib_inflateEnd(bp->strm);
4827
4828 if (rc == Z_STREAM_END)
4829 return 0;
4830
4831 return rc;
4832}
4833
4834/* nic load/unload */
4835
4836/*
4837 * General service functions
4838 */
4839
4840/* send a NIG loopback debug packet */
4841static void bnx2x_lb_pckt(struct bnx2x *bp)
4842{
4843 u32 wb_write[3];
4844
4845 /* Ethernet source and destination addresses */
4846 wb_write[0] = 0x55555555;
4847 wb_write[1] = 0x55555555;
4848 wb_write[2] = 0x20; /* SOP */
4849 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4850
4851 /* NON-IP protocol */
4852 wb_write[0] = 0x09000000;
4853 wb_write[1] = 0x55555555;
4854 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
4855 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4856}
4857
4858/* some of the internal memories
4859 * are not directly readable from the driver
4860 * to test them we send debug packets
4861 */
4862static int bnx2x_int_mem_test(struct bnx2x *bp)
4863{
4864 int factor;
4865 int count, i;
4866 u32 val = 0;
4867
4868 if (CHIP_REV_IS_FPGA(bp))
4869 factor = 120;
4870 else if (CHIP_REV_IS_EMUL(bp))
4871 factor = 200;
4872 else
4873 factor = 1;
4874
4875 DP(NETIF_MSG_HW, "start part1\n");
4876
4877 /* Disable inputs of parser neighbor blocks */
4878 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4879 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4880 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4881 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
4882
4883 /* Write 0 to parser credits for CFC search request */
4884 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4885
4886 /* send Ethernet packet */
4887 bnx2x_lb_pckt(bp);
4888
4889 /* TODO do i reset NIG statistic? */
4890 /* Wait until NIG register shows 1 packet of size 0x10 */
4891 count = 1000 * factor;
4892 while (count) {
4893
4894 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4895 val = *bnx2x_sp(bp, wb_data[0]);
4896 if (val == 0x10)
4897 break;
4898
4899 msleep(10);
4900 count--;
4901 }
4902 if (val != 0x10) {
4903 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4904 return -1;
4905 }
4906
4907 /* Wait until PRS register shows 1 packet */
4908 count = 1000 * factor;
4909 while (count) {
4910 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4911 if (val == 1)
4912 break;
4913
4914 msleep(10);
4915 count--;
4916 }
4917 if (val != 0x1) {
4918 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4919 return -2;
4920 }
4921
4922 /* Reset and init BRB, PRS */
4923 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4924 msleep(50);
4925 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4926 msleep(50);
4927 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
4928 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
4929
4930 DP(NETIF_MSG_HW, "part2\n");
4931
4932 /* Disable inputs of parser neighbor blocks */
4933 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4934 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4935 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4936 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
4937
4938 /* Write 0 to parser credits for CFC search request */
4939 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4940
4941 /* send 10 Ethernet packets */
4942 for (i = 0; i < 10; i++)
4943 bnx2x_lb_pckt(bp);
4944
4945 /* Wait until NIG register shows 10 + 1
4946 packets of size 11*0x10 = 0xb0 */
4947 count = 1000 * factor;
4948 while (count) {
4949
4950 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4951 val = *bnx2x_sp(bp, wb_data[0]);
4952 if (val == 0xb0)
4953 break;
4954
4955 msleep(10);
4956 count--;
4957 }
4958 if (val != 0xb0) {
4959 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4960 return -3;
4961 }
4962
4963 /* Wait until PRS register shows 2 packets */
4964 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4965 if (val != 2)
4966 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4967
4968 /* Write 1 to parser credits for CFC search request */
4969 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4970
4971 /* Wait until PRS register shows 3 packets */
4972 msleep(10 * factor);
4973 /* Wait until NIG register shows 1 packet of size 0x10 */
4974 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4975 if (val != 3)
4976 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4977
4978 /* clear NIG EOP FIFO */
4979 for (i = 0; i < 11; i++)
4980 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4981 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4982 if (val != 1) {
4983 BNX2X_ERR("clear of NIG failed\n");
4984 return -4;
4985 }
4986
4987 /* Reset and init BRB, PRS, NIG */
4988 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4989 msleep(50);
4990 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4991 msleep(50);
4992 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
4993 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
4994#ifndef BCM_ISCSI
4995 /* set NIC mode */
4996 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4997#endif
4998
4999 /* Enable inputs of parser neighbor blocks */
5000 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5001 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5002 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5003 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x1);
5004
5005 DP(NETIF_MSG_HW, "done\n");
5006
5007 return 0; /* OK */
5008}
5009
5010static void enable_blocks_attention(struct bnx2x *bp)
5011{
5012 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5013 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5014 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5015 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5016 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5017 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5018 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5019 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5020 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5021/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5022/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5023 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5024 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5025 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5026/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5027/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5028 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5029 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5030 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5031 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5032/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5033/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5034 if (CHIP_REV_IS_FPGA(bp))
5035 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5036 else
5037 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5038 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5039 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5040 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5041/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5042/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
5043 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5044 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5045/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5046 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18); /* bit 3,4 masked */
5047}
5048
5049
5050static int bnx2x_init_common(struct bnx2x *bp)
5051{
5052 u32 val, i;
5053
5054 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_FUNC(bp));
5055
5056 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5057 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
5058
5059 bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END);
5060 if (CHIP_IS_E1H(bp))
5061 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
5062
5063 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
5064 msleep(30);
5065 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
5066
5067 bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END);
5068 if (CHIP_IS_E1(bp)) {
5069 /* enable HW interrupt from PXP on USDM overflow
5070 bit 16 on INT_MASK_0 */
5071 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5072 }
5073
5074 bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END);
5075 bnx2x_init_pxp(bp);
5076
5077#ifdef __BIG_ENDIAN
5078 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5079 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5080 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5081 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5082 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5083 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 1);
5084
5085/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5086 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5087 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5088 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5089 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5090#endif
5091
5092#ifndef BCM_ISCSI
5093 /* set NIC mode */
5094 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5095#endif
5096
5097 REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5098#ifdef BCM_ISCSI
5099 REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
5100 REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
5101 REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
5102#endif
5103
5104 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5105 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5106
5107 /* let the HW do it's magic ... */
5108 msleep(100);
5109 /* finish PXP init */
5110 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5111 if (val != 1) {
5112 BNX2X_ERR("PXP2 CFG failed\n");
5113 return -EBUSY;
5114 }
5115 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5116 if (val != 1) {
5117 BNX2X_ERR("PXP2 RD_INIT failed\n");
5118 return -EBUSY;
5119 }
5120
5121 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5122 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5123
5124 bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END);
5125
5126 /* clean the DMAE memory */
5127 bp->dmae_ready = 1;
5128 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5129
5130 bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END);
5131 bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END);
5132 bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END);
5133 bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END);
5134
5135 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5136 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5137 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5138 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5139
5140 bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
5141 /* soft reset pulse */
5142 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5143 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5144
5145#ifdef BCM_ISCSI
5146 bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END);
5147#endif
5148
5149 bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END);
5150 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
5151 if (!CHIP_REV_IS_SLOW(bp)) {
5152 /* enable hw interrupt from doorbell Q */
5153 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5154 }
5155
5156 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5157 if (CHIP_REV_IS_SLOW(bp)) {
5158 /* fix for emulation and FPGA for no pause */
5159 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513);
5160 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 513);
5161 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0);
5162 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0);
5163 }
5164
5165 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5166 if (CHIP_IS_E1H(bp))
5167 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
5168
5169 bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END);
5170 bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END);
5171 bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
5172 bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
5173
5174 if (CHIP_IS_E1H(bp)) {
5175 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5176 STORM_INTMEM_SIZE_E1H/2);
5177 bnx2x_init_fill(bp,
5178 TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5179 0, STORM_INTMEM_SIZE_E1H/2);
5180 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5181 STORM_INTMEM_SIZE_E1H/2);
5182 bnx2x_init_fill(bp,
5183 CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5184 0, STORM_INTMEM_SIZE_E1H/2);
5185 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5186 STORM_INTMEM_SIZE_E1H/2);
5187 bnx2x_init_fill(bp,
5188 XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5189 0, STORM_INTMEM_SIZE_E1H/2);
5190 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5191 STORM_INTMEM_SIZE_E1H/2);
5192 bnx2x_init_fill(bp,
5193 USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5194 0, STORM_INTMEM_SIZE_E1H/2);
5195 } else { /* E1 */
5196 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5197 STORM_INTMEM_SIZE_E1);
5198 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5199 STORM_INTMEM_SIZE_E1);
5200 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5201 STORM_INTMEM_SIZE_E1);
5202 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5203 STORM_INTMEM_SIZE_E1);
5204 }
5205
5206 bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
5207 bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
5208 bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END);
5209 bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END);
5210
5211 /* sync semi rtc */
5212 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5213 0x80000000);
5214 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5215 0x80000000);
5216
5217 bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END);
5218 bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END);
5219 bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END);
5220
5221 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5222 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
5223 REG_WR(bp, i, 0xc0cac01a);
5224 /* TODO: replace with something meaningful */
5225 }
5226 if (CHIP_IS_E1H(bp))
5227 bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END);
5228 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5229
5230 if (sizeof(union cdu_context) != 1024)
5231 /* we currently assume that a context is 1024 bytes */
5232 printk(KERN_ALERT PFX "please adjust the size of"
5233 " cdu_context(%ld)\n", (long)sizeof(union cdu_context));
5234
5235 bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END);
5236 val = (4 << 24) + (0 << 12) + 1024;
5237 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5238 if (CHIP_IS_E1(bp)) {
5239 /* !!! fix pxp client crdit until excel update */
5240 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
5241 REG_WR(bp, CDU_REG_CDU_DEBUG, 0);
5242 }
5243
5244 bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
5245 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5246
5247 bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
5248 bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END);
5249
5250 /* PXPCS COMMON comes here */
5251 /* Reset PCIE errors for debug */
5252 REG_WR(bp, 0x2814, 0xffffffff);
5253 REG_WR(bp, 0x3820, 0xffffffff);
5254
5255 /* EMAC0 COMMON comes here */
5256 /* EMAC1 COMMON comes here */
5257 /* DBU COMMON comes here */
5258 /* DBG COMMON comes here */
5259
5260 bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END);
5261 if (CHIP_IS_E1H(bp)) {
5262 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
5263 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
5264 }
5265
5266 if (CHIP_REV_IS_SLOW(bp))
5267 msleep(200);
5268
5269 /* finish CFC init */
5270 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5271 if (val != 1) {
5272 BNX2X_ERR("CFC LL_INIT failed\n");
5273 return -EBUSY;
5274 }
5275 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5276 if (val != 1) {
5277 BNX2X_ERR("CFC AC_INIT failed\n");
5278 return -EBUSY;
5279 }
5280 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5281 if (val != 1) {
5282 BNX2X_ERR("CFC CAM_INIT failed\n");
5283 return -EBUSY;
5284 }
5285 REG_WR(bp, CFC_REG_DEBUG0, 0);
5286
5287 /* read NIG statistic
5288 to see if this is our first up since powerup */
5289 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5290 val = *bnx2x_sp(bp, wb_data[0]);
5291
5292 /* do internal memory self test */
5293 if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
5294 BNX2X_ERR("internal mem self test failed\n");
5295 return -EBUSY;
5296 }
5297
5298 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5299 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5300 /* Fan failure is indicated by SPIO 5 */
5301 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5302 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5303
5304 /* set to active low mode */
5305 val = REG_RD(bp, MISC_REG_SPIO_INT);
5306 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5307 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5308 REG_WR(bp, MISC_REG_SPIO_INT, val);
5309
5310 /* enable interrupt to signal the IGU */
5311 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5312 val |= (1 << MISC_REGISTERS_SPIO_5);
5313 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5314 break;
5315
5316 default:
5317 break;
5318 }
5319
5320 /* clear PXP2 attentions */
5321 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5322
5323 enable_blocks_attention(bp);
5324
5325 if (bp->flags & TPA_ENABLE_FLAG) {
5326 struct tstorm_eth_tpa_exist tmp = {0};
5327
5328 tmp.tpa_exist = 1;
5329
5330 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET,
5331 ((u32 *)&tmp)[0]);
5332 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4,
5333 ((u32 *)&tmp)[1]);
5334 }
5335
5336 return 0;
5337}
5338
5339static int bnx2x_init_port(struct bnx2x *bp)
5340{
5341 int port = BP_PORT(bp);
5342 u32 val;
5343
5344 DP(BNX2X_MSG_MCP, "starting port init port %x\n", port);
5345
5346 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5347
5348 /* Port PXP comes here */
5349 /* Port PXP2 comes here */
5350#ifdef BCM_ISCSI
5351 /* Port0 1
5352 * Port1 385 */
5353 i++;
5354 wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
5355 wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
5356 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5357 REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
5358
5359 /* Port0 2
5360 * Port1 386 */
5361 i++;
5362 wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
5363 wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
5364 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5365 REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
5366
5367 /* Port0 3
5368 * Port1 387 */
5369 i++;
5370 wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
5371 wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
5372 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5373 REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
5374#endif
5375 /* Port CMs come here */
5376
5377 /* Port QM comes here */
5378#ifdef BCM_ISCSI
5379 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
5380 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
5381
5382 bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START,
5383 func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
5384#endif
5385 /* Port DQ comes here */
5386 /* Port BRB1 comes here */
5387 /* Port PRS comes here */
5388 /* Port TSDM comes here */
5389 /* Port CSDM comes here */
5390 /* Port USDM comes here */
5391 /* Port XSDM comes here */
5392 bnx2x_init_block(bp, port ? TSEM_PORT1_START : TSEM_PORT0_START,
5393 port ? TSEM_PORT1_END : TSEM_PORT0_END);
5394 bnx2x_init_block(bp, port ? USEM_PORT1_START : USEM_PORT0_START,
5395 port ? USEM_PORT1_END : USEM_PORT0_END);
5396 bnx2x_init_block(bp, port ? CSEM_PORT1_START : CSEM_PORT0_START,
5397 port ? CSEM_PORT1_END : CSEM_PORT0_END);
5398 bnx2x_init_block(bp, port ? XSEM_PORT1_START : XSEM_PORT0_START,
5399 port ? XSEM_PORT1_END : XSEM_PORT0_END);
5400 /* Port UPB comes here */
5401 /* Port XPB comes here */
5402
5403 bnx2x_init_block(bp, port ? PBF_PORT1_START : PBF_PORT0_START,
5404 port ? PBF_PORT1_END : PBF_PORT0_END);
5405
5406 /* configure PBF to work without PAUSE mtu 9000 */
5407 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5408
5409 /* update threshold */
5410 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5411 /* update init credit */
5412 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5413
5414 /* probe changes */
5415 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5416 msleep(5);
5417 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5418
5419#ifdef BCM_ISCSI
5420 /* tell the searcher where the T2 table is */
5421 REG_WR(bp, SRC_REG_COUNTFREE0 + func*4, 16*1024/64);
5422
5423 wb_write[0] = U64_LO(bp->t2_mapping);
5424 wb_write[1] = U64_HI(bp->t2_mapping);
5425 REG_WR_DMAE(bp, SRC_REG_FIRSTFREE0 + func*4, wb_write, 2);
5426 wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64);
5427 wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64);
5428 REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2);
5429
5430 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10);
5431 /* Port SRCH comes here */
5432#endif
5433 /* Port CDU comes here */
5434 /* Port CFC comes here */
5435
5436 if (CHIP_IS_E1(bp)) {
5437 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5438 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5439 }
5440 bnx2x_init_block(bp, port ? HC_PORT1_START : HC_PORT0_START,
5441 port ? HC_PORT1_END : HC_PORT0_END);
5442
5443 bnx2x_init_block(bp, port ? MISC_AEU_PORT1_START :
5444 MISC_AEU_PORT0_START,
5445 port ? MISC_AEU_PORT1_END : MISC_AEU_PORT0_END);
5446 /* init aeu_mask_attn_func_0/1:
5447 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5448 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5449 * bits 4-7 are used for "per vn group attention" */
5450 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
5451 (IS_E1HMF(bp) ? 0xF7 : 0x7));
5452
5453 /* Port PXPCS comes here */
5454 /* Port EMAC0 comes here */
5455 /* Port EMAC1 comes here */
5456 /* Port DBU comes here */
5457 /* Port DBG comes here */
5458 bnx2x_init_block(bp, port ? NIG_PORT1_START : NIG_PORT0_START,
5459 port ? NIG_PORT1_END : NIG_PORT0_END);
5460
5461 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5462
5463 if (CHIP_IS_E1H(bp)) {
5464 u32 wsum;
5465 struct cmng_struct_per_port m_cmng_port;
5466 int vn;
5467
5468 /* 0x2 disable e1hov, 0x1 enable */
5469 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5470 (IS_E1HMF(bp) ? 0x1 : 0x2));
5471
5472 /* Init RATE SHAPING and FAIRNESS contexts.
5473 Initialize as if there is 10G link. */
5474 wsum = bnx2x_calc_vn_wsum(bp);
5475 bnx2x_init_port_minmax(bp, (int)wsum, 10000, &m_cmng_port);
5476 if (IS_E1HMF(bp))
5477 for (vn = VN_0; vn < E1HVN_MAX; vn++)
5478 bnx2x_init_vn_minmax(bp, 2*vn + port,
5479 wsum, 10000, &m_cmng_port);
5480 }
5481
5482 /* Port MCP comes here */
5483 /* Port DMAE comes here */
5484
5485 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5486 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5487 /* add SPIO 5 to group 0 */
5488 val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5489 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5490 REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val);
5491 break;
5492
5493 default:
5494 break;
5495 }
5496
5497 bnx2x__link_reset(bp);
5498
5499 return 0;
5500}
5501
5502#define ILT_PER_FUNC (768/2)
5503#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
5504/* the phys address is shifted right 12 bits and has an added
5505 1=valid bit added to the 53rd bit
5506 then since this is a wide register(TM)
5507 we split it into two 32 bit writes
5508 */
5509#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
5510#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
5511#define PXP_ONE_ILT(x) (((x) << 10) | x)
5512#define PXP_ILT_RANGE(f, l) (((l) << 10) | f)
5513
5514#define CNIC_ILT_LINES 0
5515
5516static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5517{
5518 int reg;
5519
5520 if (CHIP_IS_E1H(bp))
5521 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5522 else /* E1 */
5523 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5524
5525 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5526}
5527
5528static int bnx2x_init_func(struct bnx2x *bp)
5529{
5530 int port = BP_PORT(bp);
5531 int func = BP_FUNC(bp);
5532 int i;
5533
5534 DP(BNX2X_MSG_MCP, "starting func init func %x\n", func);
5535
5536 i = FUNC_ILT_BASE(func);
5537
5538 bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
5539 if (CHIP_IS_E1H(bp)) {
5540 REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i);
5541 REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
5542 } else /* E1 */
5543 REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4,
5544 PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
5545
5546
5547 if (CHIP_IS_E1H(bp)) {
5548 for (i = 0; i < 9; i++)
5549 bnx2x_init_block(bp,
5550 cm_start[func][i], cm_end[func][i]);
5551
5552 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5553 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
5554 }
5555
5556 /* HC init per function */
5557 if (CHIP_IS_E1H(bp)) {
5558 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5559
5560 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5561 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5562 }
5563 bnx2x_init_block(bp, hc_limits[func][0], hc_limits[func][1]);
5564
5565 if (CHIP_IS_E1H(bp))
5566 REG_WR(bp, HC_REG_FUNC_NUM_P0 + port*4, func);
5567
5568 /* Reset PCIE errors for debug */
5569 REG_WR(bp, 0x2114, 0xffffffff);
5570 REG_WR(bp, 0x2120, 0xffffffff);
5571
5572 return 0;
5573}
5574
5575static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5576{
5577 int i, rc = 0;
5578
5579 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
5580 BP_FUNC(bp), load_code);
5581
5582 bp->dmae_ready = 0;
5583 mutex_init(&bp->dmae_mutex);
5584 bnx2x_gunzip_init(bp);
5585
5586 switch (load_code) {
5587 case FW_MSG_CODE_DRV_LOAD_COMMON:
5588 rc = bnx2x_init_common(bp);
5589 if (rc)
5590 goto init_hw_err;
5591 /* no break */
5592
5593 case FW_MSG_CODE_DRV_LOAD_PORT:
5594 bp->dmae_ready = 1;
5595 rc = bnx2x_init_port(bp);
5596 if (rc)
5597 goto init_hw_err;
5598 /* no break */
5599
5600 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5601 bp->dmae_ready = 1;
5602 rc = bnx2x_init_func(bp);
5603 if (rc)
5604 goto init_hw_err;
5605 break;
5606
5607 default:
5608 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5609 break;
5610 }
5611
5612 if (!BP_NOMCP(bp)) {
5613 int func = BP_FUNC(bp);
5614
5615 bp->fw_drv_pulse_wr_seq =
5616 (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
5617 DRV_PULSE_SEQ_MASK);
5618 bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
5619 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x func_stx 0x%x\n",
5620 bp->fw_drv_pulse_wr_seq, bp->func_stx);
5621 } else
5622 bp->func_stx = 0;
5623
5624 /* this needs to be done before gunzip end */
5625 bnx2x_zero_def_sb(bp);
5626 for_each_queue(bp, i)
5627 bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
5628
5629init_hw_err:
5630 bnx2x_gunzip_end(bp);
5631
5632 return rc;
5633}
5634
5635/* send the MCP a request, block until there is a reply */
5636static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
5637{
5638 int func = BP_FUNC(bp);
5639 u32 seq = ++bp->fw_seq;
5640 u32 rc = 0;
5641
5642 SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
5643 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
5644
5645 /* let the FW do it's magic ... */
5646 msleep(100); /* TBD */
5647
5648 if (CHIP_REV_IS_SLOW(bp))
5649 msleep(900);
5650
5651 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
5652 DP(BNX2X_MSG_MCP, "read (%x) seq is (%x) from FW MB\n", rc, seq);
5653
5654 /* is this a reply to our command? */
5655 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
5656 rc &= FW_MSG_CODE_MASK;
5657
5658 } else {
5659 /* FW BUG! */
5660 BNX2X_ERR("FW failed to respond!\n");
5661 bnx2x_fw_dump(bp);
5662 rc = 0;
5663 }
5664
5665 return rc;
5666}
5667
5668static void bnx2x_free_mem(struct bnx2x *bp)
5669{
5670
5671#define BNX2X_PCI_FREE(x, y, size) \
5672 do { \
5673 if (x) { \
5674 pci_free_consistent(bp->pdev, size, x, y); \
5675 x = NULL; \
5676 y = 0; \
5677 } \
5678 } while (0)
5679
5680#define BNX2X_FREE(x) \
5681 do { \
5682 if (x) { \
5683 vfree(x); \
5684 x = NULL; \
5685 } \
5686 } while (0)
5687
5688 int i;
5689
5690 /* fastpath */
5691 for_each_queue(bp, i) {
5692
5693 /* Status blocks */
5694 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
5695 bnx2x_fp(bp, i, status_blk_mapping),
5696 sizeof(struct host_status_block) +
5697 sizeof(struct eth_tx_db_data));
5698
5699 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
5700 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
5701 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
5702 bnx2x_fp(bp, i, tx_desc_mapping),
5703 sizeof(struct eth_tx_bd) * NUM_TX_BD);
5704
5705 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
5706 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
5707 bnx2x_fp(bp, i, rx_desc_mapping),
5708 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5709
5710 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
5711 bnx2x_fp(bp, i, rx_comp_mapping),
5712 sizeof(struct eth_fast_path_rx_cqe) *
5713 NUM_RCQ_BD);
5714
5715 /* SGE ring */
5716 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5717 bnx2x_fp(bp, i, rx_sge_mapping),
5718 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5719 }
5720 /* end of fastpath */
5721
5722 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
5723 sizeof(struct host_def_status_block));
5724
5725 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
5726 sizeof(struct bnx2x_slowpath));
5727
5728#ifdef BCM_ISCSI
5729 BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024);
5730 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024);
5731 BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024);
5732 BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024);
5733#endif
5734 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
5735
5736#undef BNX2X_PCI_FREE
5737#undef BNX2X_KFREE
5738}
5739
5740static int bnx2x_alloc_mem(struct bnx2x *bp)
5741{
5742
5743#define BNX2X_PCI_ALLOC(x, y, size) \
5744 do { \
5745 x = pci_alloc_consistent(bp->pdev, size, y); \
5746 if (x == NULL) \
5747 goto alloc_mem_err; \
5748 memset(x, 0, size); \
5749 } while (0)
5750
5751#define BNX2X_ALLOC(x, size) \
5752 do { \
5753 x = vmalloc(size); \
5754 if (x == NULL) \
5755 goto alloc_mem_err; \
5756 memset(x, 0, size); \
5757 } while (0)
5758
5759 int i;
5760
5761 /* fastpath */
5762 for_each_queue(bp, i) {
5763 bnx2x_fp(bp, i, bp) = bp;
5764
5765 /* Status blocks */
5766 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
5767 &bnx2x_fp(bp, i, status_blk_mapping),
5768 sizeof(struct host_status_block) +
5769 sizeof(struct eth_tx_db_data));
5770
5771 bnx2x_fp(bp, i, hw_tx_prods) =
5772 (void *)(bnx2x_fp(bp, i, status_blk) + 1);
5773
5774 bnx2x_fp(bp, i, tx_prods_mapping) =
5775 bnx2x_fp(bp, i, status_blk_mapping) +
5776 sizeof(struct host_status_block);
5777
5778 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
5779 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
5780 sizeof(struct sw_tx_bd) * NUM_TX_BD);
5781 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
5782 &bnx2x_fp(bp, i, tx_desc_mapping),
5783 sizeof(struct eth_tx_bd) * NUM_TX_BD);
5784
5785 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
5786 sizeof(struct sw_rx_bd) * NUM_RX_BD);
5787 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
5788 &bnx2x_fp(bp, i, rx_desc_mapping),
5789 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5790
5791 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
5792 &bnx2x_fp(bp, i, rx_comp_mapping),
5793 sizeof(struct eth_fast_path_rx_cqe) *
5794 NUM_RCQ_BD);
5795
5796 /* SGE ring */
5797 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
5798 sizeof(struct sw_rx_page) * NUM_RX_SGE);
5799 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
5800 &bnx2x_fp(bp, i, rx_sge_mapping),
5801 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5802 }
5803 /* end of fastpath */
5804
5805 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
5806 sizeof(struct host_def_status_block));
5807
5808 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
5809 sizeof(struct bnx2x_slowpath));
5810
5811#ifdef BCM_ISCSI
5812 BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);
5813
5814 /* Initialize T1 */
5815 for (i = 0; i < 64*1024; i += 64) {
5816 *(u64 *)((char *)bp->t1 + i + 56) = 0x0UL;
5817 *(u64 *)((char *)bp->t1 + i + 3) = 0x0UL;
5818 }
5819
5820 /* allocate searcher T2 table
5821 we allocate 1/4 of alloc num for T2
5822 (which is not entered into the ILT) */
5823 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);
5824
5825 /* Initialize T2 */
5826 for (i = 0; i < 16*1024; i += 64)
5827 * (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
5828
5829 /* now fixup the last line in the block to point to the next block */
5830 *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping;
5831
5832 /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */
5833 BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024);
5834
5835 /* QM queues (128*MAX_CONN) */
5836 BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
5837#endif
5838
5839 /* Slow path ring */
5840 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
5841
5842 return 0;
5843
5844alloc_mem_err:
5845 bnx2x_free_mem(bp);
5846 return -ENOMEM;
5847
5848#undef BNX2X_PCI_ALLOC
5849#undef BNX2X_ALLOC
5850}
5851
5852static void bnx2x_free_tx_skbs(struct bnx2x *bp)
5853{
5854 int i;
5855
5856 for_each_queue(bp, i) {
5857 struct bnx2x_fastpath *fp = &bp->fp[i];
5858
5859 u16 bd_cons = fp->tx_bd_cons;
5860 u16 sw_prod = fp->tx_pkt_prod;
5861 u16 sw_cons = fp->tx_pkt_cons;
5862
5863 while (sw_cons != sw_prod) {
5864 bd_cons = bnx2x_free_tx_pkt(bp, fp, TX_BD(sw_cons));
5865 sw_cons++;
5866 }
5867 }
5868}
5869
5870static void bnx2x_free_rx_skbs(struct bnx2x *bp)
5871{
5872 int i, j;
5873
5874 for_each_queue(bp, j) {
5875 struct bnx2x_fastpath *fp = &bp->fp[j];
5876
5877 for (i = 0; i < NUM_RX_BD; i++) {
5878 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
5879 struct sk_buff *skb = rx_buf->skb;
5880
5881 if (skb == NULL)
5882 continue;
5883
5884 pci_unmap_single(bp->pdev,
5885 pci_unmap_addr(rx_buf, mapping),
5886 bp->rx_buf_use_size,
5887 PCI_DMA_FROMDEVICE);
5888
5889 rx_buf->skb = NULL;
5890 dev_kfree_skb(skb);
5891 }
5892 if (!fp->disable_tpa)
5893 bnx2x_free_tpa_pool(bp, fp,
5894 ETH_MAX_AGGREGATION_QUEUES_E1H);
5895 }
5896}
5897
5898static void bnx2x_free_skbs(struct bnx2x *bp)
5899{
5900 bnx2x_free_tx_skbs(bp);
5901 bnx2x_free_rx_skbs(bp);
5902}
5903
5904static void bnx2x_free_msix_irqs(struct bnx2x *bp)
5905{
5906 int i, offset = 1;
5907
5908 free_irq(bp->msix_table[0].vector, bp->dev);
5909 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
5910 bp->msix_table[0].vector);
5911
5912 for_each_queue(bp, i) {
5913 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq "
5914 "state %x\n", i, bp->msix_table[i + offset].vector,
5915 bnx2x_fp(bp, i, state));
5916
5917 if (bnx2x_fp(bp, i, state) != BNX2X_FP_STATE_CLOSED)
5918 BNX2X_ERR("IRQ of fp #%d being freed while "
5919 "state != closed\n", i);
5920
5921 free_irq(bp->msix_table[i + offset].vector, &bp->fp[i]);
5922 }
5923}
5924
5925static void bnx2x_free_irq(struct bnx2x *bp)
5926{
5927 if (bp->flags & USING_MSIX_FLAG) {
5928 bnx2x_free_msix_irqs(bp);
5929 pci_disable_msix(bp->pdev);
5930 bp->flags &= ~USING_MSIX_FLAG;
5931
5932 } else
5933 free_irq(bp->pdev->irq, bp->dev);
5934}
5935
5936static int bnx2x_enable_msix(struct bnx2x *bp)
5937{
5938 int i, rc, offset;
5939
5940 bp->msix_table[0].entry = 0;
5941 offset = 1;
5942 DP(NETIF_MSG_IFUP, "msix_table[0].entry = 0 (slowpath)\n");
5943
5944 for_each_queue(bp, i) {
5945 int igu_vec = offset + i + BP_L_ID(bp);
5946
5947 bp->msix_table[i + offset].entry = igu_vec;
5948 DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d "
5949 "(fastpath #%u)\n", i + offset, igu_vec, i);
5950 }
5951
5952 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0],
5953 bp->num_queues + offset);
5954 if (rc) {
5955 DP(NETIF_MSG_IFUP, "MSI-X is not attainable\n");
5956 return -1;
5957 }
5958 bp->flags |= USING_MSIX_FLAG;
5959
5960 return 0;
5961}
5962
5963static int bnx2x_req_msix_irqs(struct bnx2x *bp)
5964{
5965 int i, rc, offset = 1;
5966
5967 rc = request_irq(bp->msix_table[0].vector, bnx2x_msix_sp_int, 0,
5968 bp->dev->name, bp->dev);
5969 if (rc) {
5970 BNX2X_ERR("request sp irq failed\n");
5971 return -EBUSY;
5972 }
5973
5974 for_each_queue(bp, i) {
5975 rc = request_irq(bp->msix_table[i + offset].vector,
5976 bnx2x_msix_fp_int, 0,
5977 bp->dev->name, &bp->fp[i]);
5978 if (rc) {
5979 BNX2X_ERR("request fp #%d irq failed rc %d\n",
5980 i + offset, rc);
5981 bnx2x_free_msix_irqs(bp);
5982 return -EBUSY;
5983 }
5984
5985 bnx2x_fp(bp, i, state) = BNX2X_FP_STATE_IRQ;
5986 }
5987
5988 return 0;
5989}
5990
5991static int bnx2x_req_irq(struct bnx2x *bp)
5992{
5993 int rc;
5994
5995 rc = request_irq(bp->pdev->irq, bnx2x_interrupt, IRQF_SHARED,
5996 bp->dev->name, bp->dev);
5997 if (!rc)
5998 bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;
5999
6000 return rc;
6001}
6002
6003/*
6004 * Init service functions
6005 */
6006
6007static void bnx2x_set_mac_addr_e1(struct bnx2x *bp)
6008{
6009 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
6010 int port = BP_PORT(bp);
6011
6012 /* CAM allocation
6013 * unicasts 0-31:port0 32-63:port1
6014 * multicast 64-127:port0 128-191:port1
6015 */
6016 config->hdr.length_6b = 2;
6017 config->hdr.offset = port ? 31 : 0;
6018 config->hdr.client_id = BP_CL_ID(bp);
6019 config->hdr.reserved1 = 0;
6020
6021 /* primary MAC */
6022 config->config_table[0].cam_entry.msb_mac_addr =
6023 swab16(*(u16 *)&bp->dev->dev_addr[0]);
6024 config->config_table[0].cam_entry.middle_mac_addr =
6025 swab16(*(u16 *)&bp->dev->dev_addr[2]);
6026 config->config_table[0].cam_entry.lsb_mac_addr =
6027 swab16(*(u16 *)&bp->dev->dev_addr[4]);
6028 config->config_table[0].cam_entry.flags = cpu_to_le16(port);
6029 config->config_table[0].target_table_entry.flags = 0;
6030 config->config_table[0].target_table_entry.client_id = 0;
6031 config->config_table[0].target_table_entry.vlan_id = 0;
6032
6033 DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x)\n",
6034 config->config_table[0].cam_entry.msb_mac_addr,
6035 config->config_table[0].cam_entry.middle_mac_addr,
6036 config->config_table[0].cam_entry.lsb_mac_addr);
6037
6038 /* broadcast */
6039 config->config_table[1].cam_entry.msb_mac_addr = 0xffff;
6040 config->config_table[1].cam_entry.middle_mac_addr = 0xffff;
6041 config->config_table[1].cam_entry.lsb_mac_addr = 0xffff;
6042 config->config_table[1].cam_entry.flags = cpu_to_le16(port);
6043 config->config_table[1].target_table_entry.flags =
6044 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
6045 config->config_table[1].target_table_entry.client_id = 0;
6046 config->config_table[1].target_table_entry.vlan_id = 0;
6047
6048 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6049 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6050 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
6051}
6052
6053static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp)
6054{
6055 struct mac_configuration_cmd_e1h *config =
6056 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
6057
6058 if (bp->state != BNX2X_STATE_OPEN) {
6059 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
6060 return;
6061 }
6062
6063 /* CAM allocation for E1H
6064 * unicasts: by func number
6065 * multicast: 20+FUNC*20, 20 each
6066 */
6067 config->hdr.length_6b = 1;
6068 config->hdr.offset = BP_FUNC(bp);
6069 config->hdr.client_id = BP_CL_ID(bp);
6070 config->hdr.reserved1 = 0;
6071
6072 /* primary MAC */
6073 config->config_table[0].msb_mac_addr =
6074 swab16(*(u16 *)&bp->dev->dev_addr[0]);
6075 config->config_table[0].middle_mac_addr =
6076 swab16(*(u16 *)&bp->dev->dev_addr[2]);
6077 config->config_table[0].lsb_mac_addr =
6078 swab16(*(u16 *)&bp->dev->dev_addr[4]);
6079 config->config_table[0].client_id = BP_L_ID(bp);
6080 config->config_table[0].vlan_id = 0;
6081 config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
6082 config->config_table[0].flags = BP_PORT(bp);
6083
6084 DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x) E1HOV %d CLID %d\n",
6085 config->config_table[0].msb_mac_addr,
6086 config->config_table[0].middle_mac_addr,
6087 config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp));
6088
6089 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6090 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6091 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
6092}
6093
6094static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6095 int *state_p, int poll)
6096{
6097 /* can take a while if any port is running */
6098 int cnt = 500;
6099
6100 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6101 poll ? "polling" : "waiting", state, idx);
6102
6103 might_sleep();
6104 while (cnt--) {
6105 if (poll) {
6106 bnx2x_rx_int(bp->fp, 10);
6107 /* if index is different from 0
6108 * the reply for some commands will
6109 * be on the none default queue
6110 */
6111 if (idx)
6112 bnx2x_rx_int(&bp->fp[idx], 10);
6113 }
6114 mb(); /* state is changed by bnx2x_sp_event() */
6115
6116 if (*state_p == state)
6117 return 0;
6118
6119 msleep(1);
6120 }
6121
6122 /* timeout! */
6123 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6124 poll ? "polling" : "waiting", state, idx);
6125#ifdef BNX2X_STOP_ON_ERROR
6126 bnx2x_panic();
6127#endif
6128
6129 return -EBUSY;
6130}
6131
6132static int bnx2x_setup_leading(struct bnx2x *bp)
6133{
6134 int rc;
6135
6136 /* reset IGU state */
6137 bnx2x_ack_sb(bp, bp->fp[0].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6138
6139 /* SETUP ramrod */
6140 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
6141
6142 /* Wait for completion */
6143 rc = bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0);
6144
6145 return rc;
6146}
6147
6148static int bnx2x_setup_multi(struct bnx2x *bp, int index)
6149{
6150 /* reset IGU state */
6151 bnx2x_ack_sb(bp, bp->fp[index].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6152
6153 /* SETUP ramrod */
6154 bp->fp[index].state = BNX2X_FP_STATE_OPENING;
6155 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0, index, 0);
6156
6157 /* Wait for completion */
6158 return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index,
6159 &(bp->fp[index].state), 0);
6160}
6161
6162static int bnx2x_poll(struct napi_struct *napi, int budget);
6163static void bnx2x_set_rx_mode(struct net_device *dev);
6164
6165/* must be called with rtnl_lock */
6166static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6167{
6168 u32 load_code;
6169 int i, rc;
6170
6171#ifdef BNX2X_STOP_ON_ERROR
6172 if (unlikely(bp->panic))
6173 return -EPERM;
6174#endif
6175
6176 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
6177
6178 /* Send LOAD_REQUEST command to MCP
6179 Returns the type of LOAD command:
6180 if it is the first port to be initialized
6181 common blocks should be initialized, otherwise - not
6182 */
6183 if (!BP_NOMCP(bp)) {
6184 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
6185 if (!load_code) {
6186 BNX2X_ERR("MCP response failure, unloading\n");
6187 return -EBUSY;
6188 }
6189 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED)
6190 return -EBUSY; /* other port in diagnostic mode */
6191
6192 } else {
6193 DP(NETIF_MSG_IFUP, "NO MCP load counts before us %d, %d, %d\n",
6194 load_count[0], load_count[1], load_count[2]);
6195 load_count[0]++;
6196 load_count[1 + BP_PORT(bp)]++;
6197 DP(NETIF_MSG_IFUP, "NO MCP new load counts %d, %d, %d\n",
6198 load_count[0], load_count[1], load_count[2]);
6199 if (load_count[0] == 1)
6200 load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
6201 else if (load_count[1 + BP_PORT(bp)] == 1)
6202 load_code = FW_MSG_CODE_DRV_LOAD_PORT;
6203 else
6204 load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION;
6205 }
6206
6207 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
6208 (load_code == FW_MSG_CODE_DRV_LOAD_PORT))
6209 bp->port.pmf = 1;
6210 else
6211 bp->port.pmf = 0;
6212 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
6213
6214 /* if we can't use MSI-X we only need one fp,
6215 * so try to enable MSI-X with the requested number of fp's
6216 * and fallback to inta with one fp
6217 */
6218 if (use_inta) {
6219 bp->num_queues = 1;
6220
6221 } else {
6222 if ((use_multi > 1) && (use_multi <= BP_MAX_QUEUES(bp)))
6223 /* user requested number */
6224 bp->num_queues = use_multi;
6225
6226 else if (use_multi)
6227 bp->num_queues = min_t(u32, num_online_cpus(),
6228 BP_MAX_QUEUES(bp));
6229 else
6230 bp->num_queues = 1;
6231
6232 if (bnx2x_enable_msix(bp)) {
6233 /* failed to enable MSI-X */
6234 bp->num_queues = 1;
6235 if (use_multi)
6236 BNX2X_ERR("Multi requested but failed"
6237 " to enable MSI-X\n");
6238 }
6239 }
6240 DP(NETIF_MSG_IFUP,
6241 "set number of queues to %d\n", bp->num_queues);
6242
6243 if (bnx2x_alloc_mem(bp))
6244 return -ENOMEM;
6245
6246 for_each_queue(bp, i)
6247 bnx2x_fp(bp, i, disable_tpa) =
6248 ((bp->flags & TPA_ENABLE_FLAG) == 0);
6249
6250 /* Disable interrupt handling until HW is initialized */
6251 atomic_set(&bp->intr_sem, 1);
6252
6253 if (bp->flags & USING_MSIX_FLAG) {
6254 rc = bnx2x_req_msix_irqs(bp);
6255 if (rc) {
6256 pci_disable_msix(bp->pdev);
6257 goto load_error;
6258 }
6259 } else {
6260 bnx2x_ack_int(bp);
6261 rc = bnx2x_req_irq(bp);
6262 if (rc) {
6263 BNX2X_ERR("IRQ request failed, aborting\n");
6264 goto load_error;
6265 }
6266 }
6267
6268 for_each_queue(bp, i)
6269 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
6270 bnx2x_poll, 128);
6271
6272 /* Initialize HW */
6273 rc = bnx2x_init_hw(bp, load_code);
6274 if (rc) {
6275 BNX2X_ERR("HW init failed, aborting\n");
6276 goto load_error;
6277 }
6278
6279 /* Enable interrupt handling */
6280 atomic_set(&bp->intr_sem, 0);
6281
6282 /* Setup NIC internals and enable interrupts */
6283 bnx2x_nic_init(bp);
6284
6285 /* Send LOAD_DONE command to MCP */
6286 if (!BP_NOMCP(bp)) {
6287 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
6288 if (!load_code) {
6289 BNX2X_ERR("MCP response failure, unloading\n");
6290 rc = -EBUSY;
6291 goto load_int_disable;
6292 }
6293 }
6294
6295 bnx2x_stats_init(bp);
6296
6297 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
6298
6299 /* Enable Rx interrupt handling before sending the ramrod
6300 as it's completed on Rx FP queue */
6301 for_each_queue(bp, i)
6302 napi_enable(&bnx2x_fp(bp, i, napi));
6303
6304 rc = bnx2x_setup_leading(bp);
6305 if (rc) {
6306#ifdef BNX2X_STOP_ON_ERROR
6307 bp->panic = 1;
6308#endif
6309 goto load_stop_netif;
6310 }
6311
6312 if (CHIP_IS_E1H(bp))
6313 if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
6314 BNX2X_ERR("!!! mf_cfg function disabled\n");
6315 bp->state = BNX2X_STATE_DISABLED;
6316 }
6317
6318 if (bp->state == BNX2X_STATE_OPEN)
6319 for_each_nondefault_queue(bp, i) {
6320 rc = bnx2x_setup_multi(bp, i);
6321 if (rc)
6322 goto load_stop_netif;
6323 }
6324
6325 if (CHIP_IS_E1(bp))
6326 bnx2x_set_mac_addr_e1(bp);
6327 else
6328 bnx2x_set_mac_addr_e1h(bp);
6329
6330 if (bp->port.pmf)
6331 bnx2x_initial_phy_init(bp);
6332
6333 /* Start fast path */
6334 switch (load_mode) {
6335 case LOAD_NORMAL:
6336 /* Tx queue should be only reenabled */
6337 netif_wake_queue(bp->dev);
6338 bnx2x_set_rx_mode(bp->dev);
6339 break;
6340
6341 case LOAD_OPEN:
6342 /* IRQ is only requested from bnx2x_open */
6343 netif_start_queue(bp->dev);
6344 bnx2x_set_rx_mode(bp->dev);
6345 if (bp->flags & USING_MSIX_FLAG)
6346 printk(KERN_INFO PFX "%s: using MSI-X\n",
6347 bp->dev->name);
6348 break;
6349
6350 case LOAD_DIAG:
6351 bnx2x_set_rx_mode(bp->dev);
6352 bp->state = BNX2X_STATE_DIAG;
6353 break;
6354
6355 default:
6356 break;
6357 }
6358
6359 if (!bp->port.pmf)
6360 bnx2x__link_status_update(bp);
6361
6362 /* start the timer */
6363 mod_timer(&bp->timer, jiffies + bp->current_interval);
6364
6365
6366 return 0;
6367
6368load_stop_netif:
6369 for_each_queue(bp, i)
6370 napi_disable(&bnx2x_fp(bp, i, napi));
6371
6372load_int_disable:
6373 bnx2x_int_disable_sync(bp);
6374
6375 /* Release IRQs */
6376 bnx2x_free_irq(bp);
6377
6378 /* Free SKBs, SGEs, TPA pool and driver internals */
6379 bnx2x_free_skbs(bp);
6380 for_each_queue(bp, i)
6381 bnx2x_free_rx_sge_range(bp, bp->fp + i,
6382 RX_SGE_CNT*NUM_RX_SGE_PAGES);
6383load_error:
6384 bnx2x_free_mem(bp);
6385
6386 /* TBD we really need to reset the chip
6387 if we want to recover from this */
6388 return rc;
6389}
6390
6391static int bnx2x_stop_multi(struct bnx2x *bp, int index)
6392{
6393 int rc;
6394
6395 /* halt the connection */
6396 bp->fp[index].state = BNX2X_FP_STATE_HALTING;
6397 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, 0, 0);
6398
6399 /* Wait for completion */
6400 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index,
6401 &(bp->fp[index].state), 1);
6402 if (rc) /* timeout */
6403 return rc;
6404
6405 /* delete cfc entry */
6406 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1);
6407
6408 /* Wait for completion */
6409 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, index,
6410 &(bp->fp[index].state), 1);
6411 return rc;
6412}
6413
6414static void bnx2x_stop_leading(struct bnx2x *bp)
6415{
6416 u16 dsb_sp_prod_idx;
6417 /* if the other port is handling traffic,
6418 this can take a lot of time */
6419 int cnt = 500;
6420 int rc;
6421
6422 might_sleep();
6423
6424 /* Send HALT ramrod */
6425 bp->fp[0].state = BNX2X_FP_STATE_HALTING;
6426 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, BP_CL_ID(bp), 0);
6427
6428 /* Wait for completion */
6429 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
6430 &(bp->fp[0].state), 1);
6431 if (rc) /* timeout */
6432 return;
6433
6434 dsb_sp_prod_idx = *bp->dsb_sp_prod;
6435
6436 /* Send PORT_DELETE ramrod */
6437 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
6438
6439 /* Wait for completion to arrive on default status block
6440 we are going to reset the chip anyway
6441 so there is not much to do if this times out
6442 */
6443 while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
6444 msleep(1);
6445 if (!cnt) {
6446 DP(NETIF_MSG_IFDOWN, "timeout waiting for port del "
6447 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
6448 *bp->dsb_sp_prod, dsb_sp_prod_idx);
6449#ifdef BNX2X_STOP_ON_ERROR
6450 bnx2x_panic();
6451#endif
6452 break;
6453 }
6454 cnt--;
6455 }
6456 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
6457 bp->fp[0].state = BNX2X_FP_STATE_CLOSED;
6458}
6459
6460static void bnx2x_reset_func(struct bnx2x *bp)
6461{
6462 int port = BP_PORT(bp);
6463 int func = BP_FUNC(bp);
6464 int base, i;
6465
6466 /* Configure IGU */
6467 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6468 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6469
6470 REG_WR(bp, HC_REG_CONFIG_0 + port*4, 0x1000);
6471
6472 /* Clear ILT */
6473 base = FUNC_ILT_BASE(func);
6474 for (i = base; i < base + ILT_PER_FUNC; i++)
6475 bnx2x_ilt_wr(bp, i, 0);
6476}
6477
6478static void bnx2x_reset_port(struct bnx2x *bp)
6479{
6480 int port = BP_PORT(bp);
6481 u32 val;
6482
6483 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6484
6485 /* Do not rcv packets to BRB */
6486 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
6487 /* Do not direct rcv packets that are not for MCP to the BRB */
6488 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
6489 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6490
6491 /* Configure AEU */
6492 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
6493
6494 msleep(100);
6495 /* Check for BRB port occupancy */
6496 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
6497 if (val)
6498 DP(NETIF_MSG_IFDOWN,
6499 "BRB1 is not empty %d blooks are occupied\n", val);
6500
6501 /* TODO: Close Doorbell port? */
6502}
6503
6504static void bnx2x_reset_common(struct bnx2x *bp)
6505{
6506 /* reset_common */
6507 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6508 0xd3ffff7f);
6509 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
6510}
6511
6512static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
6513{
6514 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
6515 BP_FUNC(bp), reset_code);
6516
6517 switch (reset_code) {
6518 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
6519 bnx2x_reset_port(bp);
6520 bnx2x_reset_func(bp);
6521 bnx2x_reset_common(bp);
6522 break;
6523
6524 case FW_MSG_CODE_DRV_UNLOAD_PORT:
6525 bnx2x_reset_port(bp);
6526 bnx2x_reset_func(bp);
6527 break;
6528
6529 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
6530 bnx2x_reset_func(bp);
6531 break;
6532
6533 default:
6534 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
6535 break;
6536 }
6537}
6538
6539/* msut be called with rtnl_lock */
6540static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
6541{
6542 u32 reset_code = 0;
6543 int i, cnt;
6544
6545 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
6546
6547 bp->rx_mode = BNX2X_RX_MODE_NONE;
6548 bnx2x_set_storm_rx_mode(bp);
6549
6550 if (netif_running(bp->dev)) {
6551 netif_tx_disable(bp->dev);
6552 bp->dev->trans_start = jiffies; /* prevent tx timeout */
6553 }
6554
6555 del_timer_sync(&bp->timer);
6556 SHMEM_WR(bp, func_mb[BP_FUNC(bp)].drv_pulse_mb,
6557 (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq));
6558 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
6559
6560 /* Wait until all fast path tasks complete */
6561 for_each_queue(bp, i) {
6562 struct bnx2x_fastpath *fp = &bp->fp[i];
6563
6564#ifdef BNX2X_STOP_ON_ERROR
6565#ifdef __powerpc64__
6566 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
6567#else
6568 DP(NETIF_MSG_IFDOWN, "fp->tpa_queue_used = 0x%llx\n",
6569#endif
6570 fp->tpa_queue_used);
6571#endif
6572 cnt = 1000;
6573 smp_rmb();
6574 while (bnx2x_has_work(fp)) {
6575 msleep(1);
6576 if (!cnt) {
6577 BNX2X_ERR("timeout waiting for queue[%d]\n",
6578 i);
6579#ifdef BNX2X_STOP_ON_ERROR
6580 bnx2x_panic();
6581 return -EBUSY;
6582#else
6583 break;
6584#endif
6585 }
6586 cnt--;
6587 smp_rmb();
6588 }
6589 }
6590
6591 /* Wait until all slow path tasks complete */
6592 cnt = 1000;
6593 while ((bp->spq_left != MAX_SPQ_PENDING) && cnt--)
6594 msleep(1);
6595
6596 for_each_queue(bp, i)
6597 napi_disable(&bnx2x_fp(bp, i, napi));
6598 /* Disable interrupts after Tx and Rx are disabled on stack level */
6599 bnx2x_int_disable_sync(bp);
6600
6601 /* Release IRQs */
6602 bnx2x_free_irq(bp);
6603
6604 if (bp->flags & NO_WOL_FLAG)
6605 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
6606
6607 else if (bp->wol) {
6608 u32 emac_base = BP_PORT(bp) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6609 u8 *mac_addr = bp->dev->dev_addr;
6610 u32 val;
6611
6612 /* The mac address is written to entries 1-4 to
6613 preserve entry 0 which is used by the PMF */
6614 val = (mac_addr[0] << 8) | mac_addr[1];
6615 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + (BP_E1HVN(bp) + 1)*8, val);
6616
6617 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
6618 (mac_addr[4] << 8) | mac_addr[5];
6619 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + (BP_E1HVN(bp) + 1)*8 + 4,
6620 val);
6621
6622 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
6623
6624 } else
6625 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6626
6627 /* Close multi and leading connections
6628 Completions for ramrods are collected in a synchronous way */
6629 for_each_nondefault_queue(bp, i)
6630 if (bnx2x_stop_multi(bp, i))
6631 goto unload_error;
6632
6633 if (CHIP_IS_E1H(bp))
6634 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + BP_PORT(bp)*8, 0);
6635
6636 bnx2x_stop_leading(bp);
6637#ifdef BNX2X_STOP_ON_ERROR
6638 /* If ramrod completion timed out - break here! */
6639 if (bp->panic) {
6640 BNX2X_ERR("Stop leading failed!\n");
6641 return -EBUSY;
6642 }
6643#endif
6644
6645 if ((bp->state != BNX2X_STATE_CLOSING_WAIT4_UNLOAD) ||
6646 (bp->fp[0].state != BNX2X_FP_STATE_CLOSED)) {
6647 DP(NETIF_MSG_IFDOWN, "failed to close leading properly! "
6648 "state 0x%x fp[0].state 0x%x\n",
6649 bp->state, bp->fp[0].state);
6650 }
6651
6652unload_error:
6653 if (!BP_NOMCP(bp))
6654 reset_code = bnx2x_fw_command(bp, reset_code);
6655 else {
6656 DP(NETIF_MSG_IFDOWN, "NO MCP load counts %d, %d, %d\n",
6657 load_count[0], load_count[1], load_count[2]);
6658 load_count[0]--;
6659 load_count[1 + BP_PORT(bp)]--;
6660 DP(NETIF_MSG_IFDOWN, "NO MCP new load counts %d, %d, %d\n",
6661 load_count[0], load_count[1], load_count[2]);
6662 if (load_count[0] == 0)
6663 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
6664 else if (load_count[1 + BP_PORT(bp)] == 0)
6665 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
6666 else
6667 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
6668 }
6669
6670 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
6671 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
6672 bnx2x__link_reset(bp);
6673
6674 /* Reset the chip */
6675 bnx2x_reset_chip(bp, reset_code);
6676
6677 /* Report UNLOAD_DONE to MCP */
6678 if (!BP_NOMCP(bp))
6679 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6680
6681 /* Free SKBs, SGEs, TPA pool and driver internals */
6682 bnx2x_free_skbs(bp);
6683 for_each_queue(bp, i)
6684 bnx2x_free_rx_sge_range(bp, bp->fp + i,
6685 RX_SGE_CNT*NUM_RX_SGE_PAGES);
6686 bnx2x_free_mem(bp);
6687
6688 bp->state = BNX2X_STATE_CLOSED;
6689
6690 netif_carrier_off(bp->dev);
6691
6692 return 0;
6693}
6694
6695static void bnx2x_reset_task(struct work_struct *work)
6696{
6697 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task);
6698
6699#ifdef BNX2X_STOP_ON_ERROR
6700 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
6701 " so reset not done to allow debug dump,\n"
6702 KERN_ERR " you will need to reboot when done\n");
6703 return;
6704#endif
6705
6706 rtnl_lock();
6707
6708 if (!netif_running(bp->dev))
6709 goto reset_task_exit;
6710
6711 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
6712 bnx2x_nic_load(bp, LOAD_NORMAL);
6713
6714reset_task_exit:
6715 rtnl_unlock();
6716}
6717
6718/* end of nic load/unload */
6719
6720/* ethtool_ops */
6721
6722/*
6723 * Init service functions
6724 */
6725
6726static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
6727{
6728 u32 val;
6729
6730 /* Check if there is any driver already loaded */
6731 val = REG_RD(bp, MISC_REG_UNPREPARED);
6732 if (val == 0x1) {
6733 /* Check if it is the UNDI driver
6734 * UNDI driver initializes CID offset for normal bell to 0x7
6735 */
6736 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
6737 if (val == 0x7) {
6738 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6739 /* save our func and fw_seq */
6740 int func = BP_FUNC(bp);
6741 u16 fw_seq = bp->fw_seq;
6742
6743 BNX2X_DEV_INFO("UNDI is active! reset device\n");
6744
6745 /* try unload UNDI on port 0 */
6746 bp->func = 0;
6747 bp->fw_seq = (SHMEM_RD(bp,
6748 func_mb[bp->func].drv_mb_header) &
6749 DRV_MSG_SEQ_NUMBER_MASK);
6750
6751 reset_code = bnx2x_fw_command(bp, reset_code);
6752 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6753
6754 /* if UNDI is loaded on the other port */
6755 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
6756
6757 bp->func = 1;
6758 bp->fw_seq = (SHMEM_RD(bp,
6759 func_mb[bp->func].drv_mb_header) &
6760 DRV_MSG_SEQ_NUMBER_MASK);
6761
6762 bnx2x_fw_command(bp,
6763 DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS);
6764 bnx2x_fw_command(bp,
6765 DRV_MSG_CODE_UNLOAD_DONE);
6766
6767 /* restore our func and fw_seq */
6768 bp->func = func;
6769 bp->fw_seq = fw_seq;
6770 }
6771
6772 /* reset device */
6773 REG_WR(bp,
6774 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6775 0xd3ffff7f);
6776 REG_WR(bp,
6777 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6778 0x1403);
6779 }
6780 }
6781}
6782
6783static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
6784{
6785 u32 val, val2, val3, val4, id;
6786
6787 /* Get the chip revision id and number. */
6788 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
6789 val = REG_RD(bp, MISC_REG_CHIP_NUM);
6790 id = ((val & 0xffff) << 16);
6791 val = REG_RD(bp, MISC_REG_CHIP_REV);
6792 id |= ((val & 0xf) << 12);
6793 val = REG_RD(bp, MISC_REG_CHIP_METAL);
6794 id |= ((val & 0xff) << 4);
6795 REG_RD(bp, MISC_REG_BOND_ID);
6796 id |= (val & 0xf);
6797 bp->common.chip_id = id;
6798 bp->link_params.chip_id = bp->common.chip_id;
6799 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
6800
6801 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
6802 bp->common.flash_size = (NVRAM_1MB_SIZE <<
6803 (val & MCPR_NVM_CFG4_FLASH_SIZE));
6804 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
6805 bp->common.flash_size, bp->common.flash_size);
6806
6807 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
6808 bp->link_params.shmem_base = bp->common.shmem_base;
6809 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
6810
6811 if (!bp->common.shmem_base ||
6812 (bp->common.shmem_base < 0xA0000) ||
6813 (bp->common.shmem_base >= 0xC0000)) {
6814 BNX2X_DEV_INFO("MCP not active\n");
6815 bp->flags |= NO_MCP_FLAG;
6816 return;
6817 }
6818
6819 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
6820 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6821 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6822 BNX2X_ERR("BAD MCP validity signature\n");
6823
6824 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
6825 bp->common.board = SHMEM_RD(bp, dev_info.shared_hw_config.board);
6826
6827 BNX2X_DEV_INFO("hw_config 0x%08x board 0x%08x\n",
6828 bp->common.hw_config, bp->common.board);
6829
6830 bp->link_params.hw_led_mode = ((bp->common.hw_config &
6831 SHARED_HW_CFG_LED_MODE_MASK) >>
6832 SHARED_HW_CFG_LED_MODE_SHIFT);
6833
6834 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
6835 bp->common.bc_ver = val;
6836 BNX2X_DEV_INFO("bc_ver %X\n", val);
6837 if (val < BNX2X_BC_VER) {
6838 /* for now only warn
6839 * later we might need to enforce this */
6840 BNX2X_ERR("This driver needs bc_ver %X but found %X,"
6841 " please upgrade BC\n", BNX2X_BC_VER, val);
6842 }
6843 BNX2X_DEV_INFO("%sWoL Capable\n",
6844 (bp->flags & NO_WOL_FLAG)? "Not " : "");
6845
6846 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
6847 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
6848 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
6849 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
6850
6851 printk(KERN_INFO PFX "part number %X-%X-%X-%X\n",
6852 val, val2, val3, val4);
6853}
6854
6855static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
6856 u32 switch_cfg)
6857{
6858 int port = BP_PORT(bp);
6859 u32 ext_phy_type;
6860
6861 switch (switch_cfg) {
6862 case SWITCH_CFG_1G:
6863 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
6864
6865 ext_phy_type =
6866 SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
6867 switch (ext_phy_type) {
6868 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
6869 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
6870 ext_phy_type);
6871
6872 bp->port.supported |= (SUPPORTED_10baseT_Half |
6873 SUPPORTED_10baseT_Full |
6874 SUPPORTED_100baseT_Half |
6875 SUPPORTED_100baseT_Full |
6876 SUPPORTED_1000baseT_Full |
6877 SUPPORTED_2500baseX_Full |
6878 SUPPORTED_TP |
6879 SUPPORTED_FIBRE |
6880 SUPPORTED_Autoneg |
6881 SUPPORTED_Pause |
6882 SUPPORTED_Asym_Pause);
6883 break;
6884
6885 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
6886 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
6887 ext_phy_type);
6888
6889 bp->port.supported |= (SUPPORTED_10baseT_Half |
6890 SUPPORTED_10baseT_Full |
6891 SUPPORTED_100baseT_Half |
6892 SUPPORTED_100baseT_Full |
6893 SUPPORTED_1000baseT_Full |
6894 SUPPORTED_TP |
6895 SUPPORTED_FIBRE |
6896 SUPPORTED_Autoneg |
6897 SUPPORTED_Pause |
6898 SUPPORTED_Asym_Pause);
6899 break;
6900
6901 default:
6902 BNX2X_ERR("NVRAM config error. "
6903 "BAD SerDes ext_phy_config 0x%x\n",
6904 bp->link_params.ext_phy_config);
6905 return;
6906 }
6907
6908 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
6909 port*0x10);
6910 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
6911 break;
6912
6913 case SWITCH_CFG_10G:
6914 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
6915
6916 ext_phy_type =
6917 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
6918 switch (ext_phy_type) {
6919 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6920 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
6921 ext_phy_type);
6922
6923 bp->port.supported |= (SUPPORTED_10baseT_Half |
6924 SUPPORTED_10baseT_Full |
6925 SUPPORTED_100baseT_Half |
6926 SUPPORTED_100baseT_Full |
6927 SUPPORTED_1000baseT_Full |
6928 SUPPORTED_2500baseX_Full |
6929 SUPPORTED_10000baseT_Full |
6930 SUPPORTED_TP |
6931 SUPPORTED_FIBRE |
6932 SUPPORTED_Autoneg |
6933 SUPPORTED_Pause |
6934 SUPPORTED_Asym_Pause);
6935 break;
6936
6937 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
6938 BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
6939 ext_phy_type);
6940
6941 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6942 SUPPORTED_FIBRE |
6943 SUPPORTED_Pause |
6944 SUPPORTED_Asym_Pause);
6945 break;
6946
6947 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
6948 BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
6949 ext_phy_type);
6950
6951 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6952 SUPPORTED_1000baseT_Full |
6953 SUPPORTED_FIBRE |
6954 SUPPORTED_Pause |
6955 SUPPORTED_Asym_Pause);
6956 break;
6957
6958 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6959 BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
6960 ext_phy_type);
6961
6962 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6963 SUPPORTED_1000baseT_Full |
6964 SUPPORTED_FIBRE |
6965 SUPPORTED_Autoneg |
6966 SUPPORTED_Pause |
6967 SUPPORTED_Asym_Pause);
6968 break;
6969
6970 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6971 BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
6972 ext_phy_type);
6973
6974 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6975 SUPPORTED_2500baseX_Full |
6976 SUPPORTED_1000baseT_Full |
6977 SUPPORTED_FIBRE |
6978 SUPPORTED_Autoneg |
6979 SUPPORTED_Pause |
6980 SUPPORTED_Asym_Pause);
6981 break;
6982
6983 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
6984 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
6985 ext_phy_type);
6986
6987 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6988 SUPPORTED_TP |
6989 SUPPORTED_Autoneg |
6990 SUPPORTED_Pause |
6991 SUPPORTED_Asym_Pause);
6992 break;
6993
6994 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
6995 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
6996 bp->link_params.ext_phy_config);
6997 break;
6998
6999 default:
7000 BNX2X_ERR("NVRAM config error. "
7001 "BAD XGXS ext_phy_config 0x%x\n",
7002 bp->link_params.ext_phy_config);
7003 return;
7004 }
7005
7006 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
7007 port*0x18);
7008 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
7009
7010 break;
7011
7012 default:
7013 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
7014 bp->port.link_config);
7015 return;
7016 }
7017 bp->link_params.phy_addr = bp->port.phy_addr;
7018
7019 /* mask what we support according to speed_cap_mask */
7020 if (!(bp->link_params.speed_cap_mask &
7021 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
7022 bp->port.supported &= ~SUPPORTED_10baseT_Half;
7023
7024 if (!(bp->link_params.speed_cap_mask &
7025 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
7026 bp->port.supported &= ~SUPPORTED_10baseT_Full;
7027
7028 if (!(bp->link_params.speed_cap_mask &
7029 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
7030 bp->port.supported &= ~SUPPORTED_100baseT_Half;
7031
7032 if (!(bp->link_params.speed_cap_mask &
7033 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
7034 bp->port.supported &= ~SUPPORTED_100baseT_Full;
7035
7036 if (!(bp->link_params.speed_cap_mask &
7037 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
7038 bp->port.supported &= ~(SUPPORTED_1000baseT_Half |
7039 SUPPORTED_1000baseT_Full);
7040
7041 if (!(bp->link_params.speed_cap_mask &
7042 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7043 bp->port.supported &= ~SUPPORTED_2500baseX_Full;
7044
7045 if (!(bp->link_params.speed_cap_mask &
7046 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
7047 bp->port.supported &= ~SUPPORTED_10000baseT_Full;
7048
7049 BNX2X_DEV_INFO("supported 0x%x\n", bp->port.supported);
7050}
7051
7052static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
7053{
7054 bp->link_params.req_duplex = DUPLEX_FULL;
7055
7056 switch (bp->port.link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7057 case PORT_FEATURE_LINK_SPEED_AUTO:
7058 if (bp->port.supported & SUPPORTED_Autoneg) {
7059 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7060 bp->port.advertising = bp->port.supported;
7061 } else {
7062 u32 ext_phy_type =
7063 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7064
7065 if ((ext_phy_type ==
7066 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
7067 (ext_phy_type ==
7068 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
7069 /* force 10G, no AN */
7070 bp->link_params.req_line_speed = SPEED_10000;
7071 bp->port.advertising =
7072 (ADVERTISED_10000baseT_Full |
7073 ADVERTISED_FIBRE);
7074 break;
7075 }
7076 BNX2X_ERR("NVRAM config error. "
7077 "Invalid link_config 0x%x"
7078 " Autoneg not supported\n",
7079 bp->port.link_config);
7080 return;
7081 }
7082 break;
7083
7084 case PORT_FEATURE_LINK_SPEED_10M_FULL:
7085 if (bp->port.supported & SUPPORTED_10baseT_Full) {
7086 bp->link_params.req_line_speed = SPEED_10;
7087 bp->port.advertising = (ADVERTISED_10baseT_Full |
7088 ADVERTISED_TP);
7089 } else {
7090 BNX2X_ERR("NVRAM config error. "
7091 "Invalid link_config 0x%x"
7092 " speed_cap_mask 0x%x\n",
7093 bp->port.link_config,
7094 bp->link_params.speed_cap_mask);
7095 return;
7096 }
7097 break;
7098
7099 case PORT_FEATURE_LINK_SPEED_10M_HALF:
7100 if (bp->port.supported & SUPPORTED_10baseT_Half) {
7101 bp->link_params.req_line_speed = SPEED_10;
7102 bp->link_params.req_duplex = DUPLEX_HALF;
7103 bp->port.advertising = (ADVERTISED_10baseT_Half |
7104 ADVERTISED_TP);
7105 } else {
7106 BNX2X_ERR("NVRAM config error. "
7107 "Invalid link_config 0x%x"
7108 " speed_cap_mask 0x%x\n",
7109 bp->port.link_config,
7110 bp->link_params.speed_cap_mask);
7111 return;
7112 }
7113 break;
7114
7115 case PORT_FEATURE_LINK_SPEED_100M_FULL:
7116 if (bp->port.supported & SUPPORTED_100baseT_Full) {
7117 bp->link_params.req_line_speed = SPEED_100;
7118 bp->port.advertising = (ADVERTISED_100baseT_Full |
7119 ADVERTISED_TP);
7120 } else {
7121 BNX2X_ERR("NVRAM config error. "
7122 "Invalid link_config 0x%x"
7123 " speed_cap_mask 0x%x\n",
7124 bp->port.link_config,
7125 bp->link_params.speed_cap_mask);
7126 return;
7127 }
7128 break;
7129
7130 case PORT_FEATURE_LINK_SPEED_100M_HALF:
7131 if (bp->port.supported & SUPPORTED_100baseT_Half) {
7132 bp->link_params.req_line_speed = SPEED_100;
7133 bp->link_params.req_duplex = DUPLEX_HALF;
7134 bp->port.advertising = (ADVERTISED_100baseT_Half |
7135 ADVERTISED_TP);
7136 } else {
7137 BNX2X_ERR("NVRAM config error. "
7138 "Invalid link_config 0x%x"
7139 " speed_cap_mask 0x%x\n",
7140 bp->port.link_config,
7141 bp->link_params.speed_cap_mask);
7142 return;
7143 }
7144 break;
7145
7146 case PORT_FEATURE_LINK_SPEED_1G:
7147 if (bp->port.supported & SUPPORTED_1000baseT_Full) {
7148 bp->link_params.req_line_speed = SPEED_1000;
7149 bp->port.advertising = (ADVERTISED_1000baseT_Full |
7150 ADVERTISED_TP);
7151 } else {
7152 BNX2X_ERR("NVRAM config error. "
7153 "Invalid link_config 0x%x"
7154 " speed_cap_mask 0x%x\n",
7155 bp->port.link_config,
7156 bp->link_params.speed_cap_mask);
7157 return;
7158 }
7159 break;
7160
7161 case PORT_FEATURE_LINK_SPEED_2_5G:
7162 if (bp->port.supported & SUPPORTED_2500baseX_Full) {
7163 bp->link_params.req_line_speed = SPEED_2500;
7164 bp->port.advertising = (ADVERTISED_2500baseX_Full |
7165 ADVERTISED_TP);
7166 } else {
7167 BNX2X_ERR("NVRAM config error. "
7168 "Invalid link_config 0x%x"
7169 " speed_cap_mask 0x%x\n",
7170 bp->port.link_config,
7171 bp->link_params.speed_cap_mask);
7172 return;
7173 }
7174 break;
7175
7176 case PORT_FEATURE_LINK_SPEED_10G_CX4:
7177 case PORT_FEATURE_LINK_SPEED_10G_KX4:
7178 case PORT_FEATURE_LINK_SPEED_10G_KR:
7179 if (bp->port.supported & SUPPORTED_10000baseT_Full) {
7180 bp->link_params.req_line_speed = SPEED_10000;
7181 bp->port.advertising = (ADVERTISED_10000baseT_Full |
7182 ADVERTISED_FIBRE);
7183 } else {
7184 BNX2X_ERR("NVRAM config error. "
7185 "Invalid link_config 0x%x"
7186 " speed_cap_mask 0x%x\n",
7187 bp->port.link_config,
7188 bp->link_params.speed_cap_mask);
7189 return;
7190 }
7191 break;
7192
7193 default:
7194 BNX2X_ERR("NVRAM config error. "
7195 "BAD link speed link_config 0x%x\n",
7196 bp->port.link_config);
7197 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7198 bp->port.advertising = bp->port.supported;
7199 break;
7200 }
7201
7202 bp->link_params.req_flow_ctrl = (bp->port.link_config &
7203 PORT_FEATURE_FLOW_CONTROL_MASK);
7204 if ((bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
7205 (!bp->port.supported & SUPPORTED_Autoneg))
7206 bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
7207
7208 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x"
7209 " advertising 0x%x\n",
7210 bp->link_params.req_line_speed,
7211 bp->link_params.req_duplex,
7212 bp->link_params.req_flow_ctrl, bp->port.advertising);
7213}
7214
7215static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
7216{
7217 int port = BP_PORT(bp);
7218 u32 val, val2;
7219
7220 bp->link_params.bp = bp;
7221 bp->link_params.port = port;
7222
7223 bp->link_params.serdes_config =
7224 SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config);
7225 bp->link_params.lane_config =
7226 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
7227 bp->link_params.ext_phy_config =
7228 SHMEM_RD(bp,
7229 dev_info.port_hw_config[port].external_phy_config);
7230 bp->link_params.speed_cap_mask =
7231 SHMEM_RD(bp,
7232 dev_info.port_hw_config[port].speed_capability_mask);
7233
7234 bp->port.link_config =
7235 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
7236
7237 BNX2X_DEV_INFO("serdes_config 0x%08x lane_config 0x%08x\n"
7238 KERN_INFO " ext_phy_config 0x%08x speed_cap_mask 0x%08x"
7239 " link_config 0x%08x\n",
7240 bp->link_params.serdes_config,
7241 bp->link_params.lane_config,
7242 bp->link_params.ext_phy_config,
7243 bp->link_params.speed_cap_mask, bp->port.link_config);
7244
7245 bp->link_params.switch_cfg = (bp->port.link_config &
7246 PORT_FEATURE_CONNECTED_SWITCH_MASK);
7247 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
7248
7249 bnx2x_link_settings_requested(bp);
7250
7251 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
7252 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
7253 bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
7254 bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
7255 bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
7256 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
7257 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
7258 bp->dev->dev_addr[5] = (u8)(val & 0xff);
7259 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
7260 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
7261}
7262
7263static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
7264{
7265 int func = BP_FUNC(bp);
7266 u32 val, val2;
7267 int rc = 0;
7268
7269 bnx2x_get_common_hwinfo(bp);
7270
7271 bp->e1hov = 0;
7272 bp->e1hmf = 0;
7273 if (CHIP_IS_E1H(bp)) {
7274 bp->mf_config =
7275 SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
7276
7277 val =
7278 (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) &
7279 FUNC_MF_CFG_E1HOV_TAG_MASK);
7280 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7281
7282 bp->e1hov = val;
7283 bp->e1hmf = 1;
7284 BNX2X_DEV_INFO("MF mode E1HOV for func %d is %d "
7285 "(0x%04x)\n",
7286 func, bp->e1hov, bp->e1hov);
7287 } else {
7288 BNX2X_DEV_INFO("Single function mode\n");
7289 if (BP_E1HVN(bp)) {
7290 BNX2X_ERR("!!! No valid E1HOV for func %d,"
7291 " aborting\n", func);
7292 rc = -EPERM;
7293 }
7294 }
7295 }
7296
7297 if (!BP_NOMCP(bp)) {
7298 bnx2x_get_port_hwinfo(bp);
7299
7300 bp->fw_seq = (SHMEM_RD(bp, func_mb[func].drv_mb_header) &
7301 DRV_MSG_SEQ_NUMBER_MASK);
7302 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
7303 }
7304
7305 if (IS_E1HMF(bp)) {
7306 val2 = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_upper);
7307 val = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_lower);
7308 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
7309 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) {
7310 bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
7311 bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
7312 bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
7313 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
7314 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
7315 bp->dev->dev_addr[5] = (u8)(val & 0xff);
7316 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr,
7317 ETH_ALEN);
7318 memcpy(bp->dev->perm_addr, bp->dev->dev_addr,
7319 ETH_ALEN);
7320 }
7321
7322 return rc;
7323 }
7324
7325 if (BP_NOMCP(bp)) {
7326 /* only supposed to happen on emulation/FPGA */
7327 BNX2X_ERR("warning rendom MAC workaround active\n");
7328 random_ether_addr(bp->dev->dev_addr);
7329 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
7330 }
7331
7332 return rc;
7333}
7334
7335static int __devinit bnx2x_init_bp(struct bnx2x *bp)
7336{
7337 int func = BP_FUNC(bp);
7338 int rc;
7339
7340 if (nomcp)
7341 bp->flags |= NO_MCP_FLAG;
7342
7343 mutex_init(&bp->port.phy_mutex);
7344
7345 INIT_WORK(&bp->sp_task, bnx2x_sp_task);
7346 INIT_WORK(&bp->reset_task, bnx2x_reset_task);
7347
7348 rc = bnx2x_get_hwinfo(bp);
7349
7350 /* need to reset chip if undi was active */
7351 if (!BP_NOMCP(bp))
7352 bnx2x_undi_unload(bp);
7353
7354 if (CHIP_REV_IS_FPGA(bp))
7355 printk(KERN_ERR PFX "FPGA detected\n");
7356
7357 if (BP_NOMCP(bp) && (func == 0))
7358 printk(KERN_ERR PFX
7359 "MCP disabled, must load devices in order!\n");
7360
7361 /* Set TPA flags */
7362 if (disable_tpa) {
7363 bp->flags &= ~TPA_ENABLE_FLAG;
7364 bp->dev->features &= ~NETIF_F_LRO;
7365 } else {
7366 bp->flags |= TPA_ENABLE_FLAG;
7367 bp->dev->features |= NETIF_F_LRO;
7368 }
7369
7370
7371 bp->tx_ring_size = MAX_TX_AVAIL;
7372 bp->rx_ring_size = MAX_RX_AVAIL;
7373
7374 bp->rx_csum = 1;
7375 bp->rx_offset = 0;
7376
7377 bp->tx_ticks = 50;
7378 bp->rx_ticks = 25;
7379
7380 bp->stats_ticks = 1000000 & 0xffff00;
7381
7382 bp->timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
7383 bp->current_interval = (poll ? poll : bp->timer_interval);
7384
7385 init_timer(&bp->timer);
7386 bp->timer.expires = jiffies + bp->current_interval;
7387 bp->timer.data = (unsigned long) bp;
7388 bp->timer.function = bnx2x_timer;
7389
7390 return rc;
7391}
7392
7393/*
7394 * ethtool service functions
7395 */
7396
7397/* All ethtool functions called with rtnl_lock */
7398
7399static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7400{
7401 struct bnx2x *bp = netdev_priv(dev);
7402
7403 cmd->supported = bp->port.supported;
7404 cmd->advertising = bp->port.advertising;
7405
7406 if (netif_carrier_ok(dev)) {
7407 cmd->speed = bp->link_vars.line_speed;
7408 cmd->duplex = bp->link_vars.duplex;
7409 } else {
7410 cmd->speed = bp->link_params.req_line_speed;
7411 cmd->duplex = bp->link_params.req_duplex;
7412 }
7413 if (IS_E1HMF(bp)) {
7414 u16 vn_max_rate;
7415
7416 vn_max_rate = ((bp->mf_config & FUNC_MF_CFG_MAX_BW_MASK) >>
7417 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
7418 if (vn_max_rate < cmd->speed)
7419 cmd->speed = vn_max_rate;
7420 }
7421
7422 if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
7423 u32 ext_phy_type =
7424 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7425
7426 switch (ext_phy_type) {
7427 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7428 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7429 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7430 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
7431 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7432 cmd->port = PORT_FIBRE;
7433 break;
7434
7435 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7436 cmd->port = PORT_TP;
7437 break;
7438
7439 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7440 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
7441 bp->link_params.ext_phy_config);
7442 break;
7443
7444 default:
7445 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
7446 bp->link_params.ext_phy_config);
7447 break;
7448 }
7449 } else
7450 cmd->port = PORT_TP;
7451
7452 cmd->phy_address = bp->port.phy_addr;
7453 cmd->transceiver = XCVR_INTERNAL;
7454
7455 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
7456 cmd->autoneg = AUTONEG_ENABLE;
7457 else
7458 cmd->autoneg = AUTONEG_DISABLE;
7459
7460 cmd->maxtxpkt = 0;
7461 cmd->maxrxpkt = 0;
7462
7463 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
7464 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
7465 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
7466 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
7467 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
7468 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
7469 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
7470
7471 return 0;
7472}
7473
7474static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7475{
7476 struct bnx2x *bp = netdev_priv(dev);
7477 u32 advertising;
7478
7479 if (IS_E1HMF(bp))
7480 return 0;
7481
7482 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
7483 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
7484 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
7485 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
7486 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
7487 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
7488 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
7489
7490 if (cmd->autoneg == AUTONEG_ENABLE) {
7491 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
7492 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
7493 return -EINVAL;
7494 }
7495
7496 /* advertise the requested speed and duplex if supported */
7497 cmd->advertising &= bp->port.supported;
7498
7499 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7500 bp->link_params.req_duplex = DUPLEX_FULL;
7501 bp->port.advertising |= (ADVERTISED_Autoneg |
7502 cmd->advertising);
7503
7504 } else { /* forced speed */
7505 /* advertise the requested speed and duplex if supported */
7506 switch (cmd->speed) {
7507 case SPEED_10:
7508 if (cmd->duplex == DUPLEX_FULL) {
7509 if (!(bp->port.supported &
7510 SUPPORTED_10baseT_Full)) {
7511 DP(NETIF_MSG_LINK,
7512 "10M full not supported\n");
7513 return -EINVAL;
7514 }
7515
7516 advertising = (ADVERTISED_10baseT_Full |
7517 ADVERTISED_TP);
7518 } else {
7519 if (!(bp->port.supported &
7520 SUPPORTED_10baseT_Half)) {
7521 DP(NETIF_MSG_LINK,
7522 "10M half not supported\n");
7523 return -EINVAL;
7524 }
7525
7526 advertising = (ADVERTISED_10baseT_Half |
7527 ADVERTISED_TP);
7528 }
7529 break;
7530
7531 case SPEED_100:
7532 if (cmd->duplex == DUPLEX_FULL) {
7533 if (!(bp->port.supported &
7534 SUPPORTED_100baseT_Full)) {
7535 DP(NETIF_MSG_LINK,
7536 "100M full not supported\n");
7537 return -EINVAL;
7538 }
7539
7540 advertising = (ADVERTISED_100baseT_Full |
7541 ADVERTISED_TP);
7542 } else {
7543 if (!(bp->port.supported &
7544 SUPPORTED_100baseT_Half)) {
7545 DP(NETIF_MSG_LINK,
7546 "100M half not supported\n");
7547 return -EINVAL;
7548 }
7549
7550 advertising = (ADVERTISED_100baseT_Half |
7551 ADVERTISED_TP);
7552 }
7553 break;
7554
7555 case SPEED_1000:
7556 if (cmd->duplex != DUPLEX_FULL) {
7557 DP(NETIF_MSG_LINK, "1G half not supported\n");
7558 return -EINVAL;
7559 }
7560
7561 if (!(bp->port.supported & SUPPORTED_1000baseT_Full)) {
7562 DP(NETIF_MSG_LINK, "1G full not supported\n");
7563 return -EINVAL;
7564 }
7565
7566 advertising = (ADVERTISED_1000baseT_Full |
7567 ADVERTISED_TP);
7568 break;
7569
7570 case SPEED_2500:
7571 if (cmd->duplex != DUPLEX_FULL) {
7572 DP(NETIF_MSG_LINK,
7573 "2.5G half not supported\n");
7574 return -EINVAL;
7575 }
7576
7577 if (!(bp->port.supported & SUPPORTED_2500baseX_Full)) {
7578 DP(NETIF_MSG_LINK,
7579 "2.5G full not supported\n");
7580 return -EINVAL;
7581 }
7582
7583 advertising = (ADVERTISED_2500baseX_Full |
7584 ADVERTISED_TP);
7585 break;
7586
7587 case SPEED_10000:
7588 if (cmd->duplex != DUPLEX_FULL) {
7589 DP(NETIF_MSG_LINK, "10G half not supported\n");
7590 return -EINVAL;
7591 }
7592
7593 if (!(bp->port.supported & SUPPORTED_10000baseT_Full)) {
7594 DP(NETIF_MSG_LINK, "10G full not supported\n");
7595 return -EINVAL;
7596 }
7597
7598 advertising = (ADVERTISED_10000baseT_Full |
7599 ADVERTISED_FIBRE);
7600 break;
7601
7602 default:
7603 DP(NETIF_MSG_LINK, "Unsupported speed\n");
7604 return -EINVAL;
7605 }
7606
7607 bp->link_params.req_line_speed = cmd->speed;
7608 bp->link_params.req_duplex = cmd->duplex;
7609 bp->port.advertising = advertising;
7610 }
7611
7612 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
7613 DP_LEVEL " req_duplex %d advertising 0x%x\n",
7614 bp->link_params.req_line_speed, bp->link_params.req_duplex,
7615 bp->port.advertising);
7616
7617 if (netif_running(dev)) {
7618 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
7619 bnx2x_link_set(bp);
7620 }
7621
7622 return 0;
7623}
7624
7625#define PHY_FW_VER_LEN 10
7626
7627static void bnx2x_get_drvinfo(struct net_device *dev,
7628 struct ethtool_drvinfo *info)
7629{
7630 struct bnx2x *bp = netdev_priv(dev);
7631 char phy_fw_ver[PHY_FW_VER_LEN];
7632
7633 strcpy(info->driver, DRV_MODULE_NAME);
7634 strcpy(info->version, DRV_MODULE_VERSION);
7635
7636 phy_fw_ver[0] = '\0';
7637 if (bp->port.pmf) {
7638 bnx2x_phy_hw_lock(bp);
7639 bnx2x_get_ext_phy_fw_version(&bp->link_params,
7640 (bp->state != BNX2X_STATE_CLOSED),
7641 phy_fw_ver, PHY_FW_VER_LEN);
7642 bnx2x_phy_hw_unlock(bp);
7643 }
7644
7645 snprintf(info->fw_version, 32, "%d.%d.%d:%d BC:%x%s%s",
7646 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION,
7647 BCM_5710_FW_REVISION_VERSION,
7648 BCM_5710_FW_COMPILE_FLAGS, bp->common.bc_ver,
7649 ((phy_fw_ver[0] != '\0')? " PHY:":""), phy_fw_ver);
7650 strcpy(info->bus_info, pci_name(bp->pdev));
7651 info->n_stats = BNX2X_NUM_STATS;
7652 info->testinfo_len = BNX2X_NUM_TESTS;
7653 info->eedump_len = bp->common.flash_size;
7654 info->regdump_len = 0;
7655}
7656
7657static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7658{
7659 struct bnx2x *bp = netdev_priv(dev);
7660
7661 if (bp->flags & NO_WOL_FLAG) {
7662 wol->supported = 0;
7663 wol->wolopts = 0;
7664 } else {
7665 wol->supported = WAKE_MAGIC;
7666 if (bp->wol)
7667 wol->wolopts = WAKE_MAGIC;
7668 else
7669 wol->wolopts = 0;
7670 }
7671 memset(&wol->sopass, 0, sizeof(wol->sopass));
7672}
7673
7674static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7675{
7676 struct bnx2x *bp = netdev_priv(dev);
7677
7678 if (wol->wolopts & ~WAKE_MAGIC)
7679 return -EINVAL;
7680
7681 if (wol->wolopts & WAKE_MAGIC) {
7682 if (bp->flags & NO_WOL_FLAG)
7683 return -EINVAL;
7684
7685 bp->wol = 1;
7686 } else
7687 bp->wol = 0;
7688
7689 return 0;
7690}
7691
7692static u32 bnx2x_get_msglevel(struct net_device *dev)
7693{
7694 struct bnx2x *bp = netdev_priv(dev);
7695
7696 return bp->msglevel;
7697}
7698
7699static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
7700{
7701 struct bnx2x *bp = netdev_priv(dev);
7702
7703 if (capable(CAP_NET_ADMIN))
7704 bp->msglevel = level;
7705}
7706
7707static int bnx2x_nway_reset(struct net_device *dev)
7708{
7709 struct bnx2x *bp = netdev_priv(dev);
7710
7711 if (!bp->port.pmf)
7712 return 0;
7713
7714 if (netif_running(dev)) {
7715 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
7716 bnx2x_link_set(bp);
7717 }
7718
7719 return 0;
7720}
7721
7722static int bnx2x_get_eeprom_len(struct net_device *dev)
7723{
7724 struct bnx2x *bp = netdev_priv(dev);
7725
7726 return bp->common.flash_size;
7727}
7728
7729static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
7730{
7731 int port = BP_PORT(bp);
7732 int count, i;
7733 u32 val = 0;
7734
7735 /* adjust timeout for emulation/FPGA */
7736 count = NVRAM_TIMEOUT_COUNT;
7737 if (CHIP_REV_IS_SLOW(bp))
7738 count *= 100;
7739
7740 /* request access to nvram interface */
7741 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
7742 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
7743
7744 for (i = 0; i < count*10; i++) {
7745 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
7746 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
7747 break;
7748
7749 udelay(5);
7750 }
7751
7752 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
7753 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
7754 return -EBUSY;
7755 }
7756
7757 return 0;
7758}
7759
7760static int bnx2x_release_nvram_lock(struct bnx2x *bp)
7761{
7762 int port = BP_PORT(bp);
7763 int count, i;
7764 u32 val = 0;
7765
7766 /* adjust timeout for emulation/FPGA */
7767 count = NVRAM_TIMEOUT_COUNT;
7768 if (CHIP_REV_IS_SLOW(bp))
7769 count *= 100;
7770
7771 /* relinquish nvram interface */
7772 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
7773 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
7774
7775 for (i = 0; i < count*10; i++) {
7776 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
7777 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
7778 break;
7779
7780 udelay(5);
7781 }
7782
7783 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
7784 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
7785 return -EBUSY;
7786 }
7787
7788 return 0;
7789}
7790
7791static void bnx2x_enable_nvram_access(struct bnx2x *bp)
7792{
7793 u32 val;
7794
7795 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
7796
7797 /* enable both bits, even on read */
7798 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
7799 (val | MCPR_NVM_ACCESS_ENABLE_EN |
7800 MCPR_NVM_ACCESS_ENABLE_WR_EN));
7801}
7802
7803static void bnx2x_disable_nvram_access(struct bnx2x *bp)
7804{
7805 u32 val;
7806
7807 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
7808
7809 /* disable both bits, even after read */
7810 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
7811 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
7812 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
7813}
7814
7815static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, u32 *ret_val,
7816 u32 cmd_flags)
7817{
7818 int count, i, rc;
7819 u32 val;
7820
7821 /* build the command word */
7822 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
7823
7824 /* need to clear DONE bit separately */
7825 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
7826
7827 /* address of the NVRAM to read from */
7828 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
7829 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
7830
7831 /* issue a read command */
7832 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
7833
7834 /* adjust timeout for emulation/FPGA */
7835 count = NVRAM_TIMEOUT_COUNT;
7836 if (CHIP_REV_IS_SLOW(bp))
7837 count *= 100;
7838
7839 /* wait for completion */
7840 *ret_val = 0;
7841 rc = -EBUSY;
7842 for (i = 0; i < count; i++) {
7843 udelay(5);
7844 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
7845
7846 if (val & MCPR_NVM_COMMAND_DONE) {
7847 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
7848 /* we read nvram data in cpu order
7849 * but ethtool sees it as an array of bytes
7850 * converting to big-endian will do the work */
7851 val = cpu_to_be32(val);
7852 *ret_val = val;
7853 rc = 0;
7854 break;
7855 }
7856 }
7857
7858 return rc;
7859}
7860
7861static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
7862 int buf_size)
7863{
7864 int rc;
7865 u32 cmd_flags;
7866 u32 val;
7867
7868 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
7869 DP(BNX2X_MSG_NVM,
7870 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
7871 offset, buf_size);
7872 return -EINVAL;
7873 }
7874
7875 if (offset + buf_size > bp->common.flash_size) {
7876 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
7877 " buf_size (0x%x) > flash_size (0x%x)\n",
7878 offset, buf_size, bp->common.flash_size);
7879 return -EINVAL;
7880 }
7881
7882 /* request access to nvram interface */
7883 rc = bnx2x_acquire_nvram_lock(bp);
7884 if (rc)
7885 return rc;
7886
7887 /* enable access to nvram interface */
7888 bnx2x_enable_nvram_access(bp);
7889
7890 /* read the first word(s) */
7891 cmd_flags = MCPR_NVM_COMMAND_FIRST;
7892 while ((buf_size > sizeof(u32)) && (rc == 0)) {
7893 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
7894 memcpy(ret_buf, &val, 4);
7895
7896 /* advance to the next dword */
7897 offset += sizeof(u32);
7898 ret_buf += sizeof(u32);
7899 buf_size -= sizeof(u32);
7900 cmd_flags = 0;
7901 }
7902
7903 if (rc == 0) {
7904 cmd_flags |= MCPR_NVM_COMMAND_LAST;
7905 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
7906 memcpy(ret_buf, &val, 4);
7907 }
7908
7909 /* disable access to nvram interface */
7910 bnx2x_disable_nvram_access(bp);
7911 bnx2x_release_nvram_lock(bp);
7912
7913 return rc;
7914}
7915
7916static int bnx2x_get_eeprom(struct net_device *dev,
7917 struct ethtool_eeprom *eeprom, u8 *eebuf)
7918{
7919 struct bnx2x *bp = netdev_priv(dev);
7920 int rc;
7921
7922 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
7923 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
7924 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
7925 eeprom->len, eeprom->len);
7926
7927 /* parameters already validated in ethtool_get_eeprom */
7928
7929 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7930
7931 return rc;
7932}
7933
7934static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
7935 u32 cmd_flags)
7936{
7937 int count, i, rc;
7938
7939 /* build the command word */
7940 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
7941
7942 /* need to clear DONE bit separately */
7943 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
7944
7945 /* write the data */
7946 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
7947
7948 /* address of the NVRAM to write to */
7949 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
7950 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
7951
7952 /* issue the write command */
7953 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
7954
7955 /* adjust timeout for emulation/FPGA */
7956 count = NVRAM_TIMEOUT_COUNT;
7957 if (CHIP_REV_IS_SLOW(bp))
7958 count *= 100;
7959
7960 /* wait for completion */
7961 rc = -EBUSY;
7962 for (i = 0; i < count; i++) {
7963 udelay(5);
7964 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
7965 if (val & MCPR_NVM_COMMAND_DONE) {
7966 rc = 0;
7967 break;
7968 }
7969 }
7970
7971 return rc;
7972}
7973
7974#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
7975
7976static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
7977 int buf_size)
7978{
7979 int rc;
7980 u32 cmd_flags;
7981 u32 align_offset;
7982 u32 val;
7983
7984 if (offset + buf_size > bp->common.flash_size) {
7985 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
7986 " buf_size (0x%x) > flash_size (0x%x)\n",
7987 offset, buf_size, bp->common.flash_size);
7988 return -EINVAL;
7989 }
7990
7991 /* request access to nvram interface */
7992 rc = bnx2x_acquire_nvram_lock(bp);
7993 if (rc)
7994 return rc;
7995
7996 /* enable access to nvram interface */
7997 bnx2x_enable_nvram_access(bp);
7998
7999 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
8000 align_offset = (offset & ~0x03);
8001 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
8002
8003 if (rc == 0) {
8004 val &= ~(0xff << BYTE_OFFSET(offset));
8005 val |= (*data_buf << BYTE_OFFSET(offset));
8006
8007 /* nvram data is returned as an array of bytes
8008 * convert it back to cpu order */
8009 val = be32_to_cpu(val);
8010
8011 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
8012 cmd_flags);
8013 }
8014
8015 /* disable access to nvram interface */
8016 bnx2x_disable_nvram_access(bp);
8017 bnx2x_release_nvram_lock(bp);
8018
8019 return rc;
8020}
8021
8022static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
8023 int buf_size)
8024{
8025 int rc;
8026 u32 cmd_flags;
8027 u32 val;
8028 u32 written_so_far;
8029
8030 if (buf_size == 1) /* ethtool */
8031 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
8032
8033 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
8034 DP(BNX2X_MSG_NVM,
8035 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
8036 offset, buf_size);
8037 return -EINVAL;
8038 }
8039
8040 if (offset + buf_size > bp->common.flash_size) {
8041 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8042 " buf_size (0x%x) > flash_size (0x%x)\n",
8043 offset, buf_size, bp->common.flash_size);
8044 return -EINVAL;
8045 }
8046
8047 /* request access to nvram interface */
8048 rc = bnx2x_acquire_nvram_lock(bp);
8049 if (rc)
8050 return rc;
8051
8052 /* enable access to nvram interface */
8053 bnx2x_enable_nvram_access(bp);
8054
8055 written_so_far = 0;
8056 cmd_flags = MCPR_NVM_COMMAND_FIRST;
8057 while ((written_so_far < buf_size) && (rc == 0)) {
8058 if (written_so_far == (buf_size - sizeof(u32)))
8059 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8060 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
8061 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8062 else if ((offset % NVRAM_PAGE_SIZE) == 0)
8063 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
8064
8065 memcpy(&val, data_buf, 4);
8066
8067 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
8068
8069 /* advance to the next dword */
8070 offset += sizeof(u32);
8071 data_buf += sizeof(u32);
8072 written_so_far += sizeof(u32);
8073 cmd_flags = 0;
8074 }
8075
8076 /* disable access to nvram interface */
8077 bnx2x_disable_nvram_access(bp);
8078 bnx2x_release_nvram_lock(bp);
8079
8080 return rc;
8081}
8082
8083static int bnx2x_set_eeprom(struct net_device *dev,
8084 struct ethtool_eeprom *eeprom, u8 *eebuf)
8085{
8086 struct bnx2x *bp = netdev_priv(dev);
8087 int rc;
8088
8089 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
8090 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
8091 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
8092 eeprom->len, eeprom->len);
8093
8094 /* parameters already validated in ethtool_set_eeprom */
8095
8096 /* If the magic number is PHY (0x00504859) upgrade the PHY FW */
8097 if (eeprom->magic == 0x00504859)
8098 if (bp->port.pmf) {
8099
8100 bnx2x_phy_hw_lock(bp);
8101 rc = bnx2x_flash_download(bp, BP_PORT(bp),
8102 bp->link_params.ext_phy_config,
8103 (bp->state != BNX2X_STATE_CLOSED),
8104 eebuf, eeprom->len);
8105 if ((bp->state == BNX2X_STATE_OPEN) ||
8106 (bp->state == BNX2X_STATE_DISABLED)) {
8107 rc |= bnx2x_link_reset(&bp->link_params,
8108 &bp->link_vars);
8109 rc |= bnx2x_phy_init(&bp->link_params,
8110 &bp->link_vars);
8111 }
8112 bnx2x_phy_hw_unlock(bp);
8113
8114 } else /* Only the PMF can access the PHY */
8115 return -EINVAL;
8116 else
8117 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
8118
8119 return rc;
8120}
8121
8122static int bnx2x_get_coalesce(struct net_device *dev,
8123 struct ethtool_coalesce *coal)
8124{
8125 struct bnx2x *bp = netdev_priv(dev);
8126
8127 memset(coal, 0, sizeof(struct ethtool_coalesce));
8128
8129 coal->rx_coalesce_usecs = bp->rx_ticks;
8130 coal->tx_coalesce_usecs = bp->tx_ticks;
8131 coal->stats_block_coalesce_usecs = bp->stats_ticks;
8132
8133 return 0;
8134}
8135
8136static int bnx2x_set_coalesce(struct net_device *dev,
8137 struct ethtool_coalesce *coal)
8138{
8139 struct bnx2x *bp = netdev_priv(dev);
8140
8141 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
8142 if (bp->rx_ticks > 3000)
8143 bp->rx_ticks = 3000;
8144
8145 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
8146 if (bp->tx_ticks > 0x3000)
8147 bp->tx_ticks = 0x3000;
8148
8149 bp->stats_ticks = coal->stats_block_coalesce_usecs;
8150 if (bp->stats_ticks > 0xffff00)
8151 bp->stats_ticks = 0xffff00;
8152 bp->stats_ticks &= 0xffff00;
8153
8154 if (netif_running(dev))
8155 bnx2x_update_coalesce(bp);
8156
8157 return 0;
8158}
8159
8160static int bnx2x_set_flags(struct net_device *dev, u32 data)
8161{
8162 struct bnx2x *bp = netdev_priv(dev);
8163 int changed = 0;
8164 int rc = 0;
8165
8166 if (data & ETH_FLAG_LRO) {
8167 if (!(dev->features & NETIF_F_LRO)) {
8168 dev->features |= NETIF_F_LRO;
8169 bp->flags |= TPA_ENABLE_FLAG;
8170 changed = 1;
8171 }
8172
8173 } else if (dev->features & NETIF_F_LRO) {
8174 dev->features &= ~NETIF_F_LRO;
8175 bp->flags &= ~TPA_ENABLE_FLAG;
8176 changed = 1;
8177 }
8178
8179 if (changed && netif_running(dev)) {
8180 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8181 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
8182 }
8183
8184 return rc;
8185}
8186
8187static void bnx2x_get_ringparam(struct net_device *dev,
8188 struct ethtool_ringparam *ering)
8189{
8190 struct bnx2x *bp = netdev_priv(dev);
8191
8192 ering->rx_max_pending = MAX_RX_AVAIL;
8193 ering->rx_mini_max_pending = 0;
8194 ering->rx_jumbo_max_pending = 0;
8195
8196 ering->rx_pending = bp->rx_ring_size;
8197 ering->rx_mini_pending = 0;
8198 ering->rx_jumbo_pending = 0;
8199
8200 ering->tx_max_pending = MAX_TX_AVAIL;
8201 ering->tx_pending = bp->tx_ring_size;
8202}
8203
8204static int bnx2x_set_ringparam(struct net_device *dev,
8205 struct ethtool_ringparam *ering)
8206{
8207 struct bnx2x *bp = netdev_priv(dev);
8208 int rc = 0;
8209
8210 if ((ering->rx_pending > MAX_RX_AVAIL) ||
8211 (ering->tx_pending > MAX_TX_AVAIL) ||
8212 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
8213 return -EINVAL;
8214
8215 bp->rx_ring_size = ering->rx_pending;
8216 bp->tx_ring_size = ering->tx_pending;
8217
8218 if (netif_running(dev)) {
8219 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8220 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
8221 }
8222
8223 return rc;
8224}
8225
8226static void bnx2x_get_pauseparam(struct net_device *dev,
8227 struct ethtool_pauseparam *epause)
8228{
8229 struct bnx2x *bp = netdev_priv(dev);
8230
8231 epause->autoneg = (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
8232 (bp->link_params.req_line_speed == SPEED_AUTO_NEG);
8233
8234 epause->rx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_RX) ==
8235 FLOW_CTRL_RX);
8236 epause->tx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_TX) ==
8237 FLOW_CTRL_TX);
8238
8239 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
8240 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
8241 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
8242}
8243
8244static int bnx2x_set_pauseparam(struct net_device *dev,
8245 struct ethtool_pauseparam *epause)
8246{
8247 struct bnx2x *bp = netdev_priv(dev);
8248
8249 if (IS_E1HMF(bp))
8250 return 0;
8251
8252 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
8253 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
8254 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
8255
8256 bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO;
8257
8258 if (epause->rx_pause)
8259 bp->link_params.req_flow_ctrl |= FLOW_CTRL_RX;
8260
8261 if (epause->tx_pause)
8262 bp->link_params.req_flow_ctrl |= FLOW_CTRL_TX;
8263
8264 if (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO)
8265 bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
8266
8267 if (epause->autoneg) {
8268 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
8269 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
8270 return -EINVAL;
8271 }
8272
8273 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
8274 bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO;
8275 }
8276
8277 DP(NETIF_MSG_LINK,
8278 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl);
8279
8280 if (netif_running(dev)) {
8281 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
8282 bnx2x_link_set(bp);
8283 }
8284
8285 return 0;
8286}
8287
8288static u32 bnx2x_get_rx_csum(struct net_device *dev)
8289{
8290 struct bnx2x *bp = netdev_priv(dev);
8291
8292 return bp->rx_csum;
8293}
8294
8295static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
8296{
8297 struct bnx2x *bp = netdev_priv(dev);
8298
8299 bp->rx_csum = data;
8300 return 0;
8301}
8302
8303static int bnx2x_set_tso(struct net_device *dev, u32 data)
8304{
8305 if (data) {
8306 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
8307 dev->features |= NETIF_F_TSO6;
8308 } else {
8309 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
8310 dev->features &= ~NETIF_F_TSO6;
8311 }
8312
8313 return 0;
8314}
8315
8316static const struct {
8317 char string[ETH_GSTRING_LEN];
8318} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
8319 { "register_test (offline)" },
8320 { "memory_test (offline)" },
8321 { "loopback_test (offline)" },
8322 { "nvram_test (online)" },
8323 { "interrupt_test (online)" },
8324 { "link_test (online)" },
8325 { "idle check (online)" },
8326 { "MC errors (online)" }
8327};
8328
8329static int bnx2x_self_test_count(struct net_device *dev)
8330{
8331 return BNX2X_NUM_TESTS;
8332}
8333
8334static int bnx2x_test_registers(struct bnx2x *bp)
8335{
8336 int idx, i, rc = -ENODEV;
8337 u32 wr_val = 0;
8338 static const struct {
8339 u32 offset0;
8340 u32 offset1;
8341 u32 mask;
8342 } reg_tbl[] = {
8343/* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
8344 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
8345 { HC_REG_AGG_INT_0, 4, 0x000003ff },
8346 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
8347 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
8348 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
8349 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
8350 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
8351 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
8352 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
8353/* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
8354 { QM_REG_CONNNUM_0, 4, 0x000fffff },
8355 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
8356 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
8357 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
8358 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
8359 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
8360 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
8361 { NIG_REG_EGRESS_MNG0_FIFO, 20, 0xffffffff },
8362 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
8363/* 20 */ { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
8364 { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
8365 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
8366 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
8367 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
8368 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
8369 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
8370 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
8371 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
8372 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
8373/* 30 */ { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
8374 { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
8375 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
8376 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
8377 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
8378 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
8379 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
8380 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
8381
8382 { 0xffffffff, 0, 0x00000000 }
8383 };
8384
8385 if (!netif_running(bp->dev))
8386 return rc;
8387
8388 /* Repeat the test twice:
8389 First by writing 0x00000000, second by writing 0xffffffff */
8390 for (idx = 0; idx < 2; idx++) {
8391
8392 switch (idx) {
8393 case 0:
8394 wr_val = 0;
8395 break;
8396 case 1:
8397 wr_val = 0xffffffff;
8398 break;
8399 }
8400
8401 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
8402 u32 offset, mask, save_val, val;
8403 int port = BP_PORT(bp);
8404
8405 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
8406 mask = reg_tbl[i].mask;
8407
8408 save_val = REG_RD(bp, offset);
8409
8410 REG_WR(bp, offset, wr_val);
8411 val = REG_RD(bp, offset);
8412
8413 /* Restore the original register's value */
8414 REG_WR(bp, offset, save_val);
8415
8416 /* verify that value is as expected value */
8417 if ((val & mask) != (wr_val & mask))
8418 goto test_reg_exit;
8419 }
8420 }
8421
8422 rc = 0;
8423
8424test_reg_exit:
8425 return rc;
8426}
8427
8428static int bnx2x_test_memory(struct bnx2x *bp)
8429{
8430 int i, j, rc = -ENODEV;
8431 u32 val;
8432 static const struct {
8433 u32 offset;
8434 int size;
8435 } mem_tbl[] = {
8436 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
8437 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
8438 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
8439 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
8440 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
8441 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
8442 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
8443
8444 { 0xffffffff, 0 }
8445 };
8446 static const struct {
8447 char *name;
8448 u32 offset;
8449 u32 mask;
8450 } prty_tbl[] = {
8451 { "CCM_REG_CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0 },
8452 { "CFC_REG_CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0 },
8453 { "DMAE_REG_DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0 },
8454 { "TCM_REG_TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0 },
8455 { "UCM_REG_UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0 },
8456 { "XCM_REG_XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x1 },
8457
8458 { NULL, 0xffffffff, 0 }
8459 };
8460
8461 if (!netif_running(bp->dev))
8462 return rc;
8463
8464 /* Go through all the memories */
8465 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
8466 for (j = 0; j < mem_tbl[i].size; j++)
8467 REG_RD(bp, mem_tbl[i].offset + j*4);
8468
8469 /* Check the parity status */
8470 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
8471 val = REG_RD(bp, prty_tbl[i].offset);
8472 if (val & ~(prty_tbl[i].mask)) {
8473 DP(NETIF_MSG_HW,
8474 "%s is 0x%x\n", prty_tbl[i].name, val);
8475 goto test_mem_exit;
8476 }
8477 }
8478
8479 rc = 0;
8480
8481test_mem_exit:
8482 return rc;
8483}
8484
8485static void bnx2x_netif_start(struct bnx2x *bp)
8486{
8487 int i;
8488
8489 if (atomic_dec_and_test(&bp->intr_sem)) {
8490 if (netif_running(bp->dev)) {
8491 bnx2x_int_enable(bp);
8492 for_each_queue(bp, i)
8493 napi_enable(&bnx2x_fp(bp, i, napi));
8494 if (bp->state == BNX2X_STATE_OPEN)
8495 netif_wake_queue(bp->dev);
8496 }
8497 }
8498}
8499
8500static void bnx2x_netif_stop(struct bnx2x *bp)
8501{
8502 int i;
8503
8504 if (netif_running(bp->dev)) {
8505 netif_tx_disable(bp->dev);
8506 bp->dev->trans_start = jiffies; /* prevent tx timeout */
8507 for_each_queue(bp, i)
8508 napi_disable(&bnx2x_fp(bp, i, napi));
8509 }
8510 bnx2x_int_disable_sync(bp);
8511}
8512
8513static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up)
8514{
8515 int cnt = 1000;
8516
8517 if (link_up)
8518 while (bnx2x_link_test(bp) && cnt--)
8519 msleep(10);
8520}
8521
8522static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
8523{
8524 unsigned int pkt_size, num_pkts, i;
8525 struct sk_buff *skb;
8526 unsigned char *packet;
8527 struct bnx2x_fastpath *fp = &bp->fp[0];
8528 u16 tx_start_idx, tx_idx;
8529 u16 rx_start_idx, rx_idx;
8530 u16 pkt_prod;
8531 struct sw_tx_bd *tx_buf;
8532 struct eth_tx_bd *tx_bd;
8533 dma_addr_t mapping;
8534 union eth_rx_cqe *cqe;
8535 u8 cqe_fp_flags;
8536 struct sw_rx_bd *rx_buf;
8537 u16 len;
8538 int rc = -ENODEV;
8539
8540 if (loopback_mode == BNX2X_MAC_LOOPBACK) {
8541 bp->link_params.loopback_mode = LOOPBACK_BMAC;
8542 bnx2x_phy_hw_lock(bp);
8543 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8544 bnx2x_phy_hw_unlock(bp);
8545
8546 } else if (loopback_mode == BNX2X_PHY_LOOPBACK) {
8547 bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
8548 bnx2x_phy_hw_lock(bp);
8549 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8550 bnx2x_phy_hw_unlock(bp);
8551 /* wait until link state is restored */
8552 bnx2x_wait_for_link(bp, link_up);
8553
8554 } else
8555 return -EINVAL;
8556
8557 pkt_size = 1514;
8558 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
8559 if (!skb) {
8560 rc = -ENOMEM;
8561 goto test_loopback_exit;
8562 }
8563 packet = skb_put(skb, pkt_size);
8564 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
8565 memset(packet + ETH_ALEN, 0, (ETH_HLEN - ETH_ALEN));
8566 for (i = ETH_HLEN; i < pkt_size; i++)
8567 packet[i] = (unsigned char) (i & 0xff);
8568
8569 num_pkts = 0;
8570 tx_start_idx = le16_to_cpu(*fp->tx_cons_sb);
8571 rx_start_idx = le16_to_cpu(*fp->rx_cons_sb);
8572
8573 pkt_prod = fp->tx_pkt_prod++;
8574 tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
8575 tx_buf->first_bd = fp->tx_bd_prod;
8576 tx_buf->skb = skb;
8577
8578 tx_bd = &fp->tx_desc_ring[TX_BD(fp->tx_bd_prod)];
8579 mapping = pci_map_single(bp->pdev, skb->data,
8580 skb_headlen(skb), PCI_DMA_TODEVICE);
8581 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
8582 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
8583 tx_bd->nbd = cpu_to_le16(1);
8584 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
8585 tx_bd->vlan = cpu_to_le16(pkt_prod);
8586 tx_bd->bd_flags.as_bitfield = (ETH_TX_BD_FLAGS_START_BD |
8587 ETH_TX_BD_FLAGS_END_BD);
8588 tx_bd->general_data = ((UNICAST_ADDRESS <<
8589 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT) | 1);
8590
8591 fp->hw_tx_prods->bds_prod =
8592 cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + 1);
8593 mb(); /* FW restriction: must not reorder writing nbd and packets */
8594 fp->hw_tx_prods->packets_prod =
8595 cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1);
8596 DOORBELL(bp, FP_IDX(fp), 0);
8597
8598 mmiowb();
8599
8600 num_pkts++;
8601 fp->tx_bd_prod++;
8602 bp->dev->trans_start = jiffies;
8603
8604 udelay(100);
8605
8606 tx_idx = le16_to_cpu(*fp->tx_cons_sb);
8607 if (tx_idx != tx_start_idx + num_pkts)
8608 goto test_loopback_exit;
8609
8610 rx_idx = le16_to_cpu(*fp->rx_cons_sb);
8611 if (rx_idx != rx_start_idx + num_pkts)
8612 goto test_loopback_exit;
8613
8614 cqe = &fp->rx_comp_ring[RCQ_BD(fp->rx_comp_cons)];
8615 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
8616 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
8617 goto test_loopback_rx_exit;
8618
8619 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
8620 if (len != pkt_size)
8621 goto test_loopback_rx_exit;
8622
8623 rx_buf = &fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)];
8624 skb = rx_buf->skb;
8625 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
8626 for (i = ETH_HLEN; i < pkt_size; i++)
8627 if (*(skb->data + i) != (unsigned char) (i & 0xff))
8628 goto test_loopback_rx_exit;
8629
8630 rc = 0;
8631
8632test_loopback_rx_exit:
8633 bp->dev->last_rx = jiffies;
8634
8635 fp->rx_bd_cons = NEXT_RX_IDX(fp->rx_bd_cons);
8636 fp->rx_bd_prod = NEXT_RX_IDX(fp->rx_bd_prod);
8637 fp->rx_comp_cons = NEXT_RCQ_IDX(fp->rx_comp_cons);
8638 fp->rx_comp_prod = NEXT_RCQ_IDX(fp->rx_comp_prod);
8639
8640 /* Update producers */
8641 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
8642 fp->rx_sge_prod);
8643 mmiowb(); /* keep prod updates ordered */
8644
8645test_loopback_exit:
8646 bp->link_params.loopback_mode = LOOPBACK_NONE;
8647
8648 return rc;
8649}
8650
8651static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
8652{
8653 int rc = 0;
8654
8655 if (!netif_running(bp->dev))
8656 return BNX2X_LOOPBACK_FAILED;
8657
8658 bnx2x_netif_stop(bp);
8659
8660 if (bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up)) {
8661 DP(NETIF_MSG_PROBE, "MAC loopback failed\n");
8662 rc |= BNX2X_MAC_LOOPBACK_FAILED;
8663 }
8664
8665 if (bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up)) {
8666 DP(NETIF_MSG_PROBE, "PHY loopback failed\n");
8667 rc |= BNX2X_PHY_LOOPBACK_FAILED;
8668 }
8669
8670 bnx2x_netif_start(bp);
8671
8672 return rc;
8673}
8674
8675#define CRC32_RESIDUAL 0xdebb20e3
8676
8677static int bnx2x_test_nvram(struct bnx2x *bp)
8678{
8679 static const struct {
8680 int offset;
8681 int size;
8682 } nvram_tbl[] = {
8683 { 0, 0x14 }, /* bootstrap */
8684 { 0x14, 0xec }, /* dir */
8685 { 0x100, 0x350 }, /* manuf_info */
8686 { 0x450, 0xf0 }, /* feature_info */
8687 { 0x640, 0x64 }, /* upgrade_key_info */
8688 { 0x6a4, 0x64 },
8689 { 0x708, 0x70 }, /* manuf_key_info */
8690 { 0x778, 0x70 },
8691 { 0, 0 }
8692 };
8693 u32 buf[0x350 / 4];
8694 u8 *data = (u8 *)buf;
8695 int i, rc;
8696 u32 magic, csum;
8697
8698 rc = bnx2x_nvram_read(bp, 0, data, 4);
8699 if (rc) {
8700 DP(NETIF_MSG_PROBE, "magic value read (rc -%d)\n", -rc);
8701 goto test_nvram_exit;
8702 }
8703
8704 magic = be32_to_cpu(buf[0]);
8705 if (magic != 0x669955aa) {
8706 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
8707 rc = -ENODEV;
8708 goto test_nvram_exit;
8709 }
8710
8711 for (i = 0; nvram_tbl[i].size; i++) {
8712
8713 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
8714 nvram_tbl[i].size);
8715 if (rc) {
8716 DP(NETIF_MSG_PROBE,
8717 "nvram_tbl[%d] read data (rc -%d)\n", i, -rc);
8718 goto test_nvram_exit;
8719 }
8720
8721 csum = ether_crc_le(nvram_tbl[i].size, data);
8722 if (csum != CRC32_RESIDUAL) {
8723 DP(NETIF_MSG_PROBE,
8724 "nvram_tbl[%d] csum value (0x%08x)\n", i, csum);
8725 rc = -ENODEV;
8726 goto test_nvram_exit;
8727 }
8728 }
8729
8730test_nvram_exit:
8731 return rc;
8732}
8733
8734static int bnx2x_test_intr(struct bnx2x *bp)
8735{
8736 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
8737 int i, rc;
8738
8739 if (!netif_running(bp->dev))
8740 return -ENODEV;
8741
8742 config->hdr.length_6b = 0;
8743 config->hdr.offset = 0;
8744 config->hdr.client_id = BP_CL_ID(bp);
8745 config->hdr.reserved1 = 0;
8746
8747 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
8748 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
8749 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
8750 if (rc == 0) {
8751 bp->set_mac_pending++;
8752 for (i = 0; i < 10; i++) {
8753 if (!bp->set_mac_pending)
8754 break;
8755 msleep_interruptible(10);
8756 }
8757 if (i == 10)
8758 rc = -ENODEV;
8759 }
8760
8761 return rc;
8762}
8763
8764static void bnx2x_self_test(struct net_device *dev,
8765 struct ethtool_test *etest, u64 *buf)
8766{
8767 struct bnx2x *bp = netdev_priv(dev);
8768
8769 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
8770
8771 if (!netif_running(dev))
8772 return;
8773
8774 /* offline tests are not suppoerted in MF mode */
8775 if (IS_E1HMF(bp))
8776 etest->flags &= ~ETH_TEST_FL_OFFLINE;
8777
8778 if (etest->flags & ETH_TEST_FL_OFFLINE) {
8779 u8 link_up;
8780
8781 link_up = bp->link_vars.link_up;
8782 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8783 bnx2x_nic_load(bp, LOAD_DIAG);
8784 /* wait until link state is restored */
8785 bnx2x_wait_for_link(bp, link_up);
8786
8787 if (bnx2x_test_registers(bp) != 0) {
8788 buf[0] = 1;
8789 etest->flags |= ETH_TEST_FL_FAILED;
8790 }
8791 if (bnx2x_test_memory(bp) != 0) {
8792 buf[1] = 1;
8793 etest->flags |= ETH_TEST_FL_FAILED;
8794 }
8795 buf[2] = bnx2x_test_loopback(bp, link_up);
8796 if (buf[2] != 0)
8797 etest->flags |= ETH_TEST_FL_FAILED;
8798
8799 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8800 bnx2x_nic_load(bp, LOAD_NORMAL);
8801 /* wait until link state is restored */
8802 bnx2x_wait_for_link(bp, link_up);
8803 }
8804 if (bnx2x_test_nvram(bp) != 0) {
8805 buf[3] = 1;
8806 etest->flags |= ETH_TEST_FL_FAILED;
8807 }
8808 if (bnx2x_test_intr(bp) != 0) {
8809 buf[4] = 1;
8810 etest->flags |= ETH_TEST_FL_FAILED;
8811 }
8812 if (bp->port.pmf)
8813 if (bnx2x_link_test(bp) != 0) {
8814 buf[5] = 1;
8815 etest->flags |= ETH_TEST_FL_FAILED;
8816 }
8817 buf[7] = bnx2x_mc_assert(bp);
8818 if (buf[7] != 0)
8819 etest->flags |= ETH_TEST_FL_FAILED;
8820
8821#ifdef BNX2X_EXTRA_DEBUG
8822 bnx2x_panic_dump(bp);
8823#endif
8824}
8825
8826static const struct {
8827 long offset;
8828 int size;
8829 u32 flags;
8830 char string[ETH_GSTRING_LEN];
8831} bnx2x_stats_arr[BNX2X_NUM_STATS] = {
8832/* 1 */ { STATS_OFFSET32(valid_bytes_received_hi), 8, 1, "rx_bytes" },
8833 { STATS_OFFSET32(error_bytes_received_hi), 8, 1, "rx_error_bytes" },
8834 { STATS_OFFSET32(total_bytes_transmitted_hi), 8, 1, "tx_bytes" },
8835 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 8, 0, "tx_error_bytes" },
8836 { STATS_OFFSET32(total_unicast_packets_received_hi),
8837 8, 1, "rx_ucast_packets" },
8838 { STATS_OFFSET32(total_multicast_packets_received_hi),
8839 8, 1, "rx_mcast_packets" },
8840 { STATS_OFFSET32(total_broadcast_packets_received_hi),
8841 8, 1, "rx_bcast_packets" },
8842 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
8843 8, 1, "tx_packets" },
8844 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
8845 8, 0, "tx_mac_errors" },
8846/* 10 */{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
8847 8, 0, "tx_carrier_errors" },
8848 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
8849 8, 0, "rx_crc_errors" },
8850 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
8851 8, 0, "rx_align_errors" },
8852 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
8853 8, 0, "tx_single_collisions" },
8854 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
8855 8, 0, "tx_multi_collisions" },
8856 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
8857 8, 0, "tx_deferred" },
8858 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
8859 8, 0, "tx_excess_collisions" },
8860 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
8861 8, 0, "tx_late_collisions" },
8862 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
8863 8, 0, "tx_total_collisions" },
8864 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
8865 8, 0, "rx_fragments" },
8866/* 20 */{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 8, 0, "rx_jabbers" },
8867 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
8868 8, 0, "rx_undersize_packets" },
8869 { STATS_OFFSET32(jabber_packets_received),
8870 4, 1, "rx_oversize_packets" },
8871 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
8872 8, 0, "tx_64_byte_packets" },
8873 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
8874 8, 0, "tx_65_to_127_byte_packets" },
8875 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
8876 8, 0, "tx_128_to_255_byte_packets" },
8877 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
8878 8, 0, "tx_256_to_511_byte_packets" },
8879 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
8880 8, 0, "tx_512_to_1023_byte_packets" },
8881 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
8882 8, 0, "tx_1024_to_1522_byte_packets" },
8883 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
8884 8, 0, "tx_1523_to_9022_byte_packets" },
8885/* 30 */{ STATS_OFFSET32(rx_stat_xonpauseframesreceived_hi),
8886 8, 0, "rx_xon_frames" },
8887 { STATS_OFFSET32(rx_stat_xoffpauseframesreceived_hi),
8888 8, 0, "rx_xoff_frames" },
8889 { STATS_OFFSET32(tx_stat_outxonsent_hi), 8, 0, "tx_xon_frames" },
8890 { STATS_OFFSET32(tx_stat_outxoffsent_hi), 8, 0, "tx_xoff_frames" },
8891 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
8892 8, 0, "rx_mac_ctrl_frames" },
8893 { STATS_OFFSET32(mac_filter_discard), 4, 1, "rx_filtered_packets" },
8894 { STATS_OFFSET32(no_buff_discard), 4, 1, "rx_discards" },
8895 { STATS_OFFSET32(xxoverflow_discard), 4, 1, "rx_fw_discards" },
8896 { STATS_OFFSET32(brb_drop_hi), 8, 1, "brb_discard" },
8897/* 39 */{ STATS_OFFSET32(brb_truncate_discard), 8, 1, "brb_truncate" }
8898};
8899
8900static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
8901{
8902 struct bnx2x *bp = netdev_priv(dev);
8903 int i, j;
8904
8905 switch (stringset) {
8906 case ETH_SS_STATS:
8907 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
8908 if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags))
8909 continue;
8910 strcpy(buf + j*ETH_GSTRING_LEN,
8911 bnx2x_stats_arr[i].string);
8912 j++;
8913 }
8914 break;
8915
8916 case ETH_SS_TEST:
8917 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
8918 break;
8919 }
8920}
8921
8922static int bnx2x_get_stats_count(struct net_device *dev)
8923{
8924 struct bnx2x *bp = netdev_priv(dev);
8925 int i, num_stats = 0;
8926
8927 for (i = 0; i < BNX2X_NUM_STATS; i++) {
8928 if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags))
8929 continue;
8930 num_stats++;
8931 }
8932 return num_stats;
8933}
8934
8935static void bnx2x_get_ethtool_stats(struct net_device *dev,
8936 struct ethtool_stats *stats, u64 *buf)
8937{
8938 struct bnx2x *bp = netdev_priv(dev);
8939 u32 *hw_stats = (u32 *)&bp->eth_stats;
8940 int i, j;
8941
8942 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
8943 if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags))
8944 continue;
8945
8946 if (bnx2x_stats_arr[i].size == 0) {
8947 /* skip this counter */
8948 buf[j] = 0;
8949 j++;
8950 continue;
8951 }
8952 if (bnx2x_stats_arr[i].size == 4) {
8953 /* 4-byte counter */
8954 buf[j] = (u64) *(hw_stats + bnx2x_stats_arr[i].offset);
8955 j++;
8956 continue;
8957 }
8958 /* 8-byte counter */
8959 buf[j] = HILO_U64(*(hw_stats + bnx2x_stats_arr[i].offset),
8960 *(hw_stats + bnx2x_stats_arr[i].offset + 1));
8961 j++;
8962 }
8963}
8964
8965static int bnx2x_phys_id(struct net_device *dev, u32 data)
8966{
8967 struct bnx2x *bp = netdev_priv(dev);
8968 int port = BP_PORT(bp);
8969 int i;
8970
8971 if (!netif_running(dev))
8972 return 0;
8973
8974 if (!bp->port.pmf)
8975 return 0;
8976
8977 if (data == 0)
8978 data = 2;
8979
8980 for (i = 0; i < (data * 2); i++) {
8981 if ((i % 2) == 0)
8982 bnx2x_set_led(bp, port, LED_MODE_OPER, SPEED_1000,
8983 bp->link_params.hw_led_mode,
8984 bp->link_params.chip_id);
8985 else
8986 bnx2x_set_led(bp, port, LED_MODE_OFF, 0,
8987 bp->link_params.hw_led_mode,
8988 bp->link_params.chip_id);
8989
8990 msleep_interruptible(500);
8991 if (signal_pending(current))
8992 break;
8993 }
8994
8995 if (bp->link_vars.link_up)
8996 bnx2x_set_led(bp, port, LED_MODE_OPER,
8997 bp->link_vars.line_speed,
8998 bp->link_params.hw_led_mode,
8999 bp->link_params.chip_id);
9000
9001 return 0;
9002}
9003
9004static struct ethtool_ops bnx2x_ethtool_ops = {
9005 .get_settings = bnx2x_get_settings,
9006 .set_settings = bnx2x_set_settings,
9007 .get_drvinfo = bnx2x_get_drvinfo,
9008 .get_wol = bnx2x_get_wol,
9009 .set_wol = bnx2x_set_wol,
9010 .get_msglevel = bnx2x_get_msglevel,
9011 .set_msglevel = bnx2x_set_msglevel,
9012 .nway_reset = bnx2x_nway_reset,
9013 .get_link = ethtool_op_get_link,
9014 .get_eeprom_len = bnx2x_get_eeprom_len,
9015 .get_eeprom = bnx2x_get_eeprom,
9016 .set_eeprom = bnx2x_set_eeprom,
9017 .get_coalesce = bnx2x_get_coalesce,
9018 .set_coalesce = bnx2x_set_coalesce,
9019 .get_ringparam = bnx2x_get_ringparam,
9020 .set_ringparam = bnx2x_set_ringparam,
9021 .get_pauseparam = bnx2x_get_pauseparam,
9022 .set_pauseparam = bnx2x_set_pauseparam,
9023 .get_rx_csum = bnx2x_get_rx_csum,
9024 .set_rx_csum = bnx2x_set_rx_csum,
9025 .get_tx_csum = ethtool_op_get_tx_csum,
9026 .set_tx_csum = ethtool_op_set_tx_hw_csum,
9027 .set_flags = bnx2x_set_flags,
9028 .get_flags = ethtool_op_get_flags,
9029 .get_sg = ethtool_op_get_sg,
9030 .set_sg = ethtool_op_set_sg,
9031 .get_tso = ethtool_op_get_tso,
9032 .set_tso = bnx2x_set_tso,
9033 .self_test_count = bnx2x_self_test_count,
9034 .self_test = bnx2x_self_test,
9035 .get_strings = bnx2x_get_strings,
9036 .phys_id = bnx2x_phys_id,
9037 .get_stats_count = bnx2x_get_stats_count,
9038 .get_ethtool_stats = bnx2x_get_ethtool_stats,
9039};
9040
9041/* end of ethtool_ops */
9042
9043/****************************************************************************
9044* General service functions
9045****************************************************************************/
9046
9047static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
9048{
9049 u16 pmcsr;
9050
9051 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
9052
9053 switch (state) {
9054 case PCI_D0:
9055 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
9056 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
9057 PCI_PM_CTRL_PME_STATUS));
9058
9059 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
9060 /* delay required during transition out of D3hot */
9061 msleep(20);
9062 break;
9063
9064 case PCI_D3hot:
9065 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9066 pmcsr |= 3;
9067
9068 if (bp->wol)
9069 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
9070
9071 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
9072 pmcsr);
9073
9074 /* No more memory access after this point until
9075 * device is brought back to D0.
9076 */
9077 break;
9078
9079 default:
9080 return -EINVAL;
9081 }
9082 return 0;
9083}
9084
9085/*
9086 * net_device service functions
9087 */
9088
9089static int bnx2x_poll(struct napi_struct *napi, int budget)
9090{
9091 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
9092 napi);
9093 struct bnx2x *bp = fp->bp;
9094 int work_done = 0;
9095
9096#ifdef BNX2X_STOP_ON_ERROR
9097 if (unlikely(bp->panic))
9098 goto poll_panic;
9099#endif
9100
9101 prefetch(fp->tx_buf_ring[TX_BD(fp->tx_pkt_cons)].skb);
9102 prefetch(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb);
9103 prefetch((char *)(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb) + 256);
9104
9105 bnx2x_update_fpsb_idx(fp);
9106
9107 if ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) ||
9108 (fp->tx_pkt_prod != fp->tx_pkt_cons))
9109 bnx2x_tx_int(fp, budget);
9110
9111 if (le16_to_cpu(*fp->rx_cons_sb) != fp->rx_comp_cons)
9112 work_done = bnx2x_rx_int(fp, budget);
9113
9114 rmb(); /* bnx2x_has_work() reads the status block */
9115
9116 /* must not complete if we consumed full budget */
9117 if ((work_done < budget) && !bnx2x_has_work(fp)) {
9118
9119#ifdef BNX2X_STOP_ON_ERROR
9120poll_panic:
9121#endif
9122 netif_rx_complete(bp->dev, napi);
9123
9124 bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID,
9125 le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
9126 bnx2x_ack_sb(bp, FP_SB_ID(fp), CSTORM_ID,
9127 le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
9128 }
9129 return work_done;
9130}
9131
9132
9133/* we split the first BD into headers and data BDs
9134 * to ease the pain of our fellow micocode engineers
9135 * we use one mapping for both BDs
9136 * So far this has only been observed to happen
9137 * in Other Operating Systems(TM)
9138 */
9139static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
9140 struct bnx2x_fastpath *fp,
9141 struct eth_tx_bd **tx_bd, u16 hlen,
9142 u16 bd_prod, int nbd)
9143{
9144 struct eth_tx_bd *h_tx_bd = *tx_bd;
9145 struct eth_tx_bd *d_tx_bd;
9146 dma_addr_t mapping;
9147 int old_len = le16_to_cpu(h_tx_bd->nbytes);
9148
9149 /* first fix first BD */
9150 h_tx_bd->nbd = cpu_to_le16(nbd);
9151 h_tx_bd->nbytes = cpu_to_le16(hlen);
9152
9153 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d "
9154 "(%x:%x) nbd %d\n", h_tx_bd->nbytes, h_tx_bd->addr_hi,
9155 h_tx_bd->addr_lo, h_tx_bd->nbd);
9156
9157 /* now get a new data BD
9158 * (after the pbd) and fill it */
9159 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9160 d_tx_bd = &fp->tx_desc_ring[bd_prod];
9161
9162 mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
9163 le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
9164
9165 d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9166 d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9167 d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
9168 d_tx_bd->vlan = 0;
9169 /* this marks the BD as one that has no individual mapping
9170 * the FW ignores this flag in a BD not marked start
9171 */
9172 d_tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO;
9173 DP(NETIF_MSG_TX_QUEUED,
9174 "TSO split data size is %d (%x:%x)\n",
9175 d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
9176
9177 /* update tx_bd for marking the last BD flag */
9178 *tx_bd = d_tx_bd;
9179
9180 return bd_prod;
9181}
9182
9183static inline u16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
9184{
9185 if (fix > 0)
9186 csum = (u16) ~csum_fold(csum_sub(csum,
9187 csum_partial(t_header - fix, fix, 0)));
9188
9189 else if (fix < 0)
9190 csum = (u16) ~csum_fold(csum_add(csum,
9191 csum_partial(t_header, -fix, 0)));
9192
9193 return swab16(csum);
9194}
9195
9196static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
9197{
9198 u32 rc;
9199
9200 if (skb->ip_summed != CHECKSUM_PARTIAL)
9201 rc = XMIT_PLAIN;
9202
9203 else {
9204 if (skb->protocol == ntohs(ETH_P_IPV6)) {
9205 rc = XMIT_CSUM_V6;
9206 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
9207 rc |= XMIT_CSUM_TCP;
9208
9209 } else {
9210 rc = XMIT_CSUM_V4;
9211 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
9212 rc |= XMIT_CSUM_TCP;
9213 }
9214 }
9215
9216 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4)
9217 rc |= XMIT_GSO_V4;
9218
9219 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
9220 rc |= XMIT_GSO_V6;
9221
9222 return rc;
9223}
9224
9225/* check if packet requires linearization (packet is too fragmented) */
9226static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
9227 u32 xmit_type)
9228{
9229 int to_copy = 0;
9230 int hlen = 0;
9231 int first_bd_sz = 0;
9232
9233 /* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
9234 if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) {
9235
9236 if (xmit_type & XMIT_GSO) {
9237 unsigned short lso_mss = skb_shinfo(skb)->gso_size;
9238 /* Check if LSO packet needs to be copied:
9239 3 = 1 (for headers BD) + 2 (for PBD and last BD) */
9240 int wnd_size = MAX_FETCH_BD - 3;
9241 /* Number of widnows to check */
9242 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
9243 int wnd_idx = 0;
9244 int frag_idx = 0;
9245 u32 wnd_sum = 0;
9246
9247 /* Headers length */
9248 hlen = (int)(skb_transport_header(skb) - skb->data) +
9249 tcp_hdrlen(skb);
9250
9251 /* Amount of data (w/o headers) on linear part of SKB*/
9252 first_bd_sz = skb_headlen(skb) - hlen;
9253
9254 wnd_sum = first_bd_sz;
9255
9256 /* Calculate the first sum - it's special */
9257 for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
9258 wnd_sum +=
9259 skb_shinfo(skb)->frags[frag_idx].size;
9260
9261 /* If there was data on linear skb data - check it */
9262 if (first_bd_sz > 0) {
9263 if (unlikely(wnd_sum < lso_mss)) {
9264 to_copy = 1;
9265 goto exit_lbl;
9266 }
9267
9268 wnd_sum -= first_bd_sz;
9269 }
9270
9271 /* Others are easier: run through the frag list and
9272 check all windows */
9273 for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
9274 wnd_sum +=
9275 skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1].size;
9276
9277 if (unlikely(wnd_sum < lso_mss)) {
9278 to_copy = 1;
9279 break;
9280 }
9281 wnd_sum -=
9282 skb_shinfo(skb)->frags[wnd_idx].size;
9283 }
9284
9285 } else {
9286 /* in non-LSO too fragmented packet should always
9287 be linearized */
9288 to_copy = 1;
9289 }
9290 }
9291
9292exit_lbl:
9293 if (unlikely(to_copy))
9294 DP(NETIF_MSG_TX_QUEUED,
9295 "Linearization IS REQUIRED for %s packet. "
9296 "num_frags %d hlen %d first_bd_sz %d\n",
9297 (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
9298 skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
9299
9300 return to_copy;
9301}
9302
9303/* called with netif_tx_lock
9304 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
9305 * netif_wake_queue()
9306 */
9307static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9308{
9309 struct bnx2x *bp = netdev_priv(dev);
9310 struct bnx2x_fastpath *fp;
9311 struct sw_tx_bd *tx_buf;
9312 struct eth_tx_bd *tx_bd;
9313 struct eth_tx_parse_bd *pbd = NULL;
9314 u16 pkt_prod, bd_prod;
9315 int nbd, fp_index;
9316 dma_addr_t mapping;
9317 u32 xmit_type = bnx2x_xmit_type(bp, skb);
9318 int vlan_off = (bp->e1hov ? 4 : 0);
9319 int i;
9320 u8 hlen = 0;
9321
9322#ifdef BNX2X_STOP_ON_ERROR
9323 if (unlikely(bp->panic))
9324 return NETDEV_TX_BUSY;
9325#endif
9326
9327 fp_index = (smp_processor_id() % bp->num_queues);
9328 fp = &bp->fp[fp_index];
9329
9330 if (unlikely(bnx2x_tx_avail(bp->fp) <
9331 (skb_shinfo(skb)->nr_frags + 3))) {
9332 bp->eth_stats.driver_xoff++,
9333 netif_stop_queue(dev);
9334 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
9335 return NETDEV_TX_BUSY;
9336 }
9337
9338 DP(NETIF_MSG_TX_QUEUED, "SKB: summed %x protocol %x protocol(%x,%x)"
9339 " gso type %x xmit_type %x\n",
9340 skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
9341 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
9342
9343 /* First, check if we need to linearaize the skb
9344 (due to FW restrictions) */
9345 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
9346 /* Statistics of linearization */
9347 bp->lin_cnt++;
9348 if (skb_linearize(skb) != 0) {
9349 DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - "
9350 "silently dropping this SKB\n");
9351 dev_kfree_skb_any(skb);
9352 return 0;
9353 }
9354 }
9355
9356 /*
9357 Please read carefully. First we use one BD which we mark as start,
9358 then for TSO or xsum we have a parsing info BD,
9359 and only then we have the rest of the TSO BDs.
9360 (don't forget to mark the last one as last,
9361 and to unmap only AFTER you write to the BD ...)
9362 And above all, all pdb sizes are in words - NOT DWORDS!
9363 */
9364
9365 pkt_prod = fp->tx_pkt_prod++;
9366 bd_prod = TX_BD(fp->tx_bd_prod);
9367
9368 /* get a tx_buf and first BD */
9369 tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
9370 tx_bd = &fp->tx_desc_ring[bd_prod];
9371
9372 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
9373 tx_bd->general_data = (UNICAST_ADDRESS <<
9374 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
9375 tx_bd->general_data |= 1; /* header nbd */
9376
9377 /* remember the first BD of the packet */
9378 tx_buf->first_bd = fp->tx_bd_prod;
9379 tx_buf->skb = skb;
9380
9381 DP(NETIF_MSG_TX_QUEUED,
9382 "sending pkt %u @%p next_idx %u bd %u @%p\n",
9383 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_bd);
9384
9385 if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb)) {
9386 tx_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb));
9387 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
9388 vlan_off += 4;
9389 } else
9390 tx_bd->vlan = cpu_to_le16(pkt_prod);
9391
9392 if (xmit_type) {
9393
9394 /* turn on parsing and get a BD */
9395 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9396 pbd = (void *)&fp->tx_desc_ring[bd_prod];
9397
9398 memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
9399 }
9400
9401 if (xmit_type & XMIT_CSUM) {
9402 hlen = (skb_network_header(skb) - skb->data + vlan_off) / 2;
9403
9404 /* for now NS flag is not used in Linux */
9405 pbd->global_data = (hlen |
9406 ((skb->protocol == ntohs(ETH_P_8021Q)) <<
9407 ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
9408
9409 pbd->ip_hlen = (skb_transport_header(skb) -
9410 skb_network_header(skb)) / 2;
9411
9412 hlen += pbd->ip_hlen + tcp_hdrlen(skb) / 2;
9413
9414 pbd->total_hlen = cpu_to_le16(hlen);
9415 hlen = hlen*2 - vlan_off;
9416
9417 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_TCP_CSUM;
9418
9419 if (xmit_type & XMIT_CSUM_V4)
9420 tx_bd->bd_flags.as_bitfield |=
9421 ETH_TX_BD_FLAGS_IP_CSUM;
9422 else
9423 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6;
9424
9425 if (xmit_type & XMIT_CSUM_TCP) {
9426 pbd->tcp_pseudo_csum = swab16(tcp_hdr(skb)->check);
9427
9428 } else {
9429 s8 fix = SKB_CS_OFF(skb); /* signed! */
9430
9431 pbd->global_data |= ETH_TX_PARSE_BD_CS_ANY_FLG;
9432 pbd->cs_offset = fix / 2;
9433
9434 DP(NETIF_MSG_TX_QUEUED,
9435 "hlen %d offset %d fix %d csum before fix %x\n",
9436 le16_to_cpu(pbd->total_hlen), pbd->cs_offset, fix,
9437 SKB_CS(skb));
9438
9439 /* HW bug: fixup the CSUM */
9440 pbd->tcp_pseudo_csum =
9441 bnx2x_csum_fix(skb_transport_header(skb),
9442 SKB_CS(skb), fix);
9443
9444 DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
9445 pbd->tcp_pseudo_csum);
9446 }
9447 }
9448
9449 mapping = pci_map_single(bp->pdev, skb->data,
9450 skb_headlen(skb), PCI_DMA_TODEVICE);
9451
9452 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9453 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9454 nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL)? 1 : 2);
9455 tx_bd->nbd = cpu_to_le16(nbd);
9456 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
9457
9458 DP(NETIF_MSG_TX_QUEUED, "first bd @%p addr (%x:%x) nbd %d"
9459 " nbytes %d flags %x vlan %x\n",
9460 tx_bd, tx_bd->addr_hi, tx_bd->addr_lo, le16_to_cpu(tx_bd->nbd),
9461 le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield,
9462 le16_to_cpu(tx_bd->vlan));
9463
9464 if (xmit_type & XMIT_GSO) {
9465
9466 DP(NETIF_MSG_TX_QUEUED,
9467 "TSO packet len %d hlen %d total len %d tso size %d\n",
9468 skb->len, hlen, skb_headlen(skb),
9469 skb_shinfo(skb)->gso_size);
9470
9471 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
9472
9473 if (unlikely(skb_headlen(skb) > hlen))
9474 bd_prod = bnx2x_tx_split(bp, fp, &tx_bd, hlen,
9475 bd_prod, ++nbd);
9476
9477 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
9478 pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq);
9479 pbd->tcp_flags = pbd_tcp_flags(skb);
9480
9481 if (xmit_type & XMIT_GSO_V4) {
9482 pbd->ip_id = swab16(ip_hdr(skb)->id);
9483 pbd->tcp_pseudo_csum =
9484 swab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
9485 ip_hdr(skb)->daddr,
9486 0, IPPROTO_TCP, 0));
9487
9488 } else
9489 pbd->tcp_pseudo_csum =
9490 swab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
9491 &ipv6_hdr(skb)->daddr,
9492 0, IPPROTO_TCP, 0));
9493
9494 pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
9495 }
9496
9497 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9498 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
9499
9500 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9501 tx_bd = &fp->tx_desc_ring[bd_prod];
9502
9503 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
9504 frag->size, PCI_DMA_TODEVICE);
9505
9506 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9507 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9508 tx_bd->nbytes = cpu_to_le16(frag->size);
9509 tx_bd->vlan = cpu_to_le16(pkt_prod);
9510 tx_bd->bd_flags.as_bitfield = 0;
9511
9512 DP(NETIF_MSG_TX_QUEUED,
9513 "frag %d bd @%p addr (%x:%x) nbytes %d flags %x\n",
9514 i, tx_bd, tx_bd->addr_hi, tx_bd->addr_lo,
9515 le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield);
9516 }
9517
9518 /* now at last mark the BD as the last BD */
9519 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_END_BD;
9520
9521 DP(NETIF_MSG_TX_QUEUED, "last bd @%p flags %x\n",
9522 tx_bd, tx_bd->bd_flags.as_bitfield);
9523
9524 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9525
9526 /* now send a tx doorbell, counting the next BD
9527 * if the packet contains or ends with it
9528 */
9529 if (TX_BD_POFF(bd_prod) < nbd)
9530 nbd++;
9531
9532 if (pbd)
9533 DP(NETIF_MSG_TX_QUEUED,
9534 "PBD @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u"
9535 " tcp_flags %x xsum %x seq %u hlen %u\n",
9536 pbd, pbd->global_data, pbd->ip_hlen, pbd->ip_id,
9537 pbd->lso_mss, pbd->tcp_flags, pbd->tcp_pseudo_csum,
9538 pbd->tcp_send_seq, le16_to_cpu(pbd->total_hlen));
9539
9540 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod);
9541
9542 fp->hw_tx_prods->bds_prod =
9543 cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + nbd);
9544 mb(); /* FW restriction: must not reorder writing nbd and packets */
9545 fp->hw_tx_prods->packets_prod =
9546 cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1);
9547 DOORBELL(bp, FP_IDX(fp), 0);
9548
9549 mmiowb();
9550
9551 fp->tx_bd_prod += nbd;
9552 dev->trans_start = jiffies;
9553
9554 if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) {
9555 netif_stop_queue(dev);
9556 bp->eth_stats.driver_xoff++;
9557 if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)
9558 netif_wake_queue(dev);
9559 }
9560 fp->tx_pkt++;
9561
9562 return NETDEV_TX_OK;
9563}
9564
9565/* called with rtnl_lock */
9566static int bnx2x_open(struct net_device *dev)
9567{
9568 struct bnx2x *bp = netdev_priv(dev);
9569
9570 bnx2x_set_power_state(bp, PCI_D0);
9571
9572 return bnx2x_nic_load(bp, LOAD_OPEN);
9573}
9574
9575/* called with rtnl_lock */
9576static int bnx2x_close(struct net_device *dev)
9577{
9578 struct bnx2x *bp = netdev_priv(dev);
9579
9580 /* Unload the driver, release IRQs */
9581 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9582 if (atomic_read(&bp->pdev->enable_cnt) == 1)
9583 if (!CHIP_REV_IS_SLOW(bp))
9584 bnx2x_set_power_state(bp, PCI_D3hot);
9585
9586 return 0;
9587}
9588
9589/* called with netif_tx_lock from set_multicast */
9590static void bnx2x_set_rx_mode(struct net_device *dev)
9591{
9592 struct bnx2x *bp = netdev_priv(dev);
9593 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
9594 int port = BP_PORT(bp);
9595
9596 if (bp->state != BNX2X_STATE_OPEN) {
9597 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9598 return;
9599 }
9600
9601 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
9602
9603 if (dev->flags & IFF_PROMISC)
9604 rx_mode = BNX2X_RX_MODE_PROMISC;
9605
9606 else if ((dev->flags & IFF_ALLMULTI) ||
9607 ((dev->mc_count > BNX2X_MAX_MULTICAST) && CHIP_IS_E1(bp)))
9608 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9609
9610 else { /* some multicasts */
9611 if (CHIP_IS_E1(bp)) {
9612 int i, old, offset;
9613 struct dev_mc_list *mclist;
9614 struct mac_configuration_cmd *config =
9615 bnx2x_sp(bp, mcast_config);
9616
9617 for (i = 0, mclist = dev->mc_list;
9618 mclist && (i < dev->mc_count);
9619 i++, mclist = mclist->next) {
9620
9621 config->config_table[i].
9622 cam_entry.msb_mac_addr =
9623 swab16(*(u16 *)&mclist->dmi_addr[0]);
9624 config->config_table[i].
9625 cam_entry.middle_mac_addr =
9626 swab16(*(u16 *)&mclist->dmi_addr[2]);
9627 config->config_table[i].
9628 cam_entry.lsb_mac_addr =
9629 swab16(*(u16 *)&mclist->dmi_addr[4]);
9630 config->config_table[i].cam_entry.flags =
9631 cpu_to_le16(port);
9632 config->config_table[i].
9633 target_table_entry.flags = 0;
9634 config->config_table[i].
9635 target_table_entry.client_id = 0;
9636 config->config_table[i].
9637 target_table_entry.vlan_id = 0;
9638
9639 DP(NETIF_MSG_IFUP,
9640 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
9641 config->config_table[i].
9642 cam_entry.msb_mac_addr,
9643 config->config_table[i].
9644 cam_entry.middle_mac_addr,
9645 config->config_table[i].
9646 cam_entry.lsb_mac_addr);
9647 }
9648 old = config->hdr.length_6b;
9649 if (old > i) {
9650 for (; i < old; i++) {
9651 if (CAM_IS_INVALID(config->
9652 config_table[i])) {
9653 i--; /* already invalidated */
9654 break;
9655 }
9656 /* invalidate */
9657 CAM_INVALIDATE(config->
9658 config_table[i]);
9659 }
9660 }
9661
9662 if (CHIP_REV_IS_SLOW(bp))
9663 offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
9664 else
9665 offset = BNX2X_MAX_MULTICAST*(1 + port);
9666
9667 config->hdr.length_6b = i;
9668 config->hdr.offset = offset;
9669 config->hdr.client_id = BP_CL_ID(bp);
9670 config->hdr.reserved1 = 0;
9671
9672 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
9673 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
9674 U64_LO(bnx2x_sp_mapping(bp, mcast_config)),
9675 0);
9676 } else { /* E1H */
9677 /* Accept one or more multicasts */
9678 struct dev_mc_list *mclist;
9679 u32 mc_filter[MC_HASH_SIZE];
9680 u32 crc, bit, regidx;
9681 int i;
9682
9683 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
9684
9685 for (i = 0, mclist = dev->mc_list;
9686 mclist && (i < dev->mc_count);
9687 i++, mclist = mclist->next) {
9688
9689 DP(NETIF_MSG_IFUP, "Adding mcast MAC: "
9690 "%02x:%02x:%02x:%02x:%02x:%02x\n",
9691 mclist->dmi_addr[0], mclist->dmi_addr[1],
9692 mclist->dmi_addr[2], mclist->dmi_addr[3],
9693 mclist->dmi_addr[4], mclist->dmi_addr[5]);
9694
9695 crc = crc32c_le(0, mclist->dmi_addr, ETH_ALEN);
9696 bit = (crc >> 24) & 0xff;
9697 regidx = bit >> 5;
9698 bit &= 0x1f;
9699 mc_filter[regidx] |= (1 << bit);
9700 }
9701
9702 for (i = 0; i < MC_HASH_SIZE; i++)
9703 REG_WR(bp, MC_HASH_OFFSET(bp, i),
9704 mc_filter[i]);
9705 }
9706 }
9707
9708 bp->rx_mode = rx_mode;
9709 bnx2x_set_storm_rx_mode(bp);
9710}
9711
9712/* called with rtnl_lock */
9713static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
9714{
9715 struct sockaddr *addr = p;
9716 struct bnx2x *bp = netdev_priv(dev);
9717
9718 if (!is_valid_ether_addr((u8 *)(addr->sa_data)))
9719 return -EINVAL;
9720
9721 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9722 if (netif_running(dev)) {
9723 if (CHIP_IS_E1(bp))
9724 bnx2x_set_mac_addr_e1(bp);
9725 else
9726 bnx2x_set_mac_addr_e1h(bp);
9727 }
9728
9729 return 0;
9730}
9731
9732/* called with rtnl_lock */
9733static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9734{
9735 struct mii_ioctl_data *data = if_mii(ifr);
9736 struct bnx2x *bp = netdev_priv(dev);
9737 int err;
9738
9739 switch (cmd) {
9740 case SIOCGMIIPHY:
9741 data->phy_id = bp->port.phy_addr;
9742
9743 /* fallthrough */
9744
9745 case SIOCGMIIREG: {
9746 u16 mii_regval;
9747
9748 if (!netif_running(dev))
9749 return -EAGAIN;
9750
9751 mutex_lock(&bp->port.phy_mutex);
9752 err = bnx2x_cl45_read(bp, BP_PORT(bp), 0, bp->port.phy_addr,
9753 DEFAULT_PHY_DEV_ADDR,
9754 (data->reg_num & 0x1f), &mii_regval);
9755 data->val_out = mii_regval;
9756 mutex_unlock(&bp->port.phy_mutex);
9757 return err;
9758 }
9759
9760 case SIOCSMIIREG:
9761 if (!capable(CAP_NET_ADMIN))
9762 return -EPERM;
9763
9764 if (!netif_running(dev))
9765 return -EAGAIN;
9766
9767 mutex_lock(&bp->port.phy_mutex);
9768 err = bnx2x_cl45_write(bp, BP_PORT(bp), 0, bp->port.phy_addr,
9769 DEFAULT_PHY_DEV_ADDR,
9770 (data->reg_num & 0x1f), data->val_in);
9771 mutex_unlock(&bp->port.phy_mutex);
9772 return err;
9773
9774 default:
9775 /* do nothing */
9776 break;
9777 }
9778
9779 return -EOPNOTSUPP;
9780}
9781
9782/* called with rtnl_lock */
9783static int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
9784{
9785 struct bnx2x *bp = netdev_priv(dev);
9786 int rc = 0;
9787
9788 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
9789 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE))
9790 return -EINVAL;
9791
9792 /* This does not race with packet allocation
9793 * because the actual alloc size is
9794 * only updated as part of load
9795 */
9796 dev->mtu = new_mtu;
9797
9798 if (netif_running(dev)) {
9799 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9800 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
9801 }
9802
9803 return rc;
9804}
9805
9806static void bnx2x_tx_timeout(struct net_device *dev)
9807{
9808 struct bnx2x *bp = netdev_priv(dev);
9809
9810#ifdef BNX2X_STOP_ON_ERROR
9811 if (!bp->panic)
9812 bnx2x_panic();
9813#endif
9814 /* This allows the netif to be shutdown gracefully before resetting */
9815 schedule_work(&bp->reset_task);
9816}
9817
9818#ifdef BCM_VLAN
9819/* called with rtnl_lock */
9820static void bnx2x_vlan_rx_register(struct net_device *dev,
9821 struct vlan_group *vlgrp)
9822{
9823 struct bnx2x *bp = netdev_priv(dev);
9824
9825 bp->vlgrp = vlgrp;
9826 if (netif_running(dev))
9827 bnx2x_set_client_config(bp);
9828}
9829
9830#endif
9831
9832#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
9833static void poll_bnx2x(struct net_device *dev)
9834{
9835 struct bnx2x *bp = netdev_priv(dev);
9836
9837 disable_irq(bp->pdev->irq);
9838 bnx2x_interrupt(bp->pdev->irq, dev);
9839 enable_irq(bp->pdev->irq);
9840}
9841#endif
9842
9843static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9844 struct net_device *dev)
9845{
9846 struct bnx2x *bp;
9847 int rc;
9848
9849 SET_NETDEV_DEV(dev, &pdev->dev);
9850 bp = netdev_priv(dev);
9851
9852 bp->dev = dev;
9853 bp->pdev = pdev;
9854 bp->flags = 0;
9855 bp->func = PCI_FUNC(pdev->devfn);
9856
9857 rc = pci_enable_device(pdev);
9858 if (rc) {
9859 printk(KERN_ERR PFX "Cannot enable PCI device, aborting\n");
9860 goto err_out;
9861 }
9862
9863 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9864 printk(KERN_ERR PFX "Cannot find PCI device base address,"
9865 " aborting\n");
9866 rc = -ENODEV;
9867 goto err_out_disable;
9868 }
9869
9870 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9871 printk(KERN_ERR PFX "Cannot find second PCI device"
9872 " base address, aborting\n");
9873 rc = -ENODEV;
9874 goto err_out_disable;
9875 }
9876
9877 if (atomic_read(&pdev->enable_cnt) == 1) {
9878 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9879 if (rc) {
9880 printk(KERN_ERR PFX "Cannot obtain PCI resources,"
9881 " aborting\n");
9882 goto err_out_disable;
9883 }
9884
9885 pci_set_master(pdev);
9886 pci_save_state(pdev);
9887 }
9888
9889 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9890 if (bp->pm_cap == 0) {
9891 printk(KERN_ERR PFX "Cannot find power management"
9892 " capability, aborting\n");
9893 rc = -EIO;
9894 goto err_out_release;
9895 }
9896
9897 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9898 if (bp->pcie_cap == 0) {
9899 printk(KERN_ERR PFX "Cannot find PCI Express capability,"
9900 " aborting\n");
9901 rc = -EIO;
9902 goto err_out_release;
9903 }
9904
9905 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
9906 bp->flags |= USING_DAC_FLAG;
9907 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
9908 printk(KERN_ERR PFX "pci_set_consistent_dma_mask"
9909 " failed, aborting\n");
9910 rc = -EIO;
9911 goto err_out_release;
9912 }
9913
9914 } else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
9915 printk(KERN_ERR PFX "System does not support DMA,"
9916 " aborting\n");
9917 rc = -EIO;
9918 goto err_out_release;
9919 }
9920
9921 dev->mem_start = pci_resource_start(pdev, 0);
9922 dev->base_addr = dev->mem_start;
9923 dev->mem_end = pci_resource_end(pdev, 0);
9924
9925 dev->irq = pdev->irq;
9926
9927 bp->regview = ioremap_nocache(dev->base_addr,
9928 pci_resource_len(pdev, 0));
9929 if (!bp->regview) {
9930 printk(KERN_ERR PFX "Cannot map register space, aborting\n");
9931 rc = -ENOMEM;
9932 goto err_out_release;
9933 }
9934
9935 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
9936 min_t(u64, BNX2X_DB_SIZE,
9937 pci_resource_len(pdev, 2)));
9938 if (!bp->doorbells) {
9939 printk(KERN_ERR PFX "Cannot map doorbell space, aborting\n");
9940 rc = -ENOMEM;
9941 goto err_out_unmap;
9942 }
9943
9944 bnx2x_set_power_state(bp, PCI_D0);
9945
9946 /* clean indirect addresses */
9947 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9948 PCICFG_VENDOR_ID_OFFSET);
9949 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9950 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9951 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9952 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
9953
9954 dev->hard_start_xmit = bnx2x_start_xmit;
9955 dev->watchdog_timeo = TX_TIMEOUT;
9956
9957 dev->ethtool_ops = &bnx2x_ethtool_ops;
9958 dev->open = bnx2x_open;
9959 dev->stop = bnx2x_close;
9960 dev->set_multicast_list = bnx2x_set_rx_mode;
9961 dev->set_mac_address = bnx2x_change_mac_addr;
9962 dev->do_ioctl = bnx2x_ioctl;
9963 dev->change_mtu = bnx2x_change_mtu;
9964 dev->tx_timeout = bnx2x_tx_timeout;
9965#ifdef BCM_VLAN
9966 dev->vlan_rx_register = bnx2x_vlan_rx_register;
9967#endif
9968#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
9969 dev->poll_controller = poll_bnx2x;
9970#endif
9971 dev->features |= NETIF_F_SG;
9972 dev->features |= NETIF_F_HW_CSUM;
9973 if (bp->flags & USING_DAC_FLAG)
9974 dev->features |= NETIF_F_HIGHDMA;
9975#ifdef BCM_VLAN
9976 dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
9977#endif
9978 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9979 dev->features |= NETIF_F_TSO6;
9980
9981 return 0;
9982
9983err_out_unmap:
9984 if (bp->regview) {
9985 iounmap(bp->regview);
9986 bp->regview = NULL;
9987 }
9988 if (bp->doorbells) {
9989 iounmap(bp->doorbells);
9990 bp->doorbells = NULL;
9991 }
9992
9993err_out_release:
9994 if (atomic_read(&pdev->enable_cnt) == 1)
9995 pci_release_regions(pdev);
9996
9997err_out_disable:
9998 pci_disable_device(pdev);
9999 pci_set_drvdata(pdev, NULL);
10000
10001err_out:
10002 return rc;
10003}
10004
10005static int __devinit bnx2x_get_pcie_width(struct bnx2x *bp)
10006{
10007 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10008
10009 val = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10010 return val;
10011}
10012
10013/* return value of 1=2.5GHz 2=5GHz */
10014static int __devinit bnx2x_get_pcie_speed(struct bnx2x *bp)
10015{
10016 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10017
10018 val = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10019 return val;
10020}
10021
10022static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10023 const struct pci_device_id *ent)
10024{
10025 static int version_printed;
10026 struct net_device *dev = NULL;
10027 struct bnx2x *bp;
10028 int rc;
10029 DECLARE_MAC_BUF(mac);
10030
10031 if (version_printed++ == 0)
10032 printk(KERN_INFO "%s", version);
10033
10034 /* dev zeroed in init_etherdev */
10035 dev = alloc_etherdev(sizeof(*bp));
10036 if (!dev) {
10037 printk(KERN_ERR PFX "Cannot allocate net device\n");
10038 return -ENOMEM;
10039 }
10040
10041 netif_carrier_off(dev);
10042
10043 bp = netdev_priv(dev);
10044 bp->msglevel = debug;
10045
10046 rc = bnx2x_init_dev(pdev, dev);
10047 if (rc < 0) {
10048 free_netdev(dev);
10049 return rc;
10050 }
10051
10052 rc = register_netdev(dev);
10053 if (rc) {
10054 dev_err(&pdev->dev, "Cannot register net device\n");
10055 goto init_one_exit;
10056 }
10057
10058 pci_set_drvdata(pdev, dev);
10059
10060 rc = bnx2x_init_bp(bp);
10061 if (rc) {
10062 unregister_netdev(dev);
10063 goto init_one_exit;
10064 }
10065
10066 bp->common.name = board_info[ent->driver_data].name;
10067 printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx,"
10068 " IRQ %d, ", dev->name, bp->common.name,
10069 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10070 bnx2x_get_pcie_width(bp),
10071 (bnx2x_get_pcie_speed(bp) == 2) ? "5GHz (Gen2)" : "2.5GHz",
10072 dev->base_addr, bp->pdev->irq);
10073 printk(KERN_CONT "node addr %s\n", print_mac(mac, dev->dev_addr));
10074 return 0;
10075
10076init_one_exit:
10077 if (bp->regview)
10078 iounmap(bp->regview);
10079
10080 if (bp->doorbells)
10081 iounmap(bp->doorbells);
10082
10083 free_netdev(dev);
10084
10085 if (atomic_read(&pdev->enable_cnt) == 1)
10086 pci_release_regions(pdev);
10087
10088 pci_disable_device(pdev);
10089 pci_set_drvdata(pdev, NULL);
10090
10091 return rc;
10092}
10093
10094static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10095{
10096 struct net_device *dev = pci_get_drvdata(pdev);
10097 struct bnx2x *bp;
10098
10099 if (!dev) {
10100 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
10101 return;
10102 }
10103 bp = netdev_priv(dev);
10104
10105 unregister_netdev(dev);
10106
10107 if (bp->regview)
10108 iounmap(bp->regview);
10109
10110 if (bp->doorbells)
10111 iounmap(bp->doorbells);
10112
10113 free_netdev(dev);
10114
10115 if (atomic_read(&pdev->enable_cnt) == 1)
10116 pci_release_regions(pdev);
10117
10118 pci_disable_device(pdev);
10119 pci_set_drvdata(pdev, NULL);
10120}
10121
10122static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
10123{
10124 struct net_device *dev = pci_get_drvdata(pdev);
10125 struct bnx2x *bp;
10126
10127 if (!dev) {
10128 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
10129 return -ENODEV;
10130 }
10131 bp = netdev_priv(dev);
10132
10133 rtnl_lock();
10134
10135 pci_save_state(pdev);
10136
10137 if (!netif_running(dev)) {
10138 rtnl_unlock();
10139 return 0;
10140 }
10141
10142 netif_device_detach(dev);
10143
10144 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
10145
10146 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
10147
10148 rtnl_unlock();
10149
10150 return 0;
10151}
10152
10153static int bnx2x_resume(struct pci_dev *pdev)
10154{
10155 struct net_device *dev = pci_get_drvdata(pdev);
10156 struct bnx2x *bp;
10157 int rc;
10158
10159 if (!dev) {
10160 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
10161 return -ENODEV;
10162 }
10163 bp = netdev_priv(dev);
10164
10165 rtnl_lock();
10166
10167 pci_restore_state(pdev);
10168
10169 if (!netif_running(dev)) {
10170 rtnl_unlock();
10171 return 0;
10172 }
10173
10174 bnx2x_set_power_state(bp, PCI_D0);
10175 netif_device_attach(dev);
10176
10177 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
10178
10179 rtnl_unlock();
10180
10181 return rc;
10182}
10183
10184/**
10185 * bnx2x_io_error_detected - called when PCI error is detected
10186 * @pdev: Pointer to PCI device
10187 * @state: The current pci connection state
10188 *
10189 * This function is called after a PCI bus error affecting
10190 * this device has been detected.
10191 */
10192static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10193 pci_channel_state_t state)
10194{
10195 struct net_device *dev = pci_get_drvdata(pdev);
10196 struct bnx2x *bp = netdev_priv(dev);
10197
10198 rtnl_lock();
10199
10200 netif_device_detach(dev);
10201
10202 if (netif_running(dev))
10203 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
10204
10205 pci_disable_device(pdev);
10206
10207 rtnl_unlock();
10208
10209 /* Request a slot reset */
10210 return PCI_ERS_RESULT_NEED_RESET;
10211}
10212
10213/**
10214 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10215 * @pdev: Pointer to PCI device
10216 *
10217 * Restart the card from scratch, as if from a cold-boot.
10218 */
10219static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10220{
10221 struct net_device *dev = pci_get_drvdata(pdev);
10222 struct bnx2x *bp = netdev_priv(dev);
10223
10224 rtnl_lock();
10225
10226 if (pci_enable_device(pdev)) {
10227 dev_err(&pdev->dev,
10228 "Cannot re-enable PCI device after reset\n");
10229 rtnl_unlock();
10230 return PCI_ERS_RESULT_DISCONNECT;
10231 }
10232
10233 pci_set_master(pdev);
10234 pci_restore_state(pdev);
10235
10236 if (netif_running(dev))
10237 bnx2x_set_power_state(bp, PCI_D0);
10238
10239 rtnl_unlock();
10240
10241 return PCI_ERS_RESULT_RECOVERED;
10242}
10243
10244/**
10245 * bnx2x_io_resume - called when traffic can start flowing again
10246 * @pdev: Pointer to PCI device
10247 *
10248 * This callback is called when the error recovery driver tells us that
10249 * its OK to resume normal operation.
10250 */
10251static void bnx2x_io_resume(struct pci_dev *pdev)
10252{
10253 struct net_device *dev = pci_get_drvdata(pdev);
10254 struct bnx2x *bp = netdev_priv(dev);
10255
10256 rtnl_lock();
10257
10258 if (netif_running(dev))
10259 bnx2x_nic_load(bp, LOAD_OPEN);
10260
10261 netif_device_attach(dev);
10262
10263 rtnl_unlock();
10264}
10265
10266static struct pci_error_handlers bnx2x_err_handler = {
10267 .error_detected = bnx2x_io_error_detected,
10268 .slot_reset = bnx2x_io_slot_reset,
10269 .resume = bnx2x_io_resume,
10270};
10271
10272static struct pci_driver bnx2x_pci_driver = {
10273 .name = DRV_MODULE_NAME,
10274 .id_table = bnx2x_pci_tbl,
10275 .probe = bnx2x_init_one,
10276 .remove = __devexit_p(bnx2x_remove_one),
10277 .suspend = bnx2x_suspend,
10278 .resume = bnx2x_resume,
10279 .err_handler = &bnx2x_err_handler,
10280};
10281
10282static int __init bnx2x_init(void)
10283{
10284 return pci_register_driver(&bnx2x_pci_driver);
10285}
10286
10287static void __exit bnx2x_cleanup(void)
10288{
10289 pci_unregister_driver(&bnx2x_pci_driver);
10290}
10291
10292module_init(bnx2x_init);
10293module_exit(bnx2x_cleanup);
10294
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index 5a1aa0b55044..15c9a9946724 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -38,21 +38,19 @@
38 was asserted. */ 38 was asserted. */
39#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8 39#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
40#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc 40#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
41#define BRB1_REG_NUM_OF_FULL_CYCLES_2 0x600d0
42#define BRB1_REG_NUM_OF_FULL_CYCLES_3 0x600d4
43#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8 41#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
44/* [ST 32] The number of cycles that the pause signal towards MAC #0 was 42/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
45 asserted. */ 43 asserted. */
46#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8 44#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
47#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc 45#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
48#define BRB1_REG_NUM_OF_PAUSE_CYCLES_2 0x600c0
49#define BRB1_REG_NUM_OF_PAUSE_CYCLES_3 0x600c4
50/* [RW 10] Write client 0: De-assert pause threshold. */ 46/* [RW 10] Write client 0: De-assert pause threshold. */
51#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 47#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
52#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c 48#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
53/* [RW 10] Write client 0: Assert pause threshold. */ 49/* [RW 10] Write client 0: Assert pause threshold. */
54#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 50#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
55#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c 51#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
52/* [R 24] The number of full blocks occpied by port. */
53#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
56/* [RW 1] Reset the design by software. */ 54/* [RW 1] Reset the design by software. */
57#define BRB1_REG_SOFT_RESET 0x600dc 55#define BRB1_REG_SOFT_RESET 0x600dc
58/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ 56/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
@@ -72,6 +70,8 @@
72#define CCM_REG_CCM_INT_MASK 0xd01e4 70#define CCM_REG_CCM_INT_MASK 0xd01e4
73/* [R 11] Interrupt register #0 read */ 71/* [R 11] Interrupt register #0 read */
74#define CCM_REG_CCM_INT_STS 0xd01d8 72#define CCM_REG_CCM_INT_STS 0xd01d8
73/* [R 27] Parity register #0 read */
74#define CCM_REG_CCM_PRTY_STS 0xd01e8
75/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 75/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
76 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 76 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
77 Is used to determine the number of the AG context REG-pairs written back; 77 Is used to determine the number of the AG context REG-pairs written back;
@@ -190,25 +190,20 @@
190 weight 8 (the most prioritised); 1 stands for weight 1(least 190 weight 8 (the most prioritised); 1 stands for weight 1(least
191 prioritised); 2 stands for weight 2; tc. */ 191 prioritised); 2 stands for weight 2; tc. */
192#define CCM_REG_PBF_WEIGHT 0xd00ac 192#define CCM_REG_PBF_WEIGHT 0xd00ac
193/* [RW 6] The physical queue number of queue number 1 per port index. */
194#define CCM_REG_PHYS_QNUM1_0 0xd0134 193#define CCM_REG_PHYS_QNUM1_0 0xd0134
195#define CCM_REG_PHYS_QNUM1_1 0xd0138 194#define CCM_REG_PHYS_QNUM1_1 0xd0138
196/* [RW 6] The physical queue number of queue number 2 per port index. */
197#define CCM_REG_PHYS_QNUM2_0 0xd013c 195#define CCM_REG_PHYS_QNUM2_0 0xd013c
198#define CCM_REG_PHYS_QNUM2_1 0xd0140 196#define CCM_REG_PHYS_QNUM2_1 0xd0140
199/* [RW 6] The physical queue number of queue number 3 per port index. */
200#define CCM_REG_PHYS_QNUM3_0 0xd0144 197#define CCM_REG_PHYS_QNUM3_0 0xd0144
201/* [RW 6] The physical queue number of queue number 0 with QOS equal 0 port 198#define CCM_REG_PHYS_QNUM3_1 0xd0148
202 index 0. */
203#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114 199#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
204#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118 200#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
205/* [RW 6] The physical queue number of queue number 0 with QOS equal 1 port
206 index 0. */
207#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c 201#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
208#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120 202#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
209/* [RW 6] The physical queue number of queue number 0 with QOS equal 2 port
210 index 0. */
211#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124 203#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
204#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
205#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
206#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
212/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 207/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
213 disregarded; acknowledge output is deasserted; all other signals are 208 disregarded; acknowledge output is deasserted; all other signals are
214 treated as usual; if 1 - normal activity. */ 209 treated as usual; if 1 - normal activity. */
@@ -253,6 +248,7 @@
253 mechanism. The fields are: [5:0] - message length; [12:6] - message 248 mechanism. The fields are: [5:0] - message length; [12:6] - message
254 pointer; 18:13] - next pointer. */ 249 pointer; 18:13] - next pointer. */
255#define CCM_REG_XX_DESCR_TABLE 0xd0300 250#define CCM_REG_XX_DESCR_TABLE 0xd0300
251#define CCM_REG_XX_DESCR_TABLE_SIZE 36
256/* [R 7] Used to read the value of XX protection Free counter. */ 252/* [R 7] Used to read the value of XX protection Free counter. */
257#define CCM_REG_XX_FREE 0xd0184 253#define CCM_REG_XX_FREE 0xd0184
258/* [RW 6] Initial value for the credit counter; responsible for fulfilling 254/* [RW 6] Initial value for the credit counter; responsible for fulfilling
@@ -296,6 +292,8 @@
296/* [WB 24] MATT ram access. each entry has the following 292/* [WB 24] MATT ram access. each entry has the following
297 format:{RegionLength[11:0]; egionOffset[11:0]} */ 293 format:{RegionLength[11:0]; egionOffset[11:0]} */
298#define CDU_REG_MATT 0x101100 294#define CDU_REG_MATT 0x101100
295/* [RW 1] when this bit is set the CDU operates in e1hmf mode */
296#define CDU_REG_MF_MODE 0x101050
299/* [R 1] indication the initializing the activity counter by the hardware 297/* [R 1] indication the initializing the activity counter by the hardware
300 was done. */ 298 was done. */
301#define CFC_REG_AC_INIT_DONE 0x104078 299#define CFC_REG_AC_INIT_DONE 0x104078
@@ -330,6 +328,9 @@
330 field allows changing the priorities of the weighted-round-robin arbiter 328 field allows changing the priorities of the weighted-round-robin arbiter
331 which selects which CFC load client should be served next */ 329 which selects which CFC load client should be served next */
332#define CFC_REG_LCREQ_WEIGHTS 0x104084 330#define CFC_REG_LCREQ_WEIGHTS 0x104084
331/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
332#define CFC_REG_LINK_LIST 0x104c00
333#define CFC_REG_LINK_LIST_SIZE 256
333/* [R 1] indication the initializing the link list by the hardware was done. */ 334/* [R 1] indication the initializing the link list by the hardware was done. */
334#define CFC_REG_LL_INIT_DONE 0x104074 335#define CFC_REG_LL_INIT_DONE 0x104074
335/* [R 9] Number of allocated LCIDs which are at empty state */ 336/* [R 9] Number of allocated LCIDs which are at empty state */
@@ -342,6 +343,45 @@
342#define CFC_REG_NUM_LCIDS_LEAVING 0x104018 343#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
343/* [RW 8] The event id for aggregated interrupt 0 */ 344/* [RW 8] The event id for aggregated interrupt 0 */
344#define CSDM_REG_AGG_INT_EVENT_0 0xc2038 345#define CSDM_REG_AGG_INT_EVENT_0 0xc2038
346#define CSDM_REG_AGG_INT_EVENT_1 0xc203c
347#define CSDM_REG_AGG_INT_EVENT_10 0xc2060
348#define CSDM_REG_AGG_INT_EVENT_11 0xc2064
349#define CSDM_REG_AGG_INT_EVENT_12 0xc2068
350#define CSDM_REG_AGG_INT_EVENT_13 0xc206c
351#define CSDM_REG_AGG_INT_EVENT_14 0xc2070
352#define CSDM_REG_AGG_INT_EVENT_15 0xc2074
353#define CSDM_REG_AGG_INT_EVENT_16 0xc2078
354#define CSDM_REG_AGG_INT_EVENT_17 0xc207c
355#define CSDM_REG_AGG_INT_EVENT_18 0xc2080
356#define CSDM_REG_AGG_INT_EVENT_19 0xc2084
357#define CSDM_REG_AGG_INT_EVENT_2 0xc2040
358#define CSDM_REG_AGG_INT_EVENT_20 0xc2088
359#define CSDM_REG_AGG_INT_EVENT_21 0xc208c
360#define CSDM_REG_AGG_INT_EVENT_22 0xc2090
361#define CSDM_REG_AGG_INT_EVENT_23 0xc2094
362#define CSDM_REG_AGG_INT_EVENT_24 0xc2098
363#define CSDM_REG_AGG_INT_EVENT_25 0xc209c
364#define CSDM_REG_AGG_INT_EVENT_26 0xc20a0
365#define CSDM_REG_AGG_INT_EVENT_27 0xc20a4
366#define CSDM_REG_AGG_INT_EVENT_28 0xc20a8
367#define CSDM_REG_AGG_INT_EVENT_29 0xc20ac
368#define CSDM_REG_AGG_INT_EVENT_3 0xc2044
369#define CSDM_REG_AGG_INT_EVENT_30 0xc20b0
370#define CSDM_REG_AGG_INT_EVENT_31 0xc20b4
371#define CSDM_REG_AGG_INT_EVENT_4 0xc2048
372/* [RW 1] The T bit for aggregated interrupt 0 */
373#define CSDM_REG_AGG_INT_T_0 0xc20b8
374#define CSDM_REG_AGG_INT_T_1 0xc20bc
375#define CSDM_REG_AGG_INT_T_10 0xc20e0
376#define CSDM_REG_AGG_INT_T_11 0xc20e4
377#define CSDM_REG_AGG_INT_T_12 0xc20e8
378#define CSDM_REG_AGG_INT_T_13 0xc20ec
379#define CSDM_REG_AGG_INT_T_14 0xc20f0
380#define CSDM_REG_AGG_INT_T_15 0xc20f4
381#define CSDM_REG_AGG_INT_T_16 0xc20f8
382#define CSDM_REG_AGG_INT_T_17 0xc20fc
383#define CSDM_REG_AGG_INT_T_18 0xc2100
384#define CSDM_REG_AGG_INT_T_19 0xc2104
345/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 385/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
346#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 386#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
347/* [RW 16] The maximum value of the competion counter #0 */ 387/* [RW 16] The maximum value of the competion counter #0 */
@@ -358,6 +398,9 @@
358/* [RW 32] Interrupt mask register #0 read/write */ 398/* [RW 32] Interrupt mask register #0 read/write */
359#define CSDM_REG_CSDM_INT_MASK_0 0xc229c 399#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
360#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac 400#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
401/* [R 32] Interrupt register #0 read */
402#define CSDM_REG_CSDM_INT_STS_0 0xc2290
403#define CSDM_REG_CSDM_INT_STS_1 0xc22a0
361/* [RW 11] Parity mask register #0 read/write */ 404/* [RW 11] Parity mask register #0 read/write */
362#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc 405#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
363/* [R 11] Parity register #0 read */ 406/* [R 11] Parity register #0 read */
@@ -443,6 +486,9 @@
443/* [RW 32] Interrupt mask register #0 read/write */ 486/* [RW 32] Interrupt mask register #0 read/write */
444#define CSEM_REG_CSEM_INT_MASK_0 0x200110 487#define CSEM_REG_CSEM_INT_MASK_0 0x200110
445#define CSEM_REG_CSEM_INT_MASK_1 0x200120 488#define CSEM_REG_CSEM_INT_MASK_1 0x200120
489/* [R 32] Interrupt register #0 read */
490#define CSEM_REG_CSEM_INT_STS_0 0x200104
491#define CSEM_REG_CSEM_INT_STS_1 0x200114
446/* [RW 32] Parity mask register #0 read/write */ 492/* [RW 32] Parity mask register #0 read/write */
447#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 493#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
448#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 494#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
@@ -453,9 +499,8 @@
453#define CSEM_REG_ENABLE_OUT 0x2000a8 499#define CSEM_REG_ENABLE_OUT 0x2000a8
454/* [RW 32] This address space contains all registers and memories that are 500/* [RW 32] This address space contains all registers and memories that are
455 placed in SEM_FAST block. The SEM_FAST registers are described in 501 placed in SEM_FAST block. The SEM_FAST registers are described in
456 appendix B. In order to access the SEM_FAST registers the base address 502 appendix B. In order to access the sem_fast registers the base address
457 CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each 503 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
458 SEM_FAST register offset. */
459#define CSEM_REG_FAST_MEMORY 0x220000 504#define CSEM_REG_FAST_MEMORY 0x220000
460/* [RW 1] Disables input messages from FIC0 May be updated during run_time 505/* [RW 1] Disables input messages from FIC0 May be updated during run_time
461 by the microcode */ 506 by the microcode */
@@ -539,13 +584,10 @@
539#define DBG_REG_DBG_PRTY_MASK 0xc0a8 584#define DBG_REG_DBG_PRTY_MASK 0xc0a8
540/* [R 1] Parity register #0 read */ 585/* [R 1] Parity register #0 read */
541#define DBG_REG_DBG_PRTY_STS 0xc09c 586#define DBG_REG_DBG_PRTY_STS 0xc09c
542/* [RW 2] debug only: These bits indicate the credit for PCI request type 4
543 interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are
544 configured */
545#define DBG_REG_PCI_REQ_CREDIT 0xc120
546/* [RW 32] Commands memory. The address to command X; row Y is to calculated 587/* [RW 32] Commands memory. The address to command X; row Y is to calculated
547 as 14*X+Y. */ 588 as 14*X+Y. */
548#define DMAE_REG_CMD_MEM 0x102400 589#define DMAE_REG_CMD_MEM 0x102400
590#define DMAE_REG_CMD_MEM_SIZE 224
549/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c 591/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
550 initial value is all ones. */ 592 initial value is all ones. */
551#define DMAE_REG_CRC16C_INIT 0x10201c 593#define DMAE_REG_CRC16C_INIT 0x10201c
@@ -630,6 +672,8 @@
630#define DORQ_REG_AGG_CMD3 0x17006c 672#define DORQ_REG_AGG_CMD3 0x17006c
631/* [RW 28] UCM Header. */ 673/* [RW 28] UCM Header. */
632#define DORQ_REG_CMHEAD_RX 0x170050 674#define DORQ_REG_CMHEAD_RX 0x170050
675/* [RW 32] Doorbell address for RBC doorbells (function 0). */
676#define DORQ_REG_DB_ADDR0 0x17008c
633/* [RW 5] Interrupt mask register #0 read/write */ 677/* [RW 5] Interrupt mask register #0 read/write */
634#define DORQ_REG_DORQ_INT_MASK 0x170180 678#define DORQ_REG_DORQ_INT_MASK 0x170180
635/* [R 5] Interrupt register #0 read */ 679/* [R 5] Interrupt register #0 read */
@@ -690,75 +734,33 @@
690#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) 734#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
691#define HC_REG_AGG_INT_0 0x108050 735#define HC_REG_AGG_INT_0 0x108050
692#define HC_REG_AGG_INT_1 0x108054 736#define HC_REG_AGG_INT_1 0x108054
693/* [RW 16] attention bit and attention acknowledge bits status for port 0
694 and 1 according to the following address map: addr 0 - attn_bit_0; addr 1
695 - attn_ack_bit_0; addr 2 - attn_bit_1; addr 3 - attn_ack_bit_1; */
696#define HC_REG_ATTN_BIT 0x108120 737#define HC_REG_ATTN_BIT 0x108120
697/* [RW 16] attn bits status index for attn bit msg; addr 0 - function 0;
698 addr 1 - functin 1 */
699#define HC_REG_ATTN_IDX 0x108100 738#define HC_REG_ATTN_IDX 0x108100
700/* [RW 32] port 0 lower 32 bits address field for attn messag. */
701#define HC_REG_ATTN_MSG0_ADDR_L 0x108018 739#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
702/* [RW 32] port 1 lower 32 bits address field for attn messag. */
703#define HC_REG_ATTN_MSG1_ADDR_L 0x108020 740#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
704/* [RW 8] status block number for attn bit msg - function 0; */
705#define HC_REG_ATTN_NUM_P0 0x108038 741#define HC_REG_ATTN_NUM_P0 0x108038
706/* [RW 8] status block number for attn bit msg - function 1 */
707#define HC_REG_ATTN_NUM_P1 0x10803c 742#define HC_REG_ATTN_NUM_P1 0x10803c
708#define HC_REG_CONFIG_0 0x108000 743#define HC_REG_CONFIG_0 0x108000
709#define HC_REG_CONFIG_1 0x108004 744#define HC_REG_CONFIG_1 0x108004
745#define HC_REG_FUNC_NUM_P0 0x1080ac
746#define HC_REG_FUNC_NUM_P1 0x1080b0
710/* [RW 3] Parity mask register #0 read/write */ 747/* [RW 3] Parity mask register #0 read/write */
711#define HC_REG_HC_PRTY_MASK 0x1080a0 748#define HC_REG_HC_PRTY_MASK 0x1080a0
712/* [R 3] Parity register #0 read */ 749/* [R 3] Parity register #0 read */
713#define HC_REG_HC_PRTY_STS 0x108094 750#define HC_REG_HC_PRTY_STS 0x108094
714/* [RW 17] status block interrupt mask; one in each bit means unmask; zerow
715 in each bit means mask; bit 0 - default SB; bit 1 - SB_0; bit 2 - SB_1...
716 bit 16- SB_15; addr 0 - port 0; addr 1 - port 1 */
717#define HC_REG_INT_MASK 0x108108 751#define HC_REG_INT_MASK 0x108108
718/* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
719 lock a change fron 0 to 1 in the corresponding attention signals that
720 comes from the AEU */
721#define HC_REG_LEADING_EDGE_0 0x108040 752#define HC_REG_LEADING_EDGE_0 0x108040
722#define HC_REG_LEADING_EDGE_1 0x108048 753#define HC_REG_LEADING_EDGE_1 0x108048
723/* [RW 16] all producer and consumer of port 0 according to the following
724 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
725 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
726 U/C/X/T/Attn-69/70/71/72/73 */
727#define HC_REG_P0_PROD_CONS 0x108200 754#define HC_REG_P0_PROD_CONS 0x108200
728/* [RW 16] all producer and consumer of port 1according to the following
729 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
730 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
731 U/C/X/T/Attn-69/70/71/72/73 */
732#define HC_REG_P1_PROD_CONS 0x108400 755#define HC_REG_P1_PROD_CONS 0x108400
733/* [W 1] This register is write only and has 4 addresses as follow: 0 =
734 clear all PBA bits port 0; 1 = clear all pending interrupts request
735 port0; 2 = clear all PBA bits port 1; 3 = clear all pending interrupts
736 request port1; here is no meaning for the data in this register */
737#define HC_REG_PBA_COMMAND 0x108140 756#define HC_REG_PBA_COMMAND 0x108140
738#define HC_REG_PCI_CONFIG_0 0x108010 757#define HC_REG_PCI_CONFIG_0 0x108010
739#define HC_REG_PCI_CONFIG_1 0x108014 758#define HC_REG_PCI_CONFIG_1 0x108014
740/* [RW 24] all counters acording to the following address: LSB: 0=read; 1=
741 read_clear; 0-71 = HW counters (the inside order is the same as the
742 interrupt table in the spec); 72-219 = SW counters 1 (stops after first
743 consumer upd) the inside order is: 72-103 - U_non_default_p0; 104-135
744 C_non_defaul_p0; 36-145 U/C/X/T/Attn_default_p0; 146-177
745 U_non_default_p1; 178-209 C_non_defaul_p1; 10-219 U/C/X/T/Attn_default_p1
746 ; 220-367 = SW counters 2 (stops when prod=cons) the inside order is:
747 220-251 - U_non_default_p0; 252-283 C_non_defaul_p0; 84-293
748 U/C/X/T/Attn_default_p0; 294-325 U_non_default_p1; 326-357
749 C_non_defaul_p1; 58-367 U/C/X/T/Attn_default_p1 ; 368-515 = mailbox
750 counters; (the inside order of the mailbox counter is 368-431 U and C
751 non_default_p0; 432-441 U/C/X/T/Attn_default_p0; 442-505 U and C
752 non_default_p1; 506-515 U/C/X/T/Attn_default_p1) */
753#define HC_REG_STATISTIC_COUNTERS 0x109000 759#define HC_REG_STATISTIC_COUNTERS 0x109000
754/* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
755 lock a change fron 1 to 0 in the corresponding attention signals that
756 comes from the AEU */
757#define HC_REG_TRAILING_EDGE_0 0x108044 760#define HC_REG_TRAILING_EDGE_0 0x108044
758#define HC_REG_TRAILING_EDGE_1 0x10804c 761#define HC_REG_TRAILING_EDGE_1 0x10804c
759#define HC_REG_UC_RAM_ADDR_0 0x108028 762#define HC_REG_UC_RAM_ADDR_0 0x108028
760#define HC_REG_UC_RAM_ADDR_1 0x108030 763#define HC_REG_UC_RAM_ADDR_1 0x108030
761/* [RW 16] ustorm address for coalesc now message */
762#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068 764#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
763#define HC_REG_VQID_0 0x108008 765#define HC_REG_VQID_0 0x108008
764#define HC_REG_VQID_1 0x10800c 766#define HC_REG_VQID_1 0x10800c
@@ -883,14 +885,16 @@
883 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched 885 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
884 ump_tx_parity; [31] MCP Latched scpad_parity; */ 886 ump_tx_parity; [31] MCP Latched scpad_parity; */
885#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458 887#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
886/* [W 11] write to this register results with the clear of the latched 888/* [W 14] write to this register results with the clear of the latched
887 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in 889 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
888 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP 890 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
889 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears 891 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
890 GRC Latched reserved access attention; one in d7 clears Latched 892 GRC Latched reserved access attention; one in d7 clears Latched
891 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears 893 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
892 Latched ump_tx_parity; one in d10 clears Latched scpad_parity; read from 894 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
893 this register return zero */ 895 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
896 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
897 from this register return zero */
894#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c 898#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
895/* [RW 32] first 32b for enabling the output for function 0 output0. mapped 899/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
896 as follows: [0] NIG attention for function0; [1] NIG attention for 900 as follows: [0] NIG attention for function0; [1] NIG attention for
@@ -907,7 +911,11 @@
907 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 911 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
908#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c 912#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
909#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c 913#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
914#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
910#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c 915#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
916#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
917#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
918#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
911/* [RW 32] first 32b for enabling the output for function 1 output0. mapped 919/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
912 as follows: [0] NIG attention for function0; [1] NIG attention for 920 as follows: [0] NIG attention for function0; [1] NIG attention for
913 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 921 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
@@ -923,9 +931,13 @@
923 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 931 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
924#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c 932#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
925#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c 933#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
934#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
926#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c 935#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
927/* [RW 32] first 32b for enabling the output for close the gate nig 0. 936#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
928 mapped as follows: [0] NIG attention for function0; [1] NIG attention for 937#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
938#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
939/* [RW 32] first 32b for enabling the output for close the gate nig. mapped
940 as follows: [0] NIG attention for function0; [1] NIG attention for
929 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 941 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
930 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 942 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
931 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 943 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
@@ -939,8 +951,8 @@
939 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 951 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
940#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec 952#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
941#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c 953#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
942/* [RW 32] first 32b for enabling the output for close the gate pxp 0. 954/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
943 mapped as follows: [0] NIG attention for function0; [1] NIG attention for 955 as follows: [0] NIG attention for function0; [1] NIG attention for
944 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 956 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
945 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 957 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
946 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 958 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
@@ -984,34 +996,34 @@
984 interrupt; */ 996 interrupt; */
985#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110 997#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
986#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120 998#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
987/* [RW 32] second 32b for enabling the output for close the gate nig 0. 999/* [RW 32] second 32b for enabling the output for close the gate nig. mapped
988 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; 1000 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
989 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] 1001 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
990 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] 1002 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
991 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] 1003 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
992 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw 1004 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
993 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI 1005 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
994 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity 1006 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
995 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw 1007 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
996 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI 1008 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
997 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw 1009 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
998 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM 1010 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
999 Parity error; [31] CCM Hw interrupt; */ 1011 interrupt; */
1000#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0 1012#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1001#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190 1013#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1002/* [RW 32] second 32b for enabling the output for close the gate pxp 0. 1014/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1003 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; 1015 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1004 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] 1016 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1005 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] 1017 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1006 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] 1018 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1007 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw 1019 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1008 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI 1020 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1009 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity 1021 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1010 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw 1022 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1011 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI 1023 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1012 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw 1024 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1013 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM 1025 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1014 Parity error; [31] CCM Hw interrupt; */ 1026 interrupt; */
1015#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100 1027#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1016#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0 1028#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1017/* [RW 32] third 32b for enabling the output for function 0 output0. mapped 1029/* [RW 32] third 32b for enabling the output for function 0 output0. mapped
@@ -1044,34 +1056,34 @@
1044 attn1; */ 1056 attn1; */
1045#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114 1057#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1046#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124 1058#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1047/* [RW 32] third 32b for enabling the output for close the gate nig 0. 1059/* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1048 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] 1060 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1049 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity 1061 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1050 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC 1062 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1051 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE 1063 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1052 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] 1064 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1053 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; 1065 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1054 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; 1066 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1055 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; 1067 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1056 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; 1068 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1057 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers 1069 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1058 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] 1070 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1059 General attn1; */ 1071 attn1; */
1060#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4 1072#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1061#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194 1073#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1062/* [RW 32] third 32b for enabling the output for close the gate pxp 0. 1074/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1063 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] 1075 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1064 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity 1076 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1065 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC 1077 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1066 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE 1078 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1067 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] 1079 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1068 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; 1080 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1069 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; 1081 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1070 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; 1082 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1071 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; 1083 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1072 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers 1084 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1073 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] 1085 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1074 General attn1; */ 1086 attn1; */
1075#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104 1087#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1076#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4 1088#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1077/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped 1089/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
@@ -1088,6 +1100,10 @@
1088 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1100 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1089#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078 1101#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1090#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098 1102#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1103#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1104#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1105#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1106#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1091/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped 1107/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1092 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1108 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1093 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1109 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
@@ -1102,34 +1118,36 @@
1102 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1118 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1103#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118 1119#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1104#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138 1120#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1105/* [RW 32] fourth 32b for enabling the output for close the gate nig 1121#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1106 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General 1122#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1107 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] 1123#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1108 General attn8; [7] General attn9; [8] General attn10; [9] General attn11; 1124#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1109 [10] General attn12; [11] General attn13; [12] General attn14; [13] 1125/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1110 General attn15; [14] General attn16; [15] General attn17; [16] General 1126 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1111 attn18; [17] General attn19; [18] General attn20; [19] General attn21; 1127 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1112 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched 1128 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1113 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched 1129 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1114 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved 1130 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1115 access attention; [28] MCP Latched rom_parity; [29] MCP Latched 1131 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1116 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched 1132 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1117 scpad_parity; */ 1133 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1134 Latched timeout attention; [27] GRC Latched reserved access attention;
1135 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1136 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1118#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8 1137#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1119#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198 1138#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1120/* [RW 32] fourth 32b for enabling the output for close the gate pxp 1139/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1121 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General 1140 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1122 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] 1141 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1123 General attn8; [7] General attn9; [8] General attn10; [9] General attn11; 1142 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1124 [10] General attn12; [11] General attn13; [12] General attn14; [13] 1143 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1125 General attn15; [14] General attn16; [15] General attn17; [16] General 1144 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1126 attn18; [17] General attn19; [18] General attn20; [19] General attn21; 1145 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1127 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched 1146 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1128 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched 1147 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1129 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved 1148 Latched timeout attention; [27] GRC Latched reserved access attention;
1130 access attention; [28] MCP Latched rom_parity; [29] MCP Latched 1149 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1131 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched 1150 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1132 scpad_parity; */
1133#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 1151#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1134#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 1152#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1135/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 1153/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
@@ -1148,6 +1166,7 @@
1148#define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c 1166#define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
1149#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 1167#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1150#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c 1168#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1169#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1151#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 1170#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1152#define MISC_REG_AEU_GENERAL_ATTN_20 0xa050 1171#define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1153#define MISC_REG_AEU_GENERAL_ATTN_21 0xa054 1172#define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
@@ -1158,6 +1177,7 @@
1158#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c 1177#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1159#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 1178#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1160#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 1179#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1180#define MISC_REG_AEU_GENERAL_MASK 0xa61c
1161/* [RW 32] first 32b for inverting the input for function 0; for each bit: 1181/* [RW 32] first 32b for inverting the input for function 0; for each bit:
1162 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for 1182 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1163 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; 1183 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
@@ -1189,10 +1209,29 @@
1189#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230 1209#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1190#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240 1210#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1191/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; 1211/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1192 [9:8] = mask close the gates signals of function 0 toward PXP [8] and NIG 1212 [9:8] = raserved. Zero = mask; one = unmask */
1193 [9]. Zero = mask; one = unmask */
1194#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060 1213#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1195#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064 1214#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1215/* [RW 1] If set a system kill occurred */
1216#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1217/* [RW 32] Represent the status of the input vector to the AEU when a system
1218 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1219 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1220 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1221 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1222 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1223 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1224 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1225 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1226 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1227 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1228 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1229 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1230 interrupt; */
1231#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1232#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1233#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1234#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1196/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 1235/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1197 Port. */ 1236 Port. */
1198#define MISC_REG_BOND_ID 0xa400 1237#define MISC_REG_BOND_ID 0xa400
@@ -1206,8 +1245,80 @@
1206 starts at 0x0 for the A0 tape-out and increments by one for each 1245 starts at 0x0 for the A0 tape-out and increments by one for each
1207 all-layer tape-out. */ 1246 all-layer tape-out. */
1208#define MISC_REG_CHIP_REV 0xa40c 1247#define MISC_REG_CHIP_REV 0xa40c
1209/* [RW 32] The following driver registers(1..6) represent 6 drivers and 32 1248/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1210 clients. Each client can be controlled by one driver only. One in each 1249 32 clients. Each client can be controlled by one driver only. One in each
1250 bit represent that this driver control the appropriate client (Ex: bit 5
1251 is set means this driver control client number 5). addr1 = set; addr0 =
1252 clear; read from both addresses will give the same result = status. write
1253 to address 1 will set a request to control all the clients that their
1254 appropriate bit (in the write command) is set. if the client is free (the
1255 appropriate bit in all the other drivers is clear) one will be written to
1256 that driver register; if the client isn't free the bit will remain zero.
1257 if the appropriate bit is set (the driver request to gain control on a
1258 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1259 interrupt will be asserted). write to address 0 will set a request to
1260 free all the clients that their appropriate bit (in the write command) is
1261 set. if the appropriate bit is clear (the driver request to free a client
1262 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1263 be asserted). */
1264#define MISC_REG_DRIVER_CONTROL_10 0xa3e0
1265#define MISC_REG_DRIVER_CONTROL_10_SIZE 2
1266/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1267 32 clients. Each client can be controlled by one driver only. One in each
1268 bit represent that this driver control the appropriate client (Ex: bit 5
1269 is set means this driver control client number 5). addr1 = set; addr0 =
1270 clear; read from both addresses will give the same result = status. write
1271 to address 1 will set a request to control all the clients that their
1272 appropriate bit (in the write command) is set. if the client is free (the
1273 appropriate bit in all the other drivers is clear) one will be written to
1274 that driver register; if the client isn't free the bit will remain zero.
1275 if the appropriate bit is set (the driver request to gain control on a
1276 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1277 interrupt will be asserted). write to address 0 will set a request to
1278 free all the clients that their appropriate bit (in the write command) is
1279 set. if the appropriate bit is clear (the driver request to free a client
1280 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1281 be asserted). */
1282#define MISC_REG_DRIVER_CONTROL_11 0xa3e8
1283#define MISC_REG_DRIVER_CONTROL_11_SIZE 2
1284/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1285 32 clients. Each client can be controlled by one driver only. One in each
1286 bit represent that this driver control the appropriate client (Ex: bit 5
1287 is set means this driver control client number 5). addr1 = set; addr0 =
1288 clear; read from both addresses will give the same result = status. write
1289 to address 1 will set a request to control all the clients that their
1290 appropriate bit (in the write command) is set. if the client is free (the
1291 appropriate bit in all the other drivers is clear) one will be written to
1292 that driver register; if the client isn't free the bit will remain zero.
1293 if the appropriate bit is set (the driver request to gain control on a
1294 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1295 interrupt will be asserted). write to address 0 will set a request to
1296 free all the clients that their appropriate bit (in the write command) is
1297 set. if the appropriate bit is clear (the driver request to free a client
1298 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1299 be asserted). */
1300#define MISC_REG_DRIVER_CONTROL_12 0xa3f0
1301#define MISC_REG_DRIVER_CONTROL_12_SIZE 2
1302/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1303 32 clients. Each client can be controlled by one driver only. One in each
1304 bit represent that this driver control the appropriate client (Ex: bit 5
1305 is set means this driver control client number 5). addr1 = set; addr0 =
1306 clear; read from both addresses will give the same result = status. write
1307 to address 1 will set a request to control all the clients that their
1308 appropriate bit (in the write command) is set. if the client is free (the
1309 appropriate bit in all the other drivers is clear) one will be written to
1310 that driver register; if the client isn't free the bit will remain zero.
1311 if the appropriate bit is set (the driver request to gain control on a
1312 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1313 interrupt will be asserted). write to address 0 will set a request to
1314 free all the clients that their appropriate bit (in the write command) is
1315 set. if the appropriate bit is clear (the driver request to free a client
1316 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1317 be asserted). */
1318#define MISC_REG_DRIVER_CONTROL_13 0xa3f8
1319#define MISC_REG_DRIVER_CONTROL_13_SIZE 2
1320/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1321 32 clients. Each client can be controlled by one driver only. One in each
1211 bit represent that this driver control the appropriate client (Ex: bit 5 1322 bit represent that this driver control the appropriate client (Ex: bit 5
1212 is set means this driver control client number 5). addr1 = set; addr0 = 1323 is set means this driver control client number 5). addr1 = set; addr0 =
1213 clear; read from both addresses will give the same result = status. write 1324 clear; read from both addresses will give the same result = status. write
@@ -1223,6 +1334,47 @@
1223 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1334 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1224 be asserted). */ 1335 be asserted). */
1225#define MISC_REG_DRIVER_CONTROL_1 0xa510 1336#define MISC_REG_DRIVER_CONTROL_1 0xa510
1337#define MISC_REG_DRIVER_CONTROL_14 0xa5e0
1338#define MISC_REG_DRIVER_CONTROL_14_SIZE 2
1339/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1340 32 clients. Each client can be controlled by one driver only. One in each
1341 bit represent that this driver control the appropriate client (Ex: bit 5
1342 is set means this driver control client number 5). addr1 = set; addr0 =
1343 clear; read from both addresses will give the same result = status. write
1344 to address 1 will set a request to control all the clients that their
1345 appropriate bit (in the write command) is set. if the client is free (the
1346 appropriate bit in all the other drivers is clear) one will be written to
1347 that driver register; if the client isn't free the bit will remain zero.
1348 if the appropriate bit is set (the driver request to gain control on a
1349 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1350 interrupt will be asserted). write to address 0 will set a request to
1351 free all the clients that their appropriate bit (in the write command) is
1352 set. if the appropriate bit is clear (the driver request to free a client
1353 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1354 be asserted). */
1355#define MISC_REG_DRIVER_CONTROL_15 0xa5e8
1356#define MISC_REG_DRIVER_CONTROL_15_SIZE 2
1357/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1358 32 clients. Each client can be controlled by one driver only. One in each
1359 bit represent that this driver control the appropriate client (Ex: bit 5
1360 is set means this driver control client number 5). addr1 = set; addr0 =
1361 clear; read from both addresses will give the same result = status. write
1362 to address 1 will set a request to control all the clients that their
1363 appropriate bit (in the write command) is set. if the client is free (the
1364 appropriate bit in all the other drivers is clear) one will be written to
1365 that driver register; if the client isn't free the bit will remain zero.
1366 if the appropriate bit is set (the driver request to gain control on a
1367 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1368 interrupt will be asserted). write to address 0 will set a request to
1369 free all the clients that their appropriate bit (in the write command) is
1370 set. if the appropriate bit is clear (the driver request to free a client
1371 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1372 be asserted). */
1373#define MISC_REG_DRIVER_CONTROL_16 0xa5f0
1374#define MISC_REG_DRIVER_CONTROL_16_SIZE 2
1375/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1376 only. */
1377#define MISC_REG_E1HMF_MODE 0xa5f8
1226/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of 1378/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1227 these bits is written as a '1'; the corresponding SPIO bit will turn off 1379 these bits is written as a '1'; the corresponding SPIO bit will turn off
1228 it's drivers and become an input. This is the reset state of all GPIO 1380 it's drivers and become an input. This is the reset state of all GPIO
@@ -1240,6 +1392,18 @@
1240 This is the result value of the pin; not the drive value. Writing these 1392 This is the result value of the pin; not the drive value. Writing these
1241 bits will have not effect. */ 1393 bits will have not effect. */
1242#define MISC_REG_GPIO 0xa490 1394#define MISC_REG_GPIO 0xa490
1395/* [R 28] this field hold the last information that caused reserved
1396 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1397 [27:24] the master thatcaused the attention - according to the following
1398 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1399 dbu; 8 = dmae */
1400#define MISC_REG_GRC_RSV_ATTN 0xa3c0
1401/* [R 28] this field hold the last information that caused timeout
1402 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1403 [27:24] the master thatcaused the attention - according to the following
1404 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1405 dbu; 8 = dmae */
1406#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1243/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any 1407/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1244 access that does not finish within 1408 access that does not finish within
1245 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is 1409 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
@@ -1282,6 +1446,11 @@
1282#define MISC_REG_MISC_PRTY_MASK 0xa398 1446#define MISC_REG_MISC_PRTY_MASK 0xa398
1283/* [R 1] Parity register #0 read */ 1447/* [R 1] Parity register #0 read */
1284#define MISC_REG_MISC_PRTY_STS 0xa38c 1448#define MISC_REG_MISC_PRTY_STS 0xa38c
1449#define MISC_REG_NIG_WOL_P0 0xa270
1450#define MISC_REG_NIG_WOL_P1 0xa274
1451/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1452 assertion */
1453#define MISC_REG_PCIE_HOT_RESET 0xa618
1285/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. 1454/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1286 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 1455 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1287 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 1456 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
@@ -1303,7 +1472,7 @@
1303#define MISC_REG_PLL_STORM_CTRL_2 0xa298 1472#define MISC_REG_PLL_STORM_CTRL_2 0xa298
1304#define MISC_REG_PLL_STORM_CTRL_3 0xa29c 1473#define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1305#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0 1474#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1306/* [RW 32] reset reg#1; rite/read one = the specific block is out of reset; 1475/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1307 write/read zero = the specific block is in reset; addr 0-wr- the write 1476 write/read zero = the specific block is in reset; addr 0-wr- the write
1308 value will be written to the register; addr 1-set - one will be written 1477 value will be written to the register; addr 1-set - one will be written
1309 to all the bits that have the value of one in the data written (bits that 1478 to all the bits that have the value of one in the data written (bits that
@@ -1311,14 +1480,12 @@
1311 written to all the bits that have the value of one in the data written 1480 written to all the bits that have the value of one in the data written
1312 (bits that have the value of zero will not be change); addr 3-ignore; 1481 (bits that have the value of zero will not be change); addr 3-ignore;
1313 read ignore from all addr except addr 00; inside order of the bits is: 1482 read ignore from all addr except addr 00; inside order of the bits is:
1314 [0] rst_brb1; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5] 1483 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1315 rst_tcm; [6] rst_rbcr; [7] rst_nig; [8] rst_usdm; [9] rst_ucm; [10] 1484 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1316 rst_usem; [11] rst_upb; [12] rst_ccm; [13] rst_csem; [14] rst_csdm; [15] 1485 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1317 rst_rbcu; [16] rst_pbf; [17] rst_qm; [18] rst_tm; [19] rst_dorq; [20] 1486 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1318 rst_xcm; [21] rst_xsdm; [22] rst_xsem; [23] rst_rbct; [24] rst_cdu; [25] 1487 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1319 rst_cfc; [26] rst_pxp; [27] rst_pxpv; [28] rst_rbcp; [29] rst_hc; [30] 1488 rst_pxp_rq_rd_wr; 31:17] reserved */
1320 rst_dmae; [31] rst_semi_rtc; */
1321#define MISC_REG_RESET_REG_1 0xa580
1322#define MISC_REG_RESET_REG_2 0xa590 1489#define MISC_REG_RESET_REG_2 0xa590
1323/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is 1490/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1324 shared with the driver resides */ 1491 shared with the driver resides */
@@ -1345,7 +1512,7 @@
1345 select VAUX supply. (This is an output pin only; it is not controlled by 1512 select VAUX supply. (This is an output pin only; it is not controlled by
1346 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT 1513 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1347 field is not applicable for this pin; only the VALUE fields is relevant - 1514 field is not applicable for this pin; only the VALUE fields is relevant -
1348 it reflects the output value); [3] reserved; [4] spio_4; [5] spio_5; [6] 1515 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1349 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP 1516 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1350 device ID select; read by UMP firmware. */ 1517 device ID select; read by UMP firmware. */
1351#define MISC_REG_SPIO 0xa4fc 1518#define MISC_REG_SPIO 0xa4fc
@@ -1394,8 +1561,9 @@
1394#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8 1561#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1395/* [RW 1] output enable for RX BRB1 LP IF */ 1562/* [RW 1] output enable for RX BRB1 LP IF */
1396#define NIG_REG_BRB_LB_OUT_EN 0x10100 1563#define NIG_REG_BRB_LB_OUT_EN 0x10100
1397/* [WB_W 72] Debug packet to LP from RBC; Data spelling:[63:0] data; 64] 1564/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1398 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush */ 1565 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1566 72:73]-vnic_num; 81:74]-sideband_info */
1399#define NIG_REG_DEBUG_PACKET_LB 0x10800 1567#define NIG_REG_DEBUG_PACKET_LB 0x10800
1400/* [RW 1] Input enable for TX Debug packet */ 1568/* [RW 1] Input enable for TX Debug packet */
1401#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc 1569#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
@@ -1409,6 +1577,8 @@
1409/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs 1577/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1410 to emac for port0; other way to bmac for port0 */ 1578 to emac for port0; other way to bmac for port0 */
1411#define NIG_REG_EGRESS_EMAC0_PORT 0x10058 1579#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1580/* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */
1581#define NIG_REG_EGRESS_MNG0_FIFO 0x1045c
1412/* [RW 1] Input enable for TX PBF user packet port0 IF */ 1582/* [RW 1] Input enable for TX PBF user packet port0 IF */
1413#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc 1583#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1414/* [RW 1] Input enable for TX PBF user packet port1 IF */ 1584/* [RW 1] Input enable for TX PBF user packet port1 IF */
@@ -1438,6 +1608,8 @@
1438#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4 1608#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1439/* [RW 1] led 10g for port 0 */ 1609/* [RW 1] led 10g for port 0 */
1440#define NIG_REG_LED_10G_P0 0x10320 1610#define NIG_REG_LED_10G_P0 0x10320
1611/* [RW 1] led 10g for port 1 */
1612#define NIG_REG_LED_10G_P1 0x10324
1441/* [RW 1] Port0: This bit is set to enable the use of the 1613/* [RW 1] Port0: This bit is set to enable the use of the
1442 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field 1614 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1443 defined below. If this bit is cleared; then the blink rate will be about 1615 defined below. If this bit is cleared; then the blink rate will be about
@@ -1448,7 +1620,7 @@
1448 is reset to 0x080; giving a default blink period of approximately 8Hz. */ 1620 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1449#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310 1621#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1450/* [RW 1] Port0: If set along with the 1622/* [RW 1] Port0: If set along with the
1451 nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 1623 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1452 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED 1624 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1453 bit; the Traffic LED will blink with the blink rate specified in 1625 bit; the Traffic LED will blink with the blink rate specified in
1454 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1626 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
@@ -1470,19 +1642,47 @@
1470/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 1642/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1471 9-11PHY7; 12 MAC4; 13-15 PHY10; */ 1643 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1472#define NIG_REG_LED_MODE_P0 0x102f0 1644#define NIG_REG_LED_MODE_P0 0x102f0
1645#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1646#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
1473#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244 1647#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1648#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
1474/* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1649/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1475#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c 1650#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1651/* [RW 2] Determine the classification participants. 0: no classification.1:
1652 classification upon VLAN id. 2: classification upon MAC address. 3:
1653 classification upon both VLAN id & MAC addr. */
1654#define NIG_REG_LLH0_CLS_TYPE 0x16080
1476/* [RW 32] cm header for llh0 */ 1655/* [RW 32] cm header for llh0 */
1477#define NIG_REG_LLH0_CM_HEADER 0x1007c 1656#define NIG_REG_LLH0_CM_HEADER 0x1007c
1657#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1658#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1659/* [RW 16] destination TCP address 1. The LLH will look for this address in
1660 all incoming packets. */
1661#define NIG_REG_LLH0_DEST_TCP_0 0x10220
1662/* [RW 16] destination UDP address 1 The LLH will look for this address in
1663 all incoming packets. */
1664#define NIG_REG_LLH0_DEST_UDP_0 0x10214
1478#define NIG_REG_LLH0_ERROR_MASK 0x1008c 1665#define NIG_REG_LLH0_ERROR_MASK 0x1008c
1479/* [RW 8] event id for llh0 */ 1666/* [RW 8] event id for llh0 */
1480#define NIG_REG_LLH0_EVENT_ID 0x10084 1667#define NIG_REG_LLH0_EVENT_ID 0x10084
1668#define NIG_REG_LLH0_FUNC_EN 0x160fc
1669#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1670/* [RW 1] Determine the IP version to look for in
1671 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1672#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1673/* [RW 1] t bit for llh0 */
1674#define NIG_REG_LLH0_T_BIT 0x10074
1675/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1676#define NIG_REG_LLH0_VLAN_ID_0 0x1022c
1481/* [RW 8] init credit counter for port0 in LLH */ 1677/* [RW 8] init credit counter for port0 in LLH */
1482#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 1678#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1483#define NIG_REG_LLH0_XCM_MASK 0x10130 1679#define NIG_REG_LLH0_XCM_MASK 0x10130
1484/* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1680/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1485#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc 1681#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1682/* [RW 2] Determine the classification participants. 0: no classification.1:
1683 classification upon VLAN id. 2: classification upon MAC address. 3:
1684 classification upon both VLAN id & MAC addr. */
1685#define NIG_REG_LLH1_CLS_TYPE 0x16084
1486/* [RW 32] cm header for llh1 */ 1686/* [RW 32] cm header for llh1 */
1487#define NIG_REG_LLH1_CM_HEADER 0x10080 1687#define NIG_REG_LLH1_CM_HEADER 0x10080
1488#define NIG_REG_LLH1_ERROR_MASK 0x10090 1688#define NIG_REG_LLH1_ERROR_MASK 0x10090
@@ -1491,13 +1691,26 @@
1491/* [RW 8] init credit counter for port1 in LLH */ 1691/* [RW 8] init credit counter for port1 in LLH */
1492#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564 1692#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1493#define NIG_REG_LLH1_XCM_MASK 0x10134 1693#define NIG_REG_LLH1_XCM_MASK 0x10134
1694/* [RW 1] When this bit is set; the LLH will expect all packets to be with
1695 e1hov */
1696#define NIG_REG_LLH_E1HOV_MODE 0x160d8
1697/* [RW 1] When this bit is set; the LLH will classify the packet before
1698 sending it to the BRB or calculating WoL on it. */
1699#define NIG_REG_LLH_MF_MODE 0x16024
1494#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330 1700#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1495#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334 1701#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1496/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */ 1702/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1497#define NIG_REG_NIG_EMAC0_EN 0x1003c 1703#define NIG_REG_NIG_EMAC0_EN 0x1003c
1704/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1705#define NIG_REG_NIG_EMAC1_EN 0x10040
1498/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the 1706/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1499 EMAC0 to strip the CRC from the ingress packets. */ 1707 EMAC0 to strip the CRC from the ingress packets. */
1500#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 1708#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1709/* [R 32] Interrupt register #0 read */
1710#define NIG_REG_NIG_INT_STS_0 0x103b0
1711#define NIG_REG_NIG_INT_STS_1 0x103c0
1712/* [R 32] Parity register #0 read */
1713#define NIG_REG_NIG_PRTY_STS 0x103d0
1501/* [RW 1] Input enable for RX PBF LP IF */ 1714/* [RW 1] Input enable for RX PBF LP IF */
1502#define NIG_REG_PBF_LB_IN_EN 0x100b4 1715#define NIG_REG_PBF_LB_IN_EN 0x100b4
1503/* [RW 1] Value of this register will be transmitted to port swap when 1716/* [RW 1] Value of this register will be transmitted to port swap when
@@ -1514,9 +1727,21 @@
1514/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 1727/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1515 for port0 */ 1728 for port0 */
1516#define NIG_REG_STAT0_BRB_DISCARD 0x105f0 1729#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1730/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1731 between 1024 and 1522 bytes for port0 */
1732#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
1733/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1734 between 1523 bytes and above for port0 */
1735#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
1517/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 1736/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1518 for port1 */ 1737 for port1 */
1519#define NIG_REG_STAT1_BRB_DISCARD 0x10628 1738#define NIG_REG_STAT1_BRB_DISCARD 0x10628
1739/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1740 between 1024 and 1522 bytes for port1 */
1741#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
1742/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1743 between 1523 bytes and above for port1 */
1744#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
1520/* [WB_R 64] Rx statistics : User octets received for LP */ 1745/* [WB_R 64] Rx statistics : User octets received for LP */
1521#define NIG_REG_STAT2_BRB_OCTET 0x107e0 1746#define NIG_REG_STAT2_BRB_OCTET 0x107e0
1522#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 1747#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
@@ -1529,8 +1754,12 @@
1529#define NIG_REG_XCM0_OUT_EN 0x100f0 1754#define NIG_REG_XCM0_OUT_EN 0x100f0
1530/* [RW 1] output enable for RX_XCM1 IF */ 1755/* [RW 1] output enable for RX_XCM1 IF */
1531#define NIG_REG_XCM1_OUT_EN 0x100f4 1756#define NIG_REG_XCM1_OUT_EN 0x100f4
1757/* [RW 1] control to xgxs - remote PHY in-band MDIO */
1758#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
1532/* [RW 5] control to xgxs - CL45 DEVAD */ 1759/* [RW 5] control to xgxs - CL45 DEVAD */
1533#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c 1760#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
1761/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
1762#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
1534/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */ 1763/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1535#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340 1764#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1536/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */ 1765/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
@@ -1626,7 +1855,6 @@
1626#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c 1855#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1627/* [RW 24] CID for port 0 if no match */ 1856/* [RW 24] CID for port 0 if no match */
1628#define PRS_REG_CID_PORT_0 0x400fc 1857#define PRS_REG_CID_PORT_0 0x400fc
1629#define PRS_REG_CID_PORT_1 0x40100
1630/* [RW 32] The CM header for flush message where 'load existed' bit in CFC 1858/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1631 load response is reset and packet type is 0. Used in packet start message 1859 load response is reset and packet type is 0. Used in packet start message
1632 to TCM. */ 1860 to TCM. */
@@ -1658,11 +1886,15 @@
1658#define PRS_REG_CM_HDR_TYPE_4 0x40088 1886#define PRS_REG_CM_HDR_TYPE_4 0x40088
1659/* [RW 32] The CM header in case there was not a match on the connection */ 1887/* [RW 32] The CM header in case there was not a match on the connection */
1660#define PRS_REG_CM_NO_MATCH_HDR 0x400b8 1888#define PRS_REG_CM_NO_MATCH_HDR 0x400b8
1889/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
1890#define PRS_REG_E1HOV_MODE 0x401c8
1661/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet 1891/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
1662 start message to TCM. */ 1892 start message to TCM. */
1663#define PRS_REG_EVENT_ID_1 0x40054 1893#define PRS_REG_EVENT_ID_1 0x40054
1664#define PRS_REG_EVENT_ID_2 0x40058 1894#define PRS_REG_EVENT_ID_2 0x40058
1665#define PRS_REG_EVENT_ID_3 0x4005c 1895#define PRS_REG_EVENT_ID_3 0x4005c
1896/* [RW 16] The Ethernet type value for FCoE */
1897#define PRS_REG_FCOE_TYPE 0x401d0
1666/* [RW 8] Context region for flush packet with packet type 0. Used in CFC 1898/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
1667 load request message. */ 1899 load request message. */
1668#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004 1900#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
@@ -1730,8 +1962,17 @@
1730#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c 1962#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
1731/* [R 7] Debug only: Number of used entries in the header FIFO */ 1963/* [R 7] Debug only: Number of used entries in the header FIFO */
1732#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478 1964#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
1965#define PXP2_REG_PGL_ADDR_88_F0 0x120534
1966#define PXP2_REG_PGL_ADDR_8C_F0 0x120538
1967#define PXP2_REG_PGL_ADDR_90_F0 0x12053c
1968#define PXP2_REG_PGL_ADDR_94_F0 0x120540
1733#define PXP2_REG_PGL_CONTROL0 0x120490 1969#define PXP2_REG_PGL_CONTROL0 0x120490
1734#define PXP2_REG_PGL_CONTROL1 0x120514 1970#define PXP2_REG_PGL_CONTROL1 0x120514
1971/* [RW 32] third dword data of expansion rom request. this register is
1972 special. reading from it provides a vector outstanding read requests. if
1973 a bit is zero it means that a read request on the corresponding tag did
1974 not finish yet (not all completions have arrived for it) */
1975#define PXP2_REG_PGL_EXP_ROM2 0x120808
1735/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask; 1976/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
1736 its[15:0]-address */ 1977 its[15:0]-address */
1737#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4 1978#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
@@ -1775,8 +2016,7 @@
1775/* [R 1] this bit indicates that a read request was blocked because of 2016/* [R 1] this bit indicates that a read request was blocked because of
1776 bus_master_en was deasserted */ 2017 bus_master_en was deasserted */
1777#define PXP2_REG_PGL_READ_BLOCKED 0x120568 2018#define PXP2_REG_PGL_READ_BLOCKED 0x120568
1778/* [R 6] debug only */ 2019#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
1779#define PXP2_REG_PGL_TXR_CDTS 0x120528
1780/* [R 18] debug only */ 2020/* [R 18] debug only */
1781#define PXP2_REG_PGL_TXW_CDTS 0x12052c 2021#define PXP2_REG_PGL_TXW_CDTS 0x12052c
1782/* [R 1] this bit indicates that a write request was blocked because of 2022/* [R 1] this bit indicates that a write request was blocked because of
@@ -1828,12 +2068,14 @@
1828#define PXP2_REG_PSWRQ_QM0_L2P 0x120038 2068#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
1829#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054 2069#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
1830#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c 2070#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
1831/* [RW 25] Interrupt mask register #0 read/write */ 2071#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
1832#define PXP2_REG_PXP2_INT_MASK 0x120578 2072/* [RW 32] Interrupt mask register #0 read/write */
1833/* [R 25] Interrupt register #0 read */ 2073#define PXP2_REG_PXP2_INT_MASK_0 0x120578
1834#define PXP2_REG_PXP2_INT_STS 0x12056c 2074/* [R 32] Interrupt register #0 read */
1835/* [RC 25] Interrupt register #0 read clear */ 2075#define PXP2_REG_PXP2_INT_STS_0 0x12056c
1836#define PXP2_REG_PXP2_INT_STS_CLR 0x120570 2076#define PXP2_REG_PXP2_INT_STS_1 0x120608
2077/* [RC 32] Interrupt register #0 read clear */
2078#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
1837/* [RW 32] Parity mask register #0 read/write */ 2079/* [RW 32] Parity mask register #0 read/write */
1838#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 2080#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
1839#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 2081#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
@@ -2016,8 +2258,12 @@
2016#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4 2258#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2017/* [RW 7] Bandwidth upper bound for VQ30 */ 2259/* [RW 7] Bandwidth upper bound for VQ30 */
2018#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8 2260#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
2261/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
2262#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
2019/* [RW 2] Endian mode for cdu */ 2263/* [RW 2] Endian mode for cdu */
2020#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0 2264#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
2265#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
2266#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
2021/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k; 2267/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2022 -128k */ 2268 -128k */
2023#define PXP2_REG_RQ_CDU_P_SIZE 0x120018 2269#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
@@ -2029,14 +2275,26 @@
2029/* [RW 1] When '1'; requests will enter input buffers but wont get out 2275/* [RW 1] When '1'; requests will enter input buffers but wont get out
2030 towards the glue */ 2276 towards the glue */
2031#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330 2277#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
2278/* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */
2279#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
2280/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
2281 be asserted */
2282#define PXP2_REG_RQ_ELT_DISABLE 0x12066c
2032/* [RW 2] Endian mode for hc */ 2283/* [RW 2] Endian mode for hc */
2033#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 2284#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
2285/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
2286 compatibility needs; Note that different registers are used per mode */
2287#define PXP2_REG_RQ_ILT_MODE 0x1205b4
2034/* [WB 53] Onchip address table */ 2288/* [WB 53] Onchip address table */
2035#define PXP2_REG_RQ_ONCHIP_AT 0x122000 2289#define PXP2_REG_RQ_ONCHIP_AT 0x122000
2290/* [WB 53] Onchip address table - B0 */
2291#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
2036/* [RW 13] Pending read limiter threshold; in Dwords */ 2292/* [RW 13] Pending read limiter threshold; in Dwords */
2037#define PXP2_REG_RQ_PDR_LIMIT 0x12033c 2293#define PXP2_REG_RQ_PDR_LIMIT 0x12033c
2038/* [RW 2] Endian mode for qm */ 2294/* [RW 2] Endian mode for qm */
2039#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 2295#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
2296#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
2297#define PXP2_REG_RQ_QM_LAST_ILT 0x120638
2040/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; 2298/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2041 -128k */ 2299 -128k */
2042#define PXP2_REG_RQ_QM_P_SIZE 0x120050 2300#define PXP2_REG_RQ_QM_P_SIZE 0x120050
@@ -2050,16 +2308,22 @@
2050#define PXP2_REG_RQ_RD_MBS1 0x120168 2308#define PXP2_REG_RQ_RD_MBS1 0x120168
2051/* [RW 2] Endian mode for src */ 2309/* [RW 2] Endian mode for src */
2052#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c 2310#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
2311#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
2312#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
2053/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; 2313/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2054 -128k */ 2314 -128k */
2055#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c 2315#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2056/* [RW 2] Endian mode for tm */ 2316/* [RW 2] Endian mode for tm */
2057#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198 2317#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
2318#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
2319#define PXP2_REG_RQ_TM_LAST_ILT 0x120648
2058/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k; 2320/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2059 -128k */ 2321 -128k */
2060#define PXP2_REG_RQ_TM_P_SIZE 0x120034 2322#define PXP2_REG_RQ_TM_P_SIZE 0x120034
2061/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */ 2323/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2062#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c 2324#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
2325/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
2326#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
2063/* [R 8] Number of entries occupied by vq 0 in pswrq memory */ 2327/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2064#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810 2328#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2065/* [R 8] Number of entries occupied by vq 10 in pswrq memory */ 2329/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
@@ -2130,19 +2394,63 @@
2130/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; 2394/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2131 001:256B; 010: 512B; */ 2395 001:256B; 010: 512B; */
2132#define PXP2_REG_RQ_WR_MBS1 0x120164 2396#define PXP2_REG_RQ_WR_MBS1 0x120164
2397/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2398 buffer reaches this number has_payload will be asserted */
2399#define PXP2_REG_WR_CDU_MPS 0x1205f0
2400/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2401 buffer reaches this number has_payload will be asserted */
2402#define PXP2_REG_WR_CSDM_MPS 0x1205d0
2403/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2404 buffer reaches this number has_payload will be asserted */
2405#define PXP2_REG_WR_DBG_MPS 0x1205e8
2406/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2407 buffer reaches this number has_payload will be asserted */
2408#define PXP2_REG_WR_DMAE_MPS 0x1205ec
2133/* [RW 10] if Number of entries in dmae fifo will be higer than this 2409/* [RW 10] if Number of entries in dmae fifo will be higer than this
2134 threshold then has_payload indication will be asserted; the default value 2410 threshold then has_payload indication will be asserted; the default value
2135 should be equal to &gt; write MBS size! */ 2411 should be equal to &gt; write MBS size! */
2136#define PXP2_REG_WR_DMAE_TH 0x120368 2412#define PXP2_REG_WR_DMAE_TH 0x120368
2413/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2414 buffer reaches this number has_payload will be asserted */
2415#define PXP2_REG_WR_HC_MPS 0x1205c8
2416/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2417 buffer reaches this number has_payload will be asserted */
2418#define PXP2_REG_WR_QM_MPS 0x1205dc
2419/* [RW 1] 0 - working in A0 mode; - working in B0 mode */
2420#define PXP2_REG_WR_REV_MODE 0x120670
2421/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2422 buffer reaches this number has_payload will be asserted */
2423#define PXP2_REG_WR_SRC_MPS 0x1205e4
2424/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2425 buffer reaches this number has_payload will be asserted */
2426#define PXP2_REG_WR_TM_MPS 0x1205e0
2427/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2428 buffer reaches this number has_payload will be asserted */
2429#define PXP2_REG_WR_TSDM_MPS 0x1205d4
2137/* [RW 10] if Number of entries in usdmdp fifo will be higer than this 2430/* [RW 10] if Number of entries in usdmdp fifo will be higer than this
2138 threshold then has_payload indication will be asserted; the default value 2431 threshold then has_payload indication will be asserted; the default value
2139 should be equal to &gt; write MBS size! */ 2432 should be equal to &gt; write MBS size! */
2140#define PXP2_REG_WR_USDMDP_TH 0x120348 2433#define PXP2_REG_WR_USDMDP_TH 0x120348
2434/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2435 buffer reaches this number has_payload will be asserted */
2436#define PXP2_REG_WR_USDM_MPS 0x1205cc
2437/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2438 buffer reaches this number has_payload will be asserted */
2439#define PXP2_REG_WR_XSDM_MPS 0x1205d8
2141/* [R 1] debug only: Indication if PSWHST arbiter is idle */ 2440/* [R 1] debug only: Indication if PSWHST arbiter is idle */
2142#define PXP_REG_HST_ARB_IS_IDLE 0x103004 2441#define PXP_REG_HST_ARB_IS_IDLE 0x103004
2143/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means 2442/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2144 this client is waiting for the arbiter. */ 2443 this client is waiting for the arbiter. */
2145#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008 2444#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
2445/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
2446 should update accoring to 'hst_discard_doorbells' register when the state
2447 machine is idle */
2448#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
2449/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
2450 means this PSWHST is discarding inputs from this client. Each bit should
2451 update accoring to 'hst_discard_internal_writes' register when the state
2452 machine is idle. */
2453#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
2146/* [WB 160] Used for initialization of the inbound interrupts memory */ 2454/* [WB 160] Used for initialization of the inbound interrupts memory */
2147#define PXP_REG_HST_INBOUND_INT 0x103800 2455#define PXP_REG_HST_INBOUND_INT 0x103800
2148/* [RW 32] Interrupt mask register #0 read/write */ 2456/* [RW 32] Interrupt mask register #0 read/write */
@@ -2165,18 +2473,25 @@
2165#define QM_REG_ACTCTRINITVAL_3 0x16804c 2473#define QM_REG_ACTCTRINITVAL_3 0x16804c
2166/* [RW 32] The base logical address (in bytes) of each physical queue. The 2474/* [RW 32] The base logical address (in bytes) of each physical queue. The
2167 index I represents the physical queue number. The 12 lsbs are ignore and 2475 index I represents the physical queue number. The 12 lsbs are ignore and
2168 considered zero so practically there are only 20 bits in this register. */ 2476 considered zero so practically there are only 20 bits in this register;
2477 queues 63-0 */
2169#define QM_REG_BASEADDR 0x168900 2478#define QM_REG_BASEADDR 0x168900
2170/* [RW 16] The byte credit cost for each task. This value is for both ports */ 2479/* [RW 16] The byte credit cost for each task. This value is for both ports */
2171#define QM_REG_BYTECRDCOST 0x168234 2480#define QM_REG_BYTECRDCOST 0x168234
2172/* [RW 16] The initial byte credit value for both ports. */ 2481/* [RW 16] The initial byte credit value for both ports. */
2173#define QM_REG_BYTECRDINITVAL 0x168238 2482#define QM_REG_BYTECRDINITVAL 0x168238
2174/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 2483/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2175 queue uses port 0 else it uses port 1. */ 2484 queue uses port 0 else it uses port 1; queues 31-0 */
2176#define QM_REG_BYTECRDPORT_LSB 0x168228 2485#define QM_REG_BYTECRDPORT_LSB 0x168228
2177/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 2486/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2178 queue uses port 0 else it uses port 1. */ 2487 queue uses port 0 else it uses port 1; queues 95-64 */
2488#define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
2489/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2490 queue uses port 0 else it uses port 1; queues 63-32 */
2179#define QM_REG_BYTECRDPORT_MSB 0x168224 2491#define QM_REG_BYTECRDPORT_MSB 0x168224
2492/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2493 queue uses port 0 else it uses port 1; queues 127-96 */
2494#define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
2180/* [RW 16] The byte credit value that if above the QM is considered almost 2495/* [RW 16] The byte credit value that if above the QM is considered almost
2181 full */ 2496 full */
2182#define QM_REG_BYTECREDITAFULLTHR 0x168094 2497#define QM_REG_BYTECREDITAFULLTHR 0x168094
@@ -2203,7 +2518,7 @@
2203#define QM_REG_CMINTVOQMASK_6 0x16820c 2518#define QM_REG_CMINTVOQMASK_6 0x16820c
2204#define QM_REG_CMINTVOQMASK_7 0x168210 2519#define QM_REG_CMINTVOQMASK_7 0x168210
2205/* [RW 20] The number of connections divided by 16 which dictates the size 2520/* [RW 20] The number of connections divided by 16 which dictates the size
2206 of each queue per port 0 */ 2521 of each queue which belongs to even function number. */
2207#define QM_REG_CONNNUM_0 0x168020 2522#define QM_REG_CONNNUM_0 0x168020
2208/* [R 6] Keep the fill level of the fifo from write client 4 */ 2523/* [R 6] Keep the fill level of the fifo from write client 4 */
2209#define QM_REG_CQM_WRC_FIFOLVL 0x168018 2524#define QM_REG_CQM_WRC_FIFOLVL 0x168018
@@ -2216,74 +2531,179 @@
2216 bypass enable */ 2531 bypass enable */
2217#define QM_REG_ENBYPVOQMASK 0x16823c 2532#define QM_REG_ENBYPVOQMASK 0x16823c
2218/* [RW 32] A bit mask per each physical queue. If a bit is set then the 2533/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2219 physical queue uses the byte credit */ 2534 physical queue uses the byte credit; queues 31-0 */
2220#define QM_REG_ENBYTECRD_LSB 0x168220 2535#define QM_REG_ENBYTECRD_LSB 0x168220
2221/* [RW 32] A bit mask per each physical queue. If a bit is set then the 2536/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2222 physical queue uses the byte credit */ 2537 physical queue uses the byte credit; queues 95-64 */
2538#define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
2539/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2540 physical queue uses the byte credit; queues 63-32 */
2223#define QM_REG_ENBYTECRD_MSB 0x16821c 2541#define QM_REG_ENBYTECRD_MSB 0x16821c
2542/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2543 physical queue uses the byte credit; queues 127-96 */
2544#define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
2224/* [RW 4] If cleared then the secondary interface will not be served by the 2545/* [RW 4] If cleared then the secondary interface will not be served by the
2225 RR arbiter */ 2546 RR arbiter */
2226#define QM_REG_ENSEC 0x1680f0 2547#define QM_REG_ENSEC 0x1680f0
2227/* [RW 32] A bit vector per each physical queue which selects which function 2548/* [RW 32] NA */
2228 number to use on PCI access for that queue. */
2229#define QM_REG_FUNCNUMSEL_LSB 0x168230 2549#define QM_REG_FUNCNUMSEL_LSB 0x168230
2230/* [RW 32] A bit vector per each physical queue which selects which function 2550/* [RW 32] NA */
2231 number to use on PCI access for that queue. */
2232#define QM_REG_FUNCNUMSEL_MSB 0x16822c 2551#define QM_REG_FUNCNUMSEL_MSB 0x16822c
2233/* [RW 32] A mask register to mask the Almost empty signals which will not 2552/* [RW 32] A mask register to mask the Almost empty signals which will not
2234 be use for the almost empty indication to the HW block */ 2553 be use for the almost empty indication to the HW block; queues 31:0 */
2235#define QM_REG_HWAEMPTYMASK_LSB 0x168218 2554#define QM_REG_HWAEMPTYMASK_LSB 0x168218
2236/* [RW 32] A mask register to mask the Almost empty signals which will not 2555/* [RW 32] A mask register to mask the Almost empty signals which will not
2237 be use for the almost empty indication to the HW block */ 2556 be use for the almost empty indication to the HW block; queues 95-64 */
2557#define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
2558/* [RW 32] A mask register to mask the Almost empty signals which will not
2559 be use for the almost empty indication to the HW block; queues 63:32 */
2238#define QM_REG_HWAEMPTYMASK_MSB 0x168214 2560#define QM_REG_HWAEMPTYMASK_MSB 0x168214
2561/* [RW 32] A mask register to mask the Almost empty signals which will not
2562 be use for the almost empty indication to the HW block; queues 127-96 */
2563#define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
2239/* [RW 4] The number of outstanding request to CFC */ 2564/* [RW 4] The number of outstanding request to CFC */
2240#define QM_REG_OUTLDREQ 0x168804 2565#define QM_REG_OUTLDREQ 0x168804
2241/* [RC 1] A flag to indicate that overflow error occurred in one of the 2566/* [RC 1] A flag to indicate that overflow error occurred in one of the
2242 queues. */ 2567 queues. */
2243#define QM_REG_OVFERROR 0x16805c 2568#define QM_REG_OVFERROR 0x16805c
2244/* [RC 6] the Q were the qverflow occurs */ 2569/* [RC 7] the Q were the qverflow occurs */
2245#define QM_REG_OVFQNUM 0x168058 2570#define QM_REG_OVFQNUM 0x168058
2246/* [R 32] Pause state for physical queues 31-0 */ 2571/* [R 16] Pause state for physical queues 15-0 */
2247#define QM_REG_PAUSESTATE0 0x168410 2572#define QM_REG_PAUSESTATE0 0x168410
2248/* [R 32] Pause state for physical queues 64-32 */ 2573/* [R 16] Pause state for physical queues 31-16 */
2249#define QM_REG_PAUSESTATE1 0x168414 2574#define QM_REG_PAUSESTATE1 0x168414
2575/* [R 16] Pause state for physical queues 47-32 */
2576#define QM_REG_PAUSESTATE2 0x16e684
2577/* [R 16] Pause state for physical queues 63-48 */
2578#define QM_REG_PAUSESTATE3 0x16e688
2579/* [R 16] Pause state for physical queues 79-64 */
2580#define QM_REG_PAUSESTATE4 0x16e68c
2581/* [R 16] Pause state for physical queues 95-80 */
2582#define QM_REG_PAUSESTATE5 0x16e690
2583/* [R 16] Pause state for physical queues 111-96 */
2584#define QM_REG_PAUSESTATE6 0x16e694
2585/* [R 16] Pause state for physical queues 127-112 */
2586#define QM_REG_PAUSESTATE7 0x16e698
2250/* [RW 2] The PCI attributes field used in the PCI request. */ 2587/* [RW 2] The PCI attributes field used in the PCI request. */
2251#define QM_REG_PCIREQAT 0x168054 2588#define QM_REG_PCIREQAT 0x168054
2252/* [R 16] The byte credit of port 0 */ 2589/* [R 16] The byte credit of port 0 */
2253#define QM_REG_PORT0BYTECRD 0x168300 2590#define QM_REG_PORT0BYTECRD 0x168300
2254/* [R 16] The byte credit of port 1 */ 2591/* [R 16] The byte credit of port 1 */
2255#define QM_REG_PORT1BYTECRD 0x168304 2592#define QM_REG_PORT1BYTECRD 0x168304
2256/* [WB 54] Pointer Table Memory; The mapping is as follow: ptrtbl[53:30] 2593/* [RW 3] pci function number of queues 15-0 */
2257 read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0; 2594#define QM_REG_PQ2PCIFUNC_0 0x16e6bc
2258 ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 2595#define QM_REG_PQ2PCIFUNC_1 0x16e6c0
2596#define QM_REG_PQ2PCIFUNC_2 0x16e6c4
2597#define QM_REG_PQ2PCIFUNC_3 0x16e6c8
2598#define QM_REG_PQ2PCIFUNC_4 0x16e6cc
2599#define QM_REG_PQ2PCIFUNC_5 0x16e6d0
2600#define QM_REG_PQ2PCIFUNC_6 0x16e6d4
2601#define QM_REG_PQ2PCIFUNC_7 0x16e6d8
2602/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
2603 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2604 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2259#define QM_REG_PTRTBL 0x168a00 2605#define QM_REG_PTRTBL 0x168a00
2606/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
2607 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2608 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2609#define QM_REG_PTRTBL_EXT_A 0x16e200
2260/* [RW 2] Interrupt mask register #0 read/write */ 2610/* [RW 2] Interrupt mask register #0 read/write */
2261#define QM_REG_QM_INT_MASK 0x168444 2611#define QM_REG_QM_INT_MASK 0x168444
2262/* [R 2] Interrupt register #0 read */ 2612/* [R 2] Interrupt register #0 read */
2263#define QM_REG_QM_INT_STS 0x168438 2613#define QM_REG_QM_INT_STS 0x168438
2264/* [RW 9] Parity mask register #0 read/write */ 2614/* [RW 12] Parity mask register #0 read/write */
2265#define QM_REG_QM_PRTY_MASK 0x168454 2615#define QM_REG_QM_PRTY_MASK 0x168454
2266/* [R 9] Parity register #0 read */ 2616/* [R 12] Parity register #0 read */
2267#define QM_REG_QM_PRTY_STS 0x168448 2617#define QM_REG_QM_PRTY_STS 0x168448
2268/* [R 32] Current queues in pipeline: Queues from 32 to 63 */ 2618/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2269#define QM_REG_QSTATUS_HIGH 0x16802c 2619#define QM_REG_QSTATUS_HIGH 0x16802c
2620/* [R 32] Current queues in pipeline: Queues from 96 to 127 */
2621#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
2270/* [R 32] Current queues in pipeline: Queues from 0 to 31 */ 2622/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2271#define QM_REG_QSTATUS_LOW 0x168028 2623#define QM_REG_QSTATUS_LOW 0x168028
2272/* [R 24] The number of tasks queued for each queue */ 2624/* [R 32] Current queues in pipeline: Queues from 64 to 95 */
2625#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
2626/* [R 24] The number of tasks queued for each queue; queues 63-0 */
2273#define QM_REG_QTASKCTR_0 0x168308 2627#define QM_REG_QTASKCTR_0 0x168308
2628/* [R 24] The number of tasks queued for each queue; queues 127-64 */
2629#define QM_REG_QTASKCTR_EXT_A_0 0x16e584
2274/* [RW 4] Queue tied to VOQ */ 2630/* [RW 4] Queue tied to VOQ */
2275#define QM_REG_QVOQIDX_0 0x1680f4 2631#define QM_REG_QVOQIDX_0 0x1680f4
2276#define QM_REG_QVOQIDX_10 0x16811c 2632#define QM_REG_QVOQIDX_10 0x16811c
2633#define QM_REG_QVOQIDX_100 0x16e49c
2634#define QM_REG_QVOQIDX_101 0x16e4a0
2635#define QM_REG_QVOQIDX_102 0x16e4a4
2636#define QM_REG_QVOQIDX_103 0x16e4a8
2637#define QM_REG_QVOQIDX_104 0x16e4ac
2638#define QM_REG_QVOQIDX_105 0x16e4b0
2639#define QM_REG_QVOQIDX_106 0x16e4b4
2640#define QM_REG_QVOQIDX_107 0x16e4b8
2641#define QM_REG_QVOQIDX_108 0x16e4bc
2642#define QM_REG_QVOQIDX_109 0x16e4c0
2643#define QM_REG_QVOQIDX_100 0x16e49c
2644#define QM_REG_QVOQIDX_101 0x16e4a0
2645#define QM_REG_QVOQIDX_102 0x16e4a4
2646#define QM_REG_QVOQIDX_103 0x16e4a8
2647#define QM_REG_QVOQIDX_104 0x16e4ac
2648#define QM_REG_QVOQIDX_105 0x16e4b0
2649#define QM_REG_QVOQIDX_106 0x16e4b4
2650#define QM_REG_QVOQIDX_107 0x16e4b8
2651#define QM_REG_QVOQIDX_108 0x16e4bc
2652#define QM_REG_QVOQIDX_109 0x16e4c0
2277#define QM_REG_QVOQIDX_11 0x168120 2653#define QM_REG_QVOQIDX_11 0x168120
2654#define QM_REG_QVOQIDX_110 0x16e4c4
2655#define QM_REG_QVOQIDX_111 0x16e4c8
2656#define QM_REG_QVOQIDX_112 0x16e4cc
2657#define QM_REG_QVOQIDX_113 0x16e4d0
2658#define QM_REG_QVOQIDX_114 0x16e4d4
2659#define QM_REG_QVOQIDX_115 0x16e4d8
2660#define QM_REG_QVOQIDX_116 0x16e4dc
2661#define QM_REG_QVOQIDX_117 0x16e4e0
2662#define QM_REG_QVOQIDX_118 0x16e4e4
2663#define QM_REG_QVOQIDX_119 0x16e4e8
2664#define QM_REG_QVOQIDX_110 0x16e4c4
2665#define QM_REG_QVOQIDX_111 0x16e4c8
2666#define QM_REG_QVOQIDX_112 0x16e4cc
2667#define QM_REG_QVOQIDX_113 0x16e4d0
2668#define QM_REG_QVOQIDX_114 0x16e4d4
2669#define QM_REG_QVOQIDX_115 0x16e4d8
2670#define QM_REG_QVOQIDX_116 0x16e4dc
2671#define QM_REG_QVOQIDX_117 0x16e4e0
2672#define QM_REG_QVOQIDX_118 0x16e4e4
2673#define QM_REG_QVOQIDX_119 0x16e4e8
2278#define QM_REG_QVOQIDX_12 0x168124 2674#define QM_REG_QVOQIDX_12 0x168124
2675#define QM_REG_QVOQIDX_120 0x16e4ec
2676#define QM_REG_QVOQIDX_121 0x16e4f0
2677#define QM_REG_QVOQIDX_122 0x16e4f4
2678#define QM_REG_QVOQIDX_123 0x16e4f8
2679#define QM_REG_QVOQIDX_124 0x16e4fc
2680#define QM_REG_QVOQIDX_125 0x16e500
2681#define QM_REG_QVOQIDX_126 0x16e504
2682#define QM_REG_QVOQIDX_127 0x16e508
2683#define QM_REG_QVOQIDX_120 0x16e4ec
2684#define QM_REG_QVOQIDX_121 0x16e4f0
2685#define QM_REG_QVOQIDX_122 0x16e4f4
2686#define QM_REG_QVOQIDX_123 0x16e4f8
2687#define QM_REG_QVOQIDX_124 0x16e4fc
2688#define QM_REG_QVOQIDX_125 0x16e500
2689#define QM_REG_QVOQIDX_126 0x16e504
2690#define QM_REG_QVOQIDX_127 0x16e508
2279#define QM_REG_QVOQIDX_13 0x168128 2691#define QM_REG_QVOQIDX_13 0x168128
2280#define QM_REG_QVOQIDX_14 0x16812c 2692#define QM_REG_QVOQIDX_14 0x16812c
2281#define QM_REG_QVOQIDX_15 0x168130 2693#define QM_REG_QVOQIDX_15 0x168130
2282#define QM_REG_QVOQIDX_16 0x168134 2694#define QM_REG_QVOQIDX_16 0x168134
2283#define QM_REG_QVOQIDX_17 0x168138 2695#define QM_REG_QVOQIDX_17 0x168138
2284#define QM_REG_QVOQIDX_21 0x168148 2696#define QM_REG_QVOQIDX_21 0x168148
2697#define QM_REG_QVOQIDX_22 0x16814c
2698#define QM_REG_QVOQIDX_23 0x168150
2699#define QM_REG_QVOQIDX_24 0x168154
2285#define QM_REG_QVOQIDX_25 0x168158 2700#define QM_REG_QVOQIDX_25 0x168158
2701#define QM_REG_QVOQIDX_26 0x16815c
2702#define QM_REG_QVOQIDX_27 0x168160
2703#define QM_REG_QVOQIDX_28 0x168164
2286#define QM_REG_QVOQIDX_29 0x168168 2704#define QM_REG_QVOQIDX_29 0x168168
2705#define QM_REG_QVOQIDX_30 0x16816c
2706#define QM_REG_QVOQIDX_31 0x168170
2287#define QM_REG_QVOQIDX_32 0x168174 2707#define QM_REG_QVOQIDX_32 0x168174
2288#define QM_REG_QVOQIDX_33 0x168178 2708#define QM_REG_QVOQIDX_33 0x168178
2289#define QM_REG_QVOQIDX_34 0x16817c 2709#define QM_REG_QVOQIDX_34 0x16817c
@@ -2328,17 +2748,79 @@
2328#define QM_REG_QVOQIDX_61 0x1681e8 2748#define QM_REG_QVOQIDX_61 0x1681e8
2329#define QM_REG_QVOQIDX_62 0x1681ec 2749#define QM_REG_QVOQIDX_62 0x1681ec
2330#define QM_REG_QVOQIDX_63 0x1681f0 2750#define QM_REG_QVOQIDX_63 0x1681f0
2751#define QM_REG_QVOQIDX_64 0x16e40c
2752#define QM_REG_QVOQIDX_65 0x16e410
2753#define QM_REG_QVOQIDX_66 0x16e414
2754#define QM_REG_QVOQIDX_67 0x16e418
2755#define QM_REG_QVOQIDX_68 0x16e41c
2756#define QM_REG_QVOQIDX_69 0x16e420
2331#define QM_REG_QVOQIDX_60 0x1681e4 2757#define QM_REG_QVOQIDX_60 0x1681e4
2332#define QM_REG_QVOQIDX_61 0x1681e8 2758#define QM_REG_QVOQIDX_61 0x1681e8
2333#define QM_REG_QVOQIDX_62 0x1681ec 2759#define QM_REG_QVOQIDX_62 0x1681ec
2334#define QM_REG_QVOQIDX_63 0x1681f0 2760#define QM_REG_QVOQIDX_63 0x1681f0
2761#define QM_REG_QVOQIDX_64 0x16e40c
2762#define QM_REG_QVOQIDX_65 0x16e410
2763#define QM_REG_QVOQIDX_69 0x16e420
2335#define QM_REG_QVOQIDX_7 0x168110 2764#define QM_REG_QVOQIDX_7 0x168110
2765#define QM_REG_QVOQIDX_70 0x16e424
2766#define QM_REG_QVOQIDX_71 0x16e428
2767#define QM_REG_QVOQIDX_72 0x16e42c
2768#define QM_REG_QVOQIDX_73 0x16e430
2769#define QM_REG_QVOQIDX_74 0x16e434
2770#define QM_REG_QVOQIDX_75 0x16e438
2771#define QM_REG_QVOQIDX_76 0x16e43c
2772#define QM_REG_QVOQIDX_77 0x16e440
2773#define QM_REG_QVOQIDX_78 0x16e444
2774#define QM_REG_QVOQIDX_79 0x16e448
2775#define QM_REG_QVOQIDX_70 0x16e424
2776#define QM_REG_QVOQIDX_71 0x16e428
2777#define QM_REG_QVOQIDX_72 0x16e42c
2778#define QM_REG_QVOQIDX_73 0x16e430
2779#define QM_REG_QVOQIDX_74 0x16e434
2780#define QM_REG_QVOQIDX_75 0x16e438
2781#define QM_REG_QVOQIDX_76 0x16e43c
2782#define QM_REG_QVOQIDX_77 0x16e440
2783#define QM_REG_QVOQIDX_78 0x16e444
2784#define QM_REG_QVOQIDX_79 0x16e448
2336#define QM_REG_QVOQIDX_8 0x168114 2785#define QM_REG_QVOQIDX_8 0x168114
2786#define QM_REG_QVOQIDX_80 0x16e44c
2787#define QM_REG_QVOQIDX_81 0x16e450
2788#define QM_REG_QVOQIDX_82 0x16e454
2789#define QM_REG_QVOQIDX_83 0x16e458
2790#define QM_REG_QVOQIDX_84 0x16e45c
2791#define QM_REG_QVOQIDX_85 0x16e460
2792#define QM_REG_QVOQIDX_86 0x16e464
2793#define QM_REG_QVOQIDX_87 0x16e468
2794#define QM_REG_QVOQIDX_88 0x16e46c
2795#define QM_REG_QVOQIDX_89 0x16e470
2796#define QM_REG_QVOQIDX_80 0x16e44c
2797#define QM_REG_QVOQIDX_81 0x16e450
2798#define QM_REG_QVOQIDX_85 0x16e460
2799#define QM_REG_QVOQIDX_86 0x16e464
2800#define QM_REG_QVOQIDX_87 0x16e468
2801#define QM_REG_QVOQIDX_88 0x16e46c
2802#define QM_REG_QVOQIDX_89 0x16e470
2337#define QM_REG_QVOQIDX_9 0x168118 2803#define QM_REG_QVOQIDX_9 0x168118
2338/* [R 24] Remaining pause timeout for port 0 */ 2804#define QM_REG_QVOQIDX_90 0x16e474
2339#define QM_REG_REMAINPAUSETM0 0x168418 2805#define QM_REG_QVOQIDX_91 0x16e478
2340/* [R 24] Remaining pause timeout for port 1 */ 2806#define QM_REG_QVOQIDX_92 0x16e47c
2341#define QM_REG_REMAINPAUSETM1 0x16841c 2807#define QM_REG_QVOQIDX_93 0x16e480
2808#define QM_REG_QVOQIDX_94 0x16e484
2809#define QM_REG_QVOQIDX_95 0x16e488
2810#define QM_REG_QVOQIDX_96 0x16e48c
2811#define QM_REG_QVOQIDX_97 0x16e490
2812#define QM_REG_QVOQIDX_98 0x16e494
2813#define QM_REG_QVOQIDX_99 0x16e498
2814#define QM_REG_QVOQIDX_90 0x16e474
2815#define QM_REG_QVOQIDX_91 0x16e478
2816#define QM_REG_QVOQIDX_92 0x16e47c
2817#define QM_REG_QVOQIDX_93 0x16e480
2818#define QM_REG_QVOQIDX_94 0x16e484
2819#define QM_REG_QVOQIDX_95 0x16e488
2820#define QM_REG_QVOQIDX_96 0x16e48c
2821#define QM_REG_QVOQIDX_97 0x16e490
2822#define QM_REG_QVOQIDX_98 0x16e494
2823#define QM_REG_QVOQIDX_99 0x16e498
2342/* [RW 1] Initialization bit command */ 2824/* [RW 1] Initialization bit command */
2343#define QM_REG_SOFT_RESET 0x168428 2825#define QM_REG_SOFT_RESET 0x168428
2344/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ 2826/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
@@ -2372,44 +2854,103 @@
2372#define QM_REG_VOQINITCREDIT_4 0x168070 2854#define QM_REG_VOQINITCREDIT_4 0x168070
2373#define QM_REG_VOQINITCREDIT_5 0x168074 2855#define QM_REG_VOQINITCREDIT_5 0x168074
2374/* [RW 1] The port of which VOQ belongs */ 2856/* [RW 1] The port of which VOQ belongs */
2857#define QM_REG_VOQPORT_0 0x1682a0
2375#define QM_REG_VOQPORT_1 0x1682a4 2858#define QM_REG_VOQPORT_1 0x1682a4
2376#define QM_REG_VOQPORT_10 0x1682c8 2859#define QM_REG_VOQPORT_10 0x1682c8
2377#define QM_REG_VOQPORT_11 0x1682cc 2860#define QM_REG_VOQPORT_11 0x1682cc
2378#define QM_REG_VOQPORT_2 0x1682a8 2861#define QM_REG_VOQPORT_2 0x1682a8
2379/* [RW 32] The physical queue number associated with each VOQ */ 2862/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2380#define QM_REG_VOQQMASK_0_LSB 0x168240 2863#define QM_REG_VOQQMASK_0_LSB 0x168240
2381/* [RW 32] The physical queue number associated with each VOQ */ 2864/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2865#define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
2866/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2382#define QM_REG_VOQQMASK_0_MSB 0x168244 2867#define QM_REG_VOQQMASK_0_MSB 0x168244
2383/* [RW 32] The physical queue number associated with each VOQ */ 2868/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2869#define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
2870/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2871#define QM_REG_VOQQMASK_10_LSB 0x168290
2872/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2873#define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
2874/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2875#define QM_REG_VOQQMASK_10_MSB 0x168294
2876/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2877#define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
2878/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2879#define QM_REG_VOQQMASK_11_LSB 0x168298
2880/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2881#define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
2882/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2883#define QM_REG_VOQQMASK_11_MSB 0x16829c
2884/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2885#define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
2886/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2887#define QM_REG_VOQQMASK_1_LSB 0x168248
2888/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2889#define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
2890/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2384#define QM_REG_VOQQMASK_1_MSB 0x16824c 2891#define QM_REG_VOQQMASK_1_MSB 0x16824c
2385/* [RW 32] The physical queue number associated with each VOQ */ 2892/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2893#define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
2894/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2386#define QM_REG_VOQQMASK_2_LSB 0x168250 2895#define QM_REG_VOQQMASK_2_LSB 0x168250
2387/* [RW 32] The physical queue number associated with each VOQ */ 2896/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2897#define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
2898/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2388#define QM_REG_VOQQMASK_2_MSB 0x168254 2899#define QM_REG_VOQQMASK_2_MSB 0x168254
2389/* [RW 32] The physical queue number associated with each VOQ */ 2900/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2901#define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
2902/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2390#define QM_REG_VOQQMASK_3_LSB 0x168258 2903#define QM_REG_VOQQMASK_3_LSB 0x168258
2391/* [RW 32] The physical queue number associated with each VOQ */ 2904/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2905#define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
2906/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2907#define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
2908/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2392#define QM_REG_VOQQMASK_4_LSB 0x168260 2909#define QM_REG_VOQQMASK_4_LSB 0x168260
2393/* [RW 32] The physical queue number associated with each VOQ */ 2910/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2911#define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
2912/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2394#define QM_REG_VOQQMASK_4_MSB 0x168264 2913#define QM_REG_VOQQMASK_4_MSB 0x168264
2395/* [RW 32] The physical queue number associated with each VOQ */ 2914/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2915#define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
2916/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2396#define QM_REG_VOQQMASK_5_LSB 0x168268 2917#define QM_REG_VOQQMASK_5_LSB 0x168268
2397/* [RW 32] The physical queue number associated with each VOQ */ 2918/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2919#define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
2920/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2398#define QM_REG_VOQQMASK_5_MSB 0x16826c 2921#define QM_REG_VOQQMASK_5_MSB 0x16826c
2399/* [RW 32] The physical queue number associated with each VOQ */ 2922/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2923#define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
2924/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2400#define QM_REG_VOQQMASK_6_LSB 0x168270 2925#define QM_REG_VOQQMASK_6_LSB 0x168270
2401/* [RW 32] The physical queue number associated with each VOQ */ 2926/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2927#define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
2928/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2402#define QM_REG_VOQQMASK_6_MSB 0x168274 2929#define QM_REG_VOQQMASK_6_MSB 0x168274
2403/* [RW 32] The physical queue number associated with each VOQ */ 2930/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2931#define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
2932/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2404#define QM_REG_VOQQMASK_7_LSB 0x168278 2933#define QM_REG_VOQQMASK_7_LSB 0x168278
2405/* [RW 32] The physical queue number associated with each VOQ */ 2934/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2935#define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
2936/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2406#define QM_REG_VOQQMASK_7_MSB 0x16827c 2937#define QM_REG_VOQQMASK_7_MSB 0x16827c
2407/* [RW 32] The physical queue number associated with each VOQ */ 2938/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2939#define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
2940/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2408#define QM_REG_VOQQMASK_8_LSB 0x168280 2941#define QM_REG_VOQQMASK_8_LSB 0x168280
2409/* [RW 32] The physical queue number associated with each VOQ */ 2942/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2943#define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
2944/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2410#define QM_REG_VOQQMASK_8_MSB 0x168284 2945#define QM_REG_VOQQMASK_8_MSB 0x168284
2411/* [RW 32] The physical queue number associated with each VOQ */ 2946/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2947#define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
2948/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2412#define QM_REG_VOQQMASK_9_LSB 0x168288 2949#define QM_REG_VOQQMASK_9_LSB 0x168288
2950/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2951#define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
2952/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2953#define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
2413/* [RW 32] Wrr weights */ 2954/* [RW 32] Wrr weights */
2414#define QM_REG_WRRWEIGHTS_0 0x16880c 2955#define QM_REG_WRRWEIGHTS_0 0x16880c
2415#define QM_REG_WRRWEIGHTS_1 0x168810 2956#define QM_REG_WRRWEIGHTS_1 0x168810
@@ -2431,14 +2972,78 @@
2431#define QM_REG_WRRWEIGHTS_15 0x168828 2972#define QM_REG_WRRWEIGHTS_15 0x168828
2432#define QM_REG_WRRWEIGHTS_15_SIZE 1 2973#define QM_REG_WRRWEIGHTS_15_SIZE 1
2433/* [RW 32] Wrr weights */ 2974/* [RW 32] Wrr weights */
2975#define QM_REG_WRRWEIGHTS_16 0x16e000
2976#define QM_REG_WRRWEIGHTS_16_SIZE 1
2977/* [RW 32] Wrr weights */
2978#define QM_REG_WRRWEIGHTS_17 0x16e004
2979#define QM_REG_WRRWEIGHTS_17_SIZE 1
2980/* [RW 32] Wrr weights */
2981#define QM_REG_WRRWEIGHTS_18 0x16e008
2982#define QM_REG_WRRWEIGHTS_18_SIZE 1
2983/* [RW 32] Wrr weights */
2984#define QM_REG_WRRWEIGHTS_19 0x16e00c
2985#define QM_REG_WRRWEIGHTS_19_SIZE 1
2986/* [RW 32] Wrr weights */
2434#define QM_REG_WRRWEIGHTS_10 0x168814 2987#define QM_REG_WRRWEIGHTS_10 0x168814
2435#define QM_REG_WRRWEIGHTS_11 0x168818 2988#define QM_REG_WRRWEIGHTS_11 0x168818
2436#define QM_REG_WRRWEIGHTS_12 0x16881c 2989#define QM_REG_WRRWEIGHTS_12 0x16881c
2437#define QM_REG_WRRWEIGHTS_13 0x168820 2990#define QM_REG_WRRWEIGHTS_13 0x168820
2438#define QM_REG_WRRWEIGHTS_14 0x168824 2991#define QM_REG_WRRWEIGHTS_14 0x168824
2439#define QM_REG_WRRWEIGHTS_15 0x168828 2992#define QM_REG_WRRWEIGHTS_15 0x168828
2993#define QM_REG_WRRWEIGHTS_16 0x16e000
2994#define QM_REG_WRRWEIGHTS_17 0x16e004
2995#define QM_REG_WRRWEIGHTS_18 0x16e008
2996#define QM_REG_WRRWEIGHTS_19 0x16e00c
2440#define QM_REG_WRRWEIGHTS_2 0x16882c 2997#define QM_REG_WRRWEIGHTS_2 0x16882c
2998#define QM_REG_WRRWEIGHTS_20 0x16e010
2999#define QM_REG_WRRWEIGHTS_20_SIZE 1
3000/* [RW 32] Wrr weights */
3001#define QM_REG_WRRWEIGHTS_21 0x16e014
3002#define QM_REG_WRRWEIGHTS_21_SIZE 1
3003/* [RW 32] Wrr weights */
3004#define QM_REG_WRRWEIGHTS_22 0x16e018
3005#define QM_REG_WRRWEIGHTS_22_SIZE 1
3006/* [RW 32] Wrr weights */
3007#define QM_REG_WRRWEIGHTS_23 0x16e01c
3008#define QM_REG_WRRWEIGHTS_23_SIZE 1
3009/* [RW 32] Wrr weights */
3010#define QM_REG_WRRWEIGHTS_24 0x16e020
3011#define QM_REG_WRRWEIGHTS_24_SIZE 1
3012/* [RW 32] Wrr weights */
3013#define QM_REG_WRRWEIGHTS_25 0x16e024
3014#define QM_REG_WRRWEIGHTS_25_SIZE 1
3015/* [RW 32] Wrr weights */
3016#define QM_REG_WRRWEIGHTS_26 0x16e028
3017#define QM_REG_WRRWEIGHTS_26_SIZE 1
3018/* [RW 32] Wrr weights */
3019#define QM_REG_WRRWEIGHTS_27 0x16e02c
3020#define QM_REG_WRRWEIGHTS_27_SIZE 1
3021/* [RW 32] Wrr weights */
3022#define QM_REG_WRRWEIGHTS_28 0x16e030
3023#define QM_REG_WRRWEIGHTS_28_SIZE 1
3024/* [RW 32] Wrr weights */
3025#define QM_REG_WRRWEIGHTS_29 0x16e034
3026#define QM_REG_WRRWEIGHTS_29_SIZE 1
3027/* [RW 32] Wrr weights */
3028#define QM_REG_WRRWEIGHTS_20 0x16e010
3029#define QM_REG_WRRWEIGHTS_21 0x16e014
3030#define QM_REG_WRRWEIGHTS_22 0x16e018
3031#define QM_REG_WRRWEIGHTS_23 0x16e01c
3032#define QM_REG_WRRWEIGHTS_24 0x16e020
3033#define QM_REG_WRRWEIGHTS_25 0x16e024
3034#define QM_REG_WRRWEIGHTS_26 0x16e028
3035#define QM_REG_WRRWEIGHTS_27 0x16e02c
3036#define QM_REG_WRRWEIGHTS_28 0x16e030
3037#define QM_REG_WRRWEIGHTS_29 0x16e034
2441#define QM_REG_WRRWEIGHTS_3 0x168830 3038#define QM_REG_WRRWEIGHTS_3 0x168830
3039#define QM_REG_WRRWEIGHTS_30 0x16e038
3040#define QM_REG_WRRWEIGHTS_30_SIZE 1
3041/* [RW 32] Wrr weights */
3042#define QM_REG_WRRWEIGHTS_31 0x16e03c
3043#define QM_REG_WRRWEIGHTS_31_SIZE 1
3044/* [RW 32] Wrr weights */
3045#define QM_REG_WRRWEIGHTS_30 0x16e038
3046#define QM_REG_WRRWEIGHTS_31 0x16e03c
2442#define QM_REG_WRRWEIGHTS_4 0x168834 3047#define QM_REG_WRRWEIGHTS_4 0x168834
2443#define QM_REG_WRRWEIGHTS_5 0x168838 3048#define QM_REG_WRRWEIGHTS_5 0x168838
2444#define QM_REG_WRRWEIGHTS_6 0x16883c 3049#define QM_REG_WRRWEIGHTS_6 0x16883c
@@ -2447,6 +3052,70 @@
2447#define QM_REG_WRRWEIGHTS_9 0x168848 3052#define QM_REG_WRRWEIGHTS_9 0x168848
2448/* [R 6] Keep the fill level of the fifo from write client 1 */ 3053/* [R 6] Keep the fill level of the fifo from write client 1 */
2449#define QM_REG_XQM_WRC_FIFOLVL 0x168000 3054#define QM_REG_XQM_WRC_FIFOLVL 0x168000
3055#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3056#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3057#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3058#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3059#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3060#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3061#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3062#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3063#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3064#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3065#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3066#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3067#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3068#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3069#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3070#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3071#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3072#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3073#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3074#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3075#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3076#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3077#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3078#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3079#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3080#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3081#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3082#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3083#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3084#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3085#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3086#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3087#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3088#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3089#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3090#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3091#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3092#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3093#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3094#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3095#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3096#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3097#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3098#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3099#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3100#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3101#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3102#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3103#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3104#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3105#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3106#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3107#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3108#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3109#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3110#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3111#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3112#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3113#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3114#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3115#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3116#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3117#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3118#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2450#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3119#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2451#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3120#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2452#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3121#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
@@ -2455,6 +3124,22 @@
2455#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3124#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2456#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3125#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2457#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3126#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3127#define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3128#define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3129#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3130#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3131#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3132#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3133#define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3134#define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3135#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3136#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3137#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3138#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3139#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3140#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3141#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3142#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2458#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3143#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
2459#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3144#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
2460#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3145#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
@@ -2463,6 +3148,70 @@
2463#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3148#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
2464#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3149#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
2465#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3150#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3151#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3152#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3153#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3154#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3155#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3156#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3157#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3158#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3159#define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3160#define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3161#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3162#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3163#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3164#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3165#define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3166#define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3167#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3168#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3169#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3170#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3171#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3172#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3173#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3174#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3175#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3176#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3177#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3178#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3179#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3180#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3181#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3182#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3183#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3184#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3185#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3186#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3187#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3188#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3189#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3190#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3191#define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3192#define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3193#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3194#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3195#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3196#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3197#define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3198#define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3199#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3200#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3201#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3202#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3203#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3204#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3205#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3206#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3207#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3208#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3209#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3210#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3211#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3212#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3213#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3214#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2466#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3215#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2467#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3216#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2468#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3217#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
@@ -2471,6 +3220,78 @@
2471#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3220#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2472#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3221#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2473#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3222#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3223#define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3224#define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3225#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3226#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3227#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3228#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3229#define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3230#define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3231#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3232#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3233#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3234#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3235#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3236#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3237#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3238#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3239#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3240#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3241#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3242#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3243#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3244#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3245#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3246#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3247#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3248#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3249#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3250#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3251#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3252#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3253#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3254#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3255#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3256#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3257#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3258#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3259#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3260#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3261#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3262#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3263#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3264#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3265#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3266#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3267#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3268#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3269#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3270#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3271#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3272#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3273#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3274#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3275#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3276#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3277#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3278#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3279#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3280#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3281#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3282#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3283#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3284#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3285#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3286#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3287#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3288#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3289#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3290#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3291#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3292#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3293#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3294#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
2474#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4) 3295#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
2475#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4 3296#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
2476/* [R 1] debug only: This bit indicates wheter indicates that external 3297/* [R 1] debug only: This bit indicates wheter indicates that external
@@ -2483,6 +3304,14 @@
2483 ~dbg_registers_debug_target=0 (internal buffer) */ 3304 ~dbg_registers_debug_target=0 (internal buffer) */
2484#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128 3305#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
2485#define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1 3306#define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
3307#define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8)
3308#define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8
3309#define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8)
3310#define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8
3311#define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8)
3312#define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8
3313#define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8)
3314#define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8
2486/* [RW 32] Wrr weights */ 3315/* [RW 32] Wrr weights */
2487#define QM_REG_WRRWEIGHTS_0 0x16880c 3316#define QM_REG_WRRWEIGHTS_0 0x16880c
2488#define QM_REG_WRRWEIGHTS_0_SIZE 1 3317#define QM_REG_WRRWEIGHTS_0_SIZE 1
@@ -2531,20 +3360,67 @@
2531/* [RW 32] Wrr weights */ 3360/* [RW 32] Wrr weights */
2532#define QM_REG_WRRWEIGHTS_9 0x168848 3361#define QM_REG_WRRWEIGHTS_9 0x168848
2533#define QM_REG_WRRWEIGHTS_9_SIZE 1 3362#define QM_REG_WRRWEIGHTS_9_SIZE 1
2534/* [RW 22] Number of free element in the free list of T2 entries - port 0. */ 3363/* [RW 32] Wrr weights */
3364#define QM_REG_WRRWEIGHTS_16 0x16e000
3365#define QM_REG_WRRWEIGHTS_16_SIZE 1
3366/* [RW 32] Wrr weights */
3367#define QM_REG_WRRWEIGHTS_17 0x16e004
3368#define QM_REG_WRRWEIGHTS_17_SIZE 1
3369/* [RW 32] Wrr weights */
3370#define QM_REG_WRRWEIGHTS_18 0x16e008
3371#define QM_REG_WRRWEIGHTS_18_SIZE 1
3372/* [RW 32] Wrr weights */
3373#define QM_REG_WRRWEIGHTS_19 0x16e00c
3374#define QM_REG_WRRWEIGHTS_19_SIZE 1
3375/* [RW 32] Wrr weights */
3376#define QM_REG_WRRWEIGHTS_20 0x16e010
3377#define QM_REG_WRRWEIGHTS_20_SIZE 1
3378/* [RW 32] Wrr weights */
3379#define QM_REG_WRRWEIGHTS_21 0x16e014
3380#define QM_REG_WRRWEIGHTS_21_SIZE 1
3381/* [RW 32] Wrr weights */
3382#define QM_REG_WRRWEIGHTS_22 0x16e018
3383#define QM_REG_WRRWEIGHTS_22_SIZE 1
3384/* [RW 32] Wrr weights */
3385#define QM_REG_WRRWEIGHTS_23 0x16e01c
3386#define QM_REG_WRRWEIGHTS_23_SIZE 1
3387/* [RW 32] Wrr weights */
3388#define QM_REG_WRRWEIGHTS_24 0x16e020
3389#define QM_REG_WRRWEIGHTS_24_SIZE 1
3390/* [RW 32] Wrr weights */
3391#define QM_REG_WRRWEIGHTS_25 0x16e024
3392#define QM_REG_WRRWEIGHTS_25_SIZE 1
3393/* [RW 32] Wrr weights */
3394#define QM_REG_WRRWEIGHTS_26 0x16e028
3395#define QM_REG_WRRWEIGHTS_26_SIZE 1
3396/* [RW 32] Wrr weights */
3397#define QM_REG_WRRWEIGHTS_27 0x16e02c
3398#define QM_REG_WRRWEIGHTS_27_SIZE 1
3399/* [RW 32] Wrr weights */
3400#define QM_REG_WRRWEIGHTS_28 0x16e030
3401#define QM_REG_WRRWEIGHTS_28_SIZE 1
3402/* [RW 32] Wrr weights */
3403#define QM_REG_WRRWEIGHTS_29 0x16e034
3404#define QM_REG_WRRWEIGHTS_29_SIZE 1
3405/* [RW 32] Wrr weights */
3406#define QM_REG_WRRWEIGHTS_30 0x16e038
3407#define QM_REG_WRRWEIGHTS_30_SIZE 1
3408/* [RW 32] Wrr weights */
3409#define QM_REG_WRRWEIGHTS_31 0x16e03c
3410#define QM_REG_WRRWEIGHTS_31_SIZE 1
2535#define SRC_REG_COUNTFREE0 0x40500 3411#define SRC_REG_COUNTFREE0 0x40500
2536/* [WB 64] First free element in the free list of T2 entries - port 0. */ 3412/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3413 ports. If set the searcher support 8 functions. */
3414#define SRC_REG_E1HMF_ENABLE 0x404cc
2537#define SRC_REG_FIRSTFREE0 0x40510 3415#define SRC_REG_FIRSTFREE0 0x40510
2538#define SRC_REG_KEYRSS0_0 0x40408 3416#define SRC_REG_KEYRSS0_0 0x40408
3417#define SRC_REG_KEYRSS0_7 0x40424
2539#define SRC_REG_KEYRSS1_9 0x40454 3418#define SRC_REG_KEYRSS1_9 0x40454
2540/* [WB 64] Last free element in the free list of T2 entries - port 0. */
2541#define SRC_REG_LASTFREE0 0x40530 3419#define SRC_REG_LASTFREE0 0x40530
2542/* [RW 5] The number of hash bits used for the search (h); Values can be 8
2543 to 24. */
2544#define SRC_REG_NUMBER_HASH_BITS0 0x40400 3420#define SRC_REG_NUMBER_HASH_BITS0 0x40400
2545/* [RW 1] Reset internal state machines. */ 3421/* [RW 1] Reset internal state machines. */
2546#define SRC_REG_SOFT_RST 0x4049c 3422#define SRC_REG_SOFT_RST 0x4049c
2547/* [R 1] Interrupt register #0 read */ 3423/* [R 3] Interrupt register #0 read */
2548#define SRC_REG_SRC_INT_STS 0x404ac 3424#define SRC_REG_SRC_INT_STS 0x404ac
2549/* [RW 3] Parity mask register #0 read/write */ 3425/* [RW 3] Parity mask register #0 read/write */
2550#define SRC_REG_SRC_PRTY_MASK 0x404c8 3426#define SRC_REG_SRC_PRTY_MASK 0x404c8
@@ -2637,11 +3513,14 @@
2637 weight 8 (the most prioritised); 1 stands for weight 1(least 3513 weight 8 (the most prioritised); 1 stands for weight 1(least
2638 prioritised); 2 stands for weight 2; tc. */ 3514 prioritised); 2 stands for weight 2; tc. */
2639#define TCM_REG_PBF_WEIGHT 0x500b4 3515#define TCM_REG_PBF_WEIGHT 0x500b4
2640/* [RW 6] The physical queue number 0 per port index. */
2641#define TCM_REG_PHYS_QNUM0_0 0x500e0 3516#define TCM_REG_PHYS_QNUM0_0 0x500e0
2642#define TCM_REG_PHYS_QNUM0_1 0x500e4 3517#define TCM_REG_PHYS_QNUM0_1 0x500e4
2643/* [RW 6] The physical queue number 1 per port index. */
2644#define TCM_REG_PHYS_QNUM1_0 0x500e8 3518#define TCM_REG_PHYS_QNUM1_0 0x500e8
3519#define TCM_REG_PHYS_QNUM1_1 0x500ec
3520#define TCM_REG_PHYS_QNUM2_0 0x500f0
3521#define TCM_REG_PHYS_QNUM2_1 0x500f4
3522#define TCM_REG_PHYS_QNUM3_0 0x500f8
3523#define TCM_REG_PHYS_QNUM3_1 0x500fc
2645/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded; 3524/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
2646 acknowledge output is deasserted; all other signals are treated as usual; 3525 acknowledge output is deasserted; all other signals are treated as usual;
2647 if 1 - normal activity. */ 3526 if 1 - normal activity. */
@@ -2670,6 +3549,8 @@
2670#define TCM_REG_TCM_INT_MASK 0x501dc 3549#define TCM_REG_TCM_INT_MASK 0x501dc
2671/* [R 11] Interrupt register #0 read */ 3550/* [R 11] Interrupt register #0 read */
2672#define TCM_REG_TCM_INT_STS 0x501d0 3551#define TCM_REG_TCM_INT_STS 0x501d0
3552/* [R 27] Parity register #0 read */
3553#define TCM_REG_TCM_PRTY_STS 0x501e0
2673/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 3554/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
2674 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 3555 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
2675 Is used to determine the number of the AG context REG-pairs written back; 3556 Is used to determine the number of the AG context REG-pairs written back;
@@ -2729,6 +3610,7 @@
2729 mechanism. The fields are: [5:0] - length of the message; 15:6] - message 3610 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
2730 pointer; 20:16] - next pointer. */ 3611 pointer; 20:16] - next pointer. */
2731#define TCM_REG_XX_DESCR_TABLE 0x50280 3612#define TCM_REG_XX_DESCR_TABLE 0x50280
3613#define TCM_REG_XX_DESCR_TABLE_SIZE 32
2732/* [R 6] Use to read the value of XX protection Free counter. */ 3614/* [R 6] Use to read the value of XX protection Free counter. */
2733#define TCM_REG_XX_FREE 0x50178 3615#define TCM_REG_XX_FREE 0x50178
2734/* [RW 6] Initial value for the credit counter; responsible for fulfilling 3616/* [RW 6] Initial value for the credit counter; responsible for fulfilling
@@ -2780,7 +3662,7 @@
2780/* [RW 4] Load value for expiration credit cnt. CFC max number of 3662/* [RW 4] Load value for expiration credit cnt. CFC max number of
2781 outstanding load requests for timers (expiration) context loading. */ 3663 outstanding load requests for timers (expiration) context loading. */
2782#define TM_REG_EXP_CRDCNT_VAL 0x164238 3664#define TM_REG_EXP_CRDCNT_VAL 0x164238
2783/* [RW 18] Linear0 Max active cid. */ 3665/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
2784#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 3666#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
2785/* [WB 64] Linear0 phy address. */ 3667/* [WB 64] Linear0 phy address. */
2786#define TM_REG_LIN0_PHY_ADDR 0x164270 3668#define TM_REG_LIN0_PHY_ADDR 0x164270
@@ -2804,6 +3686,21 @@
2804#define TM_REG_TM_INT_STS 0x1640f0 3686#define TM_REG_TM_INT_STS 0x1640f0
2805/* [RW 8] The event id for aggregated interrupt 0 */ 3687/* [RW 8] The event id for aggregated interrupt 0 */
2806#define TSDM_REG_AGG_INT_EVENT_0 0x42038 3688#define TSDM_REG_AGG_INT_EVENT_0 0x42038
3689#define TSDM_REG_AGG_INT_EVENT_2 0x42040
3690#define TSDM_REG_AGG_INT_EVENT_20 0x42088
3691#define TSDM_REG_AGG_INT_EVENT_21 0x4208c
3692#define TSDM_REG_AGG_INT_EVENT_22 0x42090
3693#define TSDM_REG_AGG_INT_EVENT_23 0x42094
3694#define TSDM_REG_AGG_INT_EVENT_24 0x42098
3695#define TSDM_REG_AGG_INT_EVENT_25 0x4209c
3696#define TSDM_REG_AGG_INT_EVENT_26 0x420a0
3697#define TSDM_REG_AGG_INT_EVENT_27 0x420a4
3698#define TSDM_REG_AGG_INT_EVENT_28 0x420a8
3699#define TSDM_REG_AGG_INT_EVENT_29 0x420ac
3700#define TSDM_REG_AGG_INT_EVENT_3 0x42044
3701#define TSDM_REG_AGG_INT_EVENT_30 0x420b0
3702#define TSDM_REG_AGG_INT_EVENT_31 0x420b4
3703#define TSDM_REG_AGG_INT_EVENT_4 0x42048
2807/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 3704/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
2808#define TSDM_REG_CFC_RSP_START_ADDR 0x42008 3705#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
2809/* [RW 16] The maximum value of the competion counter #0 */ 3706/* [RW 16] The maximum value of the competion counter #0 */
@@ -2868,6 +3765,9 @@
2868/* [RW 32] Interrupt mask register #0 read/write */ 3765/* [RW 32] Interrupt mask register #0 read/write */
2869#define TSDM_REG_TSDM_INT_MASK_0 0x4229c 3766#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
2870#define TSDM_REG_TSDM_INT_MASK_1 0x422ac 3767#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
3768/* [R 32] Interrupt register #0 read */
3769#define TSDM_REG_TSDM_INT_STS_0 0x42290
3770#define TSDM_REG_TSDM_INT_STS_1 0x422a0
2871/* [RW 11] Parity mask register #0 read/write */ 3771/* [RW 11] Parity mask register #0 read/write */
2872#define TSDM_REG_TSDM_PRTY_MASK 0x422bc 3772#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
2873/* [R 11] Parity register #0 read */ 3773/* [R 11] Parity register #0 read */
@@ -2908,9 +3808,8 @@
2908#define TSEM_REG_ENABLE_OUT 0x1800a8 3808#define TSEM_REG_ENABLE_OUT 0x1800a8
2909/* [RW 32] This address space contains all registers and memories that are 3809/* [RW 32] This address space contains all registers and memories that are
2910 placed in SEM_FAST block. The SEM_FAST registers are described in 3810 placed in SEM_FAST block. The SEM_FAST registers are described in
2911 appendix B. In order to access the SEM_FAST registers the base address 3811 appendix B. In order to access the sem_fast registers the base address
2912 TSEM_REGISTERS_FAST_MEMORY (Offset: 0x1a0000) should be added to each 3812 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
2913 SEM_FAST register offset. */
2914#define TSEM_REG_FAST_MEMORY 0x1a0000 3813#define TSEM_REG_FAST_MEMORY 0x1a0000
2915/* [RW 1] Disables input messages from FIC0 May be updated during run_time 3814/* [RW 1] Disables input messages from FIC0 May be updated during run_time
2916 by the microcode */ 3815 by the microcode */
@@ -2993,6 +3892,9 @@
2993/* [RW 32] Interrupt mask register #0 read/write */ 3892/* [RW 32] Interrupt mask register #0 read/write */
2994#define TSEM_REG_TSEM_INT_MASK_0 0x180100 3893#define TSEM_REG_TSEM_INT_MASK_0 0x180100
2995#define TSEM_REG_TSEM_INT_MASK_1 0x180110 3894#define TSEM_REG_TSEM_INT_MASK_1 0x180110
3895/* [R 32] Interrupt register #0 read */
3896#define TSEM_REG_TSEM_INT_STS_0 0x1800f4
3897#define TSEM_REG_TSEM_INT_STS_1 0x180104
2996/* [RW 32] Parity mask register #0 read/write */ 3898/* [RW 32] Parity mask register #0 read/write */
2997#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 3899#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
2998#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 3900#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
@@ -3088,12 +3990,15 @@
3088#define UCM_REG_N_SM_CTX_LD_2 0xe005c 3990#define UCM_REG_N_SM_CTX_LD_2 0xe005c
3089#define UCM_REG_N_SM_CTX_LD_3 0xe0060 3991#define UCM_REG_N_SM_CTX_LD_3 0xe0060
3090#define UCM_REG_N_SM_CTX_LD_4 0xe0064 3992#define UCM_REG_N_SM_CTX_LD_4 0xe0064
3091/* [RW 6] The physical queue number 0 per port index (CID[23]) */ 3993#define UCM_REG_N_SM_CTX_LD_5 0xe0068
3092#define UCM_REG_PHYS_QNUM0_0 0xe0110 3994#define UCM_REG_PHYS_QNUM0_0 0xe0110
3093#define UCM_REG_PHYS_QNUM0_1 0xe0114 3995#define UCM_REG_PHYS_QNUM0_1 0xe0114
3094/* [RW 6] The physical queue number 1 per port index (CID[23]) */
3095#define UCM_REG_PHYS_QNUM1_0 0xe0118 3996#define UCM_REG_PHYS_QNUM1_0 0xe0118
3096#define UCM_REG_PHYS_QNUM1_1 0xe011c 3997#define UCM_REG_PHYS_QNUM1_1 0xe011c
3998#define UCM_REG_PHYS_QNUM2_0 0xe0120
3999#define UCM_REG_PHYS_QNUM2_1 0xe0124
4000#define UCM_REG_PHYS_QNUM3_0 0xe0128
4001#define UCM_REG_PHYS_QNUM3_1 0xe012c
3097/* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4002/* [RW 8] The Event ID for Timers formatting in case of stop done. */
3098#define UCM_REG_STOP_EVNT_ID 0xe00ac 4003#define UCM_REG_STOP_EVNT_ID 0xe00ac
3099/* [RC 1] Set when the message length mismatch (relative to last indication) 4004/* [RC 1] Set when the message length mismatch (relative to last indication)
@@ -3132,6 +4037,8 @@
3132#define UCM_REG_UCM_INT_MASK 0xe01d4 4037#define UCM_REG_UCM_INT_MASK 0xe01d4
3133/* [R 11] Interrupt register #0 read */ 4038/* [R 11] Interrupt register #0 read */
3134#define UCM_REG_UCM_INT_STS 0xe01c8 4039#define UCM_REG_UCM_INT_STS 0xe01c8
4040/* [R 27] Parity register #0 read */
4041#define UCM_REG_UCM_PRTY_STS 0xe01d8
3135/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS 4042/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
3136 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4043 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3137 Is used to determine the number of the AG context REG-pairs written back; 4044 Is used to determine the number of the AG context REG-pairs written back;
@@ -3189,6 +4096,7 @@
3189 mechanism. The fields are:[5:0] - message length; 14:6] - message 4096 mechanism. The fields are:[5:0] - message length; 14:6] - message
3190 pointer; 19:15] - next pointer. */ 4097 pointer; 19:15] - next pointer. */
3191#define UCM_REG_XX_DESCR_TABLE 0xe0280 4098#define UCM_REG_XX_DESCR_TABLE 0xe0280
4099#define UCM_REG_XX_DESCR_TABLE_SIZE 32
3192/* [R 6] Use to read the XX protection Free counter. */ 4100/* [R 6] Use to read the XX protection Free counter. */
3193#define UCM_REG_XX_FREE 0xe016c 4101#define UCM_REG_XX_FREE 0xe016c
3194/* [RW 6] Initial value for the credit counter; responsible for fulfilling 4102/* [RW 6] Initial value for the credit counter; responsible for fulfilling
@@ -3218,6 +4126,21 @@
3218#define USDM_REG_AGG_INT_EVENT_17 0xc407c 4126#define USDM_REG_AGG_INT_EVENT_17 0xc407c
3219#define USDM_REG_AGG_INT_EVENT_18 0xc4080 4127#define USDM_REG_AGG_INT_EVENT_18 0xc4080
3220#define USDM_REG_AGG_INT_EVENT_19 0xc4084 4128#define USDM_REG_AGG_INT_EVENT_19 0xc4084
4129#define USDM_REG_AGG_INT_EVENT_2 0xc4040
4130#define USDM_REG_AGG_INT_EVENT_20 0xc4088
4131#define USDM_REG_AGG_INT_EVENT_21 0xc408c
4132#define USDM_REG_AGG_INT_EVENT_22 0xc4090
4133#define USDM_REG_AGG_INT_EVENT_23 0xc4094
4134#define USDM_REG_AGG_INT_EVENT_24 0xc4098
4135#define USDM_REG_AGG_INT_EVENT_25 0xc409c
4136#define USDM_REG_AGG_INT_EVENT_26 0xc40a0
4137#define USDM_REG_AGG_INT_EVENT_27 0xc40a4
4138#define USDM_REG_AGG_INT_EVENT_28 0xc40a8
4139#define USDM_REG_AGG_INT_EVENT_29 0xc40ac
4140#define USDM_REG_AGG_INT_EVENT_3 0xc4044
4141#define USDM_REG_AGG_INT_EVENT_30 0xc40b0
4142#define USDM_REG_AGG_INT_EVENT_31 0xc40b4
4143#define USDM_REG_AGG_INT_EVENT_4 0xc4048
3221/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 4144/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3222 or auto-mask-mode (1) */ 4145 or auto-mask-mode (1) */
3223#define USDM_REG_AGG_INT_MODE_0 0xc41b8 4146#define USDM_REG_AGG_INT_MODE_0 0xc41b8
@@ -3298,6 +4221,9 @@
3298/* [RW 32] Interrupt mask register #0 read/write */ 4221/* [RW 32] Interrupt mask register #0 read/write */
3299#define USDM_REG_USDM_INT_MASK_0 0xc42a0 4222#define USDM_REG_USDM_INT_MASK_0 0xc42a0
3300#define USDM_REG_USDM_INT_MASK_1 0xc42b0 4223#define USDM_REG_USDM_INT_MASK_1 0xc42b0
4224/* [R 32] Interrupt register #0 read */
4225#define USDM_REG_USDM_INT_STS_0 0xc4294
4226#define USDM_REG_USDM_INT_STS_1 0xc42a4
3301/* [RW 11] Parity mask register #0 read/write */ 4227/* [RW 11] Parity mask register #0 read/write */
3302#define USDM_REG_USDM_PRTY_MASK 0xc42c0 4228#define USDM_REG_USDM_PRTY_MASK 0xc42c0
3303/* [R 11] Parity register #0 read */ 4229/* [R 11] Parity register #0 read */
@@ -3338,9 +4264,8 @@
3338#define USEM_REG_ENABLE_OUT 0x3000a8 4264#define USEM_REG_ENABLE_OUT 0x3000a8
3339/* [RW 32] This address space contains all registers and memories that are 4265/* [RW 32] This address space contains all registers and memories that are
3340 placed in SEM_FAST block. The SEM_FAST registers are described in 4266 placed in SEM_FAST block. The SEM_FAST registers are described in
3341 appendix B. In order to access the SEM_FAST registers... the base address 4267 appendix B. In order to access the sem_fast registers the base address
3342 USEM_REGISTERS_FAST_MEMORY (Offset: 0x320000) should be added to each 4268 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
3343 SEM_FAST register offset. */
3344#define USEM_REG_FAST_MEMORY 0x320000 4269#define USEM_REG_FAST_MEMORY 0x320000
3345/* [RW 1] Disables input messages from FIC0 May be updated during run_time 4270/* [RW 1] Disables input messages from FIC0 May be updated during run_time
3346 by the microcode */ 4271 by the microcode */
@@ -3423,6 +4348,9 @@
3423/* [RW 32] Interrupt mask register #0 read/write */ 4348/* [RW 32] Interrupt mask register #0 read/write */
3424#define USEM_REG_USEM_INT_MASK_0 0x300110 4349#define USEM_REG_USEM_INT_MASK_0 0x300110
3425#define USEM_REG_USEM_INT_MASK_1 0x300120 4350#define USEM_REG_USEM_INT_MASK_1 0x300120
4351/* [R 32] Interrupt register #0 read */
4352#define USEM_REG_USEM_INT_STS_0 0x300104
4353#define USEM_REG_USEM_INT_STS_1 0x300114
3426/* [RW 32] Parity mask register #0 read/write */ 4354/* [RW 32] Parity mask register #0 read/write */
3427#define USEM_REG_USEM_PRTY_MASK_0 0x300130 4355#define USEM_REG_USEM_PRTY_MASK_0 0x300130
3428#define USEM_REG_USEM_PRTY_MASK_1 0x300140 4356#define USEM_REG_USEM_PRTY_MASK_1 0x300140
@@ -3491,11 +4419,8 @@
3491 writes the initial credit value; read returns the current value of the 4419 writes the initial credit value; read returns the current value of the
3492 credit counter. Must be initialized to 64 at start-up. */ 4420 credit counter. Must be initialized to 64 at start-up. */
3493#define XCM_REG_FIC1_INIT_CRD 0x20410 4421#define XCM_REG_FIC1_INIT_CRD 0x20410
3494/* [RW 8] The maximum delayed ACK counter value.Must be at least 2. Per port
3495 value. */
3496#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118 4422#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
3497#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c 4423#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
3498/* [RW 28] The delayed ACK timeout in ticks. Per port value. */
3499#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108 4424#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
3500#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c 4425#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
3501/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 4426/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
@@ -3545,6 +4470,7 @@
3545#define XCM_REG_N_SM_CTX_LD_2 0x20068 4470#define XCM_REG_N_SM_CTX_LD_2 0x20068
3546#define XCM_REG_N_SM_CTX_LD_3 0x2006c 4471#define XCM_REG_N_SM_CTX_LD_3 0x2006c
3547#define XCM_REG_N_SM_CTX_LD_4 0x20070 4472#define XCM_REG_N_SM_CTX_LD_4 0x20070
4473#define XCM_REG_N_SM_CTX_LD_5 0x20074
3548/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 4474/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3549 acknowledge output is deasserted; all other signals are treated as usual; 4475 acknowledge output is deasserted; all other signals are treated as usual;
3550 if 1 - normal activity. */ 4476 if 1 - normal activity. */
@@ -3556,6 +4482,8 @@
3556 weight 8 (the most prioritised); 1 stands for weight 1(least 4482 weight 8 (the most prioritised); 1 stands for weight 1(least
3557 prioritised); 2 stands for weight 2; tc. */ 4483 prioritised); 2 stands for weight 2; tc. */
3558#define XCM_REG_PBF_WEIGHT 0x200d0 4484#define XCM_REG_PBF_WEIGHT 0x200d0
4485#define XCM_REG_PHYS_QNUM3_0 0x20100
4486#define XCM_REG_PHYS_QNUM3_1 0x20104
3559/* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4487/* [RW 8] The Event ID for Timers formatting in case of stop done. */
3560#define XCM_REG_STOP_EVNT_ID 0x200b8 4488#define XCM_REG_STOP_EVNT_ID 0x200b8
3561/* [RC 1] Set at message length mismatch (relative to last indication) at 4489/* [RC 1] Set at message length mismatch (relative to last indication) at
@@ -3603,53 +4531,17 @@
3603 weight 8 (the most prioritised); 1 stands for weight 1(least 4531 weight 8 (the most prioritised); 1 stands for weight 1(least
3604 prioritised); 2 stands for weight 2; tc. */ 4532 prioritised); 2 stands for weight 2; tc. */
3605#define XCM_REG_USEM_WEIGHT 0x200c8 4533#define XCM_REG_USEM_WEIGHT 0x200c8
3606/* [RW 2] DA counter command; used in case of window update doorbell.The
3607 first index stands for the value DaEnable of that connection. The second
3608 index stands for port number. */
3609#define XCM_REG_WU_DA_CNT_CMD00 0x201d4 4534#define XCM_REG_WU_DA_CNT_CMD00 0x201d4
3610/* [RW 2] DA counter command; used in case of window update doorbell.The
3611 first index stands for the value DaEnable of that connection. The second
3612 index stands for port number. */
3613#define XCM_REG_WU_DA_CNT_CMD01 0x201d8 4535#define XCM_REG_WU_DA_CNT_CMD01 0x201d8
3614/* [RW 2] DA counter command; used in case of window update doorbell.The
3615 first index stands for the value DaEnable of that connection. The second
3616 index stands for port number. */
3617#define XCM_REG_WU_DA_CNT_CMD10 0x201dc 4536#define XCM_REG_WU_DA_CNT_CMD10 0x201dc
3618/* [RW 2] DA counter command; used in case of window update doorbell.The
3619 first index stands for the value DaEnable of that connection. The second
3620 index stands for port number. */
3621#define XCM_REG_WU_DA_CNT_CMD11 0x201e0 4537#define XCM_REG_WU_DA_CNT_CMD11 0x201e0
3622/* [RW 8] DA counter update value used in case of window update doorbell.The
3623 first index stands for the value DaEnable of that connection. The second
3624 index stands for port number. */
3625#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4 4538#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
3626/* [RW 8] DA counter update value; used in case of window update
3627 doorbell.The first index stands for the value DaEnable of that
3628 connection. The second index stands for port number. */
3629#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8 4539#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
3630/* [RW 8] DA counter update value; used in case of window update
3631 doorbell.The first index stands for the value DaEnable of that
3632 connection. The second index stands for port number. */
3633#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec 4540#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
3634/* [RW 8] DA counter update value; used in case of window update
3635 doorbell.The first index stands for the value DaEnable of that
3636 connection. The second index stands for port number. */
3637#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0 4541#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
3638/* [RW 1] DA timer command; used in case of window update doorbell.The first
3639 index stands for the value DaEnable of that connection. The second index
3640 stands for port number. */
3641#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4 4542#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
3642/* [RW 1] DA timer command; used in case of window update doorbell.The first
3643 index stands for the value DaEnable of that connection. The second index
3644 stands for port number. */
3645#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8 4543#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
3646/* [RW 1] DA timer command; used in case of window update doorbell.The first
3647 index stands for the value DaEnable of that connection. The second index
3648 stands for port number. */
3649#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc 4544#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
3650/* [RW 1] DA timer command; used in case of window update doorbell.The first
3651 index stands for the value DaEnable of that connection. The second index
3652 stands for port number. */
3653#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0 4545#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
3654/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4546/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3655 acknowledge output is deasserted; all other signals are treated as usual; 4547 acknowledge output is deasserted; all other signals are treated as usual;
@@ -3659,6 +4551,8 @@
3659#define XCM_REG_XCM_INT_MASK 0x202b4 4551#define XCM_REG_XCM_INT_MASK 0x202b4
3660/* [R 14] Interrupt register #0 read */ 4552/* [R 14] Interrupt register #0 read */
3661#define XCM_REG_XCM_INT_STS 0x202a8 4553#define XCM_REG_XCM_INT_STS 0x202a8
4554/* [R 30] Parity register #0 read */
4555#define XCM_REG_XCM_PRTY_STS 0x202b8
3662/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS 4556/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
3663 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4557 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3664 Is used to determine the number of the AG context REG-pairs written back; 4558 Is used to determine the number of the AG context REG-pairs written back;
@@ -3715,6 +4609,7 @@
3715 mechanism. The fields are: [5:0] - message length; 11:6] - message 4609 mechanism. The fields are: [5:0] - message length; 11:6] - message
3716 pointer; 16:12] - next pointer. */ 4610 pointer; 16:12] - next pointer. */
3717#define XCM_REG_XX_DESCR_TABLE 0x20480 4611#define XCM_REG_XX_DESCR_TABLE 0x20480
4612#define XCM_REG_XX_DESCR_TABLE_SIZE 32
3718/* [R 6] Used to read the XX protection Free counter. */ 4613/* [R 6] Used to read the XX protection Free counter. */
3719#define XCM_REG_XX_FREE 0x20240 4614#define XCM_REG_XX_FREE 0x20240
3720/* [RW 6] Initial value for the credit counter; responsible for fulfilling 4615/* [RW 6] Initial value for the credit counter; responsible for fulfilling
@@ -3728,7 +4623,7 @@
3728#define XCM_REG_XX_MSG_NUM 0x20428 4623#define XCM_REG_XX_MSG_NUM 0x20428
3729/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4624/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3730#define XCM_REG_XX_OVFL_EVNT_ID 0x20058 4625#define XCM_REG_XX_OVFL_EVNT_ID 0x20058
3731/* [RW 15] Indirect access to the XX table of the XX protection mechanism. 4626/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3732 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - 4627 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
3733 header pointer. */ 4628 header pointer. */
3734#define XCM_REG_XX_TABLE 0x20500 4629#define XCM_REG_XX_TABLE 0x20500
@@ -3745,6 +4640,9 @@
3745#define XSDM_REG_AGG_INT_EVENT_17 0x16607c 4640#define XSDM_REG_AGG_INT_EVENT_17 0x16607c
3746#define XSDM_REG_AGG_INT_EVENT_18 0x166080 4641#define XSDM_REG_AGG_INT_EVENT_18 0x166080
3747#define XSDM_REG_AGG_INT_EVENT_19 0x166084 4642#define XSDM_REG_AGG_INT_EVENT_19 0x166084
4643#define XSDM_REG_AGG_INT_EVENT_10 0x166060
4644#define XSDM_REG_AGG_INT_EVENT_11 0x166064
4645#define XSDM_REG_AGG_INT_EVENT_12 0x166068
3748#define XSDM_REG_AGG_INT_EVENT_2 0x166040 4646#define XSDM_REG_AGG_INT_EVENT_2 0x166040
3749#define XSDM_REG_AGG_INT_EVENT_20 0x166088 4647#define XSDM_REG_AGG_INT_EVENT_20 0x166088
3750#define XSDM_REG_AGG_INT_EVENT_21 0x16608c 4648#define XSDM_REG_AGG_INT_EVENT_21 0x16608c
@@ -3756,6 +4654,15 @@
3756#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4 4654#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
3757#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8 4655#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
3758#define XSDM_REG_AGG_INT_EVENT_29 0x1660ac 4656#define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
4657#define XSDM_REG_AGG_INT_EVENT_3 0x166044
4658#define XSDM_REG_AGG_INT_EVENT_30 0x1660b0
4659#define XSDM_REG_AGG_INT_EVENT_31 0x1660b4
4660#define XSDM_REG_AGG_INT_EVENT_4 0x166048
4661#define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4662#define XSDM_REG_AGG_INT_EVENT_6 0x166050
4663#define XSDM_REG_AGG_INT_EVENT_7 0x166054
4664#define XSDM_REG_AGG_INT_EVENT_8 0x166058
4665#define XSDM_REG_AGG_INT_EVENT_9 0x16605c
3759/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 4666/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3760 or auto-mask-mode (1) */ 4667 or auto-mask-mode (1) */
3761#define XSDM_REG_AGG_INT_MODE_0 0x1661b8 4668#define XSDM_REG_AGG_INT_MODE_0 0x1661b8
@@ -3832,6 +4739,9 @@
3832/* [RW 32] Interrupt mask register #0 read/write */ 4739/* [RW 32] Interrupt mask register #0 read/write */
3833#define XSDM_REG_XSDM_INT_MASK_0 0x16629c 4740#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
3834#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac 4741#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
4742/* [R 32] Interrupt register #0 read */
4743#define XSDM_REG_XSDM_INT_STS_0 0x166290
4744#define XSDM_REG_XSDM_INT_STS_1 0x1662a0
3835/* [RW 11] Parity mask register #0 read/write */ 4745/* [RW 11] Parity mask register #0 read/write */
3836#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc 4746#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
3837/* [R 11] Parity register #0 read */ 4747/* [R 11] Parity register #0 read */
@@ -3872,9 +4782,8 @@
3872#define XSEM_REG_ENABLE_OUT 0x2800a8 4782#define XSEM_REG_ENABLE_OUT 0x2800a8
3873/* [RW 32] This address space contains all registers and memories that are 4783/* [RW 32] This address space contains all registers and memories that are
3874 placed in SEM_FAST block. The SEM_FAST registers are described in 4784 placed in SEM_FAST block. The SEM_FAST registers are described in
3875 appendix B. In order to access the SEM_FAST registers the base address 4785 appendix B. In order to access the sem_fast registers the base address
3876 XSEM_REGISTERS_FAST_MEMORY (Offset: 0x2a0000) should be added to each 4786 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
3877 SEM_FAST register offset. */
3878#define XSEM_REG_FAST_MEMORY 0x2a0000 4787#define XSEM_REG_FAST_MEMORY 0x2a0000
3879/* [RW 1] Disables input messages from FIC0 May be updated during run_time 4788/* [RW 1] Disables input messages from FIC0 May be updated during run_time
3880 by the microcode */ 4789 by the microcode */
@@ -3957,6 +4866,9 @@
3957/* [RW 32] Interrupt mask register #0 read/write */ 4866/* [RW 32] Interrupt mask register #0 read/write */
3958#define XSEM_REG_XSEM_INT_MASK_0 0x280110 4867#define XSEM_REG_XSEM_INT_MASK_0 0x280110
3959#define XSEM_REG_XSEM_INT_MASK_1 0x280120 4868#define XSEM_REG_XSEM_INT_MASK_1 0x280120
4869/* [R 32] Interrupt register #0 read */
4870#define XSEM_REG_XSEM_INT_STS_0 0x280104
4871#define XSEM_REG_XSEM_INT_STS_1 0x280114
3960/* [RW 32] Parity mask register #0 read/write */ 4872/* [RW 32] Parity mask register #0 read/write */
3961#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 4873#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
3962#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 4874#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
@@ -3993,10 +4905,14 @@
3993#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) 4905#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
3994#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) 4906#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
3995#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) 4907#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
4908#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
4909#define EMAC_LED_100MB_OVERRIDE (1L<<2)
4910#define EMAC_LED_10MB_OVERRIDE (1L<<3)
4911#define EMAC_LED_2500MB_OVERRIDE (1L<<12)
4912#define EMAC_LED_OVERRIDE (1L<<0)
4913#define EMAC_LED_TRAFFIC (1L<<6)
3996#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) 4914#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
3997#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
3998#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) 4915#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
3999#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
4000#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) 4916#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
4001#define EMAC_MDIO_COMM_DATA (0xffffL<<0) 4917#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
4002#define EMAC_MDIO_COMM_START_BUSY (1L<<29) 4918#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
@@ -4005,14 +4921,12 @@
4005#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16) 4921#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
4006#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 4922#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
4007#define EMAC_MODE_25G_MODE (1L<<5) 4923#define EMAC_MODE_25G_MODE (1L<<5)
4008#define EMAC_MODE_ACPI_RCVD (1L<<20)
4009#define EMAC_MODE_HALF_DUPLEX (1L<<1) 4924#define EMAC_MODE_HALF_DUPLEX (1L<<1)
4010#define EMAC_MODE_MPKT (1L<<18)
4011#define EMAC_MODE_MPKT_RCVD (1L<<19)
4012#define EMAC_MODE_PORT_GMII (2L<<2) 4925#define EMAC_MODE_PORT_GMII (2L<<2)
4013#define EMAC_MODE_PORT_MII (1L<<2) 4926#define EMAC_MODE_PORT_MII (1L<<2)
4014#define EMAC_MODE_PORT_MII_10M (3L<<2) 4927#define EMAC_MODE_PORT_MII_10M (3L<<2)
4015#define EMAC_MODE_RESET (1L<<0) 4928#define EMAC_MODE_RESET (1L<<0)
4929#define EMAC_REG_EMAC_LED 0xc
4016#define EMAC_REG_EMAC_MAC_MATCH 0x10 4930#define EMAC_REG_EMAC_MAC_MATCH 0x10
4017#define EMAC_REG_EMAC_MDIO_COMM 0xac 4931#define EMAC_REG_EMAC_MDIO_COMM 0xac
4018#define EMAC_REG_EMAC_MDIO_MODE 0xb4 4932#define EMAC_REG_EMAC_MDIO_MODE 0xb4
@@ -4030,14 +4944,16 @@
4030#define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 4944#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
4031#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 4945#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
4032#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 4946#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
4033#define EMAC_TX_MODE_RESET (1L<<0) 4947#define MISC_REGISTERS_GPIO_0 0
4034#define MISC_REGISTERS_GPIO_1 1 4948#define MISC_REGISTERS_GPIO_1 1
4035#define MISC_REGISTERS_GPIO_2 2 4949#define MISC_REGISTERS_GPIO_2 2
4036#define MISC_REGISTERS_GPIO_3 3 4950#define MISC_REGISTERS_GPIO_3 3
4037#define MISC_REGISTERS_GPIO_CLR_POS 16 4951#define MISC_REGISTERS_GPIO_CLR_POS 16
4038#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) 4952#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
4039#define MISC_REGISTERS_GPIO_FLOAT_POS 24 4953#define MISC_REGISTERS_GPIO_FLOAT_POS 24
4954#define MISC_REGISTERS_GPIO_HIGH 1
4040#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 4955#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
4956#define MISC_REGISTERS_GPIO_LOW 0
4041#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 4957#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
4042#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 4958#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
4043#define MISC_REGISTERS_GPIO_PORT_SHIFT 4 4959#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
@@ -4127,7 +5043,7 @@
4127#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10) 5043#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
4128#define RESERVED_GENERAL_ATTENTION_BIT_0 0 5044#define RESERVED_GENERAL_ATTENTION_BIT_0 0
4129 5045
4130#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3e0 5046#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
4131#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 5047#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
4132 5048
4133#define RESERVED_GENERAL_ATTENTION_BIT_6 6 5049#define RESERVED_GENERAL_ATTENTION_BIT_6 6
@@ -4156,6 +5072,17 @@
4156/* mcp error attention bit */ 5072/* mcp error attention bit */
4157#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 5073#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
4158 5074
5075/*E1H NIG status sync attention mapped to group 4-7*/
5076#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5077#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5078#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5079#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5080#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5081#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5082#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5083#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5084
5085
4159#define LATCHED_ATTN_RBCR 23 5086#define LATCHED_ATTN_RBCR 23
4160#define LATCHED_ATTN_RBCT 24 5087#define LATCHED_ATTN_RBCT 24
4161#define LATCHED_ATTN_RBCN 25 5088#define LATCHED_ATTN_RBCN 25
@@ -4221,22 +5148,41 @@
4221#define PCICFG_OFFSET 0x2000 5148#define PCICFG_OFFSET 0x2000
4222#define PCICFG_VENDOR_ID_OFFSET 0x00 5149#define PCICFG_VENDOR_ID_OFFSET 0x00
4223#define PCICFG_DEVICE_ID_OFFSET 0x02 5150#define PCICFG_DEVICE_ID_OFFSET 0x02
4224#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 5151#define PCICFG_COMMAND_OFFSET 0x04
4225#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 5152#define PCICFG_STATUS_OFFSET 0x06
4226#define PCICFG_INT_LINE 0x3c 5153#define PCICFG_REVESION_ID 0x08
4227#define PCICFG_INT_PIN 0x3d
4228#define PCICFG_CACHE_LINE_SIZE 0x0c 5154#define PCICFG_CACHE_LINE_SIZE 0x0c
4229#define PCICFG_LATENCY_TIMER 0x0d 5155#define PCICFG_LATENCY_TIMER 0x0d
4230#define PCICFG_REVESION_ID 0x08 5156#define PCICFG_BAR_1_LOW 0x10
4231#define PCICFG_BAR_1_LOW 0x10 5157#define PCICFG_BAR_1_HIGH 0x14
4232#define PCICFG_BAR_1_HIGH 0x14 5158#define PCICFG_BAR_2_LOW 0x18
4233#define PCICFG_BAR_2_LOW 0x18 5159#define PCICFG_BAR_2_HIGH 0x1c
4234#define PCICFG_BAR_2_HIGH 0x1c 5160#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
4235#define PCICFG_GRC_ADDRESS 0x78 5161#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
4236#define PCICFG_GRC_DATA 0x80 5162#define PCICFG_INT_LINE 0x3c
5163#define PCICFG_INT_PIN 0x3d
5164#define PCICFG_PM_CSR_OFFSET 0x4c
5165#define PCICFG_GRC_ADDRESS 0x78
5166#define PCICFG_GRC_DATA 0x80
4237#define PCICFG_DEVICE_CONTROL 0xb4 5167#define PCICFG_DEVICE_CONTROL 0xb4
4238#define PCICFG_LINK_CONTROL 0xbc 5168#define PCICFG_LINK_CONTROL 0xbc
4239 5169
5170#define PCICFG_COMMAND_IO_SPACE (1<<0)
5171#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5172#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5173#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5174#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5175#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5176#define PCICFG_COMMAND_PERR_ENA (1<<6)
5177#define PCICFG_COMMAND_STEPPING (1<<7)
5178#define PCICFG_COMMAND_SERR_ENA (1<<8)
5179#define PCICFG_COMMAND_FAST_B2B (1<<9)
5180#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5181#define PCICFG_COMMAND_RESERVED (0x1f<<11)
5182
5183#define PCICFG_PM_CSR_STATE (0x3<<0)
5184#define PCICFG_PM_CSR_PME_STATUS (1<<15)
5185
4240#define BAR_USTRORM_INTMEM 0x400000 5186#define BAR_USTRORM_INTMEM 0x400000
4241#define BAR_CSTRORM_INTMEM 0x410000 5187#define BAR_CSTRORM_INTMEM 0x410000
4242#define BAR_XSTRORM_INTMEM 0x420000 5188#define BAR_XSTRORM_INTMEM 0x420000
@@ -4336,7 +5282,7 @@
4336#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 5282#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
4337 5283
4338#define MDIO_REG_BANK_CL73_IEEEB1 0x10 5284#define MDIO_REG_BANK_CL73_IEEEB1 0x10
4339#define MDIO_CL73_IEEEB1_AN_ADV2 0x01 5285#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
4340#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 5286#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
4341#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 5287#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
4342#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 5288#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
@@ -4365,7 +5311,7 @@
4365#define MDIO_REG_BANK_RX_ALL 0x80f0 5311#define MDIO_REG_BANK_RX_ALL 0x80f0
4366#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 5312#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
4367#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5313#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4368#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 5314#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
4369 5315
4370#define MDIO_REG_BANK_TX0 0x8060 5316#define MDIO_REG_BANK_TX0 0x8060
4371#define MDIO_TX0_TX_DRIVER 0x17 5317#define MDIO_TX0_TX_DRIVER 0x17
@@ -4392,213 +5338,266 @@
4392#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 5338#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
4393#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 5339#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
4394#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 5340#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
4395#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 5341#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
4396#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 5342#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
4397#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 5343#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
4398#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 5344#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
4399#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 5345#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
4400#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 5346#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
4401 5347
4402#define MDIO_REG_BANK_GP_STATUS 0x8120 5348#define MDIO_REG_BANK_GP_STATUS 0x8120
4403#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 5349#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
4404#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 5350#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
4405#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 5351#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
4406#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 5352#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
4407#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 5353#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
4408#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 5354#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
4409#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 5355#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
4410 5356#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
4411#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 5357#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
4412#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 5358#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
4413#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 5359#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
4414#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 5360#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
4415#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 5361#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
4416#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 5362#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
4417#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 5363#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
4418#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 5364#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
4419#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 5365#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
4420#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 5366#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
4421#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 5367#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
4422#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 5368#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
4423#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 5369#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
4424#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 5370#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
4425#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 5371#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
4426#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 5372#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
4427#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 5373#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
4428#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
4429 5374
4430 5375
4431#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 5376#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
4432#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 5377#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
4433#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 5378#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
4434#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 5379#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
4435#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 5380#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
4436 5381
4437#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 5382#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
4438#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 5383#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
4439#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 5384#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
4440#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 5385#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
4441#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 5386#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
4442#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 5387#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
4443#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 5388#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
4444#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 5389#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
4445#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 5390#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
4446#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 5391#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
4447#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 5392#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
4448#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 5393#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
4449#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 5394#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
4450#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 5395#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
4451#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 5396#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
4452#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 5397#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
4453#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 5398#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
4454#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 5399#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
4455#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 5400#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
4456#define MDIO_SERDES_DIGITAL_MISC1 0x18 5401#define MDIO_SERDES_DIGITAL_MISC1 0x18
4457#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 5402#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
4458#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 5403#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
4459#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 5404#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
4460#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 5405#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
4461#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 5406#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
4462#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 5407#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
4463#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 5408#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
4464#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 5409#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
4465#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 5410#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
4466#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 5411#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
4467#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 5412#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
4468#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 5413#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
4469#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 5414#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
4470#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 5415#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
4471#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 5416#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
4472#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 5417#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
4473#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 5418#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
4474#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 5419#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
4475 5420
4476#define MDIO_REG_BANK_OVER_1G 0x8320 5421#define MDIO_REG_BANK_OVER_1G 0x8320
4477#define MDIO_OVER_1G_DIGCTL_3_4 0x14 5422#define MDIO_OVER_1G_DIGCTL_3_4 0x14
4478#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 5423#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
4479#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 5424#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
4480#define MDIO_OVER_1G_UP1 0x19 5425#define MDIO_OVER_1G_UP1 0x19
4481#define MDIO_OVER_1G_UP1_2_5G 0x0001 5426#define MDIO_OVER_1G_UP1_2_5G 0x0001
4482#define MDIO_OVER_1G_UP1_5G 0x0002 5427#define MDIO_OVER_1G_UP1_5G 0x0002
4483#define MDIO_OVER_1G_UP1_6G 0x0004 5428#define MDIO_OVER_1G_UP1_6G 0x0004
4484#define MDIO_OVER_1G_UP1_10G 0x0010 5429#define MDIO_OVER_1G_UP1_10G 0x0010
4485#define MDIO_OVER_1G_UP1_10GH 0x0008 5430#define MDIO_OVER_1G_UP1_10GH 0x0008
4486#define MDIO_OVER_1G_UP1_12G 0x0020 5431#define MDIO_OVER_1G_UP1_12G 0x0020
4487#define MDIO_OVER_1G_UP1_12_5G 0x0040 5432#define MDIO_OVER_1G_UP1_12_5G 0x0040
4488#define MDIO_OVER_1G_UP1_13G 0x0080 5433#define MDIO_OVER_1G_UP1_13G 0x0080
4489#define MDIO_OVER_1G_UP1_15G 0x0100 5434#define MDIO_OVER_1G_UP1_15G 0x0100
4490#define MDIO_OVER_1G_UP1_16G 0x0200 5435#define MDIO_OVER_1G_UP1_16G 0x0200
4491#define MDIO_OVER_1G_UP2 0x1A 5436#define MDIO_OVER_1G_UP2 0x1A
4492#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 5437#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
4493#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 5438#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
4494#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 5439#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
4495#define MDIO_OVER_1G_UP3 0x1B 5440#define MDIO_OVER_1G_UP3 0x1B
4496#define MDIO_OVER_1G_UP3_HIGIG2 0x0001 5441#define MDIO_OVER_1G_UP3_HIGIG2 0x0001
4497#define MDIO_OVER_1G_LP_UP1 0x1C 5442#define MDIO_OVER_1G_LP_UP1 0x1C
4498#define MDIO_OVER_1G_LP_UP2 0x1D 5443#define MDIO_OVER_1G_LP_UP2 0x1D
4499#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 5444#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
4500#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 5445#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
4501#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 5446#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
4502#define MDIO_OVER_1G_LP_UP3 0x1E 5447#define MDIO_OVER_1G_LP_UP3 0x1E
4503 5448
4504#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 5449#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
4505#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 5450#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
4506#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 5451#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
4507#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 5452#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
5453
5454#define MDIO_REG_BANK_CL73_USERB0 0x8370
5455#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
5456#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
5457#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
5458#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
5459#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
5460#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
5461
5462#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
5463#define MDIO_AER_BLOCK_AER_REG 0x1E
5464
5465#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
5466#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
5467#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
5468#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
5469#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
5470#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
5471#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
5472#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
5473#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
5474#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
5475#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
5476#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
5477#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
5478#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
5479#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
5480#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
5481#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
5482#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
5483#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
5484#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
5485#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
5486#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
5487#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
5488#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
5489#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
5490#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
5491#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
5492#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
5493#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
5494#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
5495#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
5496/*WhenthelinkpartnerisinSGMIImode(bit0=1),then
5497bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
5498Theotherbitsarereservedandshouldbezero*/
5499#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
5500
5501
5502#define MDIO_PMA_DEVAD 0x1
5503/*ieee*/
5504#define MDIO_PMA_REG_CTRL 0x0
5505#define MDIO_PMA_REG_STATUS 0x1
5506#define MDIO_PMA_REG_10G_CTRL2 0x7
5507#define MDIO_PMA_REG_RX_SD 0xa
5508/*bcm*/
5509#define MDIO_PMA_REG_BCM_CTRL 0x0096
5510#define MDIO_PMA_REG_FEC_CTRL 0x00ab
5511#define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
5512#define MDIO_PMA_REG_LASI_CTRL 0x9002
5513#define MDIO_PMA_REG_RX_ALARM 0x9003
5514#define MDIO_PMA_REG_TX_ALARM 0x9004
5515#define MDIO_PMA_REG_LASI_STATUS 0x9005
5516#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
5517#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
5518#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
5519#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
5520#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
5521#define MDIO_PMA_REG_MISC_CTRL 0xca0a
5522#define MDIO_PMA_REG_GEN_CTRL 0xca10
5523#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
5524#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
5525#define MDIO_PMA_REG_ROM_VER1 0xca19
5526#define MDIO_PMA_REG_ROM_VER2 0xca1a
5527#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
5528#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
5529#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
5530#define MDIO_PMA_REG_MISC_CTRL1 0xca85
5531
5532#define MDIO_PMA_REG_7101_RESET 0xc000
5533#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
5534#define MDIO_PMA_REG_7101_VER1 0xc026
5535#define MDIO_PMA_REG_7101_VER2 0xc027
5536
5537
5538#define MDIO_WIS_DEVAD 0x2
5539/*bcm*/
5540#define MDIO_WIS_REG_LASI_CNTL 0x9002
5541#define MDIO_WIS_REG_LASI_STATUS 0x9005
5542
5543#define MDIO_PCS_DEVAD 0x3
5544#define MDIO_PCS_REG_STATUS 0x0020
5545#define MDIO_PCS_REG_LASI_STATUS 0x9005
5546#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
5547#define MDIO_PCS_REG_7101_SPI_MUX 0xD008
5548#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
5549#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
5550#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
5551#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
5552#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
5553#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
5554#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
5555
4508 5556
4509#define MDIO_REG_BANK_CL73_USERB0 0x8370 5557#define MDIO_XS_DEVAD 0x4
4510#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 5558#define MDIO_XS_PLL_SEQUENCER 0x8000
4511#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 5559#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
4512#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
4513#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
4514#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
4515#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
4516 5560
4517#define MDIO_REG_BANK_AER_BLOCK 0xFFD0 5561#define MDIO_AN_DEVAD 0x7
4518#define MDIO_AER_BLOCK_AER_REG 0x1E 5562/*ieee*/
5563#define MDIO_AN_REG_CTRL 0x0000
5564#define MDIO_AN_REG_STATUS 0x0001
5565#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
5566#define MDIO_AN_REG_ADV_PAUSE 0x0010
5567#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
5568#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
5569#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
5570#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
5571#define MDIO_AN_REG_ADV 0x0011
5572#define MDIO_AN_REG_ADV2 0x0012
5573#define MDIO_AN_REG_LP_AUTO_NEG 0x0013
5574#define MDIO_AN_REG_MASTER_STATUS 0x0021
5575/*bcm*/
5576#define MDIO_AN_REG_LINK_STATUS 0x8304
5577#define MDIO_AN_REG_CL37_CL73 0x8370
5578#define MDIO_AN_REG_CL37_AN 0xffe0
5579#define MDIO_AN_REG_CL37_FD 0xffe4
4519 5580
4520#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
4521#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
4522#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
4523#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
4524#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
4525#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
4526#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
4527#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
4528#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
4529#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
4530#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
4531#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
4532#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
4533#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
4534#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
4535#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
4536#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
4537#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
4538#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
4539#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
4540#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
4541#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
4542#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
4543#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
4544#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
4545#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
4546#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
4547#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE\
4548 0x0000
4549#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH\
4550 0x0180
4551#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
4552#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
4553#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
4554 5581
5582#define IGU_FUNC_BASE 0x0400
4555 5583
4556#define EXT_PHY_AUTO_NEG_DEVAD 0x7 5584#define IGU_ADDR_MSIX 0x0000
4557#define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1 5585#define IGU_ADDR_INT_ACK 0x0200
4558#define EXT_PHY_OPT_WIS_DEVAD 0x2 5586#define IGU_ADDR_PROD_UPD 0x0201
4559#define EXT_PHY_OPT_PCS_DEVAD 0x3 5587#define IGU_ADDR_ATTN_BITS_UPD 0x0202
4560#define EXT_PHY_OPT_PHY_XS_DEVAD 0x4 5588#define IGU_ADDR_ATTN_BITS_SET 0x0203
4561#define EXT_PHY_OPT_CNTL 0x0 5589#define IGU_ADDR_ATTN_BITS_CLR 0x0204
4562#define EXT_PHY_OPT_CNTL2 0x7 5590#define IGU_ADDR_COALESCE_NOW 0x0205
4563#define EXT_PHY_OPT_PMD_RX_SD 0xa 5591#define IGU_ADDR_SIMD_MASK 0x0206
4564#define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a 5592#define IGU_ADDR_SIMD_NOMASK 0x0207
4565#define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800 5593#define IGU_ADDR_MSI_CTL 0x0210
4566#define EXT_PHY_OPT_PMD_DIGITAL_CNT 0xc808 5594#define IGU_ADDR_MSI_ADDR_LO 0x0211
4567#define EXT_PHY_OPT_PMD_DIGITAL_SATUS 0xc809 5595#define IGU_ADDR_MSI_ADDR_HI 0x0212
4568#define EXT_PHY_OPT_CMU_PLL_BYPASS 0xca09 5596#define IGU_ADDR_MSI_DATA 0x0213
4569#define EXT_PHY_OPT_LASI_CNTL 0x9002
4570#define EXT_PHY_OPT_RX_ALARM 0x9003
4571#define EXT_PHY_OPT_LASI_STATUS 0x9005
4572#define EXT_PHY_OPT_PCS_STATUS 0x0020
4573#define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018
4574#define EXT_PHY_OPT_AN_LINK_STATUS 0x8304
4575#define EXT_PHY_OPT_AN_CL37_CL73 0x8370
4576#define EXT_PHY_OPT_AN_CL37_FD 0xffe4
4577#define EXT_PHY_OPT_AN_CL37_AN 0xffe0
4578#define EXT_PHY_OPT_AN_ADV 0x11
4579 5597
4580#define EXT_PHY_KR_PMA_PMD_DEVAD 0x1 5598#define IGU_INT_ENABLE 0
4581#define EXT_PHY_KR_PCS_DEVAD 0x3 5599#define IGU_INT_DISABLE 1
4582#define EXT_PHY_KR_AUTO_NEG_DEVAD 0x7 5600#define IGU_INT_NOP 2
4583#define EXT_PHY_KR_CTRL 0x0000 5601#define IGU_INT_NOP2 3
4584#define EXT_PHY_KR_STATUS 0x0001
4585#define EXT_PHY_KR_AUTO_NEG_COMPLETE 0x0020
4586#define EXT_PHY_KR_AUTO_NEG_ADVERT 0x0010
4587#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE 0x0400
4588#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC 0x0800
4589#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH 0x0C00
4590#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK 0x0C00
4591#define EXT_PHY_KR_LP_AUTO_NEG 0x0013
4592#define EXT_PHY_KR_CTRL2 0x0007
4593#define EXT_PHY_KR_PCS_STATUS 0x0020
4594#define EXT_PHY_KR_PMD_CTRL 0x0096
4595#define EXT_PHY_KR_LASI_CNTL 0x9002
4596#define EXT_PHY_KR_LASI_STATUS 0x9005
4597#define EXT_PHY_KR_MISC_CTRL1 0xca85
4598#define EXT_PHY_KR_GEN_CTRL 0xca10
4599#define EXT_PHY_KR_ROM_CODE 0xca19
4600#define EXT_PHY_KR_ROM_RESET_INTERNAL_MP 0x0188
4601#define EXT_PHY_KR_ROM_MICRO_RESET 0x018a
4602 5602
4603#define EXT_PHY_SFX7101_XGXS_TEST1 0xc00a
4604 5603
diff --git a/drivers/net/bonding/bond_alb.c b/drivers/net/bonding/bond_alb.c
index 5a673725471c..b211486a0ca3 100644
--- a/drivers/net/bonding/bond_alb.c
+++ b/drivers/net/bonding/bond_alb.c
@@ -419,8 +419,10 @@ static void rlb_teach_disabled_mac_on_primary(struct bonding *bond, u8 addr[])
419 } 419 }
420 420
421 if (!bond->alb_info.primary_is_promisc) { 421 if (!bond->alb_info.primary_is_promisc) {
422 bond->alb_info.primary_is_promisc = 1; 422 if (!dev_set_promiscuity(bond->curr_active_slave->dev, 1))
423 dev_set_promiscuity(bond->curr_active_slave->dev, 1); 423 bond->alb_info.primary_is_promisc = 1;
424 else
425 bond->alb_info.primary_is_promisc = 0;
424 } 426 }
425 427
426 bond->alb_info.rlb_promisc_timeout_counter = 0; 428 bond->alb_info.rlb_promisc_timeout_counter = 0;
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 50a40e433154..9737c06045d6 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -88,6 +88,7 @@
88#define BOND_LINK_ARP_INTERV 0 88#define BOND_LINK_ARP_INTERV 0
89 89
90static int max_bonds = BOND_DEFAULT_MAX_BONDS; 90static int max_bonds = BOND_DEFAULT_MAX_BONDS;
91static int num_grat_arp = 1;
91static int miimon = BOND_LINK_MON_INTERV; 92static int miimon = BOND_LINK_MON_INTERV;
92static int updelay = 0; 93static int updelay = 0;
93static int downdelay = 0; 94static int downdelay = 0;
@@ -99,11 +100,13 @@ static char *xmit_hash_policy = NULL;
99static int arp_interval = BOND_LINK_ARP_INTERV; 100static int arp_interval = BOND_LINK_ARP_INTERV;
100static char *arp_ip_target[BOND_MAX_ARP_TARGETS] = { NULL, }; 101static char *arp_ip_target[BOND_MAX_ARP_TARGETS] = { NULL, };
101static char *arp_validate = NULL; 102static char *arp_validate = NULL;
102static int fail_over_mac = 0; 103static char *fail_over_mac = NULL;
103struct bond_params bonding_defaults; 104struct bond_params bonding_defaults;
104 105
105module_param(max_bonds, int, 0); 106module_param(max_bonds, int, 0);
106MODULE_PARM_DESC(max_bonds, "Max number of bonded devices"); 107MODULE_PARM_DESC(max_bonds, "Max number of bonded devices");
108module_param(num_grat_arp, int, 0644);
109MODULE_PARM_DESC(num_grat_arp, "Number of gratuitous ARP packets to send on failover event");
107module_param(miimon, int, 0); 110module_param(miimon, int, 0);
108MODULE_PARM_DESC(miimon, "Link check interval in milliseconds"); 111MODULE_PARM_DESC(miimon, "Link check interval in milliseconds");
109module_param(updelay, int, 0); 112module_param(updelay, int, 0);
@@ -133,8 +136,8 @@ module_param_array(arp_ip_target, charp, NULL, 0);
133MODULE_PARM_DESC(arp_ip_target, "arp targets in n.n.n.n form"); 136MODULE_PARM_DESC(arp_ip_target, "arp targets in n.n.n.n form");
134module_param(arp_validate, charp, 0); 137module_param(arp_validate, charp, 0);
135MODULE_PARM_DESC(arp_validate, "validate src/dst of ARP probes: none (default), active, backup or all"); 138MODULE_PARM_DESC(arp_validate, "validate src/dst of ARP probes: none (default), active, backup or all");
136module_param(fail_over_mac, int, 0); 139module_param(fail_over_mac, charp, 0);
137MODULE_PARM_DESC(fail_over_mac, "For active-backup, do not set all slaves to the same MAC. 0 of off (default), 1 for on."); 140MODULE_PARM_DESC(fail_over_mac, "For active-backup, do not set all slaves to the same MAC. none (default), active or follow");
138 141
139/*----------------------------- Global variables ----------------------------*/ 142/*----------------------------- Global variables ----------------------------*/
140 143
@@ -187,6 +190,13 @@ struct bond_parm_tbl arp_validate_tbl[] = {
187{ NULL, -1}, 190{ NULL, -1},
188}; 191};
189 192
193struct bond_parm_tbl fail_over_mac_tbl[] = {
194{ "none", BOND_FOM_NONE},
195{ "active", BOND_FOM_ACTIVE},
196{ "follow", BOND_FOM_FOLLOW},
197{ NULL, -1},
198};
199
190/*-------------------------- Forward declarations ---------------------------*/ 200/*-------------------------- Forward declarations ---------------------------*/
191 201
192static void bond_send_gratuitous_arp(struct bonding *bond); 202static void bond_send_gratuitous_arp(struct bonding *bond);
@@ -261,14 +271,14 @@ static int bond_add_vlan(struct bonding *bond, unsigned short vlan_id)
261 */ 271 */
262static int bond_del_vlan(struct bonding *bond, unsigned short vlan_id) 272static int bond_del_vlan(struct bonding *bond, unsigned short vlan_id)
263{ 273{
264 struct vlan_entry *vlan, *next; 274 struct vlan_entry *vlan;
265 int res = -ENODEV; 275 int res = -ENODEV;
266 276
267 dprintk("bond: %s, vlan id %d\n", bond->dev->name, vlan_id); 277 dprintk("bond: %s, vlan id %d\n", bond->dev->name, vlan_id);
268 278
269 write_lock_bh(&bond->lock); 279 write_lock_bh(&bond->lock);
270 280
271 list_for_each_entry_safe(vlan, next, &bond->vlan_list, vlan_list) { 281 list_for_each_entry(vlan, &bond->vlan_list, vlan_list) {
272 if (vlan->vlan_id == vlan_id) { 282 if (vlan->vlan_id == vlan_id) {
273 list_del(&vlan->vlan_list); 283 list_del(&vlan->vlan_list);
274 284
@@ -762,39 +772,49 @@ static struct dev_mc_list *bond_mc_list_find_dmi(struct dev_mc_list *dmi, struct
762/* 772/*
763 * Push the promiscuity flag down to appropriate slaves 773 * Push the promiscuity flag down to appropriate slaves
764 */ 774 */
765static void bond_set_promiscuity(struct bonding *bond, int inc) 775static int bond_set_promiscuity(struct bonding *bond, int inc)
766{ 776{
777 int err = 0;
767 if (USES_PRIMARY(bond->params.mode)) { 778 if (USES_PRIMARY(bond->params.mode)) {
768 /* write lock already acquired */ 779 /* write lock already acquired */
769 if (bond->curr_active_slave) { 780 if (bond->curr_active_slave) {
770 dev_set_promiscuity(bond->curr_active_slave->dev, inc); 781 err = dev_set_promiscuity(bond->curr_active_slave->dev,
782 inc);
771 } 783 }
772 } else { 784 } else {
773 struct slave *slave; 785 struct slave *slave;
774 int i; 786 int i;
775 bond_for_each_slave(bond, slave, i) { 787 bond_for_each_slave(bond, slave, i) {
776 dev_set_promiscuity(slave->dev, inc); 788 err = dev_set_promiscuity(slave->dev, inc);
789 if (err)
790 return err;
777 } 791 }
778 } 792 }
793 return err;
779} 794}
780 795
781/* 796/*
782 * Push the allmulti flag down to all slaves 797 * Push the allmulti flag down to all slaves
783 */ 798 */
784static void bond_set_allmulti(struct bonding *bond, int inc) 799static int bond_set_allmulti(struct bonding *bond, int inc)
785{ 800{
801 int err = 0;
786 if (USES_PRIMARY(bond->params.mode)) { 802 if (USES_PRIMARY(bond->params.mode)) {
787 /* write lock already acquired */ 803 /* write lock already acquired */
788 if (bond->curr_active_slave) { 804 if (bond->curr_active_slave) {
789 dev_set_allmulti(bond->curr_active_slave->dev, inc); 805 err = dev_set_allmulti(bond->curr_active_slave->dev,
806 inc);
790 } 807 }
791 } else { 808 } else {
792 struct slave *slave; 809 struct slave *slave;
793 int i; 810 int i;
794 bond_for_each_slave(bond, slave, i) { 811 bond_for_each_slave(bond, slave, i) {
795 dev_set_allmulti(slave->dev, inc); 812 err = dev_set_allmulti(slave->dev, inc);
813 if (err)
814 return err;
796 } 815 }
797 } 816 }
817 return err;
798} 818}
799 819
800/* 820/*
@@ -955,6 +975,7 @@ static void bond_mc_swap(struct bonding *bond, struct slave *new_active, struct
955 } 975 }
956 976
957 if (new_active) { 977 if (new_active) {
978 /* FIXME: Signal errors upstream. */
958 if (bond->dev->flags & IFF_PROMISC) { 979 if (bond->dev->flags & IFF_PROMISC) {
959 dev_set_promiscuity(new_active->dev, 1); 980 dev_set_promiscuity(new_active->dev, 1);
960 } 981 }
@@ -970,6 +991,82 @@ static void bond_mc_swap(struct bonding *bond, struct slave *new_active, struct
970 } 991 }
971} 992}
972 993
994/*
995 * bond_do_fail_over_mac
996 *
997 * Perform special MAC address swapping for fail_over_mac settings
998 *
999 * Called with RTNL, bond->lock for read, curr_slave_lock for write_bh.
1000 */
1001static void bond_do_fail_over_mac(struct bonding *bond,
1002 struct slave *new_active,
1003 struct slave *old_active)
1004{
1005 u8 tmp_mac[ETH_ALEN];
1006 struct sockaddr saddr;
1007 int rv;
1008
1009 switch (bond->params.fail_over_mac) {
1010 case BOND_FOM_ACTIVE:
1011 if (new_active)
1012 memcpy(bond->dev->dev_addr, new_active->dev->dev_addr,
1013 new_active->dev->addr_len);
1014 break;
1015 case BOND_FOM_FOLLOW:
1016 /*
1017 * if new_active && old_active, swap them
1018 * if just old_active, do nothing (going to no active slave)
1019 * if just new_active, set new_active to bond's MAC
1020 */
1021 if (!new_active)
1022 return;
1023
1024 write_unlock_bh(&bond->curr_slave_lock);
1025 read_unlock(&bond->lock);
1026
1027 if (old_active) {
1028 memcpy(tmp_mac, new_active->dev->dev_addr, ETH_ALEN);
1029 memcpy(saddr.sa_data, old_active->dev->dev_addr,
1030 ETH_ALEN);
1031 saddr.sa_family = new_active->dev->type;
1032 } else {
1033 memcpy(saddr.sa_data, bond->dev->dev_addr, ETH_ALEN);
1034 saddr.sa_family = bond->dev->type;
1035 }
1036
1037 rv = dev_set_mac_address(new_active->dev, &saddr);
1038 if (rv) {
1039 printk(KERN_ERR DRV_NAME
1040 ": %s: Error %d setting MAC of slave %s\n",
1041 bond->dev->name, -rv, new_active->dev->name);
1042 goto out;
1043 }
1044
1045 if (!old_active)
1046 goto out;
1047
1048 memcpy(saddr.sa_data, tmp_mac, ETH_ALEN);
1049 saddr.sa_family = old_active->dev->type;
1050
1051 rv = dev_set_mac_address(old_active->dev, &saddr);
1052 if (rv)
1053 printk(KERN_ERR DRV_NAME
1054 ": %s: Error %d setting MAC of slave %s\n",
1055 bond->dev->name, -rv, new_active->dev->name);
1056out:
1057 read_lock(&bond->lock);
1058 write_lock_bh(&bond->curr_slave_lock);
1059 break;
1060 default:
1061 printk(KERN_ERR DRV_NAME
1062 ": %s: bond_do_fail_over_mac impossible: bad policy %d\n",
1063 bond->dev->name, bond->params.fail_over_mac);
1064 break;
1065 }
1066
1067}
1068
1069
973/** 1070/**
974 * find_best_interface - select the best available slave to be the active one 1071 * find_best_interface - select the best available slave to be the active one
975 * @bond: our bonding struct 1072 * @bond: our bonding struct
@@ -1037,7 +1134,8 @@ static struct slave *bond_find_best_slave(struct bonding *bond)
1037 * because it is apparently the best available slave we have, even though its 1134 * because it is apparently the best available slave we have, even though its
1038 * updelay hasn't timed out yet. 1135 * updelay hasn't timed out yet.
1039 * 1136 *
1040 * Warning: Caller must hold curr_slave_lock for writing. 1137 * If new_active is not NULL, caller must hold bond->lock for read and
1138 * curr_slave_lock for write_bh.
1041 */ 1139 */
1042void bond_change_active_slave(struct bonding *bond, struct slave *new_active) 1140void bond_change_active_slave(struct bonding *bond, struct slave *new_active)
1043{ 1141{
@@ -1048,6 +1146,8 @@ void bond_change_active_slave(struct bonding *bond, struct slave *new_active)
1048 } 1146 }
1049 1147
1050 if (new_active) { 1148 if (new_active) {
1149 new_active->jiffies = jiffies;
1150
1051 if (new_active->link == BOND_LINK_BACK) { 1151 if (new_active->link == BOND_LINK_BACK) {
1052 if (USES_PRIMARY(bond->params.mode)) { 1152 if (USES_PRIMARY(bond->params.mode)) {
1053 printk(KERN_INFO DRV_NAME 1153 printk(KERN_INFO DRV_NAME
@@ -1059,7 +1159,6 @@ void bond_change_active_slave(struct bonding *bond, struct slave *new_active)
1059 1159
1060 new_active->delay = 0; 1160 new_active->delay = 0;
1061 new_active->link = BOND_LINK_UP; 1161 new_active->link = BOND_LINK_UP;
1062 new_active->jiffies = jiffies;
1063 1162
1064 if (bond->params.mode == BOND_MODE_8023AD) { 1163 if (bond->params.mode == BOND_MODE_8023AD) {
1065 bond_3ad_handle_link_change(new_active, BOND_LINK_UP); 1164 bond_3ad_handle_link_change(new_active, BOND_LINK_UP);
@@ -1101,22 +1200,22 @@ void bond_change_active_slave(struct bonding *bond, struct slave *new_active)
1101 1200
1102 if (new_active) { 1201 if (new_active) {
1103 bond_set_slave_active_flags(new_active); 1202 bond_set_slave_active_flags(new_active);
1104 }
1105 1203
1106 /* when bonding does not set the slave MAC address, the bond MAC 1204 if (bond->params.fail_over_mac)
1107 * address is the one of the active slave. 1205 bond_do_fail_over_mac(bond, new_active,
1108 */ 1206 old_active);
1109 if (new_active && bond->params.fail_over_mac) 1207
1110 memcpy(bond->dev->dev_addr, new_active->dev->dev_addr, 1208 bond->send_grat_arp = bond->params.num_grat_arp;
1111 new_active->dev->addr_len);
1112 if (bond->curr_active_slave &&
1113 test_bit(__LINK_STATE_LINKWATCH_PENDING,
1114 &bond->curr_active_slave->dev->state)) {
1115 dprintk("delaying gratuitous arp on %s\n",
1116 bond->curr_active_slave->dev->name);
1117 bond->send_grat_arp = 1;
1118 } else
1119 bond_send_gratuitous_arp(bond); 1209 bond_send_gratuitous_arp(bond);
1210
1211 write_unlock_bh(&bond->curr_slave_lock);
1212 read_unlock(&bond->lock);
1213
1214 netdev_bonding_change(bond->dev);
1215
1216 read_lock(&bond->lock);
1217 write_lock_bh(&bond->curr_slave_lock);
1218 }
1120 } 1219 }
1121} 1220}
1122 1221
@@ -1129,7 +1228,7 @@ void bond_change_active_slave(struct bonding *bond, struct slave *new_active)
1129 * - The primary_slave has got its link back. 1228 * - The primary_slave has got its link back.
1130 * - A slave has got its link back and there's no old curr_active_slave. 1229 * - A slave has got its link back and there's no old curr_active_slave.
1131 * 1230 *
1132 * Warning: Caller must hold curr_slave_lock for writing. 1231 * Caller must hold bond->lock for read and curr_slave_lock for write_bh.
1133 */ 1232 */
1134void bond_select_active_slave(struct bonding *bond) 1233void bond_select_active_slave(struct bonding *bond)
1135{ 1234{
@@ -1376,14 +1475,14 @@ int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev)
1376 printk(KERN_WARNING DRV_NAME 1475 printk(KERN_WARNING DRV_NAME
1377 ": %s: Warning: The first slave device " 1476 ": %s: Warning: The first slave device "
1378 "specified does not support setting the MAC " 1477 "specified does not support setting the MAC "
1379 "address. Enabling the fail_over_mac option.", 1478 "address. Setting fail_over_mac to active.",
1380 bond_dev->name); 1479 bond_dev->name);
1381 bond->params.fail_over_mac = 1; 1480 bond->params.fail_over_mac = BOND_FOM_ACTIVE;
1382 } else if (!bond->params.fail_over_mac) { 1481 } else if (bond->params.fail_over_mac != BOND_FOM_ACTIVE) {
1383 printk(KERN_ERR DRV_NAME 1482 printk(KERN_ERR DRV_NAME
1384 ": %s: Error: The slave device specified " 1483 ": %s: Error: The slave device specified "
1385 "does not support setting the MAC address, " 1484 "does not support setting the MAC address, "
1386 "but fail_over_mac is not enabled.\n" 1485 "but fail_over_mac is not set to active.\n"
1387 , bond_dev->name); 1486 , bond_dev->name);
1388 res = -EOPNOTSUPP; 1487 res = -EOPNOTSUPP;
1389 goto err_undo_flags; 1488 goto err_undo_flags;
@@ -1456,20 +1555,24 @@ int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev)
1456 if (!USES_PRIMARY(bond->params.mode)) { 1555 if (!USES_PRIMARY(bond->params.mode)) {
1457 /* set promiscuity level to new slave */ 1556 /* set promiscuity level to new slave */
1458 if (bond_dev->flags & IFF_PROMISC) { 1557 if (bond_dev->flags & IFF_PROMISC) {
1459 dev_set_promiscuity(slave_dev, 1); 1558 res = dev_set_promiscuity(slave_dev, 1);
1559 if (res)
1560 goto err_close;
1460 } 1561 }
1461 1562
1462 /* set allmulti level to new slave */ 1563 /* set allmulti level to new slave */
1463 if (bond_dev->flags & IFF_ALLMULTI) { 1564 if (bond_dev->flags & IFF_ALLMULTI) {
1464 dev_set_allmulti(slave_dev, 1); 1565 res = dev_set_allmulti(slave_dev, 1);
1566 if (res)
1567 goto err_close;
1465 } 1568 }
1466 1569
1467 netif_tx_lock_bh(bond_dev); 1570 netif_addr_lock_bh(bond_dev);
1468 /* upload master's mc_list to new slave */ 1571 /* upload master's mc_list to new slave */
1469 for (dmi = bond_dev->mc_list; dmi; dmi = dmi->next) { 1572 for (dmi = bond_dev->mc_list; dmi; dmi = dmi->next) {
1470 dev_mc_add (slave_dev, dmi->dmi_addr, dmi->dmi_addrlen, 0); 1573 dev_mc_add (slave_dev, dmi->dmi_addr, dmi->dmi_addrlen, 0);
1471 } 1574 }
1472 netif_tx_unlock_bh(bond_dev); 1575 netif_addr_unlock_bh(bond_dev);
1473 } 1576 }
1474 1577
1475 if (bond->params.mode == BOND_MODE_8023AD) { 1578 if (bond->params.mode == BOND_MODE_8023AD) {
@@ -1490,6 +1593,10 @@ int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev)
1490 1593
1491 bond_compute_features(bond); 1594 bond_compute_features(bond);
1492 1595
1596 write_unlock_bh(&bond->lock);
1597
1598 read_lock(&bond->lock);
1599
1493 new_slave->last_arp_rx = jiffies; 1600 new_slave->last_arp_rx = jiffies;
1494 1601
1495 if (bond->params.miimon && !bond->params.use_carrier) { 1602 if (bond->params.miimon && !bond->params.use_carrier) {
@@ -1566,6 +1673,8 @@ int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev)
1566 } 1673 }
1567 } 1674 }
1568 1675
1676 write_lock_bh(&bond->curr_slave_lock);
1677
1569 switch (bond->params.mode) { 1678 switch (bond->params.mode) {
1570 case BOND_MODE_ACTIVEBACKUP: 1679 case BOND_MODE_ACTIVEBACKUP:
1571 bond_set_slave_inactive_flags(new_slave); 1680 bond_set_slave_inactive_flags(new_slave);
@@ -1613,9 +1722,11 @@ int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev)
1613 break; 1722 break;
1614 } /* switch(bond_mode) */ 1723 } /* switch(bond_mode) */
1615 1724
1725 write_unlock_bh(&bond->curr_slave_lock);
1726
1616 bond_set_carrier(bond); 1727 bond_set_carrier(bond);
1617 1728
1618 write_unlock_bh(&bond->lock); 1729 read_unlock(&bond->lock);
1619 1730
1620 res = bond_create_slave_symlinks(bond_dev, slave_dev); 1731 res = bond_create_slave_symlinks(bond_dev, slave_dev);
1621 if (res) 1732 if (res)
@@ -1639,6 +1750,10 @@ err_unset_master:
1639 1750
1640err_restore_mac: 1751err_restore_mac:
1641 if (!bond->params.fail_over_mac) { 1752 if (!bond->params.fail_over_mac) {
1753 /* XXX TODO - fom follow mode needs to change master's
1754 * MAC if this slave's MAC is in use by the bond, or at
1755 * least print a warning.
1756 */
1642 memcpy(addr.sa_data, new_slave->perm_hwaddr, ETH_ALEN); 1757 memcpy(addr.sa_data, new_slave->perm_hwaddr, ETH_ALEN);
1643 addr.sa_family = slave_dev->type; 1758 addr.sa_family = slave_dev->type;
1644 dev_set_mac_address(slave_dev, &addr); 1759 dev_set_mac_address(slave_dev, &addr);
@@ -1693,20 +1808,18 @@ int bond_release(struct net_device *bond_dev, struct net_device *slave_dev)
1693 return -EINVAL; 1808 return -EINVAL;
1694 } 1809 }
1695 1810
1696 mac_addr_differ = memcmp(bond_dev->dev_addr, 1811 if (!bond->params.fail_over_mac) {
1697 slave->perm_hwaddr, 1812 mac_addr_differ = memcmp(bond_dev->dev_addr, slave->perm_hwaddr,
1698 ETH_ALEN); 1813 ETH_ALEN);
1699 if (!mac_addr_differ && (bond->slave_cnt > 1)) { 1814 if (!mac_addr_differ && (bond->slave_cnt > 1))
1700 printk(KERN_WARNING DRV_NAME 1815 printk(KERN_WARNING DRV_NAME
1701 ": %s: Warning: the permanent HWaddr of %s - " 1816 ": %s: Warning: the permanent HWaddr of %s - "
1702 "%s - is still in use by %s. " 1817 "%s - is still in use by %s. "
1703 "Set the HWaddr of %s to a different address " 1818 "Set the HWaddr of %s to a different address "
1704 "to avoid conflicts.\n", 1819 "to avoid conflicts.\n",
1705 bond_dev->name, 1820 bond_dev->name, slave_dev->name,
1706 slave_dev->name, 1821 print_mac(mac, slave->perm_hwaddr),
1707 print_mac(mac, slave->perm_hwaddr), 1822 bond_dev->name, slave_dev->name);
1708 bond_dev->name,
1709 slave_dev->name);
1710 } 1823 }
1711 1824
1712 /* Inform AD package of unbinding of slave. */ 1825 /* Inform AD package of unbinding of slave. */
@@ -1823,9 +1936,9 @@ int bond_release(struct net_device *bond_dev, struct net_device *slave_dev)
1823 } 1936 }
1824 1937
1825 /* flush master's mc_list from slave */ 1938 /* flush master's mc_list from slave */
1826 netif_tx_lock_bh(bond_dev); 1939 netif_addr_lock_bh(bond_dev);
1827 bond_mc_list_flush(bond_dev, slave_dev); 1940 bond_mc_list_flush(bond_dev, slave_dev);
1828 netif_tx_unlock_bh(bond_dev); 1941 netif_addr_unlock_bh(bond_dev);
1829 } 1942 }
1830 1943
1831 netdev_set_master(slave_dev, NULL); 1944 netdev_set_master(slave_dev, NULL);
@@ -1833,7 +1946,7 @@ int bond_release(struct net_device *bond_dev, struct net_device *slave_dev)
1833 /* close slave before restoring its mac address */ 1946 /* close slave before restoring its mac address */
1834 dev_close(slave_dev); 1947 dev_close(slave_dev);
1835 1948
1836 if (!bond->params.fail_over_mac) { 1949 if (bond->params.fail_over_mac != BOND_FOM_ACTIVE) {
1837 /* restore original ("permanent") mac address */ 1950 /* restore original ("permanent") mac address */
1838 memcpy(addr.sa_data, slave->perm_hwaddr, ETH_ALEN); 1951 memcpy(addr.sa_data, slave->perm_hwaddr, ETH_ALEN);
1839 addr.sa_family = slave_dev->type; 1952 addr.sa_family = slave_dev->type;
@@ -1946,9 +2059,9 @@ static int bond_release_all(struct net_device *bond_dev)
1946 } 2059 }
1947 2060
1948 /* flush master's mc_list from slave */ 2061 /* flush master's mc_list from slave */
1949 netif_tx_lock_bh(bond_dev); 2062 netif_addr_lock_bh(bond_dev);
1950 bond_mc_list_flush(bond_dev, slave_dev); 2063 bond_mc_list_flush(bond_dev, slave_dev);
1951 netif_tx_unlock_bh(bond_dev); 2064 netif_addr_unlock_bh(bond_dev);
1952 } 2065 }
1953 2066
1954 netdev_set_master(slave_dev, NULL); 2067 netdev_set_master(slave_dev, NULL);
@@ -2136,17 +2249,6 @@ static int __bond_mii_monitor(struct bonding *bond, int have_locks)
2136 * program could monitor the link itself if needed. 2249 * program could monitor the link itself if needed.
2137 */ 2250 */
2138 2251
2139 if (bond->send_grat_arp) {
2140 if (bond->curr_active_slave && test_bit(__LINK_STATE_LINKWATCH_PENDING,
2141 &bond->curr_active_slave->dev->state))
2142 dprintk("Needs to send gratuitous arp but not yet\n");
2143 else {
2144 dprintk("sending delayed gratuitous arp on on %s\n",
2145 bond->curr_active_slave->dev->name);
2146 bond_send_gratuitous_arp(bond);
2147 bond->send_grat_arp = 0;
2148 }
2149 }
2150 read_lock(&bond->curr_slave_lock); 2252 read_lock(&bond->curr_slave_lock);
2151 oldcurrent = bond->curr_active_slave; 2253 oldcurrent = bond->curr_active_slave;
2152 read_unlock(&bond->curr_slave_lock); 2254 read_unlock(&bond->curr_slave_lock);
@@ -2387,6 +2489,13 @@ void bond_mii_monitor(struct work_struct *work)
2387 read_unlock(&bond->lock); 2489 read_unlock(&bond->lock);
2388 return; 2490 return;
2389 } 2491 }
2492
2493 if (bond->send_grat_arp) {
2494 read_lock(&bond->curr_slave_lock);
2495 bond_send_gratuitous_arp(bond);
2496 read_unlock(&bond->curr_slave_lock);
2497 }
2498
2390 if (__bond_mii_monitor(bond, 0)) { 2499 if (__bond_mii_monitor(bond, 0)) {
2391 read_unlock(&bond->lock); 2500 read_unlock(&bond->lock);
2392 rtnl_lock(); 2501 rtnl_lock();
@@ -2397,7 +2506,7 @@ void bond_mii_monitor(struct work_struct *work)
2397 read_lock(&bond->lock); 2506 read_lock(&bond->lock);
2398 } 2507 }
2399 2508
2400 delay = ((bond->params.miimon * HZ) / 1000) ? : 1; 2509 delay = msecs_to_jiffies(bond->params.miimon);
2401 read_unlock(&bond->lock); 2510 read_unlock(&bond->lock);
2402 queue_delayed_work(bond->wq, &bond->mii_work, delay); 2511 queue_delayed_work(bond->wq, &bond->mii_work, delay);
2403} 2512}
@@ -2426,37 +2535,14 @@ out:
2426 return addr; 2535 return addr;
2427} 2536}
2428 2537
2429static int bond_has_ip(struct bonding *bond)
2430{
2431 struct vlan_entry *vlan, *vlan_next;
2432
2433 if (bond->master_ip)
2434 return 1;
2435
2436 if (list_empty(&bond->vlan_list))
2437 return 0;
2438
2439 list_for_each_entry_safe(vlan, vlan_next, &bond->vlan_list,
2440 vlan_list) {
2441 if (vlan->vlan_ip)
2442 return 1;
2443 }
2444
2445 return 0;
2446}
2447
2448static int bond_has_this_ip(struct bonding *bond, __be32 ip) 2538static int bond_has_this_ip(struct bonding *bond, __be32 ip)
2449{ 2539{
2450 struct vlan_entry *vlan, *vlan_next; 2540 struct vlan_entry *vlan;
2451 2541
2452 if (ip == bond->master_ip) 2542 if (ip == bond->master_ip)
2453 return 1; 2543 return 1;
2454 2544
2455 if (list_empty(&bond->vlan_list)) 2545 list_for_each_entry(vlan, &bond->vlan_list, vlan_list) {
2456 return 0;
2457
2458 list_for_each_entry_safe(vlan, vlan_next, &bond->vlan_list,
2459 vlan_list) {
2460 if (ip == vlan->vlan_ip) 2546 if (ip == vlan->vlan_ip)
2461 return 1; 2547 return 1;
2462 } 2548 }
@@ -2498,7 +2584,7 @@ static void bond_arp_send_all(struct bonding *bond, struct slave *slave)
2498{ 2584{
2499 int i, vlan_id, rv; 2585 int i, vlan_id, rv;
2500 __be32 *targets = bond->params.arp_targets; 2586 __be32 *targets = bond->params.arp_targets;
2501 struct vlan_entry *vlan, *vlan_next; 2587 struct vlan_entry *vlan;
2502 struct net_device *vlan_dev; 2588 struct net_device *vlan_dev;
2503 struct flowi fl; 2589 struct flowi fl;
2504 struct rtable *rt; 2590 struct rtable *rt;
@@ -2545,8 +2631,7 @@ static void bond_arp_send_all(struct bonding *bond, struct slave *slave)
2545 } 2631 }
2546 2632
2547 vlan_id = 0; 2633 vlan_id = 0;
2548 list_for_each_entry_safe(vlan, vlan_next, &bond->vlan_list, 2634 list_for_each_entry(vlan, &bond->vlan_list, vlan_list) {
2549 vlan_list) {
2550 vlan_dev = vlan_group_get_device(bond->vlgrp, vlan->vlan_id); 2635 vlan_dev = vlan_group_get_device(bond->vlgrp, vlan->vlan_id);
2551 if (vlan_dev == rt->u.dst.dev) { 2636 if (vlan_dev == rt->u.dst.dev) {
2552 vlan_id = vlan->vlan_id; 2637 vlan_id = vlan->vlan_id;
@@ -2576,6 +2661,8 @@ static void bond_arp_send_all(struct bonding *bond, struct slave *slave)
2576/* 2661/*
2577 * Kick out a gratuitous ARP for an IP on the bonding master plus one 2662 * Kick out a gratuitous ARP for an IP on the bonding master plus one
2578 * for each VLAN above us. 2663 * for each VLAN above us.
2664 *
2665 * Caller must hold curr_slave_lock for read or better
2579 */ 2666 */
2580static void bond_send_gratuitous_arp(struct bonding *bond) 2667static void bond_send_gratuitous_arp(struct bonding *bond)
2581{ 2668{
@@ -2585,9 +2672,13 @@ static void bond_send_gratuitous_arp(struct bonding *bond)
2585 2672
2586 dprintk("bond_send_grat_arp: bond %s slave %s\n", bond->dev->name, 2673 dprintk("bond_send_grat_arp: bond %s slave %s\n", bond->dev->name,
2587 slave ? slave->dev->name : "NULL"); 2674 slave ? slave->dev->name : "NULL");
2588 if (!slave) 2675
2676 if (!slave || !bond->send_grat_arp ||
2677 test_bit(__LINK_STATE_LINKWATCH_PENDING, &slave->dev->state))
2589 return; 2678 return;
2590 2679
2680 bond->send_grat_arp--;
2681
2591 if (bond->master_ip) { 2682 if (bond->master_ip) {
2592 bond_arp_send(slave->dev, ARPOP_REPLY, bond->master_ip, 2683 bond_arp_send(slave->dev, ARPOP_REPLY, bond->master_ip,
2593 bond->master_ip, 0); 2684 bond->master_ip, 0);
@@ -2707,7 +2798,7 @@ void bond_loadbalance_arp_mon(struct work_struct *work)
2707 2798
2708 read_lock(&bond->lock); 2799 read_lock(&bond->lock);
2709 2800
2710 delta_in_ticks = (bond->params.arp_interval * HZ) / 1000; 2801 delta_in_ticks = msecs_to_jiffies(bond->params.arp_interval);
2711 2802
2712 if (bond->kill_timers) { 2803 if (bond->kill_timers) {
2713 goto out; 2804 goto out;
@@ -2764,8 +2855,7 @@ void bond_loadbalance_arp_mon(struct work_struct *work)
2764 * if we don't know our ip yet 2855 * if we don't know our ip yet
2765 */ 2856 */
2766 if (time_after_eq(jiffies, slave->dev->trans_start + 2*delta_in_ticks) || 2857 if (time_after_eq(jiffies, slave->dev->trans_start + 2*delta_in_ticks) ||
2767 (time_after_eq(jiffies, slave->dev->last_rx + 2*delta_in_ticks) && 2858 (time_after_eq(jiffies, slave->dev->last_rx + 2*delta_in_ticks))) {
2768 bond_has_ip(bond))) {
2769 2859
2770 slave->link = BOND_LINK_DOWN; 2860 slave->link = BOND_LINK_DOWN;
2771 slave->state = BOND_STATE_BACKUP; 2861 slave->state = BOND_STATE_BACKUP;
@@ -2813,246 +2903,305 @@ out:
2813} 2903}
2814 2904
2815/* 2905/*
2816 * When using arp monitoring in active-backup mode, this function is 2906 * Called to inspect slaves for active-backup mode ARP monitor link state
2817 * called to determine if any backup slaves have went down or a new 2907 * changes. Sets new_link in slaves to specify what action should take
2818 * current slave needs to be found. 2908 * place for the slave. Returns 0 if no changes are found, >0 if changes
2819 * The backup slaves never generate traffic, they are considered up by merely 2909 * to link states must be committed.
2820 * receiving traffic. If the current slave goes down, each backup slave will 2910 *
2821 * be given the opportunity to tx/rx an arp before being taken down - this 2911 * Called with bond->lock held for read.
2822 * prevents all slaves from being taken down due to the current slave not
2823 * sending any traffic for the backups to receive. The arps are not necessarily
2824 * necessary, any tx and rx traffic will keep the current slave up. While any
2825 * rx traffic will keep the backup slaves up, the current slave is responsible
2826 * for generating traffic to keep them up regardless of any other traffic they
2827 * may have received.
2828 * see loadbalance_arp_monitor for arp monitoring in load balancing mode
2829 */ 2912 */
2830void bond_activebackup_arp_mon(struct work_struct *work) 2913static int bond_ab_arp_inspect(struct bonding *bond, int delta_in_ticks)
2831{ 2914{
2832 struct bonding *bond = container_of(work, struct bonding,
2833 arp_work.work);
2834 struct slave *slave; 2915 struct slave *slave;
2835 int delta_in_ticks; 2916 int i, commit = 0;
2836 int i;
2837 2917
2838 read_lock(&bond->lock); 2918 bond_for_each_slave(bond, slave, i) {
2919 slave->new_link = BOND_LINK_NOCHANGE;
2839 2920
2840 delta_in_ticks = (bond->params.arp_interval * HZ) / 1000; 2921 if (slave->link != BOND_LINK_UP) {
2922 if (time_before_eq(jiffies, slave_last_rx(bond, slave) +
2923 delta_in_ticks)) {
2924 slave->new_link = BOND_LINK_UP;
2925 commit++;
2926 }
2841 2927
2842 if (bond->kill_timers) { 2928 continue;
2843 goto out; 2929 }
2844 }
2845 2930
2846 if (bond->slave_cnt == 0) { 2931 /*
2847 goto re_arm; 2932 * Give slaves 2*delta after being enslaved or made
2933 * active. This avoids bouncing, as the last receive
2934 * times need a full ARP monitor cycle to be updated.
2935 */
2936 if (!time_after_eq(jiffies, slave->jiffies +
2937 2 * delta_in_ticks))
2938 continue;
2939
2940 /*
2941 * Backup slave is down if:
2942 * - No current_arp_slave AND
2943 * - more than 3*delta since last receive AND
2944 * - the bond has an IP address
2945 *
2946 * Note: a non-null current_arp_slave indicates
2947 * the curr_active_slave went down and we are
2948 * searching for a new one; under this condition
2949 * we only take the curr_active_slave down - this
2950 * gives each slave a chance to tx/rx traffic
2951 * before being taken out
2952 */
2953 if (slave->state == BOND_STATE_BACKUP &&
2954 !bond->current_arp_slave &&
2955 time_after(jiffies, slave_last_rx(bond, slave) +
2956 3 * delta_in_ticks)) {
2957 slave->new_link = BOND_LINK_DOWN;
2958 commit++;
2959 }
2960
2961 /*
2962 * Active slave is down if:
2963 * - more than 2*delta since transmitting OR
2964 * - (more than 2*delta since receive AND
2965 * the bond has an IP address)
2966 */
2967 if ((slave->state == BOND_STATE_ACTIVE) &&
2968 (time_after_eq(jiffies, slave->dev->trans_start +
2969 2 * delta_in_ticks) ||
2970 (time_after_eq(jiffies, slave_last_rx(bond, slave)
2971 + 2 * delta_in_ticks)))) {
2972 slave->new_link = BOND_LINK_DOWN;
2973 commit++;
2974 }
2848 } 2975 }
2849 2976
2850 /* determine if any slave has come up or any backup slave has 2977 read_lock(&bond->curr_slave_lock);
2851 * gone down 2978
2852 * TODO: what about up/down delay in arp mode? it wasn't here before 2979 /*
2853 * so it can wait 2980 * Trigger a commit if the primary option setting has changed.
2854 */ 2981 */
2855 bond_for_each_slave(bond, slave, i) { 2982 if (bond->primary_slave &&
2856 if (slave->link != BOND_LINK_UP) { 2983 (bond->primary_slave != bond->curr_active_slave) &&
2857 if (time_before_eq(jiffies, 2984 (bond->primary_slave->link == BOND_LINK_UP))
2858 slave_last_rx(bond, slave) + delta_in_ticks)) { 2985 commit++;
2859 2986
2860 slave->link = BOND_LINK_UP; 2987 read_unlock(&bond->curr_slave_lock);
2861 2988
2862 write_lock_bh(&bond->curr_slave_lock); 2989 return commit;
2990}
2863 2991
2864 if ((!bond->curr_active_slave) && 2992/*
2865 time_before_eq(jiffies, slave->dev->trans_start + delta_in_ticks)) { 2993 * Called to commit link state changes noted by inspection step of
2866 bond_change_active_slave(bond, slave); 2994 * active-backup mode ARP monitor.
2867 bond->current_arp_slave = NULL; 2995 *
2868 } else if (bond->curr_active_slave != slave) { 2996 * Called with RTNL and bond->lock for read.
2869 /* this slave has just come up but we 2997 */
2870 * already have a current slave; this 2998static void bond_ab_arp_commit(struct bonding *bond, int delta_in_ticks)
2871 * can also happen if bond_enslave adds 2999{
2872 * a new slave that is up while we are 3000 struct slave *slave;
2873 * searching for a new slave 3001 int i;
2874 */
2875 bond_set_slave_inactive_flags(slave);
2876 bond->current_arp_slave = NULL;
2877 }
2878 3002
2879 bond_set_carrier(bond); 3003 bond_for_each_slave(bond, slave, i) {
3004 switch (slave->new_link) {
3005 case BOND_LINK_NOCHANGE:
3006 continue;
2880 3007
2881 if (slave == bond->curr_active_slave) { 3008 case BOND_LINK_UP:
2882 printk(KERN_INFO DRV_NAME 3009 write_lock_bh(&bond->curr_slave_lock);
2883 ": %s: %s is up and now the "
2884 "active interface\n",
2885 bond->dev->name,
2886 slave->dev->name);
2887 netif_carrier_on(bond->dev);
2888 } else {
2889 printk(KERN_INFO DRV_NAME
2890 ": %s: backup interface %s is "
2891 "now up\n",
2892 bond->dev->name,
2893 slave->dev->name);
2894 }
2895 3010
2896 write_unlock_bh(&bond->curr_slave_lock); 3011 if (!bond->curr_active_slave &&
2897 } 3012 time_before_eq(jiffies, slave->dev->trans_start +
2898 } else { 3013 delta_in_ticks)) {
2899 read_lock(&bond->curr_slave_lock); 3014 slave->link = BOND_LINK_UP;
3015 bond_change_active_slave(bond, slave);
3016 bond->current_arp_slave = NULL;
2900 3017
2901 if ((slave != bond->curr_active_slave) && 3018 printk(KERN_INFO DRV_NAME
2902 (!bond->current_arp_slave) && 3019 ": %s: %s is up and now the "
2903 (time_after_eq(jiffies, slave_last_rx(bond, slave) + 3*delta_in_ticks) && 3020 "active interface\n",
2904 bond_has_ip(bond))) { 3021 bond->dev->name, slave->dev->name);
2905 /* a backup slave has gone down; three times 3022
2906 * the delta allows the current slave to be 3023 } else if (bond->curr_active_slave != slave) {
2907 * taken out before the backup slave. 3024 /* this slave has just come up but we
2908 * note: a non-null current_arp_slave indicates 3025 * already have a current slave; this can
2909 * the curr_active_slave went down and we are 3026 * also happen if bond_enslave adds a new
2910 * searching for a new one; under this 3027 * slave that is up while we are searching
2911 * condition we only take the curr_active_slave 3028 * for a new slave
2912 * down - this gives each slave a chance to
2913 * tx/rx traffic before being taken out
2914 */ 3029 */
3030 slave->link = BOND_LINK_UP;
3031 bond_set_slave_inactive_flags(slave);
3032 bond->current_arp_slave = NULL;
2915 3033
2916 read_unlock(&bond->curr_slave_lock); 3034 printk(KERN_INFO DRV_NAME
3035 ": %s: backup interface %s is now up\n",
3036 bond->dev->name, slave->dev->name);
3037 }
2917 3038
2918 slave->link = BOND_LINK_DOWN; 3039 write_unlock_bh(&bond->curr_slave_lock);
2919 3040
2920 if (slave->link_failure_count < UINT_MAX) { 3041 break;
2921 slave->link_failure_count++; 3042
2922 } 3043 case BOND_LINK_DOWN:
3044 if (slave->link_failure_count < UINT_MAX)
3045 slave->link_failure_count++;
3046
3047 slave->link = BOND_LINK_DOWN;
3048
3049 if (slave == bond->curr_active_slave) {
3050 printk(KERN_INFO DRV_NAME
3051 ": %s: link status down for active "
3052 "interface %s, disabling it\n",
3053 bond->dev->name, slave->dev->name);
2923 3054
2924 bond_set_slave_inactive_flags(slave); 3055 bond_set_slave_inactive_flags(slave);
2925 3056
3057 write_lock_bh(&bond->curr_slave_lock);
3058
3059 bond_select_active_slave(bond);
3060 if (bond->curr_active_slave)
3061 bond->curr_active_slave->jiffies =
3062 jiffies;
3063
3064 write_unlock_bh(&bond->curr_slave_lock);
3065
3066 bond->current_arp_slave = NULL;
3067
3068 } else if (slave->state == BOND_STATE_BACKUP) {
2926 printk(KERN_INFO DRV_NAME 3069 printk(KERN_INFO DRV_NAME
2927 ": %s: backup interface %s is now down\n", 3070 ": %s: backup interface %s is now down\n",
2928 bond->dev->name, 3071 bond->dev->name, slave->dev->name);
2929 slave->dev->name); 3072
2930 } else { 3073 bond_set_slave_inactive_flags(slave);
2931 read_unlock(&bond->curr_slave_lock);
2932 } 3074 }
3075 break;
3076
3077 default:
3078 printk(KERN_ERR DRV_NAME
3079 ": %s: impossible: new_link %d on slave %s\n",
3080 bond->dev->name, slave->new_link,
3081 slave->dev->name);
2933 } 3082 }
2934 } 3083 }
2935 3084
2936 read_lock(&bond->curr_slave_lock); 3085 /*
2937 slave = bond->curr_active_slave; 3086 * No race with changes to primary via sysfs, as we hold rtnl.
2938 read_unlock(&bond->curr_slave_lock); 3087 */
2939 3088 if (bond->primary_slave &&
2940 if (slave) { 3089 (bond->primary_slave != bond->curr_active_slave) &&
2941 /* if we have sent traffic in the past 2*arp_intervals but 3090 (bond->primary_slave->link == BOND_LINK_UP)) {
2942 * haven't xmit and rx traffic in that time interval, select 3091 write_lock_bh(&bond->curr_slave_lock);
2943 * a different slave. slave->jiffies is only updated when 3092 bond_change_active_slave(bond, bond->primary_slave);
2944 * a slave first becomes the curr_active_slave - not necessarily 3093 write_unlock_bh(&bond->curr_slave_lock);
2945 * after every arp; this ensures the slave has a full 2*delta 3094 }
2946 * before being taken out. if a primary is being used, check
2947 * if it is up and needs to take over as the curr_active_slave
2948 */
2949 if ((time_after_eq(jiffies, slave->dev->trans_start + 2*delta_in_ticks) ||
2950 (time_after_eq(jiffies, slave_last_rx(bond, slave) + 2*delta_in_ticks) &&
2951 bond_has_ip(bond))) &&
2952 time_after_eq(jiffies, slave->jiffies + 2*delta_in_ticks)) {
2953 3095
2954 slave->link = BOND_LINK_DOWN; 3096 bond_set_carrier(bond);
3097}
2955 3098
2956 if (slave->link_failure_count < UINT_MAX) { 3099/*
2957 slave->link_failure_count++; 3100 * Send ARP probes for active-backup mode ARP monitor.
2958 } 3101 *
3102 * Called with bond->lock held for read.
3103 */
3104static void bond_ab_arp_probe(struct bonding *bond)
3105{
3106 struct slave *slave;
3107 int i;
2959 3108
2960 printk(KERN_INFO DRV_NAME 3109 read_lock(&bond->curr_slave_lock);
2961 ": %s: link status down for active interface "
2962 "%s, disabling it\n",
2963 bond->dev->name,
2964 slave->dev->name);
2965 3110
2966 write_lock_bh(&bond->curr_slave_lock); 3111 if (bond->current_arp_slave && bond->curr_active_slave)
3112 printk("PROBE: c_arp %s && cas %s BAD\n",
3113 bond->current_arp_slave->dev->name,
3114 bond->curr_active_slave->dev->name);
2967 3115
2968 bond_select_active_slave(bond); 3116 if (bond->curr_active_slave) {
2969 slave = bond->curr_active_slave; 3117 bond_arp_send_all(bond, bond->curr_active_slave);
3118 read_unlock(&bond->curr_slave_lock);
3119 return;
3120 }
2970 3121
2971 write_unlock_bh(&bond->curr_slave_lock); 3122 read_unlock(&bond->curr_slave_lock);
2972 3123
2973 bond->current_arp_slave = slave; 3124 /* if we don't have a curr_active_slave, search for the next available
3125 * backup slave from the current_arp_slave and make it the candidate
3126 * for becoming the curr_active_slave
3127 */
2974 3128
2975 if (slave) { 3129 if (!bond->current_arp_slave) {
2976 slave->jiffies = jiffies; 3130 bond->current_arp_slave = bond->first_slave;
2977 } 3131 if (!bond->current_arp_slave)
2978 } else if ((bond->primary_slave) && 3132 return;
2979 (bond->primary_slave != slave) && 3133 }
2980 (bond->primary_slave->link == BOND_LINK_UP)) {
2981 /* at this point, slave is the curr_active_slave */
2982 printk(KERN_INFO DRV_NAME
2983 ": %s: changing from interface %s to primary "
2984 "interface %s\n",
2985 bond->dev->name,
2986 slave->dev->name,
2987 bond->primary_slave->dev->name);
2988 3134
2989 /* primary is up so switch to it */ 3135 bond_set_slave_inactive_flags(bond->current_arp_slave);
2990 write_lock_bh(&bond->curr_slave_lock);
2991 bond_change_active_slave(bond, bond->primary_slave);
2992 write_unlock_bh(&bond->curr_slave_lock);
2993 3136
2994 slave = bond->primary_slave; 3137 /* search for next candidate */
3138 bond_for_each_slave_from(bond, slave, i, bond->current_arp_slave->next) {
3139 if (IS_UP(slave->dev)) {
3140 slave->link = BOND_LINK_BACK;
3141 bond_set_slave_active_flags(slave);
3142 bond_arp_send_all(bond, slave);
2995 slave->jiffies = jiffies; 3143 slave->jiffies = jiffies;
2996 } else { 3144 bond->current_arp_slave = slave;
2997 bond->current_arp_slave = NULL; 3145 break;
2998 } 3146 }
2999 3147
3000 /* the current slave must tx an arp to ensure backup slaves 3148 /* if the link state is up at this point, we
3001 * rx traffic 3149 * mark it down - this can happen if we have
3150 * simultaneous link failures and
3151 * reselect_active_interface doesn't make this
3152 * one the current slave so it is still marked
3153 * up when it is actually down
3002 */ 3154 */
3003 if (slave && bond_has_ip(bond)) { 3155 if (slave->link == BOND_LINK_UP) {
3004 bond_arp_send_all(bond, slave); 3156 slave->link = BOND_LINK_DOWN;
3157 if (slave->link_failure_count < UINT_MAX)
3158 slave->link_failure_count++;
3159
3160 bond_set_slave_inactive_flags(slave);
3161
3162 printk(KERN_INFO DRV_NAME
3163 ": %s: backup interface %s is now down.\n",
3164 bond->dev->name, slave->dev->name);
3005 } 3165 }
3006 } 3166 }
3167}
3007 3168
3008 /* if we don't have a curr_active_slave, search for the next available 3169void bond_activebackup_arp_mon(struct work_struct *work)
3009 * backup slave from the current_arp_slave and make it the candidate 3170{
3010 * for becoming the curr_active_slave 3171 struct bonding *bond = container_of(work, struct bonding,
3011 */ 3172 arp_work.work);
3012 if (!slave) { 3173 int delta_in_ticks;
3013 if (!bond->current_arp_slave) {
3014 bond->current_arp_slave = bond->first_slave;
3015 }
3016 3174
3017 if (bond->current_arp_slave) { 3175 read_lock(&bond->lock);
3018 bond_set_slave_inactive_flags(bond->current_arp_slave);
3019 3176
3020 /* search for next candidate */ 3177 if (bond->kill_timers)
3021 bond_for_each_slave_from(bond, slave, i, bond->current_arp_slave->next) { 3178 goto out;
3022 if (IS_UP(slave->dev)) {
3023 slave->link = BOND_LINK_BACK;
3024 bond_set_slave_active_flags(slave);
3025 bond_arp_send_all(bond, slave);
3026 slave->jiffies = jiffies;
3027 bond->current_arp_slave = slave;
3028 break;
3029 }
3030 3179
3031 /* if the link state is up at this point, we 3180 delta_in_ticks = msecs_to_jiffies(bond->params.arp_interval);
3032 * mark it down - this can happen if we have
3033 * simultaneous link failures and
3034 * reselect_active_interface doesn't make this
3035 * one the current slave so it is still marked
3036 * up when it is actually down
3037 */
3038 if (slave->link == BOND_LINK_UP) {
3039 slave->link = BOND_LINK_DOWN;
3040 if (slave->link_failure_count < UINT_MAX) {
3041 slave->link_failure_count++;
3042 }
3043 3181
3044 bond_set_slave_inactive_flags(slave); 3182 if (bond->slave_cnt == 0)
3183 goto re_arm;
3045 3184
3046 printk(KERN_INFO DRV_NAME 3185 if (bond->send_grat_arp) {
3047 ": %s: backup interface %s is " 3186 read_lock(&bond->curr_slave_lock);
3048 "now down.\n", 3187 bond_send_gratuitous_arp(bond);
3049 bond->dev->name, 3188 read_unlock(&bond->curr_slave_lock);
3050 slave->dev->name);
3051 }
3052 }
3053 }
3054 } 3189 }
3055 3190
3191 if (bond_ab_arp_inspect(bond, delta_in_ticks)) {
3192 read_unlock(&bond->lock);
3193 rtnl_lock();
3194 read_lock(&bond->lock);
3195
3196 bond_ab_arp_commit(bond, delta_in_ticks);
3197
3198 read_unlock(&bond->lock);
3199 rtnl_unlock();
3200 read_lock(&bond->lock);
3201 }
3202
3203 bond_ab_arp_probe(bond);
3204
3056re_arm: 3205re_arm:
3057 if (bond->params.arp_interval) { 3206 if (bond->params.arp_interval) {
3058 queue_delayed_work(bond->wq, &bond->arp_work, delta_in_ticks); 3207 queue_delayed_work(bond->wq, &bond->arp_work, delta_in_ticks);
@@ -3128,7 +3277,8 @@ static void bond_info_show_master(struct seq_file *seq)
3128 3277
3129 if (bond->params.mode == BOND_MODE_ACTIVEBACKUP && 3278 if (bond->params.mode == BOND_MODE_ACTIVEBACKUP &&
3130 bond->params.fail_over_mac) 3279 bond->params.fail_over_mac)
3131 seq_printf(seq, " (fail_over_mac)"); 3280 seq_printf(seq, " (fail_over_mac %s)",
3281 fail_over_mac_tbl[bond->params.fail_over_mac].modename);
3132 3282
3133 seq_printf(seq, "\n"); 3283 seq_printf(seq, "\n");
3134 3284
@@ -3500,13 +3650,13 @@ static int bond_inetaddr_event(struct notifier_block *this, unsigned long event,
3500{ 3650{
3501 struct in_ifaddr *ifa = ptr; 3651 struct in_ifaddr *ifa = ptr;
3502 struct net_device *vlan_dev, *event_dev = ifa->ifa_dev->dev; 3652 struct net_device *vlan_dev, *event_dev = ifa->ifa_dev->dev;
3503 struct bonding *bond, *bond_next; 3653 struct bonding *bond;
3504 struct vlan_entry *vlan, *vlan_next; 3654 struct vlan_entry *vlan;
3505 3655
3506 if (dev_net(ifa->ifa_dev->dev) != &init_net) 3656 if (dev_net(ifa->ifa_dev->dev) != &init_net)
3507 return NOTIFY_DONE; 3657 return NOTIFY_DONE;
3508 3658
3509 list_for_each_entry_safe(bond, bond_next, &bond_dev_list, bond_list) { 3659 list_for_each_entry(bond, &bond_dev_list, bond_list) {
3510 if (bond->dev == event_dev) { 3660 if (bond->dev == event_dev) {
3511 switch (event) { 3661 switch (event) {
3512 case NETDEV_UP: 3662 case NETDEV_UP:
@@ -3520,11 +3670,7 @@ static int bond_inetaddr_event(struct notifier_block *this, unsigned long event,
3520 } 3670 }
3521 } 3671 }
3522 3672
3523 if (list_empty(&bond->vlan_list)) 3673 list_for_each_entry(vlan, &bond->vlan_list, vlan_list) {
3524 continue;
3525
3526 list_for_each_entry_safe(vlan, vlan_next, &bond->vlan_list,
3527 vlan_list) {
3528 vlan_dev = vlan_group_get_device(bond->vlgrp, vlan->vlan_id); 3674 vlan_dev = vlan_group_get_device(bond->vlgrp, vlan->vlan_id);
3529 if (vlan_dev == event_dev) { 3675 if (vlan_dev == event_dev) {
3530 switch (event) { 3676 switch (event) {
@@ -3716,6 +3862,7 @@ static int bond_close(struct net_device *bond_dev)
3716 3862
3717 write_lock_bh(&bond->lock); 3863 write_lock_bh(&bond->lock);
3718 3864
3865 bond->send_grat_arp = 0;
3719 3866
3720 /* signal timers not to re-arm */ 3867 /* signal timers not to re-arm */
3721 bond->kill_timers = 1; 3868 bond->kill_timers = 1;
@@ -3933,6 +4080,10 @@ static void bond_set_multicast_list(struct net_device *bond_dev)
3933 * Do promisc before checking multicast_mode 4080 * Do promisc before checking multicast_mode
3934 */ 4081 */
3935 if ((bond_dev->flags & IFF_PROMISC) && !(bond->flags & IFF_PROMISC)) { 4082 if ((bond_dev->flags & IFF_PROMISC) && !(bond->flags & IFF_PROMISC)) {
4083 /*
4084 * FIXME: Need to handle the error when one of the multi-slaves
4085 * encounters error.
4086 */
3936 bond_set_promiscuity(bond, 1); 4087 bond_set_promiscuity(bond, 1);
3937 } 4088 }
3938 4089
@@ -3942,6 +4093,10 @@ static void bond_set_multicast_list(struct net_device *bond_dev)
3942 4093
3943 /* set allmulti flag to slaves */ 4094 /* set allmulti flag to slaves */
3944 if ((bond_dev->flags & IFF_ALLMULTI) && !(bond->flags & IFF_ALLMULTI)) { 4095 if ((bond_dev->flags & IFF_ALLMULTI) && !(bond->flags & IFF_ALLMULTI)) {
4096 /*
4097 * FIXME: Need to handle the error when one of the multi-slaves
4098 * encounters error.
4099 */
3945 bond_set_allmulti(bond, 1); 4100 bond_set_allmulti(bond, 1);
3946 } 4101 }
3947 4102
@@ -4060,10 +4215,10 @@ static int bond_set_mac_address(struct net_device *bond_dev, void *addr)
4060 dprintk("bond=%p, name=%s\n", bond, (bond_dev ? bond_dev->name : "None")); 4215 dprintk("bond=%p, name=%s\n", bond, (bond_dev ? bond_dev->name : "None"));
4061 4216
4062 /* 4217 /*
4063 * If fail_over_mac is enabled, do nothing and return success. 4218 * If fail_over_mac is set to active, do nothing and return
4064 * Returning an error causes ifenslave to fail. 4219 * success. Returning an error causes ifenslave to fail.
4065 */ 4220 */
4066 if (bond->params.fail_over_mac) 4221 if (bond->params.fail_over_mac == BOND_FOM_ACTIVE)
4067 return 0; 4222 return 0;
4068 4223
4069 if (!is_valid_ether_addr(sa->sa_data)) { 4224 if (!is_valid_ether_addr(sa->sa_data)) {
@@ -4518,9 +4673,9 @@ static void bond_free_all(void)
4518 struct net_device *bond_dev = bond->dev; 4673 struct net_device *bond_dev = bond->dev;
4519 4674
4520 bond_work_cancel_all(bond); 4675 bond_work_cancel_all(bond);
4521 netif_tx_lock_bh(bond_dev); 4676 netif_addr_lock_bh(bond_dev);
4522 bond_mc_list_destroy(bond); 4677 bond_mc_list_destroy(bond);
4523 netif_tx_unlock_bh(bond_dev); 4678 netif_addr_unlock_bh(bond_dev);
4524 /* Release the bonded slaves */ 4679 /* Release the bonded slaves */
4525 bond_release_all(bond_dev); 4680 bond_release_all(bond_dev);
4526 bond_destroy(bond); 4681 bond_destroy(bond);
@@ -4568,7 +4723,7 @@ int bond_parse_parm(const char *buf, struct bond_parm_tbl *tbl)
4568 4723
4569static int bond_check_params(struct bond_params *params) 4724static int bond_check_params(struct bond_params *params)
4570{ 4725{
4571 int arp_validate_value; 4726 int arp_validate_value, fail_over_mac_value;
4572 4727
4573 /* 4728 /*
4574 * Convert string parameters. 4729 * Convert string parameters.
@@ -4618,11 +4773,11 @@ static int bond_check_params(struct bond_params *params)
4618 } 4773 }
4619 } 4774 }
4620 4775
4621 if (max_bonds < 1 || max_bonds > INT_MAX) { 4776 if (max_bonds < 0 || max_bonds > INT_MAX) {
4622 printk(KERN_WARNING DRV_NAME 4777 printk(KERN_WARNING DRV_NAME
4623 ": Warning: max_bonds (%d) not in range %d-%d, so it " 4778 ": Warning: max_bonds (%d) not in range %d-%d, so it "
4624 "was reset to BOND_DEFAULT_MAX_BONDS (%d)\n", 4779 "was reset to BOND_DEFAULT_MAX_BONDS (%d)\n",
4625 max_bonds, 1, INT_MAX, BOND_DEFAULT_MAX_BONDS); 4780 max_bonds, 0, INT_MAX, BOND_DEFAULT_MAX_BONDS);
4626 max_bonds = BOND_DEFAULT_MAX_BONDS; 4781 max_bonds = BOND_DEFAULT_MAX_BONDS;
4627 } 4782 }
4628 4783
@@ -4658,6 +4813,13 @@ static int bond_check_params(struct bond_params *params)
4658 use_carrier = 1; 4813 use_carrier = 1;
4659 } 4814 }
4660 4815
4816 if (num_grat_arp < 0 || num_grat_arp > 255) {
4817 printk(KERN_WARNING DRV_NAME
4818 ": Warning: num_grat_arp (%d) not in range 0-255 so it "
4819 "was reset to 1 \n", num_grat_arp);
4820 num_grat_arp = 1;
4821 }
4822
4661 /* reset values for 802.3ad */ 4823 /* reset values for 802.3ad */
4662 if (bond_mode == BOND_MODE_8023AD) { 4824 if (bond_mode == BOND_MODE_8023AD) {
4663 if (!miimon) { 4825 if (!miimon) {
@@ -4814,7 +4976,7 @@ static int bond_check_params(struct bond_params *params)
4814 4976
4815 printk("\n"); 4977 printk("\n");
4816 4978
4817 } else { 4979 } else if (max_bonds) {
4818 /* miimon and arp_interval not set, we need one so things 4980 /* miimon and arp_interval not set, we need one so things
4819 * work as expected, see bonding.txt for details 4981 * work as expected, see bonding.txt for details
4820 */ 4982 */
@@ -4836,15 +4998,29 @@ static int bond_check_params(struct bond_params *params)
4836 primary = NULL; 4998 primary = NULL;
4837 } 4999 }
4838 5000
4839 if (fail_over_mac && (bond_mode != BOND_MODE_ACTIVEBACKUP)) 5001 if (fail_over_mac) {
4840 printk(KERN_WARNING DRV_NAME 5002 fail_over_mac_value = bond_parse_parm(fail_over_mac,
4841 ": Warning: fail_over_mac only affects " 5003 fail_over_mac_tbl);
4842 "active-backup mode.\n"); 5004 if (fail_over_mac_value == -1) {
5005 printk(KERN_ERR DRV_NAME
5006 ": Error: invalid fail_over_mac \"%s\"\n",
5007 arp_validate == NULL ? "NULL" : arp_validate);
5008 return -EINVAL;
5009 }
5010
5011 if (bond_mode != BOND_MODE_ACTIVEBACKUP)
5012 printk(KERN_WARNING DRV_NAME
5013 ": Warning: fail_over_mac only affects "
5014 "active-backup mode.\n");
5015 } else {
5016 fail_over_mac_value = BOND_FOM_NONE;
5017 }
4843 5018
4844 /* fill params struct with the proper values */ 5019 /* fill params struct with the proper values */
4845 params->mode = bond_mode; 5020 params->mode = bond_mode;
4846 params->xmit_policy = xmit_hashtype; 5021 params->xmit_policy = xmit_hashtype;
4847 params->miimon = miimon; 5022 params->miimon = miimon;
5023 params->num_grat_arp = num_grat_arp;
4848 params->arp_interval = arp_interval; 5024 params->arp_interval = arp_interval;
4849 params->arp_validate = arp_validate_value; 5025 params->arp_validate = arp_validate_value;
4850 params->updelay = updelay; 5026 params->updelay = updelay;
@@ -4852,7 +5028,7 @@ static int bond_check_params(struct bond_params *params)
4852 params->use_carrier = use_carrier; 5028 params->use_carrier = use_carrier;
4853 params->lacp_fast = lacp_fast; 5029 params->lacp_fast = lacp_fast;
4854 params->primary[0] = 0; 5030 params->primary[0] = 0;
4855 params->fail_over_mac = fail_over_mac; 5031 params->fail_over_mac = fail_over_mac_value;
4856 5032
4857 if (primary) { 5033 if (primary) {
4858 strncpy(params->primary, primary, IFNAMSIZ); 5034 strncpy(params->primary, primary, IFNAMSIZ);
@@ -4866,15 +5042,28 @@ static int bond_check_params(struct bond_params *params)
4866 5042
4867static struct lock_class_key bonding_netdev_xmit_lock_key; 5043static struct lock_class_key bonding_netdev_xmit_lock_key;
4868 5044
5045static void bond_set_lockdep_class_one(struct net_device *dev,
5046 struct netdev_queue *txq,
5047 void *_unused)
5048{
5049 lockdep_set_class(&txq->_xmit_lock,
5050 &bonding_netdev_xmit_lock_key);
5051}
5052
5053static void bond_set_lockdep_class(struct net_device *dev)
5054{
5055 netdev_for_each_tx_queue(dev, bond_set_lockdep_class_one, NULL);
5056}
5057
4869/* Create a new bond based on the specified name and bonding parameters. 5058/* Create a new bond based on the specified name and bonding parameters.
4870 * If name is NULL, obtain a suitable "bond%d" name for us. 5059 * If name is NULL, obtain a suitable "bond%d" name for us.
4871 * Caller must NOT hold rtnl_lock; we need to release it here before we 5060 * Caller must NOT hold rtnl_lock; we need to release it here before we
4872 * set up our sysfs entries. 5061 * set up our sysfs entries.
4873 */ 5062 */
4874int bond_create(char *name, struct bond_params *params, struct bonding **newbond) 5063int bond_create(char *name, struct bond_params *params)
4875{ 5064{
4876 struct net_device *bond_dev; 5065 struct net_device *bond_dev;
4877 struct bonding *bond, *nxt; 5066 struct bonding *bond;
4878 int res; 5067 int res;
4879 5068
4880 rtnl_lock(); 5069 rtnl_lock();
@@ -4882,7 +5071,7 @@ int bond_create(char *name, struct bond_params *params, struct bonding **newbond
4882 5071
4883 /* Check to see if the bond already exists. */ 5072 /* Check to see if the bond already exists. */
4884 if (name) { 5073 if (name) {
4885 list_for_each_entry_safe(bond, nxt, &bond_dev_list, bond_list) 5074 list_for_each_entry(bond, &bond_dev_list, bond_list)
4886 if (strnicmp(bond->dev->name, name, IFNAMSIZ) == 0) { 5075 if (strnicmp(bond->dev->name, name, IFNAMSIZ) == 0) {
4887 printk(KERN_ERR DRV_NAME 5076 printk(KERN_ERR DRV_NAME
4888 ": cannot add bond %s; it already exists\n", 5077 ": cannot add bond %s; it already exists\n",
@@ -4923,10 +5112,7 @@ int bond_create(char *name, struct bond_params *params, struct bonding **newbond
4923 goto out_bond; 5112 goto out_bond;
4924 } 5113 }
4925 5114
4926 lockdep_set_class(&bond_dev->_xmit_lock, &bonding_netdev_xmit_lock_key); 5115 bond_set_lockdep_class(bond_dev);
4927
4928 if (newbond)
4929 *newbond = bond_dev->priv;
4930 5116
4931 netif_carrier_off(bond_dev); 5117 netif_carrier_off(bond_dev);
4932 5118
@@ -4957,7 +5143,7 @@ static int __init bonding_init(void)
4957{ 5143{
4958 int i; 5144 int i;
4959 int res; 5145 int res;
4960 struct bonding *bond, *nxt; 5146 struct bonding *bond;
4961 5147
4962 printk(KERN_INFO "%s", version); 5148 printk(KERN_INFO "%s", version);
4963 5149
@@ -4973,7 +5159,7 @@ static int __init bonding_init(void)
4973 init_rwsem(&bonding_rwsem); 5159 init_rwsem(&bonding_rwsem);
4974 5160
4975 for (i = 0; i < max_bonds; i++) { 5161 for (i = 0; i < max_bonds; i++) {
4976 res = bond_create(NULL, &bonding_defaults, NULL); 5162 res = bond_create(NULL, &bonding_defaults);
4977 if (res) 5163 if (res)
4978 goto err; 5164 goto err;
4979 } 5165 }
@@ -4987,7 +5173,7 @@ static int __init bonding_init(void)
4987 5173
4988 goto out; 5174 goto out;
4989err: 5175err:
4990 list_for_each_entry_safe(bond, nxt, &bond_dev_list, bond_list) { 5176 list_for_each_entry(bond, &bond_dev_list, bond_list) {
4991 bond_work_cancel_all(bond); 5177 bond_work_cancel_all(bond);
4992 destroy_workqueue(bond->wq); 5178 destroy_workqueue(bond->wq);
4993 } 5179 }
diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c
index 08f3d396bcd6..6caac0ffb2f2 100644
--- a/drivers/net/bonding/bond_sysfs.c
+++ b/drivers/net/bonding/bond_sysfs.c
@@ -50,9 +50,9 @@ extern struct bond_parm_tbl bond_mode_tbl[];
50extern struct bond_parm_tbl bond_lacp_tbl[]; 50extern struct bond_parm_tbl bond_lacp_tbl[];
51extern struct bond_parm_tbl xmit_hashtype_tbl[]; 51extern struct bond_parm_tbl xmit_hashtype_tbl[];
52extern struct bond_parm_tbl arp_validate_tbl[]; 52extern struct bond_parm_tbl arp_validate_tbl[];
53extern struct bond_parm_tbl fail_over_mac_tbl[];
53 54
54static int expected_refcount = -1; 55static int expected_refcount = -1;
55static struct class *netdev_class;
56/*--------------------------- Data Structures -----------------------------*/ 56/*--------------------------- Data Structures -----------------------------*/
57 57
58/* Bonding sysfs lock. Why can't we just use the subsystem lock? 58/* Bonding sysfs lock. Why can't we just use the subsystem lock?
@@ -111,7 +111,6 @@ static ssize_t bonding_store_bonds(struct class *cls, const char *buffer, size_t
111 char *ifname; 111 char *ifname;
112 int rv, res = count; 112 int rv, res = count;
113 struct bonding *bond; 113 struct bonding *bond;
114 struct bonding *nxt;
115 114
116 sscanf(buffer, "%16s", command); /* IFNAMSIZ*/ 115 sscanf(buffer, "%16s", command); /* IFNAMSIZ*/
117 ifname = command + 1; 116 ifname = command + 1;
@@ -122,7 +121,7 @@ static ssize_t bonding_store_bonds(struct class *cls, const char *buffer, size_t
122 if (command[0] == '+') { 121 if (command[0] == '+') {
123 printk(KERN_INFO DRV_NAME 122 printk(KERN_INFO DRV_NAME
124 ": %s is being created...\n", ifname); 123 ": %s is being created...\n", ifname);
125 rv = bond_create(ifname, &bonding_defaults, &bond); 124 rv = bond_create(ifname, &bonding_defaults);
126 if (rv) { 125 if (rv) {
127 printk(KERN_INFO DRV_NAME ": Bond creation failed.\n"); 126 printk(KERN_INFO DRV_NAME ": Bond creation failed.\n");
128 res = rv; 127 res = rv;
@@ -134,7 +133,7 @@ static ssize_t bonding_store_bonds(struct class *cls, const char *buffer, size_t
134 rtnl_lock(); 133 rtnl_lock();
135 down_write(&bonding_rwsem); 134 down_write(&bonding_rwsem);
136 135
137 list_for_each_entry_safe(bond, nxt, &bond_dev_list, bond_list) 136 list_for_each_entry(bond, &bond_dev_list, bond_list)
138 if (strnicmp(bond->dev->name, ifname, IFNAMSIZ) == 0) { 137 if (strnicmp(bond->dev->name, ifname, IFNAMSIZ) == 0) {
139 /* check the ref count on the bond's kobject. 138 /* check the ref count on the bond's kobject.
140 * If it's > expected, then there's a file open, 139 * If it's > expected, then there's a file open,
@@ -548,42 +547,37 @@ static ssize_t bonding_show_fail_over_mac(struct device *d, struct device_attrib
548{ 547{
549 struct bonding *bond = to_bond(d); 548 struct bonding *bond = to_bond(d);
550 549
551 return sprintf(buf, "%d\n", bond->params.fail_over_mac) + 1; 550 return sprintf(buf, "%s %d\n",
551 fail_over_mac_tbl[bond->params.fail_over_mac].modename,
552 bond->params.fail_over_mac);
552} 553}
553 554
554static ssize_t bonding_store_fail_over_mac(struct device *d, struct device_attribute *attr, const char *buf, size_t count) 555static ssize_t bonding_store_fail_over_mac(struct device *d, struct device_attribute *attr, const char *buf, size_t count)
555{ 556{
556 int new_value; 557 int new_value;
557 int ret = count;
558 struct bonding *bond = to_bond(d); 558 struct bonding *bond = to_bond(d);
559 559
560 if (bond->slave_cnt != 0) { 560 if (bond->slave_cnt != 0) {
561 printk(KERN_ERR DRV_NAME 561 printk(KERN_ERR DRV_NAME
562 ": %s: Can't alter fail_over_mac with slaves in bond.\n", 562 ": %s: Can't alter fail_over_mac with slaves in bond.\n",
563 bond->dev->name); 563 bond->dev->name);
564 ret = -EPERM; 564 return -EPERM;
565 goto out;
566 } 565 }
567 566
568 if (sscanf(buf, "%d", &new_value) != 1) { 567 new_value = bond_parse_parm(buf, fail_over_mac_tbl);
568 if (new_value < 0) {
569 printk(KERN_ERR DRV_NAME 569 printk(KERN_ERR DRV_NAME
570 ": %s: no fail_over_mac value specified.\n", 570 ": %s: Ignoring invalid fail_over_mac value %s.\n",
571 bond->dev->name); 571 bond->dev->name, buf);
572 ret = -EINVAL; 572 return -EINVAL;
573 goto out;
574 } 573 }
575 574
576 if ((new_value == 0) || (new_value == 1)) { 575 bond->params.fail_over_mac = new_value;
577 bond->params.fail_over_mac = new_value; 576 printk(KERN_INFO DRV_NAME ": %s: Setting fail_over_mac to %s (%d).\n",
578 printk(KERN_INFO DRV_NAME ": %s: Setting fail_over_mac to %d.\n", 577 bond->dev->name, fail_over_mac_tbl[new_value].modename,
579 bond->dev->name, new_value); 578 new_value);
580 } else { 579
581 printk(KERN_INFO DRV_NAME 580 return count;
582 ": %s: Ignoring invalid fail_over_mac value %d.\n",
583 bond->dev->name, new_value);
584 }
585out:
586 return ret;
587} 581}
588 582
589static DEVICE_ATTR(fail_over_mac, S_IRUGO | S_IWUSR, bonding_show_fail_over_mac, bonding_store_fail_over_mac); 583static DEVICE_ATTR(fail_over_mac, S_IRUGO | S_IWUSR, bonding_show_fail_over_mac, bonding_store_fail_over_mac);
@@ -952,6 +946,45 @@ out:
952static DEVICE_ATTR(lacp_rate, S_IRUGO | S_IWUSR, bonding_show_lacp, bonding_store_lacp); 946static DEVICE_ATTR(lacp_rate, S_IRUGO | S_IWUSR, bonding_show_lacp, bonding_store_lacp);
953 947
954/* 948/*
949 * Show and set the number of grat ARP to send after a failover event.
950 */
951static ssize_t bonding_show_n_grat_arp(struct device *d,
952 struct device_attribute *attr,
953 char *buf)
954{
955 struct bonding *bond = to_bond(d);
956
957 return sprintf(buf, "%d\n", bond->params.num_grat_arp);
958}
959
960static ssize_t bonding_store_n_grat_arp(struct device *d,
961 struct device_attribute *attr,
962 const char *buf, size_t count)
963{
964 int new_value, ret = count;
965 struct bonding *bond = to_bond(d);
966
967 if (sscanf(buf, "%d", &new_value) != 1) {
968 printk(KERN_ERR DRV_NAME
969 ": %s: no num_grat_arp value specified.\n",
970 bond->dev->name);
971 ret = -EINVAL;
972 goto out;
973 }
974 if (new_value < 0 || new_value > 255) {
975 printk(KERN_ERR DRV_NAME
976 ": %s: Invalid num_grat_arp value %d not in range 0-255; rejected.\n",
977 bond->dev->name, new_value);
978 ret = -EINVAL;
979 goto out;
980 } else {
981 bond->params.num_grat_arp = new_value;
982 }
983out:
984 return ret;
985}
986static DEVICE_ATTR(num_grat_arp, S_IRUGO | S_IWUSR, bonding_show_n_grat_arp, bonding_store_n_grat_arp);
987/*
955 * Show and set the MII monitor interval. There are two tricky bits 988 * Show and set the MII monitor interval. There are two tricky bits
956 * here. First, if MII monitoring is activated, then we must disable 989 * here. First, if MII monitoring is activated, then we must disable
957 * ARP monitoring. Second, if the timer isn't running, we must 990 * ARP monitoring. Second, if the timer isn't running, we must
@@ -1388,6 +1421,7 @@ static struct attribute *per_bond_attrs[] = {
1388 &dev_attr_updelay.attr, 1421 &dev_attr_updelay.attr,
1389 &dev_attr_lacp_rate.attr, 1422 &dev_attr_lacp_rate.attr,
1390 &dev_attr_xmit_hash_policy.attr, 1423 &dev_attr_xmit_hash_policy.attr,
1424 &dev_attr_num_grat_arp.attr,
1391 &dev_attr_miimon.attr, 1425 &dev_attr_miimon.attr,
1392 &dev_attr_primary.attr, 1426 &dev_attr_primary.attr,
1393 &dev_attr_use_carrier.attr, 1427 &dev_attr_use_carrier.attr,
@@ -1412,19 +1446,9 @@ static struct attribute_group bonding_group = {
1412 */ 1446 */
1413int bond_create_sysfs(void) 1447int bond_create_sysfs(void)
1414{ 1448{
1415 int ret = 0; 1449 int ret;
1416 struct bonding *firstbond;
1417
1418 /* get the netdev class pointer */
1419 firstbond = container_of(bond_dev_list.next, struct bonding, bond_list);
1420 if (!firstbond)
1421 return -ENODEV;
1422 1450
1423 netdev_class = firstbond->dev->dev.class; 1451 ret = netdev_class_create_file(&class_attr_bonding_masters);
1424 if (!netdev_class)
1425 return -ENODEV;
1426
1427 ret = class_create_file(netdev_class, &class_attr_bonding_masters);
1428 /* 1452 /*
1429 * Permit multiple loads of the module by ignoring failures to 1453 * Permit multiple loads of the module by ignoring failures to
1430 * create the bonding_masters sysfs file. Bonding devices 1454 * create the bonding_masters sysfs file. Bonding devices
@@ -1443,10 +1467,6 @@ int bond_create_sysfs(void)
1443 printk(KERN_ERR 1467 printk(KERN_ERR
1444 "network device named %s already exists in sysfs", 1468 "network device named %s already exists in sysfs",
1445 class_attr_bonding_masters.attr.name); 1469 class_attr_bonding_masters.attr.name);
1446 else {
1447 netdev_class = NULL;
1448 return 0;
1449 }
1450 } 1470 }
1451 1471
1452 return ret; 1472 return ret;
@@ -1458,8 +1478,7 @@ int bond_create_sysfs(void)
1458 */ 1478 */
1459void bond_destroy_sysfs(void) 1479void bond_destroy_sysfs(void)
1460{ 1480{
1461 if (netdev_class) 1481 netdev_class_remove_file(&class_attr_bonding_masters);
1462 class_remove_file(netdev_class, &class_attr_bonding_masters);
1463} 1482}
1464 1483
1465/* 1484/*
diff --git a/drivers/net/bonding/bonding.h b/drivers/net/bonding/bonding.h
index a3c74e20aa53..fb730ec0396f 100644
--- a/drivers/net/bonding/bonding.h
+++ b/drivers/net/bonding/bonding.h
@@ -22,8 +22,8 @@
22#include "bond_3ad.h" 22#include "bond_3ad.h"
23#include "bond_alb.h" 23#include "bond_alb.h"
24 24
25#define DRV_VERSION "3.2.5" 25#define DRV_VERSION "3.3.0"
26#define DRV_RELDATE "March 21, 2008" 26#define DRV_RELDATE "June 10, 2008"
27#define DRV_NAME "bonding" 27#define DRV_NAME "bonding"
28#define DRV_DESCRIPTION "Ethernet Channel Bonding Driver" 28#define DRV_DESCRIPTION "Ethernet Channel Bonding Driver"
29 29
@@ -125,6 +125,7 @@ struct bond_params {
125 int mode; 125 int mode;
126 int xmit_policy; 126 int xmit_policy;
127 int miimon; 127 int miimon;
128 int num_grat_arp;
128 int arp_interval; 129 int arp_interval;
129 int arp_validate; 130 int arp_validate;
130 int use_carrier; 131 int use_carrier;
@@ -157,6 +158,7 @@ struct slave {
157 unsigned long jiffies; 158 unsigned long jiffies;
158 unsigned long last_arp_rx; 159 unsigned long last_arp_rx;
159 s8 link; /* one of BOND_LINK_XXXX */ 160 s8 link; /* one of BOND_LINK_XXXX */
161 s8 new_link;
160 s8 state; /* one of BOND_STATE_XXXX */ 162 s8 state; /* one of BOND_STATE_XXXX */
161 u32 original_flags; 163 u32 original_flags;
162 u32 original_mtu; 164 u32 original_mtu;
@@ -169,6 +171,11 @@ struct slave {
169}; 171};
170 172
171/* 173/*
174 * Link pseudo-state only used internally by monitors
175 */
176#define BOND_LINK_NOCHANGE -1
177
178/*
172 * Here are the locking policies for the two bonding locks: 179 * Here are the locking policies for the two bonding locks:
173 * 180 *
174 * 1) Get bond->lock when reading/writing slave list. 181 * 1) Get bond->lock when reading/writing slave list.
@@ -241,6 +248,10 @@ static inline struct bonding *bond_get_bond_by_slave(struct slave *slave)
241 return (struct bonding *)slave->dev->master->priv; 248 return (struct bonding *)slave->dev->master->priv;
242} 249}
243 250
251#define BOND_FOM_NONE 0
252#define BOND_FOM_ACTIVE 1
253#define BOND_FOM_FOLLOW 2
254
244#define BOND_ARP_VALIDATE_NONE 0 255#define BOND_ARP_VALIDATE_NONE 0
245#define BOND_ARP_VALIDATE_ACTIVE (1 << BOND_STATE_ACTIVE) 256#define BOND_ARP_VALIDATE_ACTIVE (1 << BOND_STATE_ACTIVE)
246#define BOND_ARP_VALIDATE_BACKUP (1 << BOND_STATE_BACKUP) 257#define BOND_ARP_VALIDATE_BACKUP (1 << BOND_STATE_BACKUP)
@@ -301,7 +312,7 @@ static inline void bond_unset_master_alb_flags(struct bonding *bond)
301 312
302struct vlan_entry *bond_next_vlan(struct bonding *bond, struct vlan_entry *curr); 313struct vlan_entry *bond_next_vlan(struct bonding *bond, struct vlan_entry *curr);
303int bond_dev_queue_xmit(struct bonding *bond, struct sk_buff *skb, struct net_device *slave_dev); 314int bond_dev_queue_xmit(struct bonding *bond, struct sk_buff *skb, struct net_device *slave_dev);
304int bond_create(char *name, struct bond_params *params, struct bonding **newbond); 315int bond_create(char *name, struct bond_params *params);
305void bond_destroy(struct bonding *bond); 316void bond_destroy(struct bonding *bond);
306int bond_release_and_destroy(struct net_device *bond_dev, struct net_device *slave_dev); 317int bond_release_and_destroy(struct net_device *bond_dev, struct net_device *slave_dev);
307int bond_create_sysfs(void); 318int bond_create_sysfs(void);
diff --git a/drivers/net/chelsio/cxgb2.c b/drivers/net/chelsio/cxgb2.c
index a509337eab2d..638c9a27a7a6 100644
--- a/drivers/net/chelsio/cxgb2.c
+++ b/drivers/net/chelsio/cxgb2.c
@@ -1153,9 +1153,7 @@ static int __devinit init_one(struct pci_dev *pdev,
1153#ifdef CONFIG_NET_POLL_CONTROLLER 1153#ifdef CONFIG_NET_POLL_CONTROLLER
1154 netdev->poll_controller = t1_netpoll; 1154 netdev->poll_controller = t1_netpoll;
1155#endif 1155#endif
1156#ifdef CONFIG_CHELSIO_T1_NAPI
1157 netif_napi_add(netdev, &adapter->napi, t1_poll, 64); 1156 netif_napi_add(netdev, &adapter->napi, t1_poll, 64);
1158#endif
1159 1157
1160 SET_ETHTOOL_OPS(netdev, &t1_ethtool_ops); 1158 SET_ETHTOOL_OPS(netdev, &t1_ethtool_ops);
1161 } 1159 }
diff --git a/drivers/net/chelsio/sge.c b/drivers/net/chelsio/sge.c
index 8a7efd38e95b..d6c7d2aa761b 100644
--- a/drivers/net/chelsio/sge.c
+++ b/drivers/net/chelsio/sge.c
@@ -1396,20 +1396,10 @@ static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len)
1396 1396
1397 if (unlikely(adapter->vlan_grp && p->vlan_valid)) { 1397 if (unlikely(adapter->vlan_grp && p->vlan_valid)) {
1398 st->vlan_xtract++; 1398 st->vlan_xtract++;
1399#ifdef CONFIG_CHELSIO_T1_NAPI 1399 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp,
1400 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, 1400 ntohs(p->vlan));
1401 ntohs(p->vlan)); 1401 } else
1402#else
1403 vlan_hwaccel_rx(skb, adapter->vlan_grp,
1404 ntohs(p->vlan));
1405#endif
1406 } else {
1407#ifdef CONFIG_CHELSIO_T1_NAPI
1408 netif_receive_skb(skb); 1402 netif_receive_skb(skb);
1409#else
1410 netif_rx(skb);
1411#endif
1412 }
1413} 1403}
1414 1404
1415/* 1405/*
@@ -1568,7 +1558,6 @@ static inline int responses_pending(const struct adapter *adapter)
1568 return (e->GenerationBit == Q->genbit); 1558 return (e->GenerationBit == Q->genbit);
1569} 1559}
1570 1560
1571#ifdef CONFIG_CHELSIO_T1_NAPI
1572/* 1561/*
1573 * A simpler version of process_responses() that handles only pure (i.e., 1562 * A simpler version of process_responses() that handles only pure (i.e.,
1574 * non data-carrying) responses. Such respones are too light-weight to justify 1563 * non data-carrying) responses. Such respones are too light-weight to justify
@@ -1636,9 +1625,6 @@ int t1_poll(struct napi_struct *napi, int budget)
1636 return work_done; 1625 return work_done;
1637} 1626}
1638 1627
1639/*
1640 * NAPI version of the main interrupt handler.
1641 */
1642irqreturn_t t1_interrupt(int irq, void *data) 1628irqreturn_t t1_interrupt(int irq, void *data)
1643{ 1629{
1644 struct adapter *adapter = data; 1630 struct adapter *adapter = data;
@@ -1656,7 +1642,8 @@ irqreturn_t t1_interrupt(int irq, void *data)
1656 else { 1642 else {
1657 /* no data, no NAPI needed */ 1643 /* no data, no NAPI needed */
1658 writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING); 1644 writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING);
1659 napi_enable(&adapter->napi); /* undo schedule_prep */ 1645 /* undo schedule_prep */
1646 napi_enable(&adapter->napi);
1660 } 1647 }
1661 } 1648 }
1662 return IRQ_HANDLED; 1649 return IRQ_HANDLED;
@@ -1672,53 +1659,6 @@ irqreturn_t t1_interrupt(int irq, void *data)
1672 return IRQ_RETVAL(handled != 0); 1659 return IRQ_RETVAL(handled != 0);
1673} 1660}
1674 1661
1675#else
1676/*
1677 * Main interrupt handler, optimized assuming that we took a 'DATA'
1678 * interrupt.
1679 *
1680 * 1. Clear the interrupt
1681 * 2. Loop while we find valid descriptors and process them; accumulate
1682 * information that can be processed after the loop
1683 * 3. Tell the SGE at which index we stopped processing descriptors
1684 * 4. Bookkeeping; free TX buffers, ring doorbell if there are any
1685 * outstanding TX buffers waiting, replenish RX buffers, potentially
1686 * reenable upper layers if they were turned off due to lack of TX
1687 * resources which are available again.
1688 * 5. If we took an interrupt, but no valid respQ descriptors was found we
1689 * let the slow_intr_handler run and do error handling.
1690 */
1691irqreturn_t t1_interrupt(int irq, void *cookie)
1692{
1693 int work_done;
1694 struct adapter *adapter = cookie;
1695 struct respQ *Q = &adapter->sge->respQ;
1696
1697 spin_lock(&adapter->async_lock);
1698
1699 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE);
1700
1701 if (likely(responses_pending(adapter)))
1702 work_done = process_responses(adapter, -1);
1703 else
1704 work_done = t1_slow_intr_handler(adapter);
1705
1706 /*
1707 * The unconditional clearing of the PL_CAUSE above may have raced
1708 * with DMA completion and the corresponding generation of a response
1709 * to cause us to miss the resulting data interrupt. The next write
1710 * is also unconditional to recover the missed interrupt and render
1711 * this race harmless.
1712 */
1713 writel(Q->cidx, adapter->regs + A_SG_SLEEPING);
1714
1715 if (!work_done)
1716 adapter->sge->stats.unhandled_irqs++;
1717 spin_unlock(&adapter->async_lock);
1718 return IRQ_RETVAL(work_done != 0);
1719}
1720#endif
1721
1722/* 1662/*
1723 * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it. 1663 * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it.
1724 * 1664 *
diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c
index 7f3f62e1b113..fbd4280c102c 100644
--- a/drivers/net/cpmac.c
+++ b/drivers/net/cpmac.c
@@ -544,7 +544,7 @@ fatal_error:
544 544
545 spin_unlock(&priv->rx_lock); 545 spin_unlock(&priv->rx_lock);
546 netif_rx_complete(priv->dev, napi); 546 netif_rx_complete(priv->dev, napi);
547 netif_stop_queue(priv->dev); 547 netif_tx_stop_all_queues(priv->dev);
548 napi_disable(&priv->napi); 548 napi_disable(&priv->napi);
549 549
550 atomic_inc(&priv->reset_pending); 550 atomic_inc(&priv->reset_pending);
@@ -569,11 +569,7 @@ static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
569 569
570 len = max(skb->len, ETH_ZLEN); 570 len = max(skb->len, ETH_ZLEN);
571 queue = skb_get_queue_mapping(skb); 571 queue = skb_get_queue_mapping(skb);
572#ifdef CONFIG_NETDEVICES_MULTIQUEUE
573 netif_stop_subqueue(dev, queue); 572 netif_stop_subqueue(dev, queue);
574#else
575 netif_stop_queue(dev);
576#endif
577 573
578 desc = &priv->desc_ring[queue]; 574 desc = &priv->desc_ring[queue];
579 if (unlikely(desc->dataflags & CPMAC_OWN)) { 575 if (unlikely(desc->dataflags & CPMAC_OWN)) {
@@ -626,24 +622,14 @@ static void cpmac_end_xmit(struct net_device *dev, int queue)
626 622
627 dev_kfree_skb_irq(desc->skb); 623 dev_kfree_skb_irq(desc->skb);
628 desc->skb = NULL; 624 desc->skb = NULL;
629#ifdef CONFIG_NETDEVICES_MULTIQUEUE
630 if (netif_subqueue_stopped(dev, queue)) 625 if (netif_subqueue_stopped(dev, queue))
631 netif_wake_subqueue(dev, queue); 626 netif_wake_subqueue(dev, queue);
632#else
633 if (netif_queue_stopped(dev))
634 netif_wake_queue(dev);
635#endif
636 } else { 627 } else {
637 if (netif_msg_tx_err(priv) && net_ratelimit()) 628 if (netif_msg_tx_err(priv) && net_ratelimit())
638 printk(KERN_WARNING 629 printk(KERN_WARNING
639 "%s: end_xmit: spurious interrupt\n", dev->name); 630 "%s: end_xmit: spurious interrupt\n", dev->name);
640#ifdef CONFIG_NETDEVICES_MULTIQUEUE
641 if (netif_subqueue_stopped(dev, queue)) 631 if (netif_subqueue_stopped(dev, queue))
642 netif_wake_subqueue(dev, queue); 632 netif_wake_subqueue(dev, queue);
643#else
644 if (netif_queue_stopped(dev))
645 netif_wake_queue(dev);
646#endif
647 } 633 }
648} 634}
649 635
@@ -764,9 +750,7 @@ static void cpmac_hw_error(struct work_struct *work)
764 barrier(); 750 barrier();
765 atomic_dec(&priv->reset_pending); 751 atomic_dec(&priv->reset_pending);
766 752
767 for (i = 0; i < CPMAC_QUEUES; i++) 753 netif_tx_wake_all_queues(priv->dev);
768 netif_wake_subqueue(priv->dev, i);
769 netif_wake_queue(priv->dev);
770 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3); 754 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
771} 755}
772 756
@@ -795,7 +779,7 @@ static void cpmac_check_status(struct net_device *dev)
795 dev->name, tx_code, tx_channel, macstatus); 779 dev->name, tx_code, tx_channel, macstatus);
796 } 780 }
797 781
798 netif_stop_queue(dev); 782 netif_tx_stop_all_queues(dev);
799 cpmac_hw_stop(dev); 783 cpmac_hw_stop(dev);
800 if (schedule_work(&priv->reset_work)) 784 if (schedule_work(&priv->reset_work))
801 atomic_inc(&priv->reset_pending); 785 atomic_inc(&priv->reset_pending);
@@ -856,9 +840,7 @@ static void cpmac_tx_timeout(struct net_device *dev)
856 barrier(); 840 barrier();
857 atomic_dec(&priv->reset_pending); 841 atomic_dec(&priv->reset_pending);
858 842
859 netif_wake_queue(priv->dev); 843 netif_tx_wake_all_queues(priv->dev);
860 for (i = 0; i < CPMAC_QUEUES; i++)
861 netif_wake_subqueue(dev, i);
862} 844}
863 845
864static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 846static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
@@ -949,7 +931,7 @@ static void cpmac_adjust_link(struct net_device *dev)
949 931
950 spin_lock(&priv->lock); 932 spin_lock(&priv->lock);
951 if (priv->phy->link) { 933 if (priv->phy->link) {
952 netif_start_queue(dev); 934 netif_tx_start_all_queues(dev);
953 if (priv->phy->duplex != priv->oldduplex) { 935 if (priv->phy->duplex != priv->oldduplex) {
954 new_state = 1; 936 new_state = 1;
955 priv->oldduplex = priv->phy->duplex; 937 priv->oldduplex = priv->phy->duplex;
@@ -963,10 +945,10 @@ static void cpmac_adjust_link(struct net_device *dev)
963 if (!priv->oldlink) { 945 if (!priv->oldlink) {
964 new_state = 1; 946 new_state = 1;
965 priv->oldlink = 1; 947 priv->oldlink = 1;
966 netif_schedule(dev); 948 netif_tx_schedule_all(dev);
967 } 949 }
968 } else if (priv->oldlink) { 950 } else if (priv->oldlink) {
969 netif_stop_queue(dev); 951 netif_tx_stop_all_queues(dev);
970 new_state = 1; 952 new_state = 1;
971 priv->oldlink = 0; 953 priv->oldlink = 0;
972 priv->oldspeed = 0; 954 priv->oldspeed = 0;
@@ -1086,7 +1068,7 @@ static int cpmac_stop(struct net_device *dev)
1086 struct cpmac_priv *priv = netdev_priv(dev); 1068 struct cpmac_priv *priv = netdev_priv(dev);
1087 struct resource *mem; 1069 struct resource *mem;
1088 1070
1089 netif_stop_queue(dev); 1071 netif_tx_stop_all_queues(dev);
1090 1072
1091 cancel_work_sync(&priv->reset_work); 1073 cancel_work_sync(&priv->reset_work);
1092 napi_disable(&priv->napi); 1074 napi_disable(&priv->napi);
@@ -1179,7 +1161,6 @@ static int __devinit cpmac_probe(struct platform_device *pdev)
1179 dev->set_multicast_list = cpmac_set_multicast_list; 1161 dev->set_multicast_list = cpmac_set_multicast_list;
1180 dev->tx_timeout = cpmac_tx_timeout; 1162 dev->tx_timeout = cpmac_tx_timeout;
1181 dev->ethtool_ops = &cpmac_ethtool_ops; 1163 dev->ethtool_ops = &cpmac_ethtool_ops;
1182 dev->features |= NETIF_F_MULTI_QUEUE;
1183 1164
1184 netif_napi_add(dev, &priv->napi, cpmac_poll, 64); 1165 netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1185 1166
diff --git a/drivers/net/cxgb3/adapter.h b/drivers/net/cxgb3/adapter.h
index acebe431d068..271140433b09 100644
--- a/drivers/net/cxgb3/adapter.h
+++ b/drivers/net/cxgb3/adapter.h
@@ -42,6 +42,7 @@
42#include <linux/cache.h> 42#include <linux/cache.h>
43#include <linux/mutex.h> 43#include <linux/mutex.h>
44#include <linux/bitops.h> 44#include <linux/bitops.h>
45#include <linux/inet_lro.h>
45#include "t3cdev.h" 46#include "t3cdev.h"
46#include <asm/io.h> 47#include <asm/io.h>
47 48
@@ -92,6 +93,7 @@ struct sge_fl { /* SGE per free-buffer list state */
92 unsigned int gen; /* free list generation */ 93 unsigned int gen; /* free list generation */
93 struct fl_pg_chunk pg_chunk;/* page chunk cache */ 94 struct fl_pg_chunk pg_chunk;/* page chunk cache */
94 unsigned int use_pages; /* whether FL uses pages or sk_buffs */ 95 unsigned int use_pages; /* whether FL uses pages or sk_buffs */
96 unsigned int order; /* order of page allocations */
95 struct rx_desc *desc; /* address of HW Rx descriptor ring */ 97 struct rx_desc *desc; /* address of HW Rx descriptor ring */
96 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 98 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
97 dma_addr_t phys_addr; /* physical address of HW ring start */ 99 dma_addr_t phys_addr; /* physical address of HW ring start */
@@ -116,12 +118,15 @@ struct sge_rspq { /* state for an SGE response queue */
116 unsigned int polling; /* is the queue serviced through NAPI? */ 118 unsigned int polling; /* is the queue serviced through NAPI? */
117 unsigned int holdoff_tmr; /* interrupt holdoff timer in 100ns */ 119 unsigned int holdoff_tmr; /* interrupt holdoff timer in 100ns */
118 unsigned int next_holdoff; /* holdoff time for next interrupt */ 120 unsigned int next_holdoff; /* holdoff time for next interrupt */
121 unsigned int rx_recycle_buf; /* whether recycling occurred
122 within current sop-eop */
119 struct rsp_desc *desc; /* address of HW response ring */ 123 struct rsp_desc *desc; /* address of HW response ring */
120 dma_addr_t phys_addr; /* physical address of the ring */ 124 dma_addr_t phys_addr; /* physical address of the ring */
121 unsigned int cntxt_id; /* SGE context id for the response q */ 125 unsigned int cntxt_id; /* SGE context id for the response q */
122 spinlock_t lock; /* guards response processing */ 126 spinlock_t lock; /* guards response processing */
123 struct sk_buff *rx_head; /* offload packet receive queue head */ 127 struct sk_buff *rx_head; /* offload packet receive queue head */
124 struct sk_buff *rx_tail; /* offload packet receive queue tail */ 128 struct sk_buff *rx_tail; /* offload packet receive queue tail */
129 struct sk_buff *pg_skb; /* used to build frag list in napi handler */
125 130
126 unsigned long offload_pkts; 131 unsigned long offload_pkts;
127 unsigned long offload_bundles; 132 unsigned long offload_bundles;
@@ -169,16 +174,29 @@ enum { /* per port SGE statistics */
169 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */ 174 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
170 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */ 175 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
171 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */ 176 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
177 SGE_PSTAT_LRO_AGGR, /* # of page chunks added to LRO sessions */
178 SGE_PSTAT_LRO_FLUSHED, /* # of flushed LRO sessions */
179 SGE_PSTAT_LRO_NO_DESC, /* # of overflown LRO sessions */
172 180
173 SGE_PSTAT_MAX /* must be last */ 181 SGE_PSTAT_MAX /* must be last */
174}; 182};
175 183
184#define T3_MAX_LRO_SES 8
185#define T3_MAX_LRO_MAX_PKTS 64
186
176struct sge_qset { /* an SGE queue set */ 187struct sge_qset { /* an SGE queue set */
177 struct adapter *adap; 188 struct adapter *adap;
178 struct napi_struct napi; 189 struct napi_struct napi;
179 struct sge_rspq rspq; 190 struct sge_rspq rspq;
180 struct sge_fl fl[SGE_RXQ_PER_SET]; 191 struct sge_fl fl[SGE_RXQ_PER_SET];
181 struct sge_txq txq[SGE_TXQ_PER_SET]; 192 struct sge_txq txq[SGE_TXQ_PER_SET];
193 struct net_lro_mgr lro_mgr;
194 struct net_lro_desc lro_desc[T3_MAX_LRO_SES];
195 struct skb_frag_struct *lro_frag_tbl;
196 int lro_nfrags;
197 int lro_enabled;
198 int lro_frag_len;
199 void *lro_va;
182 struct net_device *netdev; 200 struct net_device *netdev;
183 unsigned long txq_stopped; /* which Tx queues are stopped */ 201 unsigned long txq_stopped; /* which Tx queues are stopped */
184 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ 202 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
diff --git a/drivers/net/cxgb3/common.h b/drivers/net/cxgb3/common.h
index 8e8ebd788537..9ecf8a6dc97f 100644
--- a/drivers/net/cxgb3/common.h
+++ b/drivers/net/cxgb3/common.h
@@ -351,6 +351,7 @@ struct tp_params {
351 351
352struct qset_params { /* SGE queue set parameters */ 352struct qset_params { /* SGE queue set parameters */
353 unsigned int polling; /* polling/interrupt service for rspq */ 353 unsigned int polling; /* polling/interrupt service for rspq */
354 unsigned int lro; /* large receive offload */
354 unsigned int coalesce_usecs; /* irq coalescing timer */ 355 unsigned int coalesce_usecs; /* irq coalescing timer */
355 unsigned int rspq_size; /* # of entries in response queue */ 356 unsigned int rspq_size; /* # of entries in response queue */
356 unsigned int fl_size; /* # of entries in regular free list */ 357 unsigned int fl_size; /* # of entries in regular free list */
diff --git a/drivers/net/cxgb3/cxgb3_ctl_defs.h b/drivers/net/cxgb3/cxgb3_ctl_defs.h
index ed0ecd9679cb..6ad92405d9a0 100644
--- a/drivers/net/cxgb3/cxgb3_ctl_defs.h
+++ b/drivers/net/cxgb3/cxgb3_ctl_defs.h
@@ -111,10 +111,7 @@ struct ulp_iscsi_info {
111 unsigned int llimit; 111 unsigned int llimit;
112 unsigned int ulimit; 112 unsigned int ulimit;
113 unsigned int tagmask; 113 unsigned int tagmask;
114 unsigned int pgsz3; 114 u8 pgsz_factor[4];
115 unsigned int pgsz2;
116 unsigned int pgsz1;
117 unsigned int pgsz0;
118 unsigned int max_rxsz; 115 unsigned int max_rxsz;
119 unsigned int max_txsz; 116 unsigned int max_txsz;
120 struct pci_dev *pdev; 117 struct pci_dev *pdev;
diff --git a/drivers/net/cxgb3/cxgb3_ioctl.h b/drivers/net/cxgb3/cxgb3_ioctl.h
index 0a82fcddf2d8..68200a14065e 100644
--- a/drivers/net/cxgb3/cxgb3_ioctl.h
+++ b/drivers/net/cxgb3/cxgb3_ioctl.h
@@ -90,6 +90,7 @@ struct ch_qset_params {
90 int32_t fl_size[2]; 90 int32_t fl_size[2];
91 int32_t intr_lat; 91 int32_t intr_lat;
92 int32_t polling; 92 int32_t polling;
93 int32_t lro;
93 int32_t cong_thres; 94 int32_t cong_thres;
94}; 95};
95 96
diff --git a/drivers/net/cxgb3/cxgb3_main.c b/drivers/net/cxgb3/cxgb3_main.c
index 3a3127216791..5447f3e60f07 100644
--- a/drivers/net/cxgb3/cxgb3_main.c
+++ b/drivers/net/cxgb3/cxgb3_main.c
@@ -1212,6 +1212,9 @@ static char stats_strings[][ETH_GSTRING_LEN] = {
1212 "VLANinsertions ", 1212 "VLANinsertions ",
1213 "TxCsumOffload ", 1213 "TxCsumOffload ",
1214 "RxCsumGood ", 1214 "RxCsumGood ",
1215 "LroAggregated ",
1216 "LroFlushed ",
1217 "LroNoDesc ",
1215 "RxDrops ", 1218 "RxDrops ",
1216 1219
1217 "CheckTXEnToggled ", 1220 "CheckTXEnToggled ",
@@ -1340,6 +1343,9 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1340 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS); 1343 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS);
1341 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM); 1344 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1342 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD); 1345 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
1346 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_LRO_AGGR);
1347 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_LRO_FLUSHED);
1348 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_LRO_NO_DESC);
1343 *data++ = s->rx_cong_drops; 1349 *data++ = s->rx_cong_drops;
1344 1350
1345 *data++ = s->num_toggled; 1351 *data++ = s->num_toggled;
@@ -1558,6 +1564,13 @@ static int set_rx_csum(struct net_device *dev, u32 data)
1558 struct port_info *p = netdev_priv(dev); 1564 struct port_info *p = netdev_priv(dev);
1559 1565
1560 p->rx_csum_offload = data; 1566 p->rx_csum_offload = data;
1567 if (!data) {
1568 struct adapter *adap = p->adapter;
1569 int i;
1570
1571 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++)
1572 adap->sge.qs[i].lro_enabled = 0;
1573 }
1561 return 0; 1574 return 0;
1562} 1575}
1563 1576
@@ -1830,6 +1843,11 @@ static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
1830 } 1843 }
1831 } 1844 }
1832 } 1845 }
1846 if (t.lro >= 0) {
1847 struct sge_qset *qs = &adapter->sge.qs[t.qset_idx];
1848 q->lro = t.lro;
1849 qs->lro_enabled = t.lro;
1850 }
1833 break; 1851 break;
1834 } 1852 }
1835 case CHELSIO_GET_QSET_PARAMS:{ 1853 case CHELSIO_GET_QSET_PARAMS:{
@@ -1849,6 +1867,7 @@ static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
1849 t.fl_size[0] = q->fl_size; 1867 t.fl_size[0] = q->fl_size;
1850 t.fl_size[1] = q->jumbo_size; 1868 t.fl_size[1] = q->jumbo_size;
1851 t.polling = q->polling; 1869 t.polling = q->polling;
1870 t.lro = q->lro;
1852 t.intr_lat = q->coalesce_usecs; 1871 t.intr_lat = q->coalesce_usecs;
1853 t.cong_thres = q->cong_thres; 1872 t.cong_thres = q->cong_thres;
1854 1873
diff --git a/drivers/net/cxgb3/cxgb3_offload.c b/drivers/net/cxgb3/cxgb3_offload.c
index cf2696873796..c5b3de1bb456 100644
--- a/drivers/net/cxgb3/cxgb3_offload.c
+++ b/drivers/net/cxgb3/cxgb3_offload.c
@@ -207,6 +207,17 @@ static int cxgb_ulp_iscsi_ctl(struct adapter *adapter, unsigned int req,
207 break; 207 break;
208 case ULP_ISCSI_SET_PARAMS: 208 case ULP_ISCSI_SET_PARAMS:
209 t3_write_reg(adapter, A_ULPRX_ISCSI_TAGMASK, uiip->tagmask); 209 t3_write_reg(adapter, A_ULPRX_ISCSI_TAGMASK, uiip->tagmask);
210 /* set MaxRxData and MaxCoalesceSize to 16224 */
211 t3_write_reg(adapter, A_TP_PARA_REG2, 0x3f603f60);
212 /* program the ddp page sizes */
213 {
214 int i;
215 unsigned int val = 0;
216 for (i = 0; i < 4; i++)
217 val |= (uiip->pgsz_factor[i] & 0xF) << (8 * i);
218 if (val)
219 t3_write_reg(adapter, A_ULPRX_ISCSI_PSZ, val);
220 }
210 break; 221 break;
211 default: 222 default:
212 ret = -EOPNOTSUPP; 223 ret = -EOPNOTSUPP;
@@ -1255,6 +1266,25 @@ static inline void unregister_tdev(struct t3cdev *tdev)
1255 mutex_unlock(&cxgb3_db_lock); 1266 mutex_unlock(&cxgb3_db_lock);
1256} 1267}
1257 1268
1269static inline int adap2type(struct adapter *adapter)
1270{
1271 int type = 0;
1272
1273 switch (adapter->params.rev) {
1274 case T3_REV_A:
1275 type = T3A;
1276 break;
1277 case T3_REV_B:
1278 case T3_REV_B2:
1279 type = T3B;
1280 break;
1281 case T3_REV_C:
1282 type = T3C;
1283 break;
1284 }
1285 return type;
1286}
1287
1258void __devinit cxgb3_adapter_ofld(struct adapter *adapter) 1288void __devinit cxgb3_adapter_ofld(struct adapter *adapter)
1259{ 1289{
1260 struct t3cdev *tdev = &adapter->tdev; 1290 struct t3cdev *tdev = &adapter->tdev;
@@ -1264,7 +1294,7 @@ void __devinit cxgb3_adapter_ofld(struct adapter *adapter)
1264 cxgb3_set_dummy_ops(tdev); 1294 cxgb3_set_dummy_ops(tdev);
1265 tdev->send = t3_offload_tx; 1295 tdev->send = t3_offload_tx;
1266 tdev->ctl = cxgb_offload_ctl; 1296 tdev->ctl = cxgb_offload_ctl;
1267 tdev->type = adapter->params.rev == 0 ? T3A : T3B; 1297 tdev->type = adap2type(adapter);
1268 1298
1269 register_tdev(tdev); 1299 register_tdev(tdev);
1270} 1300}
diff --git a/drivers/net/cxgb3/l2t.c b/drivers/net/cxgb3/l2t.c
index f510140885ae..825e510bd9ed 100644
--- a/drivers/net/cxgb3/l2t.c
+++ b/drivers/net/cxgb3/l2t.c
@@ -337,7 +337,7 @@ struct l2t_entry *t3_l2t_get(struct t3cdev *cdev, struct neighbour *neigh,
337 atomic_set(&e->refcnt, 1); 337 atomic_set(&e->refcnt, 1);
338 neigh_replace(e, neigh); 338 neigh_replace(e, neigh);
339 if (neigh->dev->priv_flags & IFF_802_1Q_VLAN) 339 if (neigh->dev->priv_flags & IFF_802_1Q_VLAN)
340 e->vlan = vlan_dev_info(neigh->dev)->vlan_id; 340 e->vlan = vlan_dev_vlan_id(neigh->dev);
341 else 341 else
342 e->vlan = VLAN_NONE; 342 e->vlan = VLAN_NONE;
343 spin_unlock(&e->lock); 343 spin_unlock(&e->lock);
diff --git a/drivers/net/cxgb3/regs.h b/drivers/net/cxgb3/regs.h
index 567178879345..4bda27c551c9 100644
--- a/drivers/net/cxgb3/regs.h
+++ b/drivers/net/cxgb3/regs.h
@@ -1517,16 +1517,18 @@
1517 1517
1518#define A_ULPRX_ISCSI_TAGMASK 0x514 1518#define A_ULPRX_ISCSI_TAGMASK 0x514
1519 1519
1520#define S_HPZ0 0 1520#define A_ULPRX_ISCSI_PSZ 0x518
1521#define M_HPZ0 0xf
1522#define V_HPZ0(x) ((x) << S_HPZ0)
1523#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
1524 1521
1525#define A_ULPRX_TDDP_LLIMIT 0x51c 1522#define A_ULPRX_TDDP_LLIMIT 0x51c
1526 1523
1527#define A_ULPRX_TDDP_ULIMIT 0x520 1524#define A_ULPRX_TDDP_ULIMIT 0x520
1528#define A_ULPRX_TDDP_PSZ 0x528 1525#define A_ULPRX_TDDP_PSZ 0x528
1529 1526
1527#define S_HPZ0 0
1528#define M_HPZ0 0xf
1529#define V_HPZ0(x) ((x) << S_HPZ0)
1530#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
1531
1530#define A_ULPRX_STAG_LLIMIT 0x52c 1532#define A_ULPRX_STAG_LLIMIT 0x52c
1531 1533
1532#define A_ULPRX_STAG_ULIMIT 0x530 1534#define A_ULPRX_STAG_ULIMIT 0x530
diff --git a/drivers/net/cxgb3/sge.c b/drivers/net/cxgb3/sge.c
index 796eb305cdc3..a96331c875e6 100644
--- a/drivers/net/cxgb3/sge.c
+++ b/drivers/net/cxgb3/sge.c
@@ -55,6 +55,9 @@
55 * directly. 55 * directly.
56 */ 56 */
57#define FL0_PG_CHUNK_SIZE 2048 57#define FL0_PG_CHUNK_SIZE 2048
58#define FL0_PG_ORDER 0
59#define FL1_PG_CHUNK_SIZE (PAGE_SIZE > 8192 ? 16384 : 8192)
60#define FL1_PG_ORDER (PAGE_SIZE > 8192 ? 0 : 1)
58 61
59#define SGE_RX_DROP_THRES 16 62#define SGE_RX_DROP_THRES 16
60 63
@@ -359,7 +362,7 @@ static void free_rx_bufs(struct pci_dev *pdev, struct sge_fl *q)
359 } 362 }
360 363
361 if (q->pg_chunk.page) { 364 if (q->pg_chunk.page) {
362 __free_page(q->pg_chunk.page); 365 __free_pages(q->pg_chunk.page, q->order);
363 q->pg_chunk.page = NULL; 366 q->pg_chunk.page = NULL;
364 } 367 }
365} 368}
@@ -376,13 +379,16 @@ static void free_rx_bufs(struct pci_dev *pdev, struct sge_fl *q)
376 * Add a buffer of the given length to the supplied HW and SW Rx 379 * Add a buffer of the given length to the supplied HW and SW Rx
377 * descriptors. 380 * descriptors.
378 */ 381 */
379static inline void add_one_rx_buf(void *va, unsigned int len, 382static inline int add_one_rx_buf(void *va, unsigned int len,
380 struct rx_desc *d, struct rx_sw_desc *sd, 383 struct rx_desc *d, struct rx_sw_desc *sd,
381 unsigned int gen, struct pci_dev *pdev) 384 unsigned int gen, struct pci_dev *pdev)
382{ 385{
383 dma_addr_t mapping; 386 dma_addr_t mapping;
384 387
385 mapping = pci_map_single(pdev, va, len, PCI_DMA_FROMDEVICE); 388 mapping = pci_map_single(pdev, va, len, PCI_DMA_FROMDEVICE);
389 if (unlikely(pci_dma_mapping_error(mapping)))
390 return -ENOMEM;
391
386 pci_unmap_addr_set(sd, dma_addr, mapping); 392 pci_unmap_addr_set(sd, dma_addr, mapping);
387 393
388 d->addr_lo = cpu_to_be32(mapping); 394 d->addr_lo = cpu_to_be32(mapping);
@@ -390,12 +396,14 @@ static inline void add_one_rx_buf(void *va, unsigned int len,
390 wmb(); 396 wmb();
391 d->len_gen = cpu_to_be32(V_FLD_GEN1(gen)); 397 d->len_gen = cpu_to_be32(V_FLD_GEN1(gen));
392 d->gen2 = cpu_to_be32(V_FLD_GEN2(gen)); 398 d->gen2 = cpu_to_be32(V_FLD_GEN2(gen));
399 return 0;
393} 400}
394 401
395static int alloc_pg_chunk(struct sge_fl *q, struct rx_sw_desc *sd, gfp_t gfp) 402static int alloc_pg_chunk(struct sge_fl *q, struct rx_sw_desc *sd, gfp_t gfp,
403 unsigned int order)
396{ 404{
397 if (!q->pg_chunk.page) { 405 if (!q->pg_chunk.page) {
398 q->pg_chunk.page = alloc_page(gfp); 406 q->pg_chunk.page = alloc_pages(gfp, order);
399 if (unlikely(!q->pg_chunk.page)) 407 if (unlikely(!q->pg_chunk.page))
400 return -ENOMEM; 408 return -ENOMEM;
401 q->pg_chunk.va = page_address(q->pg_chunk.page); 409 q->pg_chunk.va = page_address(q->pg_chunk.page);
@@ -404,7 +412,7 @@ static int alloc_pg_chunk(struct sge_fl *q, struct rx_sw_desc *sd, gfp_t gfp)
404 sd->pg_chunk = q->pg_chunk; 412 sd->pg_chunk = q->pg_chunk;
405 413
406 q->pg_chunk.offset += q->buf_size; 414 q->pg_chunk.offset += q->buf_size;
407 if (q->pg_chunk.offset == PAGE_SIZE) 415 if (q->pg_chunk.offset == (PAGE_SIZE << order))
408 q->pg_chunk.page = NULL; 416 q->pg_chunk.page = NULL;
409 else { 417 else {
410 q->pg_chunk.va += q->buf_size; 418 q->pg_chunk.va += q->buf_size;
@@ -424,15 +432,18 @@ static int alloc_pg_chunk(struct sge_fl *q, struct rx_sw_desc *sd, gfp_t gfp)
424 * allocated with the supplied gfp flags. The caller must assure that 432 * allocated with the supplied gfp flags. The caller must assure that
425 * @n does not exceed the queue's capacity. 433 * @n does not exceed the queue's capacity.
426 */ 434 */
427static void refill_fl(struct adapter *adap, struct sge_fl *q, int n, gfp_t gfp) 435static int refill_fl(struct adapter *adap, struct sge_fl *q, int n, gfp_t gfp)
428{ 436{
429 void *buf_start; 437 void *buf_start;
430 struct rx_sw_desc *sd = &q->sdesc[q->pidx]; 438 struct rx_sw_desc *sd = &q->sdesc[q->pidx];
431 struct rx_desc *d = &q->desc[q->pidx]; 439 struct rx_desc *d = &q->desc[q->pidx];
440 unsigned int count = 0;
432 441
433 while (n--) { 442 while (n--) {
443 int err;
444
434 if (q->use_pages) { 445 if (q->use_pages) {
435 if (unlikely(alloc_pg_chunk(q, sd, gfp))) { 446 if (unlikely(alloc_pg_chunk(q, sd, gfp, q->order))) {
436nomem: q->alloc_failed++; 447nomem: q->alloc_failed++;
437 break; 448 break;
438 } 449 }
@@ -447,8 +458,16 @@ nomem: q->alloc_failed++;
447 buf_start = skb->data; 458 buf_start = skb->data;
448 } 459 }
449 460
450 add_one_rx_buf(buf_start, q->buf_size, d, sd, q->gen, 461 err = add_one_rx_buf(buf_start, q->buf_size, d, sd, q->gen,
451 adap->pdev); 462 adap->pdev);
463 if (unlikely(err)) {
464 if (!q->use_pages) {
465 kfree_skb(sd->skb);
466 sd->skb = NULL;
467 }
468 break;
469 }
470
452 d++; 471 d++;
453 sd++; 472 sd++;
454 if (++q->pidx == q->size) { 473 if (++q->pidx == q->size) {
@@ -458,14 +477,19 @@ nomem: q->alloc_failed++;
458 d = q->desc; 477 d = q->desc;
459 } 478 }
460 q->credits++; 479 q->credits++;
480 count++;
461 } 481 }
462 wmb(); 482 wmb();
463 t3_write_reg(adap, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id)); 483 if (likely(count))
484 t3_write_reg(adap, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id));
485
486 return count;
464} 487}
465 488
466static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl) 489static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
467{ 490{
468 refill_fl(adap, fl, min(16U, fl->size - fl->credits), GFP_ATOMIC); 491 refill_fl(adap, fl, min(16U, fl->size - fl->credits),
492 GFP_ATOMIC | __GFP_COMP);
469} 493}
470 494
471/** 495/**
@@ -560,6 +584,8 @@ static void t3_reset_qset(struct sge_qset *q)
560 memset(q->txq, 0, sizeof(struct sge_txq) * SGE_TXQ_PER_SET); 584 memset(q->txq, 0, sizeof(struct sge_txq) * SGE_TXQ_PER_SET);
561 q->txq_stopped = 0; 585 q->txq_stopped = 0;
562 memset(&q->tx_reclaim_timer, 0, sizeof(q->tx_reclaim_timer)); 586 memset(&q->tx_reclaim_timer, 0, sizeof(q->tx_reclaim_timer));
587 kfree(q->lro_frag_tbl);
588 q->lro_nfrags = q->lro_frag_len = 0;
563} 589}
564 590
565 591
@@ -740,19 +766,22 @@ use_orig_buf:
740 * that are page chunks rather than sk_buffs. 766 * that are page chunks rather than sk_buffs.
741 */ 767 */
742static struct sk_buff *get_packet_pg(struct adapter *adap, struct sge_fl *fl, 768static struct sk_buff *get_packet_pg(struct adapter *adap, struct sge_fl *fl,
743 unsigned int len, unsigned int drop_thres) 769 struct sge_rspq *q, unsigned int len,
770 unsigned int drop_thres)
744{ 771{
745 struct sk_buff *skb = NULL; 772 struct sk_buff *newskb, *skb;
746 struct rx_sw_desc *sd = &fl->sdesc[fl->cidx]; 773 struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
747 774
748 if (len <= SGE_RX_COPY_THRES) { 775 newskb = skb = q->pg_skb;
749 skb = alloc_skb(len, GFP_ATOMIC); 776
750 if (likely(skb != NULL)) { 777 if (!skb && (len <= SGE_RX_COPY_THRES)) {
751 __skb_put(skb, len); 778 newskb = alloc_skb(len, GFP_ATOMIC);
779 if (likely(newskb != NULL)) {
780 __skb_put(newskb, len);
752 pci_dma_sync_single_for_cpu(adap->pdev, 781 pci_dma_sync_single_for_cpu(adap->pdev,
753 pci_unmap_addr(sd, dma_addr), len, 782 pci_unmap_addr(sd, dma_addr), len,
754 PCI_DMA_FROMDEVICE); 783 PCI_DMA_FROMDEVICE);
755 memcpy(skb->data, sd->pg_chunk.va, len); 784 memcpy(newskb->data, sd->pg_chunk.va, len);
756 pci_dma_sync_single_for_device(adap->pdev, 785 pci_dma_sync_single_for_device(adap->pdev,
757 pci_unmap_addr(sd, dma_addr), len, 786 pci_unmap_addr(sd, dma_addr), len,
758 PCI_DMA_FROMDEVICE); 787 PCI_DMA_FROMDEVICE);
@@ -761,14 +790,16 @@ static struct sk_buff *get_packet_pg(struct adapter *adap, struct sge_fl *fl,
761recycle: 790recycle:
762 fl->credits--; 791 fl->credits--;
763 recycle_rx_buf(adap, fl, fl->cidx); 792 recycle_rx_buf(adap, fl, fl->cidx);
764 return skb; 793 q->rx_recycle_buf++;
794 return newskb;
765 } 795 }
766 796
767 if (unlikely(fl->credits <= drop_thres)) 797 if (unlikely(q->rx_recycle_buf || (!skb && fl->credits <= drop_thres)))
768 goto recycle; 798 goto recycle;
769 799
770 skb = alloc_skb(SGE_RX_PULL_LEN, GFP_ATOMIC); 800 if (!skb)
771 if (unlikely(!skb)) { 801 newskb = alloc_skb(SGE_RX_PULL_LEN, GFP_ATOMIC);
802 if (unlikely(!newskb)) {
772 if (!drop_thres) 803 if (!drop_thres)
773 return NULL; 804 return NULL;
774 goto recycle; 805 goto recycle;
@@ -776,21 +807,29 @@ recycle:
776 807
777 pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr), 808 pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr),
778 fl->buf_size, PCI_DMA_FROMDEVICE); 809 fl->buf_size, PCI_DMA_FROMDEVICE);
779 __skb_put(skb, SGE_RX_PULL_LEN); 810 if (!skb) {
780 memcpy(skb->data, sd->pg_chunk.va, SGE_RX_PULL_LEN); 811 __skb_put(newskb, SGE_RX_PULL_LEN);
781 skb_fill_page_desc(skb, 0, sd->pg_chunk.page, 812 memcpy(newskb->data, sd->pg_chunk.va, SGE_RX_PULL_LEN);
782 sd->pg_chunk.offset + SGE_RX_PULL_LEN, 813 skb_fill_page_desc(newskb, 0, sd->pg_chunk.page,
783 len - SGE_RX_PULL_LEN); 814 sd->pg_chunk.offset + SGE_RX_PULL_LEN,
784 skb->len = len; 815 len - SGE_RX_PULL_LEN);
785 skb->data_len = len - SGE_RX_PULL_LEN; 816 newskb->len = len;
786 skb->truesize += skb->data_len; 817 newskb->data_len = len - SGE_RX_PULL_LEN;
818 } else {
819 skb_fill_page_desc(newskb, skb_shinfo(newskb)->nr_frags,
820 sd->pg_chunk.page,
821 sd->pg_chunk.offset, len);
822 newskb->len += len;
823 newskb->data_len += len;
824 }
825 newskb->truesize += newskb->data_len;
787 826
788 fl->credits--; 827 fl->credits--;
789 /* 828 /*
790 * We do not refill FLs here, we let the caller do it to overlap a 829 * We do not refill FLs here, we let the caller do it to overlap a
791 * prefetch. 830 * prefetch.
792 */ 831 */
793 return skb; 832 return newskb;
794} 833}
795 834
796/** 835/**
@@ -1831,9 +1870,10 @@ static void restart_tx(struct sge_qset *qs)
1831 * if it was immediate data in a response. 1870 * if it was immediate data in a response.
1832 */ 1871 */
1833static void rx_eth(struct adapter *adap, struct sge_rspq *rq, 1872static void rx_eth(struct adapter *adap, struct sge_rspq *rq,
1834 struct sk_buff *skb, int pad) 1873 struct sk_buff *skb, int pad, int lro)
1835{ 1874{
1836 struct cpl_rx_pkt *p = (struct cpl_rx_pkt *)(skb->data + pad); 1875 struct cpl_rx_pkt *p = (struct cpl_rx_pkt *)(skb->data + pad);
1876 struct sge_qset *qs = rspq_to_qset(rq);
1837 struct port_info *pi; 1877 struct port_info *pi;
1838 1878
1839 skb_pull(skb, sizeof(*p) + pad); 1879 skb_pull(skb, sizeof(*p) + pad);
@@ -1850,18 +1890,202 @@ static void rx_eth(struct adapter *adap, struct sge_rspq *rq,
1850 if (unlikely(p->vlan_valid)) { 1890 if (unlikely(p->vlan_valid)) {
1851 struct vlan_group *grp = pi->vlan_grp; 1891 struct vlan_group *grp = pi->vlan_grp;
1852 1892
1853 rspq_to_qset(rq)->port_stats[SGE_PSTAT_VLANEX]++; 1893 qs->port_stats[SGE_PSTAT_VLANEX]++;
1854 if (likely(grp)) 1894 if (likely(grp))
1855 __vlan_hwaccel_rx(skb, grp, ntohs(p->vlan), 1895 if (lro)
1856 rq->polling); 1896 lro_vlan_hwaccel_receive_skb(&qs->lro_mgr, skb,
1897 grp,
1898 ntohs(p->vlan),
1899 p);
1900 else
1901 __vlan_hwaccel_rx(skb, grp, ntohs(p->vlan),
1902 rq->polling);
1857 else 1903 else
1858 dev_kfree_skb_any(skb); 1904 dev_kfree_skb_any(skb);
1859 } else if (rq->polling) 1905 } else if (rq->polling) {
1860 netif_receive_skb(skb); 1906 if (lro)
1861 else 1907 lro_receive_skb(&qs->lro_mgr, skb, p);
1908 else
1909 netif_receive_skb(skb);
1910 } else
1862 netif_rx(skb); 1911 netif_rx(skb);
1863} 1912}
1864 1913
1914static inline int is_eth_tcp(u32 rss)
1915{
1916 return G_HASHTYPE(ntohl(rss)) == RSS_HASH_4_TUPLE;
1917}
1918
1919/**
1920 * lro_frame_ok - check if an ingress packet is eligible for LRO
1921 * @p: the CPL header of the packet
1922 *
1923 * Returns true if a received packet is eligible for LRO.
1924 * The following conditions must be true:
1925 * - packet is TCP/IP Ethernet II (checked elsewhere)
1926 * - not an IP fragment
1927 * - no IP options
1928 * - TCP/IP checksums are correct
1929 * - the packet is for this host
1930 */
1931static inline int lro_frame_ok(const struct cpl_rx_pkt *p)
1932{
1933 const struct ethhdr *eh = (struct ethhdr *)(p + 1);
1934 const struct iphdr *ih = (struct iphdr *)(eh + 1);
1935
1936 return (*((u8 *)p + 1) & 0x90) == 0x10 && p->csum == htons(0xffff) &&
1937 eh->h_proto == htons(ETH_P_IP) && ih->ihl == (sizeof(*ih) >> 2);
1938}
1939
1940#define TCP_FLAG_MASK (TCP_FLAG_CWR | TCP_FLAG_ECE | TCP_FLAG_URG |\
1941 TCP_FLAG_ACK | TCP_FLAG_PSH | TCP_FLAG_RST |\
1942 TCP_FLAG_SYN | TCP_FLAG_FIN)
1943#define TSTAMP_WORD ((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\
1944 (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)
1945
1946/**
1947 * lro_segment_ok - check if a TCP segment is eligible for LRO
1948 * @tcph: the TCP header of the packet
1949 *
1950 * Returns true if a TCP packet is eligible for LRO. This requires that
1951 * the packet have only the ACK flag set and no TCP options besides
1952 * time stamps.
1953 */
1954static inline int lro_segment_ok(const struct tcphdr *tcph)
1955{
1956 int optlen;
1957
1958 if (unlikely((tcp_flag_word(tcph) & TCP_FLAG_MASK) != TCP_FLAG_ACK))
1959 return 0;
1960
1961 optlen = (tcph->doff << 2) - sizeof(*tcph);
1962 if (optlen) {
1963 const u32 *opt = (const u32 *)(tcph + 1);
1964
1965 if (optlen != TCPOLEN_TSTAMP_ALIGNED ||
1966 *opt != htonl(TSTAMP_WORD) || !opt[2])
1967 return 0;
1968 }
1969 return 1;
1970}
1971
1972static int t3_get_lro_header(void **eh, void **iph, void **tcph,
1973 u64 *hdr_flags, void *priv)
1974{
1975 const struct cpl_rx_pkt *cpl = priv;
1976
1977 if (!lro_frame_ok(cpl))
1978 return -1;
1979
1980 *eh = (struct ethhdr *)(cpl + 1);
1981 *iph = (struct iphdr *)((struct ethhdr *)*eh + 1);
1982 *tcph = (struct tcphdr *)((struct iphdr *)*iph + 1);
1983
1984 if (!lro_segment_ok(*tcph))
1985 return -1;
1986
1987 *hdr_flags = LRO_IPV4 | LRO_TCP;
1988 return 0;
1989}
1990
1991static int t3_get_skb_header(struct sk_buff *skb,
1992 void **iph, void **tcph, u64 *hdr_flags,
1993 void *priv)
1994{
1995 void *eh;
1996
1997 return t3_get_lro_header(&eh, iph, tcph, hdr_flags, priv);
1998}
1999
2000static int t3_get_frag_header(struct skb_frag_struct *frag, void **eh,
2001 void **iph, void **tcph, u64 *hdr_flags,
2002 void *priv)
2003{
2004 return t3_get_lro_header(eh, iph, tcph, hdr_flags, priv);
2005}
2006
2007/**
2008 * lro_add_page - add a page chunk to an LRO session
2009 * @adap: the adapter
2010 * @qs: the associated queue set
2011 * @fl: the free list containing the page chunk to add
2012 * @len: packet length
2013 * @complete: Indicates the last fragment of a frame
2014 *
2015 * Add a received packet contained in a page chunk to an existing LRO
2016 * session.
2017 */
2018static void lro_add_page(struct adapter *adap, struct sge_qset *qs,
2019 struct sge_fl *fl, int len, int complete)
2020{
2021 struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
2022 struct cpl_rx_pkt *cpl;
2023 struct skb_frag_struct *rx_frag = qs->lro_frag_tbl;
2024 int nr_frags = qs->lro_nfrags, frag_len = qs->lro_frag_len;
2025 int offset = 0;
2026
2027 if (!nr_frags) {
2028 offset = 2 + sizeof(struct cpl_rx_pkt);
2029 qs->lro_va = cpl = sd->pg_chunk.va + 2;
2030 }
2031
2032 fl->credits--;
2033
2034 len -= offset;
2035 pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr),
2036 fl->buf_size, PCI_DMA_FROMDEVICE);
2037
2038 rx_frag += nr_frags;
2039 rx_frag->page = sd->pg_chunk.page;
2040 rx_frag->page_offset = sd->pg_chunk.offset + offset;
2041 rx_frag->size = len;
2042 frag_len += len;
2043 qs->lro_nfrags++;
2044 qs->lro_frag_len = frag_len;
2045
2046 if (!complete)
2047 return;
2048
2049 qs->lro_nfrags = qs->lro_frag_len = 0;
2050 cpl = qs->lro_va;
2051
2052 if (unlikely(cpl->vlan_valid)) {
2053 struct net_device *dev = qs->netdev;
2054 struct port_info *pi = netdev_priv(dev);
2055 struct vlan_group *grp = pi->vlan_grp;
2056
2057 if (likely(grp != NULL)) {
2058 lro_vlan_hwaccel_receive_frags(&qs->lro_mgr,
2059 qs->lro_frag_tbl,
2060 frag_len, frag_len,
2061 grp, ntohs(cpl->vlan),
2062 cpl, 0);
2063 return;
2064 }
2065 }
2066 lro_receive_frags(&qs->lro_mgr, qs->lro_frag_tbl,
2067 frag_len, frag_len, cpl, 0);
2068}
2069
2070/**
2071 * init_lro_mgr - initialize a LRO manager object
2072 * @lro_mgr: the LRO manager object
2073 */
2074static void init_lro_mgr(struct sge_qset *qs, struct net_lro_mgr *lro_mgr)
2075{
2076 lro_mgr->dev = qs->netdev;
2077 lro_mgr->features = LRO_F_NAPI;
2078 lro_mgr->ip_summed = CHECKSUM_UNNECESSARY;
2079 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2080 lro_mgr->max_desc = T3_MAX_LRO_SES;
2081 lro_mgr->lro_arr = qs->lro_desc;
2082 lro_mgr->get_frag_header = t3_get_frag_header;
2083 lro_mgr->get_skb_header = t3_get_skb_header;
2084 lro_mgr->max_aggr = T3_MAX_LRO_MAX_PKTS;
2085 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2086 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2087}
2088
1865/** 2089/**
1866 * handle_rsp_cntrl_info - handles control information in a response 2090 * handle_rsp_cntrl_info - handles control information in a response
1867 * @qs: the queue set corresponding to the response 2091 * @qs: the queue set corresponding to the response
@@ -1947,6 +2171,12 @@ static inline int is_new_response(const struct rsp_desc *r,
1947 return (r->intr_gen & F_RSPD_GEN2) == q->gen; 2171 return (r->intr_gen & F_RSPD_GEN2) == q->gen;
1948} 2172}
1949 2173
2174static inline void clear_rspq_bufstate(struct sge_rspq * const q)
2175{
2176 q->pg_skb = NULL;
2177 q->rx_recycle_buf = 0;
2178}
2179
1950#define RSPD_GTS_MASK (F_RSPD_TXQ0_GTS | F_RSPD_TXQ1_GTS) 2180#define RSPD_GTS_MASK (F_RSPD_TXQ0_GTS | F_RSPD_TXQ1_GTS)
1951#define RSPD_CTRL_MASK (RSPD_GTS_MASK | \ 2181#define RSPD_CTRL_MASK (RSPD_GTS_MASK | \
1952 V_RSPD_TXQ0_CR(M_RSPD_TXQ0_CR) | \ 2182 V_RSPD_TXQ0_CR(M_RSPD_TXQ0_CR) | \
@@ -1984,10 +2214,11 @@ static int process_responses(struct adapter *adap, struct sge_qset *qs,
1984 q->next_holdoff = q->holdoff_tmr; 2214 q->next_holdoff = q->holdoff_tmr;
1985 2215
1986 while (likely(budget_left && is_new_response(r, q))) { 2216 while (likely(budget_left && is_new_response(r, q))) {
1987 int eth, ethpad = 2; 2217 int packet_complete, eth, ethpad = 2, lro = qs->lro_enabled;
1988 struct sk_buff *skb = NULL; 2218 struct sk_buff *skb = NULL;
1989 u32 len, flags = ntohl(r->flags); 2219 u32 len, flags = ntohl(r->flags);
1990 __be32 rss_hi = *(const __be32 *)r, rss_lo = r->rss_hdr.rss_hash_val; 2220 __be32 rss_hi = *(const __be32 *)r,
2221 rss_lo = r->rss_hdr.rss_hash_val;
1991 2222
1992 eth = r->rss_hdr.opcode == CPL_RX_PKT; 2223 eth = r->rss_hdr.opcode == CPL_RX_PKT;
1993 2224
@@ -2015,6 +2246,9 @@ no_mem:
2015 } else if ((len = ntohl(r->len_cq)) != 0) { 2246 } else if ((len = ntohl(r->len_cq)) != 0) {
2016 struct sge_fl *fl; 2247 struct sge_fl *fl;
2017 2248
2249 if (eth)
2250 lro = qs->lro_enabled && is_eth_tcp(rss_hi);
2251
2018 fl = (len & F_RSPD_FLQ) ? &qs->fl[1] : &qs->fl[0]; 2252 fl = (len & F_RSPD_FLQ) ? &qs->fl[1] : &qs->fl[0];
2019 if (fl->use_pages) { 2253 if (fl->use_pages) {
2020 void *addr = fl->sdesc[fl->cidx].pg_chunk.va; 2254 void *addr = fl->sdesc[fl->cidx].pg_chunk.va;
@@ -2024,9 +2258,18 @@ no_mem:
2024 prefetch(addr + L1_CACHE_BYTES); 2258 prefetch(addr + L1_CACHE_BYTES);
2025#endif 2259#endif
2026 __refill_fl(adap, fl); 2260 __refill_fl(adap, fl);
2261 if (lro > 0) {
2262 lro_add_page(adap, qs, fl,
2263 G_RSPD_LEN(len),
2264 flags & F_RSPD_EOP);
2265 goto next_fl;
2266 }
2027 2267
2028 skb = get_packet_pg(adap, fl, G_RSPD_LEN(len), 2268 skb = get_packet_pg(adap, fl, q,
2029 eth ? SGE_RX_DROP_THRES : 0); 2269 G_RSPD_LEN(len),
2270 eth ?
2271 SGE_RX_DROP_THRES : 0);
2272 q->pg_skb = skb;
2030 } else 2273 } else
2031 skb = get_packet(adap, fl, G_RSPD_LEN(len), 2274 skb = get_packet(adap, fl, G_RSPD_LEN(len),
2032 eth ? SGE_RX_DROP_THRES : 0); 2275 eth ? SGE_RX_DROP_THRES : 0);
@@ -2036,7 +2279,7 @@ no_mem:
2036 q->rx_drops++; 2279 q->rx_drops++;
2037 } else if (unlikely(r->rss_hdr.opcode == CPL_TRACE_PKT)) 2280 } else if (unlikely(r->rss_hdr.opcode == CPL_TRACE_PKT))
2038 __skb_pull(skb, 2); 2281 __skb_pull(skb, 2);
2039 2282next_fl:
2040 if (++fl->cidx == fl->size) 2283 if (++fl->cidx == fl->size)
2041 fl->cidx = 0; 2284 fl->cidx = 0;
2042 } else 2285 } else
@@ -2060,9 +2303,13 @@ no_mem:
2060 q->credits = 0; 2303 q->credits = 0;
2061 } 2304 }
2062 2305
2063 if (likely(skb != NULL)) { 2306 packet_complete = flags &
2307 (F_RSPD_EOP | F_RSPD_IMM_DATA_VALID |
2308 F_RSPD_ASYNC_NOTIF);
2309
2310 if (skb != NULL && packet_complete) {
2064 if (eth) 2311 if (eth)
2065 rx_eth(adap, q, skb, ethpad); 2312 rx_eth(adap, q, skb, ethpad, lro);
2066 else { 2313 else {
2067 q->offload_pkts++; 2314 q->offload_pkts++;
2068 /* Preserve the RSS info in csum & priority */ 2315 /* Preserve the RSS info in csum & priority */
@@ -2072,11 +2319,19 @@ no_mem:
2072 offload_skbs, 2319 offload_skbs,
2073 ngathered); 2320 ngathered);
2074 } 2321 }
2322
2323 if (flags & F_RSPD_EOP)
2324 clear_rspq_bufstate(q);
2075 } 2325 }
2076 --budget_left; 2326 --budget_left;
2077 } 2327 }
2078 2328
2079 deliver_partial_bundle(&adap->tdev, q, offload_skbs, ngathered); 2329 deliver_partial_bundle(&adap->tdev, q, offload_skbs, ngathered);
2330 lro_flush_all(&qs->lro_mgr);
2331 qs->port_stats[SGE_PSTAT_LRO_AGGR] = qs->lro_mgr.stats.aggregated;
2332 qs->port_stats[SGE_PSTAT_LRO_FLUSHED] = qs->lro_mgr.stats.flushed;
2333 qs->port_stats[SGE_PSTAT_LRO_NO_DESC] = qs->lro_mgr.stats.no_desc;
2334
2080 if (sleeping) 2335 if (sleeping)
2081 check_ring_db(adap, qs, sleeping); 2336 check_ring_db(adap, qs, sleeping);
2082 2337
@@ -2618,8 +2873,9 @@ int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
2618 int irq_vec_idx, const struct qset_params *p, 2873 int irq_vec_idx, const struct qset_params *p,
2619 int ntxq, struct net_device *dev) 2874 int ntxq, struct net_device *dev)
2620{ 2875{
2621 int i, ret = -ENOMEM; 2876 int i, avail, ret = -ENOMEM;
2622 struct sge_qset *q = &adapter->sge.qs[id]; 2877 struct sge_qset *q = &adapter->sge.qs[id];
2878 struct net_lro_mgr *lro_mgr = &q->lro_mgr;
2623 2879
2624 init_qset_cntxt(q, id); 2880 init_qset_cntxt(q, id);
2625 init_timer(&q->tx_reclaim_timer); 2881 init_timer(&q->tx_reclaim_timer);
@@ -2687,11 +2943,23 @@ int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
2687#else 2943#else
2688 q->fl[0].buf_size = SGE_RX_SM_BUF_SIZE + sizeof(struct cpl_rx_data); 2944 q->fl[0].buf_size = SGE_RX_SM_BUF_SIZE + sizeof(struct cpl_rx_data);
2689#endif 2945#endif
2690 q->fl[0].use_pages = FL0_PG_CHUNK_SIZE > 0; 2946#if FL1_PG_CHUNK_SIZE > 0
2947 q->fl[1].buf_size = FL1_PG_CHUNK_SIZE;
2948#else
2691 q->fl[1].buf_size = is_offload(adapter) ? 2949 q->fl[1].buf_size = is_offload(adapter) ?
2692 (16 * 1024) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 2950 (16 * 1024) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
2693 MAX_FRAME_SIZE + 2 + sizeof(struct cpl_rx_pkt); 2951 MAX_FRAME_SIZE + 2 + sizeof(struct cpl_rx_pkt);
2952#endif
2694 2953
2954 q->fl[0].use_pages = FL0_PG_CHUNK_SIZE > 0;
2955 q->fl[1].use_pages = FL1_PG_CHUNK_SIZE > 0;
2956 q->fl[0].order = FL0_PG_ORDER;
2957 q->fl[1].order = FL1_PG_ORDER;
2958
2959 q->lro_frag_tbl = kcalloc(MAX_FRAME_SIZE / FL1_PG_CHUNK_SIZE + 1,
2960 sizeof(struct skb_frag_struct),
2961 GFP_KERNEL);
2962 q->lro_nfrags = q->lro_frag_len = 0;
2695 spin_lock_irq(&adapter->sge.reg_lock); 2963 spin_lock_irq(&adapter->sge.reg_lock);
2696 2964
2697 /* FL threshold comparison uses < */ 2965 /* FL threshold comparison uses < */
@@ -2742,8 +3010,23 @@ int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
2742 q->netdev = dev; 3010 q->netdev = dev;
2743 t3_update_qset_coalesce(q, p); 3011 t3_update_qset_coalesce(q, p);
2744 3012
2745 refill_fl(adapter, &q->fl[0], q->fl[0].size, GFP_KERNEL); 3013 init_lro_mgr(q, lro_mgr);
2746 refill_fl(adapter, &q->fl[1], q->fl[1].size, GFP_KERNEL); 3014
3015 avail = refill_fl(adapter, &q->fl[0], q->fl[0].size,
3016 GFP_KERNEL | __GFP_COMP);
3017 if (!avail) {
3018 CH_ALERT(adapter, "free list queue 0 initialization failed\n");
3019 goto err;
3020 }
3021 if (avail < q->fl[0].size)
3022 CH_WARN(adapter, "free list queue 0 enabled with %d credits\n",
3023 avail);
3024
3025 avail = refill_fl(adapter, &q->fl[1], q->fl[1].size,
3026 GFP_KERNEL | __GFP_COMP);
3027 if (avail < q->fl[1].size)
3028 CH_WARN(adapter, "free list queue 1 enabled with %d credits\n",
3029 avail);
2747 refill_rspq(adapter, &q->rspq, q->rspq.size - 1); 3030 refill_rspq(adapter, &q->rspq, q->rspq.size - 1);
2748 3031
2749 t3_write_reg(adapter, A_SG_GTS, V_RSPQ(q->rspq.cntxt_id) | 3032 t3_write_reg(adapter, A_SG_GTS, V_RSPQ(q->rspq.cntxt_id) |
@@ -2752,9 +3035,9 @@ int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
2752 mod_timer(&q->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); 3035 mod_timer(&q->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
2753 return 0; 3036 return 0;
2754 3037
2755 err_unlock: 3038err_unlock:
2756 spin_unlock_irq(&adapter->sge.reg_lock); 3039 spin_unlock_irq(&adapter->sge.reg_lock);
2757 err: 3040err:
2758 t3_free_qset(adapter, q); 3041 t3_free_qset(adapter, q);
2759 return ret; 3042 return ret;
2760} 3043}
@@ -2876,7 +3159,7 @@ void t3_sge_prep(struct adapter *adap, struct sge_params *p)
2876 q->coalesce_usecs = 5; 3159 q->coalesce_usecs = 5;
2877 q->rspq_size = 1024; 3160 q->rspq_size = 1024;
2878 q->fl_size = 1024; 3161 q->fl_size = 1024;
2879 q->jumbo_size = 512; 3162 q->jumbo_size = 512;
2880 q->txq_size[TXQ_ETH] = 1024; 3163 q->txq_size[TXQ_ETH] = 1024;
2881 q->txq_size[TXQ_OFLD] = 1024; 3164 q->txq_size[TXQ_OFLD] = 1024;
2882 q->txq_size[TXQ_CTRL] = 256; 3165 q->txq_size[TXQ_CTRL] = 256;
diff --git a/drivers/net/cxgb3/t3_cpl.h b/drivers/net/cxgb3/t3_cpl.h
index b7a1a310dfd4..917970ed24a1 100644
--- a/drivers/net/cxgb3/t3_cpl.h
+++ b/drivers/net/cxgb3/t3_cpl.h
@@ -174,6 +174,13 @@ enum { /* TCP congestion control algorithms */
174 CONG_ALG_HIGHSPEED 174 CONG_ALG_HIGHSPEED
175}; 175};
176 176
177enum { /* RSS hash type */
178 RSS_HASH_NONE = 0,
179 RSS_HASH_2_TUPLE = 1,
180 RSS_HASH_4_TUPLE = 2,
181 RSS_HASH_TCPV6 = 3
182};
183
177union opcode_tid { 184union opcode_tid {
178 __be32 opcode_tid; 185 __be32 opcode_tid;
179 __u8 opcode; 186 __u8 opcode;
@@ -184,6 +191,13 @@ union opcode_tid {
184#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) 191#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
185#define G_TID(x) ((x) & 0xFFFFFF) 192#define G_TID(x) ((x) & 0xFFFFFF)
186 193
194#define S_QNUM 0
195#define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF)
196
197#define S_HASHTYPE 22
198#define M_HASHTYPE 0x3
199#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
200
187/* tid is assumed to be 24-bits */ 201/* tid is assumed to be 24-bits */
188#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid)) 202#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
189 203
@@ -768,6 +782,12 @@ struct tx_data_wr {
768 __be32 param; 782 __be32 param;
769}; 783};
770 784
785/* tx_data_wr.flags fields */
786#define S_TX_ACK_PAGES 21
787#define M_TX_ACK_PAGES 0x7
788#define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
789#define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
790
771/* tx_data_wr.param fields */ 791/* tx_data_wr.param fields */
772#define S_TX_PORT 0 792#define S_TX_PORT 0
773#define M_TX_PORT 0x7 793#define M_TX_PORT 0x7
@@ -1441,4 +1461,35 @@ struct cpl_rdma_terminate {
1441#define M_TERM_TID 0xFFFFF 1461#define M_TERM_TID 0xFFFFF
1442#define V_TERM_TID(x) ((x) << S_TERM_TID) 1462#define V_TERM_TID(x) ((x) << S_TERM_TID)
1443#define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) 1463#define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1464
1465/* ULP_TX opcodes */
1466enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 };
1467
1468#define S_ULPTX_CMD 28
1469#define M_ULPTX_CMD 0xF
1470#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
1471
1472#define S_ULPTX_NFLITS 0
1473#define M_ULPTX_NFLITS 0xFF
1474#define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1475
1476struct ulp_mem_io {
1477 WR_HDR;
1478 __be32 cmd_lock_addr;
1479 __be32 len;
1480};
1481
1482/* ulp_mem_io.cmd_lock_addr fields */
1483#define S_ULP_MEMIO_ADDR 0
1484#define M_ULP_MEMIO_ADDR 0x7FFFFFF
1485#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1486#define S_ULP_MEMIO_LOCK 27
1487#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1488#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
1489
1490/* ulp_mem_io.len fields */
1491#define S_ULP_MEMIO_DATA_LEN 28
1492#define M_ULP_MEMIO_DATA_LEN 0xF
1493#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1494
1444#endif /* T3_CPL_H */ 1495#endif /* T3_CPL_H */
diff --git a/drivers/net/cxgb3/t3cdev.h b/drivers/net/cxgb3/t3cdev.h
index a18c8a140424..0a21cfbd2b21 100644
--- a/drivers/net/cxgb3/t3cdev.h
+++ b/drivers/net/cxgb3/t3cdev.h
@@ -45,7 +45,8 @@ struct cxgb3_client;
45 45
46enum t3ctype { 46enum t3ctype {
47 T3A = 0, 47 T3A = 0,
48 T3B 48 T3B,
49 T3C,
49}; 50};
50 51
51struct t3cdev { 52struct t3cdev {
@@ -63,6 +64,7 @@ struct t3cdev {
63 void *l3opt; /* optional layer 3 data */ 64 void *l3opt; /* optional layer 3 data */
64 void *l4opt; /* optional layer 4 data */ 65 void *l4opt; /* optional layer 4 data */
65 void *ulp; /* ulp stuff */ 66 void *ulp; /* ulp stuff */
67 void *ulp_iscsi; /* ulp iscsi */
66}; 68};
67 69
68#endif /* _T3CDEV_H_ */ 70#endif /* _T3CDEV_H_ */
diff --git a/drivers/net/declance.c b/drivers/net/declance.c
index 6b1e77cc069e..3e3506411ac0 100644
--- a/drivers/net/declance.c
+++ b/drivers/net/declance.c
@@ -773,8 +773,6 @@ static irqreturn_t lance_interrupt(int irq, void *dev_id)
773 return IRQ_HANDLED; 773 return IRQ_HANDLED;
774} 774}
775 775
776struct net_device *last_dev = 0;
777
778static int lance_open(struct net_device *dev) 776static int lance_open(struct net_device *dev)
779{ 777{
780 volatile u16 *ib = (volatile u16 *)dev->mem_start; 778 volatile u16 *ib = (volatile u16 *)dev->mem_start;
@@ -782,8 +780,6 @@ static int lance_open(struct net_device *dev)
782 volatile struct lance_regs *ll = lp->ll; 780 volatile struct lance_regs *ll = lp->ll;
783 int status = 0; 781 int status = 0;
784 782
785 last_dev = dev;
786
787 /* Stop the Lance */ 783 /* Stop the Lance */
788 writereg(&ll->rap, LE_CSR0); 784 writereg(&ll->rap, LE_CSR0);
789 writereg(&ll->rdp, LE_C0_STOP); 785 writereg(&ll->rdp, LE_C0_STOP);
diff --git a/drivers/net/dl2k.c b/drivers/net/dl2k.c
index e233d04a2132..f8037110a522 100644
--- a/drivers/net/dl2k.c
+++ b/drivers/net/dl2k.c
@@ -499,7 +499,7 @@ rio_timer (unsigned long data)
499 entry = np->old_rx % RX_RING_SIZE; 499 entry = np->old_rx % RX_RING_SIZE;
500 /* Dropped packets don't need to re-allocate */ 500 /* Dropped packets don't need to re-allocate */
501 if (np->rx_skbuff[entry] == NULL) { 501 if (np->rx_skbuff[entry] == NULL) {
502 skb = dev_alloc_skb (np->rx_buf_sz); 502 skb = netdev_alloc_skb (dev, np->rx_buf_sz);
503 if (skb == NULL) { 503 if (skb == NULL) {
504 np->rx_ring[entry].fraginfo = 0; 504 np->rx_ring[entry].fraginfo = 0;
505 printk (KERN_INFO 505 printk (KERN_INFO
@@ -570,7 +570,7 @@ alloc_list (struct net_device *dev)
570 /* Allocate the rx buffers */ 570 /* Allocate the rx buffers */
571 for (i = 0; i < RX_RING_SIZE; i++) { 571 for (i = 0; i < RX_RING_SIZE; i++) {
572 /* Allocated fixed size of skbuff */ 572 /* Allocated fixed size of skbuff */
573 struct sk_buff *skb = dev_alloc_skb (np->rx_buf_sz); 573 struct sk_buff *skb = netdev_alloc_skb (dev, np->rx_buf_sz);
574 np->rx_skbuff[i] = skb; 574 np->rx_skbuff[i] = skb;
575 if (skb == NULL) { 575 if (skb == NULL) {
576 printk (KERN_ERR 576 printk (KERN_ERR
@@ -867,7 +867,7 @@ receive_packet (struct net_device *dev)
867 PCI_DMA_FROMDEVICE); 867 PCI_DMA_FROMDEVICE);
868 skb_put (skb = np->rx_skbuff[entry], pkt_len); 868 skb_put (skb = np->rx_skbuff[entry], pkt_len);
869 np->rx_skbuff[entry] = NULL; 869 np->rx_skbuff[entry] = NULL;
870 } else if ((skb = dev_alloc_skb (pkt_len + 2)) != NULL) { 870 } else if ((skb = netdev_alloc_skb(dev, pkt_len + 2))) {
871 pci_dma_sync_single_for_cpu(np->pdev, 871 pci_dma_sync_single_for_cpu(np->pdev,
872 desc_to_dma(desc), 872 desc_to_dma(desc),
873 np->rx_buf_sz, 873 np->rx_buf_sz,
@@ -904,7 +904,7 @@ receive_packet (struct net_device *dev)
904 struct sk_buff *skb; 904 struct sk_buff *skb;
905 /* Dropped packets don't need to re-allocate */ 905 /* Dropped packets don't need to re-allocate */
906 if (np->rx_skbuff[entry] == NULL) { 906 if (np->rx_skbuff[entry] == NULL) {
907 skb = dev_alloc_skb (np->rx_buf_sz); 907 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
908 if (skb == NULL) { 908 if (skb == NULL) {
909 np->rx_ring[entry].fraginfo = 0; 909 np->rx_ring[entry].fraginfo = 0;
910 printk (KERN_INFO 910 printk (KERN_INFO
@@ -1753,7 +1753,7 @@ rio_close (struct net_device *dev)
1753 1753
1754 /* Stop Tx and Rx logics */ 1754 /* Stop Tx and Rx logics */
1755 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl); 1755 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
1756 synchronize_irq (dev->irq); 1756
1757 free_irq (dev->irq, dev); 1757 free_irq (dev->irq, dev);
1758 del_timer_sync (&np->timer); 1758 del_timer_sync (&np->timer);
1759 1759
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 864295e081b6..952e10d686ec 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c
@@ -44,9 +44,8 @@
44 44
45#define DM9000_PHY 0x40 /* PHY address 0x01 */ 45#define DM9000_PHY 0x40 /* PHY address 0x01 */
46 46
47#define CARDNAME "dm9000" 47#define CARDNAME "dm9000"
48#define PFX CARDNAME ": " 48#define DRV_VERSION "1.31"
49#define DRV_VERSION "1.30"
50 49
51#ifdef CONFIG_BLACKFIN 50#ifdef CONFIG_BLACKFIN
52#define readsb insb 51#define readsb insb
@@ -55,9 +54,6 @@
55#define writesb outsb 54#define writesb outsb
56#define writesw outsw 55#define writesw outsw
57#define writesl outsl 56#define writesl outsl
58#define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH
59#else
60#define DEFAULT_TRIGGER (0)
61#endif 57#endif
62 58
63/* 59/*
@@ -85,23 +81,36 @@ MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
85 * these two devices. 81 * these two devices.
86 */ 82 */
87 83
84/* The driver supports the original DM9000E, and now the two newer
85 * devices, DM9000A and DM9000B.
86 */
87
88enum dm9000_type {
89 TYPE_DM9000E, /* original DM9000 */
90 TYPE_DM9000A,
91 TYPE_DM9000B
92};
93
88/* Structure/enum declaration ------------------------------- */ 94/* Structure/enum declaration ------------------------------- */
89typedef struct board_info { 95typedef struct board_info {
90 96
91 void __iomem *io_addr; /* Register I/O base address */ 97 void __iomem *io_addr; /* Register I/O base address */
92 void __iomem *io_data; /* Data I/O address */ 98 void __iomem *io_data; /* Data I/O address */
93 u16 irq; /* IRQ */ 99 u16 irq; /* IRQ */
94 100
95 u16 tx_pkt_cnt; 101 u16 tx_pkt_cnt;
96 u16 queue_pkt_len; 102 u16 queue_pkt_len;
97 u16 queue_start_addr; 103 u16 queue_start_addr;
98 u16 dbug_cnt; 104 u16 dbug_cnt;
99 u8 io_mode; /* 0:word, 2:byte */ 105 u8 io_mode; /* 0:word, 2:byte */
100 u8 phy_addr; 106 u8 phy_addr;
101 unsigned int flags; 107 u8 imr_all;
102 unsigned int in_suspend :1;
103 108
104 int debug_level; 109 unsigned int flags;
110 unsigned int in_suspend :1;
111 int debug_level;
112
113 enum dm9000_type type;
105 114
106 void (*inblk)(void __iomem *port, void *data, int length); 115 void (*inblk)(void __iomem *port, void *data, int length);
107 void (*outblk)(void __iomem *port, void *data, int length); 116 void (*outblk)(void __iomem *port, void *data, int length);
@@ -120,10 +129,10 @@ typedef struct board_info {
120 struct delayed_work phy_poll; 129 struct delayed_work phy_poll;
121 struct net_device *ndev; 130 struct net_device *ndev;
122 131
123 spinlock_t lock; 132 spinlock_t lock;
124 133
125 struct mii_if_info mii; 134 struct mii_if_info mii;
126 u32 msg_enable; 135 u32 msg_enable;
127} board_info_t; 136} board_info_t;
128 137
129/* debug code */ 138/* debug code */
@@ -140,26 +149,6 @@ static inline board_info_t *to_dm9000_board(struct net_device *dev)
140 return dev->priv; 149 return dev->priv;
141} 150}
142 151
143/* function declaration ------------------------------------- */
144static int dm9000_probe(struct platform_device *);
145static int dm9000_open(struct net_device *);
146static int dm9000_start_xmit(struct sk_buff *, struct net_device *);
147static int dm9000_stop(struct net_device *);
148static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd);
149
150static void dm9000_init_dm9000(struct net_device *);
151
152static irqreturn_t dm9000_interrupt(int, void *);
153
154static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg);
155static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg,
156 int value);
157
158static void dm9000_read_eeprom(board_info_t *, int addr, u8 *to);
159static void dm9000_write_eeprom(board_info_t *, int addr, u8 *dp);
160static void dm9000_rx(struct net_device *);
161static void dm9000_hash_table(struct net_device *);
162
163/* DM9000 network board routine ---------------------------- */ 152/* DM9000 network board routine ---------------------------- */
164 153
165static void 154static void
@@ -302,52 +291,135 @@ static void dm9000_set_io(struct board_info *db, int byte_width)
302 291
303static void dm9000_schedule_poll(board_info_t *db) 292static void dm9000_schedule_poll(board_info_t *db)
304{ 293{
305 schedule_delayed_work(&db->phy_poll, HZ * 2); 294 if (db->type == TYPE_DM9000E)
295 schedule_delayed_work(&db->phy_poll, HZ * 2);
306} 296}
307 297
308/* Our watchdog timed out. Called by the networking layer */ 298static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
309static void dm9000_timeout(struct net_device *dev) 299{
300 board_info_t *dm = to_dm9000_board(dev);
301
302 if (!netif_running(dev))
303 return -EINVAL;
304
305 return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL);
306}
307
308static unsigned int
309dm9000_read_locked(board_info_t *db, int reg)
310{ 310{
311 board_info_t *db = (board_info_t *) dev->priv;
312 u8 reg_save;
313 unsigned long flags; 311 unsigned long flags;
312 unsigned int ret;
314 313
315 /* Save previous register address */ 314 spin_lock_irqsave(&db->lock, flags);
316 reg_save = readb(db->io_addr); 315 ret = ior(db, reg);
317 spin_lock_irqsave(&db->lock,flags); 316 spin_unlock_irqrestore(&db->lock, flags);
318 317
319 netif_stop_queue(dev); 318 return ret;
320 dm9000_reset(db); 319}
321 dm9000_init_dm9000(dev);
322 /* We can accept TX packets again */
323 dev->trans_start = jiffies;
324 netif_wake_queue(dev);
325 320
326 /* Restore previous register address */ 321static int dm9000_wait_eeprom(board_info_t *db)
327 writeb(reg_save, db->io_addr); 322{
328 spin_unlock_irqrestore(&db->lock,flags); 323 unsigned int status;
324 int timeout = 8; /* wait max 8msec */
325
326 /* The DM9000 data sheets say we should be able to
327 * poll the ERRE bit in EPCR to wait for the EEPROM
328 * operation. From testing several chips, this bit
329 * does not seem to work.
330 *
331 * We attempt to use the bit, but fall back to the
332 * timeout (which is why we do not return an error
333 * on expiry) to say that the EEPROM operation has
334 * completed.
335 */
336
337 while (1) {
338 status = dm9000_read_locked(db, DM9000_EPCR);
339
340 if ((status & EPCR_ERRE) == 0)
341 break;
342
343 msleep(1);
344
345 if (timeout-- < 0) {
346 dev_dbg(db->dev, "timeout waiting EEPROM\n");
347 break;
348 }
349 }
350
351 return 0;
329} 352}
330 353
331#ifdef CONFIG_NET_POLL_CONTROLLER
332/* 354/*
333 *Used by netconsole 355 * Read a word data from EEPROM
334 */ 356 */
335static void dm9000_poll_controller(struct net_device *dev) 357static void
358dm9000_read_eeprom(board_info_t *db, int offset, u8 *to)
336{ 359{
337 disable_irq(dev->irq); 360 unsigned long flags;
338 dm9000_interrupt(dev->irq,dev); 361
339 enable_irq(dev->irq); 362 if (db->flags & DM9000_PLATF_NO_EEPROM) {
363 to[0] = 0xff;
364 to[1] = 0xff;
365 return;
366 }
367
368 mutex_lock(&db->addr_lock);
369
370 spin_lock_irqsave(&db->lock, flags);
371
372 iow(db, DM9000_EPAR, offset);
373 iow(db, DM9000_EPCR, EPCR_ERPRR);
374
375 spin_unlock_irqrestore(&db->lock, flags);
376
377 dm9000_wait_eeprom(db);
378
379 /* delay for at-least 150uS */
380 msleep(1);
381
382 spin_lock_irqsave(&db->lock, flags);
383
384 iow(db, DM9000_EPCR, 0x0);
385
386 to[0] = ior(db, DM9000_EPDRL);
387 to[1] = ior(db, DM9000_EPDRH);
388
389 spin_unlock_irqrestore(&db->lock, flags);
390
391 mutex_unlock(&db->addr_lock);
340} 392}
341#endif
342 393
343static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 394/*
395 * Write a word data to SROM
396 */
397static void
398dm9000_write_eeprom(board_info_t *db, int offset, u8 *data)
344{ 399{
345 board_info_t *dm = to_dm9000_board(dev); 400 unsigned long flags;
346 401
347 if (!netif_running(dev)) 402 if (db->flags & DM9000_PLATF_NO_EEPROM)
348 return -EINVAL; 403 return;
349 404
350 return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); 405 mutex_lock(&db->addr_lock);
406
407 spin_lock_irqsave(&db->lock, flags);
408 iow(db, DM9000_EPAR, offset);
409 iow(db, DM9000_EPDRH, data[1]);
410 iow(db, DM9000_EPDRL, data[0]);
411 iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
412 spin_unlock_irqrestore(&db->lock, flags);
413
414 dm9000_wait_eeprom(db);
415
416 mdelay(1); /* wait at least 150uS to clear */
417
418 spin_lock_irqsave(&db->lock, flags);
419 iow(db, DM9000_EPCR, 0);
420 spin_unlock_irqrestore(&db->lock, flags);
421
422 mutex_unlock(&db->addr_lock);
351} 423}
352 424
353/* ethtool ops */ 425/* ethtool ops */
@@ -400,7 +472,14 @@ static int dm9000_nway_reset(struct net_device *dev)
400static u32 dm9000_get_link(struct net_device *dev) 472static u32 dm9000_get_link(struct net_device *dev)
401{ 473{
402 board_info_t *dm = to_dm9000_board(dev); 474 board_info_t *dm = to_dm9000_board(dev);
403 return mii_link_ok(&dm->mii); 475 u32 ret;
476
477 if (dm->flags & DM9000_PLATF_EXT_PHY)
478 ret = mii_link_ok(&dm->mii);
479 else
480 ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0;
481
482 return ret;
404} 483}
405 484
406#define DM_EEPROM_MAGIC (0x444D394B) 485#define DM_EEPROM_MAGIC (0x444D394B)
@@ -472,15 +551,48 @@ static const struct ethtool_ops dm9000_ethtool_ops = {
472 .set_eeprom = dm9000_set_eeprom, 551 .set_eeprom = dm9000_set_eeprom,
473}; 552};
474 553
554static void dm9000_show_carrier(board_info_t *db,
555 unsigned carrier, unsigned nsr)
556{
557 struct net_device *ndev = db->ndev;
558 unsigned ncr = dm9000_read_locked(db, DM9000_NCR);
559
560 if (carrier)
561 dev_info(db->dev, "%s: link up, %dMbps, %s-duplex, no LPA\n",
562 ndev->name, (nsr & NSR_SPEED) ? 10 : 100,
563 (ncr & NCR_FDX) ? "full" : "half");
564 else
565 dev_info(db->dev, "%s: link down\n", ndev->name);
566}
567
475static void 568static void
476dm9000_poll_work(struct work_struct *w) 569dm9000_poll_work(struct work_struct *w)
477{ 570{
478 struct delayed_work *dw = container_of(w, struct delayed_work, work); 571 struct delayed_work *dw = container_of(w, struct delayed_work, work);
479 board_info_t *db = container_of(dw, board_info_t, phy_poll); 572 board_info_t *db = container_of(dw, board_info_t, phy_poll);
573 struct net_device *ndev = db->ndev;
574
575 if (db->flags & DM9000_PLATF_SIMPLE_PHY &&
576 !(db->flags & DM9000_PLATF_EXT_PHY)) {
577 unsigned nsr = dm9000_read_locked(db, DM9000_NSR);
578 unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0;
579 unsigned new_carrier;
580
581 new_carrier = (nsr & NSR_LINKST) ? 1 : 0;
480 582
481 mii_check_media(&db->mii, netif_msg_link(db), 0); 583 if (old_carrier != new_carrier) {
584 if (netif_msg_link(db))
585 dm9000_show_carrier(db, new_carrier, nsr);
586
587 if (!new_carrier)
588 netif_carrier_off(ndev);
589 else
590 netif_carrier_on(ndev);
591 }
592 } else
593 mii_check_media(&db->mii, netif_msg_link(db), 0);
482 594
483 if (netif_running(db->ndev)) 595 if (netif_running(ndev))
484 dm9000_schedule_poll(db); 596 dm9000_schedule_poll(db);
485} 597}
486 598
@@ -492,12 +604,6 @@ dm9000_poll_work(struct work_struct *w)
492static void 604static void
493dm9000_release_board(struct platform_device *pdev, struct board_info *db) 605dm9000_release_board(struct platform_device *pdev, struct board_info *db)
494{ 606{
495 if (db->data_res == NULL) {
496 if (db->addr_res != NULL)
497 release_mem_region((unsigned long)db->io_addr, 4);
498 return;
499 }
500
501 /* unmap our resources */ 607 /* unmap our resources */
502 608
503 iounmap(db->io_addr); 609 iounmap(db->io_addr);
@@ -505,288 +611,73 @@ dm9000_release_board(struct platform_device *pdev, struct board_info *db)
505 611
506 /* release the resources */ 612 /* release the resources */
507 613
508 if (db->data_req != NULL) { 614 release_resource(db->data_req);
509 release_resource(db->data_req); 615 kfree(db->data_req);
510 kfree(db->data_req);
511 }
512 616
513 if (db->addr_req != NULL) { 617 release_resource(db->addr_req);
514 release_resource(db->addr_req); 618 kfree(db->addr_req);
515 kfree(db->addr_req);
516 }
517} 619}
518 620
519#define res_size(_r) (((_r)->end - (_r)->start) + 1) 621static unsigned char dm9000_type_to_char(enum dm9000_type type)
520
521/*
522 * Search DM9000 board, allocate space and register it
523 */
524static int __devinit
525dm9000_probe(struct platform_device *pdev)
526{ 622{
527 struct dm9000_plat_data *pdata = pdev->dev.platform_data; 623 switch (type) {
528 struct board_info *db; /* Point a board information structure */ 624 case TYPE_DM9000E: return 'e';
529 struct net_device *ndev; 625 case TYPE_DM9000A: return 'a';
530 const unsigned char *mac_src; 626 case TYPE_DM9000B: return 'b';
531 unsigned long base;
532 int ret = 0;
533 int iosize;
534 int i;
535 u32 id_val;
536
537 /* Init network device */
538 ndev = alloc_etherdev(sizeof (struct board_info));
539 if (!ndev) {
540 dev_err(&pdev->dev, "could not allocate device.\n");
541 return -ENOMEM;
542 }
543
544 SET_NETDEV_DEV(ndev, &pdev->dev);
545
546 dev_dbg(&pdev->dev, "dm9000_probe()\n");
547
548 /* setup board info structure */
549 db = (struct board_info *) ndev->priv;
550 memset(db, 0, sizeof (*db));
551
552 db->dev = &pdev->dev;
553 db->ndev = ndev;
554
555 spin_lock_init(&db->lock);
556 mutex_init(&db->addr_lock);
557
558 INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work);
559
560
561 if (pdev->num_resources < 2) {
562 ret = -ENODEV;
563 goto out;
564 } else if (pdev->num_resources == 2) {
565 base = pdev->resource[0].start;
566
567 if (!request_mem_region(base, 4, ndev->name)) {
568 ret = -EBUSY;
569 goto out;
570 }
571
572 ndev->base_addr = base;
573 ndev->irq = pdev->resource[1].start;
574 db->io_addr = (void __iomem *)base;
575 db->io_data = (void __iomem *)(base + 4);
576
577 /* ensure at least we have a default set of IO routines */
578 dm9000_set_io(db, 2);
579
580 } else {
581 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
582 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
583 db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
584
585 if (db->addr_res == NULL || db->data_res == NULL ||
586 db->irq_res == NULL) {
587 dev_err(db->dev, "insufficient resources\n");
588 ret = -ENOENT;
589 goto out;
590 }
591
592 i = res_size(db->addr_res);
593 db->addr_req = request_mem_region(db->addr_res->start, i,
594 pdev->name);
595
596 if (db->addr_req == NULL) {
597 dev_err(db->dev, "cannot claim address reg area\n");
598 ret = -EIO;
599 goto out;
600 }
601
602 db->io_addr = ioremap(db->addr_res->start, i);
603
604 if (db->io_addr == NULL) {
605 dev_err(db->dev, "failed to ioremap address reg\n");
606 ret = -EINVAL;
607 goto out;
608 }
609
610 iosize = res_size(db->data_res);
611 db->data_req = request_mem_region(db->data_res->start, iosize,
612 pdev->name);
613
614 if (db->data_req == NULL) {
615 dev_err(db->dev, "cannot claim data reg area\n");
616 ret = -EIO;
617 goto out;
618 }
619
620 db->io_data = ioremap(db->data_res->start, iosize);
621
622 if (db->io_data == NULL) {
623 dev_err(db->dev,"failed to ioremap data reg\n");
624 ret = -EINVAL;
625 goto out;
626 }
627
628 /* fill in parameters for net-dev structure */
629
630 ndev->base_addr = (unsigned long)db->io_addr;
631 ndev->irq = db->irq_res->start;
632
633 /* ensure at least we have a default set of IO routines */
634 dm9000_set_io(db, iosize);
635 } 627 }
636 628
637 /* check to see if anything is being over-ridden */ 629 return '?';
638 if (pdata != NULL) {
639 /* check to see if the driver wants to over-ride the
640 * default IO width */
641
642 if (pdata->flags & DM9000_PLATF_8BITONLY)
643 dm9000_set_io(db, 1);
644
645 if (pdata->flags & DM9000_PLATF_16BITONLY)
646 dm9000_set_io(db, 2);
647
648 if (pdata->flags & DM9000_PLATF_32BITONLY)
649 dm9000_set_io(db, 4);
650
651 /* check to see if there are any IO routine
652 * over-rides */
653
654 if (pdata->inblk != NULL)
655 db->inblk = pdata->inblk;
656
657 if (pdata->outblk != NULL)
658 db->outblk = pdata->outblk;
659
660 if (pdata->dumpblk != NULL)
661 db->dumpblk = pdata->dumpblk;
662
663 db->flags = pdata->flags;
664 }
665
666 dm9000_reset(db);
667
668 /* try two times, DM9000 sometimes gets the first read wrong */
669 for (i = 0; i < 8; i++) {
670 id_val = ior(db, DM9000_VIDL);
671 id_val |= (u32)ior(db, DM9000_VIDH) << 8;
672 id_val |= (u32)ior(db, DM9000_PIDL) << 16;
673 id_val |= (u32)ior(db, DM9000_PIDH) << 24;
674
675 if (id_val == DM9000_ID)
676 break;
677 dev_err(db->dev, "read wrong id 0x%08x\n", id_val);
678 }
679
680 if (id_val != DM9000_ID) {
681 dev_err(db->dev, "wrong id: 0x%08x\n", id_val);
682 ret = -ENODEV;
683 goto out;
684 }
685
686 /* from this point we assume that we have found a DM9000 */
687
688 /* driver system function */
689 ether_setup(ndev);
690
691 ndev->open = &dm9000_open;
692 ndev->hard_start_xmit = &dm9000_start_xmit;
693 ndev->tx_timeout = &dm9000_timeout;
694 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
695 ndev->stop = &dm9000_stop;
696 ndev->set_multicast_list = &dm9000_hash_table;
697 ndev->ethtool_ops = &dm9000_ethtool_ops;
698 ndev->do_ioctl = &dm9000_ioctl;
699
700#ifdef CONFIG_NET_POLL_CONTROLLER
701 ndev->poll_controller = &dm9000_poll_controller;
702#endif
703
704 db->msg_enable = NETIF_MSG_LINK;
705 db->mii.phy_id_mask = 0x1f;
706 db->mii.reg_num_mask = 0x1f;
707 db->mii.force_media = 0;
708 db->mii.full_duplex = 0;
709 db->mii.dev = ndev;
710 db->mii.mdio_read = dm9000_phy_read;
711 db->mii.mdio_write = dm9000_phy_write;
712
713 mac_src = "eeprom";
714
715 /* try reading the node address from the attached EEPROM */
716 for (i = 0; i < 6; i += 2)
717 dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i);
718
719 if (!is_valid_ether_addr(ndev->dev_addr)) {
720 /* try reading from mac */
721
722 mac_src = "chip";
723 for (i = 0; i < 6; i++)
724 ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
725 }
726
727 if (!is_valid_ether_addr(ndev->dev_addr))
728 dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
729 "set using ifconfig\n", ndev->name);
730
731 platform_set_drvdata(pdev, ndev);
732 ret = register_netdev(ndev);
733
734 if (ret == 0) {
735 DECLARE_MAC_BUF(mac);
736 printk("%s: dm9000 at %p,%p IRQ %d MAC: %s (%s)\n",
737 ndev->name, db->io_addr, db->io_data, ndev->irq,
738 print_mac(mac, ndev->dev_addr), mac_src);
739 }
740 return 0;
741
742out:
743 dev_err(db->dev, "not found (%d).\n", ret);
744
745 dm9000_release_board(pdev, db);
746 free_netdev(ndev);
747
748 return ret;
749} 630}
750 631
751/* 632/*
752 * Open the interface. 633 * Set DM9000 multicast address
753 * The interface is opened whenever "ifconfig" actives it.
754 */ 634 */
755static int 635static void
756dm9000_open(struct net_device *dev) 636dm9000_hash_table(struct net_device *dev)
757{ 637{
758 board_info_t *db = (board_info_t *) dev->priv; 638 board_info_t *db = (board_info_t *) dev->priv;
759 unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; 639 struct dev_mc_list *mcptr = dev->mc_list;
640 int mc_cnt = dev->mc_count;
641 int i, oft;
642 u32 hash_val;
643 u16 hash_table[4];
644 u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
645 unsigned long flags;
760 646
761 if (netif_msg_ifup(db)) 647 dm9000_dbg(db, 1, "entering %s\n", __func__);
762 dev_dbg(db->dev, "enabling %s\n", dev->name);
763 648
764 /* If there is no IRQ type specified, default to something that 649 spin_lock_irqsave(&db->lock, flags);
765 * may work, and tell the user that this is a problem */
766 650
767 if (irqflags == IRQF_TRIGGER_NONE) { 651 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
768 dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); 652 iow(db, oft, dev->dev_addr[i]);
769 irqflags = DEFAULT_TRIGGER;
770 }
771
772 irqflags |= IRQF_SHARED;
773 653
774 if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev)) 654 /* Clear Hash Table */
775 return -EAGAIN; 655 for (i = 0; i < 4; i++)
656 hash_table[i] = 0x0;
776 657
777 /* Initialize DM9000 board */ 658 /* broadcast address */
778 dm9000_reset(db); 659 hash_table[3] = 0x8000;
779 dm9000_init_dm9000(dev);
780 660
781 /* Init driver variable */ 661 if (dev->flags & IFF_PROMISC)
782 db->dbug_cnt = 0; 662 rcr |= RCR_PRMSC;
783 663
784 mii_check_media(&db->mii, netif_msg_link(db), 1); 664 if (dev->flags & IFF_ALLMULTI)
785 netif_start_queue(dev); 665 rcr |= RCR_ALL;
786
787 dm9000_schedule_poll(db);
788 666
789 return 0; 667 /* the multicast address in Hash Table : 64 bits */
668 for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
669 hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f;
670 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
671 }
672
673 /* Write the hash table to MAC MD table */
674 for (i = 0, oft = DM9000_MAR; i < 4; i++) {
675 iow(db, oft++, hash_table[i]);
676 iow(db, oft++, hash_table[i] >> 8);
677 }
678
679 iow(db, DM9000_RCR, rcr);
680 spin_unlock_irqrestore(&db->lock, flags);
790} 681}
791 682
792/* 683/*
@@ -795,7 +686,8 @@ dm9000_open(struct net_device *dev)
795static void 686static void
796dm9000_init_dm9000(struct net_device *dev) 687dm9000_init_dm9000(struct net_device *dev)
797{ 688{
798 board_info_t *db = (board_info_t *) dev->priv; 689 board_info_t *db = dev->priv;
690 unsigned int imr;
799 691
800 dm9000_dbg(db, 1, "entering %s\n", __func__); 692 dm9000_dbg(db, 1, "entering %s\n", __func__);
801 693
@@ -822,8 +714,14 @@ dm9000_init_dm9000(struct net_device *dev)
822 /* Set address filter table */ 714 /* Set address filter table */
823 dm9000_hash_table(dev); 715 dm9000_hash_table(dev);
824 716
717 imr = IMR_PAR | IMR_PTM | IMR_PRM;
718 if (db->type != TYPE_DM9000E)
719 imr |= IMR_LNKCHNG;
720
721 db->imr_all = imr;
722
825 /* Enable TX/RX interrupt mask */ 723 /* Enable TX/RX interrupt mask */
826 iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM); 724 iow(db, DM9000_IMR, imr);
827 725
828 /* Init Driver variable */ 726 /* Init Driver variable */
829 db->tx_pkt_cnt = 0; 727 db->tx_pkt_cnt = 0;
@@ -831,6 +729,29 @@ dm9000_init_dm9000(struct net_device *dev)
831 dev->trans_start = 0; 729 dev->trans_start = 0;
832} 730}
833 731
732/* Our watchdog timed out. Called by the networking layer */
733static void dm9000_timeout(struct net_device *dev)
734{
735 board_info_t *db = (board_info_t *) dev->priv;
736 u8 reg_save;
737 unsigned long flags;
738
739 /* Save previous register address */
740 reg_save = readb(db->io_addr);
741 spin_lock_irqsave(&db->lock, flags);
742
743 netif_stop_queue(dev);
744 dm9000_reset(db);
745 dm9000_init_dm9000(dev);
746 /* We can accept TX packets again */
747 dev->trans_start = jiffies;
748 netif_wake_queue(dev);
749
750 /* Restore previous register address */
751 writeb(reg_save, db->io_addr);
752 spin_unlock_irqrestore(&db->lock, flags);
753}
754
834/* 755/*
835 * Hardware start transmission. 756 * Hardware start transmission.
836 * Send a packet to media from the upper layer. 757 * Send a packet to media from the upper layer.
@@ -839,7 +760,7 @@ static int
839dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) 760dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
840{ 761{
841 unsigned long flags; 762 unsigned long flags;
842 board_info_t *db = (board_info_t *) dev->priv; 763 board_info_t *db = dev->priv;
843 764
844 dm9000_dbg(db, 3, "%s:\n", __func__); 765 dm9000_dbg(db, 3, "%s:\n", __func__);
845 766
@@ -879,50 +800,12 @@ dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
879 return 0; 800 return 0;
880} 801}
881 802
882static void
883dm9000_shutdown(struct net_device *dev)
884{
885 board_info_t *db = (board_info_t *) dev->priv;
886
887 /* RESET device */
888 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
889 iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
890 iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */
891 iow(db, DM9000_RCR, 0x00); /* Disable RX */
892}
893
894/*
895 * Stop the interface.
896 * The interface is stopped when it is brought.
897 */
898static int
899dm9000_stop(struct net_device *ndev)
900{
901 board_info_t *db = (board_info_t *) ndev->priv;
902
903 if (netif_msg_ifdown(db))
904 dev_dbg(db->dev, "shutting down %s\n", ndev->name);
905
906 cancel_delayed_work_sync(&db->phy_poll);
907
908 netif_stop_queue(ndev);
909 netif_carrier_off(ndev);
910
911 /* free interrupt */
912 free_irq(ndev->irq, ndev);
913
914 dm9000_shutdown(ndev);
915
916 return 0;
917}
918
919/* 803/*
920 * DM9000 interrupt handler 804 * DM9000 interrupt handler
921 * receive the packet to upper layer, free the transmitted packet 805 * receive the packet to upper layer, free the transmitted packet
922 */ 806 */
923 807
924static void 808static void dm9000_tx_done(struct net_device *dev, board_info_t *db)
925dm9000_tx_done(struct net_device *dev, board_info_t * db)
926{ 809{
927 int tx_status = ior(db, DM9000_NSR); /* Got TX status */ 810 int tx_status = ior(db, DM9000_NSR); /* Got TX status */
928 811
@@ -945,52 +828,6 @@ dm9000_tx_done(struct net_device *dev, board_info_t * db)
945 } 828 }
946} 829}
947 830
948static irqreturn_t
949dm9000_interrupt(int irq, void *dev_id)
950{
951 struct net_device *dev = dev_id;
952 board_info_t *db = (board_info_t *) dev->priv;
953 int int_status;
954 u8 reg_save;
955
956 dm9000_dbg(db, 3, "entering %s\n", __func__);
957
958 /* A real interrupt coming */
959
960 spin_lock(&db->lock);
961
962 /* Save previous register address */
963 reg_save = readb(db->io_addr);
964
965 /* Disable all interrupts */
966 iow(db, DM9000_IMR, IMR_PAR);
967
968 /* Got DM9000 interrupt status */
969 int_status = ior(db, DM9000_ISR); /* Got ISR */
970 iow(db, DM9000_ISR, int_status); /* Clear ISR status */
971
972 if (netif_msg_intr(db))
973 dev_dbg(db->dev, "interrupt status %02x\n", int_status);
974
975 /* Received the coming packet */
976 if (int_status & ISR_PRS)
977 dm9000_rx(dev);
978
979 /* Trnasmit Interrupt check */
980 if (int_status & ISR_PTS)
981 dm9000_tx_done(dev, db);
982
983 /* Re-enable interrupt mask */
984 iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
985
986 /* Restore previous register address */
987 writeb(reg_save, db->io_addr);
988
989 spin_unlock(&db->lock);
990
991 return IRQ_HANDLED;
992}
993
994struct dm9000_rxhdr { 831struct dm9000_rxhdr {
995 u8 RxPktReady; 832 u8 RxPktReady;
996 u8 RxStatus; 833 u8 RxStatus;
@@ -1094,173 +931,109 @@ dm9000_rx(struct net_device *dev)
1094 } while (rxbyte == DM9000_PKT_RDY); 931 } while (rxbyte == DM9000_PKT_RDY);
1095} 932}
1096 933
1097static unsigned int 934static irqreturn_t dm9000_interrupt(int irq, void *dev_id)
1098dm9000_read_locked(board_info_t *db, int reg)
1099{ 935{
1100 unsigned long flags; 936 struct net_device *dev = dev_id;
1101 unsigned int ret; 937 board_info_t *db = dev->priv;
938 int int_status;
939 u8 reg_save;
1102 940
1103 spin_lock_irqsave(&db->lock, flags); 941 dm9000_dbg(db, 3, "entering %s\n", __func__);
1104 ret = ior(db, reg);
1105 spin_unlock_irqrestore(&db->lock, flags);
1106 942
1107 return ret; 943 /* A real interrupt coming */
1108}
1109 944
1110static int dm9000_wait_eeprom(board_info_t *db) 945 spin_lock(&db->lock);
1111{
1112 unsigned int status;
1113 int timeout = 8; /* wait max 8msec */
1114 946
1115 /* The DM9000 data sheets say we should be able to 947 /* Save previous register address */
1116 * poll the ERRE bit in EPCR to wait for the EEPROM 948 reg_save = readb(db->io_addr);
1117 * operation. From testing several chips, this bit
1118 * does not seem to work.
1119 *
1120 * We attempt to use the bit, but fall back to the
1121 * timeout (which is why we do not return an error
1122 * on expiry) to say that the EEPROM operation has
1123 * completed.
1124 */
1125 949
1126 while (1) { 950 /* Disable all interrupts */
1127 status = dm9000_read_locked(db, DM9000_EPCR); 951 iow(db, DM9000_IMR, IMR_PAR);
1128 952
1129 if ((status & EPCR_ERRE) == 0) 953 /* Got DM9000 interrupt status */
1130 break; 954 int_status = ior(db, DM9000_ISR); /* Got ISR */
955 iow(db, DM9000_ISR, int_status); /* Clear ISR status */
1131 956
1132 if (timeout-- < 0) { 957 if (netif_msg_intr(db))
1133 dev_dbg(db->dev, "timeout waiting EEPROM\n"); 958 dev_dbg(db->dev, "interrupt status %02x\n", int_status);
1134 break;
1135 }
1136 }
1137 959
1138 return 0; 960 /* Received the coming packet */
1139} 961 if (int_status & ISR_PRS)
962 dm9000_rx(dev);
1140 963
1141/* 964 /* Trnasmit Interrupt check */
1142 * Read a word data from EEPROM 965 if (int_status & ISR_PTS)
1143 */ 966 dm9000_tx_done(dev, db);
1144static void
1145dm9000_read_eeprom(board_info_t *db, int offset, u8 *to)
1146{
1147 unsigned long flags;
1148 967
1149 if (db->flags & DM9000_PLATF_NO_EEPROM) { 968 if (db->type != TYPE_DM9000E) {
1150 to[0] = 0xff; 969 if (int_status & ISR_LNKCHNG) {
1151 to[1] = 0xff; 970 /* fire a link-change request */
1152 return; 971 schedule_delayed_work(&db->phy_poll, 1);
972 }
1153 } 973 }
1154 974
1155 mutex_lock(&db->addr_lock); 975 /* Re-enable interrupt mask */
1156 976 iow(db, DM9000_IMR, db->imr_all);
1157 spin_lock_irqsave(&db->lock, flags);
1158
1159 iow(db, DM9000_EPAR, offset);
1160 iow(db, DM9000_EPCR, EPCR_ERPRR);
1161
1162 spin_unlock_irqrestore(&db->lock, flags);
1163
1164 dm9000_wait_eeprom(db);
1165
1166 /* delay for at-least 150uS */
1167 msleep(1);
1168
1169 spin_lock_irqsave(&db->lock, flags);
1170
1171 iow(db, DM9000_EPCR, 0x0);
1172 977
1173 to[0] = ior(db, DM9000_EPDRL); 978 /* Restore previous register address */
1174 to[1] = ior(db, DM9000_EPDRH); 979 writeb(reg_save, db->io_addr);
1175 980
1176 spin_unlock_irqrestore(&db->lock, flags); 981 spin_unlock(&db->lock);
1177 982
1178 mutex_unlock(&db->addr_lock); 983 return IRQ_HANDLED;
1179} 984}
1180 985
986#ifdef CONFIG_NET_POLL_CONTROLLER
1181/* 987/*
1182 * Write a word data to SROM 988 *Used by netconsole
1183 */ 989 */
1184static void 990static void dm9000_poll_controller(struct net_device *dev)
1185dm9000_write_eeprom(board_info_t *db, int offset, u8 *data)
1186{ 991{
1187 unsigned long flags; 992 disable_irq(dev->irq);
1188 993 dm9000_interrupt(dev->irq, dev);
1189 if (db->flags & DM9000_PLATF_NO_EEPROM) 994 enable_irq(dev->irq);
1190 return;
1191
1192 mutex_lock(&db->addr_lock);
1193
1194 spin_lock_irqsave(&db->lock, flags);
1195 iow(db, DM9000_EPAR, offset);
1196 iow(db, DM9000_EPDRH, data[1]);
1197 iow(db, DM9000_EPDRL, data[0]);
1198 iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
1199 spin_unlock_irqrestore(&db->lock, flags);
1200
1201 dm9000_wait_eeprom(db);
1202
1203 mdelay(1); /* wait at least 150uS to clear */
1204
1205 spin_lock_irqsave(&db->lock, flags);
1206 iow(db, DM9000_EPCR, 0);
1207 spin_unlock_irqrestore(&db->lock, flags);
1208
1209 mutex_unlock(&db->addr_lock);
1210} 995}
996#endif
1211 997
1212/* 998/*
1213 * Set DM9000 multicast address 999 * Open the interface.
1000 * The interface is opened whenever "ifconfig" actives it.
1214 */ 1001 */
1215static void 1002static int
1216dm9000_hash_table(struct net_device *dev) 1003dm9000_open(struct net_device *dev)
1217{ 1004{
1218 board_info_t *db = (board_info_t *) dev->priv; 1005 board_info_t *db = dev->priv;
1219 struct dev_mc_list *mcptr = dev->mc_list; 1006 unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK;
1220 int mc_cnt = dev->mc_count;
1221 int i, oft;
1222 u32 hash_val;
1223 u16 hash_table[4];
1224 u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
1225 unsigned long flags;
1226
1227 dm9000_dbg(db, 1, "entering %s\n", __func__);
1228 1007
1229 spin_lock_irqsave(&db->lock, flags); 1008 if (netif_msg_ifup(db))
1009 dev_dbg(db->dev, "enabling %s\n", dev->name);
1230 1010
1231 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) 1011 /* If there is no IRQ type specified, default to something that
1232 iow(db, oft, dev->dev_addr[i]); 1012 * may work, and tell the user that this is a problem */
1233 1013
1234 /* Clear Hash Table */ 1014 if (irqflags == IRQF_TRIGGER_NONE)
1235 for (i = 0; i < 4; i++) 1015 dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n");
1236 hash_table[i] = 0x0;
1237 1016
1238 /* broadcast address */ 1017 irqflags |= IRQF_SHARED;
1239 hash_table[3] = 0x8000;
1240 1018
1241 if (dev->flags & IFF_PROMISC) 1019 if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev))
1242 rcr |= RCR_PRMSC; 1020 return -EAGAIN;
1243 1021
1244 if (dev->flags & IFF_ALLMULTI) 1022 /* Initialize DM9000 board */
1245 rcr |= RCR_ALL; 1023 dm9000_reset(db);
1024 dm9000_init_dm9000(dev);
1246 1025
1247 /* the multicast address in Hash Table : 64 bits */ 1026 /* Init driver variable */
1248 for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { 1027 db->dbug_cnt = 0;
1249 hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f;
1250 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1251 }
1252 1028
1253 /* Write the hash table to MAC MD table */ 1029 mii_check_media(&db->mii, netif_msg_link(db), 1);
1254 for (i = 0, oft = DM9000_MAR; i < 4; i++) { 1030 netif_start_queue(dev);
1255 iow(db, oft++, hash_table[i]); 1031
1256 iow(db, oft++, hash_table[i] >> 8); 1032 dm9000_schedule_poll(db);
1257 }
1258 1033
1259 iow(db, DM9000_RCR, rcr); 1034 return 0;
1260 spin_unlock_irqrestore(&db->lock, flags);
1261} 1035}
1262 1036
1263
1264/* 1037/*
1265 * Sleep, either by using msleep() or if we are suspending, then 1038 * Sleep, either by using msleep() or if we are suspending, then
1266 * use mdelay() to sleep. 1039 * use mdelay() to sleep.
@@ -1323,7 +1096,8 @@ dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
1323 * Write a word to phyxcer 1096 * Write a word to phyxcer
1324 */ 1097 */
1325static void 1098static void
1326dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value) 1099dm9000_phy_write(struct net_device *dev,
1100 int phyaddr_unused, int reg, int value)
1327{ 1101{
1328 board_info_t *db = (board_info_t *) dev->priv; 1102 board_info_t *db = (board_info_t *) dev->priv;
1329 unsigned long flags; 1103 unsigned long flags;
@@ -1363,6 +1137,273 @@ dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value)
1363 mutex_unlock(&db->addr_lock); 1137 mutex_unlock(&db->addr_lock);
1364} 1138}
1365 1139
1140static void
1141dm9000_shutdown(struct net_device *dev)
1142{
1143 board_info_t *db = dev->priv;
1144
1145 /* RESET device */
1146 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
1147 iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
1148 iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */
1149 iow(db, DM9000_RCR, 0x00); /* Disable RX */
1150}
1151
1152/*
1153 * Stop the interface.
1154 * The interface is stopped when it is brought.
1155 */
1156static int
1157dm9000_stop(struct net_device *ndev)
1158{
1159 board_info_t *db = ndev->priv;
1160
1161 if (netif_msg_ifdown(db))
1162 dev_dbg(db->dev, "shutting down %s\n", ndev->name);
1163
1164 cancel_delayed_work_sync(&db->phy_poll);
1165
1166 netif_stop_queue(ndev);
1167 netif_carrier_off(ndev);
1168
1169 /* free interrupt */
1170 free_irq(ndev->irq, ndev);
1171
1172 dm9000_shutdown(ndev);
1173
1174 return 0;
1175}
1176
1177#define res_size(_r) (((_r)->end - (_r)->start) + 1)
1178
1179/*
1180 * Search DM9000 board, allocate space and register it
1181 */
1182static int __devinit
1183dm9000_probe(struct platform_device *pdev)
1184{
1185 struct dm9000_plat_data *pdata = pdev->dev.platform_data;
1186 struct board_info *db; /* Point a board information structure */
1187 struct net_device *ndev;
1188 const unsigned char *mac_src;
1189 int ret = 0;
1190 int iosize;
1191 int i;
1192 u32 id_val;
1193
1194 /* Init network device */
1195 ndev = alloc_etherdev(sizeof(struct board_info));
1196 if (!ndev) {
1197 dev_err(&pdev->dev, "could not allocate device.\n");
1198 return -ENOMEM;
1199 }
1200
1201 SET_NETDEV_DEV(ndev, &pdev->dev);
1202
1203 dev_dbg(&pdev->dev, "dm9000_probe()\n");
1204
1205 /* setup board info structure */
1206 db = ndev->priv;
1207 memset(db, 0, sizeof(*db));
1208
1209 db->dev = &pdev->dev;
1210 db->ndev = ndev;
1211
1212 spin_lock_init(&db->lock);
1213 mutex_init(&db->addr_lock);
1214
1215 INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work);
1216
1217 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1218 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1219 db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1220
1221 if (db->addr_res == NULL || db->data_res == NULL ||
1222 db->irq_res == NULL) {
1223 dev_err(db->dev, "insufficient resources\n");
1224 ret = -ENOENT;
1225 goto out;
1226 }
1227
1228 iosize = res_size(db->addr_res);
1229 db->addr_req = request_mem_region(db->addr_res->start, iosize,
1230 pdev->name);
1231
1232 if (db->addr_req == NULL) {
1233 dev_err(db->dev, "cannot claim address reg area\n");
1234 ret = -EIO;
1235 goto out;
1236 }
1237
1238 db->io_addr = ioremap(db->addr_res->start, iosize);
1239
1240 if (db->io_addr == NULL) {
1241 dev_err(db->dev, "failed to ioremap address reg\n");
1242 ret = -EINVAL;
1243 goto out;
1244 }
1245
1246 iosize = res_size(db->data_res);
1247 db->data_req = request_mem_region(db->data_res->start, iosize,
1248 pdev->name);
1249
1250 if (db->data_req == NULL) {
1251 dev_err(db->dev, "cannot claim data reg area\n");
1252 ret = -EIO;
1253 goto out;
1254 }
1255
1256 db->io_data = ioremap(db->data_res->start, iosize);
1257
1258 if (db->io_data == NULL) {
1259 dev_err(db->dev, "failed to ioremap data reg\n");
1260 ret = -EINVAL;
1261 goto out;
1262 }
1263
1264 /* fill in parameters for net-dev structure */
1265 ndev->base_addr = (unsigned long)db->io_addr;
1266 ndev->irq = db->irq_res->start;
1267
1268 /* ensure at least we have a default set of IO routines */
1269 dm9000_set_io(db, iosize);
1270
1271 /* check to see if anything is being over-ridden */
1272 if (pdata != NULL) {
1273 /* check to see if the driver wants to over-ride the
1274 * default IO width */
1275
1276 if (pdata->flags & DM9000_PLATF_8BITONLY)
1277 dm9000_set_io(db, 1);
1278
1279 if (pdata->flags & DM9000_PLATF_16BITONLY)
1280 dm9000_set_io(db, 2);
1281
1282 if (pdata->flags & DM9000_PLATF_32BITONLY)
1283 dm9000_set_io(db, 4);
1284
1285 /* check to see if there are any IO routine
1286 * over-rides */
1287
1288 if (pdata->inblk != NULL)
1289 db->inblk = pdata->inblk;
1290
1291 if (pdata->outblk != NULL)
1292 db->outblk = pdata->outblk;
1293
1294 if (pdata->dumpblk != NULL)
1295 db->dumpblk = pdata->dumpblk;
1296
1297 db->flags = pdata->flags;
1298 }
1299
1300#ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL
1301 db->flags |= DM9000_PLATF_SIMPLE_PHY;
1302#endif
1303
1304 dm9000_reset(db);
1305
1306 /* try multiple times, DM9000 sometimes gets the read wrong */
1307 for (i = 0; i < 8; i++) {
1308 id_val = ior(db, DM9000_VIDL);
1309 id_val |= (u32)ior(db, DM9000_VIDH) << 8;
1310 id_val |= (u32)ior(db, DM9000_PIDL) << 16;
1311 id_val |= (u32)ior(db, DM9000_PIDH) << 24;
1312
1313 if (id_val == DM9000_ID)
1314 break;
1315 dev_err(db->dev, "read wrong id 0x%08x\n", id_val);
1316 }
1317
1318 if (id_val != DM9000_ID) {
1319 dev_err(db->dev, "wrong id: 0x%08x\n", id_val);
1320 ret = -ENODEV;
1321 goto out;
1322 }
1323
1324 /* Identify what type of DM9000 we are working on */
1325
1326 id_val = ior(db, DM9000_CHIPR);
1327 dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val);
1328
1329 switch (id_val) {
1330 case CHIPR_DM9000A:
1331 db->type = TYPE_DM9000A;
1332 break;
1333 case CHIPR_DM9000B:
1334 db->type = TYPE_DM9000B;
1335 break;
1336 default:
1337 dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val);
1338 db->type = TYPE_DM9000E;
1339 }
1340
1341 /* from this point we assume that we have found a DM9000 */
1342
1343 /* driver system function */
1344 ether_setup(ndev);
1345
1346 ndev->open = &dm9000_open;
1347 ndev->hard_start_xmit = &dm9000_start_xmit;
1348 ndev->tx_timeout = &dm9000_timeout;
1349 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
1350 ndev->stop = &dm9000_stop;
1351 ndev->set_multicast_list = &dm9000_hash_table;
1352 ndev->ethtool_ops = &dm9000_ethtool_ops;
1353 ndev->do_ioctl = &dm9000_ioctl;
1354
1355#ifdef CONFIG_NET_POLL_CONTROLLER
1356 ndev->poll_controller = &dm9000_poll_controller;
1357#endif
1358
1359 db->msg_enable = NETIF_MSG_LINK;
1360 db->mii.phy_id_mask = 0x1f;
1361 db->mii.reg_num_mask = 0x1f;
1362 db->mii.force_media = 0;
1363 db->mii.full_duplex = 0;
1364 db->mii.dev = ndev;
1365 db->mii.mdio_read = dm9000_phy_read;
1366 db->mii.mdio_write = dm9000_phy_write;
1367
1368 mac_src = "eeprom";
1369
1370 /* try reading the node address from the attached EEPROM */
1371 for (i = 0; i < 6; i += 2)
1372 dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i);
1373
1374 if (!is_valid_ether_addr(ndev->dev_addr)) {
1375 /* try reading from mac */
1376
1377 mac_src = "chip";
1378 for (i = 0; i < 6; i++)
1379 ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
1380 }
1381
1382 if (!is_valid_ether_addr(ndev->dev_addr))
1383 dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
1384 "set using ifconfig\n", ndev->name);
1385
1386 platform_set_drvdata(pdev, ndev);
1387 ret = register_netdev(ndev);
1388
1389 if (ret == 0) {
1390 DECLARE_MAC_BUF(mac);
1391 printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %s (%s)\n",
1392 ndev->name, dm9000_type_to_char(db->type),
1393 db->io_addr, db->io_data, ndev->irq,
1394 print_mac(mac, ndev->dev_addr), mac_src);
1395 }
1396 return 0;
1397
1398out:
1399 dev_err(db->dev, "not found (%d).\n", ret);
1400
1401 dm9000_release_board(pdev, db);
1402 free_netdev(ndev);
1403
1404 return ret;
1405}
1406
1366static int 1407static int
1367dm9000_drv_suspend(struct platform_device *dev, pm_message_t state) 1408dm9000_drv_suspend(struct platform_device *dev, pm_message_t state)
1368{ 1409{
@@ -1432,7 +1473,7 @@ dm9000_init(void)
1432{ 1473{
1433 printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); 1474 printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION);
1434 1475
1435 return platform_driver_register(&dm9000_driver); /* search board and register */ 1476 return platform_driver_register(&dm9000_driver);
1436} 1477}
1437 1478
1438static void __exit 1479static void __exit
diff --git a/drivers/net/dm9000.h b/drivers/net/dm9000.h
index 82cad360bafc..ba25cf541420 100644
--- a/drivers/net/dm9000.h
+++ b/drivers/net/dm9000.h
@@ -45,6 +45,9 @@
45#define DM9000_CHIPR 0x2C 45#define DM9000_CHIPR 0x2C
46#define DM9000_SMCR 0x2F 46#define DM9000_SMCR 0x2F
47 47
48#define CHIPR_DM9000A 0x19
49#define CHIPR_DM9000B 0x1B
50
48#define DM9000_MRCMDX 0xF0 51#define DM9000_MRCMDX 0xF0
49#define DM9000_MRCMD 0xF2 52#define DM9000_MRCMD 0xF2
50#define DM9000_MRRL 0xF4 53#define DM9000_MRRL 0xF4
@@ -131,5 +134,13 @@
131#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */ 134#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
132#define DM9000_PKT_MAX 1536 /* Received packet max size */ 135#define DM9000_PKT_MAX 1536 /* Received packet max size */
133 136
137/* DM9000A / DM9000B definitions */
138
139#define IMR_LNKCHNG (1<<5)
140#define IMR_UNDERRUN (1<<4)
141
142#define ISR_LNKCHNG (1<<5)
143#define ISR_UNDERRUN (1<<4)
144
134#endif /* _DM9000X_H_ */ 145#endif /* _DM9000X_H_ */
135 146
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 59579b1d8843..cf12b05cd011 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -47,12 +47,6 @@ static const char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation
47 * Macro expands to... 47 * Macro expands to...
48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)} 48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
49 */ 49 */
50#ifdef CONFIG_E1000E_ENABLED
51 #define PCIE(x)
52#else
53 #define PCIE(x) x,
54#endif
55
56static struct pci_device_id e1000_pci_tbl[] = { 50static struct pci_device_id e1000_pci_tbl[] = {
57 INTEL_E1000_ETHERNET_DEVICE(0x1000), 51 INTEL_E1000_ETHERNET_DEVICE(0x1000),
58 INTEL_E1000_ETHERNET_DEVICE(0x1001), 52 INTEL_E1000_ETHERNET_DEVICE(0x1001),
@@ -79,14 +73,6 @@ static struct pci_device_id e1000_pci_tbl[] = {
79 INTEL_E1000_ETHERNET_DEVICE(0x1026), 73 INTEL_E1000_ETHERNET_DEVICE(0x1026),
80 INTEL_E1000_ETHERNET_DEVICE(0x1027), 74 INTEL_E1000_ETHERNET_DEVICE(0x1027),
81 INTEL_E1000_ETHERNET_DEVICE(0x1028), 75 INTEL_E1000_ETHERNET_DEVICE(0x1028),
82PCIE( INTEL_E1000_ETHERNET_DEVICE(0x1049))
83PCIE( INTEL_E1000_ETHERNET_DEVICE(0x104A))
84PCIE( INTEL_E1000_ETHERNET_DEVICE(0x104B))
85PCIE( INTEL_E1000_ETHERNET_DEVICE(0x104C))
86PCIE( INTEL_E1000_ETHERNET_DEVICE(0x104D))
87PCIE( INTEL_E1000_ETHERNET_DEVICE(0x105E))
88PCIE( INTEL_E1000_ETHERNET_DEVICE(0x105F))
89PCIE( INTEL_E1000_ETHERNET_DEVICE(0x1060))
90 INTEL_E1000_ETHERNET_DEVICE(0x1075), 76 INTEL_E1000_ETHERNET_DEVICE(0x1075),
91 INTEL_E1000_ETHERNET_DEVICE(0x1076), 77 INTEL_E1000_ETHERNET_DEVICE(0x1076),
92 INTEL_E1000_ETHERNET_DEVICE(0x1077), 78 INTEL_E1000_ETHERNET_DEVICE(0x1077),
@@ -95,28 +81,9 @@ PCIE( INTEL_E1000_ETHERNET_DEVICE(0x1060))
95 INTEL_E1000_ETHERNET_DEVICE(0x107A), 81 INTEL_E1000_ETHERNET_DEVICE(0x107A),
96 INTEL_E1000_ETHERNET_DEVICE(0x107B), 82 INTEL_E1000_ETHERNET_DEVICE(0x107B),
97 INTEL_E1000_ETHERNET_DEVICE(0x107C), 83 INTEL_E1000_ETHERNET_DEVICE(0x107C),
98PCIE( INTEL_E1000_ETHERNET_DEVICE(0x107D))
99PCIE( INTEL_E1000_ETHERNET_DEVICE(0x107E))
100PCIE( INTEL_E1000_ETHERNET_DEVICE(0x107F))
101 INTEL_E1000_ETHERNET_DEVICE(0x108A), 84 INTEL_E1000_ETHERNET_DEVICE(0x108A),
102PCIE( INTEL_E1000_ETHERNET_DEVICE(0x108B))
103PCIE( INTEL_E1000_ETHERNET_DEVICE(0x108C))
104PCIE( INTEL_E1000_ETHERNET_DEVICE(0x1096))
105PCIE( INTEL_E1000_ETHERNET_DEVICE(0x1098))
106 INTEL_E1000_ETHERNET_DEVICE(0x1099), 85 INTEL_E1000_ETHERNET_DEVICE(0x1099),
107PCIE( INTEL_E1000_ETHERNET_DEVICE(0x109A))
108PCIE( INTEL_E1000_ETHERNET_DEVICE(0x10A4))
109PCIE( INTEL_E1000_ETHERNET_DEVICE(0x10A5))
110 INTEL_E1000_ETHERNET_DEVICE(0x10B5), 86 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
111PCIE( INTEL_E1000_ETHERNET_DEVICE(0x10B9))
112PCIE( INTEL_E1000_ETHERNET_DEVICE(0x10BA))
113PCIE( INTEL_E1000_ETHERNET_DEVICE(0x10BB))
114PCIE( INTEL_E1000_ETHERNET_DEVICE(0x10BC))
115PCIE( INTEL_E1000_ETHERNET_DEVICE(0x10C4))
116PCIE( INTEL_E1000_ETHERNET_DEVICE(0x10C5))
117PCIE( INTEL_E1000_ETHERNET_DEVICE(0x10D5))
118PCIE( INTEL_E1000_ETHERNET_DEVICE(0x10D9))
119PCIE( INTEL_E1000_ETHERNET_DEVICE(0x10DA))
120 /* required last entry */ 87 /* required last entry */
121 {0,} 88 {0,}
122}; 89};
@@ -1505,6 +1472,8 @@ e1000_open(struct net_device *netdev)
1505 1472
1506 e1000_irq_enable(adapter); 1473 e1000_irq_enable(adapter);
1507 1474
1475 netif_start_queue(netdev);
1476
1508 /* fire a link status change interrupt to start the watchdog */ 1477 /* fire a link status change interrupt to start the watchdog */
1509 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC); 1478 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC);
1510 1479
@@ -2510,10 +2479,15 @@ e1000_set_rx_mode(struct net_device *netdev)
2510 2479
2511 if (netdev->flags & IFF_PROMISC) { 2480 if (netdev->flags & IFF_PROMISC) {
2512 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2481 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2513 } else if (netdev->flags & IFF_ALLMULTI) { 2482 rctl &= ~E1000_RCTL_VFE;
2514 rctl |= E1000_RCTL_MPE;
2515 } else { 2483 } else {
2516 rctl &= ~E1000_RCTL_MPE; 2484 if (netdev->flags & IFF_ALLMULTI) {
2485 rctl |= E1000_RCTL_MPE;
2486 } else {
2487 rctl &= ~E1000_RCTL_MPE;
2488 }
2489 if (adapter->hw.mac_type != e1000_ich8lan)
2490 rctl |= E1000_RCTL_VFE;
2517 } 2491 }
2518 2492
2519 uc_ptr = NULL; 2493 uc_ptr = NULL;
@@ -4310,8 +4284,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
4310 if (unlikely(adapter->vlgrp && 4284 if (unlikely(adapter->vlgrp &&
4311 (status & E1000_RXD_STAT_VP))) { 4285 (status & E1000_RXD_STAT_VP))) {
4312 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, 4286 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4313 le16_to_cpu(rx_desc->special) & 4287 le16_to_cpu(rx_desc->special));
4314 E1000_RXD_SPC_VLAN_MASK);
4315 } else { 4288 } else {
4316 netif_receive_skb(skb); 4289 netif_receive_skb(skb);
4317 } 4290 }
@@ -4319,8 +4292,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
4319 if (unlikely(adapter->vlgrp && 4292 if (unlikely(adapter->vlgrp &&
4320 (status & E1000_RXD_STAT_VP))) { 4293 (status & E1000_RXD_STAT_VP))) {
4321 vlan_hwaccel_rx(skb, adapter->vlgrp, 4294 vlan_hwaccel_rx(skb, adapter->vlgrp,
4322 le16_to_cpu(rx_desc->special) & 4295 le16_to_cpu(rx_desc->special));
4323 E1000_RXD_SPC_VLAN_MASK);
4324 } else { 4296 } else {
4325 netif_rx(skb); 4297 netif_rx(skb);
4326 } 4298 }
@@ -4497,16 +4469,14 @@ copydone:
4497#ifdef CONFIG_E1000_NAPI 4469#ifdef CONFIG_E1000_NAPI
4498 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) { 4470 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
4499 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, 4471 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4500 le16_to_cpu(rx_desc->wb.middle.vlan) & 4472 le16_to_cpu(rx_desc->wb.middle.vlan));
4501 E1000_RXD_SPC_VLAN_MASK);
4502 } else { 4473 } else {
4503 netif_receive_skb(skb); 4474 netif_receive_skb(skb);
4504 } 4475 }
4505#else /* CONFIG_E1000_NAPI */ 4476#else /* CONFIG_E1000_NAPI */
4506 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) { 4477 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
4507 vlan_hwaccel_rx(skb, adapter->vlgrp, 4478 vlan_hwaccel_rx(skb, adapter->vlgrp,
4508 le16_to_cpu(rx_desc->wb.middle.vlan) & 4479 le16_to_cpu(rx_desc->wb.middle.vlan));
4509 E1000_RXD_SPC_VLAN_MASK);
4510 } else { 4480 } else {
4511 netif_rx(skb); 4481 netif_rx(skb);
4512 } 4482 }
@@ -4999,7 +4969,6 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4999 if (adapter->hw.mac_type != e1000_ich8lan) { 4969 if (adapter->hw.mac_type != e1000_ich8lan) {
5000 /* enable VLAN receive filtering */ 4970 /* enable VLAN receive filtering */
5001 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4971 rctl = E1000_READ_REG(&adapter->hw, RCTL);
5002 rctl |= E1000_RCTL_VFE;
5003 rctl &= ~E1000_RCTL_CFIEN; 4972 rctl &= ~E1000_RCTL_CFIEN;
5004 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 4973 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
5005 e1000_update_mng_vlan(adapter); 4974 e1000_update_mng_vlan(adapter);
@@ -5011,10 +4980,6 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
5011 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 4980 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
5012 4981
5013 if (adapter->hw.mac_type != e1000_ich8lan) { 4982 if (adapter->hw.mac_type != e1000_ich8lan) {
5014 /* disable VLAN filtering */
5015 rctl = E1000_READ_REG(&adapter->hw, RCTL);
5016 rctl &= ~E1000_RCTL_VFE;
5017 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
5018 if (adapter->mng_vlan_id != 4983 if (adapter->mng_vlan_id !=
5019 (u16)E1000_MNG_VLAN_NONE) { 4984 (u16)E1000_MNG_VLAN_NONE) {
5020 e1000_vlan_rx_kill_vid(netdev, 4985 e1000_vlan_rx_kill_vid(netdev,
@@ -5284,7 +5249,6 @@ e1000_netpoll(struct net_device *netdev)
5284 5249
5285 disable_irq(adapter->pdev->irq); 5250 disable_irq(adapter->pdev->irq);
5286 e1000_intr(adapter->pdev->irq, netdev); 5251 e1000_intr(adapter->pdev->irq, netdev);
5287 e1000_clean_tx_irq(adapter, adapter->tx_ring);
5288#ifndef CONFIG_E1000_NAPI 5252#ifndef CONFIG_E1000_NAPI
5289 adapter->clean_rx(adapter, adapter->rx_ring); 5253 adapter->clean_rx(adapter, adapter->rx_ring);
5290#endif 5254#endif
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h
index d3bc6f8101fa..4a4f62e002b2 100644
--- a/drivers/net/e1000e/e1000.h
+++ b/drivers/net/e1000e/e1000.h
@@ -283,6 +283,10 @@ struct e1000_adapter {
283 unsigned long led_status; 283 unsigned long led_status;
284 284
285 unsigned int flags; 285 unsigned int flags;
286
287 /* for ioport free */
288 int bars;
289 int need_ioport;
286}; 290};
287 291
288struct e1000_info { 292struct e1000_info {
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index 648a87bbf467..869544b8c05c 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -98,8 +98,7 @@ static void e1000_receive_skb(struct e1000_adapter *adapter,
98 98
99 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP)) 99 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
100 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, 100 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
101 le16_to_cpu(vlan) & 101 le16_to_cpu(vlan));
102 E1000_RXD_SPC_VLAN_MASK);
103 else 102 else
104 netif_receive_skb(skb); 103 netif_receive_skb(skb);
105 104
@@ -1793,7 +1792,6 @@ static void e1000_vlan_rx_register(struct net_device *netdev,
1793 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 1792 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
1794 /* enable VLAN receive filtering */ 1793 /* enable VLAN receive filtering */
1795 rctl = er32(RCTL); 1794 rctl = er32(RCTL);
1796 rctl |= E1000_RCTL_VFE;
1797 rctl &= ~E1000_RCTL_CFIEN; 1795 rctl &= ~E1000_RCTL_CFIEN;
1798 ew32(RCTL, rctl); 1796 ew32(RCTL, rctl);
1799 e1000_update_mng_vlan(adapter); 1797 e1000_update_mng_vlan(adapter);
@@ -1805,10 +1803,6 @@ static void e1000_vlan_rx_register(struct net_device *netdev,
1805 ew32(CTRL, ctrl); 1803 ew32(CTRL, ctrl);
1806 1804
1807 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 1805 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
1808 /* disable VLAN filtering */
1809 rctl = er32(RCTL);
1810 rctl &= ~E1000_RCTL_VFE;
1811 ew32(RCTL, rctl);
1812 if (adapter->mng_vlan_id != 1806 if (adapter->mng_vlan_id !=
1813 (u16)E1000_MNG_VLAN_NONE) { 1807 (u16)E1000_MNG_VLAN_NONE) {
1814 e1000_vlan_rx_kill_vid(netdev, 1808 e1000_vlan_rx_kill_vid(netdev,
@@ -2231,11 +2225,16 @@ static void e1000_set_multi(struct net_device *netdev)
2231 2225
2232 if (netdev->flags & IFF_PROMISC) { 2226 if (netdev->flags & IFF_PROMISC) {
2233 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2227 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2234 } else if (netdev->flags & IFF_ALLMULTI) { 2228 rctl &= ~E1000_RCTL_VFE;
2235 rctl |= E1000_RCTL_MPE;
2236 rctl &= ~E1000_RCTL_UPE;
2237 } else { 2229 } else {
2238 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 2230 if (netdev->flags & IFF_ALLMULTI) {
2231 rctl |= E1000_RCTL_MPE;
2232 rctl &= ~E1000_RCTL_UPE;
2233 } else {
2234 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2235 }
2236 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
2237 rctl |= E1000_RCTL_VFE;
2239 } 2238 }
2240 2239
2241 ew32(RCTL, rctl); 2240 ew32(RCTL, rctl);
@@ -2514,7 +2513,7 @@ void e1000e_down(struct e1000_adapter *adapter)
2514 ew32(RCTL, rctl & ~E1000_RCTL_EN); 2513 ew32(RCTL, rctl & ~E1000_RCTL_EN);
2515 /* flush and sleep below */ 2514 /* flush and sleep below */
2516 2515
2517 netif_stop_queue(netdev); 2516 netif_tx_stop_all_queues(netdev);
2518 2517
2519 /* disable transmits in the hardware */ 2518 /* disable transmits in the hardware */
2520 tctl = er32(TCTL); 2519 tctl = er32(TCTL);
@@ -2664,6 +2663,8 @@ static int e1000_open(struct net_device *netdev)
2664 2663
2665 e1000_irq_enable(adapter); 2664 e1000_irq_enable(adapter);
2666 2665
2666 netif_tx_start_all_queues(netdev);
2667
2667 /* fire a link status change interrupt to start the watchdog */ 2668 /* fire a link status change interrupt to start the watchdog */
2668 ew32(ICS, E1000_ICS_LSC); 2669 ew32(ICS, E1000_ICS_LSC);
2669 2670
@@ -3119,7 +3120,7 @@ static void e1000_watchdog_task(struct work_struct *work)
3119 ew32(TCTL, tctl); 3120 ew32(TCTL, tctl);
3120 3121
3121 netif_carrier_on(netdev); 3122 netif_carrier_on(netdev);
3122 netif_wake_queue(netdev); 3123 netif_tx_wake_all_queues(netdev);
3123 3124
3124 if (!test_bit(__E1000_DOWN, &adapter->state)) 3125 if (!test_bit(__E1000_DOWN, &adapter->state))
3125 mod_timer(&adapter->phy_info_timer, 3126 mod_timer(&adapter->phy_info_timer,
@@ -3131,7 +3132,7 @@ static void e1000_watchdog_task(struct work_struct *work)
3131 adapter->link_duplex = 0; 3132 adapter->link_duplex = 0;
3132 ndev_info(netdev, "Link is Down\n"); 3133 ndev_info(netdev, "Link is Down\n");
3133 netif_carrier_off(netdev); 3134 netif_carrier_off(netdev);
3134 netif_stop_queue(netdev); 3135 netif_tx_stop_all_queues(netdev);
3135 if (!test_bit(__E1000_DOWN, &adapter->state)) 3136 if (!test_bit(__E1000_DOWN, &adapter->state))
3136 mod_timer(&adapter->phy_info_timer, 3137 mod_timer(&adapter->phy_info_timer,
3137 round_jiffies(jiffies + 2 * HZ)); 3138 round_jiffies(jiffies + 2 * HZ));
@@ -4003,7 +4004,11 @@ static int e1000_resume(struct pci_dev *pdev)
4003 pci_set_power_state(pdev, PCI_D0); 4004 pci_set_power_state(pdev, PCI_D0);
4004 pci_restore_state(pdev); 4005 pci_restore_state(pdev);
4005 e1000e_disable_l1aspm(pdev); 4006 e1000e_disable_l1aspm(pdev);
4006 err = pci_enable_device(pdev); 4007
4008 if (adapter->need_ioport)
4009 err = pci_enable_device(pdev);
4010 else
4011 err = pci_enable_device_mem(pdev);
4007 if (err) { 4012 if (err) {
4008 dev_err(&pdev->dev, 4013 dev_err(&pdev->dev,
4009 "Cannot enable PCI device from suspend\n"); 4014 "Cannot enable PCI device from suspend\n");
@@ -4104,9 +4109,14 @@ static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
4104 struct net_device *netdev = pci_get_drvdata(pdev); 4109 struct net_device *netdev = pci_get_drvdata(pdev);
4105 struct e1000_adapter *adapter = netdev_priv(netdev); 4110 struct e1000_adapter *adapter = netdev_priv(netdev);
4106 struct e1000_hw *hw = &adapter->hw; 4111 struct e1000_hw *hw = &adapter->hw;
4112 int err;
4107 4113
4108 e1000e_disable_l1aspm(pdev); 4114 e1000e_disable_l1aspm(pdev);
4109 if (pci_enable_device(pdev)) { 4115 if (adapter->need_ioport)
4116 err = pci_enable_device(pdev);
4117 else
4118 err = pci_enable_device_mem(pdev);
4119 if (err) {
4110 dev_err(&pdev->dev, 4120 dev_err(&pdev->dev,
4111 "Cannot re-enable PCI device after reset.\n"); 4121 "Cannot re-enable PCI device after reset.\n");
4112 return PCI_ERS_RESULT_DISCONNECT; 4122 return PCI_ERS_RESULT_DISCONNECT;
@@ -4185,6 +4195,21 @@ static void e1000_print_device_info(struct e1000_adapter *adapter)
4185} 4195}
4186 4196
4187/** 4197/**
4198 * e1000e_is_need_ioport - determine if an adapter needs ioport resources or not
4199 * @pdev: PCI device information struct
4200 *
4201 * Returns true if an adapters needs ioport resources
4202 **/
4203static int e1000e_is_need_ioport(struct pci_dev *pdev)
4204{
4205 switch (pdev->device) {
4206 /* Currently there are no adapters that need ioport resources */
4207 default:
4208 return false;
4209 }
4210}
4211
4212/**
4188 * e1000_probe - Device Initialization Routine 4213 * e1000_probe - Device Initialization Routine
4189 * @pdev: PCI device information struct 4214 * @pdev: PCI device information struct
4190 * @ent: entry in e1000_pci_tbl 4215 * @ent: entry in e1000_pci_tbl
@@ -4209,9 +4234,19 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
4209 int i, err, pci_using_dac; 4234 int i, err, pci_using_dac;
4210 u16 eeprom_data = 0; 4235 u16 eeprom_data = 0;
4211 u16 eeprom_apme_mask = E1000_EEPROM_APME; 4236 u16 eeprom_apme_mask = E1000_EEPROM_APME;
4237 int bars, need_ioport;
4212 4238
4213 e1000e_disable_l1aspm(pdev); 4239 e1000e_disable_l1aspm(pdev);
4214 err = pci_enable_device(pdev); 4240
4241 /* do not allocate ioport bars when not needed */
4242 need_ioport = e1000e_is_need_ioport(pdev);
4243 if (need_ioport) {
4244 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
4245 err = pci_enable_device(pdev);
4246 } else {
4247 bars = pci_select_bars(pdev, IORESOURCE_MEM);
4248 err = pci_enable_device_mem(pdev);
4249 }
4215 if (err) 4250 if (err)
4216 return err; 4251 return err;
4217 4252
@@ -4234,7 +4269,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
4234 } 4269 }
4235 } 4270 }
4236 4271
4237 err = pci_request_regions(pdev, e1000e_driver_name); 4272 err = pci_request_selected_regions(pdev, bars, e1000e_driver_name);
4238 if (err) 4273 if (err)
4239 goto err_pci_reg; 4274 goto err_pci_reg;
4240 4275
@@ -4259,6 +4294,8 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
4259 adapter->hw.adapter = adapter; 4294 adapter->hw.adapter = adapter;
4260 adapter->hw.mac.type = ei->mac; 4295 adapter->hw.mac.type = ei->mac;
4261 adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1; 4296 adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1;
4297 adapter->bars = bars;
4298 adapter->need_ioport = need_ioport;
4262 4299
4263 mmio_start = pci_resource_start(pdev, 0); 4300 mmio_start = pci_resource_start(pdev, 0);
4264 mmio_len = pci_resource_len(pdev, 0); 4301 mmio_len = pci_resource_len(pdev, 0);
@@ -4344,6 +4381,11 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
4344 netdev->features |= NETIF_F_TSO; 4381 netdev->features |= NETIF_F_TSO;
4345 netdev->features |= NETIF_F_TSO6; 4382 netdev->features |= NETIF_F_TSO6;
4346 4383
4384 netdev->vlan_features |= NETIF_F_TSO;
4385 netdev->vlan_features |= NETIF_F_TSO6;
4386 netdev->vlan_features |= NETIF_F_HW_CSUM;
4387 netdev->vlan_features |= NETIF_F_SG;
4388
4347 if (pci_using_dac) 4389 if (pci_using_dac)
4348 netdev->features |= NETIF_F_HIGHDMA; 4390 netdev->features |= NETIF_F_HIGHDMA;
4349 4391
@@ -4464,7 +4506,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
4464 4506
4465 /* tell the stack to leave us alone until e1000_open() is called */ 4507 /* tell the stack to leave us alone until e1000_open() is called */
4466 netif_carrier_off(netdev); 4508 netif_carrier_off(netdev);
4467 netif_stop_queue(netdev); 4509 netif_tx_stop_all_queues(netdev);
4468 4510
4469 strcpy(netdev->name, "eth%d"); 4511 strcpy(netdev->name, "eth%d");
4470 err = register_netdev(netdev); 4512 err = register_netdev(netdev);
@@ -4493,7 +4535,7 @@ err_sw_init:
4493err_ioremap: 4535err_ioremap:
4494 free_netdev(netdev); 4536 free_netdev(netdev);
4495err_alloc_etherdev: 4537err_alloc_etherdev:
4496 pci_release_regions(pdev); 4538 pci_release_selected_regions(pdev, bars);
4497err_pci_reg: 4539err_pci_reg:
4498err_dma: 4540err_dma:
4499 pci_disable_device(pdev); 4541 pci_disable_device(pdev);
@@ -4541,7 +4583,7 @@ static void __devexit e1000_remove(struct pci_dev *pdev)
4541 iounmap(adapter->hw.hw_addr); 4583 iounmap(adapter->hw.hw_addr);
4542 if (adapter->hw.flash_address) 4584 if (adapter->hw.flash_address)
4543 iounmap(adapter->hw.flash_address); 4585 iounmap(adapter->hw.flash_address);
4544 pci_release_regions(pdev); 4586 pci_release_selected_regions(pdev, adapter->bars);
4545 4587
4546 free_netdev(netdev); 4588 free_netdev(netdev);
4547 4589
diff --git a/drivers/net/fealnx.c b/drivers/net/fealnx.c
index 7bb9c728a1d3..3c1364de2b66 100644
--- a/drivers/net/fealnx.c
+++ b/drivers/net/fealnx.c
@@ -90,6 +90,7 @@ static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
90#include <asm/processor.h> /* Processor type for cache alignment. */ 90#include <asm/processor.h> /* Processor type for cache alignment. */
91#include <asm/io.h> 91#include <asm/io.h>
92#include <asm/uaccess.h> 92#include <asm/uaccess.h>
93#include <asm/byteorder.h>
93 94
94/* These identify the driver base version and may not be removed. */ 95/* These identify the driver base version and may not be removed. */
95static char version[] = 96static char version[] =
@@ -861,40 +862,20 @@ static int netdev_open(struct net_device *dev)
861 Wait the specified 50 PCI cycles after a reset by initializing 862 Wait the specified 50 PCI cycles after a reset by initializing
862 Tx and Rx queues and the address filter list. 863 Tx and Rx queues and the address filter list.
863 FIXME (Ueimor): optimistic for alpha + posted writes ? */ 864 FIXME (Ueimor): optimistic for alpha + posted writes ? */
864#if defined(__powerpc__) || defined(__sparc__) 865
865// 89/9/1 modify,
866// np->bcrvalue=0x04 | 0x0x38; /* big-endian, 256 burst length */
867 np->bcrvalue = 0x04 | 0x10; /* big-endian, tx 8 burst length */
868 np->crvalue = 0xe00; /* rx 128 burst length */
869#elif defined(__alpha__) || defined(__x86_64__)
870// 89/9/1 modify,
871// np->bcrvalue=0x38; /* little-endian, 256 burst length */
872 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
873 np->crvalue = 0xe00; /* rx 128 burst length */
874#elif defined(__i386__)
875#if defined(MODULE)
876// 89/9/1 modify,
877// np->bcrvalue=0x38; /* little-endian, 256 burst length */
878 np->bcrvalue = 0x10; /* little-endian, 8 burst length */ 866 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
879 np->crvalue = 0xe00; /* rx 128 burst length */ 867#ifdef __BIG_ENDIAN
880#else 868 np->bcrvalue |= 0x04; /* big-endian */
881 /* When not a module we can work around broken '486 PCI boards. */
882#define x86 boot_cpu_data.x86
883// 89/9/1 modify,
884// np->bcrvalue=(x86 <= 4 ? 0x10 : 0x38);
885 np->bcrvalue = 0x10;
886 np->crvalue = (x86 <= 4 ? 0xa00 : 0xe00);
887 if (x86 <= 4)
888 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting burst "
889 "length to %x.\n", dev->name, (x86 <= 4 ? 0x10 : 0x38));
890#endif 869#endif
891#else 870
892// 89/9/1 modify, 871#if defined(__i386__) && !defined(MODULE)
893// np->bcrvalue=0x38; 872 if (boot_cpu_data.x86 <= 4)
894 np->bcrvalue = 0x10; 873 np->crvalue = 0xa00;
895 np->crvalue = 0xe00; /* rx 128 burst length */ 874 else
896#warning Processor architecture undefined!
897#endif 875#endif
876 np->crvalue = 0xe00; /* rx 128 burst length */
877
878
898// 89/12/29 add, 879// 89/12/29 add,
899// 90/1/16 modify, 880// 90/1/16 modify,
900// np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI; 881// np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
diff --git a/drivers/net/fec_mpc52xx.c b/drivers/net/fec_mpc52xx.c
index 329edd9c08fc..ae9ecb7df22b 100644
--- a/drivers/net/fec_mpc52xx.c
+++ b/drivers/net/fec_mpc52xx.c
@@ -197,7 +197,7 @@ static void mpc52xx_fec_adjust_link(struct net_device *dev)
197 if (priv->link == PHY_DOWN) { 197 if (priv->link == PHY_DOWN) {
198 new_state = 1; 198 new_state = 1;
199 priv->link = phydev->link; 199 priv->link = phydev->link;
200 netif_schedule(dev); 200 netif_tx_schedule_all(dev);
201 netif_carrier_on(dev); 201 netif_carrier_on(dev);
202 netif_start_queue(dev); 202 netif_start_queue(dev);
203 } 203 }
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 20d4fe96a81c..4ed89fa9ae46 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -426,6 +426,7 @@ union ring_type {
426#define NV_PCI_REGSZ_VER1 0x270 426#define NV_PCI_REGSZ_VER1 0x270
427#define NV_PCI_REGSZ_VER2 0x2d4 427#define NV_PCI_REGSZ_VER2 0x2d4
428#define NV_PCI_REGSZ_VER3 0x604 428#define NV_PCI_REGSZ_VER3 0x604
429#define NV_PCI_REGSZ_MAX 0x604
429 430
430/* various timeout delays: all in usec */ 431/* various timeout delays: all in usec */
431#define NV_TXRX_RESET_DELAY 4 432#define NV_TXRX_RESET_DELAY 4
@@ -784,6 +785,9 @@ struct fe_priv {
784 785
785 /* flow control */ 786 /* flow control */
786 u32 pause_flags; 787 u32 pause_flags;
788
789 /* power saved state */
790 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
787}; 791};
788 792
789/* 793/*
@@ -2827,6 +2831,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
2827 */ 2831 */
2828 nv_disable_irq(dev); 2832 nv_disable_irq(dev);
2829 netif_tx_lock_bh(dev); 2833 netif_tx_lock_bh(dev);
2834 netif_addr_lock(dev);
2830 spin_lock(&np->lock); 2835 spin_lock(&np->lock);
2831 /* stop engines */ 2836 /* stop engines */
2832 nv_stop_rxtx(dev); 2837 nv_stop_rxtx(dev);
@@ -2851,6 +2856,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
2851 /* restart rx engine */ 2856 /* restart rx engine */
2852 nv_start_rxtx(dev); 2857 nv_start_rxtx(dev);
2853 spin_unlock(&np->lock); 2858 spin_unlock(&np->lock);
2859 netif_addr_unlock(dev);
2854 netif_tx_unlock_bh(dev); 2860 netif_tx_unlock_bh(dev);
2855 nv_enable_irq(dev); 2861 nv_enable_irq(dev);
2856 } 2862 }
@@ -2887,6 +2893,7 @@ static int nv_set_mac_address(struct net_device *dev, void *addr)
2887 2893
2888 if (netif_running(dev)) { 2894 if (netif_running(dev)) {
2889 netif_tx_lock_bh(dev); 2895 netif_tx_lock_bh(dev);
2896 netif_addr_lock(dev);
2890 spin_lock_irq(&np->lock); 2897 spin_lock_irq(&np->lock);
2891 2898
2892 /* stop rx engine */ 2899 /* stop rx engine */
@@ -2898,6 +2905,7 @@ static int nv_set_mac_address(struct net_device *dev, void *addr)
2898 /* restart rx engine */ 2905 /* restart rx engine */
2899 nv_start_rx(dev); 2906 nv_start_rx(dev);
2900 spin_unlock_irq(&np->lock); 2907 spin_unlock_irq(&np->lock);
2908 netif_addr_unlock(dev);
2901 netif_tx_unlock_bh(dev); 2909 netif_tx_unlock_bh(dev);
2902 } else { 2910 } else {
2903 nv_copy_mac_to_hw(dev); 2911 nv_copy_mac_to_hw(dev);
@@ -3967,6 +3975,7 @@ static void nv_do_nic_poll(unsigned long data)
3967 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n"); 3975 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3968 if (netif_running(dev)) { 3976 if (netif_running(dev)) {
3969 netif_tx_lock_bh(dev); 3977 netif_tx_lock_bh(dev);
3978 netif_addr_lock(dev);
3970 spin_lock(&np->lock); 3979 spin_lock(&np->lock);
3971 /* stop engines */ 3980 /* stop engines */
3972 nv_stop_rxtx(dev); 3981 nv_stop_rxtx(dev);
@@ -3991,6 +4000,7 @@ static void nv_do_nic_poll(unsigned long data)
3991 /* restart rx engine */ 4000 /* restart rx engine */
3992 nv_start_rxtx(dev); 4001 nv_start_rxtx(dev);
3993 spin_unlock(&np->lock); 4002 spin_unlock(&np->lock);
4003 netif_addr_unlock(dev);
3994 netif_tx_unlock_bh(dev); 4004 netif_tx_unlock_bh(dev);
3995 } 4005 }
3996 } 4006 }
@@ -4198,6 +4208,7 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4198 4208
4199 nv_disable_irq(dev); 4209 nv_disable_irq(dev);
4200 netif_tx_lock_bh(dev); 4210 netif_tx_lock_bh(dev);
4211 netif_addr_lock(dev);
4201 /* with plain spinlock lockdep complains */ 4212 /* with plain spinlock lockdep complains */
4202 spin_lock_irqsave(&np->lock, flags); 4213 spin_lock_irqsave(&np->lock, flags);
4203 /* stop engines */ 4214 /* stop engines */
@@ -4211,6 +4222,7 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4211 */ 4222 */
4212 nv_stop_rxtx(dev); 4223 nv_stop_rxtx(dev);
4213 spin_unlock_irqrestore(&np->lock, flags); 4224 spin_unlock_irqrestore(&np->lock, flags);
4225 netif_addr_unlock(dev);
4214 netif_tx_unlock_bh(dev); 4226 netif_tx_unlock_bh(dev);
4215 } 4227 }
4216 4228
@@ -4356,10 +4368,12 @@ static int nv_nway_reset(struct net_device *dev)
4356 if (netif_running(dev)) { 4368 if (netif_running(dev)) {
4357 nv_disable_irq(dev); 4369 nv_disable_irq(dev);
4358 netif_tx_lock_bh(dev); 4370 netif_tx_lock_bh(dev);
4371 netif_addr_lock(dev);
4359 spin_lock(&np->lock); 4372 spin_lock(&np->lock);
4360 /* stop engines */ 4373 /* stop engines */
4361 nv_stop_rxtx(dev); 4374 nv_stop_rxtx(dev);
4362 spin_unlock(&np->lock); 4375 spin_unlock(&np->lock);
4376 netif_addr_unlock(dev);
4363 netif_tx_unlock_bh(dev); 4377 netif_tx_unlock_bh(dev);
4364 printk(KERN_INFO "%s: link down.\n", dev->name); 4378 printk(KERN_INFO "%s: link down.\n", dev->name);
4365 } 4379 }
@@ -4467,6 +4481,7 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri
4467 if (netif_running(dev)) { 4481 if (netif_running(dev)) {
4468 nv_disable_irq(dev); 4482 nv_disable_irq(dev);
4469 netif_tx_lock_bh(dev); 4483 netif_tx_lock_bh(dev);
4484 netif_addr_lock(dev);
4470 spin_lock(&np->lock); 4485 spin_lock(&np->lock);
4471 /* stop engines */ 4486 /* stop engines */
4472 nv_stop_rxtx(dev); 4487 nv_stop_rxtx(dev);
@@ -4515,6 +4530,7 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri
4515 /* restart engines */ 4530 /* restart engines */
4516 nv_start_rxtx(dev); 4531 nv_start_rxtx(dev);
4517 spin_unlock(&np->lock); 4532 spin_unlock(&np->lock);
4533 netif_addr_unlock(dev);
4518 netif_tx_unlock_bh(dev); 4534 netif_tx_unlock_bh(dev);
4519 nv_enable_irq(dev); 4535 nv_enable_irq(dev);
4520 } 4536 }
@@ -4552,10 +4568,12 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam*
4552 if (netif_running(dev)) { 4568 if (netif_running(dev)) {
4553 nv_disable_irq(dev); 4569 nv_disable_irq(dev);
4554 netif_tx_lock_bh(dev); 4570 netif_tx_lock_bh(dev);
4571 netif_addr_lock(dev);
4555 spin_lock(&np->lock); 4572 spin_lock(&np->lock);
4556 /* stop engines */ 4573 /* stop engines */
4557 nv_stop_rxtx(dev); 4574 nv_stop_rxtx(dev);
4558 spin_unlock(&np->lock); 4575 spin_unlock(&np->lock);
4576 netif_addr_unlock(dev);
4559 netif_tx_unlock_bh(dev); 4577 netif_tx_unlock_bh(dev);
4560 } 4578 }
4561 4579
@@ -4942,6 +4960,7 @@ static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64
4942 napi_disable(&np->napi); 4960 napi_disable(&np->napi);
4943#endif 4961#endif
4944 netif_tx_lock_bh(dev); 4962 netif_tx_lock_bh(dev);
4963 netif_addr_lock(dev);
4945 spin_lock_irq(&np->lock); 4964 spin_lock_irq(&np->lock);
4946 nv_disable_hw_interrupts(dev, np->irqmask); 4965 nv_disable_hw_interrupts(dev, np->irqmask);
4947 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { 4966 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
@@ -4955,6 +4974,7 @@ static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64
4955 /* drain rx queue */ 4974 /* drain rx queue */
4956 nv_drain_rxtx(dev); 4975 nv_drain_rxtx(dev);
4957 spin_unlock_irq(&np->lock); 4976 spin_unlock_irq(&np->lock);
4977 netif_addr_unlock(dev);
4958 netif_tx_unlock_bh(dev); 4978 netif_tx_unlock_bh(dev);
4959 } 4979 }
4960 4980
@@ -5566,6 +5586,11 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5566 /* set mac address */ 5586 /* set mac address */
5567 nv_copy_mac_to_hw(dev); 5587 nv_copy_mac_to_hw(dev);
5568 5588
5589 /* Workaround current PCI init glitch: wakeup bits aren't
5590 * being set from PCI PM capability.
5591 */
5592 device_init_wakeup(&pci_dev->dev, 1);
5593
5569 /* disable WOL */ 5594 /* disable WOL */
5570 writel(0, base + NvRegWakeUpFlags); 5595 writel(0, base + NvRegWakeUpFlags);
5571 np->wolenabled = 0; 5596 np->wolenabled = 0;
@@ -5816,50 +5841,66 @@ static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5816{ 5841{
5817 struct net_device *dev = pci_get_drvdata(pdev); 5842 struct net_device *dev = pci_get_drvdata(pdev);
5818 struct fe_priv *np = netdev_priv(dev); 5843 struct fe_priv *np = netdev_priv(dev);
5844 u8 __iomem *base = get_hwbase(dev);
5845 int i;
5819 5846
5820 if (!netif_running(dev)) 5847 if (netif_running(dev)) {
5821 goto out; 5848 // Gross.
5822 5849 nv_close(dev);
5850 }
5823 netif_device_detach(dev); 5851 netif_device_detach(dev);
5824 5852
5825 // Gross. 5853 /* save non-pci configuration space */
5826 nv_close(dev); 5854 for (i = 0;i <= np->register_size/sizeof(u32); i++)
5855 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5827 5856
5828 pci_save_state(pdev); 5857 pci_save_state(pdev);
5829 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled); 5858 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5859 pci_disable_device(pdev);
5830 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 5860 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5831out:
5832 return 0; 5861 return 0;
5833} 5862}
5834 5863
5835static int nv_resume(struct pci_dev *pdev) 5864static int nv_resume(struct pci_dev *pdev)
5836{ 5865{
5837 struct net_device *dev = pci_get_drvdata(pdev); 5866 struct net_device *dev = pci_get_drvdata(pdev);
5867 struct fe_priv *np = netdev_priv(dev);
5838 u8 __iomem *base = get_hwbase(dev); 5868 u8 __iomem *base = get_hwbase(dev);
5839 int rc = 0; 5869 int i, rc = 0;
5840 u32 txreg;
5841
5842 if (!netif_running(dev))
5843 goto out;
5844
5845 netif_device_attach(dev);
5846 5870
5847 pci_set_power_state(pdev, PCI_D0); 5871 pci_set_power_state(pdev, PCI_D0);
5848 pci_restore_state(pdev); 5872 pci_restore_state(pdev);
5873 /* ack any pending wake events, disable PME */
5849 pci_enable_wake(pdev, PCI_D0, 0); 5874 pci_enable_wake(pdev, PCI_D0, 0);
5850 5875
5851 /* restore mac address reverse flag */ 5876 /* restore non-pci configuration space */
5852 txreg = readl(base + NvRegTransmitPoll); 5877 for (i = 0;i <= np->register_size/sizeof(u32); i++)
5853 txreg |= NVREG_TRANSMITPOLL_MAC_ADDR_REV; 5878 writel(np->saved_config_space[i], base+i*sizeof(u32));
5854 writel(txreg, base + NvRegTransmitPoll);
5855 5879
5856 rc = nv_open(dev); 5880 netif_device_attach(dev);
5857 nv_set_multicast(dev); 5881 if (netif_running(dev)) {
5858out: 5882 rc = nv_open(dev);
5883 nv_set_multicast(dev);
5884 }
5859 return rc; 5885 return rc;
5860} 5886}
5887
5888static void nv_shutdown(struct pci_dev *pdev)
5889{
5890 struct net_device *dev = pci_get_drvdata(pdev);
5891 struct fe_priv *np = netdev_priv(dev);
5892
5893 if (netif_running(dev))
5894 nv_close(dev);
5895
5896 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
5897 pci_enable_wake(pdev, PCI_D3cold, np->wolenabled);
5898 pci_disable_device(pdev);
5899 pci_set_power_state(pdev, PCI_D3hot);
5900}
5861#else 5901#else
5862#define nv_suspend NULL 5902#define nv_suspend NULL
5903#define nv_shutdown NULL
5863#define nv_resume NULL 5904#define nv_resume NULL
5864#endif /* CONFIG_PM */ 5905#endif /* CONFIG_PM */
5865 5906
@@ -6030,6 +6071,7 @@ static struct pci_driver driver = {
6030 .remove = __devexit_p(nv_remove), 6071 .remove = __devexit_p(nv_remove),
6031 .suspend = nv_suspend, 6072 .suspend = nv_suspend,
6032 .resume = nv_resume, 6073 .resume = nv_resume,
6074 .shutdown = nv_shutdown,
6033}; 6075};
6034 6076
6035static int __init init_nic(void) 6077static int __init init_nic(void)
diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c
index 352574a3f056..445763e5648e 100644
--- a/drivers/net/fs_enet/fs_enet-main.c
+++ b/drivers/net/fs_enet/fs_enet-main.c
@@ -43,6 +43,7 @@
43#include <asm/uaccess.h> 43#include <asm/uaccess.h>
44 44
45#ifdef CONFIG_PPC_CPM_NEW_BINDING 45#ifdef CONFIG_PPC_CPM_NEW_BINDING
46#include <linux/of_gpio.h>
46#include <linux/of_platform.h> 47#include <linux/of_platform.h>
47#endif 48#endif
48 49
@@ -737,7 +738,7 @@ static void generic_adjust_link(struct net_device *dev)
737 if (!fep->oldlink) { 738 if (!fep->oldlink) {
738 new_state = 1; 739 new_state = 1;
739 fep->oldlink = 1; 740 fep->oldlink = 1;
740 netif_schedule(dev); 741 netif_tx_schedule_all(dev);
741 netif_carrier_on(dev); 742 netif_carrier_on(dev);
742 netif_start_queue(dev); 743 netif_start_queue(dev);
743 } 744 }
@@ -1172,8 +1173,7 @@ static int __devinit find_phy(struct device_node *np,
1172 struct fs_platform_info *fpi) 1173 struct fs_platform_info *fpi)
1173{ 1174{
1174 struct device_node *phynode, *mdionode; 1175 struct device_node *phynode, *mdionode;
1175 struct resource res; 1176 int ret = 0, len, bus_id;
1176 int ret = 0, len;
1177 const u32 *data; 1177 const u32 *data;
1178 1178
1179 data = of_get_property(np, "fixed-link", NULL); 1179 data = of_get_property(np, "fixed-link", NULL);
@@ -1190,19 +1190,28 @@ static int __devinit find_phy(struct device_node *np,
1190 if (!phynode) 1190 if (!phynode)
1191 return -EINVAL; 1191 return -EINVAL;
1192 1192
1193 mdionode = of_get_parent(phynode); 1193 data = of_get_property(phynode, "reg", &len);
1194 if (!mdionode) 1194 if (!data || len != 4) {
1195 ret = -EINVAL;
1195 goto out_put_phy; 1196 goto out_put_phy;
1197 }
1196 1198
1197 ret = of_address_to_resource(mdionode, 0, &res); 1199 mdionode = of_get_parent(phynode);
1198 if (ret) 1200 if (!mdionode) {
1199 goto out_put_mdio; 1201 ret = -EINVAL;
1202 goto out_put_phy;
1203 }
1200 1204
1201 data = of_get_property(phynode, "reg", &len); 1205 bus_id = of_get_gpio(mdionode, 0);
1202 if (!data || len != 4) 1206 if (bus_id < 0) {
1203 goto out_put_mdio; 1207 struct resource res;
1208 ret = of_address_to_resource(mdionode, 0, &res);
1209 if (ret)
1210 goto out_put_mdio;
1211 bus_id = res.start;
1212 }
1204 1213
1205 snprintf(fpi->bus_id, 16, "%x:%02x", res.start, *data); 1214 snprintf(fpi->bus_id, 16, "%x:%02x", bus_id, *data);
1206 1215
1207out_put_mdio: 1216out_put_mdio:
1208 of_node_put(mdionode); 1217 of_node_put(mdionode);
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
index 25bdd0832df5..45a63172852f 100644
--- a/drivers/net/gianfar.c
+++ b/drivers/net/gianfar.c
@@ -44,8 +44,7 @@
44 * happen immediately, but will wait until either a set number 44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the 45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and 46 * interrupt handler will signal there is work to be done, and
47 * exit. Without NAPI, the packet(s) will be handled 47 * exit. This method will start at the last known empty
48 * immediately. Both methods will start at the last known empty
49 * descriptor, and process every subsequent descriptor until there 48 * descriptor, and process every subsequent descriptor until there
50 * are none left with data (NAPI will stop after a set number of 49 * are none left with data (NAPI will stop after a set number of
51 * packets to give time to other tasks, but will eventually 50 * packets to give time to other tasks, but will eventually
@@ -101,12 +100,6 @@
101#undef BRIEF_GFAR_ERRORS 100#undef BRIEF_GFAR_ERRORS
102#undef VERBOSE_GFAR_ERRORS 101#undef VERBOSE_GFAR_ERRORS
103 102
104#ifdef CONFIG_GFAR_NAPI
105#define RECEIVE(x) netif_receive_skb(x)
106#else
107#define RECEIVE(x) netif_rx(x)
108#endif
109
110const char gfar_driver_name[] = "Gianfar Ethernet"; 103const char gfar_driver_name[] = "Gianfar Ethernet";
111const char gfar_driver_version[] = "1.3"; 104const char gfar_driver_version[] = "1.3";
112 105
@@ -131,9 +124,7 @@ static void free_skb_resources(struct gfar_private *priv);
131static void gfar_set_multi(struct net_device *dev); 124static void gfar_set_multi(struct net_device *dev);
132static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); 125static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
133static void gfar_configure_serdes(struct net_device *dev); 126static void gfar_configure_serdes(struct net_device *dev);
134#ifdef CONFIG_GFAR_NAPI
135static int gfar_poll(struct napi_struct *napi, int budget); 127static int gfar_poll(struct napi_struct *napi, int budget);
136#endif
137#ifdef CONFIG_NET_POLL_CONTROLLER 128#ifdef CONFIG_NET_POLL_CONTROLLER
138static void gfar_netpoll(struct net_device *dev); 129static void gfar_netpoll(struct net_device *dev);
139#endif 130#endif
@@ -260,9 +251,7 @@ static int gfar_probe(struct platform_device *pdev)
260 dev->hard_start_xmit = gfar_start_xmit; 251 dev->hard_start_xmit = gfar_start_xmit;
261 dev->tx_timeout = gfar_timeout; 252 dev->tx_timeout = gfar_timeout;
262 dev->watchdog_timeo = TX_TIMEOUT; 253 dev->watchdog_timeo = TX_TIMEOUT;
263#ifdef CONFIG_GFAR_NAPI
264 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT); 254 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
265#endif
266#ifdef CONFIG_NET_POLL_CONTROLLER 255#ifdef CONFIG_NET_POLL_CONTROLLER
267 dev->poll_controller = gfar_netpoll; 256 dev->poll_controller = gfar_netpoll;
268#endif 257#endif
@@ -363,11 +352,7 @@ static int gfar_probe(struct platform_device *pdev)
363 352
364 /* Even more device info helps when determining which kernel */ 353 /* Even more device info helps when determining which kernel */
365 /* provided which set of benchmarks. */ 354 /* provided which set of benchmarks. */
366#ifdef CONFIG_GFAR_NAPI
367 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name); 355 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
368#else
369 printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
370#endif
371 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n", 356 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
372 dev->name, priv->rx_ring_size, priv->tx_ring_size); 357 dev->name, priv->rx_ring_size, priv->tx_ring_size);
373 358
@@ -928,7 +913,7 @@ rx_irq_fail:
928tx_irq_fail: 913tx_irq_fail:
929 free_irq(priv->interruptError, dev); 914 free_irq(priv->interruptError, dev);
930err_irq_fail: 915err_irq_fail:
931err_rxalloc_fail: 916err_rxalloc_fail:
932rx_skb_fail: 917rx_skb_fail:
933 free_skb_resources(priv); 918 free_skb_resources(priv);
934tx_skb_fail: 919tx_skb_fail:
@@ -945,14 +930,10 @@ tx_skb_fail:
945/* Returns 0 for success. */ 930/* Returns 0 for success. */
946static int gfar_enet_open(struct net_device *dev) 931static int gfar_enet_open(struct net_device *dev)
947{ 932{
948#ifdef CONFIG_GFAR_NAPI
949 struct gfar_private *priv = netdev_priv(dev); 933 struct gfar_private *priv = netdev_priv(dev);
950#endif
951 int err; 934 int err;
952 935
953#ifdef CONFIG_GFAR_NAPI
954 napi_enable(&priv->napi); 936 napi_enable(&priv->napi);
955#endif
956 937
957 /* Initialize a bunch of registers */ 938 /* Initialize a bunch of registers */
958 init_registers(dev); 939 init_registers(dev);
@@ -962,17 +943,13 @@ static int gfar_enet_open(struct net_device *dev)
962 err = init_phy(dev); 943 err = init_phy(dev);
963 944
964 if(err) { 945 if(err) {
965#ifdef CONFIG_GFAR_NAPI
966 napi_disable(&priv->napi); 946 napi_disable(&priv->napi);
967#endif
968 return err; 947 return err;
969 } 948 }
970 949
971 err = startup_gfar(dev); 950 err = startup_gfar(dev);
972 if (err) { 951 if (err) {
973#ifdef CONFIG_GFAR_NAPI
974 napi_disable(&priv->napi); 952 napi_disable(&priv->napi);
975#endif
976 return err; 953 return err;
977 } 954 }
978 955
@@ -1128,9 +1105,7 @@ static int gfar_close(struct net_device *dev)
1128{ 1105{
1129 struct gfar_private *priv = netdev_priv(dev); 1106 struct gfar_private *priv = netdev_priv(dev);
1130 1107
1131#ifdef CONFIG_GFAR_NAPI
1132 napi_disable(&priv->napi); 1108 napi_disable(&priv->napi);
1133#endif
1134 1109
1135 stop_gfar(dev); 1110 stop_gfar(dev);
1136 1111
@@ -1259,7 +1234,7 @@ static void gfar_timeout(struct net_device *dev)
1259 startup_gfar(dev); 1234 startup_gfar(dev);
1260 } 1235 }
1261 1236
1262 netif_schedule(dev); 1237 netif_tx_schedule_all(dev);
1263} 1238}
1264 1239
1265/* Interrupt Handler for Transmit complete */ 1240/* Interrupt Handler for Transmit complete */
@@ -1427,14 +1402,9 @@ irqreturn_t gfar_receive(int irq, void *dev_id)
1427{ 1402{
1428 struct net_device *dev = (struct net_device *) dev_id; 1403 struct net_device *dev = (struct net_device *) dev_id;
1429 struct gfar_private *priv = netdev_priv(dev); 1404 struct gfar_private *priv = netdev_priv(dev);
1430#ifdef CONFIG_GFAR_NAPI
1431 u32 tempval; 1405 u32 tempval;
1432#else
1433 unsigned long flags;
1434#endif
1435 1406
1436 /* support NAPI */ 1407 /* support NAPI */
1437#ifdef CONFIG_GFAR_NAPI
1438 /* Clear IEVENT, so interrupts aren't called again 1408 /* Clear IEVENT, so interrupts aren't called again
1439 * because of the packets that have already arrived */ 1409 * because of the packets that have already arrived */
1440 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK); 1410 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
@@ -1451,38 +1421,10 @@ irqreturn_t gfar_receive(int irq, void *dev_id)
1451 dev->name, gfar_read(&priv->regs->ievent), 1421 dev->name, gfar_read(&priv->regs->ievent),
1452 gfar_read(&priv->regs->imask)); 1422 gfar_read(&priv->regs->imask));
1453 } 1423 }
1454#else
1455 /* Clear IEVENT, so rx interrupt isn't called again
1456 * because of this interrupt */
1457 gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1458
1459 spin_lock_irqsave(&priv->rxlock, flags);
1460 gfar_clean_rx_ring(dev, priv->rx_ring_size);
1461
1462 /* If we are coalescing interrupts, update the timer */
1463 /* Otherwise, clear it */
1464 if (likely(priv->rxcoalescing)) {
1465 gfar_write(&priv->regs->rxic, 0);
1466 gfar_write(&priv->regs->rxic,
1467 mk_ic_value(priv->rxcount, priv->rxtime));
1468 }
1469
1470 spin_unlock_irqrestore(&priv->rxlock, flags);
1471#endif
1472 1424
1473 return IRQ_HANDLED; 1425 return IRQ_HANDLED;
1474} 1426}
1475 1427
1476static inline int gfar_rx_vlan(struct sk_buff *skb,
1477 struct vlan_group *vlgrp, unsigned short vlctl)
1478{
1479#ifdef CONFIG_GFAR_NAPI
1480 return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1481#else
1482 return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1483#endif
1484}
1485
1486static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) 1428static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1487{ 1429{
1488 /* If valid headers were found, and valid sums 1430 /* If valid headers were found, and valid sums
@@ -1539,10 +1481,11 @@ static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1539 skb->protocol = eth_type_trans(skb, dev); 1481 skb->protocol = eth_type_trans(skb, dev);
1540 1482
1541 /* Send the packet up the stack */ 1483 /* Send the packet up the stack */
1542 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) 1484 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1543 ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl); 1485 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1544 else 1486 fcb->vlctl);
1545 ret = RECEIVE(skb); 1487 } else
1488 ret = netif_receive_skb(skb);
1546 1489
1547 if (NET_RX_DROP == ret) 1490 if (NET_RX_DROP == ret)
1548 priv->extra_stats.kernel_dropped++; 1491 priv->extra_stats.kernel_dropped++;
@@ -1629,7 +1572,6 @@ int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1629 return howmany; 1572 return howmany;
1630} 1573}
1631 1574
1632#ifdef CONFIG_GFAR_NAPI
1633static int gfar_poll(struct napi_struct *napi, int budget) 1575static int gfar_poll(struct napi_struct *napi, int budget)
1634{ 1576{
1635 struct gfar_private *priv = container_of(napi, struct gfar_private, napi); 1577 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
@@ -1664,7 +1606,6 @@ static int gfar_poll(struct napi_struct *napi, int budget)
1664 1606
1665 return howmany; 1607 return howmany;
1666} 1608}
1667#endif
1668 1609
1669#ifdef CONFIG_NET_POLL_CONTROLLER 1610#ifdef CONFIG_NET_POLL_CONTROLLER
1670/* 1611/*
@@ -1784,7 +1725,7 @@ static void adjust_link(struct net_device *dev)
1784 if (!priv->oldlink) { 1725 if (!priv->oldlink) {
1785 new_state = 1; 1726 new_state = 1;
1786 priv->oldlink = 1; 1727 priv->oldlink = 1;
1787 netif_schedule(dev); 1728 netif_tx_schedule_all(dev);
1788 } 1729 }
1789 } else if (priv->oldlink) { 1730 } else if (priv->oldlink) {
1790 new_state = 1; 1731 new_state = 1;
@@ -2003,11 +1944,6 @@ static irqreturn_t gfar_error(int irq, void *dev_id)
2003 1944
2004 gfar_receive(irq, dev_id); 1945 gfar_receive(irq, dev_id);
2005 1946
2006#ifndef CONFIG_GFAR_NAPI
2007 /* Clear the halt bit in RSTAT */
2008 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
2009#endif
2010
2011 if (netif_msg_rx_err(priv)) 1947 if (netif_msg_rx_err(priv))
2012 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n", 1948 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2013 dev->name, gfar_read(&priv->regs->rstat)); 1949 dev->name, gfar_read(&priv->regs->rstat));
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h
index 27f37c81e52c..bead71cb2b16 100644
--- a/drivers/net/gianfar.h
+++ b/drivers/net/gianfar.h
@@ -77,13 +77,8 @@ extern const char gfar_driver_name[];
77extern const char gfar_driver_version[]; 77extern const char gfar_driver_version[];
78 78
79/* These need to be powers of 2 for this driver */ 79/* These need to be powers of 2 for this driver */
80#ifdef CONFIG_GFAR_NAPI
81#define DEFAULT_TX_RING_SIZE 256 80#define DEFAULT_TX_RING_SIZE 256
82#define DEFAULT_RX_RING_SIZE 256 81#define DEFAULT_RX_RING_SIZE 256
83#else
84#define DEFAULT_TX_RING_SIZE 64
85#define DEFAULT_RX_RING_SIZE 64
86#endif
87 82
88#define GFAR_RX_MAX_RING_SIZE 256 83#define GFAR_RX_MAX_RING_SIZE 256
89#define GFAR_TX_MAX_RING_SIZE 256 84#define GFAR_TX_MAX_RING_SIZE 256
@@ -128,14 +123,8 @@ extern const char gfar_driver_version[];
128 123
129#define DEFAULT_RXTIME 21 124#define DEFAULT_RXTIME 21
130 125
131/* Non NAPI Case */
132#ifndef CONFIG_GFAR_NAPI
133#define DEFAULT_RX_COALESCE 1
134#define DEFAULT_RXCOUNT 16
135#else
136#define DEFAULT_RX_COALESCE 0 126#define DEFAULT_RX_COALESCE 0
137#define DEFAULT_RXCOUNT 0 127#define DEFAULT_RXCOUNT 0
138#endif /* CONFIG_GFAR_NAPI */
139 128
140#define MIIMCFG_INIT_VALUE 0x00000007 129#define MIIMCFG_INIT_VALUE 0x00000007
141#define MIIMCFG_RESET 0x80000000 130#define MIIMCFG_RESET 0x80000000
diff --git a/drivers/net/hamachi.c b/drivers/net/hamachi.c
index e5c2380f50ca..3199526bcecb 100644
--- a/drivers/net/hamachi.c
+++ b/drivers/net/hamachi.c
@@ -1140,11 +1140,11 @@ static void hamachi_tx_timeout(struct net_device *dev)
1140 } 1140 }
1141 /* Fill in the Rx buffers. Handle allocation failure gracefully. */ 1141 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1142 for (i = 0; i < RX_RING_SIZE; i++) { 1142 for (i = 0; i < RX_RING_SIZE; i++) {
1143 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz); 1143 struct sk_buff *skb = netdev_alloc_skb(dev, hmp->rx_buf_sz);
1144 hmp->rx_skbuff[i] = skb; 1144 hmp->rx_skbuff[i] = skb;
1145 if (skb == NULL) 1145 if (skb == NULL)
1146 break; 1146 break;
1147 skb->dev = dev; /* Mark as being used by this device. */ 1147
1148 skb_reserve(skb, 2); /* 16 byte align the IP header. */ 1148 skb_reserve(skb, 2); /* 16 byte align the IP header. */
1149 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev, 1149 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
1150 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE)); 1150 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
@@ -1178,14 +1178,6 @@ static void hamachi_init_ring(struct net_device *dev)
1178 hmp->cur_rx = hmp->cur_tx = 0; 1178 hmp->cur_rx = hmp->cur_tx = 0;
1179 hmp->dirty_rx = hmp->dirty_tx = 0; 1179 hmp->dirty_rx = hmp->dirty_tx = 0;
1180 1180
1181#if 0
1182 /* This is wrong. I'm not sure what the original plan was, but this
1183 * is wrong. An MTU of 1 gets you a buffer of 1536, while an MTU
1184 * of 1501 gets a buffer of 1533? -KDU
1185 */
1186 hmp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1187#endif
1188 /* My attempt at a reasonable correction */
1189 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1181 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1190 * card needs room to do 8 byte alignment, +2 so we can reserve 1182 * card needs room to do 8 byte alignment, +2 so we can reserve
1191 * the first 2 bytes, and +16 gets room for the status word from the 1183 * the first 2 bytes, and +16 gets room for the status word from the
diff --git a/drivers/net/hamradio/6pack.c b/drivers/net/hamradio/6pack.c
index 19dd0a61749c..0f501d2ca935 100644
--- a/drivers/net/hamradio/6pack.c
+++ b/drivers/net/hamradio/6pack.c
@@ -99,9 +99,6 @@ struct sixpack {
99 unsigned int rx_count; 99 unsigned int rx_count;
100 unsigned int rx_count_cooked; 100 unsigned int rx_count_cooked;
101 101
102 /* 6pack interface statistics. */
103 struct net_device_stats stats;
104
105 int mtu; /* Our mtu (to spot changes!) */ 102 int mtu; /* Our mtu (to spot changes!) */
106 int buffsize; /* Max buffers sizes */ 103 int buffsize; /* Max buffers sizes */
107 104
@@ -237,7 +234,7 @@ static void sp_encaps(struct sixpack *sp, unsigned char *icp, int len)
237 return; 234 return;
238 235
239out_drop: 236out_drop:
240 sp->stats.tx_dropped++; 237 sp->dev->stats.tx_dropped++;
241 netif_start_queue(sp->dev); 238 netif_start_queue(sp->dev);
242 if (net_ratelimit()) 239 if (net_ratelimit())
243 printk(KERN_DEBUG "%s: %s - dropped.\n", sp->dev->name, msg); 240 printk(KERN_DEBUG "%s: %s - dropped.\n", sp->dev->name, msg);
@@ -252,7 +249,7 @@ static int sp_xmit(struct sk_buff *skb, struct net_device *dev)
252 spin_lock_bh(&sp->lock); 249 spin_lock_bh(&sp->lock);
253 /* We were not busy, so we are now... :-) */ 250 /* We were not busy, so we are now... :-) */
254 netif_stop_queue(dev); 251 netif_stop_queue(dev);
255 sp->stats.tx_bytes += skb->len; 252 dev->stats.tx_bytes += skb->len;
256 sp_encaps(sp, skb->data, skb->len); 253 sp_encaps(sp, skb->data, skb->len);
257 spin_unlock_bh(&sp->lock); 254 spin_unlock_bh(&sp->lock);
258 255
@@ -298,18 +295,14 @@ static int sp_header(struct sk_buff *skb, struct net_device *dev,
298 return 0; 295 return 0;
299} 296}
300 297
301static struct net_device_stats *sp_get_stats(struct net_device *dev)
302{
303 struct sixpack *sp = netdev_priv(dev);
304 return &sp->stats;
305}
306
307static int sp_set_mac_address(struct net_device *dev, void *addr) 298static int sp_set_mac_address(struct net_device *dev, void *addr)
308{ 299{
309 struct sockaddr_ax25 *sa = addr; 300 struct sockaddr_ax25 *sa = addr;
310 301
311 netif_tx_lock_bh(dev); 302 netif_tx_lock_bh(dev);
303 netif_addr_lock(dev);
312 memcpy(dev->dev_addr, &sa->sax25_call, AX25_ADDR_LEN); 304 memcpy(dev->dev_addr, &sa->sax25_call, AX25_ADDR_LEN);
305 netif_addr_unlock(dev);
313 netif_tx_unlock_bh(dev); 306 netif_tx_unlock_bh(dev);
314 307
315 return 0; 308 return 0;
@@ -338,7 +331,6 @@ static void sp_setup(struct net_device *dev)
338 dev->destructor = free_netdev; 331 dev->destructor = free_netdev;
339 dev->stop = sp_close; 332 dev->stop = sp_close;
340 333
341 dev->get_stats = sp_get_stats;
342 dev->set_mac_address = sp_set_mac_address; 334 dev->set_mac_address = sp_set_mac_address;
343 dev->hard_header_len = AX25_MAX_HEADER_LEN; 335 dev->hard_header_len = AX25_MAX_HEADER_LEN;
344 dev->header_ops = &sp_header_ops; 336 dev->header_ops = &sp_header_ops;
@@ -370,7 +362,7 @@ static void sp_bump(struct sixpack *sp, char cmd)
370 362
371 count = sp->rcount + 1; 363 count = sp->rcount + 1;
372 364
373 sp->stats.rx_bytes += count; 365 sp->dev->stats.rx_bytes += count;
374 366
375 if ((skb = dev_alloc_skb(count)) == NULL) 367 if ((skb = dev_alloc_skb(count)) == NULL)
376 goto out_mem; 368 goto out_mem;
@@ -382,12 +374,12 @@ static void sp_bump(struct sixpack *sp, char cmd)
382 skb->protocol = ax25_type_trans(skb, sp->dev); 374 skb->protocol = ax25_type_trans(skb, sp->dev);
383 netif_rx(skb); 375 netif_rx(skb);
384 sp->dev->last_rx = jiffies; 376 sp->dev->last_rx = jiffies;
385 sp->stats.rx_packets++; 377 sp->dev->stats.rx_packets++;
386 378
387 return; 379 return;
388 380
389out_mem: 381out_mem:
390 sp->stats.rx_dropped++; 382 sp->dev->stats.rx_dropped++;
391} 383}
392 384
393 385
@@ -436,7 +428,7 @@ static void sixpack_write_wakeup(struct tty_struct *tty)
436 if (sp->xleft <= 0) { 428 if (sp->xleft <= 0) {
437 /* Now serial buffer is almost free & we can start 429 /* Now serial buffer is almost free & we can start
438 * transmission of another packet */ 430 * transmission of another packet */
439 sp->stats.tx_packets++; 431 sp->dev->stats.tx_packets++;
440 clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags); 432 clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
441 sp->tx_enable = 0; 433 sp->tx_enable = 0;
442 netif_wake_queue(sp->dev); 434 netif_wake_queue(sp->dev);
@@ -484,7 +476,7 @@ static void sixpack_receive_buf(struct tty_struct *tty,
484 count--; 476 count--;
485 if (fp && *fp++) { 477 if (fp && *fp++) {
486 if (!test_and_set_bit(SIXPF_ERROR, &sp->flags)) 478 if (!test_and_set_bit(SIXPF_ERROR, &sp->flags))
487 sp->stats.rx_errors++; 479 sp->dev->stats.rx_errors++;
488 continue; 480 continue;
489 } 481 }
490 } 482 }
diff --git a/drivers/net/hamradio/bpqether.c b/drivers/net/hamradio/bpqether.c
index 5f4b4c6c9f76..b6500b2aacf2 100644
--- a/drivers/net/hamradio/bpqether.c
+++ b/drivers/net/hamradio/bpqether.c
@@ -124,6 +124,18 @@ static LIST_HEAD(bpq_devices);
124 */ 124 */
125static struct lock_class_key bpq_netdev_xmit_lock_key; 125static struct lock_class_key bpq_netdev_xmit_lock_key;
126 126
127static void bpq_set_lockdep_class_one(struct net_device *dev,
128 struct netdev_queue *txq,
129 void *_unused)
130{
131 lockdep_set_class(&txq->_xmit_lock, &bpq_netdev_xmit_lock_key);
132}
133
134static void bpq_set_lockdep_class(struct net_device *dev)
135{
136 netdev_for_each_tx_queue(dev, bpq_set_lockdep_class_one, NULL);
137}
138
127/* ------------------------------------------------------------------------ */ 139/* ------------------------------------------------------------------------ */
128 140
129 141
@@ -523,7 +535,7 @@ static int bpq_new_device(struct net_device *edev)
523 err = register_netdevice(ndev); 535 err = register_netdevice(ndev);
524 if (err) 536 if (err)
525 goto error; 537 goto error;
526 lockdep_set_class(&ndev->_xmit_lock, &bpq_netdev_xmit_lock_key); 538 bpq_set_lockdep_class(ndev);
527 539
528 /* List protected by RTNL */ 540 /* List protected by RTNL */
529 list_add_rcu(&bpq->bpq_list, &bpq_devices); 541 list_add_rcu(&bpq->bpq_list, &bpq_devices);
diff --git a/drivers/net/hamradio/mkiss.c b/drivers/net/hamradio/mkiss.c
index c6ca47599fd4..3249df5e0f17 100644
--- a/drivers/net/hamradio/mkiss.c
+++ b/drivers/net/hamradio/mkiss.c
@@ -356,7 +356,9 @@ static int ax_set_mac_address(struct net_device *dev, void *addr)
356 struct sockaddr_ax25 *sa = addr; 356 struct sockaddr_ax25 *sa = addr;
357 357
358 netif_tx_lock_bh(dev); 358 netif_tx_lock_bh(dev);
359 netif_addr_lock(dev);
359 memcpy(dev->dev_addr, &sa->sax25_call, AX25_ADDR_LEN); 360 memcpy(dev->dev_addr, &sa->sax25_call, AX25_ADDR_LEN);
361 netif_addr_unlock(dev);
360 netif_tx_unlock_bh(dev); 362 netif_tx_unlock_bh(dev);
361 363
362 return 0; 364 return 0;
diff --git a/drivers/net/hp.c b/drivers/net/hp.c
index c649a8019beb..8281209ededf 100644
--- a/drivers/net/hp.c
+++ b/drivers/net/hp.c
@@ -103,7 +103,7 @@ static int __init do_hp_probe(struct net_device *dev)
103#ifndef MODULE 103#ifndef MODULE
104struct net_device * __init hp_probe(int unit) 104struct net_device * __init hp_probe(int unit)
105{ 105{
106 struct net_device *dev = alloc_ei_netdev(); 106 struct net_device *dev = alloc_eip_netdev();
107 int err; 107 int err;
108 108
109 if (!dev) 109 if (!dev)
@@ -176,7 +176,7 @@ static int __init hp_probe1(struct net_device *dev, int ioaddr)
176 outb_p(irqmap[irq] | HP_RUN, ioaddr + HP_CONFIGURE); 176 outb_p(irqmap[irq] | HP_RUN, ioaddr + HP_CONFIGURE);
177 outb_p( 0x00 | HP_RUN, ioaddr + HP_CONFIGURE); 177 outb_p( 0x00 | HP_RUN, ioaddr + HP_CONFIGURE);
178 if (irq == probe_irq_off(cookie) /* It's a good IRQ line! */ 178 if (irq == probe_irq_off(cookie) /* It's a good IRQ line! */
179 && request_irq (irq, ei_interrupt, 0, DRV_NAME, dev) == 0) { 179 && request_irq (irq, eip_interrupt, 0, DRV_NAME, dev) == 0) {
180 printk(" selecting IRQ %d.\n", irq); 180 printk(" selecting IRQ %d.\n", irq);
181 dev->irq = *irqp; 181 dev->irq = *irqp;
182 break; 182 break;
@@ -191,7 +191,7 @@ static int __init hp_probe1(struct net_device *dev, int ioaddr)
191 } else { 191 } else {
192 if (dev->irq == 2) 192 if (dev->irq == 2)
193 dev->irq = 9; 193 dev->irq = 9;
194 if ((retval = request_irq(dev->irq, ei_interrupt, 0, DRV_NAME, dev))) { 194 if ((retval = request_irq(dev->irq, eip_interrupt, 0, DRV_NAME, dev))) {
195 printk (" unable to get IRQ %d.\n", dev->irq); 195 printk (" unable to get IRQ %d.\n", dev->irq);
196 goto out; 196 goto out;
197 } 197 }
@@ -202,7 +202,7 @@ static int __init hp_probe1(struct net_device *dev, int ioaddr)
202 dev->open = &hp_open; 202 dev->open = &hp_open;
203 dev->stop = &hp_close; 203 dev->stop = &hp_close;
204#ifdef CONFIG_NET_POLL_CONTROLLER 204#ifdef CONFIG_NET_POLL_CONTROLLER
205 dev->poll_controller = ei_poll; 205 dev->poll_controller = eip_poll;
206#endif 206#endif
207 207
208 ei_status.name = name; 208 ei_status.name = name;
@@ -231,14 +231,14 @@ out:
231static int 231static int
232hp_open(struct net_device *dev) 232hp_open(struct net_device *dev)
233{ 233{
234 ei_open(dev); 234 eip_open(dev);
235 return 0; 235 return 0;
236} 236}
237 237
238static int 238static int
239hp_close(struct net_device *dev) 239hp_close(struct net_device *dev)
240{ 240{
241 ei_close(dev); 241 eip_close(dev);
242 return 0; 242 return 0;
243} 243}
244 244
@@ -421,7 +421,7 @@ init_module(void)
421 if (this_dev != 0) break; /* only autoprobe 1st one */ 421 if (this_dev != 0) break; /* only autoprobe 1st one */
422 printk(KERN_NOTICE "hp.c: Presently autoprobing (not recommended) for a single card.\n"); 422 printk(KERN_NOTICE "hp.c: Presently autoprobing (not recommended) for a single card.\n");
423 } 423 }
424 dev = alloc_ei_netdev(); 424 dev = alloc_eip_netdev();
425 if (!dev) 425 if (!dev)
426 break; 426 break;
427 dev->irq = irq[this_dev]; 427 dev->irq = irq[this_dev];
diff --git a/drivers/net/hplance.c b/drivers/net/hplance.c
index be6e5bc7c881..2e802634d366 100644
--- a/drivers/net/hplance.c
+++ b/drivers/net/hplance.c
@@ -220,12 +220,12 @@ static int hplance_close(struct net_device *dev)
220 return 0; 220 return 0;
221} 221}
222 222
223int __init hplance_init_module(void) 223static int __init hplance_init_module(void)
224{ 224{
225 return dio_register_driver(&hplance_driver); 225 return dio_register_driver(&hplance_driver);
226} 226}
227 227
228void __exit hplance_cleanup_module(void) 228static void __exit hplance_cleanup_module(void)
229{ 229{
230 dio_unregister_driver(&hplance_driver); 230 dio_unregister_driver(&hplance_driver);
231} 231}
diff --git a/drivers/net/ibm_emac/Kconfig b/drivers/net/ibm_emac/Kconfig
deleted file mode 100644
index f61c48047dc0..000000000000
--- a/drivers/net/ibm_emac/Kconfig
+++ /dev/null
@@ -1,70 +0,0 @@
1config IBM_EMAC
2 tristate "PowerPC 4xx on-chip Ethernet support"
3 depends on 4xx && !PPC_MERGE
4 help
5 This driver supports the PowerPC 4xx EMAC family of on-chip
6 Ethernet controllers.
7
8config IBM_EMAC_RXB
9 int "Number of receive buffers"
10 depends on IBM_EMAC
11 default "128"
12
13config IBM_EMAC_TXB
14 int "Number of transmit buffers"
15 depends on IBM_EMAC
16 default "64"
17
18config IBM_EMAC_POLL_WEIGHT
19 int "MAL NAPI polling weight"
20 depends on IBM_EMAC
21 default "32"
22
23config IBM_EMAC_RX_COPY_THRESHOLD
24 int "RX skb copy threshold (bytes)"
25 depends on IBM_EMAC
26 default "256"
27
28config IBM_EMAC_RX_SKB_HEADROOM
29 int "Additional RX skb headroom (bytes)"
30 depends on IBM_EMAC
31 default "0"
32 help
33 Additional receive skb headroom. Note, that driver
34 will always reserve at least 2 bytes to make IP header
35 aligned, so usually there is no need to add any additional
36 headroom.
37
38 If unsure, set to 0.
39
40config IBM_EMAC_PHY_RX_CLK_FIX
41 bool "PHY Rx clock workaround"
42 depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR)
43 help
44 Enable this if EMAC attached to a PHY which doesn't generate
45 RX clock if there is no link, if this is the case, you will
46 see "TX disable timeout" or "RX disable timeout" in the system
47 log.
48
49 If unsure, say N.
50
51config IBM_EMAC_DEBUG
52 bool "Debugging"
53 depends on IBM_EMAC
54 default n
55
56config IBM_EMAC_ZMII
57 bool
58 depends on IBM_EMAC && (NP405H || NP405L || 44x)
59 default y
60
61config IBM_EMAC_RGMII
62 bool
63 depends on IBM_EMAC && 440GX
64 default y
65
66config IBM_EMAC_TAH
67 bool
68 depends on IBM_EMAC && 440GX
69 default y
70
diff --git a/drivers/net/ibm_emac/Makefile b/drivers/net/ibm_emac/Makefile
deleted file mode 100644
index f98ddf0e807a..000000000000
--- a/drivers/net/ibm_emac/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for the PowerPC 4xx on-chip ethernet driver
3#
4
5obj-$(CONFIG_IBM_EMAC) += ibm_emac.o
6
7ibm_emac-objs := ibm_emac_mal.o ibm_emac_core.o ibm_emac_phy.o
8ibm_emac-$(CONFIG_IBM_EMAC_ZMII) += ibm_emac_zmii.o
9ibm_emac-$(CONFIG_IBM_EMAC_RGMII) += ibm_emac_rgmii.o
10ibm_emac-$(CONFIG_IBM_EMAC_TAH) += ibm_emac_tah.o
11ibm_emac-$(CONFIG_IBM_EMAC_DEBUG) += ibm_emac_debug.o
diff --git a/drivers/net/ibm_emac/ibm_emac.h b/drivers/net/ibm_emac/ibm_emac.h
deleted file mode 100644
index 97ed22bb4320..000000000000
--- a/drivers/net/ibm_emac/ibm_emac.h
+++ /dev/null
@@ -1,329 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac.h
3 *
4 * Register definitions for PowerPC 4xx on-chip ethernet contoller
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * Armin Kuster <akuster@mvista.com>
12 * Copyright 2002-2004 MontaVista Software Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 */
20#ifndef __IBM_EMAC_H_
21#define __IBM_EMAC_H_
22
23#include <linux/types.h>
24
25/* This is a simple check to prevent use of this driver on non-tested SoCs */
26#if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \
27 !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \
28 !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) && \
29 !defined(CONFIG_440GR)
30#error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"
31#endif
32
33/* EMAC registers Write Access rules */
34struct emac_regs {
35 u32 mr0; /* special */
36 u32 mr1; /* Reset */
37 u32 tmr0; /* special */
38 u32 tmr1; /* special */
39 u32 rmr; /* Reset */
40 u32 isr; /* Always */
41 u32 iser; /* Reset */
42 u32 iahr; /* Reset, R, T */
43 u32 ialr; /* Reset, R, T */
44 u32 vtpid; /* Reset, R, T */
45 u32 vtci; /* Reset, R, T */
46 u32 ptr; /* Reset, T */
47 u32 iaht1; /* Reset, R */
48 u32 iaht2; /* Reset, R */
49 u32 iaht3; /* Reset, R */
50 u32 iaht4; /* Reset, R */
51 u32 gaht1; /* Reset, R */
52 u32 gaht2; /* Reset, R */
53 u32 gaht3; /* Reset, R */
54 u32 gaht4; /* Reset, R */
55 u32 lsah;
56 u32 lsal;
57 u32 ipgvr; /* Reset, T */
58 u32 stacr; /* special */
59 u32 trtr; /* special */
60 u32 rwmr; /* Reset */
61 u32 octx;
62 u32 ocrx;
63 u32 ipcr;
64};
65
66#if !defined(CONFIG_IBM_EMAC4)
67#define EMAC_ETHTOOL_REGS_VER 0
68#define EMAC_ETHTOOL_REGS_SIZE (sizeof(struct emac_regs) - sizeof(u32))
69#else
70#define EMAC_ETHTOOL_REGS_VER 1
71#define EMAC_ETHTOOL_REGS_SIZE sizeof(struct emac_regs)
72#endif
73
74/* EMACx_MR0 */
75#define EMAC_MR0_RXI 0x80000000
76#define EMAC_MR0_TXI 0x40000000
77#define EMAC_MR0_SRST 0x20000000
78#define EMAC_MR0_TXE 0x10000000
79#define EMAC_MR0_RXE 0x08000000
80#define EMAC_MR0_WKE 0x04000000
81
82/* EMACx_MR1 */
83#define EMAC_MR1_FDE 0x80000000
84#define EMAC_MR1_ILE 0x40000000
85#define EMAC_MR1_VLE 0x20000000
86#define EMAC_MR1_EIFC 0x10000000
87#define EMAC_MR1_APP 0x08000000
88#define EMAC_MR1_IST 0x01000000
89
90#define EMAC_MR1_MF_MASK 0x00c00000
91#define EMAC_MR1_MF_10 0x00000000
92#define EMAC_MR1_MF_100 0x00400000
93#if !defined(CONFIG_IBM_EMAC4)
94#define EMAC_MR1_MF_1000 0x00000000
95#define EMAC_MR1_MF_1000GPCS 0x00000000
96#define EMAC_MR1_MF_IPPA(id) 0x00000000
97#else
98#define EMAC_MR1_MF_1000 0x00800000
99#define EMAC_MR1_MF_1000GPCS 0x00c00000
100#define EMAC_MR1_MF_IPPA(id) (((id) & 0x1f) << 6)
101#endif
102
103#define EMAC_TX_FIFO_SIZE 2048
104
105#if !defined(CONFIG_IBM_EMAC4)
106#define EMAC_MR1_RFS_4K 0x00300000
107#define EMAC_MR1_RFS_16K 0x00000000
108#define EMAC_RX_FIFO_SIZE(gige) 4096
109#define EMAC_MR1_TFS_2K 0x00080000
110#define EMAC_MR1_TR0_MULT 0x00008000
111#define EMAC_MR1_JPSM 0x00000000
112#define EMAC_MR1_MWSW_001 0x00000000
113#define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
114#else
115#define EMAC_MR1_RFS_4K 0x00180000
116#define EMAC_MR1_RFS_16K 0x00280000
117#define EMAC_RX_FIFO_SIZE(gige) ((gige) ? 16384 : 4096)
118#define EMAC_MR1_TFS_2K 0x00020000
119#define EMAC_MR1_TR 0x00008000
120#define EMAC_MR1_MWSW_001 0x00001000
121#define EMAC_MR1_JPSM 0x00000800
122#define EMAC_MR1_OBCI_MASK 0x00000038
123#define EMAC_MR1_OBCI_50 0x00000000
124#define EMAC_MR1_OBCI_66 0x00000008
125#define EMAC_MR1_OBCI_83 0x00000010
126#define EMAC_MR1_OBCI_100 0x00000018
127#define EMAC_MR1_OBCI_100P 0x00000020
128#define EMAC_MR1_OBCI(freq) ((freq) <= 50 ? EMAC_MR1_OBCI_50 : \
129 (freq) <= 66 ? EMAC_MR1_OBCI_66 : \
130 (freq) <= 83 ? EMAC_MR1_OBCI_83 : \
131 (freq) <= 100 ? EMAC_MR1_OBCI_100 : EMAC_MR1_OBCI_100P)
132#define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR | \
133 EMAC_MR1_OBCI(opb))
134#endif
135
136/* EMACx_TMR0 */
137#define EMAC_TMR0_GNP 0x80000000
138#if !defined(CONFIG_IBM_EMAC4)
139#define EMAC_TMR0_DEFAULT 0x00000000
140#else
141#define EMAC_TMR0_TFAE_2_32 0x00000001
142#define EMAC_TMR0_TFAE_4_64 0x00000002
143#define EMAC_TMR0_TFAE_8_128 0x00000003
144#define EMAC_TMR0_TFAE_16_256 0x00000004
145#define EMAC_TMR0_TFAE_32_512 0x00000005
146#define EMAC_TMR0_TFAE_64_1024 0x00000006
147#define EMAC_TMR0_TFAE_128_2048 0x00000007
148#define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_2_32
149#endif
150#define EMAC_TMR0_XMIT (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
151
152/* EMACx_TMR1 */
153
154/* IBM manuals are not very clear here.
155 * This is my interpretation of how things are. --ebs
156 */
157#if defined(CONFIG_40x)
158#define EMAC_FIFO_ENTRY_SIZE 8
159#define EMAC_MAL_BURST_SIZE (16 * 4)
160#else
161#define EMAC_FIFO_ENTRY_SIZE 16
162#define EMAC_MAL_BURST_SIZE (64 * 4)
163#endif
164
165#if !defined(CONFIG_IBM_EMAC4)
166#define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0xff) << 16))
167#else
168#define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0x3ff) << 14))
169#endif
170
171/* EMACx_RMR */
172#define EMAC_RMR_SP 0x80000000
173#define EMAC_RMR_SFCS 0x40000000
174#define EMAC_RMR_RRP 0x20000000
175#define EMAC_RMR_RFP 0x10000000
176#define EMAC_RMR_ROP 0x08000000
177#define EMAC_RMR_RPIR 0x04000000
178#define EMAC_RMR_PPP 0x02000000
179#define EMAC_RMR_PME 0x01000000
180#define EMAC_RMR_PMME 0x00800000
181#define EMAC_RMR_IAE 0x00400000
182#define EMAC_RMR_MIAE 0x00200000
183#define EMAC_RMR_BAE 0x00100000
184#define EMAC_RMR_MAE 0x00080000
185#if !defined(CONFIG_IBM_EMAC4)
186#define EMAC_RMR_BASE 0x00000000
187#else
188#define EMAC_RMR_RFAF_2_32 0x00000001
189#define EMAC_RMR_RFAF_4_64 0x00000002
190#define EMAC_RMR_RFAF_8_128 0x00000003
191#define EMAC_RMR_RFAF_16_256 0x00000004
192#define EMAC_RMR_RFAF_32_512 0x00000005
193#define EMAC_RMR_RFAF_64_1024 0x00000006
194#define EMAC_RMR_RFAF_128_2048 0x00000007
195#define EMAC_RMR_BASE EMAC_RMR_RFAF_128_2048
196#endif
197
198/* EMACx_ISR & EMACx_ISER */
199#if !defined(CONFIG_IBM_EMAC4)
200#define EMAC_ISR_TXPE 0x00000000
201#define EMAC_ISR_RXPE 0x00000000
202#define EMAC_ISR_TXUE 0x00000000
203#define EMAC_ISR_RXOE 0x00000000
204#else
205#define EMAC_ISR_TXPE 0x20000000
206#define EMAC_ISR_RXPE 0x10000000
207#define EMAC_ISR_TXUE 0x08000000
208#define EMAC_ISR_RXOE 0x04000000
209#endif
210#define EMAC_ISR_OVR 0x02000000
211#define EMAC_ISR_PP 0x01000000
212#define EMAC_ISR_BP 0x00800000
213#define EMAC_ISR_RP 0x00400000
214#define EMAC_ISR_SE 0x00200000
215#define EMAC_ISR_ALE 0x00100000
216#define EMAC_ISR_BFCS 0x00080000
217#define EMAC_ISR_PTLE 0x00040000
218#define EMAC_ISR_ORE 0x00020000
219#define EMAC_ISR_IRE 0x00010000
220#define EMAC_ISR_SQE 0x00000080
221#define EMAC_ISR_TE 0x00000040
222#define EMAC_ISR_MOS 0x00000002
223#define EMAC_ISR_MOF 0x00000001
224
225/* EMACx_STACR */
226#define EMAC_STACR_PHYD_MASK 0xffff
227#define EMAC_STACR_PHYD_SHIFT 16
228#define EMAC_STACR_OC 0x00008000
229#define EMAC_STACR_PHYE 0x00004000
230#define EMAC_STACR_STAC_MASK 0x00003000
231#define EMAC_STACR_STAC_READ 0x00001000
232#define EMAC_STACR_STAC_WRITE 0x00002000
233#if !defined(CONFIG_IBM_EMAC4)
234#define EMAC_STACR_OPBC_MASK 0x00000C00
235#define EMAC_STACR_OPBC_50 0x00000000
236#define EMAC_STACR_OPBC_66 0x00000400
237#define EMAC_STACR_OPBC_83 0x00000800
238#define EMAC_STACR_OPBC_100 0x00000C00
239#define EMAC_STACR_OPBC(freq) ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
240 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
241 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
242#define EMAC_STACR_BASE(opb) EMAC_STACR_OPBC(opb)
243#else
244#define EMAC_STACR_BASE(opb) 0x00000000
245#endif
246#define EMAC_STACR_PCDA_MASK 0x1f
247#define EMAC_STACR_PCDA_SHIFT 5
248#define EMAC_STACR_PRA_MASK 0x1f
249
250/*
251 * For the 440SPe, AMCC inexplicably changed the polarity of
252 * the "operation complete" bit in the MII control register.
253 */
254#if defined(CONFIG_440SPE)
255static inline int emac_phy_done(u32 stacr)
256{
257 return !(stacr & EMAC_STACR_OC);
258};
259#define EMAC_STACR_START EMAC_STACR_OC
260
261#else /* CONFIG_440SPE */
262static inline int emac_phy_done(u32 stacr)
263{
264 return stacr & EMAC_STACR_OC;
265};
266#define EMAC_STACR_START 0
267#endif /* !CONFIG_440SPE */
268
269/* EMACx_TRTR */
270#if !defined(CONFIG_IBM_EMAC4)
271#define EMAC_TRTR_SHIFT 27
272#else
273#define EMAC_TRTR_SHIFT 24
274#endif
275#define EMAC_TRTR(size) ((((size) >> 6) - 1) << EMAC_TRTR_SHIFT)
276
277/* EMACx_RWMR */
278#if !defined(CONFIG_IBM_EMAC4)
279#define EMAC_RWMR(l,h) (((l) << 23) | ( ((h) & 0x1ff) << 7))
280#else
281#define EMAC_RWMR(l,h) (((l) << 22) | ( ((h) & 0x3ff) << 6))
282#endif
283
284/* EMAC specific TX descriptor control fields (write access) */
285#define EMAC_TX_CTRL_GFCS 0x0200
286#define EMAC_TX_CTRL_GP 0x0100
287#define EMAC_TX_CTRL_ISA 0x0080
288#define EMAC_TX_CTRL_RSA 0x0040
289#define EMAC_TX_CTRL_IVT 0x0020
290#define EMAC_TX_CTRL_RVT 0x0010
291#define EMAC_TX_CTRL_TAH_CSUM 0x000e
292
293/* EMAC specific TX descriptor status fields (read access) */
294#define EMAC_TX_ST_BFCS 0x0200
295#define EMAC_TX_ST_LCS 0x0080
296#define EMAC_TX_ST_ED 0x0040
297#define EMAC_TX_ST_EC 0x0020
298#define EMAC_TX_ST_LC 0x0010
299#define EMAC_TX_ST_MC 0x0008
300#define EMAC_TX_ST_SC 0x0004
301#define EMAC_TX_ST_UR 0x0002
302#define EMAC_TX_ST_SQE 0x0001
303#if !defined(CONFIG_IBM_EMAC_TAH)
304#define EMAC_IS_BAD_TX(v) ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
305 EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
306 EMAC_TX_ST_MC | EMAC_TX_ST_UR))
307#else
308#define EMAC_IS_BAD_TX(v) ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
309 EMAC_TX_ST_EC | EMAC_TX_ST_LC))
310#endif
311
312/* EMAC specific RX descriptor status fields (read access) */
313#define EMAC_RX_ST_OE 0x0200
314#define EMAC_RX_ST_PP 0x0100
315#define EMAC_RX_ST_BP 0x0080
316#define EMAC_RX_ST_RP 0x0040
317#define EMAC_RX_ST_SE 0x0020
318#define EMAC_RX_ST_AE 0x0010
319#define EMAC_RX_ST_BFCS 0x0008
320#define EMAC_RX_ST_PTL 0x0004
321#define EMAC_RX_ST_ORE 0x0002
322#define EMAC_RX_ST_IRE 0x0001
323#define EMAC_RX_TAH_BAD_CSUM 0x0003
324#define EMAC_BAD_RX_MASK (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
325 EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
326 EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
327 EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
328 EMAC_RX_ST_IRE )
329#endif /* __IBM_EMAC_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c
deleted file mode 100644
index 73664f226f32..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_core.c
+++ /dev/null
@@ -1,2263 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_core.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
12 * Armin Kuster <akuster@mvista.com>
13 * Johnnie Peters <jpeters@mvista.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/errno.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/init.h>
29#include <linux/types.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/crc32.h>
34#include <linux/ethtool.h>
35#include <linux/mii.h>
36#include <linux/bitops.h>
37
38#include <asm/processor.h>
39#include <asm/io.h>
40#include <asm/dma.h>
41#include <asm/uaccess.h>
42#include <asm/ocp.h>
43
44#include "ibm_emac_core.h"
45#include "ibm_emac_debug.h"
46
47/*
48 * Lack of dma_unmap_???? calls is intentional.
49 *
50 * API-correct usage requires additional support state information to be
51 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
52 * EMAC design (e.g. TX buffer passed from network stack can be split into
53 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
54 * maintaining such information will add additional overhead.
55 * Current DMA API implementation for 4xx processors only ensures cache coherency
56 * and dma_unmap_???? routines are empty and are likely to stay this way.
57 * I decided to omit dma_unmap_??? calls because I don't want to add additional
58 * complexity just for the sake of following some abstract API, when it doesn't
59 * add any real benefit to the driver. I understand that this decision maybe
60 * controversial, but I really tried to make code API-correct and efficient
61 * at the same time and didn't come up with code I liked :(. --ebs
62 */
63
64#define DRV_NAME "emac"
65#define DRV_VERSION "3.54"
66#define DRV_DESC "PPC 4xx OCP EMAC driver"
67
68MODULE_DESCRIPTION(DRV_DESC);
69MODULE_AUTHOR
70 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
71MODULE_LICENSE("GPL");
72
73/* minimum number of free TX descriptors required to wake up TX process */
74#define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
75
76/* If packet size is less than this number, we allocate small skb and copy packet
77 * contents into it instead of just sending original big skb up
78 */
79#define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
80
81/* Since multiple EMACs share MDIO lines in various ways, we need
82 * to avoid re-using the same PHY ID in cases where the arch didn't
83 * setup precise phy_map entries
84 */
85static u32 busy_phy_map;
86
87#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && \
88 (defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR))
89/* 405EP has "EMAC to PHY Control Register" (CPC0_EPCTL) which can help us
90 * with PHY RX clock problem.
91 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, which
92 * also allows controlling each EMAC clock
93 */
94static inline void EMAC_RX_CLK_TX(int idx)
95{
96 unsigned long flags;
97 local_irq_save(flags);
98
99#if defined(CONFIG_405EP)
100 mtdcr(0xf3, mfdcr(0xf3) | (1 << idx));
101#else /* CONFIG_440EP || CONFIG_440GR */
102 SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) | (0x08000000 >> idx));
103#endif
104
105 local_irq_restore(flags);
106}
107
108static inline void EMAC_RX_CLK_DEFAULT(int idx)
109{
110 unsigned long flags;
111 local_irq_save(flags);
112
113#if defined(CONFIG_405EP)
114 mtdcr(0xf3, mfdcr(0xf3) & ~(1 << idx));
115#else /* CONFIG_440EP */
116 SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~(0x08000000 >> idx));
117#endif
118
119 local_irq_restore(flags);
120}
121#else
122#define EMAC_RX_CLK_TX(idx) ((void)0)
123#define EMAC_RX_CLK_DEFAULT(idx) ((void)0)
124#endif
125
126#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && defined(CONFIG_440GX)
127/* We can switch Ethernet clock to the internal source through SDR0_MFR[ECS],
128 * unfortunately this is less flexible than 440EP case, because it's a global
129 * setting for all EMACs, therefore we do this clock trick only during probe.
130 */
131#define EMAC_CLK_INTERNAL SDR_WRITE(DCRN_SDR_MFR, \
132 SDR_READ(DCRN_SDR_MFR) | 0x08000000)
133#define EMAC_CLK_EXTERNAL SDR_WRITE(DCRN_SDR_MFR, \
134 SDR_READ(DCRN_SDR_MFR) & ~0x08000000)
135#else
136#define EMAC_CLK_INTERNAL ((void)0)
137#define EMAC_CLK_EXTERNAL ((void)0)
138#endif
139
140/* I don't want to litter system log with timeout errors
141 * when we have brain-damaged PHY.
142 */
143static inline void emac_report_timeout_error(struct ocp_enet_private *dev,
144 const char *error)
145{
146#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX)
147 DBG("%d: %s" NL, dev->def->index, error);
148#else
149 if (net_ratelimit())
150 printk(KERN_ERR "emac%d: %s\n", dev->def->index, error);
151#endif
152}
153
154/* PHY polling intervals */
155#define PHY_POLL_LINK_ON HZ
156#define PHY_POLL_LINK_OFF (HZ / 5)
157
158/* Graceful stop timeouts in us.
159 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
160 */
161#define STOP_TIMEOUT_10 1230
162#define STOP_TIMEOUT_100 124
163#define STOP_TIMEOUT_1000 13
164#define STOP_TIMEOUT_1000_JUMBO 73
165
166/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
167static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
168 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
169 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
170 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
171 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
172 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
173 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
174 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
175 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
176 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
177 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
178 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
179 "tx_bd_excessive_collisions", "tx_bd_late_collision",
180 "tx_bd_multple_collisions", "tx_bd_single_collision",
181 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
182 "tx_errors"
183};
184
185static irqreturn_t emac_irq(int irq, void *dev_instance);
186static void emac_clean_tx_ring(struct ocp_enet_private *dev);
187
188static inline int emac_phy_supports_gige(int phy_mode)
189{
190 return phy_mode == PHY_MODE_GMII ||
191 phy_mode == PHY_MODE_RGMII ||
192 phy_mode == PHY_MODE_TBI ||
193 phy_mode == PHY_MODE_RTBI;
194}
195
196static inline int emac_phy_gpcs(int phy_mode)
197{
198 return phy_mode == PHY_MODE_TBI ||
199 phy_mode == PHY_MODE_RTBI;
200}
201
202static inline void emac_tx_enable(struct ocp_enet_private *dev)
203{
204 struct emac_regs __iomem *p = dev->emacp;
205 unsigned long flags;
206 u32 r;
207
208 local_irq_save(flags);
209
210 DBG("%d: tx_enable" NL, dev->def->index);
211
212 r = in_be32(&p->mr0);
213 if (!(r & EMAC_MR0_TXE))
214 out_be32(&p->mr0, r | EMAC_MR0_TXE);
215 local_irq_restore(flags);
216}
217
218static void emac_tx_disable(struct ocp_enet_private *dev)
219{
220 struct emac_regs __iomem *p = dev->emacp;
221 unsigned long flags;
222 u32 r;
223
224 local_irq_save(flags);
225
226 DBG("%d: tx_disable" NL, dev->def->index);
227
228 r = in_be32(&p->mr0);
229 if (r & EMAC_MR0_TXE) {
230 int n = dev->stop_timeout;
231 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
232 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
233 udelay(1);
234 --n;
235 }
236 if (unlikely(!n))
237 emac_report_timeout_error(dev, "TX disable timeout");
238 }
239 local_irq_restore(flags);
240}
241
242static void emac_rx_enable(struct ocp_enet_private *dev)
243{
244 struct emac_regs __iomem *p = dev->emacp;
245 unsigned long flags;
246 u32 r;
247
248 local_irq_save(flags);
249 if (unlikely(dev->commac.rx_stopped))
250 goto out;
251
252 DBG("%d: rx_enable" NL, dev->def->index);
253
254 r = in_be32(&p->mr0);
255 if (!(r & EMAC_MR0_RXE)) {
256 if (unlikely(!(r & EMAC_MR0_RXI))) {
257 /* Wait if previous async disable is still in progress */
258 int n = dev->stop_timeout;
259 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
260 udelay(1);
261 --n;
262 }
263 if (unlikely(!n))
264 emac_report_timeout_error(dev,
265 "RX disable timeout");
266 }
267 out_be32(&p->mr0, r | EMAC_MR0_RXE);
268 }
269 out:
270 local_irq_restore(flags);
271}
272
273static void emac_rx_disable(struct ocp_enet_private *dev)
274{
275 struct emac_regs __iomem *p = dev->emacp;
276 unsigned long flags;
277 u32 r;
278
279 local_irq_save(flags);
280
281 DBG("%d: rx_disable" NL, dev->def->index);
282
283 r = in_be32(&p->mr0);
284 if (r & EMAC_MR0_RXE) {
285 int n = dev->stop_timeout;
286 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
287 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
288 udelay(1);
289 --n;
290 }
291 if (unlikely(!n))
292 emac_report_timeout_error(dev, "RX disable timeout");
293 }
294 local_irq_restore(flags);
295}
296
297static inline void emac_rx_disable_async(struct ocp_enet_private *dev)
298{
299 struct emac_regs __iomem *p = dev->emacp;
300 unsigned long flags;
301 u32 r;
302
303 local_irq_save(flags);
304
305 DBG("%d: rx_disable_async" NL, dev->def->index);
306
307 r = in_be32(&p->mr0);
308 if (r & EMAC_MR0_RXE)
309 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
310 local_irq_restore(flags);
311}
312
313static int emac_reset(struct ocp_enet_private *dev)
314{
315 struct emac_regs __iomem *p = dev->emacp;
316 unsigned long flags;
317 int n = 20;
318
319 DBG("%d: reset" NL, dev->def->index);
320
321 local_irq_save(flags);
322
323 if (!dev->reset_failed) {
324 /* 40x erratum suggests stopping RX channel before reset,
325 * we stop TX as well
326 */
327 emac_rx_disable(dev);
328 emac_tx_disable(dev);
329 }
330
331 out_be32(&p->mr0, EMAC_MR0_SRST);
332 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
333 --n;
334 local_irq_restore(flags);
335
336 if (n) {
337 dev->reset_failed = 0;
338 return 0;
339 } else {
340 emac_report_timeout_error(dev, "reset timeout");
341 dev->reset_failed = 1;
342 return -ETIMEDOUT;
343 }
344}
345
346static void emac_hash_mc(struct ocp_enet_private *dev)
347{
348 struct emac_regs __iomem *p = dev->emacp;
349 u16 gaht[4] = { 0 };
350 struct dev_mc_list *dmi;
351
352 DBG("%d: hash_mc %d" NL, dev->def->index, dev->ndev->mc_count);
353
354 for (dmi = dev->ndev->mc_list; dmi; dmi = dmi->next) {
355 int bit;
356 DECLARE_MAC_BUF(mac);
357 DBG2("%d: mc %s" NL,
358 dev->def->index, print_mac(mac, dmi->dmi_addr));
359
360 bit = 63 - (ether_crc(ETH_ALEN, dmi->dmi_addr) >> 26);
361 gaht[bit >> 4] |= 0x8000 >> (bit & 0x0f);
362 }
363 out_be32(&p->gaht1, gaht[0]);
364 out_be32(&p->gaht2, gaht[1]);
365 out_be32(&p->gaht3, gaht[2]);
366 out_be32(&p->gaht4, gaht[3]);
367}
368
369static inline u32 emac_iff2rmr(struct net_device *ndev)
370{
371 u32 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE |
372 EMAC_RMR_BASE;
373
374 if (ndev->flags & IFF_PROMISC)
375 r |= EMAC_RMR_PME;
376 else if (ndev->flags & IFF_ALLMULTI || ndev->mc_count > 32)
377 r |= EMAC_RMR_PMME;
378 else if (ndev->mc_count > 0)
379 r |= EMAC_RMR_MAE;
380
381 return r;
382}
383
384static inline int emac_opb_mhz(void)
385{
386 return (ocp_sys_info.opb_bus_freq + 500000) / 1000000;
387}
388
389/* BHs disabled */
390static int emac_configure(struct ocp_enet_private *dev)
391{
392 struct emac_regs __iomem *p = dev->emacp;
393 struct net_device *ndev = dev->ndev;
394 int gige;
395 u32 r;
396
397 DBG("%d: configure" NL, dev->def->index);
398
399 if (emac_reset(dev) < 0)
400 return -ETIMEDOUT;
401
402 tah_reset(dev->tah_dev);
403
404 /* Mode register */
405 r = EMAC_MR1_BASE(emac_opb_mhz()) | EMAC_MR1_VLE | EMAC_MR1_IST;
406 if (dev->phy.duplex == DUPLEX_FULL)
407 r |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
408 dev->stop_timeout = STOP_TIMEOUT_10;
409 switch (dev->phy.speed) {
410 case SPEED_1000:
411 if (emac_phy_gpcs(dev->phy.mode)) {
412 r |= EMAC_MR1_MF_1000GPCS |
413 EMAC_MR1_MF_IPPA(dev->phy.address);
414
415 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
416 * identify this GPCS PHY later.
417 */
418 out_be32(&p->ipcr, 0xdeadbeef);
419 } else
420 r |= EMAC_MR1_MF_1000;
421 r |= EMAC_MR1_RFS_16K;
422 gige = 1;
423
424 if (dev->ndev->mtu > ETH_DATA_LEN) {
425 r |= EMAC_MR1_JPSM;
426 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
427 } else
428 dev->stop_timeout = STOP_TIMEOUT_1000;
429 break;
430 case SPEED_100:
431 r |= EMAC_MR1_MF_100;
432 dev->stop_timeout = STOP_TIMEOUT_100;
433 /* Fall through */
434 default:
435 r |= EMAC_MR1_RFS_4K;
436 gige = 0;
437 break;
438 }
439
440 if (dev->rgmii_dev)
441 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_input,
442 dev->phy.speed);
443 else
444 zmii_set_speed(dev->zmii_dev, dev->zmii_input, dev->phy.speed);
445
446#if !defined(CONFIG_40x)
447 /* on 40x erratum forces us to NOT use integrated flow control,
448 * let's hope it works on 44x ;)
449 */
450 if (dev->phy.duplex == DUPLEX_FULL) {
451 if (dev->phy.pause)
452 r |= EMAC_MR1_EIFC | EMAC_MR1_APP;
453 else if (dev->phy.asym_pause)
454 r |= EMAC_MR1_APP;
455 }
456#endif
457 out_be32(&p->mr1, r);
458
459 /* Set individual MAC address */
460 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
461 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
462 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
463 ndev->dev_addr[5]);
464
465 /* VLAN Tag Protocol ID */
466 out_be32(&p->vtpid, 0x8100);
467
468 /* Receive mode register */
469 r = emac_iff2rmr(ndev);
470 if (r & EMAC_RMR_MAE)
471 emac_hash_mc(dev);
472 out_be32(&p->rmr, r);
473
474 /* FIFOs thresholds */
475 r = EMAC_TMR1((EMAC_MAL_BURST_SIZE / EMAC_FIFO_ENTRY_SIZE) + 1,
476 EMAC_TX_FIFO_SIZE / 2 / EMAC_FIFO_ENTRY_SIZE);
477 out_be32(&p->tmr1, r);
478 out_be32(&p->trtr, EMAC_TRTR(EMAC_TX_FIFO_SIZE / 2));
479
480 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
481 there should be still enough space in FIFO to allow the our link
482 partner time to process this frame and also time to send PAUSE
483 frame itself.
484
485 Here is the worst case scenario for the RX FIFO "headroom"
486 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
487
488 1) One maximum-length frame on TX 1522 bytes
489 2) One PAUSE frame time 64 bytes
490 3) PAUSE frame decode time allowance 64 bytes
491 4) One maximum-length frame on RX 1522 bytes
492 5) Round-trip propagation delay of the link (100Mb) 15 bytes
493 ----------
494 3187 bytes
495
496 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
497 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
498 */
499 r = EMAC_RWMR(EMAC_RX_FIFO_SIZE(gige) / 8 / EMAC_FIFO_ENTRY_SIZE,
500 EMAC_RX_FIFO_SIZE(gige) / 4 / EMAC_FIFO_ENTRY_SIZE);
501 out_be32(&p->rwmr, r);
502
503 /* Set PAUSE timer to the maximum */
504 out_be32(&p->ptr, 0xffff);
505
506 /* IRQ sources */
507 out_be32(&p->iser, EMAC_ISR_TXPE | EMAC_ISR_RXPE | /* EMAC_ISR_TXUE |
508 EMAC_ISR_RXOE | */ EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
509 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
510 EMAC_ISR_IRE | EMAC_ISR_TE);
511
512 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
513 if (emac_phy_gpcs(dev->phy.mode))
514 mii_reset_phy(&dev->phy);
515
516 return 0;
517}
518
519/* BHs disabled */
520static void emac_reinitialize(struct ocp_enet_private *dev)
521{
522 DBG("%d: reinitialize" NL, dev->def->index);
523
524 if (!emac_configure(dev)) {
525 emac_tx_enable(dev);
526 emac_rx_enable(dev);
527 }
528}
529
530/* BHs disabled */
531static void emac_full_tx_reset(struct net_device *ndev)
532{
533 struct ocp_enet_private *dev = ndev->priv;
534 struct ocp_func_emac_data *emacdata = dev->def->additions;
535
536 DBG("%d: full_tx_reset" NL, dev->def->index);
537
538 emac_tx_disable(dev);
539 mal_disable_tx_channel(dev->mal, emacdata->mal_tx_chan);
540 emac_clean_tx_ring(dev);
541 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
542
543 emac_configure(dev);
544
545 mal_enable_tx_channel(dev->mal, emacdata->mal_tx_chan);
546 emac_tx_enable(dev);
547 emac_rx_enable(dev);
548
549 netif_wake_queue(ndev);
550}
551
552static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg)
553{
554 struct emac_regs __iomem *p = dev->emacp;
555 u32 r;
556 int n;
557
558 DBG2("%d: mdio_read(%02x,%02x)" NL, dev->def->index, id, reg);
559
560 /* Enable proper MDIO port */
561 zmii_enable_mdio(dev->zmii_dev, dev->zmii_input);
562
563 /* Wait for management interface to become idle */
564 n = 10;
565 while (!emac_phy_done(in_be32(&p->stacr))) {
566 udelay(1);
567 if (!--n)
568 goto to;
569 }
570
571 /* Issue read command */
572 out_be32(&p->stacr,
573 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_READ |
574 (reg & EMAC_STACR_PRA_MASK)
575 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT)
576 | EMAC_STACR_START);
577
578 /* Wait for read to complete */
579 n = 100;
580 while (!emac_phy_done(r = in_be32(&p->stacr))) {
581 udelay(1);
582 if (!--n)
583 goto to;
584 }
585
586 if (unlikely(r & EMAC_STACR_PHYE)) {
587 DBG("%d: mdio_read(%02x, %02x) failed" NL, dev->def->index,
588 id, reg);
589 return -EREMOTEIO;
590 }
591
592 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
593 DBG2("%d: mdio_read -> %04x" NL, dev->def->index, r);
594 return r;
595 to:
596 DBG("%d: MII management interface timeout (read)" NL, dev->def->index);
597 return -ETIMEDOUT;
598}
599
600static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg,
601 u16 val)
602{
603 struct emac_regs __iomem *p = dev->emacp;
604 int n;
605
606 DBG2("%d: mdio_write(%02x,%02x,%04x)" NL, dev->def->index, id, reg,
607 val);
608
609 /* Enable proper MDIO port */
610 zmii_enable_mdio(dev->zmii_dev, dev->zmii_input);
611
612 /* Wait for management interface to be idle */
613 n = 10;
614 while (!emac_phy_done(in_be32(&p->stacr))) {
615 udelay(1);
616 if (!--n)
617 goto to;
618 }
619
620 /* Issue write command */
621 out_be32(&p->stacr,
622 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_WRITE |
623 (reg & EMAC_STACR_PRA_MASK) |
624 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
625 (val << EMAC_STACR_PHYD_SHIFT) | EMAC_STACR_START);
626
627 /* Wait for write to complete */
628 n = 100;
629 while (!emac_phy_done(in_be32(&p->stacr))) {
630 udelay(1);
631 if (!--n)
632 goto to;
633 }
634 return;
635 to:
636 DBG("%d: MII management interface timeout (write)" NL, dev->def->index);
637}
638
639static int emac_mdio_read(struct net_device *ndev, int id, int reg)
640{
641 struct ocp_enet_private *dev = ndev->priv;
642 int res;
643
644 local_bh_disable();
645 res = __emac_mdio_read(dev->mdio_dev ? dev->mdio_dev : dev, (u8) id,
646 (u8) reg);
647 local_bh_enable();
648 return res;
649}
650
651static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
652{
653 struct ocp_enet_private *dev = ndev->priv;
654
655 local_bh_disable();
656 __emac_mdio_write(dev->mdio_dev ? dev->mdio_dev : dev, (u8) id,
657 (u8) reg, (u16) val);
658 local_bh_enable();
659}
660
661/* BHs disabled */
662static void emac_set_multicast_list(struct net_device *ndev)
663{
664 struct ocp_enet_private *dev = ndev->priv;
665 struct emac_regs __iomem *p = dev->emacp;
666 u32 rmr = emac_iff2rmr(ndev);
667
668 DBG("%d: multicast %08x" NL, dev->def->index, rmr);
669 BUG_ON(!netif_running(dev->ndev));
670
671 /* I decided to relax register access rules here to avoid
672 * full EMAC reset.
673 *
674 * There is a real problem with EMAC4 core if we use MWSW_001 bit
675 * in MR1 register and do a full EMAC reset.
676 * One TX BD status update is delayed and, after EMAC reset, it
677 * never happens, resulting in TX hung (it'll be recovered by TX
678 * timeout handler eventually, but this is just gross).
679 * So we either have to do full TX reset or try to cheat here :)
680 *
681 * The only required change is to RX mode register, so I *think* all
682 * we need is just to stop RX channel. This seems to work on all
683 * tested SoCs. --ebs
684 */
685 emac_rx_disable(dev);
686 if (rmr & EMAC_RMR_MAE)
687 emac_hash_mc(dev);
688 out_be32(&p->rmr, rmr);
689 emac_rx_enable(dev);
690}
691
692/* BHs disabled */
693static int emac_resize_rx_ring(struct ocp_enet_private *dev, int new_mtu)
694{
695 struct ocp_func_emac_data *emacdata = dev->def->additions;
696 int rx_sync_size = emac_rx_sync_size(new_mtu);
697 int rx_skb_size = emac_rx_skb_size(new_mtu);
698 int i, ret = 0;
699
700 emac_rx_disable(dev);
701 mal_disable_rx_channel(dev->mal, emacdata->mal_rx_chan);
702
703 if (dev->rx_sg_skb) {
704 ++dev->estats.rx_dropped_resize;
705 dev_kfree_skb(dev->rx_sg_skb);
706 dev->rx_sg_skb = NULL;
707 }
708
709 /* Make a first pass over RX ring and mark BDs ready, dropping
710 * non-processed packets on the way. We need this as a separate pass
711 * to simplify error recovery in the case of allocation failure later.
712 */
713 for (i = 0; i < NUM_RX_BUFF; ++i) {
714 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
715 ++dev->estats.rx_dropped_resize;
716
717 dev->rx_desc[i].data_len = 0;
718 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
719 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
720 }
721
722 /* Reallocate RX ring only if bigger skb buffers are required */
723 if (rx_skb_size <= dev->rx_skb_size)
724 goto skip;
725
726 /* Second pass, allocate new skbs */
727 for (i = 0; i < NUM_RX_BUFF; ++i) {
728 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
729 if (!skb) {
730 ret = -ENOMEM;
731 goto oom;
732 }
733
734 BUG_ON(!dev->rx_skb[i]);
735 dev_kfree_skb(dev->rx_skb[i]);
736
737 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
738 dev->rx_desc[i].data_ptr =
739 dma_map_single(dev->ldev, skb->data - 2, rx_sync_size,
740 DMA_FROM_DEVICE) + 2;
741 dev->rx_skb[i] = skb;
742 }
743 skip:
744 /* Check if we need to change "Jumbo" bit in MR1 */
745 if ((new_mtu > ETH_DATA_LEN) ^ (dev->ndev->mtu > ETH_DATA_LEN)) {
746 /* This is to prevent starting RX channel in emac_rx_enable() */
747 dev->commac.rx_stopped = 1;
748
749 dev->ndev->mtu = new_mtu;
750 emac_full_tx_reset(dev->ndev);
751 }
752
753 mal_set_rcbs(dev->mal, emacdata->mal_rx_chan, emac_rx_size(new_mtu));
754 oom:
755 /* Restart RX */
756 dev->commac.rx_stopped = dev->rx_slot = 0;
757 mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
758 emac_rx_enable(dev);
759
760 return ret;
761}
762
763/* Process ctx, rtnl_lock semaphore */
764static int emac_change_mtu(struct net_device *ndev, int new_mtu)
765{
766 struct ocp_enet_private *dev = ndev->priv;
767 int ret = 0;
768
769 if (new_mtu < EMAC_MIN_MTU || new_mtu > EMAC_MAX_MTU)
770 return -EINVAL;
771
772 DBG("%d: change_mtu(%d)" NL, dev->def->index, new_mtu);
773
774 local_bh_disable();
775 if (netif_running(ndev)) {
776 /* Check if we really need to reinitalize RX ring */
777 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
778 ret = emac_resize_rx_ring(dev, new_mtu);
779 }
780
781 if (!ret) {
782 ndev->mtu = new_mtu;
783 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
784 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
785 }
786 local_bh_enable();
787
788 return ret;
789}
790
791static void emac_clean_tx_ring(struct ocp_enet_private *dev)
792{
793 int i;
794 for (i = 0; i < NUM_TX_BUFF; ++i) {
795 if (dev->tx_skb[i]) {
796 dev_kfree_skb(dev->tx_skb[i]);
797 dev->tx_skb[i] = NULL;
798 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
799 ++dev->estats.tx_dropped;
800 }
801 dev->tx_desc[i].ctrl = 0;
802 dev->tx_desc[i].data_ptr = 0;
803 }
804}
805
806static void emac_clean_rx_ring(struct ocp_enet_private *dev)
807{
808 int i;
809 for (i = 0; i < NUM_RX_BUFF; ++i)
810 if (dev->rx_skb[i]) {
811 dev->rx_desc[i].ctrl = 0;
812 dev_kfree_skb(dev->rx_skb[i]);
813 dev->rx_skb[i] = NULL;
814 dev->rx_desc[i].data_ptr = 0;
815 }
816
817 if (dev->rx_sg_skb) {
818 dev_kfree_skb(dev->rx_sg_skb);
819 dev->rx_sg_skb = NULL;
820 }
821}
822
823static inline int emac_alloc_rx_skb(struct ocp_enet_private *dev, int slot,
824 gfp_t flags)
825{
826 struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
827 if (unlikely(!skb))
828 return -ENOMEM;
829
830 dev->rx_skb[slot] = skb;
831 dev->rx_desc[slot].data_len = 0;
832
833 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
834 dev->rx_desc[slot].data_ptr =
835 dma_map_single(dev->ldev, skb->data - 2, dev->rx_sync_size,
836 DMA_FROM_DEVICE) + 2;
837 barrier();
838 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
839 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
840
841 return 0;
842}
843
844static void emac_print_link_status(struct ocp_enet_private *dev)
845{
846 if (netif_carrier_ok(dev->ndev))
847 printk(KERN_INFO "%s: link is up, %d %s%s\n",
848 dev->ndev->name, dev->phy.speed,
849 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
850 dev->phy.pause ? ", pause enabled" :
851 dev->phy.asym_pause ? ", assymetric pause enabled" : "");
852 else
853 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
854}
855
856/* Process ctx, rtnl_lock semaphore */
857static int emac_open(struct net_device *ndev)
858{
859 struct ocp_enet_private *dev = ndev->priv;
860 struct ocp_func_emac_data *emacdata = dev->def->additions;
861 int err, i;
862
863 DBG("%d: open" NL, dev->def->index);
864
865 /* Setup error IRQ handler */
866 err = request_irq(dev->def->irq, emac_irq, 0, "EMAC", dev);
867 if (err) {
868 printk(KERN_ERR "%s: failed to request IRQ %d\n",
869 ndev->name, dev->def->irq);
870 return err;
871 }
872
873 /* Allocate RX ring */
874 for (i = 0; i < NUM_RX_BUFF; ++i)
875 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
876 printk(KERN_ERR "%s: failed to allocate RX ring\n",
877 ndev->name);
878 goto oom;
879 }
880
881 local_bh_disable();
882 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot =
883 dev->commac.rx_stopped = 0;
884 dev->rx_sg_skb = NULL;
885
886 if (dev->phy.address >= 0) {
887 int link_poll_interval;
888 if (dev->phy.def->ops->poll_link(&dev->phy)) {
889 dev->phy.def->ops->read_link(&dev->phy);
890 EMAC_RX_CLK_DEFAULT(dev->def->index);
891 netif_carrier_on(dev->ndev);
892 link_poll_interval = PHY_POLL_LINK_ON;
893 } else {
894 EMAC_RX_CLK_TX(dev->def->index);
895 netif_carrier_off(dev->ndev);
896 link_poll_interval = PHY_POLL_LINK_OFF;
897 }
898 mod_timer(&dev->link_timer, jiffies + link_poll_interval);
899 emac_print_link_status(dev);
900 } else
901 netif_carrier_on(dev->ndev);
902
903 emac_configure(dev);
904 mal_poll_add(dev->mal, &dev->commac);
905 mal_enable_tx_channel(dev->mal, emacdata->mal_tx_chan);
906 mal_set_rcbs(dev->mal, emacdata->mal_rx_chan, emac_rx_size(ndev->mtu));
907 mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
908 emac_tx_enable(dev);
909 emac_rx_enable(dev);
910 netif_start_queue(ndev);
911 local_bh_enable();
912
913 return 0;
914 oom:
915 emac_clean_rx_ring(dev);
916 free_irq(dev->def->irq, dev);
917 return -ENOMEM;
918}
919
920/* BHs disabled */
921static int emac_link_differs(struct ocp_enet_private *dev)
922{
923 u32 r = in_be32(&dev->emacp->mr1);
924
925 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
926 int speed, pause, asym_pause;
927
928 if (r & EMAC_MR1_MF_1000)
929 speed = SPEED_1000;
930 else if (r & EMAC_MR1_MF_100)
931 speed = SPEED_100;
932 else
933 speed = SPEED_10;
934
935 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
936 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
937 pause = 1;
938 asym_pause = 0;
939 break;
940 case EMAC_MR1_APP:
941 pause = 0;
942 asym_pause = 1;
943 break;
944 default:
945 pause = asym_pause = 0;
946 }
947 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
948 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
949}
950
951/* BHs disabled */
952static void emac_link_timer(unsigned long data)
953{
954 struct ocp_enet_private *dev = (struct ocp_enet_private *)data;
955 int link_poll_interval;
956
957 DBG2("%d: link timer" NL, dev->def->index);
958
959 if (dev->phy.def->ops->poll_link(&dev->phy)) {
960 if (!netif_carrier_ok(dev->ndev)) {
961 EMAC_RX_CLK_DEFAULT(dev->def->index);
962
963 /* Get new link parameters */
964 dev->phy.def->ops->read_link(&dev->phy);
965
966 if (dev->tah_dev || emac_link_differs(dev))
967 emac_full_tx_reset(dev->ndev);
968
969 netif_carrier_on(dev->ndev);
970 emac_print_link_status(dev);
971 }
972 link_poll_interval = PHY_POLL_LINK_ON;
973 } else {
974 if (netif_carrier_ok(dev->ndev)) {
975 EMAC_RX_CLK_TX(dev->def->index);
976#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX)
977 emac_reinitialize(dev);
978#endif
979 netif_carrier_off(dev->ndev);
980 emac_print_link_status(dev);
981 }
982
983 /* Retry reset if the previous attempt failed.
984 * This is needed mostly for CONFIG_IBM_EMAC_PHY_RX_CLK_FIX
985 * case, but I left it here because it shouldn't trigger for
986 * sane PHYs anyway.
987 */
988 if (unlikely(dev->reset_failed))
989 emac_reinitialize(dev);
990
991 link_poll_interval = PHY_POLL_LINK_OFF;
992 }
993 mod_timer(&dev->link_timer, jiffies + link_poll_interval);
994}
995
996/* BHs disabled */
997static void emac_force_link_update(struct ocp_enet_private *dev)
998{
999 netif_carrier_off(dev->ndev);
1000 if (timer_pending(&dev->link_timer))
1001 mod_timer(&dev->link_timer, jiffies + PHY_POLL_LINK_OFF);
1002}
1003
1004/* Process ctx, rtnl_lock semaphore */
1005static int emac_close(struct net_device *ndev)
1006{
1007 struct ocp_enet_private *dev = ndev->priv;
1008 struct ocp_func_emac_data *emacdata = dev->def->additions;
1009
1010 DBG("%d: close" NL, dev->def->index);
1011
1012 local_bh_disable();
1013
1014 if (dev->phy.address >= 0)
1015 del_timer_sync(&dev->link_timer);
1016
1017 netif_stop_queue(ndev);
1018 emac_rx_disable(dev);
1019 emac_tx_disable(dev);
1020 mal_disable_rx_channel(dev->mal, emacdata->mal_rx_chan);
1021 mal_disable_tx_channel(dev->mal, emacdata->mal_tx_chan);
1022 mal_poll_del(dev->mal, &dev->commac);
1023 local_bh_enable();
1024
1025 emac_clean_tx_ring(dev);
1026 emac_clean_rx_ring(dev);
1027 free_irq(dev->def->irq, dev);
1028
1029 return 0;
1030}
1031
1032static inline u16 emac_tx_csum(struct ocp_enet_private *dev,
1033 struct sk_buff *skb)
1034{
1035#if defined(CONFIG_IBM_EMAC_TAH)
1036 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1037 ++dev->stats.tx_packets_csum;
1038 return EMAC_TX_CTRL_TAH_CSUM;
1039 }
1040#endif
1041 return 0;
1042}
1043
1044static inline int emac_xmit_finish(struct ocp_enet_private *dev, int len)
1045{
1046 struct emac_regs __iomem *p = dev->emacp;
1047 struct net_device *ndev = dev->ndev;
1048
1049 /* Send the packet out */
1050 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1051
1052 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1053 netif_stop_queue(ndev);
1054 DBG2("%d: stopped TX queue" NL, dev->def->index);
1055 }
1056
1057 ndev->trans_start = jiffies;
1058 ++dev->stats.tx_packets;
1059 dev->stats.tx_bytes += len;
1060
1061 return 0;
1062}
1063
1064/* BHs disabled */
1065static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1066{
1067 struct ocp_enet_private *dev = ndev->priv;
1068 unsigned int len = skb->len;
1069 int slot;
1070
1071 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1072 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1073
1074 slot = dev->tx_slot++;
1075 if (dev->tx_slot == NUM_TX_BUFF) {
1076 dev->tx_slot = 0;
1077 ctrl |= MAL_TX_CTRL_WRAP;
1078 }
1079
1080 DBG2("%d: xmit(%u) %d" NL, dev->def->index, len, slot);
1081
1082 dev->tx_skb[slot] = skb;
1083 dev->tx_desc[slot].data_ptr = dma_map_single(dev->ldev, skb->data, len,
1084 DMA_TO_DEVICE);
1085 dev->tx_desc[slot].data_len = (u16) len;
1086 barrier();
1087 dev->tx_desc[slot].ctrl = ctrl;
1088
1089 return emac_xmit_finish(dev, len);
1090}
1091
1092#if defined(CONFIG_IBM_EMAC_TAH)
1093static inline int emac_xmit_split(struct ocp_enet_private *dev, int slot,
1094 u32 pd, int len, int last, u16 base_ctrl)
1095{
1096 while (1) {
1097 u16 ctrl = base_ctrl;
1098 int chunk = min(len, MAL_MAX_TX_SIZE);
1099 len -= chunk;
1100
1101 slot = (slot + 1) % NUM_TX_BUFF;
1102
1103 if (last && !len)
1104 ctrl |= MAL_TX_CTRL_LAST;
1105 if (slot == NUM_TX_BUFF - 1)
1106 ctrl |= MAL_TX_CTRL_WRAP;
1107
1108 dev->tx_skb[slot] = NULL;
1109 dev->tx_desc[slot].data_ptr = pd;
1110 dev->tx_desc[slot].data_len = (u16) chunk;
1111 dev->tx_desc[slot].ctrl = ctrl;
1112 ++dev->tx_cnt;
1113
1114 if (!len)
1115 break;
1116
1117 pd += chunk;
1118 }
1119 return slot;
1120}
1121
1122/* BHs disabled (SG version for TAH equipped EMACs) */
1123static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1124{
1125 struct ocp_enet_private *dev = ndev->priv;
1126 int nr_frags = skb_shinfo(skb)->nr_frags;
1127 int len = skb->len, chunk;
1128 int slot, i;
1129 u16 ctrl;
1130 u32 pd;
1131
1132 /* This is common "fast" path */
1133 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1134 return emac_start_xmit(skb, ndev);
1135
1136 len -= skb->data_len;
1137
1138 /* Note, this is only an *estimation*, we can still run out of empty
1139 * slots because of the additional fragmentation into
1140 * MAL_MAX_TX_SIZE-sized chunks
1141 */
1142 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1143 goto stop_queue;
1144
1145 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1146 emac_tx_csum(dev, skb);
1147 slot = dev->tx_slot;
1148
1149 /* skb data */
1150 dev->tx_skb[slot] = NULL;
1151 chunk = min(len, MAL_MAX_TX_SIZE);
1152 dev->tx_desc[slot].data_ptr = pd =
1153 dma_map_single(dev->ldev, skb->data, len, DMA_TO_DEVICE);
1154 dev->tx_desc[slot].data_len = (u16) chunk;
1155 len -= chunk;
1156 if (unlikely(len))
1157 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1158 ctrl);
1159 /* skb fragments */
1160 for (i = 0; i < nr_frags; ++i) {
1161 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1162 len = frag->size;
1163
1164 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1165 goto undo_frame;
1166
1167 pd = dma_map_page(dev->ldev, frag->page, frag->page_offset, len,
1168 DMA_TO_DEVICE);
1169
1170 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1171 ctrl);
1172 }
1173
1174 DBG2("%d: xmit_sg(%u) %d - %d" NL, dev->def->index, skb->len,
1175 dev->tx_slot, slot);
1176
1177 /* Attach skb to the last slot so we don't release it too early */
1178 dev->tx_skb[slot] = skb;
1179
1180 /* Send the packet out */
1181 if (dev->tx_slot == NUM_TX_BUFF - 1)
1182 ctrl |= MAL_TX_CTRL_WRAP;
1183 barrier();
1184 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1185 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1186
1187 return emac_xmit_finish(dev, skb->len);
1188
1189 undo_frame:
1190 /* Well, too bad. Our previous estimation was overly optimistic.
1191 * Undo everything.
1192 */
1193 while (slot != dev->tx_slot) {
1194 dev->tx_desc[slot].ctrl = 0;
1195 --dev->tx_cnt;
1196 if (--slot < 0)
1197 slot = NUM_TX_BUFF - 1;
1198 }
1199 ++dev->estats.tx_undo;
1200
1201 stop_queue:
1202 netif_stop_queue(ndev);
1203 DBG2("%d: stopped TX queue" NL, dev->def->index);
1204 return 1;
1205}
1206#else
1207# define emac_start_xmit_sg emac_start_xmit
1208#endif /* !defined(CONFIG_IBM_EMAC_TAH) */
1209
1210/* BHs disabled */
1211static void emac_parse_tx_error(struct ocp_enet_private *dev, u16 ctrl)
1212{
1213 struct ibm_emac_error_stats *st = &dev->estats;
1214 DBG("%d: BD TX error %04x" NL, dev->def->index, ctrl);
1215
1216 ++st->tx_bd_errors;
1217 if (ctrl & EMAC_TX_ST_BFCS)
1218 ++st->tx_bd_bad_fcs;
1219 if (ctrl & EMAC_TX_ST_LCS)
1220 ++st->tx_bd_carrier_loss;
1221 if (ctrl & EMAC_TX_ST_ED)
1222 ++st->tx_bd_excessive_deferral;
1223 if (ctrl & EMAC_TX_ST_EC)
1224 ++st->tx_bd_excessive_collisions;
1225 if (ctrl & EMAC_TX_ST_LC)
1226 ++st->tx_bd_late_collision;
1227 if (ctrl & EMAC_TX_ST_MC)
1228 ++st->tx_bd_multple_collisions;
1229 if (ctrl & EMAC_TX_ST_SC)
1230 ++st->tx_bd_single_collision;
1231 if (ctrl & EMAC_TX_ST_UR)
1232 ++st->tx_bd_underrun;
1233 if (ctrl & EMAC_TX_ST_SQE)
1234 ++st->tx_bd_sqe;
1235}
1236
1237static void emac_poll_tx(void *param)
1238{
1239 struct ocp_enet_private *dev = param;
1240 DBG2("%d: poll_tx, %d %d" NL, dev->def->index, dev->tx_cnt,
1241 dev->ack_slot);
1242
1243 if (dev->tx_cnt) {
1244 u16 ctrl;
1245 int slot = dev->ack_slot, n = 0;
1246 again:
1247 ctrl = dev->tx_desc[slot].ctrl;
1248 if (!(ctrl & MAL_TX_CTRL_READY)) {
1249 struct sk_buff *skb = dev->tx_skb[slot];
1250 ++n;
1251
1252 if (skb) {
1253 dev_kfree_skb(skb);
1254 dev->tx_skb[slot] = NULL;
1255 }
1256 slot = (slot + 1) % NUM_TX_BUFF;
1257
1258 if (unlikely(EMAC_IS_BAD_TX(ctrl)))
1259 emac_parse_tx_error(dev, ctrl);
1260
1261 if (--dev->tx_cnt)
1262 goto again;
1263 }
1264 if (n) {
1265 dev->ack_slot = slot;
1266 if (netif_queue_stopped(dev->ndev) &&
1267 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1268 netif_wake_queue(dev->ndev);
1269
1270 DBG2("%d: tx %d pkts" NL, dev->def->index, n);
1271 }
1272 }
1273}
1274
1275static inline void emac_recycle_rx_skb(struct ocp_enet_private *dev, int slot,
1276 int len)
1277{
1278 struct sk_buff *skb = dev->rx_skb[slot];
1279 DBG2("%d: recycle %d %d" NL, dev->def->index, slot, len);
1280
1281 if (len)
1282 dma_map_single(dev->ldev, skb->data - 2,
1283 EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
1284
1285 dev->rx_desc[slot].data_len = 0;
1286 barrier();
1287 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1288 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1289}
1290
1291static void emac_parse_rx_error(struct ocp_enet_private *dev, u16 ctrl)
1292{
1293 struct ibm_emac_error_stats *st = &dev->estats;
1294 DBG("%d: BD RX error %04x" NL, dev->def->index, ctrl);
1295
1296 ++st->rx_bd_errors;
1297 if (ctrl & EMAC_RX_ST_OE)
1298 ++st->rx_bd_overrun;
1299 if (ctrl & EMAC_RX_ST_BP)
1300 ++st->rx_bd_bad_packet;
1301 if (ctrl & EMAC_RX_ST_RP)
1302 ++st->rx_bd_runt_packet;
1303 if (ctrl & EMAC_RX_ST_SE)
1304 ++st->rx_bd_short_event;
1305 if (ctrl & EMAC_RX_ST_AE)
1306 ++st->rx_bd_alignment_error;
1307 if (ctrl & EMAC_RX_ST_BFCS)
1308 ++st->rx_bd_bad_fcs;
1309 if (ctrl & EMAC_RX_ST_PTL)
1310 ++st->rx_bd_packet_too_long;
1311 if (ctrl & EMAC_RX_ST_ORE)
1312 ++st->rx_bd_out_of_range;
1313 if (ctrl & EMAC_RX_ST_IRE)
1314 ++st->rx_bd_in_range;
1315}
1316
1317static inline void emac_rx_csum(struct ocp_enet_private *dev,
1318 struct sk_buff *skb, u16 ctrl)
1319{
1320#if defined(CONFIG_IBM_EMAC_TAH)
1321 if (!ctrl && dev->tah_dev) {
1322 skb->ip_summed = CHECKSUM_UNNECESSARY;
1323 ++dev->stats.rx_packets_csum;
1324 }
1325#endif
1326}
1327
1328static inline int emac_rx_sg_append(struct ocp_enet_private *dev, int slot)
1329{
1330 if (likely(dev->rx_sg_skb != NULL)) {
1331 int len = dev->rx_desc[slot].data_len;
1332 int tot_len = dev->rx_sg_skb->len + len;
1333
1334 if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
1335 ++dev->estats.rx_dropped_mtu;
1336 dev_kfree_skb(dev->rx_sg_skb);
1337 dev->rx_sg_skb = NULL;
1338 } else {
1339 cacheable_memcpy(skb_tail_pointer(dev->rx_sg_skb),
1340 dev->rx_skb[slot]->data, len);
1341 skb_put(dev->rx_sg_skb, len);
1342 emac_recycle_rx_skb(dev, slot, len);
1343 return 0;
1344 }
1345 }
1346 emac_recycle_rx_skb(dev, slot, 0);
1347 return -1;
1348}
1349
1350/* BHs disabled */
1351static int emac_poll_rx(void *param, int budget)
1352{
1353 struct ocp_enet_private *dev = param;
1354 int slot = dev->rx_slot, received = 0;
1355
1356 DBG2("%d: poll_rx(%d)" NL, dev->def->index, budget);
1357
1358 again:
1359 while (budget > 0) {
1360 int len;
1361 struct sk_buff *skb;
1362 u16 ctrl = dev->rx_desc[slot].ctrl;
1363
1364 if (ctrl & MAL_RX_CTRL_EMPTY)
1365 break;
1366
1367 skb = dev->rx_skb[slot];
1368 barrier();
1369 len = dev->rx_desc[slot].data_len;
1370
1371 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1372 goto sg;
1373
1374 ctrl &= EMAC_BAD_RX_MASK;
1375 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1376 emac_parse_rx_error(dev, ctrl);
1377 ++dev->estats.rx_dropped_error;
1378 emac_recycle_rx_skb(dev, slot, 0);
1379 len = 0;
1380 goto next;
1381 }
1382
1383 if (len && len < EMAC_RX_COPY_THRESH) {
1384 struct sk_buff *copy_skb =
1385 alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
1386 if (unlikely(!copy_skb))
1387 goto oom;
1388
1389 skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
1390 cacheable_memcpy(copy_skb->data - 2, skb->data - 2,
1391 len + 2);
1392 emac_recycle_rx_skb(dev, slot, len);
1393 skb = copy_skb;
1394 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
1395 goto oom;
1396
1397 skb_put(skb, len);
1398 push_packet:
1399 skb->protocol = eth_type_trans(skb, dev->ndev);
1400 emac_rx_csum(dev, skb, ctrl);
1401
1402 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1403 ++dev->estats.rx_dropped_stack;
1404 next:
1405 ++dev->stats.rx_packets;
1406 skip:
1407 dev->stats.rx_bytes += len;
1408 slot = (slot + 1) % NUM_RX_BUFF;
1409 --budget;
1410 ++received;
1411 continue;
1412 sg:
1413 if (ctrl & MAL_RX_CTRL_FIRST) {
1414 BUG_ON(dev->rx_sg_skb);
1415 if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
1416 DBG("%d: rx OOM %d" NL, dev->def->index, slot);
1417 ++dev->estats.rx_dropped_oom;
1418 emac_recycle_rx_skb(dev, slot, 0);
1419 } else {
1420 dev->rx_sg_skb = skb;
1421 skb_put(skb, len);
1422 }
1423 } else if (!emac_rx_sg_append(dev, slot) &&
1424 (ctrl & MAL_RX_CTRL_LAST)) {
1425
1426 skb = dev->rx_sg_skb;
1427 dev->rx_sg_skb = NULL;
1428
1429 ctrl &= EMAC_BAD_RX_MASK;
1430 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1431 emac_parse_rx_error(dev, ctrl);
1432 ++dev->estats.rx_dropped_error;
1433 dev_kfree_skb(skb);
1434 len = 0;
1435 } else
1436 goto push_packet;
1437 }
1438 goto skip;
1439 oom:
1440 DBG("%d: rx OOM %d" NL, dev->def->index, slot);
1441 /* Drop the packet and recycle skb */
1442 ++dev->estats.rx_dropped_oom;
1443 emac_recycle_rx_skb(dev, slot, 0);
1444 goto next;
1445 }
1446
1447 if (received) {
1448 DBG2("%d: rx %d BDs" NL, dev->def->index, received);
1449 dev->rx_slot = slot;
1450 }
1451
1452 if (unlikely(budget && dev->commac.rx_stopped)) {
1453 struct ocp_func_emac_data *emacdata = dev->def->additions;
1454
1455 barrier();
1456 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1457 DBG2("%d: rx restart" NL, dev->def->index);
1458 received = 0;
1459 goto again;
1460 }
1461
1462 if (dev->rx_sg_skb) {
1463 DBG2("%d: dropping partial rx packet" NL,
1464 dev->def->index);
1465 ++dev->estats.rx_dropped_error;
1466 dev_kfree_skb(dev->rx_sg_skb);
1467 dev->rx_sg_skb = NULL;
1468 }
1469
1470 dev->commac.rx_stopped = 0;
1471 mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
1472 emac_rx_enable(dev);
1473 dev->rx_slot = 0;
1474 }
1475 return received;
1476}
1477
1478/* BHs disabled */
1479static int emac_peek_rx(void *param)
1480{
1481 struct ocp_enet_private *dev = param;
1482 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1483}
1484
1485/* BHs disabled */
1486static int emac_peek_rx_sg(void *param)
1487{
1488 struct ocp_enet_private *dev = param;
1489 int slot = dev->rx_slot;
1490 while (1) {
1491 u16 ctrl = dev->rx_desc[slot].ctrl;
1492 if (ctrl & MAL_RX_CTRL_EMPTY)
1493 return 0;
1494 else if (ctrl & MAL_RX_CTRL_LAST)
1495 return 1;
1496
1497 slot = (slot + 1) % NUM_RX_BUFF;
1498
1499 /* I'm just being paranoid here :) */
1500 if (unlikely(slot == dev->rx_slot))
1501 return 0;
1502 }
1503}
1504
1505/* Hard IRQ */
1506static void emac_rxde(void *param)
1507{
1508 struct ocp_enet_private *dev = param;
1509 ++dev->estats.rx_stopped;
1510 emac_rx_disable_async(dev);
1511}
1512
1513/* Hard IRQ */
1514static irqreturn_t emac_irq(int irq, void *dev_instance)
1515{
1516 struct ocp_enet_private *dev = dev_instance;
1517 struct emac_regs __iomem *p = dev->emacp;
1518 struct ibm_emac_error_stats *st = &dev->estats;
1519
1520 u32 isr = in_be32(&p->isr);
1521 out_be32(&p->isr, isr);
1522
1523 DBG("%d: isr = %08x" NL, dev->def->index, isr);
1524
1525 if (isr & EMAC_ISR_TXPE)
1526 ++st->tx_parity;
1527 if (isr & EMAC_ISR_RXPE)
1528 ++st->rx_parity;
1529 if (isr & EMAC_ISR_TXUE)
1530 ++st->tx_underrun;
1531 if (isr & EMAC_ISR_RXOE)
1532 ++st->rx_fifo_overrun;
1533 if (isr & EMAC_ISR_OVR)
1534 ++st->rx_overrun;
1535 if (isr & EMAC_ISR_BP)
1536 ++st->rx_bad_packet;
1537 if (isr & EMAC_ISR_RP)
1538 ++st->rx_runt_packet;
1539 if (isr & EMAC_ISR_SE)
1540 ++st->rx_short_event;
1541 if (isr & EMAC_ISR_ALE)
1542 ++st->rx_alignment_error;
1543 if (isr & EMAC_ISR_BFCS)
1544 ++st->rx_bad_fcs;
1545 if (isr & EMAC_ISR_PTLE)
1546 ++st->rx_packet_too_long;
1547 if (isr & EMAC_ISR_ORE)
1548 ++st->rx_out_of_range;
1549 if (isr & EMAC_ISR_IRE)
1550 ++st->rx_in_range;
1551 if (isr & EMAC_ISR_SQE)
1552 ++st->tx_sqe;
1553 if (isr & EMAC_ISR_TE)
1554 ++st->tx_errors;
1555
1556 return IRQ_HANDLED;
1557}
1558
1559static struct net_device_stats *emac_stats(struct net_device *ndev)
1560{
1561 struct ocp_enet_private *dev = ndev->priv;
1562 struct ibm_emac_stats *st = &dev->stats;
1563 struct ibm_emac_error_stats *est = &dev->estats;
1564 struct net_device_stats *nst = &dev->nstats;
1565
1566 DBG2("%d: stats" NL, dev->def->index);
1567
1568 /* Compute "legacy" statistics */
1569 local_irq_disable();
1570 nst->rx_packets = (unsigned long)st->rx_packets;
1571 nst->rx_bytes = (unsigned long)st->rx_bytes;
1572 nst->tx_packets = (unsigned long)st->tx_packets;
1573 nst->tx_bytes = (unsigned long)st->tx_bytes;
1574 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1575 est->rx_dropped_error +
1576 est->rx_dropped_resize +
1577 est->rx_dropped_mtu);
1578 nst->tx_dropped = (unsigned long)est->tx_dropped;
1579
1580 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1581 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1582 est->rx_fifo_overrun +
1583 est->rx_overrun);
1584 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1585 est->rx_alignment_error);
1586 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1587 est->rx_bad_fcs);
1588 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1589 est->rx_bd_short_event +
1590 est->rx_bd_packet_too_long +
1591 est->rx_bd_out_of_range +
1592 est->rx_bd_in_range +
1593 est->rx_runt_packet +
1594 est->rx_short_event +
1595 est->rx_packet_too_long +
1596 est->rx_out_of_range +
1597 est->rx_in_range);
1598
1599 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1600 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1601 est->tx_underrun);
1602 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1603 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1604 est->tx_bd_excessive_collisions +
1605 est->tx_bd_late_collision +
1606 est->tx_bd_multple_collisions);
1607 local_irq_enable();
1608 return nst;
1609}
1610
1611static void emac_remove(struct ocp_device *ocpdev)
1612{
1613 struct ocp_enet_private *dev = ocp_get_drvdata(ocpdev);
1614
1615 DBG("%d: remove" NL, dev->def->index);
1616
1617 ocp_set_drvdata(ocpdev, NULL);
1618 unregister_netdev(dev->ndev);
1619
1620 tah_fini(dev->tah_dev);
1621 rgmii_fini(dev->rgmii_dev, dev->rgmii_input);
1622 zmii_fini(dev->zmii_dev, dev->zmii_input);
1623
1624 emac_dbg_register(dev->def->index, NULL);
1625
1626 mal_unregister_commac(dev->mal, &dev->commac);
1627 iounmap(dev->emacp);
1628 kfree(dev->ndev);
1629}
1630
1631static struct mal_commac_ops emac_commac_ops = {
1632 .poll_tx = &emac_poll_tx,
1633 .poll_rx = &emac_poll_rx,
1634 .peek_rx = &emac_peek_rx,
1635 .rxde = &emac_rxde,
1636};
1637
1638static struct mal_commac_ops emac_commac_sg_ops = {
1639 .poll_tx = &emac_poll_tx,
1640 .poll_rx = &emac_poll_rx,
1641 .peek_rx = &emac_peek_rx_sg,
1642 .rxde = &emac_rxde,
1643};
1644
1645/* Ethtool support */
1646static int emac_ethtool_get_settings(struct net_device *ndev,
1647 struct ethtool_cmd *cmd)
1648{
1649 struct ocp_enet_private *dev = ndev->priv;
1650
1651 cmd->supported = dev->phy.features;
1652 cmd->port = PORT_MII;
1653 cmd->phy_address = dev->phy.address;
1654 cmd->transceiver =
1655 dev->phy.address >= 0 ? XCVR_EXTERNAL : XCVR_INTERNAL;
1656
1657 local_bh_disable();
1658 cmd->advertising = dev->phy.advertising;
1659 cmd->autoneg = dev->phy.autoneg;
1660 cmd->speed = dev->phy.speed;
1661 cmd->duplex = dev->phy.duplex;
1662 local_bh_enable();
1663
1664 return 0;
1665}
1666
1667static int emac_ethtool_set_settings(struct net_device *ndev,
1668 struct ethtool_cmd *cmd)
1669{
1670 struct ocp_enet_private *dev = ndev->priv;
1671 u32 f = dev->phy.features;
1672
1673 DBG("%d: set_settings(%d, %d, %d, 0x%08x)" NL, dev->def->index,
1674 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1675
1676 /* Basic sanity checks */
1677 if (dev->phy.address < 0)
1678 return -EOPNOTSUPP;
1679 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1680 return -EINVAL;
1681 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1682 return -EINVAL;
1683 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1684 return -EINVAL;
1685
1686 if (cmd->autoneg == AUTONEG_DISABLE) {
1687 switch (cmd->speed) {
1688 case SPEED_10:
1689 if (cmd->duplex == DUPLEX_HALF
1690 && !(f & SUPPORTED_10baseT_Half))
1691 return -EINVAL;
1692 if (cmd->duplex == DUPLEX_FULL
1693 && !(f & SUPPORTED_10baseT_Full))
1694 return -EINVAL;
1695 break;
1696 case SPEED_100:
1697 if (cmd->duplex == DUPLEX_HALF
1698 && !(f & SUPPORTED_100baseT_Half))
1699 return -EINVAL;
1700 if (cmd->duplex == DUPLEX_FULL
1701 && !(f & SUPPORTED_100baseT_Full))
1702 return -EINVAL;
1703 break;
1704 case SPEED_1000:
1705 if (cmd->duplex == DUPLEX_HALF
1706 && !(f & SUPPORTED_1000baseT_Half))
1707 return -EINVAL;
1708 if (cmd->duplex == DUPLEX_FULL
1709 && !(f & SUPPORTED_1000baseT_Full))
1710 return -EINVAL;
1711 break;
1712 default:
1713 return -EINVAL;
1714 }
1715
1716 local_bh_disable();
1717 dev->phy.def->ops->setup_forced(&dev->phy, cmd->speed,
1718 cmd->duplex);
1719
1720 } else {
1721 if (!(f & SUPPORTED_Autoneg))
1722 return -EINVAL;
1723
1724 local_bh_disable();
1725 dev->phy.def->ops->setup_aneg(&dev->phy,
1726 (cmd->advertising & f) |
1727 (dev->phy.advertising &
1728 (ADVERTISED_Pause |
1729 ADVERTISED_Asym_Pause)));
1730 }
1731 emac_force_link_update(dev);
1732 local_bh_enable();
1733
1734 return 0;
1735}
1736
1737static void emac_ethtool_get_ringparam(struct net_device *ndev,
1738 struct ethtool_ringparam *rp)
1739{
1740 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
1741 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
1742}
1743
1744static void emac_ethtool_get_pauseparam(struct net_device *ndev,
1745 struct ethtool_pauseparam *pp)
1746{
1747 struct ocp_enet_private *dev = ndev->priv;
1748
1749 local_bh_disable();
1750 if ((dev->phy.features & SUPPORTED_Autoneg) &&
1751 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
1752 pp->autoneg = 1;
1753
1754 if (dev->phy.duplex == DUPLEX_FULL) {
1755 if (dev->phy.pause)
1756 pp->rx_pause = pp->tx_pause = 1;
1757 else if (dev->phy.asym_pause)
1758 pp->tx_pause = 1;
1759 }
1760 local_bh_enable();
1761}
1762
1763static u32 emac_ethtool_get_rx_csum(struct net_device *ndev)
1764{
1765 struct ocp_enet_private *dev = ndev->priv;
1766 return dev->tah_dev != 0;
1767}
1768
1769static int emac_get_regs_len(struct ocp_enet_private *dev)
1770{
1771 return sizeof(struct emac_ethtool_regs_subhdr) + EMAC_ETHTOOL_REGS_SIZE;
1772}
1773
1774static int emac_ethtool_get_regs_len(struct net_device *ndev)
1775{
1776 struct ocp_enet_private *dev = ndev->priv;
1777 return sizeof(struct emac_ethtool_regs_hdr) +
1778 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal) +
1779 zmii_get_regs_len(dev->zmii_dev) +
1780 rgmii_get_regs_len(dev->rgmii_dev) +
1781 tah_get_regs_len(dev->tah_dev);
1782}
1783
1784static void *emac_dump_regs(struct ocp_enet_private *dev, void *buf)
1785{
1786 struct emac_ethtool_regs_subhdr *hdr = buf;
1787
1788 hdr->version = EMAC_ETHTOOL_REGS_VER;
1789 hdr->index = dev->def->index;
1790 memcpy_fromio(hdr + 1, dev->emacp, EMAC_ETHTOOL_REGS_SIZE);
1791 return ((void *)(hdr + 1) + EMAC_ETHTOOL_REGS_SIZE);
1792}
1793
1794static void emac_ethtool_get_regs(struct net_device *ndev,
1795 struct ethtool_regs *regs, void *buf)
1796{
1797 struct ocp_enet_private *dev = ndev->priv;
1798 struct emac_ethtool_regs_hdr *hdr = buf;
1799
1800 hdr->components = 0;
1801 buf = hdr + 1;
1802
1803 local_irq_disable();
1804 buf = mal_dump_regs(dev->mal, buf);
1805 buf = emac_dump_regs(dev, buf);
1806 if (dev->zmii_dev) {
1807 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
1808 buf = zmii_dump_regs(dev->zmii_dev, buf);
1809 }
1810 if (dev->rgmii_dev) {
1811 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
1812 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
1813 }
1814 if (dev->tah_dev) {
1815 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
1816 buf = tah_dump_regs(dev->tah_dev, buf);
1817 }
1818 local_irq_enable();
1819}
1820
1821static int emac_ethtool_nway_reset(struct net_device *ndev)
1822{
1823 struct ocp_enet_private *dev = ndev->priv;
1824 int res = 0;
1825
1826 DBG("%d: nway_reset" NL, dev->def->index);
1827
1828 if (dev->phy.address < 0)
1829 return -EOPNOTSUPP;
1830
1831 local_bh_disable();
1832 if (!dev->phy.autoneg) {
1833 res = -EINVAL;
1834 goto out;
1835 }
1836
1837 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
1838 emac_force_link_update(dev);
1839
1840 out:
1841 local_bh_enable();
1842 return res;
1843}
1844
1845static int emac_get_sset_count(struct net_device *ndev, int sset)
1846{
1847 switch (sset) {
1848 case ETH_SS_STATS:
1849 return EMAC_ETHTOOL_STATS_COUNT;
1850 default:
1851 return -EOPNOTSUPP;
1852 }
1853}
1854
1855static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
1856 u8 * buf)
1857{
1858 if (stringset == ETH_SS_STATS)
1859 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
1860}
1861
1862static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
1863 struct ethtool_stats *estats,
1864 u64 * tmp_stats)
1865{
1866 struct ocp_enet_private *dev = ndev->priv;
1867 local_irq_disable();
1868 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
1869 tmp_stats += sizeof(dev->stats) / sizeof(u64);
1870 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
1871 local_irq_enable();
1872}
1873
1874static void emac_ethtool_get_drvinfo(struct net_device *ndev,
1875 struct ethtool_drvinfo *info)
1876{
1877 struct ocp_enet_private *dev = ndev->priv;
1878
1879 strcpy(info->driver, "ibm_emac");
1880 strcpy(info->version, DRV_VERSION);
1881 info->fw_version[0] = '\0';
1882 sprintf(info->bus_info, "PPC 4xx EMAC %d", dev->def->index);
1883 info->regdump_len = emac_ethtool_get_regs_len(ndev);
1884}
1885
1886static const struct ethtool_ops emac_ethtool_ops = {
1887 .get_settings = emac_ethtool_get_settings,
1888 .set_settings = emac_ethtool_set_settings,
1889 .get_drvinfo = emac_ethtool_get_drvinfo,
1890
1891 .get_regs_len = emac_ethtool_get_regs_len,
1892 .get_regs = emac_ethtool_get_regs,
1893
1894 .nway_reset = emac_ethtool_nway_reset,
1895
1896 .get_ringparam = emac_ethtool_get_ringparam,
1897 .get_pauseparam = emac_ethtool_get_pauseparam,
1898
1899 .get_rx_csum = emac_ethtool_get_rx_csum,
1900
1901 .get_strings = emac_ethtool_get_strings,
1902 .get_sset_count = emac_get_sset_count,
1903 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
1904
1905 .get_link = ethtool_op_get_link,
1906};
1907
1908static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1909{
1910 struct ocp_enet_private *dev = ndev->priv;
1911 uint16_t *data = (uint16_t *) & rq->ifr_ifru;
1912
1913 DBG("%d: ioctl %08x" NL, dev->def->index, cmd);
1914
1915 if (dev->phy.address < 0)
1916 return -EOPNOTSUPP;
1917
1918 switch (cmd) {
1919 case SIOCGMIIPHY:
1920 case SIOCDEVPRIVATE:
1921 data[0] = dev->phy.address;
1922 /* Fall through */
1923 case SIOCGMIIREG:
1924 case SIOCDEVPRIVATE + 1:
1925 data[3] = emac_mdio_read(ndev, dev->phy.address, data[1]);
1926 return 0;
1927
1928 case SIOCSMIIREG:
1929 case SIOCDEVPRIVATE + 2:
1930 if (!capable(CAP_NET_ADMIN))
1931 return -EPERM;
1932 emac_mdio_write(ndev, dev->phy.address, data[1], data[2]);
1933 return 0;
1934 default:
1935 return -EOPNOTSUPP;
1936 }
1937}
1938
1939static int __init emac_probe(struct ocp_device *ocpdev)
1940{
1941 struct ocp_func_emac_data *emacdata = ocpdev->def->additions;
1942 struct net_device *ndev;
1943 struct ocp_device *maldev;
1944 struct ocp_enet_private *dev;
1945 int err, i;
1946 DECLARE_MAC_BUF(mac);
1947
1948 DBG("%d: probe" NL, ocpdev->def->index);
1949
1950 if (!emacdata) {
1951 printk(KERN_ERR "emac%d: Missing additional data!\n",
1952 ocpdev->def->index);
1953 return -ENODEV;
1954 }
1955
1956 /* Allocate our net_device structure */
1957 ndev = alloc_etherdev(sizeof(struct ocp_enet_private));
1958 if (!ndev) {
1959 printk(KERN_ERR "emac%d: could not allocate ethernet device!\n",
1960 ocpdev->def->index);
1961 return -ENOMEM;
1962 }
1963 dev = ndev->priv;
1964 dev->ndev = ndev;
1965 dev->ldev = &ocpdev->dev;
1966 dev->def = ocpdev->def;
1967
1968 /* Find MAL device we are connected to */
1969 maldev =
1970 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_MAL, emacdata->mal_idx);
1971 if (!maldev) {
1972 printk(KERN_ERR "emac%d: unknown mal%d device!\n",
1973 dev->def->index, emacdata->mal_idx);
1974 err = -ENODEV;
1975 goto out;
1976 }
1977 dev->mal = ocp_get_drvdata(maldev);
1978 if (!dev->mal) {
1979 printk(KERN_ERR "emac%d: mal%d hasn't been initialized yet!\n",
1980 dev->def->index, emacdata->mal_idx);
1981 err = -ENODEV;
1982 goto out;
1983 }
1984
1985 /* Register with MAL */
1986 dev->commac.ops = &emac_commac_ops;
1987 dev->commac.dev = dev;
1988 dev->commac.tx_chan_mask = MAL_CHAN_MASK(emacdata->mal_tx_chan);
1989 dev->commac.rx_chan_mask = MAL_CHAN_MASK(emacdata->mal_rx_chan);
1990 err = mal_register_commac(dev->mal, &dev->commac);
1991 if (err) {
1992 printk(KERN_ERR "emac%d: failed to register with mal%d!\n",
1993 dev->def->index, emacdata->mal_idx);
1994 goto out;
1995 }
1996 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
1997 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
1998
1999 /* Get pointers to BD rings */
2000 dev->tx_desc =
2001 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal,
2002 emacdata->mal_tx_chan);
2003 dev->rx_desc =
2004 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal,
2005 emacdata->mal_rx_chan);
2006
2007 DBG("%d: tx_desc %p" NL, ocpdev->def->index, dev->tx_desc);
2008 DBG("%d: rx_desc %p" NL, ocpdev->def->index, dev->rx_desc);
2009
2010 /* Clean rings */
2011 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
2012 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
2013
2014 /* If we depend on another EMAC for MDIO, check whether it was probed already */
2015 if (emacdata->mdio_idx >= 0 && emacdata->mdio_idx != ocpdev->def->index) {
2016 struct ocp_device *mdiodev =
2017 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC,
2018 emacdata->mdio_idx);
2019 if (!mdiodev) {
2020 printk(KERN_ERR "emac%d: unknown emac%d device!\n",
2021 dev->def->index, emacdata->mdio_idx);
2022 err = -ENODEV;
2023 goto out2;
2024 }
2025 dev->mdio_dev = ocp_get_drvdata(mdiodev);
2026 if (!dev->mdio_dev) {
2027 printk(KERN_ERR
2028 "emac%d: emac%d hasn't been initialized yet!\n",
2029 dev->def->index, emacdata->mdio_idx);
2030 err = -ENODEV;
2031 goto out2;
2032 }
2033 }
2034
2035 /* Attach to ZMII, if needed */
2036 if ((err = zmii_attach(dev)) != 0)
2037 goto out2;
2038
2039 /* Attach to RGMII, if needed */
2040 if ((err = rgmii_attach(dev)) != 0)
2041 goto out3;
2042
2043 /* Attach to TAH, if needed */
2044 if ((err = tah_attach(dev)) != 0)
2045 goto out4;
2046
2047 /* Map EMAC regs */
2048 dev->emacp = ioremap(dev->def->paddr, sizeof(struct emac_regs));
2049 if (!dev->emacp) {
2050 printk(KERN_ERR "emac%d: could not ioremap device registers!\n",
2051 dev->def->index);
2052 err = -ENOMEM;
2053 goto out5;
2054 }
2055
2056 /* Fill in MAC address */
2057 for (i = 0; i < 6; ++i)
2058 ndev->dev_addr[i] = emacdata->mac_addr[i];
2059
2060 /* Set some link defaults before we can find out real parameters */
2061 dev->phy.speed = SPEED_100;
2062 dev->phy.duplex = DUPLEX_FULL;
2063 dev->phy.autoneg = AUTONEG_DISABLE;
2064 dev->phy.pause = dev->phy.asym_pause = 0;
2065 dev->stop_timeout = STOP_TIMEOUT_100;
2066 init_timer(&dev->link_timer);
2067 dev->link_timer.function = emac_link_timer;
2068 dev->link_timer.data = (unsigned long)dev;
2069
2070 /* Find PHY if any */
2071 dev->phy.dev = ndev;
2072 dev->phy.mode = emacdata->phy_mode;
2073 if (emacdata->phy_map != 0xffffffff) {
2074 u32 phy_map = emacdata->phy_map | busy_phy_map;
2075 u32 adv;
2076
2077 DBG("%d: PHY maps %08x %08x" NL, dev->def->index,
2078 emacdata->phy_map, busy_phy_map);
2079
2080 EMAC_RX_CLK_TX(dev->def->index);
2081
2082 dev->phy.mdio_read = emac_mdio_read;
2083 dev->phy.mdio_write = emac_mdio_write;
2084
2085 /* Configure EMAC with defaults so we can at least use MDIO
2086 * This is needed mostly for 440GX
2087 */
2088 if (emac_phy_gpcs(dev->phy.mode)) {
2089 /* XXX
2090 * Make GPCS PHY address equal to EMAC index.
2091 * We probably should take into account busy_phy_map
2092 * and/or phy_map here.
2093 */
2094 dev->phy.address = dev->def->index;
2095 }
2096
2097 emac_configure(dev);
2098
2099 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2100 if (!(phy_map & 1)) {
2101 int r;
2102 busy_phy_map |= 1 << i;
2103
2104 /* Quick check if there is a PHY at the address */
2105 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2106 if (r == 0xffff || r < 0)
2107 continue;
2108 if (!mii_phy_probe(&dev->phy, i))
2109 break;
2110 }
2111 if (i == 0x20) {
2112 printk(KERN_WARNING "emac%d: can't find PHY!\n",
2113 dev->def->index);
2114 goto out6;
2115 }
2116
2117 /* Init PHY */
2118 if (dev->phy.def->ops->init)
2119 dev->phy.def->ops->init(&dev->phy);
2120
2121 /* Disable any PHY features not supported by the platform */
2122 dev->phy.def->features &= ~emacdata->phy_feat_exc;
2123
2124 /* Setup initial link parameters */
2125 if (dev->phy.features & SUPPORTED_Autoneg) {
2126 adv = dev->phy.features;
2127#if !defined(CONFIG_40x)
2128 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2129#endif
2130 /* Restart autonegotiation */
2131 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2132 } else {
2133 u32 f = dev->phy.def->features;
2134 int speed = SPEED_10, fd = DUPLEX_HALF;
2135
2136 /* Select highest supported speed/duplex */
2137 if (f & SUPPORTED_1000baseT_Full) {
2138 speed = SPEED_1000;
2139 fd = DUPLEX_FULL;
2140 } else if (f & SUPPORTED_1000baseT_Half)
2141 speed = SPEED_1000;
2142 else if (f & SUPPORTED_100baseT_Full) {
2143 speed = SPEED_100;
2144 fd = DUPLEX_FULL;
2145 } else if (f & SUPPORTED_100baseT_Half)
2146 speed = SPEED_100;
2147 else if (f & SUPPORTED_10baseT_Full)
2148 fd = DUPLEX_FULL;
2149
2150 /* Force link parameters */
2151 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2152 }
2153 } else {
2154 emac_reset(dev);
2155
2156 /* PHY-less configuration.
2157 * XXX I probably should move these settings to emacdata
2158 */
2159 dev->phy.address = -1;
2160 dev->phy.features = SUPPORTED_100baseT_Full | SUPPORTED_MII;
2161 dev->phy.pause = 1;
2162 }
2163
2164 /* Fill in the driver function table */
2165 ndev->open = &emac_open;
2166 if (dev->tah_dev) {
2167 ndev->hard_start_xmit = &emac_start_xmit_sg;
2168 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2169 } else
2170 ndev->hard_start_xmit = &emac_start_xmit;
2171 ndev->tx_timeout = &emac_full_tx_reset;
2172 ndev->watchdog_timeo = 5 * HZ;
2173 ndev->stop = &emac_close;
2174 ndev->get_stats = &emac_stats;
2175 ndev->set_multicast_list = &emac_set_multicast_list;
2176 ndev->do_ioctl = &emac_ioctl;
2177 if (emac_phy_supports_gige(emacdata->phy_mode)) {
2178 ndev->change_mtu = &emac_change_mtu;
2179 dev->commac.ops = &emac_commac_sg_ops;
2180 }
2181 SET_ETHTOOL_OPS(ndev, &emac_ethtool_ops);
2182
2183 netif_carrier_off(ndev);
2184 netif_stop_queue(ndev);
2185
2186 err = register_netdev(ndev);
2187 if (err) {
2188 printk(KERN_ERR "emac%d: failed to register net device (%d)!\n",
2189 dev->def->index, err);
2190 goto out6;
2191 }
2192
2193 ocp_set_drvdata(ocpdev, dev);
2194
2195 printk("%s: emac%d, MAC %s\n",
2196 ndev->name, dev->def->index, print_mac(mac, ndev->dev_addr));
2197
2198 if (dev->phy.address >= 0)
2199 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
2200 dev->phy.def->name, dev->phy.address);
2201
2202 emac_dbg_register(dev->def->index, dev);
2203
2204 return 0;
2205 out6:
2206 iounmap(dev->emacp);
2207 out5:
2208 tah_fini(dev->tah_dev);
2209 out4:
2210 rgmii_fini(dev->rgmii_dev, dev->rgmii_input);
2211 out3:
2212 zmii_fini(dev->zmii_dev, dev->zmii_input);
2213 out2:
2214 mal_unregister_commac(dev->mal, &dev->commac);
2215 out:
2216 kfree(ndev);
2217 return err;
2218}
2219
2220static struct ocp_device_id emac_ids[] = {
2221 { .vendor = OCP_VENDOR_IBM, .function = OCP_FUNC_EMAC },
2222 { .vendor = OCP_VENDOR_INVALID}
2223};
2224
2225static struct ocp_driver emac_driver = {
2226 .name = "emac",
2227 .id_table = emac_ids,
2228 .probe = emac_probe,
2229 .remove = emac_remove,
2230};
2231
2232static int __init emac_init(void)
2233{
2234 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
2235
2236 DBG(": init" NL);
2237
2238 if (mal_init())
2239 return -ENODEV;
2240
2241 EMAC_CLK_INTERNAL;
2242 if (ocp_register_driver(&emac_driver)) {
2243 EMAC_CLK_EXTERNAL;
2244 ocp_unregister_driver(&emac_driver);
2245 mal_exit();
2246 return -ENODEV;
2247 }
2248 EMAC_CLK_EXTERNAL;
2249
2250 emac_init_debug();
2251 return 0;
2252}
2253
2254static void __exit emac_exit(void)
2255{
2256 DBG(": exit" NL);
2257 ocp_unregister_driver(&emac_driver);
2258 mal_exit();
2259 emac_fini_debug();
2260}
2261
2262module_init(emac_init);
2263module_exit(emac_exit);
diff --git a/drivers/net/ibm_emac/ibm_emac_core.h b/drivers/net/ibm_emac/ibm_emac_core.h
deleted file mode 100644
index dabb94afeb98..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_core.h
+++ /dev/null
@@ -1,222 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_core.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Johnnie Peters <jpeters@mvista.com>
12 * Copyright 2000, 2001 MontaVista Softare Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 */
20#ifndef __IBM_EMAC_CORE_H_
21#define __IBM_EMAC_CORE_H_
22
23#include <linux/netdevice.h>
24#include <linux/dma-mapping.h>
25#include <asm/ocp.h>
26
27#include "ibm_emac.h"
28#include "ibm_emac_phy.h"
29#include "ibm_emac_zmii.h"
30#include "ibm_emac_rgmii.h"
31#include "ibm_emac_mal.h"
32#include "ibm_emac_tah.h"
33
34#define NUM_TX_BUFF CONFIG_IBM_EMAC_TXB
35#define NUM_RX_BUFF CONFIG_IBM_EMAC_RXB
36
37/* Simple sanity check */
38#if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
39#error Invalid number of buffer descriptors (greater than 256)
40#endif
41
42// XXX
43#define EMAC_MIN_MTU 46
44#define EMAC_MAX_MTU 9000
45
46/* Maximum L2 header length (VLAN tagged, no FCS) */
47#define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4)
48
49/* RX BD size for the given MTU */
50static inline int emac_rx_size(int mtu)
51{
52 if (mtu > ETH_DATA_LEN)
53 return MAL_MAX_RX_SIZE;
54 else
55 return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
56}
57
58#define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment())
59
60#define EMAC_RX_SKB_HEADROOM \
61 EMAC_DMA_ALIGN(CONFIG_IBM_EMAC_RX_SKB_HEADROOM)
62
63/* Size of RX skb for the given MTU */
64static inline int emac_rx_skb_size(int mtu)
65{
66 int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
67 return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM;
68}
69
70/* RX DMA sync size */
71static inline int emac_rx_sync_size(int mtu)
72{
73 return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2);
74}
75
76/* Driver statistcs is split into two parts to make it more cache friendly:
77 * - normal statistics (packet count, etc)
78 * - error statistics
79 *
80 * When statistics is requested by ethtool, these parts are concatenated,
81 * normal one goes first.
82 *
83 * Please, keep these structures in sync with emac_stats_keys.
84 */
85
86/* Normal TX/RX Statistics */
87struct ibm_emac_stats {
88 u64 rx_packets;
89 u64 rx_bytes;
90 u64 tx_packets;
91 u64 tx_bytes;
92 u64 rx_packets_csum;
93 u64 tx_packets_csum;
94};
95
96/* Error statistics */
97struct ibm_emac_error_stats {
98 u64 tx_undo;
99
100 /* Software RX Errors */
101 u64 rx_dropped_stack;
102 u64 rx_dropped_oom;
103 u64 rx_dropped_error;
104 u64 rx_dropped_resize;
105 u64 rx_dropped_mtu;
106 u64 rx_stopped;
107 /* BD reported RX errors */
108 u64 rx_bd_errors;
109 u64 rx_bd_overrun;
110 u64 rx_bd_bad_packet;
111 u64 rx_bd_runt_packet;
112 u64 rx_bd_short_event;
113 u64 rx_bd_alignment_error;
114 u64 rx_bd_bad_fcs;
115 u64 rx_bd_packet_too_long;
116 u64 rx_bd_out_of_range;
117 u64 rx_bd_in_range;
118 /* EMAC IRQ reported RX errors */
119 u64 rx_parity;
120 u64 rx_fifo_overrun;
121 u64 rx_overrun;
122 u64 rx_bad_packet;
123 u64 rx_runt_packet;
124 u64 rx_short_event;
125 u64 rx_alignment_error;
126 u64 rx_bad_fcs;
127 u64 rx_packet_too_long;
128 u64 rx_out_of_range;
129 u64 rx_in_range;
130
131 /* Software TX Errors */
132 u64 tx_dropped;
133 /* BD reported TX errors */
134 u64 tx_bd_errors;
135 u64 tx_bd_bad_fcs;
136 u64 tx_bd_carrier_loss;
137 u64 tx_bd_excessive_deferral;
138 u64 tx_bd_excessive_collisions;
139 u64 tx_bd_late_collision;
140 u64 tx_bd_multple_collisions;
141 u64 tx_bd_single_collision;
142 u64 tx_bd_underrun;
143 u64 tx_bd_sqe;
144 /* EMAC IRQ reported TX errors */
145 u64 tx_parity;
146 u64 tx_underrun;
147 u64 tx_sqe;
148 u64 tx_errors;
149};
150
151#define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct ibm_emac_stats) + \
152 sizeof(struct ibm_emac_error_stats)) \
153 / sizeof(u64))
154
155struct ocp_enet_private {
156 struct net_device *ndev; /* 0 */
157 struct emac_regs __iomem *emacp;
158
159 struct mal_descriptor *tx_desc;
160 int tx_cnt;
161 int tx_slot;
162 int ack_slot;
163
164 struct mal_descriptor *rx_desc;
165 int rx_slot;
166 struct sk_buff *rx_sg_skb; /* 1 */
167 int rx_skb_size;
168 int rx_sync_size;
169
170 struct ibm_emac_stats stats;
171 struct ocp_device *tah_dev;
172
173 struct ibm_ocp_mal *mal;
174 struct mal_commac commac;
175
176 struct sk_buff *tx_skb[NUM_TX_BUFF];
177 struct sk_buff *rx_skb[NUM_RX_BUFF];
178
179 struct ocp_device *zmii_dev;
180 int zmii_input;
181 struct ocp_enet_private *mdio_dev;
182 struct ocp_device *rgmii_dev;
183 int rgmii_input;
184
185 struct ocp_def *def;
186
187 struct mii_phy phy;
188 struct timer_list link_timer;
189 int reset_failed;
190
191 int stop_timeout; /* in us */
192
193 struct ibm_emac_error_stats estats;
194 struct net_device_stats nstats;
195
196 struct device* ldev;
197};
198
199/* Ethtool get_regs complex data.
200 * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
201 * when available.
202 *
203 * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
204 * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
205 * Each register component is preceded with emac_ethtool_regs_subhdr.
206 * Order of the optional headers follows their relative bit posititions
207 * in emac_ethtool_regs_hdr.components
208 */
209#define EMAC_ETHTOOL_REGS_ZMII 0x00000001
210#define EMAC_ETHTOOL_REGS_RGMII 0x00000002
211#define EMAC_ETHTOOL_REGS_TAH 0x00000004
212
213struct emac_ethtool_regs_hdr {
214 u32 components;
215};
216
217struct emac_ethtool_regs_subhdr {
218 u32 version;
219 u32 index;
220};
221
222#endif /* __IBM_EMAC_CORE_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_debug.c b/drivers/net/ibm_emac/ibm_emac_debug.c
deleted file mode 100644
index 1f70906cfb98..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_debug.c
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_debug.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, debug print routines.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/netdevice.h>
19#include <linux/sysrq.h>
20#include <asm/io.h>
21
22#include "ibm_emac_core.h"
23
24static void emac_desc_dump(int idx, struct ocp_enet_private *p)
25{
26 int i;
27 printk("** EMAC%d TX BDs **\n"
28 " tx_cnt = %d tx_slot = %d ack_slot = %d\n",
29 idx, p->tx_cnt, p->tx_slot, p->ack_slot);
30 for (i = 0; i < NUM_TX_BUFF / 2; ++i)
31 printk
32 ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
33 i, p->tx_desc[i].data_ptr, p->tx_skb[i] ? 'V' : ' ',
34 p->tx_desc[i].ctrl, p->tx_desc[i].data_len,
35 NUM_TX_BUFF / 2 + i,
36 p->tx_desc[NUM_TX_BUFF / 2 + i].data_ptr,
37 p->tx_skb[NUM_TX_BUFF / 2 + i] ? 'V' : ' ',
38 p->tx_desc[NUM_TX_BUFF / 2 + i].ctrl,
39 p->tx_desc[NUM_TX_BUFF / 2 + i].data_len);
40
41 printk("** EMAC%d RX BDs **\n"
42 " rx_slot = %d rx_stopped = %d rx_skb_size = %d rx_sync_size = %d\n"
43 " rx_sg_skb = 0x%p\n",
44 idx, p->rx_slot, p->commac.rx_stopped, p->rx_skb_size,
45 p->rx_sync_size, p->rx_sg_skb);
46 for (i = 0; i < NUM_RX_BUFF / 2; ++i)
47 printk
48 ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
49 i, p->rx_desc[i].data_ptr, p->rx_skb[i] ? 'V' : ' ',
50 p->rx_desc[i].ctrl, p->rx_desc[i].data_len,
51 NUM_RX_BUFF / 2 + i,
52 p->rx_desc[NUM_RX_BUFF / 2 + i].data_ptr,
53 p->rx_skb[NUM_RX_BUFF / 2 + i] ? 'V' : ' ',
54 p->rx_desc[NUM_RX_BUFF / 2 + i].ctrl,
55 p->rx_desc[NUM_RX_BUFF / 2 + i].data_len);
56}
57
58static void emac_mac_dump(int idx, struct ocp_enet_private *dev)
59{
60 struct emac_regs __iomem *p = dev->emacp;
61
62 printk("** EMAC%d registers **\n"
63 "MR0 = 0x%08x MR1 = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x\n"
64 "RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x\n"
65 "IAR = %04x%08x VTPID = 0x%04x VTCI = 0x%04x\n"
66 "IAHT: 0x%04x 0x%04x 0x%04x 0x%04x "
67 "GAHT: 0x%04x 0x%04x 0x%04x 0x%04x\n"
68 "LSA = %04x%08x IPGVR = 0x%04x\n"
69 "STACR = 0x%08x TRTR = 0x%08x RWMR = 0x%08x\n"
70 "OCTX = 0x%08x OCRX = 0x%08x IPCR = 0x%08x\n",
71 idx, in_be32(&p->mr0), in_be32(&p->mr1),
72 in_be32(&p->tmr0), in_be32(&p->tmr1),
73 in_be32(&p->rmr), in_be32(&p->isr), in_be32(&p->iser),
74 in_be32(&p->iahr), in_be32(&p->ialr), in_be32(&p->vtpid),
75 in_be32(&p->vtci),
76 in_be32(&p->iaht1), in_be32(&p->iaht2), in_be32(&p->iaht3),
77 in_be32(&p->iaht4),
78 in_be32(&p->gaht1), in_be32(&p->gaht2), in_be32(&p->gaht3),
79 in_be32(&p->gaht4),
80 in_be32(&p->lsah), in_be32(&p->lsal), in_be32(&p->ipgvr),
81 in_be32(&p->stacr), in_be32(&p->trtr), in_be32(&p->rwmr),
82 in_be32(&p->octx), in_be32(&p->ocrx), in_be32(&p->ipcr)
83 );
84
85 emac_desc_dump(idx, dev);
86}
87
88static void emac_mal_dump(struct ibm_ocp_mal *mal)
89{
90 struct ocp_func_mal_data *maldata = mal->def->additions;
91 int i;
92
93 printk("** MAL%d Registers **\n"
94 "CFG = 0x%08x ESR = 0x%08x IER = 0x%08x\n"
95 "TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n"
96 "RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n",
97 mal->def->index,
98 get_mal_dcrn(mal, MAL_CFG), get_mal_dcrn(mal, MAL_ESR),
99 get_mal_dcrn(mal, MAL_IER),
100 get_mal_dcrn(mal, MAL_TXCASR), get_mal_dcrn(mal, MAL_TXCARR),
101 get_mal_dcrn(mal, MAL_TXEOBISR), get_mal_dcrn(mal, MAL_TXDEIR),
102 get_mal_dcrn(mal, MAL_RXCASR), get_mal_dcrn(mal, MAL_RXCARR),
103 get_mal_dcrn(mal, MAL_RXEOBISR), get_mal_dcrn(mal, MAL_RXDEIR)
104 );
105
106 printk("TX|");
107 for (i = 0; i < maldata->num_tx_chans; ++i) {
108 if (i && !(i % 4))
109 printk("\n ");
110 printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_TXCTPR(i)));
111 }
112 printk("\nRX|");
113 for (i = 0; i < maldata->num_rx_chans; ++i) {
114 if (i && !(i % 4))
115 printk("\n ");
116 printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_RXCTPR(i)));
117 }
118 printk("\n ");
119 for (i = 0; i < maldata->num_rx_chans; ++i) {
120 u32 r = get_mal_dcrn(mal, MAL_RCBS(i));
121 if (i && !(i % 3))
122 printk("\n ");
123 printk("RCBS%d = 0x%08x (%d) ", i, r, r * 16);
124 }
125 printk("\n");
126}
127
128static struct ocp_enet_private *__emacs[4];
129static struct ibm_ocp_mal *__mals[1];
130
131void emac_dbg_register(int idx, struct ocp_enet_private *dev)
132{
133 unsigned long flags;
134
135 if (idx >= ARRAY_SIZE(__emacs)) {
136 printk(KERN_WARNING
137 "invalid index %d when registering EMAC for debugging\n",
138 idx);
139 return;
140 }
141
142 local_irq_save(flags);
143 __emacs[idx] = dev;
144 local_irq_restore(flags);
145}
146
147void mal_dbg_register(int idx, struct ibm_ocp_mal *mal)
148{
149 unsigned long flags;
150
151 if (idx >= ARRAY_SIZE(__mals)) {
152 printk(KERN_WARNING
153 "invalid index %d when registering MAL for debugging\n",
154 idx);
155 return;
156 }
157
158 local_irq_save(flags);
159 __mals[idx] = mal;
160 local_irq_restore(flags);
161}
162
163void emac_dbg_dump_all(void)
164{
165 unsigned int i;
166 unsigned long flags;
167
168 local_irq_save(flags);
169
170 for (i = 0; i < ARRAY_SIZE(__mals); ++i)
171 if (__mals[i])
172 emac_mal_dump(__mals[i]);
173
174 for (i = 0; i < ARRAY_SIZE(__emacs); ++i)
175 if (__emacs[i])
176 emac_mac_dump(i, __emacs[i]);
177
178 local_irq_restore(flags);
179}
180
181#if defined(CONFIG_MAGIC_SYSRQ)
182static void emac_sysrq_handler(int key, struct tty_struct *tty)
183{
184 emac_dbg_dump_all();
185}
186
187static struct sysrq_key_op emac_sysrq_op = {
188 .handler = emac_sysrq_handler,
189 .help_msg = "emaC",
190 .action_msg = "Show EMAC(s) status",
191};
192
193int __init emac_init_debug(void)
194{
195 return register_sysrq_key('c', &emac_sysrq_op);
196}
197
198void __exit emac_fini_debug(void)
199{
200 unregister_sysrq_key('c', &emac_sysrq_op);
201}
202
203#else
204int __init emac_init_debug(void)
205{
206 return 0;
207}
208void __exit emac_fini_debug(void)
209{
210}
211#endif /* CONFIG_MAGIC_SYSRQ */
diff --git a/drivers/net/ibm_emac/ibm_emac_debug.h b/drivers/net/ibm_emac/ibm_emac_debug.h
deleted file mode 100644
index 6c7dccc84bf5..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_debug.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_debug.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, debug print routines.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15#ifndef __IBM_EMAC_DEBUG_H_
16#define __IBM_EMAC_DEBUG_H_
17
18#include <linux/init.h>
19#include "ibm_emac_core.h"
20#include "ibm_emac_mal.h"
21
22#if defined(CONFIG_IBM_EMAC_DEBUG)
23void emac_dbg_register(int idx, struct ocp_enet_private *dev);
24void mal_dbg_register(int idx, struct ibm_ocp_mal *mal);
25int emac_init_debug(void) __init;
26void emac_fini_debug(void) __exit;
27void emac_dbg_dump_all(void);
28# define DBG_LEVEL 1
29#else
30# define emac_dbg_register(x,y) ((void)0)
31# define mal_dbg_register(x,y) ((void)0)
32# define emac_init_debug() ((void)0)
33# define emac_fini_debug() ((void)0)
34# define emac_dbg_dump_all() ((void)0)
35# define DBG_LEVEL 0
36#endif
37
38#if DBG_LEVEL > 0
39# define DBG(f,x...) printk("emac" f, ##x)
40# define MAL_DBG(f,x...) printk("mal" f, ##x)
41# define ZMII_DBG(f,x...) printk("zmii" f, ##x)
42# define RGMII_DBG(f,x...) printk("rgmii" f, ##x)
43# define NL "\n"
44#else
45# define DBG(f,x...) ((void)0)
46# define MAL_DBG(f,x...) ((void)0)
47# define ZMII_DBG(f,x...) ((void)0)
48# define RGMII_DBG(f,x...) ((void)0)
49#endif
50#if DBG_LEVEL > 1
51# define DBG2(f,x...) DBG(f, ##x)
52# define MAL_DBG2(f,x...) MAL_DBG(f, ##x)
53# define ZMII_DBG2(f,x...) ZMII_DBG(f, ##x)
54# define RGMII_DBG2(f,x...) RGMII_DBG(f, ##x)
55#else
56# define DBG2(f,x...) ((void)0)
57# define MAL_DBG2(f,x...) ((void)0)
58# define ZMII_DBG2(f,x...) ((void)0)
59# define RGMII_DBG2(f,x...) ((void)0)
60#endif
61
62#endif /* __IBM_EMAC_DEBUG_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_mal.c b/drivers/net/ibm_emac/ibm_emac_mal.c
deleted file mode 100644
index dcd8826fc749..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_mal.c
+++ /dev/null
@@ -1,570 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_mal.c
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
11 * David Gibson <hermes@gibson.dropbear.id.au>,
12 *
13 * Armin Kuster <akuster@mvista.com>
14 * Copyright 2002 MontaVista Softare Inc.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 */
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/netdevice.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/dma-mapping.h>
29
30#include <asm/ocp.h>
31
32#include "ibm_emac_core.h"
33#include "ibm_emac_mal.h"
34#include "ibm_emac_debug.h"
35
36int __init mal_register_commac(struct ibm_ocp_mal *mal,
37 struct mal_commac *commac)
38{
39 unsigned long flags;
40 local_irq_save(flags);
41
42 MAL_DBG("%d: reg(%08x, %08x)" NL, mal->def->index,
43 commac->tx_chan_mask, commac->rx_chan_mask);
44
45 /* Don't let multiple commacs claim the same channel(s) */
46 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
47 (mal->rx_chan_mask & commac->rx_chan_mask)) {
48 local_irq_restore(flags);
49 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
50 mal->def->index);
51 return -EBUSY;
52 }
53
54 mal->tx_chan_mask |= commac->tx_chan_mask;
55 mal->rx_chan_mask |= commac->rx_chan_mask;
56 list_add(&commac->list, &mal->list);
57
58 local_irq_restore(flags);
59 return 0;
60}
61
62void mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac)
63{
64 unsigned long flags;
65 local_irq_save(flags);
66
67 MAL_DBG("%d: unreg(%08x, %08x)" NL, mal->def->index,
68 commac->tx_chan_mask, commac->rx_chan_mask);
69
70 mal->tx_chan_mask &= ~commac->tx_chan_mask;
71 mal->rx_chan_mask &= ~commac->rx_chan_mask;
72 list_del_init(&commac->list);
73
74 local_irq_restore(flags);
75}
76
77int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size)
78{
79 struct ocp_func_mal_data *maldata = mal->def->additions;
80 BUG_ON(channel < 0 || channel >= maldata->num_rx_chans ||
81 size > MAL_MAX_RX_SIZE);
82
83 MAL_DBG("%d: set_rbcs(%d, %lu)" NL, mal->def->index, channel, size);
84
85 if (size & 0xf) {
86 printk(KERN_WARNING
87 "mal%d: incorrect RX size %lu for the channel %d\n",
88 mal->def->index, size, channel);
89 return -EINVAL;
90 }
91
92 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
93 return 0;
94}
95
96int mal_tx_bd_offset(struct ibm_ocp_mal *mal, int channel)
97{
98 struct ocp_func_mal_data *maldata = mal->def->additions;
99 BUG_ON(channel < 0 || channel >= maldata->num_tx_chans);
100 return channel * NUM_TX_BUFF;
101}
102
103int mal_rx_bd_offset(struct ibm_ocp_mal *mal, int channel)
104{
105 struct ocp_func_mal_data *maldata = mal->def->additions;
106 BUG_ON(channel < 0 || channel >= maldata->num_rx_chans);
107 return maldata->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
108}
109
110void mal_enable_tx_channel(struct ibm_ocp_mal *mal, int channel)
111{
112 local_bh_disable();
113 MAL_DBG("%d: enable_tx(%d)" NL, mal->def->index, channel);
114 set_mal_dcrn(mal, MAL_TXCASR,
115 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
116 local_bh_enable();
117}
118
119void mal_disable_tx_channel(struct ibm_ocp_mal *mal, int channel)
120{
121 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
122 MAL_DBG("%d: disable_tx(%d)" NL, mal->def->index, channel);
123}
124
125void mal_enable_rx_channel(struct ibm_ocp_mal *mal, int channel)
126{
127 local_bh_disable();
128 MAL_DBG("%d: enable_rx(%d)" NL, mal->def->index, channel);
129 set_mal_dcrn(mal, MAL_RXCASR,
130 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
131 local_bh_enable();
132}
133
134void mal_disable_rx_channel(struct ibm_ocp_mal *mal, int channel)
135{
136 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
137 MAL_DBG("%d: disable_rx(%d)" NL, mal->def->index, channel);
138}
139
140void mal_poll_add(struct ibm_ocp_mal *mal, struct mal_commac *commac)
141{
142 local_bh_disable();
143 MAL_DBG("%d: poll_add(%p)" NL, mal->def->index, commac);
144 list_add_tail(&commac->poll_list, &mal->poll_list);
145 local_bh_enable();
146}
147
148void mal_poll_del(struct ibm_ocp_mal *mal, struct mal_commac *commac)
149{
150 local_bh_disable();
151 MAL_DBG("%d: poll_del(%p)" NL, mal->def->index, commac);
152 list_del(&commac->poll_list);
153 local_bh_enable();
154}
155
156/* synchronized by mal_poll() */
157static inline void mal_enable_eob_irq(struct ibm_ocp_mal *mal)
158{
159 MAL_DBG2("%d: enable_irq" NL, mal->def->index);
160 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
161}
162
163/* synchronized by __LINK_STATE_RX_SCHED bit in ndev->state */
164static inline void mal_disable_eob_irq(struct ibm_ocp_mal *mal)
165{
166 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
167 MAL_DBG2("%d: disable_irq" NL, mal->def->index);
168}
169
170static irqreturn_t mal_serr(int irq, void *dev_instance)
171{
172 struct ibm_ocp_mal *mal = dev_instance;
173 u32 esr = get_mal_dcrn(mal, MAL_ESR);
174
175 /* Clear the error status register */
176 set_mal_dcrn(mal, MAL_ESR, esr);
177
178 MAL_DBG("%d: SERR %08x" NL, mal->def->index, esr);
179
180 if (esr & MAL_ESR_EVB) {
181 if (esr & MAL_ESR_DE) {
182 /* We ignore Descriptor error,
183 * TXDE or RXDE interrupt will be generated anyway.
184 */
185 return IRQ_HANDLED;
186 }
187
188 if (esr & MAL_ESR_PEIN) {
189 /* PLB error, it's probably buggy hardware or
190 * incorrect physical address in BD (i.e. bug)
191 */
192 if (net_ratelimit())
193 printk(KERN_ERR
194 "mal%d: system error, PLB (ESR = 0x%08x)\n",
195 mal->def->index, esr);
196 return IRQ_HANDLED;
197 }
198
199 /* OPB error, it's probably buggy hardware or incorrect EBC setup */
200 if (net_ratelimit())
201 printk(KERN_ERR
202 "mal%d: system error, OPB (ESR = 0x%08x)\n",
203 mal->def->index, esr);
204 }
205 return IRQ_HANDLED;
206}
207
208static inline void mal_schedule_poll(struct ibm_ocp_mal *mal)
209{
210 if (likely(napi_schedule_prep(&mal->napi))) {
211 MAL_DBG2("%d: schedule_poll" NL, mal->def->index);
212 mal_disable_eob_irq(mal);
213 __napi_schedule(&mal->napi);
214 } else
215 MAL_DBG2("%d: already in poll" NL, mal->def->index);
216}
217
218static irqreturn_t mal_txeob(int irq, void *dev_instance)
219{
220 struct ibm_ocp_mal *mal = dev_instance;
221 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
222 MAL_DBG2("%d: txeob %08x" NL, mal->def->index, r);
223 mal_schedule_poll(mal);
224 set_mal_dcrn(mal, MAL_TXEOBISR, r);
225 return IRQ_HANDLED;
226}
227
228static irqreturn_t mal_rxeob(int irq, void *dev_instance)
229{
230 struct ibm_ocp_mal *mal = dev_instance;
231 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
232 MAL_DBG2("%d: rxeob %08x" NL, mal->def->index, r);
233 mal_schedule_poll(mal);
234 set_mal_dcrn(mal, MAL_RXEOBISR, r);
235 return IRQ_HANDLED;
236}
237
238static irqreturn_t mal_txde(int irq, void *dev_instance)
239{
240 struct ibm_ocp_mal *mal = dev_instance;
241 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
242 set_mal_dcrn(mal, MAL_TXDEIR, deir);
243
244 MAL_DBG("%d: txde %08x" NL, mal->def->index, deir);
245
246 if (net_ratelimit())
247 printk(KERN_ERR
248 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
249 mal->def->index, deir);
250
251 return IRQ_HANDLED;
252}
253
254static irqreturn_t mal_rxde(int irq, void *dev_instance)
255{
256 struct ibm_ocp_mal *mal = dev_instance;
257 struct list_head *l;
258 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
259
260 MAL_DBG("%d: rxde %08x" NL, mal->def->index, deir);
261
262 list_for_each(l, &mal->list) {
263 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
264 if (deir & mc->rx_chan_mask) {
265 mc->rx_stopped = 1;
266 mc->ops->rxde(mc->dev);
267 }
268 }
269
270 mal_schedule_poll(mal);
271 set_mal_dcrn(mal, MAL_RXDEIR, deir);
272
273 return IRQ_HANDLED;
274}
275
276static int mal_poll(struct napi_struct *napi, int budget)
277{
278 struct ibm_ocp_mal *mal = container_of(napi, struct ibm_ocp_mal, napi);
279 struct list_head *l;
280 int received = 0;
281
282 MAL_DBG2("%d: poll(%d) %d ->" NL, mal->def->index, *budget,
283 rx_work_limit);
284 again:
285 /* Process TX skbs */
286 list_for_each(l, &mal->poll_list) {
287 struct mal_commac *mc =
288 list_entry(l, struct mal_commac, poll_list);
289 mc->ops->poll_tx(mc->dev);
290 }
291
292 /* Process RX skbs.
293 * We _might_ need something more smart here to enforce polling fairness.
294 */
295 list_for_each(l, &mal->poll_list) {
296 struct mal_commac *mc =
297 list_entry(l, struct mal_commac, poll_list);
298 int n = mc->ops->poll_rx(mc->dev, budget);
299 if (n) {
300 received += n;
301 budget -= n;
302 if (budget <= 0)
303 goto more_work; // XXX What if this is the last one ?
304 }
305 }
306
307 /* We need to disable IRQs to protect from RXDE IRQ here */
308 local_irq_disable();
309 __napi_complete(napi);
310 mal_enable_eob_irq(mal);
311 local_irq_enable();
312
313 /* Check for "rotting" packet(s) */
314 list_for_each(l, &mal->poll_list) {
315 struct mal_commac *mc =
316 list_entry(l, struct mal_commac, poll_list);
317 if (unlikely(mc->ops->peek_rx(mc->dev) || mc->rx_stopped)) {
318 MAL_DBG2("%d: rotting packet" NL, mal->def->index);
319 if (napi_reschedule(napi))
320 mal_disable_eob_irq(mal);
321 else
322 MAL_DBG2("%d: already in poll list" NL,
323 mal->def->index);
324
325 if (budget > 0)
326 goto again;
327 else
328 goto more_work;
329 }
330 mc->ops->poll_tx(mc->dev);
331 }
332
333 more_work:
334 MAL_DBG2("%d: poll() %d <- %d" NL, mal->def->index, budget, received);
335 return received;
336}
337
338static void mal_reset(struct ibm_ocp_mal *mal)
339{
340 int n = 10;
341 MAL_DBG("%d: reset" NL, mal->def->index);
342
343 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
344
345 /* Wait for reset to complete (1 system clock) */
346 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
347 --n;
348
349 if (unlikely(!n))
350 printk(KERN_ERR "mal%d: reset timeout\n", mal->def->index);
351}
352
353int mal_get_regs_len(struct ibm_ocp_mal *mal)
354{
355 return sizeof(struct emac_ethtool_regs_subhdr) +
356 sizeof(struct ibm_mal_regs);
357}
358
359void *mal_dump_regs(struct ibm_ocp_mal *mal, void *buf)
360{
361 struct emac_ethtool_regs_subhdr *hdr = buf;
362 struct ibm_mal_regs *regs = (struct ibm_mal_regs *)(hdr + 1);
363 struct ocp_func_mal_data *maldata = mal->def->additions;
364 int i;
365
366 hdr->version = MAL_VERSION;
367 hdr->index = mal->def->index;
368
369 regs->tx_count = maldata->num_tx_chans;
370 regs->rx_count = maldata->num_rx_chans;
371
372 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
373 regs->esr = get_mal_dcrn(mal, MAL_ESR);
374 regs->ier = get_mal_dcrn(mal, MAL_IER);
375 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
376 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
377 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
378 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
379 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
380 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
381 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
382 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
383
384 for (i = 0; i < regs->tx_count; ++i)
385 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
386
387 for (i = 0; i < regs->rx_count; ++i) {
388 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
389 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
390 }
391 return regs + 1;
392}
393
394static int __init mal_probe(struct ocp_device *ocpdev)
395{
396 struct ibm_ocp_mal *mal;
397 struct ocp_func_mal_data *maldata;
398 int err = 0, i, bd_size;
399
400 MAL_DBG("%d: probe" NL, ocpdev->def->index);
401
402 maldata = ocpdev->def->additions;
403 if (maldata == NULL) {
404 printk(KERN_ERR "mal%d: missing additional data!\n",
405 ocpdev->def->index);
406 return -ENODEV;
407 }
408
409 mal = kzalloc(sizeof(struct ibm_ocp_mal), GFP_KERNEL);
410 if (!mal) {
411 printk(KERN_ERR
412 "mal%d: out of memory allocating MAL structure!\n",
413 ocpdev->def->index);
414 return -ENOMEM;
415 }
416
417 /* XXX This only works for native dcr for now */
418 mal->dcrhost = dcr_map(NULL, maldata->dcr_base, 0);
419
420 mal->def = ocpdev->def;
421
422 INIT_LIST_HEAD(&mal->poll_list);
423 mal->napi.weight = CONFIG_IBM_EMAC_POLL_WEIGHT;
424 mal->napi.poll = mal_poll;
425
426 INIT_LIST_HEAD(&mal->list);
427
428 /* Load power-on reset defaults */
429 mal_reset(mal);
430
431 /* Set the MAL configuration register */
432 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_DEFAULT | MAL_CFG_PLBB |
433 MAL_CFG_OPBBL | MAL_CFG_LEA);
434
435 mal_enable_eob_irq(mal);
436
437 /* Allocate space for BD rings */
438 BUG_ON(maldata->num_tx_chans <= 0 || maldata->num_tx_chans > 32);
439 BUG_ON(maldata->num_rx_chans <= 0 || maldata->num_rx_chans > 32);
440 bd_size = sizeof(struct mal_descriptor) *
441 (NUM_TX_BUFF * maldata->num_tx_chans +
442 NUM_RX_BUFF * maldata->num_rx_chans);
443 mal->bd_virt =
444 dma_alloc_coherent(&ocpdev->dev, bd_size, &mal->bd_dma, GFP_KERNEL);
445
446 if (!mal->bd_virt) {
447 printk(KERN_ERR
448 "mal%d: out of memory allocating RX/TX descriptors!\n",
449 mal->def->index);
450 err = -ENOMEM;
451 goto fail;
452 }
453 memset(mal->bd_virt, 0, bd_size);
454
455 for (i = 0; i < maldata->num_tx_chans; ++i)
456 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
457 sizeof(struct mal_descriptor) *
458 mal_tx_bd_offset(mal, i));
459
460 for (i = 0; i < maldata->num_rx_chans; ++i)
461 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
462 sizeof(struct mal_descriptor) *
463 mal_rx_bd_offset(mal, i));
464
465 err = request_irq(maldata->serr_irq, mal_serr, 0, "MAL SERR", mal);
466 if (err)
467 goto fail2;
468 err = request_irq(maldata->txde_irq, mal_txde, 0, "MAL TX DE", mal);
469 if (err)
470 goto fail3;
471 err = request_irq(maldata->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
472 if (err)
473 goto fail4;
474 err = request_irq(maldata->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
475 if (err)
476 goto fail5;
477 err = request_irq(maldata->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
478 if (err)
479 goto fail6;
480
481 /* Enable all MAL SERR interrupt sources */
482 set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS);
483
484 /* Advertise this instance to the rest of the world */
485 ocp_set_drvdata(ocpdev, mal);
486
487 mal_dbg_register(mal->def->index, mal);
488
489 printk(KERN_INFO "mal%d: initialized, %d TX channels, %d RX channels\n",
490 mal->def->index, maldata->num_tx_chans, maldata->num_rx_chans);
491 return 0;
492
493 fail6:
494 free_irq(maldata->rxde_irq, mal);
495 fail5:
496 free_irq(maldata->txeob_irq, mal);
497 fail4:
498 free_irq(maldata->txde_irq, mal);
499 fail3:
500 free_irq(maldata->serr_irq, mal);
501 fail2:
502 dma_free_coherent(&ocpdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
503 fail:
504 kfree(mal);
505 return err;
506}
507
508static void __exit mal_remove(struct ocp_device *ocpdev)
509{
510 struct ibm_ocp_mal *mal = ocp_get_drvdata(ocpdev);
511 struct ocp_func_mal_data *maldata = mal->def->additions;
512
513 MAL_DBG("%d: remove" NL, mal->def->index);
514
515 /* Synchronize with scheduled polling */
516 napi_disable(&mal->napi);
517
518 if (!list_empty(&mal->list)) {
519 /* This is *very* bad */
520 printk(KERN_EMERG
521 "mal%d: commac list is not empty on remove!\n",
522 mal->def->index);
523 }
524
525 ocp_set_drvdata(ocpdev, NULL);
526
527 free_irq(maldata->serr_irq, mal);
528 free_irq(maldata->txde_irq, mal);
529 free_irq(maldata->txeob_irq, mal);
530 free_irq(maldata->rxde_irq, mal);
531 free_irq(maldata->rxeob_irq, mal);
532
533 mal_reset(mal);
534
535 mal_dbg_register(mal->def->index, NULL);
536
537 dma_free_coherent(&ocpdev->dev,
538 sizeof(struct mal_descriptor) *
539 (NUM_TX_BUFF * maldata->num_tx_chans +
540 NUM_RX_BUFF * maldata->num_rx_chans), mal->bd_virt,
541 mal->bd_dma);
542
543 kfree(mal);
544}
545
546/* Structure for a device driver */
547static struct ocp_device_id mal_ids[] = {
548 { .vendor = OCP_VENDOR_IBM, .function = OCP_FUNC_MAL },
549 { .vendor = OCP_VENDOR_INVALID}
550};
551
552static struct ocp_driver mal_driver = {
553 .name = "mal",
554 .id_table = mal_ids,
555
556 .probe = mal_probe,
557 .remove = mal_remove,
558};
559
560int __init mal_init(void)
561{
562 MAL_DBG(": init" NL);
563 return ocp_register_driver(&mal_driver);
564}
565
566void __exit mal_exit(void)
567{
568 MAL_DBG(": exit" NL);
569 ocp_unregister_driver(&mal_driver);
570}
diff --git a/drivers/net/ibm_emac/ibm_emac_mal.h b/drivers/net/ibm_emac/ibm_emac_mal.h
deleted file mode 100644
index b8adbe6d4b01..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_mal.h
+++ /dev/null
@@ -1,267 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_mal.h
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2002 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#ifndef __IBM_EMAC_MAL_H_
20#define __IBM_EMAC_MAL_H_
21
22#include <linux/init.h>
23#include <linux/list.h>
24#include <linux/netdevice.h>
25
26#include <asm/io.h>
27#include <asm/dcr.h>
28
29/*
30 * These MAL "versions" probably aren't the real versions IBM uses for these
31 * MAL cores, I assigned them just to make #ifdefs in this file nicer and
32 * reflect the fact that 40x and 44x have slightly different MALs. --ebs
33 */
34#if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \
35 defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_NP405H)
36#define MAL_VERSION 1
37#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
38 defined(CONFIG_440SPE)
39#define MAL_VERSION 2
40#else
41#error "Unknown SoC, please check chip manual and choose MAL 'version'"
42#endif
43
44/* MALx DCR registers */
45#define MAL_CFG 0x00
46#define MAL_CFG_SR 0x80000000
47#define MAL_CFG_PLBB 0x00004000
48#define MAL_CFG_OPBBL 0x00000080
49#define MAL_CFG_EOPIE 0x00000004
50#define MAL_CFG_LEA 0x00000002
51#define MAL_CFG_SD 0x00000001
52#if MAL_VERSION == 1
53#define MAL_CFG_PLBP_MASK 0x00c00000
54#define MAL_CFG_PLBP_10 0x00800000
55#define MAL_CFG_GA 0x00200000
56#define MAL_CFG_OA 0x00100000
57#define MAL_CFG_PLBLE 0x00080000
58#define MAL_CFG_PLBT_MASK 0x00078000
59#define MAL_CFG_DEFAULT (MAL_CFG_PLBP_10 | MAL_CFG_PLBT_MASK)
60#elif MAL_VERSION == 2
61#define MAL_CFG_RPP_MASK 0x00c00000
62#define MAL_CFG_RPP_10 0x00800000
63#define MAL_CFG_RMBS_MASK 0x00300000
64#define MAL_CFG_WPP_MASK 0x000c0000
65#define MAL_CFG_WPP_10 0x00080000
66#define MAL_CFG_WMBS_MASK 0x00030000
67#define MAL_CFG_PLBLE 0x00008000
68#define MAL_CFG_DEFAULT (MAL_CFG_RMBS_MASK | MAL_CFG_WMBS_MASK | \
69 MAL_CFG_RPP_10 | MAL_CFG_WPP_10)
70#else
71#error "Unknown MAL version"
72#endif
73
74#define MAL_ESR 0x01
75#define MAL_ESR_EVB 0x80000000
76#define MAL_ESR_CIDT 0x40000000
77#define MAL_ESR_CID_MASK 0x3e000000
78#define MAL_ESR_CID_SHIFT 25
79#define MAL_ESR_DE 0x00100000
80#define MAL_ESR_OTE 0x00040000
81#define MAL_ESR_OSE 0x00020000
82#define MAL_ESR_PEIN 0x00010000
83#define MAL_ESR_DEI 0x00000010
84#define MAL_ESR_OTEI 0x00000004
85#define MAL_ESR_OSEI 0x00000002
86#define MAL_ESR_PBEI 0x00000001
87#if MAL_VERSION == 1
88#define MAL_ESR_ONE 0x00080000
89#define MAL_ESR_ONEI 0x00000008
90#elif MAL_VERSION == 2
91#define MAL_ESR_PTE 0x00800000
92#define MAL_ESR_PRE 0x00400000
93#define MAL_ESR_PWE 0x00200000
94#define MAL_ESR_PTEI 0x00000080
95#define MAL_ESR_PREI 0x00000040
96#define MAL_ESR_PWEI 0x00000020
97#else
98#error "Unknown MAL version"
99#endif
100
101#define MAL_IER 0x02
102#define MAL_IER_DE 0x00000010
103#define MAL_IER_OTE 0x00000004
104#define MAL_IER_OE 0x00000002
105#define MAL_IER_PE 0x00000001
106#if MAL_VERSION == 1
107#define MAL_IER_NWE 0x00000008
108#define MAL_IER_SOC_EVENTS MAL_IER_NWE
109#elif MAL_VERSION == 2
110#define MAL_IER_PT 0x00000080
111#define MAL_IER_PRE 0x00000040
112#define MAL_IER_PWE 0x00000020
113#define MAL_IER_SOC_EVENTS (MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE)
114#else
115#error "Unknown MAL version"
116#endif
117#define MAL_IER_EVENTS (MAL_IER_SOC_EVENTS | MAL_IER_OTE | \
118 MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
119
120#define MAL_TXCASR 0x04
121#define MAL_TXCARR 0x05
122#define MAL_TXEOBISR 0x06
123#define MAL_TXDEIR 0x07
124#define MAL_RXCASR 0x10
125#define MAL_RXCARR 0x11
126#define MAL_RXEOBISR 0x12
127#define MAL_RXDEIR 0x13
128#define MAL_TXCTPR(n) ((n) + 0x20)
129#define MAL_RXCTPR(n) ((n) + 0x40)
130#define MAL_RCBS(n) ((n) + 0x60)
131
132/* In reality MAL can handle TX buffers up to 4095 bytes long,
133 * but this isn't a good round number :) --ebs
134 */
135#define MAL_MAX_TX_SIZE 4080
136#define MAL_MAX_RX_SIZE 4080
137
138static inline int mal_rx_size(int len)
139{
140 len = (len + 0xf) & ~0xf;
141 return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len;
142}
143
144static inline int mal_tx_chunks(int len)
145{
146 return (len + MAL_MAX_TX_SIZE - 1) / MAL_MAX_TX_SIZE;
147}
148
149#define MAL_CHAN_MASK(n) (0x80000000 >> (n))
150
151/* MAL Buffer Descriptor structure */
152struct mal_descriptor {
153 u16 ctrl; /* MAL / Commac status control bits */
154 u16 data_len; /* Max length is 4K-1 (12 bits) */
155 u32 data_ptr; /* pointer to actual data buffer */
156};
157
158/* the following defines are for the MadMAL status and control registers. */
159/* MADMAL transmit and receive status/control bits */
160#define MAL_RX_CTRL_EMPTY 0x8000
161#define MAL_RX_CTRL_WRAP 0x4000
162#define MAL_RX_CTRL_CM 0x2000
163#define MAL_RX_CTRL_LAST 0x1000
164#define MAL_RX_CTRL_FIRST 0x0800
165#define MAL_RX_CTRL_INTR 0x0400
166#define MAL_RX_CTRL_SINGLE (MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
167#define MAL_IS_SINGLE_RX(ctrl) (((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)
168
169#define MAL_TX_CTRL_READY 0x8000
170#define MAL_TX_CTRL_WRAP 0x4000
171#define MAL_TX_CTRL_CM 0x2000
172#define MAL_TX_CTRL_LAST 0x1000
173#define MAL_TX_CTRL_INTR 0x0400
174
175struct mal_commac_ops {
176 void (*poll_tx) (void *dev);
177 int (*poll_rx) (void *dev, int budget);
178 int (*peek_rx) (void *dev);
179 void (*rxde) (void *dev);
180};
181
182struct mal_commac {
183 struct mal_commac_ops *ops;
184 void *dev;
185 struct list_head poll_list;
186 int rx_stopped;
187
188 u32 tx_chan_mask;
189 u32 rx_chan_mask;
190 struct list_head list;
191};
192
193struct ibm_ocp_mal {
194 dcr_host_t dcrhost;
195
196 struct list_head poll_list;
197 struct napi_struct napi;
198
199 struct list_head list;
200 u32 tx_chan_mask;
201 u32 rx_chan_mask;
202
203 dma_addr_t bd_dma;
204 struct mal_descriptor *bd_virt;
205
206 struct ocp_def *def;
207};
208
209static inline u32 get_mal_dcrn(struct ibm_ocp_mal *mal, int reg)
210{
211 return dcr_read(mal->dcrhost, reg);
212}
213
214static inline void set_mal_dcrn(struct ibm_ocp_mal *mal, int reg, u32 val)
215{
216 dcr_write(mal->dcrhost, reg, val);
217}
218
219/* Register MAL devices */
220int mal_init(void) __init;
221void mal_exit(void) __exit;
222
223int mal_register_commac(struct ibm_ocp_mal *mal,
224 struct mal_commac *commac) __init;
225void mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac);
226int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size);
227
228/* Returns BD ring offset for a particular channel
229 (in 'struct mal_descriptor' elements)
230*/
231int mal_tx_bd_offset(struct ibm_ocp_mal *mal, int channel);
232int mal_rx_bd_offset(struct ibm_ocp_mal *mal, int channel);
233
234void mal_enable_tx_channel(struct ibm_ocp_mal *mal, int channel);
235void mal_disable_tx_channel(struct ibm_ocp_mal *mal, int channel);
236void mal_enable_rx_channel(struct ibm_ocp_mal *mal, int channel);
237void mal_disable_rx_channel(struct ibm_ocp_mal *mal, int channel);
238
239/* Add/remove EMAC to/from MAL polling list */
240void mal_poll_add(struct ibm_ocp_mal *mal, struct mal_commac *commac);
241void mal_poll_del(struct ibm_ocp_mal *mal, struct mal_commac *commac);
242
243/* Ethtool MAL registers */
244struct ibm_mal_regs {
245 u32 tx_count;
246 u32 rx_count;
247
248 u32 cfg;
249 u32 esr;
250 u32 ier;
251 u32 tx_casr;
252 u32 tx_carr;
253 u32 tx_eobisr;
254 u32 tx_deir;
255 u32 rx_casr;
256 u32 rx_carr;
257 u32 rx_eobisr;
258 u32 rx_deir;
259 u32 tx_ctpr[32];
260 u32 rx_ctpr[32];
261 u32 rcbs[32];
262};
263
264int mal_get_regs_len(struct ibm_ocp_mal *mal);
265void *mal_dump_regs(struct ibm_ocp_mal *mal, void *buf);
266
267#endif /* __IBM_EMAC_MAL_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_phy.c b/drivers/net/ibm_emac/ibm_emac_phy.c
deleted file mode 100644
index e57862b34cae..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_phy.c
+++ /dev/null
@@ -1,398 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_phy.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
5 * Borrowed from sungem_phy.c, though I only kept the generic MII
6 * driver for now.
7 *
8 * This file should be shared with other drivers or eventually
9 * merged as the "low level" part of miilib
10 *
11 * (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org)
12 * (c) 2004-2005, Eugene Surovegin <ebs@ebshome.net>
13 *
14 */
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/netdevice.h>
19#include <linux/mii.h>
20#include <linux/ethtool.h>
21#include <linux/delay.h>
22
23#include <asm/ocp.h>
24
25#include "ibm_emac_core.h"
26#include "ibm_emac_phy.h"
27
28static inline int phy_read(struct mii_phy *phy, int reg)
29{
30 return phy->mdio_read(phy->dev, phy->address, reg);
31}
32
33static inline void phy_write(struct mii_phy *phy, int reg, int val)
34{
35 phy->mdio_write(phy->dev, phy->address, reg, val);
36}
37
38/*
39 * polls MII_BMCR until BMCR_RESET bit clears or operation times out.
40 *
41 * returns:
42 * >= 0 => success, value in BMCR returned to caller
43 * -EBUSY => failure, RESET bit never cleared
44 * otherwise => failure, lower level PHY read failed
45 */
46static int mii_spin_reset_complete(struct mii_phy *phy)
47{
48 int val;
49 int limit = 10000;
50
51 while (limit--) {
52 val = phy_read(phy, MII_BMCR);
53 if (val >= 0 && !(val & BMCR_RESET))
54 return val; /* success */
55 udelay(10);
56 }
57 if (val & BMCR_RESET)
58 val = -EBUSY;
59
60 if (net_ratelimit())
61 printk(KERN_ERR "emac%d: PHY reset timeout (%d)\n",
62 ((struct ocp_enet_private *)phy->dev->priv)->def->index,
63 val);
64 return val;
65}
66
67int mii_reset_phy(struct mii_phy *phy)
68{
69 int val;
70
71 val = phy_read(phy, MII_BMCR);
72 val &= ~BMCR_ISOLATE;
73 val |= BMCR_RESET;
74 phy_write(phy, MII_BMCR, val);
75
76 udelay(300);
77
78 val = mii_spin_reset_complete(phy);
79 if (val >= 0 && (val & BMCR_ISOLATE))
80 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
81
82 return val < 0;
83}
84
85static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
86{
87 int ctl, adv;
88
89 phy->autoneg = AUTONEG_ENABLE;
90 phy->speed = SPEED_10;
91 phy->duplex = DUPLEX_HALF;
92 phy->pause = phy->asym_pause = 0;
93 phy->advertising = advertise;
94
95 /* Setup standard advertise */
96 adv = phy_read(phy, MII_ADVERTISE);
97 if (adv < 0)
98 return adv;
99 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
100 ADVERTISE_PAUSE_ASYM);
101 if (advertise & ADVERTISED_10baseT_Half)
102 adv |= ADVERTISE_10HALF;
103 if (advertise & ADVERTISED_10baseT_Full)
104 adv |= ADVERTISE_10FULL;
105 if (advertise & ADVERTISED_100baseT_Half)
106 adv |= ADVERTISE_100HALF;
107 if (advertise & ADVERTISED_100baseT_Full)
108 adv |= ADVERTISE_100FULL;
109 if (advertise & ADVERTISED_Pause)
110 adv |= ADVERTISE_PAUSE_CAP;
111 if (advertise & ADVERTISED_Asym_Pause)
112 adv |= ADVERTISE_PAUSE_ASYM;
113 phy_write(phy, MII_ADVERTISE, adv);
114
115 if (phy->features &
116 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
117 adv = phy_read(phy, MII_CTRL1000);
118 if (adv < 0)
119 return adv;
120 adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
121 if (advertise & ADVERTISED_1000baseT_Full)
122 adv |= ADVERTISE_1000FULL;
123 if (advertise & ADVERTISED_1000baseT_Half)
124 adv |= ADVERTISE_1000HALF;
125 phy_write(phy, MII_CTRL1000, adv);
126 }
127
128 /* Start/Restart aneg */
129 /* on some PHYs (e.g. National DP83843) a write to MII_ADVERTISE
130 * causes BMCR_RESET to be set on the next read of MII_BMCR, which
131 * if not checked for causes the PHY to be reset below */
132 ctl = mii_spin_reset_complete(phy);
133 if (ctl < 0)
134 return ctl;
135
136 ctl |= BMCR_ANENABLE | BMCR_ANRESTART;
137 phy_write(phy, MII_BMCR, ctl);
138
139 return 0;
140}
141
142static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
143{
144 int ctl;
145
146 phy->autoneg = AUTONEG_DISABLE;
147 phy->speed = speed;
148 phy->duplex = fd;
149 phy->pause = phy->asym_pause = 0;
150
151 /* First reset the PHY */
152 mii_reset_phy(phy);
153
154 ctl = phy_read(phy, MII_BMCR);
155 if (ctl < 0)
156 return ctl;
157 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_ANENABLE | BMCR_SPEED1000);
158
159 /* Select speed & duplex */
160 switch (speed) {
161 case SPEED_10:
162 break;
163 case SPEED_100:
164 ctl |= BMCR_SPEED100;
165 break;
166 case SPEED_1000:
167 ctl |= BMCR_SPEED1000;
168 break;
169 default:
170 return -EINVAL;
171 }
172 if (fd == DUPLEX_FULL)
173 ctl |= BMCR_FULLDPLX;
174 phy_write(phy, MII_BMCR, ctl);
175
176 return 0;
177}
178
179static int genmii_poll_link(struct mii_phy *phy)
180{
181 int status;
182
183 /* Clear latched value with dummy read */
184 phy_read(phy, MII_BMSR);
185 status = phy_read(phy, MII_BMSR);
186 if (status < 0 || (status & BMSR_LSTATUS) == 0)
187 return 0;
188 if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE))
189 return 0;
190 return 1;
191}
192
193static int genmii_read_link(struct mii_phy *phy)
194{
195 if (phy->autoneg == AUTONEG_ENABLE) {
196 int glpa = 0;
197 int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
198 if (lpa < 0)
199 return lpa;
200
201 if (phy->features &
202 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
203 int adv = phy_read(phy, MII_CTRL1000);
204 glpa = phy_read(phy, MII_STAT1000);
205
206 if (glpa < 0 || adv < 0)
207 return adv;
208
209 glpa &= adv << 2;
210 }
211
212 phy->speed = SPEED_10;
213 phy->duplex = DUPLEX_HALF;
214 phy->pause = phy->asym_pause = 0;
215
216 if (glpa & (LPA_1000FULL | LPA_1000HALF)) {
217 phy->speed = SPEED_1000;
218 if (glpa & LPA_1000FULL)
219 phy->duplex = DUPLEX_FULL;
220 } else if (lpa & (LPA_100FULL | LPA_100HALF)) {
221 phy->speed = SPEED_100;
222 if (lpa & LPA_100FULL)
223 phy->duplex = DUPLEX_FULL;
224 } else if (lpa & LPA_10FULL)
225 phy->duplex = DUPLEX_FULL;
226
227 if (phy->duplex == DUPLEX_FULL) {
228 phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
229 phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
230 }
231 } else {
232 int bmcr = phy_read(phy, MII_BMCR);
233 if (bmcr < 0)
234 return bmcr;
235
236 if (bmcr & BMCR_FULLDPLX)
237 phy->duplex = DUPLEX_FULL;
238 else
239 phy->duplex = DUPLEX_HALF;
240 if (bmcr & BMCR_SPEED1000)
241 phy->speed = SPEED_1000;
242 else if (bmcr & BMCR_SPEED100)
243 phy->speed = SPEED_100;
244 else
245 phy->speed = SPEED_10;
246
247 phy->pause = phy->asym_pause = 0;
248 }
249 return 0;
250}
251
252/* Generic implementation for most 10/100/1000 PHYs */
253static struct mii_phy_ops generic_phy_ops = {
254 .setup_aneg = genmii_setup_aneg,
255 .setup_forced = genmii_setup_forced,
256 .poll_link = genmii_poll_link,
257 .read_link = genmii_read_link
258};
259
260static struct mii_phy_def genmii_phy_def = {
261 .phy_id = 0x00000000,
262 .phy_id_mask = 0x00000000,
263 .name = "Generic MII",
264 .ops = &generic_phy_ops
265};
266
267/* CIS8201 */
268#define MII_CIS8201_10BTCSR 0x16
269#define TENBTCSR_ECHO_DISABLE 0x2000
270#define MII_CIS8201_EPCR 0x17
271#define EPCR_MODE_MASK 0x3000
272#define EPCR_GMII_MODE 0x0000
273#define EPCR_RGMII_MODE 0x1000
274#define EPCR_TBI_MODE 0x2000
275#define EPCR_RTBI_MODE 0x3000
276#define MII_CIS8201_ACSR 0x1c
277#define ACSR_PIN_PRIO_SELECT 0x0004
278
279static int cis8201_init(struct mii_phy *phy)
280{
281 int epcr;
282
283 epcr = phy_read(phy, MII_CIS8201_EPCR);
284 if (epcr < 0)
285 return epcr;
286
287 epcr &= ~EPCR_MODE_MASK;
288
289 switch (phy->mode) {
290 case PHY_MODE_TBI:
291 epcr |= EPCR_TBI_MODE;
292 break;
293 case PHY_MODE_RTBI:
294 epcr |= EPCR_RTBI_MODE;
295 break;
296 case PHY_MODE_GMII:
297 epcr |= EPCR_GMII_MODE;
298 break;
299 case PHY_MODE_RGMII:
300 default:
301 epcr |= EPCR_RGMII_MODE;
302 }
303
304 phy_write(phy, MII_CIS8201_EPCR, epcr);
305
306 /* MII regs override strap pins */
307 phy_write(phy, MII_CIS8201_ACSR,
308 phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
309
310 /* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
311 phy_write(phy, MII_CIS8201_10BTCSR,
312 phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
313
314 return 0;
315}
316
317static struct mii_phy_ops cis8201_phy_ops = {
318 .init = cis8201_init,
319 .setup_aneg = genmii_setup_aneg,
320 .setup_forced = genmii_setup_forced,
321 .poll_link = genmii_poll_link,
322 .read_link = genmii_read_link
323};
324
325static struct mii_phy_def cis8201_phy_def = {
326 .phy_id = 0x000fc410,
327 .phy_id_mask = 0x000ffff0,
328 .name = "CIS8201 Gigabit Ethernet",
329 .ops = &cis8201_phy_ops
330};
331
332static struct mii_phy_def *mii_phy_table[] = {
333 &cis8201_phy_def,
334 &genmii_phy_def,
335 NULL
336};
337
338int mii_phy_probe(struct mii_phy *phy, int address)
339{
340 struct mii_phy_def *def;
341 int i;
342 int id;
343
344 phy->autoneg = AUTONEG_DISABLE;
345 phy->advertising = 0;
346 phy->address = address;
347 phy->speed = SPEED_10;
348 phy->duplex = DUPLEX_HALF;
349 phy->pause = phy->asym_pause = 0;
350
351 /* Take PHY out of isolate mode and reset it. */
352 if (mii_reset_phy(phy))
353 return -ENODEV;
354
355 /* Read ID and find matching entry */
356 id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2);
357 if (id < 0)
358 return -ENODEV;
359 for (i = 0; (def = mii_phy_table[i]) != NULL; i++)
360 if ((id & def->phy_id_mask) == def->phy_id)
361 break;
362 /* Should never be NULL (we have a generic entry), but... */
363 if (!def)
364 return -ENODEV;
365
366 phy->def = def;
367
368 /* Determine PHY features if needed */
369 phy->features = def->features;
370 if (!phy->features) {
371 u16 bmsr = phy_read(phy, MII_BMSR);
372 if (bmsr & BMSR_ANEGCAPABLE)
373 phy->features |= SUPPORTED_Autoneg;
374 if (bmsr & BMSR_10HALF)
375 phy->features |= SUPPORTED_10baseT_Half;
376 if (bmsr & BMSR_10FULL)
377 phy->features |= SUPPORTED_10baseT_Full;
378 if (bmsr & BMSR_100HALF)
379 phy->features |= SUPPORTED_100baseT_Half;
380 if (bmsr & BMSR_100FULL)
381 phy->features |= SUPPORTED_100baseT_Full;
382 if (bmsr & BMSR_ESTATEN) {
383 u16 esr = phy_read(phy, MII_ESTATUS);
384 if (esr & ESTATUS_1000_TFULL)
385 phy->features |= SUPPORTED_1000baseT_Full;
386 if (esr & ESTATUS_1000_THALF)
387 phy->features |= SUPPORTED_1000baseT_Half;
388 }
389 phy->features |= SUPPORTED_MII;
390 }
391
392 /* Setup default advertising */
393 phy->advertising = phy->features;
394
395 return 0;
396}
397
398MODULE_LICENSE("GPL");
diff --git a/drivers/net/ibm_emac/ibm_emac_phy.h b/drivers/net/ibm_emac/ibm_emac_phy.h
deleted file mode 100644
index a70e0fea54c4..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_phy.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_phy.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support
5 *
6 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
7 * February 2003
8 *
9 * Minor additions by Eugene Surovegin <ebs@ebshome.net>, 2004
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This file basically duplicates sungem_phy.{c,h} with different PHYs
17 * supported. I'm looking into merging that in a single mii layer more
18 * flexible than mii.c
19 */
20
21#ifndef _IBM_OCP_PHY_H_
22#define _IBM_OCP_PHY_H_
23
24struct mii_phy;
25
26/* Operations supported by any kind of PHY */
27struct mii_phy_ops {
28 int (*init) (struct mii_phy * phy);
29 int (*suspend) (struct mii_phy * phy, int wol_options);
30 int (*setup_aneg) (struct mii_phy * phy, u32 advertise);
31 int (*setup_forced) (struct mii_phy * phy, int speed, int fd);
32 int (*poll_link) (struct mii_phy * phy);
33 int (*read_link) (struct mii_phy * phy);
34};
35
36/* Structure used to statically define an mii/gii based PHY */
37struct mii_phy_def {
38 u32 phy_id; /* Concatenated ID1 << 16 | ID2 */
39 u32 phy_id_mask; /* Significant bits */
40 u32 features; /* Ethtool SUPPORTED_* defines or
41 0 for autodetect */
42 int magic_aneg; /* Autoneg does all speed test for us */
43 const char *name;
44 const struct mii_phy_ops *ops;
45};
46
47/* An instance of a PHY, partially borrowed from mii_if_info */
48struct mii_phy {
49 struct mii_phy_def *def;
50 u32 advertising; /* Ethtool ADVERTISED_* defines */
51 u32 features; /* Copied from mii_phy_def.features
52 or determined automaticaly */
53 int address; /* PHY address */
54 int mode; /* PHY mode */
55
56 /* 1: autoneg enabled, 0: disabled */
57 int autoneg;
58
59 /* forced speed & duplex (no autoneg)
60 * partner speed & duplex & pause (autoneg)
61 */
62 int speed;
63 int duplex;
64 int pause;
65 int asym_pause;
66
67 /* Provided by host chip */
68 struct net_device *dev;
69 int (*mdio_read) (struct net_device * dev, int addr, int reg);
70 void (*mdio_write) (struct net_device * dev, int addr, int reg,
71 int val);
72};
73
74/* Pass in a struct mii_phy with dev, mdio_read and mdio_write
75 * filled, the remaining fields will be filled on return
76 */
77int mii_phy_probe(struct mii_phy *phy, int address);
78int mii_reset_phy(struct mii_phy *phy);
79
80#endif /* _IBM_OCP_PHY_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_rgmii.c b/drivers/net/ibm_emac/ibm_emac_rgmii.c
deleted file mode 100644
index 9dbb5e5936c3..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_rgmii.c
+++ /dev/null
@@ -1,200 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_rgmii.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, RGMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * Copyright 2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#include <linux/kernel.h>
20#include <linux/ethtool.h>
21#include <asm/io.h>
22
23#include "ibm_emac_core.h"
24#include "ibm_emac_debug.h"
25
26/* RGMIIx_FER */
27#define RGMII_FER_MASK(idx) (0x7 << ((idx) * 4))
28#define RGMII_FER_RTBI(idx) (0x4 << ((idx) * 4))
29#define RGMII_FER_RGMII(idx) (0x5 << ((idx) * 4))
30#define RGMII_FER_TBI(idx) (0x6 << ((idx) * 4))
31#define RGMII_FER_GMII(idx) (0x7 << ((idx) * 4))
32
33/* RGMIIx_SSR */
34#define RGMII_SSR_MASK(idx) (0x7 << ((idx) * 8))
35#define RGMII_SSR_100(idx) (0x2 << ((idx) * 8))
36#define RGMII_SSR_1000(idx) (0x4 << ((idx) * 8))
37
38/* RGMII bridge supports only GMII/TBI and RGMII/RTBI PHYs */
39static inline int rgmii_valid_mode(int phy_mode)
40{
41 return phy_mode == PHY_MODE_GMII ||
42 phy_mode == PHY_MODE_RGMII ||
43 phy_mode == PHY_MODE_TBI ||
44 phy_mode == PHY_MODE_RTBI;
45}
46
47static inline const char *rgmii_mode_name(int mode)
48{
49 switch (mode) {
50 case PHY_MODE_RGMII:
51 return "RGMII";
52 case PHY_MODE_TBI:
53 return "TBI";
54 case PHY_MODE_GMII:
55 return "GMII";
56 case PHY_MODE_RTBI:
57 return "RTBI";
58 default:
59 BUG();
60 }
61}
62
63static inline u32 rgmii_mode_mask(int mode, int input)
64{
65 switch (mode) {
66 case PHY_MODE_RGMII:
67 return RGMII_FER_RGMII(input);
68 case PHY_MODE_TBI:
69 return RGMII_FER_TBI(input);
70 case PHY_MODE_GMII:
71 return RGMII_FER_GMII(input);
72 case PHY_MODE_RTBI:
73 return RGMII_FER_RTBI(input);
74 default:
75 BUG();
76 }
77}
78
79static int __init rgmii_init(struct ocp_device *ocpdev, int input, int mode)
80{
81 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
82 struct rgmii_regs *p;
83
84 RGMII_DBG("%d: init(%d, %d)" NL, ocpdev->def->index, input, mode);
85
86 if (!dev) {
87 dev = kzalloc(sizeof(struct ibm_ocp_rgmii), GFP_KERNEL);
88 if (!dev) {
89 printk(KERN_ERR
90 "rgmii%d: couldn't allocate device structure!\n",
91 ocpdev->def->index);
92 return -ENOMEM;
93 }
94
95 p = (struct rgmii_regs *)ioremap(ocpdev->def->paddr,
96 sizeof(struct rgmii_regs));
97 if (!p) {
98 printk(KERN_ERR
99 "rgmii%d: could not ioremap device registers!\n",
100 ocpdev->def->index);
101 kfree(dev);
102 return -ENOMEM;
103 }
104
105 dev->base = p;
106 ocp_set_drvdata(ocpdev, dev);
107
108 /* Disable all inputs by default */
109 out_be32(&p->fer, 0);
110 } else
111 p = dev->base;
112
113 /* Enable this input */
114 out_be32(&p->fer, in_be32(&p->fer) | rgmii_mode_mask(mode, input));
115
116 printk(KERN_NOTICE "rgmii%d: input %d in %s mode\n",
117 ocpdev->def->index, input, rgmii_mode_name(mode));
118
119 ++dev->users;
120 return 0;
121}
122
123int __init rgmii_attach(void *emac)
124{
125 struct ocp_enet_private *dev = emac;
126 struct ocp_func_emac_data *emacdata = dev->def->additions;
127
128 /* Check if we need to attach to a RGMII */
129 if (emacdata->rgmii_idx >= 0 && rgmii_valid_mode(emacdata->phy_mode)) {
130 dev->rgmii_input = emacdata->rgmii_mux;
131 dev->rgmii_dev =
132 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_RGMII,
133 emacdata->rgmii_idx);
134 if (!dev->rgmii_dev) {
135 printk(KERN_ERR "emac%d: unknown rgmii%d!\n",
136 dev->def->index, emacdata->rgmii_idx);
137 return -ENODEV;
138 }
139 if (rgmii_init
140 (dev->rgmii_dev, dev->rgmii_input, emacdata->phy_mode)) {
141 printk(KERN_ERR
142 "emac%d: rgmii%d initialization failed!\n",
143 dev->def->index, emacdata->rgmii_idx);
144 return -ENODEV;
145 }
146 }
147 return 0;
148}
149
150void rgmii_set_speed(struct ocp_device *ocpdev, int input, int speed)
151{
152 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
153 u32 ssr = in_be32(&dev->base->ssr) & ~RGMII_SSR_MASK(input);
154
155 RGMII_DBG("%d: speed(%d, %d)" NL, ocpdev->def->index, input, speed);
156
157 if (speed == SPEED_1000)
158 ssr |= RGMII_SSR_1000(input);
159 else if (speed == SPEED_100)
160 ssr |= RGMII_SSR_100(input);
161
162 out_be32(&dev->base->ssr, ssr);
163}
164
165void __rgmii_fini(struct ocp_device *ocpdev, int input)
166{
167 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
168 BUG_ON(!dev || dev->users == 0);
169
170 RGMII_DBG("%d: fini(%d)" NL, ocpdev->def->index, input);
171
172 /* Disable this input */
173 out_be32(&dev->base->fer,
174 in_be32(&dev->base->fer) & ~RGMII_FER_MASK(input));
175
176 if (!--dev->users) {
177 /* Free everything if this is the last user */
178 ocp_set_drvdata(ocpdev, NULL);
179 iounmap((void *)dev->base);
180 kfree(dev);
181 }
182}
183
184int __rgmii_get_regs_len(struct ocp_device *ocpdev)
185{
186 return sizeof(struct emac_ethtool_regs_subhdr) +
187 sizeof(struct rgmii_regs);
188}
189
190void *rgmii_dump_regs(struct ocp_device *ocpdev, void *buf)
191{
192 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
193 struct emac_ethtool_regs_subhdr *hdr = buf;
194 struct rgmii_regs *regs = (struct rgmii_regs *)(hdr + 1);
195
196 hdr->version = 0;
197 hdr->index = ocpdev->def->index;
198 memcpy_fromio(regs, dev->base, sizeof(struct rgmii_regs));
199 return regs + 1;
200}
diff --git a/drivers/net/ibm_emac/ibm_emac_rgmii.h b/drivers/net/ibm_emac/ibm_emac_rgmii.h
deleted file mode 100644
index 971e45815c6c..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_rgmii.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_rgmii.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, RGMII bridge support.
5 *
6 * Based on ocp_zmii.h/ibm_emac_zmii.h
7 * Armin Kuster akuster@mvista.com
8 *
9 * Copyright 2004 MontaVista Software, Inc.
10 * Matt Porter <mporter@kernel.crashing.org>
11 *
12 * Copyright (c) 2004, 2005 Zultys Technologies.
13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifndef _IBM_EMAC_RGMII_H_
22#define _IBM_EMAC_RGMII_H_
23
24
25/* RGMII bridge */
26struct rgmii_regs {
27 u32 fer; /* Function enable register */
28 u32 ssr; /* Speed select register */
29};
30
31/* RGMII device */
32struct ibm_ocp_rgmii {
33 struct rgmii_regs __iomem *base;
34 int users; /* number of EMACs using this RGMII bridge */
35};
36
37#ifdef CONFIG_IBM_EMAC_RGMII
38int rgmii_attach(void *emac) __init;
39
40void __rgmii_fini(struct ocp_device *ocpdev, int input);
41static inline void rgmii_fini(struct ocp_device *ocpdev, int input)
42{
43 if (ocpdev)
44 __rgmii_fini(ocpdev, input);
45}
46
47void rgmii_set_speed(struct ocp_device *ocpdev, int input, int speed);
48
49int __rgmii_get_regs_len(struct ocp_device *ocpdev);
50static inline int rgmii_get_regs_len(struct ocp_device *ocpdev)
51{
52 return ocpdev ? __rgmii_get_regs_len(ocpdev) : 0;
53}
54
55void *rgmii_dump_regs(struct ocp_device *ocpdev, void *buf);
56#else
57# define rgmii_attach(x) 0
58# define rgmii_fini(x,y) ((void)0)
59# define rgmii_set_speed(x,y,z) ((void)0)
60# define rgmii_get_regs_len(x) 0
61# define rgmii_dump_regs(x,buf) (buf)
62#endif /* !CONFIG_IBM_EMAC_RGMII */
63
64#endif /* _IBM_EMAC_RGMII_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_tah.c b/drivers/net/ibm_emac/ibm_emac_tah.c
deleted file mode 100644
index 3c2d5ba522a1..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_tah.c
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_tah.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, TAH support.
5 *
6 * Copyright 2004 MontaVista Software, Inc.
7 * Matt Porter <mporter@kernel.crashing.org>
8 *
9 * Copyright (c) 2005 Eugene Surovegin <ebs@ebshome.net>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <asm/io.h>
17
18#include "ibm_emac_core.h"
19
20static int __init tah_init(struct ocp_device *ocpdev)
21{
22 struct tah_regs *p;
23
24 if (ocp_get_drvdata(ocpdev)) {
25 printk(KERN_ERR "tah%d: already in use!\n", ocpdev->def->index);
26 return -EBUSY;
27 }
28
29 /* Initialize TAH and enable IPv4 checksum verification, no TSO yet */
30 p = (struct tah_regs *)ioremap(ocpdev->def->paddr, sizeof(*p));
31 if (!p) {
32 printk(KERN_ERR "tah%d: could not ioremap device registers!\n",
33 ocpdev->def->index);
34 return -ENOMEM;
35 }
36 ocp_set_drvdata(ocpdev, p);
37 __tah_reset(ocpdev);
38
39 return 0;
40}
41
42int __init tah_attach(void *emac)
43{
44 struct ocp_enet_private *dev = emac;
45 struct ocp_func_emac_data *emacdata = dev->def->additions;
46
47 /* Check if we need to attach to a TAH */
48 if (emacdata->tah_idx >= 0) {
49 dev->tah_dev = ocp_find_device(OCP_ANY_ID, OCP_FUNC_TAH,
50 emacdata->tah_idx);
51 if (!dev->tah_dev) {
52 printk(KERN_ERR "emac%d: unknown tah%d!\n",
53 dev->def->index, emacdata->tah_idx);
54 return -ENODEV;
55 }
56 if (tah_init(dev->tah_dev)) {
57 printk(KERN_ERR
58 "emac%d: tah%d initialization failed!\n",
59 dev->def->index, emacdata->tah_idx);
60 return -ENODEV;
61 }
62 }
63 return 0;
64}
65
66void __tah_fini(struct ocp_device *ocpdev)
67{
68 struct tah_regs *p = ocp_get_drvdata(ocpdev);
69 BUG_ON(!p);
70 ocp_set_drvdata(ocpdev, NULL);
71 iounmap((void *)p);
72}
73
74void __tah_reset(struct ocp_device *ocpdev)
75{
76 struct tah_regs *p = ocp_get_drvdata(ocpdev);
77 int n;
78
79 /* Reset TAH */
80 out_be32(&p->mr, TAH_MR_SR);
81 n = 100;
82 while ((in_be32(&p->mr) & TAH_MR_SR) && n)
83 --n;
84
85 if (unlikely(!n))
86 printk(KERN_ERR "tah%d: reset timeout\n", ocpdev->def->index);
87
88 /* 10KB TAH TX FIFO accomodates the max MTU of 9000 */
89 out_be32(&p->mr,
90 TAH_MR_CVR | TAH_MR_ST_768 | TAH_MR_TFS_10KB | TAH_MR_DTFP |
91 TAH_MR_DIG);
92}
93
94int __tah_get_regs_len(struct ocp_device *ocpdev)
95{
96 return sizeof(struct emac_ethtool_regs_subhdr) +
97 sizeof(struct tah_regs);
98}
99
100void *tah_dump_regs(struct ocp_device *ocpdev, void *buf)
101{
102 struct tah_regs *dev = ocp_get_drvdata(ocpdev);
103 struct emac_ethtool_regs_subhdr *hdr = buf;
104 struct tah_regs *regs = (struct tah_regs *)(hdr + 1);
105
106 hdr->version = 0;
107 hdr->index = ocpdev->def->index;
108 memcpy_fromio(regs, dev, sizeof(struct tah_regs));
109 return regs + 1;
110}
diff --git a/drivers/net/ibm_emac/ibm_emac_tah.h b/drivers/net/ibm_emac/ibm_emac_tah.h
deleted file mode 100644
index ccf64915e1e4..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_tah.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_tah.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, TAH support.
5 *
6 * Copyright 2004 MontaVista Software, Inc.
7 * Matt Porter <mporter@kernel.crashing.org>
8 *
9 * Copyright (c) 2005 Eugene Surovegin <ebs@ebshome.net>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#ifndef _IBM_EMAC_TAH_H
18#define _IBM_EMAC_TAH_H
19
20#include <linux/init.h>
21#include <asm/ocp.h>
22
23/* TAH */
24struct tah_regs {
25 u32 revid;
26 u32 pad[3];
27 u32 mr;
28 u32 ssr0;
29 u32 ssr1;
30 u32 ssr2;
31 u32 ssr3;
32 u32 ssr4;
33 u32 ssr5;
34 u32 tsr;
35};
36
37/* TAH engine */
38#define TAH_MR_CVR 0x80000000
39#define TAH_MR_SR 0x40000000
40#define TAH_MR_ST_256 0x01000000
41#define TAH_MR_ST_512 0x02000000
42#define TAH_MR_ST_768 0x03000000
43#define TAH_MR_ST_1024 0x04000000
44#define TAH_MR_ST_1280 0x05000000
45#define TAH_MR_ST_1536 0x06000000
46#define TAH_MR_TFS_16KB 0x00000000
47#define TAH_MR_TFS_2KB 0x00200000
48#define TAH_MR_TFS_4KB 0x00400000
49#define TAH_MR_TFS_6KB 0x00600000
50#define TAH_MR_TFS_8KB 0x00800000
51#define TAH_MR_TFS_10KB 0x00a00000
52#define TAH_MR_DTFP 0x00100000
53#define TAH_MR_DIG 0x00080000
54
55#ifdef CONFIG_IBM_EMAC_TAH
56int tah_attach(void *emac) __init;
57
58void __tah_fini(struct ocp_device *ocpdev);
59static inline void tah_fini(struct ocp_device *ocpdev)
60{
61 if (ocpdev)
62 __tah_fini(ocpdev);
63}
64
65void __tah_reset(struct ocp_device *ocpdev);
66static inline void tah_reset(struct ocp_device *ocpdev)
67{
68 if (ocpdev)
69 __tah_reset(ocpdev);
70}
71
72int __tah_get_regs_len(struct ocp_device *ocpdev);
73static inline int tah_get_regs_len(struct ocp_device *ocpdev)
74{
75 return ocpdev ? __tah_get_regs_len(ocpdev) : 0;
76}
77
78void *tah_dump_regs(struct ocp_device *ocpdev, void *buf);
79#else
80# define tah_attach(x) 0
81# define tah_fini(x) ((void)0)
82# define tah_reset(x) ((void)0)
83# define tah_get_regs_len(x) 0
84# define tah_dump_regs(x,buf) (buf)
85#endif /* !CONFIG_IBM_EMAC_TAH */
86
87#endif /* _IBM_EMAC_TAH_H */
diff --git a/drivers/net/ibm_emac/ibm_emac_zmii.c b/drivers/net/ibm_emac/ibm_emac_zmii.c
deleted file mode 100644
index 2c0fdb0cabff..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_zmii.c
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_zmii.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, ZMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2001 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#include <linux/kernel.h>
20#include <linux/ethtool.h>
21#include <asm/io.h>
22
23#include "ibm_emac_core.h"
24#include "ibm_emac_debug.h"
25
26/* ZMIIx_FER */
27#define ZMII_FER_MDI(idx) (0x80000000 >> ((idx) * 4))
28#define ZMII_FER_MDI_ALL (ZMII_FER_MDI(0) | ZMII_FER_MDI(1) | \
29 ZMII_FER_MDI(2) | ZMII_FER_MDI(3))
30
31#define ZMII_FER_SMII(idx) (0x40000000 >> ((idx) * 4))
32#define ZMII_FER_RMII(idx) (0x20000000 >> ((idx) * 4))
33#define ZMII_FER_MII(idx) (0x10000000 >> ((idx) * 4))
34
35/* ZMIIx_SSR */
36#define ZMII_SSR_SCI(idx) (0x40000000 >> ((idx) * 4))
37#define ZMII_SSR_FSS(idx) (0x20000000 >> ((idx) * 4))
38#define ZMII_SSR_SP(idx) (0x10000000 >> ((idx) * 4))
39
40/* ZMII only supports MII, RMII and SMII
41 * we also support autodetection for backward compatibility
42 */
43static inline int zmii_valid_mode(int mode)
44{
45 return mode == PHY_MODE_MII ||
46 mode == PHY_MODE_RMII ||
47 mode == PHY_MODE_SMII ||
48 mode == PHY_MODE_NA;
49}
50
51static inline const char *zmii_mode_name(int mode)
52{
53 switch (mode) {
54 case PHY_MODE_MII:
55 return "MII";
56 case PHY_MODE_RMII:
57 return "RMII";
58 case PHY_MODE_SMII:
59 return "SMII";
60 default:
61 BUG();
62 }
63}
64
65static inline u32 zmii_mode_mask(int mode, int input)
66{
67 switch (mode) {
68 case PHY_MODE_MII:
69 return ZMII_FER_MII(input);
70 case PHY_MODE_RMII:
71 return ZMII_FER_RMII(input);
72 case PHY_MODE_SMII:
73 return ZMII_FER_SMII(input);
74 default:
75 return 0;
76 }
77}
78
79static int __init zmii_init(struct ocp_device *ocpdev, int input, int *mode)
80{
81 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
82 struct zmii_regs __iomem *p;
83
84 ZMII_DBG("%d: init(%d, %d)" NL, ocpdev->def->index, input, *mode);
85
86 if (!dev) {
87 dev = kzalloc(sizeof(struct ibm_ocp_zmii), GFP_KERNEL);
88 if (!dev) {
89 printk(KERN_ERR
90 "zmii%d: couldn't allocate device structure!\n",
91 ocpdev->def->index);
92 return -ENOMEM;
93 }
94 dev->mode = PHY_MODE_NA;
95
96 p = ioremap(ocpdev->def->paddr, sizeof(struct zmii_regs));
97 if (!p) {
98 printk(KERN_ERR
99 "zmii%d: could not ioremap device registers!\n",
100 ocpdev->def->index);
101 kfree(dev);
102 return -ENOMEM;
103 }
104 dev->base = p;
105 ocp_set_drvdata(ocpdev, dev);
106
107 /* We may need FER value for autodetection later */
108 dev->fer_save = in_be32(&p->fer);
109
110 /* Disable all inputs by default */
111 out_be32(&p->fer, 0);
112 } else
113 p = dev->base;
114
115 if (!zmii_valid_mode(*mode)) {
116 /* Probably an EMAC connected to RGMII,
117 * but it still may need ZMII for MDIO
118 */
119 goto out;
120 }
121
122 /* Autodetect ZMII mode if not specified.
123 * This is only for backward compatibility with the old driver.
124 * Please, always specify PHY mode in your board port to avoid
125 * any surprises.
126 */
127 if (dev->mode == PHY_MODE_NA) {
128 if (*mode == PHY_MODE_NA) {
129 u32 r = dev->fer_save;
130
131 ZMII_DBG("%d: autodetecting mode, FER = 0x%08x" NL,
132 ocpdev->def->index, r);
133
134 if (r & (ZMII_FER_MII(0) | ZMII_FER_MII(1)))
135 dev->mode = PHY_MODE_MII;
136 else if (r & (ZMII_FER_RMII(0) | ZMII_FER_RMII(1)))
137 dev->mode = PHY_MODE_RMII;
138 else
139 dev->mode = PHY_MODE_SMII;
140 } else
141 dev->mode = *mode;
142
143 printk(KERN_NOTICE "zmii%d: bridge in %s mode\n",
144 ocpdev->def->index, zmii_mode_name(dev->mode));
145 } else {
146 /* All inputs must use the same mode */
147 if (*mode != PHY_MODE_NA && *mode != dev->mode) {
148 printk(KERN_ERR
149 "zmii%d: invalid mode %d specified for input %d\n",
150 ocpdev->def->index, *mode, input);
151 return -EINVAL;
152 }
153 }
154
155 /* Report back correct PHY mode,
156 * it may be used during PHY initialization.
157 */
158 *mode = dev->mode;
159
160 /* Enable this input */
161 out_be32(&p->fer, in_be32(&p->fer) | zmii_mode_mask(dev->mode, input));
162 out:
163 ++dev->users;
164 return 0;
165}
166
167int __init zmii_attach(void *emac)
168{
169 struct ocp_enet_private *dev = emac;
170 struct ocp_func_emac_data *emacdata = dev->def->additions;
171
172 if (emacdata->zmii_idx >= 0) {
173 dev->zmii_input = emacdata->zmii_mux;
174 dev->zmii_dev =
175 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_ZMII,
176 emacdata->zmii_idx);
177 if (!dev->zmii_dev) {
178 printk(KERN_ERR "emac%d: unknown zmii%d!\n",
179 dev->def->index, emacdata->zmii_idx);
180 return -ENODEV;
181 }
182 if (zmii_init
183 (dev->zmii_dev, dev->zmii_input, &emacdata->phy_mode)) {
184 printk(KERN_ERR
185 "emac%d: zmii%d initialization failed!\n",
186 dev->def->index, emacdata->zmii_idx);
187 return -ENODEV;
188 }
189 }
190 return 0;
191}
192
193void __zmii_enable_mdio(struct ocp_device *ocpdev, int input)
194{
195 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
196 u32 fer = in_be32(&dev->base->fer) & ~ZMII_FER_MDI_ALL;
197
198 ZMII_DBG2("%d: mdio(%d)" NL, ocpdev->def->index, input);
199
200 out_be32(&dev->base->fer, fer | ZMII_FER_MDI(input));
201}
202
203void __zmii_set_speed(struct ocp_device *ocpdev, int input, int speed)
204{
205 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
206 u32 ssr = in_be32(&dev->base->ssr);
207
208 ZMII_DBG("%d: speed(%d, %d)" NL, ocpdev->def->index, input, speed);
209
210 if (speed == SPEED_100)
211 ssr |= ZMII_SSR_SP(input);
212 else
213 ssr &= ~ZMII_SSR_SP(input);
214
215 out_be32(&dev->base->ssr, ssr);
216}
217
218void __zmii_fini(struct ocp_device *ocpdev, int input)
219{
220 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
221 BUG_ON(!dev || dev->users == 0);
222
223 ZMII_DBG("%d: fini(%d)" NL, ocpdev->def->index, input);
224
225 /* Disable this input */
226 out_be32(&dev->base->fer,
227 in_be32(&dev->base->fer) & ~zmii_mode_mask(dev->mode, input));
228
229 if (!--dev->users) {
230 /* Free everything if this is the last user */
231 ocp_set_drvdata(ocpdev, NULL);
232 iounmap(dev->base);
233 kfree(dev);
234 }
235}
236
237int __zmii_get_regs_len(struct ocp_device *ocpdev)
238{
239 return sizeof(struct emac_ethtool_regs_subhdr) +
240 sizeof(struct zmii_regs);
241}
242
243void *zmii_dump_regs(struct ocp_device *ocpdev, void *buf)
244{
245 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
246 struct emac_ethtool_regs_subhdr *hdr = buf;
247 struct zmii_regs *regs = (struct zmii_regs *)(hdr + 1);
248
249 hdr->version = 0;
250 hdr->index = ocpdev->def->index;
251 memcpy_fromio(regs, dev->base, sizeof(struct zmii_regs));
252 return regs + 1;
253}
diff --git a/drivers/net/ibm_emac/ibm_emac_zmii.h b/drivers/net/ibm_emac/ibm_emac_zmii.h
deleted file mode 100644
index fad6d8bf983a..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_zmii.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_zmii.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, ZMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2001 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#ifndef _IBM_EMAC_ZMII_H_
20#define _IBM_EMAC_ZMII_H_
21
22#include <linux/init.h>
23#include <asm/ocp.h>
24
25/* ZMII bridge registers */
26struct zmii_regs {
27 u32 fer; /* Function enable reg */
28 u32 ssr; /* Speed select reg */
29 u32 smiirs; /* SMII status reg */
30};
31
32/* ZMII device */
33struct ibm_ocp_zmii {
34 struct zmii_regs __iomem *base;
35 int mode; /* subset of PHY_MODE_XXXX */
36 int users; /* number of EMACs using this ZMII bridge */
37 u32 fer_save; /* FER value left by firmware */
38};
39
40#ifdef CONFIG_IBM_EMAC_ZMII
41int zmii_attach(void *emac) __init;
42
43void __zmii_fini(struct ocp_device *ocpdev, int input);
44static inline void zmii_fini(struct ocp_device *ocpdev, int input)
45{
46 if (ocpdev)
47 __zmii_fini(ocpdev, input);
48}
49
50void __zmii_enable_mdio(struct ocp_device *ocpdev, int input);
51static inline void zmii_enable_mdio(struct ocp_device *ocpdev, int input)
52{
53 if (ocpdev)
54 __zmii_enable_mdio(ocpdev, input);
55}
56
57void __zmii_set_speed(struct ocp_device *ocpdev, int input, int speed);
58static inline void zmii_set_speed(struct ocp_device *ocpdev, int input,
59 int speed)
60{
61 if (ocpdev)
62 __zmii_set_speed(ocpdev, input, speed);
63}
64
65int __zmii_get_regs_len(struct ocp_device *ocpdev);
66static inline int zmii_get_regs_len(struct ocp_device *ocpdev)
67{
68 return ocpdev ? __zmii_get_regs_len(ocpdev) : 0;
69}
70
71void *zmii_dump_regs(struct ocp_device *ocpdev, void *buf);
72
73#else
74# define zmii_attach(x) 0
75# define zmii_fini(x,y) ((void)0)
76# define zmii_enable_mdio(x,y) ((void)0)
77# define zmii_set_speed(x,y,z) ((void)0)
78# define zmii_get_regs_len(x) 0
79# define zmii_dump_regs(x,buf) (buf)
80#endif /* !CONFIG_IBM_EMAC_ZMII */
81
82#endif /* _IBM_EMAC_ZMII_H_ */
diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c
index 61af02b4c9d8..2e720f26ca83 100644
--- a/drivers/net/ibm_newemac/core.c
+++ b/drivers/net/ibm_newemac/core.c
@@ -295,7 +295,9 @@ static void emac_rx_disable(struct emac_instance *dev)
295static inline void emac_netif_stop(struct emac_instance *dev) 295static inline void emac_netif_stop(struct emac_instance *dev)
296{ 296{
297 netif_tx_lock_bh(dev->ndev); 297 netif_tx_lock_bh(dev->ndev);
298 netif_addr_lock(dev->ndev);
298 dev->no_mcast = 1; 299 dev->no_mcast = 1;
300 netif_addr_unlock(dev->ndev);
299 netif_tx_unlock_bh(dev->ndev); 301 netif_tx_unlock_bh(dev->ndev);
300 dev->ndev->trans_start = jiffies; /* prevent tx timeout */ 302 dev->ndev->trans_start = jiffies; /* prevent tx timeout */
301 mal_poll_disable(dev->mal, &dev->commac); 303 mal_poll_disable(dev->mal, &dev->commac);
@@ -305,9 +307,11 @@ static inline void emac_netif_stop(struct emac_instance *dev)
305static inline void emac_netif_start(struct emac_instance *dev) 307static inline void emac_netif_start(struct emac_instance *dev)
306{ 308{
307 netif_tx_lock_bh(dev->ndev); 309 netif_tx_lock_bh(dev->ndev);
310 netif_addr_lock(dev->ndev);
308 dev->no_mcast = 0; 311 dev->no_mcast = 0;
309 if (dev->mcast_pending && netif_running(dev->ndev)) 312 if (dev->mcast_pending && netif_running(dev->ndev))
310 __emac_set_multicast_list(dev); 313 __emac_set_multicast_list(dev);
314 netif_addr_unlock(dev->ndev);
311 netif_tx_unlock_bh(dev->ndev); 315 netif_tx_unlock_bh(dev->ndev);
312 316
313 netif_wake_queue(dev->ndev); 317 netif_wake_queue(dev->ndev);
diff --git a/drivers/net/ifb.c b/drivers/net/ifb.c
index af233b591534..0960e69b2da4 100644
--- a/drivers/net/ifb.c
+++ b/drivers/net/ifb.c
@@ -35,7 +35,6 @@
35#include <linux/moduleparam.h> 35#include <linux/moduleparam.h>
36#include <net/pkt_sched.h> 36#include <net/pkt_sched.h>
37#include <net/net_namespace.h> 37#include <net/net_namespace.h>
38#include <linux/lockdep.h>
39 38
40#define TX_TIMEOUT (2*HZ) 39#define TX_TIMEOUT (2*HZ)
41 40
@@ -228,16 +227,6 @@ static struct rtnl_link_ops ifb_link_ops __read_mostly = {
228module_param(numifbs, int, 0); 227module_param(numifbs, int, 0);
229MODULE_PARM_DESC(numifbs, "Number of ifb devices"); 228MODULE_PARM_DESC(numifbs, "Number of ifb devices");
230 229
231/*
232 * dev_ifb->queue_lock is usually taken after dev->ingress_lock,
233 * reversely to e.g. qdisc_lock_tree(). It should be safe until
234 * ifb doesn't take dev->queue_lock with dev_ifb->ingress_lock.
235 * But lockdep should know that ifb has different locks from dev.
236 */
237static struct lock_class_key ifb_queue_lock_key;
238static struct lock_class_key ifb_ingress_lock_key;
239
240
241static int __init ifb_init_one(int index) 230static int __init ifb_init_one(int index)
242{ 231{
243 struct net_device *dev_ifb; 232 struct net_device *dev_ifb;
@@ -258,9 +247,6 @@ static int __init ifb_init_one(int index)
258 if (err < 0) 247 if (err < 0)
259 goto err; 248 goto err;
260 249
261 lockdep_set_class(&dev_ifb->queue_lock, &ifb_queue_lock_key);
262 lockdep_set_class(&dev_ifb->ingress_lock, &ifb_ingress_lock_key);
263
264 return 0; 250 return 0;
265 251
266err: 252err:
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index cda3ec879090..e098f234770f 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel(R) Gigabit Ethernet Linux driver 3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation. 4 Copyright(c) 2007 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -31,6 +31,7 @@
31 31
32#include <linux/types.h> 32#include <linux/types.h>
33#include <linux/slab.h> 33#include <linux/slab.h>
34#include <linux/if_ether.h>
34 35
35#include "e1000_mac.h" 36#include "e1000_mac.h"
36#include "e1000_82575.h" 37#include "e1000_82575.h"
@@ -45,7 +46,6 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45static s32 igb_init_hw_82575(struct e1000_hw *); 46static s32 igb_init_hw_82575(struct e1000_hw *);
46static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); 47static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); 48static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
48static void igb_rar_set_82575(struct e1000_hw *, u8 *, u32);
49static s32 igb_reset_hw_82575(struct e1000_hw *); 49static s32 igb_reset_hw_82575(struct e1000_hw *);
50static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); 50static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
51static s32 igb_setup_copper_link_82575(struct e1000_hw *); 51static s32 igb_setup_copper_link_82575(struct e1000_hw *);
@@ -84,6 +84,12 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
84 case E1000_DEV_ID_82575GB_QUAD_COPPER: 84 case E1000_DEV_ID_82575GB_QUAD_COPPER:
85 mac->type = e1000_82575; 85 mac->type = e1000_82575;
86 break; 86 break;
87 case E1000_DEV_ID_82576:
88 case E1000_DEV_ID_82576_FIBER:
89 case E1000_DEV_ID_82576_SERDES:
90 case E1000_DEV_ID_82576_QUAD_COPPER:
91 mac->type = e1000_82576;
92 break;
87 default: 93 default:
88 return -E1000_ERR_MAC_INIT; 94 return -E1000_ERR_MAC_INIT;
89 break; 95 break;
@@ -128,6 +134,8 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
128 mac->mta_reg_count = 128; 134 mac->mta_reg_count = 128;
129 /* Set rar entry count */ 135 /* Set rar entry count */
130 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 136 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
137 if (mac->type == e1000_82576)
138 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
131 /* Set if part includes ASF firmware */ 139 /* Set if part includes ASF firmware */
132 mac->asf_firmware_present = true; 140 mac->asf_firmware_present = true;
133 /* Set if manageability features are enabled. */ 141 /* Set if manageability features are enabled. */
@@ -171,6 +179,10 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
171 * for setting word_size. 179 * for setting word_size.
172 */ 180 */
173 size += NVM_WORD_SIZE_BASE_SHIFT; 181 size += NVM_WORD_SIZE_BASE_SHIFT;
182
183 /* EEPROM access above 16k is unsupported */
184 if (size > 14)
185 size = 14;
174 nvm->word_size = 1 << size; 186 nvm->word_size = 1 << size;
175 187
176 /* setup PHY parameters */ 188 /* setup PHY parameters */
@@ -222,7 +234,7 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
222} 234}
223 235
224/** 236/**
225 * e1000_acquire_phy_82575 - Acquire rights to access PHY 237 * igb_acquire_phy_82575 - Acquire rights to access PHY
226 * @hw: pointer to the HW structure 238 * @hw: pointer to the HW structure
227 * 239 *
228 * Acquire access rights to the correct PHY. This is a 240 * Acquire access rights to the correct PHY. This is a
@@ -238,7 +250,7 @@ static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
238} 250}
239 251
240/** 252/**
241 * e1000_release_phy_82575 - Release rights to access PHY 253 * igb_release_phy_82575 - Release rights to access PHY
242 * @hw: pointer to the HW structure 254 * @hw: pointer to the HW structure
243 * 255 *
244 * A wrapper to release access rights to the correct PHY. This is a 256 * A wrapper to release access rights to the correct PHY. This is a
@@ -253,7 +265,7 @@ static void igb_release_phy_82575(struct e1000_hw *hw)
253} 265}
254 266
255/** 267/**
256 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 268 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
257 * @hw: pointer to the HW structure 269 * @hw: pointer to the HW structure
258 * @offset: register offset to be read 270 * @offset: register offset to be read
259 * @data: pointer to the read data 271 * @data: pointer to the read data
@@ -268,7 +280,7 @@ static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
268 u32 i, i2ccmd = 0; 280 u32 i, i2ccmd = 0;
269 281
270 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 282 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
271 hw_dbg(hw, "PHY Address %u is out of range\n", offset); 283 hw_dbg("PHY Address %u is out of range\n", offset);
272 return -E1000_ERR_PARAM; 284 return -E1000_ERR_PARAM;
273 } 285 }
274 286
@@ -291,11 +303,11 @@ static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
291 break; 303 break;
292 } 304 }
293 if (!(i2ccmd & E1000_I2CCMD_READY)) { 305 if (!(i2ccmd & E1000_I2CCMD_READY)) {
294 hw_dbg(hw, "I2CCMD Read did not complete\n"); 306 hw_dbg("I2CCMD Read did not complete\n");
295 return -E1000_ERR_PHY; 307 return -E1000_ERR_PHY;
296 } 308 }
297 if (i2ccmd & E1000_I2CCMD_ERROR) { 309 if (i2ccmd & E1000_I2CCMD_ERROR) {
298 hw_dbg(hw, "I2CCMD Error bit set\n"); 310 hw_dbg("I2CCMD Error bit set\n");
299 return -E1000_ERR_PHY; 311 return -E1000_ERR_PHY;
300 } 312 }
301 313
@@ -306,7 +318,7 @@ static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
306} 318}
307 319
308/** 320/**
309 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 321 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
310 * @hw: pointer to the HW structure 322 * @hw: pointer to the HW structure
311 * @offset: register offset to write to 323 * @offset: register offset to write to
312 * @data: data to write at register offset 324 * @data: data to write at register offset
@@ -322,7 +334,7 @@ static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
322 u16 phy_data_swapped; 334 u16 phy_data_swapped;
323 335
324 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 336 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
325 hw_dbg(hw, "PHY Address %d is out of range\n", offset); 337 hw_dbg("PHY Address %d is out of range\n", offset);
326 return -E1000_ERR_PARAM; 338 return -E1000_ERR_PARAM;
327 } 339 }
328 340
@@ -349,11 +361,11 @@ static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
349 break; 361 break;
350 } 362 }
351 if (!(i2ccmd & E1000_I2CCMD_READY)) { 363 if (!(i2ccmd & E1000_I2CCMD_READY)) {
352 hw_dbg(hw, "I2CCMD Write did not complete\n"); 364 hw_dbg("I2CCMD Write did not complete\n");
353 return -E1000_ERR_PHY; 365 return -E1000_ERR_PHY;
354 } 366 }
355 if (i2ccmd & E1000_I2CCMD_ERROR) { 367 if (i2ccmd & E1000_I2CCMD_ERROR) {
356 hw_dbg(hw, "I2CCMD Error bit set\n"); 368 hw_dbg("I2CCMD Error bit set\n");
357 return -E1000_ERR_PHY; 369 return -E1000_ERR_PHY;
358 } 370 }
359 371
@@ -361,10 +373,10 @@ static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
361} 373}
362 374
363/** 375/**
364 * e1000_get_phy_id_82575 - Retreive PHY addr and id 376 * igb_get_phy_id_82575 - Retrieve PHY addr and id
365 * @hw: pointer to the HW structure 377 * @hw: pointer to the HW structure
366 * 378 *
367 * Retreives the PHY address and ID for both PHY's which do and do not use 379 * Retrieves the PHY address and ID for both PHY's which do and do not use
368 * sgmi interface. 380 * sgmi interface.
369 **/ 381 **/
370static s32 igb_get_phy_id_82575(struct e1000_hw *hw) 382static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
@@ -393,9 +405,8 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
393 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 405 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
394 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 406 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
395 if (ret_val == 0) { 407 if (ret_val == 0) {
396 hw_dbg(hw, "Vendor ID 0x%08X read at address %u\n", 408 hw_dbg("Vendor ID 0x%08X read at address %u\n",
397 phy_id, 409 phy_id, phy->addr);
398 phy->addr);
399 /* 410 /*
400 * At the time of this writing, The M88 part is 411 * At the time of this writing, The M88 part is
401 * the only supported SGMII PHY product. 412 * the only supported SGMII PHY product.
@@ -403,8 +414,7 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
403 if (phy_id == M88_VENDOR) 414 if (phy_id == M88_VENDOR)
404 break; 415 break;
405 } else { 416 } else {
406 hw_dbg(hw, "PHY address %u was unreadable\n", 417 hw_dbg("PHY address %u was unreadable\n", phy->addr);
407 phy->addr);
408 } 418 }
409 } 419 }
410 420
@@ -422,7 +432,7 @@ out:
422} 432}
423 433
424/** 434/**
425 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 435 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
426 * @hw: pointer to the HW structure 436 * @hw: pointer to the HW structure
427 * 437 *
428 * Resets the PHY using the serial gigabit media independent interface. 438 * Resets the PHY using the serial gigabit media independent interface.
@@ -436,7 +446,7 @@ static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
436 * available to us at this time. 446 * available to us at this time.
437 */ 447 */
438 448
439 hw_dbg(hw, "Soft resetting SGMII attached PHY...\n"); 449 hw_dbg("Soft resetting SGMII attached PHY...\n");
440 450
441 /* 451 /*
442 * SFP documentation requires the following to configure the SPF module 452 * SFP documentation requires the following to configure the SPF module
@@ -453,7 +463,7 @@ out:
453} 463}
454 464
455/** 465/**
456 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 466 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
457 * @hw: pointer to the HW structure 467 * @hw: pointer to the HW structure
458 * @active: true to enable LPLU, false to disable 468 * @active: true to enable LPLU, false to disable
459 * 469 *
@@ -471,34 +481,29 @@ static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
471 s32 ret_val; 481 s32 ret_val;
472 u16 data; 482 u16 data;
473 483
474 ret_val = hw->phy.ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 484 ret_val = phy->ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
475 &data);
476 if (ret_val) 485 if (ret_val)
477 goto out; 486 goto out;
478 487
479 if (active) { 488 if (active) {
480 data |= IGP02E1000_PM_D0_LPLU; 489 data |= IGP02E1000_PM_D0_LPLU;
481 ret_val = hw->phy.ops.write_phy_reg(hw, 490 ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
482 IGP02E1000_PHY_POWER_MGMT, 491 data);
483 data);
484 if (ret_val) 492 if (ret_val)
485 goto out; 493 goto out;
486 494
487 /* When LPLU is enabled, we should disable SmartSpeed */ 495 /* When LPLU is enabled, we should disable SmartSpeed */
488 ret_val = hw->phy.ops.read_phy_reg(hw, 496 ret_val = phy->ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
489 IGP01E1000_PHY_PORT_CONFIG, 497 &data);
490 &data);
491 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 498 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
492 ret_val = hw->phy.ops.write_phy_reg(hw, 499 ret_val = phy->ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
493 IGP01E1000_PHY_PORT_CONFIG, 500 data);
494 data);
495 if (ret_val) 501 if (ret_val)
496 goto out; 502 goto out;
497 } else { 503 } else {
498 data &= ~IGP02E1000_PM_D0_LPLU; 504 data &= ~IGP02E1000_PM_D0_LPLU;
499 ret_val = hw->phy.ops.write_phy_reg(hw, 505 ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
500 IGP02E1000_PHY_POWER_MGMT, 506 data);
501 data);
502 /* 507 /*
503 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 508 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
504 * during Dx states where the power conservation is most 509 * during Dx states where the power conservation is most
@@ -506,29 +511,25 @@ static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
506 * SmartSpeed, so performance is maintained. 511 * SmartSpeed, so performance is maintained.
507 */ 512 */
508 if (phy->smart_speed == e1000_smart_speed_on) { 513 if (phy->smart_speed == e1000_smart_speed_on) {
509 ret_val = hw->phy.ops.read_phy_reg(hw, 514 ret_val = phy->ops.read_phy_reg(hw,
510 IGP01E1000_PHY_PORT_CONFIG, 515 IGP01E1000_PHY_PORT_CONFIG, &data);
511 &data);
512 if (ret_val) 516 if (ret_val)
513 goto out; 517 goto out;
514 518
515 data |= IGP01E1000_PSCFR_SMART_SPEED; 519 data |= IGP01E1000_PSCFR_SMART_SPEED;
516 ret_val = hw->phy.ops.write_phy_reg(hw, 520 ret_val = phy->ops.write_phy_reg(hw,
517 IGP01E1000_PHY_PORT_CONFIG, 521 IGP01E1000_PHY_PORT_CONFIG, data);
518 data);
519 if (ret_val) 522 if (ret_val)
520 goto out; 523 goto out;
521 } else if (phy->smart_speed == e1000_smart_speed_off) { 524 } else if (phy->smart_speed == e1000_smart_speed_off) {
522 ret_val = hw->phy.ops.read_phy_reg(hw, 525 ret_val = phy->ops.read_phy_reg(hw,
523 IGP01E1000_PHY_PORT_CONFIG, 526 IGP01E1000_PHY_PORT_CONFIG, &data);
524 &data);
525 if (ret_val) 527 if (ret_val)
526 goto out; 528 goto out;
527 529
528 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 530 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
529 ret_val = hw->phy.ops.write_phy_reg(hw, 531 ret_val = phy->ops.write_phy_reg(hw,
530 IGP01E1000_PHY_PORT_CONFIG, 532 IGP01E1000_PHY_PORT_CONFIG, data);
531 data);
532 if (ret_val) 533 if (ret_val)
533 goto out; 534 goto out;
534 } 535 }
@@ -539,10 +540,10 @@ out:
539} 540}
540 541
541/** 542/**
542 * e1000_acquire_nvm_82575 - Request for access to EEPROM 543 * igb_acquire_nvm_82575 - Request for access to EEPROM
543 * @hw: pointer to the HW structure 544 * @hw: pointer to the HW structure
544 * 545 *
545 * Acquire the necessary semaphores for exclussive access to the EEPROM. 546 * Acquire the necessary semaphores for exclusive access to the EEPROM.
546 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 547 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
547 * Return successful if access grant bit set, else clear the request for 548 * Return successful if access grant bit set, else clear the request for
548 * EEPROM access and return -E1000_ERR_NVM (-1). 549 * EEPROM access and return -E1000_ERR_NVM (-1).
@@ -565,7 +566,7 @@ out:
565} 566}
566 567
567/** 568/**
568 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 569 * igb_release_nvm_82575 - Release exclusive access to EEPROM
569 * @hw: pointer to the HW structure 570 * @hw: pointer to the HW structure
570 * 571 *
571 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 572 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
@@ -578,7 +579,7 @@ static void igb_release_nvm_82575(struct e1000_hw *hw)
578} 579}
579 580
580/** 581/**
581 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 582 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
582 * @hw: pointer to the HW structure 583 * @hw: pointer to the HW structure
583 * @mask: specifies which semaphore to acquire 584 * @mask: specifies which semaphore to acquire
584 * 585 *
@@ -613,7 +614,7 @@ static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
613 } 614 }
614 615
615 if (i == timeout) { 616 if (i == timeout) {
616 hw_dbg(hw, "Can't access resource, SW_FW_SYNC timeout.\n"); 617 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
617 ret_val = -E1000_ERR_SWFW_SYNC; 618 ret_val = -E1000_ERR_SWFW_SYNC;
618 goto out; 619 goto out;
619 } 620 }
@@ -628,7 +629,7 @@ out:
628} 629}
629 630
630/** 631/**
631 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 632 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
632 * @hw: pointer to the HW structure 633 * @hw: pointer to the HW structure
633 * @mask: specifies which semaphore to acquire 634 * @mask: specifies which semaphore to acquire
634 * 635 *
@@ -650,7 +651,7 @@ static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
650} 651}
651 652
652/** 653/**
653 * e1000_get_cfg_done_82575 - Read config done bit 654 * igb_get_cfg_done_82575 - Read config done bit
654 * @hw: pointer to the HW structure 655 * @hw: pointer to the HW structure
655 * 656 *
656 * Read the management control register for the config done bit for 657 * Read the management control register for the config done bit for
@@ -675,7 +676,7 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
675 timeout--; 676 timeout--;
676 } 677 }
677 if (!timeout) 678 if (!timeout)
678 hw_dbg(hw, "MNG configuration cycle has not completed.\n"); 679 hw_dbg("MNG configuration cycle has not completed.\n");
679 680
680 /* If EEPROM is not marked present, init the PHY manually */ 681 /* If EEPROM is not marked present, init the PHY manually */
681 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && 682 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
@@ -686,7 +687,7 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
686} 687}
687 688
688/** 689/**
689 * e1000_check_for_link_82575 - Check for link 690 * igb_check_for_link_82575 - Check for link
690 * @hw: pointer to the HW structure 691 * @hw: pointer to the HW structure
691 * 692 *
692 * If sgmii is enabled, then use the pcs register to determine link, otherwise 693 * If sgmii is enabled, then use the pcs register to determine link, otherwise
@@ -701,20 +702,19 @@ static s32 igb_check_for_link_82575(struct e1000_hw *hw)
701 if ((hw->phy.media_type != e1000_media_type_copper) || 702 if ((hw->phy.media_type != e1000_media_type_copper) ||
702 (igb_sgmii_active_82575(hw))) 703 (igb_sgmii_active_82575(hw)))
703 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, 704 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
704 &duplex); 705 &duplex);
705 else 706 else
706 ret_val = igb_check_for_copper_link(hw); 707 ret_val = igb_check_for_copper_link(hw);
707 708
708 return ret_val; 709 return ret_val;
709} 710}
710
711/** 711/**
712 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 712 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
713 * @hw: pointer to the HW structure 713 * @hw: pointer to the HW structure
714 * @speed: stores the current speed 714 * @speed: stores the current speed
715 * @duplex: stores the current duplex 715 * @duplex: stores the current duplex
716 * 716 *
717 * Using the physical coding sub-layer (PCS), retreive the current speed and 717 * Using the physical coding sub-layer (PCS), retrieve the current speed and
718 * duplex, then store the values in the pointers provided. 718 * duplex, then store the values in the pointers provided.
719 **/ 719 **/
720static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, 720static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
@@ -764,24 +764,135 @@ static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
764} 764}
765 765
766/** 766/**
767 * e1000_rar_set_82575 - Set receive address register 767 * igb_init_rx_addrs_82575 - Initialize receive address's
768 * @hw: pointer to the HW structure 768 * @hw: pointer to the HW structure
769 * @addr: pointer to the receive address 769 * @rar_count: receive address registers
770 * @index: receive address array register
771 * 770 *
772 * Sets the receive address array register at index to the address passed 771 * Setups the receive address registers by setting the base receive address
773 * in by addr. 772 * register to the devices MAC address and clearing all the other receive
773 * address registers to 0.
774 **/ 774 **/
775static void igb_rar_set_82575(struct e1000_hw *hw, u8 *addr, u32 index) 775static void igb_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count)
776{ 776{
777 if (index < E1000_RAR_ENTRIES_82575) 777 u32 i;
778 igb_rar_set(hw, addr, index); 778 u8 addr[6] = {0,0,0,0,0,0};
779 /*
780 * This function is essentially the same as that of
781 * e1000_init_rx_addrs_generic. However it also takes care
782 * of the special case where the register offset of the
783 * second set of RARs begins elsewhere. This is implicitly taken care by
784 * function e1000_rar_set_generic.
785 */
786
787 hw_dbg("e1000_init_rx_addrs_82575");
788
789 /* Setup the receive address */
790 hw_dbg("Programming MAC Address into RAR[0]\n");
791 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
792
793 /* Zero out the other (rar_entry_count - 1) receive addresses */
794 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
795 for (i = 1; i < rar_count; i++)
796 hw->mac.ops.rar_set(hw, addr, i);
797}
798
799/**
800 * igb_update_mc_addr_list_82575 - Update Multicast addresses
801 * @hw: pointer to the HW structure
802 * @mc_addr_list: array of multicast addresses to program
803 * @mc_addr_count: number of multicast addresses to program
804 * @rar_used_count: the first RAR register free to program
805 * @rar_count: total number of supported Receive Address Registers
806 *
807 * Updates the Receive Address Registers and Multicast Table Array.
808 * The caller must have a packed mc_addr_list of multicast addresses.
809 * The parameter rar_count will usually be hw->mac.rar_entry_count
810 * unless there are workarounds that change this.
811 **/
812void igb_update_mc_addr_list_82575(struct e1000_hw *hw,
813 u8 *mc_addr_list, u32 mc_addr_count,
814 u32 rar_used_count, u32 rar_count)
815{
816 u32 hash_value;
817 u32 i;
818 u8 addr[6] = {0,0,0,0,0,0};
819 /*
820 * This function is essentially the same as that of
821 * igb_update_mc_addr_list_generic. However it also takes care
822 * of the special case where the register offset of the
823 * second set of RARs begins elsewhere. This is implicitly taken care by
824 * function e1000_rar_set_generic.
825 */
826
827 /*
828 * Load the first set of multicast addresses into the exact
829 * filters (RAR). If there are not enough to fill the RAR
830 * array, clear the filters.
831 */
832 for (i = rar_used_count; i < rar_count; i++) {
833 if (mc_addr_count) {
834 igb_rar_set(hw, mc_addr_list, i);
835 mc_addr_count--;
836 mc_addr_list += ETH_ALEN;
837 } else {
838 igb_rar_set(hw, addr, i);
839 }
840 }
841
842 /* Clear the old settings from the MTA */
843 hw_dbg("Clearing MTA\n");
844 for (i = 0; i < hw->mac.mta_reg_count; i++) {
845 array_wr32(E1000_MTA, i, 0);
846 wrfl();
847 }
848
849 /* Load any remaining multicast addresses into the hash table. */
850 for (; mc_addr_count > 0; mc_addr_count--) {
851 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
852 hw_dbg("Hash value = 0x%03X\n", hash_value);
853 hw->mac.ops.mta_set(hw, hash_value);
854 mc_addr_list += ETH_ALEN;
855 }
856}
857
858/**
859 * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down
860 * @hw: pointer to the HW structure
861 *
862 * In the case of fiber serdes, shut down optics and PCS on driver unload
863 * when management pass thru is not enabled.
864 **/
865void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw)
866{
867 u32 reg;
868
869 if (hw->mac.type != e1000_82576 ||
870 (hw->phy.media_type != e1000_media_type_fiber &&
871 hw->phy.media_type != e1000_media_type_internal_serdes))
872 return;
873
874 /* if the management interface is not enabled, then power down */
875 if (!igb_enable_mng_pass_thru(hw)) {
876 /* Disable PCS to turn off link */
877 reg = rd32(E1000_PCS_CFG0);
878 reg &= ~E1000_PCS_CFG_PCS_EN;
879 wr32(E1000_PCS_CFG0, reg);
880
881 /* shutdown the laser */
882 reg = rd32(E1000_CTRL_EXT);
883 reg |= E1000_CTRL_EXT_SDP7_DATA;
884 wr32(E1000_CTRL_EXT, reg);
885
886 /* flush the write to verify completion */
887 wrfl();
888 msleep(1);
889 }
779 890
780 return; 891 return;
781} 892}
782 893
783/** 894/**
784 * e1000_reset_hw_82575 - Reset hardware 895 * igb_reset_hw_82575 - Reset hardware
785 * @hw: pointer to the HW structure 896 * @hw: pointer to the HW structure
786 * 897 *
787 * This resets the hardware into a known state. This is a 898 * This resets the hardware into a known state. This is a
@@ -798,9 +909,9 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
798 */ 909 */
799 ret_val = igb_disable_pcie_master(hw); 910 ret_val = igb_disable_pcie_master(hw);
800 if (ret_val) 911 if (ret_val)
801 hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); 912 hw_dbg("PCI-E Master disable polling has failed.\n");
802 913
803 hw_dbg(hw, "Masking off all interrupts\n"); 914 hw_dbg("Masking off all interrupts\n");
804 wr32(E1000_IMC, 0xffffffff); 915 wr32(E1000_IMC, 0xffffffff);
805 916
806 wr32(E1000_RCTL, 0); 917 wr32(E1000_RCTL, 0);
@@ -811,7 +922,7 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
811 922
812 ctrl = rd32(E1000_CTRL); 923 ctrl = rd32(E1000_CTRL);
813 924
814 hw_dbg(hw, "Issuing a global reset to MAC\n"); 925 hw_dbg("Issuing a global reset to MAC\n");
815 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); 926 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
816 927
817 ret_val = igb_get_auto_rd_done(hw); 928 ret_val = igb_get_auto_rd_done(hw);
@@ -821,7 +932,7 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
821 * return with an error. This can happen in situations 932 * return with an error. This can happen in situations
822 * where there is no eeprom and prevents getting link. 933 * where there is no eeprom and prevents getting link.
823 */ 934 */
824 hw_dbg(hw, "Auto Read Done did not complete\n"); 935 hw_dbg("Auto Read Done did not complete\n");
825 } 936 }
826 937
827 /* If EEPROM is not present, run manual init scripts */ 938 /* If EEPROM is not present, run manual init scripts */
@@ -838,7 +949,7 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
838} 949}
839 950
840/** 951/**
841 * e1000_init_hw_82575 - Initialize hardware 952 * igb_init_hw_82575 - Initialize hardware
842 * @hw: pointer to the HW structure 953 * @hw: pointer to the HW structure
843 * 954 *
844 * This inits the hardware readying it for operation. 955 * This inits the hardware readying it for operation.
@@ -852,18 +963,18 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)
852 /* Initialize identification LED */ 963 /* Initialize identification LED */
853 ret_val = igb_id_led_init(hw); 964 ret_val = igb_id_led_init(hw);
854 if (ret_val) { 965 if (ret_val) {
855 hw_dbg(hw, "Error initializing identification LED\n"); 966 hw_dbg("Error initializing identification LED\n");
856 /* This is not fatal and we should not stop init due to this */ 967 /* This is not fatal and we should not stop init due to this */
857 } 968 }
858 969
859 /* Disabling VLAN filtering */ 970 /* Disabling VLAN filtering */
860 hw_dbg(hw, "Initializing the IEEE VLAN\n"); 971 hw_dbg("Initializing the IEEE VLAN\n");
861 igb_clear_vfta(hw); 972 igb_clear_vfta(hw);
862 973
863 /* Setup the receive address */ 974 /* Setup the receive address */
864 igb_init_rx_addrs(hw, rar_count); 975 igb_init_rx_addrs_82575(hw, rar_count);
865 /* Zero out the Multicast HASH table */ 976 /* Zero out the Multicast HASH table */
866 hw_dbg(hw, "Zeroing the MTA\n"); 977 hw_dbg("Zeroing the MTA\n");
867 for (i = 0; i < mac->mta_reg_count; i++) 978 for (i = 0; i < mac->mta_reg_count; i++)
868 array_wr32(E1000_MTA, i, 0); 979 array_wr32(E1000_MTA, i, 0);
869 980
@@ -882,7 +993,7 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)
882} 993}
883 994
884/** 995/**
885 * e1000_setup_copper_link_82575 - Configure copper link settings 996 * igb_setup_copper_link_82575 - Configure copper link settings
886 * @hw: pointer to the HW structure 997 * @hw: pointer to the HW structure
887 * 998 *
888 * Configures the link for auto-neg or forced speed and duplex. Then we check 999 * Configures the link for auto-neg or forced speed and duplex. Then we check
@@ -933,10 +1044,10 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
933 * PHY will be set to 10H, 10F, 100H or 100F 1044 * PHY will be set to 10H, 10F, 100H or 100F
934 * depending on user settings. 1045 * depending on user settings.
935 */ 1046 */
936 hw_dbg(hw, "Forcing Speed and Duplex\n"); 1047 hw_dbg("Forcing Speed and Duplex\n");
937 ret_val = igb_phy_force_speed_duplex(hw); 1048 ret_val = igb_phy_force_speed_duplex(hw);
938 if (ret_val) { 1049 if (ret_val) {
939 hw_dbg(hw, "Error Forcing Speed and Duplex\n"); 1050 hw_dbg("Error Forcing Speed and Duplex\n");
940 goto out; 1051 goto out;
941 } 1052 }
942 } 1053 }
@@ -949,20 +1060,17 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
949 * Check link status. Wait up to 100 microseconds for link to become 1060 * Check link status. Wait up to 100 microseconds for link to become
950 * valid. 1061 * valid.
951 */ 1062 */
952 ret_val = igb_phy_has_link(hw, 1063 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
953 COPPER_LINK_UP_LIMIT,
954 10,
955 &link);
956 if (ret_val) 1064 if (ret_val)
957 goto out; 1065 goto out;
958 1066
959 if (link) { 1067 if (link) {
960 hw_dbg(hw, "Valid link established!!!\n"); 1068 hw_dbg("Valid link established!!!\n");
961 /* Config the MAC and PHY after link is up */ 1069 /* Config the MAC and PHY after link is up */
962 igb_config_collision_dist(hw); 1070 igb_config_collision_dist(hw);
963 ret_val = igb_config_fc_after_link_up(hw); 1071 ret_val = igb_config_fc_after_link_up(hw);
964 } else { 1072 } else {
965 hw_dbg(hw, "Unable to establish link!!!\n"); 1073 hw_dbg("Unable to establish link!!!\n");
966 } 1074 }
967 1075
968out: 1076out:
@@ -970,7 +1078,7 @@ out:
970} 1078}
971 1079
972/** 1080/**
973 * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes 1081 * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
974 * @hw: pointer to the HW structure 1082 * @hw: pointer to the HW structure
975 * 1083 *
976 * Configures speed and duplex for fiber and serdes links. 1084 * Configures speed and duplex for fiber and serdes links.
@@ -1018,7 +1126,7 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1018 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1126 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1019 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1127 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1020 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1128 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1021 hw_dbg(hw, "Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); 1129 hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1022 } else { 1130 } else {
1023 /* Set PCS register for forced speed */ 1131 /* Set PCS register for forced speed */
1024 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1132 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
@@ -1026,7 +1134,7 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1026 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1134 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1027 E1000_PCS_LCTL_FSD | /* Force Speed */ 1135 E1000_PCS_LCTL_FSD | /* Force Speed */
1028 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1136 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1029 hw_dbg(hw, "Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); 1137 hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1030 } 1138 }
1031 wr32(E1000_PCS_LCTL, reg); 1139 wr32(E1000_PCS_LCTL, reg);
1032 1140
@@ -1034,7 +1142,7 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1034} 1142}
1035 1143
1036/** 1144/**
1037 * e1000_configure_pcs_link_82575 - Configure PCS link 1145 * igb_configure_pcs_link_82575 - Configure PCS link
1038 * @hw: pointer to the HW structure 1146 * @hw: pointer to the HW structure
1039 * 1147 *
1040 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1148 * Configure the physical coding sub-layer (PCS) link. The PCS link is
@@ -1067,7 +1175,7 @@ static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
1067 */ 1175 */
1068 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE; 1176 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
1069 } else { 1177 } else {
1070 /* Set PCS regiseter for forced speed */ 1178 /* Set PCS register for forced speed */
1071 1179
1072 /* Turn off bits for full duplex, speed, and autoneg */ 1180 /* Turn off bits for full duplex, speed, and autoneg */
1073 reg &= ~(E1000_PCS_LCTL_FSV_1000 | 1181 reg &= ~(E1000_PCS_LCTL_FSV_1000 |
@@ -1088,8 +1196,7 @@ static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
1088 E1000_PCS_LCTL_FORCE_LINK | 1196 E1000_PCS_LCTL_FORCE_LINK |
1089 E1000_PCS_LCTL_FLV_LINK_UP; 1197 E1000_PCS_LCTL_FLV_LINK_UP;
1090 1198
1091 hw_dbg(hw, 1199 hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1092 "Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1093 reg); 1200 reg);
1094 } 1201 }
1095 wr32(E1000_PCS_LCTL, reg); 1202 wr32(E1000_PCS_LCTL, reg);
@@ -1099,7 +1206,7 @@ out:
1099} 1206}
1100 1207
1101/** 1208/**
1102 * e1000_sgmii_active_82575 - Return sgmii state 1209 * igb_sgmii_active_82575 - Return sgmii state
1103 * @hw: pointer to the HW structure 1210 * @hw: pointer to the HW structure
1104 * 1211 *
1105 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1212 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
@@ -1125,7 +1232,71 @@ out:
1125} 1232}
1126 1233
1127/** 1234/**
1128 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1235 * igb_translate_register_82576 - Translate the proper register offset
1236 * @reg: e1000 register to be read
1237 *
1238 * Registers in 82576 are located in different offsets than other adapters
1239 * even though they function in the same manner. This function takes in
1240 * the name of the register to read and returns the correct offset for
1241 * 82576 silicon.
1242 **/
1243u32 igb_translate_register_82576(u32 reg)
1244{
1245 /*
1246 * Some of the Kawela registers are located at different
1247 * offsets than they are in older adapters.
1248 * Despite the difference in location, the registers
1249 * function in the same manner.
1250 */
1251 switch (reg) {
1252 case E1000_TDBAL(0):
1253 reg = 0x0E000;
1254 break;
1255 case E1000_TDBAH(0):
1256 reg = 0x0E004;
1257 break;
1258 case E1000_TDLEN(0):
1259 reg = 0x0E008;
1260 break;
1261 case E1000_TDH(0):
1262 reg = 0x0E010;
1263 break;
1264 case E1000_TDT(0):
1265 reg = 0x0E018;
1266 break;
1267 case E1000_TXDCTL(0):
1268 reg = 0x0E028;
1269 break;
1270 case E1000_RDBAL(0):
1271 reg = 0x0C000;
1272 break;
1273 case E1000_RDBAH(0):
1274 reg = 0x0C004;
1275 break;
1276 case E1000_RDLEN(0):
1277 reg = 0x0C008;
1278 break;
1279 case E1000_RDH(0):
1280 reg = 0x0C010;
1281 break;
1282 case E1000_RDT(0):
1283 reg = 0x0C018;
1284 break;
1285 case E1000_RXDCTL(0):
1286 reg = 0x0C028;
1287 break;
1288 case E1000_SRRCTL(0):
1289 reg = 0x0C00C;
1290 break;
1291 default:
1292 break;
1293 }
1294
1295 return reg;
1296}
1297
1298/**
1299 * igb_reset_init_script_82575 - Inits HW defaults after reset
1129 * @hw: pointer to the HW structure 1300 * @hw: pointer to the HW structure
1130 * 1301 *
1131 * Inits recommended HW defaults after a reset when there is no EEPROM 1302 * Inits recommended HW defaults after a reset when there is no EEPROM
@@ -1134,7 +1305,7 @@ out:
1134static s32 igb_reset_init_script_82575(struct e1000_hw *hw) 1305static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1135{ 1306{
1136 if (hw->mac.type == e1000_82575) { 1307 if (hw->mac.type == e1000_82575) {
1137 hw_dbg(hw, "Running reset init script for 82575\n"); 1308 hw_dbg("Running reset init script for 82575\n");
1138 /* SerDes configuration via SERDESCTRL */ 1309 /* SerDes configuration via SERDESCTRL */
1139 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); 1310 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1140 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); 1311 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
@@ -1161,7 +1332,7 @@ static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1161} 1332}
1162 1333
1163/** 1334/**
1164 * e1000_read_mac_addr_82575 - Read device MAC address 1335 * igb_read_mac_addr_82575 - Read device MAC address
1165 * @hw: pointer to the HW structure 1336 * @hw: pointer to the HW structure
1166 **/ 1337 **/
1167static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) 1338static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
@@ -1175,7 +1346,7 @@ static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1175} 1346}
1176 1347
1177/** 1348/**
1178 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1349 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1179 * @hw: pointer to the HW structure 1350 * @hw: pointer to the HW structure
1180 * 1351 *
1181 * Clears the hardware counters by reading the counter registers. 1352 * Clears the hardware counters by reading the counter registers.
@@ -1238,11 +1409,84 @@ static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1238 temp = rd32(E1000_SCVPC); 1409 temp = rd32(E1000_SCVPC);
1239} 1410}
1240 1411
1412/**
1413 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1414 * @hw: pointer to the HW structure
1415 *
1416 * After rx enable if managability is enabled then there is likely some
1417 * bad data at the start of the fifo and possibly in the DMA fifo. This
1418 * function clears the fifos and flushes any packets that came in as rx was
1419 * being enabled.
1420 **/
1421void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1422{
1423 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1424 int i, ms_wait;
1425
1426 if (hw->mac.type != e1000_82575 ||
1427 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1428 return;
1429
1430 /* Disable all RX queues */
1431 for (i = 0; i < 4; i++) {
1432 rxdctl[i] = rd32(E1000_RXDCTL(i));
1433 wr32(E1000_RXDCTL(i),
1434 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1435 }
1436 /* Poll all queues to verify they have shut down */
1437 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1438 msleep(1);
1439 rx_enabled = 0;
1440 for (i = 0; i < 4; i++)
1441 rx_enabled |= rd32(E1000_RXDCTL(i));
1442 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1443 break;
1444 }
1445
1446 if (ms_wait == 10)
1447 hw_dbg("Queue disable timed out after 10ms\n");
1448
1449 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1450 * incoming packets are rejected. Set enable and wait 2ms so that
1451 * any packet that was coming in as RCTL.EN was set is flushed
1452 */
1453 rfctl = rd32(E1000_RFCTL);
1454 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1455
1456 rlpml = rd32(E1000_RLPML);
1457 wr32(E1000_RLPML, 0);
1458
1459 rctl = rd32(E1000_RCTL);
1460 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1461 temp_rctl |= E1000_RCTL_LPE;
1462
1463 wr32(E1000_RCTL, temp_rctl);
1464 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1465 wrfl();
1466 msleep(2);
1467
1468 /* Enable RX queues that were previously enabled and restore our
1469 * previous state
1470 */
1471 for (i = 0; i < 4; i++)
1472 wr32(E1000_RXDCTL(i), rxdctl[i]);
1473 wr32(E1000_RCTL, rctl);
1474 wrfl();
1475
1476 wr32(E1000_RLPML, rlpml);
1477 wr32(E1000_RFCTL, rfctl);
1478
1479 /* Flush receive errors generated by workaround */
1480 rd32(E1000_ROC);
1481 rd32(E1000_RNBC);
1482 rd32(E1000_MPC);
1483}
1484
1241static struct e1000_mac_operations e1000_mac_ops_82575 = { 1485static struct e1000_mac_operations e1000_mac_ops_82575 = {
1242 .reset_hw = igb_reset_hw_82575, 1486 .reset_hw = igb_reset_hw_82575,
1243 .init_hw = igb_init_hw_82575, 1487 .init_hw = igb_init_hw_82575,
1244 .check_for_link = igb_check_for_link_82575, 1488 .check_for_link = igb_check_for_link_82575,
1245 .rar_set = igb_rar_set_82575, 1489 .rar_set = igb_rar_set,
1246 .read_mac_addr = igb_read_mac_addr_82575, 1490 .read_mac_addr = igb_read_mac_addr_82575,
1247 .get_speed_and_duplex = igb_get_speed_and_duplex_copper, 1491 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1248}; 1492};
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h
index 76ea846663db..2f848e578a24 100644
--- a/drivers/net/igb/e1000_82575.h
+++ b/drivers/net/igb/e1000_82575.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel(R) Gigabit Ethernet Linux driver 3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation. 4 Copyright(c) 2007 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -28,7 +28,13 @@
28#ifndef _E1000_82575_H_ 28#ifndef _E1000_82575_H_
29#define _E1000_82575_H_ 29#define _E1000_82575_H_
30 30
31u32 igb_translate_register_82576(u32 reg);
32void igb_update_mc_addr_list_82575(struct e1000_hw*, u8*, u32, u32, u32);
33extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
34extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
35
31#define E1000_RAR_ENTRIES_82575 16 36#define E1000_RAR_ENTRIES_82575 16
37#define E1000_RAR_ENTRIES_82576 24
32 38
33/* SRRCTL bit definitions */ 39/* SRRCTL bit definitions */
34#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 40#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
@@ -56,7 +62,7 @@
56#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE 62#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
57#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE 63#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
58 64
59/* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */ 65/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
60 66
61/* Receive Descriptor - Advanced */ 67/* Receive Descriptor - Advanced */
62union e1000_adv_rx_desc { 68union e1000_adv_rx_desc {
@@ -93,6 +99,8 @@ union e1000_adv_rx_desc {
93/* RSS Hash results */ 99/* RSS Hash results */
94 100
95/* RSS Packet Types as indicated in the receive descriptor */ 101/* RSS Packet Types as indicated in the receive descriptor */
102#define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
103#define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
96 104
97/* Transmit Descriptor - Advanced */ 105/* Transmit Descriptor - Advanced */
98union e1000_adv_tx_desc { 106union e1000_adv_tx_desc {
@@ -142,9 +150,25 @@ struct e1000_adv_tx_context_desc {
142#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 150#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
143 151
144/* Direct Cache Access (DCA) definitions */ 152/* Direct Cache Access (DCA) definitions */
145 153#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
146 154#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
147 155
148#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* TX Desc writeback RO bit */ 156#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
157#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
158
159#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
160#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
161#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
162#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
163
164#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
165#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
166#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
167
168/* Additional DCA related definitions, note change in position of CPUID */
169#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
170#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
171#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
172#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
149 173
150#endif 174#endif
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index 8da9ffedc425..afdba3c9073c 100644
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel(R) Gigabit Ethernet Linux driver 3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation. 4 Copyright(c) 2007 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -90,13 +90,18 @@
90#define E1000_I2CCMD_ERROR 0x80000000 90#define E1000_I2CCMD_ERROR 0x80000000
91#define E1000_MAX_SGMII_PHY_REG_ADDR 255 91#define E1000_MAX_SGMII_PHY_REG_ADDR 255
92#define E1000_I2CCMD_PHY_TIMEOUT 200 92#define E1000_I2CCMD_PHY_TIMEOUT 200
93#define E1000_IVAR_VALID 0x80
94#define E1000_GPIE_NSICR 0x00000001
95#define E1000_GPIE_MSIX_MODE 0x00000010
96#define E1000_GPIE_EIAME 0x40000000
97#define E1000_GPIE_PBA 0x80000000
93 98
94/* Receive Decriptor bit definitions */ 99/* Receive Descriptor bit definitions */
95#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 100#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
96#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 101#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
97#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 102#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
98#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 103#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
99#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ 104#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
100#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 105#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
101#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 106#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
102#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 107#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
@@ -213,6 +218,7 @@
213/* Device Control */ 218/* Device Control */
214#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 219#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
215#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 220#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
221#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
216#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 222#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 223#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
218#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 224#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
@@ -244,6 +250,7 @@
244 */ 250 */
245 251
246#define E1000_CONNSW_ENRGSRC 0x4 252#define E1000_CONNSW_ENRGSRC 0x4
253#define E1000_PCS_CFG_PCS_EN 8
247#define E1000_PCS_LCTL_FLV_LINK_UP 1 254#define E1000_PCS_LCTL_FLV_LINK_UP 1
248#define E1000_PCS_LCTL_FSV_100 2 255#define E1000_PCS_LCTL_FSV_100 2
249#define E1000_PCS_LCTL_FSV_1000 4 256#define E1000_PCS_LCTL_FSV_1000 4
@@ -253,6 +260,7 @@
253#define E1000_PCS_LCTL_AN_ENABLE 0x10000 260#define E1000_PCS_LCTL_AN_ENABLE 0x10000
254#define E1000_PCS_LCTL_AN_RESTART 0x20000 261#define E1000_PCS_LCTL_AN_RESTART 0x20000
255#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 262#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
263#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
256 264
257#define E1000_PCS_LSTS_LINK_OK 1 265#define E1000_PCS_LSTS_LINK_OK 1
258#define E1000_PCS_LSTS_SPEED_100 2 266#define E1000_PCS_LSTS_SPEED_100 2
@@ -340,6 +348,7 @@
340#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 348#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
341 349
342/* Header split receive */ 350/* Header split receive */
351#define E1000_RFCTL_LEF 0x00040000
343 352
344/* Collision related configuration parameters */ 353/* Collision related configuration parameters */
345#define E1000_COLLISION_THRESHOLD 15 354#define E1000_COLLISION_THRESHOLD 15
@@ -359,6 +368,7 @@
359#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 368#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
360#define E1000_PBA_24K 0x0018 369#define E1000_PBA_24K 0x0018
361#define E1000_PBA_34K 0x0022 370#define E1000_PBA_34K 0x0022
371#define E1000_PBA_64K 0x0040 /* 64KB */
362 372
363#define IFS_MAX 80 373#define IFS_MAX 80
364#define IFS_MIN 40 374#define IFS_MIN 40
@@ -379,7 +389,7 @@
379#define E1000_ICR_RXO 0x00000040 /* rx overrun */ 389#define E1000_ICR_RXO 0x00000040 /* rx overrun */
380#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 390#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
381#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 391#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
382#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 392#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
383#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 393#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
384#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 394#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
385#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 395#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
@@ -443,12 +453,6 @@
443#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 453#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
444#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 454#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
445#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 455#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
446/* queue 0 Rx descriptor FIFO parity error */
447/* queue 0 Tx descriptor FIFO parity error */
448/* host arb read buffer parity error */
449/* packet buffer parity error */
450/* queue 1 Rx descriptor FIFO parity error */
451/* queue 1 Tx descriptor FIFO parity error */
452 456
453/* Extended Interrupt Mask Set */ 457/* Extended Interrupt Mask Set */
454#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 458#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
@@ -457,12 +461,6 @@
457/* Interrupt Cause Set */ 461/* Interrupt Cause Set */
458#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 462#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
459#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 463#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
460/* queue 0 Rx descriptor FIFO parity error */
461/* queue 0 Tx descriptor FIFO parity error */
462/* host arb read buffer parity error */
463/* packet buffer parity error */
464/* queue 1 Rx descriptor FIFO parity error */
465/* queue 1 Tx descriptor FIFO parity error */
466 464
467/* Extended Interrupt Cause Set */ 465/* Extended Interrupt Cause Set */
468 466
@@ -539,6 +537,7 @@
539/* PHY Control Register */ 537/* PHY Control Register */
540#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 538#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
541#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 539#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
540#define MII_CR_POWER_DOWN 0x0800 /* Power down */
542#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 541#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
543#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 542#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
544#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 543#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
@@ -567,7 +566,6 @@
567/* 1000BASE-T Control Register */ 566/* 1000BASE-T Control Register */
568#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 567#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
569#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 568#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
570 /* 0=DTE device */
571#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 569#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
572 /* 0=Configure PHY as Slave */ 570 /* 0=Configure PHY as Slave */
573#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 571#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
@@ -581,7 +579,7 @@
581/* PHY 1000 MII Register/Bit Definitions */ 579/* PHY 1000 MII Register/Bit Definitions */
582/* PHY Registers defined by IEEE */ 580/* PHY Registers defined by IEEE */
583#define PHY_CONTROL 0x00 /* Control Register */ 581#define PHY_CONTROL 0x00 /* Control Register */
584#define PHY_STATUS 0x01 /* Status Regiser */ 582#define PHY_STATUS 0x01 /* Status Register */
585#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 583#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
586#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 584#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
587#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 585#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
@@ -708,8 +706,8 @@
708/* Auto crossover enabled all speeds */ 706/* Auto crossover enabled all speeds */
709#define M88E1000_PSCR_AUTO_X_MODE 0x0060 707#define M88E1000_PSCR_AUTO_X_MODE 0x0060
710/* 708/*
711 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold 709 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
712 * 0=Normal 10BASE-T RX Threshold 710 * 0=Normal 10BASE-T Rx Threshold
713 */ 711 */
714/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ 712/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
715#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 713#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
diff --git a/drivers/net/igb/e1000_hw.h b/drivers/net/igb/e1000_hw.h
index 7b2c70a3b8cc..19fa4ee96f2e 100644
--- a/drivers/net/igb/e1000_hw.h
+++ b/drivers/net/igb/e1000_hw.h
@@ -38,6 +38,10 @@
38 38
39struct e1000_hw; 39struct e1000_hw;
40 40
41#define E1000_DEV_ID_82576 0x10C9
42#define E1000_DEV_ID_82576_FIBER 0x10E6
43#define E1000_DEV_ID_82576_SERDES 0x10E7
44#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
41#define E1000_DEV_ID_82575EB_COPPER 0x10A7 45#define E1000_DEV_ID_82575EB_COPPER 0x10A7
42#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 46#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
43#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 47#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
@@ -50,6 +54,7 @@ struct e1000_hw;
50enum e1000_mac_type { 54enum e1000_mac_type {
51 e1000_undefined = 0, 55 e1000_undefined = 0,
52 e1000_82575, 56 e1000_82575,
57 e1000_82576,
53 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 58 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
54}; 59};
55 60
@@ -410,14 +415,17 @@ struct e1000_mac_operations {
410 s32 (*check_for_link)(struct e1000_hw *); 415 s32 (*check_for_link)(struct e1000_hw *);
411 s32 (*reset_hw)(struct e1000_hw *); 416 s32 (*reset_hw)(struct e1000_hw *);
412 s32 (*init_hw)(struct e1000_hw *); 417 s32 (*init_hw)(struct e1000_hw *);
418 bool (*check_mng_mode)(struct e1000_hw *);
413 s32 (*setup_physical_interface)(struct e1000_hw *); 419 s32 (*setup_physical_interface)(struct e1000_hw *);
414 void (*rar_set)(struct e1000_hw *, u8 *, u32); 420 void (*rar_set)(struct e1000_hw *, u8 *, u32);
415 s32 (*read_mac_addr)(struct e1000_hw *); 421 s32 (*read_mac_addr)(struct e1000_hw *);
416 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); 422 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
423 void (*mta_set)(struct e1000_hw *, u32);
417}; 424};
418 425
419struct e1000_phy_operations { 426struct e1000_phy_operations {
420 s32 (*acquire_phy)(struct e1000_hw *); 427 s32 (*acquire_phy)(struct e1000_hw *);
428 s32 (*check_reset_block)(struct e1000_hw *);
421 s32 (*force_speed_duplex)(struct e1000_hw *); 429 s32 (*force_speed_duplex)(struct e1000_hw *);
422 s32 (*get_cfg_done)(struct e1000_hw *hw); 430 s32 (*get_cfg_done)(struct e1000_hw *hw);
423 s32 (*get_cable_length)(struct e1000_hw *); 431 s32 (*get_cable_length)(struct e1000_hw *);
@@ -586,14 +594,10 @@ struct e1000_hw {
586 594
587#ifdef DEBUG 595#ifdef DEBUG
588extern char *igb_get_hw_dev_name(struct e1000_hw *hw); 596extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
589#define hw_dbg(hw, format, arg...) \ 597#define hw_dbg(format, arg...) \
590 printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg) 598 printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
591#else 599#else
592static inline int __attribute__ ((format (printf, 2, 3))) 600#define hw_dbg(format, arg...)
593hw_dbg(struct e1000_hw *hw, const char *format, ...)
594{
595 return 0;
596}
597#endif 601#endif
598 602
599#endif 603#endif
diff --git a/drivers/net/igb/e1000_mac.c b/drivers/net/igb/e1000_mac.c
index 3e84a3f0c1d8..20408aa1f916 100644
--- a/drivers/net/igb/e1000_mac.c
+++ b/drivers/net/igb/e1000_mac.c
@@ -36,10 +36,9 @@
36 36
37static s32 igb_set_default_fc(struct e1000_hw *hw); 37static s32 igb_set_default_fc(struct e1000_hw *hw);
38static s32 igb_set_fc_watermarks(struct e1000_hw *hw); 38static s32 igb_set_fc_watermarks(struct e1000_hw *hw);
39static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
40 39
41/** 40/**
42 * e1000_remove_device - Free device specific structure 41 * igb_remove_device - Free device specific structure
43 * @hw: pointer to the HW structure 42 * @hw: pointer to the HW structure
44 * 43 *
45 * If a device specific structure was allocated, this function will 44 * If a device specific structure was allocated, this function will
@@ -73,7 +72,7 @@ static s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
73} 72}
74 73
75/** 74/**
76 * e1000_get_bus_info_pcie - Get PCIe bus information 75 * igb_get_bus_info_pcie - Get PCIe bus information
77 * @hw: pointer to the HW structure 76 * @hw: pointer to the HW structure
78 * 77 *
79 * Determines and stores the system bus information for a particular 78 * Determines and stores the system bus information for a particular
@@ -113,7 +112,7 @@ s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
113} 112}
114 113
115/** 114/**
116 * e1000_clear_vfta - Clear VLAN filter table 115 * igb_clear_vfta - Clear VLAN filter table
117 * @hw: pointer to the HW structure 116 * @hw: pointer to the HW structure
118 * 117 *
119 * Clears the register array which contains the VLAN filter table by 118 * Clears the register array which contains the VLAN filter table by
@@ -130,7 +129,7 @@ void igb_clear_vfta(struct e1000_hw *hw)
130} 129}
131 130
132/** 131/**
133 * e1000_write_vfta - Write value to VLAN filter table 132 * igb_write_vfta - Write value to VLAN filter table
134 * @hw: pointer to the HW structure 133 * @hw: pointer to the HW structure
135 * @offset: register offset in VLAN filter table 134 * @offset: register offset in VLAN filter table
136 * @value: register value written to VLAN filter table 135 * @value: register value written to VLAN filter table
@@ -145,7 +144,7 @@ void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
145} 144}
146 145
147/** 146/**
148 * e1000_init_rx_addrs - Initialize receive address's 147 * igb_init_rx_addrs - Initialize receive address's
149 * @hw: pointer to the HW structure 148 * @hw: pointer to the HW structure
150 * @rar_count: receive address registers 149 * @rar_count: receive address registers
151 * 150 *
@@ -158,12 +157,12 @@ void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
158 u32 i; 157 u32 i;
159 158
160 /* Setup the receive address */ 159 /* Setup the receive address */
161 hw_dbg(hw, "Programming MAC Address into RAR[0]\n"); 160 hw_dbg("Programming MAC Address into RAR[0]\n");
162 161
163 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 162 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
164 163
165 /* Zero out the other (rar_entry_count - 1) receive addresses */ 164 /* Zero out the other (rar_entry_count - 1) receive addresses */
166 hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1); 165 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
167 for (i = 1; i < rar_count; i++) { 166 for (i = 1; i < rar_count; i++) {
168 array_wr32(E1000_RA, (i << 1), 0); 167 array_wr32(E1000_RA, (i << 1), 0);
169 wrfl(); 168 wrfl();
@@ -173,7 +172,7 @@ void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
173} 172}
174 173
175/** 174/**
176 * e1000_check_alt_mac_addr - Check for alternate MAC addr 175 * igb_check_alt_mac_addr - Check for alternate MAC addr
177 * @hw: pointer to the HW structure 176 * @hw: pointer to the HW structure
178 * 177 *
179 * Checks the nvm for an alternate MAC address. An alternate MAC address 178 * Checks the nvm for an alternate MAC address. An alternate MAC address
@@ -193,7 +192,7 @@ s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
193 ret_val = hw->nvm.ops.read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, 192 ret_val = hw->nvm.ops.read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
194 &nvm_alt_mac_addr_offset); 193 &nvm_alt_mac_addr_offset);
195 if (ret_val) { 194 if (ret_val) {
196 hw_dbg(hw, "NVM Read Error\n"); 195 hw_dbg("NVM Read Error\n");
197 goto out; 196 goto out;
198 } 197 }
199 198
@@ -209,7 +208,7 @@ s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
209 offset = nvm_alt_mac_addr_offset + (i >> 1); 208 offset = nvm_alt_mac_addr_offset + (i >> 1);
210 ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data); 209 ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data);
211 if (ret_val) { 210 if (ret_val) {
212 hw_dbg(hw, "NVM Read Error\n"); 211 hw_dbg("NVM Read Error\n");
213 goto out; 212 goto out;
214 } 213 }
215 214
@@ -233,7 +232,7 @@ out:
233} 232}
234 233
235/** 234/**
236 * e1000_rar_set - Set receive address register 235 * igb_rar_set - Set receive address register
237 * @hw: pointer to the HW structure 236 * @hw: pointer to the HW structure
238 * @addr: pointer to the receive address 237 * @addr: pointer to the receive address
239 * @index: receive address array register 238 * @index: receive address array register
@@ -263,7 +262,7 @@ void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
263} 262}
264 263
265/** 264/**
266 * e1000_mta_set - Set multicast filter table address 265 * igb_mta_set - Set multicast filter table address
267 * @hw: pointer to the HW structure 266 * @hw: pointer to the HW structure
268 * @hash_value: determines the MTA register and bit to set 267 * @hash_value: determines the MTA register and bit to set
269 * 268 *
@@ -298,7 +297,7 @@ static void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
298} 297}
299 298
300/** 299/**
301 * e1000_update_mc_addr_list - Update Multicast addresses 300 * igb_update_mc_addr_list - Update Multicast addresses
302 * @hw: pointer to the HW structure 301 * @hw: pointer to the HW structure
303 * @mc_addr_list: array of multicast addresses to program 302 * @mc_addr_list: array of multicast addresses to program
304 * @mc_addr_count: number of multicast addresses to program 303 * @mc_addr_count: number of multicast addresses to program
@@ -336,7 +335,7 @@ void igb_update_mc_addr_list(struct e1000_hw *hw,
336 } 335 }
337 336
338 /* Clear the old settings from the MTA */ 337 /* Clear the old settings from the MTA */
339 hw_dbg(hw, "Clearing MTA\n"); 338 hw_dbg("Clearing MTA\n");
340 for (i = 0; i < hw->mac.mta_reg_count; i++) { 339 for (i = 0; i < hw->mac.mta_reg_count; i++) {
341 array_wr32(E1000_MTA, i, 0); 340 array_wr32(E1000_MTA, i, 0);
342 wrfl(); 341 wrfl();
@@ -345,14 +344,14 @@ void igb_update_mc_addr_list(struct e1000_hw *hw,
345 /* Load any remaining multicast addresses into the hash table. */ 344 /* Load any remaining multicast addresses into the hash table. */
346 for (; mc_addr_count > 0; mc_addr_count--) { 345 for (; mc_addr_count > 0; mc_addr_count--) {
347 hash_value = igb_hash_mc_addr(hw, mc_addr_list); 346 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
348 hw_dbg(hw, "Hash value = 0x%03X\n", hash_value); 347 hw_dbg("Hash value = 0x%03X\n", hash_value);
349 igb_mta_set(hw, hash_value); 348 igb_mta_set(hw, hash_value);
350 mc_addr_list += ETH_ALEN; 349 mc_addr_list += ETH_ALEN;
351 } 350 }
352} 351}
353 352
354/** 353/**
355 * e1000_hash_mc_addr - Generate a multicast hash value 354 * igb_hash_mc_addr - Generate a multicast hash value
356 * @hw: pointer to the HW structure 355 * @hw: pointer to the HW structure
357 * @mc_addr: pointer to a multicast address 356 * @mc_addr: pointer to a multicast address
358 * 357 *
@@ -360,7 +359,7 @@ void igb_update_mc_addr_list(struct e1000_hw *hw,
360 * the multicast filter table array address and new table value. See 359 * the multicast filter table array address and new table value. See
361 * igb_mta_set() 360 * igb_mta_set()
362 **/ 361 **/
363static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 362u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
364{ 363{
365 u32 hash_value, hash_mask; 364 u32 hash_value, hash_mask;
366 u8 bit_shift = 0; 365 u8 bit_shift = 0;
@@ -423,7 +422,7 @@ static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
423} 422}
424 423
425/** 424/**
426 * e1000_clear_hw_cntrs_base - Clear base hardware counters 425 * igb_clear_hw_cntrs_base - Clear base hardware counters
427 * @hw: pointer to the HW structure 426 * @hw: pointer to the HW structure
428 * 427 *
429 * Clears the base hardware counters by reading the counter registers. 428 * Clears the base hardware counters by reading the counter registers.
@@ -472,7 +471,7 @@ void igb_clear_hw_cntrs_base(struct e1000_hw *hw)
472} 471}
473 472
474/** 473/**
475 * e1000_check_for_copper_link - Check for link (Copper) 474 * igb_check_for_copper_link - Check for link (Copper)
476 * @hw: pointer to the HW structure 475 * @hw: pointer to the HW structure
477 * 476 *
478 * Checks to see of the link status of the hardware has changed. If a 477 * Checks to see of the link status of the hardware has changed. If a
@@ -540,14 +539,14 @@ s32 igb_check_for_copper_link(struct e1000_hw *hw)
540 */ 539 */
541 ret_val = igb_config_fc_after_link_up(hw); 540 ret_val = igb_config_fc_after_link_up(hw);
542 if (ret_val) 541 if (ret_val)
543 hw_dbg(hw, "Error configuring flow control\n"); 542 hw_dbg("Error configuring flow control\n");
544 543
545out: 544out:
546 return ret_val; 545 return ret_val;
547} 546}
548 547
549/** 548/**
550 * e1000_setup_link - Setup flow control and link settings 549 * igb_setup_link - Setup flow control and link settings
551 * @hw: pointer to the HW structure 550 * @hw: pointer to the HW structure
552 * 551 *
553 * Determines which flow control settings to use, then configures flow 552 * Determines which flow control settings to use, then configures flow
@@ -578,7 +577,7 @@ s32 igb_setup_link(struct e1000_hw *hw)
578 */ 577 */
579 hw->fc.original_type = hw->fc.type; 578 hw->fc.original_type = hw->fc.type;
580 579
581 hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type); 580 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.type);
582 581
583 /* Call the necessary media_type subroutine to configure the link. */ 582 /* Call the necessary media_type subroutine to configure the link. */
584 ret_val = hw->mac.ops.setup_physical_interface(hw); 583 ret_val = hw->mac.ops.setup_physical_interface(hw);
@@ -591,8 +590,7 @@ s32 igb_setup_link(struct e1000_hw *hw)
591 * control is disabled, because it does not hurt anything to 590 * control is disabled, because it does not hurt anything to
592 * initialize these registers. 591 * initialize these registers.
593 */ 592 */
594 hw_dbg(hw, 593 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
595 "Initializing the Flow Control address, type and timer regs\n");
596 wr32(E1000_FCT, FLOW_CONTROL_TYPE); 594 wr32(E1000_FCT, FLOW_CONTROL_TYPE);
597 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 595 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
598 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 596 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
@@ -606,7 +604,7 @@ out:
606} 604}
607 605
608/** 606/**
609 * e1000_config_collision_dist - Configure collision distance 607 * igb_config_collision_dist - Configure collision distance
610 * @hw: pointer to the HW structure 608 * @hw: pointer to the HW structure
611 * 609 *
612 * Configures the collision distance to the default value and is used 610 * Configures the collision distance to the default value and is used
@@ -627,7 +625,7 @@ void igb_config_collision_dist(struct e1000_hw *hw)
627} 625}
628 626
629/** 627/**
630 * e1000_set_fc_watermarks - Set flow control high/low watermarks 628 * igb_set_fc_watermarks - Set flow control high/low watermarks
631 * @hw: pointer to the HW structure 629 * @hw: pointer to the HW structure
632 * 630 *
633 * Sets the flow control high/low threshold (watermark) registers. If 631 * Sets the flow control high/low threshold (watermark) registers. If
@@ -665,7 +663,7 @@ static s32 igb_set_fc_watermarks(struct e1000_hw *hw)
665} 663}
666 664
667/** 665/**
668 * e1000_set_default_fc - Set flow control default values 666 * igb_set_default_fc - Set flow control default values
669 * @hw: pointer to the HW structure 667 * @hw: pointer to the HW structure
670 * 668 *
671 * Read the EEPROM for the default values for flow control and store the 669 * Read the EEPROM for the default values for flow control and store the
@@ -689,7 +687,7 @@ static s32 igb_set_default_fc(struct e1000_hw *hw)
689 &nvm_data); 687 &nvm_data);
690 688
691 if (ret_val) { 689 if (ret_val) {
692 hw_dbg(hw, "NVM Read Error\n"); 690 hw_dbg("NVM Read Error\n");
693 goto out; 691 goto out;
694 } 692 }
695 693
@@ -706,7 +704,7 @@ out:
706} 704}
707 705
708/** 706/**
709 * e1000_force_mac_fc - Force the MAC's flow control settings 707 * igb_force_mac_fc - Force the MAC's flow control settings
710 * @hw: pointer to the HW structure 708 * @hw: pointer to the HW structure
711 * 709 *
712 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 710 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
@@ -740,7 +738,7 @@ s32 igb_force_mac_fc(struct e1000_hw *hw)
740 * 3: Both Rx and TX flow control (symmetric) is enabled. 738 * 3: Both Rx and TX flow control (symmetric) is enabled.
741 * other: No other values should be possible at this point. 739 * other: No other values should be possible at this point.
742 */ 740 */
743 hw_dbg(hw, "hw->fc.type = %u\n", hw->fc.type); 741 hw_dbg("hw->fc.type = %u\n", hw->fc.type);
744 742
745 switch (hw->fc.type) { 743 switch (hw->fc.type) {
746 case e1000_fc_none: 744 case e1000_fc_none:
@@ -758,7 +756,7 @@ s32 igb_force_mac_fc(struct e1000_hw *hw)
758 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 756 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
759 break; 757 break;
760 default: 758 default:
761 hw_dbg(hw, "Flow control param set incorrectly\n"); 759 hw_dbg("Flow control param set incorrectly\n");
762 ret_val = -E1000_ERR_CONFIG; 760 ret_val = -E1000_ERR_CONFIG;
763 goto out; 761 goto out;
764 } 762 }
@@ -770,7 +768,7 @@ out:
770} 768}
771 769
772/** 770/**
773 * e1000_config_fc_after_link_up - Configures flow control after link 771 * igb_config_fc_after_link_up - Configures flow control after link
774 * @hw: pointer to the HW structure 772 * @hw: pointer to the HW structure
775 * 773 *
776 * Checks the status of auto-negotiation after link up to ensure that the 774 * Checks the status of auto-negotiation after link up to ensure that the
@@ -801,7 +799,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
801 } 799 }
802 800
803 if (ret_val) { 801 if (ret_val) {
804 hw_dbg(hw, "Error forcing flow control settings\n"); 802 hw_dbg("Error forcing flow control settings\n");
805 goto out; 803 goto out;
806 } 804 }
807 805
@@ -827,7 +825,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
827 goto out; 825 goto out;
828 826
829 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 827 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
830 hw_dbg(hw, "Copper PHY and Auto Neg " 828 hw_dbg("Copper PHY and Auto Neg "
831 "has not completed.\n"); 829 "has not completed.\n");
832 goto out; 830 goto out;
833 } 831 }
@@ -893,11 +891,11 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
893 */ 891 */
894 if (hw->fc.original_type == e1000_fc_full) { 892 if (hw->fc.original_type == e1000_fc_full) {
895 hw->fc.type = e1000_fc_full; 893 hw->fc.type = e1000_fc_full;
896 hw_dbg(hw, "Flow Control = FULL.\r\n"); 894 hw_dbg("Flow Control = FULL.\r\n");
897 } else { 895 } else {
898 hw->fc.type = e1000_fc_rx_pause; 896 hw->fc.type = e1000_fc_rx_pause;
899 hw_dbg(hw, "Flow Control = " 897 hw_dbg("Flow Control = "
900 "RX PAUSE frames only.\r\n"); 898 "RX PAUSE frames only.\r\n");
901 } 899 }
902 } 900 }
903 /* 901 /*
@@ -913,7 +911,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
913 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 911 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
914 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 912 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
915 hw->fc.type = e1000_fc_tx_pause; 913 hw->fc.type = e1000_fc_tx_pause;
916 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\r\n"); 914 hw_dbg("Flow Control = TX PAUSE frames only.\r\n");
917 } 915 }
918 /* 916 /*
919 * For transmitting PAUSE frames ONLY. 917 * For transmitting PAUSE frames ONLY.
@@ -928,7 +926,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
928 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 926 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
929 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 927 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
930 hw->fc.type = e1000_fc_rx_pause; 928 hw->fc.type = e1000_fc_rx_pause;
931 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n"); 929 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
932 } 930 }
933 /* 931 /*
934 * Per the IEEE spec, at this point flow control should be 932 * Per the IEEE spec, at this point flow control should be
@@ -955,10 +953,10 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
955 hw->fc.original_type == e1000_fc_tx_pause) || 953 hw->fc.original_type == e1000_fc_tx_pause) ||
956 hw->fc.strict_ieee) { 954 hw->fc.strict_ieee) {
957 hw->fc.type = e1000_fc_none; 955 hw->fc.type = e1000_fc_none;
958 hw_dbg(hw, "Flow Control = NONE.\r\n"); 956 hw_dbg("Flow Control = NONE.\r\n");
959 } else { 957 } else {
960 hw->fc.type = e1000_fc_rx_pause; 958 hw->fc.type = e1000_fc_rx_pause;
961 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n"); 959 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
962 } 960 }
963 961
964 /* 962 /*
@@ -968,7 +966,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
968 */ 966 */
969 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); 967 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
970 if (ret_val) { 968 if (ret_val) {
971 hw_dbg(hw, "Error getting link speed and duplex\n"); 969 hw_dbg("Error getting link speed and duplex\n");
972 goto out; 970 goto out;
973 } 971 }
974 972
@@ -981,7 +979,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
981 */ 979 */
982 ret_val = igb_force_mac_fc(hw); 980 ret_val = igb_force_mac_fc(hw);
983 if (ret_val) { 981 if (ret_val) {
984 hw_dbg(hw, "Error forcing flow control settings\n"); 982 hw_dbg("Error forcing flow control settings\n");
985 goto out; 983 goto out;
986 } 984 }
987 } 985 }
@@ -991,7 +989,7 @@ out:
991} 989}
992 990
993/** 991/**
994 * e1000_get_speed_and_duplex_copper - Retreive current speed/duplex 992 * igb_get_speed_and_duplex_copper - Retreive current speed/duplex
995 * @hw: pointer to the HW structure 993 * @hw: pointer to the HW structure
996 * @speed: stores the current speed 994 * @speed: stores the current speed
997 * @duplex: stores the current duplex 995 * @duplex: stores the current duplex
@@ -1007,28 +1005,28 @@ s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1007 status = rd32(E1000_STATUS); 1005 status = rd32(E1000_STATUS);
1008 if (status & E1000_STATUS_SPEED_1000) { 1006 if (status & E1000_STATUS_SPEED_1000) {
1009 *speed = SPEED_1000; 1007 *speed = SPEED_1000;
1010 hw_dbg(hw, "1000 Mbs, "); 1008 hw_dbg("1000 Mbs, ");
1011 } else if (status & E1000_STATUS_SPEED_100) { 1009 } else if (status & E1000_STATUS_SPEED_100) {
1012 *speed = SPEED_100; 1010 *speed = SPEED_100;
1013 hw_dbg(hw, "100 Mbs, "); 1011 hw_dbg("100 Mbs, ");
1014 } else { 1012 } else {
1015 *speed = SPEED_10; 1013 *speed = SPEED_10;
1016 hw_dbg(hw, "10 Mbs, "); 1014 hw_dbg("10 Mbs, ");
1017 } 1015 }
1018 1016
1019 if (status & E1000_STATUS_FD) { 1017 if (status & E1000_STATUS_FD) {
1020 *duplex = FULL_DUPLEX; 1018 *duplex = FULL_DUPLEX;
1021 hw_dbg(hw, "Full Duplex\n"); 1019 hw_dbg("Full Duplex\n");
1022 } else { 1020 } else {
1023 *duplex = HALF_DUPLEX; 1021 *duplex = HALF_DUPLEX;
1024 hw_dbg(hw, "Half Duplex\n"); 1022 hw_dbg("Half Duplex\n");
1025 } 1023 }
1026 1024
1027 return 0; 1025 return 0;
1028} 1026}
1029 1027
1030/** 1028/**
1031 * e1000_get_hw_semaphore - Acquire hardware semaphore 1029 * igb_get_hw_semaphore - Acquire hardware semaphore
1032 * @hw: pointer to the HW structure 1030 * @hw: pointer to the HW structure
1033 * 1031 *
1034 * Acquire the HW semaphore to access the PHY or NVM 1032 * Acquire the HW semaphore to access the PHY or NVM
@@ -1051,7 +1049,7 @@ s32 igb_get_hw_semaphore(struct e1000_hw *hw)
1051 } 1049 }
1052 1050
1053 if (i == timeout) { 1051 if (i == timeout) {
1054 hw_dbg(hw, "Driver can't access device - SMBI bit is set.\n"); 1052 hw_dbg("Driver can't access device - SMBI bit is set.\n");
1055 ret_val = -E1000_ERR_NVM; 1053 ret_val = -E1000_ERR_NVM;
1056 goto out; 1054 goto out;
1057 } 1055 }
@@ -1071,7 +1069,7 @@ s32 igb_get_hw_semaphore(struct e1000_hw *hw)
1071 if (i == timeout) { 1069 if (i == timeout) {
1072 /* Release semaphores */ 1070 /* Release semaphores */
1073 igb_put_hw_semaphore(hw); 1071 igb_put_hw_semaphore(hw);
1074 hw_dbg(hw, "Driver can't access the NVM\n"); 1072 hw_dbg("Driver can't access the NVM\n");
1075 ret_val = -E1000_ERR_NVM; 1073 ret_val = -E1000_ERR_NVM;
1076 goto out; 1074 goto out;
1077 } 1075 }
@@ -1081,7 +1079,7 @@ out:
1081} 1079}
1082 1080
1083/** 1081/**
1084 * e1000_put_hw_semaphore - Release hardware semaphore 1082 * igb_put_hw_semaphore - Release hardware semaphore
1085 * @hw: pointer to the HW structure 1083 * @hw: pointer to the HW structure
1086 * 1084 *
1087 * Release hardware semaphore used to access the PHY or NVM 1085 * Release hardware semaphore used to access the PHY or NVM
@@ -1098,7 +1096,7 @@ void igb_put_hw_semaphore(struct e1000_hw *hw)
1098} 1096}
1099 1097
1100/** 1098/**
1101 * e1000_get_auto_rd_done - Check for auto read completion 1099 * igb_get_auto_rd_done - Check for auto read completion
1102 * @hw: pointer to the HW structure 1100 * @hw: pointer to the HW structure
1103 * 1101 *
1104 * Check EEPROM for Auto Read done bit. 1102 * Check EEPROM for Auto Read done bit.
@@ -1117,7 +1115,7 @@ s32 igb_get_auto_rd_done(struct e1000_hw *hw)
1117 } 1115 }
1118 1116
1119 if (i == AUTO_READ_DONE_TIMEOUT) { 1117 if (i == AUTO_READ_DONE_TIMEOUT) {
1120 hw_dbg(hw, "Auto read by HW from NVM has not completed.\n"); 1118 hw_dbg("Auto read by HW from NVM has not completed.\n");
1121 ret_val = -E1000_ERR_RESET; 1119 ret_val = -E1000_ERR_RESET;
1122 goto out; 1120 goto out;
1123 } 1121 }
@@ -1127,7 +1125,7 @@ out:
1127} 1125}
1128 1126
1129/** 1127/**
1130 * e1000_valid_led_default - Verify a valid default LED config 1128 * igb_valid_led_default - Verify a valid default LED config
1131 * @hw: pointer to the HW structure 1129 * @hw: pointer to the HW structure
1132 * @data: pointer to the NVM (EEPROM) 1130 * @data: pointer to the NVM (EEPROM)
1133 * 1131 *
@@ -1140,7 +1138,7 @@ static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data)
1140 1138
1141 ret_val = hw->nvm.ops.read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1139 ret_val = hw->nvm.ops.read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1142 if (ret_val) { 1140 if (ret_val) {
1143 hw_dbg(hw, "NVM Read Error\n"); 1141 hw_dbg("NVM Read Error\n");
1144 goto out; 1142 goto out;
1145 } 1143 }
1146 1144
@@ -1152,7 +1150,7 @@ out:
1152} 1150}
1153 1151
1154/** 1152/**
1155 * e1000_id_led_init - 1153 * igb_id_led_init -
1156 * @hw: pointer to the HW structure 1154 * @hw: pointer to the HW structure
1157 * 1155 *
1158 **/ 1156 **/
@@ -1217,7 +1215,7 @@ out:
1217} 1215}
1218 1216
1219/** 1217/**
1220 * e1000_cleanup_led - Set LED config to default operation 1218 * igb_cleanup_led - Set LED config to default operation
1221 * @hw: pointer to the HW structure 1219 * @hw: pointer to the HW structure
1222 * 1220 *
1223 * Remove the current LED configuration and set the LED configuration 1221 * Remove the current LED configuration and set the LED configuration
@@ -1230,7 +1228,7 @@ s32 igb_cleanup_led(struct e1000_hw *hw)
1230} 1228}
1231 1229
1232/** 1230/**
1233 * e1000_blink_led - Blink LED 1231 * igb_blink_led - Blink LED
1234 * @hw: pointer to the HW structure 1232 * @hw: pointer to the HW structure
1235 * 1233 *
1236 * Blink the led's which are set to be on. 1234 * Blink the led's which are set to be on.
@@ -1263,7 +1261,7 @@ s32 igb_blink_led(struct e1000_hw *hw)
1263} 1261}
1264 1262
1265/** 1263/**
1266 * e1000_led_off - Turn LED off 1264 * igb_led_off - Turn LED off
1267 * @hw: pointer to the HW structure 1265 * @hw: pointer to the HW structure
1268 * 1266 *
1269 * Turn LED off. 1267 * Turn LED off.
@@ -1290,7 +1288,7 @@ s32 igb_led_off(struct e1000_hw *hw)
1290} 1288}
1291 1289
1292/** 1290/**
1293 * e1000_disable_pcie_master - Disables PCI-express master access 1291 * igb_disable_pcie_master - Disables PCI-express master access
1294 * @hw: pointer to the HW structure 1292 * @hw: pointer to the HW structure
1295 * 1293 *
1296 * Returns 0 (0) if successful, else returns -10 1294 * Returns 0 (0) if successful, else returns -10
@@ -1322,7 +1320,7 @@ s32 igb_disable_pcie_master(struct e1000_hw *hw)
1322 } 1320 }
1323 1321
1324 if (!timeout) { 1322 if (!timeout) {
1325 hw_dbg(hw, "Master requests are pending.\n"); 1323 hw_dbg("Master requests are pending.\n");
1326 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 1324 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
1327 goto out; 1325 goto out;
1328 } 1326 }
@@ -1332,7 +1330,7 @@ out:
1332} 1330}
1333 1331
1334/** 1332/**
1335 * e1000_reset_adaptive - Reset Adaptive Interframe Spacing 1333 * igb_reset_adaptive - Reset Adaptive Interframe Spacing
1336 * @hw: pointer to the HW structure 1334 * @hw: pointer to the HW structure
1337 * 1335 *
1338 * Reset the Adaptive Interframe Spacing throttle to default values. 1336 * Reset the Adaptive Interframe Spacing throttle to default values.
@@ -1342,7 +1340,7 @@ void igb_reset_adaptive(struct e1000_hw *hw)
1342 struct e1000_mac_info *mac = &hw->mac; 1340 struct e1000_mac_info *mac = &hw->mac;
1343 1341
1344 if (!mac->adaptive_ifs) { 1342 if (!mac->adaptive_ifs) {
1345 hw_dbg(hw, "Not in Adaptive IFS mode!\n"); 1343 hw_dbg("Not in Adaptive IFS mode!\n");
1346 goto out; 1344 goto out;
1347 } 1345 }
1348 1346
@@ -1361,7 +1359,7 @@ out:
1361} 1359}
1362 1360
1363/** 1361/**
1364 * e1000_update_adaptive - Update Adaptive Interframe Spacing 1362 * igb_update_adaptive - Update Adaptive Interframe Spacing
1365 * @hw: pointer to the HW structure 1363 * @hw: pointer to the HW structure
1366 * 1364 *
1367 * Update the Adaptive Interframe Spacing Throttle value based on the 1365 * Update the Adaptive Interframe Spacing Throttle value based on the
@@ -1372,7 +1370,7 @@ void igb_update_adaptive(struct e1000_hw *hw)
1372 struct e1000_mac_info *mac = &hw->mac; 1370 struct e1000_mac_info *mac = &hw->mac;
1373 1371
1374 if (!mac->adaptive_ifs) { 1372 if (!mac->adaptive_ifs) {
1375 hw_dbg(hw, "Not in Adaptive IFS mode!\n"); 1373 hw_dbg("Not in Adaptive IFS mode!\n");
1376 goto out; 1374 goto out;
1377 } 1375 }
1378 1376
@@ -1402,7 +1400,7 @@ out:
1402} 1400}
1403 1401
1404/** 1402/**
1405 * e1000_validate_mdi_setting - Verify MDI/MDIx settings 1403 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1406 * @hw: pointer to the HW structure 1404 * @hw: pointer to the HW structure
1407 * 1405 *
1408 * Verify that when not using auto-negotitation that MDI/MDIx is correctly 1406 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
@@ -1413,7 +1411,7 @@ s32 igb_validate_mdi_setting(struct e1000_hw *hw)
1413 s32 ret_val = 0; 1411 s32 ret_val = 0;
1414 1412
1415 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 1413 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
1416 hw_dbg(hw, "Invalid MDI setting detected\n"); 1414 hw_dbg("Invalid MDI setting detected\n");
1417 hw->phy.mdix = 1; 1415 hw->phy.mdix = 1;
1418 ret_val = -E1000_ERR_CONFIG; 1416 ret_val = -E1000_ERR_CONFIG;
1419 goto out; 1417 goto out;
@@ -1424,7 +1422,7 @@ out:
1424} 1422}
1425 1423
1426/** 1424/**
1427 * e1000_write_8bit_ctrl_reg - Write a 8bit CTRL register 1425 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1428 * @hw: pointer to the HW structure 1426 * @hw: pointer to the HW structure
1429 * @reg: 32bit register offset such as E1000_SCTL 1427 * @reg: 32bit register offset such as E1000_SCTL
1430 * @offset: register offset to write to 1428 * @offset: register offset to write to
@@ -1452,7 +1450,7 @@ s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
1452 break; 1450 break;
1453 } 1451 }
1454 if (!(regvalue & E1000_GEN_CTL_READY)) { 1452 if (!(regvalue & E1000_GEN_CTL_READY)) {
1455 hw_dbg(hw, "Reg %08x did not indicate ready\n", reg); 1453 hw_dbg("Reg %08x did not indicate ready\n", reg);
1456 ret_val = -E1000_ERR_PHY; 1454 ret_val = -E1000_ERR_PHY;
1457 goto out; 1455 goto out;
1458 } 1456 }
@@ -1462,7 +1460,7 @@ out:
1462} 1460}
1463 1461
1464/** 1462/**
1465 * e1000_enable_mng_pass_thru - Enable processing of ARP's 1463 * igb_enable_mng_pass_thru - Enable processing of ARP's
1466 * @hw: pointer to the HW structure 1464 * @hw: pointer to the HW structure
1467 * 1465 *
1468 * Verifies the hardware needs to allow ARPs to be processed by the host. 1466 * Verifies the hardware needs to allow ARPs to be processed by the host.
diff --git a/drivers/net/igb/e1000_mac.h b/drivers/net/igb/e1000_mac.h
index 326b6592307b..dc2f8cce15e7 100644
--- a/drivers/net/igb/e1000_mac.h
+++ b/drivers/net/igb/e1000_mac.h
@@ -94,5 +94,6 @@ enum e1000_mng_mode {
94#define E1000_HICR_C 0x02 94#define E1000_HICR_C 0x02
95 95
96extern void e1000_init_function_pointers_82575(struct e1000_hw *hw); 96extern void e1000_init_function_pointers_82575(struct e1000_hw *hw);
97extern u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
97 98
98#endif 99#endif
diff --git a/drivers/net/igb/e1000_nvm.c b/drivers/net/igb/e1000_nvm.c
index 2897106fee92..a84e4e429fa7 100644
--- a/drivers/net/igb/e1000_nvm.c
+++ b/drivers/net/igb/e1000_nvm.c
@@ -32,7 +32,7 @@
32#include "e1000_nvm.h" 32#include "e1000_nvm.h"
33 33
34/** 34/**
35 * e1000_raise_eec_clk - Raise EEPROM clock 35 * igb_raise_eec_clk - Raise EEPROM clock
36 * @hw: pointer to the HW structure 36 * @hw: pointer to the HW structure
37 * @eecd: pointer to the EEPROM 37 * @eecd: pointer to the EEPROM
38 * 38 *
@@ -47,7 +47,7 @@ static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
47} 47}
48 48
49/** 49/**
50 * e1000_lower_eec_clk - Lower EEPROM clock 50 * igb_lower_eec_clk - Lower EEPROM clock
51 * @hw: pointer to the HW structure 51 * @hw: pointer to the HW structure
52 * @eecd: pointer to the EEPROM 52 * @eecd: pointer to the EEPROM
53 * 53 *
@@ -62,7 +62,7 @@ static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
62} 62}
63 63
64/** 64/**
65 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 65 * igb_shift_out_eec_bits - Shift data bits our to the EEPROM
66 * @hw: pointer to the HW structure 66 * @hw: pointer to the HW structure
67 * @data: data to send to the EEPROM 67 * @data: data to send to the EEPROM
68 * @count: number of bits to shift out 68 * @count: number of bits to shift out
@@ -105,7 +105,7 @@ static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
105} 105}
106 106
107/** 107/**
108 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 108 * igb_shift_in_eec_bits - Shift data bits in from the EEPROM
109 * @hw: pointer to the HW structure 109 * @hw: pointer to the HW structure
110 * @count: number of bits to shift in 110 * @count: number of bits to shift in
111 * 111 *
@@ -143,7 +143,7 @@ static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
143} 143}
144 144
145/** 145/**
146 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 146 * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
147 * @hw: pointer to the HW structure 147 * @hw: pointer to the HW structure
148 * @ee_reg: EEPROM flag for polling 148 * @ee_reg: EEPROM flag for polling
149 * 149 *
@@ -174,7 +174,7 @@ static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
174} 174}
175 175
176/** 176/**
177 * e1000_acquire_nvm - Generic request for access to EEPROM 177 * igb_acquire_nvm - Generic request for access to EEPROM
178 * @hw: pointer to the HW structure 178 * @hw: pointer to the HW structure
179 * 179 *
180 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 180 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
@@ -202,7 +202,7 @@ s32 igb_acquire_nvm(struct e1000_hw *hw)
202 if (!timeout) { 202 if (!timeout) {
203 eecd &= ~E1000_EECD_REQ; 203 eecd &= ~E1000_EECD_REQ;
204 wr32(E1000_EECD, eecd); 204 wr32(E1000_EECD, eecd);
205 hw_dbg(hw, "Could not acquire NVM grant\n"); 205 hw_dbg("Could not acquire NVM grant\n");
206 ret_val = -E1000_ERR_NVM; 206 ret_val = -E1000_ERR_NVM;
207 } 207 }
208 208
@@ -210,7 +210,7 @@ s32 igb_acquire_nvm(struct e1000_hw *hw)
210} 210}
211 211
212/** 212/**
213 * e1000_standby_nvm - Return EEPROM to standby state 213 * igb_standby_nvm - Return EEPROM to standby state
214 * @hw: pointer to the HW structure 214 * @hw: pointer to the HW structure
215 * 215 *
216 * Return the EEPROM to a standby state. 216 * Return the EEPROM to a standby state.
@@ -273,7 +273,7 @@ static void e1000_stop_nvm(struct e1000_hw *hw)
273} 273}
274 274
275/** 275/**
276 * e1000_release_nvm - Release exclusive access to EEPROM 276 * igb_release_nvm - Release exclusive access to EEPROM
277 * @hw: pointer to the HW structure 277 * @hw: pointer to the HW structure
278 * 278 *
279 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 279 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
@@ -290,7 +290,7 @@ void igb_release_nvm(struct e1000_hw *hw)
290} 290}
291 291
292/** 292/**
293 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 293 * igb_ready_nvm_eeprom - Prepares EEPROM for read/write
294 * @hw: pointer to the HW structure 294 * @hw: pointer to the HW structure
295 * 295 *
296 * Setups the EEPROM for reading and writing. 296 * Setups the EEPROM for reading and writing.
@@ -337,7 +337,7 @@ static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
337 } 337 }
338 338
339 if (!timeout) { 339 if (!timeout) {
340 hw_dbg(hw, "SPI NVM Status error\n"); 340 hw_dbg("SPI NVM Status error\n");
341 ret_val = -E1000_ERR_NVM; 341 ret_val = -E1000_ERR_NVM;
342 goto out; 342 goto out;
343 } 343 }
@@ -348,7 +348,7 @@ out:
348} 348}
349 349
350/** 350/**
351 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 351 * igb_read_nvm_eerd - Reads EEPROM using EERD register
352 * @hw: pointer to the HW structure 352 * @hw: pointer to the HW structure
353 * @offset: offset of word in the EEPROM to read 353 * @offset: offset of word in the EEPROM to read
354 * @words: number of words to read 354 * @words: number of words to read
@@ -368,7 +368,7 @@ s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
368 */ 368 */
369 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 369 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
370 (words == 0)) { 370 (words == 0)) {
371 hw_dbg(hw, "nvm parameter(s) out of bounds\n"); 371 hw_dbg("nvm parameter(s) out of bounds\n");
372 ret_val = -E1000_ERR_NVM; 372 ret_val = -E1000_ERR_NVM;
373 goto out; 373 goto out;
374 } 374 }
@@ -391,7 +391,7 @@ out:
391} 391}
392 392
393/** 393/**
394 * e1000_write_nvm_spi - Write to EEPROM using SPI 394 * igb_write_nvm_spi - Write to EEPROM using SPI
395 * @hw: pointer to the HW structure 395 * @hw: pointer to the HW structure
396 * @offset: offset within the EEPROM to be written to 396 * @offset: offset within the EEPROM to be written to
397 * @words: number of words to write 397 * @words: number of words to write
@@ -414,7 +414,7 @@ s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
414 */ 414 */
415 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 415 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
416 (words == 0)) { 416 (words == 0)) {
417 hw_dbg(hw, "nvm parameter(s) out of bounds\n"); 417 hw_dbg("nvm parameter(s) out of bounds\n");
418 ret_val = -E1000_ERR_NVM; 418 ret_val = -E1000_ERR_NVM;
419 goto out; 419 goto out;
420 } 420 }
@@ -475,7 +475,7 @@ out:
475} 475}
476 476
477/** 477/**
478 * e1000_read_part_num - Read device part number 478 * igb_read_part_num - Read device part number
479 * @hw: pointer to the HW structure 479 * @hw: pointer to the HW structure
480 * @part_num: pointer to device part number 480 * @part_num: pointer to device part number
481 * 481 *
@@ -489,14 +489,14 @@ s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num)
489 489
490 ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 490 ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
491 if (ret_val) { 491 if (ret_val) {
492 hw_dbg(hw, "NVM Read Error\n"); 492 hw_dbg("NVM Read Error\n");
493 goto out; 493 goto out;
494 } 494 }
495 *part_num = (u32)(nvm_data << 16); 495 *part_num = (u32)(nvm_data << 16);
496 496
497 ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); 497 ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
498 if (ret_val) { 498 if (ret_val) {
499 hw_dbg(hw, "NVM Read Error\n"); 499 hw_dbg("NVM Read Error\n");
500 goto out; 500 goto out;
501 } 501 }
502 *part_num |= nvm_data; 502 *part_num |= nvm_data;
@@ -506,7 +506,7 @@ out:
506} 506}
507 507
508/** 508/**
509 * e1000_read_mac_addr - Read device MAC address 509 * igb_read_mac_addr - Read device MAC address
510 * @hw: pointer to the HW structure 510 * @hw: pointer to the HW structure
511 * 511 *
512 * Reads the device MAC address from the EEPROM and stores the value. 512 * Reads the device MAC address from the EEPROM and stores the value.
@@ -522,7 +522,7 @@ s32 igb_read_mac_addr(struct e1000_hw *hw)
522 offset = i >> 1; 522 offset = i >> 1;
523 ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data); 523 ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data);
524 if (ret_val) { 524 if (ret_val) {
525 hw_dbg(hw, "NVM Read Error\n"); 525 hw_dbg("NVM Read Error\n");
526 goto out; 526 goto out;
527 } 527 }
528 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 528 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
@@ -541,7 +541,7 @@ out:
541} 541}
542 542
543/** 543/**
544 * e1000_validate_nvm_checksum - Validate EEPROM checksum 544 * igb_validate_nvm_checksum - Validate EEPROM checksum
545 * @hw: pointer to the HW structure 545 * @hw: pointer to the HW structure
546 * 546 *
547 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 547 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
@@ -556,14 +556,14 @@ s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
556 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 556 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
557 ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data); 557 ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data);
558 if (ret_val) { 558 if (ret_val) {
559 hw_dbg(hw, "NVM Read Error\n"); 559 hw_dbg("NVM Read Error\n");
560 goto out; 560 goto out;
561 } 561 }
562 checksum += nvm_data; 562 checksum += nvm_data;
563 } 563 }
564 564
565 if (checksum != (u16) NVM_SUM) { 565 if (checksum != (u16) NVM_SUM) {
566 hw_dbg(hw, "NVM Checksum Invalid\n"); 566 hw_dbg("NVM Checksum Invalid\n");
567 ret_val = -E1000_ERR_NVM; 567 ret_val = -E1000_ERR_NVM;
568 goto out; 568 goto out;
569 } 569 }
@@ -573,7 +573,7 @@ out:
573} 573}
574 574
575/** 575/**
576 * e1000_update_nvm_checksum - Update EEPROM checksum 576 * igb_update_nvm_checksum - Update EEPROM checksum
577 * @hw: pointer to the HW structure 577 * @hw: pointer to the HW structure
578 * 578 *
579 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 579 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
@@ -589,7 +589,7 @@ s32 igb_update_nvm_checksum(struct e1000_hw *hw)
589 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 589 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
590 ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data); 590 ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data);
591 if (ret_val) { 591 if (ret_val) {
592 hw_dbg(hw, "NVM Read Error while updating checksum.\n"); 592 hw_dbg("NVM Read Error while updating checksum.\n");
593 goto out; 593 goto out;
594 } 594 }
595 checksum += nvm_data; 595 checksum += nvm_data;
@@ -597,7 +597,7 @@ s32 igb_update_nvm_checksum(struct e1000_hw *hw)
597 checksum = (u16) NVM_SUM - checksum; 597 checksum = (u16) NVM_SUM - checksum;
598 ret_val = hw->nvm.ops.write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); 598 ret_val = hw->nvm.ops.write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
599 if (ret_val) 599 if (ret_val)
600 hw_dbg(hw, "NVM Write Error while updating checksum.\n"); 600 hw_dbg("NVM Write Error while updating checksum.\n");
601 601
602out: 602out:
603 return ret_val; 603 return ret_val;
diff --git a/drivers/net/igb/e1000_phy.c b/drivers/net/igb/e1000_phy.c
index 08a86b107229..17fddb91c9f5 100644
--- a/drivers/net/igb/e1000_phy.c
+++ b/drivers/net/igb/e1000_phy.c
@@ -61,7 +61,7 @@ static const u16 e1000_igp_2_cable_length_table[] =
61 sizeof(e1000_igp_2_cable_length_table[0])) 61 sizeof(e1000_igp_2_cable_length_table[0]))
62 62
63/** 63/**
64 * e1000_check_reset_block - Check if PHY reset is blocked 64 * igb_check_reset_block - Check if PHY reset is blocked
65 * @hw: pointer to the HW structure 65 * @hw: pointer to the HW structure
66 * 66 *
67 * Read the PHY management control register and check whether a PHY reset 67 * Read the PHY management control register and check whether a PHY reset
@@ -79,7 +79,7 @@ s32 igb_check_reset_block(struct e1000_hw *hw)
79} 79}
80 80
81/** 81/**
82 * e1000_get_phy_id - Retrieve the PHY ID and revision 82 * igb_get_phy_id - Retrieve the PHY ID and revision
83 * @hw: pointer to the HW structure 83 * @hw: pointer to the HW structure
84 * 84 *
85 * Reads the PHY registers and stores the PHY ID and possibly the PHY 85 * Reads the PHY registers and stores the PHY ID and possibly the PHY
@@ -109,7 +109,7 @@ out:
109} 109}
110 110
111/** 111/**
112 * e1000_phy_reset_dsp - Reset PHY DSP 112 * igb_phy_reset_dsp - Reset PHY DSP
113 * @hw: pointer to the HW structure 113 * @hw: pointer to the HW structure
114 * 114 *
115 * Reset the digital signal processor. 115 * Reset the digital signal processor.
@@ -129,7 +129,7 @@ out:
129} 129}
130 130
131/** 131/**
132 * e1000_read_phy_reg_mdic - Read MDI control register 132 * igb_read_phy_reg_mdic - Read MDI control register
133 * @hw: pointer to the HW structure 133 * @hw: pointer to the HW structure
134 * @offset: register offset to be read 134 * @offset: register offset to be read
135 * @data: pointer to the read data 135 * @data: pointer to the read data
@@ -144,7 +144,7 @@ static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
144 s32 ret_val = 0; 144 s32 ret_val = 0;
145 145
146 if (offset > MAX_PHY_REG_ADDRESS) { 146 if (offset > MAX_PHY_REG_ADDRESS) {
147 hw_dbg(hw, "PHY Address %d is out of range\n", offset); 147 hw_dbg("PHY Address %d is out of range\n", offset);
148 ret_val = -E1000_ERR_PARAM; 148 ret_val = -E1000_ERR_PARAM;
149 goto out; 149 goto out;
150 } 150 }
@@ -172,12 +172,12 @@ static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
172 break; 172 break;
173 } 173 }
174 if (!(mdic & E1000_MDIC_READY)) { 174 if (!(mdic & E1000_MDIC_READY)) {
175 hw_dbg(hw, "MDI Read did not complete\n"); 175 hw_dbg("MDI Read did not complete\n");
176 ret_val = -E1000_ERR_PHY; 176 ret_val = -E1000_ERR_PHY;
177 goto out; 177 goto out;
178 } 178 }
179 if (mdic & E1000_MDIC_ERROR) { 179 if (mdic & E1000_MDIC_ERROR) {
180 hw_dbg(hw, "MDI Error\n"); 180 hw_dbg("MDI Error\n");
181 ret_val = -E1000_ERR_PHY; 181 ret_val = -E1000_ERR_PHY;
182 goto out; 182 goto out;
183 } 183 }
@@ -188,7 +188,7 @@ out:
188} 188}
189 189
190/** 190/**
191 * e1000_write_phy_reg_mdic - Write MDI control register 191 * igb_write_phy_reg_mdic - Write MDI control register
192 * @hw: pointer to the HW structure 192 * @hw: pointer to the HW structure
193 * @offset: register offset to write to 193 * @offset: register offset to write to
194 * @data: data to write to register at offset 194 * @data: data to write to register at offset
@@ -202,7 +202,7 @@ static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
202 s32 ret_val = 0; 202 s32 ret_val = 0;
203 203
204 if (offset > MAX_PHY_REG_ADDRESS) { 204 if (offset > MAX_PHY_REG_ADDRESS) {
205 hw_dbg(hw, "PHY Address %d is out of range\n", offset); 205 hw_dbg("PHY Address %d is out of range\n", offset);
206 ret_val = -E1000_ERR_PARAM; 206 ret_val = -E1000_ERR_PARAM;
207 goto out; 207 goto out;
208 } 208 }
@@ -231,12 +231,12 @@ static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
231 break; 231 break;
232 } 232 }
233 if (!(mdic & E1000_MDIC_READY)) { 233 if (!(mdic & E1000_MDIC_READY)) {
234 hw_dbg(hw, "MDI Write did not complete\n"); 234 hw_dbg("MDI Write did not complete\n");
235 ret_val = -E1000_ERR_PHY; 235 ret_val = -E1000_ERR_PHY;
236 goto out; 236 goto out;
237 } 237 }
238 if (mdic & E1000_MDIC_ERROR) { 238 if (mdic & E1000_MDIC_ERROR) {
239 hw_dbg(hw, "MDI Error\n"); 239 hw_dbg("MDI Error\n");
240 ret_val = -E1000_ERR_PHY; 240 ret_val = -E1000_ERR_PHY;
241 goto out; 241 goto out;
242 } 242 }
@@ -246,7 +246,7 @@ out:
246} 246}
247 247
248/** 248/**
249 * e1000_read_phy_reg_igp - Read igp PHY register 249 * igb_read_phy_reg_igp - Read igp PHY register
250 * @hw: pointer to the HW structure 250 * @hw: pointer to the HW structure
251 * @offset: register offset to be read 251 * @offset: register offset to be read
252 * @data: pointer to the read data 252 * @data: pointer to the read data
@@ -284,7 +284,7 @@ out:
284} 284}
285 285
286/** 286/**
287 * e1000_write_phy_reg_igp - Write igp PHY register 287 * igb_write_phy_reg_igp - Write igp PHY register
288 * @hw: pointer to the HW structure 288 * @hw: pointer to the HW structure
289 * @offset: register offset to write to 289 * @offset: register offset to write to
290 * @data: data to write at register offset 290 * @data: data to write at register offset
@@ -321,7 +321,7 @@ out:
321} 321}
322 322
323/** 323/**
324 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 324 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
325 * @hw: pointer to the HW structure 325 * @hw: pointer to the HW structure
326 * 326 *
327 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 327 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
@@ -423,7 +423,7 @@ s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
423 /* Commit the changes. */ 423 /* Commit the changes. */
424 ret_val = igb_phy_sw_reset(hw); 424 ret_val = igb_phy_sw_reset(hw);
425 if (ret_val) { 425 if (ret_val) {
426 hw_dbg(hw, "Error committing the PHY changes\n"); 426 hw_dbg("Error committing the PHY changes\n");
427 goto out; 427 goto out;
428 } 428 }
429 429
@@ -432,7 +432,7 @@ out:
432} 432}
433 433
434/** 434/**
435 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 435 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
436 * @hw: pointer to the HW structure 436 * @hw: pointer to the HW structure
437 * 437 *
438 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 438 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
@@ -451,7 +451,7 @@ s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
451 451
452 ret_val = hw->phy.ops.reset_phy(hw); 452 ret_val = hw->phy.ops.reset_phy(hw);
453 if (ret_val) { 453 if (ret_val) {
454 hw_dbg(hw, "Error resetting the PHY.\n"); 454 hw_dbg("Error resetting the PHY.\n");
455 goto out; 455 goto out;
456 } 456 }
457 457
@@ -467,7 +467,7 @@ s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
467 if (hw->phy.ops.set_d3_lplu_state) 467 if (hw->phy.ops.set_d3_lplu_state)
468 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); 468 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
469 if (ret_val) { 469 if (ret_val) {
470 hw_dbg(hw, "Error Disabling LPLU D3\n"); 470 hw_dbg("Error Disabling LPLU D3\n");
471 goto out; 471 goto out;
472 } 472 }
473 } 473 }
@@ -475,7 +475,7 @@ s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
475 /* disable lplu d0 during driver init */ 475 /* disable lplu d0 during driver init */
476 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); 476 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
477 if (ret_val) { 477 if (ret_val) {
478 hw_dbg(hw, "Error Disabling LPLU D0\n"); 478 hw_dbg("Error Disabling LPLU D0\n");
479 goto out; 479 goto out;
480 } 480 }
481 /* Configure mdi-mdix settings */ 481 /* Configure mdi-mdix settings */
@@ -570,7 +570,7 @@ out:
570} 570}
571 571
572/** 572/**
573 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 573 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
574 * @hw: pointer to the HW structure 574 * @hw: pointer to the HW structure
575 * 575 *
576 * Performs initial bounds checking on autoneg advertisement parameter, then 576 * Performs initial bounds checking on autoneg advertisement parameter, then
@@ -597,13 +597,13 @@ s32 igb_copper_link_autoneg(struct e1000_hw *hw)
597 if (phy->autoneg_advertised == 0) 597 if (phy->autoneg_advertised == 0)
598 phy->autoneg_advertised = phy->autoneg_mask; 598 phy->autoneg_advertised = phy->autoneg_mask;
599 599
600 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n"); 600 hw_dbg("Reconfiguring auto-neg advertisement params\n");
601 ret_val = igb_phy_setup_autoneg(hw); 601 ret_val = igb_phy_setup_autoneg(hw);
602 if (ret_val) { 602 if (ret_val) {
603 hw_dbg(hw, "Error Setting up Auto-Negotiation\n"); 603 hw_dbg("Error Setting up Auto-Negotiation\n");
604 goto out; 604 goto out;
605 } 605 }
606 hw_dbg(hw, "Restarting Auto-Neg\n"); 606 hw_dbg("Restarting Auto-Neg\n");
607 607
608 /* 608 /*
609 * Restart auto-negotiation by setting the Auto Neg Enable bit and 609 * Restart auto-negotiation by setting the Auto Neg Enable bit and
@@ -625,8 +625,8 @@ s32 igb_copper_link_autoneg(struct e1000_hw *hw)
625 if (phy->autoneg_wait_to_complete) { 625 if (phy->autoneg_wait_to_complete) {
626 ret_val = igb_wait_autoneg(hw); 626 ret_val = igb_wait_autoneg(hw);
627 if (ret_val) { 627 if (ret_val) {
628 hw_dbg(hw, "Error while waiting for " 628 hw_dbg("Error while waiting for "
629 "autoneg to complete\n"); 629 "autoneg to complete\n");
630 goto out; 630 goto out;
631 } 631 }
632 } 632 }
@@ -638,7 +638,7 @@ out:
638} 638}
639 639
640/** 640/**
641 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 641 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
642 * @hw: pointer to the HW structure 642 * @hw: pointer to the HW structure
643 * 643 *
644 * Reads the MII auto-neg advertisement register and/or the 1000T control 644 * Reads the MII auto-neg advertisement register and/or the 1000T control
@@ -689,39 +689,39 @@ static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
689 NWAY_AR_10T_HD_CAPS); 689 NWAY_AR_10T_HD_CAPS);
690 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 690 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
691 691
692 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised); 692 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
693 693
694 /* Do we want to advertise 10 Mb Half Duplex? */ 694 /* Do we want to advertise 10 Mb Half Duplex? */
695 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 695 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
696 hw_dbg(hw, "Advertise 10mb Half duplex\n"); 696 hw_dbg("Advertise 10mb Half duplex\n");
697 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 697 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
698 } 698 }
699 699
700 /* Do we want to advertise 10 Mb Full Duplex? */ 700 /* Do we want to advertise 10 Mb Full Duplex? */
701 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 701 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
702 hw_dbg(hw, "Advertise 10mb Full duplex\n"); 702 hw_dbg("Advertise 10mb Full duplex\n");
703 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 703 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
704 } 704 }
705 705
706 /* Do we want to advertise 100 Mb Half Duplex? */ 706 /* Do we want to advertise 100 Mb Half Duplex? */
707 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 707 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
708 hw_dbg(hw, "Advertise 100mb Half duplex\n"); 708 hw_dbg("Advertise 100mb Half duplex\n");
709 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 709 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
710 } 710 }
711 711
712 /* Do we want to advertise 100 Mb Full Duplex? */ 712 /* Do we want to advertise 100 Mb Full Duplex? */
713 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 713 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
714 hw_dbg(hw, "Advertise 100mb Full duplex\n"); 714 hw_dbg("Advertise 100mb Full duplex\n");
715 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 715 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
716 } 716 }
717 717
718 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 718 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
719 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 719 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
720 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n"); 720 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
721 721
722 /* Do we want to advertise 1000 Mb Full Duplex? */ 722 /* Do we want to advertise 1000 Mb Full Duplex? */
723 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 723 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
724 hw_dbg(hw, "Advertise 1000mb Full duplex\n"); 724 hw_dbg("Advertise 1000mb Full duplex\n");
725 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 725 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
726 } 726 }
727 727
@@ -780,7 +780,7 @@ static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
780 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 780 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
781 break; 781 break;
782 default: 782 default:
783 hw_dbg(hw, "Flow control param set incorrectly\n"); 783 hw_dbg("Flow control param set incorrectly\n");
784 ret_val = -E1000_ERR_CONFIG; 784 ret_val = -E1000_ERR_CONFIG;
785 goto out; 785 goto out;
786 } 786 }
@@ -790,7 +790,7 @@ static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
790 if (ret_val) 790 if (ret_val)
791 goto out; 791 goto out;
792 792
793 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 793 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
794 794
795 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 795 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
796 ret_val = hw->phy.ops.write_phy_reg(hw, 796 ret_val = hw->phy.ops.write_phy_reg(hw,
@@ -805,7 +805,7 @@ out:
805} 805}
806 806
807/** 807/**
808 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 808 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
809 * @hw: pointer to the HW structure 809 * @hw: pointer to the HW structure
810 * 810 *
811 * Calls the PHY setup function to force speed and duplex. Clears the 811 * Calls the PHY setup function to force speed and duplex. Clears the
@@ -846,13 +846,12 @@ s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
846 if (ret_val) 846 if (ret_val)
847 goto out; 847 goto out;
848 848
849 hw_dbg(hw, "IGP PSCR: %X\n", phy_data); 849 hw_dbg("IGP PSCR: %X\n", phy_data);
850 850
851 udelay(1); 851 udelay(1);
852 852
853 if (phy->autoneg_wait_to_complete) { 853 if (phy->autoneg_wait_to_complete) {
854 hw_dbg(hw, 854 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
855 "Waiting for forced speed/duplex link on IGP phy.\n");
856 855
857 ret_val = igb_phy_has_link(hw, 856 ret_val = igb_phy_has_link(hw,
858 PHY_FORCE_LIMIT, 857 PHY_FORCE_LIMIT,
@@ -862,7 +861,7 @@ s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
862 goto out; 861 goto out;
863 862
864 if (!link) 863 if (!link)
865 hw_dbg(hw, "Link taking longer than expected.\n"); 864 hw_dbg("Link taking longer than expected.\n");
866 865
867 /* Try once more */ 866 /* Try once more */
868 ret_val = igb_phy_has_link(hw, 867 ret_val = igb_phy_has_link(hw,
@@ -878,7 +877,7 @@ out:
878} 877}
879 878
880/** 879/**
881 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 880 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
882 * @hw: pointer to the HW structure 881 * @hw: pointer to the HW structure
883 * 882 *
884 * Calls the PHY setup function to force speed and duplex. Clears the 883 * Calls the PHY setup function to force speed and duplex. Clears the
@@ -909,7 +908,7 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
909 if (ret_val) 908 if (ret_val)
910 goto out; 909 goto out;
911 910
912 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data); 911 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
913 912
914 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data); 913 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
915 if (ret_val) 914 if (ret_val)
@@ -927,8 +926,7 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
927 udelay(1); 926 udelay(1);
928 927
929 if (phy->autoneg_wait_to_complete) { 928 if (phy->autoneg_wait_to_complete) {
930 hw_dbg(hw, 929 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
931 "Waiting for forced speed/duplex link on M88 phy.\n");
932 930
933 ret_val = igb_phy_has_link(hw, 931 ret_val = igb_phy_has_link(hw,
934 PHY_FORCE_LIMIT, 932 PHY_FORCE_LIMIT,
@@ -993,7 +991,7 @@ out:
993} 991}
994 992
995/** 993/**
996 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 994 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
997 * @hw: pointer to the HW structure 995 * @hw: pointer to the HW structure
998 * @phy_ctrl: pointer to current value of PHY_CONTROL 996 * @phy_ctrl: pointer to current value of PHY_CONTROL
999 * 997 *
@@ -1028,11 +1026,11 @@ static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1028 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1026 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1029 ctrl &= ~E1000_CTRL_FD; 1027 ctrl &= ~E1000_CTRL_FD;
1030 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1028 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1031 hw_dbg(hw, "Half Duplex\n"); 1029 hw_dbg("Half Duplex\n");
1032 } else { 1030 } else {
1033 ctrl |= E1000_CTRL_FD; 1031 ctrl |= E1000_CTRL_FD;
1034 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1032 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1035 hw_dbg(hw, "Full Duplex\n"); 1033 hw_dbg("Full Duplex\n");
1036 } 1034 }
1037 1035
1038 /* Forcing 10mb or 100mb? */ 1036 /* Forcing 10mb or 100mb? */
@@ -1040,12 +1038,12 @@ static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1040 ctrl |= E1000_CTRL_SPD_100; 1038 ctrl |= E1000_CTRL_SPD_100;
1041 *phy_ctrl |= MII_CR_SPEED_100; 1039 *phy_ctrl |= MII_CR_SPEED_100;
1042 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1040 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1043 hw_dbg(hw, "Forcing 100mb\n"); 1041 hw_dbg("Forcing 100mb\n");
1044 } else { 1042 } else {
1045 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1043 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1046 *phy_ctrl |= MII_CR_SPEED_10; 1044 *phy_ctrl |= MII_CR_SPEED_10;
1047 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1045 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1048 hw_dbg(hw, "Forcing 10mb\n"); 1046 hw_dbg("Forcing 10mb\n");
1049 } 1047 }
1050 1048
1051 igb_config_collision_dist(hw); 1049 igb_config_collision_dist(hw);
@@ -1054,7 +1052,7 @@ static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1054} 1052}
1055 1053
1056/** 1054/**
1057 * e1000_set_d3_lplu_state - Sets low power link up state for D3 1055 * igb_set_d3_lplu_state - Sets low power link up state for D3
1058 * @hw: pointer to the HW structure 1056 * @hw: pointer to the HW structure
1059 * @active: boolean used to enable/disable lplu 1057 * @active: boolean used to enable/disable lplu
1060 * 1058 *
@@ -1146,7 +1144,7 @@ out:
1146} 1144}
1147 1145
1148/** 1146/**
1149 * e1000_check_downshift - Checks whether a downshift in speed occured 1147 * igb_check_downshift - Checks whether a downshift in speed occured
1150 * @hw: pointer to the HW structure 1148 * @hw: pointer to the HW structure
1151 * 1149 *
1152 * Success returns 0, Failure returns 1 1150 * Success returns 0, Failure returns 1
@@ -1188,7 +1186,7 @@ out:
1188} 1186}
1189 1187
1190/** 1188/**
1191 * e1000_check_polarity_m88 - Checks the polarity. 1189 * igb_check_polarity_m88 - Checks the polarity.
1192 * @hw: pointer to the HW structure 1190 * @hw: pointer to the HW structure
1193 * 1191 *
1194 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1192 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
@@ -1212,7 +1210,7 @@ static s32 igb_check_polarity_m88(struct e1000_hw *hw)
1212} 1210}
1213 1211
1214/** 1212/**
1215 * e1000_check_polarity_igp - Checks the polarity. 1213 * igb_check_polarity_igp - Checks the polarity.
1216 * @hw: pointer to the HW structure 1214 * @hw: pointer to the HW structure
1217 * 1215 *
1218 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1216 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
@@ -1260,7 +1258,7 @@ out:
1260} 1258}
1261 1259
1262/** 1260/**
1263 * e1000_wait_autoneg - Wait for auto-neg compeletion 1261 * igb_wait_autoneg - Wait for auto-neg compeletion
1264 * @hw: pointer to the HW structure 1262 * @hw: pointer to the HW structure
1265 * 1263 *
1266 * Waits for auto-negotiation to complete or for the auto-negotiation time 1264 * Waits for auto-negotiation to complete or for the auto-negotiation time
@@ -1292,7 +1290,7 @@ static s32 igb_wait_autoneg(struct e1000_hw *hw)
1292} 1290}
1293 1291
1294/** 1292/**
1295 * e1000_phy_has_link - Polls PHY for link 1293 * igb_phy_has_link - Polls PHY for link
1296 * @hw: pointer to the HW structure 1294 * @hw: pointer to the HW structure
1297 * @iterations: number of times to poll for link 1295 * @iterations: number of times to poll for link
1298 * @usec_interval: delay between polling attempts 1296 * @usec_interval: delay between polling attempts
@@ -1332,7 +1330,7 @@ s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1332} 1330}
1333 1331
1334/** 1332/**
1335 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 1333 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1336 * @hw: pointer to the HW structure 1334 * @hw: pointer to the HW structure
1337 * 1335 *
1338 * Reads the PHY specific status register to retrieve the cable length 1336 * Reads the PHY specific status register to retrieve the cable length
@@ -1369,7 +1367,7 @@ out:
1369} 1367}
1370 1368
1371/** 1369/**
1372 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1370 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1373 * @hw: pointer to the HW structure 1371 * @hw: pointer to the HW structure
1374 * 1372 *
1375 * The automatic gain control (agc) normalizes the amplitude of the 1373 * The automatic gain control (agc) normalizes the amplitude of the
@@ -1442,7 +1440,7 @@ out:
1442} 1440}
1443 1441
1444/** 1442/**
1445 * e1000_get_phy_info_m88 - Retrieve PHY information 1443 * igb_get_phy_info_m88 - Retrieve PHY information
1446 * @hw: pointer to the HW structure 1444 * @hw: pointer to the HW structure
1447 * 1445 *
1448 * Valid for only copper links. Read the PHY status register (sticky read) 1446 * Valid for only copper links. Read the PHY status register (sticky read)
@@ -1459,7 +1457,7 @@ s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1459 bool link; 1457 bool link;
1460 1458
1461 if (hw->phy.media_type != e1000_media_type_copper) { 1459 if (hw->phy.media_type != e1000_media_type_copper) {
1462 hw_dbg(hw, "Phy info is only valid for copper media\n"); 1460 hw_dbg("Phy info is only valid for copper media\n");
1463 ret_val = -E1000_ERR_CONFIG; 1461 ret_val = -E1000_ERR_CONFIG;
1464 goto out; 1462 goto out;
1465 } 1463 }
@@ -1469,7 +1467,7 @@ s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1469 goto out; 1467 goto out;
1470 1468
1471 if (!link) { 1469 if (!link) {
1472 hw_dbg(hw, "Phy info is only valid if link is up\n"); 1470 hw_dbg("Phy info is only valid if link is up\n");
1473 ret_val = -E1000_ERR_CONFIG; 1471 ret_val = -E1000_ERR_CONFIG;
1474 goto out; 1472 goto out;
1475 } 1473 }
@@ -1523,7 +1521,7 @@ out:
1523} 1521}
1524 1522
1525/** 1523/**
1526 * e1000_get_phy_info_igp - Retrieve igp PHY information 1524 * igb_get_phy_info_igp - Retrieve igp PHY information
1527 * @hw: pointer to the HW structure 1525 * @hw: pointer to the HW structure
1528 * 1526 *
1529 * Read PHY status to determine if link is up. If link is up, then 1527 * Read PHY status to determine if link is up. If link is up, then
@@ -1543,7 +1541,7 @@ s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1543 goto out; 1541 goto out;
1544 1542
1545 if (!link) { 1543 if (!link) {
1546 hw_dbg(hw, "Phy info is only valid if link is up\n"); 1544 hw_dbg("Phy info is only valid if link is up\n");
1547 ret_val = -E1000_ERR_CONFIG; 1545 ret_val = -E1000_ERR_CONFIG;
1548 goto out; 1546 goto out;
1549 } 1547 }
@@ -1590,7 +1588,7 @@ out:
1590} 1588}
1591 1589
1592/** 1590/**
1593 * e1000_phy_sw_reset - PHY software reset 1591 * igb_phy_sw_reset - PHY software reset
1594 * @hw: pointer to the HW structure 1592 * @hw: pointer to the HW structure
1595 * 1593 *
1596 * Does a software reset of the PHY by reading the PHY control register and 1594 * Does a software reset of the PHY by reading the PHY control register and
@@ -1617,7 +1615,7 @@ out:
1617} 1615}
1618 1616
1619/** 1617/**
1620 * e1000_phy_hw_reset - PHY hardware reset 1618 * igb_phy_hw_reset - PHY hardware reset
1621 * @hw: pointer to the HW structure 1619 * @hw: pointer to the HW structure
1622 * 1620 *
1623 * Verify the reset block is not blocking us from resetting. Acquire 1621 * Verify the reset block is not blocking us from resetting. Acquire
@@ -1663,7 +1661,7 @@ out:
1663/* Internal function pointers */ 1661/* Internal function pointers */
1664 1662
1665/** 1663/**
1666 * e1000_get_phy_cfg_done - Generic PHY configuration done 1664 * igb_get_phy_cfg_done - Generic PHY configuration done
1667 * @hw: pointer to the HW structure 1665 * @hw: pointer to the HW structure
1668 * 1666 *
1669 * Return success if silicon family did not implement a family specific 1667 * Return success if silicon family did not implement a family specific
@@ -1678,7 +1676,7 @@ static s32 igb_get_phy_cfg_done(struct e1000_hw *hw)
1678} 1676}
1679 1677
1680/** 1678/**
1681 * e1000_release_phy - Generic release PHY 1679 * igb_release_phy - Generic release PHY
1682 * @hw: pointer to the HW structure 1680 * @hw: pointer to the HW structure
1683 * 1681 *
1684 * Return if silicon family does not require a semaphore when accessing the 1682 * Return if silicon family does not require a semaphore when accessing the
@@ -1691,7 +1689,7 @@ static void igb_release_phy(struct e1000_hw *hw)
1691} 1689}
1692 1690
1693/** 1691/**
1694 * e1000_acquire_phy - Generic acquire PHY 1692 * igb_acquire_phy - Generic acquire PHY
1695 * @hw: pointer to the HW structure 1693 * @hw: pointer to the HW structure
1696 * 1694 *
1697 * Return success if silicon family does not require a semaphore when 1695 * Return success if silicon family does not require a semaphore when
@@ -1706,7 +1704,7 @@ static s32 igb_acquire_phy(struct e1000_hw *hw)
1706} 1704}
1707 1705
1708/** 1706/**
1709 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex 1707 * igb_phy_force_speed_duplex - Generic force PHY speed/duplex
1710 * @hw: pointer to the HW structure 1708 * @hw: pointer to the HW structure
1711 * 1709 *
1712 * When the silicon family has not implemented a forced speed/duplex 1710 * When the silicon family has not implemented a forced speed/duplex
@@ -1721,14 +1719,14 @@ s32 igb_phy_force_speed_duplex(struct e1000_hw *hw)
1721} 1719}
1722 1720
1723/** 1721/**
1724 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 1722 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
1725 * @hw: pointer to the HW structure 1723 * @hw: pointer to the HW structure
1726 * 1724 *
1727 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 1725 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1728 **/ 1726 **/
1729s32 igb_phy_init_script_igp3(struct e1000_hw *hw) 1727s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
1730{ 1728{
1731 hw_dbg(hw, "Running IGP 3 PHY init script\n"); 1729 hw_dbg("Running IGP 3 PHY init script\n");
1732 1730
1733 /* PHY init IGP 3 */ 1731 /* PHY init IGP 3 */
1734 /* Enable rise/fall, 10-mode work in class-A */ 1732 /* Enable rise/fall, 10-mode work in class-A */
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h
index ff187b73c69e..b95093d24c09 100644
--- a/drivers/net/igb/e1000_regs.h
+++ b/drivers/net/igb/e1000_regs.h
@@ -56,6 +56,9 @@
56#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 56#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
57#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 57#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
58#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 58#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
59#define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
60#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
61#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
59#define E1000_TCTL 0x00400 /* TX Control - RW */ 62#define E1000_TCTL 0x00400 /* TX Control - RW */
60#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 63#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
61#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 64#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
@@ -217,6 +220,7 @@
217#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 220#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
218#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 221#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
219#define E1000_RA 0x05400 /* Receive Address - RW Array */ 222#define E1000_RA 0x05400 /* Receive Address - RW Array */
223#define E1000_RA2 0x054E0 /* 2nd half of receive address array - RW Array */
220#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 224#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
221#define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */ 225#define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */
222#define E1000_WUC 0x05800 /* Wakeup Control - RW */ 226#define E1000_WUC 0x05800 /* Wakeup Control - RW */
@@ -235,6 +239,8 @@
235#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 239#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
236#define E1000_SWSM 0x05B50 /* SW Semaphore */ 240#define E1000_SWSM 0x05B50 /* SW Semaphore */
237#define E1000_FWSM 0x05B54 /* FW Semaphore */ 241#define E1000_FWSM 0x05B54 /* FW Semaphore */
242#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */
243#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
238#define E1000_HICR 0x08F00 /* Host Inteface Control */ 244#define E1000_HICR 0x08F00 /* Host Inteface Control */
239 245
240/* RSS registers */ 246/* RSS registers */
@@ -256,7 +262,8 @@
256#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) 262#define E1000_RETA(_i) (0x05C00 + ((_i) * 4))
257#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ 263#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
258 264
259#define E1000_REGISTER(a, reg) reg 265#define E1000_REGISTER(a, reg) (((a)->mac.type < e1000_82576) \
266 ? reg : e1000_translate_register_82576(reg))
260 267
261#define wr32(reg, value) (writel(value, hw->hw_addr + reg)) 268#define wr32(reg, value) (writel(value, hw->hw_addr + reg))
262#define rd32(reg) (readl(hw->hw_addr + reg)) 269#define rd32(reg) (readl(hw->hw_addr + reg))
diff --git a/drivers/net/igb/igb.h b/drivers/net/igb/igb.h
index 6b2e7d351d65..4ff6f0567f3f 100644
--- a/drivers/net/igb/igb.h
+++ b/drivers/net/igb/igb.h
@@ -36,12 +36,20 @@
36 36
37struct igb_adapter; 37struct igb_adapter;
38 38
39#ifdef CONFIG_IGB_LRO
40#include <linux/inet_lro.h>
41#define MAX_LRO_AGGR 32
42#define MAX_LRO_DESCRIPTORS 8
43#endif
44
39/* Interrupt defines */ 45/* Interrupt defines */
40#define IGB_MAX_TX_CLEAN 72 46#define IGB_MAX_TX_CLEAN 72
41 47
42#define IGB_MIN_DYN_ITR 3000 48#define IGB_MIN_DYN_ITR 3000
43#define IGB_MAX_DYN_ITR 96000 49#define IGB_MAX_DYN_ITR 96000
44#define IGB_START_ITR 6000 50
51/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
52#define IGB_START_ITR 648
45 53
46#define IGB_DYN_ITR_PACKET_THRESHOLD 2 54#define IGB_DYN_ITR_PACKET_THRESHOLD 2
47#define IGB_DYN_ITR_LENGTH_LOW 200 55#define IGB_DYN_ITR_LENGTH_LOW 200
@@ -62,6 +70,7 @@ struct igb_adapter;
62 70
63/* Transmit and receive queues */ 71/* Transmit and receive queues */
64#define IGB_MAX_RX_QUEUES 4 72#define IGB_MAX_RX_QUEUES 4
73#define IGB_MAX_TX_QUEUES 4
65 74
66/* RX descriptor control thresholds. 75/* RX descriptor control thresholds.
67 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 76 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
@@ -124,6 +133,7 @@ struct igb_buffer {
124 struct { 133 struct {
125 struct page *page; 134 struct page *page;
126 u64 page_dma; 135 u64 page_dma;
136 unsigned int page_offset;
127 }; 137 };
128 }; 138 };
129}; 139};
@@ -150,24 +160,26 @@ struct igb_ring {
150 u16 itr_register; 160 u16 itr_register;
151 u16 cpu; 161 u16 cpu;
152 162
163 int queue_index;
153 unsigned int total_bytes; 164 unsigned int total_bytes;
154 unsigned int total_packets; 165 unsigned int total_packets;
155 166
156 union { 167 union {
157 /* TX */ 168 /* TX */
158 struct { 169 struct {
159 spinlock_t tx_clean_lock; 170 struct igb_queue_stats tx_stats;
160 spinlock_t tx_lock;
161 bool detect_tx_hung; 171 bool detect_tx_hung;
162 }; 172 };
163 /* RX */ 173 /* RX */
164 struct { 174 struct {
165 /* arrays of page information for packet split */
166 struct sk_buff *pending_skb;
167 int pending_skb_page;
168 int no_itr_adjust;
169 struct igb_queue_stats rx_stats; 175 struct igb_queue_stats rx_stats;
170 struct napi_struct napi; 176 struct napi_struct napi;
177 int set_itr;
178 struct igb_ring *buddy;
179#ifdef CONFIG_IGB_LRO
180 struct net_lro_mgr lro_mgr;
181 bool lro_used;
182#endif
171 }; 183 };
172 }; 184 };
173 185
@@ -210,7 +222,6 @@ struct igb_adapter {
210 u32 itr_setting; 222 u32 itr_setting;
211 u16 tx_itr; 223 u16 tx_itr;
212 u16 rx_itr; 224 u16 rx_itr;
213 int set_itr;
214 225
215 struct work_struct reset_task; 226 struct work_struct reset_task;
216 struct work_struct watchdog_task; 227 struct work_struct watchdog_task;
@@ -265,14 +276,34 @@ struct igb_adapter {
265 int msg_enable; 276 int msg_enable;
266 struct msix_entry *msix_entries; 277 struct msix_entry *msix_entries;
267 u32 eims_enable_mask; 278 u32 eims_enable_mask;
279 u32 eims_other;
268 280
269 /* to not mess up cache alignment, always add to the bottom */ 281 /* to not mess up cache alignment, always add to the bottom */
270 unsigned long state; 282 unsigned long state;
271 unsigned int msi_enabled; 283 unsigned int flags;
272
273 u32 eeprom_wol; 284 u32 eeprom_wol;
285
286 /* for ioport free */
287 int bars;
288 int need_ioport;
289
290 struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
291#ifdef CONFIG_IGB_LRO
292 unsigned int lro_max_aggr;
293 unsigned int lro_aggregated;
294 unsigned int lro_flushed;
295 unsigned int lro_no_desc;
296#endif
274}; 297};
275 298
299#define IGB_FLAG_HAS_MSI (1 << 0)
300#define IGB_FLAG_MSI_ENABLE (1 << 1)
301#define IGB_FLAG_HAS_DCA (1 << 2)
302#define IGB_FLAG_DCA_ENABLED (1 << 3)
303#define IGB_FLAG_IN_NETPOLL (1 << 5)
304#define IGB_FLAG_QUAD_PORT_A (1 << 6)
305#define IGB_FLAG_NEED_CTX_IDX (1 << 7)
306
276enum e1000_state_t { 307enum e1000_state_t {
277 __IGB_TESTING, 308 __IGB_TESTING,
278 __IGB_RESETTING, 309 __IGB_RESETTING,
diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c
index 0447f9bcd27a..11aee1309951 100644
--- a/drivers/net/igb/igb_ethtool.c
+++ b/drivers/net/igb/igb_ethtool.c
@@ -93,13 +93,16 @@ static const struct igb_stats igb_gstrings_stats[] = {
93 { "tx_smbus", IGB_STAT(stats.mgptc) }, 93 { "tx_smbus", IGB_STAT(stats.mgptc) },
94 { "rx_smbus", IGB_STAT(stats.mgprc) }, 94 { "rx_smbus", IGB_STAT(stats.mgprc) },
95 { "dropped_smbus", IGB_STAT(stats.mgpdc) }, 95 { "dropped_smbus", IGB_STAT(stats.mgpdc) },
96#ifdef CONFIG_IGB_LRO
97 { "lro_aggregated", IGB_STAT(lro_aggregated) },
98 { "lro_flushed", IGB_STAT(lro_flushed) },
99 { "lro_no_desc", IGB_STAT(lro_no_desc) },
100#endif
96}; 101};
97 102
98#define IGB_QUEUE_STATS_LEN \ 103#define IGB_QUEUE_STATS_LEN \
99 ((((((struct igb_adapter *)netdev->priv)->num_rx_queues > 1) ? \ 104 ((((struct igb_adapter *)netdev->priv)->num_rx_queues + \
100 ((struct igb_adapter *)netdev->priv)->num_rx_queues : 0) + \ 105 ((struct igb_adapter *)netdev->priv)->num_tx_queues) * \
101 (((((struct igb_adapter *)netdev->priv)->num_tx_queues > 1) ? \
102 ((struct igb_adapter *)netdev->priv)->num_tx_queues : 0))) * \
103 (sizeof(struct igb_queue_stats) / sizeof(u64))) 106 (sizeof(struct igb_queue_stats) / sizeof(u64)))
104#define IGB_GLOBAL_STATS_LEN \ 107#define IGB_GLOBAL_STATS_LEN \
105 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats) 108 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
@@ -829,8 +832,9 @@ err_setup:
829/* ethtool register test data */ 832/* ethtool register test data */
830struct igb_reg_test { 833struct igb_reg_test {
831 u16 reg; 834 u16 reg;
832 u8 array_len; 835 u16 reg_offset;
833 u8 test_type; 836 u16 array_len;
837 u16 test_type;
834 u32 mask; 838 u32 mask;
835 u32 write; 839 u32 write;
836}; 840};
@@ -852,34 +856,72 @@ struct igb_reg_test {
852#define TABLE64_TEST_LO 5 856#define TABLE64_TEST_LO 5
853#define TABLE64_TEST_HI 6 857#define TABLE64_TEST_HI 6
854 858
855/* default register test */ 859/* 82576 reg test */
860static struct igb_reg_test reg_test_82576[] = {
861 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
862 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
863 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
864 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
865 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
866 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
867 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
868 { E1000_RDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
869 { E1000_RDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
870 { E1000_RDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
871 /* Enable all four RX queues before testing. */
872 { E1000_RXDCTL(0), 0x100, 1, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
873 /* RDH is read-only for 82576, only test RDT. */
874 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
875 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
876 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
877 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
878 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
879 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
880 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
881 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
882 { E1000_TDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
883 { E1000_TDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
884 { E1000_TDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
885 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
886 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
887 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
888 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
889 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
890 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
891 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
892 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
893 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
894 { 0, 0, 0, 0 }
895};
896
897/* 82575 register test */
856static struct igb_reg_test reg_test_82575[] = { 898static struct igb_reg_test reg_test_82575[] = {
857 { E1000_FCAL, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 899 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
858 { E1000_FCAH, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 900 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
859 { E1000_FCT, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 901 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
860 { E1000_VET, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 902 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
861 { E1000_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 903 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
862 { E1000_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 904 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
863 { E1000_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 905 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
864 /* Enable all four RX queues before testing. */ 906 /* Enable all four RX queues before testing. */
865 { E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 907 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
866 /* RDH is read-only for 82575, only test RDT. */ 908 /* RDH is read-only for 82575, only test RDT. */
867 { E1000_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 909 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
868 { E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 910 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
869 { E1000_FCRTH, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 911 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
870 { E1000_FCTTV, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 912 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
871 { E1000_TIPG, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 913 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
872 { E1000_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 914 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
873 { E1000_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 915 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
874 { E1000_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 916 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
875 { E1000_RCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 917 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
876 { E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 918 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
877 { E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 919 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
878 { E1000_TCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 920 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
879 { E1000_TXCW, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 921 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
880 { E1000_RA, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 922 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
881 { E1000_RA, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 923 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
882 { E1000_MTA, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 924 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
883 { 0, 0, 0, 0 } 925 { 0, 0, 0, 0 }
884}; 926};
885 927
@@ -939,7 +981,15 @@ static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
939 u32 i, toggle; 981 u32 i, toggle;
940 982
941 toggle = 0x7FFFF3FF; 983 toggle = 0x7FFFF3FF;
942 test = reg_test_82575; 984
985 switch (adapter->hw.mac.type) {
986 case e1000_82576:
987 test = reg_test_82576;
988 break;
989 default:
990 test = reg_test_82575;
991 break;
992 }
943 993
944 /* Because the status register is such a special case, 994 /* Because the status register is such a special case,
945 * we handle it separately from the rest of the register 995 * we handle it separately from the rest of the register
@@ -966,19 +1016,19 @@ static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
966 for (i = 0; i < test->array_len; i++) { 1016 for (i = 0; i < test->array_len; i++) {
967 switch (test->test_type) { 1017 switch (test->test_type) {
968 case PATTERN_TEST: 1018 case PATTERN_TEST:
969 REG_PATTERN_TEST(test->reg + (i * 0x100), 1019 REG_PATTERN_TEST(test->reg + (i * test->reg_offset),
970 test->mask, 1020 test->mask,
971 test->write); 1021 test->write);
972 break; 1022 break;
973 case SET_READ_TEST: 1023 case SET_READ_TEST:
974 REG_SET_AND_CHECK(test->reg + (i * 0x100), 1024 REG_SET_AND_CHECK(test->reg + (i * test->reg_offset),
975 test->mask, 1025 test->mask,
976 test->write); 1026 test->write);
977 break; 1027 break;
978 case WRITE_NO_TEST: 1028 case WRITE_NO_TEST:
979 writel(test->write, 1029 writel(test->write,
980 (adapter->hw.hw_addr + test->reg) 1030 (adapter->hw.hw_addr + test->reg)
981 + (i * 0x100)); 1031 + (i * test->reg_offset));
982 break; 1032 break;
983 case TABLE32_TEST: 1033 case TABLE32_TEST:
984 REG_PATTERN_TEST(test->reg + (i * 4), 1034 REG_PATTERN_TEST(test->reg + (i * 4),
@@ -1052,7 +1102,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1052 if (adapter->msix_entries) { 1102 if (adapter->msix_entries) {
1053 /* NOTE: we don't test MSI-X interrupts here, yet */ 1103 /* NOTE: we don't test MSI-X interrupts here, yet */
1054 return 0; 1104 return 0;
1055 } else if (adapter->msi_enabled) { 1105 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1056 shared_int = false; 1106 shared_int = false;
1057 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) { 1107 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1058 *data = 1; 1108 *data = 1;
@@ -1394,13 +1444,39 @@ static int igb_set_phy_loopback(struct igb_adapter *adapter)
1394static int igb_setup_loopback_test(struct igb_adapter *adapter) 1444static int igb_setup_loopback_test(struct igb_adapter *adapter)
1395{ 1445{
1396 struct e1000_hw *hw = &adapter->hw; 1446 struct e1000_hw *hw = &adapter->hw;
1397 u32 rctl; 1447 u32 reg;
1398 1448
1399 if (hw->phy.media_type == e1000_media_type_fiber || 1449 if (hw->phy.media_type == e1000_media_type_fiber ||
1400 hw->phy.media_type == e1000_media_type_internal_serdes) { 1450 hw->phy.media_type == e1000_media_type_internal_serdes) {
1401 rctl = rd32(E1000_RCTL); 1451 reg = rd32(E1000_RCTL);
1402 rctl |= E1000_RCTL_LBM_TCVR; 1452 reg |= E1000_RCTL_LBM_TCVR;
1403 wr32(E1000_RCTL, rctl); 1453 wr32(E1000_RCTL, reg);
1454
1455 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1456
1457 reg = rd32(E1000_CTRL);
1458 reg &= ~(E1000_CTRL_RFCE |
1459 E1000_CTRL_TFCE |
1460 E1000_CTRL_LRST);
1461 reg |= E1000_CTRL_SLU |
1462 E1000_CTRL_FD;
1463 wr32(E1000_CTRL, reg);
1464
1465 /* Unset switch control to serdes energy detect */
1466 reg = rd32(E1000_CONNSW);
1467 reg &= ~E1000_CONNSW_ENRGSRC;
1468 wr32(E1000_CONNSW, reg);
1469
1470 /* Set PCS register for forced speed */
1471 reg = rd32(E1000_PCS_LCTL);
1472 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1473 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1474 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1475 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1476 E1000_PCS_LCTL_FSD | /* Force Speed */
1477 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1478 wr32(E1000_PCS_LCTL, reg);
1479
1404 return 0; 1480 return 0;
1405 } else if (hw->phy.media_type == e1000_media_type_copper) { 1481 } else if (hw->phy.media_type == e1000_media_type_copper) {
1406 return igb_set_phy_loopback(adapter); 1482 return igb_set_phy_loopback(adapter);
@@ -1660,6 +1736,8 @@ static int igb_wol_exclusion(struct igb_adapter *adapter,
1660 wol->supported = 0; 1736 wol->supported = 0;
1661 break; 1737 break;
1662 case E1000_DEV_ID_82575EB_FIBER_SERDES: 1738 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1739 case E1000_DEV_ID_82576_FIBER:
1740 case E1000_DEV_ID_82576_SERDES:
1663 /* Wake events not supported on port B */ 1741 /* Wake events not supported on port B */
1664 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) { 1742 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1665 wol->supported = 0; 1743 wol->supported = 0;
@@ -1668,6 +1746,15 @@ static int igb_wol_exclusion(struct igb_adapter *adapter,
1668 /* return success for non excluded adapter ports */ 1746 /* return success for non excluded adapter ports */
1669 retval = 0; 1747 retval = 0;
1670 break; 1748 break;
1749 case E1000_DEV_ID_82576_QUAD_COPPER:
1750 /* quad port adapters only support WoL on port A */
1751 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1752 wol->supported = 0;
1753 break;
1754 }
1755 /* return success for non excluded adapter ports */
1756 retval = 0;
1757 break;
1671 default: 1758 default:
1672 /* dual port cards only support WoL on port A from now on 1759 /* dual port cards only support WoL on port A from now on
1673 * unless it was enabled in the eeprom for port B 1760 * unless it was enabled in the eeprom for port B
@@ -1774,6 +1861,8 @@ static int igb_set_coalesce(struct net_device *netdev,
1774 struct ethtool_coalesce *ec) 1861 struct ethtool_coalesce *ec)
1775{ 1862{
1776 struct igb_adapter *adapter = netdev_priv(netdev); 1863 struct igb_adapter *adapter = netdev_priv(netdev);
1864 struct e1000_hw *hw = &adapter->hw;
1865 int i;
1777 1866
1778 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 1867 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1779 ((ec->rx_coalesce_usecs > 3) && 1868 ((ec->rx_coalesce_usecs > 3) &&
@@ -1782,13 +1871,16 @@ static int igb_set_coalesce(struct net_device *netdev,
1782 return -EINVAL; 1871 return -EINVAL;
1783 1872
1784 /* convert to rate of irq's per second */ 1873 /* convert to rate of irq's per second */
1785 if (ec->rx_coalesce_usecs <= 3) 1874 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
1786 adapter->itr_setting = ec->rx_coalesce_usecs; 1875 adapter->itr_setting = ec->rx_coalesce_usecs;
1787 else 1876 adapter->itr = IGB_START_ITR;
1788 adapter->itr_setting = (1000000 / ec->rx_coalesce_usecs); 1877 } else {
1878 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1879 adapter->itr = adapter->itr_setting;
1880 }
1789 1881
1790 if (netif_running(netdev)) 1882 for (i = 0; i < adapter->num_rx_queues; i++)
1791 igb_reinit_locked(adapter); 1883 wr32(adapter->rx_ring[i].itr_register, adapter->itr);
1792 1884
1793 return 0; 1885 return 0;
1794} 1886}
@@ -1801,7 +1893,7 @@ static int igb_get_coalesce(struct net_device *netdev,
1801 if (adapter->itr_setting <= 3) 1893 if (adapter->itr_setting <= 3)
1802 ec->rx_coalesce_usecs = adapter->itr_setting; 1894 ec->rx_coalesce_usecs = adapter->itr_setting;
1803 else 1895 else
1804 ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting; 1896 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
1805 1897
1806 return 0; 1898 return 0;
1807} 1899}
@@ -1835,6 +1927,18 @@ static void igb_get_ethtool_stats(struct net_device *netdev,
1835 int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64); 1927 int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64);
1836 int j; 1928 int j;
1837 int i; 1929 int i;
1930#ifdef CONFIG_IGB_LRO
1931 int aggregated = 0, flushed = 0, no_desc = 0;
1932
1933 for (i = 0; i < adapter->num_rx_queues; i++) {
1934 aggregated += adapter->rx_ring[i].lro_mgr.stats.aggregated;
1935 flushed += adapter->rx_ring[i].lro_mgr.stats.flushed;
1936 no_desc += adapter->rx_ring[i].lro_mgr.stats.no_desc;
1937 }
1938 adapter->lro_aggregated = aggregated;
1939 adapter->lro_flushed = flushed;
1940 adapter->lro_no_desc = no_desc;
1941#endif
1838 1942
1839 igb_update_stats(adapter); 1943 igb_update_stats(adapter);
1840 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 1944 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
@@ -1842,6 +1946,13 @@ static void igb_get_ethtool_stats(struct net_device *netdev,
1842 data[i] = (igb_gstrings_stats[i].sizeof_stat == 1946 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1843 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1947 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1844 } 1948 }
1949 for (j = 0; j < adapter->num_tx_queues; j++) {
1950 int k;
1951 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1952 for (k = 0; k < stat_count; k++)
1953 data[i + k] = queue_stat[k];
1954 i += k;
1955 }
1845 for (j = 0; j < adapter->num_rx_queues; j++) { 1956 for (j = 0; j < adapter->num_rx_queues; j++) {
1846 int k; 1957 int k;
1847 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats; 1958 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index e79a26a886c8..1b7cb29fe68e 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -41,22 +41,27 @@
41#include <linux/delay.h> 41#include <linux/delay.h>
42#include <linux/interrupt.h> 42#include <linux/interrupt.h>
43#include <linux/if_ether.h> 43#include <linux/if_ether.h>
44 44#ifdef CONFIG_DCA
45#include <linux/dca.h>
46#endif
45#include "igb.h" 47#include "igb.h"
46 48
47#define DRV_VERSION "1.0.8-k2" 49#define DRV_VERSION "1.2.45-k2"
48char igb_driver_name[] = "igb"; 50char igb_driver_name[] = "igb";
49char igb_driver_version[] = DRV_VERSION; 51char igb_driver_version[] = DRV_VERSION;
50static const char igb_driver_string[] = 52static const char igb_driver_string[] =
51 "Intel(R) Gigabit Ethernet Network Driver"; 53 "Intel(R) Gigabit Ethernet Network Driver";
52static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation."; 54static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
53
54 55
55static const struct e1000_info *igb_info_tbl[] = { 56static const struct e1000_info *igb_info_tbl[] = {
56 [board_82575] = &e1000_82575_info, 57 [board_82575] = &e1000_82575_info,
57}; 58};
58 59
59static struct pci_device_id igb_pci_tbl[] = { 60static struct pci_device_id igb_pci_tbl[] = {
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
60 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
@@ -71,8 +76,8 @@ static int igb_setup_all_tx_resources(struct igb_adapter *);
71static int igb_setup_all_rx_resources(struct igb_adapter *); 76static int igb_setup_all_rx_resources(struct igb_adapter *);
72static void igb_free_all_tx_resources(struct igb_adapter *); 77static void igb_free_all_tx_resources(struct igb_adapter *);
73static void igb_free_all_rx_resources(struct igb_adapter *); 78static void igb_free_all_rx_resources(struct igb_adapter *);
74static void igb_free_tx_resources(struct igb_adapter *, struct igb_ring *); 79static void igb_free_tx_resources(struct igb_ring *);
75static void igb_free_rx_resources(struct igb_adapter *, struct igb_ring *); 80static void igb_free_rx_resources(struct igb_ring *);
76void igb_update_stats(struct igb_adapter *); 81void igb_update_stats(struct igb_adapter *);
77static int igb_probe(struct pci_dev *, const struct pci_device_id *); 82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
78static void __devexit igb_remove(struct pci_dev *pdev); 83static void __devexit igb_remove(struct pci_dev *pdev);
@@ -84,8 +89,8 @@ static void igb_configure_rx(struct igb_adapter *);
84static void igb_setup_rctl(struct igb_adapter *); 89static void igb_setup_rctl(struct igb_adapter *);
85static void igb_clean_all_tx_rings(struct igb_adapter *); 90static void igb_clean_all_tx_rings(struct igb_adapter *);
86static void igb_clean_all_rx_rings(struct igb_adapter *); 91static void igb_clean_all_rx_rings(struct igb_adapter *);
87static void igb_clean_tx_ring(struct igb_adapter *, struct igb_ring *); 92static void igb_clean_tx_ring(struct igb_ring *);
88static void igb_clean_rx_ring(struct igb_adapter *, struct igb_ring *); 93static void igb_clean_rx_ring(struct igb_ring *);
89static void igb_set_multi(struct net_device *); 94static void igb_set_multi(struct net_device *);
90static void igb_update_phy_info(unsigned long); 95static void igb_update_phy_info(unsigned long);
91static void igb_watchdog(unsigned long); 96static void igb_watchdog(unsigned long);
@@ -102,12 +107,18 @@ static irqreturn_t igb_msix_other(int irq, void *);
102static irqreturn_t igb_msix_rx(int irq, void *); 107static irqreturn_t igb_msix_rx(int irq, void *);
103static irqreturn_t igb_msix_tx(int irq, void *); 108static irqreturn_t igb_msix_tx(int irq, void *);
104static int igb_clean_rx_ring_msix(struct napi_struct *, int); 109static int igb_clean_rx_ring_msix(struct napi_struct *, int);
105static bool igb_clean_tx_irq(struct igb_adapter *, struct igb_ring *); 110#ifdef CONFIG_DCA
106static int igb_clean(struct napi_struct *, int); 111static void igb_update_rx_dca(struct igb_ring *);
107static bool igb_clean_rx_irq_adv(struct igb_adapter *, 112static void igb_update_tx_dca(struct igb_ring *);
108 struct igb_ring *, int *, int); 113static void igb_setup_dca(struct igb_adapter *);
109static void igb_alloc_rx_buffers_adv(struct igb_adapter *, 114#endif /* CONFIG_DCA */
110 struct igb_ring *, int); 115static bool igb_clean_tx_irq(struct igb_ring *);
116static int igb_poll(struct napi_struct *, int);
117static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
119#ifdef CONFIG_IGB_LRO
120static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
121#endif
111static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 122static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
112static void igb_tx_timeout(struct net_device *); 123static void igb_tx_timeout(struct net_device *);
113static void igb_reset_task(struct work_struct *); 124static void igb_reset_task(struct work_struct *);
@@ -121,6 +132,14 @@ static int igb_suspend(struct pci_dev *, pm_message_t);
121static int igb_resume(struct pci_dev *); 132static int igb_resume(struct pci_dev *);
122#endif 133#endif
123static void igb_shutdown(struct pci_dev *); 134static void igb_shutdown(struct pci_dev *);
135#ifdef CONFIG_DCA
136static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
137static struct notifier_block dca_notifier = {
138 .notifier_call = igb_notify_dca,
139 .next = NULL,
140 .priority = 0
141};
142#endif
124 143
125#ifdef CONFIG_NET_POLL_CONTROLLER 144#ifdef CONFIG_NET_POLL_CONTROLLER
126/* for netdump / net console */ 145/* for netdump / net console */
@@ -153,6 +172,8 @@ static struct pci_driver igb_driver = {
153 .err_handler = &igb_err_handler 172 .err_handler = &igb_err_handler
154}; 173};
155 174
175static int global_quad_port_a; /* global quad port a indication */
176
156MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 177MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
157MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 178MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
158MODULE_LICENSE("GPL"); 179MODULE_LICENSE("GPL");
@@ -184,7 +205,12 @@ static int __init igb_init_module(void)
184 205
185 printk(KERN_INFO "%s\n", igb_copyright); 206 printk(KERN_INFO "%s\n", igb_copyright);
186 207
208 global_quad_port_a = 0;
209
187 ret = pci_register_driver(&igb_driver); 210 ret = pci_register_driver(&igb_driver);
211#ifdef CONFIG_DCA
212 dca_register_notify(&dca_notifier);
213#endif
188 return ret; 214 return ret;
189} 215}
190 216
@@ -198,6 +224,9 @@ module_init(igb_init_module);
198 **/ 224 **/
199static void __exit igb_exit_module(void) 225static void __exit igb_exit_module(void)
200{ 226{
227#ifdef CONFIG_DCA
228 dca_unregister_notify(&dca_notifier);
229#endif
201 pci_unregister_driver(&igb_driver); 230 pci_unregister_driver(&igb_driver);
202} 231}
203 232
@@ -226,25 +255,46 @@ static int igb_alloc_queues(struct igb_adapter *adapter)
226 return -ENOMEM; 255 return -ENOMEM;
227 } 256 }
228 257
258 adapter->rx_ring->buddy = adapter->tx_ring;
259
260 for (i = 0; i < adapter->num_tx_queues; i++) {
261 struct igb_ring *ring = &(adapter->tx_ring[i]);
262 ring->adapter = adapter;
263 ring->queue_index = i;
264 }
229 for (i = 0; i < adapter->num_rx_queues; i++) { 265 for (i = 0; i < adapter->num_rx_queues; i++) {
230 struct igb_ring *ring = &(adapter->rx_ring[i]); 266 struct igb_ring *ring = &(adapter->rx_ring[i]);
231 ring->adapter = adapter; 267 ring->adapter = adapter;
268 ring->queue_index = i;
232 ring->itr_register = E1000_ITR; 269 ring->itr_register = E1000_ITR;
233 270
234 if (!ring->napi.poll) 271 /* set a default napi handler for each rx_ring */
235 netif_napi_add(adapter->netdev, &ring->napi, igb_clean, 272 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
236 adapter->napi.weight /
237 adapter->num_rx_queues);
238 } 273 }
239 return 0; 274 return 0;
240} 275}
241 276
277static void igb_free_queues(struct igb_adapter *adapter)
278{
279 int i;
280
281 for (i = 0; i < adapter->num_rx_queues; i++)
282 netif_napi_del(&adapter->rx_ring[i].napi);
283
284 kfree(adapter->tx_ring);
285 kfree(adapter->rx_ring);
286}
287
242#define IGB_N0_QUEUE -1 288#define IGB_N0_QUEUE -1
243static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, 289static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
244 int tx_queue, int msix_vector) 290 int tx_queue, int msix_vector)
245{ 291{
246 u32 msixbm = 0; 292 u32 msixbm = 0;
247 struct e1000_hw *hw = &adapter->hw; 293 struct e1000_hw *hw = &adapter->hw;
294 u32 ivar, index;
295
296 switch (hw->mac.type) {
297 case e1000_82575:
248 /* The 82575 assigns vectors using a bitmask, which matches the 298 /* The 82575 assigns vectors using a bitmask, which matches the
249 bitmask for the EICR/EIMS/EIMC registers. To assign one 299 bitmask for the EICR/EIMS/EIMC registers. To assign one
250 or more queues to a vector, we write the appropriate bits 300 or more queues to a vector, we write the appropriate bits
@@ -259,6 +309,47 @@ static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
259 E1000_EICR_TX_QUEUE0 << tx_queue; 309 E1000_EICR_TX_QUEUE0 << tx_queue;
260 } 310 }
261 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 311 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
312 break;
313 case e1000_82576:
314 /* Kawela uses a table-based method for assigning vectors.
315 Each queue has a single entry in the table to which we write
316 a vector number along with a "valid" bit. Sadly, the layout
317 of the table is somewhat counterintuitive. */
318 if (rx_queue > IGB_N0_QUEUE) {
319 index = (rx_queue & 0x7);
320 ivar = array_rd32(E1000_IVAR0, index);
321 if (rx_queue < 8) {
322 /* vector goes into low byte of register */
323 ivar = ivar & 0xFFFFFF00;
324 ivar |= msix_vector | E1000_IVAR_VALID;
325 } else {
326 /* vector goes into third byte of register */
327 ivar = ivar & 0xFF00FFFF;
328 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
329 }
330 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
331 array_wr32(E1000_IVAR0, index, ivar);
332 }
333 if (tx_queue > IGB_N0_QUEUE) {
334 index = (tx_queue & 0x7);
335 ivar = array_rd32(E1000_IVAR0, index);
336 if (tx_queue < 8) {
337 /* vector goes into second byte of register */
338 ivar = ivar & 0xFFFF00FF;
339 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
340 } else {
341 /* vector goes into high byte of register */
342 ivar = ivar & 0x00FFFFFF;
343 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
344 }
345 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
346 array_wr32(E1000_IVAR0, index, ivar);
347 }
348 break;
349 default:
350 BUG();
351 break;
352 }
262} 353}
263 354
264/** 355/**
@@ -274,13 +365,19 @@ static void igb_configure_msix(struct igb_adapter *adapter)
274 struct e1000_hw *hw = &adapter->hw; 365 struct e1000_hw *hw = &adapter->hw;
275 366
276 adapter->eims_enable_mask = 0; 367 adapter->eims_enable_mask = 0;
368 if (hw->mac.type == e1000_82576)
369 /* Turn on MSI-X capability first, or our settings
370 * won't stick. And it will take days to debug. */
371 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
372 E1000_GPIE_PBA | E1000_GPIE_EIAME |
373 E1000_GPIE_NSICR);
277 374
278 for (i = 0; i < adapter->num_tx_queues; i++) { 375 for (i = 0; i < adapter->num_tx_queues; i++) {
279 struct igb_ring *tx_ring = &adapter->tx_ring[i]; 376 struct igb_ring *tx_ring = &adapter->tx_ring[i];
280 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++); 377 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
281 adapter->eims_enable_mask |= tx_ring->eims_value; 378 adapter->eims_enable_mask |= tx_ring->eims_value;
282 if (tx_ring->itr_val) 379 if (tx_ring->itr_val)
283 writel(1000000000 / (tx_ring->itr_val * 256), 380 writel(tx_ring->itr_val,
284 hw->hw_addr + tx_ring->itr_register); 381 hw->hw_addr + tx_ring->itr_register);
285 else 382 else
286 writel(1, hw->hw_addr + tx_ring->itr_register); 383 writel(1, hw->hw_addr + tx_ring->itr_register);
@@ -288,10 +385,11 @@ static void igb_configure_msix(struct igb_adapter *adapter)
288 385
289 for (i = 0; i < adapter->num_rx_queues; i++) { 386 for (i = 0; i < adapter->num_rx_queues; i++) {
290 struct igb_ring *rx_ring = &adapter->rx_ring[i]; 387 struct igb_ring *rx_ring = &adapter->rx_ring[i];
388 rx_ring->buddy = 0;
291 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++); 389 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
292 adapter->eims_enable_mask |= rx_ring->eims_value; 390 adapter->eims_enable_mask |= rx_ring->eims_value;
293 if (rx_ring->itr_val) 391 if (rx_ring->itr_val)
294 writel(1000000000 / (rx_ring->itr_val * 256), 392 writel(rx_ring->itr_val,
295 hw->hw_addr + rx_ring->itr_register); 393 hw->hw_addr + rx_ring->itr_register);
296 else 394 else
297 writel(1, hw->hw_addr + rx_ring->itr_register); 395 writel(1, hw->hw_addr + rx_ring->itr_register);
@@ -299,12 +397,11 @@ static void igb_configure_msix(struct igb_adapter *adapter)
299 397
300 398
301 /* set vector for other causes, i.e. link changes */ 399 /* set vector for other causes, i.e. link changes */
400 switch (hw->mac.type) {
401 case e1000_82575:
302 array_wr32(E1000_MSIXBM(0), vector++, 402 array_wr32(E1000_MSIXBM(0), vector++,
303 E1000_EIMS_OTHER); 403 E1000_EIMS_OTHER);
304 404
305 /* disable IAM for ICR interrupt bits */
306 wr32(E1000_IAM, 0);
307
308 tmp = rd32(E1000_CTRL_EXT); 405 tmp = rd32(E1000_CTRL_EXT);
309 /* enable MSI-X PBA support*/ 406 /* enable MSI-X PBA support*/
310 tmp |= E1000_CTRL_EXT_PBA_CLR; 407 tmp |= E1000_CTRL_EXT_PBA_CLR;
@@ -315,7 +412,21 @@ static void igb_configure_msix(struct igb_adapter *adapter)
315 412
316 wr32(E1000_CTRL_EXT, tmp); 413 wr32(E1000_CTRL_EXT, tmp);
317 adapter->eims_enable_mask |= E1000_EIMS_OTHER; 414 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
415 adapter->eims_other = E1000_EIMS_OTHER;
416
417 break;
418
419 case e1000_82576:
420 tmp = (vector++ | E1000_IVAR_VALID) << 8;
421 wr32(E1000_IVAR_MISC, tmp);
318 422
423 adapter->eims_enable_mask = (1 << (vector)) - 1;
424 adapter->eims_other = 1 << (vector - 1);
425 break;
426 default:
427 /* do nothing, since nothing else supports MSI-X */
428 break;
429 } /* switch (hw->mac.type) */
319 wrfl(); 430 wrfl();
320} 431}
321 432
@@ -341,7 +452,7 @@ static int igb_request_msix(struct igb_adapter *adapter)
341 if (err) 452 if (err)
342 goto out; 453 goto out;
343 ring->itr_register = E1000_EITR(0) + (vector << 2); 454 ring->itr_register = E1000_EITR(0) + (vector << 2);
344 ring->itr_val = adapter->itr; 455 ring->itr_val = 976; /* ~4000 ints/sec */
345 vector++; 456 vector++;
346 } 457 }
347 for (i = 0; i < adapter->num_rx_queues; i++) { 458 for (i = 0; i < adapter->num_rx_queues; i++) {
@@ -357,6 +468,9 @@ static int igb_request_msix(struct igb_adapter *adapter)
357 goto out; 468 goto out;
358 ring->itr_register = E1000_EITR(0) + (vector << 2); 469 ring->itr_register = E1000_EITR(0) + (vector << 2);
359 ring->itr_val = adapter->itr; 470 ring->itr_val = adapter->itr;
471 /* overwrite the poll routine for MSIX, we've already done
472 * netif_napi_add */
473 ring->napi.poll = &igb_clean_rx_ring_msix;
360 vector++; 474 vector++;
361 } 475 }
362 476
@@ -365,9 +479,6 @@ static int igb_request_msix(struct igb_adapter *adapter)
365 if (err) 479 if (err)
366 goto out; 480 goto out;
367 481
368 adapter->napi.poll = igb_clean_rx_ring_msix;
369 for (i = 0; i < adapter->num_rx_queues; i++)
370 adapter->rx_ring[i].napi.poll = adapter->napi.poll;
371 igb_configure_msix(adapter); 482 igb_configure_msix(adapter);
372 return 0; 483 return 0;
373out: 484out:
@@ -380,7 +491,7 @@ static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
380 pci_disable_msix(adapter->pdev); 491 pci_disable_msix(adapter->pdev);
381 kfree(adapter->msix_entries); 492 kfree(adapter->msix_entries);
382 adapter->msix_entries = NULL; 493 adapter->msix_entries = NULL;
383 } else if (adapter->msi_enabled) 494 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
384 pci_disable_msi(adapter->pdev); 495 pci_disable_msi(adapter->pdev);
385 return; 496 return;
386} 497}
@@ -417,8 +528,12 @@ static void igb_set_interrupt_capability(struct igb_adapter *adapter)
417 /* If we can't do MSI-X, try MSI */ 528 /* If we can't do MSI-X, try MSI */
418msi_only: 529msi_only:
419 adapter->num_rx_queues = 1; 530 adapter->num_rx_queues = 1;
531 adapter->num_tx_queues = 1;
420 if (!pci_enable_msi(adapter->pdev)) 532 if (!pci_enable_msi(adapter->pdev))
421 adapter->msi_enabled = 1; 533 adapter->flags |= IGB_FLAG_HAS_MSI;
534
535 /* Notify the stack of the (possibly) reduced Tx Queue count. */
536 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
422 return; 537 return;
423} 538}
424 539
@@ -436,29 +551,38 @@ static int igb_request_irq(struct igb_adapter *adapter)
436 551
437 if (adapter->msix_entries) { 552 if (adapter->msix_entries) {
438 err = igb_request_msix(adapter); 553 err = igb_request_msix(adapter);
439 if (!err) { 554 if (!err)
440 /* enable IAM, auto-mask,
441 * DO NOT USE EIAM or IAM in legacy mode */
442 wr32(E1000_IAM, IMS_ENABLE_MASK);
443 goto request_done; 555 goto request_done;
444 }
445 /* fall back to MSI */ 556 /* fall back to MSI */
446 igb_reset_interrupt_capability(adapter); 557 igb_reset_interrupt_capability(adapter);
447 if (!pci_enable_msi(adapter->pdev)) 558 if (!pci_enable_msi(adapter->pdev))
448 adapter->msi_enabled = 1; 559 adapter->flags |= IGB_FLAG_HAS_MSI;
449 igb_free_all_tx_resources(adapter); 560 igb_free_all_tx_resources(adapter);
450 igb_free_all_rx_resources(adapter); 561 igb_free_all_rx_resources(adapter);
451 adapter->num_rx_queues = 1; 562 adapter->num_rx_queues = 1;
452 igb_alloc_queues(adapter); 563 igb_alloc_queues(adapter);
564 } else {
565 switch (hw->mac.type) {
566 case e1000_82575:
567 wr32(E1000_MSIXBM(0),
568 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
569 break;
570 case e1000_82576:
571 wr32(E1000_IVAR0, E1000_IVAR_VALID);
572 break;
573 default:
574 break;
575 }
453 } 576 }
454 if (adapter->msi_enabled) { 577
578 if (adapter->flags & IGB_FLAG_HAS_MSI) {
455 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0, 579 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
456 netdev->name, netdev); 580 netdev->name, netdev);
457 if (!err) 581 if (!err)
458 goto request_done; 582 goto request_done;
459 /* fall back to legacy interrupts */ 583 /* fall back to legacy interrupts */
460 igb_reset_interrupt_capability(adapter); 584 igb_reset_interrupt_capability(adapter);
461 adapter->msi_enabled = 0; 585 adapter->flags &= ~IGB_FLAG_HAS_MSI;
462 } 586 }
463 587
464 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED, 588 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
@@ -502,9 +626,12 @@ static void igb_irq_disable(struct igb_adapter *adapter)
502 struct e1000_hw *hw = &adapter->hw; 626 struct e1000_hw *hw = &adapter->hw;
503 627
504 if (adapter->msix_entries) { 628 if (adapter->msix_entries) {
629 wr32(E1000_EIAM, 0);
505 wr32(E1000_EIMC, ~0); 630 wr32(E1000_EIMC, ~0);
506 wr32(E1000_EIAC, 0); 631 wr32(E1000_EIAC, 0);
507 } 632 }
633
634 wr32(E1000_IAM, 0);
508 wr32(E1000_IMC, ~0); 635 wr32(E1000_IMC, ~0);
509 wrfl(); 636 wrfl();
510 synchronize_irq(adapter->pdev->irq); 637 synchronize_irq(adapter->pdev->irq);
@@ -519,13 +646,14 @@ static void igb_irq_enable(struct igb_adapter *adapter)
519 struct e1000_hw *hw = &adapter->hw; 646 struct e1000_hw *hw = &adapter->hw;
520 647
521 if (adapter->msix_entries) { 648 if (adapter->msix_entries) {
522 wr32(E1000_EIMS, 649 wr32(E1000_EIAC, adapter->eims_enable_mask);
523 adapter->eims_enable_mask); 650 wr32(E1000_EIAM, adapter->eims_enable_mask);
524 wr32(E1000_EIAC, 651 wr32(E1000_EIMS, adapter->eims_enable_mask);
525 adapter->eims_enable_mask);
526 wr32(E1000_IMS, E1000_IMS_LSC); 652 wr32(E1000_IMS, E1000_IMS_LSC);
527 } else 653 } else {
528 wr32(E1000_IMS, IMS_ENABLE_MASK); 654 wr32(E1000_IMS, IMS_ENABLE_MASK);
655 wr32(E1000_IAM, IMS_ENABLE_MASK);
656 }
529} 657}
530 658
531static void igb_update_mng_vlan(struct igb_adapter *adapter) 659static void igb_update_mng_vlan(struct igb_adapter *adapter)
@@ -632,12 +760,15 @@ static void igb_configure(struct igb_adapter *adapter)
632 igb_configure_tx(adapter); 760 igb_configure_tx(adapter);
633 igb_setup_rctl(adapter); 761 igb_setup_rctl(adapter);
634 igb_configure_rx(adapter); 762 igb_configure_rx(adapter);
763
764 igb_rx_fifo_flush_82575(&adapter->hw);
765
635 /* call IGB_DESC_UNUSED which always leaves 766 /* call IGB_DESC_UNUSED which always leaves
636 * at least 1 descriptor unused to make sure 767 * at least 1 descriptor unused to make sure
637 * next_to_use != next_to_clean */ 768 * next_to_use != next_to_clean */
638 for (i = 0; i < adapter->num_rx_queues; i++) { 769 for (i = 0; i < adapter->num_rx_queues; i++) {
639 struct igb_ring *ring = &adapter->rx_ring[i]; 770 struct igb_ring *ring = &adapter->rx_ring[i];
640 igb_alloc_rx_buffers_adv(adapter, ring, IGB_DESC_UNUSED(ring)); 771 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
641 } 772 }
642 773
643 774
@@ -660,13 +791,10 @@ int igb_up(struct igb_adapter *adapter)
660 791
661 clear_bit(__IGB_DOWN, &adapter->state); 792 clear_bit(__IGB_DOWN, &adapter->state);
662 793
663 napi_enable(&adapter->napi); 794 for (i = 0; i < adapter->num_rx_queues; i++)
664 795 napi_enable(&adapter->rx_ring[i].napi);
665 if (adapter->msix_entries) { 796 if (adapter->msix_entries)
666 for (i = 0; i < adapter->num_rx_queues; i++)
667 napi_enable(&adapter->rx_ring[i].napi);
668 igb_configure_msix(adapter); 797 igb_configure_msix(adapter);
669 }
670 798
671 /* Clear any pending interrupts. */ 799 /* Clear any pending interrupts. */
672 rd32(E1000_ICR); 800 rd32(E1000_ICR);
@@ -693,7 +821,7 @@ void igb_down(struct igb_adapter *adapter)
693 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 821 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
694 /* flush and sleep below */ 822 /* flush and sleep below */
695 823
696 netif_stop_queue(netdev); 824 netif_tx_stop_all_queues(netdev);
697 825
698 /* disable transmits in the hardware */ 826 /* disable transmits in the hardware */
699 tctl = rd32(E1000_TCTL); 827 tctl = rd32(E1000_TCTL);
@@ -703,11 +831,9 @@ void igb_down(struct igb_adapter *adapter)
703 wrfl(); 831 wrfl();
704 msleep(10); 832 msleep(10);
705 833
706 napi_disable(&adapter->napi); 834 for (i = 0; i < adapter->num_rx_queues; i++)
835 napi_disable(&adapter->rx_ring[i].napi);
707 836
708 if (adapter->msix_entries)
709 for (i = 0; i < adapter->num_rx_queues; i++)
710 napi_disable(&adapter->rx_ring[i].napi);
711 igb_irq_disable(adapter); 837 igb_irq_disable(adapter);
712 838
713 del_timer_sync(&adapter->watchdog_timer); 839 del_timer_sync(&adapter->watchdog_timer);
@@ -737,16 +863,23 @@ void igb_reinit_locked(struct igb_adapter *adapter)
737void igb_reset(struct igb_adapter *adapter) 863void igb_reset(struct igb_adapter *adapter)
738{ 864{
739 struct e1000_hw *hw = &adapter->hw; 865 struct e1000_hw *hw = &adapter->hw;
740 struct e1000_fc_info *fc = &adapter->hw.fc; 866 struct e1000_mac_info *mac = &hw->mac;
867 struct e1000_fc_info *fc = &hw->fc;
741 u32 pba = 0, tx_space, min_tx_space, min_rx_space; 868 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
742 u16 hwm; 869 u16 hwm;
743 870
744 /* Repartition Pba for greater than 9k mtu 871 /* Repartition Pba for greater than 9k mtu
745 * To take effect CTRL.RST is required. 872 * To take effect CTRL.RST is required.
746 */ 873 */
874 if (mac->type != e1000_82576) {
747 pba = E1000_PBA_34K; 875 pba = E1000_PBA_34K;
876 }
877 else {
878 pba = E1000_PBA_64K;
879 }
748 880
749 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) { 881 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
882 (mac->type < e1000_82576)) {
750 /* adjust PBA for jumbo frames */ 883 /* adjust PBA for jumbo frames */
751 wr32(E1000_PBA, pba); 884 wr32(E1000_PBA, pba);
752 885
@@ -785,8 +918,8 @@ void igb_reset(struct igb_adapter *adapter)
785 if (pba < min_rx_space) 918 if (pba < min_rx_space)
786 pba = min_rx_space; 919 pba = min_rx_space;
787 } 920 }
921 wr32(E1000_PBA, pba);
788 } 922 }
789 wr32(E1000_PBA, pba);
790 923
791 /* flow control settings */ 924 /* flow control settings */
792 /* The high water mark must be low enough to fit one full frame 925 /* The high water mark must be low enough to fit one full frame
@@ -795,10 +928,15 @@ void igb_reset(struct igb_adapter *adapter)
795 * - 90% of the Rx FIFO size, or 928 * - 90% of the Rx FIFO size, or
796 * - the full Rx FIFO size minus one full frame */ 929 * - the full Rx FIFO size minus one full frame */
797 hwm = min(((pba << 10) * 9 / 10), 930 hwm = min(((pba << 10) * 9 / 10),
798 ((pba << 10) - adapter->max_frame_size)); 931 ((pba << 10) - 2 * adapter->max_frame_size));
799 932
800 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ 933 if (mac->type < e1000_82576) {
801 fc->low_water = fc->high_water - 8; 934 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
935 fc->low_water = fc->high_water - 8;
936 } else {
937 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
938 fc->low_water = fc->high_water - 16;
939 }
802 fc->pause_time = 0xFFFF; 940 fc->pause_time = 0xFFFF;
803 fc->send_xon = 1; 941 fc->send_xon = 1;
804 fc->type = fc->original_type; 942 fc->type = fc->original_type;
@@ -821,6 +959,21 @@ void igb_reset(struct igb_adapter *adapter)
821} 959}
822 960
823/** 961/**
962 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
963 * @pdev: PCI device information struct
964 *
965 * Returns true if an adapter needs ioport resources
966 **/
967static int igb_is_need_ioport(struct pci_dev *pdev)
968{
969 switch (pdev->device) {
970 /* Currently there are no adapters that need ioport resources */
971 default:
972 return false;
973 }
974}
975
976/**
824 * igb_probe - Device Initialization Routine 977 * igb_probe - Device Initialization Routine
825 * @pdev: PCI device information struct 978 * @pdev: PCI device information struct
826 * @ent: entry in igb_pci_tbl 979 * @ent: entry in igb_pci_tbl
@@ -839,13 +992,21 @@ static int __devinit igb_probe(struct pci_dev *pdev,
839 struct e1000_hw *hw; 992 struct e1000_hw *hw;
840 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 993 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
841 unsigned long mmio_start, mmio_len; 994 unsigned long mmio_start, mmio_len;
842 static int cards_found;
843 int i, err, pci_using_dac; 995 int i, err, pci_using_dac;
844 u16 eeprom_data = 0; 996 u16 eeprom_data = 0;
845 u16 eeprom_apme_mask = IGB_EEPROM_APME; 997 u16 eeprom_apme_mask = IGB_EEPROM_APME;
846 u32 part_num; 998 u32 part_num;
999 int bars, need_ioport;
847 1000
848 err = pci_enable_device(pdev); 1001 /* do not allocate ioport bars when not needed */
1002 need_ioport = igb_is_need_ioport(pdev);
1003 if (need_ioport) {
1004 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1005 err = pci_enable_device(pdev);
1006 } else {
1007 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1008 err = pci_enable_device_mem(pdev);
1009 }
849 if (err) 1010 if (err)
850 return err; 1011 return err;
851 1012
@@ -867,7 +1028,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
867 } 1028 }
868 } 1029 }
869 1030
870 err = pci_request_regions(pdev, igb_driver_name); 1031 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
871 if (err) 1032 if (err)
872 goto err_pci_reg; 1033 goto err_pci_reg;
873 1034
@@ -875,7 +1036,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
875 pci_save_state(pdev); 1036 pci_save_state(pdev);
876 1037
877 err = -ENOMEM; 1038 err = -ENOMEM;
878 netdev = alloc_etherdev(sizeof(struct igb_adapter)); 1039 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
879 if (!netdev) 1040 if (!netdev)
880 goto err_alloc_etherdev; 1041 goto err_alloc_etherdev;
881 1042
@@ -888,6 +1049,8 @@ static int __devinit igb_probe(struct pci_dev *pdev,
888 hw = &adapter->hw; 1049 hw = &adapter->hw;
889 hw->back = adapter; 1050 hw->back = adapter;
890 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE; 1051 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1052 adapter->bars = bars;
1053 adapter->need_ioport = need_ioport;
891 1054
892 mmio_start = pci_resource_start(pdev, 0); 1055 mmio_start = pci_resource_start(pdev, 0);
893 mmio_len = pci_resource_len(pdev, 0); 1056 mmio_len = pci_resource_len(pdev, 0);
@@ -907,7 +1070,6 @@ static int __devinit igb_probe(struct pci_dev *pdev,
907 igb_set_ethtool_ops(netdev); 1070 igb_set_ethtool_ops(netdev);
908 netdev->tx_timeout = &igb_tx_timeout; 1071 netdev->tx_timeout = &igb_tx_timeout;
909 netdev->watchdog_timeo = 5 * HZ; 1072 netdev->watchdog_timeo = 5 * HZ;
910 netif_napi_add(netdev, &adapter->napi, igb_clean, 64);
911 netdev->vlan_rx_register = igb_vlan_rx_register; 1073 netdev->vlan_rx_register = igb_vlan_rx_register;
912 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid; 1074 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
913 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid; 1075 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
@@ -921,8 +1083,6 @@ static int __devinit igb_probe(struct pci_dev *pdev,
921 netdev->mem_start = mmio_start; 1083 netdev->mem_start = mmio_start;
922 netdev->mem_end = mmio_start + mmio_len; 1084 netdev->mem_end = mmio_start + mmio_len;
923 1085
924 adapter->bd_number = cards_found;
925
926 /* PCI config space info */ 1086 /* PCI config space info */
927 hw->vendor_id = pdev->vendor; 1087 hw->vendor_id = pdev->vendor;
928 hw->device_id = pdev->device; 1088 hw->device_id = pdev->device;
@@ -947,6 +1107,17 @@ static int __devinit igb_probe(struct pci_dev *pdev,
947 1107
948 igb_get_bus_info_pcie(hw); 1108 igb_get_bus_info_pcie(hw);
949 1109
1110 /* set flags */
1111 switch (hw->mac.type) {
1112 case e1000_82576:
1113 case e1000_82575:
1114 adapter->flags |= IGB_FLAG_HAS_DCA;
1115 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1116 break;
1117 default:
1118 break;
1119 }
1120
950 hw->phy.autoneg_wait_to_complete = false; 1121 hw->phy.autoneg_wait_to_complete = false;
951 hw->mac.adaptive_ifs = true; 1122 hw->mac.adaptive_ifs = true;
952 1123
@@ -968,8 +1139,17 @@ static int __devinit igb_probe(struct pci_dev *pdev,
968 NETIF_F_HW_VLAN_FILTER; 1139 NETIF_F_HW_VLAN_FILTER;
969 1140
970 netdev->features |= NETIF_F_TSO; 1141 netdev->features |= NETIF_F_TSO;
971
972 netdev->features |= NETIF_F_TSO6; 1142 netdev->features |= NETIF_F_TSO6;
1143
1144#ifdef CONFIG_IGB_LRO
1145 netdev->features |= NETIF_F_LRO;
1146#endif
1147
1148 netdev->vlan_features |= NETIF_F_TSO;
1149 netdev->vlan_features |= NETIF_F_TSO6;
1150 netdev->vlan_features |= NETIF_F_HW_CSUM;
1151 netdev->vlan_features |= NETIF_F_SG;
1152
973 if (pci_using_dac) 1153 if (pci_using_dac)
974 netdev->features |= NETIF_F_HIGHDMA; 1154 netdev->features |= NETIF_F_HIGHDMA;
975 1155
@@ -1053,11 +1233,23 @@ static int __devinit igb_probe(struct pci_dev *pdev,
1053 adapter->eeprom_wol = 0; 1233 adapter->eeprom_wol = 0;
1054 break; 1234 break;
1055 case E1000_DEV_ID_82575EB_FIBER_SERDES: 1235 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1236 case E1000_DEV_ID_82576_FIBER:
1237 case E1000_DEV_ID_82576_SERDES:
1056 /* Wake events only supported on port A for dual fiber 1238 /* Wake events only supported on port A for dual fiber
1057 * regardless of eeprom setting */ 1239 * regardless of eeprom setting */
1058 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 1240 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1059 adapter->eeprom_wol = 0; 1241 adapter->eeprom_wol = 0;
1060 break; 1242 break;
1243 case E1000_DEV_ID_82576_QUAD_COPPER:
1244 /* if quad port adapter, disable WoL on all but port A */
1245 if (global_quad_port_a != 0)
1246 adapter->eeprom_wol = 0;
1247 else
1248 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1249 /* Reset for multiple quad port adapters */
1250 if (++global_quad_port_a == 4)
1251 global_quad_port_a = 0;
1252 break;
1061 } 1253 }
1062 1254
1063 /* initialize the wol settings based on the eeprom settings */ 1255 /* initialize the wol settings based on the eeprom settings */
@@ -1072,13 +1264,25 @@ static int __devinit igb_probe(struct pci_dev *pdev,
1072 1264
1073 /* tell the stack to leave us alone until igb_open() is called */ 1265 /* tell the stack to leave us alone until igb_open() is called */
1074 netif_carrier_off(netdev); 1266 netif_carrier_off(netdev);
1075 netif_stop_queue(netdev); 1267 netif_tx_stop_all_queues(netdev);
1076 1268
1077 strcpy(netdev->name, "eth%d"); 1269 strcpy(netdev->name, "eth%d");
1078 err = register_netdev(netdev); 1270 err = register_netdev(netdev);
1079 if (err) 1271 if (err)
1080 goto err_register; 1272 goto err_register;
1081 1273
1274#ifdef CONFIG_DCA
1275 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1276 (dca_add_requester(&pdev->dev) == 0)) {
1277 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1278 dev_info(&pdev->dev, "DCA enabled\n");
1279 /* Always use CB2 mode, difference is masked
1280 * in the CB driver. */
1281 wr32(E1000_DCA_CTRL, 2);
1282 igb_setup_dca(adapter);
1283 }
1284#endif
1285
1082 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 1286 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1083 /* print bus type/speed/width info */ 1287 /* print bus type/speed/width info */
1084 dev_info(&pdev->dev, 1288 dev_info(&pdev->dev,
@@ -1099,10 +1303,9 @@ static int __devinit igb_probe(struct pci_dev *pdev,
1099 dev_info(&pdev->dev, 1303 dev_info(&pdev->dev,
1100 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 1304 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1101 adapter->msix_entries ? "MSI-X" : 1305 adapter->msix_entries ? "MSI-X" :
1102 adapter->msi_enabled ? "MSI" : "legacy", 1306 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1103 adapter->num_rx_queues, adapter->num_tx_queues); 1307 adapter->num_rx_queues, adapter->num_tx_queues);
1104 1308
1105 cards_found++;
1106 return 0; 1309 return 0;
1107 1310
1108err_register: 1311err_register:
@@ -1115,15 +1318,14 @@ err_eeprom:
1115 iounmap(hw->flash_address); 1318 iounmap(hw->flash_address);
1116 1319
1117 igb_remove_device(hw); 1320 igb_remove_device(hw);
1118 kfree(adapter->tx_ring); 1321 igb_free_queues(adapter);
1119 kfree(adapter->rx_ring);
1120err_sw_init: 1322err_sw_init:
1121err_hw_init: 1323err_hw_init:
1122 iounmap(hw->hw_addr); 1324 iounmap(hw->hw_addr);
1123err_ioremap: 1325err_ioremap:
1124 free_netdev(netdev); 1326 free_netdev(netdev);
1125err_alloc_etherdev: 1327err_alloc_etherdev:
1126 pci_release_regions(pdev); 1328 pci_release_selected_regions(pdev, bars);
1127err_pci_reg: 1329err_pci_reg:
1128err_dma: 1330err_dma:
1129 pci_disable_device(pdev); 1331 pci_disable_device(pdev);
@@ -1143,6 +1345,9 @@ static void __devexit igb_remove(struct pci_dev *pdev)
1143{ 1345{
1144 struct net_device *netdev = pci_get_drvdata(pdev); 1346 struct net_device *netdev = pci_get_drvdata(pdev);
1145 struct igb_adapter *adapter = netdev_priv(netdev); 1347 struct igb_adapter *adapter = netdev_priv(netdev);
1348#ifdef CONFIG_DCA
1349 struct e1000_hw *hw = &adapter->hw;
1350#endif
1146 1351
1147 /* flush_scheduled work may reschedule our watchdog task, so 1352 /* flush_scheduled work may reschedule our watchdog task, so
1148 * explicitly disable watchdog tasks from being rescheduled */ 1353 * explicitly disable watchdog tasks from being rescheduled */
@@ -1152,6 +1357,15 @@ static void __devexit igb_remove(struct pci_dev *pdev)
1152 1357
1153 flush_scheduled_work(); 1358 flush_scheduled_work();
1154 1359
1360#ifdef CONFIG_DCA
1361 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1362 dev_info(&pdev->dev, "DCA disabled\n");
1363 dca_remove_requester(&pdev->dev);
1364 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1365 wr32(E1000_DCA_CTRL, 1);
1366 }
1367#endif
1368
1155 /* Release control of h/w to f/w. If f/w is AMT enabled, this 1369 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1156 * would have already happened in close and is redundant. */ 1370 * would have already happened in close and is redundant. */
1157 igb_release_hw_control(adapter); 1371 igb_release_hw_control(adapter);
@@ -1164,13 +1378,12 @@ static void __devexit igb_remove(struct pci_dev *pdev)
1164 igb_remove_device(&adapter->hw); 1378 igb_remove_device(&adapter->hw);
1165 igb_reset_interrupt_capability(adapter); 1379 igb_reset_interrupt_capability(adapter);
1166 1380
1167 kfree(adapter->tx_ring); 1381 igb_free_queues(adapter);
1168 kfree(adapter->rx_ring);
1169 1382
1170 iounmap(adapter->hw.hw_addr); 1383 iounmap(adapter->hw.hw_addr);
1171 if (adapter->hw.flash_address) 1384 if (adapter->hw.flash_address)
1172 iounmap(adapter->hw.flash_address); 1385 iounmap(adapter->hw.flash_address);
1173 pci_release_regions(pdev); 1386 pci_release_selected_regions(pdev, adapter->bars);
1174 1387
1175 free_netdev(netdev); 1388 free_netdev(netdev);
1176 1389
@@ -1200,9 +1413,11 @@ static int __devinit igb_sw_init(struct igb_adapter *adapter)
1200 1413
1201 /* Number of supported queues. */ 1414 /* Number of supported queues. */
1202 /* Having more queues than CPUs doesn't make sense. */ 1415 /* Having more queues than CPUs doesn't make sense. */
1203 adapter->num_tx_queues = 1; 1416 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
1204 adapter->num_rx_queues = min(IGB_MAX_RX_QUEUES, num_online_cpus()); 1417 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
1205 1418
1419 /* This call may decrease the number of queues depending on
1420 * interrupt mode. */
1206 igb_set_interrupt_capability(adapter); 1421 igb_set_interrupt_capability(adapter);
1207 1422
1208 if (igb_alloc_queues(adapter)) { 1423 if (igb_alloc_queues(adapter)) {
@@ -1270,15 +1485,16 @@ static int igb_open(struct net_device *netdev)
1270 /* From here on the code is the same as igb_up() */ 1485 /* From here on the code is the same as igb_up() */
1271 clear_bit(__IGB_DOWN, &adapter->state); 1486 clear_bit(__IGB_DOWN, &adapter->state);
1272 1487
1273 napi_enable(&adapter->napi); 1488 for (i = 0; i < adapter->num_rx_queues; i++)
1274 if (adapter->msix_entries) 1489 napi_enable(&adapter->rx_ring[i].napi);
1275 for (i = 0; i < adapter->num_rx_queues; i++)
1276 napi_enable(&adapter->rx_ring[i].napi);
1277
1278 igb_irq_enable(adapter);
1279 1490
1280 /* Clear any pending interrupts. */ 1491 /* Clear any pending interrupts. */
1281 rd32(E1000_ICR); 1492 rd32(E1000_ICR);
1493
1494 igb_irq_enable(adapter);
1495
1496 netif_tx_start_all_queues(netdev);
1497
1282 /* Fire a link status change interrupt to start the watchdog. */ 1498 /* Fire a link status change interrupt to start the watchdog. */
1283 wr32(E1000_ICS, E1000_ICS_LSC); 1499 wr32(E1000_ICS, E1000_ICS_LSC);
1284 1500
@@ -1364,8 +1580,6 @@ int igb_setup_tx_resources(struct igb_adapter *adapter,
1364 tx_ring->adapter = adapter; 1580 tx_ring->adapter = adapter;
1365 tx_ring->next_to_use = 0; 1581 tx_ring->next_to_use = 0;
1366 tx_ring->next_to_clean = 0; 1582 tx_ring->next_to_clean = 0;
1367 spin_lock_init(&tx_ring->tx_clean_lock);
1368 spin_lock_init(&tx_ring->tx_lock);
1369 return 0; 1583 return 0;
1370 1584
1371err: 1585err:
@@ -1385,6 +1599,7 @@ err:
1385static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 1599static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1386{ 1600{
1387 int i, err = 0; 1601 int i, err = 0;
1602 int r_idx;
1388 1603
1389 for (i = 0; i < adapter->num_tx_queues; i++) { 1604 for (i = 0; i < adapter->num_tx_queues; i++) {
1390 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]); 1605 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
@@ -1392,12 +1607,15 @@ static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1392 dev_err(&adapter->pdev->dev, 1607 dev_err(&adapter->pdev->dev,
1393 "Allocation for Tx Queue %u failed\n", i); 1608 "Allocation for Tx Queue %u failed\n", i);
1394 for (i--; i >= 0; i--) 1609 for (i--; i >= 0; i--)
1395 igb_free_tx_resources(adapter, 1610 igb_free_tx_resources(&adapter->tx_ring[i]);
1396 &adapter->tx_ring[i]);
1397 break; 1611 break;
1398 } 1612 }
1399 } 1613 }
1400 1614
1615 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1616 r_idx = i % adapter->num_tx_queues;
1617 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1618 }
1401 return err; 1619 return err;
1402} 1620}
1403 1621
@@ -1484,6 +1702,14 @@ int igb_setup_rx_resources(struct igb_adapter *adapter,
1484 struct pci_dev *pdev = adapter->pdev; 1702 struct pci_dev *pdev = adapter->pdev;
1485 int size, desc_len; 1703 int size, desc_len;
1486 1704
1705#ifdef CONFIG_IGB_LRO
1706 size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1707 rx_ring->lro_mgr.lro_arr = vmalloc(size);
1708 if (!rx_ring->lro_mgr.lro_arr)
1709 goto err;
1710 memset(rx_ring->lro_mgr.lro_arr, 0, size);
1711#endif
1712
1487 size = sizeof(struct igb_buffer) * rx_ring->count; 1713 size = sizeof(struct igb_buffer) * rx_ring->count;
1488 rx_ring->buffer_info = vmalloc(size); 1714 rx_ring->buffer_info = vmalloc(size);
1489 if (!rx_ring->buffer_info) 1715 if (!rx_ring->buffer_info)
@@ -1504,15 +1730,16 @@ int igb_setup_rx_resources(struct igb_adapter *adapter,
1504 1730
1505 rx_ring->next_to_clean = 0; 1731 rx_ring->next_to_clean = 0;
1506 rx_ring->next_to_use = 0; 1732 rx_ring->next_to_use = 0;
1507 rx_ring->pending_skb = NULL;
1508 1733
1509 rx_ring->adapter = adapter; 1734 rx_ring->adapter = adapter;
1510 /* FIXME: do we want to setup ring->napi->poll here? */
1511 rx_ring->napi.poll = adapter->napi.poll;
1512 1735
1513 return 0; 1736 return 0;
1514 1737
1515err: 1738err:
1739#ifdef CONFIG_IGB_LRO
1740 vfree(rx_ring->lro_mgr.lro_arr);
1741 rx_ring->lro_mgr.lro_arr = NULL;
1742#endif
1516 vfree(rx_ring->buffer_info); 1743 vfree(rx_ring->buffer_info);
1517 dev_err(&adapter->pdev->dev, "Unable to allocate memory for " 1744 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1518 "the receive descriptor ring\n"); 1745 "the receive descriptor ring\n");
@@ -1536,8 +1763,7 @@ static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1536 dev_err(&adapter->pdev->dev, 1763 dev_err(&adapter->pdev->dev,
1537 "Allocation for Rx Queue %u failed\n", i); 1764 "Allocation for Rx Queue %u failed\n", i);
1538 for (i--; i >= 0; i--) 1765 for (i--; i >= 0; i--)
1539 igb_free_rx_resources(adapter, 1766 igb_free_rx_resources(&adapter->rx_ring[i]);
1540 &adapter->rx_ring[i]);
1541 break; 1767 break;
1542 } 1768 }
1543 } 1769 }
@@ -1564,10 +1790,12 @@ static void igb_setup_rctl(struct igb_adapter *adapter)
1564 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 1790 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1565 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 1791 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1566 1792
1567 /* disable the stripping of CRC because it breaks 1793 /*
1568 * BMC firmware connected over SMBUS 1794 * enable stripping of CRC. It's unlikely this will break BMC
1569 rctl |= E1000_RCTL_SECRC; 1795 * redirection as it did with e1000. Newer features require
1796 * that the HW strips the CRC.
1570 */ 1797 */
1798 rctl |= E1000_RCTL_SECRC;
1571 1799
1572 rctl &= ~E1000_RCTL_SBP; 1800 rctl &= ~E1000_RCTL_SBP;
1573 1801
@@ -1597,15 +1825,6 @@ static void igb_setup_rctl(struct igb_adapter *adapter)
1597 rctl |= E1000_RCTL_SZ_2048; 1825 rctl |= E1000_RCTL_SZ_2048;
1598 rctl &= ~E1000_RCTL_BSEX; 1826 rctl &= ~E1000_RCTL_BSEX;
1599 break; 1827 break;
1600 case IGB_RXBUFFER_4096:
1601 rctl |= E1000_RCTL_SZ_4096;
1602 break;
1603 case IGB_RXBUFFER_8192:
1604 rctl |= E1000_RCTL_SZ_8192;
1605 break;
1606 case IGB_RXBUFFER_16384:
1607 rctl |= E1000_RCTL_SZ_16384;
1608 break;
1609 } 1828 }
1610 } else { 1829 } else {
1611 rctl &= ~E1000_RCTL_BSEX; 1830 rctl &= ~E1000_RCTL_BSEX;
@@ -1623,10 +1842,8 @@ static void igb_setup_rctl(struct igb_adapter *adapter)
1623 * so only enable packet split for jumbo frames */ 1842 * so only enable packet split for jumbo frames */
1624 if (rctl & E1000_RCTL_LPE) { 1843 if (rctl & E1000_RCTL_LPE) {
1625 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128; 1844 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1626 srrctl = adapter->rx_ps_hdr_size << 1845 srrctl |= adapter->rx_ps_hdr_size <<
1627 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 1846 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1628 /* buffer size is ALWAYS one page */
1629 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1630 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; 1847 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1631 } else { 1848 } else {
1632 adapter->rx_ps_hdr_size = 0; 1849 adapter->rx_ps_hdr_size = 0;
@@ -1660,8 +1877,7 @@ static void igb_configure_rx(struct igb_adapter *adapter)
1660 mdelay(10); 1877 mdelay(10);
1661 1878
1662 if (adapter->itr_setting > 3) 1879 if (adapter->itr_setting > 3)
1663 wr32(E1000_ITR, 1880 wr32(E1000_ITR, adapter->itr);
1664 1000000000 / (adapter->itr * 256));
1665 1881
1666 /* Setup the HW Rx Head and Tail Descriptor Pointers and 1882 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1667 * the Base and Length of the Rx Descriptor Ring */ 1883 * the Base and Length of the Rx Descriptor Ring */
@@ -1686,6 +1902,16 @@ static void igb_configure_rx(struct igb_adapter *adapter)
1686 rxdctl |= IGB_RX_HTHRESH << 8; 1902 rxdctl |= IGB_RX_HTHRESH << 8;
1687 rxdctl |= IGB_RX_WTHRESH << 16; 1903 rxdctl |= IGB_RX_WTHRESH << 16;
1688 wr32(E1000_RXDCTL(i), rxdctl); 1904 wr32(E1000_RXDCTL(i), rxdctl);
1905#ifdef CONFIG_IGB_LRO
1906 /* Intitial LRO Settings */
1907 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1908 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1909 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1910 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1911 ring->lro_mgr.dev = adapter->netdev;
1912 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1913 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1914#endif
1689 } 1915 }
1690 1916
1691 if (adapter->num_rx_queues > 1) { 1917 if (adapter->num_rx_queues > 1) {
@@ -1699,7 +1925,10 @@ static void igb_configure_rx(struct igb_adapter *adapter)
1699 1925
1700 get_random_bytes(&random[0], 40); 1926 get_random_bytes(&random[0], 40);
1701 1927
1702 shift = 6; 1928 if (hw->mac.type >= e1000_82576)
1929 shift = 0;
1930 else
1931 shift = 6;
1703 for (j = 0; j < (32 * 4); j++) { 1932 for (j = 0; j < (32 * 4); j++) {
1704 reta.bytes[j & 3] = 1933 reta.bytes[j & 3] =
1705 (j % adapter->num_rx_queues) << shift; 1934 (j % adapter->num_rx_queues) << shift;
@@ -1765,12 +1994,11 @@ static void igb_configure_rx(struct igb_adapter *adapter)
1765 * 1994 *
1766 * Free all transmit software resources 1995 * Free all transmit software resources
1767 **/ 1996 **/
1768static void igb_free_tx_resources(struct igb_adapter *adapter, 1997static void igb_free_tx_resources(struct igb_ring *tx_ring)
1769 struct igb_ring *tx_ring)
1770{ 1998{
1771 struct pci_dev *pdev = adapter->pdev; 1999 struct pci_dev *pdev = tx_ring->adapter->pdev;
1772 2000
1773 igb_clean_tx_ring(adapter, tx_ring); 2001 igb_clean_tx_ring(tx_ring);
1774 2002
1775 vfree(tx_ring->buffer_info); 2003 vfree(tx_ring->buffer_info);
1776 tx_ring->buffer_info = NULL; 2004 tx_ring->buffer_info = NULL;
@@ -1791,7 +2019,7 @@ static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1791 int i; 2019 int i;
1792 2020
1793 for (i = 0; i < adapter->num_tx_queues; i++) 2021 for (i = 0; i < adapter->num_tx_queues; i++)
1794 igb_free_tx_resources(adapter, &adapter->tx_ring[i]); 2022 igb_free_tx_resources(&adapter->tx_ring[i]);
1795} 2023}
1796 2024
1797static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter, 2025static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
@@ -1817,9 +2045,9 @@ static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1817 * @adapter: board private structure 2045 * @adapter: board private structure
1818 * @tx_ring: ring to be cleaned 2046 * @tx_ring: ring to be cleaned
1819 **/ 2047 **/
1820static void igb_clean_tx_ring(struct igb_adapter *adapter, 2048static void igb_clean_tx_ring(struct igb_ring *tx_ring)
1821 struct igb_ring *tx_ring)
1822{ 2049{
2050 struct igb_adapter *adapter = tx_ring->adapter;
1823 struct igb_buffer *buffer_info; 2051 struct igb_buffer *buffer_info;
1824 unsigned long size; 2052 unsigned long size;
1825 unsigned int i; 2053 unsigned int i;
@@ -1856,7 +2084,7 @@ static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1856 int i; 2084 int i;
1857 2085
1858 for (i = 0; i < adapter->num_tx_queues; i++) 2086 for (i = 0; i < adapter->num_tx_queues; i++)
1859 igb_clean_tx_ring(adapter, &adapter->tx_ring[i]); 2087 igb_clean_tx_ring(&adapter->tx_ring[i]);
1860} 2088}
1861 2089
1862/** 2090/**
@@ -1866,16 +2094,20 @@ static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1866 * 2094 *
1867 * Free all receive software resources 2095 * Free all receive software resources
1868 **/ 2096 **/
1869static void igb_free_rx_resources(struct igb_adapter *adapter, 2097static void igb_free_rx_resources(struct igb_ring *rx_ring)
1870 struct igb_ring *rx_ring)
1871{ 2098{
1872 struct pci_dev *pdev = adapter->pdev; 2099 struct pci_dev *pdev = rx_ring->adapter->pdev;
1873 2100
1874 igb_clean_rx_ring(adapter, rx_ring); 2101 igb_clean_rx_ring(rx_ring);
1875 2102
1876 vfree(rx_ring->buffer_info); 2103 vfree(rx_ring->buffer_info);
1877 rx_ring->buffer_info = NULL; 2104 rx_ring->buffer_info = NULL;
1878 2105
2106#ifdef CONFIG_IGB_LRO
2107 vfree(rx_ring->lro_mgr.lro_arr);
2108 rx_ring->lro_mgr.lro_arr = NULL;
2109#endif
2110
1879 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); 2111 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1880 2112
1881 rx_ring->desc = NULL; 2113 rx_ring->desc = NULL;
@@ -1892,7 +2124,7 @@ static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1892 int i; 2124 int i;
1893 2125
1894 for (i = 0; i < adapter->num_rx_queues; i++) 2126 for (i = 0; i < adapter->num_rx_queues; i++)
1895 igb_free_rx_resources(adapter, &adapter->rx_ring[i]); 2127 igb_free_rx_resources(&adapter->rx_ring[i]);
1896} 2128}
1897 2129
1898/** 2130/**
@@ -1900,9 +2132,9 @@ static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1900 * @adapter: board private structure 2132 * @adapter: board private structure
1901 * @rx_ring: ring to free buffers from 2133 * @rx_ring: ring to free buffers from
1902 **/ 2134 **/
1903static void igb_clean_rx_ring(struct igb_adapter *adapter, 2135static void igb_clean_rx_ring(struct igb_ring *rx_ring)
1904 struct igb_ring *rx_ring)
1905{ 2136{
2137 struct igb_adapter *adapter = rx_ring->adapter;
1906 struct igb_buffer *buffer_info; 2138 struct igb_buffer *buffer_info;
1907 struct pci_dev *pdev = adapter->pdev; 2139 struct pci_dev *pdev = adapter->pdev;
1908 unsigned long size; 2140 unsigned long size;
@@ -1930,20 +2162,17 @@ static void igb_clean_rx_ring(struct igb_adapter *adapter,
1930 buffer_info->skb = NULL; 2162 buffer_info->skb = NULL;
1931 } 2163 }
1932 if (buffer_info->page) { 2164 if (buffer_info->page) {
1933 pci_unmap_page(pdev, buffer_info->page_dma, 2165 if (buffer_info->page_dma)
1934 PAGE_SIZE, PCI_DMA_FROMDEVICE); 2166 pci_unmap_page(pdev, buffer_info->page_dma,
2167 PAGE_SIZE / 2,
2168 PCI_DMA_FROMDEVICE);
1935 put_page(buffer_info->page); 2169 put_page(buffer_info->page);
1936 buffer_info->page = NULL; 2170 buffer_info->page = NULL;
1937 buffer_info->page_dma = 0; 2171 buffer_info->page_dma = 0;
2172 buffer_info->page_offset = 0;
1938 } 2173 }
1939 } 2174 }
1940 2175
1941 /* there also may be some cached data from a chained receive */
1942 if (rx_ring->pending_skb) {
1943 dev_kfree_skb(rx_ring->pending_skb);
1944 rx_ring->pending_skb = NULL;
1945 }
1946
1947 size = sizeof(struct igb_buffer) * rx_ring->count; 2176 size = sizeof(struct igb_buffer) * rx_ring->count;
1948 memset(rx_ring->buffer_info, 0, size); 2177 memset(rx_ring->buffer_info, 0, size);
1949 2178
@@ -1966,7 +2195,7 @@ static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
1966 int i; 2195 int i;
1967 2196
1968 for (i = 0; i < adapter->num_rx_queues; i++) 2197 for (i = 0; i < adapter->num_rx_queues; i++)
1969 igb_clean_rx_ring(adapter, &adapter->rx_ring[i]); 2198 igb_clean_rx_ring(&adapter->rx_ring[i]);
1970} 2199}
1971 2200
1972/** 2201/**
@@ -2015,19 +2244,22 @@ static void igb_set_multi(struct net_device *netdev)
2015 2244
2016 rctl = rd32(E1000_RCTL); 2245 rctl = rd32(E1000_RCTL);
2017 2246
2018 if (netdev->flags & IFF_PROMISC) 2247 if (netdev->flags & IFF_PROMISC) {
2019 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2248 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2020 else if (netdev->flags & IFF_ALLMULTI) { 2249 rctl &= ~E1000_RCTL_VFE;
2021 rctl |= E1000_RCTL_MPE; 2250 } else {
2022 rctl &= ~E1000_RCTL_UPE; 2251 if (netdev->flags & IFF_ALLMULTI) {
2023 } else 2252 rctl |= E1000_RCTL_MPE;
2024 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 2253 rctl &= ~E1000_RCTL_UPE;
2025 2254 } else
2255 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2256 rctl |= E1000_RCTL_VFE;
2257 }
2026 wr32(E1000_RCTL, rctl); 2258 wr32(E1000_RCTL, rctl);
2027 2259
2028 if (!netdev->mc_count) { 2260 if (!netdev->mc_count) {
2029 /* nothing to program, so clear mc list */ 2261 /* nothing to program, so clear mc list */
2030 igb_update_mc_addr_list(hw, NULL, 0, 1, 2262 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
2031 mac->rar_entry_count); 2263 mac->rar_entry_count);
2032 return; 2264 return;
2033 } 2265 }
@@ -2045,7 +2277,8 @@ static void igb_set_multi(struct net_device *netdev)
2045 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); 2277 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2046 mc_ptr = mc_ptr->next; 2278 mc_ptr = mc_ptr->next;
2047 } 2279 }
2048 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count); 2280 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2281 mac->rar_entry_count);
2049 kfree(mta_list); 2282 kfree(mta_list);
2050} 2283}
2051 2284
@@ -2135,7 +2368,7 @@ static void igb_watchdog_task(struct work_struct *work)
2135 } 2368 }
2136 2369
2137 netif_carrier_on(netdev); 2370 netif_carrier_on(netdev);
2138 netif_wake_queue(netdev); 2371 netif_tx_wake_all_queues(netdev);
2139 2372
2140 if (!test_bit(__IGB_DOWN, &adapter->state)) 2373 if (!test_bit(__IGB_DOWN, &adapter->state))
2141 mod_timer(&adapter->phy_info_timer, 2374 mod_timer(&adapter->phy_info_timer,
@@ -2147,7 +2380,7 @@ static void igb_watchdog_task(struct work_struct *work)
2147 adapter->link_duplex = 0; 2380 adapter->link_duplex = 0;
2148 dev_info(&adapter->pdev->dev, "NIC Link is Down\n"); 2381 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2149 netif_carrier_off(netdev); 2382 netif_carrier_off(netdev);
2150 netif_stop_queue(netdev); 2383 netif_tx_stop_all_queues(netdev);
2151 if (!test_bit(__IGB_DOWN, &adapter->state)) 2384 if (!test_bit(__IGB_DOWN, &adapter->state))
2152 mod_timer(&adapter->phy_info_timer, 2385 mod_timer(&adapter->phy_info_timer,
2153 round_jiffies(jiffies + 2 * HZ)); 2386 round_jiffies(jiffies + 2 * HZ));
@@ -2200,38 +2433,60 @@ enum latency_range {
2200}; 2433};
2201 2434
2202 2435
2203static void igb_lower_rx_eitr(struct igb_adapter *adapter, 2436/**
2204 struct igb_ring *rx_ring) 2437 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2438 *
2439 * Stores a new ITR value based on strictly on packet size. This
2440 * algorithm is less sophisticated than that used in igb_update_itr,
2441 * due to the difficulty of synchronizing statistics across multiple
2442 * receive rings. The divisors and thresholds used by this fuction
2443 * were determined based on theoretical maximum wire speed and testing
2444 * data, in order to minimize response time while increasing bulk
2445 * throughput.
2446 * This functionality is controlled by the InterruptThrottleRate module
2447 * parameter (see igb_param.c)
2448 * NOTE: This function is called only when operating in a multiqueue
2449 * receive environment.
2450 * @rx_ring: pointer to ring
2451 **/
2452static void igb_update_ring_itr(struct igb_ring *rx_ring)
2205{ 2453{
2206 struct e1000_hw *hw = &adapter->hw; 2454 int new_val = rx_ring->itr_val;
2207 int new_val; 2455 int avg_wire_size = 0;
2456 struct igb_adapter *adapter = rx_ring->adapter;
2208 2457
2209 new_val = rx_ring->itr_val / 2; 2458 if (!rx_ring->total_packets)
2210 if (new_val < IGB_MIN_DYN_ITR) 2459 goto clear_counts; /* no packets, so don't do anything */
2211 new_val = IGB_MIN_DYN_ITR;
2212 2460
2213 if (new_val != rx_ring->itr_val) { 2461 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2214 rx_ring->itr_val = new_val; 2462 * ints/sec - ITR timer value of 120 ticks.
2215 wr32(rx_ring->itr_register, 2463 */
2216 1000000000 / (new_val * 256)); 2464 if (adapter->link_speed != SPEED_1000) {
2465 new_val = 120;
2466 goto set_itr_val;
2217 } 2467 }
2218} 2468 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2219 2469
2220static void igb_raise_rx_eitr(struct igb_adapter *adapter, 2470 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2221 struct igb_ring *rx_ring) 2471 avg_wire_size += 24;
2222{
2223 struct e1000_hw *hw = &adapter->hw;
2224 int new_val;
2225 2472
2226 new_val = rx_ring->itr_val * 2; 2473 /* Don't starve jumbo frames */
2227 if (new_val > IGB_MAX_DYN_ITR) 2474 avg_wire_size = min(avg_wire_size, 3000);
2228 new_val = IGB_MAX_DYN_ITR;
2229 2475
2476 /* Give a little boost to mid-size frames */
2477 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2478 new_val = avg_wire_size / 3;
2479 else
2480 new_val = avg_wire_size / 2;
2481
2482set_itr_val:
2230 if (new_val != rx_ring->itr_val) { 2483 if (new_val != rx_ring->itr_val) {
2231 rx_ring->itr_val = new_val; 2484 rx_ring->itr_val = new_val;
2232 wr32(rx_ring->itr_register, 2485 rx_ring->set_itr = 1;
2233 1000000000 / (new_val * 256));
2234 } 2486 }
2487clear_counts:
2488 rx_ring->total_bytes = 0;
2489 rx_ring->total_packets = 0;
2235} 2490}
2236 2491
2237/** 2492/**
@@ -2298,8 +2553,7 @@ update_itr_done:
2298 return retval; 2553 return retval;
2299} 2554}
2300 2555
2301static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register, 2556static void igb_set_itr(struct igb_adapter *adapter)
2302 int rx_only)
2303{ 2557{
2304 u16 current_itr; 2558 u16 current_itr;
2305 u32 new_itr = adapter->itr; 2559 u32 new_itr = adapter->itr;
@@ -2315,26 +2569,23 @@ static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2315 adapter->rx_itr, 2569 adapter->rx_itr,
2316 adapter->rx_ring->total_packets, 2570 adapter->rx_ring->total_packets,
2317 adapter->rx_ring->total_bytes); 2571 adapter->rx_ring->total_bytes);
2318 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2319 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2320 adapter->rx_itr = low_latency;
2321 2572
2322 if (!rx_only) { 2573 if (adapter->rx_ring->buddy) {
2323 adapter->tx_itr = igb_update_itr(adapter, 2574 adapter->tx_itr = igb_update_itr(adapter,
2324 adapter->tx_itr, 2575 adapter->tx_itr,
2325 adapter->tx_ring->total_packets, 2576 adapter->tx_ring->total_packets,
2326 adapter->tx_ring->total_bytes); 2577 adapter->tx_ring->total_bytes);
2327 /* conservative mode (itr 3) eliminates the
2328 * lowest_latency setting */
2329 if (adapter->itr_setting == 3 &&
2330 adapter->tx_itr == lowest_latency)
2331 adapter->tx_itr = low_latency;
2332 2578
2333 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2579 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2334 } else { 2580 } else {
2335 current_itr = adapter->rx_itr; 2581 current_itr = adapter->rx_itr;
2336 } 2582 }
2337 2583
2584 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2585 if (adapter->itr_setting == 3 &&
2586 current_itr == lowest_latency)
2587 current_itr = low_latency;
2588
2338 switch (current_itr) { 2589 switch (current_itr) {
2339 /* counts and packets in update_itr are dependent on these numbers */ 2590 /* counts and packets in update_itr are dependent on these numbers */
2340 case lowest_latency: 2591 case lowest_latency:
@@ -2351,6 +2602,13 @@ static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2351 } 2602 }
2352 2603
2353set_itr_now: 2604set_itr_now:
2605 adapter->rx_ring->total_bytes = 0;
2606 adapter->rx_ring->total_packets = 0;
2607 if (adapter->rx_ring->buddy) {
2608 adapter->rx_ring->buddy->total_bytes = 0;
2609 adapter->rx_ring->buddy->total_packets = 0;
2610 }
2611
2354 if (new_itr != adapter->itr) { 2612 if (new_itr != adapter->itr) {
2355 /* this attempts to bias the interrupt rate towards Bulk 2613 /* this attempts to bias the interrupt rate towards Bulk
2356 * by adding intermediate steps when interrupt rate is 2614 * by adding intermediate steps when interrupt rate is
@@ -2365,7 +2623,8 @@ set_itr_now:
2365 * ends up being correct. 2623 * ends up being correct.
2366 */ 2624 */
2367 adapter->itr = new_itr; 2625 adapter->itr = new_itr;
2368 adapter->set_itr = 1; 2626 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2627 adapter->rx_ring->set_itr = 1;
2369 } 2628 }
2370 2629
2371 return; 2630 return;
@@ -2441,9 +2700,9 @@ static inline int igb_tso_adv(struct igb_adapter *adapter,
2441 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT); 2700 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2442 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); 2701 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2443 2702
2444 /* Context index must be unique per ring. Luckily, so is the interrupt 2703 /* Context index must be unique per ring. */
2445 * mask value. */ 2704 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2446 mss_l4len_idx |= tx_ring->eims_value >> 4; 2705 mss_l4len_idx |= tx_ring->queue_index << 4;
2447 2706
2448 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 2707 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2449 context_desc->seqnum_seed = 0; 2708 context_desc->seqnum_seed = 0;
@@ -2507,8 +2766,9 @@ static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2507 2766
2508 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); 2767 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2509 context_desc->seqnum_seed = 0; 2768 context_desc->seqnum_seed = 0;
2510 context_desc->mss_l4len_idx = 2769 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2511 cpu_to_le32(tx_ring->eims_value >> 4); 2770 context_desc->mss_l4len_idx =
2771 cpu_to_le32(tx_ring->queue_index << 4);
2512 2772
2513 buffer_info->time_stamp = jiffies; 2773 buffer_info->time_stamp = jiffies;
2514 buffer_info->dma = 0; 2774 buffer_info->dma = 0;
@@ -2609,9 +2869,10 @@ static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2609 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 2869 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2610 } 2870 }
2611 2871
2612 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO | 2872 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2613 IGB_TX_FLAGS_VLAN)) 2873 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2614 olinfo_status |= tx_ring->eims_value >> 4; 2874 IGB_TX_FLAGS_VLAN)))
2875 olinfo_status |= tx_ring->queue_index << 4;
2615 2876
2616 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT); 2877 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2617 2878
@@ -2647,7 +2908,8 @@ static int __igb_maybe_stop_tx(struct net_device *netdev,
2647{ 2908{
2648 struct igb_adapter *adapter = netdev_priv(netdev); 2909 struct igb_adapter *adapter = netdev_priv(netdev);
2649 2910
2650 netif_stop_queue(netdev); 2911 netif_stop_subqueue(netdev, tx_ring->queue_index);
2912
2651 /* Herbert's original patch had: 2913 /* Herbert's original patch had:
2652 * smp_mb__after_netif_stop_queue(); 2914 * smp_mb__after_netif_stop_queue();
2653 * but since that doesn't exist yet, just open code it. */ 2915 * but since that doesn't exist yet, just open code it. */
@@ -2659,7 +2921,7 @@ static int __igb_maybe_stop_tx(struct net_device *netdev,
2659 return -EBUSY; 2921 return -EBUSY;
2660 2922
2661 /* A reprieve! */ 2923 /* A reprieve! */
2662 netif_start_queue(netdev); 2924 netif_wake_subqueue(netdev, tx_ring->queue_index);
2663 ++adapter->restart_queue; 2925 ++adapter->restart_queue;
2664 return 0; 2926 return 0;
2665} 2927}
@@ -2681,7 +2943,6 @@ static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2681 struct igb_adapter *adapter = netdev_priv(netdev); 2943 struct igb_adapter *adapter = netdev_priv(netdev);
2682 unsigned int tx_flags = 0; 2944 unsigned int tx_flags = 0;
2683 unsigned int len; 2945 unsigned int len;
2684 unsigned long irq_flags;
2685 u8 hdr_len = 0; 2946 u8 hdr_len = 0;
2686 int tso = 0; 2947 int tso = 0;
2687 2948
@@ -2697,10 +2958,6 @@ static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2697 return NETDEV_TX_OK; 2958 return NETDEV_TX_OK;
2698 } 2959 }
2699 2960
2700 if (!spin_trylock_irqsave(&tx_ring->tx_lock, irq_flags))
2701 /* Collision - tell upper layer to requeue */
2702 return NETDEV_TX_LOCKED;
2703
2704 /* need: 1 descriptor per page, 2961 /* need: 1 descriptor per page,
2705 * + 2 desc gap to keep tail from touching head, 2962 * + 2 desc gap to keep tail from touching head,
2706 * + 1 desc for skb->data, 2963 * + 1 desc for skb->data,
@@ -2708,21 +2965,23 @@ static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2708 * otherwise try next time */ 2965 * otherwise try next time */
2709 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) { 2966 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2710 /* this is a hard error */ 2967 /* this is a hard error */
2711 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2712 return NETDEV_TX_BUSY; 2968 return NETDEV_TX_BUSY;
2713 } 2969 }
2970 skb_orphan(skb);
2714 2971
2715 if (adapter->vlgrp && vlan_tx_tag_present(skb)) { 2972 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2716 tx_flags |= IGB_TX_FLAGS_VLAN; 2973 tx_flags |= IGB_TX_FLAGS_VLAN;
2717 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 2974 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2718 } 2975 }
2719 2976
2977 if (skb->protocol == htons(ETH_P_IP))
2978 tx_flags |= IGB_TX_FLAGS_IPV4;
2979
2720 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags, 2980 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2721 &hdr_len) : 0; 2981 &hdr_len) : 0;
2722 2982
2723 if (tso < 0) { 2983 if (tso < 0) {
2724 dev_kfree_skb_any(skb); 2984 dev_kfree_skb_any(skb);
2725 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2726 return NETDEV_TX_OK; 2985 return NETDEV_TX_OK;
2727 } 2986 }
2728 2987
@@ -2732,9 +2991,6 @@ static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2732 if (skb->ip_summed == CHECKSUM_PARTIAL) 2991 if (skb->ip_summed == CHECKSUM_PARTIAL)
2733 tx_flags |= IGB_TX_FLAGS_CSUM; 2992 tx_flags |= IGB_TX_FLAGS_CSUM;
2734 2993
2735 if (skb->protocol == htons(ETH_P_IP))
2736 tx_flags |= IGB_TX_FLAGS_IPV4;
2737
2738 igb_tx_queue_adv(adapter, tx_ring, tx_flags, 2994 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2739 igb_tx_map_adv(adapter, tx_ring, skb), 2995 igb_tx_map_adv(adapter, tx_ring, skb),
2740 skb->len, hdr_len); 2996 skb->len, hdr_len);
@@ -2744,14 +3000,17 @@ static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2744 /* Make sure there is space in the ring for the next send. */ 3000 /* Make sure there is space in the ring for the next send. */
2745 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4); 3001 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2746 3002
2747 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2748 return NETDEV_TX_OK; 3003 return NETDEV_TX_OK;
2749} 3004}
2750 3005
2751static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev) 3006static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2752{ 3007{
2753 struct igb_adapter *adapter = netdev_priv(netdev); 3008 struct igb_adapter *adapter = netdev_priv(netdev);
2754 struct igb_ring *tx_ring = &adapter->tx_ring[0]; 3009 struct igb_ring *tx_ring;
3010
3011 int r_idx = 0;
3012 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3013 tx_ring = adapter->multi_tx_table[r_idx];
2755 3014
2756 /* This goes back to the question of how to logically map a tx queue 3015 /* This goes back to the question of how to logically map a tx queue
2757 * to a flow. Right now, performance is impacted slightly negatively 3016 * to a flow. Right now, performance is impacted slightly negatively
@@ -2846,7 +3105,11 @@ static int igb_change_mtu(struct net_device *netdev, int new_mtu)
2846 else if (max_frame <= IGB_RXBUFFER_2048) 3105 else if (max_frame <= IGB_RXBUFFER_2048)
2847 adapter->rx_buffer_len = IGB_RXBUFFER_2048; 3106 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
2848 else 3107 else
2849 adapter->rx_buffer_len = IGB_RXBUFFER_4096; 3108#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3109 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3110#else
3111 adapter->rx_buffer_len = PAGE_SIZE / 2;
3112#endif
2850 /* adjust allocation if LPE protects us, and we aren't using SBP */ 3113 /* adjust allocation if LPE protects us, and we aren't using SBP */
2851 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || 3114 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
2852 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)) 3115 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
@@ -3010,26 +3273,19 @@ static irqreturn_t igb_msix_other(int irq, void *data)
3010 struct net_device *netdev = data; 3273 struct net_device *netdev = data;
3011 struct igb_adapter *adapter = netdev_priv(netdev); 3274 struct igb_adapter *adapter = netdev_priv(netdev);
3012 struct e1000_hw *hw = &adapter->hw; 3275 struct e1000_hw *hw = &adapter->hw;
3013 u32 eicr; 3276 u32 icr = rd32(E1000_ICR);
3014 /* disable interrupts from the "other" bit, avoid re-entry */
3015 wr32(E1000_EIMC, E1000_EIMS_OTHER);
3016
3017 eicr = rd32(E1000_EICR);
3018
3019 if (eicr & E1000_EIMS_OTHER) {
3020 u32 icr = rd32(E1000_ICR);
3021 /* reading ICR causes bit 31 of EICR to be cleared */
3022 if (!(icr & E1000_ICR_LSC))
3023 goto no_link_interrupt;
3024 hw->mac.get_link_status = 1;
3025 /* guard against interrupt when we're going down */
3026 if (!test_bit(__IGB_DOWN, &adapter->state))
3027 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3028 }
3029 3277
3278 /* reading ICR causes bit 31 of EICR to be cleared */
3279 if (!(icr & E1000_ICR_LSC))
3280 goto no_link_interrupt;
3281 hw->mac.get_link_status = 1;
3282 /* guard against interrupt when we're going down */
3283 if (!test_bit(__IGB_DOWN, &adapter->state))
3284 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3285
3030no_link_interrupt: 3286no_link_interrupt:
3031 wr32(E1000_IMS, E1000_IMS_LSC); 3287 wr32(E1000_IMS, E1000_IMS_LSC);
3032 wr32(E1000_EIMS, E1000_EIMS_OTHER); 3288 wr32(E1000_EIMS, adapter->eims_other);
3033 3289
3034 return IRQ_HANDLED; 3290 return IRQ_HANDLED;
3035} 3291}
@@ -3040,44 +3296,186 @@ static irqreturn_t igb_msix_tx(int irq, void *data)
3040 struct igb_adapter *adapter = tx_ring->adapter; 3296 struct igb_adapter *adapter = tx_ring->adapter;
3041 struct e1000_hw *hw = &adapter->hw; 3297 struct e1000_hw *hw = &adapter->hw;
3042 3298
3043 if (!tx_ring->itr_val) 3299#ifdef CONFIG_DCA
3044 wr32(E1000_EIMC, tx_ring->eims_value); 3300 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3045 3301 igb_update_tx_dca(tx_ring);
3302#endif
3046 tx_ring->total_bytes = 0; 3303 tx_ring->total_bytes = 0;
3047 tx_ring->total_packets = 0; 3304 tx_ring->total_packets = 0;
3048 if (!igb_clean_tx_irq(adapter, tx_ring)) 3305
3306 /* auto mask will automatically reenable the interrupt when we write
3307 * EICS */
3308 if (!igb_clean_tx_irq(tx_ring))
3049 /* Ring was not completely cleaned, so fire another interrupt */ 3309 /* Ring was not completely cleaned, so fire another interrupt */
3050 wr32(E1000_EICS, tx_ring->eims_value); 3310 wr32(E1000_EICS, tx_ring->eims_value);
3051 3311 else
3052 if (!tx_ring->itr_val)
3053 wr32(E1000_EIMS, tx_ring->eims_value); 3312 wr32(E1000_EIMS, tx_ring->eims_value);
3313
3054 return IRQ_HANDLED; 3314 return IRQ_HANDLED;
3055} 3315}
3056 3316
3317static void igb_write_itr(struct igb_ring *ring)
3318{
3319 struct e1000_hw *hw = &ring->adapter->hw;
3320 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3321 switch (hw->mac.type) {
3322 case e1000_82576:
3323 wr32(ring->itr_register,
3324 ring->itr_val |
3325 0x80000000);
3326 break;
3327 default:
3328 wr32(ring->itr_register,
3329 ring->itr_val |
3330 (ring->itr_val << 16));
3331 break;
3332 }
3333 ring->set_itr = 0;
3334 }
3335}
3336
3057static irqreturn_t igb_msix_rx(int irq, void *data) 3337static irqreturn_t igb_msix_rx(int irq, void *data)
3058{ 3338{
3059 struct igb_ring *rx_ring = data; 3339 struct igb_ring *rx_ring = data;
3060 struct igb_adapter *adapter = rx_ring->adapter; 3340 struct igb_adapter *adapter = rx_ring->adapter;
3061 struct e1000_hw *hw = &adapter->hw;
3062 3341
3063 if (!rx_ring->itr_val) 3342 /* Write the ITR value calculated at the end of the
3064 wr32(E1000_EIMC, rx_ring->eims_value); 3343 * previous interrupt.
3344 */
3345
3346 igb_write_itr(rx_ring);
3065 3347
3066 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi)) { 3348 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3067 rx_ring->total_bytes = 0;
3068 rx_ring->total_packets = 0;
3069 rx_ring->no_itr_adjust = 0;
3070 __netif_rx_schedule(adapter->netdev, &rx_ring->napi); 3349 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3071 } else { 3350
3072 if (!rx_ring->no_itr_adjust) { 3351#ifdef CONFIG_DCA
3073 igb_lower_rx_eitr(adapter, rx_ring); 3352 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3074 rx_ring->no_itr_adjust = 1; 3353 igb_update_rx_dca(rx_ring);
3354#endif
3355 return IRQ_HANDLED;
3356}
3357
3358#ifdef CONFIG_DCA
3359static void igb_update_rx_dca(struct igb_ring *rx_ring)
3360{
3361 u32 dca_rxctrl;
3362 struct igb_adapter *adapter = rx_ring->adapter;
3363 struct e1000_hw *hw = &adapter->hw;
3364 int cpu = get_cpu();
3365 int q = rx_ring - adapter->rx_ring;
3366
3367 if (rx_ring->cpu != cpu) {
3368 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3369 if (hw->mac.type == e1000_82576) {
3370 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3371 dca_rxctrl |= dca_get_tag(cpu) <<
3372 E1000_DCA_RXCTRL_CPUID_SHIFT;
3373 } else {
3374 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3375 dca_rxctrl |= dca_get_tag(cpu);
3075 } 3376 }
3377 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3378 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3379 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3380 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3381 rx_ring->cpu = cpu;
3076 } 3382 }
3383 put_cpu();
3384}
3077 3385
3078 return IRQ_HANDLED; 3386static void igb_update_tx_dca(struct igb_ring *tx_ring)
3387{
3388 u32 dca_txctrl;
3389 struct igb_adapter *adapter = tx_ring->adapter;
3390 struct e1000_hw *hw = &adapter->hw;
3391 int cpu = get_cpu();
3392 int q = tx_ring - adapter->tx_ring;
3393
3394 if (tx_ring->cpu != cpu) {
3395 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3396 if (hw->mac.type == e1000_82576) {
3397 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3398 dca_txctrl |= dca_get_tag(cpu) <<
3399 E1000_DCA_TXCTRL_CPUID_SHIFT;
3400 } else {
3401 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3402 dca_txctrl |= dca_get_tag(cpu);
3403 }
3404 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3405 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3406 tx_ring->cpu = cpu;
3407 }
3408 put_cpu();
3409}
3410
3411static void igb_setup_dca(struct igb_adapter *adapter)
3412{
3413 int i;
3414
3415 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3416 return;
3417
3418 for (i = 0; i < adapter->num_tx_queues; i++) {
3419 adapter->tx_ring[i].cpu = -1;
3420 igb_update_tx_dca(&adapter->tx_ring[i]);
3421 }
3422 for (i = 0; i < adapter->num_rx_queues; i++) {
3423 adapter->rx_ring[i].cpu = -1;
3424 igb_update_rx_dca(&adapter->rx_ring[i]);
3425 }
3426}
3427
3428static int __igb_notify_dca(struct device *dev, void *data)
3429{
3430 struct net_device *netdev = dev_get_drvdata(dev);
3431 struct igb_adapter *adapter = netdev_priv(netdev);
3432 struct e1000_hw *hw = &adapter->hw;
3433 unsigned long event = *(unsigned long *)data;
3434
3435 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3436 goto out;
3437
3438 switch (event) {
3439 case DCA_PROVIDER_ADD:
3440 /* if already enabled, don't do it again */
3441 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3442 break;
3443 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3444 /* Always use CB2 mode, difference is masked
3445 * in the CB driver. */
3446 wr32(E1000_DCA_CTRL, 2);
3447 if (dca_add_requester(dev) == 0) {
3448 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3449 igb_setup_dca(adapter);
3450 break;
3451 }
3452 /* Fall Through since DCA is disabled. */
3453 case DCA_PROVIDER_REMOVE:
3454 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3455 /* without this a class_device is left
3456 * hanging around in the sysfs model */
3457 dca_remove_requester(dev);
3458 dev_info(&adapter->pdev->dev, "DCA disabled\n");
3459 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3460 wr32(E1000_DCA_CTRL, 1);
3461 }
3462 break;
3463 }
3464out:
3465 return 0;
3079} 3466}
3080 3467
3468static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3469 void *p)
3470{
3471 int ret_val;
3472
3473 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3474 __igb_notify_dca);
3475
3476 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3477}
3478#endif /* CONFIG_DCA */
3081 3479
3082/** 3480/**
3083 * igb_intr_msi - Interrupt Handler 3481 * igb_intr_msi - Interrupt Handler
@@ -3088,34 +3486,19 @@ static irqreturn_t igb_intr_msi(int irq, void *data)
3088{ 3486{
3089 struct net_device *netdev = data; 3487 struct net_device *netdev = data;
3090 struct igb_adapter *adapter = netdev_priv(netdev); 3488 struct igb_adapter *adapter = netdev_priv(netdev);
3091 struct napi_struct *napi = &adapter->napi;
3092 struct e1000_hw *hw = &adapter->hw; 3489 struct e1000_hw *hw = &adapter->hw;
3093 /* read ICR disables interrupts using IAM */ 3490 /* read ICR disables interrupts using IAM */
3094 u32 icr = rd32(E1000_ICR); 3491 u32 icr = rd32(E1000_ICR);
3095 3492
3096 /* Write the ITR value calculated at the end of the 3493 igb_write_itr(adapter->rx_ring);
3097 * previous interrupt.
3098 */
3099 if (adapter->set_itr) {
3100 wr32(E1000_ITR,
3101 1000000000 / (adapter->itr * 256));
3102 adapter->set_itr = 0;
3103 }
3104 3494
3105 /* read ICR disables interrupts using IAM */
3106 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 3495 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3107 hw->mac.get_link_status = 1; 3496 hw->mac.get_link_status = 1;
3108 if (!test_bit(__IGB_DOWN, &adapter->state)) 3497 if (!test_bit(__IGB_DOWN, &adapter->state))
3109 mod_timer(&adapter->watchdog_timer, jiffies + 1); 3498 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3110 } 3499 }
3111 3500
3112 if (netif_rx_schedule_prep(netdev, napi)) { 3501 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
3113 adapter->tx_ring->total_bytes = 0;
3114 adapter->tx_ring->total_packets = 0;
3115 adapter->rx_ring->total_bytes = 0;
3116 adapter->rx_ring->total_packets = 0;
3117 __netif_rx_schedule(netdev, napi);
3118 }
3119 3502
3120 return IRQ_HANDLED; 3503 return IRQ_HANDLED;
3121} 3504}
@@ -3129,7 +3512,6 @@ static irqreturn_t igb_intr(int irq, void *data)
3129{ 3512{
3130 struct net_device *netdev = data; 3513 struct net_device *netdev = data;
3131 struct igb_adapter *adapter = netdev_priv(netdev); 3514 struct igb_adapter *adapter = netdev_priv(netdev);
3132 struct napi_struct *napi = &adapter->napi;
3133 struct e1000_hw *hw = &adapter->hw; 3515 struct e1000_hw *hw = &adapter->hw;
3134 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 3516 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3135 * need for the IMC write */ 3517 * need for the IMC write */
@@ -3138,14 +3520,7 @@ static irqreturn_t igb_intr(int irq, void *data)
3138 if (!icr) 3520 if (!icr)
3139 return IRQ_NONE; /* Not our interrupt */ 3521 return IRQ_NONE; /* Not our interrupt */
3140 3522
3141 /* Write the ITR value calculated at the end of the 3523 igb_write_itr(adapter->rx_ring);
3142 * previous interrupt.
3143 */
3144 if (adapter->set_itr) {
3145 wr32(E1000_ITR,
3146 1000000000 / (adapter->itr * 256));
3147 adapter->set_itr = 0;
3148 }
3149 3524
3150 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 3525 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3151 * not set, then the adapter didn't send an interrupt */ 3526 * not set, then the adapter didn't send an interrupt */
@@ -3161,57 +3536,41 @@ static irqreturn_t igb_intr(int irq, void *data)
3161 mod_timer(&adapter->watchdog_timer, jiffies + 1); 3536 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3162 } 3537 }
3163 3538
3164 if (netif_rx_schedule_prep(netdev, napi)) { 3539 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
3165 adapter->tx_ring->total_bytes = 0;
3166 adapter->rx_ring->total_bytes = 0;
3167 adapter->tx_ring->total_packets = 0;
3168 adapter->rx_ring->total_packets = 0;
3169 __netif_rx_schedule(netdev, napi);
3170 }
3171 3540
3172 return IRQ_HANDLED; 3541 return IRQ_HANDLED;
3173} 3542}
3174 3543
3175/** 3544/**
3176 * igb_clean - NAPI Rx polling callback 3545 * igb_poll - NAPI Rx polling callback
3177 * @adapter: board private structure 3546 * @napi: napi polling structure
3547 * @budget: count of how many packets we should handle
3178 **/ 3548 **/
3179static int igb_clean(struct napi_struct *napi, int budget) 3549static int igb_poll(struct napi_struct *napi, int budget)
3180{ 3550{
3181 struct igb_adapter *adapter = container_of(napi, struct igb_adapter, 3551 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3182 napi); 3552 struct igb_adapter *adapter = rx_ring->adapter;
3183 struct net_device *netdev = adapter->netdev; 3553 struct net_device *netdev = adapter->netdev;
3184 int tx_clean_complete = 1, work_done = 0; 3554 int tx_clean_complete, work_done = 0;
3185 int i;
3186
3187 /* Must NOT use netdev_priv macro here. */
3188 adapter = netdev->priv;
3189 3555
3190 /* Keep link state information with original netdev */ 3556 /* this poll routine only supports one tx and one rx queue */
3191 if (!netif_carrier_ok(netdev)) 3557#ifdef CONFIG_DCA
3192 goto quit_polling; 3558 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3193 3559 igb_update_tx_dca(&adapter->tx_ring[0]);
3194 /* igb_clean is called per-cpu. This lock protects tx_ring[i] from 3560#endif
3195 * being cleaned by multiple cpus simultaneously. A failure obtaining 3561 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
3196 * the lock means tx_ring[i] is currently being cleaned anyway. */
3197 for (i = 0; i < adapter->num_tx_queues; i++) {
3198 if (spin_trylock(&adapter->tx_ring[i].tx_clean_lock)) {
3199 tx_clean_complete &= igb_clean_tx_irq(adapter,
3200 &adapter->tx_ring[i]);
3201 spin_unlock(&adapter->tx_ring[i].tx_clean_lock);
3202 }
3203 }
3204 3562
3205 for (i = 0; i < adapter->num_rx_queues; i++) 3563#ifdef CONFIG_DCA
3206 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i], &work_done, 3564 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3207 adapter->rx_ring[i].napi.weight); 3565 igb_update_rx_dca(&adapter->rx_ring[0]);
3566#endif
3567 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
3208 3568
3209 /* If no Tx and not enough Rx work done, exit the polling mode */ 3569 /* If no Tx and not enough Rx work done, exit the polling mode */
3210 if ((tx_clean_complete && (work_done < budget)) || 3570 if ((tx_clean_complete && (work_done < budget)) ||
3211 !netif_running(netdev)) { 3571 !netif_running(netdev)) {
3212quit_polling:
3213 if (adapter->itr_setting & 3) 3572 if (adapter->itr_setting & 3)
3214 igb_set_itr(adapter, E1000_ITR, false); 3573 igb_set_itr(adapter);
3215 netif_rx_complete(netdev, napi); 3574 netif_rx_complete(netdev, napi);
3216 if (!test_bit(__IGB_DOWN, &adapter->state)) 3575 if (!test_bit(__IGB_DOWN, &adapter->state))
3217 igb_irq_enable(adapter); 3576 igb_irq_enable(adapter);
@@ -3233,7 +3592,11 @@ static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3233 if (!netif_carrier_ok(netdev)) 3592 if (!netif_carrier_ok(netdev))
3234 goto quit_polling; 3593 goto quit_polling;
3235 3594
3236 igb_clean_rx_irq_adv(adapter, rx_ring, &work_done, budget); 3595#ifdef CONFIG_DCA
3596 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3597 igb_update_rx_dca(rx_ring);
3598#endif
3599 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
3237 3600
3238 3601
3239 /* If not enough Rx work done, exit the polling mode */ 3602 /* If not enough Rx work done, exit the polling mode */
@@ -3241,16 +3604,16 @@ static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3241quit_polling: 3604quit_polling:
3242 netif_rx_complete(netdev, napi); 3605 netif_rx_complete(netdev, napi);
3243 3606
3244 wr32(E1000_EIMS, rx_ring->eims_value); 3607 if (adapter->itr_setting & 3) {
3245 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust && 3608 if (adapter->num_rx_queues == 1)
3246 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) { 3609 igb_set_itr(adapter);
3247 int mean_size = rx_ring->total_bytes / 3610 else
3248 rx_ring->total_packets; 3611 igb_update_ring_itr(rx_ring);
3249 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3250 igb_raise_rx_eitr(adapter, rx_ring);
3251 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3252 igb_lower_rx_eitr(adapter, rx_ring);
3253 } 3612 }
3613
3614 if (!test_bit(__IGB_DOWN, &adapter->state))
3615 wr32(E1000_EIMS, rx_ring->eims_value);
3616
3254 return 0; 3617 return 0;
3255 } 3618 }
3256 3619
@@ -3268,11 +3631,11 @@ static inline u32 get_head(struct igb_ring *tx_ring)
3268 * @adapter: board private structure 3631 * @adapter: board private structure
3269 * returns true if ring is completely cleaned 3632 * returns true if ring is completely cleaned
3270 **/ 3633 **/
3271static bool igb_clean_tx_irq(struct igb_adapter *adapter, 3634static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
3272 struct igb_ring *tx_ring)
3273{ 3635{
3274 struct net_device *netdev = adapter->netdev; 3636 struct igb_adapter *adapter = tx_ring->adapter;
3275 struct e1000_hw *hw = &adapter->hw; 3637 struct e1000_hw *hw = &adapter->hw;
3638 struct net_device *netdev = adapter->netdev;
3276 struct e1000_tx_desc *tx_desc; 3639 struct e1000_tx_desc *tx_desc;
3277 struct igb_buffer *buffer_info; 3640 struct igb_buffer *buffer_info;
3278 struct sk_buff *skb; 3641 struct sk_buff *skb;
@@ -3334,9 +3697,9 @@ done_cleaning:
3334 * sees the new next_to_clean. 3697 * sees the new next_to_clean.
3335 */ 3698 */
3336 smp_mb(); 3699 smp_mb();
3337 if (netif_queue_stopped(netdev) && 3700 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3338 !(test_bit(__IGB_DOWN, &adapter->state))) { 3701 !(test_bit(__IGB_DOWN, &adapter->state))) {
3339 netif_wake_queue(netdev); 3702 netif_wake_subqueue(netdev, tx_ring->queue_index);
3340 ++adapter->restart_queue; 3703 ++adapter->restart_queue;
3341 } 3704 }
3342 } 3705 }
@@ -3355,7 +3718,7 @@ done_cleaning:
3355 /* detected Tx unit hang */ 3718 /* detected Tx unit hang */
3356 dev_err(&adapter->pdev->dev, 3719 dev_err(&adapter->pdev->dev,
3357 "Detected Tx Unit Hang\n" 3720 "Detected Tx Unit Hang\n"
3358 " Tx Queue <%lu>\n" 3721 " Tx Queue <%d>\n"
3359 " TDH <%x>\n" 3722 " TDH <%x>\n"
3360 " TDT <%x>\n" 3723 " TDT <%x>\n"
3361 " next_to_use <%x>\n" 3724 " next_to_use <%x>\n"
@@ -3365,8 +3728,7 @@ done_cleaning:
3365 " time_stamp <%lx>\n" 3728 " time_stamp <%lx>\n"
3366 " jiffies <%lx>\n" 3729 " jiffies <%lx>\n"
3367 " desc.status <%x>\n", 3730 " desc.status <%x>\n",
3368 (unsigned long)((tx_ring - adapter->tx_ring) / 3731 tx_ring->queue_index,
3369 sizeof(struct igb_ring)),
3370 readl(adapter->hw.hw_addr + tx_ring->head), 3732 readl(adapter->hw.hw_addr + tx_ring->head),
3371 readl(adapter->hw.hw_addr + tx_ring->tail), 3733 readl(adapter->hw.hw_addr + tx_ring->tail),
3372 tx_ring->next_to_use, 3734 tx_ring->next_to_use,
@@ -3375,33 +3737,87 @@ done_cleaning:
3375 tx_ring->buffer_info[i].time_stamp, 3737 tx_ring->buffer_info[i].time_stamp,
3376 jiffies, 3738 jiffies,
3377 tx_desc->upper.fields.status); 3739 tx_desc->upper.fields.status);
3378 netif_stop_queue(netdev); 3740 netif_stop_subqueue(netdev, tx_ring->queue_index);
3379 } 3741 }
3380 } 3742 }
3381 tx_ring->total_bytes += total_bytes; 3743 tx_ring->total_bytes += total_bytes;
3382 tx_ring->total_packets += total_packets; 3744 tx_ring->total_packets += total_packets;
3745 tx_ring->tx_stats.bytes += total_bytes;
3746 tx_ring->tx_stats.packets += total_packets;
3383 adapter->net_stats.tx_bytes += total_bytes; 3747 adapter->net_stats.tx_bytes += total_bytes;
3384 adapter->net_stats.tx_packets += total_packets; 3748 adapter->net_stats.tx_packets += total_packets;
3385 return retval; 3749 return retval;
3386} 3750}
3387 3751
3752#ifdef CONFIG_IGB_LRO
3753 /**
3754 * igb_get_skb_hdr - helper function for LRO header processing
3755 * @skb: pointer to sk_buff to be added to LRO packet
3756 * @iphdr: pointer to ip header structure
3757 * @tcph: pointer to tcp header structure
3758 * @hdr_flags: pointer to header flags
3759 * @priv: pointer to the receive descriptor for the current sk_buff
3760 **/
3761static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3762 u64 *hdr_flags, void *priv)
3763{
3764 union e1000_adv_rx_desc *rx_desc = priv;
3765 u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3766 (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3767
3768 /* Verify that this is a valid IPv4 TCP packet */
3769 if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3770 E1000_RXDADV_PKTTYPE_TCP))
3771 return -1;
3772
3773 /* Set network headers */
3774 skb_reset_network_header(skb);
3775 skb_set_transport_header(skb, ip_hdrlen(skb));
3776 *iphdr = ip_hdr(skb);
3777 *tcph = tcp_hdr(skb);
3778 *hdr_flags = LRO_IPV4 | LRO_TCP;
3779
3780 return 0;
3781
3782}
3783#endif /* CONFIG_IGB_LRO */
3388 3784
3389/** 3785/**
3390 * igb_receive_skb - helper function to handle rx indications 3786 * igb_receive_skb - helper function to handle rx indications
3391 * @adapter: board private structure 3787 * @ring: pointer to receive ring receving this packet
3392 * @status: descriptor status field as written by hardware 3788 * @status: descriptor status field as written by hardware
3393 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 3789 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3394 * @skb: pointer to sk_buff to be indicated to stack 3790 * @skb: pointer to sk_buff to be indicated to stack
3395 **/ 3791 **/
3396static void igb_receive_skb(struct igb_adapter *adapter, u8 status, __le16 vlan, 3792static void igb_receive_skb(struct igb_ring *ring, u8 status,
3397 struct sk_buff *skb) 3793 union e1000_adv_rx_desc * rx_desc,
3794 struct sk_buff *skb)
3398{ 3795{
3399 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP)) 3796 struct igb_adapter * adapter = ring->adapter;
3400 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, 3797 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3401 le16_to_cpu(vlan) & 3798
3402 E1000_RXD_SPC_VLAN_MASK); 3799#ifdef CONFIG_IGB_LRO
3403 else 3800 if (adapter->netdev->features & NETIF_F_LRO &&
3404 netif_receive_skb(skb); 3801 skb->ip_summed == CHECKSUM_UNNECESSARY) {
3802 if (vlan_extracted)
3803 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3804 adapter->vlgrp,
3805 le16_to_cpu(rx_desc->wb.upper.vlan),
3806 rx_desc);
3807 else
3808 lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3809 ring->lro_used = 1;
3810 } else {
3811#endif
3812 if (vlan_extracted)
3813 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3814 le16_to_cpu(rx_desc->wb.upper.vlan));
3815 else
3816
3817 netif_receive_skb(skb);
3818#ifdef CONFIG_IGB_LRO
3819 }
3820#endif
3405} 3821}
3406 3822
3407 3823
@@ -3427,16 +3843,16 @@ static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3427 adapter->hw_csum_good++; 3843 adapter->hw_csum_good++;
3428} 3844}
3429 3845
3430static bool igb_clean_rx_irq_adv(struct igb_adapter *adapter, 3846static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3431 struct igb_ring *rx_ring, 3847 int *work_done, int budget)
3432 int *work_done, int budget)
3433{ 3848{
3849 struct igb_adapter *adapter = rx_ring->adapter;
3434 struct net_device *netdev = adapter->netdev; 3850 struct net_device *netdev = adapter->netdev;
3435 struct pci_dev *pdev = adapter->pdev; 3851 struct pci_dev *pdev = adapter->pdev;
3436 union e1000_adv_rx_desc *rx_desc , *next_rxd; 3852 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3437 struct igb_buffer *buffer_info , *next_buffer; 3853 struct igb_buffer *buffer_info , *next_buffer;
3438 struct sk_buff *skb; 3854 struct sk_buff *skb;
3439 unsigned int i, j; 3855 unsigned int i;
3440 u32 length, hlen, staterr; 3856 u32 length, hlen, staterr;
3441 bool cleaned = false; 3857 bool cleaned = false;
3442 int cleaned_count = 0; 3858 int cleaned_count = 0;
@@ -3466,64 +3882,48 @@ static bool igb_clean_rx_irq_adv(struct igb_adapter *adapter,
3466 cleaned = true; 3882 cleaned = true;
3467 cleaned_count++; 3883 cleaned_count++;
3468 3884
3469 if (rx_ring->pending_skb != NULL) { 3885 skb = buffer_info->skb;
3470 skb = rx_ring->pending_skb; 3886 prefetch(skb->data - NET_IP_ALIGN);
3471 rx_ring->pending_skb = NULL; 3887 buffer_info->skb = NULL;
3472 j = rx_ring->pending_skb_page; 3888 if (!adapter->rx_ps_hdr_size) {
3473 } else { 3889 pci_unmap_single(pdev, buffer_info->dma,
3474 skb = buffer_info->skb; 3890 adapter->rx_buffer_len +
3475 prefetch(skb->data - NET_IP_ALIGN); 3891 NET_IP_ALIGN,
3476 buffer_info->skb = NULL; 3892 PCI_DMA_FROMDEVICE);
3477 if (hlen) { 3893 skb_put(skb, length);
3478 pci_unmap_single(pdev, buffer_info->dma, 3894 goto send_up;
3479 adapter->rx_ps_hdr_size + 3895 }
3480 NET_IP_ALIGN, 3896
3481 PCI_DMA_FROMDEVICE); 3897 if (!skb_shinfo(skb)->nr_frags) {
3482 skb_put(skb, hlen); 3898 pci_unmap_single(pdev, buffer_info->dma,
3483 } else { 3899 adapter->rx_ps_hdr_size +
3484 pci_unmap_single(pdev, buffer_info->dma, 3900 NET_IP_ALIGN,
3485 adapter->rx_buffer_len + 3901 PCI_DMA_FROMDEVICE);
3486 NET_IP_ALIGN, 3902 skb_put(skb, hlen);
3487 PCI_DMA_FROMDEVICE);
3488 skb_put(skb, length);
3489 goto send_up;
3490 }
3491 j = 0;
3492 } 3903 }
3493 3904
3494 while (length) { 3905 if (length) {
3495 pci_unmap_page(pdev, buffer_info->page_dma, 3906 pci_unmap_page(pdev, buffer_info->page_dma,
3496 PAGE_SIZE, PCI_DMA_FROMDEVICE); 3907 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3497 buffer_info->page_dma = 0; 3908 buffer_info->page_dma = 0;
3498 skb_fill_page_desc(skb, j, buffer_info->page, 3909
3499 0, length); 3910 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3500 buffer_info->page = NULL; 3911 buffer_info->page,
3912 buffer_info->page_offset,
3913 length);
3914
3915 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3916 (page_count(buffer_info->page) != 1))
3917 buffer_info->page = NULL;
3918 else
3919 get_page(buffer_info->page);
3501 3920
3502 skb->len += length; 3921 skb->len += length;
3503 skb->data_len += length; 3922 skb->data_len += length;
3504 skb->truesize += length;
3505 rx_desc->wb.upper.status_error = 0;
3506 if (staterr & E1000_RXD_STAT_EOP)
3507 break;
3508 3923
3509 j++; 3924 skb->truesize += length;
3510 cleaned_count++;
3511 i++;
3512 if (i == rx_ring->count)
3513 i = 0;
3514
3515 buffer_info = &rx_ring->buffer_info[i];
3516 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3517 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3518 length = le16_to_cpu(rx_desc->wb.upper.length);
3519 if (!(staterr & E1000_RXD_STAT_DD)) {
3520 rx_ring->pending_skb = skb;
3521 rx_ring->pending_skb_page = j;
3522 goto out;
3523 }
3524 } 3925 }
3525send_up: 3926send_up:
3526 pskb_trim(skb, skb->len - 4);
3527 i++; 3927 i++;
3528 if (i == rx_ring->count) 3928 if (i == rx_ring->count)
3529 i = 0; 3929 i = 0;
@@ -3531,11 +3931,16 @@ send_up:
3531 prefetch(next_rxd); 3931 prefetch(next_rxd);
3532 next_buffer = &rx_ring->buffer_info[i]; 3932 next_buffer = &rx_ring->buffer_info[i];
3533 3933
3934 if (!(staterr & E1000_RXD_STAT_EOP)) {
3935 buffer_info->skb = xchg(&next_buffer->skb, skb);
3936 buffer_info->dma = xchg(&next_buffer->dma, 0);
3937 goto next_desc;
3938 }
3939
3534 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { 3940 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3535 dev_kfree_skb_irq(skb); 3941 dev_kfree_skb_irq(skb);
3536 goto next_desc; 3942 goto next_desc;
3537 } 3943 }
3538 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3539 3944
3540 total_bytes += skb->len; 3945 total_bytes += skb->len;
3541 total_packets++; 3946 total_packets++;
@@ -3544,7 +3949,7 @@ send_up:
3544 3949
3545 skb->protocol = eth_type_trans(skb, netdev); 3950 skb->protocol = eth_type_trans(skb, netdev);
3546 3951
3547 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb); 3952 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
3548 3953
3549 netdev->last_rx = jiffies; 3954 netdev->last_rx = jiffies;
3550 3955
@@ -3553,8 +3958,7 @@ next_desc:
3553 3958
3554 /* return some buffers to hardware, one at a time is too slow */ 3959 /* return some buffers to hardware, one at a time is too slow */
3555 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 3960 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3556 igb_alloc_rx_buffers_adv(adapter, rx_ring, 3961 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3557 cleaned_count);
3558 cleaned_count = 0; 3962 cleaned_count = 0;
3559 } 3963 }
3560 3964
@@ -3564,12 +3968,19 @@ next_desc:
3564 3968
3565 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 3969 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3566 } 3970 }
3567out: 3971
3568 rx_ring->next_to_clean = i; 3972 rx_ring->next_to_clean = i;
3569 cleaned_count = IGB_DESC_UNUSED(rx_ring); 3973 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3570 3974
3975#ifdef CONFIG_IGB_LRO
3976 if (rx_ring->lro_used) {
3977 lro_flush_all(&rx_ring->lro_mgr);
3978 rx_ring->lro_used = 0;
3979 }
3980#endif
3981
3571 if (cleaned_count) 3982 if (cleaned_count)
3572 igb_alloc_rx_buffers_adv(adapter, rx_ring, cleaned_count); 3983 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3573 3984
3574 rx_ring->total_packets += total_packets; 3985 rx_ring->total_packets += total_packets;
3575 rx_ring->total_bytes += total_bytes; 3986 rx_ring->total_bytes += total_bytes;
@@ -3585,10 +3996,10 @@ out:
3585 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split 3996 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3586 * @adapter: address of board private structure 3997 * @adapter: address of board private structure
3587 **/ 3998 **/
3588static void igb_alloc_rx_buffers_adv(struct igb_adapter *adapter, 3999static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
3589 struct igb_ring *rx_ring,
3590 int cleaned_count) 4000 int cleaned_count)
3591{ 4001{
4002 struct igb_adapter *adapter = rx_ring->adapter;
3592 struct net_device *netdev = adapter->netdev; 4003 struct net_device *netdev = adapter->netdev;
3593 struct pci_dev *pdev = adapter->pdev; 4004 struct pci_dev *pdev = adapter->pdev;
3594 union e1000_adv_rx_desc *rx_desc; 4005 union e1000_adv_rx_desc *rx_desc;
@@ -3602,16 +4013,22 @@ static void igb_alloc_rx_buffers_adv(struct igb_adapter *adapter,
3602 while (cleaned_count--) { 4013 while (cleaned_count--) {
3603 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); 4014 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3604 4015
3605 if (adapter->rx_ps_hdr_size && !buffer_info->page) { 4016 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
3606 buffer_info->page = alloc_page(GFP_ATOMIC);
3607 if (!buffer_info->page) { 4017 if (!buffer_info->page) {
3608 adapter->alloc_rx_buff_failed++; 4018 buffer_info->page = alloc_page(GFP_ATOMIC);
3609 goto no_buffers; 4019 if (!buffer_info->page) {
4020 adapter->alloc_rx_buff_failed++;
4021 goto no_buffers;
4022 }
4023 buffer_info->page_offset = 0;
4024 } else {
4025 buffer_info->page_offset ^= PAGE_SIZE / 2;
3610 } 4026 }
3611 buffer_info->page_dma = 4027 buffer_info->page_dma =
3612 pci_map_page(pdev, 4028 pci_map_page(pdev,
3613 buffer_info->page, 4029 buffer_info->page,
3614 0, PAGE_SIZE, 4030 buffer_info->page_offset,
4031 PAGE_SIZE / 2,
3615 PCI_DMA_FROMDEVICE); 4032 PCI_DMA_FROMDEVICE);
3616 } 4033 }
3617 4034
@@ -3746,7 +4163,6 @@ static void igb_vlan_rx_register(struct net_device *netdev,
3746 4163
3747 /* enable VLAN receive filtering */ 4164 /* enable VLAN receive filtering */
3748 rctl = rd32(E1000_RCTL); 4165 rctl = rd32(E1000_RCTL);
3749 rctl |= E1000_RCTL_VFE;
3750 rctl &= ~E1000_RCTL_CFIEN; 4166 rctl &= ~E1000_RCTL_CFIEN;
3751 wr32(E1000_RCTL, rctl); 4167 wr32(E1000_RCTL, rctl);
3752 igb_update_mng_vlan(adapter); 4168 igb_update_mng_vlan(adapter);
@@ -3758,10 +4174,6 @@ static void igb_vlan_rx_register(struct net_device *netdev,
3758 ctrl &= ~E1000_CTRL_VME; 4174 ctrl &= ~E1000_CTRL_VME;
3759 wr32(E1000_CTRL, ctrl); 4175 wr32(E1000_CTRL, ctrl);
3760 4176
3761 /* disable VLAN filtering */
3762 rctl = rd32(E1000_RCTL);
3763 rctl &= ~E1000_RCTL_VFE;
3764 wr32(E1000_RCTL, rctl);
3765 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) { 4177 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
3766 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); 4178 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3767 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 4179 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
@@ -3878,7 +4290,7 @@ static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3878 struct net_device *netdev = pci_get_drvdata(pdev); 4290 struct net_device *netdev = pci_get_drvdata(pdev);
3879 struct igb_adapter *adapter = netdev_priv(netdev); 4291 struct igb_adapter *adapter = netdev_priv(netdev);
3880 struct e1000_hw *hw = &adapter->hw; 4292 struct e1000_hw *hw = &adapter->hw;
3881 u32 ctrl, ctrl_ext, rctl, status; 4293 u32 ctrl, rctl, status;
3882 u32 wufc = adapter->wol; 4294 u32 wufc = adapter->wol;
3883#ifdef CONFIG_PM 4295#ifdef CONFIG_PM
3884 int retval = 0; 4296 int retval = 0;
@@ -3886,11 +4298,12 @@ static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3886 4298
3887 netif_device_detach(netdev); 4299 netif_device_detach(netdev);
3888 4300
3889 if (netif_running(netdev)) { 4301 if (netif_running(netdev))
3890 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4302 igb_close(netdev);
3891 igb_down(adapter); 4303
3892 igb_free_irq(adapter); 4304 igb_reset_interrupt_capability(adapter);
3893 } 4305
4306 igb_free_queues(adapter);
3894 4307
3895#ifdef CONFIG_PM 4308#ifdef CONFIG_PM
3896 retval = pci_save_state(pdev); 4309 retval = pci_save_state(pdev);
@@ -3921,33 +4334,24 @@ static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3921 ctrl |= E1000_CTRL_ADVD3WUC; 4334 ctrl |= E1000_CTRL_ADVD3WUC;
3922 wr32(E1000_CTRL, ctrl); 4335 wr32(E1000_CTRL, ctrl);
3923 4336
3924 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3925 adapter->hw.phy.media_type ==
3926 e1000_media_type_internal_serdes) {
3927 /* keep the laser running in D3 */
3928 ctrl_ext = rd32(E1000_CTRL_EXT);
3929 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3930 wr32(E1000_CTRL_EXT, ctrl_ext);
3931 }
3932
3933 /* Allow time for pending master requests to run */ 4337 /* Allow time for pending master requests to run */
3934 igb_disable_pcie_master(&adapter->hw); 4338 igb_disable_pcie_master(&adapter->hw);
3935 4339
3936 wr32(E1000_WUC, E1000_WUC_PME_EN); 4340 wr32(E1000_WUC, E1000_WUC_PME_EN);
3937 wr32(E1000_WUFC, wufc); 4341 wr32(E1000_WUFC, wufc);
3938 pci_enable_wake(pdev, PCI_D3hot, 1);
3939 pci_enable_wake(pdev, PCI_D3cold, 1);
3940 } else { 4342 } else {
3941 wr32(E1000_WUC, 0); 4343 wr32(E1000_WUC, 0);
3942 wr32(E1000_WUFC, 0); 4344 wr32(E1000_WUFC, 0);
3943 pci_enable_wake(pdev, PCI_D3hot, 0);
3944 pci_enable_wake(pdev, PCI_D3cold, 0);
3945 } 4345 }
3946 4346
3947 /* make sure adapter isn't asleep if manageability is enabled */ 4347 /* make sure adapter isn't asleep if manageability/wol is enabled */
3948 if (adapter->en_mng_pt) { 4348 if (wufc || adapter->en_mng_pt) {
3949 pci_enable_wake(pdev, PCI_D3hot, 1); 4349 pci_enable_wake(pdev, PCI_D3hot, 1);
3950 pci_enable_wake(pdev, PCI_D3cold, 1); 4350 pci_enable_wake(pdev, PCI_D3cold, 1);
4351 } else {
4352 igb_shutdown_fiber_serdes_link_82575(hw);
4353 pci_enable_wake(pdev, PCI_D3hot, 0);
4354 pci_enable_wake(pdev, PCI_D3cold, 0);
3951 } 4355 }
3952 4356
3953 /* Release control of h/w to f/w. If f/w is AMT enabled, this 4357 /* Release control of h/w to f/w. If f/w is AMT enabled, this
@@ -3971,7 +4375,11 @@ static int igb_resume(struct pci_dev *pdev)
3971 4375
3972 pci_set_power_state(pdev, PCI_D0); 4376 pci_set_power_state(pdev, PCI_D0);
3973 pci_restore_state(pdev); 4377 pci_restore_state(pdev);
3974 err = pci_enable_device(pdev); 4378
4379 if (adapter->need_ioport)
4380 err = pci_enable_device(pdev);
4381 else
4382 err = pci_enable_device_mem(pdev);
3975 if (err) { 4383 if (err) {
3976 dev_err(&pdev->dev, 4384 dev_err(&pdev->dev,
3977 "igb: Cannot enable PCI device from suspend\n"); 4385 "igb: Cannot enable PCI device from suspend\n");
@@ -3982,10 +4390,11 @@ static int igb_resume(struct pci_dev *pdev)
3982 pci_enable_wake(pdev, PCI_D3hot, 0); 4390 pci_enable_wake(pdev, PCI_D3hot, 0);
3983 pci_enable_wake(pdev, PCI_D3cold, 0); 4391 pci_enable_wake(pdev, PCI_D3cold, 0);
3984 4392
3985 if (netif_running(netdev)) { 4393 igb_set_interrupt_capability(adapter);
3986 err = igb_request_irq(adapter); 4394
3987 if (err) 4395 if (igb_alloc_queues(adapter)) {
3988 return err; 4396 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4397 return -ENOMEM;
3989 } 4398 }
3990 4399
3991 /* e1000_power_up_phy(adapter); */ 4400 /* e1000_power_up_phy(adapter); */
@@ -3993,10 +4402,11 @@ static int igb_resume(struct pci_dev *pdev)
3993 igb_reset(adapter); 4402 igb_reset(adapter);
3994 wr32(E1000_WUS, ~0); 4403 wr32(E1000_WUS, ~0);
3995 4404
3996 igb_init_manageability(adapter); 4405 if (netif_running(netdev)) {
3997 4406 err = igb_open(netdev);
3998 if (netif_running(netdev)) 4407 if (err)
3999 igb_up(adapter); 4408 return err;
4409 }
4000 4410
4001 netif_device_attach(netdev); 4411 netif_device_attach(netdev);
4002 4412
@@ -4026,14 +4436,17 @@ static void igb_netpoll(struct net_device *netdev)
4026 int work_done = 0; 4436 int work_done = 0;
4027 4437
4028 igb_irq_disable(adapter); 4438 igb_irq_disable(adapter);
4439 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4440
4029 for (i = 0; i < adapter->num_tx_queues; i++) 4441 for (i = 0; i < adapter->num_tx_queues; i++)
4030 igb_clean_tx_irq(adapter, &adapter->tx_ring[i]); 4442 igb_clean_tx_irq(&adapter->tx_ring[i]);
4031 4443
4032 for (i = 0; i < adapter->num_rx_queues; i++) 4444 for (i = 0; i < adapter->num_rx_queues; i++)
4033 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i], 4445 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
4034 &work_done, 4446 &work_done,
4035 adapter->rx_ring[i].napi.weight); 4447 adapter->rx_ring[i].napi.weight);
4036 4448
4449 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
4037 igb_irq_enable(adapter); 4450 igb_irq_enable(adapter);
4038} 4451}
4039#endif /* CONFIG_NET_POLL_CONTROLLER */ 4452#endif /* CONFIG_NET_POLL_CONTROLLER */
@@ -4074,8 +4487,13 @@ static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4074 struct net_device *netdev = pci_get_drvdata(pdev); 4487 struct net_device *netdev = pci_get_drvdata(pdev);
4075 struct igb_adapter *adapter = netdev_priv(netdev); 4488 struct igb_adapter *adapter = netdev_priv(netdev);
4076 struct e1000_hw *hw = &adapter->hw; 4489 struct e1000_hw *hw = &adapter->hw;
4490 int err;
4077 4491
4078 if (pci_enable_device(pdev)) { 4492 if (adapter->need_ioport)
4493 err = pci_enable_device(pdev);
4494 else
4495 err = pci_enable_device_mem(pdev);
4496 if (err) {
4079 dev_err(&pdev->dev, 4497 dev_err(&pdev->dev,
4080 "Cannot re-enable PCI device after reset.\n"); 4498 "Cannot re-enable PCI device after reset.\n");
4081 return PCI_ERS_RESULT_DISCONNECT; 4499 return PCI_ERS_RESULT_DISCONNECT;
diff --git a/drivers/net/ipg.c b/drivers/net/ipg.c
index 2c03f4e2ccc4..7373dafbb3f7 100644
--- a/drivers/net/ipg.c
+++ b/drivers/net/ipg.c
@@ -42,7 +42,6 @@
42#define ipg_r16(reg) ioread16(ioaddr + (reg)) 42#define ipg_r16(reg) ioread16(ioaddr + (reg))
43#define ipg_r8(reg) ioread8(ioaddr + (reg)) 43#define ipg_r8(reg) ioread8(ioaddr + (reg))
44 44
45#define JUMBO_FRAME_4k_ONLY
46enum { 45enum {
47 netdev_io_size = 128 46 netdev_io_size = 128
48}; 47};
@@ -55,6 +54,14 @@ MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
55MODULE_LICENSE("GPL"); 54MODULE_LICENSE("GPL");
56 55
57/* 56/*
57 * Defaults
58 */
59#define IPG_MAX_RXFRAME_SIZE 0x0600
60#define IPG_RXFRAG_SIZE 0x0600
61#define IPG_RXSUPPORT_SIZE 0x0600
62#define IPG_IS_JUMBO false
63
64/*
58 * Variable record -- index by leading revision/length 65 * Variable record -- index by leading revision/length
59 * Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN 66 * Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
60 */ 67 */
@@ -631,6 +638,7 @@ static void ipg_nic_set_multicast_list(struct net_device *dev)
631 638
632static int ipg_io_config(struct net_device *dev) 639static int ipg_io_config(struct net_device *dev)
633{ 640{
641 struct ipg_nic_private *sp = netdev_priv(dev);
634 void __iomem *ioaddr = ipg_ioaddr(dev); 642 void __iomem *ioaddr = ipg_ioaddr(dev);
635 u32 origmacctrl; 643 u32 origmacctrl;
636 u32 restoremacctrl; 644 u32 restoremacctrl;
@@ -670,7 +678,7 @@ static int ipg_io_config(struct net_device *dev)
670 /* Set RECEIVEMODE register. */ 678 /* Set RECEIVEMODE register. */
671 ipg_nic_set_multicast_list(dev); 679 ipg_nic_set_multicast_list(dev);
672 680
673 ipg_w16(IPG_MAX_RXFRAME_SIZE, MAX_FRAME_SIZE); 681 ipg_w16(sp->max_rxframe_size, MAX_FRAME_SIZE);
674 682
675 ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE, RX_DMA_POLL_PERIOD); 683 ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE, RX_DMA_POLL_PERIOD);
676 ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH); 684 ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
@@ -730,7 +738,7 @@ static int ipg_get_rxbuff(struct net_device *dev, int entry)
730 738
731 IPG_DEBUG_MSG("_get_rxbuff\n"); 739 IPG_DEBUG_MSG("_get_rxbuff\n");
732 740
733 skb = netdev_alloc_skb(dev, IPG_RXSUPPORT_SIZE + NET_IP_ALIGN); 741 skb = netdev_alloc_skb(dev, sp->rxsupport_size + NET_IP_ALIGN);
734 if (!skb) { 742 if (!skb) {
735 sp->rx_buff[entry] = NULL; 743 sp->rx_buff[entry] = NULL;
736 return -ENOMEM; 744 return -ENOMEM;
@@ -751,7 +759,7 @@ static int ipg_get_rxbuff(struct net_device *dev, int entry)
751 sp->rx_buf_sz, PCI_DMA_FROMDEVICE)); 759 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
752 760
753 /* Set the RFD fragment length. */ 761 /* Set the RFD fragment length. */
754 rxfragsize = IPG_RXFRAG_SIZE; 762 rxfragsize = sp->rxfrag_size;
755 rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN); 763 rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
756 764
757 return 0; 765 return 0;
@@ -1076,8 +1084,6 @@ static int ipg_nic_rxrestore(struct net_device *dev)
1076 return 0; 1084 return 0;
1077} 1085}
1078 1086
1079#ifdef JUMBO_FRAME
1080
1081/* use jumboindex and jumbosize to control jumbo frame status 1087/* use jumboindex and jumbosize to control jumbo frame status
1082 * initial status is jumboindex=-1 and jumbosize=0 1088 * initial status is jumboindex=-1 and jumbosize=0
1083 * 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done. 1089 * 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
@@ -1097,7 +1103,7 @@ enum {
1097 FRAME_WITH_START_WITH_END = 11 1103 FRAME_WITH_START_WITH_END = 11
1098}; 1104};
1099 1105
1100inline void ipg_nic_rx_free_skb(struct net_device *dev) 1106static void ipg_nic_rx_free_skb(struct net_device *dev)
1101{ 1107{
1102 struct ipg_nic_private *sp = netdev_priv(dev); 1108 struct ipg_nic_private *sp = netdev_priv(dev);
1103 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH; 1109 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
@@ -1113,7 +1119,7 @@ inline void ipg_nic_rx_free_skb(struct net_device *dev)
1113 } 1119 }
1114} 1120}
1115 1121
1116inline int ipg_nic_rx_check_frame_type(struct net_device *dev) 1122static int ipg_nic_rx_check_frame_type(struct net_device *dev)
1117{ 1123{
1118 struct ipg_nic_private *sp = netdev_priv(dev); 1124 struct ipg_nic_private *sp = netdev_priv(dev);
1119 struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH); 1125 struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
@@ -1126,7 +1132,7 @@ inline int ipg_nic_rx_check_frame_type(struct net_device *dev)
1126 return type; 1132 return type;
1127} 1133}
1128 1134
1129inline int ipg_nic_rx_check_error(struct net_device *dev) 1135static int ipg_nic_rx_check_error(struct net_device *dev)
1130{ 1136{
1131 struct ipg_nic_private *sp = netdev_priv(dev); 1137 struct ipg_nic_private *sp = netdev_priv(dev);
1132 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH; 1138 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
@@ -1209,8 +1215,8 @@ static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1209 1215
1210 /* accept this frame and send to upper layer */ 1216 /* accept this frame and send to upper layer */
1211 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN; 1217 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1212 if (framelen > IPG_RXFRAG_SIZE) 1218 if (framelen > sp->rxfrag_size)
1213 framelen = IPG_RXFRAG_SIZE; 1219 framelen = sp->rxfrag_size;
1214 1220
1215 skb_put(skb, framelen); 1221 skb_put(skb, framelen);
1216 skb->protocol = eth_type_trans(skb, dev); 1222 skb->protocol = eth_type_trans(skb, dev);
@@ -1243,10 +1249,10 @@ static void ipg_nic_rx_with_start(struct net_device *dev,
1243 pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN), 1249 pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1244 sp->rx_buf_sz, PCI_DMA_FROMDEVICE); 1250 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1245 1251
1246 skb_put(skb, IPG_RXFRAG_SIZE); 1252 skb_put(skb, sp->rxfrag_size);
1247 1253
1248 jumbo->found_start = 1; 1254 jumbo->found_start = 1;
1249 jumbo->current_size = IPG_RXFRAG_SIZE; 1255 jumbo->current_size = sp->rxfrag_size;
1250 jumbo->skb = skb; 1256 jumbo->skb = skb;
1251 1257
1252 sp->rx_buff[entry] = NULL; 1258 sp->rx_buff[entry] = NULL;
@@ -1272,11 +1278,7 @@ static void ipg_nic_rx_with_end(struct net_device *dev,
1272 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN; 1278 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1273 1279
1274 endframelen = framelen - jumbo->current_size; 1280 endframelen = framelen - jumbo->current_size;
1275 /* 1281 if (framelen > sp->rxsupport_size)
1276 if (framelen > IPG_RXFRAG_SIZE)
1277 framelen=IPG_RXFRAG_SIZE;
1278 */
1279 if (framelen > IPG_RXSUPPORT_SIZE)
1280 dev_kfree_skb_irq(jumbo->skb); 1282 dev_kfree_skb_irq(jumbo->skb);
1281 else { 1283 else {
1282 memcpy(skb_put(jumbo->skb, endframelen), 1284 memcpy(skb_put(jumbo->skb, endframelen),
@@ -1316,11 +1318,11 @@ static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1316 1318
1317 if (skb) { 1319 if (skb) {
1318 if (jumbo->found_start) { 1320 if (jumbo->found_start) {
1319 jumbo->current_size += IPG_RXFRAG_SIZE; 1321 jumbo->current_size += sp->rxfrag_size;
1320 if (jumbo->current_size <= IPG_RXSUPPORT_SIZE) { 1322 if (jumbo->current_size <= sp->rxsupport_size) {
1321 memcpy(skb_put(jumbo->skb, 1323 memcpy(skb_put(jumbo->skb,
1322 IPG_RXFRAG_SIZE), 1324 sp->rxfrag_size),
1323 skb->data, IPG_RXFRAG_SIZE); 1325 skb->data, sp->rxfrag_size);
1324 } 1326 }
1325 } 1327 }
1326 dev->last_rx = jiffies; 1328 dev->last_rx = jiffies;
@@ -1334,7 +1336,7 @@ static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1334 } 1336 }
1335} 1337}
1336 1338
1337static int ipg_nic_rx(struct net_device *dev) 1339static int ipg_nic_rx_jumbo(struct net_device *dev)
1338{ 1340{
1339 struct ipg_nic_private *sp = netdev_priv(dev); 1341 struct ipg_nic_private *sp = netdev_priv(dev);
1340 unsigned int curr = sp->rx_current; 1342 unsigned int curr = sp->rx_current;
@@ -1382,7 +1384,6 @@ static int ipg_nic_rx(struct net_device *dev)
1382 return 0; 1384 return 0;
1383} 1385}
1384 1386
1385#else
1386static int ipg_nic_rx(struct net_device *dev) 1387static int ipg_nic_rx(struct net_device *dev)
1387{ 1388{
1388 /* Transfer received Ethernet frames to higher network layers. */ 1389 /* Transfer received Ethernet frames to higher network layers. */
@@ -1413,11 +1414,11 @@ static int ipg_nic_rx(struct net_device *dev)
1413 /* Check for jumbo frame arrival with too small 1414 /* Check for jumbo frame arrival with too small
1414 * RXFRAG_SIZE. 1415 * RXFRAG_SIZE.
1415 */ 1416 */
1416 if (framelen > IPG_RXFRAG_SIZE) { 1417 if (framelen > sp->rxfrag_size) {
1417 IPG_DEBUG_MSG 1418 IPG_DEBUG_MSG
1418 ("RFS FrameLen > allocated fragment size.\n"); 1419 ("RFS FrameLen > allocated fragment size.\n");
1419 1420
1420 framelen = IPG_RXFRAG_SIZE; 1421 framelen = sp->rxfrag_size;
1421 } 1422 }
1422 1423
1423 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) & 1424 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
@@ -1556,7 +1557,6 @@ static int ipg_nic_rx(struct net_device *dev)
1556 1557
1557 return 0; 1558 return 0;
1558} 1559}
1559#endif
1560 1560
1561static void ipg_reset_after_host_error(struct work_struct *work) 1561static void ipg_reset_after_host_error(struct work_struct *work)
1562{ 1562{
@@ -1592,9 +1592,9 @@ static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1592 1592
1593 IPG_DEBUG_MSG("_interrupt_handler\n"); 1593 IPG_DEBUG_MSG("_interrupt_handler\n");
1594 1594
1595#ifdef JUMBO_FRAME 1595 if (sp->is_jumbo)
1596 ipg_nic_rxrestore(dev); 1596 ipg_nic_rxrestore(dev);
1597#endif 1597
1598 spin_lock(&sp->lock); 1598 spin_lock(&sp->lock);
1599 1599
1600 /* Get interrupt source information, and acknowledge 1600 /* Get interrupt source information, and acknowledge
@@ -1650,7 +1650,10 @@ static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1650 sp->RFDListCheckedCount++; 1650 sp->RFDListCheckedCount++;
1651#endif 1651#endif
1652 1652
1653 ipg_nic_rx(dev); 1653 if (sp->is_jumbo)
1654 ipg_nic_rx_jumbo(dev);
1655 else
1656 ipg_nic_rx(dev);
1654 } 1657 }
1655 1658
1656 /* If TxDMAComplete interrupt, free used TFDs. */ 1659 /* If TxDMAComplete interrupt, free used TFDs. */
@@ -1749,7 +1752,7 @@ static int ipg_nic_open(struct net_device *dev)
1749 1752
1750 IPG_DEBUG_MSG("_nic_open\n"); 1753 IPG_DEBUG_MSG("_nic_open\n");
1751 1754
1752 sp->rx_buf_sz = IPG_RXSUPPORT_SIZE; 1755 sp->rx_buf_sz = sp->rxsupport_size;
1753 1756
1754 /* Check for interrupt line conflicts, and request interrupt 1757 /* Check for interrupt line conflicts, and request interrupt
1755 * line for IPG. 1758 * line for IPG.
@@ -1804,13 +1807,10 @@ static int ipg_nic_open(struct net_device *dev)
1804 if (ipg_config_autoneg(dev) < 0) 1807 if (ipg_config_autoneg(dev) < 0)
1805 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name); 1808 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1806 1809
1807#ifdef JUMBO_FRAME
1808 /* initialize JUMBO Frame control variable */ 1810 /* initialize JUMBO Frame control variable */
1809 sp->jumbo.found_start = 0; 1811 sp->jumbo.found_start = 0;
1810 sp->jumbo.current_size = 0; 1812 sp->jumbo.current_size = 0;
1811 sp->jumbo.skb = NULL; 1813 sp->jumbo.skb = NULL;
1812 dev->mtu = IPG_TXFRAG_SIZE;
1813#endif
1814 1814
1815 /* Enable transmit and receive operation of the IPG. */ 1815 /* Enable transmit and receive operation of the IPG. */
1816 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) & 1816 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
@@ -2119,6 +2119,9 @@ static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2119 2119
2120static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu) 2120static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2121{ 2121{
2122 struct ipg_nic_private *sp = netdev_priv(dev);
2123 int err;
2124
2122 /* Function to accomodate changes to Maximum Transfer Unit 2125 /* Function to accomodate changes to Maximum Transfer Unit
2123 * (or MTU) of IPG NIC. Cannot use default function since 2126 * (or MTU) of IPG NIC. Cannot use default function since
2124 * the default will not allow for MTU > 1500 bytes. 2127 * the default will not allow for MTU > 1500 bytes.
@@ -2126,16 +2129,33 @@ static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2126 2129
2127 IPG_DEBUG_MSG("_nic_change_mtu\n"); 2130 IPG_DEBUG_MSG("_nic_change_mtu\n");
2128 2131
2129 /* Check that the new MTU value is between 68 (14 byte header, 46 2132 /*
2130 * byte payload, 4 byte FCS) and IPG_MAX_RXFRAME_SIZE, which 2133 * Check that the new MTU value is between 68 (14 byte header, 46 byte
2131 * corresponds to the MAXFRAMESIZE register in the IPG. 2134 * payload, 4 byte FCS) and 10 KB, which is the largest supported MTU.
2132 */ 2135 */
2133 if ((new_mtu < 68) || (new_mtu > IPG_MAX_RXFRAME_SIZE)) 2136 if (new_mtu < 68 || new_mtu > 10240)
2134 return -EINVAL; 2137 return -EINVAL;
2135 2138
2139 err = ipg_nic_stop(dev);
2140 if (err)
2141 return err;
2142
2136 dev->mtu = new_mtu; 2143 dev->mtu = new_mtu;
2137 2144
2138 return 0; 2145 sp->max_rxframe_size = new_mtu;
2146
2147 sp->rxfrag_size = new_mtu;
2148 if (sp->rxfrag_size > 4088)
2149 sp->rxfrag_size = 4088;
2150
2151 sp->rxsupport_size = sp->max_rxframe_size;
2152
2153 if (new_mtu > 0x0600)
2154 sp->is_jumbo = true;
2155 else
2156 sp->is_jumbo = false;
2157
2158 return ipg_nic_open(dev);
2139} 2159}
2140 2160
2141static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2161static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
@@ -2240,6 +2260,11 @@ static int __devinit ipg_probe(struct pci_dev *pdev,
2240 spin_lock_init(&sp->lock); 2260 spin_lock_init(&sp->lock);
2241 mutex_init(&sp->mii_mutex); 2261 mutex_init(&sp->mii_mutex);
2242 2262
2263 sp->is_jumbo = IPG_IS_JUMBO;
2264 sp->rxfrag_size = IPG_RXFRAG_SIZE;
2265 sp->rxsupport_size = IPG_RXSUPPORT_SIZE;
2266 sp->max_rxframe_size = IPG_MAX_RXFRAME_SIZE;
2267
2243 /* Declare IPG NIC functions for Ethernet device methods. 2268 /* Declare IPG NIC functions for Ethernet device methods.
2244 */ 2269 */
2245 dev->open = &ipg_nic_open; 2270 dev->open = &ipg_nic_open;
diff --git a/drivers/net/ipg.h b/drivers/net/ipg.h
index cda53887d4db..e0e718ab4c2e 100644
--- a/drivers/net/ipg.h
+++ b/drivers/net/ipg.h
@@ -536,83 +536,6 @@ enum ipg_regs {
536 */ 536 */
537#define IPG_FRAMESBETWEENTXDMACOMPLETES 0x1 537#define IPG_FRAMESBETWEENTXDMACOMPLETES 0x1
538 538
539#ifdef JUMBO_FRAME
540
541# ifdef JUMBO_FRAME_SIZE_2K
542# define JUMBO_FRAME_SIZE 2048
543# define __IPG_RXFRAG_SIZE 2048
544# else
545# ifdef JUMBO_FRAME_SIZE_3K
546# define JUMBO_FRAME_SIZE 3072
547# define __IPG_RXFRAG_SIZE 3072
548# else
549# ifdef JUMBO_FRAME_SIZE_4K
550# define JUMBO_FRAME_SIZE 4096
551# define __IPG_RXFRAG_SIZE 4088
552# else
553# ifdef JUMBO_FRAME_SIZE_5K
554# define JUMBO_FRAME_SIZE 5120
555# define __IPG_RXFRAG_SIZE 4088
556# else
557# ifdef JUMBO_FRAME_SIZE_6K
558# define JUMBO_FRAME_SIZE 6144
559# define __IPG_RXFRAG_SIZE 4088
560# else
561# ifdef JUMBO_FRAME_SIZE_7K
562# define JUMBO_FRAME_SIZE 7168
563# define __IPG_RXFRAG_SIZE 4088
564# else
565# ifdef JUMBO_FRAME_SIZE_8K
566# define JUMBO_FRAME_SIZE 8192
567# define __IPG_RXFRAG_SIZE 4088
568# else
569# ifdef JUMBO_FRAME_SIZE_9K
570# define JUMBO_FRAME_SIZE 9216
571# define __IPG_RXFRAG_SIZE 4088
572# else
573# ifdef JUMBO_FRAME_SIZE_10K
574# define JUMBO_FRAME_SIZE 10240
575# define __IPG_RXFRAG_SIZE 4088
576# else
577# define JUMBO_FRAME_SIZE 4096
578# endif
579# endif
580# endif
581# endif
582# endif
583# endif
584# endif
585# endif
586# endif
587#endif
588
589/* Size of allocated received buffers. Nominally 0x0600.
590 * Define larger if expecting jumbo frames.
591 */
592#ifdef JUMBO_FRAME
593/* IPG_TXFRAG_SIZE must <= 0x2b00, or TX will crash */
594#define IPG_TXFRAG_SIZE JUMBO_FRAME_SIZE
595#endif
596
597/* Size of allocated received buffers. Nominally 0x0600.
598 * Define larger if expecting jumbo frames.
599 */
600#ifdef JUMBO_FRAME
601/* 4088 = 4096 - 8 */
602#define IPG_RXFRAG_SIZE __IPG_RXFRAG_SIZE
603#define IPG_RXSUPPORT_SIZE IPG_MAX_RXFRAME_SIZE
604#else
605#define IPG_RXFRAG_SIZE 0x0600
606#define IPG_RXSUPPORT_SIZE IPG_RXFRAG_SIZE
607#endif
608
609/* IPG_MAX_RXFRAME_SIZE <= IPG_RXFRAG_SIZE */
610#ifdef JUMBO_FRAME
611#define IPG_MAX_RXFRAME_SIZE JUMBO_FRAME_SIZE
612#else
613#define IPG_MAX_RXFRAME_SIZE 0x0600
614#endif
615
616#define IPG_RFDLIST_LENGTH 0x100 539#define IPG_RFDLIST_LENGTH 0x100
617 540
618/* Maximum number of RFDs to process per interrupt. 541/* Maximum number of RFDs to process per interrupt.
@@ -786,9 +709,11 @@ struct ipg_nic_private {
786 unsigned int tx_dirty; 709 unsigned int tx_dirty;
787 unsigned int rx_current; 710 unsigned int rx_current;
788 unsigned int rx_dirty; 711 unsigned int rx_dirty;
789#ifdef JUMBO_FRAME 712 bool is_jumbo;
790 struct ipg_jumbo jumbo; 713 struct ipg_jumbo jumbo;
791#endif 714 unsigned long rxfrag_size;
715 unsigned long rxsupport_size;
716 unsigned long max_rxframe_size;
792 unsigned int rx_buf_sz; 717 unsigned int rx_buf_sz;
793 struct pci_dev *pdev; 718 struct pci_dev *pdev;
794 struct net_device *dev; 719 struct net_device *dev;
diff --git a/drivers/net/irda/ali-ircc.h b/drivers/net/irda/ali-ircc.h
index 07876578887f..ed35d99763d5 100644
--- a/drivers/net/irda/ali-ircc.h
+++ b/drivers/net/irda/ali-ircc.h
@@ -219,8 +219,6 @@ struct ali_ircc_cb {
219 int index; /* Instance index */ 219 int index; /* Instance index */
220 220
221 unsigned char fifo_opti_buf; 221 unsigned char fifo_opti_buf;
222
223 struct pm_dev *dev;
224}; 222};
225 223
226static inline void switch_bank(int iobase, int bank) 224static inline void switch_bank(int iobase, int bank)
diff --git a/drivers/net/irda/au1000_ircc.h b/drivers/net/irda/au1000_ircc.h
index 7a31d4659ed6..b4763f24dded 100644
--- a/drivers/net/irda/au1000_ircc.h
+++ b/drivers/net/irda/au1000_ircc.h
@@ -122,6 +122,5 @@ struct au1k_private {
122 struct timer_list timer; 122 struct timer_list timer;
123 123
124 spinlock_t lock; /* For serializing operations */ 124 spinlock_t lock; /* For serializing operations */
125 struct pm_dev *dev;
126}; 125};
127#endif /* AU1000_IRCC_H */ 126#endif /* AU1000_IRCC_H */
diff --git a/drivers/net/irda/donauboe.c b/drivers/net/irda/donauboe.c
index 1257e1a7e819..34ad189fff67 100644
--- a/drivers/net/irda/donauboe.c
+++ b/drivers/net/irda/donauboe.c
@@ -49,10 +49,6 @@
49/* Look at toshoboe.h (currently in include/net/irda) for details of */ 49/* Look at toshoboe.h (currently in include/net/irda) for details of */
50/* Where to get documentation on the chip */ 50/* Where to get documentation on the chip */
51 51
52
53static char *rcsid =
54 "$Id: donauboe.c V2.18 ven jan 10 03:14:16 2003$";
55
56/* See below for a description of the logic in this driver */ 52/* See below for a description of the logic in this driver */
57 53
58/* User servicable parts */ 54/* User servicable parts */
@@ -1677,7 +1673,7 @@ toshoboe_open (struct pci_dev *pci_dev, const struct pci_device_id *pdid)
1677 1673
1678 pci_set_drvdata(pci_dev,self); 1674 pci_set_drvdata(pci_dev,self);
1679 1675
1680 printk (KERN_INFO DRIVER_NAME ": Using multiple tasks, version %s\n", rcsid); 1676 printk (KERN_INFO DRIVER_NAME ": Using multiple tasks\n");
1681 1677
1682 return 0; 1678 return 0;
1683 1679
diff --git a/drivers/net/irda/smsc-ircc2.c b/drivers/net/irda/smsc-ircc2.c
index cfe0194fef71..78dc8e7837f0 100644
--- a/drivers/net/irda/smsc-ircc2.c
+++ b/drivers/net/irda/smsc-ircc2.c
@@ -1,5 +1,4 @@
1/********************************************************************* 1/*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 * 2 *
4 * Description: Driver for the SMC Infrared Communications Controller 3 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental. 4 * Status: Experimental.
diff --git a/drivers/net/irda/smsc-ircc2.h b/drivers/net/irda/smsc-ircc2.h
index 0c36286d87f7..317b7fd69bb3 100644
--- a/drivers/net/irda/smsc-ircc2.h
+++ b/drivers/net/irda/smsc-ircc2.h
@@ -1,5 +1,4 @@
1/********************************************************************* 1/*********************************************************************
2 * $Id: smsc-ircc2.h,v 1.12.2.1 2002/10/27 10:52:37 dip Exp $
3 * 2 *
4 * Description: Definitions for the SMC IrCC chipset 3 * Description: Definitions for the SMC IrCC chipset
5 * Status: Experimental. 4 * Status: Experimental.
diff --git a/drivers/net/irda/via-ircc.h b/drivers/net/irda/via-ircc.h
index 9d012f0dbd30..403c3f77634c 100644
--- a/drivers/net/irda/via-ircc.h
+++ b/drivers/net/irda/via-ircc.h
@@ -118,7 +118,6 @@ struct via_ircc_cb {
118 int index; /* Instance index */ 118 int index; /* Instance index */
119 119
120 struct eventflag EventFlag; 120 struct eventflag EventFlag;
121 struct pm_dev *dev;
122 unsigned int chip_id; /* to remember chip id */ 121 unsigned int chip_id; /* to remember chip id */
123 unsigned int RetryCount; 122 unsigned int RetryCount;
124 unsigned int RxDataReady; 123 unsigned int RxDataReady;
diff --git a/drivers/net/ixgb/Makefile b/drivers/net/ixgb/Makefile
index 838a5084fa00..0b20c5e62ffe 100644
--- a/drivers/net/ixgb/Makefile
+++ b/drivers/net/ixgb/Makefile
@@ -1,7 +1,7 @@
1################################################################################ 1################################################################################
2# 2#
3# Intel PRO/10GbE Linux driver 3# Intel PRO/10GbE Linux driver
4# Copyright(c) 1999 - 2006 Intel Corporation. 4# Copyright(c) 1999 - 2008 Intel Corporation.
5# 5#
6# This program is free software; you can redistribute it and/or modify it 6# This program is free software; you can redistribute it and/or modify it
7# under the terms and conditions of the GNU General Public License, 7# under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgb/ixgb.h b/drivers/net/ixgb/ixgb.h
index 16f9c756aa46..804698fc6a8f 100644
--- a/drivers/net/ixgb/ixgb.h
+++ b/drivers/net/ixgb/ixgb.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/10GbE Linux driver 3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -89,18 +89,16 @@ struct ixgb_adapter;
89 89
90 90
91/* TX/RX descriptor defines */ 91/* TX/RX descriptor defines */
92#define DEFAULT_TXD 256 92#define DEFAULT_TXD 256
93#define MAX_TXD 4096 93#define MAX_TXD 4096
94#define MIN_TXD 64 94#define MIN_TXD 64
95 95
96/* hardware cannot reliably support more than 512 descriptors owned by 96/* hardware cannot reliably support more than 512 descriptors owned by
97 * hardware descrioptor cache otherwise an unreliable ring under heavy 97 * hardware descriptor cache otherwise an unreliable ring under heavy
98 * recieve load may result */ 98 * receive load may result */
99/* #define DEFAULT_RXD 1024 */ 99#define DEFAULT_RXD 512
100/* #define MAX_RXD 4096 */ 100#define MAX_RXD 512
101#define DEFAULT_RXD 512 101#define MIN_RXD 64
102#define MAX_RXD 512
103#define MIN_RXD 64
104 102
105/* Supported Rx Buffer Sizes */ 103/* Supported Rx Buffer Sizes */
106#define IXGB_RXBUFFER_2048 2048 104#define IXGB_RXBUFFER_2048 2048
@@ -157,7 +155,6 @@ struct ixgb_adapter {
157 u32 part_num; 155 u32 part_num;
158 u16 link_speed; 156 u16 link_speed;
159 u16 link_duplex; 157 u16 link_duplex;
160 spinlock_t tx_lock;
161 struct work_struct tx_timeout_task; 158 struct work_struct tx_timeout_task;
162 159
163 struct timer_list blink_timer; 160 struct timer_list blink_timer;
diff --git a/drivers/net/ixgb/ixgb_ee.c b/drivers/net/ixgb/ixgb_ee.c
index 2f7ed52c7502..89ffa7264a12 100644
--- a/drivers/net/ixgb/ixgb_ee.c
+++ b/drivers/net/ixgb/ixgb_ee.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/10GbE Linux driver 3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -108,7 +108,7 @@ ixgb_shift_out_bits(struct ixgb_hw *hw,
108 */ 108 */
109 eecd_reg &= ~IXGB_EECD_DI; 109 eecd_reg &= ~IXGB_EECD_DI;
110 110
111 if(data & mask) 111 if (data & mask)
112 eecd_reg |= IXGB_EECD_DI; 112 eecd_reg |= IXGB_EECD_DI;
113 113
114 IXGB_WRITE_REG(hw, EECD, eecd_reg); 114 IXGB_WRITE_REG(hw, EECD, eecd_reg);
@@ -120,7 +120,7 @@ ixgb_shift_out_bits(struct ixgb_hw *hw,
120 120
121 mask = mask >> 1; 121 mask = mask >> 1;
122 122
123 } while(mask); 123 } while (mask);
124 124
125 /* We leave the "DI" bit set to "0" when we leave this routine. */ 125 /* We leave the "DI" bit set to "0" when we leave this routine. */
126 eecd_reg &= ~IXGB_EECD_DI; 126 eecd_reg &= ~IXGB_EECD_DI;
@@ -152,14 +152,14 @@ ixgb_shift_in_bits(struct ixgb_hw *hw)
152 eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI); 152 eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
153 data = 0; 153 data = 0;
154 154
155 for(i = 0; i < 16; i++) { 155 for (i = 0; i < 16; i++) {
156 data = data << 1; 156 data = data << 1;
157 ixgb_raise_clock(hw, &eecd_reg); 157 ixgb_raise_clock(hw, &eecd_reg);
158 158
159 eecd_reg = IXGB_READ_REG(hw, EECD); 159 eecd_reg = IXGB_READ_REG(hw, EECD);
160 160
161 eecd_reg &= ~(IXGB_EECD_DI); 161 eecd_reg &= ~(IXGB_EECD_DI);
162 if(eecd_reg & IXGB_EECD_DO) 162 if (eecd_reg & IXGB_EECD_DO)
163 data |= 1; 163 data |= 1;
164 164
165 ixgb_lower_clock(hw, &eecd_reg); 165 ixgb_lower_clock(hw, &eecd_reg);
@@ -205,7 +205,7 @@ ixgb_standby_eeprom(struct ixgb_hw *hw)
205 205
206 eecd_reg = IXGB_READ_REG(hw, EECD); 206 eecd_reg = IXGB_READ_REG(hw, EECD);
207 207
208 /* Deselct EEPROM */ 208 /* Deselect EEPROM */
209 eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK); 209 eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK);
210 IXGB_WRITE_REG(hw, EECD, eecd_reg); 210 IXGB_WRITE_REG(hw, EECD, eecd_reg);
211 udelay(50); 211 udelay(50);
@@ -293,14 +293,14 @@ ixgb_wait_eeprom_command(struct ixgb_hw *hw)
293 */ 293 */
294 ixgb_standby_eeprom(hw); 294 ixgb_standby_eeprom(hw);
295 295
296 /* Now read DO repeatedly until is high (equal to '1'). The EEEPROM will 296 /* Now read DO repeatedly until is high (equal to '1'). The EEPROM will
297 * signal that the command has been completed by raising the DO signal. 297 * signal that the command has been completed by raising the DO signal.
298 * If DO does not go high in 10 milliseconds, then error out. 298 * If DO does not go high in 10 milliseconds, then error out.
299 */ 299 */
300 for(i = 0; i < 200; i++) { 300 for (i = 0; i < 200; i++) {
301 eecd_reg = IXGB_READ_REG(hw, EECD); 301 eecd_reg = IXGB_READ_REG(hw, EECD);
302 302
303 if(eecd_reg & IXGB_EECD_DO) 303 if (eecd_reg & IXGB_EECD_DO)
304 return (true); 304 return (true);
305 305
306 udelay(50); 306 udelay(50);
@@ -328,10 +328,10 @@ ixgb_validate_eeprom_checksum(struct ixgb_hw *hw)
328 u16 checksum = 0; 328 u16 checksum = 0;
329 u16 i; 329 u16 i;
330 330
331 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) 331 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
332 checksum += ixgb_read_eeprom(hw, i); 332 checksum += ixgb_read_eeprom(hw, i);
333 333
334 if(checksum == (u16) EEPROM_SUM) 334 if (checksum == (u16) EEPROM_SUM)
335 return (true); 335 return (true);
336 else 336 else
337 return (false); 337 return (false);
@@ -351,7 +351,7 @@ ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
351 u16 checksum = 0; 351 u16 checksum = 0;
352 u16 i; 352 u16 i;
353 353
354 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) 354 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
355 checksum += ixgb_read_eeprom(hw, i); 355 checksum += ixgb_read_eeprom(hw, i);
356 356
357 checksum = (u16) EEPROM_SUM - checksum; 357 checksum = (u16) EEPROM_SUM - checksum;
@@ -365,7 +365,7 @@ ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
365 * 365 *
366 * hw - Struct containing variables accessed by shared code 366 * hw - Struct containing variables accessed by shared code
367 * reg - offset within the EEPROM to be written to 367 * reg - offset within the EEPROM to be written to
368 * data - 16 bit word to be writen to the EEPROM 368 * data - 16 bit word to be written to the EEPROM
369 * 369 *
370 * If ixgb_update_eeprom_checksum is not called after this function, the 370 * If ixgb_update_eeprom_checksum is not called after this function, the
371 * EEPROM will most likely contain an invalid checksum. 371 * EEPROM will most likely contain an invalid checksum.
@@ -472,7 +472,7 @@ ixgb_get_eeprom_data(struct ixgb_hw *hw)
472 ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 472 ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
473 473
474 DEBUGOUT("ixgb_ee: Reading eeprom data\n"); 474 DEBUGOUT("ixgb_ee: Reading eeprom data\n");
475 for(i = 0; i < IXGB_EEPROM_SIZE ; i++) { 475 for (i = 0; i < IXGB_EEPROM_SIZE ; i++) {
476 u16 ee_data; 476 u16 ee_data;
477 ee_data = ixgb_read_eeprom(hw, i); 477 ee_data = ixgb_read_eeprom(hw, i);
478 checksum += ee_data; 478 checksum += ee_data;
diff --git a/drivers/net/ixgb/ixgb_ee.h b/drivers/net/ixgb/ixgb_ee.h
index 4b7bd0d4a8a9..7ea12652f471 100644
--- a/drivers/net/ixgb/ixgb_ee.h
+++ b/drivers/net/ixgb/ixgb_ee.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/10GbE Linux driver 3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -34,11 +34,11 @@
34#define IXGB_ETH_LENGTH_OF_ADDRESS 6 34#define IXGB_ETH_LENGTH_OF_ADDRESS 6
35 35
36/* EEPROM Commands */ 36/* EEPROM Commands */
37#define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */ 37#define EEPROM_READ_OPCODE 0x6 /* EEPROM read opcode */
38#define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */ 38#define EEPROM_WRITE_OPCODE 0x5 /* EEPROM write opcode */
39#define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */ 39#define EEPROM_ERASE_OPCODE 0x7 /* EEPROM erase opcode */
40#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */ 40#define EEPROM_EWEN_OPCODE 0x13 /* EEPROM erase/write enable */
41#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */ 41#define EEPROM_EWDS_OPCODE 0x10 /* EEPROM erase/write disable */
42 42
43/* EEPROM MAP (Word Offsets) */ 43/* EEPROM MAP (Word Offsets) */
44#define EEPROM_IA_1_2_REG 0x0000 44#define EEPROM_IA_1_2_REG 0x0000
diff --git a/drivers/net/ixgb/ixgb_ethtool.c b/drivers/net/ixgb/ixgb_ethtool.c
index 8464d8a013b0..288ee1d0f431 100644
--- a/drivers/net/ixgb/ixgb_ethtool.c
+++ b/drivers/net/ixgb/ixgb_ethtool.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/10GbE Linux driver 3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -95,7 +95,7 @@ ixgb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
95 ecmd->port = PORT_FIBRE; 95 ecmd->port = PORT_FIBRE;
96 ecmd->transceiver = XCVR_EXTERNAL; 96 ecmd->transceiver = XCVR_EXTERNAL;
97 97
98 if(netif_carrier_ok(adapter->netdev)) { 98 if (netif_carrier_ok(adapter->netdev)) {
99 ecmd->speed = SPEED_10000; 99 ecmd->speed = SPEED_10000;
100 ecmd->duplex = DUPLEX_FULL; 100 ecmd->duplex = DUPLEX_FULL;
101 } else { 101 } else {
@@ -122,11 +122,11 @@ ixgb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
122{ 122{
123 struct ixgb_adapter *adapter = netdev_priv(netdev); 123 struct ixgb_adapter *adapter = netdev_priv(netdev);
124 124
125 if(ecmd->autoneg == AUTONEG_ENABLE || 125 if (ecmd->autoneg == AUTONEG_ENABLE ||
126 ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL) 126 ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)
127 return -EINVAL; 127 return -EINVAL;
128 128
129 if(netif_running(adapter->netdev)) { 129 if (netif_running(adapter->netdev)) {
130 ixgb_down(adapter, true); 130 ixgb_down(adapter, true);
131 ixgb_reset(adapter); 131 ixgb_reset(adapter);
132 ixgb_up(adapter); 132 ixgb_up(adapter);
@@ -143,14 +143,14 @@ ixgb_get_pauseparam(struct net_device *netdev,
143{ 143{
144 struct ixgb_adapter *adapter = netdev_priv(netdev); 144 struct ixgb_adapter *adapter = netdev_priv(netdev);
145 struct ixgb_hw *hw = &adapter->hw; 145 struct ixgb_hw *hw = &adapter->hw;
146 146
147 pause->autoneg = AUTONEG_DISABLE; 147 pause->autoneg = AUTONEG_DISABLE;
148 148
149 if(hw->fc.type == ixgb_fc_rx_pause) 149 if (hw->fc.type == ixgb_fc_rx_pause)
150 pause->rx_pause = 1; 150 pause->rx_pause = 1;
151 else if(hw->fc.type == ixgb_fc_tx_pause) 151 else if (hw->fc.type == ixgb_fc_tx_pause)
152 pause->tx_pause = 1; 152 pause->tx_pause = 1;
153 else if(hw->fc.type == ixgb_fc_full) { 153 else if (hw->fc.type == ixgb_fc_full) {
154 pause->rx_pause = 1; 154 pause->rx_pause = 1;
155 pause->tx_pause = 1; 155 pause->tx_pause = 1;
156 } 156 }
@@ -162,26 +162,26 @@ ixgb_set_pauseparam(struct net_device *netdev,
162{ 162{
163 struct ixgb_adapter *adapter = netdev_priv(netdev); 163 struct ixgb_adapter *adapter = netdev_priv(netdev);
164 struct ixgb_hw *hw = &adapter->hw; 164 struct ixgb_hw *hw = &adapter->hw;
165 165
166 if(pause->autoneg == AUTONEG_ENABLE) 166 if (pause->autoneg == AUTONEG_ENABLE)
167 return -EINVAL; 167 return -EINVAL;
168 168
169 if(pause->rx_pause && pause->tx_pause) 169 if (pause->rx_pause && pause->tx_pause)
170 hw->fc.type = ixgb_fc_full; 170 hw->fc.type = ixgb_fc_full;
171 else if(pause->rx_pause && !pause->tx_pause) 171 else if (pause->rx_pause && !pause->tx_pause)
172 hw->fc.type = ixgb_fc_rx_pause; 172 hw->fc.type = ixgb_fc_rx_pause;
173 else if(!pause->rx_pause && pause->tx_pause) 173 else if (!pause->rx_pause && pause->tx_pause)
174 hw->fc.type = ixgb_fc_tx_pause; 174 hw->fc.type = ixgb_fc_tx_pause;
175 else if(!pause->rx_pause && !pause->tx_pause) 175 else if (!pause->rx_pause && !pause->tx_pause)
176 hw->fc.type = ixgb_fc_none; 176 hw->fc.type = ixgb_fc_none;
177 177
178 if(netif_running(adapter->netdev)) { 178 if (netif_running(adapter->netdev)) {
179 ixgb_down(adapter, true); 179 ixgb_down(adapter, true);
180 ixgb_up(adapter); 180 ixgb_up(adapter);
181 ixgb_set_speed_duplex(netdev); 181 ixgb_set_speed_duplex(netdev);
182 } else 182 } else
183 ixgb_reset(adapter); 183 ixgb_reset(adapter);
184 184
185 return 0; 185 return 0;
186} 186}
187 187
@@ -200,7 +200,7 @@ ixgb_set_rx_csum(struct net_device *netdev, u32 data)
200 200
201 adapter->rx_csum = data; 201 adapter->rx_csum = data;
202 202
203 if(netif_running(netdev)) { 203 if (netif_running(netdev)) {
204 ixgb_down(adapter, true); 204 ixgb_down(adapter, true);
205 ixgb_up(adapter); 205 ixgb_up(adapter);
206 ixgb_set_speed_duplex(netdev); 206 ixgb_set_speed_duplex(netdev);
@@ -208,7 +208,7 @@ ixgb_set_rx_csum(struct net_device *netdev, u32 data)
208 ixgb_reset(adapter); 208 ixgb_reset(adapter);
209 return 0; 209 return 0;
210} 210}
211 211
212static u32 212static u32
213ixgb_get_tx_csum(struct net_device *netdev) 213ixgb_get_tx_csum(struct net_device *netdev)
214{ 214{
@@ -229,12 +229,12 @@ ixgb_set_tx_csum(struct net_device *netdev, u32 data)
229static int 229static int
230ixgb_set_tso(struct net_device *netdev, u32 data) 230ixgb_set_tso(struct net_device *netdev, u32 data)
231{ 231{
232 if(data) 232 if (data)
233 netdev->features |= NETIF_F_TSO; 233 netdev->features |= NETIF_F_TSO;
234 else 234 else
235 netdev->features &= ~NETIF_F_TSO; 235 netdev->features &= ~NETIF_F_TSO;
236 return 0; 236 return 0;
237} 237}
238 238
239static u32 239static u32
240ixgb_get_msglevel(struct net_device *netdev) 240ixgb_get_msglevel(struct net_device *netdev)
@@ -251,7 +251,7 @@ ixgb_set_msglevel(struct net_device *netdev, u32 data)
251} 251}
252#define IXGB_GET_STAT(_A_, _R_) _A_->stats._R_ 252#define IXGB_GET_STAT(_A_, _R_) _A_->stats._R_
253 253
254static int 254static int
255ixgb_get_regs_len(struct net_device *netdev) 255ixgb_get_regs_len(struct net_device *netdev)
256{ 256{
257#define IXGB_REG_DUMP_LEN 136*sizeof(u32) 257#define IXGB_REG_DUMP_LEN 136*sizeof(u32)
@@ -301,7 +301,7 @@ ixgb_get_regs(struct net_device *netdev,
301 *reg++ = IXGB_READ_REG(hw, RXCSUM); /* 20 */ 301 *reg++ = IXGB_READ_REG(hw, RXCSUM); /* 20 */
302 302
303 /* there are 16 RAR entries in hardware, we only use 3 */ 303 /* there are 16 RAR entries in hardware, we only use 3 */
304 for(i = 0; i < IXGB_ALL_RAR_ENTRIES; i++) { 304 for (i = 0; i < IXGB_ALL_RAR_ENTRIES; i++) {
305 *reg++ = IXGB_READ_REG_ARRAY(hw, RAL, (i << 1)); /*21,...,51 */ 305 *reg++ = IXGB_READ_REG_ARRAY(hw, RAL, (i << 1)); /*21,...,51 */
306 *reg++ = IXGB_READ_REG_ARRAY(hw, RAH, (i << 1)); /*22,...,52 */ 306 *reg++ = IXGB_READ_REG_ARRAY(hw, RAH, (i << 1)); /*22,...,52 */
307 } 307 }
@@ -415,7 +415,7 @@ ixgb_get_eeprom(struct net_device *netdev,
415 int i, max_len, first_word, last_word; 415 int i, max_len, first_word, last_word;
416 int ret_val = 0; 416 int ret_val = 0;
417 417
418 if(eeprom->len == 0) { 418 if (eeprom->len == 0) {
419 ret_val = -EINVAL; 419 ret_val = -EINVAL;
420 goto geeprom_error; 420 goto geeprom_error;
421 } 421 }
@@ -424,12 +424,12 @@ ixgb_get_eeprom(struct net_device *netdev,
424 424
425 max_len = ixgb_get_eeprom_len(netdev); 425 max_len = ixgb_get_eeprom_len(netdev);
426 426
427 if(eeprom->offset > eeprom->offset + eeprom->len) { 427 if (eeprom->offset > eeprom->offset + eeprom->len) {
428 ret_val = -EINVAL; 428 ret_val = -EINVAL;
429 goto geeprom_error; 429 goto geeprom_error;
430 } 430 }
431 431
432 if((eeprom->offset + eeprom->len) > max_len) 432 if ((eeprom->offset + eeprom->len) > max_len)
433 eeprom->len = (max_len - eeprom->offset); 433 eeprom->len = (max_len - eeprom->offset);
434 434
435 first_word = eeprom->offset >> 1; 435 first_word = eeprom->offset >> 1;
@@ -437,16 +437,14 @@ ixgb_get_eeprom(struct net_device *netdev,
437 437
438 eeprom_buff = kmalloc(sizeof(__le16) * 438 eeprom_buff = kmalloc(sizeof(__le16) *
439 (last_word - first_word + 1), GFP_KERNEL); 439 (last_word - first_word + 1), GFP_KERNEL);
440 if(!eeprom_buff) 440 if (!eeprom_buff)
441 return -ENOMEM; 441 return -ENOMEM;
442 442
443 /* note the eeprom was good because the driver loaded */ 443 /* note the eeprom was good because the driver loaded */
444 for(i = 0; i <= (last_word - first_word); i++) { 444 for (i = 0; i <= (last_word - first_word); i++)
445 eeprom_buff[i] = ixgb_get_eeprom_word(hw, (first_word + i)); 445 eeprom_buff[i] = ixgb_get_eeprom_word(hw, (first_word + i));
446 }
447 446
448 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 447 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
449 eeprom->len);
450 kfree(eeprom_buff); 448 kfree(eeprom_buff);
451 449
452geeprom_error: 450geeprom_error:
@@ -464,47 +462,47 @@ ixgb_set_eeprom(struct net_device *netdev,
464 int max_len, first_word, last_word; 462 int max_len, first_word, last_word;
465 u16 i; 463 u16 i;
466 464
467 if(eeprom->len == 0) 465 if (eeprom->len == 0)
468 return -EINVAL; 466 return -EINVAL;
469 467
470 if(eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 468 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
471 return -EFAULT; 469 return -EFAULT;
472 470
473 max_len = ixgb_get_eeprom_len(netdev); 471 max_len = ixgb_get_eeprom_len(netdev);
474 472
475 if(eeprom->offset > eeprom->offset + eeprom->len) 473 if (eeprom->offset > eeprom->offset + eeprom->len)
476 return -EINVAL; 474 return -EINVAL;
477 475
478 if((eeprom->offset + eeprom->len) > max_len) 476 if ((eeprom->offset + eeprom->len) > max_len)
479 eeprom->len = (max_len - eeprom->offset); 477 eeprom->len = (max_len - eeprom->offset);
480 478
481 first_word = eeprom->offset >> 1; 479 first_word = eeprom->offset >> 1;
482 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 480 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
483 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 481 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
484 if(!eeprom_buff) 482 if (!eeprom_buff)
485 return -ENOMEM; 483 return -ENOMEM;
486 484
487 ptr = (void *)eeprom_buff; 485 ptr = (void *)eeprom_buff;
488 486
489 if(eeprom->offset & 1) { 487 if (eeprom->offset & 1) {
490 /* need read/modify/write of first changed EEPROM word */ 488 /* need read/modify/write of first changed EEPROM word */
491 /* only the second byte of the word is being modified */ 489 /* only the second byte of the word is being modified */
492 eeprom_buff[0] = ixgb_read_eeprom(hw, first_word); 490 eeprom_buff[0] = ixgb_read_eeprom(hw, first_word);
493 ptr++; 491 ptr++;
494 } 492 }
495 if((eeprom->offset + eeprom->len) & 1) { 493 if ((eeprom->offset + eeprom->len) & 1) {
496 /* need read/modify/write of last changed EEPROM word */ 494 /* need read/modify/write of last changed EEPROM word */
497 /* only the first byte of the word is being modified */ 495 /* only the first byte of the word is being modified */
498 eeprom_buff[last_word - first_word] 496 eeprom_buff[last_word - first_word]
499 = ixgb_read_eeprom(hw, last_word); 497 = ixgb_read_eeprom(hw, last_word);
500 } 498 }
501 499
502 memcpy(ptr, bytes, eeprom->len); 500 memcpy(ptr, bytes, eeprom->len);
503 for(i = 0; i <= (last_word - first_word); i++) 501 for (i = 0; i <= (last_word - first_word); i++)
504 ixgb_write_eeprom(hw, first_word + i, eeprom_buff[i]); 502 ixgb_write_eeprom(hw, first_word + i, eeprom_buff[i]);
505 503
506 /* Update the checksum over the first part of the EEPROM if needed */ 504 /* Update the checksum over the first part of the EEPROM if needed */
507 if(first_word <= EEPROM_CHECKSUM_REG) 505 if (first_word <= EEPROM_CHECKSUM_REG)
508 ixgb_update_eeprom_checksum(hw); 506 ixgb_update_eeprom_checksum(hw);
509 507
510 kfree(eeprom_buff); 508 kfree(eeprom_buff);
@@ -534,7 +532,7 @@ ixgb_get_ringparam(struct net_device *netdev,
534 struct ixgb_desc_ring *txdr = &adapter->tx_ring; 532 struct ixgb_desc_ring *txdr = &adapter->tx_ring;
535 struct ixgb_desc_ring *rxdr = &adapter->rx_ring; 533 struct ixgb_desc_ring *rxdr = &adapter->rx_ring;
536 534
537 ring->rx_max_pending = MAX_RXD; 535 ring->rx_max_pending = MAX_RXD;
538 ring->tx_max_pending = MAX_TXD; 536 ring->tx_max_pending = MAX_TXD;
539 ring->rx_mini_max_pending = 0; 537 ring->rx_mini_max_pending = 0;
540 ring->rx_jumbo_max_pending = 0; 538 ring->rx_jumbo_max_pending = 0;
@@ -544,7 +542,7 @@ ixgb_get_ringparam(struct net_device *netdev,
544 ring->rx_jumbo_pending = 0; 542 ring->rx_jumbo_pending = 0;
545} 543}
546 544
547static int 545static int
548ixgb_set_ringparam(struct net_device *netdev, 546ixgb_set_ringparam(struct net_device *netdev,
549 struct ethtool_ringparam *ring) 547 struct ethtool_ringparam *ring)
550{ 548{
@@ -557,10 +555,10 @@ ixgb_set_ringparam(struct net_device *netdev,
557 tx_old = adapter->tx_ring; 555 tx_old = adapter->tx_ring;
558 rx_old = adapter->rx_ring; 556 rx_old = adapter->rx_ring;
559 557
560 if((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 558 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
561 return -EINVAL; 559 return -EINVAL;
562 560
563 if(netif_running(adapter->netdev)) 561 if (netif_running(adapter->netdev))
564 ixgb_down(adapter, true); 562 ixgb_down(adapter, true);
565 563
566 rxdr->count = max(ring->rx_pending,(u32)MIN_RXD); 564 rxdr->count = max(ring->rx_pending,(u32)MIN_RXD);
@@ -571,11 +569,11 @@ ixgb_set_ringparam(struct net_device *netdev,
571 txdr->count = min(txdr->count,(u32)MAX_TXD); 569 txdr->count = min(txdr->count,(u32)MAX_TXD);
572 txdr->count = ALIGN(txdr->count, IXGB_REQ_TX_DESCRIPTOR_MULTIPLE); 570 txdr->count = ALIGN(txdr->count, IXGB_REQ_TX_DESCRIPTOR_MULTIPLE);
573 571
574 if(netif_running(adapter->netdev)) { 572 if (netif_running(adapter->netdev)) {
575 /* Try to get new resources before deleting old */ 573 /* Try to get new resources before deleting old */
576 if((err = ixgb_setup_rx_resources(adapter))) 574 if ((err = ixgb_setup_rx_resources(adapter)))
577 goto err_setup_rx; 575 goto err_setup_rx;
578 if((err = ixgb_setup_tx_resources(adapter))) 576 if ((err = ixgb_setup_tx_resources(adapter)))
579 goto err_setup_tx; 577 goto err_setup_tx;
580 578
581 /* save the new, restore the old in order to free it, 579 /* save the new, restore the old in order to free it,
@@ -589,7 +587,7 @@ ixgb_set_ringparam(struct net_device *netdev,
589 ixgb_free_tx_resources(adapter); 587 ixgb_free_tx_resources(adapter);
590 adapter->rx_ring = rx_new; 588 adapter->rx_ring = rx_new;
591 adapter->tx_ring = tx_new; 589 adapter->tx_ring = tx_new;
592 if((err = ixgb_up(adapter))) 590 if ((err = ixgb_up(adapter)))
593 return err; 591 return err;
594 ixgb_set_speed_duplex(netdev); 592 ixgb_set_speed_duplex(netdev);
595 } 593 }
@@ -615,7 +613,7 @@ ixgb_led_blink_callback(unsigned long data)
615{ 613{
616 struct ixgb_adapter *adapter = (struct ixgb_adapter *)data; 614 struct ixgb_adapter *adapter = (struct ixgb_adapter *)data;
617 615
618 if(test_and_change_bit(IXGB_LED_ON, &adapter->led_status)) 616 if (test_and_change_bit(IXGB_LED_ON, &adapter->led_status))
619 ixgb_led_off(&adapter->hw); 617 ixgb_led_off(&adapter->hw);
620 else 618 else
621 ixgb_led_on(&adapter->hw); 619 ixgb_led_on(&adapter->hw);
@@ -631,7 +629,7 @@ ixgb_phys_id(struct net_device *netdev, u32 data)
631 if (!data) 629 if (!data)
632 data = INT_MAX; 630 data = INT_MAX;
633 631
634 if(!adapter->blink_timer.function) { 632 if (!adapter->blink_timer.function) {
635 init_timer(&adapter->blink_timer); 633 init_timer(&adapter->blink_timer);
636 adapter->blink_timer.function = ixgb_led_blink_callback; 634 adapter->blink_timer.function = ixgb_led_blink_callback;
637 adapter->blink_timer.data = (unsigned long)adapter; 635 adapter->blink_timer.data = (unsigned long)adapter;
@@ -647,7 +645,7 @@ ixgb_phys_id(struct net_device *netdev, u32 data)
647 return 0; 645 return 0;
648} 646}
649 647
650static int 648static int
651ixgb_get_sset_count(struct net_device *netdev, int sset) 649ixgb_get_sset_count(struct net_device *netdev, int sset)
652{ 650{
653 switch (sset) { 651 switch (sset) {
@@ -658,30 +656,30 @@ ixgb_get_sset_count(struct net_device *netdev, int sset)
658 } 656 }
659} 657}
660 658
661static void 659static void
662ixgb_get_ethtool_stats(struct net_device *netdev, 660ixgb_get_ethtool_stats(struct net_device *netdev,
663 struct ethtool_stats *stats, u64 *data) 661 struct ethtool_stats *stats, u64 *data)
664{ 662{
665 struct ixgb_adapter *adapter = netdev_priv(netdev); 663 struct ixgb_adapter *adapter = netdev_priv(netdev);
666 int i; 664 int i;
667 665
668 ixgb_update_stats(adapter); 666 ixgb_update_stats(adapter);
669 for(i = 0; i < IXGB_STATS_LEN; i++) { 667 for (i = 0; i < IXGB_STATS_LEN; i++) {
670 char *p = (char *)adapter+ixgb_gstrings_stats[i].stat_offset; 668 char *p = (char *)adapter+ixgb_gstrings_stats[i].stat_offset;
671 data[i] = (ixgb_gstrings_stats[i].sizeof_stat == 669 data[i] = (ixgb_gstrings_stats[i].sizeof_stat ==
672 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 670 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
673 } 671 }
674} 672}
675 673
676static void 674static void
677ixgb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 675ixgb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
678{ 676{
679 int i; 677 int i;
680 678
681 switch(stringset) { 679 switch(stringset) {
682 case ETH_SS_STATS: 680 case ETH_SS_STATS:
683 for(i=0; i < IXGB_STATS_LEN; i++) { 681 for (i = 0; i < IXGB_STATS_LEN; i++) {
684 memcpy(data + i * ETH_GSTRING_LEN, 682 memcpy(data + i * ETH_GSTRING_LEN,
685 ixgb_gstrings_stats[i].stat_string, 683 ixgb_gstrings_stats[i].stat_string,
686 ETH_GSTRING_LEN); 684 ETH_GSTRING_LEN);
687 } 685 }
diff --git a/drivers/net/ixgb/ixgb_hw.c b/drivers/net/ixgb/ixgb_hw.c
index 04d2003e24e1..11dcda0f453e 100644
--- a/drivers/net/ixgb/ixgb_hw.c
+++ b/drivers/net/ixgb/ixgb_hw.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/10GbE Linux driver 3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -125,7 +125,7 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
125 /* If we are stopped or resetting exit gracefully and wait to be 125 /* If we are stopped or resetting exit gracefully and wait to be
126 * started again before accessing the hardware. 126 * started again before accessing the hardware.
127 */ 127 */
128 if(hw->adapter_stopped) { 128 if (hw->adapter_stopped) {
129 DEBUGOUT("Exiting because the adapter is already stopped!!!\n"); 129 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
130 return false; 130 return false;
131 } 131 }
@@ -347,7 +347,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
347 347
348 /* Zero out the Multicast HASH table */ 348 /* Zero out the Multicast HASH table */
349 DEBUGOUT("Zeroing the MTA\n"); 349 DEBUGOUT("Zeroing the MTA\n");
350 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) 350 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
351 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 351 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
352 352
353 /* Zero out the VLAN Filter Table Array */ 353 /* Zero out the VLAN Filter Table Array */
@@ -371,7 +371,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
371 * hw - Struct containing variables accessed by shared code 371 * hw - Struct containing variables accessed by shared code
372 * 372 *
373 * Places the MAC address in receive address register 0 and clears the rest 373 * Places the MAC address in receive address register 0 and clears the rest
374 * of the receive addresss registers. Clears the multicast table. Assumes 374 * of the receive address registers. Clears the multicast table. Assumes
375 * the receiver is in reset when the routine is called. 375 * the receiver is in reset when the routine is called.
376 *****************************************************************************/ 376 *****************************************************************************/
377static void 377static void
@@ -413,7 +413,7 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
413 413
414 /* Zero out the other 15 receive addresses. */ 414 /* Zero out the other 15 receive addresses. */
415 DEBUGOUT("Clearing RAR[1-15]\n"); 415 DEBUGOUT("Clearing RAR[1-15]\n");
416 for(i = 1; i < IXGB_RAR_ENTRIES; i++) { 416 for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
417 /* Write high reg first to disable the AV bit first */ 417 /* Write high reg first to disable the AV bit first */
418 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 418 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
419 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 419 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
@@ -452,19 +452,18 @@ ixgb_mc_addr_list_update(struct ixgb_hw *hw,
452 452
453 /* Clear RAR[1-15] */ 453 /* Clear RAR[1-15] */
454 DEBUGOUT(" Clearing RAR[1-15]\n"); 454 DEBUGOUT(" Clearing RAR[1-15]\n");
455 for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) { 455 for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
456 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 456 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
457 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 457 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
458 } 458 }
459 459
460 /* Clear the MTA */ 460 /* Clear the MTA */
461 DEBUGOUT(" Clearing MTA\n"); 461 DEBUGOUT(" Clearing MTA\n");
462 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) { 462 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
463 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 463 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
464 }
465 464
466 /* Add the new addresses */ 465 /* Add the new addresses */
467 for(i = 0; i < mc_addr_count; i++) { 466 for (i = 0; i < mc_addr_count; i++) {
468 DEBUGOUT(" Adding the multicast addresses:\n"); 467 DEBUGOUT(" Adding the multicast addresses:\n");
469 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 468 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
470 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)], 469 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
@@ -482,7 +481,7 @@ ixgb_mc_addr_list_update(struct ixgb_hw *hw,
482 /* Place this multicast address in the RAR if there is room, * 481 /* Place this multicast address in the RAR if there is room, *
483 * else put it in the MTA 482 * else put it in the MTA
484 */ 483 */
485 if(rar_used_count < IXGB_RAR_ENTRIES) { 484 if (rar_used_count < IXGB_RAR_ENTRIES) {
486 ixgb_rar_set(hw, 485 ixgb_rar_set(hw,
487 mc_addr_list + 486 mc_addr_list +
488 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)), 487 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
@@ -649,7 +648,7 @@ ixgb_clear_vfta(struct ixgb_hw *hw)
649{ 648{
650 u32 offset; 649 u32 offset;
651 650
652 for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++) 651 for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
653 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 652 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
654 return; 653 return;
655} 654}
@@ -719,9 +718,8 @@ ixgb_setup_fc(struct ixgb_hw *hw)
719 /* Write the new settings */ 718 /* Write the new settings */
720 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); 719 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
721 720
722 if (pap_reg != 0) { 721 if (pap_reg != 0)
723 IXGB_WRITE_REG(hw, PAP, pap_reg); 722 IXGB_WRITE_REG(hw, PAP, pap_reg);
724 }
725 723
726 /* Set the flow control receive threshold registers. Normally, 724 /* Set the flow control receive threshold registers. Normally,
727 * these registers will be set to a default threshold that may be 725 * these registers will be set to a default threshold that may be
@@ -729,14 +727,14 @@ ixgb_setup_fc(struct ixgb_hw *hw)
729 * ability to transmit pause frames in not enabled, then these 727 * ability to transmit pause frames in not enabled, then these
730 * registers will be set to 0. 728 * registers will be set to 0.
731 */ 729 */
732 if(!(hw->fc.type & ixgb_fc_tx_pause)) { 730 if (!(hw->fc.type & ixgb_fc_tx_pause)) {
733 IXGB_WRITE_REG(hw, FCRTL, 0); 731 IXGB_WRITE_REG(hw, FCRTL, 0);
734 IXGB_WRITE_REG(hw, FCRTH, 0); 732 IXGB_WRITE_REG(hw, FCRTH, 0);
735 } else { 733 } else {
736 /* We need to set up the Receive Threshold high and low water 734 /* We need to set up the Receive Threshold high and low water
737 * marks as well as (optionally) enabling the transmission of XON 735 * marks as well as (optionally) enabling the transmission of XON
738 * frames. */ 736 * frames. */
739 if(hw->fc.send_xon) { 737 if (hw->fc.send_xon) {
740 IXGB_WRITE_REG(hw, FCRTL, 738 IXGB_WRITE_REG(hw, FCRTL,
741 (hw->fc.low_water | IXGB_FCRTL_XONE)); 739 (hw->fc.low_water | IXGB_FCRTL_XONE));
742 } else { 740 } else {
@@ -791,7 +789,7 @@ ixgb_read_phy_reg(struct ixgb_hw *hw,
791 ** from the CPU Write to the Ready bit assertion. 789 ** from the CPU Write to the Ready bit assertion.
792 **************************************************************/ 790 **************************************************************/
793 791
794 for(i = 0; i < 10; i++) 792 for (i = 0; i < 10; i++)
795 { 793 {
796 udelay(10); 794 udelay(10);
797 795
@@ -818,7 +816,7 @@ ixgb_read_phy_reg(struct ixgb_hw *hw,
818 ** from the CPU Write to the Ready bit assertion. 816 ** from the CPU Write to the Ready bit assertion.
819 **************************************************************/ 817 **************************************************************/
820 818
821 for(i = 0; i < 10; i++) 819 for (i = 0; i < 10; i++)
822 { 820 {
823 udelay(10); 821 udelay(10);
824 822
@@ -887,7 +885,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
887 ** from the CPU Write to the Ready bit assertion. 885 ** from the CPU Write to the Ready bit assertion.
888 **************************************************************/ 886 **************************************************************/
889 887
890 for(i = 0; i < 10; i++) 888 for (i = 0; i < 10; i++)
891 { 889 {
892 udelay(10); 890 udelay(10);
893 891
@@ -914,7 +912,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
914 ** from the CPU Write to the Ready bit assertion. 912 ** from the CPU Write to the Ready bit assertion.
915 **************************************************************/ 913 **************************************************************/
916 914
917 for(i = 0; i < 10; i++) 915 for (i = 0; i < 10; i++)
918 { 916 {
919 udelay(10); 917 udelay(10);
920 918
@@ -965,7 +963,7 @@ ixgb_check_for_link(struct ixgb_hw *hw)
965} 963}
966 964
967/****************************************************************************** 965/******************************************************************************
968 * Check for a bad link condition that may have occured. 966 * Check for a bad link condition that may have occurred.
969 * The indication is that the RFC / LFC registers may be incrementing 967 * The indication is that the RFC / LFC registers may be incrementing
970 * continually. A full adapter reset is required to recover. 968 * continually. A full adapter reset is required to recover.
971 * 969 *
@@ -1007,7 +1005,7 @@ ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
1007 DEBUGFUNC("ixgb_clear_hw_cntrs"); 1005 DEBUGFUNC("ixgb_clear_hw_cntrs");
1008 1006
1009 /* if we are stopped or resetting exit gracefully */ 1007 /* if we are stopped or resetting exit gracefully */
1010 if(hw->adapter_stopped) { 1008 if (hw->adapter_stopped) {
1011 DEBUGOUT("Exiting because the adapter is stopped!!!\n"); 1009 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
1012 return; 1010 return;
1013 } 1011 }
diff --git a/drivers/net/ixgb/ixgb_hw.h b/drivers/net/ixgb/ixgb_hw.h
index 39cfa47bea69..831fe0c58b2b 100644
--- a/drivers/net/ixgb/ixgb_hw.h
+++ b/drivers/net/ixgb/ixgb_hw.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/10GbE Linux driver 3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgb/ixgb_ids.h b/drivers/net/ixgb/ixgb_ids.h
index 180d20e793a5..2a58847f46e8 100644
--- a/drivers/net/ixgb/ixgb_ids.h
+++ b/drivers/net/ixgb/ixgb_ids.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/10GbE Linux driver 3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -38,11 +38,11 @@
38#define SUN_VENDOR_ID 0x108E 38#define SUN_VENDOR_ID 0x108E
39#define SUN_SUBVENDOR_ID 0x108E 39#define SUN_SUBVENDOR_ID 0x108E
40 40
41#define IXGB_DEVICE_ID_82597EX 0x1048 41#define IXGB_DEVICE_ID_82597EX 0x1048
42#define IXGB_DEVICE_ID_82597EX_SR 0x1A48 42#define IXGB_DEVICE_ID_82597EX_SR 0x1A48
43#define IXGB_DEVICE_ID_82597EX_LR 0x1B48 43#define IXGB_DEVICE_ID_82597EX_LR 0x1B48
44#define IXGB_SUBDEVICE_ID_A11F 0xA11F 44#define IXGB_SUBDEVICE_ID_A11F 0xA11F
45#define IXGB_SUBDEVICE_ID_A01F 0xA01F 45#define IXGB_SUBDEVICE_ID_A01F 0xA01F
46 46
47#define IXGB_DEVICE_ID_82597EX_CX4 0x109E 47#define IXGB_DEVICE_ID_82597EX_CX4 0x109E
48#define IXGB_SUBDEVICE_ID_A00C 0xA00C 48#define IXGB_SUBDEVICE_ID_A00C 0xA00C
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c
index cb8daddafa29..aa75385cd6c7 100644
--- a/drivers/net/ixgb/ixgb_main.c
+++ b/drivers/net/ixgb/ixgb_main.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/10GbE Linux driver 3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -31,14 +31,16 @@
31char ixgb_driver_name[] = "ixgb"; 31char ixgb_driver_name[] = "ixgb";
32static char ixgb_driver_string[] = "Intel(R) PRO/10GbE Network Driver"; 32static char ixgb_driver_string[] = "Intel(R) PRO/10GbE Network Driver";
33 33
34#ifndef CONFIG_IXGB_NAPI
35#define DRIVERNAPI
36#else
37#define DRIVERNAPI "-NAPI" 34#define DRIVERNAPI "-NAPI"
38#endif 35#define DRV_VERSION "1.0.135-k2" DRIVERNAPI
39#define DRV_VERSION "1.0.126-k4"DRIVERNAPI
40const char ixgb_driver_version[] = DRV_VERSION; 36const char ixgb_driver_version[] = DRV_VERSION;
41static const char ixgb_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; 37static const char ixgb_copyright[] = "Copyright (c) 1999-2008 Intel Corporation.";
38
39#define IXGB_CB_LENGTH 256
40static unsigned int copybreak __read_mostly = IXGB_CB_LENGTH;
41module_param(copybreak, uint, 0644);
42MODULE_PARM_DESC(copybreak,
43 "Maximum size of packet that is copied to a new buffer on receive");
42 44
43/* ixgb_pci_tbl - PCI Device ID Table 45/* ixgb_pci_tbl - PCI Device ID Table
44 * 46 *
@@ -55,7 +57,7 @@ static struct pci_device_id ixgb_pci_tbl[] = {
55 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 57 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
56 {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX_SR, 58 {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX_SR,
57 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 59 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
58 {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX_LR, 60 {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX_LR,
59 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 61 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
60 62
61 /* required last entry */ 63 /* required last entry */
@@ -65,16 +67,6 @@ static struct pci_device_id ixgb_pci_tbl[] = {
65MODULE_DEVICE_TABLE(pci, ixgb_pci_tbl); 67MODULE_DEVICE_TABLE(pci, ixgb_pci_tbl);
66 68
67/* Local Function Prototypes */ 69/* Local Function Prototypes */
68
69int ixgb_up(struct ixgb_adapter *adapter);
70void ixgb_down(struct ixgb_adapter *adapter, bool kill_watchdog);
71void ixgb_reset(struct ixgb_adapter *adapter);
72int ixgb_setup_tx_resources(struct ixgb_adapter *adapter);
73int ixgb_setup_rx_resources(struct ixgb_adapter *adapter);
74void ixgb_free_tx_resources(struct ixgb_adapter *adapter);
75void ixgb_free_rx_resources(struct ixgb_adapter *adapter);
76void ixgb_update_stats(struct ixgb_adapter *adapter);
77
78static int ixgb_init_module(void); 70static int ixgb_init_module(void);
79static void ixgb_exit_module(void); 71static void ixgb_exit_module(void);
80static int ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 72static int ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
@@ -96,18 +88,15 @@ static int ixgb_set_mac(struct net_device *netdev, void *p);
96static irqreturn_t ixgb_intr(int irq, void *data); 88static irqreturn_t ixgb_intr(int irq, void *data);
97static bool ixgb_clean_tx_irq(struct ixgb_adapter *adapter); 89static bool ixgb_clean_tx_irq(struct ixgb_adapter *adapter);
98 90
99#ifdef CONFIG_IXGB_NAPI 91static int ixgb_clean(struct napi_struct *, int);
100static int ixgb_clean(struct napi_struct *napi, int budget); 92static bool ixgb_clean_rx_irq(struct ixgb_adapter *, int *, int);
101static bool ixgb_clean_rx_irq(struct ixgb_adapter *adapter, 93static void ixgb_alloc_rx_buffers(struct ixgb_adapter *, int);
102 int *work_done, int work_to_do); 94
103#else
104static bool ixgb_clean_rx_irq(struct ixgb_adapter *adapter);
105#endif
106static void ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter);
107static void ixgb_tx_timeout(struct net_device *dev); 95static void ixgb_tx_timeout(struct net_device *dev);
108static void ixgb_tx_timeout_task(struct work_struct *work); 96static void ixgb_tx_timeout_task(struct work_struct *work);
97
109static void ixgb_vlan_rx_register(struct net_device *netdev, 98static void ixgb_vlan_rx_register(struct net_device *netdev,
110 struct vlan_group *grp); 99 struct vlan_group *grp);
111static void ixgb_vlan_rx_add_vid(struct net_device *netdev, u16 vid); 100static void ixgb_vlan_rx_add_vid(struct net_device *netdev, u16 vid);
112static void ixgb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid); 101static void ixgb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid);
113static void ixgb_restore_vlan(struct ixgb_adapter *adapter); 102static void ixgb_restore_vlan(struct ixgb_adapter *adapter);
@@ -118,7 +107,7 @@ static void ixgb_netpoll(struct net_device *dev);
118#endif 107#endif
119 108
120static pci_ers_result_t ixgb_io_error_detected (struct pci_dev *pdev, 109static pci_ers_result_t ixgb_io_error_detected (struct pci_dev *pdev,
121 enum pci_channel_state state); 110 enum pci_channel_state state);
122static pci_ers_result_t ixgb_io_slot_reset (struct pci_dev *pdev); 111static pci_ers_result_t ixgb_io_slot_reset (struct pci_dev *pdev);
123static void ixgb_io_resume (struct pci_dev *pdev); 112static void ixgb_io_resume (struct pci_dev *pdev);
124 113
@@ -146,14 +135,6 @@ static int debug = DEFAULT_DEBUG_LEVEL_SHIFT;
146module_param(debug, int, 0); 135module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 136MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148 137
149/* some defines for controlling descriptor fetches in h/w */
150#define RXDCTL_WTHRESH_DEFAULT 15 /* chip writes back at this many or RXT0 */
151#define RXDCTL_PTHRESH_DEFAULT 0 /* chip considers prefech below
152 * this */
153#define RXDCTL_HTHRESH_DEFAULT 0 /* chip will only prefetch if tail
154 * is pushed this many descriptors
155 * from head */
156
157/** 138/**
158 * ixgb_init_module - Driver Registration Routine 139 * ixgb_init_module - Driver Registration Routine
159 * 140 *
@@ -236,7 +217,7 @@ ixgb_up(struct ixgb_adapter *adapter)
236 ixgb_configure_tx(adapter); 217 ixgb_configure_tx(adapter);
237 ixgb_setup_rctl(adapter); 218 ixgb_setup_rctl(adapter);
238 ixgb_configure_rx(adapter); 219 ixgb_configure_rx(adapter);
239 ixgb_alloc_rx_buffers(adapter); 220 ixgb_alloc_rx_buffers(adapter, IXGB_DESC_UNUSED(&adapter->rx_ring));
240 221
241 /* disable interrupts and get the hardware into a known state */ 222 /* disable interrupts and get the hardware into a known state */
242 IXGB_WRITE_REG(&adapter->hw, IMC, 0xffffffff); 223 IXGB_WRITE_REG(&adapter->hw, IMC, 0xffffffff);
@@ -261,7 +242,7 @@ ixgb_up(struct ixgb_adapter *adapter)
261 return err; 242 return err;
262 } 243 }
263 244
264 if((hw->max_frame_size != max_frame) || 245 if ((hw->max_frame_size != max_frame) ||
265 (hw->max_frame_size != 246 (hw->max_frame_size !=
266 (IXGB_READ_REG(hw, MFS) >> IXGB_MFS_SHIFT))) { 247 (IXGB_READ_REG(hw, MFS) >> IXGB_MFS_SHIFT))) {
267 248
@@ -269,11 +250,11 @@ ixgb_up(struct ixgb_adapter *adapter)
269 250
270 IXGB_WRITE_REG(hw, MFS, hw->max_frame_size << IXGB_MFS_SHIFT); 251 IXGB_WRITE_REG(hw, MFS, hw->max_frame_size << IXGB_MFS_SHIFT);
271 252
272 if(hw->max_frame_size > 253 if (hw->max_frame_size >
273 IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH) { 254 IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH) {
274 u32 ctrl0 = IXGB_READ_REG(hw, CTRL0); 255 u32 ctrl0 = IXGB_READ_REG(hw, CTRL0);
275 256
276 if(!(ctrl0 & IXGB_CTRL0_JFE)) { 257 if (!(ctrl0 & IXGB_CTRL0_JFE)) {
277 ctrl0 |= IXGB_CTRL0_JFE; 258 ctrl0 |= IXGB_CTRL0_JFE;
278 IXGB_WRITE_REG(hw, CTRL0, ctrl0); 259 IXGB_WRITE_REG(hw, CTRL0, ctrl0);
279 } 260 }
@@ -282,9 +263,7 @@ ixgb_up(struct ixgb_adapter *adapter)
282 263
283 clear_bit(__IXGB_DOWN, &adapter->flags); 264 clear_bit(__IXGB_DOWN, &adapter->flags);
284 265
285#ifdef CONFIG_IXGB_NAPI
286 napi_enable(&adapter->napi); 266 napi_enable(&adapter->napi);
287#endif
288 ixgb_irq_enable(adapter); 267 ixgb_irq_enable(adapter);
289 268
290 mod_timer(&adapter->watchdog_timer, jiffies); 269 mod_timer(&adapter->watchdog_timer, jiffies);
@@ -300,9 +279,7 @@ ixgb_down(struct ixgb_adapter *adapter, bool kill_watchdog)
300 /* prevent the interrupt handler from restarting watchdog */ 279 /* prevent the interrupt handler from restarting watchdog */
301 set_bit(__IXGB_DOWN, &adapter->flags); 280 set_bit(__IXGB_DOWN, &adapter->flags);
302 281
303#ifdef CONFIG_IXGB_NAPI
304 napi_disable(&adapter->napi); 282 napi_disable(&adapter->napi);
305#endif
306 /* waiting for NAPI to complete can re-enable interrupts */ 283 /* waiting for NAPI to complete can re-enable interrupts */
307 ixgb_irq_disable(adapter); 284 ixgb_irq_disable(adapter);
308 free_irq(adapter->pdev->irq, netdev); 285 free_irq(adapter->pdev->irq, netdev);
@@ -310,7 +287,7 @@ ixgb_down(struct ixgb_adapter *adapter, bool kill_watchdog)
310 if (adapter->have_msi) 287 if (adapter->have_msi)
311 pci_disable_msi(adapter->pdev); 288 pci_disable_msi(adapter->pdev);
312 289
313 if(kill_watchdog) 290 if (kill_watchdog)
314 del_timer_sync(&adapter->watchdog_timer); 291 del_timer_sync(&adapter->watchdog_timer);
315 292
316 adapter->link_speed = 0; 293 adapter->link_speed = 0;
@@ -357,27 +334,25 @@ ixgb_reset(struct ixgb_adapter *adapter)
357 **/ 334 **/
358 335
359static int __devinit 336static int __devinit
360ixgb_probe(struct pci_dev *pdev, 337ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
361 const struct pci_device_id *ent)
362{ 338{
363 struct net_device *netdev = NULL; 339 struct net_device *netdev = NULL;
364 struct ixgb_adapter *adapter; 340 struct ixgb_adapter *adapter;
365 static int cards_found = 0; 341 static int cards_found = 0;
366 unsigned long mmio_start;
367 int mmio_len;
368 int pci_using_dac; 342 int pci_using_dac;
369 int i; 343 int i;
370 int err; 344 int err;
371 345
372 if((err = pci_enable_device(pdev))) 346 err = pci_enable_device(pdev);
347 if (err)
373 return err; 348 return err;
374 349
375 if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) && 350 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
376 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) { 351 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
377 pci_using_dac = 1; 352 pci_using_dac = 1;
378 } else { 353 } else {
379 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) || 354 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) ||
380 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) { 355 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
381 printk(KERN_ERR 356 printk(KERN_ERR
382 "ixgb: No usable DMA configuration, aborting\n"); 357 "ixgb: No usable DMA configuration, aborting\n");
383 goto err_dma_mask; 358 goto err_dma_mask;
@@ -385,13 +360,14 @@ ixgb_probe(struct pci_dev *pdev,
385 pci_using_dac = 0; 360 pci_using_dac = 0;
386 } 361 }
387 362
388 if((err = pci_request_regions(pdev, ixgb_driver_name))) 363 err = pci_request_regions(pdev, ixgb_driver_name);
364 if (err)
389 goto err_request_regions; 365 goto err_request_regions;
390 366
391 pci_set_master(pdev); 367 pci_set_master(pdev);
392 368
393 netdev = alloc_etherdev(sizeof(struct ixgb_adapter)); 369 netdev = alloc_etherdev(sizeof(struct ixgb_adapter));
394 if(!netdev) { 370 if (!netdev) {
395 err = -ENOMEM; 371 err = -ENOMEM;
396 goto err_alloc_etherdev; 372 goto err_alloc_etherdev;
397 } 373 }
@@ -405,19 +381,17 @@ ixgb_probe(struct pci_dev *pdev,
405 adapter->hw.back = adapter; 381 adapter->hw.back = adapter;
406 adapter->msg_enable = netif_msg_init(debug, DEFAULT_DEBUG_LEVEL_SHIFT); 382 adapter->msg_enable = netif_msg_init(debug, DEFAULT_DEBUG_LEVEL_SHIFT);
407 383
408 mmio_start = pci_resource_start(pdev, BAR_0); 384 adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, BAR_0),
409 mmio_len = pci_resource_len(pdev, BAR_0); 385 pci_resource_len(pdev, BAR_0));
410 386 if (!adapter->hw.hw_addr) {
411 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
412 if(!adapter->hw.hw_addr) {
413 err = -EIO; 387 err = -EIO;
414 goto err_ioremap; 388 goto err_ioremap;
415 } 389 }
416 390
417 for(i = BAR_1; i <= BAR_5; i++) { 391 for (i = BAR_1; i <= BAR_5; i++) {
418 if(pci_resource_len(pdev, i) == 0) 392 if (pci_resource_len(pdev, i) == 0)
419 continue; 393 continue;
420 if(pci_resource_flags(pdev, i) & IORESOURCE_IO) { 394 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
421 adapter->hw.io_base = pci_resource_start(pdev, i); 395 adapter->hw.io_base = pci_resource_start(pdev, i);
422 break; 396 break;
423 } 397 }
@@ -433,9 +407,7 @@ ixgb_probe(struct pci_dev *pdev,
433 ixgb_set_ethtool_ops(netdev); 407 ixgb_set_ethtool_ops(netdev);
434 netdev->tx_timeout = &ixgb_tx_timeout; 408 netdev->tx_timeout = &ixgb_tx_timeout;
435 netdev->watchdog_timeo = 5 * HZ; 409 netdev->watchdog_timeo = 5 * HZ;
436#ifdef CONFIG_IXGB_NAPI
437 netif_napi_add(netdev, &adapter->napi, ixgb_clean, 64); 410 netif_napi_add(netdev, &adapter->napi, ixgb_clean, 64);
438#endif
439 netdev->vlan_rx_register = ixgb_vlan_rx_register; 411 netdev->vlan_rx_register = ixgb_vlan_rx_register;
440 netdev->vlan_rx_add_vid = ixgb_vlan_rx_add_vid; 412 netdev->vlan_rx_add_vid = ixgb_vlan_rx_add_vid;
441 netdev->vlan_rx_kill_vid = ixgb_vlan_rx_kill_vid; 413 netdev->vlan_rx_kill_vid = ixgb_vlan_rx_kill_vid;
@@ -444,9 +416,6 @@ ixgb_probe(struct pci_dev *pdev,
444#endif 416#endif
445 417
446 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 418 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
447 netdev->mem_start = mmio_start;
448 netdev->mem_end = mmio_start + mmio_len;
449 netdev->base_addr = adapter->hw.io_base;
450 419
451 adapter->bd_number = cards_found; 420 adapter->bd_number = cards_found;
452 adapter->link_speed = 0; 421 adapter->link_speed = 0;
@@ -454,7 +423,8 @@ ixgb_probe(struct pci_dev *pdev,
454 423
455 /* setup the private structure */ 424 /* setup the private structure */
456 425
457 if((err = ixgb_sw_init(adapter))) 426 err = ixgb_sw_init(adapter);
427 if (err)
458 goto err_sw_init; 428 goto err_sw_init;
459 429
460 netdev->features = NETIF_F_SG | 430 netdev->features = NETIF_F_SG |
@@ -463,16 +433,13 @@ ixgb_probe(struct pci_dev *pdev,
463 NETIF_F_HW_VLAN_RX | 433 NETIF_F_HW_VLAN_RX |
464 NETIF_F_HW_VLAN_FILTER; 434 NETIF_F_HW_VLAN_FILTER;
465 netdev->features |= NETIF_F_TSO; 435 netdev->features |= NETIF_F_TSO;
466#ifdef NETIF_F_LLTX
467 netdev->features |= NETIF_F_LLTX;
468#endif
469 436
470 if(pci_using_dac) 437 if (pci_using_dac)
471 netdev->features |= NETIF_F_HIGHDMA; 438 netdev->features |= NETIF_F_HIGHDMA;
472 439
473 /* make sure the EEPROM is good */ 440 /* make sure the EEPROM is good */
474 441
475 if(!ixgb_validate_eeprom_checksum(&adapter->hw)) { 442 if (!ixgb_validate_eeprom_checksum(&adapter->hw)) {
476 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n"); 443 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
477 err = -EIO; 444 err = -EIO;
478 goto err_eeprom; 445 goto err_eeprom;
@@ -481,7 +448,7 @@ ixgb_probe(struct pci_dev *pdev,
481 ixgb_get_ee_mac_addr(&adapter->hw, netdev->dev_addr); 448 ixgb_get_ee_mac_addr(&adapter->hw, netdev->dev_addr);
482 memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len); 449 memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
483 450
484 if(!is_valid_ether_addr(netdev->perm_addr)) { 451 if (!is_valid_ether_addr(netdev->perm_addr)) {
485 DPRINTK(PROBE, ERR, "Invalid MAC Address\n"); 452 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
486 err = -EIO; 453 err = -EIO;
487 goto err_eeprom; 454 goto err_eeprom;
@@ -496,7 +463,8 @@ ixgb_probe(struct pci_dev *pdev,
496 INIT_WORK(&adapter->tx_timeout_task, ixgb_tx_timeout_task); 463 INIT_WORK(&adapter->tx_timeout_task, ixgb_tx_timeout_task);
497 464
498 strcpy(netdev->name, "eth%d"); 465 strcpy(netdev->name, "eth%d");
499 if((err = register_netdev(netdev))) 466 err = register_netdev(netdev);
467 if (err)
500 goto err_register; 468 goto err_register;
501 469
502 /* we're going to reset, so assume we have no link for now */ 470 /* we're going to reset, so assume we have no link for now */
@@ -543,6 +511,8 @@ ixgb_remove(struct pci_dev *pdev)
543 struct net_device *netdev = pci_get_drvdata(pdev); 511 struct net_device *netdev = pci_get_drvdata(pdev);
544 struct ixgb_adapter *adapter = netdev_priv(netdev); 512 struct ixgb_adapter *adapter = netdev_priv(netdev);
545 513
514 flush_scheduled_work();
515
546 unregister_netdev(netdev); 516 unregister_netdev(netdev);
547 517
548 iounmap(adapter->hw.hw_addr); 518 iounmap(adapter->hw.hw_addr);
@@ -575,13 +545,13 @@ ixgb_sw_init(struct ixgb_adapter *adapter)
575 hw->subsystem_id = pdev->subsystem_device; 545 hw->subsystem_id = pdev->subsystem_device;
576 546
577 hw->max_frame_size = netdev->mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH; 547 hw->max_frame_size = netdev->mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
578 adapter->rx_buffer_len = hw->max_frame_size; 548 adapter->rx_buffer_len = hw->max_frame_size + 8; /* + 8 for errata */
579 549
580 if((hw->device_id == IXGB_DEVICE_ID_82597EX) 550 if ((hw->device_id == IXGB_DEVICE_ID_82597EX)
581 || (hw->device_id == IXGB_DEVICE_ID_82597EX_CX4) 551 || (hw->device_id == IXGB_DEVICE_ID_82597EX_CX4)
582 || (hw->device_id == IXGB_DEVICE_ID_82597EX_LR) 552 || (hw->device_id == IXGB_DEVICE_ID_82597EX_LR)
583 || (hw->device_id == IXGB_DEVICE_ID_82597EX_SR)) 553 || (hw->device_id == IXGB_DEVICE_ID_82597EX_SR))
584 hw->mac_type = ixgb_82597; 554 hw->mac_type = ixgb_82597;
585 else { 555 else {
586 /* should never have loaded on this device */ 556 /* should never have loaded on this device */
587 DPRINTK(PROBE, ERR, "unsupported device id\n"); 557 DPRINTK(PROBE, ERR, "unsupported device id\n");
@@ -590,8 +560,6 @@ ixgb_sw_init(struct ixgb_adapter *adapter)
590 /* enable flow control to be programmed */ 560 /* enable flow control to be programmed */
591 hw->fc.send_xon = 1; 561 hw->fc.send_xon = 1;
592 562
593 spin_lock_init(&adapter->tx_lock);
594
595 set_bit(__IXGB_DOWN, &adapter->flags); 563 set_bit(__IXGB_DOWN, &adapter->flags);
596 return 0; 564 return 0;
597} 565}
@@ -616,16 +584,18 @@ ixgb_open(struct net_device *netdev)
616 int err; 584 int err;
617 585
618 /* allocate transmit descriptors */ 586 /* allocate transmit descriptors */
619 587 err = ixgb_setup_tx_resources(adapter);
620 if((err = ixgb_setup_tx_resources(adapter))) 588 if (err)
621 goto err_setup_tx; 589 goto err_setup_tx;
622 590
623 /* allocate receive descriptors */ 591 /* allocate receive descriptors */
624 592
625 if((err = ixgb_setup_rx_resources(adapter))) 593 err = ixgb_setup_rx_resources(adapter);
594 if (err)
626 goto err_setup_rx; 595 goto err_setup_rx;
627 596
628 if((err = ixgb_up(adapter))) 597 err = ixgb_up(adapter);
598 if (err)
629 goto err_up; 599 goto err_up;
630 600
631 return 0; 601 return 0;
@@ -681,7 +651,7 @@ ixgb_setup_tx_resources(struct ixgb_adapter *adapter)
681 651
682 size = sizeof(struct ixgb_buffer) * txdr->count; 652 size = sizeof(struct ixgb_buffer) * txdr->count;
683 txdr->buffer_info = vmalloc(size); 653 txdr->buffer_info = vmalloc(size);
684 if(!txdr->buffer_info) { 654 if (!txdr->buffer_info) {
685 DPRINTK(PROBE, ERR, 655 DPRINTK(PROBE, ERR,
686 "Unable to allocate transmit descriptor ring memory\n"); 656 "Unable to allocate transmit descriptor ring memory\n");
687 return -ENOMEM; 657 return -ENOMEM;
@@ -694,7 +664,7 @@ ixgb_setup_tx_resources(struct ixgb_adapter *adapter)
694 txdr->size = ALIGN(txdr->size, 4096); 664 txdr->size = ALIGN(txdr->size, 4096);
695 665
696 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma); 666 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
697 if(!txdr->desc) { 667 if (!txdr->desc) {
698 vfree(txdr->buffer_info); 668 vfree(txdr->buffer_info);
699 DPRINTK(PROBE, ERR, 669 DPRINTK(PROBE, ERR,
700 "Unable to allocate transmit descriptor memory\n"); 670 "Unable to allocate transmit descriptor memory\n");
@@ -723,8 +693,8 @@ ixgb_configure_tx(struct ixgb_adapter *adapter)
723 u32 tctl; 693 u32 tctl;
724 struct ixgb_hw *hw = &adapter->hw; 694 struct ixgb_hw *hw = &adapter->hw;
725 695
726 /* Setup the Base and Length of the Tx Descriptor Ring 696 /* Setup the Base and Length of the Tx Descriptor Ring
727 * tx_ring.dma can be either a 32 or 64 bit value 697 * tx_ring.dma can be either a 32 or 64 bit value
728 */ 698 */
729 699
730 IXGB_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL)); 700 IXGB_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
@@ -750,8 +720,8 @@ ixgb_configure_tx(struct ixgb_adapter *adapter)
750 720
751 /* Setup Transmit Descriptor Settings for this adapter */ 721 /* Setup Transmit Descriptor Settings for this adapter */
752 adapter->tx_cmd_type = 722 adapter->tx_cmd_type =
753 IXGB_TX_DESC_TYPE 723 IXGB_TX_DESC_TYPE |
754 | (adapter->tx_int_delay_enable ? IXGB_TX_DESC_CMD_IDE : 0); 724 (adapter->tx_int_delay_enable ? IXGB_TX_DESC_CMD_IDE : 0);
755} 725}
756 726
757/** 727/**
@@ -770,7 +740,7 @@ ixgb_setup_rx_resources(struct ixgb_adapter *adapter)
770 740
771 size = sizeof(struct ixgb_buffer) * rxdr->count; 741 size = sizeof(struct ixgb_buffer) * rxdr->count;
772 rxdr->buffer_info = vmalloc(size); 742 rxdr->buffer_info = vmalloc(size);
773 if(!rxdr->buffer_info) { 743 if (!rxdr->buffer_info) {
774 DPRINTK(PROBE, ERR, 744 DPRINTK(PROBE, ERR,
775 "Unable to allocate receive descriptor ring\n"); 745 "Unable to allocate receive descriptor ring\n");
776 return -ENOMEM; 746 return -ENOMEM;
@@ -784,7 +754,7 @@ ixgb_setup_rx_resources(struct ixgb_adapter *adapter)
784 754
785 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma); 755 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
786 756
787 if(!rxdr->desc) { 757 if (!rxdr->desc) {
788 vfree(rxdr->buffer_info); 758 vfree(rxdr->buffer_info);
789 DPRINTK(PROBE, ERR, 759 DPRINTK(PROBE, ERR,
790 "Unable to allocate receive descriptors\n"); 760 "Unable to allocate receive descriptors\n");
@@ -813,8 +783,8 @@ ixgb_setup_rctl(struct ixgb_adapter *adapter)
813 rctl &= ~(3 << IXGB_RCTL_MO_SHIFT); 783 rctl &= ~(3 << IXGB_RCTL_MO_SHIFT);
814 784
815 rctl |= 785 rctl |=
816 IXGB_RCTL_BAM | IXGB_RCTL_RDMTS_1_2 | 786 IXGB_RCTL_BAM | IXGB_RCTL_RDMTS_1_2 |
817 IXGB_RCTL_RXEN | IXGB_RCTL_CFF | 787 IXGB_RCTL_RXEN | IXGB_RCTL_CFF |
818 (adapter->hw.mc_filter_type << IXGB_RCTL_MO_SHIFT); 788 (adapter->hw.mc_filter_type << IXGB_RCTL_MO_SHIFT);
819 789
820 rctl |= IXGB_RCTL_SECRC; 790 rctl |= IXGB_RCTL_SECRC;
@@ -846,7 +816,6 @@ ixgb_configure_rx(struct ixgb_adapter *adapter)
846 struct ixgb_hw *hw = &adapter->hw; 816 struct ixgb_hw *hw = &adapter->hw;
847 u32 rctl; 817 u32 rctl;
848 u32 rxcsum; 818 u32 rxcsum;
849 u32 rxdctl;
850 819
851 /* make sure receives are disabled while setting up the descriptors */ 820 /* make sure receives are disabled while setting up the descriptors */
852 821
@@ -868,18 +837,12 @@ ixgb_configure_rx(struct ixgb_adapter *adapter)
868 IXGB_WRITE_REG(hw, RDH, 0); 837 IXGB_WRITE_REG(hw, RDH, 0);
869 IXGB_WRITE_REG(hw, RDT, 0); 838 IXGB_WRITE_REG(hw, RDT, 0);
870 839
871 /* set up pre-fetching of receive buffers so we get some before we 840 /* due to the hardware errata with RXDCTL, we are unable to use any of
872 * run out (default hardware behavior is to run out before fetching 841 * the performance enhancing features of it without causing other
873 * more). This sets up to fetch if HTHRESH rx descriptors are avail 842 * subtle bugs, some of the bugs could include receive length
874 * and the descriptors in hw cache are below PTHRESH. This avoids 843 * corruption at high data rates (WTHRESH > 0) and/or receive
875 * the hardware behavior of fetching <=512 descriptors in a single 844 * descriptor ring irregularites (particularly in hardware cache) */
876 * burst that pre-empts all other activity, usually causing fifo 845 IXGB_WRITE_REG(hw, RXDCTL, 0);
877 * overflows. */
878 /* use WTHRESH to burst write 16 descriptors or burst when RXT0 */
879 rxdctl = RXDCTL_WTHRESH_DEFAULT << IXGB_RXDCTL_WTHRESH_SHIFT |
880 RXDCTL_HTHRESH_DEFAULT << IXGB_RXDCTL_HTHRESH_SHIFT |
881 RXDCTL_PTHRESH_DEFAULT << IXGB_RXDCTL_PTHRESH_SHIFT;
882 IXGB_WRITE_REG(hw, RXDCTL, rxdctl);
883 846
884 /* Enable Receive Checksum Offload for TCP and UDP */ 847 /* Enable Receive Checksum Offload for TCP and UDP */
885 if (adapter->rx_csum) { 848 if (adapter->rx_csum) {
@@ -918,7 +881,7 @@ ixgb_free_tx_resources(struct ixgb_adapter *adapter)
918 881
919static void 882static void
920ixgb_unmap_and_free_tx_resource(struct ixgb_adapter *adapter, 883ixgb_unmap_and_free_tx_resource(struct ixgb_adapter *adapter,
921 struct ixgb_buffer *buffer_info) 884 struct ixgb_buffer *buffer_info)
922{ 885{
923 struct pci_dev *pdev = adapter->pdev; 886 struct pci_dev *pdev = adapter->pdev;
924 887
@@ -926,8 +889,10 @@ ixgb_unmap_and_free_tx_resource(struct ixgb_adapter *adapter,
926 pci_unmap_page(pdev, buffer_info->dma, buffer_info->length, 889 pci_unmap_page(pdev, buffer_info->dma, buffer_info->length,
927 PCI_DMA_TODEVICE); 890 PCI_DMA_TODEVICE);
928 891
892 /* okay to call kfree_skb here instead of kfree_skb_any because
893 * this is never called in interrupt context */
929 if (buffer_info->skb) 894 if (buffer_info->skb)
930 dev_kfree_skb_any(buffer_info->skb); 895 dev_kfree_skb(buffer_info->skb);
931 896
932 buffer_info->skb = NULL; 897 buffer_info->skb = NULL;
933 buffer_info->dma = 0; 898 buffer_info->dma = 0;
@@ -952,7 +917,7 @@ ixgb_clean_tx_ring(struct ixgb_adapter *adapter)
952 917
953 /* Free all the Tx ring sk_buffs */ 918 /* Free all the Tx ring sk_buffs */
954 919
955 for(i = 0; i < tx_ring->count; i++) { 920 for (i = 0; i < tx_ring->count; i++) {
956 buffer_info = &tx_ring->buffer_info[i]; 921 buffer_info = &tx_ring->buffer_info[i];
957 ixgb_unmap_and_free_tx_resource(adapter, buffer_info); 922 ixgb_unmap_and_free_tx_resource(adapter, buffer_info);
958 } 923 }
@@ -1010,9 +975,9 @@ ixgb_clean_rx_ring(struct ixgb_adapter *adapter)
1010 975
1011 /* Free all the Rx ring sk_buffs */ 976 /* Free all the Rx ring sk_buffs */
1012 977
1013 for(i = 0; i < rx_ring->count; i++) { 978 for (i = 0; i < rx_ring->count; i++) {
1014 buffer_info = &rx_ring->buffer_info[i]; 979 buffer_info = &rx_ring->buffer_info[i];
1015 if(buffer_info->skb) { 980 if (buffer_info->skb) {
1016 981
1017 pci_unmap_single(pdev, 982 pci_unmap_single(pdev,
1018 buffer_info->dma, 983 buffer_info->dma,
@@ -1053,7 +1018,7 @@ ixgb_set_mac(struct net_device *netdev, void *p)
1053 struct ixgb_adapter *adapter = netdev_priv(netdev); 1018 struct ixgb_adapter *adapter = netdev_priv(netdev);
1054 struct sockaddr *addr = p; 1019 struct sockaddr *addr = p;
1055 1020
1056 if(!is_valid_ether_addr(addr->sa_data)) 1021 if (!is_valid_ether_addr(addr->sa_data))
1057 return -EADDRNOTAVAIL; 1022 return -EADDRNOTAVAIL;
1058 1023
1059 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1024 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
@@ -1086,16 +1051,20 @@ ixgb_set_multi(struct net_device *netdev)
1086 1051
1087 rctl = IXGB_READ_REG(hw, RCTL); 1052 rctl = IXGB_READ_REG(hw, RCTL);
1088 1053
1089 if(netdev->flags & IFF_PROMISC) { 1054 if (netdev->flags & IFF_PROMISC) {
1090 rctl |= (IXGB_RCTL_UPE | IXGB_RCTL_MPE); 1055 rctl |= (IXGB_RCTL_UPE | IXGB_RCTL_MPE);
1091 } else if(netdev->flags & IFF_ALLMULTI) { 1056 rctl &= ~IXGB_RCTL_VFE;
1092 rctl |= IXGB_RCTL_MPE;
1093 rctl &= ~IXGB_RCTL_UPE;
1094 } else { 1057 } else {
1095 rctl &= ~(IXGB_RCTL_UPE | IXGB_RCTL_MPE); 1058 if (netdev->flags & IFF_ALLMULTI) {
1059 rctl |= IXGB_RCTL_MPE;
1060 rctl &= ~IXGB_RCTL_UPE;
1061 } else {
1062 rctl &= ~(IXGB_RCTL_UPE | IXGB_RCTL_MPE);
1063 }
1064 rctl |= IXGB_RCTL_VFE;
1096 } 1065 }
1097 1066
1098 if(netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES) { 1067 if (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES) {
1099 rctl |= IXGB_RCTL_MPE; 1068 rctl |= IXGB_RCTL_MPE;
1100 IXGB_WRITE_REG(hw, RCTL, rctl); 1069 IXGB_WRITE_REG(hw, RCTL, rctl);
1101 } else { 1070 } else {
@@ -1104,10 +1073,11 @@ ixgb_set_multi(struct net_device *netdev)
1104 1073
1105 IXGB_WRITE_REG(hw, RCTL, rctl); 1074 IXGB_WRITE_REG(hw, RCTL, rctl);
1106 1075
1107 for(i = 0, mc_ptr = netdev->mc_list; mc_ptr; 1076 for (i = 0, mc_ptr = netdev->mc_list;
1108 i++, mc_ptr = mc_ptr->next) 1077 mc_ptr;
1078 i++, mc_ptr = mc_ptr->next)
1109 memcpy(&mta[i * IXGB_ETH_LENGTH_OF_ADDRESS], 1079 memcpy(&mta[i * IXGB_ETH_LENGTH_OF_ADDRESS],
1110 mc_ptr->dmi_addr, IXGB_ETH_LENGTH_OF_ADDRESS); 1080 mc_ptr->dmi_addr, IXGB_ETH_LENGTH_OF_ADDRESS);
1111 1081
1112 ixgb_mc_addr_list_update(hw, mta, netdev->mc_count, 0); 1082 ixgb_mc_addr_list_update(hw, mta, netdev->mc_count, 0);
1113 } 1083 }
@@ -1132,8 +1102,8 @@ ixgb_watchdog(unsigned long data)
1132 netif_stop_queue(netdev); 1102 netif_stop_queue(netdev);
1133 } 1103 }
1134 1104
1135 if(adapter->hw.link_up) { 1105 if (adapter->hw.link_up) {
1136 if(!netif_carrier_ok(netdev)) { 1106 if (!netif_carrier_ok(netdev)) {
1137 DPRINTK(LINK, INFO, 1107 DPRINTK(LINK, INFO,
1138 "NIC Link is Up 10000 Mbps Full Duplex\n"); 1108 "NIC Link is Up 10000 Mbps Full Duplex\n");
1139 adapter->link_speed = 10000; 1109 adapter->link_speed = 10000;
@@ -1142,7 +1112,7 @@ ixgb_watchdog(unsigned long data)
1142 netif_wake_queue(netdev); 1112 netif_wake_queue(netdev);
1143 } 1113 }
1144 } else { 1114 } else {
1145 if(netif_carrier_ok(netdev)) { 1115 if (netif_carrier_ok(netdev)) {
1146 adapter->link_speed = 0; 1116 adapter->link_speed = 0;
1147 adapter->link_duplex = 0; 1117 adapter->link_duplex = 0;
1148 DPRINTK(LINK, INFO, "NIC Link is Down\n"); 1118 DPRINTK(LINK, INFO, "NIC Link is Down\n");
@@ -1154,8 +1124,8 @@ ixgb_watchdog(unsigned long data)
1154 1124
1155 ixgb_update_stats(adapter); 1125 ixgb_update_stats(adapter);
1156 1126
1157 if(!netif_carrier_ok(netdev)) { 1127 if (!netif_carrier_ok(netdev)) {
1158 if(IXGB_DESC_UNUSED(txdr) + 1 < txdr->count) { 1128 if (IXGB_DESC_UNUSED(txdr) + 1 < txdr->count) {
1159 /* We've lost link, so the controller stops DMA, 1129 /* We've lost link, so the controller stops DMA,
1160 * but we've got queued Tx work that's never going 1130 * but we've got queued Tx work that's never going
1161 * to get done, so reset controller to flush Tx. 1131 * to get done, so reset controller to flush Tx.
@@ -1227,7 +1197,7 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
1227 context_desc->hdr_len = hdr_len; 1197 context_desc->hdr_len = hdr_len;
1228 context_desc->status = 0; 1198 context_desc->status = 0;
1229 context_desc->cmd_type_len = cpu_to_le32( 1199 context_desc->cmd_type_len = cpu_to_le32(
1230 IXGB_CONTEXT_DESC_TYPE 1200 IXGB_CONTEXT_DESC_TYPE
1231 | IXGB_CONTEXT_DESC_CMD_TSE 1201 | IXGB_CONTEXT_DESC_CMD_TSE
1232 | IXGB_CONTEXT_DESC_CMD_IP 1202 | IXGB_CONTEXT_DESC_CMD_IP
1233 | IXGB_CONTEXT_DESC_CMD_TCP 1203 | IXGB_CONTEXT_DESC_CMD_TCP
@@ -1235,7 +1205,7 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
1235 | (skb->len - (hdr_len))); 1205 | (skb->len - (hdr_len)));
1236 1206
1237 1207
1238 if(++i == adapter->tx_ring.count) i = 0; 1208 if (++i == adapter->tx_ring.count) i = 0;
1239 adapter->tx_ring.next_to_use = i; 1209 adapter->tx_ring.next_to_use = i;
1240 1210
1241 return 1; 1211 return 1;
@@ -1251,7 +1221,7 @@ ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
1251 unsigned int i; 1221 unsigned int i;
1252 u8 css, cso; 1222 u8 css, cso;
1253 1223
1254 if(likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1224 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1255 struct ixgb_buffer *buffer_info; 1225 struct ixgb_buffer *buffer_info;
1256 css = skb_transport_offset(skb); 1226 css = skb_transport_offset(skb);
1257 cso = css + skb->csum_offset; 1227 cso = css + skb->csum_offset;
@@ -1273,7 +1243,7 @@ ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
1273 cpu_to_le32(IXGB_CONTEXT_DESC_TYPE 1243 cpu_to_le32(IXGB_CONTEXT_DESC_TYPE
1274 | IXGB_TX_DESC_CMD_IDE); 1244 | IXGB_TX_DESC_CMD_IDE);
1275 1245
1276 if(++i == adapter->tx_ring.count) i = 0; 1246 if (++i == adapter->tx_ring.count) i = 0;
1277 adapter->tx_ring.next_to_use = i; 1247 adapter->tx_ring.next_to_use = i;
1278 1248
1279 return true; 1249 return true;
@@ -1302,7 +1272,7 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb,
1302 1272
1303 i = tx_ring->next_to_use; 1273 i = tx_ring->next_to_use;
1304 1274
1305 while(len) { 1275 while (len) {
1306 buffer_info = &tx_ring->buffer_info[i]; 1276 buffer_info = &tx_ring->buffer_info[i];
1307 size = min(len, IXGB_MAX_DATA_PER_TXD); 1277 size = min(len, IXGB_MAX_DATA_PER_TXD);
1308 /* Workaround for premature desc write-backs 1278 /* Workaround for premature desc write-backs
@@ -1312,28 +1282,28 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb,
1312 1282
1313 buffer_info->length = size; 1283 buffer_info->length = size;
1314 WARN_ON(buffer_info->dma != 0); 1284 WARN_ON(buffer_info->dma != 0);
1285 buffer_info->time_stamp = jiffies;
1315 buffer_info->dma = 1286 buffer_info->dma =
1316 pci_map_single(adapter->pdev, 1287 pci_map_single(adapter->pdev,
1317 skb->data + offset, 1288 skb->data + offset,
1318 size, 1289 size,
1319 PCI_DMA_TODEVICE); 1290 PCI_DMA_TODEVICE);
1320 buffer_info->time_stamp = jiffies;
1321 buffer_info->next_to_watch = 0; 1291 buffer_info->next_to_watch = 0;
1322 1292
1323 len -= size; 1293 len -= size;
1324 offset += size; 1294 offset += size;
1325 count++; 1295 count++;
1326 if(++i == tx_ring->count) i = 0; 1296 if (++i == tx_ring->count) i = 0;
1327 } 1297 }
1328 1298
1329 for(f = 0; f < nr_frags; f++) { 1299 for (f = 0; f < nr_frags; f++) {
1330 struct skb_frag_struct *frag; 1300 struct skb_frag_struct *frag;
1331 1301
1332 frag = &skb_shinfo(skb)->frags[f]; 1302 frag = &skb_shinfo(skb)->frags[f];
1333 len = frag->size; 1303 len = frag->size;
1334 offset = 0; 1304 offset = 0;
1335 1305
1336 while(len) { 1306 while (len) {
1337 buffer_info = &tx_ring->buffer_info[i]; 1307 buffer_info = &tx_ring->buffer_info[i];
1338 size = min(len, IXGB_MAX_DATA_PER_TXD); 1308 size = min(len, IXGB_MAX_DATA_PER_TXD);
1339 1309
@@ -1344,19 +1314,19 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb,
1344 size -= 4; 1314 size -= 4;
1345 1315
1346 buffer_info->length = size; 1316 buffer_info->length = size;
1317 buffer_info->time_stamp = jiffies;
1347 buffer_info->dma = 1318 buffer_info->dma =
1348 pci_map_page(adapter->pdev, 1319 pci_map_page(adapter->pdev,
1349 frag->page, 1320 frag->page,
1350 frag->page_offset + offset, 1321 frag->page_offset + offset,
1351 size, 1322 size,
1352 PCI_DMA_TODEVICE); 1323 PCI_DMA_TODEVICE);
1353 buffer_info->time_stamp = jiffies;
1354 buffer_info->next_to_watch = 0; 1324 buffer_info->next_to_watch = 0;
1355 1325
1356 len -= size; 1326 len -= size;
1357 offset += size; 1327 offset += size;
1358 count++; 1328 count++;
1359 if(++i == tx_ring->count) i = 0; 1329 if (++i == tx_ring->count) i = 0;
1360 } 1330 }
1361 } 1331 }
1362 i = (i == 0) ? tx_ring->count - 1 : i - 1; 1332 i = (i == 0) ? tx_ring->count - 1 : i - 1;
@@ -1377,21 +1347,20 @@ ixgb_tx_queue(struct ixgb_adapter *adapter, int count, int vlan_id,int tx_flags)
1377 u8 popts = 0; 1347 u8 popts = 0;
1378 unsigned int i; 1348 unsigned int i;
1379 1349
1380 if(tx_flags & IXGB_TX_FLAGS_TSO) { 1350 if (tx_flags & IXGB_TX_FLAGS_TSO) {
1381 cmd_type_len |= IXGB_TX_DESC_CMD_TSE; 1351 cmd_type_len |= IXGB_TX_DESC_CMD_TSE;
1382 popts |= (IXGB_TX_DESC_POPTS_IXSM | IXGB_TX_DESC_POPTS_TXSM); 1352 popts |= (IXGB_TX_DESC_POPTS_IXSM | IXGB_TX_DESC_POPTS_TXSM);
1383 } 1353 }
1384 1354
1385 if(tx_flags & IXGB_TX_FLAGS_CSUM) 1355 if (tx_flags & IXGB_TX_FLAGS_CSUM)
1386 popts |= IXGB_TX_DESC_POPTS_TXSM; 1356 popts |= IXGB_TX_DESC_POPTS_TXSM;
1387 1357
1388 if(tx_flags & IXGB_TX_FLAGS_VLAN) { 1358 if (tx_flags & IXGB_TX_FLAGS_VLAN)
1389 cmd_type_len |= IXGB_TX_DESC_CMD_VLE; 1359 cmd_type_len |= IXGB_TX_DESC_CMD_VLE;
1390 }
1391 1360
1392 i = tx_ring->next_to_use; 1361 i = tx_ring->next_to_use;
1393 1362
1394 while(count--) { 1363 while (count--) {
1395 buffer_info = &tx_ring->buffer_info[i]; 1364 buffer_info = &tx_ring->buffer_info[i];
1396 tx_desc = IXGB_TX_DESC(*tx_ring, i); 1365 tx_desc = IXGB_TX_DESC(*tx_ring, i);
1397 tx_desc->buff_addr = cpu_to_le64(buffer_info->dma); 1366 tx_desc->buff_addr = cpu_to_le64(buffer_info->dma);
@@ -1401,11 +1370,11 @@ ixgb_tx_queue(struct ixgb_adapter *adapter, int count, int vlan_id,int tx_flags)
1401 tx_desc->popts = popts; 1370 tx_desc->popts = popts;
1402 tx_desc->vlan = cpu_to_le16(vlan_id); 1371 tx_desc->vlan = cpu_to_le16(vlan_id);
1403 1372
1404 if(++i == tx_ring->count) i = 0; 1373 if (++i == tx_ring->count) i = 0;
1405 } 1374 }
1406 1375
1407 tx_desc->cmd_type_len |= cpu_to_le32(IXGB_TX_DESC_CMD_EOP 1376 tx_desc->cmd_type_len |=
1408 | IXGB_TX_DESC_CMD_RS ); 1377 cpu_to_le32(IXGB_TX_DESC_CMD_EOP | IXGB_TX_DESC_CMD_RS);
1409 1378
1410 /* Force memory writes to complete before letting h/w 1379 /* Force memory writes to complete before letting h/w
1411 * know there are new descriptors to fetch. (Only 1380 * know there are new descriptors to fetch. (Only
@@ -1461,7 +1430,6 @@ ixgb_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1461 struct ixgb_adapter *adapter = netdev_priv(netdev); 1430 struct ixgb_adapter *adapter = netdev_priv(netdev);
1462 unsigned int first; 1431 unsigned int first;
1463 unsigned int tx_flags = 0; 1432 unsigned int tx_flags = 0;
1464 unsigned long flags;
1465 int vlan_id = 0; 1433 int vlan_id = 0;
1466 int tso; 1434 int tso;
1467 1435
@@ -1470,51 +1438,31 @@ ixgb_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1470 return NETDEV_TX_OK; 1438 return NETDEV_TX_OK;
1471 } 1439 }
1472 1440
1473 if(skb->len <= 0) { 1441 if (skb->len <= 0) {
1474 dev_kfree_skb_any(skb); 1442 dev_kfree_skb(skb);
1475 return 0; 1443 return 0;
1476 } 1444 }
1477 1445
1478#ifdef NETIF_F_LLTX
1479 if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
1480 /* Collision - tell upper layer to requeue */
1481 local_irq_restore(flags);
1482 return NETDEV_TX_LOCKED;
1483 }
1484#else
1485 spin_lock_irqsave(&adapter->tx_lock, flags);
1486#endif
1487
1488 if (unlikely(ixgb_maybe_stop_tx(netdev, &adapter->tx_ring, 1446 if (unlikely(ixgb_maybe_stop_tx(netdev, &adapter->tx_ring,
1489 DESC_NEEDED))) { 1447 DESC_NEEDED)))
1490 netif_stop_queue(netdev);
1491 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1492 return NETDEV_TX_BUSY; 1448 return NETDEV_TX_BUSY;
1493 }
1494
1495#ifndef NETIF_F_LLTX
1496 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1497#endif
1498 1449
1499 if(adapter->vlgrp && vlan_tx_tag_present(skb)) { 1450 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
1500 tx_flags |= IXGB_TX_FLAGS_VLAN; 1451 tx_flags |= IXGB_TX_FLAGS_VLAN;
1501 vlan_id = vlan_tx_tag_get(skb); 1452 vlan_id = vlan_tx_tag_get(skb);
1502 } 1453 }
1503 1454
1504 first = adapter->tx_ring.next_to_use; 1455 first = adapter->tx_ring.next_to_use;
1505 1456
1506 tso = ixgb_tso(adapter, skb); 1457 tso = ixgb_tso(adapter, skb);
1507 if (tso < 0) { 1458 if (tso < 0) {
1508 dev_kfree_skb_any(skb); 1459 dev_kfree_skb(skb);
1509#ifdef NETIF_F_LLTX
1510 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1511#endif
1512 return NETDEV_TX_OK; 1460 return NETDEV_TX_OK;
1513 } 1461 }
1514 1462
1515 if (likely(tso)) 1463 if (likely(tso))
1516 tx_flags |= IXGB_TX_FLAGS_TSO; 1464 tx_flags |= IXGB_TX_FLAGS_TSO;
1517 else if(ixgb_tx_csum(adapter, skb)) 1465 else if (ixgb_tx_csum(adapter, skb))
1518 tx_flags |= IXGB_TX_FLAGS_CSUM; 1466 tx_flags |= IXGB_TX_FLAGS_CSUM;
1519 1467
1520 ixgb_tx_queue(adapter, ixgb_tx_map(adapter, skb, first), vlan_id, 1468 ixgb_tx_queue(adapter, ixgb_tx_map(adapter, skb, first), vlan_id,
@@ -1522,13 +1470,9 @@ ixgb_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1522 1470
1523 netdev->trans_start = jiffies; 1471 netdev->trans_start = jiffies;
1524 1472
1525#ifdef NETIF_F_LLTX
1526 /* Make sure there is space in the ring for the next send. */ 1473 /* Make sure there is space in the ring for the next send. */
1527 ixgb_maybe_stop_tx(netdev, &adapter->tx_ring, DESC_NEEDED); 1474 ixgb_maybe_stop_tx(netdev, &adapter->tx_ring, DESC_NEEDED);
1528 1475
1529 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1530
1531#endif
1532 return NETDEV_TX_OK; 1476 return NETDEV_TX_OK;
1533} 1477}
1534 1478
@@ -1588,21 +1532,25 @@ ixgb_change_mtu(struct net_device *netdev, int new_mtu)
1588 int max_frame = new_mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH; 1532 int max_frame = new_mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
1589 int old_max_frame = netdev->mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH; 1533 int old_max_frame = netdev->mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
1590 1534
1591 1535 /* MTU < 68 is an error for IPv4 traffic, just don't allow it */
1592 if((max_frame < IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH) 1536 if ((new_mtu < 68) ||
1593 || (max_frame > IXGB_MAX_JUMBO_FRAME_SIZE + ENET_FCS_LENGTH)) { 1537 (max_frame > IXGB_MAX_JUMBO_FRAME_SIZE + ENET_FCS_LENGTH)) {
1594 DPRINTK(PROBE, ERR, "Invalid MTU setting %d\n", new_mtu); 1538 DPRINTK(PROBE, ERR, "Invalid MTU setting %d\n", new_mtu);
1595 return -EINVAL; 1539 return -EINVAL;
1596 } 1540 }
1597 1541
1598 adapter->rx_buffer_len = max_frame; 1542 if (old_max_frame == max_frame)
1543 return 0;
1544
1545 if (netif_running(netdev))
1546 ixgb_down(adapter, true);
1547
1548 adapter->rx_buffer_len = max_frame + 8; /* + 8 for errata */
1599 1549
1600 netdev->mtu = new_mtu; 1550 netdev->mtu = new_mtu;
1601 1551
1602 if ((old_max_frame != max_frame) && netif_running(netdev)) { 1552 if (netif_running(netdev))
1603 ixgb_down(adapter, true);
1604 ixgb_up(adapter); 1553 ixgb_up(adapter);
1605 }
1606 1554
1607 return 0; 1555 return 0;
1608} 1556}
@@ -1622,21 +1570,21 @@ ixgb_update_stats(struct ixgb_adapter *adapter)
1622 if (pci_channel_offline(pdev)) 1570 if (pci_channel_offline(pdev))
1623 return; 1571 return;
1624 1572
1625 if((netdev->flags & IFF_PROMISC) || (netdev->flags & IFF_ALLMULTI) || 1573 if ((netdev->flags & IFF_PROMISC) || (netdev->flags & IFF_ALLMULTI) ||
1626 (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES)) { 1574 (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES)) {
1627 u64 multi = IXGB_READ_REG(&adapter->hw, MPRCL); 1575 u64 multi = IXGB_READ_REG(&adapter->hw, MPRCL);
1628 u32 bcast_l = IXGB_READ_REG(&adapter->hw, BPRCL); 1576 u32 bcast_l = IXGB_READ_REG(&adapter->hw, BPRCL);
1629 u32 bcast_h = IXGB_READ_REG(&adapter->hw, BPRCH); 1577 u32 bcast_h = IXGB_READ_REG(&adapter->hw, BPRCH);
1630 u64 bcast = ((u64)bcast_h << 32) | bcast_l; 1578 u64 bcast = ((u64)bcast_h << 32) | bcast_l;
1631 1579
1632 multi |= ((u64)IXGB_READ_REG(&adapter->hw, MPRCH) << 32); 1580 multi |= ((u64)IXGB_READ_REG(&adapter->hw, MPRCH) << 32);
1633 /* fix up multicast stats by removing broadcasts */ 1581 /* fix up multicast stats by removing broadcasts */
1634 if(multi >= bcast) 1582 if (multi >= bcast)
1635 multi -= bcast; 1583 multi -= bcast;
1636 1584
1637 adapter->stats.mprcl += (multi & 0xFFFFFFFF); 1585 adapter->stats.mprcl += (multi & 0xFFFFFFFF);
1638 adapter->stats.mprch += (multi >> 32); 1586 adapter->stats.mprch += (multi >> 32);
1639 adapter->stats.bprcl += bcast_l; 1587 adapter->stats.bprcl += bcast_l;
1640 adapter->stats.bprch += bcast_h; 1588 adapter->stats.bprch += bcast_h;
1641 } else { 1589 } else {
1642 adapter->stats.mprcl += IXGB_READ_REG(&adapter->hw, MPRCL); 1590 adapter->stats.mprcl += IXGB_READ_REG(&adapter->hw, MPRCL);
@@ -1751,41 +1699,26 @@ ixgb_intr(int irq, void *data)
1751 struct ixgb_adapter *adapter = netdev_priv(netdev); 1699 struct ixgb_adapter *adapter = netdev_priv(netdev);
1752 struct ixgb_hw *hw = &adapter->hw; 1700 struct ixgb_hw *hw = &adapter->hw;
1753 u32 icr = IXGB_READ_REG(hw, ICR); 1701 u32 icr = IXGB_READ_REG(hw, ICR);
1754#ifndef CONFIG_IXGB_NAPI
1755 unsigned int i;
1756#endif
1757 1702
1758 if(unlikely(!icr)) 1703 if (unlikely(!icr))
1759 return IRQ_NONE; /* Not our interrupt */ 1704 return IRQ_NONE; /* Not our interrupt */
1760 1705
1761 if (unlikely(icr & (IXGB_INT_RXSEQ | IXGB_INT_LSC))) 1706 if (unlikely(icr & (IXGB_INT_RXSEQ | IXGB_INT_LSC)))
1762 if (!test_bit(__IXGB_DOWN, &adapter->flags)) 1707 if (!test_bit(__IXGB_DOWN, &adapter->flags))
1763 mod_timer(&adapter->watchdog_timer, jiffies); 1708 mod_timer(&adapter->watchdog_timer, jiffies);
1764 1709
1765#ifdef CONFIG_IXGB_NAPI
1766 if (netif_rx_schedule_prep(netdev, &adapter->napi)) { 1710 if (netif_rx_schedule_prep(netdev, &adapter->napi)) {
1767 1711
1768 /* Disable interrupts and register for poll. The flush 1712 /* Disable interrupts and register for poll. The flush
1769 of the posted write is intentionally left out. 1713 of the posted write is intentionally left out.
1770 */ 1714 */
1771 1715
1772 IXGB_WRITE_REG(&adapter->hw, IMC, ~0); 1716 IXGB_WRITE_REG(&adapter->hw, IMC, ~0);
1773 __netif_rx_schedule(netdev, &adapter->napi); 1717 __netif_rx_schedule(netdev, &adapter->napi);
1774 } 1718 }
1775#else
1776 /* yes, that is actually a & and it is meant to make sure that
1777 * every pass through this for loop checks both receive and
1778 * transmit queues for completed descriptors, intended to
1779 * avoid starvation issues and assist tx/rx fairness. */
1780 for(i = 0; i < IXGB_MAX_INTR; i++)
1781 if(!ixgb_clean_rx_irq(adapter) &
1782 !ixgb_clean_tx_irq(adapter))
1783 break;
1784#endif
1785 return IRQ_HANDLED; 1719 return IRQ_HANDLED;
1786} 1720}
1787 1721
1788#ifdef CONFIG_IXGB_NAPI
1789/** 1722/**
1790 * ixgb_clean - NAPI Rx polling callback 1723 * ixgb_clean - NAPI Rx polling callback
1791 * @adapter: board private structure 1724 * @adapter: board private structure
@@ -1804,12 +1737,12 @@ ixgb_clean(struct napi_struct *napi, int budget)
1804 /* If budget not fully consumed, exit the polling mode */ 1737 /* If budget not fully consumed, exit the polling mode */
1805 if (work_done < budget) { 1738 if (work_done < budget) {
1806 netif_rx_complete(netdev, napi); 1739 netif_rx_complete(netdev, napi);
1807 ixgb_irq_enable(adapter); 1740 if (!test_bit(__IXGB_DOWN, &adapter->flags))
1741 ixgb_irq_enable(adapter);
1808 } 1742 }
1809 1743
1810 return work_done; 1744 return work_done;
1811} 1745}
1812#endif
1813 1746
1814/** 1747/**
1815 * ixgb_clean_tx_irq - Reclaim resources after transmit completes 1748 * ixgb_clean_tx_irq - Reclaim resources after transmit completes
@@ -1830,15 +1763,15 @@ ixgb_clean_tx_irq(struct ixgb_adapter *adapter)
1830 eop = tx_ring->buffer_info[i].next_to_watch; 1763 eop = tx_ring->buffer_info[i].next_to_watch;
1831 eop_desc = IXGB_TX_DESC(*tx_ring, eop); 1764 eop_desc = IXGB_TX_DESC(*tx_ring, eop);
1832 1765
1833 while(eop_desc->status & IXGB_TX_DESC_STATUS_DD) { 1766 while (eop_desc->status & IXGB_TX_DESC_STATUS_DD) {
1834 1767
1835 for (cleaned = false; !cleaned; ) { 1768 for (cleaned = false; !cleaned; ) {
1836 tx_desc = IXGB_TX_DESC(*tx_ring, i); 1769 tx_desc = IXGB_TX_DESC(*tx_ring, i);
1837 buffer_info = &tx_ring->buffer_info[i]; 1770 buffer_info = &tx_ring->buffer_info[i];
1838 1771
1839 if (tx_desc->popts 1772 if (tx_desc->popts &
1840 & (IXGB_TX_DESC_POPTS_TXSM | 1773 (IXGB_TX_DESC_POPTS_TXSM |
1841 IXGB_TX_DESC_POPTS_IXSM)) 1774 IXGB_TX_DESC_POPTS_IXSM))
1842 adapter->hw_csum_tx_good++; 1775 adapter->hw_csum_tx_good++;
1843 1776
1844 ixgb_unmap_and_free_tx_resource(adapter, buffer_info); 1777 ixgb_unmap_and_free_tx_resource(adapter, buffer_info);
@@ -1846,7 +1779,7 @@ ixgb_clean_tx_irq(struct ixgb_adapter *adapter)
1846 *(u32 *)&(tx_desc->status) = 0; 1779 *(u32 *)&(tx_desc->status) = 0;
1847 1780
1848 cleaned = (i == eop); 1781 cleaned = (i == eop);
1849 if(++i == tx_ring->count) i = 0; 1782 if (++i == tx_ring->count) i = 0;
1850 } 1783 }
1851 1784
1852 eop = tx_ring->buffer_info[i].next_to_watch; 1785 eop = tx_ring->buffer_info[i].next_to_watch;
@@ -1855,15 +1788,20 @@ ixgb_clean_tx_irq(struct ixgb_adapter *adapter)
1855 1788
1856 tx_ring->next_to_clean = i; 1789 tx_ring->next_to_clean = i;
1857 1790
1858 if (unlikely(netif_queue_stopped(netdev))) { 1791 if (unlikely(cleaned && netif_carrier_ok(netdev) &&
1859 spin_lock(&adapter->tx_lock); 1792 IXGB_DESC_UNUSED(tx_ring) >= DESC_NEEDED)) {
1860 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev) && 1793 /* Make sure that anybody stopping the queue after this
1861 (IXGB_DESC_UNUSED(tx_ring) >= DESC_NEEDED)) 1794 * sees the new next_to_clean. */
1795 smp_mb();
1796
1797 if (netif_queue_stopped(netdev) &&
1798 !(test_bit(__IXGB_DOWN, &adapter->flags))) {
1862 netif_wake_queue(netdev); 1799 netif_wake_queue(netdev);
1863 spin_unlock(&adapter->tx_lock); 1800 ++adapter->restart_queue;
1801 }
1864 } 1802 }
1865 1803
1866 if(adapter->detect_tx_hung) { 1804 if (adapter->detect_tx_hung) {
1867 /* detect a transmit hang in hardware, this serializes the 1805 /* detect a transmit hang in hardware, this serializes the
1868 * check with the clearing of time_stamp and movement of i */ 1806 * check with the clearing of time_stamp and movement of i */
1869 adapter->detect_tx_hung = false; 1807 adapter->detect_tx_hung = false;
@@ -1906,13 +1844,13 @@ ixgb_clean_tx_irq(struct ixgb_adapter *adapter)
1906 1844
1907static void 1845static void
1908ixgb_rx_checksum(struct ixgb_adapter *adapter, 1846ixgb_rx_checksum(struct ixgb_adapter *adapter,
1909 struct ixgb_rx_desc *rx_desc, 1847 struct ixgb_rx_desc *rx_desc,
1910 struct sk_buff *skb) 1848 struct sk_buff *skb)
1911{ 1849{
1912 /* Ignore Checksum bit is set OR 1850 /* Ignore Checksum bit is set OR
1913 * TCP Checksum has not been calculated 1851 * TCP Checksum has not been calculated
1914 */ 1852 */
1915 if((rx_desc->status & IXGB_RX_DESC_STATUS_IXSM) || 1853 if ((rx_desc->status & IXGB_RX_DESC_STATUS_IXSM) ||
1916 (!(rx_desc->status & IXGB_RX_DESC_STATUS_TCPCS))) { 1854 (!(rx_desc->status & IXGB_RX_DESC_STATUS_TCPCS))) {
1917 skb->ip_summed = CHECKSUM_NONE; 1855 skb->ip_summed = CHECKSUM_NONE;
1918 return; 1856 return;
@@ -1920,7 +1858,7 @@ ixgb_rx_checksum(struct ixgb_adapter *adapter,
1920 1858
1921 /* At this point we know the hardware did the TCP checksum */ 1859 /* At this point we know the hardware did the TCP checksum */
1922 /* now look at the TCP checksum error bit */ 1860 /* now look at the TCP checksum error bit */
1923 if(rx_desc->errors & IXGB_RX_DESC_ERRORS_TCPE) { 1861 if (rx_desc->errors & IXGB_RX_DESC_ERRORS_TCPE) {
1924 /* let the stack verify checksum errors */ 1862 /* let the stack verify checksum errors */
1925 skb->ip_summed = CHECKSUM_NONE; 1863 skb->ip_summed = CHECKSUM_NONE;
1926 adapter->hw_csum_rx_error++; 1864 adapter->hw_csum_rx_error++;
@@ -1937,11 +1875,7 @@ ixgb_rx_checksum(struct ixgb_adapter *adapter,
1937 **/ 1875 **/
1938 1876
1939static bool 1877static bool
1940#ifdef CONFIG_IXGB_NAPI
1941ixgb_clean_rx_irq(struct ixgb_adapter *adapter, int *work_done, int work_to_do) 1878ixgb_clean_rx_irq(struct ixgb_adapter *adapter, int *work_done, int work_to_do)
1942#else
1943ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1944#endif
1945{ 1879{
1946 struct ixgb_desc_ring *rx_ring = &adapter->rx_ring; 1880 struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
1947 struct net_device *netdev = adapter->netdev; 1881 struct net_device *netdev = adapter->netdev;
@@ -1950,50 +1884,50 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1950 struct ixgb_buffer *buffer_info, *next_buffer, *next2_buffer; 1884 struct ixgb_buffer *buffer_info, *next_buffer, *next2_buffer;
1951 u32 length; 1885 u32 length;
1952 unsigned int i, j; 1886 unsigned int i, j;
1887 int cleaned_count = 0;
1953 bool cleaned = false; 1888 bool cleaned = false;
1954 1889
1955 i = rx_ring->next_to_clean; 1890 i = rx_ring->next_to_clean;
1956 rx_desc = IXGB_RX_DESC(*rx_ring, i); 1891 rx_desc = IXGB_RX_DESC(*rx_ring, i);
1957 buffer_info = &rx_ring->buffer_info[i]; 1892 buffer_info = &rx_ring->buffer_info[i];
1958 1893
1959 while(rx_desc->status & IXGB_RX_DESC_STATUS_DD) { 1894 while (rx_desc->status & IXGB_RX_DESC_STATUS_DD) {
1960 struct sk_buff *skb, *next_skb; 1895 struct sk_buff *skb;
1961 u8 status; 1896 u8 status;
1962 1897
1963#ifdef CONFIG_IXGB_NAPI 1898 if (*work_done >= work_to_do)
1964 if(*work_done >= work_to_do)
1965 break; 1899 break;
1966 1900
1967 (*work_done)++; 1901 (*work_done)++;
1968#endif
1969 status = rx_desc->status; 1902 status = rx_desc->status;
1970 skb = buffer_info->skb; 1903 skb = buffer_info->skb;
1971 buffer_info->skb = NULL; 1904 buffer_info->skb = NULL;
1972 1905
1973 prefetch(skb->data); 1906 prefetch(skb->data - NET_IP_ALIGN);
1974 1907
1975 if(++i == rx_ring->count) i = 0; 1908 if (++i == rx_ring->count) i = 0;
1976 next_rxd = IXGB_RX_DESC(*rx_ring, i); 1909 next_rxd = IXGB_RX_DESC(*rx_ring, i);
1977 prefetch(next_rxd); 1910 prefetch(next_rxd);
1978 1911
1979 if((j = i + 1) == rx_ring->count) j = 0; 1912 if ((j = i + 1) == rx_ring->count) j = 0;
1980 next2_buffer = &rx_ring->buffer_info[j]; 1913 next2_buffer = &rx_ring->buffer_info[j];
1981 prefetch(next2_buffer); 1914 prefetch(next2_buffer);
1982 1915
1983 next_buffer = &rx_ring->buffer_info[i]; 1916 next_buffer = &rx_ring->buffer_info[i];
1984 next_skb = next_buffer->skb;
1985 prefetch(next_skb);
1986 1917
1987 cleaned = true; 1918 cleaned = true;
1919 cleaned_count++;
1988 1920
1989 pci_unmap_single(pdev, 1921 pci_unmap_single(pdev,
1990 buffer_info->dma, 1922 buffer_info->dma,
1991 buffer_info->length, 1923 buffer_info->length,
1992 PCI_DMA_FROMDEVICE); 1924 PCI_DMA_FROMDEVICE);
1925 buffer_info->dma = 0;
1993 1926
1994 length = le16_to_cpu(rx_desc->length); 1927 length = le16_to_cpu(rx_desc->length);
1928 rx_desc->length = 0;
1995 1929
1996 if(unlikely(!(status & IXGB_RX_DESC_STATUS_EOP))) { 1930 if (unlikely(!(status & IXGB_RX_DESC_STATUS_EOP))) {
1997 1931
1998 /* All receives must fit into a single buffer */ 1932 /* All receives must fit into a single buffer */
1999 1933
@@ -2004,11 +1938,9 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
2004 goto rxdesc_done; 1938 goto rxdesc_done;
2005 } 1939 }
2006 1940
2007 if (unlikely(rx_desc->errors 1941 if (unlikely(rx_desc->errors &
2008 & (IXGB_RX_DESC_ERRORS_CE | IXGB_RX_DESC_ERRORS_SE 1942 (IXGB_RX_DESC_ERRORS_CE | IXGB_RX_DESC_ERRORS_SE |
2009 | IXGB_RX_DESC_ERRORS_P | 1943 IXGB_RX_DESC_ERRORS_P | IXGB_RX_DESC_ERRORS_RXE))) {
2010 IXGB_RX_DESC_ERRORS_RXE))) {
2011
2012 dev_kfree_skb_irq(skb); 1944 dev_kfree_skb_irq(skb);
2013 goto rxdesc_done; 1945 goto rxdesc_done;
2014 } 1946 }
@@ -2016,8 +1948,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
2016 /* code added for copybreak, this should improve 1948 /* code added for copybreak, this should improve
2017 * performance for small packets with large amounts 1949 * performance for small packets with large amounts
2018 * of reassembly being done in the stack */ 1950 * of reassembly being done in the stack */
2019#define IXGB_CB_LENGTH 256 1951 if (length < copybreak) {
2020 if (length < IXGB_CB_LENGTH) {
2021 struct sk_buff *new_skb = 1952 struct sk_buff *new_skb =
2022 netdev_alloc_skb(netdev, length + NET_IP_ALIGN); 1953 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
2023 if (new_skb) { 1954 if (new_skb) {
@@ -2042,29 +1973,24 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
2042 ixgb_rx_checksum(adapter, rx_desc, skb); 1973 ixgb_rx_checksum(adapter, rx_desc, skb);
2043 1974
2044 skb->protocol = eth_type_trans(skb, netdev); 1975 skb->protocol = eth_type_trans(skb, netdev);
2045#ifdef CONFIG_IXGB_NAPI 1976 if (adapter->vlgrp && (status & IXGB_RX_DESC_STATUS_VP)) {
2046 if(adapter->vlgrp && (status & IXGB_RX_DESC_STATUS_VP)) {
2047 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, 1977 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2048 le16_to_cpu(rx_desc->special) & 1978 le16_to_cpu(rx_desc->special));
2049 IXGB_RX_DESC_SPECIAL_VLAN_MASK);
2050 } else { 1979 } else {
2051 netif_receive_skb(skb); 1980 netif_receive_skb(skb);
2052 } 1981 }
2053#else /* CONFIG_IXGB_NAPI */
2054 if(adapter->vlgrp && (status & IXGB_RX_DESC_STATUS_VP)) {
2055 vlan_hwaccel_rx(skb, adapter->vlgrp,
2056 le16_to_cpu(rx_desc->special) &
2057 IXGB_RX_DESC_SPECIAL_VLAN_MASK);
2058 } else {
2059 netif_rx(skb);
2060 }
2061#endif /* CONFIG_IXGB_NAPI */
2062 netdev->last_rx = jiffies; 1982 netdev->last_rx = jiffies;
2063 1983
2064rxdesc_done: 1984rxdesc_done:
2065 /* clean up descriptor, might be written over by hw */ 1985 /* clean up descriptor, might be written over by hw */
2066 rx_desc->status = 0; 1986 rx_desc->status = 0;
2067 1987
1988 /* return some buffers to hardware, one at a time is too slow */
1989 if (unlikely(cleaned_count >= IXGB_RX_BUFFER_WRITE)) {
1990 ixgb_alloc_rx_buffers(adapter, cleaned_count);
1991 cleaned_count = 0;
1992 }
1993
2068 /* use prefetched values */ 1994 /* use prefetched values */
2069 rx_desc = next_rxd; 1995 rx_desc = next_rxd;
2070 buffer_info = next_buffer; 1996 buffer_info = next_buffer;
@@ -2072,7 +1998,9 @@ rxdesc_done:
2072 1998
2073 rx_ring->next_to_clean = i; 1999 rx_ring->next_to_clean = i;
2074 2000
2075 ixgb_alloc_rx_buffers(adapter); 2001 cleaned_count = IXGB_DESC_UNUSED(rx_ring);
2002 if (cleaned_count)
2003 ixgb_alloc_rx_buffers(adapter, cleaned_count);
2076 2004
2077 return cleaned; 2005 return cleaned;
2078} 2006}
@@ -2083,7 +2011,7 @@ rxdesc_done:
2083 **/ 2011 **/
2084 2012
2085static void 2013static void
2086ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter) 2014ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter, int cleaned_count)
2087{ 2015{
2088 struct ixgb_desc_ring *rx_ring = &adapter->rx_ring; 2016 struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
2089 struct net_device *netdev = adapter->netdev; 2017 struct net_device *netdev = adapter->netdev;
@@ -2100,7 +2028,7 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter)
2100 2028
2101 2029
2102 /* leave three descriptors unused */ 2030 /* leave three descriptors unused */
2103 while(--cleancount > 2) { 2031 while (--cleancount > 2 && cleaned_count--) {
2104 /* recycle! its good for you */ 2032 /* recycle! its good for you */
2105 skb = buffer_info->skb; 2033 skb = buffer_info->skb;
2106 if (skb) { 2034 if (skb) {
@@ -2133,12 +2061,12 @@ map_skb:
2133 rx_desc = IXGB_RX_DESC(*rx_ring, i); 2061 rx_desc = IXGB_RX_DESC(*rx_ring, i);
2134 rx_desc->buff_addr = cpu_to_le64(buffer_info->dma); 2062 rx_desc->buff_addr = cpu_to_le64(buffer_info->dma);
2135 /* guarantee DD bit not set now before h/w gets descriptor 2063 /* guarantee DD bit not set now before h/w gets descriptor
2136 * this is the rest of the workaround for h/w double 2064 * this is the rest of the workaround for h/w double
2137 * writeback. */ 2065 * writeback. */
2138 rx_desc->status = 0; 2066 rx_desc->status = 0;
2139 2067
2140 2068
2141 if(++i == rx_ring->count) i = 0; 2069 if (++i == rx_ring->count) i = 0;
2142 buffer_info = &rx_ring->buffer_info[i]; 2070 buffer_info = &rx_ring->buffer_info[i];
2143 } 2071 }
2144 2072
@@ -2158,7 +2086,7 @@ map_skb:
2158 2086
2159/** 2087/**
2160 * ixgb_vlan_rx_register - enables or disables vlan tagging/stripping. 2088 * ixgb_vlan_rx_register - enables or disables vlan tagging/stripping.
2161 * 2089 *
2162 * @param netdev network interface device structure 2090 * @param netdev network interface device structure
2163 * @param grp indicates to enable or disable tagging/stripping 2091 * @param grp indicates to enable or disable tagging/stripping
2164 **/ 2092 **/
@@ -2171,7 +2099,7 @@ ixgb_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2171 ixgb_irq_disable(adapter); 2099 ixgb_irq_disable(adapter);
2172 adapter->vlgrp = grp; 2100 adapter->vlgrp = grp;
2173 2101
2174 if(grp) { 2102 if (grp) {
2175 /* enable VLAN tag insert/strip */ 2103 /* enable VLAN tag insert/strip */
2176 ctrl = IXGB_READ_REG(&adapter->hw, CTRL0); 2104 ctrl = IXGB_READ_REG(&adapter->hw, CTRL0);
2177 ctrl |= IXGB_CTRL0_VME; 2105 ctrl |= IXGB_CTRL0_VME;
@@ -2180,7 +2108,6 @@ ixgb_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2180 /* enable VLAN receive filtering */ 2108 /* enable VLAN receive filtering */
2181 2109
2182 rctl = IXGB_READ_REG(&adapter->hw, RCTL); 2110 rctl = IXGB_READ_REG(&adapter->hw, RCTL);
2183 rctl |= IXGB_RCTL_VFE;
2184 rctl &= ~IXGB_RCTL_CFIEN; 2111 rctl &= ~IXGB_RCTL_CFIEN;
2185 IXGB_WRITE_REG(&adapter->hw, RCTL, rctl); 2112 IXGB_WRITE_REG(&adapter->hw, RCTL, rctl);
2186 } else { 2113 } else {
@@ -2189,12 +2116,6 @@ ixgb_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2189 ctrl = IXGB_READ_REG(&adapter->hw, CTRL0); 2116 ctrl = IXGB_READ_REG(&adapter->hw, CTRL0);
2190 ctrl &= ~IXGB_CTRL0_VME; 2117 ctrl &= ~IXGB_CTRL0_VME;
2191 IXGB_WRITE_REG(&adapter->hw, CTRL0, ctrl); 2118 IXGB_WRITE_REG(&adapter->hw, CTRL0, ctrl);
2192
2193 /* disable VLAN filtering */
2194
2195 rctl = IXGB_READ_REG(&adapter->hw, RCTL);
2196 rctl &= ~IXGB_RCTL_VFE;
2197 IXGB_WRITE_REG(&adapter->hw, RCTL, rctl);
2198 } 2119 }
2199 2120
2200 /* don't enable interrupts unless we are UP */ 2121 /* don't enable interrupts unless we are UP */
@@ -2243,10 +2164,10 @@ ixgb_restore_vlan(struct ixgb_adapter *adapter)
2243{ 2164{
2244 ixgb_vlan_rx_register(adapter->netdev, adapter->vlgrp); 2165 ixgb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2245 2166
2246 if(adapter->vlgrp) { 2167 if (adapter->vlgrp) {
2247 u16 vid; 2168 u16 vid;
2248 for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { 2169 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2249 if(!vlan_group_get_device(adapter->vlgrp, vid)) 2170 if (!vlan_group_get_device(adapter->vlgrp, vid))
2250 continue; 2171 continue;
2251 ixgb_vlan_rx_add_vid(adapter->netdev, vid); 2172 ixgb_vlan_rx_add_vid(adapter->netdev, vid);
2252 } 2173 }
@@ -2278,13 +2199,13 @@ static void ixgb_netpoll(struct net_device *dev)
2278 * This callback is called by the PCI subsystem whenever 2199 * This callback is called by the PCI subsystem whenever
2279 * a PCI bus error is detected. 2200 * a PCI bus error is detected.
2280 */ 2201 */
2281static pci_ers_result_t ixgb_io_error_detected (struct pci_dev *pdev, 2202static pci_ers_result_t ixgb_io_error_detected(struct pci_dev *pdev,
2282 enum pci_channel_state state) 2203 enum pci_channel_state state)
2283{ 2204{
2284 struct net_device *netdev = pci_get_drvdata(pdev); 2205 struct net_device *netdev = pci_get_drvdata(pdev);
2285 struct ixgb_adapter *adapter = netdev_priv(netdev); 2206 struct ixgb_adapter *adapter = netdev_priv(netdev);
2286 2207
2287 if(netif_running(netdev)) 2208 if (netif_running(netdev))
2288 ixgb_down(adapter, true); 2209 ixgb_down(adapter, true);
2289 2210
2290 pci_disable_device(pdev); 2211 pci_disable_device(pdev);
@@ -2297,17 +2218,17 @@ static pci_ers_result_t ixgb_io_error_detected (struct pci_dev *pdev,
2297 * ixgb_io_slot_reset - called after the pci bus has been reset. 2218 * ixgb_io_slot_reset - called after the pci bus has been reset.
2298 * @pdev pointer to pci device with error 2219 * @pdev pointer to pci device with error
2299 * 2220 *
2300 * This callback is called after the PCI buss has been reset. 2221 * This callback is called after the PCI bus has been reset.
2301 * Basically, this tries to restart the card from scratch. 2222 * Basically, this tries to restart the card from scratch.
2302 * This is a shortened version of the device probe/discovery code, 2223 * This is a shortened version of the device probe/discovery code,
2303 * it resembles the first-half of the ixgb_probe() routine. 2224 * it resembles the first-half of the ixgb_probe() routine.
2304 */ 2225 */
2305static pci_ers_result_t ixgb_io_slot_reset (struct pci_dev *pdev) 2226static pci_ers_result_t ixgb_io_slot_reset(struct pci_dev *pdev)
2306{ 2227{
2307 struct net_device *netdev = pci_get_drvdata(pdev); 2228 struct net_device *netdev = pci_get_drvdata(pdev);
2308 struct ixgb_adapter *adapter = netdev_priv(netdev); 2229 struct ixgb_adapter *adapter = netdev_priv(netdev);
2309 2230
2310 if(pci_enable_device(pdev)) { 2231 if (pci_enable_device(pdev)) {
2311 DPRINTK(PROBE, ERR, "Cannot re-enable PCI device after reset.\n"); 2232 DPRINTK(PROBE, ERR, "Cannot re-enable PCI device after reset.\n");
2312 return PCI_ERS_RESULT_DISCONNECT; 2233 return PCI_ERS_RESULT_DISCONNECT;
2313 } 2234 }
@@ -2323,14 +2244,14 @@ static pci_ers_result_t ixgb_io_slot_reset (struct pci_dev *pdev)
2323 ixgb_reset(adapter); 2244 ixgb_reset(adapter);
2324 2245
2325 /* Make sure the EEPROM is good */ 2246 /* Make sure the EEPROM is good */
2326 if(!ixgb_validate_eeprom_checksum(&adapter->hw)) { 2247 if (!ixgb_validate_eeprom_checksum(&adapter->hw)) {
2327 DPRINTK(PROBE, ERR, "After reset, the EEPROM checksum is not valid.\n"); 2248 DPRINTK(PROBE, ERR, "After reset, the EEPROM checksum is not valid.\n");
2328 return PCI_ERS_RESULT_DISCONNECT; 2249 return PCI_ERS_RESULT_DISCONNECT;
2329 } 2250 }
2330 ixgb_get_ee_mac_addr(&adapter->hw, netdev->dev_addr); 2251 ixgb_get_ee_mac_addr(&adapter->hw, netdev->dev_addr);
2331 memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len); 2252 memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
2332 2253
2333 if(!is_valid_ether_addr(netdev->perm_addr)) { 2254 if (!is_valid_ether_addr(netdev->perm_addr)) {
2334 DPRINTK(PROBE, ERR, "After reset, invalid MAC address.\n"); 2255 DPRINTK(PROBE, ERR, "After reset, invalid MAC address.\n");
2335 return PCI_ERS_RESULT_DISCONNECT; 2256 return PCI_ERS_RESULT_DISCONNECT;
2336 } 2257 }
@@ -2346,15 +2267,15 @@ static pci_ers_result_t ixgb_io_slot_reset (struct pci_dev *pdev)
2346 * normal operation. Implementation resembles the second-half 2267 * normal operation. Implementation resembles the second-half
2347 * of the ixgb_probe() routine. 2268 * of the ixgb_probe() routine.
2348 */ 2269 */
2349static void ixgb_io_resume (struct pci_dev *pdev) 2270static void ixgb_io_resume(struct pci_dev *pdev)
2350{ 2271{
2351 struct net_device *netdev = pci_get_drvdata(pdev); 2272 struct net_device *netdev = pci_get_drvdata(pdev);
2352 struct ixgb_adapter *adapter = netdev_priv(netdev); 2273 struct ixgb_adapter *adapter = netdev_priv(netdev);
2353 2274
2354 pci_set_master(pdev); 2275 pci_set_master(pdev);
2355 2276
2356 if(netif_running(netdev)) { 2277 if (netif_running(netdev)) {
2357 if(ixgb_up(adapter)) { 2278 if (ixgb_up(adapter)) {
2358 printk ("ixgb: can't bring device back up after reset\n"); 2279 printk ("ixgb: can't bring device back up after reset\n");
2359 return; 2280 return;
2360 } 2281 }
diff --git a/drivers/net/ixgb/ixgb_osdep.h b/drivers/net/ixgb/ixgb_osdep.h
index 4be1b273e1b8..d92e72bd627a 100644
--- a/drivers/net/ixgb/ixgb_osdep.h
+++ b/drivers/net/ixgb/ixgb_osdep.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/10GbE Linux driver 3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -40,7 +40,7 @@
40#include <linux/sched.h> 40#include <linux/sched.h>
41 41
42#undef ASSERT 42#undef ASSERT
43#define ASSERT(x) if(!(x)) BUG() 43#define ASSERT(x) if (!(x)) BUG()
44#define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B) 44#define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B)
45 45
46#ifdef DBG 46#ifdef DBG
diff --git a/drivers/net/ixgb/ixgb_param.c b/drivers/net/ixgb/ixgb_param.c
index 865d14d6e5a7..af35e1ddadd6 100644
--- a/drivers/net/ixgb/ixgb_param.c
+++ b/drivers/net/ixgb/ixgb_param.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/10GbE Linux driver 3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -136,7 +136,7 @@ IXGB_PARAM(RxFCLowThresh, "Receive Flow Control Low Threshold");
136/* Flow control request timeout (how long to pause the link partner's tx) 136/* Flow control request timeout (how long to pause the link partner's tx)
137 * (PAP 15:0) 137 * (PAP 15:0)
138 * 138 *
139 * Valid Range: 1 - 65535 139 * Valid Range: 1 - 65535
140 * 140 *
141 * Default Value: 65535 (0xffff) (we'll send an xon if we recover) 141 * Default Value: 65535 (0xffff) (we'll send an xon if we recover)
142 */ 142 */
@@ -200,7 +200,7 @@ struct ixgb_option {
200static int __devinit 200static int __devinit
201ixgb_validate_option(unsigned int *value, const struct ixgb_option *opt) 201ixgb_validate_option(unsigned int *value, const struct ixgb_option *opt)
202{ 202{
203 if(*value == OPTION_UNSET) { 203 if (*value == OPTION_UNSET) {
204 *value = opt->def; 204 *value = opt->def;
205 return 0; 205 return 0;
206 } 206 }
@@ -217,7 +217,7 @@ ixgb_validate_option(unsigned int *value, const struct ixgb_option *opt)
217 } 217 }
218 break; 218 break;
219 case range_option: 219 case range_option:
220 if(*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 220 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
221 printk(KERN_INFO "%s set to %i\n", opt->name, *value); 221 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
222 return 0; 222 return 0;
223 } 223 }
@@ -226,10 +226,10 @@ ixgb_validate_option(unsigned int *value, const struct ixgb_option *opt)
226 int i; 226 int i;
227 struct ixgb_opt_list *ent; 227 struct ixgb_opt_list *ent;
228 228
229 for(i = 0; i < opt->arg.l.nr; i++) { 229 for (i = 0; i < opt->arg.l.nr; i++) {
230 ent = &opt->arg.l.p[i]; 230 ent = &opt->arg.l.p[i];
231 if(*value == ent->i) { 231 if (*value == ent->i) {
232 if(ent->str[0] != '\0') 232 if (ent->str[0] != '\0')
233 printk(KERN_INFO "%s\n", ent->str); 233 printk(KERN_INFO "%s\n", ent->str);
234 return 0; 234 return 0;
235 } 235 }
@@ -260,7 +260,7 @@ void __devinit
260ixgb_check_options(struct ixgb_adapter *adapter) 260ixgb_check_options(struct ixgb_adapter *adapter)
261{ 261{
262 int bd = adapter->bd_number; 262 int bd = adapter->bd_number;
263 if(bd >= IXGB_MAX_NIC) { 263 if (bd >= IXGB_MAX_NIC) {
264 printk(KERN_NOTICE 264 printk(KERN_NOTICE
265 "Warning: no configuration for board #%i\n", bd); 265 "Warning: no configuration for board #%i\n", bd);
266 printk(KERN_NOTICE "Using defaults for all values\n"); 266 printk(KERN_NOTICE "Using defaults for all values\n");
@@ -277,7 +277,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
277 }; 277 };
278 struct ixgb_desc_ring *tx_ring = &adapter->tx_ring; 278 struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
279 279
280 if(num_TxDescriptors > bd) { 280 if (num_TxDescriptors > bd) {
281 tx_ring->count = TxDescriptors[bd]; 281 tx_ring->count = TxDescriptors[bd];
282 ixgb_validate_option(&tx_ring->count, &opt); 282 ixgb_validate_option(&tx_ring->count, &opt);
283 } else { 283 } else {
@@ -296,7 +296,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
296 }; 296 };
297 struct ixgb_desc_ring *rx_ring = &adapter->rx_ring; 297 struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
298 298
299 if(num_RxDescriptors > bd) { 299 if (num_RxDescriptors > bd) {
300 rx_ring->count = RxDescriptors[bd]; 300 rx_ring->count = RxDescriptors[bd];
301 ixgb_validate_option(&rx_ring->count, &opt); 301 ixgb_validate_option(&rx_ring->count, &opt);
302 } else { 302 } else {
@@ -312,7 +312,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
312 .def = OPTION_ENABLED 312 .def = OPTION_ENABLED
313 }; 313 };
314 314
315 if(num_XsumRX > bd) { 315 if (num_XsumRX > bd) {
316 unsigned int rx_csum = XsumRX[bd]; 316 unsigned int rx_csum = XsumRX[bd];
317 ixgb_validate_option(&rx_csum, &opt); 317 ixgb_validate_option(&rx_csum, &opt);
318 adapter->rx_csum = rx_csum; 318 adapter->rx_csum = rx_csum;
@@ -338,7 +338,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
338 .p = fc_list }} 338 .p = fc_list }}
339 }; 339 };
340 340
341 if(num_FlowControl > bd) { 341 if (num_FlowControl > bd) {
342 unsigned int fc = FlowControl[bd]; 342 unsigned int fc = FlowControl[bd];
343 ixgb_validate_option(&fc, &opt); 343 ixgb_validate_option(&fc, &opt);
344 adapter->hw.fc.type = fc; 344 adapter->hw.fc.type = fc;
@@ -356,14 +356,14 @@ ixgb_check_options(struct ixgb_adapter *adapter)
356 .max = MAX_FCRTH}} 356 .max = MAX_FCRTH}}
357 }; 357 };
358 358
359 if(num_RxFCHighThresh > bd) { 359 if (num_RxFCHighThresh > bd) {
360 adapter->hw.fc.high_water = RxFCHighThresh[bd]; 360 adapter->hw.fc.high_water = RxFCHighThresh[bd];
361 ixgb_validate_option(&adapter->hw.fc.high_water, &opt); 361 ixgb_validate_option(&adapter->hw.fc.high_water, &opt);
362 } else { 362 } else {
363 adapter->hw.fc.high_water = opt.def; 363 adapter->hw.fc.high_water = opt.def;
364 } 364 }
365 if (!(adapter->hw.fc.type & ixgb_fc_tx_pause) ) 365 if (!(adapter->hw.fc.type & ixgb_fc_tx_pause) )
366 printk (KERN_INFO 366 printk(KERN_INFO
367 "Ignoring RxFCHighThresh when no RxFC\n"); 367 "Ignoring RxFCHighThresh when no RxFC\n");
368 } 368 }
369 { /* Receive Flow Control Low Threshold */ 369 { /* Receive Flow Control Low Threshold */
@@ -376,14 +376,14 @@ ixgb_check_options(struct ixgb_adapter *adapter)
376 .max = MAX_FCRTL}} 376 .max = MAX_FCRTL}}
377 }; 377 };
378 378
379 if(num_RxFCLowThresh > bd) { 379 if (num_RxFCLowThresh > bd) {
380 adapter->hw.fc.low_water = RxFCLowThresh[bd]; 380 adapter->hw.fc.low_water = RxFCLowThresh[bd];
381 ixgb_validate_option(&adapter->hw.fc.low_water, &opt); 381 ixgb_validate_option(&adapter->hw.fc.low_water, &opt);
382 } else { 382 } else {
383 adapter->hw.fc.low_water = opt.def; 383 adapter->hw.fc.low_water = opt.def;
384 } 384 }
385 if (!(adapter->hw.fc.type & ixgb_fc_tx_pause) ) 385 if (!(adapter->hw.fc.type & ixgb_fc_tx_pause) )
386 printk (KERN_INFO 386 printk(KERN_INFO
387 "Ignoring RxFCLowThresh when no RxFC\n"); 387 "Ignoring RxFCLowThresh when no RxFC\n");
388 } 388 }
389 { /* Flow Control Pause Time Request*/ 389 { /* Flow Control Pause Time Request*/
@@ -396,7 +396,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
396 .max = MAX_FCPAUSE}} 396 .max = MAX_FCPAUSE}}
397 }; 397 };
398 398
399 if(num_FCReqTimeout > bd) { 399 if (num_FCReqTimeout > bd) {
400 unsigned int pause_time = FCReqTimeout[bd]; 400 unsigned int pause_time = FCReqTimeout[bd];
401 ixgb_validate_option(&pause_time, &opt); 401 ixgb_validate_option(&pause_time, &opt);
402 adapter->hw.fc.pause_time = pause_time; 402 adapter->hw.fc.pause_time = pause_time;
@@ -404,7 +404,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
404 adapter->hw.fc.pause_time = opt.def; 404 adapter->hw.fc.pause_time = opt.def;
405 } 405 }
406 if (!(adapter->hw.fc.type & ixgb_fc_tx_pause) ) 406 if (!(adapter->hw.fc.type & ixgb_fc_tx_pause) )
407 printk (KERN_INFO 407 printk(KERN_INFO
408 "Ignoring FCReqTimeout when no RxFC\n"); 408 "Ignoring FCReqTimeout when no RxFC\n");
409 } 409 }
410 /* high low and spacing check for rx flow control thresholds */ 410 /* high low and spacing check for rx flow control thresholds */
@@ -412,7 +412,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
412 /* high must be greater than low */ 412 /* high must be greater than low */
413 if (adapter->hw.fc.high_water < (adapter->hw.fc.low_water + 8)) { 413 if (adapter->hw.fc.high_water < (adapter->hw.fc.low_water + 8)) {
414 /* set defaults */ 414 /* set defaults */
415 printk (KERN_INFO 415 printk(KERN_INFO
416 "RxFCHighThresh must be >= (RxFCLowThresh + 8), " 416 "RxFCHighThresh must be >= (RxFCLowThresh + 8), "
417 "Using Defaults\n"); 417 "Using Defaults\n");
418 adapter->hw.fc.high_water = DEFAULT_FCRTH; 418 adapter->hw.fc.high_water = DEFAULT_FCRTH;
@@ -429,7 +429,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
429 .max = MAX_RDTR}} 429 .max = MAX_RDTR}}
430 }; 430 };
431 431
432 if(num_RxIntDelay > bd) { 432 if (num_RxIntDelay > bd) {
433 adapter->rx_int_delay = RxIntDelay[bd]; 433 adapter->rx_int_delay = RxIntDelay[bd];
434 ixgb_validate_option(&adapter->rx_int_delay, &opt); 434 ixgb_validate_option(&adapter->rx_int_delay, &opt);
435 } else { 435 } else {
@@ -446,7 +446,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
446 .max = MAX_TIDV}} 446 .max = MAX_TIDV}}
447 }; 447 };
448 448
449 if(num_TxIntDelay > bd) { 449 if (num_TxIntDelay > bd) {
450 adapter->tx_int_delay = TxIntDelay[bd]; 450 adapter->tx_int_delay = TxIntDelay[bd];
451 ixgb_validate_option(&adapter->tx_int_delay, &opt); 451 ixgb_validate_option(&adapter->tx_int_delay, &opt);
452 } else { 452 } else {
@@ -462,7 +462,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
462 .def = OPTION_ENABLED 462 .def = OPTION_ENABLED
463 }; 463 };
464 464
465 if(num_IntDelayEnable > bd) { 465 if (num_IntDelayEnable > bd) {
466 unsigned int ide = IntDelayEnable[bd]; 466 unsigned int ide = IntDelayEnable[bd];
467 ixgb_validate_option(&ide, &opt); 467 ixgb_validate_option(&ide, &opt);
468 adapter->tx_int_delay_enable = ide; 468 adapter->tx_int_delay_enable = ide;
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index d98113472a89..956914a5028d 100644
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -32,6 +32,7 @@
32#include <linux/types.h> 32#include <linux/types.h>
33#include <linux/pci.h> 33#include <linux/pci.h>
34#include <linux/netdevice.h> 34#include <linux/netdevice.h>
35#include <linux/inet_lro.h>
35 36
36#include "ixgbe_type.h" 37#include "ixgbe_type.h"
37#include "ixgbe_common.h" 38#include "ixgbe_common.h"
@@ -100,6 +101,9 @@
100#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 101#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
101#define IXGBE_TX_FLAGS_VLAN_SHIFT 16 102#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
102 103
104#define IXGBE_MAX_LRO_DESCRIPTORS 8
105#define IXGBE_MAX_LRO_AGGREGATE 32
106
103/* wrapper around a pointer to a socket buffer, 107/* wrapper around a pointer to a socket buffer,
104 * so a DMA handle can be stored along with the buffer */ 108 * so a DMA handle can be stored along with the buffer */
105struct ixgbe_tx_buffer { 109struct ixgbe_tx_buffer {
@@ -150,6 +154,8 @@ struct ixgbe_ring {
150 /* cpu for tx queue */ 154 /* cpu for tx queue */
151 int cpu; 155 int cpu;
152#endif 156#endif
157 struct net_lro_mgr lro_mgr;
158 bool lro_used;
153 struct ixgbe_queue_stats stats; 159 struct ixgbe_queue_stats stats;
154 u8 v_idx; /* maps directly to the index for this ring in the hardware 160 u8 v_idx; /* maps directly to the index for this ring in the hardware
155 * vector array, can also be used for finding the bit in EICR 161 * vector array, can also be used for finding the bit in EICR
@@ -287,6 +293,9 @@ struct ixgbe_adapter {
287 293
288 unsigned long state; 294 unsigned long state;
289 u64 tx_busy; 295 u64 tx_busy;
296 u64 lro_aggregated;
297 u64 lro_flushed;
298 u64 lro_no_desc;
290}; 299};
291 300
292enum ixbge_state_t { 301enum ixbge_state_t {
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c
index 4e463778bcfd..3efe5dda10af 100644
--- a/drivers/net/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c
@@ -90,6 +90,8 @@ static struct ixgbe_stats ixgbe_gstrings_stats[] = {
90 {"rx_header_split", IXGBE_STAT(rx_hdr_split)}, 90 {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
91 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 91 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
92 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 92 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
93 {"lro_aggregated", IXGBE_STAT(lro_aggregated)},
94 {"lro_flushed", IXGBE_STAT(lro_flushed)},
93}; 95};
94 96
95#define IXGBE_QUEUE_STATS_LEN \ 97#define IXGBE_QUEUE_STATS_LEN \
@@ -250,22 +252,10 @@ static int ixgbe_set_tso(struct net_device *netdev, u32 data)
250 netdev->features |= NETIF_F_TSO; 252 netdev->features |= NETIF_F_TSO;
251 netdev->features |= NETIF_F_TSO6; 253 netdev->features |= NETIF_F_TSO6;
252 } else { 254 } else {
253#ifdef CONFIG_NETDEVICES_MULTIQUEUE 255 netif_tx_stop_all_queues(netdev);
254 struct ixgbe_adapter *adapter = netdev_priv(netdev);
255 int i;
256#endif
257 netif_stop_queue(netdev);
258#ifdef CONFIG_NETDEVICES_MULTIQUEUE
259 for (i = 0; i < adapter->num_tx_queues; i++)
260 netif_stop_subqueue(netdev, i);
261#endif
262 netdev->features &= ~NETIF_F_TSO; 256 netdev->features &= ~NETIF_F_TSO;
263 netdev->features &= ~NETIF_F_TSO6; 257 netdev->features &= ~NETIF_F_TSO6;
264#ifdef CONFIG_NETDEVICES_MULTIQUEUE 258 netif_tx_start_all_queues(netdev);
265 for (i = 0; i < adapter->num_tx_queues; i++)
266 netif_start_subqueue(netdev, i);
267#endif
268 netif_start_queue(netdev);
269 } 259 }
270 return 0; 260 return 0;
271} 261}
@@ -787,6 +777,7 @@ static void ixgbe_get_ethtool_stats(struct net_device *netdev,
787 int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64); 777 int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
788 int j, k; 778 int j, k;
789 int i; 779 int i;
780 u64 aggregated = 0, flushed = 0, no_desc = 0;
790 781
791 ixgbe_update_stats(adapter); 782 ixgbe_update_stats(adapter);
792 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 783 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
@@ -801,11 +792,17 @@ static void ixgbe_get_ethtool_stats(struct net_device *netdev,
801 i += k; 792 i += k;
802 } 793 }
803 for (j = 0; j < adapter->num_rx_queues; j++) { 794 for (j = 0; j < adapter->num_rx_queues; j++) {
795 aggregated += adapter->rx_ring[j].lro_mgr.stats.aggregated;
796 flushed += adapter->rx_ring[j].lro_mgr.stats.flushed;
797 no_desc += adapter->rx_ring[j].lro_mgr.stats.no_desc;
804 queue_stat = (u64 *)&adapter->rx_ring[j].stats; 798 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
805 for (k = 0; k < stat_count; k++) 799 for (k = 0; k < stat_count; k++)
806 data[i + k] = queue_stat[k]; 800 data[i + k] = queue_stat[k];
807 i += k; 801 i += k;
808 } 802 }
803 adapter->lro_aggregated = aggregated;
804 adapter->lro_flushed = flushed;
805 adapter->lro_no_desc = no_desc;
809} 806}
810 807
811static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 808static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
@@ -973,6 +970,8 @@ static struct ethtool_ops ixgbe_ethtool_ops = {
973 .get_ethtool_stats = ixgbe_get_ethtool_stats, 970 .get_ethtool_stats = ixgbe_get_ethtool_stats,
974 .get_coalesce = ixgbe_get_coalesce, 971 .get_coalesce = ixgbe_get_coalesce,
975 .set_coalesce = ixgbe_set_coalesce, 972 .set_coalesce = ixgbe_set_coalesce,
973 .get_flags = ethtool_op_get_flags,
974 .set_flags = ethtool_op_set_flags,
976}; 975};
977 976
978void ixgbe_set_ethtool_ops(struct net_device *netdev) 977void ixgbe_set_ethtool_ops(struct net_device *netdev)
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 8f0460901153..be7b723c924f 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -266,28 +266,16 @@ static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
266 * sees the new next_to_clean. 266 * sees the new next_to_clean.
267 */ 267 */
268 smp_mb(); 268 smp_mb();
269#ifdef CONFIG_NETDEVICES_MULTIQUEUE
270 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && 269 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
271 !test_bit(__IXGBE_DOWN, &adapter->state)) { 270 !test_bit(__IXGBE_DOWN, &adapter->state)) {
272 netif_wake_subqueue(netdev, tx_ring->queue_index); 271 netif_wake_subqueue(netdev, tx_ring->queue_index);
273 adapter->restart_queue++; 272 adapter->restart_queue++;
274 } 273 }
275#else
276 if (netif_queue_stopped(netdev) &&
277 !test_bit(__IXGBE_DOWN, &adapter->state)) {
278 netif_wake_queue(netdev);
279 adapter->restart_queue++;
280 }
281#endif
282 } 274 }
283 275
284 if (adapter->detect_tx_hung) 276 if (adapter->detect_tx_hung)
285 if (ixgbe_check_tx_hang(adapter, tx_ring, eop, eop_desc)) 277 if (ixgbe_check_tx_hang(adapter, tx_ring, eop, eop_desc))
286#ifdef CONFIG_NETDEVICES_MULTIQUEUE
287 netif_stop_subqueue(netdev, tx_ring->queue_index); 278 netif_stop_subqueue(netdev, tx_ring->queue_index);
288#else
289 netif_stop_queue(netdev);
290#endif
291 279
292 if (total_tx_packets >= tx_ring->work_limit) 280 if (total_tx_packets >= tx_ring->work_limit)
293 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->eims_value); 281 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->eims_value);
@@ -389,24 +377,39 @@ static int __ixgbe_notify_dca(struct device *dev, void *data)
389 * ixgbe_receive_skb - Send a completed packet up the stack 377 * ixgbe_receive_skb - Send a completed packet up the stack
390 * @adapter: board private structure 378 * @adapter: board private structure
391 * @skb: packet to send up 379 * @skb: packet to send up
392 * @is_vlan: packet has a VLAN tag 380 * @status: hardware indication of status of receive
393 * @tag: VLAN tag from descriptor 381 * @rx_ring: rx descriptor ring (for a specific queue) to setup
382 * @rx_desc: rx descriptor
394 **/ 383 **/
395static void ixgbe_receive_skb(struct ixgbe_adapter *adapter, 384static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
396 struct sk_buff *skb, bool is_vlan, 385 struct sk_buff *skb, u8 status,
397 u16 tag) 386 struct ixgbe_ring *ring,
387 union ixgbe_adv_rx_desc *rx_desc)
398{ 388{
399 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { 389 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
400 if (adapter->vlgrp && is_vlan) 390 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
401 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
402 else
403 netif_receive_skb(skb);
404 } else {
405 391
392 if (adapter->netdev->features & NETIF_F_LRO &&
393 skb->ip_summed == CHECKSUM_UNNECESSARY) {
406 if (adapter->vlgrp && is_vlan) 394 if (adapter->vlgrp && is_vlan)
407 vlan_hwaccel_rx(skb, adapter->vlgrp, tag); 395 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
396 adapter->vlgrp, tag,
397 rx_desc);
408 else 398 else
409 netif_rx(skb); 399 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
400 ring->lro_used = true;
401 } else {
402 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
403 if (adapter->vlgrp && is_vlan)
404 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
405 else
406 netif_receive_skb(skb);
407 } else {
408 if (adapter->vlgrp && is_vlan)
409 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
410 else
411 netif_rx(skb);
412 }
410 } 413 }
411} 414}
412 415
@@ -546,8 +549,8 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
546 struct sk_buff *skb; 549 struct sk_buff *skb;
547 unsigned int i; 550 unsigned int i;
548 u32 upper_len, len, staterr; 551 u32 upper_len, len, staterr;
549 u16 hdr_info, vlan_tag; 552 u16 hdr_info;
550 bool is_vlan, cleaned = false; 553 bool cleaned = false;
551 int cleaned_count = 0; 554 int cleaned_count = 0;
552 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 555 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
553 556
@@ -556,8 +559,6 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
556 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); 559 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
557 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 560 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
558 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 561 rx_buffer_info = &rx_ring->rx_buffer_info[i];
559 is_vlan = (staterr & IXGBE_RXD_STAT_VP);
560 vlan_tag = le16_to_cpu(rx_desc->wb.upper.vlan);
561 562
562 while (staterr & IXGBE_RXD_STAT_DD) { 563 while (staterr & IXGBE_RXD_STAT_DD) {
563 if (*work_done >= work_to_do) 564 if (*work_done >= work_to_do)
@@ -635,7 +636,7 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
635 total_rx_packets++; 636 total_rx_packets++;
636 637
637 skb->protocol = eth_type_trans(skb, netdev); 638 skb->protocol = eth_type_trans(skb, netdev);
638 ixgbe_receive_skb(adapter, skb, is_vlan, vlan_tag); 639 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
639 netdev->last_rx = jiffies; 640 netdev->last_rx = jiffies;
640 641
641next_desc: 642next_desc:
@@ -652,8 +653,11 @@ next_desc:
652 rx_buffer_info = next_buffer; 653 rx_buffer_info = next_buffer;
653 654
654 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 655 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
655 is_vlan = (staterr & IXGBE_RXD_STAT_VP); 656 }
656 vlan_tag = le16_to_cpu(rx_desc->wb.upper.vlan); 657
658 if (rx_ring->lro_used) {
659 lro_flush_all(&rx_ring->lro_mgr);
660 rx_ring->lro_used = false;
657 } 661 }
658 662
659 rx_ring->next_to_clean = i; 663 rx_ring->next_to_clean = i;
@@ -1382,6 +1386,33 @@ static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1382 1386
1383#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 1387#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1384/** 1388/**
1389 * ixgbe_get_skb_hdr - helper function for LRO header processing
1390 * @skb: pointer to sk_buff to be added to LRO packet
1391 * @iphdr: pointer to tcp header structure
1392 * @tcph: pointer to tcp header structure
1393 * @hdr_flags: pointer to header flags
1394 * @priv: private data
1395 **/
1396static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1397 u64 *hdr_flags, void *priv)
1398{
1399 union ixgbe_adv_rx_desc *rx_desc = priv;
1400
1401 /* Verify that this is a valid IPv4 TCP packet */
1402 if (!(rx_desc->wb.lower.lo_dword.pkt_info &
1403 (IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP)))
1404 return -1;
1405
1406 /* Set network headers */
1407 skb_reset_network_header(skb);
1408 skb_set_transport_header(skb, ip_hdrlen(skb));
1409 *iphdr = ip_hdr(skb);
1410 *tcph = tcp_hdr(skb);
1411 *hdr_flags = LRO_IPV4 | LRO_TCP;
1412 return 0;
1413}
1414
1415/**
1385 * ixgbe_configure_rx - Configure 8254x Receive Unit after Reset 1416 * ixgbe_configure_rx - Configure 8254x Receive Unit after Reset
1386 * @adapter: board private structure 1417 * @adapter: board private structure
1387 * 1418 *
@@ -1470,6 +1501,17 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1470 adapter->rx_ring[i].tail = IXGBE_RDT(i); 1501 adapter->rx_ring[i].tail = IXGBE_RDT(i);
1471 } 1502 }
1472 1503
1504 /* Intitial LRO Settings */
1505 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1506 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1507 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1508 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1509 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1510 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1511 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1512 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1513 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1514
1473 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { 1515 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1474 /* Fill out redirection table */ 1516 /* Fill out redirection table */
1475 for (i = 0, j = 0; i < 128; i++, j++) { 1517 for (i = 0, j = 0; i < 128; i++, j++) {
@@ -1532,7 +1574,7 @@ static void ixgbe_vlan_rx_register(struct net_device *netdev,
1532 if (grp) { 1574 if (grp) {
1533 /* enable VLAN tag insert/strip */ 1575 /* enable VLAN tag insert/strip */
1534 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); 1576 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1535 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; 1577 ctrl |= IXGBE_VLNCTRL_VME;
1536 ctrl &= ~IXGBE_VLNCTRL_CFIEN; 1578 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1537 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); 1579 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1538 } 1580 }
@@ -1603,11 +1645,15 @@ static void ixgbe_set_multi(struct net_device *netdev)
1603 1645
1604 if (netdev->flags & IFF_PROMISC) { 1646 if (netdev->flags & IFF_PROMISC) {
1605 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 1647 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1606 } else if (netdev->flags & IFF_ALLMULTI) { 1648 fctrl &= ~IXGBE_VLNCTRL_VFE;
1607 fctrl |= IXGBE_FCTRL_MPE;
1608 fctrl &= ~IXGBE_FCTRL_UPE;
1609 } else { 1649 } else {
1610 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 1650 if (netdev->flags & IFF_ALLMULTI) {
1651 fctrl |= IXGBE_FCTRL_MPE;
1652 fctrl &= ~IXGBE_FCTRL_UPE;
1653 } else {
1654 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1655 }
1656 fctrl |= IXGBE_VLNCTRL_VFE;
1611 } 1657 }
1612 1658
1613 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1659 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
@@ -1967,7 +2013,7 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
1967 del_timer_sync(&adapter->watchdog_timer); 2013 del_timer_sync(&adapter->watchdog_timer);
1968 2014
1969 netif_carrier_off(netdev); 2015 netif_carrier_off(netdev);
1970 netif_stop_queue(netdev); 2016 netif_tx_stop_all_queues(netdev);
1971 2017
1972 if (!pci_channel_offline(adapter->pdev)) 2018 if (!pci_channel_offline(adapter->pdev))
1973 ixgbe_reset(adapter); 2019 ixgbe_reset(adapter);
@@ -2138,11 +2184,7 @@ static void __devinit ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2138 case (IXGBE_FLAG_RSS_ENABLED): 2184 case (IXGBE_FLAG_RSS_ENABLED):
2139 rss_m = 0xF; 2185 rss_m = 0xF;
2140 nrq = rss_i; 2186 nrq = rss_i;
2141#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2142 ntq = rss_i; 2187 ntq = rss_i;
2143#else
2144 ntq = 1;
2145#endif
2146 break; 2188 break;
2147 case 0: 2189 case 0:
2148 default: 2190 default:
@@ -2316,10 +2358,8 @@ try_msi:
2316 } 2358 }
2317 2359
2318out: 2360out:
2319#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2320 /* Notify the stack of the (possibly) reduced Tx Queue count. */ 2361 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2321 adapter->netdev->egress_subqueue_count = adapter->num_tx_queues; 2362 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2322#endif
2323 2363
2324 return err; 2364 return err;
2325} 2365}
@@ -2490,12 +2530,18 @@ int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2490 struct pci_dev *pdev = adapter->pdev; 2530 struct pci_dev *pdev = adapter->pdev;
2491 int size; 2531 int size;
2492 2532
2533 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
2534 rxdr->lro_mgr.lro_arr = vmalloc(size);
2535 if (!rxdr->lro_mgr.lro_arr)
2536 return -ENOMEM;
2537 memset(rxdr->lro_mgr.lro_arr, 0, size);
2538
2493 size = sizeof(struct ixgbe_rx_buffer) * rxdr->count; 2539 size = sizeof(struct ixgbe_rx_buffer) * rxdr->count;
2494 rxdr->rx_buffer_info = vmalloc(size); 2540 rxdr->rx_buffer_info = vmalloc(size);
2495 if (!rxdr->rx_buffer_info) { 2541 if (!rxdr->rx_buffer_info) {
2496 DPRINTK(PROBE, ERR, 2542 DPRINTK(PROBE, ERR,
2497 "vmalloc allocation failed for the rx desc ring\n"); 2543 "vmalloc allocation failed for the rx desc ring\n");
2498 return -ENOMEM; 2544 goto alloc_failed;
2499 } 2545 }
2500 memset(rxdr->rx_buffer_info, 0, size); 2546 memset(rxdr->rx_buffer_info, 0, size);
2501 2547
@@ -2509,13 +2555,18 @@ int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2509 DPRINTK(PROBE, ERR, 2555 DPRINTK(PROBE, ERR,
2510 "Memory allocation failed for the rx desc ring\n"); 2556 "Memory allocation failed for the rx desc ring\n");
2511 vfree(rxdr->rx_buffer_info); 2557 vfree(rxdr->rx_buffer_info);
2512 return -ENOMEM; 2558 goto alloc_failed;
2513 } 2559 }
2514 2560
2515 rxdr->next_to_clean = 0; 2561 rxdr->next_to_clean = 0;
2516 rxdr->next_to_use = 0; 2562 rxdr->next_to_use = 0;
2517 2563
2518 return 0; 2564 return 0;
2565
2566alloc_failed:
2567 vfree(rxdr->lro_mgr.lro_arr);
2568 rxdr->lro_mgr.lro_arr = NULL;
2569 return -ENOMEM;
2519} 2570}
2520 2571
2521/** 2572/**
@@ -2566,6 +2617,9 @@ static void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2566{ 2617{
2567 struct pci_dev *pdev = adapter->pdev; 2618 struct pci_dev *pdev = adapter->pdev;
2568 2619
2620 vfree(rx_ring->lro_mgr.lro_arr);
2621 rx_ring->lro_mgr.lro_arr = NULL;
2622
2569 ixgbe_clean_rx_ring(adapter, rx_ring); 2623 ixgbe_clean_rx_ring(adapter, rx_ring);
2570 2624
2571 vfree(rx_ring->rx_buffer_info); 2625 vfree(rx_ring->rx_buffer_info);
@@ -2711,6 +2765,8 @@ static int ixgbe_open(struct net_device *netdev)
2711 if (err) 2765 if (err)
2712 goto err_up; 2766 goto err_up;
2713 2767
2768 netif_tx_start_all_queues(netdev);
2769
2714 return 0; 2770 return 0;
2715 2771
2716err_up: 2772err_up:
@@ -2842,9 +2898,6 @@ static void ixgbe_watchdog(unsigned long data)
2842 struct net_device *netdev = adapter->netdev; 2898 struct net_device *netdev = adapter->netdev;
2843 bool link_up; 2899 bool link_up;
2844 u32 link_speed = 0; 2900 u32 link_speed = 0;
2845#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2846 int i;
2847#endif
2848 2901
2849 adapter->hw.mac.ops.check_link(&adapter->hw, &(link_speed), &link_up); 2902 adapter->hw.mac.ops.check_link(&adapter->hw, &(link_speed), &link_up);
2850 2903
@@ -2865,11 +2918,7 @@ static void ixgbe_watchdog(unsigned long data)
2865 (FLOW_TX ? "TX" : "None")))); 2918 (FLOW_TX ? "TX" : "None"))));
2866 2919
2867 netif_carrier_on(netdev); 2920 netif_carrier_on(netdev);
2868 netif_wake_queue(netdev); 2921 netif_tx_wake_all_queues(netdev);
2869#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2870 for (i = 0; i < adapter->num_tx_queues; i++)
2871 netif_wake_subqueue(netdev, i);
2872#endif
2873 } else { 2922 } else {
2874 /* Force detection of hung controller */ 2923 /* Force detection of hung controller */
2875 adapter->detect_tx_hung = true; 2924 adapter->detect_tx_hung = true;
@@ -2878,7 +2927,7 @@ static void ixgbe_watchdog(unsigned long data)
2878 if (netif_carrier_ok(netdev)) { 2927 if (netif_carrier_ok(netdev)) {
2879 DPRINTK(LINK, INFO, "NIC Link is Down\n"); 2928 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2880 netif_carrier_off(netdev); 2929 netif_carrier_off(netdev);
2881 netif_stop_queue(netdev); 2930 netif_tx_stop_all_queues(netdev);
2882 } 2931 }
2883 } 2932 }
2884 2933
@@ -3196,11 +3245,7 @@ static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3196{ 3245{
3197 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3246 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3198 3247
3199#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3200 netif_stop_subqueue(netdev, tx_ring->queue_index); 3248 netif_stop_subqueue(netdev, tx_ring->queue_index);
3201#else
3202 netif_stop_queue(netdev);
3203#endif
3204 /* Herbert's original patch had: 3249 /* Herbert's original patch had:
3205 * smp_mb__after_netif_stop_queue(); 3250 * smp_mb__after_netif_stop_queue();
3206 * but since that doesn't exist yet, just open code it. */ 3251 * but since that doesn't exist yet, just open code it. */
@@ -3212,11 +3257,7 @@ static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3212 return -EBUSY; 3257 return -EBUSY;
3213 3258
3214 /* A reprieve! - use start_queue because it doesn't call schedule */ 3259 /* A reprieve! - use start_queue because it doesn't call schedule */
3215#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3216 netif_wake_subqueue(netdev, tx_ring->queue_index); 3260 netif_wake_subqueue(netdev, tx_ring->queue_index);
3217#else
3218 netif_wake_queue(netdev);
3219#endif
3220 ++adapter->restart_queue; 3261 ++adapter->restart_queue;
3221 return 0; 3262 return 0;
3222} 3263}
@@ -3244,9 +3285,7 @@ static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3244 unsigned int f; 3285 unsigned int f;
3245 unsigned int nr_frags = skb_shinfo(skb)->nr_frags; 3286 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3246 len -= skb->data_len; 3287 len -= skb->data_len;
3247#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3248 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping; 3288 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
3249#endif
3250 tx_ring = &adapter->tx_ring[r_idx]; 3289 tx_ring = &adapter->tx_ring[r_idx];
3251 3290
3252 3291
@@ -3434,11 +3473,7 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
3434 pci_set_master(pdev); 3473 pci_set_master(pdev);
3435 pci_save_state(pdev); 3474 pci_save_state(pdev);
3436 3475
3437#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3438 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); 3476 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
3439#else
3440 netdev = alloc_etherdev(sizeof(struct ixgbe_adapter));
3441#endif
3442 if (!netdev) { 3477 if (!netdev) {
3443 err = -ENOMEM; 3478 err = -ENOMEM;
3444 goto err_alloc_etherdev; 3479 goto err_alloc_etherdev;
@@ -3518,16 +3553,18 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
3518 NETIF_F_HW_VLAN_RX | 3553 NETIF_F_HW_VLAN_RX |
3519 NETIF_F_HW_VLAN_FILTER; 3554 NETIF_F_HW_VLAN_FILTER;
3520 3555
3556 netdev->features |= NETIF_F_LRO;
3521 netdev->features |= NETIF_F_TSO; 3557 netdev->features |= NETIF_F_TSO;
3522
3523 netdev->features |= NETIF_F_TSO6; 3558 netdev->features |= NETIF_F_TSO6;
3559
3560 netdev->vlan_features |= NETIF_F_TSO;
3561 netdev->vlan_features |= NETIF_F_TSO6;
3562 netdev->vlan_features |= NETIF_F_HW_CSUM;
3563 netdev->vlan_features |= NETIF_F_SG;
3564
3524 if (pci_using_dac) 3565 if (pci_using_dac)
3525 netdev->features |= NETIF_F_HIGHDMA; 3566 netdev->features |= NETIF_F_HIGHDMA;
3526 3567
3527#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3528 netdev->features |= NETIF_F_MULTI_QUEUE;
3529#endif
3530
3531 /* make sure the EEPROM is good */ 3568 /* make sure the EEPROM is good */
3532 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) { 3569 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
3533 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); 3570 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
@@ -3593,11 +3630,7 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
3593 ixgbe_start_hw(hw); 3630 ixgbe_start_hw(hw);
3594 3631
3595 netif_carrier_off(netdev); 3632 netif_carrier_off(netdev);
3596 netif_stop_queue(netdev); 3633 netif_tx_stop_all_queues(netdev);
3597#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3598 for (i = 0; i < adapter->num_tx_queues; i++)
3599 netif_stop_subqueue(netdev, i);
3600#endif
3601 3634
3602 ixgbe_napi_add_all(adapter); 3635 ixgbe_napi_add_all(adapter);
3603 3636
diff --git a/drivers/net/ixp2000/ixpdev.c b/drivers/net/ixp2000/ixpdev.c
index 484cb2ba717f..7111c65f0b30 100644
--- a/drivers/net/ixp2000/ixpdev.c
+++ b/drivers/net/ixp2000/ixpdev.c
@@ -108,14 +108,14 @@ static int ixpdev_rx(struct net_device *dev, int processed, int budget)
108 if (unlikely(!netif_running(nds[desc->channel]))) 108 if (unlikely(!netif_running(nds[desc->channel])))
109 goto err; 109 goto err;
110 110
111 skb = dev_alloc_skb(desc->pkt_length + 2); 111 skb = netdev_alloc_skb(dev, desc->pkt_length + 2);
112 if (likely(skb != NULL)) { 112 if (likely(skb != NULL)) {
113 skb_reserve(skb, 2); 113 skb_reserve(skb, 2);
114 skb_copy_to_linear_data(skb, buf, desc->pkt_length); 114 skb_copy_to_linear_data(skb, buf, desc->pkt_length);
115 skb_put(skb, desc->pkt_length); 115 skb_put(skb, desc->pkt_length);
116 skb->protocol = eth_type_trans(skb, nds[desc->channel]); 116 skb->protocol = eth_type_trans(skb, nds[desc->channel]);
117 117
118 skb->dev->last_rx = jiffies; 118 dev->last_rx = jiffies;
119 119
120 netif_receive_skb(skb); 120 netif_receive_skb(skb);
121 } 121 }
diff --git a/drivers/net/lib8390.c b/drivers/net/lib8390.c
index 0c5447dac03b..00d59ab2f8ac 100644
--- a/drivers/net/lib8390.c
+++ b/drivers/net/lib8390.c
@@ -150,19 +150,19 @@ static void __NS8390_init(struct net_device *dev, int startp);
150 * card means that approach caused horrible problems like losing serial data 150 * card means that approach caused horrible problems like losing serial data
151 * at 38400 baud on some chips. Remember many 8390 nics on PCI were ISA 151 * at 38400 baud on some chips. Remember many 8390 nics on PCI were ISA
152 * chips with FPGA front ends. 152 * chips with FPGA front ends.
153 * 153 *
154 * Ok the logic behind the 8390 is very simple: 154 * Ok the logic behind the 8390 is very simple:
155 * 155 *
156 * Things to know 156 * Things to know
157 * - IRQ delivery is asynchronous to the PCI bus 157 * - IRQ delivery is asynchronous to the PCI bus
158 * - Blocking the local CPU IRQ via spin locks was too slow 158 * - Blocking the local CPU IRQ via spin locks was too slow
159 * - The chip has register windows needing locking work 159 * - The chip has register windows needing locking work
160 * 160 *
161 * So the path was once (I say once as people appear to have changed it 161 * So the path was once (I say once as people appear to have changed it
162 * in the mean time and it now looks rather bogus if the changes to use 162 * in the mean time and it now looks rather bogus if the changes to use
163 * disable_irq_nosync_irqsave are disabling the local IRQ) 163 * disable_irq_nosync_irqsave are disabling the local IRQ)
164 * 164 *
165 * 165 *
166 * Take the page lock 166 * Take the page lock
167 * Mask the IRQ on chip 167 * Mask the IRQ on chip
168 * Disable the IRQ (but not mask locally- someone seems to have 168 * Disable the IRQ (but not mask locally- someone seems to have
@@ -170,22 +170,22 @@ static void __NS8390_init(struct net_device *dev, int startp);
170 * [This must be _nosync as the page lock may otherwise 170 * [This must be _nosync as the page lock may otherwise
171 * deadlock us] 171 * deadlock us]
172 * Drop the page lock and turn IRQs back on 172 * Drop the page lock and turn IRQs back on
173 * 173 *
174 * At this point an existing IRQ may still be running but we can't 174 * At this point an existing IRQ may still be running but we can't
175 * get a new one 175 * get a new one
176 * 176 *
177 * Take the lock (so we know the IRQ has terminated) but don't mask 177 * Take the lock (so we know the IRQ has terminated) but don't mask
178 * the IRQs on the processor 178 * the IRQs on the processor
179 * Set irqlock [for debug] 179 * Set irqlock [for debug]
180 * 180 *
181 * Transmit (slow as ****) 181 * Transmit (slow as ****)
182 * 182 *
183 * re-enable the IRQ 183 * re-enable the IRQ
184 * 184 *
185 * 185 *
186 * We have to use disable_irq because otherwise you will get delayed 186 * We have to use disable_irq because otherwise you will get delayed
187 * interrupts on the APIC bus deadlocking the transmit path. 187 * interrupts on the APIC bus deadlocking the transmit path.
188 * 188 *
189 * Quite hairy but the chip simply wasn't designed for SMP and you can't 189 * Quite hairy but the chip simply wasn't designed for SMP and you can't
190 * even ACK an interrupt without risking corrupting other parallel 190 * even ACK an interrupt without risking corrupting other parallel
191 * activities on the chip." [lkml, 25 Jul 2007] 191 * activities on the chip." [lkml, 25 Jul 2007]
@@ -265,7 +265,7 @@ static void ei_tx_timeout(struct net_device *dev)
265 int txsr, isr, tickssofar = jiffies - dev->trans_start; 265 int txsr, isr, tickssofar = jiffies - dev->trans_start;
266 unsigned long flags; 266 unsigned long flags;
267 267
268 ei_local->stat.tx_errors++; 268 dev->stats.tx_errors++;
269 269
270 spin_lock_irqsave(&ei_local->page_lock, flags); 270 spin_lock_irqsave(&ei_local->page_lock, flags);
271 txsr = ei_inb(e8390_base+EN0_TSR); 271 txsr = ei_inb(e8390_base+EN0_TSR);
@@ -276,7 +276,7 @@ static void ei_tx_timeout(struct net_device *dev)
276 dev->name, (txsr & ENTSR_ABT) ? "excess collisions." : 276 dev->name, (txsr & ENTSR_ABT) ? "excess collisions." :
277 (isr) ? "lost interrupt?" : "cable problem?", txsr, isr, tickssofar); 277 (isr) ? "lost interrupt?" : "cable problem?", txsr, isr, tickssofar);
278 278
279 if (!isr && !ei_local->stat.tx_packets) 279 if (!isr && !dev->stats.tx_packets)
280 { 280 {
281 /* The 8390 probably hasn't gotten on the cable yet. */ 281 /* The 8390 probably hasn't gotten on the cable yet. */
282 ei_local->interface_num ^= 1; /* Try a different xcvr. */ 282 ei_local->interface_num ^= 1; /* Try a different xcvr. */
@@ -374,7 +374,7 @@ static int ei_start_xmit(struct sk_buff *skb, struct net_device *dev)
374 ei_outb_p(ENISR_ALL, e8390_base + EN0_IMR); 374 ei_outb_p(ENISR_ALL, e8390_base + EN0_IMR);
375 spin_unlock(&ei_local->page_lock); 375 spin_unlock(&ei_local->page_lock);
376 enable_irq_lockdep_irqrestore(dev->irq, &flags); 376 enable_irq_lockdep_irqrestore(dev->irq, &flags);
377 ei_local->stat.tx_errors++; 377 dev->stats.tx_errors++;
378 return 1; 378 return 1;
379 } 379 }
380 380
@@ -417,7 +417,7 @@ static int ei_start_xmit(struct sk_buff *skb, struct net_device *dev)
417 enable_irq_lockdep_irqrestore(dev->irq, &flags); 417 enable_irq_lockdep_irqrestore(dev->irq, &flags);
418 418
419 dev_kfree_skb (skb); 419 dev_kfree_skb (skb);
420 ei_local->stat.tx_bytes += send_length; 420 dev->stats.tx_bytes += send_length;
421 421
422 return 0; 422 return 0;
423} 423}
@@ -493,9 +493,9 @@ static irqreturn_t __ei_interrupt(int irq, void *dev_id)
493 493
494 if (interrupts & ENISR_COUNTERS) 494 if (interrupts & ENISR_COUNTERS)
495 { 495 {
496 ei_local->stat.rx_frame_errors += ei_inb_p(e8390_base + EN0_COUNTER0); 496 dev->stats.rx_frame_errors += ei_inb_p(e8390_base + EN0_COUNTER0);
497 ei_local->stat.rx_crc_errors += ei_inb_p(e8390_base + EN0_COUNTER1); 497 dev->stats.rx_crc_errors += ei_inb_p(e8390_base + EN0_COUNTER1);
498 ei_local->stat.rx_missed_errors+= ei_inb_p(e8390_base + EN0_COUNTER2); 498 dev->stats.rx_missed_errors+= ei_inb_p(e8390_base + EN0_COUNTER2);
499 ei_outb_p(ENISR_COUNTERS, e8390_base + EN0_ISR); /* Ack intr. */ 499 ei_outb_p(ENISR_COUNTERS, e8390_base + EN0_ISR); /* Ack intr. */
500 } 500 }
501 501
@@ -553,7 +553,8 @@ static void __ei_poll(struct net_device *dev)
553static void ei_tx_err(struct net_device *dev) 553static void ei_tx_err(struct net_device *dev)
554{ 554{
555 unsigned long e8390_base = dev->base_addr; 555 unsigned long e8390_base = dev->base_addr;
556 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev); 556 /* ei_local is used on some platforms via the EI_SHIFT macro */
557 struct ei_device *ei_local __maybe_unused = netdev_priv(dev);
557 unsigned char txsr = ei_inb_p(e8390_base+EN0_TSR); 558 unsigned char txsr = ei_inb_p(e8390_base+EN0_TSR);
558 unsigned char tx_was_aborted = txsr & (ENTSR_ABT+ENTSR_FU); 559 unsigned char tx_was_aborted = txsr & (ENTSR_ABT+ENTSR_FU);
559 560
@@ -578,10 +579,10 @@ static void ei_tx_err(struct net_device *dev)
578 ei_tx_intr(dev); 579 ei_tx_intr(dev);
579 else 580 else
580 { 581 {
581 ei_local->stat.tx_errors++; 582 dev->stats.tx_errors++;
582 if (txsr & ENTSR_CRS) ei_local->stat.tx_carrier_errors++; 583 if (txsr & ENTSR_CRS) dev->stats.tx_carrier_errors++;
583 if (txsr & ENTSR_CDH) ei_local->stat.tx_heartbeat_errors++; 584 if (txsr & ENTSR_CDH) dev->stats.tx_heartbeat_errors++;
584 if (txsr & ENTSR_OWC) ei_local->stat.tx_window_errors++; 585 if (txsr & ENTSR_OWC) dev->stats.tx_window_errors++;
585 } 586 }
586} 587}
587 588
@@ -645,25 +646,25 @@ static void ei_tx_intr(struct net_device *dev)
645 646
646 /* Minimize Tx latency: update the statistics after we restart TXing. */ 647 /* Minimize Tx latency: update the statistics after we restart TXing. */
647 if (status & ENTSR_COL) 648 if (status & ENTSR_COL)
648 ei_local->stat.collisions++; 649 dev->stats.collisions++;
649 if (status & ENTSR_PTX) 650 if (status & ENTSR_PTX)
650 ei_local->stat.tx_packets++; 651 dev->stats.tx_packets++;
651 else 652 else
652 { 653 {
653 ei_local->stat.tx_errors++; 654 dev->stats.tx_errors++;
654 if (status & ENTSR_ABT) 655 if (status & ENTSR_ABT)
655 { 656 {
656 ei_local->stat.tx_aborted_errors++; 657 dev->stats.tx_aborted_errors++;
657 ei_local->stat.collisions += 16; 658 dev->stats.collisions += 16;
658 } 659 }
659 if (status & ENTSR_CRS) 660 if (status & ENTSR_CRS)
660 ei_local->stat.tx_carrier_errors++; 661 dev->stats.tx_carrier_errors++;
661 if (status & ENTSR_FU) 662 if (status & ENTSR_FU)
662 ei_local->stat.tx_fifo_errors++; 663 dev->stats.tx_fifo_errors++;
663 if (status & ENTSR_CDH) 664 if (status & ENTSR_CDH)
664 ei_local->stat.tx_heartbeat_errors++; 665 dev->stats.tx_heartbeat_errors++;
665 if (status & ENTSR_OWC) 666 if (status & ENTSR_OWC)
666 ei_local->stat.tx_window_errors++; 667 dev->stats.tx_window_errors++;
667 } 668 }
668 netif_wake_queue(dev); 669 netif_wake_queue(dev);
669} 670}
@@ -730,7 +731,7 @@ static void ei_receive(struct net_device *dev)
730 && rx_frame.next != next_frame + 1 - num_rx_pages) { 731 && rx_frame.next != next_frame + 1 - num_rx_pages) {
731 ei_local->current_page = rxing_page; 732 ei_local->current_page = rxing_page;
732 ei_outb(ei_local->current_page-1, e8390_base+EN0_BOUNDARY); 733 ei_outb(ei_local->current_page-1, e8390_base+EN0_BOUNDARY);
733 ei_local->stat.rx_errors++; 734 dev->stats.rx_errors++;
734 continue; 735 continue;
735 } 736 }
736 737
@@ -740,8 +741,8 @@ static void ei_receive(struct net_device *dev)
740 printk(KERN_DEBUG "%s: bogus packet size: %d, status=%#2x nxpg=%#2x.\n", 741 printk(KERN_DEBUG "%s: bogus packet size: %d, status=%#2x nxpg=%#2x.\n",
741 dev->name, rx_frame.count, rx_frame.status, 742 dev->name, rx_frame.count, rx_frame.status,
742 rx_frame.next); 743 rx_frame.next);
743 ei_local->stat.rx_errors++; 744 dev->stats.rx_errors++;
744 ei_local->stat.rx_length_errors++; 745 dev->stats.rx_length_errors++;
745 } 746 }
746 else if ((pkt_stat & 0x0F) == ENRSR_RXOK) 747 else if ((pkt_stat & 0x0F) == ENRSR_RXOK)
747 { 748 {
@@ -753,7 +754,7 @@ static void ei_receive(struct net_device *dev)
753 if (ei_debug > 1) 754 if (ei_debug > 1)
754 printk(KERN_DEBUG "%s: Couldn't allocate a sk_buff of size %d.\n", 755 printk(KERN_DEBUG "%s: Couldn't allocate a sk_buff of size %d.\n",
755 dev->name, pkt_len); 756 dev->name, pkt_len);
756 ei_local->stat.rx_dropped++; 757 dev->stats.rx_dropped++;
757 break; 758 break;
758 } 759 }
759 else 760 else
@@ -764,10 +765,10 @@ static void ei_receive(struct net_device *dev)
764 skb->protocol=eth_type_trans(skb,dev); 765 skb->protocol=eth_type_trans(skb,dev);
765 netif_rx(skb); 766 netif_rx(skb);
766 dev->last_rx = jiffies; 767 dev->last_rx = jiffies;
767 ei_local->stat.rx_packets++; 768 dev->stats.rx_packets++;
768 ei_local->stat.rx_bytes += pkt_len; 769 dev->stats.rx_bytes += pkt_len;
769 if (pkt_stat & ENRSR_PHY) 770 if (pkt_stat & ENRSR_PHY)
770 ei_local->stat.multicast++; 771 dev->stats.multicast++;
771 } 772 }
772 } 773 }
773 else 774 else
@@ -776,10 +777,10 @@ static void ei_receive(struct net_device *dev)
776 printk(KERN_DEBUG "%s: bogus packet: status=%#2x nxpg=%#2x size=%d\n", 777 printk(KERN_DEBUG "%s: bogus packet: status=%#2x nxpg=%#2x size=%d\n",
777 dev->name, rx_frame.status, rx_frame.next, 778 dev->name, rx_frame.status, rx_frame.next,
778 rx_frame.count); 779 rx_frame.count);
779 ei_local->stat.rx_errors++; 780 dev->stats.rx_errors++;
780 /* NB: The NIC counts CRC, frame and missed errors. */ 781 /* NB: The NIC counts CRC, frame and missed errors. */
781 if (pkt_stat & ENRSR_FO) 782 if (pkt_stat & ENRSR_FO)
782 ei_local->stat.rx_fifo_errors++; 783 dev->stats.rx_fifo_errors++;
783 } 784 }
784 next_frame = rx_frame.next; 785 next_frame = rx_frame.next;
785 786
@@ -816,7 +817,8 @@ static void ei_rx_overrun(struct net_device *dev)
816{ 817{
817 unsigned long e8390_base = dev->base_addr; 818 unsigned long e8390_base = dev->base_addr;
818 unsigned char was_txing, must_resend = 0; 819 unsigned char was_txing, must_resend = 0;
819 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev); 820 /* ei_local is used on some platforms via the EI_SHIFT macro */
821 struct ei_device *ei_local __maybe_unused = netdev_priv(dev);
820 822
821 /* 823 /*
822 * Record whether a Tx was in progress and then issue the 824 * Record whether a Tx was in progress and then issue the
@@ -827,7 +829,7 @@ static void ei_rx_overrun(struct net_device *dev)
827 829
828 if (ei_debug > 1) 830 if (ei_debug > 1)
829 printk(KERN_DEBUG "%s: Receiver overrun.\n", dev->name); 831 printk(KERN_DEBUG "%s: Receiver overrun.\n", dev->name);
830 ei_local->stat.rx_over_errors++; 832 dev->stats.rx_over_errors++;
831 833
832 /* 834 /*
833 * Wait a full Tx time (1.2ms) + some guard time, NS says 1.6ms total. 835 * Wait a full Tx time (1.2ms) + some guard time, NS says 1.6ms total.
@@ -889,16 +891,16 @@ static struct net_device_stats *get_stats(struct net_device *dev)
889 891
890 /* If the card is stopped, just return the present stats. */ 892 /* If the card is stopped, just return the present stats. */
891 if (!netif_running(dev)) 893 if (!netif_running(dev))
892 return &ei_local->stat; 894 return &dev->stats;
893 895
894 spin_lock_irqsave(&ei_local->page_lock,flags); 896 spin_lock_irqsave(&ei_local->page_lock,flags);
895 /* Read the counter registers, assuming we are in page 0. */ 897 /* Read the counter registers, assuming we are in page 0. */
896 ei_local->stat.rx_frame_errors += ei_inb_p(ioaddr + EN0_COUNTER0); 898 dev->stats.rx_frame_errors += ei_inb_p(ioaddr + EN0_COUNTER0);
897 ei_local->stat.rx_crc_errors += ei_inb_p(ioaddr + EN0_COUNTER1); 899 dev->stats.rx_crc_errors += ei_inb_p(ioaddr + EN0_COUNTER1);
898 ei_local->stat.rx_missed_errors+= ei_inb_p(ioaddr + EN0_COUNTER2); 900 dev->stats.rx_missed_errors+= ei_inb_p(ioaddr + EN0_COUNTER2);
899 spin_unlock_irqrestore(&ei_local->page_lock, flags); 901 spin_unlock_irqrestore(&ei_local->page_lock, flags);
900 902
901 return &ei_local->stat; 903 return &dev->stats;
902} 904}
903 905
904/* 906/*
diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c
index 41b774baac4d..49f6bc036a92 100644
--- a/drivers/net/loopback.c
+++ b/drivers/net/loopback.c
@@ -153,7 +153,7 @@ static int loopback_xmit(struct sk_buff *skb, struct net_device *dev)
153 dev->last_rx = jiffies; 153 dev->last_rx = jiffies;
154 154
155 /* it's OK to use per_cpu_ptr() because BHs are off */ 155 /* it's OK to use per_cpu_ptr() because BHs are off */
156 pcpu_lstats = netdev_priv(dev); 156 pcpu_lstats = dev->ml_priv;
157 lb_stats = per_cpu_ptr(pcpu_lstats, smp_processor_id()); 157 lb_stats = per_cpu_ptr(pcpu_lstats, smp_processor_id());
158 lb_stats->bytes += skb->len; 158 lb_stats->bytes += skb->len;
159 lb_stats->packets++; 159 lb_stats->packets++;
@@ -171,7 +171,7 @@ static struct net_device_stats *get_stats(struct net_device *dev)
171 unsigned long packets = 0; 171 unsigned long packets = 0;
172 int i; 172 int i;
173 173
174 pcpu_lstats = netdev_priv(dev); 174 pcpu_lstats = dev->ml_priv;
175 for_each_possible_cpu(i) { 175 for_each_possible_cpu(i) {
176 const struct pcpu_lstats *lb_stats; 176 const struct pcpu_lstats *lb_stats;
177 177
@@ -207,13 +207,13 @@ static int loopback_dev_init(struct net_device *dev)
207 if (!lstats) 207 if (!lstats)
208 return -ENOMEM; 208 return -ENOMEM;
209 209
210 dev->priv = lstats; 210 dev->ml_priv = lstats;
211 return 0; 211 return 0;
212} 212}
213 213
214static void loopback_dev_free(struct net_device *dev) 214static void loopback_dev_free(struct net_device *dev)
215{ 215{
216 struct pcpu_lstats *lstats = netdev_priv(dev); 216 struct pcpu_lstats *lstats = dev->ml_priv;
217 217
218 free_percpu(lstats); 218 free_percpu(lstats);
219 free_netdev(dev); 219 free_netdev(dev);
diff --git a/drivers/net/mac8390.c b/drivers/net/mac8390.c
index 9e700749bb31..98e3eb2697c9 100644
--- a/drivers/net/mac8390.c
+++ b/drivers/net/mac8390.c
@@ -117,8 +117,6 @@ enum mac8390_access {
117 ACCESS_16, 117 ACCESS_16,
118}; 118};
119 119
120extern enum mac8390_type mac8390_ident(struct nubus_dev * dev);
121extern int mac8390_memsize(unsigned long membase);
122extern int mac8390_memtest(struct net_device * dev); 120extern int mac8390_memtest(struct net_device * dev);
123static int mac8390_initdev(struct net_device * dev, struct nubus_dev * ndev, 121static int mac8390_initdev(struct net_device * dev, struct nubus_dev * ndev,
124 enum mac8390_type type); 122 enum mac8390_type type);
@@ -163,7 +161,7 @@ static void slow_sane_block_output(struct net_device *dev, int count,
163static void word_memcpy_tocard(void *tp, const void *fp, int count); 161static void word_memcpy_tocard(void *tp, const void *fp, int count);
164static void word_memcpy_fromcard(void *tp, const void *fp, int count); 162static void word_memcpy_fromcard(void *tp, const void *fp, int count);
165 163
166enum mac8390_type __init mac8390_ident(struct nubus_dev * dev) 164static enum mac8390_type __init mac8390_ident(struct nubus_dev *dev)
167{ 165{
168 switch (dev->dr_sw) { 166 switch (dev->dr_sw) {
169 case NUBUS_DRSW_3COM: 167 case NUBUS_DRSW_3COM:
@@ -234,7 +232,7 @@ enum mac8390_type __init mac8390_ident(struct nubus_dev * dev)
234 return MAC8390_NONE; 232 return MAC8390_NONE;
235} 233}
236 234
237enum mac8390_access __init mac8390_testio(volatile unsigned long membase) 235static enum mac8390_access __init mac8390_testio(volatile unsigned long membase)
238{ 236{
239 unsigned long outdata = 0xA5A0B5B0; 237 unsigned long outdata = 0xA5A0B5B0;
240 unsigned long indata = 0x00000000; 238 unsigned long indata = 0x00000000;
@@ -252,7 +250,7 @@ enum mac8390_access __init mac8390_testio(volatile unsigned long membase)
252 return ACCESS_UNKNOWN; 250 return ACCESS_UNKNOWN;
253} 251}
254 252
255int __init mac8390_memsize(unsigned long membase) 253static int __init mac8390_memsize(unsigned long membase)
256{ 254{
257 unsigned long flags; 255 unsigned long flags;
258 int i, j; 256 int i, j;
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 0a5745a854c7..0496d16f9de5 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -80,8 +80,12 @@ static void __init macb_get_hwaddr(struct macb *bp)
80 addr[4] = top & 0xff; 80 addr[4] = top & 0xff;
81 addr[5] = (top >> 8) & 0xff; 81 addr[5] = (top >> 8) & 0xff;
82 82
83 if (is_valid_ether_addr(addr)) 83 if (is_valid_ether_addr(addr)) {
84 memcpy(bp->dev->dev_addr, addr, sizeof(addr)); 84 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
85 } else {
86 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
87 random_ether_addr(bp->dev->dev_addr);
88 }
85} 89}
86 90
87static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 91static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
@@ -161,7 +165,7 @@ static void macb_handle_link_change(struct net_device *dev)
161 165
162 if (phydev->link != bp->link) { 166 if (phydev->link != bp->link) {
163 if (phydev->link) 167 if (phydev->link)
164 netif_schedule(dev); 168 netif_tx_schedule_all(dev);
165 else { 169 else {
166 bp->speed = 0; 170 bp->speed = 0;
167 bp->duplex = -1; 171 bp->duplex = -1;
diff --git a/drivers/net/macsonic.c b/drivers/net/macsonic.c
index b267161418ea..e64c2086d33c 100644
--- a/drivers/net/macsonic.c
+++ b/drivers/net/macsonic.c
@@ -83,9 +83,6 @@ static unsigned int sonic_debug = 1;
83 83
84static int sonic_version_printed; 84static int sonic_version_printed;
85 85
86extern int mac_onboard_sonic_probe(struct net_device* dev);
87extern int mac_nubus_sonic_probe(struct net_device* dev);
88
89/* For onboard SONIC */ 86/* For onboard SONIC */
90#define ONBOARD_SONIC_REGISTERS 0x50F0A000 87#define ONBOARD_SONIC_REGISTERS 0x50F0A000
91#define ONBOARD_SONIC_PROM_BASE 0x50f08000 88#define ONBOARD_SONIC_PROM_BASE 0x50f08000
@@ -170,7 +167,7 @@ static int macsonic_close(struct net_device* dev)
170 return err; 167 return err;
171} 168}
172 169
173int __init macsonic_init(struct net_device* dev) 170static int __init macsonic_init(struct net_device *dev)
174{ 171{
175 struct sonic_local* lp = netdev_priv(dev); 172 struct sonic_local* lp = netdev_priv(dev);
176 173
@@ -218,7 +215,7 @@ int __init macsonic_init(struct net_device* dev)
218 return 0; 215 return 0;
219} 216}
220 217
221int __init mac_onboard_sonic_ethernet_addr(struct net_device* dev) 218static int __init mac_onboard_sonic_ethernet_addr(struct net_device *dev)
222{ 219{
223 struct sonic_local *lp = netdev_priv(dev); 220 struct sonic_local *lp = netdev_priv(dev);
224 const int prom_addr = ONBOARD_SONIC_PROM_BASE; 221 const int prom_addr = ONBOARD_SONIC_PROM_BASE;
@@ -284,7 +281,7 @@ int __init mac_onboard_sonic_ethernet_addr(struct net_device* dev)
284 } else return 0; 281 } else return 0;
285} 282}
286 283
287int __init mac_onboard_sonic_probe(struct net_device* dev) 284static int __init mac_onboard_sonic_probe(struct net_device *dev)
288{ 285{
289 /* Bwahahaha */ 286 /* Bwahahaha */
290 static int once_is_more_than_enough; 287 static int once_is_more_than_enough;
@@ -405,9 +402,9 @@ int __init mac_onboard_sonic_probe(struct net_device* dev)
405 return macsonic_init(dev); 402 return macsonic_init(dev);
406} 403}
407 404
408int __init mac_nubus_sonic_ethernet_addr(struct net_device* dev, 405static int __init mac_nubus_sonic_ethernet_addr(struct net_device *dev,
409 unsigned long prom_addr, 406 unsigned long prom_addr,
410 int id) 407 int id)
411{ 408{
412 int i; 409 int i;
413 for(i = 0; i < 6; i++) 410 for(i = 0; i < 6; i++)
@@ -420,7 +417,7 @@ int __init mac_nubus_sonic_ethernet_addr(struct net_device* dev,
420 return 0; 417 return 0;
421} 418}
422 419
423int __init macsonic_ident(struct nubus_dev* ndev) 420static int __init macsonic_ident(struct nubus_dev *ndev)
424{ 421{
425 if (ndev->dr_hw == NUBUS_DRHW_ASANTE_LC && 422 if (ndev->dr_hw == NUBUS_DRHW_ASANTE_LC &&
426 ndev->dr_sw == NUBUS_DRSW_SONIC_LC) 423 ndev->dr_sw == NUBUS_DRSW_SONIC_LC)
@@ -445,7 +442,7 @@ int __init macsonic_ident(struct nubus_dev* ndev)
445 return -1; 442 return -1;
446} 443}
447 444
448int __init mac_nubus_sonic_probe(struct net_device* dev) 445static int __init mac_nubus_sonic_probe(struct net_device *dev)
449{ 446{
450 static int slots; 447 static int slots;
451 struct nubus_dev* ndev = NULL; 448 struct nubus_dev* ndev = NULL;
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
index 860d75d81f82..efbc15567dd3 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -189,12 +189,20 @@ static int macvlan_open(struct net_device *dev)
189 189
190 err = dev_unicast_add(lowerdev, dev->dev_addr, ETH_ALEN); 190 err = dev_unicast_add(lowerdev, dev->dev_addr, ETH_ALEN);
191 if (err < 0) 191 if (err < 0)
192 return err; 192 goto out;
193 if (dev->flags & IFF_ALLMULTI) 193 if (dev->flags & IFF_ALLMULTI) {
194 dev_set_allmulti(lowerdev, 1); 194 err = dev_set_allmulti(lowerdev, 1);
195 if (err < 0)
196 goto del_unicast;
197 }
195 198
196 hlist_add_head_rcu(&vlan->hlist, &port->vlan_hash[dev->dev_addr[5]]); 199 hlist_add_head_rcu(&vlan->hlist, &port->vlan_hash[dev->dev_addr[5]]);
197 return 0; 200 return 0;
201
202del_unicast:
203 dev_unicast_delete(lowerdev, dev->dev_addr, ETH_ALEN);
204out:
205 return err;
198} 206}
199 207
200static int macvlan_stop(struct net_device *dev) 208static int macvlan_stop(struct net_device *dev)
@@ -277,6 +285,19 @@ static struct lock_class_key macvlan_netdev_xmit_lock_key;
277#define MACVLAN_STATE_MASK \ 285#define MACVLAN_STATE_MASK \
278 ((1<<__LINK_STATE_NOCARRIER) | (1<<__LINK_STATE_DORMANT)) 286 ((1<<__LINK_STATE_NOCARRIER) | (1<<__LINK_STATE_DORMANT))
279 287
288static void macvlan_set_lockdep_class_one(struct net_device *dev,
289 struct netdev_queue *txq,
290 void *_unused)
291{
292 lockdep_set_class(&txq->_xmit_lock,
293 &macvlan_netdev_xmit_lock_key);
294}
295
296static void macvlan_set_lockdep_class(struct net_device *dev)
297{
298 netdev_for_each_tx_queue(dev, macvlan_set_lockdep_class_one, NULL);
299}
300
280static int macvlan_init(struct net_device *dev) 301static int macvlan_init(struct net_device *dev)
281{ 302{
282 struct macvlan_dev *vlan = netdev_priv(dev); 303 struct macvlan_dev *vlan = netdev_priv(dev);
@@ -287,7 +308,8 @@ static int macvlan_init(struct net_device *dev)
287 dev->features = lowerdev->features & MACVLAN_FEATURES; 308 dev->features = lowerdev->features & MACVLAN_FEATURES;
288 dev->iflink = lowerdev->ifindex; 309 dev->iflink = lowerdev->ifindex;
289 310
290 lockdep_set_class(&dev->_xmit_lock, &macvlan_netdev_xmit_lock_key); 311 macvlan_set_lockdep_class(dev);
312
291 return 0; 313 return 0;
292} 314}
293 315
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index b7915cdcc6a5..83a877f3a553 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -34,406 +34,145 @@
34 * along with this program; if not, write to the Free Software 34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */ 36 */
37
37#include <linux/init.h> 38#include <linux/init.h>
38#include <linux/dma-mapping.h> 39#include <linux/dma-mapping.h>
39#include <linux/in.h> 40#include <linux/in.h>
40#include <linux/ip.h>
41#include <linux/tcp.h> 41#include <linux/tcp.h>
42#include <linux/udp.h> 42#include <linux/udp.h>
43#include <linux/etherdevice.h> 43#include <linux/etherdevice.h>
44
45#include <linux/bitops.h>
46#include <linux/delay.h> 44#include <linux/delay.h>
47#include <linux/ethtool.h> 45#include <linux/ethtool.h>
48#include <linux/platform_device.h> 46#include <linux/platform_device.h>
49
50#include <linux/module.h> 47#include <linux/module.h>
51#include <linux/kernel.h> 48#include <linux/kernel.h>
52#include <linux/spinlock.h> 49#include <linux/spinlock.h>
53#include <linux/workqueue.h> 50#include <linux/workqueue.h>
54#include <linux/mii.h> 51#include <linux/mii.h>
55
56#include <linux/mv643xx_eth.h> 52#include <linux/mv643xx_eth.h>
57
58#include <asm/io.h> 53#include <asm/io.h>
59#include <asm/types.h> 54#include <asm/types.h>
60#include <asm/pgtable.h>
61#include <asm/system.h> 55#include <asm/system.h>
62#include <asm/delay.h>
63#include <asm/dma-mapping.h>
64 56
65#define MV643XX_CHECKSUM_OFFLOAD_TX 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
66#define MV643XX_NAPI 58static char mv643xx_eth_driver_version[] = "1.1";
67#define MV643XX_TX_FAST_REFILL
68#undef MV643XX_COAL
69 59
70#define MV643XX_TX_COAL 100 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
71#ifdef MV643XX_COAL 61#define MV643XX_ETH_NAPI
72#define MV643XX_RX_COAL 100 62#define MV643XX_ETH_TX_FAST_REFILL
73#endif
74 63
75#ifdef MV643XX_CHECKSUM_OFFLOAD_TX 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
76#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
77#else 66#else
78#define MAX_DESCS_PER_SKB 1 67#define MAX_DESCS_PER_SKB 1
79#endif 68#endif
80 69
81#define ETH_VLAN_HLEN 4
82#define ETH_FCS_LEN 4
83#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
84#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
85 ETH_VLAN_HLEN + ETH_FCS_LEN)
86#define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
87 dma_get_cache_alignment())
88
89/* 70/*
90 * Registers shared between all ports. 71 * Registers shared between all ports.
91 */ 72 */
92#define PHY_ADDR_REG 0x0000 73#define PHY_ADDR 0x0000
93#define SMI_REG 0x0004 74#define SMI_REG 0x0004
94#define WINDOW_BASE(i) (0x0200 + ((i) << 3)) 75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
95#define WINDOW_SIZE(i) (0x0204 + ((i) << 3)) 76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
96#define WINDOW_REMAP_HIGH(i) (0x0280 + ((i) << 2)) 77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
97#define WINDOW_BAR_ENABLE 0x0290 78#define WINDOW_BAR_ENABLE 0x0290
98#define WINDOW_PROTECT(i) (0x0294 + ((i) << 4)) 79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
99 80
100/* 81/*
101 * Per-port registers. 82 * Per-port registers.
102 */ 83 */
103#define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10)) 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
104#define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10)) 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
105#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
106#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) 87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
107#define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10)) 88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
108#define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10)) 89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
109#define PORT_STATUS_REG(p) (0x0444 + ((p) << 10)) 90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
110#define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10)) 91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
111#define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10)) 92#define TX_FIFO_EMPTY 0x00000400
112#define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10)) 93#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
113#define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10)) 94#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
114#define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10)) 95#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
115#define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10)) 96#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
116#define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10)) 97#define TX_BW_BURST(p) (0x045c + ((p) << 10))
117#define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10)) 98#define INT_CAUSE(p) (0x0460 + ((p) << 10))
118#define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10)) 99#define INT_TX_END 0x07f80000
119#define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10)) 100#define INT_RX 0x0007fbfc
120#define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7)) 101#define INT_EXT 0x00000002
121#define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10)) 102#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
122#define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10)) 103#define INT_EXT_LINK 0x00100000
123#define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10)) 104#define INT_EXT_PHY 0x00010000
124 105#define INT_EXT_TX_ERROR_0 0x00000100
125/* These macros describe Ethernet Port configuration reg (Px_cR) bits */ 106#define INT_EXT_TX_0 0x00000001
126#define UNICAST_NORMAL_MODE (0 << 0) 107#define INT_EXT_TX 0x0000ffff
127#define UNICAST_PROMISCUOUS_MODE (1 << 0) 108#define INT_MASK(p) (0x0468 + ((p) << 10))
128#define DEFAULT_RX_QUEUE(queue) ((queue) << 1) 109#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
129#define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4) 110#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
130#define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7) 111#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
131#define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) 112#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
132#define RECEIVE_BC_IF_IP (0 << 8) 113#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
133#define REJECT_BC_IF_IP (1 << 8) 114#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
134#define RECEIVE_BC_IF_ARP (0 << 9) 115#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
135#define REJECT_BC_IF_ARP (1 << 9) 116#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
136#define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12) 117#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
137#define CAPTURE_TCP_FRAMES_DIS (0 << 14) 118#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
138#define CAPTURE_TCP_FRAMES_EN (1 << 14) 119#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
139#define CAPTURE_UDP_FRAMES_DIS (0 << 15) 120#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
140#define CAPTURE_UDP_FRAMES_EN (1 << 15) 121#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
141#define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16) 122#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
142#define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19) 123#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
143#define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22) 124#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
144 125
145#define PORT_CONFIG_DEFAULT_VALUE \ 126
146 UNICAST_NORMAL_MODE | \ 127/*
147 DEFAULT_RX_QUEUE(0) | \ 128 * SDMA configuration register.
148 DEFAULT_RX_ARP_QUEUE(0) | \ 129 */
149 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
150 RECEIVE_BC_IF_IP | \
151 RECEIVE_BC_IF_ARP | \
152 CAPTURE_TCP_FRAMES_DIS | \
153 CAPTURE_UDP_FRAMES_DIS | \
154 DEFAULT_RX_TCP_QUEUE(0) | \
155 DEFAULT_RX_UDP_QUEUE(0) | \
156 DEFAULT_RX_BPDU_QUEUE(0)
157
158/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
159#define CLASSIFY_EN (1 << 0)
160#define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
161#define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
162#define PARTITION_DISABLE (0 << 2)
163#define PARTITION_ENABLE (1 << 2)
164
165#define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
166 SPAN_BPDU_PACKETS_AS_NORMAL | \
167 PARTITION_DISABLE
168
169/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
170#define RIFB (1 << 0)
171#define RX_BURST_SIZE_1_64BIT (0 << 1)
172#define RX_BURST_SIZE_2_64BIT (1 << 1)
173#define RX_BURST_SIZE_4_64BIT (2 << 1) 130#define RX_BURST_SIZE_4_64BIT (2 << 1)
174#define RX_BURST_SIZE_8_64BIT (3 << 1)
175#define RX_BURST_SIZE_16_64BIT (4 << 1)
176#define BLM_RX_NO_SWAP (1 << 4) 131#define BLM_RX_NO_SWAP (1 << 4)
177#define BLM_RX_BYTE_SWAP (0 << 4)
178#define BLM_TX_NO_SWAP (1 << 5) 132#define BLM_TX_NO_SWAP (1 << 5)
179#define BLM_TX_BYTE_SWAP (0 << 5)
180#define DESCRIPTORS_BYTE_SWAP (1 << 6)
181#define DESCRIPTORS_NO_SWAP (0 << 6)
182#define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
183#define TX_BURST_SIZE_1_64BIT (0 << 22)
184#define TX_BURST_SIZE_2_64BIT (1 << 22)
185#define TX_BURST_SIZE_4_64BIT (2 << 22) 133#define TX_BURST_SIZE_4_64BIT (2 << 22)
186#define TX_BURST_SIZE_8_64BIT (3 << 22)
187#define TX_BURST_SIZE_16_64BIT (4 << 22)
188 134
189#if defined(__BIG_ENDIAN) 135#if defined(__BIG_ENDIAN)
190#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 136#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
191 RX_BURST_SIZE_4_64BIT | \ 137 RX_BURST_SIZE_4_64BIT | \
192 IPG_INT_RX(0) | \
193 TX_BURST_SIZE_4_64BIT 138 TX_BURST_SIZE_4_64BIT
194#elif defined(__LITTLE_ENDIAN) 139#elif defined(__LITTLE_ENDIAN)
195#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 140#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
196 RX_BURST_SIZE_4_64BIT | \ 141 RX_BURST_SIZE_4_64BIT | \
197 BLM_RX_NO_SWAP | \ 142 BLM_RX_NO_SWAP | \
198 BLM_TX_NO_SWAP | \ 143 BLM_TX_NO_SWAP | \
199 IPG_INT_RX(0) | \
200 TX_BURST_SIZE_4_64BIT 144 TX_BURST_SIZE_4_64BIT
201#else 145#else
202#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 146#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
203#endif 147#endif
204 148
205/* These macros describe Ethernet Port serial control reg (PSCR) bits */ 149
206#define SERIAL_PORT_DISABLE (0 << 0) 150/*
207#define SERIAL_PORT_ENABLE (1 << 0) 151 * Port serial control register.
208#define DO_NOT_FORCE_LINK_PASS (0 << 1) 152 */
209#define FORCE_LINK_PASS (1 << 1) 153#define SET_MII_SPEED_TO_100 (1 << 24)
210#define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2) 154#define SET_GMII_SPEED_TO_1000 (1 << 23)
211#define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2) 155#define SET_FULL_DUPLEX_MODE (1 << 21)
212#define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
213#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
214#define ADV_NO_FLOW_CTRL (0 << 4)
215#define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
216#define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
217#define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
218#define FORCE_BP_MODE_NO_JAM (0 << 7)
219#define FORCE_BP_MODE_JAM_TX (1 << 7)
220#define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
221#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
222#define FORCE_LINK_FAIL (0 << 10)
223#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
224#define RETRANSMIT_16_ATTEMPTS (0 << 11)
225#define RETRANSMIT_FOREVER (1 << 11)
226#define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
227#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
228#define DTE_ADV_0 (0 << 14)
229#define DTE_ADV_1 (1 << 14)
230#define DISABLE_AUTO_NEG_BYPASS (0 << 15)
231#define ENABLE_AUTO_NEG_BYPASS (1 << 15)
232#define AUTO_NEG_NO_CHANGE (0 << 16)
233#define RESTART_AUTO_NEG (1 << 16)
234#define MAX_RX_PACKET_1518BYTE (0 << 17)
235#define MAX_RX_PACKET_1522BYTE (1 << 17) 156#define MAX_RX_PACKET_1522BYTE (1 << 17)
236#define MAX_RX_PACKET_1552BYTE (2 << 17)
237#define MAX_RX_PACKET_9022BYTE (3 << 17)
238#define MAX_RX_PACKET_9192BYTE (4 << 17)
239#define MAX_RX_PACKET_9700BYTE (5 << 17) 157#define MAX_RX_PACKET_9700BYTE (5 << 17)
240#define MAX_RX_PACKET_MASK (7 << 17) 158#define MAX_RX_PACKET_MASK (7 << 17)
241#define CLR_EXT_LOOPBACK (0 << 20) 159#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
242#define SET_EXT_LOOPBACK (1 << 20) 160#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
243#define SET_HALF_DUPLEX_MODE (0 << 21) 161#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
244#define SET_FULL_DUPLEX_MODE (1 << 21) 162#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
245#define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22) 163#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
246#define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) 164#define FORCE_LINK_PASS (1 << 1)
247#define SET_GMII_SPEED_TO_10_100 (0 << 23) 165#define SERIAL_PORT_ENABLE (1 << 0)
248#define SET_GMII_SPEED_TO_1000 (1 << 23)
249#define SET_MII_SPEED_TO_10 (0 << 24)
250#define SET_MII_SPEED_TO_100 (1 << 24)
251 166
252#define PORT_SERIAL_CONTROL_DEFAULT_VALUE \ 167#define DEFAULT_RX_QUEUE_SIZE 400
253 DO_NOT_FORCE_LINK_PASS | \ 168#define DEFAULT_TX_QUEUE_SIZE 800
254 ENABLE_AUTO_NEG_FOR_DUPLX | \ 169
255 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ 170
256 ADV_SYMMETRIC_FLOW_CTRL | \ 171/*
257 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 172 * RX/TX descriptors.
258 FORCE_BP_MODE_NO_JAM | \
259 (1 << 9) /* reserved */ | \
260 DO_NOT_FORCE_LINK_FAIL | \
261 RETRANSMIT_16_ATTEMPTS | \
262 ENABLE_AUTO_NEG_SPEED_GMII | \
263 DTE_ADV_0 | \
264 DISABLE_AUTO_NEG_BYPASS | \
265 AUTO_NEG_NO_CHANGE | \
266 MAX_RX_PACKET_9700BYTE | \
267 CLR_EXT_LOOPBACK | \
268 SET_FULL_DUPLEX_MODE | \
269 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
270
271/* These macros describe Ethernet Serial Status reg (PSR) bits */
272#define PORT_STATUS_MODE_10_BIT (1 << 0)
273#define PORT_STATUS_LINK_UP (1 << 1)
274#define PORT_STATUS_FULL_DUPLEX (1 << 2)
275#define PORT_STATUS_FLOW_CONTROL (1 << 3)
276#define PORT_STATUS_GMII_1000 (1 << 4)
277#define PORT_STATUS_MII_100 (1 << 5)
278/* PSR bit 6 is undocumented */
279#define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
280#define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
281#define PORT_STATUS_PARTITION (1 << 9)
282#define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
283/* PSR bits 11-31 are reserved */
284
285#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
286#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
287
288#define DESC_SIZE 64
289
290#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
291#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
292
293#define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
294#define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
295#define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
296#define ETH_INT_CAUSE_EXT 0x00000002
297#define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
298
299#define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
300#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
301#define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
302#define ETH_INT_CAUSE_PHY 0x00010000
303#define ETH_INT_CAUSE_STATE 0x00100000
304#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
305 ETH_INT_CAUSE_STATE)
306
307#define ETH_INT_MASK_ALL 0x00000000
308#define ETH_INT_MASK_ALL_EXT 0x00000000
309
310#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
311#define PHY_WAIT_MICRO_SECONDS 10
312
313/* Buffer offset from buffer pointer */
314#define RX_BUF_OFFSET 0x2
315
316/* Gigabit Ethernet Unit Global Registers */
317
318/* MIB Counters register definitions */
319#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
320#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
321#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
322#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
323#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
324#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
325#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
326#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
327#define ETH_MIB_FRAMES_64_OCTETS 0x20
328#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
329#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
330#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
331#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
332#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
333#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
334#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
335#define ETH_MIB_GOOD_FRAMES_SENT 0x40
336#define ETH_MIB_EXCESSIVE_COLLISION 0x44
337#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
338#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
339#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
340#define ETH_MIB_FC_SENT 0x54
341#define ETH_MIB_GOOD_FC_RECEIVED 0x58
342#define ETH_MIB_BAD_FC_RECEIVED 0x5c
343#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
344#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
345#define ETH_MIB_OVERSIZE_RECEIVED 0x68
346#define ETH_MIB_JABBER_RECEIVED 0x6c
347#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
348#define ETH_MIB_BAD_CRC_EVENT 0x74
349#define ETH_MIB_COLLISION 0x78
350#define ETH_MIB_LATE_COLLISION 0x7c
351
352/* Port serial status reg (PSR) */
353#define ETH_INTERFACE_PCM 0x00000001
354#define ETH_LINK_IS_UP 0x00000002
355#define ETH_PORT_AT_FULL_DUPLEX 0x00000004
356#define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
357#define ETH_GMII_SPEED_1000 0x00000010
358#define ETH_MII_SPEED_100 0x00000020
359#define ETH_TX_IN_PROGRESS 0x00000080
360#define ETH_BYPASS_ACTIVE 0x00000100
361#define ETH_PORT_AT_PARTITION_STATE 0x00000200
362#define ETH_PORT_TX_FIFO_EMPTY 0x00000400
363
364/* SMI reg */
365#define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
366#define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
367#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
368#define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
369
370/* Interrupt Cause Register Bit Definitions */
371
372/* SDMA command status fields macros */
373
374/* Tx & Rx descriptors status */
375#define ETH_ERROR_SUMMARY 0x00000001
376
377/* Tx & Rx descriptors command */
378#define ETH_BUFFER_OWNED_BY_DMA 0x80000000
379
380/* Tx descriptors status */
381#define ETH_LC_ERROR 0
382#define ETH_UR_ERROR 0x00000002
383#define ETH_RL_ERROR 0x00000004
384#define ETH_LLC_SNAP_FORMAT 0x00000200
385
386/* Rx descriptors status */
387#define ETH_OVERRUN_ERROR 0x00000002
388#define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
389#define ETH_RESOURCE_ERROR 0x00000006
390#define ETH_VLAN_TAGGED 0x00080000
391#define ETH_BPDU_FRAME 0x00100000
392#define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
393#define ETH_OTHER_FRAME_TYPE 0x00400000
394#define ETH_LAYER_2_IS_ETH_V_2 0x00800000
395#define ETH_FRAME_TYPE_IP_V_4 0x01000000
396#define ETH_FRAME_HEADER_OK 0x02000000
397#define ETH_RX_LAST_DESC 0x04000000
398#define ETH_RX_FIRST_DESC 0x08000000
399#define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
400#define ETH_RX_ENABLE_INTERRUPT 0x20000000
401#define ETH_LAYER_4_CHECKSUM_OK 0x40000000
402
403/* Rx descriptors byte count */
404#define ETH_FRAME_FRAGMENTED 0x00000004
405
406/* Tx descriptors command */
407#define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
408#define ETH_FRAME_SET_TO_VLAN 0x00008000
409#define ETH_UDP_FRAME 0x00010000
410#define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
411#define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
412#define ETH_ZERO_PADDING 0x00080000
413#define ETH_TX_LAST_DESC 0x00100000
414#define ETH_TX_FIRST_DESC 0x00200000
415#define ETH_GEN_CRC 0x00400000
416#define ETH_TX_ENABLE_INTERRUPT 0x00800000
417#define ETH_AUTO_MODE 0x40000000
418
419#define ETH_TX_IHL_SHIFT 11
420
421/* typedefs */
422
423typedef enum _eth_func_ret_status {
424 ETH_OK, /* Returned as expected. */
425 ETH_ERROR, /* Fundamental error. */
426 ETH_RETRY, /* Could not process request. Try later.*/
427 ETH_END_OF_JOB, /* Ring has nothing to process. */
428 ETH_QUEUE_FULL, /* Ring resource error. */
429 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
430} ETH_FUNC_RET_STATUS;
431
432/* These are for big-endian machines. Little endian needs different
433 * definitions.
434 */ 173 */
435#if defined(__BIG_ENDIAN) 174#if defined(__BIG_ENDIAN)
436struct eth_rx_desc { 175struct rx_desc {
437 u16 byte_cnt; /* Descriptor buffer byte count */ 176 u16 byte_cnt; /* Descriptor buffer byte count */
438 u16 buf_size; /* Buffer size */ 177 u16 buf_size; /* Buffer size */
439 u32 cmd_sts; /* Descriptor command status */ 178 u32 cmd_sts; /* Descriptor command status */
@@ -441,7 +180,7 @@ struct eth_rx_desc {
441 u32 buf_ptr; /* Descriptor buffer pointer */ 180 u32 buf_ptr; /* Descriptor buffer pointer */
442}; 181};
443 182
444struct eth_tx_desc { 183struct tx_desc {
445 u16 byte_cnt; /* buffer byte count */ 184 u16 byte_cnt; /* buffer byte count */
446 u16 l4i_chk; /* CPU provided TCP checksum */ 185 u16 l4i_chk; /* CPU provided TCP checksum */
447 u32 cmd_sts; /* Command/status field */ 186 u32 cmd_sts; /* Command/status field */
@@ -449,7 +188,7 @@ struct eth_tx_desc {
449 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 188 u32 buf_ptr; /* pointer to buffer for this descriptor*/
450}; 189};
451#elif defined(__LITTLE_ENDIAN) 190#elif defined(__LITTLE_ENDIAN)
452struct eth_rx_desc { 191struct rx_desc {
453 u32 cmd_sts; /* Descriptor command status */ 192 u32 cmd_sts; /* Descriptor command status */
454 u16 buf_size; /* Buffer size */ 193 u16 buf_size; /* Buffer size */
455 u16 byte_cnt; /* Descriptor buffer byte count */ 194 u16 byte_cnt; /* Descriptor buffer byte count */
@@ -457,7 +196,7 @@ struct eth_rx_desc {
457 u32 next_desc_ptr; /* Next descriptor pointer */ 196 u32 next_desc_ptr; /* Next descriptor pointer */
458}; 197};
459 198
460struct eth_tx_desc { 199struct tx_desc {
461 u32 cmd_sts; /* Command/status field */ 200 u32 cmd_sts; /* Command/status field */
462 u16 l4i_chk; /* CPU provided TCP checksum */ 201 u16 l4i_chk; /* CPU provided TCP checksum */
463 u16 byte_cnt; /* buffer byte count */ 202 u16 byte_cnt; /* buffer byte count */
@@ -468,18 +207,59 @@ struct eth_tx_desc {
468#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 207#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
469#endif 208#endif
470 209
471/* Unified struct for Rx and Tx operations. The user is not required to */ 210/* RX & TX descriptor command */
472/* be familier with neither Tx nor Rx descriptors. */ 211#define BUFFER_OWNED_BY_DMA 0x80000000
473struct pkt_info { 212
474 unsigned short byte_cnt; /* Descriptor buffer byte count */ 213/* RX & TX descriptor status */
475 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ 214#define ERROR_SUMMARY 0x00000001
476 unsigned int cmd_sts; /* Descriptor command status */ 215
477 dma_addr_t buf_ptr; /* Descriptor buffer pointer */ 216/* RX descriptor status */
478 struct sk_buff *return_info; /* User resource return information */ 217#define LAYER_4_CHECKSUM_OK 0x40000000
218#define RX_ENABLE_INTERRUPT 0x20000000
219#define RX_FIRST_DESC 0x08000000
220#define RX_LAST_DESC 0x04000000
221
222/* TX descriptor command */
223#define TX_ENABLE_INTERRUPT 0x00800000
224#define GEN_CRC 0x00400000
225#define TX_FIRST_DESC 0x00200000
226#define TX_LAST_DESC 0x00100000
227#define ZERO_PADDING 0x00080000
228#define GEN_IP_V4_CHECKSUM 0x00040000
229#define GEN_TCP_UDP_CHECKSUM 0x00020000
230#define UDP_FRAME 0x00010000
231
232#define TX_IHL_SHIFT 11
233
234
235/* global *******************************************************************/
236struct mv643xx_eth_shared_private {
237 /*
238 * Ethernet controller base address.
239 */
240 void __iomem *base;
241
242 /*
243 * Protects access to SMI_REG, which is shared between ports.
244 */
245 spinlock_t phy_lock;
246
247 /*
248 * Per-port MBUS window access register value.
249 */
250 u32 win_protect;
251
252 /*
253 * Hardware-specific parameters.
254 */
255 unsigned int t_clk;
256 int extended_rx_coal_limit;
257 int tx_bw_control_moved;
479}; 258};
480 259
481/* Ethernet port specific information */ 260
482struct mv643xx_mib_counters { 261/* per-port *****************************************************************/
262struct mib_counters {
483 u64 good_octets_received; 263 u64 good_octets_received;
484 u32 bad_octets_received; 264 u32 bad_octets_received;
485 u32 internal_mac_transmit_err; 265 u32 internal_mac_transmit_err;
@@ -512,461 +292,282 @@ struct mv643xx_mib_counters {
512 u32 late_collision; 292 u32 late_collision;
513}; 293};
514 294
515struct mv643xx_shared_private { 295struct rx_queue {
516 void __iomem *eth_base; 296 int index;
517
518 /* used to protect SMI_REG, which is shared across ports */
519 spinlock_t phy_lock;
520 297
521 u32 win_protect; 298 int rx_ring_size;
522
523 unsigned int t_clk;
524};
525
526struct mv643xx_private {
527 struct mv643xx_shared_private *shared;
528 int port_num; /* User Ethernet port number */
529
530 struct mv643xx_shared_private *shared_smi;
531
532 u32 rx_sram_addr; /* Base address of rx sram area */
533 u32 rx_sram_size; /* Size of rx sram area */
534 u32 tx_sram_addr; /* Base address of tx sram area */
535 u32 tx_sram_size; /* Size of tx sram area */
536 299
537 int rx_resource_err; /* Rx ring resource error flag */ 300 int rx_desc_count;
301 int rx_curr_desc;
302 int rx_used_desc;
538 303
539 /* Tx/Rx rings managment indexes fields. For driver use */ 304 struct rx_desc *rx_desc_area;
305 dma_addr_t rx_desc_dma;
306 int rx_desc_area_size;
307 struct sk_buff **rx_skb;
540 308
541 /* Next available and first returning Rx resource */ 309 struct timer_list rx_oom;
542 int rx_curr_desc_q, rx_used_desc_q; 310};
543 311
544 /* Next available and first returning Tx resource */ 312struct tx_queue {
545 int tx_curr_desc_q, tx_used_desc_q; 313 int index;
546 314
547#ifdef MV643XX_TX_FAST_REFILL 315 int tx_ring_size;
548 u32 tx_clean_threshold;
549#endif
550 316
551 struct eth_rx_desc *p_rx_desc_area; 317 int tx_desc_count;
552 dma_addr_t rx_desc_dma; 318 int tx_curr_desc;
553 int rx_desc_area_size; 319 int tx_used_desc;
554 struct sk_buff **rx_skb;
555 320
556 struct eth_tx_desc *p_tx_desc_area; 321 struct tx_desc *tx_desc_area;
557 dma_addr_t tx_desc_dma; 322 dma_addr_t tx_desc_dma;
558 int tx_desc_area_size; 323 int tx_desc_area_size;
559 struct sk_buff **tx_skb; 324 struct sk_buff **tx_skb;
325};
560 326
561 struct work_struct tx_timeout_task; 327struct mv643xx_eth_private {
328 struct mv643xx_eth_shared_private *shared;
329 int port_num;
562 330
563 struct net_device *dev; 331 struct net_device *dev;
564 struct napi_struct napi; 332
565 struct net_device_stats stats; 333 struct mv643xx_eth_shared_private *shared_smi;
566 struct mv643xx_mib_counters mib_counters; 334 int phy_addr;
335
567 spinlock_t lock; 336 spinlock_t lock;
568 /* Size of Tx Ring per queue */ 337
569 int tx_ring_size; 338 struct mib_counters mib_counters;
570 /* Number of tx descriptors in use */ 339 struct work_struct tx_timeout_task;
571 int tx_desc_count; 340 struct mii_if_info mii;
572 /* Size of Rx Ring per queue */
573 int rx_ring_size;
574 /* Number of rx descriptors in use */
575 int rx_desc_count;
576 341
577 /* 342 /*
578 * Used in case RX Ring is empty, which can be caused when 343 * RX state.
579 * system does not have resources (skb's)
580 */ 344 */
581 struct timer_list timeout; 345 int default_rx_ring_size;
582 346 unsigned long rx_desc_sram_addr;
583 u32 rx_int_coal; 347 int rx_desc_sram_size;
584 u32 tx_int_coal; 348 u8 rxq_mask;
585 struct mii_if_info mii; 349 int rxq_primary;
586}; 350 struct napi_struct napi;
351 struct rx_queue rxq[8];
587 352
588/* Static function declarations */ 353 /*
589static void eth_port_init(struct mv643xx_private *mp); 354 * TX state.
590static void eth_port_reset(struct mv643xx_private *mp); 355 */
591static void eth_port_start(struct net_device *dev); 356 int default_tx_ring_size;
592 357 unsigned long tx_desc_sram_addr;
593static void ethernet_phy_reset(struct mv643xx_private *mp); 358 int tx_desc_sram_size;
594 359 u8 txq_mask;
595static void eth_port_write_smi_reg(struct mv643xx_private *mp, 360 int txq_primary;
596 unsigned int phy_reg, unsigned int value); 361 struct tx_queue txq[8];
597 362#ifdef MV643XX_ETH_TX_FAST_REFILL
598static void eth_port_read_smi_reg(struct mv643xx_private *mp, 363 int tx_clean_threshold;
599 unsigned int phy_reg, unsigned int *value);
600
601static void eth_clear_mib_counters(struct mv643xx_private *mp);
602
603static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
604 struct pkt_info *p_pkt_info);
605static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
606 struct pkt_info *p_pkt_info);
607
608static void eth_port_uc_addr_get(struct mv643xx_private *mp,
609 unsigned char *p_addr);
610static void eth_port_uc_addr_set(struct mv643xx_private *mp,
611 unsigned char *p_addr);
612static void eth_port_set_multicast_list(struct net_device *);
613static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
614 unsigned int queues);
615static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
616 unsigned int queues);
617static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp);
618static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp);
619static int mv643xx_eth_open(struct net_device *);
620static int mv643xx_eth_stop(struct net_device *);
621static void eth_port_init_mac_tables(struct mv643xx_private *mp);
622#ifdef MV643XX_NAPI
623static int mv643xx_poll(struct napi_struct *napi, int budget);
624#endif 364#endif
625static int ethernet_phy_get(struct mv643xx_private *mp); 365};
626static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr);
627static int ethernet_phy_detect(struct mv643xx_private *mp);
628static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
629static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
630static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
631static const struct ethtool_ops mv643xx_ethtool_ops;
632 366
633static char mv643xx_driver_name[] = "mv643xx_eth";
634static char mv643xx_driver_version[] = "1.0";
635 367
636static inline u32 rdl(struct mv643xx_private *mp, int offset) 368/* port register accessors **************************************************/
369static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
637{ 370{
638 return readl(mp->shared->eth_base + offset); 371 return readl(mp->shared->base + offset);
639} 372}
640 373
641static inline void wrl(struct mv643xx_private *mp, int offset, u32 data) 374static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
642{ 375{
643 writel(data, mp->shared->eth_base + offset); 376 writel(data, mp->shared->base + offset);
644} 377}
645 378
646/*
647 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
648 *
649 * Input : pointer to ethernet interface network device structure
650 * new mtu size
651 * Output : 0 upon success, -EINVAL upon failure
652 */
653static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
654{
655 if ((new_mtu > 9500) || (new_mtu < 64))
656 return -EINVAL;
657 379
658 dev->mtu = new_mtu; 380/* rxq/txq helper functions *************************************************/
659 if (!netif_running(dev)) 381static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
660 return 0;
661
662 /*
663 * Stop and then re-open the interface. This will allocate RX
664 * skbs of the new MTU.
665 * There is a possible danger that the open will not succeed,
666 * due to memory being full, which might fail the open function.
667 */
668 mv643xx_eth_stop(dev);
669 if (mv643xx_eth_open(dev)) {
670 printk(KERN_ERR "%s: Fatal error on opening device\n",
671 dev->name);
672 }
673
674 return 0;
675}
676
677/*
678 * mv643xx_eth_rx_refill_descs
679 *
680 * Fills / refills RX queue on a certain gigabit ethernet port
681 *
682 * Input : pointer to ethernet interface network device structure
683 * Output : N/A
684 */
685static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
686{ 382{
687 struct mv643xx_private *mp = netdev_priv(dev); 383 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
688 struct pkt_info pkt_info;
689 struct sk_buff *skb;
690 int unaligned;
691
692 while (mp->rx_desc_count < mp->rx_ring_size) {
693 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
694 if (!skb)
695 break;
696 mp->rx_desc_count++;
697 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
698 if (unaligned)
699 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
700 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
701 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
702 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
703 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
704 pkt_info.return_info = skb;
705 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
706 printk(KERN_ERR
707 "%s: Error allocating RX Ring\n", dev->name);
708 break;
709 }
710 skb_reserve(skb, ETH_HW_IP_ALIGN);
711 }
712 /*
713 * If RX ring is empty of SKB, set a timer to try allocating
714 * again at a later time.
715 */
716 if (mp->rx_desc_count == 0) {
717 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
718 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
719 add_timer(&mp->timeout);
720 }
721} 384}
722 385
723/* 386static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
724 * mv643xx_eth_rx_refill_descs_timer_wrapper
725 *
726 * Timer routine to wake up RX queue filling task. This function is
727 * used only in case the RX queue is empty, and all alloc_skb has
728 * failed (due to out of memory event).
729 *
730 * Input : pointer to ethernet interface network device structure
731 * Output : N/A
732 */
733static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
734{ 387{
735 mv643xx_eth_rx_refill_descs((struct net_device *)data); 388 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
736} 389}
737 390
738/* 391static void rxq_enable(struct rx_queue *rxq)
739 * mv643xx_eth_update_mac_address
740 *
741 * Update the MAC address of the port in the address table
742 *
743 * Input : pointer to ethernet interface network device structure
744 * Output : N/A
745 */
746static void mv643xx_eth_update_mac_address(struct net_device *dev)
747{ 392{
748 struct mv643xx_private *mp = netdev_priv(dev); 393 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
749 394 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
750 eth_port_init_mac_tables(mp);
751 eth_port_uc_addr_set(mp, dev->dev_addr);
752} 395}
753 396
754/* 397static void rxq_disable(struct rx_queue *rxq)
755 * mv643xx_eth_set_rx_mode
756 *
757 * Change from promiscuos to regular rx mode
758 *
759 * Input : pointer to ethernet interface network device structure
760 * Output : N/A
761 */
762static void mv643xx_eth_set_rx_mode(struct net_device *dev)
763{ 398{
764 struct mv643xx_private *mp = netdev_priv(dev); 399 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
765 u32 config_reg; 400 u8 mask = 1 << rxq->index;
766 401
767 config_reg = rdl(mp, PORT_CONFIG_REG(mp->port_num)); 402 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
768 if (dev->flags & IFF_PROMISC) 403 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
769 config_reg |= (u32) UNICAST_PROMISCUOUS_MODE; 404 udelay(10);
770 else
771 config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE;
772 wrl(mp, PORT_CONFIG_REG(mp->port_num), config_reg);
773
774 eth_port_set_multicast_list(dev);
775} 405}
776 406
777/* 407static void txq_enable(struct tx_queue *txq)
778 * mv643xx_eth_set_mac_address
779 *
780 * Change the interface's mac address.
781 * No special hardware thing should be done because interface is always
782 * put in promiscuous mode.
783 *
784 * Input : pointer to ethernet interface network device structure and
785 * a pointer to the designated entry to be added to the cache.
786 * Output : zero upon success, negative upon failure
787 */
788static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
789{ 408{
790 int i; 409 struct mv643xx_eth_private *mp = txq_to_mp(txq);
791 410 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
792 for (i = 0; i < 6; i++)
793 /* +2 is for the offset of the HW addr type */
794 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
795 mv643xx_eth_update_mac_address(dev);
796 return 0;
797} 411}
798 412
799/* 413static void txq_disable(struct tx_queue *txq)
800 * mv643xx_eth_tx_timeout
801 *
802 * Called upon a timeout on transmitting a packet
803 *
804 * Input : pointer to ethernet interface network device structure.
805 * Output : N/A
806 */
807static void mv643xx_eth_tx_timeout(struct net_device *dev)
808{ 414{
809 struct mv643xx_private *mp = netdev_priv(dev); 415 struct mv643xx_eth_private *mp = txq_to_mp(txq);
810 416 u8 mask = 1 << txq->index;
811 printk(KERN_INFO "%s: TX timeout ", dev->name);
812 417
813 /* Do the reset outside of interrupt context */ 418 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
814 schedule_work(&mp->tx_timeout_task); 419 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
420 udelay(10);
815} 421}
816 422
817/* 423static void __txq_maybe_wake(struct tx_queue *txq)
818 * mv643xx_eth_tx_timeout_task
819 *
820 * Actual routine to reset the adapter when a timeout on Tx has occurred
821 */
822static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
823{ 424{
824 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, 425 struct mv643xx_eth_private *mp = txq_to_mp(txq);
825 tx_timeout_task);
826 struct net_device *dev = mp->dev;
827 426
828 if (!netif_running(dev)) 427 /*
829 return; 428 * netif_{stop,wake}_queue() flow control only applies to
429 * the primary queue.
430 */
431 BUG_ON(txq->index != mp->txq_primary);
830 432
831 netif_stop_queue(dev); 433 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
434 netif_wake_queue(mp->dev);
435}
832 436
833 eth_port_reset(mp);
834 eth_port_start(dev);
835 437
836 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) 438/* rx ***********************************************************************/
837 netif_wake_queue(dev); 439static void txq_reclaim(struct tx_queue *txq, int force);
838}
839 440
840/** 441static void rxq_refill(struct rx_queue *rxq)
841 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
842 *
843 * If force is non-zero, frees uncompleted descriptors as well
844 */
845static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
846{ 442{
847 struct mv643xx_private *mp = netdev_priv(dev); 443 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
848 struct eth_tx_desc *desc;
849 u32 cmd_sts;
850 struct sk_buff *skb;
851 unsigned long flags; 444 unsigned long flags;
852 int tx_index;
853 dma_addr_t addr;
854 int count;
855 int released = 0;
856 445
857 while (mp->tx_desc_count > 0) { 446 spin_lock_irqsave(&mp->lock, flags);
858 spin_lock_irqsave(&mp->lock, flags);
859
860 /* tx_desc_count might have changed before acquiring the lock */
861 if (mp->tx_desc_count <= 0) {
862 spin_unlock_irqrestore(&mp->lock, flags);
863 return released;
864 }
865
866 tx_index = mp->tx_used_desc_q;
867 desc = &mp->p_tx_desc_area[tx_index];
868 cmd_sts = desc->cmd_sts;
869 447
870 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { 448 while (rxq->rx_desc_count < rxq->rx_ring_size) {
871 spin_unlock_irqrestore(&mp->lock, flags); 449 int skb_size;
872 return released; 450 struct sk_buff *skb;
873 } 451 int unaligned;
452 int rx;
874 453
875 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; 454 /*
876 mp->tx_desc_count--; 455 * Reserve 2+14 bytes for an ethernet header (the
456 * hardware automatically prepends 2 bytes of dummy
457 * data to each received packet), 4 bytes for a VLAN
458 * header, and 4 bytes for the trailing FCS -- 24
459 * bytes total.
460 */
461 skb_size = mp->dev->mtu + 24;
877 462
878 addr = desc->buf_ptr; 463 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
879 count = desc->byte_cnt; 464 if (skb == NULL)
880 skb = mp->tx_skb[tx_index]; 465 break;
881 if (skb)
882 mp->tx_skb[tx_index] = NULL;
883 466
884 if (cmd_sts & ETH_ERROR_SUMMARY) { 467 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
885 printk("%s: Error in TX\n", dev->name); 468 if (unaligned)
886 dev->stats.tx_errors++; 469 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
887 }
888 470
889 spin_unlock_irqrestore(&mp->lock, flags); 471 rxq->rx_desc_count++;
472 rx = rxq->rx_used_desc;
473 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
890 474
891 if (cmd_sts & ETH_TX_FIRST_DESC) 475 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
892 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); 476 skb_size, DMA_FROM_DEVICE);
893 else 477 rxq->rx_desc_area[rx].buf_size = skb_size;
894 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); 478 rxq->rx_skb[rx] = skb;
479 wmb();
480 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
481 RX_ENABLE_INTERRUPT;
482 wmb();
895 483
896 if (skb) 484 /*
897 dev_kfree_skb_irq(skb); 485 * The hardware automatically prepends 2 bytes of
486 * dummy data to each received packet, so that the
487 * IP header ends up 16-byte aligned.
488 */
489 skb_reserve(skb, 2);
490 }
898 491
899 released = 1; 492 if (rxq->rx_desc_count != rxq->rx_ring_size) {
493 rxq->rx_oom.expires = jiffies + (HZ / 10);
494 add_timer(&rxq->rx_oom);
900 } 495 }
901 496
902 return released; 497 spin_unlock_irqrestore(&mp->lock, flags);
903} 498}
904 499
905static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) 500static inline void rxq_refill_timer_wrapper(unsigned long data)
906{ 501{
907 struct mv643xx_private *mp = netdev_priv(dev); 502 rxq_refill((struct rx_queue *)data);
908
909 if (mv643xx_eth_free_tx_descs(dev, 0) &&
910 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
911 netif_wake_queue(dev);
912} 503}
913 504
914static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) 505static int rxq_process(struct rx_queue *rxq, int budget)
915{ 506{
916 mv643xx_eth_free_tx_descs(dev, 1); 507 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
917} 508 struct net_device_stats *stats = &mp->dev->stats;
509 int rx;
918 510
919/* 511 rx = 0;
920 * mv643xx_eth_receive 512 while (rx < budget) {
921 * 513 struct rx_desc *rx_desc;
922 * This function is forward packets that are received from the port's 514 unsigned int cmd_sts;
923 * queues toward kernel core or FastRoute them to another interface. 515 struct sk_buff *skb;
924 * 516 unsigned long flags;
925 * Input : dev - a pointer to the required interface 517
926 * max - maximum number to receive (0 means unlimted) 518 spin_lock_irqsave(&mp->lock, flags);
927 * 519
928 * Output : number of served packets 520 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
929 */ 521
930static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) 522 cmd_sts = rx_desc->cmd_sts;
931{ 523 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
932 struct mv643xx_private *mp = netdev_priv(dev); 524 spin_unlock_irqrestore(&mp->lock, flags);
933 struct net_device_stats *stats = &dev->stats; 525 break;
934 unsigned int received_packets = 0; 526 }
935 struct sk_buff *skb; 527 rmb();
936 struct pkt_info pkt_info; 528
529 skb = rxq->rx_skb[rxq->rx_curr_desc];
530 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
937 531
938 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { 532 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
939 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, 533
940 DMA_FROM_DEVICE); 534 spin_unlock_irqrestore(&mp->lock, flags);
941 mp->rx_desc_count--; 535
942 received_packets++; 536 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
537 mp->dev->mtu + 24, DMA_FROM_DEVICE);
538 rxq->rx_desc_count--;
539 rx++;
943 540
944 /* 541 /*
945 * Update statistics. 542 * Update statistics.
946 * Note byte count includes 4 byte CRC count 543 *
544 * Note that the descriptor byte count includes 2 dummy
545 * bytes automatically inserted by the hardware at the
546 * start of the packet (which we don't count), and a 4
547 * byte CRC at the end of the packet (which we do count).
947 */ 548 */
948 stats->rx_packets++; 549 stats->rx_packets++;
949 stats->rx_bytes += pkt_info.byte_cnt; 550 stats->rx_bytes += rx_desc->byte_cnt - 2;
950 skb = pkt_info.return_info; 551
951 /* 552 /*
952 * In case received a packet without first / last bits on OR 553 * In case we received a packet without first / last bits
953 * the error summary bit is on, the packets needs to be dropeed. 554 * on, or the error summary bit is set, the packet needs
555 * to be dropped.
954 */ 556 */
955 if (((pkt_info.cmd_sts 557 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
956 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != 558 (RX_FIRST_DESC | RX_LAST_DESC))
957 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) 559 || (cmd_sts & ERROR_SUMMARY)) {
958 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
959 stats->rx_dropped++; 560 stats->rx_dropped++;
960 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | 561
961 ETH_RX_LAST_DESC)) != 562 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
962 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { 563 (RX_FIRST_DESC | RX_LAST_DESC)) {
963 if (net_ratelimit()) 564 if (net_ratelimit())
964 printk(KERN_ERR 565 dev_printk(KERN_ERR, &mp->dev->dev,
965 "%s: Received packet spread " 566 "received packet spanning "
966 "on multiple descriptors\n", 567 "multiple descriptors\n");
967 dev->name);
968 } 568 }
969 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) 569
570 if (cmd_sts & ERROR_SUMMARY)
970 stats->rx_errors++; 571 stats->rx_errors++;
971 572
972 dev_kfree_skb_irq(skb); 573 dev_kfree_skb_irq(skb);
@@ -975,2391 +576,2003 @@ static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
975 * The -4 is for the CRC in the trailer of the 576 * The -4 is for the CRC in the trailer of the
976 * received packet 577 * received packet
977 */ 578 */
978 skb_put(skb, pkt_info.byte_cnt - 4); 579 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
979 580
980 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { 581 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
981 skb->ip_summed = CHECKSUM_UNNECESSARY; 582 skb->ip_summed = CHECKSUM_UNNECESSARY;
982 skb->csum = htons( 583 skb->csum = htons(
983 (pkt_info.cmd_sts & 0x0007fff8) >> 3); 584 (cmd_sts & 0x0007fff8) >> 3);
984 } 585 }
985 skb->protocol = eth_type_trans(skb, dev); 586 skb->protocol = eth_type_trans(skb, mp->dev);
986#ifdef MV643XX_NAPI 587#ifdef MV643XX_ETH_NAPI
987 netif_receive_skb(skb); 588 netif_receive_skb(skb);
988#else 589#else
989 netif_rx(skb); 590 netif_rx(skb);
990#endif 591#endif
991 } 592 }
992 dev->last_rx = jiffies; 593
594 mp->dev->last_rx = jiffies;
993 } 595 }
994 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
995 596
996 return received_packets; 597 rxq_refill(rxq);
598
599 return rx;
997} 600}
998 601
999/* Set the mv643xx port configuration register for the speed/duplex mode. */ 602#ifdef MV643XX_ETH_NAPI
1000static void mv643xx_eth_update_pscr(struct net_device *dev, 603static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1001 struct ethtool_cmd *ecmd)
1002{ 604{
1003 struct mv643xx_private *mp = netdev_priv(dev); 605 struct mv643xx_eth_private *mp;
1004 int port_num = mp->port_num; 606 int rx;
1005 u32 o_pscr, n_pscr; 607 int i;
1006 unsigned int queues;
1007 608
1008 o_pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); 609 mp = container_of(napi, struct mv643xx_eth_private, napi);
1009 n_pscr = o_pscr;
1010 610
1011 /* clear speed, duplex and rx buffer size fields */ 611#ifdef MV643XX_ETH_TX_FAST_REFILL
1012 n_pscr &= ~(SET_MII_SPEED_TO_100 | 612 if (++mp->tx_clean_threshold > 5) {
1013 SET_GMII_SPEED_TO_1000 | 613 mp->tx_clean_threshold = 0;
1014 SET_FULL_DUPLEX_MODE | 614 for (i = 0; i < 8; i++)
1015 MAX_RX_PACKET_MASK); 615 if (mp->txq_mask & (1 << i))
1016 616 txq_reclaim(mp->txq + i, 0);
1017 if (ecmd->duplex == DUPLEX_FULL)
1018 n_pscr |= SET_FULL_DUPLEX_MODE;
1019
1020 if (ecmd->speed == SPEED_1000)
1021 n_pscr |= SET_GMII_SPEED_TO_1000 |
1022 MAX_RX_PACKET_9700BYTE;
1023 else {
1024 if (ecmd->speed == SPEED_100)
1025 n_pscr |= SET_MII_SPEED_TO_100;
1026 n_pscr |= MAX_RX_PACKET_1522BYTE;
1027 } 617 }
618#endif
1028 619
1029 if (n_pscr != o_pscr) { 620 rx = 0;
1030 if ((o_pscr & SERIAL_PORT_ENABLE) == 0) 621 for (i = 7; rx < budget && i >= 0; i--)
1031 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 622 if (mp->rxq_mask & (1 << i))
1032 else { 623 rx += rxq_process(mp->rxq + i, budget - rx);
1033 queues = mv643xx_eth_port_disable_tx(mp); 624
1034 625 if (rx < budget) {
1035 o_pscr &= ~SERIAL_PORT_ENABLE; 626 netif_rx_complete(mp->dev, napi);
1036 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), o_pscr); 627 wrl(mp, INT_CAUSE(mp->port_num), 0);
1037 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 628 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1038 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 629 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1039 if (queues)
1040 mv643xx_eth_port_enable_tx(mp, queues);
1041 }
1042 } 630 }
631
632 return rx;
1043} 633}
634#endif
1044 635
1045/*
1046 * mv643xx_eth_int_handler
1047 *
1048 * Main interrupt handler for the gigbit ethernet ports
1049 *
1050 * Input : irq - irq number (not used)
1051 * dev_id - a pointer to the required interface's data structure
1052 * regs - not used
1053 * Output : N/A
1054 */
1055 636
1056static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) 637/* tx ***********************************************************************/
638static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1057{ 639{
1058 struct net_device *dev = (struct net_device *)dev_id; 640 int frag;
1059 struct mv643xx_private *mp = netdev_priv(dev);
1060 u32 eth_int_cause, eth_int_cause_ext = 0;
1061 unsigned int port_num = mp->port_num;
1062
1063 /* Read interrupt cause registers */
1064 eth_int_cause = rdl(mp, INTERRUPT_CAUSE_REG(port_num)) &
1065 ETH_INT_UNMASK_ALL;
1066 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1067 eth_int_cause_ext = rdl(mp,
1068 INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
1069 ETH_INT_UNMASK_ALL_EXT;
1070 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num),
1071 ~eth_int_cause_ext);
1072 }
1073
1074 /* PHY status changed */
1075 if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
1076 struct ethtool_cmd cmd;
1077 641
1078 if (mii_link_ok(&mp->mii)) { 642 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1079 mii_ethtool_gset(&mp->mii, &cmd); 643 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
1080 mv643xx_eth_update_pscr(dev, &cmd); 644 if (fragp->size <= 8 && fragp->page_offset & 7)
1081 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); 645 return 1;
1082 if (!netif_carrier_ok(dev)) {
1083 netif_carrier_on(dev);
1084 if (mp->tx_ring_size - mp->tx_desc_count >=
1085 MAX_DESCS_PER_SKB)
1086 netif_wake_queue(dev);
1087 }
1088 } else if (netif_carrier_ok(dev)) {
1089 netif_stop_queue(dev);
1090 netif_carrier_off(dev);
1091 }
1092 } 646 }
1093 647
1094#ifdef MV643XX_NAPI 648 return 0;
1095 if (eth_int_cause & ETH_INT_CAUSE_RX) { 649}
1096 /* schedule the NAPI poll routine to maintain port */
1097 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1098 650
1099 /* wait for previous write to complete */ 651static int txq_alloc_desc_index(struct tx_queue *txq)
1100 rdl(mp, INTERRUPT_MASK_REG(port_num)); 652{
653 int tx_desc_curr;
1101 654
1102 netif_rx_schedule(dev, &mp->napi); 655 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1103 }
1104#else
1105 if (eth_int_cause & ETH_INT_CAUSE_RX)
1106 mv643xx_eth_receive_queue(dev, INT_MAX);
1107#endif
1108 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
1109 mv643xx_eth_free_completed_tx_descs(dev);
1110 656
1111 /* 657 tx_desc_curr = txq->tx_curr_desc;
1112 * If no real interrupt occured, exit. 658 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
1113 * This can happen when using gigE interrupt coalescing mechanism.
1114 */
1115 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
1116 return IRQ_NONE;
1117 659
1118 return IRQ_HANDLED; 660 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
1119}
1120 661
1121#ifdef MV643XX_COAL 662 return tx_desc_curr;
663}
1122 664
1123/* 665static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
1124 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
1125 *
1126 * DESCRIPTION:
1127 * This routine sets the RX coalescing interrupt mechanism parameter.
1128 * This parameter is a timeout counter, that counts in 64 t_clk
1129 * chunks ; that when timeout event occurs a maskable interrupt
1130 * occurs.
1131 * The parameter is calculated using the tClk of the MV-643xx chip
1132 * , and the required delay of the interrupt in usec.
1133 *
1134 * INPUT:
1135 * struct mv643xx_private *mp Ethernet port
1136 * unsigned int delay Delay in usec
1137 *
1138 * OUTPUT:
1139 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1140 *
1141 * RETURN:
1142 * The interrupt coalescing value set in the gigE port.
1143 *
1144 */
1145static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp,
1146 unsigned int delay)
1147{ 666{
1148 unsigned int port_num = mp->port_num; 667 int nr_frags = skb_shinfo(skb)->nr_frags;
1149 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; 668 int frag;
1150 669
1151 /* Set RX Coalescing mechanism */ 670 for (frag = 0; frag < nr_frags; frag++) {
1152 wrl(mp, SDMA_CONFIG_REG(port_num), 671 skb_frag_t *this_frag;
1153 ((coal & 0x3fff) << 8) | 672 int tx_index;
1154 (rdl(mp, SDMA_CONFIG_REG(port_num)) 673 struct tx_desc *desc;
1155 & 0xffc000ff));
1156 674
1157 return coal; 675 this_frag = &skb_shinfo(skb)->frags[frag];
1158} 676 tx_index = txq_alloc_desc_index(txq);
1159#endif 677 desc = &txq->tx_desc_area[tx_index];
1160 678
1161/* 679 /*
1162 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path 680 * The last fragment will generate an interrupt
1163 * 681 * which will free the skb on TX completion.
1164 * DESCRIPTION: 682 */
1165 * This routine sets the TX coalescing interrupt mechanism parameter. 683 if (frag == nr_frags - 1) {
1166 * This parameter is a timeout counter, that counts in 64 t_clk 684 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
1167 * chunks ; that when timeout event occurs a maskable interrupt 685 ZERO_PADDING | TX_LAST_DESC |
1168 * occurs. 686 TX_ENABLE_INTERRUPT;
1169 * The parameter is calculated using the t_cLK frequency of the 687 txq->tx_skb[tx_index] = skb;
1170 * MV-643xx chip and the required delay in the interrupt in uSec 688 } else {
1171 * 689 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
1172 * INPUT: 690 txq->tx_skb[tx_index] = NULL;
1173 * struct mv643xx_private *mp Ethernet port 691 }
1174 * unsigned int delay Delay in uSeconds
1175 *
1176 * OUTPUT:
1177 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1178 *
1179 * RETURN:
1180 * The interrupt coalescing value set in the gigE port.
1181 *
1182 */
1183static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp,
1184 unsigned int delay)
1185{
1186 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1187 692
1188 /* Set TX Coalescing mechanism */ 693 desc->l4i_chk = 0;
1189 wrl(mp, TX_FIFO_URGENT_THRESHOLD_REG(mp->port_num), coal << 4); 694 desc->byte_cnt = this_frag->size;
695 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
696 this_frag->page_offset,
697 this_frag->size,
698 DMA_TO_DEVICE);
699 }
700}
1190 701
1191 return coal; 702static inline __be16 sum16_as_be(__sum16 sum)
703{
704 return (__force __be16)sum;
1192} 705}
1193 706
1194/* 707static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1195 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1196 *
1197 * DESCRIPTION:
1198 * This function prepares a Rx chained list of descriptors and packet
1199 * buffers in a form of a ring. The routine must be called after port
1200 * initialization routine and before port start routine.
1201 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1202 * devices in the system (i.e. DRAM). This function uses the ethernet
1203 * struct 'virtual to physical' routine (set by the user) to set the ring
1204 * with physical addresses.
1205 *
1206 * INPUT:
1207 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1208 *
1209 * OUTPUT:
1210 * The routine updates the Ethernet port control struct with information
1211 * regarding the Rx descriptors and buffers.
1212 *
1213 * RETURN:
1214 * None.
1215 */
1216static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
1217{ 708{
1218 volatile struct eth_rx_desc *p_rx_desc; 709 int nr_frags = skb_shinfo(skb)->nr_frags;
1219 int rx_desc_num = mp->rx_ring_size; 710 int tx_index;
1220 int i; 711 struct tx_desc *desc;
712 u32 cmd_sts;
713 int length;
1221 714
1222 /* initialize the next_desc_ptr links in the Rx descriptors ring */ 715 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1223 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; 716
1224 for (i = 0; i < rx_desc_num; i++) { 717 tx_index = txq_alloc_desc_index(txq);
1225 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + 718 desc = &txq->tx_desc_area[tx_index];
1226 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); 719
720 if (nr_frags) {
721 txq_submit_frag_skb(txq, skb);
722
723 length = skb_headlen(skb);
724 txq->tx_skb[tx_index] = NULL;
725 } else {
726 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
727 length = skb->len;
728 txq->tx_skb[tx_index] = skb;
1227 } 729 }
1228 730
1229 /* Save Rx desc pointer to driver struct. */ 731 desc->byte_cnt = length;
1230 mp->rx_curr_desc_q = 0; 732 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1231 mp->rx_used_desc_q = 0;
1232 733
1233 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); 734 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1234} 735 BUG_ON(skb->protocol != htons(ETH_P_IP));
1235 736
1236/* 737 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
1237 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. 738 GEN_IP_V4_CHECKSUM |
1238 * 739 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
1239 * DESCRIPTION:
1240 * This function prepares a Tx chained list of descriptors and packet
1241 * buffers in a form of a ring. The routine must be called after port
1242 * initialization routine and before port start routine.
1243 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1244 * devices in the system (i.e. DRAM). This function uses the ethernet
1245 * struct 'virtual to physical' routine (set by the user) to set the ring
1246 * with physical addresses.
1247 *
1248 * INPUT:
1249 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1250 *
1251 * OUTPUT:
1252 * The routine updates the Ethernet port control struct with information
1253 * regarding the Tx descriptors and buffers.
1254 *
1255 * RETURN:
1256 * None.
1257 */
1258static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
1259{
1260 int tx_desc_num = mp->tx_ring_size;
1261 struct eth_tx_desc *p_tx_desc;
1262 int i;
1263 740
1264 /* Initialize the next_desc_ptr links in the Tx descriptors ring */ 741 switch (ip_hdr(skb)->protocol) {
1265 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; 742 case IPPROTO_UDP:
1266 for (i = 0; i < tx_desc_num; i++) { 743 cmd_sts |= UDP_FRAME;
1267 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + 744 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
1268 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); 745 break;
746 case IPPROTO_TCP:
747 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
748 break;
749 default:
750 BUG();
751 }
752 } else {
753 /* Errata BTS #50, IHL must be 5 if no HW checksum */
754 cmd_sts |= 5 << TX_IHL_SHIFT;
755 desc->l4i_chk = 0;
1269 } 756 }
1270 757
1271 mp->tx_curr_desc_q = 0; 758 /* ensure all other descriptors are written before first cmd_sts */
1272 mp->tx_used_desc_q = 0; 759 wmb();
760 desc->cmd_sts = cmd_sts;
761
762 /* ensure all descriptors are written before poking hardware */
763 wmb();
764 txq_enable(txq);
1273 765
1274 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); 766 txq->tx_desc_count += nr_frags + 1;
1275} 767}
1276 768
1277static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 769static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1278{ 770{
1279 struct mv643xx_private *mp = netdev_priv(dev); 771 struct mv643xx_eth_private *mp = netdev_priv(dev);
1280 int err; 772 struct net_device_stats *stats = &dev->stats;
773 struct tx_queue *txq;
774 unsigned long flags;
1281 775
1282 spin_lock_irq(&mp->lock); 776 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1283 err = mii_ethtool_sset(&mp->mii, cmd); 777 stats->tx_dropped++;
1284 spin_unlock_irq(&mp->lock); 778 dev_printk(KERN_DEBUG, &dev->dev,
779 "failed to linearize skb with tiny "
780 "unaligned fragment\n");
781 return NETDEV_TX_BUSY;
782 }
1285 783
1286 return err; 784 spin_lock_irqsave(&mp->lock, flags);
1287}
1288 785
1289static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 786 txq = mp->txq + mp->txq_primary;
1290{
1291 struct mv643xx_private *mp = netdev_priv(dev);
1292 int err;
1293 787
1294 spin_lock_irq(&mp->lock); 788 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
1295 err = mii_ethtool_gset(&mp->mii, cmd); 789 spin_unlock_irqrestore(&mp->lock, flags);
1296 spin_unlock_irq(&mp->lock); 790 if (txq->index == mp->txq_primary && net_ratelimit())
791 dev_printk(KERN_ERR, &dev->dev,
792 "primary tx queue full?!\n");
793 kfree_skb(skb);
794 return NETDEV_TX_OK;
795 }
1297 796
1298 /* The PHY may support 1000baseT_Half, but the mv643xx does not */ 797 txq_submit_skb(txq, skb);
1299 cmd->supported &= ~SUPPORTED_1000baseT_Half; 798 stats->tx_bytes += skb->len;
1300 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 799 stats->tx_packets++;
800 dev->trans_start = jiffies;
1301 801
1302 return err; 802 if (txq->index == mp->txq_primary) {
803 int entries_left;
804
805 entries_left = txq->tx_ring_size - txq->tx_desc_count;
806 if (entries_left < MAX_DESCS_PER_SKB)
807 netif_stop_queue(dev);
808 }
809
810 spin_unlock_irqrestore(&mp->lock, flags);
811
812 return NETDEV_TX_OK;
1303} 813}
1304 814
815
816/* tx rate control **********************************************************/
1305/* 817/*
1306 * mv643xx_eth_open 818 * Set total maximum TX rate (shared by all TX queues for this port)
1307 * 819 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1308 * This function is called when openning the network device. The function
1309 * should initialize all the hardware, initialize cyclic Rx/Tx
1310 * descriptors chain and buffers and allocate an IRQ to the network
1311 * device.
1312 *
1313 * Input : a pointer to the network device structure
1314 *
1315 * Output : zero of success , nonzero if fails.
1316 */ 820 */
1317 821static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1318static int mv643xx_eth_open(struct net_device *dev)
1319{ 822{
1320 struct mv643xx_private *mp = netdev_priv(dev); 823 int token_rate;
1321 unsigned int port_num = mp->port_num; 824 int mtu;
1322 unsigned int size; 825 int bucket_size;
1323 int err;
1324 826
1325 /* Clear any pending ethernet port interrupts */ 827 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1326 wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0); 828 if (token_rate > 1023)
1327 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); 829 token_rate = 1023;
1328 /* wait for previous write to complete */
1329 rdl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num));
1330 830
1331 err = request_irq(dev->irq, mv643xx_eth_int_handler, 831 mtu = (mp->dev->mtu + 255) >> 8;
1332 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); 832 if (mtu > 63)
1333 if (err) { 833 mtu = 63;
1334 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
1335 return -EAGAIN;
1336 }
1337 834
1338 eth_port_init(mp); 835 bucket_size = (burst + 255) >> 8;
836 if (bucket_size > 65535)
837 bucket_size = 65535;
1339 838
1340 memset(&mp->timeout, 0, sizeof(struct timer_list)); 839 if (mp->shared->tx_bw_control_moved) {
1341 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; 840 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
1342 mp->timeout.data = (unsigned long)dev; 841 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
1343 842 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
1344 /* Allocate RX and TX skb rings */ 843 } else {
1345 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, 844 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
1346 GFP_KERNEL); 845 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
1347 if (!mp->rx_skb) { 846 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
1348 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
1349 err = -ENOMEM;
1350 goto out_free_irq;
1351 }
1352 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1353 GFP_KERNEL);
1354 if (!mp->tx_skb) {
1355 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1356 err = -ENOMEM;
1357 goto out_free_rx_skb;
1358 } 847 }
848}
1359 849
1360 /* Allocate TX ring */ 850static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1361 mp->tx_desc_count = 0; 851{
1362 size = mp->tx_ring_size * sizeof(struct eth_tx_desc); 852 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1363 mp->tx_desc_area_size = size; 853 int token_rate;
1364 854 int bucket_size;
1365 if (mp->tx_sram_size) {
1366 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
1367 mp->tx_sram_size);
1368 mp->tx_desc_dma = mp->tx_sram_addr;
1369 } else
1370 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
1371 &mp->tx_desc_dma,
1372 GFP_KERNEL);
1373 855
1374 if (!mp->p_tx_desc_area) { 856 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1375 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", 857 if (token_rate > 1023)
1376 dev->name, size); 858 token_rate = 1023;
1377 err = -ENOMEM;
1378 goto out_free_tx_skb;
1379 }
1380 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
1381 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
1382
1383 ether_init_tx_desc_ring(mp);
1384
1385 /* Allocate RX ring */
1386 mp->rx_desc_count = 0;
1387 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
1388 mp->rx_desc_area_size = size;
1389
1390 if (mp->rx_sram_size) {
1391 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
1392 mp->rx_sram_size);
1393 mp->rx_desc_dma = mp->rx_sram_addr;
1394 } else
1395 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
1396 &mp->rx_desc_dma,
1397 GFP_KERNEL);
1398 859
1399 if (!mp->p_rx_desc_area) { 860 bucket_size = (burst + 255) >> 8;
1400 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", 861 if (bucket_size > 65535)
1401 dev->name, size); 862 bucket_size = 65535;
1402 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
1403 dev->name);
1404 if (mp->rx_sram_size)
1405 iounmap(mp->p_tx_desc_area);
1406 else
1407 dma_free_coherent(NULL, mp->tx_desc_area_size,
1408 mp->p_tx_desc_area, mp->tx_desc_dma);
1409 err = -ENOMEM;
1410 goto out_free_tx_skb;
1411 }
1412 memset((void *)mp->p_rx_desc_area, 0, size);
1413 863
1414 ether_init_rx_desc_ring(mp); 864 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
1415 865 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
1416 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ 866 (bucket_size << 10) | token_rate);
867}
1417 868
1418#ifdef MV643XX_NAPI 869static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1419 napi_enable(&mp->napi); 870{
1420#endif 871 struct mv643xx_eth_private *mp = txq_to_mp(txq);
872 int off;
873 u32 val;
1421 874
1422 eth_port_start(dev); 875 /*
876 * Turn on fixed priority mode.
877 */
878 if (mp->shared->tx_bw_control_moved)
879 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
880 else
881 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1423 882
1424 /* Interrupt Coalescing */ 883 val = rdl(mp, off);
884 val |= 1 << txq->index;
885 wrl(mp, off, val);
886}
1425 887
1426#ifdef MV643XX_COAL 888static void txq_set_wrr(struct tx_queue *txq, int weight)
1427 mp->rx_int_coal = 889{
1428 eth_port_set_rx_coal(mp, MV643XX_RX_COAL); 890 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1429#endif 891 int off;
892 u32 val;
1430 893
1431 mp->tx_int_coal = 894 /*
1432 eth_port_set_tx_coal(mp, MV643XX_TX_COAL); 895 * Turn off fixed priority mode.
896 */
897 if (mp->shared->tx_bw_control_moved)
898 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
899 else
900 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1433 901
1434 /* Unmask phy and link status changes interrupts */ 902 val = rdl(mp, off);
1435 wrl(mp, INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT); 903 val &= ~(1 << txq->index);
904 wrl(mp, off, val);
1436 905
1437 /* Unmask RX buffer and TX end interrupt */ 906 /*
1438 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); 907 * Configure WRR weight for this queue.
908 */
909 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
1439 910
1440 return 0; 911 val = rdl(mp, off);
912 val = (val & ~0xff) | (weight & 0xff);
913 wrl(mp, off, val);
914}
1441 915
1442out_free_tx_skb:
1443 kfree(mp->tx_skb);
1444out_free_rx_skb:
1445 kfree(mp->rx_skb);
1446out_free_irq:
1447 free_irq(dev->irq, dev);
1448 916
1449 return err; 917/* mii management interface *************************************************/
1450} 918#define SMI_BUSY 0x10000000
919#define SMI_READ_VALID 0x08000000
920#define SMI_OPCODE_READ 0x04000000
921#define SMI_OPCODE_WRITE 0x00000000
1451 922
1452static void mv643xx_eth_free_tx_rings(struct net_device *dev) 923static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
924 unsigned int reg, unsigned int *value)
1453{ 925{
1454 struct mv643xx_private *mp = netdev_priv(dev); 926 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
927 unsigned long flags;
928 int i;
1455 929
1456 /* Stop Tx Queues */ 930 /* the SMI register is a shared resource */
1457 mv643xx_eth_port_disable_tx(mp); 931 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1458 932
1459 /* Free outstanding skb's on TX ring */ 933 /* wait for the SMI register to become available */
1460 mv643xx_eth_free_all_tx_descs(dev); 934 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
935 if (i == 1000) {
936 printk("%s: PHY busy timeout\n", mp->dev->name);
937 goto out;
938 }
939 udelay(10);
940 }
1461 941
1462 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); 942 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1463 943
1464 /* Free TX ring */ 944 /* now wait for the data to be valid */
1465 if (mp->tx_sram_size) 945 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
1466 iounmap(mp->p_tx_desc_area); 946 if (i == 1000) {
1467 else 947 printk("%s: PHY read timeout\n", mp->dev->name);
1468 dma_free_coherent(NULL, mp->tx_desc_area_size, 948 goto out;
1469 mp->p_tx_desc_area, mp->tx_desc_dma); 949 }
950 udelay(10);
951 }
952
953 *value = readl(smi_reg) & 0xffff;
954out:
955 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1470} 956}
1471 957
1472static void mv643xx_eth_free_rx_rings(struct net_device *dev) 958static void smi_reg_write(struct mv643xx_eth_private *mp,
959 unsigned int addr,
960 unsigned int reg, unsigned int value)
1473{ 961{
1474 struct mv643xx_private *mp = netdev_priv(dev); 962 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
1475 int curr; 963 unsigned long flags;
964 int i;
1476 965
1477 /* Stop RX Queues */ 966 /* the SMI register is a shared resource */
1478 mv643xx_eth_port_disable_rx(mp); 967 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1479 968
1480 /* Free preallocated skb's on RX rings */ 969 /* wait for the SMI register to become available */
1481 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { 970 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
1482 if (mp->rx_skb[curr]) { 971 if (i == 1000) {
1483 dev_kfree_skb(mp->rx_skb[curr]); 972 printk("%s: PHY busy timeout\n", mp->dev->name);
1484 mp->rx_desc_count--; 973 goto out;
1485 } 974 }
975 udelay(10);
1486 } 976 }
1487 977
1488 if (mp->rx_desc_count) 978 writel(SMI_OPCODE_WRITE | (reg << 21) |
1489 printk(KERN_ERR 979 (addr << 16) | (value & 0xffff), smi_reg);
1490 "%s: Error in freeing Rx Ring. %d skb's still" 980out:
1491 " stuck in RX Ring - ignoring them\n", dev->name, 981 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1492 mp->rx_desc_count);
1493 /* Free RX ring */
1494 if (mp->rx_sram_size)
1495 iounmap(mp->p_rx_desc_area);
1496 else
1497 dma_free_coherent(NULL, mp->rx_desc_area_size,
1498 mp->p_rx_desc_area, mp->rx_desc_dma);
1499} 982}
1500 983
1501/*
1502 * mv643xx_eth_stop
1503 *
1504 * This function is used when closing the network device.
1505 * It updates the hardware,
1506 * release all memory that holds buffers and descriptors and release the IRQ.
1507 * Input : a pointer to the device structure
1508 * Output : zero if success , nonzero if fails
1509 */
1510 984
1511static int mv643xx_eth_stop(struct net_device *dev) 985/* mib counters *************************************************************/
986static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1512{ 987{
1513 struct mv643xx_private *mp = netdev_priv(dev); 988 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1514 unsigned int port_num = mp->port_num; 989}
1515 990
1516 /* Mask all interrupts on ethernet port */ 991static void mib_counters_clear(struct mv643xx_eth_private *mp)
1517 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); 992{
1518 /* wait for previous write to complete */ 993 int i;
1519 rdl(mp, INTERRUPT_MASK_REG(port_num));
1520 994
1521#ifdef MV643XX_NAPI 995 for (i = 0; i < 0x80; i += 4)
1522 napi_disable(&mp->napi); 996 mib_read(mp, i);
1523#endif 997}
1524 netif_carrier_off(dev); 998
1525 netif_stop_queue(dev); 999static void mib_counters_update(struct mv643xx_eth_private *mp)
1000{
1001 struct mib_counters *p = &mp->mib_counters;
1002
1003 p->good_octets_received += mib_read(mp, 0x00);
1004 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1005 p->bad_octets_received += mib_read(mp, 0x08);
1006 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1007 p->good_frames_received += mib_read(mp, 0x10);
1008 p->bad_frames_received += mib_read(mp, 0x14);
1009 p->broadcast_frames_received += mib_read(mp, 0x18);
1010 p->multicast_frames_received += mib_read(mp, 0x1c);
1011 p->frames_64_octets += mib_read(mp, 0x20);
1012 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1013 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1014 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1015 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1016 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1017 p->good_octets_sent += mib_read(mp, 0x38);
1018 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1019 p->good_frames_sent += mib_read(mp, 0x40);
1020 p->excessive_collision += mib_read(mp, 0x44);
1021 p->multicast_frames_sent += mib_read(mp, 0x48);
1022 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1023 p->unrec_mac_control_received += mib_read(mp, 0x50);
1024 p->fc_sent += mib_read(mp, 0x54);
1025 p->good_fc_received += mib_read(mp, 0x58);
1026 p->bad_fc_received += mib_read(mp, 0x5c);
1027 p->undersize_received += mib_read(mp, 0x60);
1028 p->fragments_received += mib_read(mp, 0x64);
1029 p->oversize_received += mib_read(mp, 0x68);
1030 p->jabber_received += mib_read(mp, 0x6c);
1031 p->mac_receive_error += mib_read(mp, 0x70);
1032 p->bad_crc_event += mib_read(mp, 0x74);
1033 p->collision += mib_read(mp, 0x78);
1034 p->late_collision += mib_read(mp, 0x7c);
1035}
1036
1037
1038/* ethtool ******************************************************************/
1039struct mv643xx_eth_stats {
1040 char stat_string[ETH_GSTRING_LEN];
1041 int sizeof_stat;
1042 int netdev_off;
1043 int mp_off;
1044};
1045
1046#define SSTAT(m) \
1047 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1048 offsetof(struct net_device, stats.m), -1 }
1049
1050#define MIBSTAT(m) \
1051 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1052 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1053
1054static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1055 SSTAT(rx_packets),
1056 SSTAT(tx_packets),
1057 SSTAT(rx_bytes),
1058 SSTAT(tx_bytes),
1059 SSTAT(rx_errors),
1060 SSTAT(tx_errors),
1061 SSTAT(rx_dropped),
1062 SSTAT(tx_dropped),
1063 MIBSTAT(good_octets_received),
1064 MIBSTAT(bad_octets_received),
1065 MIBSTAT(internal_mac_transmit_err),
1066 MIBSTAT(good_frames_received),
1067 MIBSTAT(bad_frames_received),
1068 MIBSTAT(broadcast_frames_received),
1069 MIBSTAT(multicast_frames_received),
1070 MIBSTAT(frames_64_octets),
1071 MIBSTAT(frames_65_to_127_octets),
1072 MIBSTAT(frames_128_to_255_octets),
1073 MIBSTAT(frames_256_to_511_octets),
1074 MIBSTAT(frames_512_to_1023_octets),
1075 MIBSTAT(frames_1024_to_max_octets),
1076 MIBSTAT(good_octets_sent),
1077 MIBSTAT(good_frames_sent),
1078 MIBSTAT(excessive_collision),
1079 MIBSTAT(multicast_frames_sent),
1080 MIBSTAT(broadcast_frames_sent),
1081 MIBSTAT(unrec_mac_control_received),
1082 MIBSTAT(fc_sent),
1083 MIBSTAT(good_fc_received),
1084 MIBSTAT(bad_fc_received),
1085 MIBSTAT(undersize_received),
1086 MIBSTAT(fragments_received),
1087 MIBSTAT(oversize_received),
1088 MIBSTAT(jabber_received),
1089 MIBSTAT(mac_receive_error),
1090 MIBSTAT(bad_crc_event),
1091 MIBSTAT(collision),
1092 MIBSTAT(late_collision),
1093};
1526 1094
1527 eth_port_reset(mp); 1095static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1096{
1097 struct mv643xx_eth_private *mp = netdev_priv(dev);
1098 int err;
1528 1099
1529 mv643xx_eth_free_tx_rings(dev); 1100 spin_lock_irq(&mp->lock);
1530 mv643xx_eth_free_rx_rings(dev); 1101 err = mii_ethtool_gset(&mp->mii, cmd);
1102 spin_unlock_irq(&mp->lock);
1531 1103
1532 free_irq(dev->irq, dev); 1104 /*
1105 * The MAC does not support 1000baseT_Half.
1106 */
1107 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1108 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1109
1110 return err;
1111}
1112
1113static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1114{
1115 cmd->supported = SUPPORTED_MII;
1116 cmd->advertising = ADVERTISED_MII;
1117 cmd->speed = SPEED_1000;
1118 cmd->duplex = DUPLEX_FULL;
1119 cmd->port = PORT_MII;
1120 cmd->phy_address = 0;
1121 cmd->transceiver = XCVR_INTERNAL;
1122 cmd->autoneg = AUTONEG_DISABLE;
1123 cmd->maxtxpkt = 1;
1124 cmd->maxrxpkt = 1;
1533 1125
1534 return 0; 1126 return 0;
1535} 1127}
1536 1128
1537#ifdef MV643XX_NAPI 1129static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1538/*
1539 * mv643xx_poll
1540 *
1541 * This function is used in case of NAPI
1542 */
1543static int mv643xx_poll(struct napi_struct *napi, int budget)
1544{ 1130{
1545 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi); 1131 struct mv643xx_eth_private *mp = netdev_priv(dev);
1546 struct net_device *dev = mp->dev; 1132 int err;
1547 unsigned int port_num = mp->port_num;
1548 int work_done;
1549 1133
1550#ifdef MV643XX_TX_FAST_REFILL 1134 /*
1551 if (++mp->tx_clean_threshold > 5) { 1135 * The MAC does not support 1000baseT_Half.
1552 mv643xx_eth_free_completed_tx_descs(dev); 1136 */
1553 mp->tx_clean_threshold = 0; 1137 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1554 }
1555#endif
1556 1138
1557 work_done = 0; 1139 spin_lock_irq(&mp->lock);
1558 if ((rdl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) 1140 err = mii_ethtool_sset(&mp->mii, cmd);
1559 != (u32) mp->rx_used_desc_q) 1141 spin_unlock_irq(&mp->lock);
1560 work_done = mv643xx_eth_receive_queue(dev, budget);
1561 1142
1562 if (work_done < budget) { 1143 return err;
1563 netif_rx_complete(dev, napi); 1144}
1564 wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0);
1565 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1566 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1567 }
1568 1145
1569 return work_done; 1146static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1147{
1148 return -EINVAL;
1570} 1149}
1571#endif
1572 1150
1573/** 1151static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1574 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments 1152 struct ethtool_drvinfo *drvinfo)
1575 * 1153{
1576 * Hardware can't handle unaligned fragments smaller than 9 bytes. 1154 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1577 * This helper function detects that case. 1155 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1578 */ 1156 strncpy(drvinfo->fw_version, "N/A", 32);
1157 strncpy(drvinfo->bus_info, "platform", 32);
1158 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1159}
1579 1160
1580static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) 1161static int mv643xx_eth_nway_reset(struct net_device *dev)
1581{ 1162{
1582 unsigned int frag; 1163 struct mv643xx_eth_private *mp = netdev_priv(dev);
1583 skb_frag_t *fragp;
1584 1164
1585 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 1165 return mii_nway_restart(&mp->mii);
1586 fragp = &skb_shinfo(skb)->frags[frag];
1587 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1588 return 1;
1589 }
1590 return 0;
1591} 1166}
1592 1167
1593/** 1168static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1594 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1595 */
1596static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1597{ 1169{
1598 int tx_desc_curr; 1170 return -EINVAL;
1599 1171}
1600 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1601 1172
1602 tx_desc_curr = mp->tx_curr_desc_q; 1173static u32 mv643xx_eth_get_link(struct net_device *dev)
1603 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; 1174{
1175 struct mv643xx_eth_private *mp = netdev_priv(dev);
1604 1176
1605 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); 1177 return mii_link_ok(&mp->mii);
1178}
1606 1179
1607 return tx_desc_curr; 1180static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1181{
1182 return 1;
1608} 1183}
1609 1184
1610/** 1185static void mv643xx_eth_get_strings(struct net_device *dev,
1611 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. 1186 uint32_t stringset, uint8_t *data)
1612 *
1613 * Ensure the data for each fragment to be transmitted is mapped properly,
1614 * then fill in descriptors in the tx hw queue.
1615 */
1616static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1617 struct sk_buff *skb)
1618{ 1187{
1619 int frag; 1188 int i;
1620 int tx_index;
1621 struct eth_tx_desc *desc;
1622 1189
1623 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 1190 if (stringset == ETH_SS_STATS) {
1624 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; 1191 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1625 1192 memcpy(data + i * ETH_GSTRING_LEN,
1626 tx_index = eth_alloc_tx_desc_index(mp); 1193 mv643xx_eth_stats[i].stat_string,
1627 desc = &mp->p_tx_desc_area[tx_index]; 1194 ETH_GSTRING_LEN);
1628 1195 }
1629 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1630 /* Last Frag enables interrupt and frees the skb */
1631 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1632 desc->cmd_sts |= ETH_ZERO_PADDING |
1633 ETH_TX_LAST_DESC |
1634 ETH_TX_ENABLE_INTERRUPT;
1635 mp->tx_skb[tx_index] = skb;
1636 } else
1637 mp->tx_skb[tx_index] = NULL;
1638
1639 desc = &mp->p_tx_desc_area[tx_index];
1640 desc->l4i_chk = 0;
1641 desc->byte_cnt = this_frag->size;
1642 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1643 this_frag->page_offset,
1644 this_frag->size,
1645 DMA_TO_DEVICE);
1646 } 1196 }
1647} 1197}
1648 1198
1649static inline __be16 sum16_as_be(__sum16 sum) 1199static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1200 struct ethtool_stats *stats,
1201 uint64_t *data)
1650{ 1202{
1651 return (__force __be16)sum; 1203 struct mv643xx_eth_private *mp = dev->priv;
1652} 1204 int i;
1653 1205
1654/** 1206 mib_counters_update(mp);
1655 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1656 *
1657 * Ensure the data for an skb to be transmitted is mapped properly,
1658 * then fill in descriptors in the tx hw queue and start the hardware.
1659 */
1660static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1661 struct sk_buff *skb)
1662{
1663 int tx_index;
1664 struct eth_tx_desc *desc;
1665 u32 cmd_sts;
1666 int length;
1667 int nr_frags = skb_shinfo(skb)->nr_frags;
1668 1207
1669 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; 1208 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1209 const struct mv643xx_eth_stats *stat;
1210 void *p;
1670 1211
1671 tx_index = eth_alloc_tx_desc_index(mp); 1212 stat = mv643xx_eth_stats + i;
1672 desc = &mp->p_tx_desc_area[tx_index];
1673 1213
1674 if (nr_frags) { 1214 if (stat->netdev_off >= 0)
1675 eth_tx_fill_frag_descs(mp, skb); 1215 p = ((void *)mp->dev) + stat->netdev_off;
1216 else
1217 p = ((void *)mp) + stat->mp_off;
1676 1218
1677 length = skb_headlen(skb); 1219 data[i] = (stat->sizeof_stat == 8) ?
1678 mp->tx_skb[tx_index] = NULL; 1220 *(uint64_t *)p : *(uint32_t *)p;
1679 } else {
1680 cmd_sts |= ETH_ZERO_PADDING |
1681 ETH_TX_LAST_DESC |
1682 ETH_TX_ENABLE_INTERRUPT;
1683 length = skb->len;
1684 mp->tx_skb[tx_index] = skb;
1685 } 1221 }
1222}
1686 1223
1687 desc->byte_cnt = length; 1224static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1688 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); 1225{
1226 if (sset == ETH_SS_STATS)
1227 return ARRAY_SIZE(mv643xx_eth_stats);
1689 1228
1690 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1229 return -EOPNOTSUPP;
1691 BUG_ON(skb->protocol != htons(ETH_P_IP)); 1230}
1692 1231
1693 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | 1232static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1694 ETH_GEN_IP_V_4_CHECKSUM | 1233 .get_settings = mv643xx_eth_get_settings,
1695 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; 1234 .set_settings = mv643xx_eth_set_settings,
1235 .get_drvinfo = mv643xx_eth_get_drvinfo,
1236 .nway_reset = mv643xx_eth_nway_reset,
1237 .get_link = mv643xx_eth_get_link,
1238 .set_sg = ethtool_op_set_sg,
1239 .get_strings = mv643xx_eth_get_strings,
1240 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1241 .get_sset_count = mv643xx_eth_get_sset_count,
1242};
1696 1243
1697 switch (ip_hdr(skb)->protocol) { 1244static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1698 case IPPROTO_UDP: 1245 .get_settings = mv643xx_eth_get_settings_phyless,
1699 cmd_sts |= ETH_UDP_FRAME; 1246 .set_settings = mv643xx_eth_set_settings_phyless,
1700 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); 1247 .get_drvinfo = mv643xx_eth_get_drvinfo,
1701 break; 1248 .nway_reset = mv643xx_eth_nway_reset_phyless,
1702 case IPPROTO_TCP: 1249 .get_link = mv643xx_eth_get_link_phyless,
1703 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); 1250 .set_sg = ethtool_op_set_sg,
1704 break; 1251 .get_strings = mv643xx_eth_get_strings,
1705 default: 1252 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1706 BUG(); 1253 .get_sset_count = mv643xx_eth_get_sset_count,
1707 } 1254};
1708 } else {
1709 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1710 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1711 desc->l4i_chk = 0;
1712 }
1713 1255
1714 /* ensure all other descriptors are written before first cmd_sts */
1715 wmb();
1716 desc->cmd_sts = cmd_sts;
1717 1256
1718 /* ensure all descriptors are written before poking hardware */ 1257/* address handling *********************************************************/
1719 wmb(); 1258static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1720 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); 1259{
1260 unsigned int mac_h;
1261 unsigned int mac_l;
1262
1263 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1264 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1721 1265
1722 mp->tx_desc_count += nr_frags + 1; 1266 addr[0] = (mac_h >> 24) & 0xff;
1267 addr[1] = (mac_h >> 16) & 0xff;
1268 addr[2] = (mac_h >> 8) & 0xff;
1269 addr[3] = mac_h & 0xff;
1270 addr[4] = (mac_l >> 8) & 0xff;
1271 addr[5] = mac_l & 0xff;
1723} 1272}
1724 1273
1725/** 1274static void init_mac_tables(struct mv643xx_eth_private *mp)
1726 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1727 *
1728 */
1729static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1730{ 1275{
1731 struct mv643xx_private *mp = netdev_priv(dev); 1276 int i;
1732 struct net_device_stats *stats = &dev->stats;
1733 unsigned long flags;
1734
1735 BUG_ON(netif_queue_stopped(dev));
1736 1277
1737 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { 1278 for (i = 0; i < 0x100; i += 4) {
1738 stats->tx_dropped++; 1279 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1739 printk(KERN_DEBUG "%s: failed to linearize tiny " 1280 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1740 "unaligned fragment\n", dev->name);
1741 return NETDEV_TX_BUSY;
1742 } 1281 }
1743 1282
1744 spin_lock_irqsave(&mp->lock, flags); 1283 for (i = 0; i < 0x10; i += 4)
1284 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1285}
1745 1286
1746 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { 1287static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1747 printk(KERN_ERR "%s: transmit with queue full\n", dev->name); 1288 int table, unsigned char entry)
1748 netif_stop_queue(dev); 1289{
1749 spin_unlock_irqrestore(&mp->lock, flags); 1290 unsigned int table_reg;
1750 return NETDEV_TX_BUSY;
1751 }
1752 1291
1753 eth_tx_submit_descs_for_skb(mp, skb); 1292 /* Set "accepts frame bit" at specified table entry */
1754 stats->tx_bytes += skb->len; 1293 table_reg = rdl(mp, table + (entry & 0xfc));
1755 stats->tx_packets++; 1294 table_reg |= 0x01 << (8 * (entry & 3));
1756 dev->trans_start = jiffies; 1295 wrl(mp, table + (entry & 0xfc), table_reg);
1296}
1757 1297
1758 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) 1298static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1759 netif_stop_queue(dev); 1299{
1300 unsigned int mac_h;
1301 unsigned int mac_l;
1302 int table;
1760 1303
1761 spin_unlock_irqrestore(&mp->lock, flags); 1304 mac_l = (addr[4] << 8) | addr[5];
1305 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1762 1306
1763 return NETDEV_TX_OK; 1307 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1308 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1309
1310 table = UNICAST_TABLE(mp->port_num);
1311 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1764} 1312}
1765 1313
1766#ifdef CONFIG_NET_POLL_CONTROLLER 1314static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1767static void mv643xx_netpoll(struct net_device *netdev)
1768{ 1315{
1769 struct mv643xx_private *mp = netdev_priv(netdev); 1316 struct mv643xx_eth_private *mp = netdev_priv(dev);
1770 int port_num = mp->port_num;
1771 1317
1772 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); 1318 /* +2 is for the offset of the HW addr type */
1773 /* wait for previous write to complete */ 1319 memcpy(dev->dev_addr, addr + 2, 6);
1774 rdl(mp, INTERRUPT_MASK_REG(port_num));
1775 1320
1776 mv643xx_eth_int_handler(netdev->irq, netdev); 1321 init_mac_tables(mp);
1322 uc_addr_set(mp, dev->dev_addr);
1777 1323
1778 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); 1324 return 0;
1779} 1325}
1780#endif
1781 1326
1782static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, 1327static int addr_crc(unsigned char *addr)
1783 int speed, int duplex,
1784 struct ethtool_cmd *cmd)
1785{ 1328{
1786 struct mv643xx_private *mp = netdev_priv(dev); 1329 int crc = 0;
1330 int i;
1787 1331
1788 memset(cmd, 0, sizeof(*cmd)); 1332 for (i = 0; i < 6; i++) {
1333 int j;
1789 1334
1790 cmd->port = PORT_MII; 1335 crc = (crc ^ addr[i]) << 8;
1791 cmd->transceiver = XCVR_INTERNAL; 1336 for (j = 7; j >= 0; j--) {
1792 cmd->phy_address = phy_address; 1337 if (crc & (0x100 << j))
1793 1338 crc ^= 0x107 << j;
1794 if (speed == 0) { 1339 }
1795 cmd->autoneg = AUTONEG_ENABLE;
1796 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1797 cmd->speed = SPEED_100;
1798 cmd->advertising = ADVERTISED_10baseT_Half |
1799 ADVERTISED_10baseT_Full |
1800 ADVERTISED_100baseT_Half |
1801 ADVERTISED_100baseT_Full;
1802 if (mp->mii.supports_gmii)
1803 cmd->advertising |= ADVERTISED_1000baseT_Full;
1804 } else {
1805 cmd->autoneg = AUTONEG_DISABLE;
1806 cmd->speed = speed;
1807 cmd->duplex = duplex;
1808 } 1340 }
1341
1342 return crc;
1809} 1343}
1810 1344
1811/*/ 1345static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1812 * mv643xx_eth_probe
1813 *
1814 * First function called after registering the network device.
1815 * It's purpose is to initialize the device as an ethernet device,
1816 * fill the ethernet device structure with pointers * to functions,
1817 * and set the MAC address of the interface
1818 *
1819 * Input : struct device *
1820 * Output : -ENOMEM if failed , 0 if success
1821 */
1822static int mv643xx_eth_probe(struct platform_device *pdev)
1823{ 1346{
1824 struct mv643xx_eth_platform_data *pd; 1347 struct mv643xx_eth_private *mp = netdev_priv(dev);
1825 int port_num; 1348 u32 port_config;
1826 struct mv643xx_private *mp; 1349 struct dev_addr_list *addr;
1827 struct net_device *dev; 1350 int i;
1828 u8 *p;
1829 struct resource *res;
1830 int err;
1831 struct ethtool_cmd cmd;
1832 int duplex = DUPLEX_HALF;
1833 int speed = 0; /* default to auto-negotiation */
1834 DECLARE_MAC_BUF(mac);
1835 1351
1836 pd = pdev->dev.platform_data; 1352 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1837 if (pd == NULL) { 1353 if (dev->flags & IFF_PROMISC)
1838 printk(KERN_ERR "No mv643xx_eth_platform_data\n"); 1354 port_config |= UNICAST_PROMISCUOUS_MODE;
1839 return -ENODEV; 1355 else
1356 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1357 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1358
1359 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1360 int port_num = mp->port_num;
1361 u32 accept = 0x01010101;
1362
1363 for (i = 0; i < 0x100; i += 4) {
1364 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1365 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1366 }
1367 return;
1840 } 1368 }
1841 1369
1842 if (pd->shared == NULL) { 1370 for (i = 0; i < 0x100; i += 4) {
1843 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n"); 1371 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1844 return -ENODEV; 1372 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1845 } 1373 }
1846 1374
1847 dev = alloc_etherdev(sizeof(struct mv643xx_private)); 1375 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1848 if (!dev) 1376 u8 *a = addr->da_addr;
1849 return -ENOMEM; 1377 int table;
1850 1378
1851 platform_set_drvdata(pdev, dev); 1379 if (addr->da_addrlen != 6)
1380 continue;
1852 1381
1853 mp = netdev_priv(dev); 1382 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1854 mp->dev = dev; 1383 table = SPECIAL_MCAST_TABLE(mp->port_num);
1855#ifdef MV643XX_NAPI 1384 set_filter_table_entry(mp, table, a[5]);
1856 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64); 1385 } else {
1857#endif 1386 int crc = addr_crc(a);
1858 1387
1859 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1388 table = OTHER_MCAST_TABLE(mp->port_num);
1860 BUG_ON(!res); 1389 set_filter_table_entry(mp, table, crc);
1861 dev->irq = res->start; 1390 }
1391 }
1392}
1862 1393
1863 dev->open = mv643xx_eth_open;
1864 dev->stop = mv643xx_eth_stop;
1865 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1866 dev->set_mac_address = mv643xx_eth_set_mac_address;
1867 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1868 1394
1869 /* No need to Tx Timeout */ 1395/* rx/tx queue initialisation ***********************************************/
1870 dev->tx_timeout = mv643xx_eth_tx_timeout; 1396static int rxq_init(struct mv643xx_eth_private *mp, int index)
1397{
1398 struct rx_queue *rxq = mp->rxq + index;
1399 struct rx_desc *rx_desc;
1400 int size;
1401 int i;
1871 1402
1872#ifdef CONFIG_NET_POLL_CONTROLLER 1403 rxq->index = index;
1873 dev->poll_controller = mv643xx_netpoll;
1874#endif
1875 1404
1876 dev->watchdog_timeo = 2 * HZ; 1405 rxq->rx_ring_size = mp->default_rx_ring_size;
1877 dev->base_addr = 0;
1878 dev->change_mtu = mv643xx_eth_change_mtu;
1879 dev->do_ioctl = mv643xx_eth_do_ioctl;
1880 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1881 1406
1882#ifdef MV643XX_CHECKSUM_OFFLOAD_TX 1407 rxq->rx_desc_count = 0;
1883#ifdef MAX_SKB_FRAGS 1408 rxq->rx_curr_desc = 0;
1884 /* 1409 rxq->rx_used_desc = 0;
1885 * Zero copy can only work if we use Discovery II memory. Else, we will
1886 * have to map the buffers to ISA memory which is only 16 MB
1887 */
1888 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1889#endif
1890#endif
1891 1410
1892 /* Configure the timeout task */ 1411 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1893 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1894 1412
1895 spin_lock_init(&mp->lock); 1413 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1414 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1415 mp->rx_desc_sram_size);
1416 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1417 } else {
1418 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1419 &rxq->rx_desc_dma,
1420 GFP_KERNEL);
1421 }
1896 1422
1897 mp->shared = platform_get_drvdata(pd->shared); 1423 if (rxq->rx_desc_area == NULL) {
1898 port_num = mp->port_num = pd->port_number; 1424 dev_printk(KERN_ERR, &mp->dev->dev,
1425 "can't allocate rx ring (%d bytes)\n", size);
1426 goto out;
1427 }
1428 memset(rxq->rx_desc_area, 0, size);
1899 1429
1900 if (mp->shared->win_protect) 1430 rxq->rx_desc_area_size = size;
1901 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect); 1431 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1432 GFP_KERNEL);
1433 if (rxq->rx_skb == NULL) {
1434 dev_printk(KERN_ERR, &mp->dev->dev,
1435 "can't allocate rx skb ring\n");
1436 goto out_free;
1437 }
1902 1438
1903 mp->shared_smi = mp->shared; 1439 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1904 if (pd->shared_smi != NULL) 1440 for (i = 0; i < rxq->rx_ring_size; i++) {
1905 mp->shared_smi = platform_get_drvdata(pd->shared_smi); 1441 int nexti = (i + 1) % rxq->rx_ring_size;
1442 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1443 nexti * sizeof(struct rx_desc);
1444 }
1906 1445
1907 /* set default config values */ 1446 init_timer(&rxq->rx_oom);
1908 eth_port_uc_addr_get(mp, dev->dev_addr); 1447 rxq->rx_oom.data = (unsigned long)rxq;
1909 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE; 1448 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1910 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1911 1449
1912 if (is_valid_ether_addr(pd->mac_addr)) 1450 return 0;
1913 memcpy(dev->dev_addr, pd->mac_addr, 6);
1914 1451
1915 if (pd->phy_addr || pd->force_phy_addr)
1916 ethernet_phy_set(mp, pd->phy_addr);
1917 1452
1918 if (pd->rx_queue_size) 1453out_free:
1919 mp->rx_ring_size = pd->rx_queue_size; 1454 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1455 iounmap(rxq->rx_desc_area);
1456 else
1457 dma_free_coherent(NULL, size,
1458 rxq->rx_desc_area,
1459 rxq->rx_desc_dma);
1920 1460
1921 if (pd->tx_queue_size) 1461out:
1922 mp->tx_ring_size = pd->tx_queue_size; 1462 return -ENOMEM;
1463}
1923 1464
1924 if (pd->tx_sram_size) { 1465static void rxq_deinit(struct rx_queue *rxq)
1925 mp->tx_sram_size = pd->tx_sram_size; 1466{
1926 mp->tx_sram_addr = pd->tx_sram_addr; 1467 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1927 } 1468 int i;
1928 1469
1929 if (pd->rx_sram_size) { 1470 rxq_disable(rxq);
1930 mp->rx_sram_size = pd->rx_sram_size;
1931 mp->rx_sram_addr = pd->rx_sram_addr;
1932 }
1933 1471
1934 duplex = pd->duplex; 1472 del_timer_sync(&rxq->rx_oom);
1935 speed = pd->speed;
1936 1473
1937 /* Hook up MII support for ethtool */ 1474 for (i = 0; i < rxq->rx_ring_size; i++) {
1938 mp->mii.dev = dev; 1475 if (rxq->rx_skb[i]) {
1939 mp->mii.mdio_read = mv643xx_mdio_read; 1476 dev_kfree_skb(rxq->rx_skb[i]);
1940 mp->mii.mdio_write = mv643xx_mdio_write; 1477 rxq->rx_desc_count--;
1941 mp->mii.phy_id = ethernet_phy_get(mp); 1478 }
1942 mp->mii.phy_id_mask = 0x3f; 1479 }
1943 mp->mii.reg_num_mask = 0x1f;
1944 1480
1945 err = ethernet_phy_detect(mp); 1481 if (rxq->rx_desc_count) {
1946 if (err) { 1482 dev_printk(KERN_ERR, &mp->dev->dev,
1947 pr_debug("%s: No PHY detected at addr %d\n", 1483 "error freeing rx ring -- %d skbs stuck\n",
1948 dev->name, ethernet_phy_get(mp)); 1484 rxq->rx_desc_count);
1949 goto out;
1950 } 1485 }
1951 1486
1952 ethernet_phy_reset(mp); 1487 if (rxq->index == mp->rxq_primary &&
1953 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); 1488 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1954 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); 1489 iounmap(rxq->rx_desc_area);
1955 mv643xx_eth_update_pscr(dev, &cmd); 1490 else
1956 mv643xx_set_settings(dev, &cmd); 1491 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1492 rxq->rx_desc_area, rxq->rx_desc_dma);
1957 1493
1958 SET_NETDEV_DEV(dev, &pdev->dev); 1494 kfree(rxq->rx_skb);
1959 err = register_netdev(dev); 1495}
1960 if (err)
1961 goto out;
1962 1496
1963 p = dev->dev_addr; 1497static int txq_init(struct mv643xx_eth_private *mp, int index)
1964 printk(KERN_NOTICE 1498{
1965 "%s: port %d with MAC address %s\n", 1499 struct tx_queue *txq = mp->txq + index;
1966 dev->name, port_num, print_mac(mac, p)); 1500 struct tx_desc *tx_desc;
1501 int size;
1502 int i;
1967 1503
1968 if (dev->features & NETIF_F_SG) 1504 txq->index = index;
1969 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1970 1505
1971 if (dev->features & NETIF_F_IP_CSUM) 1506 txq->tx_ring_size = mp->default_tx_ring_size;
1972 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1973 dev->name);
1974 1507
1975#ifdef MV643XX_CHECKSUM_OFFLOAD_TX 1508 txq->tx_desc_count = 0;
1976 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); 1509 txq->tx_curr_desc = 0;
1977#endif 1510 txq->tx_used_desc = 0;
1978 1511
1979#ifdef MV643XX_COAL 1512 size = txq->tx_ring_size * sizeof(struct tx_desc);
1980 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1981 dev->name);
1982#endif
1983 1513
1984#ifdef MV643XX_NAPI 1514 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1985 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); 1515 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1986#endif 1516 mp->tx_desc_sram_size);
1517 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1518 } else {
1519 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1520 &txq->tx_desc_dma,
1521 GFP_KERNEL);
1522 }
1523
1524 if (txq->tx_desc_area == NULL) {
1525 dev_printk(KERN_ERR, &mp->dev->dev,
1526 "can't allocate tx ring (%d bytes)\n", size);
1527 goto out;
1528 }
1529 memset(txq->tx_desc_area, 0, size);
1987 1530
1988 if (mp->tx_sram_size > 0) 1531 txq->tx_desc_area_size = size;
1989 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); 1532 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1533 GFP_KERNEL);
1534 if (txq->tx_skb == NULL) {
1535 dev_printk(KERN_ERR, &mp->dev->dev,
1536 "can't allocate tx skb ring\n");
1537 goto out_free;
1538 }
1539
1540 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1541 for (i = 0; i < txq->tx_ring_size; i++) {
1542 int nexti = (i + 1) % txq->tx_ring_size;
1543 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1544 nexti * sizeof(struct tx_desc);
1545 }
1990 1546
1991 return 0; 1547 return 0;
1992 1548
1993out:
1994 free_netdev(dev);
1995 1549
1996 return err; 1550out_free:
1551 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1552 iounmap(txq->tx_desc_area);
1553 else
1554 dma_free_coherent(NULL, size,
1555 txq->tx_desc_area,
1556 txq->tx_desc_dma);
1557
1558out:
1559 return -ENOMEM;
1997} 1560}
1998 1561
1999static int mv643xx_eth_remove(struct platform_device *pdev) 1562static void txq_reclaim(struct tx_queue *txq, int force)
2000{ 1563{
2001 struct net_device *dev = platform_get_drvdata(pdev); 1564 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1565 unsigned long flags;
2002 1566
2003 unregister_netdev(dev); 1567 spin_lock_irqsave(&mp->lock, flags);
2004 flush_scheduled_work(); 1568 while (txq->tx_desc_count > 0) {
1569 int tx_index;
1570 struct tx_desc *desc;
1571 u32 cmd_sts;
1572 struct sk_buff *skb;
1573 dma_addr_t addr;
1574 int count;
1575
1576 tx_index = txq->tx_used_desc;
1577 desc = &txq->tx_desc_area[tx_index];
1578 cmd_sts = desc->cmd_sts;
2005 1579
2006 free_netdev(dev); 1580 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
2007 platform_set_drvdata(pdev, NULL); 1581 break;
2008 return 0;
2009}
2010 1582
2011static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp, 1583 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
2012 struct mbus_dram_target_info *dram) 1584 txq->tx_desc_count--;
2013{
2014 void __iomem *base = msp->eth_base;
2015 u32 win_enable;
2016 u32 win_protect;
2017 int i;
2018 1585
2019 for (i = 0; i < 6; i++) { 1586 addr = desc->buf_ptr;
2020 writel(0, base + WINDOW_BASE(i)); 1587 count = desc->byte_cnt;
2021 writel(0, base + WINDOW_SIZE(i)); 1588 skb = txq->tx_skb[tx_index];
2022 if (i < 4) 1589 txq->tx_skb[tx_index] = NULL;
2023 writel(0, base + WINDOW_REMAP_HIGH(i));
2024 }
2025 1590
2026 win_enable = 0x3f; 1591 if (cmd_sts & ERROR_SUMMARY) {
2027 win_protect = 0; 1592 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1593 mp->dev->stats.tx_errors++;
1594 }
2028 1595
2029 for (i = 0; i < dram->num_cs; i++) { 1596 /*
2030 struct mbus_dram_window *cs = dram->cs + i; 1597 * Drop mp->lock while we free the skb.
1598 */
1599 spin_unlock_irqrestore(&mp->lock, flags);
2031 1600
2032 writel((cs->base & 0xffff0000) | 1601 if (cmd_sts & TX_FIRST_DESC)
2033 (cs->mbus_attr << 8) | 1602 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
2034 dram->mbus_dram_target_id, base + WINDOW_BASE(i)); 1603 else
2035 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); 1604 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
2036 1605
2037 win_enable &= ~(1 << i); 1606 if (skb)
2038 win_protect |= 3 << (2 * i); 1607 dev_kfree_skb_irq(skb);
2039 }
2040 1608
2041 writel(win_enable, base + WINDOW_BAR_ENABLE); 1609 spin_lock_irqsave(&mp->lock, flags);
2042 msp->win_protect = win_protect; 1610 }
1611 spin_unlock_irqrestore(&mp->lock, flags);
2043} 1612}
2044 1613
2045static int mv643xx_eth_shared_probe(struct platform_device *pdev) 1614static void txq_deinit(struct tx_queue *txq)
2046{ 1615{
2047 static int mv643xx_version_printed = 0; 1616 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2048 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2049 struct mv643xx_shared_private *msp;
2050 struct resource *res;
2051 int ret;
2052 1617
2053 if (!mv643xx_version_printed++) 1618 txq_disable(txq);
2054 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); 1619 txq_reclaim(txq, 1);
2055 1620
2056 ret = -EINVAL; 1621 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2057 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2058 if (res == NULL)
2059 goto out;
2060 1622
2061 ret = -ENOMEM; 1623 if (txq->index == mp->txq_primary &&
2062 msp = kmalloc(sizeof(*msp), GFP_KERNEL); 1624 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2063 if (msp == NULL) 1625 iounmap(txq->tx_desc_area);
2064 goto out; 1626 else
2065 memset(msp, 0, sizeof(*msp)); 1627 dma_free_coherent(NULL, txq->tx_desc_area_size,
1628 txq->tx_desc_area, txq->tx_desc_dma);
2066 1629
2067 msp->eth_base = ioremap(res->start, res->end - res->start + 1); 1630 kfree(txq->tx_skb);
2068 if (msp->eth_base == NULL) 1631}
2069 goto out_free;
2070 1632
2071 spin_lock_init(&msp->phy_lock);
2072 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2073 1633
2074 platform_set_drvdata(pdev, msp); 1634/* netdev ops and related ***************************************************/
1635static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1636{
1637 u32 pscr_o;
1638 u32 pscr_n;
2075 1639
2076 /* 1640 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2077 * (Re-)program MBUS remapping windows if we are asked to.
2078 */
2079 if (pd != NULL && pd->dram != NULL)
2080 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2081 1641
2082 return 0; 1642 /* clear speed, duplex and rx buffer size fields */
1643 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1644 SET_GMII_SPEED_TO_1000 |
1645 SET_FULL_DUPLEX_MODE |
1646 MAX_RX_PACKET_MASK);
2083 1647
2084out_free: 1648 if (speed == SPEED_1000) {
2085 kfree(msp); 1649 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
2086out: 1650 } else {
2087 return ret; 1651 if (speed == SPEED_100)
2088} 1652 pscr_n |= SET_MII_SPEED_TO_100;
1653 pscr_n |= MAX_RX_PACKET_1522BYTE;
1654 }
2089 1655
2090static int mv643xx_eth_shared_remove(struct platform_device *pdev) 1656 if (duplex == DUPLEX_FULL)
2091{ 1657 pscr_n |= SET_FULL_DUPLEX_MODE;
2092 struct mv643xx_shared_private *msp = platform_get_drvdata(pdev);
2093 1658
2094 iounmap(msp->eth_base); 1659 if (pscr_n != pscr_o) {
2095 kfree(msp); 1660 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1661 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1662 else {
1663 int i;
2096 1664
2097 return 0; 1665 for (i = 0; i < 8; i++)
1666 if (mp->txq_mask & (1 << i))
1667 txq_disable(mp->txq + i);
1668
1669 pscr_o &= ~SERIAL_PORT_ENABLE;
1670 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1671 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1672 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1673
1674 for (i = 0; i < 8; i++)
1675 if (mp->txq_mask & (1 << i))
1676 txq_enable(mp->txq + i);
1677 }
1678 }
2098} 1679}
2099 1680
2100static void mv643xx_eth_shutdown(struct platform_device *pdev) 1681static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2101{ 1682{
2102 struct net_device *dev = platform_get_drvdata(pdev); 1683 struct net_device *dev = (struct net_device *)dev_id;
2103 struct mv643xx_private *mp = netdev_priv(dev); 1684 struct mv643xx_eth_private *mp = netdev_priv(dev);
2104 unsigned int port_num = mp->port_num; 1685 u32 int_cause;
1686 u32 int_cause_ext;
1687 u32 txq_active;
1688
1689 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1690 (INT_TX_END | INT_RX | INT_EXT);
1691 if (int_cause == 0)
1692 return IRQ_NONE;
2105 1693
2106 /* Mask all interrupts on ethernet port */ 1694 int_cause_ext = 0;
2107 wrl(mp, INTERRUPT_MASK_REG(port_num), 0); 1695 if (int_cause & INT_EXT) {
2108 rdl(mp, INTERRUPT_MASK_REG(port_num)); 1696 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1697 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1698 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1699 }
2109 1700
2110 eth_port_reset(mp); 1701 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
2111} 1702 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
1703 int i;
2112 1704
2113static struct platform_driver mv643xx_eth_driver = { 1705 if (mp->phy_addr != -1) {
2114 .probe = mv643xx_eth_probe, 1706 struct ethtool_cmd cmd;
2115 .remove = mv643xx_eth_remove,
2116 .shutdown = mv643xx_eth_shutdown,
2117 .driver = {
2118 .name = MV643XX_ETH_NAME,
2119 .owner = THIS_MODULE,
2120 },
2121};
2122 1707
2123static struct platform_driver mv643xx_eth_shared_driver = { 1708 mii_ethtool_gset(&mp->mii, &cmd);
2124 .probe = mv643xx_eth_shared_probe, 1709 update_pscr(mp, cmd.speed, cmd.duplex);
2125 .remove = mv643xx_eth_shared_remove, 1710 }
2126 .driver = {
2127 .name = MV643XX_ETH_SHARED_NAME,
2128 .owner = THIS_MODULE,
2129 },
2130};
2131 1711
2132/* 1712 for (i = 0; i < 8; i++)
2133 * mv643xx_init_module 1713 if (mp->txq_mask & (1 << i))
2134 * 1714 txq_enable(mp->txq + i);
2135 * Registers the network drivers into the Linux kernel
2136 *
2137 * Input : N/A
2138 *
2139 * Output : N/A
2140 */
2141static int __init mv643xx_init_module(void)
2142{
2143 int rc;
2144 1715
2145 rc = platform_driver_register(&mv643xx_eth_shared_driver); 1716 if (!netif_carrier_ok(dev)) {
2146 if (!rc) { 1717 netif_carrier_on(dev);
2147 rc = platform_driver_register(&mv643xx_eth_driver); 1718 __txq_maybe_wake(mp->txq + mp->txq_primary);
2148 if (rc) 1719 }
2149 platform_driver_unregister(&mv643xx_eth_shared_driver); 1720 } else if (netif_carrier_ok(dev)) {
1721 netif_stop_queue(dev);
1722 netif_carrier_off(dev);
1723 }
2150 } 1724 }
2151 return rc;
2152}
2153 1725
2154/* 1726 /*
2155 * mv643xx_cleanup_module 1727 * RxBuffer or RxError set for any of the 8 queues?
2156 * 1728 */
2157 * Registers the network drivers into the Linux kernel 1729#ifdef MV643XX_ETH_NAPI
2158 * 1730 if (int_cause & INT_RX) {
2159 * Input : N/A 1731 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2160 * 1732 rdl(mp, INT_MASK(mp->port_num));
2161 * Output : N/A
2162 */
2163static void __exit mv643xx_cleanup_module(void)
2164{
2165 platform_driver_unregister(&mv643xx_eth_driver);
2166 platform_driver_unregister(&mv643xx_eth_shared_driver);
2167}
2168 1733
2169module_init(mv643xx_init_module); 1734 netif_rx_schedule(dev, &mp->napi);
2170module_exit(mv643xx_cleanup_module); 1735 }
1736#else
1737 if (int_cause & INT_RX) {
1738 int i;
2171 1739
2172MODULE_LICENSE("GPL"); 1740 for (i = 7; i >= 0; i--)
2173MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" 1741 if (mp->rxq_mask & (1 << i))
2174 " and Dale Farnsworth"); 1742 rxq_process(mp->rxq + i, INT_MAX);
2175MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); 1743 }
2176MODULE_ALIAS("platform:" MV643XX_ETH_NAME); 1744#endif
2177MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2178 1745
2179/* 1746 txq_active = rdl(mp, TXQ_COMMAND(mp->port_num));
2180 * The second part is the low level driver of the gigE ethernet ports.
2181 */
2182 1747
2183/* 1748 /*
2184 * Marvell's Gigabit Ethernet controller low level driver 1749 * TxBuffer or TxError set for any of the 8 queues?
2185 * 1750 */
2186 * DESCRIPTION: 1751 if (int_cause_ext & INT_EXT_TX) {
2187 * This file introduce low level API to Marvell's Gigabit Ethernet 1752 int i;
2188 * controller. This Gigabit Ethernet Controller driver API controls
2189 * 1) Operations (i.e. port init, start, reset etc').
2190 * 2) Data flow (i.e. port send, receive etc').
2191 * Each Gigabit Ethernet port is controlled via
2192 * struct mv643xx_private.
2193 * This struct includes user configuration information as well as
2194 * driver internal data needed for its operations.
2195 *
2196 * Supported Features:
2197 * - This low level driver is OS independent. Allocating memory for
2198 * the descriptor rings and buffers are not within the scope of
2199 * this driver.
2200 * - The user is free from Rx/Tx queue managing.
2201 * - This low level driver introduce functionality API that enable
2202 * the to operate Marvell's Gigabit Ethernet Controller in a
2203 * convenient way.
2204 * - Simple Gigabit Ethernet port operation API.
2205 * - Simple Gigabit Ethernet port data flow API.
2206 * - Data flow and operation API support per queue functionality.
2207 * - Support cached descriptors for better performance.
2208 * - Enable access to all four DRAM banks and internal SRAM memory
2209 * spaces.
2210 * - PHY access and control API.
2211 * - Port control register configuration API.
2212 * - Full control over Unicast and Multicast MAC configurations.
2213 *
2214 * Operation flow:
2215 *
2216 * Initialization phase
2217 * This phase complete the initialization of the the
2218 * mv643xx_private struct.
2219 * User information regarding port configuration has to be set
2220 * prior to calling the port initialization routine.
2221 *
2222 * In this phase any port Tx/Rx activity is halted, MIB counters
2223 * are cleared, PHY address is set according to user parameter and
2224 * access to DRAM and internal SRAM memory spaces.
2225 *
2226 * Driver ring initialization
2227 * Allocating memory for the descriptor rings and buffers is not
2228 * within the scope of this driver. Thus, the user is required to
2229 * allocate memory for the descriptors ring and buffers. Those
2230 * memory parameters are used by the Rx and Tx ring initialization
2231 * routines in order to curve the descriptor linked list in a form
2232 * of a ring.
2233 * Note: Pay special attention to alignment issues when using
2234 * cached descriptors/buffers. In this phase the driver store
2235 * information in the mv643xx_private struct regarding each queue
2236 * ring.
2237 *
2238 * Driver start
2239 * This phase prepares the Ethernet port for Rx and Tx activity.
2240 * It uses the information stored in the mv643xx_private struct to
2241 * initialize the various port registers.
2242 *
2243 * Data flow:
2244 * All packet references to/from the driver are done using
2245 * struct pkt_info.
2246 * This struct is a unified struct used with Rx and Tx operations.
2247 * This way the user is not required to be familiar with neither
2248 * Tx nor Rx descriptors structures.
2249 * The driver's descriptors rings are management by indexes.
2250 * Those indexes controls the ring resources and used to indicate
2251 * a SW resource error:
2252 * 'current'
2253 * This index points to the current available resource for use. For
2254 * example in Rx process this index will point to the descriptor
2255 * that will be passed to the user upon calling the receive
2256 * routine. In Tx process, this index will point to the descriptor
2257 * that will be assigned with the user packet info and transmitted.
2258 * 'used'
2259 * This index points to the descriptor that need to restore its
2260 * resources. For example in Rx process, using the Rx buffer return
2261 * API will attach the buffer returned in packet info to the
2262 * descriptor pointed by 'used'. In Tx process, using the Tx
2263 * descriptor return will merely return the user packet info with
2264 * the command status of the transmitted buffer pointed by the
2265 * 'used' index. Nevertheless, it is essential to use this routine
2266 * to update the 'used' index.
2267 * 'first'
2268 * This index supports Tx Scatter-Gather. It points to the first
2269 * descriptor of a packet assembled of multiple buffers. For
2270 * example when in middle of Such packet we have a Tx resource
2271 * error the 'curr' index get the value of 'first' to indicate
2272 * that the ring returned to its state before trying to transmit
2273 * this packet.
2274 *
2275 * Receive operation:
2276 * The eth_port_receive API set the packet information struct,
2277 * passed by the caller, with received information from the
2278 * 'current' SDMA descriptor.
2279 * It is the user responsibility to return this resource back
2280 * to the Rx descriptor ring to enable the reuse of this source.
2281 * Return Rx resource is done using the eth_rx_return_buff API.
2282 *
2283 * Prior to calling the initialization routine eth_port_init() the user
2284 * must set the following fields under mv643xx_private struct:
2285 * port_num User Ethernet port number.
2286 * port_config User port configuration value.
2287 * port_config_extend User port config extend value.
2288 * port_sdma_config User port SDMA config value.
2289 * port_serial_control User port serial control value.
2290 *
2291 * This driver data flow is done using the struct pkt_info which
2292 * is a unified struct for Rx and Tx operations:
2293 *
2294 * byte_cnt Tx/Rx descriptor buffer byte count.
2295 * l4i_chk CPU provided TCP Checksum. For Tx operation
2296 * only.
2297 * cmd_sts Tx/Rx descriptor command status.
2298 * buf_ptr Tx/Rx descriptor buffer pointer.
2299 * return_info Tx/Rx user resource return information.
2300 */
2301 1753
2302/* Ethernet Port routines */ 1754 for (i = 0; i < 8; i++)
2303static void eth_port_set_filter_table_entry(struct mv643xx_private *mp, 1755 if (mp->txq_mask & (1 << i))
2304 int table, unsigned char entry); 1756 txq_reclaim(mp->txq + i, 0);
1757 }
2305 1758
2306/* 1759 /*
2307 * eth_port_init - Initialize the Ethernet port driver 1760 * Any TxEnd interrupts?
2308 * 1761 */
2309 * DESCRIPTION: 1762 if (int_cause & INT_TX_END) {
2310 * This function prepares the ethernet port to start its activity: 1763 int i;
2311 * 1) Completes the ethernet port driver struct initialization toward port 1764
2312 * start routine. 1765 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
2313 * 2) Resets the device to a quiescent state in case of warm reboot. 1766 for (i = 0; i < 8; i++) {
2314 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. 1767 struct tx_queue *txq = mp->txq + i;
2315 * 4) Clean MAC tables. The reset status of those tables is unknown. 1768 if (txq->tx_desc_count && !((txq_active >> i) & 1))
2316 * 5) Set PHY address. 1769 txq_enable(txq);
2317 * Note: Call this routine prior to eth_port_start routine and after 1770 }
2318 * setting user values in the user fields of Ethernet port control 1771 }
2319 * struct.
2320 *
2321 * INPUT:
2322 * struct mv643xx_private *mp Ethernet port control struct
2323 *
2324 * OUTPUT:
2325 * See description.
2326 *
2327 * RETURN:
2328 * None.
2329 */
2330static void eth_port_init(struct mv643xx_private *mp)
2331{
2332 mp->rx_resource_err = 0;
2333 1772
2334 eth_port_reset(mp); 1773 /*
1774 * Enough space again in the primary TX queue for a full packet?
1775 */
1776 if (int_cause_ext & INT_EXT_TX) {
1777 struct tx_queue *txq = mp->txq + mp->txq_primary;
1778 __txq_maybe_wake(txq);
1779 }
2335 1780
2336 eth_port_init_mac_tables(mp); 1781 return IRQ_HANDLED;
2337} 1782}
2338 1783
2339/* 1784static void phy_reset(struct mv643xx_eth_private *mp)
2340 * eth_port_start - Start the Ethernet port activity.
2341 *
2342 * DESCRIPTION:
2343 * This routine prepares the Ethernet port for Rx and Tx activity:
2344 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2345 * has been initialized a descriptor's ring (using
2346 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2347 * 2. Initialize and enable the Ethernet configuration port by writing to
2348 * the port's configuration and command registers.
2349 * 3. Initialize and enable the SDMA by writing to the SDMA's
2350 * configuration and command registers. After completing these steps,
2351 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2352 *
2353 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2354 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2355 * and ether_init_rx_desc_ring for Rx queues).
2356 *
2357 * INPUT:
2358 * dev - a pointer to the required interface
2359 *
2360 * OUTPUT:
2361 * Ethernet port is ready to receive and transmit.
2362 *
2363 * RETURN:
2364 * None.
2365 */
2366static void eth_port_start(struct net_device *dev)
2367{ 1785{
2368 struct mv643xx_private *mp = netdev_priv(dev); 1786 unsigned int data;
2369 unsigned int port_num = mp->port_num;
2370 int tx_curr_desc, rx_curr_desc;
2371 u32 pscr;
2372 struct ethtool_cmd ethtool_cmd;
2373
2374 /* Assignment of Tx CTRP of given queue */
2375 tx_curr_desc = mp->tx_curr_desc_q;
2376 wrl(mp, TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2377 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
2378
2379 /* Assignment of Rx CRDP of given queue */
2380 rx_curr_desc = mp->rx_curr_desc_q;
2381 wrl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2382 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
2383 1787
2384 /* Add the assigned Ethernet address to the port's address table */ 1788 smi_reg_read(mp, mp->phy_addr, 0, &data);
2385 eth_port_uc_addr_set(mp, dev->dev_addr); 1789 data |= 0x8000;
1790 smi_reg_write(mp, mp->phy_addr, 0, data);
2386 1791
2387 /* Assign port configuration and command. */ 1792 do {
2388 wrl(mp, PORT_CONFIG_REG(port_num), 1793 udelay(1);
2389 PORT_CONFIG_DEFAULT_VALUE); 1794 smi_reg_read(mp, mp->phy_addr, 0, &data);
2390 1795 } while (data & 0x8000);
2391 wrl(mp, PORT_CONFIG_EXTEND_REG(port_num), 1796}
2392 PORT_CONFIG_EXTEND_DEFAULT_VALUE);
2393 1797
2394 pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); 1798static void port_start(struct mv643xx_eth_private *mp)
1799{
1800 u32 pscr;
1801 int i;
2395 1802
1803 /*
1804 * Configure basic link parameters.
1805 */
1806 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2396 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); 1807 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
2397 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); 1808 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2398
2399 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | 1809 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
2400 DISABLE_AUTO_NEG_SPEED_GMII | 1810 DISABLE_AUTO_NEG_SPEED_GMII |
2401 DISABLE_AUTO_NEG_FOR_DUPLX | 1811 DISABLE_AUTO_NEG_FOR_DUPLEX |
2402 DO_NOT_FORCE_LINK_FAIL | 1812 DO_NOT_FORCE_LINK_FAIL |
2403 SERIAL_PORT_CONTROL_RESERVED; 1813 SERIAL_PORT_CONTROL_RESERVED;
1814 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1815 pscr |= SERIAL_PORT_ENABLE;
1816 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2404 1817
2405 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); 1818 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
2406 1819
2407 pscr |= SERIAL_PORT_ENABLE; 1820 /*
2408 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); 1821 * Perform PHY reset, if there is a PHY.
1822 */
1823 if (mp->phy_addr != -1) {
1824 struct ethtool_cmd cmd;
2409 1825
2410 /* Assign port SDMA configuration */ 1826 mv643xx_eth_get_settings(mp->dev, &cmd);
2411 wrl(mp, SDMA_CONFIG_REG(port_num), 1827 phy_reset(mp);
2412 PORT_SDMA_CONFIG_DEFAULT_VALUE); 1828 mv643xx_eth_set_settings(mp->dev, &cmd);
1829 }
2413 1830
2414 /* Enable port Rx. */ 1831 /*
2415 mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED); 1832 * Configure TX path and queues.
1833 */
1834 tx_set_rate(mp, 1000000000, 16777216);
1835 for (i = 0; i < 8; i++) {
1836 struct tx_queue *txq = mp->txq + i;
1837 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
1838 u32 addr;
2416 1839
2417 /* Disable port bandwidth limits by clearing MTU register */ 1840 if ((mp->txq_mask & (1 << i)) == 0)
2418 wrl(mp, MAXIMUM_TRANSMIT_UNIT(port_num), 0); 1841 continue;
2419 1842
2420 /* save phy settings across reset */ 1843 addr = (u32)txq->tx_desc_dma;
2421 mv643xx_get_settings(dev, &ethtool_cmd); 1844 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
2422 ethernet_phy_reset(mp); 1845 wrl(mp, off, addr);
2423 mv643xx_set_settings(dev, &ethtool_cmd);
2424}
2425 1846
2426/* 1847 txq_set_rate(txq, 1000000000, 16777216);
2427 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers 1848 txq_set_fixed_prio_mode(txq);
2428 */ 1849 }
2429static void eth_port_uc_addr_set(struct mv643xx_private *mp,
2430 unsigned char *p_addr)
2431{
2432 unsigned int port_num = mp->port_num;
2433 unsigned int mac_h;
2434 unsigned int mac_l;
2435 int table;
2436 1850
2437 mac_l = (p_addr[4] << 8) | (p_addr[5]); 1851 /*
2438 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | 1852 * Add configured unicast address to address filter table.
2439 (p_addr[3] << 0); 1853 */
1854 uc_addr_set(mp, mp->dev->dev_addr);
2440 1855
2441 wrl(mp, MAC_ADDR_LOW(port_num), mac_l); 1856 /*
2442 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h); 1857 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1858 * frames to RX queue #0.
1859 */
1860 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
2443 1861
2444 /* Accept frames with this address */ 1862 /*
2445 table = DA_FILTER_UNICAST_TABLE_BASE(port_num); 1863 * Treat BPDUs as normal multicasts, and disable partition mode.
2446 eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f); 1864 */
2447} 1865 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
2448 1866
2449/* 1867 /*
2450 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers 1868 * Enable the receive queues.
2451 */ 1869 */
2452static void eth_port_uc_addr_get(struct mv643xx_private *mp, 1870 for (i = 0; i < 8; i++) {
2453 unsigned char *p_addr) 1871 struct rx_queue *rxq = mp->rxq + i;
2454{ 1872 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
2455 unsigned int port_num = mp->port_num; 1873 u32 addr;
2456 unsigned int mac_h; 1874
2457 unsigned int mac_l; 1875 if ((mp->rxq_mask & (1 << i)) == 0)
1876 continue;
2458 1877
2459 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num)); 1878 addr = (u32)rxq->rx_desc_dma;
2460 mac_l = rdl(mp, MAC_ADDR_LOW(port_num)); 1879 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1880 wrl(mp, off, addr);
2461 1881
2462 p_addr[0] = (mac_h >> 24) & 0xff; 1882 rxq_enable(rxq);
2463 p_addr[1] = (mac_h >> 16) & 0xff; 1883 }
2464 p_addr[2] = (mac_h >> 8) & 0xff;
2465 p_addr[3] = mac_h & 0xff;
2466 p_addr[4] = (mac_l >> 8) & 0xff;
2467 p_addr[5] = mac_l & 0xff;
2468} 1884}
2469 1885
2470/* 1886static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2471 * The entries in each table are indexed by a hash of a packet's MAC
2472 * address. One bit in each entry determines whether the packet is
2473 * accepted. There are 4 entries (each 8 bits wide) in each register
2474 * of the table. The bits in each entry are defined as follows:
2475 * 0 Accept=1, Drop=0
2476 * 3-1 Queue (ETH_Q0=0)
2477 * 7-4 Reserved = 0;
2478 */
2479static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
2480 int table, unsigned char entry)
2481{ 1887{
2482 unsigned int table_reg; 1888 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2483 unsigned int tbl_offset; 1889 u32 val;
2484 unsigned int reg_offset; 1890
1891 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1892 if (mp->shared->extended_rx_coal_limit) {
1893 if (coal > 0xffff)
1894 coal = 0xffff;
1895 val &= ~0x023fff80;
1896 val |= (coal & 0x8000) << 10;
1897 val |= (coal & 0x7fff) << 7;
1898 } else {
1899 if (coal > 0x3fff)
1900 coal = 0x3fff;
1901 val &= ~0x003fff00;
1902 val |= (coal & 0x3fff) << 8;
1903 }
1904 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1905}
2485 1906
2486 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ 1907static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2487 reg_offset = entry % 4; /* Entry offset within the register */ 1908{
1909 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2488 1910
2489 /* Set "accepts frame bit" at specified table entry */ 1911 if (coal > 0x3fff)
2490 table_reg = rdl(mp, table + tbl_offset); 1912 coal = 0x3fff;
2491 table_reg |= 0x01 << (8 * reg_offset); 1913 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2492 wrl(mp, table + tbl_offset, table_reg);
2493} 1914}
2494 1915
2495/* 1916static int mv643xx_eth_open(struct net_device *dev)
2496 * eth_port_mc_addr - Multicast address settings.
2497 *
2498 * The MV device supports multicast using two tables:
2499 * 1) Special Multicast Table for MAC addresses of the form
2500 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2501 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2502 * Table entries in the DA-Filter table.
2503 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2504 * is used as an index to the Other Multicast Table entries in the
2505 * DA-Filter table. This function calculates the CRC-8bit value.
2506 * In either case, eth_port_set_filter_table_entry() is then called
2507 * to set to set the actual table entry.
2508 */
2509static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr)
2510{ 1917{
2511 unsigned int port_num = mp->port_num; 1918 struct mv643xx_eth_private *mp = netdev_priv(dev);
2512 unsigned int mac_h; 1919 int err;
2513 unsigned int mac_l;
2514 unsigned char crc_result = 0;
2515 int table;
2516 int mac_array[48];
2517 int crc[8];
2518 int i; 1920 int i;
2519 1921
2520 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && 1922 wrl(mp, INT_CAUSE(mp->port_num), 0);
2521 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { 1923 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2522 table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num); 1924 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2523 eth_port_set_filter_table_entry(mp, table, p_addr[5]); 1925
2524 return; 1926 err = request_irq(dev->irq, mv643xx_eth_irq,
1927 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1928 dev->name, dev);
1929 if (err) {
1930 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1931 return -EAGAIN;
2525 } 1932 }
2526 1933
2527 /* Calculate CRC-8 out of the given address */ 1934 init_mac_tables(mp);
2528 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2529 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2530 (p_addr[4] << 8) | (p_addr[5] << 0);
2531
2532 for (i = 0; i < 32; i++)
2533 mac_array[i] = (mac_l >> i) & 0x1;
2534 for (i = 32; i < 48; i++)
2535 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2536
2537 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2538 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2539 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2540 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2541 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2542
2543 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2544 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2545 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2546 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2547 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2548 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2549 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2550
2551 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2552 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2553 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2554 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2555 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2556 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2557
2558 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2559 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2560 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2561 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2562 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2563 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2564
2565 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2566 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2567 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2568 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2569 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2570 mac_array[3] ^ mac_array[2];
2571
2572 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2573 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2574 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2575 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2576 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2577 mac_array[4] ^ mac_array[3];
2578
2579 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2580 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2581 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2582 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2583 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2584 mac_array[4];
2585
2586 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2587 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2588 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2589 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2590 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2591 1935
2592 for (i = 0; i < 8; i++) 1936 for (i = 0; i < 8; i++) {
2593 crc_result = crc_result | (crc[i] << i); 1937 if ((mp->rxq_mask & (1 << i)) == 0)
1938 continue;
2594 1939
2595 table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num); 1940 err = rxq_init(mp, i);
2596 eth_port_set_filter_table_entry(mp, table, crc_result); 1941 if (err) {
2597} 1942 while (--i >= 0)
1943 if (mp->rxq_mask & (1 << i))
1944 rxq_deinit(mp->rxq + i);
1945 goto out;
1946 }
2598 1947
2599/* 1948 rxq_refill(mp->rxq + i);
2600 * Set the entire multicast list based on dev->mc_list. 1949 }
2601 */
2602static void eth_port_set_multicast_list(struct net_device *dev)
2603{
2604 1950
2605 struct dev_mc_list *mc_list; 1951 for (i = 0; i < 8; i++) {
2606 int i; 1952 if ((mp->txq_mask & (1 << i)) == 0)
2607 int table_index; 1953 continue;
2608 struct mv643xx_private *mp = netdev_priv(dev);
2609 unsigned int eth_port_num = mp->port_num;
2610 1954
2611 /* If the device is in promiscuous mode or in all multicast mode, 1955 err = txq_init(mp, i);
2612 * we will fully populate both multicast tables with accept. 1956 if (err) {
2613 * This is guaranteed to yield a match on all multicast addresses... 1957 while (--i >= 0)
2614 */ 1958 if (mp->txq_mask & (1 << i))
2615 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { 1959 txq_deinit(mp->txq + i);
2616 for (table_index = 0; table_index <= 0xFC; table_index += 4) { 1960 goto out_free;
2617 /* Set all entries in DA filter special multicast
2618 * table (Ex_dFSMT)
2619 * Set for ETH_Q0 for now
2620 * Bits
2621 * 0 Accept=1, Drop=0
2622 * 3-1 Queue ETH_Q0=0
2623 * 7-4 Reserved = 0;
2624 */
2625 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2626
2627 /* Set all entries in DA filter other multicast
2628 * table (Ex_dFOMT)
2629 * Set for ETH_Q0 for now
2630 * Bits
2631 * 0 Accept=1, Drop=0
2632 * 3-1 Queue ETH_Q0=0
2633 * 7-4 Reserved = 0;
2634 */
2635 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2636 } 1961 }
2637 return;
2638 } 1962 }
2639 1963
2640 /* We will clear out multicast tables every time we get the list. 1964#ifdef MV643XX_ETH_NAPI
2641 * Then add the entire new list... 1965 napi_enable(&mp->napi);
2642 */ 1966#endif
2643 for (table_index = 0; table_index <= 0xFC; table_index += 4) { 1967
2644 /* Clear DA filter special multicast table (Ex_dFSMT) */ 1968 port_start(mp);
2645 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2646 (eth_port_num) + table_index, 0);
2647
2648 /* Clear DA filter other multicast table (Ex_dFOMT) */
2649 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2650 (eth_port_num) + table_index, 0);
2651 }
2652 1969
2653 /* Get pointer to net_device multicast list and add each one... */ 1970 set_rx_coal(mp, 0);
2654 for (i = 0, mc_list = dev->mc_list; 1971 set_tx_coal(mp, 0);
2655 (i < 256) && (mc_list != NULL) && (i < dev->mc_count); 1972
2656 i++, mc_list = mc_list->next) 1973 wrl(mp, INT_MASK_EXT(mp->port_num),
2657 if (mc_list->dmi_addrlen == 6) 1974 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2658 eth_port_mc_addr(mp, mc_list->dmi_addr); 1975
1976 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1977
1978 return 0;
1979
1980
1981out_free:
1982 for (i = 0; i < 8; i++)
1983 if (mp->rxq_mask & (1 << i))
1984 rxq_deinit(mp->rxq + i);
1985out:
1986 free_irq(dev->irq, dev);
1987
1988 return err;
2659} 1989}
2660 1990
2661/* 1991static void port_reset(struct mv643xx_eth_private *mp)
2662 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables 1992{
2663 * 1993 unsigned int data;
2664 * DESCRIPTION: 1994 int i;
2665 * Go through all the DA filter tables (Unicast, Special Multicast & 1995
2666 * Other Multicast) and set each entry to 0. 1996 for (i = 0; i < 8; i++) {
2667 * 1997 if (mp->rxq_mask & (1 << i))
2668 * INPUT: 1998 rxq_disable(mp->rxq + i);
2669 * struct mv643xx_private *mp Ethernet Port. 1999 if (mp->txq_mask & (1 << i))
2670 * 2000 txq_disable(mp->txq + i);
2671 * OUTPUT:
2672 * Multicast and Unicast packets are rejected.
2673 *
2674 * RETURN:
2675 * None.
2676 */
2677static void eth_port_init_mac_tables(struct mv643xx_private *mp)
2678{
2679 unsigned int port_num = mp->port_num;
2680 int table_index;
2681
2682 /* Clear DA filter unicast table (Ex_dFUT) */
2683 for (table_index = 0; table_index <= 0xC; table_index += 4)
2684 wrl(mp, DA_FILTER_UNICAST_TABLE_BASE(port_num) +
2685 table_index, 0);
2686
2687 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2688 /* Clear DA filter special multicast table (Ex_dFSMT) */
2689 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num) +
2690 table_index, 0);
2691 /* Clear DA filter other multicast table (Ex_dFOMT) */
2692 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num) +
2693 table_index, 0);
2694 } 2001 }
2002 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
2003 udelay(10);
2004
2005 /* Reset the Enable bit in the Configuration Register */
2006 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2007 data &= ~(SERIAL_PORT_ENABLE |
2008 DO_NOT_FORCE_LINK_FAIL |
2009 FORCE_LINK_PASS);
2010 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2695} 2011}
2696 2012
2697/* 2013static int mv643xx_eth_stop(struct net_device *dev)
2698 * eth_clear_mib_counters - Clear all MIB counters
2699 *
2700 * DESCRIPTION:
2701 * This function clears all MIB counters of a specific ethernet port.
2702 * A read from the MIB counter will reset the counter.
2703 *
2704 * INPUT:
2705 * struct mv643xx_private *mp Ethernet Port.
2706 *
2707 * OUTPUT:
2708 * After reading all MIB counters, the counters resets.
2709 *
2710 * RETURN:
2711 * MIB counter value.
2712 *
2713 */
2714static void eth_clear_mib_counters(struct mv643xx_private *mp)
2715{ 2014{
2716 unsigned int port_num = mp->port_num; 2015 struct mv643xx_eth_private *mp = netdev_priv(dev);
2717 int i; 2016 int i;
2718 2017
2719 /* Perform dummy reads from MIB counters */ 2018 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2720 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; 2019 rdl(mp, INT_MASK(mp->port_num));
2721 i += 4) 2020
2722 rdl(mp, MIB_COUNTERS_BASE(port_num) + i); 2021#ifdef MV643XX_ETH_NAPI
2022 napi_disable(&mp->napi);
2023#endif
2024 netif_carrier_off(dev);
2025 netif_stop_queue(dev);
2026
2027 free_irq(dev->irq, dev);
2028
2029 port_reset(mp);
2030 mib_counters_update(mp);
2031
2032 for (i = 0; i < 8; i++) {
2033 if (mp->rxq_mask & (1 << i))
2034 rxq_deinit(mp->rxq + i);
2035 if (mp->txq_mask & (1 << i))
2036 txq_deinit(mp->txq + i);
2037 }
2038
2039 return 0;
2723} 2040}
2724 2041
2725static inline u32 read_mib(struct mv643xx_private *mp, int offset) 2042static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2726{ 2043{
2727 return rdl(mp, MIB_COUNTERS_BASE(mp->port_num) + offset); 2044 struct mv643xx_eth_private *mp = netdev_priv(dev);
2045
2046 if (mp->phy_addr != -1)
2047 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2048
2049 return -EOPNOTSUPP;
2728} 2050}
2729 2051
2730static void eth_update_mib_counters(struct mv643xx_private *mp) 2052static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2731{ 2053{
2732 struct mv643xx_mib_counters *p = &mp->mib_counters; 2054 struct mv643xx_eth_private *mp = netdev_priv(dev);
2733 int offset;
2734 2055
2735 p->good_octets_received += 2056 if (new_mtu < 64 || new_mtu > 9500)
2736 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); 2057 return -EINVAL;
2737 p->good_octets_received +=
2738 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2739 2058
2740 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; 2059 dev->mtu = new_mtu;
2741 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; 2060 tx_set_rate(mp, 1000000000, 16777216);
2742 offset += 4)
2743 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
2744 2061
2745 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); 2062 if (!netif_running(dev))
2746 p->good_octets_sent += 2063 return 0;
2747 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2748 2064
2749 for (offset = ETH_MIB_GOOD_FRAMES_SENT; 2065 /*
2750 offset <= ETH_MIB_LATE_COLLISION; 2066 * Stop and then re-open the interface. This will allocate RX
2751 offset += 4) 2067 * skbs of the new MTU.
2752 *(u32 *)((char *)p + offset) += read_mib(mp, offset); 2068 * There is a possible danger that the open will not succeed,
2069 * due to memory being full.
2070 */
2071 mv643xx_eth_stop(dev);
2072 if (mv643xx_eth_open(dev)) {
2073 dev_printk(KERN_ERR, &dev->dev,
2074 "fatal error on re-opening device after "
2075 "MTU change\n");
2076 }
2077
2078 return 0;
2753} 2079}
2754 2080
2755/* 2081static void tx_timeout_task(struct work_struct *ugly)
2756 * ethernet_phy_detect - Detect whether a phy is present
2757 *
2758 * DESCRIPTION:
2759 * This function tests whether there is a PHY present on
2760 * the specified port.
2761 *
2762 * INPUT:
2763 * struct mv643xx_private *mp Ethernet Port.
2764 *
2765 * OUTPUT:
2766 * None
2767 *
2768 * RETURN:
2769 * 0 on success
2770 * -ENODEV on failure
2771 *
2772 */
2773static int ethernet_phy_detect(struct mv643xx_private *mp)
2774{ 2082{
2775 unsigned int phy_reg_data0; 2083 struct mv643xx_eth_private *mp;
2776 int auto_neg;
2777 2084
2778 eth_port_read_smi_reg(mp, 0, &phy_reg_data0); 2085 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2779 auto_neg = phy_reg_data0 & 0x1000; 2086 if (netif_running(mp->dev)) {
2780 phy_reg_data0 ^= 0x1000; /* invert auto_neg */ 2087 netif_stop_queue(mp->dev);
2781 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2782 2088
2783 eth_port_read_smi_reg(mp, 0, &phy_reg_data0); 2089 port_reset(mp);
2784 if ((phy_reg_data0 & 0x1000) == auto_neg) 2090 port_start(mp);
2785 return -ENODEV; /* change didn't take */
2786 2091
2787 phy_reg_data0 ^= 0x1000; 2092 __txq_maybe_wake(mp->txq + mp->txq_primary);
2788 eth_port_write_smi_reg(mp, 0, phy_reg_data0); 2093 }
2789 return 0;
2790} 2094}
2791 2095
2792/* 2096static void mv643xx_eth_tx_timeout(struct net_device *dev)
2793 * ethernet_phy_get - Get the ethernet port PHY address.
2794 *
2795 * DESCRIPTION:
2796 * This routine returns the given ethernet port PHY address.
2797 *
2798 * INPUT:
2799 * struct mv643xx_private *mp Ethernet Port.
2800 *
2801 * OUTPUT:
2802 * None.
2803 *
2804 * RETURN:
2805 * PHY address.
2806 *
2807 */
2808static int ethernet_phy_get(struct mv643xx_private *mp)
2809{ 2097{
2810 unsigned int reg_data; 2098 struct mv643xx_eth_private *mp = netdev_priv(dev);
2811 2099
2812 reg_data = rdl(mp, PHY_ADDR_REG); 2100 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2813 2101
2814 return ((reg_data >> (5 * mp->port_num)) & 0x1f); 2102 schedule_work(&mp->tx_timeout_task);
2815} 2103}
2816 2104
2817/* 2105#ifdef CONFIG_NET_POLL_CONTROLLER
2818 * ethernet_phy_set - Set the ethernet port PHY address. 2106static void mv643xx_eth_netpoll(struct net_device *dev)
2819 *
2820 * DESCRIPTION:
2821 * This routine sets the given ethernet port PHY address.
2822 *
2823 * INPUT:
2824 * struct mv643xx_private *mp Ethernet Port.
2825 * int phy_addr PHY address.
2826 *
2827 * OUTPUT:
2828 * None.
2829 *
2830 * RETURN:
2831 * None.
2832 *
2833 */
2834static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr)
2835{ 2107{
2836 u32 reg_data; 2108 struct mv643xx_eth_private *mp = netdev_priv(dev);
2837 int addr_shift = 5 * mp->port_num; 2109
2110 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2111 rdl(mp, INT_MASK(mp->port_num));
2112
2113 mv643xx_eth_irq(dev->irq, dev);
2838 2114
2839 reg_data = rdl(mp, PHY_ADDR_REG); 2115 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_CAUSE_EXT);
2840 reg_data &= ~(0x1f << addr_shift);
2841 reg_data |= (phy_addr & 0x1f) << addr_shift;
2842 wrl(mp, PHY_ADDR_REG, reg_data);
2843} 2116}
2117#endif
2844 2118
2845/* 2119static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2846 * ethernet_phy_reset - Reset Ethernet port PHY.
2847 *
2848 * DESCRIPTION:
2849 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2850 *
2851 * INPUT:
2852 * struct mv643xx_private *mp Ethernet Port.
2853 *
2854 * OUTPUT:
2855 * The PHY is reset.
2856 *
2857 * RETURN:
2858 * None.
2859 *
2860 */
2861static void ethernet_phy_reset(struct mv643xx_private *mp)
2862{ 2120{
2863 unsigned int phy_reg_data; 2121 struct mv643xx_eth_private *mp = netdev_priv(dev);
2122 int val;
2864 2123
2865 /* Reset the PHY */ 2124 smi_reg_read(mp, addr, reg, &val);
2866 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2867 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2868 eth_port_write_smi_reg(mp, 0, phy_reg_data);
2869 2125
2870 /* wait for PHY to come out of reset */ 2126 return val;
2871 do {
2872 udelay(1);
2873 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2874 } while (phy_reg_data & 0x8000);
2875} 2127}
2876 2128
2877static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp, 2129static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2878 unsigned int queues)
2879{ 2130{
2880 wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(mp->port_num), queues); 2131 struct mv643xx_eth_private *mp = netdev_priv(dev);
2132 smi_reg_write(mp, addr, reg, val);
2881} 2133}
2882 2134
2883static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
2884 unsigned int queues)
2885{
2886 wrl(mp, RECEIVE_QUEUE_COMMAND_REG(mp->port_num), queues);
2887}
2888 2135
2889static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp) 2136/* platform glue ************************************************************/
2137static void
2138mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2139 struct mbus_dram_target_info *dram)
2890{ 2140{
2891 unsigned int port_num = mp->port_num; 2141 void __iomem *base = msp->base;
2892 u32 queues; 2142 u32 win_enable;
2143 u32 win_protect;
2144 int i;
2893 2145
2894 /* Stop Tx port activity. Check port Tx activity. */ 2146 for (i = 0; i < 6; i++) {
2895 queues = rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF; 2147 writel(0, base + WINDOW_BASE(i));
2896 if (queues) { 2148 writel(0, base + WINDOW_SIZE(i));
2897 /* Issue stop command for active queues only */ 2149 if (i < 4)
2898 wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8)); 2150 writel(0, base + WINDOW_REMAP_HIGH(i));
2151 }
2899 2152
2900 /* Wait for all Tx activity to terminate. */ 2153 win_enable = 0x3f;
2901 /* Check port cause register that all Tx queues are stopped */ 2154 win_protect = 0;
2902 while (rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2903 udelay(PHY_WAIT_MICRO_SECONDS);
2904 2155
2905 /* Wait for Tx FIFO to empty */ 2156 for (i = 0; i < dram->num_cs; i++) {
2906 while (rdl(mp, PORT_STATUS_REG(port_num)) & 2157 struct mbus_dram_window *cs = dram->cs + i;
2907 ETH_PORT_TX_FIFO_EMPTY) 2158
2908 udelay(PHY_WAIT_MICRO_SECONDS); 2159 writel((cs->base & 0xffff0000) |
2160 (cs->mbus_attr << 8) |
2161 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2162 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2163
2164 win_enable &= ~(1 << i);
2165 win_protect |= 3 << (2 * i);
2909 } 2166 }
2910 2167
2911 return queues; 2168 writel(win_enable, base + WINDOW_BAR_ENABLE);
2169 msp->win_protect = win_protect;
2912} 2170}
2913 2171
2914static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp) 2172static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2915{ 2173{
2916 unsigned int port_num = mp->port_num; 2174 /*
2917 u32 queues; 2175 * Check whether we have a 14-bit coal limit field in bits
2918 2176 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2919 /* Stop Rx port activity. Check port Rx activity. */ 2177 * SDMA config register.
2920 queues = rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF; 2178 */
2921 if (queues) { 2179 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2922 /* Issue stop command for active queues only */ 2180 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2923 wrl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8)); 2181 msp->extended_rx_coal_limit = 1;
2924 2182 else
2925 /* Wait for all Rx activity to terminate. */ 2183 msp->extended_rx_coal_limit = 0;
2926 /* Check port cause register that all Rx queues are stopped */
2927 while (rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2928 udelay(PHY_WAIT_MICRO_SECONDS);
2929 }
2930 2184
2931 return queues; 2185 /*
2186 * Check whether the TX rate control registers are in the
2187 * old or the new place.
2188 */
2189 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2190 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2191 msp->tx_bw_control_moved = 1;
2192 else
2193 msp->tx_bw_control_moved = 0;
2932} 2194}
2933 2195
2934/* 2196static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2935 * eth_port_reset - Reset Ethernet port
2936 *
2937 * DESCRIPTION:
2938 * This routine resets the chip by aborting any SDMA engine activity and
2939 * clearing the MIB counters. The Receiver and the Transmit unit are in
2940 * idle state after this command is performed and the port is disabled.
2941 *
2942 * INPUT:
2943 * struct mv643xx_private *mp Ethernet Port.
2944 *
2945 * OUTPUT:
2946 * Channel activity is halted.
2947 *
2948 * RETURN:
2949 * None.
2950 *
2951 */
2952static void eth_port_reset(struct mv643xx_private *mp)
2953{ 2197{
2954 unsigned int port_num = mp->port_num; 2198 static int mv643xx_eth_version_printed = 0;
2955 unsigned int reg_data; 2199 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2200 struct mv643xx_eth_shared_private *msp;
2201 struct resource *res;
2202 int ret;
2956 2203
2957 mv643xx_eth_port_disable_tx(mp); 2204 if (!mv643xx_eth_version_printed++)
2958 mv643xx_eth_port_disable_rx(mp); 2205 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2959 2206
2960 /* Clear all MIB counters */ 2207 ret = -EINVAL;
2961 eth_clear_mib_counters(mp); 2208 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2209 if (res == NULL)
2210 goto out;
2962 2211
2963 /* Reset the Enable bit in the Configuration Register */ 2212 ret = -ENOMEM;
2964 reg_data = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); 2213 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2965 reg_data &= ~(SERIAL_PORT_ENABLE | 2214 if (msp == NULL)
2966 DO_NOT_FORCE_LINK_FAIL | 2215 goto out;
2967 FORCE_LINK_PASS); 2216 memset(msp, 0, sizeof(*msp));
2968 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2969}
2970 2217
2218 msp->base = ioremap(res->start, res->end - res->start + 1);
2219 if (msp->base == NULL)
2220 goto out_free;
2971 2221
2972/* 2222 spin_lock_init(&msp->phy_lock);
2973 * eth_port_read_smi_reg - Read PHY registers
2974 *
2975 * DESCRIPTION:
2976 * This routine utilize the SMI interface to interact with the PHY in
2977 * order to perform PHY register read.
2978 *
2979 * INPUT:
2980 * struct mv643xx_private *mp Ethernet Port.
2981 * unsigned int phy_reg PHY register address offset.
2982 * unsigned int *value Register value buffer.
2983 *
2984 * OUTPUT:
2985 * Write the value of a specified PHY register into given buffer.
2986 *
2987 * RETURN:
2988 * false if the PHY is busy or read data is not in valid state.
2989 * true otherwise.
2990 *
2991 */
2992static void eth_port_read_smi_reg(struct mv643xx_private *mp,
2993 unsigned int phy_reg, unsigned int *value)
2994{
2995 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
2996 int phy_addr = ethernet_phy_get(mp);
2997 unsigned long flags;
2998 int i;
2999 2223
3000 /* the SMI register is a shared resource */ 2224 /*
3001 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); 2225 * (Re-)program MBUS remapping windows if we are asked to.
2226 */
2227 if (pd != NULL && pd->dram != NULL)
2228 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
3002 2229
3003 /* wait for the SMI register to become available */ 2230 /*
3004 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { 2231 * Detect hardware parameters.
3005 if (i == PHY_WAIT_ITERATIONS) { 2232 */
3006 printk("%s: PHY busy timeout\n", mp->dev->name); 2233 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
3007 goto out; 2234 infer_hw_params(msp);
3008 }
3009 udelay(PHY_WAIT_MICRO_SECONDS);
3010 }
3011 2235
3012 writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ, 2236 platform_set_drvdata(pdev, msp);
3013 smi_reg);
3014 2237
3015 /* now wait for the data to be valid */ 2238 return 0;
3016 for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) {
3017 if (i == PHY_WAIT_ITERATIONS) {
3018 printk("%s: PHY read timeout\n", mp->dev->name);
3019 goto out;
3020 }
3021 udelay(PHY_WAIT_MICRO_SECONDS);
3022 }
3023 2239
3024 *value = readl(smi_reg) & 0xffff; 2240out_free:
2241 kfree(msp);
3025out: 2242out:
3026 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); 2243 return ret;
3027} 2244}
3028 2245
3029/* 2246static int mv643xx_eth_shared_remove(struct platform_device *pdev)
3030 * eth_port_write_smi_reg - Write to PHY registers
3031 *
3032 * DESCRIPTION:
3033 * This routine utilize the SMI interface to interact with the PHY in
3034 * order to perform writes to PHY registers.
3035 *
3036 * INPUT:
3037 * struct mv643xx_private *mp Ethernet Port.
3038 * unsigned int phy_reg PHY register address offset.
3039 * unsigned int value Register value.
3040 *
3041 * OUTPUT:
3042 * Write the given value to the specified PHY register.
3043 *
3044 * RETURN:
3045 * false if the PHY is busy.
3046 * true otherwise.
3047 *
3048 */
3049static void eth_port_write_smi_reg(struct mv643xx_private *mp,
3050 unsigned int phy_reg, unsigned int value)
3051{ 2247{
3052 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; 2248 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
3053 int phy_addr = ethernet_phy_get(mp);
3054 unsigned long flags;
3055 int i;
3056
3057 /* the SMI register is a shared resource */
3058 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
3059 2249
3060 /* wait for the SMI register to become available */ 2250 iounmap(msp->base);
3061 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { 2251 kfree(msp);
3062 if (i == PHY_WAIT_ITERATIONS) {
3063 printk("%s: PHY busy timeout\n", mp->dev->name);
3064 goto out;
3065 }
3066 udelay(PHY_WAIT_MICRO_SECONDS);
3067 }
3068 2252
3069 writel((phy_addr << 16) | (phy_reg << 21) | 2253 return 0;
3070 ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
3071out:
3072 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
3073} 2254}
3074 2255
3075/* 2256static struct platform_driver mv643xx_eth_shared_driver = {
3076 * Wrappers for MII support library. 2257 .probe = mv643xx_eth_shared_probe,
3077 */ 2258 .remove = mv643xx_eth_shared_remove,
3078static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) 2259 .driver = {
2260 .name = MV643XX_ETH_SHARED_NAME,
2261 .owner = THIS_MODULE,
2262 },
2263};
2264
2265static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
3079{ 2266{
3080 struct mv643xx_private *mp = netdev_priv(dev); 2267 int addr_shift = 5 * mp->port_num;
3081 int val; 2268 u32 data;
3082 2269
3083 eth_port_read_smi_reg(mp, location, &val); 2270 data = rdl(mp, PHY_ADDR);
3084 return val; 2271 data &= ~(0x1f << addr_shift);
2272 data |= (phy_addr & 0x1f) << addr_shift;
2273 wrl(mp, PHY_ADDR, data);
3085} 2274}
3086 2275
3087static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) 2276static int phy_addr_get(struct mv643xx_eth_private *mp)
3088{ 2277{
3089 struct mv643xx_private *mp = netdev_priv(dev); 2278 unsigned int data;
3090 eth_port_write_smi_reg(mp, location, val); 2279
2280 data = rdl(mp, PHY_ADDR);
2281
2282 return (data >> (5 * mp->port_num)) & 0x1f;
3091} 2283}
3092 2284
3093/* 2285static void set_params(struct mv643xx_eth_private *mp,
3094 * eth_port_receive - Get received information from Rx ring. 2286 struct mv643xx_eth_platform_data *pd)
3095 *
3096 * DESCRIPTION:
3097 * This routine returns the received data to the caller. There is no
3098 * data copying during routine operation. All information is returned
3099 * using pointer to packet information struct passed from the caller.
3100 * If the routine exhausts Rx ring resources then the resource error flag
3101 * is set.
3102 *
3103 * INPUT:
3104 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3105 * struct pkt_info *p_pkt_info User packet buffer.
3106 *
3107 * OUTPUT:
3108 * Rx ring current and used indexes are updated.
3109 *
3110 * RETURN:
3111 * ETH_ERROR in case the routine can not access Rx desc ring.
3112 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
3113 * ETH_END_OF_JOB if there is no received data.
3114 * ETH_OK otherwise.
3115 */
3116static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
3117 struct pkt_info *p_pkt_info)
3118{ 2287{
3119 int rx_next_curr_desc, rx_curr_desc, rx_used_desc; 2288 struct net_device *dev = mp->dev;
3120 volatile struct eth_rx_desc *p_rx_desc;
3121 unsigned int command_status;
3122 unsigned long flags;
3123 2289
3124 /* Do not process Rx ring in case of Rx ring resource error */ 2290 if (is_valid_ether_addr(pd->mac_addr))
3125 if (mp->rx_resource_err) 2291 memcpy(dev->dev_addr, pd->mac_addr, 6);
3126 return ETH_QUEUE_FULL; 2292 else
2293 uc_addr_get(mp, dev->dev_addr);
3127 2294
3128 spin_lock_irqsave(&mp->lock, flags); 2295 if (pd->phy_addr == -1) {
2296 mp->shared_smi = NULL;
2297 mp->phy_addr = -1;
2298 } else {
2299 mp->shared_smi = mp->shared;
2300 if (pd->shared_smi != NULL)
2301 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
3129 2302
3130 /* Get the Rx Desc ring 'curr and 'used' indexes */ 2303 if (pd->force_phy_addr || pd->phy_addr) {
3131 rx_curr_desc = mp->rx_curr_desc_q; 2304 mp->phy_addr = pd->phy_addr & 0x3f;
3132 rx_used_desc = mp->rx_used_desc_q; 2305 phy_addr_set(mp, mp->phy_addr);
2306 } else {
2307 mp->phy_addr = phy_addr_get(mp);
2308 }
2309 }
3133 2310
3134 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; 2311 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2312 if (pd->rx_queue_size)
2313 mp->default_rx_ring_size = pd->rx_queue_size;
2314 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2315 mp->rx_desc_sram_size = pd->rx_sram_size;
3135 2316
3136 /* The following parameters are used to save readings from memory */ 2317 if (pd->rx_queue_mask)
3137 command_status = p_rx_desc->cmd_sts; 2318 mp->rxq_mask = pd->rx_queue_mask;
3138 rmb(); 2319 else
2320 mp->rxq_mask = 0x01;
2321 mp->rxq_primary = fls(mp->rxq_mask) - 1;
3139 2322
3140 /* Nothing to receive... */ 2323 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
3141 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { 2324 if (pd->tx_queue_size)
3142 spin_unlock_irqrestore(&mp->lock, flags); 2325 mp->default_tx_ring_size = pd->tx_queue_size;
3143 return ETH_END_OF_JOB; 2326 mp->tx_desc_sram_addr = pd->tx_sram_addr;
3144 } 2327 mp->tx_desc_sram_size = pd->tx_sram_size;
3145 2328
3146 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET; 2329 if (pd->tx_queue_mask)
3147 p_pkt_info->cmd_sts = command_status; 2330 mp->txq_mask = pd->tx_queue_mask;
3148 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET; 2331 else
3149 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; 2332 mp->txq_mask = 0x01;
3150 p_pkt_info->l4i_chk = p_rx_desc->buf_size; 2333 mp->txq_primary = fls(mp->txq_mask) - 1;
2334}
3151 2335
3152 /* 2336static int phy_detect(struct mv643xx_eth_private *mp)
3153 * Clean the return info field to indicate that the 2337{
3154 * packet has been moved to the upper layers 2338 unsigned int data;
3155 */ 2339 unsigned int data2;
3156 mp->rx_skb[rx_curr_desc] = NULL;
3157 2340
3158 /* Update current index in data structure */ 2341 smi_reg_read(mp, mp->phy_addr, 0, &data);
3159 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; 2342 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
3160 mp->rx_curr_desc_q = rx_next_curr_desc;
3161 2343
3162 /* Rx descriptors exhausted. Set the Rx ring resource error flag */ 2344 smi_reg_read(mp, mp->phy_addr, 0, &data2);
3163 if (rx_next_curr_desc == rx_used_desc) 2345 if (((data ^ data2) & 0x1000) == 0)
3164 mp->rx_resource_err = 1; 2346 return -ENODEV;
3165 2347
3166 spin_unlock_irqrestore(&mp->lock, flags); 2348 smi_reg_write(mp, mp->phy_addr, 0, data);
3167 2349
3168 return ETH_OK; 2350 return 0;
3169} 2351}
3170 2352
3171/* 2353static int phy_init(struct mv643xx_eth_private *mp,
3172 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. 2354 struct mv643xx_eth_platform_data *pd)
3173 *
3174 * DESCRIPTION:
3175 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
3176 * next 'used' descriptor and attached the returned buffer to it.
3177 * In case the Rx ring was in "resource error" condition, where there are
3178 * no available Rx resources, the function resets the resource error flag.
3179 *
3180 * INPUT:
3181 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3182 * struct pkt_info *p_pkt_info Information on returned buffer.
3183 *
3184 * OUTPUT:
3185 * New available Rx resource in Rx descriptor ring.
3186 *
3187 * RETURN:
3188 * ETH_ERROR in case the routine can not access Rx desc ring.
3189 * ETH_OK otherwise.
3190 */
3191static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
3192 struct pkt_info *p_pkt_info)
3193{ 2355{
3194 int used_rx_desc; /* Where to return Rx resource */ 2356 struct ethtool_cmd cmd;
3195 volatile struct eth_rx_desc *p_used_rx_desc; 2357 int err;
3196 unsigned long flags;
3197 2358
3198 spin_lock_irqsave(&mp->lock, flags); 2359 err = phy_detect(mp);
2360 if (err) {
2361 dev_printk(KERN_INFO, &mp->dev->dev,
2362 "no PHY detected at addr %d\n", mp->phy_addr);
2363 return err;
2364 }
2365 phy_reset(mp);
3199 2366
3200 /* Get 'used' Rx descriptor */ 2367 mp->mii.phy_id = mp->phy_addr;
3201 used_rx_desc = mp->rx_used_desc_q; 2368 mp->mii.phy_id_mask = 0x3f;
3202 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; 2369 mp->mii.reg_num_mask = 0x1f;
2370 mp->mii.dev = mp->dev;
2371 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2372 mp->mii.mdio_write = mv643xx_eth_mdio_write;
3203 2373
3204 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; 2374 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
3205 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
3206 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
3207 2375
3208 /* Flush the write pipe */ 2376 memset(&cmd, 0, sizeof(cmd));
2377
2378 cmd.port = PORT_MII;
2379 cmd.transceiver = XCVR_INTERNAL;
2380 cmd.phy_address = mp->phy_addr;
2381 if (pd->speed == 0) {
2382 cmd.autoneg = AUTONEG_ENABLE;
2383 cmd.speed = SPEED_100;
2384 cmd.advertising = ADVERTISED_10baseT_Half |
2385 ADVERTISED_10baseT_Full |
2386 ADVERTISED_100baseT_Half |
2387 ADVERTISED_100baseT_Full;
2388 if (mp->mii.supports_gmii)
2389 cmd.advertising |= ADVERTISED_1000baseT_Full;
2390 } else {
2391 cmd.autoneg = AUTONEG_DISABLE;
2392 cmd.speed = pd->speed;
2393 cmd.duplex = pd->duplex;
2394 }
3209 2395
3210 /* Return the descriptor to DMA ownership */ 2396 update_pscr(mp, cmd.speed, cmd.duplex);
3211 wmb(); 2397 mv643xx_eth_set_settings(mp->dev, &cmd);
3212 p_used_rx_desc->cmd_sts =
3213 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3214 wmb();
3215 2398
3216 /* Move the used descriptor pointer to the next descriptor */ 2399 return 0;
3217 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; 2400}
3218 2401
3219 /* Any Rx return cancels the Rx resource error status */ 2402static int mv643xx_eth_probe(struct platform_device *pdev)
3220 mp->rx_resource_err = 0; 2403{
2404 struct mv643xx_eth_platform_data *pd;
2405 struct mv643xx_eth_private *mp;
2406 struct net_device *dev;
2407 struct resource *res;
2408 DECLARE_MAC_BUF(mac);
2409 int err;
3221 2410
3222 spin_unlock_irqrestore(&mp->lock, flags); 2411 pd = pdev->dev.platform_data;
2412 if (pd == NULL) {
2413 dev_printk(KERN_ERR, &pdev->dev,
2414 "no mv643xx_eth_platform_data\n");
2415 return -ENODEV;
2416 }
3223 2417
3224 return ETH_OK; 2418 if (pd->shared == NULL) {
3225} 2419 dev_printk(KERN_ERR, &pdev->dev,
2420 "no mv643xx_eth_platform_data->shared\n");
2421 return -ENODEV;
2422 }
3226 2423
3227/************* Begin ethtool support *************************/ 2424 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2425 if (!dev)
2426 return -ENOMEM;
3228 2427
3229struct mv643xx_stats { 2428 mp = netdev_priv(dev);
3230 char stat_string[ETH_GSTRING_LEN]; 2429 platform_set_drvdata(pdev, mp);
3231 int sizeof_stat;
3232 int stat_offset;
3233};
3234 2430
3235#define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \ 2431 mp->shared = platform_get_drvdata(pd->shared);
3236 offsetof(struct mv643xx_private, m) 2432 mp->port_num = pd->port_number;
3237
3238static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
3239 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
3240 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
3241 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
3242 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
3243 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
3244 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
3245 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
3246 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
3247 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
3248 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
3249 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
3250 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
3251 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
3252 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
3253 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
3254 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
3255 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
3256 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
3257 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
3258 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
3259 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
3260 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
3261 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
3262 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
3263 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
3264 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
3265 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
3266 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
3267 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3268 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3269 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3270 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3271 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3272 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3273 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3274 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3275 { "collision", MV643XX_STAT(mib_counters.collision) },
3276 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3277};
3278 2433
3279#define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats) 2434 mp->dev = dev;
2435#ifdef MV643XX_ETH_NAPI
2436 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2437#endif
3280 2438
3281static void mv643xx_get_drvinfo(struct net_device *netdev, 2439 set_params(mp, pd);
3282 struct ethtool_drvinfo *drvinfo)
3283{
3284 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3285 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3286 strncpy(drvinfo->fw_version, "N/A", 32);
3287 strncpy(drvinfo->bus_info, "mv643xx", 32);
3288 drvinfo->n_stats = MV643XX_STATS_LEN;
3289}
3290 2440
3291static int mv643xx_get_sset_count(struct net_device *netdev, int sset) 2441 spin_lock_init(&mp->lock);
3292{
3293 switch (sset) {
3294 case ETH_SS_STATS:
3295 return MV643XX_STATS_LEN;
3296 default:
3297 return -EOPNOTSUPP;
3298 }
3299}
3300 2442
3301static void mv643xx_get_ethtool_stats(struct net_device *netdev, 2443 mib_counters_clear(mp);
3302 struct ethtool_stats *stats, uint64_t *data) 2444 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3303{
3304 struct mv643xx_private *mp = netdev->priv;
3305 int i;
3306 2445
3307 eth_update_mib_counters(mp); 2446 if (mp->phy_addr != -1) {
2447 err = phy_init(mp, pd);
2448 if (err)
2449 goto out;
3308 2450
3309 for (i = 0; i < MV643XX_STATS_LEN; i++) { 2451 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
3310 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; 2452 } else {
3311 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == 2453 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
3312 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3313 } 2454 }
3314}
3315 2455
3316static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
3317 uint8_t *data)
3318{
3319 int i;
3320 2456
3321 switch(stringset) { 2457 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3322 case ETH_SS_STATS: 2458 BUG_ON(!res);
3323 for (i=0; i < MV643XX_STATS_LEN; i++) { 2459 dev->irq = res->start;
3324 memcpy(data + i * ETH_GSTRING_LEN, 2460
3325 mv643xx_gstrings_stats[i].stat_string, 2461 dev->hard_start_xmit = mv643xx_eth_xmit;
3326 ETH_GSTRING_LEN); 2462 dev->open = mv643xx_eth_open;
3327 } 2463 dev->stop = mv643xx_eth_stop;
3328 break; 2464 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
3329 } 2465 dev->set_mac_address = mv643xx_eth_set_mac_address;
2466 dev->do_ioctl = mv643xx_eth_ioctl;
2467 dev->change_mtu = mv643xx_eth_change_mtu;
2468 dev->tx_timeout = mv643xx_eth_tx_timeout;
2469#ifdef CONFIG_NET_POLL_CONTROLLER
2470 dev->poll_controller = mv643xx_eth_netpoll;
2471#endif
2472 dev->watchdog_timeo = 2 * HZ;
2473 dev->base_addr = 0;
2474
2475#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2476 /*
2477 * Zero copy can only work if we use Discovery II memory. Else, we will
2478 * have to map the buffers to ISA memory which is only 16 MB
2479 */
2480 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2481#endif
2482
2483 SET_NETDEV_DEV(dev, &pdev->dev);
2484
2485 if (mp->shared->win_protect)
2486 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2487
2488 err = register_netdev(dev);
2489 if (err)
2490 goto out;
2491
2492 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2493 mp->port_num, print_mac(mac, dev->dev_addr));
2494
2495 if (dev->features & NETIF_F_SG)
2496 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2497
2498 if (dev->features & NETIF_F_IP_CSUM)
2499 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2500
2501#ifdef MV643XX_ETH_NAPI
2502 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2503#endif
2504
2505 if (mp->tx_desc_sram_size > 0)
2506 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2507
2508 return 0;
2509
2510out:
2511 free_netdev(dev);
2512
2513 return err;
3330} 2514}
3331 2515
3332static u32 mv643xx_eth_get_link(struct net_device *dev) 2516static int mv643xx_eth_remove(struct platform_device *pdev)
3333{ 2517{
3334 struct mv643xx_private *mp = netdev_priv(dev); 2518 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3335 2519
3336 return mii_link_ok(&mp->mii); 2520 unregister_netdev(mp->dev);
2521 flush_scheduled_work();
2522 free_netdev(mp->dev);
2523
2524 platform_set_drvdata(pdev, NULL);
2525
2526 return 0;
3337} 2527}
3338 2528
3339static int mv643xx_eth_nway_restart(struct net_device *dev) 2529static void mv643xx_eth_shutdown(struct platform_device *pdev)
3340{ 2530{
3341 struct mv643xx_private *mp = netdev_priv(dev); 2531 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3342 2532
3343 return mii_nway_restart(&mp->mii); 2533 /* Mask all interrupts on ethernet port */
2534 wrl(mp, INT_MASK(mp->port_num), 0);
2535 rdl(mp, INT_MASK(mp->port_num));
2536
2537 if (netif_running(mp->dev))
2538 port_reset(mp);
3344} 2539}
3345 2540
3346static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2541static struct platform_driver mv643xx_eth_driver = {
2542 .probe = mv643xx_eth_probe,
2543 .remove = mv643xx_eth_remove,
2544 .shutdown = mv643xx_eth_shutdown,
2545 .driver = {
2546 .name = MV643XX_ETH_NAME,
2547 .owner = THIS_MODULE,
2548 },
2549};
2550
2551static int __init mv643xx_eth_init_module(void)
3347{ 2552{
3348 struct mv643xx_private *mp = netdev_priv(dev); 2553 int rc;
2554
2555 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2556 if (!rc) {
2557 rc = platform_driver_register(&mv643xx_eth_driver);
2558 if (rc)
2559 platform_driver_unregister(&mv643xx_eth_shared_driver);
2560 }
3349 2561
3350 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); 2562 return rc;
3351} 2563}
2564module_init(mv643xx_eth_init_module);
3352 2565
3353static const struct ethtool_ops mv643xx_ethtool_ops = { 2566static void __exit mv643xx_eth_cleanup_module(void)
3354 .get_settings = mv643xx_get_settings, 2567{
3355 .set_settings = mv643xx_set_settings, 2568 platform_driver_unregister(&mv643xx_eth_driver);
3356 .get_drvinfo = mv643xx_get_drvinfo, 2569 platform_driver_unregister(&mv643xx_eth_shared_driver);
3357 .get_link = mv643xx_eth_get_link, 2570}
3358 .set_sg = ethtool_op_set_sg, 2571module_exit(mv643xx_eth_cleanup_module);
3359 .get_sset_count = mv643xx_get_sset_count,
3360 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3361 .get_strings = mv643xx_get_strings,
3362 .nway_reset = mv643xx_eth_nway_restart,
3363};
3364 2572
3365/************* End ethtool support *************************/ 2573MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2574 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2575MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2576MODULE_LICENSE("GPL");
2577MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2578MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index 823bb6d35334..b3981ed972bf 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -49,6 +49,7 @@
49#include <linux/if_ether.h> 49#include <linux/if_ether.h>
50#include <linux/if_vlan.h> 50#include <linux/if_vlan.h>
51#include <linux/inet_lro.h> 51#include <linux/inet_lro.h>
52#include <linux/dca.h>
52#include <linux/ip.h> 53#include <linux/ip.h>
53#include <linux/inet.h> 54#include <linux/inet.h>
54#include <linux/in.h> 55#include <linux/in.h>
@@ -185,11 +186,18 @@ struct myri10ge_slice_state {
185 dma_addr_t fw_stats_bus; 186 dma_addr_t fw_stats_bus;
186 int watchdog_tx_done; 187 int watchdog_tx_done;
187 int watchdog_tx_req; 188 int watchdog_tx_req;
189#ifdef CONFIG_DCA
190 int cached_dca_tag;
191 int cpu;
192 __be32 __iomem *dca_tag;
193#endif
194 char irq_desc[32];
188}; 195};
189 196
190struct myri10ge_priv { 197struct myri10ge_priv {
191 struct myri10ge_slice_state ss; 198 struct myri10ge_slice_state *ss;
192 int tx_boundary; /* boundary transmits cannot cross */ 199 int tx_boundary; /* boundary transmits cannot cross */
200 int num_slices;
193 int running; /* running? */ 201 int running; /* running? */
194 int csum_flag; /* rx_csums? */ 202 int csum_flag; /* rx_csums? */
195 int small_bytes; 203 int small_bytes;
@@ -208,6 +216,11 @@ struct myri10ge_priv {
208 dma_addr_t cmd_bus; 216 dma_addr_t cmd_bus;
209 struct pci_dev *pdev; 217 struct pci_dev *pdev;
210 int msi_enabled; 218 int msi_enabled;
219 int msix_enabled;
220 struct msix_entry *msix_vectors;
221#ifdef CONFIG_DCA
222 int dca_enabled;
223#endif
211 u32 link_state; 224 u32 link_state;
212 unsigned int rdma_tags_available; 225 unsigned int rdma_tags_available;
213 int intr_coal_delay; 226 int intr_coal_delay;
@@ -244,6 +257,8 @@ struct myri10ge_priv {
244 257
245static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat"; 258static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
246static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat"; 259static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
260static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
261static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
247 262
248static char *myri10ge_fw_name = NULL; 263static char *myri10ge_fw_name = NULL;
249module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR); 264module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
@@ -321,6 +336,18 @@ static int myri10ge_wcfifo = 0;
321module_param(myri10ge_wcfifo, int, S_IRUGO); 336module_param(myri10ge_wcfifo, int, S_IRUGO);
322MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled"); 337MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
323 338
339static int myri10ge_max_slices = 1;
340module_param(myri10ge_max_slices, int, S_IRUGO);
341MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
342
343static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
344module_param(myri10ge_rss_hash, int, S_IRUGO);
345MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
346
347static int myri10ge_dca = 1;
348module_param(myri10ge_dca, int, S_IRUGO);
349MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
350
324#define MYRI10GE_FW_OFFSET 1024*1024 351#define MYRI10GE_FW_OFFSET 1024*1024
325#define MYRI10GE_HIGHPART_TO_U32(X) \ 352#define MYRI10GE_HIGHPART_TO_U32(X) \
326(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0) 353(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
@@ -664,7 +691,7 @@ static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
664 return 0; 691 return 0;
665} 692}
666 693
667static int myri10ge_load_firmware(struct myri10ge_priv *mgp) 694static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
668{ 695{
669 char __iomem *submit; 696 char __iomem *submit;
670 __be32 buf[16] __attribute__ ((__aligned__(8))); 697 __be32 buf[16] __attribute__ ((__aligned__(8)));
@@ -674,6 +701,8 @@ static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
674 size = 0; 701 size = 0;
675 status = myri10ge_load_hotplug_firmware(mgp, &size); 702 status = myri10ge_load_hotplug_firmware(mgp, &size);
676 if (status) { 703 if (status) {
704 if (!adopt)
705 return status;
677 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n"); 706 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
678 707
679 /* Do not attempt to adopt firmware if there 708 /* Do not attempt to adopt firmware if there
@@ -866,8 +895,12 @@ abort:
866static int myri10ge_reset(struct myri10ge_priv *mgp) 895static int myri10ge_reset(struct myri10ge_priv *mgp)
867{ 896{
868 struct myri10ge_cmd cmd; 897 struct myri10ge_cmd cmd;
869 int status; 898 struct myri10ge_slice_state *ss;
899 int i, status;
870 size_t bytes; 900 size_t bytes;
901#ifdef CONFIG_DCA
902 unsigned long dca_tag_off;
903#endif
871 904
872 /* try to send a reset command to the card to see if it 905 /* try to send a reset command to the card to see if it
873 * is alive */ 906 * is alive */
@@ -879,20 +912,74 @@ static int myri10ge_reset(struct myri10ge_priv *mgp)
879 } 912 }
880 913
881 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST); 914 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
915 /*
916 * Use non-ndis mcp_slot (eg, 4 bytes total,
917 * no toeplitz hash value returned. Older firmware will
918 * not understand this command, but will use the correct
919 * sized mcp_slot, so we ignore error returns
920 */
921 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
922 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
882 923
883 /* Now exchange information about interrupts */ 924 /* Now exchange information about interrupts */
884 925
885 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry); 926 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
886 memset(mgp->ss.rx_done.entry, 0, bytes);
887 cmd.data0 = (u32) bytes; 927 cmd.data0 = (u32) bytes;
888 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0); 928 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
889 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->ss.rx_done.bus); 929
890 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->ss.rx_done.bus); 930 /*
891 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0); 931 * Even though we already know how many slices are supported
932 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
933 * has magic side effects, and must be called after a reset.
934 * It must be called prior to calling any RSS related cmds,
935 * including assigning an interrupt queue for anything but
936 * slice 0. It must also be called *after*
937 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
938 * the firmware to compute offsets.
939 */
940
941 if (mgp->num_slices > 1) {
942
943 /* ask the maximum number of slices it supports */
944 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
945 &cmd, 0);
946 if (status != 0) {
947 dev_err(&mgp->pdev->dev,
948 "failed to get number of slices\n");
949 }
950
951 /*
952 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
953 * to setting up the interrupt queue DMA
954 */
955
956 cmd.data0 = mgp->num_slices;
957 cmd.data1 = 1; /* use MSI-X */
958 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
959 &cmd, 0);
960 if (status != 0) {
961 dev_err(&mgp->pdev->dev,
962 "failed to set number of slices\n");
963
964 return status;
965 }
966 }
967 for (i = 0; i < mgp->num_slices; i++) {
968 ss = &mgp->ss[i];
969 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
970 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
971 cmd.data2 = i;
972 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
973 &cmd, 0);
974 };
892 975
893 status |= 976 status |=
894 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0); 977 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
895 mgp->ss.irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0); 978 for (i = 0; i < mgp->num_slices; i++) {
979 ss = &mgp->ss[i];
980 ss->irq_claim =
981 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
982 }
896 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, 983 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
897 &cmd, 0); 984 &cmd, 0);
898 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0); 985 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
@@ -906,24 +993,116 @@ static int myri10ge_reset(struct myri10ge_priv *mgp)
906 } 993 }
907 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr); 994 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
908 995
909 memset(mgp->ss.rx_done.entry, 0, bytes); 996#ifdef CONFIG_DCA
997 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
998 dca_tag_off = cmd.data0;
999 for (i = 0; i < mgp->num_slices; i++) {
1000 ss = &mgp->ss[i];
1001 if (status == 0) {
1002 ss->dca_tag = (__iomem __be32 *)
1003 (mgp->sram + dca_tag_off + 4 * i);
1004 } else {
1005 ss->dca_tag = NULL;
1006 }
1007 }
1008#endif /* CONFIG_DCA */
910 1009
911 /* reset mcp/driver shared state back to 0 */ 1010 /* reset mcp/driver shared state back to 0 */
912 mgp->ss.tx.req = 0; 1011
913 mgp->ss.tx.done = 0;
914 mgp->ss.tx.pkt_start = 0;
915 mgp->ss.tx.pkt_done = 0;
916 mgp->ss.rx_big.cnt = 0;
917 mgp->ss.rx_small.cnt = 0;
918 mgp->ss.rx_done.idx = 0;
919 mgp->ss.rx_done.cnt = 0;
920 mgp->link_changes = 0; 1012 mgp->link_changes = 0;
1013 for (i = 0; i < mgp->num_slices; i++) {
1014 ss = &mgp->ss[i];
1015
1016 memset(ss->rx_done.entry, 0, bytes);
1017 ss->tx.req = 0;
1018 ss->tx.done = 0;
1019 ss->tx.pkt_start = 0;
1020 ss->tx.pkt_done = 0;
1021 ss->rx_big.cnt = 0;
1022 ss->rx_small.cnt = 0;
1023 ss->rx_done.idx = 0;
1024 ss->rx_done.cnt = 0;
1025 ss->tx.wake_queue = 0;
1026 ss->tx.stop_queue = 0;
1027 }
1028
921 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr); 1029 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
922 myri10ge_change_pause(mgp, mgp->pause); 1030 myri10ge_change_pause(mgp, mgp->pause);
923 myri10ge_set_multicast_list(mgp->dev); 1031 myri10ge_set_multicast_list(mgp->dev);
924 return status; 1032 return status;
925} 1033}
926 1034
1035#ifdef CONFIG_DCA
1036static void
1037myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1038{
1039 ss->cpu = cpu;
1040 ss->cached_dca_tag = tag;
1041 put_be32(htonl(tag), ss->dca_tag);
1042}
1043
1044static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1045{
1046 int cpu = get_cpu();
1047 int tag;
1048
1049 if (cpu != ss->cpu) {
1050 tag = dca_get_tag(cpu);
1051 if (ss->cached_dca_tag != tag)
1052 myri10ge_write_dca(ss, cpu, tag);
1053 }
1054 put_cpu();
1055}
1056
1057static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1058{
1059 int err, i;
1060 struct pci_dev *pdev = mgp->pdev;
1061
1062 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1063 return;
1064 if (!myri10ge_dca) {
1065 dev_err(&pdev->dev, "dca disabled by administrator\n");
1066 return;
1067 }
1068 err = dca_add_requester(&pdev->dev);
1069 if (err) {
1070 dev_err(&pdev->dev,
1071 "dca_add_requester() failed, err=%d\n", err);
1072 return;
1073 }
1074 mgp->dca_enabled = 1;
1075 for (i = 0; i < mgp->num_slices; i++)
1076 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1077}
1078
1079static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1080{
1081 struct pci_dev *pdev = mgp->pdev;
1082 int err;
1083
1084 if (!mgp->dca_enabled)
1085 return;
1086 mgp->dca_enabled = 0;
1087 err = dca_remove_requester(&pdev->dev);
1088}
1089
1090static int myri10ge_notify_dca_device(struct device *dev, void *data)
1091{
1092 struct myri10ge_priv *mgp;
1093 unsigned long event;
1094
1095 mgp = dev_get_drvdata(dev);
1096 event = *(unsigned long *)data;
1097
1098 if (event == DCA_PROVIDER_ADD)
1099 myri10ge_setup_dca(mgp);
1100 else if (event == DCA_PROVIDER_REMOVE)
1101 myri10ge_teardown_dca(mgp);
1102 return 0;
1103}
1104#endif /* CONFIG_DCA */
1105
927static inline void 1106static inline void
928myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst, 1107myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
929 struct mcp_kreq_ether_recv *src) 1108 struct mcp_kreq_ether_recv *src)
@@ -1102,9 +1281,10 @@ myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1102 rx_frags[0].size -= MXGEFW_PAD; 1281 rx_frags[0].size -= MXGEFW_PAD;
1103 len -= MXGEFW_PAD; 1282 len -= MXGEFW_PAD;
1104 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags, 1283 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1105 len, len,
1106 /* opaque, will come back in get_frag_header */ 1284 /* opaque, will come back in get_frag_header */
1285 len, len,
1107 (void *)(__force unsigned long)csum, csum); 1286 (void *)(__force unsigned long)csum, csum);
1287
1108 return 1; 1288 return 1;
1109 } 1289 }
1110 1290
@@ -1243,7 +1423,7 @@ myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1243 1423
1244static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp) 1424static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1245{ 1425{
1246 struct mcp_irq_data *stats = mgp->ss.fw_stats; 1426 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1247 1427
1248 if (unlikely(stats->stats_updated)) { 1428 if (unlikely(stats->stats_updated)) {
1249 unsigned link_up = ntohl(stats->link_up); 1429 unsigned link_up = ntohl(stats->link_up);
@@ -1290,6 +1470,11 @@ static int myri10ge_poll(struct napi_struct *napi, int budget)
1290 struct net_device *netdev = ss->mgp->dev; 1470 struct net_device *netdev = ss->mgp->dev;
1291 int work_done; 1471 int work_done;
1292 1472
1473#ifdef CONFIG_DCA
1474 if (ss->mgp->dca_enabled)
1475 myri10ge_update_dca(ss);
1476#endif
1477
1293 /* process as many rx events as NAPI will allow */ 1478 /* process as many rx events as NAPI will allow */
1294 work_done = myri10ge_clean_rx_done(ss, budget); 1479 work_done = myri10ge_clean_rx_done(ss, budget);
1295 1480
@@ -1309,6 +1494,13 @@ static irqreturn_t myri10ge_intr(int irq, void *arg)
1309 u32 send_done_count; 1494 u32 send_done_count;
1310 int i; 1495 int i;
1311 1496
1497 /* an interrupt on a non-zero slice is implicitly valid
1498 * since MSI-X irqs are not shared */
1499 if (ss != mgp->ss) {
1500 netif_rx_schedule(ss->dev, &ss->napi);
1501 return (IRQ_HANDLED);
1502 }
1503
1312 /* make sure it is our IRQ, and that the DMA has finished */ 1504 /* make sure it is our IRQ, and that the DMA has finished */
1313 if (unlikely(!stats->valid)) 1505 if (unlikely(!stats->valid))
1314 return (IRQ_NONE); 1506 return (IRQ_NONE);
@@ -1318,7 +1510,7 @@ static irqreturn_t myri10ge_intr(int irq, void *arg)
1318 if (stats->valid & 1) 1510 if (stats->valid & 1)
1319 netif_rx_schedule(ss->dev, &ss->napi); 1511 netif_rx_schedule(ss->dev, &ss->napi);
1320 1512
1321 if (!mgp->msi_enabled) { 1513 if (!mgp->msi_enabled && !mgp->msix_enabled) {
1322 put_be32(0, mgp->irq_deassert); 1514 put_be32(0, mgp->irq_deassert);
1323 if (!myri10ge_deassert_wait) 1515 if (!myri10ge_deassert_wait)
1324 stats->valid = 0; 1516 stats->valid = 0;
@@ -1453,10 +1645,10 @@ myri10ge_get_ringparam(struct net_device *netdev,
1453{ 1645{
1454 struct myri10ge_priv *mgp = netdev_priv(netdev); 1646 struct myri10ge_priv *mgp = netdev_priv(netdev);
1455 1647
1456 ring->rx_mini_max_pending = mgp->ss.rx_small.mask + 1; 1648 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1457 ring->rx_max_pending = mgp->ss.rx_big.mask + 1; 1649 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1458 ring->rx_jumbo_max_pending = 0; 1650 ring->rx_jumbo_max_pending = 0;
1459 ring->tx_max_pending = mgp->ss.rx_small.mask + 1; 1651 ring->tx_max_pending = mgp->ss[0].rx_small.mask + 1;
1460 ring->rx_mini_pending = ring->rx_mini_max_pending; 1652 ring->rx_mini_pending = ring->rx_mini_max_pending;
1461 ring->rx_pending = ring->rx_max_pending; 1653 ring->rx_pending = ring->rx_max_pending;
1462 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending; 1654 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
@@ -1504,9 +1696,12 @@ static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1504 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", 1696 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1505 "tx_heartbeat_errors", "tx_window_errors", 1697 "tx_heartbeat_errors", "tx_window_errors",
1506 /* device-specific stats */ 1698 /* device-specific stats */
1507 "tx_boundary", "WC", "irq", "MSI", 1699 "tx_boundary", "WC", "irq", "MSI", "MSIX",
1508 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs", 1700 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1509 "serial_number", "watchdog_resets", 1701 "serial_number", "watchdog_resets",
1702#ifdef CONFIG_DCA
1703 "dca_capable", "dca_enabled",
1704#endif
1510 "link_changes", "link_up", "dropped_link_overflow", 1705 "link_changes", "link_up", "dropped_link_overflow",
1511 "dropped_link_error_or_filtered", 1706 "dropped_link_error_or_filtered",
1512 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32", 1707 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
@@ -1531,23 +1726,31 @@ static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1531static void 1726static void
1532myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data) 1727myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1533{ 1728{
1729 struct myri10ge_priv *mgp = netdev_priv(netdev);
1730 int i;
1731
1534 switch (stringset) { 1732 switch (stringset) {
1535 case ETH_SS_STATS: 1733 case ETH_SS_STATS:
1536 memcpy(data, *myri10ge_gstrings_main_stats, 1734 memcpy(data, *myri10ge_gstrings_main_stats,
1537 sizeof(myri10ge_gstrings_main_stats)); 1735 sizeof(myri10ge_gstrings_main_stats));
1538 data += sizeof(myri10ge_gstrings_main_stats); 1736 data += sizeof(myri10ge_gstrings_main_stats);
1539 memcpy(data, *myri10ge_gstrings_slice_stats, 1737 for (i = 0; i < mgp->num_slices; i++) {
1540 sizeof(myri10ge_gstrings_slice_stats)); 1738 memcpy(data, *myri10ge_gstrings_slice_stats,
1541 data += sizeof(myri10ge_gstrings_slice_stats); 1739 sizeof(myri10ge_gstrings_slice_stats));
1740 data += sizeof(myri10ge_gstrings_slice_stats);
1741 }
1542 break; 1742 break;
1543 } 1743 }
1544} 1744}
1545 1745
1546static int myri10ge_get_sset_count(struct net_device *netdev, int sset) 1746static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1547{ 1747{
1748 struct myri10ge_priv *mgp = netdev_priv(netdev);
1749
1548 switch (sset) { 1750 switch (sset) {
1549 case ETH_SS_STATS: 1751 case ETH_SS_STATS:
1550 return MYRI10GE_MAIN_STATS_LEN + MYRI10GE_SLICE_STATS_LEN; 1752 return MYRI10GE_MAIN_STATS_LEN +
1753 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1551 default: 1754 default:
1552 return -EOPNOTSUPP; 1755 return -EOPNOTSUPP;
1553 } 1756 }
@@ -1559,6 +1762,7 @@ myri10ge_get_ethtool_stats(struct net_device *netdev,
1559{ 1762{
1560 struct myri10ge_priv *mgp = netdev_priv(netdev); 1763 struct myri10ge_priv *mgp = netdev_priv(netdev);
1561 struct myri10ge_slice_state *ss; 1764 struct myri10ge_slice_state *ss;
1765 int slice;
1562 int i; 1766 int i;
1563 1767
1564 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++) 1768 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
@@ -1568,15 +1772,20 @@ myri10ge_get_ethtool_stats(struct net_device *netdev,
1568 data[i++] = (unsigned int)mgp->wc_enabled; 1772 data[i++] = (unsigned int)mgp->wc_enabled;
1569 data[i++] = (unsigned int)mgp->pdev->irq; 1773 data[i++] = (unsigned int)mgp->pdev->irq;
1570 data[i++] = (unsigned int)mgp->msi_enabled; 1774 data[i++] = (unsigned int)mgp->msi_enabled;
1775 data[i++] = (unsigned int)mgp->msix_enabled;
1571 data[i++] = (unsigned int)mgp->read_dma; 1776 data[i++] = (unsigned int)mgp->read_dma;
1572 data[i++] = (unsigned int)mgp->write_dma; 1777 data[i++] = (unsigned int)mgp->write_dma;
1573 data[i++] = (unsigned int)mgp->read_write_dma; 1778 data[i++] = (unsigned int)mgp->read_write_dma;
1574 data[i++] = (unsigned int)mgp->serial_number; 1779 data[i++] = (unsigned int)mgp->serial_number;
1575 data[i++] = (unsigned int)mgp->watchdog_resets; 1780 data[i++] = (unsigned int)mgp->watchdog_resets;
1781#ifdef CONFIG_DCA
1782 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1783 data[i++] = (unsigned int)(mgp->dca_enabled);
1784#endif
1576 data[i++] = (unsigned int)mgp->link_changes; 1785 data[i++] = (unsigned int)mgp->link_changes;
1577 1786
1578 /* firmware stats are useful only in the first slice */ 1787 /* firmware stats are useful only in the first slice */
1579 ss = &mgp->ss; 1788 ss = &mgp->ss[0];
1580 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up); 1789 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1581 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow); 1790 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1582 data[i++] = 1791 data[i++] =
@@ -1592,24 +1801,27 @@ myri10ge_get_ethtool_stats(struct net_device *netdev,
1592 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer); 1801 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1593 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer); 1802 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1594 1803
1595 data[i++] = 0; 1804 for (slice = 0; slice < mgp->num_slices; slice++) {
1596 data[i++] = (unsigned int)ss->tx.pkt_start; 1805 ss = &mgp->ss[slice];
1597 data[i++] = (unsigned int)ss->tx.pkt_done; 1806 data[i++] = slice;
1598 data[i++] = (unsigned int)ss->tx.req; 1807 data[i++] = (unsigned int)ss->tx.pkt_start;
1599 data[i++] = (unsigned int)ss->tx.done; 1808 data[i++] = (unsigned int)ss->tx.pkt_done;
1600 data[i++] = (unsigned int)ss->rx_small.cnt; 1809 data[i++] = (unsigned int)ss->tx.req;
1601 data[i++] = (unsigned int)ss->rx_big.cnt; 1810 data[i++] = (unsigned int)ss->tx.done;
1602 data[i++] = (unsigned int)ss->tx.wake_queue; 1811 data[i++] = (unsigned int)ss->rx_small.cnt;
1603 data[i++] = (unsigned int)ss->tx.stop_queue; 1812 data[i++] = (unsigned int)ss->rx_big.cnt;
1604 data[i++] = (unsigned int)ss->tx.linearized; 1813 data[i++] = (unsigned int)ss->tx.wake_queue;
1605 data[i++] = ss->rx_done.lro_mgr.stats.aggregated; 1814 data[i++] = (unsigned int)ss->tx.stop_queue;
1606 data[i++] = ss->rx_done.lro_mgr.stats.flushed; 1815 data[i++] = (unsigned int)ss->tx.linearized;
1607 if (ss->rx_done.lro_mgr.stats.flushed) 1816 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1608 data[i++] = ss->rx_done.lro_mgr.stats.aggregated / 1817 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1609 ss->rx_done.lro_mgr.stats.flushed; 1818 if (ss->rx_done.lro_mgr.stats.flushed)
1610 else 1819 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1611 data[i++] = 0; 1820 ss->rx_done.lro_mgr.stats.flushed;
1612 data[i++] = ss->rx_done.lro_mgr.stats.no_desc; 1821 else
1822 data[i++] = 0;
1823 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1824 }
1613} 1825}
1614 1826
1615static void myri10ge_set_msglevel(struct net_device *netdev, u32 value) 1827static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
@@ -1652,12 +1864,15 @@ static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1652 struct net_device *dev = mgp->dev; 1864 struct net_device *dev = mgp->dev;
1653 int tx_ring_size, rx_ring_size; 1865 int tx_ring_size, rx_ring_size;
1654 int tx_ring_entries, rx_ring_entries; 1866 int tx_ring_entries, rx_ring_entries;
1655 int i, status; 1867 int i, slice, status;
1656 size_t bytes; 1868 size_t bytes;
1657 1869
1658 /* get ring sizes */ 1870 /* get ring sizes */
1871 slice = ss - mgp->ss;
1872 cmd.data0 = slice;
1659 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0); 1873 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1660 tx_ring_size = cmd.data0; 1874 tx_ring_size = cmd.data0;
1875 cmd.data0 = slice;
1661 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0); 1876 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1662 if (status != 0) 1877 if (status != 0)
1663 return status; 1878 return status;
@@ -1722,15 +1937,17 @@ static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1722 mgp->small_bytes + MXGEFW_PAD, 0); 1937 mgp->small_bytes + MXGEFW_PAD, 0);
1723 1938
1724 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) { 1939 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
1725 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n", 1940 printk(KERN_ERR
1726 dev->name, ss->rx_small.fill_cnt); 1941 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1942 dev->name, slice, ss->rx_small.fill_cnt);
1727 goto abort_with_rx_small_ring; 1943 goto abort_with_rx_small_ring;
1728 } 1944 }
1729 1945
1730 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0); 1946 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1731 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) { 1947 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
1732 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n", 1948 printk(KERN_ERR
1733 dev->name, ss->rx_big.fill_cnt); 1949 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
1950 dev->name, slice, ss->rx_big.fill_cnt);
1734 goto abort_with_rx_big_ring; 1951 goto abort_with_rx_big_ring;
1735 } 1952 }
1736 1953
@@ -1782,6 +1999,10 @@ static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
1782 struct myri10ge_tx_buf *tx; 1999 struct myri10ge_tx_buf *tx;
1783 int i, len, idx; 2000 int i, len, idx;
1784 2001
2002 /* If not allocated, skip it */
2003 if (ss->tx.req_list == NULL)
2004 return;
2005
1785 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) { 2006 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1786 idx = i & ss->rx_big.mask; 2007 idx = i & ss->rx_big.mask;
1787 if (i == ss->rx_big.fill_cnt - 1) 2008 if (i == ss->rx_big.fill_cnt - 1)
@@ -1844,25 +2065,67 @@ static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
1844static int myri10ge_request_irq(struct myri10ge_priv *mgp) 2065static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1845{ 2066{
1846 struct pci_dev *pdev = mgp->pdev; 2067 struct pci_dev *pdev = mgp->pdev;
2068 struct myri10ge_slice_state *ss;
2069 struct net_device *netdev = mgp->dev;
2070 int i;
1847 int status; 2071 int status;
1848 2072
2073 mgp->msi_enabled = 0;
2074 mgp->msix_enabled = 0;
2075 status = 0;
1849 if (myri10ge_msi) { 2076 if (myri10ge_msi) {
1850 status = pci_enable_msi(pdev); 2077 if (mgp->num_slices > 1) {
1851 if (status != 0) 2078 status =
1852 dev_err(&pdev->dev, 2079 pci_enable_msix(pdev, mgp->msix_vectors,
1853 "Error %d setting up MSI; falling back to xPIC\n", 2080 mgp->num_slices);
1854 status); 2081 if (status == 0) {
1855 else 2082 mgp->msix_enabled = 1;
1856 mgp->msi_enabled = 1; 2083 } else {
1857 } else { 2084 dev_err(&pdev->dev,
1858 mgp->msi_enabled = 0; 2085 "Error %d setting up MSI-X\n", status);
2086 return status;
2087 }
2088 }
2089 if (mgp->msix_enabled == 0) {
2090 status = pci_enable_msi(pdev);
2091 if (status != 0) {
2092 dev_err(&pdev->dev,
2093 "Error %d setting up MSI; falling back to xPIC\n",
2094 status);
2095 } else {
2096 mgp->msi_enabled = 1;
2097 }
2098 }
1859 } 2099 }
1860 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED, 2100 if (mgp->msix_enabled) {
1861 mgp->dev->name, mgp); 2101 for (i = 0; i < mgp->num_slices; i++) {
1862 if (status != 0) { 2102 ss = &mgp->ss[i];
1863 dev_err(&pdev->dev, "failed to allocate IRQ\n"); 2103 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
1864 if (mgp->msi_enabled) 2104 "%s:slice-%d", netdev->name, i);
1865 pci_disable_msi(pdev); 2105 status = request_irq(mgp->msix_vectors[i].vector,
2106 myri10ge_intr, 0, ss->irq_desc,
2107 ss);
2108 if (status != 0) {
2109 dev_err(&pdev->dev,
2110 "slice %d failed to allocate IRQ\n", i);
2111 i--;
2112 while (i >= 0) {
2113 free_irq(mgp->msix_vectors[i].vector,
2114 &mgp->ss[i]);
2115 i--;
2116 }
2117 pci_disable_msix(pdev);
2118 return status;
2119 }
2120 }
2121 } else {
2122 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2123 mgp->dev->name, &mgp->ss[0]);
2124 if (status != 0) {
2125 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2126 if (mgp->msi_enabled)
2127 pci_disable_msi(pdev);
2128 }
1866 } 2129 }
1867 return status; 2130 return status;
1868} 2131}
@@ -1870,10 +2133,18 @@ static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1870static void myri10ge_free_irq(struct myri10ge_priv *mgp) 2133static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1871{ 2134{
1872 struct pci_dev *pdev = mgp->pdev; 2135 struct pci_dev *pdev = mgp->pdev;
2136 int i;
1873 2137
1874 free_irq(pdev->irq, mgp); 2138 if (mgp->msix_enabled) {
2139 for (i = 0; i < mgp->num_slices; i++)
2140 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2141 } else {
2142 free_irq(pdev->irq, &mgp->ss[0]);
2143 }
1875 if (mgp->msi_enabled) 2144 if (mgp->msi_enabled)
1876 pci_disable_msi(pdev); 2145 pci_disable_msi(pdev);
2146 if (mgp->msix_enabled)
2147 pci_disable_msix(pdev);
1877} 2148}
1878 2149
1879static int 2150static int
@@ -1935,12 +2206,82 @@ myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1935 return 0; 2206 return 0;
1936} 2207}
1937 2208
2209static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2210{
2211 struct myri10ge_cmd cmd;
2212 struct myri10ge_slice_state *ss;
2213 int status;
2214
2215 ss = &mgp->ss[slice];
2216 cmd.data0 = 0; /* single slice for now */
2217 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
2218 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2219 (mgp->sram + cmd.data0);
2220
2221 cmd.data0 = slice;
2222 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2223 &cmd, 0);
2224 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2225 (mgp->sram + cmd.data0);
2226
2227 cmd.data0 = slice;
2228 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2229 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2230 (mgp->sram + cmd.data0);
2231
2232 if (myri10ge_wcfifo && mgp->wc_enabled) {
2233 ss->tx.wc_fifo = (u8 __iomem *)
2234 mgp->sram + MXGEFW_ETH_SEND_4 + 64 * slice;
2235 ss->rx_small.wc_fifo = (u8 __iomem *)
2236 mgp->sram + MXGEFW_ETH_RECV_SMALL + 64 * slice;
2237 ss->rx_big.wc_fifo = (u8 __iomem *)
2238 mgp->sram + MXGEFW_ETH_RECV_BIG + 64 * slice;
2239 } else {
2240 ss->tx.wc_fifo = NULL;
2241 ss->rx_small.wc_fifo = NULL;
2242 ss->rx_big.wc_fifo = NULL;
2243 }
2244 return status;
2245
2246}
2247
2248static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2249{
2250 struct myri10ge_cmd cmd;
2251 struct myri10ge_slice_state *ss;
2252 int status;
2253
2254 ss = &mgp->ss[slice];
2255 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2256 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2257 cmd.data2 = sizeof(struct mcp_irq_data);
2258 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2259 if (status == -ENOSYS) {
2260 dma_addr_t bus = ss->fw_stats_bus;
2261 if (slice != 0)
2262 return -EINVAL;
2263 bus += offsetof(struct mcp_irq_data, send_done_count);
2264 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2265 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2266 status = myri10ge_send_cmd(mgp,
2267 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2268 &cmd, 0);
2269 /* Firmware cannot support multicast without STATS_DMA_V2 */
2270 mgp->fw_multicast_support = 0;
2271 } else {
2272 mgp->fw_multicast_support = 1;
2273 }
2274 return 0;
2275}
2276
1938static int myri10ge_open(struct net_device *dev) 2277static int myri10ge_open(struct net_device *dev)
1939{ 2278{
2279 struct myri10ge_slice_state *ss;
1940 struct myri10ge_priv *mgp = netdev_priv(dev); 2280 struct myri10ge_priv *mgp = netdev_priv(dev);
1941 struct myri10ge_cmd cmd; 2281 struct myri10ge_cmd cmd;
2282 int i, status, big_pow2, slice;
2283 u8 *itable;
1942 struct net_lro_mgr *lro_mgr; 2284 struct net_lro_mgr *lro_mgr;
1943 int status, big_pow2;
1944 2285
1945 if (mgp->running != MYRI10GE_ETH_STOPPED) 2286 if (mgp->running != MYRI10GE_ETH_STOPPED)
1946 return -EBUSY; 2287 return -EBUSY;
@@ -1952,6 +2293,48 @@ static int myri10ge_open(struct net_device *dev)
1952 goto abort_with_nothing; 2293 goto abort_with_nothing;
1953 } 2294 }
1954 2295
2296 if (mgp->num_slices > 1) {
2297 cmd.data0 = mgp->num_slices;
2298 cmd.data1 = 1; /* use MSI-X */
2299 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2300 &cmd, 0);
2301 if (status != 0) {
2302 printk(KERN_ERR
2303 "myri10ge: %s: failed to set number of slices\n",
2304 dev->name);
2305 goto abort_with_nothing;
2306 }
2307 /* setup the indirection table */
2308 cmd.data0 = mgp->num_slices;
2309 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2310 &cmd, 0);
2311
2312 status |= myri10ge_send_cmd(mgp,
2313 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2314 &cmd, 0);
2315 if (status != 0) {
2316 printk(KERN_ERR
2317 "myri10ge: %s: failed to setup rss tables\n",
2318 dev->name);
2319 }
2320
2321 /* just enable an identity mapping */
2322 itable = mgp->sram + cmd.data0;
2323 for (i = 0; i < mgp->num_slices; i++)
2324 __raw_writeb(i, &itable[i]);
2325
2326 cmd.data0 = 1;
2327 cmd.data1 = myri10ge_rss_hash;
2328 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2329 &cmd, 0);
2330 if (status != 0) {
2331 printk(KERN_ERR
2332 "myri10ge: %s: failed to enable slices\n",
2333 dev->name);
2334 goto abort_with_nothing;
2335 }
2336 }
2337
1955 status = myri10ge_request_irq(mgp); 2338 status = myri10ge_request_irq(mgp);
1956 if (status != 0) 2339 if (status != 0)
1957 goto abort_with_nothing; 2340 goto abort_with_nothing;
@@ -1975,41 +2358,6 @@ static int myri10ge_open(struct net_device *dev)
1975 if (myri10ge_small_bytes > 0) 2358 if (myri10ge_small_bytes > 0)
1976 mgp->small_bytes = myri10ge_small_bytes; 2359 mgp->small_bytes = myri10ge_small_bytes;
1977 2360
1978 /* get the lanai pointers to the send and receive rings */
1979
1980 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1981 mgp->ss.tx.lanai =
1982 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1983
1984 status |=
1985 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1986 mgp->ss.rx_small.lanai =
1987 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1988
1989 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1990 mgp->ss.rx_big.lanai =
1991 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1992
1993 if (status != 0) {
1994 printk(KERN_ERR
1995 "myri10ge: %s: failed to get ring sizes or locations\n",
1996 dev->name);
1997 mgp->running = MYRI10GE_ETH_STOPPED;
1998 goto abort_with_irq;
1999 }
2000
2001 if (myri10ge_wcfifo && mgp->wc_enabled) {
2002 mgp->ss.tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
2003 mgp->ss.rx_small.wc_fifo =
2004 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
2005 mgp->ss.rx_big.wc_fifo =
2006 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
2007 } else {
2008 mgp->ss.tx.wc_fifo = NULL;
2009 mgp->ss.rx_small.wc_fifo = NULL;
2010 mgp->ss.rx_big.wc_fifo = NULL;
2011 }
2012
2013 /* Firmware needs the big buff size as a power of 2. Lie and 2361 /* Firmware needs the big buff size as a power of 2. Lie and
2014 * tell him the buffer is larger, because we only use 1 2362 * tell him the buffer is larger, because we only use 1
2015 * buffer/pkt, and the mtu will prevent overruns. 2363 * buffer/pkt, and the mtu will prevent overruns.
@@ -2024,9 +2372,44 @@ static int myri10ge_open(struct net_device *dev)
2024 mgp->big_bytes = big_pow2; 2372 mgp->big_bytes = big_pow2;
2025 } 2373 }
2026 2374
2027 status = myri10ge_allocate_rings(&mgp->ss); 2375 /* setup the per-slice data structures */
2028 if (status != 0) 2376 for (slice = 0; slice < mgp->num_slices; slice++) {
2029 goto abort_with_irq; 2377 ss = &mgp->ss[slice];
2378
2379 status = myri10ge_get_txrx(mgp, slice);
2380 if (status != 0) {
2381 printk(KERN_ERR
2382 "myri10ge: %s: failed to get ring sizes or locations\n",
2383 dev->name);
2384 goto abort_with_rings;
2385 }
2386 status = myri10ge_allocate_rings(ss);
2387 if (status != 0)
2388 goto abort_with_rings;
2389 if (slice == 0)
2390 status = myri10ge_set_stats(mgp, slice);
2391 if (status) {
2392 printk(KERN_ERR
2393 "myri10ge: %s: Couldn't set stats DMA\n",
2394 dev->name);
2395 goto abort_with_rings;
2396 }
2397
2398 lro_mgr = &ss->rx_done.lro_mgr;
2399 lro_mgr->dev = dev;
2400 lro_mgr->features = LRO_F_NAPI;
2401 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2402 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2403 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2404 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2405 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2406 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2407 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2408 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2409
2410 /* must happen prior to any irq */
2411 napi_enable(&(ss)->napi);
2412 }
2030 2413
2031 /* now give firmware buffers sizes, and MTU */ 2414 /* now give firmware buffers sizes, and MTU */
2032 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN; 2415 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
@@ -2043,25 +2426,15 @@ static int myri10ge_open(struct net_device *dev)
2043 goto abort_with_rings; 2426 goto abort_with_rings;
2044 } 2427 }
2045 2428
2046 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->ss.fw_stats_bus); 2429 /*
2047 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->ss.fw_stats_bus); 2430 * Set Linux style TSO mode; this is needed only on newer
2048 cmd.data2 = sizeof(struct mcp_irq_data); 2431 * firmware versions. Older versions default to Linux
2049 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0); 2432 * style TSO
2050 if (status == -ENOSYS) { 2433 */
2051 dma_addr_t bus = mgp->ss.fw_stats_bus; 2434 cmd.data0 = 0;
2052 bus += offsetof(struct mcp_irq_data, send_done_count); 2435 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2053 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus); 2436 if (status && status != -ENOSYS) {
2054 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus); 2437 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
2055 status = myri10ge_send_cmd(mgp,
2056 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2057 &cmd, 0);
2058 /* Firmware cannot support multicast without STATS_DMA_V2 */
2059 mgp->fw_multicast_support = 0;
2060 } else {
2061 mgp->fw_multicast_support = 1;
2062 }
2063 if (status) {
2064 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
2065 dev->name); 2438 dev->name);
2066 goto abort_with_rings; 2439 goto abort_with_rings;
2067 } 2440 }
@@ -2069,21 +2442,6 @@ static int myri10ge_open(struct net_device *dev)
2069 mgp->link_state = ~0U; 2442 mgp->link_state = ~0U;
2070 mgp->rdma_tags_available = 15; 2443 mgp->rdma_tags_available = 15;
2071 2444
2072 lro_mgr = &mgp->ss.rx_done.lro_mgr;
2073 lro_mgr->dev = dev;
2074 lro_mgr->features = LRO_F_NAPI;
2075 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2076 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2077 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2078 lro_mgr->lro_arr = mgp->ss.rx_done.lro_desc;
2079 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2080 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2081 lro_mgr->frag_align_pad = 2;
2082 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2083 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2084
2085 napi_enable(&mgp->ss.napi); /* must happen prior to any irq */
2086
2087 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0); 2445 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2088 if (status) { 2446 if (status) {
2089 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n", 2447 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
@@ -2091,8 +2449,6 @@ static int myri10ge_open(struct net_device *dev)
2091 goto abort_with_rings; 2449 goto abort_with_rings;
2092 } 2450 }
2093 2451
2094 mgp->ss.tx.wake_queue = 0;
2095 mgp->ss.tx.stop_queue = 0;
2096 mgp->running = MYRI10GE_ETH_RUNNING; 2452 mgp->running = MYRI10GE_ETH_RUNNING;
2097 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ; 2453 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2098 add_timer(&mgp->watchdog_timer); 2454 add_timer(&mgp->watchdog_timer);
@@ -2100,9 +2456,9 @@ static int myri10ge_open(struct net_device *dev)
2100 return 0; 2456 return 0;
2101 2457
2102abort_with_rings: 2458abort_with_rings:
2103 myri10ge_free_rings(&mgp->ss); 2459 for (i = 0; i < mgp->num_slices; i++)
2460 myri10ge_free_rings(&mgp->ss[i]);
2104 2461
2105abort_with_irq:
2106 myri10ge_free_irq(mgp); 2462 myri10ge_free_irq(mgp);
2107 2463
2108abort_with_nothing: 2464abort_with_nothing:
@@ -2115,16 +2471,19 @@ static int myri10ge_close(struct net_device *dev)
2115 struct myri10ge_priv *mgp = netdev_priv(dev); 2471 struct myri10ge_priv *mgp = netdev_priv(dev);
2116 struct myri10ge_cmd cmd; 2472 struct myri10ge_cmd cmd;
2117 int status, old_down_cnt; 2473 int status, old_down_cnt;
2474 int i;
2118 2475
2119 if (mgp->running != MYRI10GE_ETH_RUNNING) 2476 if (mgp->running != MYRI10GE_ETH_RUNNING)
2120 return 0; 2477 return 0;
2121 2478
2122 if (mgp->ss.tx.req_bytes == NULL) 2479 if (mgp->ss[0].tx.req_bytes == NULL)
2123 return 0; 2480 return 0;
2124 2481
2125 del_timer_sync(&mgp->watchdog_timer); 2482 del_timer_sync(&mgp->watchdog_timer);
2126 mgp->running = MYRI10GE_ETH_STOPPING; 2483 mgp->running = MYRI10GE_ETH_STOPPING;
2127 napi_disable(&mgp->ss.napi); 2484 for (i = 0; i < mgp->num_slices; i++) {
2485 napi_disable(&mgp->ss[i].napi);
2486 }
2128 netif_carrier_off(dev); 2487 netif_carrier_off(dev);
2129 netif_stop_queue(dev); 2488 netif_stop_queue(dev);
2130 old_down_cnt = mgp->down_cnt; 2489 old_down_cnt = mgp->down_cnt;
@@ -2140,7 +2499,8 @@ static int myri10ge_close(struct net_device *dev)
2140 2499
2141 netif_tx_disable(dev); 2500 netif_tx_disable(dev);
2142 myri10ge_free_irq(mgp); 2501 myri10ge_free_irq(mgp);
2143 myri10ge_free_rings(&mgp->ss); 2502 for (i = 0; i < mgp->num_slices; i++)
2503 myri10ge_free_rings(&mgp->ss[i]);
2144 2504
2145 mgp->running = MYRI10GE_ETH_STOPPED; 2505 mgp->running = MYRI10GE_ETH_STOPPED;
2146 return 0; 2506 return 0;
@@ -2261,7 +2621,7 @@ static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2261 u8 flags, odd_flag; 2621 u8 flags, odd_flag;
2262 2622
2263 /* always transmit through slot 0 */ 2623 /* always transmit through slot 0 */
2264 ss = &mgp->ss; 2624 ss = mgp->ss;
2265 tx = &ss->tx; 2625 tx = &ss->tx;
2266again: 2626again:
2267 req = tx->req_list; 2627 req = tx->req_list;
@@ -2566,7 +2926,21 @@ drop:
2566static struct net_device_stats *myri10ge_get_stats(struct net_device *dev) 2926static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2567{ 2927{
2568 struct myri10ge_priv *mgp = netdev_priv(dev); 2928 struct myri10ge_priv *mgp = netdev_priv(dev);
2569 return &mgp->stats; 2929 struct myri10ge_slice_netstats *slice_stats;
2930 struct net_device_stats *stats = &mgp->stats;
2931 int i;
2932
2933 memset(stats, 0, sizeof(*stats));
2934 for (i = 0; i < mgp->num_slices; i++) {
2935 slice_stats = &mgp->ss[i].stats;
2936 stats->rx_packets += slice_stats->rx_packets;
2937 stats->tx_packets += slice_stats->tx_packets;
2938 stats->rx_bytes += slice_stats->rx_bytes;
2939 stats->tx_bytes += slice_stats->tx_bytes;
2940 stats->rx_dropped += slice_stats->rx_dropped;
2941 stats->tx_dropped += slice_stats->tx_dropped;
2942 }
2943 return stats;
2570} 2944}
2571 2945
2572static void myri10ge_set_multicast_list(struct net_device *dev) 2946static void myri10ge_set_multicast_list(struct net_device *dev)
@@ -2777,10 +3151,10 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2777 * 3151 *
2778 * If the driver can neither enable ECRC nor verify that it has 3152 * If the driver can neither enable ECRC nor verify that it has
2779 * already been enabled, then it must use a firmware image which works 3153 * already been enabled, then it must use a firmware image which works
2780 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it 3154 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
2781 * should also ensure that it never gives the device a Read-DMA which is 3155 * should also ensure that it never gives the device a Read-DMA which is
2782 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is 3156 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
2783 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat) 3157 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
2784 * firmware image, and set tx_boundary to 4KB. 3158 * firmware image, and set tx_boundary to 4KB.
2785 */ 3159 */
2786 3160
@@ -2809,7 +3183,7 @@ static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
2809 * completions) in order to see if it works on this host. 3183 * completions) in order to see if it works on this host.
2810 */ 3184 */
2811 mgp->fw_name = myri10ge_fw_aligned; 3185 mgp->fw_name = myri10ge_fw_aligned;
2812 status = myri10ge_load_firmware(mgp); 3186 status = myri10ge_load_firmware(mgp, 1);
2813 if (status != 0) { 3187 if (status != 0) {
2814 goto abort; 3188 goto abort;
2815 } 3189 }
@@ -2990,6 +3364,7 @@ static void myri10ge_watchdog(struct work_struct *work)
2990 struct myri10ge_tx_buf *tx; 3364 struct myri10ge_tx_buf *tx;
2991 u32 reboot; 3365 u32 reboot;
2992 int status; 3366 int status;
3367 int i;
2993 u16 cmd, vendor; 3368 u16 cmd, vendor;
2994 3369
2995 mgp->watchdog_resets++; 3370 mgp->watchdog_resets++;
@@ -3037,20 +3412,26 @@ static void myri10ge_watchdog(struct work_struct *work)
3037 3412
3038 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n", 3413 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3039 mgp->dev->name); 3414 mgp->dev->name);
3040 tx = &mgp->ss.tx; 3415 for (i = 0; i < mgp->num_slices; i++) {
3041 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n", 3416 tx = &mgp->ss[i].tx;
3042 mgp->dev->name, tx->req, tx->done, 3417 printk(KERN_INFO
3043 tx->pkt_start, tx->pkt_done, 3418 "myri10ge: %s: (%d): %d %d %d %d %d\n",
3044 (int)ntohl(mgp->ss.fw_stats->send_done_count)); 3419 mgp->dev->name, i, tx->req, tx->done,
3045 msleep(2000); 3420 tx->pkt_start, tx->pkt_done,
3046 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n", 3421 (int)ntohl(mgp->ss[i].fw_stats->
3047 mgp->dev->name, tx->req, tx->done, 3422 send_done_count));
3048 tx->pkt_start, tx->pkt_done, 3423 msleep(2000);
3049 (int)ntohl(mgp->ss.fw_stats->send_done_count)); 3424 printk(KERN_INFO
3425 "myri10ge: %s: (%d): %d %d %d %d %d\n",
3426 mgp->dev->name, i, tx->req, tx->done,
3427 tx->pkt_start, tx->pkt_done,
3428 (int)ntohl(mgp->ss[i].fw_stats->
3429 send_done_count));
3430 }
3050 } 3431 }
3051 rtnl_lock(); 3432 rtnl_lock();
3052 myri10ge_close(mgp->dev); 3433 myri10ge_close(mgp->dev);
3053 status = myri10ge_load_firmware(mgp); 3434 status = myri10ge_load_firmware(mgp, 1);
3054 if (status != 0) 3435 if (status != 0)
3055 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n", 3436 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3056 mgp->dev->name); 3437 mgp->dev->name);
@@ -3070,47 +3451,241 @@ static void myri10ge_watchdog_timer(unsigned long arg)
3070{ 3451{
3071 struct myri10ge_priv *mgp; 3452 struct myri10ge_priv *mgp;
3072 struct myri10ge_slice_state *ss; 3453 struct myri10ge_slice_state *ss;
3454 int i, reset_needed;
3073 u32 rx_pause_cnt; 3455 u32 rx_pause_cnt;
3074 3456
3075 mgp = (struct myri10ge_priv *)arg; 3457 mgp = (struct myri10ge_priv *)arg;
3076 3458
3077 rx_pause_cnt = ntohl(mgp->ss.fw_stats->dropped_pause); 3459 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3460 for (i = 0, reset_needed = 0;
3461 i < mgp->num_slices && reset_needed == 0; ++i) {
3462
3463 ss = &mgp->ss[i];
3464 if (ss->rx_small.watchdog_needed) {
3465 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3466 mgp->small_bytes + MXGEFW_PAD,
3467 1);
3468 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3469 myri10ge_fill_thresh)
3470 ss->rx_small.watchdog_needed = 0;
3471 }
3472 if (ss->rx_big.watchdog_needed) {
3473 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3474 mgp->big_bytes, 1);
3475 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3476 myri10ge_fill_thresh)
3477 ss->rx_big.watchdog_needed = 0;
3478 }
3078 3479
3079 ss = &mgp->ss; 3480 if (ss->tx.req != ss->tx.done &&
3080 if (ss->rx_small.watchdog_needed) { 3481 ss->tx.done == ss->watchdog_tx_done &&
3081 myri10ge_alloc_rx_pages(mgp, &ss->rx_small, 3482 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3082 mgp->small_bytes + MXGEFW_PAD, 1); 3483 /* nic seems like it might be stuck.. */
3083 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >= 3484 if (rx_pause_cnt != mgp->watchdog_pause) {
3084 myri10ge_fill_thresh) 3485 if (net_ratelimit())
3085 ss->rx_small.watchdog_needed = 0; 3486 printk(KERN_WARNING "myri10ge %s:"
3086 } 3487 "TX paused, check link partner\n",
3087 if (ss->rx_big.watchdog_needed) { 3488 mgp->dev->name);
3088 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 1); 3489 } else {
3089 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >= 3490 reset_needed = 1;
3090 myri10ge_fill_thresh) 3491 }
3091 ss->rx_big.watchdog_needed = 0;
3092 }
3093
3094 if (ss->tx.req != ss->tx.done &&
3095 ss->tx.done == ss->watchdog_tx_done &&
3096 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3097 /* nic seems like it might be stuck.. */
3098 if (rx_pause_cnt != mgp->watchdog_pause) {
3099 if (net_ratelimit())
3100 printk(KERN_WARNING "myri10ge %s:"
3101 "TX paused, check link partner\n",
3102 mgp->dev->name);
3103 } else {
3104 schedule_work(&mgp->watchdog_work);
3105 return;
3106 } 3492 }
3493 ss->watchdog_tx_done = ss->tx.done;
3494 ss->watchdog_tx_req = ss->tx.req;
3107 } 3495 }
3108 /* rearm timer */
3109 mod_timer(&mgp->watchdog_timer,
3110 jiffies + myri10ge_watchdog_timeout * HZ);
3111 ss->watchdog_tx_done = ss->tx.done;
3112 ss->watchdog_tx_req = ss->tx.req;
3113 mgp->watchdog_pause = rx_pause_cnt; 3496 mgp->watchdog_pause = rx_pause_cnt;
3497
3498 if (reset_needed) {
3499 schedule_work(&mgp->watchdog_work);
3500 } else {
3501 /* rearm timer */
3502 mod_timer(&mgp->watchdog_timer,
3503 jiffies + myri10ge_watchdog_timeout * HZ);
3504 }
3505}
3506
3507static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3508{
3509 struct myri10ge_slice_state *ss;
3510 struct pci_dev *pdev = mgp->pdev;
3511 size_t bytes;
3512 int i;
3513
3514 if (mgp->ss == NULL)
3515 return;
3516
3517 for (i = 0; i < mgp->num_slices; i++) {
3518 ss = &mgp->ss[i];
3519 if (ss->rx_done.entry != NULL) {
3520 bytes = mgp->max_intr_slots *
3521 sizeof(*ss->rx_done.entry);
3522 dma_free_coherent(&pdev->dev, bytes,
3523 ss->rx_done.entry, ss->rx_done.bus);
3524 ss->rx_done.entry = NULL;
3525 }
3526 if (ss->fw_stats != NULL) {
3527 bytes = sizeof(*ss->fw_stats);
3528 dma_free_coherent(&pdev->dev, bytes,
3529 ss->fw_stats, ss->fw_stats_bus);
3530 ss->fw_stats = NULL;
3531 }
3532 }
3533 kfree(mgp->ss);
3534 mgp->ss = NULL;
3535}
3536
3537static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3538{
3539 struct myri10ge_slice_state *ss;
3540 struct pci_dev *pdev = mgp->pdev;
3541 size_t bytes;
3542 int i;
3543
3544 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3545 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3546 if (mgp->ss == NULL) {
3547 return -ENOMEM;
3548 }
3549
3550 for (i = 0; i < mgp->num_slices; i++) {
3551 ss = &mgp->ss[i];
3552 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3553 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3554 &ss->rx_done.bus,
3555 GFP_KERNEL);
3556 if (ss->rx_done.entry == NULL)
3557 goto abort;
3558 memset(ss->rx_done.entry, 0, bytes);
3559 bytes = sizeof(*ss->fw_stats);
3560 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3561 &ss->fw_stats_bus,
3562 GFP_KERNEL);
3563 if (ss->fw_stats == NULL)
3564 goto abort;
3565 ss->mgp = mgp;
3566 ss->dev = mgp->dev;
3567 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3568 myri10ge_napi_weight);
3569 }
3570 return 0;
3571abort:
3572 myri10ge_free_slices(mgp);
3573 return -ENOMEM;
3574}
3575
3576/*
3577 * This function determines the number of slices supported.
3578 * The number slices is the minumum of the number of CPUS,
3579 * the number of MSI-X irqs supported, the number of slices
3580 * supported by the firmware
3581 */
3582static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3583{
3584 struct myri10ge_cmd cmd;
3585 struct pci_dev *pdev = mgp->pdev;
3586 char *old_fw;
3587 int i, status, ncpus, msix_cap;
3588
3589 mgp->num_slices = 1;
3590 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3591 ncpus = num_online_cpus();
3592
3593 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3594 (myri10ge_max_slices == -1 && ncpus < 2))
3595 return;
3596
3597 /* try to load the slice aware rss firmware */
3598 old_fw = mgp->fw_name;
3599 if (old_fw == myri10ge_fw_aligned)
3600 mgp->fw_name = myri10ge_fw_rss_aligned;
3601 else
3602 mgp->fw_name = myri10ge_fw_rss_unaligned;
3603 status = myri10ge_load_firmware(mgp, 0);
3604 if (status != 0) {
3605 dev_info(&pdev->dev, "Rss firmware not found\n");
3606 return;
3607 }
3608
3609 /* hit the board with a reset to ensure it is alive */
3610 memset(&cmd, 0, sizeof(cmd));
3611 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3612 if (status != 0) {
3613 dev_err(&mgp->pdev->dev, "failed reset\n");
3614 goto abort_with_fw;
3615 return;
3616 }
3617
3618 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3619
3620 /* tell it the size of the interrupt queues */
3621 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3622 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3623 if (status != 0) {
3624 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3625 goto abort_with_fw;
3626 }
3627
3628 /* ask the maximum number of slices it supports */
3629 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3630 if (status != 0)
3631 goto abort_with_fw;
3632 else
3633 mgp->num_slices = cmd.data0;
3634
3635 /* Only allow multiple slices if MSI-X is usable */
3636 if (!myri10ge_msi) {
3637 goto abort_with_fw;
3638 }
3639
3640 /* if the admin did not specify a limit to how many
3641 * slices we should use, cap it automatically to the
3642 * number of CPUs currently online */
3643 if (myri10ge_max_slices == -1)
3644 myri10ge_max_slices = ncpus;
3645
3646 if (mgp->num_slices > myri10ge_max_slices)
3647 mgp->num_slices = myri10ge_max_slices;
3648
3649 /* Now try to allocate as many MSI-X vectors as we have
3650 * slices. We give up on MSI-X if we can only get a single
3651 * vector. */
3652
3653 mgp->msix_vectors = kzalloc(mgp->num_slices *
3654 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3655 if (mgp->msix_vectors == NULL)
3656 goto disable_msix;
3657 for (i = 0; i < mgp->num_slices; i++) {
3658 mgp->msix_vectors[i].entry = i;
3659 }
3660
3661 while (mgp->num_slices > 1) {
3662 /* make sure it is a power of two */
3663 while (!is_power_of_2(mgp->num_slices))
3664 mgp->num_slices--;
3665 if (mgp->num_slices == 1)
3666 goto disable_msix;
3667 status = pci_enable_msix(pdev, mgp->msix_vectors,
3668 mgp->num_slices);
3669 if (status == 0) {
3670 pci_disable_msix(pdev);
3671 return;
3672 }
3673 if (status > 0)
3674 mgp->num_slices = status;
3675 else
3676 goto disable_msix;
3677 }
3678
3679disable_msix:
3680 if (mgp->msix_vectors != NULL) {
3681 kfree(mgp->msix_vectors);
3682 mgp->msix_vectors = NULL;
3683 }
3684
3685abort_with_fw:
3686 mgp->num_slices = 1;
3687 mgp->fw_name = old_fw;
3688 myri10ge_load_firmware(mgp, 0);
3114} 3689}
3115 3690
3116static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3691static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
@@ -3118,7 +3693,6 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3118 struct net_device *netdev; 3693 struct net_device *netdev;
3119 struct myri10ge_priv *mgp; 3694 struct myri10ge_priv *mgp;
3120 struct device *dev = &pdev->dev; 3695 struct device *dev = &pdev->dev;
3121 size_t bytes;
3122 int i; 3696 int i;
3123 int status = -ENXIO; 3697 int status = -ENXIO;
3124 int dac_enabled; 3698 int dac_enabled;
@@ -3133,7 +3707,6 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3133 3707
3134 mgp = netdev_priv(netdev); 3708 mgp = netdev_priv(netdev);
3135 mgp->dev = netdev; 3709 mgp->dev = netdev;
3136 netif_napi_add(netdev, &mgp->ss.napi, myri10ge_poll, myri10ge_napi_weight);
3137 mgp->pdev = pdev; 3710 mgp->pdev = pdev;
3138 mgp->csum_flag = MXGEFW_FLAGS_CKSUM; 3711 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3139 mgp->pause = myri10ge_flow_control; 3712 mgp->pause = myri10ge_flow_control;
@@ -3179,11 +3752,6 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3179 if (mgp->cmd == NULL) 3752 if (mgp->cmd == NULL)
3180 goto abort_with_netdev; 3753 goto abort_with_netdev;
3181 3754
3182 mgp->ss.fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3183 &mgp->ss.fw_stats_bus, GFP_KERNEL);
3184 if (mgp->ss.fw_stats == NULL)
3185 goto abort_with_cmd;
3186
3187 mgp->board_span = pci_resource_len(pdev, 0); 3755 mgp->board_span = pci_resource_len(pdev, 0);
3188 mgp->iomem_base = pci_resource_start(pdev, 0); 3756 mgp->iomem_base = pci_resource_start(pdev, 0);
3189 mgp->mtrr = -1; 3757 mgp->mtrr = -1;
@@ -3220,28 +3788,28 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3220 for (i = 0; i < ETH_ALEN; i++) 3788 for (i = 0; i < ETH_ALEN; i++)
3221 netdev->dev_addr[i] = mgp->mac_addr[i]; 3789 netdev->dev_addr[i] = mgp->mac_addr[i];
3222 3790
3223 /* allocate rx done ring */
3224 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3225 mgp->ss.rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3226 &mgp->ss.rx_done.bus, GFP_KERNEL);
3227 if (mgp->ss.rx_done.entry == NULL)
3228 goto abort_with_ioremap;
3229 memset(mgp->ss.rx_done.entry, 0, bytes);
3230
3231 myri10ge_select_firmware(mgp); 3791 myri10ge_select_firmware(mgp);
3232 3792
3233 status = myri10ge_load_firmware(mgp); 3793 status = myri10ge_load_firmware(mgp, 1);
3234 if (status != 0) { 3794 if (status != 0) {
3235 dev_err(&pdev->dev, "failed to load firmware\n"); 3795 dev_err(&pdev->dev, "failed to load firmware\n");
3236 goto abort_with_rx_done; 3796 goto abort_with_ioremap;
3797 }
3798 myri10ge_probe_slices(mgp);
3799 status = myri10ge_alloc_slices(mgp);
3800 if (status != 0) {
3801 dev_err(&pdev->dev, "failed to alloc slice state\n");
3802 goto abort_with_firmware;
3237 } 3803 }
3238 3804
3239 status = myri10ge_reset(mgp); 3805 status = myri10ge_reset(mgp);
3240 if (status != 0) { 3806 if (status != 0) {
3241 dev_err(&pdev->dev, "failed reset\n"); 3807 dev_err(&pdev->dev, "failed reset\n");
3242 goto abort_with_firmware; 3808 goto abort_with_slices;
3243 } 3809 }
3244 3810#ifdef CONFIG_DCA
3811 myri10ge_setup_dca(mgp);
3812#endif
3245 pci_set_drvdata(pdev, mgp); 3813 pci_set_drvdata(pdev, mgp);
3246 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU) 3814 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3247 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN; 3815 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
@@ -3284,24 +3852,27 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3284 dev_err(&pdev->dev, "register_netdev failed: %d\n", status); 3852 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3285 goto abort_with_state; 3853 goto abort_with_state;
3286 } 3854 }
3287 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n", 3855 if (mgp->msix_enabled)
3288 (mgp->msi_enabled ? "MSI" : "xPIC"), 3856 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3289 netdev->irq, mgp->tx_boundary, mgp->fw_name, 3857 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3290 (mgp->wc_enabled ? "Enabled" : "Disabled")); 3858 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3859 else
3860 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3861 mgp->msi_enabled ? "MSI" : "xPIC",
3862 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3863 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3291 3864
3292 return 0; 3865 return 0;
3293 3866
3294abort_with_state: 3867abort_with_state:
3295 pci_restore_state(pdev); 3868 pci_restore_state(pdev);
3296 3869
3870abort_with_slices:
3871 myri10ge_free_slices(mgp);
3872
3297abort_with_firmware: 3873abort_with_firmware:
3298 myri10ge_dummy_rdma(mgp, 0); 3874 myri10ge_dummy_rdma(mgp, 0);
3299 3875
3300abort_with_rx_done:
3301 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3302 dma_free_coherent(&pdev->dev, bytes,
3303 mgp->ss.rx_done.entry, mgp->ss.rx_done.bus);
3304
3305abort_with_ioremap: 3876abort_with_ioremap:
3306 iounmap(mgp->sram); 3877 iounmap(mgp->sram);
3307 3878
@@ -3310,10 +3881,6 @@ abort_with_wc:
3310 if (mgp->mtrr >= 0) 3881 if (mgp->mtrr >= 0)
3311 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span); 3882 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3312#endif 3883#endif
3313 dma_free_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3314 mgp->ss.fw_stats, mgp->ss.fw_stats_bus);
3315
3316abort_with_cmd:
3317 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd), 3884 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3318 mgp->cmd, mgp->cmd_bus); 3885 mgp->cmd, mgp->cmd_bus);
3319 3886
@@ -3334,7 +3901,6 @@ static void myri10ge_remove(struct pci_dev *pdev)
3334{ 3901{
3335 struct myri10ge_priv *mgp; 3902 struct myri10ge_priv *mgp;
3336 struct net_device *netdev; 3903 struct net_device *netdev;
3337 size_t bytes;
3338 3904
3339 mgp = pci_get_drvdata(pdev); 3905 mgp = pci_get_drvdata(pdev);
3340 if (mgp == NULL) 3906 if (mgp == NULL)
@@ -3344,24 +3910,23 @@ static void myri10ge_remove(struct pci_dev *pdev)
3344 netdev = mgp->dev; 3910 netdev = mgp->dev;
3345 unregister_netdev(netdev); 3911 unregister_netdev(netdev);
3346 3912
3913#ifdef CONFIG_DCA
3914 myri10ge_teardown_dca(mgp);
3915#endif
3347 myri10ge_dummy_rdma(mgp, 0); 3916 myri10ge_dummy_rdma(mgp, 0);
3348 3917
3349 /* avoid a memory leak */ 3918 /* avoid a memory leak */
3350 pci_restore_state(pdev); 3919 pci_restore_state(pdev);
3351 3920
3352 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3353 dma_free_coherent(&pdev->dev, bytes,
3354 mgp->ss.rx_done.entry, mgp->ss.rx_done.bus);
3355
3356 iounmap(mgp->sram); 3921 iounmap(mgp->sram);
3357 3922
3358#ifdef CONFIG_MTRR 3923#ifdef CONFIG_MTRR
3359 if (mgp->mtrr >= 0) 3924 if (mgp->mtrr >= 0)
3360 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span); 3925 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3361#endif 3926#endif
3362 dma_free_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats), 3927 myri10ge_free_slices(mgp);
3363 mgp->ss.fw_stats, mgp->ss.fw_stats_bus); 3928 if (mgp->msix_vectors != NULL)
3364 3929 kfree(mgp->msix_vectors);
3365 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd), 3930 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3366 mgp->cmd, mgp->cmd_bus); 3931 mgp->cmd, mgp->cmd_bus);
3367 3932
@@ -3390,10 +3955,42 @@ static struct pci_driver myri10ge_driver = {
3390#endif 3955#endif
3391}; 3956};
3392 3957
3958#ifdef CONFIG_DCA
3959static int
3960myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
3961{
3962 int err = driver_for_each_device(&myri10ge_driver.driver,
3963 NULL, &event,
3964 myri10ge_notify_dca_device);
3965
3966 if (err)
3967 return NOTIFY_BAD;
3968 return NOTIFY_DONE;
3969}
3970
3971static struct notifier_block myri10ge_dca_notifier = {
3972 .notifier_call = myri10ge_notify_dca,
3973 .next = NULL,
3974 .priority = 0,
3975};
3976#endif /* CONFIG_DCA */
3977
3393static __init int myri10ge_init_module(void) 3978static __init int myri10ge_init_module(void)
3394{ 3979{
3395 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name, 3980 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3396 MYRI10GE_VERSION_STR); 3981 MYRI10GE_VERSION_STR);
3982
3983 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_SRC_PORT ||
3984 myri10ge_rss_hash < MXGEFW_RSS_HASH_TYPE_IPV4) {
3985 printk(KERN_ERR
3986 "%s: Illegal rssh hash type %d, defaulting to source port\n",
3987 myri10ge_driver.name, myri10ge_rss_hash);
3988 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
3989 }
3990#ifdef CONFIG_DCA
3991 dca_register_notify(&myri10ge_dca_notifier);
3992#endif
3993
3397 return pci_register_driver(&myri10ge_driver); 3994 return pci_register_driver(&myri10ge_driver);
3398} 3995}
3399 3996
@@ -3401,6 +3998,9 @@ module_init(myri10ge_init_module);
3401 3998
3402static __exit void myri10ge_cleanup_module(void) 3999static __exit void myri10ge_cleanup_module(void)
3403{ 4000{
4001#ifdef CONFIG_DCA
4002 dca_unregister_notify(&myri10ge_dca_notifier);
4003#endif
3404 pci_unregister_driver(&myri10ge_driver); 4004 pci_unregister_driver(&myri10ge_driver);
3405} 4005}
3406 4006
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index 46119bb3770a..b238ed0e8ace 100644
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -664,7 +664,7 @@ static ssize_t natsemi_show_##_name(struct device *dev, \
664NATSEMI_ATTR(dspcfg_workaround); 664NATSEMI_ATTR(dspcfg_workaround);
665 665
666static ssize_t natsemi_show_dspcfg_workaround(struct device *dev, 666static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
667 struct device_attribute *attr, 667 struct device_attribute *attr,
668 char *buf) 668 char *buf)
669{ 669{
670 struct netdev_private *np = netdev_priv(to_net_dev(dev)); 670 struct netdev_private *np = netdev_priv(to_net_dev(dev));
@@ -687,7 +687,7 @@ static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
687 || !strncmp("0", buf, count - 1)) 687 || !strncmp("0", buf, count - 1))
688 new_setting = 0; 688 new_setting = 0;
689 else 689 else
690 return count; 690 return count;
691 691
692 spin_lock_irqsave(&np->lock, flags); 692 spin_lock_irqsave(&np->lock, flags);
693 693
diff --git a/drivers/net/ne.c b/drivers/net/ne.c
index 874d291cbaed..14126973bd12 100644
--- a/drivers/net/ne.c
+++ b/drivers/net/ne.c
@@ -217,7 +217,7 @@ static int __init do_ne_probe(struct net_device *dev)
217#ifndef MODULE 217#ifndef MODULE
218struct net_device * __init ne_probe(int unit) 218struct net_device * __init ne_probe(int unit)
219{ 219{
220 struct net_device *dev = alloc_ei_netdev(); 220 struct net_device *dev = alloc_eip_netdev();
221 int err; 221 int err;
222 222
223 if (!dev) 223 if (!dev)
@@ -490,7 +490,7 @@ static int __init ne_probe1(struct net_device *dev, unsigned long ioaddr)
490 490
491 /* Snarf the interrupt now. There's no point in waiting since we cannot 491 /* Snarf the interrupt now. There's no point in waiting since we cannot
492 share and the board will usually be enabled. */ 492 share and the board will usually be enabled. */
493 ret = request_irq(dev->irq, ei_interrupt, 0, name, dev); 493 ret = request_irq(dev->irq, eip_interrupt, 0, name, dev);
494 if (ret) { 494 if (ret) {
495 printk (" unable to get IRQ %d (errno=%d).\n", dev->irq, ret); 495 printk (" unable to get IRQ %d (errno=%d).\n", dev->irq, ret);
496 goto err_out; 496 goto err_out;
@@ -534,7 +534,7 @@ static int __init ne_probe1(struct net_device *dev, unsigned long ioaddr)
534 dev->open = &ne_open; 534 dev->open = &ne_open;
535 dev->stop = &ne_close; 535 dev->stop = &ne_close;
536#ifdef CONFIG_NET_POLL_CONTROLLER 536#ifdef CONFIG_NET_POLL_CONTROLLER
537 dev->poll_controller = ei_poll; 537 dev->poll_controller = eip_poll;
538#endif 538#endif
539 NS8390_init(dev, 0); 539 NS8390_init(dev, 0);
540 540
@@ -554,7 +554,7 @@ err_out:
554 554
555static int ne_open(struct net_device *dev) 555static int ne_open(struct net_device *dev)
556{ 556{
557 ei_open(dev); 557 eip_open(dev);
558 return 0; 558 return 0;
559} 559}
560 560
@@ -562,7 +562,7 @@ static int ne_close(struct net_device *dev)
562{ 562{
563 if (ei_debug > 1) 563 if (ei_debug > 1)
564 printk(KERN_DEBUG "%s: Shutting down ethercard.\n", dev->name); 564 printk(KERN_DEBUG "%s: Shutting down ethercard.\n", dev->name);
565 ei_close(dev); 565 eip_close(dev);
566 return 0; 566 return 0;
567} 567}
568 568
@@ -814,7 +814,7 @@ static int __init ne_drv_probe(struct platform_device *pdev)
814 if (!res || irq < 0) 814 if (!res || irq < 0)
815 return -ENODEV; 815 return -ENODEV;
816 816
817 dev = alloc_ei_netdev(); 817 dev = alloc_eip_netdev();
818 if (!dev) 818 if (!dev)
819 return -ENOMEM; 819 return -ENOMEM;
820 dev->irq = irq; 820 dev->irq = irq;
@@ -912,7 +912,7 @@ int __init init_module(void)
912 int plat_found = !ne_init(); 912 int plat_found = !ne_init();
913 913
914 for (this_dev = 0; this_dev < MAX_NE_CARDS; this_dev++) { 914 for (this_dev = 0; this_dev < MAX_NE_CARDS; this_dev++) {
915 struct net_device *dev = alloc_ei_netdev(); 915 struct net_device *dev = alloc_eip_netdev();
916 if (!dev) 916 if (!dev)
917 break; 917 break;
918 dev->irq = irq[this_dev]; 918 dev->irq = irq[this_dev];
diff --git a/drivers/net/ne2.c b/drivers/net/ne2.c
index f4cd8c7e81ba..8f7256346922 100644
--- a/drivers/net/ne2.c
+++ b/drivers/net/ne2.c
@@ -280,7 +280,7 @@ static int __init do_ne2_probe(struct net_device *dev)
280#ifndef MODULE 280#ifndef MODULE
281struct net_device * __init ne2_probe(int unit) 281struct net_device * __init ne2_probe(int unit)
282{ 282{
283 struct net_device *dev = alloc_ei_netdev(); 283 struct net_device *dev = alloc_eip_netdev();
284 int err; 284 int err;
285 285
286 if (!dev) 286 if (!dev)
@@ -457,7 +457,7 @@ static int __init ne2_probe1(struct net_device *dev, int slot)
457 457
458 /* Snarf the interrupt now. There's no point in waiting since we cannot 458 /* Snarf the interrupt now. There's no point in waiting since we cannot
459 share and the board will usually be enabled. */ 459 share and the board will usually be enabled. */
460 retval = request_irq(dev->irq, ei_interrupt, 0, DRV_NAME, dev); 460 retval = request_irq(dev->irq, eip_interrupt, 0, DRV_NAME, dev);
461 if (retval) { 461 if (retval) {
462 printk (" unable to get IRQ %d (irqval=%d).\n", 462 printk (" unable to get IRQ %d (irqval=%d).\n",
463 dev->irq, retval); 463 dev->irq, retval);
@@ -497,9 +497,9 @@ static int __init ne2_probe1(struct net_device *dev, int slot)
497 dev->open = &ne_open; 497 dev->open = &ne_open;
498 dev->stop = &ne_close; 498 dev->stop = &ne_close;
499#ifdef CONFIG_NET_POLL_CONTROLLER 499#ifdef CONFIG_NET_POLL_CONTROLLER
500 dev->poll_controller = ei_poll; 500 dev->poll_controller = eip_poll;
501#endif 501#endif
502 NS8390_init(dev, 0); 502 NS8390p_init(dev, 0);
503 503
504 retval = register_netdev(dev); 504 retval = register_netdev(dev);
505 if (retval) 505 if (retval)
@@ -515,7 +515,7 @@ out:
515 515
516static int ne_open(struct net_device *dev) 516static int ne_open(struct net_device *dev)
517{ 517{
518 ei_open(dev); 518 eip_open(dev);
519 return 0; 519 return 0;
520} 520}
521 521
@@ -523,7 +523,7 @@ static int ne_close(struct net_device *dev)
523{ 523{
524 if (ei_debug > 1) 524 if (ei_debug > 1)
525 printk("%s: Shutting down ethercard.\n", dev->name); 525 printk("%s: Shutting down ethercard.\n", dev->name);
526 ei_close(dev); 526 eip_close(dev);
527 return 0; 527 return 0;
528} 528}
529 529
@@ -748,7 +748,7 @@ retry:
748 if (time_after(jiffies, dma_start + 2*HZ/100)) { /* 20ms */ 748 if (time_after(jiffies, dma_start + 2*HZ/100)) { /* 20ms */
749 printk("%s: timeout waiting for Tx RDC.\n", dev->name); 749 printk("%s: timeout waiting for Tx RDC.\n", dev->name);
750 ne_reset_8390(dev); 750 ne_reset_8390(dev);
751 NS8390_init(dev,1); 751 NS8390p_init(dev, 1);
752 break; 752 break;
753 } 753 }
754 754
@@ -781,7 +781,7 @@ int __init init_module(void)
781 int this_dev, found = 0; 781 int this_dev, found = 0;
782 782
783 for (this_dev = 0; this_dev < MAX_NE_CARDS; this_dev++) { 783 for (this_dev = 0; this_dev < MAX_NE_CARDS; this_dev++) {
784 dev = alloc_ei_netdev(); 784 dev = alloc_eip_netdev();
785 if (!dev) 785 if (!dev)
786 break; 786 break;
787 dev->irq = irq[this_dev]; 787 dev->irq = irq[this_dev];
diff --git a/drivers/net/niu.c b/drivers/net/niu.c
index 918f802fe089..8ee7d7bb951b 100644
--- a/drivers/net/niu.c
+++ b/drivers/net/niu.c
@@ -3236,10 +3236,14 @@ static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3236 3236
3237static void niu_tx_work(struct niu *np, struct tx_ring_info *rp) 3237static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3238{ 3238{
3239 struct netdev_queue *txq;
3239 u16 pkt_cnt, tmp; 3240 u16 pkt_cnt, tmp;
3240 int cons; 3241 int cons, index;
3241 u64 cs; 3242 u64 cs;
3242 3243
3244 index = (rp - np->tx_rings);
3245 txq = netdev_get_tx_queue(np->dev, index);
3246
3243 cs = rp->tx_cs; 3247 cs = rp->tx_cs;
3244 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK)))) 3248 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3245 goto out; 3249 goto out;
@@ -3262,13 +3266,13 @@ static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3262 smp_mb(); 3266 smp_mb();
3263 3267
3264out: 3268out:
3265 if (unlikely(netif_queue_stopped(np->dev) && 3269 if (unlikely(netif_tx_queue_stopped(txq) &&
3266 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) { 3270 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3267 netif_tx_lock(np->dev); 3271 __netif_tx_lock(txq, smp_processor_id());
3268 if (netif_queue_stopped(np->dev) && 3272 if (netif_tx_queue_stopped(txq) &&
3269 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))) 3273 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3270 netif_wake_queue(np->dev); 3274 netif_tx_wake_queue(txq);
3271 netif_tx_unlock(np->dev); 3275 __netif_tx_unlock(txq);
3272 } 3276 }
3273} 3277}
3274 3278
@@ -4061,6 +4065,8 @@ static int niu_alloc_channels(struct niu *np)
4061 np->num_rx_rings = parent->rxchan_per_port[port]; 4065 np->num_rx_rings = parent->rxchan_per_port[port];
4062 np->num_tx_rings = parent->txchan_per_port[port]; 4066 np->num_tx_rings = parent->txchan_per_port[port];
4063 4067
4068 np->dev->real_num_tx_queues = np->num_tx_rings;
4069
4064 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info), 4070 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4065 GFP_KERNEL); 4071 GFP_KERNEL);
4066 err = -ENOMEM; 4072 err = -ENOMEM;
@@ -5686,7 +5692,7 @@ static int niu_open(struct net_device *dev)
5686 goto out_free_irq; 5692 goto out_free_irq;
5687 } 5693 }
5688 5694
5689 netif_start_queue(dev); 5695 netif_tx_start_all_queues(dev);
5690 5696
5691 if (np->link_config.loopback_mode != LOOPBACK_DISABLED) 5697 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
5692 netif_carrier_on(dev); 5698 netif_carrier_on(dev);
@@ -5710,7 +5716,7 @@ static void niu_full_shutdown(struct niu *np, struct net_device *dev)
5710 cancel_work_sync(&np->reset_task); 5716 cancel_work_sync(&np->reset_task);
5711 5717
5712 niu_disable_napi(np); 5718 niu_disable_napi(np);
5713 netif_stop_queue(dev); 5719 netif_tx_stop_all_queues(dev);
5714 5720
5715 del_timer_sync(&np->timer); 5721 del_timer_sync(&np->timer);
5716 5722
@@ -5971,7 +5977,7 @@ static void niu_netif_start(struct niu *np)
5971 * so long as all callers are assured to have free tx slots 5977 * so long as all callers are assured to have free tx slots
5972 * (such as after niu_init_hw). 5978 * (such as after niu_init_hw).
5973 */ 5979 */
5974 netif_wake_queue(np->dev); 5980 netif_tx_wake_all_queues(np->dev);
5975 5981
5976 niu_enable_napi(np); 5982 niu_enable_napi(np);
5977 5983
@@ -6097,15 +6103,11 @@ static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6097 return ret; 6103 return ret;
6098} 6104}
6099 6105
6100static struct tx_ring_info *tx_ring_select(struct niu *np, struct sk_buff *skb)
6101{
6102 return &np->tx_rings[0];
6103}
6104
6105static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev) 6106static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6106{ 6107{
6107 struct niu *np = netdev_priv(dev); 6108 struct niu *np = netdev_priv(dev);
6108 unsigned long align, headroom; 6109 unsigned long align, headroom;
6110 struct netdev_queue *txq;
6109 struct tx_ring_info *rp; 6111 struct tx_ring_info *rp;
6110 struct tx_pkt_hdr *tp; 6112 struct tx_pkt_hdr *tp;
6111 unsigned int len, nfg; 6113 unsigned int len, nfg;
@@ -6113,10 +6115,12 @@ static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6113 int prod, i, tlen; 6115 int prod, i, tlen;
6114 u64 mapping, mrk; 6116 u64 mapping, mrk;
6115 6117
6116 rp = tx_ring_select(np, skb); 6118 i = skb_get_queue_mapping(skb);
6119 rp = &np->tx_rings[i];
6120 txq = netdev_get_tx_queue(dev, i);
6117 6121
6118 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) { 6122 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6119 netif_stop_queue(dev); 6123 netif_tx_stop_queue(txq);
6120 dev_err(np->device, PFX "%s: BUG! Tx ring full when " 6124 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6121 "queue awake!\n", dev->name); 6125 "queue awake!\n", dev->name);
6122 rp->tx_errors++; 6126 rp->tx_errors++;
@@ -6215,9 +6219,9 @@ static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6215 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3)); 6219 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6216 6220
6217 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) { 6221 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6218 netif_stop_queue(dev); 6222 netif_tx_stop_queue(txq);
6219 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)) 6223 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6220 netif_wake_queue(dev); 6224 netif_tx_wake_queue(txq);
6221 } 6225 }
6222 6226
6223 dev->trans_start = jiffies; 6227 dev->trans_start = jiffies;
@@ -6275,7 +6279,7 @@ static int niu_change_mtu(struct net_device *dev, int new_mtu)
6275 spin_unlock_irq(&np->lock); 6279 spin_unlock_irq(&np->lock);
6276 6280
6277 if (!err) { 6281 if (!err) {
6278 netif_start_queue(dev); 6282 netif_tx_start_all_queues(dev);
6279 if (np->link_config.loopback_mode != LOOPBACK_DISABLED) 6283 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6280 netif_carrier_on(dev); 6284 netif_carrier_on(dev);
6281 6285
@@ -6385,6 +6389,162 @@ static int niu_get_eeprom(struct net_device *dev,
6385 return 0; 6389 return 0;
6386} 6390}
6387 6391
6392static int niu_ethflow_to_class(int flow_type, u64 *class)
6393{
6394 switch (flow_type) {
6395 case TCP_V4_FLOW:
6396 *class = CLASS_CODE_TCP_IPV4;
6397 break;
6398 case UDP_V4_FLOW:
6399 *class = CLASS_CODE_UDP_IPV4;
6400 break;
6401 case AH_ESP_V4_FLOW:
6402 *class = CLASS_CODE_AH_ESP_IPV4;
6403 break;
6404 case SCTP_V4_FLOW:
6405 *class = CLASS_CODE_SCTP_IPV4;
6406 break;
6407 case TCP_V6_FLOW:
6408 *class = CLASS_CODE_TCP_IPV6;
6409 break;
6410 case UDP_V6_FLOW:
6411 *class = CLASS_CODE_UDP_IPV6;
6412 break;
6413 case AH_ESP_V6_FLOW:
6414 *class = CLASS_CODE_AH_ESP_IPV6;
6415 break;
6416 case SCTP_V6_FLOW:
6417 *class = CLASS_CODE_SCTP_IPV6;
6418 break;
6419 default:
6420 return -1;
6421 }
6422
6423 return 1;
6424}
6425
6426static u64 niu_flowkey_to_ethflow(u64 flow_key)
6427{
6428 u64 ethflow = 0;
6429
6430 if (flow_key & FLOW_KEY_PORT)
6431 ethflow |= RXH_DEV_PORT;
6432 if (flow_key & FLOW_KEY_L2DA)
6433 ethflow |= RXH_L2DA;
6434 if (flow_key & FLOW_KEY_VLAN)
6435 ethflow |= RXH_VLAN;
6436 if (flow_key & FLOW_KEY_IPSA)
6437 ethflow |= RXH_IP_SRC;
6438 if (flow_key & FLOW_KEY_IPDA)
6439 ethflow |= RXH_IP_DST;
6440 if (flow_key & FLOW_KEY_PROTO)
6441 ethflow |= RXH_L3_PROTO;
6442 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
6443 ethflow |= RXH_L4_B_0_1;
6444 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
6445 ethflow |= RXH_L4_B_2_3;
6446
6447 return ethflow;
6448
6449}
6450
6451static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
6452{
6453 u64 key = 0;
6454
6455 if (ethflow & RXH_DEV_PORT)
6456 key |= FLOW_KEY_PORT;
6457 if (ethflow & RXH_L2DA)
6458 key |= FLOW_KEY_L2DA;
6459 if (ethflow & RXH_VLAN)
6460 key |= FLOW_KEY_VLAN;
6461 if (ethflow & RXH_IP_SRC)
6462 key |= FLOW_KEY_IPSA;
6463 if (ethflow & RXH_IP_DST)
6464 key |= FLOW_KEY_IPDA;
6465 if (ethflow & RXH_L3_PROTO)
6466 key |= FLOW_KEY_PROTO;
6467 if (ethflow & RXH_L4_B_0_1)
6468 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
6469 if (ethflow & RXH_L4_B_2_3)
6470 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
6471
6472 *flow_key = key;
6473
6474 return 1;
6475
6476}
6477
6478static int niu_get_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6479{
6480 struct niu *np = netdev_priv(dev);
6481 u64 class;
6482
6483 cmd->data = 0;
6484
6485 if (!niu_ethflow_to_class(cmd->flow_type, &class))
6486 return -EINVAL;
6487
6488 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6489 TCAM_KEY_DISC)
6490 cmd->data = RXH_DISCARD;
6491 else
6492
6493 cmd->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
6494 CLASS_CODE_USER_PROG1]);
6495 return 0;
6496}
6497
6498static int niu_set_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6499{
6500 struct niu *np = netdev_priv(dev);
6501 u64 class;
6502 u64 flow_key = 0;
6503 unsigned long flags;
6504
6505 if (!niu_ethflow_to_class(cmd->flow_type, &class))
6506 return -EINVAL;
6507
6508 if (class < CLASS_CODE_USER_PROG1 ||
6509 class > CLASS_CODE_SCTP_IPV6)
6510 return -EINVAL;
6511
6512 if (cmd->data & RXH_DISCARD) {
6513 niu_lock_parent(np, flags);
6514 flow_key = np->parent->tcam_key[class -
6515 CLASS_CODE_USER_PROG1];
6516 flow_key |= TCAM_KEY_DISC;
6517 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6518 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6519 niu_unlock_parent(np, flags);
6520 return 0;
6521 } else {
6522 /* Discard was set before, but is not set now */
6523 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6524 TCAM_KEY_DISC) {
6525 niu_lock_parent(np, flags);
6526 flow_key = np->parent->tcam_key[class -
6527 CLASS_CODE_USER_PROG1];
6528 flow_key &= ~TCAM_KEY_DISC;
6529 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
6530 flow_key);
6531 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
6532 flow_key;
6533 niu_unlock_parent(np, flags);
6534 }
6535 }
6536
6537 if (!niu_ethflow_to_flowkey(cmd->data, &flow_key))
6538 return -EINVAL;
6539
6540 niu_lock_parent(np, flags);
6541 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6542 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6543 niu_unlock_parent(np, flags);
6544
6545 return 0;
6546}
6547
6388static const struct { 6548static const struct {
6389 const char string[ETH_GSTRING_LEN]; 6549 const char string[ETH_GSTRING_LEN];
6390} niu_xmac_stat_keys[] = { 6550} niu_xmac_stat_keys[] = {
@@ -6615,6 +6775,8 @@ static const struct ethtool_ops niu_ethtool_ops = {
6615 .get_stats_count = niu_get_stats_count, 6775 .get_stats_count = niu_get_stats_count,
6616 .get_ethtool_stats = niu_get_ethtool_stats, 6776 .get_ethtool_stats = niu_get_ethtool_stats,
6617 .phys_id = niu_phys_id, 6777 .phys_id = niu_phys_id,
6778 .get_rxhash = niu_get_hash_opts,
6779 .set_rxhash = niu_set_hash_opts,
6618}; 6780};
6619 6781
6620static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent, 6782static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
@@ -8374,9 +8536,10 @@ static struct net_device * __devinit niu_alloc_and_init(
8374 struct of_device *op, const struct niu_ops *ops, 8536 struct of_device *op, const struct niu_ops *ops,
8375 u8 port) 8537 u8 port)
8376{ 8538{
8377 struct net_device *dev = alloc_etherdev(sizeof(struct niu)); 8539 struct net_device *dev;
8378 struct niu *np; 8540 struct niu *np;
8379 8541
8542 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
8380 if (!dev) { 8543 if (!dev) {
8381 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n"); 8544 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
8382 return NULL; 8545 return NULL;
diff --git a/drivers/net/niu.h b/drivers/net/niu.h
index 12fd570b9423..c6fa883daa22 100644
--- a/drivers/net/niu.h
+++ b/drivers/net/niu.h
@@ -281,7 +281,7 @@
281#define XMAC_ADDR1 0x000a8UL 281#define XMAC_ADDR1 0x000a8UL
282#define XMAC_ADDR1_ADDR1 0x000000000000ffffULL 282#define XMAC_ADDR1_ADDR1 0x000000000000ffffULL
283 283
284#define XMAC_ADDR2 0x000b0UL 284#define XMAC_ADDR2 0x000b0UL
285#define XMAC_ADDR2_ADDR2 0x000000000000ffffULL 285#define XMAC_ADDR2_ADDR2 0x000000000000ffffULL
286 286
287#define XMAC_ADDR_CMPEN 0x00208UL 287#define XMAC_ADDR_CMPEN 0x00208UL
diff --git a/drivers/net/ns83820.c b/drivers/net/ns83820.c
index b42c05f84be1..ff449619f047 100644
--- a/drivers/net/ns83820.c
+++ b/drivers/net/ns83820.c
@@ -585,16 +585,13 @@ static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
585 for (i=0; i<NR_RX_DESC; i++) { 585 for (i=0; i<NR_RX_DESC; i++) {
586 struct sk_buff *skb; 586 struct sk_buff *skb;
587 long res; 587 long res;
588
588 /* extra 16 bytes for alignment */ 589 /* extra 16 bytes for alignment */
589 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp); 590 skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp);
590 if (unlikely(!skb)) 591 if (unlikely(!skb))
591 break; 592 break;
592 593
593 res = (long)skb->data & 0xf; 594 skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16));
594 res = 0x10 - res;
595 res &= 0xf;
596 skb_reserve(skb, res);
597
598 if (gfp != GFP_ATOMIC) 595 if (gfp != GFP_ATOMIC)
599 spin_lock_irqsave(&dev->rx_info.lock, flags); 596 spin_lock_irqsave(&dev->rx_info.lock, flags);
600 res = ns83820_add_rx_skb(dev, skb); 597 res = ns83820_add_rx_skb(dev, skb);
diff --git a/drivers/net/pci-skeleton.c b/drivers/net/pci-skeleton.c
index fffc49befe04..53451c3b2c0d 100644
--- a/drivers/net/pci-skeleton.c
+++ b/drivers/net/pci-skeleton.c
@@ -1739,7 +1739,6 @@ static int netdrv_close (struct net_device *dev)
1739 1739
1740 spin_unlock_irqrestore (&tp->lock, flags); 1740 spin_unlock_irqrestore (&tp->lock, flags);
1741 1741
1742 synchronize_irq (dev->irq);
1743 free_irq (dev->irq, dev); 1742 free_irq (dev->irq, dev);
1744 1743
1745 netdrv_tx_clear (dev); 1744 netdrv_tx_clear (dev);
diff --git a/drivers/net/pcmcia/3c574_cs.c b/drivers/net/pcmcia/3c574_cs.c
index 3b78a3819bb3..7112fd5e0e1b 100644
--- a/drivers/net/pcmcia/3c574_cs.c
+++ b/drivers/net/pcmcia/3c574_cs.c
@@ -208,7 +208,6 @@ enum Window4 { /* Window 4: Xcvr/media bits. */
208struct el3_private { 208struct el3_private {
209 struct pcmcia_device *p_dev; 209 struct pcmcia_device *p_dev;
210 dev_node_t node; 210 dev_node_t node;
211 struct net_device_stats stats;
212 u16 advertising, partner; /* NWay media advertisement */ 211 u16 advertising, partner; /* NWay media advertisement */
213 unsigned char phys; /* MII device address */ 212 unsigned char phys; /* MII device address */
214 unsigned int autoselect:1, default_media:3; /* Read from the EEPROM/Wn3_Config. */ 213 unsigned int autoselect:1, default_media:3; /* Read from the EEPROM/Wn3_Config. */
@@ -741,12 +740,11 @@ static int el3_open(struct net_device *dev)
741 740
742static void el3_tx_timeout(struct net_device *dev) 741static void el3_tx_timeout(struct net_device *dev)
743{ 742{
744 struct el3_private *lp = netdev_priv(dev);
745 unsigned int ioaddr = dev->base_addr; 743 unsigned int ioaddr = dev->base_addr;
746 744
747 printk(KERN_NOTICE "%s: Transmit timed out!\n", dev->name); 745 printk(KERN_NOTICE "%s: Transmit timed out!\n", dev->name);
748 dump_status(dev); 746 dump_status(dev);
749 lp->stats.tx_errors++; 747 dev->stats.tx_errors++;
750 dev->trans_start = jiffies; 748 dev->trans_start = jiffies;
751 /* Issue TX_RESET and TX_START commands. */ 749 /* Issue TX_RESET and TX_START commands. */
752 tc574_wait_for_completion(dev, TxReset); 750 tc574_wait_for_completion(dev, TxReset);
@@ -756,7 +754,6 @@ static void el3_tx_timeout(struct net_device *dev)
756 754
757static void pop_tx_status(struct net_device *dev) 755static void pop_tx_status(struct net_device *dev)
758{ 756{
759 struct el3_private *lp = netdev_priv(dev);
760 unsigned int ioaddr = dev->base_addr; 757 unsigned int ioaddr = dev->base_addr;
761 int i; 758 int i;
762 759
@@ -772,7 +769,7 @@ static void pop_tx_status(struct net_device *dev)
772 DEBUG(1, "%s: transmit error: status 0x%02x\n", 769 DEBUG(1, "%s: transmit error: status 0x%02x\n",
773 dev->name, tx_status); 770 dev->name, tx_status);
774 outw(TxEnable, ioaddr + EL3_CMD); 771 outw(TxEnable, ioaddr + EL3_CMD);
775 lp->stats.tx_aborted_errors++; 772 dev->stats.tx_aborted_errors++;
776 } 773 }
777 outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */ 774 outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */
778 } 775 }
@@ -987,7 +984,7 @@ static struct net_device_stats *el3_get_stats(struct net_device *dev)
987 update_stats(dev); 984 update_stats(dev);
988 spin_unlock_irqrestore(&lp->window_lock, flags); 985 spin_unlock_irqrestore(&lp->window_lock, flags);
989 } 986 }
990 return &lp->stats; 987 return &dev->stats;
991} 988}
992 989
993/* Update statistics. 990/* Update statistics.
@@ -996,7 +993,6 @@ static struct net_device_stats *el3_get_stats(struct net_device *dev)
996 */ 993 */
997static void update_stats(struct net_device *dev) 994static void update_stats(struct net_device *dev)
998{ 995{
999 struct el3_private *lp = netdev_priv(dev);
1000 unsigned int ioaddr = dev->base_addr; 996 unsigned int ioaddr = dev->base_addr;
1001 u8 rx, tx, up; 997 u8 rx, tx, up;
1002 998
@@ -1008,15 +1004,15 @@ static void update_stats(struct net_device *dev)
1008 /* Unlike the 3c509 we need not turn off stats updates while reading. */ 1004 /* Unlike the 3c509 we need not turn off stats updates while reading. */
1009 /* Switch to the stats window, and read everything. */ 1005 /* Switch to the stats window, and read everything. */
1010 EL3WINDOW(6); 1006 EL3WINDOW(6);
1011 lp->stats.tx_carrier_errors += inb(ioaddr + 0); 1007 dev->stats.tx_carrier_errors += inb(ioaddr + 0);
1012 lp->stats.tx_heartbeat_errors += inb(ioaddr + 1); 1008 dev->stats.tx_heartbeat_errors += inb(ioaddr + 1);
1013 /* Multiple collisions. */ inb(ioaddr + 2); 1009 /* Multiple collisions. */ inb(ioaddr + 2);
1014 lp->stats.collisions += inb(ioaddr + 3); 1010 dev->stats.collisions += inb(ioaddr + 3);
1015 lp->stats.tx_window_errors += inb(ioaddr + 4); 1011 dev->stats.tx_window_errors += inb(ioaddr + 4);
1016 lp->stats.rx_fifo_errors += inb(ioaddr + 5); 1012 dev->stats.rx_fifo_errors += inb(ioaddr + 5);
1017 lp->stats.tx_packets += inb(ioaddr + 6); 1013 dev->stats.tx_packets += inb(ioaddr + 6);
1018 up = inb(ioaddr + 9); 1014 up = inb(ioaddr + 9);
1019 lp->stats.tx_packets += (up&0x30) << 4; 1015 dev->stats.tx_packets += (up&0x30) << 4;
1020 /* Rx packets */ inb(ioaddr + 7); 1016 /* Rx packets */ inb(ioaddr + 7);
1021 /* Tx deferrals */ inb(ioaddr + 8); 1017 /* Tx deferrals */ inb(ioaddr + 8);
1022 rx = inw(ioaddr + 10); 1018 rx = inw(ioaddr + 10);
@@ -1026,14 +1022,13 @@ static void update_stats(struct net_device *dev)
1026 /* BadSSD */ inb(ioaddr + 12); 1022 /* BadSSD */ inb(ioaddr + 12);
1027 up = inb(ioaddr + 13); 1023 up = inb(ioaddr + 13);
1028 1024
1029 lp->stats.tx_bytes += tx + ((up & 0xf0) << 12); 1025 dev->stats.tx_bytes += tx + ((up & 0xf0) << 12);
1030 1026
1031 EL3WINDOW(1); 1027 EL3WINDOW(1);
1032} 1028}
1033 1029
1034static int el3_rx(struct net_device *dev, int worklimit) 1030static int el3_rx(struct net_device *dev, int worklimit)
1035{ 1031{
1036 struct el3_private *lp = netdev_priv(dev);
1037 unsigned int ioaddr = dev->base_addr; 1032 unsigned int ioaddr = dev->base_addr;
1038 short rx_status; 1033 short rx_status;
1039 1034
@@ -1043,14 +1038,14 @@ static int el3_rx(struct net_device *dev, int worklimit)
1043 (--worklimit >= 0)) { 1038 (--worklimit >= 0)) {
1044 if (rx_status & 0x4000) { /* Error, update stats. */ 1039 if (rx_status & 0x4000) { /* Error, update stats. */
1045 short error = rx_status & 0x3800; 1040 short error = rx_status & 0x3800;
1046 lp->stats.rx_errors++; 1041 dev->stats.rx_errors++;
1047 switch (error) { 1042 switch (error) {
1048 case 0x0000: lp->stats.rx_over_errors++; break; 1043 case 0x0000: dev->stats.rx_over_errors++; break;
1049 case 0x0800: lp->stats.rx_length_errors++; break; 1044 case 0x0800: dev->stats.rx_length_errors++; break;
1050 case 0x1000: lp->stats.rx_frame_errors++; break; 1045 case 0x1000: dev->stats.rx_frame_errors++; break;
1051 case 0x1800: lp->stats.rx_length_errors++; break; 1046 case 0x1800: dev->stats.rx_length_errors++; break;
1052 case 0x2000: lp->stats.rx_frame_errors++; break; 1047 case 0x2000: dev->stats.rx_frame_errors++; break;
1053 case 0x2800: lp->stats.rx_crc_errors++; break; 1048 case 0x2800: dev->stats.rx_crc_errors++; break;
1054 } 1049 }
1055 } else { 1050 } else {
1056 short pkt_len = rx_status & 0x7ff; 1051 short pkt_len = rx_status & 0x7ff;
@@ -1067,12 +1062,12 @@ static int el3_rx(struct net_device *dev, int worklimit)
1067 skb->protocol = eth_type_trans(skb, dev); 1062 skb->protocol = eth_type_trans(skb, dev);
1068 netif_rx(skb); 1063 netif_rx(skb);
1069 dev->last_rx = jiffies; 1064 dev->last_rx = jiffies;
1070 lp->stats.rx_packets++; 1065 dev->stats.rx_packets++;
1071 lp->stats.rx_bytes += pkt_len; 1066 dev->stats.rx_bytes += pkt_len;
1072 } else { 1067 } else {
1073 DEBUG(1, "%s: couldn't allocate a sk_buff of" 1068 DEBUG(1, "%s: couldn't allocate a sk_buff of"
1074 " size %d.\n", dev->name, pkt_len); 1069 " size %d.\n", dev->name, pkt_len);
1075 lp->stats.rx_dropped++; 1070 dev->stats.rx_dropped++;
1076 } 1071 }
1077 } 1072 }
1078 tc574_wait_for_completion(dev, RxDiscard); 1073 tc574_wait_for_completion(dev, RxDiscard);
diff --git a/drivers/net/pcmcia/3c589_cs.c b/drivers/net/pcmcia/3c589_cs.c
index 1b1abb19c911..549a64558420 100644
--- a/drivers/net/pcmcia/3c589_cs.c
+++ b/drivers/net/pcmcia/3c589_cs.c
@@ -107,7 +107,6 @@ enum RxFilter {
107struct el3_private { 107struct el3_private {
108 struct pcmcia_device *p_dev; 108 struct pcmcia_device *p_dev;
109 dev_node_t node; 109 dev_node_t node;
110 struct net_device_stats stats;
111 /* For transceiver monitoring */ 110 /* For transceiver monitoring */
112 struct timer_list media; 111 struct timer_list media;
113 u16 media_status; 112 u16 media_status;
@@ -566,12 +565,11 @@ static int el3_open(struct net_device *dev)
566 565
567static void el3_tx_timeout(struct net_device *dev) 566static void el3_tx_timeout(struct net_device *dev)
568{ 567{
569 struct el3_private *lp = netdev_priv(dev);
570 unsigned int ioaddr = dev->base_addr; 568 unsigned int ioaddr = dev->base_addr;
571 569
572 printk(KERN_WARNING "%s: Transmit timed out!\n", dev->name); 570 printk(KERN_WARNING "%s: Transmit timed out!\n", dev->name);
573 dump_status(dev); 571 dump_status(dev);
574 lp->stats.tx_errors++; 572 dev->stats.tx_errors++;
575 dev->trans_start = jiffies; 573 dev->trans_start = jiffies;
576 /* Issue TX_RESET and TX_START commands. */ 574 /* Issue TX_RESET and TX_START commands. */
577 tc589_wait_for_completion(dev, TxReset); 575 tc589_wait_for_completion(dev, TxReset);
@@ -581,7 +579,6 @@ static void el3_tx_timeout(struct net_device *dev)
581 579
582static void pop_tx_status(struct net_device *dev) 580static void pop_tx_status(struct net_device *dev)
583{ 581{
584 struct el3_private *lp = netdev_priv(dev);
585 unsigned int ioaddr = dev->base_addr; 582 unsigned int ioaddr = dev->base_addr;
586 int i; 583 int i;
587 584
@@ -596,7 +593,7 @@ static void pop_tx_status(struct net_device *dev)
596 DEBUG(1, "%s: transmit error: status 0x%02x\n", 593 DEBUG(1, "%s: transmit error: status 0x%02x\n",
597 dev->name, tx_status); 594 dev->name, tx_status);
598 outw(TxEnable, ioaddr + EL3_CMD); 595 outw(TxEnable, ioaddr + EL3_CMD);
599 lp->stats.tx_aborted_errors++; 596 dev->stats.tx_aborted_errors++;
600 } 597 }
601 outb(0x00, ioaddr + TX_STATUS); /* Pop the status stack. */ 598 outb(0x00, ioaddr + TX_STATUS); /* Pop the status stack. */
602 } 599 }
@@ -614,7 +611,7 @@ static int el3_start_xmit(struct sk_buff *skb, struct net_device *dev)
614 611
615 spin_lock_irqsave(&priv->lock, flags); 612 spin_lock_irqsave(&priv->lock, flags);
616 613
617 priv->stats.tx_bytes += skb->len; 614 dev->stats.tx_bytes += skb->len;
618 615
619 /* Put out the doubleword header... */ 616 /* Put out the doubleword header... */
620 outw(skb->len, ioaddr + TX_FIFO); 617 outw(skb->len, ioaddr + TX_FIFO);
@@ -764,7 +761,7 @@ static void media_check(unsigned long arg)
764 outw(StatsDisable, ioaddr + EL3_CMD); 761 outw(StatsDisable, ioaddr + EL3_CMD);
765 errs = inb(ioaddr + 0); 762 errs = inb(ioaddr + 0);
766 outw(StatsEnable, ioaddr + EL3_CMD); 763 outw(StatsEnable, ioaddr + EL3_CMD);
767 lp->stats.tx_carrier_errors += errs; 764 dev->stats.tx_carrier_errors += errs;
768 if (errs || (lp->media_status & 0x0010)) media |= 0x0010; 765 if (errs || (lp->media_status & 0x0010)) media |= 0x0010;
769 } 766 }
770 767
@@ -814,7 +811,7 @@ static struct net_device_stats *el3_get_stats(struct net_device *dev)
814 update_stats(dev); 811 update_stats(dev);
815 spin_unlock_irqrestore(&lp->lock, flags); 812 spin_unlock_irqrestore(&lp->lock, flags);
816 } 813 }
817 return &lp->stats; 814 return &dev->stats;
818} 815}
819 816
820/* 817/*
@@ -827,7 +824,6 @@ static struct net_device_stats *el3_get_stats(struct net_device *dev)
827*/ 824*/
828static void update_stats(struct net_device *dev) 825static void update_stats(struct net_device *dev)
829{ 826{
830 struct el3_private *lp = netdev_priv(dev);
831 unsigned int ioaddr = dev->base_addr; 827 unsigned int ioaddr = dev->base_addr;
832 828
833 DEBUG(2, "%s: updating the statistics.\n", dev->name); 829 DEBUG(2, "%s: updating the statistics.\n", dev->name);
@@ -835,13 +831,13 @@ static void update_stats(struct net_device *dev)
835 outw(StatsDisable, ioaddr + EL3_CMD); 831 outw(StatsDisable, ioaddr + EL3_CMD);
836 /* Switch to the stats window, and read everything. */ 832 /* Switch to the stats window, and read everything. */
837 EL3WINDOW(6); 833 EL3WINDOW(6);
838 lp->stats.tx_carrier_errors += inb(ioaddr + 0); 834 dev->stats.tx_carrier_errors += inb(ioaddr + 0);
839 lp->stats.tx_heartbeat_errors += inb(ioaddr + 1); 835 dev->stats.tx_heartbeat_errors += inb(ioaddr + 1);
840 /* Multiple collisions. */ inb(ioaddr + 2); 836 /* Multiple collisions. */ inb(ioaddr + 2);
841 lp->stats.collisions += inb(ioaddr + 3); 837 dev->stats.collisions += inb(ioaddr + 3);
842 lp->stats.tx_window_errors += inb(ioaddr + 4); 838 dev->stats.tx_window_errors += inb(ioaddr + 4);
843 lp->stats.rx_fifo_errors += inb(ioaddr + 5); 839 dev->stats.rx_fifo_errors += inb(ioaddr + 5);
844 lp->stats.tx_packets += inb(ioaddr + 6); 840 dev->stats.tx_packets += inb(ioaddr + 6);
845 /* Rx packets */ inb(ioaddr + 7); 841 /* Rx packets */ inb(ioaddr + 7);
846 /* Tx deferrals */ inb(ioaddr + 8); 842 /* Tx deferrals */ inb(ioaddr + 8);
847 /* Rx octets */ inw(ioaddr + 10); 843 /* Rx octets */ inw(ioaddr + 10);
@@ -854,7 +850,6 @@ static void update_stats(struct net_device *dev)
854 850
855static int el3_rx(struct net_device *dev) 851static int el3_rx(struct net_device *dev)
856{ 852{
857 struct el3_private *lp = netdev_priv(dev);
858 unsigned int ioaddr = dev->base_addr; 853 unsigned int ioaddr = dev->base_addr;
859 int worklimit = 32; 854 int worklimit = 32;
860 short rx_status; 855 short rx_status;
@@ -865,14 +860,14 @@ static int el3_rx(struct net_device *dev)
865 (--worklimit >= 0)) { 860 (--worklimit >= 0)) {
866 if (rx_status & 0x4000) { /* Error, update stats. */ 861 if (rx_status & 0x4000) { /* Error, update stats. */
867 short error = rx_status & 0x3800; 862 short error = rx_status & 0x3800;
868 lp->stats.rx_errors++; 863 dev->stats.rx_errors++;
869 switch (error) { 864 switch (error) {
870 case 0x0000: lp->stats.rx_over_errors++; break; 865 case 0x0000: dev->stats.rx_over_errors++; break;
871 case 0x0800: lp->stats.rx_length_errors++; break; 866 case 0x0800: dev->stats.rx_length_errors++; break;
872 case 0x1000: lp->stats.rx_frame_errors++; break; 867 case 0x1000: dev->stats.rx_frame_errors++; break;
873 case 0x1800: lp->stats.rx_length_errors++; break; 868 case 0x1800: dev->stats.rx_length_errors++; break;
874 case 0x2000: lp->stats.rx_frame_errors++; break; 869 case 0x2000: dev->stats.rx_frame_errors++; break;
875 case 0x2800: lp->stats.rx_crc_errors++; break; 870 case 0x2800: dev->stats.rx_crc_errors++; break;
876 } 871 }
877 } else { 872 } else {
878 short pkt_len = rx_status & 0x7ff; 873 short pkt_len = rx_status & 0x7ff;
@@ -889,12 +884,12 @@ static int el3_rx(struct net_device *dev)
889 skb->protocol = eth_type_trans(skb, dev); 884 skb->protocol = eth_type_trans(skb, dev);
890 netif_rx(skb); 885 netif_rx(skb);
891 dev->last_rx = jiffies; 886 dev->last_rx = jiffies;
892 lp->stats.rx_packets++; 887 dev->stats.rx_packets++;
893 lp->stats.rx_bytes += pkt_len; 888 dev->stats.rx_bytes += pkt_len;
894 } else { 889 } else {
895 DEBUG(1, "%s: couldn't allocate a sk_buff of" 890 DEBUG(1, "%s: couldn't allocate a sk_buff of"
896 " size %d.\n", dev->name, pkt_len); 891 " size %d.\n", dev->name, pkt_len);
897 lp->stats.rx_dropped++; 892 dev->stats.rx_dropped++;
898 } 893 }
899 } 894 }
900 /* Pop the top of the Rx FIFO */ 895 /* Pop the top of the Rx FIFO */
@@ -929,7 +924,7 @@ static int el3_close(struct net_device *dev)
929 DEBUG(1, "%s: shutting down ethercard.\n", dev->name); 924 DEBUG(1, "%s: shutting down ethercard.\n", dev->name);
930 925
931 if (pcmcia_dev_present(link)) { 926 if (pcmcia_dev_present(link)) {
932 /* Turn off statistics ASAP. We update lp->stats below. */ 927 /* Turn off statistics ASAP. We update dev->stats below. */
933 outw(StatsDisable, ioaddr + EL3_CMD); 928 outw(StatsDisable, ioaddr + EL3_CMD);
934 929
935 /* Disable the receiver and transmitter. */ 930 /* Disable the receiver and transmitter. */
diff --git a/drivers/net/pcmcia/axnet_cs.c b/drivers/net/pcmcia/axnet_cs.c
index 70d012e90dcf..3f682d49a4e6 100644
--- a/drivers/net/pcmcia/axnet_cs.c
+++ b/drivers/net/pcmcia/axnet_cs.c
@@ -1023,7 +1023,7 @@ static void ei_tx_timeout(struct net_device *dev)
1023 int txsr, isr, tickssofar = jiffies - dev->trans_start; 1023 int txsr, isr, tickssofar = jiffies - dev->trans_start;
1024 unsigned long flags; 1024 unsigned long flags;
1025 1025
1026 ei_local->stat.tx_errors++; 1026 dev->stats.tx_errors++;
1027 1027
1028 spin_lock_irqsave(&ei_local->page_lock, flags); 1028 spin_lock_irqsave(&ei_local->page_lock, flags);
1029 txsr = inb(e8390_base+EN0_TSR); 1029 txsr = inb(e8390_base+EN0_TSR);
@@ -1034,7 +1034,7 @@ static void ei_tx_timeout(struct net_device *dev)
1034 dev->name, (txsr & ENTSR_ABT) ? "excess collisions." : 1034 dev->name, (txsr & ENTSR_ABT) ? "excess collisions." :
1035 (isr) ? "lost interrupt?" : "cable problem?", txsr, isr, tickssofar); 1035 (isr) ? "lost interrupt?" : "cable problem?", txsr, isr, tickssofar);
1036 1036
1037 if (!isr && !ei_local->stat.tx_packets) 1037 if (!isr && !dev->stats.tx_packets)
1038 { 1038 {
1039 /* The 8390 probably hasn't gotten on the cable yet. */ 1039 /* The 8390 probably hasn't gotten on the cable yet. */
1040 ei_local->interface_num ^= 1; /* Try a different xcvr. */ 1040 ei_local->interface_num ^= 1; /* Try a different xcvr. */
@@ -1124,7 +1124,7 @@ static int ei_start_xmit(struct sk_buff *skb, struct net_device *dev)
1124 netif_stop_queue(dev); 1124 netif_stop_queue(dev);
1125 outb_p(ENISR_ALL, e8390_base + EN0_IMR); 1125 outb_p(ENISR_ALL, e8390_base + EN0_IMR);
1126 spin_unlock_irqrestore(&ei_local->page_lock, flags); 1126 spin_unlock_irqrestore(&ei_local->page_lock, flags);
1127 ei_local->stat.tx_errors++; 1127 dev->stats.tx_errors++;
1128 return 1; 1128 return 1;
1129 } 1129 }
1130 1130
@@ -1172,7 +1172,7 @@ static int ei_start_xmit(struct sk_buff *skb, struct net_device *dev)
1172 spin_unlock_irqrestore(&ei_local->page_lock, flags); 1172 spin_unlock_irqrestore(&ei_local->page_lock, flags);
1173 1173
1174 dev_kfree_skb (skb); 1174 dev_kfree_skb (skb);
1175 ei_local->stat.tx_bytes += send_length; 1175 dev->stats.tx_bytes += send_length;
1176 1176
1177 return 0; 1177 return 0;
1178} 1178}
@@ -1264,9 +1264,9 @@ static irqreturn_t ax_interrupt(int irq, void *dev_id)
1264 1264
1265 if (interrupts & ENISR_COUNTERS) 1265 if (interrupts & ENISR_COUNTERS)
1266 { 1266 {
1267 ei_local->stat.rx_frame_errors += inb_p(e8390_base + EN0_COUNTER0); 1267 dev->stats.rx_frame_errors += inb_p(e8390_base + EN0_COUNTER0);
1268 ei_local->stat.rx_crc_errors += inb_p(e8390_base + EN0_COUNTER1); 1268 dev->stats.rx_crc_errors += inb_p(e8390_base + EN0_COUNTER1);
1269 ei_local->stat.rx_missed_errors+= inb_p(e8390_base + EN0_COUNTER2); 1269 dev->stats.rx_missed_errors+= inb_p(e8390_base + EN0_COUNTER2);
1270 } 1270 }
1271 } 1271 }
1272 1272
@@ -1311,7 +1311,6 @@ static irqreturn_t ax_interrupt(int irq, void *dev_id)
1311static void ei_tx_err(struct net_device *dev) 1311static void ei_tx_err(struct net_device *dev)
1312{ 1312{
1313 long e8390_base = dev->base_addr; 1313 long e8390_base = dev->base_addr;
1314 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
1315 unsigned char txsr = inb_p(e8390_base+EN0_TSR); 1314 unsigned char txsr = inb_p(e8390_base+EN0_TSR);
1316 unsigned char tx_was_aborted = txsr & (ENTSR_ABT+ENTSR_FU); 1315 unsigned char tx_was_aborted = txsr & (ENTSR_ABT+ENTSR_FU);
1317 1316
@@ -1334,10 +1333,10 @@ static void ei_tx_err(struct net_device *dev)
1334 ei_tx_intr(dev); 1333 ei_tx_intr(dev);
1335 else 1334 else
1336 { 1335 {
1337 ei_local->stat.tx_errors++; 1336 dev->stats.tx_errors++;
1338 if (txsr & ENTSR_CRS) ei_local->stat.tx_carrier_errors++; 1337 if (txsr & ENTSR_CRS) dev->stats.tx_carrier_errors++;
1339 if (txsr & ENTSR_CDH) ei_local->stat.tx_heartbeat_errors++; 1338 if (txsr & ENTSR_CDH) dev->stats.tx_heartbeat_errors++;
1340 if (txsr & ENTSR_OWC) ei_local->stat.tx_window_errors++; 1339 if (txsr & ENTSR_OWC) dev->stats.tx_window_errors++;
1341 } 1340 }
1342} 1341}
1343 1342
@@ -1399,25 +1398,25 @@ static void ei_tx_intr(struct net_device *dev)
1399 1398
1400 /* Minimize Tx latency: update the statistics after we restart TXing. */ 1399 /* Minimize Tx latency: update the statistics after we restart TXing. */
1401 if (status & ENTSR_COL) 1400 if (status & ENTSR_COL)
1402 ei_local->stat.collisions++; 1401 dev->stats.collisions++;
1403 if (status & ENTSR_PTX) 1402 if (status & ENTSR_PTX)
1404 ei_local->stat.tx_packets++; 1403 dev->stats.tx_packets++;
1405 else 1404 else
1406 { 1405 {
1407 ei_local->stat.tx_errors++; 1406 dev->stats.tx_errors++;
1408 if (status & ENTSR_ABT) 1407 if (status & ENTSR_ABT)
1409 { 1408 {
1410 ei_local->stat.tx_aborted_errors++; 1409 dev->stats.tx_aborted_errors++;
1411 ei_local->stat.collisions += 16; 1410 dev->stats.collisions += 16;
1412 } 1411 }
1413 if (status & ENTSR_CRS) 1412 if (status & ENTSR_CRS)
1414 ei_local->stat.tx_carrier_errors++; 1413 dev->stats.tx_carrier_errors++;
1415 if (status & ENTSR_FU) 1414 if (status & ENTSR_FU)
1416 ei_local->stat.tx_fifo_errors++; 1415 dev->stats.tx_fifo_errors++;
1417 if (status & ENTSR_CDH) 1416 if (status & ENTSR_CDH)
1418 ei_local->stat.tx_heartbeat_errors++; 1417 dev->stats.tx_heartbeat_errors++;
1419 if (status & ENTSR_OWC) 1418 if (status & ENTSR_OWC)
1420 ei_local->stat.tx_window_errors++; 1419 dev->stats.tx_window_errors++;
1421 } 1420 }
1422 netif_wake_queue(dev); 1421 netif_wake_queue(dev);
1423} 1422}
@@ -1478,8 +1477,8 @@ static void ei_receive(struct net_device *dev)
1478 printk(KERN_DEBUG "%s: bogus packet size: %d, status=%#2x nxpg=%#2x.\n", 1477 printk(KERN_DEBUG "%s: bogus packet size: %d, status=%#2x nxpg=%#2x.\n",
1479 dev->name, rx_frame.count, rx_frame.status, 1478 dev->name, rx_frame.count, rx_frame.status,
1480 rx_frame.next); 1479 rx_frame.next);
1481 ei_local->stat.rx_errors++; 1480 dev->stats.rx_errors++;
1482 ei_local->stat.rx_length_errors++; 1481 dev->stats.rx_length_errors++;
1483 } 1482 }
1484 else if ((pkt_stat & 0x0F) == ENRSR_RXOK) 1483 else if ((pkt_stat & 0x0F) == ENRSR_RXOK)
1485 { 1484 {
@@ -1491,7 +1490,7 @@ static void ei_receive(struct net_device *dev)
1491 if (ei_debug > 1) 1490 if (ei_debug > 1)
1492 printk(KERN_DEBUG "%s: Couldn't allocate a sk_buff of size %d.\n", 1491 printk(KERN_DEBUG "%s: Couldn't allocate a sk_buff of size %d.\n",
1493 dev->name, pkt_len); 1492 dev->name, pkt_len);
1494 ei_local->stat.rx_dropped++; 1493 dev->stats.rx_dropped++;
1495 break; 1494 break;
1496 } 1495 }
1497 else 1496 else
@@ -1502,10 +1501,10 @@ static void ei_receive(struct net_device *dev)
1502 skb->protocol=eth_type_trans(skb,dev); 1501 skb->protocol=eth_type_trans(skb,dev);
1503 netif_rx(skb); 1502 netif_rx(skb);
1504 dev->last_rx = jiffies; 1503 dev->last_rx = jiffies;
1505 ei_local->stat.rx_packets++; 1504 dev->stats.rx_packets++;
1506 ei_local->stat.rx_bytes += pkt_len; 1505 dev->stats.rx_bytes += pkt_len;
1507 if (pkt_stat & ENRSR_PHY) 1506 if (pkt_stat & ENRSR_PHY)
1508 ei_local->stat.multicast++; 1507 dev->stats.multicast++;
1509 } 1508 }
1510 } 1509 }
1511 else 1510 else
@@ -1514,10 +1513,10 @@ static void ei_receive(struct net_device *dev)
1514 printk(KERN_DEBUG "%s: bogus packet: status=%#2x nxpg=%#2x size=%d\n", 1513 printk(KERN_DEBUG "%s: bogus packet: status=%#2x nxpg=%#2x size=%d\n",
1515 dev->name, rx_frame.status, rx_frame.next, 1514 dev->name, rx_frame.status, rx_frame.next,
1516 rx_frame.count); 1515 rx_frame.count);
1517 ei_local->stat.rx_errors++; 1516 dev->stats.rx_errors++;
1518 /* NB: The NIC counts CRC, frame and missed errors. */ 1517 /* NB: The NIC counts CRC, frame and missed errors. */
1519 if (pkt_stat & ENRSR_FO) 1518 if (pkt_stat & ENRSR_FO)
1520 ei_local->stat.rx_fifo_errors++; 1519 dev->stats.rx_fifo_errors++;
1521 } 1520 }
1522 next_frame = rx_frame.next; 1521 next_frame = rx_frame.next;
1523 1522
@@ -1552,7 +1551,6 @@ static void ei_rx_overrun(struct net_device *dev)
1552 axnet_dev_t *info = PRIV(dev); 1551 axnet_dev_t *info = PRIV(dev);
1553 long e8390_base = dev->base_addr; 1552 long e8390_base = dev->base_addr;
1554 unsigned char was_txing, must_resend = 0; 1553 unsigned char was_txing, must_resend = 0;
1555 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
1556 1554
1557 /* 1555 /*
1558 * Record whether a Tx was in progress and then issue the 1556 * Record whether a Tx was in progress and then issue the
@@ -1563,7 +1561,7 @@ static void ei_rx_overrun(struct net_device *dev)
1563 1561
1564 if (ei_debug > 1) 1562 if (ei_debug > 1)
1565 printk(KERN_DEBUG "%s: Receiver overrun.\n", dev->name); 1563 printk(KERN_DEBUG "%s: Receiver overrun.\n", dev->name);
1566 ei_local->stat.rx_over_errors++; 1564 dev->stats.rx_over_errors++;
1567 1565
1568 /* 1566 /*
1569 * Wait a full Tx time (1.2ms) + some guard time, NS says 1.6ms total. 1567 * Wait a full Tx time (1.2ms) + some guard time, NS says 1.6ms total.
@@ -1624,16 +1622,16 @@ static struct net_device_stats *get_stats(struct net_device *dev)
1624 1622
1625 /* If the card is stopped, just return the present stats. */ 1623 /* If the card is stopped, just return the present stats. */
1626 if (!netif_running(dev)) 1624 if (!netif_running(dev))
1627 return &ei_local->stat; 1625 return &dev->stats;
1628 1626
1629 spin_lock_irqsave(&ei_local->page_lock,flags); 1627 spin_lock_irqsave(&ei_local->page_lock,flags);
1630 /* Read the counter registers, assuming we are in page 0. */ 1628 /* Read the counter registers, assuming we are in page 0. */
1631 ei_local->stat.rx_frame_errors += inb_p(ioaddr + EN0_COUNTER0); 1629 dev->stats.rx_frame_errors += inb_p(ioaddr + EN0_COUNTER0);
1632 ei_local->stat.rx_crc_errors += inb_p(ioaddr + EN0_COUNTER1); 1630 dev->stats.rx_crc_errors += inb_p(ioaddr + EN0_COUNTER1);
1633 ei_local->stat.rx_missed_errors+= inb_p(ioaddr + EN0_COUNTER2); 1631 dev->stats.rx_missed_errors+= inb_p(ioaddr + EN0_COUNTER2);
1634 spin_unlock_irqrestore(&ei_local->page_lock, flags); 1632 spin_unlock_irqrestore(&ei_local->page_lock, flags);
1635 1633
1636 return &ei_local->stat; 1634 return &dev->stats;
1637} 1635}
1638 1636
1639/* 1637/*
diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c
index 1c89b97f4e09..ca8c0e037400 100644
--- a/drivers/net/pcnet32.c
+++ b/drivers/net/pcnet32.c
@@ -1973,7 +1973,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1973 err_free_ring: 1973 err_free_ring:
1974 pcnet32_free_ring(dev); 1974 pcnet32_free_ring(dev);
1975 err_free_consistent: 1975 err_free_consistent:
1976 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 1976 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1977 lp->init_block, lp->init_dma_addr); 1977 lp->init_block, lp->init_dma_addr);
1978 err_free_netdev: 1978 err_free_netdev:
1979 free_netdev(dev); 1979 free_netdev(dev);
@@ -2953,7 +2953,7 @@ static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2953 unregister_netdev(dev); 2953 unregister_netdev(dev);
2954 pcnet32_free_ring(dev); 2954 pcnet32_free_ring(dev);
2955 release_region(dev->base_addr, PCNET32_TOTAL_SIZE); 2955 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2956 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 2956 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2957 lp->init_block, lp->init_dma_addr); 2957 lp->init_block, lp->init_dma_addr);
2958 free_netdev(dev); 2958 free_netdev(dev);
2959 pci_disable_device(pdev); 2959 pci_disable_device(pdev);
@@ -3036,7 +3036,7 @@ static void __exit pcnet32_cleanup_module(void)
3036 unregister_netdev(pcnet32_dev); 3036 unregister_netdev(pcnet32_dev);
3037 pcnet32_free_ring(pcnet32_dev); 3037 pcnet32_free_ring(pcnet32_dev);
3038 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); 3038 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3039 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 3039 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3040 lp->init_block, lp->init_dma_addr); 3040 lp->init_block, lp->init_dma_addr);
3041 free_netdev(pcnet32_dev); 3041 free_netdev(pcnet32_dev);
3042 pcnet32_dev = next_dev; 3042 pcnet32_dev = next_dev;
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 6eb2d31d1e34..d55932acd887 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -53,7 +53,8 @@ config SMSC_PHY
53config BROADCOM_PHY 53config BROADCOM_PHY
54 tristate "Drivers for Broadcom PHYs" 54 tristate "Drivers for Broadcom PHYs"
55 ---help--- 55 ---help---
56 Currently supports the BCM5411, BCM5421 and BCM5461 PHYs. 56 Currently supports the BCM5411, BCM5421, BCM5461, BCM5464, BCM5481
57 and BCM5482 PHYs.
57 58
58config ICPLUS_PHY 59config ICPLUS_PHY
59 tristate "Drivers for ICPlus PHYs" 60 tristate "Drivers for ICPlus PHYs"
@@ -83,4 +84,10 @@ config MDIO_BITBANG
83 84
84 If in doubt, say N. 85 If in doubt, say N.
85 86
87config MDIO_OF_GPIO
88 tristate "Support for GPIO lib-based bitbanged MDIO buses"
89 depends on MDIO_BITBANG && OF_GPIO
90 ---help---
91 Supports GPIO lib-based MDIO busses.
92
86endif # PHYLIB 93endif # PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 5997d6ef702b..eee329fa6f53 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_ICPLUS_PHY) += icplus.o
15obj-$(CONFIG_REALTEK_PHY) += realtek.o 15obj-$(CONFIG_REALTEK_PHY) += realtek.o
16obj-$(CONFIG_FIXED_PHY) += fixed.o 16obj-$(CONFIG_FIXED_PHY) += fixed.o
17obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o 17obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
18obj-$(CONFIG_MDIO_OF_GPIO) += mdio-ofgpio.o
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 60c5cfe96918..4b4dc98ad165 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -24,6 +24,12 @@
24#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */ 24#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
25#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */ 25#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
26 26
27#define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
28#define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
29#define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
30#define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
31
32#define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
27#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */ 33#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
28#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */ 34#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
29#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */ 35#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
@@ -42,10 +48,120 @@
42#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */ 48#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
43#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */ 49#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
44 50
51#define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
52#define MII_BCM54XX_SHD_WRITE 0x8000
53#define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
54#define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
55
56/*
57 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
58 * BCM5482, and possibly some others.
59 */
60#define BCM_LED_SRC_LINKSPD1 0x0
61#define BCM_LED_SRC_LINKSPD2 0x1
62#define BCM_LED_SRC_XMITLED 0x2
63#define BCM_LED_SRC_ACTIVITYLED 0x3
64#define BCM_LED_SRC_FDXLED 0x4
65#define BCM_LED_SRC_SLAVE 0x5
66#define BCM_LED_SRC_INTR 0x6
67#define BCM_LED_SRC_QUALITY 0x7
68#define BCM_LED_SRC_RCVLED 0x8
69#define BCM_LED_SRC_MULTICOLOR1 0xa
70#define BCM_LED_SRC_OPENSHORT 0xb
71#define BCM_LED_SRC_OFF 0xe /* Tied high */
72#define BCM_LED_SRC_ON 0xf /* Tied low */
73
74/*
75 * BCM5482: Shadow registers
76 * Shadow values go into bits [14:10] of register 0x1c to select a shadow
77 * register to access.
78 */
79#define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
80 /* LED3 / ~LINKSPD[2] selector */
81#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
82 /* LED1 / ~LINKSPD[1] selector */
83#define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
84#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
85#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
86#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
87#define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */
88#define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
89
90/*
91 * BCM5482: Secondary SerDes registers
92 */
93#define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
94#define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
95#define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
96#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
97#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
98
99/*
100 * Device flags for PHYs that can be configured for different operating
101 * modes.
102 */
103#define PHY_BCM_FLAGS_VALID 0x80000000
104#define PHY_BCM_FLAGS_INTF_XAUI 0x00000020
105#define PHY_BCM_FLAGS_INTF_SGMII 0x00000010
106#define PHY_BCM_FLAGS_MODE_1000BX 0x00000002
107#define PHY_BCM_FLAGS_MODE_COPPER 0x00000001
108
45MODULE_DESCRIPTION("Broadcom PHY driver"); 109MODULE_DESCRIPTION("Broadcom PHY driver");
46MODULE_AUTHOR("Maciej W. Rozycki"); 110MODULE_AUTHOR("Maciej W. Rozycki");
47MODULE_LICENSE("GPL"); 111MODULE_LICENSE("GPL");
48 112
113/*
114 * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
115 * 0x1c shadow registers.
116 */
117static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
118{
119 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
120 return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
121}
122
123static int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow, u16 val)
124{
125 return phy_write(phydev, MII_BCM54XX_SHD,
126 MII_BCM54XX_SHD_WRITE |
127 MII_BCM54XX_SHD_VAL(shadow) |
128 MII_BCM54XX_SHD_DATA(val));
129}
130
131/*
132 * Indirect register access functions for the Expansion Registers
133 * and Secondary SerDes registers (when sec_serdes=1).
134 */
135static int bcm54xx_exp_read(struct phy_device *phydev,
136 int sec_serdes, u8 regnum)
137{
138 int val;
139
140 phy_write(phydev, MII_BCM54XX_EXP_SEL,
141 (sec_serdes ? MII_BCM54XX_EXP_SEL_SSD :
142 MII_BCM54XX_EXP_SEL_ER) |
143 regnum);
144 val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
145 phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
146
147 return val;
148}
149
150static int bcm54xx_exp_write(struct phy_device *phydev,
151 int sec_serdes, u8 regnum, u16 val)
152{
153 int ret;
154
155 phy_write(phydev, MII_BCM54XX_EXP_SEL,
156 (sec_serdes ? MII_BCM54XX_EXP_SEL_SSD :
157 MII_BCM54XX_EXP_SEL_ER) |
158 regnum);
159 ret = phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
160 phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
161
162 return ret;
163}
164
49static int bcm54xx_config_init(struct phy_device *phydev) 165static int bcm54xx_config_init(struct phy_device *phydev)
50{ 166{
51 int reg, err; 167 int reg, err;
@@ -70,6 +186,87 @@ static int bcm54xx_config_init(struct phy_device *phydev)
70 return 0; 186 return 0;
71} 187}
72 188
189static int bcm5482_config_init(struct phy_device *phydev)
190{
191 int err, reg;
192
193 err = bcm54xx_config_init(phydev);
194
195 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
196 /*
197 * Enable secondary SerDes and its use as an LED source
198 */
199 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_SSD);
200 bcm54xx_shadow_write(phydev, BCM5482_SHD_SSD,
201 reg |
202 BCM5482_SHD_SSD_LEDM |
203 BCM5482_SHD_SSD_EN);
204
205 /*
206 * Enable SGMII slave mode and auto-detection
207 */
208 reg = bcm54xx_exp_read(phydev, 1, BCM5482_SSD_SGMII_SLAVE);
209 bcm54xx_exp_write(phydev, 1, BCM5482_SSD_SGMII_SLAVE,
210 reg |
211 BCM5482_SSD_SGMII_SLAVE_EN |
212 BCM5482_SSD_SGMII_SLAVE_AD);
213
214 /*
215 * Disable secondary SerDes powerdown
216 */
217 reg = bcm54xx_exp_read(phydev, 1, BCM5482_SSD_1000BX_CTL);
218 bcm54xx_exp_write(phydev, 1, BCM5482_SSD_1000BX_CTL,
219 reg & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
220
221 /*
222 * Select 1000BASE-X register set (primary SerDes)
223 */
224 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_MODE);
225 bcm54xx_shadow_write(phydev, BCM5482_SHD_MODE,
226 reg | BCM5482_SHD_MODE_1000BX);
227
228 /*
229 * LED1=ACTIVITYLED, LED3=LINKSPD[2]
230 * (Use LED1 as secondary SerDes ACTIVITY LED)
231 */
232 bcm54xx_shadow_write(phydev, BCM5482_SHD_LEDS1,
233 BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
234 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
235
236 /*
237 * Auto-negotiation doesn't seem to work quite right
238 * in this mode, so we disable it and force it to the
239 * right speed/duplex setting. Only 'link status'
240 * is important.
241 */
242 phydev->autoneg = AUTONEG_DISABLE;
243 phydev->speed = SPEED_1000;
244 phydev->duplex = DUPLEX_FULL;
245 }
246
247 return err;
248}
249
250static int bcm5482_read_status(struct phy_device *phydev)
251{
252 int err;
253
254 err = genphy_read_status(phydev);
255
256 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
257 /*
258 * Only link status matters for 1000Base-X mode, so force
259 * 1000 Mbit/s full-duplex status
260 */
261 if (phydev->link) {
262 phydev->speed = SPEED_1000;
263 phydev->duplex = DUPLEX_FULL;
264 }
265 }
266
267 return err;
268}
269
73static int bcm54xx_ack_interrupt(struct phy_device *phydev) 270static int bcm54xx_ack_interrupt(struct phy_device *phydev)
74{ 271{
75 int reg; 272 int reg;
@@ -210,9 +407,9 @@ static struct phy_driver bcm5482_driver = {
210 .name = "Broadcom BCM5482", 407 .name = "Broadcom BCM5482",
211 .features = PHY_GBIT_FEATURES, 408 .features = PHY_GBIT_FEATURES,
212 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 409 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
213 .config_init = bcm54xx_config_init, 410 .config_init = bcm5482_config_init,
214 .config_aneg = genphy_config_aneg, 411 .config_aneg = genphy_config_aneg,
215 .read_status = genphy_read_status, 412 .read_status = bcm5482_read_status,
216 .ack_interrupt = bcm54xx_ack_interrupt, 413 .ack_interrupt = bcm54xx_ack_interrupt,
217 .config_intr = bcm54xx_config_intr, 414 .config_intr = bcm54xx_config_intr,
218 .driver = { .owner = THIS_MODULE }, 415 .driver = { .owner = THIS_MODULE },
diff --git a/drivers/net/phy/mdio-bitbang.c b/drivers/net/phy/mdio-bitbang.c
index 2747b1f89ffe..c01b78013ddc 100644
--- a/drivers/net/phy/mdio-bitbang.c
+++ b/drivers/net/phy/mdio-bitbang.c
@@ -177,6 +177,7 @@ struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl)
177 177
178 return bus; 178 return bus;
179} 179}
180EXPORT_SYMBOL(alloc_mdio_bitbang);
180 181
181void free_mdio_bitbang(struct mii_bus *bus) 182void free_mdio_bitbang(struct mii_bus *bus)
182{ 183{
@@ -185,5 +186,6 @@ void free_mdio_bitbang(struct mii_bus *bus)
185 module_put(ctrl->ops->owner); 186 module_put(ctrl->ops->owner);
186 kfree(bus); 187 kfree(bus);
187} 188}
189EXPORT_SYMBOL(free_mdio_bitbang);
188 190
189MODULE_LICENSE("GPL"); 191MODULE_LICENSE("GPL");
diff --git a/drivers/net/phy/mdio-ofgpio.c b/drivers/net/phy/mdio-ofgpio.c
new file mode 100644
index 000000000000..7edfc0c34835
--- /dev/null
+++ b/drivers/net/phy/mdio-ofgpio.c
@@ -0,0 +1,205 @@
1/*
2 * OpenFirmware GPIO based MDIO bitbang driver.
3 *
4 * Copyright (c) 2008 CSE Semaphore Belgium.
5 * by Laurent Pinchart <laurentp@cse-semaphore.com>
6 *
7 * Based on earlier work by
8 *
9 * Copyright (c) 2003 Intracom S.A.
10 * by Pantelis Antoniou <panto@intracom.gr>
11 *
12 * 2005 (c) MontaVista Software, Inc.
13 * Vitaly Bordug <vbordug@ru.mvista.com>
14 *
15 * This file is licensed under the terms of the GNU General Public License
16 * version 2. This program is licensed "as is" without any warranty of any
17 * kind, whether express or implied.
18 */
19
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/mdio-bitbang.h>
25#include <linux/of_gpio.h>
26#include <linux/of_platform.h>
27
28struct mdio_gpio_info {
29 struct mdiobb_ctrl ctrl;
30 int mdc, mdio;
31};
32
33static void mdio_dir(struct mdiobb_ctrl *ctrl, int dir)
34{
35 struct mdio_gpio_info *bitbang =
36 container_of(ctrl, struct mdio_gpio_info, ctrl);
37
38 if (dir)
39 gpio_direction_output(bitbang->mdio, 1);
40 else
41 gpio_direction_input(bitbang->mdio);
42}
43
44static int mdio_read(struct mdiobb_ctrl *ctrl)
45{
46 struct mdio_gpio_info *bitbang =
47 container_of(ctrl, struct mdio_gpio_info, ctrl);
48
49 return gpio_get_value(bitbang->mdio);
50}
51
52static void mdio(struct mdiobb_ctrl *ctrl, int what)
53{
54 struct mdio_gpio_info *bitbang =
55 container_of(ctrl, struct mdio_gpio_info, ctrl);
56
57 gpio_set_value(bitbang->mdio, what);
58}
59
60static void mdc(struct mdiobb_ctrl *ctrl, int what)
61{
62 struct mdio_gpio_info *bitbang =
63 container_of(ctrl, struct mdio_gpio_info, ctrl);
64
65 gpio_set_value(bitbang->mdc, what);
66}
67
68static struct mdiobb_ops mdio_gpio_ops = {
69 .owner = THIS_MODULE,
70 .set_mdc = mdc,
71 .set_mdio_dir = mdio_dir,
72 .set_mdio_data = mdio,
73 .get_mdio_data = mdio_read,
74};
75
76static int __devinit mdio_ofgpio_bitbang_init(struct mii_bus *bus,
77 struct device_node *np)
78{
79 struct mdio_gpio_info *bitbang = bus->priv;
80
81 bitbang->mdc = of_get_gpio(np, 0);
82 bitbang->mdio = of_get_gpio(np, 1);
83
84 if (bitbang->mdc < 0 || bitbang->mdio < 0)
85 return -ENODEV;
86
87 snprintf(bus->id, MII_BUS_ID_SIZE, "%x", bitbang->mdc);
88 return 0;
89}
90
91static void __devinit add_phy(struct mii_bus *bus, struct device_node *np)
92{
93 const u32 *data;
94 int len, id, irq;
95
96 data = of_get_property(np, "reg", &len);
97 if (!data || len != 4)
98 return;
99
100 id = *data;
101 bus->phy_mask &= ~(1 << id);
102
103 irq = of_irq_to_resource(np, 0, NULL);
104 if (irq != NO_IRQ)
105 bus->irq[id] = irq;
106}
107
108static int __devinit mdio_ofgpio_probe(struct of_device *ofdev,
109 const struct of_device_id *match)
110{
111 struct device_node *np = NULL;
112 struct mii_bus *new_bus;
113 struct mdio_gpio_info *bitbang;
114 int ret = -ENOMEM;
115 int i;
116
117 bitbang = kzalloc(sizeof(struct mdio_gpio_info), GFP_KERNEL);
118 if (!bitbang)
119 goto out;
120
121 bitbang->ctrl.ops = &mdio_gpio_ops;
122
123 new_bus = alloc_mdio_bitbang(&bitbang->ctrl);
124 if (!new_bus)
125 goto out_free_priv;
126
127 new_bus->name = "GPIO Bitbanged MII",
128
129 ret = mdio_ofgpio_bitbang_init(new_bus, ofdev->node);
130 if (ret)
131 goto out_free_bus;
132
133 new_bus->phy_mask = ~0;
134 new_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
135 if (!new_bus->irq)
136 goto out_free_bus;
137
138 for (i = 0; i < PHY_MAX_ADDR; i++)
139 new_bus->irq[i] = -1;
140
141 while ((np = of_get_next_child(ofdev->node, np)))
142 if (!strcmp(np->type, "ethernet-phy"))
143 add_phy(new_bus, np);
144
145 new_bus->dev = &ofdev->dev;
146 dev_set_drvdata(&ofdev->dev, new_bus);
147
148 ret = mdiobus_register(new_bus);
149 if (ret)
150 goto out_free_irqs;
151
152 return 0;
153
154out_free_irqs:
155 dev_set_drvdata(&ofdev->dev, NULL);
156 kfree(new_bus->irq);
157out_free_bus:
158 kfree(new_bus);
159out_free_priv:
160 free_mdio_bitbang(new_bus);
161out:
162 return ret;
163}
164
165static int mdio_ofgpio_remove(struct of_device *ofdev)
166{
167 struct mii_bus *bus = dev_get_drvdata(&ofdev->dev);
168 struct mdio_gpio_info *bitbang = bus->priv;
169
170 mdiobus_unregister(bus);
171 free_mdio_bitbang(bus);
172 dev_set_drvdata(&ofdev->dev, NULL);
173 kfree(bus->irq);
174 kfree(bitbang);
175 kfree(bus);
176
177 return 0;
178}
179
180static struct of_device_id mdio_ofgpio_match[] = {
181 {
182 .compatible = "virtual,mdio-gpio",
183 },
184 {},
185};
186
187static struct of_platform_driver mdio_ofgpio_driver = {
188 .name = "mdio-gpio",
189 .match_table = mdio_ofgpio_match,
190 .probe = mdio_ofgpio_probe,
191 .remove = mdio_ofgpio_remove,
192};
193
194static int mdio_ofgpio_init(void)
195{
196 return of_register_platform_driver(&mdio_ofgpio_driver);
197}
198
199static void mdio_ofgpio_exit(void)
200{
201 of_unregister_platform_driver(&mdio_ofgpio_driver);
202}
203
204module_init(mdio_ofgpio_init);
205module_exit(mdio_ofgpio_exit);
diff --git a/drivers/net/ppp_generic.c b/drivers/net/ppp_generic.c
index 83625fdff3dd..6b1d7a8edf15 100644
--- a/drivers/net/ppp_generic.c
+++ b/drivers/net/ppp_generic.c
@@ -363,7 +363,7 @@ static int ppp_open(struct inode *inode, struct file *file)
363 return 0; 363 return 0;
364} 364}
365 365
366static int ppp_release(struct inode *inode, struct file *file) 366static int ppp_release(struct inode *unused, struct file *file)
367{ 367{
368 struct ppp_file *pf = file->private_data; 368 struct ppp_file *pf = file->private_data;
369 struct ppp *ppp; 369 struct ppp *ppp;
@@ -547,8 +547,7 @@ static int get_filter(void __user *arg, struct sock_filter **p)
547} 547}
548#endif /* CONFIG_PPP_FILTER */ 548#endif /* CONFIG_PPP_FILTER */
549 549
550static int ppp_ioctl(struct inode *inode, struct file *file, 550static long ppp_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
551 unsigned int cmd, unsigned long arg)
552{ 551{
553 struct ppp_file *pf = file->private_data; 552 struct ppp_file *pf = file->private_data;
554 struct ppp *ppp; 553 struct ppp *ppp;
@@ -576,24 +575,29 @@ static int ppp_ioctl(struct inode *inode, struct file *file,
576 * this fd and reopening /dev/ppp. 575 * this fd and reopening /dev/ppp.
577 */ 576 */
578 err = -EINVAL; 577 err = -EINVAL;
578 lock_kernel();
579 if (pf->kind == INTERFACE) { 579 if (pf->kind == INTERFACE) {
580 ppp = PF_TO_PPP(pf); 580 ppp = PF_TO_PPP(pf);
581 if (file == ppp->owner) 581 if (file == ppp->owner)
582 ppp_shutdown_interface(ppp); 582 ppp_shutdown_interface(ppp);
583 } 583 }
584 if (atomic_read(&file->f_count) <= 2) { 584 if (atomic_read(&file->f_count) <= 2) {
585 ppp_release(inode, file); 585 ppp_release(NULL, file);
586 err = 0; 586 err = 0;
587 } else 587 } else
588 printk(KERN_DEBUG "PPPIOCDETACH file->f_count=%d\n", 588 printk(KERN_DEBUG "PPPIOCDETACH file->f_count=%d\n",
589 atomic_read(&file->f_count)); 589 atomic_read(&file->f_count));
590 unlock_kernel();
590 return err; 591 return err;
591 } 592 }
592 593
593 if (pf->kind == CHANNEL) { 594 if (pf->kind == CHANNEL) {
594 struct channel *pch = PF_TO_CHANNEL(pf); 595 struct channel *pch;
595 struct ppp_channel *chan; 596 struct ppp_channel *chan;
596 597
598 lock_kernel();
599 pch = PF_TO_CHANNEL(pf);
600
597 switch (cmd) { 601 switch (cmd) {
598 case PPPIOCCONNECT: 602 case PPPIOCCONNECT:
599 if (get_user(unit, p)) 603 if (get_user(unit, p))
@@ -613,6 +617,7 @@ static int ppp_ioctl(struct inode *inode, struct file *file,
613 err = chan->ops->ioctl(chan, cmd, arg); 617 err = chan->ops->ioctl(chan, cmd, arg);
614 up_read(&pch->chan_sem); 618 up_read(&pch->chan_sem);
615 } 619 }
620 unlock_kernel();
616 return err; 621 return err;
617 } 622 }
618 623
@@ -622,6 +627,7 @@ static int ppp_ioctl(struct inode *inode, struct file *file,
622 return -EINVAL; 627 return -EINVAL;
623 } 628 }
624 629
630 lock_kernel();
625 ppp = PF_TO_PPP(pf); 631 ppp = PF_TO_PPP(pf);
626 switch (cmd) { 632 switch (cmd) {
627 case PPPIOCSMRU: 633 case PPPIOCSMRU:
@@ -769,7 +775,7 @@ static int ppp_ioctl(struct inode *inode, struct file *file,
769 default: 775 default:
770 err = -ENOTTY; 776 err = -ENOTTY;
771 } 777 }
772 778 unlock_kernel();
773 return err; 779 return err;
774} 780}
775 781
@@ -781,6 +787,7 @@ static int ppp_unattached_ioctl(struct ppp_file *pf, struct file *file,
781 struct channel *chan; 787 struct channel *chan;
782 int __user *p = (int __user *)arg; 788 int __user *p = (int __user *)arg;
783 789
790 lock_kernel();
784 switch (cmd) { 791 switch (cmd) {
785 case PPPIOCNEWUNIT: 792 case PPPIOCNEWUNIT:
786 /* Create a new ppp unit */ 793 /* Create a new ppp unit */
@@ -829,6 +836,7 @@ static int ppp_unattached_ioctl(struct ppp_file *pf, struct file *file,
829 default: 836 default:
830 err = -ENOTTY; 837 err = -ENOTTY;
831 } 838 }
839 unlock_kernel();
832 return err; 840 return err;
833} 841}
834 842
@@ -837,7 +845,7 @@ static const struct file_operations ppp_device_fops = {
837 .read = ppp_read, 845 .read = ppp_read,
838 .write = ppp_write, 846 .write = ppp_write,
839 .poll = ppp_poll, 847 .poll = ppp_poll,
840 .ioctl = ppp_ioctl, 848 .unlocked_ioctl = ppp_ioctl,
841 .open = ppp_open, 849 .open = ppp_open,
842 .release = ppp_release 850 .release = ppp_release
843}; 851};
diff --git a/drivers/net/ps3_gelic_net.c b/drivers/net/ps3_gelic_net.c
index e365efb3c627..2eb54fd7bed5 100644
--- a/drivers/net/ps3_gelic_net.c
+++ b/drivers/net/ps3_gelic_net.c
@@ -110,7 +110,7 @@ static void gelic_card_get_ether_port_status(struct gelic_card *card,
110void gelic_card_up(struct gelic_card *card) 110void gelic_card_up(struct gelic_card *card)
111{ 111{
112 pr_debug("%s: called\n", __func__); 112 pr_debug("%s: called\n", __func__);
113 down(&card->updown_lock); 113 mutex_lock(&card->updown_lock);
114 if (atomic_inc_return(&card->users) == 1) { 114 if (atomic_inc_return(&card->users) == 1) {
115 pr_debug("%s: real do\n", __func__); 115 pr_debug("%s: real do\n", __func__);
116 /* enable irq */ 116 /* enable irq */
@@ -120,7 +120,7 @@ void gelic_card_up(struct gelic_card *card)
120 120
121 napi_enable(&card->napi); 121 napi_enable(&card->napi);
122 } 122 }
123 up(&card->updown_lock); 123 mutex_unlock(&card->updown_lock);
124 pr_debug("%s: done\n", __func__); 124 pr_debug("%s: done\n", __func__);
125} 125}
126 126
@@ -128,7 +128,7 @@ void gelic_card_down(struct gelic_card *card)
128{ 128{
129 u64 mask; 129 u64 mask;
130 pr_debug("%s: called\n", __func__); 130 pr_debug("%s: called\n", __func__);
131 down(&card->updown_lock); 131 mutex_lock(&card->updown_lock);
132 if (atomic_dec_if_positive(&card->users) == 0) { 132 if (atomic_dec_if_positive(&card->users) == 0) {
133 pr_debug("%s: real do\n", __func__); 133 pr_debug("%s: real do\n", __func__);
134 napi_disable(&card->napi); 134 napi_disable(&card->napi);
@@ -146,7 +146,7 @@ void gelic_card_down(struct gelic_card *card)
146 /* stop tx */ 146 /* stop tx */
147 gelic_card_disable_txdmac(card); 147 gelic_card_disable_txdmac(card);
148 } 148 }
149 up(&card->updown_lock); 149 mutex_unlock(&card->updown_lock);
150 pr_debug("%s: done\n", __func__); 150 pr_debug("%s: done\n", __func__);
151} 151}
152 152
@@ -1534,7 +1534,7 @@ static struct gelic_card *gelic_alloc_card_net(struct net_device **netdev)
1534 INIT_WORK(&card->tx_timeout_task, gelic_net_tx_timeout_task); 1534 INIT_WORK(&card->tx_timeout_task, gelic_net_tx_timeout_task);
1535 init_waitqueue_head(&card->waitq); 1535 init_waitqueue_head(&card->waitq);
1536 atomic_set(&card->tx_timeout_task_counter, 0); 1536 atomic_set(&card->tx_timeout_task_counter, 0);
1537 init_MUTEX(&card->updown_lock); 1537 mutex_init(&card->updown_lock);
1538 atomic_set(&card->users, 0); 1538 atomic_set(&card->users, 0);
1539 1539
1540 return card; 1540 return card;
diff --git a/drivers/net/ps3_gelic_net.h b/drivers/net/ps3_gelic_net.h
index 520f143c2c09..8b413868bbe2 100644
--- a/drivers/net/ps3_gelic_net.h
+++ b/drivers/net/ps3_gelic_net.h
@@ -298,7 +298,7 @@ struct gelic_card {
298 wait_queue_head_t waitq; 298 wait_queue_head_t waitq;
299 299
300 /* only first user should up the card */ 300 /* only first user should up the card */
301 struct semaphore updown_lock; 301 struct mutex updown_lock;
302 atomic_t users; 302 atomic_t users;
303 303
304 u64 ether_port_status; 304 u64 ether_port_status;
diff --git a/drivers/net/ps3_gelic_wireless.c b/drivers/net/ps3_gelic_wireless.c
index 1dae1f2ed813..6b2dee0cf3a9 100644
--- a/drivers/net/ps3_gelic_wireless.c
+++ b/drivers/net/ps3_gelic_wireless.c
@@ -45,7 +45,8 @@
45#include "ps3_gelic_wireless.h" 45#include "ps3_gelic_wireless.h"
46 46
47 47
48static int gelic_wl_start_scan(struct gelic_wl_info *wl, int always_scan); 48static int gelic_wl_start_scan(struct gelic_wl_info *wl, int always_scan,
49 u8 *essid, size_t essid_len);
49static int gelic_wl_try_associate(struct net_device *netdev); 50static int gelic_wl_try_associate(struct net_device *netdev);
50 51
51/* 52/*
@@ -105,6 +106,7 @@ static const struct eurus_cmd_arg_info cmd_info[GELIC_EURUS_CMD_MAX_INDEX] = {
105 [GELIC_EURUS_CMD_GET_WEP_CFG] = { .post_arg = 1}, 106 [GELIC_EURUS_CMD_GET_WEP_CFG] = { .post_arg = 1},
106 [GELIC_EURUS_CMD_GET_WPA_CFG] = { .post_arg = 1}, 107 [GELIC_EURUS_CMD_GET_WPA_CFG] = { .post_arg = 1},
107 [GELIC_EURUS_CMD_GET_RSSI_CFG] = { .post_arg = 1}, 108 [GELIC_EURUS_CMD_GET_RSSI_CFG] = { .post_arg = 1},
109 [GELIC_EURUS_CMD_START_SCAN] = { .pre_arg = 1},
108 [GELIC_EURUS_CMD_GET_SCAN] = { .post_arg = 1}, 110 [GELIC_EURUS_CMD_GET_SCAN] = { .post_arg = 1},
109}; 111};
110 112
@@ -163,7 +165,9 @@ static void gelic_eurus_sync_cmd_worker(struct work_struct *work)
163 card = port_to_card(wl_port(wl)); 165 card = port_to_card(wl_port(wl));
164 166
165 if (cmd_info[cmd->cmd].pre_arg) { 167 if (cmd_info[cmd->cmd].pre_arg) {
166 arg1 = ps3_mm_phys_to_lpar(__pa(cmd->buffer)); 168 arg1 = (cmd->buffer) ?
169 ps3_mm_phys_to_lpar(__pa(cmd->buffer)) :
170 0;
167 arg2 = cmd->buf_size; 171 arg2 = cmd->buf_size;
168 } else { 172 } else {
169 arg1 = 0; 173 arg1 = 0;
@@ -240,12 +244,12 @@ static u32 gelic_wl_get_link(struct net_device *netdev)
240 u32 ret; 244 u32 ret;
241 245
242 pr_debug("%s: <-\n", __func__); 246 pr_debug("%s: <-\n", __func__);
243 down(&wl->assoc_stat_lock); 247 mutex_lock(&wl->assoc_stat_lock);
244 if (wl->assoc_stat == GELIC_WL_ASSOC_STAT_ASSOCIATED) 248 if (wl->assoc_stat == GELIC_WL_ASSOC_STAT_ASSOCIATED)
245 ret = 1; 249 ret = 1;
246 else 250 else
247 ret = 0; 251 ret = 0;
248 up(&wl->assoc_stat_lock); 252 mutex_unlock(&wl->assoc_stat_lock);
249 pr_debug("%s: ->\n", __func__); 253 pr_debug("%s: ->\n", __func__);
250 return ret; 254 return ret;
251} 255}
@@ -350,7 +354,8 @@ static int gelic_wl_get_range(struct net_device *netdev,
350 354
351 /* encryption capability */ 355 /* encryption capability */
352 range->enc_capa = IW_ENC_CAPA_WPA | 356 range->enc_capa = IW_ENC_CAPA_WPA |
353 IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP; 357 IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP |
358 IW_ENC_CAPA_4WAY_HANDSHAKE;
354 if (wpa2_capable()) 359 if (wpa2_capable())
355 range->enc_capa |= IW_ENC_CAPA_WPA2; 360 range->enc_capa |= IW_ENC_CAPA_WPA2;
356 range->encoding_size[0] = 5; /* 40bit WEP */ 361 range->encoding_size[0] = 5; /* 40bit WEP */
@@ -359,6 +364,9 @@ static int gelic_wl_get_range(struct net_device *netdev,
359 range->num_encoding_sizes = 3; 364 range->num_encoding_sizes = 3;
360 range->max_encoding_tokens = GELIC_WEP_KEYS; 365 range->max_encoding_tokens = GELIC_WEP_KEYS;
361 366
367 /* scan capability */
368 range->scan_capa = IW_SCAN_CAPA_ESSID;
369
362 pr_debug("%s: ->\n", __func__); 370 pr_debug("%s: ->\n", __func__);
363 return 0; 371 return 0;
364 372
@@ -370,8 +378,18 @@ static int gelic_wl_set_scan(struct net_device *netdev,
370 union iwreq_data *wrqu, char *extra) 378 union iwreq_data *wrqu, char *extra)
371{ 379{
372 struct gelic_wl_info *wl = port_wl(netdev_priv(netdev)); 380 struct gelic_wl_info *wl = port_wl(netdev_priv(netdev));
373 381 struct iw_scan_req *req;
374 return gelic_wl_start_scan(wl, 1); 382 u8 *essid = NULL;
383 size_t essid_len = 0;
384
385 if (wrqu->data.length == sizeof(struct iw_scan_req) &&
386 wrqu->data.flags & IW_SCAN_THIS_ESSID) {
387 req = (struct iw_scan_req*)extra;
388 essid = req->essid;
389 essid_len = req->essid_len;
390 pr_debug("%s: ESSID scan =%s\n", __func__, essid);
391 }
392 return gelic_wl_start_scan(wl, 1, essid, essid_len);
375} 393}
376 394
377#define OUI_LEN 3 395#define OUI_LEN 3
@@ -553,6 +571,7 @@ static void gelic_wl_parse_ie(u8 *data, size_t len,
553 * independent format 571 * independent format
554 */ 572 */
555static char *gelic_wl_translate_scan(struct net_device *netdev, 573static char *gelic_wl_translate_scan(struct net_device *netdev,
574 struct iw_request_info *info,
556 char *ev, 575 char *ev,
557 char *stop, 576 char *stop,
558 struct gelic_wl_scan_info *network) 577 struct gelic_wl_scan_info *network)
@@ -570,26 +589,26 @@ static char *gelic_wl_translate_scan(struct net_device *netdev,
570 iwe.cmd = SIOCGIWAP; 589 iwe.cmd = SIOCGIWAP;
571 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 590 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
572 memcpy(iwe.u.ap_addr.sa_data, &scan->bssid[2], ETH_ALEN); 591 memcpy(iwe.u.ap_addr.sa_data, &scan->bssid[2], ETH_ALEN);
573 ev = iwe_stream_add_event(ev, stop, &iwe, IW_EV_ADDR_LEN); 592 ev = iwe_stream_add_event(info, ev, stop, &iwe, IW_EV_ADDR_LEN);
574 593
575 /* ESSID */ 594 /* ESSID */
576 iwe.cmd = SIOCGIWESSID; 595 iwe.cmd = SIOCGIWESSID;
577 iwe.u.data.flags = 1; 596 iwe.u.data.flags = 1;
578 iwe.u.data.length = strnlen(scan->essid, 32); 597 iwe.u.data.length = strnlen(scan->essid, 32);
579 ev = iwe_stream_add_point(ev, stop, &iwe, scan->essid); 598 ev = iwe_stream_add_point(info, ev, stop, &iwe, scan->essid);
580 599
581 /* FREQUENCY */ 600 /* FREQUENCY */
582 iwe.cmd = SIOCGIWFREQ; 601 iwe.cmd = SIOCGIWFREQ;
583 iwe.u.freq.m = be16_to_cpu(scan->channel); 602 iwe.u.freq.m = be16_to_cpu(scan->channel);
584 iwe.u.freq.e = 0; /* table value in MHz */ 603 iwe.u.freq.e = 0; /* table value in MHz */
585 iwe.u.freq.i = 0; 604 iwe.u.freq.i = 0;
586 ev = iwe_stream_add_event(ev, stop, &iwe, IW_EV_FREQ_LEN); 605 ev = iwe_stream_add_event(info, ev, stop, &iwe, IW_EV_FREQ_LEN);
587 606
588 /* RATES */ 607 /* RATES */
589 iwe.cmd = SIOCGIWRATE; 608 iwe.cmd = SIOCGIWRATE;
590 iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0; 609 iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0;
591 /* to stuff multiple values in one event */ 610 /* to stuff multiple values in one event */
592 tmp = ev + IW_EV_LCP_LEN; 611 tmp = ev + iwe_stream_lcp_len(info);
593 /* put them in ascendant order (older is first) */ 612 /* put them in ascendant order (older is first) */
594 i = 0; 613 i = 0;
595 j = 0; 614 j = 0;
@@ -602,16 +621,16 @@ static char *gelic_wl_translate_scan(struct net_device *netdev,
602 else 621 else
603 rate = scan->rate[i++] & 0x7f; 622 rate = scan->rate[i++] & 0x7f;
604 iwe.u.bitrate.value = rate * 500000; /* 500kbps unit */ 623 iwe.u.bitrate.value = rate * 500000; /* 500kbps unit */
605 tmp = iwe_stream_add_value(ev, tmp, stop, &iwe, 624 tmp = iwe_stream_add_value(info, ev, tmp, stop, &iwe,
606 IW_EV_PARAM_LEN); 625 IW_EV_PARAM_LEN);
607 } 626 }
608 while (j < network->rate_ext_len) { 627 while (j < network->rate_ext_len) {
609 iwe.u.bitrate.value = (scan->ext_rate[j++] & 0x7f) * 500000; 628 iwe.u.bitrate.value = (scan->ext_rate[j++] & 0x7f) * 500000;
610 tmp = iwe_stream_add_value(ev, tmp, stop, &iwe, 629 tmp = iwe_stream_add_value(info, ev, tmp, stop, &iwe,
611 IW_EV_PARAM_LEN); 630 IW_EV_PARAM_LEN);
612 } 631 }
613 /* Check if we added any rate */ 632 /* Check if we added any rate */
614 if (IW_EV_LCP_LEN < (tmp - ev)) 633 if (iwe_stream_lcp_len(info) < (tmp - ev))
615 ev = tmp; 634 ev = tmp;
616 635
617 /* ENCODE */ 636 /* ENCODE */
@@ -621,7 +640,7 @@ static char *gelic_wl_translate_scan(struct net_device *netdev,
621 else 640 else
622 iwe.u.data.flags = IW_ENCODE_DISABLED; 641 iwe.u.data.flags = IW_ENCODE_DISABLED;
623 iwe.u.data.length = 0; 642 iwe.u.data.length = 0;
624 ev = iwe_stream_add_point(ev, stop, &iwe, scan->essid); 643 ev = iwe_stream_add_point(info, ev, stop, &iwe, scan->essid);
625 644
626 /* MODE */ 645 /* MODE */
627 iwe.cmd = SIOCGIWMODE; 646 iwe.cmd = SIOCGIWMODE;
@@ -631,7 +650,7 @@ static char *gelic_wl_translate_scan(struct net_device *netdev,
631 iwe.u.mode = IW_MODE_MASTER; 650 iwe.u.mode = IW_MODE_MASTER;
632 else 651 else
633 iwe.u.mode = IW_MODE_ADHOC; 652 iwe.u.mode = IW_MODE_ADHOC;
634 ev = iwe_stream_add_event(ev, stop, &iwe, IW_EV_UINT_LEN); 653 ev = iwe_stream_add_event(info, ev, stop, &iwe, IW_EV_UINT_LEN);
635 } 654 }
636 655
637 /* QUAL */ 656 /* QUAL */
@@ -641,7 +660,7 @@ static char *gelic_wl_translate_scan(struct net_device *netdev,
641 iwe.u.qual.level = be16_to_cpu(scan->rssi); 660 iwe.u.qual.level = be16_to_cpu(scan->rssi);
642 iwe.u.qual.qual = be16_to_cpu(scan->rssi); 661 iwe.u.qual.qual = be16_to_cpu(scan->rssi);
643 iwe.u.qual.noise = 0; 662 iwe.u.qual.noise = 0;
644 ev = iwe_stream_add_event(ev, stop, &iwe, IW_EV_QUAL_LEN); 663 ev = iwe_stream_add_event(info, ev, stop, &iwe, IW_EV_QUAL_LEN);
645 664
646 /* RSN */ 665 /* RSN */
647 memset(&iwe, 0, sizeof(iwe)); 666 memset(&iwe, 0, sizeof(iwe));
@@ -651,7 +670,7 @@ static char *gelic_wl_translate_scan(struct net_device *netdev,
651 if (len) { 670 if (len) {
652 iwe.cmd = IWEVGENIE; 671 iwe.cmd = IWEVGENIE;
653 iwe.u.data.length = len; 672 iwe.u.data.length = len;
654 ev = iwe_stream_add_point(ev, stop, &iwe, buf); 673 ev = iwe_stream_add_point(info, ev, stop, &iwe, buf);
655 } 674 }
656 } else { 675 } else {
657 /* this scan info has IE data */ 676 /* this scan info has IE data */
@@ -666,7 +685,7 @@ static char *gelic_wl_translate_scan(struct net_device *netdev,
666 memcpy(buf, ie_info.wpa.data, ie_info.wpa.len); 685 memcpy(buf, ie_info.wpa.data, ie_info.wpa.len);
667 iwe.cmd = IWEVGENIE; 686 iwe.cmd = IWEVGENIE;
668 iwe.u.data.length = ie_info.wpa.len; 687 iwe.u.data.length = ie_info.wpa.len;
669 ev = iwe_stream_add_point(ev, stop, &iwe, buf); 688 ev = iwe_stream_add_point(info, ev, stop, &iwe, buf);
670 } 689 }
671 690
672 if (ie_info.rsn.len && (ie_info.rsn.len <= sizeof(buf))) { 691 if (ie_info.rsn.len && (ie_info.rsn.len <= sizeof(buf))) {
@@ -674,7 +693,7 @@ static char *gelic_wl_translate_scan(struct net_device *netdev,
674 memcpy(buf, ie_info.rsn.data, ie_info.rsn.len); 693 memcpy(buf, ie_info.rsn.data, ie_info.rsn.len);
675 iwe.cmd = IWEVGENIE; 694 iwe.cmd = IWEVGENIE;
676 iwe.u.data.length = ie_info.rsn.len; 695 iwe.u.data.length = ie_info.rsn.len;
677 ev = iwe_stream_add_point(ev, stop, &iwe, buf); 696 ev = iwe_stream_add_point(info, ev, stop, &iwe, buf);
678 } 697 }
679 } 698 }
680 699
@@ -695,7 +714,7 @@ static int gelic_wl_get_scan(struct net_device *netdev,
695 unsigned long this_time = jiffies; 714 unsigned long this_time = jiffies;
696 715
697 pr_debug("%s: <-\n", __func__); 716 pr_debug("%s: <-\n", __func__);
698 if (down_interruptible(&wl->scan_lock)) 717 if (mutex_lock_interruptible(&wl->scan_lock))
699 return -EAGAIN; 718 return -EAGAIN;
700 719
701 switch (wl->scan_stat) { 720 switch (wl->scan_stat) {
@@ -719,7 +738,8 @@ static int gelic_wl_get_scan(struct net_device *netdev,
719 if (wl->scan_age == 0 || 738 if (wl->scan_age == 0 ||
720 time_after(scan_info->last_scanned + wl->scan_age, 739 time_after(scan_info->last_scanned + wl->scan_age,
721 this_time)) 740 this_time))
722 ev = gelic_wl_translate_scan(netdev, ev, stop, 741 ev = gelic_wl_translate_scan(netdev, info,
742 ev, stop,
723 scan_info); 743 scan_info);
724 else 744 else
725 pr_debug("%s:entry too old\n", __func__); 745 pr_debug("%s:entry too old\n", __func__);
@@ -733,7 +753,7 @@ static int gelic_wl_get_scan(struct net_device *netdev,
733 wrqu->data.length = ev - extra; 753 wrqu->data.length = ev - extra;
734 wrqu->data.flags = 0; 754 wrqu->data.flags = 0;
735out: 755out:
736 up(&wl->scan_lock); 756 mutex_unlock(&wl->scan_lock);
737 pr_debug("%s: -> %d %d\n", __func__, ret, wrqu->data.length); 757 pr_debug("%s: -> %d %d\n", __func__, ret, wrqu->data.length);
738 return ret; 758 return ret;
739} 759}
@@ -979,7 +999,7 @@ static int gelic_wl_get_essid(struct net_device *netdev,
979 unsigned long irqflag; 999 unsigned long irqflag;
980 1000
981 pr_debug("%s: <- \n", __func__); 1001 pr_debug("%s: <- \n", __func__);
982 down(&wl->assoc_stat_lock); 1002 mutex_lock(&wl->assoc_stat_lock);
983 spin_lock_irqsave(&wl->lock, irqflag); 1003 spin_lock_irqsave(&wl->lock, irqflag);
984 if (test_bit(GELIC_WL_STAT_ESSID_SET, &wl->stat) || 1004 if (test_bit(GELIC_WL_STAT_ESSID_SET, &wl->stat) ||
985 wl->assoc_stat == GELIC_WL_ASSOC_STAT_ASSOCIATED) { 1005 wl->assoc_stat == GELIC_WL_ASSOC_STAT_ASSOCIATED) {
@@ -989,7 +1009,7 @@ static int gelic_wl_get_essid(struct net_device *netdev,
989 } else 1009 } else
990 data->essid.flags = 0; 1010 data->essid.flags = 0;
991 1011
992 up(&wl->assoc_stat_lock); 1012 mutex_unlock(&wl->assoc_stat_lock);
993 spin_unlock_irqrestore(&wl->lock, irqflag); 1013 spin_unlock_irqrestore(&wl->lock, irqflag);
994 pr_debug("%s: -> len=%d \n", __func__, data->essid.length); 1014 pr_debug("%s: -> len=%d \n", __func__, data->essid.length);
995 1015
@@ -1170,7 +1190,7 @@ static int gelic_wl_get_ap(struct net_device *netdev,
1170 unsigned long irqflag; 1190 unsigned long irqflag;
1171 1191
1172 pr_debug("%s: <-\n", __func__); 1192 pr_debug("%s: <-\n", __func__);
1173 down(&wl->assoc_stat_lock); 1193 mutex_lock(&wl->assoc_stat_lock);
1174 spin_lock_irqsave(&wl->lock, irqflag); 1194 spin_lock_irqsave(&wl->lock, irqflag);
1175 if (wl->assoc_stat == GELIC_WL_ASSOC_STAT_ASSOCIATED) { 1195 if (wl->assoc_stat == GELIC_WL_ASSOC_STAT_ASSOCIATED) {
1176 data->ap_addr.sa_family = ARPHRD_ETHER; 1196 data->ap_addr.sa_family = ARPHRD_ETHER;
@@ -1180,7 +1200,7 @@ static int gelic_wl_get_ap(struct net_device *netdev,
1180 memset(data->ap_addr.sa_data, 0, ETH_ALEN); 1200 memset(data->ap_addr.sa_data, 0, ETH_ALEN);
1181 1201
1182 spin_unlock_irqrestore(&wl->lock, irqflag); 1202 spin_unlock_irqrestore(&wl->lock, irqflag);
1183 up(&wl->assoc_stat_lock); 1203 mutex_unlock(&wl->assoc_stat_lock);
1184 pr_debug("%s: ->\n", __func__); 1204 pr_debug("%s: ->\n", __func__);
1185 return 0; 1205 return 0;
1186} 1206}
@@ -1256,42 +1276,19 @@ static int gelic_wl_set_encodeext(struct net_device *netdev,
1256 set_bit(key_index, &wl->key_enabled); 1276 set_bit(key_index, &wl->key_enabled);
1257 /* remember wep info changed */ 1277 /* remember wep info changed */
1258 set_bit(GELIC_WL_STAT_CONFIGURED, &wl->stat); 1278 set_bit(GELIC_WL_STAT_CONFIGURED, &wl->stat);
1259 } else if ((alg == IW_ENCODE_ALG_TKIP) || (alg == IW_ENCODE_ALG_CCMP)) { 1279 } else if (alg == IW_ENCODE_ALG_PMK) {
1260 pr_debug("%s: TKIP/CCMP requested alg=%d\n", __func__, alg); 1280 if (ext->key_len != WPA_PSK_LEN) {
1261 /* check key length */ 1281 pr_err("%s: PSK length wrong %d\n", __func__,
1262 if (IW_ENCODING_TOKEN_MAX < ext->key_len) { 1282 ext->key_len);
1263 pr_info("%s: key is too long %d\n", __func__,
1264 ext->key_len);
1265 ret = -EINVAL; 1283 ret = -EINVAL;
1266 goto done; 1284 goto done;
1267 } 1285 }
1268 if (alg == IW_ENCODE_ALG_CCMP) { 1286 memset(wl->psk, 0, sizeof(wl->psk));
1269 pr_debug("%s: AES selected\n", __func__); 1287 memcpy(wl->psk, ext->key, ext->key_len);
1270 wl->group_cipher_method = GELIC_WL_CIPHER_AES; 1288 wl->psk_len = ext->key_len;
1271 wl->pairwise_cipher_method = GELIC_WL_CIPHER_AES; 1289 wl->psk_type = GELIC_EURUS_WPA_PSK_BIN;
1272 wl->wpa_level = GELIC_WL_WPA_LEVEL_WPA2; 1290 /* remember PSK configured */
1273 } else { 1291 set_bit(GELIC_WL_STAT_WPA_PSK_SET, &wl->stat);
1274 pr_debug("%s: TKIP selected, WPA forced\n", __func__);
1275 wl->group_cipher_method = GELIC_WL_CIPHER_TKIP;
1276 wl->pairwise_cipher_method = GELIC_WL_CIPHER_TKIP;
1277 /* FIXME: how do we do if WPA2 + TKIP? */
1278 wl->wpa_level = GELIC_WL_WPA_LEVEL_WPA;
1279 }
1280 if (flags & IW_ENCODE_RESTRICTED)
1281 BUG();
1282 wl->auth_method = GELIC_EURUS_AUTH_OPEN;
1283 /* We should use same key for both and unicast */
1284 if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY)
1285 pr_debug("%s: group key \n", __func__);
1286 else
1287 pr_debug("%s: unicast key \n", __func__);
1288 /* OK, update the key */
1289 wl->key_len[key_index] = ext->key_len;
1290 memset(wl->key[key_index], 0, IW_ENCODING_TOKEN_MAX);
1291 memcpy(wl->key[key_index], ext->key, ext->key_len);
1292 set_bit(key_index, &wl->key_enabled);
1293 /* remember info changed */
1294 set_bit(GELIC_WL_STAT_CONFIGURED, &wl->stat);
1295 } 1292 }
1296done: 1293done:
1297 spin_unlock_irqrestore(&wl->lock, irqflag); 1294 spin_unlock_irqrestore(&wl->lock, irqflag);
@@ -1397,6 +1394,7 @@ static int gelic_wl_get_mode(struct net_device *netdev,
1397 return 0; 1394 return 0;
1398} 1395}
1399 1396
1397#ifdef CONFIG_GELIC_WIRELESS_OLD_PSK_INTERFACE
1400/* SIOCIWFIRSTPRIV */ 1398/* SIOCIWFIRSTPRIV */
1401static int hex2bin(u8 *str, u8 *bin, unsigned int len) 1399static int hex2bin(u8 *str, u8 *bin, unsigned int len)
1402{ 1400{
@@ -1501,6 +1499,7 @@ static int gelic_wl_priv_get_psk(struct net_device *net_dev,
1501 pr_debug("%s:-> %d\n", __func__, data->data.length); 1499 pr_debug("%s:-> %d\n", __func__, data->data.length);
1502 return 0; 1500 return 0;
1503} 1501}
1502#endif
1504 1503
1505/* SIOCGIWNICKN */ 1504/* SIOCGIWNICKN */
1506static int gelic_wl_get_nick(struct net_device *net_dev, 1505static int gelic_wl_get_nick(struct net_device *net_dev,
@@ -1524,15 +1523,20 @@ static struct iw_statistics *gelic_wl_get_wireless_stats(
1524 struct gelic_eurus_cmd *cmd; 1523 struct gelic_eurus_cmd *cmd;
1525 struct iw_statistics *is; 1524 struct iw_statistics *is;
1526 struct gelic_eurus_rssi_info *rssi; 1525 struct gelic_eurus_rssi_info *rssi;
1526 void *buf;
1527 1527
1528 pr_debug("%s: <-\n", __func__); 1528 pr_debug("%s: <-\n", __func__);
1529 1529
1530 buf = (void *)__get_free_page(GFP_KERNEL);
1531 if (!buf)
1532 return NULL;
1533
1530 is = &wl->iwstat; 1534 is = &wl->iwstat;
1531 memset(is, 0, sizeof(*is)); 1535 memset(is, 0, sizeof(*is));
1532 cmd = gelic_eurus_sync_cmd(wl, GELIC_EURUS_CMD_GET_RSSI_CFG, 1536 cmd = gelic_eurus_sync_cmd(wl, GELIC_EURUS_CMD_GET_RSSI_CFG,
1533 wl->buf, sizeof(*rssi)); 1537 buf, sizeof(*rssi));
1534 if (cmd && !cmd->status && !cmd->cmd_status) { 1538 if (cmd && !cmd->status && !cmd->cmd_status) {
1535 rssi = wl->buf; 1539 rssi = buf;
1536 is->qual.level = be16_to_cpu(rssi->rssi); 1540 is->qual.level = be16_to_cpu(rssi->rssi);
1537 is->qual.updated = IW_QUAL_LEVEL_UPDATED | 1541 is->qual.updated = IW_QUAL_LEVEL_UPDATED |
1538 IW_QUAL_QUAL_INVALID | IW_QUAL_NOISE_INVALID; 1542 IW_QUAL_QUAL_INVALID | IW_QUAL_NOISE_INVALID;
@@ -1541,6 +1545,7 @@ static struct iw_statistics *gelic_wl_get_wireless_stats(
1541 is->qual.updated = IW_QUAL_ALL_INVALID; 1545 is->qual.updated = IW_QUAL_ALL_INVALID;
1542 1546
1543 kfree(cmd); 1547 kfree(cmd);
1548 free_page((unsigned long)buf);
1544 pr_debug("%s: ->\n", __func__); 1549 pr_debug("%s: ->\n", __func__);
1545 return is; 1550 return is;
1546} 1551}
@@ -1548,13 +1553,16 @@ static struct iw_statistics *gelic_wl_get_wireless_stats(
1548/* 1553/*
1549 * scanning helpers 1554 * scanning helpers
1550 */ 1555 */
1551static int gelic_wl_start_scan(struct gelic_wl_info *wl, int always_scan) 1556static int gelic_wl_start_scan(struct gelic_wl_info *wl, int always_scan,
1557 u8 *essid, size_t essid_len)
1552{ 1558{
1553 struct gelic_eurus_cmd *cmd; 1559 struct gelic_eurus_cmd *cmd;
1554 int ret = 0; 1560 int ret = 0;
1561 void *buf = NULL;
1562 size_t len;
1555 1563
1556 pr_debug("%s: <- always=%d\n", __func__, always_scan); 1564 pr_debug("%s: <- always=%d\n", __func__, always_scan);
1557 if (down_interruptible(&wl->scan_lock)) 1565 if (mutex_lock_interruptible(&wl->scan_lock))
1558 return -ERESTARTSYS; 1566 return -ERESTARTSYS;
1559 1567
1560 /* 1568 /*
@@ -1574,12 +1582,27 @@ static int gelic_wl_start_scan(struct gelic_wl_info *wl, int always_scan)
1574 complete(&wl->scan_done); 1582 complete(&wl->scan_done);
1575 goto out; 1583 goto out;
1576 } 1584 }
1585
1586 /* ESSID scan ? */
1587 if (essid_len && essid) {
1588 buf = (void *)__get_free_page(GFP_KERNEL);
1589 if (!buf) {
1590 ret = -ENOMEM;
1591 goto out;
1592 }
1593 len = IW_ESSID_MAX_SIZE; /* hypervisor always requires 32 */
1594 memset(buf, 0, len);
1595 memcpy(buf, essid, essid_len);
1596 pr_debug("%s: essid scan='%s'\n", __func__, (char *)buf);
1597 } else
1598 len = 0;
1599
1577 /* 1600 /*
1578 * issue start scan request 1601 * issue start scan request
1579 */ 1602 */
1580 wl->scan_stat = GELIC_WL_SCAN_STAT_SCANNING; 1603 wl->scan_stat = GELIC_WL_SCAN_STAT_SCANNING;
1581 cmd = gelic_eurus_sync_cmd(wl, GELIC_EURUS_CMD_START_SCAN, 1604 cmd = gelic_eurus_sync_cmd(wl, GELIC_EURUS_CMD_START_SCAN,
1582 NULL, 0); 1605 buf, len);
1583 if (!cmd || cmd->status || cmd->cmd_status) { 1606 if (!cmd || cmd->status || cmd->cmd_status) {
1584 wl->scan_stat = GELIC_WL_SCAN_STAT_INIT; 1607 wl->scan_stat = GELIC_WL_SCAN_STAT_INIT;
1585 complete(&wl->scan_done); 1608 complete(&wl->scan_done);
@@ -1588,7 +1611,8 @@ static int gelic_wl_start_scan(struct gelic_wl_info *wl, int always_scan)
1588 } 1611 }
1589 kfree(cmd); 1612 kfree(cmd);
1590out: 1613out:
1591 up(&wl->scan_lock); 1614 free_page((unsigned long)buf);
1615 mutex_unlock(&wl->scan_lock);
1592 pr_debug("%s: ->\n", __func__); 1616 pr_debug("%s: ->\n", __func__);
1593 return ret; 1617 return ret;
1594} 1618}
@@ -1607,10 +1631,17 @@ static void gelic_wl_scan_complete_event(struct gelic_wl_info *wl)
1607 union iwreq_data data; 1631 union iwreq_data data;
1608 unsigned long this_time = jiffies; 1632 unsigned long this_time = jiffies;
1609 unsigned int data_len, i, found, r; 1633 unsigned int data_len, i, found, r;
1634 void *buf;
1610 DECLARE_MAC_BUF(mac); 1635 DECLARE_MAC_BUF(mac);
1611 1636
1612 pr_debug("%s:start\n", __func__); 1637 pr_debug("%s:start\n", __func__);
1613 down(&wl->scan_lock); 1638 mutex_lock(&wl->scan_lock);
1639
1640 buf = (void *)__get_free_page(GFP_KERNEL);
1641 if (!buf) {
1642 pr_info("%s: scan buffer alloc failed\n", __func__);
1643 goto out;
1644 }
1614 1645
1615 if (wl->scan_stat != GELIC_WL_SCAN_STAT_SCANNING) { 1646 if (wl->scan_stat != GELIC_WL_SCAN_STAT_SCANNING) {
1616 /* 1647 /*
@@ -1622,7 +1653,7 @@ static void gelic_wl_scan_complete_event(struct gelic_wl_info *wl)
1622 } 1653 }
1623 1654
1624 cmd = gelic_eurus_sync_cmd(wl, GELIC_EURUS_CMD_GET_SCAN, 1655 cmd = gelic_eurus_sync_cmd(wl, GELIC_EURUS_CMD_GET_SCAN,
1625 wl->buf, PAGE_SIZE); 1656 buf, PAGE_SIZE);
1626 if (!cmd || cmd->status || cmd->cmd_status) { 1657 if (!cmd || cmd->status || cmd->cmd_status) {
1627 wl->scan_stat = GELIC_WL_SCAN_STAT_INIT; 1658 wl->scan_stat = GELIC_WL_SCAN_STAT_INIT;
1628 pr_info("%s:cmd failed\n", __func__); 1659 pr_info("%s:cmd failed\n", __func__);
@@ -1649,7 +1680,7 @@ static void gelic_wl_scan_complete_event(struct gelic_wl_info *wl)
1649 } 1680 }
1650 1681
1651 /* put them in the newtork_list */ 1682 /* put them in the newtork_list */
1652 for (i = 0, scan_info_size = 0, scan_info = wl->buf; 1683 for (i = 0, scan_info_size = 0, scan_info = buf;
1653 scan_info_size < data_len; 1684 scan_info_size < data_len;
1654 i++, scan_info_size += be16_to_cpu(scan_info->size), 1685 i++, scan_info_size += be16_to_cpu(scan_info->size),
1655 scan_info = (void *)scan_info + be16_to_cpu(scan_info->size)) { 1686 scan_info = (void *)scan_info + be16_to_cpu(scan_info->size)) {
@@ -1726,8 +1757,9 @@ static void gelic_wl_scan_complete_event(struct gelic_wl_info *wl)
1726 wireless_send_event(port_to_netdev(wl_port(wl)), SIOCGIWSCAN, &data, 1757 wireless_send_event(port_to_netdev(wl_port(wl)), SIOCGIWSCAN, &data,
1727 NULL); 1758 NULL);
1728out: 1759out:
1760 free_page((unsigned long)buf);
1729 complete(&wl->scan_done); 1761 complete(&wl->scan_done);
1730 up(&wl->scan_lock); 1762 mutex_unlock(&wl->scan_lock);
1731 pr_debug("%s:end\n", __func__); 1763 pr_debug("%s:end\n", __func__);
1732} 1764}
1733 1765
@@ -1848,7 +1880,10 @@ static int gelic_wl_do_wep_setup(struct gelic_wl_info *wl)
1848 1880
1849 pr_debug("%s: <-\n", __func__); 1881 pr_debug("%s: <-\n", __func__);
1850 /* we can assume no one should uses the buffer */ 1882 /* we can assume no one should uses the buffer */
1851 wep = wl->buf; 1883 wep = (struct gelic_eurus_wep_cfg *)__get_free_page(GFP_KERNEL);
1884 if (!wep)
1885 return -ENOMEM;
1886
1852 memset(wep, 0, sizeof(*wep)); 1887 memset(wep, 0, sizeof(*wep));
1853 1888
1854 if (wl->group_cipher_method == GELIC_WL_CIPHER_WEP) { 1889 if (wl->group_cipher_method == GELIC_WL_CIPHER_WEP) {
@@ -1898,6 +1933,7 @@ static int gelic_wl_do_wep_setup(struct gelic_wl_info *wl)
1898 1933
1899 kfree(cmd); 1934 kfree(cmd);
1900out: 1935out:
1936 free_page((unsigned long)wep);
1901 pr_debug("%s: ->\n", __func__); 1937 pr_debug("%s: ->\n", __func__);
1902 return ret; 1938 return ret;
1903} 1939}
@@ -1941,7 +1977,10 @@ static int gelic_wl_do_wpa_setup(struct gelic_wl_info *wl)
1941 1977
1942 pr_debug("%s: <-\n", __func__); 1978 pr_debug("%s: <-\n", __func__);
1943 /* we can assume no one should uses the buffer */ 1979 /* we can assume no one should uses the buffer */
1944 wpa = wl->buf; 1980 wpa = (struct gelic_eurus_wpa_cfg *)__get_free_page(GFP_KERNEL);
1981 if (!wpa)
1982 return -ENOMEM;
1983
1945 memset(wpa, 0, sizeof(*wpa)); 1984 memset(wpa, 0, sizeof(*wpa));
1946 1985
1947 if (!test_bit(GELIC_WL_STAT_WPA_PSK_SET, &wl->stat)) 1986 if (!test_bit(GELIC_WL_STAT_WPA_PSK_SET, &wl->stat))
@@ -2000,6 +2039,7 @@ static int gelic_wl_do_wpa_setup(struct gelic_wl_info *wl)
2000 else if (cmd->status || cmd->cmd_status) 2039 else if (cmd->status || cmd->cmd_status)
2001 ret = -ENXIO; 2040 ret = -ENXIO;
2002 kfree(cmd); 2041 kfree(cmd);
2042 free_page((unsigned long)wpa);
2003 pr_debug("%s: --> %d\n", __func__, ret); 2043 pr_debug("%s: --> %d\n", __func__, ret);
2004 return ret; 2044 return ret;
2005} 2045}
@@ -2018,7 +2058,10 @@ static int gelic_wl_associate_bss(struct gelic_wl_info *wl,
2018 pr_debug("%s: <-\n", __func__); 2058 pr_debug("%s: <-\n", __func__);
2019 2059
2020 /* do common config */ 2060 /* do common config */
2021 common = wl->buf; 2061 common = (struct gelic_eurus_common_cfg *)__get_free_page(GFP_KERNEL);
2062 if (!common)
2063 return -ENOMEM;
2064
2022 memset(common, 0, sizeof(*common)); 2065 memset(common, 0, sizeof(*common));
2023 common->bss_type = cpu_to_be16(GELIC_EURUS_BSS_INFRA); 2066 common->bss_type = cpu_to_be16(GELIC_EURUS_BSS_INFRA);
2024 common->op_mode = cpu_to_be16(GELIC_EURUS_OPMODE_11BG); 2067 common->op_mode = cpu_to_be16(GELIC_EURUS_OPMODE_11BG);
@@ -2104,6 +2147,7 @@ static int gelic_wl_associate_bss(struct gelic_wl_info *wl,
2104 pr_info("%s: connected\n", __func__); 2147 pr_info("%s: connected\n", __func__);
2105 } 2148 }
2106out: 2149out:
2150 free_page((unsigned long)common);
2107 pr_debug("%s: ->\n", __func__); 2151 pr_debug("%s: ->\n", __func__);
2108 return ret; 2152 return ret;
2109} 2153}
@@ -2151,7 +2195,7 @@ static void gelic_wl_disconnect_event(struct gelic_wl_info *wl,
2151 * As it waits with timeout, just leave assoc_done 2195 * As it waits with timeout, just leave assoc_done
2152 * uncompleted, then it terminates with timeout 2196 * uncompleted, then it terminates with timeout
2153 */ 2197 */
2154 if (down_trylock(&wl->assoc_stat_lock)) { 2198 if (!mutex_trylock(&wl->assoc_stat_lock)) {
2155 pr_debug("%s: already locked\n", __func__); 2199 pr_debug("%s: already locked\n", __func__);
2156 lock = 0; 2200 lock = 0;
2157 } else { 2201 } else {
@@ -2170,7 +2214,7 @@ static void gelic_wl_disconnect_event(struct gelic_wl_info *wl,
2170 netif_carrier_off(port_to_netdev(wl_port(wl))); 2214 netif_carrier_off(port_to_netdev(wl_port(wl)));
2171 2215
2172 if (lock) 2216 if (lock)
2173 up(&wl->assoc_stat_lock); 2217 mutex_unlock(&wl->assoc_stat_lock);
2174} 2218}
2175/* 2219/*
2176 * event worker 2220 * event worker
@@ -2255,15 +2299,30 @@ static void gelic_wl_assoc_worker(struct work_struct *work)
2255 2299
2256 struct gelic_wl_scan_info *best_bss; 2300 struct gelic_wl_scan_info *best_bss;
2257 int ret; 2301 int ret;
2302 unsigned long irqflag;
2303 u8 *essid;
2304 size_t essid_len;
2258 2305
2259 wl = container_of(work, struct gelic_wl_info, assoc_work.work); 2306 wl = container_of(work, struct gelic_wl_info, assoc_work.work);
2260 2307
2261 down(&wl->assoc_stat_lock); 2308 mutex_lock(&wl->assoc_stat_lock);
2262 2309
2263 if (wl->assoc_stat != GELIC_WL_ASSOC_STAT_DISCONN) 2310 if (wl->assoc_stat != GELIC_WL_ASSOC_STAT_DISCONN)
2264 goto out; 2311 goto out;
2265 2312
2266 ret = gelic_wl_start_scan(wl, 0); 2313 spin_lock_irqsave(&wl->lock, irqflag);
2314 if (test_bit(GELIC_WL_STAT_ESSID_SET, &wl->stat)) {
2315 pr_debug("%s: assoc ESSID configured %s\n", __func__,
2316 wl->essid);
2317 essid = wl->essid;
2318 essid_len = wl->essid_len;
2319 } else {
2320 essid = NULL;
2321 essid_len = 0;
2322 }
2323 spin_unlock_irqrestore(&wl->lock, irqflag);
2324
2325 ret = gelic_wl_start_scan(wl, 0, essid, essid_len);
2267 if (ret == -ERESTARTSYS) { 2326 if (ret == -ERESTARTSYS) {
2268 pr_debug("%s: scan start failed association\n", __func__); 2327 pr_debug("%s: scan start failed association\n", __func__);
2269 schedule_delayed_work(&wl->assoc_work, HZ/10); /*FIXME*/ 2328 schedule_delayed_work(&wl->assoc_work, HZ/10); /*FIXME*/
@@ -2282,7 +2341,7 @@ static void gelic_wl_assoc_worker(struct work_struct *work)
2282 wait_for_completion(&wl->scan_done); 2341 wait_for_completion(&wl->scan_done);
2283 2342
2284 pr_debug("%s: scan done\n", __func__); 2343 pr_debug("%s: scan done\n", __func__);
2285 down(&wl->scan_lock); 2344 mutex_lock(&wl->scan_lock);
2286 if (wl->scan_stat != GELIC_WL_SCAN_STAT_GOT_LIST) { 2345 if (wl->scan_stat != GELIC_WL_SCAN_STAT_GOT_LIST) {
2287 gelic_wl_send_iwap_event(wl, NULL); 2346 gelic_wl_send_iwap_event(wl, NULL);
2288 pr_info("%s: no scan list. association failed\n", __func__); 2347 pr_info("%s: no scan list. association failed\n", __func__);
@@ -2302,9 +2361,9 @@ static void gelic_wl_assoc_worker(struct work_struct *work)
2302 if (ret) 2361 if (ret)
2303 pr_info("%s: association failed %d\n", __func__, ret); 2362 pr_info("%s: association failed %d\n", __func__, ret);
2304scan_lock_out: 2363scan_lock_out:
2305 up(&wl->scan_lock); 2364 mutex_unlock(&wl->scan_lock);
2306out: 2365out:
2307 up(&wl->assoc_stat_lock); 2366 mutex_unlock(&wl->assoc_stat_lock);
2308} 2367}
2309/* 2368/*
2310 * Interrupt handler 2369 * Interrupt handler
@@ -2351,6 +2410,7 @@ static const iw_handler gelic_wl_wext_handler[] =
2351 IW_IOCTL(SIOCGIWNICKN) = gelic_wl_get_nick, 2410 IW_IOCTL(SIOCGIWNICKN) = gelic_wl_get_nick,
2352}; 2411};
2353 2412
2413#ifdef CONFIG_GELIC_WIRELESS_OLD_PSK_INTERFACE
2354static struct iw_priv_args gelic_wl_private_args[] = 2414static struct iw_priv_args gelic_wl_private_args[] =
2355{ 2415{
2356 { 2416 {
@@ -2372,15 +2432,18 @@ static const iw_handler gelic_wl_private_handler[] =
2372 gelic_wl_priv_set_psk, 2432 gelic_wl_priv_set_psk,
2373 gelic_wl_priv_get_psk, 2433 gelic_wl_priv_get_psk,
2374}; 2434};
2435#endif
2375 2436
2376static const struct iw_handler_def gelic_wl_wext_handler_def = { 2437static const struct iw_handler_def gelic_wl_wext_handler_def = {
2377 .num_standard = ARRAY_SIZE(gelic_wl_wext_handler), 2438 .num_standard = ARRAY_SIZE(gelic_wl_wext_handler),
2378 .standard = gelic_wl_wext_handler, 2439 .standard = gelic_wl_wext_handler,
2379 .get_wireless_stats = gelic_wl_get_wireless_stats, 2440 .get_wireless_stats = gelic_wl_get_wireless_stats,
2441#ifdef CONFIG_GELIC_WIRELESS_OLD_PSK_INTERFACE
2380 .num_private = ARRAY_SIZE(gelic_wl_private_handler), 2442 .num_private = ARRAY_SIZE(gelic_wl_private_handler),
2381 .num_private_args = ARRAY_SIZE(gelic_wl_private_args), 2443 .num_private_args = ARRAY_SIZE(gelic_wl_private_args),
2382 .private = gelic_wl_private_handler, 2444 .private = gelic_wl_private_handler,
2383 .private_args = gelic_wl_private_args, 2445 .private_args = gelic_wl_private_args,
2446#endif
2384}; 2447};
2385 2448
2386static struct net_device *gelic_wl_alloc(struct gelic_card *card) 2449static struct net_device *gelic_wl_alloc(struct gelic_card *card)
@@ -2431,8 +2494,8 @@ static struct net_device *gelic_wl_alloc(struct gelic_card *card)
2431 2494
2432 INIT_DELAYED_WORK(&wl->event_work, gelic_wl_event_worker); 2495 INIT_DELAYED_WORK(&wl->event_work, gelic_wl_event_worker);
2433 INIT_DELAYED_WORK(&wl->assoc_work, gelic_wl_assoc_worker); 2496 INIT_DELAYED_WORK(&wl->assoc_work, gelic_wl_assoc_worker);
2434 init_MUTEX(&wl->scan_lock); 2497 mutex_init(&wl->scan_lock);
2435 init_MUTEX(&wl->assoc_stat_lock); 2498 mutex_init(&wl->assoc_stat_lock);
2436 2499
2437 init_completion(&wl->scan_done); 2500 init_completion(&wl->scan_done);
2438 /* for the case that no scan request is issued and stop() is called */ 2501 /* for the case that no scan request is issued and stop() is called */
@@ -2446,16 +2509,9 @@ static struct net_device *gelic_wl_alloc(struct gelic_card *card)
2446 BUILD_BUG_ON(PAGE_SIZE < 2509 BUILD_BUG_ON(PAGE_SIZE <
2447 sizeof(struct gelic_eurus_scan_info) * 2510 sizeof(struct gelic_eurus_scan_info) *
2448 GELIC_EURUS_MAX_SCAN); 2511 GELIC_EURUS_MAX_SCAN);
2449 wl->buf = (void *)get_zeroed_page(GFP_KERNEL);
2450 if (!wl->buf) {
2451 pr_info("%s:buffer allocation failed\n", __func__);
2452 goto fail_getpage;
2453 }
2454 pr_debug("%s:end\n", __func__); 2512 pr_debug("%s:end\n", __func__);
2455 return netdev; 2513 return netdev;
2456 2514
2457fail_getpage:
2458 destroy_workqueue(wl->event_queue);
2459fail_event_workqueue: 2515fail_event_workqueue:
2460 destroy_workqueue(wl->eurus_cmd_queue); 2516 destroy_workqueue(wl->eurus_cmd_queue);
2461fail_cmd_workqueue: 2517fail_cmd_workqueue:
@@ -2474,8 +2530,6 @@ static void gelic_wl_free(struct gelic_wl_info *wl)
2474 2530
2475 pr_debug("%s: <-\n", __func__); 2531 pr_debug("%s: <-\n", __func__);
2476 2532
2477 free_page((unsigned long)wl->buf);
2478
2479 pr_debug("%s: destroy queues\n", __func__); 2533 pr_debug("%s: destroy queues\n", __func__);
2480 destroy_workqueue(wl->eurus_cmd_queue); 2534 destroy_workqueue(wl->eurus_cmd_queue);
2481 destroy_workqueue(wl->event_queue); 2535 destroy_workqueue(wl->event_queue);
diff --git a/drivers/net/ps3_gelic_wireless.h b/drivers/net/ps3_gelic_wireless.h
index 103697166720..5339e0078d18 100644
--- a/drivers/net/ps3_gelic_wireless.h
+++ b/drivers/net/ps3_gelic_wireless.h
@@ -241,7 +241,7 @@ enum gelic_wl_assoc_state {
241#define GELIC_WEP_KEYS 4 241#define GELIC_WEP_KEYS 4
242struct gelic_wl_info { 242struct gelic_wl_info {
243 /* bss list */ 243 /* bss list */
244 struct semaphore scan_lock; 244 struct mutex scan_lock;
245 struct list_head network_list; 245 struct list_head network_list;
246 struct list_head network_free_list; 246 struct list_head network_free_list;
247 struct gelic_wl_scan_info *networks; 247 struct gelic_wl_scan_info *networks;
@@ -266,7 +266,7 @@ struct gelic_wl_info {
266 enum gelic_wl_wpa_level wpa_level; /* wpa/wpa2 */ 266 enum gelic_wl_wpa_level wpa_level; /* wpa/wpa2 */
267 267
268 /* association handling */ 268 /* association handling */
269 struct semaphore assoc_stat_lock; 269 struct mutex assoc_stat_lock;
270 struct delayed_work assoc_work; 270 struct delayed_work assoc_work;
271 enum gelic_wl_assoc_state assoc_stat; 271 enum gelic_wl_assoc_state assoc_stat;
272 struct completion assoc_done; 272 struct completion assoc_done;
@@ -288,9 +288,6 @@ struct gelic_wl_info {
288 u8 active_bssid[ETH_ALEN]; /* associated bssid */ 288 u8 active_bssid[ETH_ALEN]; /* associated bssid */
289 unsigned int essid_len; 289 unsigned int essid_len;
290 290
291 /* buffer for hypervisor IO */
292 void *buf;
293
294 struct iw_public_data wireless_data; 291 struct iw_public_data wireless_data;
295 struct iw_statistics iwstat; 292 struct iw_statistics iwstat;
296}; 293};
diff --git a/drivers/net/qla3xxx.c b/drivers/net/qla3xxx.c
index bccee68bd48a..e7d48a352beb 100644
--- a/drivers/net/qla3xxx.c
+++ b/drivers/net/qla3xxx.c
@@ -1437,9 +1437,9 @@ static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1437 reg &= ~PHY_GIG_ALL_PARAMS; 1437 reg &= ~PHY_GIG_ALL_PARAMS;
1438 1438
1439 if(portConfiguration & PORT_CONFIG_1000MB_SPEED) { 1439 if(portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1440 if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) 1440 if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1441 reg |= PHY_GIG_ADV_1000F; 1441 reg |= PHY_GIG_ADV_1000F;
1442 else 1442 else
1443 reg |= PHY_GIG_ADV_1000H; 1443 reg |= PHY_GIG_ADV_1000H;
1444 } 1444 }
1445 1445
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 657242504621..cfe8829ed31f 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -28,13 +28,7 @@
28#include <asm/io.h> 28#include <asm/io.h>
29#include <asm/irq.h> 29#include <asm/irq.h>
30 30
31#ifdef CONFIG_R8169_NAPI 31#define RTL8169_VERSION "2.3LK-NAPI"
32#define NAPI_SUFFIX "-NAPI"
33#else
34#define NAPI_SUFFIX ""
35#endif
36
37#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
38#define MODULENAME "r8169" 32#define MODULENAME "r8169"
39#define PFX MODULENAME ": " 33#define PFX MODULENAME ": "
40 34
@@ -57,16 +51,6 @@
57#define TX_BUFFS_AVAIL(tp) \ 51#define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) 52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59 53
60#ifdef CONFIG_R8169_NAPI
61#define rtl8169_rx_skb netif_receive_skb
62#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
63#define rtl8169_rx_quota(count, quota) min(count, quota)
64#else
65#define rtl8169_rx_skb netif_rx
66#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
67#define rtl8169_rx_quota(count, quota) count
68#endif
69
70/* Maximum events (Rx packets, etc.) to handle at each interrupt. */ 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
71static const int max_interrupt_work = 20; 55static const int max_interrupt_work = 20;
72 56
@@ -394,9 +378,7 @@ struct rtl8169_private {
394 void __iomem *mmio_addr; /* memory map physical address */ 378 void __iomem *mmio_addr; /* memory map physical address */
395 struct pci_dev *pci_dev; /* Index of PCI device */ 379 struct pci_dev *pci_dev; /* Index of PCI device */
396 struct net_device *dev; 380 struct net_device *dev;
397#ifdef CONFIG_R8169_NAPI
398 struct napi_struct napi; 381 struct napi_struct napi;
399#endif
400 spinlock_t lock; /* spin lock flag */ 382 spinlock_t lock; /* spin lock flag */
401 u32 msg_enable; 383 u32 msg_enable;
402 int chipset; 384 int chipset;
@@ -458,10 +440,7 @@ static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
458static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); 440static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
459static void rtl8169_down(struct net_device *dev); 441static void rtl8169_down(struct net_device *dev);
460static void rtl8169_rx_clear(struct rtl8169_private *tp); 442static void rtl8169_rx_clear(struct rtl8169_private *tp);
461
462#ifdef CONFIG_R8169_NAPI
463static int rtl8169_poll(struct napi_struct *napi, int budget); 443static int rtl8169_poll(struct napi_struct *napi, int budget);
464#endif
465 444
466static const unsigned int rtl8169_rx_config = 445static const unsigned int rtl8169_rx_config =
467 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 446 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
@@ -843,10 +822,11 @@ static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
843 struct sk_buff *skb) 822 struct sk_buff *skb)
844{ 823{
845 u32 opts2 = le32_to_cpu(desc->opts2); 824 u32 opts2 = le32_to_cpu(desc->opts2);
825 struct vlan_group *vlgrp = tp->vlgrp;
846 int ret; 826 int ret;
847 827
848 if (tp->vlgrp && (opts2 & RxVlanTag)) { 828 if (vlgrp && (opts2 & RxVlanTag)) {
849 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff)); 829 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
850 ret = 0; 830 ret = 0;
851 } else 831 } else
852 ret = -1; 832 ret = -1;
@@ -1764,9 +1744,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1764 dev->change_mtu = rtl8169_change_mtu; 1744 dev->change_mtu = rtl8169_change_mtu;
1765 dev->set_mac_address = rtl_set_mac_address; 1745 dev->set_mac_address = rtl_set_mac_address;
1766 1746
1767#ifdef CONFIG_R8169_NAPI
1768 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); 1747 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1769#endif
1770 1748
1771#ifdef CONFIG_R8169_VLAN 1749#ifdef CONFIG_R8169_VLAN
1772 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 1750 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
@@ -1887,9 +1865,7 @@ static int rtl8169_open(struct net_device *dev)
1887 if (retval < 0) 1865 if (retval < 0)
1888 goto err_release_ring_2; 1866 goto err_release_ring_2;
1889 1867
1890#ifdef CONFIG_R8169_NAPI
1891 napi_enable(&tp->napi); 1868 napi_enable(&tp->napi);
1892#endif
1893 1869
1894 rtl_hw_start(dev); 1870 rtl_hw_start(dev);
1895 1871
@@ -2197,9 +2173,7 @@ static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2197 if (ret < 0) 2173 if (ret < 0)
2198 goto out; 2174 goto out;
2199 2175
2200#ifdef CONFIG_R8169_NAPI
2201 napi_enable(&tp->napi); 2176 napi_enable(&tp->napi);
2202#endif
2203 2177
2204 rtl_hw_start(dev); 2178 rtl_hw_start(dev);
2205 2179
@@ -2391,17 +2365,13 @@ static void rtl8169_wait_for_quiescence(struct net_device *dev)
2391 synchronize_irq(dev->irq); 2365 synchronize_irq(dev->irq);
2392 2366
2393 /* Wait for any pending NAPI task to complete */ 2367 /* Wait for any pending NAPI task to complete */
2394#ifdef CONFIG_R8169_NAPI
2395 napi_disable(&tp->napi); 2368 napi_disable(&tp->napi);
2396#endif
2397 2369
2398 rtl8169_irq_mask_and_ack(ioaddr); 2370 rtl8169_irq_mask_and_ack(ioaddr);
2399 2371
2400#ifdef CONFIG_R8169_NAPI
2401 tp->intr_mask = 0xffff; 2372 tp->intr_mask = 0xffff;
2402 RTL_W16(IntrMask, tp->intr_event); 2373 RTL_W16(IntrMask, tp->intr_event);
2403 napi_enable(&tp->napi); 2374 napi_enable(&tp->napi);
2404#endif
2405} 2375}
2406 2376
2407static void rtl8169_reinit_task(struct work_struct *work) 2377static void rtl8169_reinit_task(struct work_struct *work)
@@ -2767,7 +2737,7 @@ static int rtl8169_rx_interrupt(struct net_device *dev,
2767 2737
2768 cur_rx = tp->cur_rx; 2738 cur_rx = tp->cur_rx;
2769 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; 2739 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2770 rx_left = rtl8169_rx_quota(rx_left, budget); 2740 rx_left = min(rx_left, budget);
2771 2741
2772 for (; rx_left > 0; rx_left--, cur_rx++) { 2742 for (; rx_left > 0; rx_left--, cur_rx++) {
2773 unsigned int entry = cur_rx % NUM_RX_DESC; 2743 unsigned int entry = cur_rx % NUM_RX_DESC;
@@ -2829,7 +2799,7 @@ static int rtl8169_rx_interrupt(struct net_device *dev,
2829 skb->protocol = eth_type_trans(skb, dev); 2799 skb->protocol = eth_type_trans(skb, dev);
2830 2800
2831 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) 2801 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2832 rtl8169_rx_skb(skb); 2802 netif_receive_skb(skb);
2833 2803
2834 dev->last_rx = jiffies; 2804 dev->last_rx = jiffies;
2835 dev->stats.rx_bytes += pkt_size; 2805 dev->stats.rx_bytes += pkt_size;
@@ -2869,87 +2839,61 @@ static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2869{ 2839{
2870 struct net_device *dev = dev_instance; 2840 struct net_device *dev = dev_instance;
2871 struct rtl8169_private *tp = netdev_priv(dev); 2841 struct rtl8169_private *tp = netdev_priv(dev);
2872 int boguscnt = max_interrupt_work;
2873 void __iomem *ioaddr = tp->mmio_addr; 2842 void __iomem *ioaddr = tp->mmio_addr;
2874 int status;
2875 int handled = 0; 2843 int handled = 0;
2844 int status;
2876 2845
2877 do { 2846 status = RTL_R16(IntrStatus);
2878 status = RTL_R16(IntrStatus);
2879 2847
2880 /* hotplug/major error/no more work/shared irq */ 2848 /* hotplug/major error/no more work/shared irq */
2881 if ((status == 0xFFFF) || !status) 2849 if ((status == 0xffff) || !status)
2882 break; 2850 goto out;
2883 2851
2884 handled = 1; 2852 handled = 1;
2885 2853
2886 if (unlikely(!netif_running(dev))) { 2854 if (unlikely(!netif_running(dev))) {
2887 rtl8169_asic_down(ioaddr); 2855 rtl8169_asic_down(ioaddr);
2888 goto out; 2856 goto out;
2889 } 2857 }
2890 2858
2891 status &= tp->intr_mask; 2859 status &= tp->intr_mask;
2892 RTL_W16(IntrStatus, 2860 RTL_W16(IntrStatus,
2893 (status & RxFIFOOver) ? (status | RxOverflow) : status); 2861 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2894 2862
2895 if (!(status & tp->intr_event)) 2863 if (!(status & tp->intr_event))
2896 break; 2864 goto out;
2897 2865
2898 /* Work around for rx fifo overflow */ 2866 /* Work around for rx fifo overflow */
2899 if (unlikely(status & RxFIFOOver) && 2867 if (unlikely(status & RxFIFOOver) &&
2900 (tp->mac_version == RTL_GIGA_MAC_VER_11)) { 2868 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2901 netif_stop_queue(dev); 2869 netif_stop_queue(dev);
2902 rtl8169_tx_timeout(dev); 2870 rtl8169_tx_timeout(dev);
2903 break; 2871 goto out;
2904 } 2872 }
2905 2873
2906 if (unlikely(status & SYSErr)) { 2874 if (unlikely(status & SYSErr)) {
2907 rtl8169_pcierr_interrupt(dev); 2875 rtl8169_pcierr_interrupt(dev);
2908 break; 2876 goto out;
2909 } 2877 }
2910 2878
2911 if (status & LinkChg) 2879 if (status & LinkChg)
2912 rtl8169_check_link_status(dev, tp, ioaddr); 2880 rtl8169_check_link_status(dev, tp, ioaddr);
2913 2881
2914#ifdef CONFIG_R8169_NAPI 2882 if (status & tp->napi_event) {
2915 if (status & tp->napi_event) { 2883 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2916 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); 2884 tp->intr_mask = ~tp->napi_event;
2917 tp->intr_mask = ~tp->napi_event;
2918 2885
2919 if (likely(netif_rx_schedule_prep(dev, &tp->napi))) 2886 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2920 __netif_rx_schedule(dev, &tp->napi); 2887 __netif_rx_schedule(dev, &tp->napi);
2921 else if (netif_msg_intr(tp)) { 2888 else if (netif_msg_intr(tp)) {
2922 printk(KERN_INFO "%s: interrupt %04x in poll\n", 2889 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2923 dev->name, status); 2890 dev->name, status);
2924 }
2925 } 2891 }
2926 break;
2927#else
2928 /* Rx interrupt */
2929 if (status & (RxOK | RxOverflow | RxFIFOOver))
2930 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
2931
2932 /* Tx interrupt */
2933 if (status & (TxOK | TxErr))
2934 rtl8169_tx_interrupt(dev, tp, ioaddr);
2935#endif
2936
2937 boguscnt--;
2938 } while (boguscnt > 0);
2939
2940 if (boguscnt <= 0) {
2941 if (netif_msg_intr(tp) && net_ratelimit() ) {
2942 printk(KERN_WARNING
2943 "%s: Too much work at interrupt!\n", dev->name);
2944 }
2945 /* Clear all interrupt sources. */
2946 RTL_W16(IntrStatus, 0xffff);
2947 } 2892 }
2948out: 2893out:
2949 return IRQ_RETVAL(handled); 2894 return IRQ_RETVAL(handled);
2950} 2895}
2951 2896
2952#ifdef CONFIG_R8169_NAPI
2953static int rtl8169_poll(struct napi_struct *napi, int budget) 2897static int rtl8169_poll(struct napi_struct *napi, int budget)
2954{ 2898{
2955 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 2899 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
@@ -2975,7 +2919,6 @@ static int rtl8169_poll(struct napi_struct *napi, int budget)
2975 2919
2976 return work_done; 2920 return work_done;
2977} 2921}
2978#endif
2979 2922
2980static void rtl8169_down(struct net_device *dev) 2923static void rtl8169_down(struct net_device *dev)
2981{ 2924{
@@ -2987,9 +2930,7 @@ static void rtl8169_down(struct net_device *dev)
2987 2930
2988 netif_stop_queue(dev); 2931 netif_stop_queue(dev);
2989 2932
2990#ifdef CONFIG_R8169_NAPI
2991 napi_disable(&tp->napi); 2933 napi_disable(&tp->napi);
2992#endif
2993 2934
2994core_down: 2935core_down:
2995 spin_lock_irq(&tp->lock); 2936 spin_lock_irq(&tp->lock);
@@ -3098,8 +3039,10 @@ static void rtl_set_rx_mode(struct net_device *dev)
3098 (tp->mac_version == RTL_GIGA_MAC_VER_15) || 3039 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
3099 (tp->mac_version == RTL_GIGA_MAC_VER_16) || 3040 (tp->mac_version == RTL_GIGA_MAC_VER_16) ||
3100 (tp->mac_version == RTL_GIGA_MAC_VER_17)) { 3041 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
3101 mc_filter[0] = 0xffffffff; 3042 u32 data = mc_filter[0];
3102 mc_filter[1] = 0xffffffff; 3043
3044 mc_filter[0] = swab32(mc_filter[1]);
3045 mc_filter[1] = swab32(data);
3103 } 3046 }
3104 3047
3105 RTL_W32(MAR0 + 0, mc_filter[0]); 3048 RTL_W32(MAR0 + 0, mc_filter[0]);
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index ae7b697456b4..9dae40ccf048 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -86,7 +86,7 @@
86#include "s2io.h" 86#include "s2io.h"
87#include "s2io-regs.h" 87#include "s2io-regs.h"
88 88
89#define DRV_VERSION "2.0.26.24" 89#define DRV_VERSION "2.0.26.25"
90 90
91/* S2io Driver name & version. */ 91/* S2io Driver name & version. */
92static char s2io_driver_name[] = "Neterion"; 92static char s2io_driver_name[] = "Neterion";
@@ -545,91 +545,63 @@ static struct pci_driver s2io_driver = {
545/* netqueue manipulation helper functions */ 545/* netqueue manipulation helper functions */
546static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp) 546static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
547{ 547{
548 int i; 548 if (!sp->config.multiq) {
549#ifdef CONFIG_NETDEVICES_MULTIQUEUE 549 int i;
550 if (sp->config.multiq) { 550
551 for (i = 0; i < sp->config.tx_fifo_num; i++)
552 netif_stop_subqueue(sp->dev, i);
553 } else
554#endif
555 {
556 for (i = 0; i < sp->config.tx_fifo_num; i++) 551 for (i = 0; i < sp->config.tx_fifo_num; i++)
557 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP; 552 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
558 netif_stop_queue(sp->dev);
559 } 553 }
554 netif_tx_stop_all_queues(sp->dev);
560} 555}
561 556
562static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no) 557static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
563{ 558{
564#ifdef CONFIG_NETDEVICES_MULTIQUEUE 559 if (!sp->config.multiq)
565 if (sp->config.multiq)
566 netif_stop_subqueue(sp->dev, fifo_no);
567 else
568#endif
569 {
570 sp->mac_control.fifos[fifo_no].queue_state = 560 sp->mac_control.fifos[fifo_no].queue_state =
571 FIFO_QUEUE_STOP; 561 FIFO_QUEUE_STOP;
572 netif_stop_queue(sp->dev); 562
573 } 563 netif_tx_stop_all_queues(sp->dev);
574} 564}
575 565
576static inline void s2io_start_all_tx_queue(struct s2io_nic *sp) 566static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
577{ 567{
578 int i; 568 if (!sp->config.multiq) {
579#ifdef CONFIG_NETDEVICES_MULTIQUEUE 569 int i;
580 if (sp->config.multiq) { 570
581 for (i = 0; i < sp->config.tx_fifo_num; i++)
582 netif_start_subqueue(sp->dev, i);
583 } else
584#endif
585 {
586 for (i = 0; i < sp->config.tx_fifo_num; i++) 571 for (i = 0; i < sp->config.tx_fifo_num; i++)
587 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START; 572 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
588 netif_start_queue(sp->dev);
589 } 573 }
574 netif_tx_start_all_queues(sp->dev);
590} 575}
591 576
592static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no) 577static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
593{ 578{
594#ifdef CONFIG_NETDEVICES_MULTIQUEUE 579 if (!sp->config.multiq)
595 if (sp->config.multiq)
596 netif_start_subqueue(sp->dev, fifo_no);
597 else
598#endif
599 {
600 sp->mac_control.fifos[fifo_no].queue_state = 580 sp->mac_control.fifos[fifo_no].queue_state =
601 FIFO_QUEUE_START; 581 FIFO_QUEUE_START;
602 netif_start_queue(sp->dev); 582
603 } 583 netif_tx_start_all_queues(sp->dev);
604} 584}
605 585
606static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp) 586static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
607{ 587{
608 int i; 588 if (!sp->config.multiq) {
609#ifdef CONFIG_NETDEVICES_MULTIQUEUE 589 int i;
610 if (sp->config.multiq) { 590
611 for (i = 0; i < sp->config.tx_fifo_num; i++)
612 netif_wake_subqueue(sp->dev, i);
613 } else
614#endif
615 {
616 for (i = 0; i < sp->config.tx_fifo_num; i++) 591 for (i = 0; i < sp->config.tx_fifo_num; i++)
617 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START; 592 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
618 netif_wake_queue(sp->dev);
619 } 593 }
594 netif_tx_wake_all_queues(sp->dev);
620} 595}
621 596
622static inline void s2io_wake_tx_queue( 597static inline void s2io_wake_tx_queue(
623 struct fifo_info *fifo, int cnt, u8 multiq) 598 struct fifo_info *fifo, int cnt, u8 multiq)
624{ 599{
625 600
626#ifdef CONFIG_NETDEVICES_MULTIQUEUE
627 if (multiq) { 601 if (multiq) {
628 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no)) 602 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
629 netif_wake_subqueue(fifo->dev, fifo->fifo_no); 603 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
630 } else 604 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
631#endif
632 if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
633 if (netif_queue_stopped(fifo->dev)) { 605 if (netif_queue_stopped(fifo->dev)) {
634 fifo->queue_state = FIFO_QUEUE_START; 606 fifo->queue_state = FIFO_QUEUE_START;
635 netif_wake_queue(fifo->dev); 607 netif_wake_queue(fifo->dev);
@@ -1909,8 +1881,6 @@ static int init_nic(struct s2io_nic *nic)
1909 1881
1910static int s2io_link_fault_indication(struct s2io_nic *nic) 1882static int s2io_link_fault_indication(struct s2io_nic *nic)
1911{ 1883{
1912 if (nic->config.intr_type != INTA)
1913 return MAC_RMAC_ERR_TIMER;
1914 if (nic->device_type == XFRAME_II_DEVICE) 1884 if (nic->device_type == XFRAME_II_DEVICE)
1915 return LINK_UP_DOWN_INTERRUPT; 1885 return LINK_UP_DOWN_INTERRUPT;
1916 else 1886 else
@@ -1943,7 +1913,9 @@ static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1943{ 1913{
1944 struct XENA_dev_config __iomem *bar0 = nic->bar0; 1914 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1945 register u64 gen_int_mask = 0; 1915 register u64 gen_int_mask = 0;
1916 u64 interruptible;
1946 1917
1918 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1947 if (mask & TX_DMA_INTR) { 1919 if (mask & TX_DMA_INTR) {
1948 1920
1949 gen_int_mask |= TXDMA_INT_M; 1921 gen_int_mask |= TXDMA_INT_M;
@@ -2033,10 +2005,12 @@ static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
2033 gen_int_mask |= RXMAC_INT_M; 2005 gen_int_mask |= RXMAC_INT_M;
2034 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag, 2006 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2035 &bar0->mac_int_mask); 2007 &bar0->mac_int_mask);
2036 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR | 2008 interruptible = RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2037 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR | 2009 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2038 RMAC_DOUBLE_ECC_ERR | 2010 RMAC_DOUBLE_ECC_ERR;
2039 RMAC_LINK_STATE_CHANGE_INT, 2011 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2012 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2013 do_s2io_write_bits(interruptible,
2040 flag, &bar0->mac_rmac_err_mask); 2014 flag, &bar0->mac_rmac_err_mask);
2041 } 2015 }
2042 2016
@@ -2519,6 +2493,9 @@ static void stop_nic(struct s2io_nic *nic)
2519/** 2493/**
2520 * fill_rx_buffers - Allocates the Rx side skbs 2494 * fill_rx_buffers - Allocates the Rx side skbs
2521 * @ring_info: per ring structure 2495 * @ring_info: per ring structure
2496 * @from_card_up: If this is true, we will map the buffer to get
2497 * the dma address for buf0 and buf1 to give it to the card.
2498 * Else we will sync the already mapped buffer to give it to the card.
2522 * Description: 2499 * Description:
2523 * The function allocates Rx side skbs and puts the physical 2500 * The function allocates Rx side skbs and puts the physical
2524 * address of these buffers into the RxD buffer pointers, so that the NIC 2501 * address of these buffers into the RxD buffer pointers, so that the NIC
@@ -2536,7 +2513,7 @@ static void stop_nic(struct s2io_nic *nic)
2536 * SUCCESS on success or an appropriate -ve value on failure. 2513 * SUCCESS on success or an appropriate -ve value on failure.
2537 */ 2514 */
2538 2515
2539static int fill_rx_buffers(struct ring_info *ring) 2516static int fill_rx_buffers(struct ring_info *ring, int from_card_up)
2540{ 2517{
2541 struct sk_buff *skb; 2518 struct sk_buff *skb;
2542 struct RxD_t *rxdp; 2519 struct RxD_t *rxdp;
@@ -2566,7 +2543,7 @@ static int fill_rx_buffers(struct ring_info *ring)
2566 if (block_no) 2543 if (block_no)
2567 rxd_index += (block_no * ring->rxd_count); 2544 rxd_index += (block_no * ring->rxd_count);
2568 2545
2569 if ((block_no == block_no1) && 2546 if ((block_no == block_no1) &&
2570 (off == ring->rx_curr_get_info.offset) && 2547 (off == ring->rx_curr_get_info.offset) &&
2571 (rxdp->Host_Control)) { 2548 (rxdp->Host_Control)) {
2572 DBG_PRINT(INTR_DBG, "%s: Get and Put", 2549 DBG_PRINT(INTR_DBG, "%s: Get and Put",
@@ -2612,7 +2589,7 @@ static int fill_rx_buffers(struct ring_info *ring)
2612 first_rxdp->Control_1 |= RXD_OWN_XENA; 2589 first_rxdp->Control_1 |= RXD_OWN_XENA;
2613 } 2590 }
2614 stats->mem_alloc_fail_cnt++; 2591 stats->mem_alloc_fail_cnt++;
2615 2592
2616 return -ENOMEM ; 2593 return -ENOMEM ;
2617 } 2594 }
2618 stats->mem_allocated += skb->truesize; 2595 stats->mem_allocated += skb->truesize;
@@ -2655,17 +2632,16 @@ static int fill_rx_buffers(struct ring_info *ring)
2655 skb->data = (void *) (unsigned long)tmp; 2632 skb->data = (void *) (unsigned long)tmp;
2656 skb_reset_tail_pointer(skb); 2633 skb_reset_tail_pointer(skb);
2657 2634
2658 /* AK: check is wrong. 0 can be valid dma address */ 2635 if (from_card_up) {
2659 if (!(rxdp3->Buffer0_ptr))
2660 rxdp3->Buffer0_ptr = 2636 rxdp3->Buffer0_ptr =
2661 pci_map_single(ring->pdev, ba->ba_0, 2637 pci_map_single(ring->pdev, ba->ba_0,
2662 BUF0_LEN, PCI_DMA_FROMDEVICE); 2638 BUF0_LEN, PCI_DMA_FROMDEVICE);
2663 else 2639 if (pci_dma_mapping_error(rxdp3->Buffer0_ptr))
2640 goto pci_map_failed;
2641 } else
2664 pci_dma_sync_single_for_device(ring->pdev, 2642 pci_dma_sync_single_for_device(ring->pdev,
2665 (dma_addr_t) rxdp3->Buffer0_ptr, 2643 (dma_addr_t) rxdp3->Buffer0_ptr,
2666 BUF0_LEN, PCI_DMA_FROMDEVICE); 2644 BUF0_LEN, PCI_DMA_FROMDEVICE);
2667 if (pci_dma_mapping_error(rxdp3->Buffer0_ptr))
2668 goto pci_map_failed;
2669 2645
2670 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN); 2646 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2671 if (ring->rxd_mode == RXD_MODE_3B) { 2647 if (ring->rxd_mode == RXD_MODE_3B) {
@@ -2682,21 +2658,22 @@ static int fill_rx_buffers(struct ring_info *ring)
2682 if (pci_dma_mapping_error(rxdp3->Buffer2_ptr)) 2658 if (pci_dma_mapping_error(rxdp3->Buffer2_ptr))
2683 goto pci_map_failed; 2659 goto pci_map_failed;
2684 2660
2685 /* AK: check is wrong */ 2661 if (from_card_up) {
2686 if (!rxdp3->Buffer1_ptr)
2687 rxdp3->Buffer1_ptr = 2662 rxdp3->Buffer1_ptr =
2688 pci_map_single(ring->pdev, 2663 pci_map_single(ring->pdev,
2689 ba->ba_1, BUF1_LEN, 2664 ba->ba_1, BUF1_LEN,
2690 PCI_DMA_FROMDEVICE); 2665 PCI_DMA_FROMDEVICE);
2691 2666
2692 if (pci_dma_mapping_error(rxdp3->Buffer1_ptr)) { 2667 if (pci_dma_mapping_error
2693 pci_unmap_single 2668 (rxdp3->Buffer1_ptr)) {
2694 (ring->pdev, 2669 pci_unmap_single
2695 (dma_addr_t)(unsigned long) 2670 (ring->pdev,
2696 skb->data, 2671 (dma_addr_t)(unsigned long)
2697 ring->mtu + 4, 2672 skb->data,
2698 PCI_DMA_FROMDEVICE); 2673 ring->mtu + 4,
2699 goto pci_map_failed; 2674 PCI_DMA_FROMDEVICE);
2675 goto pci_map_failed;
2676 }
2700 } 2677 }
2701 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1); 2678 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2702 rxdp->Control_2 |= SET_BUFFER2_SIZE_3 2679 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
@@ -2831,7 +2808,7 @@ static void free_rx_buffers(struct s2io_nic *sp)
2831 2808
2832static int s2io_chk_rx_buffers(struct ring_info *ring) 2809static int s2io_chk_rx_buffers(struct ring_info *ring)
2833{ 2810{
2834 if (fill_rx_buffers(ring) == -ENOMEM) { 2811 if (fill_rx_buffers(ring, 0) == -ENOMEM) {
2835 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name); 2812 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2836 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n"); 2813 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2837 } 2814 }
@@ -2962,7 +2939,7 @@ static void s2io_netpoll(struct net_device *dev)
2962 rx_intr_handler(&mac_control->rings[i], 0); 2939 rx_intr_handler(&mac_control->rings[i], 0);
2963 2940
2964 for (i = 0; i < config->rx_ring_num; i++) { 2941 for (i = 0; i < config->rx_ring_num; i++) {
2965 if (fill_rx_buffers(&mac_control->rings[i]) == -ENOMEM) { 2942 if (fill_rx_buffers(&mac_control->rings[i], 0) == -ENOMEM) {
2966 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name); 2943 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2967 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n"); 2944 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2968 break; 2945 break;
@@ -4189,15 +4166,12 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4189 return NETDEV_TX_LOCKED; 4166 return NETDEV_TX_LOCKED;
4190 } 4167 }
4191 4168
4192#ifdef CONFIG_NETDEVICES_MULTIQUEUE
4193 if (sp->config.multiq) { 4169 if (sp->config.multiq) {
4194 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) { 4170 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4195 spin_unlock_irqrestore(&fifo->tx_lock, flags); 4171 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4196 return NETDEV_TX_BUSY; 4172 return NETDEV_TX_BUSY;
4197 } 4173 }
4198 } else 4174 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4199#endif
4200 if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4201 if (netif_queue_stopped(dev)) { 4175 if (netif_queue_stopped(dev)) {
4202 spin_unlock_irqrestore(&fifo->tx_lock, flags); 4176 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4203 return NETDEV_TX_BUSY; 4177 return NETDEV_TX_BUSY;
@@ -4394,18 +4368,24 @@ static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4394 /* Nothing much can be done. Get out */ 4368 /* Nothing much can be done. Get out */
4395 return IRQ_HANDLED; 4369 return IRQ_HANDLED;
4396 4370
4397 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); 4371 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4372 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4398 4373
4399 if (reason & GEN_INTR_TXTRAFFIC) 4374 if (reason & GEN_INTR_TXPIC)
4400 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); 4375 s2io_txpic_intr_handle(sp);
4401 4376
4402 for (i = 0; i < config->tx_fifo_num; i++) 4377 if (reason & GEN_INTR_TXTRAFFIC)
4403 tx_intr_handler(&fifos[i]); 4378 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4404 4379
4405 writeq(sp->general_int_mask, &bar0->general_int_mask); 4380 for (i = 0; i < config->tx_fifo_num; i++)
4406 readl(&bar0->general_int_status); 4381 tx_intr_handler(&fifos[i]);
4407 4382
4408 return IRQ_HANDLED; 4383 writeq(sp->general_int_mask, &bar0->general_int_mask);
4384 readl(&bar0->general_int_status);
4385 return IRQ_HANDLED;
4386 }
4387 /* The interrupt was not raised by us */
4388 return IRQ_NONE;
4409} 4389}
4410 4390
4411static void s2io_txpic_intr_handle(struct s2io_nic *sp) 4391static void s2io_txpic_intr_handle(struct s2io_nic *sp)
@@ -6988,7 +6968,7 @@ static int rxd_owner_bit_reset(struct s2io_nic *sp)
6988 &skb,(u64 *)&temp0_64, 6968 &skb,(u64 *)&temp0_64,
6989 (u64 *)&temp1_64, 6969 (u64 *)&temp1_64,
6990 (u64 *)&temp2_64, 6970 (u64 *)&temp2_64,
6991 size) == ENOMEM) { 6971 size) == -ENOMEM) {
6992 return 0; 6972 return 0;
6993 } 6973 }
6994 6974
@@ -7133,6 +7113,9 @@ static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
7133 7113
7134 s2io_rem_isr(sp); 7114 s2io_rem_isr(sp);
7135 7115
7116 /* stop the tx queue, indicate link down */
7117 s2io_link(sp, LINK_DOWN);
7118
7136 /* Check if the device is Quiescent and then Reset the NIC */ 7119 /* Check if the device is Quiescent and then Reset the NIC */
7137 while(do_io) { 7120 while(do_io) {
7138 /* As per the HW requirement we need to replenish the 7121 /* As per the HW requirement we need to replenish the
@@ -7204,7 +7187,7 @@ static int s2io_card_up(struct s2io_nic * sp)
7204 7187
7205 for (i = 0; i < config->rx_ring_num; i++) { 7188 for (i = 0; i < config->rx_ring_num; i++) {
7206 mac_control->rings[i].mtu = dev->mtu; 7189 mac_control->rings[i].mtu = dev->mtu;
7207 ret = fill_rx_buffers(&mac_control->rings[i]); 7190 ret = fill_rx_buffers(&mac_control->rings[i], 1);
7208 if (ret) { 7191 if (ret) {
7209 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n", 7192 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7210 dev->name); 7193 dev->name);
@@ -7265,17 +7248,19 @@ static int s2io_card_up(struct s2io_nic * sp)
7265 7248
7266 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2)); 7249 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7267 7250
7251 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7252
7268 /* Enable select interrupts */ 7253 /* Enable select interrupts */
7269 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS); 7254 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7270 if (sp->config.intr_type != INTA) 7255 if (sp->config.intr_type != INTA) {
7271 en_dis_able_nic_intrs(sp, TX_TRAFFIC_INTR, ENABLE_INTRS); 7256 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7272 else { 7257 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7258 } else {
7273 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR; 7259 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7274 interruptible |= TX_PIC_INTR; 7260 interruptible |= TX_PIC_INTR;
7275 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS); 7261 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7276 } 7262 }
7277 7263
7278 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7279 return 0; 7264 return 0;
7280} 7265}
7281 7266
@@ -7633,12 +7618,6 @@ static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7633 DBG_PRINT(ERR_DBG, "tx fifos\n"); 7618 DBG_PRINT(ERR_DBG, "tx fifos\n");
7634 } 7619 }
7635 7620
7636#ifndef CONFIG_NETDEVICES_MULTIQUEUE
7637 if (multiq) {
7638 DBG_PRINT(ERR_DBG, "s2io: Multiqueue support not enabled\n");
7639 multiq = 0;
7640 }
7641#endif
7642 if (multiq) 7621 if (multiq)
7643 *dev_multiq = multiq; 7622 *dev_multiq = multiq;
7644 7623
@@ -7783,12 +7762,10 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7783 pci_disable_device(pdev); 7762 pci_disable_device(pdev);
7784 return -ENODEV; 7763 return -ENODEV;
7785 } 7764 }
7786#ifdef CONFIG_NETDEVICES_MULTIQUEUE
7787 if (dev_multiq) 7765 if (dev_multiq)
7788 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num); 7766 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7789 else 7767 else
7790#endif 7768 dev = alloc_etherdev(sizeof(struct s2io_nic));
7791 dev = alloc_etherdev(sizeof(struct s2io_nic));
7792 if (dev == NULL) { 7769 if (dev == NULL) {
7793 DBG_PRINT(ERR_DBG, "Device allocation failed\n"); 7770 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7794 pci_disable_device(pdev); 7771 pci_disable_device(pdev);
@@ -7979,10 +7956,6 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7979 dev->features |= NETIF_F_UFO; 7956 dev->features |= NETIF_F_UFO;
7980 dev->features |= NETIF_F_HW_CSUM; 7957 dev->features |= NETIF_F_HW_CSUM;
7981 } 7958 }
7982#ifdef CONFIG_NETDEVICES_MULTIQUEUE
7983 if (config->multiq)
7984 dev->features |= NETIF_F_MULTI_QUEUE;
7985#endif
7986 dev->tx_timeout = &s2io_tx_watchdog; 7959 dev->tx_timeout = &s2io_tx_watchdog;
7987 dev->watchdog_timeo = WATCH_DOG_TIMEOUT; 7960 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7988 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic); 7961 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
@@ -8708,5 +8681,5 @@ static void s2io_io_resume(struct pci_dev *pdev)
8708 } 8681 }
8709 8682
8710 netif_device_attach(netdev); 8683 netif_device_attach(netdev);
8711 netif_wake_queue(netdev); 8684 netif_tx_wake_all_queues(netdev);
8712} 8685}
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index 1827b6686c98..6722a2f7d091 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -748,7 +748,7 @@ struct ring_info {
748 748
749 /* interface MTU value */ 749 /* interface MTU value */
750 unsigned mtu; 750 unsigned mtu;
751 751
752 /* Buffer Address store. */ 752 /* Buffer Address store. */
753 struct buffAdd **ba; 753 struct buffAdd **ba;
754 754
@@ -1107,6 +1107,7 @@ static int init_shared_mem(struct s2io_nic *sp);
1107static void free_shared_mem(struct s2io_nic *sp); 1107static void free_shared_mem(struct s2io_nic *sp);
1108static int init_nic(struct s2io_nic *nic); 1108static int init_nic(struct s2io_nic *nic);
1109static int rx_intr_handler(struct ring_info *ring_data, int budget); 1109static int rx_intr_handler(struct ring_info *ring_data, int budget);
1110static void s2io_txpic_intr_handle(struct s2io_nic *sp);
1110static void tx_intr_handler(struct fifo_info *fifo_data); 1111static void tx_intr_handler(struct fifo_info *fifo_data);
1111static void s2io_handle_errors(void * dev_id); 1112static void s2io_handle_errors(void * dev_id);
1112 1113
diff --git a/drivers/net/saa9730.c b/drivers/net/saa9730.c
deleted file mode 100644
index c65199df8a7f..000000000000
--- a/drivers/net/saa9730.c
+++ /dev/null
@@ -1,1139 +0,0 @@
1/*
2 * Copyright (C) 2000, 2005 MIPS Technologies, Inc. All rights reserved.
3 * Authors: Carsten Langgaard <carstenl@mips.com>
4 * Maciej W. Rozycki <macro@mips.com>
5 * Copyright (C) 2004 Ralf Baechle <ralf@linux-mips.org>
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * SAA9730 ethernet driver.
21 *
22 * Changes:
23 * Angelo Dell'Aera <buffer@antifork.org> : Conversion to the new PCI API
24 * (pci_driver).
25 * Conversion to spinlocks.
26 * Error handling fixes.
27 */
28
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/delay.h>
32#include <linux/etherdevice.h>
33#include <linux/module.h>
34#include <linux/skbuff.h>
35#include <linux/pci.h>
36#include <linux/spinlock.h>
37#include <linux/types.h>
38
39#include <asm/addrspace.h>
40#include <asm/io.h>
41
42#include <asm/mips-boards/prom.h>
43
44#include "saa9730.h"
45
46#ifdef LAN_SAA9730_DEBUG
47int lan_saa9730_debug = LAN_SAA9730_DEBUG;
48#else
49int lan_saa9730_debug;
50#endif
51
52#define DRV_MODULE_NAME "saa9730"
53
54static struct pci_device_id saa9730_pci_tbl[] = {
55 { PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730,
56 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
57 { 0, }
58};
59
60MODULE_DEVICE_TABLE(pci, saa9730_pci_tbl);
61
62/* Non-zero only if the current card is a PCI with BIOS-set IRQ. */
63static unsigned int pci_irq_line;
64
65static void evm_saa9730_enable_lan_int(struct lan_saa9730_private *lp)
66{
67 writel(readl(&lp->evm_saa9730_regs->InterruptBlock1) | EVM_LAN_INT,
68 &lp->evm_saa9730_regs->InterruptBlock1);
69 writel(readl(&lp->evm_saa9730_regs->InterruptStatus1) | EVM_LAN_INT,
70 &lp->evm_saa9730_regs->InterruptStatus1);
71 writel(readl(&lp->evm_saa9730_regs->InterruptEnable1) | EVM_LAN_INT |
72 EVM_MASTER_EN, &lp->evm_saa9730_regs->InterruptEnable1);
73}
74
75static void evm_saa9730_disable_lan_int(struct lan_saa9730_private *lp)
76{
77 writel(readl(&lp->evm_saa9730_regs->InterruptBlock1) & ~EVM_LAN_INT,
78 &lp->evm_saa9730_regs->InterruptBlock1);
79 writel(readl(&lp->evm_saa9730_regs->InterruptEnable1) & ~EVM_LAN_INT,
80 &lp->evm_saa9730_regs->InterruptEnable1);
81}
82
83static void evm_saa9730_clear_lan_int(struct lan_saa9730_private *lp)
84{
85 writel(EVM_LAN_INT, &lp->evm_saa9730_regs->InterruptStatus1);
86}
87
88static void evm_saa9730_block_lan_int(struct lan_saa9730_private *lp)
89{
90 writel(readl(&lp->evm_saa9730_regs->InterruptBlock1) & ~EVM_LAN_INT,
91 &lp->evm_saa9730_regs->InterruptBlock1);
92}
93
94static void evm_saa9730_unblock_lan_int(struct lan_saa9730_private *lp)
95{
96 writel(readl(&lp->evm_saa9730_regs->InterruptBlock1) | EVM_LAN_INT,
97 &lp->evm_saa9730_regs->InterruptBlock1);
98}
99
100static void __used show_saa9730_regs(struct net_device *dev)
101{
102 struct lan_saa9730_private *lp = netdev_priv(dev);
103 int i, j;
104
105 printk("TxmBufferA = %p\n", lp->TxmBuffer[0][0]);
106 printk("TxmBufferB = %p\n", lp->TxmBuffer[1][0]);
107 printk("RcvBufferA = %p\n", lp->RcvBuffer[0][0]);
108 printk("RcvBufferB = %p\n", lp->RcvBuffer[1][0]);
109
110 for (i = 0; i < LAN_SAA9730_BUFFERS; i++) {
111 for (j = 0; j < LAN_SAA9730_TXM_Q_SIZE; j++) {
112 printk("TxmBuffer[%d][%d] = %x\n", i, j,
113 le32_to_cpu(*(unsigned int *)
114 lp->TxmBuffer[i][j]));
115 }
116 }
117 for (i = 0; i < LAN_SAA9730_BUFFERS; i++) {
118 for (j = 0; j < LAN_SAA9730_RCV_Q_SIZE; j++) {
119 printk("RcvBuffer[%d][%d] = %x\n", i, j,
120 le32_to_cpu(*(unsigned int *)
121 lp->RcvBuffer[i][j]));
122 }
123 }
124 printk("lp->evm_saa9730_regs->InterruptBlock1 = %x\n",
125 readl(&lp->evm_saa9730_regs->InterruptBlock1));
126 printk("lp->evm_saa9730_regs->InterruptStatus1 = %x\n",
127 readl(&lp->evm_saa9730_regs->InterruptStatus1));
128 printk("lp->evm_saa9730_regs->InterruptEnable1 = %x\n",
129 readl(&lp->evm_saa9730_regs->InterruptEnable1));
130 printk("lp->lan_saa9730_regs->Ok2Use = %x\n",
131 readl(&lp->lan_saa9730_regs->Ok2Use));
132 printk("lp->NextTxmBufferIndex = %x\n", lp->NextTxmBufferIndex);
133 printk("lp->NextTxmPacketIndex = %x\n", lp->NextTxmPacketIndex);
134 printk("lp->PendingTxmBufferIndex = %x\n",
135 lp->PendingTxmBufferIndex);
136 printk("lp->PendingTxmPacketIndex = %x\n",
137 lp->PendingTxmPacketIndex);
138 printk("lp->lan_saa9730_regs->LanDmaCtl = %x\n",
139 readl(&lp->lan_saa9730_regs->LanDmaCtl));
140 printk("lp->lan_saa9730_regs->DmaStatus = %x\n",
141 readl(&lp->lan_saa9730_regs->DmaStatus));
142 printk("lp->lan_saa9730_regs->CamCtl = %x\n",
143 readl(&lp->lan_saa9730_regs->CamCtl));
144 printk("lp->lan_saa9730_regs->TxCtl = %x\n",
145 readl(&lp->lan_saa9730_regs->TxCtl));
146 printk("lp->lan_saa9730_regs->TxStatus = %x\n",
147 readl(&lp->lan_saa9730_regs->TxStatus));
148 printk("lp->lan_saa9730_regs->RxCtl = %x\n",
149 readl(&lp->lan_saa9730_regs->RxCtl));
150 printk("lp->lan_saa9730_regs->RxStatus = %x\n",
151 readl(&lp->lan_saa9730_regs->RxStatus));
152
153 for (i = 0; i < LAN_SAA9730_CAM_DWORDS; i++) {
154 writel(i, &lp->lan_saa9730_regs->CamAddress);
155 printk("lp->lan_saa9730_regs->CamData = %x\n",
156 readl(&lp->lan_saa9730_regs->CamData));
157 }
158
159 printk("dev->stats.tx_packets = %lx\n", dev->stats.tx_packets);
160 printk("dev->stats.tx_errors = %lx\n", dev->stats.tx_errors);
161 printk("dev->stats.tx_aborted_errors = %lx\n",
162 dev->stats.tx_aborted_errors);
163 printk("dev->stats.tx_window_errors = %lx\n",
164 dev->stats.tx_window_errors);
165 printk("dev->stats.tx_carrier_errors = %lx\n",
166 dev->stats.tx_carrier_errors);
167 printk("dev->stats.tx_fifo_errors = %lx\n",
168 dev->stats.tx_fifo_errors);
169 printk("dev->stats.tx_heartbeat_errors = %lx\n",
170 dev->stats.tx_heartbeat_errors);
171 printk("dev->stats.collisions = %lx\n", dev->stats.collisions);
172
173 printk("dev->stats.rx_packets = %lx\n", dev->stats.rx_packets);
174 printk("dev->stats.rx_errors = %lx\n", dev->stats.rx_errors);
175 printk("dev->stats.rx_dropped = %lx\n", dev->stats.rx_dropped);
176 printk("dev->stats.rx_crc_errors = %lx\n", dev->stats.rx_crc_errors);
177 printk("dev->stats.rx_frame_errors = %lx\n",
178 dev->stats.rx_frame_errors);
179 printk("dev->stats.rx_fifo_errors = %lx\n",
180 dev->stats.rx_fifo_errors);
181 printk("dev->stats.rx_length_errors = %lx\n",
182 dev->stats.rx_length_errors);
183
184 printk("lp->lan_saa9730_regs->DebugPCIMasterAddr = %x\n",
185 readl(&lp->lan_saa9730_regs->DebugPCIMasterAddr));
186 printk("lp->lan_saa9730_regs->DebugLanTxStateMachine = %x\n",
187 readl(&lp->lan_saa9730_regs->DebugLanTxStateMachine));
188 printk("lp->lan_saa9730_regs->DebugLanRxStateMachine = %x\n",
189 readl(&lp->lan_saa9730_regs->DebugLanRxStateMachine));
190 printk("lp->lan_saa9730_regs->DebugLanTxFifoPointers = %x\n",
191 readl(&lp->lan_saa9730_regs->DebugLanTxFifoPointers));
192 printk("lp->lan_saa9730_regs->DebugLanRxFifoPointers = %x\n",
193 readl(&lp->lan_saa9730_regs->DebugLanRxFifoPointers));
194 printk("lp->lan_saa9730_regs->DebugLanCtlStateMachine = %x\n",
195 readl(&lp->lan_saa9730_regs->DebugLanCtlStateMachine));
196}
197
198static void lan_saa9730_buffer_init(struct lan_saa9730_private *lp)
199{
200 int i, j;
201
202 /* Init RX buffers */
203 for (i = 0; i < LAN_SAA9730_BUFFERS; i++) {
204 for (j = 0; j < LAN_SAA9730_RCV_Q_SIZE; j++) {
205 *(unsigned int *) lp->RcvBuffer[i][j] =
206 cpu_to_le32(RXSF_READY <<
207 RX_STAT_CTL_OWNER_SHF);
208 }
209 }
210
211 /* Init TX buffers */
212 for (i = 0; i < LAN_SAA9730_BUFFERS; i++) {
213 for (j = 0; j < LAN_SAA9730_TXM_Q_SIZE; j++) {
214 *(unsigned int *) lp->TxmBuffer[i][j] =
215 cpu_to_le32(TXSF_EMPTY <<
216 TX_STAT_CTL_OWNER_SHF);
217 }
218 }
219}
220
221static void lan_saa9730_free_buffers(struct pci_dev *pdev,
222 struct lan_saa9730_private *lp)
223{
224 pci_free_consistent(pdev, lp->buffer_size, lp->buffer_start,
225 lp->dma_addr);
226}
227
228static int lan_saa9730_allocate_buffers(struct pci_dev *pdev,
229 struct lan_saa9730_private *lp)
230{
231 void *Pa;
232 unsigned int i, j, rxoffset, txoffset;
233 int ret;
234
235 /* Initialize buffer space */
236 lp->DmaRcvPackets = LAN_SAA9730_RCV_Q_SIZE;
237 lp->DmaTxmPackets = LAN_SAA9730_TXM_Q_SIZE;
238
239 /* Initialize Rx Buffer Index */
240 lp->NextRcvPacketIndex = 0;
241 lp->NextRcvBufferIndex = 0;
242
243 /* Set current buffer index & next available packet index */
244 lp->NextTxmPacketIndex = 0;
245 lp->NextTxmBufferIndex = 0;
246 lp->PendingTxmPacketIndex = 0;
247 lp->PendingTxmBufferIndex = 0;
248
249 /*
250 * Allocate all RX and TX packets in one chunk.
251 * The Rx and Tx packets must be PACKET_SIZE aligned.
252 */
253 lp->buffer_size = ((LAN_SAA9730_RCV_Q_SIZE + LAN_SAA9730_TXM_Q_SIZE) *
254 LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_BUFFERS) +
255 LAN_SAA9730_PACKET_SIZE;
256 lp->buffer_start = pci_alloc_consistent(pdev, lp->buffer_size,
257 &lp->dma_addr);
258 if (!lp->buffer_start) {
259 ret = -ENOMEM;
260 goto out;
261 }
262
263 Pa = (void *)ALIGN((unsigned long)lp->buffer_start,
264 LAN_SAA9730_PACKET_SIZE);
265
266 rxoffset = Pa - lp->buffer_start;
267
268 /* Init RX buffers */
269 for (i = 0; i < LAN_SAA9730_BUFFERS; i++) {
270 for (j = 0; j < LAN_SAA9730_RCV_Q_SIZE; j++) {
271 *(unsigned int *) Pa =
272 cpu_to_le32(RXSF_READY <<
273 RX_STAT_CTL_OWNER_SHF);
274 lp->RcvBuffer[i][j] = Pa;
275 Pa += LAN_SAA9730_PACKET_SIZE;
276 }
277 }
278
279 txoffset = Pa - lp->buffer_start;
280
281 /* Init TX buffers */
282 for (i = 0; i < LAN_SAA9730_BUFFERS; i++) {
283 for (j = 0; j < LAN_SAA9730_TXM_Q_SIZE; j++) {
284 *(unsigned int *) Pa =
285 cpu_to_le32(TXSF_EMPTY <<
286 TX_STAT_CTL_OWNER_SHF);
287 lp->TxmBuffer[i][j] = Pa;
288 Pa += LAN_SAA9730_PACKET_SIZE;
289 }
290 }
291
292 /*
293 * Set rx buffer A and rx buffer B to point to the first two buffer
294 * spaces.
295 */
296 writel(lp->dma_addr + rxoffset, &lp->lan_saa9730_regs->RxBuffA);
297 writel(lp->dma_addr + rxoffset +
298 LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_RCV_Q_SIZE,
299 &lp->lan_saa9730_regs->RxBuffB);
300
301 /*
302 * Set txm_buf_a and txm_buf_b to point to the first two buffer
303 * space
304 */
305 writel(lp->dma_addr + txoffset,
306 &lp->lan_saa9730_regs->TxBuffA);
307 writel(lp->dma_addr + txoffset +
308 LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_TXM_Q_SIZE,
309 &lp->lan_saa9730_regs->TxBuffB);
310
311 /* Set packet number */
312 writel((lp->DmaRcvPackets << PK_COUNT_RX_A_SHF) |
313 (lp->DmaRcvPackets << PK_COUNT_RX_B_SHF) |
314 (lp->DmaTxmPackets << PK_COUNT_TX_A_SHF) |
315 (lp->DmaTxmPackets << PK_COUNT_TX_B_SHF),
316 &lp->lan_saa9730_regs->PacketCount);
317
318 return 0;
319
320out:
321 return ret;
322}
323
324static int lan_saa9730_cam_load(struct lan_saa9730_private *lp)
325{
326 unsigned int i;
327 unsigned char *NetworkAddress;
328
329 NetworkAddress = (unsigned char *) &lp->PhysicalAddress[0][0];
330
331 for (i = 0; i < LAN_SAA9730_CAM_DWORDS; i++) {
332 /* First set address to where data is written */
333 writel(i, &lp->lan_saa9730_regs->CamAddress);
334 writel((NetworkAddress[0] << 24) | (NetworkAddress[1] << 16) |
335 (NetworkAddress[2] << 8) | NetworkAddress[3],
336 &lp->lan_saa9730_regs->CamData);
337 NetworkAddress += 4;
338 }
339 return 0;
340}
341
342static int lan_saa9730_cam_init(struct net_device *dev)
343{
344 struct lan_saa9730_private *lp = netdev_priv(dev);
345 unsigned int i;
346
347 /* Copy MAC-address into all entries. */
348 for (i = 0; i < LAN_SAA9730_CAM_ENTRIES; i++) {
349 memcpy((unsigned char *) lp->PhysicalAddress[i],
350 (unsigned char *) dev->dev_addr, 6);
351 }
352
353 return 0;
354}
355
356static int lan_saa9730_mii_init(struct lan_saa9730_private *lp)
357{
358 int i, l;
359
360 /* Check link status, spin here till station is not busy. */
361 i = 0;
362 while (readl(&lp->lan_saa9730_regs->StationMgmtCtl) & MD_CA_BUSY) {
363 i++;
364 if (i > 100) {
365 printk("Error: lan_saa9730_mii_init: timeout\n");
366 return -1;
367 }
368 mdelay(1); /* wait 1 ms. */
369 }
370
371 /* Now set the control and address register. */
372 writel(MD_CA_BUSY | PHY_STATUS | PHY_ADDRESS << MD_CA_PHY_SHF,
373 &lp->lan_saa9730_regs->StationMgmtCtl);
374
375 /* check link status, spin here till station is not busy */
376 i = 0;
377 while (readl(&lp->lan_saa9730_regs->StationMgmtCtl) & MD_CA_BUSY) {
378 i++;
379 if (i > 100) {
380 printk("Error: lan_saa9730_mii_init: timeout\n");
381 return -1;
382 }
383 mdelay(1); /* wait 1 ms. */
384 }
385
386 /* Wait for 1 ms. */
387 mdelay(1);
388
389 /* Check the link status. */
390 if (readl(&lp->lan_saa9730_regs->StationMgmtData) &
391 PHY_STATUS_LINK_UP) {
392 /* Link is up. */
393 return 0;
394 } else {
395 /* Link is down, reset the PHY first. */
396
397 /* set PHY address = 'CONTROL' */
398 writel(PHY_ADDRESS << MD_CA_PHY_SHF | MD_CA_WR | PHY_CONTROL,
399 &lp->lan_saa9730_regs->StationMgmtCtl);
400
401 /* Wait for 1 ms. */
402 mdelay(1);
403
404 /* set 'CONTROL' = force reset and renegotiate */
405 writel(PHY_CONTROL_RESET | PHY_CONTROL_AUTO_NEG |
406 PHY_CONTROL_RESTART_AUTO_NEG,
407 &lp->lan_saa9730_regs->StationMgmtData);
408
409 /* Wait for 50 ms. */
410 mdelay(50);
411
412 /* set 'BUSY' to start operation */
413 writel(MD_CA_BUSY | PHY_ADDRESS << MD_CA_PHY_SHF | MD_CA_WR |
414 PHY_CONTROL, &lp->lan_saa9730_regs->StationMgmtCtl);
415
416 /* await completion */
417 i = 0;
418 while (readl(&lp->lan_saa9730_regs->StationMgmtCtl) &
419 MD_CA_BUSY) {
420 i++;
421 if (i > 100) {
422 printk
423 ("Error: lan_saa9730_mii_init: timeout\n");
424 return -1;
425 }
426 mdelay(1); /* wait 1 ms. */
427 }
428
429 /* Wait for 1 ms. */
430 mdelay(1);
431
432 for (l = 0; l < 2; l++) {
433 /* set PHY address = 'STATUS' */
434 writel(MD_CA_BUSY | PHY_ADDRESS << MD_CA_PHY_SHF |
435 PHY_STATUS,
436 &lp->lan_saa9730_regs->StationMgmtCtl);
437
438 /* await completion */
439 i = 0;
440 while (readl(&lp->lan_saa9730_regs->StationMgmtCtl) &
441 MD_CA_BUSY) {
442 i++;
443 if (i > 100) {
444 printk
445 ("Error: lan_saa9730_mii_init: timeout\n");
446 return -1;
447 }
448 mdelay(1); /* wait 1 ms. */
449 }
450
451 /* wait for 3 sec. */
452 mdelay(3000);
453
454 /* check the link status */
455 if (readl(&lp->lan_saa9730_regs->StationMgmtData) &
456 PHY_STATUS_LINK_UP) {
457 /* link is up */
458 break;
459 }
460 }
461 }
462
463 return 0;
464}
465
466static int lan_saa9730_control_init(struct lan_saa9730_private *lp)
467{
468 /* Initialize DMA control register. */
469 writel((LANMB_ANY << DMA_CTL_MAX_XFER_SHF) |
470 (LANEND_LITTLE << DMA_CTL_ENDIAN_SHF) |
471 (LAN_SAA9730_RCV_Q_INT_THRESHOLD << DMA_CTL_RX_INT_COUNT_SHF)
472 | DMA_CTL_RX_INT_TO_EN | DMA_CTL_RX_INT_EN |
473 DMA_CTL_MAC_RX_INT_EN | DMA_CTL_MAC_TX_INT_EN,
474 &lp->lan_saa9730_regs->LanDmaCtl);
475
476 /* Initial MAC control register. */
477 writel((MACCM_MII << MAC_CONTROL_CONN_SHF) | MAC_CONTROL_FULL_DUP,
478 &lp->lan_saa9730_regs->MacCtl);
479
480 /* Initialize CAM control register. */
481 writel(CAM_CONTROL_COMP_EN | CAM_CONTROL_BROAD_ACC,
482 &lp->lan_saa9730_regs->CamCtl);
483
484 /*
485 * Initialize CAM enable register, only turn on first entry, should
486 * contain own addr.
487 */
488 writel(0x0001, &lp->lan_saa9730_regs->CamEnable);
489
490 /* Initialize Tx control register */
491 writel(TX_CTL_EN_COMP, &lp->lan_saa9730_regs->TxCtl);
492
493 /* Initialize Rcv control register */
494 writel(RX_CTL_STRIP_CRC, &lp->lan_saa9730_regs->RxCtl);
495
496 /* Reset DMA engine */
497 writel(DMA_TEST_SW_RESET, &lp->lan_saa9730_regs->DmaTest);
498
499 return 0;
500}
501
502static int lan_saa9730_stop(struct lan_saa9730_private *lp)
503{
504 int i;
505
506 /* Stop DMA first */
507 writel(readl(&lp->lan_saa9730_regs->LanDmaCtl) &
508 ~(DMA_CTL_EN_TX_DMA | DMA_CTL_EN_RX_DMA),
509 &lp->lan_saa9730_regs->LanDmaCtl);
510
511 /* Set the SW Reset bits in DMA and MAC control registers */
512 writel(DMA_TEST_SW_RESET, &lp->lan_saa9730_regs->DmaTest);
513 writel(readl(&lp->lan_saa9730_regs->MacCtl) | MAC_CONTROL_RESET,
514 &lp->lan_saa9730_regs->MacCtl);
515
516 /*
517 * Wait for MAC reset to have finished. The reset bit is auto cleared
518 * when the reset is done.
519 */
520 i = 0;
521 while (readl(&lp->lan_saa9730_regs->MacCtl) & MAC_CONTROL_RESET) {
522 i++;
523 if (i > 100) {
524 printk
525 ("Error: lan_sa9730_stop: MAC reset timeout\n");
526 return -1;
527 }
528 mdelay(1); /* wait 1 ms. */
529 }
530
531 return 0;
532}
533
534static int lan_saa9730_dma_init(struct lan_saa9730_private *lp)
535{
536 /* Stop lan controller. */
537 lan_saa9730_stop(lp);
538
539 writel(LAN_SAA9730_DEFAULT_TIME_OUT_CNT,
540 &lp->lan_saa9730_regs->Timeout);
541
542 return 0;
543}
544
545static int lan_saa9730_start(struct lan_saa9730_private *lp)
546{
547 lan_saa9730_buffer_init(lp);
548
549 /* Initialize Rx Buffer Index */
550 lp->NextRcvPacketIndex = 0;
551 lp->NextRcvBufferIndex = 0;
552
553 /* Set current buffer index & next available packet index */
554 lp->NextTxmPacketIndex = 0;
555 lp->NextTxmBufferIndex = 0;
556 lp->PendingTxmPacketIndex = 0;
557 lp->PendingTxmBufferIndex = 0;
558
559 writel(readl(&lp->lan_saa9730_regs->LanDmaCtl) | DMA_CTL_EN_TX_DMA |
560 DMA_CTL_EN_RX_DMA, &lp->lan_saa9730_regs->LanDmaCtl);
561
562 /* For Tx, turn on MAC then DMA */
563 writel(readl(&lp->lan_saa9730_regs->TxCtl) | TX_CTL_TX_EN,
564 &lp->lan_saa9730_regs->TxCtl);
565
566 /* For Rx, turn on DMA then MAC */
567 writel(readl(&lp->lan_saa9730_regs->RxCtl) | RX_CTL_RX_EN,
568 &lp->lan_saa9730_regs->RxCtl);
569
570 /* Set Ok2Use to let hardware own the buffers. */
571 writel(OK2USE_RX_A | OK2USE_RX_B, &lp->lan_saa9730_regs->Ok2Use);
572
573 return 0;
574}
575
576static int lan_saa9730_restart(struct lan_saa9730_private *lp)
577{
578 lan_saa9730_stop(lp);
579 lan_saa9730_start(lp);
580
581 return 0;
582}
583
584static int lan_saa9730_tx(struct net_device *dev)
585{
586 struct lan_saa9730_private *lp = netdev_priv(dev);
587 unsigned int *pPacket;
588 unsigned int tx_status;
589
590 if (lan_saa9730_debug > 5)
591 printk("lan_saa9730_tx interrupt\n");
592
593 /* Clear interrupt. */
594 writel(DMA_STATUS_MAC_TX_INT, &lp->lan_saa9730_regs->DmaStatus);
595
596 while (1) {
597 pPacket = lp->TxmBuffer[lp->PendingTxmBufferIndex]
598 [lp->PendingTxmPacketIndex];
599
600 /* Get status of first packet transmitted. */
601 tx_status = le32_to_cpu(*pPacket);
602
603 /* Check ownership. */
604 if ((tx_status & TX_STAT_CTL_OWNER_MSK) !=
605 (TXSF_HWDONE << TX_STAT_CTL_OWNER_SHF)) break;
606
607 /* Check for error. */
608 if (tx_status & TX_STAT_CTL_ERROR_MSK) {
609 if (lan_saa9730_debug > 1)
610 printk("lan_saa9730_tx: tx error = %x\n",
611 tx_status);
612
613 dev->stats.tx_errors++;
614 if (tx_status &
615 (TX_STATUS_EX_COLL << TX_STAT_CTL_STATUS_SHF))
616 dev->stats.tx_aborted_errors++;
617 if (tx_status &
618 (TX_STATUS_LATE_COLL << TX_STAT_CTL_STATUS_SHF))
619 dev->stats.tx_window_errors++;
620 if (tx_status &
621 (TX_STATUS_L_CARR << TX_STAT_CTL_STATUS_SHF))
622 dev->stats.tx_carrier_errors++;
623 if (tx_status &
624 (TX_STATUS_UNDER << TX_STAT_CTL_STATUS_SHF))
625 dev->stats.tx_fifo_errors++;
626 if (tx_status &
627 (TX_STATUS_SQ_ERR << TX_STAT_CTL_STATUS_SHF))
628 dev->stats.tx_heartbeat_errors++;
629
630 dev->stats.collisions +=
631 tx_status & TX_STATUS_TX_COLL_MSK;
632 }
633
634 /* Free buffer. */
635 *pPacket =
636 cpu_to_le32(TXSF_EMPTY << TX_STAT_CTL_OWNER_SHF);
637
638 /* Update pending index pointer. */
639 lp->PendingTxmPacketIndex++;
640 if (lp->PendingTxmPacketIndex >= LAN_SAA9730_TXM_Q_SIZE) {
641 lp->PendingTxmPacketIndex = 0;
642 lp->PendingTxmBufferIndex ^= 1;
643 }
644 }
645
646 /* The tx buffer is no longer full. */
647 netif_wake_queue(dev);
648
649 return 0;
650}
651
652static int lan_saa9730_rx(struct net_device *dev)
653{
654 struct lan_saa9730_private *lp = netdev_priv(dev);
655 int len = 0;
656 struct sk_buff *skb = 0;
657 unsigned int rx_status;
658 int BufferIndex;
659 int PacketIndex;
660 unsigned int *pPacket;
661 unsigned char *pData;
662
663 if (lan_saa9730_debug > 5)
664 printk("lan_saa9730_rx interrupt\n");
665
666 /* Clear receive interrupts. */
667 writel(DMA_STATUS_MAC_RX_INT | DMA_STATUS_RX_INT |
668 DMA_STATUS_RX_TO_INT, &lp->lan_saa9730_regs->DmaStatus);
669
670 /* Address next packet */
671 BufferIndex = lp->NextRcvBufferIndex;
672 PacketIndex = lp->NextRcvPacketIndex;
673 pPacket = lp->RcvBuffer[BufferIndex][PacketIndex];
674 rx_status = le32_to_cpu(*pPacket);
675
676 /* Process each packet. */
677 while ((rx_status & RX_STAT_CTL_OWNER_MSK) ==
678 (RXSF_HWDONE << RX_STAT_CTL_OWNER_SHF)) {
679 /* Check the rx status. */
680 if (rx_status & (RX_STATUS_GOOD << RX_STAT_CTL_STATUS_SHF)) {
681 /* Received packet is good. */
682 len = (rx_status & RX_STAT_CTL_LENGTH_MSK) >>
683 RX_STAT_CTL_LENGTH_SHF;
684
685 pData = (unsigned char *) pPacket;
686 pData += 4;
687 skb = dev_alloc_skb(len + 2);
688 if (skb == 0) {
689 printk
690 ("%s: Memory squeeze, deferring packet.\n",
691 dev->name);
692 dev->stats.rx_dropped++;
693 } else {
694 dev->stats.rx_bytes += len;
695 dev->stats.rx_packets++;
696 skb_reserve(skb, 2); /* 16 byte align */
697 skb_put(skb, len); /* make room */
698 skb_copy_to_linear_data(skb,
699 (unsigned char *) pData,
700 len);
701 skb->protocol = eth_type_trans(skb, dev);
702 netif_rx(skb);
703 dev->last_rx = jiffies;
704 }
705 } else {
706 /* We got an error packet. */
707 if (lan_saa9730_debug > 2)
708 printk
709 ("lan_saa9730_rx: We got an error packet = %x\n",
710 rx_status);
711
712 dev->stats.rx_errors++;
713 if (rx_status &
714 (RX_STATUS_CRC_ERR << RX_STAT_CTL_STATUS_SHF))
715 dev->stats.rx_crc_errors++;
716 if (rx_status &
717 (RX_STATUS_ALIGN_ERR << RX_STAT_CTL_STATUS_SHF))
718 dev->stats.rx_frame_errors++;
719 if (rx_status &
720 (RX_STATUS_OVERFLOW << RX_STAT_CTL_STATUS_SHF))
721 dev->stats.rx_fifo_errors++;
722 if (rx_status &
723 (RX_STATUS_LONG_ERR << RX_STAT_CTL_STATUS_SHF))
724 dev->stats.rx_length_errors++;
725 }
726
727 /* Indicate we have processed the buffer. */
728 *pPacket = cpu_to_le32(RXSF_READY << RX_STAT_CTL_OWNER_SHF);
729
730 /* Make sure A or B is available to hardware as appropriate. */
731 writel(BufferIndex ? OK2USE_RX_B : OK2USE_RX_A,
732 &lp->lan_saa9730_regs->Ok2Use);
733
734 /* Go to next packet in sequence. */
735 lp->NextRcvPacketIndex++;
736 if (lp->NextRcvPacketIndex >= LAN_SAA9730_RCV_Q_SIZE) {
737 lp->NextRcvPacketIndex = 0;
738 lp->NextRcvBufferIndex ^= 1;
739 }
740
741 /* Address next packet */
742 BufferIndex = lp->NextRcvBufferIndex;
743 PacketIndex = lp->NextRcvPacketIndex;
744 pPacket = lp->RcvBuffer[BufferIndex][PacketIndex];
745 rx_status = le32_to_cpu(*pPacket);
746 }
747
748 return 0;
749}
750
751static irqreturn_t lan_saa9730_interrupt(const int irq, void *dev_id)
752{
753 struct net_device *dev = dev_id;
754 struct lan_saa9730_private *lp = netdev_priv(dev);
755
756 if (lan_saa9730_debug > 5)
757 printk("lan_saa9730_interrupt\n");
758
759 /* Disable the EVM LAN interrupt. */
760 evm_saa9730_block_lan_int(lp);
761
762 /* Clear the EVM LAN interrupt. */
763 evm_saa9730_clear_lan_int(lp);
764
765 /* Service pending transmit interrupts. */
766 if (readl(&lp->lan_saa9730_regs->DmaStatus) & DMA_STATUS_MAC_TX_INT)
767 lan_saa9730_tx(dev);
768
769 /* Service pending receive interrupts. */
770 if (readl(&lp->lan_saa9730_regs->DmaStatus) &
771 (DMA_STATUS_MAC_RX_INT | DMA_STATUS_RX_INT |
772 DMA_STATUS_RX_TO_INT)) lan_saa9730_rx(dev);
773
774 /* Enable the EVM LAN interrupt. */
775 evm_saa9730_unblock_lan_int(lp);
776
777 return IRQ_HANDLED;
778}
779
780static int lan_saa9730_open(struct net_device *dev)
781{
782 struct lan_saa9730_private *lp = netdev_priv(dev);
783
784 /* Associate IRQ with lan_saa9730_interrupt */
785 if (request_irq(dev->irq, &lan_saa9730_interrupt, 0, "SAA9730 Eth",
786 dev)) {
787 printk("lan_saa9730_open: Can't get irq %d\n", dev->irq);
788 return -EAGAIN;
789 }
790
791 /* Enable the Lan interrupt in the event manager. */
792 evm_saa9730_enable_lan_int(lp);
793
794 /* Start the LAN controller */
795 if (lan_saa9730_start(lp))
796 return -1;
797
798 netif_start_queue(dev);
799
800 return 0;
801}
802
803static int lan_saa9730_write(struct lan_saa9730_private *lp,
804 struct sk_buff *skb, int skblen)
805{
806 unsigned char *pbData = skb->data;
807 unsigned int len = skblen;
808 unsigned char *pbPacketData;
809 unsigned int tx_status;
810 int BufferIndex;
811 int PacketIndex;
812
813 if (lan_saa9730_debug > 5)
814 printk("lan_saa9730_write: skb=%p\n", skb);
815
816 BufferIndex = lp->NextTxmBufferIndex;
817 PacketIndex = lp->NextTxmPacketIndex;
818
819 tx_status = le32_to_cpu(*(unsigned int *)lp->TxmBuffer[BufferIndex]
820 [PacketIndex]);
821 if ((tx_status & TX_STAT_CTL_OWNER_MSK) !=
822 (TXSF_EMPTY << TX_STAT_CTL_OWNER_SHF)) {
823 if (lan_saa9730_debug > 4)
824 printk
825 ("lan_saa9730_write: Tx buffer not available: tx_status = %x\n",
826 tx_status);
827 return -1;
828 }
829
830 lp->NextTxmPacketIndex++;
831 if (lp->NextTxmPacketIndex >= LAN_SAA9730_TXM_Q_SIZE) {
832 lp->NextTxmPacketIndex = 0;
833 lp->NextTxmBufferIndex ^= 1;
834 }
835
836 pbPacketData = lp->TxmBuffer[BufferIndex][PacketIndex];
837 pbPacketData += 4;
838
839 /* copy the bits */
840 memcpy(pbPacketData, pbData, len);
841
842 /* Set transmit status for hardware */
843 *(unsigned int *)lp->TxmBuffer[BufferIndex][PacketIndex] =
844 cpu_to_le32((TXSF_READY << TX_STAT_CTL_OWNER_SHF) |
845 (TX_STAT_CTL_INT_AFTER_TX <<
846 TX_STAT_CTL_FRAME_SHF) |
847 (len << TX_STAT_CTL_LENGTH_SHF));
848
849 /* Make sure A or B is available to hardware as appropriate. */
850 writel(BufferIndex ? OK2USE_TX_B : OK2USE_TX_A,
851 &lp->lan_saa9730_regs->Ok2Use);
852
853 return 0;
854}
855
856static void lan_saa9730_tx_timeout(struct net_device *dev)
857{
858 struct lan_saa9730_private *lp = netdev_priv(dev);
859
860 /* Transmitter timeout, serious problems */
861 dev->stats.tx_errors++;
862 printk("%s: transmit timed out, reset\n", dev->name);
863 /*show_saa9730_regs(dev); */
864 lan_saa9730_restart(lp);
865
866 dev->trans_start = jiffies;
867 netif_wake_queue(dev);
868}
869
870static int lan_saa9730_start_xmit(struct sk_buff *skb,
871 struct net_device *dev)
872{
873 struct lan_saa9730_private *lp = netdev_priv(dev);
874 unsigned long flags;
875 int skblen;
876 int len;
877
878 if (lan_saa9730_debug > 4)
879 printk("Send packet: skb=%p\n", skb);
880
881 skblen = skb->len;
882
883 spin_lock_irqsave(&lp->lock, flags);
884
885 len = (skblen <= ETH_ZLEN) ? ETH_ZLEN : skblen;
886
887 if (lan_saa9730_write(lp, skb, skblen)) {
888 spin_unlock_irqrestore(&lp->lock, flags);
889 printk("Error when writing packet to controller: skb=%p\n", skb);
890 netif_stop_queue(dev);
891 return -1;
892 }
893
894 dev->stats.tx_bytes += len;
895 dev->stats.tx_packets++;
896
897 dev->trans_start = jiffies;
898 netif_wake_queue(dev);
899 dev_kfree_skb(skb);
900
901 spin_unlock_irqrestore(&lp->lock, flags);
902
903 return 0;
904}
905
906static int lan_saa9730_close(struct net_device *dev)
907{
908 struct lan_saa9730_private *lp = netdev_priv(dev);
909
910 if (lan_saa9730_debug > 1)
911 printk("lan_saa9730_close:\n");
912
913 netif_stop_queue(dev);
914
915 /* Disable the Lan interrupt in the event manager. */
916 evm_saa9730_disable_lan_int(lp);
917
918 /* Stop the controller */
919 if (lan_saa9730_stop(lp))
920 return -1;
921
922 free_irq(dev->irq, (void *) dev);
923
924 return 0;
925}
926
927static void lan_saa9730_set_multicast(struct net_device *dev)
928{
929 struct lan_saa9730_private *lp = netdev_priv(dev);
930
931 /* Stop the controller */
932 lan_saa9730_stop(lp);
933
934 if (dev->flags & IFF_PROMISC) {
935 /* accept all packets */
936 writel(CAM_CONTROL_COMP_EN | CAM_CONTROL_STATION_ACC |
937 CAM_CONTROL_GROUP_ACC | CAM_CONTROL_BROAD_ACC,
938 &lp->lan_saa9730_regs->CamCtl);
939 } else {
940 if (dev->flags & IFF_ALLMULTI || dev->mc_count) {
941 /* accept all multicast packets */
942 /*
943 * Will handle the multicast stuff later. -carstenl
944 */
945 writel(CAM_CONTROL_COMP_EN | CAM_CONTROL_GROUP_ACC |
946 CAM_CONTROL_BROAD_ACC,
947 &lp->lan_saa9730_regs->CamCtl);
948 }
949 }
950
951 lan_saa9730_restart(lp);
952}
953
954
955static void __devexit saa9730_remove_one(struct pci_dev *pdev)
956{
957 struct net_device *dev = pci_get_drvdata(pdev);
958 struct lan_saa9730_private *lp = netdev_priv(dev);
959
960 if (dev) {
961 unregister_netdev(dev);
962 lan_saa9730_free_buffers(pdev, lp);
963 iounmap(lp->lan_saa9730_regs);
964 iounmap(lp->evm_saa9730_regs);
965 free_netdev(dev);
966 pci_release_regions(pdev);
967 pci_disable_device(pdev);
968 pci_set_drvdata(pdev, NULL);
969 }
970}
971
972
973static int lan_saa9730_init(struct net_device *dev, struct pci_dev *pdev,
974 unsigned long ioaddr, int irq)
975{
976 struct lan_saa9730_private *lp = netdev_priv(dev);
977 unsigned char ethernet_addr[6];
978 int ret;
979
980 if (get_ethernet_addr(ethernet_addr)) {
981 ret = -ENODEV;
982 goto out;
983 }
984
985 memcpy(dev->dev_addr, ethernet_addr, 6);
986 dev->base_addr = ioaddr;
987 dev->irq = irq;
988
989 lp->pci_dev = pdev;
990
991 /* Set SAA9730 LAN base address. */
992 lp->lan_saa9730_regs = ioremap(ioaddr + SAA9730_LAN_REGS_ADDR,
993 SAA9730_LAN_REGS_SIZE);
994 if (!lp->lan_saa9730_regs) {
995 ret = -ENOMEM;
996 goto out;
997 }
998
999 /* Set SAA9730 EVM base address. */
1000 lp->evm_saa9730_regs = ioremap(ioaddr + SAA9730_EVM_REGS_ADDR,
1001 SAA9730_EVM_REGS_SIZE);
1002 if (!lp->evm_saa9730_regs) {
1003 ret = -ENOMEM;
1004 goto out_iounmap_lan;
1005 }
1006
1007 /* Allocate LAN RX/TX frame buffer space. */
1008 if ((ret = lan_saa9730_allocate_buffers(pdev, lp)))
1009 goto out_iounmap;
1010
1011 /* Stop LAN controller. */
1012 if ((ret = lan_saa9730_stop(lp)))
1013 goto out_free_consistent;
1014
1015 /* Initialize CAM registers. */
1016 if ((ret = lan_saa9730_cam_init(dev)))
1017 goto out_free_consistent;
1018
1019 /* Initialize MII registers. */
1020 if ((ret = lan_saa9730_mii_init(lp)))
1021 goto out_free_consistent;
1022
1023 /* Initialize control registers. */
1024 if ((ret = lan_saa9730_control_init(lp)))
1025 goto out_free_consistent;
1026
1027 /* Load CAM registers. */
1028 if ((ret = lan_saa9730_cam_load(lp)))
1029 goto out_free_consistent;
1030
1031 /* Initialize DMA context registers. */
1032 if ((ret = lan_saa9730_dma_init(lp)))
1033 goto out_free_consistent;
1034
1035 spin_lock_init(&lp->lock);
1036
1037 dev->open = lan_saa9730_open;
1038 dev->hard_start_xmit = lan_saa9730_start_xmit;
1039 dev->stop = lan_saa9730_close;
1040 dev->set_multicast_list = lan_saa9730_set_multicast;
1041 dev->tx_timeout = lan_saa9730_tx_timeout;
1042 dev->watchdog_timeo = (HZ >> 1);
1043 dev->dma = 0;
1044
1045 ret = register_netdev (dev);
1046 if (ret)
1047 goto out_free_consistent;
1048
1049 return 0;
1050
1051out_free_consistent:
1052 lan_saa9730_free_buffers(pdev, lp);
1053out_iounmap:
1054 iounmap(lp->evm_saa9730_regs);
1055out_iounmap_lan:
1056 iounmap(lp->lan_saa9730_regs);
1057out:
1058 return ret;
1059}
1060
1061
1062static int __devinit saa9730_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1063{
1064 struct net_device *dev = NULL;
1065 unsigned long pci_ioaddr;
1066 int err;
1067
1068 if (lan_saa9730_debug > 1)
1069 printk("saa9730.c: PCI bios is present, checking for devices...\n");
1070
1071 err = pci_enable_device(pdev);
1072 if (err) {
1073 printk(KERN_ERR "Cannot enable PCI device, aborting.\n");
1074 goto out;
1075 }
1076
1077 err = pci_request_regions(pdev, DRV_MODULE_NAME);
1078 if (err) {
1079 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
1080 goto out_disable_pdev;
1081 }
1082
1083 pci_irq_line = pdev->irq;
1084 /* LAN base address in located at BAR 1. */
1085
1086 pci_ioaddr = pci_resource_start(pdev, 1);
1087 pci_set_master(pdev);
1088
1089 printk("Found SAA9730 (PCI) at %lx, irq %d.\n",
1090 pci_ioaddr, pci_irq_line);
1091
1092 dev = alloc_etherdev(sizeof(struct lan_saa9730_private));
1093 if (!dev)
1094 goto out_disable_pdev;
1095
1096 err = lan_saa9730_init(dev, pdev, pci_ioaddr, pci_irq_line);
1097 if (err) {
1098 printk("LAN init failed");
1099 goto out_free_netdev;
1100 }
1101
1102 pci_set_drvdata(pdev, dev);
1103 SET_NETDEV_DEV(dev, &pdev->dev);
1104 return 0;
1105
1106out_free_netdev:
1107 free_netdev(dev);
1108out_disable_pdev:
1109 pci_disable_device(pdev);
1110out:
1111 pci_set_drvdata(pdev, NULL);
1112 return err;
1113}
1114
1115
1116static struct pci_driver saa9730_driver = {
1117 .name = DRV_MODULE_NAME,
1118 .id_table = saa9730_pci_tbl,
1119 .probe = saa9730_init_one,
1120 .remove = __devexit_p(saa9730_remove_one),
1121};
1122
1123
1124static int __init saa9730_init(void)
1125{
1126 return pci_register_driver(&saa9730_driver);
1127}
1128
1129static void __exit saa9730_cleanup(void)
1130{
1131 pci_unregister_driver(&saa9730_driver);
1132}
1133
1134module_init(saa9730_init);
1135module_exit(saa9730_cleanup);
1136
1137MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1138MODULE_DESCRIPTION("Philips SAA9730 ethernet driver");
1139MODULE_LICENSE("GPL");
diff --git a/drivers/net/saa9730.h b/drivers/net/saa9730.h
deleted file mode 100644
index 010a120ea938..000000000000
--- a/drivers/net/saa9730.h
+++ /dev/null
@@ -1,384 +0,0 @@
1/*
2 * Copyright (C) 2000, 2005 MIPS Technologies, Inc. All rights reserved.
3 * Authors: Carsten Langgaard <carstenl@mips.com>
4 * Maciej W. Rozycki <macro@mips.com>
5 *
6 * ########################################################################
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * ########################################################################
22 *
23 * SAA9730 ethernet driver description.
24 *
25 */
26#ifndef _SAA9730_H
27#define _SAA9730_H
28
29
30/* Number of 6-byte entries in the CAM. */
31#define LAN_SAA9730_CAM_ENTRIES 10
32#define LAN_SAA9730_CAM_DWORDS ((LAN_SAA9730_CAM_ENTRIES*6)/4)
33
34/* TX and RX packet size: fixed to 2048 bytes, according to HW requirements. */
35#define LAN_SAA9730_PACKET_SIZE 2048
36
37/*
38 * Number of TX buffers = number of RX buffers = 2, which is fixed according
39 * to HW requirements.
40 */
41#define LAN_SAA9730_BUFFERS 2
42
43/* Number of RX packets per RX buffer. */
44#define LAN_SAA9730_RCV_Q_SIZE 15
45
46/* Number of TX packets per TX buffer. */
47#define LAN_SAA9730_TXM_Q_SIZE 15
48
49/*
50 * We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
51 * packets received.
52 * If however we receive less than LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
53 * packets, the hardware can timeout after a certain time and still tell
54 * us packets have arrived.
55 * The timeout value in unit of 32 PCI clocks (33Mhz).
56 * The value 200 approximates 0.0002 seconds.
57 */
58#define LAN_SAA9730_RCV_Q_INT_THRESHOLD 1
59#define LAN_SAA9730_DEFAULT_TIME_OUT_CNT 10
60
61#define RXSF_NDIS 0
62#define RXSF_READY 2
63#define RXSF_HWDONE 3
64
65#define TXSF_EMPTY 0
66#define TXSF_READY 2
67#define TXSF_HWDONE 3
68
69#define LANEND_LITTLE 0
70#define LANEND_BIG_2143 1
71#define LANEND_BIG_4321 2
72
73#define LANMB_ANY 0
74#define LANMB_8 1
75#define LANMB_32 2
76#define LANMB_64 3
77
78#define MACCM_AUTOMATIC 0
79#define MACCM_10MB 1
80#define MACCM_MII 2
81
82/*
83 * PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board)
84 */
85#define PHY_CONTROL 0x0
86#define PHY_STATUS 0x1
87#define PHY_STATUS_LINK_UP 0x4
88#define PHY_CONTROL_RESET 0x8000
89#define PHY_CONTROL_AUTO_NEG 0x1000
90#define PHY_CONTROL_RESTART_AUTO_NEG 0x0200
91#define PHY_ADDRESS 0x0
92
93/* PK_COUNT register. */
94#define PK_COUNT_TX_A_SHF 24
95#define PK_COUNT_TX_A_MSK (0xff << PK_COUNT_TX_A_SHF)
96#define PK_COUNT_TX_B_SHF 16
97#define PK_COUNT_TX_B_MSK (0xff << PK_COUNT_TX_B_SHF)
98#define PK_COUNT_RX_A_SHF 8
99#define PK_COUNT_RX_A_MSK (0xff << PK_COUNT_RX_A_SHF)
100#define PK_COUNT_RX_B_SHF 0
101#define PK_COUNT_RX_B_MSK (0xff << PK_COUNT_RX_B_SHF)
102
103/* OK2USE register. */
104#define OK2USE_TX_A 0x8
105#define OK2USE_TX_B 0x4
106#define OK2USE_RX_A 0x2
107#define OK2USE_RX_B 0x1
108
109/* LAN DMA CONTROL register. */
110#define DMA_CTL_BLK_INT 0x80000000
111#define DMA_CTL_MAX_XFER_SHF 18
112#define DMA_CTL_MAX_XFER_MSK (0x3 << LAN_DMA_CTL_MAX_XFER_SHF)
113#define DMA_CTL_ENDIAN_SHF 16
114#define DMA_CTL_ENDIAN_MSK (0x3 << LAN_DMA_CTL_ENDIAN_SHF)
115#define DMA_CTL_RX_INT_COUNT_SHF 8
116#define DMA_CTL_RX_INT_COUNT_MSK (0xff << LAN_DMA_CTL_RX_INT_COUNT_SHF)
117#define DMA_CTL_EN_TX_DMA 0x00000080
118#define DMA_CTL_EN_RX_DMA 0x00000040
119#define DMA_CTL_RX_INT_BUFFUL_EN 0x00000020
120#define DMA_CTL_RX_INT_TO_EN 0x00000010
121#define DMA_CTL_RX_INT_EN 0x00000008
122#define DMA_CTL_TX_INT_EN 0x00000004
123#define DMA_CTL_MAC_TX_INT_EN 0x00000002
124#define DMA_CTL_MAC_RX_INT_EN 0x00000001
125
126/* DMA STATUS register. */
127#define DMA_STATUS_BAD_ADDR_SHF 16
128#define DMA_STATUS_BAD_ADDR_MSK (0xf << DMA_STATUS_BAD_ADDR_SHF)
129#define DMA_STATUS_RX_PKTS_RECEIVED_SHF 8
130#define DMA_STATUS_RX_PKTS_RECEIVED_MSK (0xff << DMA_STATUS_RX_PKTS_RECEIVED_SHF)
131#define DMA_STATUS_TX_EN_SYNC 0x00000080
132#define DMA_STATUS_RX_BUF_A_FUL 0x00000040
133#define DMA_STATUS_RX_BUF_B_FUL 0x00000020
134#define DMA_STATUS_RX_TO_INT 0x00000010
135#define DMA_STATUS_RX_INT 0x00000008
136#define DMA_STATUS_TX_INT 0x00000004
137#define DMA_STATUS_MAC_TX_INT 0x00000002
138#define DMA_STATUS_MAC_RX_INT 0x00000001
139
140/* DMA TEST/PANIC SWITHES register. */
141#define DMA_TEST_LOOPBACK 0x01000000
142#define DMA_TEST_SW_RESET 0x00000001
143
144/* MAC CONTROL register. */
145#define MAC_CONTROL_EN_MISS_ROLL 0x00002000
146#define MAC_CONTROL_MISS_ROLL 0x00000400
147#define MAC_CONTROL_LOOP10 0x00000080
148#define MAC_CONTROL_CONN_SHF 5
149#define MAC_CONTROL_CONN_MSK (0x3 << MAC_CONTROL_CONN_SHF)
150#define MAC_CONTROL_MAC_LOOP 0x00000010
151#define MAC_CONTROL_FULL_DUP 0x00000008
152#define MAC_CONTROL_RESET 0x00000004
153#define MAC_CONTROL_HALT_IMM 0x00000002
154#define MAC_CONTROL_HALT_REQ 0x00000001
155
156/* CAM CONTROL register. */
157#define CAM_CONTROL_COMP_EN 0x00000010
158#define CAM_CONTROL_NEG_CAM 0x00000008
159#define CAM_CONTROL_BROAD_ACC 0x00000004
160#define CAM_CONTROL_GROUP_ACC 0x00000002
161#define CAM_CONTROL_STATION_ACC 0x00000001
162
163/* TRANSMIT CONTROL register. */
164#define TX_CTL_EN_COMP 0x00004000
165#define TX_CTL_EN_TX_PAR 0x00002000
166#define TX_CTL_EN_LATE_COLL 0x00001000
167#define TX_CTL_EN_EX_COLL 0x00000800
168#define TX_CTL_EN_L_CARR 0x00000400
169#define TX_CTL_EN_EX_DEFER 0x00000200
170#define TX_CTL_EN_UNDER 0x00000100
171#define TX_CTL_MII10 0x00000080
172#define TX_CTL_SD_PAUSE 0x00000040
173#define TX_CTL_NO_EX_DEF0 0x00000020
174#define TX_CTL_F_BACK 0x00000010
175#define TX_CTL_NO_CRC 0x00000008
176#define TX_CTL_NO_PAD 0x00000004
177#define TX_CTL_TX_HALT 0x00000002
178#define TX_CTL_TX_EN 0x00000001
179
180/* TRANSMIT STATUS register. */
181#define TX_STATUS_SQ_ERR 0x00010000
182#define TX_STATUS_TX_HALTED 0x00008000
183#define TX_STATUS_COMP 0x00004000
184#define TX_STATUS_TX_PAR 0x00002000
185#define TX_STATUS_LATE_COLL 0x00001000
186#define TX_STATUS_TX10_STAT 0x00000800
187#define TX_STATUS_L_CARR 0x00000400
188#define TX_STATUS_EX_DEFER 0x00000200
189#define TX_STATUS_UNDER 0x00000100
190#define TX_STATUS_IN_TX 0x00000080
191#define TX_STATUS_PAUSED 0x00000040
192#define TX_STATUS_TX_DEFERRED 0x00000020
193#define TX_STATUS_EX_COLL 0x00000010
194#define TX_STATUS_TX_COLL_SHF 0
195#define TX_STATUS_TX_COLL_MSK (0xf << TX_STATUS_TX_COLL_SHF)
196
197/* RECEIVE CONTROL register. */
198#define RX_CTL_EN_GOOD 0x00004000
199#define RX_CTL_EN_RX_PAR 0x00002000
200#define RX_CTL_EN_LONG_ERR 0x00000800
201#define RX_CTL_EN_OVER 0x00000400
202#define RX_CTL_EN_CRC_ERR 0x00000200
203#define RX_CTL_EN_ALIGN 0x00000100
204#define RX_CTL_IGNORE_CRC 0x00000040
205#define RX_CTL_PASS_CTL 0x00000020
206#define RX_CTL_STRIP_CRC 0x00000010
207#define RX_CTL_SHORT_EN 0x00000008
208#define RX_CTL_LONG_EN 0x00000004
209#define RX_CTL_RX_HALT 0x00000002
210#define RX_CTL_RX_EN 0x00000001
211
212/* RECEIVE STATUS register. */
213#define RX_STATUS_RX_HALTED 0x00008000
214#define RX_STATUS_GOOD 0x00004000
215#define RX_STATUS_RX_PAR 0x00002000
216#define RX_STATUS_LONG_ERR 0x00000800
217#define RX_STATUS_OVERFLOW 0x00000400
218#define RX_STATUS_CRC_ERR 0x00000200
219#define RX_STATUS_ALIGN_ERR 0x00000100
220#define RX_STATUS_RX10_STAT 0x00000080
221#define RX_STATUS_INT_RX 0x00000040
222#define RX_STATUS_CTL_RECD 0x00000020
223
224/* MD_CA register. */
225#define MD_CA_PRE_SUP 0x00001000
226#define MD_CA_BUSY 0x00000800
227#define MD_CA_WR 0x00000400
228#define MD_CA_PHY_SHF 5
229#define MD_CA_PHY_MSK (0x1f << MD_CA_PHY_SHF)
230#define MD_CA_ADDR_SHF 0
231#define MD_CA_ADDR_MSK (0x1f << MD_CA_ADDR_SHF)
232
233/* Tx Status/Control. */
234#define TX_STAT_CTL_OWNER_SHF 30
235#define TX_STAT_CTL_OWNER_MSK (0x3 << TX_STAT_CTL_OWNER_SHF)
236#define TX_STAT_CTL_FRAME_SHF 27
237#define TX_STAT_CTL_FRAME_MSK (0x7 << TX_STAT_CTL_FRAME_SHF)
238#define TX_STAT_CTL_STATUS_SHF 11
239#define TX_STAT_CTL_STATUS_MSK (0x1ffff << TX_STAT_CTL_STATUS_SHF)
240#define TX_STAT_CTL_LENGTH_SHF 0
241#define TX_STAT_CTL_LENGTH_MSK (0x7ff << TX_STAT_CTL_LENGTH_SHF)
242
243#define TX_STAT_CTL_ERROR_MSK ((TX_STATUS_SQ_ERR | \
244 TX_STATUS_TX_HALTED | \
245 TX_STATUS_TX_PAR | \
246 TX_STATUS_LATE_COLL | \
247 TX_STATUS_L_CARR | \
248 TX_STATUS_EX_DEFER | \
249 TX_STATUS_UNDER | \
250 TX_STATUS_PAUSED | \
251 TX_STATUS_TX_DEFERRED | \
252 TX_STATUS_EX_COLL | \
253 TX_STATUS_TX_COLL_MSK) \
254 << TX_STAT_CTL_STATUS_SHF)
255#define TX_STAT_CTL_INT_AFTER_TX 0x4
256
257/* Rx Status/Control. */
258#define RX_STAT_CTL_OWNER_SHF 30
259#define RX_STAT_CTL_OWNER_MSK (0x3 << RX_STAT_CTL_OWNER_SHF)
260#define RX_STAT_CTL_STATUS_SHF 11
261#define RX_STAT_CTL_STATUS_MSK (0xffff << RX_STAT_CTL_STATUS_SHF)
262#define RX_STAT_CTL_LENGTH_SHF 0
263#define RX_STAT_CTL_LENGTH_MSK (0x7ff << RX_STAT_CTL_LENGTH_SHF)
264
265
266
267/* The SAA9730 (LAN) controller register map, as seen via the PCI-bus. */
268#define SAA9730_LAN_REGS_ADDR 0x20400
269#define SAA9730_LAN_REGS_SIZE 0x00400
270
271struct lan_saa9730_regmap {
272 volatile unsigned int TxBuffA; /* 0x20400 */
273 volatile unsigned int TxBuffB; /* 0x20404 */
274 volatile unsigned int RxBuffA; /* 0x20408 */
275 volatile unsigned int RxBuffB; /* 0x2040c */
276 volatile unsigned int PacketCount; /* 0x20410 */
277 volatile unsigned int Ok2Use; /* 0x20414 */
278 volatile unsigned int LanDmaCtl; /* 0x20418 */
279 volatile unsigned int Timeout; /* 0x2041c */
280 volatile unsigned int DmaStatus; /* 0x20420 */
281 volatile unsigned int DmaTest; /* 0x20424 */
282 volatile unsigned char filler20428[0x20430 - 0x20428];
283 volatile unsigned int PauseCount; /* 0x20430 */
284 volatile unsigned int RemotePauseCount; /* 0x20434 */
285 volatile unsigned char filler20438[0x20440 - 0x20438];
286 volatile unsigned int MacCtl; /* 0x20440 */
287 volatile unsigned int CamCtl; /* 0x20444 */
288 volatile unsigned int TxCtl; /* 0x20448 */
289 volatile unsigned int TxStatus; /* 0x2044c */
290 volatile unsigned int RxCtl; /* 0x20450 */
291 volatile unsigned int RxStatus; /* 0x20454 */
292 volatile unsigned int StationMgmtData; /* 0x20458 */
293 volatile unsigned int StationMgmtCtl; /* 0x2045c */
294 volatile unsigned int CamAddress; /* 0x20460 */
295 volatile unsigned int CamData; /* 0x20464 */
296 volatile unsigned int CamEnable; /* 0x20468 */
297 volatile unsigned char filler2046c[0x20500 - 0x2046c];
298 volatile unsigned int DebugPCIMasterAddr; /* 0x20500 */
299 volatile unsigned int DebugLanTxStateMachine; /* 0x20504 */
300 volatile unsigned int DebugLanRxStateMachine; /* 0x20508 */
301 volatile unsigned int DebugLanTxFifoPointers; /* 0x2050c */
302 volatile unsigned int DebugLanRxFifoPointers; /* 0x20510 */
303 volatile unsigned int DebugLanCtlStateMachine; /* 0x20514 */
304};
305typedef volatile struct lan_saa9730_regmap t_lan_saa9730_regmap;
306
307
308/* EVM interrupt control registers. */
309#define EVM_LAN_INT 0x00010000
310#define EVM_MASTER_EN 0x00000001
311
312/* The SAA9730 (EVM) controller register map, as seen via the PCI-bus. */
313#define SAA9730_EVM_REGS_ADDR 0x02000
314#define SAA9730_EVM_REGS_SIZE 0x00400
315
316struct evm_saa9730_regmap {
317 volatile unsigned int InterruptStatus1; /* 0x2000 */
318 volatile unsigned int InterruptEnable1; /* 0x2004 */
319 volatile unsigned int InterruptMonitor1; /* 0x2008 */
320 volatile unsigned int Counter; /* 0x200c */
321 volatile unsigned int CounterThreshold; /* 0x2010 */
322 volatile unsigned int CounterControl; /* 0x2014 */
323 volatile unsigned int GpioControl1; /* 0x2018 */
324 volatile unsigned int InterruptStatus2; /* 0x201c */
325 volatile unsigned int InterruptEnable2; /* 0x2020 */
326 volatile unsigned int InterruptMonitor2; /* 0x2024 */
327 volatile unsigned int GpioControl2; /* 0x2028 */
328 volatile unsigned int InterruptBlock1; /* 0x202c */
329 volatile unsigned int InterruptBlock2; /* 0x2030 */
330};
331typedef volatile struct evm_saa9730_regmap t_evm_saa9730_regmap;
332
333
334struct lan_saa9730_private {
335 /*
336 * Rx/Tx packet buffers.
337 * The Rx and Tx packets must be PACKET_SIZE aligned.
338 */
339 void *buffer_start;
340 unsigned int buffer_size;
341
342 /*
343 * DMA address of beginning of this object, returned
344 * by pci_alloc_consistent().
345 */
346 dma_addr_t dma_addr;
347
348 /* Pointer to the associated pci device structure */
349 struct pci_dev *pci_dev;
350
351 /* Pointer for the SAA9730 LAN controller register set. */
352 t_lan_saa9730_regmap *lan_saa9730_regs;
353
354 /* Pointer to the SAA9730 EVM register. */
355 t_evm_saa9730_regmap *evm_saa9730_regs;
356
357 /* Rcv buffer Index. */
358 unsigned char NextRcvPacketIndex;
359 /* Next buffer index. */
360 unsigned char NextRcvBufferIndex;
361
362 /* Index of next packet to use in that buffer. */
363 unsigned char NextTxmPacketIndex;
364 /* Next buffer index. */
365 unsigned char NextTxmBufferIndex;
366
367 /* Index of first pending packet ready to send. */
368 unsigned char PendingTxmPacketIndex;
369 /* Pending buffer index. */
370 unsigned char PendingTxmBufferIndex;
371
372 unsigned char DmaRcvPackets;
373 unsigned char DmaTxmPackets;
374
375 void *TxmBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_TXM_Q_SIZE];
376 void *RcvBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_RCV_Q_SIZE];
377 unsigned int TxBufferFree[LAN_SAA9730_BUFFERS];
378
379 unsigned char PhysicalAddress[LAN_SAA9730_CAM_ENTRIES][6];
380
381 spinlock_t lock;
382};
383
384#endif /* _SAA9730_H */
diff --git a/drivers/net/sb1250-mac.c b/drivers/net/sb1250-mac.c
index 33bb18f810fb..fe41e4ec21ec 100644
--- a/drivers/net/sb1250-mac.c
+++ b/drivers/net/sb1250-mac.c
@@ -1064,7 +1064,7 @@ static void sbmac_netpoll(struct net_device *netdev)
1064 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), 1064 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1065 sc->sbm_imr); 1065 sc->sbm_imr);
1066#else 1066#else
1067 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1067 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1068 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); 1068 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1069#endif 1069#endif
1070} 1070}
diff --git a/drivers/net/sfc/Kconfig b/drivers/net/sfc/Kconfig
index dbad95c295bd..3be13b592b4d 100644
--- a/drivers/net/sfc/Kconfig
+++ b/drivers/net/sfc/Kconfig
@@ -4,6 +4,8 @@ config SFC
4 select MII 4 select MII
5 select INET_LRO 5 select INET_LRO
6 select CRC32 6 select CRC32
7 select I2C
8 select I2C_ALGOBIT
7 help 9 help
8 This driver supports 10-gigabit Ethernet cards based on 10 This driver supports 10-gigabit Ethernet cards based on
9 the Solarflare Communications Solarstorm SFC4000 controller. 11 the Solarflare Communications Solarstorm SFC4000 controller.
diff --git a/drivers/net/sfc/Makefile b/drivers/net/sfc/Makefile
index 1d2daeec7ac1..c8f5704c8fb1 100644
--- a/drivers/net/sfc/Makefile
+++ b/drivers/net/sfc/Makefile
@@ -1,5 +1,5 @@
1sfc-y += efx.o falcon.o tx.o rx.o falcon_xmac.o \ 1sfc-y += efx.o falcon.o tx.o rx.o falcon_xmac.o \
2 i2c-direct.o selftest.o ethtool.o xfp_phy.o \ 2 selftest.o ethtool.o xfp_phy.o \
3 mdio_10g.o tenxpress.o boards.o sfe4001.o 3 mdio_10g.o tenxpress.o boards.o sfe4001.o
4 4
5obj-$(CONFIG_SFC) += sfc.o 5obj-$(CONFIG_SFC) += sfc.o
diff --git a/drivers/net/sfc/boards.c b/drivers/net/sfc/boards.c
index 7fc0328dc055..d3d3dd0a1170 100644
--- a/drivers/net/sfc/boards.c
+++ b/drivers/net/sfc/boards.c
@@ -109,7 +109,7 @@ static struct efx_board_data board_data[] = {
109 [EFX_BOARD_INVALID] = 109 [EFX_BOARD_INVALID] =
110 {NULL, NULL, dummy_init}, 110 {NULL, NULL, dummy_init},
111 [EFX_BOARD_SFE4001] = 111 [EFX_BOARD_SFE4001] =
112 {"SFE4001", "10GBASE-T adapter", sfe4001_poweron}, 112 {"SFE4001", "10GBASE-T adapter", sfe4001_init},
113 [EFX_BOARD_SFE4002] = 113 [EFX_BOARD_SFE4002] =
114 {"SFE4002", "XFP adapter", sfe4002_init}, 114 {"SFE4002", "XFP adapter", sfe4002_init},
115}; 115};
diff --git a/drivers/net/sfc/boards.h b/drivers/net/sfc/boards.h
index 695764dc2e64..e5e844359ce7 100644
--- a/drivers/net/sfc/boards.h
+++ b/drivers/net/sfc/boards.h
@@ -20,8 +20,7 @@ enum efx_board_type {
20}; 20};
21 21
22extern int efx_set_board_info(struct efx_nic *efx, u16 revision_info); 22extern int efx_set_board_info(struct efx_nic *efx, u16 revision_info);
23extern int sfe4001_poweron(struct efx_nic *efx); 23extern int sfe4001_init(struct efx_nic *efx);
24extern void sfe4001_poweroff(struct efx_nic *efx);
25/* Are we putting the PHY into flash config mode */ 24/* Are we putting the PHY into flash config mode */
26extern unsigned int sfe4001_phy_flash_cfg; 25extern unsigned int sfe4001_phy_flash_cfg;
27 26
diff --git a/drivers/net/sfc/efx.c b/drivers/net/sfc/efx.c
index 449760642e31..7b2015f9e469 100644
--- a/drivers/net/sfc/efx.c
+++ b/drivers/net/sfc/efx.c
@@ -696,8 +696,8 @@ static void efx_stop_port(struct efx_nic *efx)
696 696
697 /* Serialise against efx_set_multicast_list() */ 697 /* Serialise against efx_set_multicast_list() */
698 if (efx_dev_registered(efx)) { 698 if (efx_dev_registered(efx)) {
699 netif_tx_lock_bh(efx->net_dev); 699 netif_addr_lock_bh(efx->net_dev);
700 netif_tx_unlock_bh(efx->net_dev); 700 netif_addr_unlock_bh(efx->net_dev);
701 } 701 }
702} 702}
703 703
@@ -1815,6 +1815,7 @@ static struct efx_board efx_dummy_board_info = {
1815 .init = efx_nic_dummy_op_int, 1815 .init = efx_nic_dummy_op_int,
1816 .init_leds = efx_port_dummy_op_int, 1816 .init_leds = efx_port_dummy_op_int,
1817 .set_fault_led = efx_port_dummy_op_blink, 1817 .set_fault_led = efx_port_dummy_op_blink,
1818 .fini = efx_port_dummy_op_void,
1818}; 1819};
1819 1820
1820/************************************************************************** 1821/**************************************************************************
@@ -1941,6 +1942,7 @@ static void efx_pci_remove_main(struct efx_nic *efx)
1941 efx_fini_port(efx); 1942 efx_fini_port(efx);
1942 1943
1943 /* Shutdown the board, then the NIC and board state */ 1944 /* Shutdown the board, then the NIC and board state */
1945 efx->board_info.fini(efx);
1944 falcon_fini_interrupt(efx); 1946 falcon_fini_interrupt(efx);
1945 1947
1946 efx_fini_napi(efx); 1948 efx_fini_napi(efx);
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index 790db89db345..630406e142e5 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -13,6 +13,8 @@
13#include <linux/pci.h> 13#include <linux/pci.h>
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/seq_file.h> 15#include <linux/seq_file.h>
16#include <linux/i2c.h>
17#include <linux/i2c-algo-bit.h>
16#include "net_driver.h" 18#include "net_driver.h"
17#include "bitfield.h" 19#include "bitfield.h"
18#include "efx.h" 20#include "efx.h"
@@ -36,10 +38,12 @@
36 * struct falcon_nic_data - Falcon NIC state 38 * struct falcon_nic_data - Falcon NIC state
37 * @next_buffer_table: First available buffer table id 39 * @next_buffer_table: First available buffer table id
38 * @pci_dev2: The secondary PCI device if present 40 * @pci_dev2: The secondary PCI device if present
41 * @i2c_data: Operations and state for I2C bit-bashing algorithm
39 */ 42 */
40struct falcon_nic_data { 43struct falcon_nic_data {
41 unsigned next_buffer_table; 44 unsigned next_buffer_table;
42 struct pci_dev *pci_dev2; 45 struct pci_dev *pci_dev2;
46 struct i2c_algo_bit_data i2c_data;
43}; 47};
44 48
45/************************************************************************** 49/**************************************************************************
@@ -175,39 +179,57 @@ static inline int falcon_event_present(efx_qword_t *event)
175 * 179 *
176 ************************************************************************** 180 **************************************************************************
177 */ 181 */
178static void falcon_setsdascl(struct efx_i2c_interface *i2c) 182static void falcon_setsda(void *data, int state)
179{ 183{
184 struct efx_nic *efx = (struct efx_nic *)data;
180 efx_oword_t reg; 185 efx_oword_t reg;
181 186
182 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER); 187 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
183 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, (i2c->scl ? 0 : 1)); 188 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
184 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, (i2c->sda ? 0 : 1)); 189 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
185 falcon_write(i2c->efx, &reg, GPIO_CTL_REG_KER);
186} 190}
187 191
188static int falcon_getsda(struct efx_i2c_interface *i2c) 192static void falcon_setscl(void *data, int state)
189{ 193{
194 struct efx_nic *efx = (struct efx_nic *)data;
190 efx_oword_t reg; 195 efx_oword_t reg;
191 196
192 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER); 197 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
198 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
199 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
200}
201
202static int falcon_getsda(void *data)
203{
204 struct efx_nic *efx = (struct efx_nic *)data;
205 efx_oword_t reg;
206
207 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
193 return EFX_OWORD_FIELD(reg, GPIO3_IN); 208 return EFX_OWORD_FIELD(reg, GPIO3_IN);
194} 209}
195 210
196static int falcon_getscl(struct efx_i2c_interface *i2c) 211static int falcon_getscl(void *data)
197{ 212{
213 struct efx_nic *efx = (struct efx_nic *)data;
198 efx_oword_t reg; 214 efx_oword_t reg;
199 215
200 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER); 216 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
201 return EFX_DWORD_FIELD(reg, GPIO0_IN); 217 return EFX_OWORD_FIELD(reg, GPIO0_IN);
202} 218}
203 219
204static struct efx_i2c_bit_operations falcon_i2c_bit_operations = { 220static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
205 .setsda = falcon_setsdascl, 221 .setsda = falcon_setsda,
206 .setscl = falcon_setsdascl, 222 .setscl = falcon_setscl,
207 .getsda = falcon_getsda, 223 .getsda = falcon_getsda,
208 .getscl = falcon_getscl, 224 .getscl = falcon_getscl,
209 .udelay = 100, 225 .udelay = 5,
210 .mdelay = 10, 226 /*
227 * This is the number of system clock ticks after which
228 * i2c-algo-bit gives up waiting for SCL to become high.
229 * It must be at least 2 since the first tick can happen
230 * immediately after it starts waiting.
231 */
232 .timeout = 2,
211}; 233};
212 234
213/************************************************************************** 235/**************************************************************************
@@ -2405,12 +2427,6 @@ int falcon_probe_nic(struct efx_nic *efx)
2405 struct falcon_nic_data *nic_data; 2427 struct falcon_nic_data *nic_data;
2406 int rc; 2428 int rc;
2407 2429
2408 /* Initialise I2C interface state */
2409 efx->i2c.efx = efx;
2410 efx->i2c.op = &falcon_i2c_bit_operations;
2411 efx->i2c.sda = 1;
2412 efx->i2c.scl = 1;
2413
2414 /* Allocate storage for hardware specific data */ 2430 /* Allocate storage for hardware specific data */
2415 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 2431 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2416 efx->nic_data = nic_data; 2432 efx->nic_data = nic_data;
@@ -2461,6 +2477,18 @@ int falcon_probe_nic(struct efx_nic *efx)
2461 if (rc) 2477 if (rc)
2462 goto fail5; 2478 goto fail5;
2463 2479
2480 /* Initialise I2C adapter */
2481 efx->i2c_adap.owner = THIS_MODULE;
2482 efx->i2c_adap.class = I2C_CLASS_HWMON;
2483 nic_data->i2c_data = falcon_i2c_bit_operations;
2484 nic_data->i2c_data.data = efx;
2485 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2486 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2487 strcpy(efx->i2c_adap.name, "SFC4000 GPIO");
2488 rc = i2c_bit_add_bus(&efx->i2c_adap);
2489 if (rc)
2490 goto fail5;
2491
2464 return 0; 2492 return 0;
2465 2493
2466 fail5: 2494 fail5:
@@ -2635,6 +2663,10 @@ int falcon_init_nic(struct efx_nic *efx)
2635void falcon_remove_nic(struct efx_nic *efx) 2663void falcon_remove_nic(struct efx_nic *efx)
2636{ 2664{
2637 struct falcon_nic_data *nic_data = efx->nic_data; 2665 struct falcon_nic_data *nic_data = efx->nic_data;
2666 int rc;
2667
2668 rc = i2c_del_adapter(&efx->i2c_adap);
2669 BUG_ON(rc);
2638 2670
2639 falcon_free_buffer(efx, &efx->irq_status); 2671 falcon_free_buffer(efx, &efx->irq_status);
2640 2672
diff --git a/drivers/net/sfc/i2c-direct.c b/drivers/net/sfc/i2c-direct.c
deleted file mode 100644
index b6c62d0ed9c2..000000000000
--- a/drivers/net/sfc/i2c-direct.c
+++ /dev/null
@@ -1,381 +0,0 @@
1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/delay.h>
12#include "net_driver.h"
13#include "i2c-direct.h"
14
15/*
16 * I2C data (SDA) and clock (SCL) line read/writes with appropriate
17 * delays.
18 */
19
20static inline void setsda(struct efx_i2c_interface *i2c, int state)
21{
22 udelay(i2c->op->udelay);
23 i2c->sda = state;
24 i2c->op->setsda(i2c);
25 udelay(i2c->op->udelay);
26}
27
28static inline void setscl(struct efx_i2c_interface *i2c, int state)
29{
30 udelay(i2c->op->udelay);
31 i2c->scl = state;
32 i2c->op->setscl(i2c);
33 udelay(i2c->op->udelay);
34}
35
36static inline int getsda(struct efx_i2c_interface *i2c)
37{
38 int sda;
39
40 udelay(i2c->op->udelay);
41 sda = i2c->op->getsda(i2c);
42 udelay(i2c->op->udelay);
43 return sda;
44}
45
46static inline int getscl(struct efx_i2c_interface *i2c)
47{
48 int scl;
49
50 udelay(i2c->op->udelay);
51 scl = i2c->op->getscl(i2c);
52 udelay(i2c->op->udelay);
53 return scl;
54}
55
56/*
57 * I2C low-level protocol operations
58 *
59 */
60
61static inline void i2c_release(struct efx_i2c_interface *i2c)
62{
63 EFX_WARN_ON_PARANOID(!i2c->scl);
64 EFX_WARN_ON_PARANOID(!i2c->sda);
65 /* Devices may time out if operations do not end */
66 setscl(i2c, 1);
67 setsda(i2c, 1);
68 EFX_BUG_ON_PARANOID(getsda(i2c) != 1);
69 EFX_BUG_ON_PARANOID(getscl(i2c) != 1);
70}
71
72static inline void i2c_start(struct efx_i2c_interface *i2c)
73{
74 /* We may be restarting immediately after a {send,recv}_bit,
75 * so SCL will not necessarily already be high.
76 */
77 EFX_WARN_ON_PARANOID(!i2c->sda);
78 setscl(i2c, 1);
79 setsda(i2c, 0);
80 setscl(i2c, 0);
81 setsda(i2c, 1);
82}
83
84static inline void i2c_send_bit(struct efx_i2c_interface *i2c, int bit)
85{
86 EFX_WARN_ON_PARANOID(i2c->scl != 0);
87 setsda(i2c, bit);
88 setscl(i2c, 1);
89 setscl(i2c, 0);
90 setsda(i2c, 1);
91}
92
93static inline int i2c_recv_bit(struct efx_i2c_interface *i2c)
94{
95 int bit;
96
97 EFX_WARN_ON_PARANOID(i2c->scl != 0);
98 EFX_WARN_ON_PARANOID(!i2c->sda);
99 setscl(i2c, 1);
100 bit = getsda(i2c);
101 setscl(i2c, 0);
102 return bit;
103}
104
105static inline void i2c_stop(struct efx_i2c_interface *i2c)
106{
107 EFX_WARN_ON_PARANOID(i2c->scl != 0);
108 setsda(i2c, 0);
109 setscl(i2c, 1);
110 setsda(i2c, 1);
111}
112
113/*
114 * I2C mid-level protocol operations
115 *
116 */
117
118/* Sends a byte via the I2C bus and checks for an acknowledgement from
119 * the slave device.
120 */
121static int i2c_send_byte(struct efx_i2c_interface *i2c, u8 byte)
122{
123 int i;
124
125 /* Send byte */
126 for (i = 0; i < 8; i++) {
127 i2c_send_bit(i2c, !!(byte & 0x80));
128 byte <<= 1;
129 }
130
131 /* Check for acknowledgement from slave */
132 return (i2c_recv_bit(i2c) == 0 ? 0 : -EIO);
133}
134
135/* Receives a byte via the I2C bus and sends ACK/NACK to the slave device. */
136static u8 i2c_recv_byte(struct efx_i2c_interface *i2c, int ack)
137{
138 u8 value = 0;
139 int i;
140
141 /* Receive byte */
142 for (i = 0; i < 8; i++)
143 value = (value << 1) | i2c_recv_bit(i2c);
144
145 /* Send ACK/NACK */
146 i2c_send_bit(i2c, (ack ? 0 : 1));
147
148 return value;
149}
150
151/* Calculate command byte for a read operation */
152static inline u8 i2c_read_cmd(u8 device_id)
153{
154 return ((device_id << 1) | 1);
155}
156
157/* Calculate command byte for a write operation */
158static inline u8 i2c_write_cmd(u8 device_id)
159{
160 return ((device_id << 1) | 0);
161}
162
163int efx_i2c_check_presence(struct efx_i2c_interface *i2c, u8 device_id)
164{
165 int rc;
166
167 /* If someone is driving the bus low we just give up. */
168 if (getsda(i2c) == 0 || getscl(i2c) == 0) {
169 EFX_ERR(i2c->efx, "%s someone is holding the I2C bus low."
170 " Giving up.\n", __func__);
171 return -EFAULT;
172 }
173
174 /* Pretend to initiate a device write */
175 i2c_start(i2c);
176 rc = i2c_send_byte(i2c, i2c_write_cmd(device_id));
177 if (rc)
178 goto out;
179
180 out:
181 i2c_stop(i2c);
182 i2c_release(i2c);
183
184 return rc;
185}
186
187/* This performs a fast read of one or more consecutive bytes from an
188 * I2C device. Not all devices support consecutive reads of more than
189 * one byte; for these devices use efx_i2c_read() instead.
190 */
191int efx_i2c_fast_read(struct efx_i2c_interface *i2c,
192 u8 device_id, u8 offset, u8 *data, unsigned int len)
193{
194 int i;
195 int rc;
196
197 EFX_WARN_ON_PARANOID(getsda(i2c) != 1);
198 EFX_WARN_ON_PARANOID(getscl(i2c) != 1);
199 EFX_WARN_ON_PARANOID(data == NULL);
200 EFX_WARN_ON_PARANOID(len < 1);
201
202 /* Select device and starting offset */
203 i2c_start(i2c);
204 rc = i2c_send_byte(i2c, i2c_write_cmd(device_id));
205 if (rc)
206 goto out;
207 rc = i2c_send_byte(i2c, offset);
208 if (rc)
209 goto out;
210
211 /* Read data from device */
212 i2c_start(i2c);
213 rc = i2c_send_byte(i2c, i2c_read_cmd(device_id));
214 if (rc)
215 goto out;
216 for (i = 0; i < (len - 1); i++)
217 /* Read and acknowledge all but the last byte */
218 data[i] = i2c_recv_byte(i2c, 1);
219 /* Read last byte with no acknowledgement */
220 data[i] = i2c_recv_byte(i2c, 0);
221
222 out:
223 i2c_stop(i2c);
224 i2c_release(i2c);
225
226 return rc;
227}
228
229/* This performs a fast write of one or more consecutive bytes to an
230 * I2C device. Not all devices support consecutive writes of more
231 * than one byte; for these devices use efx_i2c_write() instead.
232 */
233int efx_i2c_fast_write(struct efx_i2c_interface *i2c,
234 u8 device_id, u8 offset,
235 const u8 *data, unsigned int len)
236{
237 int i;
238 int rc;
239
240 EFX_WARN_ON_PARANOID(getsda(i2c) != 1);
241 EFX_WARN_ON_PARANOID(getscl(i2c) != 1);
242 EFX_WARN_ON_PARANOID(len < 1);
243
244 /* Select device and starting offset */
245 i2c_start(i2c);
246 rc = i2c_send_byte(i2c, i2c_write_cmd(device_id));
247 if (rc)
248 goto out;
249 rc = i2c_send_byte(i2c, offset);
250 if (rc)
251 goto out;
252
253 /* Write data to device */
254 for (i = 0; i < len; i++) {
255 rc = i2c_send_byte(i2c, data[i]);
256 if (rc)
257 goto out;
258 }
259
260 out:
261 i2c_stop(i2c);
262 i2c_release(i2c);
263
264 return rc;
265}
266
267/* I2C byte-by-byte read */
268int efx_i2c_read(struct efx_i2c_interface *i2c,
269 u8 device_id, u8 offset, u8 *data, unsigned int len)
270{
271 int rc;
272
273 /* i2c_fast_read with length 1 is a single byte read */
274 for (; len > 0; offset++, data++, len--) {
275 rc = efx_i2c_fast_read(i2c, device_id, offset, data, 1);
276 if (rc)
277 return rc;
278 }
279
280 return 0;
281}
282
283/* I2C byte-by-byte write */
284int efx_i2c_write(struct efx_i2c_interface *i2c,
285 u8 device_id, u8 offset, const u8 *data, unsigned int len)
286{
287 int rc;
288
289 /* i2c_fast_write with length 1 is a single byte write */
290 for (; len > 0; offset++, data++, len--) {
291 rc = efx_i2c_fast_write(i2c, device_id, offset, data, 1);
292 if (rc)
293 return rc;
294 mdelay(i2c->op->mdelay);
295 }
296
297 return 0;
298}
299
300
301/* This is just a slightly neater wrapper round efx_i2c_fast_write
302 * in the case where the target doesn't take an offset
303 */
304int efx_i2c_send_bytes(struct efx_i2c_interface *i2c,
305 u8 device_id, const u8 *data, unsigned int len)
306{
307 return efx_i2c_fast_write(i2c, device_id, data[0], data + 1, len - 1);
308}
309
310/* I2C receiving of bytes - does not send an offset byte */
311int efx_i2c_recv_bytes(struct efx_i2c_interface *i2c, u8 device_id,
312 u8 *bytes, unsigned int len)
313{
314 int i;
315 int rc;
316
317 EFX_WARN_ON_PARANOID(getsda(i2c) != 1);
318 EFX_WARN_ON_PARANOID(getscl(i2c) != 1);
319 EFX_WARN_ON_PARANOID(len < 1);
320
321 /* Select device */
322 i2c_start(i2c);
323
324 /* Read data from device */
325 rc = i2c_send_byte(i2c, i2c_read_cmd(device_id));
326 if (rc)
327 goto out;
328
329 for (i = 0; i < (len - 1); i++)
330 /* Read and acknowledge all but the last byte */
331 bytes[i] = i2c_recv_byte(i2c, 1);
332 /* Read last byte with no acknowledgement */
333 bytes[i] = i2c_recv_byte(i2c, 0);
334
335 out:
336 i2c_stop(i2c);
337 i2c_release(i2c);
338
339 return rc;
340}
341
342/* SMBus and some I2C devices will time out if the I2C clock is
343 * held low for too long. This is most likely to happen in virtualised
344 * systems (when the entire domain is descheduled) but could in
345 * principle happen due to preemption on any busy system (and given the
346 * potential length of an I2C operation turning preemption off is not
347 * a sensible option). The following functions deal with the failure by
348 * retrying up to a fixed number of times.
349 */
350
351#define I2C_MAX_RETRIES (10)
352
353/* The timeout problem will result in -EIO. If the wrapped function
354 * returns any other error, pass this up and do not retry. */
355#define RETRY_WRAPPER(_f) \
356 int retries = I2C_MAX_RETRIES; \
357 int rc; \
358 while (retries) { \
359 rc = _f; \
360 if (rc != -EIO) \
361 return rc; \
362 retries--; \
363 } \
364 return rc; \
365
366int efx_i2c_check_presence_retry(struct efx_i2c_interface *i2c, u8 device_id)
367{
368 RETRY_WRAPPER(efx_i2c_check_presence(i2c, device_id))
369}
370
371int efx_i2c_read_retry(struct efx_i2c_interface *i2c,
372 u8 device_id, u8 offset, u8 *data, unsigned int len)
373{
374 RETRY_WRAPPER(efx_i2c_read(i2c, device_id, offset, data, len))
375}
376
377int efx_i2c_write_retry(struct efx_i2c_interface *i2c,
378 u8 device_id, u8 offset, const u8 *data, unsigned int len)
379{
380 RETRY_WRAPPER(efx_i2c_write(i2c, device_id, offset, data, len))
381}
diff --git a/drivers/net/sfc/i2c-direct.h b/drivers/net/sfc/i2c-direct.h
deleted file mode 100644
index 291e561071f5..000000000000
--- a/drivers/net/sfc/i2c-direct.h
+++ /dev/null
@@ -1,91 +0,0 @@
1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005 Fen Systems Ltd.
4 * Copyright 2006 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef EFX_I2C_DIRECT_H
12#define EFX_I2C_DIRECT_H
13
14#include "net_driver.h"
15
16/*
17 * Direct control of an I2C bus
18 */
19
20struct efx_i2c_interface;
21
22/**
23 * struct efx_i2c_bit_operations - I2C bus direct control methods
24 *
25 * I2C bus direct control methods.
26 *
27 * @setsda: Set state of SDA line
28 * @setscl: Set state of SCL line
29 * @getsda: Get state of SDA line
30 * @getscl: Get state of SCL line
31 * @udelay: Delay between each bit operation
32 * @mdelay: Delay between each byte write
33 */
34struct efx_i2c_bit_operations {
35 void (*setsda) (struct efx_i2c_interface *i2c);
36 void (*setscl) (struct efx_i2c_interface *i2c);
37 int (*getsda) (struct efx_i2c_interface *i2c);
38 int (*getscl) (struct efx_i2c_interface *i2c);
39 unsigned int udelay;
40 unsigned int mdelay;
41};
42
43/**
44 * struct efx_i2c_interface - an I2C interface
45 *
46 * An I2C interface.
47 *
48 * @efx: Attached Efx NIC
49 * @op: I2C bus control methods
50 * @sda: Current output state of SDA line
51 * @scl: Current output state of SCL line
52 */
53struct efx_i2c_interface {
54 struct efx_nic *efx;
55 struct efx_i2c_bit_operations *op;
56 unsigned int sda:1;
57 unsigned int scl:1;
58};
59
60extern int efx_i2c_check_presence(struct efx_i2c_interface *i2c, u8 device_id);
61extern int efx_i2c_fast_read(struct efx_i2c_interface *i2c,
62 u8 device_id, u8 offset,
63 u8 *data, unsigned int len);
64extern int efx_i2c_fast_write(struct efx_i2c_interface *i2c,
65 u8 device_id, u8 offset,
66 const u8 *data, unsigned int len);
67extern int efx_i2c_read(struct efx_i2c_interface *i2c,
68 u8 device_id, u8 offset, u8 *data, unsigned int len);
69extern int efx_i2c_write(struct efx_i2c_interface *i2c,
70 u8 device_id, u8 offset,
71 const u8 *data, unsigned int len);
72
73extern int efx_i2c_send_bytes(struct efx_i2c_interface *i2c, u8 device_id,
74 const u8 *bytes, unsigned int len);
75
76extern int efx_i2c_recv_bytes(struct efx_i2c_interface *i2c, u8 device_id,
77 u8 *bytes, unsigned int len);
78
79
80/* Versions of the API that retry on failure. */
81extern int efx_i2c_check_presence_retry(struct efx_i2c_interface *i2c,
82 u8 device_id);
83
84extern int efx_i2c_read_retry(struct efx_i2c_interface *i2c,
85 u8 device_id, u8 offset, u8 *data, unsigned int len);
86
87extern int efx_i2c_write_retry(struct efx_i2c_interface *i2c,
88 u8 device_id, u8 offset,
89 const u8 *data, unsigned int len);
90
91#endif /* EFX_I2C_DIRECT_H */
diff --git a/drivers/net/sfc/net_driver.h b/drivers/net/sfc/net_driver.h
index 5e20e7551dae..d803b86c647c 100644
--- a/drivers/net/sfc/net_driver.h
+++ b/drivers/net/sfc/net_driver.h
@@ -26,10 +26,10 @@
26#include <linux/highmem.h> 26#include <linux/highmem.h>
27#include <linux/workqueue.h> 27#include <linux/workqueue.h>
28#include <linux/inet_lro.h> 28#include <linux/inet_lro.h>
29#include <linux/i2c.h>
29 30
30#include "enum.h" 31#include "enum.h"
31#include "bitfield.h" 32#include "bitfield.h"
32#include "i2c-direct.h"
33 33
34#define EFX_MAX_LRO_DESCRIPTORS 8 34#define EFX_MAX_LRO_DESCRIPTORS 8
35#define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS 35#define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS
@@ -418,7 +418,10 @@ struct efx_blinker {
418 * @init_leds: Sets up board LEDs 418 * @init_leds: Sets up board LEDs
419 * @set_fault_led: Turns the fault LED on or off 419 * @set_fault_led: Turns the fault LED on or off
420 * @blink: Starts/stops blinking 420 * @blink: Starts/stops blinking
421 * @fini: Cleanup function
421 * @blinker: used to blink LEDs in software 422 * @blinker: used to blink LEDs in software
423 * @hwmon_client: I2C client for hardware monitor
424 * @ioexp_client: I2C client for power/port control
422 */ 425 */
423struct efx_board { 426struct efx_board {
424 int type; 427 int type;
@@ -431,7 +434,9 @@ struct efx_board {
431 int (*init_leds)(struct efx_nic *efx); 434 int (*init_leds)(struct efx_nic *efx);
432 void (*set_fault_led) (struct efx_nic *efx, int state); 435 void (*set_fault_led) (struct efx_nic *efx, int state);
433 void (*blink) (struct efx_nic *efx, int start); 436 void (*blink) (struct efx_nic *efx, int start);
437 void (*fini) (struct efx_nic *nic);
434 struct efx_blinker blinker; 438 struct efx_blinker blinker;
439 struct i2c_client *hwmon_client, *ioexp_client;
435}; 440};
436 441
437#define STRING_TABLE_LOOKUP(val, member) \ 442#define STRING_TABLE_LOOKUP(val, member) \
@@ -618,7 +623,7 @@ union efx_multicast_hash {
618 * @membase: Memory BAR value 623 * @membase: Memory BAR value
619 * @biu_lock: BIU (bus interface unit) lock 624 * @biu_lock: BIU (bus interface unit) lock
620 * @interrupt_mode: Interrupt mode 625 * @interrupt_mode: Interrupt mode
621 * @i2c: I2C interface 626 * @i2c_adap: I2C adapter
622 * @board_info: Board-level information 627 * @board_info: Board-level information
623 * @state: Device state flag. Serialised by the rtnl_lock. 628 * @state: Device state flag. Serialised by the rtnl_lock.
624 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE) 629 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
@@ -686,7 +691,7 @@ struct efx_nic {
686 spinlock_t biu_lock; 691 spinlock_t biu_lock;
687 enum efx_int_mode interrupt_mode; 692 enum efx_int_mode interrupt_mode;
688 693
689 struct efx_i2c_interface i2c; 694 struct i2c_adapter i2c_adap;
690 struct efx_board board_info; 695 struct efx_board board_info;
691 696
692 enum nic_state state; 697 enum nic_state state;
diff --git a/drivers/net/sfc/sfe4001.c b/drivers/net/sfc/sfe4001.c
index 66a0d1442aba..b27849523990 100644
--- a/drivers/net/sfc/sfe4001.c
+++ b/drivers/net/sfc/sfe4001.c
@@ -106,28 +106,27 @@
106 106
107static const u8 xgphy_max_temperature = 90; 107static const u8 xgphy_max_temperature = 90;
108 108
109void sfe4001_poweroff(struct efx_nic *efx) 109static void sfe4001_poweroff(struct efx_nic *efx)
110{ 110{
111 struct efx_i2c_interface *i2c = &efx->i2c; 111 struct i2c_client *ioexp_client = efx->board_info.ioexp_client;
112 struct i2c_client *hwmon_client = efx->board_info.hwmon_client;
112 113
113 u8 cfg, out, in; 114 /* Turn off all power rails and disable outputs */
115 i2c_smbus_write_byte_data(ioexp_client, P0_OUT, 0xff);
116 i2c_smbus_write_byte_data(ioexp_client, P1_CONFIG, 0xff);
117 i2c_smbus_write_byte_data(ioexp_client, P0_CONFIG, 0xff);
114 118
115 EFX_INFO(efx, "%s\n", __func__); 119 /* Clear any over-temperature alert */
116 120 i2c_smbus_read_byte_data(hwmon_client, RSL);
117 /* Turn off all power rails */ 121}
118 out = 0xff;
119 efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1);
120
121 /* Disable port 1 outputs on IO expander */
122 cfg = 0xff;
123 efx_i2c_write(i2c, PCA9539, P1_CONFIG, &cfg, 1);
124 122
125 /* Disable port 0 outputs on IO expander */ 123static void sfe4001_fini(struct efx_nic *efx)
126 cfg = 0xff; 124{
127 efx_i2c_write(i2c, PCA9539, P0_CONFIG, &cfg, 1); 125 EFX_INFO(efx, "%s\n", __func__);
128 126
129 /* Clear any over-temperature alert */ 127 sfe4001_poweroff(efx);
130 efx_i2c_read(i2c, MAX6647, RSL, &in, 1); 128 i2c_unregister_device(efx->board_info.ioexp_client);
129 i2c_unregister_device(efx->board_info.hwmon_client);
131} 130}
132 131
133/* The P0_EN_3V3X line on SFE4001 boards (from A2 onward) is connected 132/* The P0_EN_3V3X line on SFE4001 boards (from A2 onward) is connected
@@ -143,14 +142,26 @@ MODULE_PARM_DESC(phy_flash_cfg,
143 * be turned on before the PHY can be used. 142 * be turned on before the PHY can be used.
144 * Context: Process context, rtnl lock held 143 * Context: Process context, rtnl lock held
145 */ 144 */
146int sfe4001_poweron(struct efx_nic *efx) 145int sfe4001_init(struct efx_nic *efx)
147{ 146{
148 struct efx_i2c_interface *i2c = &efx->i2c; 147 struct i2c_client *hwmon_client, *ioexp_client;
149 unsigned int count; 148 unsigned int count;
150 int rc; 149 int rc;
151 u8 out, in, cfg; 150 u8 out;
152 efx_dword_t reg; 151 efx_dword_t reg;
153 152
153 hwmon_client = i2c_new_dummy(&efx->i2c_adap, MAX6647);
154 if (!hwmon_client)
155 return -EIO;
156 efx->board_info.hwmon_client = hwmon_client;
157
158 ioexp_client = i2c_new_dummy(&efx->i2c_adap, PCA9539);
159 if (!ioexp_client) {
160 rc = -EIO;
161 goto fail_hwmon;
162 }
163 efx->board_info.ioexp_client = ioexp_client;
164
154 /* 10Xpress has fixed-function LED pins, so there is no board-specific 165 /* 10Xpress has fixed-function LED pins, so there is no board-specific
155 * blink code. */ 166 * blink code. */
156 efx->board_info.blink = tenxpress_phy_blink; 167 efx->board_info.blink = tenxpress_phy_blink;
@@ -166,44 +177,45 @@ int sfe4001_poweron(struct efx_nic *efx)
166 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 177 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
167 udelay(10); 178 udelay(10);
168 179
180 efx->board_info.fini = sfe4001_fini;
181
169 /* Set DSP over-temperature alert threshold */ 182 /* Set DSP over-temperature alert threshold */
170 EFX_INFO(efx, "DSP cut-out at %dC\n", xgphy_max_temperature); 183 EFX_INFO(efx, "DSP cut-out at %dC\n", xgphy_max_temperature);
171 rc = efx_i2c_write(i2c, MAX6647, WLHO, 184 rc = i2c_smbus_write_byte_data(hwmon_client, WLHO,
172 &xgphy_max_temperature, 1); 185 xgphy_max_temperature);
173 if (rc) 186 if (rc)
174 goto fail1; 187 goto fail_ioexp;
175 188
176 /* Read it back and verify */ 189 /* Read it back and verify */
177 rc = efx_i2c_read(i2c, MAX6647, RLHN, &in, 1); 190 rc = i2c_smbus_read_byte_data(hwmon_client, RLHN);
178 if (rc) 191 if (rc < 0)
179 goto fail1; 192 goto fail_ioexp;
180 if (in != xgphy_max_temperature) { 193 if (rc != xgphy_max_temperature) {
181 rc = -EFAULT; 194 rc = -EFAULT;
182 goto fail1; 195 goto fail_ioexp;
183 } 196 }
184 197
185 /* Clear any previous over-temperature alert */ 198 /* Clear any previous over-temperature alert */
186 rc = efx_i2c_read(i2c, MAX6647, RSL, &in, 1); 199 rc = i2c_smbus_read_byte_data(hwmon_client, RSL);
187 if (rc) 200 if (rc < 0)
188 goto fail1; 201 goto fail_ioexp;
189 202
190 /* Enable port 0 and port 1 outputs on IO expander */ 203 /* Enable port 0 and port 1 outputs on IO expander */
191 cfg = 0x00; 204 rc = i2c_smbus_write_byte_data(ioexp_client, P0_CONFIG, 0x00);
192 rc = efx_i2c_write(i2c, PCA9539, P0_CONFIG, &cfg, 1);
193 if (rc) 205 if (rc)
194 goto fail1; 206 goto fail_ioexp;
195 cfg = 0xff & ~(1 << P1_SPARE_LBN); 207 rc = i2c_smbus_write_byte_data(ioexp_client, P1_CONFIG,
196 rc = efx_i2c_write(i2c, PCA9539, P1_CONFIG, &cfg, 1); 208 0xff & ~(1 << P1_SPARE_LBN));
197 if (rc) 209 if (rc)
198 goto fail2; 210 goto fail_on;
199 211
200 /* Turn all power off then wait 1 sec. This ensures PHY is reset */ 212 /* Turn all power off then wait 1 sec. This ensures PHY is reset */
201 out = 0xff & ~((0 << P0_EN_1V2_LBN) | (0 << P0_EN_2V5_LBN) | 213 out = 0xff & ~((0 << P0_EN_1V2_LBN) | (0 << P0_EN_2V5_LBN) |
202 (0 << P0_EN_3V3X_LBN) | (0 << P0_EN_5V_LBN) | 214 (0 << P0_EN_3V3X_LBN) | (0 << P0_EN_5V_LBN) |
203 (0 << P0_EN_1V0X_LBN)); 215 (0 << P0_EN_1V0X_LBN));
204 rc = efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1); 216 rc = i2c_smbus_write_byte_data(ioexp_client, P0_OUT, out);
205 if (rc) 217 if (rc)
206 goto fail3; 218 goto fail_on;
207 219
208 schedule_timeout_uninterruptible(HZ); 220 schedule_timeout_uninterruptible(HZ);
209 count = 0; 221 count = 0;
@@ -215,26 +227,26 @@ int sfe4001_poweron(struct efx_nic *efx)
215 if (sfe4001_phy_flash_cfg) 227 if (sfe4001_phy_flash_cfg)
216 out |= 1 << P0_EN_3V3X_LBN; 228 out |= 1 << P0_EN_3V3X_LBN;
217 229
218 rc = efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1); 230 rc = i2c_smbus_write_byte_data(ioexp_client, P0_OUT, out);
219 if (rc) 231 if (rc)
220 goto fail3; 232 goto fail_on;
221 msleep(10); 233 msleep(10);
222 234
223 /* Turn on 1V power rail */ 235 /* Turn on 1V power rail */
224 out &= ~(1 << P0_EN_1V0X_LBN); 236 out &= ~(1 << P0_EN_1V0X_LBN);
225 rc = efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1); 237 rc = i2c_smbus_write_byte_data(ioexp_client, P0_OUT, out);
226 if (rc) 238 if (rc)
227 goto fail3; 239 goto fail_on;
228 240
229 EFX_INFO(efx, "waiting for power (attempt %d)...\n", count); 241 EFX_INFO(efx, "waiting for power (attempt %d)...\n", count);
230 242
231 schedule_timeout_uninterruptible(HZ); 243 schedule_timeout_uninterruptible(HZ);
232 244
233 /* Check DSP is powered */ 245 /* Check DSP is powered */
234 rc = efx_i2c_read(i2c, PCA9539, P1_IN, &in, 1); 246 rc = i2c_smbus_read_byte_data(ioexp_client, P1_IN);
235 if (rc) 247 if (rc < 0)
236 goto fail3; 248 goto fail_on;
237 if (in & (1 << P1_AFE_PWD_LBN)) 249 if (rc & (1 << P1_AFE_PWD_LBN))
238 goto done; 250 goto done;
239 251
240 /* DSP doesn't look powered in flash config mode */ 252 /* DSP doesn't look powered in flash config mode */
@@ -244,23 +256,17 @@ int sfe4001_poweron(struct efx_nic *efx)
244 256
245 EFX_INFO(efx, "timed out waiting for power\n"); 257 EFX_INFO(efx, "timed out waiting for power\n");
246 rc = -ETIMEDOUT; 258 rc = -ETIMEDOUT;
247 goto fail3; 259 goto fail_on;
248 260
249done: 261done:
250 EFX_INFO(efx, "PHY is powered on\n"); 262 EFX_INFO(efx, "PHY is powered on\n");
251 return 0; 263 return 0;
252 264
253fail3: 265fail_on:
254 /* Turn off all power rails */ 266 sfe4001_poweroff(efx);
255 out = 0xff; 267fail_ioexp:
256 efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1); 268 i2c_unregister_device(ioexp_client);
257 /* Disable port 1 outputs on IO expander */ 269fail_hwmon:
258 out = 0xff; 270 i2c_unregister_device(hwmon_client);
259 efx_i2c_write(i2c, PCA9539, P1_CONFIG, &out, 1);
260fail2:
261 /* Disable port 0 outputs on IO expander */
262 out = 0xff;
263 efx_i2c_write(i2c, PCA9539, P0_CONFIG, &out, 1);
264fail1:
265 return rc; 271 return rc;
266} 272}
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
new file mode 100644
index 000000000000..a4bc812aa999
--- /dev/null
+++ b/drivers/net/sh_eth.c
@@ -0,0 +1,1174 @@
1/*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006,2007 Nobuhiro Iwamatsu
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23#include <linux/version.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/delay.h>
28#include <linux/platform_device.h>
29#include <linux/mdio-bitbang.h>
30#include <linux/netdevice.h>
31#include <linux/phy.h>
32#include <linux/cache.h>
33#include <linux/io.h>
34
35#include "sh_eth.h"
36
37/*
38 * Program the hardware MAC address from dev->dev_addr.
39 */
40static void update_mac_address(struct net_device *ndev)
41{
42 u32 ioaddr = ndev->base_addr;
43
44 ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
45 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]),
46 ioaddr + MAHR);
47 ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
48 ioaddr + MALR);
49}
50
51/*
52 * Get MAC address from SuperH MAC address register
53 *
54 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
55 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
56 * When you want use this device, you must set MAC address in bootloader.
57 *
58 */
59static void read_mac_address(struct net_device *ndev)
60{
61 u32 ioaddr = ndev->base_addr;
62
63 ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24);
64 ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF;
65 ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF;
66 ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF);
67 ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF;
68 ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF);
69}
70
71struct bb_info {
72 struct mdiobb_ctrl ctrl;
73 u32 addr;
74 u32 mmd_msk;/* MMD */
75 u32 mdo_msk;
76 u32 mdi_msk;
77 u32 mdc_msk;
78};
79
80/* PHY bit set */
81static void bb_set(u32 addr, u32 msk)
82{
83 ctrl_outl(ctrl_inl(addr) | msk, addr);
84}
85
86/* PHY bit clear */
87static void bb_clr(u32 addr, u32 msk)
88{
89 ctrl_outl((ctrl_inl(addr) & ~msk), addr);
90}
91
92/* PHY bit read */
93static int bb_read(u32 addr, u32 msk)
94{
95 return (ctrl_inl(addr) & msk) != 0;
96}
97
98/* Data I/O pin control */
99static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
100{
101 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
102 if (bit)
103 bb_set(bitbang->addr, bitbang->mmd_msk);
104 else
105 bb_clr(bitbang->addr, bitbang->mmd_msk);
106}
107
108/* Set bit data*/
109static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
110{
111 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
112
113 if (bit)
114 bb_set(bitbang->addr, bitbang->mdo_msk);
115 else
116 bb_clr(bitbang->addr, bitbang->mdo_msk);
117}
118
119/* Get bit data*/
120static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
121{
122 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
123 return bb_read(bitbang->addr, bitbang->mdi_msk);
124}
125
126/* MDC pin control */
127static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
128{
129 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
130
131 if (bit)
132 bb_set(bitbang->addr, bitbang->mdc_msk);
133 else
134 bb_clr(bitbang->addr, bitbang->mdc_msk);
135}
136
137/* mdio bus control struct */
138static struct mdiobb_ops bb_ops = {
139 .owner = THIS_MODULE,
140 .set_mdc = sh_mdc_ctrl,
141 .set_mdio_dir = sh_mmd_ctrl,
142 .set_mdio_data = sh_set_mdio,
143 .get_mdio_data = sh_get_mdio,
144};
145
146static void sh_eth_reset(struct net_device *ndev)
147{
148 u32 ioaddr = ndev->base_addr;
149
150 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
151 mdelay(3);
152 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
153}
154
155/* free skb and descriptor buffer */
156static void sh_eth_ring_free(struct net_device *ndev)
157{
158 struct sh_eth_private *mdp = netdev_priv(ndev);
159 int i;
160
161 /* Free Rx skb ringbuffer */
162 if (mdp->rx_skbuff) {
163 for (i = 0; i < RX_RING_SIZE; i++) {
164 if (mdp->rx_skbuff[i])
165 dev_kfree_skb(mdp->rx_skbuff[i]);
166 }
167 }
168 kfree(mdp->rx_skbuff);
169
170 /* Free Tx skb ringbuffer */
171 if (mdp->tx_skbuff) {
172 for (i = 0; i < TX_RING_SIZE; i++) {
173 if (mdp->tx_skbuff[i])
174 dev_kfree_skb(mdp->tx_skbuff[i]);
175 }
176 }
177 kfree(mdp->tx_skbuff);
178}
179
180/* format skb and descriptor buffer */
181static void sh_eth_ring_format(struct net_device *ndev)
182{
183 struct sh_eth_private *mdp = netdev_priv(ndev);
184 int i;
185 struct sk_buff *skb;
186 struct sh_eth_rxdesc *rxdesc = NULL;
187 struct sh_eth_txdesc *txdesc = NULL;
188 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
189 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
190
191 mdp->cur_rx = mdp->cur_tx = 0;
192 mdp->dirty_rx = mdp->dirty_tx = 0;
193
194 memset(mdp->rx_ring, 0, rx_ringsize);
195
196 /* build Rx ring buffer */
197 for (i = 0; i < RX_RING_SIZE; i++) {
198 /* skb */
199 mdp->rx_skbuff[i] = NULL;
200 skb = dev_alloc_skb(mdp->rx_buf_sz);
201 mdp->rx_skbuff[i] = skb;
202 if (skb == NULL)
203 break;
204 skb->dev = ndev; /* Mark as being used by this device. */
205 skb_reserve(skb, RX_OFFSET);
206
207 /* RX descriptor */
208 rxdesc = &mdp->rx_ring[i];
209 rxdesc->addr = (u32)skb->data & ~0x3UL;
210 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
211
212 /* The size of the buffer is 16 byte boundary. */
213 rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F;
214 }
215
216 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
217
218 /* Mark the last entry as wrapping the ring. */
219 rxdesc->status |= cpu_to_le32(RC_RDEL);
220
221 memset(mdp->tx_ring, 0, tx_ringsize);
222
223 /* build Tx ring buffer */
224 for (i = 0; i < TX_RING_SIZE; i++) {
225 mdp->tx_skbuff[i] = NULL;
226 txdesc = &mdp->tx_ring[i];
227 txdesc->status = cpu_to_le32(TD_TFP);
228 txdesc->buffer_length = 0;
229 }
230
231 txdesc->status |= cpu_to_le32(TD_TDLE);
232}
233
234/* Get skb and descriptor buffer */
235static int sh_eth_ring_init(struct net_device *ndev)
236{
237 struct sh_eth_private *mdp = netdev_priv(ndev);
238 int rx_ringsize, tx_ringsize, ret = 0;
239
240 /*
241 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
242 * card needs room to do 8 byte alignment, +2 so we can reserve
243 * the first 2 bytes, and +16 gets room for the status word from the
244 * card.
245 */
246 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
247 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
248
249 /* Allocate RX and TX skb rings */
250 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
251 GFP_KERNEL);
252 if (!mdp->rx_skbuff) {
253 printk(KERN_ERR "%s: Cannot allocate Rx skb\n", ndev->name);
254 ret = -ENOMEM;
255 return ret;
256 }
257
258 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
259 GFP_KERNEL);
260 if (!mdp->tx_skbuff) {
261 printk(KERN_ERR "%s: Cannot allocate Tx skb\n", ndev->name);
262 ret = -ENOMEM;
263 goto skb_ring_free;
264 }
265
266 /* Allocate all Rx descriptors. */
267 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
268 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
269 GFP_KERNEL);
270
271 if (!mdp->rx_ring) {
272 printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n",
273 ndev->name, rx_ringsize);
274 ret = -ENOMEM;
275 goto desc_ring_free;
276 }
277
278 mdp->dirty_rx = 0;
279
280 /* Allocate all Tx descriptors. */
281 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
282 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
283 GFP_KERNEL);
284 if (!mdp->tx_ring) {
285 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
286 ndev->name, tx_ringsize);
287 ret = -ENOMEM;
288 goto desc_ring_free;
289 }
290 return ret;
291
292desc_ring_free:
293 /* free DMA buffer */
294 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
295
296skb_ring_free:
297 /* Free Rx and Tx skb ring buffer */
298 sh_eth_ring_free(ndev);
299
300 return ret;
301}
302
303static int sh_eth_dev_init(struct net_device *ndev)
304{
305 int ret = 0;
306 struct sh_eth_private *mdp = netdev_priv(ndev);
307 u32 ioaddr = ndev->base_addr;
308 u_int32_t rx_int_var, tx_int_var;
309 u32 val;
310
311 /* Soft Reset */
312 sh_eth_reset(ndev);
313
314 ctrl_outl(RPADIR_PADS1, ioaddr + RPADIR); /* SH7712-DMA-RX-PAD2 */
315
316 /* all sh_eth int mask */
317 ctrl_outl(0, ioaddr + EESIPR);
318
319 /* FIFO size set */
320 ctrl_outl(0, ioaddr + EDMR); /* Endian change */
321
322 ctrl_outl((FIFO_SIZE_T | FIFO_SIZE_R), ioaddr + FDR);
323 ctrl_outl(0, ioaddr + TFTR);
324
325 ctrl_outl(0, ioaddr + RMCR);
326
327 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
328 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
329 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
330
331 ctrl_outl((FIFO_F_D_RFF | FIFO_F_D_RFD), ioaddr + FCFTR);
332 ctrl_outl(0, ioaddr + TRIMD);
333
334 /* Descriptor format */
335 sh_eth_ring_format(ndev);
336
337 ctrl_outl((u32)mdp->rx_ring, ioaddr + RDLAR);
338 ctrl_outl((u32)mdp->tx_ring, ioaddr + TDLAR);
339
340 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
341 ctrl_outl((DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff), ioaddr + EESIPR);
342
343 /* PAUSE Prohibition */
344 val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) |
345 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
346
347 ctrl_outl(val, ioaddr + ECMR);
348 ctrl_outl(ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD |
349 ECSIPR_MPDIP, ioaddr + ECSR);
350 ctrl_outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP |
351 ECSIPR_ICDIP | ECSIPR_MPDIP, ioaddr + ECSIPR);
352
353 /* Set MAC address */
354 update_mac_address(ndev);
355
356 /* mask reset */
357#if defined(CONFIG_CPU_SUBTYPE_SH7710)
358 ctrl_outl(APR_AP, ioaddr + APR);
359 ctrl_outl(MPR_MP, ioaddr + MPR);
360 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
361 ctrl_outl(BCFR_UNLIMITED, ioaddr + BCFR);
362#endif
363 /* Setting the Rx mode will start the Rx process. */
364 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
365
366 netif_start_queue(ndev);
367
368 return ret;
369}
370
371/* free Tx skb function */
372static int sh_eth_txfree(struct net_device *ndev)
373{
374 struct sh_eth_private *mdp = netdev_priv(ndev);
375 struct sh_eth_txdesc *txdesc;
376 int freeNum = 0;
377 int entry = 0;
378
379 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
380 entry = mdp->dirty_tx % TX_RING_SIZE;
381 txdesc = &mdp->tx_ring[entry];
382 if (txdesc->status & cpu_to_le32(TD_TACT))
383 break;
384 /* Free the original skb. */
385 if (mdp->tx_skbuff[entry]) {
386 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
387 mdp->tx_skbuff[entry] = NULL;
388 freeNum++;
389 }
390 txdesc->status = cpu_to_le32(TD_TFP);
391 if (entry >= TX_RING_SIZE - 1)
392 txdesc->status |= cpu_to_le32(TD_TDLE);
393
394 mdp->stats.tx_packets++;
395 mdp->stats.tx_bytes += txdesc->buffer_length;
396 }
397 return freeNum;
398}
399
400/* Packet receive function */
401static int sh_eth_rx(struct net_device *ndev)
402{
403 struct sh_eth_private *mdp = netdev_priv(ndev);
404 struct sh_eth_rxdesc *rxdesc;
405
406 int entry = mdp->cur_rx % RX_RING_SIZE;
407 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
408 struct sk_buff *skb;
409 u16 pkt_len = 0;
410 u32 desc_status;
411
412 rxdesc = &mdp->rx_ring[entry];
413 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
414 desc_status = le32_to_cpu(rxdesc->status);
415 pkt_len = rxdesc->frame_length;
416
417 if (--boguscnt < 0)
418 break;
419
420 if (!(desc_status & RDFEND))
421 mdp->stats.rx_length_errors++;
422
423 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
424 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
425 mdp->stats.rx_errors++;
426 if (desc_status & RD_RFS1)
427 mdp->stats.rx_crc_errors++;
428 if (desc_status & RD_RFS2)
429 mdp->stats.rx_frame_errors++;
430 if (desc_status & RD_RFS3)
431 mdp->stats.rx_length_errors++;
432 if (desc_status & RD_RFS4)
433 mdp->stats.rx_length_errors++;
434 if (desc_status & RD_RFS6)
435 mdp->stats.rx_missed_errors++;
436 if (desc_status & RD_RFS10)
437 mdp->stats.rx_over_errors++;
438 } else {
439 swaps((char *)(rxdesc->addr & ~0x3), pkt_len + 2);
440 skb = mdp->rx_skbuff[entry];
441 mdp->rx_skbuff[entry] = NULL;
442 skb_put(skb, pkt_len);
443 skb->protocol = eth_type_trans(skb, ndev);
444 netif_rx(skb);
445 ndev->last_rx = jiffies;
446 mdp->stats.rx_packets++;
447 mdp->stats.rx_bytes += pkt_len;
448 }
449 rxdesc->status |= cpu_to_le32(RD_RACT);
450 entry = (++mdp->cur_rx) % RX_RING_SIZE;
451 }
452
453 /* Refill the Rx ring buffers. */
454 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
455 entry = mdp->dirty_rx % RX_RING_SIZE;
456 rxdesc = &mdp->rx_ring[entry];
457 if (mdp->rx_skbuff[entry] == NULL) {
458 skb = dev_alloc_skb(mdp->rx_buf_sz);
459 mdp->rx_skbuff[entry] = skb;
460 if (skb == NULL)
461 break; /* Better luck next round. */
462 skb->dev = ndev;
463 skb_reserve(skb, RX_OFFSET);
464 rxdesc->addr = (u32)skb->data & ~0x3UL;
465 }
466 /* The size of the buffer is 16 byte boundary. */
467 rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F;
468 if (entry >= RX_RING_SIZE - 1)
469 rxdesc->status |=
470 cpu_to_le32(RD_RACT | RD_RFP | RC_RDEL);
471 else
472 rxdesc->status |=
473 cpu_to_le32(RD_RACT | RD_RFP);
474 }
475
476 /* Restart Rx engine if stopped. */
477 /* If we don't need to check status, don't. -KDU */
478 ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR);
479
480 return 0;
481}
482
483/* error control function */
484static void sh_eth_error(struct net_device *ndev, int intr_status)
485{
486 struct sh_eth_private *mdp = netdev_priv(ndev);
487 u32 ioaddr = ndev->base_addr;
488 u32 felic_stat;
489
490 if (intr_status & EESR_ECI) {
491 felic_stat = ctrl_inl(ioaddr + ECSR);
492 ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */
493 if (felic_stat & ECSR_ICD)
494 mdp->stats.tx_carrier_errors++;
495 if (felic_stat & ECSR_LCHNG) {
496 /* Link Changed */
497 u32 link_stat = (ctrl_inl(ioaddr + PSR));
498 if (!(link_stat & PHY_ST_LINK)) {
499 /* Link Down : disable tx and rx */
500 ctrl_outl(ctrl_inl(ioaddr + ECMR) &
501 ~(ECMR_RE | ECMR_TE), ioaddr + ECMR);
502 } else {
503 /* Link Up */
504 ctrl_outl(ctrl_inl(ioaddr + EESIPR) &
505 ~DMAC_M_ECI, ioaddr + EESIPR);
506 /*clear int */
507 ctrl_outl(ctrl_inl(ioaddr + ECSR),
508 ioaddr + ECSR);
509 ctrl_outl(ctrl_inl(ioaddr + EESIPR) |
510 DMAC_M_ECI, ioaddr + EESIPR);
511 /* enable tx and rx */
512 ctrl_outl(ctrl_inl(ioaddr + ECMR) |
513 (ECMR_RE | ECMR_TE), ioaddr + ECMR);
514 }
515 }
516 }
517
518 if (intr_status & EESR_TWB) {
519 /* Write buck end. unused write back interrupt */
520 if (intr_status & EESR_TABT) /* Transmit Abort int */
521 mdp->stats.tx_aborted_errors++;
522 }
523
524 if (intr_status & EESR_RABT) {
525 /* Receive Abort int */
526 if (intr_status & EESR_RFRMER) {
527 /* Receive Frame Overflow int */
528 mdp->stats.rx_frame_errors++;
529 printk(KERN_ERR "Receive Frame Overflow\n");
530 }
531 }
532
533 if (intr_status & EESR_ADE) {
534 if (intr_status & EESR_TDE) {
535 if (intr_status & EESR_TFE)
536 mdp->stats.tx_fifo_errors++;
537 }
538 }
539
540 if (intr_status & EESR_RDE) {
541 /* Receive Descriptor Empty int */
542 mdp->stats.rx_over_errors++;
543
544 if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R)
545 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
546 printk(KERN_ERR "Receive Descriptor Empty\n");
547 }
548 if (intr_status & EESR_RFE) {
549 /* Receive FIFO Overflow int */
550 mdp->stats.rx_fifo_errors++;
551 printk(KERN_ERR "Receive FIFO Overflow\n");
552 }
553 if (intr_status &
554 (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)) {
555 /* Tx error */
556 u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR);
557 /* dmesg */
558 printk(KERN_ERR "%s:TX error. status=%8.8x cur_tx=%8.8x ",
559 ndev->name, intr_status, mdp->cur_tx);
560 printk(KERN_ERR "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
561 mdp->dirty_tx, (u32) ndev->state, edtrr);
562 /* dirty buffer free */
563 sh_eth_txfree(ndev);
564
565 /* SH7712 BUG */
566 if (edtrr ^ EDTRR_TRNS) {
567 /* tx dma start */
568 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
569 }
570 /* wakeup */
571 netif_wake_queue(ndev);
572 }
573}
574
575static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
576{
577 struct net_device *ndev = netdev;
578 struct sh_eth_private *mdp = netdev_priv(ndev);
579 u32 ioaddr, boguscnt = RX_RING_SIZE;
580 u32 intr_status = 0;
581
582 ioaddr = ndev->base_addr;
583 spin_lock(&mdp->lock);
584
585 intr_status = ctrl_inl(ioaddr + EESR);
586 /* Clear interrupt */
587 ctrl_outl(intr_status, ioaddr + EESR);
588
589 if (intr_status & (EESR_FRC | EESR_RINT8 |
590 EESR_RINT5 | EESR_RINT4 | EESR_RINT3 | EESR_RINT2 |
591 EESR_RINT1))
592 sh_eth_rx(ndev);
593 if (intr_status & (EESR_FTC |
594 EESR_TINT4 | EESR_TINT3 | EESR_TINT2 | EESR_TINT1)) {
595
596 sh_eth_txfree(ndev);
597 netif_wake_queue(ndev);
598 }
599
600 if (intr_status & EESR_ERR_CHECK)
601 sh_eth_error(ndev, intr_status);
602
603 if (--boguscnt < 0) {
604 printk(KERN_WARNING
605 "%s: Too much work at interrupt, status=0x%4.4x.\n",
606 ndev->name, intr_status);
607 }
608
609 spin_unlock(&mdp->lock);
610
611 return IRQ_HANDLED;
612}
613
614static void sh_eth_timer(unsigned long data)
615{
616 struct net_device *ndev = (struct net_device *)data;
617 struct sh_eth_private *mdp = netdev_priv(ndev);
618
619 mod_timer(&mdp->timer, jiffies + (10 * HZ));
620}
621
622/* PHY state control function */
623static void sh_eth_adjust_link(struct net_device *ndev)
624{
625 struct sh_eth_private *mdp = netdev_priv(ndev);
626 struct phy_device *phydev = mdp->phydev;
627 u32 ioaddr = ndev->base_addr;
628 int new_state = 0;
629
630 if (phydev->link != PHY_DOWN) {
631 if (phydev->duplex != mdp->duplex) {
632 new_state = 1;
633 mdp->duplex = phydev->duplex;
634 }
635
636 if (phydev->speed != mdp->speed) {
637 new_state = 1;
638 mdp->speed = phydev->speed;
639 }
640 if (mdp->link == PHY_DOWN) {
641 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
642 | ECMR_DM, ioaddr + ECMR);
643 new_state = 1;
644 mdp->link = phydev->link;
645 netif_tx_schedule_all(ndev);
646 netif_carrier_on(ndev);
647 netif_start_queue(ndev);
648 }
649 } else if (mdp->link) {
650 new_state = 1;
651 mdp->link = PHY_DOWN;
652 mdp->speed = 0;
653 mdp->duplex = -1;
654 netif_stop_queue(ndev);
655 netif_carrier_off(ndev);
656 }
657
658 if (new_state)
659 phy_print_status(phydev);
660}
661
662/* PHY init function */
663static int sh_eth_phy_init(struct net_device *ndev)
664{
665 struct sh_eth_private *mdp = netdev_priv(ndev);
666 char phy_id[BUS_ID_SIZE];
667 struct phy_device *phydev = NULL;
668
669 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT,
670 mdp->mii_bus->id , mdp->phy_id);
671
672 mdp->link = PHY_DOWN;
673 mdp->speed = 0;
674 mdp->duplex = -1;
675
676 /* Try connect to PHY */
677 phydev = phy_connect(ndev, phy_id, &sh_eth_adjust_link,
678 0, PHY_INTERFACE_MODE_MII);
679 if (IS_ERR(phydev)) {
680 dev_err(&ndev->dev, "phy_connect failed\n");
681 return PTR_ERR(phydev);
682 }
683 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
684 phydev->addr, phydev->drv->name);
685
686 mdp->phydev = phydev;
687
688 return 0;
689}
690
691/* PHY control start function */
692static int sh_eth_phy_start(struct net_device *ndev)
693{
694 struct sh_eth_private *mdp = netdev_priv(ndev);
695 int ret;
696
697 ret = sh_eth_phy_init(ndev);
698 if (ret)
699 return ret;
700
701 /* reset phy - this also wakes it from PDOWN */
702 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
703 phy_start(mdp->phydev);
704
705 return 0;
706}
707
708/* network device open function */
709static int sh_eth_open(struct net_device *ndev)
710{
711 int ret = 0;
712 struct sh_eth_private *mdp = netdev_priv(ndev);
713
714 ret = request_irq(ndev->irq, &sh_eth_interrupt, 0, ndev->name, ndev);
715 if (ret) {
716 printk(KERN_ERR "Can not assign IRQ number to %s\n", CARDNAME);
717 return ret;
718 }
719
720 /* Descriptor set */
721 ret = sh_eth_ring_init(ndev);
722 if (ret)
723 goto out_free_irq;
724
725 /* device init */
726 ret = sh_eth_dev_init(ndev);
727 if (ret)
728 goto out_free_irq;
729
730 /* PHY control start*/
731 ret = sh_eth_phy_start(ndev);
732 if (ret)
733 goto out_free_irq;
734
735 /* Set the timer to check for link beat. */
736 init_timer(&mdp->timer);
737 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
738 setup_timer(&mdp->timer, sh_eth_timer, ndev);
739
740 return ret;
741
742out_free_irq:
743 free_irq(ndev->irq, ndev);
744 return ret;
745}
746
747/* Timeout function */
748static void sh_eth_tx_timeout(struct net_device *ndev)
749{
750 struct sh_eth_private *mdp = netdev_priv(ndev);
751 u32 ioaddr = ndev->base_addr;
752 struct sh_eth_rxdesc *rxdesc;
753 int i;
754
755 netif_stop_queue(ndev);
756
757 /* worning message out. */
758 printk(KERN_WARNING "%s: transmit timed out, status %8.8x,"
759 " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR));
760
761 /* tx_errors count up */
762 mdp->stats.tx_errors++;
763
764 /* timer off */
765 del_timer_sync(&mdp->timer);
766
767 /* Free all the skbuffs in the Rx queue. */
768 for (i = 0; i < RX_RING_SIZE; i++) {
769 rxdesc = &mdp->rx_ring[i];
770 rxdesc->status = 0;
771 rxdesc->addr = 0xBADF00D0;
772 if (mdp->rx_skbuff[i])
773 dev_kfree_skb(mdp->rx_skbuff[i]);
774 mdp->rx_skbuff[i] = NULL;
775 }
776 for (i = 0; i < TX_RING_SIZE; i++) {
777 if (mdp->tx_skbuff[i])
778 dev_kfree_skb(mdp->tx_skbuff[i]);
779 mdp->tx_skbuff[i] = NULL;
780 }
781
782 /* device init */
783 sh_eth_dev_init(ndev);
784
785 /* timer on */
786 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
787 add_timer(&mdp->timer);
788}
789
790/* Packet transmit function */
791static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
792{
793 struct sh_eth_private *mdp = netdev_priv(ndev);
794 struct sh_eth_txdesc *txdesc;
795 u32 entry;
796 int flags;
797
798 spin_lock_irqsave(&mdp->lock, flags);
799 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
800 if (!sh_eth_txfree(ndev)) {
801 netif_stop_queue(ndev);
802 spin_unlock_irqrestore(&mdp->lock, flags);
803 return 1;
804 }
805 }
806 spin_unlock_irqrestore(&mdp->lock, flags);
807
808 entry = mdp->cur_tx % TX_RING_SIZE;
809 mdp->tx_skbuff[entry] = skb;
810 txdesc = &mdp->tx_ring[entry];
811 txdesc->addr = (u32)(skb->data);
812 /* soft swap. */
813 swaps((char *)(txdesc->addr & ~0x3), skb->len + 2);
814 /* write back */
815 __flush_purge_region(skb->data, skb->len);
816 if (skb->len < ETHERSMALL)
817 txdesc->buffer_length = ETHERSMALL;
818 else
819 txdesc->buffer_length = skb->len;
820
821 if (entry >= TX_RING_SIZE - 1)
822 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
823 else
824 txdesc->status |= cpu_to_le32(TD_TACT);
825
826 mdp->cur_tx++;
827
828 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
829 ndev->trans_start = jiffies;
830
831 return 0;
832}
833
834/* device close function */
835static int sh_eth_close(struct net_device *ndev)
836{
837 struct sh_eth_private *mdp = netdev_priv(ndev);
838 u32 ioaddr = ndev->base_addr;
839 int ringsize;
840
841 netif_stop_queue(ndev);
842
843 /* Disable interrupts by clearing the interrupt mask. */
844 ctrl_outl(0x0000, ioaddr + EESIPR);
845
846 /* Stop the chip's Tx and Rx processes. */
847 ctrl_outl(0, ioaddr + EDTRR);
848 ctrl_outl(0, ioaddr + EDRRR);
849
850 /* PHY Disconnect */
851 if (mdp->phydev) {
852 phy_stop(mdp->phydev);
853 phy_disconnect(mdp->phydev);
854 }
855
856 free_irq(ndev->irq, ndev);
857
858 del_timer_sync(&mdp->timer);
859
860 /* Free all the skbuffs in the Rx queue. */
861 sh_eth_ring_free(ndev);
862
863 /* free DMA buffer */
864 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
865 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
866
867 /* free DMA buffer */
868 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
869 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
870
871 return 0;
872}
873
874static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
875{
876 struct sh_eth_private *mdp = netdev_priv(ndev);
877 u32 ioaddr = ndev->base_addr;
878
879 mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR);
880 ctrl_outl(0, ioaddr + TROCR); /* (write clear) */
881 mdp->stats.collisions += ctrl_inl(ioaddr + CDCR);
882 ctrl_outl(0, ioaddr + CDCR); /* (write clear) */
883 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR);
884 ctrl_outl(0, ioaddr + LCCR); /* (write clear) */
885 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR);
886 ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */
887
888 return &mdp->stats;
889}
890
891/* ioctl to device funciotn*/
892static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
893 int cmd)
894{
895 struct sh_eth_private *mdp = netdev_priv(ndev);
896 struct phy_device *phydev = mdp->phydev;
897
898 if (!netif_running(ndev))
899 return -EINVAL;
900
901 if (!phydev)
902 return -ENODEV;
903
904 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
905}
906
907
908/* Multicast reception directions set */
909static void sh_eth_set_multicast_list(struct net_device *ndev)
910{
911 u32 ioaddr = ndev->base_addr;
912
913 if (ndev->flags & IFF_PROMISC) {
914 /* Set promiscuous. */
915 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
916 ioaddr + ECMR);
917 } else {
918 /* Normal, unicast/broadcast-only mode. */
919 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
920 ioaddr + ECMR);
921 }
922}
923
924/* SuperH's TSU register init function */
925static void sh_eth_tsu_init(u32 ioaddr)
926{
927 ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */
928 ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */
929 ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */
930 ctrl_outl(0xc, ioaddr + TSU_BSYSL0);
931 ctrl_outl(0xc, ioaddr + TSU_BSYSL1);
932 ctrl_outl(0, ioaddr + TSU_PRISL0);
933 ctrl_outl(0, ioaddr + TSU_PRISL1);
934 ctrl_outl(0, ioaddr + TSU_FWSL0);
935 ctrl_outl(0, ioaddr + TSU_FWSL1);
936 ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
937 ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
938 ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
939 ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */
940 ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
941 ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
942 ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */
943 ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */
944 ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */
945 ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */
946}
947
948/* MDIO bus release function */
949static int sh_mdio_release(struct net_device *ndev)
950{
951 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
952
953 /* unregister mdio bus */
954 mdiobus_unregister(bus);
955
956 /* remove mdio bus info from net_device */
957 dev_set_drvdata(&ndev->dev, NULL);
958
959 /* free bitbang info */
960 free_mdio_bitbang(bus);
961
962 return 0;
963}
964
965/* MDIO bus init function */
966static int sh_mdio_init(struct net_device *ndev, int id)
967{
968 int ret, i;
969 struct bb_info *bitbang;
970 struct sh_eth_private *mdp = netdev_priv(ndev);
971
972 /* create bit control struct for PHY */
973 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
974 if (!bitbang) {
975 ret = -ENOMEM;
976 goto out;
977 }
978
979 /* bitbang init */
980 bitbang->addr = ndev->base_addr + PIR;
981 bitbang->mdi_msk = 0x08;
982 bitbang->mdo_msk = 0x04;
983 bitbang->mmd_msk = 0x02;/* MMD */
984 bitbang->mdc_msk = 0x01;
985 bitbang->ctrl.ops = &bb_ops;
986
987 /* MII contorller setting */
988 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
989 if (!mdp->mii_bus) {
990 ret = -ENOMEM;
991 goto out_free_bitbang;
992 }
993
994 /* Hook up MII support for ethtool */
995 mdp->mii_bus->name = "sh_mii";
996 mdp->mii_bus->dev = &ndev->dev;
997 mdp->mii_bus->id[0] = id;
998
999 /* PHY IRQ */
1000 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1001 if (!mdp->mii_bus->irq) {
1002 ret = -ENOMEM;
1003 goto out_free_bus;
1004 }
1005
1006 for (i = 0; i < PHY_MAX_ADDR; i++)
1007 mdp->mii_bus->irq[i] = PHY_POLL;
1008
1009 /* regist mdio bus */
1010 ret = mdiobus_register(mdp->mii_bus);
1011 if (ret)
1012 goto out_free_irq;
1013
1014 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1015
1016 return 0;
1017
1018out_free_irq:
1019 kfree(mdp->mii_bus->irq);
1020
1021out_free_bus:
1022 kfree(mdp->mii_bus);
1023
1024out_free_bitbang:
1025 kfree(bitbang);
1026
1027out:
1028 return ret;
1029}
1030
1031static int sh_eth_drv_probe(struct platform_device *pdev)
1032{
1033 int ret, i, devno = 0;
1034 struct resource *res;
1035 struct net_device *ndev = NULL;
1036 struct sh_eth_private *mdp;
1037
1038 /* get base addr */
1039 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1040 if (unlikely(res == NULL)) {
1041 dev_err(&pdev->dev, "invalid resource\n");
1042 ret = -EINVAL;
1043 goto out;
1044 }
1045
1046 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1047 if (!ndev) {
1048 printk(KERN_ERR "%s: could not allocate device.\n", CARDNAME);
1049 ret = -ENOMEM;
1050 goto out;
1051 }
1052
1053 /* The sh Ether-specific entries in the device structure. */
1054 ndev->base_addr = res->start;
1055 devno = pdev->id;
1056 if (devno < 0)
1057 devno = 0;
1058
1059 ndev->dma = -1;
1060 ndev->irq = platform_get_irq(pdev, 0);
1061 if (ndev->irq < 0) {
1062 ret = -ENODEV;
1063 goto out_release;
1064 }
1065
1066 SET_NETDEV_DEV(ndev, &pdev->dev);
1067
1068 /* Fill in the fields of the device structure with ethernet values. */
1069 ether_setup(ndev);
1070
1071 mdp = netdev_priv(ndev);
1072 spin_lock_init(&mdp->lock);
1073
1074 /* get PHY ID */
1075 mdp->phy_id = (int)pdev->dev.platform_data;
1076
1077 /* set function */
1078 ndev->open = sh_eth_open;
1079 ndev->hard_start_xmit = sh_eth_start_xmit;
1080 ndev->stop = sh_eth_close;
1081 ndev->get_stats = sh_eth_get_stats;
1082 ndev->set_multicast_list = sh_eth_set_multicast_list;
1083 ndev->do_ioctl = sh_eth_do_ioctl;
1084 ndev->tx_timeout = sh_eth_tx_timeout;
1085 ndev->watchdog_timeo = TX_TIMEOUT;
1086
1087 mdp->post_rx = POST_RX >> (devno << 1);
1088 mdp->post_fw = POST_FW >> (devno << 1);
1089
1090 /* read and set MAC address */
1091 read_mac_address(ndev);
1092
1093 /* First device only init */
1094 if (!devno) {
1095 /* reset device */
1096 ctrl_outl(ARSTR_ARSTR, ndev->base_addr + ARSTR);
1097 mdelay(1);
1098
1099 /* TSU init (Init only)*/
1100 sh_eth_tsu_init(SH_TSU_ADDR);
1101 }
1102
1103 /* network device register */
1104 ret = register_netdev(ndev);
1105 if (ret)
1106 goto out_release;
1107
1108 /* mdio bus init */
1109 ret = sh_mdio_init(ndev, pdev->id);
1110 if (ret)
1111 goto out_unregister;
1112
1113 /* pritnt device infomation */
1114 printk(KERN_INFO "%s: %s at 0x%x, ",
1115 ndev->name, CARDNAME, (u32) ndev->base_addr);
1116
1117 for (i = 0; i < 5; i++)
1118 printk(KERN_INFO "%2.2x:", ndev->dev_addr[i]);
1119 printk(KERN_INFO "%2.2x, IRQ %d.\n", ndev->dev_addr[i], ndev->irq);
1120
1121 platform_set_drvdata(pdev, ndev);
1122
1123 return ret;
1124
1125out_unregister:
1126 unregister_netdev(ndev);
1127
1128out_release:
1129 /* net_dev free */
1130 if (ndev)
1131 free_netdev(ndev);
1132
1133out:
1134 return ret;
1135}
1136
1137static int sh_eth_drv_remove(struct platform_device *pdev)
1138{
1139 struct net_device *ndev = platform_get_drvdata(pdev);
1140
1141 sh_mdio_release(ndev);
1142 unregister_netdev(ndev);
1143 flush_scheduled_work();
1144
1145 free_netdev(ndev);
1146 platform_set_drvdata(pdev, NULL);
1147
1148 return 0;
1149}
1150
1151static struct platform_driver sh_eth_driver = {
1152 .probe = sh_eth_drv_probe,
1153 .remove = sh_eth_drv_remove,
1154 .driver = {
1155 .name = CARDNAME,
1156 },
1157};
1158
1159static int __init sh_eth_init(void)
1160{
1161 return platform_driver_register(&sh_eth_driver);
1162}
1163
1164static void __exit sh_eth_cleanup(void)
1165{
1166 platform_driver_unregister(&sh_eth_driver);
1167}
1168
1169module_init(sh_eth_init);
1170module_exit(sh_eth_cleanup);
1171
1172MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1173MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1174MODULE_LICENSE("GPL v2");
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
new file mode 100644
index 000000000000..e01e1c347715
--- /dev/null
+++ b/drivers/net/sh_eth.h
@@ -0,0 +1,464 @@
1/*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23#ifndef __SH_ETH_H__
24#define __SH_ETH_H__
25
26#include <linux/module.h>
27#include <linux/kernel.h>
28#include <linux/spinlock.h>
29#include <linux/workqueue.h>
30#include <linux/netdevice.h>
31#include <linux/phy.h>
32
33#define CARDNAME "sh-eth"
34#define TX_TIMEOUT (5*HZ)
35
36#define TX_RING_SIZE 128 /* Tx ring size */
37#define RX_RING_SIZE 128 /* Rx ring size */
38#define RX_OFFSET 2 /* skb offset */
39#define ETHERSMALL 60
40#define PKT_BUF_SZ 1538
41
42/* Chip Base Address */
43#define SH_TSU_ADDR 0xA7000804
44
45/* Chip Registers */
46/* E-DMAC */
47#define EDMR 0x0000
48#define EDTRR 0x0004
49#define EDRRR 0x0008
50#define TDLAR 0x000C
51#define RDLAR 0x0010
52#define EESR 0x0014
53#define EESIPR 0x0018
54#define TRSCER 0x001C
55#define RMFCR 0x0020
56#define TFTR 0x0024
57#define FDR 0x0028
58#define RMCR 0x002C
59#define EDOCR 0x0030
60#define FCFTR 0x0034
61#define RPADIR 0x0038
62#define TRIMD 0x003C
63#define RBWAR 0x0040
64#define RDFAR 0x0044
65#define TBRAR 0x004C
66#define TDFAR 0x0050
67/* Ether Register */
68#define ECMR 0x0160
69#define ECSR 0x0164
70#define ECSIPR 0x0168
71#define PIR 0x016C
72#define MAHR 0x0170
73#define MALR 0x0174
74#define RFLR 0x0178
75#define PSR 0x017C
76#define TROCR 0x0180
77#define CDCR 0x0184
78#define LCCR 0x0188
79#define CNDCR 0x018C
80#define CEFCR 0x0194
81#define FRECR 0x0198
82#define TSFRCR 0x019C
83#define TLFRCR 0x01A0
84#define RFCR 0x01A4
85#define MAFCR 0x01A8
86#define IPGR 0x01B4
87#if defined(CONFIG_CPU_SUBTYPE_SH7710)
88#define APR 0x01B8
89#define MPR 0x01BC
90#define TPAUSER 0x1C4
91#define BCFR 0x1CC
92#endif /* CONFIG_CPU_SH7710 */
93
94#define ARSTR 0x0800
95
96/* TSU */
97#define TSU_CTRST 0x004
98#define TSU_FWEN0 0x010
99#define TSU_FWEN1 0x014
100#define TSU_FCM 0x018
101#define TSU_BSYSL0 0x020
102#define TSU_BSYSL1 0x024
103#define TSU_PRISL0 0x028
104#define TSU_PRISL1 0x02C
105#define TSU_FWSL0 0x030
106#define TSU_FWSL1 0x034
107#define TSU_FWSLC 0x038
108#define TSU_QTAGM0 0x040
109#define TSU_QTAGM1 0x044
110#define TSU_ADQT0 0x048
111#define TSU_ADQT1 0x04C
112#define TSU_FWSR 0x050
113#define TSU_FWINMK 0x054
114#define TSU_ADSBSY 0x060
115#define TSU_TEN 0x064
116#define TSU_POST1 0x070
117#define TSU_POST2 0x074
118#define TSU_POST3 0x078
119#define TSU_POST4 0x07C
120#define TXNLCR0 0x080
121#define TXALCR0 0x084
122#define RXNLCR0 0x088
123#define RXALCR0 0x08C
124#define FWNLCR0 0x090
125#define FWALCR0 0x094
126#define TXNLCR1 0x0A0
127#define TXALCR1 0x0A4
128#define RXNLCR1 0x0A8
129#define RXALCR1 0x0AC
130#define FWNLCR1 0x0B0
131#define FWALCR1 0x0B4
132
133#define TSU_ADRH0 0x0100
134#define TSU_ADRL0 0x0104
135#define TSU_ADRL31 0x01FC
136
137/* Register's bits */
138
139/* EDMR */
140enum DMAC_M_BIT {
141 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, EDMR_SRST = 0x01,
142};
143
144/* EDTRR */
145enum DMAC_T_BIT {
146 EDTRR_TRNS = 0x01,
147};
148
149/* EDRRR*/
150enum EDRRR_R_BIT {
151 EDRRR_R = 0x01,
152};
153
154/* TPAUSER */
155enum TPAUSER_BIT {
156 TPAUSER_TPAUSE = 0x0000ffff,
157 TPAUSER_UNLIMITED = 0,
158};
159
160/* BCFR */
161enum BCFR_BIT {
162 BCFR_RPAUSE = 0x0000ffff,
163 BCFR_UNLIMITED = 0,
164};
165
166/* PIR */
167enum PIR_BIT {
168 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
169};
170
171/* PSR */
172enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
173
174/* EESR */
175enum EESR_BIT {
176 EESR_TWB = 0x40000000, EESR_TABT = 0x04000000,
177 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
178 EESR_ADE = 0x00800000, EESR_ECI = 0x00400000,
179 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
180 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
181 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
182 EESR_TINT4 = 0x00000800, EESR_TINT3 = 0x00000400,
183 EESR_TINT2 = 0x00000200, EESR_TINT1 = 0x00000100,
184 EESR_RINT8 = 0x00000080, EESR_RINT5 = 0x00000010,
185 EESR_RINT4 = 0x00000008, EESR_RINT3 = 0x00000004,
186 EESR_RINT2 = 0x00000002, EESR_RINT1 = 0x00000001,
187};
188
189#define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
190 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
191
192/* EESIPR */
193enum DMAC_IM_BIT {
194 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
195 DMAC_M_RABT = 0x02000000,
196 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
197 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
198 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
199 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
200 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
201 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
202 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
203 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
204 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
205 DMAC_M_RINT1 = 0x00000001,
206};
207
208/* Receive descriptor bit */
209enum RD_STS_BIT {
210 RD_RACT = 0x80000000, RC_RDEL = 0x40000000,
211 RC_RFP1 = 0x20000000, RC_RFP0 = 0x10000000,
212 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
213 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
214 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
215 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
216 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
217 RD_RFS1 = 0x00000001,
218};
219#define RDF1ST RC_RFP1
220#define RDFEND RC_RFP0
221#define RD_RFP (RC_RFP1|RC_RFP0)
222
223/* FCFTR */
224enum FCFTR_BIT {
225 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
226 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
227 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
228};
229#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
230#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
231
232/* Transfer descriptor bit */
233enum TD_STS_BIT {
234 TD_TACT = 0x80000000, TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
235 TD_TFP0 = 0x10000000,
236};
237#define TDF1ST TD_TFP1
238#define TDFEND TD_TFP0
239#define TD_TFP (TD_TFP1|TD_TFP0)
240
241/* RMCR */
242enum RECV_RST_BIT { RMCR_RST = 0x01, };
243/* ECMR */
244enum FELIC_MODE_BIT {
245 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
246 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
247 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
248 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
249 ECMR_PRM = 0x00000001,
250};
251
252/* ECSR */
253enum ECSR_STATUS_BIT {
254 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, ECSR_LCHNG = 0x04,
255 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
256};
257
258/* ECSIPR */
259enum ECSIPR_STATUS_MASK_BIT {
260 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, ECSIPR_LCHNGIP = 0x04,
261 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
262};
263
264/* APR */
265enum APR_BIT {
266 APR_AP = 0x00000001,
267};
268
269/* MPR */
270enum MPR_BIT {
271 MPR_MP = 0x00000001,
272};
273
274/* TRSCER */
275enum DESC_I_BIT {
276 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
277 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
278 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
279 DESC_I_RINT1 = 0x0001,
280};
281
282/* RPADIR */
283enum RPADIR_BIT {
284 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
285 RPADIR_PADR = 0x0003f,
286};
287
288/* FDR */
289enum FIFO_SIZE_BIT {
290 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
291};
292enum phy_offsets {
293 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
294 PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
295 PHY_16 = 16,
296};
297
298/* PHY_CTRL */
299enum PHY_CTRL_BIT {
300 PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
301 PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
302 PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
303};
304#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
305
306/* PHY_STAT */
307enum PHY_STAT_BIT {
308 PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
309 PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
310 PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
311 PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
312};
313
314/* PHY_ANA */
315enum PHY_ANA_BIT {
316 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
317 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
318 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
319 PHY_A_SEL = 0x001f,
320};
321/* PHY_ANL */
322enum PHY_ANL_BIT {
323 PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
324 PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
325 PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
326 PHY_L_SEL = 0x001f,
327};
328
329/* PHY_ANE */
330enum PHY_ANE_BIT {
331 PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
332 PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
333};
334
335/* DM9161 */
336enum PHY_16_BIT {
337 PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
338 PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
339 PHY_16_TXselect = 0x0400,
340 PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
341 PHY_16_Force100LNK = 0x0080,
342 PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
343 PHY_16_RPDCTR_EN = 0x0010,
344 PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
345 PHY_16_Sleepmode = 0x0002,
346 PHY_16_RemoteLoopOut = 0x0001,
347};
348
349#define POST_RX 0x08
350#define POST_FW 0x04
351#define POST0_RX (POST_RX)
352#define POST0_FW (POST_FW)
353#define POST1_RX (POST_RX >> 2)
354#define POST1_FW (POST_FW >> 2)
355#define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
356
357/* ARSTR */
358enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
359
360/* TSU_FWEN0 */
361enum TSU_FWEN0_BIT {
362 TSU_FWEN0_0 = 0x00000001,
363};
364
365/* TSU_ADSBSY */
366enum TSU_ADSBSY_BIT {
367 TSU_ADSBSY_0 = 0x00000001,
368};
369
370/* TSU_TEN */
371enum TSU_TEN_BIT {
372 TSU_TEN_0 = 0x80000000,
373};
374
375/* TSU_FWSL0 */
376enum TSU_FWSL0_BIT {
377 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
378 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
379 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
380};
381
382/* TSU_FWSLC */
383enum TSU_FWSLC_BIT {
384 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
385 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
386 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
387 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
388 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
389};
390
391/*
392 * The sh ether Tx buffer descriptors.
393 * This structure should be 20 bytes.
394 */
395struct sh_eth_txdesc {
396 u32 status; /* TD0 */
397#if defined(CONFIG_CPU_LITTLE_ENDIAN)
398 u16 pad0; /* TD1 */
399 u16 buffer_length; /* TD1 */
400#else
401 u16 buffer_length; /* TD1 */
402 u16 pad0; /* TD1 */
403#endif
404 u32 addr; /* TD2 */
405 u32 pad1; /* padding data */
406};
407
408/*
409 * The sh ether Rx buffer descriptors.
410 * This structure should be 20 bytes.
411 */
412struct sh_eth_rxdesc {
413 u32 status; /* RD0 */
414#if defined(CONFIG_CPU_LITTLE_ENDIAN)
415 u16 frame_length; /* RD1 */
416 u16 buffer_length; /* RD1 */
417#else
418 u16 buffer_length; /* RD1 */
419 u16 frame_length; /* RD1 */
420#endif
421 u32 addr; /* RD2 */
422 u32 pad0; /* padding data */
423};
424
425struct sh_eth_private {
426 dma_addr_t rx_desc_dma;
427 dma_addr_t tx_desc_dma;
428 struct sh_eth_rxdesc *rx_ring;
429 struct sh_eth_txdesc *tx_ring;
430 struct sk_buff **rx_skbuff;
431 struct sk_buff **tx_skbuff;
432 struct net_device_stats stats;
433 struct timer_list timer;
434 spinlock_t lock;
435 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
436 u32 cur_tx, dirty_tx;
437 u32 rx_buf_sz; /* Based on MTU+slack. */
438 /* MII transceiver section. */
439 u32 phy_id; /* PHY ID */
440 struct mii_bus *mii_bus; /* MDIO bus control */
441 struct phy_device *phydev; /* PHY device control */
442 enum phy_state link;
443 int msg_enable;
444 int speed;
445 int duplex;
446 u32 rx_int_var, tx_int_var; /* interrupt control variables */
447 char post_rx; /* POST receive */
448 char post_fw; /* POST forward */
449 struct net_device_stats tsu_stats; /* TSU forward status */
450};
451
452static void swaps(char *src, int len)
453{
454#ifdef __LITTLE_ENDIAN__
455 u32 *p = (u32 *)src;
456 u32 *maxp;
457 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
458
459 for (; p < maxp; p++)
460 *p = swab32(*p);
461#endif
462}
463
464#endif
diff --git a/drivers/net/sis190.c b/drivers/net/sis190.c
index abc63b0663be..3fe01763760e 100644
--- a/drivers/net/sis190.c
+++ b/drivers/net/sis190.c
@@ -1656,7 +1656,7 @@ static inline void sis190_init_rxfilter(struct net_device *dev)
1656 SIS_PCI_COMMIT(); 1656 SIS_PCI_COMMIT();
1657} 1657}
1658 1658
1659static int __devinit sis190_get_mac_addr(struct pci_dev *pdev, 1659static int __devinit sis190_get_mac_addr(struct pci_dev *pdev,
1660 struct net_device *dev) 1660 struct net_device *dev)
1661{ 1661{
1662 int rc; 1662 int rc;
diff --git a/drivers/net/sis900.c b/drivers/net/sis900.c
index ec95e493ac1c..fa3a460f8e2f 100644
--- a/drivers/net/sis900.c
+++ b/drivers/net/sis900.c
@@ -1766,7 +1766,7 @@ static int sis900_rx(struct net_device *net_dev)
1766 skb = sis_priv->rx_skbuff[entry]; 1766 skb = sis_priv->rx_skbuff[entry];
1767 net_dev->stats.rx_dropped++; 1767 net_dev->stats.rx_dropped++;
1768 goto refill_rx_ring; 1768 goto refill_rx_ring;
1769 } 1769 }
1770 1770
1771 /* This situation should never happen, but due to 1771 /* This situation should never happen, but due to
1772 some unknow bugs, it is possible that 1772 some unknow bugs, it is possible that
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index c8a5ef2d75f4..711e4a8948e0 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -51,7 +51,7 @@
51#include "sky2.h" 51#include "sky2.h"
52 52
53#define DRV_NAME "sky2" 53#define DRV_NAME "sky2"
54#define DRV_VERSION "1.21" 54#define DRV_VERSION "1.22"
55#define PFX DRV_NAME " " 55#define PFX DRV_NAME " "
56 56
57/* 57/*
@@ -98,7 +98,7 @@ static int disable_msi = 0;
98module_param(disable_msi, int, 0); 98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100 100
101static const struct pci_device_id sky2_id_table[] = { 101static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
@@ -137,6 +137,7 @@ static const struct pci_device_id sky2_id_table[] = {
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
140 { 0 } 141 { 0 }
141}; 142};
142 143
@@ -147,17 +148,6 @@ static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 148static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; 149static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149 150
150/* This driver supports yukon2 chipset only */
151static const char *yukon2_name[] = {
152 "XL", /* 0xb3 */
153 "EC Ultra", /* 0xb4 */
154 "Extreme", /* 0xb5 */
155 "EC", /* 0xb6 */
156 "FE", /* 0xb7 */
157 "FE+", /* 0xb8 */
158 "Supreme", /* 0xb9 */
159};
160
161static void sky2_set_multicast(struct net_device *dev); 151static void sky2_set_multicast(struct net_device *dev);
162 152
163/* Access to PHY via serial interconnect */ 153/* Access to PHY via serial interconnect */
@@ -285,6 +275,86 @@ static void sky2_power_aux(struct sky2_hw *hw)
285 PC_VAUX_ON | PC_VCC_OFF)); 275 PC_VAUX_ON | PC_VCC_OFF));
286} 276}
287 277
278static void sky2_power_state(struct sky2_hw *hw, pci_power_t state)
279{
280 u16 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
281 int pex = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
282 u32 reg;
283
284 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
285
286 switch (state) {
287 case PCI_D0:
288 break;
289
290 case PCI_D1:
291 power_control |= 1;
292 break;
293
294 case PCI_D2:
295 power_control |= 2;
296 break;
297
298 case PCI_D3hot:
299 case PCI_D3cold:
300 power_control |= 3;
301 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
302 /* additional power saving measurements */
303 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
304
305 /* set gating core clock for LTSSM in L1 state */
306 reg |= P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
307 /* auto clock gated scheme controlled by CLKREQ */
308 P_ASPM_A1_MODE_SELECT |
309 /* enable Gate Root Core Clock */
310 P_CLK_GATE_ROOT_COR_ENA;
311
312 if (pex && (hw->flags & SKY2_HW_CLK_POWER)) {
313 /* enable Clock Power Management (CLKREQ) */
314 u16 ctrl = sky2_pci_read16(hw, pex + PCI_EXP_DEVCTL);
315
316 ctrl |= PCI_EXP_DEVCTL_AUX_PME;
317 sky2_pci_write16(hw, pex + PCI_EXP_DEVCTL, ctrl);
318 } else
319 /* force CLKREQ Enable in Our4 (A1b only) */
320 reg |= P_ASPM_FORCE_CLKREQ_ENA;
321
322 /* set Mask Register for Release/Gate Clock */
323 sky2_pci_write32(hw, PCI_DEV_REG5,
324 P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
325 P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
326 P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
327 } else
328 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_CLK_HALT);
329
330 /* put CPU into reset state */
331 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_RESET);
332 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev == CHIP_REV_YU_SU_A0)
333 /* put CPU into halt state */
334 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_HALTED);
335
336 if (pex && !(hw->flags & SKY2_HW_RAM_BUFFER)) {
337 reg = sky2_pci_read32(hw, PCI_DEV_REG1);
338 /* force to PCIe L1 */
339 reg |= PCI_FORCE_PEX_L1;
340 sky2_pci_write32(hw, PCI_DEV_REG1, reg);
341 }
342 break;
343
344 default:
345 dev_warn(&hw->pdev->dev, PFX "Invalid power state (%d) ",
346 state);
347 return;
348 }
349
350 power_control |= PCI_PM_CTRL_PME_ENABLE;
351 /* Finally, set the new power state. */
352 sky2_pci_write32(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
353
354 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
355 sky2_pci_read32(hw, B0_CTST);
356}
357
288static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) 358static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
289{ 359{
290 u16 reg; 360 u16 reg;
@@ -579,8 +649,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
579 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 649 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
580 } 650 }
581 651
582 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 652 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
583 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
584 /* apply fixes in PHY AFE */ 653 /* apply fixes in PHY AFE */
585 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 654 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
586 655
@@ -588,9 +657,11 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
588 gm_phy_write(hw, port, 0x18, 0xaa99); 657 gm_phy_write(hw, port, 0x18, 0xaa99);
589 gm_phy_write(hw, port, 0x17, 0x2011); 658 gm_phy_write(hw, port, 0x17, 0x2011);
590 659
591 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 660 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
592 gm_phy_write(hw, port, 0x18, 0xa204); 661 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
593 gm_phy_write(hw, port, 0x17, 0x2002); 662 gm_phy_write(hw, port, 0x18, 0xa204);
663 gm_phy_write(hw, port, 0x17, 0x2002);
664 }
594 665
595 /* set page register to 0 */ 666 /* set page register to 0 */
596 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 667 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
@@ -599,7 +670,8 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
599 /* apply workaround for integrated resistors calibration */ 670 /* apply workaround for integrated resistors calibration */
600 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); 671 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
601 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); 672 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
602 } else if (hw->chip_id != CHIP_ID_YUKON_EX) { 673 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
674 hw->chip_id < CHIP_ID_YUKON_SUPR) {
603 /* no effect on Yukon-XL */ 675 /* no effect on Yukon-XL */
604 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 676 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
605 677
@@ -620,28 +692,71 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
620 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 692 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
621} 693}
622 694
623static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) 695static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
696static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
697
698static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
624{ 699{
625 u32 reg1; 700 u32 reg1;
626 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
627 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
628 701
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 702 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
630 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 703 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
631 /* Turn on/off phy power saving */ 704 reg1 &= ~phy_power[port];
632 if (onoff)
633 reg1 &= ~phy_power[port];
634 else
635 reg1 |= phy_power[port];
636 705
637 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 706 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
638 reg1 |= coma_mode[port]; 707 reg1 |= coma_mode[port];
639 708
640 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 709 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
641 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 710 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
642 sky2_pci_read32(hw, PCI_DEV_REG1); 711 sky2_pci_read32(hw, PCI_DEV_REG1);
712}
713
714static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
715{
716 u32 reg1;
717 u16 ctrl;
718
719 /* release GPHY Control reset */
720 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
721
722 /* release GMAC reset */
723 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
724
725 if (hw->flags & SKY2_HW_NEWER_PHY) {
726 /* select page 2 to access MAC control register */
727 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
643 728
644 udelay(100); 729 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
730 /* allow GMII Power Down */
731 ctrl &= ~PHY_M_MAC_GMIF_PUP;
732 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
733
734 /* set page register back to 0 */
735 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
736 }
737
738 /* setup General Purpose Control Register */
739 gma_write16(hw, port, GM_GP_CTRL,
740 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
741
742 if (hw->chip_id != CHIP_ID_YUKON_EC) {
743 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
744 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
745
746 /* enable Power Down */
747 ctrl |= PHY_M_PC_POW_D_ENA;
748 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
749 }
750
751 /* set IEEE compatible Power Down Mode (dev. #4.99) */
752 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
753 }
754
755 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
756 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
757 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
758 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
759 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
645} 760}
646 761
647/* Force a renegotiation */ 762/* Force a renegotiation */
@@ -676,8 +791,11 @@ static void sky2_wol_init(struct sky2_port *sky2)
676 791
677 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); 792 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
678 sky2->flow_mode = FC_NONE; 793 sky2->flow_mode = FC_NONE;
679 sky2_phy_power(hw, port, 1); 794
680 sky2_phy_reinit(sky2); 795 spin_lock_bh(&sky2->phy_lock);
796 sky2_phy_power_up(hw, port);
797 sky2_phy_init(hw, port);
798 spin_unlock_bh(&sky2->phy_lock);
681 799
682 sky2->flow_mode = save_mode; 800 sky2->flow_mode = save_mode;
683 sky2->advertising = ctrl; 801 sky2->advertising = ctrl;
@@ -782,6 +900,7 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
782 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 900 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
783 901
784 spin_lock_bh(&sky2->phy_lock); 902 spin_lock_bh(&sky2->phy_lock);
903 sky2_phy_power_up(hw, port);
785 sky2_phy_init(hw, port); 904 sky2_phy_init(hw, port);
786 spin_unlock_bh(&sky2->phy_lock); 905 spin_unlock_bh(&sky2->phy_lock);
787 906
@@ -1386,8 +1505,6 @@ static int sky2_up(struct net_device *dev)
1386 if (!sky2->rx_ring) 1505 if (!sky2->rx_ring)
1387 goto err_out; 1506 goto err_out;
1388 1507
1389 sky2_phy_power(hw, port, 1);
1390
1391 sky2_mac_init(hw, port); 1508 sky2_mac_init(hw, port);
1392 1509
1393 /* Register is number of 4K blocks on internal RAM buffer. */ 1510 /* Register is number of 4K blocks on internal RAM buffer. */
@@ -1768,7 +1885,7 @@ static int sky2_down(struct net_device *dev)
1768 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 1885 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1769 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 1886 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1770 1887
1771 sky2_phy_power(hw, port, 0); 1888 sky2_phy_power_down(hw, port);
1772 1889
1773 netif_carrier_off(dev); 1890 netif_carrier_off(dev);
1774 1891
@@ -2694,6 +2811,7 @@ static u32 sky2_mhz(const struct sky2_hw *hw)
2694 case CHIP_ID_YUKON_EC_U: 2811 case CHIP_ID_YUKON_EC_U:
2695 case CHIP_ID_YUKON_EX: 2812 case CHIP_ID_YUKON_EX:
2696 case CHIP_ID_YUKON_SUPR: 2813 case CHIP_ID_YUKON_SUPR:
2814 case CHIP_ID_YUKON_UL_2:
2697 return 125; 2815 return 125;
2698 2816
2699 case CHIP_ID_YUKON_FE: 2817 case CHIP_ID_YUKON_FE:
@@ -2742,6 +2860,10 @@ static int __devinit sky2_init(struct sky2_hw *hw)
2742 hw->flags = SKY2_HW_GIGABIT 2860 hw->flags = SKY2_HW_GIGABIT
2743 | SKY2_HW_NEWER_PHY 2861 | SKY2_HW_NEWER_PHY
2744 | SKY2_HW_ADV_POWER_CTL; 2862 | SKY2_HW_ADV_POWER_CTL;
2863
2864 /* check for Rev. A1 dev 4200 */
2865 if (sky2_read16(hw, Q_ADDR(Q_XA1, Q_WM)) == 0)
2866 hw->flags |= SKY2_HW_CLK_POWER;
2745 break; 2867 break;
2746 2868
2747 case CHIP_ID_YUKON_EX: 2869 case CHIP_ID_YUKON_EX:
@@ -2782,6 +2904,11 @@ static int __devinit sky2_init(struct sky2_hw *hw)
2782 | SKY2_HW_ADV_POWER_CTL; 2904 | SKY2_HW_ADV_POWER_CTL;
2783 break; 2905 break;
2784 2906
2907 case CHIP_ID_YUKON_UL_2:
2908 hw->flags = SKY2_HW_GIGABIT
2909 | SKY2_HW_ADV_POWER_CTL;
2910 break;
2911
2785 default: 2912 default:
2786 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 2913 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2787 hw->chip_id); 2914 hw->chip_id);
@@ -2792,6 +2919,11 @@ static int __devinit sky2_init(struct sky2_hw *hw)
2792 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') 2919 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2793 hw->flags |= SKY2_HW_FIBRE_PHY; 2920 hw->flags |= SKY2_HW_FIBRE_PHY;
2794 2921
2922 hw->pm_cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PM);
2923 if (hw->pm_cap == 0) {
2924 dev_err(&hw->pdev->dev, "cannot find PowerManagement capability\n");
2925 return -EIO;
2926 }
2795 2927
2796 hw->ports = 1; 2928 hw->ports = 1;
2797 t8 = sky2_read8(hw, B2_Y2_HW_RES); 2929 t8 = sky2_read8(hw, B2_Y2_HW_RES);
@@ -3379,7 +3511,7 @@ static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3379 3511
3380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3381 } else 3513 } else
3382 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 3514 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3383 PHY_M_LED_MO_DUP(mode) | 3515 PHY_M_LED_MO_DUP(mode) |
3384 PHY_M_LED_MO_10(mode) | 3516 PHY_M_LED_MO_10(mode) |
3385 PHY_M_LED_MO_100(mode) | 3517 PHY_M_LED_MO_100(mode) |
@@ -4132,12 +4264,34 @@ static int __devinit pci_wake_enabled(struct pci_dev *dev)
4132 return value & PCI_PM_CTRL_PME_ENABLE; 4264 return value & PCI_PM_CTRL_PME_ENABLE;
4133} 4265}
4134 4266
4267/* This driver supports yukon2 chipset only */
4268static const char *sky2_name(u8 chipid, char *buf, int sz)
4269{
4270 const char *name[] = {
4271 "XL", /* 0xb3 */
4272 "EC Ultra", /* 0xb4 */
4273 "Extreme", /* 0xb5 */
4274 "EC", /* 0xb6 */
4275 "FE", /* 0xb7 */
4276 "FE+", /* 0xb8 */
4277 "Supreme", /* 0xb9 */
4278 "UL 2", /* 0xba */
4279 };
4280
4281 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4282 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4283 else
4284 snprintf(buf, sz, "(chip %#x)", chipid);
4285 return buf;
4286}
4287
4135static int __devinit sky2_probe(struct pci_dev *pdev, 4288static int __devinit sky2_probe(struct pci_dev *pdev,
4136 const struct pci_device_id *ent) 4289 const struct pci_device_id *ent)
4137{ 4290{
4138 struct net_device *dev; 4291 struct net_device *dev;
4139 struct sky2_hw *hw; 4292 struct sky2_hw *hw;
4140 int err, using_dac = 0, wol_default; 4293 int err, using_dac = 0, wol_default;
4294 char buf1[16];
4141 4295
4142 err = pci_enable_device(pdev); 4296 err = pci_enable_device(pdev);
4143 if (err) { 4297 if (err) {
@@ -4208,10 +4362,10 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
4208 if (err) 4362 if (err)
4209 goto err_out_iounmap; 4363 goto err_out_iounmap;
4210 4364
4211 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n", 4365 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-2 %s rev %d\n",
4212 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0), 4366 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4213 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], 4367 pdev->irq, sky2_name(hw->chip_id, buf1, sizeof(buf1)),
4214 hw->chip_id, hw->chip_rev); 4368 hw->chip_rev);
4215 4369
4216 sky2_reset(hw); 4370 sky2_reset(hw);
4217 4371
@@ -4363,7 +4517,7 @@ static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4363 4517
4364 pci_save_state(pdev); 4518 pci_save_state(pdev);
4365 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); 4519 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4366 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 4520 sky2_power_state(hw, pci_choose_state(pdev, state));
4367 4521
4368 return 0; 4522 return 0;
4369} 4523}
@@ -4376,9 +4530,7 @@ static int sky2_resume(struct pci_dev *pdev)
4376 if (!hw) 4530 if (!hw)
4377 return 0; 4531 return 0;
4378 4532
4379 err = pci_set_power_state(pdev, PCI_D0); 4533 sky2_power_state(hw, PCI_D0);
4380 if (err)
4381 goto out;
4382 4534
4383 err = pci_restore_state(pdev); 4535 err = pci_restore_state(pdev);
4384 if (err) 4536 if (err)
@@ -4448,8 +4600,7 @@ static void sky2_shutdown(struct pci_dev *pdev)
4448 pci_enable_wake(pdev, PCI_D3cold, wol); 4600 pci_enable_wake(pdev, PCI_D3cold, wol);
4449 4601
4450 pci_disable_device(pdev); 4602 pci_disable_device(pdev);
4451 pci_set_power_state(pdev, PCI_D3hot); 4603 sky2_power_state(hw, PCI_D3hot);
4452
4453} 4604}
4454 4605
4455static struct pci_driver sky2_driver = { 4606static struct pci_driver sky2_driver = {
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index c0a5eea20007..4d9c4a19bb85 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -28,6 +28,11 @@ enum pci_dev_reg_1 {
28 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ 28 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
29 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */ 29 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
30 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */ 30 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
31
32 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
33 PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
34 PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */
35 PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
31}; 36};
32 37
33enum pci_dev_reg_2 { 38enum pci_dev_reg_2 {
@@ -45,7 +50,11 @@ enum pci_dev_reg_2 {
45 50
46/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 51/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
47enum pci_dev_reg_4 { 52enum pci_dev_reg_4 {
48 /* (Link Training & Status State Machine) */ 53 /* (Link Training & Status State Machine) */
54 P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */
55#define P_PEX_LTSSM_STAT(x) ((x << 25) & P_PEX_LTSSM_STAT_MSK)
56 P_PEX_LTSSM_L1_STAT = 0x34,
57 P_PEX_LTSSM_DET_STAT = 0x01,
49 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */ 58 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
50 /* (Active State Power Management) */ 59 /* (Active State Power Management) */
51 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */ 60 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
@@ -432,6 +441,7 @@ enum {
432 CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */ 441 CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */
433 CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */ 442 CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
434 CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */ 443 CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
444 CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
435}; 445};
436enum yukon_ec_rev { 446enum yukon_ec_rev {
437 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */ 447 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
@@ -454,6 +464,9 @@ enum yukon_ex_rev {
454 CHIP_REV_YU_EX_A0 = 1, 464 CHIP_REV_YU_EX_A0 = 1,
455 CHIP_REV_YU_EX_B0 = 2, 465 CHIP_REV_YU_EX_B0 = 2,
456}; 466};
467enum yukon_supr_rev {
468 CHIP_REV_YU_SU_A0 = 0,
469};
457 470
458 471
459/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 472/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
@@ -1143,6 +1156,12 @@ enum {
1143 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */ 1156 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1144}; 1157};
1145 1158
1159/* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
1160enum {
1161 PHY_M_PC_COP_TX_DIS = 1<<3, /* Copper Transmitter Disable */
1162 PHY_M_PC_POW_D_ENA = 1<<2, /* Power Down Enable */
1163};
1164
1146/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1165/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1147enum { 1166enum {
1148 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */ 1167 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
@@ -1411,6 +1430,7 @@ enum {
1411/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 1430/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1412enum { 1431enum {
1413 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */ 1432 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1433 PHY_M_MAC_GMIF_PUP = 1<<3, /* GMII Power Up (88E1149 only) */
1414 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */ 1434 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1415 PHY_M_MAC_MD_COPPER = 5,/* Copper only */ 1435 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1416 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ 1436 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
@@ -2052,7 +2072,9 @@ struct sky2_hw {
2052#define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */ 2072#define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */
2053#define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */ 2073#define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */
2054#define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */ 2074#define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */
2075#define SKY2_HW_CLK_POWER 0x00000100 /* clock power management */
2055 2076
2077 int pm_cap;
2056 u8 chip_id; 2078 u8 chip_id;
2057 u8 chip_rev; 2079 u8 chip_rev;
2058 u8 pmd_type; 2080 u8 pmd_type;
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index e2ee91a6ae7e..c5871624f972 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -106,55 +106,6 @@ MODULE_ALIAS("platform:smc911x");
106 */ 106 */
107#define POWER_DOWN 1 107#define POWER_DOWN 1
108 108
109
110/* store this information for the driver.. */
111struct smc911x_local {
112 /*
113 * If I have to wait until the DMA is finished and ready to reload a
114 * packet, I will store the skbuff here. Then, the DMA will send it
115 * out and free it.
116 */
117 struct sk_buff *pending_tx_skb;
118
119 /* version/revision of the SMC911x chip */
120 u16 version;
121 u16 revision;
122
123 /* FIFO sizes */
124 int tx_fifo_kb;
125 int tx_fifo_size;
126 int rx_fifo_size;
127 int afc_cfg;
128
129 /* Contains the current active receive/phy mode */
130 int ctl_rfduplx;
131 int ctl_rspeed;
132
133 u32 msg_enable;
134 u32 phy_type;
135 struct mii_if_info mii;
136
137 /* work queue */
138 struct work_struct phy_configure;
139
140 int tx_throttle;
141 spinlock_t lock;
142
143 struct net_device *netdev;
144
145#ifdef SMC_USE_DMA
146 /* DMA needs the physical address of the chip */
147 u_long physaddr;
148 int rxdma;
149 int txdma;
150 int rxdma_active;
151 int txdma_active;
152 struct sk_buff *current_rx_skb;
153 struct sk_buff *current_tx_skb;
154 struct device *dev;
155#endif
156};
157
158#if SMC_DEBUG > 0 109#if SMC_DEBUG > 0
159#define DBG(n, args...) \ 110#define DBG(n, args...) \
160 do { \ 111 do { \
@@ -202,24 +153,24 @@ static void PRINT_PKT(u_char *buf, int length)
202 153
203 154
204/* this enables an interrupt in the interrupt mask register */ 155/* this enables an interrupt in the interrupt mask register */
205#define SMC_ENABLE_INT(x) do { \ 156#define SMC_ENABLE_INT(lp, x) do { \
206 unsigned int __mask; \ 157 unsigned int __mask; \
207 unsigned long __flags; \ 158 unsigned long __flags; \
208 spin_lock_irqsave(&lp->lock, __flags); \ 159 spin_lock_irqsave(&lp->lock, __flags); \
209 __mask = SMC_GET_INT_EN(); \ 160 __mask = SMC_GET_INT_EN((lp)); \
210 __mask |= (x); \ 161 __mask |= (x); \
211 SMC_SET_INT_EN(__mask); \ 162 SMC_SET_INT_EN((lp), __mask); \
212 spin_unlock_irqrestore(&lp->lock, __flags); \ 163 spin_unlock_irqrestore(&lp->lock, __flags); \
213} while (0) 164} while (0)
214 165
215/* this disables an interrupt from the interrupt mask register */ 166/* this disables an interrupt from the interrupt mask register */
216#define SMC_DISABLE_INT(x) do { \ 167#define SMC_DISABLE_INT(lp, x) do { \
217 unsigned int __mask; \ 168 unsigned int __mask; \
218 unsigned long __flags; \ 169 unsigned long __flags; \
219 spin_lock_irqsave(&lp->lock, __flags); \ 170 spin_lock_irqsave(&lp->lock, __flags); \
220 __mask = SMC_GET_INT_EN(); \ 171 __mask = SMC_GET_INT_EN((lp)); \
221 __mask &= ~(x); \ 172 __mask &= ~(x); \
222 SMC_SET_INT_EN(__mask); \ 173 SMC_SET_INT_EN((lp), __mask); \
223 spin_unlock_irqrestore(&lp->lock, __flags); \ 174 spin_unlock_irqrestore(&lp->lock, __flags); \
224} while (0) 175} while (0)
225 176
@@ -228,7 +179,6 @@ static void PRINT_PKT(u_char *buf, int length)
228 */ 179 */
229static void smc911x_reset(struct net_device *dev) 180static void smc911x_reset(struct net_device *dev)
230{ 181{
231 unsigned long ioaddr = dev->base_addr;
232 struct smc911x_local *lp = netdev_priv(dev); 182 struct smc911x_local *lp = netdev_priv(dev);
233 unsigned int reg, timeout=0, resets=1; 183 unsigned int reg, timeout=0, resets=1;
234 unsigned long flags; 184 unsigned long flags;
@@ -236,13 +186,13 @@ static void smc911x_reset(struct net_device *dev)
236 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 186 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
237 187
238 /* Take out of PM setting first */ 188 /* Take out of PM setting first */
239 if ((SMC_GET_PMT_CTRL() & PMT_CTRL_READY_) == 0) { 189 if ((SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_) == 0) {
240 /* Write to the bytetest will take out of powerdown */ 190 /* Write to the bytetest will take out of powerdown */
241 SMC_SET_BYTE_TEST(0); 191 SMC_SET_BYTE_TEST(lp, 0);
242 timeout=10; 192 timeout=10;
243 do { 193 do {
244 udelay(10); 194 udelay(10);
245 reg = SMC_GET_PMT_CTRL() & PMT_CTRL_READY_; 195 reg = SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_;
246 } while (--timeout && !reg); 196 } while (--timeout && !reg);
247 if (timeout == 0) { 197 if (timeout == 0) {
248 PRINTK("%s: smc911x_reset timeout waiting for PM restore\n", dev->name); 198 PRINTK("%s: smc911x_reset timeout waiting for PM restore\n", dev->name);
@@ -252,15 +202,15 @@ static void smc911x_reset(struct net_device *dev)
252 202
253 /* Disable all interrupts */ 203 /* Disable all interrupts */
254 spin_lock_irqsave(&lp->lock, flags); 204 spin_lock_irqsave(&lp->lock, flags);
255 SMC_SET_INT_EN(0); 205 SMC_SET_INT_EN(lp, 0);
256 spin_unlock_irqrestore(&lp->lock, flags); 206 spin_unlock_irqrestore(&lp->lock, flags);
257 207
258 while (resets--) { 208 while (resets--) {
259 SMC_SET_HW_CFG(HW_CFG_SRST_); 209 SMC_SET_HW_CFG(lp, HW_CFG_SRST_);
260 timeout=10; 210 timeout=10;
261 do { 211 do {
262 udelay(10); 212 udelay(10);
263 reg = SMC_GET_HW_CFG(); 213 reg = SMC_GET_HW_CFG(lp);
264 /* If chip indicates reset timeout then try again */ 214 /* If chip indicates reset timeout then try again */
265 if (reg & HW_CFG_SRST_TO_) { 215 if (reg & HW_CFG_SRST_TO_) {
266 PRINTK("%s: chip reset timeout, retrying...\n", dev->name); 216 PRINTK("%s: chip reset timeout, retrying...\n", dev->name);
@@ -276,7 +226,7 @@ static void smc911x_reset(struct net_device *dev)
276 226
277 /* make sure EEPROM has finished loading before setting GPIO_CFG */ 227 /* make sure EEPROM has finished loading before setting GPIO_CFG */
278 timeout=1000; 228 timeout=1000;
279 while ( timeout-- && (SMC_GET_E2P_CMD() & E2P_CMD_EPC_BUSY_)) { 229 while ( timeout-- && (SMC_GET_E2P_CMD(lp) & E2P_CMD_EPC_BUSY_)) {
280 udelay(10); 230 udelay(10);
281 } 231 }
282 if (timeout == 0){ 232 if (timeout == 0){
@@ -285,24 +235,24 @@ static void smc911x_reset(struct net_device *dev)
285 } 235 }
286 236
287 /* Initialize interrupts */ 237 /* Initialize interrupts */
288 SMC_SET_INT_EN(0); 238 SMC_SET_INT_EN(lp, 0);
289 SMC_ACK_INT(-1); 239 SMC_ACK_INT(lp, -1);
290 240
291 /* Reset the FIFO level and flow control settings */ 241 /* Reset the FIFO level and flow control settings */
292 SMC_SET_HW_CFG((lp->tx_fifo_kb & 0xF) << 16); 242 SMC_SET_HW_CFG(lp, (lp->tx_fifo_kb & 0xF) << 16);
293//TODO: Figure out what appropriate pause time is 243//TODO: Figure out what appropriate pause time is
294 SMC_SET_FLOW(FLOW_FCPT_ | FLOW_FCEN_); 244 SMC_SET_FLOW(lp, FLOW_FCPT_ | FLOW_FCEN_);
295 SMC_SET_AFC_CFG(lp->afc_cfg); 245 SMC_SET_AFC_CFG(lp, lp->afc_cfg);
296 246
297 247
298 /* Set to LED outputs */ 248 /* Set to LED outputs */
299 SMC_SET_GPIO_CFG(0x70070000); 249 SMC_SET_GPIO_CFG(lp, 0x70070000);
300 250
301 /* 251 /*
302 * Deassert IRQ for 1*10us for edge type interrupts 252 * Deassert IRQ for 1*10us for edge type interrupts
303 * and drive IRQ pin push-pull 253 * and drive IRQ pin push-pull
304 */ 254 */
305 SMC_SET_IRQ_CFG( (1 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_ ); 255 SMC_SET_IRQ_CFG(lp, (1 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_);
306 256
307 /* clear anything saved */ 257 /* clear anything saved */
308 if (lp->pending_tx_skb != NULL) { 258 if (lp->pending_tx_skb != NULL) {
@@ -318,46 +268,45 @@ static void smc911x_reset(struct net_device *dev)
318 */ 268 */
319static void smc911x_enable(struct net_device *dev) 269static void smc911x_enable(struct net_device *dev)
320{ 270{
321 unsigned long ioaddr = dev->base_addr;
322 struct smc911x_local *lp = netdev_priv(dev); 271 struct smc911x_local *lp = netdev_priv(dev);
323 unsigned mask, cfg, cr; 272 unsigned mask, cfg, cr;
324 unsigned long flags; 273 unsigned long flags;
325 274
326 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 275 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
327 276
328 SMC_SET_MAC_ADDR(dev->dev_addr); 277 SMC_SET_MAC_ADDR(lp, dev->dev_addr);
329 278
330 /* Enable TX */ 279 /* Enable TX */
331 cfg = SMC_GET_HW_CFG(); 280 cfg = SMC_GET_HW_CFG(lp);
332 cfg &= HW_CFG_TX_FIF_SZ_ | 0xFFF; 281 cfg &= HW_CFG_TX_FIF_SZ_ | 0xFFF;
333 cfg |= HW_CFG_SF_; 282 cfg |= HW_CFG_SF_;
334 SMC_SET_HW_CFG(cfg); 283 SMC_SET_HW_CFG(lp, cfg);
335 SMC_SET_FIFO_TDA(0xFF); 284 SMC_SET_FIFO_TDA(lp, 0xFF);
336 /* Update TX stats on every 64 packets received or every 1 sec */ 285 /* Update TX stats on every 64 packets received or every 1 sec */
337 SMC_SET_FIFO_TSL(64); 286 SMC_SET_FIFO_TSL(lp, 64);
338 SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000); 287 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
339 288
340 spin_lock_irqsave(&lp->lock, flags); 289 spin_lock_irqsave(&lp->lock, flags);
341 SMC_GET_MAC_CR(cr); 290 SMC_GET_MAC_CR(lp, cr);
342 cr |= MAC_CR_TXEN_ | MAC_CR_HBDIS_; 291 cr |= MAC_CR_TXEN_ | MAC_CR_HBDIS_;
343 SMC_SET_MAC_CR(cr); 292 SMC_SET_MAC_CR(lp, cr);
344 SMC_SET_TX_CFG(TX_CFG_TX_ON_); 293 SMC_SET_TX_CFG(lp, TX_CFG_TX_ON_);
345 spin_unlock_irqrestore(&lp->lock, flags); 294 spin_unlock_irqrestore(&lp->lock, flags);
346 295
347 /* Add 2 byte padding to start of packets */ 296 /* Add 2 byte padding to start of packets */
348 SMC_SET_RX_CFG((2<<8) & RX_CFG_RXDOFF_); 297 SMC_SET_RX_CFG(lp, (2<<8) & RX_CFG_RXDOFF_);
349 298
350 /* Turn on receiver and enable RX */ 299 /* Turn on receiver and enable RX */
351 if (cr & MAC_CR_RXEN_) 300 if (cr & MAC_CR_RXEN_)
352 DBG(SMC_DEBUG_RX, "%s: Receiver already enabled\n", dev->name); 301 DBG(SMC_DEBUG_RX, "%s: Receiver already enabled\n", dev->name);
353 302
354 spin_lock_irqsave(&lp->lock, flags); 303 spin_lock_irqsave(&lp->lock, flags);
355 SMC_SET_MAC_CR( cr | MAC_CR_RXEN_ ); 304 SMC_SET_MAC_CR(lp, cr | MAC_CR_RXEN_);
356 spin_unlock_irqrestore(&lp->lock, flags); 305 spin_unlock_irqrestore(&lp->lock, flags);
357 306
358 /* Interrupt on every received packet */ 307 /* Interrupt on every received packet */
359 SMC_SET_FIFO_RSA(0x01); 308 SMC_SET_FIFO_RSA(lp, 0x01);
360 SMC_SET_FIFO_RSL(0x00); 309 SMC_SET_FIFO_RSL(lp, 0x00);
361 310
362 /* now, enable interrupts */ 311 /* now, enable interrupts */
363 mask = INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_ | INT_EN_RSFL_EN_ | 312 mask = INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_ | INT_EN_RSFL_EN_ |
@@ -368,7 +317,7 @@ static void smc911x_enable(struct net_device *dev)
368 else { 317 else {
369 mask|=INT_EN_RDFO_EN_; 318 mask|=INT_EN_RDFO_EN_;
370 } 319 }
371 SMC_ENABLE_INT(mask); 320 SMC_ENABLE_INT(lp, mask);
372} 321}
373 322
374/* 323/*
@@ -376,7 +325,6 @@ static void smc911x_enable(struct net_device *dev)
376 */ 325 */
377static void smc911x_shutdown(struct net_device *dev) 326static void smc911x_shutdown(struct net_device *dev)
378{ 327{
379 unsigned long ioaddr = dev->base_addr;
380 struct smc911x_local *lp = netdev_priv(dev); 328 struct smc911x_local *lp = netdev_priv(dev);
381 unsigned cr; 329 unsigned cr;
382 unsigned long flags; 330 unsigned long flags;
@@ -384,35 +332,35 @@ static void smc911x_shutdown(struct net_device *dev)
384 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", CARDNAME, __FUNCTION__); 332 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", CARDNAME, __FUNCTION__);
385 333
386 /* Disable IRQ's */ 334 /* Disable IRQ's */
387 SMC_SET_INT_EN(0); 335 SMC_SET_INT_EN(lp, 0);
388 336
389 /* Turn of Rx and TX */ 337 /* Turn of Rx and TX */
390 spin_lock_irqsave(&lp->lock, flags); 338 spin_lock_irqsave(&lp->lock, flags);
391 SMC_GET_MAC_CR(cr); 339 SMC_GET_MAC_CR(lp, cr);
392 cr &= ~(MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_); 340 cr &= ~(MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
393 SMC_SET_MAC_CR(cr); 341 SMC_SET_MAC_CR(lp, cr);
394 SMC_SET_TX_CFG(TX_CFG_STOP_TX_); 342 SMC_SET_TX_CFG(lp, TX_CFG_STOP_TX_);
395 spin_unlock_irqrestore(&lp->lock, flags); 343 spin_unlock_irqrestore(&lp->lock, flags);
396} 344}
397 345
398static inline void smc911x_drop_pkt(struct net_device *dev) 346static inline void smc911x_drop_pkt(struct net_device *dev)
399{ 347{
400 unsigned long ioaddr = dev->base_addr; 348 struct smc911x_local *lp = netdev_priv(dev);
401 unsigned int fifo_count, timeout, reg; 349 unsigned int fifo_count, timeout, reg;
402 350
403 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n", CARDNAME, __FUNCTION__); 351 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n", CARDNAME, __FUNCTION__);
404 fifo_count = SMC_GET_RX_FIFO_INF() & 0xFFFF; 352 fifo_count = SMC_GET_RX_FIFO_INF(lp) & 0xFFFF;
405 if (fifo_count <= 4) { 353 if (fifo_count <= 4) {
406 /* Manually dump the packet data */ 354 /* Manually dump the packet data */
407 while (fifo_count--) 355 while (fifo_count--)
408 SMC_GET_RX_FIFO(); 356 SMC_GET_RX_FIFO(lp);
409 } else { 357 } else {
410 /* Fast forward through the bad packet */ 358 /* Fast forward through the bad packet */
411 SMC_SET_RX_DP_CTRL(RX_DP_CTRL_FFWD_BUSY_); 359 SMC_SET_RX_DP_CTRL(lp, RX_DP_CTRL_FFWD_BUSY_);
412 timeout=50; 360 timeout=50;
413 do { 361 do {
414 udelay(10); 362 udelay(10);
415 reg = SMC_GET_RX_DP_CTRL() & RX_DP_CTRL_FFWD_BUSY_; 363 reg = SMC_GET_RX_DP_CTRL(lp) & RX_DP_CTRL_FFWD_BUSY_;
416 } while (--timeout && reg); 364 } while (--timeout && reg);
417 if (timeout == 0) { 365 if (timeout == 0) {
418 PRINTK("%s: timeout waiting for RX fast forward\n", dev->name); 366 PRINTK("%s: timeout waiting for RX fast forward\n", dev->name);
@@ -428,14 +376,14 @@ static inline void smc911x_drop_pkt(struct net_device *dev)
428 */ 376 */
429static inline void smc911x_rcv(struct net_device *dev) 377static inline void smc911x_rcv(struct net_device *dev)
430{ 378{
431 unsigned long ioaddr = dev->base_addr; 379 struct smc911x_local *lp = netdev_priv(dev);
432 unsigned int pkt_len, status; 380 unsigned int pkt_len, status;
433 struct sk_buff *skb; 381 struct sk_buff *skb;
434 unsigned char *data; 382 unsigned char *data;
435 383
436 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n", 384 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n",
437 dev->name, __FUNCTION__); 385 dev->name, __FUNCTION__);
438 status = SMC_GET_RX_STS_FIFO(); 386 status = SMC_GET_RX_STS_FIFO(lp);
439 DBG(SMC_DEBUG_RX, "%s: Rx pkt len %d status 0x%08x \n", 387 DBG(SMC_DEBUG_RX, "%s: Rx pkt len %d status 0x%08x \n",
440 dev->name, (status & 0x3fff0000) >> 16, status & 0xc000ffff); 388 dev->name, (status & 0x3fff0000) >> 16, status & 0xc000ffff);
441 pkt_len = (status & RX_STS_PKT_LEN_) >> 16; 389 pkt_len = (status & RX_STS_PKT_LEN_) >> 16;
@@ -472,24 +420,23 @@ static inline void smc911x_rcv(struct net_device *dev)
472 skb_put(skb,pkt_len-4); 420 skb_put(skb,pkt_len-4);
473#ifdef SMC_USE_DMA 421#ifdef SMC_USE_DMA
474 { 422 {
475 struct smc911x_local *lp = netdev_priv(dev);
476 unsigned int fifo; 423 unsigned int fifo;
477 /* Lower the FIFO threshold if possible */ 424 /* Lower the FIFO threshold if possible */
478 fifo = SMC_GET_FIFO_INT(); 425 fifo = SMC_GET_FIFO_INT(lp);
479 if (fifo & 0xFF) fifo--; 426 if (fifo & 0xFF) fifo--;
480 DBG(SMC_DEBUG_RX, "%s: Setting RX stat FIFO threshold to %d\n", 427 DBG(SMC_DEBUG_RX, "%s: Setting RX stat FIFO threshold to %d\n",
481 dev->name, fifo & 0xff); 428 dev->name, fifo & 0xff);
482 SMC_SET_FIFO_INT(fifo); 429 SMC_SET_FIFO_INT(lp, fifo);
483 /* Setup RX DMA */ 430 /* Setup RX DMA */
484 SMC_SET_RX_CFG(RX_CFG_RX_END_ALGN16_ | ((2<<8) & RX_CFG_RXDOFF_)); 431 SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN16_ | ((2<<8) & RX_CFG_RXDOFF_));
485 lp->rxdma_active = 1; 432 lp->rxdma_active = 1;
486 lp->current_rx_skb = skb; 433 lp->current_rx_skb = skb;
487 SMC_PULL_DATA(data, (pkt_len+2+15) & ~15); 434 SMC_PULL_DATA(lp, data, (pkt_len+2+15) & ~15);
488 /* Packet processing deferred to DMA RX interrupt */ 435 /* Packet processing deferred to DMA RX interrupt */
489 } 436 }
490#else 437#else
491 SMC_SET_RX_CFG(RX_CFG_RX_END_ALGN4_ | ((2<<8) & RX_CFG_RXDOFF_)); 438 SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN4_ | ((2<<8) & RX_CFG_RXDOFF_));
492 SMC_PULL_DATA(data, pkt_len+2+3); 439 SMC_PULL_DATA(lp, data, pkt_len+2+3);
493 440
494 DBG(SMC_DEBUG_PKTS, "%s: Received packet\n", dev->name); 441 DBG(SMC_DEBUG_PKTS, "%s: Received packet\n", dev->name);
495 PRINT_PKT(data, ((pkt_len - 4) <= 64) ? pkt_len - 4 : 64); 442 PRINT_PKT(data, ((pkt_len - 4) <= 64) ? pkt_len - 4 : 64);
@@ -508,7 +455,6 @@ static inline void smc911x_rcv(struct net_device *dev)
508static void smc911x_hardware_send_pkt(struct net_device *dev) 455static void smc911x_hardware_send_pkt(struct net_device *dev)
509{ 456{
510 struct smc911x_local *lp = netdev_priv(dev); 457 struct smc911x_local *lp = netdev_priv(dev);
511 unsigned long ioaddr = dev->base_addr;
512 struct sk_buff *skb; 458 struct sk_buff *skb;
513 unsigned int cmdA, cmdB, len; 459 unsigned int cmdA, cmdB, len;
514 unsigned char *buf; 460 unsigned char *buf;
@@ -541,8 +487,8 @@ static void smc911x_hardware_send_pkt(struct net_device *dev)
541 487
542 DBG(SMC_DEBUG_TX, "%s: TX PKT LENGTH 0x%04x (%d) BUF 0x%p CMDA 0x%08x CMDB 0x%08x\n", 488 DBG(SMC_DEBUG_TX, "%s: TX PKT LENGTH 0x%04x (%d) BUF 0x%p CMDA 0x%08x CMDB 0x%08x\n",
543 dev->name, len, len, buf, cmdA, cmdB); 489 dev->name, len, len, buf, cmdA, cmdB);
544 SMC_SET_TX_FIFO(cmdA); 490 SMC_SET_TX_FIFO(lp, cmdA);
545 SMC_SET_TX_FIFO(cmdB); 491 SMC_SET_TX_FIFO(lp, cmdB);
546 492
547 DBG(SMC_DEBUG_PKTS, "%s: Transmitted packet\n", dev->name); 493 DBG(SMC_DEBUG_PKTS, "%s: Transmitted packet\n", dev->name);
548 PRINT_PKT(buf, len <= 64 ? len : 64); 494 PRINT_PKT(buf, len <= 64 ? len : 64);
@@ -550,10 +496,10 @@ static void smc911x_hardware_send_pkt(struct net_device *dev)
550 /* Send pkt via PIO or DMA */ 496 /* Send pkt via PIO or DMA */
551#ifdef SMC_USE_DMA 497#ifdef SMC_USE_DMA
552 lp->current_tx_skb = skb; 498 lp->current_tx_skb = skb;
553 SMC_PUSH_DATA(buf, len); 499 SMC_PUSH_DATA(lp, buf, len);
554 /* DMA complete IRQ will free buffer and set jiffies */ 500 /* DMA complete IRQ will free buffer and set jiffies */
555#else 501#else
556 SMC_PUSH_DATA(buf, len); 502 SMC_PUSH_DATA(lp, buf, len);
557 dev->trans_start = jiffies; 503 dev->trans_start = jiffies;
558 dev_kfree_skb(skb); 504 dev_kfree_skb(skb);
559#endif 505#endif
@@ -562,7 +508,7 @@ static void smc911x_hardware_send_pkt(struct net_device *dev)
562 netif_wake_queue(dev); 508 netif_wake_queue(dev);
563 } 509 }
564 spin_unlock_irqrestore(&lp->lock, flags); 510 spin_unlock_irqrestore(&lp->lock, flags);
565 SMC_ENABLE_INT(INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_); 511 SMC_ENABLE_INT(lp, INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_);
566} 512}
567 513
568/* 514/*
@@ -574,7 +520,6 @@ static void smc911x_hardware_send_pkt(struct net_device *dev)
574static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) 520static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
575{ 521{
576 struct smc911x_local *lp = netdev_priv(dev); 522 struct smc911x_local *lp = netdev_priv(dev);
577 unsigned long ioaddr = dev->base_addr;
578 unsigned int free; 523 unsigned int free;
579 unsigned long flags; 524 unsigned long flags;
580 525
@@ -583,7 +528,7 @@ static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
583 528
584 BUG_ON(lp->pending_tx_skb != NULL); 529 BUG_ON(lp->pending_tx_skb != NULL);
585 530
586 free = SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TDFREE_; 531 free = SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TDFREE_;
587 DBG(SMC_DEBUG_TX, "%s: TX free space %d\n", dev->name, free); 532 DBG(SMC_DEBUG_TX, "%s: TX free space %d\n", dev->name, free);
588 533
589 /* Turn off the flow when running out of space in FIFO */ 534 /* Turn off the flow when running out of space in FIFO */
@@ -592,7 +537,7 @@ static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
592 dev->name, free); 537 dev->name, free);
593 spin_lock_irqsave(&lp->lock, flags); 538 spin_lock_irqsave(&lp->lock, flags);
594 /* Reenable when at least 1 packet of size MTU present */ 539 /* Reenable when at least 1 packet of size MTU present */
595 SMC_SET_FIFO_TDA((SMC911X_TX_FIFO_LOW_THRESHOLD)/64); 540 SMC_SET_FIFO_TDA(lp, (SMC911X_TX_FIFO_LOW_THRESHOLD)/64);
596 lp->tx_throttle = 1; 541 lp->tx_throttle = 1;
597 netif_stop_queue(dev); 542 netif_stop_queue(dev);
598 spin_unlock_irqrestore(&lp->lock, flags); 543 spin_unlock_irqrestore(&lp->lock, flags);
@@ -647,7 +592,6 @@ static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
647 */ 592 */
648static void smc911x_tx(struct net_device *dev) 593static void smc911x_tx(struct net_device *dev)
649{ 594{
650 unsigned long ioaddr = dev->base_addr;
651 struct smc911x_local *lp = netdev_priv(dev); 595 struct smc911x_local *lp = netdev_priv(dev);
652 unsigned int tx_status; 596 unsigned int tx_status;
653 597
@@ -655,11 +599,11 @@ static void smc911x_tx(struct net_device *dev)
655 dev->name, __FUNCTION__); 599 dev->name, __FUNCTION__);
656 600
657 /* Collect the TX status */ 601 /* Collect the TX status */
658 while (((SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TSUSED_) >> 16) != 0) { 602 while (((SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16) != 0) {
659 DBG(SMC_DEBUG_TX, "%s: Tx stat FIFO used 0x%04x\n", 603 DBG(SMC_DEBUG_TX, "%s: Tx stat FIFO used 0x%04x\n",
660 dev->name, 604 dev->name,
661 (SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TSUSED_) >> 16); 605 (SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16);
662 tx_status = SMC_GET_TX_STS_FIFO(); 606 tx_status = SMC_GET_TX_STS_FIFO(lp);
663 dev->stats.tx_packets++; 607 dev->stats.tx_packets++;
664 dev->stats.tx_bytes+=tx_status>>16; 608 dev->stats.tx_bytes+=tx_status>>16;
665 DBG(SMC_DEBUG_TX, "%s: Tx FIFO tag 0x%04x status 0x%04x\n", 609 DBG(SMC_DEBUG_TX, "%s: Tx FIFO tag 0x%04x status 0x%04x\n",
@@ -697,10 +641,10 @@ static void smc911x_tx(struct net_device *dev)
697 641
698static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg) 642static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg)
699{ 643{
700 unsigned long ioaddr = dev->base_addr; 644 struct smc911x_local *lp = netdev_priv(dev);
701 unsigned int phydata; 645 unsigned int phydata;
702 646
703 SMC_GET_MII(phyreg, phyaddr, phydata); 647 SMC_GET_MII(lp, phyreg, phyaddr, phydata);
704 648
705 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%02x, phydata=0x%04x\n", 649 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%02x, phydata=0x%04x\n",
706 __FUNCTION__, phyaddr, phyreg, phydata); 650 __FUNCTION__, phyaddr, phyreg, phydata);
@@ -714,12 +658,12 @@ static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg)
714static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg, 658static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg,
715 int phydata) 659 int phydata)
716{ 660{
717 unsigned long ioaddr = dev->base_addr; 661 struct smc911x_local *lp = netdev_priv(dev);
718 662
719 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 663 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
720 __FUNCTION__, phyaddr, phyreg, phydata); 664 __FUNCTION__, phyaddr, phyreg, phydata);
721 665
722 SMC_SET_MII(phyreg, phyaddr, phydata); 666 SMC_SET_MII(lp, phyreg, phyaddr, phydata);
723} 667}
724 668
725/* 669/*
@@ -728,7 +672,6 @@ static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg,
728 */ 672 */
729static void smc911x_phy_detect(struct net_device *dev) 673static void smc911x_phy_detect(struct net_device *dev)
730{ 674{
731 unsigned long ioaddr = dev->base_addr;
732 struct smc911x_local *lp = netdev_priv(dev); 675 struct smc911x_local *lp = netdev_priv(dev);
733 int phyaddr; 676 int phyaddr;
734 unsigned int cfg, id1, id2; 677 unsigned int cfg, id1, id2;
@@ -744,30 +687,30 @@ static void smc911x_phy_detect(struct net_device *dev)
744 switch(lp->version) { 687 switch(lp->version) {
745 case 0x115: 688 case 0x115:
746 case 0x117: 689 case 0x117:
747 cfg = SMC_GET_HW_CFG(); 690 cfg = SMC_GET_HW_CFG(lp);
748 if (cfg & HW_CFG_EXT_PHY_DET_) { 691 if (cfg & HW_CFG_EXT_PHY_DET_) {
749 cfg &= ~HW_CFG_PHY_CLK_SEL_; 692 cfg &= ~HW_CFG_PHY_CLK_SEL_;
750 cfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_; 693 cfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
751 SMC_SET_HW_CFG(cfg); 694 SMC_SET_HW_CFG(lp, cfg);
752 udelay(10); /* Wait for clocks to stop */ 695 udelay(10); /* Wait for clocks to stop */
753 696
754 cfg |= HW_CFG_EXT_PHY_EN_; 697 cfg |= HW_CFG_EXT_PHY_EN_;
755 SMC_SET_HW_CFG(cfg); 698 SMC_SET_HW_CFG(lp, cfg);
756 udelay(10); /* Wait for clocks to stop */ 699 udelay(10); /* Wait for clocks to stop */
757 700
758 cfg &= ~HW_CFG_PHY_CLK_SEL_; 701 cfg &= ~HW_CFG_PHY_CLK_SEL_;
759 cfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_; 702 cfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
760 SMC_SET_HW_CFG(cfg); 703 SMC_SET_HW_CFG(lp, cfg);
761 udelay(10); /* Wait for clocks to stop */ 704 udelay(10); /* Wait for clocks to stop */
762 705
763 cfg |= HW_CFG_SMI_SEL_; 706 cfg |= HW_CFG_SMI_SEL_;
764 SMC_SET_HW_CFG(cfg); 707 SMC_SET_HW_CFG(lp, cfg);
765 708
766 for (phyaddr = 1; phyaddr < 32; ++phyaddr) { 709 for (phyaddr = 1; phyaddr < 32; ++phyaddr) {
767 710
768 /* Read the PHY identifiers */ 711 /* Read the PHY identifiers */
769 SMC_GET_PHY_ID1(phyaddr & 31, id1); 712 SMC_GET_PHY_ID1(lp, phyaddr & 31, id1);
770 SMC_GET_PHY_ID2(phyaddr & 31, id2); 713 SMC_GET_PHY_ID2(lp, phyaddr & 31, id2);
771 714
772 /* Make sure it is a valid identifier */ 715 /* Make sure it is a valid identifier */
773 if (id1 != 0x0000 && id1 != 0xffff && 716 if (id1 != 0x0000 && id1 != 0xffff &&
@@ -782,8 +725,8 @@ static void smc911x_phy_detect(struct net_device *dev)
782 } 725 }
783 default: 726 default:
784 /* Internal media only */ 727 /* Internal media only */
785 SMC_GET_PHY_ID1(1, id1); 728 SMC_GET_PHY_ID1(lp, 1, id1);
786 SMC_GET_PHY_ID2(1, id2); 729 SMC_GET_PHY_ID2(lp, 1, id2);
787 /* Save the PHY's address */ 730 /* Save the PHY's address */
788 lp->mii.phy_id = 1; 731 lp->mii.phy_id = 1;
789 lp->phy_type = id1 << 16 | id2; 732 lp->phy_type = id1 << 16 | id2;
@@ -800,16 +743,15 @@ static void smc911x_phy_detect(struct net_device *dev)
800static int smc911x_phy_fixed(struct net_device *dev) 743static int smc911x_phy_fixed(struct net_device *dev)
801{ 744{
802 struct smc911x_local *lp = netdev_priv(dev); 745 struct smc911x_local *lp = netdev_priv(dev);
803 unsigned long ioaddr = dev->base_addr;
804 int phyaddr = lp->mii.phy_id; 746 int phyaddr = lp->mii.phy_id;
805 int bmcr; 747 int bmcr;
806 748
807 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 749 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
808 750
809 /* Enter Link Disable state */ 751 /* Enter Link Disable state */
810 SMC_GET_PHY_BMCR(phyaddr, bmcr); 752 SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
811 bmcr |= BMCR_PDOWN; 753 bmcr |= BMCR_PDOWN;
812 SMC_SET_PHY_BMCR(phyaddr, bmcr); 754 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
813 755
814 /* 756 /*
815 * Set our fixed capabilities 757 * Set our fixed capabilities
@@ -823,11 +765,11 @@ static int smc911x_phy_fixed(struct net_device *dev)
823 bmcr |= BMCR_SPEED100; 765 bmcr |= BMCR_SPEED100;
824 766
825 /* Write our capabilities to the phy control register */ 767 /* Write our capabilities to the phy control register */
826 SMC_SET_PHY_BMCR(phyaddr, bmcr); 768 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
827 769
828 /* Re-Configure the Receive/Phy Control register */ 770 /* Re-Configure the Receive/Phy Control register */
829 bmcr &= ~BMCR_PDOWN; 771 bmcr &= ~BMCR_PDOWN;
830 SMC_SET_PHY_BMCR(phyaddr, bmcr); 772 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
831 773
832 return 1; 774 return 1;
833} 775}
@@ -847,7 +789,6 @@ static int smc911x_phy_fixed(struct net_device *dev)
847static int smc911x_phy_reset(struct net_device *dev, int phy) 789static int smc911x_phy_reset(struct net_device *dev, int phy)
848{ 790{
849 struct smc911x_local *lp = netdev_priv(dev); 791 struct smc911x_local *lp = netdev_priv(dev);
850 unsigned long ioaddr = dev->base_addr;
851 int timeout; 792 int timeout;
852 unsigned long flags; 793 unsigned long flags;
853 unsigned int reg; 794 unsigned int reg;
@@ -855,15 +796,15 @@ static int smc911x_phy_reset(struct net_device *dev, int phy)
855 DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __FUNCTION__); 796 DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __FUNCTION__);
856 797
857 spin_lock_irqsave(&lp->lock, flags); 798 spin_lock_irqsave(&lp->lock, flags);
858 reg = SMC_GET_PMT_CTRL(); 799 reg = SMC_GET_PMT_CTRL(lp);
859 reg &= ~0xfffff030; 800 reg &= ~0xfffff030;
860 reg |= PMT_CTRL_PHY_RST_; 801 reg |= PMT_CTRL_PHY_RST_;
861 SMC_SET_PMT_CTRL(reg); 802 SMC_SET_PMT_CTRL(lp, reg);
862 spin_unlock_irqrestore(&lp->lock, flags); 803 spin_unlock_irqrestore(&lp->lock, flags);
863 for (timeout = 2; timeout; timeout--) { 804 for (timeout = 2; timeout; timeout--) {
864 msleep(50); 805 msleep(50);
865 spin_lock_irqsave(&lp->lock, flags); 806 spin_lock_irqsave(&lp->lock, flags);
866 reg = SMC_GET_PMT_CTRL(); 807 reg = SMC_GET_PMT_CTRL(lp);
867 spin_unlock_irqrestore(&lp->lock, flags); 808 spin_unlock_irqrestore(&lp->lock, flags);
868 if (!(reg & PMT_CTRL_PHY_RST_)) { 809 if (!(reg & PMT_CTRL_PHY_RST_)) {
869 /* extra delay required because the phy may 810 /* extra delay required because the phy may
@@ -888,13 +829,13 @@ static int smc911x_phy_reset(struct net_device *dev, int phy)
888 */ 829 */
889static void smc911x_phy_powerdown(struct net_device *dev, int phy) 830static void smc911x_phy_powerdown(struct net_device *dev, int phy)
890{ 831{
891 unsigned long ioaddr = dev->base_addr; 832 struct smc911x_local *lp = netdev_priv(dev);
892 unsigned int bmcr; 833 unsigned int bmcr;
893 834
894 /* Enter Link Disable state */ 835 /* Enter Link Disable state */
895 SMC_GET_PHY_BMCR(phy, bmcr); 836 SMC_GET_PHY_BMCR(lp, phy, bmcr);
896 bmcr |= BMCR_PDOWN; 837 bmcr |= BMCR_PDOWN;
897 SMC_SET_PHY_BMCR(phy, bmcr); 838 SMC_SET_PHY_BMCR(lp, phy, bmcr);
898} 839}
899 840
900/* 841/*
@@ -908,7 +849,6 @@ static void smc911x_phy_powerdown(struct net_device *dev, int phy)
908static void smc911x_phy_check_media(struct net_device *dev, int init) 849static void smc911x_phy_check_media(struct net_device *dev, int init)
909{ 850{
910 struct smc911x_local *lp = netdev_priv(dev); 851 struct smc911x_local *lp = netdev_priv(dev);
911 unsigned long ioaddr = dev->base_addr;
912 int phyaddr = lp->mii.phy_id; 852 int phyaddr = lp->mii.phy_id;
913 unsigned int bmcr, cr; 853 unsigned int bmcr, cr;
914 854
@@ -916,8 +856,8 @@ static void smc911x_phy_check_media(struct net_device *dev, int init)
916 856
917 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { 857 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
918 /* duplex state has changed */ 858 /* duplex state has changed */
919 SMC_GET_PHY_BMCR(phyaddr, bmcr); 859 SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
920 SMC_GET_MAC_CR(cr); 860 SMC_GET_MAC_CR(lp, cr);
921 if (lp->mii.full_duplex) { 861 if (lp->mii.full_duplex) {
922 DBG(SMC_DEBUG_MISC, "%s: Configuring for full-duplex mode\n", dev->name); 862 DBG(SMC_DEBUG_MISC, "%s: Configuring for full-duplex mode\n", dev->name);
923 bmcr |= BMCR_FULLDPLX; 863 bmcr |= BMCR_FULLDPLX;
@@ -927,8 +867,8 @@ static void smc911x_phy_check_media(struct net_device *dev, int init)
927 bmcr &= ~BMCR_FULLDPLX; 867 bmcr &= ~BMCR_FULLDPLX;
928 cr &= ~MAC_CR_RCVOWN_; 868 cr &= ~MAC_CR_RCVOWN_;
929 } 869 }
930 SMC_SET_PHY_BMCR(phyaddr, bmcr); 870 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
931 SMC_SET_MAC_CR(cr); 871 SMC_SET_MAC_CR(lp, cr);
932 } 872 }
933} 873}
934 874
@@ -946,7 +886,6 @@ static void smc911x_phy_configure(struct work_struct *work)
946 struct smc911x_local *lp = container_of(work, struct smc911x_local, 886 struct smc911x_local *lp = container_of(work, struct smc911x_local,
947 phy_configure); 887 phy_configure);
948 struct net_device *dev = lp->netdev; 888 struct net_device *dev = lp->netdev;
949 unsigned long ioaddr = dev->base_addr;
950 int phyaddr = lp->mii.phy_id; 889 int phyaddr = lp->mii.phy_id;
951 int my_phy_caps; /* My PHY capabilities */ 890 int my_phy_caps; /* My PHY capabilities */
952 int my_ad_caps; /* My Advertised capabilities */ 891 int my_ad_caps; /* My Advertised capabilities */
@@ -971,7 +910,7 @@ static void smc911x_phy_configure(struct work_struct *work)
971 * Enable PHY Interrupts (for register 18) 910 * Enable PHY Interrupts (for register 18)
972 * Interrupts listed here are enabled 911 * Interrupts listed here are enabled
973 */ 912 */
974 SMC_SET_PHY_INT_MASK(phyaddr, PHY_INT_MASK_ENERGY_ON_ | 913 SMC_SET_PHY_INT_MASK(lp, phyaddr, PHY_INT_MASK_ENERGY_ON_ |
975 PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_REMOTE_FAULT_ | 914 PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_REMOTE_FAULT_ |
976 PHY_INT_MASK_LINK_DOWN_); 915 PHY_INT_MASK_LINK_DOWN_);
977 916
@@ -982,7 +921,7 @@ static void smc911x_phy_configure(struct work_struct *work)
982 } 921 }
983 922
984 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ 923 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
985 SMC_GET_PHY_BMSR(phyaddr, my_phy_caps); 924 SMC_GET_PHY_BMSR(lp, phyaddr, my_phy_caps);
986 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { 925 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
987 printk(KERN_INFO "Auto negotiation NOT supported\n"); 926 printk(KERN_INFO "Auto negotiation NOT supported\n");
988 smc911x_phy_fixed(dev); 927 smc911x_phy_fixed(dev);
@@ -1011,7 +950,7 @@ static void smc911x_phy_configure(struct work_struct *work)
1011 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); 950 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
1012 951
1013 /* Update our Auto-Neg Advertisement Register */ 952 /* Update our Auto-Neg Advertisement Register */
1014 SMC_SET_PHY_MII_ADV(phyaddr, my_ad_caps); 953 SMC_SET_PHY_MII_ADV(lp, phyaddr, my_ad_caps);
1015 lp->mii.advertising = my_ad_caps; 954 lp->mii.advertising = my_ad_caps;
1016 955
1017 /* 956 /*
@@ -1020,13 +959,13 @@ static void smc911x_phy_configure(struct work_struct *work)
1020 * the link does not come up. 959 * the link does not come up.
1021 */ 960 */
1022 udelay(10); 961 udelay(10);
1023 SMC_GET_PHY_MII_ADV(phyaddr, status); 962 SMC_GET_PHY_MII_ADV(lp, phyaddr, status);
1024 963
1025 DBG(SMC_DEBUG_MISC, "%s: phy caps=0x%04x\n", dev->name, my_phy_caps); 964 DBG(SMC_DEBUG_MISC, "%s: phy caps=0x%04x\n", dev->name, my_phy_caps);
1026 DBG(SMC_DEBUG_MISC, "%s: phy advertised caps=0x%04x\n", dev->name, my_ad_caps); 965 DBG(SMC_DEBUG_MISC, "%s: phy advertised caps=0x%04x\n", dev->name, my_ad_caps);
1027 966
1028 /* Restart auto-negotiation process in order to advertise my caps */ 967 /* Restart auto-negotiation process in order to advertise my caps */
1029 SMC_SET_PHY_BMCR(phyaddr, BMCR_ANENABLE | BMCR_ANRESTART); 968 SMC_SET_PHY_BMCR(lp, phyaddr, BMCR_ANENABLE | BMCR_ANRESTART);
1030 969
1031 smc911x_phy_check_media(dev, 1); 970 smc911x_phy_check_media(dev, 1);
1032 971
@@ -1043,7 +982,6 @@ smc911x_phy_configure_exit:
1043static void smc911x_phy_interrupt(struct net_device *dev) 982static void smc911x_phy_interrupt(struct net_device *dev)
1044{ 983{
1045 struct smc911x_local *lp = netdev_priv(dev); 984 struct smc911x_local *lp = netdev_priv(dev);
1046 unsigned long ioaddr = dev->base_addr;
1047 int phyaddr = lp->mii.phy_id; 985 int phyaddr = lp->mii.phy_id;
1048 int status; 986 int status;
1049 987
@@ -1054,11 +992,11 @@ static void smc911x_phy_interrupt(struct net_device *dev)
1054 992
1055 smc911x_phy_check_media(dev, 0); 993 smc911x_phy_check_media(dev, 0);
1056 /* read to clear status bits */ 994 /* read to clear status bits */
1057 SMC_GET_PHY_INT_SRC(phyaddr,status); 995 SMC_GET_PHY_INT_SRC(lp, phyaddr,status);
1058 DBG(SMC_DEBUG_MISC, "%s: PHY interrupt status 0x%04x\n", 996 DBG(SMC_DEBUG_MISC, "%s: PHY interrupt status 0x%04x\n",
1059 dev->name, status & 0xffff); 997 dev->name, status & 0xffff);
1060 DBG(SMC_DEBUG_MISC, "%s: AFC_CFG 0x%08x\n", 998 DBG(SMC_DEBUG_MISC, "%s: AFC_CFG 0x%08x\n",
1061 dev->name, SMC_GET_AFC_CFG()); 999 dev->name, SMC_GET_AFC_CFG(lp));
1062} 1000}
1063 1001
1064/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ 1002/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
@@ -1070,7 +1008,6 @@ static void smc911x_phy_interrupt(struct net_device *dev)
1070static irqreturn_t smc911x_interrupt(int irq, void *dev_id) 1008static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
1071{ 1009{
1072 struct net_device *dev = dev_id; 1010 struct net_device *dev = dev_id;
1073 unsigned long ioaddr = dev->base_addr;
1074 struct smc911x_local *lp = netdev_priv(dev); 1011 struct smc911x_local *lp = netdev_priv(dev);
1075 unsigned int status, mask, timeout; 1012 unsigned int status, mask, timeout;
1076 unsigned int rx_overrun=0, cr, pkts; 1013 unsigned int rx_overrun=0, cr, pkts;
@@ -1081,21 +1018,21 @@ static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
1081 spin_lock_irqsave(&lp->lock, flags); 1018 spin_lock_irqsave(&lp->lock, flags);
1082 1019
1083 /* Spurious interrupt check */ 1020 /* Spurious interrupt check */
1084 if ((SMC_GET_IRQ_CFG() & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) != 1021 if ((SMC_GET_IRQ_CFG(lp) & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) !=
1085 (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) { 1022 (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) {
1086 spin_unlock_irqrestore(&lp->lock, flags); 1023 spin_unlock_irqrestore(&lp->lock, flags);
1087 return IRQ_NONE; 1024 return IRQ_NONE;
1088 } 1025 }
1089 1026
1090 mask = SMC_GET_INT_EN(); 1027 mask = SMC_GET_INT_EN(lp);
1091 SMC_SET_INT_EN(0); 1028 SMC_SET_INT_EN(lp, 0);
1092 1029
1093 /* set a timeout value, so I don't stay here forever */ 1030 /* set a timeout value, so I don't stay here forever */
1094 timeout = 8; 1031 timeout = 8;
1095 1032
1096 1033
1097 do { 1034 do {
1098 status = SMC_GET_INT(); 1035 status = SMC_GET_INT(lp);
1099 1036
1100 DBG(SMC_DEBUG_MISC, "%s: INT 0x%08x MASK 0x%08x OUTSIDE MASK 0x%08x\n", 1037 DBG(SMC_DEBUG_MISC, "%s: INT 0x%08x MASK 0x%08x OUTSIDE MASK 0x%08x\n",
1101 dev->name, status, mask, status & ~mask); 1038 dev->name, status, mask, status & ~mask);
@@ -1106,53 +1043,53 @@ static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
1106 1043
1107 /* Handle SW interrupt condition */ 1044 /* Handle SW interrupt condition */
1108 if (status & INT_STS_SW_INT_) { 1045 if (status & INT_STS_SW_INT_) {
1109 SMC_ACK_INT(INT_STS_SW_INT_); 1046 SMC_ACK_INT(lp, INT_STS_SW_INT_);
1110 mask &= ~INT_EN_SW_INT_EN_; 1047 mask &= ~INT_EN_SW_INT_EN_;
1111 } 1048 }
1112 /* Handle various error conditions */ 1049 /* Handle various error conditions */
1113 if (status & INT_STS_RXE_) { 1050 if (status & INT_STS_RXE_) {
1114 SMC_ACK_INT(INT_STS_RXE_); 1051 SMC_ACK_INT(lp, INT_STS_RXE_);
1115 dev->stats.rx_errors++; 1052 dev->stats.rx_errors++;
1116 } 1053 }
1117 if (status & INT_STS_RXDFH_INT_) { 1054 if (status & INT_STS_RXDFH_INT_) {
1118 SMC_ACK_INT(INT_STS_RXDFH_INT_); 1055 SMC_ACK_INT(lp, INT_STS_RXDFH_INT_);
1119 dev->stats.rx_dropped+=SMC_GET_RX_DROP(); 1056 dev->stats.rx_dropped+=SMC_GET_RX_DROP(lp);
1120 } 1057 }
1121 /* Undocumented interrupt-what is the right thing to do here? */ 1058 /* Undocumented interrupt-what is the right thing to do here? */
1122 if (status & INT_STS_RXDF_INT_) { 1059 if (status & INT_STS_RXDF_INT_) {
1123 SMC_ACK_INT(INT_STS_RXDF_INT_); 1060 SMC_ACK_INT(lp, INT_STS_RXDF_INT_);
1124 } 1061 }
1125 1062
1126 /* Rx Data FIFO exceeds set level */ 1063 /* Rx Data FIFO exceeds set level */
1127 if (status & INT_STS_RDFL_) { 1064 if (status & INT_STS_RDFL_) {
1128 if (IS_REV_A(lp->revision)) { 1065 if (IS_REV_A(lp->revision)) {
1129 rx_overrun=1; 1066 rx_overrun=1;
1130 SMC_GET_MAC_CR(cr); 1067 SMC_GET_MAC_CR(lp, cr);
1131 cr &= ~MAC_CR_RXEN_; 1068 cr &= ~MAC_CR_RXEN_;
1132 SMC_SET_MAC_CR(cr); 1069 SMC_SET_MAC_CR(lp, cr);
1133 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name); 1070 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
1134 dev->stats.rx_errors++; 1071 dev->stats.rx_errors++;
1135 dev->stats.rx_fifo_errors++; 1072 dev->stats.rx_fifo_errors++;
1136 } 1073 }
1137 SMC_ACK_INT(INT_STS_RDFL_); 1074 SMC_ACK_INT(lp, INT_STS_RDFL_);
1138 } 1075 }
1139 if (status & INT_STS_RDFO_) { 1076 if (status & INT_STS_RDFO_) {
1140 if (!IS_REV_A(lp->revision)) { 1077 if (!IS_REV_A(lp->revision)) {
1141 SMC_GET_MAC_CR(cr); 1078 SMC_GET_MAC_CR(lp, cr);
1142 cr &= ~MAC_CR_RXEN_; 1079 cr &= ~MAC_CR_RXEN_;
1143 SMC_SET_MAC_CR(cr); 1080 SMC_SET_MAC_CR(lp, cr);
1144 rx_overrun=1; 1081 rx_overrun=1;
1145 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name); 1082 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
1146 dev->stats.rx_errors++; 1083 dev->stats.rx_errors++;
1147 dev->stats.rx_fifo_errors++; 1084 dev->stats.rx_fifo_errors++;
1148 } 1085 }
1149 SMC_ACK_INT(INT_STS_RDFO_); 1086 SMC_ACK_INT(lp, INT_STS_RDFO_);
1150 } 1087 }
1151 /* Handle receive condition */ 1088 /* Handle receive condition */
1152 if ((status & INT_STS_RSFL_) || rx_overrun) { 1089 if ((status & INT_STS_RSFL_) || rx_overrun) {
1153 unsigned int fifo; 1090 unsigned int fifo;
1154 DBG(SMC_DEBUG_RX, "%s: RX irq\n", dev->name); 1091 DBG(SMC_DEBUG_RX, "%s: RX irq\n", dev->name);
1155 fifo = SMC_GET_RX_FIFO_INF(); 1092 fifo = SMC_GET_RX_FIFO_INF(lp);
1156 pkts = (fifo & RX_FIFO_INF_RXSUSED_) >> 16; 1093 pkts = (fifo & RX_FIFO_INF_RXSUSED_) >> 16;
1157 DBG(SMC_DEBUG_RX, "%s: Rx FIFO pkts %d, bytes %d\n", 1094 DBG(SMC_DEBUG_RX, "%s: Rx FIFO pkts %d, bytes %d\n",
1158 dev->name, pkts, fifo & 0xFFFF ); 1095 dev->name, pkts, fifo & 0xFFFF );
@@ -1163,61 +1100,61 @@ static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
1163 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, 1100 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA,
1164 "%s: RX DMA active\n", dev->name); 1101 "%s: RX DMA active\n", dev->name);
1165 /* The DMA is already running so up the IRQ threshold */ 1102 /* The DMA is already running so up the IRQ threshold */
1166 fifo = SMC_GET_FIFO_INT() & ~0xFF; 1103 fifo = SMC_GET_FIFO_INT(lp) & ~0xFF;
1167 fifo |= pkts & 0xFF; 1104 fifo |= pkts & 0xFF;
1168 DBG(SMC_DEBUG_RX, 1105 DBG(SMC_DEBUG_RX,
1169 "%s: Setting RX stat FIFO threshold to %d\n", 1106 "%s: Setting RX stat FIFO threshold to %d\n",
1170 dev->name, fifo & 0xff); 1107 dev->name, fifo & 0xff);
1171 SMC_SET_FIFO_INT(fifo); 1108 SMC_SET_FIFO_INT(lp, fifo);
1172 } else 1109 } else
1173#endif 1110#endif
1174 smc911x_rcv(dev); 1111 smc911x_rcv(dev);
1175 } 1112 }
1176 SMC_ACK_INT(INT_STS_RSFL_); 1113 SMC_ACK_INT(lp, INT_STS_RSFL_);
1177 } 1114 }
1178 /* Handle transmit FIFO available */ 1115 /* Handle transmit FIFO available */
1179 if (status & INT_STS_TDFA_) { 1116 if (status & INT_STS_TDFA_) {
1180 DBG(SMC_DEBUG_TX, "%s: TX data FIFO space available irq\n", dev->name); 1117 DBG(SMC_DEBUG_TX, "%s: TX data FIFO space available irq\n", dev->name);
1181 SMC_SET_FIFO_TDA(0xFF); 1118 SMC_SET_FIFO_TDA(lp, 0xFF);
1182 lp->tx_throttle = 0; 1119 lp->tx_throttle = 0;
1183#ifdef SMC_USE_DMA 1120#ifdef SMC_USE_DMA
1184 if (!lp->txdma_active) 1121 if (!lp->txdma_active)
1185#endif 1122#endif
1186 netif_wake_queue(dev); 1123 netif_wake_queue(dev);
1187 SMC_ACK_INT(INT_STS_TDFA_); 1124 SMC_ACK_INT(lp, INT_STS_TDFA_);
1188 } 1125 }
1189 /* Handle transmit done condition */ 1126 /* Handle transmit done condition */
1190#if 1 1127#if 1
1191 if (status & (INT_STS_TSFL_ | INT_STS_GPT_INT_)) { 1128 if (status & (INT_STS_TSFL_ | INT_STS_GPT_INT_)) {
1192 DBG(SMC_DEBUG_TX | SMC_DEBUG_MISC, 1129 DBG(SMC_DEBUG_TX | SMC_DEBUG_MISC,
1193 "%s: Tx stat FIFO limit (%d) /GPT irq\n", 1130 "%s: Tx stat FIFO limit (%d) /GPT irq\n",
1194 dev->name, (SMC_GET_FIFO_INT() & 0x00ff0000) >> 16); 1131 dev->name, (SMC_GET_FIFO_INT(lp) & 0x00ff0000) >> 16);
1195 smc911x_tx(dev); 1132 smc911x_tx(dev);
1196 SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000); 1133 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
1197 SMC_ACK_INT(INT_STS_TSFL_); 1134 SMC_ACK_INT(lp, INT_STS_TSFL_);
1198 SMC_ACK_INT(INT_STS_TSFL_ | INT_STS_GPT_INT_); 1135 SMC_ACK_INT(lp, INT_STS_TSFL_ | INT_STS_GPT_INT_);
1199 } 1136 }
1200#else 1137#else
1201 if (status & INT_STS_TSFL_) { 1138 if (status & INT_STS_TSFL_) {
1202 DBG(SMC_DEBUG_TX, "%s: TX status FIFO limit (%d) irq \n", dev->name, ); 1139 DBG(SMC_DEBUG_TX, "%s: TX status FIFO limit (%d) irq \n", dev->name, );
1203 smc911x_tx(dev); 1140 smc911x_tx(dev);
1204 SMC_ACK_INT(INT_STS_TSFL_); 1141 SMC_ACK_INT(lp, INT_STS_TSFL_);
1205 } 1142 }
1206 1143
1207 if (status & INT_STS_GPT_INT_) { 1144 if (status & INT_STS_GPT_INT_) {
1208 DBG(SMC_DEBUG_RX, "%s: IRQ_CFG 0x%08x FIFO_INT 0x%08x RX_CFG 0x%08x\n", 1145 DBG(SMC_DEBUG_RX, "%s: IRQ_CFG 0x%08x FIFO_INT 0x%08x RX_CFG 0x%08x\n",
1209 dev->name, 1146 dev->name,
1210 SMC_GET_IRQ_CFG(), 1147 SMC_GET_IRQ_CFG(lp),
1211 SMC_GET_FIFO_INT(), 1148 SMC_GET_FIFO_INT(lp),
1212 SMC_GET_RX_CFG()); 1149 SMC_GET_RX_CFG(lp));
1213 DBG(SMC_DEBUG_RX, "%s: Rx Stat FIFO Used 0x%02x " 1150 DBG(SMC_DEBUG_RX, "%s: Rx Stat FIFO Used 0x%02x "
1214 "Data FIFO Used 0x%04x Stat FIFO 0x%08x\n", 1151 "Data FIFO Used 0x%04x Stat FIFO 0x%08x\n",
1215 dev->name, 1152 dev->name,
1216 (SMC_GET_RX_FIFO_INF() & 0x00ff0000) >> 16, 1153 (SMC_GET_RX_FIFO_INF(lp) & 0x00ff0000) >> 16,
1217 SMC_GET_RX_FIFO_INF() & 0xffff, 1154 SMC_GET_RX_FIFO_INF(lp) & 0xffff,
1218 SMC_GET_RX_STS_FIFO_PEEK()); 1155 SMC_GET_RX_STS_FIFO_PEEK(lp));
1219 SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000); 1156 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
1220 SMC_ACK_INT(INT_STS_GPT_INT_); 1157 SMC_ACK_INT(lp, INT_STS_GPT_INT_);
1221 } 1158 }
1222#endif 1159#endif
1223 1160
@@ -1225,12 +1162,12 @@ static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
1225 if (status & INT_STS_PHY_INT_) { 1162 if (status & INT_STS_PHY_INT_) {
1226 DBG(SMC_DEBUG_MISC, "%s: PHY irq\n", dev->name); 1163 DBG(SMC_DEBUG_MISC, "%s: PHY irq\n", dev->name);
1227 smc911x_phy_interrupt(dev); 1164 smc911x_phy_interrupt(dev);
1228 SMC_ACK_INT(INT_STS_PHY_INT_); 1165 SMC_ACK_INT(lp, INT_STS_PHY_INT_);
1229 } 1166 }
1230 } while (--timeout); 1167 } while (--timeout);
1231 1168
1232 /* restore mask state */ 1169 /* restore mask state */
1233 SMC_SET_INT_EN(mask); 1170 SMC_SET_INT_EN(lp, mask);
1234 1171
1235 DBG(SMC_DEBUG_MISC, "%s: Interrupt done (%d loops)\n", 1172 DBG(SMC_DEBUG_MISC, "%s: Interrupt done (%d loops)\n",
1236 dev->name, 8-timeout); 1173 dev->name, 8-timeout);
@@ -1332,22 +1269,21 @@ static void smc911x_poll_controller(struct net_device *dev)
1332static void smc911x_timeout(struct net_device *dev) 1269static void smc911x_timeout(struct net_device *dev)
1333{ 1270{
1334 struct smc911x_local *lp = netdev_priv(dev); 1271 struct smc911x_local *lp = netdev_priv(dev);
1335 unsigned long ioaddr = dev->base_addr;
1336 int status, mask; 1272 int status, mask;
1337 unsigned long flags; 1273 unsigned long flags;
1338 1274
1339 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 1275 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1340 1276
1341 spin_lock_irqsave(&lp->lock, flags); 1277 spin_lock_irqsave(&lp->lock, flags);
1342 status = SMC_GET_INT(); 1278 status = SMC_GET_INT(lp);
1343 mask = SMC_GET_INT_EN(); 1279 mask = SMC_GET_INT_EN(lp);
1344 spin_unlock_irqrestore(&lp->lock, flags); 1280 spin_unlock_irqrestore(&lp->lock, flags);
1345 DBG(SMC_DEBUG_MISC, "%s: INT 0x%02x MASK 0x%02x \n", 1281 DBG(SMC_DEBUG_MISC, "%s: INT 0x%02x MASK 0x%02x \n",
1346 dev->name, status, mask); 1282 dev->name, status, mask);
1347 1283
1348 /* Dump the current TX FIFO contents and restart */ 1284 /* Dump the current TX FIFO contents and restart */
1349 mask = SMC_GET_TX_CFG(); 1285 mask = SMC_GET_TX_CFG(lp);
1350 SMC_SET_TX_CFG(mask | TX_CFG_TXS_DUMP_ | TX_CFG_TXD_DUMP_); 1286 SMC_SET_TX_CFG(lp, mask | TX_CFG_TXS_DUMP_ | TX_CFG_TXD_DUMP_);
1351 /* 1287 /*
1352 * Reconfiguring the PHY doesn't seem like a bad idea here, but 1288 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1353 * smc911x_phy_configure() calls msleep() which calls schedule_timeout() 1289 * smc911x_phy_configure() calls msleep() which calls schedule_timeout()
@@ -1370,7 +1306,6 @@ static void smc911x_timeout(struct net_device *dev)
1370static void smc911x_set_multicast_list(struct net_device *dev) 1306static void smc911x_set_multicast_list(struct net_device *dev)
1371{ 1307{
1372 struct smc911x_local *lp = netdev_priv(dev); 1308 struct smc911x_local *lp = netdev_priv(dev);
1373 unsigned long ioaddr = dev->base_addr;
1374 unsigned int multicast_table[2]; 1309 unsigned int multicast_table[2];
1375 unsigned int mcr, update_multicast = 0; 1310 unsigned int mcr, update_multicast = 0;
1376 unsigned long flags; 1311 unsigned long flags;
@@ -1378,7 +1313,7 @@ static void smc911x_set_multicast_list(struct net_device *dev)
1378 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 1313 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1379 1314
1380 spin_lock_irqsave(&lp->lock, flags); 1315 spin_lock_irqsave(&lp->lock, flags);
1381 SMC_GET_MAC_CR(mcr); 1316 SMC_GET_MAC_CR(lp, mcr);
1382 spin_unlock_irqrestore(&lp->lock, flags); 1317 spin_unlock_irqrestore(&lp->lock, flags);
1383 1318
1384 if (dev->flags & IFF_PROMISC) { 1319 if (dev->flags & IFF_PROMISC) {
@@ -1455,13 +1390,13 @@ static void smc911x_set_multicast_list(struct net_device *dev)
1455 } 1390 }
1456 1391
1457 spin_lock_irqsave(&lp->lock, flags); 1392 spin_lock_irqsave(&lp->lock, flags);
1458 SMC_SET_MAC_CR(mcr); 1393 SMC_SET_MAC_CR(lp, mcr);
1459 if (update_multicast) { 1394 if (update_multicast) {
1460 DBG(SMC_DEBUG_MISC, 1395 DBG(SMC_DEBUG_MISC,
1461 "%s: update mcast hash table 0x%08x 0x%08x\n", 1396 "%s: update mcast hash table 0x%08x 0x%08x\n",
1462 dev->name, multicast_table[0], multicast_table[1]); 1397 dev->name, multicast_table[0], multicast_table[1]);
1463 SMC_SET_HASHL(multicast_table[0]); 1398 SMC_SET_HASHL(lp, multicast_table[0]);
1464 SMC_SET_HASHH(multicast_table[1]); 1399 SMC_SET_HASHH(lp, multicast_table[1]);
1465 } 1400 }
1466 spin_unlock_irqrestore(&lp->lock, flags); 1401 spin_unlock_irqrestore(&lp->lock, flags);
1467} 1402}
@@ -1545,7 +1480,6 @@ static int
1545smc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) 1480smc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1546{ 1481{
1547 struct smc911x_local *lp = netdev_priv(dev); 1482 struct smc911x_local *lp = netdev_priv(dev);
1548 unsigned long ioaddr = dev->base_addr;
1549 int ret, status; 1483 int ret, status;
1550 unsigned long flags; 1484 unsigned long flags;
1551 1485
@@ -1573,7 +1507,7 @@ smc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1573 else 1507 else
1574 cmd->transceiver = XCVR_EXTERNAL; 1508 cmd->transceiver = XCVR_EXTERNAL;
1575 cmd->port = 0; 1509 cmd->port = 0;
1576 SMC_GET_PHY_SPECIAL(lp->mii.phy_id, status); 1510 SMC_GET_PHY_SPECIAL(lp, lp->mii.phy_id, status);
1577 cmd->duplex = 1511 cmd->duplex =
1578 (status & (PHY_SPECIAL_SPD_10FULL_ | PHY_SPECIAL_SPD_100FULL_)) ? 1512 (status & (PHY_SPECIAL_SPD_10FULL_ | PHY_SPECIAL_SPD_100FULL_)) ?
1579 DUPLEX_FULL : DUPLEX_HALF; 1513 DUPLEX_FULL : DUPLEX_HALF;
@@ -1654,7 +1588,6 @@ static int smc911x_ethtool_getregslen(struct net_device *dev)
1654static void smc911x_ethtool_getregs(struct net_device *dev, 1588static void smc911x_ethtool_getregs(struct net_device *dev,
1655 struct ethtool_regs* regs, void *buf) 1589 struct ethtool_regs* regs, void *buf)
1656{ 1590{
1657 unsigned long ioaddr = dev->base_addr;
1658 struct smc911x_local *lp = netdev_priv(dev); 1591 struct smc911x_local *lp = netdev_priv(dev);
1659 unsigned long flags; 1592 unsigned long flags;
1660 u32 reg,i,j=0; 1593 u32 reg,i,j=0;
@@ -1662,17 +1595,17 @@ static void smc911x_ethtool_getregs(struct net_device *dev,
1662 1595
1663 regs->version = lp->version; 1596 regs->version = lp->version;
1664 for(i=ID_REV;i<=E2P_CMD;i+=4) { 1597 for(i=ID_REV;i<=E2P_CMD;i+=4) {
1665 data[j++] = SMC_inl(ioaddr,i); 1598 data[j++] = SMC_inl(lp, i);
1666 } 1599 }
1667 for(i=MAC_CR;i<=WUCSR;i++) { 1600 for(i=MAC_CR;i<=WUCSR;i++) {
1668 spin_lock_irqsave(&lp->lock, flags); 1601 spin_lock_irqsave(&lp->lock, flags);
1669 SMC_GET_MAC_CSR(i, reg); 1602 SMC_GET_MAC_CSR(lp, i, reg);
1670 spin_unlock_irqrestore(&lp->lock, flags); 1603 spin_unlock_irqrestore(&lp->lock, flags);
1671 data[j++] = reg; 1604 data[j++] = reg;
1672 } 1605 }
1673 for(i=0;i<=31;i++) { 1606 for(i=0;i<=31;i++) {
1674 spin_lock_irqsave(&lp->lock, flags); 1607 spin_lock_irqsave(&lp->lock, flags);
1675 SMC_GET_MII(i, lp->mii.phy_id, reg); 1608 SMC_GET_MII(lp, i, lp->mii.phy_id, reg);
1676 spin_unlock_irqrestore(&lp->lock, flags); 1609 spin_unlock_irqrestore(&lp->lock, flags);
1677 data[j++] = reg & 0xFFFF; 1610 data[j++] = reg & 0xFFFF;
1678 } 1611 }
@@ -1680,11 +1613,11 @@ static void smc911x_ethtool_getregs(struct net_device *dev,
1680 1613
1681static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev) 1614static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
1682{ 1615{
1683 unsigned long ioaddr = dev->base_addr; 1616 struct smc911x_local *lp = netdev_priv(dev);
1684 unsigned int timeout; 1617 unsigned int timeout;
1685 int e2p_cmd; 1618 int e2p_cmd;
1686 1619
1687 e2p_cmd = SMC_GET_E2P_CMD(); 1620 e2p_cmd = SMC_GET_E2P_CMD(lp);
1688 for(timeout=10;(e2p_cmd & E2P_CMD_EPC_BUSY_) && timeout; timeout--) { 1621 for(timeout=10;(e2p_cmd & E2P_CMD_EPC_BUSY_) && timeout; timeout--) {
1689 if (e2p_cmd & E2P_CMD_EPC_TIMEOUT_) { 1622 if (e2p_cmd & E2P_CMD_EPC_TIMEOUT_) {
1690 PRINTK("%s: %s timeout waiting for EEPROM to respond\n", 1623 PRINTK("%s: %s timeout waiting for EEPROM to respond\n",
@@ -1692,7 +1625,7 @@ static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
1692 return -EFAULT; 1625 return -EFAULT;
1693 } 1626 }
1694 mdelay(1); 1627 mdelay(1);
1695 e2p_cmd = SMC_GET_E2P_CMD(); 1628 e2p_cmd = SMC_GET_E2P_CMD(lp);
1696 } 1629 }
1697 if (timeout == 0) { 1630 if (timeout == 0) {
1698 PRINTK("%s: %s timeout waiting for EEPROM CMD not busy\n", 1631 PRINTK("%s: %s timeout waiting for EEPROM CMD not busy\n",
@@ -1705,12 +1638,12 @@ static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
1705static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev, 1638static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev,
1706 int cmd, int addr) 1639 int cmd, int addr)
1707{ 1640{
1708 unsigned long ioaddr = dev->base_addr; 1641 struct smc911x_local *lp = netdev_priv(dev);
1709 int ret; 1642 int ret;
1710 1643
1711 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0) 1644 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1712 return ret; 1645 return ret;
1713 SMC_SET_E2P_CMD(E2P_CMD_EPC_BUSY_ | 1646 SMC_SET_E2P_CMD(lp, E2P_CMD_EPC_BUSY_ |
1714 ((cmd) & (0x7<<28)) | 1647 ((cmd) & (0x7<<28)) |
1715 ((addr) & 0xFF)); 1648 ((addr) & 0xFF));
1716 return 0; 1649 return 0;
@@ -1719,24 +1652,24 @@ static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev,
1719static inline int smc911x_ethtool_read_eeprom_byte(struct net_device *dev, 1652static inline int smc911x_ethtool_read_eeprom_byte(struct net_device *dev,
1720 u8 *data) 1653 u8 *data)
1721{ 1654{
1722 unsigned long ioaddr = dev->base_addr; 1655 struct smc911x_local *lp = netdev_priv(dev);
1723 int ret; 1656 int ret;
1724 1657
1725 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0) 1658 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1726 return ret; 1659 return ret;
1727 *data = SMC_GET_E2P_DATA(); 1660 *data = SMC_GET_E2P_DATA(lp);
1728 return 0; 1661 return 0;
1729} 1662}
1730 1663
1731static inline int smc911x_ethtool_write_eeprom_byte(struct net_device *dev, 1664static inline int smc911x_ethtool_write_eeprom_byte(struct net_device *dev,
1732 u8 data) 1665 u8 data)
1733{ 1666{
1734 unsigned long ioaddr = dev->base_addr; 1667 struct smc911x_local *lp = netdev_priv(dev);
1735 int ret; 1668 int ret;
1736 1669
1737 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0) 1670 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1738 return ret; 1671 return ret;
1739 SMC_SET_E2P_DATA(data); 1672 SMC_SET_E2P_DATA(lp, data);
1740 return 0; 1673 return 0;
1741} 1674}
1742 1675
@@ -1803,8 +1736,9 @@ static const struct ethtool_ops smc911x_ethtool_ops = {
1803 * This routine has a simple purpose -- make the SMC chip generate an 1736 * This routine has a simple purpose -- make the SMC chip generate an
1804 * interrupt, so an auto-detect routine can detect it, and find the IRQ, 1737 * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1805 */ 1738 */
1806static int __init smc911x_findirq(unsigned long ioaddr) 1739static int __init smc911x_findirq(struct net_device *dev)
1807{ 1740{
1741 struct smc911x_local *lp = netdev_priv(dev);
1808 int timeout = 20; 1742 int timeout = 20;
1809 unsigned long cookie; 1743 unsigned long cookie;
1810 1744
@@ -1816,7 +1750,7 @@ static int __init smc911x_findirq(unsigned long ioaddr)
1816 * Force a SW interrupt 1750 * Force a SW interrupt
1817 */ 1751 */
1818 1752
1819 SMC_SET_INT_EN(INT_EN_SW_INT_EN_); 1753 SMC_SET_INT_EN(lp, INT_EN_SW_INT_EN_);
1820 1754
1821 /* 1755 /*
1822 * Wait until positive that the interrupt has been generated 1756 * Wait until positive that the interrupt has been generated
@@ -1824,7 +1758,7 @@ static int __init smc911x_findirq(unsigned long ioaddr)
1824 do { 1758 do {
1825 int int_status; 1759 int int_status;
1826 udelay(10); 1760 udelay(10);
1827 int_status = SMC_GET_INT_EN(); 1761 int_status = SMC_GET_INT_EN(lp);
1828 if (int_status & INT_EN_SW_INT_EN_) 1762 if (int_status & INT_EN_SW_INT_EN_)
1829 break; /* got the interrupt */ 1763 break; /* got the interrupt */
1830 } while (--timeout); 1764 } while (--timeout);
@@ -1837,7 +1771,7 @@ static int __init smc911x_findirq(unsigned long ioaddr)
1837 */ 1771 */
1838 1772
1839 /* and disable all interrupts again */ 1773 /* and disable all interrupts again */
1840 SMC_SET_INT_EN(0); 1774 SMC_SET_INT_EN(lp, 0);
1841 1775
1842 /* and return what I found */ 1776 /* and return what I found */
1843 return probe_irq_off(cookie); 1777 return probe_irq_off(cookie);
@@ -1866,17 +1800,18 @@ static int __init smc911x_findirq(unsigned long ioaddr)
1866 * o actually GRAB the irq. 1800 * o actually GRAB the irq.
1867 * o GRAB the region 1801 * o GRAB the region
1868 */ 1802 */
1869static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr) 1803static int __init smc911x_probe(struct net_device *dev)
1870{ 1804{
1871 struct smc911x_local *lp = netdev_priv(dev); 1805 struct smc911x_local *lp = netdev_priv(dev);
1872 int i, retval; 1806 int i, retval;
1873 unsigned int val, chip_id, revision; 1807 unsigned int val, chip_id, revision;
1874 const char *version_string; 1808 const char *version_string;
1809 unsigned long irq_flags;
1875 1810
1876 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 1811 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1877 1812
1878 /* First, see if the endian word is recognized */ 1813 /* First, see if the endian word is recognized */
1879 val = SMC_GET_BYTE_TEST(); 1814 val = SMC_GET_BYTE_TEST(lp);
1880 DBG(SMC_DEBUG_MISC, "%s: endian probe returned 0x%04x\n", CARDNAME, val); 1815 DBG(SMC_DEBUG_MISC, "%s: endian probe returned 0x%04x\n", CARDNAME, val);
1881 if (val != 0x87654321) { 1816 if (val != 0x87654321) {
1882 printk(KERN_ERR "Invalid chip endian 0x08%x\n",val); 1817 printk(KERN_ERR "Invalid chip endian 0x08%x\n",val);
@@ -1889,7 +1824,7 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
1889 * recognize. These might need to be added to later, 1824 * recognize. These might need to be added to later,
1890 * as future revisions could be added. 1825 * as future revisions could be added.
1891 */ 1826 */
1892 chip_id = SMC_GET_PN(); 1827 chip_id = SMC_GET_PN(lp);
1893 DBG(SMC_DEBUG_MISC, "%s: id probe returned 0x%04x\n", CARDNAME, chip_id); 1828 DBG(SMC_DEBUG_MISC, "%s: id probe returned 0x%04x\n", CARDNAME, chip_id);
1894 for(i=0;chip_ids[i].id != 0; i++) { 1829 for(i=0;chip_ids[i].id != 0; i++) {
1895 if (chip_ids[i].id == chip_id) break; 1830 if (chip_ids[i].id == chip_id) break;
@@ -1901,7 +1836,7 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
1901 } 1836 }
1902 version_string = chip_ids[i].name; 1837 version_string = chip_ids[i].name;
1903 1838
1904 revision = SMC_GET_REV(); 1839 revision = SMC_GET_REV(lp);
1905 DBG(SMC_DEBUG_MISC, "%s: revision = 0x%04x\n", CARDNAME, revision); 1840 DBG(SMC_DEBUG_MISC, "%s: revision = 0x%04x\n", CARDNAME, revision);
1906 1841
1907 /* At this point I'll assume that the chip is an SMC911x. */ 1842 /* At this point I'll assume that the chip is an SMC911x. */
@@ -1915,7 +1850,6 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
1915 } 1850 }
1916 1851
1917 /* fill in some of the fields */ 1852 /* fill in some of the fields */
1918 dev->base_addr = ioaddr;
1919 lp->version = chip_ids[i].id; 1853 lp->version = chip_ids[i].id;
1920 lp->revision = revision; 1854 lp->revision = revision;
1921 lp->tx_fifo_kb = tx_fifo_kb; 1855 lp->tx_fifo_kb = tx_fifo_kb;
@@ -1974,7 +1908,7 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
1974 spin_lock_init(&lp->lock); 1908 spin_lock_init(&lp->lock);
1975 1909
1976 /* Get the MAC address */ 1910 /* Get the MAC address */
1977 SMC_GET_MAC_ADDR(dev->dev_addr); 1911 SMC_GET_MAC_ADDR(lp, dev->dev_addr);
1978 1912
1979 /* now, reset the chip, and put it into a known state */ 1913 /* now, reset the chip, and put it into a known state */
1980 smc911x_reset(dev); 1914 smc911x_reset(dev);
@@ -1991,7 +1925,7 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
1991 1925
1992 trials = 3; 1926 trials = 3;
1993 while (trials--) { 1927 while (trials--) {
1994 dev->irq = smc911x_findirq(ioaddr); 1928 dev->irq = smc911x_findirq(dev);
1995 if (dev->irq) 1929 if (dev->irq)
1996 break; 1930 break;
1997 /* kick the card and try again */ 1931 /* kick the card and try again */
@@ -2039,9 +1973,15 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
2039 lp->ctl_rfduplx = 1; 1973 lp->ctl_rfduplx = 1;
2040 lp->ctl_rspeed = 100; 1974 lp->ctl_rspeed = 100;
2041 1975
1976#ifdef SMC_DYNAMIC_BUS_CONFIG
1977 irq_flags = lp->cfg.irq_flags;
1978#else
1979 irq_flags = IRQF_SHARED | SMC_IRQ_SENSE;
1980#endif
1981
2042 /* Grab the IRQ */ 1982 /* Grab the IRQ */
2043 retval = request_irq(dev->irq, &smc911x_interrupt, 1983 retval = request_irq(dev->irq, &smc911x_interrupt,
2044 IRQF_SHARED | SMC_IRQ_SENSE, dev->name, dev); 1984 irq_flags, dev->name, dev);
2045 if (retval) 1985 if (retval)
2046 goto err_out; 1986 goto err_out;
2047 1987
@@ -2111,6 +2051,7 @@ err_out:
2111 */ 2051 */
2112static int smc911x_drv_probe(struct platform_device *pdev) 2052static int smc911x_drv_probe(struct platform_device *pdev)
2113{ 2053{
2054 struct smc91x_platdata *pd = pdev->dev.platform_data;
2114 struct net_device *ndev; 2055 struct net_device *ndev;
2115 struct resource *res; 2056 struct resource *res;
2116 struct smc911x_local *lp; 2057 struct smc911x_local *lp;
@@ -2144,6 +2085,13 @@ static int smc911x_drv_probe(struct platform_device *pdev)
2144 ndev->irq = platform_get_irq(pdev, 0); 2085 ndev->irq = platform_get_irq(pdev, 0);
2145 lp = netdev_priv(ndev); 2086 lp = netdev_priv(ndev);
2146 lp->netdev = ndev; 2087 lp->netdev = ndev;
2088#ifdef SMC_DYNAMIC_BUS_CONFIG
2089 if (!pd) {
2090 ret = -EINVAL;
2091 goto release_both;
2092 }
2093 memcpy(&lp->cfg, pd, sizeof(lp->cfg));
2094#endif
2147 2095
2148 addr = ioremap(res->start, SMC911X_IO_EXTENT); 2096 addr = ioremap(res->start, SMC911X_IO_EXTENT);
2149 if (!addr) { 2097 if (!addr) {
@@ -2152,7 +2100,9 @@ static int smc911x_drv_probe(struct platform_device *pdev)
2152 } 2100 }
2153 2101
2154 platform_set_drvdata(pdev, ndev); 2102 platform_set_drvdata(pdev, ndev);
2155 ret = smc911x_probe(ndev, (unsigned long)addr); 2103 lp->base = addr;
2104 ndev->base_addr = res->start;
2105 ret = smc911x_probe(ndev);
2156 if (ret != 0) { 2106 if (ret != 0) {
2157 platform_set_drvdata(pdev, NULL); 2107 platform_set_drvdata(pdev, NULL);
2158 iounmap(addr); 2108 iounmap(addr);
@@ -2176,6 +2126,7 @@ out:
2176static int smc911x_drv_remove(struct platform_device *pdev) 2126static int smc911x_drv_remove(struct platform_device *pdev)
2177{ 2127{
2178 struct net_device *ndev = platform_get_drvdata(pdev); 2128 struct net_device *ndev = platform_get_drvdata(pdev);
2129 struct smc911x_local *lp = netdev_priv(ndev);
2179 struct resource *res; 2130 struct resource *res;
2180 2131
2181 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__); 2132 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
@@ -2187,7 +2138,6 @@ static int smc911x_drv_remove(struct platform_device *pdev)
2187 2138
2188#ifdef SMC_USE_DMA 2139#ifdef SMC_USE_DMA
2189 { 2140 {
2190 struct smc911x_local *lp = netdev_priv(ndev);
2191 if (lp->rxdma != -1) { 2141 if (lp->rxdma != -1) {
2192 SMC_DMA_FREE(dev, lp->rxdma); 2142 SMC_DMA_FREE(dev, lp->rxdma);
2193 } 2143 }
@@ -2196,7 +2146,7 @@ static int smc911x_drv_remove(struct platform_device *pdev)
2196 } 2146 }
2197 } 2147 }
2198#endif 2148#endif
2199 iounmap((void *)ndev->base_addr); 2149 iounmap(lp->base);
2200 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2150 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2201 release_mem_region(res->start, SMC911X_IO_EXTENT); 2151 release_mem_region(res->start, SMC911X_IO_EXTENT);
2202 2152
@@ -2207,7 +2157,7 @@ static int smc911x_drv_remove(struct platform_device *pdev)
2207static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state) 2157static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state)
2208{ 2158{
2209 struct net_device *ndev = platform_get_drvdata(dev); 2159 struct net_device *ndev = platform_get_drvdata(dev);
2210 unsigned long ioaddr = ndev->base_addr; 2160 struct smc911x_local *lp = netdev_priv(ndev);
2211 2161
2212 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__); 2162 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
2213 if (ndev) { 2163 if (ndev) {
@@ -2216,7 +2166,7 @@ static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state)
2216 smc911x_shutdown(ndev); 2166 smc911x_shutdown(ndev);
2217#if POWER_DOWN 2167#if POWER_DOWN
2218 /* Set D2 - Energy detect only setting */ 2168 /* Set D2 - Energy detect only setting */
2219 SMC_SET_PMT_CTRL(2<<12); 2169 SMC_SET_PMT_CTRL(lp, 2<<12);
2220#endif 2170#endif
2221 } 2171 }
2222 } 2172 }
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 7defa63b9c74..76c17c28fab4 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -29,6 +29,7 @@
29#ifndef _SMC911X_H_ 29#ifndef _SMC911X_H_
30#define _SMC911X_H_ 30#define _SMC911X_H_
31 31
32#include <linux/smc911x.h>
32/* 33/*
33 * Use the DMA feature on PXA chips 34 * Use the DMA feature on PXA chips
34 */ 35 */
@@ -38,42 +39,160 @@
38 #define SMC_USE_32BIT 1 39 #define SMC_USE_32BIT 1
39 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING 40 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
40#elif defined(CONFIG_SH_MAGIC_PANEL_R2) 41#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
41 #define SMC_USE_SH_DMA 0
42 #define SMC_USE_16BIT 0 42 #define SMC_USE_16BIT 0
43 #define SMC_USE_32BIT 1 43 #define SMC_USE_32BIT 1
44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW 44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
45#else
46/*
47 * Default configuration
48 */
49
50#define SMC_DYNAMIC_BUS_CONFIG
45#endif 51#endif
46 52
53/* store this information for the driver.. */
54struct smc911x_local {
55 /*
56 * If I have to wait until the DMA is finished and ready to reload a
57 * packet, I will store the skbuff here. Then, the DMA will send it
58 * out and free it.
59 */
60 struct sk_buff *pending_tx_skb;
61
62 /* version/revision of the SMC911x chip */
63 u16 version;
64 u16 revision;
65
66 /* FIFO sizes */
67 int tx_fifo_kb;
68 int tx_fifo_size;
69 int rx_fifo_size;
70 int afc_cfg;
71
72 /* Contains the current active receive/phy mode */
73 int ctl_rfduplx;
74 int ctl_rspeed;
75
76 u32 msg_enable;
77 u32 phy_type;
78 struct mii_if_info mii;
79
80 /* work queue */
81 struct work_struct phy_configure;
82
83 int tx_throttle;
84 spinlock_t lock;
85
86 struct net_device *netdev;
87
88#ifdef SMC_USE_DMA
89 /* DMA needs the physical address of the chip */
90 u_long physaddr;
91 int rxdma;
92 int txdma;
93 int rxdma_active;
94 int txdma_active;
95 struct sk_buff *current_rx_skb;
96 struct sk_buff *current_tx_skb;
97 struct device *dev;
98#endif
99 void __iomem *base;
100#ifdef SMC_DYNAMIC_BUS_CONFIG
101 struct smc911x_platdata cfg;
102#endif
103};
47 104
48/* 105/*
49 * Define the bus width specific IO macros 106 * Define the bus width specific IO macros
50 */ 107 */
51 108
109#ifdef SMC_DYNAMIC_BUS_CONFIG
110static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
111{
112 void __iomem *ioaddr = lp->base + reg;
113
114 if (lp->cfg.flags & SMC911X_USE_32BIT)
115 return readl(ioaddr);
116
117 if (lp->cfg.flags & SMC911X_USE_16BIT)
118 return readw(ioaddr) | (readw(ioaddr + 2) << 16);
119
120 BUG();
121}
122
123static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
124 int reg)
125{
126 void __iomem *ioaddr = lp->base + reg;
127
128 if (lp->cfg.flags & SMC911X_USE_32BIT) {
129 writel(value, ioaddr);
130 return;
131 }
132
133 if (lp->cfg.flags & SMC911X_USE_16BIT) {
134 writew(value & 0xffff, ioaddr);
135 writew(value >> 16, ioaddr + 2);
136 return;
137 }
138
139 BUG();
140}
141
142static inline void SMC_insl(struct smc911x_local *lp, int reg,
143 void *addr, unsigned int count)
144{
145 void __iomem *ioaddr = lp->base + reg;
146
147 if (lp->cfg.flags & SMC911X_USE_32BIT) {
148 readsl(ioaddr, addr, count);
149 return;
150 }
151
152 if (lp->cfg.flags & SMC911X_USE_16BIT) {
153 readsw(ioaddr, addr, count * 2);
154 return;
155 }
156
157 BUG();
158}
159
160static inline void SMC_outsl(struct smc911x_local *lp, int reg,
161 void *addr, unsigned int count)
162{
163 void __iomem *ioaddr = lp->base + reg;
164
165 if (lp->cfg.flags & SMC911X_USE_32BIT) {
166 writesl(ioaddr, addr, count);
167 return;
168 }
169
170 if (lp->cfg.flags & SMC911X_USE_16BIT) {
171 writesw(ioaddr, addr, count * 2);
172 return;
173 }
174
175 BUG();
176}
177#else
52#if SMC_USE_16BIT 178#if SMC_USE_16BIT
53#define SMC_inb(a, r) readb((a) + (r)) 179#define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
54#define SMC_inw(a, r) readw((a) + (r)) 180#define SMC_outl(v, lp, r) \
55#define SMC_inl(a, r) ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw(a+2, r)<<16))
56#define SMC_outb(v, a, r) writeb(v, (a) + (r))
57#define SMC_outw(v, a, r) writew(v, (a) + (r))
58#define SMC_outl(v, a, r) \
59 do{ \ 181 do{ \
60 writel(v & 0xFFFF, (a) + (r)); \ 182 writew(v & 0xFFFF, (lp)->base + (r)); \
61 writel(v >> 16, (a) + (r) + 2); \ 183 writew(v >> 16, (lp)->base + (r) + 2); \
62 } while (0) 184 } while (0)
63#define SMC_insl(a, r, p, l) readsw((short*)((a) + (r)), p, l*2) 185#define SMC_insl(lp, r, p, l) readsw((short*)((lp)->base + (r)), p, l*2)
64#define SMC_outsl(a, r, p, l) writesw((short*)((a) + (r)), p, l*2) 186#define SMC_outsl(lp, r, p, l) writesw((short*)((lp)->base + (r)), p, l*2)
65 187
66#elif SMC_USE_32BIT 188#elif SMC_USE_32BIT
67#define SMC_inb(a, r) readb((a) + (r)) 189#define SMC_inl(lp, r) readl((lp)->base + (r))
68#define SMC_inw(a, r) readw((a) + (r)) 190#define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
69#define SMC_inl(a, r) readl((a) + (r)) 191#define SMC_insl(lp, r, p, l) readsl((int*)((lp)->base + (r)), p, l)
70#define SMC_outb(v, a, r) writeb(v, (a) + (r)) 192#define SMC_outsl(lp, r, p, l) writesl((int*)((lp)->base + (r)), p, l)
71#define SMC_outl(v, a, r) writel(v, (a) + (r))
72#define SMC_insl(a, r, p, l) readsl((int*)((a) + (r)), p, l)
73#define SMC_outsl(a, r, p, l) writesl((int*)((a) + (r)), p, l)
74 193
75#endif /* SMC_USE_16BIT */ 194#endif /* SMC_USE_16BIT */
76 195#endif /* SMC_DYNAMIC_BUS_CONFIG */
77 196
78 197
79#ifdef SMC_USE_PXA_DMA 198#ifdef SMC_USE_PXA_DMA
@@ -110,22 +229,22 @@ static int rx_dmalen, tx_dmalen;
110 229
111#ifdef SMC_insl 230#ifdef SMC_insl
112#undef SMC_insl 231#undef SMC_insl
113#define SMC_insl(a, r, p, l) \ 232#define SMC_insl(lp, r, p, l) \
114 smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l) 233 smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
115 234
116static inline void 235static inline void
117smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr, 236smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
118 int reg, int dma, u_char *buf, int len) 237 int reg, int dma, u_char *buf, int len)
119{ 238{
120 /* 64 bit alignment is required for memory to memory DMA */ 239 /* 64 bit alignment is required for memory to memory DMA */
121 if ((long)buf & 4) { 240 if ((long)buf & 4) {
122 *((u32 *)buf) = SMC_inl(ioaddr, reg); 241 *((u32 *)buf) = SMC_inl(lp, reg);
123 buf += 4; 242 buf += 4;
124 len--; 243 len--;
125 } 244 }
126 245
127 len *= 4; 246 len *= 4;
128 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE); 247 rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
129 rx_dmalen = len; 248 rx_dmalen = len;
130 DCSR(dma) = DCSR_NODESC; 249 DCSR(dma) = DCSR_NODESC;
131 DTADR(dma) = rx_dmabuf; 250 DTADR(dma) = rx_dmabuf;
@@ -136,52 +255,24 @@ smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
136} 255}
137#endif 256#endif
138 257
139#ifdef SMC_insw
140#undef SMC_insw
141#define SMC_insw(a, r, p, l) \
142 smc_pxa_dma_insw(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
143
144static inline void
145smc_pxa_dma_insw(struct device *dev, u_long ioaddr, u_long physaddr,
146 int reg, int dma, u_char *buf, int len)
147{
148 /* 64 bit alignment is required for memory to memory DMA */
149 while ((long)buf & 6) {
150 *((u16 *)buf) = SMC_inw(ioaddr, reg);
151 buf += 2;
152 len--;
153 }
154
155 len *= 2;
156 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
157 rx_dmalen = len;
158 DCSR(dma) = DCSR_NODESC;
159 DTADR(dma) = rx_dmabuf;
160 DSADR(dma) = physaddr + reg;
161 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
162 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
163 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
164}
165#endif
166
167#ifdef SMC_outsl 258#ifdef SMC_outsl
168#undef SMC_outsl 259#undef SMC_outsl
169#define SMC_outsl(a, r, p, l) \ 260#define SMC_outsl(lp, r, p, l) \
170 smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l) 261 smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
171 262
172static inline void 263static inline void
173smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr, 264smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
174 int reg, int dma, u_char *buf, int len) 265 int reg, int dma, u_char *buf, int len)
175{ 266{
176 /* 64 bit alignment is required for memory to memory DMA */ 267 /* 64 bit alignment is required for memory to memory DMA */
177 if ((long)buf & 4) { 268 if ((long)buf & 4) {
178 SMC_outl(*((u32 *)buf), ioaddr, reg); 269 SMC_outl(*((u32 *)buf), lp, reg);
179 buf += 4; 270 buf += 4;
180 len--; 271 len--;
181 } 272 }
182 273
183 len *= 4; 274 len *= 4;
184 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE); 275 tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
185 tx_dmalen = len; 276 tx_dmalen = len;
186 DCSR(dma) = DCSR_NODESC; 277 DCSR(dma) = DCSR_NODESC;
187 DSADR(dma) = tx_dmabuf; 278 DSADR(dma) = tx_dmabuf;
@@ -191,35 +282,6 @@ smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
191 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 282 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
192} 283}
193#endif 284#endif
194
195#ifdef SMC_outsw
196#undef SMC_outsw
197#define SMC_outsw(a, r, p, l) \
198 smc_pxa_dma_outsw(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
199
200static inline void
201smc_pxa_dma_outsw(struct device *dev, u_long ioaddr, u_long physaddr,
202 int reg, int dma, u_char *buf, int len)
203{
204 /* 64 bit alignment is required for memory to memory DMA */
205 while ((long)buf & 6) {
206 SMC_outw(*((u16 *)buf), ioaddr, reg);
207 buf += 2;
208 len--;
209 }
210
211 len *= 2;
212 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
213 tx_dmalen = len;
214 DCSR(dma) = DCSR_NODESC;
215 DSADR(dma) = tx_dmabuf;
216 DTADR(dma) = physaddr + reg;
217 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
218 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
219 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
220}
221#endif
222
223#endif /* SMC_USE_PXA_DMA */ 285#endif /* SMC_USE_PXA_DMA */
224 286
225 287
@@ -629,213 +691,213 @@ static const struct chip_id chip_ids[] = {
629 * capabilities. Please use those and not the in/out primitives. 691 * capabilities. Please use those and not the in/out primitives.
630 */ 692 */
631/* FIFO read/write macros */ 693/* FIFO read/write macros */
632#define SMC_PUSH_DATA(p, l) SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 ) 694#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
633#define SMC_PULL_DATA(p, l) SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 ) 695#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
634#define SMC_SET_TX_FIFO(x) SMC_outl( x, ioaddr, TX_DATA_FIFO ) 696#define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
635#define SMC_GET_RX_FIFO() SMC_inl( ioaddr, RX_DATA_FIFO ) 697#define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
636 698
637 699
638/* I/O mapped register read/write macros */ 700/* I/O mapped register read/write macros */
639#define SMC_GET_TX_STS_FIFO() SMC_inl( ioaddr, TX_STATUS_FIFO ) 701#define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
640#define SMC_GET_RX_STS_FIFO() SMC_inl( ioaddr, RX_STATUS_FIFO ) 702#define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
641#define SMC_GET_RX_STS_FIFO_PEEK() SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK ) 703#define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
642#define SMC_GET_PN() (SMC_inl( ioaddr, ID_REV ) >> 16) 704#define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
643#define SMC_GET_REV() (SMC_inl( ioaddr, ID_REV ) & 0xFFFF) 705#define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
644#define SMC_GET_IRQ_CFG() SMC_inl( ioaddr, INT_CFG ) 706#define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
645#define SMC_SET_IRQ_CFG(x) SMC_outl( x, ioaddr, INT_CFG ) 707#define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
646#define SMC_GET_INT() SMC_inl( ioaddr, INT_STS ) 708#define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
647#define SMC_ACK_INT(x) SMC_outl( x, ioaddr, INT_STS ) 709#define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
648#define SMC_GET_INT_EN() SMC_inl( ioaddr, INT_EN ) 710#define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
649#define SMC_SET_INT_EN(x) SMC_outl( x, ioaddr, INT_EN ) 711#define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
650#define SMC_GET_BYTE_TEST() SMC_inl( ioaddr, BYTE_TEST ) 712#define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
651#define SMC_SET_BYTE_TEST(x) SMC_outl( x, ioaddr, BYTE_TEST ) 713#define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
652#define SMC_GET_FIFO_INT() SMC_inl( ioaddr, FIFO_INT ) 714#define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
653#define SMC_SET_FIFO_INT(x) SMC_outl( x, ioaddr, FIFO_INT ) 715#define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
654#define SMC_SET_FIFO_TDA(x) \ 716#define SMC_SET_FIFO_TDA(lp, x) \
655 do { \ 717 do { \
656 unsigned long __flags; \ 718 unsigned long __flags; \
657 int __mask; \ 719 int __mask; \
658 local_irq_save(__flags); \ 720 local_irq_save(__flags); \
659 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24); \ 721 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
660 SMC_SET_FIFO_INT( __mask | (x)<<24 ); \ 722 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
661 local_irq_restore(__flags); \ 723 local_irq_restore(__flags); \
662 } while (0) 724 } while (0)
663#define SMC_SET_FIFO_TSL(x) \ 725#define SMC_SET_FIFO_TSL(lp, x) \
664 do { \ 726 do { \
665 unsigned long __flags; \ 727 unsigned long __flags; \
666 int __mask; \ 728 int __mask; \
667 local_irq_save(__flags); \ 729 local_irq_save(__flags); \
668 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16); \ 730 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
669 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \ 731 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
670 local_irq_restore(__flags); \ 732 local_irq_restore(__flags); \
671 } while (0) 733 } while (0)
672#define SMC_SET_FIFO_RSA(x) \ 734#define SMC_SET_FIFO_RSA(lp, x) \
673 do { \ 735 do { \
674 unsigned long __flags; \ 736 unsigned long __flags; \
675 int __mask; \ 737 int __mask; \
676 local_irq_save(__flags); \ 738 local_irq_save(__flags); \
677 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8); \ 739 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
678 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8)); \ 740 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
679 local_irq_restore(__flags); \ 741 local_irq_restore(__flags); \
680 } while (0) 742 } while (0)
681#define SMC_SET_FIFO_RSL(x) \ 743#define SMC_SET_FIFO_RSL(lp, x) \
682 do { \ 744 do { \
683 unsigned long __flags; \ 745 unsigned long __flags; \
684 int __mask; \ 746 int __mask; \
685 local_irq_save(__flags); \ 747 local_irq_save(__flags); \
686 __mask = SMC_GET_FIFO_INT() & ~0xFF; \ 748 __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
687 SMC_SET_FIFO_INT( __mask | ((x) & 0xFF)); \ 749 SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
688 local_irq_restore(__flags); \ 750 local_irq_restore(__flags); \
689 } while (0) 751 } while (0)
690#define SMC_GET_RX_CFG() SMC_inl( ioaddr, RX_CFG ) 752#define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
691#define SMC_SET_RX_CFG(x) SMC_outl( x, ioaddr, RX_CFG ) 753#define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
692#define SMC_GET_TX_CFG() SMC_inl( ioaddr, TX_CFG ) 754#define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
693#define SMC_SET_TX_CFG(x) SMC_outl( x, ioaddr, TX_CFG ) 755#define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
694#define SMC_GET_HW_CFG() SMC_inl( ioaddr, HW_CFG ) 756#define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
695#define SMC_SET_HW_CFG(x) SMC_outl( x, ioaddr, HW_CFG ) 757#define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
696#define SMC_GET_RX_DP_CTRL() SMC_inl( ioaddr, RX_DP_CTRL ) 758#define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
697#define SMC_SET_RX_DP_CTRL(x) SMC_outl( x, ioaddr, RX_DP_CTRL ) 759#define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
698#define SMC_GET_PMT_CTRL() SMC_inl( ioaddr, PMT_CTRL ) 760#define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
699#define SMC_SET_PMT_CTRL(x) SMC_outl( x, ioaddr, PMT_CTRL ) 761#define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
700#define SMC_GET_GPIO_CFG() SMC_inl( ioaddr, GPIO_CFG ) 762#define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
701#define SMC_SET_GPIO_CFG(x) SMC_outl( x, ioaddr, GPIO_CFG ) 763#define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
702#define SMC_GET_RX_FIFO_INF() SMC_inl( ioaddr, RX_FIFO_INF ) 764#define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
703#define SMC_SET_RX_FIFO_INF(x) SMC_outl( x, ioaddr, RX_FIFO_INF ) 765#define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
704#define SMC_GET_TX_FIFO_INF() SMC_inl( ioaddr, TX_FIFO_INF ) 766#define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
705#define SMC_SET_TX_FIFO_INF(x) SMC_outl( x, ioaddr, TX_FIFO_INF ) 767#define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
706#define SMC_GET_GPT_CFG() SMC_inl( ioaddr, GPT_CFG ) 768#define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
707#define SMC_SET_GPT_CFG(x) SMC_outl( x, ioaddr, GPT_CFG ) 769#define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
708#define SMC_GET_RX_DROP() SMC_inl( ioaddr, RX_DROP ) 770#define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
709#define SMC_SET_RX_DROP(x) SMC_outl( x, ioaddr, RX_DROP ) 771#define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
710#define SMC_GET_MAC_CMD() SMC_inl( ioaddr, MAC_CSR_CMD ) 772#define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
711#define SMC_SET_MAC_CMD(x) SMC_outl( x, ioaddr, MAC_CSR_CMD ) 773#define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
712#define SMC_GET_MAC_DATA() SMC_inl( ioaddr, MAC_CSR_DATA ) 774#define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
713#define SMC_SET_MAC_DATA(x) SMC_outl( x, ioaddr, MAC_CSR_DATA ) 775#define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
714#define SMC_GET_AFC_CFG() SMC_inl( ioaddr, AFC_CFG ) 776#define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
715#define SMC_SET_AFC_CFG(x) SMC_outl( x, ioaddr, AFC_CFG ) 777#define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
716#define SMC_GET_E2P_CMD() SMC_inl( ioaddr, E2P_CMD ) 778#define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
717#define SMC_SET_E2P_CMD(x) SMC_outl( x, ioaddr, E2P_CMD ) 779#define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
718#define SMC_GET_E2P_DATA() SMC_inl( ioaddr, E2P_DATA ) 780#define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
719#define SMC_SET_E2P_DATA(x) SMC_outl( x, ioaddr, E2P_DATA ) 781#define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
720 782
721/* MAC register read/write macros */ 783/* MAC register read/write macros */
722#define SMC_GET_MAC_CSR(a,v) \ 784#define SMC_GET_MAC_CSR(lp,a,v) \
723 do { \ 785 do { \
724 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 786 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
725 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | \ 787 SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
726 MAC_CSR_CMD_R_NOT_W_ | (a) ); \ 788 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
727 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 789 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
728 v = SMC_GET_MAC_DATA(); \ 790 v = SMC_GET_MAC_DATA((lp)); \
729 } while (0) 791 } while (0)
730#define SMC_SET_MAC_CSR(a,v) \ 792#define SMC_SET_MAC_CSR(lp,a,v) \
731 do { \ 793 do { \
732 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 794 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
733 SMC_SET_MAC_DATA(v); \ 795 SMC_SET_MAC_DATA((lp), v); \
734 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) ); \ 796 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
735 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 797 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
736 } while (0) 798 } while (0)
737#define SMC_GET_MAC_CR(x) SMC_GET_MAC_CSR( MAC_CR, x ) 799#define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
738#define SMC_SET_MAC_CR(x) SMC_SET_MAC_CSR( MAC_CR, x ) 800#define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
739#define SMC_GET_ADDRH(x) SMC_GET_MAC_CSR( ADDRH, x ) 801#define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
740#define SMC_SET_ADDRH(x) SMC_SET_MAC_CSR( ADDRH, x ) 802#define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
741#define SMC_GET_ADDRL(x) SMC_GET_MAC_CSR( ADDRL, x ) 803#define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
742#define SMC_SET_ADDRL(x) SMC_SET_MAC_CSR( ADDRL, x ) 804#define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
743#define SMC_GET_HASHH(x) SMC_GET_MAC_CSR( HASHH, x ) 805#define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
744#define SMC_SET_HASHH(x) SMC_SET_MAC_CSR( HASHH, x ) 806#define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
745#define SMC_GET_HASHL(x) SMC_GET_MAC_CSR( HASHL, x ) 807#define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
746#define SMC_SET_HASHL(x) SMC_SET_MAC_CSR( HASHL, x ) 808#define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
747#define SMC_GET_MII_ACC(x) SMC_GET_MAC_CSR( MII_ACC, x ) 809#define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
748#define SMC_SET_MII_ACC(x) SMC_SET_MAC_CSR( MII_ACC, x ) 810#define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
749#define SMC_GET_MII_DATA(x) SMC_GET_MAC_CSR( MII_DATA, x ) 811#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
750#define SMC_SET_MII_DATA(x) SMC_SET_MAC_CSR( MII_DATA, x ) 812#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
751#define SMC_GET_FLOW(x) SMC_GET_MAC_CSR( FLOW, x ) 813#define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
752#define SMC_SET_FLOW(x) SMC_SET_MAC_CSR( FLOW, x ) 814#define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
753#define SMC_GET_VLAN1(x) SMC_GET_MAC_CSR( VLAN1, x ) 815#define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
754#define SMC_SET_VLAN1(x) SMC_SET_MAC_CSR( VLAN1, x ) 816#define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
755#define SMC_GET_VLAN2(x) SMC_GET_MAC_CSR( VLAN2, x ) 817#define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
756#define SMC_SET_VLAN2(x) SMC_SET_MAC_CSR( VLAN2, x ) 818#define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
757#define SMC_SET_WUFF(x) SMC_SET_MAC_CSR( WUFF, x ) 819#define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
758#define SMC_GET_WUCSR(x) SMC_GET_MAC_CSR( WUCSR, x ) 820#define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
759#define SMC_SET_WUCSR(x) SMC_SET_MAC_CSR( WUCSR, x ) 821#define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
760 822
761/* PHY register read/write macros */ 823/* PHY register read/write macros */
762#define SMC_GET_MII(a,phy,v) \ 824#define SMC_GET_MII(lp,a,phy,v) \
763 do { \ 825 do { \
764 u32 __v; \ 826 u32 __v; \
765 do { \ 827 do { \
766 SMC_GET_MII_ACC(__v); \ 828 SMC_GET_MII_ACC((lp), __v); \
767 } while ( __v & MII_ACC_MII_BUSY_ ); \ 829 } while ( __v & MII_ACC_MII_BUSY_ ); \
768 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \ 830 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
769 MII_ACC_MII_BUSY_); \ 831 MII_ACC_MII_BUSY_); \
770 do { \ 832 do { \
771 SMC_GET_MII_ACC(__v); \ 833 SMC_GET_MII_ACC( (lp), __v); \
772 } while ( __v & MII_ACC_MII_BUSY_ ); \ 834 } while ( __v & MII_ACC_MII_BUSY_ ); \
773 SMC_GET_MII_DATA(v); \ 835 SMC_GET_MII_DATA((lp), v); \
774 } while (0) 836 } while (0)
775#define SMC_SET_MII(a,phy,v) \ 837#define SMC_SET_MII(lp,a,phy,v) \
776 do { \ 838 do { \
777 u32 __v; \ 839 u32 __v; \
778 do { \ 840 do { \
779 SMC_GET_MII_ACC(__v); \ 841 SMC_GET_MII_ACC((lp), __v); \
780 } while ( __v & MII_ACC_MII_BUSY_ ); \ 842 } while ( __v & MII_ACC_MII_BUSY_ ); \
781 SMC_SET_MII_DATA(v); \ 843 SMC_SET_MII_DATA((lp), v); \
782 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \ 844 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
783 MII_ACC_MII_BUSY_ | \ 845 MII_ACC_MII_BUSY_ | \
784 MII_ACC_MII_WRITE_ ); \ 846 MII_ACC_MII_WRITE_ ); \
785 do { \ 847 do { \
786 SMC_GET_MII_ACC(__v); \ 848 SMC_GET_MII_ACC((lp), __v); \
787 } while ( __v & MII_ACC_MII_BUSY_ ); \ 849 } while ( __v & MII_ACC_MII_BUSY_ ); \
788 } while (0) 850 } while (0)
789#define SMC_GET_PHY_BMCR(phy,x) SMC_GET_MII( MII_BMCR, phy, x ) 851#define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
790#define SMC_SET_PHY_BMCR(phy,x) SMC_SET_MII( MII_BMCR, phy, x ) 852#define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
791#define SMC_GET_PHY_BMSR(phy,x) SMC_GET_MII( MII_BMSR, phy, x ) 853#define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
792#define SMC_GET_PHY_ID1(phy,x) SMC_GET_MII( MII_PHYSID1, phy, x ) 854#define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
793#define SMC_GET_PHY_ID2(phy,x) SMC_GET_MII( MII_PHYSID2, phy, x ) 855#define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
794#define SMC_GET_PHY_MII_ADV(phy,x) SMC_GET_MII( MII_ADVERTISE, phy, x ) 856#define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
795#define SMC_SET_PHY_MII_ADV(phy,x) SMC_SET_MII( MII_ADVERTISE, phy, x ) 857#define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
796#define SMC_GET_PHY_MII_LPA(phy,x) SMC_GET_MII( MII_LPA, phy, x ) 858#define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
797#define SMC_SET_PHY_MII_LPA(phy,x) SMC_SET_MII( MII_LPA, phy, x ) 859#define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
798#define SMC_GET_PHY_CTRL_STS(phy,x) SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x ) 860#define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
799#define SMC_SET_PHY_CTRL_STS(phy,x) SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x ) 861#define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
800#define SMC_GET_PHY_INT_SRC(phy,x) SMC_GET_MII( PHY_INT_SRC, phy, x ) 862#define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
801#define SMC_SET_PHY_INT_SRC(phy,x) SMC_SET_MII( PHY_INT_SRC, phy, x ) 863#define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
802#define SMC_GET_PHY_INT_MASK(phy,x) SMC_GET_MII( PHY_INT_MASK, phy, x ) 864#define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
803#define SMC_SET_PHY_INT_MASK(phy,x) SMC_SET_MII( PHY_INT_MASK, phy, x ) 865#define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
804#define SMC_GET_PHY_SPECIAL(phy,x) SMC_GET_MII( PHY_SPECIAL, phy, x ) 866#define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
805 867
806 868
807 869
808/* Misc read/write macros */ 870/* Misc read/write macros */
809 871
810#ifndef SMC_GET_MAC_ADDR 872#ifndef SMC_GET_MAC_ADDR
811#define SMC_GET_MAC_ADDR(addr) \ 873#define SMC_GET_MAC_ADDR(lp, addr) \
812 do { \ 874 do { \
813 unsigned int __v; \ 875 unsigned int __v; \
814 \ 876 \
815 SMC_GET_MAC_CSR(ADDRL, __v); \ 877 SMC_GET_MAC_CSR((lp), ADDRL, __v); \
816 addr[0] = __v; addr[1] = __v >> 8; \ 878 addr[0] = __v; addr[1] = __v >> 8; \
817 addr[2] = __v >> 16; addr[3] = __v >> 24; \ 879 addr[2] = __v >> 16; addr[3] = __v >> 24; \
818 SMC_GET_MAC_CSR(ADDRH, __v); \ 880 SMC_GET_MAC_CSR((lp), ADDRH, __v); \
819 addr[4] = __v; addr[5] = __v >> 8; \ 881 addr[4] = __v; addr[5] = __v >> 8; \
820 } while (0) 882 } while (0)
821#endif 883#endif
822 884
823#define SMC_SET_MAC_ADDR(addr) \ 885#define SMC_SET_MAC_ADDR(lp, addr) \
824 do { \ 886 do { \
825 SMC_SET_MAC_CSR(ADDRL, \ 887 SMC_SET_MAC_CSR((lp), ADDRL, \
826 addr[0] | \ 888 addr[0] | \
827 (addr[1] << 8) | \ 889 (addr[1] << 8) | \
828 (addr[2] << 16) | \ 890 (addr[2] << 16) | \
829 (addr[3] << 24)); \ 891 (addr[3] << 24)); \
830 SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\ 892 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
831 } while (0) 893 } while (0)
832 894
833 895
834#define SMC_WRITE_EEPROM_CMD(cmd, addr) \ 896#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
835 do { \ 897 do { \
836 while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 898 while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
837 SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a ); \ 899 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
838 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 900 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
839 } while (0) 901 } while (0)
840 902
841#endif /* _SMC911X_H_ */ 903#endif /* _SMC911X_H_ */
diff --git a/drivers/net/spider_net.c b/drivers/net/spider_net.c
index 477671606273..00aa0b108cb9 100644
--- a/drivers/net/spider_net.c
+++ b/drivers/net/spider_net.c
@@ -1704,7 +1704,7 @@ spider_net_poll_controller(struct net_device *netdev)
1704 * 1704 *
1705 * spider_net_enable_interrupt enables several interrupts 1705 * spider_net_enable_interrupt enables several interrupts
1706 */ 1706 */
1707static void 1707static void
1708spider_net_enable_interrupts(struct spider_net_card *card) 1708spider_net_enable_interrupts(struct spider_net_card *card)
1709{ 1709{
1710 spider_net_write_reg(card, SPIDER_NET_GHIINT0MSK, 1710 spider_net_write_reg(card, SPIDER_NET_GHIINT0MSK,
@@ -1721,7 +1721,7 @@ spider_net_enable_interrupts(struct spider_net_card *card)
1721 * 1721 *
1722 * spider_net_disable_interrupts disables all the interrupts 1722 * spider_net_disable_interrupts disables all the interrupts
1723 */ 1723 */
1724static void 1724static void
1725spider_net_disable_interrupts(struct spider_net_card *card) 1725spider_net_disable_interrupts(struct spider_net_card *card)
1726{ 1726{
1727 spider_net_write_reg(card, SPIDER_NET_GHIINT0MSK, 0); 1727 spider_net_write_reg(card, SPIDER_NET_GHIINT0MSK, 0);
diff --git a/drivers/net/starfire.c b/drivers/net/starfire.c
index 7b7b1717b0d1..1d2ef8f47780 100644
--- a/drivers/net/starfire.c
+++ b/drivers/net/starfire.c
@@ -27,8 +27,8 @@
27*/ 27*/
28 28
29#define DRV_NAME "starfire" 29#define DRV_NAME "starfire"
30#define DRV_VERSION "2.0" 30#define DRV_VERSION "2.1"
31#define DRV_RELDATE "June 27, 2006" 31#define DRV_RELDATE "July 6, 2008"
32 32
33#include <linux/module.h> 33#include <linux/module.h>
34#include <linux/kernel.h> 34#include <linux/kernel.h>
@@ -69,10 +69,6 @@
69#define VLAN_SUPPORT 69#define VLAN_SUPPORT
70#endif 70#endif
71 71
72#ifndef CONFIG_ADAPTEC_STARFIRE_NAPI
73#undef HAVE_NETDEV_POLL
74#endif
75
76/* The user-configurable values. 72/* The user-configurable values.
77 These may be modified when a driver module is loaded.*/ 73 These may be modified when a driver module is loaded.*/
78 74
@@ -177,44 +173,6 @@ static int full_duplex[MAX_UNITS] = {0, };
177#define skb_first_frag_len(skb) skb_headlen(skb) 173#define skb_first_frag_len(skb) skb_headlen(skb)
178#define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1) 174#define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
179 175
180#ifdef HAVE_NETDEV_POLL
181#define init_poll(dev, np) \
182 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work)
183#define netdev_rx(dev, np, ioaddr) \
184do { \
185 u32 intr_enable; \
186 if (netif_rx_schedule_prep(dev, &np->napi)) { \
187 __netif_rx_schedule(dev, &np->napi); \
188 intr_enable = readl(ioaddr + IntrEnable); \
189 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \
190 writel(intr_enable, ioaddr + IntrEnable); \
191 readl(ioaddr + IntrEnable); /* flush PCI posting buffers */ \
192 } else { \
193 /* Paranoia check */ \
194 intr_enable = readl(ioaddr + IntrEnable); \
195 if (intr_enable & (IntrRxDone | IntrRxEmpty)) { \
196 printk(KERN_INFO "%s: interrupt while in polling mode!\n", dev->name); \
197 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \
198 writel(intr_enable, ioaddr + IntrEnable); \
199 } \
200 } \
201} while (0)
202#define netdev_receive_skb(skb) netif_receive_skb(skb)
203#define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_receive_skb(skb, vlgrp, vlid)
204static int netdev_poll(struct napi_struct *napi, int budget);
205#else /* not HAVE_NETDEV_POLL */
206#define init_poll(dev, np)
207#define netdev_receive_skb(skb) netif_rx(skb)
208#define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_rx(skb, vlgrp, vlid)
209#define netdev_rx(dev, np, ioaddr) \
210do { \
211 int quota = np->dirty_rx + RX_RING_SIZE - np->cur_rx; \
212 __netdev_rx(dev, &quota);\
213} while (0)
214#endif /* not HAVE_NETDEV_POLL */
215/* end of compatibility code */
216
217
218/* These identify the driver base version and may not be removed. */ 176/* These identify the driver base version and may not be removed. */
219static char version[] = 177static char version[] =
220KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n" 178KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
@@ -635,6 +593,7 @@ static int start_tx(struct sk_buff *skb, struct net_device *dev);
635static irqreturn_t intr_handler(int irq, void *dev_instance); 593static irqreturn_t intr_handler(int irq, void *dev_instance);
636static void netdev_error(struct net_device *dev, int intr_status); 594static void netdev_error(struct net_device *dev, int intr_status);
637static int __netdev_rx(struct net_device *dev, int *quota); 595static int __netdev_rx(struct net_device *dev, int *quota);
596static int netdev_poll(struct napi_struct *napi, int budget);
638static void refill_rx_ring(struct net_device *dev); 597static void refill_rx_ring(struct net_device *dev);
639static void netdev_error(struct net_device *dev, int intr_status); 598static void netdev_error(struct net_device *dev, int intr_status);
640static void set_rx_mode(struct net_device *dev); 599static void set_rx_mode(struct net_device *dev);
@@ -851,7 +810,7 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
851 dev->hard_start_xmit = &start_tx; 810 dev->hard_start_xmit = &start_tx;
852 dev->tx_timeout = tx_timeout; 811 dev->tx_timeout = tx_timeout;
853 dev->watchdog_timeo = TX_TIMEOUT; 812 dev->watchdog_timeo = TX_TIMEOUT;
854 init_poll(dev, np); 813 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work);
855 dev->stop = &netdev_close; 814 dev->stop = &netdev_close;
856 dev->get_stats = &get_stats; 815 dev->get_stats = &get_stats;
857 dev->set_multicast_list = &set_rx_mode; 816 dev->set_multicast_list = &set_rx_mode;
@@ -1054,9 +1013,8 @@ static int netdev_open(struct net_device *dev)
1054 1013
1055 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl); 1014 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1056 1015
1057#ifdef HAVE_NETDEV_POLL
1058 napi_enable(&np->napi); 1016 napi_enable(&np->napi);
1059#endif 1017
1060 netif_start_queue(dev); 1018 netif_start_queue(dev);
1061 1019
1062 if (debug > 1) 1020 if (debug > 1)
@@ -1330,8 +1288,28 @@ static irqreturn_t intr_handler(int irq, void *dev_instance)
1330 1288
1331 handled = 1; 1289 handled = 1;
1332 1290
1333 if (intr_status & (IntrRxDone | IntrRxEmpty)) 1291 if (intr_status & (IntrRxDone | IntrRxEmpty)) {
1334 netdev_rx(dev, np, ioaddr); 1292 u32 enable;
1293
1294 if (likely(netif_rx_schedule_prep(dev, &np->napi))) {
1295 __netif_rx_schedule(dev, &np->napi);
1296 enable = readl(ioaddr + IntrEnable);
1297 enable &= ~(IntrRxDone | IntrRxEmpty);
1298 writel(enable, ioaddr + IntrEnable);
1299 /* flush PCI posting buffers */
1300 readl(ioaddr + IntrEnable);
1301 } else {
1302 /* Paranoia check */
1303 enable = readl(ioaddr + IntrEnable);
1304 if (enable & (IntrRxDone | IntrRxEmpty)) {
1305 printk(KERN_INFO
1306 "%s: interrupt while in poll!\n",
1307 dev->name);
1308 enable &= ~(IntrRxDone | IntrRxEmpty);
1309 writel(enable, ioaddr + IntrEnable);
1310 }
1311 }
1312 }
1335 1313
1336 /* Scavenge the skbuff list based on the Tx-done queue. 1314 /* Scavenge the skbuff list based on the Tx-done queue.
1337 There are redundant checks here that may be cleaned up 1315 There are redundant checks here that may be cleaned up
@@ -1411,8 +1389,10 @@ static irqreturn_t intr_handler(int irq, void *dev_instance)
1411} 1389}
1412 1390
1413 1391
1414/* This routine is logically part of the interrupt/poll handler, but separated 1392/*
1415 for clarity, code sharing between NAPI/non-NAPI, and better register allocation. */ 1393 * This routine is logically part of the interrupt/poll handler, but separated
1394 * for clarity and better register allocation.
1395 */
1416static int __netdev_rx(struct net_device *dev, int *quota) 1396static int __netdev_rx(struct net_device *dev, int *quota)
1417{ 1397{
1418 struct netdev_private *np = netdev_priv(dev); 1398 struct netdev_private *np = netdev_priv(dev);
@@ -1507,13 +1487,20 @@ static int __netdev_rx(struct net_device *dev, int *quota)
1507 } 1487 }
1508#ifdef VLAN_SUPPORT 1488#ifdef VLAN_SUPPORT
1509 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) { 1489 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
1510 if (debug > 4) 1490 u16 vlid = le16_to_cpu(desc->vlanid);
1511 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n", le16_to_cpu(desc->vlanid)); 1491
1512 /* vlan_netdev_receive_skb() expects a packet with the VLAN tag stripped out */ 1492 if (debug > 4) {
1513 vlan_netdev_receive_skb(skb, np->vlgrp, le16_to_cpu(desc->vlanid) & VLAN_VID_MASK); 1493 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n",
1494 vlid);
1495 }
1496 /*
1497 * vlan_hwaccel_rx expects a packet with the VLAN tag
1498 * stripped out.
1499 */
1500 vlan_hwaccel_rx(skb, np->vlgrp, vlid);
1514 } else 1501 } else
1515#endif /* VLAN_SUPPORT */ 1502#endif /* VLAN_SUPPORT */
1516 netdev_receive_skb(skb); 1503 netif_receive_skb(skb);
1517 dev->last_rx = jiffies; 1504 dev->last_rx = jiffies;
1518 np->stats.rx_packets++; 1505 np->stats.rx_packets++;
1519 1506
@@ -1532,8 +1519,6 @@ static int __netdev_rx(struct net_device *dev, int *quota)
1532 return retcode; 1519 return retcode;
1533} 1520}
1534 1521
1535
1536#ifdef HAVE_NETDEV_POLL
1537static int netdev_poll(struct napi_struct *napi, int budget) 1522static int netdev_poll(struct napi_struct *napi, int budget)
1538{ 1523{
1539 struct netdev_private *np = container_of(napi, struct netdev_private, napi); 1524 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
@@ -1564,8 +1549,6 @@ static int netdev_poll(struct napi_struct *napi, int budget)
1564 /* Restart Rx engine if stopped. */ 1549 /* Restart Rx engine if stopped. */
1565 return budget - quota; 1550 return budget - quota;
1566} 1551}
1567#endif /* HAVE_NETDEV_POLL */
1568
1569 1552
1570static void refill_rx_ring(struct net_device *dev) 1553static void refill_rx_ring(struct net_device *dev)
1571{ 1554{
@@ -1906,9 +1889,8 @@ static int netdev_close(struct net_device *dev)
1906 int i; 1889 int i;
1907 1890
1908 netif_stop_queue(dev); 1891 netif_stop_queue(dev);
1909#ifdef HAVE_NETDEV_POLL 1892
1910 napi_disable(&np->napi); 1893 napi_disable(&np->napi);
1911#endif
1912 1894
1913 if (debug > 1) { 1895 if (debug > 1) {
1914 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n", 1896 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
@@ -2044,11 +2026,8 @@ static int __init starfire_init (void)
2044/* when a module, this is printed whether or not devices are found in probe */ 2026/* when a module, this is printed whether or not devices are found in probe */
2045#ifdef MODULE 2027#ifdef MODULE
2046 printk(version); 2028 printk(version);
2047#ifdef HAVE_NETDEV_POLL 2029
2048 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n"); 2030 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2049#else
2050 printk(KERN_INFO DRV_NAME ": polling (NAPI) disabled\n");
2051#endif
2052#endif 2031#endif
2053 2032
2054 /* we can do this test only at run-time... sigh */ 2033 /* we can do this test only at run-time... sigh */
diff --git a/drivers/net/sunlance.c b/drivers/net/sunlance.c
index 26ade68aeabf..4e994f87469e 100644
--- a/drivers/net/sunlance.c
+++ b/drivers/net/sunlance.c
@@ -915,15 +915,11 @@ static void build_fake_packet(struct lance_private *lp)
915 lp->tx_new = TX_NEXT(entry); 915 lp->tx_new = TX_NEXT(entry);
916} 916}
917 917
918struct net_device *last_dev;
919
920static int lance_open(struct net_device *dev) 918static int lance_open(struct net_device *dev)
921{ 919{
922 struct lance_private *lp = netdev_priv(dev); 920 struct lance_private *lp = netdev_priv(dev);
923 int status = 0; 921 int status = 0;
924 922
925 last_dev = dev;
926
927 STOP_LANCE(lp); 923 STOP_LANCE(lp);
928 924
929 if (request_irq(dev->irq, &lance_interrupt, IRQF_SHARED, 925 if (request_irq(dev->irq, &lance_interrupt, IRQF_SHARED,
diff --git a/drivers/net/tc35815.c b/drivers/net/tc35815.c
index b07b8cbadeaf..41d3ac45685f 100644
--- a/drivers/net/tc35815.c
+++ b/drivers/net/tc35815.c
@@ -672,7 +672,7 @@ static void tc_handle_link_change(struct net_device *dev)
672 if (dev->flags & IFF_PROMISC) 672 if (dev->flags & IFF_PROMISC)
673 tc35815_set_multicast_list(dev); 673 tc35815_set_multicast_list(dev);
674#endif 674#endif
675 netif_schedule(dev); 675 netif_tx_schedule_all(dev);
676 } else { 676 } else {
677 lp->speed = 0; 677 lp->speed = 0;
678 lp->duplex = -1; 678 lp->duplex = -1;
diff --git a/drivers/net/tehuti.c b/drivers/net/tehuti.c
index 432e837a1760..91f9054a1d95 100644
--- a/drivers/net/tehuti.c
+++ b/drivers/net/tehuti.c
@@ -1165,7 +1165,7 @@ NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1165 GET_RXD_VLAN_ID(rxd_vlan))->name); 1165 GET_RXD_VLAN_ID(rxd_vlan))->name);
1166 /* NAPI variant of receive functions */ 1166 /* NAPI variant of receive functions */
1167 vlan_hwaccel_receive_skb(skb, priv->vlgrp, 1167 vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1168 GET_RXD_VLAN_ID(rxd_vlan)); 1168 GET_RXD_VLAN_TCI(rxd_vlan));
1169 } else { 1169 } else {
1170 netif_receive_skb(skb); 1170 netif_receive_skb(skb);
1171 } 1171 }
diff --git a/drivers/net/tehuti.h b/drivers/net/tehuti.h
index efd170f451b4..c66dfc9ec1ec 100644
--- a/drivers/net/tehuti.h
+++ b/drivers/net/tehuti.h
@@ -309,6 +309,7 @@ struct rxf_desc {
309#define GET_RXD_PKT_ID(x) GET_BITS_SHIFT((x), 3, 28) 309#define GET_RXD_PKT_ID(x) GET_BITS_SHIFT((x), 3, 28)
310#define GET_RXD_VTAG(x) GET_BITS_SHIFT((x), 1, 31) 310#define GET_RXD_VTAG(x) GET_BITS_SHIFT((x), 1, 31)
311#define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0) 311#define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0)
312#define GET_RXD_VLAN_TCI(x) GET_BITS_SHIFT((x), 16, 0)
312#define GET_RXD_CFI(x) GET_BITS_SHIFT((x), 1, 12) 313#define GET_RXD_CFI(x) GET_BITS_SHIFT((x), 1, 12)
313#define GET_RXD_PRIO(x) GET_BITS_SHIFT((x), 3, 13) 314#define GET_RXD_PRIO(x) GET_BITS_SHIFT((x), 3, 13)
314 315
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index cc4bde852542..633c128a6228 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -32,6 +32,8 @@
32#include <linux/skbuff.h> 32#include <linux/skbuff.h>
33#include <linux/ethtool.h> 33#include <linux/ethtool.h>
34#include <linux/mii.h> 34#include <linux/mii.h>
35#include <linux/phy.h>
36#include <linux/brcmphy.h>
35#include <linux/if_vlan.h> 37#include <linux/if_vlan.h>
36#include <linux/ip.h> 38#include <linux/ip.h>
37#include <linux/tcp.h> 39#include <linux/tcp.h>
@@ -64,8 +66,8 @@
64 66
65#define DRV_MODULE_NAME "tg3" 67#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": " 68#define PFX DRV_MODULE_NAME ": "
67#define DRV_MODULE_VERSION "3.92.1" 69#define DRV_MODULE_VERSION "3.93"
68#define DRV_MODULE_RELDATE "June 9, 2008" 70#define DRV_MODULE_RELDATE "May 22, 2008"
69 71
70#define TG3_DEF_MAC_MODE 0 72#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0 73#define TG3_DEF_RX_MODE 0
@@ -203,6 +205,7 @@ static struct pci_device_id tg3_pci_tbl[] = {
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, 205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, 206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, 207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
206 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, 209 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
207 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, 210 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
208 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, 211 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
@@ -804,6 +807,569 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
804 return ret; 807 return ret;
805} 808}
806 809
810static int tg3_bmcr_reset(struct tg3 *tp)
811{
812 u32 phy_control;
813 int limit, err;
814
815 /* OK, reset it, and poll the BMCR_RESET bit until it
816 * clears or we time out.
817 */
818 phy_control = BMCR_RESET;
819 err = tg3_writephy(tp, MII_BMCR, phy_control);
820 if (err != 0)
821 return -EBUSY;
822
823 limit = 5000;
824 while (limit--) {
825 err = tg3_readphy(tp, MII_BMCR, &phy_control);
826 if (err != 0)
827 return -EBUSY;
828
829 if ((phy_control & BMCR_RESET) == 0) {
830 udelay(40);
831 break;
832 }
833 udelay(10);
834 }
835 if (limit <= 0)
836 return -EBUSY;
837
838 return 0;
839}
840
841static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
842{
843 struct tg3 *tp = (struct tg3 *)bp->priv;
844 u32 val;
845
846 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
847 return -EAGAIN;
848
849 if (tg3_readphy(tp, reg, &val))
850 return -EIO;
851
852 return val;
853}
854
855static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
856{
857 struct tg3 *tp = (struct tg3 *)bp->priv;
858
859 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
860 return -EAGAIN;
861
862 if (tg3_writephy(tp, reg, val))
863 return -EIO;
864
865 return 0;
866}
867
868static int tg3_mdio_reset(struct mii_bus *bp)
869{
870 return 0;
871}
872
873static void tg3_mdio_config(struct tg3 *tp)
874{
875 u32 val;
876
877 if (tp->mdio_bus.phy_map[PHY_ADDR]->interface !=
878 PHY_INTERFACE_MODE_RGMII)
879 return;
880
881 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
882 MAC_PHYCFG1_RGMII_SND_STAT_EN);
883 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
884 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
885 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
886 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
887 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
888 }
889 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
890
891 val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
892 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
893 val |= MAC_PHYCFG2_INBAND_ENABLE;
894 tw32(MAC_PHYCFG2, val);
895
896 val = tr32(MAC_EXT_RGMII_MODE);
897 val &= ~(MAC_RGMII_MODE_RX_INT_B |
898 MAC_RGMII_MODE_RX_QUALITY |
899 MAC_RGMII_MODE_RX_ACTIVITY |
900 MAC_RGMII_MODE_RX_ENG_DET |
901 MAC_RGMII_MODE_TX_ENABLE |
902 MAC_RGMII_MODE_TX_LOWPWR |
903 MAC_RGMII_MODE_TX_RESET);
904 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
905 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
906 val |= MAC_RGMII_MODE_RX_INT_B |
907 MAC_RGMII_MODE_RX_QUALITY |
908 MAC_RGMII_MODE_RX_ACTIVITY |
909 MAC_RGMII_MODE_RX_ENG_DET;
910 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
911 val |= MAC_RGMII_MODE_TX_ENABLE |
912 MAC_RGMII_MODE_TX_LOWPWR |
913 MAC_RGMII_MODE_TX_RESET;
914 }
915 tw32(MAC_EXT_RGMII_MODE, val);
916}
917
918static void tg3_mdio_start(struct tg3 *tp)
919{
920 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
921 mutex_lock(&tp->mdio_bus.mdio_lock);
922 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
923 mutex_unlock(&tp->mdio_bus.mdio_lock);
924 }
925
926 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
927 tw32_f(MAC_MI_MODE, tp->mi_mode);
928 udelay(80);
929
930 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)
931 tg3_mdio_config(tp);
932}
933
934static void tg3_mdio_stop(struct tg3 *tp)
935{
936 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
937 mutex_lock(&tp->mdio_bus.mdio_lock);
938 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
939 mutex_unlock(&tp->mdio_bus.mdio_lock);
940 }
941}
942
943static int tg3_mdio_init(struct tg3 *tp)
944{
945 int i;
946 u32 reg;
947 struct phy_device *phydev;
948 struct mii_bus *mdio_bus = &tp->mdio_bus;
949
950 tg3_mdio_start(tp);
951
952 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
953 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
954 return 0;
955
956 memset(mdio_bus, 0, sizeof(*mdio_bus));
957
958 mdio_bus->name = "tg3 mdio bus";
959 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
960 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
961 mdio_bus->priv = tp;
962 mdio_bus->dev = &tp->pdev->dev;
963 mdio_bus->read = &tg3_mdio_read;
964 mdio_bus->write = &tg3_mdio_write;
965 mdio_bus->reset = &tg3_mdio_reset;
966 mdio_bus->phy_mask = ~(1 << PHY_ADDR);
967 mdio_bus->irq = &tp->mdio_irq[0];
968
969 for (i = 0; i < PHY_MAX_ADDR; i++)
970 mdio_bus->irq[i] = PHY_POLL;
971
972 /* The bus registration will look for all the PHYs on the mdio bus.
973 * Unfortunately, it does not ensure the PHY is powered up before
974 * accessing the PHY ID registers. A chip reset is the
975 * quickest way to bring the device back to an operational state..
976 */
977 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
978 tg3_bmcr_reset(tp);
979
980 i = mdiobus_register(mdio_bus);
981 if (i) {
982 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
983 tp->dev->name, i);
984 return i;
985 }
986
987 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
988
989 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
990
991 switch (phydev->phy_id) {
992 case TG3_PHY_ID_BCM50610:
993 phydev->interface = PHY_INTERFACE_MODE_RGMII;
994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
995 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
997 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
998 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
999 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1000 break;
1001 case TG3_PHY_ID_BCMAC131:
1002 phydev->interface = PHY_INTERFACE_MODE_MII;
1003 break;
1004 }
1005
1006 tg3_mdio_config(tp);
1007
1008 return 0;
1009}
1010
1011static void tg3_mdio_fini(struct tg3 *tp)
1012{
1013 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1014 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1015 mdiobus_unregister(&tp->mdio_bus);
1016 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1017 }
1018}
1019
1020/* tp->lock is held. */
1021static void tg3_wait_for_event_ack(struct tg3 *tp)
1022{
1023 int i;
1024
1025 /* Wait for up to 2.5 milliseconds */
1026 for (i = 0; i < 250000; i++) {
1027 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1028 break;
1029 udelay(10);
1030 }
1031}
1032
1033/* tp->lock is held. */
1034static void tg3_ump_link_report(struct tg3 *tp)
1035{
1036 u32 reg;
1037 u32 val;
1038
1039 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1040 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1041 return;
1042
1043 tg3_wait_for_event_ack(tp);
1044
1045 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1046
1047 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1048
1049 val = 0;
1050 if (!tg3_readphy(tp, MII_BMCR, &reg))
1051 val = reg << 16;
1052 if (!tg3_readphy(tp, MII_BMSR, &reg))
1053 val |= (reg & 0xffff);
1054 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1055
1056 val = 0;
1057 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1058 val = reg << 16;
1059 if (!tg3_readphy(tp, MII_LPA, &reg))
1060 val |= (reg & 0xffff);
1061 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1062
1063 val = 0;
1064 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1065 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1066 val = reg << 16;
1067 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1068 val |= (reg & 0xffff);
1069 }
1070 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1071
1072 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1073 val = reg << 16;
1074 else
1075 val = 0;
1076 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1077
1078 val = tr32(GRC_RX_CPU_EVENT);
1079 val |= GRC_RX_CPU_DRIVER_EVENT;
1080 tw32_f(GRC_RX_CPU_EVENT, val);
1081}
1082
1083static void tg3_link_report(struct tg3 *tp)
1084{
1085 if (!netif_carrier_ok(tp->dev)) {
1086 if (netif_msg_link(tp))
1087 printk(KERN_INFO PFX "%s: Link is down.\n",
1088 tp->dev->name);
1089 tg3_ump_link_report(tp);
1090 } else if (netif_msg_link(tp)) {
1091 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1092 tp->dev->name,
1093 (tp->link_config.active_speed == SPEED_1000 ?
1094 1000 :
1095 (tp->link_config.active_speed == SPEED_100 ?
1096 100 : 10)),
1097 (tp->link_config.active_duplex == DUPLEX_FULL ?
1098 "full" : "half"));
1099
1100 printk(KERN_INFO PFX
1101 "%s: Flow control is %s for TX and %s for RX.\n",
1102 tp->dev->name,
1103 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1104 "on" : "off",
1105 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1106 "on" : "off");
1107 tg3_ump_link_report(tp);
1108 }
1109}
1110
1111static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1112{
1113 u16 miireg;
1114
1115 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1116 miireg = ADVERTISE_PAUSE_CAP;
1117 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1118 miireg = ADVERTISE_PAUSE_ASYM;
1119 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1120 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1121 else
1122 miireg = 0;
1123
1124 return miireg;
1125}
1126
1127static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1128{
1129 u16 miireg;
1130
1131 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1132 miireg = ADVERTISE_1000XPAUSE;
1133 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1134 miireg = ADVERTISE_1000XPSE_ASYM;
1135 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1136 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1137 else
1138 miireg = 0;
1139
1140 return miireg;
1141}
1142
1143static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1144{
1145 u8 cap = 0;
1146
1147 if (lcladv & ADVERTISE_PAUSE_CAP) {
1148 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1149 if (rmtadv & LPA_PAUSE_CAP)
1150 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1151 else if (rmtadv & LPA_PAUSE_ASYM)
1152 cap = TG3_FLOW_CTRL_RX;
1153 } else {
1154 if (rmtadv & LPA_PAUSE_CAP)
1155 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1156 }
1157 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1158 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1159 cap = TG3_FLOW_CTRL_TX;
1160 }
1161
1162 return cap;
1163}
1164
1165static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1166{
1167 u8 cap = 0;
1168
1169 if (lcladv & ADVERTISE_1000XPAUSE) {
1170 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1171 if (rmtadv & LPA_1000XPAUSE)
1172 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1173 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1174 cap = TG3_FLOW_CTRL_RX;
1175 } else {
1176 if (rmtadv & LPA_1000XPAUSE)
1177 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1178 }
1179 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1180 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1181 cap = TG3_FLOW_CTRL_TX;
1182 }
1183
1184 return cap;
1185}
1186
1187static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1188{
1189 u8 autoneg;
1190 u8 flowctrl = 0;
1191 u32 old_rx_mode = tp->rx_mode;
1192 u32 old_tx_mode = tp->tx_mode;
1193
1194 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1195 autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
1196 else
1197 autoneg = tp->link_config.autoneg;
1198
1199 if (autoneg == AUTONEG_ENABLE &&
1200 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1201 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1202 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1203 else
1204 flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1205 } else
1206 flowctrl = tp->link_config.flowctrl;
1207
1208 tp->link_config.active_flowctrl = flowctrl;
1209
1210 if (flowctrl & TG3_FLOW_CTRL_RX)
1211 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1212 else
1213 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1214
1215 if (old_rx_mode != tp->rx_mode)
1216 tw32_f(MAC_RX_MODE, tp->rx_mode);
1217
1218 if (flowctrl & TG3_FLOW_CTRL_TX)
1219 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1220 else
1221 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1222
1223 if (old_tx_mode != tp->tx_mode)
1224 tw32_f(MAC_TX_MODE, tp->tx_mode);
1225}
1226
1227static void tg3_adjust_link(struct net_device *dev)
1228{
1229 u8 oldflowctrl, linkmesg = 0;
1230 u32 mac_mode, lcl_adv, rmt_adv;
1231 struct tg3 *tp = netdev_priv(dev);
1232 struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1233
1234 spin_lock(&tp->lock);
1235
1236 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1237 MAC_MODE_HALF_DUPLEX);
1238
1239 oldflowctrl = tp->link_config.active_flowctrl;
1240
1241 if (phydev->link) {
1242 lcl_adv = 0;
1243 rmt_adv = 0;
1244
1245 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1246 mac_mode |= MAC_MODE_PORT_MODE_MII;
1247 else
1248 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1249
1250 if (phydev->duplex == DUPLEX_HALF)
1251 mac_mode |= MAC_MODE_HALF_DUPLEX;
1252 else {
1253 lcl_adv = tg3_advert_flowctrl_1000T(
1254 tp->link_config.flowctrl);
1255
1256 if (phydev->pause)
1257 rmt_adv = LPA_PAUSE_CAP;
1258 if (phydev->asym_pause)
1259 rmt_adv |= LPA_PAUSE_ASYM;
1260 }
1261
1262 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1263 } else
1264 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1265
1266 if (mac_mode != tp->mac_mode) {
1267 tp->mac_mode = mac_mode;
1268 tw32_f(MAC_MODE, tp->mac_mode);
1269 udelay(40);
1270 }
1271
1272 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1273 tw32(MAC_TX_LENGTHS,
1274 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1275 (6 << TX_LENGTHS_IPG_SHIFT) |
1276 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1277 else
1278 tw32(MAC_TX_LENGTHS,
1279 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1280 (6 << TX_LENGTHS_IPG_SHIFT) |
1281 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1282
1283 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1284 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1285 phydev->speed != tp->link_config.active_speed ||
1286 phydev->duplex != tp->link_config.active_duplex ||
1287 oldflowctrl != tp->link_config.active_flowctrl)
1288 linkmesg = 1;
1289
1290 tp->link_config.active_speed = phydev->speed;
1291 tp->link_config.active_duplex = phydev->duplex;
1292
1293 spin_unlock(&tp->lock);
1294
1295 if (linkmesg)
1296 tg3_link_report(tp);
1297}
1298
1299static int tg3_phy_init(struct tg3 *tp)
1300{
1301 struct phy_device *phydev;
1302
1303 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1304 return 0;
1305
1306 /* Bring the PHY back to a known state. */
1307 tg3_bmcr_reset(tp);
1308
1309 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1310
1311 /* Attach the MAC to the PHY. */
1312 phydev = phy_connect(tp->dev, phydev->dev.bus_id, tg3_adjust_link,
1313 phydev->dev_flags, phydev->interface);
1314 if (IS_ERR(phydev)) {
1315 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1316 return PTR_ERR(phydev);
1317 }
1318
1319 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1320
1321 /* Mask with MAC supported features. */
1322 phydev->supported &= (PHY_GBIT_FEATURES |
1323 SUPPORTED_Pause |
1324 SUPPORTED_Asym_Pause);
1325
1326 phydev->advertising = phydev->supported;
1327
1328 printk(KERN_INFO
1329 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1330 tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1331
1332 return 0;
1333}
1334
1335static void tg3_phy_start(struct tg3 *tp)
1336{
1337 struct phy_device *phydev;
1338
1339 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1340 return;
1341
1342 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1343
1344 if (tp->link_config.phy_is_low_power) {
1345 tp->link_config.phy_is_low_power = 0;
1346 phydev->speed = tp->link_config.orig_speed;
1347 phydev->duplex = tp->link_config.orig_duplex;
1348 phydev->autoneg = tp->link_config.orig_autoneg;
1349 phydev->advertising = tp->link_config.orig_advertising;
1350 }
1351
1352 phy_start(phydev);
1353
1354 phy_start_aneg(phydev);
1355}
1356
1357static void tg3_phy_stop(struct tg3 *tp)
1358{
1359 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1360 return;
1361
1362 phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
1363}
1364
1365static void tg3_phy_fini(struct tg3 *tp)
1366{
1367 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1368 phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
1369 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1370 }
1371}
1372
807static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) 1373static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
808{ 1374{
809 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); 1375 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
@@ -861,37 +1427,6 @@ static void tg3_phy_set_wirespeed(struct tg3 *tp)
861 (val | (1 << 15) | (1 << 4))); 1427 (val | (1 << 15) | (1 << 4)));
862} 1428}
863 1429
864static int tg3_bmcr_reset(struct tg3 *tp)
865{
866 u32 phy_control;
867 int limit, err;
868
869 /* OK, reset it, and poll the BMCR_RESET bit until it
870 * clears or we time out.
871 */
872 phy_control = BMCR_RESET;
873 err = tg3_writephy(tp, MII_BMCR, phy_control);
874 if (err != 0)
875 return -EBUSY;
876
877 limit = 5000;
878 while (limit--) {
879 err = tg3_readphy(tp, MII_BMCR, &phy_control);
880 if (err != 0)
881 return -EBUSY;
882
883 if ((phy_control & BMCR_RESET) == 0) {
884 udelay(40);
885 break;
886 }
887 udelay(10);
888 }
889 if (limit <= 0)
890 return -EBUSY;
891
892 return 0;
893}
894
895static void tg3_phy_apply_otp(struct tg3 *tp) 1430static void tg3_phy_apply_otp(struct tg3 *tp)
896{ 1431{
897 u32 otp, phy; 1432 u32 otp, phy;
@@ -1115,8 +1650,6 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1115 return err; 1650 return err;
1116} 1651}
1117 1652
1118static void tg3_link_report(struct tg3 *);
1119
1120/* This will reset the tigon3 PHY if there is no valid 1653/* This will reset the tigon3 PHY if there is no valid
1121 * link unless the FORCE argument is non-zero. 1654 * link unless the FORCE argument is non-zero.
1122 */ 1655 */
@@ -1421,7 +1954,7 @@ static void tg3_power_down_phy(struct tg3 *tp)
1421 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); 1954 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1422 udelay(40); 1955 udelay(40);
1423 return; 1956 return;
1424 } else { 1957 } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1425 tg3_writephy(tp, MII_TG3_EXT_CTRL, 1958 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1426 MII_TG3_EXT_CTRL_FORCE_LED_OFF); 1959 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1427 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2); 1960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
@@ -1495,7 +2028,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1495 "requested.\n", 2028 "requested.\n",
1496 tp->dev->name, state); 2029 tp->dev->name, state);
1497 return -EINVAL; 2030 return -EINVAL;
1498 }; 2031 }
1499 2032
1500 power_control |= PCI_PM_CTRL_PME_ENABLE; 2033 power_control |= PCI_PM_CTRL_PME_ENABLE;
1501 2034
@@ -1503,18 +2036,55 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1503 tw32(TG3PCI_MISC_HOST_CTRL, 2036 tw32(TG3PCI_MISC_HOST_CTRL,
1504 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); 2037 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1505 2038
1506 if (tp->link_config.phy_is_low_power == 0) { 2039 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
1507 tp->link_config.phy_is_low_power = 1; 2040 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
1508 tp->link_config.orig_speed = tp->link_config.speed; 2041 !tp->link_config.phy_is_low_power) {
1509 tp->link_config.orig_duplex = tp->link_config.duplex; 2042 struct phy_device *phydev;
1510 tp->link_config.orig_autoneg = tp->link_config.autoneg; 2043 u32 advertising;
1511 } 2044
2045 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
2046
2047 tp->link_config.phy_is_low_power = 1;
2048
2049 tp->link_config.orig_speed = phydev->speed;
2050 tp->link_config.orig_duplex = phydev->duplex;
2051 tp->link_config.orig_autoneg = phydev->autoneg;
2052 tp->link_config.orig_advertising = phydev->advertising;
2053
2054 advertising = ADVERTISED_TP |
2055 ADVERTISED_Pause |
2056 ADVERTISED_Autoneg |
2057 ADVERTISED_10baseT_Half;
2058
2059 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2060 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
2061 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2062 advertising |=
2063 ADVERTISED_100baseT_Half |
2064 ADVERTISED_100baseT_Full |
2065 ADVERTISED_10baseT_Full;
2066 else
2067 advertising |= ADVERTISED_10baseT_Full;
2068 }
1512 2069
1513 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { 2070 phydev->advertising = advertising;
1514 tp->link_config.speed = SPEED_10; 2071
1515 tp->link_config.duplex = DUPLEX_HALF; 2072 phy_start_aneg(phydev);
1516 tp->link_config.autoneg = AUTONEG_ENABLE; 2073 }
1517 tg3_setup_phy(tp, 0); 2074 } else {
2075 if (tp->link_config.phy_is_low_power == 0) {
2076 tp->link_config.phy_is_low_power = 1;
2077 tp->link_config.orig_speed = tp->link_config.speed;
2078 tp->link_config.orig_duplex = tp->link_config.duplex;
2079 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2080 }
2081
2082 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2083 tp->link_config.speed = SPEED_10;
2084 tp->link_config.duplex = DUPLEX_HALF;
2085 tp->link_config.autoneg = AUTONEG_ENABLE;
2086 tg3_setup_phy(tp, 0);
2087 }
1518 } 2088 }
1519 2089
1520 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 2090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
@@ -1545,8 +2115,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1545 u32 mac_mode; 2115 u32 mac_mode;
1546 2116
1547 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { 2117 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1548 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); 2118 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1549 udelay(40); 2119 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2120 udelay(40);
2121 }
1550 2122
1551 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) 2123 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1552 mac_mode = MAC_MODE_PORT_MODE_GMII; 2124 mac_mode = MAC_MODE_PORT_MODE_GMII;
@@ -1671,212 +2243,6 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1671 return 0; 2243 return 0;
1672} 2244}
1673 2245
1674/* tp->lock is held. */
1675static void tg3_wait_for_event_ack(struct tg3 *tp)
1676{
1677 int i;
1678
1679 /* Wait for up to 2.5 milliseconds */
1680 for (i = 0; i < 250000; i++) {
1681 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1682 break;
1683 udelay(10);
1684 }
1685}
1686
1687/* tp->lock is held. */
1688static void tg3_ump_link_report(struct tg3 *tp)
1689{
1690 u32 reg;
1691 u32 val;
1692
1693 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1694 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1695 return;
1696
1697 tg3_wait_for_event_ack(tp);
1698
1699 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1700
1701 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1702
1703 val = 0;
1704 if (!tg3_readphy(tp, MII_BMCR, &reg))
1705 val = reg << 16;
1706 if (!tg3_readphy(tp, MII_BMSR, &reg))
1707 val |= (reg & 0xffff);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1709
1710 val = 0;
1711 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1712 val = reg << 16;
1713 if (!tg3_readphy(tp, MII_LPA, &reg))
1714 val |= (reg & 0xffff);
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1716
1717 val = 0;
1718 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1719 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1720 val = reg << 16;
1721 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1722 val |= (reg & 0xffff);
1723 }
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1725
1726 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1727 val = reg << 16;
1728 else
1729 val = 0;
1730 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1731
1732 val = tr32(GRC_RX_CPU_EVENT);
1733 val |= GRC_RX_CPU_DRIVER_EVENT;
1734 tw32_f(GRC_RX_CPU_EVENT, val);
1735}
1736
1737static void tg3_link_report(struct tg3 *tp)
1738{
1739 if (!netif_carrier_ok(tp->dev)) {
1740 if (netif_msg_link(tp))
1741 printk(KERN_INFO PFX "%s: Link is down.\n",
1742 tp->dev->name);
1743 tg3_ump_link_report(tp);
1744 } else if (netif_msg_link(tp)) {
1745 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1746 tp->dev->name,
1747 (tp->link_config.active_speed == SPEED_1000 ?
1748 1000 :
1749 (tp->link_config.active_speed == SPEED_100 ?
1750 100 : 10)),
1751 (tp->link_config.active_duplex == DUPLEX_FULL ?
1752 "full" : "half"));
1753
1754 printk(KERN_INFO PFX
1755 "%s: Flow control is %s for TX and %s for RX.\n",
1756 tp->dev->name,
1757 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1758 "on" : "off",
1759 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1760 "on" : "off");
1761 tg3_ump_link_report(tp);
1762 }
1763}
1764
1765static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1766{
1767 u16 miireg;
1768
1769 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1770 miireg = ADVERTISE_PAUSE_CAP;
1771 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1772 miireg = ADVERTISE_PAUSE_ASYM;
1773 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1774 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1775 else
1776 miireg = 0;
1777
1778 return miireg;
1779}
1780
1781static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1782{
1783 u16 miireg;
1784
1785 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1786 miireg = ADVERTISE_1000XPAUSE;
1787 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1788 miireg = ADVERTISE_1000XPSE_ASYM;
1789 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1790 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1791 else
1792 miireg = 0;
1793
1794 return miireg;
1795}
1796
1797static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1798{
1799 u8 cap = 0;
1800
1801 if (lcladv & ADVERTISE_PAUSE_CAP) {
1802 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1803 if (rmtadv & LPA_PAUSE_CAP)
1804 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1805 else if (rmtadv & LPA_PAUSE_ASYM)
1806 cap = TG3_FLOW_CTRL_RX;
1807 } else {
1808 if (rmtadv & LPA_PAUSE_CAP)
1809 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1810 }
1811 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1812 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1813 cap = TG3_FLOW_CTRL_TX;
1814 }
1815
1816 return cap;
1817}
1818
1819static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1820{
1821 u8 cap = 0;
1822
1823 if (lcladv & ADVERTISE_1000XPAUSE) {
1824 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1825 if (rmtadv & LPA_1000XPAUSE)
1826 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1827 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1828 cap = TG3_FLOW_CTRL_RX;
1829 } else {
1830 if (rmtadv & LPA_1000XPAUSE)
1831 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1832 }
1833 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1834 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1835 cap = TG3_FLOW_CTRL_TX;
1836 }
1837
1838 return cap;
1839}
1840
1841static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1842{
1843 u8 new_tg3_flags = 0;
1844 u32 old_rx_mode = tp->rx_mode;
1845 u32 old_tx_mode = tp->tx_mode;
1846
1847 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1848 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1849 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1850 new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
1851 remote_adv);
1852 else
1853 new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
1854 remote_adv);
1855 } else {
1856 new_tg3_flags = tp->link_config.flowctrl;
1857 }
1858
1859 tp->link_config.active_flowctrl = new_tg3_flags;
1860
1861 if (new_tg3_flags & TG3_FLOW_CTRL_RX)
1862 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1863 else
1864 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1865
1866 if (old_rx_mode != tp->rx_mode) {
1867 tw32_f(MAC_RX_MODE, tp->rx_mode);
1868 }
1869
1870 if (new_tg3_flags & TG3_FLOW_CTRL_TX)
1871 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1872 else
1873 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1874
1875 if (old_tx_mode != tp->tx_mode) {
1876 tw32_f(MAC_TX_MODE, tp->tx_mode);
1877 }
1878}
1879
1880static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) 2246static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1881{ 2247{
1882 switch (val & MII_TG3_AUX_STAT_SPDMASK) { 2248 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
@@ -1921,7 +2287,7 @@ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8
1921 *speed = SPEED_INVALID; 2287 *speed = SPEED_INVALID;
1922 *duplex = DUPLEX_INVALID; 2288 *duplex = DUPLEX_INVALID;
1923 break; 2289 break;
1924 }; 2290 }
1925} 2291}
1926 2292
1927static void tg3_phy_copper_begin(struct tg3 *tp) 2293static void tg3_phy_copper_begin(struct tg3 *tp)
@@ -2033,7 +2399,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
2033 case SPEED_1000: 2399 case SPEED_1000:
2034 bmcr |= TG3_BMCR_SPEED1000; 2400 bmcr |= TG3_BMCR_SPEED1000;
2035 break; 2401 break;
2036 }; 2402 }
2037 2403
2038 if (tp->link_config.duplex == DUPLEX_FULL) 2404 if (tp->link_config.duplex == DUPLEX_FULL)
2039 bmcr |= BMCR_FULLDPLX; 2405 bmcr |= BMCR_FULLDPLX;
@@ -2731,7 +3097,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2731 default: 3097 default:
2732 ret = ANEG_FAILED; 3098 ret = ANEG_FAILED;
2733 break; 3099 break;
2734 }; 3100 }
2735 3101
2736 return ret; 3102 return ret;
2737} 3103}
@@ -3572,7 +3938,7 @@ static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3572 3938
3573 default: 3939 default:
3574 return -EINVAL; 3940 return -EINVAL;
3575 }; 3941 }
3576 3942
3577 /* Do not overwrite any of the map or rp information 3943 /* Do not overwrite any of the map or rp information
3578 * until we are sure we can commit to a new buffer. 3944 * until we are sure we can commit to a new buffer.
@@ -3632,7 +3998,7 @@ static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3632 3998
3633 default: 3999 default:
3634 return; 4000 return;
3635 }; 4001 }
3636 4002
3637 dest_map->skb = src_map->skb; 4003 dest_map->skb = src_map->skb;
3638 pci_unmap_addr_set(dest_map, mapping, 4004 pci_unmap_addr_set(dest_map, mapping,
@@ -3842,7 +4208,15 @@ static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
3842 sblk->status = SD_STATUS_UPDATED | 4208 sblk->status = SD_STATUS_UPDATED |
3843 (sblk->status & ~SD_STATUS_LINK_CHG); 4209 (sblk->status & ~SD_STATUS_LINK_CHG);
3844 spin_lock(&tp->lock); 4210 spin_lock(&tp->lock);
3845 tg3_setup_phy(tp, 0); 4211 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4212 tw32_f(MAC_STATUS,
4213 (MAC_STATUS_SYNC_CHANGED |
4214 MAC_STATUS_CFG_CHANGED |
4215 MAC_STATUS_MI_COMPLETION |
4216 MAC_STATUS_LNKSTATE_CHANGED));
4217 udelay(40);
4218 } else
4219 tg3_setup_phy(tp, 0);
3846 spin_unlock(&tp->lock); 4220 spin_unlock(&tp->lock);
3847 } 4221 }
3848 } 4222 }
@@ -4130,6 +4504,7 @@ static void tg3_poll_controller(struct net_device *dev)
4130static void tg3_reset_task(struct work_struct *work) 4504static void tg3_reset_task(struct work_struct *work)
4131{ 4505{
4132 struct tg3 *tp = container_of(work, struct tg3, reset_task); 4506 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4507 int err;
4133 unsigned int restart_timer; 4508 unsigned int restart_timer;
4134 4509
4135 tg3_full_lock(tp, 0); 4510 tg3_full_lock(tp, 0);
@@ -4141,6 +4516,8 @@ static void tg3_reset_task(struct work_struct *work)
4141 4516
4142 tg3_full_unlock(tp); 4517 tg3_full_unlock(tp);
4143 4518
4519 tg3_phy_stop(tp);
4520
4144 tg3_netif_stop(tp); 4521 tg3_netif_stop(tp);
4145 4522
4146 tg3_full_lock(tp, 1); 4523 tg3_full_lock(tp, 1);
@@ -4156,7 +4533,8 @@ static void tg3_reset_task(struct work_struct *work)
4156 } 4533 }
4157 4534
4158 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); 4535 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4159 if (tg3_init_hw(tp, 1)) 4536 err = tg3_init_hw(tp, 1);
4537 if (err)
4160 goto out; 4538 goto out;
4161 4539
4162 tg3_netif_start(tp); 4540 tg3_netif_start(tp);
@@ -4166,6 +4544,9 @@ static void tg3_reset_task(struct work_struct *work)
4166 4544
4167out: 4545out:
4168 tg3_full_unlock(tp); 4546 tg3_full_unlock(tp);
4547
4548 if (!err)
4549 tg3_phy_start(tp);
4169} 4550}
4170 4551
4171static void tg3_dump_short_state(struct tg3 *tp) 4552static void tg3_dump_short_state(struct tg3 *tp)
@@ -4669,6 +5050,8 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4669 return 0; 5050 return 0;
4670 } 5051 }
4671 5052
5053 tg3_phy_stop(tp);
5054
4672 tg3_netif_stop(tp); 5055 tg3_netif_stop(tp);
4673 5056
4674 tg3_full_lock(tp, 1); 5057 tg3_full_lock(tp, 1);
@@ -4684,6 +5067,9 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4684 5067
4685 tg3_full_unlock(tp); 5068 tg3_full_unlock(tp);
4686 5069
5070 if (!err)
5071 tg3_phy_start(tp);
5072
4687 return err; 5073 return err;
4688} 5074}
4689 5075
@@ -4975,7 +5361,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int
4975 5361
4976 default: 5362 default:
4977 break; 5363 break;
4978 }; 5364 }
4979 } 5365 }
4980 5366
4981 val = tr32(ofs); 5367 val = tr32(ofs);
@@ -5217,7 +5603,7 @@ static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5217 5603
5218 default: 5604 default:
5219 break; 5605 break;
5220 }; 5606 }
5221 } 5607 }
5222 5608
5223 if (kind == RESET_KIND_INIT || 5609 if (kind == RESET_KIND_INIT ||
@@ -5242,7 +5628,7 @@ static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5242 5628
5243 default: 5629 default:
5244 break; 5630 break;
5245 }; 5631 }
5246 } 5632 }
5247 5633
5248 if (kind == RESET_KIND_SHUTDOWN) 5634 if (kind == RESET_KIND_SHUTDOWN)
@@ -5271,7 +5657,7 @@ static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5271 5657
5272 default: 5658 default:
5273 break; 5659 break;
5274 }; 5660 }
5275 } 5661 }
5276} 5662}
5277 5663
@@ -5393,6 +5779,8 @@ static int tg3_chip_reset(struct tg3 *tp)
5393 5779
5394 tg3_nvram_lock(tp); 5780 tg3_nvram_lock(tp);
5395 5781
5782 tg3_mdio_stop(tp);
5783
5396 /* No matching tg3_nvram_unlock() after this because 5784 /* No matching tg3_nvram_unlock() after this because
5397 * chip reset below will undo the nvram lock. 5785 * chip reset below will undo the nvram lock.
5398 */ 5786 */
@@ -5408,7 +5796,8 @@ static int tg3_chip_reset(struct tg3 *tp)
5408 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 5796 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5409 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 5797 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 5798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5411 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 5799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
5800 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
5412 tw32(GRC_FASTBOOT_PC, 0); 5801 tw32(GRC_FASTBOOT_PC, 0);
5413 5802
5414 /* 5803 /*
@@ -5544,6 +5933,8 @@ static int tg3_chip_reset(struct tg3 *tp)
5544 tw32_f(MAC_MODE, 0); 5933 tw32_f(MAC_MODE, 0);
5545 udelay(40); 5934 udelay(40);
5546 5935
5936 tg3_mdio_start(tp);
5937
5547 err = tg3_poll_fw(tp); 5938 err = tg3_poll_fw(tp);
5548 if (err) 5939 if (err)
5549 return err; 5940 return err;
@@ -6623,7 +7014,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6623 tg3_abort_hw(tp, 1); 7014 tg3_abort_hw(tp, 1);
6624 } 7015 }
6625 7016
6626 if (reset_phy) 7017 if (reset_phy &&
7018 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6627 tg3_phy_reset(tp); 7019 tg3_phy_reset(tp);
6628 7020
6629 err = tg3_chip_reset(tp); 7021 err = tg3_chip_reset(tp);
@@ -6699,7 +7091,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6699 return err; 7091 return err;
6700 7092
6701 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && 7093 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6702 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { 7094 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7095 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6703 /* This value is determined during the probe time DMA 7096 /* This value is determined during the probe time DMA
6704 * engine test, tg3_test_dma. 7097 * engine test, tg3_test_dma.
6705 */ 7098 */
@@ -6938,7 +7331,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6938 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | 7331 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6939 RDMAC_MODE_LNGREAD_ENAB); 7332 RDMAC_MODE_LNGREAD_ENAB);
6940 7333
6941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) 7334 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7335 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
6942 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | 7336 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6943 RDMAC_MODE_MBUF_RBD_CRPT_ENAB | 7337 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6944 RDMAC_MODE_MBUF_SBD_CRPT_ENAB; 7338 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
@@ -7106,8 +7500,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7106 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) || 7500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7107 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) || 7501 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7108 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) || 7502 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7109 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)) 7503 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) ||
7110 val |= (1 << 29); 7504 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785))
7505 val |= WDMAC_MODE_STATUS_TAG_FIX;
7111 7506
7112 tw32_f(WDMAC_MODE, val); 7507 tw32_f(WDMAC_MODE, val);
7113 udelay(40); 7508 udelay(40);
@@ -7168,23 +7563,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7168 7563
7169 tp->rx_mode = RX_MODE_ENABLE; 7564 tp->rx_mode = RX_MODE_ENABLE;
7170 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 7565 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7171 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 7566 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7567 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
7568 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7172 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; 7569 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7173 7570
7174 tw32_f(MAC_RX_MODE, tp->rx_mode); 7571 tw32_f(MAC_RX_MODE, tp->rx_mode);
7175 udelay(10); 7572 udelay(10);
7176 7573
7177 if (tp->link_config.phy_is_low_power) {
7178 tp->link_config.phy_is_low_power = 0;
7179 tp->link_config.speed = tp->link_config.orig_speed;
7180 tp->link_config.duplex = tp->link_config.orig_duplex;
7181 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7182 }
7183
7184 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
7185 tw32_f(MAC_MI_MODE, tp->mi_mode);
7186 udelay(80);
7187
7188 tw32(MAC_LED_CTRL, tp->led_ctrl); 7574 tw32(MAC_LED_CTRL, tp->led_ctrl);
7189 7575
7190 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); 7576 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
@@ -7231,19 +7617,28 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7231 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 7617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7232 } 7618 }
7233 7619
7234 err = tg3_setup_phy(tp, 0); 7620 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7235 if (err) 7621 if (tp->link_config.phy_is_low_power) {
7236 return err; 7622 tp->link_config.phy_is_low_power = 0;
7623 tp->link_config.speed = tp->link_config.orig_speed;
7624 tp->link_config.duplex = tp->link_config.orig_duplex;
7625 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7626 }
7237 7627
7238 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && 7628 err = tg3_setup_phy(tp, 0);
7239 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) { 7629 if (err)
7240 u32 tmp; 7630 return err;
7241 7631
7242 /* Clear CRC stats. */ 7632 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7243 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { 7633 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7244 tg3_writephy(tp, MII_TG3_TEST1, 7634 u32 tmp;
7245 tmp | MII_TG3_TEST1_CRC_EN); 7635
7246 tg3_readphy(tp, 0x14, &tmp); 7636 /* Clear CRC stats. */
7637 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7638 tg3_writephy(tp, MII_TG3_TEST1,
7639 tmp | MII_TG3_TEST1_CRC_EN);
7640 tg3_readphy(tp, 0x14, &tmp);
7641 }
7247 } 7642 }
7248 } 7643 }
7249 7644
@@ -7296,7 +7691,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7296 7691
7297 default: 7692 default:
7298 break; 7693 break;
7299 }; 7694 }
7300 7695
7301 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) 7696 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7302 /* Write our heartbeat update interval to APE. */ 7697 /* Write our heartbeat update interval to APE. */
@@ -7758,6 +8153,8 @@ static int tg3_open(struct net_device *dev)
7758 } 8153 }
7759 } 8154 }
7760 8155
8156 tg3_phy_start(tp);
8157
7761 tg3_full_lock(tp, 0); 8158 tg3_full_lock(tp, 0);
7762 8159
7763 add_timer(&tp->timer); 8160 add_timer(&tp->timer);
@@ -8559,7 +8956,13 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
8559 8956
8560static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 8957static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8561{ 8958{
8562 struct tg3 *tp = netdev_priv(dev); 8959 struct tg3 *tp = netdev_priv(dev);
8960
8961 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8962 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8963 return -EAGAIN;
8964 return phy_ethtool_gset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8965 }
8563 8966
8564 cmd->supported = (SUPPORTED_Autoneg); 8967 cmd->supported = (SUPPORTED_Autoneg);
8565 8968
@@ -8596,6 +8999,12 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8596{ 8999{
8597 struct tg3 *tp = netdev_priv(dev); 9000 struct tg3 *tp = netdev_priv(dev);
8598 9001
9002 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9003 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9004 return -EAGAIN;
9005 return phy_ethtool_sset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
9006 }
9007
8599 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { 9008 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8600 /* These are the only valid advertisement bits allowed. */ 9009 /* These are the only valid advertisement bits allowed. */
8601 if (cmd->autoneg == AUTONEG_ENABLE && 9010 if (cmd->autoneg == AUTONEG_ENABLE &&
@@ -8628,7 +9037,7 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8628 tp->link_config.advertising = 0; 9037 tp->link_config.advertising = 0;
8629 tp->link_config.speed = cmd->speed; 9038 tp->link_config.speed = cmd->speed;
8630 tp->link_config.duplex = cmd->duplex; 9039 tp->link_config.duplex = cmd->duplex;
8631 } 9040 }
8632 9041
8633 tp->link_config.orig_speed = tp->link_config.speed; 9042 tp->link_config.orig_speed = tp->link_config.speed;
8634 tp->link_config.orig_duplex = tp->link_config.duplex; 9043 tp->link_config.orig_duplex = tp->link_config.duplex;
@@ -8711,7 +9120,10 @@ static int tg3_set_tso(struct net_device *dev, u32 value)
8711 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) { 9120 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8712 if (value) { 9121 if (value) {
8713 dev->features |= NETIF_F_TSO6; 9122 dev->features |= NETIF_F_TSO6;
8714 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 9123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9124 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9125 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9126 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8715 dev->features |= NETIF_F_TSO_ECN; 9127 dev->features |= NETIF_F_TSO_ECN;
8716 } else 9128 } else
8717 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN); 9129 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
@@ -8722,7 +9134,6 @@ static int tg3_set_tso(struct net_device *dev, u32 value)
8722static int tg3_nway_reset(struct net_device *dev) 9134static int tg3_nway_reset(struct net_device *dev)
8723{ 9135{
8724 struct tg3 *tp = netdev_priv(dev); 9136 struct tg3 *tp = netdev_priv(dev);
8725 u32 bmcr;
8726 int r; 9137 int r;
8727 9138
8728 if (!netif_running(dev)) 9139 if (!netif_running(dev))
@@ -8731,17 +9142,25 @@ static int tg3_nway_reset(struct net_device *dev)
8731 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) 9142 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8732 return -EINVAL; 9143 return -EINVAL;
8733 9144
8734 spin_lock_bh(&tp->lock); 9145 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8735 r = -EINVAL; 9146 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8736 tg3_readphy(tp, MII_BMCR, &bmcr); 9147 return -EAGAIN;
8737 if (!tg3_readphy(tp, MII_BMCR, &bmcr) && 9148 r = phy_start_aneg(tp->mdio_bus.phy_map[PHY_ADDR]);
8738 ((bmcr & BMCR_ANENABLE) || 9149 } else {
8739 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) { 9150 u32 bmcr;
8740 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | 9151
8741 BMCR_ANENABLE); 9152 spin_lock_bh(&tp->lock);
8742 r = 0; 9153 r = -EINVAL;
9154 tg3_readphy(tp, MII_BMCR, &bmcr);
9155 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9156 ((bmcr & BMCR_ANENABLE) ||
9157 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9158 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9159 BMCR_ANENABLE);
9160 r = 0;
9161 }
9162 spin_unlock_bh(&tp->lock);
8743 } 9163 }
8744 spin_unlock_bh(&tp->lock);
8745 9164
8746 return r; 9165 return r;
8747} 9166}
@@ -8783,6 +9202,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
8783 return -EINVAL; 9202 return -EINVAL;
8784 9203
8785 if (netif_running(dev)) { 9204 if (netif_running(dev)) {
9205 tg3_phy_stop(tp);
8786 tg3_netif_stop(tp); 9206 tg3_netif_stop(tp);
8787 irq_sync = 1; 9207 irq_sync = 1;
8788 } 9208 }
@@ -8806,6 +9226,9 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
8806 9226
8807 tg3_full_unlock(tp); 9227 tg3_full_unlock(tp);
8808 9228
9229 if (irq_sync && !err)
9230 tg3_phy_start(tp);
9231
8809 return err; 9232 return err;
8810} 9233}
8811 9234
@@ -8829,36 +9252,92 @@ static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam
8829static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 9252static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8830{ 9253{
8831 struct tg3 *tp = netdev_priv(dev); 9254 struct tg3 *tp = netdev_priv(dev);
8832 int irq_sync = 0, err = 0; 9255 int err = 0;
8833 9256
8834 if (netif_running(dev)) { 9257 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8835 tg3_netif_stop(tp); 9258 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8836 irq_sync = 1; 9259 return -EAGAIN;
8837 }
8838 9260
8839 tg3_full_lock(tp, irq_sync); 9261 if (epause->autoneg) {
9262 u32 newadv;
9263 struct phy_device *phydev;
8840 9264
8841 if (epause->autoneg) 9265 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
8842 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8843 else
8844 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8845 if (epause->rx_pause)
8846 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
8847 else
8848 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
8849 if (epause->tx_pause)
8850 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
8851 else
8852 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
8853 9266
8854 if (netif_running(dev)) { 9267 if (epause->rx_pause) {
8855 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 9268 if (epause->tx_pause)
8856 err = tg3_restart_hw(tp, 1); 9269 newadv = ADVERTISED_Pause;
8857 if (!err) 9270 else
8858 tg3_netif_start(tp); 9271 newadv = ADVERTISED_Pause |
8859 } 9272 ADVERTISED_Asym_Pause;
9273 } else if (epause->tx_pause) {
9274 newadv = ADVERTISED_Asym_Pause;
9275 } else
9276 newadv = 0;
9277
9278 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9279 u32 oldadv = phydev->advertising &
9280 (ADVERTISED_Pause |
9281 ADVERTISED_Asym_Pause);
9282 if (oldadv != newadv) {
9283 phydev->advertising &=
9284 ~(ADVERTISED_Pause |
9285 ADVERTISED_Asym_Pause);
9286 phydev->advertising |= newadv;
9287 err = phy_start_aneg(phydev);
9288 }
9289 } else {
9290 tp->link_config.advertising &=
9291 ~(ADVERTISED_Pause |
9292 ADVERTISED_Asym_Pause);
9293 tp->link_config.advertising |= newadv;
9294 }
9295 } else {
9296 if (epause->rx_pause)
9297 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9298 else
9299 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
8860 9300
8861 tg3_full_unlock(tp); 9301 if (epause->tx_pause)
9302 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9303 else
9304 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9305
9306 if (netif_running(dev))
9307 tg3_setup_flow_control(tp, 0, 0);
9308 }
9309 } else {
9310 int irq_sync = 0;
9311
9312 if (netif_running(dev)) {
9313 tg3_netif_stop(tp);
9314 irq_sync = 1;
9315 }
9316
9317 tg3_full_lock(tp, irq_sync);
9318
9319 if (epause->autoneg)
9320 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9321 else
9322 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9323 if (epause->rx_pause)
9324 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9325 else
9326 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9327 if (epause->tx_pause)
9328 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9329 else
9330 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9331
9332 if (netif_running(dev)) {
9333 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9334 err = tg3_restart_hw(tp, 1);
9335 if (!err)
9336 tg3_netif_start(tp);
9337 }
9338
9339 tg3_full_unlock(tp);
9340 }
8862 9341
8863 return err; 9342 return err;
8864} 9343}
@@ -8902,7 +9381,8 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 9381 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8903 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 9382 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
8904 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 9383 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 9384 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9385 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8906 ethtool_op_set_tx_ipv6_csum(dev, data); 9386 ethtool_op_set_tx_ipv6_csum(dev, data);
8907 else 9387 else
8908 ethtool_op_set_tx_csum(dev, data); 9388 ethtool_op_set_tx_csum(dev, data);
@@ -9423,7 +9903,8 @@ static int tg3_test_memory(struct tg3 *tp)
9423 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 9903 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9424 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 9904 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 9905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 9906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9907 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9427 mem_tbl = mem_tbl_5755; 9908 mem_tbl = mem_tbl_5755;
9428 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 9909 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9429 mem_tbl = mem_tbl_5906; 9910 mem_tbl = mem_tbl_5906;
@@ -9630,7 +10111,8 @@ static int tg3_test_loopback(struct tg3 *tp)
9630 return TG3_LOOPBACK_FAILED; 10111 return TG3_LOOPBACK_FAILED;
9631 10112
9632 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 10113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9633 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { 10114 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10115 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
9634 int i; 10116 int i;
9635 u32 status; 10117 u32 status;
9636 10118
@@ -9658,14 +10140,16 @@ static int tg3_test_loopback(struct tg3 *tp)
9658 err |= TG3_MAC_LOOPBACK_FAILED; 10140 err |= TG3_MAC_LOOPBACK_FAILED;
9659 10141
9660 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 10142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9661 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { 10143 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10144 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
9662 tw32(TG3_CPMU_CTRL, cpmuctrl); 10145 tw32(TG3_CPMU_CTRL, cpmuctrl);
9663 10146
9664 /* Release the mutex */ 10147 /* Release the mutex */
9665 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); 10148 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9666 } 10149 }
9667 10150
9668 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { 10151 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10152 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9669 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) 10153 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9670 err |= TG3_PHY_LOOPBACK_FAILED; 10154 err |= TG3_PHY_LOOPBACK_FAILED;
9671 } 10155 }
@@ -9692,9 +10176,10 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9692 data[1] = 1; 10176 data[1] = 1;
9693 } 10177 }
9694 if (etest->flags & ETH_TEST_FL_OFFLINE) { 10178 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9695 int err, irq_sync = 0; 10179 int err, err2 = 0, irq_sync = 0;
9696 10180
9697 if (netif_running(dev)) { 10181 if (netif_running(dev)) {
10182 tg3_phy_stop(tp);
9698 tg3_netif_stop(tp); 10183 tg3_netif_stop(tp);
9699 irq_sync = 1; 10184 irq_sync = 1;
9700 } 10185 }
@@ -9735,11 +10220,15 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9735 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 10220 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9736 if (netif_running(dev)) { 10221 if (netif_running(dev)) {
9737 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 10222 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9738 if (!tg3_restart_hw(tp, 1)) 10223 err2 = tg3_restart_hw(tp, 1);
10224 if (!err2)
9739 tg3_netif_start(tp); 10225 tg3_netif_start(tp);
9740 } 10226 }
9741 10227
9742 tg3_full_unlock(tp); 10228 tg3_full_unlock(tp);
10229
10230 if (irq_sync && !err2)
10231 tg3_phy_start(tp);
9743 } 10232 }
9744 if (tp->link_config.phy_is_low_power) 10233 if (tp->link_config.phy_is_low_power)
9745 tg3_set_power_state(tp, PCI_D3hot); 10234 tg3_set_power_state(tp, PCI_D3hot);
@@ -9752,6 +10241,12 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9752 struct tg3 *tp = netdev_priv(dev); 10241 struct tg3 *tp = netdev_priv(dev);
9753 int err; 10242 int err;
9754 10243
10244 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10245 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10246 return -EAGAIN;
10247 return phy_mii_ioctl(tp->mdio_bus.phy_map[PHY_ADDR], data, cmd);
10248 }
10249
9755 switch(cmd) { 10250 switch(cmd) {
9756 case SIOCGMIIPHY: 10251 case SIOCGMIIPHY:
9757 data->phy_id = PHY_ADDR; 10252 data->phy_id = PHY_ADDR;
@@ -10294,7 +10789,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
10294 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) 10789 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10295 tg3_get_5755_nvram_info(tp); 10790 tg3_get_5755_nvram_info(tp);
10296 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 10791 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10297 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) 10792 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10793 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10298 tg3_get_5787_nvram_info(tp); 10794 tg3_get_5787_nvram_info(tp);
10299 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 10795 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10300 tg3_get_5761_nvram_info(tp); 10796 tg3_get_5761_nvram_info(tp);
@@ -10625,6 +11121,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10625 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) && 11121 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
10626 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) && 11122 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
10627 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) && 11123 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
11124 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) &&
10628 (tp->nvram_jedecnum == JEDEC_ST) && 11125 (tp->nvram_jedecnum == JEDEC_ST) &&
10629 (nvram_cmd & NVRAM_CMD_FIRST)) { 11126 (nvram_cmd & NVRAM_CMD_FIRST)) {
10630 11127
@@ -10807,7 +11304,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10807 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); 11304 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10808 if (val == NIC_SRAM_DATA_SIG_MAGIC) { 11305 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10809 u32 nic_cfg, led_cfg; 11306 u32 nic_cfg, led_cfg;
10810 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id; 11307 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
10811 int eeprom_phy_serdes = 0; 11308 int eeprom_phy_serdes = 0;
10812 11309
10813 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); 11310 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
@@ -10821,6 +11318,9 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10821 (ver > 0) && (ver < 0x100)) 11318 (ver > 0) && (ver < 0x100))
10822 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); 11319 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10823 11320
11321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11322 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11323
10824 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == 11324 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10825 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) 11325 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10826 eeprom_phy_serdes = 1; 11326 eeprom_phy_serdes = 1;
@@ -10893,7 +11393,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10893 LED_CTRL_MODE_PHY_2); 11393 LED_CTRL_MODE_PHY_2);
10894 break; 11394 break;
10895 11395
10896 }; 11396 }
10897 11397
10898 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 11398 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10899 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && 11399 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
@@ -10945,6 +11445,13 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10945 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) 11445 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10946 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; 11446 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10947 } 11447 }
11448
11449 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11450 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11451 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11452 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11453 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11454 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
10948 } 11455 }
10949} 11456}
10950 11457
@@ -11003,6 +11510,9 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
11003 u32 hw_phy_id, hw_phy_id_masked; 11510 u32 hw_phy_id, hw_phy_id_masked;
11004 int err; 11511 int err;
11005 11512
11513 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11514 return tg3_phy_init(tp);
11515
11006 /* Reading the PHY ID register can conflict with ASF 11516 /* Reading the PHY ID register can conflict with ASF
11007 * firwmare access to the PHY hardware. 11517 * firwmare access to the PHY hardware.
11008 */ 11518 */
@@ -11525,6 +12035,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11525 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 12035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11526 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11527 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 12037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11528 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || 12039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11529 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) 12040 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11530 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; 12041 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
@@ -11546,6 +12057,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11546 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 12057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11547 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11548 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 12059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12060 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11549 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 12061 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11550 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; 12062 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11551 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; 12063 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
@@ -11558,14 +12070,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11558 } 12070 }
11559 } 12071 }
11560 12072
11561 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && 12073 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11562 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 && 12074 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11563 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11564 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
11565 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
11566 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
11567 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
11568 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
11569 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE; 12075 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11570 12076
11571 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); 12077 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
@@ -11754,7 +12260,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11754 } 12260 }
11755 12261
11756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12262 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11757 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { 12263 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
11758 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; 12265 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
11759 12266
11760 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 || 12267 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
@@ -11847,7 +12354,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11847 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG; 12354 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
11848 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) 12355 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
11849 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM; 12356 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
11850 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) 12357 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12358 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
11851 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; 12359 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
11852 } 12360 }
11853 12361
@@ -11858,8 +12366,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11858 tp->phy_otp = TG3_OTP_DEFAULT; 12366 tp->phy_otp = TG3_OTP_DEFAULT;
11859 } 12367 }
11860 12368
11861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12369 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
11862 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11863 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; 12370 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
11864 else 12371 else
11865 tp->mi_mode = MAC_MI_MODE_BASE; 12372 tp->mi_mode = MAC_MI_MODE_BASE;
@@ -11869,9 +12376,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11869 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) 12376 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
11870 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; 12377 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
11871 12378
11872 /* Initialize MAC MI mode, polling disabled. */ 12379 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11873 tw32_f(MAC_MI_MODE, tp->mi_mode); 12380 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
11874 udelay(80); 12381
12382 err = tg3_mdio_init(tp);
12383 if (err)
12384 return err;
11875 12385
11876 /* Initialize data/descriptor byte/word swapping. */ 12386 /* Initialize data/descriptor byte/word swapping. */
11877 val = tr32(GRC_MODE); 12387 val = tr32(GRC_MODE);
@@ -11952,6 +12462,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11952 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n", 12462 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11953 pci_name(tp->pdev), err); 12463 pci_name(tp->pdev), err);
11954 /* ... but do not return immediately ... */ 12464 /* ... but do not return immediately ... */
12465 tg3_mdio_fini(tp);
11955 } 12466 }
11956 12467
11957 tg3_read_partno(tp); 12468 tg3_read_partno(tp);
@@ -11999,6 +12510,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 12510 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12001 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 12512 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12513 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 12514 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12003 tp->dev->hard_start_xmit = tg3_start_xmit; 12515 tp->dev->hard_start_xmit = tg3_start_xmit;
12004 else 12516 else
@@ -12201,7 +12713,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12201 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | 12713 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12202 DMA_RWCTRL_WRITE_BNDRY_384_PCIX); 12714 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12203 break; 12715 break;
12204 }; 12716 }
12205 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { 12717 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12206 switch (cacheline_size) { 12718 switch (cacheline_size) {
12207 case 16: 12719 case 16:
@@ -12218,7 +12730,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12218 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; 12730 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12219 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; 12731 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12220 break; 12732 break;
12221 }; 12733 }
12222 } else { 12734 } else {
12223 switch (cacheline_size) { 12735 switch (cacheline_size) {
12224 case 16: 12736 case 16:
@@ -12262,7 +12774,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12262 val |= (DMA_RWCTRL_READ_BNDRY_1024 | 12774 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12263 DMA_RWCTRL_WRITE_BNDRY_1024); 12775 DMA_RWCTRL_WRITE_BNDRY_1024);
12264 break; 12776 break;
12265 }; 12777 }
12266 } 12778 }
12267 12779
12268out: 12780out:
@@ -12622,7 +13134,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
12622 case PHY_ID_BCM8002: return "8002/serdes"; 13134 case PHY_ID_BCM8002: return "8002/serdes";
12623 case 0: return "serdes"; 13135 case 0: return "serdes";
12624 default: return "unknown"; 13136 default: return "unknown";
12625 }; 13137 }
12626} 13138}
12627 13139
12628static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) 13140static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
@@ -12923,7 +13435,10 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
12923 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) && 13435 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
12924 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) 13436 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
12925 dev->features |= NETIF_F_TSO6; 13437 dev->features |= NETIF_F_TSO6;
12926 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 13438 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13439 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13440 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13441 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12927 dev->features |= NETIF_F_TSO_ECN; 13442 dev->features |= NETIF_F_TSO_ECN;
12928 } 13443 }
12929 13444
@@ -12989,7 +13504,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
12989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 13504 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 13505 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 13506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 13507 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13508 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12993 dev->features |= NETIF_F_IPV6_CSUM; 13509 dev->features |= NETIF_F_IPV6_CSUM;
12994 13510
12995 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; 13511 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
@@ -13071,6 +13587,12 @@ static void __devexit tg3_remove_one(struct pci_dev *pdev)
13071 struct tg3 *tp = netdev_priv(dev); 13587 struct tg3 *tp = netdev_priv(dev);
13072 13588
13073 flush_scheduled_work(); 13589 flush_scheduled_work();
13590
13591 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13592 tg3_phy_fini(tp);
13593 tg3_mdio_fini(tp);
13594 }
13595
13074 unregister_netdev(dev); 13596 unregister_netdev(dev);
13075 if (tp->aperegs) { 13597 if (tp->aperegs) {
13076 iounmap(tp->aperegs); 13598 iounmap(tp->aperegs);
@@ -13103,6 +13625,7 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13103 return 0; 13625 return 0;
13104 13626
13105 flush_scheduled_work(); 13627 flush_scheduled_work();
13628 tg3_phy_stop(tp);
13106 tg3_netif_stop(tp); 13629 tg3_netif_stop(tp);
13107 13630
13108 del_timer_sync(&tp->timer); 13631 del_timer_sync(&tp->timer);
@@ -13120,10 +13643,13 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13120 13643
13121 err = tg3_set_power_state(tp, pci_choose_state(pdev, state)); 13644 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
13122 if (err) { 13645 if (err) {
13646 int err2;
13647
13123 tg3_full_lock(tp, 0); 13648 tg3_full_lock(tp, 0);
13124 13649
13125 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 13650 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13126 if (tg3_restart_hw(tp, 1)) 13651 err2 = tg3_restart_hw(tp, 1);
13652 if (err2)
13127 goto out; 13653 goto out;
13128 13654
13129 tp->timer.expires = jiffies + tp->timer_offset; 13655 tp->timer.expires = jiffies + tp->timer_offset;
@@ -13134,6 +13660,9 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13134 13660
13135out: 13661out:
13136 tg3_full_unlock(tp); 13662 tg3_full_unlock(tp);
13663
13664 if (!err2)
13665 tg3_phy_start(tp);
13137 } 13666 }
13138 13667
13139 return err; 13668 return err;
@@ -13171,6 +13700,9 @@ static int tg3_resume(struct pci_dev *pdev)
13171out: 13700out:
13172 tg3_full_unlock(tp); 13701 tg3_full_unlock(tp);
13173 13702
13703 if (!err)
13704 tg3_phy_start(tp);
13705
13174 return err; 13706 return err;
13175} 13707}
13176 13708
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 0404f93baa29..df07842172b7 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -128,6 +128,7 @@
128#define ASIC_REV_USE_PROD_ID_REG 0x0f 128#define ASIC_REV_USE_PROD_ID_REG 0x0f
129#define ASIC_REV_5784 0x5784 129#define ASIC_REV_5784 0x5784
130#define ASIC_REV_5761 0x5761 130#define ASIC_REV_5761 0x5761
131#define ASIC_REV_5785 0x5785
131#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) 132#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
132#define CHIPREV_5700_AX 0x70 133#define CHIPREV_5700_AX 0x70
133#define CHIPREV_5700_BX 0x71 134#define CHIPREV_5700_BX 0x71
@@ -528,7 +529,23 @@
528#define MAC_SERDES_CFG 0x00000590 529#define MAC_SERDES_CFG 0x00000590
529#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 530#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
530#define MAC_SERDES_STAT 0x00000594 531#define MAC_SERDES_STAT 0x00000594
531/* 0x598 --> 0x5b0 unused */ 532/* 0x598 --> 0x5a0 unused */
533#define MAC_PHYCFG1 0x000005a0
534#define MAC_PHYCFG1_RGMII_INT 0x00000001
535#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
536#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
537#define MAC_PHYCFG1_TXC_DRV 0x20000000
538#define MAC_PHYCFG2 0x000005a4
539#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
540#define MAC_EXT_RGMII_MODE 0x000005a8
541#define MAC_RGMII_MODE_TX_ENABLE 0x00000001
542#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
543#define MAC_RGMII_MODE_TX_RESET 0x00000004
544#define MAC_RGMII_MODE_RX_INT_B 0x00000100
545#define MAC_RGMII_MODE_RX_QUALITY 0x00000200
546#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
547#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
548/* 0x5ac --> 0x5b0 unused */
532#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ 549#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
533#define SERDES_RX_SIG_DETECT 0x00000400 550#define SERDES_RX_SIG_DETECT 0x00000400
534#define SG_DIG_CTRL 0x000005b0 551#define SG_DIG_CTRL 0x000005b0
@@ -1109,6 +1126,7 @@
1109#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1126#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1110#define WDMAC_MODE_LNGREAD_ENAB 0x00000200 1127#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1111#define WDMAC_MODE_RX_ACCEL 0x00000400 1128#define WDMAC_MODE_RX_ACCEL 0x00000400
1129#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
1112#define WDMAC_STATUS 0x00004c04 1130#define WDMAC_STATUS 0x00004c04
1113#define WDMAC_STATUS_TGTABORT 0x00000004 1131#define WDMAC_STATUS_TGTABORT 0x00000004
1114#define WDMAC_STATUS_MSTABORT 0x00000008 1132#define WDMAC_STATUS_MSTABORT 0x00000008
@@ -1713,6 +1731,12 @@
1713#define NIC_SRAM_DATA_CFG_3 0x00000d3c 1731#define NIC_SRAM_DATA_CFG_3 0x00000d3c
1714#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 1732#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
1715 1733
1734#define NIC_SRAM_DATA_CFG_4 0x00000d60
1735#define NIC_SRAM_GMII_MODE 0x00000002
1736#define NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004
1737#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
1738#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
1739
1716#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 1740#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1717 1741
1718#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 1742#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
@@ -2204,6 +2228,7 @@ struct tg3_link_config {
2204 u16 orig_speed; 2228 u16 orig_speed;
2205 u8 orig_duplex; 2229 u8 orig_duplex;
2206 u8 orig_autoneg; 2230 u8 orig_autoneg;
2231 u32 orig_advertising;
2207}; 2232};
2208 2233
2209struct tg3_bufmgr_config { 2234struct tg3_bufmgr_config {
@@ -2479,6 +2504,13 @@ struct tg3 {
2479#define TG3_FLG3_ENABLE_APE 0x00000002 2504#define TG3_FLG3_ENABLE_APE 0x00000002
2480#define TG3_FLG3_5761_5784_AX_FIXES 0x00000004 2505#define TG3_FLG3_5761_5784_AX_FIXES 0x00000004
2481#define TG3_FLG3_5701_DMA_BUG 0x00000008 2506#define TG3_FLG3_5701_DMA_BUG 0x00000008
2507#define TG3_FLG3_USE_PHYLIB 0x00000010
2508#define TG3_FLG3_MDIOBUS_INITED 0x00000020
2509#define TG3_FLG3_MDIOBUS_PAUSED 0x00000040
2510#define TG3_FLG3_PHY_CONNECTED 0x00000080
2511#define TG3_FLG3_RGMII_STD_IBND_DISABLE 0x00000100
2512#define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
2513#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
2482 2514
2483 struct timer_list timer; 2515 struct timer_list timer;
2484 u16 timer_counter; 2516 u16 timer_counter;
@@ -2519,6 +2551,9 @@ struct tg3 {
2519 int msi_cap; 2551 int msi_cap;
2520 int pcix_cap; 2552 int pcix_cap;
2521 2553
2554 struct mii_bus mdio_bus;
2555 int mdio_irq[PHY_MAX_ADDR];
2556
2522 /* PHY info */ 2557 /* PHY info */
2523 u32 phy_id; 2558 u32 phy_id;
2524#define PHY_ID_MASK 0xfffffff0 2559#define PHY_ID_MASK 0xfffffff0
@@ -2546,6 +2581,9 @@ struct tg3 {
2546#define PHY_REV_BCM5401_B2 0x3 2581#define PHY_REV_BCM5401_B2 0x3
2547#define PHY_REV_BCM5401_C0 0x6 2582#define PHY_REV_BCM5401_C0 0x6
2548#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */ 2583#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
2584#define TG3_PHY_ID_BCM50610 0x143bd60
2585#define TG3_PHY_ID_BCMAC131 0x143bc70
2586
2549 2587
2550 u32 led_ctrl; 2588 u32 led_ctrl;
2551 u32 phy_otp; 2589 u32 phy_otp;
diff --git a/drivers/net/tlan.c b/drivers/net/tlan.c
index 0166407d7061..85246ed7cb9c 100644
--- a/drivers/net/tlan.c
+++ b/drivers/net/tlan.c
@@ -13,8 +13,6 @@
13 * This software may be used and distributed according to the terms 13 * This software may be used and distributed according to the terms
14 * of the GNU General Public License, incorporated herein by reference. 14 * of the GNU General Public License, incorporated herein by reference.
15 * 15 *
16 ** This file is best viewed/edited with columns>=132.
17 *
18 ** Useful (if not required) reading: 16 ** Useful (if not required) reading:
19 * 17 *
20 * Texas Instruments, ThunderLAN Programmer's Guide, 18 * Texas Instruments, ThunderLAN Programmer's Guide,
@@ -218,9 +216,7 @@ static int bbuf;
218module_param(bbuf, int, 0); 216module_param(bbuf, int, 0);
219MODULE_PARM_DESC(bbuf, "ThunderLAN use big buffer (0-1)"); 217MODULE_PARM_DESC(bbuf, "ThunderLAN use big buffer (0-1)");
220 218
221static u8 *TLanPadBuffer; 219static const char TLanSignature[] = "TLAN";
222static dma_addr_t TLanPadBufferDMA;
223static char TLanSignature[] = "TLAN";
224static const char tlan_banner[] = "ThunderLAN driver v1.15\n"; 220static const char tlan_banner[] = "ThunderLAN driver v1.15\n";
225static int tlan_have_pci; 221static int tlan_have_pci;
226static int tlan_have_eisa; 222static int tlan_have_eisa;
@@ -238,9 +234,11 @@ static struct board {
238 { "Compaq Netelligent 10 T PCI UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 }, 234 { "Compaq Netelligent 10 T PCI UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
239 { "Compaq Netelligent 10/100 TX PCI UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 }, 235 { "Compaq Netelligent 10/100 TX PCI UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
240 { "Compaq Integrated NetFlex-3/P", TLAN_ADAPTER_NONE, 0x83 }, 236 { "Compaq Integrated NetFlex-3/P", TLAN_ADAPTER_NONE, 0x83 },
241 { "Compaq NetFlex-3/P", TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83 }, 237 { "Compaq NetFlex-3/P",
238 TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83 },
242 { "Compaq NetFlex-3/P", TLAN_ADAPTER_NONE, 0x83 }, 239 { "Compaq NetFlex-3/P", TLAN_ADAPTER_NONE, 0x83 },
243 { "Compaq Netelligent Integrated 10/100 TX UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 }, 240 { "Compaq Netelligent Integrated 10/100 TX UTP",
241 TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
244 { "Compaq Netelligent Dual 10/100 TX PCI UTP", TLAN_ADAPTER_NONE, 0x83 }, 242 { "Compaq Netelligent Dual 10/100 TX PCI UTP", TLAN_ADAPTER_NONE, 0x83 },
245 { "Compaq Netelligent 10/100 TX Embedded UTP", TLAN_ADAPTER_NONE, 0x83 }, 243 { "Compaq Netelligent 10/100 TX Embedded UTP", TLAN_ADAPTER_NONE, 0x83 },
246 { "Olicom OC-2183/2185", TLAN_ADAPTER_USE_INTERN_10, 0x83 }, 244 { "Olicom OC-2183/2185", TLAN_ADAPTER_USE_INTERN_10, 0x83 },
@@ -248,8 +246,9 @@ static struct board {
248 { "Olicom OC-2326", TLAN_ADAPTER_USE_INTERN_10, 0xF8 }, 246 { "Olicom OC-2326", TLAN_ADAPTER_USE_INTERN_10, 0xF8 },
249 { "Compaq Netelligent 10/100 TX UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 }, 247 { "Compaq Netelligent 10/100 TX UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
250 { "Compaq Netelligent 10 T/2 PCI UTP/Coax", TLAN_ADAPTER_NONE, 0x83 }, 248 { "Compaq Netelligent 10 T/2 PCI UTP/Coax", TLAN_ADAPTER_NONE, 0x83 },
251 { "Compaq NetFlex-3/E", TLAN_ADAPTER_ACTIVITY_LED | /* EISA card */ 249 { "Compaq NetFlex-3/E",
252 TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83 }, 250 TLAN_ADAPTER_ACTIVITY_LED | /* EISA card */
251 TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83 },
253 { "Compaq NetFlex-3/E", TLAN_ADAPTER_ACTIVITY_LED, 0x83 }, /* EISA card */ 252 { "Compaq NetFlex-3/E", TLAN_ADAPTER_ACTIVITY_LED, 0x83 }, /* EISA card */
254}; 253};
255 254
@@ -294,12 +293,12 @@ static int TLan_Close( struct net_device *);
294static struct net_device_stats *TLan_GetStats( struct net_device *); 293static struct net_device_stats *TLan_GetStats( struct net_device *);
295static void TLan_SetMulticastList( struct net_device *); 294static void TLan_SetMulticastList( struct net_device *);
296static int TLan_ioctl( struct net_device *dev, struct ifreq *rq, int cmd); 295static int TLan_ioctl( struct net_device *dev, struct ifreq *rq, int cmd);
297static int TLan_probe1( struct pci_dev *pdev, long ioaddr, int irq, int rev, const struct pci_device_id *ent); 296static int TLan_probe1( struct pci_dev *pdev, long ioaddr,
297 int irq, int rev, const struct pci_device_id *ent);
298static void TLan_tx_timeout( struct net_device *dev); 298static void TLan_tx_timeout( struct net_device *dev);
299static void TLan_tx_timeout_work(struct work_struct *work); 299static void TLan_tx_timeout_work(struct work_struct *work);
300static int tlan_init_one( struct pci_dev *pdev, const struct pci_device_id *ent); 300static int tlan_init_one( struct pci_dev *pdev, const struct pci_device_id *ent);
301 301
302static u32 TLan_HandleInvalid( struct net_device *, u16 );
303static u32 TLan_HandleTxEOF( struct net_device *, u16 ); 302static u32 TLan_HandleTxEOF( struct net_device *, u16 );
304static u32 TLan_HandleStatOverflow( struct net_device *, u16 ); 303static u32 TLan_HandleStatOverflow( struct net_device *, u16 );
305static u32 TLan_HandleRxEOF( struct net_device *, u16 ); 304static u32 TLan_HandleRxEOF( struct net_device *, u16 );
@@ -348,29 +347,27 @@ static void TLan_EeReceiveByte( u16, u8 *, int );
348static int TLan_EeReadByte( struct net_device *, u8, u8 * ); 347static int TLan_EeReadByte( struct net_device *, u8, u8 * );
349 348
350 349
351static void 350static inline void
352TLan_StoreSKB( struct tlan_list_tag *tag, struct sk_buff *skb) 351TLan_StoreSKB( struct tlan_list_tag *tag, struct sk_buff *skb)
353{ 352{
354 unsigned long addr = (unsigned long)skb; 353 unsigned long addr = (unsigned long)skb;
355 tag->buffer[9].address = (u32)addr; 354 tag->buffer[9].address = addr;
356 addr >>= 31; /* >>= 32 is undefined for 32bit arch, stupid C */ 355 tag->buffer[8].address = upper_32_bits(addr);
357 addr >>= 1;
358 tag->buffer[8].address = (u32)addr;
359} 356}
360 357
361static struct sk_buff * 358static inline struct sk_buff *
362TLan_GetSKB( struct tlan_list_tag *tag) 359TLan_GetSKB( const struct tlan_list_tag *tag)
363{ 360{
364 unsigned long addr = tag->buffer[8].address; 361 unsigned long addr;
365 addr <<= 31; 362
366 addr <<= 1; 363 addr = tag->buffer[8].address;
367 addr |= tag->buffer[9].address; 364 addr |= (tag->buffer[9].address << 16) << 16;
368 return (struct sk_buff *) addr; 365 return (struct sk_buff *) addr;
369} 366}
370 367
371 368
372static TLanIntVectorFunc *TLanIntVector[TLAN_INT_NUMBER_OF_INTS] = { 369static TLanIntVectorFunc *TLanIntVector[TLAN_INT_NUMBER_OF_INTS] = {
373 TLan_HandleInvalid, 370 NULL,
374 TLan_HandleTxEOF, 371 TLan_HandleTxEOF,
375 TLan_HandleStatOverflow, 372 TLan_HandleStatOverflow,
376 TLan_HandleRxEOF, 373 TLan_HandleRxEOF,
@@ -444,7 +441,9 @@ static void __devexit tlan_remove_one( struct pci_dev *pdev)
444 unregister_netdev( dev ); 441 unregister_netdev( dev );
445 442
446 if ( priv->dmaStorage ) { 443 if ( priv->dmaStorage ) {
447 pci_free_consistent(priv->pciDev, priv->dmaSize, priv->dmaStorage, priv->dmaStorageDMA ); 444 pci_free_consistent(priv->pciDev,
445 priv->dmaSize, priv->dmaStorage,
446 priv->dmaStorageDMA );
448 } 447 }
449 448
450#ifdef CONFIG_PCI 449#ifdef CONFIG_PCI
@@ -469,16 +468,6 @@ static int __init tlan_probe(void)
469 468
470 printk(KERN_INFO "%s", tlan_banner); 469 printk(KERN_INFO "%s", tlan_banner);
471 470
472 TLanPadBuffer = (u8 *) pci_alloc_consistent(NULL, TLAN_MIN_FRAME_SIZE, &TLanPadBufferDMA);
473
474 if (TLanPadBuffer == NULL) {
475 printk(KERN_ERR "TLAN: Could not allocate memory for pad buffer.\n");
476 rc = -ENOMEM;
477 goto err_out;
478 }
479
480 memset(TLanPadBuffer, 0, TLAN_MIN_FRAME_SIZE);
481
482 TLAN_DBG(TLAN_DEBUG_PROBE, "Starting PCI Probe....\n"); 471 TLAN_DBG(TLAN_DEBUG_PROBE, "Starting PCI Probe....\n");
483 472
484 /* Use new style PCI probing. Now the kernel will 473 /* Use new style PCI probing. Now the kernel will
@@ -506,8 +495,6 @@ static int __init tlan_probe(void)
506err_out_pci_unreg: 495err_out_pci_unreg:
507 pci_unregister_driver(&tlan_driver); 496 pci_unregister_driver(&tlan_driver);
508err_out_pci_free: 497err_out_pci_free:
509 pci_free_consistent(NULL, TLAN_MIN_FRAME_SIZE, TLanPadBuffer, TLanPadBufferDMA);
510err_out:
511 return rc; 498 return rc;
512} 499}
513 500
@@ -539,7 +526,8 @@ static int __devinit tlan_init_one( struct pci_dev *pdev,
539 **************************************************************/ 526 **************************************************************/
540 527
541static int __devinit TLan_probe1(struct pci_dev *pdev, 528static int __devinit TLan_probe1(struct pci_dev *pdev,
542 long ioaddr, int irq, int rev, const struct pci_device_id *ent ) 529 long ioaddr, int irq, int rev,
530 const struct pci_device_id *ent )
543{ 531{
544 532
545 struct net_device *dev; 533 struct net_device *dev;
@@ -625,8 +613,10 @@ static int __devinit TLan_probe1(struct pci_dev *pdev,
625 /* Kernel parameters */ 613 /* Kernel parameters */
626 if (dev->mem_start) { 614 if (dev->mem_start) {
627 priv->aui = dev->mem_start & 0x01; 615 priv->aui = dev->mem_start & 0x01;
628 priv->duplex = ((dev->mem_start & 0x06) == 0x06) ? 0 : (dev->mem_start & 0x06) >> 1; 616 priv->duplex = ((dev->mem_start & 0x06) == 0x06) ? 0
629 priv->speed = ((dev->mem_start & 0x18) == 0x18) ? 0 : (dev->mem_start & 0x18) >> 3; 617 : (dev->mem_start & 0x06) >> 1;
618 priv->speed = ((dev->mem_start & 0x18) == 0x18) ? 0
619 : (dev->mem_start & 0x18) >> 3;
630 620
631 if (priv->speed == 0x1) { 621 if (priv->speed == 0x1) {
632 priv->speed = TLAN_SPEED_10; 622 priv->speed = TLAN_SPEED_10;
@@ -706,7 +696,8 @@ static void TLan_Eisa_Cleanup(void)
706 dev = TLan_Eisa_Devices; 696 dev = TLan_Eisa_Devices;
707 priv = netdev_priv(dev); 697 priv = netdev_priv(dev);
708 if (priv->dmaStorage) { 698 if (priv->dmaStorage) {
709 pci_free_consistent(priv->pciDev, priv->dmaSize, priv->dmaStorage, priv->dmaStorageDMA ); 699 pci_free_consistent(priv->pciDev, priv->dmaSize,
700 priv->dmaStorage, priv->dmaStorageDMA );
710 } 701 }
711 release_region( dev->base_addr, 0x10); 702 release_region( dev->base_addr, 0x10);
712 unregister_netdev( dev ); 703 unregister_netdev( dev );
@@ -724,8 +715,6 @@ static void __exit tlan_exit(void)
724 if (tlan_have_eisa) 715 if (tlan_have_eisa)
725 TLan_Eisa_Cleanup(); 716 TLan_Eisa_Cleanup();
726 717
727 pci_free_consistent(NULL, TLAN_MIN_FRAME_SIZE, TLanPadBuffer, TLanPadBufferDMA);
728
729} 718}
730 719
731 720
@@ -763,8 +752,10 @@ static void __init TLan_EisaProbe (void)
763 /* Loop through all slots of the EISA bus */ 752 /* Loop through all slots of the EISA bus */
764 for (ioaddr = 0x1000; ioaddr < 0x9000; ioaddr += 0x1000) { 753 for (ioaddr = 0x1000; ioaddr < 0x9000; ioaddr += 0x1000) {
765 754
766 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n", (int) ioaddr + 0xC80, inw(ioaddr + EISA_ID)); 755 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n",
767 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n", (int) ioaddr + 0xC82, inw(ioaddr + EISA_ID2)); 756 (int) ioaddr + 0xC80, inw(ioaddr + EISA_ID));
757 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n",
758 (int) ioaddr + 0xC82, inw(ioaddr + EISA_ID2));
768 759
769 760
770 TLAN_DBG(TLAN_DEBUG_PROBE, "Probing for EISA adapter at IO: 0x%4x : ", 761 TLAN_DBG(TLAN_DEBUG_PROBE, "Probing for EISA adapter at IO: 0x%4x : ",
@@ -874,7 +865,8 @@ static int TLan_Init( struct net_device *dev )
874 dma_size = ( TLAN_NUM_RX_LISTS + TLAN_NUM_TX_LISTS ) 865 dma_size = ( TLAN_NUM_RX_LISTS + TLAN_NUM_TX_LISTS )
875 * ( sizeof(TLanList) ); 866 * ( sizeof(TLanList) );
876 } 867 }
877 priv->dmaStorage = pci_alloc_consistent(priv->pciDev, dma_size, &priv->dmaStorageDMA); 868 priv->dmaStorage = pci_alloc_consistent(priv->pciDev,
869 dma_size, &priv->dmaStorageDMA);
878 priv->dmaSize = dma_size; 870 priv->dmaSize = dma_size;
879 871
880 if ( priv->dmaStorage == NULL ) { 872 if ( priv->dmaStorage == NULL ) {
@@ -883,16 +875,19 @@ static int TLan_Init( struct net_device *dev )
883 return -ENOMEM; 875 return -ENOMEM;
884 } 876 }
885 memset( priv->dmaStorage, 0, dma_size ); 877 memset( priv->dmaStorage, 0, dma_size );
886 priv->rxList = (TLanList *) 878 priv->rxList = (TLanList *) ALIGN((unsigned long)priv->dmaStorage, 8);
887 ( ( ( (u32) priv->dmaStorage ) + 7 ) & 0xFFFFFFF8 ); 879 priv->rxListDMA = ALIGN(priv->dmaStorageDMA, 8);
888 priv->rxListDMA = ( ( ( (u32) priv->dmaStorageDMA ) + 7 ) & 0xFFFFFFF8 );
889 priv->txList = priv->rxList + TLAN_NUM_RX_LISTS; 880 priv->txList = priv->rxList + TLAN_NUM_RX_LISTS;
890 priv->txListDMA = priv->rxListDMA + sizeof(TLanList) * TLAN_NUM_RX_LISTS; 881 priv->txListDMA = priv->rxListDMA + sizeof(TLanList) * TLAN_NUM_RX_LISTS;
882
891 if ( bbuf ) { 883 if ( bbuf ) {
892 priv->rxBuffer = (u8 *) ( priv->txList + TLAN_NUM_TX_LISTS ); 884 priv->rxBuffer = (u8 *) ( priv->txList + TLAN_NUM_TX_LISTS );
893 priv->rxBufferDMA =priv->txListDMA + sizeof(TLanList) * TLAN_NUM_TX_LISTS; 885 priv->rxBufferDMA =priv->txListDMA
894 priv->txBuffer = priv->rxBuffer + ( TLAN_NUM_RX_LISTS * TLAN_MAX_FRAME_SIZE ); 886 + sizeof(TLanList) * TLAN_NUM_TX_LISTS;
895 priv->txBufferDMA = priv->rxBufferDMA + ( TLAN_NUM_RX_LISTS * TLAN_MAX_FRAME_SIZE ); 887 priv->txBuffer = priv->rxBuffer
888 + ( TLAN_NUM_RX_LISTS * TLAN_MAX_FRAME_SIZE );
889 priv->txBufferDMA = priv->rxBufferDMA
890 + ( TLAN_NUM_RX_LISTS * TLAN_MAX_FRAME_SIZE );
896 } 891 }
897 892
898 err = 0; 893 err = 0;
@@ -952,10 +947,12 @@ static int TLan_Open( struct net_device *dev )
952 int err; 947 int err;
953 948
954 priv->tlanRev = TLan_DioRead8( dev->base_addr, TLAN_DEF_REVISION ); 949 priv->tlanRev = TLan_DioRead8( dev->base_addr, TLAN_DEF_REVISION );
955 err = request_irq( dev->irq, TLan_HandleInterrupt, IRQF_SHARED, TLanSignature, dev ); 950 err = request_irq( dev->irq, TLan_HandleInterrupt, IRQF_SHARED,
951 dev->name, dev );
956 952
957 if ( err ) { 953 if ( err ) {
958 printk(KERN_ERR "TLAN: Cannot open %s because IRQ %d is already in use.\n", dev->name, dev->irq ); 954 pr_err("TLAN: Cannot open %s because IRQ %d is already in use.\n",
955 dev->name, dev->irq );
959 return err; 956 return err;
960 } 957 }
961 958
@@ -969,7 +966,8 @@ static int TLan_Open( struct net_device *dev )
969 TLan_ReadAndClearStats( dev, TLAN_IGNORE ); 966 TLan_ReadAndClearStats( dev, TLAN_IGNORE );
970 TLan_ResetAdapter( dev ); 967 TLan_ResetAdapter( dev );
971 968
972 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Opened. TLAN Chip Rev: %x\n", dev->name, priv->tlanRev ); 969 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Opened. TLAN Chip Rev: %x\n",
970 dev->name, priv->tlanRev );
973 971
974 return 0; 972 return 0;
975 973
@@ -1007,14 +1005,16 @@ static int TLan_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1007 1005
1008 1006
1009 case SIOCGMIIREG: /* Read MII PHY register. */ 1007 case SIOCGMIIREG: /* Read MII PHY register. */
1010 TLan_MiiReadReg(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, &data->val_out); 1008 TLan_MiiReadReg(dev, data->phy_id & 0x1f,
1009 data->reg_num & 0x1f, &data->val_out);
1011 return 0; 1010 return 0;
1012 1011
1013 1012
1014 case SIOCSMIIREG: /* Write MII PHY register. */ 1013 case SIOCSMIIREG: /* Write MII PHY register. */
1015 if (!capable(CAP_NET_ADMIN)) 1014 if (!capable(CAP_NET_ADMIN))
1016 return -EPERM; 1015 return -EPERM;
1017 TLan_MiiWriteReg(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); 1016 TLan_MiiWriteReg(dev, data->phy_id & 0x1f,
1017 data->reg_num & 0x1f, data->val_in);
1018 return 0; 1018 return 0;
1019 default: 1019 default:
1020 return -EOPNOTSUPP; 1020 return -EOPNOTSUPP;
@@ -1096,20 +1096,25 @@ static int TLan_StartTx( struct sk_buff *skb, struct net_device *dev )
1096 TLanList *tail_list; 1096 TLanList *tail_list;
1097 dma_addr_t tail_list_phys; 1097 dma_addr_t tail_list_phys;
1098 u8 *tail_buffer; 1098 u8 *tail_buffer;
1099 int pad;
1100 unsigned long flags; 1099 unsigned long flags;
1101 1100
1102 if ( ! priv->phyOnline ) { 1101 if ( ! priv->phyOnline ) {
1103 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s PHY is not ready\n", dev->name ); 1102 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s PHY is not ready\n",
1103 dev->name );
1104 dev_kfree_skb_any(skb); 1104 dev_kfree_skb_any(skb);
1105 return 0; 1105 return 0;
1106 } 1106 }
1107 1107
1108 if (skb_padto(skb, TLAN_MIN_FRAME_SIZE))
1109 return 0;
1110
1108 tail_list = priv->txList + priv->txTail; 1111 tail_list = priv->txList + priv->txTail;
1109 tail_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txTail; 1112 tail_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txTail;
1110 1113
1111 if ( tail_list->cStat != TLAN_CSTAT_UNUSED ) { 1114 if ( tail_list->cStat != TLAN_CSTAT_UNUSED ) {
1112 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s is busy (Head=%d Tail=%d)\n", dev->name, priv->txHead, priv->txTail ); 1115 TLAN_DBG( TLAN_DEBUG_TX,
1116 "TRANSMIT: %s is busy (Head=%d Tail=%d)\n",
1117 dev->name, priv->txHead, priv->txTail );
1113 netif_stop_queue(dev); 1118 netif_stop_queue(dev);
1114 priv->txBusyCount++; 1119 priv->txBusyCount++;
1115 return 1; 1120 return 1;
@@ -1121,37 +1126,34 @@ static int TLan_StartTx( struct sk_buff *skb, struct net_device *dev )
1121 tail_buffer = priv->txBuffer + ( priv->txTail * TLAN_MAX_FRAME_SIZE ); 1126 tail_buffer = priv->txBuffer + ( priv->txTail * TLAN_MAX_FRAME_SIZE );
1122 skb_copy_from_linear_data(skb, tail_buffer, skb->len); 1127 skb_copy_from_linear_data(skb, tail_buffer, skb->len);
1123 } else { 1128 } else {
1124 tail_list->buffer[0].address = pci_map_single(priv->pciDev, skb->data, skb->len, PCI_DMA_TODEVICE); 1129 tail_list->buffer[0].address = pci_map_single(priv->pciDev,
1130 skb->data, skb->len,
1131 PCI_DMA_TODEVICE);
1125 TLan_StoreSKB(tail_list, skb); 1132 TLan_StoreSKB(tail_list, skb);
1126 } 1133 }
1127 1134
1128 pad = TLAN_MIN_FRAME_SIZE - skb->len; 1135 tail_list->frameSize = (u16) skb->len;
1129 1136 tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) skb->len;
1130 if ( pad > 0 ) { 1137 tail_list->buffer[1].count = 0;
1131 tail_list->frameSize = (u16) skb->len + pad; 1138 tail_list->buffer[1].address = 0;
1132 tail_list->buffer[0].count = (u32) skb->len;
1133 tail_list->buffer[1].count = TLAN_LAST_BUFFER | (u32) pad;
1134 tail_list->buffer[1].address = TLanPadBufferDMA;
1135 } else {
1136 tail_list->frameSize = (u16) skb->len;
1137 tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) skb->len;
1138 tail_list->buffer[1].count = 0;
1139 tail_list->buffer[1].address = 0;
1140 }
1141 1139
1142 spin_lock_irqsave(&priv->lock, flags); 1140 spin_lock_irqsave(&priv->lock, flags);
1143 tail_list->cStat = TLAN_CSTAT_READY; 1141 tail_list->cStat = TLAN_CSTAT_READY;
1144 if ( ! priv->txInProgress ) { 1142 if ( ! priv->txInProgress ) {
1145 priv->txInProgress = 1; 1143 priv->txInProgress = 1;
1146 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Starting TX on buffer %d\n", priv->txTail ); 1144 TLAN_DBG( TLAN_DEBUG_TX,
1145 "TRANSMIT: Starting TX on buffer %d\n", priv->txTail );
1147 outl( tail_list_phys, dev->base_addr + TLAN_CH_PARM ); 1146 outl( tail_list_phys, dev->base_addr + TLAN_CH_PARM );
1148 outl( TLAN_HC_GO, dev->base_addr + TLAN_HOST_CMD ); 1147 outl( TLAN_HC_GO, dev->base_addr + TLAN_HOST_CMD );
1149 } else { 1148 } else {
1150 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Adding buffer %d to TX channel\n", priv->txTail ); 1149 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Adding buffer %d to TX channel\n",
1150 priv->txTail );
1151 if ( priv->txTail == 0 ) { 1151 if ( priv->txTail == 0 ) {
1152 ( priv->txList + ( TLAN_NUM_TX_LISTS - 1 ) )->forward = tail_list_phys; 1152 ( priv->txList + ( TLAN_NUM_TX_LISTS - 1 ) )->forward
1153 = tail_list_phys;
1153 } else { 1154 } else {
1154 ( priv->txList + ( priv->txTail - 1 ) )->forward = tail_list_phys; 1155 ( priv->txList + ( priv->txTail - 1 ) )->forward
1156 = tail_list_phys;
1155 } 1157 }
1156 } 1158 }
1157 spin_unlock_irqrestore(&priv->lock, flags); 1159 spin_unlock_irqrestore(&priv->lock, flags);
@@ -1191,33 +1193,31 @@ static int TLan_StartTx( struct sk_buff *skb, struct net_device *dev )
1191 1193
1192static irqreturn_t TLan_HandleInterrupt(int irq, void *dev_id) 1194static irqreturn_t TLan_HandleInterrupt(int irq, void *dev_id)
1193{ 1195{
1194 u32 ack; 1196 struct net_device *dev = dev_id;
1195 struct net_device *dev; 1197 TLanPrivateInfo *priv = netdev_priv(dev);
1196 u32 host_cmd;
1197 u16 host_int; 1198 u16 host_int;
1198 int type; 1199 u16 type;
1199 TLanPrivateInfo *priv;
1200
1201 dev = dev_id;
1202 priv = netdev_priv(dev);
1203 1200
1204 spin_lock(&priv->lock); 1201 spin_lock(&priv->lock);
1205 1202
1206 host_int = inw( dev->base_addr + TLAN_HOST_INT ); 1203 host_int = inw( dev->base_addr + TLAN_HOST_INT );
1207 outw( host_int, dev->base_addr + TLAN_HOST_INT );
1208
1209 type = ( host_int & TLAN_HI_IT_MASK ) >> 2; 1204 type = ( host_int & TLAN_HI_IT_MASK ) >> 2;
1205 if ( type ) {
1206 u32 ack;
1207 u32 host_cmd;
1210 1208
1211 ack = TLanIntVector[type]( dev, host_int ); 1209 outw( host_int, dev->base_addr + TLAN_HOST_INT );
1210 ack = TLanIntVector[type]( dev, host_int );
1212 1211
1213 if ( ack ) { 1212 if ( ack ) {
1214 host_cmd = TLAN_HC_ACK | ack | ( type << 18 ); 1213 host_cmd = TLAN_HC_ACK | ack | ( type << 18 );
1215 outl( host_cmd, dev->base_addr + TLAN_HOST_CMD ); 1214 outl( host_cmd, dev->base_addr + TLAN_HOST_CMD );
1215 }
1216 } 1216 }
1217 1217
1218 spin_unlock(&priv->lock); 1218 spin_unlock(&priv->lock);
1219 1219
1220 return IRQ_HANDLED; 1220 return IRQ_RETVAL(type);
1221} /* TLan_HandleInterrupts */ 1221} /* TLan_HandleInterrupts */
1222 1222
1223 1223
@@ -1286,8 +1286,10 @@ static struct net_device_stats *TLan_GetStats( struct net_device *dev )
1286 /* Should only read stats if open ? */ 1286 /* Should only read stats if open ? */
1287 TLan_ReadAndClearStats( dev, TLAN_RECORD ); 1287 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1288 1288
1289 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: %s EOC count = %d\n", dev->name, priv->rxEocCount ); 1289 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: %s EOC count = %d\n", dev->name,
1290 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s Busy count = %d\n", dev->name, priv->txBusyCount ); 1290 priv->rxEocCount );
1291 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s Busy count = %d\n", dev->name,
1292 priv->txBusyCount );
1291 if ( debug & TLAN_DEBUG_GNRL ) { 1293 if ( debug & TLAN_DEBUG_GNRL ) {
1292 TLan_PrintDio( dev->base_addr ); 1294 TLan_PrintDio( dev->base_addr );
1293 TLan_PhyPrint( dev ); 1295 TLan_PhyPrint( dev );
@@ -1299,7 +1301,7 @@ static struct net_device_stats *TLan_GetStats( struct net_device *dev )
1299 TLan_PrintList( priv->txList + i, "TX", i ); 1301 TLan_PrintList( priv->txList + i, "TX", i );
1300 } 1302 }
1301 1303
1302 return ( &( (TLanPrivateInfo *) netdev_priv(dev) )->stats ); 1304 return &dev->stats;
1303 1305
1304} /* TLan_GetStats */ 1306} /* TLan_GetStats */
1305 1307
@@ -1337,10 +1339,12 @@ static void TLan_SetMulticastList( struct net_device *dev )
1337 1339
1338 if ( dev->flags & IFF_PROMISC ) { 1340 if ( dev->flags & IFF_PROMISC ) {
1339 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD ); 1341 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD );
1340 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, tmp | TLAN_NET_CMD_CAF ); 1342 TLan_DioWrite8( dev->base_addr,
1343 TLAN_NET_CMD, tmp | TLAN_NET_CMD_CAF );
1341 } else { 1344 } else {
1342 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD ); 1345 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD );
1343 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF ); 1346 TLan_DioWrite8( dev->base_addr,
1347 TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF );
1344 if ( dev->flags & IFF_ALLMULTI ) { 1348 if ( dev->flags & IFF_ALLMULTI ) {
1345 for ( i = 0; i < 3; i++ ) 1349 for ( i = 0; i < 3; i++ )
1346 TLan_SetMac( dev, i + 1, NULL ); 1350 TLan_SetMac( dev, i + 1, NULL );
@@ -1349,7 +1353,8 @@ static void TLan_SetMulticastList( struct net_device *dev )
1349 } else { 1353 } else {
1350 for ( i = 0; i < dev->mc_count; i++ ) { 1354 for ( i = 0; i < dev->mc_count; i++ ) {
1351 if ( i < 3 ) { 1355 if ( i < 3 ) {
1352 TLan_SetMac( dev, i + 1, (char *) &dmi->dmi_addr ); 1356 TLan_SetMac( dev, i + 1,
1357 (char *) &dmi->dmi_addr );
1353 } else { 1358 } else {
1354 offset = TLan_HashFunc( (u8 *) &dmi->dmi_addr ); 1359 offset = TLan_HashFunc( (u8 *) &dmi->dmi_addr );
1355 if ( offset < 32 ) 1360 if ( offset < 32 )
@@ -1383,31 +1388,6 @@ static void TLan_SetMulticastList( struct net_device *dev )
1383*****************************************************************************/ 1388*****************************************************************************/
1384 1389
1385 1390
1386 /***************************************************************
1387 * TLan_HandleInvalid
1388 *
1389 * Returns:
1390 * 0
1391 * Parms:
1392 * dev Device assigned the IRQ that was
1393 * raised.
1394 * host_int The contents of the HOST_INT
1395 * port.
1396 *
1397 * This function handles invalid interrupts. This should
1398 * never happen unless some other adapter is trying to use
1399 * the IRQ line assigned to the device.
1400 *
1401 **************************************************************/
1402
1403static u32 TLan_HandleInvalid( struct net_device *dev, u16 host_int )
1404{
1405 /* printk( "TLAN: Invalid interrupt on %s.\n", dev->name ); */
1406 return 0;
1407
1408} /* TLan_HandleInvalid */
1409
1410
1411 1391
1412 1392
1413 /*************************************************************** 1393 /***************************************************************
@@ -1441,14 +1421,16 @@ static u32 TLan_HandleTxEOF( struct net_device *dev, u16 host_int )
1441 u32 ack = 0; 1421 u32 ack = 0;
1442 u16 tmpCStat; 1422 u16 tmpCStat;
1443 1423
1444 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Handling TX EOF (Head=%d Tail=%d)\n", priv->txHead, priv->txTail ); 1424 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Handling TX EOF (Head=%d Tail=%d)\n",
1425 priv->txHead, priv->txTail );
1445 head_list = priv->txList + priv->txHead; 1426 head_list = priv->txList + priv->txHead;
1446 1427
1447 while (((tmpCStat = head_list->cStat ) & TLAN_CSTAT_FRM_CMP) && (ack < 255)) { 1428 while (((tmpCStat = head_list->cStat ) & TLAN_CSTAT_FRM_CMP) && (ack < 255)) {
1448 ack++; 1429 ack++;
1449 if ( ! bbuf ) { 1430 if ( ! bbuf ) {
1450 struct sk_buff *skb = TLan_GetSKB(head_list); 1431 struct sk_buff *skb = TLan_GetSKB(head_list);
1451 pci_unmap_single(priv->pciDev, head_list->buffer[0].address, skb->len, PCI_DMA_TODEVICE); 1432 pci_unmap_single(priv->pciDev, head_list->buffer[0].address,
1433 skb->len, PCI_DMA_TODEVICE);
1452 dev_kfree_skb_any(skb); 1434 dev_kfree_skb_any(skb);
1453 head_list->buffer[8].address = 0; 1435 head_list->buffer[8].address = 0;
1454 head_list->buffer[9].address = 0; 1436 head_list->buffer[9].address = 0;
@@ -1457,7 +1439,7 @@ static u32 TLan_HandleTxEOF( struct net_device *dev, u16 host_int )
1457 if ( tmpCStat & TLAN_CSTAT_EOC ) 1439 if ( tmpCStat & TLAN_CSTAT_EOC )
1458 eoc = 1; 1440 eoc = 1;
1459 1441
1460 priv->stats.tx_bytes += head_list->frameSize; 1442 dev->stats.tx_bytes += head_list->frameSize;
1461 1443
1462 head_list->cStat = TLAN_CSTAT_UNUSED; 1444 head_list->cStat = TLAN_CSTAT_UNUSED;
1463 netif_start_queue(dev); 1445 netif_start_queue(dev);
@@ -1469,7 +1451,9 @@ static u32 TLan_HandleTxEOF( struct net_device *dev, u16 host_int )
1469 printk(KERN_INFO "TLAN: Received interrupt for uncompleted TX frame.\n"); 1451 printk(KERN_INFO "TLAN: Received interrupt for uncompleted TX frame.\n");
1470 1452
1471 if ( eoc ) { 1453 if ( eoc ) {
1472 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Handling TX EOC (Head=%d Tail=%d)\n", priv->txHead, priv->txTail ); 1454 TLAN_DBG( TLAN_DEBUG_TX,
1455 "TRANSMIT: Handling TX EOC (Head=%d Tail=%d)\n",
1456 priv->txHead, priv->txTail );
1473 head_list = priv->txList + priv->txHead; 1457 head_list = priv->txList + priv->txHead;
1474 head_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txHead; 1458 head_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txHead;
1475 if ( ( head_list->cStat & TLAN_CSTAT_READY ) == TLAN_CSTAT_READY ) { 1459 if ( ( head_list->cStat & TLAN_CSTAT_READY ) == TLAN_CSTAT_READY ) {
@@ -1481,7 +1465,8 @@ static u32 TLan_HandleTxEOF( struct net_device *dev, u16 host_int )
1481 } 1465 }
1482 1466
1483 if ( priv->adapter->flags & TLAN_ADAPTER_ACTIVITY_LED ) { 1467 if ( priv->adapter->flags & TLAN_ADAPTER_ACTIVITY_LED ) {
1484 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT ); 1468 TLan_DioWrite8( dev->base_addr,
1469 TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT );
1485 if ( priv->timer.function == NULL ) { 1470 if ( priv->timer.function == NULL ) {
1486 priv->timer.function = &TLan_Timer; 1471 priv->timer.function = &TLan_Timer;
1487 priv->timer.data = (unsigned long) dev; 1472 priv->timer.data = (unsigned long) dev;
@@ -1563,66 +1548,65 @@ static u32 TLan_HandleRxEOF( struct net_device *dev, u16 host_int )
1563 TLanList *head_list; 1548 TLanList *head_list;
1564 struct sk_buff *skb; 1549 struct sk_buff *skb;
1565 TLanList *tail_list; 1550 TLanList *tail_list;
1566 void *t;
1567 u32 frameSize;
1568 u16 tmpCStat; 1551 u16 tmpCStat;
1569 dma_addr_t head_list_phys; 1552 dma_addr_t head_list_phys;
1570 1553
1571 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: Handling RX EOF (Head=%d Tail=%d)\n", priv->rxHead, priv->rxTail ); 1554 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: Handling RX EOF (Head=%d Tail=%d)\n",
1555 priv->rxHead, priv->rxTail );
1572 head_list = priv->rxList + priv->rxHead; 1556 head_list = priv->rxList + priv->rxHead;
1573 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead; 1557 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1574 1558
1575 while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP) && (ack < 255)) { 1559 while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP) && (ack < 255)) {
1576 frameSize = head_list->frameSize; 1560 dma_addr_t frameDma = head_list->buffer[0].address;
1561 u32 frameSize = head_list->frameSize;
1577 ack++; 1562 ack++;
1578 if (tmpCStat & TLAN_CSTAT_EOC) 1563 if (tmpCStat & TLAN_CSTAT_EOC)
1579 eoc = 1; 1564 eoc = 1;
1580 1565
1581 if (bbuf) { 1566 if (bbuf) {
1582 skb = dev_alloc_skb(frameSize + 7); 1567 skb = netdev_alloc_skb(dev, frameSize + 7);
1583 if (skb == NULL) 1568 if ( !skb )
1584 printk(KERN_INFO "TLAN: Couldn't allocate memory for received data.\n"); 1569 goto drop_and_reuse;
1585 else { 1570
1586 head_buffer = priv->rxBuffer + (priv->rxHead * TLAN_MAX_FRAME_SIZE); 1571 head_buffer = priv->rxBuffer
1587 skb_reserve(skb, 2); 1572 + (priv->rxHead * TLAN_MAX_FRAME_SIZE);
1588 t = (void *) skb_put(skb, frameSize); 1573 skb_reserve(skb, 2);
1589 1574 pci_dma_sync_single_for_cpu(priv->pciDev,
1590 priv->stats.rx_bytes += head_list->frameSize; 1575 frameDma, frameSize,
1591 1576 PCI_DMA_FROMDEVICE);
1592 memcpy( t, head_buffer, frameSize ); 1577 skb_copy_from_linear_data(skb, head_buffer, frameSize);
1593 skb->protocol = eth_type_trans( skb, dev ); 1578 skb_put(skb, frameSize);
1594 netif_rx( skb ); 1579 dev->stats.rx_bytes += frameSize;
1595 } 1580
1581 skb->protocol = eth_type_trans( skb, dev );
1582 netif_rx( skb );
1596 } else { 1583 } else {
1597 struct sk_buff *new_skb; 1584 struct sk_buff *new_skb;
1598 1585
1599 /* 1586 new_skb = netdev_alloc_skb(dev, TLAN_MAX_FRAME_SIZE + 7 );
1600 * I changed the algorithm here. What we now do 1587 if ( !new_skb )
1601 * is allocate the new frame. If this fails we 1588 goto drop_and_reuse;
1602 * simply recycle the frame.
1603 */
1604 1589
1605 new_skb = dev_alloc_skb( TLAN_MAX_FRAME_SIZE + 7 ); 1590 skb = TLan_GetSKB(head_list);
1591 pci_unmap_single(priv->pciDev, frameDma,
1592 TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
1593 skb_put( skb, frameSize );
1606 1594
1607 if ( new_skb != NULL ) { 1595 dev->stats.rx_bytes += frameSize;
1608 skb = TLan_GetSKB(head_list);
1609 pci_unmap_single(priv->pciDev, head_list->buffer[0].address, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
1610 skb_trim( skb, frameSize );
1611 1596
1612 priv->stats.rx_bytes += frameSize; 1597 skb->protocol = eth_type_trans( skb, dev );
1598 netif_rx( skb );
1613 1599
1614 skb->protocol = eth_type_trans( skb, dev ); 1600 skb_reserve( new_skb, NET_IP_ALIGN );
1615 netif_rx( skb ); 1601 head_list->buffer[0].address = pci_map_single(priv->pciDev,
1602 new_skb->data,
1603 TLAN_MAX_FRAME_SIZE,
1604 PCI_DMA_FROMDEVICE);
1616 1605
1617 skb_reserve( new_skb, 2 ); 1606 TLan_StoreSKB(head_list, new_skb);
1618 t = (void *) skb_put( new_skb, TLAN_MAX_FRAME_SIZE );
1619 head_list->buffer[0].address = pci_map_single(priv->pciDev, new_skb->data, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
1620 head_list->buffer[8].address = (u32) t;
1621 TLan_StoreSKB(head_list, new_skb);
1622 } else
1623 printk(KERN_WARNING "TLAN: Couldn't allocate memory for received data.\n" );
1624 }
1625 1607
1608 }
1609drop_and_reuse:
1626 head_list->forward = 0; 1610 head_list->forward = 0;
1627 head_list->cStat = 0; 1611 head_list->cStat = 0;
1628 tail_list = priv->rxList + priv->rxTail; 1612 tail_list = priv->rxList + priv->rxTail;
@@ -1638,10 +1622,10 @@ static u32 TLan_HandleRxEOF( struct net_device *dev, u16 host_int )
1638 printk(KERN_INFO "TLAN: Received interrupt for uncompleted RX frame.\n"); 1622 printk(KERN_INFO "TLAN: Received interrupt for uncompleted RX frame.\n");
1639 1623
1640 1624
1641
1642
1643 if ( eoc ) { 1625 if ( eoc ) {
1644 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: Handling RX EOC (Head=%d Tail=%d)\n", priv->rxHead, priv->rxTail ); 1626 TLAN_DBG( TLAN_DEBUG_RX,
1627 "RECEIVE: Handling RX EOC (Head=%d Tail=%d)\n",
1628 priv->rxHead, priv->rxTail );
1645 head_list = priv->rxList + priv->rxHead; 1629 head_list = priv->rxList + priv->rxHead;
1646 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead; 1630 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1647 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM ); 1631 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM );
@@ -1650,7 +1634,8 @@ static u32 TLan_HandleRxEOF( struct net_device *dev, u16 host_int )
1650 } 1634 }
1651 1635
1652 if ( priv->adapter->flags & TLAN_ADAPTER_ACTIVITY_LED ) { 1636 if ( priv->adapter->flags & TLAN_ADAPTER_ACTIVITY_LED ) {
1653 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT ); 1637 TLan_DioWrite8( dev->base_addr,
1638 TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT );
1654 if ( priv->timer.function == NULL ) { 1639 if ( priv->timer.function == NULL ) {
1655 priv->timer.function = &TLan_Timer; 1640 priv->timer.function = &TLan_Timer;
1656 priv->timer.data = (unsigned long) dev; 1641 priv->timer.data = (unsigned long) dev;
@@ -1728,7 +1713,9 @@ static u32 TLan_HandleTxEOC( struct net_device *dev, u16 host_int )
1728 1713
1729 host_int = 0; 1714 host_int = 0;
1730 if ( priv->tlanRev < 0x30 ) { 1715 if ( priv->tlanRev < 0x30 ) {
1731 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Handling TX EOC (Head=%d Tail=%d) -- IRQ\n", priv->txHead, priv->txTail ); 1716 TLAN_DBG( TLAN_DEBUG_TX,
1717 "TRANSMIT: Handling TX EOC (Head=%d Tail=%d) -- IRQ\n",
1718 priv->txHead, priv->txTail );
1732 head_list = priv->txList + priv->txHead; 1719 head_list = priv->txList + priv->txHead;
1733 head_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txHead; 1720 head_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txHead;
1734 if ( ( head_list->cStat & TLAN_CSTAT_READY ) == TLAN_CSTAT_READY ) { 1721 if ( ( head_list->cStat & TLAN_CSTAT_READY ) == TLAN_CSTAT_READY ) {
@@ -1796,15 +1783,18 @@ static u32 TLan_HandleStatusCheck( struct net_device *dev, u16 host_int )
1796 net_sts = TLan_DioRead8( dev->base_addr, TLAN_NET_STS ); 1783 net_sts = TLan_DioRead8( dev->base_addr, TLAN_NET_STS );
1797 if ( net_sts ) { 1784 if ( net_sts ) {
1798 TLan_DioWrite8( dev->base_addr, TLAN_NET_STS, net_sts ); 1785 TLan_DioWrite8( dev->base_addr, TLAN_NET_STS, net_sts );
1799 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Net_Sts = %x\n", dev->name, (unsigned) net_sts ); 1786 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Net_Sts = %x\n",
1787 dev->name, (unsigned) net_sts );
1800 } 1788 }
1801 if ( ( net_sts & TLAN_NET_STS_MIRQ ) && ( priv->phyNum == 0 ) ) { 1789 if ( ( net_sts & TLAN_NET_STS_MIRQ ) && ( priv->phyNum == 0 ) ) {
1802 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_STS, &tlphy_sts ); 1790 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_STS, &tlphy_sts );
1803 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl ); 1791 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl );
1804 if ( ! ( tlphy_sts & TLAN_TS_POLOK ) && ! ( tlphy_ctl & TLAN_TC_SWAPOL ) ) { 1792 if ( ! ( tlphy_sts & TLAN_TS_POLOK ) &&
1793 ! ( tlphy_ctl & TLAN_TC_SWAPOL ) ) {
1805 tlphy_ctl |= TLAN_TC_SWAPOL; 1794 tlphy_ctl |= TLAN_TC_SWAPOL;
1806 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl); 1795 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
1807 } else if ( ( tlphy_sts & TLAN_TS_POLOK ) && ( tlphy_ctl & TLAN_TC_SWAPOL ) ) { 1796 } else if ( ( tlphy_sts & TLAN_TS_POLOK )
1797 && ( tlphy_ctl & TLAN_TC_SWAPOL ) ) {
1808 tlphy_ctl &= ~TLAN_TC_SWAPOL; 1798 tlphy_ctl &= ~TLAN_TC_SWAPOL;
1809 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl); 1799 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
1810 } 1800 }
@@ -1849,7 +1839,9 @@ static u32 TLan_HandleRxEOC( struct net_device *dev, u16 host_int )
1849 u32 ack = 1; 1839 u32 ack = 1;
1850 1840
1851 if ( priv->tlanRev < 0x30 ) { 1841 if ( priv->tlanRev < 0x30 ) {
1852 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: Handling RX EOC (Head=%d Tail=%d) -- IRQ\n", priv->rxHead, priv->rxTail ); 1842 TLAN_DBG( TLAN_DEBUG_RX,
1843 "RECEIVE: Handling RX EOC (Head=%d Tail=%d) -- IRQ\n",
1844 priv->rxHead, priv->rxTail );
1853 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead; 1845 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1854 outl( head_list_phys, dev->base_addr + TLAN_CH_PARM ); 1846 outl( head_list_phys, dev->base_addr + TLAN_CH_PARM );
1855 ack |= TLAN_HC_GO | TLAN_HC_RT; 1847 ack |= TLAN_HC_GO | TLAN_HC_RT;
@@ -1940,10 +1932,12 @@ static void TLan_Timer( unsigned long data )
1940 if ( priv->timer.function == NULL ) { 1932 if ( priv->timer.function == NULL ) {
1941 elapsed = jiffies - priv->timerSetAt; 1933 elapsed = jiffies - priv->timerSetAt;
1942 if ( elapsed >= TLAN_TIMER_ACT_DELAY ) { 1934 if ( elapsed >= TLAN_TIMER_ACT_DELAY ) {
1943 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK ); 1935 TLan_DioWrite8( dev->base_addr,
1936 TLAN_LED_REG, TLAN_LED_LINK );
1944 } else { 1937 } else {
1945 priv->timer.function = &TLan_Timer; 1938 priv->timer.function = &TLan_Timer;
1946 priv->timer.expires = priv->timerSetAt + TLAN_TIMER_ACT_DELAY; 1939 priv->timer.expires = priv->timerSetAt
1940 + TLAN_TIMER_ACT_DELAY;
1947 spin_unlock_irqrestore(&priv->lock, flags); 1941 spin_unlock_irqrestore(&priv->lock, flags);
1948 add_timer( &priv->timer ); 1942 add_timer( &priv->timer );
1949 break; 1943 break;
@@ -1998,7 +1992,8 @@ static void TLan_ResetLists( struct net_device *dev )
1998 list = priv->txList + i; 1992 list = priv->txList + i;
1999 list->cStat = TLAN_CSTAT_UNUSED; 1993 list->cStat = TLAN_CSTAT_UNUSED;
2000 if ( bbuf ) { 1994 if ( bbuf ) {
2001 list->buffer[0].address = priv->txBufferDMA + ( i * TLAN_MAX_FRAME_SIZE ); 1995 list->buffer[0].address = priv->txBufferDMA
1996 + ( i * TLAN_MAX_FRAME_SIZE );
2002 } else { 1997 } else {
2003 list->buffer[0].address = 0; 1998 list->buffer[0].address = 0;
2004 } 1999 }
@@ -2017,28 +2012,32 @@ static void TLan_ResetLists( struct net_device *dev )
2017 list->frameSize = TLAN_MAX_FRAME_SIZE; 2012 list->frameSize = TLAN_MAX_FRAME_SIZE;
2018 list->buffer[0].count = TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER; 2013 list->buffer[0].count = TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
2019 if ( bbuf ) { 2014 if ( bbuf ) {
2020 list->buffer[0].address = priv->rxBufferDMA + ( i * TLAN_MAX_FRAME_SIZE ); 2015 list->buffer[0].address = priv->rxBufferDMA
2016 + ( i * TLAN_MAX_FRAME_SIZE );
2021 } else { 2017 } else {
2022 skb = dev_alloc_skb( TLAN_MAX_FRAME_SIZE + 7 ); 2018 skb = netdev_alloc_skb(dev, TLAN_MAX_FRAME_SIZE + 7 );
2023 if ( skb == NULL ) { 2019 if ( !skb ) {
2024 printk( "TLAN: Couldn't allocate memory for received data.\n" ); 2020 pr_err("TLAN: out of memory for received data.\n" );
2025 /* If this ever happened it would be a problem */ 2021 break;
2026 } else {
2027 skb->dev = dev;
2028 skb_reserve( skb, 2 );
2029 t = (void *) skb_put( skb, TLAN_MAX_FRAME_SIZE );
2030 } 2022 }
2031 list->buffer[0].address = pci_map_single(priv->pciDev, t, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE); 2023
2032 list->buffer[8].address = (u32) t; 2024 skb_reserve( skb, NET_IP_ALIGN );
2025 list->buffer[0].address = pci_map_single(priv->pciDev, t,
2026 TLAN_MAX_FRAME_SIZE,
2027 PCI_DMA_FROMDEVICE);
2033 TLan_StoreSKB(list, skb); 2028 TLan_StoreSKB(list, skb);
2034 } 2029 }
2035 list->buffer[1].count = 0; 2030 list->buffer[1].count = 0;
2036 list->buffer[1].address = 0; 2031 list->buffer[1].address = 0;
2037 if ( i < TLAN_NUM_RX_LISTS - 1 ) 2032 list->forward = list_phys + sizeof(TLanList);
2038 list->forward = list_phys + sizeof(TLanList); 2033 }
2039 else 2034
2040 list->forward = 0; 2035 /* in case ran out of memory early, clear bits */
2036 while (i < TLAN_NUM_RX_LISTS) {
2037 TLan_StoreSKB(priv->rxList + i, NULL);
2038 ++i;
2041 } 2039 }
2040 list->forward = 0;
2042 2041
2043} /* TLan_ResetLists */ 2042} /* TLan_ResetLists */
2044 2043
@@ -2055,7 +2054,9 @@ static void TLan_FreeLists( struct net_device *dev )
2055 list = priv->txList + i; 2054 list = priv->txList + i;
2056 skb = TLan_GetSKB(list); 2055 skb = TLan_GetSKB(list);
2057 if ( skb ) { 2056 if ( skb ) {
2058 pci_unmap_single(priv->pciDev, list->buffer[0].address, skb->len, PCI_DMA_TODEVICE); 2057 pci_unmap_single(priv->pciDev,
2058 list->buffer[0].address, skb->len,
2059 PCI_DMA_TODEVICE);
2059 dev_kfree_skb_any( skb ); 2060 dev_kfree_skb_any( skb );
2060 list->buffer[8].address = 0; 2061 list->buffer[8].address = 0;
2061 list->buffer[9].address = 0; 2062 list->buffer[9].address = 0;
@@ -2066,7 +2067,10 @@ static void TLan_FreeLists( struct net_device *dev )
2066 list = priv->rxList + i; 2067 list = priv->rxList + i;
2067 skb = TLan_GetSKB(list); 2068 skb = TLan_GetSKB(list);
2068 if ( skb ) { 2069 if ( skb ) {
2069 pci_unmap_single(priv->pciDev, list->buffer[0].address, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE); 2070 pci_unmap_single(priv->pciDev,
2071 list->buffer[0].address,
2072 TLAN_MAX_FRAME_SIZE,
2073 PCI_DMA_FROMDEVICE);
2070 dev_kfree_skb_any( skb ); 2074 dev_kfree_skb_any( skb );
2071 list->buffer[8].address = 0; 2075 list->buffer[8].address = 0;
2072 list->buffer[9].address = 0; 2076 list->buffer[9].address = 0;
@@ -2097,7 +2101,8 @@ static void TLan_PrintDio( u16 io_base )
2097 u32 data0, data1; 2101 u32 data0, data1;
2098 int i; 2102 int i;
2099 2103
2100 printk( "TLAN: Contents of internal registers for io base 0x%04hx.\n", io_base ); 2104 printk( "TLAN: Contents of internal registers for io base 0x%04hx.\n",
2105 io_base );
2101 printk( "TLAN: Off. +0 +4\n" ); 2106 printk( "TLAN: Off. +0 +4\n" );
2102 for ( i = 0; i < 0x4C; i+= 8 ) { 2107 for ( i = 0; i < 0x4C; i+= 8 ) {
2103 data0 = TLan_DioRead32( io_base, i ); 2108 data0 = TLan_DioRead32( io_base, i );
@@ -2131,13 +2136,14 @@ static void TLan_PrintList( TLanList *list, char *type, int num)
2131{ 2136{
2132 int i; 2137 int i;
2133 2138
2134 printk( "TLAN: %s List %d at 0x%08x\n", type, num, (u32) list ); 2139 printk( "TLAN: %s List %d at %p\n", type, num, list );
2135 printk( "TLAN: Forward = 0x%08x\n", list->forward ); 2140 printk( "TLAN: Forward = 0x%08x\n", list->forward );
2136 printk( "TLAN: CSTAT = 0x%04hx\n", list->cStat ); 2141 printk( "TLAN: CSTAT = 0x%04hx\n", list->cStat );
2137 printk( "TLAN: Frame Size = 0x%04hx\n", list->frameSize ); 2142 printk( "TLAN: Frame Size = 0x%04hx\n", list->frameSize );
2138 /* for ( i = 0; i < 10; i++ ) { */ 2143 /* for ( i = 0; i < 10; i++ ) { */
2139 for ( i = 0; i < 2; i++ ) { 2144 for ( i = 0; i < 2; i++ ) {
2140 printk( "TLAN: Buffer[%d].count, addr = 0x%08x, 0x%08x\n", i, list->buffer[i].count, list->buffer[i].address ); 2145 printk( "TLAN: Buffer[%d].count, addr = 0x%08x, 0x%08x\n",
2146 i, list->buffer[i].count, list->buffer[i].address );
2141 } 2147 }
2142 2148
2143} /* TLan_PrintList */ 2149} /* TLan_PrintList */
@@ -2165,7 +2171,6 @@ static void TLan_PrintList( TLanList *list, char *type, int num)
2165 2171
2166static void TLan_ReadAndClearStats( struct net_device *dev, int record ) 2172static void TLan_ReadAndClearStats( struct net_device *dev, int record )
2167{ 2173{
2168 TLanPrivateInfo *priv = netdev_priv(dev);
2169 u32 tx_good, tx_under; 2174 u32 tx_good, tx_under;
2170 u32 rx_good, rx_over; 2175 u32 rx_good, rx_over;
2171 u32 def_tx, crc, code; 2176 u32 def_tx, crc, code;
@@ -2202,18 +2207,18 @@ static void TLan_ReadAndClearStats( struct net_device *dev, int record )
2202 loss = inb( dev->base_addr + TLAN_DIO_DATA + 2 ); 2207 loss = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
2203 2208
2204 if ( record ) { 2209 if ( record ) {
2205 priv->stats.rx_packets += rx_good; 2210 dev->stats.rx_packets += rx_good;
2206 priv->stats.rx_errors += rx_over + crc + code; 2211 dev->stats.rx_errors += rx_over + crc + code;
2207 priv->stats.tx_packets += tx_good; 2212 dev->stats.tx_packets += tx_good;
2208 priv->stats.tx_errors += tx_under + loss; 2213 dev->stats.tx_errors += tx_under + loss;
2209 priv->stats.collisions += multi_col + single_col + excess_col + late_col; 2214 dev->stats.collisions += multi_col + single_col + excess_col + late_col;
2210 2215
2211 priv->stats.rx_over_errors += rx_over; 2216 dev->stats.rx_over_errors += rx_over;
2212 priv->stats.rx_crc_errors += crc; 2217 dev->stats.rx_crc_errors += crc;
2213 priv->stats.rx_frame_errors += code; 2218 dev->stats.rx_frame_errors += code;
2214 2219
2215 priv->stats.tx_aborted_errors += tx_under; 2220 dev->stats.tx_aborted_errors += tx_under;
2216 priv->stats.tx_carrier_errors += loss; 2221 dev->stats.tx_carrier_errors += loss;
2217 } 2222 }
2218 2223
2219} /* TLan_ReadAndClearStats */ 2224} /* TLan_ReadAndClearStats */
@@ -2354,14 +2359,16 @@ TLan_FinishReset( struct net_device *dev )
2354 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &tlphy_id1 ); 2359 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &tlphy_id1 );
2355 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &tlphy_id2 ); 2360 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &tlphy_id2 );
2356 2361
2357 if ( ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) || ( priv->aui ) ) { 2362 if ( ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) ||
2363 ( priv->aui ) ) {
2358 status = MII_GS_LINK; 2364 status = MII_GS_LINK;
2359 printk( "TLAN: %s: Link forced.\n", dev->name ); 2365 printk( "TLAN: %s: Link forced.\n", dev->name );
2360 } else { 2366 } else {
2361 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status ); 2367 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2362 udelay( 1000 ); 2368 udelay( 1000 );
2363 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status ); 2369 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2364 if ( (status & MII_GS_LINK) && /* We only support link info on Nat.Sem. PHY's */ 2370 if ( (status & MII_GS_LINK) &&
2371 /* We only support link info on Nat.Sem. PHY's */
2365 (tlphy_id1 == NAT_SEM_ID1) && 2372 (tlphy_id1 == NAT_SEM_ID1) &&
2366 (tlphy_id2 == NAT_SEM_ID2) ) { 2373 (tlphy_id2 == NAT_SEM_ID2) ) {
2367 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &partner ); 2374 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &partner );
@@ -2370,12 +2377,12 @@ TLan_FinishReset( struct net_device *dev )
2370 printk( "TLAN: %s: Link active with ", dev->name ); 2377 printk( "TLAN: %s: Link active with ", dev->name );
2371 if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) { 2378 if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
2372 printk( "forced 10%sMbps %s-Duplex\n", 2379 printk( "forced 10%sMbps %s-Duplex\n",
2373 tlphy_par & TLAN_PHY_SPEED_100 ? "" : "0", 2380 tlphy_par & TLAN_PHY_SPEED_100 ? "" : "0",
2374 tlphy_par & TLAN_PHY_DUPLEX_FULL ? "Full" : "Half"); 2381 tlphy_par & TLAN_PHY_DUPLEX_FULL ? "Full" : "Half");
2375 } else { 2382 } else {
2376 printk( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n", 2383 printk( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
2377 tlphy_par & TLAN_PHY_SPEED_100 ? "" : "0", 2384 tlphy_par & TLAN_PHY_SPEED_100 ? "" : "0",
2378 tlphy_par & TLAN_PHY_DUPLEX_FULL ? "Full" : "Half"); 2385 tlphy_par & TLAN_PHY_DUPLEX_FULL ? "Full" : "Half");
2379 printk("TLAN: Partner capability: "); 2386 printk("TLAN: Partner capability: ");
2380 for (i = 5; i <= 10; i++) 2387 for (i = 5; i <= 10; i++)
2381 if (partner & (1<<i)) 2388 if (partner & (1<<i))
@@ -2416,7 +2423,8 @@ TLan_FinishReset( struct net_device *dev )
2416 outl( TLAN_HC_GO | TLAN_HC_RT, dev->base_addr + TLAN_HOST_CMD ); 2423 outl( TLAN_HC_GO | TLAN_HC_RT, dev->base_addr + TLAN_HOST_CMD );
2417 netif_carrier_on(dev); 2424 netif_carrier_on(dev);
2418 } else { 2425 } else {
2419 printk( "TLAN: %s: Link inactive, will retry in 10 secs...\n", dev->name ); 2426 printk( "TLAN: %s: Link inactive, will retry in 10 secs...\n",
2427 dev->name );
2420 TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_FINISH_RESET ); 2428 TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_FINISH_RESET );
2421 return; 2429 return;
2422 } 2430 }
@@ -2456,10 +2464,12 @@ static void TLan_SetMac( struct net_device *dev, int areg, char *mac )
2456 2464
2457 if ( mac != NULL ) { 2465 if ( mac != NULL ) {
2458 for ( i = 0; i < 6; i++ ) 2466 for ( i = 0; i < 6; i++ )
2459 TLan_DioWrite8( dev->base_addr, TLAN_AREG_0 + areg + i, mac[i] ); 2467 TLan_DioWrite8( dev->base_addr,
2468 TLAN_AREG_0 + areg + i, mac[i] );
2460 } else { 2469 } else {
2461 for ( i = 0; i < 6; i++ ) 2470 for ( i = 0; i < 6; i++ )
2462 TLan_DioWrite8( dev->base_addr, TLAN_AREG_0 + areg + i, 0 ); 2471 TLan_DioWrite8( dev->base_addr,
2472 TLAN_AREG_0 + areg + i, 0 );
2463 } 2473 }
2464 2474
2465} /* TLan_SetMac */ 2475} /* TLan_SetMac */
@@ -2565,9 +2575,13 @@ static void TLan_PhyDetect( struct net_device *dev )
2565 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &control ); 2575 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &control );
2566 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &hi ); 2576 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &hi );
2567 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &lo ); 2577 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &lo );
2568 if ( ( control != 0xFFFF ) || ( hi != 0xFFFF ) || ( lo != 0xFFFF ) ) { 2578 if ( ( control != 0xFFFF ) ||
2569 TLAN_DBG( TLAN_DEBUG_GNRL, "PHY found at %02x %04x %04x %04x\n", phy, control, hi, lo ); 2579 ( hi != 0xFFFF ) || ( lo != 0xFFFF ) ) {
2570 if ( ( priv->phy[1] == TLAN_PHY_NONE ) && ( phy != TLAN_PHY_MAX_ADDR ) ) { 2580 TLAN_DBG( TLAN_DEBUG_GNRL,
2581 "PHY found at %02x %04x %04x %04x\n",
2582 phy, control, hi, lo );
2583 if ( ( priv->phy[1] == TLAN_PHY_NONE ) &&
2584 ( phy != TLAN_PHY_MAX_ADDR ) ) {
2571 priv->phy[1] = phy; 2585 priv->phy[1] = phy;
2572 } 2586 }
2573 } 2587 }
@@ -2595,7 +2609,9 @@ static void TLan_PhyPowerDown( struct net_device *dev )
2595 value = MII_GC_PDOWN | MII_GC_LOOPBK | MII_GC_ISOLATE; 2609 value = MII_GC_PDOWN | MII_GC_LOOPBK | MII_GC_ISOLATE;
2596 TLan_MiiSync( dev->base_addr ); 2610 TLan_MiiSync( dev->base_addr );
2597 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value ); 2611 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value );
2598 if ( ( priv->phyNum == 0 ) && ( priv->phy[1] != TLAN_PHY_NONE ) && ( ! ( priv->adapter->flags & TLAN_ADAPTER_USE_INTERN_10 ) ) ) { 2612 if ( ( priv->phyNum == 0 ) &&
2613 ( priv->phy[1] != TLAN_PHY_NONE ) &&
2614 ( ! ( priv->adapter->flags & TLAN_ADAPTER_USE_INTERN_10 ) ) ) {
2599 TLan_MiiSync( dev->base_addr ); 2615 TLan_MiiSync( dev->base_addr );
2600 TLan_MiiWriteReg( dev, priv->phy[1], MII_GEN_CTL, value ); 2616 TLan_MiiWriteReg( dev, priv->phy[1], MII_GEN_CTL, value );
2601 } 2617 }
@@ -2768,10 +2784,10 @@ static void TLan_PhyFinishAutoNeg( struct net_device *dev )
2768 * more time. Perhaps we should fail after a while. 2784 * more time. Perhaps we should fail after a while.
2769 */ 2785 */
2770 if (!priv->neg_be_verbose++) { 2786 if (!priv->neg_be_verbose++) {
2771 printk(KERN_INFO "TLAN: Giving autonegotiation more time.\n"); 2787 pr_info("TLAN: Giving autonegotiation more time.\n");
2772 printk(KERN_INFO "TLAN: Please check that your adapter has\n"); 2788 pr_info("TLAN: Please check that your adapter has\n");
2773 printk(KERN_INFO "TLAN: been properly connected to a HUB or Switch.\n"); 2789 pr_info("TLAN: been properly connected to a HUB or Switch.\n");
2774 printk(KERN_INFO "TLAN: Trying to establish link in the background...\n"); 2790 pr_info("TLAN: Trying to establish link in the background...\n");
2775 } 2791 }
2776 TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN ); 2792 TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN );
2777 return; 2793 return;
@@ -2787,7 +2803,9 @@ static void TLan_PhyFinishAutoNeg( struct net_device *dev )
2787 priv->tlanFullDuplex = TRUE; 2803 priv->tlanFullDuplex = TRUE;
2788 } 2804 }
2789 2805
2790 if ( ( ! ( mode & 0x0180 ) ) && ( priv->adapter->flags & TLAN_ADAPTER_USE_INTERN_10 ) && ( priv->phyNum != 0 ) ) { 2806 if ( ( ! ( mode & 0x0180 ) ) &&
2807 ( priv->adapter->flags & TLAN_ADAPTER_USE_INTERN_10 ) &&
2808 ( priv->phyNum != 0 ) ) {
2791 priv->phyNum = 0; 2809 priv->phyNum = 0;
2792 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN; 2810 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
2793 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data ); 2811 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data );
@@ -2796,12 +2814,14 @@ static void TLan_PhyFinishAutoNeg( struct net_device *dev )
2796 } 2814 }
2797 2815
2798 if ( priv->phyNum == 0 ) { 2816 if ( priv->phyNum == 0 ) {
2799 if ( ( priv->duplex == TLAN_DUPLEX_FULL ) || ( an_adv & an_lpa & 0x0040 ) ) { 2817 if ( ( priv->duplex == TLAN_DUPLEX_FULL ) ||
2800 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB | MII_GC_DUPLEX ); 2818 ( an_adv & an_lpa & 0x0040 ) ) {
2801 printk( "TLAN: Starting internal PHY with FULL-DUPLEX\n" ); 2819 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL,
2820 MII_GC_AUTOENB | MII_GC_DUPLEX );
2821 pr_info("TLAN: Starting internal PHY with FULL-DUPLEX\n" );
2802 } else { 2822 } else {
2803 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB ); 2823 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB );
2804 printk( "TLAN: Starting internal PHY with HALF-DUPLEX\n" ); 2824 pr_info( "TLAN: Starting internal PHY with HALF-DUPLEX\n" );
2805 } 2825 }
2806 } 2826 }
2807 2827
@@ -3209,7 +3229,8 @@ static int TLan_EeSendByte( u16 io_base, u8 data, int stop )
3209 TLan_SetBit( TLAN_NET_SIO_ETXEN, sio ); 3229 TLan_SetBit( TLAN_NET_SIO_ETXEN, sio );
3210 3230
3211 if ( ( ! err ) && stop ) { 3231 if ( ( ! err ) && stop ) {
3212 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio ); /* STOP, raise data while clock is high */ 3232 /* STOP, raise data while clock is high */
3233 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3213 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio ); 3234 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3214 TLan_SetBit( TLAN_NET_SIO_EDATA, sio ); 3235 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3215 } 3236 }
@@ -3272,7 +3293,8 @@ static void TLan_EeReceiveByte( u16 io_base, u8 *data, int stop )
3272 TLan_SetBit( TLAN_NET_SIO_EDATA, sio ); /* No ack = 1 (?) */ 3293 TLan_SetBit( TLAN_NET_SIO_EDATA, sio ); /* No ack = 1 (?) */
3273 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio ); 3294 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3274 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio ); 3295 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3275 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio ); /* STOP, raise data while clock is high */ 3296 /* STOP, raise data while clock is high */
3297 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3276 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio ); 3298 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3277 TLan_SetBit( TLAN_NET_SIO_EDATA, sio ); 3299 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3278 } 3300 }
diff --git a/drivers/net/tlan.h b/drivers/net/tlan.h
index 41ce0b665937..4b82f283e985 100644
--- a/drivers/net/tlan.h
+++ b/drivers/net/tlan.h
@@ -13,8 +13,6 @@
13 * This software may be used and distributed according to the terms 13 * This software may be used and distributed according to the terms
14 * of the GNU General Public License, incorporated herein by reference. 14 * of the GNU General Public License, incorporated herein by reference.
15 * 15 *
16 ** This file is best viewed/edited with tabstop=4, colums>=132
17 *
18 * 16 *
19 * Dec 10, 1999 Torben Mathiasen <torben.mathiasen@compaq.com> 17 * Dec 10, 1999 Torben Mathiasen <torben.mathiasen@compaq.com>
20 * New Maintainer 18 * New Maintainer
@@ -45,7 +43,9 @@
45#define TLAN_IGNORE 0 43#define TLAN_IGNORE 0
46#define TLAN_RECORD 1 44#define TLAN_RECORD 1
47 45
48#define TLAN_DBG(lvl, format, args...) if (debug&lvl) printk(KERN_DEBUG "TLAN: " format, ##args ); 46#define TLAN_DBG(lvl, format, args...) \
47 do { if (debug&lvl) printk(KERN_DEBUG "TLAN: " format, ##args ); } while(0)
48
49#define TLAN_DEBUG_GNRL 0x0001 49#define TLAN_DEBUG_GNRL 0x0001
50#define TLAN_DEBUG_TX 0x0002 50#define TLAN_DEBUG_TX 0x0002
51#define TLAN_DEBUG_RX 0x0004 51#define TLAN_DEBUG_RX 0x0004
@@ -194,7 +194,6 @@ typedef struct tlan_private_tag {
194 u32 timerSetAt; 194 u32 timerSetAt;
195 u32 timerType; 195 u32 timerType;
196 struct timer_list timer; 196 struct timer_list timer;
197 struct net_device_stats stats;
198 struct board *adapter; 197 struct board *adapter;
199 u32 adapterRev; 198 u32 adapterRev;
200 u32 aui; 199 u32 aui;
@@ -205,7 +204,6 @@ typedef struct tlan_private_tag {
205 u32 speed; 204 u32 speed;
206 u8 tlanRev; 205 u8 tlanRev;
207 u8 tlanFullDuplex; 206 u8 tlanFullDuplex;
208 char devName[8];
209 spinlock_t lock; 207 spinlock_t lock;
210 u8 link; 208 u8 link;
211 u8 is_eisa; 209 u8 is_eisa;
@@ -517,12 +515,18 @@ static inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)
517 * xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) ) 515 * xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) )
518 * #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) ) 516 * #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) )
519 * 517 *
520 * hash = XOR8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), DA(a,36), DA(a,42) ); 518 * hash = XOR8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24),
521 * hash |= XOR8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), DA(a,37), DA(a,43) ) << 1; 519 * DA(a,30), DA(a,36), DA(a,42) );
522 * hash |= XOR8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), DA(a,38), DA(a,44) ) << 2; 520 * hash |= XOR8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25),
523 * hash |= XOR8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), DA(a,39), DA(a,45) ) << 3; 521 * DA(a,31), DA(a,37), DA(a,43) ) << 1;
524 * hash |= XOR8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), DA(a,40), DA(a,46) ) << 4; 522 * hash |= XOR8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26),
525 * hash |= XOR8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), DA(a,41), DA(a,47) ) << 5; 523 * DA(a,32), DA(a,38), DA(a,44) ) << 2;
524 * hash |= XOR8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27),
525 * DA(a,33), DA(a,39), DA(a,45) ) << 3;
526 * hash |= XOR8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28),
527 * DA(a,34), DA(a,40), DA(a,46) ) << 4;
528 * hash |= XOR8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29),
529 * DA(a,35), DA(a,41), DA(a,47) ) << 5;
526 * 530 *
527 */ 531 */
528static inline u32 TLan_HashFunc( const u8 *a ) 532static inline u32 TLan_HashFunc( const u8 *a )
diff --git a/drivers/net/tokenring/3c359.c b/drivers/net/tokenring/3c359.c
index 45208a0e69a0..7766cde0d63d 100644
--- a/drivers/net/tokenring/3c359.c
+++ b/drivers/net/tokenring/3c359.c
@@ -132,7 +132,6 @@ static void xl_dn_comp(struct net_device *dev);
132static int xl_close(struct net_device *dev); 132static int xl_close(struct net_device *dev);
133static void xl_set_rx_mode(struct net_device *dev); 133static void xl_set_rx_mode(struct net_device *dev);
134static irqreturn_t xl_interrupt(int irq, void *dev_id); 134static irqreturn_t xl_interrupt(int irq, void *dev_id);
135static struct net_device_stats * xl_get_stats(struct net_device *dev);
136static int xl_set_mac_address(struct net_device *dev, void *addr) ; 135static int xl_set_mac_address(struct net_device *dev, void *addr) ;
137static void xl_arb_cmd(struct net_device *dev); 136static void xl_arb_cmd(struct net_device *dev);
138static void xl_asb_cmd(struct net_device *dev) ; 137static void xl_asb_cmd(struct net_device *dev) ;
@@ -343,7 +342,6 @@ static int __devinit xl_probe(struct pci_dev *pdev,
343 dev->stop=&xl_close; 342 dev->stop=&xl_close;
344 dev->do_ioctl=NULL; 343 dev->do_ioctl=NULL;
345 dev->set_multicast_list=&xl_set_rx_mode; 344 dev->set_multicast_list=&xl_set_rx_mode;
346 dev->get_stats=&xl_get_stats ;
347 dev->set_mac_address=&xl_set_mac_address ; 345 dev->set_mac_address=&xl_set_mac_address ;
348 SET_NETDEV_DEV(dev, &pdev->dev); 346 SET_NETDEV_DEV(dev, &pdev->dev);
349 347
@@ -921,7 +919,7 @@ static void xl_rx(struct net_device *dev)
921 adv_rx_ring(dev) ; 919 adv_rx_ring(dev) ;
922 920
923 adv_rx_ring(dev) ; /* One more time just for luck :) */ 921 adv_rx_ring(dev) ; /* One more time just for luck :) */
924 xl_priv->xl_stats.rx_dropped++ ; 922 dev->stats.rx_dropped++ ;
925 923
926 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 924 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
927 return ; 925 return ;
@@ -957,7 +955,7 @@ static void xl_rx(struct net_device *dev)
957 if (skb==NULL) { /* Still need to fix the rx ring */ 955 if (skb==NULL) { /* Still need to fix the rx ring */
958 printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ; 956 printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ;
959 adv_rx_ring(dev) ; 957 adv_rx_ring(dev) ;
960 xl_priv->xl_stats.rx_dropped++ ; 958 dev->stats.rx_dropped++ ;
961 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 959 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
962 return ; 960 return ;
963 } 961 }
@@ -971,8 +969,8 @@ static void xl_rx(struct net_device *dev)
971 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE)); 969 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
972 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG; 970 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
973 adv_rx_ring(dev) ; 971 adv_rx_ring(dev) ;
974 xl_priv->xl_stats.rx_packets++ ; 972 dev->stats.rx_packets++ ;
975 xl_priv->xl_stats.rx_bytes += frame_length ; 973 dev->stats.rx_bytes += frame_length ;
976 974
977 netif_rx(skb2) ; 975 netif_rx(skb2) ;
978 } /* if multiple buffers */ 976 } /* if multiple buffers */
@@ -1182,8 +1180,8 @@ static int xl_xmit(struct sk_buff *skb, struct net_device *dev)
1182 txd->buffer = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE)); 1180 txd->buffer = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE));
1183 txd->buffer_length = cpu_to_le32(skb->len) | TXDNFRAGLAST; 1181 txd->buffer_length = cpu_to_le32(skb->len) | TXDNFRAGLAST;
1184 xl_priv->tx_ring_skb[tx_head] = skb ; 1182 xl_priv->tx_ring_skb[tx_head] = skb ;
1185 xl_priv->xl_stats.tx_packets++ ; 1183 dev->stats.tx_packets++ ;
1186 xl_priv->xl_stats.tx_bytes += skb->len ; 1184 dev->stats.tx_bytes += skb->len ;
1187 1185
1188 /* 1186 /*
1189 * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1 1187 * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1
@@ -1463,12 +1461,6 @@ static void xl_srb_bh(struct net_device *dev)
1463 return ; 1461 return ;
1464} 1462}
1465 1463
1466static struct net_device_stats * xl_get_stats(struct net_device *dev)
1467{
1468 struct xl_private *xl_priv = netdev_priv(dev);
1469 return (struct net_device_stats *) &xl_priv->xl_stats;
1470}
1471
1472static int xl_set_mac_address (struct net_device *dev, void *addr) 1464static int xl_set_mac_address (struct net_device *dev, void *addr)
1473{ 1465{
1474 struct sockaddr *saddr = addr ; 1466 struct sockaddr *saddr = addr ;
diff --git a/drivers/net/tokenring/3c359.h b/drivers/net/tokenring/3c359.h
index 74cf8e1a181b..66b1ff603234 100644
--- a/drivers/net/tokenring/3c359.h
+++ b/drivers/net/tokenring/3c359.h
@@ -273,8 +273,6 @@ struct xl_private {
273 struct wait_queue *srb_wait; 273 struct wait_queue *srb_wait;
274 volatile int asb_queued; 274 volatile int asb_queued;
275 275
276 struct net_device_stats xl_stats ;
277
278 u16 mac_buffer ; 276 u16 mac_buffer ;
279 u16 xl_lan_status ; 277 u16 xl_lan_status ;
280 u8 xl_ring_speed ; 278 u8 xl_ring_speed ;
diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c
index 6017d5267d08..43fde99b24ac 100644
--- a/drivers/net/tsi108_eth.c
+++ b/drivers/net/tsi108_eth.c
@@ -803,7 +803,8 @@ static int tsi108_refill_rx(struct net_device *dev, int budget)
803 int rx = data->rxhead; 803 int rx = data->rxhead;
804 struct sk_buff *skb; 804 struct sk_buff *skb;
805 805
806 data->rxskbs[rx] = skb = dev_alloc_skb(TSI108_RXBUF_SIZE + 2); 806 data->rxskbs[rx] = skb = netdev_alloc_skb(dev,
807 TSI108_RXBUF_SIZE + 2);
807 if (!skb) 808 if (!skb)
808 break; 809 break;
809 810
@@ -1352,8 +1353,9 @@ static int tsi108_open(struct net_device *dev)
1352 data->rxhead = 0; 1353 data->rxhead = 0;
1353 1354
1354 for (i = 0; i < TSI108_RXRING_LEN; i++) { 1355 for (i = 0; i < TSI108_RXRING_LEN; i++) {
1355 struct sk_buff *skb = dev_alloc_skb(TSI108_RXBUF_SIZE + NET_IP_ALIGN); 1356 struct sk_buff *skb;
1356 1357
1358 skb = netdev_alloc_skb(dev, TSI108_RXBUF_SIZE + NET_IP_ALIGN);
1357 if (!skb) { 1359 if (!skb) {
1358 /* Bah. No memory for now, but maybe we'll get 1360 /* Bah. No memory for now, but maybe we'll get
1359 * some more later. 1361 * some more later.
@@ -1435,7 +1437,6 @@ static int tsi108_close(struct net_device *dev)
1435 dev_kfree_skb(skb); 1437 dev_kfree_skb(skb);
1436 } 1438 }
1437 1439
1438 synchronize_irq(data->irq_num);
1439 free_irq(data->irq_num, dev); 1440 free_irq(data->irq_num, dev);
1440 1441
1441 /* Discard the RX ring. */ 1442 /* Discard the RX ring. */
@@ -1526,7 +1527,7 @@ static int tsi108_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1526 struct tsi108_prv_data *data = netdev_priv(dev); 1527 struct tsi108_prv_data *data = netdev_priv(dev);
1527 unsigned long flags; 1528 unsigned long flags;
1528 int rc; 1529 int rc;
1529 1530
1530 spin_lock_irqsave(&data->txlock, flags); 1531 spin_lock_irqsave(&data->txlock, flags);
1531 rc = mii_ethtool_gset(&data->mii_if, cmd); 1532 rc = mii_ethtool_gset(&data->mii_if, cmd);
1532 spin_unlock_irqrestore(&data->txlock, flags); 1533 spin_unlock_irqrestore(&data->txlock, flags);
@@ -1543,7 +1544,7 @@ static int tsi108_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1543 spin_lock_irqsave(&data->txlock, flags); 1544 spin_lock_irqsave(&data->txlock, flags);
1544 rc = mii_ethtool_sset(&data->mii_if, cmd); 1545 rc = mii_ethtool_sset(&data->mii_if, cmd);
1545 spin_unlock_irqrestore(&data->txlock, flags); 1546 spin_unlock_irqrestore(&data->txlock, flags);
1546 1547
1547 return rc; 1548 return rc;
1548} 1549}
1549 1550
diff --git a/drivers/net/tulip/21142.c b/drivers/net/tulip/21142.c
index 6c400ccd38b4..1210fb3748a7 100644
--- a/drivers/net/tulip/21142.c
+++ b/drivers/net/tulip/21142.c
@@ -1,7 +1,6 @@
1/* 1/*
2 drivers/net/tulip/21142.c 2 drivers/net/tulip/21142.c
3 3
4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 4 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 5 Written/copyright 1994-2001 by Donald Becker.
7 6
@@ -9,9 +8,8 @@
9 of the GNU General Public License, incorporated herein by reference. 8 of the GNU General Public License, incorporated herein by reference.
10 9
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} 10 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project 11 for more information on this driver.
13 Web page at http://sourceforge.net/projects/tulip/ 12 Please submit bugs to http://bugzilla.kernel.org/ .
14
15*/ 13*/
16 14
17#include <linux/delay.h> 15#include <linux/delay.h>
diff --git a/drivers/net/tulip/de2104x.c b/drivers/net/tulip/de2104x.c
index 1b5edd646a8c..9281d06d5aaa 100644
--- a/drivers/net/tulip/de2104x.c
+++ b/drivers/net/tulip/de2104x.c
@@ -124,8 +124,6 @@ MODULE_PARM_DESC (rx_copybreak, "de2104x Breakpoint at which Rx packets are copi
124/* Time in jiffies before concluding the transmitter is hung. */ 124/* Time in jiffies before concluding the transmitter is hung. */
125#define TX_TIMEOUT (6*HZ) 125#define TX_TIMEOUT (6*HZ)
126 126
127#define DE_UNALIGNED_16(a) (u16)(get_unaligned((u16 *)(a)))
128
129/* This is a mysterious value that can be written to CSR11 in the 21040 (only) 127/* This is a mysterious value that can be written to CSR11 in the 21040 (only)
130 to support a pre-NWay full-duplex signaling mechanism using short frames. 128 to support a pre-NWay full-duplex signaling mechanism using short frames.
131 No one knows what it should be, but if left at its default value some 129 No one knows what it should be, but if left at its default value some
@@ -1811,7 +1809,7 @@ static void __devinit de21041_get_srom_info (struct de_private *de)
1811 goto bad_srom; 1809 goto bad_srom;
1812 1810
1813 /* get default media type */ 1811 /* get default media type */
1814 switch (DE_UNALIGNED_16(&il->default_media)) { 1812 switch (get_unaligned(&il->default_media)) {
1815 case 0x0001: de->media_type = DE_MEDIA_BNC; break; 1813 case 0x0001: de->media_type = DE_MEDIA_BNC; break;
1816 case 0x0002: de->media_type = DE_MEDIA_AUI; break; 1814 case 0x0002: de->media_type = DE_MEDIA_AUI; break;
1817 case 0x0204: de->media_type = DE_MEDIA_TP_FD; break; 1815 case 0x0204: de->media_type = DE_MEDIA_TP_FD; break;
@@ -1875,9 +1873,9 @@ static void __devinit de21041_get_srom_info (struct de_private *de)
1875 bufp += sizeof (ib->opts); 1873 bufp += sizeof (ib->opts);
1876 1874
1877 if (ib->opts & MediaCustomCSRs) { 1875 if (ib->opts & MediaCustomCSRs) {
1878 de->media[idx].csr13 = DE_UNALIGNED_16(&ib->csr13); 1876 de->media[idx].csr13 = get_unaligned(&ib->csr13);
1879 de->media[idx].csr14 = DE_UNALIGNED_16(&ib->csr14); 1877 de->media[idx].csr14 = get_unaligned(&ib->csr14);
1880 de->media[idx].csr15 = DE_UNALIGNED_16(&ib->csr15); 1878 de->media[idx].csr15 = get_unaligned(&ib->csr15);
1881 bufp += sizeof(ib->csr13) + sizeof(ib->csr14) + 1879 bufp += sizeof(ib->csr13) + sizeof(ib->csr14) +
1882 sizeof(ib->csr15); 1880 sizeof(ib->csr15);
1883 1881
diff --git a/drivers/net/tulip/eeprom.c b/drivers/net/tulip/eeprom.c
index da2206f6021d..0dcced1263b9 100644
--- a/drivers/net/tulip/eeprom.c
+++ b/drivers/net/tulip/eeprom.c
@@ -1,7 +1,6 @@
1/* 1/*
2 drivers/net/tulip/eeprom.c 2 drivers/net/tulip/eeprom.c
3 3
4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 4 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 5 Written/copyright 1994-2001 by Donald Becker.
7 6
@@ -9,9 +8,8 @@
9 of the GNU General Public License, incorporated herein by reference. 8 of the GNU General Public License, incorporated herein by reference.
10 9
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} 10 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project 11 for more information on this driver.
13 Web page at http://sourceforge.net/projects/tulip/ 12 Please submit bug reports to http://bugzilla.kernel.org/.
14
15*/ 13*/
16 14
17#include <linux/pci.h> 15#include <linux/pci.h>
diff --git a/drivers/net/tulip/interrupt.c b/drivers/net/tulip/interrupt.c
index 6284afd14bbb..c6bad987d63e 100644
--- a/drivers/net/tulip/interrupt.c
+++ b/drivers/net/tulip/interrupt.c
@@ -1,7 +1,6 @@
1/* 1/*
2 drivers/net/tulip/interrupt.c 2 drivers/net/tulip/interrupt.c
3 3
4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 4 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 5 Written/copyright 1994-2001 by Donald Becker.
7 6
@@ -9,8 +8,8 @@
9 of the GNU General Public License, incorporated herein by reference. 8 of the GNU General Public License, incorporated herein by reference.
10 9
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} 10 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project 11 for more information on this driver.
13 Web page at http://sourceforge.net/projects/tulip/ 12 Please submit bugs to http://bugzilla.kernel.org/ .
14 13
15*/ 14*/
16 15
diff --git a/drivers/net/tulip/media.c b/drivers/net/tulip/media.c
index b56256636543..91cf9c863910 100644
--- a/drivers/net/tulip/media.c
+++ b/drivers/net/tulip/media.c
@@ -1,7 +1,6 @@
1/* 1/*
2 drivers/net/tulip/media.c 2 drivers/net/tulip/media.c
3 3
4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 4 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 5 Written/copyright 1994-2001 by Donald Becker.
7 6
@@ -9,9 +8,9 @@
9 of the GNU General Public License, incorporated herein by reference. 8 of the GNU General Public License, incorporated herein by reference.
10 9
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} 10 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project 11 for more information on this driver.
13 Web page at http://sourceforge.net/projects/tulip/
14 12
13 Please submit bugs to http://bugzilla.kernel.org/ .
15*/ 14*/
16 15
17#include <linux/kernel.h> 16#include <linux/kernel.h>
diff --git a/drivers/net/tulip/pnic.c b/drivers/net/tulip/pnic.c
index be82a2effee3..d3253ed09dfc 100644
--- a/drivers/net/tulip/pnic.c
+++ b/drivers/net/tulip/pnic.c
@@ -1,7 +1,6 @@
1/* 1/*
2 drivers/net/tulip/pnic.c 2 drivers/net/tulip/pnic.c
3 3
4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 4 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 5 Written/copyright 1994-2001 by Donald Becker.
7 6
@@ -9,9 +8,9 @@
9 of the GNU General Public License, incorporated herein by reference. 8 of the GNU General Public License, incorporated herein by reference.
10 9
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} 10 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project 11 for more information on this driver.
13 Web page at http://sourceforge.net/projects/tulip/
14 12
13 Please submit bugs to http://bugzilla.kernel.org/ .
15*/ 14*/
16 15
17#include <linux/kernel.h> 16#include <linux/kernel.h>
diff --git a/drivers/net/tulip/pnic2.c b/drivers/net/tulip/pnic2.c
index 4e4a879c3fa5..f49579128fb5 100644
--- a/drivers/net/tulip/pnic2.c
+++ b/drivers/net/tulip/pnic2.c
@@ -1,7 +1,6 @@
1/* 1/*
2 drivers/net/tulip/pnic2.c 2 drivers/net/tulip/pnic2.c
3 3
4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 4 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 5 Written/copyright 1994-2001 by Donald Becker.
7 Modified to hep support PNIC_II by Kevin B. Hendricks 6 Modified to hep support PNIC_II by Kevin B. Hendricks
@@ -10,9 +9,9 @@
10 of the GNU General Public License, incorporated herein by reference. 9 of the GNU General Public License, incorporated herein by reference.
11 10
12 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} 11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
13 for more information on this driver, or visit the project 12 for more information on this driver.
14 Web page at http://sourceforge.net/projects/tulip/
15 13
14 Please submit bugs to http://bugzilla.kernel.org/ .
16*/ 15*/
17 16
18 17
diff --git a/drivers/net/tulip/timer.c b/drivers/net/tulip/timer.c
index d2c1f42109b0..a0e084223082 100644
--- a/drivers/net/tulip/timer.c
+++ b/drivers/net/tulip/timer.c
@@ -1,7 +1,6 @@
1/* 1/*
2 drivers/net/tulip/timer.c 2 drivers/net/tulip/timer.c
3 3
4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 4 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 5 Written/copyright 1994-2001 by Donald Becker.
7 6
@@ -9,11 +8,12 @@
9 of the GNU General Public License, incorporated herein by reference. 8 of the GNU General Public License, incorporated herein by reference.
10 9
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} 10 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project 11 for more information on this driver.
13 Web page at http://sourceforge.net/projects/tulip/
14 12
13 Please submit bugs to http://bugzilla.kernel.org/ .
15*/ 14*/
16 15
16
17#include "tulip.h" 17#include "tulip.h"
18 18
19 19
diff --git a/drivers/net/tulip/tulip.h b/drivers/net/tulip/tulip.h
index 92c68a22f16b..19abbc36b60a 100644
--- a/drivers/net/tulip/tulip.h
+++ b/drivers/net/tulip/tulip.h
@@ -8,9 +8,9 @@
8 of the GNU General Public License, incorporated herein by reference. 8 of the GNU General Public License, incorporated herein by reference.
9 9
10 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} 10 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
11 for more information on this driver, or visit the project 11 for more information on this driver.
12 Web page at http://sourceforge.net/projects/tulip/
13 12
13 Please submit bugs to http://bugzilla.kernel.org/ .
14*/ 14*/
15 15
16#ifndef __NET_TULIP_H__ 16#ifndef __NET_TULIP_H__
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
index af8d2c436efd..cafa89e60167 100644
--- a/drivers/net/tulip/tulip_core.c
+++ b/drivers/net/tulip/tulip_core.c
@@ -1,7 +1,5 @@
1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */ 1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
2 2
3/*
4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team 3 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker. 4 Written/copyright 1994-2001 by Donald Becker.
7 5
@@ -9,9 +7,9 @@
9 of the GNU General Public License, incorporated herein by reference. 7 of the GNU General Public License, incorporated herein by reference.
10 8
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} 9 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project 10 for more information on this driver.
13 Web page at http://sourceforge.net/projects/tulip/
14 11
12 Please submit bugs to http://bugzilla.kernel.org/ .
15*/ 13*/
16 14
17 15
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index eba1271b9735..a82b32b40131 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -18,15 +18,11 @@
18/* 18/*
19 * Changes: 19 * Changes:
20 * 20 *
21 * Brian Braunstein <linuxkernel@bristyle.com> 2007/03/23
22 * Fixed hw address handling. Now net_device.dev_addr is kept consistent
23 * with tun.dev_addr when the address is set by this module.
24 *
25 * Mike Kershaw <dragorn@kismetwireless.net> 2005/08/14 21 * Mike Kershaw <dragorn@kismetwireless.net> 2005/08/14
26 * Add TUNSETLINK ioctl to set the link encapsulation 22 * Add TUNSETLINK ioctl to set the link encapsulation
27 * 23 *
28 * Mark Smith <markzzzsmith@yahoo.com.au> 24 * Mark Smith <markzzzsmith@yahoo.com.au>
29 * Use random_ether_addr() for tap MAC address. 25 * Use random_ether_addr() for tap MAC address.
30 * 26 *
31 * Harald Roelle <harald.roelle@ifi.lmu.de> 2004/04/20 27 * Harald Roelle <harald.roelle@ifi.lmu.de> 2004/04/20
32 * Fixes in packet dropping, queue length setting and queue wakeup. 28 * Fixes in packet dropping, queue length setting and queue wakeup.
@@ -64,6 +60,7 @@
64#include <linux/if_tun.h> 60#include <linux/if_tun.h>
65#include <linux/crc32.h> 61#include <linux/crc32.h>
66#include <linux/nsproxy.h> 62#include <linux/nsproxy.h>
63#include <linux/virtio_net.h>
67#include <net/net_namespace.h> 64#include <net/net_namespace.h>
68#include <net/netns/generic.h> 65#include <net/netns/generic.h>
69 66
@@ -83,9 +80,16 @@ static int debug;
83#define DBG1( a... ) 80#define DBG1( a... )
84#endif 81#endif
85 82
83#define FLT_EXACT_COUNT 8
84struct tap_filter {
85 unsigned int count; /* Number of addrs. Zero means disabled */
86 u32 mask[2]; /* Mask of the hashed addrs */
87 unsigned char addr[FLT_EXACT_COUNT][ETH_ALEN];
88};
89
86struct tun_struct { 90struct tun_struct {
87 struct list_head list; 91 struct list_head list;
88 unsigned long flags; 92 unsigned int flags;
89 int attached; 93 int attached;
90 uid_t owner; 94 uid_t owner;
91 gid_t group; 95 gid_t group;
@@ -94,19 +98,119 @@ struct tun_struct {
94 struct sk_buff_head readq; 98 struct sk_buff_head readq;
95 99
96 struct net_device *dev; 100 struct net_device *dev;
101 struct fasync_struct *fasync;
97 102
98 struct fasync_struct *fasync; 103 struct tap_filter txflt;
99
100 unsigned long if_flags;
101 u8 dev_addr[ETH_ALEN];
102 u32 chr_filter[2];
103 u32 net_filter[2];
104 104
105#ifdef TUN_DEBUG 105#ifdef TUN_DEBUG
106 int debug; 106 int debug;
107#endif 107#endif
108}; 108};
109 109
110/* TAP filterting */
111static void addr_hash_set(u32 *mask, const u8 *addr)
112{
113 int n = ether_crc(ETH_ALEN, addr) >> 26;
114 mask[n >> 5] |= (1 << (n & 31));
115}
116
117static unsigned int addr_hash_test(const u32 *mask, const u8 *addr)
118{
119 int n = ether_crc(ETH_ALEN, addr) >> 26;
120 return mask[n >> 5] & (1 << (n & 31));
121}
122
123static int update_filter(struct tap_filter *filter, void __user *arg)
124{
125 struct { u8 u[ETH_ALEN]; } *addr;
126 struct tun_filter uf;
127 int err, alen, n, nexact;
128
129 if (copy_from_user(&uf, arg, sizeof(uf)))
130 return -EFAULT;
131
132 if (!uf.count) {
133 /* Disabled */
134 filter->count = 0;
135 return 0;
136 }
137
138 alen = ETH_ALEN * uf.count;
139 addr = kmalloc(alen, GFP_KERNEL);
140 if (!addr)
141 return -ENOMEM;
142
143 if (copy_from_user(addr, arg + sizeof(uf), alen)) {
144 err = -EFAULT;
145 goto done;
146 }
147
148 /* The filter is updated without holding any locks. Which is
149 * perfectly safe. We disable it first and in the worst
150 * case we'll accept a few undesired packets. */
151 filter->count = 0;
152 wmb();
153
154 /* Use first set of addresses as an exact filter */
155 for (n = 0; n < uf.count && n < FLT_EXACT_COUNT; n++)
156 memcpy(filter->addr[n], addr[n].u, ETH_ALEN);
157
158 nexact = n;
159
160 /* The rest is hashed */
161 memset(filter->mask, 0, sizeof(filter->mask));
162 for (; n < uf.count; n++)
163 addr_hash_set(filter->mask, addr[n].u);
164
165 /* For ALLMULTI just set the mask to all ones.
166 * This overrides the mask populated above. */
167 if ((uf.flags & TUN_FLT_ALLMULTI))
168 memset(filter->mask, ~0, sizeof(filter->mask));
169
170 /* Now enable the filter */
171 wmb();
172 filter->count = nexact;
173
174 /* Return the number of exact filters */
175 err = nexact;
176
177done:
178 kfree(addr);
179 return err;
180}
181
182/* Returns: 0 - drop, !=0 - accept */
183static int run_filter(struct tap_filter *filter, const struct sk_buff *skb)
184{
185 /* Cannot use eth_hdr(skb) here because skb_mac_hdr() is incorrect
186 * at this point. */
187 struct ethhdr *eh = (struct ethhdr *) skb->data;
188 int i;
189
190 /* Exact match */
191 for (i = 0; i < filter->count; i++)
192 if (!compare_ether_addr(eh->h_dest, filter->addr[i]))
193 return 1;
194
195 /* Inexact match (multicast only) */
196 if (is_multicast_ether_addr(eh->h_dest))
197 return addr_hash_test(filter->mask, eh->h_dest);
198
199 return 0;
200}
201
202/*
203 * Checks whether the packet is accepted or not.
204 * Returns: 0 - drop, !=0 - accept
205 */
206static int check_filter(struct tap_filter *filter, const struct sk_buff *skb)
207{
208 if (!filter->count)
209 return 1;
210
211 return run_filter(filter, skb);
212}
213
110/* Network device part of the driver */ 214/* Network device part of the driver */
111 215
112static unsigned int tun_net_id; 216static unsigned int tun_net_id;
@@ -141,7 +245,12 @@ static int tun_net_xmit(struct sk_buff *skb, struct net_device *dev)
141 if (!tun->attached) 245 if (!tun->attached)
142 goto drop; 246 goto drop;
143 247
144 /* Packet dropping */ 248 /* Drop if the filter does not like it.
249 * This is a noop if the filter is disabled.
250 * Filter can be enabled only for the TAP devices. */
251 if (!check_filter(&tun->txflt, skb))
252 goto drop;
253
145 if (skb_queue_len(&tun->readq) >= dev->tx_queue_len) { 254 if (skb_queue_len(&tun->readq) >= dev->tx_queue_len) {
146 if (!(tun->flags & TUN_ONE_QUEUE)) { 255 if (!(tun->flags & TUN_ONE_QUEUE)) {
147 /* Normal queueing mode. */ 256 /* Normal queueing mode. */
@@ -158,7 +267,7 @@ static int tun_net_xmit(struct sk_buff *skb, struct net_device *dev)
158 } 267 }
159 } 268 }
160 269
161 /* Queue packet */ 270 /* Enqueue packet */
162 skb_queue_tail(&tun->readq, skb); 271 skb_queue_tail(&tun->readq, skb);
163 dev->trans_start = jiffies; 272 dev->trans_start = jiffies;
164 273
@@ -174,41 +283,14 @@ drop:
174 return 0; 283 return 0;
175} 284}
176 285
177/** Add the specified Ethernet address to this multicast filter. */ 286static void tun_net_mclist(struct net_device *dev)
178static void
179add_multi(u32* filter, const u8* addr)
180{ 287{
181 int bit_nr = ether_crc(ETH_ALEN, addr) >> 26; 288 /*
182 filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 289 * This callback is supposed to deal with mc filter in
183} 290 * _rx_ path and has nothing to do with the _tx_ path.
184 291 * In rx path we always accept everything userspace gives us.
185/** Remove the specified Ethernet addres from this multicast filter. */ 292 */
186static void 293 return;
187del_multi(u32* filter, const u8* addr)
188{
189 int bit_nr = ether_crc(ETH_ALEN, addr) >> 26;
190 filter[bit_nr >> 5] &= ~(1 << (bit_nr & 31));
191}
192
193/** Update the list of multicast groups to which the network device belongs.
194 * This list is used to filter packets being sent from the character device to
195 * the network device. */
196static void
197tun_net_mclist(struct net_device *dev)
198{
199 struct tun_struct *tun = netdev_priv(dev);
200 const struct dev_mc_list *mclist;
201 int i;
202 DECLARE_MAC_BUF(mac);
203 DBG(KERN_DEBUG "%s: tun_net_mclist: mc_count %d\n",
204 dev->name, dev->mc_count);
205 memset(tun->chr_filter, 0, sizeof tun->chr_filter);
206 for (i = 0, mclist = dev->mc_list; i < dev->mc_count && mclist != NULL;
207 i++, mclist = mclist->next) {
208 add_multi(tun->net_filter, mclist->dmi_addr);
209 DBG(KERN_DEBUG "%s: tun_net_mclist: %s\n",
210 dev->name, print_mac(mac, mclist->dmi_addr));
211 }
212} 294}
213 295
214#define MIN_MTU 68 296#define MIN_MTU 68
@@ -244,13 +326,11 @@ static void tun_net_init(struct net_device *dev)
244 326
245 case TUN_TAP_DEV: 327 case TUN_TAP_DEV:
246 /* Ethernet TAP Device */ 328 /* Ethernet TAP Device */
247 dev->set_multicast_list = tun_net_mclist;
248
249 ether_setup(dev); 329 ether_setup(dev);
250 dev->change_mtu = tun_net_change_mtu; 330 dev->change_mtu = tun_net_change_mtu;
331 dev->set_multicast_list = tun_net_mclist;
251 332
252 /* random address already created for us by tun_set_iff, use it */ 333 random_ether_addr(dev->dev_addr);
253 memcpy(dev->dev_addr, tun->dev_addr, min(sizeof(tun->dev_addr), sizeof(dev->dev_addr)) );
254 334
255 dev->tx_queue_len = TUN_READQ_SIZE; /* We prefer our own queue length */ 335 dev->tx_queue_len = TUN_READQ_SIZE; /* We prefer our own queue length */
256 break; 336 break;
@@ -284,6 +364,7 @@ static __inline__ ssize_t tun_get_user(struct tun_struct *tun, struct iovec *iv,
284 struct tun_pi pi = { 0, __constant_htons(ETH_P_IP) }; 364 struct tun_pi pi = { 0, __constant_htons(ETH_P_IP) };
285 struct sk_buff *skb; 365 struct sk_buff *skb;
286 size_t len = count, align = 0; 366 size_t len = count, align = 0;
367 struct virtio_net_hdr gso = { 0 };
287 368
288 if (!(tun->flags & TUN_NO_PI)) { 369 if (!(tun->flags & TUN_NO_PI)) {
289 if ((len -= sizeof(pi)) > count) 370 if ((len -= sizeof(pi)) > count)
@@ -293,6 +374,17 @@ static __inline__ ssize_t tun_get_user(struct tun_struct *tun, struct iovec *iv,
293 return -EFAULT; 374 return -EFAULT;
294 } 375 }
295 376
377 if (tun->flags & TUN_VNET_HDR) {
378 if ((len -= sizeof(gso)) > count)
379 return -EINVAL;
380
381 if (memcpy_fromiovec((void *)&gso, iv, sizeof(gso)))
382 return -EFAULT;
383
384 if (gso.hdr_len > len)
385 return -EINVAL;
386 }
387
296 if ((tun->flags & TUN_TYPE_MASK) == TUN_TAP_DEV) { 388 if ((tun->flags & TUN_TYPE_MASK) == TUN_TAP_DEV) {
297 align = NET_IP_ALIGN; 389 align = NET_IP_ALIGN;
298 if (unlikely(len < ETH_HLEN)) 390 if (unlikely(len < ETH_HLEN))
@@ -312,6 +404,16 @@ static __inline__ ssize_t tun_get_user(struct tun_struct *tun, struct iovec *iv,
312 return -EFAULT; 404 return -EFAULT;
313 } 405 }
314 406
407 if (gso.flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
408 if (!skb_partial_csum_set(skb, gso.csum_start,
409 gso.csum_offset)) {
410 tun->dev->stats.rx_frame_errors++;
411 kfree_skb(skb);
412 return -EINVAL;
413 }
414 } else if (tun->flags & TUN_NOCHECKSUM)
415 skb->ip_summed = CHECKSUM_UNNECESSARY;
416
315 switch (tun->flags & TUN_TYPE_MASK) { 417 switch (tun->flags & TUN_TYPE_MASK) {
316 case TUN_TUN_DEV: 418 case TUN_TUN_DEV:
317 if (tun->flags & TUN_NO_PI) { 419 if (tun->flags & TUN_NO_PI) {
@@ -338,8 +440,35 @@ static __inline__ ssize_t tun_get_user(struct tun_struct *tun, struct iovec *iv,
338 break; 440 break;
339 }; 441 };
340 442
341 if (tun->flags & TUN_NOCHECKSUM) 443 if (gso.gso_type != VIRTIO_NET_HDR_GSO_NONE) {
342 skb->ip_summed = CHECKSUM_UNNECESSARY; 444 pr_debug("GSO!\n");
445 switch (gso.gso_type & ~VIRTIO_NET_HDR_GSO_ECN) {
446 case VIRTIO_NET_HDR_GSO_TCPV4:
447 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
448 break;
449 case VIRTIO_NET_HDR_GSO_TCPV6:
450 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
451 break;
452 default:
453 tun->dev->stats.rx_frame_errors++;
454 kfree_skb(skb);
455 return -EINVAL;
456 }
457
458 if (gso.gso_type & VIRTIO_NET_HDR_GSO_ECN)
459 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
460
461 skb_shinfo(skb)->gso_size = gso.gso_size;
462 if (skb_shinfo(skb)->gso_size == 0) {
463 tun->dev->stats.rx_frame_errors++;
464 kfree_skb(skb);
465 return -EINVAL;
466 }
467
468 /* Header must be checked, and gso_segs computed. */
469 skb_shinfo(skb)->gso_type |= SKB_GSO_DODGY;
470 skb_shinfo(skb)->gso_segs = 0;
471 }
343 472
344 netif_rx_ni(skb); 473 netif_rx_ni(skb);
345 tun->dev->last_rx = jiffies; 474 tun->dev->last_rx = jiffies;
@@ -385,6 +514,39 @@ static __inline__ ssize_t tun_put_user(struct tun_struct *tun,
385 total += sizeof(pi); 514 total += sizeof(pi);
386 } 515 }
387 516
517 if (tun->flags & TUN_VNET_HDR) {
518 struct virtio_net_hdr gso = { 0 }; /* no info leak */
519 if ((len -= sizeof(gso)) < 0)
520 return -EINVAL;
521
522 if (skb_is_gso(skb)) {
523 struct skb_shared_info *sinfo = skb_shinfo(skb);
524
525 /* This is a hint as to how much should be linear. */
526 gso.hdr_len = skb_headlen(skb);
527 gso.gso_size = sinfo->gso_size;
528 if (sinfo->gso_type & SKB_GSO_TCPV4)
529 gso.gso_type = VIRTIO_NET_HDR_GSO_TCPV4;
530 else if (sinfo->gso_type & SKB_GSO_TCPV6)
531 gso.gso_type = VIRTIO_NET_HDR_GSO_TCPV6;
532 else
533 BUG();
534 if (sinfo->gso_type & SKB_GSO_TCP_ECN)
535 gso.gso_type |= VIRTIO_NET_HDR_GSO_ECN;
536 } else
537 gso.gso_type = VIRTIO_NET_HDR_GSO_NONE;
538
539 if (skb->ip_summed == CHECKSUM_PARTIAL) {
540 gso.flags = VIRTIO_NET_HDR_F_NEEDS_CSUM;
541 gso.csum_start = skb->csum_start - skb_headroom(skb);
542 gso.csum_offset = skb->csum_offset;
543 } /* else everything is zero */
544
545 if (unlikely(memcpy_toiovec(iv, (void *)&gso, sizeof(gso))))
546 return -EFAULT;
547 total += sizeof(gso);
548 }
549
388 len = min_t(int, skb->len, len); 550 len = min_t(int, skb->len, len);
389 551
390 skb_copy_datagram_iovec(skb, 0, iv, len); 552 skb_copy_datagram_iovec(skb, 0, iv, len);
@@ -404,7 +566,6 @@ static ssize_t tun_chr_aio_read(struct kiocb *iocb, const struct iovec *iv,
404 DECLARE_WAITQUEUE(wait, current); 566 DECLARE_WAITQUEUE(wait, current);
405 struct sk_buff *skb; 567 struct sk_buff *skb;
406 ssize_t len, ret = 0; 568 ssize_t len, ret = 0;
407 DECLARE_MAC_BUF(mac);
408 569
409 if (!tun) 570 if (!tun)
410 return -EBADFD; 571 return -EBADFD;
@@ -417,10 +578,6 @@ static ssize_t tun_chr_aio_read(struct kiocb *iocb, const struct iovec *iv,
417 578
418 add_wait_queue(&tun->read_wait, &wait); 579 add_wait_queue(&tun->read_wait, &wait);
419 while (len) { 580 while (len) {
420 const u8 ones[ ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
421 u8 addr[ ETH_ALEN];
422 int bit_nr;
423
424 current->state = TASK_INTERRUPTIBLE; 581 current->state = TASK_INTERRUPTIBLE;
425 582
426 /* Read frames from the queue */ 583 /* Read frames from the queue */
@@ -440,36 +597,9 @@ static ssize_t tun_chr_aio_read(struct kiocb *iocb, const struct iovec *iv,
440 } 597 }
441 netif_wake_queue(tun->dev); 598 netif_wake_queue(tun->dev);
442 599
443 /** Decide whether to accept this packet. This code is designed to 600 ret = tun_put_user(tun, skb, (struct iovec *) iv, len);
444 * behave identically to an Ethernet interface. Accept the packet if 601 kfree_skb(skb);
445 * - we are promiscuous. 602 break;
446 * - the packet is addressed to us.
447 * - the packet is broadcast.
448 * - the packet is multicast and
449 * - we are multicast promiscous.
450 * - we belong to the multicast group.
451 */
452 skb_copy_from_linear_data(skb, addr, min_t(size_t, sizeof addr,
453 skb->len));
454 bit_nr = ether_crc(sizeof addr, addr) >> 26;
455 if ((tun->if_flags & IFF_PROMISC) ||
456 memcmp(addr, tun->dev_addr, sizeof addr) == 0 ||
457 memcmp(addr, ones, sizeof addr) == 0 ||
458 (((addr[0] == 1 && addr[1] == 0 && addr[2] == 0x5e) ||
459 (addr[0] == 0x33 && addr[1] == 0x33)) &&
460 ((tun->if_flags & IFF_ALLMULTI) ||
461 (tun->chr_filter[bit_nr >> 5] & (1 << (bit_nr & 31)))))) {
462 DBG(KERN_DEBUG "%s: tun_chr_readv: accepted: %s\n",
463 tun->dev->name, print_mac(mac, addr));
464 ret = tun_put_user(tun, skb, (struct iovec *) iv, len);
465 kfree_skb(skb);
466 break;
467 } else {
468 DBG(KERN_DEBUG "%s: tun_chr_readv: rejected: %s\n",
469 tun->dev->name, print_mac(mac, addr));
470 kfree_skb(skb);
471 continue;
472 }
473 } 603 }
474 604
475 current->state = TASK_RUNNING; 605 current->state = TASK_RUNNING;
@@ -565,12 +695,7 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr)
565 tun = netdev_priv(dev); 695 tun = netdev_priv(dev);
566 tun->dev = dev; 696 tun->dev = dev;
567 tun->flags = flags; 697 tun->flags = flags;
568 /* Be promiscuous by default to maintain previous behaviour. */ 698 tun->txflt.count = 0;
569 tun->if_flags = IFF_PROMISC;
570 /* Generate random Ethernet address. */
571 *(__be16 *)tun->dev_addr = htons(0x00FF);
572 get_random_bytes(tun->dev_addr + sizeof(u16), 4);
573 memset(tun->chr_filter, 0, sizeof tun->chr_filter);
574 699
575 tun_net_init(dev); 700 tun_net_init(dev);
576 701
@@ -599,6 +724,11 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr)
599 else 724 else
600 tun->flags &= ~TUN_ONE_QUEUE; 725 tun->flags &= ~TUN_ONE_QUEUE;
601 726
727 if (ifr->ifr_flags & IFF_VNET_HDR)
728 tun->flags |= TUN_VNET_HDR;
729 else
730 tun->flags &= ~TUN_VNET_HDR;
731
602 file->private_data = tun; 732 file->private_data = tun;
603 tun->attached = 1; 733 tun->attached = 1;
604 get_net(dev_net(tun->dev)); 734 get_net(dev_net(tun->dev));
@@ -618,12 +748,53 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr)
618 return err; 748 return err;
619} 749}
620 750
751/* This is like a cut-down ethtool ops, except done via tun fd so no
752 * privs required. */
753static int set_offload(struct net_device *dev, unsigned long arg)
754{
755 unsigned int old_features, features;
756
757 old_features = dev->features;
758 /* Unset features, set them as we chew on the arg. */
759 features = (old_features & ~(NETIF_F_HW_CSUM|NETIF_F_SG|NETIF_F_FRAGLIST
760 |NETIF_F_TSO_ECN|NETIF_F_TSO|NETIF_F_TSO6));
761
762 if (arg & TUN_F_CSUM) {
763 features |= NETIF_F_HW_CSUM|NETIF_F_SG|NETIF_F_FRAGLIST;
764 arg &= ~TUN_F_CSUM;
765
766 if (arg & (TUN_F_TSO4|TUN_F_TSO6)) {
767 if (arg & TUN_F_TSO_ECN) {
768 features |= NETIF_F_TSO_ECN;
769 arg &= ~TUN_F_TSO_ECN;
770 }
771 if (arg & TUN_F_TSO4)
772 features |= NETIF_F_TSO;
773 if (arg & TUN_F_TSO6)
774 features |= NETIF_F_TSO6;
775 arg &= ~(TUN_F_TSO4|TUN_F_TSO6);
776 }
777 }
778
779 /* This gives the user a way to test for new features in future by
780 * trying to set them. */
781 if (arg)
782 return -EINVAL;
783
784 dev->features = features;
785 if (old_features != dev->features)
786 netdev_features_change(dev);
787
788 return 0;
789}
790
621static int tun_chr_ioctl(struct inode *inode, struct file *file, 791static int tun_chr_ioctl(struct inode *inode, struct file *file,
622 unsigned int cmd, unsigned long arg) 792 unsigned int cmd, unsigned long arg)
623{ 793{
624 struct tun_struct *tun = file->private_data; 794 struct tun_struct *tun = file->private_data;
625 void __user* argp = (void __user*)arg; 795 void __user* argp = (void __user*)arg;
626 struct ifreq ifr; 796 struct ifreq ifr;
797 int ret;
627 DECLARE_MAC_BUF(mac); 798 DECLARE_MAC_BUF(mac);
628 799
629 if (cmd == TUNSETIFF || _IOC_TYPE(cmd) == 0x89) 800 if (cmd == TUNSETIFF || _IOC_TYPE(cmd) == 0x89)
@@ -647,6 +818,15 @@ static int tun_chr_ioctl(struct inode *inode, struct file *file,
647 return 0; 818 return 0;
648 } 819 }
649 820
821 if (cmd == TUNGETFEATURES) {
822 /* Currently this just means: "what IFF flags are valid?".
823 * This is needed because we never checked for invalid flags on
824 * TUNSETIFF. */
825 return put_user(IFF_TUN | IFF_TAP | IFF_NO_PI | IFF_ONE_QUEUE |
826 IFF_VNET_HDR,
827 (unsigned int __user*)argp);
828 }
829
650 if (!tun) 830 if (!tun)
651 return -EBADFD; 831 return -EBADFD;
652 832
@@ -690,9 +870,6 @@ static int tun_chr_ioctl(struct inode *inode, struct file *file,
690 break; 870 break;
691 871
692 case TUNSETLINK: 872 case TUNSETLINK:
693 {
694 int ret;
695
696 /* Only allow setting the type when the interface is down */ 873 /* Only allow setting the type when the interface is down */
697 rtnl_lock(); 874 rtnl_lock();
698 if (tun->dev->flags & IFF_UP) { 875 if (tun->dev->flags & IFF_UP) {
@@ -706,85 +883,44 @@ static int tun_chr_ioctl(struct inode *inode, struct file *file,
706 } 883 }
707 rtnl_unlock(); 884 rtnl_unlock();
708 return ret; 885 return ret;
709 }
710 886
711#ifdef TUN_DEBUG 887#ifdef TUN_DEBUG
712 case TUNSETDEBUG: 888 case TUNSETDEBUG:
713 tun->debug = arg; 889 tun->debug = arg;
714 break; 890 break;
715#endif 891#endif
892 case TUNSETOFFLOAD:
893 rtnl_lock();
894 ret = set_offload(tun->dev, arg);
895 rtnl_unlock();
896 return ret;
716 897
717 case SIOCGIFFLAGS: 898 case TUNSETTXFILTER:
718 ifr.ifr_flags = tun->if_flags; 899 /* Can be set only for TAPs */
719 if (copy_to_user( argp, &ifr, sizeof ifr)) 900 if ((tun->flags & TUN_TYPE_MASK) != TUN_TAP_DEV)
720 return -EFAULT; 901 return -EINVAL;
721 return 0; 902 rtnl_lock();
722 903 ret = update_filter(&tun->txflt, (void *) __user arg);
723 case SIOCSIFFLAGS: 904 rtnl_unlock();
724 /** Set the character device's interface flags. Currently only 905 return ret;
725 * IFF_PROMISC and IFF_ALLMULTI are used. */
726 tun->if_flags = ifr.ifr_flags;
727 DBG(KERN_INFO "%s: interface flags 0x%lx\n",
728 tun->dev->name, tun->if_flags);
729 return 0;
730 906
731 case SIOCGIFHWADDR: 907 case SIOCGIFHWADDR:
732 /* Note: the actual net device's address may be different */ 908 /* Get hw addres */
733 memcpy(ifr.ifr_hwaddr.sa_data, tun->dev_addr, 909 memcpy(ifr.ifr_hwaddr.sa_data, tun->dev->dev_addr, ETH_ALEN);
734 min(sizeof ifr.ifr_hwaddr.sa_data, sizeof tun->dev_addr)); 910 ifr.ifr_hwaddr.sa_family = tun->dev->type;
735 if (copy_to_user( argp, &ifr, sizeof ifr)) 911 if (copy_to_user(argp, &ifr, sizeof ifr))
736 return -EFAULT; 912 return -EFAULT;
737 return 0; 913 return 0;
738 914
739 case SIOCSIFHWADDR: 915 case SIOCSIFHWADDR:
740 { 916 /* Set hw address */
741 /* try to set the actual net device's hw address */ 917 DBG(KERN_DEBUG "%s: set hw address: %s\n",
742 int ret; 918 tun->dev->name, print_mac(mac, ifr.ifr_hwaddr.sa_data));
743 919
744 rtnl_lock(); 920 rtnl_lock();
745 ret = dev_set_mac_address(tun->dev, &ifr.ifr_hwaddr); 921 ret = dev_set_mac_address(tun->dev, &ifr.ifr_hwaddr);
746 rtnl_unlock(); 922 rtnl_unlock();
747 923 return ret;
748 if (ret == 0) {
749 /** Set the character device's hardware address. This is used when
750 * filtering packets being sent from the network device to the character
751 * device. */
752 memcpy(tun->dev_addr, ifr.ifr_hwaddr.sa_data,
753 min(sizeof ifr.ifr_hwaddr.sa_data, sizeof tun->dev_addr));
754 DBG(KERN_DEBUG "%s: set hardware address: %x:%x:%x:%x:%x:%x\n",
755 tun->dev->name,
756 tun->dev_addr[0], tun->dev_addr[1], tun->dev_addr[2],
757 tun->dev_addr[3], tun->dev_addr[4], tun->dev_addr[5]);
758 }
759
760 return ret;
761 }
762
763 case SIOCADDMULTI:
764 /** Add the specified group to the character device's multicast filter
765 * list. */
766 rtnl_lock();
767 netif_tx_lock_bh(tun->dev);
768 add_multi(tun->chr_filter, ifr.ifr_hwaddr.sa_data);
769 netif_tx_unlock_bh(tun->dev);
770 rtnl_unlock();
771
772 DBG(KERN_DEBUG "%s: add multi: %s\n",
773 tun->dev->name, print_mac(mac, ifr.ifr_hwaddr.sa_data));
774 return 0;
775
776 case SIOCDELMULTI:
777 /** Remove the specified group from the character device's multicast
778 * filter list. */
779 rtnl_lock();
780 netif_tx_lock_bh(tun->dev);
781 del_multi(tun->chr_filter, ifr.ifr_hwaddr.sa_data);
782 netif_tx_unlock_bh(tun->dev);
783 rtnl_unlock();
784
785 DBG(KERN_DEBUG "%s: del multi: %s\n",
786 tun->dev->name, print_mac(mac, ifr.ifr_hwaddr.sa_data));
787 return 0;
788 924
789 default: 925 default:
790 return -EINVAL; 926 return -EINVAL;
diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c
index c0dd25ba7a18..8549f1159a30 100644
--- a/drivers/net/typhoon.c
+++ b/drivers/net/typhoon.c
@@ -334,8 +334,6 @@ enum state_values {
334#define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY) 334#define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
335#define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY) 335#define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
336 336
337#define typhoon_synchronize_irq(x) synchronize_irq(x)
338
339#if defined(NETIF_F_TSO) 337#if defined(NETIF_F_TSO)
340#define skb_tso_size(x) (skb_shinfo(x)->gso_size) 338#define skb_tso_size(x) (skb_shinfo(x)->gso_size)
341#define TSO_NUM_DESCRIPTORS 2 339#define TSO_NUM_DESCRIPTORS 2
@@ -2143,7 +2141,6 @@ typhoon_close(struct net_device *dev)
2143 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name); 2141 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2144 2142
2145 /* Make sure there is no irq handler running on a different CPU. */ 2143 /* Make sure there is no irq handler running on a different CPU. */
2146 typhoon_synchronize_irq(dev->irq);
2147 free_irq(dev->irq, dev); 2144 free_irq(dev->irq, dev);
2148 2145
2149 typhoon_free_rx_rings(tp); 2146 typhoon_free_rx_rings(tp);
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 402e81020fb8..756ba10b79d6 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -1588,7 +1588,7 @@ static void adjust_link(struct net_device *dev)
1588 if (!ugeth->oldlink) { 1588 if (!ugeth->oldlink) {
1589 new_state = 1; 1589 new_state = 1;
1590 ugeth->oldlink = 1; 1590 ugeth->oldlink = 1;
1591 netif_schedule(dev); 1591 netif_tx_schedule_all(dev);
1592 } 1592 }
1593 } else if (ugeth->oldlink) { 1593 } else if (ugeth->oldlink) {
1594 new_state = 1; 1594 new_state = 1;
@@ -3372,7 +3372,7 @@ static void ucc_geth_timeout(struct net_device *dev)
3372 ucc_geth_startup(ugeth); 3372 ucc_geth_startup(ugeth);
3373 } 3373 }
3374 3374
3375 netif_schedule(dev); 3375 netif_tx_schedule_all(dev);
3376} 3376}
3377 3377
3378/* This is called by the kernel when a frame is ready for transmission. */ 3378/* This is called by the kernel when a frame is ready for transmission. */
@@ -3500,11 +3500,7 @@ static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit
3500 3500
3501 dev->stats.rx_bytes += length; 3501 dev->stats.rx_bytes += length;
3502 /* Send the packet up the stack */ 3502 /* Send the packet up the stack */
3503#ifdef CONFIG_UGETH_NAPI
3504 netif_receive_skb(skb); 3503 netif_receive_skb(skb);
3505#else
3506 netif_rx(skb);
3507#endif /* CONFIG_UGETH_NAPI */
3508 } 3504 }
3509 3505
3510 ugeth->dev->last_rx = jiffies; 3506 ugeth->dev->last_rx = jiffies;
@@ -3580,7 +3576,6 @@ static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3580 return 0; 3576 return 0;
3581} 3577}
3582 3578
3583#ifdef CONFIG_UGETH_NAPI
3584static int ucc_geth_poll(struct napi_struct *napi, int budget) 3579static int ucc_geth_poll(struct napi_struct *napi, int budget)
3585{ 3580{
3586 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); 3581 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
@@ -3607,7 +3602,6 @@ static int ucc_geth_poll(struct napi_struct *napi, int budget)
3607 3602
3608 return howmany; 3603 return howmany;
3609} 3604}
3610#endif /* CONFIG_UGETH_NAPI */
3611 3605
3612static irqreturn_t ucc_geth_irq_handler(int irq, void *info) 3606static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3613{ 3607{
@@ -3617,9 +3611,6 @@ static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3617 struct ucc_geth_info *ug_info; 3611 struct ucc_geth_info *ug_info;
3618 register u32 ucce; 3612 register u32 ucce;
3619 register u32 uccm; 3613 register u32 uccm;
3620#ifndef CONFIG_UGETH_NAPI
3621 register u32 rx_mask;
3622#endif
3623 register u32 tx_mask; 3614 register u32 tx_mask;
3624 u8 i; 3615 u8 i;
3625 3616
@@ -3636,21 +3627,11 @@ static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3636 3627
3637 /* check for receive events that require processing */ 3628 /* check for receive events that require processing */
3638 if (ucce & UCCE_RX_EVENTS) { 3629 if (ucce & UCCE_RX_EVENTS) {
3639#ifdef CONFIG_UGETH_NAPI
3640 if (netif_rx_schedule_prep(dev, &ugeth->napi)) { 3630 if (netif_rx_schedule_prep(dev, &ugeth->napi)) {
3641 uccm &= ~UCCE_RX_EVENTS; 3631 uccm &= ~UCCE_RX_EVENTS;
3642 out_be32(uccf->p_uccm, uccm); 3632 out_be32(uccf->p_uccm, uccm);
3643 __netif_rx_schedule(dev, &ugeth->napi); 3633 __netif_rx_schedule(dev, &ugeth->napi);
3644 } 3634 }
3645#else
3646 rx_mask = UCCE_RXBF_SINGLE_MASK;
3647 for (i = 0; i < ug_info->numQueuesRx; i++) {
3648 if (ucce & rx_mask)
3649 ucc_geth_rx(ugeth, i, (int)ugeth->ug_info->bdRingLenRx[i]);
3650 ucce &= ~rx_mask;
3651 rx_mask <<= 1;
3652 }
3653#endif /* CONFIG_UGETH_NAPI */
3654 } 3635 }
3655 3636
3656 /* Tx event processing */ 3637 /* Tx event processing */
@@ -3720,9 +3701,8 @@ static int ucc_geth_open(struct net_device *dev)
3720 return err; 3701 return err;
3721 } 3702 }
3722 3703
3723#ifdef CONFIG_UGETH_NAPI
3724 napi_enable(&ugeth->napi); 3704 napi_enable(&ugeth->napi);
3725#endif 3705
3726 err = ucc_geth_startup(ugeth); 3706 err = ucc_geth_startup(ugeth);
3727 if (err) { 3707 if (err) {
3728 if (netif_msg_ifup(ugeth)) 3708 if (netif_msg_ifup(ugeth))
@@ -3783,9 +3763,8 @@ static int ucc_geth_open(struct net_device *dev)
3783 return err; 3763 return err;
3784 3764
3785out_err: 3765out_err:
3786#ifdef CONFIG_UGETH_NAPI
3787 napi_disable(&ugeth->napi); 3766 napi_disable(&ugeth->napi);
3788#endif 3767
3789 return err; 3768 return err;
3790} 3769}
3791 3770
@@ -3796,9 +3775,7 @@ static int ucc_geth_close(struct net_device *dev)
3796 3775
3797 ugeth_vdbg("%s: IN", __FUNCTION__); 3776 ugeth_vdbg("%s: IN", __FUNCTION__);
3798 3777
3799#ifdef CONFIG_UGETH_NAPI
3800 napi_disable(&ugeth->napi); 3778 napi_disable(&ugeth->napi);
3801#endif
3802 3779
3803 ucc_geth_stop(ugeth); 3780 ucc_geth_stop(ugeth);
3804 3781
@@ -4050,9 +4027,7 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma
4050 dev->hard_start_xmit = ucc_geth_start_xmit; 4027 dev->hard_start_xmit = ucc_geth_start_xmit;
4051 dev->tx_timeout = ucc_geth_timeout; 4028 dev->tx_timeout = ucc_geth_timeout;
4052 dev->watchdog_timeo = TX_TIMEOUT; 4029 dev->watchdog_timeo = TX_TIMEOUT;
4053#ifdef CONFIG_UGETH_NAPI
4054 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT); 4030 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT);
4055#endif /* CONFIG_UGETH_NAPI */
4056#ifdef CONFIG_NET_POLL_CONTROLLER 4031#ifdef CONFIG_NET_POLL_CONTROLLER
4057 dev->poll_controller = ucc_netpoll; 4032 dev->poll_controller = ucc_netpoll;
4058#endif 4033#endif
diff --git a/drivers/net/ucc_geth_ethtool.c b/drivers/net/ucc_geth_ethtool.c
index f5839c4a5cbd..cfbbfee55836 100644
--- a/drivers/net/ucc_geth_ethtool.c
+++ b/drivers/net/ucc_geth_ethtool.c
@@ -5,7 +5,7 @@
5 * 5 *
6 * Author: Li Yang <leoli@freescale.com> 6 * Author: Li Yang <leoli@freescale.com>
7 * 7 *
8 * Limitation: 8 * Limitation:
9 * Can only get/set setttings of the first queue. 9 * Can only get/set setttings of the first queue.
10 * Need to re-open the interface manually after changing some paramters. 10 * Need to re-open the interface manually after changing some paramters.
11 * 11 *
@@ -160,7 +160,7 @@ uec_set_pauseparam(struct net_device *netdev,
160 160
161 ugeth->ug_info->receiveFlowControl = pause->rx_pause; 161 ugeth->ug_info->receiveFlowControl = pause->rx_pause;
162 ugeth->ug_info->transmitFlowControl = pause->tx_pause; 162 ugeth->ug_info->transmitFlowControl = pause->tx_pause;
163 163
164 if (ugeth->phydev->autoneg) { 164 if (ugeth->phydev->autoneg) {
165 if (netif_running(netdev)) { 165 if (netif_running(netdev)) {
166 /* FIXME: automatically restart */ 166 /* FIXME: automatically restart */
diff --git a/drivers/net/usb/Kconfig b/drivers/net/usb/Kconfig
index 0604f3faf043..68e198bd538b 100644
--- a/drivers/net/usb/Kconfig
+++ b/drivers/net/usb/Kconfig
@@ -154,6 +154,16 @@ config USB_NET_AX8817X
154 This driver creates an interface named "ethX", where X depends on 154 This driver creates an interface named "ethX", where X depends on
155 what other networking devices you have in use. 155 what other networking devices you have in use.
156 156
157config USB_HSO
158 tristate "Option USB High Speed Mobile Devices"
159 depends on USB && RFKILL
160 default n
161 help
162 Choose this option if you have an Option HSDPA/HSUPA card.
163 These cards support downlink speeds of 7.2Mbps or greater.
164
165 To compile this driver as a module, choose M here: the
166 module will be called hso.
157 167
158config USB_NET_CDCETHER 168config USB_NET_CDCETHER
159 tristate "CDC Ethernet support (smart devices such as cable modems)" 169 tristate "CDC Ethernet support (smart devices such as cable modems)"
diff --git a/drivers/net/usb/Makefile b/drivers/net/usb/Makefile
index 595a539f8384..24800c157f98 100644
--- a/drivers/net/usb/Makefile
+++ b/drivers/net/usb/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_USB_CATC) += catc.o
6obj-$(CONFIG_USB_KAWETH) += kaweth.o 6obj-$(CONFIG_USB_KAWETH) += kaweth.o
7obj-$(CONFIG_USB_PEGASUS) += pegasus.o 7obj-$(CONFIG_USB_PEGASUS) += pegasus.o
8obj-$(CONFIG_USB_RTL8150) += rtl8150.o 8obj-$(CONFIG_USB_RTL8150) += rtl8150.o
9obj-$(CONFIG_USB_HSO) += hso.o
9obj-$(CONFIG_USB_NET_AX8817X) += asix.o 10obj-$(CONFIG_USB_NET_AX8817X) += asix.o
10obj-$(CONFIG_USB_NET_CDCETHER) += cdc_ether.o 11obj-$(CONFIG_USB_NET_CDCETHER) += cdc_ether.o
11obj-$(CONFIG_USB_NET_DM9601) += dm9601.o 12obj-$(CONFIG_USB_NET_DM9601) += dm9601.o
diff --git a/drivers/net/usb/hso.c b/drivers/net/usb/hso.c
new file mode 100644
index 000000000000..031d07b105af
--- /dev/null
+++ b/drivers/net/usb/hso.c
@@ -0,0 +1,2836 @@
1/******************************************************************************
2 *
3 * Driver for Option High Speed Mobile Devices.
4 *
5 * Copyright (C) 2008 Option International
6 * Copyright (C) 2007 Andrew Bird (Sphere Systems Ltd)
7 * <ajb@spheresystems.co.uk>
8 * Copyright (C) 2008 Greg Kroah-Hartman <gregkh@suse.de>
9 * Copyright (C) 2008 Novell, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
23 * USA
24 *
25 *
26 *****************************************************************************/
27
28/******************************************************************************
29 *
30 * Description of the device:
31 *
32 * Interface 0: Contains the IP network interface on the bulk end points.
33 * The multiplexed serial ports are using the interrupt and
34 * control endpoints.
35 * Interrupt contains a bitmap telling which multiplexed
36 * serialport needs servicing.
37 *
38 * Interface 1: Diagnostics port, uses bulk only, do not submit urbs until the
39 * port is opened, as this have a huge impact on the network port
40 * throughput.
41 *
42 * Interface 2: Standard modem interface - circuit switched interface, should
43 * not be used.
44 *
45 *****************************************************************************/
46
47#include <linux/sched.h>
48#include <linux/slab.h>
49#include <linux/init.h>
50#include <linux/delay.h>
51#include <linux/netdevice.h>
52#include <linux/module.h>
53#include <linux/ethtool.h>
54#include <linux/usb.h>
55#include <linux/timer.h>
56#include <linux/tty.h>
57#include <linux/tty_driver.h>
58#include <linux/tty_flip.h>
59#include <linux/kmod.h>
60#include <linux/rfkill.h>
61#include <linux/ip.h>
62#include <linux/uaccess.h>
63#include <linux/usb/cdc.h>
64#include <net/arp.h>
65#include <asm/byteorder.h>
66
67
68#define DRIVER_VERSION "1.2"
69#define MOD_AUTHOR "Option Wireless"
70#define MOD_DESCRIPTION "USB High Speed Option driver"
71#define MOD_LICENSE "GPL"
72
73#define HSO_MAX_NET_DEVICES 10
74#define HSO__MAX_MTU 2048
75#define DEFAULT_MTU 1500
76#define DEFAULT_MRU 1500
77
78#define CTRL_URB_RX_SIZE 1024
79#define CTRL_URB_TX_SIZE 64
80
81#define BULK_URB_RX_SIZE 4096
82#define BULK_URB_TX_SIZE 8192
83
84#define MUX_BULK_RX_BUF_SIZE HSO__MAX_MTU
85#define MUX_BULK_TX_BUF_SIZE HSO__MAX_MTU
86#define MUX_BULK_RX_BUF_COUNT 4
87#define USB_TYPE_OPTION_VENDOR 0x20
88
89/* These definitions are used with the struct hso_net flags element */
90/* - use *_bit operations on it. (bit indices not values.) */
91#define HSO_NET_RUNNING 0
92
93#define HSO_NET_TX_TIMEOUT (HZ*10)
94
95/* Serial port defines and structs. */
96#define HSO_SERIAL_FLAG_RX_SENT 0
97
98#define HSO_SERIAL_MAGIC 0x48534f31
99
100/* Number of ttys to handle */
101#define HSO_SERIAL_TTY_MINORS 256
102
103#define MAX_RX_URBS 2
104
105#define get_serial_by_tty(x) \
106 (x ? (struct hso_serial *)x->driver_data : NULL)
107
108/*****************************************************************************/
109/* Debugging functions */
110/*****************************************************************************/
111#define D__(lvl_, fmt, arg...) \
112 do { \
113 printk(lvl_ "[%d:%s]: " fmt "\n", \
114 __LINE__, __func__, ## arg); \
115 } while (0)
116
117#define D_(lvl, args...) \
118 do { \
119 if (lvl & debug) \
120 D__(KERN_INFO, args); \
121 } while (0)
122
123#define D1(args...) D_(0x01, ##args)
124#define D2(args...) D_(0x02, ##args)
125#define D3(args...) D_(0x04, ##args)
126#define D4(args...) D_(0x08, ##args)
127#define D5(args...) D_(0x10, ##args)
128
129/*****************************************************************************/
130/* Enumerators */
131/*****************************************************************************/
132enum pkt_parse_state {
133 WAIT_IP,
134 WAIT_DATA,
135 WAIT_SYNC
136};
137
138/*****************************************************************************/
139/* Structs */
140/*****************************************************************************/
141
142struct hso_shared_int {
143 struct usb_endpoint_descriptor *intr_endp;
144 void *shared_intr_buf;
145 struct urb *shared_intr_urb;
146 struct usb_device *usb;
147 int use_count;
148 int ref_count;
149 struct mutex shared_int_lock;
150};
151
152struct hso_net {
153 struct hso_device *parent;
154 struct net_device *net;
155 struct rfkill *rfkill;
156
157 struct usb_endpoint_descriptor *in_endp;
158 struct usb_endpoint_descriptor *out_endp;
159
160 struct urb *mux_bulk_rx_urb_pool[MUX_BULK_RX_BUF_COUNT];
161 struct urb *mux_bulk_tx_urb;
162 void *mux_bulk_rx_buf_pool[MUX_BULK_RX_BUF_COUNT];
163 void *mux_bulk_tx_buf;
164
165 struct sk_buff *skb_rx_buf;
166 struct sk_buff *skb_tx_buf;
167
168 enum pkt_parse_state rx_parse_state;
169 spinlock_t net_lock;
170
171 unsigned short rx_buf_size;
172 unsigned short rx_buf_missing;
173 struct iphdr rx_ip_hdr;
174
175 unsigned long flags;
176};
177
178struct hso_serial {
179 struct hso_device *parent;
180 int magic;
181 u8 minor;
182
183 struct hso_shared_int *shared_int;
184
185 /* rx/tx urb could be either a bulk urb or a control urb depending
186 on which serial port it is used on. */
187 struct urb *rx_urb[MAX_RX_URBS];
188 u8 num_rx_urbs;
189 u8 *rx_data[MAX_RX_URBS];
190 u16 rx_data_length; /* should contain allocated length */
191
192 struct urb *tx_urb;
193 u8 *tx_data;
194 u8 *tx_buffer;
195 u16 tx_data_length; /* should contain allocated length */
196 u16 tx_data_count;
197 u16 tx_buffer_count;
198 struct usb_ctrlrequest ctrl_req_tx;
199 struct usb_ctrlrequest ctrl_req_rx;
200
201 struct usb_endpoint_descriptor *in_endp;
202 struct usb_endpoint_descriptor *out_endp;
203
204 unsigned long flags;
205 u8 rts_state;
206 u8 dtr_state;
207 unsigned tx_urb_used:1;
208
209 /* from usb_serial_port */
210 struct tty_struct *tty;
211 int open_count;
212 spinlock_t serial_lock;
213
214 int (*write_data) (struct hso_serial *serial);
215};
216
217struct hso_device {
218 union {
219 struct hso_serial *dev_serial;
220 struct hso_net *dev_net;
221 } port_data;
222
223 u32 port_spec;
224
225 u8 is_active;
226 u8 usb_gone;
227 struct work_struct async_get_intf;
228 struct work_struct async_put_intf;
229
230 struct usb_device *usb;
231 struct usb_interface *interface;
232
233 struct device *dev;
234 struct kref ref;
235 struct mutex mutex;
236};
237
238/* Type of interface */
239#define HSO_INTF_MASK 0xFF00
240#define HSO_INTF_MUX 0x0100
241#define HSO_INTF_BULK 0x0200
242
243/* Type of port */
244#define HSO_PORT_MASK 0xFF
245#define HSO_PORT_NO_PORT 0x0
246#define HSO_PORT_CONTROL 0x1
247#define HSO_PORT_APP 0x2
248#define HSO_PORT_GPS 0x3
249#define HSO_PORT_PCSC 0x4
250#define HSO_PORT_APP2 0x5
251#define HSO_PORT_GPS_CONTROL 0x6
252#define HSO_PORT_MSD 0x7
253#define HSO_PORT_VOICE 0x8
254#define HSO_PORT_DIAG2 0x9
255#define HSO_PORT_DIAG 0x10
256#define HSO_PORT_MODEM 0x11
257#define HSO_PORT_NETWORK 0x12
258
259/* Additional device info */
260#define HSO_INFO_MASK 0xFF000000
261#define HSO_INFO_CRC_BUG 0x01000000
262
263/*****************************************************************************/
264/* Prototypes */
265/*****************************************************************************/
266/* Serial driver functions */
267static int hso_serial_tiocmset(struct tty_struct *tty, struct file *file,
268 unsigned int set, unsigned int clear);
269static void ctrl_callback(struct urb *urb);
270static void put_rxbuf_data(struct urb *urb, struct hso_serial *serial);
271static void hso_kick_transmit(struct hso_serial *serial);
272/* Helper functions */
273static int hso_mux_submit_intr_urb(struct hso_shared_int *mux_int,
274 struct usb_device *usb, gfp_t gfp);
275static void log_usb_status(int status, const char *function);
276static struct usb_endpoint_descriptor *hso_get_ep(struct usb_interface *intf,
277 int type, int dir);
278static int hso_get_mux_ports(struct usb_interface *intf, unsigned char *ports);
279static void hso_free_interface(struct usb_interface *intf);
280static int hso_start_serial_device(struct hso_device *hso_dev, gfp_t flags);
281static int hso_stop_serial_device(struct hso_device *hso_dev);
282static int hso_start_net_device(struct hso_device *hso_dev);
283static void hso_free_shared_int(struct hso_shared_int *shared_int);
284static int hso_stop_net_device(struct hso_device *hso_dev);
285static void hso_serial_ref_free(struct kref *ref);
286static void async_get_intf(struct work_struct *data);
287static void async_put_intf(struct work_struct *data);
288static int hso_put_activity(struct hso_device *hso_dev);
289static int hso_get_activity(struct hso_device *hso_dev);
290
291/*****************************************************************************/
292/* Helping functions */
293/*****************************************************************************/
294
295/* #define DEBUG */
296
297#define dev2net(x) (x->port_data.dev_net)
298#define dev2ser(x) (x->port_data.dev_serial)
299
300/* Debugging functions */
301#ifdef DEBUG
302static void dbg_dump(int line_count, const char *func_name, unsigned char *buf,
303 unsigned int len)
304{
305 u8 i = 0;
306
307 printk(KERN_DEBUG "[%d:%s]: len %d", line_count, func_name, len);
308
309 for (i = 0; i < len; i++) {
310 if (!(i % 16))
311 printk("\n 0x%03x: ", i);
312 printk("%02x ", (unsigned char)buf[i]);
313 }
314 printk("\n");
315}
316
317#define DUMP(buf_, len_) \
318 dbg_dump(__LINE__, __func__, buf_, len_)
319
320#define DUMP1(buf_, len_) \
321 do { \
322 if (0x01 & debug) \
323 DUMP(buf_, len_); \
324 } while (0)
325#else
326#define DUMP(buf_, len_)
327#define DUMP1(buf_, len_)
328#endif
329
330/* module parameters */
331static int debug;
332static int tty_major;
333static int disable_net;
334
335/* driver info */
336static const char driver_name[] = "hso";
337static const char tty_filename[] = "ttyHS";
338static const char *version = __FILE__ ": " DRIVER_VERSION " " MOD_AUTHOR;
339/* the usb driver itself (registered in hso_init) */
340static struct usb_driver hso_driver;
341/* serial structures */
342static struct tty_driver *tty_drv;
343static struct hso_device *serial_table[HSO_SERIAL_TTY_MINORS];
344static struct hso_device *network_table[HSO_MAX_NET_DEVICES];
345static spinlock_t serial_table_lock;
346static struct ktermios *hso_serial_termios[HSO_SERIAL_TTY_MINORS];
347static struct ktermios *hso_serial_termios_locked[HSO_SERIAL_TTY_MINORS];
348
349static const s32 default_port_spec[] = {
350 HSO_INTF_MUX | HSO_PORT_NETWORK,
351 HSO_INTF_BULK | HSO_PORT_DIAG,
352 HSO_INTF_BULK | HSO_PORT_MODEM,
353 0
354};
355
356static const s32 icon321_port_spec[] = {
357 HSO_INTF_MUX | HSO_PORT_NETWORK,
358 HSO_INTF_BULK | HSO_PORT_DIAG2,
359 HSO_INTF_BULK | HSO_PORT_MODEM,
360 HSO_INTF_BULK | HSO_PORT_DIAG,
361 0
362};
363
364#define default_port_device(vendor, product) \
365 USB_DEVICE(vendor, product), \
366 .driver_info = (kernel_ulong_t)default_port_spec
367
368#define icon321_port_device(vendor, product) \
369 USB_DEVICE(vendor, product), \
370 .driver_info = (kernel_ulong_t)icon321_port_spec
371
372/* list of devices we support */
373static const struct usb_device_id hso_ids[] = {
374 {default_port_device(0x0af0, 0x6711)},
375 {default_port_device(0x0af0, 0x6731)},
376 {default_port_device(0x0af0, 0x6751)},
377 {default_port_device(0x0af0, 0x6771)},
378 {default_port_device(0x0af0, 0x6791)},
379 {default_port_device(0x0af0, 0x6811)},
380 {default_port_device(0x0af0, 0x6911)},
381 {default_port_device(0x0af0, 0x6951)},
382 {default_port_device(0x0af0, 0x6971)},
383 {default_port_device(0x0af0, 0x7011)},
384 {default_port_device(0x0af0, 0x7031)},
385 {default_port_device(0x0af0, 0x7051)},
386 {default_port_device(0x0af0, 0x7071)},
387 {default_port_device(0x0af0, 0x7111)},
388 {default_port_device(0x0af0, 0x7211)},
389 {default_port_device(0x0af0, 0x7251)},
390 {default_port_device(0x0af0, 0x7271)},
391 {default_port_device(0x0af0, 0x7311)},
392 {default_port_device(0x0af0, 0xc031)}, /* Icon-Edge */
393 {icon321_port_device(0x0af0, 0xd013)}, /* Module HSxPA */
394 {icon321_port_device(0x0af0, 0xd031)}, /* Icon-321 */
395 {default_port_device(0x0af0, 0xd033)}, /* Icon-322 */
396 {USB_DEVICE(0x0af0, 0x7301)}, /* GE40x */
397 {USB_DEVICE(0x0af0, 0x7361)}, /* GE40x */
398 {USB_DEVICE(0x0af0, 0x7401)}, /* GI 0401 */
399 {USB_DEVICE(0x0af0, 0x7501)}, /* GTM 382 */
400 {USB_DEVICE(0x0af0, 0x7601)}, /* GE40x */
401 {}
402};
403MODULE_DEVICE_TABLE(usb, hso_ids);
404
405/* Sysfs attribute */
406static ssize_t hso_sysfs_show_porttype(struct device *dev,
407 struct device_attribute *attr,
408 char *buf)
409{
410 struct hso_device *hso_dev = dev->driver_data;
411 char *port_name;
412
413 if (!hso_dev)
414 return 0;
415
416 switch (hso_dev->port_spec & HSO_PORT_MASK) {
417 case HSO_PORT_CONTROL:
418 port_name = "Control";
419 break;
420 case HSO_PORT_APP:
421 port_name = "Application";
422 break;
423 case HSO_PORT_APP2:
424 port_name = "Application2";
425 break;
426 case HSO_PORT_GPS:
427 port_name = "GPS";
428 break;
429 case HSO_PORT_GPS_CONTROL:
430 port_name = "GPS Control";
431 break;
432 case HSO_PORT_PCSC:
433 port_name = "PCSC";
434 break;
435 case HSO_PORT_DIAG:
436 port_name = "Diagnostic";
437 break;
438 case HSO_PORT_DIAG2:
439 port_name = "Diagnostic2";
440 break;
441 case HSO_PORT_MODEM:
442 port_name = "Modem";
443 break;
444 case HSO_PORT_NETWORK:
445 port_name = "Network";
446 break;
447 default:
448 port_name = "Unknown";
449 break;
450 }
451
452 return sprintf(buf, "%s\n", port_name);
453}
454static DEVICE_ATTR(hsotype, S_IRUGO, hso_sysfs_show_porttype, NULL);
455
456/* converts mux value to a port spec value */
457static u32 hso_mux_to_port(int mux)
458{
459 u32 result;
460
461 switch (mux) {
462 case 0x1:
463 result = HSO_PORT_CONTROL;
464 break;
465 case 0x2:
466 result = HSO_PORT_APP;
467 break;
468 case 0x4:
469 result = HSO_PORT_PCSC;
470 break;
471 case 0x8:
472 result = HSO_PORT_GPS;
473 break;
474 case 0x10:
475 result = HSO_PORT_APP2;
476 break;
477 default:
478 result = HSO_PORT_NO_PORT;
479 }
480 return result;
481}
482
483/* converts port spec value to a mux value */
484static u32 hso_port_to_mux(int port)
485{
486 u32 result;
487
488 switch (port & HSO_PORT_MASK) {
489 case HSO_PORT_CONTROL:
490 result = 0x0;
491 break;
492 case HSO_PORT_APP:
493 result = 0x1;
494 break;
495 case HSO_PORT_PCSC:
496 result = 0x2;
497 break;
498 case HSO_PORT_GPS:
499 result = 0x3;
500 break;
501 case HSO_PORT_APP2:
502 result = 0x4;
503 break;
504 default:
505 result = 0x0;
506 }
507 return result;
508}
509
510static struct hso_serial *get_serial_by_shared_int_and_type(
511 struct hso_shared_int *shared_int,
512 int mux)
513{
514 int i, port;
515
516 port = hso_mux_to_port(mux);
517
518 for (i = 0; i < HSO_SERIAL_TTY_MINORS; i++) {
519 if (serial_table[i]
520 && (dev2ser(serial_table[i])->shared_int == shared_int)
521 && ((serial_table[i]->port_spec & HSO_PORT_MASK) == port)) {
522 return dev2ser(serial_table[i]);
523 }
524 }
525
526 return NULL;
527}
528
529static struct hso_serial *get_serial_by_index(unsigned index)
530{
531 struct hso_serial *serial;
532 unsigned long flags;
533
534 if (!serial_table[index])
535 return NULL;
536 spin_lock_irqsave(&serial_table_lock, flags);
537 serial = dev2ser(serial_table[index]);
538 spin_unlock_irqrestore(&serial_table_lock, flags);
539
540 return serial;
541}
542
543static int get_free_serial_index(void)
544{
545 int index;
546 unsigned long flags;
547
548 spin_lock_irqsave(&serial_table_lock, flags);
549 for (index = 0; index < HSO_SERIAL_TTY_MINORS; index++) {
550 if (serial_table[index] == NULL) {
551 spin_unlock_irqrestore(&serial_table_lock, flags);
552 return index;
553 }
554 }
555 spin_unlock_irqrestore(&serial_table_lock, flags);
556
557 printk(KERN_ERR "%s: no free serial devices in table\n", __func__);
558 return -1;
559}
560
561static void set_serial_by_index(unsigned index, struct hso_serial *serial)
562{
563 unsigned long flags;
564 spin_lock_irqsave(&serial_table_lock, flags);
565 if (serial)
566 serial_table[index] = serial->parent;
567 else
568 serial_table[index] = NULL;
569 spin_unlock_irqrestore(&serial_table_lock, flags);
570}
571
572/* log a meaningfull explanation of an USB status */
573static void log_usb_status(int status, const char *function)
574{
575 char *explanation;
576
577 switch (status) {
578 case -ENODEV:
579 explanation = "no device";
580 break;
581 case -ENOENT:
582 explanation = "endpoint not enabled";
583 break;
584 case -EPIPE:
585 explanation = "endpoint stalled";
586 break;
587 case -ENOSPC:
588 explanation = "not enough bandwidth";
589 break;
590 case -ESHUTDOWN:
591 explanation = "device disabled";
592 break;
593 case -EHOSTUNREACH:
594 explanation = "device suspended";
595 break;
596 case -EINVAL:
597 case -EAGAIN:
598 case -EFBIG:
599 case -EMSGSIZE:
600 explanation = "internal error";
601 break;
602 default:
603 explanation = "unknown status";
604 break;
605 }
606 D1("%s: received USB status - %s (%d)", function, explanation, status);
607}
608
609/* Network interface functions */
610
611/* called when net interface is brought up by ifconfig */
612static int hso_net_open(struct net_device *net)
613{
614 struct hso_net *odev = netdev_priv(net);
615 unsigned long flags = 0;
616
617 if (!odev) {
618 dev_err(&net->dev, "No net device !\n");
619 return -ENODEV;
620 }
621
622 odev->skb_tx_buf = NULL;
623
624 /* setup environment */
625 spin_lock_irqsave(&odev->net_lock, flags);
626 odev->rx_parse_state = WAIT_IP;
627 odev->rx_buf_size = 0;
628 odev->rx_buf_missing = sizeof(struct iphdr);
629 spin_unlock_irqrestore(&odev->net_lock, flags);
630
631 hso_start_net_device(odev->parent);
632
633 /* We are up and running. */
634 set_bit(HSO_NET_RUNNING, &odev->flags);
635
636 /* Tell the kernel we are ready to start receiving from it */
637 netif_start_queue(net);
638
639 return 0;
640}
641
642/* called when interface is brought down by ifconfig */
643static int hso_net_close(struct net_device *net)
644{
645 struct hso_net *odev = netdev_priv(net);
646
647 /* we don't need the queue anymore */
648 netif_stop_queue(net);
649 /* no longer running */
650 clear_bit(HSO_NET_RUNNING, &odev->flags);
651
652 hso_stop_net_device(odev->parent);
653
654 /* done */
655 return 0;
656}
657
658/* USB tells is xmit done, we should start the netqueue again */
659static void write_bulk_callback(struct urb *urb)
660{
661 struct hso_net *odev = urb->context;
662 int status = urb->status;
663
664 /* Sanity check */
665 if (!odev || !test_bit(HSO_NET_RUNNING, &odev->flags)) {
666 dev_err(&urb->dev->dev, "%s: device not running\n", __func__);
667 return;
668 }
669
670 /* Do we still have a valid kernel network device? */
671 if (!netif_device_present(odev->net)) {
672 dev_err(&urb->dev->dev, "%s: net device not present\n",
673 __func__);
674 return;
675 }
676
677 /* log status, but don't act on it, we don't need to resubmit anything
678 * anyhow */
679 if (status)
680 log_usb_status(status, __func__);
681
682 hso_put_activity(odev->parent);
683
684 /* Tell the network interface we are ready for another frame */
685 netif_wake_queue(odev->net);
686}
687
688/* called by kernel when we need to transmit a packet */
689static int hso_net_start_xmit(struct sk_buff *skb, struct net_device *net)
690{
691 struct hso_net *odev = netdev_priv(net);
692 int result;
693
694 /* Tell the kernel, "No more frames 'til we are done with this one." */
695 netif_stop_queue(net);
696 if (hso_get_activity(odev->parent) == -EAGAIN) {
697 odev->skb_tx_buf = skb;
698 return 0;
699 }
700
701 /* log if asked */
702 DUMP1(skb->data, skb->len);
703 /* Copy it from kernel memory to OUR memory */
704 memcpy(odev->mux_bulk_tx_buf, skb->data, skb->len);
705 D1("len: %d/%d", skb->len, MUX_BULK_TX_BUF_SIZE);
706
707 /* Fill in the URB for shipping it out. */
708 usb_fill_bulk_urb(odev->mux_bulk_tx_urb,
709 odev->parent->usb,
710 usb_sndbulkpipe(odev->parent->usb,
711 odev->out_endp->
712 bEndpointAddress & 0x7F),
713 odev->mux_bulk_tx_buf, skb->len, write_bulk_callback,
714 odev);
715
716 /* Deal with the Zero Length packet problem, I hope */
717 odev->mux_bulk_tx_urb->transfer_flags |= URB_ZERO_PACKET;
718
719 /* Send the URB on its merry way. */
720 result = usb_submit_urb(odev->mux_bulk_tx_urb, GFP_ATOMIC);
721 if (result) {
722 dev_warn(&odev->parent->interface->dev,
723 "failed mux_bulk_tx_urb %d", result);
724 net->stats.tx_errors++;
725 netif_start_queue(net);
726 } else {
727 net->stats.tx_packets++;
728 net->stats.tx_bytes += skb->len;
729 /* And tell the kernel when the last transmit started. */
730 net->trans_start = jiffies;
731 }
732 dev_kfree_skb(skb);
733 /* we're done */
734 return result;
735}
736
737static void hso_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info)
738{
739 struct hso_net *odev = netdev_priv(net);
740
741 strncpy(info->driver, driver_name, ETHTOOL_BUSINFO_LEN);
742 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
743 usb_make_path(odev->parent->usb, info->bus_info, sizeof info->bus_info);
744}
745
746static struct ethtool_ops ops = {
747 .get_drvinfo = hso_get_drvinfo,
748 .get_link = ethtool_op_get_link
749};
750
751/* called when a packet did not ack after watchdogtimeout */
752static void hso_net_tx_timeout(struct net_device *net)
753{
754 struct hso_net *odev = netdev_priv(net);
755
756 if (!odev)
757 return;
758
759 /* Tell syslog we are hosed. */
760 dev_warn(&net->dev, "Tx timed out.\n");
761
762 /* Tear the waiting frame off the list */
763 if (odev->mux_bulk_tx_urb
764 && (odev->mux_bulk_tx_urb->status == -EINPROGRESS))
765 usb_unlink_urb(odev->mux_bulk_tx_urb);
766
767 /* Update statistics */
768 net->stats.tx_errors++;
769}
770
771/* make a real packet from the received USB buffer */
772static void packetizeRx(struct hso_net *odev, unsigned char *ip_pkt,
773 unsigned int count, unsigned char is_eop)
774{
775 unsigned short temp_bytes;
776 unsigned short buffer_offset = 0;
777 unsigned short frame_len;
778 unsigned char *tmp_rx_buf;
779
780 /* log if needed */
781 D1("Rx %d bytes", count);
782 DUMP(ip_pkt, min(128, (int)count));
783
784 while (count) {
785 switch (odev->rx_parse_state) {
786 case WAIT_IP:
787 /* waiting for IP header. */
788 /* wanted bytes - size of ip header */
789 temp_bytes =
790 (count <
791 odev->rx_buf_missing) ? count : odev->
792 rx_buf_missing;
793
794 memcpy(((unsigned char *)(&odev->rx_ip_hdr)) +
795 odev->rx_buf_size, ip_pkt + buffer_offset,
796 temp_bytes);
797
798 odev->rx_buf_size += temp_bytes;
799 buffer_offset += temp_bytes;
800 odev->rx_buf_missing -= temp_bytes;
801 count -= temp_bytes;
802
803 if (!odev->rx_buf_missing) {
804 /* header is complete allocate an sk_buffer and
805 * continue to WAIT_DATA */
806 frame_len = ntohs(odev->rx_ip_hdr.tot_len);
807
808 if ((frame_len > DEFAULT_MRU) ||
809 (frame_len < sizeof(struct iphdr))) {
810 dev_err(&odev->net->dev,
811 "Invalid frame (%d) length\n",
812 frame_len);
813 odev->rx_parse_state = WAIT_SYNC;
814 continue;
815 }
816 /* Allocate an sk_buff */
817 odev->skb_rx_buf = dev_alloc_skb(frame_len);
818 if (!odev->skb_rx_buf) {
819 /* We got no receive buffer. */
820 D1("could not allocate memory");
821 odev->rx_parse_state = WAIT_SYNC;
822 return;
823 }
824 /* Here's where it came from */
825 odev->skb_rx_buf->dev = odev->net;
826
827 /* Copy what we got so far. make room for iphdr
828 * after tail. */
829 tmp_rx_buf =
830 skb_put(odev->skb_rx_buf,
831 sizeof(struct iphdr));
832 memcpy(tmp_rx_buf, (char *)&(odev->rx_ip_hdr),
833 sizeof(struct iphdr));
834
835 /* ETH_HLEN */
836 odev->rx_buf_size = sizeof(struct iphdr);
837
838 /* Filip actually use .tot_len */
839 odev->rx_buf_missing =
840 frame_len - sizeof(struct iphdr);
841 odev->rx_parse_state = WAIT_DATA;
842 }
843 break;
844
845 case WAIT_DATA:
846 temp_bytes = (count < odev->rx_buf_missing)
847 ? count : odev->rx_buf_missing;
848
849 /* Copy the rest of the bytes that are left in the
850 * buffer into the waiting sk_buf. */
851 /* Make room for temp_bytes after tail. */
852 tmp_rx_buf = skb_put(odev->skb_rx_buf, temp_bytes);
853 memcpy(tmp_rx_buf, ip_pkt + buffer_offset, temp_bytes);
854
855 odev->rx_buf_missing -= temp_bytes;
856 count -= temp_bytes;
857 buffer_offset += temp_bytes;
858 odev->rx_buf_size += temp_bytes;
859 if (!odev->rx_buf_missing) {
860 /* Packet is complete. Inject into stack. */
861 /* We have IP packet here */
862 odev->skb_rx_buf->protocol =
863 __constant_htons(ETH_P_IP);
864 /* don't check it */
865 odev->skb_rx_buf->ip_summed =
866 CHECKSUM_UNNECESSARY;
867
868 skb_reset_mac_header(odev->skb_rx_buf);
869
870 /* Ship it off to the kernel */
871 netif_rx(odev->skb_rx_buf);
872 /* No longer our buffer. */
873 odev->skb_rx_buf = NULL;
874
875 /* update out statistics */
876 odev->net->stats.rx_packets++;
877
878 odev->net->stats.rx_bytes += odev->rx_buf_size;
879
880 odev->rx_buf_size = 0;
881 odev->rx_buf_missing = sizeof(struct iphdr);
882 odev->rx_parse_state = WAIT_IP;
883 }
884 break;
885
886 case WAIT_SYNC:
887 D1(" W_S");
888 count = 0;
889 break;
890 default:
891 D1(" ");
892 count--;
893 break;
894 }
895 }
896
897 /* Recovery mechanism for WAIT_SYNC state. */
898 if (is_eop) {
899 if (odev->rx_parse_state == WAIT_SYNC) {
900 odev->rx_parse_state = WAIT_IP;
901 odev->rx_buf_size = 0;
902 odev->rx_buf_missing = sizeof(struct iphdr);
903 }
904 }
905}
906
907/* Moving data from usb to kernel (in interrupt state) */
908static void read_bulk_callback(struct urb *urb)
909{
910 struct hso_net *odev = urb->context;
911 struct net_device *net;
912 int result;
913 int status = urb->status;
914
915 /* is al ok? (Filip: Who's Al ?) */
916 if (status) {
917 log_usb_status(status, __func__);
918 return;
919 }
920
921 /* Sanity check */
922 if (!odev || !test_bit(HSO_NET_RUNNING, &odev->flags)) {
923 D1("BULK IN callback but driver is not active!");
924 return;
925 }
926 usb_mark_last_busy(urb->dev);
927
928 net = odev->net;
929
930 if (!netif_device_present(net)) {
931 /* Somebody killed our network interface... */
932 return;
933 }
934
935 if (odev->parent->port_spec & HSO_INFO_CRC_BUG) {
936 u32 rest;
937 u8 crc_check[4] = { 0xDE, 0xAD, 0xBE, 0xEF };
938 rest = urb->actual_length % odev->in_endp->wMaxPacketSize;
939 if (((rest == 5) || (rest == 6))
940 && !memcmp(((u8 *) urb->transfer_buffer) +
941 urb->actual_length - 4, crc_check, 4)) {
942 urb->actual_length -= 4;
943 }
944 }
945
946 /* do we even have a packet? */
947 if (urb->actual_length) {
948 /* Handle the IP stream, add header and push it onto network
949 * stack if the packet is complete. */
950 spin_lock(&odev->net_lock);
951 packetizeRx(odev, urb->transfer_buffer, urb->actual_length,
952 (urb->transfer_buffer_length >
953 urb->actual_length) ? 1 : 0);
954 spin_unlock(&odev->net_lock);
955 }
956
957 /* We are done with this URB, resubmit it. Prep the USB to wait for
958 * another frame. Reuse same as received. */
959 usb_fill_bulk_urb(urb,
960 odev->parent->usb,
961 usb_rcvbulkpipe(odev->parent->usb,
962 odev->in_endp->
963 bEndpointAddress & 0x7F),
964 urb->transfer_buffer, MUX_BULK_RX_BUF_SIZE,
965 read_bulk_callback, odev);
966
967 /* Give this to the USB subsystem so it can tell us when more data
968 * arrives. */
969 result = usb_submit_urb(urb, GFP_ATOMIC);
970 if (result)
971 dev_warn(&odev->parent->interface->dev,
972 "%s failed submit mux_bulk_rx_urb %d", __func__,
973 result);
974}
975
976/* Serial driver functions */
977
978static void _hso_serial_set_termios(struct tty_struct *tty,
979 struct ktermios *old)
980{
981 struct hso_serial *serial = get_serial_by_tty(tty);
982 struct ktermios *termios;
983
984 if ((!tty) || (!tty->termios) || (!serial)) {
985 printk(KERN_ERR "%s: no tty structures", __func__);
986 return;
987 }
988
989 D4("port %d", serial->minor);
990
991 /*
992 * The default requirements for this device are:
993 */
994 termios = tty->termios;
995 termios->c_iflag &=
996 ~(IGNBRK /* disable ignore break */
997 | BRKINT /* disable break causes interrupt */
998 | PARMRK /* disable mark parity errors */
999 | ISTRIP /* disable clear high bit of input characters */
1000 | INLCR /* disable translate NL to CR */
1001 | IGNCR /* disable ignore CR */
1002 | ICRNL /* disable translate CR to NL */
1003 | IXON); /* disable enable XON/XOFF flow control */
1004
1005 /* disable postprocess output characters */
1006 termios->c_oflag &= ~OPOST;
1007
1008 termios->c_lflag &=
1009 ~(ECHO /* disable echo input characters */
1010 | ECHONL /* disable echo new line */
1011 | ICANON /* disable erase, kill, werase, and rprnt
1012 special characters */
1013 | ISIG /* disable interrupt, quit, and suspend special
1014 characters */
1015 | IEXTEN); /* disable non-POSIX special characters */
1016
1017 termios->c_cflag &=
1018 ~(CSIZE /* no size */
1019 | PARENB /* disable parity bit */
1020 | CBAUD /* clear current baud rate */
1021 | CBAUDEX); /* clear current buad rate */
1022
1023 termios->c_cflag |= CS8; /* character size 8 bits */
1024
1025 /* baud rate 115200 */
1026 tty_encode_baud_rate(serial->tty, 115200, 115200);
1027
1028 /*
1029 * Force low_latency on; otherwise the pushes are scheduled;
1030 * this is bad as it opens up the possibility of dropping bytes
1031 * on the floor. We don't want to drop bytes on the floor. :)
1032 */
1033 serial->tty->low_latency = 1;
1034 return;
1035}
1036
1037/* open the requested serial port */
1038static int hso_serial_open(struct tty_struct *tty, struct file *filp)
1039{
1040 struct hso_serial *serial = get_serial_by_index(tty->index);
1041 int result;
1042
1043 /* sanity check */
1044 if (serial == NULL || serial->magic != HSO_SERIAL_MAGIC) {
1045 tty->driver_data = NULL;
1046 D1("Failed to open port");
1047 return -ENODEV;
1048 }
1049
1050 mutex_lock(&serial->parent->mutex);
1051 result = usb_autopm_get_interface(serial->parent->interface);
1052 if (result < 0)
1053 goto err_out;
1054
1055 D1("Opening %d", serial->minor);
1056 kref_get(&serial->parent->ref);
1057
1058 /* setup */
1059 tty->driver_data = serial;
1060 serial->tty = tty;
1061
1062 /* check for port allready opened, if not set the termios */
1063 serial->open_count++;
1064 if (serial->open_count == 1) {
1065 tty->low_latency = 1;
1066 serial->flags = 0;
1067 /* Force default termio settings */
1068 _hso_serial_set_termios(tty, NULL);
1069 result = hso_start_serial_device(serial->parent, GFP_KERNEL);
1070 if (result) {
1071 hso_stop_serial_device(serial->parent);
1072 serial->open_count--;
1073 kref_put(&serial->parent->ref, hso_serial_ref_free);
1074 }
1075 } else {
1076 D1("Port was already open");
1077 }
1078
1079 usb_autopm_put_interface(serial->parent->interface);
1080
1081 /* done */
1082 if (result)
1083 hso_serial_tiocmset(tty, NULL, TIOCM_RTS | TIOCM_DTR, 0);
1084err_out:
1085 mutex_unlock(&serial->parent->mutex);
1086 return result;
1087}
1088
1089/* close the requested serial port */
1090static void hso_serial_close(struct tty_struct *tty, struct file *filp)
1091{
1092 struct hso_serial *serial = tty->driver_data;
1093 u8 usb_gone;
1094
1095 D1("Closing serial port");
1096
1097 mutex_lock(&serial->parent->mutex);
1098 usb_gone = serial->parent->usb_gone;
1099
1100 if (!usb_gone)
1101 usb_autopm_get_interface(serial->parent->interface);
1102
1103 /* reset the rts and dtr */
1104 /* do the actual close */
1105 serial->open_count--;
1106 if (serial->open_count <= 0) {
1107 kref_put(&serial->parent->ref, hso_serial_ref_free);
1108 serial->open_count = 0;
1109 if (serial->tty) {
1110 serial->tty->driver_data = NULL;
1111 serial->tty = NULL;
1112 }
1113 if (!usb_gone)
1114 hso_stop_serial_device(serial->parent);
1115 }
1116 if (!usb_gone)
1117 usb_autopm_put_interface(serial->parent->interface);
1118 mutex_unlock(&serial->parent->mutex);
1119}
1120
1121/* close the requested serial port */
1122static int hso_serial_write(struct tty_struct *tty, const unsigned char *buf,
1123 int count)
1124{
1125 struct hso_serial *serial = get_serial_by_tty(tty);
1126 int space, tx_bytes;
1127 unsigned long flags;
1128
1129 /* sanity check */
1130 if (serial == NULL) {
1131 printk(KERN_ERR "%s: serial is NULL\n", __func__);
1132 return -ENODEV;
1133 }
1134
1135 spin_lock_irqsave(&serial->serial_lock, flags);
1136
1137 space = serial->tx_data_length - serial->tx_buffer_count;
1138 tx_bytes = (count < space) ? count : space;
1139
1140 if (!tx_bytes)
1141 goto out;
1142
1143 memcpy(serial->tx_buffer + serial->tx_buffer_count, buf, tx_bytes);
1144 serial->tx_buffer_count += tx_bytes;
1145
1146out:
1147 spin_unlock_irqrestore(&serial->serial_lock, flags);
1148
1149 hso_kick_transmit(serial);
1150 /* done */
1151 return tx_bytes;
1152}
1153
1154/* how much room is there for writing */
1155static int hso_serial_write_room(struct tty_struct *tty)
1156{
1157 struct hso_serial *serial = get_serial_by_tty(tty);
1158 int room;
1159 unsigned long flags;
1160
1161 spin_lock_irqsave(&serial->serial_lock, flags);
1162 room = serial->tx_data_length - serial->tx_buffer_count;
1163 spin_unlock_irqrestore(&serial->serial_lock, flags);
1164
1165 /* return free room */
1166 return room;
1167}
1168
1169/* setup the term */
1170static void hso_serial_set_termios(struct tty_struct *tty, struct ktermios *old)
1171{
1172 struct hso_serial *serial = get_serial_by_tty(tty);
1173 unsigned long flags;
1174
1175 if (old)
1176 D5("Termios called with: cflags new[%d] - old[%d]",
1177 tty->termios->c_cflag, old->c_cflag);
1178
1179 /* the actual setup */
1180 spin_lock_irqsave(&serial->serial_lock, flags);
1181 if (serial->open_count)
1182 _hso_serial_set_termios(tty, old);
1183 else
1184 tty->termios = old;
1185 spin_unlock_irqrestore(&serial->serial_lock, flags);
1186
1187 /* done */
1188 return;
1189}
1190
1191/* how many characters in the buffer */
1192static int hso_serial_chars_in_buffer(struct tty_struct *tty)
1193{
1194 struct hso_serial *serial = get_serial_by_tty(tty);
1195 int chars;
1196 unsigned long flags;
1197
1198 /* sanity check */
1199 if (serial == NULL)
1200 return 0;
1201
1202 spin_lock_irqsave(&serial->serial_lock, flags);
1203 chars = serial->tx_buffer_count;
1204 spin_unlock_irqrestore(&serial->serial_lock, flags);
1205
1206 return chars;
1207}
1208
1209static int hso_serial_tiocmget(struct tty_struct *tty, struct file *file)
1210{
1211 unsigned int value;
1212 struct hso_serial *serial = get_serial_by_tty(tty);
1213 unsigned long flags;
1214
1215 /* sanity check */
1216 if (!serial) {
1217 D1("no tty structures");
1218 return -EINVAL;
1219 }
1220
1221 spin_lock_irqsave(&serial->serial_lock, flags);
1222 value = ((serial->rts_state) ? TIOCM_RTS : 0) |
1223 ((serial->dtr_state) ? TIOCM_DTR : 0);
1224 spin_unlock_irqrestore(&serial->serial_lock, flags);
1225
1226 return value;
1227}
1228
1229static int hso_serial_tiocmset(struct tty_struct *tty, struct file *file,
1230 unsigned int set, unsigned int clear)
1231{
1232 int val = 0;
1233 unsigned long flags;
1234 int if_num;
1235 struct hso_serial *serial = get_serial_by_tty(tty);
1236
1237 /* sanity check */
1238 if (!serial) {
1239 D1("no tty structures");
1240 return -EINVAL;
1241 }
1242 if_num = serial->parent->interface->altsetting->desc.bInterfaceNumber;
1243
1244 spin_lock_irqsave(&serial->serial_lock, flags);
1245 if (set & TIOCM_RTS)
1246 serial->rts_state = 1;
1247 if (set & TIOCM_DTR)
1248 serial->dtr_state = 1;
1249
1250 if (clear & TIOCM_RTS)
1251 serial->rts_state = 0;
1252 if (clear & TIOCM_DTR)
1253 serial->dtr_state = 0;
1254
1255 if (serial->dtr_state)
1256 val |= 0x01;
1257 if (serial->rts_state)
1258 val |= 0x02;
1259
1260 spin_unlock_irqrestore(&serial->serial_lock, flags);
1261
1262 return usb_control_msg(serial->parent->usb,
1263 usb_rcvctrlpipe(serial->parent->usb, 0), 0x22,
1264 0x21, val, if_num, NULL, 0,
1265 USB_CTRL_SET_TIMEOUT);
1266}
1267
1268/* starts a transmit */
1269static void hso_kick_transmit(struct hso_serial *serial)
1270{
1271 u8 *temp;
1272 unsigned long flags;
1273 int res;
1274
1275 spin_lock_irqsave(&serial->serial_lock, flags);
1276 if (!serial->tx_buffer_count)
1277 goto out;
1278
1279 if (serial->tx_urb_used)
1280 goto out;
1281
1282 /* Wakeup USB interface if necessary */
1283 if (hso_get_activity(serial->parent) == -EAGAIN)
1284 goto out;
1285
1286 /* Switch pointers around to avoid memcpy */
1287 temp = serial->tx_buffer;
1288 serial->tx_buffer = serial->tx_data;
1289 serial->tx_data = temp;
1290 serial->tx_data_count = serial->tx_buffer_count;
1291 serial->tx_buffer_count = 0;
1292
1293 /* If temp is set, it means we switched buffers */
1294 if (temp && serial->write_data) {
1295 res = serial->write_data(serial);
1296 if (res >= 0)
1297 serial->tx_urb_used = 1;
1298 }
1299out:
1300 spin_unlock_irqrestore(&serial->serial_lock, flags);
1301}
1302
1303/* make a request (for reading and writing data to muxed serial port) */
1304static int mux_device_request(struct hso_serial *serial, u8 type, u16 port,
1305 struct urb *ctrl_urb,
1306 struct usb_ctrlrequest *ctrl_req,
1307 u8 *ctrl_urb_data, u32 size)
1308{
1309 int result;
1310 int pipe;
1311
1312 /* Sanity check */
1313 if (!serial || !ctrl_urb || !ctrl_req) {
1314 printk(KERN_ERR "%s: Wrong arguments\n", __func__);
1315 return -EINVAL;
1316 }
1317
1318 /* initialize */
1319 ctrl_req->wValue = 0;
1320 ctrl_req->wIndex = hso_port_to_mux(port);
1321 ctrl_req->wLength = size;
1322
1323 if (type == USB_CDC_GET_ENCAPSULATED_RESPONSE) {
1324 /* Reading command */
1325 ctrl_req->bRequestType = USB_DIR_IN |
1326 USB_TYPE_OPTION_VENDOR |
1327 USB_RECIP_INTERFACE;
1328 ctrl_req->bRequest = USB_CDC_GET_ENCAPSULATED_RESPONSE;
1329 pipe = usb_rcvctrlpipe(serial->parent->usb, 0);
1330 } else {
1331 /* Writing command */
1332 ctrl_req->bRequestType = USB_DIR_OUT |
1333 USB_TYPE_OPTION_VENDOR |
1334 USB_RECIP_INTERFACE;
1335 ctrl_req->bRequest = USB_CDC_SEND_ENCAPSULATED_COMMAND;
1336 pipe = usb_sndctrlpipe(serial->parent->usb, 0);
1337 }
1338 /* syslog */
1339 D2("%s command (%02x) len: %d, port: %d",
1340 type == USB_CDC_GET_ENCAPSULATED_RESPONSE ? "Read" : "Write",
1341 ctrl_req->bRequestType, ctrl_req->wLength, port);
1342
1343 /* Load ctrl urb */
1344 ctrl_urb->transfer_flags = 0;
1345 usb_fill_control_urb(ctrl_urb,
1346 serial->parent->usb,
1347 pipe,
1348 (u8 *) ctrl_req,
1349 ctrl_urb_data, size, ctrl_callback, serial);
1350 /* Send it on merry way */
1351 result = usb_submit_urb(ctrl_urb, GFP_ATOMIC);
1352 if (result) {
1353 dev_err(&ctrl_urb->dev->dev,
1354 "%s failed submit ctrl_urb %d type %d", __func__,
1355 result, type);
1356 return result;
1357 }
1358
1359 /* done */
1360 return size;
1361}
1362
1363/* called by intr_callback when read occurs */
1364static int hso_mux_serial_read(struct hso_serial *serial)
1365{
1366 if (!serial)
1367 return -EINVAL;
1368
1369 /* clean data */
1370 memset(serial->rx_data[0], 0, CTRL_URB_RX_SIZE);
1371 /* make the request */
1372
1373 if (serial->num_rx_urbs != 1) {
1374 dev_err(&serial->parent->interface->dev,
1375 "ERROR: mux'd reads with multiple buffers "
1376 "not possible\n");
1377 return 0;
1378 }
1379 return mux_device_request(serial,
1380 USB_CDC_GET_ENCAPSULATED_RESPONSE,
1381 serial->parent->port_spec & HSO_PORT_MASK,
1382 serial->rx_urb[0],
1383 &serial->ctrl_req_rx,
1384 serial->rx_data[0], serial->rx_data_length);
1385}
1386
1387/* used for muxed serial port callback (muxed serial read) */
1388static void intr_callback(struct urb *urb)
1389{
1390 struct hso_shared_int *shared_int = urb->context;
1391 struct hso_serial *serial;
1392 unsigned char *port_req;
1393 int status = urb->status;
1394 int i;
1395
1396 usb_mark_last_busy(urb->dev);
1397
1398 /* sanity check */
1399 if (!shared_int)
1400 return;
1401
1402 /* status check */
1403 if (status) {
1404 log_usb_status(status, __func__);
1405 return;
1406 }
1407 D4("\n--- Got intr callback 0x%02X ---", status);
1408
1409 /* what request? */
1410 port_req = urb->transfer_buffer;
1411 D4(" port_req = 0x%.2X\n", *port_req);
1412 /* loop over all muxed ports to find the one sending this */
1413 for (i = 0; i < 8; i++) {
1414 /* max 8 channels on MUX */
1415 if (*port_req & (1 << i)) {
1416 serial = get_serial_by_shared_int_and_type(shared_int,
1417 (1 << i));
1418 if (serial != NULL) {
1419 D1("Pending read interrupt on port %d\n", i);
1420 if (!test_and_set_bit(HSO_SERIAL_FLAG_RX_SENT,
1421 &serial->flags)) {
1422 /* Setup and send a ctrl req read on
1423 * port i */
1424 hso_mux_serial_read(serial);
1425 } else {
1426 D1("Already pending a read on "
1427 "port %d\n", i);
1428 }
1429 }
1430 }
1431 }
1432 /* Resubmit interrupt urb */
1433 hso_mux_submit_intr_urb(shared_int, urb->dev, GFP_ATOMIC);
1434}
1435
1436/* called for writing to muxed serial port */
1437static int hso_mux_serial_write_data(struct hso_serial *serial)
1438{
1439 if (NULL == serial)
1440 return -EINVAL;
1441
1442 return mux_device_request(serial,
1443 USB_CDC_SEND_ENCAPSULATED_COMMAND,
1444 serial->parent->port_spec & HSO_PORT_MASK,
1445 serial->tx_urb,
1446 &serial->ctrl_req_tx,
1447 serial->tx_data, serial->tx_data_count);
1448}
1449
1450/* write callback for Diag and CS port */
1451static void hso_std_serial_write_bulk_callback(struct urb *urb)
1452{
1453 struct hso_serial *serial = urb->context;
1454 int status = urb->status;
1455
1456 /* sanity check */
1457 if (!serial) {
1458 D1("serial == NULL");
1459 return;
1460 }
1461
1462 spin_lock(&serial->serial_lock);
1463 serial->tx_urb_used = 0;
1464 spin_unlock(&serial->serial_lock);
1465 if (status) {
1466 log_usb_status(status, __func__);
1467 return;
1468 }
1469 hso_put_activity(serial->parent);
1470 tty_wakeup(serial->tty);
1471 hso_kick_transmit(serial);
1472
1473 D1(" ");
1474 return;
1475}
1476
1477/* called for writing diag or CS serial port */
1478static int hso_std_serial_write_data(struct hso_serial *serial)
1479{
1480 int count = serial->tx_data_count;
1481 int result;
1482
1483 usb_fill_bulk_urb(serial->tx_urb,
1484 serial->parent->usb,
1485 usb_sndbulkpipe(serial->parent->usb,
1486 serial->out_endp->
1487 bEndpointAddress & 0x7F),
1488 serial->tx_data, serial->tx_data_count,
1489 hso_std_serial_write_bulk_callback, serial);
1490
1491 result = usb_submit_urb(serial->tx_urb, GFP_ATOMIC);
1492 if (result) {
1493 dev_warn(&serial->parent->usb->dev,
1494 "Failed to submit urb - res %d\n", result);
1495 return result;
1496 }
1497
1498 return count;
1499}
1500
1501/* callback after read or write on muxed serial port */
1502static void ctrl_callback(struct urb *urb)
1503{
1504 struct hso_serial *serial = urb->context;
1505 struct usb_ctrlrequest *req;
1506 int status = urb->status;
1507
1508 /* sanity check */
1509 if (!serial)
1510 return;
1511
1512 spin_lock(&serial->serial_lock);
1513 serial->tx_urb_used = 0;
1514 spin_unlock(&serial->serial_lock);
1515 if (status) {
1516 log_usb_status(status, __func__);
1517 return;
1518 }
1519
1520 /* what request? */
1521 req = (struct usb_ctrlrequest *)(urb->setup_packet);
1522 D4("\n--- Got muxed ctrl callback 0x%02X ---", status);
1523 D4("Actual length of urb = %d\n", urb->actual_length);
1524 DUMP1(urb->transfer_buffer, urb->actual_length);
1525
1526 if (req->bRequestType ==
1527 (USB_DIR_IN | USB_TYPE_OPTION_VENDOR | USB_RECIP_INTERFACE)) {
1528 /* response to a read command */
1529 if (serial->open_count > 0) {
1530 /* handle RX data the normal way */
1531 put_rxbuf_data(urb, serial);
1532 }
1533
1534 /* Re issue a read as long as we receive data. */
1535 if (urb->actual_length != 0)
1536 hso_mux_serial_read(serial);
1537 else
1538 clear_bit(HSO_SERIAL_FLAG_RX_SENT, &serial->flags);
1539 } else {
1540 hso_put_activity(serial->parent);
1541 tty_wakeup(serial->tty);
1542 /* response to a write command */
1543 hso_kick_transmit(serial);
1544 }
1545}
1546
1547/* handle RX data for serial port */
1548static void put_rxbuf_data(struct urb *urb, struct hso_serial *serial)
1549{
1550 struct tty_struct *tty = serial->tty;
1551
1552 /* Sanity check */
1553 if (urb == NULL || serial == NULL) {
1554 D1("serial = NULL");
1555 return;
1556 }
1557
1558 /* Push data to tty */
1559 if (tty && urb->actual_length) {
1560 D1("data to push to tty");
1561 tty_insert_flip_string(tty, urb->transfer_buffer,
1562 urb->actual_length);
1563 tty_flip_buffer_push(tty);
1564 }
1565}
1566
1567/* read callback for Diag and CS port */
1568static void hso_std_serial_read_bulk_callback(struct urb *urb)
1569{
1570 struct hso_serial *serial = urb->context;
1571 int result;
1572 int status = urb->status;
1573
1574 /* sanity check */
1575 if (!serial) {
1576 D1("serial == NULL");
1577 return;
1578 } else if (status) {
1579 log_usb_status(status, __func__);
1580 return;
1581 }
1582
1583 D4("\n--- Got serial_read_bulk callback %02x ---", status);
1584 D1("Actual length = %d\n", urb->actual_length);
1585 DUMP1(urb->transfer_buffer, urb->actual_length);
1586
1587 /* Anyone listening? */
1588 if (serial->open_count == 0)
1589 return;
1590
1591 if (status == 0) {
1592 if (serial->parent->port_spec & HSO_INFO_CRC_BUG) {
1593 u32 rest;
1594 u8 crc_check[4] = { 0xDE, 0xAD, 0xBE, 0xEF };
1595 rest =
1596 urb->actual_length %
1597 serial->in_endp->wMaxPacketSize;
1598 if (((rest == 5) || (rest == 6))
1599 && !memcmp(((u8 *) urb->transfer_buffer) +
1600 urb->actual_length - 4, crc_check, 4)) {
1601 urb->actual_length -= 4;
1602 }
1603 }
1604 /* Valid data, handle RX data */
1605 put_rxbuf_data(urb, serial);
1606 } else if (status == -ENOENT || status == -ECONNRESET) {
1607 /* Unlinked - check for throttled port. */
1608 D2("Port %d, successfully unlinked urb", serial->minor);
1609 } else {
1610 D2("Port %d, status = %d for read urb", serial->minor, status);
1611 return;
1612 }
1613
1614 usb_mark_last_busy(urb->dev);
1615
1616 /* We are done with this URB, resubmit it. Prep the USB to wait for
1617 * another frame */
1618 usb_fill_bulk_urb(urb, serial->parent->usb,
1619 usb_rcvbulkpipe(serial->parent->usb,
1620 serial->in_endp->
1621 bEndpointAddress & 0x7F),
1622 urb->transfer_buffer, serial->rx_data_length,
1623 hso_std_serial_read_bulk_callback, serial);
1624 /* Give this to the USB subsystem so it can tell us when more data
1625 * arrives. */
1626 result = usb_submit_urb(urb, GFP_ATOMIC);
1627 if (result) {
1628 dev_err(&urb->dev->dev, "%s failed submit serial rx_urb %d",
1629 __func__, result);
1630 }
1631}
1632
1633/* Base driver functions */
1634
1635static void hso_log_port(struct hso_device *hso_dev)
1636{
1637 char *port_type;
1638 char port_dev[20];
1639
1640 switch (hso_dev->port_spec & HSO_PORT_MASK) {
1641 case HSO_PORT_CONTROL:
1642 port_type = "Control";
1643 break;
1644 case HSO_PORT_APP:
1645 port_type = "Application";
1646 break;
1647 case HSO_PORT_GPS:
1648 port_type = "GPS";
1649 break;
1650 case HSO_PORT_GPS_CONTROL:
1651 port_type = "GPS control";
1652 break;
1653 case HSO_PORT_APP2:
1654 port_type = "Application2";
1655 break;
1656 case HSO_PORT_PCSC:
1657 port_type = "PCSC";
1658 break;
1659 case HSO_PORT_DIAG:
1660 port_type = "Diagnostic";
1661 break;
1662 case HSO_PORT_DIAG2:
1663 port_type = "Diagnostic2";
1664 break;
1665 case HSO_PORT_MODEM:
1666 port_type = "Modem";
1667 break;
1668 case HSO_PORT_NETWORK:
1669 port_type = "Network";
1670 break;
1671 default:
1672 port_type = "Unknown";
1673 break;
1674 }
1675 if ((hso_dev->port_spec & HSO_PORT_MASK) == HSO_PORT_NETWORK) {
1676 sprintf(port_dev, "%s", dev2net(hso_dev)->net->name);
1677 } else
1678 sprintf(port_dev, "/dev/%s%d", tty_filename,
1679 dev2ser(hso_dev)->minor);
1680
1681 dev_dbg(&hso_dev->interface->dev, "HSO: Found %s port %s\n",
1682 port_type, port_dev);
1683}
1684
1685static int hso_start_net_device(struct hso_device *hso_dev)
1686{
1687 int i, result = 0;
1688 struct hso_net *hso_net = dev2net(hso_dev);
1689
1690 if (!hso_net)
1691 return -ENODEV;
1692
1693 /* send URBs for all read buffers */
1694 for (i = 0; i < MUX_BULK_RX_BUF_COUNT; i++) {
1695
1696 /* Prep a receive URB */
1697 usb_fill_bulk_urb(hso_net->mux_bulk_rx_urb_pool[i],
1698 hso_dev->usb,
1699 usb_rcvbulkpipe(hso_dev->usb,
1700 hso_net->in_endp->
1701 bEndpointAddress & 0x7F),
1702 hso_net->mux_bulk_rx_buf_pool[i],
1703 MUX_BULK_RX_BUF_SIZE, read_bulk_callback,
1704 hso_net);
1705
1706 /* Put it out there so the device can send us stuff */
1707 result = usb_submit_urb(hso_net->mux_bulk_rx_urb_pool[i],
1708 GFP_NOIO);
1709 if (result)
1710 dev_warn(&hso_dev->usb->dev,
1711 "%s failed mux_bulk_rx_urb[%d] %d\n", __func__,
1712 i, result);
1713 }
1714
1715 return result;
1716}
1717
1718static int hso_stop_net_device(struct hso_device *hso_dev)
1719{
1720 int i;
1721 struct hso_net *hso_net = dev2net(hso_dev);
1722
1723 if (!hso_net)
1724 return -ENODEV;
1725
1726 for (i = 0; i < MUX_BULK_RX_BUF_COUNT; i++) {
1727 if (hso_net->mux_bulk_rx_urb_pool[i])
1728 usb_kill_urb(hso_net->mux_bulk_rx_urb_pool[i]);
1729
1730 }
1731 if (hso_net->mux_bulk_tx_urb)
1732 usb_kill_urb(hso_net->mux_bulk_tx_urb);
1733
1734 return 0;
1735}
1736
1737static int hso_start_serial_device(struct hso_device *hso_dev, gfp_t flags)
1738{
1739 int i, result = 0;
1740 struct hso_serial *serial = dev2ser(hso_dev);
1741
1742 if (!serial)
1743 return -ENODEV;
1744
1745 /* If it is not the MUX port fill in and submit a bulk urb (already
1746 * allocated in hso_serial_start) */
1747 if (!(serial->parent->port_spec & HSO_INTF_MUX)) {
1748 for (i = 0; i < serial->num_rx_urbs; i++) {
1749 usb_fill_bulk_urb(serial->rx_urb[i],
1750 serial->parent->usb,
1751 usb_rcvbulkpipe(serial->parent->usb,
1752 serial->in_endp->
1753 bEndpointAddress &
1754 0x7F),
1755 serial->rx_data[i],
1756 serial->rx_data_length,
1757 hso_std_serial_read_bulk_callback,
1758 serial);
1759 result = usb_submit_urb(serial->rx_urb[i], flags);
1760 if (result) {
1761 dev_warn(&serial->parent->usb->dev,
1762 "Failed to submit urb - res %d\n",
1763 result);
1764 break;
1765 }
1766 }
1767 } else {
1768 mutex_lock(&serial->shared_int->shared_int_lock);
1769 if (!serial->shared_int->use_count) {
1770 result =
1771 hso_mux_submit_intr_urb(serial->shared_int,
1772 hso_dev->usb, flags);
1773 }
1774 serial->shared_int->use_count++;
1775 mutex_unlock(&serial->shared_int->shared_int_lock);
1776 }
1777
1778 return result;
1779}
1780
1781static int hso_stop_serial_device(struct hso_device *hso_dev)
1782{
1783 int i;
1784 struct hso_serial *serial = dev2ser(hso_dev);
1785
1786 if (!serial)
1787 return -ENODEV;
1788
1789 for (i = 0; i < serial->num_rx_urbs; i++) {
1790 if (serial->rx_urb[i])
1791 usb_kill_urb(serial->rx_urb[i]);
1792 }
1793
1794 if (serial->tx_urb)
1795 usb_kill_urb(serial->tx_urb);
1796
1797 if (serial->shared_int) {
1798 mutex_lock(&serial->shared_int->shared_int_lock);
1799 if (serial->shared_int->use_count &&
1800 (--serial->shared_int->use_count == 0)) {
1801 struct urb *urb;
1802
1803 urb = serial->shared_int->shared_intr_urb;
1804 if (urb)
1805 usb_kill_urb(urb);
1806 }
1807 mutex_unlock(&serial->shared_int->shared_int_lock);
1808 }
1809
1810 return 0;
1811}
1812
1813static void hso_serial_common_free(struct hso_serial *serial)
1814{
1815 int i;
1816
1817 if (serial->parent->dev)
1818 device_remove_file(serial->parent->dev, &dev_attr_hsotype);
1819
1820 tty_unregister_device(tty_drv, serial->minor);
1821
1822 for (i = 0; i < serial->num_rx_urbs; i++) {
1823 /* unlink and free RX URB */
1824 usb_free_urb(serial->rx_urb[i]);
1825 /* free the RX buffer */
1826 kfree(serial->rx_data[i]);
1827 }
1828
1829 /* unlink and free TX URB */
1830 usb_free_urb(serial->tx_urb);
1831 kfree(serial->tx_data);
1832}
1833
1834static int hso_serial_common_create(struct hso_serial *serial, int num_urbs,
1835 int rx_size, int tx_size)
1836{
1837 struct device *dev;
1838 int minor;
1839 int i;
1840
1841 minor = get_free_serial_index();
1842 if (minor < 0)
1843 goto exit;
1844
1845 /* register our minor number */
1846 serial->parent->dev = tty_register_device(tty_drv, minor,
1847 &serial->parent->interface->dev);
1848 dev = serial->parent->dev;
1849 dev->driver_data = serial->parent;
1850 i = device_create_file(dev, &dev_attr_hsotype);
1851
1852 /* fill in specific data for later use */
1853 serial->minor = minor;
1854 serial->magic = HSO_SERIAL_MAGIC;
1855 spin_lock_init(&serial->serial_lock);
1856 serial->num_rx_urbs = num_urbs;
1857
1858 /* RX, allocate urb and initialize */
1859
1860 /* prepare our RX buffer */
1861 serial->rx_data_length = rx_size;
1862 for (i = 0; i < serial->num_rx_urbs; i++) {
1863 serial->rx_urb[i] = usb_alloc_urb(0, GFP_KERNEL);
1864 if (!serial->rx_urb[i]) {
1865 dev_err(dev, "Could not allocate urb?\n");
1866 goto exit;
1867 }
1868 serial->rx_urb[i]->transfer_buffer = NULL;
1869 serial->rx_urb[i]->transfer_buffer_length = 0;
1870 serial->rx_data[i] = kzalloc(serial->rx_data_length,
1871 GFP_KERNEL);
1872 if (!serial->rx_data[i]) {
1873 dev_err(dev, "%s - Out of memory\n", __func__);
1874 goto exit;
1875 }
1876 }
1877
1878 /* TX, allocate urb and initialize */
1879 serial->tx_urb = usb_alloc_urb(0, GFP_KERNEL);
1880 if (!serial->tx_urb) {
1881 dev_err(dev, "Could not allocate urb?\n");
1882 goto exit;
1883 }
1884 serial->tx_urb->transfer_buffer = NULL;
1885 serial->tx_urb->transfer_buffer_length = 0;
1886 /* prepare our TX buffer */
1887 serial->tx_data_count = 0;
1888 serial->tx_buffer_count = 0;
1889 serial->tx_data_length = tx_size;
1890 serial->tx_data = kzalloc(serial->tx_data_length, GFP_KERNEL);
1891 if (!serial->tx_data) {
1892 dev_err(dev, "%s - Out of memory", __func__);
1893 goto exit;
1894 }
1895 serial->tx_buffer = kzalloc(serial->tx_data_length, GFP_KERNEL);
1896 if (!serial->tx_buffer) {
1897 dev_err(dev, "%s - Out of memory", __func__);
1898 goto exit;
1899 }
1900
1901 return 0;
1902exit:
1903 hso_serial_common_free(serial);
1904 return -1;
1905}
1906
1907/* Frees a general hso device */
1908static void hso_free_device(struct hso_device *hso_dev)
1909{
1910 kfree(hso_dev);
1911}
1912
1913/* Creates a general hso device */
1914static struct hso_device *hso_create_device(struct usb_interface *intf,
1915 int port_spec)
1916{
1917 struct hso_device *hso_dev;
1918
1919 hso_dev = kzalloc(sizeof(*hso_dev), GFP_ATOMIC);
1920 if (!hso_dev)
1921 return NULL;
1922
1923 hso_dev->port_spec = port_spec;
1924 hso_dev->usb = interface_to_usbdev(intf);
1925 hso_dev->interface = intf;
1926 kref_init(&hso_dev->ref);
1927 mutex_init(&hso_dev->mutex);
1928
1929 INIT_WORK(&hso_dev->async_get_intf, async_get_intf);
1930 INIT_WORK(&hso_dev->async_put_intf, async_put_intf);
1931
1932 return hso_dev;
1933}
1934
1935/* Removes a network device in the network device table */
1936static int remove_net_device(struct hso_device *hso_dev)
1937{
1938 int i;
1939
1940 for (i = 0; i < HSO_MAX_NET_DEVICES; i++) {
1941 if (network_table[i] == hso_dev) {
1942 network_table[i] = NULL;
1943 break;
1944 }
1945 }
1946 if (i == HSO_MAX_NET_DEVICES)
1947 return -1;
1948 return 0;
1949}
1950
1951/* Frees our network device */
1952static void hso_free_net_device(struct hso_device *hso_dev)
1953{
1954 int i;
1955 struct hso_net *hso_net = dev2net(hso_dev);
1956
1957 if (!hso_net)
1958 return;
1959
1960 /* start freeing */
1961 for (i = 0; i < MUX_BULK_RX_BUF_COUNT; i++) {
1962 usb_free_urb(hso_net->mux_bulk_rx_urb_pool[i]);
1963 kfree(hso_net->mux_bulk_rx_buf_pool[i]);
1964 }
1965 usb_free_urb(hso_net->mux_bulk_tx_urb);
1966 kfree(hso_net->mux_bulk_tx_buf);
1967
1968 remove_net_device(hso_net->parent);
1969
1970 if (hso_net->net) {
1971 unregister_netdev(hso_net->net);
1972 free_netdev(hso_net->net);
1973 }
1974
1975 hso_free_device(hso_dev);
1976}
1977
1978/* initialize the network interface */
1979static void hso_net_init(struct net_device *net)
1980{
1981 struct hso_net *hso_net = netdev_priv(net);
1982
1983 D1("sizeof hso_net is %d", (int)sizeof(*hso_net));
1984
1985 /* fill in the other fields */
1986 net->open = hso_net_open;
1987 net->stop = hso_net_close;
1988 net->hard_start_xmit = hso_net_start_xmit;
1989 net->tx_timeout = hso_net_tx_timeout;
1990 net->watchdog_timeo = HSO_NET_TX_TIMEOUT;
1991 net->flags = IFF_POINTOPOINT | IFF_NOARP | IFF_MULTICAST;
1992 net->type = ARPHRD_NONE;
1993 net->mtu = DEFAULT_MTU - 14;
1994 net->tx_queue_len = 10;
1995 SET_ETHTOOL_OPS(net, &ops);
1996
1997 /* and initialize the semaphore */
1998 spin_lock_init(&hso_net->net_lock);
1999}
2000
2001/* Adds a network device in the network device table */
2002static int add_net_device(struct hso_device *hso_dev)
2003{
2004 int i;
2005
2006 for (i = 0; i < HSO_MAX_NET_DEVICES; i++) {
2007 if (network_table[i] == NULL) {
2008 network_table[i] = hso_dev;
2009 break;
2010 }
2011 }
2012 if (i == HSO_MAX_NET_DEVICES)
2013 return -1;
2014 return 0;
2015}
2016
2017static int hso_radio_toggle(void *data, enum rfkill_state state)
2018{
2019 struct hso_device *hso_dev = data;
2020 int enabled = (state == RFKILL_STATE_ON);
2021 int rv;
2022
2023 mutex_lock(&hso_dev->mutex);
2024 if (hso_dev->usb_gone)
2025 rv = 0;
2026 else
2027 rv = usb_control_msg(hso_dev->usb, usb_rcvctrlpipe(hso_dev->usb, 0),
2028 enabled ? 0x82 : 0x81, 0x40, 0, 0, NULL, 0,
2029 USB_CTRL_SET_TIMEOUT);
2030 mutex_unlock(&hso_dev->mutex);
2031 return rv;
2032}
2033
2034/* Creates and sets up everything for rfkill */
2035static void hso_create_rfkill(struct hso_device *hso_dev,
2036 struct usb_interface *interface)
2037{
2038 struct hso_net *hso_net = dev2net(hso_dev);
2039 struct device *dev = hso_dev->dev;
2040 char *rfkn;
2041
2042 hso_net->rfkill = rfkill_allocate(&interface_to_usbdev(interface)->dev,
2043 RFKILL_TYPE_WLAN);
2044 if (!hso_net->rfkill) {
2045 dev_err(dev, "%s - Out of memory", __func__);
2046 return;
2047 }
2048 rfkn = kzalloc(20, GFP_KERNEL);
2049 if (!rfkn) {
2050 rfkill_free(hso_net->rfkill);
2051 dev_err(dev, "%s - Out of memory", __func__);
2052 return;
2053 }
2054 snprintf(rfkn, 20, "hso-%d",
2055 interface->altsetting->desc.bInterfaceNumber);
2056 hso_net->rfkill->name = rfkn;
2057 hso_net->rfkill->state = RFKILL_STATE_ON;
2058 hso_net->rfkill->data = hso_dev;
2059 hso_net->rfkill->toggle_radio = hso_radio_toggle;
2060 if (rfkill_register(hso_net->rfkill) < 0) {
2061 kfree(rfkn);
2062 hso_net->rfkill->name = NULL;
2063 rfkill_free(hso_net->rfkill);
2064 dev_err(dev, "%s - Failed to register rfkill", __func__);
2065 return;
2066 }
2067}
2068
2069/* Creates our network device */
2070static struct hso_device *hso_create_net_device(struct usb_interface *interface)
2071{
2072 int result, i;
2073 struct net_device *net;
2074 struct hso_net *hso_net;
2075 struct hso_device *hso_dev;
2076
2077 hso_dev = hso_create_device(interface, HSO_INTF_MUX | HSO_PORT_NETWORK);
2078 if (!hso_dev)
2079 return NULL;
2080
2081 /* allocate our network device, then we can put in our private data */
2082 /* call hso_net_init to do the basic initialization */
2083 net = alloc_netdev(sizeof(struct hso_net), "hso%d", hso_net_init);
2084 if (!net) {
2085 dev_err(&interface->dev, "Unable to create ethernet device\n");
2086 goto exit;
2087 }
2088
2089 hso_net = netdev_priv(net);
2090
2091 hso_dev->port_data.dev_net = hso_net;
2092 hso_net->net = net;
2093 hso_net->parent = hso_dev;
2094
2095 hso_net->in_endp = hso_get_ep(interface, USB_ENDPOINT_XFER_BULK,
2096 USB_DIR_IN);
2097 if (!hso_net->in_endp) {
2098 dev_err(&interface->dev, "Can't find BULK IN endpoint\n");
2099 goto exit;
2100 }
2101 hso_net->out_endp = hso_get_ep(interface, USB_ENDPOINT_XFER_BULK,
2102 USB_DIR_OUT);
2103 if (!hso_net->out_endp) {
2104 dev_err(&interface->dev, "Can't find BULK OUT endpoint\n");
2105 goto exit;
2106 }
2107 SET_NETDEV_DEV(net, &interface->dev);
2108
2109 /* registering our net device */
2110 result = register_netdev(net);
2111 if (result) {
2112 dev_err(&interface->dev, "Failed to register device\n");
2113 goto exit;
2114 }
2115
2116 /* start allocating */
2117 for (i = 0; i < MUX_BULK_RX_BUF_COUNT; i++) {
2118 hso_net->mux_bulk_rx_urb_pool[i] = usb_alloc_urb(0, GFP_KERNEL);
2119 if (!hso_net->mux_bulk_rx_urb_pool[i]) {
2120 dev_err(&interface->dev, "Could not allocate rx urb\n");
2121 goto exit;
2122 }
2123 hso_net->mux_bulk_rx_buf_pool[i] = kzalloc(MUX_BULK_RX_BUF_SIZE,
2124 GFP_KERNEL);
2125 if (!hso_net->mux_bulk_rx_buf_pool[i]) {
2126 dev_err(&interface->dev, "Could not allocate rx buf\n");
2127 goto exit;
2128 }
2129 }
2130 hso_net->mux_bulk_tx_urb = usb_alloc_urb(0, GFP_KERNEL);
2131 if (!hso_net->mux_bulk_tx_urb) {
2132 dev_err(&interface->dev, "Could not allocate tx urb\n");
2133 goto exit;
2134 }
2135 hso_net->mux_bulk_tx_buf = kzalloc(MUX_BULK_TX_BUF_SIZE, GFP_KERNEL);
2136 if (!hso_net->mux_bulk_tx_buf) {
2137 dev_err(&interface->dev, "Could not allocate tx buf\n");
2138 goto exit;
2139 }
2140
2141 add_net_device(hso_dev);
2142
2143 hso_log_port(hso_dev);
2144
2145 hso_create_rfkill(hso_dev, interface);
2146
2147 return hso_dev;
2148exit:
2149 hso_free_net_device(hso_dev);
2150 return NULL;
2151}
2152
2153/* Frees an AT channel ( goes for both mux and non-mux ) */
2154static void hso_free_serial_device(struct hso_device *hso_dev)
2155{
2156 struct hso_serial *serial = dev2ser(hso_dev);
2157
2158 if (!serial)
2159 return;
2160 set_serial_by_index(serial->minor, NULL);
2161
2162 hso_serial_common_free(serial);
2163
2164 if (serial->shared_int) {
2165 mutex_lock(&serial->shared_int->shared_int_lock);
2166 if (--serial->shared_int->ref_count == 0)
2167 hso_free_shared_int(serial->shared_int);
2168 else
2169 mutex_unlock(&serial->shared_int->shared_int_lock);
2170 }
2171 kfree(serial);
2172 hso_free_device(hso_dev);
2173}
2174
2175/* Creates a bulk AT channel */
2176static struct hso_device *hso_create_bulk_serial_device(
2177 struct usb_interface *interface, int port)
2178{
2179 struct hso_device *hso_dev;
2180 struct hso_serial *serial;
2181 int num_urbs;
2182
2183 hso_dev = hso_create_device(interface, port);
2184 if (!hso_dev)
2185 return NULL;
2186
2187 serial = kzalloc(sizeof(*serial), GFP_KERNEL);
2188 if (!serial)
2189 goto exit;
2190
2191 serial->parent = hso_dev;
2192 hso_dev->port_data.dev_serial = serial;
2193
2194 if (port & HSO_PORT_MODEM)
2195 num_urbs = 2;
2196 else
2197 num_urbs = 1;
2198
2199 if (hso_serial_common_create(serial, num_urbs, BULK_URB_RX_SIZE,
2200 BULK_URB_TX_SIZE))
2201 goto exit;
2202
2203 serial->in_endp = hso_get_ep(interface, USB_ENDPOINT_XFER_BULK,
2204 USB_DIR_IN);
2205 if (!serial->in_endp) {
2206 dev_err(&interface->dev, "Failed to find BULK IN ep\n");
2207 goto exit;
2208 }
2209
2210 if (!
2211 (serial->out_endp =
2212 hso_get_ep(interface, USB_ENDPOINT_XFER_BULK, USB_DIR_OUT))) {
2213 dev_err(&interface->dev, "Failed to find BULK IN ep\n");
2214 goto exit;
2215 }
2216
2217 serial->write_data = hso_std_serial_write_data;
2218
2219 /* and record this serial */
2220 set_serial_by_index(serial->minor, serial);
2221
2222 /* setup the proc dirs and files if needed */
2223 hso_log_port(hso_dev);
2224
2225 /* done, return it */
2226 return hso_dev;
2227exit:
2228 if (hso_dev && serial)
2229 hso_serial_common_free(serial);
2230 kfree(serial);
2231 hso_free_device(hso_dev);
2232 return NULL;
2233}
2234
2235/* Creates a multiplexed AT channel */
2236static
2237struct hso_device *hso_create_mux_serial_device(struct usb_interface *interface,
2238 int port,
2239 struct hso_shared_int *mux)
2240{
2241 struct hso_device *hso_dev;
2242 struct hso_serial *serial;
2243 int port_spec;
2244
2245 port_spec = HSO_INTF_MUX;
2246 port_spec &= ~HSO_PORT_MASK;
2247
2248 port_spec |= hso_mux_to_port(port);
2249 if ((port_spec & HSO_PORT_MASK) == HSO_PORT_NO_PORT)
2250 return NULL;
2251
2252 hso_dev = hso_create_device(interface, port_spec);
2253 if (!hso_dev)
2254 return NULL;
2255
2256 serial = kzalloc(sizeof(*serial), GFP_KERNEL);
2257 if (!serial)
2258 goto exit;
2259
2260 hso_dev->port_data.dev_serial = serial;
2261 serial->parent = hso_dev;
2262
2263 if (hso_serial_common_create
2264 (serial, 1, CTRL_URB_RX_SIZE, CTRL_URB_TX_SIZE))
2265 goto exit;
2266
2267 serial->tx_data_length--;
2268 serial->write_data = hso_mux_serial_write_data;
2269
2270 serial->shared_int = mux;
2271 mutex_lock(&serial->shared_int->shared_int_lock);
2272 serial->shared_int->ref_count++;
2273 mutex_unlock(&serial->shared_int->shared_int_lock);
2274
2275 /* and record this serial */
2276 set_serial_by_index(serial->minor, serial);
2277
2278 /* setup the proc dirs and files if needed */
2279 hso_log_port(hso_dev);
2280
2281 /* done, return it */
2282 return hso_dev;
2283
2284exit:
2285 if (serial) {
2286 tty_unregister_device(tty_drv, serial->minor);
2287 kfree(serial);
2288 }
2289 if (hso_dev)
2290 hso_free_device(hso_dev);
2291 return NULL;
2292
2293}
2294
2295static void hso_free_shared_int(struct hso_shared_int *mux)
2296{
2297 usb_free_urb(mux->shared_intr_urb);
2298 kfree(mux->shared_intr_buf);
2299 mutex_unlock(&mux->shared_int_lock);
2300 kfree(mux);
2301}
2302
2303static
2304struct hso_shared_int *hso_create_shared_int(struct usb_interface *interface)
2305{
2306 struct hso_shared_int *mux = kzalloc(sizeof(*mux), GFP_KERNEL);
2307
2308 if (!mux)
2309 return NULL;
2310
2311 mux->intr_endp = hso_get_ep(interface, USB_ENDPOINT_XFER_INT,
2312 USB_DIR_IN);
2313 if (!mux->intr_endp) {
2314 dev_err(&interface->dev, "Can't find INT IN endpoint\n");
2315 goto exit;
2316 }
2317
2318 mux->shared_intr_urb = usb_alloc_urb(0, GFP_KERNEL);
2319 if (!mux->shared_intr_urb) {
2320 dev_err(&interface->dev, "Could not allocate intr urb?");
2321 goto exit;
2322 }
2323 mux->shared_intr_buf = kzalloc(mux->intr_endp->wMaxPacketSize,
2324 GFP_KERNEL);
2325 if (!mux->shared_intr_buf) {
2326 dev_err(&interface->dev, "Could not allocate intr buf?");
2327 goto exit;
2328 }
2329
2330 mutex_init(&mux->shared_int_lock);
2331
2332 return mux;
2333
2334exit:
2335 kfree(mux->shared_intr_buf);
2336 usb_free_urb(mux->shared_intr_urb);
2337 kfree(mux);
2338 return NULL;
2339}
2340
2341/* Gets the port spec for a certain interface */
2342static int hso_get_config_data(struct usb_interface *interface)
2343{
2344 struct usb_device *usbdev = interface_to_usbdev(interface);
2345 u8 config_data[17];
2346 u32 if_num = interface->altsetting->desc.bInterfaceNumber;
2347 s32 result;
2348
2349 if (usb_control_msg(usbdev, usb_rcvctrlpipe(usbdev, 0),
2350 0x86, 0xC0, 0, 0, config_data, 17,
2351 USB_CTRL_SET_TIMEOUT) != 0x11) {
2352 return -EIO;
2353 }
2354
2355 switch (config_data[if_num]) {
2356 case 0x0:
2357 result = 0;
2358 break;
2359 case 0x1:
2360 result = HSO_PORT_DIAG;
2361 break;
2362 case 0x2:
2363 result = HSO_PORT_GPS;
2364 break;
2365 case 0x3:
2366 result = HSO_PORT_GPS_CONTROL;
2367 break;
2368 case 0x4:
2369 result = HSO_PORT_APP;
2370 break;
2371 case 0x5:
2372 result = HSO_PORT_APP2;
2373 break;
2374 case 0x6:
2375 result = HSO_PORT_CONTROL;
2376 break;
2377 case 0x7:
2378 result = HSO_PORT_NETWORK;
2379 break;
2380 case 0x8:
2381 result = HSO_PORT_MODEM;
2382 break;
2383 case 0x9:
2384 result = HSO_PORT_MSD;
2385 break;
2386 case 0xa:
2387 result = HSO_PORT_PCSC;
2388 break;
2389 case 0xb:
2390 result = HSO_PORT_VOICE;
2391 break;
2392 default:
2393 result = 0;
2394 }
2395
2396 if (result)
2397 result |= HSO_INTF_BULK;
2398
2399 if (config_data[16] & 0x1)
2400 result |= HSO_INFO_CRC_BUG;
2401
2402 return result;
2403}
2404
2405/* called once for each interface upon device insertion */
2406static int hso_probe(struct usb_interface *interface,
2407 const struct usb_device_id *id)
2408{
2409 int mux, i, if_num, port_spec;
2410 unsigned char port_mask;
2411 struct hso_device *hso_dev = NULL;
2412 struct hso_shared_int *shared_int;
2413 struct hso_device *tmp_dev = NULL;
2414
2415 if_num = interface->altsetting->desc.bInterfaceNumber;
2416
2417 /* Get the interface/port specification from either driver_info or from
2418 * the device itself */
2419 if (id->driver_info)
2420 port_spec = ((u32 *)(id->driver_info))[if_num];
2421 else
2422 port_spec = hso_get_config_data(interface);
2423
2424 if (interface->cur_altsetting->desc.bInterfaceClass != 0xFF) {
2425 dev_err(&interface->dev, "Not our interface\n");
2426 return -ENODEV;
2427 }
2428 /* Check if we need to switch to alt interfaces prior to port
2429 * configuration */
2430 if (interface->num_altsetting > 1)
2431 usb_set_interface(interface_to_usbdev(interface), if_num, 1);
2432 interface->needs_remote_wakeup = 1;
2433
2434 /* Allocate new hso device(s) */
2435 switch (port_spec & HSO_INTF_MASK) {
2436 case HSO_INTF_MUX:
2437 if ((port_spec & HSO_PORT_MASK) == HSO_PORT_NETWORK) {
2438 /* Create the network device */
2439 if (!disable_net) {
2440 hso_dev = hso_create_net_device(interface);
2441 if (!hso_dev)
2442 goto exit;
2443 tmp_dev = hso_dev;
2444 }
2445 }
2446
2447 if (hso_get_mux_ports(interface, &port_mask))
2448 /* TODO: de-allocate everything */
2449 goto exit;
2450
2451 shared_int = hso_create_shared_int(interface);
2452 if (!shared_int)
2453 goto exit;
2454
2455 for (i = 1, mux = 0; i < 0x100; i = i << 1, mux++) {
2456 if (port_mask & i) {
2457 hso_dev = hso_create_mux_serial_device(
2458 interface, i, shared_int);
2459 if (!hso_dev)
2460 goto exit;
2461 }
2462 }
2463
2464 if (tmp_dev)
2465 hso_dev = tmp_dev;
2466 break;
2467
2468 case HSO_INTF_BULK:
2469 /* It's a regular bulk interface */
2470 if (((port_spec & HSO_PORT_MASK) == HSO_PORT_NETWORK)
2471 && !disable_net)
2472 hso_dev = hso_create_net_device(interface);
2473 else
2474 hso_dev =
2475 hso_create_bulk_serial_device(interface, port_spec);
2476 if (!hso_dev)
2477 goto exit;
2478 break;
2479 default:
2480 goto exit;
2481 }
2482
2483 usb_driver_claim_interface(&hso_driver, interface, hso_dev);
2484
2485 /* save our data pointer in this device */
2486 usb_set_intfdata(interface, hso_dev);
2487
2488 /* done */
2489 return 0;
2490exit:
2491 hso_free_interface(interface);
2492 return -ENODEV;
2493}
2494
2495/* device removed, cleaning up */
2496static void hso_disconnect(struct usb_interface *interface)
2497{
2498 hso_free_interface(interface);
2499
2500 /* remove reference of our private data */
2501 usb_set_intfdata(interface, NULL);
2502
2503 usb_driver_release_interface(&hso_driver, interface);
2504}
2505
2506static void async_get_intf(struct work_struct *data)
2507{
2508 struct hso_device *hso_dev =
2509 container_of(data, struct hso_device, async_get_intf);
2510 usb_autopm_get_interface(hso_dev->interface);
2511}
2512
2513static void async_put_intf(struct work_struct *data)
2514{
2515 struct hso_device *hso_dev =
2516 container_of(data, struct hso_device, async_put_intf);
2517 usb_autopm_put_interface(hso_dev->interface);
2518}
2519
2520static int hso_get_activity(struct hso_device *hso_dev)
2521{
2522 if (hso_dev->usb->state == USB_STATE_SUSPENDED) {
2523 if (!hso_dev->is_active) {
2524 hso_dev->is_active = 1;
2525 schedule_work(&hso_dev->async_get_intf);
2526 }
2527 }
2528
2529 if (hso_dev->usb->state != USB_STATE_CONFIGURED)
2530 return -EAGAIN;
2531
2532 usb_mark_last_busy(hso_dev->usb);
2533
2534 return 0;
2535}
2536
2537static int hso_put_activity(struct hso_device *hso_dev)
2538{
2539 if (hso_dev->usb->state != USB_STATE_SUSPENDED) {
2540 if (hso_dev->is_active) {
2541 hso_dev->is_active = 0;
2542 schedule_work(&hso_dev->async_put_intf);
2543 return -EAGAIN;
2544 }
2545 }
2546 hso_dev->is_active = 0;
2547 return 0;
2548}
2549
2550/* called by kernel when we need to suspend device */
2551static int hso_suspend(struct usb_interface *iface, pm_message_t message)
2552{
2553 int i, result;
2554
2555 /* Stop all serial ports */
2556 for (i = 0; i < HSO_SERIAL_TTY_MINORS; i++) {
2557 if (serial_table[i] && (serial_table[i]->interface == iface)) {
2558 result = hso_stop_serial_device(serial_table[i]);
2559 if (result)
2560 goto out;
2561 }
2562 }
2563
2564 /* Stop all network ports */
2565 for (i = 0; i < HSO_MAX_NET_DEVICES; i++) {
2566 if (network_table[i] &&
2567 (network_table[i]->interface == iface)) {
2568 result = hso_stop_net_device(network_table[i]);
2569 if (result)
2570 goto out;
2571 }
2572 }
2573
2574out:
2575 return 0;
2576}
2577
2578/* called by kernel when we need to resume device */
2579static int hso_resume(struct usb_interface *iface)
2580{
2581 int i, result = 0;
2582 struct hso_net *hso_net;
2583
2584 /* Start all serial ports */
2585 for (i = 0; i < HSO_SERIAL_TTY_MINORS; i++) {
2586 if (serial_table[i] && (serial_table[i]->interface == iface)) {
2587 if (dev2ser(serial_table[i])->open_count) {
2588 result =
2589 hso_start_serial_device(serial_table[i], GFP_NOIO);
2590 hso_kick_transmit(dev2ser(serial_table[i]));
2591 if (result)
2592 goto out;
2593 }
2594 }
2595 }
2596
2597 /* Start all network ports */
2598 for (i = 0; i < HSO_MAX_NET_DEVICES; i++) {
2599 if (network_table[i] &&
2600 (network_table[i]->interface == iface)) {
2601 hso_net = dev2net(network_table[i]);
2602 /* First transmit any lingering data, then restart the
2603 * device. */
2604 if (hso_net->skb_tx_buf) {
2605 dev_dbg(&iface->dev,
2606 "Transmitting lingering data\n");
2607 hso_net_start_xmit(hso_net->skb_tx_buf,
2608 hso_net->net);
2609 }
2610 result = hso_start_net_device(network_table[i]);
2611 if (result)
2612 goto out;
2613 }
2614 }
2615
2616out:
2617 return result;
2618}
2619
2620static void hso_serial_ref_free(struct kref *ref)
2621{
2622 struct hso_device *hso_dev = container_of(ref, struct hso_device, ref);
2623
2624 hso_free_serial_device(hso_dev);
2625}
2626
2627static void hso_free_interface(struct usb_interface *interface)
2628{
2629 struct hso_serial *hso_dev;
2630 int i;
2631
2632 for (i = 0; i < HSO_SERIAL_TTY_MINORS; i++) {
2633 if (serial_table[i]
2634 && (serial_table[i]->interface == interface)) {
2635 hso_dev = dev2ser(serial_table[i]);
2636 if (hso_dev->tty)
2637 tty_hangup(hso_dev->tty);
2638 mutex_lock(&hso_dev->parent->mutex);
2639 hso_dev->parent->usb_gone = 1;
2640 mutex_unlock(&hso_dev->parent->mutex);
2641 kref_put(&serial_table[i]->ref, hso_serial_ref_free);
2642 }
2643 }
2644
2645 for (i = 0; i < HSO_MAX_NET_DEVICES; i++) {
2646 if (network_table[i]
2647 && (network_table[i]->interface == interface)) {
2648 struct rfkill *rfk = dev2net(network_table[i])->rfkill;
2649 /* hso_stop_net_device doesn't stop the net queue since
2650 * traffic needs to start it again when suspended */
2651 netif_stop_queue(dev2net(network_table[i])->net);
2652 hso_stop_net_device(network_table[i]);
2653 cancel_work_sync(&network_table[i]->async_put_intf);
2654 cancel_work_sync(&network_table[i]->async_get_intf);
2655 if(rfk)
2656 rfkill_unregister(rfk);
2657 hso_free_net_device(network_table[i]);
2658 }
2659 }
2660}
2661
2662/* Helper functions */
2663
2664/* Get the endpoint ! */
2665static struct usb_endpoint_descriptor *hso_get_ep(struct usb_interface *intf,
2666 int type, int dir)
2667{
2668 int i;
2669 struct usb_host_interface *iface = intf->cur_altsetting;
2670 struct usb_endpoint_descriptor *endp;
2671
2672 for (i = 0; i < iface->desc.bNumEndpoints; i++) {
2673 endp = &iface->endpoint[i].desc;
2674 if (((endp->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == dir) &&
2675 ((endp->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == type))
2676 return endp;
2677 }
2678
2679 return NULL;
2680}
2681
2682/* Get the byte that describes which ports are enabled */
2683static int hso_get_mux_ports(struct usb_interface *intf, unsigned char *ports)
2684{
2685 int i;
2686 struct usb_host_interface *iface = intf->cur_altsetting;
2687
2688 if (iface->extralen == 3) {
2689 *ports = iface->extra[2];
2690 return 0;
2691 }
2692
2693 for (i = 0; i < iface->desc.bNumEndpoints; i++) {
2694 if (iface->endpoint[i].extralen == 3) {
2695 *ports = iface->endpoint[i].extra[2];
2696 return 0;
2697 }
2698 }
2699
2700 return -1;
2701}
2702
2703/* interrupt urb needs to be submitted, used for serial read of muxed port */
2704static int hso_mux_submit_intr_urb(struct hso_shared_int *shared_int,
2705 struct usb_device *usb, gfp_t gfp)
2706{
2707 int result;
2708
2709 usb_fill_int_urb(shared_int->shared_intr_urb, usb,
2710 usb_rcvintpipe(usb,
2711 shared_int->intr_endp->bEndpointAddress & 0x7F),
2712 shared_int->shared_intr_buf,
2713 shared_int->intr_endp->wMaxPacketSize,
2714 intr_callback, shared_int,
2715 shared_int->intr_endp->bInterval);
2716
2717 result = usb_submit_urb(shared_int->shared_intr_urb, gfp);
2718 if (result)
2719 dev_warn(&usb->dev, "%s failed mux_intr_urb %d", __func__,
2720 result);
2721
2722 return result;
2723}
2724
2725/* operations setup of the serial interface */
2726static struct tty_operations hso_serial_ops = {
2727 .open = hso_serial_open,
2728 .close = hso_serial_close,
2729 .write = hso_serial_write,
2730 .write_room = hso_serial_write_room,
2731 .set_termios = hso_serial_set_termios,
2732 .chars_in_buffer = hso_serial_chars_in_buffer,
2733 .tiocmget = hso_serial_tiocmget,
2734 .tiocmset = hso_serial_tiocmset,
2735};
2736
2737static struct usb_driver hso_driver = {
2738 .name = driver_name,
2739 .probe = hso_probe,
2740 .disconnect = hso_disconnect,
2741 .id_table = hso_ids,
2742 .suspend = hso_suspend,
2743 .resume = hso_resume,
2744 .supports_autosuspend = 1,
2745};
2746
2747static int __init hso_init(void)
2748{
2749 int i;
2750 int result;
2751
2752 /* put it in the log */
2753 printk(KERN_INFO "hso: %s\n", version);
2754
2755 /* Initialise the serial table semaphore and table */
2756 spin_lock_init(&serial_table_lock);
2757 for (i = 0; i < HSO_SERIAL_TTY_MINORS; i++)
2758 serial_table[i] = NULL;
2759
2760 /* allocate our driver using the proper amount of supported minors */
2761 tty_drv = alloc_tty_driver(HSO_SERIAL_TTY_MINORS);
2762 if (!tty_drv)
2763 return -ENOMEM;
2764
2765 /* fill in all needed values */
2766 tty_drv->magic = TTY_DRIVER_MAGIC;
2767 tty_drv->owner = THIS_MODULE;
2768 tty_drv->driver_name = driver_name;
2769 tty_drv->name = tty_filename;
2770
2771 /* if major number is provided as parameter, use that one */
2772 if (tty_major)
2773 tty_drv->major = tty_major;
2774
2775 tty_drv->minor_start = 0;
2776 tty_drv->num = HSO_SERIAL_TTY_MINORS;
2777 tty_drv->type = TTY_DRIVER_TYPE_SERIAL;
2778 tty_drv->subtype = SERIAL_TYPE_NORMAL;
2779 tty_drv->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
2780 tty_drv->init_termios = tty_std_termios;
2781 tty_drv->init_termios.c_cflag = B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2782 tty_drv->termios = hso_serial_termios;
2783 tty_drv->termios_locked = hso_serial_termios_locked;
2784 tty_set_operations(tty_drv, &hso_serial_ops);
2785
2786 /* register the tty driver */
2787 result = tty_register_driver(tty_drv);
2788 if (result) {
2789 printk(KERN_ERR "%s - tty_register_driver failed(%d)\n",
2790 __func__, result);
2791 return result;
2792 }
2793
2794 /* register this module as an usb driver */
2795 result = usb_register(&hso_driver);
2796 if (result) {
2797 printk(KERN_ERR "Could not register hso driver? error: %d\n",
2798 result);
2799 /* cleanup serial interface */
2800 tty_unregister_driver(tty_drv);
2801 return result;
2802 }
2803
2804 /* done */
2805 return 0;
2806}
2807
2808static void __exit hso_exit(void)
2809{
2810 printk(KERN_INFO "hso: unloaded\n");
2811
2812 tty_unregister_driver(tty_drv);
2813 /* deregister the usb driver */
2814 usb_deregister(&hso_driver);
2815}
2816
2817/* Module definitions */
2818module_init(hso_init);
2819module_exit(hso_exit);
2820
2821MODULE_AUTHOR(MOD_AUTHOR);
2822MODULE_DESCRIPTION(MOD_DESCRIPTION);
2823MODULE_LICENSE(MOD_LICENSE);
2824MODULE_INFO(Version, DRIVER_VERSION);
2825
2826/* change the debug level (eg: insmod hso.ko debug=0x04) */
2827MODULE_PARM_DESC(debug, "Level of debug [0x01 | 0x02 | 0x04 | 0x08 | 0x10]");
2828module_param(debug, int, S_IRUGO | S_IWUSR);
2829
2830/* set the major tty number (eg: insmod hso.ko tty_major=245) */
2831MODULE_PARM_DESC(tty_major, "Set the major tty number");
2832module_param(tty_major, int, S_IRUGO | S_IWUSR);
2833
2834/* disable network interface (eg: insmod hso.ko disable_net=1) */
2835MODULE_PARM_DESC(disable_net, "Disable the network interface");
2836module_param(disable_net, int, S_IRUGO | S_IWUSR);
diff --git a/drivers/net/usb/rndis_host.c b/drivers/net/usb/rndis_host.c
index ae467f182c40..61c98beb4d17 100644
--- a/drivers/net/usb/rndis_host.c
+++ b/drivers/net/usb/rndis_host.c
@@ -74,7 +74,7 @@ EXPORT_SYMBOL_GPL(rndis_status);
74 * Call context is likely probe(), before interface name is known, 74 * Call context is likely probe(), before interface name is known,
75 * which is why we won't try to use it in the diagnostics. 75 * which is why we won't try to use it in the diagnostics.
76 */ 76 */
77int rndis_command(struct usbnet *dev, struct rndis_msg_hdr *buf) 77int rndis_command(struct usbnet *dev, struct rndis_msg_hdr *buf, int buflen)
78{ 78{
79 struct cdc_state *info = (void *) &dev->data; 79 struct cdc_state *info = (void *) &dev->data;
80 int master_ifnum; 80 int master_ifnum;
@@ -121,7 +121,7 @@ int rndis_command(struct usbnet *dev, struct rndis_msg_hdr *buf)
121 USB_CDC_GET_ENCAPSULATED_RESPONSE, 121 USB_CDC_GET_ENCAPSULATED_RESPONSE,
122 USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE, 122 USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE,
123 0, master_ifnum, 123 0, master_ifnum,
124 buf, CONTROL_BUFFER_SIZE, 124 buf, buflen,
125 RNDIS_CONTROL_TIMEOUT_MS); 125 RNDIS_CONTROL_TIMEOUT_MS);
126 if (likely(retval >= 8)) { 126 if (likely(retval >= 8)) {
127 msg_len = le32_to_cpu(buf->msg_len); 127 msg_len = le32_to_cpu(buf->msg_len);
@@ -239,7 +239,7 @@ static int rndis_query(struct usbnet *dev, struct usb_interface *intf,
239 u.get->len = cpu_to_le32(in_len); 239 u.get->len = cpu_to_le32(in_len);
240 u.get->offset = ccpu2(20); 240 u.get->offset = ccpu2(20);
241 241
242 retval = rndis_command(dev, u.header); 242 retval = rndis_command(dev, u.header, CONTROL_BUFFER_SIZE);
243 if (unlikely(retval < 0)) { 243 if (unlikely(retval < 0)) {
244 dev_err(&intf->dev, "RNDIS_MSG_QUERY(0x%08x) failed, %d\n", 244 dev_err(&intf->dev, "RNDIS_MSG_QUERY(0x%08x) failed, %d\n",
245 oid, retval); 245 oid, retval);
@@ -328,7 +328,7 @@ generic_rndis_bind(struct usbnet *dev, struct usb_interface *intf, int flags)
328 u.init->max_transfer_size = cpu_to_le32(dev->rx_urb_size); 328 u.init->max_transfer_size = cpu_to_le32(dev->rx_urb_size);
329 329
330 net->change_mtu = NULL; 330 net->change_mtu = NULL;
331 retval = rndis_command(dev, u.header); 331 retval = rndis_command(dev, u.header, CONTROL_BUFFER_SIZE);
332 if (unlikely(retval < 0)) { 332 if (unlikely(retval < 0)) {
333 /* it might not even be an RNDIS device!! */ 333 /* it might not even be an RNDIS device!! */
334 dev_err(&intf->dev, "RNDIS init failed, %d\n", retval); 334 dev_err(&intf->dev, "RNDIS init failed, %d\n", retval);
@@ -409,7 +409,7 @@ generic_rndis_bind(struct usbnet *dev, struct usb_interface *intf, int flags)
409 u.set->offset = ccpu2((sizeof *u.set) - 8); 409 u.set->offset = ccpu2((sizeof *u.set) - 8);
410 *(__le32 *)(u.buf + sizeof *u.set) = RNDIS_DEFAULT_FILTER; 410 *(__le32 *)(u.buf + sizeof *u.set) = RNDIS_DEFAULT_FILTER;
411 411
412 retval = rndis_command(dev, u.header); 412 retval = rndis_command(dev, u.header, CONTROL_BUFFER_SIZE);
413 if (unlikely(retval < 0)) { 413 if (unlikely(retval < 0)) {
414 dev_err(&intf->dev, "rndis set packet filter, %d\n", retval); 414 dev_err(&intf->dev, "rndis set packet filter, %d\n", retval);
415 goto halt_fail_and_release; 415 goto halt_fail_and_release;
@@ -424,7 +424,7 @@ halt_fail_and_release:
424 memset(u.halt, 0, sizeof *u.halt); 424 memset(u.halt, 0, sizeof *u.halt);
425 u.halt->msg_type = RNDIS_MSG_HALT; 425 u.halt->msg_type = RNDIS_MSG_HALT;
426 u.halt->msg_len = ccpu2(sizeof *u.halt); 426 u.halt->msg_len = ccpu2(sizeof *u.halt);
427 (void) rndis_command(dev, (void *)u.halt); 427 (void) rndis_command(dev, (void *)u.halt, CONTROL_BUFFER_SIZE);
428fail_and_release: 428fail_and_release:
429 usb_set_intfdata(info->data, NULL); 429 usb_set_intfdata(info->data, NULL);
430 usb_driver_release_interface(driver_of(intf), info->data); 430 usb_driver_release_interface(driver_of(intf), info->data);
@@ -449,7 +449,7 @@ void rndis_unbind(struct usbnet *dev, struct usb_interface *intf)
449 if (halt) { 449 if (halt) {
450 halt->msg_type = RNDIS_MSG_HALT; 450 halt->msg_type = RNDIS_MSG_HALT;
451 halt->msg_len = ccpu2(sizeof *halt); 451 halt->msg_len = ccpu2(sizeof *halt);
452 (void) rndis_command(dev, (void *)halt); 452 (void) rndis_command(dev, (void *)halt, CONTROL_BUFFER_SIZE);
453 kfree(halt); 453 kfree(halt);
454 } 454 }
455 455
diff --git a/drivers/net/via-rhine.c b/drivers/net/via-rhine.c
index 8c9d6ae2bb31..96dff04334b8 100644
--- a/drivers/net/via-rhine.c
+++ b/drivers/net/via-rhine.c
@@ -73,12 +73,7 @@ static const int multicast_filter_limit = 32;
73 There are no ill effects from too-large receive rings. */ 73 There are no ill effects from too-large receive rings. */
74#define TX_RING_SIZE 16 74#define TX_RING_SIZE 16
75#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */ 75#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
76#ifdef CONFIG_VIA_RHINE_NAPI
77#define RX_RING_SIZE 64 76#define RX_RING_SIZE 64
78#else
79#define RX_RING_SIZE 16
80#endif
81
82 77
83/* Operational parameters that usually are not changed. */ 78/* Operational parameters that usually are not changed. */
84 79
@@ -583,7 +578,6 @@ static void rhine_poll(struct net_device *dev)
583} 578}
584#endif 579#endif
585 580
586#ifdef CONFIG_VIA_RHINE_NAPI
587static int rhine_napipoll(struct napi_struct *napi, int budget) 581static int rhine_napipoll(struct napi_struct *napi, int budget)
588{ 582{
589 struct rhine_private *rp = container_of(napi, struct rhine_private, napi); 583 struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
@@ -604,7 +598,6 @@ static int rhine_napipoll(struct napi_struct *napi, int budget)
604 } 598 }
605 return work_done; 599 return work_done;
606} 600}
607#endif
608 601
609static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr) 602static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
610{ 603{
@@ -784,9 +777,8 @@ static int __devinit rhine_init_one(struct pci_dev *pdev,
784#ifdef CONFIG_NET_POLL_CONTROLLER 777#ifdef CONFIG_NET_POLL_CONTROLLER
785 dev->poll_controller = rhine_poll; 778 dev->poll_controller = rhine_poll;
786#endif 779#endif
787#ifdef CONFIG_VIA_RHINE_NAPI
788 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64); 780 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
789#endif 781
790 if (rp->quirks & rqRhineI) 782 if (rp->quirks & rqRhineI)
791 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM; 783 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
792 784
@@ -1056,9 +1048,7 @@ static void init_registers(struct net_device *dev)
1056 1048
1057 rhine_set_rx_mode(dev); 1049 rhine_set_rx_mode(dev);
1058 1050
1059#ifdef CONFIG_VIA_RHINE_NAPI
1060 napi_enable(&rp->napi); 1051 napi_enable(&rp->napi);
1061#endif
1062 1052
1063 /* Enable interrupts by setting the interrupt mask. */ 1053 /* Enable interrupts by setting the interrupt mask. */
1064 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | 1054 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
@@ -1193,9 +1183,7 @@ static void rhine_tx_timeout(struct net_device *dev)
1193 /* protect against concurrent rx interrupts */ 1183 /* protect against concurrent rx interrupts */
1194 disable_irq(rp->pdev->irq); 1184 disable_irq(rp->pdev->irq);
1195 1185
1196#ifdef CONFIG_VIA_RHINE_NAPI
1197 napi_disable(&rp->napi); 1186 napi_disable(&rp->napi);
1198#endif
1199 1187
1200 spin_lock(&rp->lock); 1188 spin_lock(&rp->lock);
1201 1189
@@ -1319,16 +1307,12 @@ static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
1319 1307
1320 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped | 1308 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
1321 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) { 1309 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
1322#ifdef CONFIG_VIA_RHINE_NAPI
1323 iowrite16(IntrTxAborted | 1310 iowrite16(IntrTxAborted |
1324 IntrTxDone | IntrTxError | IntrTxUnderrun | 1311 IntrTxDone | IntrTxError | IntrTxUnderrun |
1325 IntrPCIErr | IntrStatsMax | IntrLinkChange, 1312 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1326 ioaddr + IntrEnable); 1313 ioaddr + IntrEnable);
1327 1314
1328 netif_rx_schedule(dev, &rp->napi); 1315 netif_rx_schedule(dev, &rp->napi);
1329#else
1330 rhine_rx(dev, RX_RING_SIZE);
1331#endif
1332 } 1316 }
1333 1317
1334 if (intr_status & (IntrTxErrSummary | IntrTxDone)) { 1318 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
@@ -1520,11 +1504,7 @@ static int rhine_rx(struct net_device *dev, int limit)
1520 PCI_DMA_FROMDEVICE); 1504 PCI_DMA_FROMDEVICE);
1521 } 1505 }
1522 skb->protocol = eth_type_trans(skb, dev); 1506 skb->protocol = eth_type_trans(skb, dev);
1523#ifdef CONFIG_VIA_RHINE_NAPI
1524 netif_receive_skb(skb); 1507 netif_receive_skb(skb);
1525#else
1526 netif_rx(skb);
1527#endif
1528 dev->last_rx = jiffies; 1508 dev->last_rx = jiffies;
1529 rp->stats.rx_bytes += pkt_len; 1509 rp->stats.rx_bytes += pkt_len;
1530 rp->stats.rx_packets++; 1510 rp->stats.rx_packets++;
@@ -1836,9 +1816,7 @@ static int rhine_close(struct net_device *dev)
1836 spin_lock_irq(&rp->lock); 1816 spin_lock_irq(&rp->lock);
1837 1817
1838 netif_stop_queue(dev); 1818 netif_stop_queue(dev);
1839#ifdef CONFIG_VIA_RHINE_NAPI
1840 napi_disable(&rp->napi); 1819 napi_disable(&rp->napi);
1841#endif
1842 1820
1843 if (debug > 1) 1821 if (debug > 1)
1844 printk(KERN_DEBUG "%s: Shutting down ethercard, " 1822 printk(KERN_DEBUG "%s: Shutting down ethercard, "
@@ -1937,9 +1915,8 @@ static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1937 if (!netif_running(dev)) 1915 if (!netif_running(dev))
1938 return 0; 1916 return 0;
1939 1917
1940#ifdef CONFIG_VIA_RHINE_NAPI
1941 napi_disable(&rp->napi); 1918 napi_disable(&rp->napi);
1942#endif 1919
1943 netif_device_detach(dev); 1920 netif_device_detach(dev);
1944 pci_save_state(pdev); 1921 pci_save_state(pdev);
1945 1922
diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c
index 6b8d882d197b..370ce30f2f45 100644
--- a/drivers/net/via-velocity.c
+++ b/drivers/net/via-velocity.c
@@ -1102,61 +1102,41 @@ static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pc
1102 1102
1103static int velocity_init_rings(struct velocity_info *vptr) 1103static int velocity_init_rings(struct velocity_info *vptr)
1104{ 1104{
1105 int i; 1105 struct velocity_opt *opt = &vptr->options;
1106 unsigned int psize; 1106 const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
1107 unsigned int tsize; 1107 const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
1108 struct pci_dev *pdev = vptr->pdev;
1108 dma_addr_t pool_dma; 1109 dma_addr_t pool_dma;
1109 u8 *pool; 1110 void *pool;
1110 1111 unsigned int i;
1111 /*
1112 * Allocate all RD/TD rings a single pool
1113 */
1114
1115 psize = vptr->options.numrx * sizeof(struct rx_desc) +
1116 vptr->options.numtx * sizeof(struct tx_desc) * vptr->num_txq;
1117 1112
1118 /* 1113 /*
1114 * Allocate all RD/TD rings a single pool.
1115 *
1119 * pci_alloc_consistent() fulfills the requirement for 64 bytes 1116 * pci_alloc_consistent() fulfills the requirement for 64 bytes
1120 * alignment 1117 * alignment
1121 */ 1118 */
1122 pool = pci_alloc_consistent(vptr->pdev, psize, &pool_dma); 1119 pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->num_txq +
1123 1120 rx_ring_size, &pool_dma);
1124 if (pool == NULL) { 1121 if (!pool) {
1125 printk(KERN_ERR "%s : DMA memory allocation failed.\n", 1122 dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
1126 vptr->dev->name); 1123 vptr->dev->name);
1127 return -ENOMEM; 1124 return -ENOMEM;
1128 } 1125 }
1129 1126
1130 memset(pool, 0, psize); 1127 vptr->rd_ring = pool;
1131
1132 vptr->rd_ring = (struct rx_desc *) pool;
1133
1134 vptr->rd_pool_dma = pool_dma; 1128 vptr->rd_pool_dma = pool_dma;
1135 1129
1136 tsize = vptr->options.numtx * PKT_BUF_SZ * vptr->num_txq; 1130 pool += rx_ring_size;
1137 vptr->tx_bufs = pci_alloc_consistent(vptr->pdev, tsize, 1131 pool_dma += rx_ring_size;
1138 &vptr->tx_bufs_dma);
1139 1132
1140 if (vptr->tx_bufs == NULL) {
1141 printk(KERN_ERR "%s: DMA memory allocation failed.\n",
1142 vptr->dev->name);
1143 pci_free_consistent(vptr->pdev, psize, pool, pool_dma);
1144 return -ENOMEM;
1145 }
1146
1147 memset(vptr->tx_bufs, 0, vptr->options.numtx * PKT_BUF_SZ * vptr->num_txq);
1148
1149 i = vptr->options.numrx * sizeof(struct rx_desc);
1150 pool += i;
1151 pool_dma += i;
1152 for (i = 0; i < vptr->num_txq; i++) { 1133 for (i = 0; i < vptr->num_txq; i++) {
1153 int offset = vptr->options.numtx * sizeof(struct tx_desc); 1134 vptr->td_rings[i] = pool;
1154
1155 vptr->td_pool_dma[i] = pool_dma; 1135 vptr->td_pool_dma[i] = pool_dma;
1156 vptr->td_rings[i] = (struct tx_desc *) pool; 1136 pool += tx_ring_size;
1157 pool += offset; 1137 pool_dma += tx_ring_size;
1158 pool_dma += offset;
1159 } 1138 }
1139
1160 return 0; 1140 return 0;
1161} 1141}
1162 1142
@@ -1169,19 +1149,13 @@ static int velocity_init_rings(struct velocity_info *vptr)
1169 1149
1170static void velocity_free_rings(struct velocity_info *vptr) 1150static void velocity_free_rings(struct velocity_info *vptr)
1171{ 1151{
1172 int size; 1152 const int size = vptr->options.numrx * sizeof(struct rx_desc) +
1173 1153 vptr->options.numtx * sizeof(struct tx_desc) * vptr->num_txq;
1174 size = vptr->options.numrx * sizeof(struct rx_desc) +
1175 vptr->options.numtx * sizeof(struct tx_desc) * vptr->num_txq;
1176 1154
1177 pci_free_consistent(vptr->pdev, size, vptr->rd_ring, vptr->rd_pool_dma); 1155 pci_free_consistent(vptr->pdev, size, vptr->rd_ring, vptr->rd_pool_dma);
1178
1179 size = vptr->options.numtx * PKT_BUF_SZ * vptr->num_txq;
1180
1181 pci_free_consistent(vptr->pdev, size, vptr->tx_bufs, vptr->tx_bufs_dma);
1182} 1156}
1183 1157
1184static inline void velocity_give_many_rx_descs(struct velocity_info *vptr) 1158static void velocity_give_many_rx_descs(struct velocity_info *vptr)
1185{ 1159{
1186 struct mac_regs __iomem *regs = vptr->mac_regs; 1160 struct mac_regs __iomem *regs = vptr->mac_regs;
1187 int avail, dirty, unusable; 1161 int avail, dirty, unusable;
@@ -1208,7 +1182,7 @@ static inline void velocity_give_many_rx_descs(struct velocity_info *vptr)
1208 1182
1209static int velocity_rx_refill(struct velocity_info *vptr) 1183static int velocity_rx_refill(struct velocity_info *vptr)
1210{ 1184{
1211 int dirty = vptr->rd_dirty, done = 0, ret = 0; 1185 int dirty = vptr->rd_dirty, done = 0;
1212 1186
1213 do { 1187 do {
1214 struct rx_desc *rd = vptr->rd_ring + dirty; 1188 struct rx_desc *rd = vptr->rd_ring + dirty;
@@ -1218,8 +1192,7 @@ static int velocity_rx_refill(struct velocity_info *vptr)
1218 break; 1192 break;
1219 1193
1220 if (!vptr->rd_info[dirty].skb) { 1194 if (!vptr->rd_info[dirty].skb) {
1221 ret = velocity_alloc_rx_buf(vptr, dirty); 1195 if (velocity_alloc_rx_buf(vptr, dirty) < 0)
1222 if (ret < 0)
1223 break; 1196 break;
1224 } 1197 }
1225 done++; 1198 done++;
@@ -1229,10 +1202,14 @@ static int velocity_rx_refill(struct velocity_info *vptr)
1229 if (done) { 1202 if (done) {
1230 vptr->rd_dirty = dirty; 1203 vptr->rd_dirty = dirty;
1231 vptr->rd_filled += done; 1204 vptr->rd_filled += done;
1232 velocity_give_many_rx_descs(vptr);
1233 } 1205 }
1234 1206
1235 return ret; 1207 return done;
1208}
1209
1210static void velocity_set_rxbufsize(struct velocity_info *vptr, int mtu)
1211{
1212 vptr->rx_buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32;
1236} 1213}
1237 1214
1238/** 1215/**
@@ -1245,25 +1222,24 @@ static int velocity_rx_refill(struct velocity_info *vptr)
1245 1222
1246static int velocity_init_rd_ring(struct velocity_info *vptr) 1223static int velocity_init_rd_ring(struct velocity_info *vptr)
1247{ 1224{
1248 int ret; 1225 int ret = -ENOMEM;
1249 int mtu = vptr->dev->mtu;
1250
1251 vptr->rx_buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32;
1252 1226
1253 vptr->rd_info = kcalloc(vptr->options.numrx, 1227 vptr->rd_info = kcalloc(vptr->options.numrx,
1254 sizeof(struct velocity_rd_info), GFP_KERNEL); 1228 sizeof(struct velocity_rd_info), GFP_KERNEL);
1255 if (!vptr->rd_info) 1229 if (!vptr->rd_info)
1256 return -ENOMEM; 1230 goto out;
1257 1231
1258 vptr->rd_filled = vptr->rd_dirty = vptr->rd_curr = 0; 1232 vptr->rd_filled = vptr->rd_dirty = vptr->rd_curr = 0;
1259 1233
1260 ret = velocity_rx_refill(vptr); 1234 if (velocity_rx_refill(vptr) != vptr->options.numrx) {
1261 if (ret < 0) {
1262 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR 1235 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
1263 "%s: failed to allocate RX buffer.\n", vptr->dev->name); 1236 "%s: failed to allocate RX buffer.\n", vptr->dev->name);
1264 velocity_free_rd_ring(vptr); 1237 velocity_free_rd_ring(vptr);
1238 goto out;
1265 } 1239 }
1266 1240
1241 ret = 0;
1242out:
1267 return ret; 1243 return ret;
1268} 1244}
1269 1245
@@ -1313,10 +1289,8 @@ static void velocity_free_rd_ring(struct velocity_info *vptr)
1313 1289
1314static int velocity_init_td_ring(struct velocity_info *vptr) 1290static int velocity_init_td_ring(struct velocity_info *vptr)
1315{ 1291{
1316 int i, j;
1317 dma_addr_t curr; 1292 dma_addr_t curr;
1318 struct tx_desc *td; 1293 unsigned int j;
1319 struct velocity_td_info *td_info;
1320 1294
1321 /* Init the TD ring entries */ 1295 /* Init the TD ring entries */
1322 for (j = 0; j < vptr->num_txq; j++) { 1296 for (j = 0; j < vptr->num_txq; j++) {
@@ -1331,14 +1305,6 @@ static int velocity_init_td_ring(struct velocity_info *vptr)
1331 return -ENOMEM; 1305 return -ENOMEM;
1332 } 1306 }
1333 1307
1334 for (i = 0; i < vptr->options.numtx; i++, curr += sizeof(struct tx_desc)) {
1335 td = &(vptr->td_rings[j][i]);
1336 td_info = &(vptr->td_infos[j][i]);
1337 td_info->buf = vptr->tx_bufs +
1338 (j * vptr->options.numtx + i) * PKT_BUF_SZ;
1339 td_info->buf_dma = vptr->tx_bufs_dma +
1340 (j * vptr->options.numtx + i) * PKT_BUF_SZ;
1341 }
1342 vptr->td_tail[j] = vptr->td_curr[j] = vptr->td_used[j] = 0; 1308 vptr->td_tail[j] = vptr->td_curr[j] = vptr->td_used[j] = 0;
1343 } 1309 }
1344 return 0; 1310 return 0;
@@ -1448,10 +1414,8 @@ static int velocity_rx_srv(struct velocity_info *vptr, int status)
1448 1414
1449 vptr->rd_curr = rd_curr; 1415 vptr->rd_curr = rd_curr;
1450 1416
1451 if (works > 0 && velocity_rx_refill(vptr) < 0) { 1417 if ((works > 0) && (velocity_rx_refill(vptr) > 0))
1452 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR 1418 velocity_give_many_rx_descs(vptr);
1453 "%s: rx buf allocation failure\n", vptr->dev->name);
1454 }
1455 1419
1456 VAR_USED(stats); 1420 VAR_USED(stats);
1457 return works; 1421 return works;
@@ -1495,24 +1459,18 @@ static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
1495 * enough. This function returns a negative value if the received 1459 * enough. This function returns a negative value if the received
1496 * packet is too big or if memory is exhausted. 1460 * packet is too big or if memory is exhausted.
1497 */ 1461 */
1498static inline int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size, 1462static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
1499 struct velocity_info *vptr) 1463 struct velocity_info *vptr)
1500{ 1464{
1501 int ret = -1; 1465 int ret = -1;
1502
1503 if (pkt_size < rx_copybreak) { 1466 if (pkt_size < rx_copybreak) {
1504 struct sk_buff *new_skb; 1467 struct sk_buff *new_skb;
1505 1468
1506 new_skb = dev_alloc_skb(pkt_size + 2); 1469 new_skb = netdev_alloc_skb(vptr->dev, pkt_size + 2);
1507 if (new_skb) { 1470 if (new_skb) {
1508 new_skb->dev = vptr->dev;
1509 new_skb->ip_summed = rx_skb[0]->ip_summed; 1471 new_skb->ip_summed = rx_skb[0]->ip_summed;
1510 1472 skb_reserve(new_skb, 2);
1511 if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) 1473 skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
1512 skb_reserve(new_skb, 2);
1513
1514 skb_copy_from_linear_data(rx_skb[0], new_skb->data,
1515 pkt_size);
1516 *rx_skb = new_skb; 1474 *rx_skb = new_skb;
1517 ret = 0; 1475 ret = 0;
1518 } 1476 }
@@ -1533,12 +1491,8 @@ static inline int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
1533static inline void velocity_iph_realign(struct velocity_info *vptr, 1491static inline void velocity_iph_realign(struct velocity_info *vptr,
1534 struct sk_buff *skb, int pkt_size) 1492 struct sk_buff *skb, int pkt_size)
1535{ 1493{
1536 /* FIXME - memmove ? */
1537 if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) { 1494 if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
1538 int i; 1495 memmove(skb->data + 2, skb->data, pkt_size);
1539
1540 for (i = pkt_size; i >= 0; i--)
1541 *(skb->data + i + 2) = *(skb->data + i);
1542 skb_reserve(skb, 2); 1496 skb_reserve(skb, 2);
1543 } 1497 }
1544} 1498}
@@ -1629,7 +1583,7 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
1629 struct rx_desc *rd = &(vptr->rd_ring[idx]); 1583 struct rx_desc *rd = &(vptr->rd_ring[idx]);
1630 struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]); 1584 struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]);
1631 1585
1632 rd_info->skb = dev_alloc_skb(vptr->rx_buf_sz + 64); 1586 rd_info->skb = netdev_alloc_skb(vptr->dev, vptr->rx_buf_sz + 64);
1633 if (rd_info->skb == NULL) 1587 if (rd_info->skb == NULL)
1634 return -ENOMEM; 1588 return -ENOMEM;
1635 1589
@@ -1638,7 +1592,6 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
1638 * 64byte alignment. 1592 * 64byte alignment.
1639 */ 1593 */
1640 skb_reserve(rd_info->skb, (unsigned long) rd_info->skb->data & 63); 1594 skb_reserve(rd_info->skb, (unsigned long) rd_info->skb->data & 63);
1641 rd_info->skb->dev = vptr->dev;
1642 rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data, vptr->rx_buf_sz, PCI_DMA_FROMDEVICE); 1595 rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data, vptr->rx_buf_sz, PCI_DMA_FROMDEVICE);
1643 1596
1644 /* 1597 /*
@@ -1878,7 +1831,7 @@ static void velocity_free_tx_buf(struct velocity_info *vptr, struct velocity_td_
1878 /* 1831 /*
1879 * Don't unmap the pre-allocated tx_bufs 1832 * Don't unmap the pre-allocated tx_bufs
1880 */ 1833 */
1881 if (tdinfo->skb_dma && (tdinfo->skb_dma[0] != tdinfo->buf_dma)) { 1834 if (tdinfo->skb_dma) {
1882 1835
1883 for (i = 0; i < tdinfo->nskb_dma; i++) { 1836 for (i = 0; i < tdinfo->nskb_dma; i++) {
1884#ifdef VELOCITY_ZERO_COPY_SUPPORT 1837#ifdef VELOCITY_ZERO_COPY_SUPPORT
@@ -1909,6 +1862,8 @@ static int velocity_open(struct net_device *dev)
1909 struct velocity_info *vptr = netdev_priv(dev); 1862 struct velocity_info *vptr = netdev_priv(dev);
1910 int ret; 1863 int ret;
1911 1864
1865 velocity_set_rxbufsize(vptr, dev->mtu);
1866
1912 ret = velocity_init_rings(vptr); 1867 ret = velocity_init_rings(vptr);
1913 if (ret < 0) 1868 if (ret < 0)
1914 goto out; 1869 goto out;
@@ -1924,6 +1879,8 @@ static int velocity_open(struct net_device *dev)
1924 /* Ensure chip is running */ 1879 /* Ensure chip is running */
1925 pci_set_power_state(vptr->pdev, PCI_D0); 1880 pci_set_power_state(vptr->pdev, PCI_D0);
1926 1881
1882 velocity_give_many_rx_descs(vptr);
1883
1927 velocity_init_registers(vptr, VELOCITY_INIT_COLD); 1884 velocity_init_registers(vptr, VELOCITY_INIT_COLD);
1928 1885
1929 ret = request_irq(vptr->pdev->irq, &velocity_intr, IRQF_SHARED, 1886 ret = request_irq(vptr->pdev->irq, &velocity_intr, IRQF_SHARED,
@@ -1988,6 +1945,8 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
1988 1945
1989 dev->mtu = new_mtu; 1946 dev->mtu = new_mtu;
1990 1947
1948 velocity_set_rxbufsize(vptr, new_mtu);
1949
1991 ret = velocity_init_rd_ring(vptr); 1950 ret = velocity_init_rd_ring(vptr);
1992 if (ret < 0) 1951 if (ret < 0)
1993 goto out_unlock; 1952 goto out_unlock;
@@ -2074,9 +2033,19 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
2074 struct tx_desc *td_ptr; 2033 struct tx_desc *td_ptr;
2075 struct velocity_td_info *tdinfo; 2034 struct velocity_td_info *tdinfo;
2076 unsigned long flags; 2035 unsigned long flags;
2077 int index;
2078 int pktlen = skb->len; 2036 int pktlen = skb->len;
2079 __le16 len = cpu_to_le16(pktlen); 2037 __le16 len;
2038 int index;
2039
2040
2041
2042 if (skb->len < ETH_ZLEN) {
2043 if (skb_padto(skb, ETH_ZLEN))
2044 goto out;
2045 pktlen = ETH_ZLEN;
2046 }
2047
2048 len = cpu_to_le16(pktlen);
2080 2049
2081#ifdef VELOCITY_ZERO_COPY_SUPPORT 2050#ifdef VELOCITY_ZERO_COPY_SUPPORT
2082 if (skb_shinfo(skb)->nr_frags > 6 && __skb_linearize(skb)) { 2051 if (skb_shinfo(skb)->nr_frags > 6 && __skb_linearize(skb)) {
@@ -2094,23 +2063,6 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
2094 td_ptr->tdesc1.TCR = TCR0_TIC; 2063 td_ptr->tdesc1.TCR = TCR0_TIC;
2095 td_ptr->td_buf[0].size &= ~TD_QUEUE; 2064 td_ptr->td_buf[0].size &= ~TD_QUEUE;
2096 2065
2097 /*
2098 * Pad short frames.
2099 */
2100 if (pktlen < ETH_ZLEN) {
2101 /* Cannot occur until ZC support */
2102 pktlen = ETH_ZLEN;
2103 len = cpu_to_le16(ETH_ZLEN);
2104 skb_copy_from_linear_data(skb, tdinfo->buf, skb->len);
2105 memset(tdinfo->buf + skb->len, 0, ETH_ZLEN - skb->len);
2106 tdinfo->skb = skb;
2107 tdinfo->skb_dma[0] = tdinfo->buf_dma;
2108 td_ptr->tdesc0.len = len;
2109 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
2110 td_ptr->td_buf[0].pa_high = 0;
2111 td_ptr->td_buf[0].size = len; /* queue is 0 anyway */
2112 tdinfo->nskb_dma = 1;
2113 } else
2114#ifdef VELOCITY_ZERO_COPY_SUPPORT 2066#ifdef VELOCITY_ZERO_COPY_SUPPORT
2115 if (skb_shinfo(skb)->nr_frags > 0) { 2067 if (skb_shinfo(skb)->nr_frags > 0) {
2116 int nfrags = skb_shinfo(skb)->nr_frags; 2068 int nfrags = skb_shinfo(skb)->nr_frags;
@@ -2202,7 +2154,8 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
2202 } 2154 }
2203 dev->trans_start = jiffies; 2155 dev->trans_start = jiffies;
2204 spin_unlock_irqrestore(&vptr->lock, flags); 2156 spin_unlock_irqrestore(&vptr->lock, flags);
2205 return 0; 2157out:
2158 return NETDEV_TX_OK;
2206} 2159}
2207 2160
2208/** 2161/**
diff --git a/drivers/net/via-velocity.h b/drivers/net/via-velocity.h
index 7387be4f428d..86446147284c 100644
--- a/drivers/net/via-velocity.h
+++ b/drivers/net/via-velocity.h
@@ -236,10 +236,8 @@ struct velocity_rd_info {
236 236
237struct velocity_td_info { 237struct velocity_td_info {
238 struct sk_buff *skb; 238 struct sk_buff *skb;
239 u8 *buf;
240 int nskb_dma; 239 int nskb_dma;
241 dma_addr_t skb_dma[7]; 240 dma_addr_t skb_dma[7];
242 dma_addr_t buf_dma;
243}; 241};
244 242
245enum velocity_owner { 243enum velocity_owner {
@@ -1506,9 +1504,6 @@ struct velocity_info {
1506 dma_addr_t rd_pool_dma; 1504 dma_addr_t rd_pool_dma;
1507 dma_addr_t td_pool_dma[TX_QUEUE_NO]; 1505 dma_addr_t td_pool_dma[TX_QUEUE_NO];
1508 1506
1509 dma_addr_t tx_bufs_dma;
1510 u8 *tx_bufs;
1511
1512 struct vlan_group *vlgrp; 1507 struct vlan_group *vlgrp;
1513 u8 ip_addr[4]; 1508 u8 ip_addr[4];
1514 enum chip_type chip_id; 1509 enum chip_type chip_id;
diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c
index 4452306d5328..c28d7cb2035b 100644
--- a/drivers/net/virtio_net.c
+++ b/drivers/net/virtio_net.c
@@ -550,7 +550,8 @@ static struct virtio_device_id id_table[] = {
550}; 550};
551 551
552static unsigned int features[] = { 552static unsigned int features[] = {
553 VIRTIO_NET_F_CSUM, VIRTIO_NET_F_GSO, VIRTIO_NET_F_MAC, 553 VIRTIO_NET_F_CSUM, VIRTIO_NET_F_GUEST_CSUM,
554 VIRTIO_NET_F_GSO, VIRTIO_NET_F_MAC,
554 VIRTIO_NET_F_HOST_TSO4, VIRTIO_NET_F_HOST_UFO, VIRTIO_NET_F_HOST_TSO6, 555 VIRTIO_NET_F_HOST_TSO4, VIRTIO_NET_F_HOST_UFO, VIRTIO_NET_F_HOST_TSO6,
555 VIRTIO_NET_F_HOST_ECN, VIRTIO_F_NOTIFY_ON_EMPTY, 556 VIRTIO_NET_F_HOST_ECN, VIRTIO_F_NOTIFY_ON_EMPTY,
556}; 557};
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index d5140aed7b79..846be60e7821 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -390,8 +390,7 @@ config WAN_ROUTER_DRIVERS
390 390
391 Select driver your card and remember to say Y to "Wan Router." 391 Select driver your card and remember to say Y to "Wan Router."
392 You will need the wan-tools package which is available from 392 You will need the wan-tools package which is available from
393 <ftp://ftp.sangoma.com/>. For more information read: 393 <ftp://ftp.sangoma.com/>.
394 <file:Documentation/networking/wan-router.txt>.
395 394
396 Note that the answer to this question won't directly affect the 395 Note that the answer to this question won't directly affect the
397 kernel except for how subordinate drivers may be built: 396 kernel except for how subordinate drivers may be built:
diff --git a/drivers/net/wan/c101.c b/drivers/net/wan/c101.c
index c2cc42f723d5..c8e563106a4a 100644
--- a/drivers/net/wan/c101.c
+++ b/drivers/net/wan/c101.c
@@ -133,9 +133,9 @@ static void sca_msci_intr(port_t *port)
133 sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port); 133 sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port);
134 134
135 if (stat & ST1_UDRN) { 135 if (stat & ST1_UDRN) {
136 struct net_device_stats *stats = hdlc_stats(port_to_dev(port)); 136 /* TX Underrun error detected */
137 stats->tx_errors++; /* TX Underrun error detected */ 137 port_to_dev(port)->stats.tx_errors++;
138 stats->tx_fifo_errors++; 138 port_to_dev(port)->stats.tx_fifo_errors++;
139 } 139 }
140 140
141 stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */ 141 stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */
diff --git a/drivers/net/wan/dscc4.c b/drivers/net/wan/dscc4.c
index c6f26e28e376..50ef5b4efd6d 100644
--- a/drivers/net/wan/dscc4.c
+++ b/drivers/net/wan/dscc4.c
@@ -642,7 +642,6 @@ static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
642 struct net_device *dev) 642 struct net_device *dev)
643{ 643{
644 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE; 644 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
645 struct net_device_stats *stats = hdlc_stats(dev);
646 struct pci_dev *pdev = dpriv->pci_priv->pdev; 645 struct pci_dev *pdev = dpriv->pci_priv->pdev;
647 struct sk_buff *skb; 646 struct sk_buff *skb;
648 int pkt_len; 647 int pkt_len;
@@ -656,8 +655,8 @@ static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
656 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data), 655 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
657 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE); 656 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
658 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) { 657 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
659 stats->rx_packets++; 658 dev->stats.rx_packets++;
660 stats->rx_bytes += pkt_len; 659 dev->stats.rx_bytes += pkt_len;
661 skb_put(skb, pkt_len); 660 skb_put(skb, pkt_len);
662 if (netif_running(dev)) 661 if (netif_running(dev))
663 skb->protocol = hdlc_type_trans(skb, dev); 662 skb->protocol = hdlc_type_trans(skb, dev);
@@ -665,13 +664,13 @@ static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
665 netif_rx(skb); 664 netif_rx(skb);
666 } else { 665 } else {
667 if (skb->data[pkt_len] & FrameRdo) 666 if (skb->data[pkt_len] & FrameRdo)
668 stats->rx_fifo_errors++; 667 dev->stats.rx_fifo_errors++;
669 else if (!(skb->data[pkt_len] | ~FrameCrc)) 668 else if (!(skb->data[pkt_len] | ~FrameCrc))
670 stats->rx_crc_errors++; 669 dev->stats.rx_crc_errors++;
671 else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab))) 670 else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
672 stats->rx_length_errors++; 671 dev->stats.rx_length_errors++;
673 else 672 else
674 stats->rx_errors++; 673 dev->stats.rx_errors++;
675 dev_kfree_skb_irq(skb); 674 dev_kfree_skb_irq(skb);
676 } 675 }
677refill: 676refill:
@@ -1569,7 +1568,6 @@ try:
1569 1568
1570 if (state & SccEvt) { 1569 if (state & SccEvt) {
1571 if (state & Alls) { 1570 if (state & Alls) {
1572 struct net_device_stats *stats = hdlc_stats(dev);
1573 struct sk_buff *skb; 1571 struct sk_buff *skb;
1574 struct TxFD *tx_fd; 1572 struct TxFD *tx_fd;
1575 1573
@@ -1586,8 +1584,8 @@ try:
1586 pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data), 1584 pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data),
1587 skb->len, PCI_DMA_TODEVICE); 1585 skb->len, PCI_DMA_TODEVICE);
1588 if (tx_fd->state & FrameEnd) { 1586 if (tx_fd->state & FrameEnd) {
1589 stats->tx_packets++; 1587 dev->stats.tx_packets++;
1590 stats->tx_bytes += skb->len; 1588 dev->stats.tx_bytes += skb->len;
1591 } 1589 }
1592 dev_kfree_skb_irq(skb); 1590 dev_kfree_skb_irq(skb);
1593 dpriv->tx_skbuff[cur] = NULL; 1591 dpriv->tx_skbuff[cur] = NULL;
@@ -1698,7 +1696,7 @@ try:
1698 } 1696 }
1699 if (state & Err) { 1697 if (state & Err) {
1700 printk(KERN_INFO "%s: Tx ERR\n", dev->name); 1698 printk(KERN_INFO "%s: Tx ERR\n", dev->name);
1701 hdlc_stats(dev)->tx_errors++; 1699 dev->stats.tx_errors++;
1702 state &= ~Err; 1700 state &= ~Err;
1703 } 1701 }
1704 } 1702 }
@@ -1834,7 +1832,7 @@ try:
1834 if (!(rx_fd->state2 & DataComplete)) 1832 if (!(rx_fd->state2 & DataComplete))
1835 break; 1833 break;
1836 if (rx_fd->state2 & FrameAborted) { 1834 if (rx_fd->state2 & FrameAborted) {
1837 hdlc_stats(dev)->rx_over_errors++; 1835 dev->stats.rx_over_errors++;
1838 rx_fd->state1 |= Hold; 1836 rx_fd->state1 |= Hold;
1839 rx_fd->state2 = 0x00000000; 1837 rx_fd->state2 = 0x00000000;
1840 rx_fd->end = cpu_to_le32(0xbabeface); 1838 rx_fd->end = cpu_to_le32(0xbabeface);
diff --git a/drivers/net/wan/farsync.c b/drivers/net/wan/farsync.c
index 547368e9633d..754f00809e3e 100644
--- a/drivers/net/wan/farsync.c
+++ b/drivers/net/wan/farsync.c
@@ -845,7 +845,6 @@ fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
845 int len, int txpos) 845 int len, int txpos)
846{ 846{
847 struct net_device *dev = port_to_dev(port); 847 struct net_device *dev = port_to_dev(port);
848 struct net_device_stats *stats = hdlc_stats(dev);
849 848
850 /* 849 /*
851 * Everything is now set, just tell the card to go 850 * Everything is now set, just tell the card to go
@@ -853,8 +852,8 @@ fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
853 dbg(DBG_TX, "fst_tx_dma_complete\n"); 852 dbg(DBG_TX, "fst_tx_dma_complete\n");
854 FST_WRB(card, txDescrRing[port->index][txpos].bits, 853 FST_WRB(card, txDescrRing[port->index][txpos].bits,
855 DMA_OWN | TX_STP | TX_ENP); 854 DMA_OWN | TX_STP | TX_ENP);
856 stats->tx_packets++; 855 dev->stats.tx_packets++;
857 stats->tx_bytes += len; 856 dev->stats.tx_bytes += len;
858 dev->trans_start = jiffies; 857 dev->trans_start = jiffies;
859} 858}
860 859
@@ -876,7 +875,6 @@ fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
876 int len, struct sk_buff *skb, int rxp) 875 int len, struct sk_buff *skb, int rxp)
877{ 876{
878 struct net_device *dev = port_to_dev(port); 877 struct net_device *dev = port_to_dev(port);
879 struct net_device_stats *stats = hdlc_stats(dev);
880 int pi; 878 int pi;
881 int rx_status; 879 int rx_status;
882 880
@@ -888,8 +886,8 @@ fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
888 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 886 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
889 887
890 /* Update stats */ 888 /* Update stats */
891 stats->rx_packets++; 889 dev->stats.rx_packets++;
892 stats->rx_bytes += len; 890 dev->stats.rx_bytes += len;
893 891
894 /* Push upstream */ 892 /* Push upstream */
895 dbg(DBG_RX, "Pushing the frame up the stack\n"); 893 dbg(DBG_RX, "Pushing the frame up the stack\n");
@@ -900,7 +898,7 @@ fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
900 rx_status = netif_rx(skb); 898 rx_status = netif_rx(skb);
901 fst_process_rx_status(rx_status, port_to_dev(port)->name); 899 fst_process_rx_status(rx_status, port_to_dev(port)->name);
902 if (rx_status == NET_RX_DROP) 900 if (rx_status == NET_RX_DROP)
903 stats->rx_dropped++; 901 dev->stats.rx_dropped++;
904 dev->last_rx = jiffies; 902 dev->last_rx = jiffies;
905} 903}
906 904
@@ -1163,29 +1161,28 @@ fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1163 unsigned char dmabits, int rxp, unsigned short len) 1161 unsigned char dmabits, int rxp, unsigned short len)
1164{ 1162{
1165 struct net_device *dev = port_to_dev(port); 1163 struct net_device *dev = port_to_dev(port);
1166 struct net_device_stats *stats = hdlc_stats(dev);
1167 1164
1168 /* 1165 /*
1169 * Increment the appropriate error counter 1166 * Increment the appropriate error counter
1170 */ 1167 */
1171 stats->rx_errors++; 1168 dev->stats.rx_errors++;
1172 if (dmabits & RX_OFLO) { 1169 if (dmabits & RX_OFLO) {
1173 stats->rx_fifo_errors++; 1170 dev->stats.rx_fifo_errors++;
1174 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n", 1171 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1175 card->card_no, port->index, rxp); 1172 card->card_no, port->index, rxp);
1176 } 1173 }
1177 if (dmabits & RX_CRC) { 1174 if (dmabits & RX_CRC) {
1178 stats->rx_crc_errors++; 1175 dev->stats.rx_crc_errors++;
1179 dbg(DBG_ASS, "Rx crc error on card %d port %d\n", 1176 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1180 card->card_no, port->index); 1177 card->card_no, port->index);
1181 } 1178 }
1182 if (dmabits & RX_FRAM) { 1179 if (dmabits & RX_FRAM) {
1183 stats->rx_frame_errors++; 1180 dev->stats.rx_frame_errors++;
1184 dbg(DBG_ASS, "Rx frame error on card %d port %d\n", 1181 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1185 card->card_no, port->index); 1182 card->card_no, port->index);
1186 } 1183 }
1187 if (dmabits == (RX_STP | RX_ENP)) { 1184 if (dmabits == (RX_STP | RX_ENP)) {
1188 stats->rx_length_errors++; 1185 dev->stats.rx_length_errors++;
1189 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n", 1186 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1190 len, card->card_no, port->index); 1187 len, card->card_no, port->index);
1191 } 1188 }
@@ -1242,7 +1239,6 @@ fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1242 unsigned short len; 1239 unsigned short len;
1243 struct sk_buff *skb; 1240 struct sk_buff *skb;
1244 struct net_device *dev = port_to_dev(port); 1241 struct net_device *dev = port_to_dev(port);
1245 struct net_device_stats *stats = hdlc_stats(dev);
1246 1242
1247 /* Check we have a buffer to process */ 1243 /* Check we have a buffer to process */
1248 pi = port->index; 1244 pi = port->index;
@@ -1291,7 +1287,7 @@ fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1291 if ((skb = dev_alloc_skb(len)) == NULL) { 1287 if ((skb = dev_alloc_skb(len)) == NULL) {
1292 dbg(DBG_RX, "intr_rx: can't allocate buffer\n"); 1288 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1293 1289
1294 stats->rx_dropped++; 1290 dev->stats.rx_dropped++;
1295 1291
1296 /* Return descriptor to card */ 1292 /* Return descriptor to card */
1297 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1293 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
@@ -1316,8 +1312,8 @@ fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1316 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1312 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1317 1313
1318 /* Update stats */ 1314 /* Update stats */
1319 stats->rx_packets++; 1315 dev->stats.rx_packets++;
1320 stats->rx_bytes += len; 1316 dev->stats.rx_bytes += len;
1321 1317
1322 /* Push upstream */ 1318 /* Push upstream */
1323 dbg(DBG_RX, "Pushing frame up the stack\n"); 1319 dbg(DBG_RX, "Pushing frame up the stack\n");
@@ -1327,9 +1323,8 @@ fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1327 skb->protocol = hdlc_type_trans(skb, dev); 1323 skb->protocol = hdlc_type_trans(skb, dev);
1328 rx_status = netif_rx(skb); 1324 rx_status = netif_rx(skb);
1329 fst_process_rx_status(rx_status, port_to_dev(port)->name); 1325 fst_process_rx_status(rx_status, port_to_dev(port)->name);
1330 if (rx_status == NET_RX_DROP) { 1326 if (rx_status == NET_RX_DROP)
1331 stats->rx_dropped++; 1327 dev->stats.rx_dropped++;
1332 }
1333 dev->last_rx = jiffies; 1328 dev->last_rx = jiffies;
1334 } else { 1329 } else {
1335 card->dma_skb_rx = skb; 1330 card->dma_skb_rx = skb;
@@ -1361,7 +1356,6 @@ do_bottom_half_tx(struct fst_card_info *card)
1361 struct sk_buff *skb; 1356 struct sk_buff *skb;
1362 unsigned long flags; 1357 unsigned long flags;
1363 struct net_device *dev; 1358 struct net_device *dev;
1364 struct net_device_stats *stats;
1365 1359
1366 /* 1360 /*
1367 * Find a free buffer for the transmit 1361 * Find a free buffer for the transmit
@@ -1373,12 +1367,10 @@ do_bottom_half_tx(struct fst_card_info *card)
1373 if (!port->run) 1367 if (!port->run)
1374 continue; 1368 continue;
1375 1369
1376 dev = port_to_dev(port); 1370 dev = port_to_dev(port);
1377 stats = hdlc_stats(dev); 1371 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1378 while (! 1372 DMA_OWN)
1379 (FST_RDB(card, txDescrRing[pi][port->txpos].bits) & 1373 && !(card->dmatx_in_progress)) {
1380 DMA_OWN)
1381 && !(card->dmatx_in_progress)) {
1382 /* 1374 /*
1383 * There doesn't seem to be a txdone event per-se 1375 * There doesn't seem to be a txdone event per-se
1384 * We seem to have to deduce it, by checking the DMA_OWN 1376 * We seem to have to deduce it, by checking the DMA_OWN
@@ -1422,8 +1414,8 @@ do_bottom_half_tx(struct fst_card_info *card)
1422 txDescrRing[pi][port->txpos]. 1414 txDescrRing[pi][port->txpos].
1423 bits, 1415 bits,
1424 DMA_OWN | TX_STP | TX_ENP); 1416 DMA_OWN | TX_STP | TX_ENP);
1425 stats->tx_packets++; 1417 dev->stats.tx_packets++;
1426 stats->tx_bytes += skb->len; 1418 dev->stats.tx_bytes += skb->len;
1427 dev->trans_start = jiffies; 1419 dev->trans_start = jiffies;
1428 } else { 1420 } else {
1429 /* Or do it through dma */ 1421 /* Or do it through dma */
@@ -1628,8 +1620,8 @@ fst_intr(int dummy, void *dev_id)
1628 * always load up the entire packet for DMA. 1620 * always load up the entire packet for DMA.
1629 */ 1621 */
1630 dbg(DBG_TX, "Tx underflow port %d\n", port->index); 1622 dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1631 hdlc_stats(port_to_dev(port))->tx_errors++; 1623 port_to_dev(port)->stats.tx_errors++;
1632 hdlc_stats(port_to_dev(port))->tx_fifo_errors++; 1624 port_to_dev(port)->stats.tx_fifo_errors++;
1633 dbg(DBG_ASS, "Tx underflow on card %d port %d\n", 1625 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1634 card->card_no, port->index); 1626 card->card_no, port->index);
1635 break; 1627 break;
@@ -2292,12 +2284,11 @@ fst_tx_timeout(struct net_device *dev)
2292{ 2284{
2293 struct fst_port_info *port; 2285 struct fst_port_info *port;
2294 struct fst_card_info *card; 2286 struct fst_card_info *card;
2295 struct net_device_stats *stats = hdlc_stats(dev);
2296 2287
2297 port = dev_to_port(dev); 2288 port = dev_to_port(dev);
2298 card = port->card; 2289 card = port->card;
2299 stats->tx_errors++; 2290 dev->stats.tx_errors++;
2300 stats->tx_aborted_errors++; 2291 dev->stats.tx_aborted_errors++;
2301 dbg(DBG_ASS, "Tx timeout card %d port %d\n", 2292 dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2302 card->card_no, port->index); 2293 card->card_no, port->index);
2303 fst_issue_cmd(port, ABORTTX); 2294 fst_issue_cmd(port, ABORTTX);
@@ -2312,7 +2303,6 @@ fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2312{ 2303{
2313 struct fst_card_info *card; 2304 struct fst_card_info *card;
2314 struct fst_port_info *port; 2305 struct fst_port_info *port;
2315 struct net_device_stats *stats = hdlc_stats(dev);
2316 unsigned long flags; 2306 unsigned long flags;
2317 int txq_length; 2307 int txq_length;
2318 2308
@@ -2323,8 +2313,8 @@ fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2323 /* Drop packet with error if we don't have carrier */ 2313 /* Drop packet with error if we don't have carrier */
2324 if (!netif_carrier_ok(dev)) { 2314 if (!netif_carrier_ok(dev)) {
2325 dev_kfree_skb(skb); 2315 dev_kfree_skb(skb);
2326 stats->tx_errors++; 2316 dev->stats.tx_errors++;
2327 stats->tx_carrier_errors++; 2317 dev->stats.tx_carrier_errors++;
2328 dbg(DBG_ASS, 2318 dbg(DBG_ASS,
2329 "Tried to transmit but no carrier on card %d port %d\n", 2319 "Tried to transmit but no carrier on card %d port %d\n",
2330 card->card_no, port->index); 2320 card->card_no, port->index);
@@ -2336,7 +2326,7 @@ fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2336 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len, 2326 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2337 LEN_TX_BUFFER); 2327 LEN_TX_BUFFER);
2338 dev_kfree_skb(skb); 2328 dev_kfree_skb(skb);
2339 stats->tx_errors++; 2329 dev->stats.tx_errors++;
2340 return 0; 2330 return 0;
2341 } 2331 }
2342 2332
@@ -2368,7 +2358,7 @@ fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2368 * This shouldn't have happened but such is life 2358 * This shouldn't have happened but such is life
2369 */ 2359 */
2370 dev_kfree_skb(skb); 2360 dev_kfree_skb(skb);
2371 stats->tx_errors++; 2361 dev->stats.tx_errors++;
2372 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n", 2362 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2373 card->card_no, port->index); 2363 card->card_no, port->index);
2374 return 0; 2364 return 0;
diff --git a/drivers/net/wan/hd6457x.c b/drivers/net/wan/hd6457x.c
index 8d0a1f2f00e5..591fb45a7c68 100644
--- a/drivers/net/wan/hd6457x.c
+++ b/drivers/net/wan/hd6457x.c
@@ -271,9 +271,9 @@ static inline void sca_msci_intr(port_t *port)
271 sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card); 271 sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
272 272
273 if (stat & ST1_UDRN) { 273 if (stat & ST1_UDRN) {
274 struct net_device_stats *stats = hdlc_stats(port_to_dev(port)); 274 /* TX Underrun error detected */
275 stats->tx_errors++; /* TX Underrun error detected */ 275 port_to_dev(port)->stats.tx_errors++;
276 stats->tx_fifo_errors++; 276 port_to_dev(port)->stats.tx_fifo_errors++;
277 } 277 }
278 278
279 if (stat & ST1_CDCD) 279 if (stat & ST1_CDCD)
@@ -286,7 +286,6 @@ static inline void sca_msci_intr(port_t *port)
286static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, u16 rxin) 286static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, u16 rxin)
287{ 287{
288 struct net_device *dev = port_to_dev(port); 288 struct net_device *dev = port_to_dev(port);
289 struct net_device_stats *stats = hdlc_stats(dev);
290 struct sk_buff *skb; 289 struct sk_buff *skb;
291 u16 len; 290 u16 len;
292 u32 buff; 291 u32 buff;
@@ -298,7 +297,7 @@ static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, u1
298 len = readw(&desc->len); 297 len = readw(&desc->len);
299 skb = dev_alloc_skb(len); 298 skb = dev_alloc_skb(len);
300 if (!skb) { 299 if (!skb) {
301 stats->rx_dropped++; 300 dev->stats.rx_dropped++;
302 return; 301 return;
303 } 302 }
304 303
@@ -327,8 +326,8 @@ static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, u1
327 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len); 326 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
328 debug_frame(skb); 327 debug_frame(skb);
329#endif 328#endif
330 stats->rx_packets++; 329 dev->stats.rx_packets++;
331 stats->rx_bytes += skb->len; 330 dev->stats.rx_bytes += skb->len;
332 dev->last_rx = jiffies; 331 dev->last_rx = jiffies;
333 skb->protocol = hdlc_type_trans(skb, dev); 332 skb->protocol = hdlc_type_trans(skb, dev);
334 netif_rx(skb); 333 netif_rx(skb);
@@ -339,17 +338,18 @@ static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, u1
339/* Receive DMA interrupt service */ 338/* Receive DMA interrupt service */
340static inline void sca_rx_intr(port_t *port) 339static inline void sca_rx_intr(port_t *port)
341{ 340{
341 struct net_device *dev = port_to_dev(port);
342 u16 dmac = get_dmac_rx(port); 342 u16 dmac = get_dmac_rx(port);
343 card_t *card = port_to_card(port); 343 card_t *card = port_to_card(port);
344 u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */ 344 u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
345 struct net_device_stats *stats = hdlc_stats(port_to_dev(port));
346 345
347 /* Reset DSR status bits */ 346 /* Reset DSR status bits */
348 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 347 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
349 DSR_RX(phy_node(port)), card); 348 DSR_RX(phy_node(port)), card);
350 349
351 if (stat & DSR_BOF) 350 if (stat & DSR_BOF)
352 stats->rx_over_errors++; /* Dropped one or more frames */ 351 /* Dropped one or more frames */
352 dev->stats.rx_over_errors++;
353 353
354 while (1) { 354 while (1) {
355 u32 desc_off = desc_offset(port, port->rxin, 0); 355 u32 desc_off = desc_offset(port, port->rxin, 0);
@@ -364,12 +364,14 @@ static inline void sca_rx_intr(port_t *port)
364 if (!(stat & ST_RX_EOM)) 364 if (!(stat & ST_RX_EOM))
365 port->rxpart = 1; /* partial frame received */ 365 port->rxpart = 1; /* partial frame received */
366 else if ((stat & ST_ERROR_MASK) || port->rxpart) { 366 else if ((stat & ST_ERROR_MASK) || port->rxpart) {
367 stats->rx_errors++; 367 dev->stats.rx_errors++;
368 if (stat & ST_RX_OVERRUN) stats->rx_fifo_errors++; 368 if (stat & ST_RX_OVERRUN)
369 dev->stats.rx_fifo_errors++;
369 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | 370 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
370 ST_RX_RESBIT)) || port->rxpart) 371 ST_RX_RESBIT)) || port->rxpart)
371 stats->rx_frame_errors++; 372 dev->stats.rx_frame_errors++;
372 else if (stat & ST_RX_CRC) stats->rx_crc_errors++; 373 else if (stat & ST_RX_CRC)
374 dev->stats.rx_crc_errors++;
373 if (stat & ST_RX_EOM) 375 if (stat & ST_RX_EOM)
374 port->rxpart = 0; /* received last fragment */ 376 port->rxpart = 0; /* received last fragment */
375 } else 377 } else
@@ -390,7 +392,6 @@ static inline void sca_rx_intr(port_t *port)
390static inline void sca_tx_intr(port_t *port) 392static inline void sca_tx_intr(port_t *port)
391{ 393{
392 struct net_device *dev = port_to_dev(port); 394 struct net_device *dev = port_to_dev(port);
393 struct net_device_stats *stats = hdlc_stats(dev);
394 u16 dmac = get_dmac_tx(port); 395 u16 dmac = get_dmac_tx(port);
395 card_t* card = port_to_card(port); 396 card_t* card = port_to_card(port);
396 u8 stat; 397 u8 stat;
@@ -412,8 +413,8 @@ static inline void sca_tx_intr(port_t *port)
412 break; /* Transmitter is/will_be sending this frame */ 413 break; /* Transmitter is/will_be sending this frame */
413 414
414 desc = desc_address(port, port->txlast, 1); 415 desc = desc_address(port, port->txlast, 1);
415 stats->tx_packets++; 416 dev->stats.tx_packets++;
416 stats->tx_bytes += readw(&desc->len); 417 dev->stats.tx_bytes += readw(&desc->len);
417 writeb(0, &desc->stat); /* Free descriptor */ 418 writeb(0, &desc->stat); /* Free descriptor */
418 port->txlast = next_desc(port, port->txlast, 1); 419 port->txlast = next_desc(port, port->txlast, 1);
419 } 420 }
diff --git a/drivers/net/wan/hdlc.c b/drivers/net/wan/hdlc.c
index 7f984895b0d5..e3a536477c7e 100644
--- a/drivers/net/wan/hdlc.c
+++ b/drivers/net/wan/hdlc.c
@@ -57,7 +57,7 @@ static int hdlc_change_mtu(struct net_device *dev, int new_mtu)
57 57
58static struct net_device_stats *hdlc_get_stats(struct net_device *dev) 58static struct net_device_stats *hdlc_get_stats(struct net_device *dev)
59{ 59{
60 return hdlc_stats(dev); 60 return &dev->stats;
61} 61}
62 62
63 63
diff --git a/drivers/net/wan/hdlc_cisco.c b/drivers/net/wan/hdlc_cisco.c
index 762d21c1c703..849819c2552d 100644
--- a/drivers/net/wan/hdlc_cisco.c
+++ b/drivers/net/wan/hdlc_cisco.c
@@ -252,8 +252,8 @@ static int cisco_rx(struct sk_buff *skb)
252 dev_kfree_skb_any(skb); 252 dev_kfree_skb_any(skb);
253 return NET_RX_DROP; 253 return NET_RX_DROP;
254 254
255 rx_error: 255rx_error:
256 dev_to_hdlc(dev)->stats.rx_errors++; /* Mark error */ 256 dev->stats.rx_errors++; /* Mark error */
257 dev_kfree_skb_any(skb); 257 dev_kfree_skb_any(skb);
258 return NET_RX_DROP; 258 return NET_RX_DROP;
259} 259}
diff --git a/drivers/net/wan/hdlc_fr.c b/drivers/net/wan/hdlc_fr.c
index 6d35155c7145..62e93dac6b13 100644
--- a/drivers/net/wan/hdlc_fr.c
+++ b/drivers/net/wan/hdlc_fr.c
@@ -135,11 +135,6 @@ typedef struct pvc_device_struct {
135 }state; 135 }state;
136}pvc_device; 136}pvc_device;
137 137
138struct pvc_desc {
139 struct net_device_stats stats;
140 pvc_device *pvc;
141};
142
143struct frad_state { 138struct frad_state {
144 fr_proto settings; 139 fr_proto settings;
145 pvc_device *first_pvc; 140 pvc_device *first_pvc;
@@ -179,15 +174,6 @@ static inline struct frad_state* state(hdlc_device *hdlc)
179 return(struct frad_state *)(hdlc->state); 174 return(struct frad_state *)(hdlc->state);
180} 175}
181 176
182static inline struct pvc_desc* pvcdev_to_desc(struct net_device *dev)
183{
184 return dev->priv;
185}
186
187static inline struct net_device_stats* pvc_get_stats(struct net_device *dev)
188{
189 return &pvcdev_to_desc(dev)->stats;
190}
191 177
192static inline pvc_device* find_pvc(hdlc_device *hdlc, u16 dlci) 178static inline pvc_device* find_pvc(hdlc_device *hdlc, u16 dlci)
193{ 179{
@@ -357,7 +343,7 @@ static int fr_hard_header(struct sk_buff **skb_p, u16 dlci)
357 343
358static int pvc_open(struct net_device *dev) 344static int pvc_open(struct net_device *dev)
359{ 345{
360 pvc_device *pvc = pvcdev_to_desc(dev)->pvc; 346 pvc_device *pvc = dev->priv;
361 347
362 if ((pvc->frad->flags & IFF_UP) == 0) 348 if ((pvc->frad->flags & IFF_UP) == 0)
363 return -EIO; /* Frad must be UP in order to activate PVC */ 349 return -EIO; /* Frad must be UP in order to activate PVC */
@@ -377,7 +363,7 @@ static int pvc_open(struct net_device *dev)
377 363
378static int pvc_close(struct net_device *dev) 364static int pvc_close(struct net_device *dev)
379{ 365{
380 pvc_device *pvc = pvcdev_to_desc(dev)->pvc; 366 pvc_device *pvc = dev->priv;
381 367
382 if (--pvc->open_count == 0) { 368 if (--pvc->open_count == 0) {
383 hdlc_device *hdlc = dev_to_hdlc(pvc->frad); 369 hdlc_device *hdlc = dev_to_hdlc(pvc->frad);
@@ -396,7 +382,7 @@ static int pvc_close(struct net_device *dev)
396 382
397static int pvc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 383static int pvc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
398{ 384{
399 pvc_device *pvc = pvcdev_to_desc(dev)->pvc; 385 pvc_device *pvc = dev->priv;
400 fr_proto_pvc_info info; 386 fr_proto_pvc_info info;
401 387
402 if (ifr->ifr_settings.type == IF_GET_PROTO) { 388 if (ifr->ifr_settings.type == IF_GET_PROTO) {
@@ -424,8 +410,7 @@ static int pvc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
424 410
425static int pvc_xmit(struct sk_buff *skb, struct net_device *dev) 411static int pvc_xmit(struct sk_buff *skb, struct net_device *dev)
426{ 412{
427 pvc_device *pvc = pvcdev_to_desc(dev)->pvc; 413 pvc_device *pvc = dev->priv;
428 struct net_device_stats *stats = pvc_get_stats(dev);
429 414
430 if (pvc->state.active) { 415 if (pvc->state.active) {
431 if (dev->type == ARPHRD_ETHER) { 416 if (dev->type == ARPHRD_ETHER) {
@@ -435,7 +420,7 @@ static int pvc_xmit(struct sk_buff *skb, struct net_device *dev)
435 if (skb_tailroom(skb) < pad) 420 if (skb_tailroom(skb) < pad)
436 if (pskb_expand_head(skb, 0, pad, 421 if (pskb_expand_head(skb, 0, pad,
437 GFP_ATOMIC)) { 422 GFP_ATOMIC)) {
438 stats->tx_dropped++; 423 dev->stats.tx_dropped++;
439 dev_kfree_skb(skb); 424 dev_kfree_skb(skb);
440 return 0; 425 return 0;
441 } 426 }
@@ -445,17 +430,17 @@ static int pvc_xmit(struct sk_buff *skb, struct net_device *dev)
445 skb->protocol = __constant_htons(ETH_P_802_3); 430 skb->protocol = __constant_htons(ETH_P_802_3);
446 } 431 }
447 if (!fr_hard_header(&skb, pvc->dlci)) { 432 if (!fr_hard_header(&skb, pvc->dlci)) {
448 stats->tx_bytes += skb->len; 433 dev->stats.tx_bytes += skb->len;
449 stats->tx_packets++; 434 dev->stats.tx_packets++;
450 if (pvc->state.fecn) /* TX Congestion counter */ 435 if (pvc->state.fecn) /* TX Congestion counter */
451 stats->tx_compressed++; 436 dev->stats.tx_compressed++;
452 skb->dev = pvc->frad; 437 skb->dev = pvc->frad;
453 dev_queue_xmit(skb); 438 dev_queue_xmit(skb);
454 return 0; 439 return 0;
455 } 440 }
456 } 441 }
457 442
458 stats->tx_dropped++; 443 dev->stats.tx_dropped++;
459 dev_kfree_skb(skb); 444 dev_kfree_skb(skb);
460 return 0; 445 return 0;
461} 446}
@@ -955,7 +940,7 @@ static int fr_rx(struct sk_buff *skb)
955 940
956 941
957 if ((skb = skb_share_check(skb, GFP_ATOMIC)) == NULL) { 942 if ((skb = skb_share_check(skb, GFP_ATOMIC)) == NULL) {
958 dev_to_hdlc(frad)->stats.rx_dropped++; 943 frad->stats.rx_dropped++;
959 return NET_RX_DROP; 944 return NET_RX_DROP;
960 } 945 }
961 946
@@ -1003,11 +988,10 @@ static int fr_rx(struct sk_buff *skb)
1003 } 988 }
1004 989
1005 if (dev) { 990 if (dev) {
1006 struct net_device_stats *stats = pvc_get_stats(dev); 991 dev->stats.rx_packets++; /* PVC traffic */
1007 stats->rx_packets++; /* PVC traffic */ 992 dev->stats.rx_bytes += skb->len;
1008 stats->rx_bytes += skb->len;
1009 if (pvc->state.becn) 993 if (pvc->state.becn)
1010 stats->rx_compressed++; 994 dev->stats.rx_compressed++;
1011 skb->dev = dev; 995 skb->dev = dev;
1012 netif_rx(skb); 996 netif_rx(skb);
1013 return NET_RX_SUCCESS; 997 return NET_RX_SUCCESS;
@@ -1017,7 +1001,7 @@ static int fr_rx(struct sk_buff *skb)
1017 } 1001 }
1018 1002
1019 rx_error: 1003 rx_error:
1020 dev_to_hdlc(frad)->stats.rx_errors++; /* Mark error */ 1004 frad->stats.rx_errors++; /* Mark error */
1021 dev_kfree_skb_any(skb); 1005 dev_kfree_skb_any(skb);
1022 return NET_RX_DROP; 1006 return NET_RX_DROP;
1023} 1007}
@@ -1088,7 +1072,7 @@ static void pvc_setup(struct net_device *dev)
1088static int fr_add_pvc(struct net_device *frad, unsigned int dlci, int type) 1072static int fr_add_pvc(struct net_device *frad, unsigned int dlci, int type)
1089{ 1073{
1090 hdlc_device *hdlc = dev_to_hdlc(frad); 1074 hdlc_device *hdlc = dev_to_hdlc(frad);
1091 pvc_device *pvc = NULL; 1075 pvc_device *pvc;
1092 struct net_device *dev; 1076 struct net_device *dev;
1093 int result, used; 1077 int result, used;
1094 1078
@@ -1104,10 +1088,9 @@ static int fr_add_pvc(struct net_device *frad, unsigned int dlci, int type)
1104 used = pvc_is_used(pvc); 1088 used = pvc_is_used(pvc);
1105 1089
1106 if (type == ARPHRD_ETHER) 1090 if (type == ARPHRD_ETHER)
1107 dev = alloc_netdev(sizeof(struct pvc_desc), "pvceth%d", 1091 dev = alloc_netdev(0, "pvceth%d", ether_setup);
1108 ether_setup);
1109 else 1092 else
1110 dev = alloc_netdev(sizeof(struct pvc_desc), "pvc%d", pvc_setup); 1093 dev = alloc_netdev(0, "pvc%d", pvc_setup);
1111 1094
1112 if (!dev) { 1095 if (!dev) {
1113 printk(KERN_WARNING "%s: Memory squeeze on fr_pvc()\n", 1096 printk(KERN_WARNING "%s: Memory squeeze on fr_pvc()\n",
@@ -1123,14 +1106,13 @@ static int fr_add_pvc(struct net_device *frad, unsigned int dlci, int type)
1123 dlci_to_q922(dev->broadcast, dlci); 1106 dlci_to_q922(dev->broadcast, dlci);
1124 } 1107 }
1125 dev->hard_start_xmit = pvc_xmit; 1108 dev->hard_start_xmit = pvc_xmit;
1126 dev->get_stats = pvc_get_stats;
1127 dev->open = pvc_open; 1109 dev->open = pvc_open;
1128 dev->stop = pvc_close; 1110 dev->stop = pvc_close;
1129 dev->do_ioctl = pvc_ioctl; 1111 dev->do_ioctl = pvc_ioctl;
1130 dev->change_mtu = pvc_change_mtu; 1112 dev->change_mtu = pvc_change_mtu;
1131 dev->mtu = HDLC_MAX_MTU; 1113 dev->mtu = HDLC_MAX_MTU;
1132 dev->tx_queue_len = 0; 1114 dev->tx_queue_len = 0;
1133 pvcdev_to_desc(dev)->pvc = pvc; 1115 dev->priv = pvc;
1134 1116
1135 result = dev_alloc_name(dev, dev->name); 1117 result = dev_alloc_name(dev, dev->name);
1136 if (result < 0) { 1118 if (result < 0) {
diff --git a/drivers/net/wan/hdlc_raw_eth.c b/drivers/net/wan/hdlc_raw_eth.c
index d20c685f6711..26dee600506f 100644
--- a/drivers/net/wan/hdlc_raw_eth.c
+++ b/drivers/net/wan/hdlc_raw_eth.c
@@ -33,7 +33,7 @@ static int eth_tx(struct sk_buff *skb, struct net_device *dev)
33 int len = skb->len; 33 int len = skb->len;
34 if (skb_tailroom(skb) < pad) 34 if (skb_tailroom(skb) < pad)
35 if (pskb_expand_head(skb, 0, pad, GFP_ATOMIC)) { 35 if (pskb_expand_head(skb, 0, pad, GFP_ATOMIC)) {
36 hdlc_stats(dev)->tx_dropped++; 36 dev->stats.tx_dropped++;
37 dev_kfree_skb(skb); 37 dev_kfree_skb(skb);
38 return 0; 38 return 0;
39 } 39 }
diff --git a/drivers/net/wan/hdlc_x25.c b/drivers/net/wan/hdlc_x25.c
index c15cc11e399b..e808720030ef 100644
--- a/drivers/net/wan/hdlc_x25.c
+++ b/drivers/net/wan/hdlc_x25.c
@@ -164,17 +164,15 @@ static void x25_close(struct net_device *dev)
164 164
165static int x25_rx(struct sk_buff *skb) 165static int x25_rx(struct sk_buff *skb)
166{ 166{
167 struct hdlc_device *hdlc = dev_to_hdlc(skb->dev);
168
169 if ((skb = skb_share_check(skb, GFP_ATOMIC)) == NULL) { 167 if ((skb = skb_share_check(skb, GFP_ATOMIC)) == NULL) {
170 hdlc->stats.rx_dropped++; 168 skb->dev->stats.rx_dropped++;
171 return NET_RX_DROP; 169 return NET_RX_DROP;
172 } 170 }
173 171
174 if (lapb_data_received(skb->dev, skb) == LAPB_OK) 172 if (lapb_data_received(skb->dev, skb) == LAPB_OK)
175 return NET_RX_SUCCESS; 173 return NET_RX_SUCCESS;
176 174
177 hdlc->stats.rx_errors++; 175 skb->dev->stats.rx_errors++;
178 dev_kfree_skb_any(skb); 176 dev_kfree_skb_any(skb);
179 return NET_RX_DROP; 177 return NET_RX_DROP;
180} 178}
diff --git a/drivers/net/wan/pc300_drv.c b/drivers/net/wan/pc300_drv.c
index 57914fbd41d3..334170527755 100644
--- a/drivers/net/wan/pc300_drv.c
+++ b/drivers/net/wan/pc300_drv.c
@@ -285,7 +285,6 @@ static void rx_dma_buf_init(pc300_t *, int);
285static void tx_dma_buf_check(pc300_t *, int); 285static void tx_dma_buf_check(pc300_t *, int);
286static void rx_dma_buf_check(pc300_t *, int); 286static void rx_dma_buf_check(pc300_t *, int);
287static irqreturn_t cpc_intr(int, void *); 287static irqreturn_t cpc_intr(int, void *);
288static struct net_device_stats *cpc_get_stats(struct net_device *);
289static int clock_rate_calc(uclong, uclong, int *); 288static int clock_rate_calc(uclong, uclong, int *);
290static uclong detect_ram(pc300_t *); 289static uclong detect_ram(pc300_t *);
291static void plx_init(pc300_t *); 290static void plx_init(pc300_t *);
@@ -1775,13 +1774,12 @@ static void cpc_tx_timeout(struct net_device *dev)
1775 pc300dev_t *d = (pc300dev_t *) dev->priv; 1774 pc300dev_t *d = (pc300dev_t *) dev->priv;
1776 pc300ch_t *chan = (pc300ch_t *) d->chan; 1775 pc300ch_t *chan = (pc300ch_t *) d->chan;
1777 pc300_t *card = (pc300_t *) chan->card; 1776 pc300_t *card = (pc300_t *) chan->card;
1778 struct net_device_stats *stats = hdlc_stats(dev);
1779 int ch = chan->channel; 1777 int ch = chan->channel;
1780 unsigned long flags; 1778 unsigned long flags;
1781 ucchar ilar; 1779 ucchar ilar;
1782 1780
1783 stats->tx_errors++; 1781 dev->stats.tx_errors++;
1784 stats->tx_aborted_errors++; 1782 dev->stats.tx_aborted_errors++;
1785 CPC_LOCK(card, flags); 1783 CPC_LOCK(card, flags);
1786 if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) { 1784 if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1787 printk("%s: ILAR=0x%x\n", dev->name, ilar); 1785 printk("%s: ILAR=0x%x\n", dev->name, ilar);
@@ -1803,7 +1801,6 @@ static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1803 pc300dev_t *d = (pc300dev_t *) dev->priv; 1801 pc300dev_t *d = (pc300dev_t *) dev->priv;
1804 pc300ch_t *chan = (pc300ch_t *) d->chan; 1802 pc300ch_t *chan = (pc300ch_t *) d->chan;
1805 pc300_t *card = (pc300_t *) chan->card; 1803 pc300_t *card = (pc300_t *) chan->card;
1806 struct net_device_stats *stats = hdlc_stats(dev);
1807 int ch = chan->channel; 1804 int ch = chan->channel;
1808 unsigned long flags; 1805 unsigned long flags;
1809#ifdef PC300_DEBUG_TX 1806#ifdef PC300_DEBUG_TX
@@ -1817,13 +1814,13 @@ static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1817 } else if (!netif_carrier_ok(dev)) { 1814 } else if (!netif_carrier_ok(dev)) {
1818 /* DCD must be OFF: drop packet */ 1815 /* DCD must be OFF: drop packet */
1819 dev_kfree_skb(skb); 1816 dev_kfree_skb(skb);
1820 stats->tx_errors++; 1817 dev->stats.tx_errors++;
1821 stats->tx_carrier_errors++; 1818 dev->stats.tx_carrier_errors++;
1822 return 0; 1819 return 0;
1823 } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) { 1820 } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1824 printk("%s: DCD is OFF. Going administrative down.\n", dev->name); 1821 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1825 stats->tx_errors++; 1822 dev->stats.tx_errors++;
1826 stats->tx_carrier_errors++; 1823 dev->stats.tx_carrier_errors++;
1827 dev_kfree_skb(skb); 1824 dev_kfree_skb(skb);
1828 netif_carrier_off(dev); 1825 netif_carrier_off(dev);
1829 CPC_LOCK(card, flags); 1826 CPC_LOCK(card, flags);
@@ -1843,8 +1840,8 @@ static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1843// printk("%s: write error. Dropping TX packet.\n", dev->name); 1840// printk("%s: write error. Dropping TX packet.\n", dev->name);
1844 netif_stop_queue(dev); 1841 netif_stop_queue(dev);
1845 dev_kfree_skb(skb); 1842 dev_kfree_skb(skb);
1846 stats->tx_errors++; 1843 dev->stats.tx_errors++;
1847 stats->tx_dropped++; 1844 dev->stats.tx_dropped++;
1848 return 0; 1845 return 0;
1849 } 1846 }
1850#ifdef PC300_DEBUG_TX 1847#ifdef PC300_DEBUG_TX
@@ -1886,7 +1883,6 @@ static void cpc_net_rx(struct net_device *dev)
1886 pc300dev_t *d = (pc300dev_t *) dev->priv; 1883 pc300dev_t *d = (pc300dev_t *) dev->priv;
1887 pc300ch_t *chan = (pc300ch_t *) d->chan; 1884 pc300ch_t *chan = (pc300ch_t *) d->chan;
1888 pc300_t *card = (pc300_t *) chan->card; 1885 pc300_t *card = (pc300_t *) chan->card;
1889 struct net_device_stats *stats = hdlc_stats(dev);
1890 int ch = chan->channel; 1886 int ch = chan->channel;
1891#ifdef PC300_DEBUG_RX 1887#ifdef PC300_DEBUG_RX
1892 int i; 1888 int i;
@@ -1922,24 +1918,24 @@ static void cpc_net_rx(struct net_device *dev)
1922#endif 1918#endif
1923 if ((skb == NULL) && (rxb > 0)) { 1919 if ((skb == NULL) && (rxb > 0)) {
1924 /* rxb > dev->mtu */ 1920 /* rxb > dev->mtu */
1925 stats->rx_errors++; 1921 dev->stats.rx_errors++;
1926 stats->rx_length_errors++; 1922 dev->stats.rx_length_errors++;
1927 continue; 1923 continue;
1928 } 1924 }
1929 1925
1930 if (rxb < 0) { /* Invalid frame */ 1926 if (rxb < 0) { /* Invalid frame */
1931 rxb = -rxb; 1927 rxb = -rxb;
1932 if (rxb & DST_OVR) { 1928 if (rxb & DST_OVR) {
1933 stats->rx_errors++; 1929 dev->stats.rx_errors++;
1934 stats->rx_fifo_errors++; 1930 dev->stats.rx_fifo_errors++;
1935 } 1931 }
1936 if (rxb & DST_CRC) { 1932 if (rxb & DST_CRC) {
1937 stats->rx_errors++; 1933 dev->stats.rx_errors++;
1938 stats->rx_crc_errors++; 1934 dev->stats.rx_crc_errors++;
1939 } 1935 }
1940 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) { 1936 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1941 stats->rx_errors++; 1937 dev->stats.rx_errors++;
1942 stats->rx_frame_errors++; 1938 dev->stats.rx_frame_errors++;
1943 } 1939 }
1944 } 1940 }
1945 if (skb) { 1941 if (skb) {
@@ -1948,7 +1944,7 @@ static void cpc_net_rx(struct net_device *dev)
1948 continue; 1944 continue;
1949 } 1945 }
1950 1946
1951 stats->rx_bytes += rxb; 1947 dev->stats.rx_bytes += rxb;
1952 1948
1953#ifdef PC300_DEBUG_RX 1949#ifdef PC300_DEBUG_RX
1954 printk("%s R:", dev->name); 1950 printk("%s R:", dev->name);
@@ -1959,7 +1955,7 @@ static void cpc_net_rx(struct net_device *dev)
1959 if (d->trace_on) { 1955 if (d->trace_on) {
1960 cpc_trace(dev, skb, 'R'); 1956 cpc_trace(dev, skb, 'R');
1961 } 1957 }
1962 stats->rx_packets++; 1958 dev->stats.rx_packets++;
1963 skb->protocol = hdlc_type_trans(skb, dev); 1959 skb->protocol = hdlc_type_trans(skb, dev);
1964 netif_rx(skb); 1960 netif_rx(skb);
1965 } 1961 }
@@ -1974,16 +1970,15 @@ static void sca_tx_intr(pc300dev_t *dev)
1974 pc300_t *card = (pc300_t *)chan->card; 1970 pc300_t *card = (pc300_t *)chan->card;
1975 int ch = chan->channel; 1971 int ch = chan->channel;
1976 volatile pcsca_bd_t __iomem * ptdescr; 1972 volatile pcsca_bd_t __iomem * ptdescr;
1977 struct net_device_stats *stats = hdlc_stats(dev->dev);
1978 1973
1979 /* Clean up descriptors from previous transmission */ 1974 /* Clean up descriptors from previous transmission */
1980 ptdescr = (card->hw.rambase + 1975 ptdescr = (card->hw.rambase +
1981 TX_BD_ADDR(ch,chan->tx_first_bd)); 1976 TX_BD_ADDR(ch,chan->tx_first_bd));
1982 while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) != 1977 while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1983 TX_BD_ADDR(ch,chan->tx_first_bd)) && 1978 TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1984 (cpc_readb(&ptdescr->status) & DST_OSB)) { 1979 (cpc_readb(&ptdescr->status) & DST_OSB)) {
1985 stats->tx_packets++; 1980 dev->dev->stats.tx_packets++;
1986 stats->tx_bytes += cpc_readw(&ptdescr->len); 1981 dev->dev->stats.tx_bytes += cpc_readw(&ptdescr->len);
1987 cpc_writeb(&ptdescr->status, DST_OSB); 1982 cpc_writeb(&ptdescr->status, DST_OSB);
1988 cpc_writew(&ptdescr->len, 0); 1983 cpc_writew(&ptdescr->len, 0);
1989 chan->nfree_tx_bd++; 1984 chan->nfree_tx_bd++;
@@ -2048,8 +2043,8 @@ static void sca_intr(pc300_t * card)
2048 } 2043 }
2049 cpc_net_rx(dev); 2044 cpc_net_rx(dev);
2050 /* Discard invalid frames */ 2045 /* Discard invalid frames */
2051 hdlc_stats(dev)->rx_errors++; 2046 dev->stats.rx_errors++;
2052 hdlc_stats(dev)->rx_over_errors++; 2047 dev->stats.rx_over_errors++;
2053 chan->rx_first_bd = 0; 2048 chan->rx_first_bd = 0;
2054 chan->rx_last_bd = N_DMA_RX_BUF - 1; 2049 chan->rx_last_bd = N_DMA_RX_BUF - 1;
2055 rx_dma_start(card, ch); 2050 rx_dma_start(card, ch);
@@ -2115,8 +2110,8 @@ static void sca_intr(pc300_t * card)
2115 card->hw.cpld_reg2) & 2110 card->hw.cpld_reg2) &
2116 ~ (CPLD_REG2_FALC_LED1 << (2 * ch))); 2111 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2117 } 2112 }
2118 hdlc_stats(dev)->tx_errors++; 2113 dev->stats.tx_errors++;
2119 hdlc_stats(dev)->tx_fifo_errors++; 2114 dev->stats.tx_fifo_errors++;
2120 sca_tx_intr(d); 2115 sca_tx_intr(d);
2121 } 2116 }
2122 } 2117 }
@@ -2604,7 +2599,7 @@ static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2604 case SIOCGPC300UTILSTATS: 2599 case SIOCGPC300UTILSTATS:
2605 { 2600 {
2606 if (!arg) { /* clear statistics */ 2601 if (!arg) { /* clear statistics */
2607 memset(hdlc_stats(dev), 0, sizeof(struct net_device_stats)); 2602 memset(&dev->stats, 0, sizeof(dev->stats));
2608 if (card->hw.type == PC300_TE) { 2603 if (card->hw.type == PC300_TE) {
2609 memset(&chan->falc, 0, sizeof(falc_t)); 2604 memset(&chan->falc, 0, sizeof(falc_t));
2610 } 2605 }
@@ -2615,8 +2610,8 @@ static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2615 pc300stats.hw_type = card->hw.type; 2610 pc300stats.hw_type = card->hw.type;
2616 pc300stats.line_on = card->chan[ch].d.line_on; 2611 pc300stats.line_on = card->chan[ch].d.line_on;
2617 pc300stats.line_off = card->chan[ch].d.line_off; 2612 pc300stats.line_off = card->chan[ch].d.line_off;
2618 memcpy(&pc300stats.gen_stats, hdlc_stats(dev), 2613 memcpy(&pc300stats.gen_stats, &dev->stats,
2619 sizeof(struct net_device_stats)); 2614 sizeof(dev->stats));
2620 if (card->hw.type == PC300_TE) 2615 if (card->hw.type == PC300_TE)
2621 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t)); 2616 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2622 if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t))) 2617 if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
@@ -2823,11 +2818,6 @@ static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2823 } 2818 }
2824} 2819}
2825 2820
2826static struct net_device_stats *cpc_get_stats(struct net_device *dev)
2827{
2828 return hdlc_stats(dev);
2829}
2830
2831static int clock_rate_calc(uclong rate, uclong clock, int *br_io) 2821static int clock_rate_calc(uclong rate, uclong clock, int *br_io)
2832{ 2822{
2833 int br, tc; 2823 int br, tc;
@@ -3394,7 +3384,6 @@ static void cpc_init_card(pc300_t * card)
3394 dev->stop = cpc_close; 3384 dev->stop = cpc_close;
3395 dev->tx_timeout = cpc_tx_timeout; 3385 dev->tx_timeout = cpc_tx_timeout;
3396 dev->watchdog_timeo = PC300_TX_TIMEOUT; 3386 dev->watchdog_timeo = PC300_TX_TIMEOUT;
3397 dev->get_stats = cpc_get_stats;
3398 dev->set_multicast_list = NULL; 3387 dev->set_multicast_list = NULL;
3399 dev->set_mac_address = NULL; 3388 dev->set_mac_address = NULL;
3400 dev->change_mtu = cpc_change_mtu; 3389 dev->change_mtu = cpc_change_mtu;
diff --git a/drivers/net/wan/pc300_tty.c b/drivers/net/wan/pc300_tty.c
index c2c10c632260..4518d0aa2480 100644
--- a/drivers/net/wan/pc300_tty.c
+++ b/drivers/net/wan/pc300_tty.c
@@ -458,7 +458,7 @@ static int cpc_tty_write(struct tty_struct *tty, const unsigned char *buf, int c
458 CPC_TTY_DBG("%s: cpc_tty_write data len=%i\n",cpc_tty->name,count); 458 CPC_TTY_DBG("%s: cpc_tty_write data len=%i\n",cpc_tty->name,count);
459 459
460 pc300chan = (pc300ch_t *)((pc300dev_t*)cpc_tty->pc300dev)->chan; 460 pc300chan = (pc300ch_t *)((pc300dev_t*)cpc_tty->pc300dev)->chan;
461 stats = hdlc_stats(((pc300dev_t*)cpc_tty->pc300dev)->dev); 461 stats = &cpc_tty->pc300dev->dev->stats;
462 card = (pc300_t *) pc300chan->card; 462 card = (pc300_t *) pc300chan->card;
463 ch = pc300chan->channel; 463 ch = pc300chan->channel;
464 464
@@ -743,7 +743,7 @@ void cpc_tty_receive(pc300dev_t *pc300dev)
743 pc300_t *card = (pc300_t *)pc300chan->card; 743 pc300_t *card = (pc300_t *)pc300chan->card;
744 int ch = pc300chan->channel; 744 int ch = pc300chan->channel;
745 volatile pcsca_bd_t __iomem * ptdescr; 745 volatile pcsca_bd_t __iomem * ptdescr;
746 struct net_device_stats *stats = hdlc_stats(pc300dev->dev); 746 struct net_device_stats *stats = &pc300dev->dev->stats;
747 int rx_len, rx_aux; 747 int rx_len, rx_aux;
748 volatile unsigned char status; 748 volatile unsigned char status;
749 unsigned short first_bd = pc300chan->rx_first_bd; 749 unsigned short first_bd = pc300chan->rx_first_bd;
@@ -917,7 +917,7 @@ static int cpc_tty_send_to_card(pc300dev_t *dev,void* buf, int len)
917 pc300ch_t *chan = (pc300ch_t *)dev->chan; 917 pc300ch_t *chan = (pc300ch_t *)dev->chan;
918 pc300_t *card = (pc300_t *)chan->card; 918 pc300_t *card = (pc300_t *)chan->card;
919 int ch = chan->channel; 919 int ch = chan->channel;
920 struct net_device_stats *stats = hdlc_stats(dev->dev); 920 struct net_device_stats *stats = &dev->dev->stats;
921 unsigned long flags; 921 unsigned long flags;
922 volatile pcsca_bd_t __iomem *ptdescr; 922 volatile pcsca_bd_t __iomem *ptdescr;
923 int i, nchar; 923 int i, nchar;
diff --git a/drivers/net/wan/wanxl.c b/drivers/net/wan/wanxl.c
index d4aab8a28b61..a8a5ca0ee6c2 100644
--- a/drivers/net/wan/wanxl.c
+++ b/drivers/net/wan/wanxl.c
@@ -161,7 +161,6 @@ static inline void wanxl_cable_intr(port_t *port)
161static inline void wanxl_tx_intr(port_t *port) 161static inline void wanxl_tx_intr(port_t *port)
162{ 162{
163 struct net_device *dev = port->dev; 163 struct net_device *dev = port->dev;
164 struct net_device_stats *stats = hdlc_stats(dev);
165 while (1) { 164 while (1) {
166 desc_t *desc = &get_status(port)->tx_descs[port->tx_in]; 165 desc_t *desc = &get_status(port)->tx_descs[port->tx_in];
167 struct sk_buff *skb = port->tx_skbs[port->tx_in]; 166 struct sk_buff *skb = port->tx_skbs[port->tx_in];
@@ -173,13 +172,13 @@ static inline void wanxl_tx_intr(port_t *port)
173 return; 172 return;
174 173
175 case PACKET_UNDERRUN: 174 case PACKET_UNDERRUN:
176 stats->tx_errors++; 175 dev->stats.tx_errors++;
177 stats->tx_fifo_errors++; 176 dev->stats.tx_fifo_errors++;
178 break; 177 break;
179 178
180 default: 179 default:
181 stats->tx_packets++; 180 dev->stats.tx_packets++;
182 stats->tx_bytes += skb->len; 181 dev->stats.tx_bytes += skb->len;
183 } 182 }
184 desc->stat = PACKET_EMPTY; /* Free descriptor */ 183 desc->stat = PACKET_EMPTY; /* Free descriptor */
185 pci_unmap_single(port->card->pdev, desc->address, skb->len, 184 pci_unmap_single(port->card->pdev, desc->address, skb->len,
@@ -205,10 +204,9 @@ static inline void wanxl_rx_intr(card_t *card)
205 port_t *port = &card->ports[desc->stat & 204 port_t *port = &card->ports[desc->stat &
206 PACKET_PORT_MASK]; 205 PACKET_PORT_MASK];
207 struct net_device *dev = port->dev; 206 struct net_device *dev = port->dev;
208 struct net_device_stats *stats = hdlc_stats(dev);
209 207
210 if (!skb) 208 if (!skb)
211 stats->rx_dropped++; 209 dev->stats.rx_dropped++;
212 else { 210 else {
213 pci_unmap_single(card->pdev, desc->address, 211 pci_unmap_single(card->pdev, desc->address,
214 BUFFER_LENGTH, 212 BUFFER_LENGTH,
@@ -220,8 +218,8 @@ static inline void wanxl_rx_intr(card_t *card)
220 skb->len); 218 skb->len);
221 debug_frame(skb); 219 debug_frame(skb);
222#endif 220#endif
223 stats->rx_packets++; 221 dev->stats.rx_packets++;
224 stats->rx_bytes += skb->len; 222 dev->stats.rx_bytes += skb->len;
225 dev->last_rx = jiffies; 223 dev->last_rx = jiffies;
226 skb->protocol = hdlc_type_trans(skb, dev); 224 skb->protocol = hdlc_type_trans(skb, dev);
227 netif_rx(skb); 225 netif_rx(skb);
@@ -468,13 +466,13 @@ static int wanxl_close(struct net_device *dev)
468 466
469static struct net_device_stats *wanxl_get_stats(struct net_device *dev) 467static struct net_device_stats *wanxl_get_stats(struct net_device *dev)
470{ 468{
471 struct net_device_stats *stats = hdlc_stats(dev);
472 port_t *port = dev_to_port(dev); 469 port_t *port = dev_to_port(dev);
473 470
474 stats->rx_over_errors = get_status(port)->rx_overruns; 471 dev->stats.rx_over_errors = get_status(port)->rx_overruns;
475 stats->rx_frame_errors = get_status(port)->rx_frame_errors; 472 dev->stats.rx_frame_errors = get_status(port)->rx_frame_errors;
476 stats->rx_errors = stats->rx_over_errors + stats->rx_frame_errors; 473 dev->stats.rx_errors = dev->stats.rx_over_errors +
477 return stats; 474 dev->stats.rx_frame_errors;
475 return &dev->stats;
478} 476}
479 477
480 478
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index fdf5aa8b8429..91fc2c765d90 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -635,14 +635,20 @@ config RTL8180
635 Thanks to Realtek for their support! 635 Thanks to Realtek for their support!
636 636
637config RTL8187 637config RTL8187
638 tristate "Realtek 8187 USB support" 638 tristate "Realtek 8187 and 8187B USB support"
639 depends on MAC80211 && USB && WLAN_80211 && EXPERIMENTAL 639 depends on MAC80211 && USB && WLAN_80211 && EXPERIMENTAL
640 select EEPROM_93CX6 640 select EEPROM_93CX6
641 ---help--- 641 ---help---
642 This is a driver for RTL8187 based cards. 642 This is a driver for RTL8187 and RTL8187B based cards.
643 These are USB based chips found in cards such as: 643 These are USB based chips found in devices such as:
644 644
645 Netgear WG111v2 645 Netgear WG111v2
646 Level 1 WNC-0301USB
647 Micronet SP907GK V5
648 Encore ENUWI-G2
649 Trendnet TEW-424UB
650 ASUS P5B Deluxe
651 Toshiba Satellite Pro series of laptops
646 652
647 Thanks to Realtek for their support! 653 Thanks to Realtek for their support!
648 654
@@ -673,6 +679,19 @@ config ADM8211
673 679
674 Thanks to Infineon-ADMtek for their support of this driver. 680 Thanks to Infineon-ADMtek for their support of this driver.
675 681
682config MAC80211_HWSIM
683 tristate "Simulated radio testing tool for mac80211"
684 depends on MAC80211 && WLAN_80211
685 ---help---
686 This driver is a developer testing tool that can be used to test
687 IEEE 802.11 networking stack (mac80211) functionality. This is not
688 needed for normal wireless LAN usage and is only for testing. See
689 Documentation/networking/mac80211_hwsim for more information on how
690 to use this tool.
691
692 To compile this driver as a module, choose M here: the module will be
693 called mac80211_hwsim. If unsure, say N.
694
676source "drivers/net/wireless/p54/Kconfig" 695source "drivers/net/wireless/p54/Kconfig"
677source "drivers/net/wireless/ath5k/Kconfig" 696source "drivers/net/wireless/ath5k/Kconfig"
678source "drivers/net/wireless/iwlwifi/Kconfig" 697source "drivers/net/wireless/iwlwifi/Kconfig"
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
index 2c343aae38d4..54a4f6f1db67 100644
--- a/drivers/net/wireless/Makefile
+++ b/drivers/net/wireless/Makefile
@@ -62,3 +62,5 @@ obj-$(CONFIG_RT2X00) += rt2x00/
62obj-$(CONFIG_P54_COMMON) += p54/ 62obj-$(CONFIG_P54_COMMON) += p54/
63 63
64obj-$(CONFIG_ATH5K) += ath5k/ 64obj-$(CONFIG_ATH5K) += ath5k/
65
66obj-$(CONFIG_MAC80211_HWSIM) += mac80211_hwsim.o
diff --git a/drivers/net/wireless/adm8211.c b/drivers/net/wireless/adm8211.c
index 5c0d2b082750..3333d4596b8d 100644
--- a/drivers/net/wireless/adm8211.c
+++ b/drivers/net/wireless/adm8211.c
@@ -306,11 +306,10 @@ static int adm8211_get_tx_stats(struct ieee80211_hw *dev,
306 struct ieee80211_tx_queue_stats *stats) 306 struct ieee80211_tx_queue_stats *stats)
307{ 307{
308 struct adm8211_priv *priv = dev->priv; 308 struct adm8211_priv *priv = dev->priv;
309 struct ieee80211_tx_queue_stats_data *data = &stats->data[0];
310 309
311 data->len = priv->cur_tx - priv->dirty_tx; 310 stats[0].len = priv->cur_tx - priv->dirty_tx;
312 data->limit = priv->tx_ring_size - 2; 311 stats[0].limit = priv->tx_ring_size - 2;
313 data->count = priv->dirty_tx; 312 stats[0].count = priv->dirty_tx;
314 313
315 return 0; 314 return 0;
316} 315}
@@ -325,7 +324,7 @@ static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
325 for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) { 324 for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
326 unsigned int entry = dirty_tx % priv->tx_ring_size; 325 unsigned int entry = dirty_tx % priv->tx_ring_size;
327 u32 status = le32_to_cpu(priv->tx_ring[entry].status); 326 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
328 struct ieee80211_tx_status tx_status; 327 struct ieee80211_tx_info *txi;
329 struct adm8211_tx_ring_info *info; 328 struct adm8211_tx_ring_info *info;
330 struct sk_buff *skb; 329 struct sk_buff *skb;
331 330
@@ -335,24 +334,23 @@ static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
335 334
336 info = &priv->tx_buffers[entry]; 335 info = &priv->tx_buffers[entry];
337 skb = info->skb; 336 skb = info->skb;
337 txi = IEEE80211_SKB_CB(skb);
338 338
339 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */ 339 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
340 340
341 pci_unmap_single(priv->pdev, info->mapping, 341 pci_unmap_single(priv->pdev, info->mapping,
342 info->skb->len, PCI_DMA_TODEVICE); 342 info->skb->len, PCI_DMA_TODEVICE);
343 343
344 memset(&tx_status, 0, sizeof(tx_status)); 344 memset(&txi->status, 0, sizeof(txi->status));
345 skb_pull(skb, sizeof(struct adm8211_tx_hdr)); 345 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
346 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen); 346 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
347 memcpy(&tx_status.control, &info->tx_control, 347 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK)) {
348 sizeof(tx_status.control));
349 if (!(tx_status.control.flags & IEEE80211_TXCTL_NO_ACK)) {
350 if (status & TDES0_STATUS_ES) 348 if (status & TDES0_STATUS_ES)
351 tx_status.excessive_retries = 1; 349 txi->status.excessive_retries = 1;
352 else 350 else
353 tx_status.flags |= IEEE80211_TX_STATUS_ACK; 351 txi->flags |= IEEE80211_TX_STAT_ACK;
354 } 352 }
355 ieee80211_tx_status_irqsafe(dev, skb, &tx_status); 353 ieee80211_tx_status_irqsafe(dev, skb);
356 354
357 info->skb = NULL; 355 info->skb = NULL;
358 } 356 }
@@ -446,9 +444,9 @@ static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
446 struct ieee80211_rx_status rx_status = {0}; 444 struct ieee80211_rx_status rx_status = {0};
447 445
448 if (priv->pdev->revision < ADM8211_REV_CA) 446 if (priv->pdev->revision < ADM8211_REV_CA)
449 rx_status.ssi = rssi; 447 rx_status.signal = rssi;
450 else 448 else
451 rx_status.ssi = 100 - rssi; 449 rx_status.signal = 100 - rssi;
452 450
453 rx_status.rate_idx = rate; 451 rx_status.rate_idx = rate;
454 452
@@ -1639,7 +1637,6 @@ static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int
1639/* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */ 1637/* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1640static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb, 1638static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1641 u16 plcp_signal, 1639 u16 plcp_signal,
1642 struct ieee80211_tx_control *control,
1643 size_t hdrlen) 1640 size_t hdrlen)
1644{ 1641{
1645 struct adm8211_priv *priv = dev->priv; 1642 struct adm8211_priv *priv = dev->priv;
@@ -1665,7 +1662,6 @@ static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1665 1662
1666 priv->tx_buffers[entry].skb = skb; 1663 priv->tx_buffers[entry].skb = skb;
1667 priv->tx_buffers[entry].mapping = mapping; 1664 priv->tx_buffers[entry].mapping = mapping;
1668 memcpy(&priv->tx_buffers[entry].tx_control, control, sizeof(*control));
1669 priv->tx_buffers[entry].hdrlen = hdrlen; 1665 priv->tx_buffers[entry].hdrlen = hdrlen;
1670 priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping); 1666 priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1671 1667
@@ -1686,22 +1682,20 @@ static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1686} 1682}
1687 1683
1688/* Put adm8211_tx_hdr on skb and transmit */ 1684/* Put adm8211_tx_hdr on skb and transmit */
1689static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb, 1685static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
1690 struct ieee80211_tx_control *control)
1691{ 1686{
1692 struct adm8211_tx_hdr *txhdr; 1687 struct adm8211_tx_hdr *txhdr;
1693 u16 fc;
1694 size_t payload_len, hdrlen; 1688 size_t payload_len, hdrlen;
1695 int plcp, dur, len, plcp_signal, short_preamble; 1689 int plcp, dur, len, plcp_signal, short_preamble;
1696 struct ieee80211_hdr *hdr; 1690 struct ieee80211_hdr *hdr;
1691 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1692 struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
1697 1693
1698 short_preamble = !!(control->tx_rate->flags & 1694 short_preamble = !!(txrate->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE);
1699 IEEE80211_TXCTL_SHORT_PREAMBLE); 1695 plcp_signal = txrate->bitrate;
1700 plcp_signal = control->tx_rate->bitrate;
1701 1696
1702 hdr = (struct ieee80211_hdr *)skb->data; 1697 hdr = (struct ieee80211_hdr *)skb->data;
1703 fc = le16_to_cpu(hdr->frame_control) & ~IEEE80211_FCTL_PROTECTED; 1698 hdrlen = ieee80211_hdrlen(hdr->frame_control);
1704 hdrlen = ieee80211_get_hdrlen(fc);
1705 memcpy(skb->cb, skb->data, hdrlen); 1699 memcpy(skb->cb, skb->data, hdrlen);
1706 hdr = (struct ieee80211_hdr *)skb->cb; 1700 hdr = (struct ieee80211_hdr *)skb->cb;
1707 skb_pull(skb, hdrlen); 1701 skb_pull(skb, hdrlen);
@@ -1715,8 +1709,6 @@ static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
1715 txhdr->frame_control = hdr->frame_control; 1709 txhdr->frame_control = hdr->frame_control;
1716 1710
1717 len = hdrlen + payload_len + FCS_LEN; 1711 len = hdrlen + payload_len + FCS_LEN;
1718 if (fc & IEEE80211_FCTL_PROTECTED)
1719 len += 8;
1720 1712
1721 txhdr->frag = cpu_to_le16(0x0FFF); 1713 txhdr->frag = cpu_to_le16(0x0FFF);
1722 adm8211_calc_durations(&dur, &plcp, payload_len, 1714 adm8211_calc_durations(&dur, &plcp, payload_len,
@@ -1731,15 +1723,12 @@ static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
1731 if (short_preamble) 1723 if (short_preamble)
1732 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE); 1724 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1733 1725
1734 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS) 1726 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
1735 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS); 1727 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1736 1728
1737 if (fc & IEEE80211_FCTL_PROTECTED) 1729 txhdr->retry_limit = info->control.retry_limit;
1738 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE);
1739 1730
1740 txhdr->retry_limit = control->retry_limit; 1731 adm8211_tx_raw(dev, skb, plcp_signal, hdrlen);
1741
1742 adm8211_tx_raw(dev, skb, plcp_signal, control, hdrlen);
1743 1732
1744 return NETDEV_TX_OK; 1733 return NETDEV_TX_OK;
1745} 1734}
@@ -1894,9 +1883,10 @@ static int __devinit adm8211_probe(struct pci_dev *pdev,
1894 1883
1895 dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr); 1884 dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1896 /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */ 1885 /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1886 dev->flags = IEEE80211_HW_SIGNAL_UNSPEC;
1897 1887
1898 dev->channel_change_time = 1000; 1888 dev->channel_change_time = 1000;
1899 dev->max_rssi = 100; /* FIXME: find better value */ 1889 dev->max_signal = 100; /* FIXME: find better value */
1900 1890
1901 dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */ 1891 dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1902 1892
@@ -2015,7 +2005,7 @@ static int adm8211_resume(struct pci_dev *pdev)
2015 2005
2016 if (priv->mode != IEEE80211_IF_TYPE_INVALID) { 2006 if (priv->mode != IEEE80211_IF_TYPE_INVALID) {
2017 adm8211_start(dev); 2007 adm8211_start(dev);
2018 ieee80211_start_queues(dev); 2008 ieee80211_wake_queues(dev);
2019 } 2009 }
2020 2010
2021 return 0; 2011 return 0;
diff --git a/drivers/net/wireless/adm8211.h b/drivers/net/wireless/adm8211.h
index 8d7c564b3b04..9b190ee26e90 100644
--- a/drivers/net/wireless/adm8211.h
+++ b/drivers/net/wireless/adm8211.h
@@ -443,7 +443,6 @@ struct adm8211_rx_ring_info {
443struct adm8211_tx_ring_info { 443struct adm8211_tx_ring_info {
444 struct sk_buff *skb; 444 struct sk_buff *skb;
445 dma_addr_t mapping; 445 dma_addr_t mapping;
446 struct ieee80211_tx_control tx_control;
447 size_t hdrlen; 446 size_t hdrlen;
448}; 447};
449 448
diff --git a/drivers/net/wireless/airo.c b/drivers/net/wireless/airo.c
index 32019fb878d8..b5cd850a4a59 100644
--- a/drivers/net/wireless/airo.c
+++ b/drivers/net/wireless/airo.c
@@ -85,10 +85,10 @@ static struct pci_driver airo_driver = {
85 85
86/* Include Wireless Extension definition and check version - Jean II */ 86/* Include Wireless Extension definition and check version - Jean II */
87#include <linux/wireless.h> 87#include <linux/wireless.h>
88#define WIRELESS_SPY // enable iwspy support 88#define WIRELESS_SPY /* enable iwspy support */
89#include <net/iw_handler.h> // New driver API 89#include <net/iw_handler.h> /* New driver API */
90 90
91#define CISCO_EXT // enable Cisco extensions 91#define CISCO_EXT /* enable Cisco extensions */
92#ifdef CISCO_EXT 92#ifdef CISCO_EXT
93#include <linux/delay.h> 93#include <linux/delay.h>
94#endif 94#endif
@@ -281,7 +281,7 @@ MODULE_PARM_DESC(proc_perm, "The permission bits of the files in /proc");
281/* This is a kind of sloppy hack to get this information to OUT4500 and 281/* This is a kind of sloppy hack to get this information to OUT4500 and
282 IN4500. I would be extremely interested in the situation where this 282 IN4500. I would be extremely interested in the situation where this
283 doesn't work though!!! */ 283 doesn't work though!!! */
284static int do8bitIO = 0; 284static int do8bitIO /* = 0 */;
285 285
286/* Return codes */ 286/* Return codes */
287#define SUCCESS 0 287#define SUCCESS 0
@@ -398,8 +398,8 @@ static int do8bitIO = 0;
398#define MAXTXQ 64 398#define MAXTXQ 64
399 399
400/* BAP selectors */ 400/* BAP selectors */
401#define BAP0 0 // Used for receiving packets 401#define BAP0 0 /* Used for receiving packets */
402#define BAP1 2 // Used for xmiting packets and working with RIDS 402#define BAP1 2 /* Used for xmiting packets and working with RIDS */
403 403
404/* Flags */ 404/* Flags */
405#define COMMAND_BUSY 0x8000 405#define COMMAND_BUSY 0x8000
@@ -1148,7 +1148,6 @@ static u8 airo_dbm_to_pct (tdsRssiEntry *rssi_rid, u8 dbm);
1148static void airo_networks_free(struct airo_info *ai); 1148static void airo_networks_free(struct airo_info *ai);
1149 1149
1150struct airo_info { 1150struct airo_info {
1151 struct net_device_stats stats;
1152 struct net_device *dev; 1151 struct net_device *dev;
1153 struct list_head dev_list; 1152 struct list_head dev_list;
1154 /* Note, we can have MAX_FIDS outstanding. FIDs are 16-bits, so we 1153 /* Note, we can have MAX_FIDS outstanding. FIDs are 16-bits, so we
@@ -1924,7 +1923,7 @@ static int mpi_start_xmit(struct sk_buff *skb, struct net_device *dev) {
1924 if (npacks >= MAXTXQ - 1) { 1923 if (npacks >= MAXTXQ - 1) {
1925 netif_stop_queue (dev); 1924 netif_stop_queue (dev);
1926 if (npacks > MAXTXQ) { 1925 if (npacks > MAXTXQ) {
1927 ai->stats.tx_fifo_errors++; 1926 dev->stats.tx_fifo_errors++;
1928 return 1; 1927 return 1;
1929 } 1928 }
1930 skb_queue_tail (&ai->txq, skb); 1929 skb_queue_tail (&ai->txq, skb);
@@ -2044,13 +2043,13 @@ static void get_tx_error(struct airo_info *ai, s32 fid)
2044 bap_read(ai, &status, 2, BAP0); 2043 bap_read(ai, &status, 2, BAP0);
2045 } 2044 }
2046 if (le16_to_cpu(status) & 2) /* Too many retries */ 2045 if (le16_to_cpu(status) & 2) /* Too many retries */
2047 ai->stats.tx_aborted_errors++; 2046 ai->dev->stats.tx_aborted_errors++;
2048 if (le16_to_cpu(status) & 4) /* Transmit lifetime exceeded */ 2047 if (le16_to_cpu(status) & 4) /* Transmit lifetime exceeded */
2049 ai->stats.tx_heartbeat_errors++; 2048 ai->dev->stats.tx_heartbeat_errors++;
2050 if (le16_to_cpu(status) & 8) /* Aid fail */ 2049 if (le16_to_cpu(status) & 8) /* Aid fail */
2051 { } 2050 { }
2052 if (le16_to_cpu(status) & 0x10) /* MAC disabled */ 2051 if (le16_to_cpu(status) & 0x10) /* MAC disabled */
2053 ai->stats.tx_carrier_errors++; 2052 ai->dev->stats.tx_carrier_errors++;
2054 if (le16_to_cpu(status) & 0x20) /* Association lost */ 2053 if (le16_to_cpu(status) & 0x20) /* Association lost */
2055 { } 2054 { }
2056 /* We produce a TXDROP event only for retry or lifetime 2055 /* We produce a TXDROP event only for retry or lifetime
@@ -2102,7 +2101,7 @@ static void airo_end_xmit(struct net_device *dev) {
2102 for (; i < MAX_FIDS / 2 && (priv->fids[i] & 0xffff0000); i++); 2101 for (; i < MAX_FIDS / 2 && (priv->fids[i] & 0xffff0000); i++);
2103 } else { 2102 } else {
2104 priv->fids[fid] &= 0xffff; 2103 priv->fids[fid] &= 0xffff;
2105 priv->stats.tx_window_errors++; 2104 dev->stats.tx_window_errors++;
2106 } 2105 }
2107 if (i < MAX_FIDS / 2) 2106 if (i < MAX_FIDS / 2)
2108 netif_wake_queue(dev); 2107 netif_wake_queue(dev);
@@ -2128,7 +2127,7 @@ static int airo_start_xmit(struct sk_buff *skb, struct net_device *dev) {
2128 netif_stop_queue(dev); 2127 netif_stop_queue(dev);
2129 2128
2130 if (i == MAX_FIDS / 2) { 2129 if (i == MAX_FIDS / 2) {
2131 priv->stats.tx_fifo_errors++; 2130 dev->stats.tx_fifo_errors++;
2132 return 1; 2131 return 1;
2133 } 2132 }
2134 } 2133 }
@@ -2167,7 +2166,7 @@ static void airo_end_xmit11(struct net_device *dev) {
2167 for (; i < MAX_FIDS && (priv->fids[i] & 0xffff0000); i++); 2166 for (; i < MAX_FIDS && (priv->fids[i] & 0xffff0000); i++);
2168 } else { 2167 } else {
2169 priv->fids[fid] &= 0xffff; 2168 priv->fids[fid] &= 0xffff;
2170 priv->stats.tx_window_errors++; 2169 dev->stats.tx_window_errors++;
2171 } 2170 }
2172 if (i < MAX_FIDS) 2171 if (i < MAX_FIDS)
2173 netif_wake_queue(dev); 2172 netif_wake_queue(dev);
@@ -2199,7 +2198,7 @@ static int airo_start_xmit11(struct sk_buff *skb, struct net_device *dev) {
2199 netif_stop_queue(dev); 2198 netif_stop_queue(dev);
2200 2199
2201 if (i == MAX_FIDS) { 2200 if (i == MAX_FIDS) {
2202 priv->stats.tx_fifo_errors++; 2201 dev->stats.tx_fifo_errors++;
2203 return 1; 2202 return 1;
2204 } 2203 }
2205 } 2204 }
@@ -2219,8 +2218,9 @@ static int airo_start_xmit11(struct sk_buff *skb, struct net_device *dev) {
2219 return 0; 2218 return 0;
2220} 2219}
2221 2220
2222static void airo_read_stats(struct airo_info *ai) 2221static void airo_read_stats(struct net_device *dev)
2223{ 2222{
2223 struct airo_info *ai = dev->priv;
2224 StatsRid stats_rid; 2224 StatsRid stats_rid;
2225 __le32 *vals = stats_rid.vals; 2225 __le32 *vals = stats_rid.vals;
2226 2226
@@ -2232,23 +2232,24 @@ static void airo_read_stats(struct airo_info *ai)
2232 readStatsRid(ai, &stats_rid, RID_STATS, 0); 2232 readStatsRid(ai, &stats_rid, RID_STATS, 0);
2233 up(&ai->sem); 2233 up(&ai->sem);
2234 2234
2235 ai->stats.rx_packets = le32_to_cpu(vals[43]) + le32_to_cpu(vals[44]) + 2235 dev->stats.rx_packets = le32_to_cpu(vals[43]) + le32_to_cpu(vals[44]) +
2236 le32_to_cpu(vals[45]); 2236 le32_to_cpu(vals[45]);
2237 ai->stats.tx_packets = le32_to_cpu(vals[39]) + le32_to_cpu(vals[40]) + 2237 dev->stats.tx_packets = le32_to_cpu(vals[39]) + le32_to_cpu(vals[40]) +
2238 le32_to_cpu(vals[41]); 2238 le32_to_cpu(vals[41]);
2239 ai->stats.rx_bytes = le32_to_cpu(vals[92]); 2239 dev->stats.rx_bytes = le32_to_cpu(vals[92]);
2240 ai->stats.tx_bytes = le32_to_cpu(vals[91]); 2240 dev->stats.tx_bytes = le32_to_cpu(vals[91]);
2241 ai->stats.rx_errors = le32_to_cpu(vals[0]) + le32_to_cpu(vals[2]) + 2241 dev->stats.rx_errors = le32_to_cpu(vals[0]) + le32_to_cpu(vals[2]) +
2242 le32_to_cpu(vals[3]) + le32_to_cpu(vals[4]); 2242 le32_to_cpu(vals[3]) + le32_to_cpu(vals[4]);
2243 ai->stats.tx_errors = le32_to_cpu(vals[42]) + ai->stats.tx_fifo_errors; 2243 dev->stats.tx_errors = le32_to_cpu(vals[42]) +
2244 ai->stats.multicast = le32_to_cpu(vals[43]); 2244 dev->stats.tx_fifo_errors;
2245 ai->stats.collisions = le32_to_cpu(vals[89]); 2245 dev->stats.multicast = le32_to_cpu(vals[43]);
2246 dev->stats.collisions = le32_to_cpu(vals[89]);
2246 2247
2247 /* detailed rx_errors: */ 2248 /* detailed rx_errors: */
2248 ai->stats.rx_length_errors = le32_to_cpu(vals[3]); 2249 dev->stats.rx_length_errors = le32_to_cpu(vals[3]);
2249 ai->stats.rx_crc_errors = le32_to_cpu(vals[4]); 2250 dev->stats.rx_crc_errors = le32_to_cpu(vals[4]);
2250 ai->stats.rx_frame_errors = le32_to_cpu(vals[2]); 2251 dev->stats.rx_frame_errors = le32_to_cpu(vals[2]);
2251 ai->stats.rx_fifo_errors = le32_to_cpu(vals[0]); 2252 dev->stats.rx_fifo_errors = le32_to_cpu(vals[0]);
2252} 2253}
2253 2254
2254static struct net_device_stats *airo_get_stats(struct net_device *dev) 2255static struct net_device_stats *airo_get_stats(struct net_device *dev)
@@ -2261,10 +2262,10 @@ static struct net_device_stats *airo_get_stats(struct net_device *dev)
2261 set_bit(JOB_STATS, &local->jobs); 2262 set_bit(JOB_STATS, &local->jobs);
2262 wake_up_interruptible(&local->thr_wait); 2263 wake_up_interruptible(&local->thr_wait);
2263 } else 2264 } else
2264 airo_read_stats(local); 2265 airo_read_stats(dev);
2265 } 2266 }
2266 2267
2267 return &local->stats; 2268 return &dev->stats;
2268} 2269}
2269 2270
2270static void airo_set_promisc(struct airo_info *ai) { 2271static void airo_set_promisc(struct airo_info *ai) {
@@ -3093,7 +3094,7 @@ static int airo_thread(void *data) {
3093 else if (test_bit(JOB_XMIT11, &ai->jobs)) 3094 else if (test_bit(JOB_XMIT11, &ai->jobs))
3094 airo_end_xmit11(dev); 3095 airo_end_xmit11(dev);
3095 else if (test_bit(JOB_STATS, &ai->jobs)) 3096 else if (test_bit(JOB_STATS, &ai->jobs))
3096 airo_read_stats(ai); 3097 airo_read_stats(dev);
3097 else if (test_bit(JOB_WSTATS, &ai->jobs)) 3098 else if (test_bit(JOB_WSTATS, &ai->jobs))
3098 airo_read_wireless_stats(ai); 3099 airo_read_wireless_stats(ai);
3099 else if (test_bit(JOB_PROMISC, &ai->jobs)) 3100 else if (test_bit(JOB_PROMISC, &ai->jobs))
@@ -3289,7 +3290,7 @@ static irqreturn_t airo_interrupt(int irq, void *dev_id)
3289 3290
3290 skb = dev_alloc_skb( len + hdrlen + 2 + 2 ); 3291 skb = dev_alloc_skb( len + hdrlen + 2 + 2 );
3291 if ( !skb ) { 3292 if ( !skb ) {
3292 apriv->stats.rx_dropped++; 3293 dev->stats.rx_dropped++;
3293 goto badrx; 3294 goto badrx;
3294 } 3295 }
3295 skb_reserve(skb, 2); /* This way the IP header is aligned */ 3296 skb_reserve(skb, 2); /* This way the IP header is aligned */
@@ -3557,7 +3558,7 @@ static void mpi_receive_802_3(struct airo_info *ai)
3557 3558
3558 skb = dev_alloc_skb(len); 3559 skb = dev_alloc_skb(len);
3559 if (!skb) { 3560 if (!skb) {
3560 ai->stats.rx_dropped++; 3561 ai->dev->stats.rx_dropped++;
3561 goto badrx; 3562 goto badrx;
3562 } 3563 }
3563 buffer = skb_put(skb,len); 3564 buffer = skb_put(skb,len);
@@ -3650,7 +3651,7 @@ void mpi_receive_802_11 (struct airo_info *ai)
3650 3651
3651 skb = dev_alloc_skb( len + hdrlen + 2 ); 3652 skb = dev_alloc_skb( len + hdrlen + 2 );
3652 if ( !skb ) { 3653 if ( !skb ) {
3653 ai->stats.rx_dropped++; 3654 ai->dev->stats.rx_dropped++;
3654 goto badrx; 3655 goto badrx;
3655 } 3656 }
3656 buffer = (u16*)skb_put (skb, len + hdrlen); 3657 buffer = (u16*)skb_put (skb, len + hdrlen);
@@ -4560,22 +4561,13 @@ static ssize_t proc_read( struct file *file,
4560 size_t len, 4561 size_t len,
4561 loff_t *offset ) 4562 loff_t *offset )
4562{ 4563{
4563 loff_t pos = *offset; 4564 struct proc_data *priv = file->private_data;
4564 struct proc_data *priv = (struct proc_data*)file->private_data;
4565 4565
4566 if (!priv->rbuffer) 4566 if (!priv->rbuffer)
4567 return -EINVAL; 4567 return -EINVAL;
4568 4568
4569 if (pos < 0) 4569 return simple_read_from_buffer(buffer, len, offset, priv->rbuffer,
4570 return -EINVAL; 4570 priv->readlen);
4571 if (pos >= priv->readlen)
4572 return 0;
4573 if (len > priv->readlen - pos)
4574 len = priv->readlen - pos;
4575 if (copy_to_user(buffer, priv->rbuffer + pos, len))
4576 return -EFAULT;
4577 *offset = pos + len;
4578 return len;
4579} 4571}
4580 4572
4581/* 4573/*
@@ -5530,11 +5522,13 @@ static int airo_pci_suspend(struct pci_dev *pdev, pm_message_t state)
5530 Cmd cmd; 5522 Cmd cmd;
5531 Resp rsp; 5523 Resp rsp;
5532 5524
5533 if ((ai->APList == NULL) && 5525 if (!ai->APList)
5534 (ai->APList = kmalloc(sizeof(APListRid), GFP_KERNEL)) == NULL) 5526 ai->APList = kmalloc(sizeof(APListRid), GFP_KERNEL);
5527 if (!ai->APList)
5535 return -ENOMEM; 5528 return -ENOMEM;
5536 if ((ai->SSID == NULL) && 5529 if (!ai->SSID)
5537 (ai->SSID = kmalloc(sizeof(SsidRid), GFP_KERNEL)) == NULL) 5530 ai->SSID = kmalloc(sizeof(SsidRid), GFP_KERNEL);
5531 if (!ai->SSID)
5538 return -ENOMEM; 5532 return -ENOMEM;
5539 readAPListRid(ai, ai->APList); 5533 readAPListRid(ai, ai->APList);
5540 readSsidRid(ai, ai->SSID); 5534 readSsidRid(ai, ai->SSID);
@@ -5545,7 +5539,7 @@ static int airo_pci_suspend(struct pci_dev *pdev, pm_message_t state)
5545 disable_MAC(ai, 0); 5539 disable_MAC(ai, 0);
5546 netif_device_detach(dev); 5540 netif_device_detach(dev);
5547 ai->power = state; 5541 ai->power = state;
5548 cmd.cmd=HOSTSLEEP; 5542 cmd.cmd = HOSTSLEEP;
5549 issuecommand(ai, &cmd, &rsp); 5543 issuecommand(ai, &cmd, &rsp);
5550 5544
5551 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 5545 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
@@ -5575,7 +5569,7 @@ static int airo_pci_resume(struct pci_dev *pdev)
5575 msleep(100); 5569 msleep(100);
5576 } 5570 }
5577 5571
5578 set_bit (FLAG_COMMIT, &ai->flags); 5572 set_bit(FLAG_COMMIT, &ai->flags);
5579 disable_MAC(ai, 0); 5573 disable_MAC(ai, 0);
5580 msleep(200); 5574 msleep(200);
5581 if (ai->SSID) { 5575 if (ai->SSID) {
@@ -5602,9 +5596,6 @@ static int airo_pci_resume(struct pci_dev *pdev)
5602static int __init airo_init_module( void ) 5596static int __init airo_init_module( void )
5603{ 5597{
5604 int i; 5598 int i;
5605#if 0
5606 int have_isa_dev = 0;
5607#endif
5608 5599
5609 airo_entry = create_proc_entry("driver/aironet", 5600 airo_entry = create_proc_entry("driver/aironet",
5610 S_IFDIR | airo_perm, 5601 S_IFDIR | airo_perm,
@@ -5615,15 +5606,11 @@ static int __init airo_init_module( void )
5615 airo_entry->gid = proc_gid; 5606 airo_entry->gid = proc_gid;
5616 } 5607 }
5617 5608
5618 for( i = 0; i < 4 && io[i] && irq[i]; i++ ) { 5609 for (i = 0; i < 4 && io[i] && irq[i]; i++) {
5619 airo_print_info("", "Trying to configure ISA adapter at irq=%d " 5610 airo_print_info("", "Trying to configure ISA adapter at irq=%d "
5620 "io=0x%x", irq[i], io[i] ); 5611 "io=0x%x", irq[i], io[i] );
5621 if (init_airo_card( irq[i], io[i], 0, NULL )) 5612 if (init_airo_card( irq[i], io[i], 0, NULL ))
5622#if 0
5623 have_isa_dev = 1;
5624#else
5625 /* do nothing */ ; 5613 /* do nothing */ ;
5626#endif
5627 } 5614 }
5628 5615
5629#ifdef CONFIG_PCI 5616#ifdef CONFIG_PCI
@@ -5669,7 +5656,7 @@ static void __exit airo_cleanup_module( void )
5669 5656
5670static u8 airo_rssi_to_dbm (tdsRssiEntry *rssi_rid, u8 rssi) 5657static u8 airo_rssi_to_dbm (tdsRssiEntry *rssi_rid, u8 rssi)
5671{ 5658{
5672 if( !rssi_rid ) 5659 if (!rssi_rid)
5673 return 0; 5660 return 0;
5674 5661
5675 return (0x100 - rssi_rid[rssi].rssidBm); 5662 return (0x100 - rssi_rid[rssi].rssidBm);
@@ -5679,10 +5666,10 @@ static u8 airo_dbm_to_pct (tdsRssiEntry *rssi_rid, u8 dbm)
5679{ 5666{
5680 int i; 5667 int i;
5681 5668
5682 if( !rssi_rid ) 5669 if (!rssi_rid)
5683 return 0; 5670 return 0;
5684 5671
5685 for( i = 0; i < 256; i++ ) 5672 for (i = 0; i < 256; i++)
5686 if (rssi_rid[i].rssidBm == dbm) 5673 if (rssi_rid[i].rssidBm == dbm)
5687 return rssi_rid[i].rssipct; 5674 return rssi_rid[i].rssipct;
5688 5675
@@ -7164,6 +7151,7 @@ out:
7164 * format that the Wireless Tools will understand - Jean II 7151 * format that the Wireless Tools will understand - Jean II
7165 */ 7152 */
7166static inline char *airo_translate_scan(struct net_device *dev, 7153static inline char *airo_translate_scan(struct net_device *dev,
7154 struct iw_request_info *info,
7167 char *current_ev, 7155 char *current_ev,
7168 char *end_buf, 7156 char *end_buf,
7169 BSSListRid *bss) 7157 BSSListRid *bss)
@@ -7180,7 +7168,8 @@ static inline char *airo_translate_scan(struct net_device *dev,
7180 iwe.cmd = SIOCGIWAP; 7168 iwe.cmd = SIOCGIWAP;
7181 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 7169 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
7182 memcpy(iwe.u.ap_addr.sa_data, bss->bssid, ETH_ALEN); 7170 memcpy(iwe.u.ap_addr.sa_data, bss->bssid, ETH_ALEN);
7183 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_ADDR_LEN); 7171 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
7172 &iwe, IW_EV_ADDR_LEN);
7184 7173
7185 /* Other entries will be displayed in the order we give them */ 7174 /* Other entries will be displayed in the order we give them */
7186 7175
@@ -7190,7 +7179,8 @@ static inline char *airo_translate_scan(struct net_device *dev,
7190 iwe.u.data.length = 32; 7179 iwe.u.data.length = 32;
7191 iwe.cmd = SIOCGIWESSID; 7180 iwe.cmd = SIOCGIWESSID;
7192 iwe.u.data.flags = 1; 7181 iwe.u.data.flags = 1;
7193 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, bss->ssid); 7182 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
7183 &iwe, bss->ssid);
7194 7184
7195 /* Add mode */ 7185 /* Add mode */
7196 iwe.cmd = SIOCGIWMODE; 7186 iwe.cmd = SIOCGIWMODE;
@@ -7200,7 +7190,8 @@ static inline char *airo_translate_scan(struct net_device *dev,
7200 iwe.u.mode = IW_MODE_MASTER; 7190 iwe.u.mode = IW_MODE_MASTER;
7201 else 7191 else
7202 iwe.u.mode = IW_MODE_ADHOC; 7192 iwe.u.mode = IW_MODE_ADHOC;
7203 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_UINT_LEN); 7193 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
7194 &iwe, IW_EV_UINT_LEN);
7204 } 7195 }
7205 7196
7206 /* Add frequency */ 7197 /* Add frequency */
@@ -7211,7 +7202,8 @@ static inline char *airo_translate_scan(struct net_device *dev,
7211 */ 7202 */
7212 iwe.u.freq.m = frequency_list[iwe.u.freq.m - 1] * 100000; 7203 iwe.u.freq.m = frequency_list[iwe.u.freq.m - 1] * 100000;
7213 iwe.u.freq.e = 1; 7204 iwe.u.freq.e = 1;
7214 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_FREQ_LEN); 7205 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
7206 &iwe, IW_EV_FREQ_LEN);
7215 7207
7216 dBm = le16_to_cpu(bss->dBm); 7208 dBm = le16_to_cpu(bss->dBm);
7217 7209
@@ -7231,7 +7223,8 @@ static inline char *airo_translate_scan(struct net_device *dev,
7231 | IW_QUAL_DBM; 7223 | IW_QUAL_DBM;
7232 } 7224 }
7233 iwe.u.qual.noise = ai->wstats.qual.noise; 7225 iwe.u.qual.noise = ai->wstats.qual.noise;
7234 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_QUAL_LEN); 7226 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
7227 &iwe, IW_EV_QUAL_LEN);
7235 7228
7236 /* Add encryption capability */ 7229 /* Add encryption capability */
7237 iwe.cmd = SIOCGIWENCODE; 7230 iwe.cmd = SIOCGIWENCODE;
@@ -7240,11 +7233,12 @@ static inline char *airo_translate_scan(struct net_device *dev,
7240 else 7233 else
7241 iwe.u.data.flags = IW_ENCODE_DISABLED; 7234 iwe.u.data.flags = IW_ENCODE_DISABLED;
7242 iwe.u.data.length = 0; 7235 iwe.u.data.length = 0;
7243 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, bss->ssid); 7236 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
7237 &iwe, bss->ssid);
7244 7238
7245 /* Rate : stuffing multiple values in a single event require a bit 7239 /* Rate : stuffing multiple values in a single event require a bit
7246 * more of magic - Jean II */ 7240 * more of magic - Jean II */
7247 current_val = current_ev + IW_EV_LCP_LEN; 7241 current_val = current_ev + iwe_stream_lcp_len(info);
7248 7242
7249 iwe.cmd = SIOCGIWRATE; 7243 iwe.cmd = SIOCGIWRATE;
7250 /* Those two flags are ignored... */ 7244 /* Those two flags are ignored... */
@@ -7257,10 +7251,12 @@ static inline char *airo_translate_scan(struct net_device *dev,
7257 /* Bit rate given in 500 kb/s units (+ 0x80) */ 7251 /* Bit rate given in 500 kb/s units (+ 0x80) */
7258 iwe.u.bitrate.value = ((bss->rates[i] & 0x7f) * 500000); 7252 iwe.u.bitrate.value = ((bss->rates[i] & 0x7f) * 500000);
7259 /* Add new value to event */ 7253 /* Add new value to event */
7260 current_val = iwe_stream_add_value(current_ev, current_val, end_buf, &iwe, IW_EV_PARAM_LEN); 7254 current_val = iwe_stream_add_value(info, current_ev,
7255 current_val, end_buf,
7256 &iwe, IW_EV_PARAM_LEN);
7261 } 7257 }
7262 /* Check if we added any event */ 7258 /* Check if we added any event */
7263 if((current_val - current_ev) > IW_EV_LCP_LEN) 7259 if ((current_val - current_ev) > iwe_stream_lcp_len(info))
7264 current_ev = current_val; 7260 current_ev = current_val;
7265 7261
7266 /* Beacon interval */ 7262 /* Beacon interval */
@@ -7269,7 +7265,8 @@ static inline char *airo_translate_scan(struct net_device *dev,
7269 iwe.cmd = IWEVCUSTOM; 7265 iwe.cmd = IWEVCUSTOM;
7270 sprintf(buf, "bcn_int=%d", bss->beaconInterval); 7266 sprintf(buf, "bcn_int=%d", bss->beaconInterval);
7271 iwe.u.data.length = strlen(buf); 7267 iwe.u.data.length = strlen(buf);
7272 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf); 7268 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
7269 &iwe, buf);
7273 kfree(buf); 7270 kfree(buf);
7274 } 7271 }
7275 7272
@@ -7303,8 +7300,10 @@ static inline char *airo_translate_scan(struct net_device *dev,
7303 iwe.cmd = IWEVGENIE; 7300 iwe.cmd = IWEVGENIE;
7304 iwe.u.data.length = min(info_element->len + 2, 7301 iwe.u.data.length = min(info_element->len + 2,
7305 MAX_WPA_IE_LEN); 7302 MAX_WPA_IE_LEN);
7306 current_ev = iwe_stream_add_point(current_ev, end_buf, 7303 current_ev = iwe_stream_add_point(
7307 &iwe, (char *) info_element); 7304 info, current_ev,
7305 end_buf, &iwe,
7306 (char *) info_element);
7308 } 7307 }
7309 break; 7308 break;
7310 7309
@@ -7312,8 +7311,9 @@ static inline char *airo_translate_scan(struct net_device *dev,
7312 iwe.cmd = IWEVGENIE; 7311 iwe.cmd = IWEVGENIE;
7313 iwe.u.data.length = min(info_element->len + 2, 7312 iwe.u.data.length = min(info_element->len + 2,
7314 MAX_WPA_IE_LEN); 7313 MAX_WPA_IE_LEN);
7315 current_ev = iwe_stream_add_point(current_ev, end_buf, 7314 current_ev = iwe_stream_add_point(
7316 &iwe, (char *) info_element); 7315 info, current_ev, end_buf,
7316 &iwe, (char *) info_element);
7317 break; 7317 break;
7318 7318
7319 default: 7319 default:
@@ -7352,7 +7352,7 @@ static int airo_get_scan(struct net_device *dev,
7352 7352
7353 list_for_each_entry (net, &ai->network_list, list) { 7353 list_for_each_entry (net, &ai->network_list, list) {
7354 /* Translate to WE format this entry */ 7354 /* Translate to WE format this entry */
7355 current_ev = airo_translate_scan(dev, current_ev, 7355 current_ev = airo_translate_scan(dev, info, current_ev,
7356 extra + dwrq->length, 7356 extra + dwrq->length,
7357 &net->bss); 7357 &net->bss);
7358 7358
diff --git a/drivers/net/wireless/arlan-main.c b/drivers/net/wireless/arlan-main.c
index dbdfc9e39d20..dec5e874a54d 100644
--- a/drivers/net/wireless/arlan-main.c
+++ b/drivers/net/wireless/arlan-main.c
@@ -125,7 +125,7 @@ static inline int arlan_drop_tx(struct net_device *dev)
125{ 125{
126 struct arlan_private *priv = netdev_priv(dev); 126 struct arlan_private *priv = netdev_priv(dev);
127 127
128 priv->stats.tx_errors++; 128 dev->stats.tx_errors++;
129 if (priv->Conf->tx_delay_ms) 129 if (priv->Conf->tx_delay_ms)
130 { 130 {
131 priv->tx_done_delayed = jiffies + priv->Conf->tx_delay_ms * HZ / 1000 + 1; 131 priv->tx_done_delayed = jiffies + priv->Conf->tx_delay_ms * HZ / 1000 + 1;
@@ -1269,7 +1269,7 @@ static void arlan_tx_done_interrupt(struct net_device *dev, int status)
1269 { 1269 {
1270 IFDEBUG(ARLAN_DEBUG_TX_CHAIN) 1270 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
1271 printk("arlan intr: transmit OK\n"); 1271 printk("arlan intr: transmit OK\n");
1272 priv->stats.tx_packets++; 1272 dev->stats.tx_packets++;
1273 priv->bad = 0; 1273 priv->bad = 0;
1274 priv->reset = 0; 1274 priv->reset = 0;
1275 priv->retransmissions = 0; 1275 priv->retransmissions = 0;
@@ -1496,7 +1496,7 @@ static void arlan_rx_interrupt(struct net_device *dev, u_char rxStatus, u_short
1496 if (skb == NULL) 1496 if (skb == NULL)
1497 { 1497 {
1498 printk(KERN_ERR "%s: Memory squeeze, dropping packet.\n", dev->name); 1498 printk(KERN_ERR "%s: Memory squeeze, dropping packet.\n", dev->name);
1499 priv->stats.rx_dropped++; 1499 dev->stats.rx_dropped++;
1500 break; 1500 break;
1501 } 1501 }
1502 skb_reserve(skb, 2); 1502 skb_reserve(skb, 2);
@@ -1536,14 +1536,14 @@ static void arlan_rx_interrupt(struct net_device *dev, u_char rxStatus, u_short
1536 } 1536 }
1537 netif_rx(skb); 1537 netif_rx(skb);
1538 dev->last_rx = jiffies; 1538 dev->last_rx = jiffies;
1539 priv->stats.rx_packets++; 1539 dev->stats.rx_packets++;
1540 priv->stats.rx_bytes += pkt_len; 1540 dev->stats.rx_bytes += pkt_len;
1541 } 1541 }
1542 break; 1542 break;
1543 1543
1544 default: 1544 default:
1545 printk(KERN_ERR "arlan intr: received unknown status\n"); 1545 printk(KERN_ERR "arlan intr: received unknown status\n");
1546 priv->stats.rx_crc_errors++; 1546 dev->stats.rx_crc_errors++;
1547 break; 1547 break;
1548 } 1548 }
1549 ARLAN_DEBUG_EXIT("arlan_rx_interrupt"); 1549 ARLAN_DEBUG_EXIT("arlan_rx_interrupt");
@@ -1719,23 +1719,23 @@ static struct net_device_stats *arlan_statistics(struct net_device *dev)
1719 1719
1720 /* Update the statistics from the device registers. */ 1720 /* Update the statistics from the device registers. */
1721 1721
1722 READSHM(priv->stats.collisions, arlan->numReTransmissions, u_int); 1722 READSHM(dev->stats.collisions, arlan->numReTransmissions, u_int);
1723 READSHM(priv->stats.rx_crc_errors, arlan->numCRCErrors, u_int); 1723 READSHM(dev->stats.rx_crc_errors, arlan->numCRCErrors, u_int);
1724 READSHM(priv->stats.rx_dropped, arlan->numFramesDiscarded, u_int); 1724 READSHM(dev->stats.rx_dropped, arlan->numFramesDiscarded, u_int);
1725 READSHM(priv->stats.rx_fifo_errors, arlan->numRXBufferOverflows, u_int); 1725 READSHM(dev->stats.rx_fifo_errors, arlan->numRXBufferOverflows, u_int);
1726 READSHM(priv->stats.rx_frame_errors, arlan->numReceiveFramesLost, u_int); 1726 READSHM(dev->stats.rx_frame_errors, arlan->numReceiveFramesLost, u_int);
1727 READSHM(priv->stats.rx_over_errors, arlan->numRXOverruns, u_int); 1727 READSHM(dev->stats.rx_over_errors, arlan->numRXOverruns, u_int);
1728 READSHM(priv->stats.rx_packets, arlan->numDatagramsReceived, u_int); 1728 READSHM(dev->stats.rx_packets, arlan->numDatagramsReceived, u_int);
1729 READSHM(priv->stats.tx_aborted_errors, arlan->numAbortErrors, u_int); 1729 READSHM(dev->stats.tx_aborted_errors, arlan->numAbortErrors, u_int);
1730 READSHM(priv->stats.tx_carrier_errors, arlan->numStatusTimeouts, u_int); 1730 READSHM(dev->stats.tx_carrier_errors, arlan->numStatusTimeouts, u_int);
1731 READSHM(priv->stats.tx_dropped, arlan->numDatagramsDiscarded, u_int); 1731 READSHM(dev->stats.tx_dropped, arlan->numDatagramsDiscarded, u_int);
1732 READSHM(priv->stats.tx_fifo_errors, arlan->numTXUnderruns, u_int); 1732 READSHM(dev->stats.tx_fifo_errors, arlan->numTXUnderruns, u_int);
1733 READSHM(priv->stats.tx_packets, arlan->numDatagramsTransmitted, u_int); 1733 READSHM(dev->stats.tx_packets, arlan->numDatagramsTransmitted, u_int);
1734 READSHM(priv->stats.tx_window_errors, arlan->numHoldOffs, u_int); 1734 READSHM(dev->stats.tx_window_errors, arlan->numHoldOffs, u_int);
1735 1735
1736 ARLAN_DEBUG_EXIT("arlan_statistics"); 1736 ARLAN_DEBUG_EXIT("arlan_statistics");
1737 1737
1738 return &priv->stats; 1738 return &dev->stats;
1739} 1739}
1740 1740
1741 1741
diff --git a/drivers/net/wireless/arlan.h b/drivers/net/wireless/arlan.h
index 3ed1df75900f..fb3ad51a1caf 100644
--- a/drivers/net/wireless/arlan.h
+++ b/drivers/net/wireless/arlan.h
@@ -330,7 +330,6 @@ struct TxParam
330#define TX_RING_SIZE 2 330#define TX_RING_SIZE 2
331/* Information that need to be kept for each board. */ 331/* Information that need to be kept for each board. */
332struct arlan_private { 332struct arlan_private {
333 struct net_device_stats stats;
334 struct arlan_shmem __iomem * card; 333 struct arlan_shmem __iomem * card;
335 struct arlan_shmem * conf; 334 struct arlan_shmem * conf;
336 335
diff --git a/drivers/net/wireless/ath5k/Kconfig b/drivers/net/wireless/ath5k/Kconfig
index f1f2aea2eab4..75383a5df992 100644
--- a/drivers/net/wireless/ath5k/Kconfig
+++ b/drivers/net/wireless/ath5k/Kconfig
@@ -1,6 +1,9 @@
1config ATH5K 1config ATH5K
2 tristate "Atheros 5xxx wireless cards support" 2 tristate "Atheros 5xxx wireless cards support"
3 depends on PCI && MAC80211 && WLAN_80211 && EXPERIMENTAL 3 depends on PCI && MAC80211 && WLAN_80211 && EXPERIMENTAL
4 select MAC80211_LEDS
5 select LEDS_CLASS
6 select NEW_LEDS
4 ---help--- 7 ---help---
5 This module adds support for wireless adapters based on 8 This module adds support for wireless adapters based on
6 Atheros 5xxx chipset. 9 Atheros 5xxx chipset.
diff --git a/drivers/net/wireless/ath5k/base.c b/drivers/net/wireless/ath5k/base.c
index 635b9ac9aaa1..217d506527a9 100644
--- a/drivers/net/wireless/ath5k/base.c
+++ b/drivers/net/wireless/ath5k/base.c
@@ -58,11 +58,6 @@
58#include "reg.h" 58#include "reg.h"
59#include "debug.h" 59#include "debug.h"
60 60
61enum {
62 ATH_LED_TX,
63 ATH_LED_RX,
64};
65
66static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */ 61static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
67 62
68 63
@@ -167,8 +162,7 @@ static struct pci_driver ath5k_pci_driver = {
167/* 162/*
168 * Prototypes - MAC 802.11 stack related functions 163 * Prototypes - MAC 802.11 stack related functions
169 */ 164 */
170static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb, 165static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
171 struct ieee80211_tx_control *ctl);
172static int ath5k_reset(struct ieee80211_hw *hw); 166static int ath5k_reset(struct ieee80211_hw *hw);
173static int ath5k_start(struct ieee80211_hw *hw); 167static int ath5k_start(struct ieee80211_hw *hw);
174static void ath5k_stop(struct ieee80211_hw *hw); 168static void ath5k_stop(struct ieee80211_hw *hw);
@@ -196,8 +190,7 @@ static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
196static u64 ath5k_get_tsf(struct ieee80211_hw *hw); 190static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
197static void ath5k_reset_tsf(struct ieee80211_hw *hw); 191static void ath5k_reset_tsf(struct ieee80211_hw *hw);
198static int ath5k_beacon_update(struct ieee80211_hw *hw, 192static int ath5k_beacon_update(struct ieee80211_hw *hw,
199 struct sk_buff *skb, 193 struct sk_buff *skb);
200 struct ieee80211_tx_control *ctl);
201 194
202static struct ieee80211_ops ath5k_hw_ops = { 195static struct ieee80211_ops ath5k_hw_ops = {
203 .tx = ath5k_tx, 196 .tx = ath5k_tx,
@@ -214,7 +207,6 @@ static struct ieee80211_ops ath5k_hw_ops = {
214 .get_tx_stats = ath5k_get_tx_stats, 207 .get_tx_stats = ath5k_get_tx_stats,
215 .get_tsf = ath5k_get_tsf, 208 .get_tsf = ath5k_get_tsf,
216 .reset_tsf = ath5k_reset_tsf, 209 .reset_tsf = ath5k_reset_tsf,
217 .beacon_update = ath5k_beacon_update,
218}; 210};
219 211
220/* 212/*
@@ -251,9 +243,7 @@ static void ath5k_desc_free(struct ath5k_softc *sc,
251static int ath5k_rxbuf_setup(struct ath5k_softc *sc, 243static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
252 struct ath5k_buf *bf); 244 struct ath5k_buf *bf);
253static int ath5k_txbuf_setup(struct ath5k_softc *sc, 245static int ath5k_txbuf_setup(struct ath5k_softc *sc,
254 struct ath5k_buf *bf, 246 struct ath5k_buf *bf);
255 struct ieee80211_tx_control *ctl);
256
257static inline void ath5k_txbuf_free(struct ath5k_softc *sc, 247static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
258 struct ath5k_buf *bf) 248 struct ath5k_buf *bf)
259{ 249{
@@ -289,8 +279,7 @@ static void ath5k_tx_processq(struct ath5k_softc *sc,
289static void ath5k_tasklet_tx(unsigned long data); 279static void ath5k_tasklet_tx(unsigned long data);
290/* Beacon handling */ 280/* Beacon handling */
291static int ath5k_beacon_setup(struct ath5k_softc *sc, 281static int ath5k_beacon_setup(struct ath5k_softc *sc,
292 struct ath5k_buf *bf, 282 struct ath5k_buf *bf);
293 struct ieee80211_tx_control *ctl);
294static void ath5k_beacon_send(struct ath5k_softc *sc); 283static void ath5k_beacon_send(struct ath5k_softc *sc);
295static void ath5k_beacon_config(struct ath5k_softc *sc); 284static void ath5k_beacon_config(struct ath5k_softc *sc);
296static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); 285static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
@@ -314,13 +303,10 @@ static void ath5k_tasklet_reset(unsigned long data);
314 303
315static void ath5k_calibrate(unsigned long data); 304static void ath5k_calibrate(unsigned long data);
316/* LED functions */ 305/* LED functions */
317static void ath5k_led_off(unsigned long data); 306static int ath5k_init_leds(struct ath5k_softc *sc);
318static void ath5k_led_blink(struct ath5k_softc *sc, 307static void ath5k_led_enable(struct ath5k_softc *sc);
319 unsigned int on, 308static void ath5k_led_off(struct ath5k_softc *sc);
320 unsigned int off); 309static void ath5k_unregister_leds(struct ath5k_softc *sc);
321static void ath5k_led_event(struct ath5k_softc *sc,
322 int event);
323
324 310
325/* 311/*
326 * Module init/exit functions 312 * Module init/exit functions
@@ -458,13 +444,11 @@ ath5k_pci_probe(struct pci_dev *pdev,
458 444
459 /* Initialize driver private data */ 445 /* Initialize driver private data */
460 SET_IEEE80211_DEV(hw, &pdev->dev); 446 SET_IEEE80211_DEV(hw, &pdev->dev);
461 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS; 447 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
448 IEEE80211_HW_SIGNAL_DBM |
449 IEEE80211_HW_NOISE_DBM;
462 hw->extra_tx_headroom = 2; 450 hw->extra_tx_headroom = 2;
463 hw->channel_change_time = 5000; 451 hw->channel_change_time = 5000;
464 /* these names are misleading */
465 hw->max_rssi = -110; /* signal in dBm */
466 hw->max_noise = -110; /* noise in dBm */
467 hw->max_signal = 100; /* we will provide a percentage based on rssi */
468 sc = hw->priv; 452 sc = hw->priv;
469 sc->hw = hw; 453 sc->hw = hw;
470 sc->pdev = pdev; 454 sc->pdev = pdev;
@@ -603,8 +587,7 @@ ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
603 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 587 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
604 struct ath5k_softc *sc = hw->priv; 588 struct ath5k_softc *sc = hw->priv;
605 589
606 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) 590 ath5k_led_off(sc);
607 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
608 591
609 ath5k_stop_hw(sc); 592 ath5k_stop_hw(sc);
610 pci_save_state(pdev); 593 pci_save_state(pdev);
@@ -639,10 +622,7 @@ ath5k_pci_resume(struct pci_dev *pdev)
639 pci_write_config_byte(pdev, 0x41, 0); 622 pci_write_config_byte(pdev, 0x41, 0);
640 623
641 ath5k_init(sc); 624 ath5k_init(sc);
642 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) { 625 ath5k_led_enable(sc);
643 ath5k_hw_set_gpio_output(ah, sc->led_pin);
644 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
645 }
646 626
647 /* 627 /*
648 * Reset the key cache since some parts do not 628 * Reset the key cache since some parts do not
@@ -749,27 +729,6 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
749 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 729 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
750 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc); 730 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
751 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc); 731 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
752 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
753
754 sc->led_on = 0; /* low true */
755 /*
756 * Auto-enable soft led processing for IBM cards and for
757 * 5211 minipci cards.
758 */
759 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
760 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
761 __set_bit(ATH_STAT_LEDSOFT, sc->status);
762 sc->led_pin = 0;
763 }
764 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
765 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
766 __set_bit(ATH_STAT_LEDSOFT, sc->status);
767 sc->led_pin = 0;
768 }
769 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
770 ath5k_hw_set_gpio_output(ah, sc->led_pin);
771 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
772 }
773 732
774 ath5k_hw_get_lladdr(ah, mac); 733 ath5k_hw_get_lladdr(ah, mac);
775 SET_IEEE80211_PERM_ADDR(hw, mac); 734 SET_IEEE80211_PERM_ADDR(hw, mac);
@@ -783,6 +742,8 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
783 goto err_queues; 742 goto err_queues;
784 } 743 }
785 744
745 ath5k_init_leds(sc);
746
786 return 0; 747 return 0;
787err_queues: 748err_queues:
788 ath5k_txq_release(sc); 749 ath5k_txq_release(sc);
@@ -816,6 +777,7 @@ ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
816 ath5k_desc_free(sc, pdev); 777 ath5k_desc_free(sc, pdev);
817 ath5k_txq_release(sc); 778 ath5k_txq_release(sc);
818 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); 779 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
780 ath5k_unregister_leds(sc);
819 781
820 /* 782 /*
821 * NB: can't reclaim these until after ieee80211_ifdetach 783 * NB: can't reclaim these until after ieee80211_ifdetach
@@ -1067,65 +1029,9 @@ ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1067 return 0; 1029 return 0;
1068} 1030}
1069 1031
1070/*
1071 * TODO: CLEAN THIS !!!
1072 */
1073static void 1032static void
1074ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) 1033ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1075{ 1034{
1076 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1077 /* from Atheros NDIS driver, w/ permission */
1078 static const struct {
1079 u16 rate; /* tx/rx 802.11 rate */
1080 u16 timeOn; /* LED on time (ms) */
1081 u16 timeOff; /* LED off time (ms) */
1082 } blinkrates[] = {
1083 { 108, 40, 10 },
1084 { 96, 44, 11 },
1085 { 72, 50, 13 },
1086 { 48, 57, 14 },
1087 { 36, 67, 16 },
1088 { 24, 80, 20 },
1089 { 22, 100, 25 },
1090 { 18, 133, 34 },
1091 { 12, 160, 40 },
1092 { 10, 200, 50 },
1093 { 6, 240, 58 },
1094 { 4, 267, 66 },
1095 { 2, 400, 100 },
1096 { 0, 500, 130 }
1097 };
1098 const struct ath5k_rate_table *rt =
1099 ath5k_hw_get_rate_table(sc->ah, mode);
1100 unsigned int i, j;
1101
1102 BUG_ON(rt == NULL);
1103
1104 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1105 for (i = 0; i < 32; i++) {
1106 u8 ix = rt->rate_code_to_index[i];
1107 if (ix == 0xff) {
1108 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1109 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1110 continue;
1111 }
1112 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
1113 /* receive frames include FCS */
1114 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1115 IEEE80211_RADIOTAP_F_FCS;
1116 /* setup blink rate table to avoid per-packet lookup */
1117 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1118 if (blinkrates[j].rate == /* XXX why 7f? */
1119 (rt->rates[ix].dot11_rate&0x7f))
1120 break;
1121
1122 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1123 timeOn);
1124 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1125 timeOff);
1126 }
1127 }
1128
1129 sc->curmode = mode; 1035 sc->curmode = mode;
1130 1036
1131 if (mode == AR5K_MODE_11A) { 1037 if (mode == AR5K_MODE_11A) {
@@ -1297,36 +1203,36 @@ ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1297} 1203}
1298 1204
1299static int 1205static int
1300ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 1206ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1301 struct ieee80211_tx_control *ctl)
1302{ 1207{
1303 struct ath5k_hw *ah = sc->ah; 1208 struct ath5k_hw *ah = sc->ah;
1304 struct ath5k_txq *txq = sc->txq; 1209 struct ath5k_txq *txq = sc->txq;
1305 struct ath5k_desc *ds = bf->desc; 1210 struct ath5k_desc *ds = bf->desc;
1306 struct sk_buff *skb = bf->skb; 1211 struct sk_buff *skb = bf->skb;
1212 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1307 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 1213 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1308 int ret; 1214 int ret;
1309 1215
1310 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 1216 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1311 bf->ctl = *ctl; 1217
1312 /* XXX endianness */ 1218 /* XXX endianness */
1313 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 1219 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1314 PCI_DMA_TODEVICE); 1220 PCI_DMA_TODEVICE);
1315 1221
1316 if (ctl->flags & IEEE80211_TXCTL_NO_ACK) 1222 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1317 flags |= AR5K_TXDESC_NOACK; 1223 flags |= AR5K_TXDESC_NOACK;
1318 1224
1319 pktlen = skb->len; 1225 pktlen = skb->len;
1320 1226
1321 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) { 1227 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT)) {
1322 keyidx = ctl->key_idx; 1228 keyidx = info->control.hw_key->hw_key_idx;
1323 pktlen += ctl->icv_len; 1229 pktlen += info->control.icv_len;
1324 } 1230 }
1325
1326 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 1231 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1327 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, 1232 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1328 (sc->power_level * 2), ctl->tx_rate->hw_value, 1233 (sc->power_level * 2),
1329 ctl->retry_limit, keyidx, 0, flags, 0, 0); 1234 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1235 info->control.retry_limit, keyidx, 0, flags, 0, 0);
1330 if (ret) 1236 if (ret)
1331 goto err_unmap; 1237 goto err_unmap;
1332 1238
@@ -1335,7 +1241,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1335 1241
1336 spin_lock_bh(&txq->lock); 1242 spin_lock_bh(&txq->lock);
1337 list_add_tail(&bf->list, &txq->q); 1243 list_add_tail(&bf->list, &txq->q);
1338 sc->tx_stats.data[txq->qnum].len++; 1244 sc->tx_stats[txq->qnum].len++;
1339 if (txq->link == NULL) /* is this first packet? */ 1245 if (txq->link == NULL) /* is this first packet? */
1340 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr); 1246 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1341 else /* no, so only link it */ 1247 else /* no, so only link it */
@@ -1566,7 +1472,7 @@ ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1566 ath5k_txbuf_free(sc, bf); 1472 ath5k_txbuf_free(sc, bf);
1567 1473
1568 spin_lock_bh(&sc->txbuflock); 1474 spin_lock_bh(&sc->txbuflock);
1569 sc->tx_stats.data[txq->qnum].len--; 1475 sc->tx_stats[txq->qnum].len--;
1570 list_move_tail(&bf->list, &sc->txbuf); 1476 list_move_tail(&bf->list, &sc->txbuf);
1571 sc->txbuf_len++; 1477 sc->txbuf_len++;
1572 spin_unlock_bh(&sc->txbuflock); 1478 spin_unlock_bh(&sc->txbuflock);
@@ -1601,7 +1507,7 @@ ath5k_txq_cleanup(struct ath5k_softc *sc)
1601 sc->txqs[i].link); 1507 sc->txqs[i].link);
1602 } 1508 }
1603 } 1509 }
1604 ieee80211_start_queues(sc->hw); /* XXX move to callers */ 1510 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1605 1511
1606 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) 1512 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1607 if (sc->txqs[i].setup) 1513 if (sc->txqs[i].setup)
@@ -1698,9 +1604,9 @@ ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1698 /* Apparently when a default key is used to decrypt the packet 1604 /* Apparently when a default key is used to decrypt the packet
1699 the hw does not set the index used to decrypt. In such cases 1605 the hw does not set the index used to decrypt. In such cases
1700 get the index from the packet. */ 1606 get the index from the packet. */
1701 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) && 1607 if (ieee80211_has_protected(hdr->frame_control) &&
1702 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1608 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1703 skb->len >= hlen + 4) { 1609 skb->len >= hlen + 4) {
1704 keyix = skb->data[hlen + 3] >> 6; 1610 keyix = skb->data[hlen + 3] >> 6;
1705 1611
1706 if (test_bit(keyix, sc->keymap)) 1612 if (test_bit(keyix, sc->keymap))
@@ -1719,10 +1625,7 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1719 u32 hw_tu; 1625 u32 hw_tu;
1720 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1626 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1721 1627
1722 if ((le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_FTYPE) == 1628 if (ieee80211_is_beacon(mgmt->frame_control) &&
1723 IEEE80211_FTYPE_MGMT &&
1724 (le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_STYPE) ==
1725 IEEE80211_STYPE_BEACON &&
1726 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1629 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1727 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) { 1630 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1728 /* 1631 /*
@@ -1895,20 +1798,9 @@ accept:
1895 rxs.freq = sc->curchan->center_freq; 1798 rxs.freq = sc->curchan->center_freq;
1896 rxs.band = sc->curband->band; 1799 rxs.band = sc->curband->band;
1897 1800
1898 /*
1899 * signal quality:
1900 * the names here are misleading and the usage of these
1901 * values by iwconfig makes it even worse
1902 */
1903 /* noise floor in dBm, from the last noise calibration */
1904 rxs.noise = sc->ah->ah_noise_floor; 1801 rxs.noise = sc->ah->ah_noise_floor;
1905 /* signal level in dBm */ 1802 rxs.signal = rxs.noise + rs.rs_rssi;
1906 rxs.ssi = rxs.noise + rs.rs_rssi; 1803 rxs.qual = rs.rs_rssi * 100 / 64;
1907 /*
1908 * "signal" is actually displayed as Link Quality by iwconfig
1909 * we provide a percentage based on rssi (assuming max rssi 64)
1910 */
1911 rxs.signal = rs.rs_rssi * 100 / 64;
1912 1804
1913 rxs.antenna = rs.rs_antenna; 1805 rxs.antenna = rs.rs_antenna;
1914 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate); 1806 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
@@ -1921,8 +1813,6 @@ accept:
1921 ath5k_check_ibss_tsf(sc, skb, &rxs); 1813 ath5k_check_ibss_tsf(sc, skb, &rxs);
1922 1814
1923 __ieee80211_rx(sc->hw, skb, &rxs); 1815 __ieee80211_rx(sc->hw, skb, &rxs);
1924 sc->led_rxrate = rs.rs_rate;
1925 ath5k_led_event(sc, ATH_LED_RX);
1926next: 1816next:
1927 list_move_tail(&bf->list, &sc->rxbuf); 1817 list_move_tail(&bf->list, &sc->rxbuf);
1928 } while (ath5k_rxbuf_setup(sc, bf) == 0); 1818 } while (ath5k_rxbuf_setup(sc, bf) == 0);
@@ -1939,11 +1829,11 @@ next:
1939static void 1829static void
1940ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1830ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1941{ 1831{
1942 struct ieee80211_tx_status txs = {};
1943 struct ath5k_tx_status ts = {}; 1832 struct ath5k_tx_status ts = {};
1944 struct ath5k_buf *bf, *bf0; 1833 struct ath5k_buf *bf, *bf0;
1945 struct ath5k_desc *ds; 1834 struct ath5k_desc *ds;
1946 struct sk_buff *skb; 1835 struct sk_buff *skb;
1836 struct ieee80211_tx_info *info;
1947 int ret; 1837 int ret;
1948 1838
1949 spin_lock(&txq->lock); 1839 spin_lock(&txq->lock);
@@ -1963,28 +1853,29 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1963 } 1853 }
1964 1854
1965 skb = bf->skb; 1855 skb = bf->skb;
1856 info = IEEE80211_SKB_CB(skb);
1966 bf->skb = NULL; 1857 bf->skb = NULL;
1858
1967 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, 1859 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1968 PCI_DMA_TODEVICE); 1860 PCI_DMA_TODEVICE);
1969 1861
1970 txs.control = bf->ctl; 1862 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1971 txs.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1972 if (unlikely(ts.ts_status)) { 1863 if (unlikely(ts.ts_status)) {
1973 sc->ll_stats.dot11ACKFailureCount++; 1864 sc->ll_stats.dot11ACKFailureCount++;
1974 if (ts.ts_status & AR5K_TXERR_XRETRY) 1865 if (ts.ts_status & AR5K_TXERR_XRETRY)
1975 txs.excessive_retries = 1; 1866 info->status.excessive_retries = 1;
1976 else if (ts.ts_status & AR5K_TXERR_FILT) 1867 else if (ts.ts_status & AR5K_TXERR_FILT)
1977 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; 1868 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1978 } else { 1869 } else {
1979 txs.flags |= IEEE80211_TX_STATUS_ACK; 1870 info->flags |= IEEE80211_TX_STAT_ACK;
1980 txs.ack_signal = ts.ts_rssi; 1871 info->status.ack_signal = ts.ts_rssi;
1981 } 1872 }
1982 1873
1983 ieee80211_tx_status(sc->hw, skb, &txs); 1874 ieee80211_tx_status(sc->hw, skb);
1984 sc->tx_stats.data[txq->qnum].count++; 1875 sc->tx_stats[txq->qnum].count++;
1985 1876
1986 spin_lock(&sc->txbuflock); 1877 spin_lock(&sc->txbuflock);
1987 sc->tx_stats.data[txq->qnum].len--; 1878 sc->tx_stats[txq->qnum].len--;
1988 list_move_tail(&bf->list, &sc->txbuf); 1879 list_move_tail(&bf->list, &sc->txbuf);
1989 sc->txbuf_len++; 1880 sc->txbuf_len++;
1990 spin_unlock(&sc->txbuflock); 1881 spin_unlock(&sc->txbuflock);
@@ -2002,13 +1893,9 @@ ath5k_tasklet_tx(unsigned long data)
2002 struct ath5k_softc *sc = (void *)data; 1893 struct ath5k_softc *sc = (void *)data;
2003 1894
2004 ath5k_tx_processq(sc, sc->txq); 1895 ath5k_tx_processq(sc, sc->txq);
2005
2006 ath5k_led_event(sc, ATH_LED_TX);
2007} 1896}
2008 1897
2009 1898
2010
2011
2012/*****************\ 1899/*****************\
2013* Beacon handling * 1900* Beacon handling *
2014\*****************/ 1901\*****************/
@@ -2017,10 +1904,10 @@ ath5k_tasklet_tx(unsigned long data)
2017 * Setup the beacon frame for transmit. 1904 * Setup the beacon frame for transmit.
2018 */ 1905 */
2019static int 1906static int
2020ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 1907ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2021 struct ieee80211_tx_control *ctl)
2022{ 1908{
2023 struct sk_buff *skb = bf->skb; 1909 struct sk_buff *skb = bf->skb;
1910 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2024 struct ath5k_hw *ah = sc->ah; 1911 struct ath5k_hw *ah = sc->ah;
2025 struct ath5k_desc *ds; 1912 struct ath5k_desc *ds;
2026 int ret, antenna = 0; 1913 int ret, antenna = 0;
@@ -2059,7 +1946,8 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
2059 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1946 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2060 ieee80211_get_hdrlen_from_skb(skb), 1947 ieee80211_get_hdrlen_from_skb(skb),
2061 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 1948 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2062 ctl->tx_rate->hw_value, 1, AR5K_TXKEYIX_INVALID, 1949 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1950 1, AR5K_TXKEYIX_INVALID,
2063 antenna, flags, 0, 0); 1951 antenna, flags, 0, 0);
2064 if (ret) 1952 if (ret)
2065 goto err_unmap; 1953 goto err_unmap;
@@ -2382,11 +2270,7 @@ ath5k_stop_locked(struct ath5k_softc *sc)
2382 ieee80211_stop_queues(sc->hw); 2270 ieee80211_stop_queues(sc->hw);
2383 2271
2384 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2272 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2385 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) { 2273 ath5k_led_off(sc);
2386 del_timer_sync(&sc->led_tim);
2387 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2388 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2389 }
2390 ath5k_hw_set_intr(ah, 0); 2274 ath5k_hw_set_intr(ah, 0);
2391 } 2275 }
2392 ath5k_txq_cleanup(sc); 2276 ath5k_txq_cleanup(sc);
@@ -2582,54 +2466,123 @@ ath5k_calibrate(unsigned long data)
2582\***************/ 2466\***************/
2583 2467
2584static void 2468static void
2585ath5k_led_off(unsigned long data) 2469ath5k_led_enable(struct ath5k_softc *sc)
2586{ 2470{
2587 struct ath5k_softc *sc = (void *)data; 2471 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2588 2472 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2589 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status)) 2473 ath5k_led_off(sc);
2590 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2591 else {
2592 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2593 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2594 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2595 } 2474 }
2596} 2475}
2597 2476
2598/*
2599 * Blink the LED according to the specified on/off times.
2600 */
2601static void 2477static void
2602ath5k_led_blink(struct ath5k_softc *sc, unsigned int on, 2478ath5k_led_on(struct ath5k_softc *sc)
2603 unsigned int off)
2604{ 2479{
2605 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off); 2480 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2481 return;
2606 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on); 2482 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2607 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2608 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2609 sc->led_off = off;
2610 mod_timer(&sc->led_tim, jiffies + on);
2611} 2483}
2612 2484
2613static void 2485static void
2614ath5k_led_event(struct ath5k_softc *sc, int event) 2486ath5k_led_off(struct ath5k_softc *sc)
2615{ 2487{
2616 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status))) 2488 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2617 return; 2489 return;
2618 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status))) 2490 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2619 return; /* don't interrupt active blink */ 2491}
2620 switch (event) { 2492
2621 case ATH_LED_TX: 2493static void
2622 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon, 2494ath5k_led_brightness_set(struct led_classdev *led_dev,
2623 sc->hwmap[sc->led_txrate].ledoff); 2495 enum led_brightness brightness)
2624 break; 2496{
2625 case ATH_LED_RX: 2497 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2626 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon, 2498 led_dev);
2627 sc->hwmap[sc->led_rxrate].ledoff); 2499
2628 break; 2500 if (brightness == LED_OFF)
2501 ath5k_led_off(led->sc);
2502 else
2503 ath5k_led_on(led->sc);
2504}
2505
2506static int
2507ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2508 const char *name, char *trigger)
2509{
2510 int err;
2511
2512 led->sc = sc;
2513 strncpy(led->name, name, sizeof(led->name));
2514 led->led_dev.name = led->name;
2515 led->led_dev.default_trigger = trigger;
2516 led->led_dev.brightness_set = ath5k_led_brightness_set;
2517
2518 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2519 if (err)
2520 {
2521 ATH5K_WARN(sc, "could not register LED %s\n", name);
2522 led->sc = NULL;
2629 } 2523 }
2524 return err;
2630} 2525}
2631 2526
2527static void
2528ath5k_unregister_led(struct ath5k_led *led)
2529{
2530 if (!led->sc)
2531 return;
2532 led_classdev_unregister(&led->led_dev);
2533 ath5k_led_off(led->sc);
2534 led->sc = NULL;
2535}
2536
2537static void
2538ath5k_unregister_leds(struct ath5k_softc *sc)
2539{
2540 ath5k_unregister_led(&sc->rx_led);
2541 ath5k_unregister_led(&sc->tx_led);
2542}
2543
2544
2545static int
2546ath5k_init_leds(struct ath5k_softc *sc)
2547{
2548 int ret = 0;
2549 struct ieee80211_hw *hw = sc->hw;
2550 struct pci_dev *pdev = sc->pdev;
2551 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2552
2553 sc->led_on = 0; /* active low */
2632 2554
2555 /*
2556 * Auto-enable soft led processing for IBM cards and for
2557 * 5211 minipci cards.
2558 */
2559 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2560 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2561 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2562 sc->led_pin = 0;
2563 }
2564 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2565 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2566 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2567 sc->led_pin = 1;
2568 }
2569 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2570 goto out;
2571
2572 ath5k_led_enable(sc);
2573
2574 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2575 ret = ath5k_register_led(sc, &sc->rx_led, name,
2576 ieee80211_get_rx_led_name(hw));
2577 if (ret)
2578 goto out;
2579
2580 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2581 ret = ath5k_register_led(sc, &sc->tx_led, name,
2582 ieee80211_get_tx_led_name(hw));
2583out:
2584 return ret;
2585}
2633 2586
2634 2587
2635/********************\ 2588/********************\
@@ -2637,8 +2590,7 @@ ath5k_led_event(struct ath5k_softc *sc, int event)
2637\********************/ 2590\********************/
2638 2591
2639static int 2592static int
2640ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb, 2593ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2641 struct ieee80211_tx_control *ctl)
2642{ 2594{
2643 struct ath5k_softc *sc = hw->priv; 2595 struct ath5k_softc *sc = hw->priv;
2644 struct ath5k_buf *bf; 2596 struct ath5k_buf *bf;
@@ -2667,13 +2619,11 @@ ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2667 memmove(skb->data, skb->data+pad, hdrlen); 2619 memmove(skb->data, skb->data+pad, hdrlen);
2668 } 2620 }
2669 2621
2670 sc->led_txrate = ctl->tx_rate->hw_value;
2671
2672 spin_lock_irqsave(&sc->txbuflock, flags); 2622 spin_lock_irqsave(&sc->txbuflock, flags);
2673 if (list_empty(&sc->txbuf)) { 2623 if (list_empty(&sc->txbuf)) {
2674 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); 2624 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2675 spin_unlock_irqrestore(&sc->txbuflock, flags); 2625 spin_unlock_irqrestore(&sc->txbuflock, flags);
2676 ieee80211_stop_queue(hw, ctl->queue); 2626 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2677 return -1; 2627 return -1;
2678 } 2628 }
2679 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); 2629 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
@@ -2685,7 +2635,7 @@ ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2685 2635
2686 bf->skb = skb; 2636 bf->skb = skb;
2687 2637
2688 if (ath5k_txbuf_setup(sc, bf, ctl)) { 2638 if (ath5k_txbuf_setup(sc, bf)) {
2689 bf->skb = NULL; 2639 bf->skb = NULL;
2690 spin_lock_irqsave(&sc->txbuflock, flags); 2640 spin_lock_irqsave(&sc->txbuflock, flags);
2691 list_add_tail(&bf->list, &sc->txbuf); 2641 list_add_tail(&bf->list, &sc->txbuf);
@@ -2834,6 +2784,18 @@ ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2834 * a clean way of letting us retrieve this yet. */ 2784 * a clean way of letting us retrieve this yet. */
2835 ath5k_hw_set_associd(ah, ah->ah_bssid, 0); 2785 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2836 } 2786 }
2787
2788 if (conf->changed & IEEE80211_IFCC_BEACON &&
2789 vif->type == IEEE80211_IF_TYPE_IBSS) {
2790 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2791 if (!beacon) {
2792 ret = -ENOMEM;
2793 goto unlock;
2794 }
2795 /* call old handler for now */
2796 ath5k_beacon_update(hw, beacon);
2797 }
2798
2837 mutex_unlock(&sc->lock); 2799 mutex_unlock(&sc->lock);
2838 2800
2839 return ath5k_reset(hw); 2801 return ath5k_reset(hw);
@@ -3063,8 +3025,7 @@ ath5k_reset_tsf(struct ieee80211_hw *hw)
3063} 3025}
3064 3026
3065static int 3027static int
3066ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, 3028ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
3067 struct ieee80211_tx_control *ctl)
3068{ 3029{
3069 struct ath5k_softc *sc = hw->priv; 3030 struct ath5k_softc *sc = hw->priv;
3070 int ret; 3031 int ret;
@@ -3080,7 +3041,7 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
3080 3041
3081 ath5k_txbuf_free(sc, sc->bbuf); 3042 ath5k_txbuf_free(sc, sc->bbuf);
3082 sc->bbuf->skb = skb; 3043 sc->bbuf->skb = skb;
3083 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl); 3044 ret = ath5k_beacon_setup(sc, sc->bbuf);
3084 if (ret) 3045 if (ret)
3085 sc->bbuf->skb = NULL; 3046 sc->bbuf->skb = NULL;
3086 else 3047 else
diff --git a/drivers/net/wireless/ath5k/base.h b/drivers/net/wireless/ath5k/base.h
index 3a9755893018..47f414b09e67 100644
--- a/drivers/net/wireless/ath5k/base.h
+++ b/drivers/net/wireless/ath5k/base.h
@@ -45,6 +45,7 @@
45#include <linux/list.h> 45#include <linux/list.h>
46#include <linux/wireless.h> 46#include <linux/wireless.h>
47#include <linux/if_ether.h> 47#include <linux/if_ether.h>
48#include <linux/leds.h>
48 49
49#include "ath5k.h" 50#include "ath5k.h"
50#include "debug.h" 51#include "debug.h"
@@ -60,7 +61,6 @@ struct ath5k_buf {
60 dma_addr_t daddr; /* physical addr of desc */ 61 dma_addr_t daddr; /* physical addr of desc */
61 struct sk_buff *skb; /* skbuff for buf */ 62 struct sk_buff *skb; /* skbuff for buf */
62 dma_addr_t skbaddr;/* physical addr of skb data */ 63 dma_addr_t skbaddr;/* physical addr of skb data */
63 struct ieee80211_tx_control ctl;
64}; 64};
65 65
66/* 66/*
@@ -80,6 +80,19 @@ struct ath5k_txq {
80 bool setup; 80 bool setup;
81}; 81};
82 82
83#define ATH5K_LED_MAX_NAME_LEN 31
84
85/*
86 * State for LED triggers
87 */
88struct ath5k_led
89{
90 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
91 struct ath5k_softc *sc; /* driver state */
92 struct led_classdev led_dev; /* led classdev */
93};
94
95
83#if CHAN_DEBUG 96#if CHAN_DEBUG
84#define ATH_CHAN_MAX (26+26+26+200+200) 97#define ATH_CHAN_MAX (26+26+26+200+200)
85#else 98#else
@@ -92,7 +105,8 @@ struct ath5k_softc {
92 struct pci_dev *pdev; /* for dma mapping */ 105 struct pci_dev *pdev; /* for dma mapping */
93 void __iomem *iobase; /* address of the device */ 106 void __iomem *iobase; /* address of the device */
94 struct mutex lock; /* dev-level lock */ 107 struct mutex lock; /* dev-level lock */
95 struct ieee80211_tx_queue_stats tx_stats; 108 /* FIXME: how many does it really need? */
109 struct ieee80211_tx_queue_stats tx_stats[16];
96 struct ieee80211_low_level_stats ll_stats; 110 struct ieee80211_low_level_stats ll_stats;
97 struct ieee80211_hw *hw; /* IEEE 802.11 common */ 111 struct ieee80211_hw *hw; /* IEEE 802.11 common */
98 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 112 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
@@ -118,13 +132,11 @@ struct ath5k_softc {
118 size_t desc_len; /* size of TX/RX descriptors */ 132 size_t desc_len; /* size of TX/RX descriptors */
119 u16 cachelsz; /* cache line size */ 133 u16 cachelsz; /* cache line size */
120 134
121 DECLARE_BITMAP(status, 6); 135 DECLARE_BITMAP(status, 4);
122#define ATH_STAT_INVALID 0 /* disable hardware accesses */ 136#define ATH_STAT_INVALID 0 /* disable hardware accesses */
123#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */ 137#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
124#define ATH_STAT_PROMISC 2 138#define ATH_STAT_PROMISC 2
125#define ATH_STAT_LEDBLINKING 3 /* LED blink operation active */ 139#define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
126#define ATH_STAT_LEDENDBLINK 4 /* finish LED blink operation */
127#define ATH_STAT_LEDSOFT 5 /* enable LED gpio status */
128 140
129 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */ 141 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
130 unsigned int curmode; /* current phy mode */ 142 unsigned int curmode; /* current phy mode */
@@ -132,13 +144,6 @@ struct ath5k_softc {
132 144
133 struct ieee80211_vif *vif; 145 struct ieee80211_vif *vif;
134 146
135 struct {
136 u8 rxflags; /* radiotap rx flags */
137 u8 txflags; /* radiotap tx flags */
138 u16 ledon; /* softled on time */
139 u16 ledoff; /* softled off time */
140 } hwmap[32]; /* h/w rate ix mappings */
141
142 enum ath5k_int imask; /* interrupt mask copy */ 147 enum ath5k_int imask; /* interrupt mask copy */
143 148
144 DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */ 149 DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */
@@ -148,9 +153,6 @@ struct ath5k_softc {
148 unsigned int led_pin, /* GPIO pin for driving LED */ 153 unsigned int led_pin, /* GPIO pin for driving LED */
149 led_on, /* pin setting for LED on */ 154 led_on, /* pin setting for LED on */
150 led_off; /* off time for current blink */ 155 led_off; /* off time for current blink */
151 struct timer_list led_tim; /* led off timer */
152 u8 led_rxrate; /* current rx rate for LED */
153 u8 led_txrate; /* current tx rate for LED */
154 156
155 struct tasklet_struct restq; /* reset tasklet */ 157 struct tasklet_struct restq; /* reset tasklet */
156 158
@@ -159,6 +161,7 @@ struct ath5k_softc {
159 spinlock_t rxbuflock; 161 spinlock_t rxbuflock;
160 u32 *rxlink; /* link ptr in last RX desc */ 162 u32 *rxlink; /* link ptr in last RX desc */
161 struct tasklet_struct rxtq; /* rx intr tasklet */ 163 struct tasklet_struct rxtq; /* rx intr tasklet */
164 struct ath5k_led rx_led; /* rx led */
162 165
163 struct list_head txbuf; /* transmit buffer */ 166 struct list_head txbuf; /* transmit buffer */
164 spinlock_t txbuflock; 167 spinlock_t txbuflock;
@@ -167,6 +170,7 @@ struct ath5k_softc {
167 170
168 struct ath5k_txq *txq; /* beacon and tx*/ 171 struct ath5k_txq *txq; /* beacon and tx*/
169 struct tasklet_struct txtq; /* tx intr tasklet */ 172 struct tasklet_struct txtq; /* tx intr tasklet */
173 struct ath5k_led tx_led; /* tx led */
170 174
171 struct ath5k_buf *bbuf; /* beacon buffer */ 175 struct ath5k_buf *bbuf; /* beacon buffer */
172 unsigned int bhalq, /* SW q for outgoing beacons */ 176 unsigned int bhalq, /* SW q for outgoing beacons */
diff --git a/drivers/net/wireless/ath5k/hw.c b/drivers/net/wireless/ath5k/hw.c
index 77990b56860b..c6d12c53bda4 100644
--- a/drivers/net/wireless/ath5k/hw.c
+++ b/drivers/net/wireless/ath5k/hw.c
@@ -31,14 +31,14 @@
31#include "base.h" 31#include "base.h"
32#include "debug.h" 32#include "debug.h"
33 33
34/*Rate tables*/ 34/* Rate tables */
35static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A; 35static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A;
36static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B; 36static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B;
37static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G; 37static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G;
38static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; 38static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO;
39static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; 39static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
40 40
41/*Prototypes*/ 41/* Prototypes */
42static int ath5k_hw_nic_reset(struct ath5k_hw *, u32); 42static int ath5k_hw_nic_reset(struct ath5k_hw *, u32);
43static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool); 43static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool);
44static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *, 44static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
diff --git a/drivers/net/wireless/atmel.c b/drivers/net/wireless/atmel.c
index d1acef7e0b14..bd35bb0a1480 100644
--- a/drivers/net/wireless/atmel.c
+++ b/drivers/net/wireless/atmel.c
@@ -433,7 +433,6 @@ struct atmel_private {
433 struct net_device *dev; 433 struct net_device *dev;
434 struct device *sys_dev; 434 struct device *sys_dev;
435 struct iw_statistics wstats; 435 struct iw_statistics wstats;
436 struct net_device_stats stats; // device stats
437 spinlock_t irqlock, timerlock; // spinlocks 436 spinlock_t irqlock, timerlock; // spinlocks
438 enum { BUS_TYPE_PCCARD, BUS_TYPE_PCI } bus_type; 437 enum { BUS_TYPE_PCCARD, BUS_TYPE_PCI } bus_type;
439 enum { 438 enum {
@@ -694,9 +693,9 @@ static void tx_done_irq(struct atmel_private *priv)
694 693
695 if (type == TX_PACKET_TYPE_DATA) { 694 if (type == TX_PACKET_TYPE_DATA) {
696 if (status == TX_STATUS_SUCCESS) 695 if (status == TX_STATUS_SUCCESS)
697 priv->stats.tx_packets++; 696 priv->dev->stats.tx_packets++;
698 else 697 else
699 priv->stats.tx_errors++; 698 priv->dev->stats.tx_errors++;
700 netif_wake_queue(priv->dev); 699 netif_wake_queue(priv->dev);
701 } 700 }
702 } 701 }
@@ -792,13 +791,13 @@ static int start_tx(struct sk_buff *skb, struct net_device *dev)
792 791
793 if (priv->card && priv->present_callback && 792 if (priv->card && priv->present_callback &&
794 !(*priv->present_callback)(priv->card)) { 793 !(*priv->present_callback)(priv->card)) {
795 priv->stats.tx_errors++; 794 dev->stats.tx_errors++;
796 dev_kfree_skb(skb); 795 dev_kfree_skb(skb);
797 return 0; 796 return 0;
798 } 797 }
799 798
800 if (priv->station_state != STATION_STATE_READY) { 799 if (priv->station_state != STATION_STATE_READY) {
801 priv->stats.tx_errors++; 800 dev->stats.tx_errors++;
802 dev_kfree_skb(skb); 801 dev_kfree_skb(skb);
803 return 0; 802 return 0;
804 } 803 }
@@ -815,7 +814,7 @@ static int start_tx(struct sk_buff *skb, struct net_device *dev)
815 initial + 18 (+30-12) */ 814 initial + 18 (+30-12) */
816 815
817 if (!(buff = find_tx_buff(priv, len + 18))) { 816 if (!(buff = find_tx_buff(priv, len + 18))) {
818 priv->stats.tx_dropped++; 817 dev->stats.tx_dropped++;
819 spin_unlock_irqrestore(&priv->irqlock, flags); 818 spin_unlock_irqrestore(&priv->irqlock, flags);
820 spin_unlock_bh(&priv->timerlock); 819 spin_unlock_bh(&priv->timerlock);
821 netif_stop_queue(dev); 820 netif_stop_queue(dev);
@@ -851,7 +850,7 @@ static int start_tx(struct sk_buff *skb, struct net_device *dev)
851 /* low bit of first byte of destination tells us if broadcast */ 850 /* low bit of first byte of destination tells us if broadcast */
852 tx_update_descriptor(priv, *(skb->data) & 0x01, len + 18, buff, TX_PACKET_TYPE_DATA); 851 tx_update_descriptor(priv, *(skb->data) & 0x01, len + 18, buff, TX_PACKET_TYPE_DATA);
853 dev->trans_start = jiffies; 852 dev->trans_start = jiffies;
854 priv->stats.tx_bytes += len; 853 dev->stats.tx_bytes += len;
855 854
856 spin_unlock_irqrestore(&priv->irqlock, flags); 855 spin_unlock_irqrestore(&priv->irqlock, flags);
857 spin_unlock_bh(&priv->timerlock); 856 spin_unlock_bh(&priv->timerlock);
@@ -895,7 +894,7 @@ static void fast_rx_path(struct atmel_private *priv,
895 } 894 }
896 895
897 if (!(skb = dev_alloc_skb(msdu_size + 14))) { 896 if (!(skb = dev_alloc_skb(msdu_size + 14))) {
898 priv->stats.rx_dropped++; 897 priv->dev->stats.rx_dropped++;
899 return; 898 return;
900 } 899 }
901 900
@@ -908,7 +907,7 @@ static void fast_rx_path(struct atmel_private *priv,
908 crc = crc32_le(crc, skbp + 12, msdu_size); 907 crc = crc32_le(crc, skbp + 12, msdu_size);
909 atmel_copy_to_host(priv->dev, (void *)&netcrc, rx_packet_loc + 30 + msdu_size, 4); 908 atmel_copy_to_host(priv->dev, (void *)&netcrc, rx_packet_loc + 30 + msdu_size, 4);
910 if ((crc ^ 0xffffffff) != netcrc) { 909 if ((crc ^ 0xffffffff) != netcrc) {
911 priv->stats.rx_crc_errors++; 910 priv->dev->stats.rx_crc_errors++;
912 dev_kfree_skb(skb); 911 dev_kfree_skb(skb);
913 return; 912 return;
914 } 913 }
@@ -924,8 +923,8 @@ static void fast_rx_path(struct atmel_private *priv,
924 skb->protocol = eth_type_trans(skb, priv->dev); 923 skb->protocol = eth_type_trans(skb, priv->dev);
925 skb->ip_summed = CHECKSUM_NONE; 924 skb->ip_summed = CHECKSUM_NONE;
926 netif_rx(skb); 925 netif_rx(skb);
927 priv->stats.rx_bytes += 12 + msdu_size; 926 priv->dev->stats.rx_bytes += 12 + msdu_size;
928 priv->stats.rx_packets++; 927 priv->dev->stats.rx_packets++;
929} 928}
930 929
931/* Test to see if the packet in card memory at packet_loc has a valid CRC 930/* Test to see if the packet in card memory at packet_loc has a valid CRC
@@ -991,7 +990,7 @@ static void frag_rx_path(struct atmel_private *priv,
991 crc = crc32_le(crc, &priv->rx_buf[12], msdu_size); 990 crc = crc32_le(crc, &priv->rx_buf[12], msdu_size);
992 atmel_copy_to_host(priv->dev, (void *)&netcrc, rx_packet_loc + msdu_size, 4); 991 atmel_copy_to_host(priv->dev, (void *)&netcrc, rx_packet_loc + msdu_size, 4);
993 if ((crc ^ 0xffffffff) != netcrc) { 992 if ((crc ^ 0xffffffff) != netcrc) {
994 priv->stats.rx_crc_errors++; 993 priv->dev->stats.rx_crc_errors++;
995 memset(priv->frag_source, 0xff, 6); 994 memset(priv->frag_source, 0xff, 6);
996 } 995 }
997 } 996 }
@@ -1009,7 +1008,7 @@ static void frag_rx_path(struct atmel_private *priv,
1009 msdu_size); 1008 msdu_size);
1010 atmel_copy_to_host(priv->dev, (void *)&netcrc, rx_packet_loc + msdu_size, 4); 1009 atmel_copy_to_host(priv->dev, (void *)&netcrc, rx_packet_loc + msdu_size, 4);
1011 if ((crc ^ 0xffffffff) != netcrc) { 1010 if ((crc ^ 0xffffffff) != netcrc) {
1012 priv->stats.rx_crc_errors++; 1011 priv->dev->stats.rx_crc_errors++;
1013 memset(priv->frag_source, 0xff, 6); 1012 memset(priv->frag_source, 0xff, 6);
1014 more_frags = 1; /* don't send broken assembly */ 1013 more_frags = 1; /* don't send broken assembly */
1015 } 1014 }
@@ -1021,7 +1020,7 @@ static void frag_rx_path(struct atmel_private *priv,
1021 if (!more_frags) { /* last one */ 1020 if (!more_frags) { /* last one */
1022 memset(priv->frag_source, 0xff, 6); 1021 memset(priv->frag_source, 0xff, 6);
1023 if (!(skb = dev_alloc_skb(priv->frag_len + 14))) { 1022 if (!(skb = dev_alloc_skb(priv->frag_len + 14))) {
1024 priv->stats.rx_dropped++; 1023 priv->dev->stats.rx_dropped++;
1025 } else { 1024 } else {
1026 skb_reserve(skb, 2); 1025 skb_reserve(skb, 2);
1027 memcpy(skb_put(skb, priv->frag_len + 12), 1026 memcpy(skb_put(skb, priv->frag_len + 12),
@@ -1031,8 +1030,8 @@ static void frag_rx_path(struct atmel_private *priv,
1031 skb->protocol = eth_type_trans(skb, priv->dev); 1030 skb->protocol = eth_type_trans(skb, priv->dev);
1032 skb->ip_summed = CHECKSUM_NONE; 1031 skb->ip_summed = CHECKSUM_NONE;
1033 netif_rx(skb); 1032 netif_rx(skb);
1034 priv->stats.rx_bytes += priv->frag_len + 12; 1033 priv->dev->stats.rx_bytes += priv->frag_len + 12;
1035 priv->stats.rx_packets++; 1034 priv->dev->stats.rx_packets++;
1036 } 1035 }
1037 } 1036 }
1038 } else 1037 } else
@@ -1057,7 +1056,7 @@ static void rx_done_irq(struct atmel_private *priv)
1057 if (status == 0xc1) /* determined by experiment */ 1056 if (status == 0xc1) /* determined by experiment */
1058 priv->wstats.discard.nwid++; 1057 priv->wstats.discard.nwid++;
1059 else 1058 else
1060 priv->stats.rx_errors++; 1059 priv->dev->stats.rx_errors++;
1061 goto next; 1060 goto next;
1062 } 1061 }
1063 1062
@@ -1065,7 +1064,7 @@ static void rx_done_irq(struct atmel_private *priv)
1065 rx_packet_loc = atmel_rmem16(priv, atmel_rx(priv, RX_DESC_MSDU_POS_OFFSET, priv->rx_desc_head)); 1064 rx_packet_loc = atmel_rmem16(priv, atmel_rx(priv, RX_DESC_MSDU_POS_OFFSET, priv->rx_desc_head));
1066 1065
1067 if (msdu_size < 30) { 1066 if (msdu_size < 30) {
1068 priv->stats.rx_errors++; 1067 priv->dev->stats.rx_errors++;
1069 goto next; 1068 goto next;
1070 } 1069 }
1071 1070
@@ -1123,7 +1122,7 @@ static void rx_done_irq(struct atmel_private *priv)
1123 msdu_size -= 4; 1122 msdu_size -= 4;
1124 crc = crc32_le(crc, (unsigned char *)&priv->rx_buf, msdu_size); 1123 crc = crc32_le(crc, (unsigned char *)&priv->rx_buf, msdu_size);
1125 if ((crc ^ 0xffffffff) != (*((u32 *)&priv->rx_buf[msdu_size]))) { 1124 if ((crc ^ 0xffffffff) != (*((u32 *)&priv->rx_buf[msdu_size]))) {
1126 priv->stats.rx_crc_errors++; 1125 priv->dev->stats.rx_crc_errors++;
1127 goto next; 1126 goto next;
1128 } 1127 }
1129 } 1128 }
@@ -1250,12 +1249,6 @@ static irqreturn_t service_interrupt(int irq, void *dev_id)
1250 } 1249 }
1251} 1250}
1252 1251
1253static struct net_device_stats *atmel_get_stats(struct net_device *dev)
1254{
1255 struct atmel_private *priv = netdev_priv(dev);
1256 return &priv->stats;
1257}
1258
1259static struct iw_statistics *atmel_get_wireless_stats(struct net_device *dev) 1252static struct iw_statistics *atmel_get_wireless_stats(struct net_device *dev)
1260{ 1253{
1261 struct atmel_private *priv = netdev_priv(dev); 1254 struct atmel_private *priv = netdev_priv(dev);
@@ -1518,8 +1511,6 @@ struct net_device *init_atmel_card(unsigned short irq, unsigned long port,
1518 priv->crc_ok_cnt = priv->crc_ko_cnt = 0; 1511 priv->crc_ok_cnt = priv->crc_ko_cnt = 0;
1519 } else 1512 } else
1520 priv->probe_crc = 0; 1513 priv->probe_crc = 0;
1521 memset(&priv->stats, 0, sizeof(priv->stats));
1522 memset(&priv->wstats, 0, sizeof(priv->wstats));
1523 priv->last_qual = jiffies; 1514 priv->last_qual = jiffies;
1524 priv->last_beacon_timestamp = 0; 1515 priv->last_beacon_timestamp = 0;
1525 memset(priv->frag_source, 0xff, sizeof(priv->frag_source)); 1516 memset(priv->frag_source, 0xff, sizeof(priv->frag_source));
@@ -1568,7 +1559,6 @@ struct net_device *init_atmel_card(unsigned short irq, unsigned long port,
1568 dev->change_mtu = atmel_change_mtu; 1559 dev->change_mtu = atmel_change_mtu;
1569 dev->set_mac_address = atmel_set_mac_address; 1560 dev->set_mac_address = atmel_set_mac_address;
1570 dev->hard_start_xmit = start_tx; 1561 dev->hard_start_xmit = start_tx;
1571 dev->get_stats = atmel_get_stats;
1572 dev->wireless_handlers = (struct iw_handler_def *)&atmel_handler_def; 1562 dev->wireless_handlers = (struct iw_handler_def *)&atmel_handler_def;
1573 dev->do_ioctl = atmel_ioctl; 1563 dev->do_ioctl = atmel_ioctl;
1574 dev->irq = irq; 1564 dev->irq = irq;
@@ -2320,30 +2310,40 @@ static int atmel_get_scan(struct net_device *dev,
2320 iwe.cmd = SIOCGIWAP; 2310 iwe.cmd = SIOCGIWAP;
2321 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 2311 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
2322 memcpy(iwe.u.ap_addr.sa_data, priv->BSSinfo[i].BSSID, 6); 2312 memcpy(iwe.u.ap_addr.sa_data, priv->BSSinfo[i].BSSID, 6);
2323 current_ev = iwe_stream_add_event(current_ev, extra + IW_SCAN_MAX_DATA, &iwe, IW_EV_ADDR_LEN); 2313 current_ev = iwe_stream_add_event(info, current_ev,
2314 extra + IW_SCAN_MAX_DATA,
2315 &iwe, IW_EV_ADDR_LEN);
2324 2316
2325 iwe.u.data.length = priv->BSSinfo[i].SSIDsize; 2317 iwe.u.data.length = priv->BSSinfo[i].SSIDsize;
2326 if (iwe.u.data.length > 32) 2318 if (iwe.u.data.length > 32)
2327 iwe.u.data.length = 32; 2319 iwe.u.data.length = 32;
2328 iwe.cmd = SIOCGIWESSID; 2320 iwe.cmd = SIOCGIWESSID;
2329 iwe.u.data.flags = 1; 2321 iwe.u.data.flags = 1;
2330 current_ev = iwe_stream_add_point(current_ev, extra + IW_SCAN_MAX_DATA, &iwe, priv->BSSinfo[i].SSID); 2322 current_ev = iwe_stream_add_point(info, current_ev,
2323 extra + IW_SCAN_MAX_DATA,
2324 &iwe, priv->BSSinfo[i].SSID);
2331 2325
2332 iwe.cmd = SIOCGIWMODE; 2326 iwe.cmd = SIOCGIWMODE;
2333 iwe.u.mode = priv->BSSinfo[i].BSStype; 2327 iwe.u.mode = priv->BSSinfo[i].BSStype;
2334 current_ev = iwe_stream_add_event(current_ev, extra + IW_SCAN_MAX_DATA, &iwe, IW_EV_UINT_LEN); 2328 current_ev = iwe_stream_add_event(info, current_ev,
2329 extra + IW_SCAN_MAX_DATA,
2330 &iwe, IW_EV_UINT_LEN);
2335 2331
2336 iwe.cmd = SIOCGIWFREQ; 2332 iwe.cmd = SIOCGIWFREQ;
2337 iwe.u.freq.m = priv->BSSinfo[i].channel; 2333 iwe.u.freq.m = priv->BSSinfo[i].channel;
2338 iwe.u.freq.e = 0; 2334 iwe.u.freq.e = 0;
2339 current_ev = iwe_stream_add_event(current_ev, extra + IW_SCAN_MAX_DATA, &iwe, IW_EV_FREQ_LEN); 2335 current_ev = iwe_stream_add_event(info, current_ev,
2336 extra + IW_SCAN_MAX_DATA,
2337 &iwe, IW_EV_FREQ_LEN);
2340 2338
2341 /* Add quality statistics */ 2339 /* Add quality statistics */
2342 iwe.cmd = IWEVQUAL; 2340 iwe.cmd = IWEVQUAL;
2343 iwe.u.qual.level = priv->BSSinfo[i].RSSI; 2341 iwe.u.qual.level = priv->BSSinfo[i].RSSI;
2344 iwe.u.qual.qual = iwe.u.qual.level; 2342 iwe.u.qual.qual = iwe.u.qual.level;
2345 /* iwe.u.qual.noise = SOMETHING */ 2343 /* iwe.u.qual.noise = SOMETHING */
2346 current_ev = iwe_stream_add_event(current_ev, extra + IW_SCAN_MAX_DATA , &iwe, IW_EV_QUAL_LEN); 2344 current_ev = iwe_stream_add_event(info, current_ev,
2345 extra + IW_SCAN_MAX_DATA,
2346 &iwe, IW_EV_QUAL_LEN);
2347 2347
2348 2348
2349 iwe.cmd = SIOCGIWENCODE; 2349 iwe.cmd = SIOCGIWENCODE;
@@ -2352,7 +2352,9 @@ static int atmel_get_scan(struct net_device *dev,
2352 else 2352 else
2353 iwe.u.data.flags = IW_ENCODE_DISABLED; 2353 iwe.u.data.flags = IW_ENCODE_DISABLED;
2354 iwe.u.data.length = 0; 2354 iwe.u.data.length = 0;
2355 current_ev = iwe_stream_add_point(current_ev, extra + IW_SCAN_MAX_DATA, &iwe, NULL); 2355 current_ev = iwe_stream_add_point(info, current_ev,
2356 extra + IW_SCAN_MAX_DATA,
2357 &iwe, NULL);
2356 } 2358 }
2357 2359
2358 /* Length of data */ 2360 /* Length of data */
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index d3db298c05fc..edcdfa366452 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -410,8 +410,7 @@ enum {
410#define B43_IRQ_TIMEOUT 0x80000000 410#define B43_IRQ_TIMEOUT 0x80000000
411 411
412#define B43_IRQ_ALL 0xFFFFFFFF 412#define B43_IRQ_ALL 0xFFFFFFFF
413#define B43_IRQ_MASKTEMPLATE (B43_IRQ_MAC_SUSPENDED | \ 413#define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \
414 B43_IRQ_TBTT_INDI | \
415 B43_IRQ_ATIM_END | \ 414 B43_IRQ_ATIM_END | \
416 B43_IRQ_PMQ | \ 415 B43_IRQ_PMQ | \
417 B43_IRQ_MAC_TXERR | \ 416 B43_IRQ_MAC_TXERR | \
@@ -423,6 +422,28 @@ enum {
423 B43_IRQ_RFKILL | \ 422 B43_IRQ_RFKILL | \
424 B43_IRQ_TX_OK) 423 B43_IRQ_TX_OK)
425 424
425/* The firmware register to fetch the debug-IRQ reason from. */
426#define B43_DEBUGIRQ_REASON_REG 63
427/* Debug-IRQ reasons. */
428#define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */
429#define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */
430#define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */
431#define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */
432#define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */
433
434/* The firmware register that contains the "marker" line. */
435#define B43_MARKER_ID_REG 2
436#define B43_MARKER_LINE_REG 3
437
438/* The firmware register to fetch the panic reason from. */
439#define B43_FWPANIC_REASON_REG 3
440/* Firmware panic reason codes */
441#define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */
442#define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */
443
444/* The firmware register that contains the watchdog counter. */
445#define B43_WATCHDOG_REG 1
446
426/* Device specific rate values. 447/* Device specific rate values.
427 * The actual values defined here are (rate_in_mbps * 2). 448 * The actual values defined here are (rate_in_mbps * 2).
428 * Some code depends on this. Don't change it. */ 449 * Some code depends on this. Don't change it. */
@@ -733,7 +754,6 @@ struct b43_wl {
733 /* The beacon we are currently using (AP or IBSS mode). 754 /* The beacon we are currently using (AP or IBSS mode).
734 * This beacon stuff is protected by the irq_lock. */ 755 * This beacon stuff is protected by the irq_lock. */
735 struct sk_buff *current_beacon; 756 struct sk_buff *current_beacon;
736 struct ieee80211_tx_control beacon_txctl;
737 bool beacon0_uploaded; 757 bool beacon0_uploaded;
738 bool beacon1_uploaded; 758 bool beacon1_uploaded;
739 bool beacon_templates_virgin; /* Never wrote the templates? */ 759 bool beacon_templates_virgin; /* Never wrote the templates? */
@@ -767,6 +787,13 @@ struct b43_firmware {
767 u16 rev; 787 u16 rev;
768 /* Firmware patchlevel */ 788 /* Firmware patchlevel */
769 u16 patch; 789 u16 patch;
790
791 /* Set to true, if we are using an opensource firmware. */
792 bool opensource;
793 /* Set to true, if the core needs a PCM firmware, but
794 * we failed to load one. This is always false for
795 * core rev > 10, as these don't need PCM firmware. */
796 bool pcm_request_failed;
770}; 797};
771 798
772/* Device (802.11 core) initialization status. */ 799/* Device (802.11 core) initialization status. */
@@ -940,22 +967,6 @@ static inline bool __b43_warn_on_dummy(bool x) { return x; }
940# define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x))) 967# define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
941#endif 968#endif
942 969
943/** Limit a value between two limits */
944#ifdef limit_value
945# undef limit_value
946#endif
947#define limit_value(value, min, max) \
948 ({ \
949 typeof(value) __value = (value); \
950 typeof(value) __min = (min); \
951 typeof(value) __max = (max); \
952 if (__value < __min) \
953 __value = __min; \
954 else if (__value > __max) \
955 __value = __max; \
956 __value; \
957 })
958
959/* Convert an integer to a Q5.2 value */ 970/* Convert an integer to a Q5.2 value */
960#define INT_TO_Q52(i) ((i) << 2) 971#define INT_TO_Q52(i) ((i) << 2)
961/* Convert a Q5.2 value to an integer (precision loss!) */ 972/* Convert a Q5.2 value to an integer (precision loss!) */
diff --git a/drivers/net/wireless/b43/debugfs.c b/drivers/net/wireless/b43/debugfs.c
index 7fca2ebc747f..29851bc1101f 100644
--- a/drivers/net/wireless/b43/debugfs.c
+++ b/drivers/net/wireless/b43/debugfs.c
@@ -74,70 +74,327 @@ struct b43_dfs_file * fops_to_dfs_file(struct b43_wldev *dev,
74 } while (0) 74 } while (0)
75 75
76 76
77/* wl->irq_lock is locked */ 77/* The biggest address values for SHM access from the debugfs files. */
78static ssize_t tsf_read_file(struct b43_wldev *dev, 78#define B43_MAX_SHM_ROUTING 4
79 char *buf, size_t bufsize) 79#define B43_MAX_SHM_ADDR 0xFFFF
80
81static ssize_t shm16read__read_file(struct b43_wldev *dev,
82 char *buf, size_t bufsize)
80{ 83{
81 ssize_t count = 0; 84 ssize_t count = 0;
82 u64 tsf; 85 unsigned int routing, addr;
86 u16 val;
83 87
84 b43_tsf_read(dev, &tsf); 88 routing = dev->dfsentry->shm16read_routing_next;
85 fappend("0x%08x%08x\n", 89 addr = dev->dfsentry->shm16read_addr_next;
86 (unsigned int)((tsf & 0xFFFFFFFF00000000ULL) >> 32), 90 if ((routing > B43_MAX_SHM_ROUTING) ||
87 (unsigned int)(tsf & 0xFFFFFFFFULL)); 91 (addr > B43_MAX_SHM_ADDR))
92 return -EDESTADDRREQ;
93
94 val = b43_shm_read16(dev, routing, addr);
95 fappend("0x%04X\n", val);
88 96
89 return count; 97 return count;
90} 98}
91 99
92/* wl->irq_lock is locked */ 100static int shm16read__write_file(struct b43_wldev *dev,
93static int tsf_write_file(struct b43_wldev *dev, 101 const char *buf, size_t count)
94 const char *buf, size_t count)
95{ 102{
96 u64 tsf; 103 unsigned int routing, addr;
104 int res;
97 105
98 if (sscanf(buf, "%llu", (unsigned long long *)(&tsf)) != 1) 106 res = sscanf(buf, "0x%X 0x%X", &routing, &addr);
107 if (res != 2)
99 return -EINVAL; 108 return -EINVAL;
100 b43_tsf_write(dev, tsf); 109 if (routing > B43_MAX_SHM_ROUTING)
110 return -EADDRNOTAVAIL;
111 if (addr > B43_MAX_SHM_ADDR)
112 return -EADDRNOTAVAIL;
113 if (routing == B43_SHM_SHARED) {
114 if ((addr % 2) != 0)
115 return -EADDRNOTAVAIL;
116 }
117
118 dev->dfsentry->shm16read_routing_next = routing;
119 dev->dfsentry->shm16read_addr_next = addr;
101 120
102 return 0; 121 return 0;
103} 122}
104 123
105/* wl->irq_lock is locked */ 124static int shm16write__write_file(struct b43_wldev *dev,
106static ssize_t ucode_regs_read_file(struct b43_wldev *dev, 125 const char *buf, size_t count)
126{
127 unsigned int routing, addr, mask, set;
128 u16 val;
129 int res;
130 unsigned long flags;
131
132 res = sscanf(buf, "0x%X 0x%X 0x%X 0x%X",
133 &routing, &addr, &mask, &set);
134 if (res != 4)
135 return -EINVAL;
136 if (routing > B43_MAX_SHM_ROUTING)
137 return -EADDRNOTAVAIL;
138 if (addr > B43_MAX_SHM_ADDR)
139 return -EADDRNOTAVAIL;
140 if (routing == B43_SHM_SHARED) {
141 if ((addr % 2) != 0)
142 return -EADDRNOTAVAIL;
143 }
144 if ((mask > 0xFFFF) || (set > 0xFFFF))
145 return -E2BIG;
146
147 spin_lock_irqsave(&dev->wl->shm_lock, flags);
148 if (mask == 0)
149 val = 0;
150 else
151 val = __b43_shm_read16(dev, routing, addr);
152 val &= mask;
153 val |= set;
154 __b43_shm_write16(dev, routing, addr, val);
155 spin_unlock_irqrestore(&dev->wl->shm_lock, flags);
156
157 return 0;
158}
159
160static ssize_t shm32read__read_file(struct b43_wldev *dev,
107 char *buf, size_t bufsize) 161 char *buf, size_t bufsize)
108{ 162{
109 ssize_t count = 0; 163 ssize_t count = 0;
110 int i; 164 unsigned int routing, addr;
165 u32 val;
166
167 routing = dev->dfsentry->shm32read_routing_next;
168 addr = dev->dfsentry->shm32read_addr_next;
169 if ((routing > B43_MAX_SHM_ROUTING) ||
170 (addr > B43_MAX_SHM_ADDR))
171 return -EDESTADDRREQ;
172
173 val = b43_shm_read32(dev, routing, addr);
174 fappend("0x%08X\n", val);
111 175
112 for (i = 0; i < 64; i++) { 176 return count;
113 fappend("r%d = 0x%04x\n", i, 177}
114 b43_shm_read16(dev, B43_SHM_SCRATCH, i)); 178
179static int shm32read__write_file(struct b43_wldev *dev,
180 const char *buf, size_t count)
181{
182 unsigned int routing, addr;
183 int res;
184
185 res = sscanf(buf, "0x%X 0x%X", &routing, &addr);
186 if (res != 2)
187 return -EINVAL;
188 if (routing > B43_MAX_SHM_ROUTING)
189 return -EADDRNOTAVAIL;
190 if (addr > B43_MAX_SHM_ADDR)
191 return -EADDRNOTAVAIL;
192 if (routing == B43_SHM_SHARED) {
193 if ((addr % 2) != 0)
194 return -EADDRNOTAVAIL;
115 } 195 }
116 196
197 dev->dfsentry->shm32read_routing_next = routing;
198 dev->dfsentry->shm32read_addr_next = addr;
199
200 return 0;
201}
202
203static int shm32write__write_file(struct b43_wldev *dev,
204 const char *buf, size_t count)
205{
206 unsigned int routing, addr, mask, set;
207 u32 val;
208 int res;
209 unsigned long flags;
210
211 res = sscanf(buf, "0x%X 0x%X 0x%X 0x%X",
212 &routing, &addr, &mask, &set);
213 if (res != 4)
214 return -EINVAL;
215 if (routing > B43_MAX_SHM_ROUTING)
216 return -EADDRNOTAVAIL;
217 if (addr > B43_MAX_SHM_ADDR)
218 return -EADDRNOTAVAIL;
219 if (routing == B43_SHM_SHARED) {
220 if ((addr % 2) != 0)
221 return -EADDRNOTAVAIL;
222 }
223 if ((mask > 0xFFFFFFFF) || (set > 0xFFFFFFFF))
224 return -E2BIG;
225
226 spin_lock_irqsave(&dev->wl->shm_lock, flags);
227 if (mask == 0)
228 val = 0;
229 else
230 val = __b43_shm_read32(dev, routing, addr);
231 val &= mask;
232 val |= set;
233 __b43_shm_write32(dev, routing, addr, val);
234 spin_unlock_irqrestore(&dev->wl->shm_lock, flags);
235
236 return 0;
237}
238
239/* The biggest MMIO address that we allow access to from the debugfs files. */
240#define B43_MAX_MMIO_ACCESS (0xF00 - 1)
241
242static ssize_t mmio16read__read_file(struct b43_wldev *dev,
243 char *buf, size_t bufsize)
244{
245 ssize_t count = 0;
246 unsigned int addr;
247 u16 val;
248
249 addr = dev->dfsentry->mmio16read_next;
250 if (addr > B43_MAX_MMIO_ACCESS)
251 return -EDESTADDRREQ;
252
253 val = b43_read16(dev, addr);
254 fappend("0x%04X\n", val);
255
256 return count;
257}
258
259static int mmio16read__write_file(struct b43_wldev *dev,
260 const char *buf, size_t count)
261{
262 unsigned int addr;
263 int res;
264
265 res = sscanf(buf, "0x%X", &addr);
266 if (res != 1)
267 return -EINVAL;
268 if (addr > B43_MAX_MMIO_ACCESS)
269 return -EADDRNOTAVAIL;
270 if ((addr % 2) != 0)
271 return -EINVAL;
272
273 dev->dfsentry->mmio16read_next = addr;
274
275 return 0;
276}
277
278static int mmio16write__write_file(struct b43_wldev *dev,
279 const char *buf, size_t count)
280{
281 unsigned int addr, mask, set;
282 int res;
283 u16 val;
284
285 res = sscanf(buf, "0x%X 0x%X 0x%X", &addr, &mask, &set);
286 if (res != 3)
287 return -EINVAL;
288 if (addr > B43_MAX_MMIO_ACCESS)
289 return -EADDRNOTAVAIL;
290 if ((mask > 0xFFFF) || (set > 0xFFFF))
291 return -E2BIG;
292 if ((addr % 2) != 0)
293 return -EINVAL;
294
295 if (mask == 0)
296 val = 0;
297 else
298 val = b43_read16(dev, addr);
299 val &= mask;
300 val |= set;
301 b43_write16(dev, addr, val);
302
303 return 0;
304}
305
306static ssize_t mmio32read__read_file(struct b43_wldev *dev,
307 char *buf, size_t bufsize)
308{
309 ssize_t count = 0;
310 unsigned int addr;
311 u32 val;
312
313 addr = dev->dfsentry->mmio32read_next;
314 if (addr > B43_MAX_MMIO_ACCESS)
315 return -EDESTADDRREQ;
316
317 val = b43_read32(dev, addr);
318 fappend("0x%08X\n", val);
319
117 return count; 320 return count;
118} 321}
119 322
323static int mmio32read__write_file(struct b43_wldev *dev,
324 const char *buf, size_t count)
325{
326 unsigned int addr;
327 int res;
328
329 res = sscanf(buf, "0x%X", &addr);
330 if (res != 1)
331 return -EINVAL;
332 if (addr > B43_MAX_MMIO_ACCESS)
333 return -EADDRNOTAVAIL;
334 if ((addr % 4) != 0)
335 return -EINVAL;
336
337 dev->dfsentry->mmio32read_next = addr;
338
339 return 0;
340}
341
342static int mmio32write__write_file(struct b43_wldev *dev,
343 const char *buf, size_t count)
344{
345 unsigned int addr, mask, set;
346 int res;
347 u32 val;
348
349 res = sscanf(buf, "0x%X 0x%X 0x%X", &addr, &mask, &set);
350 if (res != 3)
351 return -EINVAL;
352 if (addr > B43_MAX_MMIO_ACCESS)
353 return -EADDRNOTAVAIL;
354 if ((mask > 0xFFFFFFFF) || (set > 0xFFFFFFFF))
355 return -E2BIG;
356 if ((addr % 4) != 0)
357 return -EINVAL;
358
359 if (mask == 0)
360 val = 0;
361 else
362 val = b43_read32(dev, addr);
363 val &= mask;
364 val |= set;
365 b43_write32(dev, addr, val);
366
367 return 0;
368}
369
120/* wl->irq_lock is locked */ 370/* wl->irq_lock is locked */
121static ssize_t shm_read_file(struct b43_wldev *dev, 371static ssize_t tsf_read_file(struct b43_wldev *dev,
122 char *buf, size_t bufsize) 372 char *buf, size_t bufsize)
123{ 373{
124 ssize_t count = 0; 374 ssize_t count = 0;
125 int i; 375 u64 tsf;
126 u16 tmp;
127 __le16 *le16buf = (__le16 *)buf;
128 376
129 for (i = 0; i < 0x1000; i++) { 377 b43_tsf_read(dev, &tsf);
130 if (bufsize < sizeof(tmp)) 378 fappend("0x%08x%08x\n",
131 break; 379 (unsigned int)((tsf & 0xFFFFFFFF00000000ULL) >> 32),
132 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 2 * i); 380 (unsigned int)(tsf & 0xFFFFFFFFULL));
133 le16buf[i] = cpu_to_le16(tmp);
134 count += sizeof(tmp);
135 bufsize -= sizeof(tmp);
136 }
137 381
138 return count; 382 return count;
139} 383}
140 384
385/* wl->irq_lock is locked */
386static int tsf_write_file(struct b43_wldev *dev,
387 const char *buf, size_t count)
388{
389 u64 tsf;
390
391 if (sscanf(buf, "%llu", (unsigned long long *)(&tsf)) != 1)
392 return -EINVAL;
393 b43_tsf_write(dev, tsf);
394
395 return 0;
396}
397
141static ssize_t txstat_read_file(struct b43_wldev *dev, 398static ssize_t txstat_read_file(struct b43_wldev *dev,
142 char *buf, size_t bufsize) 399 char *buf, size_t bufsize)
143{ 400{
@@ -270,24 +527,22 @@ static int restart_write_file(struct b43_wldev *dev,
270 return err; 527 return err;
271} 528}
272 529
273static ssize_t append_lo_table(ssize_t count, char *buf, const size_t bufsize, 530static unsigned long calc_expire_secs(unsigned long now,
274 struct b43_loctl table[B43_NR_BB][B43_NR_RF]) 531 unsigned long time,
532 unsigned long expire)
275{ 533{
276 unsigned int i, j; 534 expire = time + expire;
277 struct b43_loctl *ctl; 535
278 536 if (time_after(now, expire))
279 for (i = 0; i < B43_NR_BB; i++) { 537 return 0; /* expired */
280 for (j = 0; j < B43_NR_RF; j++) { 538 if (expire < now) {
281 ctl = &(table[i][j]); 539 /* jiffies wrapped */
282 fappend("(bbatt %2u, rfatt %2u) -> " 540 expire -= MAX_JIFFY_OFFSET;
283 "(I %+3d, Q %+3d, Used: %d, Calibrated: %d)\n", 541 now -= MAX_JIFFY_OFFSET;
284 i, j, ctl->i, ctl->q,
285 ctl->used,
286 b43_loctl_is_calibrated(ctl));
287 }
288 } 542 }
543 B43_WARN_ON(expire < now);
289 544
290 return count; 545 return (expire - now) / HZ;
291} 546}
292 547
293static ssize_t loctls_read_file(struct b43_wldev *dev, 548static ssize_t loctls_read_file(struct b43_wldev *dev,
@@ -296,27 +551,45 @@ static ssize_t loctls_read_file(struct b43_wldev *dev,
296 ssize_t count = 0; 551 ssize_t count = 0;
297 struct b43_txpower_lo_control *lo; 552 struct b43_txpower_lo_control *lo;
298 int i, err = 0; 553 int i, err = 0;
554 struct b43_lo_calib *cal;
555 unsigned long now = jiffies;
556 struct b43_phy *phy = &dev->phy;
299 557
300 if (dev->phy.type != B43_PHYTYPE_G) { 558 if (phy->type != B43_PHYTYPE_G) {
301 fappend("Device is not a G-PHY\n"); 559 fappend("Device is not a G-PHY\n");
302 err = -ENODEV; 560 err = -ENODEV;
303 goto out; 561 goto out;
304 } 562 }
305 lo = dev->phy.lo_control; 563 lo = phy->lo_control;
306 fappend("-- Local Oscillator calibration data --\n\n"); 564 fappend("-- Local Oscillator calibration data --\n\n");
307 fappend("Measured: %d, Rebuild: %d, HW-power-control: %d\n", 565 fappend("HW-power-control enabled: %d\n",
308 lo->lo_measured,
309 lo->rebuild,
310 dev->phy.hardware_power_control); 566 dev->phy.hardware_power_control);
311 fappend("TX Bias: 0x%02X, TX Magn: 0x%02X\n", 567 fappend("TX Bias: 0x%02X, TX Magn: 0x%02X (expire in %lu sec)\n",
312 lo->tx_bias, lo->tx_magn); 568 lo->tx_bias, lo->tx_magn,
313 fappend("Power Vector: 0x%08X%08X\n", 569 calc_expire_secs(now, lo->txctl_measured_time,
570 B43_LO_TXCTL_EXPIRE));
571 fappend("Power Vector: 0x%08X%08X (expires in %lu sec)\n",
314 (unsigned int)((lo->power_vector & 0xFFFFFFFF00000000ULL) >> 32), 572 (unsigned int)((lo->power_vector & 0xFFFFFFFF00000000ULL) >> 32),
315 (unsigned int)(lo->power_vector & 0x00000000FFFFFFFFULL)); 573 (unsigned int)(lo->power_vector & 0x00000000FFFFFFFFULL),
316 fappend("\nControl table WITH PADMIX:\n"); 574 calc_expire_secs(now, lo->pwr_vec_read_time,
317 count = append_lo_table(count, buf, bufsize, lo->with_padmix); 575 B43_LO_PWRVEC_EXPIRE));
318 fappend("\nControl table WITHOUT PADMIX:\n"); 576
319 count = append_lo_table(count, buf, bufsize, lo->no_padmix); 577 fappend("\nCalibrated settings:\n");
578 list_for_each_entry(cal, &lo->calib_list, list) {
579 bool active;
580
581 active = (b43_compare_bbatt(&cal->bbatt, &phy->bbatt) &&
582 b43_compare_rfatt(&cal->rfatt, &phy->rfatt));
583 fappend("BB(%d), RF(%d,%d) -> I=%d, Q=%d "
584 "(expires in %lu sec)%s\n",
585 cal->bbatt.att,
586 cal->rfatt.att, cal->rfatt.with_padmix,
587 cal->ctl.i, cal->ctl.q,
588 calc_expire_secs(now, cal->calib_time,
589 B43_LO_CALIB_EXPIRE),
590 active ? " ACTIVE" : "");
591 }
592
320 fappend("\nUsed RF attenuation values: Value(WithPadmix flag)\n"); 593 fappend("\nUsed RF attenuation values: Value(WithPadmix flag)\n");
321 for (i = 0; i < lo->rfatt_list.len; i++) { 594 for (i = 0; i < lo->rfatt_list.len; i++) {
322 fappend("%u(%d), ", 595 fappend("%u(%d), ",
@@ -351,7 +624,7 @@ static ssize_t b43_debugfs_read(struct file *file, char __user *userbuf,
351 struct b43_dfs_file *dfile; 624 struct b43_dfs_file *dfile;
352 ssize_t uninitialized_var(ret); 625 ssize_t uninitialized_var(ret);
353 char *buf; 626 char *buf;
354 const size_t bufsize = 1024 * 128; 627 const size_t bufsize = 1024 * 16; /* 16 kiB buffer */
355 const size_t buforder = get_order(bufsize); 628 const size_t buforder = get_order(bufsize);
356 int err = 0; 629 int err = 0;
357 630
@@ -380,8 +653,6 @@ static ssize_t b43_debugfs_read(struct file *file, char __user *userbuf,
380 err = -ENOMEM; 653 err = -ENOMEM;
381 goto out_unlock; 654 goto out_unlock;
382 } 655 }
383 /* Sparse warns about the following memset, because it has a big
384 * size value. That warning is bogus, so I will ignore it. --mb */
385 memset(buf, 0, bufsize); 656 memset(buf, 0, bufsize);
386 if (dfops->take_irqlock) { 657 if (dfops->take_irqlock) {
387 spin_lock_irq(&dev->wl->irq_lock); 658 spin_lock_irq(&dev->wl->irq_lock);
@@ -482,9 +753,15 @@ out_unlock:
482 .take_irqlock = _take_irqlock, \ 753 .take_irqlock = _take_irqlock, \
483 } 754 }
484 755
756B43_DEBUGFS_FOPS(shm16read, shm16read__read_file, shm16read__write_file, 1);
757B43_DEBUGFS_FOPS(shm16write, NULL, shm16write__write_file, 1);
758B43_DEBUGFS_FOPS(shm32read, shm32read__read_file, shm32read__write_file, 1);
759B43_DEBUGFS_FOPS(shm32write, NULL, shm32write__write_file, 1);
760B43_DEBUGFS_FOPS(mmio16read, mmio16read__read_file, mmio16read__write_file, 1);
761B43_DEBUGFS_FOPS(mmio16write, NULL, mmio16write__write_file, 1);
762B43_DEBUGFS_FOPS(mmio32read, mmio32read__read_file, mmio32read__write_file, 1);
763B43_DEBUGFS_FOPS(mmio32write, NULL, mmio32write__write_file, 1);
485B43_DEBUGFS_FOPS(tsf, tsf_read_file, tsf_write_file, 1); 764B43_DEBUGFS_FOPS(tsf, tsf_read_file, tsf_write_file, 1);
486B43_DEBUGFS_FOPS(ucode_regs, ucode_regs_read_file, NULL, 1);
487B43_DEBUGFS_FOPS(shm, shm_read_file, NULL, 1);
488B43_DEBUGFS_FOPS(txstat, txstat_read_file, NULL, 0); 765B43_DEBUGFS_FOPS(txstat, txstat_read_file, NULL, 0);
489B43_DEBUGFS_FOPS(txpower_g, txpower_g_read_file, txpower_g_write_file, 0); 766B43_DEBUGFS_FOPS(txpower_g, txpower_g_read_file, txpower_g_write_file, 0);
490B43_DEBUGFS_FOPS(restart, NULL, restart_write_file, 1); 767B43_DEBUGFS_FOPS(restart, NULL, restart_write_file, 1);
@@ -523,6 +800,8 @@ static void b43_add_dynamic_debug(struct b43_wldev *dev)
523 add_dyn_dbg("debug_dmaverbose", B43_DBG_DMAVERBOSE, 0); 800 add_dyn_dbg("debug_dmaverbose", B43_DBG_DMAVERBOSE, 0);
524 add_dyn_dbg("debug_pwork_fast", B43_DBG_PWORK_FAST, 0); 801 add_dyn_dbg("debug_pwork_fast", B43_DBG_PWORK_FAST, 0);
525 add_dyn_dbg("debug_pwork_stop", B43_DBG_PWORK_STOP, 0); 802 add_dyn_dbg("debug_pwork_stop", B43_DBG_PWORK_STOP, 0);
803 add_dyn_dbg("debug_lo", B43_DBG_LO, 0);
804 add_dyn_dbg("debug_firmware", B43_DBG_FIRMWARE, 0);
526 805
527#undef add_dyn_dbg 806#undef add_dyn_dbg
528} 807}
@@ -569,6 +848,13 @@ void b43_debugfs_add_device(struct b43_wldev *dev)
569 return; 848 return;
570 } 849 }
571 850
851 e->mmio16read_next = 0xFFFF; /* invalid address */
852 e->mmio32read_next = 0xFFFF; /* invalid address */
853 e->shm16read_routing_next = 0xFFFFFFFF; /* invalid routing */
854 e->shm16read_addr_next = 0xFFFFFFFF; /* invalid address */
855 e->shm32read_routing_next = 0xFFFFFFFF; /* invalid routing */
856 e->shm32read_addr_next = 0xFFFFFFFF; /* invalid address */
857
572#define ADD_FILE(name, mode) \ 858#define ADD_FILE(name, mode) \
573 do { \ 859 do { \
574 struct dentry *d; \ 860 struct dentry *d; \
@@ -581,9 +867,15 @@ void b43_debugfs_add_device(struct b43_wldev *dev)
581 } while (0) 867 } while (0)
582 868
583 869
870 ADD_FILE(shm16read, 0600);
871 ADD_FILE(shm16write, 0200);
872 ADD_FILE(shm32read, 0600);
873 ADD_FILE(shm32write, 0200);
874 ADD_FILE(mmio16read, 0600);
875 ADD_FILE(mmio16write, 0200);
876 ADD_FILE(mmio32read, 0600);
877 ADD_FILE(mmio32write, 0200);
584 ADD_FILE(tsf, 0600); 878 ADD_FILE(tsf, 0600);
585 ADD_FILE(ucode_regs, 0400);
586 ADD_FILE(shm, 0400);
587 ADD_FILE(txstat, 0400); 879 ADD_FILE(txstat, 0400);
588 ADD_FILE(txpower_g, 0600); 880 ADD_FILE(txpower_g, 0600);
589 ADD_FILE(restart, 0200); 881 ADD_FILE(restart, 0200);
@@ -605,9 +897,15 @@ void b43_debugfs_remove_device(struct b43_wldev *dev)
605 return; 897 return;
606 b43_remove_dynamic_debug(dev); 898 b43_remove_dynamic_debug(dev);
607 899
900 debugfs_remove(e->file_shm16read.dentry);
901 debugfs_remove(e->file_shm16write.dentry);
902 debugfs_remove(e->file_shm32read.dentry);
903 debugfs_remove(e->file_shm32write.dentry);
904 debugfs_remove(e->file_mmio16read.dentry);
905 debugfs_remove(e->file_mmio16write.dentry);
906 debugfs_remove(e->file_mmio32read.dentry);
907 debugfs_remove(e->file_mmio32write.dentry);
608 debugfs_remove(e->file_tsf.dentry); 908 debugfs_remove(e->file_tsf.dentry);
609 debugfs_remove(e->file_ucode_regs.dentry);
610 debugfs_remove(e->file_shm.dentry);
611 debugfs_remove(e->file_txstat.dentry); 909 debugfs_remove(e->file_txstat.dentry);
612 debugfs_remove(e->file_txpower_g.dentry); 910 debugfs_remove(e->file_txpower_g.dentry);
613 debugfs_remove(e->file_restart.dentry); 911 debugfs_remove(e->file_restart.dentry);
diff --git a/drivers/net/wireless/b43/debugfs.h b/drivers/net/wireless/b43/debugfs.h
index 6eebe858db5a..22ffd02ba554 100644
--- a/drivers/net/wireless/b43/debugfs.h
+++ b/drivers/net/wireless/b43/debugfs.h
@@ -10,6 +10,8 @@ enum b43_dyndbg { /* Dynamic debugging features */
10 B43_DBG_DMAVERBOSE, 10 B43_DBG_DMAVERBOSE,
11 B43_DBG_PWORK_FAST, 11 B43_DBG_PWORK_FAST,
12 B43_DBG_PWORK_STOP, 12 B43_DBG_PWORK_STOP,
13 B43_DBG_LO,
14 B43_DBG_FIRMWARE,
13 __B43_NR_DYNDBG, 15 __B43_NR_DYNDBG,
14}; 16};
15 17
@@ -35,9 +37,15 @@ struct b43_dfsentry {
35 struct b43_wldev *dev; 37 struct b43_wldev *dev;
36 struct dentry *subdir; 38 struct dentry *subdir;
37 39
40 struct b43_dfs_file file_shm16read;
41 struct b43_dfs_file file_shm16write;
42 struct b43_dfs_file file_shm32read;
43 struct b43_dfs_file file_shm32write;
44 struct b43_dfs_file file_mmio16read;
45 struct b43_dfs_file file_mmio16write;
46 struct b43_dfs_file file_mmio32read;
47 struct b43_dfs_file file_mmio32write;
38 struct b43_dfs_file file_tsf; 48 struct b43_dfs_file file_tsf;
39 struct b43_dfs_file file_ucode_regs;
40 struct b43_dfs_file file_shm;
41 struct b43_dfs_file file_txstat; 49 struct b43_dfs_file file_txstat;
42 struct b43_dfs_file file_txpower_g; 50 struct b43_dfs_file file_txpower_g;
43 struct b43_dfs_file file_restart; 51 struct b43_dfs_file file_restart;
@@ -45,6 +53,18 @@ struct b43_dfsentry {
45 53
46 struct b43_txstatus_log txstatlog; 54 struct b43_txstatus_log txstatlog;
47 55
56 /* The cached address for the next mmio16read file read */
57 u16 mmio16read_next;
58 /* The cached address for the next mmio32read file read */
59 u16 mmio32read_next;
60
61 /* The cached address for the next shm16read file read */
62 u32 shm16read_routing_next;
63 u32 shm16read_addr_next;
64 /* The cached address for the next shm32read file read */
65 u32 shm32read_routing_next;
66 u32 shm32read_addr_next;
67
48 /* Enabled/Disabled list for the dynamic debugging features. */ 68 /* Enabled/Disabled list for the dynamic debugging features. */
49 u32 dyn_debug[__B43_NR_DYNDBG]; 69 u32 dyn_debug[__B43_NR_DYNDBG];
50 /* Dentries for the dynamic debugging entries. */ 70 /* Dentries for the dynamic debugging entries. */
diff --git a/drivers/net/wireless/b43/dma.c b/drivers/net/wireless/b43/dma.c
index e23f2f172bd7..098f886976f6 100644
--- a/drivers/net/wireless/b43/dma.c
+++ b/drivers/net/wireless/b43/dma.c
@@ -328,11 +328,11 @@ static inline
328 dma_addr_t dmaaddr; 328 dma_addr_t dmaaddr;
329 329
330 if (tx) { 330 if (tx) {
331 dmaaddr = dma_map_single(ring->dev->dev->dma_dev, 331 dmaaddr = ssb_dma_map_single(ring->dev->dev,
332 buf, len, DMA_TO_DEVICE); 332 buf, len, DMA_TO_DEVICE);
333 } else { 333 } else {
334 dmaaddr = dma_map_single(ring->dev->dev->dma_dev, 334 dmaaddr = ssb_dma_map_single(ring->dev->dev,
335 buf, len, DMA_FROM_DEVICE); 335 buf, len, DMA_FROM_DEVICE);
336 } 336 }
337 337
338 return dmaaddr; 338 return dmaaddr;
@@ -343,11 +343,11 @@ static inline
343 dma_addr_t addr, size_t len, int tx) 343 dma_addr_t addr, size_t len, int tx)
344{ 344{
345 if (tx) { 345 if (tx) {
346 dma_unmap_single(ring->dev->dev->dma_dev, 346 ssb_dma_unmap_single(ring->dev->dev,
347 addr, len, DMA_TO_DEVICE); 347 addr, len, DMA_TO_DEVICE);
348 } else { 348 } else {
349 dma_unmap_single(ring->dev->dev->dma_dev, 349 ssb_dma_unmap_single(ring->dev->dev,
350 addr, len, DMA_FROM_DEVICE); 350 addr, len, DMA_FROM_DEVICE);
351 } 351 }
352} 352}
353 353
@@ -356,8 +356,8 @@ static inline
356 dma_addr_t addr, size_t len) 356 dma_addr_t addr, size_t len)
357{ 357{
358 B43_WARN_ON(ring->tx); 358 B43_WARN_ON(ring->tx);
359 dma_sync_single_for_cpu(ring->dev->dev->dma_dev, 359 ssb_dma_sync_single_for_cpu(ring->dev->dev,
360 addr, len, DMA_FROM_DEVICE); 360 addr, len, DMA_FROM_DEVICE);
361} 361}
362 362
363static inline 363static inline
@@ -365,8 +365,8 @@ static inline
365 dma_addr_t addr, size_t len) 365 dma_addr_t addr, size_t len)
366{ 366{
367 B43_WARN_ON(ring->tx); 367 B43_WARN_ON(ring->tx);
368 dma_sync_single_for_device(ring->dev->dev->dma_dev, 368 ssb_dma_sync_single_for_device(ring->dev->dev,
369 addr, len, DMA_FROM_DEVICE); 369 addr, len, DMA_FROM_DEVICE);
370} 370}
371 371
372static inline 372static inline
@@ -381,7 +381,6 @@ static inline
381 381
382static int alloc_ringmemory(struct b43_dmaring *ring) 382static int alloc_ringmemory(struct b43_dmaring *ring)
383{ 383{
384 struct device *dma_dev = ring->dev->dev->dma_dev;
385 gfp_t flags = GFP_KERNEL; 384 gfp_t flags = GFP_KERNEL;
386 385
387 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K 386 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
@@ -392,11 +391,14 @@ static int alloc_ringmemory(struct b43_dmaring *ring)
392 * For unknown reasons - possibly a hardware error - the BCM4311 rev 391 * For unknown reasons - possibly a hardware error - the BCM4311 rev
393 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory, 392 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
394 * which accounts for the GFP_DMA flag below. 393 * which accounts for the GFP_DMA flag below.
394 *
395 * The flags here must match the flags in free_ringmemory below!
395 */ 396 */
396 if (ring->type == B43_DMA_64BIT) 397 if (ring->type == B43_DMA_64BIT)
397 flags |= GFP_DMA; 398 flags |= GFP_DMA;
398 ring->descbase = dma_alloc_coherent(dma_dev, B43_DMA_RINGMEMSIZE, 399 ring->descbase = ssb_dma_alloc_consistent(ring->dev->dev,
399 &(ring->dmabase), flags); 400 B43_DMA_RINGMEMSIZE,
401 &(ring->dmabase), flags);
400 if (!ring->descbase) { 402 if (!ring->descbase) {
401 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n"); 403 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
402 return -ENOMEM; 404 return -ENOMEM;
@@ -408,10 +410,13 @@ static int alloc_ringmemory(struct b43_dmaring *ring)
408 410
409static void free_ringmemory(struct b43_dmaring *ring) 411static void free_ringmemory(struct b43_dmaring *ring)
410{ 412{
411 struct device *dma_dev = ring->dev->dev->dma_dev; 413 gfp_t flags = GFP_KERNEL;
414
415 if (ring->type == B43_DMA_64BIT)
416 flags |= GFP_DMA;
412 417
413 dma_free_coherent(dma_dev, B43_DMA_RINGMEMSIZE, 418 ssb_dma_free_consistent(ring->dev->dev, B43_DMA_RINGMEMSIZE,
414 ring->descbase, ring->dmabase); 419 ring->descbase, ring->dmabase, flags);
415} 420}
416 421
417/* Reset the RX DMA channel */ 422/* Reset the RX DMA channel */
@@ -518,7 +523,7 @@ static bool b43_dma_mapping_error(struct b43_dmaring *ring,
518 dma_addr_t addr, 523 dma_addr_t addr,
519 size_t buffersize, bool dma_to_device) 524 size_t buffersize, bool dma_to_device)
520{ 525{
521 if (unlikely(dma_mapping_error(addr))) 526 if (unlikely(ssb_dma_mapping_error(ring->dev->dev, addr)))
522 return 1; 527 return 1;
523 528
524 switch (ring->type) { 529 switch (ring->type) {
@@ -844,10 +849,10 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
844 goto err_kfree_meta; 849 goto err_kfree_meta;
845 850
846 /* test for ability to dma to txhdr_cache */ 851 /* test for ability to dma to txhdr_cache */
847 dma_test = dma_map_single(dev->dev->dma_dev, 852 dma_test = ssb_dma_map_single(dev->dev,
848 ring->txhdr_cache, 853 ring->txhdr_cache,
849 b43_txhdr_size(dev), 854 b43_txhdr_size(dev),
850 DMA_TO_DEVICE); 855 DMA_TO_DEVICE);
851 856
852 if (b43_dma_mapping_error(ring, dma_test, 857 if (b43_dma_mapping_error(ring, dma_test,
853 b43_txhdr_size(dev), 1)) { 858 b43_txhdr_size(dev), 1)) {
@@ -859,10 +864,10 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
859 if (!ring->txhdr_cache) 864 if (!ring->txhdr_cache)
860 goto err_kfree_meta; 865 goto err_kfree_meta;
861 866
862 dma_test = dma_map_single(dev->dev->dma_dev, 867 dma_test = ssb_dma_map_single(dev->dev,
863 ring->txhdr_cache, 868 ring->txhdr_cache,
864 b43_txhdr_size(dev), 869 b43_txhdr_size(dev),
865 DMA_TO_DEVICE); 870 DMA_TO_DEVICE);
866 871
867 if (b43_dma_mapping_error(ring, dma_test, 872 if (b43_dma_mapping_error(ring, dma_test,
868 b43_txhdr_size(dev), 1)) { 873 b43_txhdr_size(dev), 1)) {
@@ -873,9 +878,9 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
873 } 878 }
874 } 879 }
875 880
876 dma_unmap_single(dev->dev->dma_dev, 881 ssb_dma_unmap_single(dev->dev,
877 dma_test, b43_txhdr_size(dev), 882 dma_test, b43_txhdr_size(dev),
878 DMA_TO_DEVICE); 883 DMA_TO_DEVICE);
879 } 884 }
880 885
881 err = alloc_ringmemory(ring); 886 err = alloc_ringmemory(ring);
@@ -1130,10 +1135,10 @@ struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1130} 1135}
1131 1136
1132static int dma_tx_fragment(struct b43_dmaring *ring, 1137static int dma_tx_fragment(struct b43_dmaring *ring,
1133 struct sk_buff *skb, 1138 struct sk_buff *skb)
1134 struct ieee80211_tx_control *ctl)
1135{ 1139{
1136 const struct b43_dma_ops *ops = ring->ops; 1140 const struct b43_dma_ops *ops = ring->ops;
1141 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1137 u8 *header; 1142 u8 *header;
1138 int slot, old_top_slot, old_used_slots; 1143 int slot, old_top_slot, old_used_slots;
1139 int err; 1144 int err;
@@ -1157,7 +1162,7 @@ static int dma_tx_fragment(struct b43_dmaring *ring,
1157 header = &(ring->txhdr_cache[slot * hdrsize]); 1162 header = &(ring->txhdr_cache[slot * hdrsize]);
1158 cookie = generate_cookie(ring, slot); 1163 cookie = generate_cookie(ring, slot);
1159 err = b43_generate_txhdr(ring->dev, header, 1164 err = b43_generate_txhdr(ring->dev, header,
1160 skb->data, skb->len, ctl, cookie); 1165 skb->data, skb->len, info, cookie);
1161 if (unlikely(err)) { 1166 if (unlikely(err)) {
1162 ring->current_slot = old_top_slot; 1167 ring->current_slot = old_top_slot;
1163 ring->used_slots = old_used_slots; 1168 ring->used_slots = old_used_slots;
@@ -1179,7 +1184,6 @@ static int dma_tx_fragment(struct b43_dmaring *ring,
1179 desc = ops->idx2desc(ring, slot, &meta); 1184 desc = ops->idx2desc(ring, slot, &meta);
1180 memset(meta, 0, sizeof(*meta)); 1185 memset(meta, 0, sizeof(*meta));
1181 1186
1182 memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
1183 meta->skb = skb; 1187 meta->skb = skb;
1184 meta->is_last_fragment = 1; 1188 meta->is_last_fragment = 1;
1185 1189
@@ -1209,7 +1213,7 @@ static int dma_tx_fragment(struct b43_dmaring *ring,
1209 1213
1210 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1); 1214 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1211 1215
1212 if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) { 1216 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1213 /* Tell the firmware about the cookie of the last 1217 /* Tell the firmware about the cookie of the last
1214 * mcast frame, so it can clear the more-data bit in it. */ 1218 * mcast frame, so it can clear the more-data bit in it. */
1215 b43_shm_write16(ring->dev, B43_SHM_SHARED, 1219 b43_shm_write16(ring->dev, B43_SHM_SHARED,
@@ -1280,16 +1284,16 @@ static struct b43_dmaring * select_ring_by_priority(struct b43_wldev *dev,
1280 return ring; 1284 return ring;
1281} 1285}
1282 1286
1283int b43_dma_tx(struct b43_wldev *dev, 1287int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
1284 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
1285{ 1288{
1286 struct b43_dmaring *ring; 1289 struct b43_dmaring *ring;
1287 struct ieee80211_hdr *hdr; 1290 struct ieee80211_hdr *hdr;
1288 int err = 0; 1291 int err = 0;
1289 unsigned long flags; 1292 unsigned long flags;
1293 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1290 1294
1291 hdr = (struct ieee80211_hdr *)skb->data; 1295 hdr = (struct ieee80211_hdr *)skb->data;
1292 if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) { 1296 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1293 /* The multicast ring will be sent after the DTIM */ 1297 /* The multicast ring will be sent after the DTIM */
1294 ring = dev->dma.tx_ring_mcast; 1298 ring = dev->dma.tx_ring_mcast;
1295 /* Set the more-data bit. Ucode will clear it on 1299 /* Set the more-data bit. Ucode will clear it on
@@ -1297,7 +1301,8 @@ int b43_dma_tx(struct b43_wldev *dev,
1297 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA); 1301 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1298 } else { 1302 } else {
1299 /* Decide by priority where to put this frame. */ 1303 /* Decide by priority where to put this frame. */
1300 ring = select_ring_by_priority(dev, ctl->queue); 1304 ring = select_ring_by_priority(
1305 dev, skb_get_queue_mapping(skb));
1301 } 1306 }
1302 1307
1303 spin_lock_irqsave(&ring->lock, flags); 1308 spin_lock_irqsave(&ring->lock, flags);
@@ -1315,9 +1320,9 @@ int b43_dma_tx(struct b43_wldev *dev,
1315 /* Assign the queue number to the ring (if not already done before) 1320 /* Assign the queue number to the ring (if not already done before)
1316 * so TX status handling can use it. The queue to ring mapping is 1321 * so TX status handling can use it. The queue to ring mapping is
1317 * static, so we don't need to store it per frame. */ 1322 * static, so we don't need to store it per frame. */
1318 ring->queue_prio = ctl->queue; 1323 ring->queue_prio = skb_get_queue_mapping(skb);
1319 1324
1320 err = dma_tx_fragment(ring, skb, ctl); 1325 err = dma_tx_fragment(ring, skb);
1321 if (unlikely(err == -ENOKEY)) { 1326 if (unlikely(err == -ENOKEY)) {
1322 /* Drop this packet, as we don't have the encryption key 1327 /* Drop this packet, as we don't have the encryption key
1323 * anymore and must not transmit it unencrypted. */ 1328 * anymore and must not transmit it unencrypted. */
@@ -1333,7 +1338,7 @@ int b43_dma_tx(struct b43_wldev *dev,
1333 if ((free_slots(ring) < SLOTS_PER_PACKET) || 1338 if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1334 should_inject_overflow(ring)) { 1339 should_inject_overflow(ring)) {
1335 /* This TX ring is full. */ 1340 /* This TX ring is full. */
1336 ieee80211_stop_queue(dev->wl->hw, ctl->queue); 1341 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
1337 ring->stopped = 1; 1342 ring->stopped = 1;
1338 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) { 1343 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1339 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index); 1344 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
@@ -1376,13 +1381,19 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
1376 b43_txhdr_size(dev), 1); 1381 b43_txhdr_size(dev), 1);
1377 1382
1378 if (meta->is_last_fragment) { 1383 if (meta->is_last_fragment) {
1379 B43_WARN_ON(!meta->skb); 1384 struct ieee80211_tx_info *info;
1380 /* Call back to inform the ieee80211 subsystem about the 1385
1381 * status of the transmission. 1386 BUG_ON(!meta->skb);
1382 * Some fields of txstat are already filled in dma_tx(). 1387
1388 info = IEEE80211_SKB_CB(meta->skb);
1389
1390 memset(&info->status, 0, sizeof(info->status));
1391
1392 /*
1393 * Call back to inform the ieee80211 subsystem about
1394 * the status of the transmission.
1383 */ 1395 */
1384 frame_succeed = b43_fill_txstatus_report( 1396 frame_succeed = b43_fill_txstatus_report(info, status);
1385 &(meta->txstat), status);
1386#ifdef CONFIG_B43_DEBUG 1397#ifdef CONFIG_B43_DEBUG
1387 if (frame_succeed) 1398 if (frame_succeed)
1388 ring->nr_succeed_tx_packets++; 1399 ring->nr_succeed_tx_packets++;
@@ -1390,8 +1401,8 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
1390 ring->nr_failed_tx_packets++; 1401 ring->nr_failed_tx_packets++;
1391 ring->nr_total_packet_tries += status->frame_count; 1402 ring->nr_total_packet_tries += status->frame_count;
1392#endif /* DEBUG */ 1403#endif /* DEBUG */
1393 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb, 1404 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
1394 &(meta->txstat)); 1405
1395 /* skb is freed by ieee80211_tx_status_irqsafe() */ 1406 /* skb is freed by ieee80211_tx_status_irqsafe() */
1396 meta->skb = NULL; 1407 meta->skb = NULL;
1397 } else { 1408 } else {
@@ -1426,18 +1437,16 @@ void b43_dma_get_tx_stats(struct b43_wldev *dev,
1426{ 1437{
1427 const int nr_queues = dev->wl->hw->queues; 1438 const int nr_queues = dev->wl->hw->queues;
1428 struct b43_dmaring *ring; 1439 struct b43_dmaring *ring;
1429 struct ieee80211_tx_queue_stats_data *data;
1430 unsigned long flags; 1440 unsigned long flags;
1431 int i; 1441 int i;
1432 1442
1433 for (i = 0; i < nr_queues; i++) { 1443 for (i = 0; i < nr_queues; i++) {
1434 data = &(stats->data[i]);
1435 ring = select_ring_by_priority(dev, i); 1444 ring = select_ring_by_priority(dev, i);
1436 1445
1437 spin_lock_irqsave(&ring->lock, flags); 1446 spin_lock_irqsave(&ring->lock, flags);
1438 data->len = ring->used_slots / SLOTS_PER_PACKET; 1447 stats[i].len = ring->used_slots / SLOTS_PER_PACKET;
1439 data->limit = ring->nr_slots / SLOTS_PER_PACKET; 1448 stats[i].limit = ring->nr_slots / SLOTS_PER_PACKET;
1440 data->count = ring->nr_tx_packets; 1449 stats[i].count = ring->nr_tx_packets;
1441 spin_unlock_irqrestore(&ring->lock, flags); 1450 spin_unlock_irqrestore(&ring->lock, flags);
1442 } 1451 }
1443} 1452}
diff --git a/drivers/net/wireless/b43/dma.h b/drivers/net/wireless/b43/dma.h
index 20acf885dba5..d1eb5c0848a5 100644
--- a/drivers/net/wireless/b43/dma.h
+++ b/drivers/net/wireless/b43/dma.h
@@ -181,7 +181,6 @@ struct b43_dmadesc_meta {
181 dma_addr_t dmaaddr; 181 dma_addr_t dmaaddr;
182 /* ieee80211 TX status. Only used once per 802.11 frag. */ 182 /* ieee80211 TX status. Only used once per 802.11 frag. */
183 bool is_last_fragment; 183 bool is_last_fragment;
184 struct ieee80211_tx_status txstat;
185}; 184};
186 185
187struct b43_dmaring; 186struct b43_dmaring;
@@ -285,7 +284,7 @@ void b43_dma_get_tx_stats(struct b43_wldev *dev,
285 struct ieee80211_tx_queue_stats *stats); 284 struct ieee80211_tx_queue_stats *stats);
286 285
287int b43_dma_tx(struct b43_wldev *dev, 286int b43_dma_tx(struct b43_wldev *dev,
288 struct sk_buff *skb, struct ieee80211_tx_control *ctl); 287 struct sk_buff *skb);
289void b43_dma_handle_txstatus(struct b43_wldev *dev, 288void b43_dma_handle_txstatus(struct b43_wldev *dev,
290 const struct b43_txstatus *status); 289 const struct b43_txstatus *status);
291 290
diff --git a/drivers/net/wireless/b43/lo.c b/drivers/net/wireless/b43/lo.c
index d890f366a23b..9c854d6aae36 100644
--- a/drivers/net/wireless/b43/lo.c
+++ b/drivers/net/wireless/b43/lo.c
@@ -36,17 +36,28 @@
36#include <linux/sched.h> 36#include <linux/sched.h>
37 37
38 38
39/* Define to 1 to always calibrate all possible LO control pairs. 39static struct b43_lo_calib * b43_find_lo_calib(struct b43_txpower_lo_control *lo,
40 * This is a workaround until we fix the partial LO calibration optimization. */ 40 const struct b43_bbatt *bbatt,
41#define B43_CALIB_ALL_LOCTLS 1 41 const struct b43_rfatt *rfatt)
42{
43 struct b43_lo_calib *c;
44
45 list_for_each_entry(c, &lo->calib_list, list) {
46 if (!b43_compare_bbatt(&c->bbatt, bbatt))
47 continue;
48 if (!b43_compare_rfatt(&c->rfatt, rfatt))
49 continue;
50 return c;
51 }
42 52
53 return NULL;
54}
43 55
44/* Write the LocalOscillator Control (adjust) value-pair. */ 56/* Write the LocalOscillator Control (adjust) value-pair. */
45static void b43_lo_write(struct b43_wldev *dev, struct b43_loctl *control) 57static void b43_lo_write(struct b43_wldev *dev, struct b43_loctl *control)
46{ 58{
47 struct b43_phy *phy = &dev->phy; 59 struct b43_phy *phy = &dev->phy;
48 u16 value; 60 u16 value;
49 u16 reg;
50 61
51 if (B43_DEBUG) { 62 if (B43_DEBUG) {
52 if (unlikely(abs(control->i) > 16 || abs(control->q) > 16)) { 63 if (unlikely(abs(control->i) > 16 || abs(control->q) > 16)) {
@@ -56,189 +67,11 @@ static void b43_lo_write(struct b43_wldev *dev, struct b43_loctl *control)
56 return; 67 return;
57 } 68 }
58 } 69 }
70 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
59 71
60 value = (u8) (control->q); 72 value = (u8) (control->q);
61 value |= ((u8) (control->i)) << 8; 73 value |= ((u8) (control->i)) << 8;
62 74 b43_phy_write(dev, B43_PHY_LO_CTL, value);
63 reg = (phy->type == B43_PHYTYPE_B) ? 0x002F : B43_PHY_LO_CTL;
64 b43_phy_write(dev, reg, value);
65}
66
67static int assert_rfatt_and_bbatt(const struct b43_rfatt *rfatt,
68 const struct b43_bbatt *bbatt,
69 struct b43_wldev *dev)
70{
71 int err = 0;
72
73 /* Check the attenuation values against the LO control array sizes. */
74 if (unlikely(rfatt->att >= B43_NR_RF)) {
75 b43err(dev->wl, "rfatt(%u) >= size of LO array\n", rfatt->att);
76 err = -EINVAL;
77 }
78 if (unlikely(bbatt->att >= B43_NR_BB)) {
79 b43err(dev->wl, "bbatt(%u) >= size of LO array\n", bbatt->att);
80 err = -EINVAL;
81 }
82
83 return err;
84}
85
86#if !B43_CALIB_ALL_LOCTLS
87static
88struct b43_loctl *b43_get_lo_g_ctl_nopadmix(struct b43_wldev *dev,
89 const struct b43_rfatt *rfatt,
90 const struct b43_bbatt *bbatt)
91{
92 struct b43_phy *phy = &dev->phy;
93 struct b43_txpower_lo_control *lo = phy->lo_control;
94
95 if (assert_rfatt_and_bbatt(rfatt, bbatt, dev))
96 return &(lo->no_padmix[0][0]); /* Just prevent a crash */
97 return &(lo->no_padmix[bbatt->att][rfatt->att]);
98}
99#endif /* !B43_CALIB_ALL_LOCTLS */
100
101struct b43_loctl *b43_get_lo_g_ctl(struct b43_wldev *dev,
102 const struct b43_rfatt *rfatt,
103 const struct b43_bbatt *bbatt)
104{
105 struct b43_phy *phy = &dev->phy;
106 struct b43_txpower_lo_control *lo = phy->lo_control;
107
108 if (assert_rfatt_and_bbatt(rfatt, bbatt, dev))
109 return &(lo->no_padmix[0][0]); /* Just prevent a crash */
110 if (rfatt->with_padmix)
111 return &(lo->with_padmix[bbatt->att][rfatt->att]);
112 return &(lo->no_padmix[bbatt->att][rfatt->att]);
113}
114
115/* Call a function for every possible LO control value-pair. */
116static void b43_call_for_each_loctl(struct b43_wldev *dev,
117 void (*func) (struct b43_wldev *,
118 struct b43_loctl *))
119{
120 struct b43_phy *phy = &dev->phy;
121 struct b43_txpower_lo_control *ctl = phy->lo_control;
122 int i, j;
123
124 for (i = 0; i < B43_NR_BB; i++) {
125 for (j = 0; j < B43_NR_RF; j++)
126 func(dev, &(ctl->with_padmix[i][j]));
127 }
128 for (i = 0; i < B43_NR_BB; i++) {
129 for (j = 0; j < B43_NR_RF; j++)
130 func(dev, &(ctl->no_padmix[i][j]));
131 }
132}
133
134static u16 lo_b_r15_loop(struct b43_wldev *dev)
135{
136 int i;
137 u16 ret = 0;
138
139 for (i = 0; i < 10; i++) {
140 b43_phy_write(dev, 0x0015, 0xAFA0);
141 udelay(1);
142 b43_phy_write(dev, 0x0015, 0xEFA0);
143 udelay(10);
144 b43_phy_write(dev, 0x0015, 0xFFA0);
145 udelay(40);
146 ret += b43_phy_read(dev, 0x002C);
147 }
148
149 return ret;
150}
151
152void b43_lo_b_measure(struct b43_wldev *dev)
153{
154 struct b43_phy *phy = &dev->phy;
155 u16 regstack[12] = { 0 };
156 u16 mls;
157 u16 fval;
158 int i, j;
159
160 regstack[0] = b43_phy_read(dev, 0x0015);
161 regstack[1] = b43_radio_read16(dev, 0x0052) & 0xFFF0;
162
163 if (phy->radio_ver == 0x2053) {
164 regstack[2] = b43_phy_read(dev, 0x000A);
165 regstack[3] = b43_phy_read(dev, 0x002A);
166 regstack[4] = b43_phy_read(dev, 0x0035);
167 regstack[5] = b43_phy_read(dev, 0x0003);
168 regstack[6] = b43_phy_read(dev, 0x0001);
169 regstack[7] = b43_phy_read(dev, 0x0030);
170
171 regstack[8] = b43_radio_read16(dev, 0x0043);
172 regstack[9] = b43_radio_read16(dev, 0x007A);
173 regstack[10] = b43_read16(dev, 0x03EC);
174 regstack[11] = b43_radio_read16(dev, 0x0052) & 0x00F0;
175
176 b43_phy_write(dev, 0x0030, 0x00FF);
177 b43_write16(dev, 0x03EC, 0x3F3F);
178 b43_phy_write(dev, 0x0035, regstack[4] & 0xFF7F);
179 b43_radio_write16(dev, 0x007A, regstack[9] & 0xFFF0);
180 }
181 b43_phy_write(dev, 0x0015, 0xB000);
182 b43_phy_write(dev, 0x002B, 0x0004);
183
184 if (phy->radio_ver == 0x2053) {
185 b43_phy_write(dev, 0x002B, 0x0203);
186 b43_phy_write(dev, 0x002A, 0x08A3);
187 }
188
189 phy->minlowsig[0] = 0xFFFF;
190
191 for (i = 0; i < 4; i++) {
192 b43_radio_write16(dev, 0x0052, regstack[1] | i);
193 lo_b_r15_loop(dev);
194 }
195 for (i = 0; i < 10; i++) {
196 b43_radio_write16(dev, 0x0052, regstack[1] | i);
197 mls = lo_b_r15_loop(dev) / 10;
198 if (mls < phy->minlowsig[0]) {
199 phy->minlowsig[0] = mls;
200 phy->minlowsigpos[0] = i;
201 }
202 }
203 b43_radio_write16(dev, 0x0052, regstack[1] | phy->minlowsigpos[0]);
204
205 phy->minlowsig[1] = 0xFFFF;
206
207 for (i = -4; i < 5; i += 2) {
208 for (j = -4; j < 5; j += 2) {
209 if (j < 0)
210 fval = (0x0100 * i) + j + 0x0100;
211 else
212 fval = (0x0100 * i) + j;
213 b43_phy_write(dev, 0x002F, fval);
214 mls = lo_b_r15_loop(dev) / 10;
215 if (mls < phy->minlowsig[1]) {
216 phy->minlowsig[1] = mls;
217 phy->minlowsigpos[1] = fval;
218 }
219 }
220 }
221 phy->minlowsigpos[1] += 0x0101;
222
223 b43_phy_write(dev, 0x002F, phy->minlowsigpos[1]);
224 if (phy->radio_ver == 0x2053) {
225 b43_phy_write(dev, 0x000A, regstack[2]);
226 b43_phy_write(dev, 0x002A, regstack[3]);
227 b43_phy_write(dev, 0x0035, regstack[4]);
228 b43_phy_write(dev, 0x0003, regstack[5]);
229 b43_phy_write(dev, 0x0001, regstack[6]);
230 b43_phy_write(dev, 0x0030, regstack[7]);
231
232 b43_radio_write16(dev, 0x0043, regstack[8]);
233 b43_radio_write16(dev, 0x007A, regstack[9]);
234
235 b43_radio_write16(dev, 0x0052,
236 (b43_radio_read16(dev, 0x0052) & 0x000F)
237 | regstack[11]);
238
239 b43_write16(dev, 0x03EC, regstack[10]);
240 }
241 b43_phy_write(dev, 0x0015, regstack[0]);
242} 75}
243 76
244static u16 lo_measure_feedthrough(struct b43_wldev *dev, 77static u16 lo_measure_feedthrough(struct b43_wldev *dev,
@@ -366,7 +199,7 @@ static void lo_measure_txctl_values(struct b43_wldev *dev)
366 if (lb_gain > 10) { 199 if (lb_gain > 10) {
367 radio_pctl_reg = 0; 200 radio_pctl_reg = 0;
368 pga = abs(10 - lb_gain) / 6; 201 pga = abs(10 - lb_gain) / 6;
369 pga = limit_value(pga, 0, 15); 202 pga = clamp_val(pga, 0, 15);
370 } else { 203 } else {
371 int cmp_val; 204 int cmp_val;
372 int tmp; 205 int tmp;
@@ -438,48 +271,26 @@ static void lo_measure_txctl_values(struct b43_wldev *dev)
438 b43_radio_write16(dev, 0x52, b43_radio_read16(dev, 0x52) 271 b43_radio_write16(dev, 0x52, b43_radio_read16(dev, 0x52)
439 & 0xFFF0); /* TX bias == 0 */ 272 & 0xFFF0); /* TX bias == 0 */
440 } 273 }
274 lo->txctl_measured_time = jiffies;
441} 275}
442 276
443static void lo_read_power_vector(struct b43_wldev *dev) 277static void lo_read_power_vector(struct b43_wldev *dev)
444{ 278{
445 struct b43_phy *phy = &dev->phy; 279 struct b43_phy *phy = &dev->phy;
446 struct b43_txpower_lo_control *lo = phy->lo_control; 280 struct b43_txpower_lo_control *lo = phy->lo_control;
447 u16 i; 281 int i;
448 u64 tmp; 282 u64 tmp;
449 u64 power_vector = 0; 283 u64 power_vector = 0;
450 int rf_offset, bb_offset;
451 struct b43_loctl *loctl;
452 284
453 for (i = 0; i < 8; i += 2) { 285 for (i = 0; i < 8; i += 2) {
454 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x310 + i); 286 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x310 + i);
455 /* Clear the top byte. We get holes in the bitmap... */
456 tmp &= 0xFF;
457 power_vector |= (tmp << (i * 8)); 287 power_vector |= (tmp << (i * 8));
458 /* Clear the vector on the device. */ 288 /* Clear the vector on the device. */
459 b43_shm_write16(dev, B43_SHM_SHARED, 0x310 + i, 0); 289 b43_shm_write16(dev, B43_SHM_SHARED, 0x310 + i, 0);
460 } 290 }
461
462 if (power_vector) 291 if (power_vector)
463 lo->power_vector = power_vector; 292 lo->power_vector = power_vector;
464 power_vector = lo->power_vector; 293 lo->pwr_vec_read_time = jiffies;
465
466 for (i = 0; i < 64; i++) {
467 if (power_vector & ((u64) 1ULL << i)) {
468 /* Now figure out which b43_loctl corresponds
469 * to this bit.
470 */
471 rf_offset = i / lo->rfatt_list.len;
472 bb_offset = i % lo->rfatt_list.len; //FIXME?
473 loctl =
474 b43_get_lo_g_ctl(dev,
475 &lo->rfatt_list.list[rf_offset],
476 &lo->bbatt_list.list[bb_offset]);
477 /* And mark it as "used", as the device told us
478 * through the bitmap it is using it.
479 */
480 loctl->used = 1;
481 }
482 }
483} 294}
484 295
485/* 802.11/LO/GPHY/MeasuringGains */ 296/* 802.11/LO/GPHY/MeasuringGains */
@@ -510,7 +321,7 @@ static void lo_measure_gain_values(struct b43_wldev *dev,
510 phy->lna_lod_gain = 1; 321 phy->lna_lod_gain = 1;
511 trsw_rx_gain -= 8; 322 trsw_rx_gain -= 8;
512 } 323 }
513 trsw_rx_gain = limit_value(trsw_rx_gain, 0, 0x2D); 324 trsw_rx_gain = clamp_val(trsw_rx_gain, 0, 0x2D);
514 phy->pga_gain = trsw_rx_gain / 3; 325 phy->pga_gain = trsw_rx_gain / 3;
515 if (phy->pga_gain >= 5) { 326 if (phy->pga_gain >= 5) {
516 phy->pga_gain -= 5; 327 phy->pga_gain -= 5;
@@ -609,8 +420,6 @@ static void lo_measure_setup(struct b43_wldev *dev,
609 b43_phy_write(dev, B43_PHY_CCK(0x16), 0x410); 420 b43_phy_write(dev, B43_PHY_CCK(0x16), 0x410);
610 b43_phy_write(dev, B43_PHY_CCK(0x17), 0x820); 421 b43_phy_write(dev, B43_PHY_CCK(0x17), 0x820);
611 } 422 }
612 if (!lo->rebuild && b43_has_hardware_pctl(phy))
613 lo_read_power_vector(dev);
614 if (phy->rev >= 2) { 423 if (phy->rev >= 2) {
615 sav->phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER); 424 sav->phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
616 sav->phy_analogoverval = 425 sav->phy_analogoverval =
@@ -691,8 +500,12 @@ static void lo_measure_setup(struct b43_wldev *dev,
691 b43_radio_read16(dev, 0x51); /* dummy read */ 500 b43_radio_read16(dev, 0x51); /* dummy read */
692 if (phy->type == B43_PHYTYPE_G) 501 if (phy->type == B43_PHYTYPE_G)
693 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0); 502 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0);
694 if (lo->rebuild) 503
504 /* Re-measure the txctl values, if needed. */
505 if (time_before(lo->txctl_measured_time,
506 jiffies - B43_LO_TXCTL_EXPIRE))
695 lo_measure_txctl_values(dev); 507 lo_measure_txctl_values(dev);
508
696 if (phy->type == B43_PHYTYPE_G && phy->rev >= 3) { 509 if (phy->type == B43_PHYTYPE_G && phy->rev >= 3) {
697 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC078); 510 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC078);
698 } else { 511 } else {
@@ -707,7 +520,6 @@ static void lo_measure_restore(struct b43_wldev *dev,
707 struct lo_g_saved_values *sav) 520 struct lo_g_saved_values *sav)
708{ 521{
709 struct b43_phy *phy = &dev->phy; 522 struct b43_phy *phy = &dev->phy;
710 struct b43_txpower_lo_control *lo = phy->lo_control;
711 u16 tmp; 523 u16 tmp;
712 524
713 if (phy->rev >= 2) { 525 if (phy->rev >= 2) {
@@ -722,14 +534,6 @@ static void lo_measure_restore(struct b43_wldev *dev,
722 tmp = (phy->pga_gain | 0xEFA0); 534 tmp = (phy->pga_gain | 0xEFA0);
723 b43_phy_write(dev, B43_PHY_PGACTL, tmp); 535 b43_phy_write(dev, B43_PHY_PGACTL, tmp);
724 } 536 }
725 if (b43_has_hardware_pctl(phy)) {
726 b43_gphy_dc_lt_init(dev);
727 } else {
728 if (lo->rebuild)
729 b43_lo_g_adjust_to(dev, 3, 2, 0);
730 else
731 b43_lo_g_adjust(dev);
732 }
733 if (phy->type == B43_PHYTYPE_G) { 537 if (phy->type == B43_PHYTYPE_G) {
734 if (phy->rev >= 3) 538 if (phy->rev >= 3)
735 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0xC078); 539 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0xC078);
@@ -793,7 +597,6 @@ static int lo_probe_possible_loctls(struct b43_wldev *dev,
793 struct b43_lo_g_statemachine *d) 597 struct b43_lo_g_statemachine *d)
794{ 598{
795 struct b43_phy *phy = &dev->phy; 599 struct b43_phy *phy = &dev->phy;
796 struct b43_txpower_lo_control *lo = phy->lo_control;
797 struct b43_loctl test_loctl; 600 struct b43_loctl test_loctl;
798 struct b43_loctl orig_loctl; 601 struct b43_loctl orig_loctl;
799 struct b43_loctl prev_loctl = { 602 struct b43_loctl prev_loctl = {
@@ -852,7 +655,7 @@ static int lo_probe_possible_loctls(struct b43_wldev *dev,
852 found_lower = 1; 655 found_lower = 1;
853 d->lowest_feedth = feedth; 656 d->lowest_feedth = feedth;
854 if ((d->nr_measured < 2) && 657 if ((d->nr_measured < 2) &&
855 (!has_loopback_gain(phy) || lo->rebuild)) 658 !has_loopback_gain(phy))
856 break; 659 break;
857 } 660 }
858 } 661 }
@@ -874,7 +677,6 @@ static void lo_probe_loctls_statemachine(struct b43_wldev *dev,
874 int *max_rx_gain) 677 int *max_rx_gain)
875{ 678{
876 struct b43_phy *phy = &dev->phy; 679 struct b43_phy *phy = &dev->phy;
877 struct b43_txpower_lo_control *lo = phy->lo_control;
878 struct b43_lo_g_statemachine d; 680 struct b43_lo_g_statemachine d;
879 u16 feedth; 681 u16 feedth;
880 int found_lower; 682 int found_lower;
@@ -883,18 +685,18 @@ static void lo_probe_loctls_statemachine(struct b43_wldev *dev,
883 685
884 d.nr_measured = 0; 686 d.nr_measured = 0;
885 d.state_val_multiplier = 1; 687 d.state_val_multiplier = 1;
886 if (has_loopback_gain(phy) && !lo->rebuild) 688 if (has_loopback_gain(phy))
887 d.state_val_multiplier = 3; 689 d.state_val_multiplier = 3;
888 690
889 memcpy(&d.min_loctl, loctl, sizeof(struct b43_loctl)); 691 memcpy(&d.min_loctl, loctl, sizeof(struct b43_loctl));
890 if (has_loopback_gain(phy) && lo->rebuild) 692 if (has_loopback_gain(phy))
891 max_repeat = 4; 693 max_repeat = 4;
892 do { 694 do {
893 b43_lo_write(dev, &d.min_loctl); 695 b43_lo_write(dev, &d.min_loctl);
894 feedth = lo_measure_feedthrough(dev, phy->lna_gain, 696 feedth = lo_measure_feedthrough(dev, phy->lna_gain,
895 phy->pga_gain, 697 phy->pga_gain,
896 phy->trsw_rx_gain); 698 phy->trsw_rx_gain);
897 if (!lo->rebuild && feedth < 0x258) { 699 if (feedth < 0x258) {
898 if (feedth >= 0x12C) 700 if (feedth >= 0x12C)
899 *max_rx_gain += 6; 701 *max_rx_gain += 6;
900 else 702 else
@@ -944,278 +746,188 @@ static void lo_probe_loctls_statemachine(struct b43_wldev *dev,
944 } while (++repeat_cnt < max_repeat); 746 } while (++repeat_cnt < max_repeat);
945} 747}
946 748
947#if B43_CALIB_ALL_LOCTLS 749static
948static const struct b43_rfatt b43_full_rfatt_list_items[] = { 750struct b43_lo_calib * b43_calibrate_lo_setting(struct b43_wldev *dev,
949 { .att = 0, .with_padmix = 0, }, 751 const struct b43_bbatt *bbatt,
950 { .att = 1, .with_padmix = 0, }, 752 const struct b43_rfatt *rfatt)
951 { .att = 2, .with_padmix = 0, },
952 { .att = 3, .with_padmix = 0, },
953 { .att = 4, .with_padmix = 0, },
954 { .att = 5, .with_padmix = 0, },
955 { .att = 6, .with_padmix = 0, },
956 { .att = 7, .with_padmix = 0, },
957 { .att = 8, .with_padmix = 0, },
958 { .att = 9, .with_padmix = 0, },
959 { .att = 10, .with_padmix = 0, },
960 { .att = 11, .with_padmix = 0, },
961 { .att = 12, .with_padmix = 0, },
962 { .att = 13, .with_padmix = 0, },
963 { .att = 14, .with_padmix = 0, },
964 { .att = 15, .with_padmix = 0, },
965 { .att = 0, .with_padmix = 1, },
966 { .att = 1, .with_padmix = 1, },
967 { .att = 2, .with_padmix = 1, },
968 { .att = 3, .with_padmix = 1, },
969 { .att = 4, .with_padmix = 1, },
970 { .att = 5, .with_padmix = 1, },
971 { .att = 6, .with_padmix = 1, },
972 { .att = 7, .with_padmix = 1, },
973 { .att = 8, .with_padmix = 1, },
974 { .att = 9, .with_padmix = 1, },
975 { .att = 10, .with_padmix = 1, },
976 { .att = 11, .with_padmix = 1, },
977 { .att = 12, .with_padmix = 1, },
978 { .att = 13, .with_padmix = 1, },
979 { .att = 14, .with_padmix = 1, },
980 { .att = 15, .with_padmix = 1, },
981};
982static const struct b43_rfatt_list b43_full_rfatt_list = {
983 .list = b43_full_rfatt_list_items,
984 .len = ARRAY_SIZE(b43_full_rfatt_list_items),
985};
986
987static const struct b43_bbatt b43_full_bbatt_list_items[] = {
988 { .att = 0, },
989 { .att = 1, },
990 { .att = 2, },
991 { .att = 3, },
992 { .att = 4, },
993 { .att = 5, },
994 { .att = 6, },
995 { .att = 7, },
996 { .att = 8, },
997 { .att = 9, },
998 { .att = 10, },
999 { .att = 11, },
1000};
1001static const struct b43_bbatt_list b43_full_bbatt_list = {
1002 .list = b43_full_bbatt_list_items,
1003 .len = ARRAY_SIZE(b43_full_bbatt_list_items),
1004};
1005#endif /* B43_CALIB_ALL_LOCTLS */
1006
1007static void lo_measure(struct b43_wldev *dev)
1008{ 753{
1009 struct b43_phy *phy = &dev->phy; 754 struct b43_phy *phy = &dev->phy;
1010 struct b43_txpower_lo_control *lo = phy->lo_control;
1011 struct b43_loctl loctl = { 755 struct b43_loctl loctl = {
1012 .i = 0, 756 .i = 0,
1013 .q = 0, 757 .q = 0,
1014 }; 758 };
1015 struct b43_loctl *ploctl;
1016 int max_rx_gain; 759 int max_rx_gain;
1017 int rfidx, bbidx; 760 struct b43_lo_calib *cal;
1018 const struct b43_bbatt_list *bbatt_list; 761 struct lo_g_saved_values uninitialized_var(saved_regs);
1019 const struct b43_rfatt_list *rfatt_list;
1020
1021 /* Values from the "TXCTL Register and Value Table" */ 762 /* Values from the "TXCTL Register and Value Table" */
1022 u16 txctl_reg; 763 u16 txctl_reg;
1023 u16 txctl_value; 764 u16 txctl_value;
1024 u16 pad_mix_gain; 765 u16 pad_mix_gain;
1025 766
1026 bbatt_list = &lo->bbatt_list; 767 saved_regs.old_channel = phy->channel;
1027 rfatt_list = &lo->rfatt_list; 768 b43_mac_suspend(dev);
1028#if B43_CALIB_ALL_LOCTLS 769 lo_measure_setup(dev, &saved_regs);
1029 bbatt_list = &b43_full_bbatt_list;
1030 rfatt_list = &b43_full_rfatt_list;
1031#endif
1032 770
1033 txctl_reg = lo_txctl_register_table(dev, &txctl_value, &pad_mix_gain); 771 txctl_reg = lo_txctl_register_table(dev, &txctl_value, &pad_mix_gain);
1034 772
1035 for (rfidx = 0; rfidx < rfatt_list->len; rfidx++) { 773 b43_radio_write16(dev, 0x43,
1036 774 (b43_radio_read16(dev, 0x43) & 0xFFF0)
1037 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43) 775 | rfatt->att);
1038 & 0xFFF0) | 776 b43_radio_write16(dev, txctl_reg,
1039 rfatt_list->list[rfidx].att); 777 (b43_radio_read16(dev, txctl_reg) & ~txctl_value)
1040 b43_radio_write16(dev, txctl_reg, 778 | (rfatt->with_padmix) ? txctl_value : 0);
1041 (b43_radio_read16(dev, txctl_reg)
1042 & ~txctl_value)
1043 | (rfatt_list->list[rfidx].with_padmix ?
1044 txctl_value : 0));
1045
1046 for (bbidx = 0; bbidx < bbatt_list->len; bbidx++) {
1047 if (lo->rebuild) {
1048#if B43_CALIB_ALL_LOCTLS
1049 ploctl = b43_get_lo_g_ctl(dev,
1050 &rfatt_list->list[rfidx],
1051 &bbatt_list->list[bbidx]);
1052#else
1053 ploctl = b43_get_lo_g_ctl_nopadmix(dev,
1054 &rfatt_list->
1055 list[rfidx],
1056 &bbatt_list->
1057 list[bbidx]);
1058#endif
1059 } else {
1060 ploctl = b43_get_lo_g_ctl(dev,
1061 &rfatt_list->list[rfidx],
1062 &bbatt_list->list[bbidx]);
1063 if (!ploctl->used)
1064 continue;
1065 }
1066 memcpy(&loctl, ploctl, sizeof(loctl));
1067 loctl.i = 0;
1068 loctl.q = 0;
1069
1070 max_rx_gain = rfatt_list->list[rfidx].att * 2;
1071 max_rx_gain += bbatt_list->list[bbidx].att / 2;
1072 if (rfatt_list->list[rfidx].with_padmix)
1073 max_rx_gain -= pad_mix_gain;
1074 if (has_loopback_gain(phy))
1075 max_rx_gain += phy->max_lb_gain;
1076 lo_measure_gain_values(dev, max_rx_gain,
1077 has_loopback_gain(phy));
1078
1079 b43_phy_set_baseband_attenuation(dev,
1080 bbatt_list->list[bbidx].att);
1081 lo_probe_loctls_statemachine(dev, &loctl, &max_rx_gain);
1082 if (phy->type == B43_PHYTYPE_B) {
1083 loctl.i++;
1084 loctl.q++;
1085 }
1086 b43_loctl_set_calibrated(&loctl, 1);
1087 memcpy(ploctl, &loctl, sizeof(loctl));
1088 }
1089 }
1090}
1091
1092#if B43_DEBUG
1093static void do_validate_loctl(struct b43_wldev *dev, struct b43_loctl *control)
1094{
1095 const int is_initializing = (b43_status(dev) == B43_STAT_UNINIT);
1096 int i = control->i;
1097 int q = control->q;
1098 779
1099 if (b43_loctl_is_calibrated(control)) { 780 max_rx_gain = rfatt->att * 2;
1100 if ((abs(i) > 16) || (abs(q) > 16)) 781 max_rx_gain += bbatt->att / 2;
1101 goto error; 782 if (rfatt->with_padmix)
1102 } else { 783 max_rx_gain -= pad_mix_gain;
1103 if (control->used) 784 if (has_loopback_gain(phy))
1104 goto error; 785 max_rx_gain += phy->max_lb_gain;
1105 if (dev->phy.lo_control->rebuild) { 786 lo_measure_gain_values(dev, max_rx_gain,
1106 control->i = 0; 787 has_loopback_gain(phy));
1107 control->q = 0; 788
1108 if ((i != B43_LOCTL_POISON) || 789 b43_phy_set_baseband_attenuation(dev, bbatt->att);
1109 (q != B43_LOCTL_POISON)) 790 lo_probe_loctls_statemachine(dev, &loctl, &max_rx_gain);
1110 goto error; 791
1111 } 792 lo_measure_restore(dev, &saved_regs);
793 b43_mac_enable(dev);
794
795 if (b43_debug(dev, B43_DBG_LO)) {
796 b43dbg(dev->wl, "LO: Calibrated for BB(%u), RF(%u,%u) "
797 "=> I=%d Q=%d\n",
798 bbatt->att, rfatt->att, rfatt->with_padmix,
799 loctl.i, loctl.q);
1112 } 800 }
1113 if (is_initializing && control->used)
1114 goto error;
1115
1116 return;
1117error:
1118 b43err(dev->wl, "LO control pair validation failed "
1119 "(I: %d, Q: %d, used %u, calib: %u, initing: %d)\n",
1120 i, q, control->used,
1121 b43_loctl_is_calibrated(control),
1122 is_initializing);
1123}
1124 801
1125static void validate_all_loctls(struct b43_wldev *dev) 802 cal = kmalloc(sizeof(*cal), GFP_KERNEL);
1126{ 803 if (!cal) {
1127 b43_call_for_each_loctl(dev, do_validate_loctl); 804 b43warn(dev->wl, "LO calib: out of memory\n");
1128} 805 return NULL;
1129
1130static void do_reset_calib(struct b43_wldev *dev, struct b43_loctl *control)
1131{
1132 if (dev->phy.lo_control->rebuild ||
1133 control->used) {
1134 b43_loctl_set_calibrated(control, 0);
1135 control->i = B43_LOCTL_POISON;
1136 control->q = B43_LOCTL_POISON;
1137 } 806 }
807 memcpy(&cal->bbatt, bbatt, sizeof(*bbatt));
808 memcpy(&cal->rfatt, rfatt, sizeof(*rfatt));
809 memcpy(&cal->ctl, &loctl, sizeof(loctl));
810 cal->calib_time = jiffies;
811 INIT_LIST_HEAD(&cal->list);
812
813 return cal;
1138} 814}
1139 815
1140static void reset_all_loctl_calibration_states(struct b43_wldev *dev) 816/* Get a calibrated LO setting for the given attenuation values.
817 * Might return a NULL pointer under OOM! */
818static
819struct b43_lo_calib * b43_get_calib_lo_settings(struct b43_wldev *dev,
820 const struct b43_bbatt *bbatt,
821 const struct b43_rfatt *rfatt)
1141{ 822{
1142 b43_call_for_each_loctl(dev, do_reset_calib); 823 struct b43_txpower_lo_control *lo = dev->phy.lo_control;
824 struct b43_lo_calib *c;
825
826 c = b43_find_lo_calib(lo, bbatt, rfatt);
827 if (c)
828 return c;
829 /* Not in the list of calibrated LO settings.
830 * Calibrate it now. */
831 c = b43_calibrate_lo_setting(dev, bbatt, rfatt);
832 if (!c)
833 return NULL;
834 list_add(&c->list, &lo->calib_list);
835
836 return c;
1143} 837}
1144 838
1145#else /* B43_DEBUG */ 839void b43_gphy_dc_lt_init(struct b43_wldev *dev, bool update_all)
1146static inline void validate_all_loctls(struct b43_wldev *dev) { }
1147static inline void reset_all_loctl_calibration_states(struct b43_wldev *dev) { }
1148#endif /* B43_DEBUG */
1149
1150void b43_lo_g_measure(struct b43_wldev *dev)
1151{ 840{
1152 struct b43_phy *phy = &dev->phy; 841 struct b43_phy *phy = &dev->phy;
1153 struct lo_g_saved_values uninitialized_var(sav); 842 struct b43_txpower_lo_control *lo = phy->lo_control;
1154 843 int i;
1155 B43_WARN_ON((phy->type != B43_PHYTYPE_B) && 844 int rf_offset, bb_offset;
1156 (phy->type != B43_PHYTYPE_G)); 845 const struct b43_rfatt *rfatt;
1157 846 const struct b43_bbatt *bbatt;
1158 sav.old_channel = phy->channel; 847 u64 power_vector;
1159 lo_measure_setup(dev, &sav); 848 bool table_changed = 0;
1160 reset_all_loctl_calibration_states(dev);
1161 lo_measure(dev);
1162 lo_measure_restore(dev, &sav);
1163
1164 validate_all_loctls(dev);
1165 849
1166 phy->lo_control->lo_measured = 1; 850 BUILD_BUG_ON(B43_DC_LT_SIZE != 32);
1167 phy->lo_control->rebuild = 0; 851 B43_WARN_ON(lo->rfatt_list.len * lo->bbatt_list.len > 64);
1168}
1169 852
1170#if B43_DEBUG 853 power_vector = lo->power_vector;
1171static void validate_loctl_calibration(struct b43_wldev *dev, 854 if (!update_all && !power_vector)
1172 struct b43_loctl *loctl, 855 return; /* Nothing to do. */
1173 struct b43_rfatt *rfatt, 856
1174 struct b43_bbatt *bbatt) 857 /* Suspend the MAC now to avoid continuous suspend/enable
1175{ 858 * cycles in the loop. */
1176 if (b43_loctl_is_calibrated(loctl)) 859 b43_mac_suspend(dev);
1177 return; 860
1178 if (!dev->phy.lo_control->lo_measured) { 861 for (i = 0; i < B43_DC_LT_SIZE * 2; i++) {
1179 /* On init we set the attenuation values before we 862 struct b43_lo_calib *cal;
1180 * calibrated the LO. I guess that's OK. */ 863 int idx;
1181 return; 864 u16 val;
865
866 if (!update_all && !(power_vector & (((u64)1ULL) << i)))
867 continue;
868 /* Update the table entry for this power_vector bit.
869 * The table rows are RFatt entries and columns are BBatt. */
870 bb_offset = i / lo->rfatt_list.len;
871 rf_offset = i % lo->rfatt_list.len;
872 bbatt = &(lo->bbatt_list.list[bb_offset]);
873 rfatt = &(lo->rfatt_list.list[rf_offset]);
874
875 cal = b43_calibrate_lo_setting(dev, bbatt, rfatt);
876 if (!cal) {
877 b43warn(dev->wl, "LO: Could not "
878 "calibrate DC table entry\n");
879 continue;
880 }
881 /*FIXME: Is Q really in the low nibble? */
882 val = (u8)(cal->ctl.q);
883 val |= ((u8)(cal->ctl.i)) << 4;
884 kfree(cal);
885
886 /* Get the index into the hardware DC LT. */
887 idx = i / 2;
888 /* Change the table in memory. */
889 if (i % 2) {
890 /* Change the high byte. */
891 lo->dc_lt[idx] = (lo->dc_lt[idx] & 0x00FF)
892 | ((val & 0x00FF) << 8);
893 } else {
894 /* Change the low byte. */
895 lo->dc_lt[idx] = (lo->dc_lt[idx] & 0xFF00)
896 | (val & 0x00FF);
897 }
898 table_changed = 1;
1182 } 899 }
1183 b43err(dev->wl, "Adjusting Local Oscillator to an uncalibrated " 900 if (table_changed) {
1184 "control pair: rfatt=%u,%spadmix bbatt=%u\n", 901 /* The table changed in memory. Update the hardware table. */
1185 rfatt->att, 902 for (i = 0; i < B43_DC_LT_SIZE; i++)
1186 (rfatt->with_padmix) ? "" : "no-", 903 b43_phy_write(dev, 0x3A0 + i, lo->dc_lt[i]);
1187 bbatt->att); 904 }
1188} 905 b43_mac_enable(dev);
1189#else
1190static inline void validate_loctl_calibration(struct b43_wldev *dev,
1191 struct b43_loctl *loctl,
1192 struct b43_rfatt *rfatt,
1193 struct b43_bbatt *bbatt)
1194{
1195} 906}
1196#endif
1197 907
1198static inline void fixup_rfatt_for_txcontrol(struct b43_rfatt *rf, 908/* Fixup the RF attenuation value for the case where we are
1199 u8 tx_control) 909 * using the PAD mixer. */
910static inline void b43_lo_fixup_rfatt(struct b43_rfatt *rf)
1200{ 911{
1201 if (tx_control & B43_TXCTL_TXMIX) { 912 if (!rf->with_padmix)
1202 if (rf->att < 5) 913 return;
1203 rf->att = 4; 914 if ((rf->att != 1) && (rf->att != 2) && (rf->att != 3))
1204 } 915 rf->att = 4;
1205} 916}
1206 917
1207void b43_lo_g_adjust(struct b43_wldev *dev) 918void b43_lo_g_adjust(struct b43_wldev *dev)
1208{ 919{
1209 struct b43_phy *phy = &dev->phy; 920 struct b43_phy *phy = &dev->phy;
921 struct b43_lo_calib *cal;
1210 struct b43_rfatt rf; 922 struct b43_rfatt rf;
1211 struct b43_loctl *loctl;
1212 923
1213 memcpy(&rf, &phy->rfatt, sizeof(rf)); 924 memcpy(&rf, &phy->rfatt, sizeof(rf));
1214 fixup_rfatt_for_txcontrol(&rf, phy->tx_control); 925 b43_lo_fixup_rfatt(&rf);
1215 926
1216 loctl = b43_get_lo_g_ctl(dev, &rf, &phy->bbatt); 927 cal = b43_get_calib_lo_settings(dev, &phy->bbatt, &rf);
1217 validate_loctl_calibration(dev, loctl, &rf, &phy->bbatt); 928 if (!cal)
1218 b43_lo_write(dev, loctl); 929 return;
930 b43_lo_write(dev, &cal->ctl);
1219} 931}
1220 932
1221void b43_lo_g_adjust_to(struct b43_wldev *dev, 933void b43_lo_g_adjust_to(struct b43_wldev *dev,
@@ -1223,39 +935,102 @@ void b43_lo_g_adjust_to(struct b43_wldev *dev,
1223{ 935{
1224 struct b43_rfatt rf; 936 struct b43_rfatt rf;
1225 struct b43_bbatt bb; 937 struct b43_bbatt bb;
1226 struct b43_loctl *loctl; 938 struct b43_lo_calib *cal;
1227 939
1228 memset(&rf, 0, sizeof(rf)); 940 memset(&rf, 0, sizeof(rf));
1229 memset(&bb, 0, sizeof(bb)); 941 memset(&bb, 0, sizeof(bb));
1230 rf.att = rfatt; 942 rf.att = rfatt;
1231 bb.att = bbatt; 943 bb.att = bbatt;
1232 fixup_rfatt_for_txcontrol(&rf, tx_control); 944 b43_lo_fixup_rfatt(&rf);
1233 loctl = b43_get_lo_g_ctl(dev, &rf, &bb); 945 cal = b43_get_calib_lo_settings(dev, &bb, &rf);
1234 validate_loctl_calibration(dev, loctl, &rf, &bb); 946 if (!cal)
1235 b43_lo_write(dev, loctl); 947 return;
948 b43_lo_write(dev, &cal->ctl);
1236} 949}
1237 950
1238static void do_mark_unused(struct b43_wldev *dev, struct b43_loctl *control) 951/* Periodic LO maintanance work */
952void b43_lo_g_maintanance_work(struct b43_wldev *dev)
1239{ 953{
1240 control->used = 0; 954 struct b43_phy *phy = &dev->phy;
955 struct b43_txpower_lo_control *lo = phy->lo_control;
956 unsigned long now;
957 unsigned long expire;
958 struct b43_lo_calib *cal, *tmp;
959 bool current_item_expired = 0;
960 bool hwpctl;
961
962 if (!lo)
963 return;
964 now = jiffies;
965 hwpctl = b43_has_hardware_pctl(phy);
966
967 if (hwpctl) {
968 /* Read the power vector and update it, if needed. */
969 expire = now - B43_LO_PWRVEC_EXPIRE;
970 if (time_before(lo->pwr_vec_read_time, expire)) {
971 lo_read_power_vector(dev);
972 b43_gphy_dc_lt_init(dev, 0);
973 }
974 //FIXME Recalc the whole DC table from time to time?
975 }
976
977 if (hwpctl)
978 return;
979 /* Search for expired LO settings. Remove them.
980 * Recalibrate the current setting, if expired. */
981 expire = now - B43_LO_CALIB_EXPIRE;
982 list_for_each_entry_safe(cal, tmp, &lo->calib_list, list) {
983 if (!time_before(cal->calib_time, expire))
984 continue;
985 /* This item expired. */
986 if (b43_compare_bbatt(&cal->bbatt, &phy->bbatt) &&
987 b43_compare_rfatt(&cal->rfatt, &phy->rfatt)) {
988 B43_WARN_ON(current_item_expired);
989 current_item_expired = 1;
990 }
991 if (b43_debug(dev, B43_DBG_LO)) {
992 b43dbg(dev->wl, "LO: Item BB(%u), RF(%u,%u), "
993 "I=%d, Q=%d expired\n",
994 cal->bbatt.att, cal->rfatt.att,
995 cal->rfatt.with_padmix,
996 cal->ctl.i, cal->ctl.q);
997 }
998 list_del(&cal->list);
999 kfree(cal);
1000 }
1001 if (current_item_expired || unlikely(list_empty(&lo->calib_list))) {
1002 /* Recalibrate currently used LO setting. */
1003 if (b43_debug(dev, B43_DBG_LO))
1004 b43dbg(dev->wl, "LO: Recalibrating current LO setting\n");
1005 cal = b43_calibrate_lo_setting(dev, &phy->bbatt, &phy->rfatt);
1006 if (cal) {
1007 list_add(&cal->list, &lo->calib_list);
1008 b43_lo_write(dev, &cal->ctl);
1009 } else
1010 b43warn(dev->wl, "Failed to recalibrate current LO setting\n");
1011 }
1241} 1012}
1242 1013
1243void b43_lo_g_ctl_mark_all_unused(struct b43_wldev *dev) 1014void b43_lo_g_cleanup(struct b43_wldev *dev)
1244{ 1015{
1245 struct b43_phy *phy = &dev->phy; 1016 struct b43_txpower_lo_control *lo = dev->phy.lo_control;
1246 struct b43_txpower_lo_control *lo = phy->lo_control; 1017 struct b43_lo_calib *cal, *tmp;
1247 1018
1248 b43_call_for_each_loctl(dev, do_mark_unused); 1019 if (!lo)
1249 lo->rebuild = 1; 1020 return;
1021 list_for_each_entry_safe(cal, tmp, &lo->calib_list, list) {
1022 list_del(&cal->list);
1023 kfree(cal);
1024 }
1250} 1025}
1251 1026
1252void b43_lo_g_ctl_mark_cur_used(struct b43_wldev *dev) 1027/* LO Initialization */
1028void b43_lo_g_init(struct b43_wldev *dev)
1253{ 1029{
1254 struct b43_phy *phy = &dev->phy; 1030 struct b43_phy *phy = &dev->phy;
1255 struct b43_rfatt rf;
1256 1031
1257 memcpy(&rf, &phy->rfatt, sizeof(rf)); 1032 if (b43_has_hardware_pctl(phy)) {
1258 fixup_rfatt_for_txcontrol(&rf, phy->tx_control); 1033 lo_read_power_vector(dev);
1259 1034 b43_gphy_dc_lt_init(dev, 1);
1260 b43_get_lo_g_ctl(dev, &rf, &phy->bbatt)->used = 1; 1035 }
1261} 1036}
diff --git a/drivers/net/wireless/b43/lo.h b/drivers/net/wireless/b43/lo.h
index 455615d1f8c6..1da321cabc12 100644
--- a/drivers/net/wireless/b43/lo.h
+++ b/drivers/net/wireless/b43/lo.h
@@ -10,82 +10,63 @@ struct b43_loctl {
10 /* Control values. */ 10 /* Control values. */
11 s8 i; 11 s8 i;
12 s8 q; 12 s8 q;
13 /* "Used by hardware" flag. */
14 bool used;
15#ifdef CONFIG_B43_DEBUG
16 /* Is this lo-control-array entry calibrated? */
17 bool calibrated;
18#endif
19}; 13};
20
21/* Debugging: Poison value for i and q values. */ 14/* Debugging: Poison value for i and q values. */
22#define B43_LOCTL_POISON 111 15#define B43_LOCTL_POISON 111
23 16
24/* loctl->calibrated debugging mechanism */ 17/* This struct holds calibrated LO settings for a set of
25#ifdef CONFIG_B43_DEBUG 18 * Baseband and RF attenuation settings. */
26static inline void b43_loctl_set_calibrated(struct b43_loctl *loctl, 19struct b43_lo_calib {
27 bool calibrated) 20 /* The set of attenuation values this set of LO
28{ 21 * control values is calibrated for. */
29 loctl->calibrated = calibrated; 22 struct b43_bbatt bbatt;
30} 23 struct b43_rfatt rfatt;
31static inline bool b43_loctl_is_calibrated(struct b43_loctl *loctl) 24 /* The set of control values for the LO. */
32{ 25 struct b43_loctl ctl;
33 return loctl->calibrated; 26 /* The time when these settings were calibrated (in jiffies) */
34} 27 unsigned long calib_time;
35#else 28 /* List. */
36static inline void b43_loctl_set_calibrated(struct b43_loctl *loctl, 29 struct list_head list;
37 bool calibrated) 30};
38{ 31
39} 32/* Size of the DC Lookup Table in 16bit words. */
40static inline bool b43_loctl_is_calibrated(struct b43_loctl *loctl) 33#define B43_DC_LT_SIZE 32
41{ 34
42 return 1; 35/* Local Oscillator calibration information */
43}
44#endif
45
46/* TX Power LO Control Array.
47 * Value-pairs to adjust the LocalOscillator are stored
48 * in this structure.
49 * There are two different set of values. One for "Flag is Set"
50 * and one for "Flag is Unset".
51 * By "Flag" the flag in struct b43_rfatt is meant.
52 * The Value arrays are two-dimensional. The first index
53 * is the baseband attenuation and the second index
54 * is the radio attenuation.
55 * Use b43_get_lo_g_ctl() to retrieve a value from the lists.
56 */
57struct b43_txpower_lo_control { 36struct b43_txpower_lo_control {
58#define B43_NR_BB 12 37 /* Lists of RF and BB attenuation values for this device.
59#define B43_NR_RF 16 38 * Used for building hardware power control tables. */
60 /* LO Control values, with PAD Mixer */
61 struct b43_loctl with_padmix[B43_NR_BB][B43_NR_RF];
62 /* LO Control values, without PAD Mixer */
63 struct b43_loctl no_padmix[B43_NR_BB][B43_NR_RF];
64
65 /* Flag to indicate a complete rebuild of the two tables above
66 * to the LO measuring code. */
67 bool rebuild;
68
69 /* Lists of valid RF and BB attenuation values for this device. */
70 struct b43_rfatt_list rfatt_list; 39 struct b43_rfatt_list rfatt_list;
71 struct b43_bbatt_list bbatt_list; 40 struct b43_bbatt_list bbatt_list;
72 41
42 /* The DC Lookup Table is cached in memory here.
43 * Note that this is only used for Hardware Power Control. */
44 u16 dc_lt[B43_DC_LT_SIZE];
45
46 /* List of calibrated control values (struct b43_lo_calib). */
47 struct list_head calib_list;
48 /* Last time the power vector was read (jiffies). */
49 unsigned long pwr_vec_read_time;
50 /* Last time the txctl values were measured (jiffies). */
51 unsigned long txctl_measured_time;
52
73 /* Current TX Bias value */ 53 /* Current TX Bias value */
74 u8 tx_bias; 54 u8 tx_bias;
75 /* Current TX Magnification Value (if used by the device) */ 55 /* Current TX Magnification Value (if used by the device) */
76 u8 tx_magn; 56 u8 tx_magn;
77 57
78 /* GPHY LO is measured. */
79 bool lo_measured;
80
81 /* Saved device PowerVector */ 58 /* Saved device PowerVector */
82 u64 power_vector; 59 u64 power_vector;
83}; 60};
84 61
85/* Measure the BPHY Local Oscillator. */ 62/* Calibration expire timeouts.
86void b43_lo_b_measure(struct b43_wldev *dev); 63 * Timeouts must be multiple of 15 seconds. To make sure
87/* Measure the BPHY/GPHY Local Oscillator. */ 64 * the item really expired when the 15 second timer hits, we
88void b43_lo_g_measure(struct b43_wldev *dev); 65 * subtract two additional seconds from the timeout. */
66#define B43_LO_CALIB_EXPIRE (HZ * (30 - 2))
67#define B43_LO_PWRVEC_EXPIRE (HZ * (30 - 2))
68#define B43_LO_TXCTL_EXPIRE (HZ * (180 - 4))
69
89 70
90/* Adjust the Local Oscillator to the saved attenuation 71/* Adjust the Local Oscillator to the saved attenuation
91 * and txctl values. 72 * and txctl values.
@@ -95,18 +76,10 @@ void b43_lo_g_adjust(struct b43_wldev *dev);
95void b43_lo_g_adjust_to(struct b43_wldev *dev, 76void b43_lo_g_adjust_to(struct b43_wldev *dev,
96 u16 rfatt, u16 bbatt, u16 tx_control); 77 u16 rfatt, u16 bbatt, u16 tx_control);
97 78
98/* Mark all possible b43_lo_g_ctl as "unused" */ 79void b43_gphy_dc_lt_init(struct b43_wldev *dev, bool update_all);
99void b43_lo_g_ctl_mark_all_unused(struct b43_wldev *dev);
100/* Mark the b43_lo_g_ctl corresponding to the current
101 * attenuation values as used.
102 */
103void b43_lo_g_ctl_mark_cur_used(struct b43_wldev *dev);
104 80
105/* Get a reference to a LO Control value pair in the 81void b43_lo_g_maintanance_work(struct b43_wldev *dev);
106 * TX Power LO Control Array. 82void b43_lo_g_cleanup(struct b43_wldev *dev);
107 */ 83void b43_lo_g_init(struct b43_wldev *dev);
108struct b43_loctl *b43_get_lo_g_ctl(struct b43_wldev *dev,
109 const struct b43_rfatt *rfatt,
110 const struct b43_bbatt *bbatt);
111 84
112#endif /* B43_LO_H_ */ 85#endif /* B43_LO_H_ */
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index a70827793086..e78319aa47c1 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -373,13 +373,10 @@ static inline void b43_shm_control_word(struct b43_wldev *dev,
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
374} 374}
375 375
376u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 376u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
377{ 377{
378 struct b43_wl *wl = dev->wl;
379 unsigned long flags;
380 u32 ret; 378 u32 ret;
381 379
382 spin_lock_irqsave(&wl->shm_lock, flags);
383 if (routing == B43_SHM_SHARED) { 380 if (routing == B43_SHM_SHARED) {
384 B43_WARN_ON(offset & 0x0001); 381 B43_WARN_ON(offset & 0x0001);
385 if (offset & 0x0003) { 382 if (offset & 0x0003) {
@@ -397,18 +394,26 @@ u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
397 b43_shm_control_word(dev, routing, offset); 394 b43_shm_control_word(dev, routing, offset);
398 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 395 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
399out: 396out:
400 spin_unlock_irqrestore(&wl->shm_lock, flags);
401
402 return ret; 397 return ret;
403} 398}
404 399
405u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset) 400u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
406{ 401{
407 struct b43_wl *wl = dev->wl; 402 struct b43_wl *wl = dev->wl;
408 unsigned long flags; 403 unsigned long flags;
409 u16 ret; 404 u32 ret;
410 405
411 spin_lock_irqsave(&wl->shm_lock, flags); 406 spin_lock_irqsave(&wl->shm_lock, flags);
407 ret = __b43_shm_read32(dev, routing, offset);
408 spin_unlock_irqrestore(&wl->shm_lock, flags);
409
410 return ret;
411}
412
413u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
414{
415 u16 ret;
416
412 if (routing == B43_SHM_SHARED) { 417 if (routing == B43_SHM_SHARED) {
413 B43_WARN_ON(offset & 0x0001); 418 B43_WARN_ON(offset & 0x0001);
414 if (offset & 0x0003) { 419 if (offset & 0x0003) {
@@ -423,17 +428,24 @@ u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
423 b43_shm_control_word(dev, routing, offset); 428 b43_shm_control_word(dev, routing, offset);
424 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 429 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
425out: 430out:
426 spin_unlock_irqrestore(&wl->shm_lock, flags);
427
428 return ret; 431 return ret;
429} 432}
430 433
431void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 434u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
432{ 435{
433 struct b43_wl *wl = dev->wl; 436 struct b43_wl *wl = dev->wl;
434 unsigned long flags; 437 unsigned long flags;
438 u16 ret;
435 439
436 spin_lock_irqsave(&wl->shm_lock, flags); 440 spin_lock_irqsave(&wl->shm_lock, flags);
441 ret = __b43_shm_read16(dev, routing, offset);
442 spin_unlock_irqrestore(&wl->shm_lock, flags);
443
444 return ret;
445}
446
447void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
448{
437 if (routing == B43_SHM_SHARED) { 449 if (routing == B43_SHM_SHARED) {
438 B43_WARN_ON(offset & 0x0001); 450 B43_WARN_ON(offset & 0x0001);
439 if (offset & 0x0003) { 451 if (offset & 0x0003) {
@@ -443,35 +455,47 @@ void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
443 (value >> 16) & 0xffff); 455 (value >> 16) & 0xffff);
444 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 456 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
445 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff); 457 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
446 goto out; 458 return;
447 } 459 }
448 offset >>= 2; 460 offset >>= 2;
449 } 461 }
450 b43_shm_control_word(dev, routing, offset); 462 b43_shm_control_word(dev, routing, offset);
451 b43_write32(dev, B43_MMIO_SHM_DATA, value); 463 b43_write32(dev, B43_MMIO_SHM_DATA, value);
452out:
453 spin_unlock_irqrestore(&wl->shm_lock, flags);
454} 464}
455 465
456void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 466void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
457{ 467{
458 struct b43_wl *wl = dev->wl; 468 struct b43_wl *wl = dev->wl;
459 unsigned long flags; 469 unsigned long flags;
460 470
461 spin_lock_irqsave(&wl->shm_lock, flags); 471 spin_lock_irqsave(&wl->shm_lock, flags);
472 __b43_shm_write32(dev, routing, offset, value);
473 spin_unlock_irqrestore(&wl->shm_lock, flags);
474}
475
476void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
477{
462 if (routing == B43_SHM_SHARED) { 478 if (routing == B43_SHM_SHARED) {
463 B43_WARN_ON(offset & 0x0001); 479 B43_WARN_ON(offset & 0x0001);
464 if (offset & 0x0003) { 480 if (offset & 0x0003) {
465 /* Unaligned access */ 481 /* Unaligned access */
466 b43_shm_control_word(dev, routing, offset >> 2); 482 b43_shm_control_word(dev, routing, offset >> 2);
467 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 483 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
468 goto out; 484 return;
469 } 485 }
470 offset >>= 2; 486 offset >>= 2;
471 } 487 }
472 b43_shm_control_word(dev, routing, offset); 488 b43_shm_control_word(dev, routing, offset);
473 b43_write16(dev, B43_MMIO_SHM_DATA, value); 489 b43_write16(dev, B43_MMIO_SHM_DATA, value);
474out: 490}
491
492void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
493{
494 struct b43_wl *wl = dev->wl;
495 unsigned long flags;
496
497 spin_lock_irqsave(&wl->shm_lock, flags);
498 __b43_shm_write16(dev, routing, offset, value);
475 spin_unlock_irqrestore(&wl->shm_lock, flags); 499 spin_unlock_irqrestore(&wl->shm_lock, flags);
476} 500}
477 501
@@ -1187,10 +1211,10 @@ static void handle_irq_noise(struct b43_wldev *dev)
1187 /* Get the noise samples. */ 1211 /* Get the noise samples. */
1188 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1212 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1189 i = dev->noisecalc.nr_samples; 1213 i = dev->noisecalc.nr_samples;
1190 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1214 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1191 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1215 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1192 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1216 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1193 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1217 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1194 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1218 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1195 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1219 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1196 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1220 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
@@ -1372,18 +1396,18 @@ static void b43_write_beacon_template(struct b43_wldev *dev,
1372 unsigned int rate; 1396 unsigned int rate;
1373 u16 ctl; 1397 u16 ctl;
1374 int antenna; 1398 int antenna;
1399 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1375 1400
1376 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); 1401 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1377 len = min((size_t) dev->wl->current_beacon->len, 1402 len = min((size_t) dev->wl->current_beacon->len,
1378 0x200 - sizeof(struct b43_plcp_hdr6)); 1403 0x200 - sizeof(struct b43_plcp_hdr6));
1379 rate = dev->wl->beacon_txctl.tx_rate->hw_value; 1404 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1380 1405
1381 b43_write_template_common(dev, (const u8 *)bcn, 1406 b43_write_template_common(dev, (const u8 *)bcn,
1382 len, ram_offset, shm_size_offset, rate); 1407 len, ram_offset, shm_size_offset, rate);
1383 1408
1384 /* Write the PHY TX control parameters. */ 1409 /* Write the PHY TX control parameters. */
1385 antenna = b43_antenna_from_ieee80211(dev, 1410 antenna = b43_antenna_from_ieee80211(dev, info->antenna_sel_tx);
1386 dev->wl->beacon_txctl.antenna_sel_tx);
1387 antenna = b43_antenna_to_phyctl(antenna); 1411 antenna = b43_antenna_to_phyctl(antenna);
1388 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 1412 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1389 /* We can't send beacons with short preamble. Would get PHY errors. */ 1413 /* We can't send beacons with short preamble. Would get PHY errors. */
@@ -1434,11 +1458,17 @@ static void b43_write_beacon_template(struct b43_wldev *dev,
1434 i += ie_len + 2; 1458 i += ie_len + 2;
1435 } 1459 }
1436 if (!tim_found) { 1460 if (!tim_found) {
1437 b43warn(dev->wl, "Did not find a valid TIM IE in " 1461 /*
1438 "the beacon template packet. AP or IBSS operation " 1462 * If ucode wants to modify TIM do it behind the beacon, this
1439 "may be broken.\n"); 1463 * will happen, for example, when doing mesh networking.
1440 } else 1464 */
1441 b43dbg(dev->wl, "Updated beacon template\n"); 1465 b43_shm_write16(dev, B43_SHM_SHARED,
1466 B43_SHM_SH_TIMBPOS,
1467 len + sizeof(struct b43_plcp_hdr6));
1468 b43_shm_write16(dev, B43_SHM_SHARED,
1469 B43_SHM_SH_DTIMPER, 0);
1470 }
1471 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1442} 1472}
1443 1473
1444static void b43_write_probe_resp_plcp(struct b43_wldev *dev, 1474static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
@@ -1577,7 +1607,8 @@ static void handle_irq_beacon(struct b43_wldev *dev)
1577 struct b43_wl *wl = dev->wl; 1607 struct b43_wl *wl = dev->wl;
1578 u32 cmd, beacon0_valid, beacon1_valid; 1608 u32 cmd, beacon0_valid, beacon1_valid;
1579 1609
1580 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 1610 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP) &&
1611 !b43_is_mode(wl, IEEE80211_IF_TYPE_MESH_POINT))
1581 return; 1612 return;
1582 1613
1583 /* This is the bottom half of the asynchronous beacon update. */ 1614 /* This is the bottom half of the asynchronous beacon update. */
@@ -1644,19 +1675,27 @@ static void b43_beacon_update_trigger_work(struct work_struct *work)
1644 1675
1645/* Asynchronously update the packet templates in template RAM. 1676/* Asynchronously update the packet templates in template RAM.
1646 * Locking: Requires wl->irq_lock to be locked. */ 1677 * Locking: Requires wl->irq_lock to be locked. */
1647static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon, 1678static void b43_update_templates(struct b43_wl *wl)
1648 const struct ieee80211_tx_control *txctl)
1649{ 1679{
1680 struct sk_buff *beacon;
1681
1650 /* This is the top half of the ansynchronous beacon update. 1682 /* This is the top half of the ansynchronous beacon update.
1651 * The bottom half is the beacon IRQ. 1683 * The bottom half is the beacon IRQ.
1652 * Beacon update must be asynchronous to avoid sending an 1684 * Beacon update must be asynchronous to avoid sending an
1653 * invalid beacon. This can happen for example, if the firmware 1685 * invalid beacon. This can happen for example, if the firmware
1654 * transmits a beacon while we are updating it. */ 1686 * transmits a beacon while we are updating it. */
1655 1687
1688 /* We could modify the existing beacon and set the aid bit in
1689 * the TIM field, but that would probably require resizing and
1690 * moving of data within the beacon template.
1691 * Simply request a new beacon and let mac80211 do the hard work. */
1692 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1693 if (unlikely(!beacon))
1694 return;
1695
1656 if (wl->current_beacon) 1696 if (wl->current_beacon)
1657 dev_kfree_skb_any(wl->current_beacon); 1697 dev_kfree_skb_any(wl->current_beacon);
1658 wl->current_beacon = beacon; 1698 wl->current_beacon = beacon;
1659 memcpy(&wl->beacon_txctl, txctl, sizeof(wl->beacon_txctl));
1660 wl->beacon0_uploaded = 0; 1699 wl->beacon0_uploaded = 0;
1661 wl->beacon1_uploaded = 0; 1700 wl->beacon1_uploaded = 0;
1662 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger); 1701 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
@@ -1695,9 +1734,100 @@ static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1695 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int); 1734 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1696} 1735}
1697 1736
1737static void b43_handle_firmware_panic(struct b43_wldev *dev)
1738{
1739 u16 reason;
1740
1741 /* Read the register that contains the reason code for the panic. */
1742 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1743 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1744
1745 switch (reason) {
1746 default:
1747 b43dbg(dev->wl, "The panic reason is unknown.\n");
1748 /* fallthrough */
1749 case B43_FWPANIC_DIE:
1750 /* Do not restart the controller or firmware.
1751 * The device is nonfunctional from now on.
1752 * Restarting would result in this panic to trigger again,
1753 * so we avoid that recursion. */
1754 break;
1755 case B43_FWPANIC_RESTART:
1756 b43_controller_restart(dev, "Microcode panic");
1757 break;
1758 }
1759}
1760
1698static void handle_irq_ucode_debug(struct b43_wldev *dev) 1761static void handle_irq_ucode_debug(struct b43_wldev *dev)
1699{ 1762{
1700 //TODO 1763 unsigned int i, cnt;
1764 u16 reason, marker_id, marker_line;
1765 __le16 *buf;
1766
1767 /* The proprietary firmware doesn't have this IRQ. */
1768 if (!dev->fw.opensource)
1769 return;
1770
1771 /* Read the register that contains the reason code for this IRQ. */
1772 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1773
1774 switch (reason) {
1775 case B43_DEBUGIRQ_PANIC:
1776 b43_handle_firmware_panic(dev);
1777 break;
1778 case B43_DEBUGIRQ_DUMP_SHM:
1779 if (!B43_DEBUG)
1780 break; /* Only with driver debugging enabled. */
1781 buf = kmalloc(4096, GFP_ATOMIC);
1782 if (!buf) {
1783 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1784 goto out;
1785 }
1786 for (i = 0; i < 4096; i += 2) {
1787 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1788 buf[i / 2] = cpu_to_le16(tmp);
1789 }
1790 b43info(dev->wl, "Shared memory dump:\n");
1791 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1792 16, 2, buf, 4096, 1);
1793 kfree(buf);
1794 break;
1795 case B43_DEBUGIRQ_DUMP_REGS:
1796 if (!B43_DEBUG)
1797 break; /* Only with driver debugging enabled. */
1798 b43info(dev->wl, "Microcode register dump:\n");
1799 for (i = 0, cnt = 0; i < 64; i++) {
1800 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1801 if (cnt == 0)
1802 printk(KERN_INFO);
1803 printk("r%02u: 0x%04X ", i, tmp);
1804 cnt++;
1805 if (cnt == 6) {
1806 printk("\n");
1807 cnt = 0;
1808 }
1809 }
1810 printk("\n");
1811 break;
1812 case B43_DEBUGIRQ_MARKER:
1813 if (!B43_DEBUG)
1814 break; /* Only with driver debugging enabled. */
1815 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1816 B43_MARKER_ID_REG);
1817 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1818 B43_MARKER_LINE_REG);
1819 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1820 "at line number %u\n",
1821 marker_id, marker_line);
1822 break;
1823 default:
1824 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1825 reason);
1826 }
1827out:
1828 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1829 b43_shm_write16(dev, B43_SHM_SCRATCH,
1830 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1701} 1831}
1702 1832
1703/* Interrupt handler bottom-half */ 1833/* Interrupt handler bottom-half */
@@ -1884,7 +2014,8 @@ static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1884 2014
1885static int do_request_fw(struct b43_wldev *dev, 2015static int do_request_fw(struct b43_wldev *dev,
1886 const char *name, 2016 const char *name,
1887 struct b43_firmware_file *fw) 2017 struct b43_firmware_file *fw,
2018 bool silent)
1888{ 2019{
1889 char path[sizeof(modparam_fwpostfix) + 32]; 2020 char path[sizeof(modparam_fwpostfix) + 32];
1890 const struct firmware *blob; 2021 const struct firmware *blob;
@@ -1908,9 +2039,15 @@ static int do_request_fw(struct b43_wldev *dev,
1908 "b43%s/%s.fw", 2039 "b43%s/%s.fw",
1909 modparam_fwpostfix, name); 2040 modparam_fwpostfix, name);
1910 err = request_firmware(&blob, path, dev->dev->dev); 2041 err = request_firmware(&blob, path, dev->dev->dev);
1911 if (err) { 2042 if (err == -ENOENT) {
1912 b43err(dev->wl, "Firmware file \"%s\" not found " 2043 if (!silent) {
1913 "or load failed.\n", path); 2044 b43err(dev->wl, "Firmware file \"%s\" not found\n",
2045 path);
2046 }
2047 return err;
2048 } else if (err) {
2049 b43err(dev->wl, "Firmware file \"%s\" request failed (err=%d)\n",
2050 path, err);
1914 return err; 2051 return err;
1915 } 2052 }
1916 if (blob->size < sizeof(struct b43_fw_header)) 2053 if (blob->size < sizeof(struct b43_fw_header))
@@ -1961,7 +2098,7 @@ static int b43_request_firmware(struct b43_wldev *dev)
1961 filename = "ucode13"; 2098 filename = "ucode13";
1962 else 2099 else
1963 goto err_no_ucode; 2100 goto err_no_ucode;
1964 err = do_request_fw(dev, filename, &fw->ucode); 2101 err = do_request_fw(dev, filename, &fw->ucode, 0);
1965 if (err) 2102 if (err)
1966 goto err_load; 2103 goto err_load;
1967 2104
@@ -1972,8 +2109,13 @@ static int b43_request_firmware(struct b43_wldev *dev)
1972 filename = NULL; 2109 filename = NULL;
1973 else 2110 else
1974 goto err_no_pcm; 2111 goto err_no_pcm;
1975 err = do_request_fw(dev, filename, &fw->pcm); 2112 fw->pcm_request_failed = 0;
1976 if (err) 2113 err = do_request_fw(dev, filename, &fw->pcm, 1);
2114 if (err == -ENOENT) {
2115 /* We did not find a PCM file? Not fatal, but
2116 * core rev <= 10 must do without hwcrypto then. */
2117 fw->pcm_request_failed = 1;
2118 } else if (err)
1977 goto err_load; 2119 goto err_load;
1978 2120
1979 /* Get initvals */ 2121 /* Get initvals */
@@ -1991,7 +2133,7 @@ static int b43_request_firmware(struct b43_wldev *dev)
1991 if ((rev >= 5) && (rev <= 10)) 2133 if ((rev >= 5) && (rev <= 10))
1992 filename = "b0g0initvals5"; 2134 filename = "b0g0initvals5";
1993 else if (rev >= 13) 2135 else if (rev >= 13)
1994 filename = "lp0initvals13"; 2136 filename = "b0g0initvals13";
1995 else 2137 else
1996 goto err_no_initvals; 2138 goto err_no_initvals;
1997 break; 2139 break;
@@ -2004,7 +2146,7 @@ static int b43_request_firmware(struct b43_wldev *dev)
2004 default: 2146 default:
2005 goto err_no_initvals; 2147 goto err_no_initvals;
2006 } 2148 }
2007 err = do_request_fw(dev, filename, &fw->initvals); 2149 err = do_request_fw(dev, filename, &fw->initvals, 0);
2008 if (err) 2150 if (err)
2009 goto err_load; 2151 goto err_load;
2010 2152
@@ -2038,7 +2180,7 @@ static int b43_request_firmware(struct b43_wldev *dev)
2038 default: 2180 default:
2039 goto err_no_initvals; 2181 goto err_no_initvals;
2040 } 2182 }
2041 err = do_request_fw(dev, filename, &fw->initvals_band); 2183 err = do_request_fw(dev, filename, &fw->initvals_band, 0);
2042 if (err) 2184 if (err)
2043 goto err_load; 2185 goto err_load;
2044 2186
@@ -2155,14 +2297,28 @@ static int b43_upload_microcode(struct b43_wldev *dev)
2155 err = -EOPNOTSUPP; 2297 err = -EOPNOTSUPP;
2156 goto error; 2298 goto error;
2157 } 2299 }
2158 b43info(dev->wl, "Loading firmware version %u.%u "
2159 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2160 fwrev, fwpatch,
2161 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2162 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2163
2164 dev->fw.rev = fwrev; 2300 dev->fw.rev = fwrev;
2165 dev->fw.patch = fwpatch; 2301 dev->fw.patch = fwpatch;
2302 dev->fw.opensource = (fwdate == 0xFFFF);
2303
2304 if (dev->fw.opensource) {
2305 /* Patchlevel info is encoded in the "time" field. */
2306 dev->fw.patch = fwtime;
2307 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2308 dev->fw.rev, dev->fw.patch,
2309 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
2310 } else {
2311 b43info(dev->wl, "Loading firmware version %u.%u "
2312 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2313 fwrev, fwpatch,
2314 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2315 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2316 if (dev->fw.pcm_request_failed) {
2317 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2318 "Hardware accelerated cryptography is disabled.\n");
2319 b43_print_fw_helptext(dev->wl, 0);
2320 }
2321 }
2166 2322
2167 if (b43_is_old_txhdr_format(dev)) { 2323 if (b43_is_old_txhdr_format(dev)) {
2168 b43warn(dev->wl, "You are using an old firmware image. " 2324 b43warn(dev->wl, "You are using an old firmware image. "
@@ -2339,8 +2495,21 @@ static void b43_gpio_cleanup(struct b43_wldev *dev)
2339} 2495}
2340 2496
2341/* http://bcm-specs.sipsolutions.net/EnableMac */ 2497/* http://bcm-specs.sipsolutions.net/EnableMac */
2342static void b43_mac_enable(struct b43_wldev *dev) 2498void b43_mac_enable(struct b43_wldev *dev)
2343{ 2499{
2500 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2501 u16 fwstate;
2502
2503 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2504 B43_SHM_SH_UCODESTAT);
2505 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2506 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2507 b43err(dev->wl, "b43_mac_enable(): The firmware "
2508 "should be suspended, but current state is %u\n",
2509 fwstate);
2510 }
2511 }
2512
2344 dev->mac_suspended--; 2513 dev->mac_suspended--;
2345 B43_WARN_ON(dev->mac_suspended < 0); 2514 B43_WARN_ON(dev->mac_suspended < 0);
2346 if (dev->mac_suspended == 0) { 2515 if (dev->mac_suspended == 0) {
@@ -2353,16 +2522,11 @@ static void b43_mac_enable(struct b43_wldev *dev)
2353 b43_read32(dev, B43_MMIO_MACCTL); 2522 b43_read32(dev, B43_MMIO_MACCTL);
2354 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2523 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2355 b43_power_saving_ctl_bits(dev, 0); 2524 b43_power_saving_ctl_bits(dev, 0);
2356
2357 /* Re-enable IRQs. */
2358 spin_lock_irq(&dev->wl->irq_lock);
2359 b43_interrupt_enable(dev, dev->irq_savedstate);
2360 spin_unlock_irq(&dev->wl->irq_lock);
2361 } 2525 }
2362} 2526}
2363 2527
2364/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 2528/* http://bcm-specs.sipsolutions.net/SuspendMAC */
2365static void b43_mac_suspend(struct b43_wldev *dev) 2529void b43_mac_suspend(struct b43_wldev *dev)
2366{ 2530{
2367 int i; 2531 int i;
2368 u32 tmp; 2532 u32 tmp;
@@ -2371,14 +2535,6 @@ static void b43_mac_suspend(struct b43_wldev *dev)
2371 B43_WARN_ON(dev->mac_suspended < 0); 2535 B43_WARN_ON(dev->mac_suspended < 0);
2372 2536
2373 if (dev->mac_suspended == 0) { 2537 if (dev->mac_suspended == 0) {
2374 /* Mask IRQs before suspending MAC. Otherwise
2375 * the MAC stays busy and won't suspend. */
2376 spin_lock_irq(&dev->wl->irq_lock);
2377 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2378 spin_unlock_irq(&dev->wl->irq_lock);
2379 b43_synchronize_irq(dev);
2380 dev->irq_savedstate = tmp;
2381
2382 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2538 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2383 b43_write32(dev, B43_MMIO_MACCTL, 2539 b43_write32(dev, B43_MMIO_MACCTL,
2384 b43_read32(dev, B43_MMIO_MACCTL) 2540 b43_read32(dev, B43_MMIO_MACCTL)
@@ -2420,7 +2576,8 @@ static void b43_adjust_opmode(struct b43_wldev *dev)
2420 ctl &= ~B43_MACCTL_BEACPROMISC; 2576 ctl &= ~B43_MACCTL_BEACPROMISC;
2421 ctl |= B43_MACCTL_INFRA; 2577 ctl |= B43_MACCTL_INFRA;
2422 2578
2423 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2579 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP) ||
2580 b43_is_mode(wl, IEEE80211_IF_TYPE_MESH_POINT))
2424 ctl |= B43_MACCTL_AP; 2581 ctl |= B43_MACCTL_AP;
2425 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS)) 2582 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2426 ctl &= ~B43_MACCTL_INFRA; 2583 ctl &= ~B43_MACCTL_INFRA;
@@ -2534,6 +2691,7 @@ static void b43_chip_exit(struct b43_wldev *dev)
2534{ 2691{
2535 b43_radio_turn_off(dev, 1); 2692 b43_radio_turn_off(dev, 1);
2536 b43_gpio_cleanup(dev); 2693 b43_gpio_cleanup(dev);
2694 b43_lo_g_cleanup(dev);
2537 /* firmware is released later */ 2695 /* firmware is released later */
2538} 2696}
2539 2697
@@ -2640,28 +2798,12 @@ err_gpio_clean:
2640 return err; 2798 return err;
2641} 2799}
2642 2800
2643static void b43_periodic_every120sec(struct b43_wldev *dev)
2644{
2645 struct b43_phy *phy = &dev->phy;
2646
2647 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2648 return;
2649
2650 b43_mac_suspend(dev);
2651 b43_lo_g_measure(dev);
2652 b43_mac_enable(dev);
2653 if (b43_has_hardware_pctl(phy))
2654 b43_lo_g_ctl_mark_all_unused(dev);
2655}
2656
2657static void b43_periodic_every60sec(struct b43_wldev *dev) 2801static void b43_periodic_every60sec(struct b43_wldev *dev)
2658{ 2802{
2659 struct b43_phy *phy = &dev->phy; 2803 struct b43_phy *phy = &dev->phy;
2660 2804
2661 if (phy->type != B43_PHYTYPE_G) 2805 if (phy->type != B43_PHYTYPE_G)
2662 return; 2806 return;
2663 if (!b43_has_hardware_pctl(phy))
2664 b43_lo_g_ctl_mark_all_unused(dev);
2665 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) { 2807 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2666 b43_mac_suspend(dev); 2808 b43_mac_suspend(dev);
2667 b43_calc_nrssi_slope(dev); 2809 b43_calc_nrssi_slope(dev);
@@ -2688,6 +2830,21 @@ static void b43_periodic_every30sec(struct b43_wldev *dev)
2688static void b43_periodic_every15sec(struct b43_wldev *dev) 2830static void b43_periodic_every15sec(struct b43_wldev *dev)
2689{ 2831{
2690 struct b43_phy *phy = &dev->phy; 2832 struct b43_phy *phy = &dev->phy;
2833 u16 wdr;
2834
2835 if (dev->fw.opensource) {
2836 /* Check if the firmware is still alive.
2837 * It will reset the watchdog counter to 0 in its idle loop. */
2838 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2839 if (unlikely(wdr)) {
2840 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2841 b43_controller_restart(dev, "Firmware watchdog");
2842 return;
2843 } else {
2844 b43_shm_write16(dev, B43_SHM_SCRATCH,
2845 B43_WATCHDOG_REG, 1);
2846 }
2847 }
2691 2848
2692 if (phy->type == B43_PHYTYPE_G) { 2849 if (phy->type == B43_PHYTYPE_G) {
2693 //TODO: update_aci_moving_average 2850 //TODO: update_aci_moving_average
@@ -2713,6 +2870,7 @@ static void b43_periodic_every15sec(struct b43_wldev *dev)
2713 } 2870 }
2714 } 2871 }
2715 b43_phy_xmitpower(dev); //FIXME: unless scanning? 2872 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2873 b43_lo_g_maintanance_work(dev);
2716 //TODO for APHY (temperature?) 2874 //TODO for APHY (temperature?)
2717 2875
2718 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 2876 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
@@ -2724,8 +2882,6 @@ static void do_periodic_work(struct b43_wldev *dev)
2724 unsigned int state; 2882 unsigned int state;
2725 2883
2726 state = dev->periodic_state; 2884 state = dev->periodic_state;
2727 if (state % 8 == 0)
2728 b43_periodic_every120sec(dev);
2729 if (state % 4 == 0) 2885 if (state % 4 == 0)
2730 b43_periodic_every60sec(dev); 2886 b43_periodic_every60sec(dev);
2731 if (state % 2 == 0) 2887 if (state % 2 == 0)
@@ -2873,8 +3029,7 @@ static int b43_rng_init(struct b43_wl *wl)
2873} 3029}
2874 3030
2875static int b43_op_tx(struct ieee80211_hw *hw, 3031static int b43_op_tx(struct ieee80211_hw *hw,
2876 struct sk_buff *skb, 3032 struct sk_buff *skb)
2877 struct ieee80211_tx_control *ctl)
2878{ 3033{
2879 struct b43_wl *wl = hw_to_b43_wl(hw); 3034 struct b43_wl *wl = hw_to_b43_wl(hw);
2880 struct b43_wldev *dev = wl->current_dev; 3035 struct b43_wldev *dev = wl->current_dev;
@@ -2895,9 +3050,9 @@ static int b43_op_tx(struct ieee80211_hw *hw,
2895 err = -ENODEV; 3050 err = -ENODEV;
2896 if (likely(b43_status(dev) >= B43_STAT_STARTED)) { 3051 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2897 if (b43_using_pio_transfers(dev)) 3052 if (b43_using_pio_transfers(dev))
2898 err = b43_pio_tx(dev, skb, ctl); 3053 err = b43_pio_tx(dev, skb);
2899 else 3054 else
2900 err = b43_dma_tx(dev, skb, ctl); 3055 err = b43_dma_tx(dev, skb);
2901 } 3056 }
2902 3057
2903 read_unlock_irqrestore(&wl->tx_lock, flags); 3058 read_unlock_irqrestore(&wl->tx_lock, flags);
@@ -2918,53 +3073,20 @@ static void b43_qos_params_upload(struct b43_wldev *dev,
2918 u16 shm_offset) 3073 u16 shm_offset)
2919{ 3074{
2920 u16 params[B43_NR_QOSPARAMS]; 3075 u16 params[B43_NR_QOSPARAMS];
2921 int cw_min, cw_max, aifs, bslots, tmp; 3076 int bslots, tmp;
2922 unsigned int i; 3077 unsigned int i;
2923 3078
2924 const u16 aCWmin = 0x0001; 3079 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
2925 const u16 aCWmax = 0x03FF;
2926
2927 /* Calculate the default values for the parameters, if needed. */
2928 switch (shm_offset) {
2929 case B43_QOS_VOICE:
2930 aifs = (p->aifs == -1) ? 2 : p->aifs;
2931 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min;
2932 cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max;
2933 break;
2934 case B43_QOS_VIDEO:
2935 aifs = (p->aifs == -1) ? 2 : p->aifs;
2936 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min;
2937 cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max;
2938 break;
2939 case B43_QOS_BESTEFFORT:
2940 aifs = (p->aifs == -1) ? 3 : p->aifs;
2941 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2942 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2943 break;
2944 case B43_QOS_BACKGROUND:
2945 aifs = (p->aifs == -1) ? 7 : p->aifs;
2946 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2947 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2948 break;
2949 default:
2950 B43_WARN_ON(1);
2951 return;
2952 }
2953 if (cw_min <= 0)
2954 cw_min = aCWmin;
2955 if (cw_max <= 0)
2956 cw_max = aCWmin;
2957 bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min;
2958 3080
2959 memset(&params, 0, sizeof(params)); 3081 memset(&params, 0, sizeof(params));
2960 3082
2961 params[B43_QOSPARAM_TXOP] = p->txop * 32; 3083 params[B43_QOSPARAM_TXOP] = p->txop * 32;
2962 params[B43_QOSPARAM_CWMIN] = cw_min; 3084 params[B43_QOSPARAM_CWMIN] = p->cw_min;
2963 params[B43_QOSPARAM_CWMAX] = cw_max; 3085 params[B43_QOSPARAM_CWMAX] = p->cw_max;
2964 params[B43_QOSPARAM_CWCUR] = cw_min; 3086 params[B43_QOSPARAM_CWCUR] = p->cw_min;
2965 params[B43_QOSPARAM_AIFS] = aifs; 3087 params[B43_QOSPARAM_AIFS] = p->aifs;
2966 params[B43_QOSPARAM_BSLOTS] = bslots; 3088 params[B43_QOSPARAM_BSLOTS] = bslots;
2967 params[B43_QOSPARAM_REGGAP] = bslots + aifs; 3089 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
2968 3090
2969 for (i = 0; i < ARRAY_SIZE(params); i++) { 3091 for (i = 0; i < ARRAY_SIZE(params); i++) {
2970 if (i == B43_QOSPARAM_STATUS) { 3092 if (i == B43_QOSPARAM_STATUS) {
@@ -3060,8 +3182,7 @@ static void b43_qos_update_work(struct work_struct *work)
3060 mutex_unlock(&wl->mutex); 3182 mutex_unlock(&wl->mutex);
3061} 3183}
3062 3184
3063static int b43_op_conf_tx(struct ieee80211_hw *hw, 3185static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3064 int _queue,
3065 const struct ieee80211_tx_queue_params *params) 3186 const struct ieee80211_tx_queue_params *params)
3066{ 3187{
3067 struct b43_wl *wl = hw_to_b43_wl(hw); 3188 struct b43_wl *wl = hw_to_b43_wl(hw);
@@ -3309,8 +3430,9 @@ static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3309 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx); 3430 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
3310 b43_set_rx_antenna(dev, antenna); 3431 b43_set_rx_antenna(dev, antenna);
3311 3432
3312 /* Update templates for AP mode. */ 3433 /* Update templates for AP/mesh mode. */
3313 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 3434 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP) ||
3435 b43_is_mode(wl, IEEE80211_IF_TYPE_MESH_POINT))
3314 b43_set_beacon_int(dev, conf->beacon_int); 3436 b43_set_beacon_int(dev, conf->beacon_int);
3315 3437
3316 if (!!conf->radio_enabled != phy->radio_on) { 3438 if (!!conf->radio_enabled != phy->radio_on) {
@@ -3361,6 +3483,13 @@ static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3361 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 3483 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3362 goto out_unlock; 3484 goto out_unlock;
3363 3485
3486 if (dev->fw.pcm_request_failed) {
3487 /* We don't have firmware for the crypto engine.
3488 * Must use software-crypto. */
3489 err = -EOPNOTSUPP;
3490 goto out_unlock;
3491 }
3492
3364 err = -EINVAL; 3493 err = -EINVAL;
3365 switch (key->alg) { 3494 switch (key->alg) {
3366 case ALG_WEP: 3495 case ALG_WEP:
@@ -3491,13 +3620,16 @@ static int b43_op_config_interface(struct ieee80211_hw *hw,
3491 else 3620 else
3492 memset(wl->bssid, 0, ETH_ALEN); 3621 memset(wl->bssid, 0, ETH_ALEN);
3493 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 3622 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3494 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) { 3623 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP) ||
3495 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP); 3624 b43_is_mode(wl, IEEE80211_IF_TYPE_MESH_POINT)) {
3496 b43_set_ssid(dev, conf->ssid, conf->ssid_len); 3625 B43_WARN_ON(vif->type != wl->if_type);
3497 if (conf->beacon) { 3626 if (conf->changed & IEEE80211_IFCC_SSID)
3498 b43_update_templates(wl, conf->beacon, 3627 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3499 conf->beacon_control); 3628 if (conf->changed & IEEE80211_IFCC_BEACON)
3500 } 3629 b43_update_templates(wl);
3630 } else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS)) {
3631 if (conf->changed & IEEE80211_IFCC_BEACON)
3632 b43_update_templates(wl);
3501 } 3633 }
3502 b43_write_mac_bssid_templates(dev); 3634 b43_write_mac_bssid_templates(dev);
3503 } 3635 }
@@ -3562,7 +3694,6 @@ static int b43_wireless_core_start(struct b43_wldev *dev)
3562 /* Start data flow (TX/RX). */ 3694 /* Start data flow (TX/RX). */
3563 b43_mac_enable(dev); 3695 b43_mac_enable(dev);
3564 b43_interrupt_enable(dev, dev->irq_savedstate); 3696 b43_interrupt_enable(dev, dev->irq_savedstate);
3565 ieee80211_start_queues(dev->wl->hw);
3566 3697
3567 /* Start maintainance work */ 3698 /* Start maintainance work */
3568 b43_periodic_tasks_setup(dev); 3699 b43_periodic_tasks_setup(dev);
@@ -3703,8 +3834,8 @@ static void setup_struct_phy_for_init(struct b43_wldev *dev,
3703 lo = phy->lo_control; 3834 lo = phy->lo_control;
3704 if (lo) { 3835 if (lo) {
3705 memset(lo, 0, sizeof(*(phy->lo_control))); 3836 memset(lo, 0, sizeof(*(phy->lo_control)));
3706 lo->rebuild = 1;
3707 lo->tx_bias = 0xFF; 3837 lo->tx_bias = 0xFF;
3838 INIT_LIST_HEAD(&lo->calib_list);
3708 } 3839 }
3709 phy->max_lb_gain = 0; 3840 phy->max_lb_gain = 0;
3710 phy->trsw_rx_gain = 0; 3841 phy->trsw_rx_gain = 0;
@@ -4035,6 +4166,7 @@ static int b43_op_add_interface(struct ieee80211_hw *hw,
4035 /* TODO: allow WDS/AP devices to coexist */ 4166 /* TODO: allow WDS/AP devices to coexist */
4036 4167
4037 if (conf->type != IEEE80211_IF_TYPE_AP && 4168 if (conf->type != IEEE80211_IF_TYPE_AP &&
4169 conf->type != IEEE80211_IF_TYPE_MESH_POINT &&
4038 conf->type != IEEE80211_IF_TYPE_STA && 4170 conf->type != IEEE80211_IF_TYPE_STA &&
4039 conf->type != IEEE80211_IF_TYPE_WDS && 4171 conf->type != IEEE80211_IF_TYPE_WDS &&
4040 conf->type != IEEE80211_IF_TYPE_IBSS) 4172 conf->type != IEEE80211_IF_TYPE_IBSS)
@@ -4185,33 +4317,10 @@ out_unlock:
4185static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set) 4317static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
4186{ 4318{
4187 struct b43_wl *wl = hw_to_b43_wl(hw); 4319 struct b43_wl *wl = hw_to_b43_wl(hw);
4188 struct sk_buff *beacon;
4189 unsigned long flags;
4190 struct ieee80211_tx_control txctl;
4191
4192 /* We could modify the existing beacon and set the aid bit in
4193 * the TIM field, but that would probably require resizing and
4194 * moving of data within the beacon template.
4195 * Simply request a new beacon and let mac80211 do the hard work. */
4196 beacon = ieee80211_beacon_get(hw, wl->vif, &txctl);
4197 if (unlikely(!beacon))
4198 return -ENOMEM;
4199 spin_lock_irqsave(&wl->irq_lock, flags);
4200 b43_update_templates(wl, beacon, &txctl);
4201 spin_unlock_irqrestore(&wl->irq_lock, flags);
4202
4203 return 0;
4204}
4205
4206static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
4207 struct sk_buff *beacon,
4208 struct ieee80211_tx_control *ctl)
4209{
4210 struct b43_wl *wl = hw_to_b43_wl(hw);
4211 unsigned long flags; 4320 unsigned long flags;
4212 4321
4213 spin_lock_irqsave(&wl->irq_lock, flags); 4322 spin_lock_irqsave(&wl->irq_lock, flags);
4214 b43_update_templates(wl, beacon, ctl); 4323 b43_update_templates(wl);
4215 spin_unlock_irqrestore(&wl->irq_lock, flags); 4324 spin_unlock_irqrestore(&wl->irq_lock, flags);
4216 4325
4217 return 0; 4326 return 0;
@@ -4242,7 +4351,6 @@ static const struct ieee80211_ops b43_hw_ops = {
4242 .stop = b43_op_stop, 4351 .stop = b43_op_stop,
4243 .set_retry_limit = b43_op_set_retry_limit, 4352 .set_retry_limit = b43_op_set_retry_limit,
4244 .set_tim = b43_op_beacon_set_tim, 4353 .set_tim = b43_op_beacon_set_tim,
4245 .beacon_update = b43_op_ibss_beacon_update,
4246 .sta_notify = b43_op_sta_notify, 4354 .sta_notify = b43_op_sta_notify,
4247}; 4355};
4248 4356
@@ -4538,10 +4646,10 @@ static int b43_wireless_init(struct ssb_device *dev)
4538 4646
4539 /* fill hw info */ 4647 /* fill hw info */
4540 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | 4648 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4541 IEEE80211_HW_RX_INCLUDES_FCS; 4649 IEEE80211_HW_RX_INCLUDES_FCS |
4542 hw->max_signal = 100; 4650 IEEE80211_HW_SIGNAL_DBM |
4543 hw->max_rssi = -110; 4651 IEEE80211_HW_NOISE_DBM;
4544 hw->max_noise = -110; 4652
4545 hw->queues = b43_modparam_qos ? 4 : 1; 4653 hw->queues = b43_modparam_qos ? 4 : 1;
4546 SET_IEEE80211_DEV(hw, dev->dev); 4654 SET_IEEE80211_DEV(hw, dev->dev);
4547 if (is_valid_ether_addr(sprom->et1mac)) 4655 if (is_valid_ether_addr(sprom->et1mac))
diff --git a/drivers/net/wireless/b43/main.h b/drivers/net/wireless/b43/main.h
index 5230aeca78bf..f871a252cb55 100644
--- a/drivers/net/wireless/b43/main.h
+++ b/drivers/net/wireless/b43/main.h
@@ -95,9 +95,13 @@ void b43_tsf_read(struct b43_wldev *dev, u64 * tsf);
95void b43_tsf_write(struct b43_wldev *dev, u64 tsf); 95void b43_tsf_write(struct b43_wldev *dev, u64 tsf);
96 96
97u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset); 97u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset);
98u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset);
98u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset); 99u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset);
100u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset);
99void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value); 101void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value);
102void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value);
100void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value); 103void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value);
104void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value);
101 105
102u64 b43_hf_read(struct b43_wldev *dev); 106u64 b43_hf_read(struct b43_wldev *dev);
103void b43_hf_write(struct b43_wldev *dev, u64 value); 107void b43_hf_write(struct b43_wldev *dev, u64 value);
@@ -114,4 +118,7 @@ void b43_controller_restart(struct b43_wldev *dev, const char *reason);
114#define B43_PS_ASLEEP (1 << 3) /* Force device asleep */ 118#define B43_PS_ASLEEP (1 << 3) /* Force device asleep */
115void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags); 119void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags);
116 120
121void b43_mac_suspend(struct b43_wldev *dev);
122void b43_mac_enable(struct b43_wldev *dev);
123
117#endif /* B43_MAIN_H_ */ 124#endif /* B43_MAIN_H_ */
diff --git a/drivers/net/wireless/b43/nphy.c b/drivers/net/wireless/b43/nphy.c
index 8695eb223476..644eed993bea 100644
--- a/drivers/net/wireless/b43/nphy.c
+++ b/drivers/net/wireless/b43/nphy.c
@@ -29,8 +29,6 @@
29#include "nphy.h" 29#include "nphy.h"
30#include "tables_nphy.h" 30#include "tables_nphy.h"
31 31
32#include <linux/delay.h>
33
34 32
35void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna) 33void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
36{//TODO 34{//TODO
diff --git a/drivers/net/wireless/b43/phy.c b/drivers/net/wireless/b43/phy.c
index de024dc03718..305d4cd6fd03 100644
--- a/drivers/net/wireless/b43/phy.c
+++ b/drivers/net/wireless/b43/phy.c
@@ -28,6 +28,7 @@
28#include <linux/delay.h> 28#include <linux/delay.h>
29#include <linux/io.h> 29#include <linux/io.h>
30#include <linux/types.h> 30#include <linux/types.h>
31#include <linux/bitrev.h>
31 32
32#include "b43.h" 33#include "b43.h"
33#include "phy.h" 34#include "phy.h"
@@ -83,25 +84,9 @@ const u8 b43_radio_channel_codes_bg[] = {
83 72, 84, 84 72, 84,
84}; 85};
85 86
87#define bitrev4(tmp) (bitrev8(tmp) >> 4)
86static void b43_phy_initg(struct b43_wldev *dev); 88static void b43_phy_initg(struct b43_wldev *dev);
87 89
88/* Reverse the bits of a 4bit value.
89 * Example: 1101 is flipped 1011
90 */
91static u16 flip_4bit(u16 value)
92{
93 u16 flipped = 0x0000;
94
95 B43_WARN_ON(value & ~0x000F);
96
97 flipped |= (value & 0x0001) << 3;
98 flipped |= (value & 0x0002) << 1;
99 flipped |= (value & 0x0004) >> 1;
100 flipped |= (value & 0x0008) >> 3;
101
102 return flipped;
103}
104
105static void generate_rfatt_list(struct b43_wldev *dev, 90static void generate_rfatt_list(struct b43_wldev *dev,
106 struct b43_rfatt_list *list) 91 struct b43_rfatt_list *list)
107{ 92{
@@ -145,8 +130,7 @@ static void generate_rfatt_list(struct b43_wldev *dev,
145 {.att = 9,.with_padmix = 1,}, 130 {.att = 9,.with_padmix = 1,},
146 }; 131 };
147 132
148 if ((phy->type == B43_PHYTYPE_A && phy->rev < 5) || 133 if (!b43_has_hardware_pctl(phy)) {
149 (phy->type == B43_PHYTYPE_G && phy->rev < 6)) {
150 /* Software pctl */ 134 /* Software pctl */
151 list->list = rfatt_0; 135 list->list = rfatt_0;
152 list->len = ARRAY_SIZE(rfatt_0); 136 list->len = ARRAY_SIZE(rfatt_0);
@@ -158,7 +142,7 @@ static void generate_rfatt_list(struct b43_wldev *dev,
158 /* Hardware pctl */ 142 /* Hardware pctl */
159 list->list = rfatt_1; 143 list->list = rfatt_1;
160 list->len = ARRAY_SIZE(rfatt_1); 144 list->len = ARRAY_SIZE(rfatt_1);
161 list->min_val = 2; 145 list->min_val = 0;
162 list->max_val = 14; 146 list->max_val = 14;
163 return; 147 return;
164 } 148 }
@@ -346,6 +330,7 @@ void b43_set_txpower_g(struct b43_wldev *dev,
346 /* Save the values for later */ 330 /* Save the values for later */
347 phy->tx_control = tx_control; 331 phy->tx_control = tx_control;
348 memcpy(&phy->rfatt, rfatt, sizeof(*rfatt)); 332 memcpy(&phy->rfatt, rfatt, sizeof(*rfatt));
333 phy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX);
349 memcpy(&phy->bbatt, bbatt, sizeof(*bbatt)); 334 memcpy(&phy->bbatt, bbatt, sizeof(*bbatt));
350 335
351 if (b43_debug(dev, B43_DBG_XMITPOWER)) { 336 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
@@ -559,11 +544,6 @@ static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
559 u16 tmp; 544 u16 tmp;
560 u8 rf, bb; 545 u8 rf, bb;
561 546
562 if (!lo->lo_measured) {
563 b43_phy_write(dev, 0x3FF, 0);
564 return;
565 }
566
567 for (rf = 0; rf < lo->rfatt_list.len; rf++) { 547 for (rf = 0; rf < lo->rfatt_list.len; rf++) {
568 for (bb = 0; bb < lo->bbatt_list.len; bb++) { 548 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
569 if (nr_written >= 0x40) 549 if (nr_written >= 0x40)
@@ -581,42 +561,6 @@ static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
581 } 561 }
582} 562}
583 563
584/* GPHY_DC_Lookup_Table */
585void b43_gphy_dc_lt_init(struct b43_wldev *dev)
586{
587 struct b43_phy *phy = &dev->phy;
588 struct b43_txpower_lo_control *lo = phy->lo_control;
589 struct b43_loctl *loctl0;
590 struct b43_loctl *loctl1;
591 int i;
592 int rf_offset, bb_offset;
593 u16 tmp;
594
595 for (i = 0; i < lo->rfatt_list.len + lo->bbatt_list.len; i += 2) {
596 rf_offset = i / lo->rfatt_list.len;
597 bb_offset = i % lo->rfatt_list.len;
598
599 loctl0 = b43_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
600 &lo->bbatt_list.list[bb_offset]);
601 if (i + 1 < lo->rfatt_list.len * lo->bbatt_list.len) {
602 rf_offset = (i + 1) / lo->rfatt_list.len;
603 bb_offset = (i + 1) % lo->rfatt_list.len;
604
605 loctl1 =
606 b43_get_lo_g_ctl(dev,
607 &lo->rfatt_list.list[rf_offset],
608 &lo->bbatt_list.list[bb_offset]);
609 } else
610 loctl1 = loctl0;
611
612 tmp = ((u16) loctl0->q & 0xF);
613 tmp |= ((u16) loctl0->i & 0xF) << 4;
614 tmp |= ((u16) loctl1->q & 0xF) << 8;
615 tmp |= ((u16) loctl1->i & 0xF) << 12; //FIXME?
616 b43_phy_write(dev, 0x3A0 + (i / 2), tmp);
617 }
618}
619
620static void hardware_pctl_init_aphy(struct b43_wldev *dev) 564static void hardware_pctl_init_aphy(struct b43_wldev *dev)
621{ 565{
622 //TODO 566 //TODO
@@ -643,7 +587,7 @@ static void hardware_pctl_init_gphy(struct b43_wldev *dev)
643 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) 587 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
644 & 0xFFBF); 588 & 0xFFBF);
645 589
646 b43_gphy_dc_lt_init(dev); 590 b43_gphy_dc_lt_init(dev, 1);
647} 591}
648 592
649/* HardwarePowerControl init for A and G PHY */ 593/* HardwarePowerControl init for A and G PHY */
@@ -931,109 +875,6 @@ static void b43_phy_inita(struct b43_wldev *dev)
931 } 875 }
932} 876}
933 877
934static void b43_phy_initb2(struct b43_wldev *dev)
935{
936 struct b43_phy *phy = &dev->phy;
937 u16 offset, val;
938
939 b43_write16(dev, 0x03EC, 0x3F22);
940 b43_phy_write(dev, 0x0020, 0x301C);
941 b43_phy_write(dev, 0x0026, 0x0000);
942 b43_phy_write(dev, 0x0030, 0x00C6);
943 b43_phy_write(dev, 0x0088, 0x3E00);
944 val = 0x3C3D;
945 for (offset = 0x0089; offset < 0x00A7; offset++) {
946 b43_phy_write(dev, offset, val);
947 val -= 0x0202;
948 }
949 b43_phy_write(dev, 0x03E4, 0x3000);
950 b43_radio_selectchannel(dev, phy->channel, 0);
951 if (phy->radio_ver != 0x2050) {
952 b43_radio_write16(dev, 0x0075, 0x0080);
953 b43_radio_write16(dev, 0x0079, 0x0081);
954 }
955 b43_radio_write16(dev, 0x0050, 0x0020);
956 b43_radio_write16(dev, 0x0050, 0x0023);
957 if (phy->radio_ver == 0x2050) {
958 b43_radio_write16(dev, 0x0050, 0x0020);
959 b43_radio_write16(dev, 0x005A, 0x0070);
960 b43_radio_write16(dev, 0x005B, 0x007B);
961 b43_radio_write16(dev, 0x005C, 0x00B0);
962 b43_radio_write16(dev, 0x007A, 0x000F);
963 b43_phy_write(dev, 0x0038, 0x0677);
964 b43_radio_init2050(dev);
965 }
966 b43_phy_write(dev, 0x0014, 0x0080);
967 b43_phy_write(dev, 0x0032, 0x00CA);
968 b43_phy_write(dev, 0x0032, 0x00CC);
969 b43_phy_write(dev, 0x0035, 0x07C2);
970 b43_lo_b_measure(dev);
971 b43_phy_write(dev, 0x0026, 0xCC00);
972 if (phy->radio_ver != 0x2050)
973 b43_phy_write(dev, 0x0026, 0xCE00);
974 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1000);
975 b43_phy_write(dev, 0x002A, 0x88A3);
976 if (phy->radio_ver != 0x2050)
977 b43_phy_write(dev, 0x002A, 0x88C2);
978 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
979 b43_phy_init_pctl(dev);
980}
981
982static void b43_phy_initb4(struct b43_wldev *dev)
983{
984 struct b43_phy *phy = &dev->phy;
985 u16 offset, val;
986
987 b43_write16(dev, 0x03EC, 0x3F22);
988 b43_phy_write(dev, 0x0020, 0x301C);
989 b43_phy_write(dev, 0x0026, 0x0000);
990 b43_phy_write(dev, 0x0030, 0x00C6);
991 b43_phy_write(dev, 0x0088, 0x3E00);
992 val = 0x3C3D;
993 for (offset = 0x0089; offset < 0x00A7; offset++) {
994 b43_phy_write(dev, offset, val);
995 val -= 0x0202;
996 }
997 b43_phy_write(dev, 0x03E4, 0x3000);
998 b43_radio_selectchannel(dev, phy->channel, 0);
999 if (phy->radio_ver != 0x2050) {
1000 b43_radio_write16(dev, 0x0075, 0x0080);
1001 b43_radio_write16(dev, 0x0079, 0x0081);
1002 }
1003 b43_radio_write16(dev, 0x0050, 0x0020);
1004 b43_radio_write16(dev, 0x0050, 0x0023);
1005 if (phy->radio_ver == 0x2050) {
1006 b43_radio_write16(dev, 0x0050, 0x0020);
1007 b43_radio_write16(dev, 0x005A, 0x0070);
1008 b43_radio_write16(dev, 0x005B, 0x007B);
1009 b43_radio_write16(dev, 0x005C, 0x00B0);
1010 b43_radio_write16(dev, 0x007A, 0x000F);
1011 b43_phy_write(dev, 0x0038, 0x0677);
1012 b43_radio_init2050(dev);
1013 }
1014 b43_phy_write(dev, 0x0014, 0x0080);
1015 b43_phy_write(dev, 0x0032, 0x00CA);
1016 if (phy->radio_ver == 0x2050)
1017 b43_phy_write(dev, 0x0032, 0x00E0);
1018 b43_phy_write(dev, 0x0035, 0x07C2);
1019
1020 b43_lo_b_measure(dev);
1021
1022 b43_phy_write(dev, 0x0026, 0xCC00);
1023 if (phy->radio_ver == 0x2050)
1024 b43_phy_write(dev, 0x0026, 0xCE00);
1025 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1100);
1026 b43_phy_write(dev, 0x002A, 0x88A3);
1027 if (phy->radio_ver == 0x2050)
1028 b43_phy_write(dev, 0x002A, 0x88C2);
1029 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1030 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
1031 b43_calc_nrssi_slope(dev);
1032 b43_calc_nrssi_threshold(dev);
1033 }
1034 b43_phy_init_pctl(dev);
1035}
1036
1037static void b43_phy_initb5(struct b43_wldev *dev) 878static void b43_phy_initb5(struct b43_wldev *dev)
1038{ 879{
1039 struct ssb_bus *bus = dev->dev->bus; 880 struct ssb_bus *bus = dev->dev->bus;
@@ -1259,19 +1100,9 @@ static void b43_phy_initb6(struct b43_wldev *dev)
1259 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0) 1100 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1260 | 0x0004); 1101 | 0x0004);
1261 } 1102 }
1262 if (phy->type == B43_PHYTYPE_B) { 1103 if (phy->type == B43_PHYTYPE_B)
1263 b43_write16(dev, 0x03E6, 0x8140); 1104 B43_WARN_ON(1);
1264 b43_phy_write(dev, 0x0016, 0x0410); 1105 else if (phy->type == B43_PHYTYPE_G)
1265 b43_phy_write(dev, 0x0017, 0x0820);
1266 b43_phy_write(dev, 0x0062, 0x0007);
1267 b43_radio_init2050(dev);
1268 b43_lo_g_measure(dev);
1269 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
1270 b43_calc_nrssi_slope(dev);
1271 b43_calc_nrssi_threshold(dev);
1272 }
1273 b43_phy_init_pctl(dev);
1274 } else if (phy->type == B43_PHYTYPE_G)
1275 b43_write16(dev, 0x03E6, 0x0); 1106 b43_write16(dev, 0x03E6, 0x0);
1276} 1107}
1277 1108
@@ -1534,34 +1365,31 @@ static void b43_phy_initg(struct b43_wldev *dev)
1534 else 1365 else
1535 b43_radio_write16(dev, 0x0078, phy->initval); 1366 b43_radio_write16(dev, 0x0078, phy->initval);
1536 } 1367 }
1537 if (phy->lo_control->tx_bias == 0xFF) { 1368 b43_lo_g_init(dev);
1538 b43_lo_g_measure(dev); 1369 if (has_tx_magnification(phy)) {
1370 b43_radio_write16(dev, 0x52,
1371 (b43_radio_read16(dev, 0x52) & 0xFF00)
1372 | phy->lo_control->tx_bias | phy->
1373 lo_control->tx_magn);
1539 } else { 1374 } else {
1540 if (has_tx_magnification(phy)) { 1375 b43_radio_write16(dev, 0x52,
1541 b43_radio_write16(dev, 0x52, 1376 (b43_radio_read16(dev, 0x52) & 0xFFF0)
1542 (b43_radio_read16(dev, 0x52) & 0xFF00) 1377 | phy->lo_control->tx_bias);
1543 | phy->lo_control->tx_bias | phy->
1544 lo_control->tx_magn);
1545 } else {
1546 b43_radio_write16(dev, 0x52,
1547 (b43_radio_read16(dev, 0x52) & 0xFFF0)
1548 | phy->lo_control->tx_bias);
1549 }
1550 if (phy->rev >= 6) {
1551 b43_phy_write(dev, B43_PHY_CCK(0x36),
1552 (b43_phy_read(dev, B43_PHY_CCK(0x36))
1553 & 0x0FFF) | (phy->lo_control->
1554 tx_bias << 12));
1555 }
1556 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
1557 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
1558 else
1559 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
1560 if (phy->rev < 2)
1561 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
1562 else
1563 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
1564 } 1378 }
1379 if (phy->rev >= 6) {
1380 b43_phy_write(dev, B43_PHY_CCK(0x36),
1381 (b43_phy_read(dev, B43_PHY_CCK(0x36))
1382 & 0x0FFF) | (phy->lo_control->
1383 tx_bias << 12));
1384 }
1385 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
1386 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
1387 else
1388 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
1389 if (phy->rev < 2)
1390 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
1391 else
1392 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
1565 if (phy->gmode || phy->rev >= 2) { 1393 if (phy->gmode || phy->rev >= 2) {
1566 b43_lo_g_adjust(dev); 1394 b43_lo_g_adjust(dev);
1567 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078); 1395 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
@@ -1572,7 +1400,7 @@ static void b43_phy_initg(struct b43_wldev *dev)
1572 * the value 0x7FFFFFFF here. I think that is some weird 1400 * the value 0x7FFFFFFF here. I think that is some weird
1573 * compiler optimization in the original driver. 1401 * compiler optimization in the original driver.
1574 * Essentially, what we do here is resetting all NRSSI LT 1402 * Essentially, what we do here is resetting all NRSSI LT
1575 * entries to -32 (see the limit_value() in nrssi_hw_update()) 1403 * entries to -32 (see the clamp_val() in nrssi_hw_update())
1576 */ 1404 */
1577 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME? 1405 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME?
1578 b43_calc_nrssi_threshold(dev); 1406 b43_calc_nrssi_threshold(dev);
@@ -1634,13 +1462,13 @@ static s8 b43_phy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
1634 switch (phy->type) { 1462 switch (phy->type) {
1635 case B43_PHYTYPE_A: 1463 case B43_PHYTYPE_A:
1636 tmp += 0x80; 1464 tmp += 0x80;
1637 tmp = limit_value(tmp, 0x00, 0xFF); 1465 tmp = clamp_val(tmp, 0x00, 0xFF);
1638 dbm = phy->tssi2dbm[tmp]; 1466 dbm = phy->tssi2dbm[tmp];
1639 //TODO: There's a FIXME on the specs 1467 //TODO: There's a FIXME on the specs
1640 break; 1468 break;
1641 case B43_PHYTYPE_B: 1469 case B43_PHYTYPE_B:
1642 case B43_PHYTYPE_G: 1470 case B43_PHYTYPE_G:
1643 tmp = limit_value(tmp, 0x00, 0x3F); 1471 tmp = clamp_val(tmp, 0x00, 0x3F);
1644 dbm = phy->tssi2dbm[tmp]; 1472 dbm = phy->tssi2dbm[tmp];
1645 break; 1473 break;
1646 default: 1474 default:
@@ -1699,8 +1527,8 @@ void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
1699 break; 1527 break;
1700 } 1528 }
1701 1529
1702 *_rfatt = limit_value(rfatt, rf_min, rf_max); 1530 *_rfatt = clamp_val(rfatt, rf_min, rf_max);
1703 *_bbatt = limit_value(bbatt, bb_min, bb_max); 1531 *_bbatt = clamp_val(bbatt, bb_min, bb_max);
1704} 1532}
1705 1533
1706/* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */ 1534/* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
@@ -1795,7 +1623,7 @@ void b43_phy_xmitpower(struct b43_wldev *dev)
1795 /* Get desired power (in Q5.2) */ 1623 /* Get desired power (in Q5.2) */
1796 desired_pwr = INT_TO_Q52(phy->power_level); 1624 desired_pwr = INT_TO_Q52(phy->power_level);
1797 /* And limit it. max_pwr already is Q5.2 */ 1625 /* And limit it. max_pwr already is Q5.2 */
1798 desired_pwr = limit_value(desired_pwr, 0, max_pwr); 1626 desired_pwr = clamp_val(desired_pwr, 0, max_pwr);
1799 if (b43_debug(dev, B43_DBG_XMITPOWER)) { 1627 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
1800 b43dbg(dev->wl, 1628 b43dbg(dev->wl,
1801 "Current TX power output: " Q52_FMT 1629 "Current TX power output: " Q52_FMT
@@ -1821,10 +1649,8 @@ void b43_phy_xmitpower(struct b43_wldev *dev)
1821 bbatt_delta -= 4 * rfatt_delta; 1649 bbatt_delta -= 4 * rfatt_delta;
1822 1650
1823 /* So do we finally need to adjust something? */ 1651 /* So do we finally need to adjust something? */
1824 if ((rfatt_delta == 0) && (bbatt_delta == 0)) { 1652 if ((rfatt_delta == 0) && (bbatt_delta == 0))
1825 b43_lo_g_ctl_mark_cur_used(dev);
1826 return; 1653 return;
1827 }
1828 1654
1829 /* Calculate the new attenuation values. */ 1655 /* Calculate the new attenuation values. */
1830 bbatt = phy->bbatt.att; 1656 bbatt = phy->bbatt.att;
@@ -1870,7 +1696,6 @@ void b43_phy_xmitpower(struct b43_wldev *dev)
1870 b43_radio_lock(dev); 1696 b43_radio_lock(dev);
1871 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, 1697 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt,
1872 phy->tx_control); 1698 phy->tx_control);
1873 b43_lo_g_ctl_mark_cur_used(dev);
1874 b43_radio_unlock(dev); 1699 b43_radio_unlock(dev);
1875 b43_phy_unlock(dev); 1700 b43_phy_unlock(dev);
1876 break; 1701 break;
@@ -1908,7 +1733,7 @@ static inline
1908 f = q; 1733 f = q;
1909 i++; 1734 i++;
1910 } while (delta >= 2); 1735 } while (delta >= 2);
1911 entry[index] = limit_value(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128); 1736 entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
1912 return 0; 1737 return 0;
1913} 1738}
1914 1739
@@ -2007,24 +1832,6 @@ int b43_phy_init(struct b43_wldev *dev)
2007 else 1832 else
2008 unsupported = 1; 1833 unsupported = 1;
2009 break; 1834 break;
2010 case B43_PHYTYPE_B:
2011 switch (phy->rev) {
2012 case 2:
2013 b43_phy_initb2(dev);
2014 break;
2015 case 4:
2016 b43_phy_initb4(dev);
2017 break;
2018 case 5:
2019 b43_phy_initb5(dev);
2020 break;
2021 case 6:
2022 b43_phy_initb6(dev);
2023 break;
2024 default:
2025 unsupported = 1;
2026 }
2027 break;
2028 case B43_PHYTYPE_G: 1835 case B43_PHYTYPE_G:
2029 b43_phy_initg(dev); 1836 b43_phy_initg(dev);
2030 break; 1837 break;
@@ -2452,7 +2259,7 @@ void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
2452 for (i = 0; i < 64; i++) { 2259 for (i = 0; i < 64; i++) {
2453 tmp = b43_nrssi_hw_read(dev, i); 2260 tmp = b43_nrssi_hw_read(dev, i);
2454 tmp -= val; 2261 tmp -= val;
2455 tmp = limit_value(tmp, -32, 31); 2262 tmp = clamp_val(tmp, -32, 31);
2456 b43_nrssi_hw_write(dev, i, tmp); 2263 b43_nrssi_hw_write(dev, i, tmp);
2457 } 2264 }
2458} 2265}
@@ -2469,7 +2276,7 @@ void b43_nrssi_mem_update(struct b43_wldev *dev)
2469 tmp = (i - delta) * phy->nrssislope; 2276 tmp = (i - delta) * phy->nrssislope;
2470 tmp /= 0x10000; 2277 tmp /= 0x10000;
2471 tmp += 0x3A; 2278 tmp += 0x3A;
2472 tmp = limit_value(tmp, 0, 0x3F); 2279 tmp = clamp_val(tmp, 0, 0x3F);
2473 phy->nrssi_lt[i] = tmp; 2280 phy->nrssi_lt[i] = tmp;
2474 } 2281 }
2475} 2282}
@@ -2906,7 +2713,7 @@ void b43_calc_nrssi_threshold(struct b43_wldev *dev)
2906 } else 2713 } else
2907 threshold = phy->nrssi[1] - 5; 2714 threshold = phy->nrssi[1] - 5;
2908 2715
2909 threshold = limit_value(threshold, 0, 0x3E); 2716 threshold = clamp_val(threshold, 0, 0x3E);
2910 b43_phy_read(dev, 0x0020); /* dummy read */ 2717 b43_phy_read(dev, 0x0020); /* dummy read */
2911 b43_phy_write(dev, 0x0020, 2718 b43_phy_write(dev, 0x0020,
2912 (((u16) threshold) << 8) | 0x001C); 2719 (((u16) threshold) << 8) | 0x001C);
@@ -2957,7 +2764,7 @@ void b43_calc_nrssi_threshold(struct b43_wldev *dev)
2957 else 2764 else
2958 a += 32; 2765 a += 32;
2959 a = a >> 6; 2766 a = a >> 6;
2960 a = limit_value(a, -31, 31); 2767 a = clamp_val(a, -31, 31);
2961 2768
2962 b = b * (phy->nrssi[1] - phy->nrssi[0]); 2769 b = b * (phy->nrssi[1] - phy->nrssi[0]);
2963 b += (phy->nrssi[0] << 6); 2770 b += (phy->nrssi[0] << 6);
@@ -2966,7 +2773,7 @@ void b43_calc_nrssi_threshold(struct b43_wldev *dev)
2966 else 2773 else
2967 b += 32; 2774 b += 32;
2968 b = b >> 6; 2775 b = b >> 6;
2969 b = limit_value(b, -31, 31); 2776 b = clamp_val(b, -31, 31);
2970 2777
2971 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000; 2778 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
2972 tmp_u16 |= ((u32) b & 0x0000003F); 2779 tmp_u16 |= ((u32) b & 0x0000003F);
@@ -3069,13 +2876,13 @@ b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
3069 } 2876 }
3070 radio_stacksave(0x0078); 2877 radio_stacksave(0x0078);
3071 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E); 2878 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
3072 flipped = flip_4bit(tmp); 2879 B43_WARN_ON(tmp > 15);
2880 flipped = bitrev4(tmp);
3073 if (flipped < 10 && flipped >= 8) 2881 if (flipped < 10 && flipped >= 8)
3074 flipped = 7; 2882 flipped = 7;
3075 else if (flipped >= 10) 2883 else if (flipped >= 10)
3076 flipped -= 3; 2884 flipped -= 3;
3077 flipped = flip_4bit(flipped); 2885 flipped = (bitrev4(flipped) << 1) | 0x0020;
3078 flipped = (flipped << 1) | 0x0020;
3079 b43_radio_write16(dev, 0x0078, flipped); 2886 b43_radio_write16(dev, 0x0078, flipped);
3080 2887
3081 b43_calc_nrssi_threshold(dev); 2888 b43_calc_nrssi_threshold(dev);
@@ -3708,7 +3515,7 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
3708 tmp1 >>= 9; 3515 tmp1 >>= 9;
3709 3516
3710 for (i = 0; i < 16; i++) { 3517 for (i = 0; i < 16; i++) {
3711 radio78 = ((flip_4bit(i) << 1) | 0x20); 3518 radio78 = (bitrev4(i) << 1) | 0x0020;
3712 b43_radio_write16(dev, 0x78, radio78); 3519 b43_radio_write16(dev, 0x78, radio78);
3713 udelay(10); 3520 udelay(10);
3714 for (j = 0; j < 16; j++) { 3521 for (j = 0; j < 16; j++) {
diff --git a/drivers/net/wireless/b43/phy.h b/drivers/net/wireless/b43/phy.h
index 6d165d822175..4aab10903529 100644
--- a/drivers/net/wireless/b43/phy.h
+++ b/drivers/net/wireless/b43/phy.h
@@ -225,7 +225,6 @@ int b43_phy_init(struct b43_wldev *dev);
225void b43_set_rx_antenna(struct b43_wldev *dev, int antenna); 225void b43_set_rx_antenna(struct b43_wldev *dev, int antenna);
226 226
227void b43_phy_xmitpower(struct b43_wldev *dev); 227void b43_phy_xmitpower(struct b43_wldev *dev);
228void b43_gphy_dc_lt_init(struct b43_wldev *dev);
229 228
230/* Returns the boolean whether the board has HardwarePowerControl */ 229/* Returns the boolean whether the board has HardwarePowerControl */
231bool b43_has_hardware_pctl(struct b43_phy *phy); 230bool b43_has_hardware_pctl(struct b43_phy *phy);
@@ -252,6 +251,14 @@ struct b43_rfatt_list {
252 u8 max_val; 251 u8 max_val;
253}; 252};
254 253
254/* Returns true, if the values are the same. */
255static inline bool b43_compare_rfatt(const struct b43_rfatt *a,
256 const struct b43_rfatt *b)
257{
258 return ((a->att == b->att) &&
259 (a->with_padmix == b->with_padmix));
260}
261
255/* Baseband Attenuation */ 262/* Baseband Attenuation */
256struct b43_bbatt { 263struct b43_bbatt {
257 u8 att; /* Attenuation value */ 264 u8 att; /* Attenuation value */
@@ -265,6 +272,13 @@ struct b43_bbatt_list {
265 u8 max_val; 272 u8 max_val;
266}; 273};
267 274
275/* Returns true, if the values are the same. */
276static inline bool b43_compare_bbatt(const struct b43_bbatt *a,
277 const struct b43_bbatt *b)
278{
279 return (a->att == b->att);
280}
281
268/* tx_control bits. */ 282/* tx_control bits. */
269#define B43_TXCTL_PA3DB 0x40 /* PA Gain 3dB */ 283#define B43_TXCTL_PA3DB 0x40 /* PA Gain 3dB */
270#define B43_TXCTL_PA2DB 0x20 /* PA Gain 2dB */ 284#define B43_TXCTL_PA2DB 0x20 /* PA Gain 2dB */
diff --git a/drivers/net/wireless/b43/pio.c b/drivers/net/wireless/b43/pio.c
index fcacafb04346..401591267592 100644
--- a/drivers/net/wireless/b43/pio.c
+++ b/drivers/net/wireless/b43/pio.c
@@ -446,29 +446,27 @@ static void pio_tx_frame_4byte_queue(struct b43_pio_txpacket *pack,
446} 446}
447 447
448static int pio_tx_frame(struct b43_pio_txqueue *q, 448static int pio_tx_frame(struct b43_pio_txqueue *q,
449 struct sk_buff *skb, 449 struct sk_buff *skb)
450 struct ieee80211_tx_control *ctl)
451{ 450{
452 struct b43_pio_txpacket *pack; 451 struct b43_pio_txpacket *pack;
453 struct b43_txhdr txhdr; 452 struct b43_txhdr txhdr;
454 u16 cookie; 453 u16 cookie;
455 int err; 454 int err;
456 unsigned int hdrlen; 455 unsigned int hdrlen;
456 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
457 457
458 B43_WARN_ON(list_empty(&q->packets_list)); 458 B43_WARN_ON(list_empty(&q->packets_list));
459 pack = list_entry(q->packets_list.next, 459 pack = list_entry(q->packets_list.next,
460 struct b43_pio_txpacket, list); 460 struct b43_pio_txpacket, list);
461 memset(&pack->txstat, 0, sizeof(pack->txstat));
462 memcpy(&pack->txstat.control, ctl, sizeof(*ctl));
463 461
464 cookie = generate_cookie(q, pack); 462 cookie = generate_cookie(q, pack);
465 hdrlen = b43_txhdr_size(q->dev); 463 hdrlen = b43_txhdr_size(q->dev);
466 err = b43_generate_txhdr(q->dev, (u8 *)&txhdr, skb->data, 464 err = b43_generate_txhdr(q->dev, (u8 *)&txhdr, skb->data,
467 skb->len, ctl, cookie); 465 skb->len, info, cookie);
468 if (err) 466 if (err)
469 return err; 467 return err;
470 468
471 if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) { 469 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
472 /* Tell the firmware about the cookie of the last 470 /* Tell the firmware about the cookie of the last
473 * mcast frame, so it can clear the more-data bit in it. */ 471 * mcast frame, so it can clear the more-data bit in it. */
474 b43_shm_write16(q->dev, B43_SHM_SHARED, 472 b43_shm_write16(q->dev, B43_SHM_SHARED,
@@ -492,17 +490,18 @@ static int pio_tx_frame(struct b43_pio_txqueue *q,
492 return 0; 490 return 0;
493} 491}
494 492
495int b43_pio_tx(struct b43_wldev *dev, 493int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb)
496 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
497{ 494{
498 struct b43_pio_txqueue *q; 495 struct b43_pio_txqueue *q;
499 struct ieee80211_hdr *hdr; 496 struct ieee80211_hdr *hdr;
500 unsigned long flags; 497 unsigned long flags;
501 unsigned int hdrlen, total_len; 498 unsigned int hdrlen, total_len;
502 int err = 0; 499 int err = 0;
500 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
503 501
504 hdr = (struct ieee80211_hdr *)skb->data; 502 hdr = (struct ieee80211_hdr *)skb->data;
505 if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) { 503
504 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
506 /* The multicast queue will be sent after the DTIM. */ 505 /* The multicast queue will be sent after the DTIM. */
507 q = dev->pio.tx_queue_mcast; 506 q = dev->pio.tx_queue_mcast;
508 /* Set the frame More-Data bit. Ucode will clear it 507 /* Set the frame More-Data bit. Ucode will clear it
@@ -510,7 +509,7 @@ int b43_pio_tx(struct b43_wldev *dev,
510 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA); 509 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
511 } else { 510 } else {
512 /* Decide by priority where to put this frame. */ 511 /* Decide by priority where to put this frame. */
513 q = select_queue_by_priority(dev, ctl->queue); 512 q = select_queue_by_priority(dev, skb_get_queue_mapping(skb));
514 } 513 }
515 514
516 spin_lock_irqsave(&q->lock, flags); 515 spin_lock_irqsave(&q->lock, flags);
@@ -533,7 +532,7 @@ int b43_pio_tx(struct b43_wldev *dev,
533 if (total_len > (q->buffer_size - q->buffer_used)) { 532 if (total_len > (q->buffer_size - q->buffer_used)) {
534 /* Not enough memory on the queue. */ 533 /* Not enough memory on the queue. */
535 err = -EBUSY; 534 err = -EBUSY;
536 ieee80211_stop_queue(dev->wl->hw, ctl->queue); 535 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
537 q->stopped = 1; 536 q->stopped = 1;
538 goto out_unlock; 537 goto out_unlock;
539 } 538 }
@@ -541,9 +540,9 @@ int b43_pio_tx(struct b43_wldev *dev,
541 /* Assign the queue number to the ring (if not already done before) 540 /* Assign the queue number to the ring (if not already done before)
542 * so TX status handling can use it. The mac80211-queue to b43-queue 541 * so TX status handling can use it. The mac80211-queue to b43-queue
543 * mapping is static, so we don't need to store it per frame. */ 542 * mapping is static, so we don't need to store it per frame. */
544 q->queue_prio = ctl->queue; 543 q->queue_prio = skb_get_queue_mapping(skb);
545 544
546 err = pio_tx_frame(q, skb, ctl); 545 err = pio_tx_frame(q, skb);
547 if (unlikely(err == -ENOKEY)) { 546 if (unlikely(err == -ENOKEY)) {
548 /* Drop this packet, as we don't have the encryption key 547 /* Drop this packet, as we don't have the encryption key
549 * anymore and must not transmit it unencrypted. */ 548 * anymore and must not transmit it unencrypted. */
@@ -561,7 +560,7 @@ int b43_pio_tx(struct b43_wldev *dev,
561 if (((q->buffer_size - q->buffer_used) < roundup(2 + 2 + 6, 4)) || 560 if (((q->buffer_size - q->buffer_used) < roundup(2 + 2 + 6, 4)) ||
562 (q->free_packet_slots == 0)) { 561 (q->free_packet_slots == 0)) {
563 /* The queue is full. */ 562 /* The queue is full. */
564 ieee80211_stop_queue(dev->wl->hw, ctl->queue); 563 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
565 q->stopped = 1; 564 q->stopped = 1;
566 } 565 }
567 566
@@ -578,6 +577,7 @@ void b43_pio_handle_txstatus(struct b43_wldev *dev,
578 struct b43_pio_txqueue *q; 577 struct b43_pio_txqueue *q;
579 struct b43_pio_txpacket *pack = NULL; 578 struct b43_pio_txpacket *pack = NULL;
580 unsigned int total_len; 579 unsigned int total_len;
580 struct ieee80211_tx_info *info;
581 581
582 q = parse_cookie(dev, status->cookie, &pack); 582 q = parse_cookie(dev, status->cookie, &pack);
583 if (unlikely(!q)) 583 if (unlikely(!q))
@@ -586,15 +586,17 @@ void b43_pio_handle_txstatus(struct b43_wldev *dev,
586 586
587 spin_lock(&q->lock); /* IRQs are already disabled. */ 587 spin_lock(&q->lock); /* IRQs are already disabled. */
588 588
589 b43_fill_txstatus_report(&(pack->txstat), status); 589 info = IEEE80211_SKB_CB(pack->skb);
590 memset(&info->status, 0, sizeof(info->status));
591
592 b43_fill_txstatus_report(info, status);
590 593
591 total_len = pack->skb->len + b43_txhdr_size(dev); 594 total_len = pack->skb->len + b43_txhdr_size(dev);
592 total_len = roundup(total_len, 4); 595 total_len = roundup(total_len, 4);
593 q->buffer_used -= total_len; 596 q->buffer_used -= total_len;
594 q->free_packet_slots += 1; 597 q->free_packet_slots += 1;
595 598
596 ieee80211_tx_status_irqsafe(dev->wl->hw, pack->skb, 599 ieee80211_tx_status_irqsafe(dev->wl->hw, pack->skb);
597 &(pack->txstat));
598 pack->skb = NULL; 600 pack->skb = NULL;
599 list_add(&pack->list, &q->packets_list); 601 list_add(&pack->list, &q->packets_list);
600 602
@@ -611,18 +613,16 @@ void b43_pio_get_tx_stats(struct b43_wldev *dev,
611{ 613{
612 const int nr_queues = dev->wl->hw->queues; 614 const int nr_queues = dev->wl->hw->queues;
613 struct b43_pio_txqueue *q; 615 struct b43_pio_txqueue *q;
614 struct ieee80211_tx_queue_stats_data *data;
615 unsigned long flags; 616 unsigned long flags;
616 int i; 617 int i;
617 618
618 for (i = 0; i < nr_queues; i++) { 619 for (i = 0; i < nr_queues; i++) {
619 data = &(stats->data[i]);
620 q = select_queue_by_priority(dev, i); 620 q = select_queue_by_priority(dev, i);
621 621
622 spin_lock_irqsave(&q->lock, flags); 622 spin_lock_irqsave(&q->lock, flags);
623 data->len = B43_PIO_MAX_NR_TXPACKETS - q->free_packet_slots; 623 stats[i].len = B43_PIO_MAX_NR_TXPACKETS - q->free_packet_slots;
624 data->limit = B43_PIO_MAX_NR_TXPACKETS; 624 stats[i].limit = B43_PIO_MAX_NR_TXPACKETS;
625 data->count = q->nr_tx_packets; 625 stats[i].count = q->nr_tx_packets;
626 spin_unlock_irqrestore(&q->lock, flags); 626 spin_unlock_irqrestore(&q->lock, flags);
627 } 627 }
628} 628}
diff --git a/drivers/net/wireless/b43/pio.h b/drivers/net/wireless/b43/pio.h
index e2ec676cc9e4..6c174c91ca20 100644
--- a/drivers/net/wireless/b43/pio.h
+++ b/drivers/net/wireless/b43/pio.h
@@ -62,8 +62,6 @@ struct b43_pio_txpacket {
62 struct b43_pio_txqueue *queue; 62 struct b43_pio_txqueue *queue;
63 /* The TX data packet. */ 63 /* The TX data packet. */
64 struct sk_buff *skb; 64 struct sk_buff *skb;
65 /* The status meta data. */
66 struct ieee80211_tx_status txstat;
67 /* Index in the (struct b43_pio_txqueue)->packets array. */ 65 /* Index in the (struct b43_pio_txqueue)->packets array. */
68 u8 index; 66 u8 index;
69 67
@@ -167,8 +165,7 @@ int b43_pio_init(struct b43_wldev *dev);
167void b43_pio_stop(struct b43_wldev *dev); 165void b43_pio_stop(struct b43_wldev *dev);
168void b43_pio_free(struct b43_wldev *dev); 166void b43_pio_free(struct b43_wldev *dev);
169 167
170int b43_pio_tx(struct b43_wldev *dev, 168int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb);
171 struct sk_buff *skb, struct ieee80211_tx_control *ctl);
172void b43_pio_handle_txstatus(struct b43_wldev *dev, 169void b43_pio_handle_txstatus(struct b43_wldev *dev,
173 const struct b43_txstatus *status); 170 const struct b43_txstatus *status);
174void b43_pio_get_tx_stats(struct b43_wldev *dev, 171void b43_pio_get_tx_stats(struct b43_wldev *dev,
@@ -193,8 +190,7 @@ static inline void b43_pio_stop(struct b43_wldev *dev)
193{ 190{
194} 191}
195static inline int b43_pio_tx(struct b43_wldev *dev, 192static inline int b43_pio_tx(struct b43_wldev *dev,
196 struct sk_buff *skb, 193 struct sk_buff *skb)
197 struct ieee80211_tx_control *ctl)
198{ 194{
199 return 0; 195 return 0;
200} 196}
diff --git a/drivers/net/wireless/b43/rfkill.c b/drivers/net/wireless/b43/rfkill.c
index 11f53cb1139e..fec5645944a4 100644
--- a/drivers/net/wireless/b43/rfkill.c
+++ b/drivers/net/wireless/b43/rfkill.c
@@ -43,6 +43,23 @@ static bool b43_is_hw_radio_enabled(struct b43_wldev *dev)
43 return 0; 43 return 0;
44} 44}
45 45
46/* Update the rfkill state */
47static void b43_rfkill_update_state(struct b43_wldev *dev)
48{
49 struct b43_rfkill *rfk = &(dev->wl->rfkill);
50
51 if (!dev->radio_hw_enable) {
52 rfk->rfkill->state = RFKILL_STATE_HARD_BLOCKED;
53 return;
54 }
55
56 if (!dev->phy.radio_on)
57 rfk->rfkill->state = RFKILL_STATE_SOFT_BLOCKED;
58 else
59 rfk->rfkill->state = RFKILL_STATE_UNBLOCKED;
60
61}
62
46/* The poll callback for the hardware button. */ 63/* The poll callback for the hardware button. */
47static void b43_rfkill_poll(struct input_polled_dev *poll_dev) 64static void b43_rfkill_poll(struct input_polled_dev *poll_dev)
48{ 65{
@@ -60,6 +77,7 @@ static void b43_rfkill_poll(struct input_polled_dev *poll_dev)
60 if (unlikely(enabled != dev->radio_hw_enable)) { 77 if (unlikely(enabled != dev->radio_hw_enable)) {
61 dev->radio_hw_enable = enabled; 78 dev->radio_hw_enable = enabled;
62 report_change = 1; 79 report_change = 1;
80 b43_rfkill_update_state(dev);
63 b43info(wl, "Radio hardware status changed to %s\n", 81 b43info(wl, "Radio hardware status changed to %s\n",
64 enabled ? "ENABLED" : "DISABLED"); 82 enabled ? "ENABLED" : "DISABLED");
65 } 83 }
@@ -88,7 +106,7 @@ static int b43_rfkill_soft_toggle(void *data, enum rfkill_state state)
88 goto out_unlock; 106 goto out_unlock;
89 err = 0; 107 err = 0;
90 switch (state) { 108 switch (state) {
91 case RFKILL_STATE_ON: 109 case RFKILL_STATE_UNBLOCKED:
92 if (!dev->radio_hw_enable) { 110 if (!dev->radio_hw_enable) {
93 /* No luck. We can't toggle the hardware RF-kill 111 /* No luck. We can't toggle the hardware RF-kill
94 * button from software. */ 112 * button from software. */
@@ -98,10 +116,13 @@ static int b43_rfkill_soft_toggle(void *data, enum rfkill_state state)
98 if (!dev->phy.radio_on) 116 if (!dev->phy.radio_on)
99 b43_radio_turn_on(dev); 117 b43_radio_turn_on(dev);
100 break; 118 break;
101 case RFKILL_STATE_OFF: 119 case RFKILL_STATE_SOFT_BLOCKED:
102 if (dev->phy.radio_on) 120 if (dev->phy.radio_on)
103 b43_radio_turn_off(dev, 0); 121 b43_radio_turn_off(dev, 0);
104 break; 122 break;
123 default:
124 b43warn(wl, "Received unexpected rfkill state %d.\n", state);
125 break;
105 } 126 }
106out_unlock: 127out_unlock:
107 mutex_unlock(&wl->mutex); 128 mutex_unlock(&wl->mutex);
@@ -132,7 +153,7 @@ void b43_rfkill_init(struct b43_wldev *dev)
132 snprintf(rfk->name, sizeof(rfk->name), 153 snprintf(rfk->name, sizeof(rfk->name),
133 "b43-%s", wiphy_name(wl->hw->wiphy)); 154 "b43-%s", wiphy_name(wl->hw->wiphy));
134 rfk->rfkill->name = rfk->name; 155 rfk->rfkill->name = rfk->name;
135 rfk->rfkill->state = RFKILL_STATE_ON; 156 rfk->rfkill->state = RFKILL_STATE_UNBLOCKED;
136 rfk->rfkill->data = dev; 157 rfk->rfkill->data = dev;
137 rfk->rfkill->toggle_radio = b43_rfkill_soft_toggle; 158 rfk->rfkill->toggle_radio = b43_rfkill_soft_toggle;
138 rfk->rfkill->user_claim_unsupported = 1; 159 rfk->rfkill->user_claim_unsupported = 1;
diff --git a/drivers/net/wireless/b43/xmit.c b/drivers/net/wireless/b43/xmit.c
index 19aefbfb2c93..8d54502222a6 100644
--- a/drivers/net/wireless/b43/xmit.c
+++ b/drivers/net/wireless/b43/xmit.c
@@ -185,15 +185,15 @@ int b43_generate_txhdr(struct b43_wldev *dev,
185 u8 *_txhdr, 185 u8 *_txhdr,
186 const unsigned char *fragment_data, 186 const unsigned char *fragment_data,
187 unsigned int fragment_len, 187 unsigned int fragment_len,
188 const struct ieee80211_tx_control *txctl, 188 const struct ieee80211_tx_info *info,
189 u16 cookie) 189 u16 cookie)
190{ 190{
191 struct b43_txhdr *txhdr = (struct b43_txhdr *)_txhdr; 191 struct b43_txhdr *txhdr = (struct b43_txhdr *)_txhdr;
192 const struct b43_phy *phy = &dev->phy; 192 const struct b43_phy *phy = &dev->phy;
193 const struct ieee80211_hdr *wlhdr = 193 const struct ieee80211_hdr *wlhdr =
194 (const struct ieee80211_hdr *)fragment_data; 194 (const struct ieee80211_hdr *)fragment_data;
195 int use_encryption = (!(txctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)); 195 int use_encryption = (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT));
196 u16 fctl = le16_to_cpu(wlhdr->frame_control); 196 __le16 fctl = wlhdr->frame_control;
197 struct ieee80211_rate *fbrate; 197 struct ieee80211_rate *fbrate;
198 u8 rate, rate_fb; 198 u8 rate, rate_fb;
199 int rate_ofdm, rate_fb_ofdm; 199 int rate_ofdm, rate_fb_ofdm;
@@ -201,13 +201,14 @@ int b43_generate_txhdr(struct b43_wldev *dev,
201 u32 mac_ctl = 0; 201 u32 mac_ctl = 0;
202 u16 phy_ctl = 0; 202 u16 phy_ctl = 0;
203 u8 extra_ft = 0; 203 u8 extra_ft = 0;
204 struct ieee80211_rate *txrate;
204 205
205 memset(txhdr, 0, sizeof(*txhdr)); 206 memset(txhdr, 0, sizeof(*txhdr));
206 207
207 WARN_ON(!txctl->tx_rate); 208 txrate = ieee80211_get_tx_rate(dev->wl->hw, info);
208 rate = txctl->tx_rate ? txctl->tx_rate->hw_value : B43_CCK_RATE_1MB; 209 rate = txrate ? txrate->hw_value : B43_CCK_RATE_1MB;
209 rate_ofdm = b43_is_ofdm_rate(rate); 210 rate_ofdm = b43_is_ofdm_rate(rate);
210 fbrate = txctl->alt_retry_rate ? : txctl->tx_rate; 211 fbrate = ieee80211_get_alt_retry_rate(dev->wl->hw, info) ? : txrate;
211 rate_fb = fbrate->hw_value; 212 rate_fb = fbrate->hw_value;
212 rate_fb_ofdm = b43_is_ofdm_rate(rate_fb); 213 rate_fb_ofdm = b43_is_ofdm_rate(rate_fb);
213 214
@@ -227,15 +228,13 @@ int b43_generate_txhdr(struct b43_wldev *dev,
227 * use the original dur_id field. */ 228 * use the original dur_id field. */
228 txhdr->dur_fb = wlhdr->duration_id; 229 txhdr->dur_fb = wlhdr->duration_id;
229 } else { 230 } else {
230 txhdr->dur_fb = ieee80211_generic_frame_duration(dev->wl->hw, 231 txhdr->dur_fb = ieee80211_generic_frame_duration(
231 txctl->vif, 232 dev->wl->hw, info->control.vif, fragment_len, fbrate);
232 fragment_len,
233 fbrate);
234 } 233 }
235 234
236 plcp_fragment_len = fragment_len + FCS_LEN; 235 plcp_fragment_len = fragment_len + FCS_LEN;
237 if (use_encryption) { 236 if (use_encryption) {
238 u8 key_idx = (u16) (txctl->key_idx); 237 u8 key_idx = info->control.hw_key->hw_key_idx;
239 struct b43_key *key; 238 struct b43_key *key;
240 int wlhdr_len; 239 int wlhdr_len;
241 size_t iv_len; 240 size_t iv_len;
@@ -253,15 +252,15 @@ int b43_generate_txhdr(struct b43_wldev *dev,
253 } 252 }
254 253
255 /* Hardware appends ICV. */ 254 /* Hardware appends ICV. */
256 plcp_fragment_len += txctl->icv_len; 255 plcp_fragment_len += info->control.icv_len;
257 256
258 key_idx = b43_kidx_to_fw(dev, key_idx); 257 key_idx = b43_kidx_to_fw(dev, key_idx);
259 mac_ctl |= (key_idx << B43_TXH_MAC_KEYIDX_SHIFT) & 258 mac_ctl |= (key_idx << B43_TXH_MAC_KEYIDX_SHIFT) &
260 B43_TXH_MAC_KEYIDX; 259 B43_TXH_MAC_KEYIDX;
261 mac_ctl |= (key->algorithm << B43_TXH_MAC_KEYALG_SHIFT) & 260 mac_ctl |= (key->algorithm << B43_TXH_MAC_KEYALG_SHIFT) &
262 B43_TXH_MAC_KEYALG; 261 B43_TXH_MAC_KEYALG;
263 wlhdr_len = ieee80211_get_hdrlen(fctl); 262 wlhdr_len = ieee80211_hdrlen(fctl);
264 iv_len = min((size_t) txctl->iv_len, 263 iv_len = min((size_t) info->control.iv_len,
265 ARRAY_SIZE(txhdr->iv)); 264 ARRAY_SIZE(txhdr->iv));
266 memcpy(txhdr->iv, ((u8 *) wlhdr) + wlhdr_len, iv_len); 265 memcpy(txhdr->iv, ((u8 *) wlhdr) + wlhdr_len, iv_len);
267 } 266 }
@@ -292,10 +291,10 @@ int b43_generate_txhdr(struct b43_wldev *dev,
292 phy_ctl |= B43_TXH_PHY_ENC_OFDM; 291 phy_ctl |= B43_TXH_PHY_ENC_OFDM;
293 else 292 else
294 phy_ctl |= B43_TXH_PHY_ENC_CCK; 293 phy_ctl |= B43_TXH_PHY_ENC_CCK;
295 if (txctl->flags & IEEE80211_TXCTL_SHORT_PREAMBLE) 294 if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE)
296 phy_ctl |= B43_TXH_PHY_SHORTPRMBL; 295 phy_ctl |= B43_TXH_PHY_SHORTPRMBL;
297 296
298 switch (b43_ieee80211_antenna_sanitize(dev, txctl->antenna_sel_tx)) { 297 switch (b43_ieee80211_antenna_sanitize(dev, info->antenna_sel_tx)) {
299 case 0: /* Default */ 298 case 0: /* Default */
300 phy_ctl |= B43_TXH_PHY_ANT01AUTO; 299 phy_ctl |= B43_TXH_PHY_ANT01AUTO;
301 break; 300 break;
@@ -316,34 +315,36 @@ int b43_generate_txhdr(struct b43_wldev *dev,
316 } 315 }
317 316
318 /* MAC control */ 317 /* MAC control */
319 if (!(txctl->flags & IEEE80211_TXCTL_NO_ACK)) 318 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
320 mac_ctl |= B43_TXH_MAC_ACK; 319 mac_ctl |= B43_TXH_MAC_ACK;
321 if (!(((fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL) && 320 /* use hardware sequence counter as the non-TID counter */
322 ((fctl & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_PSPOLL))) 321 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
323 mac_ctl |= B43_TXH_MAC_HWSEQ; 322 mac_ctl |= B43_TXH_MAC_HWSEQ;
324 if (txctl->flags & IEEE80211_TXCTL_FIRST_FRAGMENT) 323 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
325 mac_ctl |= B43_TXH_MAC_STMSDU; 324 mac_ctl |= B43_TXH_MAC_STMSDU;
326 if (phy->type == B43_PHYTYPE_A) 325 if (phy->type == B43_PHYTYPE_A)
327 mac_ctl |= B43_TXH_MAC_5GHZ; 326 mac_ctl |= B43_TXH_MAC_5GHZ;
328 if (txctl->flags & IEEE80211_TXCTL_LONG_RETRY_LIMIT) 327 if (info->flags & IEEE80211_TX_CTL_LONG_RETRY_LIMIT)
329 mac_ctl |= B43_TXH_MAC_LONGFRAME; 328 mac_ctl |= B43_TXH_MAC_LONGFRAME;
330 329
331 /* Generate the RTS or CTS-to-self frame */ 330 /* Generate the RTS or CTS-to-self frame */
332 if ((txctl->flags & IEEE80211_TXCTL_USE_RTS_CTS) || 331 if ((info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) ||
333 (txctl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)) { 332 (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT)) {
334 unsigned int len; 333 unsigned int len;
335 struct ieee80211_hdr *hdr; 334 struct ieee80211_hdr *hdr;
336 int rts_rate, rts_rate_fb; 335 int rts_rate, rts_rate_fb;
337 int rts_rate_ofdm, rts_rate_fb_ofdm; 336 int rts_rate_ofdm, rts_rate_fb_ofdm;
338 struct b43_plcp_hdr6 *plcp; 337 struct b43_plcp_hdr6 *plcp;
338 struct ieee80211_rate *rts_cts_rate;
339 339
340 WARN_ON(!txctl->rts_cts_rate); 340 rts_cts_rate = ieee80211_get_rts_cts_rate(dev->wl->hw, info);
341 rts_rate = txctl->rts_cts_rate ? txctl->rts_cts_rate->hw_value : B43_CCK_RATE_1MB; 341
342 rts_rate = rts_cts_rate ? rts_cts_rate->hw_value : B43_CCK_RATE_1MB;
342 rts_rate_ofdm = b43_is_ofdm_rate(rts_rate); 343 rts_rate_ofdm = b43_is_ofdm_rate(rts_rate);
343 rts_rate_fb = b43_calc_fallback_rate(rts_rate); 344 rts_rate_fb = b43_calc_fallback_rate(rts_rate);
344 rts_rate_fb_ofdm = b43_is_ofdm_rate(rts_rate_fb); 345 rts_rate_fb_ofdm = b43_is_ofdm_rate(rts_rate_fb);
345 346
346 if (txctl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) { 347 if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
347 struct ieee80211_cts *cts; 348 struct ieee80211_cts *cts;
348 349
349 if (b43_is_old_txhdr_format(dev)) { 350 if (b43_is_old_txhdr_format(dev)) {
@@ -353,9 +354,9 @@ int b43_generate_txhdr(struct b43_wldev *dev,
353 cts = (struct ieee80211_cts *) 354 cts = (struct ieee80211_cts *)
354 (txhdr->new_format.rts_frame); 355 (txhdr->new_format.rts_frame);
355 } 356 }
356 ieee80211_ctstoself_get(dev->wl->hw, txctl->vif, 357 ieee80211_ctstoself_get(dev->wl->hw, info->control.vif,
357 fragment_data, fragment_len, 358 fragment_data, fragment_len,
358 txctl, cts); 359 info, cts);
359 mac_ctl |= B43_TXH_MAC_SENDCTS; 360 mac_ctl |= B43_TXH_MAC_SENDCTS;
360 len = sizeof(struct ieee80211_cts); 361 len = sizeof(struct ieee80211_cts);
361 } else { 362 } else {
@@ -368,9 +369,9 @@ int b43_generate_txhdr(struct b43_wldev *dev,
368 rts = (struct ieee80211_rts *) 369 rts = (struct ieee80211_rts *)
369 (txhdr->new_format.rts_frame); 370 (txhdr->new_format.rts_frame);
370 } 371 }
371 ieee80211_rts_get(dev->wl->hw, txctl->vif, 372 ieee80211_rts_get(dev->wl->hw, info->control.vif,
372 fragment_data, fragment_len, 373 fragment_data, fragment_len,
373 txctl, rts); 374 info, rts);
374 mac_ctl |= B43_TXH_MAC_SENDRTS; 375 mac_ctl |= B43_TXH_MAC_SENDRTS;
375 len = sizeof(struct ieee80211_rts); 376 len = sizeof(struct ieee80211_rts);
376 } 377 }
@@ -508,7 +509,7 @@ void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr)
508 struct b43_plcp_hdr6 *plcp; 509 struct b43_plcp_hdr6 *plcp;
509 struct ieee80211_hdr *wlhdr; 510 struct ieee80211_hdr *wlhdr;
510 const struct b43_rxhdr_fw4 *rxhdr = _rxhdr; 511 const struct b43_rxhdr_fw4 *rxhdr = _rxhdr;
511 u16 fctl; 512 __le16 fctl;
512 u16 phystat0, phystat3, chanstat, mactime; 513 u16 phystat0, phystat3, chanstat, mactime;
513 u32 macstat; 514 u32 macstat;
514 u16 chanid; 515 u16 chanid;
@@ -548,7 +549,7 @@ void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr)
548 goto drop; 549 goto drop;
549 } 550 }
550 wlhdr = (struct ieee80211_hdr *)(skb->data); 551 wlhdr = (struct ieee80211_hdr *)(skb->data);
551 fctl = le16_to_cpu(wlhdr->frame_control); 552 fctl = wlhdr->frame_control;
552 553
553 if (macstat & B43_RX_MAC_DEC) { 554 if (macstat & B43_RX_MAC_DEC) {
554 unsigned int keyidx; 555 unsigned int keyidx;
@@ -563,7 +564,7 @@ void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr)
563 B43_WARN_ON(keyidx >= dev->max_nr_keys); 564 B43_WARN_ON(keyidx >= dev->max_nr_keys);
564 565
565 if (dev->key[keyidx].algorithm != B43_SEC_ALGO_NONE) { 566 if (dev->key[keyidx].algorithm != B43_SEC_ALGO_NONE) {
566 wlhdr_len = ieee80211_get_hdrlen(fctl); 567 wlhdr_len = ieee80211_hdrlen(fctl);
567 if (unlikely(skb->len < (wlhdr_len + 3))) { 568 if (unlikely(skb->len < (wlhdr_len + 3))) {
568 b43dbg(dev->wl, 569 b43dbg(dev->wl,
569 "RX: Packet size underrun (3)\n"); 570 "RX: Packet size underrun (3)\n");
@@ -581,12 +582,11 @@ void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr)
581 // and also find out what the maximum possible value is. 582 // and also find out what the maximum possible value is.
582 // Fill status.ssi and status.signal fields. 583 // Fill status.ssi and status.signal fields.
583 } else { 584 } else {
584 status.ssi = b43_rssi_postprocess(dev, rxhdr->jssi, 585 status.signal = b43_rssi_postprocess(dev, rxhdr->jssi,
585 (phystat0 & B43_RX_PHYST0_OFDM), 586 (phystat0 & B43_RX_PHYST0_OFDM),
586 (phystat0 & B43_RX_PHYST0_GAINCTL), 587 (phystat0 & B43_RX_PHYST0_GAINCTL),
587 (phystat3 & B43_RX_PHYST3_TRSTATE)); 588 (phystat3 & B43_RX_PHYST3_TRSTATE));
588 /* the next line looks wrong, but is what mac80211 wants */ 589 status.qual = (rxhdr->jssi * 100) / B43_RX_MAX_SSI;
589 status.signal = (rxhdr->jssi * 100) / B43_RX_MAX_SSI;
590 } 590 }
591 591
592 if (phystat0 & B43_RX_PHYST0_OFDM) 592 if (phystat0 & B43_RX_PHYST0_OFDM)
@@ -604,9 +604,7 @@ void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr)
604 * of timestamp, i.e. about 65 milliseconds after the PHY received 604 * of timestamp, i.e. about 65 milliseconds after the PHY received
605 * the first symbol. 605 * the first symbol.
606 */ 606 */
607 if (((fctl & (IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) 607 if (ieee80211_is_beacon(fctl) || dev->wl->radiotap_enabled) {
608 == (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON)) ||
609 dev->wl->radiotap_enabled) {
610 u16 low_mactime_now; 608 u16 low_mactime_now;
611 609
612 b43_tsf_read(dev, &status.mactime); 610 b43_tsf_read(dev, &status.mactime);
@@ -685,27 +683,27 @@ void b43_handle_txstatus(struct b43_wldev *dev,
685/* Fill out the mac80211 TXstatus report based on the b43-specific 683/* Fill out the mac80211 TXstatus report based on the b43-specific
686 * txstatus report data. This returns a boolean whether the frame was 684 * txstatus report data. This returns a boolean whether the frame was
687 * successfully transmitted. */ 685 * successfully transmitted. */
688bool b43_fill_txstatus_report(struct ieee80211_tx_status *report, 686bool b43_fill_txstatus_report(struct ieee80211_tx_info *report,
689 const struct b43_txstatus *status) 687 const struct b43_txstatus *status)
690{ 688{
691 bool frame_success = 1; 689 bool frame_success = 1;
692 690
693 if (status->acked) { 691 if (status->acked) {
694 /* The frame was ACKed. */ 692 /* The frame was ACKed. */
695 report->flags |= IEEE80211_TX_STATUS_ACK; 693 report->flags |= IEEE80211_TX_STAT_ACK;
696 } else { 694 } else {
697 /* The frame was not ACKed... */ 695 /* The frame was not ACKed... */
698 if (!(report->control.flags & IEEE80211_TXCTL_NO_ACK)) { 696 if (!(report->flags & IEEE80211_TX_CTL_NO_ACK)) {
699 /* ...but we expected an ACK. */ 697 /* ...but we expected an ACK. */
700 frame_success = 0; 698 frame_success = 0;
701 report->excessive_retries = 1; 699 report->status.excessive_retries = 1;
702 } 700 }
703 } 701 }
704 if (status->frame_count == 0) { 702 if (status->frame_count == 0) {
705 /* The frame was not transmitted at all. */ 703 /* The frame was not transmitted at all. */
706 report->retry_count = 0; 704 report->status.retry_count = 0;
707 } else 705 } else
708 report->retry_count = status->frame_count - 1; 706 report->status.retry_count = status->frame_count - 1;
709 707
710 return frame_success; 708 return frame_success;
711} 709}
diff --git a/drivers/net/wireless/b43/xmit.h b/drivers/net/wireless/b43/xmit.h
index b05f44e0d626..0215faf47541 100644
--- a/drivers/net/wireless/b43/xmit.h
+++ b/drivers/net/wireless/b43/xmit.h
@@ -178,7 +178,7 @@ int b43_generate_txhdr(struct b43_wldev *dev,
178 u8 * txhdr, 178 u8 * txhdr,
179 const unsigned char *fragment_data, 179 const unsigned char *fragment_data,
180 unsigned int fragment_len, 180 unsigned int fragment_len,
181 const struct ieee80211_tx_control *txctl, u16 cookie); 181 const struct ieee80211_tx_info *txctl, u16 cookie);
182 182
183/* Transmit Status */ 183/* Transmit Status */
184struct b43_txstatus { 184struct b43_txstatus {
@@ -294,7 +294,7 @@ void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);
294 294
295void b43_handle_txstatus(struct b43_wldev *dev, 295void b43_handle_txstatus(struct b43_wldev *dev,
296 const struct b43_txstatus *status); 296 const struct b43_txstatus *status);
297bool b43_fill_txstatus_report(struct ieee80211_tx_status *report, 297bool b43_fill_txstatus_report(struct ieee80211_tx_info *report,
298 const struct b43_txstatus *status); 298 const struct b43_txstatus *status);
299 299
300void b43_tx_suspend(struct b43_wldev *dev); 300void b43_tx_suspend(struct b43_wldev *dev);
diff --git a/drivers/net/wireless/b43legacy/b43legacy.h b/drivers/net/wireless/b43legacy/b43legacy.h
index ded3cd31b3df..c40078e1fff9 100644
--- a/drivers/net/wireless/b43legacy/b43legacy.h
+++ b/drivers/net/wireless/b43legacy/b43legacy.h
@@ -823,23 +823,6 @@ void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
823# define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0) 823# define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)
824#endif /* DEBUG */ 824#endif /* DEBUG */
825 825
826
827/** Limit a value between two limits */
828#ifdef limit_value
829# undef limit_value
830#endif
831#define limit_value(value, min, max) \
832 ({ \
833 typeof(value) __value = (value); \
834 typeof(value) __min = (min); \
835 typeof(value) __max = (max); \
836 if (__value < __min) \
837 __value = __min; \
838 else if (__value > __max) \
839 __value = __max; \
840 __value; \
841 })
842
843/* Macros for printing a value in Q5.2 format */ 826/* Macros for printing a value in Q5.2 format */
844#define Q52_FMT "%u.%u" 827#define Q52_FMT "%u.%u"
845#define Q52_ARG(q52) ((q52) / 4), (((q52) & 3) * 100 / 4) 828#define Q52_ARG(q52) ((q52) / 4), (((q52) & 3) * 100 / 4)
diff --git a/drivers/net/wireless/b43legacy/dma.c b/drivers/net/wireless/b43legacy/dma.c
index 93ddc1cbcc8b..fb6819e40f38 100644
--- a/drivers/net/wireless/b43legacy/dma.c
+++ b/drivers/net/wireless/b43legacy/dma.c
@@ -393,13 +393,13 @@ dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring,
393 dma_addr_t dmaaddr; 393 dma_addr_t dmaaddr;
394 394
395 if (tx) 395 if (tx)
396 dmaaddr = dma_map_single(ring->dev->dev->dma_dev, 396 dmaaddr = ssb_dma_map_single(ring->dev->dev,
397 buf, len, 397 buf, len,
398 DMA_TO_DEVICE); 398 DMA_TO_DEVICE);
399 else 399 else
400 dmaaddr = dma_map_single(ring->dev->dev->dma_dev, 400 dmaaddr = ssb_dma_map_single(ring->dev->dev,
401 buf, len, 401 buf, len,
402 DMA_FROM_DEVICE); 402 DMA_FROM_DEVICE);
403 403
404 return dmaaddr; 404 return dmaaddr;
405} 405}
@@ -411,13 +411,13 @@ void unmap_descbuffer(struct b43legacy_dmaring *ring,
411 int tx) 411 int tx)
412{ 412{
413 if (tx) 413 if (tx)
414 dma_unmap_single(ring->dev->dev->dma_dev, 414 ssb_dma_unmap_single(ring->dev->dev,
415 addr, len, 415 addr, len,
416 DMA_TO_DEVICE); 416 DMA_TO_DEVICE);
417 else 417 else
418 dma_unmap_single(ring->dev->dev->dma_dev, 418 ssb_dma_unmap_single(ring->dev->dev,
419 addr, len, 419 addr, len,
420 DMA_FROM_DEVICE); 420 DMA_FROM_DEVICE);
421} 421}
422 422
423static inline 423static inline
@@ -427,8 +427,8 @@ void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring,
427{ 427{
428 B43legacy_WARN_ON(ring->tx); 428 B43legacy_WARN_ON(ring->tx);
429 429
430 dma_sync_single_for_cpu(ring->dev->dev->dma_dev, 430 ssb_dma_sync_single_for_cpu(ring->dev->dev,
431 addr, len, DMA_FROM_DEVICE); 431 addr, len, DMA_FROM_DEVICE);
432} 432}
433 433
434static inline 434static inline
@@ -438,8 +438,8 @@ void sync_descbuffer_for_device(struct b43legacy_dmaring *ring,
438{ 438{
439 B43legacy_WARN_ON(ring->tx); 439 B43legacy_WARN_ON(ring->tx);
440 440
441 dma_sync_single_for_device(ring->dev->dev->dma_dev, 441 ssb_dma_sync_single_for_device(ring->dev->dev,
442 addr, len, DMA_FROM_DEVICE); 442 addr, len, DMA_FROM_DEVICE);
443} 443}
444 444
445static inline 445static inline
@@ -458,10 +458,11 @@ void free_descriptor_buffer(struct b43legacy_dmaring *ring,
458 458
459static int alloc_ringmemory(struct b43legacy_dmaring *ring) 459static int alloc_ringmemory(struct b43legacy_dmaring *ring)
460{ 460{
461 struct device *dma_dev = ring->dev->dev->dma_dev; 461 /* GFP flags must match the flags in free_ringmemory()! */
462 462 ring->descbase = ssb_dma_alloc_consistent(ring->dev->dev,
463 ring->descbase = dma_alloc_coherent(dma_dev, B43legacy_DMA_RINGMEMSIZE, 463 B43legacy_DMA_RINGMEMSIZE,
464 &(ring->dmabase), GFP_KERNEL); 464 &(ring->dmabase),
465 GFP_KERNEL);
465 if (!ring->descbase) { 466 if (!ring->descbase) {
466 b43legacyerr(ring->dev->wl, "DMA ringmemory allocation" 467 b43legacyerr(ring->dev->wl, "DMA ringmemory allocation"
467 " failed\n"); 468 " failed\n");
@@ -474,10 +475,8 @@ static int alloc_ringmemory(struct b43legacy_dmaring *ring)
474 475
475static void free_ringmemory(struct b43legacy_dmaring *ring) 476static void free_ringmemory(struct b43legacy_dmaring *ring)
476{ 477{
477 struct device *dma_dev = ring->dev->dev->dma_dev; 478 ssb_dma_free_consistent(ring->dev->dev, B43legacy_DMA_RINGMEMSIZE,
478 479 ring->descbase, ring->dmabase, GFP_KERNEL);
479 dma_free_coherent(dma_dev, B43legacy_DMA_RINGMEMSIZE,
480 ring->descbase, ring->dmabase);
481} 480}
482 481
483/* Reset the RX DMA channel */ 482/* Reset the RX DMA channel */
@@ -589,7 +588,7 @@ static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring,
589 size_t buffersize, 588 size_t buffersize,
590 bool dma_to_device) 589 bool dma_to_device)
591{ 590{
592 if (unlikely(dma_mapping_error(addr))) 591 if (unlikely(ssb_dma_mapping_error(ring->dev->dev, addr)))
593 return 1; 592 return 1;
594 593
595 switch (ring->type) { 594 switch (ring->type) {
@@ -860,6 +859,18 @@ static u64 supported_dma_mask(struct b43legacy_wldev *dev)
860 return DMA_30BIT_MASK; 859 return DMA_30BIT_MASK;
861} 860}
862 861
862static enum b43legacy_dmatype dma_mask_to_engine_type(u64 dmamask)
863{
864 if (dmamask == DMA_30BIT_MASK)
865 return B43legacy_DMA_30BIT;
866 if (dmamask == DMA_32BIT_MASK)
867 return B43legacy_DMA_32BIT;
868 if (dmamask == DMA_64BIT_MASK)
869 return B43legacy_DMA_64BIT;
870 B43legacy_WARN_ON(1);
871 return B43legacy_DMA_30BIT;
872}
873
863/* Main initialization function. */ 874/* Main initialization function. */
864static 875static
865struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev, 876struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
@@ -894,9 +905,9 @@ struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
894 goto err_kfree_meta; 905 goto err_kfree_meta;
895 906
896 /* test for ability to dma to txhdr_cache */ 907 /* test for ability to dma to txhdr_cache */
897 dma_test = dma_map_single(dev->dev->dma_dev, ring->txhdr_cache, 908 dma_test = ssb_dma_map_single(dev->dev, ring->txhdr_cache,
898 sizeof(struct b43legacy_txhdr_fw3), 909 sizeof(struct b43legacy_txhdr_fw3),
899 DMA_TO_DEVICE); 910 DMA_TO_DEVICE);
900 911
901 if (b43legacy_dma_mapping_error(ring, dma_test, 912 if (b43legacy_dma_mapping_error(ring, dma_test,
902 sizeof(struct b43legacy_txhdr_fw3), 1)) { 913 sizeof(struct b43legacy_txhdr_fw3), 1)) {
@@ -908,7 +919,7 @@ struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
908 if (!ring->txhdr_cache) 919 if (!ring->txhdr_cache)
909 goto err_kfree_meta; 920 goto err_kfree_meta;
910 921
911 dma_test = dma_map_single(dev->dev->dma_dev, 922 dma_test = ssb_dma_map_single(dev->dev,
912 ring->txhdr_cache, 923 ring->txhdr_cache,
913 sizeof(struct b43legacy_txhdr_fw3), 924 sizeof(struct b43legacy_txhdr_fw3),
914 DMA_TO_DEVICE); 925 DMA_TO_DEVICE);
@@ -918,9 +929,9 @@ struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
918 goto err_kfree_txhdr_cache; 929 goto err_kfree_txhdr_cache;
919 } 930 }
920 931
921 dma_unmap_single(dev->dev->dma_dev, 932 ssb_dma_unmap_single(dev->dev, dma_test,
922 dma_test, sizeof(struct b43legacy_txhdr_fw3), 933 sizeof(struct b43legacy_txhdr_fw3),
923 DMA_TO_DEVICE); 934 DMA_TO_DEVICE);
924 } 935 }
925 936
926 ring->nr_slots = nr_slots; 937 ring->nr_slots = nr_slots;
@@ -1019,6 +1030,43 @@ void b43legacy_dma_free(struct b43legacy_wldev *dev)
1019 dma->tx_ring0 = NULL; 1030 dma->tx_ring0 = NULL;
1020} 1031}
1021 1032
1033static int b43legacy_dma_set_mask(struct b43legacy_wldev *dev, u64 mask)
1034{
1035 u64 orig_mask = mask;
1036 bool fallback = 0;
1037 int err;
1038
1039 /* Try to set the DMA mask. If it fails, try falling back to a
1040 * lower mask, as we can always also support a lower one. */
1041 while (1) {
1042 err = ssb_dma_set_mask(dev->dev, mask);
1043 if (!err)
1044 break;
1045 if (mask == DMA_64BIT_MASK) {
1046 mask = DMA_32BIT_MASK;
1047 fallback = 1;
1048 continue;
1049 }
1050 if (mask == DMA_32BIT_MASK) {
1051 mask = DMA_30BIT_MASK;
1052 fallback = 1;
1053 continue;
1054 }
1055 b43legacyerr(dev->wl, "The machine/kernel does not support "
1056 "the required %u-bit DMA mask\n",
1057 (unsigned int)dma_mask_to_engine_type(orig_mask));
1058 return -EOPNOTSUPP;
1059 }
1060 if (fallback) {
1061 b43legacyinfo(dev->wl, "DMA mask fallback from %u-bit to %u-"
1062 "bit\n",
1063 (unsigned int)dma_mask_to_engine_type(orig_mask),
1064 (unsigned int)dma_mask_to_engine_type(mask));
1065 }
1066
1067 return 0;
1068}
1069
1022int b43legacy_dma_init(struct b43legacy_wldev *dev) 1070int b43legacy_dma_init(struct b43legacy_wldev *dev)
1023{ 1071{
1024 struct b43legacy_dma *dma = &dev->dma; 1072 struct b43legacy_dma *dma = &dev->dma;
@@ -1028,21 +1076,8 @@ int b43legacy_dma_init(struct b43legacy_wldev *dev)
1028 enum b43legacy_dmatype type; 1076 enum b43legacy_dmatype type;
1029 1077
1030 dmamask = supported_dma_mask(dev); 1078 dmamask = supported_dma_mask(dev);
1031 switch (dmamask) { 1079 type = dma_mask_to_engine_type(dmamask);
1032 default: 1080 err = b43legacy_dma_set_mask(dev, dmamask);
1033 B43legacy_WARN_ON(1);
1034 case DMA_30BIT_MASK:
1035 type = B43legacy_DMA_30BIT;
1036 break;
1037 case DMA_32BIT_MASK:
1038 type = B43legacy_DMA_32BIT;
1039 break;
1040 case DMA_64BIT_MASK:
1041 type = B43legacy_DMA_64BIT;
1042 break;
1043 }
1044
1045 err = ssb_dma_set_mask(dev->dev, dmamask);
1046 if (err) { 1081 if (err) {
1047#ifdef CONFIG_B43LEGACY_PIO 1082#ifdef CONFIG_B43LEGACY_PIO
1048 b43legacywarn(dev->wl, "DMA for this device not supported. " 1083 b43legacywarn(dev->wl, "DMA for this device not supported. "
@@ -1205,10 +1240,10 @@ struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev,
1205} 1240}
1206 1241
1207static int dma_tx_fragment(struct b43legacy_dmaring *ring, 1242static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1208 struct sk_buff *skb, 1243 struct sk_buff *skb)
1209 struct ieee80211_tx_control *ctl)
1210{ 1244{
1211 const struct b43legacy_dma_ops *ops = ring->ops; 1245 const struct b43legacy_dma_ops *ops = ring->ops;
1246 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1212 u8 *header; 1247 u8 *header;
1213 int slot, old_top_slot, old_used_slots; 1248 int slot, old_top_slot, old_used_slots;
1214 int err; 1249 int err;
@@ -1231,7 +1266,7 @@ static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1231 header = &(ring->txhdr_cache[slot * sizeof( 1266 header = &(ring->txhdr_cache[slot * sizeof(
1232 struct b43legacy_txhdr_fw3)]); 1267 struct b43legacy_txhdr_fw3)]);
1233 err = b43legacy_generate_txhdr(ring->dev, header, 1268 err = b43legacy_generate_txhdr(ring->dev, header,
1234 skb->data, skb->len, ctl, 1269 skb->data, skb->len, info,
1235 generate_cookie(ring, slot)); 1270 generate_cookie(ring, slot));
1236 if (unlikely(err)) { 1271 if (unlikely(err)) {
1237 ring->current_slot = old_top_slot; 1272 ring->current_slot = old_top_slot;
@@ -1255,7 +1290,6 @@ static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1255 desc = ops->idx2desc(ring, slot, &meta); 1290 desc = ops->idx2desc(ring, slot, &meta);
1256 memset(meta, 0, sizeof(*meta)); 1291 memset(meta, 0, sizeof(*meta));
1257 1292
1258 memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
1259 meta->skb = skb; 1293 meta->skb = skb;
1260 meta->is_last_fragment = 1; 1294 meta->is_last_fragment = 1;
1261 1295
@@ -1323,14 +1357,13 @@ int should_inject_overflow(struct b43legacy_dmaring *ring)
1323} 1357}
1324 1358
1325int b43legacy_dma_tx(struct b43legacy_wldev *dev, 1359int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1326 struct sk_buff *skb, 1360 struct sk_buff *skb)
1327 struct ieee80211_tx_control *ctl)
1328{ 1361{
1329 struct b43legacy_dmaring *ring; 1362 struct b43legacy_dmaring *ring;
1330 int err = 0; 1363 int err = 0;
1331 unsigned long flags; 1364 unsigned long flags;
1332 1365
1333 ring = priority_to_txring(dev, ctl->queue); 1366 ring = priority_to_txring(dev, skb_get_queue_mapping(skb));
1334 spin_lock_irqsave(&ring->lock, flags); 1367 spin_lock_irqsave(&ring->lock, flags);
1335 B43legacy_WARN_ON(!ring->tx); 1368 B43legacy_WARN_ON(!ring->tx);
1336 if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) { 1369 if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
@@ -1343,7 +1376,7 @@ int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1343 * That would be a mac80211 bug. */ 1376 * That would be a mac80211 bug. */
1344 B43legacy_BUG_ON(ring->stopped); 1377 B43legacy_BUG_ON(ring->stopped);
1345 1378
1346 err = dma_tx_fragment(ring, skb, ctl); 1379 err = dma_tx_fragment(ring, skb);
1347 if (unlikely(err == -ENOKEY)) { 1380 if (unlikely(err == -ENOKEY)) {
1348 /* Drop this packet, as we don't have the encryption key 1381 /* Drop this packet, as we don't have the encryption key
1349 * anymore and must not transmit it unencrypted. */ 1382 * anymore and must not transmit it unencrypted. */
@@ -1401,26 +1434,29 @@ void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1401 1); 1434 1);
1402 1435
1403 if (meta->is_last_fragment) { 1436 if (meta->is_last_fragment) {
1404 B43legacy_WARN_ON(!meta->skb); 1437 struct ieee80211_tx_info *info;
1438 BUG_ON(!meta->skb);
1439 info = IEEE80211_SKB_CB(meta->skb);
1405 /* Call back to inform the ieee80211 subsystem about the 1440 /* Call back to inform the ieee80211 subsystem about the
1406 * status of the transmission. 1441 * status of the transmission.
1407 * Some fields of txstat are already filled in dma_tx(). 1442 * Some fields of txstat are already filled in dma_tx().
1408 */ 1443 */
1444
1445 memset(&info->status, 0, sizeof(info->status));
1446
1409 if (status->acked) { 1447 if (status->acked) {
1410 meta->txstat.flags |= IEEE80211_TX_STATUS_ACK; 1448 info->flags |= IEEE80211_TX_STAT_ACK;
1411 } else { 1449 } else {
1412 if (!(meta->txstat.control.flags 1450 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
1413 & IEEE80211_TXCTL_NO_ACK)) 1451 info->status.excessive_retries = 1;
1414 meta->txstat.excessive_retries = 1;
1415 } 1452 }
1416 if (status->frame_count == 0) { 1453 if (status->frame_count == 0) {
1417 /* The frame was not transmitted at all. */ 1454 /* The frame was not transmitted at all. */
1418 meta->txstat.retry_count = 0; 1455 info->status.retry_count = 0;
1419 } else 1456 } else
1420 meta->txstat.retry_count = status->frame_count 1457 info->status.retry_count = status->frame_count
1421 - 1; 1458 - 1;
1422 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb, 1459 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
1423 &(meta->txstat));
1424 /* skb is freed by ieee80211_tx_status_irqsafe() */ 1460 /* skb is freed by ieee80211_tx_status_irqsafe() */
1425 meta->skb = NULL; 1461 meta->skb = NULL;
1426 } else { 1462 } else {
@@ -1455,18 +1491,16 @@ void b43legacy_dma_get_tx_stats(struct b43legacy_wldev *dev,
1455{ 1491{
1456 const int nr_queues = dev->wl->hw->queues; 1492 const int nr_queues = dev->wl->hw->queues;
1457 struct b43legacy_dmaring *ring; 1493 struct b43legacy_dmaring *ring;
1458 struct ieee80211_tx_queue_stats_data *data;
1459 unsigned long flags; 1494 unsigned long flags;
1460 int i; 1495 int i;
1461 1496
1462 for (i = 0; i < nr_queues; i++) { 1497 for (i = 0; i < nr_queues; i++) {
1463 data = &(stats->data[i]);
1464 ring = priority_to_txring(dev, i); 1498 ring = priority_to_txring(dev, i);
1465 1499
1466 spin_lock_irqsave(&ring->lock, flags); 1500 spin_lock_irqsave(&ring->lock, flags);
1467 data->len = ring->used_slots / SLOTS_PER_PACKET; 1501 stats[i].len = ring->used_slots / SLOTS_PER_PACKET;
1468 data->limit = ring->nr_slots / SLOTS_PER_PACKET; 1502 stats[i].limit = ring->nr_slots / SLOTS_PER_PACKET;
1469 data->count = ring->nr_tx_packets; 1503 stats[i].count = ring->nr_tx_packets;
1470 spin_unlock_irqrestore(&ring->lock, flags); 1504 spin_unlock_irqrestore(&ring->lock, flags);
1471 } 1505 }
1472} 1506}
diff --git a/drivers/net/wireless/b43legacy/dma.h b/drivers/net/wireless/b43legacy/dma.h
index 2dd488c5be2d..2f186003c31e 100644
--- a/drivers/net/wireless/b43legacy/dma.h
+++ b/drivers/net/wireless/b43legacy/dma.h
@@ -195,7 +195,6 @@ struct b43legacy_dmadesc_meta {
195 dma_addr_t dmaaddr; 195 dma_addr_t dmaaddr;
196 /* ieee80211 TX status. Only used once per 802.11 frag. */ 196 /* ieee80211 TX status. Only used once per 802.11 frag. */
197 bool is_last_fragment; 197 bool is_last_fragment;
198 struct ieee80211_tx_status txstat;
199}; 198};
200 199
201struct b43legacy_dmaring; 200struct b43legacy_dmaring;
@@ -297,8 +296,7 @@ void b43legacy_dma_get_tx_stats(struct b43legacy_wldev *dev,
297 struct ieee80211_tx_queue_stats *stats); 296 struct ieee80211_tx_queue_stats *stats);
298 297
299int b43legacy_dma_tx(struct b43legacy_wldev *dev, 298int b43legacy_dma_tx(struct b43legacy_wldev *dev,
300 struct sk_buff *skb, 299 struct sk_buff *skb);
301 struct ieee80211_tx_control *ctl);
302void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev, 300void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
303 const struct b43legacy_txstatus *status); 301 const struct b43legacy_txstatus *status);
304 302
@@ -323,8 +321,7 @@ void b43legacy_dma_get_tx_stats(struct b43legacy_wldev *dev,
323} 321}
324static inline 322static inline
325int b43legacy_dma_tx(struct b43legacy_wldev *dev, 323int b43legacy_dma_tx(struct b43legacy_wldev *dev,
326 struct sk_buff *skb, 324 struct sk_buff *skb)
327 struct ieee80211_tx_control *ctl)
328{ 325{
329 return 0; 326 return 0;
330} 327}
diff --git a/drivers/net/wireless/b43legacy/main.c b/drivers/net/wireless/b43legacy/main.c
index 3e612d0a13e8..a1b8bf3ee732 100644
--- a/drivers/net/wireless/b43legacy/main.c
+++ b/drivers/net/wireless/b43legacy/main.c
@@ -846,10 +846,10 @@ static void handle_irq_noise(struct b43legacy_wldev *dev)
846 /* Get the noise samples. */ 846 /* Get the noise samples. */
847 B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8); 847 B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
848 i = dev->noisecalc.nr_samples; 848 i = dev->noisecalc.nr_samples;
849 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 849 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
850 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 850 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
851 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 851 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
852 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 852 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
853 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 853 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
854 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 854 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
855 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 855 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
@@ -1138,14 +1138,22 @@ static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1138 1138
1139/* Asynchronously update the packet templates in template RAM. 1139/* Asynchronously update the packet templates in template RAM.
1140 * Locking: Requires wl->irq_lock to be locked. */ 1140 * Locking: Requires wl->irq_lock to be locked. */
1141static void b43legacy_update_templates(struct b43legacy_wl *wl, 1141static void b43legacy_update_templates(struct b43legacy_wl *wl)
1142 struct sk_buff *beacon)
1143{ 1142{
1143 struct sk_buff *beacon;
1144 /* This is the top half of the ansynchronous beacon update. The bottom 1144 /* This is the top half of the ansynchronous beacon update. The bottom
1145 * half is the beacon IRQ. Beacon update must be asynchronous to avoid 1145 * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1146 * sending an invalid beacon. This can happen for example, if the 1146 * sending an invalid beacon. This can happen for example, if the
1147 * firmware transmits a beacon while we are updating it. */ 1147 * firmware transmits a beacon while we are updating it. */
1148 1148
1149 /* We could modify the existing beacon and set the aid bit in the TIM
1150 * field, but that would probably require resizing and moving of data
1151 * within the beacon template. Simply request a new beacon and let
1152 * mac80211 do the hard work. */
1153 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1154 if (unlikely(!beacon))
1155 return;
1156
1149 if (wl->current_beacon) 1157 if (wl->current_beacon)
1150 dev_kfree_skb_any(wl->current_beacon); 1158 dev_kfree_skb_any(wl->current_beacon);
1151 wl->current_beacon = beacon; 1159 wl->current_beacon = beacon;
@@ -2358,8 +2366,7 @@ static int b43legacy_rng_init(struct b43legacy_wl *wl)
2358} 2366}
2359 2367
2360static int b43legacy_op_tx(struct ieee80211_hw *hw, 2368static int b43legacy_op_tx(struct ieee80211_hw *hw,
2361 struct sk_buff *skb, 2369 struct sk_buff *skb)
2362 struct ieee80211_tx_control *ctl)
2363{ 2370{
2364 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 2371 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2365 struct b43legacy_wldev *dev = wl->current_dev; 2372 struct b43legacy_wldev *dev = wl->current_dev;
@@ -2373,10 +2380,10 @@ static int b43legacy_op_tx(struct ieee80211_hw *hw,
2373 /* DMA-TX is done without a global lock. */ 2380 /* DMA-TX is done without a global lock. */
2374 if (b43legacy_using_pio(dev)) { 2381 if (b43legacy_using_pio(dev)) {
2375 spin_lock_irqsave(&wl->irq_lock, flags); 2382 spin_lock_irqsave(&wl->irq_lock, flags);
2376 err = b43legacy_pio_tx(dev, skb, ctl); 2383 err = b43legacy_pio_tx(dev, skb);
2377 spin_unlock_irqrestore(&wl->irq_lock, flags); 2384 spin_unlock_irqrestore(&wl->irq_lock, flags);
2378 } else 2385 } else
2379 err = b43legacy_dma_tx(dev, skb, ctl); 2386 err = b43legacy_dma_tx(dev, skb);
2380out: 2387out:
2381 if (unlikely(err)) { 2388 if (unlikely(err)) {
2382 /* Drop the packet. */ 2389 /* Drop the packet. */
@@ -2385,8 +2392,7 @@ out:
2385 return NETDEV_TX_OK; 2392 return NETDEV_TX_OK;
2386} 2393}
2387 2394
2388static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, 2395static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
2389 int queue,
2390 const struct ieee80211_tx_queue_params *params) 2396 const struct ieee80211_tx_queue_params *params)
2391{ 2397{
2392 return 0; 2398 return 0;
@@ -2729,10 +2735,13 @@ static int b43legacy_op_config_interface(struct ieee80211_hw *hw,
2729 memset(wl->bssid, 0, ETH_ALEN); 2735 memset(wl->bssid, 0, ETH_ALEN);
2730 if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) { 2736 if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2731 if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP)) { 2737 if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2732 B43legacy_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP); 2738 B43legacy_WARN_ON(vif->type != IEEE80211_IF_TYPE_AP);
2733 b43legacy_set_ssid(dev, conf->ssid, conf->ssid_len); 2739 b43legacy_set_ssid(dev, conf->ssid, conf->ssid_len);
2734 if (conf->beacon) 2740 if (conf->changed & IEEE80211_IFCC_BEACON)
2735 b43legacy_update_templates(wl, conf->beacon); 2741 b43legacy_update_templates(wl);
2742 } else if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_IBSS)) {
2743 if (conf->changed & IEEE80211_IFCC_BEACON)
2744 b43legacy_update_templates(wl);
2736 } 2745 }
2737 b43legacy_write_mac_bssid_templates(dev); 2746 b43legacy_write_mac_bssid_templates(dev);
2738 } 2747 }
@@ -2797,7 +2806,6 @@ static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2797 /* Start data flow (TX/RX) */ 2806 /* Start data flow (TX/RX) */
2798 b43legacy_mac_enable(dev); 2807 b43legacy_mac_enable(dev);
2799 b43legacy_interrupt_enable(dev, dev->irq_savedstate); 2808 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
2800 ieee80211_start_queues(dev->wl->hw);
2801 2809
2802 /* Start maintenance work */ 2810 /* Start maintenance work */
2803 b43legacy_periodic_tasks_setup(dev); 2811 b43legacy_periodic_tasks_setup(dev);
@@ -3399,32 +3407,10 @@ static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw,
3399 int aid, int set) 3407 int aid, int set)
3400{ 3408{
3401 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 3409 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3402 struct sk_buff *beacon;
3403 unsigned long flags;
3404
3405 /* We could modify the existing beacon and set the aid bit in the TIM
3406 * field, but that would probably require resizing and moving of data
3407 * within the beacon template. Simply request a new beacon and let
3408 * mac80211 do the hard work. */
3409 beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3410 if (unlikely(!beacon))
3411 return -ENOMEM;
3412 spin_lock_irqsave(&wl->irq_lock, flags);
3413 b43legacy_update_templates(wl, beacon);
3414 spin_unlock_irqrestore(&wl->irq_lock, flags);
3415
3416 return 0;
3417}
3418
3419static int b43legacy_op_ibss_beacon_update(struct ieee80211_hw *hw,
3420 struct sk_buff *beacon,
3421 struct ieee80211_tx_control *ctl)
3422{
3423 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3424 unsigned long flags; 3410 unsigned long flags;
3425 3411
3426 spin_lock_irqsave(&wl->irq_lock, flags); 3412 spin_lock_irqsave(&wl->irq_lock, flags);
3427 b43legacy_update_templates(wl, beacon); 3413 b43legacy_update_templates(wl);
3428 spin_unlock_irqrestore(&wl->irq_lock, flags); 3414 spin_unlock_irqrestore(&wl->irq_lock, flags);
3429 3415
3430 return 0; 3416 return 0;
@@ -3444,7 +3430,6 @@ static const struct ieee80211_ops b43legacy_hw_ops = {
3444 .stop = b43legacy_op_stop, 3430 .stop = b43legacy_op_stop,
3445 .set_retry_limit = b43legacy_op_set_retry_limit, 3431 .set_retry_limit = b43legacy_op_set_retry_limit,
3446 .set_tim = b43legacy_op_beacon_set_tim, 3432 .set_tim = b43legacy_op_beacon_set_tim,
3447 .beacon_update = b43legacy_op_ibss_beacon_update,
3448}; 3433};
3449 3434
3450/* Hard-reset the chip. Do not call this directly. 3435/* Hard-reset the chip. Do not call this directly.
@@ -3718,10 +3703,9 @@ static int b43legacy_wireless_init(struct ssb_device *dev)
3718 3703
3719 /* fill hw info */ 3704 /* fill hw info */
3720 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | 3705 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3721 IEEE80211_HW_RX_INCLUDES_FCS; 3706 IEEE80211_HW_RX_INCLUDES_FCS |
3722 hw->max_signal = 100; 3707 IEEE80211_HW_SIGNAL_DBM |
3723 hw->max_rssi = -110; 3708 IEEE80211_HW_NOISE_DBM;
3724 hw->max_noise = -110;
3725 hw->queues = 1; /* FIXME: hardware has more queues */ 3709 hw->queues = 1; /* FIXME: hardware has more queues */
3726 SET_IEEE80211_DEV(hw, dev->dev); 3710 SET_IEEE80211_DEV(hw, dev->dev);
3727 if (is_valid_ether_addr(sprom->et1mac)) 3711 if (is_valid_ether_addr(sprom->et1mac))
diff --git a/drivers/net/wireless/b43legacy/phy.c b/drivers/net/wireless/b43legacy/phy.c
index 8e5c09b81871..768cccb9b1ba 100644
--- a/drivers/net/wireless/b43legacy/phy.c
+++ b/drivers/net/wireless/b43legacy/phy.c
@@ -1088,7 +1088,7 @@ static void b43legacy_phy_initg(struct b43legacy_wldev *dev)
1088 * the value 0x7FFFFFFF here. I think that is some weird 1088 * the value 0x7FFFFFFF here. I think that is some weird
1089 * compiler optimization in the original driver. 1089 * compiler optimization in the original driver.
1090 * Essentially, what we do here is resetting all NRSSI LT 1090 * Essentially, what we do here is resetting all NRSSI LT
1091 * entries to -32 (see the limit_value() in nrssi_hw_update()) 1091 * entries to -32 (see the clamp_val() in nrssi_hw_update())
1092 */ 1092 */
1093 b43legacy_nrssi_hw_update(dev, 0xFFFF); 1093 b43legacy_nrssi_hw_update(dev, 0xFFFF);
1094 b43legacy_calc_nrssi_threshold(dev); 1094 b43legacy_calc_nrssi_threshold(dev);
@@ -1756,7 +1756,7 @@ static s8 b43legacy_phy_estimate_power_out(struct b43legacy_wldev *dev, s8 tssi)
1756 switch (phy->type) { 1756 switch (phy->type) {
1757 case B43legacy_PHYTYPE_B: 1757 case B43legacy_PHYTYPE_B:
1758 case B43legacy_PHYTYPE_G: 1758 case B43legacy_PHYTYPE_G:
1759 tmp = limit_value(tmp, 0x00, 0x3F); 1759 tmp = clamp_val(tmp, 0x00, 0x3F);
1760 dbm = phy->tssi2dbm[tmp]; 1760 dbm = phy->tssi2dbm[tmp];
1761 break; 1761 break;
1762 default: 1762 default:
@@ -1859,7 +1859,7 @@ void b43legacy_phy_xmitpower(struct b43legacy_wldev *dev)
1859 1859
1860 /* find the desired power in Q5.2 - power_level is in dBm 1860 /* find the desired power in Q5.2 - power_level is in dBm
1861 * and limit it - max_pwr is already in Q5.2 */ 1861 * and limit it - max_pwr is already in Q5.2 */
1862 desired_pwr = limit_value(phy->power_level << 2, 0, max_pwr); 1862 desired_pwr = clamp_val(phy->power_level << 2, 0, max_pwr);
1863 if (b43legacy_debug(dev, B43legacy_DBG_XMITPOWER)) 1863 if (b43legacy_debug(dev, B43legacy_DBG_XMITPOWER))
1864 b43legacydbg(dev->wl, "Current TX power output: " Q52_FMT 1864 b43legacydbg(dev->wl, "Current TX power output: " Q52_FMT
1865 " dBm, Desired TX power output: " Q52_FMT 1865 " dBm, Desired TX power output: " Q52_FMT
@@ -1905,7 +1905,7 @@ void b43legacy_phy_xmitpower(struct b43legacy_wldev *dev)
1905 radio_attenuation++; 1905 radio_attenuation++;
1906 } 1906 }
1907 } 1907 }
1908 baseband_attenuation = limit_value(baseband_attenuation, 0, 11); 1908 baseband_attenuation = clamp_val(baseband_attenuation, 0, 11);
1909 1909
1910 txpower = phy->txctl1; 1910 txpower = phy->txctl1;
1911 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) { 1911 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
@@ -1933,8 +1933,8 @@ void b43legacy_phy_xmitpower(struct b43legacy_wldev *dev)
1933 } 1933 }
1934 /* Save the control values */ 1934 /* Save the control values */
1935 phy->txctl1 = txpower; 1935 phy->txctl1 = txpower;
1936 baseband_attenuation = limit_value(baseband_attenuation, 0, 11); 1936 baseband_attenuation = clamp_val(baseband_attenuation, 0, 11);
1937 radio_attenuation = limit_value(radio_attenuation, 0, 9); 1937 radio_attenuation = clamp_val(radio_attenuation, 0, 9);
1938 phy->rfatt = radio_attenuation; 1938 phy->rfatt = radio_attenuation;
1939 phy->bbatt = baseband_attenuation; 1939 phy->bbatt = baseband_attenuation;
1940 1940
@@ -1979,7 +1979,7 @@ s8 b43legacy_tssi2dbm_entry(s8 entry [], u8 index, s16 pab0, s16 pab1, s16 pab2)
1979 f = q; 1979 f = q;
1980 i++; 1980 i++;
1981 } while (delta >= 2); 1981 } while (delta >= 2);
1982 entry[index] = limit_value(b43legacy_tssi2dbm_ad(m1 * f, 8192), 1982 entry[index] = clamp_val(b43legacy_tssi2dbm_ad(m1 * f, 8192),
1983 -127, 128); 1983 -127, 128);
1984 return 0; 1984 return 0;
1985} 1985}
diff --git a/drivers/net/wireless/b43legacy/pio.c b/drivers/net/wireless/b43legacy/pio.c
index bcdd54eb2edb..a86c7647fa2d 100644
--- a/drivers/net/wireless/b43legacy/pio.c
+++ b/drivers/net/wireless/b43legacy/pio.c
@@ -196,7 +196,7 @@ static int pio_tx_write_fragment(struct b43legacy_pioqueue *queue,
196 B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0); 196 B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0);
197 err = b43legacy_generate_txhdr(queue->dev, 197 err = b43legacy_generate_txhdr(queue->dev,
198 txhdr, skb->data, skb->len, 198 txhdr, skb->data, skb->len,
199 &packet->txstat.control, 199 IEEE80211_SKB_CB(skb),
200 generate_cookie(queue, packet)); 200 generate_cookie(queue, packet));
201 if (err) 201 if (err)
202 return err; 202 return err;
@@ -463,8 +463,7 @@ err_destroy0:
463} 463}
464 464
465int b43legacy_pio_tx(struct b43legacy_wldev *dev, 465int b43legacy_pio_tx(struct b43legacy_wldev *dev,
466 struct sk_buff *skb, 466 struct sk_buff *skb)
467 struct ieee80211_tx_control *ctl)
468{ 467{
469 struct b43legacy_pioqueue *queue = dev->pio.queue1; 468 struct b43legacy_pioqueue *queue = dev->pio.queue1;
470 struct b43legacy_pio_txpacket *packet; 469 struct b43legacy_pio_txpacket *packet;
@@ -476,9 +475,6 @@ int b43legacy_pio_tx(struct b43legacy_wldev *dev,
476 list); 475 list);
477 packet->skb = skb; 476 packet->skb = skb;
478 477
479 memset(&packet->txstat, 0, sizeof(packet->txstat));
480 memcpy(&packet->txstat.control, ctl, sizeof(*ctl));
481
482 list_move_tail(&packet->list, &queue->txqueue); 478 list_move_tail(&packet->list, &queue->txqueue);
483 queue->nr_txfree--; 479 queue->nr_txfree--;
484 queue->nr_tx_packets++; 480 queue->nr_tx_packets++;
@@ -494,6 +490,7 @@ void b43legacy_pio_handle_txstatus(struct b43legacy_wldev *dev,
494{ 490{
495 struct b43legacy_pioqueue *queue; 491 struct b43legacy_pioqueue *queue;
496 struct b43legacy_pio_txpacket *packet; 492 struct b43legacy_pio_txpacket *packet;
493 struct ieee80211_tx_info *info;
497 494
498 queue = parse_cookie(dev, status->cookie, &packet); 495 queue = parse_cookie(dev, status->cookie, &packet);
499 B43legacy_WARN_ON(!queue); 496 B43legacy_WARN_ON(!queue);
@@ -505,11 +502,13 @@ void b43legacy_pio_handle_txstatus(struct b43legacy_wldev *dev,
505 queue->tx_devq_used -= (packet->skb->len + 502 queue->tx_devq_used -= (packet->skb->len +
506 sizeof(struct b43legacy_txhdr_fw3)); 503 sizeof(struct b43legacy_txhdr_fw3));
507 504
505 info = IEEE80211_SKB_CB(packet->skb);
506 memset(&info->status, 0, sizeof(info->status));
507
508 if (status->acked) 508 if (status->acked)
509 packet->txstat.flags |= IEEE80211_TX_STATUS_ACK; 509 info->flags |= IEEE80211_TX_STAT_ACK;
510 packet->txstat.retry_count = status->frame_count - 1; 510 info->status.retry_count = status->frame_count - 1;
511 ieee80211_tx_status_irqsafe(dev->wl->hw, packet->skb, 511 ieee80211_tx_status_irqsafe(dev->wl->hw, packet->skb);
512 &(packet->txstat));
513 packet->skb = NULL; 512 packet->skb = NULL;
514 513
515 free_txpacket(packet, 1); 514 free_txpacket(packet, 1);
@@ -525,13 +524,11 @@ void b43legacy_pio_get_tx_stats(struct b43legacy_wldev *dev,
525{ 524{
526 struct b43legacy_pio *pio = &dev->pio; 525 struct b43legacy_pio *pio = &dev->pio;
527 struct b43legacy_pioqueue *queue; 526 struct b43legacy_pioqueue *queue;
528 struct ieee80211_tx_queue_stats_data *data;
529 527
530 queue = pio->queue1; 528 queue = pio->queue1;
531 data = &(stats->data[0]); 529 stats[0].len = B43legacy_PIO_MAXTXPACKETS - queue->nr_txfree;
532 data->len = B43legacy_PIO_MAXTXPACKETS - queue->nr_txfree; 530 stats[0].limit = B43legacy_PIO_MAXTXPACKETS;
533 data->limit = B43legacy_PIO_MAXTXPACKETS; 531 stats[0].count = queue->nr_tx_packets;
534 data->count = queue->nr_tx_packets;
535} 532}
536 533
537static void pio_rx_error(struct b43legacy_pioqueue *queue, 534static void pio_rx_error(struct b43legacy_pioqueue *queue,
diff --git a/drivers/net/wireless/b43legacy/pio.h b/drivers/net/wireless/b43legacy/pio.h
index 5bfed0c40030..464fec05a06d 100644
--- a/drivers/net/wireless/b43legacy/pio.h
+++ b/drivers/net/wireless/b43legacy/pio.h
@@ -41,7 +41,6 @@ struct b43legacy_xmitstatus;
41struct b43legacy_pio_txpacket { 41struct b43legacy_pio_txpacket {
42 struct b43legacy_pioqueue *queue; 42 struct b43legacy_pioqueue *queue;
43 struct sk_buff *skb; 43 struct sk_buff *skb;
44 struct ieee80211_tx_status txstat;
45 struct list_head list; 44 struct list_head list;
46}; 45};
47 46
@@ -104,8 +103,7 @@ int b43legacy_pio_init(struct b43legacy_wldev *dev);
104void b43legacy_pio_free(struct b43legacy_wldev *dev); 103void b43legacy_pio_free(struct b43legacy_wldev *dev);
105 104
106int b43legacy_pio_tx(struct b43legacy_wldev *dev, 105int b43legacy_pio_tx(struct b43legacy_wldev *dev,
107 struct sk_buff *skb, 106 struct sk_buff *skb);
108 struct ieee80211_tx_control *ctl);
109void b43legacy_pio_handle_txstatus(struct b43legacy_wldev *dev, 107void b43legacy_pio_handle_txstatus(struct b43legacy_wldev *dev,
110 const struct b43legacy_txstatus *status); 108 const struct b43legacy_txstatus *status);
111void b43legacy_pio_get_tx_stats(struct b43legacy_wldev *dev, 109void b43legacy_pio_get_tx_stats(struct b43legacy_wldev *dev,
@@ -132,8 +130,7 @@ void b43legacy_pio_free(struct b43legacy_wldev *dev)
132} 130}
133static inline 131static inline
134int b43legacy_pio_tx(struct b43legacy_wldev *dev, 132int b43legacy_pio_tx(struct b43legacy_wldev *dev,
135 struct sk_buff *skb, 133 struct sk_buff *skb)
136 struct ieee80211_tx_control *ctl)
137{ 134{
138 return 0; 135 return 0;
139} 136}
diff --git a/drivers/net/wireless/b43legacy/radio.c b/drivers/net/wireless/b43legacy/radio.c
index 955832e8654f..2df545cfad14 100644
--- a/drivers/net/wireless/b43legacy/radio.c
+++ b/drivers/net/wireless/b43legacy/radio.c
@@ -357,7 +357,7 @@ void b43legacy_nrssi_hw_update(struct b43legacy_wldev *dev, u16 val)
357 for (i = 0; i < 64; i++) { 357 for (i = 0; i < 64; i++) {
358 tmp = b43legacy_nrssi_hw_read(dev, i); 358 tmp = b43legacy_nrssi_hw_read(dev, i);
359 tmp -= val; 359 tmp -= val;
360 tmp = limit_value(tmp, -32, 31); 360 tmp = clamp_val(tmp, -32, 31);
361 b43legacy_nrssi_hw_write(dev, i, tmp); 361 b43legacy_nrssi_hw_write(dev, i, tmp);
362 } 362 }
363} 363}
@@ -375,7 +375,7 @@ void b43legacy_nrssi_mem_update(struct b43legacy_wldev *dev)
375 tmp = (i - delta) * phy->nrssislope; 375 tmp = (i - delta) * phy->nrssislope;
376 tmp /= 0x10000; 376 tmp /= 0x10000;
377 tmp += 0x3A; 377 tmp += 0x3A;
378 tmp = limit_value(tmp, 0, 0x3F); 378 tmp = clamp_val(tmp, 0, 0x3F);
379 phy->nrssi_lt[i] = tmp; 379 phy->nrssi_lt[i] = tmp;
380 } 380 }
381} 381}
@@ -839,7 +839,7 @@ void b43legacy_calc_nrssi_threshold(struct b43legacy_wldev *dev)
839 } else 839 } else
840 threshold = phy->nrssi[1] - 5; 840 threshold = phy->nrssi[1] - 5;
841 841
842 threshold = limit_value(threshold, 0, 0x3E); 842 threshold = clamp_val(threshold, 0, 0x3E);
843 b43legacy_phy_read(dev, 0x0020); /* dummy read */ 843 b43legacy_phy_read(dev, 0x0020); /* dummy read */
844 b43legacy_phy_write(dev, 0x0020, (((u16)threshold) << 8) 844 b43legacy_phy_write(dev, 0x0020, (((u16)threshold) << 8)
845 | 0x001C); 845 | 0x001C);
@@ -892,7 +892,7 @@ void b43legacy_calc_nrssi_threshold(struct b43legacy_wldev *dev)
892 else 892 else
893 a += 32; 893 a += 32;
894 a = a >> 6; 894 a = a >> 6;
895 a = limit_value(a, -31, 31); 895 a = clamp_val(a, -31, 31);
896 896
897 b = b * (phy->nrssi[1] - phy->nrssi[0]); 897 b = b * (phy->nrssi[1] - phy->nrssi[0]);
898 b += (phy->nrssi[0] << 6); 898 b += (phy->nrssi[0] << 6);
@@ -901,7 +901,7 @@ void b43legacy_calc_nrssi_threshold(struct b43legacy_wldev *dev)
901 else 901 else
902 b += 32; 902 b += 32;
903 b = b >> 6; 903 b = b >> 6;
904 b = limit_value(b, -31, 31); 904 b = clamp_val(b, -31, 31);
905 905
906 tmp_u16 = b43legacy_phy_read(dev, 0x048A) & 0xF000; 906 tmp_u16 = b43legacy_phy_read(dev, 0x048A) & 0xF000;
907 tmp_u16 |= ((u32)b & 0x0000003F); 907 tmp_u16 |= ((u32)b & 0x0000003F);
@@ -1905,7 +1905,7 @@ void b43legacy_radio_set_txpower_a(struct b43legacy_wldev *dev, u16 txpower)
1905 u16 dac; 1905 u16 dac;
1906 u16 ilt; 1906 u16 ilt;
1907 1907
1908 txpower = limit_value(txpower, 0, 63); 1908 txpower = clamp_val(txpower, 0, 63);
1909 1909
1910 pamp = b43legacy_get_txgain_freq_power_amp(txpower); 1910 pamp = b43legacy_get_txgain_freq_power_amp(txpower);
1911 pamp <<= 5; 1911 pamp <<= 5;
diff --git a/drivers/net/wireless/b43legacy/rfkill.c b/drivers/net/wireless/b43legacy/rfkill.c
index d178dfbb1c9f..476add97e974 100644
--- a/drivers/net/wireless/b43legacy/rfkill.c
+++ b/drivers/net/wireless/b43legacy/rfkill.c
@@ -44,6 +44,23 @@ static bool b43legacy_is_hw_radio_enabled(struct b43legacy_wldev *dev)
44 return 0; 44 return 0;
45} 45}
46 46
47/* Update the rfkill state */
48static void b43legacy_rfkill_update_state(struct b43legacy_wldev *dev)
49{
50 struct b43legacy_rfkill *rfk = &(dev->wl->rfkill);
51
52 if (!dev->radio_hw_enable) {
53 rfk->rfkill->state = RFKILL_STATE_HARD_BLOCKED;
54 return;
55 }
56
57 if (!dev->phy.radio_on)
58 rfk->rfkill->state = RFKILL_STATE_SOFT_BLOCKED;
59 else
60 rfk->rfkill->state = RFKILL_STATE_UNBLOCKED;
61
62}
63
47/* The poll callback for the hardware button. */ 64/* The poll callback for the hardware button. */
48static void b43legacy_rfkill_poll(struct input_polled_dev *poll_dev) 65static void b43legacy_rfkill_poll(struct input_polled_dev *poll_dev)
49{ 66{
@@ -61,6 +78,7 @@ static void b43legacy_rfkill_poll(struct input_polled_dev *poll_dev)
61 if (unlikely(enabled != dev->radio_hw_enable)) { 78 if (unlikely(enabled != dev->radio_hw_enable)) {
62 dev->radio_hw_enable = enabled; 79 dev->radio_hw_enable = enabled;
63 report_change = 1; 80 report_change = 1;
81 b43legacy_rfkill_update_state(dev);
64 b43legacyinfo(wl, "Radio hardware status changed to %s\n", 82 b43legacyinfo(wl, "Radio hardware status changed to %s\n",
65 enabled ? "ENABLED" : "DISABLED"); 83 enabled ? "ENABLED" : "DISABLED");
66 } 84 }
@@ -90,7 +108,7 @@ static int b43legacy_rfkill_soft_toggle(void *data, enum rfkill_state state)
90 goto out_unlock; 108 goto out_unlock;
91 err = 0; 109 err = 0;
92 switch (state) { 110 switch (state) {
93 case RFKILL_STATE_ON: 111 case RFKILL_STATE_UNBLOCKED:
94 if (!dev->radio_hw_enable) { 112 if (!dev->radio_hw_enable) {
95 /* No luck. We can't toggle the hardware RF-kill 113 /* No luck. We can't toggle the hardware RF-kill
96 * button from software. */ 114 * button from software. */
@@ -100,10 +118,14 @@ static int b43legacy_rfkill_soft_toggle(void *data, enum rfkill_state state)
100 if (!dev->phy.radio_on) 118 if (!dev->phy.radio_on)
101 b43legacy_radio_turn_on(dev); 119 b43legacy_radio_turn_on(dev);
102 break; 120 break;
103 case RFKILL_STATE_OFF: 121 case RFKILL_STATE_SOFT_BLOCKED:
104 if (dev->phy.radio_on) 122 if (dev->phy.radio_on)
105 b43legacy_radio_turn_off(dev, 0); 123 b43legacy_radio_turn_off(dev, 0);
106 break; 124 break;
125 default:
126 b43legacywarn(wl, "Received unexpected rfkill state %d.\n",
127 state);
128 break;
107 } 129 }
108 130
109out_unlock: 131out_unlock:
@@ -135,7 +157,7 @@ void b43legacy_rfkill_init(struct b43legacy_wldev *dev)
135 snprintf(rfk->name, sizeof(rfk->name), 157 snprintf(rfk->name, sizeof(rfk->name),
136 "b43legacy-%s", wiphy_name(wl->hw->wiphy)); 158 "b43legacy-%s", wiphy_name(wl->hw->wiphy));
137 rfk->rfkill->name = rfk->name; 159 rfk->rfkill->name = rfk->name;
138 rfk->rfkill->state = RFKILL_STATE_ON; 160 rfk->rfkill->state = RFKILL_STATE_UNBLOCKED;
139 rfk->rfkill->data = dev; 161 rfk->rfkill->data = dev;
140 rfk->rfkill->toggle_radio = b43legacy_rfkill_soft_toggle; 162 rfk->rfkill->toggle_radio = b43legacy_rfkill_soft_toggle;
141 rfk->rfkill->user_claim_unsupported = 1; 163 rfk->rfkill->user_claim_unsupported = 1;
diff --git a/drivers/net/wireless/b43legacy/xmit.c b/drivers/net/wireless/b43legacy/xmit.c
index dcad2491a606..e969ed8d412d 100644
--- a/drivers/net/wireless/b43legacy/xmit.c
+++ b/drivers/net/wireless/b43legacy/xmit.c
@@ -188,11 +188,11 @@ static int generate_txhdr_fw3(struct b43legacy_wldev *dev,
188 struct b43legacy_txhdr_fw3 *txhdr, 188 struct b43legacy_txhdr_fw3 *txhdr,
189 const unsigned char *fragment_data, 189 const unsigned char *fragment_data,
190 unsigned int fragment_len, 190 unsigned int fragment_len,
191 const struct ieee80211_tx_control *txctl, 191 const struct ieee80211_tx_info *info,
192 u16 cookie) 192 u16 cookie)
193{ 193{
194 const struct ieee80211_hdr *wlhdr; 194 const struct ieee80211_hdr *wlhdr;
195 int use_encryption = (!(txctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)); 195 int use_encryption = (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT));
196 u16 fctl; 196 u16 fctl;
197 u8 rate; 197 u8 rate;
198 struct ieee80211_rate *rate_fb; 198 struct ieee80211_rate *rate_fb;
@@ -201,15 +201,18 @@ static int generate_txhdr_fw3(struct b43legacy_wldev *dev,
201 unsigned int plcp_fragment_len; 201 unsigned int plcp_fragment_len;
202 u32 mac_ctl = 0; 202 u32 mac_ctl = 0;
203 u16 phy_ctl = 0; 203 u16 phy_ctl = 0;
204 struct ieee80211_rate *tx_rate;
204 205
205 wlhdr = (const struct ieee80211_hdr *)fragment_data; 206 wlhdr = (const struct ieee80211_hdr *)fragment_data;
206 fctl = le16_to_cpu(wlhdr->frame_control); 207 fctl = le16_to_cpu(wlhdr->frame_control);
207 208
208 memset(txhdr, 0, sizeof(*txhdr)); 209 memset(txhdr, 0, sizeof(*txhdr));
209 210
210 rate = txctl->tx_rate->hw_value; 211 tx_rate = ieee80211_get_tx_rate(dev->wl->hw, info);
212
213 rate = tx_rate->hw_value;
211 rate_ofdm = b43legacy_is_ofdm_rate(rate); 214 rate_ofdm = b43legacy_is_ofdm_rate(rate);
212 rate_fb = txctl->alt_retry_rate ? : txctl->tx_rate; 215 rate_fb = ieee80211_get_alt_retry_rate(dev->wl->hw, info) ? : tx_rate;
213 rate_fb_ofdm = b43legacy_is_ofdm_rate(rate_fb->hw_value); 216 rate_fb_ofdm = b43legacy_is_ofdm_rate(rate_fb->hw_value);
214 217
215 txhdr->mac_frame_ctl = wlhdr->frame_control; 218 txhdr->mac_frame_ctl = wlhdr->frame_control;
@@ -225,14 +228,14 @@ static int generate_txhdr_fw3(struct b43legacy_wldev *dev,
225 txhdr->dur_fb = wlhdr->duration_id; 228 txhdr->dur_fb = wlhdr->duration_id;
226 } else { 229 } else {
227 txhdr->dur_fb = ieee80211_generic_frame_duration(dev->wl->hw, 230 txhdr->dur_fb = ieee80211_generic_frame_duration(dev->wl->hw,
228 txctl->vif, 231 info->control.vif,
229 fragment_len, 232 fragment_len,
230 rate_fb); 233 rate_fb);
231 } 234 }
232 235
233 plcp_fragment_len = fragment_len + FCS_LEN; 236 plcp_fragment_len = fragment_len + FCS_LEN;
234 if (use_encryption) { 237 if (use_encryption) {
235 u8 key_idx = (u16)(txctl->key_idx); 238 u8 key_idx = info->control.hw_key->hw_key_idx;
236 struct b43legacy_key *key; 239 struct b43legacy_key *key;
237 int wlhdr_len; 240 int wlhdr_len;
238 size_t iv_len; 241 size_t iv_len;
@@ -242,7 +245,7 @@ static int generate_txhdr_fw3(struct b43legacy_wldev *dev,
242 245
243 if (key->enabled) { 246 if (key->enabled) {
244 /* Hardware appends ICV. */ 247 /* Hardware appends ICV. */
245 plcp_fragment_len += txctl->icv_len; 248 plcp_fragment_len += info->control.icv_len;
246 249
247 key_idx = b43legacy_kidx_to_fw(dev, key_idx); 250 key_idx = b43legacy_kidx_to_fw(dev, key_idx);
248 mac_ctl |= (key_idx << B43legacy_TX4_MAC_KEYIDX_SHIFT) & 251 mac_ctl |= (key_idx << B43legacy_TX4_MAC_KEYIDX_SHIFT) &
@@ -251,7 +254,7 @@ static int generate_txhdr_fw3(struct b43legacy_wldev *dev,
251 B43legacy_TX4_MAC_KEYALG_SHIFT) & 254 B43legacy_TX4_MAC_KEYALG_SHIFT) &
252 B43legacy_TX4_MAC_KEYALG; 255 B43legacy_TX4_MAC_KEYALG;
253 wlhdr_len = ieee80211_get_hdrlen(fctl); 256 wlhdr_len = ieee80211_get_hdrlen(fctl);
254 iv_len = min((size_t)txctl->iv_len, 257 iv_len = min((size_t)info->control.iv_len,
255 ARRAY_SIZE(txhdr->iv)); 258 ARRAY_SIZE(txhdr->iv));
256 memcpy(txhdr->iv, ((u8 *)wlhdr) + wlhdr_len, iv_len); 259 memcpy(txhdr->iv, ((u8 *)wlhdr) + wlhdr_len, iv_len);
257 } else { 260 } else {
@@ -275,7 +278,7 @@ static int generate_txhdr_fw3(struct b43legacy_wldev *dev,
275 phy_ctl |= B43legacy_TX4_PHY_OFDM; 278 phy_ctl |= B43legacy_TX4_PHY_OFDM;
276 if (dev->short_preamble) 279 if (dev->short_preamble)
277 phy_ctl |= B43legacy_TX4_PHY_SHORTPRMBL; 280 phy_ctl |= B43legacy_TX4_PHY_SHORTPRMBL;
278 switch (txctl->antenna_sel_tx) { 281 switch (info->antenna_sel_tx) {
279 case 0: 282 case 0:
280 phy_ctl |= B43legacy_TX4_PHY_ANTLAST; 283 phy_ctl |= B43legacy_TX4_PHY_ANTLAST;
281 break; 284 break;
@@ -290,21 +293,20 @@ static int generate_txhdr_fw3(struct b43legacy_wldev *dev,
290 } 293 }
291 294
292 /* MAC control */ 295 /* MAC control */
293 if (!(txctl->flags & IEEE80211_TXCTL_NO_ACK)) 296 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
294 mac_ctl |= B43legacy_TX4_MAC_ACK; 297 mac_ctl |= B43legacy_TX4_MAC_ACK;
295 if (!(((fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL) && 298 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
296 ((fctl & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_PSPOLL)))
297 mac_ctl |= B43legacy_TX4_MAC_HWSEQ; 299 mac_ctl |= B43legacy_TX4_MAC_HWSEQ;
298 if (txctl->flags & IEEE80211_TXCTL_FIRST_FRAGMENT) 300 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
299 mac_ctl |= B43legacy_TX4_MAC_STMSDU; 301 mac_ctl |= B43legacy_TX4_MAC_STMSDU;
300 if (rate_fb_ofdm) 302 if (rate_fb_ofdm)
301 mac_ctl |= B43legacy_TX4_MAC_FALLBACKOFDM; 303 mac_ctl |= B43legacy_TX4_MAC_FALLBACKOFDM;
302 if (txctl->flags & IEEE80211_TXCTL_LONG_RETRY_LIMIT) 304 if (info->flags & IEEE80211_TX_CTL_LONG_RETRY_LIMIT)
303 mac_ctl |= B43legacy_TX4_MAC_LONGFRAME; 305 mac_ctl |= B43legacy_TX4_MAC_LONGFRAME;
304 306
305 /* Generate the RTS or CTS-to-self frame */ 307 /* Generate the RTS or CTS-to-self frame */
306 if ((txctl->flags & IEEE80211_TXCTL_USE_RTS_CTS) || 308 if ((info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) ||
307 (txctl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)) { 309 (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT)) {
308 unsigned int len; 310 unsigned int len;
309 struct ieee80211_hdr *hdr; 311 struct ieee80211_hdr *hdr;
310 int rts_rate; 312 int rts_rate;
@@ -312,26 +314,26 @@ static int generate_txhdr_fw3(struct b43legacy_wldev *dev,
312 int rts_rate_ofdm; 314 int rts_rate_ofdm;
313 int rts_rate_fb_ofdm; 315 int rts_rate_fb_ofdm;
314 316
315 rts_rate = txctl->rts_cts_rate->hw_value; 317 rts_rate = ieee80211_get_rts_cts_rate(dev->wl->hw, info)->hw_value;
316 rts_rate_ofdm = b43legacy_is_ofdm_rate(rts_rate); 318 rts_rate_ofdm = b43legacy_is_ofdm_rate(rts_rate);
317 rts_rate_fb = b43legacy_calc_fallback_rate(rts_rate); 319 rts_rate_fb = b43legacy_calc_fallback_rate(rts_rate);
318 rts_rate_fb_ofdm = b43legacy_is_ofdm_rate(rts_rate_fb); 320 rts_rate_fb_ofdm = b43legacy_is_ofdm_rate(rts_rate_fb);
319 if (rts_rate_fb_ofdm) 321 if (rts_rate_fb_ofdm)
320 mac_ctl |= B43legacy_TX4_MAC_CTSFALLBACKOFDM; 322 mac_ctl |= B43legacy_TX4_MAC_CTSFALLBACKOFDM;
321 323
322 if (txctl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) { 324 if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
323 ieee80211_ctstoself_get(dev->wl->hw, 325 ieee80211_ctstoself_get(dev->wl->hw,
324 txctl->vif, 326 info->control.vif,
325 fragment_data, 327 fragment_data,
326 fragment_len, txctl, 328 fragment_len, info,
327 (struct ieee80211_cts *) 329 (struct ieee80211_cts *)
328 (txhdr->rts_frame)); 330 (txhdr->rts_frame));
329 mac_ctl |= B43legacy_TX4_MAC_SENDCTS; 331 mac_ctl |= B43legacy_TX4_MAC_SENDCTS;
330 len = sizeof(struct ieee80211_cts); 332 len = sizeof(struct ieee80211_cts);
331 } else { 333 } else {
332 ieee80211_rts_get(dev->wl->hw, 334 ieee80211_rts_get(dev->wl->hw,
333 txctl->vif, 335 info->control.vif,
334 fragment_data, fragment_len, txctl, 336 fragment_data, fragment_len, info,
335 (struct ieee80211_rts *) 337 (struct ieee80211_rts *)
336 (txhdr->rts_frame)); 338 (txhdr->rts_frame));
337 mac_ctl |= B43legacy_TX4_MAC_SENDRTS; 339 mac_ctl |= B43legacy_TX4_MAC_SENDRTS;
@@ -362,12 +364,12 @@ int b43legacy_generate_txhdr(struct b43legacy_wldev *dev,
362 u8 *txhdr, 364 u8 *txhdr,
363 const unsigned char *fragment_data, 365 const unsigned char *fragment_data,
364 unsigned int fragment_len, 366 unsigned int fragment_len,
365 const struct ieee80211_tx_control *txctl, 367 const struct ieee80211_tx_info *info,
366 u16 cookie) 368 u16 cookie)
367{ 369{
368 return generate_txhdr_fw3(dev, (struct b43legacy_txhdr_fw3 *)txhdr, 370 return generate_txhdr_fw3(dev, (struct b43legacy_txhdr_fw3 *)txhdr,
369 fragment_data, fragment_len, 371 fragment_data, fragment_len,
370 txctl, cookie); 372 info, cookie);
371} 373}
372 374
373static s8 b43legacy_rssi_postprocess(struct b43legacy_wldev *dev, 375static s8 b43legacy_rssi_postprocess(struct b43legacy_wldev *dev,
@@ -439,7 +441,7 @@ void b43legacy_rx(struct b43legacy_wldev *dev,
439 struct b43legacy_plcp_hdr6 *plcp; 441 struct b43legacy_plcp_hdr6 *plcp;
440 struct ieee80211_hdr *wlhdr; 442 struct ieee80211_hdr *wlhdr;
441 const struct b43legacy_rxhdr_fw3 *rxhdr = _rxhdr; 443 const struct b43legacy_rxhdr_fw3 *rxhdr = _rxhdr;
442 u16 fctl; 444 __le16 fctl;
443 u16 phystat0; 445 u16 phystat0;
444 u16 phystat3; 446 u16 phystat3;
445 u16 chanstat; 447 u16 chanstat;
@@ -477,7 +479,7 @@ void b43legacy_rx(struct b43legacy_wldev *dev,
477 goto drop; 479 goto drop;
478 } 480 }
479 wlhdr = (struct ieee80211_hdr *)(skb->data); 481 wlhdr = (struct ieee80211_hdr *)(skb->data);
480 fctl = le16_to_cpu(wlhdr->frame_control); 482 fctl = wlhdr->frame_control;
481 483
482 if ((macstat & B43legacy_RX_MAC_DEC) && 484 if ((macstat & B43legacy_RX_MAC_DEC) &&
483 !(macstat & B43legacy_RX_MAC_DECERR)) { 485 !(macstat & B43legacy_RX_MAC_DECERR)) {
@@ -496,11 +498,11 @@ void b43legacy_rx(struct b43legacy_wldev *dev,
496 498
497 if (dev->key[keyidx].algorithm != B43legacy_SEC_ALGO_NONE) { 499 if (dev->key[keyidx].algorithm != B43legacy_SEC_ALGO_NONE) {
498 /* Remove PROTECTED flag to mark it as decrypted. */ 500 /* Remove PROTECTED flag to mark it as decrypted. */
499 B43legacy_WARN_ON(!(fctl & IEEE80211_FCTL_PROTECTED)); 501 B43legacy_WARN_ON(!ieee80211_has_protected(fctl));
500 fctl &= ~IEEE80211_FCTL_PROTECTED; 502 fctl &= ~cpu_to_le16(IEEE80211_FCTL_PROTECTED);
501 wlhdr->frame_control = cpu_to_le16(fctl); 503 wlhdr->frame_control = fctl;
502 504
503 wlhdr_len = ieee80211_get_hdrlen(fctl); 505 wlhdr_len = ieee80211_hdrlen(fctl);
504 if (unlikely(skb->len < (wlhdr_len + 3))) { 506 if (unlikely(skb->len < (wlhdr_len + 3))) {
505 b43legacydbg(dev->wl, "RX: Packet size" 507 b43legacydbg(dev->wl, "RX: Packet size"
506 " underrun3\n"); 508 " underrun3\n");
@@ -532,12 +534,12 @@ void b43legacy_rx(struct b43legacy_wldev *dev,
532 } 534 }
533 } 535 }
534 536
535 status.ssi = b43legacy_rssi_postprocess(dev, jssi, 537 status.signal = b43legacy_rssi_postprocess(dev, jssi,
536 (phystat0 & B43legacy_RX_PHYST0_OFDM), 538 (phystat0 & B43legacy_RX_PHYST0_OFDM),
537 (phystat0 & B43legacy_RX_PHYST0_GAINCTL), 539 (phystat0 & B43legacy_RX_PHYST0_GAINCTL),
538 (phystat3 & B43legacy_RX_PHYST3_TRSTATE)); 540 (phystat3 & B43legacy_RX_PHYST3_TRSTATE));
539 status.noise = dev->stats.link_noise; 541 status.noise = dev->stats.link_noise;
540 status.signal = (jssi * 100) / B43legacy_RX_MAX_SSI; 542 status.qual = (jssi * 100) / B43legacy_RX_MAX_SSI;
541 /* change to support A PHY */ 543 /* change to support A PHY */
542 if (phystat0 & B43legacy_RX_PHYST0_OFDM) 544 if (phystat0 & B43legacy_RX_PHYST0_OFDM)
543 status.rate_idx = b43legacy_plcp_get_bitrate_idx_ofdm(plcp, false); 545 status.rate_idx = b43legacy_plcp_get_bitrate_idx_ofdm(plcp, false);
@@ -553,9 +555,7 @@ void b43legacy_rx(struct b43legacy_wldev *dev,
553 * of timestamp, i.e. about 65 milliseconds after the PHY received 555 * of timestamp, i.e. about 65 milliseconds after the PHY received
554 * the first symbol. 556 * the first symbol.
555 */ 557 */
556 if (((fctl & (IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) 558 if (ieee80211_is_beacon(fctl) || dev->wl->radiotap_enabled) {
557 == (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON)) ||
558 dev->wl->radiotap_enabled) {
559 u16 low_mactime_now; 559 u16 low_mactime_now;
560 560
561 b43legacy_tsf_read(dev, &status.mactime); 561 b43legacy_tsf_read(dev, &status.mactime);
diff --git a/drivers/net/wireless/b43legacy/xmit.h b/drivers/net/wireless/b43legacy/xmit.h
index bab47928a0c9..e56777e0feab 100644
--- a/drivers/net/wireless/b43legacy/xmit.h
+++ b/drivers/net/wireless/b43legacy/xmit.h
@@ -80,7 +80,7 @@ int b43legacy_generate_txhdr(struct b43legacy_wldev *dev,
80 u8 *txhdr, 80 u8 *txhdr,
81 const unsigned char *fragment_data, 81 const unsigned char *fragment_data,
82 unsigned int fragment_len, 82 unsigned int fragment_len,
83 const struct ieee80211_tx_control *txctl, 83 const struct ieee80211_tx_info *info,
84 u16 cookie); 84 u16 cookie);
85 85
86 86
diff --git a/drivers/net/wireless/hostap/hostap.h b/drivers/net/wireless/hostap/hostap.h
index 547ba84dc797..3a386a636cca 100644
--- a/drivers/net/wireless/hostap/hostap.h
+++ b/drivers/net/wireless/hostap/hostap.h
@@ -67,7 +67,8 @@ void * ap_crypt_get_ptrs(struct ap_data *ap, u8 *addr, int permanent,
67int prism2_ap_get_sta_qual(local_info_t *local, struct sockaddr addr[], 67int prism2_ap_get_sta_qual(local_info_t *local, struct sockaddr addr[],
68 struct iw_quality qual[], int buf_size, 68 struct iw_quality qual[], int buf_size,
69 int aplist); 69 int aplist);
70int prism2_ap_translate_scan(struct net_device *dev, char *buffer); 70int prism2_ap_translate_scan(struct net_device *dev,
71 struct iw_request_info *info, char *buffer);
71int prism2_hostapd(struct ap_data *ap, struct prism2_hostapd_param *param); 72int prism2_hostapd(struct ap_data *ap, struct prism2_hostapd_param *param);
72 73
73 74
diff --git a/drivers/net/wireless/hostap/hostap_80211_rx.c b/drivers/net/wireless/hostap/hostap_80211_rx.c
index 020f450e9dba..f106bc1585a4 100644
--- a/drivers/net/wireless/hostap/hostap_80211_rx.c
+++ b/drivers/net/wireless/hostap/hostap_80211_rx.c
@@ -78,6 +78,9 @@ int prism2_rx_80211(struct net_device *dev, struct sk_buff *skb,
78 prism_header = 2; 78 prism_header = 2;
79 phdrlen = sizeof(struct linux_wlan_ng_cap_hdr); 79 phdrlen = sizeof(struct linux_wlan_ng_cap_hdr);
80 } 80 }
81 } else if (dev->type == ARPHRD_IEEE80211_RADIOTAP) {
82 prism_header = 3;
83 phdrlen = sizeof(struct hostap_radiotap_rx);
81 } else { 84 } else {
82 prism_header = 0; 85 prism_header = 0;
83 phdrlen = 0; 86 phdrlen = 0;
@@ -165,6 +168,24 @@ hdr->f.status = s; hdr->f.len = l; hdr->f.data = d
165 hdr->ssi_noise = htonl(rx_stats->noise); 168 hdr->ssi_noise = htonl(rx_stats->noise);
166 hdr->preamble = htonl(0); /* unknown */ 169 hdr->preamble = htonl(0); /* unknown */
167 hdr->encoding = htonl(1); /* cck */ 170 hdr->encoding = htonl(1); /* cck */
171 } else if (prism_header == 3) {
172 struct hostap_radiotap_rx *hdr;
173 hdr = (struct hostap_radiotap_rx *)skb_push(skb, phdrlen);
174 memset(hdr, 0, phdrlen);
175 hdr->hdr.it_len = cpu_to_le16(phdrlen);
176 hdr->hdr.it_present =
177 cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
178 (1 << IEEE80211_RADIOTAP_CHANNEL) |
179 (1 << IEEE80211_RADIOTAP_RATE) |
180 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
181 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE));
182 hdr->tsft = cpu_to_le64(rx_stats->mac_time);
183 hdr->chan_freq = cpu_to_le16(freq_list[local->channel - 1]);
184 hdr->chan_flags = cpu_to_le16(IEEE80211_CHAN_CCK |
185 IEEE80211_CHAN_2GHZ);
186 hdr->rate = rx_stats->rate / 5;
187 hdr->dbm_antsignal = rx_stats->signal;
188 hdr->dbm_antnoise = rx_stats->noise;
168 } 189 }
169 190
170 ret = skb->len - phdrlen; 191 ret = skb->len - phdrlen;
diff --git a/drivers/net/wireless/hostap/hostap_ap.c b/drivers/net/wireless/hostap/hostap_ap.c
index ab981afd481d..af3d4ef2a80b 100644
--- a/drivers/net/wireless/hostap/hostap_ap.c
+++ b/drivers/net/wireless/hostap/hostap_ap.c
@@ -2420,7 +2420,8 @@ int prism2_ap_get_sta_qual(local_info_t *local, struct sockaddr addr[],
2420 2420
2421/* Translate our list of Access Points & Stations to a card independant 2421/* Translate our list of Access Points & Stations to a card independant
2422 * format that the Wireless Tools will understand - Jean II */ 2422 * format that the Wireless Tools will understand - Jean II */
2423int prism2_ap_translate_scan(struct net_device *dev, char *buffer) 2423int prism2_ap_translate_scan(struct net_device *dev,
2424 struct iw_request_info *info, char *buffer)
2424{ 2425{
2425 struct hostap_interface *iface; 2426 struct hostap_interface *iface;
2426 local_info_t *local; 2427 local_info_t *local;
@@ -2449,8 +2450,8 @@ int prism2_ap_translate_scan(struct net_device *dev, char *buffer)
2449 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 2450 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
2450 memcpy(iwe.u.ap_addr.sa_data, sta->addr, ETH_ALEN); 2451 memcpy(iwe.u.ap_addr.sa_data, sta->addr, ETH_ALEN);
2451 iwe.len = IW_EV_ADDR_LEN; 2452 iwe.len = IW_EV_ADDR_LEN;
2452 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, 2453 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
2453 IW_EV_ADDR_LEN); 2454 &iwe, IW_EV_ADDR_LEN);
2454 2455
2455 /* Use the mode to indicate if it's a station or 2456 /* Use the mode to indicate if it's a station or
2456 * an Access Point */ 2457 * an Access Point */
@@ -2461,8 +2462,8 @@ int prism2_ap_translate_scan(struct net_device *dev, char *buffer)
2461 else 2462 else
2462 iwe.u.mode = IW_MODE_INFRA; 2463 iwe.u.mode = IW_MODE_INFRA;
2463 iwe.len = IW_EV_UINT_LEN; 2464 iwe.len = IW_EV_UINT_LEN;
2464 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, 2465 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
2465 IW_EV_UINT_LEN); 2466 &iwe, IW_EV_UINT_LEN);
2466 2467
2467 /* Some quality */ 2468 /* Some quality */
2468 memset(&iwe, 0, sizeof(iwe)); 2469 memset(&iwe, 0, sizeof(iwe));
@@ -2477,8 +2478,8 @@ int prism2_ap_translate_scan(struct net_device *dev, char *buffer)
2477 iwe.u.qual.noise = HFA384X_LEVEL_TO_dBm(sta->last_rx_silence); 2478 iwe.u.qual.noise = HFA384X_LEVEL_TO_dBm(sta->last_rx_silence);
2478 iwe.u.qual.updated = sta->last_rx_updated; 2479 iwe.u.qual.updated = sta->last_rx_updated;
2479 iwe.len = IW_EV_QUAL_LEN; 2480 iwe.len = IW_EV_QUAL_LEN;
2480 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, 2481 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
2481 IW_EV_QUAL_LEN); 2482 &iwe, IW_EV_QUAL_LEN);
2482 2483
2483#ifndef PRISM2_NO_KERNEL_IEEE80211_MGMT 2484#ifndef PRISM2_NO_KERNEL_IEEE80211_MGMT
2484 if (sta->ap) { 2485 if (sta->ap) {
@@ -2486,8 +2487,8 @@ int prism2_ap_translate_scan(struct net_device *dev, char *buffer)
2486 iwe.cmd = SIOCGIWESSID; 2487 iwe.cmd = SIOCGIWESSID;
2487 iwe.u.data.length = sta->u.ap.ssid_len; 2488 iwe.u.data.length = sta->u.ap.ssid_len;
2488 iwe.u.data.flags = 1; 2489 iwe.u.data.flags = 1;
2489 current_ev = iwe_stream_add_point(current_ev, end_buf, 2490 current_ev = iwe_stream_add_point(info, current_ev,
2490 &iwe, 2491 end_buf, &iwe,
2491 sta->u.ap.ssid); 2492 sta->u.ap.ssid);
2492 2493
2493 memset(&iwe, 0, sizeof(iwe)); 2494 memset(&iwe, 0, sizeof(iwe));
@@ -2497,10 +2498,9 @@ int prism2_ap_translate_scan(struct net_device *dev, char *buffer)
2497 IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; 2498 IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
2498 else 2499 else
2499 iwe.u.data.flags = IW_ENCODE_DISABLED; 2500 iwe.u.data.flags = IW_ENCODE_DISABLED;
2500 current_ev = iwe_stream_add_point(current_ev, end_buf, 2501 current_ev = iwe_stream_add_point(info, current_ev,
2501 &iwe, 2502 end_buf, &iwe,
2502 sta->u.ap.ssid 2503 sta->u.ap.ssid);
2503 /* 0 byte memcpy */);
2504 2504
2505 if (sta->u.ap.channel > 0 && 2505 if (sta->u.ap.channel > 0 &&
2506 sta->u.ap.channel <= FREQ_COUNT) { 2506 sta->u.ap.channel <= FREQ_COUNT) {
@@ -2510,7 +2510,7 @@ int prism2_ap_translate_scan(struct net_device *dev, char *buffer)
2510 * 100000; 2510 * 100000;
2511 iwe.u.freq.e = 1; 2511 iwe.u.freq.e = 1;
2512 current_ev = iwe_stream_add_event( 2512 current_ev = iwe_stream_add_event(
2513 current_ev, end_buf, &iwe, 2513 info, current_ev, end_buf, &iwe,
2514 IW_EV_FREQ_LEN); 2514 IW_EV_FREQ_LEN);
2515 } 2515 }
2516 2516
@@ -2519,8 +2519,8 @@ int prism2_ap_translate_scan(struct net_device *dev, char *buffer)
2519 sprintf(buf, "beacon_interval=%d", 2519 sprintf(buf, "beacon_interval=%d",
2520 sta->listen_interval); 2520 sta->listen_interval);
2521 iwe.u.data.length = strlen(buf); 2521 iwe.u.data.length = strlen(buf);
2522 current_ev = iwe_stream_add_point(current_ev, end_buf, 2522 current_ev = iwe_stream_add_point(info, current_ev,
2523 &iwe, buf); 2523 end_buf, &iwe, buf);
2524 } 2524 }
2525#endif /* PRISM2_NO_KERNEL_IEEE80211_MGMT */ 2525#endif /* PRISM2_NO_KERNEL_IEEE80211_MGMT */
2526 2526
diff --git a/drivers/net/wireless/hostap/hostap_hw.c b/drivers/net/wireless/hostap/hostap_hw.c
index 936f52e3d95c..13d5882f1f21 100644
--- a/drivers/net/wireless/hostap/hostap_hw.c
+++ b/drivers/net/wireless/hostap/hostap_hw.c
@@ -3102,6 +3102,18 @@ static void prism2_clear_set_tim_queue(local_info_t *local)
3102 */ 3102 */
3103static struct lock_class_key hostap_netdev_xmit_lock_key; 3103static struct lock_class_key hostap_netdev_xmit_lock_key;
3104 3104
3105static void prism2_set_lockdep_class_one(struct net_device *dev,
3106 struct netdev_queue *txq,
3107 void *_unused)
3108{
3109 lockdep_set_class(&txq->_xmit_lock,
3110 &hostap_netdev_xmit_lock_key);
3111}
3112
3113static void prism2_set_lockdep_class(struct net_device *dev)
3114{
3115 netdev_for_each_tx_queue(dev, prism2_set_lockdep_class_one, NULL);
3116}
3105 3117
3106static struct net_device * 3118static struct net_device *
3107prism2_init_local_data(struct prism2_helper_functions *funcs, int card_idx, 3119prism2_init_local_data(struct prism2_helper_functions *funcs, int card_idx,
@@ -3204,6 +3216,7 @@ prism2_init_local_data(struct prism2_helper_functions *funcs, int card_idx,
3204 local->auth_algs = PRISM2_AUTH_OPEN | PRISM2_AUTH_SHARED_KEY; 3216 local->auth_algs = PRISM2_AUTH_OPEN | PRISM2_AUTH_SHARED_KEY;
3205 local->sram_type = -1; 3217 local->sram_type = -1;
3206 local->scan_channel_mask = 0xffff; 3218 local->scan_channel_mask = 0xffff;
3219 local->monitor_type = PRISM2_MONITOR_RADIOTAP;
3207 3220
3208 /* Initialize task queue structures */ 3221 /* Initialize task queue structures */
3209 INIT_WORK(&local->reset_queue, handle_reset_queue); 3222 INIT_WORK(&local->reset_queue, handle_reset_queue);
@@ -3267,7 +3280,7 @@ while (0)
3267 if (ret >= 0) 3280 if (ret >= 0)
3268 ret = register_netdevice(dev); 3281 ret = register_netdevice(dev);
3269 3282
3270 lockdep_set_class(&dev->_xmit_lock, &hostap_netdev_xmit_lock_key); 3283 prism2_set_lockdep_class(dev);
3271 rtnl_unlock(); 3284 rtnl_unlock();
3272 if (ret < 0) { 3285 if (ret < 0) {
3273 printk(KERN_WARNING "%s: register netdevice failed!\n", 3286 printk(KERN_WARNING "%s: register netdevice failed!\n",
@@ -3416,7 +3429,7 @@ static void prism2_free_local_data(struct net_device *dev)
3416} 3429}
3417 3430
3418 3431
3419#ifndef PRISM2_PLX 3432#if (defined(PRISM2_PCI) && defined(CONFIG_PM)) || defined(PRISM2_PCCARD)
3420static void prism2_suspend(struct net_device *dev) 3433static void prism2_suspend(struct net_device *dev)
3421{ 3434{
3422 struct hostap_interface *iface; 3435 struct hostap_interface *iface;
@@ -3435,7 +3448,7 @@ static void prism2_suspend(struct net_device *dev)
3435 /* Disable hardware and firmware */ 3448 /* Disable hardware and firmware */
3436 prism2_hw_shutdown(dev, 0); 3449 prism2_hw_shutdown(dev, 0);
3437} 3450}
3438#endif /* PRISM2_PLX */ 3451#endif /* (PRISM2_PCI && CONFIG_PM) || PRISM2_PCCARD */
3439 3452
3440 3453
3441/* These might at some point be compiled separately and used as separate 3454/* These might at some point be compiled separately and used as separate
diff --git a/drivers/net/wireless/hostap/hostap_ioctl.c b/drivers/net/wireless/hostap/hostap_ioctl.c
index 0ca0bfeb0ada..3f8b1d7036e5 100644
--- a/drivers/net/wireless/hostap/hostap_ioctl.c
+++ b/drivers/net/wireless/hostap/hostap_ioctl.c
@@ -897,6 +897,8 @@ static void hostap_monitor_set_type(local_info_t *local)
897 if (local->monitor_type == PRISM2_MONITOR_PRISM || 897 if (local->monitor_type == PRISM2_MONITOR_PRISM ||
898 local->monitor_type == PRISM2_MONITOR_CAPHDR) { 898 local->monitor_type == PRISM2_MONITOR_CAPHDR) {
899 dev->type = ARPHRD_IEEE80211_PRISM; 899 dev->type = ARPHRD_IEEE80211_PRISM;
900 } else if (local->monitor_type == PRISM2_MONITOR_RADIOTAP) {
901 dev->type = ARPHRD_IEEE80211_RADIOTAP;
900 } else { 902 } else {
901 dev->type = ARPHRD_IEEE80211; 903 dev->type = ARPHRD_IEEE80211;
902 } 904 }
@@ -1793,6 +1795,7 @@ static int prism2_ioctl_siwscan(struct net_device *dev,
1793 1795
1794#ifndef PRISM2_NO_STATION_MODES 1796#ifndef PRISM2_NO_STATION_MODES
1795static char * __prism2_translate_scan(local_info_t *local, 1797static char * __prism2_translate_scan(local_info_t *local,
1798 struct iw_request_info *info,
1796 struct hfa384x_hostscan_result *scan, 1799 struct hfa384x_hostscan_result *scan,
1797 struct hostap_bss_info *bss, 1800 struct hostap_bss_info *bss,
1798 char *current_ev, char *end_buf) 1801 char *current_ev, char *end_buf)
@@ -1823,7 +1826,7 @@ static char * __prism2_translate_scan(local_info_t *local,
1823 iwe.cmd = SIOCGIWAP; 1826 iwe.cmd = SIOCGIWAP;
1824 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 1827 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
1825 memcpy(iwe.u.ap_addr.sa_data, bssid, ETH_ALEN); 1828 memcpy(iwe.u.ap_addr.sa_data, bssid, ETH_ALEN);
1826 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, 1829 current_ev = iwe_stream_add_event(info, current_ev, end_buf, &iwe,
1827 IW_EV_ADDR_LEN); 1830 IW_EV_ADDR_LEN);
1828 1831
1829 /* Other entries will be displayed in the order we give them */ 1832 /* Other entries will be displayed in the order we give them */
@@ -1832,7 +1835,8 @@ static char * __prism2_translate_scan(local_info_t *local,
1832 iwe.cmd = SIOCGIWESSID; 1835 iwe.cmd = SIOCGIWESSID;
1833 iwe.u.data.length = ssid_len; 1836 iwe.u.data.length = ssid_len;
1834 iwe.u.data.flags = 1; 1837 iwe.u.data.flags = 1;
1835 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, ssid); 1838 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
1839 &iwe, ssid);
1836 1840
1837 memset(&iwe, 0, sizeof(iwe)); 1841 memset(&iwe, 0, sizeof(iwe));
1838 iwe.cmd = SIOCGIWMODE; 1842 iwe.cmd = SIOCGIWMODE;
@@ -1847,8 +1851,8 @@ static char * __prism2_translate_scan(local_info_t *local,
1847 iwe.u.mode = IW_MODE_MASTER; 1851 iwe.u.mode = IW_MODE_MASTER;
1848 else 1852 else
1849 iwe.u.mode = IW_MODE_ADHOC; 1853 iwe.u.mode = IW_MODE_ADHOC;
1850 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, 1854 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
1851 IW_EV_UINT_LEN); 1855 &iwe, IW_EV_UINT_LEN);
1852 } 1856 }
1853 1857
1854 memset(&iwe, 0, sizeof(iwe)); 1858 memset(&iwe, 0, sizeof(iwe));
@@ -1864,8 +1868,8 @@ static char * __prism2_translate_scan(local_info_t *local,
1864 if (chan > 0) { 1868 if (chan > 0) {
1865 iwe.u.freq.m = freq_list[chan - 1] * 100000; 1869 iwe.u.freq.m = freq_list[chan - 1] * 100000;
1866 iwe.u.freq.e = 1; 1870 iwe.u.freq.e = 1;
1867 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, 1871 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
1868 IW_EV_FREQ_LEN); 1872 &iwe, IW_EV_FREQ_LEN);
1869 } 1873 }
1870 1874
1871 if (scan) { 1875 if (scan) {
@@ -1884,8 +1888,8 @@ static char * __prism2_translate_scan(local_info_t *local,
1884 | IW_QUAL_NOISE_UPDATED 1888 | IW_QUAL_NOISE_UPDATED
1885 | IW_QUAL_QUAL_INVALID 1889 | IW_QUAL_QUAL_INVALID
1886 | IW_QUAL_DBM; 1890 | IW_QUAL_DBM;
1887 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, 1891 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
1888 IW_EV_QUAL_LEN); 1892 &iwe, IW_EV_QUAL_LEN);
1889 } 1893 }
1890 1894
1891 memset(&iwe, 0, sizeof(iwe)); 1895 memset(&iwe, 0, sizeof(iwe));
@@ -1895,13 +1899,13 @@ static char * __prism2_translate_scan(local_info_t *local,
1895 else 1899 else
1896 iwe.u.data.flags = IW_ENCODE_DISABLED; 1900 iwe.u.data.flags = IW_ENCODE_DISABLED;
1897 iwe.u.data.length = 0; 1901 iwe.u.data.length = 0;
1898 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, ""); 1902 current_ev = iwe_stream_add_point(info, current_ev, end_buf, &iwe, "");
1899 1903
1900 /* TODO: add SuppRates into BSS table */ 1904 /* TODO: add SuppRates into BSS table */
1901 if (scan) { 1905 if (scan) {
1902 memset(&iwe, 0, sizeof(iwe)); 1906 memset(&iwe, 0, sizeof(iwe));
1903 iwe.cmd = SIOCGIWRATE; 1907 iwe.cmd = SIOCGIWRATE;
1904 current_val = current_ev + IW_EV_LCP_LEN; 1908 current_val = current_ev + iwe_stream_lcp_len(info);
1905 pos = scan->sup_rates; 1909 pos = scan->sup_rates;
1906 for (i = 0; i < sizeof(scan->sup_rates); i++) { 1910 for (i = 0; i < sizeof(scan->sup_rates); i++) {
1907 if (pos[i] == 0) 1911 if (pos[i] == 0)
@@ -1909,11 +1913,11 @@ static char * __prism2_translate_scan(local_info_t *local,
1909 /* Bit rate given in 500 kb/s units (+ 0x80) */ 1913 /* Bit rate given in 500 kb/s units (+ 0x80) */
1910 iwe.u.bitrate.value = ((pos[i] & 0x7f) * 500000); 1914 iwe.u.bitrate.value = ((pos[i] & 0x7f) * 500000);
1911 current_val = iwe_stream_add_value( 1915 current_val = iwe_stream_add_value(
1912 current_ev, current_val, end_buf, &iwe, 1916 info, current_ev, current_val, end_buf, &iwe,
1913 IW_EV_PARAM_LEN); 1917 IW_EV_PARAM_LEN);
1914 } 1918 }
1915 /* Check if we added any event */ 1919 /* Check if we added any event */
1916 if ((current_val - current_ev) > IW_EV_LCP_LEN) 1920 if ((current_val - current_ev) > iwe_stream_lcp_len(info))
1917 current_ev = current_val; 1921 current_ev = current_val;
1918 } 1922 }
1919 1923
@@ -1924,15 +1928,15 @@ static char * __prism2_translate_scan(local_info_t *local,
1924 iwe.cmd = IWEVCUSTOM; 1928 iwe.cmd = IWEVCUSTOM;
1925 sprintf(buf, "bcn_int=%d", le16_to_cpu(scan->beacon_interval)); 1929 sprintf(buf, "bcn_int=%d", le16_to_cpu(scan->beacon_interval));
1926 iwe.u.data.length = strlen(buf); 1930 iwe.u.data.length = strlen(buf);
1927 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, 1931 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
1928 buf); 1932 &iwe, buf);
1929 1933
1930 memset(&iwe, 0, sizeof(iwe)); 1934 memset(&iwe, 0, sizeof(iwe));
1931 iwe.cmd = IWEVCUSTOM; 1935 iwe.cmd = IWEVCUSTOM;
1932 sprintf(buf, "resp_rate=%d", le16_to_cpu(scan->rate)); 1936 sprintf(buf, "resp_rate=%d", le16_to_cpu(scan->rate));
1933 iwe.u.data.length = strlen(buf); 1937 iwe.u.data.length = strlen(buf);
1934 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, 1938 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
1935 buf); 1939 &iwe, buf);
1936 1940
1937 if (local->last_scan_type == PRISM2_HOSTSCAN && 1941 if (local->last_scan_type == PRISM2_HOSTSCAN &&
1938 (capabilities & WLAN_CAPABILITY_IBSS)) { 1942 (capabilities & WLAN_CAPABILITY_IBSS)) {
@@ -1940,8 +1944,8 @@ static char * __prism2_translate_scan(local_info_t *local,
1940 iwe.cmd = IWEVCUSTOM; 1944 iwe.cmd = IWEVCUSTOM;
1941 sprintf(buf, "atim=%d", le16_to_cpu(scan->atim)); 1945 sprintf(buf, "atim=%d", le16_to_cpu(scan->atim));
1942 iwe.u.data.length = strlen(buf); 1946 iwe.u.data.length = strlen(buf);
1943 current_ev = iwe_stream_add_point(current_ev, end_buf, 1947 current_ev = iwe_stream_add_point(info, current_ev,
1944 &iwe, buf); 1948 end_buf, &iwe, buf);
1945 } 1949 }
1946 } 1950 }
1947 kfree(buf); 1951 kfree(buf);
@@ -1950,16 +1954,16 @@ static char * __prism2_translate_scan(local_info_t *local,
1950 memset(&iwe, 0, sizeof(iwe)); 1954 memset(&iwe, 0, sizeof(iwe));
1951 iwe.cmd = IWEVGENIE; 1955 iwe.cmd = IWEVGENIE;
1952 iwe.u.data.length = bss->wpa_ie_len; 1956 iwe.u.data.length = bss->wpa_ie_len;
1953 current_ev = iwe_stream_add_point( 1957 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
1954 current_ev, end_buf, &iwe, bss->wpa_ie); 1958 &iwe, bss->wpa_ie);
1955 } 1959 }
1956 1960
1957 if (bss && bss->rsn_ie_len > 0 && bss->rsn_ie_len <= MAX_WPA_IE_LEN) { 1961 if (bss && bss->rsn_ie_len > 0 && bss->rsn_ie_len <= MAX_WPA_IE_LEN) {
1958 memset(&iwe, 0, sizeof(iwe)); 1962 memset(&iwe, 0, sizeof(iwe));
1959 iwe.cmd = IWEVGENIE; 1963 iwe.cmd = IWEVGENIE;
1960 iwe.u.data.length = bss->rsn_ie_len; 1964 iwe.u.data.length = bss->rsn_ie_len;
1961 current_ev = iwe_stream_add_point( 1965 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
1962 current_ev, end_buf, &iwe, bss->rsn_ie); 1966 &iwe, bss->rsn_ie);
1963 } 1967 }
1964 1968
1965 return current_ev; 1969 return current_ev;
@@ -1969,6 +1973,7 @@ static char * __prism2_translate_scan(local_info_t *local,
1969/* Translate scan data returned from the card to a card independant 1973/* Translate scan data returned from the card to a card independant
1970 * format that the Wireless Tools will understand - Jean II */ 1974 * format that the Wireless Tools will understand - Jean II */
1971static inline int prism2_translate_scan(local_info_t *local, 1975static inline int prism2_translate_scan(local_info_t *local,
1976 struct iw_request_info *info,
1972 char *buffer, int buflen) 1977 char *buffer, int buflen)
1973{ 1978{
1974 struct hfa384x_hostscan_result *scan; 1979 struct hfa384x_hostscan_result *scan;
@@ -1999,13 +2004,14 @@ static inline int prism2_translate_scan(local_info_t *local,
1999 if (memcmp(bss->bssid, scan->bssid, ETH_ALEN) == 0) { 2004 if (memcmp(bss->bssid, scan->bssid, ETH_ALEN) == 0) {
2000 bss->included = 1; 2005 bss->included = 1;
2001 current_ev = __prism2_translate_scan( 2006 current_ev = __prism2_translate_scan(
2002 local, scan, bss, current_ev, end_buf); 2007 local, info, scan, bss, current_ev,
2008 end_buf);
2003 found++; 2009 found++;
2004 } 2010 }
2005 } 2011 }
2006 if (!found) { 2012 if (!found) {
2007 current_ev = __prism2_translate_scan( 2013 current_ev = __prism2_translate_scan(
2008 local, scan, NULL, current_ev, end_buf); 2014 local, info, scan, NULL, current_ev, end_buf);
2009 } 2015 }
2010 /* Check if there is space for one more entry */ 2016 /* Check if there is space for one more entry */
2011 if ((end_buf - current_ev) <= IW_EV_ADDR_LEN) { 2017 if ((end_buf - current_ev) <= IW_EV_ADDR_LEN) {
@@ -2023,7 +2029,7 @@ static inline int prism2_translate_scan(local_info_t *local,
2023 bss = list_entry(ptr, struct hostap_bss_info, list); 2029 bss = list_entry(ptr, struct hostap_bss_info, list);
2024 if (bss->included) 2030 if (bss->included)
2025 continue; 2031 continue;
2026 current_ev = __prism2_translate_scan(local, NULL, bss, 2032 current_ev = __prism2_translate_scan(local, info, NULL, bss,
2027 current_ev, end_buf); 2033 current_ev, end_buf);
2028 /* Check if there is space for one more entry */ 2034 /* Check if there is space for one more entry */
2029 if ((end_buf - current_ev) <= IW_EV_ADDR_LEN) { 2035 if ((end_buf - current_ev) <= IW_EV_ADDR_LEN) {
@@ -2070,7 +2076,7 @@ static inline int prism2_ioctl_giwscan_sta(struct net_device *dev,
2070 } 2076 }
2071 local->scan_timestamp = 0; 2077 local->scan_timestamp = 0;
2072 2078
2073 res = prism2_translate_scan(local, extra, data->length); 2079 res = prism2_translate_scan(local, info, extra, data->length);
2074 2080
2075 if (res >= 0) { 2081 if (res >= 0) {
2076 data->length = res; 2082 data->length = res;
@@ -2103,7 +2109,7 @@ static int prism2_ioctl_giwscan(struct net_device *dev,
2103 * Jean II */ 2109 * Jean II */
2104 2110
2105 /* Translate to WE format */ 2111 /* Translate to WE format */
2106 res = prism2_ap_translate_scan(dev, extra); 2112 res = prism2_ap_translate_scan(dev, info, extra);
2107 if (res >= 0) { 2113 if (res >= 0) {
2108 printk(KERN_DEBUG "Scan result translation succeeded " 2114 printk(KERN_DEBUG "Scan result translation succeeded "
2109 "(length=%d)\n", res); 2115 "(length=%d)\n", res);
@@ -2516,7 +2522,8 @@ static int prism2_ioctl_priv_prism2_param(struct net_device *dev,
2516 case PRISM2_PARAM_MONITOR_TYPE: 2522 case PRISM2_PARAM_MONITOR_TYPE:
2517 if (value != PRISM2_MONITOR_80211 && 2523 if (value != PRISM2_MONITOR_80211 &&
2518 value != PRISM2_MONITOR_CAPHDR && 2524 value != PRISM2_MONITOR_CAPHDR &&
2519 value != PRISM2_MONITOR_PRISM) { 2525 value != PRISM2_MONITOR_PRISM &&
2526 value != PRISM2_MONITOR_RADIOTAP) {
2520 ret = -EINVAL; 2527 ret = -EINVAL;
2521 break; 2528 break;
2522 } 2529 }
diff --git a/drivers/net/wireless/hostap/hostap_main.c b/drivers/net/wireless/hostap/hostap_main.c
index a38e85f334df..756ab56c1f40 100644
--- a/drivers/net/wireless/hostap/hostap_main.c
+++ b/drivers/net/wireless/hostap/hostap_main.c
@@ -597,25 +597,7 @@ void hostap_dump_tx_header(const char *name, const struct hfa384x_tx_frame *tx)
597static int hostap_80211_header_parse(const struct sk_buff *skb, 597static int hostap_80211_header_parse(const struct sk_buff *skb,
598 unsigned char *haddr) 598 unsigned char *haddr)
599{ 599{
600 struct hostap_interface *iface = netdev_priv(skb->dev); 600 memcpy(haddr, skb_mac_header(skb) + 10, ETH_ALEN); /* addr2 */
601 local_info_t *local = iface->local;
602
603 if (local->monitor_type == PRISM2_MONITOR_PRISM ||
604 local->monitor_type == PRISM2_MONITOR_CAPHDR) {
605 const unsigned char *mac = skb_mac_header(skb);
606
607 if (*(u32 *)mac == LWNG_CAP_DID_BASE) {
608 memcpy(haddr,
609 mac + sizeof(struct linux_wlan_ng_prism_hdr) + 10,
610 ETH_ALEN); /* addr2 */
611 } else { /* (*(u32 *)mac == htonl(LWNG_CAPHDR_VERSION)) */
612 memcpy(haddr,
613 mac + sizeof(struct linux_wlan_ng_cap_hdr) + 10,
614 ETH_ALEN); /* addr2 */
615 }
616 } else
617 memcpy(haddr, skb_mac_header(skb) + 10, ETH_ALEN); /* addr2 */
618
619 return ETH_ALEN; 601 return ETH_ALEN;
620} 602}
621 603
diff --git a/drivers/net/wireless/hostap/hostap_wlan.h b/drivers/net/wireless/hostap/hostap_wlan.h
index 15445bce2ac7..ffdf4876121b 100644
--- a/drivers/net/wireless/hostap/hostap_wlan.h
+++ b/drivers/net/wireless/hostap/hostap_wlan.h
@@ -5,6 +5,7 @@
5#include <linux/netdevice.h> 5#include <linux/netdevice.h>
6#include <linux/mutex.h> 6#include <linux/mutex.h>
7#include <net/iw_handler.h> 7#include <net/iw_handler.h>
8#include <net/ieee80211_radiotap.h>
8 9
9#include "hostap_config.h" 10#include "hostap_config.h"
10#include "hostap_common.h" 11#include "hostap_common.h"
@@ -55,6 +56,17 @@ struct linux_wlan_ng_cap_hdr {
55 __be32 encoding; 56 __be32 encoding;
56} __attribute__ ((packed)); 57} __attribute__ ((packed));
57 58
59struct hostap_radiotap_rx {
60 struct ieee80211_radiotap_header hdr;
61 __le64 tsft;
62 u8 rate;
63 u8 padding;
64 __le16 chan_freq;
65 __le16 chan_flags;
66 s8 dbm_antsignal;
67 s8 dbm_antnoise;
68} __attribute__ ((packed));
69
58#define LWNG_CAP_DID_BASE (4 | (1 << 6)) /* section 4, group 1 */ 70#define LWNG_CAP_DID_BASE (4 | (1 << 6)) /* section 4, group 1 */
59#define LWNG_CAPHDR_VERSION 0x80211001 71#define LWNG_CAPHDR_VERSION 0x80211001
60 72
@@ -734,7 +746,7 @@ struct local_info {
734 unsigned long scan_timestamp; /* Time started to scan */ 746 unsigned long scan_timestamp; /* Time started to scan */
735 enum { 747 enum {
736 PRISM2_MONITOR_80211 = 0, PRISM2_MONITOR_PRISM = 1, 748 PRISM2_MONITOR_80211 = 0, PRISM2_MONITOR_PRISM = 1,
737 PRISM2_MONITOR_CAPHDR = 2 749 PRISM2_MONITOR_CAPHDR = 2, PRISM2_MONITOR_RADIOTAP = 3
738 } monitor_type; 750 } monitor_type;
739 int monitor_allow_fcserr; 751 int monitor_allow_fcserr;
740 752
diff --git a/drivers/net/wireless/iwlwifi/Kconfig b/drivers/net/wireless/iwlwifi/Kconfig
index 62fb89d82318..82b66a3d3a5d 100644
--- a/drivers/net/wireless/iwlwifi/Kconfig
+++ b/drivers/net/wireless/iwlwifi/Kconfig
@@ -8,7 +8,6 @@ config IWLCORE
8 select MAC80211_LEDS if IWLWIFI_LEDS 8 select MAC80211_LEDS if IWLWIFI_LEDS
9 select LEDS_CLASS if IWLWIFI_LEDS 9 select LEDS_CLASS if IWLWIFI_LEDS
10 select RFKILL if IWLWIFI_RFKILL 10 select RFKILL if IWLWIFI_RFKILL
11 select RFKILL_INPUT if IWLWIFI_RFKILL
12 11
13config IWLWIFI_LEDS 12config IWLWIFI_LEDS
14 bool 13 bool
@@ -45,14 +44,6 @@ config IWL4965
45 say M here and read <file:Documentation/kbuild/modules.txt>. The 44 say M here and read <file:Documentation/kbuild/modules.txt>. The
46 module will be called iwl4965.ko. 45 module will be called iwl4965.ko.
47 46
48config IWL4965_HT
49 bool "Enable 802.11n HT features in iwl4965 driver"
50 depends on EXPERIMENTAL
51 depends on IWL4965
52 ---help---
53 This option enables IEEE 802.11n High Throughput features
54 for the iwl4965 driver.
55
56config IWL4965_LEDS 47config IWL4965_LEDS
57 bool "Enable LEDS features in iwl4965 driver" 48 bool "Enable LEDS features in iwl4965 driver"
58 depends on IWL4965 49 depends on IWL4965
@@ -67,13 +58,6 @@ config IWL4965_SPECTRUM_MEASUREMENT
67 ---help--- 58 ---help---
68 This option will enable spectrum measurement for the iwl4965 driver. 59 This option will enable spectrum measurement for the iwl4965 driver.
69 60
70config IWL4965_SENSITIVITY
71 bool "Enable Sensitivity Calibration in iwl4965 driver"
72 depends on IWL4965
73 ---help---
74 This option will enable sensitivity calibration for the iwl4965
75 driver.
76
77config IWLWIFI_DEBUG 61config IWLWIFI_DEBUG
78 bool "Enable full debugging output in iwl4965 driver" 62 bool "Enable full debugging output in iwl4965 driver"
79 depends on IWL4965 63 depends on IWL4965
@@ -85,13 +69,13 @@ config IWLWIFI_DEBUG
85 control which debug output is sent to the kernel log by setting the 69 control which debug output is sent to the kernel log by setting the
86 value in 70 value in
87 71
88 /sys/bus/pci/drivers/${DRIVER}/debug_level 72 /sys/class/net/wlan0/device/debug_level
89 73
90 This entry will only exist if this option is enabled. 74 This entry will only exist if this option is enabled.
91 75
92 To set a value, simply echo an 8-byte hex value to the same file: 76 To set a value, simply echo an 8-byte hex value to the same file:
93 77
94 % echo 0x43fff > /sys/bus/pci/drivers/${DRIVER}/debug_level 78 % echo 0x43fff > /sys/class/net/wlan0/device/debug_level
95 79
96 You can find the list of debug mask values in: 80 You can find the list of debug mask values in:
97 drivers/net/wireless/iwlwifi/iwl-4965-debug.h 81 drivers/net/wireless/iwlwifi/iwl-4965-debug.h
@@ -100,6 +84,13 @@ config IWLWIFI_DEBUG
100 as the debug information can assist others in helping you resolve 84 as the debug information can assist others in helping you resolve
101 any problems you may encounter. 85 any problems you may encounter.
102 86
87config IWL5000
88 bool "Intel Wireless WiFi 5000AGN"
89 depends on IWL4965
90 ---help---
91 This option enables support for Intel Wireless WiFi Link 5000AGN Family
92 Dependency on 4965 is temporary
93
103config IWLWIFI_DEBUGFS 94config IWLWIFI_DEBUGFS
104 bool "Iwlwifi debugfs support" 95 bool "Iwlwifi debugfs support"
105 depends on IWLCORE && IWLWIFI_DEBUG && MAC80211_DEBUGFS 96 depends on IWLCORE && IWLWIFI_DEBUG && MAC80211_DEBUGFS
@@ -113,6 +104,7 @@ config IWL3945
113 select IWLWIFI 104 select IWLWIFI
114 select MAC80211_LEDS if IWL3945_LEDS 105 select MAC80211_LEDS if IWL3945_LEDS
115 select LEDS_CLASS if IWL3945_LEDS 106 select LEDS_CLASS if IWL3945_LEDS
107 select RFKILL if IWL3945_RFKILL
116 ---help--- 108 ---help---
117 Select to build the driver supporting the: 109 Select to build the driver supporting the:
118 110
@@ -135,6 +127,10 @@ config IWL3945
135 say M here and read <file:Documentation/kbuild/modules.txt>. The 127 say M here and read <file:Documentation/kbuild/modules.txt>. The
136 module will be called iwl3945.ko. 128 module will be called iwl3945.ko.
137 129
130config IWL3945_RFKILL
131 bool "Enable RF kill support in iwl3945 drivers"
132 depends on IWL3945
133
138config IWL3945_SPECTRUM_MEASUREMENT 134config IWL3945_SPECTRUM_MEASUREMENT
139 bool "Enable Spectrum Measurement in iwl3945 drivers" 135 bool "Enable Spectrum Measurement in iwl3945 drivers"
140 depends on IWL3945 136 depends on IWL3945
diff --git a/drivers/net/wireless/iwlwifi/Makefile b/drivers/net/wireless/iwlwifi/Makefile
index ec6187b75c3b..1f52b92f08b5 100644
--- a/drivers/net/wireless/iwlwifi/Makefile
+++ b/drivers/net/wireless/iwlwifi/Makefile
@@ -1,5 +1,7 @@
1obj-$(CONFIG_IWLCORE) += iwlcore.o 1obj-$(CONFIG_IWLCORE) += iwlcore.o
2iwlcore-objs := iwl-core.o iwl-eeprom.o iwl-hcmd.o 2iwlcore-objs := iwl-core.o iwl-eeprom.o iwl-hcmd.o iwl-power.o
3iwlcore-objs += iwl-rx.o iwl-tx.o iwl-sta.o iwl-calib.o
4iwlcore-objs += iwl-scan.o
3iwlcore-$(CONFIG_IWLWIFI_DEBUGFS) += iwl-debugfs.o 5iwlcore-$(CONFIG_IWLWIFI_DEBUGFS) += iwl-debugfs.o
4iwlcore-$(CONFIG_IWLWIFI_LEDS) += iwl-led.o 6iwlcore-$(CONFIG_IWLWIFI_LEDS) += iwl-led.o
5iwlcore-$(CONFIG_IWLWIFI_RFKILL) += iwl-rfkill.o 7iwlcore-$(CONFIG_IWLWIFI_RFKILL) += iwl-rfkill.o
@@ -9,5 +11,10 @@ iwl3945-objs := iwl3945-base.o iwl-3945.o iwl-3945-rs.o
9iwl3945-$(CONFIG_IWL3945_LEDS) += iwl-3945-led.o 11iwl3945-$(CONFIG_IWL3945_LEDS) += iwl-3945-led.o
10 12
11obj-$(CONFIG_IWL4965) += iwl4965.o 13obj-$(CONFIG_IWL4965) += iwl4965.o
12iwl4965-objs := iwl4965-base.o iwl-4965.o iwl-4965-rs.o iwl-sta.o 14iwl4965-objs := iwl4965-base.o iwl-4965.o iwl-4965-rs.o
15
16ifeq ($(CONFIG_IWL5000),y)
17 iwl4965-objs += iwl-5000.o
18endif
19
13 20
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
index ad612a8719f4..644bd9e08052 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
@@ -126,7 +126,7 @@ enum {
126 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ 126 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
127 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ 127 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
128 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ 128 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
129 EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel (not used) */ 129 /* Bit 6 Reserved (was Narrow Channel) */
130 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ 130 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
131}; 131};
132 132
@@ -289,17 +289,6 @@ struct iwl3945_eeprom {
289#define PCI_REG_WUM8 0x0E8 289#define PCI_REG_WUM8 0x0E8
290#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) 290#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
291 291
292/* SCD (3945 Tx Frame Scheduler) */
293#define SCD_BASE (CSR_BASE + 0x2E00)
294
295#define SCD_MODE_REG (SCD_BASE + 0x000)
296#define SCD_ARASTAT_REG (SCD_BASE + 0x004)
297#define SCD_TXFACT_REG (SCD_BASE + 0x010)
298#define SCD_TXF4MF_REG (SCD_BASE + 0x014)
299#define SCD_TXF5MF_REG (SCD_BASE + 0x020)
300#define SCD_SBYP_MODE_1_REG (SCD_BASE + 0x02C)
301#define SCD_SBYP_MODE_2_REG (SCD_BASE + 0x030)
302
303/*=== FH (data Flow Handler) ===*/ 292/*=== FH (data Flow Handler) ===*/
304#define FH_BASE (0x800) 293#define FH_BASE (0x800)
305 294
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-led.c b/drivers/net/wireless/iwlwifi/iwl-3945-led.c
index 8b1528e52d43..6be1fe13fa57 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945-led.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-led.c
@@ -42,14 +42,11 @@
42#include "iwl-3945.h" 42#include "iwl-3945.h"
43#include "iwl-helpers.h" 43#include "iwl-helpers.h"
44 44
45#define IWL_1MB_RATE (128 * 1024)
46#define IWL_LED_THRESHOLD (16)
47#define IWL_MAX_BLINK_TBL (10)
48 45
49static const struct { 46static const struct {
50 u16 brightness; 47 u16 brightness;
51 u8 on_time; 48 u8 on_time;
52 u8 of_time; 49 u8 off_time;
53} blink_tbl[] = 50} blink_tbl[] =
54{ 51{
55 {300, 25, 25}, 52 {300, 25, 25},
@@ -61,9 +58,16 @@ static const struct {
61 {15, 95, 95 }, 58 {15, 95, 95 },
62 {10, 110, 110}, 59 {10, 110, 110},
63 {5, 130, 130}, 60 {5, 130, 130},
64 {0, 167, 167} 61 {0, 167, 167},
62 /*SOLID_ON*/
63 {-1, IWL_LED_SOLID, 0}
65}; 64};
66 65
66#define IWL_1MB_RATE (128 * 1024)
67#define IWL_LED_THRESHOLD (16)
68#define IWL_MAX_BLINK_TBL (ARRAY_SIZE(blink_tbl) - 1) /*Exclude Solid on*/
69#define IWL_SOLID_BLINK_IDX (ARRAY_SIZE(blink_tbl) - 1)
70
67static int iwl3945_led_cmd_callback(struct iwl3945_priv *priv, 71static int iwl3945_led_cmd_callback(struct iwl3945_priv *priv,
68 struct iwl3945_cmd *cmd, 72 struct iwl3945_cmd *cmd,
69 struct sk_buff *skb) 73 struct sk_buff *skb)
@@ -71,6 +75,10 @@ static int iwl3945_led_cmd_callback(struct iwl3945_priv *priv,
71 return 1; 75 return 1;
72} 76}
73 77
78static inline int iwl3945_brightness_to_idx(enum led_brightness brightness)
79{
80 return fls(0x000000FF & (u32)brightness);
81}
74 82
75/* Send led command */ 83/* Send led command */
76static int iwl_send_led_cmd(struct iwl3945_priv *priv, 84static int iwl_send_led_cmd(struct iwl3945_priv *priv,
@@ -81,49 +89,45 @@ static int iwl_send_led_cmd(struct iwl3945_priv *priv,
81 .len = sizeof(struct iwl3945_led_cmd), 89 .len = sizeof(struct iwl3945_led_cmd),
82 .data = led_cmd, 90 .data = led_cmd,
83 .meta.flags = CMD_ASYNC, 91 .meta.flags = CMD_ASYNC,
84 .meta.u.callback = iwl3945_led_cmd_callback 92 .meta.u.callback = iwl3945_led_cmd_callback,
85 }; 93 };
86 94
87 return iwl3945_send_cmd(priv, &cmd); 95 return iwl3945_send_cmd(priv, &cmd);
88} 96}
89 97
90 98
99
91/* Set led on command */ 100/* Set led on command */
92static int iwl3945_led_on(struct iwl3945_priv *priv, int led_id) 101static int iwl3945_led_pattern(struct iwl3945_priv *priv, int led_id,
102 unsigned int idx)
93{ 103{
94 struct iwl3945_led_cmd led_cmd = { 104 struct iwl3945_led_cmd led_cmd = {
95 .id = led_id, 105 .id = led_id,
96 .on = IWL_LED_SOLID,
97 .off = 0,
98 .interval = IWL_DEF_LED_INTRVL 106 .interval = IWL_DEF_LED_INTRVL
99 }; 107 };
108
109 BUG_ON(idx > IWL_MAX_BLINK_TBL);
110
111 led_cmd.on = blink_tbl[idx].on_time;
112 led_cmd.off = blink_tbl[idx].off_time;
113
100 return iwl_send_led_cmd(priv, &led_cmd); 114 return iwl_send_led_cmd(priv, &led_cmd);
101} 115}
102 116
117
118#if 1
103/* Set led on command */ 119/* Set led on command */
104static int iwl3945_led_pattern(struct iwl3945_priv *priv, int led_id, 120static int iwl3945_led_on(struct iwl3945_priv *priv, int led_id)
105 enum led_brightness brightness)
106{ 121{
107 struct iwl3945_led_cmd led_cmd = { 122 struct iwl3945_led_cmd led_cmd = {
108 .id = led_id, 123 .id = led_id,
109 .on = brightness, 124 .on = IWL_LED_SOLID,
110 .off = brightness, 125 .off = 0,
111 .interval = IWL_DEF_LED_INTRVL 126 .interval = IWL_DEF_LED_INTRVL
112 }; 127 };
113 if (brightness == LED_FULL) {
114 led_cmd.on = IWL_LED_SOLID;
115 led_cmd.off = 0;
116 }
117 return iwl_send_led_cmd(priv, &led_cmd); 128 return iwl_send_led_cmd(priv, &led_cmd);
118} 129}
119 130
120/* Set led register off */
121static int iwl3945_led_on_reg(struct iwl3945_priv *priv, int led_id)
122{
123 IWL_DEBUG_LED("led on %d\n", led_id);
124 return iwl3945_led_on(priv, led_id);
125}
126
127/* Set led off command */ 131/* Set led off command */
128static int iwl3945_led_off(struct iwl3945_priv *priv, int led_id) 132static int iwl3945_led_off(struct iwl3945_priv *priv, int led_id)
129{ 133{
@@ -136,27 +140,7 @@ static int iwl3945_led_off(struct iwl3945_priv *priv, int led_id)
136 IWL_DEBUG_LED("led off %d\n", led_id); 140 IWL_DEBUG_LED("led off %d\n", led_id);
137 return iwl_send_led_cmd(priv, &led_cmd); 141 return iwl_send_led_cmd(priv, &led_cmd);
138} 142}
139 143#endif
140/* Set led register off */
141static int iwl3945_led_off_reg(struct iwl3945_priv *priv, int led_id)
142{
143 iwl3945_led_off(priv, led_id);
144 return 0;
145}
146
147/* Set led blink command */
148static int iwl3945_led_not_solid(struct iwl3945_priv *priv, int led_id,
149 u8 brightness)
150{
151 struct iwl3945_led_cmd led_cmd = {
152 .id = led_id,
153 .on = brightness,
154 .off = brightness,
155 .interval = IWL_DEF_LED_INTRVL
156 };
157
158 return iwl_send_led_cmd(priv, &led_cmd);
159}
160 144
161 145
162/* 146/*
@@ -206,8 +190,10 @@ static void iwl3945_led_brightness_set(struct led_classdev *led_cdev,
206 led->led_off(priv, IWL_LED_LINK); 190 led->led_off(priv, IWL_LED_LINK);
207 break; 191 break;
208 default: 192 default:
209 if (led->led_pattern) 193 if (led->led_pattern) {
210 led->led_pattern(priv, IWL_LED_LINK, brightness); 194 int idx = iwl3945_brightness_to_idx(brightness);
195 led->led_pattern(priv, IWL_LED_LINK, idx);
196 }
211 break; 197 break;
212 } 198 }
213} 199}
@@ -252,24 +238,20 @@ static int iwl3945_led_register_led(struct iwl3945_priv *priv,
252static inline u8 get_blink_rate(struct iwl3945_priv *priv) 238static inline u8 get_blink_rate(struct iwl3945_priv *priv)
253{ 239{
254 int index; 240 int index;
255 u8 blink_rate; 241 u64 current_tpt = priv->rxtxpackets;
256 242 s64 tpt = current_tpt - priv->led_tpt;
257 if (priv->rxtxpackets < IWL_LED_THRESHOLD)
258 index = 10;
259 else {
260 for (index = 0; index < IWL_MAX_BLINK_TBL; index++) {
261 if (priv->rxtxpackets > (blink_tbl[index].brightness *
262 IWL_1MB_RATE))
263 break;
264 }
265 }
266 /* if 0 frame is transfered */
267 if ((index == IWL_MAX_BLINK_TBL) || !priv->allow_blinking)
268 blink_rate = IWL_LED_SOLID;
269 else
270 blink_rate = blink_tbl[index].on_time;
271 243
272 return blink_rate; 244 if (tpt < 0)
245 tpt = -tpt;
246 priv->led_tpt = current_tpt;
247
248 if (!priv->allow_blinking)
249 index = IWL_MAX_BLINK_TBL;
250 else
251 for (index = 0; index < IWL_MAX_BLINK_TBL; index++)
252 if (tpt > (blink_tbl[index].brightness * IWL_1MB_RATE))
253 break;
254 return index;
273} 255}
274 256
275static inline int is_rf_kill(struct iwl3945_priv *priv) 257static inline int is_rf_kill(struct iwl3945_priv *priv)
@@ -285,7 +267,7 @@ static inline int is_rf_kill(struct iwl3945_priv *priv)
285 */ 267 */
286void iwl3945_led_background(struct iwl3945_priv *priv) 268void iwl3945_led_background(struct iwl3945_priv *priv)
287{ 269{
288 u8 blink_rate; 270 u8 blink_idx;
289 271
290 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { 272 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
291 priv->last_blink_time = 0; 273 priv->last_blink_time = 0;
@@ -298,9 +280,10 @@ void iwl3945_led_background(struct iwl3945_priv *priv)
298 280
299 if (!priv->allow_blinking) { 281 if (!priv->allow_blinking) {
300 priv->last_blink_time = 0; 282 priv->last_blink_time = 0;
301 if (priv->last_blink_rate != IWL_LED_SOLID) { 283 if (priv->last_blink_rate != IWL_SOLID_BLINK_IDX) {
302 priv->last_blink_rate = IWL_LED_SOLID; 284 priv->last_blink_rate = IWL_SOLID_BLINK_IDX;
303 iwl3945_led_on(priv, IWL_LED_LINK); 285 iwl3945_led_pattern(priv, IWL_LED_LINK,
286 IWL_SOLID_BLINK_IDX);
304 } 287 }
305 return; 288 return;
306 } 289 }
@@ -309,21 +292,14 @@ void iwl3945_led_background(struct iwl3945_priv *priv)
309 msecs_to_jiffies(1000))) 292 msecs_to_jiffies(1000)))
310 return; 293 return;
311 294
312 blink_rate = get_blink_rate(priv); 295 blink_idx = get_blink_rate(priv);
313 296
314 /* call only if blink rate change */ 297 /* call only if blink rate change */
315 if (blink_rate != priv->last_blink_rate) { 298 if (blink_idx != priv->last_blink_rate)
316 if (blink_rate != IWL_LED_SOLID) { 299 iwl3945_led_pattern(priv, IWL_LED_LINK, blink_idx);
317 priv->last_blink_time = jiffies +
318 msecs_to_jiffies(1000);
319 iwl3945_led_not_solid(priv, IWL_LED_LINK, blink_rate);
320 } else {
321 priv->last_blink_time = 0;
322 iwl3945_led_on(priv, IWL_LED_LINK);
323 }
324 }
325 300
326 priv->last_blink_rate = blink_rate; 301 priv->last_blink_time = jiffies;
302 priv->last_blink_rate = blink_idx;
327 priv->rxtxpackets = 0; 303 priv->rxtxpackets = 0;
328} 304}
329 305
@@ -337,6 +313,7 @@ int iwl3945_led_register(struct iwl3945_priv *priv)
337 313
338 priv->last_blink_rate = 0; 314 priv->last_blink_rate = 0;
339 priv->rxtxpackets = 0; 315 priv->rxtxpackets = 0;
316 priv->led_tpt = 0;
340 priv->last_blink_time = 0; 317 priv->last_blink_time = 0;
341 priv->allow_blinking = 0; 318 priv->allow_blinking = 0;
342 319
@@ -344,8 +321,8 @@ int iwl3945_led_register(struct iwl3945_priv *priv)
344 snprintf(name, sizeof(name), "iwl-%s:radio", 321 snprintf(name, sizeof(name), "iwl-%s:radio",
345 wiphy_name(priv->hw->wiphy)); 322 wiphy_name(priv->hw->wiphy));
346 323
347 priv->led[IWL_LED_TRG_RADIO].led_on = iwl3945_led_on_reg; 324 priv->led[IWL_LED_TRG_RADIO].led_on = iwl3945_led_on;
348 priv->led[IWL_LED_TRG_RADIO].led_off = iwl3945_led_off_reg; 325 priv->led[IWL_LED_TRG_RADIO].led_off = iwl3945_led_off;
349 priv->led[IWL_LED_TRG_RADIO].led_pattern = NULL; 326 priv->led[IWL_LED_TRG_RADIO].led_pattern = NULL;
350 327
351 ret = iwl3945_led_register_led(priv, 328 ret = iwl3945_led_register_led(priv,
@@ -364,8 +341,8 @@ int iwl3945_led_register(struct iwl3945_priv *priv)
364 IWL_LED_TRG_ASSOC, 0, 341 IWL_LED_TRG_ASSOC, 0,
365 name, trigger); 342 name, trigger);
366 /* for assoc always turn led on */ 343 /* for assoc always turn led on */
367 priv->led[IWL_LED_TRG_ASSOC].led_on = iwl3945_led_on_reg; 344 priv->led[IWL_LED_TRG_ASSOC].led_on = iwl3945_led_on;
368 priv->led[IWL_LED_TRG_ASSOC].led_off = iwl3945_led_on_reg; 345 priv->led[IWL_LED_TRG_ASSOC].led_off = iwl3945_led_on;
369 priv->led[IWL_LED_TRG_ASSOC].led_pattern = NULL; 346 priv->led[IWL_LED_TRG_ASSOC].led_pattern = NULL;
370 347
371 if (ret) 348 if (ret)
@@ -391,6 +368,7 @@ int iwl3945_led_register(struct iwl3945_priv *priv)
391 trigger = ieee80211_get_tx_led_name(priv->hw); 368 trigger = ieee80211_get_tx_led_name(priv->hw);
392 snprintf(name, sizeof(name), "iwl-%s:TX", 369 snprintf(name, sizeof(name), "iwl-%s:TX",
393 wiphy_name(priv->hw->wiphy)); 370 wiphy_name(priv->hw->wiphy));
371
394 ret = iwl3945_led_register_led(priv, 372 ret = iwl3945_led_register_led(priv,
395 &priv->led[IWL_LED_TRG_TX], 373 &priv->led[IWL_LED_TRG_TX],
396 IWL_LED_TRG_TX, 0, 374 IWL_LED_TRG_TX, 0,
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-led.h b/drivers/net/wireless/iwlwifi/iwl-3945-led.h
index b1d2f6b8b259..47b7e0bac802 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945-led.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-led.h
@@ -54,7 +54,7 @@ struct iwl3945_led {
54 int (*led_on) (struct iwl3945_priv *priv, int led_id); 54 int (*led_on) (struct iwl3945_priv *priv, int led_id);
55 int (*led_off) (struct iwl3945_priv *priv, int led_id); 55 int (*led_off) (struct iwl3945_priv *priv, int led_id);
56 int (*led_pattern) (struct iwl3945_priv *priv, int led_id, 56 int (*led_pattern) (struct iwl3945_priv *priv, int led_id,
57 enum led_brightness brightness); 57 unsigned int idx);
58 58
59 enum led_type type; 59 enum led_type type;
60 unsigned int registered; 60 unsigned int registered;
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-rs.c b/drivers/net/wireless/iwlwifi/iwl-3945-rs.c
index 85c22641542d..10c64bdb314c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945-rs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-rs.c
@@ -29,7 +29,6 @@
29#include <linux/skbuff.h> 29#include <linux/skbuff.h>
30#include <linux/wireless.h> 30#include <linux/wireless.h>
31#include <net/mac80211.h> 31#include <net/mac80211.h>
32#include <net/ieee80211.h>
33 32
34#include <linux/netdevice.h> 33#include <linux/netdevice.h>
35#include <linux/etherdevice.h> 34#include <linux/etherdevice.h>
@@ -446,8 +445,7 @@ static int rs_adjust_next_rate(struct iwl3945_priv *priv, int rate)
446 */ 445 */
447static void rs_tx_status(void *priv_rate, 446static void rs_tx_status(void *priv_rate,
448 struct net_device *dev, 447 struct net_device *dev,
449 struct sk_buff *skb, 448 struct sk_buff *skb)
450 struct ieee80211_tx_status *tx_resp)
451{ 449{
452 u8 retries, current_count; 450 u8 retries, current_count;
453 int scale_rate_index, first_index, last_index; 451 int scale_rate_index, first_index, last_index;
@@ -458,14 +456,15 @@ static void rs_tx_status(void *priv_rate,
458 struct ieee80211_local *local = wdev_priv(dev->ieee80211_ptr); 456 struct ieee80211_local *local = wdev_priv(dev->ieee80211_ptr);
459 struct iwl3945_rs_sta *rs_sta; 457 struct iwl3945_rs_sta *rs_sta;
460 struct ieee80211_supported_band *sband; 458 struct ieee80211_supported_band *sband;
459 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
461 460
462 IWL_DEBUG_RATE("enter\n"); 461 IWL_DEBUG_RATE("enter\n");
463 462
464 sband = local->hw.wiphy->bands[local->hw.conf.channel->band]; 463 sband = local->hw.wiphy->bands[local->hw.conf.channel->band];
465 464
466 465
467 retries = tx_resp->retry_count; 466 retries = info->status.retry_count;
468 first_index = tx_resp->control.tx_rate->hw_value; 467 first_index = sband->bitrates[info->tx_rate_idx].hw_value;
469 if ((first_index < 0) || (first_index >= IWL_RATE_COUNT)) { 468 if ((first_index < 0) || (first_index >= IWL_RATE_COUNT)) {
470 IWL_DEBUG_RATE("leave: Rate out of bounds: %d\n", first_index); 469 IWL_DEBUG_RATE("leave: Rate out of bounds: %d\n", first_index);
471 return; 470 return;
@@ -526,11 +525,11 @@ static void rs_tx_status(void *priv_rate,
526 /* Update the last index window with success/failure based on ACK */ 525 /* Update the last index window with success/failure based on ACK */
527 IWL_DEBUG_RATE("Update rate %d with %s.\n", 526 IWL_DEBUG_RATE("Update rate %d with %s.\n",
528 last_index, 527 last_index,
529 (tx_resp->flags & IEEE80211_TX_STATUS_ACK) ? 528 (info->flags & IEEE80211_TX_STAT_ACK) ?
530 "success" : "failure"); 529 "success" : "failure");
531 iwl3945_collect_tx_data(rs_sta, 530 iwl3945_collect_tx_data(rs_sta,
532 &rs_sta->win[last_index], 531 &rs_sta->win[last_index],
533 tx_resp->flags & IEEE80211_TX_STATUS_ACK, 1); 532 info->flags & IEEE80211_TX_STAT_ACK, 1);
534 533
535 /* We updated the rate scale window -- if its been more than 534 /* We updated the rate scale window -- if its been more than
536 * flush_time since the last run, schedule the flush 535 * flush_time since the last run, schedule the flush
@@ -670,7 +669,7 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
670 is_multicast_ether_addr(hdr->addr1) || 669 is_multicast_ether_addr(hdr->addr1) ||
671 !sta || !sta->rate_ctrl_priv) { 670 !sta || !sta->rate_ctrl_priv) {
672 IWL_DEBUG_RATE("leave: No STA priv data to update!\n"); 671 IWL_DEBUG_RATE("leave: No STA priv data to update!\n");
673 sel->rate = rate_lowest(local, sband, sta); 672 sel->rate_idx = rate_lowest_index(local, sband, sta);
674 rcu_read_unlock(); 673 rcu_read_unlock();
675 return; 674 return;
676 } 675 }
@@ -814,7 +813,7 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
814 813
815 IWL_DEBUG_RATE("leave: %d\n", index); 814 IWL_DEBUG_RATE("leave: %d\n", index);
816 815
817 sel->rate = &sband->bitrates[sta->txrate_idx]; 816 sel->rate_idx = sta->txrate_idx;
818} 817}
819 818
820static struct rate_control_ops rs_ops = { 819static struct rate_control_ops rs_ops = {
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index 55ac850744b3..c2a76785b665 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -283,8 +283,7 @@ static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
283 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { 283 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
284 284
285 tx_info = &txq->txb[txq->q.read_ptr]; 285 tx_info = &txq->txb[txq->q.read_ptr];
286 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0], 286 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
287 &tx_info->status);
288 tx_info->skb[0] = NULL; 287 tx_info->skb[0] = NULL;
289 iwl3945_hw_txq_free_tfd(priv, txq); 288 iwl3945_hw_txq_free_tfd(priv, txq);
290 } 289 }
@@ -306,7 +305,7 @@ static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
306 int txq_id = SEQ_TO_QUEUE(sequence); 305 int txq_id = SEQ_TO_QUEUE(sequence);
307 int index = SEQ_TO_INDEX(sequence); 306 int index = SEQ_TO_INDEX(sequence);
308 struct iwl3945_tx_queue *txq = &priv->txq[txq_id]; 307 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
309 struct ieee80211_tx_status *tx_status; 308 struct ieee80211_tx_info *info;
310 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 309 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
311 u32 status = le32_to_cpu(tx_resp->status); 310 u32 status = le32_to_cpu(tx_resp->status);
312 int rate_idx; 311 int rate_idx;
@@ -319,19 +318,22 @@ static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
319 return; 318 return;
320 } 319 }
321 320
322 tx_status = &(txq->txb[txq->q.read_ptr].status); 321 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
322 memset(&info->status, 0, sizeof(info->status));
323 323
324 tx_status->retry_count = tx_resp->failure_frame; 324 info->status.retry_count = tx_resp->failure_frame;
325 /* tx_status->rts_retry_count = tx_resp->failure_rts; */ 325 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
326 tx_status->flags = ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ? 326 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
327 IEEE80211_TX_STATUS_ACK : 0; 327 IEEE80211_TX_STAT_ACK : 0;
328 328
329 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", 329 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
330 txq_id, iwl3945_get_tx_fail_reason(status), status, 330 txq_id, iwl3945_get_tx_fail_reason(status), status,
331 tx_resp->rate, tx_resp->failure_frame); 331 tx_resp->rate, tx_resp->failure_frame);
332 332
333 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate); 333 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
334 tx_status->control.tx_rate = &priv->ieee_rates[rate_idx]; 334 if (info->band == IEEE80211_BAND_5GHZ)
335 rate_idx -= IWL_FIRST_OFDM_RATE;
336 info->tx_rate_idx = rate_idx;
335 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index); 337 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
336 iwl3945_tx_queue_reclaim(priv, txq_id, index); 338 iwl3945_tx_queue_reclaim(priv, txq_id, index);
337 339
@@ -386,7 +388,7 @@ static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
386 u32 print_dump = 0; /* set to 1 to dump all frames' contents */ 388 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
387 u32 hundred = 0; 389 u32 hundred = 0;
388 u32 dataframe = 0; 390 u32 dataframe = 0;
389 u16 fc; 391 __le16 fc;
390 u16 seq_ctl; 392 u16 seq_ctl;
391 u16 channel; 393 u16 channel;
392 u16 phy_flags; 394 u16 phy_flags;
@@ -405,7 +407,7 @@ static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
405 u8 *data = IWL_RX_DATA(pkt); 407 u8 *data = IWL_RX_DATA(pkt);
406 408
407 /* MAC header */ 409 /* MAC header */
408 fc = le16_to_cpu(header->frame_control); 410 fc = header->frame_control;
409 seq_ctl = le16_to_cpu(header->seq_ctrl); 411 seq_ctl = le16_to_cpu(header->seq_ctrl);
410 412
411 /* metadata */ 413 /* metadata */
@@ -429,8 +431,8 @@ static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
429 431
430 /* if data frame is to us and all is good, 432 /* if data frame is to us and all is good,
431 * (optionally) print summary for only 1 out of every 100 */ 433 * (optionally) print summary for only 1 out of every 100 */
432 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) == 434 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
433 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) { 435 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
434 dataframe = 1; 436 dataframe = 1;
435 if (!group100) 437 if (!group100)
436 print_summary = 1; /* print each frame */ 438 print_summary = 1; /* print each frame */
@@ -453,13 +455,13 @@ static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
453 455
454 if (hundred) 456 if (hundred)
455 title = "100Frames"; 457 title = "100Frames";
456 else if (fc & IEEE80211_FCTL_RETRY) 458 else if (ieee80211_has_retry(fc))
457 title = "Retry"; 459 title = "Retry";
458 else if (ieee80211_is_assoc_response(fc)) 460 else if (ieee80211_is_assoc_resp(fc))
459 title = "AscRsp"; 461 title = "AscRsp";
460 else if (ieee80211_is_reassoc_response(fc)) 462 else if (ieee80211_is_reassoc_resp(fc))
461 title = "RasRsp"; 463 title = "RasRsp";
462 else if (ieee80211_is_probe_response(fc)) { 464 else if (ieee80211_is_probe_resp(fc)) {
463 title = "PrbRsp"; 465 title = "PrbRsp";
464 print_dump = 1; /* dump frame contents */ 466 print_dump = 1; /* dump frame contents */
465 } else if (ieee80211_is_beacon(fc)) { 467 } else if (ieee80211_is_beacon(fc)) {
@@ -488,14 +490,14 @@ static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
488 if (dataframe) 490 if (dataframe)
489 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, " 491 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
490 "len=%u, rssi=%d, chnl=%d, rate=%d, \n", 492 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
491 title, fc, header->addr1[5], 493 title, le16_to_cpu(fc), header->addr1[5],
492 length, rssi, channel, rate); 494 length, rssi, channel, rate);
493 else { 495 else {
494 /* src/dst addresses assume managed mode */ 496 /* src/dst addresses assume managed mode */
495 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, " 497 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
496 "src=0x%02x, rssi=%u, tim=%lu usec, " 498 "src=0x%02x, rssi=%u, tim=%lu usec, "
497 "phy=0x%02x, chnl=%d\n", 499 "phy=0x%02x, chnl=%d\n",
498 title, fc, header->addr1[5], 500 title, le16_to_cpu(fc), header->addr1[5],
499 header->addr3[5], rssi, 501 header->addr3[5], rssi,
500 tsf_low - priv->scan_start_tsf, 502 tsf_low - priv->scan_start_tsf,
501 phy_flags, channel); 503 phy_flags, channel);
@@ -512,6 +514,23 @@ static inline void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
512} 514}
513#endif 515#endif
514 516
517/* This is necessary only for a number of statistics, see the caller. */
518static int iwl3945_is_network_packet(struct iwl3945_priv *priv,
519 struct ieee80211_hdr *header)
520{
521 /* Filter incoming packets to determine if they are targeted toward
522 * this network, discarding packets coming from ourselves */
523 switch (priv->iw_mode) {
524 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
525 /* packets to our IBSS update information */
526 return !compare_ether_addr(header->addr3, priv->bssid);
527 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
528 /* packets to our IBSS update information */
529 return !compare_ether_addr(header->addr2, priv->bssid);
530 default:
531 return 1;
532 }
533}
515 534
516static void iwl3945_add_radiotap(struct iwl3945_priv *priv, 535static void iwl3945_add_radiotap(struct iwl3945_priv *priv,
517 struct sk_buff *skb, 536 struct sk_buff *skb,
@@ -520,7 +539,7 @@ static void iwl3945_add_radiotap(struct iwl3945_priv *priv,
520{ 539{
521 /* First cache any information we need before we overwrite 540 /* First cache any information we need before we overwrite
522 * the information provided in the skb from the hardware */ 541 * the information provided in the skb from the hardware */
523 s8 signal = stats->ssi; 542 s8 signal = stats->signal;
524 s8 noise = 0; 543 s8 noise = 0;
525 int rate = stats->rate_idx; 544 int rate = stats->rate_idx;
526 u64 tsf = stats->mactime; 545 u64 tsf = stats->mactime;
@@ -606,12 +625,12 @@ static void iwl3945_add_radiotap(struct iwl3945_priv *priv,
606 stats->flag |= RX_FLAG_RADIOTAP; 625 stats->flag |= RX_FLAG_RADIOTAP;
607} 626}
608 627
609static void iwl3945_handle_data_packet(struct iwl3945_priv *priv, int is_data, 628static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
610 struct iwl3945_rx_mem_buffer *rxb, 629 struct iwl3945_rx_mem_buffer *rxb,
611 struct ieee80211_rx_status *stats) 630 struct ieee80211_rx_status *stats)
612{ 631{
613 struct ieee80211_hdr *hdr;
614 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data; 632 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
633 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
615 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); 634 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
616 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt); 635 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
617 short len = le16_to_cpu(rx_hdr->len); 636 short len = le16_to_cpu(rx_hdr->len);
@@ -633,8 +652,6 @@ static void iwl3945_handle_data_packet(struct iwl3945_priv *priv, int is_data,
633 /* Set the size of the skb to the size of the frame */ 652 /* Set the size of the skb to the size of the frame */
634 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len)); 653 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
635 654
636 hdr = (void *)rxb->skb->data;
637
638 if (iwl3945_param_hwcrypto) 655 if (iwl3945_param_hwcrypto)
639 iwl3945_set_decrypted_flag(priv, rxb->skb, 656 iwl3945_set_decrypted_flag(priv, rxb->skb,
640 le32_to_cpu(rx_end->status), stats); 657 le32_to_cpu(rx_end->status), stats);
@@ -643,7 +660,7 @@ static void iwl3945_handle_data_packet(struct iwl3945_priv *priv, int is_data,
643 iwl3945_add_radiotap(priv, rxb->skb, rx_hdr, stats); 660 iwl3945_add_radiotap(priv, rxb->skb, rx_hdr, stats);
644 661
645#ifdef CONFIG_IWL3945_LEDS 662#ifdef CONFIG_IWL3945_LEDS
646 if (is_data) 663 if (ieee80211_is_data(hdr->frame_control))
647 priv->rxtxpackets += len; 664 priv->rxtxpackets += len;
648#endif 665#endif
649 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats); 666 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
@@ -692,12 +709,12 @@ static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
692 } 709 }
693 710
694 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { 711 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
695 iwl3945_handle_data_packet(priv, 1, rxb, &rx_status); 712 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
696 return; 713 return;
697 } 714 }
698 715
699 /* Convert 3945's rssi indicator to dBm */ 716 /* Convert 3945's rssi indicator to dBm */
700 rx_status.ssi = rx_stats->rssi - IWL_RSSI_OFFSET; 717 rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET;
701 718
702 /* Set default noise value to -127 */ 719 /* Set default noise value to -127 */
703 if (priv->last_rx_noise == 0) 720 if (priv->last_rx_noise == 0)
@@ -716,21 +733,21 @@ static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
716 * Calculate rx_status.signal (quality indicator in %) based on SNR. */ 733 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
717 if (rx_stats_noise_diff) { 734 if (rx_stats_noise_diff) {
718 snr = rx_stats_sig_avg / rx_stats_noise_diff; 735 snr = rx_stats_sig_avg / rx_stats_noise_diff;
719 rx_status.noise = rx_status.ssi - 736 rx_status.noise = rx_status.signal -
720 iwl3945_calc_db_from_ratio(snr); 737 iwl3945_calc_db_from_ratio(snr);
721 rx_status.signal = iwl3945_calc_sig_qual(rx_status.ssi, 738 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
722 rx_status.noise); 739 rx_status.noise);
723 740
724 /* If noise info not available, calculate signal quality indicator (%) 741 /* If noise info not available, calculate signal quality indicator (%)
725 * using just the dBm signal level. */ 742 * using just the dBm signal level. */
726 } else { 743 } else {
727 rx_status.noise = priv->last_rx_noise; 744 rx_status.noise = priv->last_rx_noise;
728 rx_status.signal = iwl3945_calc_sig_qual(rx_status.ssi, 0); 745 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
729 } 746 }
730 747
731 748
732 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n", 749 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
733 rx_status.ssi, rx_status.noise, rx_status.signal, 750 rx_status.signal, rx_status.noise, rx_status.qual,
734 rx_stats_sig_avg, rx_stats_noise_diff); 751 rx_stats_sig_avg, rx_stats_noise_diff);
735 752
736 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt); 753 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
@@ -740,8 +757,8 @@ static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
740 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n", 757 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
741 network_packet ? '*' : ' ', 758 network_packet ? '*' : ' ',
742 le16_to_cpu(rx_hdr->channel), 759 le16_to_cpu(rx_hdr->channel),
743 rx_status.ssi, rx_status.ssi, 760 rx_status.signal, rx_status.signal,
744 rx_status.ssi, rx_status.rate_idx); 761 rx_status.noise, rx_status.rate_idx);
745 762
746#ifdef CONFIG_IWL3945_DEBUG 763#ifdef CONFIG_IWL3945_DEBUG
747 if (iwl3945_debug_level & (IWL_DL_RX)) 764 if (iwl3945_debug_level & (IWL_DL_RX))
@@ -752,7 +769,7 @@ static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
752 if (network_packet) { 769 if (network_packet) {
753 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp); 770 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
754 priv->last_tsf = le64_to_cpu(rx_end->timestamp); 771 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
755 priv->last_rx_rssi = rx_status.ssi; 772 priv->last_rx_rssi = rx_status.signal;
756 priv->last_rx_noise = rx_status.noise; 773 priv->last_rx_noise = rx_status.noise;
757 } 774 }
758 775
@@ -840,27 +857,12 @@ static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
840 } 857 }
841 } 858 }
842 859
843 iwl3945_handle_data_packet(priv, 0, rxb, &rx_status); 860 case IEEE80211_FTYPE_DATA:
844 break; 861 /* fall through */
845 862 default:
846 case IEEE80211_FTYPE_CTL: 863 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
847 break;
848
849 case IEEE80211_FTYPE_DATA: {
850 DECLARE_MAC_BUF(mac1);
851 DECLARE_MAC_BUF(mac2);
852 DECLARE_MAC_BUF(mac3);
853
854 if (unlikely(iwl3945_is_duplicate_packet(priv, header)))
855 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
856 print_mac(mac1, header->addr1),
857 print_mac(mac2, header->addr2),
858 print_mac(mac3, header->addr3));
859 else
860 iwl3945_handle_data_packet(priv, 1, rxb, &rx_status);
861 break; 864 break;
862 } 865 }
863 }
864} 866}
865 867
866int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr, 868int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
@@ -962,23 +964,24 @@ u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
962*/ 964*/
963void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv, 965void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
964 struct iwl3945_cmd *cmd, 966 struct iwl3945_cmd *cmd,
965 struct ieee80211_tx_control *ctrl, 967 struct ieee80211_tx_info *info,
966 struct ieee80211_hdr *hdr, int sta_id, int tx_id) 968 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
967{ 969{
968 unsigned long flags; 970 unsigned long flags;
969 u16 rate_index = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1); 971 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
972 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
970 u16 rate_mask; 973 u16 rate_mask;
971 int rate; 974 int rate;
972 u8 rts_retry_limit; 975 u8 rts_retry_limit;
973 u8 data_retry_limit; 976 u8 data_retry_limit;
974 __le32 tx_flags; 977 __le32 tx_flags;
975 u16 fc = le16_to_cpu(hdr->frame_control); 978 __le16 fc = hdr->frame_control;
976 979
977 rate = iwl3945_rates[rate_index].plcp; 980 rate = iwl3945_rates[rate_index].plcp;
978 tx_flags = cmd->cmd.tx.tx_flags; 981 tx_flags = cmd->cmd.tx.tx_flags;
979 982
980 /* We need to figure out how to get the sta->supp_rates while 983 /* We need to figure out how to get the sta->supp_rates while
981 * in this running context; perhaps encoding into ctrl->tx_rate? */ 984 * in this running context */
982 rate_mask = IWL_RATES_MASK; 985 rate_mask = IWL_RATES_MASK;
983 986
984 spin_lock_irqsave(&priv->sta_lock, flags); 987 spin_lock_irqsave(&priv->sta_lock, flags);
@@ -997,7 +1000,7 @@ void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
997 else 1000 else
998 rts_retry_limit = 7; 1001 rts_retry_limit = 7;
999 1002
1000 if (ieee80211_is_probe_response(fc)) { 1003 if (ieee80211_is_probe_resp(fc)) {
1001 data_retry_limit = 3; 1004 data_retry_limit = 3;
1002 if (data_retry_limit < rts_retry_limit) 1005 if (data_retry_limit < rts_retry_limit)
1003 rts_retry_limit = data_retry_limit; 1006 rts_retry_limit = data_retry_limit;
@@ -1007,12 +1010,12 @@ void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
1007 if (priv->data_retry_limit != -1) 1010 if (priv->data_retry_limit != -1)
1008 data_retry_limit = priv->data_retry_limit; 1011 data_retry_limit = priv->data_retry_limit;
1009 1012
1010 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) { 1013 if (ieee80211_is_mgmt(fc)) {
1011 switch (fc & IEEE80211_FCTL_STYPE) { 1014 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
1012 case IEEE80211_STYPE_AUTH: 1015 case cpu_to_le16(IEEE80211_STYPE_AUTH):
1013 case IEEE80211_STYPE_DEAUTH: 1016 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
1014 case IEEE80211_STYPE_ASSOC_REQ: 1017 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
1015 case IEEE80211_STYPE_REASSOC_REQ: 1018 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
1016 if (tx_flags & TX_CMD_FLG_RTS_MSK) { 1019 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
1017 tx_flags &= ~TX_CMD_FLG_RTS_MSK; 1020 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
1018 tx_flags |= TX_CMD_FLG_CTS_MSK; 1021 tx_flags |= TX_CMD_FLG_CTS_MSK;
@@ -1233,7 +1236,7 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
1233 iwl3945_power_init_handle(priv); 1236 iwl3945_power_init_handle(priv);
1234 1237
1235 spin_lock_irqsave(&priv->lock, flags); 1238 spin_lock_irqsave(&priv->lock, flags);
1236 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24)); 1239 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
1237 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, 1240 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1238 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 1241 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1239 1242
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.h b/drivers/net/wireless/iwlwifi/iwl-3945.h
index c7695a215a39..fa81ba1af3d3 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.h
@@ -36,6 +36,10 @@
36#include <linux/kernel.h> 36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h> 37#include <net/ieee80211_radiotap.h>
38 38
39/*used for rfkill*/
40#include <linux/rfkill.h>
41#include <linux/input.h>
42
39/* Hardware specific file defines the PCI IDs table for that hardware module */ 43/* Hardware specific file defines the PCI IDs table for that hardware module */
40extern struct pci_device_id iwl3945_hw_card_ids[]; 44extern struct pci_device_id iwl3945_hw_card_ids[];
41 45
@@ -124,7 +128,6 @@ int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i);
124 128
125/* One for each TFD */ 129/* One for each TFD */
126struct iwl3945_tx_info { 130struct iwl3945_tx_info {
127 struct ieee80211_tx_status status;
128 struct sk_buff *skb[MAX_NUM_OF_TBS]; 131 struct sk_buff *skb[MAX_NUM_OF_TBS];
129}; 132};
130 133
@@ -507,8 +510,6 @@ struct iwl3945_ucode {
507 u8 data[0]; /* data in same order as "size" elements */ 510 u8 data[0]; /* data in same order as "size" elements */
508}; 511};
509 512
510#define IWL_IBSS_MAC_HASH_SIZE 32
511
512struct iwl3945_ibss_seq { 513struct iwl3945_ibss_seq {
513 u8 mac[ETH_ALEN]; 514 u8 mac[ETH_ALEN];
514 u16 seq_num; 515 u16 seq_num;
@@ -566,17 +567,8 @@ extern int iwl3945_send_add_station(struct iwl3945_priv *priv,
566 struct iwl3945_addsta_cmd *sta, u8 flags); 567 struct iwl3945_addsta_cmd *sta, u8 flags);
567extern u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *bssid, 568extern u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *bssid,
568 int is_ap, u8 flags); 569 int is_ap, u8 flags);
569extern int iwl3945_is_network_packet(struct iwl3945_priv *priv,
570 struct ieee80211_hdr *header);
571extern int iwl3945_power_init_handle(struct iwl3945_priv *priv); 570extern int iwl3945_power_init_handle(struct iwl3945_priv *priv);
572extern int iwl3945_eeprom_init(struct iwl3945_priv *priv); 571extern int iwl3945_eeprom_init(struct iwl3945_priv *priv);
573extern void iwl3945_handle_data_packet_monitor(struct iwl3945_priv *priv,
574 struct iwl3945_rx_mem_buffer *rxb,
575 void *data, short len,
576 struct ieee80211_rx_status *stats,
577 u16 phy_flags);
578extern int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv,
579 struct ieee80211_hdr *header);
580extern int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv); 572extern int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv);
581extern void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, 573extern void iwl3945_rx_queue_reset(struct iwl3945_priv *priv,
582 struct iwl3945_rx_queue *rxq); 574 struct iwl3945_rx_queue *rxq);
@@ -645,7 +637,7 @@ extern unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
645extern int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv); 637extern int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv);
646extern void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv, 638extern void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
647 struct iwl3945_cmd *cmd, 639 struct iwl3945_cmd *cmd,
648 struct ieee80211_tx_control *ctrl, 640 struct ieee80211_tx_info *info,
649 struct ieee80211_hdr *hdr, 641 struct ieee80211_hdr *hdr,
650 int sta_id, int tx_id); 642 int sta_id, int tx_id);
651extern int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv); 643extern int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv);
@@ -687,6 +679,18 @@ enum {
687 679
688#endif 680#endif
689 681
682#ifdef CONFIG_IWL3945_RFKILL
683struct iwl3945_priv;
684
685void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv);
686void iwl3945_rfkill_unregister(struct iwl3945_priv *priv);
687int iwl3945_rfkill_init(struct iwl3945_priv *priv);
688#else
689static inline void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv) {}
690static inline void iwl3945_rfkill_unregister(struct iwl3945_priv *priv) {}
691static inline int iwl3945_rfkill_init(struct iwl3945_priv *priv) { return 0; }
692#endif
693
690#define IWL_MAX_NUM_QUEUES IWL39_MAX_NUM_QUEUES 694#define IWL_MAX_NUM_QUEUES IWL39_MAX_NUM_QUEUES
691 695
692struct iwl3945_priv { 696struct iwl3945_priv {
@@ -780,12 +784,17 @@ struct iwl3945_priv {
780 struct iwl3945_init_alive_resp card_alive_init; 784 struct iwl3945_init_alive_resp card_alive_init;
781 struct iwl3945_alive_resp card_alive; 785 struct iwl3945_alive_resp card_alive;
782 786
787#ifdef CONFIG_IWL3945_RFKILL
788 struct rfkill *rfkill;
789#endif
790
783#ifdef CONFIG_IWL3945_LEDS 791#ifdef CONFIG_IWL3945_LEDS
784 struct iwl3945_led led[IWL_LED_TRG_MAX]; 792 struct iwl3945_led led[IWL_LED_TRG_MAX];
785 unsigned long last_blink_time; 793 unsigned long last_blink_time;
786 u8 last_blink_rate; 794 u8 last_blink_rate;
787 u8 allow_blinking; 795 u8 allow_blinking;
788 unsigned int rxtxpackets; 796 unsigned int rxtxpackets;
797 u64 led_tpt;
789#endif 798#endif
790 799
791 800
@@ -836,20 +845,10 @@ struct iwl3945_priv {
836 845
837 u8 mac80211_registered; 846 u8 mac80211_registered;
838 847
839 u32 notif_missed_beacons;
840
841 /* Rx'd packet timing information */ 848 /* Rx'd packet timing information */
842 u32 last_beacon_time; 849 u32 last_beacon_time;
843 u64 last_tsf; 850 u64 last_tsf;
844 851
845 /* Duplicate packet detection */
846 u16 last_seq_num;
847 u16 last_frag_num;
848 unsigned long last_packet_time;
849
850 /* Hash table for finding stations in IBSS network */
851 struct list_head ibss_mac_hash[IWL_IBSS_MAC_HASH_SIZE];
852
853 /* eeprom */ 852 /* eeprom */
854 struct iwl3945_eeprom eeprom; 853 struct iwl3945_eeprom eeprom;
855 854
@@ -886,6 +885,7 @@ struct iwl3945_priv {
886 struct work_struct report_work; 885 struct work_struct report_work;
887 struct work_struct request_scan; 886 struct work_struct request_scan;
888 struct work_struct beacon_update; 887 struct work_struct beacon_update;
888 struct work_struct set_monitor;
889 889
890 struct tasklet_struct irq_tasklet; 890 struct tasklet_struct irq_tasklet;
891 891
@@ -924,11 +924,6 @@ static inline int is_channel_valid(const struct iwl3945_channel_info *ch_info)
924 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; 924 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
925} 925}
926 926
927static inline int is_channel_narrow(const struct iwl3945_channel_info *ch_info)
928{
929 return (ch_info->flags & EEPROM_CHANNEL_NARROW) ? 1 : 0;
930}
931
932static inline int is_channel_radar(const struct iwl3945_channel_info *ch_info) 927static inline int is_channel_radar(const struct iwl3945_channel_info *ch_info)
933{ 928{
934 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; 929 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
index 1a66b508a8ea..fce950f4163c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
@@ -62,13 +62,18 @@
62 *****************************************************************************/ 62 *****************************************************************************/
63/* 63/*
64 * Please use this file (iwl-4965-hw.h) only for hardware-related definitions. 64 * Please use this file (iwl-4965-hw.h) only for hardware-related definitions.
65 * Use iwl-4965-commands.h for uCode API definitions. 65 * Use iwl-commands.h for uCode API definitions.
66 * Use iwl-4965.h for driver implementation definitions. 66 * Use iwl-dev.h for driver implementation definitions.
67 */ 67 */
68 68
69#ifndef __iwl_4965_hw_h__ 69#ifndef __iwl_4965_hw_h__
70#define __iwl_4965_hw_h__ 70#define __iwl_4965_hw_h__
71 71
72#include "iwl-fh.h"
73
74/* EERPROM */
75#define IWL4965_EEPROM_IMG_SIZE 1024
76
72/* 77/*
73 * uCode queue management definitions ... 78 * uCode queue management definitions ...
74 * Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4. 79 * Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4.
@@ -77,7 +82,7 @@
77 */ 82 */
78#define IWL_CMD_QUEUE_NUM 4 83#define IWL_CMD_QUEUE_NUM 4
79#define IWL_CMD_FIFO_NUM 4 84#define IWL_CMD_FIFO_NUM 4
80#define IWL_BACK_QUEUE_FIRST_ID 7 85#define IWL49_FIRST_AMPDU_QUEUE 7
81 86
82/* Tx rates */ 87/* Tx rates */
83#define IWL_CCK_RATES 4 88#define IWL_CCK_RATES 4
@@ -93,11 +98,16 @@
93#define IWL_RSSI_OFFSET 44 98#define IWL_RSSI_OFFSET 44
94 99
95 100
96#include "iwl-4965-commands.h" 101#include "iwl-commands.h"
97 102
98#define PCI_LINK_CTRL 0x0F0 103/* PCI registers */
104#define PCI_LINK_CTRL 0x0F0 /* 1 byte */
99#define PCI_POWER_SOURCE 0x0C8 105#define PCI_POWER_SOURCE 0x0C8
100#define PCI_REG_WUM8 0x0E8 106#define PCI_REG_WUM8 0x0E8
107
108/* PCI register values */
109#define PCI_LINK_VAL_L0S_EN 0x01
110#define PCI_LINK_VAL_L1_EN 0x02
101#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) 111#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
102 112
103#define TFD_QUEUE_SIZE_MAX (256) 113#define TFD_QUEUE_SIZE_MAX (256)
@@ -131,10 +141,8 @@
131#define RTC_DATA_LOWER_BOUND (0x800000) 141#define RTC_DATA_LOWER_BOUND (0x800000)
132#define IWL49_RTC_DATA_UPPER_BOUND (0x80A000) 142#define IWL49_RTC_DATA_UPPER_BOUND (0x80A000)
133 143
134#define IWL49_RTC_INST_SIZE \ 144#define IWL49_RTC_INST_SIZE (IWL49_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
135 (IWL49_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND) 145#define IWL49_RTC_DATA_SIZE (IWL49_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
136#define IWL49_RTC_DATA_SIZE \
137 (IWL49_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
138 146
139#define IWL_MAX_INST_SIZE IWL49_RTC_INST_SIZE 147#define IWL_MAX_INST_SIZE IWL49_RTC_INST_SIZE
140#define IWL_MAX_DATA_SIZE IWL49_RTC_DATA_SIZE 148#define IWL_MAX_DATA_SIZE IWL49_RTC_DATA_SIZE
@@ -785,585 +793,6 @@ enum {
785 793
786/********************* END TXPOWER *****************************************/ 794/********************* END TXPOWER *****************************************/
787 795
788/****************************/
789/* Flow Handler Definitions */
790/****************************/
791
792/**
793 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
794 * Addresses are offsets from device's PCI hardware base address.
795 */
796#define FH_MEM_LOWER_BOUND (0x1000)
797#define FH_MEM_UPPER_BOUND (0x1EF0)
798
799/**
800 * Keep-Warm (KW) buffer base address.
801 *
802 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
803 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
804 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
805 * from going into a power-savings mode that would cause higher DRAM latency,
806 * and possible data over/under-runs, before all Tx/Rx is complete.
807 *
808 * Driver loads IWL_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
809 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
810 * automatically invokes keep-warm accesses when normal accesses might not
811 * be sufficient to maintain fast DRAM response.
812 *
813 * Bit fields:
814 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
815 */
816#define IWL_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
817
818
819/**
820 * TFD Circular Buffers Base (CBBC) addresses
821 *
822 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
823 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
824 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
825 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
826 * aligned (address bits 0-7 must be 0).
827 *
828 * Bit fields in each pointer register:
829 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
830 */
831#define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
832#define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
833
834/* Find TFD CB base pointer for given queue (range 0-15). */
835#define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
836
837
838/**
839 * Rx SRAM Control and Status Registers (RSCSR)
840 *
841 * These registers provide handshake between driver and 4965 for the Rx queue
842 * (this queue handles *all* command responses, notifications, Rx data, etc.
843 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
844 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
845 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
846 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
847 * mapping between RBDs and RBs.
848 *
849 * Driver must allocate host DRAM memory for the following, and set the
850 * physical address of each into 4965 registers:
851 *
852 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
853 * entries (although any power of 2, up to 4096, is selectable by driver).
854 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
855 * (typically 4K, although 8K or 16K are also selectable by driver).
856 * Driver sets up RB size and number of RBDs in the CB via Rx config
857 * register FH_MEM_RCSR_CHNL0_CONFIG_REG.
858 *
859 * Bit fields within one RBD:
860 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
861 *
862 * Driver sets physical address [35:8] of base of RBD circular buffer
863 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
864 *
865 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
866 * (RBs) have been filled, via a "write pointer", actually the index of
867 * the RB's corresponding RBD within the circular buffer. Driver sets
868 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
869 *
870 * Bit fields in lower dword of Rx status buffer (upper dword not used
871 * by driver; see struct iwl4965_shared, val0):
872 * 31-12: Not used by driver
873 * 11- 0: Index of last filled Rx buffer descriptor
874 * (4965 writes, driver reads this value)
875 *
876 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
877 * enter pointers to these RBs into contiguous RBD circular buffer entries,
878 * and update the 4965's "write" index register, FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
879 *
880 * This "write" index corresponds to the *next* RBD that the driver will make
881 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
882 * the circular buffer. This value should initially be 0 (before preparing any
883 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
884 * wrap back to 0 at the end of the circular buffer (but don't wrap before
885 * "read" index has advanced past 1! See below).
886 * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
887 *
888 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
889 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
890 * to tell the driver the index of the latest filled RBD. The driver must
891 * read this "read" index from DRAM after receiving an Rx interrupt from 4965.
892 *
893 * The driver must also internally keep track of a third index, which is the
894 * next RBD to process. When receiving an Rx interrupt, driver should process
895 * all filled but unprocessed RBs up to, but not including, the RB
896 * corresponding to the "read" index. For example, if "read" index becomes "1",
897 * driver may process the RB pointed to by RBD 0. Depending on volume of
898 * traffic, there may be many RBs to process.
899 *
900 * If read index == write index, 4965 thinks there is no room to put new data.
901 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
902 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
903 * and "read" indexes; that is, make sure that there are no more than 254
904 * buffers waiting to be filled.
905 */
906#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
907#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
908#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
909
910/**
911 * Physical base address of 8-byte Rx Status buffer.
912 * Bit fields:
913 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
914 */
915#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
916
917/**
918 * Physical base address of Rx Buffer Descriptor Circular Buffer.
919 * Bit fields:
920 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
921 */
922#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
923
924/**
925 * Rx write pointer (index, really!).
926 * Bit fields:
927 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
928 * NOTE: For 256-entry circular buffer, use only bits [7:0].
929 */
930#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
931#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
932
933
934/**
935 * Rx Config/Status Registers (RCSR)
936 * Rx Config Reg for channel 0 (only channel used)
937 *
938 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
939 * normal operation (see bit fields).
940 *
941 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
942 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
943 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
944 *
945 * Bit fields:
946 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
947 * '10' operate normally
948 * 29-24: reserved
949 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
950 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
951 * 19-18: reserved
952 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
953 * '10' 12K, '11' 16K.
954 * 15-14: reserved
955 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
956 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
957 * typical value 0x10 (about 1/2 msec)
958 * 3- 0: reserved
959 */
960#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
961#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
962#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
963
964#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
965
966#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */
967#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */
968#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */
969#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */
970#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */
971#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */
972
973#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
974#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT (4)
975#define RX_RB_TIMEOUT (0x10)
976
977#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
978#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
979#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
980
981#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
982#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
983#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
984#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
985
986#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
987#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
988
989
990/**
991 * Rx Shared Status Registers (RSSR)
992 *
993 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG),
994 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
995 *
996 * Bit fields:
997 * 24: 1 = Channel 0 is idle
998 *
999 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV contain
1000 * default values that should not be altered by the driver.
1001 */
1002#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
1003#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
1004
1005#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
1006#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
1007#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008)
1008
1009#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1010
1011
1012/**
1013 * Transmit DMA Channel Control/Status Registers (TCSR)
1014 *
1015 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
1016 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1017 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1018 *
1019 * To use a Tx DMA channel, driver must initialize its
1020 * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1021 *
1022 * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1023 * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1024 *
1025 * All other bits should be 0.
1026 *
1027 * Bit fields:
1028 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1029 * '10' operate normally
1030 * 29- 4: Reserved, set to "0"
1031 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1032 * 2- 0: Reserved, set to "0"
1033 */
1034#define IWL_FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
1035#define IWL_FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
1036
1037/* Find Control/Status reg for given Tx DMA/FIFO channel */
1038#define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1039 (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
1040
1041#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
1042#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
1043
1044#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1045#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1046#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1047
1048/**
1049 * Tx Shared Status Registers (TSSR)
1050 *
1051 * After stopping Tx DMA channel (writing 0 to
1052 * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1053 * IWL_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1054 * (channel's buffers empty | no pending requests).
1055 *
1056 * Bit fields:
1057 * 31-24: 1 = Channel buffers empty (channel 7:0)
1058 * 23-16: 1 = No pending requests (channel 7:0)
1059 */
1060#define IWL_FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
1061#define IWL_FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
1062
1063#define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010)
1064
1065#define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \
1066 ((1 << (_chnl)) << 24)
1067#define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \
1068 ((1 << (_chnl)) << 16)
1069
1070#define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
1071 (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
1072 IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
1073
1074
1075/********************* START TX SCHEDULER *************************************/
1076
1077/**
1078 * 4965 Tx Scheduler
1079 *
1080 * The Tx Scheduler selects the next frame to be transmitted, chosing TFDs
1081 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
1082 * host DRAM. It steers each frame's Tx command (which contains the frame
1083 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1084 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
1085 * but one DMA channel may take input from several queues.
1086 *
1087 * Tx DMA channels have dedicated purposes. For 4965, they are used as follows:
1088 *
1089 * 0 -- EDCA BK (background) frames, lowest priority
1090 * 1 -- EDCA BE (best effort) frames, normal priority
1091 * 2 -- EDCA VI (video) frames, higher priority
1092 * 3 -- EDCA VO (voice) and management frames, highest priority
1093 * 4 -- Commands (e.g. RXON, etc.)
1094 * 5 -- HCCA short frames
1095 * 6 -- HCCA long frames
1096 * 7 -- not used by driver (device-internal only)
1097 *
1098 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1099 * In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to
1100 * support 11n aggregation via EDCA DMA channels.
1101 *
1102 * The driver sets up each queue to work in one of two modes:
1103 *
1104 * 1) Scheduler-Ack, in which the scheduler automatically supports a
1105 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1106 * contains TFDs for a unique combination of Recipient Address (RA)
1107 * and Traffic Identifier (TID), that is, traffic of a given
1108 * Quality-Of-Service (QOS) priority, destined for a single station.
1109 *
1110 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1111 * each frame within the BA window, including whether it's been transmitted,
1112 * and whether it's been acknowledged by the receiving station. The device
1113 * automatically processes block-acks received from the receiving STA,
1114 * and reschedules un-acked frames to be retransmitted (successful
1115 * Tx completion may end up being out-of-order).
1116 *
1117 * The driver must maintain the queue's Byte Count table in host DRAM
1118 * (struct iwl4965_sched_queue_byte_cnt_tbl) for this mode.
1119 * This mode does not support fragmentation.
1120 *
1121 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1122 * The device may automatically retry Tx, but will retry only one frame
1123 * at a time, until receiving ACK from receiving station, or reaching
1124 * retry limit and giving up.
1125 *
1126 * The command queue (#4) must use this mode!
1127 * This mode does not require use of the Byte Count table in host DRAM.
1128 *
1129 * Driver controls scheduler operation via 3 means:
1130 * 1) Scheduler registers
1131 * 2) Shared scheduler data base in internal 4956 SRAM
1132 * 3) Shared data in host DRAM
1133 *
1134 * Initialization:
1135 *
1136 * When loading, driver should allocate memory for:
1137 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
1138 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
1139 * (1024 bytes for each queue).
1140 *
1141 * After receiving "Alive" response from uCode, driver must initialize
1142 * the scheduler (especially for queue #4, the command queue, otherwise
1143 * the driver can't issue commands!):
1144 */
1145
1146/**
1147 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1148 * can keep track of at one time when creating block-ack chains of frames.
1149 * Note that "64" matches the number of ack bits in a block-ack packet.
1150 * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize
1151 * SCD_CONTEXT_QUEUE_OFFSET(x) values.
1152 */
1153#define SCD_WIN_SIZE 64
1154#define SCD_FRAME_LIMIT 64
1155
1156/* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */
1157#define SCD_START_OFFSET 0xa02c00
1158
1159/*
1160 * 4965 tells driver SRAM address for internal scheduler structs via this reg.
1161 * Value is valid only after "Alive" response from uCode.
1162 */
1163#define SCD_SRAM_BASE_ADDR (SCD_START_OFFSET + 0x0)
1164
1165/*
1166 * Driver may need to update queue-empty bits after changing queue's
1167 * write and read pointers (indexes) during (re-)initialization (i.e. when
1168 * scheduler is not tracking what's happening).
1169 * Bit fields:
1170 * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit
1171 * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty
1172 * NOTE: This register is not used by Linux driver.
1173 */
1174#define SCD_EMPTY_BITS (SCD_START_OFFSET + 0x4)
1175
1176/*
1177 * Physical base address of array of byte count (BC) circular buffers (CBs).
1178 * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode.
1179 * This register points to BC CB for queue 0, must be on 1024-byte boundary.
1180 * Others are spaced by 1024 bytes.
1181 * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad.
1182 * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff).
1183 * Bit fields:
1184 * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned.
1185 */
1186#define SCD_DRAM_BASE_ADDR (SCD_START_OFFSET + 0x10)
1187
1188/*
1189 * Enables any/all Tx DMA/FIFO channels.
1190 * Scheduler generates requests for only the active channels.
1191 * Set this to 0xff to enable all 8 channels (normal usage).
1192 * Bit fields:
1193 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7
1194 */
1195#define SCD_TXFACT (SCD_START_OFFSET + 0x1c)
1196
1197/* Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". */
1198#define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
1199 ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
1200
1201/*
1202 * Queue (x) Write Pointers (indexes, really!), one for each Tx queue.
1203 * Initialized and updated by driver as new TFDs are added to queue.
1204 * NOTE: If using Block Ack, index must correspond to frame's
1205 * Start Sequence Number; index = (SSN & 0xff)
1206 * NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses?
1207 */
1208#define SCD_QUEUE_WRPTR(x) (SCD_START_OFFSET + 0x24 + (x) * 4)
1209
1210/*
1211 * Queue (x) Read Pointers (indexes, really!), one for each Tx queue.
1212 * For FIFO mode, index indicates next frame to transmit.
1213 * For Scheduler-ACK mode, index indicates first frame in Tx window.
1214 * Initialized by driver, updated by scheduler.
1215 */
1216#define SCD_QUEUE_RDPTR(x) (SCD_START_OFFSET + 0x64 + (x) * 4)
1217
1218/*
1219 * Select which queues work in chain mode (1) vs. not (0).
1220 * Use chain mode to build chains of aggregated frames.
1221 * Bit fields:
1222 * 31-16: Reserved
1223 * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time
1224 * NOTE: If driver sets up queue for chain mode, it should be also set up
1225 * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x).
1226 */
1227#define SCD_QUEUECHAIN_SEL (SCD_START_OFFSET + 0xd0)
1228
1229/*
1230 * Select which queues interrupt driver when scheduler increments
1231 * a queue's read pointer (index).
1232 * Bit fields:
1233 * 31-16: Reserved
1234 * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled
1235 * NOTE: This functionality is apparently a no-op; driver relies on interrupts
1236 * from Rx queue to read Tx command responses and update Tx queues.
1237 */
1238#define SCD_INTERRUPT_MASK (SCD_START_OFFSET + 0xe4)
1239
1240/*
1241 * Queue search status registers. One for each queue.
1242 * Sets up queue mode and assigns queue to Tx DMA channel.
1243 * Bit fields:
1244 * 19-10: Write mask/enable bits for bits 0-9
1245 * 9: Driver should init to "0"
1246 * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0).
1247 * Driver should init to "1" for aggregation mode, or "0" otherwise.
1248 * 7-6: Driver should init to "0"
1249 * 5: Window Size Left; indicates whether scheduler can request
1250 * another TFD, based on window size, etc. Driver should init
1251 * this bit to "1" for aggregation mode, or "0" for non-agg.
1252 * 4-1: Tx FIFO to use (range 0-7).
1253 * 0: Queue is active (1), not active (0).
1254 * Other bits should be written as "0"
1255 *
1256 * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled
1257 * via SCD_QUEUECHAIN_SEL.
1258 */
1259#define SCD_QUEUE_STATUS_BITS(x) (SCD_START_OFFSET + 0x104 + (x) * 4)
1260
1261/* Bit field positions */
1262#define SCD_QUEUE_STTS_REG_POS_ACTIVE (0)
1263#define SCD_QUEUE_STTS_REG_POS_TXF (1)
1264#define SCD_QUEUE_STTS_REG_POS_WSL (5)
1265#define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)
1266
1267/* Write masks */
1268#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)
1269#define SCD_QUEUE_STTS_REG_MSK (0x0007FC00)
1270
1271/**
1272 * 4965 internal SRAM structures for scheduler, shared with driver ...
1273 *
1274 * Driver should clear and initialize the following areas after receiving
1275 * "Alive" response from 4965 uCode, i.e. after initial
1276 * uCode load, or after a uCode load done for error recovery:
1277 *
1278 * SCD_CONTEXT_DATA_OFFSET (size 128 bytes)
1279 * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes)
1280 * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes)
1281 *
1282 * Driver accesses SRAM via HBUS_TARG_MEM_* registers.
1283 * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR.
1284 * All OFFSET values must be added to this base address.
1285 */
1286
1287/*
1288 * Queue context. One 8-byte entry for each of 16 queues.
1289 *
1290 * Driver should clear this entire area (size 0x80) to 0 after receiving
1291 * "Alive" notification from uCode. Additionally, driver should init
1292 * each queue's entry as follows:
1293 *
1294 * LS Dword bit fields:
1295 * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64.
1296 *
1297 * MS Dword bit fields:
1298 * 16-22: Frame limit. Driver should init to 10 (0xa).
1299 *
1300 * Driver should init all other bits to 0.
1301 *
1302 * Init must be done after driver receives "Alive" response from 4965 uCode,
1303 * and when setting up queue for aggregation.
1304 */
1305#define SCD_CONTEXT_DATA_OFFSET 0x380
1306#define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
1307
1308#define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)
1309#define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)
1310#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1311#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1312
1313/*
1314 * Tx Status Bitmap
1315 *
1316 * Driver should clear this entire area (size 0x100) to 0 after receiving
1317 * "Alive" notification from uCode. Area is used only by device itself;
1318 * no other support (besides clearing) is required from driver.
1319 */
1320#define SCD_TX_STTS_BITMAP_OFFSET 0x400
1321
1322/*
1323 * RAxTID to queue translation mapping.
1324 *
1325 * When queue is in Scheduler-ACK mode, frames placed in a that queue must be
1326 * for only one combination of receiver address (RA) and traffic ID (TID), i.e.
1327 * one QOS priority level destined for one station (for this wireless link,
1328 * not final destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit
1329 * mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK
1330 * mode, the device ignores the mapping value.
1331 *
1332 * Bit fields, for each 16-bit map:
1333 * 15-9: Reserved, set to 0
1334 * 8-4: Index into device's station table for recipient station
1335 * 3-0: Traffic ID (tid), range 0-15
1336 *
1337 * Driver should clear this entire area (size 32 bytes) to 0 after receiving
1338 * "Alive" notification from uCode. To update a 16-bit map value, driver
1339 * must read a dword-aligned value from device SRAM, replace the 16-bit map
1340 * value of interest, and write the dword value back into device SRAM.
1341 */
1342#define SCD_TRANSLATE_TBL_OFFSET 0x500
1343
1344/* Find translation table dword to read/write for given queue */
1345#define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
1346 ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
1347
1348#define SCD_TXFIFO_POS_TID (0)
1349#define SCD_TXFIFO_POS_RA (4)
1350#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1351
1352/*********************** END TX SCHEDULER *************************************/
1353
1354static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags)
1355{
1356 return le32_to_cpu(rate_n_flags) & 0xFF;
1357}
1358static inline u16 iwl4965_hw_get_rate_n_flags(__le32 rate_n_flags)
1359{
1360 return le32_to_cpu(rate_n_flags) & 0xFFFF;
1361}
1362static inline __le32 iwl4965_hw_set_rate_n_flags(u8 rate, u16 flags)
1363{
1364 return cpu_to_le32(flags|(u16)rate);
1365}
1366
1367 796
1368/** 797/**
1369 * Tx/Rx Queues 798 * Tx/Rx Queues
@@ -1385,14 +814,15 @@ static inline __le32 iwl4965_hw_set_rate_n_flags(u8 rate, u16 flags)
1385 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array 814 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
1386 * in DRAM containing 256 Transmit Frame Descriptors (TFDs). 815 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
1387 */ 816 */
1388#define IWL4965_MAX_WIN_SIZE 64 817#define IWL49_MAX_WIN_SIZE 64
1389#define IWL4965_QUEUE_SIZE 256 818#define IWL49_QUEUE_SIZE 256
1390#define IWL4965_NUM_FIFOS 7 819#define IWL49_NUM_FIFOS 7
1391#define IWL4965_MAX_NUM_QUEUES 16 820#define IWL49_CMD_FIFO_NUM 4
1392 821#define IWL49_NUM_QUEUES 16
822#define IWL49_NUM_AMPDU_QUEUES 8
1393 823
1394/** 824/**
1395 * struct iwl4965_tfd_frame_data 825 * struct iwl_tfd_frame_data
1396 * 826 *
1397 * Describes up to 2 buffers containing (contiguous) portions of a Tx frame. 827 * Describes up to 2 buffers containing (contiguous) portions of a Tx frame.
1398 * Each buffer must be on dword boundary. 828 * Each buffer must be on dword boundary.
@@ -1411,7 +841,7 @@ static inline __le32 iwl4965_hw_set_rate_n_flags(u8 rate, u16 flags)
1411 * 31-20: Tx buffer 2 length (bytes) 841 * 31-20: Tx buffer 2 length (bytes)
1412 * 19- 0: Tx buffer 2 address bits [35:16] 842 * 19- 0: Tx buffer 2 address bits [35:16]
1413 */ 843 */
1414struct iwl4965_tfd_frame_data { 844struct iwl_tfd_frame_data {
1415 __le32 tb1_addr; 845 __le32 tb1_addr;
1416 846
1417 __le32 val1; 847 __le32 val1;
@@ -1441,7 +871,7 @@ struct iwl4965_tfd_frame_data {
1441 871
1442 872
1443/** 873/**
1444 * struct iwl4965_tfd_frame 874 * struct iwl_tfd_frame
1445 * 875 *
1446 * Transmit Frame Descriptor (TFD) 876 * Transmit Frame Descriptor (TFD)
1447 * 877 *
@@ -1468,7 +898,7 @@ struct iwl4965_tfd_frame_data {
1468 * 898 *
1469 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 899 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1470 */ 900 */
1471struct iwl4965_tfd_frame { 901struct iwl_tfd_frame {
1472 __le32 val0; 902 __le32 val0;
1473 /* __le32 rsvd1:24; */ 903 /* __le32 rsvd1:24; */
1474 /* __le32 num_tbs:5; */ 904 /* __le32 num_tbs:5; */
@@ -1477,7 +907,7 @@ struct iwl4965_tfd_frame {
1477#define IWL_num_tbs_SYM val0 907#define IWL_num_tbs_SYM val0
1478 /* __le32 rsvd2:1; */ 908 /* __le32 rsvd2:1; */
1479 /* __le32 padding:2; */ 909 /* __le32 padding:2; */
1480 struct iwl4965_tfd_frame_data pa[10]; 910 struct iwl_tfd_frame_data pa[10];
1481 __le32 reserved; 911 __le32 reserved;
1482} __attribute__ ((packed)); 912} __attribute__ ((packed));
1483 913
@@ -1520,10 +950,10 @@ struct iwl4965_queue_byte_cnt_entry {
1520 * 4965 assumes tables are separated by 1024 bytes. 950 * 4965 assumes tables are separated by 1024 bytes.
1521 */ 951 */
1522struct iwl4965_sched_queue_byte_cnt_tbl { 952struct iwl4965_sched_queue_byte_cnt_tbl {
1523 struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE + 953 struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL49_QUEUE_SIZE +
1524 IWL4965_MAX_WIN_SIZE]; 954 IWL49_MAX_WIN_SIZE];
1525 u8 dont_care[1024 - 955 u8 dont_care[1024 -
1526 (IWL4965_QUEUE_SIZE + IWL4965_MAX_WIN_SIZE) * 956 (IWL49_QUEUE_SIZE + IWL49_MAX_WIN_SIZE) *
1527 sizeof(__le16)]; 957 sizeof(__le16)];
1528} __attribute__ ((packed)); 958} __attribute__ ((packed));
1529 959
@@ -1553,7 +983,7 @@ struct iwl4965_sched_queue_byte_cnt_tbl {
1553 */ 983 */
1554struct iwl4965_shared { 984struct iwl4965_shared {
1555 struct iwl4965_sched_queue_byte_cnt_tbl 985 struct iwl4965_sched_queue_byte_cnt_tbl
1556 queues_byte_cnt_tbls[IWL4965_MAX_NUM_QUEUES]; 986 queues_byte_cnt_tbls[IWL49_NUM_QUEUES];
1557 __le32 rb_closed; 987 __le32 rb_closed;
1558 988
1559 /* __le32 rb_closed_stts_rb_num:12; */ 989 /* __le32 rb_closed_stts_rb_num:12; */
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-rs.c b/drivers/net/wireless/iwlwifi/iwl-4965-rs.c
index 3a7f0cb710ec..3ccb84aa5dbc 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-rs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-rs.c
@@ -28,7 +28,6 @@
28#include <linux/skbuff.h> 28#include <linux/skbuff.h>
29#include <linux/wireless.h> 29#include <linux/wireless.h>
30#include <net/mac80211.h> 30#include <net/mac80211.h>
31#include <net/ieee80211.h>
32 31
33#include <linux/netdevice.h> 32#include <linux/netdevice.h>
34#include <linux/etherdevice.h> 33#include <linux/etherdevice.h>
@@ -38,13 +37,14 @@
38 37
39#include "../net/mac80211/rate.h" 38#include "../net/mac80211/rate.h"
40 39
41#include "iwl-4965.h" 40#include "iwl-dev.h"
41#include "iwl-sta.h"
42#include "iwl-core.h" 42#include "iwl-core.h"
43#include "iwl-helpers.h" 43#include "iwl-helpers.h"
44 44
45#define RS_NAME "iwl-4965-rs" 45#define RS_NAME "iwl-4965-rs"
46 46
47#define NUM_TRY_BEFORE_ANTENNA_TOGGLE 1 47#define NUM_TRY_BEFORE_ANT_TOGGLE 1
48#define IWL_NUMBER_TRY 1 48#define IWL_NUMBER_TRY 1
49#define IWL_HT_NUMBER_TRY 3 49#define IWL_HT_NUMBER_TRY 3
50 50
@@ -65,9 +65,16 @@ static u8 rs_ht_to_legacy[] = {
65 IWL_RATE_48M_INDEX, IWL_RATE_54M_INDEX 65 IWL_RATE_48M_INDEX, IWL_RATE_54M_INDEX
66}; 66};
67 67
68struct iwl4965_rate { 68static const u8 ant_toggle_lookup[] = {
69 u32 rate_n_flags; 69 /*ANT_NONE -> */ ANT_NONE,
70} __attribute__ ((packed)); 70 /*ANT_A -> */ ANT_B,
71 /*ANT_B -> */ ANT_C,
72 /*ANT_AB -> */ ANT_BC,
73 /*ANT_C -> */ ANT_A,
74 /*ANT_AC -> */ ANT_AB,
75 /*ANT_BC -> */ ANT_AC,
76 /*ANT_ABC -> */ ANT_ABC,
77};
71 78
72/** 79/**
73 * struct iwl4965_rate_scale_data -- tx success history for one rate 80 * struct iwl4965_rate_scale_data -- tx success history for one rate
@@ -88,19 +95,17 @@ struct iwl4965_rate_scale_data {
88 * one for "active", and one for "search". 95 * one for "active", and one for "search".
89 */ 96 */
90struct iwl4965_scale_tbl_info { 97struct iwl4965_scale_tbl_info {
91 enum iwl4965_table_type lq_type; 98 enum iwl_table_type lq_type;
92 enum iwl4965_antenna_type antenna_type; 99 u8 ant_type;
93 u8 is_SGI; /* 1 = short guard interval */ 100 u8 is_SGI; /* 1 = short guard interval */
94 u8 is_fat; /* 1 = 40 MHz channel width */ 101 u8 is_fat; /* 1 = 40 MHz channel width */
95 u8 is_dup; /* 1 = duplicated data streams */ 102 u8 is_dup; /* 1 = duplicated data streams */
96 u8 action; /* change modulation; IWL_[LEGACY/SISO/MIMO]_SWITCH_* */ 103 u8 action; /* change modulation; IWL_[LEGACY/SISO/MIMO]_SWITCH_* */
97 s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */ 104 s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */
98 struct iwl4965_rate current_rate; /* rate_n_flags, uCode API format */ 105 u32 current_rate; /* rate_n_flags, uCode API format */
99 struct iwl4965_rate_scale_data win[IWL_RATE_COUNT]; /* rate histories */ 106 struct iwl4965_rate_scale_data win[IWL_RATE_COUNT]; /* rate histories */
100}; 107};
101 108
102#ifdef CONFIG_IWL4965_HT
103
104struct iwl4965_traffic_load { 109struct iwl4965_traffic_load {
105 unsigned long time_stamp; /* age of the oldest statistics */ 110 unsigned long time_stamp; /* age of the oldest statistics */
106 u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time 111 u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time
@@ -112,8 +117,6 @@ struct iwl4965_traffic_load {
112 u8 head; /* start of the circular buffer */ 117 u8 head; /* start of the circular buffer */
113}; 118};
114 119
115#endif /* CONFIG_IWL4965_HT */
116
117/** 120/**
118 * struct iwl4965_lq_sta -- driver's rate scaling private structure 121 * struct iwl4965_lq_sta -- driver's rate scaling private structure
119 * 122 *
@@ -136,8 +139,6 @@ struct iwl4965_lq_sta {
136 u32 flush_timer; /* time staying in mode before new search */ 139 u32 flush_timer; /* time staying in mode before new search */
137 140
138 u8 action_counter; /* # mode-switch actions tried */ 141 u8 action_counter; /* # mode-switch actions tried */
139 u8 antenna;
140 u8 valid_antenna;
141 u8 is_green; 142 u8 is_green;
142 u8 is_dup; 143 u8 is_dup;
143 enum ieee80211_band band; 144 enum ieee80211_band band;
@@ -145,24 +146,21 @@ struct iwl4965_lq_sta {
145 146
146 /* The following are bitmaps of rates; IWL_RATE_6M_MASK, etc. */ 147 /* The following are bitmaps of rates; IWL_RATE_6M_MASK, etc. */
147 u32 supp_rates; 148 u32 supp_rates;
148 u16 active_rate; 149 u16 active_legacy_rate;
149 u16 active_siso_rate; 150 u16 active_siso_rate;
150 u16 active_mimo_rate; 151 u16 active_mimo2_rate;
152 u16 active_mimo3_rate;
151 u16 active_rate_basic; 153 u16 active_rate_basic;
152 154
153 struct iwl_link_quality_cmd lq; 155 struct iwl_link_quality_cmd lq;
154 struct iwl4965_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */ 156 struct iwl4965_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */
155#ifdef CONFIG_IWL4965_HT
156 struct iwl4965_traffic_load load[TID_MAX_LOAD_COUNT]; 157 struct iwl4965_traffic_load load[TID_MAX_LOAD_COUNT];
157 u8 tx_agg_tid_en; 158 u8 tx_agg_tid_en;
158#endif
159#ifdef CONFIG_MAC80211_DEBUGFS 159#ifdef CONFIG_MAC80211_DEBUGFS
160 struct dentry *rs_sta_dbgfs_scale_table_file; 160 struct dentry *rs_sta_dbgfs_scale_table_file;
161 struct dentry *rs_sta_dbgfs_stats_table_file; 161 struct dentry *rs_sta_dbgfs_stats_table_file;
162#ifdef CONFIG_IWL4965_HT
163 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file; 162 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
164#endif 163 u32 dbg_fixed_rate;
165 struct iwl4965_rate dbg_fixed;
166#endif 164#endif
167 struct iwl_priv *drv; 165 struct iwl_priv *drv;
168}; 166};
@@ -171,17 +169,17 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
171 struct net_device *dev, 169 struct net_device *dev,
172 struct ieee80211_hdr *hdr, 170 struct ieee80211_hdr *hdr,
173 struct sta_info *sta); 171 struct sta_info *sta);
174static void rs_fill_link_cmd(struct iwl4965_lq_sta *lq_sta, 172static void rs_fill_link_cmd(const struct iwl_priv *priv,
175 struct iwl4965_rate *tx_mcs, 173 struct iwl4965_lq_sta *lq_sta,
176 struct iwl_link_quality_cmd *tbl); 174 u32 rate_n_flags);
177 175
178 176
179#ifdef CONFIG_MAC80211_DEBUGFS 177#ifdef CONFIG_MAC80211_DEBUGFS
180static void rs_dbgfs_set_mcs(struct iwl4965_lq_sta *lq_sta, 178static void rs_dbgfs_set_mcs(struct iwl4965_lq_sta *lq_sta,
181 struct iwl4965_rate *mcs, int index); 179 u32 *rate_n_flags, int index);
182#else 180#else
183static void rs_dbgfs_set_mcs(struct iwl4965_lq_sta *lq_sta, 181static void rs_dbgfs_set_mcs(struct iwl4965_lq_sta *lq_sta,
184 struct iwl4965_rate *mcs, int index) 182 u32 *rate_n_flags, int index)
185{} 183{}
186#endif 184#endif
187 185
@@ -190,6 +188,7 @@ static void rs_dbgfs_set_mcs(struct iwl4965_lq_sta *lq_sta,
190 * 1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54, 60 MBits 188 * 1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54, 60 MBits
191 * "G" is the only table that supports CCK (the first 4 rates). 189 * "G" is the only table that supports CCK (the first 4 rates).
192 */ 190 */
191/*FIXME:RS:need to spearate tables for MIMO2/MIMO3*/
193static s32 expected_tpt_A[IWL_RATE_COUNT] = { 192static s32 expected_tpt_A[IWL_RATE_COUNT] = {
194 0, 0, 0, 0, 40, 57, 72, 98, 121, 154, 177, 186, 186 193 0, 0, 0, 0, 40, 57, 72, 98, 121, 154, 177, 186, 186
195}; 194};
@@ -230,7 +229,7 @@ static s32 expected_tpt_mimo40MHzSGI[IWL_RATE_COUNT] = {
230 0, 0, 0, 0, 131, 131, 191, 222, 242, 270, 284, 289, 293 229 0, 0, 0, 0, 131, 131, 191, 222, 242, 270, 284, 289, 293
231}; 230};
232 231
233static inline u8 iwl4965_rate_get_rate(u32 rate_n_flags) 232static inline u8 rs_extract_rate(u32 rate_n_flags)
234{ 233{
235 return (u8)(rate_n_flags & 0xFF); 234 return (u8)(rate_n_flags & 0xFF);
236} 235}
@@ -245,7 +244,11 @@ static void rs_rate_scale_clear_window(struct iwl4965_rate_scale_data *window)
245 window->stamp = 0; 244 window->stamp = 0;
246} 245}
247 246
248#ifdef CONFIG_IWL4965_HT 247static inline u8 rs_is_valid_ant(u8 valid_antenna, u8 ant_type)
248{
249 return ((ant_type & valid_antenna) == ant_type);
250}
251
249/* 252/*
250 * removes the old data from the statistics. All data that is older than 253 * removes the old data from the statistics. All data that is older than
251 * TID_MAX_TIME_DIFF, will be deleted. 254 * TID_MAX_TIME_DIFF, will be deleted.
@@ -271,15 +274,21 @@ static void rs_tl_rm_old_stats(struct iwl4965_traffic_load *tl, u32 curr_time)
271 * increment traffic load value for tid and also remove 274 * increment traffic load value for tid and also remove
272 * any old values if passed the certain time period 275 * any old values if passed the certain time period
273 */ 276 */
274static void rs_tl_add_packet(struct iwl4965_lq_sta *lq_data, u8 tid) 277static u8 rs_tl_add_packet(struct iwl4965_lq_sta *lq_data,
278 struct ieee80211_hdr *hdr)
275{ 279{
276 u32 curr_time = jiffies_to_msecs(jiffies); 280 u32 curr_time = jiffies_to_msecs(jiffies);
277 u32 time_diff; 281 u32 time_diff;
278 s32 index; 282 s32 index;
279 struct iwl4965_traffic_load *tl = NULL; 283 struct iwl4965_traffic_load *tl = NULL;
284 __le16 fc = hdr->frame_control;
285 u8 tid;
280 286
281 if (tid >= TID_MAX_LOAD_COUNT) 287 if (ieee80211_is_data_qos(fc)) {
282 return; 288 u8 *qc = ieee80211_get_qos_ctl(hdr);
289 tid = qc[0] & 0xf;
290 } else
291 return MAX_TID_COUNT;
283 292
284 tl = &lq_data->load[tid]; 293 tl = &lq_data->load[tid];
285 294
@@ -292,7 +301,7 @@ static void rs_tl_add_packet(struct iwl4965_lq_sta *lq_data, u8 tid)
292 tl->queue_count = 1; 301 tl->queue_count = 1;
293 tl->head = 0; 302 tl->head = 0;
294 tl->packet_count[0] = 1; 303 tl->packet_count[0] = 1;
295 return; 304 return MAX_TID_COUNT;
296 } 305 }
297 306
298 time_diff = TIME_WRAP_AROUND(tl->time_stamp, curr_time); 307 time_diff = TIME_WRAP_AROUND(tl->time_stamp, curr_time);
@@ -309,6 +318,8 @@ static void rs_tl_add_packet(struct iwl4965_lq_sta *lq_data, u8 tid)
309 318
310 if ((index + 1) > tl->queue_count) 319 if ((index + 1) > tl->queue_count)
311 tl->queue_count = index + 1; 320 tl->queue_count = index + 1;
321
322 return tid;
312} 323}
313 324
314/* 325/*
@@ -349,9 +360,9 @@ static void rs_tl_turn_on_agg_for_tid(struct iwl_priv *priv,
349 unsigned long state; 360 unsigned long state;
350 DECLARE_MAC_BUF(mac); 361 DECLARE_MAC_BUF(mac);
351 362
352 spin_lock_bh(&sta->ampdu_mlme.ampdu_tx); 363 spin_lock_bh(&sta->lock);
353 state = sta->ampdu_mlme.tid_state_tx[tid]; 364 state = sta->ampdu_mlme.tid_state_tx[tid];
354 spin_unlock_bh(&sta->ampdu_mlme.ampdu_tx); 365 spin_unlock_bh(&sta->lock);
355 366
356 if (state == HT_AGG_STATE_IDLE && 367 if (state == HT_AGG_STATE_IDLE &&
357 rs_tl_get_load(lq_data, tid) > IWL_AGG_LOAD_THRESHOLD) { 368 rs_tl_get_load(lq_data, tid) > IWL_AGG_LOAD_THRESHOLD) {
@@ -372,7 +383,12 @@ static void rs_tl_turn_on_agg(struct iwl_priv *priv, u8 tid,
372 rs_tl_turn_on_agg_for_tid(priv, lq_data, tid, sta); 383 rs_tl_turn_on_agg_for_tid(priv, lq_data, tid, sta);
373} 384}
374 385
375#endif /* CONFIG_IWLWIFI_HT */ 386static inline int get_num_of_ant_from_rate(u32 rate_n_flags)
387{
388 return (!!(rate_n_flags & RATE_MCS_ANT_A_MSK) +
389 !!(rate_n_flags & RATE_MCS_ANT_B_MSK) +
390 !!(rate_n_flags & RATE_MCS_ANT_C_MSK));
391}
376 392
377/** 393/**
378 * rs_collect_tx_data - Update the success/failure sliding window 394 * rs_collect_tx_data - Update the success/failure sliding window
@@ -386,8 +402,7 @@ static int rs_collect_tx_data(struct iwl4965_rate_scale_data *windows,
386 int successes) 402 int successes)
387{ 403{
388 struct iwl4965_rate_scale_data *window = NULL; 404 struct iwl4965_rate_scale_data *window = NULL;
389 u64 mask; 405 static const u64 mask = (((u64)1) << (IWL_RATE_MAX_WINDOW - 1));
390 u8 win_size = IWL_RATE_MAX_WINDOW;
391 s32 fail_count; 406 s32 fail_count;
392 407
393 if (scale_index < 0 || scale_index >= IWL_RATE_COUNT) 408 if (scale_index < 0 || scale_index >= IWL_RATE_COUNT)
@@ -405,14 +420,14 @@ static int rs_collect_tx_data(struct iwl4965_rate_scale_data *windows,
405 * we keep these bitmaps!). 420 * we keep these bitmaps!).
406 */ 421 */
407 while (retries > 0) { 422 while (retries > 0) {
408 if (window->counter >= win_size) { 423 if (window->counter >= IWL_RATE_MAX_WINDOW) {
409 window->counter = win_size - 1; 424
410 mask = 1; 425 /* remove earliest */
411 mask = (mask << (win_size - 1)); 426 window->counter = IWL_RATE_MAX_WINDOW - 1;
427
412 if (window->data & mask) { 428 if (window->data & mask) {
413 window->data &= ~mask; 429 window->data &= ~mask;
414 window->success_counter = 430 window->success_counter--;
415 window->success_counter - 1;
416 } 431 }
417 } 432 }
418 433
@@ -422,10 +437,9 @@ static int rs_collect_tx_data(struct iwl4965_rate_scale_data *windows,
422 /* Shift bitmap by one frame (throw away oldest history), 437 /* Shift bitmap by one frame (throw away oldest history),
423 * OR in "1", and increment "success" if this 438 * OR in "1", and increment "success" if this
424 * frame was successful. */ 439 * frame was successful. */
425 mask = window->data; 440 window->data <<= 1;;
426 window->data = (mask << 1);
427 if (successes > 0) { 441 if (successes > 0) {
428 window->success_counter = window->success_counter + 1; 442 window->success_counter++;
429 window->data |= 0x1; 443 window->data |= 0x1;
430 successes--; 444 successes--;
431 } 445 }
@@ -458,168 +472,162 @@ static int rs_collect_tx_data(struct iwl4965_rate_scale_data *windows,
458/* 472/*
459 * Fill uCode API rate_n_flags field, based on "search" or "active" table. 473 * Fill uCode API rate_n_flags field, based on "search" or "active" table.
460 */ 474 */
461static void rs_mcs_from_tbl(struct iwl4965_rate *mcs_rate, 475/* FIXME:RS:remove this function and put the flags statically in the table */
462 struct iwl4965_scale_tbl_info *tbl, 476static u32 rate_n_flags_from_tbl(struct iwl4965_scale_tbl_info *tbl,
463 int index, u8 use_green) 477 int index, u8 use_green)
464{ 478{
479 u32 rate_n_flags = 0;
480
465 if (is_legacy(tbl->lq_type)) { 481 if (is_legacy(tbl->lq_type)) {
466 mcs_rate->rate_n_flags = iwl4965_rates[index].plcp; 482 rate_n_flags = iwl_rates[index].plcp;
467 if (index >= IWL_FIRST_CCK_RATE && index <= IWL_LAST_CCK_RATE) 483 if (index >= IWL_FIRST_CCK_RATE && index <= IWL_LAST_CCK_RATE)
468 mcs_rate->rate_n_flags |= RATE_MCS_CCK_MSK; 484 rate_n_flags |= RATE_MCS_CCK_MSK;
469 485
470 } else if (is_siso(tbl->lq_type)) { 486 } else if (is_Ht(tbl->lq_type)) {
471 if (index > IWL_LAST_OFDM_RATE) 487 if (index > IWL_LAST_OFDM_RATE) {
488 IWL_ERROR("invalid HT rate index %d\n", index);
472 index = IWL_LAST_OFDM_RATE; 489 index = IWL_LAST_OFDM_RATE;
473 mcs_rate->rate_n_flags = iwl4965_rates[index].plcp_siso | 490 }
474 RATE_MCS_HT_MSK; 491 rate_n_flags = RATE_MCS_HT_MSK;
475 } else {
476 if (index > IWL_LAST_OFDM_RATE)
477 index = IWL_LAST_OFDM_RATE;
478 mcs_rate->rate_n_flags = iwl4965_rates[index].plcp_mimo |
479 RATE_MCS_HT_MSK;
480 }
481
482 switch (tbl->antenna_type) {
483 case ANT_BOTH:
484 mcs_rate->rate_n_flags |= RATE_MCS_ANT_AB_MSK;
485 break;
486 case ANT_MAIN:
487 mcs_rate->rate_n_flags |= RATE_MCS_ANT_A_MSK;
488 break;
489 case ANT_AUX:
490 mcs_rate->rate_n_flags |= RATE_MCS_ANT_B_MSK;
491 break;
492 case ANT_NONE:
493 break;
494 }
495
496 if (is_legacy(tbl->lq_type))
497 return;
498 492
499 if (tbl->is_fat) { 493 if (is_siso(tbl->lq_type))
500 if (tbl->is_dup) 494 rate_n_flags |= iwl_rates[index].plcp_siso;
501 mcs_rate->rate_n_flags |= RATE_MCS_DUP_MSK; 495 else if (is_mimo2(tbl->lq_type))
496 rate_n_flags |= iwl_rates[index].plcp_mimo2;
502 else 497 else
503 mcs_rate->rate_n_flags |= RATE_MCS_FAT_MSK; 498 rate_n_flags |= iwl_rates[index].plcp_mimo3;
499 } else {
500 IWL_ERROR("Invalid tbl->lq_type %d\n", tbl->lq_type);
504 } 501 }
505 if (tbl->is_SGI)
506 mcs_rate->rate_n_flags |= RATE_MCS_SGI_MSK;
507 502
508 if (use_green) { 503 rate_n_flags |= ((tbl->ant_type << RATE_MCS_ANT_POS) &
509 mcs_rate->rate_n_flags |= RATE_MCS_GF_MSK; 504 RATE_MCS_ANT_ABC_MSK);
510 if (is_siso(tbl->lq_type)) 505
511 mcs_rate->rate_n_flags &= ~RATE_MCS_SGI_MSK; 506 if (is_Ht(tbl->lq_type)) {
507 if (tbl->is_fat) {
508 if (tbl->is_dup)
509 rate_n_flags |= RATE_MCS_DUP_MSK;
510 else
511 rate_n_flags |= RATE_MCS_FAT_MSK;
512 }
513 if (tbl->is_SGI)
514 rate_n_flags |= RATE_MCS_SGI_MSK;
515
516 if (use_green) {
517 rate_n_flags |= RATE_MCS_GF_MSK;
518 if (is_siso(tbl->lq_type) && tbl->is_SGI) {
519 rate_n_flags &= ~RATE_MCS_SGI_MSK;
520 IWL_ERROR("GF was set with SGI:SISO\n");
521 }
522 }
512 } 523 }
524 return rate_n_flags;
513} 525}
514 526
515/* 527/*
516 * Interpret uCode API's rate_n_flags format, 528 * Interpret uCode API's rate_n_flags format,
517 * fill "search" or "active" tx mode table. 529 * fill "search" or "active" tx mode table.
518 */ 530 */
519static int rs_get_tbl_info_from_mcs(const struct iwl4965_rate *mcs_rate, 531static int rs_get_tbl_info_from_mcs(const u32 rate_n_flags,
520 enum ieee80211_band band, 532 enum ieee80211_band band,
521 struct iwl4965_scale_tbl_info *tbl, 533 struct iwl4965_scale_tbl_info *tbl,
522 int *rate_idx) 534 int *rate_idx)
523{ 535{
524 int index; 536 u32 ant_msk = (rate_n_flags & RATE_MCS_ANT_ABC_MSK);
525 u32 ant_msk; 537 u8 num_of_ant = get_num_of_ant_from_rate(rate_n_flags);
538 u8 mcs;
526 539
527 index = iwl4965_hwrate_to_plcp_idx(mcs_rate->rate_n_flags); 540 *rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags);
528 541
529 if (index == IWL_RATE_INVALID) { 542 if (*rate_idx == IWL_RATE_INVALID) {
530 *rate_idx = -1; 543 *rate_idx = -1;
531 return -EINVAL; 544 return -EINVAL;
532 } 545 }
533 tbl->is_SGI = 0; /* default legacy setup */ 546 tbl->is_SGI = 0; /* default legacy setup */
534 tbl->is_fat = 0; 547 tbl->is_fat = 0;
535 tbl->is_dup = 0; 548 tbl->is_dup = 0;
536 tbl->antenna_type = ANT_BOTH; /* default MIMO setup */ 549 tbl->ant_type = (ant_msk >> RATE_MCS_ANT_POS);
550 tbl->lq_type = LQ_NONE;
537 551
538 /* legacy rate format */ 552 /* legacy rate format */
539 if (!(mcs_rate->rate_n_flags & RATE_MCS_HT_MSK)) { 553 if (!(rate_n_flags & RATE_MCS_HT_MSK)) {
540 ant_msk = (mcs_rate->rate_n_flags & RATE_MCS_ANT_AB_MSK); 554 if (num_of_ant == 1) {
541
542 if (ant_msk == RATE_MCS_ANT_AB_MSK)
543 tbl->lq_type = LQ_NONE;
544 else {
545
546 if (band == IEEE80211_BAND_5GHZ) 555 if (band == IEEE80211_BAND_5GHZ)
547 tbl->lq_type = LQ_A; 556 tbl->lq_type = LQ_A;
548 else 557 else
549 tbl->lq_type = LQ_G; 558 tbl->lq_type = LQ_G;
550
551 if (mcs_rate->rate_n_flags & RATE_MCS_ANT_A_MSK)
552 tbl->antenna_type = ANT_MAIN;
553 else
554 tbl->antenna_type = ANT_AUX;
555 }
556 *rate_idx = index;
557
558 /* HT rate format, SISO (might be 20 MHz legacy or 40 MHz fat width) */
559 } else if (iwl4965_rate_get_rate(mcs_rate->rate_n_flags)
560 <= IWL_RATE_SISO_60M_PLCP) {
561 tbl->lq_type = LQ_SISO;
562
563 ant_msk = (mcs_rate->rate_n_flags & RATE_MCS_ANT_AB_MSK);
564 if (ant_msk == RATE_MCS_ANT_AB_MSK)
565 tbl->lq_type = LQ_NONE;
566 else {
567 if (mcs_rate->rate_n_flags & RATE_MCS_ANT_A_MSK)
568 tbl->antenna_type = ANT_MAIN;
569 else
570 tbl->antenna_type = ANT_AUX;
571 } 559 }
572 if (mcs_rate->rate_n_flags & RATE_MCS_SGI_MSK) 560 /* HT rate format */
573 tbl->is_SGI = 1;
574
575 if ((mcs_rate->rate_n_flags & RATE_MCS_FAT_MSK) ||
576 (mcs_rate->rate_n_flags & RATE_MCS_DUP_MSK))
577 tbl->is_fat = 1;
578
579 if (mcs_rate->rate_n_flags & RATE_MCS_DUP_MSK)
580 tbl->is_dup = 1;
581
582 *rate_idx = index;
583
584 /* HT rate format, MIMO (might be 20 MHz legacy or 40 MHz fat width) */
585 } else { 561 } else {
586 tbl->lq_type = LQ_MIMO; 562 if (rate_n_flags & RATE_MCS_SGI_MSK)
587 if (mcs_rate->rate_n_flags & RATE_MCS_SGI_MSK)
588 tbl->is_SGI = 1; 563 tbl->is_SGI = 1;
589 564
590 if ((mcs_rate->rate_n_flags & RATE_MCS_FAT_MSK) || 565 if ((rate_n_flags & RATE_MCS_FAT_MSK) ||
591 (mcs_rate->rate_n_flags & RATE_MCS_DUP_MSK)) 566 (rate_n_flags & RATE_MCS_DUP_MSK))
592 tbl->is_fat = 1; 567 tbl->is_fat = 1;
593 568
594 if (mcs_rate->rate_n_flags & RATE_MCS_DUP_MSK) 569 if (rate_n_flags & RATE_MCS_DUP_MSK)
595 tbl->is_dup = 1; 570 tbl->is_dup = 1;
596 *rate_idx = index; 571
572 mcs = rs_extract_rate(rate_n_flags);
573
574 /* SISO */
575 if (mcs <= IWL_RATE_SISO_60M_PLCP) {
576 if (num_of_ant == 1)
577 tbl->lq_type = LQ_SISO; /*else NONE*/
578 /* MIMO2 */
579 } else if (mcs <= IWL_RATE_MIMO2_60M_PLCP) {
580 if (num_of_ant == 2)
581 tbl->lq_type = LQ_MIMO2;
582 /* MIMO3 */
583 } else {
584 if (num_of_ant == 3)
585 tbl->lq_type = LQ_MIMO3;
586 }
597 } 587 }
598 return 0; 588 return 0;
599} 589}
600 590
601static inline void rs_toggle_antenna(struct iwl4965_rate *new_rate, 591/* switch to another antenna/antennas and return 1 */
602 struct iwl4965_scale_tbl_info *tbl) 592/* if no other valid antenna found, return 0 */
593static int rs_toggle_antenna(u32 valid_ant, u32 *rate_n_flags,
594 struct iwl4965_scale_tbl_info *tbl)
603{ 595{
604 if (tbl->antenna_type == ANT_AUX) { 596 u8 new_ant_type;
605 tbl->antenna_type = ANT_MAIN; 597
606 new_rate->rate_n_flags &= ~RATE_MCS_ANT_B_MSK; 598 if (!tbl->ant_type || tbl->ant_type > ANT_ABC)
607 new_rate->rate_n_flags |= RATE_MCS_ANT_A_MSK; 599 return 0;
608 } else { 600
609 tbl->antenna_type = ANT_AUX; 601 if (!rs_is_valid_ant(valid_ant, tbl->ant_type))
610 new_rate->rate_n_flags &= ~RATE_MCS_ANT_A_MSK; 602 return 0;
611 new_rate->rate_n_flags |= RATE_MCS_ANT_B_MSK; 603
612 } 604 new_ant_type = ant_toggle_lookup[tbl->ant_type];
605
606 while ((new_ant_type != tbl->ant_type) &&
607 !rs_is_valid_ant(valid_ant, new_ant_type))
608 new_ant_type = ant_toggle_lookup[new_ant_type];
609
610 if (new_ant_type == tbl->ant_type)
611 return 0;
612
613 tbl->ant_type = new_ant_type;
614 *rate_n_flags &= ~RATE_MCS_ANT_ABC_MSK;
615 *rate_n_flags |= new_ant_type << RATE_MCS_ANT_POS;
616 return 1;
613} 617}
614 618
615static inline u8 rs_use_green(struct iwl_priv *priv, 619/* FIXME:RS: in 4965 we don't use greenfield at all */
616 struct ieee80211_conf *conf) 620/* FIXME:RS: don't use greenfield for now in TX */
621#if 0
622static inline u8 rs_use_green(struct iwl_priv *priv, struct ieee80211_conf *conf)
617{ 623{
618#ifdef CONFIG_IWL4965_HT
619 return ((conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) && 624 return ((conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) &&
620 priv->current_ht_config.is_green_field && 625 priv->current_ht_config.is_green_field &&
621 !priv->current_ht_config.non_GF_STA_present); 626 !priv->current_ht_config.non_GF_STA_present);
622#endif /* CONFIG_IWL4965_HT */ 627}
628#endif
629static inline u8 rs_use_green(struct iwl_priv *priv, struct ieee80211_conf *conf)
630{
623 return 0; 631 return 0;
624} 632}
625 633
@@ -630,27 +638,28 @@ static inline u8 rs_use_green(struct iwl_priv *priv,
630 * basic available rates. 638 * basic available rates.
631 * 639 *
632 */ 640 */
633static void rs_get_supported_rates(struct iwl4965_lq_sta *lq_sta, 641static u16 rs_get_supported_rates(struct iwl4965_lq_sta *lq_sta,
634 struct ieee80211_hdr *hdr, 642 struct ieee80211_hdr *hdr,
635 enum iwl4965_table_type rate_type, 643 enum iwl_table_type rate_type)
636 u16 *data_rate)
637{ 644{
638 if (is_legacy(rate_type)) 645 if (hdr && is_multicast_ether_addr(hdr->addr1) &&
639 *data_rate = lq_sta->active_rate; 646 lq_sta->active_rate_basic)
640 else { 647 return lq_sta->active_rate_basic;
648
649 if (is_legacy(rate_type)) {
650 return lq_sta->active_legacy_rate;
651 } else {
641 if (is_siso(rate_type)) 652 if (is_siso(rate_type))
642 *data_rate = lq_sta->active_siso_rate; 653 return lq_sta->active_siso_rate;
654 else if (is_mimo2(rate_type))
655 return lq_sta->active_mimo2_rate;
643 else 656 else
644 *data_rate = lq_sta->active_mimo_rate; 657 return lq_sta->active_mimo3_rate;
645 }
646
647 if (hdr && is_multicast_ether_addr(hdr->addr1) &&
648 lq_sta->active_rate_basic) {
649 *data_rate = lq_sta->active_rate_basic;
650 } 658 }
651} 659}
652 660
653static u16 rs_get_adjacent_rate(u8 index, u16 rate_mask, int rate_type) 661static u16 rs_get_adjacent_rate(struct iwl_priv *priv, u8 index, u16 rate_mask,
662 int rate_type)
654{ 663{
655 u8 high = IWL_RATE_INVALID; 664 u8 high = IWL_RATE_INVALID;
656 u8 low = IWL_RATE_INVALID; 665 u8 low = IWL_RATE_INVALID;
@@ -684,7 +693,7 @@ static u16 rs_get_adjacent_rate(u8 index, u16 rate_mask, int rate_type)
684 693
685 low = index; 694 low = index;
686 while (low != IWL_RATE_INVALID) { 695 while (low != IWL_RATE_INVALID) {
687 low = iwl4965_rates[low].prev_rs; 696 low = iwl_rates[low].prev_rs;
688 if (low == IWL_RATE_INVALID) 697 if (low == IWL_RATE_INVALID)
689 break; 698 break;
690 if (rate_mask & (1 << low)) 699 if (rate_mask & (1 << low))
@@ -694,7 +703,7 @@ static u16 rs_get_adjacent_rate(u8 index, u16 rate_mask, int rate_type)
694 703
695 high = index; 704 high = index;
696 while (high != IWL_RATE_INVALID) { 705 while (high != IWL_RATE_INVALID) {
697 high = iwl4965_rates[high].next_rs; 706 high = iwl_rates[high].next_rs;
698 if (high == IWL_RATE_INVALID) 707 if (high == IWL_RATE_INVALID)
699 break; 708 break;
700 if (rate_mask & (1 << high)) 709 if (rate_mask & (1 << high))
@@ -705,9 +714,9 @@ static u16 rs_get_adjacent_rate(u8 index, u16 rate_mask, int rate_type)
705 return (high << 8) | low; 714 return (high << 8) | low;
706} 715}
707 716
708static void rs_get_lower_rate(struct iwl4965_lq_sta *lq_sta, 717static u32 rs_get_lower_rate(struct iwl4965_lq_sta *lq_sta,
709 struct iwl4965_scale_tbl_info *tbl, u8 scale_index, 718 struct iwl4965_scale_tbl_info *tbl, u8 scale_index,
710 u8 ht_possible, struct iwl4965_rate *mcs_rate) 719 u8 ht_possible)
711{ 720{
712 s32 low; 721 s32 low;
713 u16 rate_mask; 722 u16 rate_mask;
@@ -726,15 +735,14 @@ static void rs_get_lower_rate(struct iwl4965_lq_sta *lq_sta,
726 else 735 else
727 tbl->lq_type = LQ_G; 736 tbl->lq_type = LQ_G;
728 737
729 if ((tbl->antenna_type == ANT_BOTH) || 738 if (num_of_ant(tbl->ant_type) > 1)
730 (tbl->antenna_type == ANT_NONE)) 739 tbl->ant_type = ANT_A;/*FIXME:RS*/
731 tbl->antenna_type = ANT_MAIN;
732 740
733 tbl->is_fat = 0; 741 tbl->is_fat = 0;
734 tbl->is_SGI = 0; 742 tbl->is_SGI = 0;
735 } 743 }
736 744
737 rs_get_supported_rates(lq_sta, NULL, tbl->lq_type, &rate_mask); 745 rate_mask = rs_get_supported_rates(lq_sta, NULL, tbl->lq_type);
738 746
739 /* Mask with station rate restriction */ 747 /* Mask with station rate restriction */
740 if (is_legacy(tbl->lq_type)) { 748 if (is_legacy(tbl->lq_type)) {
@@ -748,25 +756,26 @@ static void rs_get_lower_rate(struct iwl4965_lq_sta *lq_sta,
748 756
749 /* If we switched from HT to legacy, check current rate */ 757 /* If we switched from HT to legacy, check current rate */
750 if (switch_to_legacy && (rate_mask & (1 << scale_index))) { 758 if (switch_to_legacy && (rate_mask & (1 << scale_index))) {
751 rs_mcs_from_tbl(mcs_rate, tbl, scale_index, is_green); 759 low = scale_index;
752 return; 760 goto out;
753 } 761 }
754 762
755 high_low = rs_get_adjacent_rate(scale_index, rate_mask, tbl->lq_type); 763 high_low = rs_get_adjacent_rate(lq_sta->drv, scale_index, rate_mask,
764 tbl->lq_type);
756 low = high_low & 0xff; 765 low = high_low & 0xff;
757 766
758 if (low != IWL_RATE_INVALID) 767 if (low == IWL_RATE_INVALID)
759 rs_mcs_from_tbl(mcs_rate, tbl, low, is_green); 768 low = scale_index;
760 else 769
761 rs_mcs_from_tbl(mcs_rate, tbl, scale_index, is_green); 770out:
771 return rate_n_flags_from_tbl(tbl, low, is_green);
762} 772}
763 773
764/* 774/*
765 * mac80211 sends us Tx status 775 * mac80211 sends us Tx status
766 */ 776 */
767static void rs_tx_status(void *priv_rate, struct net_device *dev, 777static void rs_tx_status(void *priv_rate, struct net_device *dev,
768 struct sk_buff *skb, 778 struct sk_buff *skb)
769 struct ieee80211_tx_status *tx_resp)
770{ 779{
771 int status; 780 int status;
772 u8 retries; 781 u8 retries;
@@ -778,13 +787,14 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev,
778 struct iwl_priv *priv = (struct iwl_priv *)priv_rate; 787 struct iwl_priv *priv = (struct iwl_priv *)priv_rate;
779 struct ieee80211_local *local = wdev_priv(dev->ieee80211_ptr); 788 struct ieee80211_local *local = wdev_priv(dev->ieee80211_ptr);
780 struct ieee80211_hw *hw = local_to_hw(local); 789 struct ieee80211_hw *hw = local_to_hw(local);
790 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
781 struct iwl4965_rate_scale_data *window = NULL; 791 struct iwl4965_rate_scale_data *window = NULL;
782 struct iwl4965_rate_scale_data *search_win = NULL; 792 struct iwl4965_rate_scale_data *search_win = NULL;
783 struct iwl4965_rate tx_mcs; 793 u32 tx_rate;
784 struct iwl4965_scale_tbl_info tbl_type; 794 struct iwl4965_scale_tbl_info tbl_type;
785 struct iwl4965_scale_tbl_info *curr_tbl, *search_tbl; 795 struct iwl4965_scale_tbl_info *curr_tbl, *search_tbl;
786 u8 active_index = 0; 796 u8 active_index = 0;
787 u16 fc = le16_to_cpu(hdr->frame_control); 797 __le16 fc = hdr->frame_control;
788 s32 tpt = 0; 798 s32 tpt = 0;
789 799
790 IWL_DEBUG_RATE_LIMIT("get frame ack response, update rate scale window\n"); 800 IWL_DEBUG_RATE_LIMIT("get frame ack response, update rate scale window\n");
@@ -793,11 +803,11 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev,
793 return; 803 return;
794 804
795 /* This packet was aggregated but doesn't carry rate scale info */ 805 /* This packet was aggregated but doesn't carry rate scale info */
796 if ((tx_resp->control.flags & IEEE80211_TXCTL_AMPDU) && 806 if ((info->flags & IEEE80211_TX_CTL_AMPDU) &&
797 !(tx_resp->flags & IEEE80211_TX_STATUS_AMPDU)) 807 !(info->flags & IEEE80211_TX_STAT_AMPDU))
798 return; 808 return;
799 809
800 retries = tx_resp->retry_count; 810 retries = info->status.retry_count;
801 811
802 if (retries > 15) 812 if (retries > 15)
803 retries = 15; 813 retries = 15;
@@ -812,9 +822,6 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev,
812 822
813 lq_sta = (struct iwl4965_lq_sta *)sta->rate_ctrl_priv; 823 lq_sta = (struct iwl4965_lq_sta *)sta->rate_ctrl_priv;
814 824
815 if (!priv->lq_mngr.lq_ready)
816 goto out;
817
818 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && 825 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
819 !lq_sta->ibss_sta_added) 826 !lq_sta->ibss_sta_added)
820 goto out; 827 goto out;
@@ -822,15 +829,6 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev,
822 table = &lq_sta->lq; 829 table = &lq_sta->lq;
823 active_index = lq_sta->active_tbl; 830 active_index = lq_sta->active_tbl;
824 831
825 /* Get mac80211 antenna info */
826 lq_sta->antenna =
827 (lq_sta->valid_antenna & local->hw.conf.antenna_sel_tx);
828 if (!lq_sta->antenna)
829 lq_sta->antenna = lq_sta->valid_antenna;
830
831 /* Ignore mac80211 antenna info for now */
832 lq_sta->antenna = lq_sta->valid_antenna;
833
834 curr_tbl = &(lq_sta->lq_info[active_index]); 832 curr_tbl = &(lq_sta->lq_info[active_index]);
835 search_tbl = &(lq_sta->lq_info[(1 - active_index)]); 833 search_tbl = &(lq_sta->lq_info[(1 - active_index)]);
836 window = (struct iwl4965_rate_scale_data *) 834 window = (struct iwl4965_rate_scale_data *)
@@ -846,28 +844,26 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev,
846 * to check "search" mode, or a prior "search" mode after we've moved 844 * to check "search" mode, or a prior "search" mode after we've moved
847 * to a new "search" mode (which might become the new "active" mode). 845 * to a new "search" mode (which might become the new "active" mode).
848 */ 846 */
849 tx_mcs.rate_n_flags = le32_to_cpu(table->rs_table[0].rate_n_flags); 847 tx_rate = le32_to_cpu(table->rs_table[0].rate_n_flags);
850 rs_get_tbl_info_from_mcs(&tx_mcs, priv->band, &tbl_type, &rs_index); 848 rs_get_tbl_info_from_mcs(tx_rate, priv->band, &tbl_type, &rs_index);
851 if (priv->band == IEEE80211_BAND_5GHZ) 849 if (priv->band == IEEE80211_BAND_5GHZ)
852 rs_index -= IWL_FIRST_OFDM_RATE; 850 rs_index -= IWL_FIRST_OFDM_RATE;
853 851
854 if ((tx_resp->control.tx_rate == NULL) || 852 if ((info->tx_rate_idx < 0) ||
855 (tbl_type.is_SGI ^ 853 (tbl_type.is_SGI ^
856 !!(tx_resp->control.flags & IEEE80211_TXCTL_SHORT_GI)) || 854 !!(info->flags & IEEE80211_TX_CTL_SHORT_GI)) ||
857 (tbl_type.is_fat ^ 855 (tbl_type.is_fat ^
858 !!(tx_resp->control.flags & IEEE80211_TXCTL_40_MHZ_WIDTH)) || 856 !!(info->flags & IEEE80211_TX_CTL_40_MHZ_WIDTH)) ||
859 (tbl_type.is_dup ^ 857 (tbl_type.is_dup ^
860 !!(tx_resp->control.flags & IEEE80211_TXCTL_DUP_DATA)) || 858 !!(info->flags & IEEE80211_TX_CTL_DUP_DATA)) ||
861 (tbl_type.antenna_type ^ 859 (tbl_type.ant_type ^ info->antenna_sel_tx) ||
862 tx_resp->control.antenna_sel_tx) || 860 (!!(tx_rate & RATE_MCS_HT_MSK) ^
863 (!!(tx_mcs.rate_n_flags & RATE_MCS_HT_MSK) ^ 861 !!(info->flags & IEEE80211_TX_CTL_OFDM_HT)) ||
864 !!(tx_resp->control.flags & IEEE80211_TXCTL_OFDM_HT)) || 862 (!!(tx_rate & RATE_MCS_GF_MSK) ^
865 (!!(tx_mcs.rate_n_flags & RATE_MCS_GF_MSK) ^ 863 !!(info->flags & IEEE80211_TX_CTL_GREEN_FIELD)) ||
866 !!(tx_resp->control.flags & IEEE80211_TXCTL_GREEN_FIELD)) ||
867 (hw->wiphy->bands[priv->band]->bitrates[rs_index].bitrate != 864 (hw->wiphy->bands[priv->band]->bitrates[rs_index].bitrate !=
868 tx_resp->control.tx_rate->bitrate)) { 865 hw->wiphy->bands[info->band]->bitrates[info->tx_rate_idx].bitrate)) {
869 IWL_DEBUG_RATE("initial rate does not match 0x%x\n", 866 IWL_DEBUG_RATE("initial rate does not match 0x%x\n", tx_rate);
870 tx_mcs.rate_n_flags);
871 goto out; 867 goto out;
872 } 868 }
873 869
@@ -875,15 +871,14 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev,
875 while (retries) { 871 while (retries) {
876 /* Look up the rate and other info used for each tx attempt. 872 /* Look up the rate and other info used for each tx attempt.
877 * Each tx attempt steps one entry deeper in the rate table. */ 873 * Each tx attempt steps one entry deeper in the rate table. */
878 tx_mcs.rate_n_flags = 874 tx_rate = le32_to_cpu(table->rs_table[index].rate_n_flags);
879 le32_to_cpu(table->rs_table[index].rate_n_flags); 875 rs_get_tbl_info_from_mcs(tx_rate, priv->band,
880 rs_get_tbl_info_from_mcs(&tx_mcs, priv->band,
881 &tbl_type, &rs_index); 876 &tbl_type, &rs_index);
882 877
883 /* If type matches "search" table, 878 /* If type matches "search" table,
884 * add failure to "search" history */ 879 * add failure to "search" history */
885 if ((tbl_type.lq_type == search_tbl->lq_type) && 880 if ((tbl_type.lq_type == search_tbl->lq_type) &&
886 (tbl_type.antenna_type == search_tbl->antenna_type) && 881 (tbl_type.ant_type == search_tbl->ant_type) &&
887 (tbl_type.is_SGI == search_tbl->is_SGI)) { 882 (tbl_type.is_SGI == search_tbl->is_SGI)) {
888 if (search_tbl->expected_tpt) 883 if (search_tbl->expected_tpt)
889 tpt = search_tbl->expected_tpt[rs_index]; 884 tpt = search_tbl->expected_tpt[rs_index];
@@ -894,7 +889,7 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev,
894 /* Else if type matches "current/active" table, 889 /* Else if type matches "current/active" table,
895 * add failure to "current/active" history */ 890 * add failure to "current/active" history */
896 } else if ((tbl_type.lq_type == curr_tbl->lq_type) && 891 } else if ((tbl_type.lq_type == curr_tbl->lq_type) &&
897 (tbl_type.antenna_type == curr_tbl->antenna_type) && 892 (tbl_type.ant_type == curr_tbl->ant_type) &&
898 (tbl_type.is_SGI == curr_tbl->is_SGI)) { 893 (tbl_type.is_SGI == curr_tbl->is_SGI)) {
899 if (curr_tbl->expected_tpt) 894 if (curr_tbl->expected_tpt)
900 tpt = curr_tbl->expected_tpt[rs_index]; 895 tpt = curr_tbl->expected_tpt[rs_index];
@@ -917,44 +912,41 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev,
917 * if Tx was successful first try, use original rate, 912 * if Tx was successful first try, use original rate,
918 * else look up the rate that was, finally, successful. 913 * else look up the rate that was, finally, successful.
919 */ 914 */
920 tx_mcs.rate_n_flags = le32_to_cpu(table->rs_table[index].rate_n_flags); 915 tx_rate = le32_to_cpu(table->rs_table[index].rate_n_flags);
921 rs_get_tbl_info_from_mcs(&tx_mcs, priv->band, &tbl_type, &rs_index); 916 rs_get_tbl_info_from_mcs(tx_rate, priv->band, &tbl_type, &rs_index);
922 917
923 /* Update frame history window with "success" if Tx got ACKed ... */ 918 /* Update frame history window with "success" if Tx got ACKed ... */
924 if (tx_resp->flags & IEEE80211_TX_STATUS_ACK) 919 status = !!(info->flags & IEEE80211_TX_STAT_ACK);
925 status = 1;
926 else
927 status = 0;
928 920
929 /* If type matches "search" table, 921 /* If type matches "search" table,
930 * add final tx status to "search" history */ 922 * add final tx status to "search" history */
931 if ((tbl_type.lq_type == search_tbl->lq_type) && 923 if ((tbl_type.lq_type == search_tbl->lq_type) &&
932 (tbl_type.antenna_type == search_tbl->antenna_type) && 924 (tbl_type.ant_type == search_tbl->ant_type) &&
933 (tbl_type.is_SGI == search_tbl->is_SGI)) { 925 (tbl_type.is_SGI == search_tbl->is_SGI)) {
934 if (search_tbl->expected_tpt) 926 if (search_tbl->expected_tpt)
935 tpt = search_tbl->expected_tpt[rs_index]; 927 tpt = search_tbl->expected_tpt[rs_index];
936 else 928 else
937 tpt = 0; 929 tpt = 0;
938 if (tx_resp->control.flags & IEEE80211_TXCTL_AMPDU) 930 if (info->flags & IEEE80211_TX_CTL_AMPDU)
939 rs_collect_tx_data(search_win, rs_index, tpt, 931 rs_collect_tx_data(search_win, rs_index, tpt,
940 tx_resp->ampdu_ack_len, 932 info->status.ampdu_ack_len,
941 tx_resp->ampdu_ack_map); 933 info->status.ampdu_ack_map);
942 else 934 else
943 rs_collect_tx_data(search_win, rs_index, tpt, 935 rs_collect_tx_data(search_win, rs_index, tpt,
944 1, status); 936 1, status);
945 /* Else if type matches "current/active" table, 937 /* Else if type matches "current/active" table,
946 * add final tx status to "current/active" history */ 938 * add final tx status to "current/active" history */
947 } else if ((tbl_type.lq_type == curr_tbl->lq_type) && 939 } else if ((tbl_type.lq_type == curr_tbl->lq_type) &&
948 (tbl_type.antenna_type == curr_tbl->antenna_type) && 940 (tbl_type.ant_type == curr_tbl->ant_type) &&
949 (tbl_type.is_SGI == curr_tbl->is_SGI)) { 941 (tbl_type.is_SGI == curr_tbl->is_SGI)) {
950 if (curr_tbl->expected_tpt) 942 if (curr_tbl->expected_tpt)
951 tpt = curr_tbl->expected_tpt[rs_index]; 943 tpt = curr_tbl->expected_tpt[rs_index];
952 else 944 else
953 tpt = 0; 945 tpt = 0;
954 if (tx_resp->control.flags & IEEE80211_TXCTL_AMPDU) 946 if (info->flags & IEEE80211_TX_CTL_AMPDU)
955 rs_collect_tx_data(window, rs_index, tpt, 947 rs_collect_tx_data(window, rs_index, tpt,
956 tx_resp->ampdu_ack_len, 948 info->status.ampdu_ack_len,
957 tx_resp->ampdu_ack_map); 949 info->status.ampdu_ack_map);
958 else 950 else
959 rs_collect_tx_data(window, rs_index, tpt, 951 rs_collect_tx_data(window, rs_index, tpt,
960 1, status); 952 1, status);
@@ -963,10 +955,10 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev,
963 /* If not searching for new mode, increment success/failed counter 955 /* If not searching for new mode, increment success/failed counter
964 * ... these help determine when to start searching again */ 956 * ... these help determine when to start searching again */
965 if (lq_sta->stay_in_tbl) { 957 if (lq_sta->stay_in_tbl) {
966 if (tx_resp->control.flags & IEEE80211_TXCTL_AMPDU) { 958 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
967 lq_sta->total_success += tx_resp->ampdu_ack_map; 959 lq_sta->total_success += info->status.ampdu_ack_map;
968 lq_sta->total_failed += 960 lq_sta->total_failed +=
969 (tx_resp->ampdu_ack_len - tx_resp->ampdu_ack_map); 961 (info->status.ampdu_ack_len - info->status.ampdu_ack_map);
970 } else { 962 } else {
971 if (status) 963 if (status)
972 lq_sta->total_success++; 964 lq_sta->total_success++;
@@ -982,30 +974,6 @@ out:
982 return; 974 return;
983} 975}
984 976
985static u8 rs_is_ant_connected(u8 valid_antenna,
986 enum iwl4965_antenna_type antenna_type)
987{
988 if (antenna_type == ANT_AUX)
989 return ((valid_antenna & 0x2) ? 1:0);
990 else if (antenna_type == ANT_MAIN)
991 return ((valid_antenna & 0x1) ? 1:0);
992 else if (antenna_type == ANT_BOTH)
993 return ((valid_antenna & 0x3) == 0x3);
994
995 return 1;
996}
997
998static u8 rs_is_other_ant_connected(u8 valid_antenna,
999 enum iwl4965_antenna_type antenna_type)
1000{
1001 if (antenna_type == ANT_AUX)
1002 return rs_is_ant_connected(valid_antenna, ANT_MAIN);
1003 else
1004 return rs_is_ant_connected(valid_antenna, ANT_AUX);
1005
1006 return 0;
1007}
1008
1009/* 977/*
1010 * Begin a period of staying with a selected modulation mode. 978 * Begin a period of staying with a selected modulation mode.
1011 * Set "stay_in_tbl" flag to prevent any mode switches. 979 * Set "stay_in_tbl" flag to prevent any mode switches.
@@ -1014,10 +982,10 @@ static u8 rs_is_other_ant_connected(u8 valid_antenna,
1014 * These control how long we stay using same modulation mode before 982 * These control how long we stay using same modulation mode before
1015 * searching for a new mode. 983 * searching for a new mode.
1016 */ 984 */
1017static void rs_set_stay_in_table(u8 is_legacy, 985static void rs_set_stay_in_table(struct iwl_priv *priv, u8 is_legacy,
1018 struct iwl4965_lq_sta *lq_sta) 986 struct iwl4965_lq_sta *lq_sta)
1019{ 987{
1020 IWL_DEBUG_HT("we are staying in the same table\n"); 988 IWL_DEBUG_RATE("we are staying in the same table\n");
1021 lq_sta->stay_in_tbl = 1; /* only place this gets set */ 989 lq_sta->stay_in_tbl = 1; /* only place this gets set */
1022 if (is_legacy) { 990 if (is_legacy) {
1023 lq_sta->table_count_limit = IWL_LEGACY_TABLE_COUNT; 991 lq_sta->table_count_limit = IWL_LEGACY_TABLE_COUNT;
@@ -1036,7 +1004,7 @@ static void rs_set_stay_in_table(u8 is_legacy,
1036/* 1004/*
1037 * Find correct throughput table for given mode of modulation 1005 * Find correct throughput table for given mode of modulation
1038 */ 1006 */
1039static void rs_get_expected_tpt_table(struct iwl4965_lq_sta *lq_sta, 1007static void rs_set_expected_tpt_table(struct iwl4965_lq_sta *lq_sta,
1040 struct iwl4965_scale_tbl_info *tbl) 1008 struct iwl4965_scale_tbl_info *tbl)
1041{ 1009{
1042 if (is_legacy(tbl->lq_type)) { 1010 if (is_legacy(tbl->lq_type)) {
@@ -1055,7 +1023,7 @@ static void rs_get_expected_tpt_table(struct iwl4965_lq_sta *lq_sta,
1055 else 1023 else
1056 tbl->expected_tpt = expected_tpt_siso20MHz; 1024 tbl->expected_tpt = expected_tpt_siso20MHz;
1057 1025
1058 } else if (is_mimo(tbl->lq_type)) { 1026 } else if (is_mimo(tbl->lq_type)) { /* FIXME:need to separate mimo2/3 */
1059 if (tbl->is_fat && !lq_sta->is_dup) 1027 if (tbl->is_fat && !lq_sta->is_dup)
1060 if (tbl->is_SGI) 1028 if (tbl->is_SGI)
1061 tbl->expected_tpt = expected_tpt_mimo40MHzSGI; 1029 tbl->expected_tpt = expected_tpt_mimo40MHzSGI;
@@ -1069,7 +1037,6 @@ static void rs_get_expected_tpt_table(struct iwl4965_lq_sta *lq_sta,
1069 tbl->expected_tpt = expected_tpt_G; 1037 tbl->expected_tpt = expected_tpt_G;
1070} 1038}
1071 1039
1072#ifdef CONFIG_IWL4965_HT
1073/* 1040/*
1074 * Find starting rate for new "search" high-throughput mode of modulation. 1041 * Find starting rate for new "search" high-throughput mode of modulation.
1075 * Goal is to find lowest expected rate (under perfect conditions) that is 1042 * Goal is to find lowest expected rate (under perfect conditions) that is
@@ -1085,7 +1052,7 @@ static void rs_get_expected_tpt_table(struct iwl4965_lq_sta *lq_sta,
1085static s32 rs_get_best_rate(struct iwl_priv *priv, 1052static s32 rs_get_best_rate(struct iwl_priv *priv,
1086 struct iwl4965_lq_sta *lq_sta, 1053 struct iwl4965_lq_sta *lq_sta,
1087 struct iwl4965_scale_tbl_info *tbl, /* "search" */ 1054 struct iwl4965_scale_tbl_info *tbl, /* "search" */
1088 u16 rate_mask, s8 index, s8 rate) 1055 u16 rate_mask, s8 index)
1089{ 1056{
1090 /* "active" values */ 1057 /* "active" values */
1091 struct iwl4965_scale_tbl_info *active_tbl = 1058 struct iwl4965_scale_tbl_info *active_tbl =
@@ -1098,11 +1065,13 @@ static s32 rs_get_best_rate(struct iwl_priv *priv,
1098 1065
1099 s32 new_rate, high, low, start_hi; 1066 s32 new_rate, high, low, start_hi;
1100 u16 high_low; 1067 u16 high_low;
1068 s8 rate = index;
1101 1069
1102 new_rate = high = low = start_hi = IWL_RATE_INVALID; 1070 new_rate = high = low = start_hi = IWL_RATE_INVALID;
1103 1071
1104 for (; ;) { 1072 for (; ;) {
1105 high_low = rs_get_adjacent_rate(rate, rate_mask, tbl->lq_type); 1073 high_low = rs_get_adjacent_rate(priv, rate, rate_mask,
1074 tbl->lq_type);
1106 1075
1107 low = high_low & 0xff; 1076 low = high_low & 0xff;
1108 high = (high_low >> 8) & 0xff; 1077 high = (high_low >> 8) & 0xff;
@@ -1169,23 +1138,16 @@ static s32 rs_get_best_rate(struct iwl_priv *priv,
1169 1138
1170 return new_rate; 1139 return new_rate;
1171} 1140}
1172#endif /* CONFIG_IWL4965_HT */
1173
1174static inline u8 rs_is_both_ant_supp(u8 valid_antenna)
1175{
1176 return (rs_is_ant_connected(valid_antenna, ANT_BOTH));
1177}
1178 1141
1179/* 1142/*
1180 * Set up search table for MIMO 1143 * Set up search table for MIMO
1181 */ 1144 */
1182static int rs_switch_to_mimo(struct iwl_priv *priv, 1145static int rs_switch_to_mimo2(struct iwl_priv *priv,
1183 struct iwl4965_lq_sta *lq_sta, 1146 struct iwl4965_lq_sta *lq_sta,
1184 struct ieee80211_conf *conf, 1147 struct ieee80211_conf *conf,
1185 struct sta_info *sta, 1148 struct sta_info *sta,
1186 struct iwl4965_scale_tbl_info *tbl, int index) 1149 struct iwl4965_scale_tbl_info *tbl, int index)
1187{ 1150{
1188#ifdef CONFIG_IWL4965_HT
1189 u16 rate_mask; 1151 u16 rate_mask;
1190 s32 rate; 1152 s32 rate;
1191 s8 is_green = lq_sta->is_green; 1153 s8 is_green = lq_sta->is_green;
@@ -1194,26 +1156,27 @@ static int rs_switch_to_mimo(struct iwl_priv *priv,
1194 !sta->ht_info.ht_supported) 1156 !sta->ht_info.ht_supported)
1195 return -1; 1157 return -1;
1196 1158
1197 IWL_DEBUG_HT("LQ: try to switch to MIMO\n");
1198 tbl->lq_type = LQ_MIMO;
1199 rs_get_supported_rates(lq_sta, NULL, tbl->lq_type,
1200 &rate_mask);
1201
1202 if (priv->current_ht_config.tx_mimo_ps_mode == IWL_MIMO_PS_STATIC) 1159 if (priv->current_ht_config.tx_mimo_ps_mode == IWL_MIMO_PS_STATIC)
1203 return -1; 1160 return -1;
1204 1161
1205 /* Need both Tx chains/antennas to support MIMO */ 1162 /* Need both Tx chains/antennas to support MIMO */
1206 if (!rs_is_both_ant_supp(lq_sta->antenna)) 1163 if (priv->hw_params.tx_chains_num < 2)
1207 return -1; 1164 return -1;
1208 1165
1166 IWL_DEBUG_RATE("LQ: try to switch to MIMO2\n");
1167
1168 tbl->lq_type = LQ_MIMO2;
1209 tbl->is_dup = lq_sta->is_dup; 1169 tbl->is_dup = lq_sta->is_dup;
1210 tbl->action = 0; 1170 tbl->action = 0;
1171 rate_mask = lq_sta->active_mimo2_rate;
1172
1211 if (priv->current_ht_config.supported_chan_width 1173 if (priv->current_ht_config.supported_chan_width
1212 == IWL_CHANNEL_WIDTH_40MHZ) 1174 == IWL_CHANNEL_WIDTH_40MHZ)
1213 tbl->is_fat = 1; 1175 tbl->is_fat = 1;
1214 else 1176 else
1215 tbl->is_fat = 0; 1177 tbl->is_fat = 0;
1216 1178
1179 /* FIXME: - don't toggle SGI here
1217 if (tbl->is_fat) { 1180 if (tbl->is_fat) {
1218 if (priv->current_ht_config.sgf & HT_SHORT_GI_40MHZ_ONLY) 1181 if (priv->current_ht_config.sgf & HT_SHORT_GI_40MHZ_ONLY)
1219 tbl->is_SGI = 1; 1182 tbl->is_SGI = 1;
@@ -1223,22 +1186,24 @@ static int rs_switch_to_mimo(struct iwl_priv *priv,
1223 tbl->is_SGI = 1; 1186 tbl->is_SGI = 1;
1224 else 1187 else
1225 tbl->is_SGI = 0; 1188 tbl->is_SGI = 0;
1189 */
1190
1191 rs_set_expected_tpt_table(lq_sta, tbl);
1226 1192
1227 rs_get_expected_tpt_table(lq_sta, tbl); 1193 rate = rs_get_best_rate(priv, lq_sta, tbl, rate_mask, index);
1228 1194
1229 rate = rs_get_best_rate(priv, lq_sta, tbl, rate_mask, index, index); 1195 IWL_DEBUG_RATE("LQ: MIMO2 best rate %d mask %X\n", rate, rate_mask);
1230 1196
1231 IWL_DEBUG_HT("LQ: MIMO best rate %d mask %X\n", rate, rate_mask); 1197 if ((rate == IWL_RATE_INVALID) || !((1 << rate) & rate_mask)) {
1232 if ((rate == IWL_RATE_INVALID) || !((1 << rate) & rate_mask)) 1198 IWL_DEBUG_RATE("Can't switch with index %d rate mask %x\n",
1199 rate, rate_mask);
1233 return -1; 1200 return -1;
1234 rs_mcs_from_tbl(&tbl->current_rate, tbl, rate, is_green); 1201 }
1202 tbl->current_rate = rate_n_flags_from_tbl(tbl, rate, is_green);
1235 1203
1236 IWL_DEBUG_HT("LQ: Switch to new mcs %X index is green %X\n", 1204 IWL_DEBUG_RATE("LQ: Switch to new mcs %X index is green %X\n",
1237 tbl->current_rate.rate_n_flags, is_green); 1205 tbl->current_rate, is_green);
1238 return 0; 1206 return 0;
1239#else
1240 return -1;
1241#endif /*CONFIG_IWL4965_HT */
1242} 1207}
1243 1208
1244/* 1209/*
@@ -1250,21 +1215,20 @@ static int rs_switch_to_siso(struct iwl_priv *priv,
1250 struct sta_info *sta, 1215 struct sta_info *sta,
1251 struct iwl4965_scale_tbl_info *tbl, int index) 1216 struct iwl4965_scale_tbl_info *tbl, int index)
1252{ 1217{
1253#ifdef CONFIG_IWL4965_HT
1254 u16 rate_mask; 1218 u16 rate_mask;
1255 u8 is_green = lq_sta->is_green; 1219 u8 is_green = lq_sta->is_green;
1256 s32 rate; 1220 s32 rate;
1257 1221
1258 IWL_DEBUG_HT("LQ: try to switch to SISO\n");
1259 if (!(conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) || 1222 if (!(conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) ||
1260 !sta->ht_info.ht_supported) 1223 !sta->ht_info.ht_supported)
1261 return -1; 1224 return -1;
1262 1225
1226 IWL_DEBUG_RATE("LQ: try to switch to SISO\n");
1227
1263 tbl->is_dup = lq_sta->is_dup; 1228 tbl->is_dup = lq_sta->is_dup;
1264 tbl->lq_type = LQ_SISO; 1229 tbl->lq_type = LQ_SISO;
1265 tbl->action = 0; 1230 tbl->action = 0;
1266 rs_get_supported_rates(lq_sta, NULL, tbl->lq_type, 1231 rate_mask = lq_sta->active_siso_rate;
1267 &rate_mask);
1268 1232
1269 if (priv->current_ht_config.supported_chan_width 1233 if (priv->current_ht_config.supported_chan_width
1270 == IWL_CHANNEL_WIDTH_40MHZ) 1234 == IWL_CHANNEL_WIDTH_40MHZ)
@@ -1272,6 +1236,7 @@ static int rs_switch_to_siso(struct iwl_priv *priv,
1272 else 1236 else
1273 tbl->is_fat = 0; 1237 tbl->is_fat = 0;
1274 1238
1239 /* FIXME: - don't toggle SGI here
1275 if (tbl->is_fat) { 1240 if (tbl->is_fat) {
1276 if (priv->current_ht_config.sgf & HT_SHORT_GI_40MHZ_ONLY) 1241 if (priv->current_ht_config.sgf & HT_SHORT_GI_40MHZ_ONLY)
1277 tbl->is_SGI = 1; 1242 tbl->is_SGI = 1;
@@ -1281,27 +1246,24 @@ static int rs_switch_to_siso(struct iwl_priv *priv,
1281 tbl->is_SGI = 1; 1246 tbl->is_SGI = 1;
1282 else 1247 else
1283 tbl->is_SGI = 0; 1248 tbl->is_SGI = 0;
1249 */
1284 1250
1285 if (is_green) 1251 if (is_green)
1286 tbl->is_SGI = 0; 1252 tbl->is_SGI = 0; /*11n spec: no SGI in SISO+Greenfield*/
1287 1253
1288 rs_get_expected_tpt_table(lq_sta, tbl); 1254 rs_set_expected_tpt_table(lq_sta, tbl);
1289 rate = rs_get_best_rate(priv, lq_sta, tbl, rate_mask, index, index); 1255 rate = rs_get_best_rate(priv, lq_sta, tbl, rate_mask, index);
1290 1256
1291 IWL_DEBUG_HT("LQ: get best rate %d mask %X\n", rate, rate_mask); 1257 IWL_DEBUG_RATE("LQ: get best rate %d mask %X\n", rate, rate_mask);
1292 if ((rate == IWL_RATE_INVALID) || !((1 << rate) & rate_mask)) { 1258 if ((rate == IWL_RATE_INVALID) || !((1 << rate) & rate_mask)) {
1293 IWL_DEBUG_HT("can not switch with index %d rate mask %x\n", 1259 IWL_DEBUG_RATE("can not switch with index %d rate mask %x\n",
1294 rate, rate_mask); 1260 rate, rate_mask);
1295 return -1; 1261 return -1;
1296 } 1262 }
1297 rs_mcs_from_tbl(&tbl->current_rate, tbl, rate, is_green); 1263 tbl->current_rate = rate_n_flags_from_tbl(tbl, rate, is_green);
1298 IWL_DEBUG_HT("LQ: Switch to new mcs %X index is green %X\n", 1264 IWL_DEBUG_RATE("LQ: Switch to new mcs %X index is green %X\n",
1299 tbl->current_rate.rate_n_flags, is_green); 1265 tbl->current_rate, is_green);
1300 return 0; 1266 return 0;
1301#else
1302 return -1;
1303
1304#endif /*CONFIG_IWL4965_HT */
1305} 1267}
1306 1268
1307/* 1269/*
@@ -1313,7 +1275,6 @@ static int rs_move_legacy_other(struct iwl_priv *priv,
1313 struct sta_info *sta, 1275 struct sta_info *sta,
1314 int index) 1276 int index)
1315{ 1277{
1316 int ret = 0;
1317 struct iwl4965_scale_tbl_info *tbl = 1278 struct iwl4965_scale_tbl_info *tbl =
1318 &(lq_sta->lq_info[lq_sta->active_tbl]); 1279 &(lq_sta->lq_info[lq_sta->active_tbl]);
1319 struct iwl4965_scale_tbl_info *search_tbl = 1280 struct iwl4965_scale_tbl_info *search_tbl =
@@ -1322,41 +1283,35 @@ static int rs_move_legacy_other(struct iwl_priv *priv,
1322 u32 sz = (sizeof(struct iwl4965_scale_tbl_info) - 1283 u32 sz = (sizeof(struct iwl4965_scale_tbl_info) -
1323 (sizeof(struct iwl4965_rate_scale_data) * IWL_RATE_COUNT)); 1284 (sizeof(struct iwl4965_rate_scale_data) * IWL_RATE_COUNT));
1324 u8 start_action = tbl->action; 1285 u8 start_action = tbl->action;
1286 u8 valid_tx_ant = priv->hw_params.valid_tx_ant;
1287 int ret = 0;
1325 1288
1326 for (; ;) { 1289 for (; ;) {
1327 switch (tbl->action) { 1290 switch (tbl->action) {
1328 case IWL_LEGACY_SWITCH_ANTENNA: 1291 case IWL_LEGACY_SWITCH_ANTENNA:
1329 IWL_DEBUG_HT("LQ Legacy switch Antenna\n"); 1292 IWL_DEBUG_RATE("LQ: Legacy toggle Antenna\n");
1330 1293
1331 search_tbl->lq_type = LQ_NONE;
1332 lq_sta->action_counter++; 1294 lq_sta->action_counter++;
1333 1295
1334 /* Don't change antenna if success has been great */ 1296 /* Don't change antenna if success has been great */
1335 if (window->success_ratio >= IWL_RS_GOOD_RATIO) 1297 if (window->success_ratio >= IWL_RS_GOOD_RATIO)
1336 break; 1298 break;
1337 1299
1338 /* Don't change antenna if other one is not connected */
1339 if (!rs_is_other_ant_connected(lq_sta->antenna,
1340 tbl->antenna_type))
1341 break;
1342
1343 /* Set up search table to try other antenna */ 1300 /* Set up search table to try other antenna */
1344 memcpy(search_tbl, tbl, sz); 1301 memcpy(search_tbl, tbl, sz);
1345 1302
1346 rs_toggle_antenna(&(search_tbl->current_rate), 1303 if (rs_toggle_antenna(valid_tx_ant,
1347 search_tbl); 1304 &search_tbl->current_rate, search_tbl)) {
1348 rs_get_expected_tpt_table(lq_sta, search_tbl); 1305 lq_sta->search_better_tbl = 1;
1349 lq_sta->search_better_tbl = 1; 1306 goto out;
1350 goto out; 1307 }
1351 1308 break;
1352 case IWL_LEGACY_SWITCH_SISO: 1309 case IWL_LEGACY_SWITCH_SISO:
1353 IWL_DEBUG_HT("LQ: Legacy switch to SISO\n"); 1310 IWL_DEBUG_RATE("LQ: Legacy switch to SISO\n");
1354 1311
1355 /* Set up search table to try SISO */ 1312 /* Set up search table to try SISO */
1356 memcpy(search_tbl, tbl, sz); 1313 memcpy(search_tbl, tbl, sz);
1357 search_tbl->lq_type = LQ_SISO;
1358 search_tbl->is_SGI = 0; 1314 search_tbl->is_SGI = 0;
1359 search_tbl->is_fat = 0;
1360 ret = rs_switch_to_siso(priv, lq_sta, conf, sta, 1315 ret = rs_switch_to_siso(priv, lq_sta, conf, sta,
1361 search_tbl, index); 1316 search_tbl, index);
1362 if (!ret) { 1317 if (!ret) {
@@ -1366,16 +1321,15 @@ static int rs_move_legacy_other(struct iwl_priv *priv,
1366 } 1321 }
1367 1322
1368 break; 1323 break;
1369 case IWL_LEGACY_SWITCH_MIMO: 1324 case IWL_LEGACY_SWITCH_MIMO2:
1370 IWL_DEBUG_HT("LQ: Legacy switch MIMO\n"); 1325 IWL_DEBUG_RATE("LQ: Legacy switch to MIMO2\n");
1371 1326
1372 /* Set up search table to try MIMO */ 1327 /* Set up search table to try MIMO */
1373 memcpy(search_tbl, tbl, sz); 1328 memcpy(search_tbl, tbl, sz);
1374 search_tbl->lq_type = LQ_MIMO;
1375 search_tbl->is_SGI = 0; 1329 search_tbl->is_SGI = 0;
1376 search_tbl->is_fat = 0; 1330 search_tbl->ant_type = ANT_AB;/*FIXME:RS*/
1377 search_tbl->antenna_type = ANT_BOTH; 1331 /*FIXME:RS:need to check ant validity*/
1378 ret = rs_switch_to_mimo(priv, lq_sta, conf, sta, 1332 ret = rs_switch_to_mimo2(priv, lq_sta, conf, sta,
1379 search_tbl, index); 1333 search_tbl, index);
1380 if (!ret) { 1334 if (!ret) {
1381 lq_sta->search_better_tbl = 1; 1335 lq_sta->search_better_tbl = 1;
@@ -1385,7 +1339,7 @@ static int rs_move_legacy_other(struct iwl_priv *priv,
1385 break; 1339 break;
1386 } 1340 }
1387 tbl->action++; 1341 tbl->action++;
1388 if (tbl->action > IWL_LEGACY_SWITCH_MIMO) 1342 if (tbl->action > IWL_LEGACY_SWITCH_MIMO2)
1389 tbl->action = IWL_LEGACY_SWITCH_ANTENNA; 1343 tbl->action = IWL_LEGACY_SWITCH_ANTENNA;
1390 1344
1391 if (tbl->action == start_action) 1345 if (tbl->action == start_action)
@@ -1396,7 +1350,7 @@ static int rs_move_legacy_other(struct iwl_priv *priv,
1396 1350
1397 out: 1351 out:
1398 tbl->action++; 1352 tbl->action++;
1399 if (tbl->action > IWL_LEGACY_SWITCH_MIMO) 1353 if (tbl->action > IWL_LEGACY_SWITCH_MIMO2)
1400 tbl->action = IWL_LEGACY_SWITCH_ANTENNA; 1354 tbl->action = IWL_LEGACY_SWITCH_ANTENNA;
1401 return 0; 1355 return 0;
1402 1356
@@ -1411,7 +1365,6 @@ static int rs_move_siso_to_other(struct iwl_priv *priv,
1411 struct sta_info *sta, 1365 struct sta_info *sta,
1412 int index) 1366 int index)
1413{ 1367{
1414 int ret;
1415 u8 is_green = lq_sta->is_green; 1368 u8 is_green = lq_sta->is_green;
1416 struct iwl4965_scale_tbl_info *tbl = 1369 struct iwl4965_scale_tbl_info *tbl =
1417 &(lq_sta->lq_info[lq_sta->active_tbl]); 1370 &(lq_sta->lq_info[lq_sta->active_tbl]);
@@ -1421,35 +1374,30 @@ static int rs_move_siso_to_other(struct iwl_priv *priv,
1421 u32 sz = (sizeof(struct iwl4965_scale_tbl_info) - 1374 u32 sz = (sizeof(struct iwl4965_scale_tbl_info) -
1422 (sizeof(struct iwl4965_rate_scale_data) * IWL_RATE_COUNT)); 1375 (sizeof(struct iwl4965_rate_scale_data) * IWL_RATE_COUNT));
1423 u8 start_action = tbl->action; 1376 u8 start_action = tbl->action;
1377 u8 valid_tx_ant = priv->hw_params.valid_tx_ant;
1378 int ret;
1424 1379
1425 for (;;) { 1380 for (;;) {
1426 lq_sta->action_counter++; 1381 lq_sta->action_counter++;
1427 switch (tbl->action) { 1382 switch (tbl->action) {
1428 case IWL_SISO_SWITCH_ANTENNA: 1383 case IWL_SISO_SWITCH_ANTENNA:
1429 IWL_DEBUG_HT("LQ: SISO SWITCH ANTENNA SISO\n"); 1384 IWL_DEBUG_RATE("LQ: SISO toggle Antenna\n");
1430 search_tbl->lq_type = LQ_NONE;
1431 if (window->success_ratio >= IWL_RS_GOOD_RATIO) 1385 if (window->success_ratio >= IWL_RS_GOOD_RATIO)
1432 break; 1386 break;
1433 if (!rs_is_other_ant_connected(lq_sta->antenna,
1434 tbl->antenna_type))
1435 break;
1436 1387
1437 memcpy(search_tbl, tbl, sz); 1388 memcpy(search_tbl, tbl, sz);
1438 search_tbl->action = IWL_SISO_SWITCH_MIMO; 1389 if (rs_toggle_antenna(valid_tx_ant,
1439 rs_toggle_antenna(&(search_tbl->current_rate), 1390 &search_tbl->current_rate, search_tbl)) {
1440 search_tbl); 1391 lq_sta->search_better_tbl = 1;
1441 lq_sta->search_better_tbl = 1; 1392 goto out;
1442 1393 }
1443 goto out; 1394 break;
1444 1395 case IWL_SISO_SWITCH_MIMO2:
1445 case IWL_SISO_SWITCH_MIMO: 1396 IWL_DEBUG_RATE("LQ: SISO switch to MIMO2\n");
1446 IWL_DEBUG_HT("LQ: SISO SWITCH TO MIMO FROM SISO\n");
1447 memcpy(search_tbl, tbl, sz); 1397 memcpy(search_tbl, tbl, sz);
1448 search_tbl->lq_type = LQ_MIMO;
1449 search_tbl->is_SGI = 0; 1398 search_tbl->is_SGI = 0;
1450 search_tbl->is_fat = 0; 1399 search_tbl->ant_type = ANT_AB; /*FIXME:RS*/
1451 search_tbl->antenna_type = ANT_BOTH; 1400 ret = rs_switch_to_mimo2(priv, lq_sta, conf, sta,
1452 ret = rs_switch_to_mimo(priv, lq_sta, conf, sta,
1453 search_tbl, index); 1401 search_tbl, index);
1454 if (!ret) { 1402 if (!ret) {
1455 lq_sta->search_better_tbl = 1; 1403 lq_sta->search_better_tbl = 1;
@@ -1457,29 +1405,34 @@ static int rs_move_siso_to_other(struct iwl_priv *priv,
1457 } 1405 }
1458 break; 1406 break;
1459 case IWL_SISO_SWITCH_GI: 1407 case IWL_SISO_SWITCH_GI:
1460 IWL_DEBUG_HT("LQ: SISO SWITCH TO GI\n"); 1408 if (!tbl->is_fat &&
1409 !(priv->current_ht_config.sgf &
1410 HT_SHORT_GI_20MHZ))
1411 break;
1412 if (tbl->is_fat &&
1413 !(priv->current_ht_config.sgf &
1414 HT_SHORT_GI_40MHZ))
1415 break;
1416
1417 IWL_DEBUG_RATE("LQ: SISO toggle SGI/NGI\n");
1461 1418
1462 memcpy(search_tbl, tbl, sz); 1419 memcpy(search_tbl, tbl, sz);
1463 search_tbl->action = 0; 1420 if (is_green) {
1464 if (search_tbl->is_SGI) 1421 if (!tbl->is_SGI)
1465 search_tbl->is_SGI = 0; 1422 break;
1466 else if (!is_green) 1423 else
1467 search_tbl->is_SGI = 1; 1424 IWL_ERROR("SGI was set in GF+SISO\n");
1468 else 1425 }
1469 break; 1426 search_tbl->is_SGI = !tbl->is_SGI;
1470 lq_sta->search_better_tbl = 1; 1427 rs_set_expected_tpt_table(lq_sta, search_tbl);
1471 if ((tbl->lq_type == LQ_SISO) && 1428 if (tbl->is_SGI) {
1472 (tbl->is_SGI)) {
1473 s32 tpt = lq_sta->last_tpt / 100; 1429 s32 tpt = lq_sta->last_tpt / 100;
1474 if (((!tbl->is_fat) && 1430 if (tpt >= search_tbl->expected_tpt[index])
1475 (tpt >= expected_tpt_siso20MHz[index])) || 1431 break;
1476 ((tbl->is_fat) &&
1477 (tpt >= expected_tpt_siso40MHz[index])))
1478 lq_sta->search_better_tbl = 0;
1479 } 1432 }
1480 rs_get_expected_tpt_table(lq_sta, search_tbl); 1433 search_tbl->current_rate = rate_n_flags_from_tbl(
1481 rs_mcs_from_tbl(&search_tbl->current_rate, 1434 search_tbl, index, is_green);
1482 search_tbl, index, is_green); 1435 lq_sta->search_better_tbl = 1;
1483 goto out; 1436 goto out;
1484 } 1437 }
1485 tbl->action++; 1438 tbl->action++;
@@ -1507,7 +1460,6 @@ static int rs_move_mimo_to_other(struct iwl_priv *priv,
1507 struct sta_info *sta, 1460 struct sta_info *sta,
1508 int index) 1461 int index)
1509{ 1462{
1510 int ret;
1511 s8 is_green = lq_sta->is_green; 1463 s8 is_green = lq_sta->is_green;
1512 struct iwl4965_scale_tbl_info *tbl = 1464 struct iwl4965_scale_tbl_info *tbl =
1513 &(lq_sta->lq_info[lq_sta->active_tbl]); 1465 &(lq_sta->lq_info[lq_sta->active_tbl]);
@@ -1516,24 +1468,24 @@ static int rs_move_mimo_to_other(struct iwl_priv *priv,
1516 u32 sz = (sizeof(struct iwl4965_scale_tbl_info) - 1468 u32 sz = (sizeof(struct iwl4965_scale_tbl_info) -
1517 (sizeof(struct iwl4965_rate_scale_data) * IWL_RATE_COUNT)); 1469 (sizeof(struct iwl4965_rate_scale_data) * IWL_RATE_COUNT));
1518 u8 start_action = tbl->action; 1470 u8 start_action = tbl->action;
1471 /*u8 valid_tx_ant = priv->hw_params.valid_tx_ant;*/
1472 int ret;
1519 1473
1520 for (;;) { 1474 for (;;) {
1521 lq_sta->action_counter++; 1475 lq_sta->action_counter++;
1522 switch (tbl->action) { 1476 switch (tbl->action) {
1523 case IWL_MIMO_SWITCH_ANTENNA_A: 1477 case IWL_MIMO_SWITCH_ANTENNA_A:
1524 case IWL_MIMO_SWITCH_ANTENNA_B: 1478 case IWL_MIMO_SWITCH_ANTENNA_B:
1525 IWL_DEBUG_HT("LQ: MIMO SWITCH TO SISO\n"); 1479 IWL_DEBUG_RATE("LQ: MIMO2 switch to SISO\n");
1526
1527 1480
1528 /* Set up new search table for SISO */ 1481 /* Set up new search table for SISO */
1529 memcpy(search_tbl, tbl, sz); 1482 memcpy(search_tbl, tbl, sz);
1530 search_tbl->lq_type = LQ_SISO; 1483
1531 search_tbl->is_SGI = 0; 1484 /*FIXME:RS:need to check ant validity + C*/
1532 search_tbl->is_fat = 0;
1533 if (tbl->action == IWL_MIMO_SWITCH_ANTENNA_A) 1485 if (tbl->action == IWL_MIMO_SWITCH_ANTENNA_A)
1534 search_tbl->antenna_type = ANT_MAIN; 1486 search_tbl->ant_type = ANT_A;
1535 else 1487 else
1536 search_tbl->antenna_type = ANT_AUX; 1488 search_tbl->ant_type = ANT_B;
1537 1489
1538 ret = rs_switch_to_siso(priv, lq_sta, conf, sta, 1490 ret = rs_switch_to_siso(priv, lq_sta, conf, sta,
1539 search_tbl, index); 1491 search_tbl, index);
@@ -1544,37 +1496,35 @@ static int rs_move_mimo_to_other(struct iwl_priv *priv,
1544 break; 1496 break;
1545 1497
1546 case IWL_MIMO_SWITCH_GI: 1498 case IWL_MIMO_SWITCH_GI:
1547 IWL_DEBUG_HT("LQ: MIMO SWITCH TO GI\n"); 1499 if (!tbl->is_fat &&
1500 !(priv->current_ht_config.sgf &
1501 HT_SHORT_GI_20MHZ))
1502 break;
1503 if (tbl->is_fat &&
1504 !(priv->current_ht_config.sgf &
1505 HT_SHORT_GI_40MHZ))
1506 break;
1507
1508 IWL_DEBUG_RATE("LQ: MIMO toggle SGI/NGI\n");
1548 1509
1549 /* Set up new search table for MIMO */ 1510 /* Set up new search table for MIMO */
1550 memcpy(search_tbl, tbl, sz); 1511 memcpy(search_tbl, tbl, sz);
1551 search_tbl->lq_type = LQ_MIMO; 1512 search_tbl->is_SGI = !tbl->is_SGI;
1552 search_tbl->antenna_type = ANT_BOTH; 1513 rs_set_expected_tpt_table(lq_sta, search_tbl);
1553 search_tbl->action = 0;
1554 if (search_tbl->is_SGI)
1555 search_tbl->is_SGI = 0;
1556 else
1557 search_tbl->is_SGI = 1;
1558 lq_sta->search_better_tbl = 1;
1559
1560 /* 1514 /*
1561 * If active table already uses the fastest possible 1515 * If active table already uses the fastest possible
1562 * modulation (dual stream with short guard interval), 1516 * modulation (dual stream with short guard interval),
1563 * and it's working well, there's no need to look 1517 * and it's working well, there's no need to look
1564 * for a better type of modulation! 1518 * for a better type of modulation!
1565 */ 1519 */
1566 if ((tbl->lq_type == LQ_MIMO) && 1520 if (tbl->is_SGI) {
1567 (tbl->is_SGI)) {
1568 s32 tpt = lq_sta->last_tpt / 100; 1521 s32 tpt = lq_sta->last_tpt / 100;
1569 if (((!tbl->is_fat) && 1522 if (tpt >= search_tbl->expected_tpt[index])
1570 (tpt >= expected_tpt_mimo20MHz[index])) || 1523 break;
1571 ((tbl->is_fat) &&
1572 (tpt >= expected_tpt_mimo40MHz[index])))
1573 lq_sta->search_better_tbl = 0;
1574 } 1524 }
1575 rs_get_expected_tpt_table(lq_sta, search_tbl); 1525 search_tbl->current_rate = rate_n_flags_from_tbl(
1576 rs_mcs_from_tbl(&search_tbl->current_rate, 1526 search_tbl, index, is_green);
1577 search_tbl, index, is_green); 1527 lq_sta->search_better_tbl = 1;
1578 goto out; 1528 goto out;
1579 1529
1580 } 1530 }
@@ -1608,7 +1558,9 @@ static void rs_stay_in_table(struct iwl4965_lq_sta *lq_sta)
1608 int i; 1558 int i;
1609 int active_tbl; 1559 int active_tbl;
1610 int flush_interval_passed = 0; 1560 int flush_interval_passed = 0;
1561 struct iwl_priv *priv;
1611 1562
1563 priv = lq_sta->drv;
1612 active_tbl = lq_sta->active_tbl; 1564 active_tbl = lq_sta->active_tbl;
1613 1565
1614 tbl = &(lq_sta->lq_info[active_tbl]); 1566 tbl = &(lq_sta->lq_info[active_tbl]);
@@ -1623,9 +1575,6 @@ static void rs_stay_in_table(struct iwl4965_lq_sta *lq_sta)
1623 (unsigned long)(lq_sta->flush_timer + 1575 (unsigned long)(lq_sta->flush_timer +
1624 IWL_RATE_SCALE_FLUSH_INTVL)); 1576 IWL_RATE_SCALE_FLUSH_INTVL));
1625 1577
1626 /* For now, disable the elapsed time criterion */
1627 flush_interval_passed = 0;
1628
1629 /* 1578 /*
1630 * Check if we should allow search for new modulation mode. 1579 * Check if we should allow search for new modulation mode.
1631 * If many frames have failed or succeeded, or we've used 1580 * If many frames have failed or succeeded, or we've used
@@ -1638,7 +1587,7 @@ static void rs_stay_in_table(struct iwl4965_lq_sta *lq_sta)
1638 (lq_sta->total_success > lq_sta->max_success_limit) || 1587 (lq_sta->total_success > lq_sta->max_success_limit) ||
1639 ((!lq_sta->search_better_tbl) && (lq_sta->flush_timer) 1588 ((!lq_sta->search_better_tbl) && (lq_sta->flush_timer)
1640 && (flush_interval_passed))) { 1589 && (flush_interval_passed))) {
1641 IWL_DEBUG_HT("LQ: stay is expired %d %d %d\n:", 1590 IWL_DEBUG_RATE("LQ: stay is expired %d %d %d\n:",
1642 lq_sta->total_failed, 1591 lq_sta->total_failed,
1643 lq_sta->total_success, 1592 lq_sta->total_success,
1644 flush_interval_passed); 1593 flush_interval_passed);
@@ -1661,7 +1610,7 @@ static void rs_stay_in_table(struct iwl4965_lq_sta *lq_sta)
1661 lq_sta->table_count_limit) { 1610 lq_sta->table_count_limit) {
1662 lq_sta->table_count = 0; 1611 lq_sta->table_count = 0;
1663 1612
1664 IWL_DEBUG_HT("LQ: stay in table clear win\n"); 1613 IWL_DEBUG_RATE("LQ: stay in table clear win\n");
1665 for (i = 0; i < IWL_RATE_COUNT; i++) 1614 for (i = 0; i < IWL_RATE_COUNT; i++)
1666 rs_rate_scale_clear_window( 1615 rs_rate_scale_clear_window(
1667 &(tbl->win[i])); 1616 &(tbl->win[i]));
@@ -1699,24 +1648,23 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1699 int high_tpt = IWL_INVALID_VALUE; 1648 int high_tpt = IWL_INVALID_VALUE;
1700 u32 fail_count; 1649 u32 fail_count;
1701 s8 scale_action = 0; 1650 s8 scale_action = 0;
1702 u16 fc, rate_mask; 1651 __le16 fc;
1652 u16 rate_mask;
1703 u8 update_lq = 0; 1653 u8 update_lq = 0;
1704 struct iwl4965_lq_sta *lq_sta; 1654 struct iwl4965_lq_sta *lq_sta;
1705 struct iwl4965_scale_tbl_info *tbl, *tbl1; 1655 struct iwl4965_scale_tbl_info *tbl, *tbl1;
1706 u16 rate_scale_index_msk = 0; 1656 u16 rate_scale_index_msk = 0;
1707 struct iwl4965_rate mcs_rate; 1657 u32 rate;
1708 u8 is_green = 0; 1658 u8 is_green = 0;
1709 u8 active_tbl = 0; 1659 u8 active_tbl = 0;
1710 u8 done_search = 0; 1660 u8 done_search = 0;
1711 u16 high_low; 1661 u16 high_low;
1712#ifdef CONFIG_IWL4965_HT 1662 s32 sr;
1713 u8 tid = MAX_TID_COUNT; 1663 u8 tid = MAX_TID_COUNT;
1714 __le16 *qc;
1715#endif
1716 1664
1717 IWL_DEBUG_RATE("rate scale calculate new rate for skb\n"); 1665 IWL_DEBUG_RATE("rate scale calculate new rate for skb\n");
1718 1666
1719 fc = le16_to_cpu(hdr->frame_control); 1667 fc = hdr->frame_control;
1720 if (!ieee80211_is_data(fc) || is_multicast_ether_addr(hdr->addr1)) { 1668 if (!ieee80211_is_data(fc) || is_multicast_ether_addr(hdr->addr1)) {
1721 /* Send management frames and broadcast/multicast data using 1669 /* Send management frames and broadcast/multicast data using
1722 * lowest rate. */ 1670 * lowest rate. */
@@ -1727,19 +1675,10 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1727 if (!sta || !sta->rate_ctrl_priv) 1675 if (!sta || !sta->rate_ctrl_priv)
1728 return; 1676 return;
1729 1677
1730 if (!priv->lq_mngr.lq_ready) {
1731 IWL_DEBUG_RATE("still rate scaling not ready\n");
1732 return;
1733 }
1734 lq_sta = (struct iwl4965_lq_sta *)sta->rate_ctrl_priv; 1678 lq_sta = (struct iwl4965_lq_sta *)sta->rate_ctrl_priv;
1735 1679
1736#ifdef CONFIG_IWL4965_HT 1680 tid = rs_tl_add_packet(lq_sta, hdr);
1737 qc = ieee80211_get_qos_ctrl(hdr); 1681
1738 if (qc) {
1739 tid = (u8)(le16_to_cpu(*qc) & 0xf);
1740 rs_tl_add_packet(lq_sta, tid);
1741 }
1742#endif
1743 /* 1682 /*
1744 * Select rate-scale / modulation-mode table to work with in 1683 * Select rate-scale / modulation-mode table to work with in
1745 * the rest of this function: "search" if searching for better 1684 * the rest of this function: "search" if searching for better
@@ -1760,8 +1699,7 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1760 tbl->lq_type); 1699 tbl->lq_type);
1761 1700
1762 /* rates available for this association, and for modulation mode */ 1701 /* rates available for this association, and for modulation mode */
1763 rs_get_supported_rates(lq_sta, hdr, tbl->lq_type, 1702 rate_mask = rs_get_supported_rates(lq_sta, hdr, tbl->lq_type);
1764 &rate_mask);
1765 1703
1766 IWL_DEBUG_RATE("mask 0x%04X \n", rate_mask); 1704 IWL_DEBUG_RATE("mask 0x%04X \n", rate_mask);
1767 1705
@@ -1781,27 +1719,16 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1781 if (!rate_scale_index_msk) 1719 if (!rate_scale_index_msk)
1782 rate_scale_index_msk = rate_mask; 1720 rate_scale_index_msk = rate_mask;
1783 1721
1784 /* If current rate is no longer supported on current association, 1722 if (!((1 << index) & rate_scale_index_msk)) {
1785 * or user changed preferences for rates, find a new supported rate. */ 1723 IWL_ERROR("Current Rate is not valid\n");
1786 if (index < 0 || !((1 << index) & rate_scale_index_msk)) { 1724 return;
1787 index = IWL_INVALID_VALUE;
1788 update_lq = 1;
1789
1790 /* get the highest available rate */
1791 for (i = 0; i <= IWL_RATE_COUNT; i++) {
1792 if ((1 << i) & rate_scale_index_msk)
1793 index = i;
1794 }
1795
1796 if (index == IWL_INVALID_VALUE) {
1797 IWL_WARNING("Can not find a suitable rate\n");
1798 return;
1799 }
1800 } 1725 }
1801 1726
1802 /* Get expected throughput table and history window for current rate */ 1727 /* Get expected throughput table and history window for current rate */
1803 if (!tbl->expected_tpt) 1728 if (!tbl->expected_tpt) {
1804 rs_get_expected_tpt_table(lq_sta, tbl); 1729 IWL_ERROR("tbl->expected_tpt is NULL\n");
1730 return;
1731 }
1805 1732
1806 window = &(tbl->win[index]); 1733 window = &(tbl->win[index]);
1807 1734
@@ -1813,10 +1740,9 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1813 * in current association (use new rate found above). 1740 * in current association (use new rate found above).
1814 */ 1741 */
1815 fail_count = window->counter - window->success_counter; 1742 fail_count = window->counter - window->success_counter;
1816 if (((fail_count < IWL_RATE_MIN_FAILURE_TH) && 1743 if ((fail_count < IWL_RATE_MIN_FAILURE_TH) &&
1817 (window->success_counter < IWL_RATE_MIN_SUCCESS_TH)) 1744 (window->success_counter < IWL_RATE_MIN_SUCCESS_TH)) {
1818 || (tbl->expected_tpt == NULL)) { 1745 IWL_DEBUG_RATE("LQ: still below TH. succ=%d total=%d "
1819 IWL_DEBUG_RATE("LQ: still below TH succ %d total %d "
1820 "for index %d\n", 1746 "for index %d\n",
1821 window->success_counter, window->counter, index); 1747 window->success_counter, window->counter, index);
1822 1748
@@ -1827,44 +1753,51 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1827 * or search for a new one? */ 1753 * or search for a new one? */
1828 rs_stay_in_table(lq_sta); 1754 rs_stay_in_table(lq_sta);
1829 1755
1830 /* Set up new rate table in uCode, if needed */
1831 if (update_lq) {
1832 rs_mcs_from_tbl(&mcs_rate, tbl, index, is_green);
1833 rs_fill_link_cmd(lq_sta, &mcs_rate, &lq_sta->lq);
1834 iwl_send_lq_cmd(priv, &lq_sta->lq, CMD_ASYNC);
1835 }
1836 goto out; 1756 goto out;
1837 1757
1838 /* Else we have enough samples; calculate estimate of 1758 /* Else we have enough samples; calculate estimate of
1839 * actual average throughput */ 1759 * actual average throughput */
1840 } else 1760 } else {
1841 window->average_tpt = ((window->success_ratio * 1761 /*FIXME:RS remove this else if we don't get this error*/
1762 if (window->average_tpt != ((window->success_ratio *
1763 tbl->expected_tpt[index] + 64) / 128)) {
1764 IWL_ERROR("expected_tpt should have been calculated"
1765 " by now\n");
1766 window->average_tpt = ((window->success_ratio *
1842 tbl->expected_tpt[index] + 64) / 128); 1767 tbl->expected_tpt[index] + 64) / 128);
1768 }
1769 }
1843 1770
1844 /* If we are searching for better modulation mode, check success. */ 1771 /* If we are searching for better modulation mode, check success. */
1845 if (lq_sta->search_better_tbl) { 1772 if (lq_sta->search_better_tbl) {
1846 int success_limit = IWL_RATE_SCALE_SWITCH;
1847 1773
1848 /* If good success, continue using the "search" mode; 1774 /* If good success, continue using the "search" mode;
1849 * no need to send new link quality command, since we're 1775 * no need to send new link quality command, since we're
1850 * continuing to use the setup that we've been trying. */ 1776 * continuing to use the setup that we've been trying. */
1851 if ((window->success_ratio > success_limit) || 1777 if (window->average_tpt > lq_sta->last_tpt) {
1852 (window->average_tpt > lq_sta->last_tpt)) { 1778
1853 if (!is_legacy(tbl->lq_type)) { 1779 IWL_DEBUG_RATE("LQ: SWITCHING TO CURRENT TABLE "
1854 IWL_DEBUG_HT("LQ: we are switching to HT" 1780 "suc=%d cur-tpt=%d old-tpt=%d\n",
1855 " rate suc %d current tpt %d" 1781 window->success_ratio,
1856 " old tpt %d\n", 1782 window->average_tpt,
1857 window->success_ratio, 1783 lq_sta->last_tpt);
1858 window->average_tpt, 1784
1859 lq_sta->last_tpt); 1785 if (!is_legacy(tbl->lq_type))
1860 lq_sta->enable_counter = 1; 1786 lq_sta->enable_counter = 1;
1861 } 1787
1862 /* Swap tables; "search" becomes "active" */ 1788 /* Swap tables; "search" becomes "active" */
1863 lq_sta->active_tbl = active_tbl; 1789 lq_sta->active_tbl = active_tbl;
1864 current_tpt = window->average_tpt; 1790 current_tpt = window->average_tpt;
1865 1791
1866 /* Else poor success; go back to mode in "active" table */ 1792 /* Else poor success; go back to mode in "active" table */
1867 } else { 1793 } else {
1794
1795 IWL_DEBUG_RATE("LQ: GOING BACK TO THE OLD TABLE "
1796 "suc=%d cur-tpt=%d old-tpt=%d\n",
1797 window->success_ratio,
1798 window->average_tpt,
1799 lq_sta->last_tpt);
1800
1868 /* Nullify "search" table */ 1801 /* Nullify "search" table */
1869 tbl->lq_type = LQ_NONE; 1802 tbl->lq_type = LQ_NONE;
1870 1803
@@ -1873,13 +1806,11 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1873 tbl = &(lq_sta->lq_info[active_tbl]); 1806 tbl = &(lq_sta->lq_info[active_tbl]);
1874 1807
1875 /* Revert to "active" rate and throughput info */ 1808 /* Revert to "active" rate and throughput info */
1876 index = iwl4965_hwrate_to_plcp_idx( 1809 index = iwl_hwrate_to_plcp_idx(tbl->current_rate);
1877 tbl->current_rate.rate_n_flags);
1878 current_tpt = lq_sta->last_tpt; 1810 current_tpt = lq_sta->last_tpt;
1879 1811
1880 /* Need to set up a new rate table in uCode */ 1812 /* Need to set up a new rate table in uCode */
1881 update_lq = 1; 1813 update_lq = 1;
1882 IWL_DEBUG_HT("XXY GO BACK TO OLD TABLE\n");
1883 } 1814 }
1884 1815
1885 /* Either way, we've made a decision; modulation mode 1816 /* Either way, we've made a decision; modulation mode
@@ -1891,11 +1822,13 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1891 1822
1892 /* (Else) not in search of better modulation mode, try for better 1823 /* (Else) not in search of better modulation mode, try for better
1893 * starting rate, while staying in this mode. */ 1824 * starting rate, while staying in this mode. */
1894 high_low = rs_get_adjacent_rate(index, rate_scale_index_msk, 1825 high_low = rs_get_adjacent_rate(priv, index, rate_scale_index_msk,
1895 tbl->lq_type); 1826 tbl->lq_type);
1896 low = high_low & 0xff; 1827 low = high_low & 0xff;
1897 high = (high_low >> 8) & 0xff; 1828 high = (high_low >> 8) & 0xff;
1898 1829
1830 sr = window->success_ratio;
1831
1899 /* Collect measured throughputs for current and adjacent rates */ 1832 /* Collect measured throughputs for current and adjacent rates */
1900 current_tpt = window->average_tpt; 1833 current_tpt = window->average_tpt;
1901 if (low != IWL_RATE_INVALID) 1834 if (low != IWL_RATE_INVALID)
@@ -1903,19 +1836,22 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1903 if (high != IWL_RATE_INVALID) 1836 if (high != IWL_RATE_INVALID)
1904 high_tpt = tbl->win[high].average_tpt; 1837 high_tpt = tbl->win[high].average_tpt;
1905 1838
1906 /* Assume rate increase */ 1839 scale_action = 0;
1907 scale_action = 1;
1908 1840
1909 /* Too many failures, decrease rate */ 1841 /* Too many failures, decrease rate */
1910 if ((window->success_ratio <= IWL_RATE_DECREASE_TH) || 1842 if ((sr <= IWL_RATE_DECREASE_TH) || (current_tpt == 0)) {
1911 (current_tpt == 0)) {
1912 IWL_DEBUG_RATE("decrease rate because of low success_ratio\n"); 1843 IWL_DEBUG_RATE("decrease rate because of low success_ratio\n");
1913 scale_action = -1; 1844 scale_action = -1;
1914 1845
1915 /* No throughput measured yet for adjacent rates; try increase. */ 1846 /* No throughput measured yet for adjacent rates; try increase. */
1916 } else if ((low_tpt == IWL_INVALID_VALUE) && 1847 } else if ((low_tpt == IWL_INVALID_VALUE) &&
1917 (high_tpt == IWL_INVALID_VALUE)) 1848 (high_tpt == IWL_INVALID_VALUE)) {
1918 scale_action = 1; 1849
1850 if (high != IWL_RATE_INVALID && sr >= IWL_RATE_INCREASE_TH)
1851 scale_action = 1;
1852 else if (low != IWL_RATE_INVALID)
1853 scale_action = -1;
1854 }
1919 1855
1920 /* Both adjacent throughputs are measured, but neither one has better 1856 /* Both adjacent throughputs are measured, but neither one has better
1921 * throughput; we're using the best rate, don't change it! */ 1857 * throughput; we're using the best rate, don't change it! */
@@ -1931,9 +1867,10 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1931 /* Higher adjacent rate's throughput is measured */ 1867 /* Higher adjacent rate's throughput is measured */
1932 if (high_tpt != IWL_INVALID_VALUE) { 1868 if (high_tpt != IWL_INVALID_VALUE) {
1933 /* Higher rate has better throughput */ 1869 /* Higher rate has better throughput */
1934 if (high_tpt > current_tpt) 1870 if (high_tpt > current_tpt &&
1871 sr >= IWL_RATE_INCREASE_TH) {
1935 scale_action = 1; 1872 scale_action = 1;
1936 else { 1873 } else {
1937 IWL_DEBUG_RATE 1874 IWL_DEBUG_RATE
1938 ("decrease rate because of high tpt\n"); 1875 ("decrease rate because of high tpt\n");
1939 scale_action = -1; 1876 scale_action = -1;
@@ -1946,23 +1883,17 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1946 IWL_DEBUG_RATE 1883 IWL_DEBUG_RATE
1947 ("decrease rate because of low tpt\n"); 1884 ("decrease rate because of low tpt\n");
1948 scale_action = -1; 1885 scale_action = -1;
1949 } else 1886 } else if (sr >= IWL_RATE_INCREASE_TH) {
1950 scale_action = 1; 1887 scale_action = 1;
1888 }
1951 } 1889 }
1952 } 1890 }
1953 1891
1954 /* Sanity check; asked for decrease, but success rate or throughput 1892 /* Sanity check; asked for decrease, but success rate or throughput
1955 * has been good at old rate. Don't change it. */ 1893 * has been good at old rate. Don't change it. */
1956 if (scale_action == -1) { 1894 if ((scale_action == -1) && (low != IWL_RATE_INVALID) &&
1957 if ((low != IWL_RATE_INVALID) && 1895 ((sr > IWL_RATE_HIGH_TH) ||
1958 ((window->success_ratio > IWL_RATE_HIGH_TH) ||
1959 (current_tpt > (100 * tbl->expected_tpt[low])))) 1896 (current_tpt > (100 * tbl->expected_tpt[low]))))
1960 scale_action = 0;
1961
1962 /* Sanity check; asked for increase, but success rate has not been great
1963 * even at old rate, higher rate will be worse. Don't change it. */
1964 } else if ((scale_action == 1) &&
1965 (window->success_ratio < IWL_RATE_INCREASE_TH))
1966 scale_action = 0; 1897 scale_action = 0;
1967 1898
1968 switch (scale_action) { 1899 switch (scale_action) {
@@ -1987,15 +1918,15 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
1987 break; 1918 break;
1988 } 1919 }
1989 1920
1990 IWL_DEBUG_HT("choose rate scale index %d action %d low %d " 1921 IWL_DEBUG_RATE("choose rate scale index %d action %d low %d "
1991 "high %d type %d\n", 1922 "high %d type %d\n",
1992 index, scale_action, low, high, tbl->lq_type); 1923 index, scale_action, low, high, tbl->lq_type);
1993 1924
1994 lq_update: 1925lq_update:
1995 /* Replace uCode's rate table for the destination station. */ 1926 /* Replace uCode's rate table for the destination station. */
1996 if (update_lq) { 1927 if (update_lq) {
1997 rs_mcs_from_tbl(&mcs_rate, tbl, index, is_green); 1928 rate = rate_n_flags_from_tbl(tbl, index, is_green);
1998 rs_fill_link_cmd(lq_sta, &mcs_rate, &lq_sta->lq); 1929 rs_fill_link_cmd(priv, lq_sta, rate);
1999 iwl_send_lq_cmd(priv, &lq_sta->lq, CMD_ASYNC); 1930 iwl_send_lq_cmd(priv, &lq_sta->lq, CMD_ASYNC);
2000 } 1931 }
2001 1932
@@ -2029,13 +1960,11 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
2029 rs_rate_scale_clear_window(&(tbl->win[i])); 1960 rs_rate_scale_clear_window(&(tbl->win[i]));
2030 1961
2031 /* Use new "search" start rate */ 1962 /* Use new "search" start rate */
2032 index = iwl4965_hwrate_to_plcp_idx( 1963 index = iwl_hwrate_to_plcp_idx(tbl->current_rate);
2033 tbl->current_rate.rate_n_flags);
2034 1964
2035 IWL_DEBUG_HT("Switch current mcs: %X index: %d\n", 1965 IWL_DEBUG_RATE("Switch current mcs: %X index: %d\n",
2036 tbl->current_rate.rate_n_flags, index); 1966 tbl->current_rate, index);
2037 rs_fill_link_cmd(lq_sta, &tbl->current_rate, 1967 rs_fill_link_cmd(priv, lq_sta, tbl->current_rate);
2038 &lq_sta->lq);
2039 iwl_send_lq_cmd(priv, &lq_sta->lq, CMD_ASYNC); 1968 iwl_send_lq_cmd(priv, &lq_sta->lq, CMD_ASYNC);
2040 } 1969 }
2041 1970
@@ -2046,13 +1975,11 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
2046 * before next round of mode comparisons. */ 1975 * before next round of mode comparisons. */
2047 tbl1 = &(lq_sta->lq_info[lq_sta->active_tbl]); 1976 tbl1 = &(lq_sta->lq_info[lq_sta->active_tbl]);
2048 if (is_legacy(tbl1->lq_type) && 1977 if (is_legacy(tbl1->lq_type) &&
2049#ifdef CONFIG_IWL4965_HT
2050 (!(conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE)) && 1978 (!(conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE)) &&
2051#endif
2052 (lq_sta->action_counter >= 1)) { 1979 (lq_sta->action_counter >= 1)) {
2053 lq_sta->action_counter = 0; 1980 lq_sta->action_counter = 0;
2054 IWL_DEBUG_HT("LQ: STAY in legacy table\n"); 1981 IWL_DEBUG_RATE("LQ: STAY in legacy table\n");
2055 rs_set_stay_in_table(1, lq_sta); 1982 rs_set_stay_in_table(priv, 1, lq_sta);
2056 } 1983 }
2057 1984
2058 /* If we're in an HT mode, and all 3 mode switch actions 1985 /* If we're in an HT mode, and all 3 mode switch actions
@@ -2060,16 +1987,14 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
2060 * mode for a while before next round of mode comparisons. */ 1987 * mode for a while before next round of mode comparisons. */
2061 if (lq_sta->enable_counter && 1988 if (lq_sta->enable_counter &&
2062 (lq_sta->action_counter >= IWL_ACTION_LIMIT)) { 1989 (lq_sta->action_counter >= IWL_ACTION_LIMIT)) {
2063#ifdef CONFIG_IWL4965_HT
2064 if ((lq_sta->last_tpt > IWL_AGG_TPT_THREHOLD) && 1990 if ((lq_sta->last_tpt > IWL_AGG_TPT_THREHOLD) &&
2065 (lq_sta->tx_agg_tid_en & (1 << tid)) && 1991 (lq_sta->tx_agg_tid_en & (1 << tid)) &&
2066 (tid != MAX_TID_COUNT)) { 1992 (tid != MAX_TID_COUNT)) {
2067 IWL_DEBUG_HT("try to aggregate tid %d\n", tid); 1993 IWL_DEBUG_RATE("try to aggregate tid %d\n", tid);
2068 rs_tl_turn_on_agg(priv, tid, lq_sta, sta); 1994 rs_tl_turn_on_agg(priv, tid, lq_sta, sta);
2069 } 1995 }
2070#endif /*CONFIG_IWL4965_HT */
2071 lq_sta->action_counter = 0; 1996 lq_sta->action_counter = 0;
2072 rs_set_stay_in_table(0, lq_sta); 1997 rs_set_stay_in_table(priv, 0, lq_sta);
2073 } 1998 }
2074 1999
2075 /* 2000 /*
@@ -2085,7 +2010,7 @@ static void rs_rate_scale_perform(struct iwl_priv *priv,
2085 } 2010 }
2086 2011
2087out: 2012out:
2088 rs_mcs_from_tbl(&tbl->current_rate, tbl, index, is_green); 2013 tbl->current_rate = rate_n_flags_from_tbl(tbl, index, is_green);
2089 i = index; 2014 i = index;
2090 sta->last_txrate_idx = i; 2015 sta->last_txrate_idx = i;
2091 2016
@@ -2105,13 +2030,14 @@ static void rs_initialize_lq(struct iwl_priv *priv,
2105 struct ieee80211_conf *conf, 2030 struct ieee80211_conf *conf,
2106 struct sta_info *sta) 2031 struct sta_info *sta)
2107{ 2032{
2108 int i;
2109 struct iwl4965_lq_sta *lq_sta; 2033 struct iwl4965_lq_sta *lq_sta;
2110 struct iwl4965_scale_tbl_info *tbl; 2034 struct iwl4965_scale_tbl_info *tbl;
2111 u8 active_tbl = 0;
2112 int rate_idx; 2035 int rate_idx;
2036 int i;
2037 u32 rate;
2113 u8 use_green = rs_use_green(priv, conf); 2038 u8 use_green = rs_use_green(priv, conf);
2114 struct iwl4965_rate mcs_rate; 2039 u8 active_tbl = 0;
2040 u8 valid_tx_ant;
2115 2041
2116 if (!sta || !sta->rate_ctrl_priv) 2042 if (!sta || !sta->rate_ctrl_priv)
2117 goto out; 2043 goto out;
@@ -2123,6 +2049,8 @@ static void rs_initialize_lq(struct iwl_priv *priv,
2123 (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)) 2049 (priv->iw_mode == IEEE80211_IF_TYPE_IBSS))
2124 goto out; 2050 goto out;
2125 2051
2052 valid_tx_ant = priv->hw_params.valid_tx_ant;
2053
2126 if (!lq_sta->search_better_tbl) 2054 if (!lq_sta->search_better_tbl)
2127 active_tbl = lq_sta->active_tbl; 2055 active_tbl = lq_sta->active_tbl;
2128 else 2056 else
@@ -2133,22 +2061,23 @@ static void rs_initialize_lq(struct iwl_priv *priv,
2133 if ((i < 0) || (i >= IWL_RATE_COUNT)) 2061 if ((i < 0) || (i >= IWL_RATE_COUNT))
2134 i = 0; 2062 i = 0;
2135 2063
2136 mcs_rate.rate_n_flags = iwl4965_rates[i].plcp ; 2064 /* FIXME:RS: This is also wrong in 4965 */
2137 mcs_rate.rate_n_flags |= RATE_MCS_ANT_B_MSK; 2065 rate = iwl_rates[i].plcp;
2138 mcs_rate.rate_n_flags &= ~RATE_MCS_ANT_A_MSK; 2066 rate |= RATE_MCS_ANT_B_MSK;
2067 rate &= ~RATE_MCS_ANT_A_MSK;
2139 2068
2140 if (i >= IWL_FIRST_CCK_RATE && i <= IWL_LAST_CCK_RATE) 2069 if (i >= IWL_FIRST_CCK_RATE && i <= IWL_LAST_CCK_RATE)
2141 mcs_rate.rate_n_flags |= RATE_MCS_CCK_MSK; 2070 rate |= RATE_MCS_CCK_MSK;
2142 2071
2143 tbl->antenna_type = ANT_AUX; 2072 tbl->ant_type = ANT_B;
2144 rs_get_tbl_info_from_mcs(&mcs_rate, priv->band, tbl, &rate_idx); 2073 rs_get_tbl_info_from_mcs(rate, priv->band, tbl, &rate_idx);
2145 if (!rs_is_ant_connected(priv->valid_antenna, tbl->antenna_type)) 2074 if (!rs_is_valid_ant(valid_tx_ant, tbl->ant_type))
2146 rs_toggle_antenna(&mcs_rate, tbl); 2075 rs_toggle_antenna(valid_tx_ant, &rate, tbl);
2147 2076
2148 rs_mcs_from_tbl(&mcs_rate, tbl, rate_idx, use_green); 2077 rate = rate_n_flags_from_tbl(tbl, rate_idx, use_green);
2149 tbl->current_rate.rate_n_flags = mcs_rate.rate_n_flags; 2078 tbl->current_rate = rate;
2150 rs_get_expected_tpt_table(lq_sta, tbl); 2079 rs_set_expected_tpt_table(lq_sta, tbl);
2151 rs_fill_link_cmd(lq_sta, &mcs_rate, &lq_sta->lq); 2080 rs_fill_link_cmd(NULL, lq_sta, rate);
2152 iwl_send_lq_cmd(priv, &lq_sta->lq, CMD_ASYNC); 2081 iwl_send_lq_cmd(priv, &lq_sta->lq, CMD_ASYNC);
2153 out: 2082 out:
2154 return; 2083 return;
@@ -2165,7 +2094,7 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
2165 struct ieee80211_conf *conf = &local->hw.conf; 2094 struct ieee80211_conf *conf = &local->hw.conf;
2166 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2095 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2167 struct sta_info *sta; 2096 struct sta_info *sta;
2168 u16 fc; 2097 __le16 fc;
2169 struct iwl_priv *priv = (struct iwl_priv *)priv_rate; 2098 struct iwl_priv *priv = (struct iwl_priv *)priv_rate;
2170 struct iwl4965_lq_sta *lq_sta; 2099 struct iwl4965_lq_sta *lq_sta;
2171 2100
@@ -2177,10 +2106,10 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
2177 2106
2178 /* Send management frames and broadcast/multicast data using lowest 2107 /* Send management frames and broadcast/multicast data using lowest
2179 * rate. */ 2108 * rate. */
2180 fc = le16_to_cpu(hdr->frame_control); 2109 fc = hdr->frame_control;
2181 if (!ieee80211_is_data(fc) || is_multicast_ether_addr(hdr->addr1) || 2110 if (!ieee80211_is_data(fc) || is_multicast_ether_addr(hdr->addr1) ||
2182 !sta || !sta->rate_ctrl_priv) { 2111 !sta || !sta->rate_ctrl_priv) {
2183 sel->rate = rate_lowest(local, sband, sta); 2112 sel->rate_idx = rate_lowest_index(local, sband, sta);
2184 goto out; 2113 goto out;
2185 } 2114 }
2186 2115
@@ -2189,13 +2118,13 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
2189 2118
2190 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && 2119 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2191 !lq_sta->ibss_sta_added) { 2120 !lq_sta->ibss_sta_added) {
2192 u8 sta_id = iwl4965_hw_find_station(priv, hdr->addr1); 2121 u8 sta_id = iwl_find_station(priv, hdr->addr1);
2193 DECLARE_MAC_BUF(mac); 2122 DECLARE_MAC_BUF(mac);
2194 2123
2195 if (sta_id == IWL_INVALID_STATION) { 2124 if (sta_id == IWL_INVALID_STATION) {
2196 IWL_DEBUG_RATE("LQ: ADD station %s\n", 2125 IWL_DEBUG_RATE("LQ: ADD station %s\n",
2197 print_mac(mac, hdr->addr1)); 2126 print_mac(mac, hdr->addr1));
2198 sta_id = iwl4965_add_station_flags(priv, hdr->addr1, 2127 sta_id = iwl_add_station_flags(priv, hdr->addr1,
2199 0, CMD_ASYNC, NULL); 2128 0, CMD_ASYNC, NULL);
2200 } 2129 }
2201 if ((sta_id != IWL_INVALID_STATION)) { 2130 if ((sta_id != IWL_INVALID_STATION)) {
@@ -2204,26 +2133,27 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
2204 lq_sta->ibss_sta_added = 1; 2133 lq_sta->ibss_sta_added = 1;
2205 rs_initialize_lq(priv, conf, sta); 2134 rs_initialize_lq(priv, conf, sta);
2206 } 2135 }
2207 if (!lq_sta->ibss_sta_added)
2208 goto done;
2209 } 2136 }
2210 2137
2211done:
2212 if ((i < 0) || (i > IWL_RATE_COUNT)) { 2138 if ((i < 0) || (i > IWL_RATE_COUNT)) {
2213 sel->rate = rate_lowest(local, sband, sta); 2139 sel->rate_idx = rate_lowest_index(local, sband, sta);
2214 goto out; 2140 goto out;
2215 } 2141 }
2216 2142
2217 sel->rate = &priv->ieee_rates[i]; 2143 if (sband->band == IEEE80211_BAND_5GHZ)
2144 i -= IWL_FIRST_OFDM_RATE;
2145 sel->rate_idx = i;
2218out: 2146out:
2219 rcu_read_unlock(); 2147 rcu_read_unlock();
2220} 2148}
2221 2149
2222static void *rs_alloc_sta(void *priv, gfp_t gfp) 2150static void *rs_alloc_sta(void *priv_rate, gfp_t gfp)
2223{ 2151{
2224 struct iwl4965_lq_sta *lq_sta; 2152 struct iwl4965_lq_sta *lq_sta;
2153 struct iwl_priv *priv;
2225 int i, j; 2154 int i, j;
2226 2155
2156 priv = (struct iwl_priv *)priv_rate;
2227 IWL_DEBUG_RATE("create station rate scale window\n"); 2157 IWL_DEBUG_RATE("create station rate scale window\n");
2228 2158
2229 lq_sta = kzalloc(sizeof(struct iwl4965_lq_sta), gfp); 2159 lq_sta = kzalloc(sizeof(struct iwl4965_lq_sta), gfp);
@@ -2259,7 +2189,7 @@ static void rs_rate_init(void *priv_rate, void *priv_sta,
2259 for (i = 0; i < IWL_RATE_COUNT; i++) 2189 for (i = 0; i < IWL_RATE_COUNT; i++)
2260 rs_rate_scale_clear_window(&(lq_sta->lq_info[j].win[i])); 2190 rs_rate_scale_clear_window(&(lq_sta->lq_info[j].win[i]));
2261 2191
2262 IWL_DEBUG_RATE("rate scale global init\n"); 2192 IWL_DEBUG_RATE("LQ: *** rate scale global init ***\n");
2263 /* TODO: what is a good starting rate for STA? About middle? Maybe not 2193 /* TODO: what is a good starting rate for STA? About middle? Maybe not
2264 * the lowest or the highest rate.. Could consider using RSSI from 2194 * the lowest or the highest rate.. Could consider using RSSI from
2265 * previous packets? Need to have IEEE 802.1X auth succeed immediately 2195 * previous packets? Need to have IEEE 802.1X auth succeed immediately
@@ -2267,17 +2197,17 @@ static void rs_rate_init(void *priv_rate, void *priv_sta,
2267 2197
2268 lq_sta->ibss_sta_added = 0; 2198 lq_sta->ibss_sta_added = 0;
2269 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { 2199 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2270 u8 sta_id = iwl4965_hw_find_station(priv, sta->addr); 2200 u8 sta_id = iwl_find_station(priv, sta->addr);
2271 DECLARE_MAC_BUF(mac); 2201 DECLARE_MAC_BUF(mac);
2272 2202
2273 /* for IBSS the call are from tasklet */ 2203 /* for IBSS the call are from tasklet */
2274 IWL_DEBUG_HT("LQ: ADD station %s\n", 2204 IWL_DEBUG_RATE("LQ: ADD station %s\n",
2275 print_mac(mac, sta->addr)); 2205 print_mac(mac, sta->addr));
2276 2206
2277 if (sta_id == IWL_INVALID_STATION) { 2207 if (sta_id == IWL_INVALID_STATION) {
2278 IWL_DEBUG_RATE("LQ: ADD station %s\n", 2208 IWL_DEBUG_RATE("LQ: ADD station %s\n",
2279 print_mac(mac, sta->addr)); 2209 print_mac(mac, sta->addr));
2280 sta_id = iwl4965_add_station_flags(priv, sta->addr, 2210 sta_id = iwl_add_station_flags(priv, sta->addr,
2281 0, CMD_ASYNC, NULL); 2211 0, CMD_ASYNC, NULL);
2282 } 2212 }
2283 if ((sta_id != IWL_INVALID_STATION)) { 2213 if ((sta_id != IWL_INVALID_STATION)) {
@@ -2300,92 +2230,95 @@ static void rs_rate_init(void *priv_rate, void *priv_sta,
2300 sta->last_txrate_idx += IWL_FIRST_OFDM_RATE; 2230 sta->last_txrate_idx += IWL_FIRST_OFDM_RATE;
2301 2231
2302 lq_sta->is_dup = 0; 2232 lq_sta->is_dup = 0;
2303 lq_sta->valid_antenna = priv->valid_antenna;
2304 lq_sta->antenna = priv->antenna;
2305 lq_sta->is_green = rs_use_green(priv, conf); 2233 lq_sta->is_green = rs_use_green(priv, conf);
2306 lq_sta->active_rate = priv->active_rate; 2234 lq_sta->active_legacy_rate = priv->active_rate & ~(0x1000);
2307 lq_sta->active_rate &= ~(0x1000);
2308 lq_sta->active_rate_basic = priv->active_rate_basic; 2235 lq_sta->active_rate_basic = priv->active_rate_basic;
2309 lq_sta->band = priv->band; 2236 lq_sta->band = priv->band;
2310#ifdef CONFIG_IWL4965_HT
2311 /* 2237 /*
2312 * active_siso_rate mask includes 9 MBits (bit 5), and CCK (bits 0-3), 2238 * active_siso_rate mask includes 9 MBits (bit 5), and CCK (bits 0-3),
2313 * supp_rates[] does not; shift to convert format, force 9 MBits off. 2239 * supp_rates[] does not; shift to convert format, force 9 MBits off.
2314 */ 2240 */
2315 lq_sta->active_siso_rate = (priv->current_ht_config.supp_mcs_set[0] << 1); 2241 lq_sta->active_siso_rate = conf->ht_conf.supp_mcs_set[0] << 1;
2316 lq_sta->active_siso_rate |= 2242 lq_sta->active_siso_rate |= conf->ht_conf.supp_mcs_set[0] & 0x1;
2317 (priv->current_ht_config.supp_mcs_set[0] & 0x1);
2318 lq_sta->active_siso_rate &= ~((u16)0x2); 2243 lq_sta->active_siso_rate &= ~((u16)0x2);
2319 lq_sta->active_siso_rate = 2244 lq_sta->active_siso_rate <<= IWL_FIRST_OFDM_RATE;
2320 lq_sta->active_siso_rate << IWL_FIRST_OFDM_RATE;
2321 2245
2322 /* Same here */ 2246 /* Same here */
2323 lq_sta->active_mimo_rate = (priv->current_ht_config.supp_mcs_set[1] << 1); 2247 lq_sta->active_mimo2_rate = conf->ht_conf.supp_mcs_set[1] << 1;
2324 lq_sta->active_mimo_rate |= 2248 lq_sta->active_mimo2_rate |= conf->ht_conf.supp_mcs_set[1] & 0x1;
2325 (priv->current_ht_config.supp_mcs_set[1] & 0x1); 2249 lq_sta->active_mimo2_rate &= ~((u16)0x2);
2326 lq_sta->active_mimo_rate &= ~((u16)0x2); 2250 lq_sta->active_mimo2_rate <<= IWL_FIRST_OFDM_RATE;
2327 lq_sta->active_mimo_rate = 2251
2328 lq_sta->active_mimo_rate << IWL_FIRST_OFDM_RATE; 2252 lq_sta->active_mimo3_rate = conf->ht_conf.supp_mcs_set[2] << 1;
2329 IWL_DEBUG_HT("SISO RATE 0x%X MIMO RATE 0x%X\n", 2253 lq_sta->active_mimo3_rate |= conf->ht_conf.supp_mcs_set[2] & 0x1;
2254 lq_sta->active_mimo3_rate &= ~((u16)0x2);
2255 lq_sta->active_mimo3_rate <<= IWL_FIRST_OFDM_RATE;
2256
2257 IWL_DEBUG_RATE("SISO-RATE=%X MIMO2-RATE=%X MIMO3-RATE=%X\n",
2330 lq_sta->active_siso_rate, 2258 lq_sta->active_siso_rate,
2331 lq_sta->active_mimo_rate); 2259 lq_sta->active_mimo2_rate,
2260 lq_sta->active_mimo3_rate);
2261
2262 /* These values will be overriden later */
2263 lq_sta->lq.general_params.single_stream_ant_msk = ANT_A;
2264 lq_sta->lq.general_params.dual_stream_ant_msk = ANT_AB;
2265
2332 /* as default allow aggregation for all tids */ 2266 /* as default allow aggregation for all tids */
2333 lq_sta->tx_agg_tid_en = IWL_AGG_ALL_TID; 2267 lq_sta->tx_agg_tid_en = IWL_AGG_ALL_TID;
2334#endif /*CONFIG_IWL4965_HT*/
2335#ifdef CONFIG_MAC80211_DEBUGFS
2336 lq_sta->drv = priv; 2268 lq_sta->drv = priv;
2337#endif
2338
2339 if (priv->assoc_station_added)
2340 priv->lq_mngr.lq_ready = 1;
2341 2269
2342 rs_initialize_lq(priv, conf, sta); 2270 rs_initialize_lq(priv, conf, sta);
2343} 2271}
2344 2272
2345static void rs_fill_link_cmd(struct iwl4965_lq_sta *lq_sta, 2273static void rs_fill_link_cmd(const struct iwl_priv *priv,
2346 struct iwl4965_rate *tx_mcs, 2274 struct iwl4965_lq_sta *lq_sta,
2347 struct iwl_link_quality_cmd *lq_cmd) 2275 u32 new_rate)
2348{ 2276{
2277 struct iwl4965_scale_tbl_info tbl_type;
2349 int index = 0; 2278 int index = 0;
2350 int rate_idx; 2279 int rate_idx;
2351 int repeat_rate = 0; 2280 int repeat_rate = 0;
2352 u8 ant_toggle_count = 0; 2281 u8 ant_toggle_cnt = 0;
2353 u8 use_ht_possible = 1; 2282 u8 use_ht_possible = 1;
2354 struct iwl4965_rate new_rate; 2283 u8 valid_tx_ant = 0;
2355 struct iwl4965_scale_tbl_info tbl_type = { 0 }; 2284 struct iwl_link_quality_cmd *lq_cmd = &lq_sta->lq;
2356 2285
2357 /* Override starting rate (index 0) if needed for debug purposes */ 2286 /* Override starting rate (index 0) if needed for debug purposes */
2358 rs_dbgfs_set_mcs(lq_sta, tx_mcs, index); 2287 rs_dbgfs_set_mcs(lq_sta, &new_rate, index);
2359 2288
2360 /* Interpret rate_n_flags */ 2289 /* Interpret new_rate (rate_n_flags) */
2361 rs_get_tbl_info_from_mcs(tx_mcs, lq_sta->band, 2290 memset(&tbl_type, 0, sizeof(tbl_type));
2291 rs_get_tbl_info_from_mcs(new_rate, lq_sta->band,
2362 &tbl_type, &rate_idx); 2292 &tbl_type, &rate_idx);
2363 2293
2364 /* How many times should we repeat the initial rate? */ 2294 /* How many times should we repeat the initial rate? */
2365 if (is_legacy(tbl_type.lq_type)) { 2295 if (is_legacy(tbl_type.lq_type)) {
2366 ant_toggle_count = 1; 2296 ant_toggle_cnt = 1;
2367 repeat_rate = IWL_NUMBER_TRY; 2297 repeat_rate = IWL_NUMBER_TRY;
2368 } else 2298 } else {
2369 repeat_rate = IWL_HT_NUMBER_TRY; 2299 repeat_rate = IWL_HT_NUMBER_TRY;
2300 }
2370 2301
2371 lq_cmd->general_params.mimo_delimiter = 2302 lq_cmd->general_params.mimo_delimiter =
2372 is_mimo(tbl_type.lq_type) ? 1 : 0; 2303 is_mimo(tbl_type.lq_type) ? 1 : 0;
2373 2304
2374 /* Fill 1st table entry (index 0) */ 2305 /* Fill 1st table entry (index 0) */
2375 lq_cmd->rs_table[index].rate_n_flags = 2306 lq_cmd->rs_table[index].rate_n_flags = cpu_to_le32(new_rate);
2376 cpu_to_le32(tx_mcs->rate_n_flags);
2377 new_rate.rate_n_flags = tx_mcs->rate_n_flags;
2378 2307
2379 if (is_mimo(tbl_type.lq_type) || (tbl_type.antenna_type == ANT_MAIN)) 2308 if (num_of_ant(tbl_type.ant_type) == 1) {
2380 lq_cmd->general_params.single_stream_ant_msk 2309 lq_cmd->general_params.single_stream_ant_msk =
2381 = LINK_QUAL_ANT_A_MSK; 2310 tbl_type.ant_type;
2382 else 2311 } else if (num_of_ant(tbl_type.ant_type) == 2) {
2383 lq_cmd->general_params.single_stream_ant_msk 2312 lq_cmd->general_params.dual_stream_ant_msk =
2384 = LINK_QUAL_ANT_B_MSK; 2313 tbl_type.ant_type;
2314 } /* otherwise we don't modify the existing value */
2385 2315
2386 index++; 2316 index++;
2387 repeat_rate--; 2317 repeat_rate--;
2388 2318
2319 if (priv)
2320 valid_tx_ant = priv->hw_params.valid_tx_ant;
2321
2389 /* Fill rest of rate table */ 2322 /* Fill rest of rate table */
2390 while (index < LINK_QUAL_MAX_RETRY_NUM) { 2323 while (index < LINK_QUAL_MAX_RETRY_NUM) {
2391 /* Repeat initial/next rate. 2324 /* Repeat initial/next rate.
@@ -2393,26 +2326,25 @@ static void rs_fill_link_cmd(struct iwl4965_lq_sta *lq_sta,
2393 * For HT IWL_HT_NUMBER_TRY == 3, this executes twice. */ 2326 * For HT IWL_HT_NUMBER_TRY == 3, this executes twice. */
2394 while (repeat_rate > 0 && (index < LINK_QUAL_MAX_RETRY_NUM)) { 2327 while (repeat_rate > 0 && (index < LINK_QUAL_MAX_RETRY_NUM)) {
2395 if (is_legacy(tbl_type.lq_type)) { 2328 if (is_legacy(tbl_type.lq_type)) {
2396 if (ant_toggle_count < 2329 if (ant_toggle_cnt < NUM_TRY_BEFORE_ANT_TOGGLE)
2397 NUM_TRY_BEFORE_ANTENNA_TOGGLE) 2330 ant_toggle_cnt++;
2398 ant_toggle_count++; 2331 else if (priv &&
2399 else { 2332 rs_toggle_antenna(valid_tx_ant,
2400 rs_toggle_antenna(&new_rate, &tbl_type); 2333 &new_rate, &tbl_type))
2401 ant_toggle_count = 1; 2334 ant_toggle_cnt = 1;
2402 } 2335}
2403 }
2404 2336
2405 /* Override next rate if needed for debug purposes */ 2337 /* Override next rate if needed for debug purposes */
2406 rs_dbgfs_set_mcs(lq_sta, &new_rate, index); 2338 rs_dbgfs_set_mcs(lq_sta, &new_rate, index);
2407 2339
2408 /* Fill next table entry */ 2340 /* Fill next table entry */
2409 lq_cmd->rs_table[index].rate_n_flags = 2341 lq_cmd->rs_table[index].rate_n_flags =
2410 cpu_to_le32(new_rate.rate_n_flags); 2342 cpu_to_le32(new_rate);
2411 repeat_rate--; 2343 repeat_rate--;
2412 index++; 2344 index++;
2413 } 2345 }
2414 2346
2415 rs_get_tbl_info_from_mcs(&new_rate, lq_sta->band, &tbl_type, 2347 rs_get_tbl_info_from_mcs(new_rate, lq_sta->band, &tbl_type,
2416 &rate_idx); 2348 &rate_idx);
2417 2349
2418 /* Indicate to uCode which entries might be MIMO. 2350 /* Indicate to uCode which entries might be MIMO.
@@ -2422,20 +2354,22 @@ static void rs_fill_link_cmd(struct iwl4965_lq_sta *lq_sta,
2422 lq_cmd->general_params.mimo_delimiter = index; 2354 lq_cmd->general_params.mimo_delimiter = index;
2423 2355
2424 /* Get next rate */ 2356 /* Get next rate */
2425 rs_get_lower_rate(lq_sta, &tbl_type, rate_idx, 2357 new_rate = rs_get_lower_rate(lq_sta, &tbl_type, rate_idx,
2426 use_ht_possible, &new_rate); 2358 use_ht_possible);
2427 2359
2428 /* How many times should we repeat the next rate? */ 2360 /* How many times should we repeat the next rate? */
2429 if (is_legacy(tbl_type.lq_type)) { 2361 if (is_legacy(tbl_type.lq_type)) {
2430 if (ant_toggle_count < NUM_TRY_BEFORE_ANTENNA_TOGGLE) 2362 if (ant_toggle_cnt < NUM_TRY_BEFORE_ANT_TOGGLE)
2431 ant_toggle_count++; 2363 ant_toggle_cnt++;
2432 else { 2364 else if (priv &&
2433 rs_toggle_antenna(&new_rate, &tbl_type); 2365 rs_toggle_antenna(valid_tx_ant,
2434 ant_toggle_count = 1; 2366 &new_rate, &tbl_type))
2435 } 2367 ant_toggle_cnt = 1;
2368
2436 repeat_rate = IWL_NUMBER_TRY; 2369 repeat_rate = IWL_NUMBER_TRY;
2437 } else 2370 } else {
2438 repeat_rate = IWL_HT_NUMBER_TRY; 2371 repeat_rate = IWL_HT_NUMBER_TRY;
2372 }
2439 2373
2440 /* Don't allow HT rates after next pass. 2374 /* Don't allow HT rates after next pass.
2441 * rs_get_lower_rate() will change type to LQ_A or LQ_G. */ 2375 * rs_get_lower_rate() will change type to LQ_A or LQ_G. */
@@ -2445,14 +2379,13 @@ static void rs_fill_link_cmd(struct iwl4965_lq_sta *lq_sta,
2445 rs_dbgfs_set_mcs(lq_sta, &new_rate, index); 2379 rs_dbgfs_set_mcs(lq_sta, &new_rate, index);
2446 2380
2447 /* Fill next table entry */ 2381 /* Fill next table entry */
2448 lq_cmd->rs_table[index].rate_n_flags = 2382 lq_cmd->rs_table[index].rate_n_flags = cpu_to_le32(new_rate);
2449 cpu_to_le32(new_rate.rate_n_flags);
2450 2383
2451 index++; 2384 index++;
2452 repeat_rate--; 2385 repeat_rate--;
2453 } 2386 }
2454 2387
2455 lq_cmd->general_params.dual_stream_ant_msk = 3; 2388 lq_cmd->agg_params.agg_frame_cnt_limit = 64;
2456 lq_cmd->agg_params.agg_dis_start_th = 3; 2389 lq_cmd->agg_params.agg_dis_start_th = 3;
2457 lq_cmd->agg_params.agg_time_limit = cpu_to_le16(4000); 2390 lq_cmd->agg_params.agg_time_limit = cpu_to_le16(4000);
2458} 2391}
@@ -2473,15 +2406,17 @@ static void rs_clear(void *priv_rate)
2473 2406
2474 IWL_DEBUG_RATE("enter\n"); 2407 IWL_DEBUG_RATE("enter\n");
2475 2408
2476 priv->lq_mngr.lq_ready = 0; 2409 /* TODO - add rate scale state reset */
2477 2410
2478 IWL_DEBUG_RATE("leave\n"); 2411 IWL_DEBUG_RATE("leave\n");
2479} 2412}
2480 2413
2481static void rs_free_sta(void *priv, void *priv_sta) 2414static void rs_free_sta(void *priv_rate, void *priv_sta)
2482{ 2415{
2483 struct iwl4965_lq_sta *lq_sta = priv_sta; 2416 struct iwl4965_lq_sta *lq_sta = priv_sta;
2417 struct iwl_priv *priv;
2484 2418
2419 priv = (struct iwl_priv *)priv_rate;
2485 IWL_DEBUG_RATE("enter\n"); 2420 IWL_DEBUG_RATE("enter\n");
2486 kfree(lq_sta); 2421 kfree(lq_sta);
2487 IWL_DEBUG_RATE("leave\n"); 2422 IWL_DEBUG_RATE("leave\n");
@@ -2495,54 +2430,56 @@ static int open_file_generic(struct inode *inode, struct file *file)
2495 return 0; 2430 return 0;
2496} 2431}
2497static void rs_dbgfs_set_mcs(struct iwl4965_lq_sta *lq_sta, 2432static void rs_dbgfs_set_mcs(struct iwl4965_lq_sta *lq_sta,
2498 struct iwl4965_rate *mcs, int index) 2433 u32 *rate_n_flags, int index)
2499{ 2434{
2500 u32 base_rate; 2435 struct iwl_priv *priv;
2501 2436
2502 if (lq_sta->band == IEEE80211_BAND_5GHZ) 2437 priv = lq_sta->drv;
2503 base_rate = 0x800D; 2438 if (lq_sta->dbg_fixed_rate) {
2504 else 2439 if (index < 12) {
2505 base_rate = 0x820A; 2440 *rate_n_flags = lq_sta->dbg_fixed_rate;
2506 2441 } else {
2507 if (lq_sta->dbg_fixed.rate_n_flags) { 2442 if (lq_sta->band == IEEE80211_BAND_5GHZ)
2508 if (index < 12) 2443 *rate_n_flags = 0x800D;
2509 mcs->rate_n_flags = lq_sta->dbg_fixed.rate_n_flags; 2444 else
2510 else 2445 *rate_n_flags = 0x820A;
2511 mcs->rate_n_flags = base_rate; 2446 }
2512 IWL_DEBUG_RATE("Fixed rate ON\n"); 2447 IWL_DEBUG_RATE("Fixed rate ON\n");
2513 return; 2448 } else {
2449 IWL_DEBUG_RATE("Fixed rate OFF\n");
2514 } 2450 }
2515
2516 IWL_DEBUG_RATE("Fixed rate OFF\n");
2517} 2451}
2518 2452
2519static ssize_t rs_sta_dbgfs_scale_table_write(struct file *file, 2453static ssize_t rs_sta_dbgfs_scale_table_write(struct file *file,
2520 const char __user *user_buf, size_t count, loff_t *ppos) 2454 const char __user *user_buf, size_t count, loff_t *ppos)
2521{ 2455{
2522 struct iwl4965_lq_sta *lq_sta = file->private_data; 2456 struct iwl4965_lq_sta *lq_sta = file->private_data;
2457 struct iwl_priv *priv;
2523 char buf[64]; 2458 char buf[64];
2524 int buf_size; 2459 int buf_size;
2525 u32 parsed_rate; 2460 u32 parsed_rate;
2526 2461
2462 priv = lq_sta->drv;
2527 memset(buf, 0, sizeof(buf)); 2463 memset(buf, 0, sizeof(buf));
2528 buf_size = min(count, sizeof(buf) - 1); 2464 buf_size = min(count, sizeof(buf) - 1);
2529 if (copy_from_user(buf, user_buf, buf_size)) 2465 if (copy_from_user(buf, user_buf, buf_size))
2530 return -EFAULT; 2466 return -EFAULT;
2531 2467
2532 if (sscanf(buf, "%x", &parsed_rate) == 1) 2468 if (sscanf(buf, "%x", &parsed_rate) == 1)
2533 lq_sta->dbg_fixed.rate_n_flags = parsed_rate; 2469 lq_sta->dbg_fixed_rate = parsed_rate;
2534 else 2470 else
2535 lq_sta->dbg_fixed.rate_n_flags = 0; 2471 lq_sta->dbg_fixed_rate = 0;
2536 2472
2537 lq_sta->active_rate = 0x0FFF; /* 1 - 54 MBits, includes CCK */ 2473 lq_sta->active_legacy_rate = 0x0FFF; /* 1 - 54 MBits, includes CCK */
2538 lq_sta->active_siso_rate = 0x1FD0; /* 6 - 60 MBits, no 9, no CCK */ 2474 lq_sta->active_siso_rate = 0x1FD0; /* 6 - 60 MBits, no 9, no CCK */
2539 lq_sta->active_mimo_rate = 0x1FD0; /* 6 - 60 MBits, no 9, no CCK */ 2475 lq_sta->active_mimo2_rate = 0x1FD0; /* 6 - 60 MBits, no 9, no CCK */
2476 lq_sta->active_mimo3_rate = 0x1FD0; /* 6 - 60 MBits, no 9, no CCK */
2540 2477
2541 IWL_DEBUG_RATE("sta_id %d rate 0x%X\n", 2478 IWL_DEBUG_RATE("sta_id %d rate 0x%X\n",
2542 lq_sta->lq.sta_id, lq_sta->dbg_fixed.rate_n_flags); 2479 lq_sta->lq.sta_id, lq_sta->dbg_fixed_rate);
2543 2480
2544 if (lq_sta->dbg_fixed.rate_n_flags) { 2481 if (lq_sta->dbg_fixed_rate) {
2545 rs_fill_link_cmd(lq_sta, &lq_sta->dbg_fixed, &lq_sta->lq); 2482 rs_fill_link_cmd(NULL, lq_sta, lq_sta->dbg_fixed_rate);
2546 iwl_send_lq_cmd(lq_sta->drv, &lq_sta->lq, CMD_ASYNC); 2483 iwl_send_lq_cmd(lq_sta->drv, &lq_sta->lq, CMD_ASYNC);
2547 } 2484 }
2548 2485
@@ -2561,9 +2498,9 @@ static ssize_t rs_sta_dbgfs_scale_table_read(struct file *file,
2561 desc += sprintf(buff+desc, "sta_id %d\n", lq_sta->lq.sta_id); 2498 desc += sprintf(buff+desc, "sta_id %d\n", lq_sta->lq.sta_id);
2562 desc += sprintf(buff+desc, "failed=%d success=%d rate=0%X\n", 2499 desc += sprintf(buff+desc, "failed=%d success=%d rate=0%X\n",
2563 lq_sta->total_failed, lq_sta->total_success, 2500 lq_sta->total_failed, lq_sta->total_success,
2564 lq_sta->active_rate); 2501 lq_sta->active_legacy_rate);
2565 desc += sprintf(buff+desc, "fixed rate 0x%X\n", 2502 desc += sprintf(buff+desc, "fixed rate 0x%X\n",
2566 lq_sta->dbg_fixed.rate_n_flags); 2503 lq_sta->dbg_fixed_rate);
2567 desc += sprintf(buff+desc, "general:" 2504 desc += sprintf(buff+desc, "general:"
2568 "flags=0x%X mimo-d=%d s-ant0x%x d-ant=0x%x\n", 2505 "flags=0x%X mimo-d=%d s-ant0x%x d-ant=0x%x\n",
2569 lq_sta->lq.general_params.flags, 2506 lq_sta->lq.general_params.flags,
@@ -2613,7 +2550,7 @@ static ssize_t rs_sta_dbgfs_stats_table_read(struct file *file,
2613 lq_sta->lq_info[i].is_SGI, 2550 lq_sta->lq_info[i].is_SGI,
2614 lq_sta->lq_info[i].is_fat, 2551 lq_sta->lq_info[i].is_fat,
2615 lq_sta->lq_info[i].is_dup, 2552 lq_sta->lq_info[i].is_dup,
2616 lq_sta->lq_info[i].current_rate.rate_n_flags); 2553 lq_sta->lq_info[i].current_rate);
2617 for (j = 0; j < IWL_RATE_COUNT; j++) { 2554 for (j = 0; j < IWL_RATE_COUNT; j++) {
2618 desc += sprintf(buff+desc, 2555 desc += sprintf(buff+desc,
2619 "counter=%d success=%d %%=%d\n", 2556 "counter=%d success=%d %%=%d\n",
@@ -2640,11 +2577,9 @@ static void rs_add_debugfs(void *priv, void *priv_sta,
2640 lq_sta->rs_sta_dbgfs_stats_table_file = 2577 lq_sta->rs_sta_dbgfs_stats_table_file =
2641 debugfs_create_file("rate_stats_table", 0600, dir, 2578 debugfs_create_file("rate_stats_table", 0600, dir,
2642 lq_sta, &rs_sta_dbgfs_stats_table_ops); 2579 lq_sta, &rs_sta_dbgfs_stats_table_ops);
2643#ifdef CONFIG_IWL4965_HT
2644 lq_sta->rs_sta_dbgfs_tx_agg_tid_en_file = 2580 lq_sta->rs_sta_dbgfs_tx_agg_tid_en_file =
2645 debugfs_create_u8("tx_agg_tid_enable", 0600, dir, 2581 debugfs_create_u8("tx_agg_tid_enable", 0600, dir,
2646 &lq_sta->tx_agg_tid_en); 2582 &lq_sta->tx_agg_tid_en);
2647#endif
2648 2583
2649} 2584}
2650 2585
@@ -2653,9 +2588,7 @@ static void rs_remove_debugfs(void *priv, void *priv_sta)
2653 struct iwl4965_lq_sta *lq_sta = priv_sta; 2588 struct iwl4965_lq_sta *lq_sta = priv_sta;
2654 debugfs_remove(lq_sta->rs_sta_dbgfs_scale_table_file); 2589 debugfs_remove(lq_sta->rs_sta_dbgfs_scale_table_file);
2655 debugfs_remove(lq_sta->rs_sta_dbgfs_stats_table_file); 2590 debugfs_remove(lq_sta->rs_sta_dbgfs_stats_table_file);
2656#ifdef CONFIG_IWL4965_HT
2657 debugfs_remove(lq_sta->rs_sta_dbgfs_tx_agg_tid_en_file); 2591 debugfs_remove(lq_sta->rs_sta_dbgfs_tx_agg_tid_en_file);
2658#endif
2659} 2592}
2660#endif 2593#endif
2661 2594
@@ -2703,7 +2636,7 @@ int iwl4965_fill_rs_info(struct ieee80211_hw *hw, char *buf, u8 sta_id)
2703 lq_sta = (void *)sta->rate_ctrl_priv; 2636 lq_sta = (void *)sta->rate_ctrl_priv;
2704 2637
2705 lq_type = lq_sta->lq_info[lq_sta->active_tbl].lq_type; 2638 lq_type = lq_sta->lq_info[lq_sta->active_tbl].lq_type;
2706 antenna = lq_sta->lq_info[lq_sta->active_tbl].antenna_type; 2639 antenna = lq_sta->lq_info[lq_sta->active_tbl].ant_type;
2707 2640
2708 if (is_legacy(lq_type)) 2641 if (is_legacy(lq_type))
2709 i = IWL_RATE_54M_INDEX; 2642 i = IWL_RATE_54M_INDEX;
@@ -2715,7 +2648,7 @@ int iwl4965_fill_rs_info(struct ieee80211_hw *hw, char *buf, u8 sta_id)
2715 int active = lq_sta->active_tbl; 2648 int active = lq_sta->active_tbl;
2716 2649
2717 cnt += 2650 cnt +=
2718 sprintf(&buf[cnt], " %2dMbs: ", iwl4965_rates[i].ieee / 2); 2651 sprintf(&buf[cnt], " %2dMbs: ", iwl_rates[i].ieee / 2);
2719 2652
2720 mask = (1ULL << (IWL_RATE_MAX_WINDOW - 1)); 2653 mask = (1ULL << (IWL_RATE_MAX_WINDOW - 1));
2721 for (j = 0; j < IWL_RATE_MAX_WINDOW; j++, mask >>= 1) 2654 for (j = 0; j < IWL_RATE_MAX_WINDOW; j++, mask >>= 1)
@@ -2726,7 +2659,7 @@ int iwl4965_fill_rs_info(struct ieee80211_hw *hw, char *buf, u8 sta_id)
2726 samples += lq_sta->lq_info[active].win[i].counter; 2659 samples += lq_sta->lq_info[active].win[i].counter;
2727 good += lq_sta->lq_info[active].win[i].success_counter; 2660 good += lq_sta->lq_info[active].win[i].success_counter;
2728 success += lq_sta->lq_info[active].win[i].success_counter * 2661 success += lq_sta->lq_info[active].win[i].success_counter *
2729 iwl4965_rates[i].ieee; 2662 iwl_rates[i].ieee;
2730 2663
2731 if (lq_sta->lq_info[active].win[i].stamp) { 2664 if (lq_sta->lq_info[active].win[i].stamp) {
2732 int delta = 2665 int delta =
@@ -2746,10 +2679,11 @@ int iwl4965_fill_rs_info(struct ieee80211_hw *hw, char *buf, u8 sta_id)
2746 i = j; 2679 i = j;
2747 } 2680 }
2748 2681
2749 /* Display the average rate of all samples taken. 2682 /*
2750 * 2683 * Display the average rate of all samples taken.
2751 * NOTE: We multiply # of samples by 2 since the IEEE measurement 2684 * NOTE: We multiply # of samples by 2 since the IEEE measurement
2752 * added from iwl4965_rates is actually 2X the rate */ 2685 * added from iwl_rates is actually 2X the rate.
2686 */
2753 if (samples) 2687 if (samples)
2754 cnt += sprintf(&buf[cnt], 2688 cnt += sprintf(&buf[cnt],
2755 "\nAverage rate is %3d.%02dMbs over last %4dms\n" 2689 "\nAverage rate is %3d.%02dMbs over last %4dms\n"
@@ -2767,13 +2701,6 @@ int iwl4965_fill_rs_info(struct ieee80211_hw *hw, char *buf, u8 sta_id)
2767 return cnt; 2701 return cnt;
2768} 2702}
2769 2703
2770void iwl4965_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id)
2771{
2772 struct iwl_priv *priv = hw->priv;
2773
2774 priv->lq_mngr.lq_ready = 1;
2775}
2776
2777int iwl4965_rate_control_register(void) 2704int iwl4965_rate_control_register(void)
2778{ 2705{
2779 return ieee80211_rate_control_register(&rs_ops); 2706 return ieee80211_rate_control_register(&rs_ops);
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-rs.h b/drivers/net/wireless/iwlwifi/iwl-4965-rs.h
index 866e378aa385..9b9972885aa5 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-rs.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-rs.h
@@ -27,12 +27,13 @@
27#ifndef __iwl_4965_rs_h__ 27#ifndef __iwl_4965_rs_h__
28#define __iwl_4965_rs_h__ 28#define __iwl_4965_rs_h__
29 29
30#include "iwl-4965.h" 30#include "iwl-dev.h"
31 31
32struct iwl4965_rate_info { 32struct iwl_rate_info {
33 u8 plcp; /* uCode API: IWL_RATE_6M_PLCP, etc. */ 33 u8 plcp; /* uCode API: IWL_RATE_6M_PLCP, etc. */
34 u8 plcp_siso; /* uCode API: IWL_RATE_SISO_6M_PLCP, etc. */ 34 u8 plcp_siso; /* uCode API: IWL_RATE_SISO_6M_PLCP, etc. */
35 u8 plcp_mimo; /* uCode API: IWL_RATE_MIMO_6M_PLCP, etc. */ 35 u8 plcp_mimo2; /* uCode API: IWL_RATE_MIMO2_6M_PLCP, etc. */
36 u8 plcp_mimo3; /* uCode API: IWL_RATE_MIMO3_6M_PLCP, etc. */
36 u8 ieee; /* MAC header: IWL_RATE_6M_IEEE, etc. */ 37 u8 ieee; /* MAC header: IWL_RATE_6M_IEEE, etc. */
37 u8 prev_ieee; /* previous rate in IEEE speeds */ 38 u8 prev_ieee; /* previous rate in IEEE speeds */
38 u8 next_ieee; /* next rate in IEEE speeds */ 39 u8 next_ieee; /* next rate in IEEE speeds */
@@ -44,7 +45,7 @@ struct iwl4965_rate_info {
44 45
45/* 46/*
46 * These serve as indexes into 47 * These serve as indexes into
47 * struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT]; 48 * struct iwl_rate_info iwl_rates[IWL_RATE_COUNT];
48 */ 49 */
49enum { 50enum {
50 IWL_RATE_1M_INDEX = 0, 51 IWL_RATE_1M_INDEX = 0,
@@ -60,9 +61,9 @@ enum {
60 IWL_RATE_48M_INDEX, 61 IWL_RATE_48M_INDEX,
61 IWL_RATE_54M_INDEX, 62 IWL_RATE_54M_INDEX,
62 IWL_RATE_60M_INDEX, 63 IWL_RATE_60M_INDEX,
63 IWL_RATE_COUNT, 64 IWL_RATE_COUNT, /*FIXME:RS:change to IWL_RATE_INDEX_COUNT,*/
64 IWL_RATE_INVM_INDEX = IWL_RATE_COUNT, 65 IWL_RATE_INVM_INDEX = IWL_RATE_COUNT,
65 IWL_RATE_INVALID = IWL_RATE_INVM_INDEX 66 IWL_RATE_INVALID = IWL_RATE_COUNT,
66}; 67};
67 68
68enum { 69enum {
@@ -97,11 +98,13 @@ enum {
97 IWL_RATE_36M_PLCP = 11, 98 IWL_RATE_36M_PLCP = 11,
98 IWL_RATE_48M_PLCP = 1, 99 IWL_RATE_48M_PLCP = 1,
99 IWL_RATE_54M_PLCP = 3, 100 IWL_RATE_54M_PLCP = 3,
100 IWL_RATE_60M_PLCP = 3, 101 IWL_RATE_60M_PLCP = 3,/*FIXME:RS:should be removed*/
101 IWL_RATE_1M_PLCP = 10, 102 IWL_RATE_1M_PLCP = 10,
102 IWL_RATE_2M_PLCP = 20, 103 IWL_RATE_2M_PLCP = 20,
103 IWL_RATE_5M_PLCP = 55, 104 IWL_RATE_5M_PLCP = 55,
104 IWL_RATE_11M_PLCP = 110, 105 IWL_RATE_11M_PLCP = 110,
106 /*FIXME:RS:change to IWL_RATE_LEGACY_??M_PLCP */
107 /*FIXME:RS:add IWL_RATE_LEGACY_INVM_PLCP = 0,*/
105}; 108};
106 109
107/* 4965 uCode API values for OFDM high-throughput (HT) bit rates */ 110/* 4965 uCode API values for OFDM high-throughput (HT) bit rates */
@@ -114,16 +117,25 @@ enum {
114 IWL_RATE_SISO_48M_PLCP = 5, 117 IWL_RATE_SISO_48M_PLCP = 5,
115 IWL_RATE_SISO_54M_PLCP = 6, 118 IWL_RATE_SISO_54M_PLCP = 6,
116 IWL_RATE_SISO_60M_PLCP = 7, 119 IWL_RATE_SISO_60M_PLCP = 7,
117 IWL_RATE_MIMO_6M_PLCP = 0x8, 120 IWL_RATE_MIMO2_6M_PLCP = 0x8,
118 IWL_RATE_MIMO_12M_PLCP = 0x9, 121 IWL_RATE_MIMO2_12M_PLCP = 0x9,
119 IWL_RATE_MIMO_18M_PLCP = 0xa, 122 IWL_RATE_MIMO2_18M_PLCP = 0xa,
120 IWL_RATE_MIMO_24M_PLCP = 0xb, 123 IWL_RATE_MIMO2_24M_PLCP = 0xb,
121 IWL_RATE_MIMO_36M_PLCP = 0xc, 124 IWL_RATE_MIMO2_36M_PLCP = 0xc,
122 IWL_RATE_MIMO_48M_PLCP = 0xd, 125 IWL_RATE_MIMO2_48M_PLCP = 0xd,
123 IWL_RATE_MIMO_54M_PLCP = 0xe, 126 IWL_RATE_MIMO2_54M_PLCP = 0xe,
124 IWL_RATE_MIMO_60M_PLCP = 0xf, 127 IWL_RATE_MIMO2_60M_PLCP = 0xf,
128 IWL_RATE_MIMO3_6M_PLCP = 0x10,
129 IWL_RATE_MIMO3_12M_PLCP = 0x11,
130 IWL_RATE_MIMO3_18M_PLCP = 0x12,
131 IWL_RATE_MIMO3_24M_PLCP = 0x13,
132 IWL_RATE_MIMO3_36M_PLCP = 0x14,
133 IWL_RATE_MIMO3_48M_PLCP = 0x15,
134 IWL_RATE_MIMO3_54M_PLCP = 0x16,
135 IWL_RATE_MIMO3_60M_PLCP = 0x17,
125 IWL_RATE_SISO_INVM_PLCP, 136 IWL_RATE_SISO_INVM_PLCP,
126 IWL_RATE_MIMO_INVM_PLCP = IWL_RATE_SISO_INVM_PLCP, 137 IWL_RATE_MIMO2_INVM_PLCP = IWL_RATE_SISO_INVM_PLCP,
138 IWL_RATE_MIMO3_INVM_PLCP = IWL_RATE_SISO_INVM_PLCP,
127}; 139};
128 140
129/* MAC header values for bit rates */ 141/* MAC header values for bit rates */
@@ -196,11 +208,11 @@ enum {
196/* possible actions when in legacy mode */ 208/* possible actions when in legacy mode */
197#define IWL_LEGACY_SWITCH_ANTENNA 0 209#define IWL_LEGACY_SWITCH_ANTENNA 0
198#define IWL_LEGACY_SWITCH_SISO 1 210#define IWL_LEGACY_SWITCH_SISO 1
199#define IWL_LEGACY_SWITCH_MIMO 2 211#define IWL_LEGACY_SWITCH_MIMO2 2
200 212
201/* possible actions when in siso mode */ 213/* possible actions when in siso mode */
202#define IWL_SISO_SWITCH_ANTENNA 0 214#define IWL_SISO_SWITCH_ANTENNA 0
203#define IWL_SISO_SWITCH_MIMO 1 215#define IWL_SISO_SWITCH_MIMO2 1
204#define IWL_SISO_SWITCH_GI 2 216#define IWL_SISO_SWITCH_GI 2
205 217
206/* possible actions when in mimo mode */ 218/* possible actions when in mimo mode */
@@ -208,6 +220,10 @@ enum {
208#define IWL_MIMO_SWITCH_ANTENNA_B 1 220#define IWL_MIMO_SWITCH_ANTENNA_B 1
209#define IWL_MIMO_SWITCH_GI 2 221#define IWL_MIMO_SWITCH_GI 2
210 222
223/*FIXME:RS:separate MIMO2/3 transitions*/
224
225/*FIXME:RS:add posible acctions for MIMO3*/
226
211#define IWL_ACTION_LIMIT 3 /* # possible actions */ 227#define IWL_ACTION_LIMIT 3 /* # possible actions */
212 228
213#define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */ 229#define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */
@@ -224,43 +240,52 @@ enum {
224#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING) 240#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
225#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y)) 241#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
226 242
227extern const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT]; 243extern const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT];
228 244
229enum iwl4965_table_type { 245enum iwl_table_type {
230 LQ_NONE, 246 LQ_NONE,
231 LQ_G, /* legacy types */ 247 LQ_G, /* legacy types */
232 LQ_A, 248 LQ_A,
233 LQ_SISO, /* high-throughput types */ 249 LQ_SISO, /* high-throughput types */
234 LQ_MIMO, 250 LQ_MIMO2,
251 LQ_MIMO3,
235 LQ_MAX, 252 LQ_MAX,
236}; 253};
237 254
238#define is_legacy(tbl) (((tbl) == LQ_G) || ((tbl) == LQ_A)) 255#define is_legacy(tbl) (((tbl) == LQ_G) || ((tbl) == LQ_A))
239#define is_siso(tbl) (((tbl) == LQ_SISO)) 256#define is_siso(tbl) ((tbl) == LQ_SISO)
240#define is_mimo(tbl) (((tbl) == LQ_MIMO)) 257#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
258#define is_mimo3(tbl) ((tbl) == LQ_MIMO3)
259#define is_mimo(tbl) (is_mimo2(tbl) || is_mimo3(tbl))
241#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl)) 260#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
242#define is_a_band(tbl) (((tbl) == LQ_A)) 261#define is_a_band(tbl) ((tbl) == LQ_A)
243#define is_g_and(tbl) (((tbl) == LQ_G)) 262#define is_g_and(tbl) ((tbl) == LQ_G)
244 263
245/* 4965 has 2 antennas/chains for Tx (but 3 for Rx) */ 264#define ANT_NONE 0x0
246enum iwl4965_antenna_type { 265#define ANT_A BIT(0)
247 ANT_NONE, 266#define ANT_B BIT(1)
248 ANT_MAIN, 267#define ANT_AB (ANT_A | ANT_B)
249 ANT_AUX, 268#define ANT_C BIT(2)
250 ANT_BOTH, 269#define ANT_AC (ANT_A | ANT_C)
251}; 270#define ANT_BC (ANT_B | ANT_C)
271#define ANT_ABC (ANT_AB | ANT_C)
272
273static inline u8 num_of_ant(u8 mask)
274{
275 return !!((mask) & ANT_A) +
276 !!((mask) & ANT_B) +
277 !!((mask) & ANT_C);
278}
252 279
253static inline u8 iwl4965_get_prev_ieee_rate(u8 rate_index) 280static inline u8 iwl4965_get_prev_ieee_rate(u8 rate_index)
254{ 281{
255 u8 rate = iwl4965_rates[rate_index].prev_ieee; 282 u8 rate = iwl_rates[rate_index].prev_ieee;
256 283
257 if (rate == IWL_RATE_INVALID) 284 if (rate == IWL_RATE_INVALID)
258 rate = rate_index; 285 rate = rate_index;
259 return rate; 286 return rate;
260} 287}
261 288
262extern int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags);
263
264/** 289/**
265 * iwl4965_fill_rs_info - Fill an output text buffer with the rate representation 290 * iwl4965_fill_rs_info - Fill an output text buffer with the rate representation
266 * 291 *
@@ -271,14 +296,6 @@ extern int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags);
271extern int iwl4965_fill_rs_info(struct ieee80211_hw *, char *buf, u8 sta_id); 296extern int iwl4965_fill_rs_info(struct ieee80211_hw *, char *buf, u8 sta_id);
272 297
273/** 298/**
274 * iwl4965_rate_scale_init - Initialize the rate scale table based on assoc info
275 *
276 * The specific throughput table used is based on the type of network
277 * the associated with, including A, B, G, and G w/ TGG protection
278 */
279extern void iwl4965_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
280
281/**
282 * iwl4965_rate_control_register - Register the rate control algorithm callbacks 299 * iwl4965_rate_control_register - Register the rate control algorithm callbacks
283 * 300 *
284 * Since the rate control algorithm is hardware specific, there is no need 301 * Since the rate control algorithm is hardware specific, there is no need
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index de330ae0ca95..9afecb813716 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -39,81 +39,33 @@
39#include <asm/unaligned.h> 39#include <asm/unaligned.h>
40 40
41#include "iwl-eeprom.h" 41#include "iwl-eeprom.h"
42#include "iwl-4965.h" 42#include "iwl-dev.h"
43#include "iwl-core.h" 43#include "iwl-core.h"
44#include "iwl-io.h" 44#include "iwl-io.h"
45#include "iwl-helpers.h" 45#include "iwl-helpers.h"
46#include "iwl-calib.h"
47#include "iwl-sta.h"
48
49static int iwl4965_send_tx_power(struct iwl_priv *priv);
50static int iwl4965_hw_get_temperature(const struct iwl_priv *priv);
51
52/* Change firmware file name, using "-" and incrementing number,
53 * *only* when uCode interface or architecture changes so that it
54 * is not compatible with earlier drivers.
55 * This number will also appear in << 8 position of 1st dword of uCode file */
56#define IWL4965_UCODE_API "-2"
57
46 58
47/* module parameters */ 59/* module parameters */
48static struct iwl_mod_params iwl4965_mod_params = { 60static struct iwl_mod_params iwl4965_mod_params = {
49 .num_of_queues = IWL4965_MAX_NUM_QUEUES, 61 .num_of_queues = IWL49_NUM_QUEUES,
62 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
50 .enable_qos = 1, 63 .enable_qos = 1,
51 .amsdu_size_8K = 1, 64 .amsdu_size_8K = 1,
65 .restart_fw = 1,
52 /* the rest are 0 by default */ 66 /* the rest are 0 by default */
53}; 67};
54 68
55static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
56
57#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
58 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
59 IWL_RATE_SISO_##s##M_PLCP, \
60 IWL_RATE_MIMO_##s##M_PLCP, \
61 IWL_RATE_##r##M_IEEE, \
62 IWL_RATE_##ip##M_INDEX, \
63 IWL_RATE_##in##M_INDEX, \
64 IWL_RATE_##rp##M_INDEX, \
65 IWL_RATE_##rn##M_INDEX, \
66 IWL_RATE_##pp##M_INDEX, \
67 IWL_RATE_##np##M_INDEX }
68
69/*
70 * Parameter order:
71 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
72 *
73 * If there isn't a valid next or previous rate then INV is used which
74 * maps to IWL_RATE_INVALID
75 *
76 */
77const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
78 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
79 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
80 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
81 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
82 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
83 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
84 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
85 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
86 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
87 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
88 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
89 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
90 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
91};
92
93#ifdef CONFIG_IWL4965_HT
94
95static const u16 default_tid_to_tx_fifo[] = {
96 IWL_TX_FIFO_AC1,
97 IWL_TX_FIFO_AC0,
98 IWL_TX_FIFO_AC0,
99 IWL_TX_FIFO_AC1,
100 IWL_TX_FIFO_AC2,
101 IWL_TX_FIFO_AC2,
102 IWL_TX_FIFO_AC3,
103 IWL_TX_FIFO_AC3,
104 IWL_TX_FIFO_NONE,
105 IWL_TX_FIFO_NONE,
106 IWL_TX_FIFO_NONE,
107 IWL_TX_FIFO_NONE,
108 IWL_TX_FIFO_NONE,
109 IWL_TX_FIFO_NONE,
110 IWL_TX_FIFO_NONE,
111 IWL_TX_FIFO_NONE,
112 IWL_TX_FIFO_AC3
113};
114
115#endif /*CONFIG_IWL4965_HT */
116
117/* check contents of special bootstrap uCode SRAM */ 69/* check contents of special bootstrap uCode SRAM */
118static int iwl4965_verify_bsm(struct iwl_priv *priv) 70static int iwl4965_verify_bsm(struct iwl_priv *priv)
119{ 71{
@@ -192,15 +144,18 @@ static int iwl4965_load_bsm(struct iwl_priv *priv)
192 144
193 IWL_DEBUG_INFO("Begin load bsm\n"); 145 IWL_DEBUG_INFO("Begin load bsm\n");
194 146
147 priv->ucode_type = UCODE_RT;
148
195 /* make sure bootstrap program is no larger than BSM's SRAM size */ 149 /* make sure bootstrap program is no larger than BSM's SRAM size */
196 if (len > IWL_MAX_BSM_SIZE) 150 if (len > IWL_MAX_BSM_SIZE)
197 return -EINVAL; 151 return -EINVAL;
198 152
199 /* Tell bootstrap uCode where to find the "Initialize" uCode 153 /* Tell bootstrap uCode where to find the "Initialize" uCode
200 * in host DRAM ... host DRAM physical address bits 35:4 for 4965. 154 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
201 * NOTE: iwl4965_initialize_alive_start() will replace these values, 155 * NOTE: iwl_init_alive_start() will replace these values,
202 * after the "initialize" uCode has run, to point to 156 * after the "initialize" uCode has run, to point to
203 * runtime/protocol instructions and backup data cache. */ 157 * runtime/protocol instructions and backup data cache.
158 */
204 pinst = priv->ucode_init.p_addr >> 4; 159 pinst = priv->ucode_init.p_addr >> 4;
205 pdata = priv->ucode_init_data.p_addr >> 4; 160 pdata = priv->ucode_init_data.p_addr >> 4;
206 inst_len = priv->ucode_init.len; 161 inst_len = priv->ucode_init.len;
@@ -259,271 +214,134 @@ static int iwl4965_load_bsm(struct iwl_priv *priv)
259 return 0; 214 return 0;
260} 215}
261 216
262static int iwl4965_init_drv(struct iwl_priv *priv) 217/**
218 * iwl4965_set_ucode_ptrs - Set uCode address location
219 *
220 * Tell initialization uCode where to find runtime uCode.
221 *
222 * BSM registers initially contain pointers to initialization uCode.
223 * We need to replace them to load runtime uCode inst and data,
224 * and to save runtime data when powering down.
225 */
226static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
263{ 227{
264 int ret; 228 dma_addr_t pinst;
265 int i; 229 dma_addr_t pdata;
266 230 unsigned long flags;
267 priv->antenna = (enum iwl4965_antenna)priv->cfg->mod_params->antenna; 231 int ret = 0;
268 priv->retry_rate = 1;
269 priv->ibss_beacon = NULL;
270
271 spin_lock_init(&priv->lock);
272 spin_lock_init(&priv->power_data.lock);
273 spin_lock_init(&priv->sta_lock);
274 spin_lock_init(&priv->hcmd_lock);
275 spin_lock_init(&priv->lq_mngr.lock);
276
277 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
278 sizeof(struct iwl4965_shared),
279 &priv->shared_phys);
280
281 if (!priv->shared_virt) {
282 ret = -ENOMEM;
283 goto err;
284 }
285
286 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
287
288
289 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
290 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
291
292 INIT_LIST_HEAD(&priv->free_frames);
293
294 mutex_init(&priv->mutex);
295
296 /* Clear the driver's (not device's) station table */
297 iwlcore_clear_stations_table(priv);
298
299 priv->data_retry_limit = -1;
300 priv->ieee_channels = NULL;
301 priv->ieee_rates = NULL;
302 priv->band = IEEE80211_BAND_2GHZ;
303
304 priv->iw_mode = IEEE80211_IF_TYPE_STA;
305
306 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
307 priv->valid_antenna = 0x7; /* assume all 3 connected */
308 priv->ps_mode = IWL_MIMO_PS_NONE;
309
310 /* Choose which receivers/antennas to use */
311 iwl4965_set_rxon_chain(priv);
312
313 iwlcore_reset_qos(priv);
314
315 priv->qos_data.qos_active = 0;
316 priv->qos_data.qos_cap.val = 0;
317
318 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
319 232
320 priv->rates_mask = IWL_RATES_MASK; 233 /* bits 35:4 for 4965 */
321 /* If power management is turned on, default to AC mode */ 234 pinst = priv->ucode_code.p_addr >> 4;
322 priv->power_mode = IWL_POWER_AC; 235 pdata = priv->ucode_data_backup.p_addr >> 4;
323 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
324 236
325 ret = iwl_init_channel_map(priv); 237 spin_lock_irqsave(&priv->lock, flags);
238 ret = iwl_grab_nic_access(priv);
326 if (ret) { 239 if (ret) {
327 IWL_ERROR("initializing regulatory failed: %d\n", ret); 240 spin_unlock_irqrestore(&priv->lock, flags);
328 goto err; 241 return ret;
329 } 242 }
330 243
331 ret = iwl4965_init_geos(priv); 244 /* Tell bootstrap uCode where to find image to load */
332 if (ret) { 245 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
333 IWL_ERROR("initializing geos failed: %d\n", ret); 246 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
334 goto err_free_channel_map; 247 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
335 } 248 priv->ucode_data.len);
336 249
337 ret = ieee80211_register_hw(priv->hw); 250 /* Inst bytecount must be last to set up, bit 31 signals uCode
338 if (ret) { 251 * that all new ptr/size info is in place */
339 IWL_ERROR("Failed to register network device (error %d)\n", 252 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
340 ret); 253 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
341 goto err_free_geos; 254 iwl_release_nic_access(priv);
342 }
343 255
344 priv->hw->conf.beacon_int = 100; 256 spin_unlock_irqrestore(&priv->lock, flags);
345 priv->mac80211_registered = 1;
346 257
347 return 0; 258 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
348 259
349err_free_geos:
350 iwl4965_free_geos(priv);
351err_free_channel_map:
352 iwl_free_channel_map(priv);
353err:
354 return ret; 260 return ret;
355} 261}
356 262
357static int is_fat_channel(__le32 rxon_flags) 263/**
358{ 264 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
359 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) || 265 *
360 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK); 266 * Called after REPLY_ALIVE notification received from "initialize" uCode.
361} 267 *
362 268 * The 4965 "initialize" ALIVE reply contains calibration data for:
363static u8 is_single_stream(struct iwl_priv *priv) 269 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
364{ 270 * (3945 does not contain this data).
365#ifdef CONFIG_IWL4965_HT 271 *
366 if (!priv->current_ht_config.is_ht || 272 * Tell "initialize" uCode to go ahead and load the runtime uCode.
367 (priv->current_ht_config.supp_mcs_set[1] == 0) || 273*/
368 (priv->ps_mode == IWL_MIMO_PS_STATIC)) 274static void iwl4965_init_alive_start(struct iwl_priv *priv)
369 return 1; 275{
370#else 276 /* Check alive response for "valid" sign from uCode */
371 return 1; 277 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
372#endif /*CONFIG_IWL4965_HT */ 278 /* We had an error bringing up the hardware, so take it
373 return 0; 279 * all the way back down so we can try again */
374} 280 IWL_DEBUG_INFO("Initialize Alive failed.\n");
375 281 goto restart;
376int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags) 282 }
377{ 283
378 int idx = 0; 284 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
379 285 * This is a paranoid check, because we would not have gotten the
380 /* 4965 HT rate format */ 286 * "initialize" alive if code weren't properly loaded. */
381 if (rate_n_flags & RATE_MCS_HT_MSK) { 287 if (iwl_verify_ucode(priv)) {
382 idx = (rate_n_flags & 0xff); 288 /* Runtime instruction load was bad;
383 289 * take it all the way back down so we can try again */
384 if (idx >= IWL_RATE_MIMO_6M_PLCP) 290 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
385 idx = idx - IWL_RATE_MIMO_6M_PLCP; 291 goto restart;
386 292 }
387 idx += IWL_FIRST_OFDM_RATE; 293
388 /* skip 9M not supported in ht*/ 294 /* Calculate temperature */
389 if (idx >= IWL_RATE_9M_INDEX) 295 priv->temperature = iwl4965_hw_get_temperature(priv);
390 idx += 1; 296
391 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE)) 297 /* Send pointers to protocol/runtime uCode image ... init code will
392 return idx; 298 * load and launch runtime uCode, which will send us another "Alive"
393 299 * notification. */
394 /* 4965 legacy rate format, search for match in table */ 300 IWL_DEBUG_INFO("Initialization Alive received.\n");
395 } else { 301 if (iwl4965_set_ucode_ptrs(priv)) {
396 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++) 302 /* Runtime instruction load won't happen;
397 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF)) 303 * take it all the way back down so we can try again */
398 return idx; 304 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
305 goto restart;
399 } 306 }
307 return;
400 308
401 return -1; 309restart:
310 queue_work(priv->workqueue, &priv->restart);
402} 311}
403 312
404/** 313static int is_fat_channel(__le32 rxon_flags)
405 * translate ucode response to mac80211 tx status control values
406 */
407void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
408 struct ieee80211_tx_control *control)
409{ 314{
410 int rate_index; 315 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
411 316 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
412 control->antenna_sel_tx =
413 ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_POS);
414 if (rate_n_flags & RATE_MCS_HT_MSK)
415 control->flags |= IEEE80211_TXCTL_OFDM_HT;
416 if (rate_n_flags & RATE_MCS_GF_MSK)
417 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
418 if (rate_n_flags & RATE_MCS_FAT_MSK)
419 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
420 if (rate_n_flags & RATE_MCS_DUP_MSK)
421 control->flags |= IEEE80211_TXCTL_DUP_DATA;
422 if (rate_n_flags & RATE_MCS_SGI_MSK)
423 control->flags |= IEEE80211_TXCTL_SHORT_GI;
424 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
425 * IEEE80211_BAND_2GHZ band as it contains all the rates */
426 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
427 if (rate_index == -1)
428 control->tx_rate = NULL;
429 else
430 control->tx_rate =
431 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
432} 317}
433 318
434/* 319/*
435 * Determine how many receiver/antenna chains to use. 320 * EEPROM handlers
436 * More provides better reception via diversity. Fewer saves power.
437 * MIMO (dual stream) requires at least 2, but works better with 3.
438 * This does not determine *which* chains to use, just how many.
439 */ 321 */
440static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
441 u8 *idle_state, u8 *rx_state)
442{
443 u8 is_single = is_single_stream(priv);
444 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
445
446 /* # of Rx chains to use when expecting MIMO. */
447 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
448 *rx_state = 2;
449 else
450 *rx_state = 3;
451
452 /* # Rx chains when idling and maybe trying to save power */
453 switch (priv->ps_mode) {
454 case IWL_MIMO_PS_STATIC:
455 case IWL_MIMO_PS_DYNAMIC:
456 *idle_state = (is_cam) ? 2 : 1;
457 break;
458 case IWL_MIMO_PS_NONE:
459 *idle_state = (is_cam) ? *rx_state : 1;
460 break;
461 default:
462 *idle_state = 1;
463 break;
464 }
465 322
466 return 0; 323static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
467}
468
469int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
470{ 324{
471 int rc; 325 u16 eeprom_ver;
472 unsigned long flags; 326 u16 calib_ver;
473 327
474 spin_lock_irqsave(&priv->lock, flags); 328 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
475 rc = iwl_grab_nic_access(priv);
476 if (rc) {
477 spin_unlock_irqrestore(&priv->lock, flags);
478 return rc;
479 }
480 329
481 /* stop Rx DMA */ 330 calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
482 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
483 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
484 (1 << 24), 1000);
485 if (rc < 0)
486 IWL_ERROR("Can't stop Rx DMA.\n");
487 331
488 iwl_release_nic_access(priv); 332 if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
489 spin_unlock_irqrestore(&priv->lock, flags); 333 calib_ver < EEPROM_4965_TX_POWER_VERSION)
334 goto err;
490 335
491 return 0; 336 return 0;
492} 337err:
493 338 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
494u8 iwl4965_hw_find_station(struct iwl_priv *priv, const u8 *addr) 339 eeprom_ver, EEPROM_4965_EEPROM_VERSION,
495{ 340 calib_ver, EEPROM_4965_TX_POWER_VERSION);
496 int i; 341 return -EINVAL;
497 int start = 0;
498 int ret = IWL_INVALID_STATION;
499 unsigned long flags;
500 DECLARE_MAC_BUF(mac);
501
502 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
503 (priv->iw_mode == IEEE80211_IF_TYPE_AP))
504 start = IWL_STA_ID;
505
506 if (is_broadcast_ether_addr(addr))
507 return priv->hw_params.bcast_sta_id;
508
509 spin_lock_irqsave(&priv->sta_lock, flags);
510 for (i = start; i < priv->hw_params.max_stations; i++)
511 if ((priv->stations[i].used) &&
512 (!compare_ether_addr
513 (priv->stations[i].sta.sta.addr, addr))) {
514 ret = i;
515 goto out;
516 }
517
518 IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
519 print_mac(mac, addr), priv->num_stations);
520 342
521 out:
522 spin_unlock_irqrestore(&priv->sta_lock, flags);
523 return ret;
524} 343}
525 344int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
526static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
527{ 345{
528 int ret; 346 int ret;
529 unsigned long flags; 347 unsigned long flags;
@@ -535,340 +353,130 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
535 return ret; 353 return ret;
536 } 354 }
537 355
538 if (!pwr_max) { 356 if (src == IWL_PWR_SRC_VAUX) {
539 u32 val; 357 u32 val;
540
541 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE, 358 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
542 &val); 359 &val);
543 360
544 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) 361 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
545 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 362 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
546 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 363 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
547 ~APMG_PS_CTRL_MSK_PWR_SRC); 364 ~APMG_PS_CTRL_MSK_PWR_SRC);
548 } else 365 }
366 } else {
549 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 367 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
550 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 368 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
551 ~APMG_PS_CTRL_MSK_PWR_SRC); 369 ~APMG_PS_CTRL_MSK_PWR_SRC);
552
553 iwl_release_nic_access(priv);
554 spin_unlock_irqrestore(&priv->lock, flags);
555
556 return ret;
557}
558
559static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
560{
561 int ret;
562 unsigned long flags;
563 unsigned int rb_size;
564
565 spin_lock_irqsave(&priv->lock, flags);
566 ret = iwl_grab_nic_access(priv);
567 if (ret) {
568 spin_unlock_irqrestore(&priv->lock, flags);
569 return ret;
570 } 370 }
571 371
572 if (priv->cfg->mod_params->amsdu_size_8K)
573 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
574 else
575 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
576
577 /* Stop Rx DMA */
578 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
579
580 /* Reset driver's Rx queue write index */
581 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
582
583 /* Tell device where to find RBD circular buffer in DRAM */
584 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
585 rxq->dma_addr >> 8);
586
587 /* Tell device where in DRAM to update its Rx status */
588 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
589 (priv->shared_phys +
590 offsetof(struct iwl4965_shared, rb_closed)) >> 4);
591
592 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
593 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
594 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
595 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
596 rb_size |
597 /* 0x10 << 4 | */
598 (RX_QUEUE_SIZE_LOG <<
599 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
600
601 /*
602 * iwl_write32(priv,CSR_INT_COAL_REG,0);
603 */
604
605 iwl_release_nic_access(priv);
606 spin_unlock_irqrestore(&priv->lock, flags);
607
608 return 0;
609}
610
611/* Tell 4965 where to find the "keep warm" buffer */
612static int iwl4965_kw_init(struct iwl_priv *priv)
613{
614 unsigned long flags;
615 int rc;
616
617 spin_lock_irqsave(&priv->lock, flags);
618 rc = iwl_grab_nic_access(priv);
619 if (rc)
620 goto out;
621
622 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
623 priv->kw.dma_addr >> 4);
624 iwl_release_nic_access(priv); 372 iwl_release_nic_access(priv);
625out:
626 spin_unlock_irqrestore(&priv->lock, flags); 373 spin_unlock_irqrestore(&priv->lock, flags);
627 return rc;
628}
629
630static int iwl4965_kw_alloc(struct iwl_priv *priv)
631{
632 struct pci_dev *dev = priv->pci_dev;
633 struct iwl4965_kw *kw = &priv->kw;
634
635 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
636 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
637 if (!kw->v_addr)
638 return -ENOMEM;
639 374
640 return 0; 375 return ret;
641} 376}
642 377
643/** 378/*
644 * iwl4965_kw_free - Free the "keep warm" buffer 379 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
380 * must be called under priv->lock and mac access
645 */ 381 */
646static void iwl4965_kw_free(struct iwl_priv *priv) 382static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
647{ 383{
648 struct pci_dev *dev = priv->pci_dev; 384 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
649 struct iwl4965_kw *kw = &priv->kw;
650
651 if (kw->v_addr) {
652 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
653 memset(kw, 0, sizeof(*kw));
654 }
655} 385}
656 386
657/** 387static int iwl4965_apm_init(struct iwl_priv *priv)
658 * iwl4965_txq_ctx_reset - Reset TX queue context
659 * Destroys all DMA structures and initialise them again
660 *
661 * @param priv
662 * @return error code
663 */
664static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
665{ 388{
666 int rc = 0; 389 int ret = 0;
667 int txq_id, slots_num;
668 unsigned long flags;
669
670 iwl4965_kw_free(priv);
671
672 /* Free all tx/cmd queues and keep-warm buffer */
673 iwl4965_hw_txq_ctx_free(priv);
674
675 /* Alloc keep-warm buffer */
676 rc = iwl4965_kw_alloc(priv);
677 if (rc) {
678 IWL_ERROR("Keep Warm allocation failed");
679 goto error_kw;
680 }
681
682 spin_lock_irqsave(&priv->lock, flags);
683
684 rc = iwl_grab_nic_access(priv);
685 if (unlikely(rc)) {
686 IWL_ERROR("TX reset failed");
687 spin_unlock_irqrestore(&priv->lock, flags);
688 goto error_reset;
689 }
690
691 /* Turn off all Tx DMA channels */
692 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
693 iwl_release_nic_access(priv);
694 spin_unlock_irqrestore(&priv->lock, flags);
695
696 /* Tell 4965 where to find the keep-warm buffer */
697 rc = iwl4965_kw_init(priv);
698 if (rc) {
699 IWL_ERROR("kw_init failed\n");
700 goto error_reset;
701 }
702
703 /* Alloc and init all (default 16) Tx queues,
704 * including the command queue (#4) */
705 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
706 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
707 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
708 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
709 txq_id);
710 if (rc) {
711 IWL_ERROR("Tx %d queue init failed\n", txq_id);
712 goto error;
713 }
714 }
715
716 return rc;
717
718 error:
719 iwl4965_hw_txq_ctx_free(priv);
720 error_reset:
721 iwl4965_kw_free(priv);
722 error_kw:
723 return rc;
724}
725
726int iwl4965_hw_nic_init(struct iwl_priv *priv)
727{
728 int rc;
729 unsigned long flags;
730 struct iwl4965_rx_queue *rxq = &priv->rxq;
731 u8 rev_id;
732 u32 val;
733 u8 val_link;
734
735 iwl4965_power_init_handle(priv);
736 390
737 /* nic_init */ 391 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
738 spin_lock_irqsave(&priv->lock, flags); 392 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
739 393
394 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
740 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 395 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
741 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 396 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
742 397
398 /* set "initialization complete" bit to move adapter
399 * D0U* --> D0A* state */
743 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 400 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
744 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
745 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
746 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
747 if (rc < 0) {
748 spin_unlock_irqrestore(&priv->lock, flags);
749 IWL_DEBUG_INFO("Failed to init the card\n");
750 return rc;
751 }
752 401
753 rc = iwl_grab_nic_access(priv); 402 /* wait for clock stabilization */
754 if (rc) { 403 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
755 spin_unlock_irqrestore(&priv->lock, flags); 404 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
756 return rc; 405 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
406 if (ret < 0) {
407 IWL_DEBUG_INFO("Failed to init the card\n");
408 goto out;
757 } 409 }
758 410
759 iwl_read_prph(priv, APMG_CLK_CTRL_REG); 411 ret = iwl_grab_nic_access(priv);
412 if (ret)
413 goto out;
760 414
761 iwl_write_prph(priv, APMG_CLK_CTRL_REG, 415 /* enable DMA */
762 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT); 416 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
763 iwl_read_prph(priv, APMG_CLK_CTRL_REG); 417 APMG_CLK_VAL_BSM_CLK_RQT);
764 418
765 udelay(20); 419 udelay(20);
766 420
421 /* disable L1-Active */
767 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 422 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
768 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 423 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
769 424
770 iwl_release_nic_access(priv); 425 iwl_release_nic_access(priv);
771 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32); 426out:
772 spin_unlock_irqrestore(&priv->lock, flags); 427 return ret;
428}
773 429
774 /* Determine HW type */
775 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
776 if (rc)
777 return rc;
778 430
779 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id); 431static void iwl4965_nic_config(struct iwl_priv *priv)
432{
433 unsigned long flags;
434 u32 val;
435 u16 radio_cfg;
436 u8 val_link;
780 437
781 iwl4965_nic_set_pwr_src(priv, 1);
782 spin_lock_irqsave(&priv->lock, flags); 438 spin_lock_irqsave(&priv->lock, flags);
783 439
784 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) { 440 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
785 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val); 441 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
786 /* Enable No Snoop field */ 442 /* Enable No Snoop field */
787 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8, 443 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
788 val & ~(1 << 11)); 444 val & ~(1 << 11));
789 } 445 }
790 446
791 spin_unlock_irqrestore(&priv->lock, flags);
792
793 if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
794 IWL_ERROR("Older EEPROM detected! Aborting.\n");
795 return -EINVAL;
796 }
797
798 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link); 447 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
799 448
800 /* disable L1 entry -- workaround for pre-B1 */ 449 /* L1 is enabled by BIOS */
801 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02); 450 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
451 /* diable L0S disabled L1A enabled */
452 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
453 else
454 /* L0S enabled L1A disabled */
455 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
802 456
803 spin_lock_irqsave(&priv->lock, flags); 457 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
804 458
805 /* set CSR_HW_CONFIG_REG for uCode use */ 459 /* write radio config values to register */
460 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
461 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
462 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
463 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
464 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
806 465
466 /* set CSR_HW_CONFIG_REG for uCode use */
807 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 467 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
808 CSR49_HW_IF_CONFIG_REG_BIT_4965_R | 468 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
809 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI | 469 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
810 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
811 470
812 rc = iwl_grab_nic_access(priv); 471 priv->calib_info = (struct iwl_eeprom_calib_info *)
813 if (rc < 0) { 472 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
814 spin_unlock_irqrestore(&priv->lock, flags);
815 IWL_DEBUG_INFO("Failed to init the card\n");
816 return rc;
817 }
818 473
819 iwl_read_prph(priv, APMG_PS_CTRL_REG);
820 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
821 udelay(5);
822 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
823
824 iwl_release_nic_access(priv);
825 spin_unlock_irqrestore(&priv->lock, flags); 474 spin_unlock_irqrestore(&priv->lock, flags);
826
827 iwl4965_hw_card_show_info(priv);
828
829 /* end nic_init */
830
831 /* Allocate the RX queue, or reset if it is already allocated */
832 if (!rxq->bd) {
833 rc = iwl4965_rx_queue_alloc(priv);
834 if (rc) {
835 IWL_ERROR("Unable to initialize Rx queue\n");
836 return -ENOMEM;
837 }
838 } else
839 iwl4965_rx_queue_reset(priv, rxq);
840
841 iwl4965_rx_replenish(priv);
842
843 iwl4965_rx_init(priv, rxq);
844
845 spin_lock_irqsave(&priv->lock, flags);
846
847 rxq->need_update = 1;
848 iwl4965_rx_queue_update_write_ptr(priv, rxq);
849
850 spin_unlock_irqrestore(&priv->lock, flags);
851
852 /* Allocate and init all Tx and Command queues */
853 rc = iwl4965_txq_ctx_reset(priv);
854 if (rc)
855 return rc;
856
857 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
858 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
859
860 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
861 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
862
863 set_bit(STATUS_INIT, &priv->status);
864
865 return 0;
866} 475}
867 476
868int iwl4965_hw_nic_stop_master(struct iwl_priv *priv) 477static int iwl4965_apm_stop_master(struct iwl_priv *priv)
869{ 478{
870 int rc = 0; 479 int ret = 0;
871 u32 reg_val;
872 unsigned long flags; 480 unsigned long flags;
873 481
874 spin_lock_irqsave(&priv->lock, flags); 482 spin_lock_irqsave(&priv->lock, flags);
@@ -876,64 +484,24 @@ int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
876 /* set stop master bit */ 484 /* set stop master bit */
877 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 485 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
878 486
879 reg_val = iwl_read32(priv, CSR_GP_CNTRL); 487 ret = iwl_poll_bit(priv, CSR_RESET,
880
881 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
882 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
883 IWL_DEBUG_INFO("Card in power save, master is already "
884 "stopped\n");
885 else {
886 rc = iwl_poll_bit(priv, CSR_RESET,
887 CSR_RESET_REG_FLAG_MASTER_DISABLED, 488 CSR_RESET_REG_FLAG_MASTER_DISABLED,
888 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 489 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
889 if (rc < 0) { 490 if (ret < 0)
890 spin_unlock_irqrestore(&priv->lock, flags); 491 goto out;
891 return rc;
892 }
893 }
894 492
493out:
895 spin_unlock_irqrestore(&priv->lock, flags); 494 spin_unlock_irqrestore(&priv->lock, flags);
896 IWL_DEBUG_INFO("stop master\n"); 495 IWL_DEBUG_INFO("stop master\n");
897 496
898 return rc; 497 return ret;
899}
900
901/**
902 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
903 */
904void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
905{
906
907 int txq_id;
908 unsigned long flags;
909
910 /* Stop each Tx DMA channel, and wait for it to be idle */
911 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
912 spin_lock_irqsave(&priv->lock, flags);
913 if (iwl_grab_nic_access(priv)) {
914 spin_unlock_irqrestore(&priv->lock, flags);
915 continue;
916 }
917
918 iwl_write_direct32(priv,
919 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
920 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
921 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
922 (txq_id), 200);
923 iwl_release_nic_access(priv);
924 spin_unlock_irqrestore(&priv->lock, flags);
925 }
926
927 /* Deallocate memory for all Tx queues */
928 iwl4965_hw_txq_ctx_free(priv);
929} 498}
930 499
931int iwl4965_hw_nic_reset(struct iwl_priv *priv) 500static void iwl4965_apm_stop(struct iwl_priv *priv)
932{ 501{
933 int rc = 0;
934 unsigned long flags; 502 unsigned long flags;
935 503
936 iwl4965_hw_nic_stop_master(priv); 504 iwl4965_apm_stop_master(priv);
937 505
938 spin_lock_irqsave(&priv->lock, flags); 506 spin_lock_irqsave(&priv->lock, flags);
939 507
@@ -942,508 +510,66 @@ int iwl4965_hw_nic_reset(struct iwl_priv *priv)
942 udelay(10); 510 udelay(10);
943 511
944 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 512 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
945 rc = iwl_poll_bit(priv, CSR_RESET,
946 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
947 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
948
949 udelay(10);
950
951 rc = iwl_grab_nic_access(priv);
952 if (!rc) {
953 iwl_write_prph(priv, APMG_CLK_EN_REG,
954 APMG_CLK_VAL_DMA_CLK_RQT |
955 APMG_CLK_VAL_BSM_CLK_RQT);
956
957 udelay(10);
958
959 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
960 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
961
962 iwl_release_nic_access(priv);
963 }
964
965 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
966 wake_up_interruptible(&priv->wait_command_queue);
967
968 spin_unlock_irqrestore(&priv->lock, flags); 513 spin_unlock_irqrestore(&priv->lock, flags);
969
970 return rc;
971
972} 514}
973 515
974#define REG_RECALIB_PERIOD (60) 516static int iwl4965_apm_reset(struct iwl_priv *priv)
975
976/**
977 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
978 *
979 * This callback is provided in order to send a statistics request.
980 *
981 * This timer function is continually reset to execute within
982 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
983 * was received. We need to ensure we receive the statistics in order
984 * to update the temperature used for calibrating the TXPOWER.
985 */
986static void iwl4965_bg_statistics_periodic(unsigned long data)
987{ 517{
988 struct iwl_priv *priv = (struct iwl_priv *)data;
989
990 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
991 return;
992
993 iwl_send_statistics_request(priv, CMD_ASYNC);
994}
995
996#define CT_LIMIT_CONST 259
997#define TM_CT_KILL_THRESHOLD 110
998
999void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
1000{
1001 struct iwl4965_ct_kill_config cmd;
1002 u32 R1, R2, R3;
1003 u32 temp_th;
1004 u32 crit_temperature;
1005 unsigned long flags;
1006 int ret = 0; 518 int ret = 0;
519 unsigned long flags;
1007 520
1008 spin_lock_irqsave(&priv->lock, flags); 521 iwl4965_apm_stop_master(priv);
1009 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1010 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1011 spin_unlock_irqrestore(&priv->lock, flags);
1012
1013 if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
1014 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1015 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1016 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1017 } else {
1018 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1019 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1020 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1021 }
1022
1023 temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
1024
1025 crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
1026 cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
1027 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1028 sizeof(cmd), &cmd);
1029 if (ret)
1030 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1031 else
1032 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
1033}
1034
1035#ifdef CONFIG_IWL4965_SENSITIVITY
1036
1037/* "false alarms" are signals that our DSP tries to lock onto,
1038 * but then determines that they are either noise, or transmissions
1039 * from a distant wireless network (also "noise", really) that get
1040 * "stepped on" by stronger transmissions within our own network.
1041 * This algorithm attempts to set a sensitivity level that is high
1042 * enough to receive all of our own network traffic, but not so
1043 * high that our DSP gets too busy trying to lock onto non-network
1044 * activity/noise. */
1045static int iwl4965_sens_energy_cck(struct iwl_priv *priv,
1046 u32 norm_fa,
1047 u32 rx_enable_time,
1048 struct statistics_general_data *rx_info)
1049{
1050 u32 max_nrg_cck = 0;
1051 int i = 0;
1052 u8 max_silence_rssi = 0;
1053 u32 silence_ref = 0;
1054 u8 silence_rssi_a = 0;
1055 u8 silence_rssi_b = 0;
1056 u8 silence_rssi_c = 0;
1057 u32 val;
1058
1059 /* "false_alarms" values below are cross-multiplications to assess the
1060 * numbers of false alarms within the measured period of actual Rx
1061 * (Rx is off when we're txing), vs the min/max expected false alarms
1062 * (some should be expected if rx is sensitive enough) in a
1063 * hypothetical listening period of 200 time units (TU), 204.8 msec:
1064 *
1065 * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
1066 *
1067 * */
1068 u32 false_alarms = norm_fa * 200 * 1024;
1069 u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
1070 u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
1071 struct iwl4965_sensitivity_data *data = NULL;
1072
1073 data = &(priv->sensitivity_data);
1074
1075 data->nrg_auto_corr_silence_diff = 0;
1076
1077 /* Find max silence rssi among all 3 receivers.
1078 * This is background noise, which may include transmissions from other
1079 * networks, measured during silence before our network's beacon */
1080 silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
1081 ALL_BAND_FILTER) >> 8);
1082 silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
1083 ALL_BAND_FILTER) >> 8);
1084 silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
1085 ALL_BAND_FILTER) >> 8);
1086
1087 val = max(silence_rssi_b, silence_rssi_c);
1088 max_silence_rssi = max(silence_rssi_a, (u8) val);
1089
1090 /* Store silence rssi in 20-beacon history table */
1091 data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
1092 data->nrg_silence_idx++;
1093 if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
1094 data->nrg_silence_idx = 0;
1095
1096 /* Find max silence rssi across 20 beacon history */
1097 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
1098 val = data->nrg_silence_rssi[i];
1099 silence_ref = max(silence_ref, val);
1100 }
1101 IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
1102 silence_rssi_a, silence_rssi_b, silence_rssi_c,
1103 silence_ref);
1104
1105 /* Find max rx energy (min value!) among all 3 receivers,
1106 * measured during beacon frame.
1107 * Save it in 10-beacon history table. */
1108 i = data->nrg_energy_idx;
1109 val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
1110 data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
1111
1112 data->nrg_energy_idx++;
1113 if (data->nrg_energy_idx >= 10)
1114 data->nrg_energy_idx = 0;
1115
1116 /* Find min rx energy (max value) across 10 beacon history.
1117 * This is the minimum signal level that we want to receive well.
1118 * Add backoff (margin so we don't miss slightly lower energy frames).
1119 * This establishes an upper bound (min value) for energy threshold. */
1120 max_nrg_cck = data->nrg_value[0];
1121 for (i = 1; i < 10; i++)
1122 max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
1123 max_nrg_cck += 6;
1124
1125 IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
1126 rx_info->beacon_energy_a, rx_info->beacon_energy_b,
1127 rx_info->beacon_energy_c, max_nrg_cck - 6);
1128
1129 /* Count number of consecutive beacons with fewer-than-desired
1130 * false alarms. */
1131 if (false_alarms < min_false_alarms)
1132 data->num_in_cck_no_fa++;
1133 else
1134 data->num_in_cck_no_fa = 0;
1135 IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
1136 data->num_in_cck_no_fa);
1137
1138 /* If we got too many false alarms this time, reduce sensitivity */
1139 if (false_alarms > max_false_alarms) {
1140 IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
1141 false_alarms, max_false_alarms);
1142 IWL_DEBUG_CALIB("... reducing sensitivity\n");
1143 data->nrg_curr_state = IWL_FA_TOO_MANY;
1144
1145 if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
1146 /* Store for "fewer than desired" on later beacon */
1147 data->nrg_silence_ref = silence_ref;
1148
1149 /* increase energy threshold (reduce nrg value)
1150 * to decrease sensitivity */
1151 if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
1152 data->nrg_th_cck = data->nrg_th_cck
1153 - NRG_STEP_CCK;
1154 }
1155
1156 /* increase auto_corr values to decrease sensitivity */
1157 if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
1158 data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
1159 else {
1160 val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
1161 data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
1162 }
1163 val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
1164 data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
1165
1166 /* Else if we got fewer than desired, increase sensitivity */
1167 } else if (false_alarms < min_false_alarms) {
1168 data->nrg_curr_state = IWL_FA_TOO_FEW;
1169
1170 /* Compare silence level with silence level for most recent
1171 * healthy number or too many false alarms */
1172 data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
1173 (s32)silence_ref;
1174
1175 IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
1176 false_alarms, min_false_alarms,
1177 data->nrg_auto_corr_silence_diff);
1178
1179 /* Increase value to increase sensitivity, but only if:
1180 * 1a) previous beacon did *not* have *too many* false alarms
1181 * 1b) AND there's a significant difference in Rx levels
1182 * from a previous beacon with too many, or healthy # FAs
1183 * OR 2) We've seen a lot of beacons (100) with too few
1184 * false alarms */
1185 if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
1186 ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
1187 (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
1188
1189 IWL_DEBUG_CALIB("... increasing sensitivity\n");
1190 /* Increase nrg value to increase sensitivity */
1191 val = data->nrg_th_cck + NRG_STEP_CCK;
1192 data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
1193
1194 /* Decrease auto_corr values to increase sensitivity */
1195 val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
1196 data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
1197
1198 val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
1199 data->auto_corr_cck_mrc =
1200 max((u32)AUTO_CORR_MIN_CCK_MRC, val);
1201
1202 } else
1203 IWL_DEBUG_CALIB("... but not changing sensitivity\n");
1204
1205 /* Else we got a healthy number of false alarms, keep status quo */
1206 } else {
1207 IWL_DEBUG_CALIB(" FA in safe zone\n");
1208 data->nrg_curr_state = IWL_FA_GOOD_RANGE;
1209
1210 /* Store for use in "fewer than desired" with later beacon */
1211 data->nrg_silence_ref = silence_ref;
1212
1213 /* If previous beacon had too many false alarms,
1214 * give it some extra margin by reducing sensitivity again
1215 * (but don't go below measured energy of desired Rx) */
1216 if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
1217 IWL_DEBUG_CALIB("... increasing margin\n");
1218 data->nrg_th_cck -= NRG_MARGIN;
1219 }
1220 }
1221
1222 /* Make sure the energy threshold does not go above the measured
1223 * energy of the desired Rx signals (reduced by backoff margin),
1224 * or else we might start missing Rx frames.
1225 * Lower value is higher energy, so we use max()!
1226 */
1227 data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
1228 IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
1229
1230 data->nrg_prev_state = data->nrg_curr_state;
1231
1232 return 0;
1233}
1234
1235
1236static int iwl4965_sens_auto_corr_ofdm(struct iwl_priv *priv,
1237 u32 norm_fa,
1238 u32 rx_enable_time)
1239{
1240 u32 val;
1241 u32 false_alarms = norm_fa * 200 * 1024;
1242 u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
1243 u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
1244 struct iwl4965_sensitivity_data *data = NULL;
1245
1246 data = &(priv->sensitivity_data);
1247
1248 /* If we got too many false alarms this time, reduce sensitivity */
1249 if (false_alarms > max_false_alarms) {
1250
1251 IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
1252 false_alarms, max_false_alarms);
1253
1254 val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
1255 data->auto_corr_ofdm =
1256 min((u32)AUTO_CORR_MAX_OFDM, val);
1257
1258 val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
1259 data->auto_corr_ofdm_mrc =
1260 min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
1261
1262 val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
1263 data->auto_corr_ofdm_x1 =
1264 min((u32)AUTO_CORR_MAX_OFDM_X1, val);
1265
1266 val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
1267 data->auto_corr_ofdm_mrc_x1 =
1268 min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
1269 }
1270
1271 /* Else if we got fewer than desired, increase sensitivity */
1272 else if (false_alarms < min_false_alarms) {
1273
1274 IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
1275 false_alarms, min_false_alarms);
1276
1277 val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
1278 data->auto_corr_ofdm =
1279 max((u32)AUTO_CORR_MIN_OFDM, val);
1280
1281 val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
1282 data->auto_corr_ofdm_mrc =
1283 max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
1284
1285 val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
1286 data->auto_corr_ofdm_x1 =
1287 max((u32)AUTO_CORR_MIN_OFDM_X1, val);
1288
1289 val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
1290 data->auto_corr_ofdm_mrc_x1 =
1291 max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
1292 }
1293 522
1294 else 523 spin_lock_irqsave(&priv->lock, flags);
1295 IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
1296 min_false_alarms, false_alarms, max_false_alarms);
1297 524
1298 return 0; 525 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1299}
1300 526
1301static int iwl4965_sensitivity_callback(struct iwl_priv *priv, 527 udelay(10);
1302 struct iwl_cmd *cmd, struct sk_buff *skb)
1303{
1304 /* We didn't cache the SKB; let the caller free it */
1305 return 1;
1306}
1307 528
1308/* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */ 529 /* FIXME: put here L1A -L0S w/a */
1309static int iwl4965_sensitivity_write(struct iwl_priv *priv, u8 flags)
1310{
1311 struct iwl4965_sensitivity_cmd cmd ;
1312 struct iwl4965_sensitivity_data *data = NULL;
1313 struct iwl_host_cmd cmd_out = {
1314 .id = SENSITIVITY_CMD,
1315 .len = sizeof(struct iwl4965_sensitivity_cmd),
1316 .meta.flags = flags,
1317 .data = &cmd,
1318 };
1319 int ret;
1320 530
1321 data = &(priv->sensitivity_data); 531 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1322
1323 memset(&cmd, 0, sizeof(cmd));
1324
1325 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
1326 cpu_to_le16((u16)data->auto_corr_ofdm);
1327 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
1328 cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
1329 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
1330 cpu_to_le16((u16)data->auto_corr_ofdm_x1);
1331 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
1332 cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
1333
1334 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
1335 cpu_to_le16((u16)data->auto_corr_cck);
1336 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
1337 cpu_to_le16((u16)data->auto_corr_cck_mrc);
1338
1339 cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
1340 cpu_to_le16((u16)data->nrg_th_cck);
1341 cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
1342 cpu_to_le16((u16)data->nrg_th_ofdm);
1343
1344 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
1345 __constant_cpu_to_le16(190);
1346 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
1347 __constant_cpu_to_le16(390);
1348 cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
1349 __constant_cpu_to_le16(62);
1350
1351 IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
1352 data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
1353 data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
1354 data->nrg_th_ofdm);
1355
1356 IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
1357 data->auto_corr_cck, data->auto_corr_cck_mrc,
1358 data->nrg_th_cck);
1359
1360 /* Update uCode's "work" table, and copy it to DSP */
1361 cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
1362
1363 if (flags & CMD_ASYNC)
1364 cmd_out.meta.u.callback = iwl4965_sensitivity_callback;
1365
1366 /* Don't send command to uCode if nothing has changed */
1367 if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
1368 sizeof(u16)*HD_TABLE_SIZE)) {
1369 IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
1370 return 0;
1371 }
1372 532
1373 /* Copy table for comparison next time */ 533 ret = iwl_poll_bit(priv, CSR_RESET,
1374 memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]), 534 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1375 sizeof(u16)*HD_TABLE_SIZE); 535 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
1376 536
1377 ret = iwl_send_cmd(priv, &cmd_out);
1378 if (ret) 537 if (ret)
1379 IWL_ERROR("SENSITIVITY_CMD failed\n"); 538 goto out;
1380
1381 return ret;
1382}
1383
1384void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags, u8 force)
1385{
1386 struct iwl4965_sensitivity_data *data = NULL;
1387 int i;
1388 int ret = 0;
1389
1390 IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
1391
1392 if (force)
1393 memset(&(priv->sensitivity_tbl[0]), 0,
1394 sizeof(u16)*HD_TABLE_SIZE);
1395
1396 /* Clear driver's sensitivity algo data */
1397 data = &(priv->sensitivity_data);
1398 memset(data, 0, sizeof(struct iwl4965_sensitivity_data));
1399 539
1400 data->num_in_cck_no_fa = 0; 540 udelay(10);
1401 data->nrg_curr_state = IWL_FA_TOO_MANY;
1402 data->nrg_prev_state = IWL_FA_TOO_MANY;
1403 data->nrg_silence_ref = 0;
1404 data->nrg_silence_idx = 0;
1405 data->nrg_energy_idx = 0;
1406 541
1407 for (i = 0; i < 10; i++) 542 ret = iwl_grab_nic_access(priv);
1408 data->nrg_value[i] = 0; 543 if (ret)
544 goto out;
545 /* Enable DMA and BSM Clock */
546 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
547 APMG_CLK_VAL_BSM_CLK_RQT);
1409 548
1410 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) 549 udelay(10);
1411 data->nrg_silence_rssi[i] = 0;
1412 550
1413 data->auto_corr_ofdm = 90; 551 /* disable L1A */
1414 data->auto_corr_ofdm_mrc = 170; 552 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1415 data->auto_corr_ofdm_x1 = 105; 553 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1416 data->auto_corr_ofdm_mrc_x1 = 220;
1417 data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
1418 data->auto_corr_cck_mrc = 200;
1419 data->nrg_th_cck = 100;
1420 data->nrg_th_ofdm = 100;
1421 554
1422 data->last_bad_plcp_cnt_ofdm = 0; 555 iwl_release_nic_access(priv);
1423 data->last_fa_cnt_ofdm = 0;
1424 data->last_bad_plcp_cnt_cck = 0;
1425 data->last_fa_cnt_cck = 0;
1426 556
1427 /* Clear prior Sensitivity command data to force send to uCode */ 557 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1428 if (force) 558 wake_up_interruptible(&priv->wait_command_queue);
1429 memset(&(priv->sensitivity_tbl[0]), 0,
1430 sizeof(u16)*HD_TABLE_SIZE);
1431 559
1432 ret |= iwl4965_sensitivity_write(priv, flags); 560out:
1433 IWL_DEBUG_CALIB("<<return 0x%X\n", ret); 561 spin_unlock_irqrestore(&priv->lock, flags);
1434 562
1435 return; 563 return ret;
1436} 564}
1437 565
1438
1439/* Reset differential Rx gains in NIC to prepare for chain noise calibration. 566/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1440 * Called after every association, but this runs only once! 567 * Called after every association, but this runs only once!
1441 * ... once chain noise is calibrated the first time, it's good forever. */ 568 * ... once chain noise is calibrated the first time, it's good forever. */
1442void iwl4965_chain_noise_reset(struct iwl_priv *priv) 569static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
1443{ 570{
1444 struct iwl4965_chain_noise_data *data = NULL; 571 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
1445 572
1446 data = &(priv->chain_noise_data);
1447 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { 573 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
1448 struct iwl4965_calibration_cmd cmd; 574 struct iwl4965_calibration_cmd cmd;
1449 575
@@ -1452,388 +578,89 @@ void iwl4965_chain_noise_reset(struct iwl_priv *priv)
1452 cmd.diff_gain_a = 0; 578 cmd.diff_gain_a = 0;
1453 cmd.diff_gain_b = 0; 579 cmd.diff_gain_b = 0;
1454 cmd.diff_gain_c = 0; 580 cmd.diff_gain_c = 0;
1455 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, 581 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1456 sizeof(cmd), &cmd, NULL); 582 sizeof(cmd), &cmd))
1457 msleep(4); 583 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
1458 data->state = IWL_CHAIN_NOISE_ACCUMULATE; 584 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1459 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); 585 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1460 } 586 }
1461 return;
1462} 587}
1463 588
1464/* 589static void iwl4965_gain_computation(struct iwl_priv *priv,
1465 * Accumulate 20 beacons of signal and noise statistics for each of 590 u32 *average_noise,
1466 * 3 receivers/antennas/rx-chains, then figure out: 591 u16 min_average_noise_antenna_i,
1467 * 1) Which antennas are connected. 592 u32 min_average_noise)
1468 * 2) Differential rx gain settings to balance the 3 receivers.
1469 */
1470static void iwl4965_noise_calibration(struct iwl_priv *priv,
1471 struct iwl4965_notif_statistics *stat_resp)
1472{ 593{
1473 struct iwl4965_chain_noise_data *data = NULL; 594 int i, ret;
1474 int ret = 0; 595 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
1475
1476 u32 chain_noise_a;
1477 u32 chain_noise_b;
1478 u32 chain_noise_c;
1479 u32 chain_sig_a;
1480 u32 chain_sig_b;
1481 u32 chain_sig_c;
1482 u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1483 u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1484 u32 max_average_sig;
1485 u16 max_average_sig_antenna_i;
1486 u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
1487 u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
1488 u16 i = 0;
1489 u16 chan_num = INITIALIZATION_VALUE;
1490 u32 band = INITIALIZATION_VALUE;
1491 u32 active_chains = 0;
1492 unsigned long flags;
1493 struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
1494
1495 data = &(priv->chain_noise_data);
1496
1497 /* Accumulate just the first 20 beacons after the first association,
1498 * then we're done forever. */
1499 if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
1500 if (data->state == IWL_CHAIN_NOISE_ALIVE)
1501 IWL_DEBUG_CALIB("Wait for noise calib reset\n");
1502 return;
1503 }
1504
1505 spin_lock_irqsave(&priv->lock, flags);
1506 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1507 IWL_DEBUG_CALIB(" << Interference data unavailable\n");
1508 spin_unlock_irqrestore(&priv->lock, flags);
1509 return;
1510 }
1511
1512 band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
1513 chan_num = le16_to_cpu(priv->staging_rxon.channel);
1514
1515 /* Make sure we accumulate data for just the associated channel
1516 * (even if scanning). */
1517 if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
1518 ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
1519 (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
1520 IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
1521 chan_num, band);
1522 spin_unlock_irqrestore(&priv->lock, flags);
1523 return;
1524 }
1525
1526 /* Accumulate beacon statistics values across 20 beacons */
1527 chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
1528 IN_BAND_FILTER;
1529 chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
1530 IN_BAND_FILTER;
1531 chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
1532 IN_BAND_FILTER;
1533
1534 chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
1535 chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
1536 chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
1537
1538 spin_unlock_irqrestore(&priv->lock, flags);
1539
1540 data->beacon_count++;
1541
1542 data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
1543 data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
1544 data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
1545
1546 data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
1547 data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
1548 data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
1549
1550 IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
1551 data->beacon_count);
1552 IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
1553 chain_sig_a, chain_sig_b, chain_sig_c);
1554 IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
1555 chain_noise_a, chain_noise_b, chain_noise_c);
1556
1557 /* If this is the 20th beacon, determine:
1558 * 1) Disconnected antennas (using signal strengths)
1559 * 2) Differential gain (using silence noise) to balance receivers */
1560 if (data->beacon_count == CAL_NUM_OF_BEACONS) {
1561
1562 /* Analyze signal for disconnected antenna */
1563 average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
1564 average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
1565 average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
1566
1567 if (average_sig[0] >= average_sig[1]) {
1568 max_average_sig = average_sig[0];
1569 max_average_sig_antenna_i = 0;
1570 active_chains = (1 << max_average_sig_antenna_i);
1571 } else {
1572 max_average_sig = average_sig[1];
1573 max_average_sig_antenna_i = 1;
1574 active_chains = (1 << max_average_sig_antenna_i);
1575 }
1576
1577 if (average_sig[2] >= max_average_sig) {
1578 max_average_sig = average_sig[2];
1579 max_average_sig_antenna_i = 2;
1580 active_chains = (1 << max_average_sig_antenna_i);
1581 }
1582
1583 IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
1584 average_sig[0], average_sig[1], average_sig[2]);
1585 IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
1586 max_average_sig, max_average_sig_antenna_i);
1587
1588 /* Compare signal strengths for all 3 receivers. */
1589 for (i = 0; i < NUM_RX_CHAINS; i++) {
1590 if (i != max_average_sig_antenna_i) {
1591 s32 rssi_delta = (max_average_sig -
1592 average_sig[i]);
1593
1594 /* If signal is very weak, compared with
1595 * strongest, mark it as disconnected. */
1596 if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
1597 data->disconn_array[i] = 1;
1598 else
1599 active_chains |= (1 << i);
1600 IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
1601 "disconn_array[i] = %d\n",
1602 i, rssi_delta, data->disconn_array[i]);
1603 }
1604 }
1605
1606 /*If both chains A & B are disconnected -
1607 * connect B and leave A as is */
1608 if (data->disconn_array[CHAIN_A] &&
1609 data->disconn_array[CHAIN_B]) {
1610 data->disconn_array[CHAIN_B] = 0;
1611 active_chains |= (1 << CHAIN_B);
1612 IWL_DEBUG_CALIB("both A & B chains are disconnected! "
1613 "W/A - declare B as connected\n");
1614 }
1615 596
1616 IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n", 597 data->delta_gain_code[min_average_noise_antenna_i] = 0;
1617 active_chains);
1618 598
1619 /* Save for use within RXON, TX, SCAN commands, etc. */ 599 for (i = 0; i < NUM_RX_CHAINS; i++) {
1620 priv->valid_antenna = active_chains; 600 s32 delta_g = 0;
1621 601
1622 /* Analyze noise for rx balance */ 602 if (!(data->disconn_array[i]) &&
1623 average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS); 603 (data->delta_gain_code[i] ==
1624 average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
1625 average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
1626
1627 for (i = 0; i < NUM_RX_CHAINS; i++) {
1628 if (!(data->disconn_array[i]) &&
1629 (average_noise[i] <= min_average_noise)) {
1630 /* This means that chain i is active and has
1631 * lower noise values so far: */
1632 min_average_noise = average_noise[i];
1633 min_average_noise_antenna_i = i;
1634 }
1635 }
1636
1637 data->delta_gain_code[min_average_noise_antenna_i] = 0;
1638
1639 IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
1640 average_noise[0], average_noise[1],
1641 average_noise[2]);
1642
1643 IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
1644 min_average_noise, min_average_noise_antenna_i);
1645
1646 for (i = 0; i < NUM_RX_CHAINS; i++) {
1647 s32 delta_g = 0;
1648
1649 if (!(data->disconn_array[i]) &&
1650 (data->delta_gain_code[i] ==
1651 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) { 604 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
1652 delta_g = average_noise[i] - min_average_noise; 605 delta_g = average_noise[i] - min_average_noise;
1653 data->delta_gain_code[i] = (u8)((delta_g * 606 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
1654 10) / 15); 607 data->delta_gain_code[i] =
1655 if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE < 608 min(data->delta_gain_code[i],
1656 data->delta_gain_code[i]) 609 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
1657 data->delta_gain_code[i] = 610
1658 CHAIN_NOISE_MAX_DELTA_GAIN_CODE; 611 data->delta_gain_code[i] =
1659 612 (data->delta_gain_code[i] | (1 << 2));
1660 data->delta_gain_code[i] = 613 } else {
1661 (data->delta_gain_code[i] | (1 << 2)); 614 data->delta_gain_code[i] = 0;
1662 } else
1663 data->delta_gain_code[i] = 0;
1664 }
1665 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1666 data->delta_gain_code[0],
1667 data->delta_gain_code[1],
1668 data->delta_gain_code[2]);
1669
1670 /* Differential gain gets sent to uCode only once */
1671 if (!data->radio_write) {
1672 struct iwl4965_calibration_cmd cmd;
1673 data->radio_write = 1;
1674
1675 memset(&cmd, 0, sizeof(cmd));
1676 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1677 cmd.diff_gain_a = data->delta_gain_code[0];
1678 cmd.diff_gain_b = data->delta_gain_code[1];
1679 cmd.diff_gain_c = data->delta_gain_code[2];
1680 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1681 sizeof(cmd), &cmd);
1682 if (ret)
1683 IWL_DEBUG_CALIB("fail sending cmd "
1684 "REPLY_PHY_CALIBRATION_CMD \n");
1685
1686 /* TODO we might want recalculate
1687 * rx_chain in rxon cmd */
1688
1689 /* Mark so we run this algo only once! */
1690 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1691 } 615 }
1692 data->chain_noise_a = 0;
1693 data->chain_noise_b = 0;
1694 data->chain_noise_c = 0;
1695 data->chain_signal_a = 0;
1696 data->chain_signal_b = 0;
1697 data->chain_signal_c = 0;
1698 data->beacon_count = 0;
1699 }
1700 return;
1701}
1702
1703static void iwl4965_sensitivity_calibration(struct iwl_priv *priv,
1704 struct iwl4965_notif_statistics *resp)
1705{
1706 u32 rx_enable_time;
1707 u32 fa_cck;
1708 u32 fa_ofdm;
1709 u32 bad_plcp_cck;
1710 u32 bad_plcp_ofdm;
1711 u32 norm_fa_ofdm;
1712 u32 norm_fa_cck;
1713 struct iwl4965_sensitivity_data *data = NULL;
1714 struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
1715 struct statistics_rx *statistics = &(resp->rx);
1716 unsigned long flags;
1717 struct statistics_general_data statis;
1718 int ret;
1719
1720 data = &(priv->sensitivity_data);
1721
1722 if (!iwl_is_associated(priv)) {
1723 IWL_DEBUG_CALIB("<< - not associated\n");
1724 return;
1725 } 616 }
617 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
618 data->delta_gain_code[0],
619 data->delta_gain_code[1],
620 data->delta_gain_code[2]);
1726 621
1727 spin_lock_irqsave(&priv->lock, flags); 622 /* Differential gain gets sent to uCode only once */
1728 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) { 623 if (!data->radio_write) {
1729 IWL_DEBUG_CALIB("<< invalid data.\n"); 624 struct iwl4965_calibration_cmd cmd;
1730 spin_unlock_irqrestore(&priv->lock, flags); 625 data->radio_write = 1;
1731 return;
1732 }
1733
1734 /* Extract Statistics: */
1735 rx_enable_time = le32_to_cpu(rx_info->channel_load);
1736 fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
1737 fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
1738 bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
1739 bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
1740
1741 statis.beacon_silence_rssi_a =
1742 le32_to_cpu(statistics->general.beacon_silence_rssi_a);
1743 statis.beacon_silence_rssi_b =
1744 le32_to_cpu(statistics->general.beacon_silence_rssi_b);
1745 statis.beacon_silence_rssi_c =
1746 le32_to_cpu(statistics->general.beacon_silence_rssi_c);
1747 statis.beacon_energy_a =
1748 le32_to_cpu(statistics->general.beacon_energy_a);
1749 statis.beacon_energy_b =
1750 le32_to_cpu(statistics->general.beacon_energy_b);
1751 statis.beacon_energy_c =
1752 le32_to_cpu(statistics->general.beacon_energy_c);
1753
1754 spin_unlock_irqrestore(&priv->lock, flags);
1755
1756 IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
1757
1758 if (!rx_enable_time) {
1759 IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
1760 return;
1761 }
1762
1763 /* These statistics increase monotonically, and do not reset
1764 * at each beacon. Calculate difference from last value, or just
1765 * use the new statistics value if it has reset or wrapped around. */
1766 if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
1767 data->last_bad_plcp_cnt_cck = bad_plcp_cck;
1768 else {
1769 bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
1770 data->last_bad_plcp_cnt_cck += bad_plcp_cck;
1771 }
1772 626
1773 if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm) 627 memset(&cmd, 0, sizeof(cmd));
1774 data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm; 628 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1775 else { 629 cmd.diff_gain_a = data->delta_gain_code[0];
1776 bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm; 630 cmd.diff_gain_b = data->delta_gain_code[1];
1777 data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm; 631 cmd.diff_gain_c = data->delta_gain_code[2];
1778 } 632 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
633 sizeof(cmd), &cmd);
634 if (ret)
635 IWL_DEBUG_CALIB("fail sending cmd "
636 "REPLY_PHY_CALIBRATION_CMD \n");
1779 637
1780 if (data->last_fa_cnt_ofdm > fa_ofdm) 638 /* TODO we might want recalculate
1781 data->last_fa_cnt_ofdm = fa_ofdm; 639 * rx_chain in rxon cmd */
1782 else {
1783 fa_ofdm -= data->last_fa_cnt_ofdm;
1784 data->last_fa_cnt_ofdm += fa_ofdm;
1785 }
1786 640
1787 if (data->last_fa_cnt_cck > fa_cck) 641 /* Mark so we run this algo only once! */
1788 data->last_fa_cnt_cck = fa_cck; 642 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1789 else {
1790 fa_cck -= data->last_fa_cnt_cck;
1791 data->last_fa_cnt_cck += fa_cck;
1792 } 643 }
1793 644 data->chain_noise_a = 0;
1794 /* Total aborted signal locks */ 645 data->chain_noise_b = 0;
1795 norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm; 646 data->chain_noise_c = 0;
1796 norm_fa_cck = fa_cck + bad_plcp_cck; 647 data->chain_signal_a = 0;
1797 648 data->chain_signal_b = 0;
1798 IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck, 649 data->chain_signal_c = 0;
1799 bad_plcp_cck, fa_ofdm, bad_plcp_ofdm); 650 data->beacon_count = 0;
1800
1801 iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
1802 iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
1803 ret = iwl4965_sensitivity_write(priv, CMD_ASYNC);
1804
1805 return;
1806} 651}
1807 652
1808static void iwl4965_bg_sensitivity_work(struct work_struct *work) 653static void iwl4965_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
654 __le32 *tx_flags)
1809{ 655{
1810 struct iwl_priv *priv = container_of(work, struct iwl_priv, 656 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
1811 sensitivity_work); 657 *tx_flags |= TX_CMD_FLG_RTS_MSK;
1812 658 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
1813 mutex_lock(&priv->mutex); 659 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
1814 660 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
1815 if (test_bit(STATUS_EXIT_PENDING, &priv->status) || 661 *tx_flags |= TX_CMD_FLG_CTS_MSK;
1816 test_bit(STATUS_SCANNING, &priv->status)) {
1817 mutex_unlock(&priv->mutex);
1818 return;
1819 }
1820
1821 if (priv->start_calib) {
1822 iwl4965_noise_calibration(priv, &priv->statistics);
1823
1824 if (priv->sensitivity_data.state ==
1825 IWL_SENS_CALIB_NEED_REINIT) {
1826 iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
1827 priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
1828 } else
1829 iwl4965_sensitivity_calibration(priv,
1830 &priv->statistics);
1831 } 662 }
1832
1833 mutex_unlock(&priv->mutex);
1834 return;
1835} 663}
1836#endif /*CONFIG_IWL4965_SENSITIVITY*/
1837 664
1838static void iwl4965_bg_txpower_work(struct work_struct *work) 665static void iwl4965_bg_txpower_work(struct work_struct *work)
1839{ 666{
@@ -1853,7 +680,7 @@ static void iwl4965_bg_txpower_work(struct work_struct *work)
1853 /* Regardless of if we are assocaited, we must reconfigure the 680 /* Regardless of if we are assocaited, we must reconfigure the
1854 * TX power since frames can be sent on non-radar channels while 681 * TX power since frames can be sent on non-radar channels while
1855 * not associated */ 682 * not associated */
1856 iwl4965_hw_reg_send_txpower(priv); 683 iwl4965_send_tx_power(priv);
1857 684
1858 /* Update last_temperature to keep is_calib_needed from running 685 /* Update last_temperature to keep is_calib_needed from running
1859 * when it isn't needed... */ 686 * when it isn't needed... */
@@ -1880,7 +707,7 @@ static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
1880 * NOTE: Acquire priv->lock before calling this function ! 707 * NOTE: Acquire priv->lock before calling this function !
1881 */ 708 */
1882static void iwl4965_tx_queue_set_status(struct iwl_priv *priv, 709static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
1883 struct iwl4965_tx_queue *txq, 710 struct iwl_tx_queue *txq,
1884 int tx_fifo_id, int scd_retry) 711 int tx_fifo_id, int scd_retry)
1885{ 712{
1886 int txq_id = txq->q.id; 713 int txq_id = txq->q.id;
@@ -1890,11 +717,11 @@ static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
1890 717
1891 /* Set up and activate */ 718 /* Set up and activate */
1892 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id), 719 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1893 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 720 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1894 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | 721 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
1895 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) | 722 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
1896 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) | 723 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1897 SCD_QUEUE_STTS_REG_MSK); 724 IWL49_SCD_QUEUE_STTS_REG_MSK);
1898 725
1899 txq->sched_retry = scd_retry; 726 txq->sched_retry = scd_retry;
1900 727
@@ -1908,22 +735,12 @@ static const u16 default_queue_to_tx_fifo[] = {
1908 IWL_TX_FIFO_AC2, 735 IWL_TX_FIFO_AC2,
1909 IWL_TX_FIFO_AC1, 736 IWL_TX_FIFO_AC1,
1910 IWL_TX_FIFO_AC0, 737 IWL_TX_FIFO_AC0,
1911 IWL_CMD_FIFO_NUM, 738 IWL49_CMD_FIFO_NUM,
1912 IWL_TX_FIFO_HCCA_1, 739 IWL_TX_FIFO_HCCA_1,
1913 IWL_TX_FIFO_HCCA_2 740 IWL_TX_FIFO_HCCA_2
1914}; 741};
1915 742
1916static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id) 743static int iwl4965_alive_notify(struct iwl_priv *priv)
1917{
1918 set_bit(txq_id, &priv->txq_ctx_active_msk);
1919}
1920
1921static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1922{
1923 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1924}
1925
1926int iwl4965_alive_notify(struct iwl_priv *priv)
1927{ 744{
1928 u32 a; 745 u32 a;
1929 int i = 0; 746 int i = 0;
@@ -1932,15 +749,6 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1932 749
1933 spin_lock_irqsave(&priv->lock, flags); 750 spin_lock_irqsave(&priv->lock, flags);
1934 751
1935#ifdef CONFIG_IWL4965_SENSITIVITY
1936 memset(&(priv->sensitivity_data), 0,
1937 sizeof(struct iwl4965_sensitivity_data));
1938 memset(&(priv->chain_noise_data), 0,
1939 sizeof(struct iwl4965_chain_noise_data));
1940 for (i = 0; i < NUM_RX_CHAINS; i++)
1941 priv->chain_noise_data.delta_gain_code[i] =
1942 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
1943#endif /* CONFIG_IWL4965_SENSITIVITY*/
1944 ret = iwl_grab_nic_access(priv); 752 ret = iwl_grab_nic_access(priv);
1945 if (ret) { 753 if (ret) {
1946 spin_unlock_irqrestore(&priv->lock, flags); 754 spin_unlock_irqrestore(&priv->lock, flags);
@@ -1949,10 +757,10 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1949 757
1950 /* Clear 4965's internal Tx Scheduler data base */ 758 /* Clear 4965's internal Tx Scheduler data base */
1951 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR); 759 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
1952 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET; 760 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
1953 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4) 761 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1954 iwl_write_targ_mem(priv, a, 0); 762 iwl_write_targ_mem(priv, a, 0);
1955 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4) 763 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
1956 iwl_write_targ_mem(priv, a, 0); 764 iwl_write_targ_mem(priv, a, 0);
1957 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) 765 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
1958 iwl_write_targ_mem(priv, a, 0); 766 iwl_write_targ_mem(priv, a, 0);
@@ -1974,160 +782,109 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1974 782
1975 /* Max Tx Window size for Scheduler-ACK mode */ 783 /* Max Tx Window size for Scheduler-ACK mode */
1976 iwl_write_targ_mem(priv, priv->scd_base_addr + 784 iwl_write_targ_mem(priv, priv->scd_base_addr +
1977 SCD_CONTEXT_QUEUE_OFFSET(i), 785 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
1978 (SCD_WIN_SIZE << 786 (SCD_WIN_SIZE <<
1979 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & 787 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1980 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 788 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1981 789
1982 /* Frame limit */ 790 /* Frame limit */
1983 iwl_write_targ_mem(priv, priv->scd_base_addr + 791 iwl_write_targ_mem(priv, priv->scd_base_addr +
1984 SCD_CONTEXT_QUEUE_OFFSET(i) + 792 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
1985 sizeof(u32), 793 sizeof(u32),
1986 (SCD_FRAME_LIMIT << 794 (SCD_FRAME_LIMIT <<
1987 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 795 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1988 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 796 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1989 797
1990 } 798 }
1991 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK, 799 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
1992 (1 << priv->hw_params.max_txq_num) - 1); 800 (1 << priv->hw_params.max_txq_num) - 1);
1993 801
1994 /* Activate all Tx DMA/FIFO channels */ 802 /* Activate all Tx DMA/FIFO channels */
1995 iwl_write_prph(priv, IWL49_SCD_TXFACT, 803 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
1996 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1997 804
1998 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 805 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
1999 806
2000 /* Map each Tx/cmd queue to its corresponding fifo */ 807 /* Map each Tx/cmd queue to its corresponding fifo */
2001 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) { 808 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
2002 int ac = default_queue_to_tx_fifo[i]; 809 int ac = default_queue_to_tx_fifo[i];
2003 iwl4965_txq_ctx_activate(priv, i); 810 iwl_txq_ctx_activate(priv, i);
2004 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 811 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
2005 } 812 }
2006 813
2007 iwl_release_nic_access(priv); 814 iwl_release_nic_access(priv);
2008 spin_unlock_irqrestore(&priv->lock, flags); 815 spin_unlock_irqrestore(&priv->lock, flags);
2009 816
2010 /* Ask for statistics now, the uCode will send statistics notification
2011 * periodically after association */
2012 iwl_send_statistics_request(priv, CMD_ASYNC);
2013 return ret; 817 return ret;
2014} 818}
2015 819
820static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
821 .min_nrg_cck = 97,
822 .max_nrg_cck = 0,
823
824 .auto_corr_min_ofdm = 85,
825 .auto_corr_min_ofdm_mrc = 170,
826 .auto_corr_min_ofdm_x1 = 105,
827 .auto_corr_min_ofdm_mrc_x1 = 220,
828
829 .auto_corr_max_ofdm = 120,
830 .auto_corr_max_ofdm_mrc = 210,
831 .auto_corr_max_ofdm_x1 = 140,
832 .auto_corr_max_ofdm_mrc_x1 = 270,
833
834 .auto_corr_min_cck = 125,
835 .auto_corr_max_cck = 200,
836 .auto_corr_min_cck_mrc = 200,
837 .auto_corr_max_cck_mrc = 400,
838
839 .nrg_th_cck = 100,
840 .nrg_th_ofdm = 100,
841};
842
2016/** 843/**
2017 * iwl4965_hw_set_hw_params 844 * iwl4965_hw_set_hw_params
2018 * 845 *
2019 * Called when initializing driver 846 * Called when initializing driver
2020 */ 847 */
2021int iwl4965_hw_set_hw_params(struct iwl_priv *priv) 848static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
2022{ 849{
2023 850
2024 if ((priv->cfg->mod_params->num_of_queues > IWL4965_MAX_NUM_QUEUES) || 851 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
2025 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { 852 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
2026 IWL_ERROR("invalid queues_num, should be between %d and %d\n", 853 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
2027 IWL_MIN_NUM_QUEUES, IWL4965_MAX_NUM_QUEUES); 854 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
2028 return -EINVAL; 855 return -EINVAL;
2029 } 856 }
2030 857
2031 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; 858 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
2032 priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd); 859 priv->hw_params.first_ampdu_q = IWL49_FIRST_AMPDU_QUEUE;
2033 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2034 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2035 if (priv->cfg->mod_params->amsdu_size_8K)
2036 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
2037 else
2038 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
2039 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
2040 priv->hw_params.max_stations = IWL4965_STATION_COUNT; 860 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
2041 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID; 861 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
862 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
863 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
864 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
865 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
2042 866
2043 priv->hw_params.tx_chains_num = 2; 867 priv->hw_params.tx_chains_num = 2;
2044 priv->hw_params.rx_chains_num = 2; 868 priv->hw_params.rx_chains_num = 2;
2045 priv->hw_params.valid_tx_ant = (IWL_ANTENNA_MAIN | IWL_ANTENNA_AUX); 869 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
2046 priv->hw_params.valid_rx_ant = (IWL_ANTENNA_MAIN | IWL_ANTENNA_AUX); 870 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
2047 871 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
2048 return 0;
2049}
2050
2051/**
2052 * iwl4965_hw_txq_ctx_free - Free TXQ Context
2053 *
2054 * Destroy all TX DMA queues and structures
2055 */
2056void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
2057{
2058 int txq_id;
2059
2060 /* Tx queues */
2061 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
2062 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
2063
2064 /* Keep-warm buffer */
2065 iwl4965_kw_free(priv);
2066}
2067
2068/**
2069 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
2070 *
2071 * Does NOT advance any TFD circular buffer read/write indexes
2072 * Does NOT free the TFD itself (which is within circular buffer)
2073 */
2074int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
2075{
2076 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
2077 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
2078 struct pci_dev *dev = priv->pci_dev;
2079 int i;
2080 int counter = 0;
2081 int index, is_odd;
2082 872
2083 /* Host command buffers stay mapped in memory, nothing to clean */ 873 priv->hw_params.sens = &iwl4965_sensitivity;
2084 if (txq->q.id == IWL_CMD_QUEUE_NUM)
2085 return 0;
2086
2087 /* Sanity check on number of chunks */
2088 counter = IWL_GET_BITS(*bd, num_tbs);
2089 if (counter > MAX_NUM_OF_TBS) {
2090 IWL_ERROR("Too many chunks: %i\n", counter);
2091 /* @todo issue fatal error, it is quite serious situation */
2092 return 0;
2093 }
2094 874
2095 /* Unmap chunks, if any.
2096 * TFD info for odd chunks is different format than for even chunks. */
2097 for (i = 0; i < counter; i++) {
2098 index = i / 2;
2099 is_odd = i & 0x1;
2100
2101 if (is_odd)
2102 pci_unmap_single(
2103 dev,
2104 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
2105 (IWL_GET_BITS(bd->pa[index],
2106 tb2_addr_hi20) << 16),
2107 IWL_GET_BITS(bd->pa[index], tb2_len),
2108 PCI_DMA_TODEVICE);
2109
2110 else if (i > 0)
2111 pci_unmap_single(dev,
2112 le32_to_cpu(bd->pa[index].tb1_addr),
2113 IWL_GET_BITS(bd->pa[index], tb1_len),
2114 PCI_DMA_TODEVICE);
2115
2116 /* Free SKB, if any, for this chunk */
2117 if (txq->txb[txq->q.read_ptr].skb[i]) {
2118 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
2119
2120 dev_kfree_skb(skb);
2121 txq->txb[txq->q.read_ptr].skb[i] = NULL;
2122 }
2123 }
2124 return 0; 875 return 0;
2125} 876}
2126 877
2127int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power) 878/* set card power command */
879static int iwl4965_set_power(struct iwl_priv *priv,
880 void *cmd)
2128{ 881{
2129 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n"); 882 int ret = 0;
2130 return -EINVAL; 883
884 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
885 sizeof(struct iwl4965_powertable_cmd),
886 cmd, NULL);
887 return ret;
2131} 888}
2132 889
2133static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res) 890static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
@@ -2179,20 +936,6 @@ static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
2179 return comp; 936 return comp;
2180} 937}
2181 938
2182static const struct iwl_channel_info *
2183iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
2184 enum ieee80211_band band, u16 channel)
2185{
2186 const struct iwl_channel_info *ch_info;
2187
2188 ch_info = iwl_get_channel_info(priv, band, channel);
2189
2190 if (!is_channel_valid(ch_info))
2191 return NULL;
2192
2193 return ch_info;
2194}
2195
2196static s32 iwl4965_get_tx_atten_grp(u16 channel) 939static s32 iwl4965_get_tx_atten_grp(u16 channel)
2197{ 940{
2198 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH && 941 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
@@ -2224,11 +967,11 @@ static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
2224 s32 b = -1; 967 s32 b = -1;
2225 968
2226 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) { 969 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
2227 if (priv->eeprom.calib_info.band_info[b].ch_from == 0) 970 if (priv->calib_info->band_info[b].ch_from == 0)
2228 continue; 971 continue;
2229 972
2230 if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from) 973 if ((channel >= priv->calib_info->band_info[b].ch_from)
2231 && (channel <= priv->eeprom.calib_info.band_info[b].ch_to)) 974 && (channel <= priv->calib_info->band_info[b].ch_to))
2232 break; 975 break;
2233 } 976 }
2234 977
@@ -2256,14 +999,14 @@ static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
2256 * in channel number. 999 * in channel number.
2257 */ 1000 */
2258static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel, 1001static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
2259 struct iwl4965_eeprom_calib_ch_info *chan_info) 1002 struct iwl_eeprom_calib_ch_info *chan_info)
2260{ 1003{
2261 s32 s = -1; 1004 s32 s = -1;
2262 u32 c; 1005 u32 c;
2263 u32 m; 1006 u32 m;
2264 const struct iwl4965_eeprom_calib_measure *m1; 1007 const struct iwl_eeprom_calib_measure *m1;
2265 const struct iwl4965_eeprom_calib_measure *m2; 1008 const struct iwl_eeprom_calib_measure *m2;
2266 struct iwl4965_eeprom_calib_measure *omeas; 1009 struct iwl_eeprom_calib_measure *omeas;
2267 u32 ch_i1; 1010 u32 ch_i1;
2268 u32 ch_i2; 1011 u32 ch_i2;
2269 1012
@@ -2273,8 +1016,8 @@ static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
2273 return -1; 1016 return -1;
2274 } 1017 }
2275 1018
2276 ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num; 1019 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
2277 ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num; 1020 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
2278 chan_info->ch_num = (u8) channel; 1021 chan_info->ch_num = (u8) channel;
2279 1022
2280 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n", 1023 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
@@ -2282,9 +1025,9 @@ static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
2282 1025
2283 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) { 1026 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
2284 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) { 1027 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
2285 m1 = &(priv->eeprom.calib_info.band_info[s].ch1. 1028 m1 = &(priv->calib_info->band_info[s].ch1.
2286 measurements[c][m]); 1029 measurements[c][m]);
2287 m2 = &(priv->eeprom.calib_info.band_info[s].ch2. 1030 m2 = &(priv->calib_info->band_info[s].ch2.
2288 measurements[c][m]); 1031 measurements[c][m]);
2289 omeas = &(chan_info->measurements[c][m]); 1032 omeas = &(chan_info->measurements[c][m]);
2290 1033
@@ -2603,8 +1346,8 @@ static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
2603 int i; 1346 int i;
2604 int c; 1347 int c;
2605 const struct iwl_channel_info *ch_info = NULL; 1348 const struct iwl_channel_info *ch_info = NULL;
2606 struct iwl4965_eeprom_calib_ch_info ch_eeprom_info; 1349 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
2607 const struct iwl4965_eeprom_calib_measure *measurement; 1350 const struct iwl_eeprom_calib_measure *measurement;
2608 s16 voltage; 1351 s16 voltage;
2609 s32 init_voltage; 1352 s32 init_voltage;
2610 s32 voltage_compensation; 1353 s32 voltage_compensation;
@@ -2616,30 +1359,17 @@ static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
2616 s32 factory_actual_pwr[2]; 1359 s32 factory_actual_pwr[2];
2617 s32 power_index; 1360 s32 power_index;
2618 1361
2619 /* Sanity check requested level (dBm) */
2620 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
2621 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
2622 priv->user_txpower_limit);
2623 return -EINVAL;
2624 }
2625 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
2626 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
2627 priv->user_txpower_limit);
2628 return -EINVAL;
2629 }
2630
2631 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units 1362 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
2632 * are used for indexing into txpower table) */ 1363 * are used for indexing into txpower table) */
2633 user_target_power = 2 * priv->user_txpower_limit; 1364 user_target_power = 2 * priv->tx_power_user_lmt;
2634 1365
2635 /* Get current (RXON) channel, band, width */ 1366 /* Get current (RXON) channel, band, width */
2636 ch_info =
2637 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
2638
2639 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band, 1367 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
2640 is_fat); 1368 is_fat);
2641 1369
2642 if (!ch_info) 1370 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1371
1372 if (!is_channel_valid(ch_info))
2643 return -EINVAL; 1373 return -EINVAL;
2644 1374
2645 /* get txatten group, used to select 1) thermal txpower adjustment 1375 /* get txatten group, used to select 1) thermal txpower adjustment
@@ -2661,9 +1391,9 @@ static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
2661 /* hardware txpower limits ... 1391 /* hardware txpower limits ...
2662 * saturation (clipping distortion) txpowers are in half-dBm */ 1392 * saturation (clipping distortion) txpowers are in half-dBm */
2663 if (band) 1393 if (band)
2664 saturation_power = priv->eeprom.calib_info.saturation_power24; 1394 saturation_power = priv->calib_info->saturation_power24;
2665 else 1395 else
2666 saturation_power = priv->eeprom.calib_info.saturation_power52; 1396 saturation_power = priv->calib_info->saturation_power52;
2667 1397
2668 if (saturation_power < IWL_TX_POWER_SATURATION_MIN || 1398 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
2669 saturation_power > IWL_TX_POWER_SATURATION_MAX) { 1399 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
@@ -2693,7 +1423,7 @@ static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
2693 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info); 1423 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2694 1424
2695 /* calculate tx gain adjustment based on power supply voltage */ 1425 /* calculate tx gain adjustment based on power supply voltage */
2696 voltage = priv->eeprom.calib_info.voltage; 1426 voltage = priv->calib_info->voltage;
2697 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage); 1427 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2698 voltage_compensation = 1428 voltage_compensation =
2699 iwl4965_get_voltage_compensation(voltage, init_voltage); 1429 iwl4965_get_voltage_compensation(voltage, init_voltage);
@@ -2840,12 +1570,12 @@ static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
2840} 1570}
2841 1571
2842/** 1572/**
2843 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit 1573 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
2844 * 1574 *
2845 * Uses the active RXON for channel, band, and characteristics (fat, high) 1575 * Uses the active RXON for channel, band, and characteristics (fat, high)
2846 * The power limit is taken from priv->user_txpower_limit. 1576 * The power limit is taken from priv->tx_power_user_lmt.
2847 */ 1577 */
2848int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv) 1578static int iwl4965_send_tx_power(struct iwl_priv *priv)
2849{ 1579{
2850 struct iwl4965_txpowertable_cmd cmd = { 0 }; 1580 struct iwl4965_txpowertable_cmd cmd = { 0 };
2851 int ret; 1581 int ret;
@@ -2888,8 +1618,8 @@ static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2888{ 1618{
2889 int ret = 0; 1619 int ret = 0;
2890 struct iwl4965_rxon_assoc_cmd rxon_assoc; 1620 struct iwl4965_rxon_assoc_cmd rxon_assoc;
2891 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon; 1621 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
2892 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon; 1622 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
2893 1623
2894 if ((rxon1->flags == rxon2->flags) && 1624 if ((rxon1->flags == rxon2->flags) &&
2895 (rxon1->filter_flags == rxon2->filter_flags) && 1625 (rxon1->filter_flags == rxon2->filter_flags) &&
@@ -2965,89 +1695,14 @@ int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
2965 return rc; 1695 return rc;
2966} 1696}
2967 1697
2968#define RTS_HCCA_RETRY_LIMIT 3 1698static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
2969#define RTS_DFAULT_RETRY_LIMIT 60
2970
2971void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
2972 struct iwl_cmd *cmd,
2973 struct ieee80211_tx_control *ctrl,
2974 struct ieee80211_hdr *hdr, int sta_id,
2975 int is_hcca)
2976{
2977 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
2978 u8 rts_retry_limit = 0;
2979 u8 data_retry_limit = 0;
2980 u16 fc = le16_to_cpu(hdr->frame_control);
2981 u8 rate_plcp;
2982 u16 rate_flags = 0;
2983 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
2984
2985 rate_plcp = iwl4965_rates[rate_idx].plcp;
2986
2987 rts_retry_limit = (is_hcca) ?
2988 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2989
2990 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2991 rate_flags |= RATE_MCS_CCK_MSK;
2992
2993
2994 if (ieee80211_is_probe_response(fc)) {
2995 data_retry_limit = 3;
2996 if (data_retry_limit < rts_retry_limit)
2997 rts_retry_limit = data_retry_limit;
2998 } else
2999 data_retry_limit = IWL_DEFAULT_TX_RETRY;
3000
3001 if (priv->data_retry_limit != -1)
3002 data_retry_limit = priv->data_retry_limit;
3003
3004
3005 if (ieee80211_is_data(fc)) {
3006 tx->initial_rate_index = 0;
3007 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
3008 } else {
3009 switch (fc & IEEE80211_FCTL_STYPE) {
3010 case IEEE80211_STYPE_AUTH:
3011 case IEEE80211_STYPE_DEAUTH:
3012 case IEEE80211_STYPE_ASSOC_REQ:
3013 case IEEE80211_STYPE_REASSOC_REQ:
3014 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
3015 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
3016 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
3017 }
3018 break;
3019 default:
3020 break;
3021 }
3022
3023 /* Alternate between antenna A and B for successive frames */
3024 if (priv->use_ant_b_for_management_frame) {
3025 priv->use_ant_b_for_management_frame = 0;
3026 rate_flags |= RATE_MCS_ANT_B_MSK;
3027 } else {
3028 priv->use_ant_b_for_management_frame = 1;
3029 rate_flags |= RATE_MCS_ANT_A_MSK;
3030 }
3031 }
3032
3033 tx->rts_retry_limit = rts_retry_limit;
3034 tx->data_retry_limit = data_retry_limit;
3035 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
3036}
3037
3038int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
3039{ 1699{
3040 struct iwl4965_shared *s = priv->shared_virt; 1700 struct iwl4965_shared *s = priv->shared_virt;
3041 return le32_to_cpu(s->rb_closed) & 0xFFF; 1701 return le32_to_cpu(s->rb_closed) & 0xFFF;
3042} 1702}
3043 1703
3044int iwl4965_hw_get_temperature(struct iwl_priv *priv)
3045{
3046 return priv->temperature;
3047}
3048
3049unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv, 1704unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
3050 struct iwl4965_frame *frame, u8 rate) 1705 struct iwl_frame *frame, u8 rate)
3051{ 1706{
3052 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd; 1707 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
3053 unsigned int frame_size; 1708 unsigned int frame_size;
@@ -3060,7 +1715,7 @@ unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
3060 1715
3061 frame_size = iwl4965_fill_beacon_frame(priv, 1716 frame_size = iwl4965_fill_beacon_frame(priv,
3062 tx_beacon_cmd->frame, 1717 tx_beacon_cmd->frame,
3063 iwl4965_broadcast_addr, 1718 iwl_bcast_addr,
3064 sizeof(frame->u) - sizeof(*tx_beacon_cmd)); 1719 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
3065 1720
3066 BUG_ON(frame_size > MAX_MPDU_SIZE); 1721 BUG_ON(frame_size > MAX_MPDU_SIZE);
@@ -3068,105 +1723,45 @@ unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
3068 1723
3069 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP)) 1724 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
3070 tx_beacon_cmd->tx.rate_n_flags = 1725 tx_beacon_cmd->tx.rate_n_flags =
3071 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK); 1726 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
3072 else 1727 else
3073 tx_beacon_cmd->tx.rate_n_flags = 1728 tx_beacon_cmd->tx.rate_n_flags =
3074 iwl4965_hw_set_rate_n_flags(rate, 0); 1729 iwl_hw_set_rate_n_flags(rate, 0);
3075 1730
3076 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK | 1731 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
3077 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK); 1732 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
3078 return (sizeof(*tx_beacon_cmd) + frame_size); 1733 return (sizeof(*tx_beacon_cmd) + frame_size);
3079} 1734}
3080 1735
3081/* 1736static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
3082 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
3083 * given Tx queue, and enable the DMA channel used for that queue.
3084 *
3085 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3086 * channels supported in hardware.
3087 */
3088int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
3089{
3090 int rc;
3091 unsigned long flags;
3092 int txq_id = txq->q.id;
3093
3094 spin_lock_irqsave(&priv->lock, flags);
3095 rc = iwl_grab_nic_access(priv);
3096 if (rc) {
3097 spin_unlock_irqrestore(&priv->lock, flags);
3098 return rc;
3099 }
3100
3101 /* Circular buffer (TFD queue in DRAM) physical base address */
3102 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
3103 txq->q.dma_addr >> 8);
3104
3105 /* Enable DMA channel, using same id as for TFD queue */
3106 iwl_write_direct32(
3107 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
3108 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
3109 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
3110 iwl_release_nic_access(priv);
3111 spin_unlock_irqrestore(&priv->lock, flags);
3112
3113 return 0;
3114}
3115
3116int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
3117 dma_addr_t addr, u16 len)
3118{ 1737{
3119 int index, is_odd; 1738 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
3120 struct iwl4965_tfd_frame *tfd = ptr; 1739 sizeof(struct iwl4965_shared),
3121 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs); 1740 &priv->shared_phys);
3122 1741 if (!priv->shared_virt)
3123 /* Each TFD can point to a maximum 20 Tx buffers */ 1742 return -ENOMEM;
3124 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
3125 IWL_ERROR("Error can not send more than %d chunks\n",
3126 MAX_NUM_OF_TBS);
3127 return -EINVAL;
3128 }
3129
3130 index = num_tbs / 2;
3131 is_odd = num_tbs & 0x1;
3132 1743
3133 if (!is_odd) { 1744 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
3134 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
3135 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
3136 iwl_get_dma_hi_address(addr));
3137 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
3138 } else {
3139 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
3140 (u32) (addr & 0xffff));
3141 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
3142 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
3143 }
3144 1745
3145 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1); 1746 priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
3146 1747
3147 return 0; 1748 return 0;
3148} 1749}
3149 1750
3150static void iwl4965_hw_card_show_info(struct iwl_priv *priv) 1751static void iwl4965_free_shared_mem(struct iwl_priv *priv)
3151{ 1752{
3152 u16 hw_version = priv->eeprom.board_revision_4965; 1753 if (priv->shared_virt)
3153 1754 pci_free_consistent(priv->pci_dev,
3154 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n", 1755 sizeof(struct iwl4965_shared),
3155 ((hw_version >> 8) & 0x0F), 1756 priv->shared_virt,
3156 ((hw_version >> 8) >> 4), (hw_version & 0x00FF)); 1757 priv->shared_phys);
3157
3158 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
3159 priv->eeprom.board_pba_number_4965);
3160} 1758}
3161 1759
3162#define IWL_TX_CRC_SIZE 4
3163#define IWL_TX_DELIMITER_SIZE 4
3164
3165/** 1760/**
3166 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 1761 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
3167 */ 1762 */
3168static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv, 1763static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
3169 struct iwl4965_tx_queue *txq, 1764 struct iwl_tx_queue *txq,
3170 u16 byte_cnt) 1765 u16 byte_cnt)
3171{ 1766{
3172 int len; 1767 int len;
@@ -3180,50 +1775,13 @@ static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
3180 tfd_offset[txq->q.write_ptr], byte_cnt, len); 1775 tfd_offset[txq->q.write_ptr], byte_cnt, len);
3181 1776
3182 /* If within first 64 entries, duplicate at end */ 1777 /* If within first 64 entries, duplicate at end */
3183 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE) 1778 if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
3184 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 1779 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
3185 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr], 1780 tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
3186 byte_cnt, len); 1781 byte_cnt, len);
3187} 1782}
3188 1783
3189/** 1784/**
3190 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
3191 *
3192 * Selects how many and which Rx receivers/antennas/chains to use.
3193 * This should not be used for scan command ... it puts data in wrong place.
3194 */
3195void iwl4965_set_rxon_chain(struct iwl_priv *priv)
3196{
3197 u8 is_single = is_single_stream(priv);
3198 u8 idle_state, rx_state;
3199
3200 priv->staging_rxon.rx_chain = 0;
3201 rx_state = idle_state = 3;
3202
3203 /* Tell uCode which antennas are actually connected.
3204 * Before first association, we assume all antennas are connected.
3205 * Just after first association, iwl4965_noise_calibration()
3206 * checks which antennas actually *are* connected. */
3207 priv->staging_rxon.rx_chain |=
3208 cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
3209
3210 /* How many receivers should we use? */
3211 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
3212 priv->staging_rxon.rx_chain |=
3213 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
3214 priv->staging_rxon.rx_chain |=
3215 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
3216
3217 if (!is_single && (rx_state >= 2) &&
3218 !test_bit(STATUS_POWER_PMI, &priv->status))
3219 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
3220 else
3221 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
3222
3223 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
3224}
3225
3226/**
3227 * sign_extend - Sign extend a value using specified bit as sign-bit 1785 * sign_extend - Sign extend a value using specified bit as sign-bit
3228 * 1786 *
3229 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1 1787 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
@@ -3240,12 +1798,12 @@ static s32 sign_extend(u32 oper, int index)
3240} 1798}
3241 1799
3242/** 1800/**
3243 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin) 1801 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
3244 * @statistics: Provides the temperature reading from the uCode 1802 * @statistics: Provides the temperature reading from the uCode
3245 * 1803 *
3246 * A return of <0 indicates bogus data in the statistics 1804 * A return of <0 indicates bogus data in the statistics
3247 */ 1805 */
3248int iwl4965_get_temperature(const struct iwl_priv *priv) 1806static int iwl4965_hw_get_temperature(const struct iwl_priv *priv)
3249{ 1807{
3250 s32 temperature; 1808 s32 temperature;
3251 s32 vt; 1809 s32 vt;
@@ -3280,8 +1838,7 @@ int iwl4965_get_temperature(const struct iwl_priv *priv)
3280 vt = sign_extend( 1838 vt = sign_extend(
3281 le32_to_cpu(priv->statistics.general.temperature), 23); 1839 le32_to_cpu(priv->statistics.general.temperature), 23);
3282 1840
3283 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", 1841 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
3284 R1, R2, R3, vt);
3285 1842
3286 if (R3 == R1) { 1843 if (R3 == R1) {
3287 IWL_ERROR("Calibration conflict R1 == R3\n"); 1844 IWL_ERROR("Calibration conflict R1 == R3\n");
@@ -3292,11 +1849,10 @@ int iwl4965_get_temperature(const struct iwl_priv *priv)
3292 * Add offset to center the adjustment around 0 degrees Centigrade. */ 1849 * Add offset to center the adjustment around 0 degrees Centigrade. */
3293 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2); 1850 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
3294 temperature /= (R3 - R1); 1851 temperature /= (R3 - R1);
3295 temperature = (temperature * 97) / 100 + 1852 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
3296 TEMPERATURE_CALIB_KELVIN_OFFSET;
3297 1853
3298 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature, 1854 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n",
3299 KELVIN_TO_CELSIUS(temperature)); 1855 temperature, KELVIN_TO_CELSIUS(temperature));
3300 1856
3301 return temperature; 1857 return temperature;
3302} 1858}
@@ -3343,89 +1899,11 @@ static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
3343 return 1; 1899 return 1;
3344} 1900}
3345 1901
3346/* Calculate noise level, based on measurements during network silence just 1902static void iwl4965_temperature_calib(struct iwl_priv *priv)
3347 * before arriving beacon. This measurement can be done only if we know
3348 * exactly when to expect beacons, therefore only when we're associated. */
3349static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
3350{
3351 struct statistics_rx_non_phy *rx_info
3352 = &(priv->statistics.rx.general);
3353 int num_active_rx = 0;
3354 int total_silence = 0;
3355 int bcn_silence_a =
3356 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
3357 int bcn_silence_b =
3358 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
3359 int bcn_silence_c =
3360 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
3361
3362 if (bcn_silence_a) {
3363 total_silence += bcn_silence_a;
3364 num_active_rx++;
3365 }
3366 if (bcn_silence_b) {
3367 total_silence += bcn_silence_b;
3368 num_active_rx++;
3369 }
3370 if (bcn_silence_c) {
3371 total_silence += bcn_silence_c;
3372 num_active_rx++;
3373 }
3374
3375 /* Average among active antennas */
3376 if (num_active_rx)
3377 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
3378 else
3379 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3380
3381 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
3382 bcn_silence_a, bcn_silence_b, bcn_silence_c,
3383 priv->last_rx_noise);
3384}
3385
3386void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
3387{ 1903{
3388 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3389 int change;
3390 s32 temp; 1904 s32 temp;
3391 1905
3392 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n", 1906 temp = iwl4965_hw_get_temperature(priv);
3393 (int)sizeof(priv->statistics), pkt->len);
3394
3395 change = ((priv->statistics.general.temperature !=
3396 pkt->u.stats.general.temperature) ||
3397 ((priv->statistics.flag &
3398 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
3399 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
3400
3401 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
3402
3403 set_bit(STATUS_STATISTICS, &priv->status);
3404
3405 /* Reschedule the statistics timer to occur in
3406 * REG_RECALIB_PERIOD seconds to ensure we get a
3407 * thermal update even if the uCode doesn't give
3408 * us one */
3409 mod_timer(&priv->statistics_periodic, jiffies +
3410 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
3411
3412 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3413 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
3414 iwl4965_rx_calc_noise(priv);
3415#ifdef CONFIG_IWL4965_SENSITIVITY
3416 queue_work(priv->workqueue, &priv->sensitivity_work);
3417#endif
3418 }
3419
3420 iwl_leds_background(priv);
3421
3422 /* If the hardware hasn't reported a change in
3423 * temperature then don't bother computing a
3424 * calibrated temperature value */
3425 if (!change)
3426 return;
3427
3428 temp = iwl4965_get_temperature(priv);
3429 if (temp < 0) 1907 if (temp < 0)
3430 return; 1908 return;
3431 1909
@@ -3444,810 +1922,12 @@ void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffe
3444 priv->temperature = temp; 1922 priv->temperature = temp;
3445 set_bit(STATUS_TEMPERATURE, &priv->status); 1923 set_bit(STATUS_TEMPERATURE, &priv->status);
3446 1924
3447 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) && 1925 if (!priv->disable_tx_power_cal &&
3448 iwl4965_is_temp_calib_needed(priv)) 1926 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1927 iwl4965_is_temp_calib_needed(priv))
3449 queue_work(priv->workqueue, &priv->txpower_work); 1928 queue_work(priv->workqueue, &priv->txpower_work);
3450} 1929}
3451 1930
3452static void iwl4965_add_radiotap(struct iwl_priv *priv,
3453 struct sk_buff *skb,
3454 struct iwl4965_rx_phy_res *rx_start,
3455 struct ieee80211_rx_status *stats,
3456 u32 ampdu_status)
3457{
3458 s8 signal = stats->ssi;
3459 s8 noise = 0;
3460 int rate = stats->rate_idx;
3461 u64 tsf = stats->mactime;
3462 __le16 antenna;
3463 __le16 phy_flags_hw = rx_start->phy_flags;
3464 struct iwl4965_rt_rx_hdr {
3465 struct ieee80211_radiotap_header rt_hdr;
3466 __le64 rt_tsf; /* TSF */
3467 u8 rt_flags; /* radiotap packet flags */
3468 u8 rt_rate; /* rate in 500kb/s */
3469 __le16 rt_channelMHz; /* channel in MHz */
3470 __le16 rt_chbitmask; /* channel bitfield */
3471 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
3472 s8 rt_dbmnoise;
3473 u8 rt_antenna; /* antenna number */
3474 } __attribute__ ((packed)) *iwl4965_rt;
3475
3476 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
3477 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
3478 if (net_ratelimit())
3479 printk(KERN_ERR "not enough headroom [%d] for "
3480 "radiotap head [%zd]\n",
3481 skb_headroom(skb), sizeof(*iwl4965_rt));
3482 return;
3483 }
3484
3485 /* put radiotap header in front of 802.11 header and data */
3486 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
3487
3488 /* initialise radiotap header */
3489 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
3490 iwl4965_rt->rt_hdr.it_pad = 0;
3491
3492 /* total header + data */
3493 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
3494 &iwl4965_rt->rt_hdr.it_len);
3495
3496 /* Indicate all the fields we add to the radiotap header */
3497 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
3498 (1 << IEEE80211_RADIOTAP_FLAGS) |
3499 (1 << IEEE80211_RADIOTAP_RATE) |
3500 (1 << IEEE80211_RADIOTAP_CHANNEL) |
3501 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
3502 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
3503 (1 << IEEE80211_RADIOTAP_ANTENNA)),
3504 &iwl4965_rt->rt_hdr.it_present);
3505
3506 /* Zero the flags, we'll add to them as we go */
3507 iwl4965_rt->rt_flags = 0;
3508
3509 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
3510
3511 iwl4965_rt->rt_dbmsignal = signal;
3512 iwl4965_rt->rt_dbmnoise = noise;
3513
3514 /* Convert the channel frequency and set the flags */
3515 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
3516 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
3517 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3518 IEEE80211_CHAN_5GHZ),
3519 &iwl4965_rt->rt_chbitmask);
3520 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
3521 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
3522 IEEE80211_CHAN_2GHZ),
3523 &iwl4965_rt->rt_chbitmask);
3524 else /* 802.11g */
3525 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3526 IEEE80211_CHAN_2GHZ),
3527 &iwl4965_rt->rt_chbitmask);
3528
3529 if (rate == -1)
3530 iwl4965_rt->rt_rate = 0;
3531 else {
3532 if (stats->band == IEEE80211_BAND_5GHZ)
3533 rate += IWL_FIRST_OFDM_RATE;
3534
3535 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
3536 }
3537
3538 /*
3539 * "antenna number"
3540 *
3541 * It seems that the antenna field in the phy flags value
3542 * is actually a bitfield. This is undefined by radiotap,
3543 * it wants an actual antenna number but I always get "7"
3544 * for most legacy frames I receive indicating that the
3545 * same frame was received on all three RX chains.
3546 *
3547 * I think this field should be removed in favour of a
3548 * new 802.11n radiotap field "RX chains" that is defined
3549 * as a bitmask.
3550 */
3551 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
3552 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
3553
3554 /* set the preamble flag if appropriate */
3555 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
3556 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3557
3558 stats->flag |= RX_FLAG_RADIOTAP;
3559}
3560
3561static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
3562{
3563 /* 0 - mgmt, 1 - cnt, 2 - data */
3564 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
3565 priv->rx_stats[idx].cnt++;
3566 priv->rx_stats[idx].bytes += len;
3567}
3568
3569static u32 iwl4965_translate_rx_status(u32 decrypt_in)
3570{
3571 u32 decrypt_out = 0;
3572
3573 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
3574 RX_RES_STATUS_STATION_FOUND)
3575 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
3576 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
3577
3578 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
3579
3580 /* packet was not encrypted */
3581 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
3582 RX_RES_STATUS_SEC_TYPE_NONE)
3583 return decrypt_out;
3584
3585 /* packet was encrypted with unknown alg */
3586 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
3587 RX_RES_STATUS_SEC_TYPE_ERR)
3588 return decrypt_out;
3589
3590 /* decryption was not done in HW */
3591 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
3592 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
3593 return decrypt_out;
3594
3595 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
3596
3597 case RX_RES_STATUS_SEC_TYPE_CCMP:
3598 /* alg is CCM: check MIC only */
3599 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
3600 /* Bad MIC */
3601 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
3602 else
3603 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
3604
3605 break;
3606
3607 case RX_RES_STATUS_SEC_TYPE_TKIP:
3608 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
3609 /* Bad TTAK */
3610 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
3611 break;
3612 }
3613 /* fall through if TTAK OK */
3614 default:
3615 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
3616 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
3617 else
3618 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
3619 break;
3620 };
3621
3622 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
3623 decrypt_in, decrypt_out);
3624
3625 return decrypt_out;
3626}
3627
3628static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
3629 int include_phy,
3630 struct iwl4965_rx_mem_buffer *rxb,
3631 struct ieee80211_rx_status *stats)
3632{
3633 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
3634 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3635 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
3636 struct ieee80211_hdr *hdr;
3637 u16 len;
3638 __le32 *rx_end;
3639 unsigned int skblen;
3640 u32 ampdu_status;
3641 u32 ampdu_status_legacy;
3642
3643 if (!include_phy && priv->last_phy_res[0])
3644 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3645
3646 if (!rx_start) {
3647 IWL_ERROR("MPDU frame without a PHY data\n");
3648 return;
3649 }
3650 if (include_phy) {
3651 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3652 rx_start->cfg_phy_cnt);
3653
3654 len = le16_to_cpu(rx_start->byte_count);
3655
3656 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3657 sizeof(struct iwl4965_rx_phy_res) +
3658 rx_start->cfg_phy_cnt + len);
3659
3660 } else {
3661 struct iwl4965_rx_mpdu_res_start *amsdu =
3662 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3663
3664 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3665 sizeof(struct iwl4965_rx_mpdu_res_start));
3666 len = le16_to_cpu(amsdu->byte_count);
3667 rx_start->byte_count = amsdu->byte_count;
3668 rx_end = (__le32 *) (((u8 *) hdr) + len);
3669 }
3670 if (len > priv->hw_params.max_pkt_size || len < 16) {
3671 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
3672 return;
3673 }
3674
3675 ampdu_status = le32_to_cpu(*rx_end);
3676 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3677
3678 if (!include_phy) {
3679 /* New status scheme, need to translate */
3680 ampdu_status_legacy = ampdu_status;
3681 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3682 }
3683
3684 /* start from MAC */
3685 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3686 skb_put(rxb->skb, len); /* end where data ends */
3687
3688 /* We only process data packets if the interface is open */
3689 if (unlikely(!priv->is_open)) {
3690 IWL_DEBUG_DROP_LIMIT
3691 ("Dropping packet while interface is not open.\n");
3692 return;
3693 }
3694
3695 stats->flag = 0;
3696 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3697
3698 if (!priv->cfg->mod_params->sw_crypto)
3699 iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
3700
3701 if (priv->add_radiotap)
3702 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3703
3704 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
3705 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3706 priv->alloc_rxb_skb--;
3707 rxb->skb = NULL;
3708}
3709
3710/* Calc max signal level (dBm) among 3 possible receivers */
3711static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3712{
3713 /* data from PHY/DSP regarding signal strength, etc.,
3714 * contents are always there, not configurable by host. */
3715 struct iwl4965_rx_non_cfg_phy *ncphy =
3716 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3717 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3718 >> IWL_AGC_DB_POS;
3719
3720 u32 valid_antennae =
3721 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3722 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3723 u8 max_rssi = 0;
3724 u32 i;
3725
3726 /* Find max rssi among 3 possible receivers.
3727 * These values are measured by the digital signal processor (DSP).
3728 * They should stay fairly constant even as the signal strength varies,
3729 * if the radio's automatic gain control (AGC) is working right.
3730 * AGC value (see below) will provide the "interesting" info. */
3731 for (i = 0; i < 3; i++)
3732 if (valid_antennae & (1 << i))
3733 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3734
3735 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3736 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3737 max_rssi, agc);
3738
3739 /* dBm = max_rssi dB - agc dB - constant.
3740 * Higher AGC (higher radio gain) means lower signal. */
3741 return (max_rssi - agc - IWL_RSSI_OFFSET);
3742}
3743
3744#ifdef CONFIG_IWL4965_HT
3745
3746void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
3747 struct ieee80211_ht_info *ht_info,
3748 enum ieee80211_band band)
3749{
3750 ht_info->cap = 0;
3751 memset(ht_info->supp_mcs_set, 0, 16);
3752
3753 ht_info->ht_supported = 1;
3754
3755 if (band == IEEE80211_BAND_5GHZ) {
3756 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3757 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3758 ht_info->supp_mcs_set[4] = 0x01;
3759 }
3760 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3761 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3762 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3763 (IWL_MIMO_PS_NONE << 2));
3764
3765 if (priv->cfg->mod_params->amsdu_size_8K)
3766 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
3767
3768 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3769 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3770
3771 ht_info->supp_mcs_set[0] = 0xFF;
3772 ht_info->supp_mcs_set[1] = 0xFF;
3773}
3774#endif /* CONFIG_IWL4965_HT */
3775
3776static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
3777{
3778 unsigned long flags;
3779
3780 spin_lock_irqsave(&priv->sta_lock, flags);
3781 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3782 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3783 priv->stations[sta_id].sta.sta.modify_mask = 0;
3784 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3785 spin_unlock_irqrestore(&priv->sta_lock, flags);
3786
3787 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
3788}
3789
3790static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
3791{
3792 /* FIXME: need locking over ps_status ??? */
3793 u8 sta_id = iwl4965_hw_find_station(priv, addr);
3794
3795 if (sta_id != IWL_INVALID_STATION) {
3796 u8 sta_awake = priv->stations[sta_id].
3797 ps_status == STA_PS_STATUS_WAKE;
3798
3799 if (sta_awake && ps_bit)
3800 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3801 else if (!sta_awake && !ps_bit) {
3802 iwl4965_sta_modify_ps_wake(priv, sta_id);
3803 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3804 }
3805 }
3806}
3807#ifdef CONFIG_IWLWIFI_DEBUG
3808
3809/**
3810 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3811 *
3812 * You may hack this function to show different aspects of received frames,
3813 * including selective frame dumps.
3814 * group100 parameter selects whether to show 1 out of 100 good frames.
3815 *
3816 * TODO: This was originally written for 3945, need to audit for
3817 * proper operation with 4965.
3818 */
3819static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3820 struct iwl4965_rx_packet *pkt,
3821 struct ieee80211_hdr *header, int group100)
3822{
3823 u32 to_us;
3824 u32 print_summary = 0;
3825 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3826 u32 hundred = 0;
3827 u32 dataframe = 0;
3828 u16 fc;
3829 u16 seq_ctl;
3830 u16 channel;
3831 u16 phy_flags;
3832 int rate_sym;
3833 u16 length;
3834 u16 status;
3835 u16 bcn_tmr;
3836 u32 tsf_low;
3837 u64 tsf;
3838 u8 rssi;
3839 u8 agc;
3840 u16 sig_avg;
3841 u16 noise_diff;
3842 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3843 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3844 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3845 u8 *data = IWL_RX_DATA(pkt);
3846
3847 if (likely(!(iwl_debug_level & IWL_DL_RX)))
3848 return;
3849
3850 /* MAC header */
3851 fc = le16_to_cpu(header->frame_control);
3852 seq_ctl = le16_to_cpu(header->seq_ctrl);
3853
3854 /* metadata */
3855 channel = le16_to_cpu(rx_hdr->channel);
3856 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3857 rate_sym = rx_hdr->rate;
3858 length = le16_to_cpu(rx_hdr->len);
3859
3860 /* end-of-frame status and timestamp */
3861 status = le32_to_cpu(rx_end->status);
3862 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3863 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3864 tsf = le64_to_cpu(rx_end->timestamp);
3865
3866 /* signal statistics */
3867 rssi = rx_stats->rssi;
3868 agc = rx_stats->agc;
3869 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3870 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3871
3872 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3873
3874 /* if data frame is to us and all is good,
3875 * (optionally) print summary for only 1 out of every 100 */
3876 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3877 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3878 dataframe = 1;
3879 if (!group100)
3880 print_summary = 1; /* print each frame */
3881 else if (priv->framecnt_to_us < 100) {
3882 priv->framecnt_to_us++;
3883 print_summary = 0;
3884 } else {
3885 priv->framecnt_to_us = 0;
3886 print_summary = 1;
3887 hundred = 1;
3888 }
3889 } else {
3890 /* print summary for all other frames */
3891 print_summary = 1;
3892 }
3893
3894 if (print_summary) {
3895 char *title;
3896 int rate_idx;
3897 u32 bitrate;
3898
3899 if (hundred)
3900 title = "100Frames";
3901 else if (fc & IEEE80211_FCTL_RETRY)
3902 title = "Retry";
3903 else if (ieee80211_is_assoc_response(fc))
3904 title = "AscRsp";
3905 else if (ieee80211_is_reassoc_response(fc))
3906 title = "RasRsp";
3907 else if (ieee80211_is_probe_response(fc)) {
3908 title = "PrbRsp";
3909 print_dump = 1; /* dump frame contents */
3910 } else if (ieee80211_is_beacon(fc)) {
3911 title = "Beacon";
3912 print_dump = 1; /* dump frame contents */
3913 } else if (ieee80211_is_atim(fc))
3914 title = "ATIM";
3915 else if (ieee80211_is_auth(fc))
3916 title = "Auth";
3917 else if (ieee80211_is_deauth(fc))
3918 title = "DeAuth";
3919 else if (ieee80211_is_disassoc(fc))
3920 title = "DisAssoc";
3921 else
3922 title = "Frame";
3923
3924 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3925 if (unlikely(rate_idx == -1))
3926 bitrate = 0;
3927 else
3928 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3929
3930 /* print frame summary.
3931 * MAC addresses show just the last byte (for brevity),
3932 * but you can hack it to show more, if you'd like to. */
3933 if (dataframe)
3934 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3935 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3936 title, fc, header->addr1[5],
3937 length, rssi, channel, bitrate);
3938 else {
3939 /* src/dst addresses assume managed mode */
3940 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3941 "src=0x%02x, rssi=%u, tim=%lu usec, "
3942 "phy=0x%02x, chnl=%d\n",
3943 title, fc, header->addr1[5],
3944 header->addr3[5], rssi,
3945 tsf_low - priv->scan_start_tsf,
3946 phy_flags, channel);
3947 }
3948 }
3949 if (print_dump)
3950 iwl_print_hex_dump(IWL_DL_RX, data, length);
3951}
3952#else
3953static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3954 struct iwl4965_rx_packet *pkt,
3955 struct ieee80211_hdr *header,
3956 int group100)
3957{
3958}
3959#endif
3960
3961
3962
3963/* Called for REPLY_RX (legacy ABG frames), or
3964 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
3965static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
3966 struct iwl4965_rx_mem_buffer *rxb)
3967{
3968 struct ieee80211_hdr *header;
3969 struct ieee80211_rx_status rx_status;
3970 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3971 /* Use phy data (Rx signal strength, etc.) contained within
3972 * this rx packet for legacy frames,
3973 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
3974 int include_phy = (pkt->hdr.cmd == REPLY_RX);
3975 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3976 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3977 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3978 __le32 *rx_end;
3979 unsigned int len = 0;
3980 u16 fc;
3981 u8 network_packet;
3982
3983 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
3984 rx_status.freq =
3985 ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
3986 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3987 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
3988 rx_status.rate_idx =
3989 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
3990 if (rx_status.band == IEEE80211_BAND_5GHZ)
3991 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3992
3993 rx_status.antenna = 0;
3994 rx_status.flag = 0;
3995
3996 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
3997 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3998 rx_start->cfg_phy_cnt);
3999 return;
4000 }
4001
4002 if (!include_phy) {
4003 if (priv->last_phy_res[0])
4004 rx_start = (struct iwl4965_rx_phy_res *)
4005 &priv->last_phy_res[1];
4006 else
4007 rx_start = NULL;
4008 }
4009
4010 if (!rx_start) {
4011 IWL_ERROR("MPDU frame without a PHY data\n");
4012 return;
4013 }
4014
4015 if (include_phy) {
4016 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
4017 + rx_start->cfg_phy_cnt);
4018
4019 len = le16_to_cpu(rx_start->byte_count);
4020 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
4021 sizeof(struct iwl4965_rx_phy_res) + len);
4022 } else {
4023 struct iwl4965_rx_mpdu_res_start *amsdu =
4024 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
4025
4026 header = (void *)(pkt->u.raw +
4027 sizeof(struct iwl4965_rx_mpdu_res_start));
4028 len = le16_to_cpu(amsdu->byte_count);
4029 rx_end = (__le32 *) (pkt->u.raw +
4030 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
4031 }
4032
4033 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
4034 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
4035 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
4036 le32_to_cpu(*rx_end));
4037 return;
4038 }
4039
4040 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
4041
4042 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
4043 rx_status.ssi = iwl4965_calc_rssi(rx_start);
4044
4045 /* Meaningful noise values are available only from beacon statistics,
4046 * which are gathered only when associated, and indicate noise
4047 * only for the associated network channel ...
4048 * Ignore these noise values while scanning (other channels) */
4049 if (iwl_is_associated(priv) &&
4050 !test_bit(STATUS_SCANNING, &priv->status)) {
4051 rx_status.noise = priv->last_rx_noise;
4052 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
4053 rx_status.noise);
4054 } else {
4055 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
4056 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
4057 }
4058
4059 /* Reset beacon noise level if not associated. */
4060 if (!iwl_is_associated(priv))
4061 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
4062
4063 /* Set "1" to report good data frames in groups of 100 */
4064 /* FIXME: need to optimze the call: */
4065 iwl4965_dbg_report_frame(priv, pkt, header, 1);
4066
4067 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
4068 rx_status.ssi, rx_status.noise, rx_status.signal,
4069 (unsigned long long)rx_status.mactime);
4070
4071 network_packet = iwl4965_is_network_packet(priv, header);
4072 if (network_packet) {
4073 priv->last_rx_rssi = rx_status.ssi;
4074 priv->last_beacon_time = priv->ucode_beacon_time;
4075 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
4076 }
4077
4078 fc = le16_to_cpu(header->frame_control);
4079 switch (fc & IEEE80211_FCTL_FTYPE) {
4080 case IEEE80211_FTYPE_MGMT:
4081 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
4082 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
4083 header->addr2);
4084 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
4085 break;
4086
4087 case IEEE80211_FTYPE_CTL:
4088#ifdef CONFIG_IWL4965_HT
4089 switch (fc & IEEE80211_FCTL_STYPE) {
4090 case IEEE80211_STYPE_BACK_REQ:
4091 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
4092 iwl4965_handle_data_packet(priv, 0, include_phy,
4093 rxb, &rx_status);
4094 break;
4095 default:
4096 break;
4097 }
4098#endif
4099 break;
4100
4101 case IEEE80211_FTYPE_DATA: {
4102 DECLARE_MAC_BUF(mac1);
4103 DECLARE_MAC_BUF(mac2);
4104 DECLARE_MAC_BUF(mac3);
4105
4106 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
4107 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
4108 header->addr2);
4109
4110 if (unlikely(!network_packet))
4111 IWL_DEBUG_DROP("Dropping (non network): "
4112 "%s, %s, %s\n",
4113 print_mac(mac1, header->addr1),
4114 print_mac(mac2, header->addr2),
4115 print_mac(mac3, header->addr3));
4116 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
4117 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
4118 print_mac(mac1, header->addr1),
4119 print_mac(mac2, header->addr2),
4120 print_mac(mac3, header->addr3));
4121 else
4122 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
4123 &rx_status);
4124 break;
4125 }
4126 default:
4127 break;
4128
4129 }
4130}
4131
4132/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
4133 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
4134static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
4135 struct iwl4965_rx_mem_buffer *rxb)
4136{
4137 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4138 priv->last_phy_res[0] = 1;
4139 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
4140 sizeof(struct iwl4965_rx_phy_res));
4141}
4142static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
4143 struct iwl4965_rx_mem_buffer *rxb)
4144
4145{
4146#ifdef CONFIG_IWL4965_SENSITIVITY
4147 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4148 struct iwl4965_missed_beacon_notif *missed_beacon;
4149
4150 missed_beacon = &pkt->u.missed_beacon;
4151 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
4152 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
4153 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
4154 le32_to_cpu(missed_beacon->total_missed_becons),
4155 le32_to_cpu(missed_beacon->num_recvd_beacons),
4156 le32_to_cpu(missed_beacon->num_expected_beacons));
4157 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
4158 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
4159 queue_work(priv->workqueue, &priv->sensitivity_work);
4160 }
4161#endif /*CONFIG_IWL4965_SENSITIVITY*/
4162}
4163#ifdef CONFIG_IWL4965_HT
4164
4165/**
4166 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
4167 */
4168static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
4169 int sta_id, int tid)
4170{
4171 unsigned long flags;
4172
4173 /* Remove "disable" flag, to enable Tx for this TID */
4174 spin_lock_irqsave(&priv->sta_lock, flags);
4175 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
4176 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
4177 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4178 spin_unlock_irqrestore(&priv->sta_lock, flags);
4179
4180 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
4181}
4182
4183/**
4184 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
4185 *
4186 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
4187 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
4188 */
4189static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
4190 struct iwl4965_ht_agg *agg,
4191 struct iwl4965_compressed_ba_resp*
4192 ba_resp)
4193
4194{
4195 int i, sh, ack;
4196 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
4197 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
4198 u64 bitmap;
4199 int successes = 0;
4200 struct ieee80211_tx_status *tx_status;
4201
4202 if (unlikely(!agg->wait_for_ba)) {
4203 IWL_ERROR("Received BA when not expected\n");
4204 return -EINVAL;
4205 }
4206
4207 /* Mark that the expected block-ack response arrived */
4208 agg->wait_for_ba = 0;
4209 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
4210
4211 /* Calculate shift to align block-ack bits with our Tx window bits */
4212 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
4213 if (sh < 0) /* tbw something is wrong with indices */
4214 sh += 0x100;
4215
4216 /* don't use 64-bit values for now */
4217 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
4218
4219 if (agg->frame_count > (64 - sh)) {
4220 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
4221 return -1;
4222 }
4223
4224 /* check for success or failure according to the
4225 * transmitted bitmap and block-ack bitmap */
4226 bitmap &= agg->bitmap;
4227
4228 /* For each frame attempted in aggregation,
4229 * update driver's record of tx frame's status. */
4230 for (i = 0; i < agg->frame_count ; i++) {
4231 ack = bitmap & (1 << i);
4232 successes += !!ack;
4233 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
4234 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
4235 agg->start_idx + i);
4236 }
4237
4238 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
4239 tx_status->flags = IEEE80211_TX_STATUS_ACK;
4240 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
4241 tx_status->ampdu_ack_map = successes;
4242 tx_status->ampdu_ack_len = agg->frame_count;
4243 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
4244 &tx_status->control);
4245
4246 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
4247
4248 return 0;
4249}
4250
4251/** 1931/**
4252 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration 1932 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
4253 */ 1933 */
@@ -4258,22 +1938,24 @@ static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
4258 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 1938 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
4259 iwl_write_prph(priv, 1939 iwl_write_prph(priv,
4260 IWL49_SCD_QUEUE_STATUS_BITS(txq_id), 1940 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
4261 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| 1941 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
4262 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 1942 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
4263} 1943}
4264 1944
4265/** 1945/**
4266 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID 1946 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
4267 * priv->lock must be held by the caller 1947 * priv->lock must be held by the caller
4268 */ 1948 */
4269static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id, 1949static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
4270 u16 ssn_idx, u8 tx_fifo) 1950 u16 ssn_idx, u8 tx_fifo)
4271{ 1951{
4272 int ret = 0; 1952 int ret = 0;
4273 1953
4274 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) { 1954 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
4275 IWL_WARNING("queue number too small: %d, must be > %d\n", 1955 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
4276 txq_id, IWL_BACK_QUEUE_FIRST_ID); 1956 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1957 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1958 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
4277 return -EINVAL; 1959 return -EINVAL;
4278 } 1960 }
4279 1961
@@ -4291,7 +1973,7 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
4291 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); 1973 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4292 1974
4293 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id)); 1975 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
4294 iwl4965_txq_ctx_deactivate(priv, txq_id); 1976 iwl_txq_ctx_deactivate(priv, txq_id);
4295 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 1977 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
4296 1978
4297 iwl_release_nic_access(priv); 1979 iwl_release_nic_access(priv);
@@ -4299,121 +1981,6 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
4299 return 0; 1981 return 0;
4300} 1982}
4301 1983
4302int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
4303 u8 tid, int txq_id)
4304{
4305 struct iwl4965_queue *q = &priv->txq[txq_id].q;
4306 u8 *addr = priv->stations[sta_id].sta.sta.addr;
4307 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
4308
4309 switch (priv->stations[sta_id].tid[tid].agg.state) {
4310 case IWL_EMPTYING_HW_QUEUE_DELBA:
4311 /* We are reclaiming the last packet of the */
4312 /* aggregated HW queue */
4313 if (txq_id == tid_data->agg.txq_id &&
4314 q->read_ptr == q->write_ptr) {
4315 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
4316 int tx_fifo = default_tid_to_tx_fifo[tid];
4317 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
4318 iwl4965_tx_queue_agg_disable(priv, txq_id,
4319 ssn, tx_fifo);
4320 tid_data->agg.state = IWL_AGG_OFF;
4321 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4322 }
4323 break;
4324 case IWL_EMPTYING_HW_QUEUE_ADDBA:
4325 /* We are reclaiming the last packet of the queue */
4326 if (tid_data->tfds_in_queue == 0) {
4327 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
4328 tid_data->agg.state = IWL_AGG_ON;
4329 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4330 }
4331 break;
4332 }
4333 return 0;
4334}
4335
4336/**
4337 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
4338 * @index -- current index
4339 * @n_bd -- total number of entries in queue (s/b power of 2)
4340 */
4341static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
4342{
4343 return (index == 0) ? n_bd - 1 : index - 1;
4344}
4345
4346/**
4347 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
4348 *
4349 * Handles block-acknowledge notification from device, which reports success
4350 * of frames sent via aggregation.
4351 */
4352static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
4353 struct iwl4965_rx_mem_buffer *rxb)
4354{
4355 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4356 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
4357 int index;
4358 struct iwl4965_tx_queue *txq = NULL;
4359 struct iwl4965_ht_agg *agg;
4360 DECLARE_MAC_BUF(mac);
4361
4362 /* "flow" corresponds to Tx queue */
4363 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
4364
4365 /* "ssn" is start of block-ack Tx window, corresponds to index
4366 * (in Tx queue's circular buffer) of first TFD/frame in window */
4367 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
4368
4369 if (scd_flow >= priv->hw_params.max_txq_num) {
4370 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
4371 return;
4372 }
4373
4374 txq = &priv->txq[scd_flow];
4375 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
4376
4377 /* Find index just before block-ack window */
4378 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
4379
4380 /* TODO: Need to get this copy more safely - now good for debug */
4381
4382 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
4383 "sta_id = %d\n",
4384 agg->wait_for_ba,
4385 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
4386 ba_resp->sta_id);
4387 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
4388 "%d, scd_ssn = %d\n",
4389 ba_resp->tid,
4390 ba_resp->seq_ctl,
4391 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
4392 ba_resp->scd_flow,
4393 ba_resp->scd_ssn);
4394 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
4395 agg->start_idx,
4396 (unsigned long long)agg->bitmap);
4397
4398 /* Update driver's record of ACK vs. not for each frame in window */
4399 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
4400
4401 /* Release all TFDs before the SSN, i.e. all TFDs in front of
4402 * block-ack window (we assume that they've been successfully
4403 * transmitted ... if not, it's too late anyway). */
4404 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
4405 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
4406 priv->stations[ba_resp->sta_id].
4407 tid[ba_resp->tid].tfds_in_queue -= freed;
4408 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
4409 priv->mac80211_registered &&
4410 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
4411 ieee80211_wake_queue(priv->hw, scd_flow);
4412 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
4413 ba_resp->tid, scd_flow);
4414 }
4415}
4416
4417/** 1984/**
4418 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue 1985 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
4419 */ 1986 */
@@ -4424,10 +1991,10 @@ static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
4424 u32 tbl_dw; 1991 u32 tbl_dw;
4425 u16 scd_q2ratid; 1992 u16 scd_q2ratid;
4426 1993
4427 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1994 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
4428 1995
4429 tbl_dw_addr = priv->scd_base_addr + 1996 tbl_dw_addr = priv->scd_base_addr +
4430 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 1997 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
4431 1998
4432 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); 1999 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
4433 2000
@@ -4445,31 +2012,34 @@ static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
4445/** 2012/**
4446 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue 2013 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
4447 * 2014 *
4448 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID, 2015 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
4449 * i.e. it must be one of the higher queues used for aggregation 2016 * i.e. it must be one of the higher queues used for aggregation
4450 */ 2017 */
4451static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id, 2018static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
4452 int tx_fifo, int sta_id, int tid, 2019 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
4453 u16 ssn_idx)
4454{ 2020{
4455 unsigned long flags; 2021 unsigned long flags;
4456 int rc; 2022 int ret;
4457 u16 ra_tid; 2023 u16 ra_tid;
4458 2024
4459 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) 2025 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
4460 IWL_WARNING("queue number too small: %d, must be > %d\n", 2026 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
4461 txq_id, IWL_BACK_QUEUE_FIRST_ID); 2027 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
2028 txq_id, IWL49_FIRST_AMPDU_QUEUE,
2029 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
2030 return -EINVAL;
2031 }
4462 2032
4463 ra_tid = BUILD_RAxTID(sta_id, tid); 2033 ra_tid = BUILD_RAxTID(sta_id, tid);
4464 2034
4465 /* Modify device's station table to Tx this TID */ 2035 /* Modify device's station table to Tx this TID */
4466 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid); 2036 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
4467 2037
4468 spin_lock_irqsave(&priv->lock, flags); 2038 spin_lock_irqsave(&priv->lock, flags);
4469 rc = iwl_grab_nic_access(priv); 2039 ret = iwl_grab_nic_access(priv);
4470 if (rc) { 2040 if (ret) {
4471 spin_unlock_irqrestore(&priv->lock, flags); 2041 spin_unlock_irqrestore(&priv->lock, flags);
4472 return rc; 2042 return ret;
4473 } 2043 }
4474 2044
4475 /* Stop this Tx queue before configuring it */ 2045 /* Stop this Tx queue before configuring it */
@@ -4489,14 +2059,14 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4489 2059
4490 /* Set up Tx window size and frame limit for this queue */ 2060 /* Set up Tx window size and frame limit for this queue */
4491 iwl_write_targ_mem(priv, 2061 iwl_write_targ_mem(priv,
4492 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id), 2062 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
4493 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & 2063 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4494 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 2064 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
4495 2065
4496 iwl_write_targ_mem(priv, priv->scd_base_addr + 2066 iwl_write_targ_mem(priv, priv->scd_base_addr +
4497 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 2067 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
4498 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) 2068 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
4499 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 2069 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4500 2070
4501 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id)); 2071 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
4502 2072
@@ -4509,444 +2079,313 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4509 return 0; 2079 return 0;
4510} 2080}
4511 2081
4512#endif /* CONFIG_IWL4965_HT */ 2082int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4513 2083 enum ieee80211_ampdu_mlme_action action,
4514/** 2084 const u8 *addr, u16 tid, u16 *ssn)
4515 * iwl4965_add_station - Initialize a station's hardware rate table
4516 *
4517 * The uCode's station table contains a table of fallback rates
4518 * for automatic fallback during transmission.
4519 *
4520 * NOTE: This sets up a default set of values. These will be replaced later
4521 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
4522 * rc80211_simple.
4523 *
4524 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
4525 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
4526 * which requires station table entry to exist).
4527 */
4528void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
4529{
4530 int i, r;
4531 struct iwl_link_quality_cmd link_cmd = {
4532 .reserved1 = 0,
4533 };
4534 u16 rate_flags;
4535
4536 /* Set up the rate scaling to start at selected rate, fall back
4537 * all the way down to 1M in IEEE order, and then spin on 1M */
4538 if (is_ap)
4539 r = IWL_RATE_54M_INDEX;
4540 else if (priv->band == IEEE80211_BAND_5GHZ)
4541 r = IWL_RATE_6M_INDEX;
4542 else
4543 r = IWL_RATE_1M_INDEX;
4544
4545 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
4546 rate_flags = 0;
4547 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
4548 rate_flags |= RATE_MCS_CCK_MSK;
4549
4550 /* Use Tx antenna B only */
4551 rate_flags |= RATE_MCS_ANT_B_MSK;
4552 rate_flags &= ~RATE_MCS_ANT_A_MSK;
4553
4554 link_cmd.rs_table[i].rate_n_flags =
4555 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
4556 r = iwl4965_get_prev_ieee_rate(r);
4557 }
4558
4559 link_cmd.general_params.single_stream_ant_msk = 2;
4560 link_cmd.general_params.dual_stream_ant_msk = 3;
4561 link_cmd.agg_params.agg_dis_start_th = 3;
4562 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
4563
4564 /* Update the rate scaling for control frame Tx to AP */
4565 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
4566
4567 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
4568 sizeof(link_cmd), &link_cmd, NULL);
4569}
4570
4571#ifdef CONFIG_IWL4965_HT
4572
4573static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
4574 enum ieee80211_band band,
4575 u16 channel, u8 extension_chan_offset)
4576{
4577 const struct iwl_channel_info *ch_info;
4578
4579 ch_info = iwl_get_channel_info(priv, band, channel);
4580 if (!is_channel_valid(ch_info))
4581 return 0;
4582
4583 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
4584 return 0;
4585
4586 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
4587 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
4588 return 1;
4589
4590 return 0;
4591}
4592
4593static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
4594 struct ieee80211_ht_info *sta_ht_inf)
4595{
4596 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
4597
4598 if ((!iwl_ht_conf->is_ht) ||
4599 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
4600 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
4601 return 0;
4602
4603 if (sta_ht_inf) {
4604 if ((!sta_ht_inf->ht_supported) ||
4605 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
4606 return 0;
4607 }
4608
4609 return (iwl4965_is_channel_extension(priv, priv->band,
4610 iwl_ht_conf->control_channel,
4611 iwl_ht_conf->extension_chan_offset));
4612}
4613
4614void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
4615{ 2085{
4616 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon; 2086 struct iwl_priv *priv = hw->priv;
4617 u32 val; 2087 DECLARE_MAC_BUF(mac);
4618 2088
4619 if (!ht_info->is_ht) 2089 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
4620 return; 2090 print_mac(mac, addr), tid);
4621 2091
4622 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */ 2092 if (!(priv->cfg->sku & IWL_SKU_N))
4623 if (iwl4965_is_fat_tx_allowed(priv, NULL)) 2093 return -EACCES;
4624 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4625 else
4626 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4627 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
4628
4629 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
4630 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
4631 le16_to_cpu(rxon->channel),
4632 ht_info->control_channel);
4633 rxon->channel = cpu_to_le16(ht_info->control_channel);
4634 return;
4635 }
4636 2094
4637 /* Note: control channel is opposite of extension channel */ 2095 switch (action) {
4638 switch (ht_info->extension_chan_offset) { 2096 case IEEE80211_AMPDU_RX_START:
4639 case IWL_EXT_CHANNEL_OFFSET_ABOVE: 2097 IWL_DEBUG_HT("start Rx\n");
4640 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); 2098 return iwl_rx_agg_start(priv, addr, tid, *ssn);
4641 break; 2099 case IEEE80211_AMPDU_RX_STOP:
4642 case IWL_EXT_CHANNEL_OFFSET_BELOW: 2100 IWL_DEBUG_HT("stop Rx\n");
4643 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; 2101 return iwl_rx_agg_stop(priv, addr, tid);
4644 break; 2102 case IEEE80211_AMPDU_TX_START:
4645 case IWL_EXT_CHANNEL_OFFSET_NONE: 2103 IWL_DEBUG_HT("start Tx\n");
2104 return iwl_tx_agg_start(priv, addr, tid, ssn);
2105 case IEEE80211_AMPDU_TX_STOP:
2106 IWL_DEBUG_HT("stop Tx\n");
2107 return iwl_tx_agg_stop(priv, addr, tid);
4646 default: 2108 default:
4647 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK; 2109 IWL_DEBUG_HT("unknown\n");
2110 return -EINVAL;
4648 break; 2111 break;
4649 } 2112 }
4650 2113 return 0;
4651 val = ht_info->ht_protection;
4652
4653 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4654
4655 iwl4965_set_rxon_chain(priv);
4656
4657 IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
4658 "rxon flags 0x%X operation mode :0x%X "
4659 "extension channel offset 0x%x "
4660 "control chan %d\n",
4661 ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
4662 le32_to_cpu(rxon->flags), ht_info->ht_protection,
4663 ht_info->extension_chan_offset,
4664 ht_info->control_channel);
4665 return;
4666} 2114}
4667 2115
4668void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index, 2116static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
4669 struct ieee80211_ht_info *sta_ht_inf)
4670{ 2117{
4671 __le32 sta_flags; 2118 switch (cmd_id) {
4672 u8 mimo_ps_mode; 2119 case REPLY_RXON:
4673 2120 return (u16) sizeof(struct iwl4965_rxon_cmd);
4674 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
4675 goto done;
4676
4677 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4678
4679 sta_flags = priv->stations[index].sta.station_flags;
4680
4681 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4682
4683 switch (mimo_ps_mode) {
4684 case WLAN_HT_CAP_MIMO_PS_STATIC:
4685 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4686 break;
4687 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
4688 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
4689 break;
4690 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4691 break;
4692 default: 2121 default:
4693 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode); 2122 return len;
4694 break;
4695 } 2123 }
4696
4697 sta_flags |= cpu_to_le32(
4698 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
4699
4700 sta_flags |= cpu_to_le32(
4701 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
4702
4703 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
4704 sta_flags |= STA_FLG_FAT_EN_MSK;
4705 else
4706 sta_flags &= ~STA_FLG_FAT_EN_MSK;
4707
4708 priv->stations[index].sta.station_flags = sta_flags;
4709 done:
4710 return;
4711} 2124}
4712 2125
4713static void iwl4965_sta_modify_add_ba_tid(struct iwl_priv *priv, 2126static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
4714 int sta_id, int tid, u16 ssn)
4715{ 2127{
4716 unsigned long flags; 2128 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
4717 2129 addsta->mode = cmd->mode;
4718 spin_lock_irqsave(&priv->sta_lock, flags); 2130 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
4719 priv->stations[sta_id].sta.station_flags_msk = 0; 2131 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
4720 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK; 2132 addsta->station_flags = cmd->station_flags;
4721 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid; 2133 addsta->station_flags_msk = cmd->station_flags_msk;
4722 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn); 2134 addsta->tid_disable_tx = cmd->tid_disable_tx;
4723 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 2135 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
4724 spin_unlock_irqrestore(&priv->sta_lock, flags); 2136 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2137 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2138 addsta->reserved1 = __constant_cpu_to_le16(0);
2139 addsta->reserved2 = __constant_cpu_to_le32(0);
4725 2140
4726 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC); 2141 return (u16)sizeof(struct iwl4965_addsta_cmd);
4727} 2142}
4728 2143
4729static void iwl4965_sta_modify_del_ba_tid(struct iwl_priv *priv, 2144static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
4730 int sta_id, int tid)
4731{ 2145{
4732 unsigned long flags; 2146 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
4733
4734 spin_lock_irqsave(&priv->sta_lock, flags);
4735 priv->stations[sta_id].sta.station_flags_msk = 0;
4736 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4737 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4738 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4739 spin_unlock_irqrestore(&priv->sta_lock, flags);
4740
4741 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
4742} 2147}
4743 2148
4744/* 2149/**
4745 * Find first available (lowest unused) Tx Queue, mark it "active". 2150 * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
4746 * Called only when finding queue for aggregation.
4747 * Should never return anything < 7, because they should already
4748 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4749 */ 2151 */
4750static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv) 2152static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
4751{ 2153 struct iwl_ht_agg *agg,
4752 int txq_id; 2154 struct iwl4965_tx_resp *tx_resp,
4753 2155 int txq_id, u16 start_idx)
4754 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
4755 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4756 return txq_id;
4757 return -1;
4758}
4759
4760static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
4761 u16 tid, u16 *start_seq_num)
4762{ 2156{
4763 struct iwl_priv *priv = hw->priv; 2157 u16 status;
4764 int sta_id; 2158 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
4765 int tx_fifo; 2159 struct ieee80211_tx_info *info = NULL;
4766 int txq_id; 2160 struct ieee80211_hdr *hdr = NULL;
4767 int ssn = -1; 2161 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
4768 int ret = 0; 2162 int i, sh, idx;
4769 unsigned long flags; 2163 u16 seq;
4770 struct iwl4965_tid_data *tid_data; 2164 if (agg->wait_for_ba)
4771 DECLARE_MAC_BUF(mac); 2165 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
4772 2166
4773 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) 2167 agg->frame_count = tx_resp->frame_count;
4774 tx_fifo = default_tid_to_tx_fifo[tid]; 2168 agg->start_idx = start_idx;
4775 else 2169 agg->rate_n_flags = rate_n_flags;
4776 return -EINVAL; 2170 agg->bitmap = 0;
4777 2171
4778 IWL_WARNING("%s on da = %s tid = %d\n", 2172 /* # frames attempted by Tx command */
4779 __func__, print_mac(mac, da), tid); 2173 if (agg->frame_count == 1) {
4780 2174 /* Only one frame was attempted; no block-ack will arrive */
4781 sta_id = iwl4965_hw_find_station(priv, da); 2175 status = le16_to_cpu(frame_status[0].status);
4782 if (sta_id == IWL_INVALID_STATION) 2176 idx = start_idx;
4783 return -ENXIO; 2177
4784 2178 /* FIXME: code repetition */
4785 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) { 2179 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
4786 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n"); 2180 agg->frame_count, agg->start_idx, idx);
4787 return -ENXIO; 2181
4788 } 2182 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
4789 2183 info->status.retry_count = tx_resp->failure_frame;
4790 txq_id = iwl4965_txq_ctx_activate_free(priv); 2184 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
4791 if (txq_id == -1) 2185 info->flags |= iwl_is_tx_success(status)?
4792 return -ENXIO; 2186 IEEE80211_TX_STAT_ACK : 0;
2187 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
2188 /* FIXME: code repetition end */
2189
2190 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
2191 status & 0xff, tx_resp->failure_frame);
2192 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
2193
2194 agg->wait_for_ba = 0;
2195 } else {
2196 /* Two or more frames were attempted; expect block-ack */
2197 u64 bitmap = 0;
2198 int start = agg->start_idx;
2199
2200 /* Construct bit-map of pending frames within Tx window */
2201 for (i = 0; i < agg->frame_count; i++) {
2202 u16 sc;
2203 status = le16_to_cpu(frame_status[i].status);
2204 seq = le16_to_cpu(frame_status[i].sequence);
2205 idx = SEQ_TO_INDEX(seq);
2206 txq_id = SEQ_TO_QUEUE(seq);
2207
2208 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
2209 AGG_TX_STATE_ABORT_MSK))
2210 continue;
2211
2212 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2213 agg->frame_count, txq_id, idx);
2214
2215 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
2216
2217 sc = le16_to_cpu(hdr->seq_ctrl);
2218 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2219 IWL_ERROR("BUG_ON idx doesn't match seq control"
2220 " idx=%d, seq_idx=%d, seq=%d\n",
2221 idx, SEQ_TO_SN(sc),
2222 hdr->seq_ctrl);
2223 return -1;
2224 }
4793 2225
4794 spin_lock_irqsave(&priv->sta_lock, flags); 2226 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
4795 tid_data = &priv->stations[sta_id].tid[tid]; 2227 i, idx, SEQ_TO_SN(sc));
4796 ssn = SEQ_TO_SN(tid_data->seq_number); 2228
4797 tid_data->agg.txq_id = txq_id; 2229 sh = idx - start;
4798 spin_unlock_irqrestore(&priv->sta_lock, flags); 2230 if (sh > 64) {
2231 sh = (start - idx) + 0xff;
2232 bitmap = bitmap << sh;
2233 sh = 0;
2234 start = idx;
2235 } else if (sh < -64)
2236 sh = 0xff - (start - idx);
2237 else if (sh < 0) {
2238 sh = start - idx;
2239 start = idx;
2240 bitmap = bitmap << sh;
2241 sh = 0;
2242 }
2243 bitmap |= (1 << sh);
2244 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
2245 start, (u32)(bitmap & 0xFFFFFFFF));
2246 }
4799 2247
4800 *start_seq_num = ssn; 2248 agg->bitmap = bitmap;
4801 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo, 2249 agg->start_idx = start;
4802 sta_id, tid, ssn); 2250 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
4803 if (ret) 2251 agg->frame_count, agg->start_idx,
4804 return ret; 2252 (unsigned long long)agg->bitmap);
4805 2253
4806 ret = 0; 2254 if (bitmap)
4807 if (tid_data->tfds_in_queue == 0) { 2255 agg->wait_for_ba = 1;
4808 printk(KERN_ERR "HW queue is empty\n");
4809 tid_data->agg.state = IWL_AGG_ON;
4810 ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
4811 } else {
4812 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4813 tid_data->tfds_in_queue);
4814 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4815 } 2256 }
4816 return ret; 2257 return 0;
4817} 2258}
4818 2259
4819static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da, 2260/**
4820 u16 tid) 2261 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
4821{ 2262 */
4822 2263static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
4823 struct iwl_priv *priv = hw->priv; 2264 struct iwl_rx_mem_buffer *rxb)
4824 int tx_fifo_id, txq_id, sta_id, ssn = -1; 2265{
4825 struct iwl4965_tid_data *tid_data; 2266 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
4826 int ret, write_ptr, read_ptr; 2267 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
4827 unsigned long flags; 2268 int txq_id = SEQ_TO_QUEUE(sequence);
4828 DECLARE_MAC_BUF(mac); 2269 int index = SEQ_TO_INDEX(sequence);
2270 struct iwl_tx_queue *txq = &priv->txq[txq_id];
2271 struct ieee80211_tx_info *info;
2272 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2273 u32 status = le32_to_cpu(tx_resp->u.status);
2274 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
2275 __le16 fc;
2276 struct ieee80211_hdr *hdr;
2277 u8 *qc = NULL;
4829 2278
4830 if (!da) { 2279 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
4831 IWL_ERROR("da = NULL\n"); 2280 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
4832 return -EINVAL; 2281 "is out of range [0-%d] %d %d\n", txq_id,
2282 index, txq->q.n_bd, txq->q.write_ptr,
2283 txq->q.read_ptr);
2284 return;
4833 } 2285 }
4834 2286
4835 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) 2287 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
4836 tx_fifo_id = default_tid_to_tx_fifo[tid]; 2288 memset(&info->status, 0, sizeof(info->status));
4837 else
4838 return -EINVAL;
4839
4840 sta_id = iwl4965_hw_find_station(priv, da);
4841
4842 if (sta_id == IWL_INVALID_STATION)
4843 return -ENXIO;
4844
4845 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4846 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4847 2289
4848 tid_data = &priv->stations[sta_id].tid[tid]; 2290 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
4849 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; 2291 fc = hdr->frame_control;
4850 txq_id = tid_data->agg.txq_id; 2292 if (ieee80211_is_data_qos(fc)) {
4851 write_ptr = priv->txq[txq_id].q.write_ptr; 2293 qc = ieee80211_get_qos_ctl(hdr);
4852 read_ptr = priv->txq[txq_id].q.read_ptr; 2294 tid = qc[0] & 0xf;
2295 }
4853 2296
4854 /* The queue is not empty */ 2297 sta_id = iwl_get_ra_sta_id(priv, hdr);
4855 if (write_ptr != read_ptr) { 2298 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
4856 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n"); 2299 IWL_ERROR("Station not known\n");
4857 priv->stations[sta_id].tid[tid].agg.state = 2300 return;
4858 IWL_EMPTYING_HW_QUEUE_DELBA;
4859 return 0;
4860 } 2301 }
4861 2302
4862 IWL_DEBUG_HT("HW queue empty\n");; 2303 if (txq->sched_retry) {
4863 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; 2304 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2305 struct iwl_ht_agg *agg = NULL;
4864 2306
4865 spin_lock_irqsave(&priv->lock, flags); 2307 if (!qc)
4866 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id); 2308 return;
4867 spin_unlock_irqrestore(&priv->lock, flags);
4868 2309
4869 if (ret) 2310 agg = &priv->stations[sta_id].tid[tid].agg;
4870 return ret;
4871 2311
4872 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid); 2312 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
4873 2313
4874 IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n", 2314 /* check if BAR is needed */
4875 print_mac(mac, da), tid); 2315 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2316 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
4876 2317
4877 return 0; 2318 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
4878} 2319 int freed, ampdu_q;
2320 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2321 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
2322 "%d index %d\n", scd_ssn , index);
2323 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2324 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
4879 2325
4880int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw, 2326 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
4881 enum ieee80211_ampdu_mlme_action action, 2327 txq_id >= 0 && priv->mac80211_registered &&
4882 const u8 *addr, u16 tid, u16 *ssn) 2328 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
4883{ 2329 /* calculate mac80211 ampdu sw queue to wake */
4884 struct iwl_priv *priv = hw->priv; 2330 ampdu_q = txq_id - IWL49_FIRST_AMPDU_QUEUE +
4885 int sta_id; 2331 priv->hw->queues;
4886 DECLARE_MAC_BUF(mac); 2332 if (agg->state == IWL_AGG_OFF)
4887 2333 ieee80211_wake_queue(priv->hw, txq_id);
4888 IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ", 2334 else
4889 print_mac(mac, addr), tid); 2335 ieee80211_wake_queue(priv->hw, ampdu_q);
4890 sta_id = iwl4965_hw_find_station(priv, addr); 2336 }
4891 switch (action) { 2337 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
4892 case IEEE80211_AMPDU_RX_START: 2338 }
4893 IWL_DEBUG_HT("start Rx\n"); 2339 } else {
4894 iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn); 2340 info->status.retry_count = tx_resp->failure_frame;
4895 break; 2341 info->flags |=
4896 case IEEE80211_AMPDU_RX_STOP: 2342 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
4897 IWL_DEBUG_HT("stop Rx\n"); 2343 iwl_hwrate_to_tx_control(priv,
4898 iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid); 2344 le32_to_cpu(tx_resp->rate_n_flags),
4899 break; 2345 info);
4900 case IEEE80211_AMPDU_TX_START: 2346
4901 IWL_DEBUG_HT("start Tx\n"); 2347 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
4902 return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn); 2348 "0x%x retries %d\n", txq_id,
4903 case IEEE80211_AMPDU_TX_STOP: 2349 iwl_get_tx_fail_reason(status),
4904 IWL_DEBUG_HT("stop Tx\n"); 2350 status, le32_to_cpu(tx_resp->rate_n_flags),
4905 return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid); 2351 tx_resp->failure_frame);
4906 default: 2352
4907 IWL_DEBUG_HT("unknown\n"); 2353 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
4908 return -EINVAL; 2354
4909 break; 2355 if (index != -1) {
2356 int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2357 if (tid != MAX_TID_COUNT)
2358 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2359 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
2360 (txq_id >= 0) && priv->mac80211_registered)
2361 ieee80211_wake_queue(priv->hw, txq_id);
2362 if (tid != MAX_TID_COUNT)
2363 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
2364 }
4910 } 2365 }
4911 return 0; 2366
2367 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
2368 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
4912} 2369}
4913 2370
4914#endif /* CONFIG_IWL4965_HT */
4915 2371
4916/* Set up 4965-specific Rx frame reply handlers */ 2372/* Set up 4965-specific Rx frame reply handlers */
4917void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv) 2373static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
4918{ 2374{
4919 /* Legacy Rx frames */ 2375 /* Legacy Rx frames */
4920 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx; 2376 priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
4921 2377 /* Tx response */
4922 /* High-throughput (HT) Rx frames */ 2378 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
4923 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4924 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4925
4926 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4927 iwl4965_rx_missed_beacon_notif;
4928
4929#ifdef CONFIG_IWL4965_HT
4930 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
4931#endif /* CONFIG_IWL4965_HT */
4932} 2379}
4933 2380
4934void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv) 2381static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
4935{ 2382{
4936 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work); 2383 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4937#ifdef CONFIG_IWL4965_SENSITIVITY
4938 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4939#endif
4940 init_timer(&priv->statistics_periodic);
4941 priv->statistics_periodic.data = (unsigned long)priv;
4942 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4943} 2384}
4944 2385
4945void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv) 2386static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
4946{ 2387{
4947 del_timer_sync(&priv->statistics_periodic); 2388 cancel_work_sync(&priv->txpower_work);
4948
4949 cancel_delayed_work(&priv->init_alive_start);
4950} 2389}
4951 2390
4952 2391
@@ -4955,23 +2394,56 @@ static struct iwl_hcmd_ops iwl4965_hcmd = {
4955}; 2394};
4956 2395
4957static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = { 2396static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4958 .enqueue_hcmd = iwl4965_enqueue_hcmd, 2397 .get_hcmd_size = iwl4965_get_hcmd_size,
2398 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
2399 .chain_noise_reset = iwl4965_chain_noise_reset,
2400 .gain_computation = iwl4965_gain_computation,
2401 .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag,
4959}; 2402};
4960 2403
4961static struct iwl_lib_ops iwl4965_lib = { 2404static struct iwl_lib_ops iwl4965_lib = {
4962 .init_drv = iwl4965_init_drv,
4963 .set_hw_params = iwl4965_hw_set_hw_params, 2405 .set_hw_params = iwl4965_hw_set_hw_params,
2406 .alloc_shared_mem = iwl4965_alloc_shared_mem,
2407 .free_shared_mem = iwl4965_free_shared_mem,
2408 .shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
4964 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl, 2409 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
4965 .hw_nic_init = iwl4965_hw_nic_init, 2410 .txq_set_sched = iwl4965_txq_set_sched,
2411 .txq_agg_enable = iwl4965_txq_agg_enable,
2412 .txq_agg_disable = iwl4965_txq_agg_disable,
2413 .rx_handler_setup = iwl4965_rx_handler_setup,
2414 .setup_deferred_work = iwl4965_setup_deferred_work,
2415 .cancel_deferred_work = iwl4965_cancel_deferred_work,
4966 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr, 2416 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4967 .alive_notify = iwl4965_alive_notify, 2417 .alive_notify = iwl4965_alive_notify,
2418 .init_alive_start = iwl4965_init_alive_start,
4968 .load_ucode = iwl4965_load_bsm, 2419 .load_ucode = iwl4965_load_bsm,
2420 .apm_ops = {
2421 .init = iwl4965_apm_init,
2422 .reset = iwl4965_apm_reset,
2423 .stop = iwl4965_apm_stop,
2424 .config = iwl4965_nic_config,
2425 .set_pwr_src = iwl4965_set_pwr_src,
2426 },
4969 .eeprom_ops = { 2427 .eeprom_ops = {
2428 .regulatory_bands = {
2429 EEPROM_REGULATORY_BAND_1_CHANNELS,
2430 EEPROM_REGULATORY_BAND_2_CHANNELS,
2431 EEPROM_REGULATORY_BAND_3_CHANNELS,
2432 EEPROM_REGULATORY_BAND_4_CHANNELS,
2433 EEPROM_REGULATORY_BAND_5_CHANNELS,
2434 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
2435 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
2436 },
4970 .verify_signature = iwlcore_eeprom_verify_signature, 2437 .verify_signature = iwlcore_eeprom_verify_signature,
4971 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 2438 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4972 .release_semaphore = iwlcore_eeprom_release_semaphore, 2439 .release_semaphore = iwlcore_eeprom_release_semaphore,
2440 .check_version = iwl4965_eeprom_check_version,
2441 .query_addr = iwlcore_eeprom_query_addr,
4973 }, 2442 },
4974 .radio_kill_sw = iwl4965_radio_kill_sw, 2443 .set_power = iwl4965_set_power,
2444 .send_tx_power = iwl4965_send_tx_power,
2445 .update_chain_flags = iwl4965_update_chain_flags,
2446 .temperature = iwl4965_temperature_calib,
4975}; 2447};
4976 2448
4977static struct iwl_ops iwl4965_ops = { 2449static struct iwl_ops iwl4965_ops = {
@@ -4984,10 +2456,14 @@ struct iwl_cfg iwl4965_agn_cfg = {
4984 .name = "4965AGN", 2456 .name = "4965AGN",
4985 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode", 2457 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
4986 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 2458 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
2459 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
4987 .ops = &iwl4965_ops, 2460 .ops = &iwl4965_ops,
4988 .mod_params = &iwl4965_mod_params, 2461 .mod_params = &iwl4965_mod_params,
4989}; 2462};
4990 2463
2464/* Module firmware */
2465MODULE_FIRMWARE("iwlwifi-4965" IWL4965_UCODE_API ".ucode");
2466
4991module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444); 2467module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4992MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); 2468MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4993module_param_named(disable, iwl4965_mod_params.disable, int, 0444); 2469module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
@@ -5002,10 +2478,14 @@ MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
5002 2478
5003module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444); 2479module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
5004MODULE_PARM_DESC(queues_num, "number of hw queues."); 2480MODULE_PARM_DESC(queues_num, "number of hw queues.");
5005
5006/* QoS */ 2481/* QoS */
5007module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444); 2482module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
5008MODULE_PARM_DESC(qos_enable, "enable all QoS functionality"); 2483MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
2484/* 11n */
2485module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, 0444);
2486MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
5009module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444); 2487module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
5010MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); 2488MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
5011 2489
2490module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
2491MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000-hw.h b/drivers/net/wireless/iwlwifi/iwl-5000-hw.h
new file mode 100644
index 000000000000..17d4f31c5934
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-5000-hw.h
@@ -0,0 +1,134 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2008 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63/*
64 * Please use this file (iwl-5000-hw.h) only for hardware-related definitions.
65 * Use iwl-5000-commands.h for uCode API definitions.
66 */
67
68#ifndef __iwl_5000_hw_h__
69#define __iwl_5000_hw_h__
70
71#define IWL50_RTC_INST_UPPER_BOUND (0x020000)
72#define IWL50_RTC_DATA_UPPER_BOUND (0x80C000)
73#define IWL50_RTC_INST_SIZE (IWL50_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
74#define IWL50_RTC_DATA_SIZE (IWL50_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
75
76/* EERPROM */
77#define IWL_5000_EEPROM_IMG_SIZE 2048
78
79
80#define IWL50_MAX_WIN_SIZE 64
81#define IWL50_QUEUE_SIZE 256
82#define IWL50_CMD_FIFO_NUM 7
83#define IWL50_NUM_QUEUES 20
84#define IWL50_NUM_AMPDU_QUEUES 10
85#define IWL50_FIRST_AMPDU_QUEUE 10
86
87#define IWL_sta_id_POS 12
88#define IWL_sta_id_LEN 4
89#define IWL_sta_id_SYM val
90
91/* Fixed (non-configurable) rx data from phy */
92
93/* Base physical address of iwl5000_shared is provided to SCD_DRAM_BASE_ADDR
94 * and &iwl5000_shared.val0 is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG */
95struct iwl5000_sched_queue_byte_cnt_tbl {
96 struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL50_QUEUE_SIZE +
97 IWL50_MAX_WIN_SIZE];
98} __attribute__ ((packed));
99
100struct iwl5000_shared {
101 struct iwl5000_sched_queue_byte_cnt_tbl
102 queues_byte_cnt_tbls[IWL50_NUM_QUEUES];
103 __le32 rb_closed;
104
105 /* __le32 rb_closed_stts_rb_num:12; */
106#define IWL_rb_closed_stts_rb_num_POS 0
107#define IWL_rb_closed_stts_rb_num_LEN 12
108#define IWL_rb_closed_stts_rb_num_SYM rb_closed
109 /* __le32 rsrv1:4; */
110 /* __le32 rb_closed_stts_rx_frame_num:12; */
111#define IWL_rb_closed_stts_rx_frame_num_POS 16
112#define IWL_rb_closed_stts_rx_frame_num_LEN 12
113#define IWL_rb_closed_stts_rx_frame_num_SYM rb_closed
114 /* __le32 rsrv2:4; */
115
116 __le32 frm_finished;
117 /* __le32 frame_finished_stts_rb_num:12; */
118#define IWL_frame_finished_stts_rb_num_POS 0
119#define IWL_frame_finished_stts_rb_num_LEN 12
120#define IWL_frame_finished_stts_rb_num_SYM frm_finished
121 /* __le32 rsrv3:4; */
122 /* __le32 frame_finished_stts_rx_frame_num:12; */
123#define IWL_frame_finished_stts_rx_frame_num_POS 16
124#define IWL_frame_finished_stts_rx_frame_num_LEN 12
125#define IWL_frame_finished_stts_rx_frame_num_SYM frm_finished
126 /* __le32 rsrv4:4; */
127
128 __le32 padding1; /* so that allocation will be aligned to 16B */
129 __le32 padding2;
130} __attribute__ ((packed));
131
132
133#endif /* __iwl_5000_hw_h__ */
134
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
new file mode 100644
index 000000000000..878d6193b232
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -0,0 +1,1580 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/version.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
37#include <linux/etherdevice.h>
38#include <asm/unaligned.h>
39
40#include "iwl-eeprom.h"
41#include "iwl-dev.h"
42#include "iwl-core.h"
43#include "iwl-io.h"
44#include "iwl-sta.h"
45#include "iwl-helpers.h"
46#include "iwl-5000-hw.h"
47
48#define IWL5000_UCODE_API "-1"
49
50static const u16 iwl5000_default_queue_to_tx_fifo[] = {
51 IWL_TX_FIFO_AC3,
52 IWL_TX_FIFO_AC2,
53 IWL_TX_FIFO_AC1,
54 IWL_TX_FIFO_AC0,
55 IWL50_CMD_FIFO_NUM,
56 IWL_TX_FIFO_HCCA_1,
57 IWL_TX_FIFO_HCCA_2
58};
59
60/* FIXME: same implementation as 4965 */
61static int iwl5000_apm_stop_master(struct iwl_priv *priv)
62{
63 int ret = 0;
64 unsigned long flags;
65
66 spin_lock_irqsave(&priv->lock, flags);
67
68 /* set stop master bit */
69 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
70
71 ret = iwl_poll_bit(priv, CSR_RESET,
72 CSR_RESET_REG_FLAG_MASTER_DISABLED,
73 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
74 if (ret < 0)
75 goto out;
76
77out:
78 spin_unlock_irqrestore(&priv->lock, flags);
79 IWL_DEBUG_INFO("stop master\n");
80
81 return ret;
82}
83
84
85static int iwl5000_apm_init(struct iwl_priv *priv)
86{
87 int ret = 0;
88
89 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
90 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
91
92 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
93 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
94 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
95
96 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
97
98 /* set "initialization complete" bit to move adapter
99 * D0U* --> D0A* state */
100 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
101
102 /* wait for clock stabilization */
103 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
104 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
105 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
106 if (ret < 0) {
107 IWL_DEBUG_INFO("Failed to init the card\n");
108 return ret;
109 }
110
111 ret = iwl_grab_nic_access(priv);
112 if (ret)
113 return ret;
114
115 /* enable DMA */
116 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
117
118 udelay(20);
119
120 /* disable L1-Active */
121 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
122 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
123
124 iwl_release_nic_access(priv);
125
126 return ret;
127}
128
129/* FIXME: this is indentical to 4965 */
130static void iwl5000_apm_stop(struct iwl_priv *priv)
131{
132 unsigned long flags;
133
134 iwl5000_apm_stop_master(priv);
135
136 spin_lock_irqsave(&priv->lock, flags);
137
138 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
139
140 udelay(10);
141
142 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
143
144 spin_unlock_irqrestore(&priv->lock, flags);
145}
146
147
148static int iwl5000_apm_reset(struct iwl_priv *priv)
149{
150 int ret = 0;
151 unsigned long flags;
152
153 iwl5000_apm_stop_master(priv);
154
155 spin_lock_irqsave(&priv->lock, flags);
156
157 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
158
159 udelay(10);
160
161
162 /* FIXME: put here L1A -L0S w/a */
163
164 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
165
166 /* set "initialization complete" bit to move adapter
167 * D0U* --> D0A* state */
168 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
169
170 /* wait for clock stabilization */
171 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
172 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
173 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
174 if (ret < 0) {
175 IWL_DEBUG_INFO("Failed to init the card\n");
176 goto out;
177 }
178
179 ret = iwl_grab_nic_access(priv);
180 if (ret)
181 goto out;
182
183 /* enable DMA */
184 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
185
186 udelay(20);
187
188 /* disable L1-Active */
189 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
190 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
191
192 iwl_release_nic_access(priv);
193
194out:
195 spin_unlock_irqrestore(&priv->lock, flags);
196
197 return ret;
198}
199
200
201static void iwl5000_nic_config(struct iwl_priv *priv)
202{
203 unsigned long flags;
204 u16 radio_cfg;
205 u8 val_link;
206
207 spin_lock_irqsave(&priv->lock, flags);
208
209 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
210
211 /* L1 is enabled by BIOS */
212 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
213 /* diable L0S disabled L1A enabled */
214 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
215 else
216 /* L0S enabled L1A disabled */
217 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
218
219 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
220
221 /* write radio config values to register */
222 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
223 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
224 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
225 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
226 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
227
228 /* set CSR_HW_CONFIG_REG for uCode use */
229 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
230 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
231 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
232
233 spin_unlock_irqrestore(&priv->lock, flags);
234}
235
236
237
238/*
239 * EEPROM
240 */
241static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
242{
243 u16 offset = 0;
244
245 if ((address & INDIRECT_ADDRESS) == 0)
246 return address;
247
248 switch (address & INDIRECT_TYPE_MSK) {
249 case INDIRECT_HOST:
250 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
251 break;
252 case INDIRECT_GENERAL:
253 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
254 break;
255 case INDIRECT_REGULATORY:
256 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
257 break;
258 case INDIRECT_CALIBRATION:
259 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
260 break;
261 case INDIRECT_PROCESS_ADJST:
262 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
263 break;
264 case INDIRECT_OTHERS:
265 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
266 break;
267 default:
268 IWL_ERROR("illegal indirect type: 0x%X\n",
269 address & INDIRECT_TYPE_MSK);
270 break;
271 }
272
273 /* translate the offset from words to byte */
274 return (address & ADDRESS_MSK) + (offset << 1);
275}
276
277static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
278{
279 u16 eeprom_ver;
280 struct iwl_eeprom_calib_hdr {
281 u8 version;
282 u8 pa_type;
283 u16 voltage;
284 } *hdr;
285
286 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
287
288 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
289 EEPROM_5000_CALIB_ALL);
290
291 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
292 hdr->version < EEPROM_5000_TX_POWER_VERSION)
293 goto err;
294
295 return 0;
296err:
297 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
298 eeprom_ver, EEPROM_5000_EEPROM_VERSION,
299 hdr->version, EEPROM_5000_TX_POWER_VERSION);
300 return -EINVAL;
301
302}
303
304static void iwl5000_gain_computation(struct iwl_priv *priv,
305 u32 average_noise[NUM_RX_CHAINS],
306 u16 min_average_noise_antenna_i,
307 u32 min_average_noise)
308{
309 int i;
310 s32 delta_g;
311 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
312
313 /* Find Gain Code for the antennas B and C */
314 for (i = 1; i < NUM_RX_CHAINS; i++) {
315 if ((data->disconn_array[i])) {
316 data->delta_gain_code[i] = 0;
317 continue;
318 }
319 delta_g = (1000 * ((s32)average_noise[0] -
320 (s32)average_noise[i])) / 1500;
321 /* bound gain by 2 bits value max, 3rd bit is sign */
322 data->delta_gain_code[i] =
323 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
324
325 if (delta_g < 0)
326 /* set negative sign */
327 data->delta_gain_code[i] |= (1 << 2);
328 }
329
330 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
331 data->delta_gain_code[1], data->delta_gain_code[2]);
332
333 if (!data->radio_write) {
334 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
335 memset(&cmd, 0, sizeof(cmd));
336
337 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
338 cmd.delta_gain_1 = data->delta_gain_code[1];
339 cmd.delta_gain_2 = data->delta_gain_code[2];
340 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
341 sizeof(cmd), &cmd, NULL);
342
343 data->radio_write = 1;
344 data->state = IWL_CHAIN_NOISE_CALIBRATED;
345 }
346
347 data->chain_noise_a = 0;
348 data->chain_noise_b = 0;
349 data->chain_noise_c = 0;
350 data->chain_signal_a = 0;
351 data->chain_signal_b = 0;
352 data->chain_signal_c = 0;
353 data->beacon_count = 0;
354}
355
356static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
357{
358 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
359
360 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
361 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
362
363 memset(&cmd, 0, sizeof(cmd));
364 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
365 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
366 sizeof(cmd), &cmd))
367 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
368 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
369 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
370 }
371}
372
373static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
374 __le32 *tx_flags)
375{
376 if ((info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) ||
377 (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT))
378 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
379 else
380 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
381}
382
383static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
384 .min_nrg_cck = 95,
385 .max_nrg_cck = 0,
386 .auto_corr_min_ofdm = 90,
387 .auto_corr_min_ofdm_mrc = 170,
388 .auto_corr_min_ofdm_x1 = 120,
389 .auto_corr_min_ofdm_mrc_x1 = 240,
390
391 .auto_corr_max_ofdm = 120,
392 .auto_corr_max_ofdm_mrc = 210,
393 .auto_corr_max_ofdm_x1 = 155,
394 .auto_corr_max_ofdm_mrc_x1 = 290,
395
396 .auto_corr_min_cck = 125,
397 .auto_corr_max_cck = 200,
398 .auto_corr_min_cck_mrc = 170,
399 .auto_corr_max_cck_mrc = 400,
400 .nrg_th_cck = 95,
401 .nrg_th_ofdm = 95,
402};
403
404static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
405 size_t offset)
406{
407 u32 address = eeprom_indirect_address(priv, offset);
408 BUG_ON(address >= priv->cfg->eeprom_size);
409 return &priv->eeprom[address];
410}
411
412/*
413 * Calibration
414 */
415static int iwl5000_send_Xtal_calib(struct iwl_priv *priv)
416{
417 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
418
419 struct iwl5000_calibration cal_cmd = {
420 .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD,
421 .data = {
422 (u8)xtal_calib[0],
423 (u8)xtal_calib[1],
424 }
425 };
426
427 return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
428 sizeof(cal_cmd), &cal_cmd);
429}
430
431static int iwl5000_send_calib_results(struct iwl_priv *priv)
432{
433 int ret = 0;
434
435 struct iwl_host_cmd hcmd = {
436 .id = REPLY_PHY_CALIBRATION_CMD,
437 .meta.flags = CMD_SIZE_HUGE,
438 };
439
440 if (priv->calib_results.lo_res) {
441 hcmd.len = priv->calib_results.lo_res_len;
442 hcmd.data = priv->calib_results.lo_res;
443 ret = iwl_send_cmd_sync(priv, &hcmd);
444
445 if (ret)
446 goto err;
447 }
448
449 if (priv->calib_results.tx_iq_res) {
450 hcmd.len = priv->calib_results.tx_iq_res_len;
451 hcmd.data = priv->calib_results.tx_iq_res;
452 ret = iwl_send_cmd_sync(priv, &hcmd);
453
454 if (ret)
455 goto err;
456 }
457
458 if (priv->calib_results.tx_iq_perd_res) {
459 hcmd.len = priv->calib_results.tx_iq_perd_res_len;
460 hcmd.data = priv->calib_results.tx_iq_perd_res;
461 ret = iwl_send_cmd_sync(priv, &hcmd);
462
463 if (ret)
464 goto err;
465 }
466
467 return 0;
468err:
469 IWL_ERROR("Error %d\n", ret);
470 return ret;
471}
472
473static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
474{
475 struct iwl5000_calib_cfg_cmd calib_cfg_cmd;
476 struct iwl_host_cmd cmd = {
477 .id = CALIBRATION_CFG_CMD,
478 .len = sizeof(struct iwl5000_calib_cfg_cmd),
479 .data = &calib_cfg_cmd,
480 };
481
482 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
483 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
484 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
485 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
486 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
487
488 return iwl_send_cmd(priv, &cmd);
489}
490
491static void iwl5000_rx_calib_result(struct iwl_priv *priv,
492 struct iwl_rx_mem_buffer *rxb)
493{
494 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
495 struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw;
496 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
497
498 iwl_free_calib_results(priv);
499
500 /* reduce the size of the length field itself */
501 len -= 4;
502
503 switch (hdr->op_code) {
504 case IWL5000_PHY_CALIBRATE_LO_CMD:
505 priv->calib_results.lo_res = kzalloc(len, GFP_ATOMIC);
506 priv->calib_results.lo_res_len = len;
507 memcpy(priv->calib_results.lo_res, pkt->u.raw, len);
508 break;
509 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD:
510 priv->calib_results.tx_iq_res = kzalloc(len, GFP_ATOMIC);
511 priv->calib_results.tx_iq_res_len = len;
512 memcpy(priv->calib_results.tx_iq_res, pkt->u.raw, len);
513 break;
514 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD:
515 priv->calib_results.tx_iq_perd_res = kzalloc(len, GFP_ATOMIC);
516 priv->calib_results.tx_iq_perd_res_len = len;
517 memcpy(priv->calib_results.tx_iq_perd_res, pkt->u.raw, len);
518 break;
519 default:
520 IWL_ERROR("Unknown calibration notification %d\n",
521 hdr->op_code);
522 return;
523 }
524}
525
526static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
527 struct iwl_rx_mem_buffer *rxb)
528{
529 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
530 queue_work(priv->workqueue, &priv->restart);
531}
532
533/*
534 * ucode
535 */
536static int iwl5000_load_section(struct iwl_priv *priv,
537 struct fw_desc *image,
538 u32 dst_addr)
539{
540 int ret = 0;
541 unsigned long flags;
542
543 dma_addr_t phy_addr = image->p_addr;
544 u32 byte_cnt = image->len;
545
546 spin_lock_irqsave(&priv->lock, flags);
547 ret = iwl_grab_nic_access(priv);
548 if (ret) {
549 spin_unlock_irqrestore(&priv->lock, flags);
550 return ret;
551 }
552
553 iwl_write_direct32(priv,
554 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
555 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
556
557 iwl_write_direct32(priv,
558 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
559
560 iwl_write_direct32(priv,
561 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
562 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
563
564 /* FIME: write the MSB of the phy_addr in CTRL1
565 * iwl_write_direct32(priv,
566 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
567 ((phy_addr & MSB_MSK)
568 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
569 */
570 iwl_write_direct32(priv,
571 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
572 iwl_write_direct32(priv,
573 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
574 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
575 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
576 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
577
578 iwl_write_direct32(priv,
579 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
580 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
581 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
582 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
583
584 iwl_release_nic_access(priv);
585 spin_unlock_irqrestore(&priv->lock, flags);
586 return 0;
587}
588
589static int iwl5000_load_given_ucode(struct iwl_priv *priv,
590 struct fw_desc *inst_image,
591 struct fw_desc *data_image)
592{
593 int ret = 0;
594
595 ret = iwl5000_load_section(
596 priv, inst_image, RTC_INST_LOWER_BOUND);
597 if (ret)
598 return ret;
599
600 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
601 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
602 priv->ucode_write_complete, 5 * HZ);
603 if (ret == -ERESTARTSYS) {
604 IWL_ERROR("Could not load the INST uCode section due "
605 "to interrupt\n");
606 return ret;
607 }
608 if (!ret) {
609 IWL_ERROR("Could not load the INST uCode section\n");
610 return -ETIMEDOUT;
611 }
612
613 priv->ucode_write_complete = 0;
614
615 ret = iwl5000_load_section(
616 priv, data_image, RTC_DATA_LOWER_BOUND);
617 if (ret)
618 return ret;
619
620 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
621
622 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
623 priv->ucode_write_complete, 5 * HZ);
624 if (ret == -ERESTARTSYS) {
625 IWL_ERROR("Could not load the INST uCode section due "
626 "to interrupt\n");
627 return ret;
628 } else if (!ret) {
629 IWL_ERROR("Could not load the DATA uCode section\n");
630 return -ETIMEDOUT;
631 } else
632 ret = 0;
633
634 priv->ucode_write_complete = 0;
635
636 return ret;
637}
638
639static int iwl5000_load_ucode(struct iwl_priv *priv)
640{
641 int ret = 0;
642
643 /* check whether init ucode should be loaded, or rather runtime ucode */
644 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
645 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
646 ret = iwl5000_load_given_ucode(priv,
647 &priv->ucode_init, &priv->ucode_init_data);
648 if (!ret) {
649 IWL_DEBUG_INFO("Init ucode load complete.\n");
650 priv->ucode_type = UCODE_INIT;
651 }
652 } else {
653 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
654 "Loading runtime ucode...\n");
655 ret = iwl5000_load_given_ucode(priv,
656 &priv->ucode_code, &priv->ucode_data);
657 if (!ret) {
658 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
659 priv->ucode_type = UCODE_RT;
660 }
661 }
662
663 return ret;
664}
665
666static void iwl5000_init_alive_start(struct iwl_priv *priv)
667{
668 int ret = 0;
669
670 /* Check alive response for "valid" sign from uCode */
671 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
672 /* We had an error bringing up the hardware, so take it
673 * all the way back down so we can try again */
674 IWL_DEBUG_INFO("Initialize Alive failed.\n");
675 goto restart;
676 }
677
678 /* initialize uCode was loaded... verify inst image.
679 * This is a paranoid check, because we would not have gotten the
680 * "initialize" alive if code weren't properly loaded. */
681 if (iwl_verify_ucode(priv)) {
682 /* Runtime instruction load was bad;
683 * take it all the way back down so we can try again */
684 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
685 goto restart;
686 }
687
688 iwl_clear_stations_table(priv);
689 ret = priv->cfg->ops->lib->alive_notify(priv);
690 if (ret) {
691 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
692 goto restart;
693 }
694
695 iwl5000_send_calib_cfg(priv);
696 return;
697
698restart:
699 /* real restart (first load init_ucode) */
700 queue_work(priv->workqueue, &priv->restart);
701}
702
703static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
704 int txq_id, u32 index)
705{
706 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
707 (index & 0xff) | (txq_id << 8));
708 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
709}
710
711static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
712 struct iwl_tx_queue *txq,
713 int tx_fifo_id, int scd_retry)
714{
715 int txq_id = txq->q.id;
716 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
717
718 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
719 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
720 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
721 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
722 IWL50_SCD_QUEUE_STTS_REG_MSK);
723
724 txq->sched_retry = scd_retry;
725
726 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
727 active ? "Activate" : "Deactivate",
728 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
729}
730
731static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
732{
733 struct iwl_wimax_coex_cmd coex_cmd;
734
735 memset(&coex_cmd, 0, sizeof(coex_cmd));
736
737 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
738 sizeof(coex_cmd), &coex_cmd);
739}
740
741static int iwl5000_alive_notify(struct iwl_priv *priv)
742{
743 u32 a;
744 int i = 0;
745 unsigned long flags;
746 int ret;
747
748 spin_lock_irqsave(&priv->lock, flags);
749
750 ret = iwl_grab_nic_access(priv);
751 if (ret) {
752 spin_unlock_irqrestore(&priv->lock, flags);
753 return ret;
754 }
755
756 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
757 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
758 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
759 a += 4)
760 iwl_write_targ_mem(priv, a, 0);
761 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
762 a += 4)
763 iwl_write_targ_mem(priv, a, 0);
764 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
765 iwl_write_targ_mem(priv, a, 0);
766
767 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
768 (priv->shared_phys +
769 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
770 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
771 IWL50_SCD_QUEUECHAIN_SEL_ALL(
772 priv->hw_params.max_txq_num));
773 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
774
775 /* initiate the queues */
776 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
777 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
778 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
779 iwl_write_targ_mem(priv, priv->scd_base_addr +
780 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
781 iwl_write_targ_mem(priv, priv->scd_base_addr +
782 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
783 sizeof(u32),
784 ((SCD_WIN_SIZE <<
785 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
786 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
787 ((SCD_FRAME_LIMIT <<
788 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
789 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
790 }
791
792 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
793 IWL_MASK(0, priv->hw_params.max_txq_num));
794
795 /* Activate all Tx DMA/FIFO channels */
796 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
797
798 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
799 /* map qos queues to fifos one-to-one */
800 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
801 int ac = iwl5000_default_queue_to_tx_fifo[i];
802 iwl_txq_ctx_activate(priv, i);
803 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
804 }
805 /* TODO - need to initialize those FIFOs inside the loop above,
806 * not only mark them as active */
807 iwl_txq_ctx_activate(priv, 4);
808 iwl_txq_ctx_activate(priv, 7);
809 iwl_txq_ctx_activate(priv, 8);
810 iwl_txq_ctx_activate(priv, 9);
811
812 iwl_release_nic_access(priv);
813 spin_unlock_irqrestore(&priv->lock, flags);
814
815
816 iwl5000_send_wimax_coex(priv);
817
818 iwl5000_send_Xtal_calib(priv);
819
820 if (priv->ucode_type == UCODE_RT)
821 iwl5000_send_calib_results(priv);
822
823 return 0;
824}
825
826static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
827{
828 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
829 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
830 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
831 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
832 return -EINVAL;
833 }
834
835 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
836 priv->hw_params.first_ampdu_q = IWL50_FIRST_AMPDU_QUEUE;
837 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
838 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
839 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
840 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
841 priv->hw_params.max_bsm_size = 0;
842 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
843 BIT(IEEE80211_BAND_5GHZ);
844 priv->hw_params.sens = &iwl5000_sensitivity;
845
846 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
847 case CSR_HW_REV_TYPE_5100:
848 case CSR_HW_REV_TYPE_5150:
849 priv->hw_params.tx_chains_num = 1;
850 priv->hw_params.rx_chains_num = 2;
851 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
852 priv->hw_params.valid_tx_ant = ANT_A;
853 priv->hw_params.valid_rx_ant = ANT_AB;
854 break;
855 case CSR_HW_REV_TYPE_5300:
856 case CSR_HW_REV_TYPE_5350:
857 priv->hw_params.tx_chains_num = 3;
858 priv->hw_params.rx_chains_num = 3;
859 priv->hw_params.valid_tx_ant = ANT_ABC;
860 priv->hw_params.valid_rx_ant = ANT_ABC;
861 break;
862 }
863
864 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
865 case CSR_HW_REV_TYPE_5100:
866 case CSR_HW_REV_TYPE_5300:
867 /* 5X00 wants in Celsius */
868 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
869 break;
870 case CSR_HW_REV_TYPE_5150:
871 case CSR_HW_REV_TYPE_5350:
872 /* 5X50 wants in Kelvin */
873 priv->hw_params.ct_kill_threshold =
874 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
875 break;
876 }
877
878 return 0;
879}
880
881static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
882{
883 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
884 sizeof(struct iwl5000_shared),
885 &priv->shared_phys);
886 if (!priv->shared_virt)
887 return -ENOMEM;
888
889 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
890
891 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
892
893 return 0;
894}
895
896static void iwl5000_free_shared_mem(struct iwl_priv *priv)
897{
898 if (priv->shared_virt)
899 pci_free_consistent(priv->pci_dev,
900 sizeof(struct iwl5000_shared),
901 priv->shared_virt,
902 priv->shared_phys);
903}
904
905static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
906{
907 struct iwl5000_shared *s = priv->shared_virt;
908 return le32_to_cpu(s->rb_closed) & 0xFFF;
909}
910
911/**
912 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
913 */
914static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
915 struct iwl_tx_queue *txq,
916 u16 byte_cnt)
917{
918 struct iwl5000_shared *shared_data = priv->shared_virt;
919 int txq_id = txq->q.id;
920 u8 sec_ctl = 0;
921 u8 sta = 0;
922 int len;
923
924 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
925
926 if (txq_id != IWL_CMD_QUEUE_NUM) {
927 sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id;
928 sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl;
929
930 switch (sec_ctl & TX_CMD_SEC_MSK) {
931 case TX_CMD_SEC_CCM:
932 len += CCMP_MIC_LEN;
933 break;
934 case TX_CMD_SEC_TKIP:
935 len += TKIP_ICV_LEN;
936 break;
937 case TX_CMD_SEC_WEP:
938 len += WEP_IV_LEN + WEP_ICV_LEN;
939 break;
940 }
941 }
942
943 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
944 tfd_offset[txq->q.write_ptr], byte_cnt, len);
945
946 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
947 tfd_offset[txq->q.write_ptr], sta_id, sta);
948
949 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
950 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
951 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
952 byte_cnt, len);
953 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
954 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
955 sta_id, sta);
956 }
957}
958
959static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
960 struct iwl_tx_queue *txq)
961{
962 int txq_id = txq->q.id;
963 struct iwl5000_shared *shared_data = priv->shared_virt;
964 u8 sta = 0;
965
966 if (txq_id != IWL_CMD_QUEUE_NUM)
967 sta = txq->cmd[txq->q.read_ptr].cmd.tx.sta_id;
968
969 shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr].
970 val = cpu_to_le16(1 | (sta << 12));
971
972 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
973 shared_data->queues_byte_cnt_tbls[txq_id].
974 tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr].
975 val = cpu_to_le16(1 | (sta << 12));
976 }
977}
978
979static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
980 u16 txq_id)
981{
982 u32 tbl_dw_addr;
983 u32 tbl_dw;
984 u16 scd_q2ratid;
985
986 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
987
988 tbl_dw_addr = priv->scd_base_addr +
989 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
990
991 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
992
993 if (txq_id & 0x1)
994 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
995 else
996 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
997
998 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
999
1000 return 0;
1001}
1002static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
1003{
1004 /* Simply stop the queue, but don't change any configuration;
1005 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1006 iwl_write_prph(priv,
1007 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
1008 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1009 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1010}
1011
1012static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1013 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1014{
1015 unsigned long flags;
1016 int ret;
1017 u16 ra_tid;
1018
1019 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1020 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1021 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1022 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1023 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1024 return -EINVAL;
1025 }
1026
1027 ra_tid = BUILD_RAxTID(sta_id, tid);
1028
1029 /* Modify device's station table to Tx this TID */
1030 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
1031
1032 spin_lock_irqsave(&priv->lock, flags);
1033 ret = iwl_grab_nic_access(priv);
1034 if (ret) {
1035 spin_unlock_irqrestore(&priv->lock, flags);
1036 return ret;
1037 }
1038
1039 /* Stop this Tx queue before configuring it */
1040 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1041
1042 /* Map receiver-address / traffic-ID to this queue */
1043 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1044
1045 /* Set this queue as a chain-building queue */
1046 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1047
1048 /* enable aggregations for the queue */
1049 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1050
1051 /* Place first TFD at index corresponding to start sequence number.
1052 * Assumes that ssn_idx is valid (!= 0xFFF) */
1053 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1054 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1055 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1056
1057 /* Set up Tx window size and frame limit for this queue */
1058 iwl_write_targ_mem(priv, priv->scd_base_addr +
1059 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1060 sizeof(u32),
1061 ((SCD_WIN_SIZE <<
1062 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1063 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1064 ((SCD_FRAME_LIMIT <<
1065 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1066 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1067
1068 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1069
1070 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1071 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1072
1073 iwl_release_nic_access(priv);
1074 spin_unlock_irqrestore(&priv->lock, flags);
1075
1076 return 0;
1077}
1078
1079static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1080 u16 ssn_idx, u8 tx_fifo)
1081{
1082 int ret;
1083
1084 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1085 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1086 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1087 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1088 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1089 return -EINVAL;
1090 }
1091
1092 ret = iwl_grab_nic_access(priv);
1093 if (ret)
1094 return ret;
1095
1096 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1097
1098 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1099
1100 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1101 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1102 /* supposes that ssn_idx is valid (!= 0xFFF) */
1103 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1104
1105 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1106 iwl_txq_ctx_deactivate(priv, txq_id);
1107 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1108
1109 iwl_release_nic_access(priv);
1110
1111 return 0;
1112}
1113
1114static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1115{
1116 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1117 memcpy(data, cmd, size);
1118 return size;
1119}
1120
1121
1122/*
1123 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
1124 * must be called under priv->lock and mac access
1125 */
1126static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1127{
1128 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1129}
1130
1131
1132static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1133{
1134 return le32_to_cpup((__le32*)&tx_resp->status +
1135 tx_resp->frame_count) & MAX_SN;
1136}
1137
1138static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1139 struct iwl_ht_agg *agg,
1140 struct iwl5000_tx_resp *tx_resp,
1141 int txq_id, u16 start_idx)
1142{
1143 u16 status;
1144 struct agg_tx_status *frame_status = &tx_resp->status;
1145 struct ieee80211_tx_info *info = NULL;
1146 struct ieee80211_hdr *hdr = NULL;
1147 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1148 int i, sh, idx;
1149 u16 seq;
1150
1151 if (agg->wait_for_ba)
1152 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1153
1154 agg->frame_count = tx_resp->frame_count;
1155 agg->start_idx = start_idx;
1156 agg->rate_n_flags = rate_n_flags;
1157 agg->bitmap = 0;
1158
1159 /* # frames attempted by Tx command */
1160 if (agg->frame_count == 1) {
1161 /* Only one frame was attempted; no block-ack will arrive */
1162 status = le16_to_cpu(frame_status[0].status);
1163 idx = start_idx;
1164
1165 /* FIXME: code repetition */
1166 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1167 agg->frame_count, agg->start_idx, idx);
1168
1169 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1170 info->status.retry_count = tx_resp->failure_frame;
1171 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1172 info->flags |= iwl_is_tx_success(status)?
1173 IEEE80211_TX_STAT_ACK : 0;
1174 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1175
1176 /* FIXME: code repetition end */
1177
1178 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1179 status & 0xff, tx_resp->failure_frame);
1180 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
1181
1182 agg->wait_for_ba = 0;
1183 } else {
1184 /* Two or more frames were attempted; expect block-ack */
1185 u64 bitmap = 0;
1186 int start = agg->start_idx;
1187
1188 /* Construct bit-map of pending frames within Tx window */
1189 for (i = 0; i < agg->frame_count; i++) {
1190 u16 sc;
1191 status = le16_to_cpu(frame_status[i].status);
1192 seq = le16_to_cpu(frame_status[i].sequence);
1193 idx = SEQ_TO_INDEX(seq);
1194 txq_id = SEQ_TO_QUEUE(seq);
1195
1196 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1197 AGG_TX_STATE_ABORT_MSK))
1198 continue;
1199
1200 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1201 agg->frame_count, txq_id, idx);
1202
1203 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1204
1205 sc = le16_to_cpu(hdr->seq_ctrl);
1206 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1207 IWL_ERROR("BUG_ON idx doesn't match seq control"
1208 " idx=%d, seq_idx=%d, seq=%d\n",
1209 idx, SEQ_TO_SN(sc),
1210 hdr->seq_ctrl);
1211 return -1;
1212 }
1213
1214 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1215 i, idx, SEQ_TO_SN(sc));
1216
1217 sh = idx - start;
1218 if (sh > 64) {
1219 sh = (start - idx) + 0xff;
1220 bitmap = bitmap << sh;
1221 sh = 0;
1222 start = idx;
1223 } else if (sh < -64)
1224 sh = 0xff - (start - idx);
1225 else if (sh < 0) {
1226 sh = start - idx;
1227 start = idx;
1228 bitmap = bitmap << sh;
1229 sh = 0;
1230 }
1231 bitmap |= (1 << sh);
1232 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
1233 start, (u32)(bitmap & 0xFFFFFFFF));
1234 }
1235
1236 agg->bitmap = bitmap;
1237 agg->start_idx = start;
1238 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1239 agg->frame_count, agg->start_idx,
1240 (unsigned long long)agg->bitmap);
1241
1242 if (bitmap)
1243 agg->wait_for_ba = 1;
1244 }
1245 return 0;
1246}
1247
1248static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1249 struct iwl_rx_mem_buffer *rxb)
1250{
1251 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1252 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1253 int txq_id = SEQ_TO_QUEUE(sequence);
1254 int index = SEQ_TO_INDEX(sequence);
1255 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1256 struct ieee80211_tx_info *info;
1257 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1258 u32 status = le16_to_cpu(tx_resp->status.status);
1259 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
1260 struct ieee80211_hdr *hdr;
1261 u8 *qc = NULL;
1262
1263 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1264 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1265 "is out of range [0-%d] %d %d\n", txq_id,
1266 index, txq->q.n_bd, txq->q.write_ptr,
1267 txq->q.read_ptr);
1268 return;
1269 }
1270
1271 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1272 memset(&info->status, 0, sizeof(info->status));
1273
1274 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
1275 if (ieee80211_is_data_qos(hdr->frame_control)) {
1276 qc = ieee80211_get_qos_ctl(hdr);
1277 tid = qc[0] & 0xf;
1278 }
1279
1280 sta_id = iwl_get_ra_sta_id(priv, hdr);
1281 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
1282 IWL_ERROR("Station not known\n");
1283 return;
1284 }
1285
1286 if (txq->sched_retry) {
1287 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1288 struct iwl_ht_agg *agg = NULL;
1289
1290 if (!qc)
1291 return;
1292
1293 agg = &priv->stations[sta_id].tid[tid].agg;
1294
1295 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1296
1297 /* check if BAR is needed */
1298 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1299 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1300
1301 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1302 int freed, ampdu_q;
1303 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1304 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
1305 "%d index %d\n", scd_ssn , index);
1306 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1307 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1308
1309 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1310 txq_id >= 0 && priv->mac80211_registered &&
1311 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
1312 /* calculate mac80211 ampdu sw queue to wake */
1313 ampdu_q = txq_id - IWL50_FIRST_AMPDU_QUEUE +
1314 priv->hw->queues;
1315 if (agg->state == IWL_AGG_OFF)
1316 ieee80211_wake_queue(priv->hw, txq_id);
1317 else
1318 ieee80211_wake_queue(priv->hw, ampdu_q);
1319 }
1320 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1321 }
1322 } else {
1323 info->status.retry_count = tx_resp->failure_frame;
1324 info->flags =
1325 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
1326 iwl_hwrate_to_tx_control(priv,
1327 le32_to_cpu(tx_resp->rate_n_flags),
1328 info);
1329
1330 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
1331 "0x%x retries %d\n", txq_id,
1332 iwl_get_tx_fail_reason(status),
1333 status, le32_to_cpu(tx_resp->rate_n_flags),
1334 tx_resp->failure_frame);
1335
1336 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
1337 if (index != -1) {
1338 int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1339 if (tid != MAX_TID_COUNT)
1340 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1341 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1342 (txq_id >= 0) && priv->mac80211_registered)
1343 ieee80211_wake_queue(priv->hw, txq_id);
1344 if (tid != MAX_TID_COUNT)
1345 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1346 }
1347 }
1348
1349 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1350 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1351}
1352
1353/* Currently 5000 is the supperset of everything */
1354static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1355{
1356 return len;
1357}
1358
1359static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1360{
1361 /* in 5000 the tx power calibration is done in uCode */
1362 priv->disable_tx_power_cal = 1;
1363}
1364
1365static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1366{
1367 /* init calibration handlers */
1368 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1369 iwl5000_rx_calib_result;
1370 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1371 iwl5000_rx_calib_complete;
1372 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1373}
1374
1375
1376static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1377{
1378 return (addr >= RTC_DATA_LOWER_BOUND) &&
1379 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1380}
1381
1382static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1383{
1384 int ret = 0;
1385 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1386 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1387 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1388
1389 if ((rxon1->flags == rxon2->flags) &&
1390 (rxon1->filter_flags == rxon2->filter_flags) &&
1391 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1392 (rxon1->ofdm_ht_single_stream_basic_rates ==
1393 rxon2->ofdm_ht_single_stream_basic_rates) &&
1394 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1395 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1396 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1397 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1398 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1399 (rxon1->rx_chain == rxon2->rx_chain) &&
1400 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1401 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1402 return 0;
1403 }
1404
1405 rxon_assoc.flags = priv->staging_rxon.flags;
1406 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1407 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1408 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1409 rxon_assoc.reserved1 = 0;
1410 rxon_assoc.reserved2 = 0;
1411 rxon_assoc.reserved3 = 0;
1412 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1413 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1414 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1415 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1416 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1417 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1418 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1419 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1420
1421 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1422 sizeof(rxon_assoc), &rxon_assoc, NULL);
1423 if (ret)
1424 return ret;
1425
1426 return ret;
1427}
1428static int iwl5000_send_tx_power(struct iwl_priv *priv)
1429{
1430 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1431
1432 /* half dBm need to multiply */
1433 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1434 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1435 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1436 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1437 sizeof(tx_power_cmd), &tx_power_cmd,
1438 NULL);
1439}
1440
1441static void iwl5000_temperature(struct iwl_priv *priv)
1442{
1443 /* store temperature from statistics (in Celsius) */
1444 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1445}
1446
1447static struct iwl_hcmd_ops iwl5000_hcmd = {
1448 .rxon_assoc = iwl5000_send_rxon_assoc,
1449};
1450
1451static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1452 .get_hcmd_size = iwl5000_get_hcmd_size,
1453 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1454 .gain_computation = iwl5000_gain_computation,
1455 .chain_noise_reset = iwl5000_chain_noise_reset,
1456 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1457};
1458
1459static struct iwl_lib_ops iwl5000_lib = {
1460 .set_hw_params = iwl5000_hw_set_hw_params,
1461 .alloc_shared_mem = iwl5000_alloc_shared_mem,
1462 .free_shared_mem = iwl5000_free_shared_mem,
1463 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
1464 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1465 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1466 .txq_set_sched = iwl5000_txq_set_sched,
1467 .txq_agg_enable = iwl5000_txq_agg_enable,
1468 .txq_agg_disable = iwl5000_txq_agg_disable,
1469 .rx_handler_setup = iwl5000_rx_handler_setup,
1470 .setup_deferred_work = iwl5000_setup_deferred_work,
1471 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1472 .load_ucode = iwl5000_load_ucode,
1473 .init_alive_start = iwl5000_init_alive_start,
1474 .alive_notify = iwl5000_alive_notify,
1475 .send_tx_power = iwl5000_send_tx_power,
1476 .temperature = iwl5000_temperature,
1477 .apm_ops = {
1478 .init = iwl5000_apm_init,
1479 .reset = iwl5000_apm_reset,
1480 .stop = iwl5000_apm_stop,
1481 .config = iwl5000_nic_config,
1482 .set_pwr_src = iwl4965_set_pwr_src,
1483 },
1484 .eeprom_ops = {
1485 .regulatory_bands = {
1486 EEPROM_5000_REG_BAND_1_CHANNELS,
1487 EEPROM_5000_REG_BAND_2_CHANNELS,
1488 EEPROM_5000_REG_BAND_3_CHANNELS,
1489 EEPROM_5000_REG_BAND_4_CHANNELS,
1490 EEPROM_5000_REG_BAND_5_CHANNELS,
1491 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1492 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1493 },
1494 .verify_signature = iwlcore_eeprom_verify_signature,
1495 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1496 .release_semaphore = iwlcore_eeprom_release_semaphore,
1497 .check_version = iwl5000_eeprom_check_version,
1498 .query_addr = iwl5000_eeprom_query_addr,
1499 },
1500};
1501
1502static struct iwl_ops iwl5000_ops = {
1503 .lib = &iwl5000_lib,
1504 .hcmd = &iwl5000_hcmd,
1505 .utils = &iwl5000_hcmd_utils,
1506};
1507
1508static struct iwl_mod_params iwl50_mod_params = {
1509 .num_of_queues = IWL50_NUM_QUEUES,
1510 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1511 .enable_qos = 1,
1512 .amsdu_size_8K = 1,
1513 .restart_fw = 1,
1514 /* the rest are 0 by default */
1515};
1516
1517
1518struct iwl_cfg iwl5300_agn_cfg = {
1519 .name = "5300AGN",
1520 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1521 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1522 .ops = &iwl5000_ops,
1523 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1524 .mod_params = &iwl50_mod_params,
1525};
1526
1527struct iwl_cfg iwl5100_bg_cfg = {
1528 .name = "5100BG",
1529 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1530 .sku = IWL_SKU_G,
1531 .ops = &iwl5000_ops,
1532 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1533 .mod_params = &iwl50_mod_params,
1534};
1535
1536struct iwl_cfg iwl5100_abg_cfg = {
1537 .name = "5100ABG",
1538 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1539 .sku = IWL_SKU_A|IWL_SKU_G,
1540 .ops = &iwl5000_ops,
1541 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1542 .mod_params = &iwl50_mod_params,
1543};
1544
1545struct iwl_cfg iwl5100_agn_cfg = {
1546 .name = "5100AGN",
1547 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1548 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1549 .ops = &iwl5000_ops,
1550 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1551 .mod_params = &iwl50_mod_params,
1552};
1553
1554struct iwl_cfg iwl5350_agn_cfg = {
1555 .name = "5350AGN",
1556 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1557 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1558 .ops = &iwl5000_ops,
1559 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1560 .mod_params = &iwl50_mod_params,
1561};
1562
1563module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1564MODULE_PARM_DESC(disable50,
1565 "manually disable the 50XX radio (default 0 [radio on])");
1566module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1567MODULE_PARM_DESC(swcrypto50,
1568 "using software crypto engine (default 0 [hardware])\n");
1569module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1570MODULE_PARM_DESC(debug50, "50XX debug output mask");
1571module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1572MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1573module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1574MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
1575module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1576MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1577module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1578MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1579module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1580MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
diff --git a/drivers/net/wireless/iwlwifi/iwl-calib.c b/drivers/net/wireless/iwlwifi/iwl-calib.c
new file mode 100644
index 000000000000..ef49440bd7f6
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-calib.c
@@ -0,0 +1,802 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Tomas Winkler <tomas.winkler@intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
62
63#include <net/mac80211.h>
64
65#include "iwl-dev.h"
66#include "iwl-core.h"
67#include "iwl-calib.h"
68
69/* "false alarms" are signals that our DSP tries to lock onto,
70 * but then determines that they are either noise, or transmissions
71 * from a distant wireless network (also "noise", really) that get
72 * "stepped on" by stronger transmissions within our own network.
73 * This algorithm attempts to set a sensitivity level that is high
74 * enough to receive all of our own network traffic, but not so
75 * high that our DSP gets too busy trying to lock onto non-network
76 * activity/noise. */
77static int iwl_sens_energy_cck(struct iwl_priv *priv,
78 u32 norm_fa,
79 u32 rx_enable_time,
80 struct statistics_general_data *rx_info)
81{
82 u32 max_nrg_cck = 0;
83 int i = 0;
84 u8 max_silence_rssi = 0;
85 u32 silence_ref = 0;
86 u8 silence_rssi_a = 0;
87 u8 silence_rssi_b = 0;
88 u8 silence_rssi_c = 0;
89 u32 val;
90
91 /* "false_alarms" values below are cross-multiplications to assess the
92 * numbers of false alarms within the measured period of actual Rx
93 * (Rx is off when we're txing), vs the min/max expected false alarms
94 * (some should be expected if rx is sensitive enough) in a
95 * hypothetical listening period of 200 time units (TU), 204.8 msec:
96 *
97 * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
98 *
99 * */
100 u32 false_alarms = norm_fa * 200 * 1024;
101 u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
102 u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
103 struct iwl_sensitivity_data *data = NULL;
104 const struct iwl_sensitivity_ranges *ranges = priv->hw_params.sens;
105
106 data = &(priv->sensitivity_data);
107
108 data->nrg_auto_corr_silence_diff = 0;
109
110 /* Find max silence rssi among all 3 receivers.
111 * This is background noise, which may include transmissions from other
112 * networks, measured during silence before our network's beacon */
113 silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
114 ALL_BAND_FILTER) >> 8);
115 silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
116 ALL_BAND_FILTER) >> 8);
117 silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
118 ALL_BAND_FILTER) >> 8);
119
120 val = max(silence_rssi_b, silence_rssi_c);
121 max_silence_rssi = max(silence_rssi_a, (u8) val);
122
123 /* Store silence rssi in 20-beacon history table */
124 data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
125 data->nrg_silence_idx++;
126 if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
127 data->nrg_silence_idx = 0;
128
129 /* Find max silence rssi across 20 beacon history */
130 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
131 val = data->nrg_silence_rssi[i];
132 silence_ref = max(silence_ref, val);
133 }
134 IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
135 silence_rssi_a, silence_rssi_b, silence_rssi_c,
136 silence_ref);
137
138 /* Find max rx energy (min value!) among all 3 receivers,
139 * measured during beacon frame.
140 * Save it in 10-beacon history table. */
141 i = data->nrg_energy_idx;
142 val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
143 data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
144
145 data->nrg_energy_idx++;
146 if (data->nrg_energy_idx >= 10)
147 data->nrg_energy_idx = 0;
148
149 /* Find min rx energy (max value) across 10 beacon history.
150 * This is the minimum signal level that we want to receive well.
151 * Add backoff (margin so we don't miss slightly lower energy frames).
152 * This establishes an upper bound (min value) for energy threshold. */
153 max_nrg_cck = data->nrg_value[0];
154 for (i = 1; i < 10; i++)
155 max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
156 max_nrg_cck += 6;
157
158 IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
159 rx_info->beacon_energy_a, rx_info->beacon_energy_b,
160 rx_info->beacon_energy_c, max_nrg_cck - 6);
161
162 /* Count number of consecutive beacons with fewer-than-desired
163 * false alarms. */
164 if (false_alarms < min_false_alarms)
165 data->num_in_cck_no_fa++;
166 else
167 data->num_in_cck_no_fa = 0;
168 IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
169 data->num_in_cck_no_fa);
170
171 /* If we got too many false alarms this time, reduce sensitivity */
172 if ((false_alarms > max_false_alarms) &&
173 (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK)) {
174 IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
175 false_alarms, max_false_alarms);
176 IWL_DEBUG_CALIB("... reducing sensitivity\n");
177 data->nrg_curr_state = IWL_FA_TOO_MANY;
178 /* Store for "fewer than desired" on later beacon */
179 data->nrg_silence_ref = silence_ref;
180
181 /* increase energy threshold (reduce nrg value)
182 * to decrease sensitivity */
183 if (data->nrg_th_cck >
184 (ranges->max_nrg_cck + NRG_STEP_CCK))
185 data->nrg_th_cck = data->nrg_th_cck
186 - NRG_STEP_CCK;
187 else
188 data->nrg_th_cck = ranges->max_nrg_cck;
189 /* Else if we got fewer than desired, increase sensitivity */
190 } else if (false_alarms < min_false_alarms) {
191 data->nrg_curr_state = IWL_FA_TOO_FEW;
192
193 /* Compare silence level with silence level for most recent
194 * healthy number or too many false alarms */
195 data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
196 (s32)silence_ref;
197
198 IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
199 false_alarms, min_false_alarms,
200 data->nrg_auto_corr_silence_diff);
201
202 /* Increase value to increase sensitivity, but only if:
203 * 1a) previous beacon did *not* have *too many* false alarms
204 * 1b) AND there's a significant difference in Rx levels
205 * from a previous beacon with too many, or healthy # FAs
206 * OR 2) We've seen a lot of beacons (100) with too few
207 * false alarms */
208 if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
209 ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
210 (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
211
212 IWL_DEBUG_CALIB("... increasing sensitivity\n");
213 /* Increase nrg value to increase sensitivity */
214 val = data->nrg_th_cck + NRG_STEP_CCK;
215 data->nrg_th_cck = min((u32)ranges->min_nrg_cck, val);
216 } else {
217 IWL_DEBUG_CALIB("... but not changing sensitivity\n");
218 }
219
220 /* Else we got a healthy number of false alarms, keep status quo */
221 } else {
222 IWL_DEBUG_CALIB(" FA in safe zone\n");
223 data->nrg_curr_state = IWL_FA_GOOD_RANGE;
224
225 /* Store for use in "fewer than desired" with later beacon */
226 data->nrg_silence_ref = silence_ref;
227
228 /* If previous beacon had too many false alarms,
229 * give it some extra margin by reducing sensitivity again
230 * (but don't go below measured energy of desired Rx) */
231 if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
232 IWL_DEBUG_CALIB("... increasing margin\n");
233 if (data->nrg_th_cck > (max_nrg_cck + NRG_MARGIN))
234 data->nrg_th_cck -= NRG_MARGIN;
235 else
236 data->nrg_th_cck = max_nrg_cck;
237 }
238 }
239
240 /* Make sure the energy threshold does not go above the measured
241 * energy of the desired Rx signals (reduced by backoff margin),
242 * or else we might start missing Rx frames.
243 * Lower value is higher energy, so we use max()!
244 */
245 data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
246 IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
247
248 data->nrg_prev_state = data->nrg_curr_state;
249
250 /* Auto-correlation CCK algorithm */
251 if (false_alarms > min_false_alarms) {
252
253 /* increase auto_corr values to decrease sensitivity
254 * so the DSP won't be disturbed by the noise
255 */
256 if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
257 data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
258 else {
259 val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
260 data->auto_corr_cck =
261 min((u32)ranges->auto_corr_max_cck, val);
262 }
263 val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
264 data->auto_corr_cck_mrc =
265 min((u32)ranges->auto_corr_max_cck_mrc, val);
266 } else if ((false_alarms < min_false_alarms) &&
267 ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
268 (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
269
270 /* Decrease auto_corr values to increase sensitivity */
271 val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
272 data->auto_corr_cck =
273 max((u32)ranges->auto_corr_min_cck, val);
274 val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
275 data->auto_corr_cck_mrc =
276 max((u32)ranges->auto_corr_min_cck_mrc, val);
277 }
278
279 return 0;
280}
281
282
283static int iwl_sens_auto_corr_ofdm(struct iwl_priv *priv,
284 u32 norm_fa,
285 u32 rx_enable_time)
286{
287 u32 val;
288 u32 false_alarms = norm_fa * 200 * 1024;
289 u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
290 u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
291 struct iwl_sensitivity_data *data = NULL;
292 const struct iwl_sensitivity_ranges *ranges = priv->hw_params.sens;
293
294 data = &(priv->sensitivity_data);
295
296 /* If we got too many false alarms this time, reduce sensitivity */
297 if (false_alarms > max_false_alarms) {
298
299 IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
300 false_alarms, max_false_alarms);
301
302 val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
303 data->auto_corr_ofdm =
304 min((u32)ranges->auto_corr_max_ofdm, val);
305
306 val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
307 data->auto_corr_ofdm_mrc =
308 min((u32)ranges->auto_corr_max_ofdm_mrc, val);
309
310 val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
311 data->auto_corr_ofdm_x1 =
312 min((u32)ranges->auto_corr_max_ofdm_x1, val);
313
314 val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
315 data->auto_corr_ofdm_mrc_x1 =
316 min((u32)ranges->auto_corr_max_ofdm_mrc_x1, val);
317 }
318
319 /* Else if we got fewer than desired, increase sensitivity */
320 else if (false_alarms < min_false_alarms) {
321
322 IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
323 false_alarms, min_false_alarms);
324
325 val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
326 data->auto_corr_ofdm =
327 max((u32)ranges->auto_corr_min_ofdm, val);
328
329 val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
330 data->auto_corr_ofdm_mrc =
331 max((u32)ranges->auto_corr_min_ofdm_mrc, val);
332
333 val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
334 data->auto_corr_ofdm_x1 =
335 max((u32)ranges->auto_corr_min_ofdm_x1, val);
336
337 val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
338 data->auto_corr_ofdm_mrc_x1 =
339 max((u32)ranges->auto_corr_min_ofdm_mrc_x1, val);
340 } else {
341 IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
342 min_false_alarms, false_alarms, max_false_alarms);
343 }
344 return 0;
345}
346
347/* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
348static int iwl_sensitivity_write(struct iwl_priv *priv)
349{
350 int ret = 0;
351 struct iwl_sensitivity_cmd cmd ;
352 struct iwl_sensitivity_data *data = NULL;
353 struct iwl_host_cmd cmd_out = {
354 .id = SENSITIVITY_CMD,
355 .len = sizeof(struct iwl_sensitivity_cmd),
356 .meta.flags = CMD_ASYNC,
357 .data = &cmd,
358 };
359
360 data = &(priv->sensitivity_data);
361
362 memset(&cmd, 0, sizeof(cmd));
363
364 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
365 cpu_to_le16((u16)data->auto_corr_ofdm);
366 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
367 cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
368 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
369 cpu_to_le16((u16)data->auto_corr_ofdm_x1);
370 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
371 cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
372
373 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
374 cpu_to_le16((u16)data->auto_corr_cck);
375 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
376 cpu_to_le16((u16)data->auto_corr_cck_mrc);
377
378 cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
379 cpu_to_le16((u16)data->nrg_th_cck);
380 cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
381 cpu_to_le16((u16)data->nrg_th_ofdm);
382
383 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
384 __constant_cpu_to_le16(190);
385 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
386 __constant_cpu_to_le16(390);
387 cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
388 __constant_cpu_to_le16(62);
389
390 IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
391 data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
392 data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
393 data->nrg_th_ofdm);
394
395 IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
396 data->auto_corr_cck, data->auto_corr_cck_mrc,
397 data->nrg_th_cck);
398
399 /* Update uCode's "work" table, and copy it to DSP */
400 cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
401
402 /* Don't send command to uCode if nothing has changed */
403 if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
404 sizeof(u16)*HD_TABLE_SIZE)) {
405 IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
406 return 0;
407 }
408
409 /* Copy table for comparison next time */
410 memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
411 sizeof(u16)*HD_TABLE_SIZE);
412
413 ret = iwl_send_cmd(priv, &cmd_out);
414 if (ret)
415 IWL_ERROR("SENSITIVITY_CMD failed\n");
416
417 return ret;
418}
419
420void iwl_init_sensitivity(struct iwl_priv *priv)
421{
422 int ret = 0;
423 int i;
424 struct iwl_sensitivity_data *data = NULL;
425 const struct iwl_sensitivity_ranges *ranges = priv->hw_params.sens;
426
427 if (priv->disable_sens_cal)
428 return;
429
430 IWL_DEBUG_CALIB("Start iwl_init_sensitivity\n");
431
432 /* Clear driver's sensitivity algo data */
433 data = &(priv->sensitivity_data);
434
435 if (ranges == NULL)
436 return;
437
438 memset(data, 0, sizeof(struct iwl_sensitivity_data));
439
440 data->num_in_cck_no_fa = 0;
441 data->nrg_curr_state = IWL_FA_TOO_MANY;
442 data->nrg_prev_state = IWL_FA_TOO_MANY;
443 data->nrg_silence_ref = 0;
444 data->nrg_silence_idx = 0;
445 data->nrg_energy_idx = 0;
446
447 for (i = 0; i < 10; i++)
448 data->nrg_value[i] = 0;
449
450 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
451 data->nrg_silence_rssi[i] = 0;
452
453 data->auto_corr_ofdm = 90;
454 data->auto_corr_ofdm_mrc = ranges->auto_corr_min_ofdm_mrc;
455 data->auto_corr_ofdm_x1 = ranges->auto_corr_min_ofdm_x1;
456 data->auto_corr_ofdm_mrc_x1 = ranges->auto_corr_min_ofdm_mrc_x1;
457 data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
458 data->auto_corr_cck_mrc = ranges->auto_corr_min_cck_mrc;
459 data->nrg_th_cck = ranges->nrg_th_cck;
460 data->nrg_th_ofdm = ranges->nrg_th_ofdm;
461
462 data->last_bad_plcp_cnt_ofdm = 0;
463 data->last_fa_cnt_ofdm = 0;
464 data->last_bad_plcp_cnt_cck = 0;
465 data->last_fa_cnt_cck = 0;
466
467 ret |= iwl_sensitivity_write(priv);
468 IWL_DEBUG_CALIB("<<return 0x%X\n", ret);
469}
470EXPORT_SYMBOL(iwl_init_sensitivity);
471
472void iwl_sensitivity_calibration(struct iwl_priv *priv,
473 struct iwl_notif_statistics *resp)
474{
475 u32 rx_enable_time;
476 u32 fa_cck;
477 u32 fa_ofdm;
478 u32 bad_plcp_cck;
479 u32 bad_plcp_ofdm;
480 u32 norm_fa_ofdm;
481 u32 norm_fa_cck;
482 struct iwl_sensitivity_data *data = NULL;
483 struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
484 struct statistics_rx *statistics = &(resp->rx);
485 unsigned long flags;
486 struct statistics_general_data statis;
487
488 if (priv->disable_sens_cal)
489 return;
490
491 data = &(priv->sensitivity_data);
492
493 if (!iwl_is_associated(priv)) {
494 IWL_DEBUG_CALIB("<< - not associated\n");
495 return;
496 }
497
498 spin_lock_irqsave(&priv->lock, flags);
499 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
500 IWL_DEBUG_CALIB("<< invalid data.\n");
501 spin_unlock_irqrestore(&priv->lock, flags);
502 return;
503 }
504
505 /* Extract Statistics: */
506 rx_enable_time = le32_to_cpu(rx_info->channel_load);
507 fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
508 fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
509 bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
510 bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
511
512 statis.beacon_silence_rssi_a =
513 le32_to_cpu(statistics->general.beacon_silence_rssi_a);
514 statis.beacon_silence_rssi_b =
515 le32_to_cpu(statistics->general.beacon_silence_rssi_b);
516 statis.beacon_silence_rssi_c =
517 le32_to_cpu(statistics->general.beacon_silence_rssi_c);
518 statis.beacon_energy_a =
519 le32_to_cpu(statistics->general.beacon_energy_a);
520 statis.beacon_energy_b =
521 le32_to_cpu(statistics->general.beacon_energy_b);
522 statis.beacon_energy_c =
523 le32_to_cpu(statistics->general.beacon_energy_c);
524
525 spin_unlock_irqrestore(&priv->lock, flags);
526
527 IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
528
529 if (!rx_enable_time) {
530 IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
531 return;
532 }
533
534 /* These statistics increase monotonically, and do not reset
535 * at each beacon. Calculate difference from last value, or just
536 * use the new statistics value if it has reset or wrapped around. */
537 if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
538 data->last_bad_plcp_cnt_cck = bad_plcp_cck;
539 else {
540 bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
541 data->last_bad_plcp_cnt_cck += bad_plcp_cck;
542 }
543
544 if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
545 data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
546 else {
547 bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
548 data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
549 }
550
551 if (data->last_fa_cnt_ofdm > fa_ofdm)
552 data->last_fa_cnt_ofdm = fa_ofdm;
553 else {
554 fa_ofdm -= data->last_fa_cnt_ofdm;
555 data->last_fa_cnt_ofdm += fa_ofdm;
556 }
557
558 if (data->last_fa_cnt_cck > fa_cck)
559 data->last_fa_cnt_cck = fa_cck;
560 else {
561 fa_cck -= data->last_fa_cnt_cck;
562 data->last_fa_cnt_cck += fa_cck;
563 }
564
565 /* Total aborted signal locks */
566 norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
567 norm_fa_cck = fa_cck + bad_plcp_cck;
568
569 IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
570 bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
571
572 iwl_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
573 iwl_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
574 iwl_sensitivity_write(priv);
575
576 return;
577}
578EXPORT_SYMBOL(iwl_sensitivity_calibration);
579
580/*
581 * Accumulate 20 beacons of signal and noise statistics for each of
582 * 3 receivers/antennas/rx-chains, then figure out:
583 * 1) Which antennas are connected.
584 * 2) Differential rx gain settings to balance the 3 receivers.
585 */
586void iwl_chain_noise_calibration(struct iwl_priv *priv,
587 struct iwl_notif_statistics *stat_resp)
588{
589 struct iwl_chain_noise_data *data = NULL;
590
591 u32 chain_noise_a;
592 u32 chain_noise_b;
593 u32 chain_noise_c;
594 u32 chain_sig_a;
595 u32 chain_sig_b;
596 u32 chain_sig_c;
597 u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
598 u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
599 u32 max_average_sig;
600 u16 max_average_sig_antenna_i;
601 u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
602 u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
603 u16 i = 0;
604 u16 rxon_chnum = INITIALIZATION_VALUE;
605 u16 stat_chnum = INITIALIZATION_VALUE;
606 u8 rxon_band24;
607 u8 stat_band24;
608 u32 active_chains = 0;
609 u8 num_tx_chains;
610 unsigned long flags;
611 struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
612
613 if (priv->disable_chain_noise_cal)
614 return;
615
616 data = &(priv->chain_noise_data);
617
618 /* Accumulate just the first 20 beacons after the first association,
619 * then we're done forever. */
620 if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
621 if (data->state == IWL_CHAIN_NOISE_ALIVE)
622 IWL_DEBUG_CALIB("Wait for noise calib reset\n");
623 return;
624 }
625
626 spin_lock_irqsave(&priv->lock, flags);
627 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
628 IWL_DEBUG_CALIB(" << Interference data unavailable\n");
629 spin_unlock_irqrestore(&priv->lock, flags);
630 return;
631 }
632
633 rxon_band24 = !!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK);
634 rxon_chnum = le16_to_cpu(priv->staging_rxon.channel);
635 stat_band24 = !!(stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK);
636 stat_chnum = le32_to_cpu(stat_resp->flag) >> 16;
637
638 /* Make sure we accumulate data for just the associated channel
639 * (even if scanning). */
640 if ((rxon_chnum != stat_chnum) || (rxon_band24 != stat_band24)) {
641 IWL_DEBUG_CALIB("Stats not from chan=%d, band24=%d\n",
642 rxon_chnum, rxon_band24);
643 spin_unlock_irqrestore(&priv->lock, flags);
644 return;
645 }
646
647 /* Accumulate beacon statistics values across 20 beacons */
648 chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
649 IN_BAND_FILTER;
650 chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
651 IN_BAND_FILTER;
652 chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
653 IN_BAND_FILTER;
654
655 chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
656 chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
657 chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
658
659 spin_unlock_irqrestore(&priv->lock, flags);
660
661 data->beacon_count++;
662
663 data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
664 data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
665 data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
666
667 data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
668 data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
669 data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
670
671 IWL_DEBUG_CALIB("chan=%d, band24=%d, beacon=%d\n",
672 rxon_chnum, rxon_band24, data->beacon_count);
673 IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
674 chain_sig_a, chain_sig_b, chain_sig_c);
675 IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
676 chain_noise_a, chain_noise_b, chain_noise_c);
677
678 /* If this is the 20th beacon, determine:
679 * 1) Disconnected antennas (using signal strengths)
680 * 2) Differential gain (using silence noise) to balance receivers */
681 if (data->beacon_count != CAL_NUM_OF_BEACONS)
682 return;
683
684 /* Analyze signal for disconnected antenna */
685 average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
686 average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
687 average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
688
689 if (average_sig[0] >= average_sig[1]) {
690 max_average_sig = average_sig[0];
691 max_average_sig_antenna_i = 0;
692 active_chains = (1 << max_average_sig_antenna_i);
693 } else {
694 max_average_sig = average_sig[1];
695 max_average_sig_antenna_i = 1;
696 active_chains = (1 << max_average_sig_antenna_i);
697 }
698
699 if (average_sig[2] >= max_average_sig) {
700 max_average_sig = average_sig[2];
701 max_average_sig_antenna_i = 2;
702 active_chains = (1 << max_average_sig_antenna_i);
703 }
704
705 IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
706 average_sig[0], average_sig[1], average_sig[2]);
707 IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
708 max_average_sig, max_average_sig_antenna_i);
709
710 /* Compare signal strengths for all 3 receivers. */
711 for (i = 0; i < NUM_RX_CHAINS; i++) {
712 if (i != max_average_sig_antenna_i) {
713 s32 rssi_delta = (max_average_sig - average_sig[i]);
714
715 /* If signal is very weak, compared with
716 * strongest, mark it as disconnected. */
717 if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
718 data->disconn_array[i] = 1;
719 else
720 active_chains |= (1 << i);
721 IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
722 "disconn_array[i] = %d\n",
723 i, rssi_delta, data->disconn_array[i]);
724 }
725 }
726
727 num_tx_chains = 0;
728 for (i = 0; i < NUM_RX_CHAINS; i++) {
729 /* loops on all the bits of
730 * priv->hw_setting.valid_tx_ant */
731 u8 ant_msk = (1 << i);
732 if (!(priv->hw_params.valid_tx_ant & ant_msk))
733 continue;
734
735 num_tx_chains++;
736 if (data->disconn_array[i] == 0)
737 /* there is a Tx antenna connected */
738 break;
739 if (num_tx_chains == priv->hw_params.tx_chains_num &&
740 data->disconn_array[i]) {
741 /* This is the last TX antenna and is also
742 * disconnected connect it anyway */
743 data->disconn_array[i] = 0;
744 active_chains |= ant_msk;
745 IWL_DEBUG_CALIB("All Tx chains are disconnected W/A - "
746 "declare %d as connected\n", i);
747 break;
748 }
749 }
750
751 IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
752 active_chains);
753
754 /* Save for use within RXON, TX, SCAN commands, etc. */
755 /*priv->valid_antenna = active_chains;*/
756 /*FIXME: should be reflected in RX chains in RXON */
757
758 /* Analyze noise for rx balance */
759 average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
760 average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
761 average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
762
763 for (i = 0; i < NUM_RX_CHAINS; i++) {
764 if (!(data->disconn_array[i]) &&
765 (average_noise[i] <= min_average_noise)) {
766 /* This means that chain i is active and has
767 * lower noise values so far: */
768 min_average_noise = average_noise[i];
769 min_average_noise_antenna_i = i;
770 }
771 }
772
773 IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
774 average_noise[0], average_noise[1],
775 average_noise[2]);
776
777 IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
778 min_average_noise, min_average_noise_antenna_i);
779
780 priv->cfg->ops->utils->gain_computation(priv, average_noise,
781 min_average_noise_antenna_i, min_average_noise);
782}
783EXPORT_SYMBOL(iwl_chain_noise_calibration);
784
785
786void iwl_reset_run_time_calib(struct iwl_priv *priv)
787{
788 int i;
789 memset(&(priv->sensitivity_data), 0,
790 sizeof(struct iwl_sensitivity_data));
791 memset(&(priv->chain_noise_data), 0,
792 sizeof(struct iwl_chain_noise_data));
793 for (i = 0; i < NUM_RX_CHAINS; i++)
794 priv->chain_noise_data.delta_gain_code[i] =
795 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
796
797 /* Ask for statistics now, the uCode will send notification
798 * periodically after association */
799 iwl_send_statistics_request(priv, CMD_ASYNC);
800}
801EXPORT_SYMBOL(iwl_reset_run_time_calib);
802
diff --git a/drivers/net/wireless/iwlwifi/iwl-calib.h b/drivers/net/wireless/iwlwifi/iwl-calib.h
new file mode 100644
index 000000000000..94c8e316382a
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-calib.h
@@ -0,0 +1,84 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Tomas Winkler <tomas.winkler@intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
62#ifndef __iwl_calib_h__
63#define __iwl_calib_h__
64
65#include "iwl-dev.h"
66#include "iwl-core.h"
67#include "iwl-commands.h"
68
69void iwl_chain_noise_calibration(struct iwl_priv *priv,
70 struct iwl_notif_statistics *stat_resp);
71void iwl_sensitivity_calibration(struct iwl_priv *priv,
72 struct iwl_notif_statistics *resp);
73
74void iwl_init_sensitivity(struct iwl_priv *priv);
75void iwl_reset_run_time_calib(struct iwl_priv *priv);
76static inline void iwl_chain_noise_reset(struct iwl_priv *priv)
77{
78
79 if (!priv->disable_chain_noise_cal &&
80 priv->cfg->ops->utils->chain_noise_reset)
81 priv->cfg->ops->utils->chain_noise_reset(priv);
82}
83
84#endif /* __iwl_calib_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-commands.h b/drivers/net/wireless/iwlwifi/iwl-commands.h
index 3bcd107e2d71..e9bb1de0ce3f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-commands.h
+++ b/drivers/net/wireless/iwlwifi/iwl-commands.h
@@ -61,9 +61,9 @@
61 * 61 *
62 *****************************************************************************/ 62 *****************************************************************************/
63/* 63/*
64 * Please use this file (iwl-4965-commands.h) only for uCode API definitions. 64 * Please use this file (iwl-commands.h) only for uCode API definitions.
65 * Please use iwl-4965-hw.h for hardware-related definitions. 65 * Please use iwl-4965-hw.h for hardware-related definitions.
66 * Please use iwl-4965.h for driver implementation definitions. 66 * Please use iwl-dev.h for driver implementation definitions.
67 */ 67 */
68 68
69#ifndef __iwl4965_commands_h__ 69#ifndef __iwl4965_commands_h__
@@ -93,6 +93,11 @@ enum {
93 REPLY_LEDS_CMD = 0x48, 93 REPLY_LEDS_CMD = 0x48,
94 REPLY_TX_LINK_QUALITY_CMD = 0x4e, /* 4965 only */ 94 REPLY_TX_LINK_QUALITY_CMD = 0x4e, /* 4965 only */
95 95
96 /* WiMAX coexistence */
97 COEX_PRIORITY_TABLE_CMD = 0x5a, /*5000 only */
98 COEX_MEDIUM_NOTIFICATION = 0x5b,
99 COEX_EVENT_CMD = 0x5c,
100
96 /* 802.11h related */ 101 /* 802.11h related */
97 RADAR_NOTIFICATION = 0x70, /* not used */ 102 RADAR_NOTIFICATION = 0x70, /* not used */
98 REPLY_QUIET_CMD = 0x71, /* not used */ 103 REPLY_QUIET_CMD = 0x71, /* not used */
@@ -121,6 +126,7 @@ enum {
121 /* Miscellaneous commands */ 126 /* Miscellaneous commands */
122 QUIET_NOTIFICATION = 0x96, /* not used */ 127 QUIET_NOTIFICATION = 0x96, /* not used */
123 REPLY_TX_PWR_TABLE_CMD = 0x97, 128 REPLY_TX_PWR_TABLE_CMD = 0x97,
129 REPLY_TX_POWER_DBM_CMD = 0x98,
124 MEASURE_ABORT_NOTIFICATION = 0x99, /* not used */ 130 MEASURE_ABORT_NOTIFICATION = 0x99, /* not used */
125 131
126 /* Bluetooth device coexistance config command */ 132 /* Bluetooth device coexistance config command */
@@ -269,21 +275,13 @@ struct iwl_cmd_header {
269 * 10 B active, A inactive 275 * 10 B active, A inactive
270 * 11 Both active 276 * 11 Both active
271 */ 277 */
272#define RATE_MCS_ANT_POS 14 278#define RATE_MCS_ANT_POS 14
273#define RATE_MCS_ANT_A_MSK 0x04000 279#define RATE_MCS_ANT_A_MSK 0x04000
274#define RATE_MCS_ANT_B_MSK 0x08000 280#define RATE_MCS_ANT_B_MSK 0x08000
275#define RATE_MCS_ANT_AB_MSK 0x0C000 281#define RATE_MCS_ANT_C_MSK 0x10000
282#define RATE_MCS_ANT_ABC_MSK 0x1C000
276 283
277 284#define RATE_MCS_ANT_INIT_IND 1
278/**
279 * struct iwl4965_tx_power - txpower format used in REPLY_SCAN_CMD
280 *
281 * Scan uses only one transmitter, so only one analog/dsp gain pair is needed.
282 */
283struct iwl4965_tx_power {
284 u8 tx_gain; /* gain for analog radio */
285 u8 dsp_atten; /* gain for DSP */
286} __attribute__ ((packed));
287 285
288#define POWER_TABLE_NUM_ENTRIES 33 286#define POWER_TABLE_NUM_ENTRIES 33
289#define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32 287#define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32
@@ -333,6 +331,19 @@ struct iwl4965_tx_power_db {
333 struct tx_power_dual_stream power_tbl[POWER_TABLE_NUM_ENTRIES]; 331 struct tx_power_dual_stream power_tbl[POWER_TABLE_NUM_ENTRIES];
334} __attribute__ ((packed)); 332} __attribute__ ((packed));
335 333
334/**
335 * Commad REPLY_TX_POWER_DBM_CMD = 0x98
336 * struct iwl5000_tx_power_dbm_cmd
337 */
338#define IWL50_TX_POWER_AUTO 0x7f
339#define IWL50_TX_POWER_NO_CLOSED (0x1 << 6)
340
341struct iwl5000_tx_power_dbm_cmd {
342 s8 global_lmt; /*in half-dBm (e.g. 30 = 15 dBm) */
343 u8 flags;
344 s8 srv_chan_lmt; /*in half-dBm (e.g. 30 = 15 dBm) */
345 u8 reserved;
346} __attribute__ ((packed));
336 347
337/****************************************************************************** 348/******************************************************************************
338 * (0a) 349 * (0a)
@@ -367,7 +378,7 @@ struct iwl4965_tx_power_db {
367 * 3) Tx gain compensation to balance 4965's 2 Tx chains for MIMO operation, 378 * 3) Tx gain compensation to balance 4965's 2 Tx chains for MIMO operation,
368 * for each of 5 frequency ranges. 379 * for each of 5 frequency ranges.
369 */ 380 */
370struct iwl4965_init_alive_resp { 381struct iwl_init_alive_resp {
371 u8 ucode_minor; 382 u8 ucode_minor;
372 u8 ucode_major; 383 u8 ucode_major;
373 __le16 reserved1; 384 __le16 reserved1;
@@ -443,7 +454,7 @@ struct iwl4965_init_alive_resp {
443 * The Linux driver can print both logs to the system log when a uCode error 454 * The Linux driver can print both logs to the system log when a uCode error
444 * occurs. 455 * occurs.
445 */ 456 */
446struct iwl4965_alive_resp { 457struct iwl_alive_resp {
447 u8 ucode_minor; 458 u8 ucode_minor;
448 u8 ucode_major; 459 u8 ucode_major;
449 __le16 reserved1; 460 __le16 reserved1;
@@ -467,7 +478,7 @@ union tsf {
467/* 478/*
468 * REPLY_ERROR = 0x2 (response only, not a command) 479 * REPLY_ERROR = 0x2 (response only, not a command)
469 */ 480 */
470struct iwl4965_error_resp { 481struct iwl_error_resp {
471 __le32 error_type; 482 __le32 error_type;
472 u8 cmd_id; 483 u8 cmd_id;
473 u8 reserved1; 484 u8 reserved1;
@@ -545,6 +556,8 @@ enum {
545#define RXON_FLG_CHANNEL_MODE_MSK __constant_cpu_to_le32(0x3 << 25) 556#define RXON_FLG_CHANNEL_MODE_MSK __constant_cpu_to_le32(0x3 << 25)
546#define RXON_FLG_CHANNEL_MODE_PURE_40_MSK __constant_cpu_to_le32(0x1 << 25) 557#define RXON_FLG_CHANNEL_MODE_PURE_40_MSK __constant_cpu_to_le32(0x1 << 25)
547#define RXON_FLG_CHANNEL_MODE_MIXED_MSK __constant_cpu_to_le32(0x2 << 25) 558#define RXON_FLG_CHANNEL_MODE_MIXED_MSK __constant_cpu_to_le32(0x2 << 25)
559/* CTS to self (if spec allows) flag */
560#define RXON_FLG_SELF_CTS_EN __constant_cpu_to_le32(0x1<<30)
548 561
549/* rx_config filter flags */ 562/* rx_config filter flags */
550/* accept all data frames */ 563/* accept all data frames */
@@ -599,6 +612,46 @@ struct iwl4965_rxon_cmd {
599 u8 ofdm_ht_dual_stream_basic_rates; 612 u8 ofdm_ht_dual_stream_basic_rates;
600} __attribute__ ((packed)); 613} __attribute__ ((packed));
601 614
615/* 5000 HW just extend this cmmand */
616struct iwl_rxon_cmd {
617 u8 node_addr[6];
618 __le16 reserved1;
619 u8 bssid_addr[6];
620 __le16 reserved2;
621 u8 wlap_bssid_addr[6];
622 __le16 reserved3;
623 u8 dev_type;
624 u8 air_propagation;
625 __le16 rx_chain;
626 u8 ofdm_basic_rates;
627 u8 cck_basic_rates;
628 __le16 assoc_id;
629 __le32 flags;
630 __le32 filter_flags;
631 __le16 channel;
632 u8 ofdm_ht_single_stream_basic_rates;
633 u8 ofdm_ht_dual_stream_basic_rates;
634 u8 ofdm_ht_triple_stream_basic_rates;
635 u8 reserved5;
636 __le16 acquisition_data;
637 __le16 reserved6;
638} __attribute__ ((packed));
639
640struct iwl5000_rxon_assoc_cmd {
641 __le32 flags;
642 __le32 filter_flags;
643 u8 ofdm_basic_rates;
644 u8 cck_basic_rates;
645 __le16 reserved1;
646 u8 ofdm_ht_single_stream_basic_rates;
647 u8 ofdm_ht_dual_stream_basic_rates;
648 u8 ofdm_ht_triple_stream_basic_rates;
649 u8 reserved2;
650 __le16 rx_chain_select_flags;
651 __le16 acquisition_data;
652 __le32 reserved3;
653} __attribute__ ((packed));
654
602/* 655/*
603 * REPLY_RXON_ASSOC = 0x11 (command, has simple generic response) 656 * REPLY_RXON_ASSOC = 0x11 (command, has simple generic response)
604 */ 657 */
@@ -613,6 +666,9 @@ struct iwl4965_rxon_assoc_cmd {
613 __le16 reserved; 666 __le16 reserved;
614} __attribute__ ((packed)); 667} __attribute__ ((packed));
615 668
669
670
671
616/* 672/*
617 * REPLY_RXON_TIMING = 0x14 (command, has simple generic response) 673 * REPLY_RXON_TIMING = 0x14 (command, has simple generic response)
618 */ 674 */
@@ -669,7 +725,7 @@ struct iwl4965_csa_notification {
669 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 725 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
670 * value, to cap the CW value. 726 * value, to cap the CW value.
671 */ 727 */
672struct iwl4965_ac_qos { 728struct iwl_ac_qos {
673 __le16 cw_min; 729 __le16 cw_min;
674 __le16 cw_max; 730 __le16 cw_max;
675 u8 aifsn; 731 u8 aifsn;
@@ -691,9 +747,9 @@ struct iwl4965_ac_qos {
691 * This command sets up timings for each of the 4 prioritized EDCA Tx FIFOs 747 * This command sets up timings for each of the 4 prioritized EDCA Tx FIFOs
692 * 0: Background, 1: Best Effort, 2: Video, 3: Voice. 748 * 0: Background, 1: Best Effort, 2: Video, 3: Voice.
693 */ 749 */
694struct iwl4965_qosparam_cmd { 750struct iwl_qosparam_cmd {
695 __le32 qos_flags; 751 __le32 qos_flags;
696 struct iwl4965_ac_qos ac[AC_NUM]; 752 struct iwl_ac_qos ac[AC_NUM];
697} __attribute__ ((packed)); 753} __attribute__ ((packed));
698 754
699/****************************************************************************** 755/******************************************************************************
@@ -711,6 +767,8 @@ struct iwl4965_qosparam_cmd {
711#define IWL_STA_ID 2 767#define IWL_STA_ID 2
712#define IWL4965_BROADCAST_ID 31 768#define IWL4965_BROADCAST_ID 31
713#define IWL4965_STATION_COUNT 32 769#define IWL4965_STATION_COUNT 32
770#define IWL5000_BROADCAST_ID 15
771#define IWL5000_STATION_COUNT 16
714 772
715#define IWL_STATION_COUNT 32 /* MAX(3945,4965)*/ 773#define IWL_STATION_COUNT 32 /* MAX(3945,4965)*/
716#define IWL_INVALID_STATION 255 774#define IWL_INVALID_STATION 255
@@ -766,6 +824,20 @@ struct iwl4965_keyinfo {
766 u8 key[16]; /* 16-byte unicast decryption key */ 824 u8 key[16]; /* 16-byte unicast decryption key */
767} __attribute__ ((packed)); 825} __attribute__ ((packed));
768 826
827/* 5000 */
828struct iwl_keyinfo {
829 __le16 key_flags;
830 u8 tkip_rx_tsc_byte2; /* TSC[2] for key mix ph1 detection */
831 u8 reserved1;
832 __le16 tkip_rx_ttak[5]; /* 10-byte unicast TKIP TTAK */
833 u8 key_offset;
834 u8 reserved2;
835 u8 key[16]; /* 16-byte unicast decryption key */
836 __le64 tx_secur_seq_cnt;
837 __le64 hw_tkip_mic_rx_key;
838 __le64 hw_tkip_mic_tx_key;
839} __attribute__ ((packed));
840
769/** 841/**
770 * struct sta_id_modify 842 * struct sta_id_modify
771 * @addr[ETH_ALEN]: station's MAC address 843 * @addr[ETH_ALEN]: station's MAC address
@@ -841,6 +913,38 @@ struct iwl4965_addsta_cmd {
841 __le32 reserved2; 913 __le32 reserved2;
842} __attribute__ ((packed)); 914} __attribute__ ((packed));
843 915
916/* 5000 */
917struct iwl_addsta_cmd {
918 u8 mode; /* 1: modify existing, 0: add new station */
919 u8 reserved[3];
920 struct sta_id_modify sta;
921 struct iwl_keyinfo key;
922 __le32 station_flags; /* STA_FLG_* */
923 __le32 station_flags_msk; /* STA_FLG_* */
924
925 /* bit field to disable (1) or enable (0) Tx for Traffic ID (TID)
926 * corresponding to bit (e.g. bit 5 controls TID 5).
927 * Set modify_mask bit STA_MODIFY_TID_DISABLE_TX to use this field. */
928 __le16 tid_disable_tx;
929
930 __le16 reserved1;
931
932 /* TID for which to add block-ack support.
933 * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
934 u8 add_immediate_ba_tid;
935
936 /* TID for which to remove block-ack support.
937 * Set modify_mask bit STA_MODIFY_DELBA_TID_MSK to use this field. */
938 u8 remove_immediate_ba_tid;
939
940 /* Starting Sequence Number for added block-ack support.
941 * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
942 __le16 add_immediate_ba_ssn;
943
944 __le32 reserved2;
945} __attribute__ ((packed));
946
947
844#define ADD_STA_SUCCESS_MSK 0x1 948#define ADD_STA_SUCCESS_MSK 0x1
845#define ADD_STA_NO_ROOM_IN_TABLE 0x2 949#define ADD_STA_NO_ROOM_IN_TABLE 0x2
846#define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4 950#define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4
@@ -848,10 +952,28 @@ struct iwl4965_addsta_cmd {
848/* 952/*
849 * REPLY_ADD_STA = 0x18 (response) 953 * REPLY_ADD_STA = 0x18 (response)
850 */ 954 */
851struct iwl4965_add_sta_resp { 955struct iwl_add_sta_resp {
852 u8 status; /* ADD_STA_* */ 956 u8 status; /* ADD_STA_* */
853} __attribute__ ((packed)); 957} __attribute__ ((packed));
854 958
959#define REM_STA_SUCCESS_MSK 0x1
960/*
961 * REPLY_REM_STA = 0x19 (response)
962 */
963struct iwl_rem_sta_resp {
964 u8 status;
965} __attribute__ ((packed));
966
967/*
968 * REPLY_REM_STA = 0x19 (command)
969 */
970struct iwl_rem_sta_cmd {
971 u8 num_sta; /* number of removed stations */
972 u8 reserved[3];
973 u8 addr[ETH_ALEN]; /* MAC addr of the first station */
974 u8 reserved2[2];
975} __attribute__ ((packed));
976
855/* 977/*
856 * REPLY_WEP_KEY = 0x20 978 * REPLY_WEP_KEY = 0x20
857 */ 979 */
@@ -875,6 +997,7 @@ struct iwl_wep_cmd {
875#define WEP_KEY_WEP_TYPE 1 997#define WEP_KEY_WEP_TYPE 1
876#define WEP_KEYS_MAX 4 998#define WEP_KEYS_MAX 4
877#define WEP_INVALID_OFFSET 0xff 999#define WEP_INVALID_OFFSET 0xff
1000#define WEP_KEY_LEN_64 5
878#define WEP_KEY_LEN_128 13 1001#define WEP_KEY_LEN_128 13
879 1002
880/****************************************************************************** 1003/******************************************************************************
@@ -1018,6 +1141,11 @@ struct iwl4965_rx_mpdu_res_start {
1018 1141
1019/* REPLY_TX Tx flags field */ 1142/* REPLY_TX Tx flags field */
1020 1143
1144/* 1: Use RTS/CTS protocol or CTS-to-self if spec alows it
1145 * before this frame. if CTS-to-self required check
1146 * RXON_FLG_SELF_CTS_EN status. */
1147#define TX_CMD_FLG_RTS_CTS_MSK __constant_cpu_to_le32(1 << 0)
1148
1021/* 1: Use Request-To-Send protocol before this frame. 1149/* 1: Use Request-To-Send protocol before this frame.
1022 * Mutually exclusive vs. TX_CMD_FLG_CTS_MSK. */ 1150 * Mutually exclusive vs. TX_CMD_FLG_CTS_MSK. */
1023#define TX_CMD_FLG_RTS_MSK __constant_cpu_to_le32(1 << 1) 1151#define TX_CMD_FLG_RTS_MSK __constant_cpu_to_le32(1 << 1)
@@ -1100,6 +1228,14 @@ struct iwl4965_rx_mpdu_res_start {
1100#define TX_CMD_SEC_KEY128 0x08 1228#define TX_CMD_SEC_KEY128 0x08
1101 1229
1102/* 1230/*
1231 * security overhead sizes
1232 */
1233#define WEP_IV_LEN 4
1234#define WEP_ICV_LEN 4
1235#define CCMP_MIC_LEN 8
1236#define TKIP_ICV_LEN 4
1237
1238/*
1103 * 4965 uCode updates these Tx attempt count values in host DRAM. 1239 * 4965 uCode updates these Tx attempt count values in host DRAM.
1104 * Used for managing Tx retries when expecting block-acks. 1240 * Used for managing Tx retries when expecting block-acks.
1105 * Driver should set these fields to 0. 1241 * Driver should set these fields to 0.
@@ -1113,7 +1249,7 @@ struct iwl4965_dram_scratch {
1113/* 1249/*
1114 * REPLY_TX = 0x1c (command) 1250 * REPLY_TX = 0x1c (command)
1115 */ 1251 */
1116struct iwl4965_tx_cmd { 1252struct iwl_tx_cmd {
1117 /* 1253 /*
1118 * MPDU byte count: 1254 * MPDU byte count:
1119 * MAC header (24/26/30/32 bytes) + 2 bytes pad if 26/30 header size, 1255 * MAC header (24/26/30/32 bytes) + 2 bytes pad if 26/30 header size,
@@ -1259,6 +1395,15 @@ enum {
1259 TX_ABORT_REQUIRED_MSK = 0x80000000, /* bits 31:31 */ 1395 TX_ABORT_REQUIRED_MSK = 0x80000000, /* bits 31:31 */
1260}; 1396};
1261 1397
1398static inline int iwl_is_tx_success(u32 status)
1399{
1400 status &= TX_STATUS_MSK;
1401 return (status == TX_STATUS_SUCCESS)
1402 || (status == TX_STATUS_DIRECT_DONE);
1403}
1404
1405
1406
1262/* ******************************* 1407/* *******************************
1263 * TX aggregation status 1408 * TX aggregation status
1264 ******************************* */ 1409 ******************************* */
@@ -1313,6 +1458,11 @@ enum {
1313 * within the sending station (this 4965), rather than whether it was 1458 * within the sending station (this 4965), rather than whether it was
1314 * received successfully by the destination station. 1459 * received successfully by the destination station.
1315 */ 1460 */
1461struct agg_tx_status {
1462 __le16 status;
1463 __le16 sequence;
1464} __attribute__ ((packed));
1465
1316struct iwl4965_tx_resp { 1466struct iwl4965_tx_resp {
1317 u8 frame_count; /* 1 no aggregation, >1 aggregation */ 1467 u8 frame_count; /* 1 no aggregation, >1 aggregation */
1318 u8 bt_kill_count; /* # blocked by bluetooth (unused for agg) */ 1468 u8 bt_kill_count; /* # blocked by bluetooth (unused for agg) */
@@ -1344,34 +1494,56 @@ struct iwl4965_tx_resp {
1344 * table entry used for all frames in the new agg. 1494 * table entry used for all frames in the new agg.
1345 * 31-16: Sequence # for this frame's Tx cmd (not SSN!) 1495 * 31-16: Sequence # for this frame's Tx cmd (not SSN!)
1346 */ 1496 */
1347 __le32 status; /* TX status (for aggregation status of 1st frame) */ 1497 union {
1498 __le32 status;
1499 struct agg_tx_status agg_status[0]; /* for each agg frame */
1500 } u;
1348} __attribute__ ((packed)); 1501} __attribute__ ((packed));
1349 1502
1350struct agg_tx_status { 1503struct iwl5000_tx_resp {
1351 __le16 status; 1504 u8 frame_count; /* 1 no aggregation, >1 aggregation */
1352 __le16 sequence; 1505 u8 bt_kill_count; /* # blocked by bluetooth (unused for agg) */
1353} __attribute__ ((packed)); 1506 u8 failure_rts; /* # failures due to unsuccessful RTS */
1507 u8 failure_frame; /* # failures due to no ACK (unused for agg) */
1354 1508
1355struct iwl4965_tx_resp_agg { 1509 /* For non-agg: Rate at which frame was successful.
1356 u8 frame_count; /* 1 no aggregation, >1 aggregation */ 1510 * For agg: Rate at which all frames were transmitted. */
1357 u8 reserved1; 1511 __le32 rate_n_flags; /* RATE_MCS_* */
1358 u8 failure_rts; 1512
1359 u8 failure_frame; 1513 /* For non-agg: RTS + CTS + frame tx attempts time + ACK.
1360 __le32 rate_n_flags; 1514 * For agg: RTS + CTS + aggregation tx time + block-ack time. */
1361 __le16 wireless_media_time; 1515 __le16 wireless_media_time; /* uSecs */
1362 __le16 reserved3; 1516
1363 __le32 pa_power1; 1517 __le16 reserved;
1518 __le32 pa_power1; /* RF power amplifier measurement (not used) */
1364 __le32 pa_power2; 1519 __le32 pa_power2;
1365 struct agg_tx_status status; /* TX status (for aggregation status */
1366 /* of 1st frame) */
1367} __attribute__ ((packed));
1368 1520
1521 __le32 tfd_info;
1522 __le16 seq_ctl;
1523 __le16 byte_cnt;
1524 __le32 tlc_info;
1525 /*
1526 * For non-agg: frame status TX_STATUS_*
1527 * For agg: status of 1st frame, AGG_TX_STATE_*; other frame status
1528 * fields follow this one, up to frame_count.
1529 * Bit fields:
1530 * 11- 0: AGG_TX_STATE_* status code
1531 * 15-12: Retry count for 1st frame in aggregation (retries
1532 * occur if tx failed for this frame when it was a
1533 * member of a previous aggregation block). If rate
1534 * scaling is used, retry count indicates the rate
1535 * table entry used for all frames in the new agg.
1536 * 31-16: Sequence # for this frame's Tx cmd (not SSN!)
1537 */
1538 struct agg_tx_status status; /* TX status (in aggregation -
1539 * status of 1st frame) */
1540} __attribute__ ((packed));
1369/* 1541/*
1370 * REPLY_COMPRESSED_BA = 0xc5 (response only, not a command) 1542 * REPLY_COMPRESSED_BA = 0xc5 (response only, not a command)
1371 * 1543 *
1372 * Reports Block-Acknowledge from recipient station 1544 * Reports Block-Acknowledge from recipient station
1373 */ 1545 */
1374struct iwl4965_compressed_ba_resp { 1546struct iwl_compressed_ba_resp {
1375 __le32 sta_addr_lo32; 1547 __le32 sta_addr_lo32;
1376 __le16 sta_addr_hi16; 1548 __le16 sta_addr_hi16;
1377 __le16 reserved; 1549 __le16 reserved;
@@ -1853,6 +2025,7 @@ struct iwl4965_spectrum_notification {
1853#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK __constant_cpu_to_le16(1 << 0) 2025#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK __constant_cpu_to_le16(1 << 0)
1854#define IWL_POWER_SLEEP_OVER_DTIM_MSK __constant_cpu_to_le16(1 << 2) 2026#define IWL_POWER_SLEEP_OVER_DTIM_MSK __constant_cpu_to_le16(1 << 2)
1855#define IWL_POWER_PCI_PM_MSK __constant_cpu_to_le16(1 << 3) 2027#define IWL_POWER_PCI_PM_MSK __constant_cpu_to_le16(1 << 3)
2028#define IWL_POWER_FAST_PD __constant_cpu_to_le16(1 << 4)
1856 2029
1857struct iwl4965_powertable_cmd { 2030struct iwl4965_powertable_cmd {
1858 __le16 flags; 2031 __le16 flags;
@@ -1914,7 +2087,7 @@ struct iwl4965_card_state_notif {
1914#define RF_CARD_DISABLED 0x04 2087#define RF_CARD_DISABLED 0x04
1915#define RXON_CARD_DISABLED 0x10 2088#define RXON_CARD_DISABLED 0x10
1916 2089
1917struct iwl4965_ct_kill_config { 2090struct iwl_ct_kill_config {
1918 __le32 reserved; 2091 __le32 reserved;
1919 __le32 critical_temperature_M; 2092 __le32 critical_temperature_M;
1920 __le32 critical_temperature_R; 2093 __le32 critical_temperature_R;
@@ -1926,8 +2099,11 @@ struct iwl4965_ct_kill_config {
1926 * 2099 *
1927 *****************************************************************************/ 2100 *****************************************************************************/
1928 2101
2102#define SCAN_CHANNEL_TYPE_PASSIVE __constant_cpu_to_le32(0)
2103#define SCAN_CHANNEL_TYPE_ACTIVE __constant_cpu_to_le32(1)
2104
1929/** 2105/**
1930 * struct iwl4965_scan_channel - entry in REPLY_SCAN_CMD channel table 2106 * struct iwl_scan_channel - entry in REPLY_SCAN_CMD channel table
1931 * 2107 *
1932 * One for each channel in the scan list. 2108 * One for each channel in the scan list.
1933 * Each channel can independently select: 2109 * Each channel can independently select:
@@ -1937,7 +2113,7 @@ struct iwl4965_ct_kill_config {
1937 * quiet_plcp_th, good_CRC_th) 2113 * quiet_plcp_th, good_CRC_th)
1938 * 2114 *
1939 * To avoid uCode errors, make sure the following are true (see comments 2115 * To avoid uCode errors, make sure the following are true (see comments
1940 * under struct iwl4965_scan_cmd about max_out_time and quiet_time): 2116 * under struct iwl_scan_cmd about max_out_time and quiet_time):
1941 * 1) If using passive_dwell (i.e. passive_dwell != 0): 2117 * 1) If using passive_dwell (i.e. passive_dwell != 0):
1942 * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0) 2118 * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0)
1943 * 2) quiet_time <= active_dwell 2119 * 2) quiet_time <= active_dwell
@@ -1945,37 +2121,38 @@ struct iwl4965_ct_kill_config {
1945 * passive_dwell < max_out_time 2121 * passive_dwell < max_out_time
1946 * active_dwell < max_out_time 2122 * active_dwell < max_out_time
1947 */ 2123 */
1948struct iwl4965_scan_channel { 2124struct iwl_scan_channel {
1949 /* 2125 /*
1950 * type is defined as: 2126 * type is defined as:
1951 * 0:0 1 = active, 0 = passive 2127 * 0:0 1 = active, 0 = passive
1952 * 1:4 SSID direct bit map; if a bit is set, then corresponding 2128 * 1:20 SSID direct bit map; if a bit is set, then corresponding
1953 * SSID IE is transmitted in probe request. 2129 * SSID IE is transmitted in probe request.
1954 * 5:7 reserved 2130 * 21:31 reserved
1955 */ 2131 */
1956 u8 type; 2132 __le32 type;
1957 u8 channel; /* band is selected by iwl4965_scan_cmd "flags" field */ 2133 __le16 channel; /* band is selected by iwl_scan_cmd "flags" field */
1958 struct iwl4965_tx_power tpc; 2134 u8 tx_gain; /* gain for analog radio */
2135 u8 dsp_atten; /* gain for DSP */
1959 __le16 active_dwell; /* in 1024-uSec TU (time units), typ 5-50 */ 2136 __le16 active_dwell; /* in 1024-uSec TU (time units), typ 5-50 */
1960 __le16 passive_dwell; /* in 1024-uSec TU (time units), typ 20-500 */ 2137 __le16 passive_dwell; /* in 1024-uSec TU (time units), typ 20-500 */
1961} __attribute__ ((packed)); 2138} __attribute__ ((packed));
1962 2139
1963/** 2140/**
1964 * struct iwl4965_ssid_ie - directed scan network information element 2141 * struct iwl_ssid_ie - directed scan network information element
1965 * 2142 *
1966 * Up to 4 of these may appear in REPLY_SCAN_CMD, selected by "type" field 2143 * Up to 4 of these may appear in REPLY_SCAN_CMD, selected by "type" field
1967 * in struct iwl4965_scan_channel; each channel may select different ssids from 2144 * in struct iwl4965_scan_channel; each channel may select different ssids from
1968 * among the 4 entries. SSID IEs get transmitted in reverse order of entry. 2145 * among the 4 entries. SSID IEs get transmitted in reverse order of entry.
1969 */ 2146 */
1970struct iwl4965_ssid_ie { 2147struct iwl_ssid_ie {
1971 u8 id; 2148 u8 id;
1972 u8 len; 2149 u8 len;
1973 u8 ssid[32]; 2150 u8 ssid[32];
1974} __attribute__ ((packed)); 2151} __attribute__ ((packed));
1975 2152
1976#define PROBE_OPTION_MAX 0x4 2153#define PROBE_OPTION_MAX 0x14
1977#define TX_CMD_LIFE_TIME_INFINITE __constant_cpu_to_le32(0xFFFFFFFF) 2154#define TX_CMD_LIFE_TIME_INFINITE __constant_cpu_to_le32(0xFFFFFFFF)
1978#define IWL_GOOD_CRC_TH __constant_cpu_to_le16(1) 2155#define IWL_GOOD_CRC_TH __constant_cpu_to_le16(1)
1979#define IWL_MAX_SCAN_SIZE 1024 2156#define IWL_MAX_SCAN_SIZE 1024
1980 2157
1981/* 2158/*
@@ -2028,9 +2205,9 @@ struct iwl4965_ssid_ie {
2028 * Driver must use separate scan commands for 2.4 vs. 5 GHz bands. 2205 * Driver must use separate scan commands for 2.4 vs. 5 GHz bands.
2029 * 2206 *
2030 * To avoid uCode errors, see timing restrictions described under 2207 * To avoid uCode errors, see timing restrictions described under
2031 * struct iwl4965_scan_channel. 2208 * struct iwl_scan_channel.
2032 */ 2209 */
2033struct iwl4965_scan_cmd { 2210struct iwl_scan_cmd {
2034 __le16 len; 2211 __le16 len;
2035 u8 reserved0; 2212 u8 reserved0;
2036 u8 channel_count; /* # channels in channel list */ 2213 u8 channel_count; /* # channels in channel list */
@@ -2051,10 +2228,10 @@ struct iwl4965_scan_cmd {
2051 2228
2052 /* For active scans (set to all-0s for passive scans). 2229 /* For active scans (set to all-0s for passive scans).
2053 * Does not include payload. Must specify Tx rate; no rate scaling. */ 2230 * Does not include payload. Must specify Tx rate; no rate scaling. */
2054 struct iwl4965_tx_cmd tx_cmd; 2231 struct iwl_tx_cmd tx_cmd;
2055 2232
2056 /* For directed active scans (set to all-0s otherwise) */ 2233 /* For directed active scans (set to all-0s otherwise) */
2057 struct iwl4965_ssid_ie direct_scan[PROBE_OPTION_MAX]; 2234 struct iwl_ssid_ie direct_scan[PROBE_OPTION_MAX];
2058 2235
2059 /* 2236 /*
2060 * Probe request frame, followed by channel list. 2237 * Probe request frame, followed by channel list.
@@ -2082,14 +2259,14 @@ struct iwl4965_scan_cmd {
2082/* 2259/*
2083 * REPLY_SCAN_CMD = 0x80 (response) 2260 * REPLY_SCAN_CMD = 0x80 (response)
2084 */ 2261 */
2085struct iwl4965_scanreq_notification { 2262struct iwl_scanreq_notification {
2086 __le32 status; /* 1: okay, 2: cannot fulfill request */ 2263 __le32 status; /* 1: okay, 2: cannot fulfill request */
2087} __attribute__ ((packed)); 2264} __attribute__ ((packed));
2088 2265
2089/* 2266/*
2090 * SCAN_START_NOTIFICATION = 0x82 (notification only, not a command) 2267 * SCAN_START_NOTIFICATION = 0x82 (notification only, not a command)
2091 */ 2268 */
2092struct iwl4965_scanstart_notification { 2269struct iwl_scanstart_notification {
2093 __le32 tsf_low; 2270 __le32 tsf_low;
2094 __le32 tsf_high; 2271 __le32 tsf_high;
2095 __le32 beacon_timer; 2272 __le32 beacon_timer;
@@ -2106,7 +2283,7 @@ struct iwl4965_scanstart_notification {
2106/* 2283/*
2107 * SCAN_RESULTS_NOTIFICATION = 0x83 (notification only, not a command) 2284 * SCAN_RESULTS_NOTIFICATION = 0x83 (notification only, not a command)
2108 */ 2285 */
2109struct iwl4965_scanresults_notification { 2286struct iwl_scanresults_notification {
2110 u8 channel; 2287 u8 channel;
2111 u8 band; 2288 u8 band;
2112 u8 reserved[2]; 2289 u8 reserved[2];
@@ -2118,7 +2295,7 @@ struct iwl4965_scanresults_notification {
2118/* 2295/*
2119 * SCAN_COMPLETE_NOTIFICATION = 0x84 (notification only, not a command) 2296 * SCAN_COMPLETE_NOTIFICATION = 0x84 (notification only, not a command)
2120 */ 2297 */
2121struct iwl4965_scancomplete_notification { 2298struct iwl_scancomplete_notification {
2122 u8 scanned_channels; 2299 u8 scanned_channels;
2123 u8 status; 2300 u8 status;
2124 u8 reserved; 2301 u8 reserved;
@@ -2148,7 +2325,7 @@ struct iwl4965_beacon_notif {
2148 * REPLY_TX_BEACON = 0x91 (command, has simple generic response) 2325 * REPLY_TX_BEACON = 0x91 (command, has simple generic response)
2149 */ 2326 */
2150struct iwl4965_tx_beacon_cmd { 2327struct iwl4965_tx_beacon_cmd {
2151 struct iwl4965_tx_cmd tx; 2328 struct iwl_tx_cmd tx;
2152 __le16 tim_idx; 2329 __le16 tim_idx;
2153 u8 tim_size; 2330 u8 tim_size;
2154 u8 reserved1; 2331 u8 reserved1;
@@ -2339,7 +2516,7 @@ struct statistics_general {
2339 */ 2516 */
2340#define IWL_STATS_CONF_CLEAR_STATS __constant_cpu_to_le32(0x1) /* see above */ 2517#define IWL_STATS_CONF_CLEAR_STATS __constant_cpu_to_le32(0x1) /* see above */
2341#define IWL_STATS_CONF_DISABLE_NOTIF __constant_cpu_to_le32(0x2)/* see above */ 2518#define IWL_STATS_CONF_DISABLE_NOTIF __constant_cpu_to_le32(0x2)/* see above */
2342struct iwl4965_statistics_cmd { 2519struct iwl_statistics_cmd {
2343 __le32 configuration_flags; /* IWL_STATS_CONF_* */ 2520 __le32 configuration_flags; /* IWL_STATS_CONF_* */
2344} __attribute__ ((packed)); 2521} __attribute__ ((packed));
2345 2522
@@ -2360,7 +2537,7 @@ struct iwl4965_statistics_cmd {
2360 */ 2537 */
2361#define STATISTICS_REPLY_FLG_BAND_24G_MSK __constant_cpu_to_le32(0x2) 2538#define STATISTICS_REPLY_FLG_BAND_24G_MSK __constant_cpu_to_le32(0x2)
2362#define STATISTICS_REPLY_FLG_FAT_MODE_MSK __constant_cpu_to_le32(0x8) 2539#define STATISTICS_REPLY_FLG_FAT_MODE_MSK __constant_cpu_to_le32(0x8)
2363struct iwl4965_notif_statistics { 2540struct iwl_notif_statistics {
2364 __le32 flag; 2541 __le32 flag;
2365 struct statistics_rx rx; 2542 struct statistics_rx rx;
2366 struct statistics_tx tx; 2543 struct statistics_tx tx;
@@ -2559,7 +2736,7 @@ struct iwl4965_missed_beacon_notif {
2559 */ 2736 */
2560 2737
2561/* 2738/*
2562 * Table entries in SENSITIVITY_CMD (struct iwl4965_sensitivity_cmd) 2739 * Table entries in SENSITIVITY_CMD (struct iwl_sensitivity_cmd)
2563 */ 2740 */
2564#define HD_TABLE_SIZE (11) /* number of entries */ 2741#define HD_TABLE_SIZE (11) /* number of entries */
2565#define HD_MIN_ENERGY_CCK_DET_INDEX (0) /* table indexes */ 2742#define HD_MIN_ENERGY_CCK_DET_INDEX (0) /* table indexes */
@@ -2574,18 +2751,18 @@ struct iwl4965_missed_beacon_notif {
2574#define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9) 2751#define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9)
2575#define HD_OFDM_ENERGY_TH_IN_INDEX (10) 2752#define HD_OFDM_ENERGY_TH_IN_INDEX (10)
2576 2753
2577/* Control field in struct iwl4965_sensitivity_cmd */ 2754/* Control field in struct iwl_sensitivity_cmd */
2578#define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE __constant_cpu_to_le16(0) 2755#define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE __constant_cpu_to_le16(0)
2579#define SENSITIVITY_CMD_CONTROL_WORK_TABLE __constant_cpu_to_le16(1) 2756#define SENSITIVITY_CMD_CONTROL_WORK_TABLE __constant_cpu_to_le16(1)
2580 2757
2581/** 2758/**
2582 * struct iwl4965_sensitivity_cmd 2759 * struct iwl_sensitivity_cmd
2583 * @control: (1) updates working table, (0) updates default table 2760 * @control: (1) updates working table, (0) updates default table
2584 * @table: energy threshold values, use HD_* as index into table 2761 * @table: energy threshold values, use HD_* as index into table
2585 * 2762 *
2586 * Always use "1" in "control" to update uCode's working table and DSP. 2763 * Always use "1" in "control" to update uCode's working table and DSP.
2587 */ 2764 */
2588struct iwl4965_sensitivity_cmd { 2765struct iwl_sensitivity_cmd {
2589 __le16 control; /* always use "1" */ 2766 __le16 control; /* always use "1" */
2590 __le16 table[HD_TABLE_SIZE]; /* use HD_* as index */ 2767 __le16 table[HD_TABLE_SIZE]; /* use HD_* as index */
2591} __attribute__ ((packed)); 2768} __attribute__ ((packed));
@@ -2659,6 +2836,86 @@ struct iwl4965_calibration_cmd {
2659 u8 reserved1; 2836 u8 reserved1;
2660} __attribute__ ((packed)); 2837} __attribute__ ((packed));
2661 2838
2839/* Phy calibration command for 5000 series */
2840
2841enum {
2842 IWL5000_PHY_CALIBRATE_DC_CMD = 8,
2843 IWL5000_PHY_CALIBRATE_LO_CMD = 9,
2844 IWL5000_PHY_CALIBRATE_RX_BB_CMD = 10,
2845 IWL5000_PHY_CALIBRATE_TX_IQ_CMD = 11,
2846 IWL5000_PHY_CALIBRATE_RX_IQ_CMD = 12,
2847 IWL5000_PHY_CALIBRATION_NOISE_CMD = 13,
2848 IWL5000_PHY_CALIBRATE_AGC_TABLE_CMD = 14,
2849 IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD = 15,
2850 IWL5000_PHY_CALIBRATE_BASE_BAND_CMD = 16,
2851 IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD = 17,
2852 IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD = 18,
2853 IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD = 19,
2854};
2855
2856enum {
2857 CALIBRATION_CFG_CMD = 0x65,
2858 CALIBRATION_RES_NOTIFICATION = 0x66,
2859 CALIBRATION_COMPLETE_NOTIFICATION = 0x67
2860};
2861
2862struct iwl_cal_crystal_freq_cmd {
2863 u8 cap_pin1;
2864 u8 cap_pin2;
2865} __attribute__ ((packed));
2866
2867struct iwl5000_calibration {
2868 u8 op_code;
2869 u8 first_group;
2870 u8 num_groups;
2871 u8 all_data_valid;
2872 struct iwl_cal_crystal_freq_cmd data;
2873} __attribute__ ((packed));
2874
2875#define IWL_CALIB_INIT_CFG_ALL __constant_cpu_to_le32(0xffffffff)
2876
2877struct iwl_calib_cfg_elmnt_s {
2878 __le32 is_enable;
2879 __le32 start;
2880 __le32 send_res;
2881 __le32 apply_res;
2882 __le32 reserved;
2883} __attribute__ ((packed));
2884
2885struct iwl_calib_cfg_status_s {
2886 struct iwl_calib_cfg_elmnt_s once;
2887 struct iwl_calib_cfg_elmnt_s perd;
2888 __le32 flags;
2889} __attribute__ ((packed));
2890
2891struct iwl5000_calib_cfg_cmd {
2892 struct iwl_calib_cfg_status_s ucd_calib_cfg;
2893 struct iwl_calib_cfg_status_s drv_calib_cfg;
2894 __le32 reserved1;
2895} __attribute__ ((packed));
2896
2897struct iwl5000_calib_hdr {
2898 u8 op_code;
2899 u8 first_group;
2900 u8 groups_num;
2901 u8 data_valid;
2902} __attribute__ ((packed));
2903
2904struct iwl5000_calibration_chain_noise_reset_cmd {
2905 u8 op_code; /* IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD */
2906 u8 flags; /* not used */
2907 __le16 reserved;
2908} __attribute__ ((packed));
2909
2910struct iwl5000_calibration_chain_noise_gain_cmd {
2911 u8 op_code; /* IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD */
2912 u8 flags; /* not used */
2913 __le16 reserved;
2914 u8 delta_gain_1;
2915 u8 delta_gain_2;
2916 __le16 reserved1;
2917} __attribute__ ((packed));
2918
2662/****************************************************************************** 2919/******************************************************************************
2663 * (12) 2920 * (12)
2664 * Miscellaneous Commands: 2921 * Miscellaneous Commands:
@@ -2672,7 +2929,7 @@ struct iwl4965_calibration_cmd {
2672 * For each of 3 possible LEDs (Activity/Link/Tech, selected by "id" field), 2929 * For each of 3 possible LEDs (Activity/Link/Tech, selected by "id" field),
2673 * this command turns it on or off, or sets up a periodic blinking cycle. 2930 * this command turns it on or off, or sets up a periodic blinking cycle.
2674 */ 2931 */
2675struct iwl4965_led_cmd { 2932struct iwl_led_cmd {
2676 __le32 interval; /* "interval" in uSec */ 2933 __le32 interval; /* "interval" in uSec */
2677 u8 id; /* 1: Activity, 2: Link, 3: Tech */ 2934 u8 id; /* 1: Activity, 2: Link, 3: Tech */
2678 u8 off; /* # intervals off while blinking; 2935 u8 off; /* # intervals off while blinking;
@@ -2682,30 +2939,81 @@ struct iwl4965_led_cmd {
2682 u8 reserved; 2939 u8 reserved;
2683} __attribute__ ((packed)); 2940} __attribute__ ((packed));
2684 2941
2942/*
2943 * Coexistence WIFI/WIMAX Command
2944 * COEX_PRIORITY_TABLE_CMD = 0x5a
2945 *
2946 */
2947enum {
2948 COEX_UNASSOC_IDLE = 0,
2949 COEX_UNASSOC_MANUAL_SCAN = 1,
2950 COEX_UNASSOC_AUTO_SCAN = 2,
2951 COEX_CALIBRATION = 3,
2952 COEX_PERIODIC_CALIBRATION = 4,
2953 COEX_CONNECTION_ESTAB = 5,
2954 COEX_ASSOCIATED_IDLE = 6,
2955 COEX_ASSOC_MANUAL_SCAN = 7,
2956 COEX_ASSOC_AUTO_SCAN = 8,
2957 COEX_ASSOC_ACTIVE_LEVEL = 9,
2958 COEX_RF_ON = 10,
2959 COEX_RF_OFF = 11,
2960 COEX_STAND_ALONE_DEBUG = 12,
2961 COEX_IPAN_ASSOC_LEVEL = 13,
2962 COEX_RSRVD1 = 14,
2963 COEX_RSRVD2 = 15,
2964 COEX_NUM_OF_EVENTS = 16
2965};
2966
2967struct iwl_wimax_coex_event_entry {
2968 u8 request_prio;
2969 u8 win_medium_prio;
2970 u8 reserved;
2971 u8 flags;
2972} __attribute__ ((packed));
2973
2974/* COEX flag masks */
2975
2976/* Staion table is valid */
2977#define COEX_FLAGS_STA_TABLE_VALID_MSK (0x1)
2978/* UnMask wakeup src at unassociated sleep */
2979#define COEX_FLAGS_UNASSOC_WA_UNMASK_MSK (0x4)
2980/* UnMask wakeup src at associated sleep */
2981#define COEX_FLAGS_ASSOC_WA_UNMASK_MSK (0x8)
2982/* Enable CoEx feature. */
2983#define COEX_FLAGS_COEX_ENABLE_MSK (0x80)
2984
2985struct iwl_wimax_coex_cmd {
2986 u8 flags;
2987 u8 reserved[3];
2988 struct iwl_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS];
2989} __attribute__ ((packed));
2990
2685/****************************************************************************** 2991/******************************************************************************
2686 * (13) 2992 * (13)
2687 * Union of all expected notifications/responses: 2993 * Union of all expected notifications/responses:
2688 * 2994 *
2689 *****************************************************************************/ 2995 *****************************************************************************/
2690 2996
2691struct iwl4965_rx_packet { 2997struct iwl_rx_packet {
2692 __le32 len; 2998 __le32 len;
2693 struct iwl_cmd_header hdr; 2999 struct iwl_cmd_header hdr;
2694 union { 3000 union {
2695 struct iwl4965_alive_resp alive_frame; 3001 struct iwl_alive_resp alive_frame;
2696 struct iwl4965_rx_frame rx_frame; 3002 struct iwl4965_rx_frame rx_frame;
2697 struct iwl4965_tx_resp tx_resp; 3003 struct iwl4965_tx_resp tx_resp;
2698 struct iwl4965_spectrum_notification spectrum_notif; 3004 struct iwl4965_spectrum_notification spectrum_notif;
2699 struct iwl4965_csa_notification csa_notif; 3005 struct iwl4965_csa_notification csa_notif;
2700 struct iwl4965_error_resp err_resp; 3006 struct iwl_error_resp err_resp;
2701 struct iwl4965_card_state_notif card_state_notif; 3007 struct iwl4965_card_state_notif card_state_notif;
2702 struct iwl4965_beacon_notif beacon_status; 3008 struct iwl4965_beacon_notif beacon_status;
2703 struct iwl4965_add_sta_resp add_sta; 3009 struct iwl_add_sta_resp add_sta;
3010 struct iwl_rem_sta_resp rem_sta;
2704 struct iwl4965_sleep_notification sleep_notif; 3011 struct iwl4965_sleep_notification sleep_notif;
2705 struct iwl4965_spectrum_resp spectrum; 3012 struct iwl4965_spectrum_resp spectrum;
2706 struct iwl4965_notif_statistics stats; 3013 struct iwl_notif_statistics stats;
2707 struct iwl4965_compressed_ba_resp compressed_ba; 3014 struct iwl_compressed_ba_resp compressed_ba;
2708 struct iwl4965_missed_beacon_notif missed_beacon; 3015 struct iwl4965_missed_beacon_notif missed_beacon;
3016 struct iwl5000_calibration calib;
2709 __le32 status; 3017 __le32 status;
2710 u8 raw[0]; 3018 u8 raw[0];
2711 } u; 3019 } u;
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c
index 2dfd982d7d1f..a44188bf4459 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.c
+++ b/drivers/net/wireless/iwlwifi/iwl-core.c
@@ -34,9 +34,11 @@
34struct iwl_priv; /* FIXME: remove */ 34struct iwl_priv; /* FIXME: remove */
35#include "iwl-debug.h" 35#include "iwl-debug.h"
36#include "iwl-eeprom.h" 36#include "iwl-eeprom.h"
37#include "iwl-4965.h" /* FIXME: remove */ 37#include "iwl-dev.h" /* FIXME: remove */
38#include "iwl-core.h" 38#include "iwl-core.h"
39#include "iwl-io.h"
39#include "iwl-rfkill.h" 40#include "iwl-rfkill.h"
41#include "iwl-power.h"
40 42
41 43
42MODULE_DESCRIPTION("iwl core"); 44MODULE_DESCRIPTION("iwl core");
@@ -44,10 +46,106 @@ MODULE_VERSION(IWLWIFI_VERSION);
44MODULE_AUTHOR(DRV_COPYRIGHT); 46MODULE_AUTHOR(DRV_COPYRIGHT);
45MODULE_LICENSE("GPL"); 47MODULE_LICENSE("GPL");
46 48
47#ifdef CONFIG_IWLWIFI_DEBUG 49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
48u32 iwl_debug_level; 50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
49EXPORT_SYMBOL(iwl_debug_level); 51 IWL_RATE_SISO_##s##M_PLCP, \
50#endif 52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
62/*
63 * Parameter order:
64 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
65 *
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
68 *
69 */
70const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
71 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
75 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
83 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
84 /* FIXME:RS: ^^ should be INV (legacy) */
85};
86EXPORT_SYMBOL(iwl_rates);
87
88/**
89 * translate ucode response to mac80211 tx status control values
90 */
91void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
92 struct ieee80211_tx_info *control)
93{
94 int rate_index;
95
96 control->antenna_sel_tx =
97 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
98 if (rate_n_flags & RATE_MCS_HT_MSK)
99 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
100 if (rate_n_flags & RATE_MCS_GF_MSK)
101 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
102 if (rate_n_flags & RATE_MCS_FAT_MSK)
103 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
104 if (rate_n_flags & RATE_MCS_DUP_MSK)
105 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
106 if (rate_n_flags & RATE_MCS_SGI_MSK)
107 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
108 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
109 if (control->band == IEEE80211_BAND_5GHZ)
110 rate_index -= IWL_FIRST_OFDM_RATE;
111 control->tx_rate_idx = rate_index;
112}
113EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
114
115int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
116{
117 int idx = 0;
118
119 /* HT rate format */
120 if (rate_n_flags & RATE_MCS_HT_MSK) {
121 idx = (rate_n_flags & 0xff);
122
123 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
124 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
125
126 idx += IWL_FIRST_OFDM_RATE;
127 /* skip 9M not supported in ht*/
128 if (idx >= IWL_RATE_9M_INDEX)
129 idx += 1;
130 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
131 return idx;
132
133 /* legacy rate format, search for match in table */
134 } else {
135 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
136 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
137 return idx;
138 }
139
140 return -1;
141}
142EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
143
144
145
146const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
147EXPORT_SYMBOL(iwl_bcast_addr);
148
51 149
52/* This function both allocates and initializes hw and priv. */ 150/* This function both allocates and initializes hw and priv. */
53struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg, 151struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
@@ -72,25 +170,132 @@ out:
72} 170}
73EXPORT_SYMBOL(iwl_alloc_all); 171EXPORT_SYMBOL(iwl_alloc_all);
74 172
173void iwl_hw_detect(struct iwl_priv *priv)
174{
175 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
176 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
177 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
178}
179EXPORT_SYMBOL(iwl_hw_detect);
180
181/* Tell nic where to find the "keep warm" buffer */
182int iwl_kw_init(struct iwl_priv *priv)
183{
184 unsigned long flags;
185 int ret;
186
187 spin_lock_irqsave(&priv->lock, flags);
188 ret = iwl_grab_nic_access(priv);
189 if (ret)
190 goto out;
191
192 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
193 priv->kw.dma_addr >> 4);
194 iwl_release_nic_access(priv);
195out:
196 spin_unlock_irqrestore(&priv->lock, flags);
197 return ret;
198}
199
200int iwl_kw_alloc(struct iwl_priv *priv)
201{
202 struct pci_dev *dev = priv->pci_dev;
203 struct iwl_kw *kw = &priv->kw;
204
205 kw->size = IWL_KW_SIZE;
206 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
207 if (!kw->v_addr)
208 return -ENOMEM;
209
210 return 0;
211}
212
213/**
214 * iwl_kw_free - Free the "keep warm" buffer
215 */
216void iwl_kw_free(struct iwl_priv *priv)
217{
218 struct pci_dev *dev = priv->pci_dev;
219 struct iwl_kw *kw = &priv->kw;
220
221 if (kw->v_addr) {
222 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
223 memset(kw, 0, sizeof(*kw));
224 }
225}
226
227int iwl_hw_nic_init(struct iwl_priv *priv)
228{
229 unsigned long flags;
230 struct iwl_rx_queue *rxq = &priv->rxq;
231 int ret;
232
233 /* nic_init */
234 spin_lock_irqsave(&priv->lock, flags);
235 priv->cfg->ops->lib->apm_ops.init(priv);
236 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
237 spin_unlock_irqrestore(&priv->lock, flags);
238
239 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
240
241 priv->cfg->ops->lib->apm_ops.config(priv);
242
243 /* Allocate the RX queue, or reset if it is already allocated */
244 if (!rxq->bd) {
245 ret = iwl_rx_queue_alloc(priv);
246 if (ret) {
247 IWL_ERROR("Unable to initialize Rx queue\n");
248 return -ENOMEM;
249 }
250 } else
251 iwl_rx_queue_reset(priv, rxq);
252
253 iwl_rx_replenish(priv);
254
255 iwl_rx_init(priv, rxq);
256
257 spin_lock_irqsave(&priv->lock, flags);
258
259 rxq->need_update = 1;
260 iwl_rx_queue_update_write_ptr(priv, rxq);
261
262 spin_unlock_irqrestore(&priv->lock, flags);
263
264 /* Allocate and init all Tx and Command queues */
265 ret = iwl_txq_ctx_reset(priv);
266 if (ret)
267 return ret;
268
269 set_bit(STATUS_INIT, &priv->status);
270
271 return 0;
272}
273EXPORT_SYMBOL(iwl_hw_nic_init);
274
75/** 275/**
76 * iwlcore_clear_stations_table - Clear the driver's station table 276 * iwl_clear_stations_table - Clear the driver's station table
77 * 277 *
78 * NOTE: This does not clear or otherwise alter the device's station table. 278 * NOTE: This does not clear or otherwise alter the device's station table.
79 */ 279 */
80void iwlcore_clear_stations_table(struct iwl_priv *priv) 280void iwl_clear_stations_table(struct iwl_priv *priv)
81{ 281{
82 unsigned long flags; 282 unsigned long flags;
83 283
84 spin_lock_irqsave(&priv->sta_lock, flags); 284 spin_lock_irqsave(&priv->sta_lock, flags);
85 285
286 if (iwl_is_alive(priv) &&
287 !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
288 iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
289 IWL_ERROR("Couldn't clear the station table\n");
290
86 priv->num_stations = 0; 291 priv->num_stations = 0;
87 memset(priv->stations, 0, sizeof(priv->stations)); 292 memset(priv->stations, 0, sizeof(priv->stations));
88 293
89 spin_unlock_irqrestore(&priv->sta_lock, flags); 294 spin_unlock_irqrestore(&priv->sta_lock, flags);
90} 295}
91EXPORT_SYMBOL(iwlcore_clear_stations_table); 296EXPORT_SYMBOL(iwl_clear_stations_table);
92 297
93void iwlcore_reset_qos(struct iwl_priv *priv) 298void iwl_reset_qos(struct iwl_priv *priv)
94{ 299{
95 u16 cw_min = 15; 300 u16 cw_min = 15;
96 u16 cw_max = 1023; 301 u16 cw_max = 1023;
@@ -176,7 +381,397 @@ void iwlcore_reset_qos(struct iwl_priv *priv)
176 381
177 spin_unlock_irqrestore(&priv->lock, flags); 382 spin_unlock_irqrestore(&priv->lock, flags);
178} 383}
179EXPORT_SYMBOL(iwlcore_reset_qos); 384EXPORT_SYMBOL(iwl_reset_qos);
385
386#define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
387#define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
388static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
389 struct ieee80211_ht_info *ht_info,
390 enum ieee80211_band band)
391{
392 u16 max_bit_rate = 0;
393 u8 rx_chains_num = priv->hw_params.rx_chains_num;
394 u8 tx_chains_num = priv->hw_params.tx_chains_num;
395
396 ht_info->cap = 0;
397 memset(ht_info->supp_mcs_set, 0, 16);
398
399 ht_info->ht_supported = 1;
400
401 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
402 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
403 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
404 (IWL_MIMO_PS_NONE << 2));
405
406 max_bit_rate = MAX_BIT_RATE_20_MHZ;
407 if (priv->hw_params.fat_channel & BIT(band)) {
408 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
409 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
410 ht_info->supp_mcs_set[4] = 0x01;
411 max_bit_rate = MAX_BIT_RATE_40_MHZ;
412 }
413
414 if (priv->cfg->mod_params->amsdu_size_8K)
415 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
416
417 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
418 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
419
420 ht_info->supp_mcs_set[0] = 0xFF;
421 if (rx_chains_num >= 2)
422 ht_info->supp_mcs_set[1] = 0xFF;
423 if (rx_chains_num >= 3)
424 ht_info->supp_mcs_set[2] = 0xFF;
425
426 /* Highest supported Rx data rate */
427 max_bit_rate *= rx_chains_num;
428 ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
429 ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
430
431 /* Tx MCS capabilities */
432 ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
433 if (tx_chains_num != rx_chains_num) {
434 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
435 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
436 }
437}
438
439static void iwlcore_init_hw_rates(struct iwl_priv *priv,
440 struct ieee80211_rate *rates)
441{
442 int i;
443
444 for (i = 0; i < IWL_RATE_COUNT; i++) {
445 rates[i].bitrate = iwl_rates[i].ieee * 5;
446 rates[i].hw_value = i; /* Rate scaling will work on indexes */
447 rates[i].hw_value_short = i;
448 rates[i].flags = 0;
449 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
450 /*
451 * If CCK != 1M then set short preamble rate flag.
452 */
453 rates[i].flags |=
454 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
455 0 : IEEE80211_RATE_SHORT_PREAMBLE;
456 }
457 }
458}
459
460/**
461 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
462 */
463static int iwlcore_init_geos(struct iwl_priv *priv)
464{
465 struct iwl_channel_info *ch;
466 struct ieee80211_supported_band *sband;
467 struct ieee80211_channel *channels;
468 struct ieee80211_channel *geo_ch;
469 struct ieee80211_rate *rates;
470 int i = 0;
471
472 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
473 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
474 IWL_DEBUG_INFO("Geography modes already initialized.\n");
475 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
476 return 0;
477 }
478
479 channels = kzalloc(sizeof(struct ieee80211_channel) *
480 priv->channel_count, GFP_KERNEL);
481 if (!channels)
482 return -ENOMEM;
483
484 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
485 GFP_KERNEL);
486 if (!rates) {
487 kfree(channels);
488 return -ENOMEM;
489 }
490
491 /* 5.2GHz channels start after the 2.4GHz channels */
492 sband = &priv->bands[IEEE80211_BAND_5GHZ];
493 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
494 /* just OFDM */
495 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
496 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
497
498 if (priv->cfg->sku & IWL_SKU_N)
499 iwlcore_init_ht_hw_capab(priv, &sband->ht_info,
500 IEEE80211_BAND_5GHZ);
501
502 sband = &priv->bands[IEEE80211_BAND_2GHZ];
503 sband->channels = channels;
504 /* OFDM & CCK */
505 sband->bitrates = rates;
506 sband->n_bitrates = IWL_RATE_COUNT;
507
508 if (priv->cfg->sku & IWL_SKU_N)
509 iwlcore_init_ht_hw_capab(priv, &sband->ht_info,
510 IEEE80211_BAND_2GHZ);
511
512 priv->ieee_channels = channels;
513 priv->ieee_rates = rates;
514
515 iwlcore_init_hw_rates(priv, rates);
516
517 for (i = 0; i < priv->channel_count; i++) {
518 ch = &priv->channel_info[i];
519
520 /* FIXME: might be removed if scan is OK */
521 if (!is_channel_valid(ch))
522 continue;
523
524 if (is_channel_a_band(ch))
525 sband = &priv->bands[IEEE80211_BAND_5GHZ];
526 else
527 sband = &priv->bands[IEEE80211_BAND_2GHZ];
528
529 geo_ch = &sband->channels[sband->n_channels++];
530
531 geo_ch->center_freq =
532 ieee80211_channel_to_frequency(ch->channel);
533 geo_ch->max_power = ch->max_power_avg;
534 geo_ch->max_antenna_gain = 0xff;
535 geo_ch->hw_value = ch->channel;
536
537 if (is_channel_valid(ch)) {
538 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
539 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
540
541 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
542 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
543
544 if (ch->flags & EEPROM_CHANNEL_RADAR)
545 geo_ch->flags |= IEEE80211_CHAN_RADAR;
546
547 geo_ch->flags |= ch->fat_extension_channel;
548
549 if (ch->max_power_avg > priv->tx_power_channel_lmt)
550 priv->tx_power_channel_lmt = ch->max_power_avg;
551 } else {
552 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
553 }
554
555 /* Save flags for reg domain usage */
556 geo_ch->orig_flags = geo_ch->flags;
557
558 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
559 ch->channel, geo_ch->center_freq,
560 is_channel_a_band(ch) ? "5.2" : "2.4",
561 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
562 "restricted" : "valid",
563 geo_ch->flags);
564 }
565
566 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
567 priv->cfg->sku & IWL_SKU_A) {
568 printk(KERN_INFO DRV_NAME
569 ": Incorrectly detected BG card as ABG. Please send "
570 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
571 priv->pci_dev->device, priv->pci_dev->subsystem_device);
572 priv->cfg->sku &= ~IWL_SKU_A;
573 }
574
575 printk(KERN_INFO DRV_NAME
576 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
577 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
578 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
579
580
581 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
582
583 return 0;
584}
585
586/*
587 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
588 */
589static void iwlcore_free_geos(struct iwl_priv *priv)
590{
591 kfree(priv->ieee_channels);
592 kfree(priv->ieee_rates);
593 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
594}
595
596static u8 is_single_rx_stream(struct iwl_priv *priv)
597{
598 return !priv->current_ht_config.is_ht ||
599 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
600 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
601 priv->ps_mode == IWL_MIMO_PS_STATIC;
602}
603
604static u8 iwl_is_channel_extension(struct iwl_priv *priv,
605 enum ieee80211_band band,
606 u16 channel, u8 extension_chan_offset)
607{
608 const struct iwl_channel_info *ch_info;
609
610 ch_info = iwl_get_channel_info(priv, band, channel);
611 if (!is_channel_valid(ch_info))
612 return 0;
613
614 if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE)
615 return !(ch_info->fat_extension_channel &
616 IEEE80211_CHAN_NO_FAT_ABOVE);
617 else if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW)
618 return !(ch_info->fat_extension_channel &
619 IEEE80211_CHAN_NO_FAT_BELOW);
620
621 return 0;
622}
623
624u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
625 struct ieee80211_ht_info *sta_ht_inf)
626{
627 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
628
629 if ((!iwl_ht_conf->is_ht) ||
630 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
631 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE))
632 return 0;
633
634 if (sta_ht_inf) {
635 if ((!sta_ht_inf->ht_supported) ||
636 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
637 return 0;
638 }
639
640 return iwl_is_channel_extension(priv, priv->band,
641 iwl_ht_conf->control_channel,
642 iwl_ht_conf->extension_chan_offset);
643}
644EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
645
646void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
647{
648 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
649 u32 val;
650
651 if (!ht_info->is_ht)
652 return;
653
654 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
655 if (iwl_is_fat_tx_allowed(priv, NULL))
656 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
657 else
658 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
659 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
660
661 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
662 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
663 le16_to_cpu(rxon->channel),
664 ht_info->control_channel);
665 return;
666 }
667
668 /* Note: control channel is opposite of extension channel */
669 switch (ht_info->extension_chan_offset) {
670 case IEEE80211_HT_IE_CHA_SEC_ABOVE:
671 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
672 break;
673 case IEEE80211_HT_IE_CHA_SEC_BELOW:
674 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
675 break;
676 case IEEE80211_HT_IE_CHA_SEC_NONE:
677 default:
678 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
679 break;
680 }
681
682 val = ht_info->ht_protection;
683
684 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
685
686 iwl_set_rxon_chain(priv);
687
688 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
689 "rxon flags 0x%X operation mode :0x%X "
690 "extension channel offset 0x%x "
691 "control chan %d\n",
692 ht_info->supp_mcs_set[0],
693 ht_info->supp_mcs_set[1],
694 ht_info->supp_mcs_set[2],
695 le32_to_cpu(rxon->flags), ht_info->ht_protection,
696 ht_info->extension_chan_offset,
697 ht_info->control_channel);
698 return;
699}
700EXPORT_SYMBOL(iwl_set_rxon_ht);
701
702/*
703 * Determine how many receiver/antenna chains to use.
704 * More provides better reception via diversity. Fewer saves power.
705 * MIMO (dual stream) requires at least 2, but works better with 3.
706 * This does not determine *which* chains to use, just how many.
707 */
708static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
709 u8 *idle_state, u8 *rx_state)
710{
711 u8 is_single = is_single_rx_stream(priv);
712 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
713
714 /* # of Rx chains to use when expecting MIMO. */
715 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
716 *rx_state = 2;
717 else
718 *rx_state = 3;
719
720 /* # Rx chains when idling and maybe trying to save power */
721 switch (priv->ps_mode) {
722 case IWL_MIMO_PS_STATIC:
723 case IWL_MIMO_PS_DYNAMIC:
724 *idle_state = (is_cam) ? 2 : 1;
725 break;
726 case IWL_MIMO_PS_NONE:
727 *idle_state = (is_cam) ? *rx_state : 1;
728 break;
729 default:
730 *idle_state = 1;
731 break;
732 }
733
734 return 0;
735}
736
737/**
738 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
739 *
740 * Selects how many and which Rx receivers/antennas/chains to use.
741 * This should not be used for scan command ... it puts data in wrong place.
742 */
743void iwl_set_rxon_chain(struct iwl_priv *priv)
744{
745 u8 is_single = is_single_rx_stream(priv);
746 u8 idle_state, rx_state;
747
748 priv->staging_rxon.rx_chain = 0;
749 rx_state = idle_state = 3;
750
751 /* Tell uCode which antennas are actually connected.
752 * Before first association, we assume all antennas are connected.
753 * Just after first association, iwl_chain_noise_calibration()
754 * checks which antennas actually *are* connected. */
755 priv->staging_rxon.rx_chain |=
756 cpu_to_le16(priv->hw_params.valid_rx_ant <<
757 RXON_RX_CHAIN_VALID_POS);
758
759 /* How many receivers should we use? */
760 iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
761 priv->staging_rxon.rx_chain |=
762 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
763 priv->staging_rxon.rx_chain |=
764 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
765
766 if (!is_single && (rx_state >= 2) &&
767 !test_bit(STATUS_POWER_PMI, &priv->status))
768 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
769 else
770 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
771
772 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
773}
774EXPORT_SYMBOL(iwl_set_rxon_chain);
180 775
181/** 776/**
182 * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON 777 * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
@@ -188,7 +783,7 @@ EXPORT_SYMBOL(iwlcore_reset_qos);
188 * NOTE: Does not commit to the hardware; it sets appropriate bit fields 783 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
189 * in the staging RXON flag structure based on the phymode 784 * in the staging RXON flag structure based on the phymode
190 */ 785 */
191int iwlcore_set_rxon_channel(struct iwl_priv *priv, 786int iwl_set_rxon_channel(struct iwl_priv *priv,
192 enum ieee80211_band band, 787 enum ieee80211_band band,
193 u16 channel) 788 u16 channel)
194{ 789{
@@ -214,68 +809,185 @@ int iwlcore_set_rxon_channel(struct iwl_priv *priv,
214 809
215 return 0; 810 return 0;
216} 811}
217EXPORT_SYMBOL(iwlcore_set_rxon_channel); 812EXPORT_SYMBOL(iwl_set_rxon_channel);
218 813
219static void iwlcore_init_hw(struct iwl_priv *priv) 814int iwl_setup_mac(struct iwl_priv *priv)
220{ 815{
816 int ret;
221 struct ieee80211_hw *hw = priv->hw; 817 struct ieee80211_hw *hw = priv->hw;
222 hw->rate_control_algorithm = "iwl-4965-rs"; 818 hw->rate_control_algorithm = "iwl-4965-rs";
223 819
224 /* Tell mac80211 and its clients (e.g. Wireless Extensions) 820 /* Tell mac80211 our characteristics */
225 * the range of signal quality values that we'll provide. 821 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
226 * Negative values for level/noise indicate that we'll provide dBm. 822 IEEE80211_HW_SIGNAL_DBM |
227 * For WE, at least, non-0 values here *enable* display of values 823 IEEE80211_HW_NOISE_DBM;
228 * in app (iwconfig). */
229 hw->max_rssi = -20; /* signal level, negative indicates dBm */
230 hw->max_noise = -20; /* noise level, negative indicates dBm */
231 hw->max_signal = 100; /* link quality indication (%) */
232
233 /* Tell mac80211 our Tx characteristics */
234 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
235
236 /* Default value; 4 EDCA QOS priorities */ 824 /* Default value; 4 EDCA QOS priorities */
237 hw->queues = 4; 825 hw->queues = 4;
238#ifdef CONFIG_IWL4965_HT 826 /* queues to support 11n aggregation */
239 /* Enhanced value; more queues, to support 11n aggregation */ 827 if (priv->cfg->sku & IWL_SKU_N)
240 hw->queues = 16; 828 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
241#endif /* CONFIG_IWL4965_HT */ 829
830 hw->conf.beacon_int = 100;
831
832 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
833 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
834 &priv->bands[IEEE80211_BAND_2GHZ];
835 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
836 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
837 &priv->bands[IEEE80211_BAND_5GHZ];
838
839 ret = ieee80211_register_hw(priv->hw);
840 if (ret) {
841 IWL_ERROR("Failed to register hw (error %d)\n", ret);
842 return ret;
843 }
844 priv->mac80211_registered = 1;
845
846 return 0;
242} 847}
848EXPORT_SYMBOL(iwl_setup_mac);
243 849
244int iwl_setup(struct iwl_priv *priv) 850int iwl_set_hw_params(struct iwl_priv *priv)
245{ 851{
246 int ret = 0; 852 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
247 iwlcore_init_hw(priv); 853 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
248 ret = priv->cfg->ops->lib->init_drv(priv); 854 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
249 return ret; 855 if (priv->cfg->mod_params->amsdu_size_8K)
856 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
857 else
858 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
859 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
860
861 if (priv->cfg->mod_params->disable_11n)
862 priv->cfg->sku &= ~IWL_SKU_N;
863
864 /* Device-specific setup */
865 return priv->cfg->ops->lib->set_hw_params(priv);
250} 866}
251EXPORT_SYMBOL(iwl_setup); 867EXPORT_SYMBOL(iwl_set_hw_params);
252 868
253/* Low level driver call this function to update iwlcore with 869int iwl_init_drv(struct iwl_priv *priv)
254 * driver status.
255 */
256int iwlcore_low_level_notify(struct iwl_priv *priv,
257 enum iwlcore_card_notify notify)
258{ 870{
259 int ret; 871 int ret;
260 switch (notify) { 872
261 case IWLCORE_INIT_EVT: 873 priv->retry_rate = 1;
262 ret = iwl_rfkill_init(priv); 874 priv->ibss_beacon = NULL;
263 if (ret) 875
264 IWL_ERROR("Unable to initialize RFKILL system. " 876 spin_lock_init(&priv->lock);
265 "Ignoring error: %d\n", ret); 877 spin_lock_init(&priv->power_data.lock);
266 break; 878 spin_lock_init(&priv->sta_lock);
267 case IWLCORE_START_EVT: 879 spin_lock_init(&priv->hcmd_lock);
268 break; 880 spin_lock_init(&priv->lq_mngr.lock);
269 case IWLCORE_STOP_EVT: 881
270 break; 882 INIT_LIST_HEAD(&priv->free_frames);
271 case IWLCORE_REMOVE_EVT: 883
272 iwl_rfkill_unregister(priv); 884 mutex_init(&priv->mutex);
273 break; 885
886 /* Clear the driver's (not device's) station table */
887 iwl_clear_stations_table(priv);
888
889 priv->data_retry_limit = -1;
890 priv->ieee_channels = NULL;
891 priv->ieee_rates = NULL;
892 priv->band = IEEE80211_BAND_2GHZ;
893
894 priv->iw_mode = IEEE80211_IF_TYPE_STA;
895
896 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
897 priv->ps_mode = IWL_MIMO_PS_NONE;
898
899 /* Choose which receivers/antennas to use */
900 iwl_set_rxon_chain(priv);
901 iwl_init_scan_params(priv);
902
903 if (priv->cfg->mod_params->enable_qos)
904 priv->qos_data.qos_enable = 1;
905
906 iwl_reset_qos(priv);
907
908 priv->qos_data.qos_active = 0;
909 priv->qos_data.qos_cap.val = 0;
910
911 iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
912
913 priv->rates_mask = IWL_RATES_MASK;
914 /* If power management is turned on, default to AC mode */
915 priv->power_mode = IWL_POWER_AC;
916 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
917
918 ret = iwl_init_channel_map(priv);
919 if (ret) {
920 IWL_ERROR("initializing regulatory failed: %d\n", ret);
921 goto err;
922 }
923
924 ret = iwlcore_init_geos(priv);
925 if (ret) {
926 IWL_ERROR("initializing geos failed: %d\n", ret);
927 goto err_free_channel_map;
274 } 928 }
275 929
276 return 0; 930 return 0;
931
932err_free_channel_map:
933 iwl_free_channel_map(priv);
934err:
935 return ret;
936}
937EXPORT_SYMBOL(iwl_init_drv);
938
939void iwl_free_calib_results(struct iwl_priv *priv)
940{
941 kfree(priv->calib_results.lo_res);
942 priv->calib_results.lo_res = NULL;
943 priv->calib_results.lo_res_len = 0;
944
945 kfree(priv->calib_results.tx_iq_res);
946 priv->calib_results.tx_iq_res = NULL;
947 priv->calib_results.tx_iq_res_len = 0;
948
949 kfree(priv->calib_results.tx_iq_perd_res);
950 priv->calib_results.tx_iq_perd_res = NULL;
951 priv->calib_results.tx_iq_perd_res_len = 0;
952}
953EXPORT_SYMBOL(iwl_free_calib_results);
954
955int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
956{
957 int ret = 0;
958 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
959 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
960 priv->tx_power_user_lmt);
961 return -EINVAL;
962 }
963
964 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
965 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
966 priv->tx_power_user_lmt);
967 return -EINVAL;
968 }
969
970 if (priv->tx_power_user_lmt != tx_power)
971 force = true;
972
973 priv->tx_power_user_lmt = tx_power;
974
975 if (force && priv->cfg->ops->lib->send_tx_power)
976 ret = priv->cfg->ops->lib->send_tx_power(priv);
977
978 return ret;
979}
980EXPORT_SYMBOL(iwl_set_tx_power);
981
982
983void iwl_uninit_drv(struct iwl_priv *priv)
984{
985 iwl_free_calib_results(priv);
986 iwlcore_free_geos(priv);
987 iwl_free_channel_map(priv);
988 kfree(priv->scan);
277} 989}
278EXPORT_SYMBOL(iwlcore_low_level_notify); 990EXPORT_SYMBOL(iwl_uninit_drv);
279 991
280int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags) 992int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
281{ 993{
@@ -290,3 +1002,440 @@ int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
290} 1002}
291EXPORT_SYMBOL(iwl_send_statistics_request); 1003EXPORT_SYMBOL(iwl_send_statistics_request);
292 1004
1005/**
1006 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1007 * using sample data 100 bytes apart. If these sample points are good,
1008 * it's a pretty good bet that everything between them is good, too.
1009 */
1010static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1011{
1012 u32 val;
1013 int ret = 0;
1014 u32 errcnt = 0;
1015 u32 i;
1016
1017 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1018
1019 ret = iwl_grab_nic_access(priv);
1020 if (ret)
1021 return ret;
1022
1023 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1024 /* read data comes through single port, auto-incr addr */
1025 /* NOTE: Use the debugless read so we don't flood kernel log
1026 * if IWL_DL_IO is set */
1027 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1028 i + RTC_INST_LOWER_BOUND);
1029 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1030 if (val != le32_to_cpu(*image)) {
1031 ret = -EIO;
1032 errcnt++;
1033 if (errcnt >= 3)
1034 break;
1035 }
1036 }
1037
1038 iwl_release_nic_access(priv);
1039
1040 return ret;
1041}
1042
1043/**
1044 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1045 * looking at all data.
1046 */
1047static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1048 u32 len)
1049{
1050 u32 val;
1051 u32 save_len = len;
1052 int ret = 0;
1053 u32 errcnt;
1054
1055 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1056
1057 ret = iwl_grab_nic_access(priv);
1058 if (ret)
1059 return ret;
1060
1061 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1062
1063 errcnt = 0;
1064 for (; len > 0; len -= sizeof(u32), image++) {
1065 /* read data comes through single port, auto-incr addr */
1066 /* NOTE: Use the debugless read so we don't flood kernel log
1067 * if IWL_DL_IO is set */
1068 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1069 if (val != le32_to_cpu(*image)) {
1070 IWL_ERROR("uCode INST section is invalid at "
1071 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1072 save_len - len, val, le32_to_cpu(*image));
1073 ret = -EIO;
1074 errcnt++;
1075 if (errcnt >= 20)
1076 break;
1077 }
1078 }
1079
1080 iwl_release_nic_access(priv);
1081
1082 if (!errcnt)
1083 IWL_DEBUG_INFO
1084 ("ucode image in INSTRUCTION memory is good\n");
1085
1086 return ret;
1087}
1088
1089/**
1090 * iwl_verify_ucode - determine which instruction image is in SRAM,
1091 * and verify its contents
1092 */
1093int iwl_verify_ucode(struct iwl_priv *priv)
1094{
1095 __le32 *image;
1096 u32 len;
1097 int ret;
1098
1099 /* Try bootstrap */
1100 image = (__le32 *)priv->ucode_boot.v_addr;
1101 len = priv->ucode_boot.len;
1102 ret = iwlcore_verify_inst_sparse(priv, image, len);
1103 if (!ret) {
1104 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1105 return 0;
1106 }
1107
1108 /* Try initialize */
1109 image = (__le32 *)priv->ucode_init.v_addr;
1110 len = priv->ucode_init.len;
1111 ret = iwlcore_verify_inst_sparse(priv, image, len);
1112 if (!ret) {
1113 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1114 return 0;
1115 }
1116
1117 /* Try runtime/protocol */
1118 image = (__le32 *)priv->ucode_code.v_addr;
1119 len = priv->ucode_code.len;
1120 ret = iwlcore_verify_inst_sparse(priv, image, len);
1121 if (!ret) {
1122 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1123 return 0;
1124 }
1125
1126 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1127
1128 /* Since nothing seems to match, show first several data entries in
1129 * instruction SRAM, so maybe visual inspection will give a clue.
1130 * Selection of bootstrap image (vs. other images) is arbitrary. */
1131 image = (__le32 *)priv->ucode_boot.v_addr;
1132 len = priv->ucode_boot.len;
1133 ret = iwl_verify_inst_full(priv, image, len);
1134
1135 return ret;
1136}
1137EXPORT_SYMBOL(iwl_verify_ucode);
1138
1139
1140static const char *desc_lookup(int i)
1141{
1142 switch (i) {
1143 case 1:
1144 return "FAIL";
1145 case 2:
1146 return "BAD_PARAM";
1147 case 3:
1148 return "BAD_CHECKSUM";
1149 case 4:
1150 return "NMI_INTERRUPT";
1151 case 5:
1152 return "SYSASSERT";
1153 case 6:
1154 return "FATAL_ERROR";
1155 }
1156
1157 return "UNKNOWN";
1158}
1159
1160#define ERROR_START_OFFSET (1 * sizeof(u32))
1161#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1162
1163void iwl_dump_nic_error_log(struct iwl_priv *priv)
1164{
1165 u32 data2, line;
1166 u32 desc, time, count, base, data1;
1167 u32 blink1, blink2, ilink1, ilink2;
1168 int ret;
1169
1170 if (priv->ucode_type == UCODE_INIT)
1171 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1172 else
1173 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1174
1175 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1176 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1177 return;
1178 }
1179
1180 ret = iwl_grab_nic_access(priv);
1181 if (ret) {
1182 IWL_WARNING("Can not read from adapter at this time.\n");
1183 return;
1184 }
1185
1186 count = iwl_read_targ_mem(priv, base);
1187
1188 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1189 IWL_ERROR("Start IWL Error Log Dump:\n");
1190 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1191 }
1192
1193 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1194 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1195 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1196 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1197 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1198 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1199 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1200 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1201 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1202
1203 IWL_ERROR("Desc Time "
1204 "data1 data2 line\n");
1205 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1206 desc_lookup(desc), desc, time, data1, data2, line);
1207 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1208 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1209 ilink1, ilink2);
1210
1211 iwl_release_nic_access(priv);
1212}
1213EXPORT_SYMBOL(iwl_dump_nic_error_log);
1214
1215#define EVENT_START_OFFSET (4 * sizeof(u32))
1216
1217/**
1218 * iwl_print_event_log - Dump error event log to syslog
1219 *
1220 * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1221 */
1222void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1223 u32 num_events, u32 mode)
1224{
1225 u32 i;
1226 u32 base; /* SRAM byte address of event log header */
1227 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1228 u32 ptr; /* SRAM byte address of log data */
1229 u32 ev, time, data; /* event log data */
1230
1231 if (num_events == 0)
1232 return;
1233 if (priv->ucode_type == UCODE_INIT)
1234 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1235 else
1236 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1237
1238 if (mode == 0)
1239 event_size = 2 * sizeof(u32);
1240 else
1241 event_size = 3 * sizeof(u32);
1242
1243 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1244
1245 /* "time" is actually "data" for mode 0 (no timestamp).
1246 * place event id # at far right for easier visual parsing. */
1247 for (i = 0; i < num_events; i++) {
1248 ev = iwl_read_targ_mem(priv, ptr);
1249 ptr += sizeof(u32);
1250 time = iwl_read_targ_mem(priv, ptr);
1251 ptr += sizeof(u32);
1252 if (mode == 0) {
1253 /* data, ev */
1254 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1255 } else {
1256 data = iwl_read_targ_mem(priv, ptr);
1257 ptr += sizeof(u32);
1258 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1259 time, data, ev);
1260 }
1261 }
1262}
1263EXPORT_SYMBOL(iwl_print_event_log);
1264
1265
1266void iwl_dump_nic_event_log(struct iwl_priv *priv)
1267{
1268 int ret;
1269 u32 base; /* SRAM byte address of event log header */
1270 u32 capacity; /* event log capacity in # entries */
1271 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1272 u32 num_wraps; /* # times uCode wrapped to top of log */
1273 u32 next_entry; /* index of next entry to be written by uCode */
1274 u32 size; /* # entries that we'll print */
1275
1276 if (priv->ucode_type == UCODE_INIT)
1277 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1278 else
1279 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1280
1281 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1282 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1283 return;
1284 }
1285
1286 ret = iwl_grab_nic_access(priv);
1287 if (ret) {
1288 IWL_WARNING("Can not read from adapter at this time.\n");
1289 return;
1290 }
1291
1292 /* event log header */
1293 capacity = iwl_read_targ_mem(priv, base);
1294 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1295 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1296 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1297
1298 size = num_wraps ? capacity : next_entry;
1299
1300 /* bail out if nothing in log */
1301 if (size == 0) {
1302 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1303 iwl_release_nic_access(priv);
1304 return;
1305 }
1306
1307 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1308 size, num_wraps);
1309
1310 /* if uCode has wrapped back to top of log, start at the oldest entry,
1311 * i.e the next one that uCode would fill. */
1312 if (num_wraps)
1313 iwl_print_event_log(priv, next_entry,
1314 capacity - next_entry, mode);
1315 /* (then/else) start at top of log */
1316 iwl_print_event_log(priv, 0, next_entry, mode);
1317
1318 iwl_release_nic_access(priv);
1319}
1320EXPORT_SYMBOL(iwl_dump_nic_event_log);
1321
1322void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1323{
1324 struct iwl_ct_kill_config cmd;
1325 unsigned long flags;
1326 int ret = 0;
1327
1328 spin_lock_irqsave(&priv->lock, flags);
1329 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1330 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1331 spin_unlock_irqrestore(&priv->lock, flags);
1332
1333 cmd.critical_temperature_R =
1334 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1335
1336 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1337 sizeof(cmd), &cmd);
1338 if (ret)
1339 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1340 else
1341 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1342 "critical temperature is %d\n",
1343 cmd.critical_temperature_R);
1344}
1345EXPORT_SYMBOL(iwl_rf_kill_ct_config);
1346
1347/*
1348 * CARD_STATE_CMD
1349 *
1350 * Use: Sets the device's internal card state to enable, disable, or halt
1351 *
1352 * When in the 'enable' state the card operates as normal.
1353 * When in the 'disable' state, the card enters into a low power mode.
1354 * When in the 'halt' state, the card is shut down and must be fully
1355 * restarted to come back on.
1356 */
1357static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1358{
1359 struct iwl_host_cmd cmd = {
1360 .id = REPLY_CARD_STATE_CMD,
1361 .len = sizeof(u32),
1362 .data = &flags,
1363 .meta.flags = meta_flag,
1364 };
1365
1366 return iwl_send_cmd(priv, &cmd);
1367}
1368
1369void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1370{
1371 unsigned long flags;
1372
1373 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1374 return;
1375
1376 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1377
1378 iwl_scan_cancel(priv);
1379 /* FIXME: This is a workaround for AP */
1380 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
1381 spin_lock_irqsave(&priv->lock, flags);
1382 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1383 CSR_UCODE_SW_BIT_RFKILL);
1384 spin_unlock_irqrestore(&priv->lock, flags);
1385 /* call the host command only if no hw rf-kill set */
1386 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1387 iwl_is_ready(priv))
1388 iwl_send_card_state(priv,
1389 CARD_STATE_CMD_DISABLE, 0);
1390 set_bit(STATUS_RF_KILL_SW, &priv->status);
1391 /* make sure mac80211 stop sending Tx frame */
1392 if (priv->mac80211_registered)
1393 ieee80211_stop_queues(priv->hw);
1394 }
1395}
1396EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1397
1398int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1399{
1400 unsigned long flags;
1401
1402 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1403 return 0;
1404
1405 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1406
1407 spin_lock_irqsave(&priv->lock, flags);
1408 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1409
1410 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1411 * notification where it will clear SW rfkill status.
1412 * Setting it here would break the handler. Only if the
1413 * interface is down we can set here since we don't
1414 * receive any further notification.
1415 */
1416 if (!priv->is_open)
1417 clear_bit(STATUS_RF_KILL_SW, &priv->status);
1418 spin_unlock_irqrestore(&priv->lock, flags);
1419
1420 /* wake up ucode */
1421 msleep(10);
1422
1423 spin_lock_irqsave(&priv->lock, flags);
1424 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1425 if (!iwl_grab_nic_access(priv))
1426 iwl_release_nic_access(priv);
1427 spin_unlock_irqrestore(&priv->lock, flags);
1428
1429 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1430 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1431 "disabled by HW switch\n");
1432 return 0;
1433 }
1434
1435 /* If the driver is already loaded, it will receive
1436 * CARD_STATE_NOTIFICATION notifications and the handler will
1437 * call restart to reload the driver.
1438 */
1439 return 1;
1440}
1441EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.h b/drivers/net/wireless/iwlwifi/iwl-core.h
index 7193d97630dc..db66114f1e56 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.h
+++ b/drivers/net/wireless/iwlwifi/iwl-core.h
@@ -70,7 +70,7 @@ struct iwl_host_cmd;
70struct iwl_cmd; 70struct iwl_cmd;
71 71
72 72
73#define IWLWIFI_VERSION "1.2.26k" 73#define IWLWIFI_VERSION "1.3.27k"
74#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation" 74#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
75 75
76#define IWL_PCI_DEVICE(dev, subdev, cfg) \ 76#define IWL_PCI_DEVICE(dev, subdev, cfg) \
@@ -86,28 +86,63 @@ struct iwl_hcmd_ops {
86 int (*rxon_assoc)(struct iwl_priv *priv); 86 int (*rxon_assoc)(struct iwl_priv *priv);
87}; 87};
88struct iwl_hcmd_utils_ops { 88struct iwl_hcmd_utils_ops {
89 int (*enqueue_hcmd)(struct iwl_priv *priv, struct iwl_host_cmd *cmd); 89 u16 (*get_hcmd_size)(u8 cmd_id, u16 len);
90 u16 (*build_addsta_hcmd)(const struct iwl_addsta_cmd *cmd, u8 *data);
91 void (*gain_computation)(struct iwl_priv *priv,
92 u32 *average_noise,
93 u16 min_average_noise_antennat_i,
94 u32 min_average_noise);
95 void (*chain_noise_reset)(struct iwl_priv *priv);
96 void (*rts_tx_cmd_flag)(struct ieee80211_tx_info *info,
97 __le32 *tx_flags);
90}; 98};
91 99
92struct iwl_lib_ops { 100struct iwl_lib_ops {
93 /* iwlwifi driver (priv) init */
94 int (*init_drv)(struct iwl_priv *priv);
95 /* set hw dependant perameters */ 101 /* set hw dependant perameters */
96 int (*set_hw_params)(struct iwl_priv *priv); 102 int (*set_hw_params)(struct iwl_priv *priv);
97 103 /* ucode shared memory */
104 int (*alloc_shared_mem)(struct iwl_priv *priv);
105 void (*free_shared_mem)(struct iwl_priv *priv);
106 int (*shared_mem_rx_idx)(struct iwl_priv *priv);
107 /* Handling TX */
98 void (*txq_update_byte_cnt_tbl)(struct iwl_priv *priv, 108 void (*txq_update_byte_cnt_tbl)(struct iwl_priv *priv,
99 struct iwl4965_tx_queue *txq, 109 struct iwl_tx_queue *txq,
100 u16 byte_cnt); 110 u16 byte_cnt);
101 /* nic init */ 111 void (*txq_inval_byte_cnt_tbl)(struct iwl_priv *priv,
102 int (*hw_nic_init)(struct iwl_priv *priv); 112 struct iwl_tx_queue *txq);
113 void (*txq_set_sched)(struct iwl_priv *priv, u32 mask);
114 /* aggregations */
115 int (*txq_agg_enable)(struct iwl_priv *priv, int txq_id, int tx_fifo,
116 int sta_id, int tid, u16 ssn_idx);
117 int (*txq_agg_disable)(struct iwl_priv *priv, u16 txq_id, u16 ssn_idx,
118 u8 tx_fifo);
119 /* setup Rx handler */
120 void (*rx_handler_setup)(struct iwl_priv *priv);
121 /* setup deferred work */
122 void (*setup_deferred_work)(struct iwl_priv *priv);
123 /* cancel deferred work */
124 void (*cancel_deferred_work)(struct iwl_priv *priv);
125 /* alive notification after init uCode load */
126 void (*init_alive_start)(struct iwl_priv *priv);
103 /* alive notification */ 127 /* alive notification */
104 int (*alive_notify)(struct iwl_priv *priv); 128 int (*alive_notify)(struct iwl_priv *priv);
105 /* check validity of rtc data address */ 129 /* check validity of rtc data address */
106 int (*is_valid_rtc_data_addr)(u32 addr); 130 int (*is_valid_rtc_data_addr)(u32 addr);
107 /* 1st ucode load */ 131 /* 1st ucode load */
108 int (*load_ucode)(struct iwl_priv *priv); 132 int (*load_ucode)(struct iwl_priv *priv);
109 /* rfkill */ 133 /* power management */
110 void (*radio_kill_sw)(struct iwl_priv *priv, int disable_radio); 134 struct {
135 int (*init)(struct iwl_priv *priv);
136 int (*reset)(struct iwl_priv *priv);
137 void (*stop)(struct iwl_priv *priv);
138 void (*config)(struct iwl_priv *priv);
139 int (*set_pwr_src)(struct iwl_priv *priv, enum iwl_pwr_src src);
140 } apm_ops;
141 /* power */
142 int (*set_power)(struct iwl_priv *priv, void *cmd);
143 int (*send_tx_power) (struct iwl_priv *priv);
144 void (*update_chain_flags)(struct iwl_priv *priv);
145 void (*temperature) (struct iwl_priv *priv);
111 /* eeprom operations (as defined in iwl-eeprom.h) */ 146 /* eeprom operations (as defined in iwl-eeprom.h) */
112 struct iwl_eeprom_ops eeprom_ops; 147 struct iwl_eeprom_ops eeprom_ops;
113}; 148};
@@ -124,15 +159,19 @@ struct iwl_mod_params {
124 int debug; /* def: 0 = minimal debug log messages */ 159 int debug; /* def: 0 = minimal debug log messages */
125 int disable_hw_scan; /* def: 0 = use h/w scan */ 160 int disable_hw_scan; /* def: 0 = use h/w scan */
126 int num_of_queues; /* def: HW dependent */ 161 int num_of_queues; /* def: HW dependent */
162 int num_of_ampdu_queues;/* def: HW dependent */
127 int enable_qos; /* def: 1 = use quality of service */ 163 int enable_qos; /* def: 1 = use quality of service */
164 int disable_11n; /* def: 0 = disable 11n capabilities */
128 int amsdu_size_8K; /* def: 1 = enable 8K amsdu size */ 165 int amsdu_size_8K; /* def: 1 = enable 8K amsdu size */
129 int antenna; /* def: 0 = both antennas (use diversity) */ 166 int antenna; /* def: 0 = both antennas (use diversity) */
167 int restart_fw; /* def: 1 = restart firmware */
130}; 168};
131 169
132struct iwl_cfg { 170struct iwl_cfg {
133 const char *name; 171 const char *name;
134 const char *fw_name; 172 const char *fw_name;
135 unsigned int sku; 173 unsigned int sku;
174 int eeprom_size;
136 const struct iwl_ops *ops; 175 const struct iwl_ops *ops;
137 const struct iwl_mod_params *mod_params; 176 const struct iwl_mod_params *mod_params;
138}; 177};
@@ -143,14 +182,113 @@ struct iwl_cfg {
143 182
144struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg, 183struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
145 struct ieee80211_ops *hw_ops); 184 struct ieee80211_ops *hw_ops);
185void iwl_hw_detect(struct iwl_priv *priv);
146 186
147void iwlcore_clear_stations_table(struct iwl_priv *priv); 187void iwl_clear_stations_table(struct iwl_priv *priv);
148void iwlcore_reset_qos(struct iwl_priv *priv); 188void iwl_free_calib_results(struct iwl_priv *priv);
149int iwlcore_set_rxon_channel(struct iwl_priv *priv, 189void iwl_reset_qos(struct iwl_priv *priv);
190void iwl_set_rxon_chain(struct iwl_priv *priv);
191int iwl_set_rxon_channel(struct iwl_priv *priv,
150 enum ieee80211_band band, 192 enum ieee80211_band band,
151 u16 channel); 193 u16 channel);
194void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info);
195u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
196 struct ieee80211_ht_info *sta_ht_inf);
197int iwl_hw_nic_init(struct iwl_priv *priv);
198int iwl_setup_mac(struct iwl_priv *priv);
199int iwl_set_hw_params(struct iwl_priv *priv);
200int iwl_init_drv(struct iwl_priv *priv);
201void iwl_uninit_drv(struct iwl_priv *priv);
202/* "keep warm" functions */
203int iwl_kw_init(struct iwl_priv *priv);
204int iwl_kw_alloc(struct iwl_priv *priv);
205void iwl_kw_free(struct iwl_priv *priv);
206
207/*****************************************************
208* RX
209******************************************************/
210void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq);
211int iwl_rx_queue_alloc(struct iwl_priv *priv);
212void iwl_rx_handle(struct iwl_priv *priv);
213int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
214 struct iwl_rx_queue *q);
215void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq);
216void iwl_rx_replenish(struct iwl_priv *priv);
217int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq);
218int iwl_rx_agg_start(struct iwl_priv *priv, const u8 *addr, int tid, u16 ssn);
219int iwl_rx_agg_stop(struct iwl_priv *priv, const u8 *addr, int tid);
220/* FIXME: remove when TX is moved to iwl core */
221int iwl_rx_queue_restock(struct iwl_priv *priv);
222int iwl_rx_queue_space(const struct iwl_rx_queue *q);
223void iwl_rx_allocate(struct iwl_priv *priv);
224void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
225int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index);
226/* Handlers */
227void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
228 struct iwl_rx_mem_buffer *rxb);
229void iwl_rx_statistics(struct iwl_priv *priv,
230 struct iwl_rx_mem_buffer *rxb);
231
232/* TX helpers */
233
234/*****************************************************
235* TX
236******************************************************/
237int iwl_txq_ctx_reset(struct iwl_priv *priv);
238int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb);
239/* FIXME: remove when free Tx is fully merged into iwlcore */
240int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq);
241void iwl_hw_txq_ctx_free(struct iwl_priv *priv);
242int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *tfd,
243 dma_addr_t addr, u16 len);
244int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq);
245int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn);
246int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid);
247int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id);
248
249/*****************************************************
250 * TX power
251 ****************************************************/
252int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force);
253
254/*****************************************************
255 * RF -Kill - here and not in iwl-rfkill.h to be available when
256 * RF-kill subsystem is not compiled.
257 ****************************************************/
258void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv);
259int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv);
260
261/*******************************************************************************
262 * Rate
263 ******************************************************************************/
264
265void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
266 struct ieee80211_tx_info *info);
267int iwl_hwrate_to_plcp_idx(u32 rate_n_flags);
268
269static inline u8 iwl_hw_get_rate(__le32 rate_n_flags)
270{
271 return le32_to_cpu(rate_n_flags) & 0xFF;
272}
273static inline u32 iwl_hw_get_rate_n_flags(__le32 rate_n_flags)
274{
275 return le32_to_cpu(rate_n_flags) & 0x1FFFF;
276}
277static inline __le32 iwl_hw_set_rate_n_flags(u8 rate, u32 flags)
278{
279 return cpu_to_le32(flags|(u32)rate);
280}
152 281
153int iwl_setup(struct iwl_priv *priv); 282/*******************************************************************************
283 * Scanning
284 ******************************************************************************/
285void iwl_init_scan_params(struct iwl_priv *priv);
286int iwl_scan_cancel(struct iwl_priv *priv);
287int iwl_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms);
288const char *iwl_escape_essid(const char *essid, u8 essid_len);
289int iwl_scan_initiate(struct iwl_priv *priv);
290void iwl_setup_rx_scan_handlers(struct iwl_priv *priv);
291void iwl_setup_scan_deferred_work(struct iwl_priv *priv);
154 292
155/***************************************************** 293/*****************************************************
156 * S e n d i n g H o s t C o m m a n d s * 294 * S e n d i n g H o s t C o m m a n d s *
@@ -167,6 +305,17 @@ int iwl_send_cmd_pdu_async(struct iwl_priv *priv, u8 id, u16 len,
167 int (*callback)(struct iwl_priv *priv, 305 int (*callback)(struct iwl_priv *priv,
168 struct iwl_cmd *cmd, 306 struct iwl_cmd *cmd,
169 struct sk_buff *skb)); 307 struct sk_buff *skb));
308
309int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd);
310
311/*****************************************************
312* Error Handling Debugging
313******************************************************/
314void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
315 u32 num_events, u32 mode);
316void iwl_dump_nic_error_log(struct iwl_priv *priv);
317void iwl_dump_nic_event_log(struct iwl_priv *priv);
318
170/*************** DRIVER STATUS FUNCTIONS *****/ 319/*************** DRIVER STATUS FUNCTIONS *****/
171 320
172#define STATUS_HCMD_ACTIVE 0 /* host command in progress */ 321#define STATUS_HCMD_ACTIVE 0 /* host command in progress */
@@ -188,6 +337,7 @@ int iwl_send_cmd_pdu_async(struct iwl_priv *priv, u8 id, u16 len,
188#define STATUS_POWER_PMI 16 337#define STATUS_POWER_PMI 16
189#define STATUS_FW_ERROR 17 338#define STATUS_FW_ERROR 17
190#define STATUS_CONF_PENDING 18 339#define STATUS_CONF_PENDING 18
340#define STATUS_MODE_PENDING 19
191 341
192 342
193static inline int iwl_is_ready(struct iwl_priv *priv) 343static inline int iwl_is_ready(struct iwl_priv *priv)
@@ -209,10 +359,19 @@ static inline int iwl_is_init(struct iwl_priv *priv)
209 return test_bit(STATUS_INIT, &priv->status); 359 return test_bit(STATUS_INIT, &priv->status);
210} 360}
211 361
362static inline int iwl_is_rfkill_sw(struct iwl_priv *priv)
363{
364 return test_bit(STATUS_RF_KILL_SW, &priv->status);
365}
366
367static inline int iwl_is_rfkill_hw(struct iwl_priv *priv)
368{
369 return test_bit(STATUS_RF_KILL_HW, &priv->status);
370}
371
212static inline int iwl_is_rfkill(struct iwl_priv *priv) 372static inline int iwl_is_rfkill(struct iwl_priv *priv)
213{ 373{
214 return test_bit(STATUS_RF_KILL_HW, &priv->status) || 374 return iwl_is_rfkill_hw(priv) || iwl_is_rfkill_sw(priv);
215 test_bit(STATUS_RF_KILL_SW, &priv->status);
216} 375}
217 376
218static inline int iwl_is_ready_rf(struct iwl_priv *priv) 377static inline int iwl_is_ready_rf(struct iwl_priv *priv)
@@ -224,23 +383,27 @@ static inline int iwl_is_ready_rf(struct iwl_priv *priv)
224 return iwl_is_ready(priv); 383 return iwl_is_ready(priv);
225} 384}
226 385
227 386extern void iwl_rf_kill_ct_config(struct iwl_priv *priv);
228enum iwlcore_card_notify {
229 IWLCORE_INIT_EVT = 0,
230 IWLCORE_START_EVT = 1,
231 IWLCORE_STOP_EVT = 2,
232 IWLCORE_REMOVE_EVT = 3,
233};
234
235int iwlcore_low_level_notify(struct iwl_priv *priv,
236 enum iwlcore_card_notify notify);
237extern int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags); 387extern int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags);
238int iwl_send_lq_cmd(struct iwl_priv *priv, 388extern int iwl_verify_ucode(struct iwl_priv *priv);
239 struct iwl_link_quality_cmd *lq, u8 flags); 389extern int iwl_send_lq_cmd(struct iwl_priv *priv,
390 struct iwl_link_quality_cmd *lq, u8 flags);
391extern void iwl_rx_reply_rx(struct iwl_priv *priv,
392 struct iwl_rx_mem_buffer *rxb);
393extern void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
394 struct iwl_rx_mem_buffer *rxb);
395void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
396 struct iwl_rx_mem_buffer *rxb);
240 397
241static inline int iwl_send_rxon_assoc(struct iwl_priv *priv) 398static inline int iwl_send_rxon_assoc(struct iwl_priv *priv)
242{ 399{
243 return priv->cfg->ops->hcmd->rxon_assoc(priv); 400 return priv->cfg->ops->hcmd->rxon_assoc(priv);
244} 401}
245 402
403static inline const struct ieee80211_supported_band *iwl_get_hw_mode(
404 struct iwl_priv *priv, enum ieee80211_band band)
405{
406 return priv->hw->wiphy->bands[band];
407}
408
246#endif /* __iwl_core_h__ */ 409#endif /* __iwl_core_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h
index 12725796ea5f..545ed692d889 100644
--- a/drivers/net/wireless/iwlwifi/iwl-csr.h
+++ b/drivers/net/wireless/iwlwifi/iwl-csr.h
@@ -87,16 +87,16 @@
87/* EEPROM reads */ 87/* EEPROM reads */
88#define CSR_EEPROM_REG (CSR_BASE+0x02c) 88#define CSR_EEPROM_REG (CSR_BASE+0x02c)
89#define CSR_EEPROM_GP (CSR_BASE+0x030) 89#define CSR_EEPROM_GP (CSR_BASE+0x030)
90#define CSR_GIO_REG (CSR_BASE+0x03C)
90#define CSR_GP_UCODE (CSR_BASE+0x044) 91#define CSR_GP_UCODE (CSR_BASE+0x044)
91#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 92#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
92#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 93#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
93#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 94#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
94#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 95#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
95#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
96#define CSR_LED_REG (CSR_BASE+0x094) 96#define CSR_LED_REG (CSR_BASE+0x094)
97#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
97 98
98/* Analog phase-lock-loop configuration (3945 only) 99/* Analog phase-lock-loop configuration */
99 * Set bit 24. */
100#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 100#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
101/* 101/*
102 * Indicates hardware rev, to determine CCK backoff for txpower calculation. 102 * Indicates hardware rev, to determine CCK backoff for txpower calculation.
@@ -107,9 +107,9 @@
107 107
108/* Bits for CSR_HW_IF_CONFIG_REG */ 108/* Bits for CSR_HW_IF_CONFIG_REG */
109#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010) 109#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010)
110#define CSR49_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) 110#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
111#define CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 111#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
112#define CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 112#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
113 113
114#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100) 114#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100)
115#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200) 115#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200)
@@ -170,6 +170,10 @@
170#define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ 170#define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
171 CSR_FH_INT_BIT_TX_CHNL0) 171 CSR_FH_INT_BIT_TX_CHNL0)
172 172
173/* GPIO */
174#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
175#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
176#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
173 177
174/* RESET */ 178/* RESET */
175#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 179#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
@@ -191,6 +195,16 @@
191#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 195#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
192 196
193 197
198/* HW REV */
199#define CSR_HW_REV_TYPE_MSK (0x00000F0)
200#define CSR_HW_REV_TYPE_3945 (0x00000D0)
201#define CSR_HW_REV_TYPE_4965 (0x0000000)
202#define CSR_HW_REV_TYPE_5300 (0x0000020)
203#define CSR_HW_REV_TYPE_5350 (0x0000030)
204#define CSR_HW_REV_TYPE_5100 (0x0000050)
205#define CSR_HW_REV_TYPE_5150 (0x0000040)
206#define CSR_HW_REV_TYPE_NONE (0x00000F0)
207
194/* EEPROM REG */ 208/* EEPROM REG */
195#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 209#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
196#define CSR_EEPROM_REG_BIT_CMD (0x00000002) 210#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
@@ -200,17 +214,15 @@
200#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000) 214#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
201#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 215#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
202 216
217/* CSR GIO */
218#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
219
203/* UCODE DRV GP */ 220/* UCODE DRV GP */
204#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 221#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
205#define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 222#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
206#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 223#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
207#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 224#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
208 225
209/* GPIO */
210#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
211#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
212#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
213
214/* GI Chicken Bits */ 226/* GI Chicken Bits */
215#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 227#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
216#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 228#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
@@ -220,6 +232,10 @@
220#define CSR_LED_REG_TRUN_ON (0x78) 232#define CSR_LED_REG_TRUN_ON (0x78)
221#define CSR_LED_REG_TRUN_OFF (0x38) 233#define CSR_LED_REG_TRUN_OFF (0x38)
222 234
235/* ANA_PLL */
236#define CSR39_ANA_PLL_CFG_VAL (0x01000000)
237#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
238
223/*=== HBUS (Host-side Bus) ===*/ 239/*=== HBUS (Host-side Bus) ===*/
224#define HBUS_BASE (0x400) 240#define HBUS_BASE (0x400)
225/* 241/*
diff --git a/drivers/net/wireless/iwlwifi/iwl-debug.h b/drivers/net/wireless/iwlwifi/iwl-debug.h
index c60724c21db8..58384805a494 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debug.h
+++ b/drivers/net/wireless/iwlwifi/iwl-debug.h
@@ -30,37 +30,35 @@
30#define __iwl_debug_h__ 30#define __iwl_debug_h__
31 31
32#ifdef CONFIG_IWLWIFI_DEBUG 32#ifdef CONFIG_IWLWIFI_DEBUG
33extern u32 iwl_debug_level;
34#define IWL_DEBUG(level, fmt, args...) \ 33#define IWL_DEBUG(level, fmt, args...) \
35do { if (iwl_debug_level & (level)) \ 34do { if (priv->debug_level & (level)) \
36 printk(KERN_ERR DRV_NAME": %c %s " fmt, \ 35 dev_printk(KERN_ERR, &(priv->hw->wiphy->dev), "%c %s " fmt, \
37 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0) 36 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
38 37
39#define IWL_DEBUG_LIMIT(level, fmt, args...) \ 38#define IWL_DEBUG_LIMIT(level, fmt, args...) \
40do { if ((iwl_debug_level & (level)) && net_ratelimit()) \ 39do { if ((priv->debug_level & (level)) && net_ratelimit()) \
41 printk(KERN_ERR DRV_NAME": %c %s " fmt, \ 40 dev_printk(KERN_ERR, &(priv->hw->wiphy->dev), "%c %s " fmt, \
42 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0) 41 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
43 42
44static inline void iwl_print_hex_dump(int level, void *p, u32 len)
45{
46 if (!(iwl_debug_level & level))
47 return;
48
49 print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
50 p, len, 1);
51}
52
53#ifdef CONFIG_IWLWIFI_DEBUGFS 43#ifdef CONFIG_IWLWIFI_DEBUGFS
54struct iwl_debugfs { 44struct iwl_debugfs {
55 const char *name; 45 const char *name;
56 struct dentry *dir_drv; 46 struct dentry *dir_drv;
57 struct dentry *dir_data; 47 struct dentry *dir_data;
58 struct dir_data_files{ 48 struct dentry *dir_rf;
49 struct dir_data_files {
59 struct dentry *file_sram; 50 struct dentry *file_sram;
51 struct dentry *file_eeprom;
60 struct dentry *file_stations; 52 struct dentry *file_stations;
61 struct dentry *file_rx_statistics; 53 struct dentry *file_rx_statistics;
62 struct dentry *file_tx_statistics; 54 struct dentry *file_tx_statistics;
55 struct dentry *file_log_event;
63 } dbgfs_data_files; 56 } dbgfs_data_files;
57 struct dir_rf_files {
58 struct dentry *file_disable_sensitivity;
59 struct dentry *file_disable_chain_noise;
60 struct dentry *file_disable_tx_power;
61 } dbgfs_rf_files;
64 u32 sram_offset; 62 u32 sram_offset;
65 u32 sram_len; 63 u32 sram_len;
66}; 64};
@@ -76,9 +74,6 @@ static inline void IWL_DEBUG(int level, const char *fmt, ...)
76static inline void IWL_DEBUG_LIMIT(int level, const char *fmt, ...) 74static inline void IWL_DEBUG_LIMIT(int level, const char *fmt, ...)
77{ 75{
78} 76}
79static inline void iwl_print_hex_dump(int level, void *p, u32 len)
80{
81}
82#endif /* CONFIG_IWLWIFI_DEBUG */ 77#endif /* CONFIG_IWLWIFI_DEBUG */
83 78
84 79
diff --git a/drivers/net/wireless/iwlwifi/iwl-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
index 9a30e1df311d..ed948dc59b3d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debugfs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
@@ -34,7 +34,7 @@
34#include <net/mac80211.h> 34#include <net/mac80211.h>
35 35
36 36
37#include "iwl-4965.h" 37#include "iwl-dev.h"
38#include "iwl-debug.h" 38#include "iwl-debug.h"
39#include "iwl-core.h" 39#include "iwl-core.h"
40#include "iwl-io.h" 40#include "iwl-io.h"
@@ -55,6 +55,13 @@
55 goto err; \ 55 goto err; \
56} while (0) 56} while (0)
57 57
58#define DEBUGFS_ADD_BOOL(name, parent, ptr) do { \
59 dbgfs->dbgfs_##parent##_files.file_##name = \
60 debugfs_create_bool(#name, 0644, dbgfs->dir_##parent, ptr); \
61 if (IS_ERR(dbgfs->dbgfs_##parent##_files.file_##name)) \
62 goto err; \
63} while (0)
64
58#define DEBUGFS_REMOVE(name) do { \ 65#define DEBUGFS_REMOVE(name) do { \
59 debugfs_remove(name); \ 66 debugfs_remove(name); \
60 name = NULL; \ 67 name = NULL; \
@@ -85,6 +92,14 @@ static const struct file_operations iwl_dbgfs_##name##_ops = { \
85 .open = iwl_dbgfs_open_file_generic, \ 92 .open = iwl_dbgfs_open_file_generic, \
86}; 93};
87 94
95#define DEBUGFS_WRITE_FILE_OPS(name) \
96 DEBUGFS_WRITE_FUNC(name); \
97static const struct file_operations iwl_dbgfs_##name##_ops = { \
98 .write = iwl_dbgfs_##name##_write, \
99 .open = iwl_dbgfs_open_file_generic, \
100};
101
102
88#define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 103#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
89 DEBUGFS_READ_FUNC(name); \ 104 DEBUGFS_READ_FUNC(name); \
90 DEBUGFS_WRITE_FUNC(name); \ 105 DEBUGFS_WRITE_FUNC(name); \
@@ -206,7 +221,7 @@ static ssize_t iwl_dbgfs_stations_read(struct file *file, char __user *user_buf,
206 size_t count, loff_t *ppos) 221 size_t count, loff_t *ppos)
207{ 222{
208 struct iwl_priv *priv = (struct iwl_priv *)file->private_data; 223 struct iwl_priv *priv = (struct iwl_priv *)file->private_data;
209 struct iwl4965_station_entry *station; 224 struct iwl_station_entry *station;
210 int max_sta = priv->hw_params.max_stations; 225 int max_sta = priv->hw_params.max_stations;
211 char *buf; 226 char *buf;
212 int i, j, pos = 0; 227 int i, j, pos = 0;
@@ -240,21 +255,18 @@ static ssize_t iwl_dbgfs_stations_read(struct file *file, char __user *user_buf,
240 pos += scnprintf(buf + pos, bufsz - pos, "tid data:\n"); 255 pos += scnprintf(buf + pos, bufsz - pos, "tid data:\n");
241 pos += scnprintf(buf + pos, bufsz - pos, 256 pos += scnprintf(buf + pos, bufsz - pos,
242 "seq_num\t\ttxq_id"); 257 "seq_num\t\ttxq_id");
243#ifdef CONFIG_IWL4965_HT
244 pos += scnprintf(buf + pos, bufsz - pos, 258 pos += scnprintf(buf + pos, bufsz - pos,
245 "\tframe_count\twait_for_ba\t"); 259 "\tframe_count\twait_for_ba\t");
246 pos += scnprintf(buf + pos, bufsz - pos, 260 pos += scnprintf(buf + pos, bufsz - pos,
247 "start_idx\tbitmap0\t"); 261 "start_idx\tbitmap0\t");
248 pos += scnprintf(buf + pos, bufsz - pos, 262 pos += scnprintf(buf + pos, bufsz - pos,
249 "bitmap1\trate_n_flags"); 263 "bitmap1\trate_n_flags");
250#endif
251 pos += scnprintf(buf + pos, bufsz - pos, "\n"); 264 pos += scnprintf(buf + pos, bufsz - pos, "\n");
252 265
253 for (j = 0; j < MAX_TID_COUNT; j++) { 266 for (j = 0; j < MAX_TID_COUNT; j++) {
254 pos += scnprintf(buf + pos, bufsz - pos, 267 pos += scnprintf(buf + pos, bufsz - pos,
255 "[%d]:\t\t%u", j, 268 "[%d]:\t\t%u", j,
256 station->tid[j].seq_number); 269 station->tid[j].seq_number);
257#ifdef CONFIG_IWL4965_HT
258 pos += scnprintf(buf + pos, bufsz - pos, 270 pos += scnprintf(buf + pos, bufsz - pos,
259 "\t%u\t\t%u\t\t%u\t\t", 271 "\t%u\t\t%u\t\t%u\t\t",
260 station->tid[j].agg.txq_id, 272 station->tid[j].agg.txq_id,
@@ -265,7 +277,6 @@ static ssize_t iwl_dbgfs_stations_read(struct file *file, char __user *user_buf,
265 station->tid[j].agg.start_idx, 277 station->tid[j].agg.start_idx,
266 (unsigned long long)station->tid[j].agg.bitmap, 278 (unsigned long long)station->tid[j].agg.bitmap,
267 station->tid[j].agg.rate_n_flags); 279 station->tid[j].agg.rate_n_flags);
268#endif
269 pos += scnprintf(buf + pos, bufsz - pos, "\n"); 280 pos += scnprintf(buf + pos, bufsz - pos, "\n");
270 } 281 }
271 pos += scnprintf(buf + pos, bufsz - pos, "\n"); 282 pos += scnprintf(buf + pos, bufsz - pos, "\n");
@@ -277,8 +288,70 @@ static ssize_t iwl_dbgfs_stations_read(struct file *file, char __user *user_buf,
277 return ret; 288 return ret;
278} 289}
279 290
291static ssize_t iwl_dbgfs_eeprom_read(struct file *file,
292 char __user *user_buf,
293 size_t count,
294 loff_t *ppos)
295{
296 ssize_t ret;
297 struct iwl_priv *priv = (struct iwl_priv *)file->private_data;
298 int pos = 0, ofs = 0, buf_size = 0;
299 const u8 *ptr;
300 char *buf;
301 size_t eeprom_len = priv->cfg->eeprom_size;
302 buf_size = 4 * eeprom_len + 256;
303
304 if (eeprom_len % 16) {
305 IWL_ERROR("EEPROM size is not multiple of 16.\n");
306 return -ENODATA;
307 }
308
309 /* 4 characters for byte 0xYY */
310 buf = kzalloc(buf_size, GFP_KERNEL);
311 if (!buf) {
312 IWL_ERROR("Can not allocate Buffer\n");
313 return -ENOMEM;
314 }
315
316 ptr = priv->eeprom;
317 for (ofs = 0 ; ofs < eeprom_len ; ofs += 16) {
318 pos += scnprintf(buf + pos, buf_size - pos, "0x%.4x ", ofs);
319 hex_dump_to_buffer(ptr + ofs, 16 , 16, 2, buf + pos,
320 buf_size - pos, 0);
321 pos += strlen(buf);
322 if (buf_size - pos > 0)
323 buf[pos++] = '\n';
324 }
325
326 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
327 kfree(buf);
328 return ret;
329}
330
331static ssize_t iwl_dbgfs_log_event_write(struct file *file,
332 const char __user *user_buf,
333 size_t count, loff_t *ppos)
334{
335 struct iwl_priv *priv = file->private_data;
336 u32 event_log_flag;
337 char buf[8];
338 int buf_size;
339
340 memset(buf, 0, sizeof(buf));
341 buf_size = min(count, sizeof(buf) - 1);
342 if (copy_from_user(buf, user_buf, buf_size))
343 return -EFAULT;
344 if (sscanf(buf, "%d", &event_log_flag) != 1)
345 return -EFAULT;
346 if (event_log_flag == 1)
347 iwl_dump_nic_event_log(priv);
348
349 return count;
350}
280 351
281DEBUGFS_READ_WRITE_FILE_OPS(sram); 352DEBUGFS_READ_WRITE_FILE_OPS(sram);
353DEBUGFS_WRITE_FILE_OPS(log_event);
354DEBUGFS_READ_FILE_OPS(eeprom);
282DEBUGFS_READ_FILE_OPS(stations); 355DEBUGFS_READ_FILE_OPS(stations);
283DEBUGFS_READ_FILE_OPS(rx_statistics); 356DEBUGFS_READ_FILE_OPS(rx_statistics);
284DEBUGFS_READ_FILE_OPS(tx_statistics); 357DEBUGFS_READ_FILE_OPS(tx_statistics);
@@ -290,6 +363,7 @@ DEBUGFS_READ_FILE_OPS(tx_statistics);
290int iwl_dbgfs_register(struct iwl_priv *priv, const char *name) 363int iwl_dbgfs_register(struct iwl_priv *priv, const char *name)
291{ 364{
292 struct iwl_debugfs *dbgfs; 365 struct iwl_debugfs *dbgfs;
366 struct dentry *phyd = priv->hw->wiphy->debugfsdir;
293 367
294 dbgfs = kzalloc(sizeof(struct iwl_debugfs), GFP_KERNEL); 368 dbgfs = kzalloc(sizeof(struct iwl_debugfs), GFP_KERNEL);
295 if (!dbgfs) { 369 if (!dbgfs) {
@@ -298,17 +372,23 @@ int iwl_dbgfs_register(struct iwl_priv *priv, const char *name)
298 372
299 priv->dbgfs = dbgfs; 373 priv->dbgfs = dbgfs;
300 dbgfs->name = name; 374 dbgfs->name = name;
301 dbgfs->dir_drv = debugfs_create_dir(name, NULL); 375 dbgfs->dir_drv = debugfs_create_dir(name, phyd);
302 if (!dbgfs->dir_drv || IS_ERR(dbgfs->dir_drv)){ 376 if (!dbgfs->dir_drv || IS_ERR(dbgfs->dir_drv)){
303 goto err; 377 goto err;
304 } 378 }
305 379
306 DEBUGFS_ADD_DIR(data, dbgfs->dir_drv); 380 DEBUGFS_ADD_DIR(data, dbgfs->dir_drv);
381 DEBUGFS_ADD_DIR(rf, dbgfs->dir_drv);
382 DEBUGFS_ADD_FILE(eeprom, data);
307 DEBUGFS_ADD_FILE(sram, data); 383 DEBUGFS_ADD_FILE(sram, data);
384 DEBUGFS_ADD_FILE(log_event, data);
308 DEBUGFS_ADD_FILE(stations, data); 385 DEBUGFS_ADD_FILE(stations, data);
309 DEBUGFS_ADD_FILE(rx_statistics, data); 386 DEBUGFS_ADD_FILE(rx_statistics, data);
310 DEBUGFS_ADD_FILE(tx_statistics, data); 387 DEBUGFS_ADD_FILE(tx_statistics, data);
311 388 DEBUGFS_ADD_BOOL(disable_sensitivity, rf, &priv->disable_sens_cal);
389 DEBUGFS_ADD_BOOL(disable_chain_noise, rf,
390 &priv->disable_chain_noise_cal);
391 DEBUGFS_ADD_BOOL(disable_tx_power, rf, &priv->disable_tx_power_cal);
312 return 0; 392 return 0;
313 393
314err: 394err:
@@ -327,11 +407,17 @@ void iwl_dbgfs_unregister(struct iwl_priv *priv)
327 if (!(priv->dbgfs)) 407 if (!(priv->dbgfs))
328 return; 408 return;
329 409
410 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_eeprom);
330 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_rx_statistics); 411 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_rx_statistics);
331 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_tx_statistics); 412 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_tx_statistics);
332 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_sram); 413 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_sram);
414 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_log_event);
333 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_stations); 415 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_stations);
334 DEBUGFS_REMOVE(priv->dbgfs->dir_data); 416 DEBUGFS_REMOVE(priv->dbgfs->dir_data);
417 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_rf_files.file_disable_sensitivity);
418 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_rf_files.file_disable_chain_noise);
419 DEBUGFS_REMOVE(priv->dbgfs->dbgfs_rf_files.file_disable_tx_power);
420 DEBUGFS_REMOVE(priv->dbgfs->dir_rf);
335 DEBUGFS_REMOVE(priv->dbgfs->dir_drv); 421 DEBUGFS_REMOVE(priv->dbgfs->dir_drv);
336 kfree(priv->dbgfs); 422 kfree(priv->dbgfs);
337 priv->dbgfs = NULL; 423 priv->dbgfs = NULL;
@@ -339,3 +425,4 @@ void iwl_dbgfs_unregister(struct iwl_priv *priv)
339EXPORT_SYMBOL(iwl_dbgfs_unregister); 425EXPORT_SYMBOL(iwl_dbgfs_unregister);
340 426
341 427
428
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.h b/drivers/net/wireless/iwlwifi/iwl-dev.h
index 581b98556c86..4d789e353e3a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.h
+++ b/drivers/net/wireless/iwlwifi/iwl-dev.h
@@ -24,13 +24,13 @@
24 * 24 *
25 *****************************************************************************/ 25 *****************************************************************************/
26/* 26/*
27 * Please use this file (iwl-4965.h) for driver implementation definitions. 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
28 * Please use iwl-4965-commands.h for uCode API definitions. 28 * Please use iwl-commands.h for uCode API definitions.
29 * Please use iwl-4965-hw.h for hardware-related definitions. 29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */ 30 */
31 31
32#ifndef __iwl_4965_h__ 32#ifndef __iwl_dev_h__
33#define __iwl_4965_h__ 33#define __iwl_dev_h__
34 34
35#include <linux/pci.h> /* for struct pci_device_id */ 35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h> 36#include <linux/kernel.h>
@@ -44,16 +44,18 @@
44#include "iwl-prph.h" 44#include "iwl-prph.h"
45#include "iwl-debug.h" 45#include "iwl-debug.h"
46#include "iwl-led.h" 46#include "iwl-led.h"
47#include "iwl-power.h"
47 48
48/* configuration for the iwl4965 */ 49/* configuration for the iwl4965 */
49extern struct iwl_cfg iwl4965_agn_cfg; 50extern struct iwl_cfg iwl4965_agn_cfg;
51extern struct iwl_cfg iwl5300_agn_cfg;
52extern struct iwl_cfg iwl5100_agn_cfg;
53extern struct iwl_cfg iwl5350_agn_cfg;
54extern struct iwl_cfg iwl5100_bg_cfg;
55extern struct iwl_cfg iwl5100_abg_cfg;
50 56
51/* Change firmware file name, using "-" and incrementing number, 57/* CT-KILL constants */
52 * *only* when uCode interface or architecture changes so that it 58#define CT_KILL_THRESHOLD 110 /* in Celsius */
53 * is not compatible with earlier drivers.
54 * This number will also appear in << 8 position of 1st dword of uCode file */
55#define IWL4965_UCODE_API "-1"
56
57 59
58/* Default noise level to report when noise measurement is not available. 60/* Default noise level to report when noise measurement is not available.
59 * This may be because we're: 61 * This may be because we're:
@@ -68,12 +70,6 @@ extern struct iwl_cfg iwl4965_agn_cfg;
68 * averages within an s8's (used in some apps) range of negative values. */ 70 * averages within an s8's (used in some apps) range of negative values. */
69#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127) 71#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
70 72
71enum iwl4965_antenna {
72 IWL_ANTENNA_DIVERSITY,
73 IWL_ANTENNA_MAIN,
74 IWL_ANTENNA_AUX
75};
76
77/* 73/*
78 * RTS threshold here is total size [2347] minus 4 FCS bytes 74 * RTS threshold here is total size [2347] minus 4 FCS bytes
79 * Per spec: 75 * Per spec:
@@ -91,7 +87,7 @@ enum iwl4965_antenna {
91#define DEFAULT_SHORT_RETRY_LIMIT 7U 87#define DEFAULT_SHORT_RETRY_LIMIT 7U
92#define DEFAULT_LONG_RETRY_LIMIT 4U 88#define DEFAULT_LONG_RETRY_LIMIT 4U
93 89
94struct iwl4965_rx_mem_buffer { 90struct iwl_rx_mem_buffer {
95 dma_addr_t dma_addr; 91 dma_addr_t dma_addr;
96 struct sk_buff *skb; 92 struct sk_buff *skb;
97 struct list_head list; 93 struct list_head list;
@@ -102,7 +98,7 @@ struct iwl4965_rx_mem_buffer {
102 * 98 *
103 * Contains common data for Rx and Tx queues 99 * Contains common data for Rx and Tx queues
104 */ 100 */
105struct iwl4965_queue { 101struct iwl_queue {
106 int n_bd; /* number of BDs in this queue */ 102 int n_bd; /* number of BDs in this queue */
107 int write_ptr; /* 1-st empty entry (index) host_w*/ 103 int write_ptr; /* 1-st empty entry (index) host_w*/
108 int read_ptr; /* last used entry (index) host_r*/ 104 int read_ptr; /* last used entry (index) host_r*/
@@ -118,13 +114,12 @@ struct iwl4965_queue {
118#define MAX_NUM_OF_TBS (20) 114#define MAX_NUM_OF_TBS (20)
119 115
120/* One for each TFD */ 116/* One for each TFD */
121struct iwl4965_tx_info { 117struct iwl_tx_info {
122 struct ieee80211_tx_status status;
123 struct sk_buff *skb[MAX_NUM_OF_TBS]; 118 struct sk_buff *skb[MAX_NUM_OF_TBS];
124}; 119};
125 120
126/** 121/**
127 * struct iwl4965_tx_queue - Tx Queue for DMA 122 * struct iwl_tx_queue - Tx Queue for DMA
128 * @q: generic Rx/Tx queue descriptor 123 * @q: generic Rx/Tx queue descriptor
129 * @bd: base of circular buffer of TFDs 124 * @bd: base of circular buffer of TFDs
130 * @cmd: array of command/Tx buffers 125 * @cmd: array of command/Tx buffers
@@ -136,12 +131,12 @@ struct iwl4965_tx_info {
136 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 131 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
137 * descriptors) and required locking structures. 132 * descriptors) and required locking structures.
138 */ 133 */
139struct iwl4965_tx_queue { 134struct iwl_tx_queue {
140 struct iwl4965_queue q; 135 struct iwl_queue q;
141 struct iwl4965_tfd_frame *bd; 136 struct iwl_tfd_frame *bd;
142 struct iwl_cmd *cmd; 137 struct iwl_cmd *cmd;
143 dma_addr_t dma_addr_cmd; 138 dma_addr_t dma_addr_cmd;
144 struct iwl4965_tx_info *txb; 139 struct iwl_tx_info *txb;
145 int need_update; 140 int need_update;
146 int sched_retry; 141 int sched_retry;
147 int active; 142 int active;
@@ -158,50 +153,17 @@ struct iwl4965_channel_tgh_info {
158 s64 last_radar_time; 153 s64 last_radar_time;
159}; 154};
160 155
161/* current Tx power values to use, one for each rate for each channel.
162 * requested power is limited by:
163 * -- regulatory EEPROM limits for this channel
164 * -- hardware capabilities (clip-powers)
165 * -- spectrum management
166 * -- user preference (e.g. iwconfig)
167 * when requested power is set, base power index must also be set. */
168struct iwl4965_channel_power_info {
169 struct iwl4965_tx_power tpc; /* actual radio and DSP gain settings */
170 s8 power_table_index; /* actual (compenst'd) index into gain table */
171 s8 base_power_index; /* gain index for power at factory temp. */
172 s8 requested_power; /* power (dBm) requested for this chnl/rate */
173};
174
175/* current scan Tx power values to use, one for each scan rate for each
176 * channel. */
177struct iwl4965_scan_power_info {
178 struct iwl4965_tx_power tpc; /* actual radio and DSP gain settings */
179 s8 power_table_index; /* actual (compenst'd) index into gain table */
180 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
181};
182
183/* For fat_extension_channel */
184enum {
185 HT_IE_EXT_CHANNEL_NONE = 0,
186 HT_IE_EXT_CHANNEL_ABOVE,
187 HT_IE_EXT_CHANNEL_INVALID,
188 HT_IE_EXT_CHANNEL_BELOW,
189 HT_IE_EXT_CHANNEL_MAX
190};
191
192/* 156/*
193 * One for each channel, holds all channel setup data 157 * One for each channel, holds all channel setup data
194 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant 158 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
195 * with one another! 159 * with one another!
196 */ 160 */
197#define IWL4965_MAX_RATE (33)
198
199struct iwl_channel_info { 161struct iwl_channel_info {
200 struct iwl4965_channel_tgd_info tgd; 162 struct iwl4965_channel_tgd_info tgd;
201 struct iwl4965_channel_tgh_info tgh; 163 struct iwl4965_channel_tgh_info tgh;
202 struct iwl4965_eeprom_channel eeprom; /* EEPROM regulatory limit */ 164 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
203 struct iwl4965_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for 165 struct iwl_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for
204 * FAT channel */ 166 * FAT channel */
205 167
206 u8 channel; /* channel number */ 168 u8 channel; /* channel number */
207 u8 flags; /* flags copied from EEPROM */ 169 u8 flags; /* flags copied from EEPROM */
@@ -214,11 +176,6 @@ struct iwl_channel_info {
214 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */ 176 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
215 enum ieee80211_band band; 177 enum ieee80211_band band;
216 178
217 /* Radio/DSP gain settings for each "normal" data Tx rate.
218 * These include, in addition to RF and DSP gain, a few fields for
219 * remembering/modifying gain settings (indexes). */
220 struct iwl4965_channel_power_info power_info[IWL4965_MAX_RATE];
221
222 /* FAT channel info */ 179 /* FAT channel info */
223 s8 fat_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ 180 s8 fat_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
224 s8 fat_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */ 181 s8 fat_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */
@@ -226,9 +183,6 @@ struct iwl_channel_info {
226 s8 fat_scan_power; /* (dBm) eeprom, direct scans, any rate */ 183 s8 fat_scan_power; /* (dBm) eeprom, direct scans, any rate */
227 u8 fat_flags; /* flags copied from EEPROM */ 184 u8 fat_flags; /* flags copied from EEPROM */
228 u8 fat_extension_channel; /* HT_IE_EXT_CHANNEL_* */ 185 u8 fat_extension_channel; /* HT_IE_EXT_CHANNEL_* */
229
230 /* Radio/DSP gain settings for each scan rate, for directed scans. */
231 struct iwl4965_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
232}; 186};
233 187
234struct iwl4965_clip_group { 188struct iwl4965_clip_group {
@@ -252,29 +206,9 @@ struct iwl4965_clip_group {
252 206
253/* Power management (not Tx power) structures */ 207/* Power management (not Tx power) structures */
254 208
255struct iwl4965_power_vec_entry { 209enum iwl_pwr_src {
256 struct iwl4965_powertable_cmd cmd; 210 IWL_PWR_SRC_VMAIN,
257 u8 no_dtim; 211 IWL_PWR_SRC_VAUX,
258};
259#define IWL_POWER_RANGE_0 (0)
260#define IWL_POWER_RANGE_1 (1)
261
262#define IWL_POWER_MODE_CAM 0x00 /* Continuously Aware Mode, always on */
263#define IWL_POWER_INDEX_3 0x03
264#define IWL_POWER_INDEX_5 0x05
265#define IWL_POWER_AC 0x06
266#define IWL_POWER_BATTERY 0x07
267#define IWL_POWER_LIMIT 0x07
268#define IWL_POWER_MASK 0x0F
269#define IWL_POWER_ENABLED 0x10
270#define IWL_POWER_LEVEL(x) ((x) & IWL_POWER_MASK)
271
272struct iwl4965_power_mgr {
273 spinlock_t lock;
274 struct iwl4965_power_vec_entry pwr_range_0[IWL_POWER_AC];
275 struct iwl4965_power_vec_entry pwr_range_1[IWL_POWER_AC];
276 u8 active_index;
277 u32 dtim_val;
278}; 212};
279 213
280#define IEEE80211_DATA_LEN 2304 214#define IEEE80211_DATA_LEN 2304
@@ -282,7 +216,7 @@ struct iwl4965_power_mgr {
282#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) 216#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
283#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) 217#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
284 218
285struct iwl4965_frame { 219struct iwl_frame {
286 union { 220 union {
287 struct ieee80211_hdr frame; 221 struct ieee80211_hdr frame;
288 struct iwl4965_tx_beacon_cmd beacon; 222 struct iwl4965_tx_beacon_cmd beacon;
@@ -328,6 +262,8 @@ struct iwl_cmd_meta {
328 262
329} __attribute__ ((packed)); 263} __attribute__ ((packed));
330 264
265#define IWL_CMD_MAX_PAYLOAD 320
266
331/** 267/**
332 * struct iwl_cmd 268 * struct iwl_cmd
333 * 269 *
@@ -339,8 +275,8 @@ struct iwl_cmd {
339 struct iwl_cmd_meta meta; /* driver data */ 275 struct iwl_cmd_meta meta; /* driver data */
340 struct iwl_cmd_header hdr; /* uCode API */ 276 struct iwl_cmd_header hdr; /* uCode API */
341 union { 277 union {
342 struct iwl4965_addsta_cmd addsta; 278 struct iwl_addsta_cmd addsta;
343 struct iwl4965_led_cmd led; 279 struct iwl_led_cmd led;
344 u32 flags; 280 u32 flags;
345 u8 val8; 281 u8 val8;
346 u16 val16; 282 u16 val16;
@@ -348,12 +284,13 @@ struct iwl_cmd {
348 struct iwl4965_bt_cmd bt; 284 struct iwl4965_bt_cmd bt;
349 struct iwl4965_rxon_time_cmd rxon_time; 285 struct iwl4965_rxon_time_cmd rxon_time;
350 struct iwl4965_powertable_cmd powertable; 286 struct iwl4965_powertable_cmd powertable;
351 struct iwl4965_qosparam_cmd qosparam; 287 struct iwl_qosparam_cmd qosparam;
352 struct iwl4965_tx_cmd tx; 288 struct iwl_tx_cmd tx;
353 struct iwl4965_tx_beacon_cmd tx_beacon; 289 struct iwl4965_tx_beacon_cmd tx_beacon;
354 struct iwl4965_rxon_assoc_cmd rxon_assoc; 290 struct iwl4965_rxon_assoc_cmd rxon_assoc;
291 struct iwl_rem_sta_cmd rm_sta;
355 u8 *indirect; 292 u8 *indirect;
356 u8 payload[360]; 293 u8 payload[IWL_CMD_MAX_PAYLOAD];
357 } __attribute__ ((packed)) cmd; 294 } __attribute__ ((packed)) cmd;
358} __attribute__ ((packed)); 295} __attribute__ ((packed));
359 296
@@ -378,7 +315,7 @@ struct iwl_host_cmd {
378#define SUP_RATE_11G_MAX_NUM_CHANNELS 12 315#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
379 316
380/** 317/**
381 * struct iwl4965_rx_queue - Rx queue 318 * struct iwl_rx_queue - Rx queue
382 * @processed: Internal index to last handled Rx packet 319 * @processed: Internal index to last handled Rx packet
383 * @read: Shared index to newest available Rx buffer 320 * @read: Shared index to newest available Rx buffer
384 * @write: Shared index to oldest written Rx packet 321 * @write: Shared index to oldest written Rx packet
@@ -387,13 +324,13 @@ struct iwl_host_cmd {
387 * @rx_used: List of Rx buffers with no SKB 324 * @rx_used: List of Rx buffers with no SKB
388 * @need_update: flag to indicate we need to update read/write index 325 * @need_update: flag to indicate we need to update read/write index
389 * 326 *
390 * NOTE: rx_free and rx_used are used as a FIFO for iwl4965_rx_mem_buffers 327 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
391 */ 328 */
392struct iwl4965_rx_queue { 329struct iwl_rx_queue {
393 __le32 *bd; 330 __le32 *bd;
394 dma_addr_t dma_addr; 331 dma_addr_t dma_addr;
395 struct iwl4965_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; 332 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
396 struct iwl4965_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 333 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
397 u32 processed; 334 u32 processed;
398 u32 read; 335 u32 read;
399 u32 write; 336 u32 write;
@@ -419,9 +356,8 @@ struct iwl4965_rx_queue {
419#define IWL_INVALID_RATE 0xFF 356#define IWL_INVALID_RATE 0xFF
420#define IWL_INVALID_VALUE -1 357#define IWL_INVALID_VALUE -1
421 358
422#ifdef CONFIG_IWL4965_HT
423/** 359/**
424 * struct iwl4965_ht_agg -- aggregation status while waiting for block-ack 360 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
425 * @txq_id: Tx queue used for Tx attempt 361 * @txq_id: Tx queue used for Tx attempt
426 * @frame_count: # frames attempted by Tx command 362 * @frame_count: # frames attempted by Tx command
427 * @wait_for_ba: Expect block-ack before next Tx reply 363 * @wait_for_ba: Expect block-ack before next Tx reply
@@ -434,7 +370,7 @@ struct iwl4965_rx_queue {
434 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info 370 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
435 * until block ack arrives. 371 * until block ack arrives.
436 */ 372 */
437struct iwl4965_ht_agg { 373struct iwl_ht_agg {
438 u16 txq_id; 374 u16 txq_id;
439 u16 frame_count; 375 u16 frame_count;
440 u16 wait_for_ba; 376 u16 wait_for_ba;
@@ -448,21 +384,17 @@ struct iwl4965_ht_agg {
448 u8 state; 384 u8 state;
449}; 385};
450 386
451#endif /* CONFIG_IWL4965_HT */
452 387
453struct iwl4965_tid_data { 388struct iwl_tid_data {
454 u16 seq_number; 389 u16 seq_number;
455 u16 tfds_in_queue; 390 u16 tfds_in_queue;
456#ifdef CONFIG_IWL4965_HT 391 struct iwl_ht_agg agg;
457 struct iwl4965_ht_agg agg;
458#endif /* CONFIG_IWL4965_HT */
459}; 392};
460 393
461struct iwl4965_hw_key { 394struct iwl_hw_key {
462 enum ieee80211_key_alg alg; 395 enum ieee80211_key_alg alg;
463 int keylen; 396 int keylen;
464 u8 keyidx; 397 u8 keyidx;
465 struct ieee80211_key_conf *conf;
466 u8 key[32]; 398 u8 key[32];
467}; 399};
468 400
@@ -474,7 +406,6 @@ union iwl4965_ht_rate_supp {
474 }; 406 };
475}; 407};
476 408
477#ifdef CONFIG_IWL4965_HT
478#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3) 409#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
479#define CFG_HT_MPDU_DENSITY_2USEC (0x5) 410#define CFG_HT_MPDU_DENSITY_2USEC (0x5)
480#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC 411#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC
@@ -497,9 +428,8 @@ struct iwl_ht_info {
497 u8 ht_protection; 428 u8 ht_protection;
498 u8 non_GF_STA_present; 429 u8 non_GF_STA_present;
499}; 430};
500#endif /*CONFIG_IWL4965_HT */
501 431
502union iwl4965_qos_capabity { 432union iwl_qos_capabity {
503 struct { 433 struct {
504 u8 edca_count:4; /* bit 0-3 */ 434 u8 edca_count:4; /* bit 0-3 */
505 u8 q_ack:1; /* bit 4 */ 435 u8 q_ack:1; /* bit 4 */
@@ -520,22 +450,22 @@ union iwl4965_qos_capabity {
520}; 450};
521 451
522/* QoS structures */ 452/* QoS structures */
523struct iwl4965_qos_info { 453struct iwl_qos_info {
524 int qos_enable; 454 int qos_enable;
525 int qos_active; 455 int qos_active;
526 union iwl4965_qos_capabity qos_cap; 456 union iwl_qos_capabity qos_cap;
527 struct iwl4965_qosparam_cmd def_qos_parm; 457 struct iwl_qosparam_cmd def_qos_parm;
528}; 458};
529 459
530#define STA_PS_STATUS_WAKE 0 460#define STA_PS_STATUS_WAKE 0
531#define STA_PS_STATUS_SLEEP 1 461#define STA_PS_STATUS_SLEEP 1
532 462
533struct iwl4965_station_entry { 463struct iwl_station_entry {
534 struct iwl4965_addsta_cmd sta; 464 struct iwl_addsta_cmd sta;
535 struct iwl4965_tid_data tid[MAX_TID_COUNT]; 465 struct iwl_tid_data tid[MAX_TID_COUNT];
536 u8 used; 466 u8 used;
537 u8 ps_status; 467 u8 ps_status;
538 struct iwl4965_hw_key keyinfo; 468 struct iwl_hw_key keyinfo;
539}; 469};
540 470
541/* one for each uCode image (inst/data, boot/init/runtime) */ 471/* one for each uCode image (inst/data, boot/init/runtime) */
@@ -546,7 +476,7 @@ struct fw_desc {
546}; 476};
547 477
548/* uCode file layout */ 478/* uCode file layout */
549struct iwl4965_ucode { 479struct iwl_ucode {
550 __le32 ver; /* major/minor/subminor */ 480 __le32 ver; /* major/minor/subminor */
551 __le32 inst_size; /* bytes of runtime instructions */ 481 __le32 inst_size; /* bytes of runtime instructions */
552 __le32 data_size; /* bytes of runtime data */ 482 __le32 data_size; /* bytes of runtime data */
@@ -556,8 +486,6 @@ struct iwl4965_ucode {
556 u8 data[0]; /* data in same order as "size" elements */ 486 u8 data[0]; /* data in same order as "size" elements */
557}; 487};
558 488
559#define IWL_IBSS_MAC_HASH_SIZE 32
560
561struct iwl4965_ibss_seq { 489struct iwl4965_ibss_seq {
562 u8 mac[ETH_ALEN]; 490 u8 mac[ETH_ALEN];
563 u16 seq_num; 491 u16 seq_num;
@@ -566,20 +494,52 @@ struct iwl4965_ibss_seq {
566 struct list_head list; 494 struct list_head list;
567}; 495};
568 496
497struct iwl_sensitivity_ranges {
498 u16 min_nrg_cck;
499 u16 max_nrg_cck;
500
501 u16 nrg_th_cck;
502 u16 nrg_th_ofdm;
503
504 u16 auto_corr_min_ofdm;
505 u16 auto_corr_min_ofdm_mrc;
506 u16 auto_corr_min_ofdm_x1;
507 u16 auto_corr_min_ofdm_mrc_x1;
508
509 u16 auto_corr_max_ofdm;
510 u16 auto_corr_max_ofdm_mrc;
511 u16 auto_corr_max_ofdm_x1;
512 u16 auto_corr_max_ofdm_mrc_x1;
513
514 u16 auto_corr_max_cck;
515 u16 auto_corr_max_cck_mrc;
516 u16 auto_corr_min_cck;
517 u16 auto_corr_min_cck_mrc;
518};
519
520
521#define IWL_FAT_CHANNEL_52 BIT(IEEE80211_BAND_5GHZ)
522
569/** 523/**
570 * struct iwl_hw_params 524 * struct iwl_hw_params
571 * @max_txq_num: Max # Tx queues supported 525 * @max_txq_num: Max # Tx queues supported
572 * @tx_cmd_len: Size of Tx command (but not including frame itself) 526 * @tx/rx_chains_num: Number of TX/RX chains
573 * @tx_ant_num: Number of TX antennas 527 * @valid_tx/rx_ant: usable antennas
574 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2) 528 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
575 * @rx_buffer_size:
576 * @max_rxq_log: Log-base-2 of max_rxq_size 529 * @max_rxq_log: Log-base-2 of max_rxq_size
530 * @rx_buf_size: Rx buffer size
577 * @max_stations: 531 * @max_stations:
578 * @bcast_sta_id: 532 * @bcast_sta_id:
533 * @fat_channel: is 40MHz width possible in band 2.4
534 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
535 * @sw_crypto: 0 for hw, 1 for sw
536 * @max_xxx_size: for ucode uses
537 * @ct_kill_threshold: temperature threshold
538 * @struct iwl_sensitivity_ranges: range of sensitivity values
539 * @first_ampdu_q: first HW queue available for ampdu
579 */ 540 */
580struct iwl_hw_params { 541struct iwl_hw_params {
581 u16 max_txq_num; 542 u16 max_txq_num;
582 u16 tx_cmd_len;
583 u8 tx_chains_num; 543 u8 tx_chains_num;
584 u8 rx_chains_num; 544 u8 rx_chains_num;
585 u8 valid_tx_ant; 545 u8 valid_tx_ant;
@@ -590,10 +550,18 @@ struct iwl_hw_params {
590 u32 max_pkt_size; 550 u32 max_pkt_size;
591 u8 max_stations; 551 u8 max_stations;
592 u8 bcast_sta_id; 552 u8 bcast_sta_id;
553 u8 fat_channel;
554 u8 sw_crypto;
555 u32 max_inst_size;
556 u32 max_data_size;
557 u32 max_bsm_size;
558 u32 ct_kill_threshold; /* value in hw-dependent units */
559 const struct iwl_sensitivity_ranges *sens;
560 u8 first_ampdu_q;
593}; 561};
594 562
595#define HT_SHORT_GI_20MHZ_ONLY (1 << 0) 563#define HT_SHORT_GI_20MHZ (1 << 0)
596#define HT_SHORT_GI_40MHZ_ONLY (1 << 1) 564#define HT_SHORT_GI_40MHZ (1 << 1)
597 565
598 566
599#define IWL_RX_HDR(x) ((struct iwl4965_rx_frame_hdr *)(\ 567#define IWL_RX_HDR(x) ((struct iwl4965_rx_frame_hdr *)(\
@@ -612,51 +580,18 @@ struct iwl_hw_params {
612 * for use by iwl-*.c 580 * for use by iwl-*.c
613 * 581 *
614 *****************************************************************************/ 582 *****************************************************************************/
615struct iwl4965_addsta_cmd; 583struct iwl_addsta_cmd;
616extern int iwl4965_send_add_station(struct iwl_priv *priv, 584extern int iwl_send_add_sta(struct iwl_priv *priv,
617 struct iwl4965_addsta_cmd *sta, u8 flags); 585 struct iwl_addsta_cmd *sta, u8 flags);
618extern u8 iwl4965_add_station_flags(struct iwl_priv *priv, const u8 *addr, 586u8 iwl_add_station_flags(struct iwl_priv *priv, const u8 *addr, int is_ap,
619 int is_ap, u8 flags, void *ht_data); 587 u8 flags, struct ieee80211_ht_info *ht_info);
620extern int iwl4965_is_network_packet(struct iwl_priv *priv,
621 struct ieee80211_hdr *header);
622extern int iwl4965_power_init_handle(struct iwl_priv *priv);
623extern void iwl4965_handle_data_packet_monitor(struct iwl_priv *priv,
624 struct iwl4965_rx_mem_buffer *rxb,
625 void *data, short len,
626 struct ieee80211_rx_status *stats,
627 u16 phy_flags);
628extern int iwl4965_is_duplicate_packet(struct iwl_priv *priv,
629 struct ieee80211_hdr *header);
630extern int iwl4965_rx_queue_alloc(struct iwl_priv *priv);
631extern void iwl4965_rx_queue_reset(struct iwl_priv *priv,
632 struct iwl4965_rx_queue *rxq);
633extern int iwl4965_calc_db_from_ratio(int sig_ratio);
634extern int iwl4965_calc_sig_qual(int rssi_dbm, int noise_dbm);
635extern int iwl4965_tx_queue_init(struct iwl_priv *priv,
636 struct iwl4965_tx_queue *txq, int count, u32 id);
637extern void iwl4965_rx_replenish(void *data);
638extern void iwl4965_tx_queue_free(struct iwl_priv *priv, struct iwl4965_tx_queue *txq);
639extern unsigned int iwl4965_fill_beacon_frame(struct iwl_priv *priv, 588extern unsigned int iwl4965_fill_beacon_frame(struct iwl_priv *priv,
640 struct ieee80211_hdr *hdr, 589 struct ieee80211_hdr *hdr,
641 const u8 *dest, int left); 590 const u8 *dest, int left);
642extern int iwl4965_rx_queue_update_write_ptr(struct iwl_priv *priv, 591extern void iwl4965_update_chain_flags(struct iwl_priv *priv);
643 struct iwl4965_rx_queue *q); 592int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src);
644extern void iwl4965_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
645 u32 decrypt_res,
646 struct ieee80211_rx_status *stats);
647extern __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr);
648int iwl4965_init_geos(struct iwl_priv *priv);
649void iwl4965_free_geos(struct iwl_priv *priv);
650
651extern const u8 iwl4965_broadcast_addr[ETH_ALEN];
652int iwl4965_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd);
653 593
654/* 594extern const u8 iwl_bcast_addr[ETH_ALEN];
655 * Currently used by iwl-3945-rs... look at restructuring so that it doesn't
656 * call this... todo... fix that.
657*/
658extern u8 iwl4965_sync_station(struct iwl_priv *priv, int sta_id,
659 u16 tx_rate, u8 flags);
660 595
661/****************************************************************************** 596/******************************************************************************
662 * 597 *
@@ -674,96 +609,51 @@ extern u8 iwl4965_sync_station(struct iwl_priv *priv, int sta_id,
674 * iwl4965_mac_ <-- mac80211 callback 609 * iwl4965_mac_ <-- mac80211 callback
675 * 610 *
676 ****************************************************************************/ 611 ****************************************************************************/
677extern void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv); 612extern int iwl_rxq_stop(struct iwl_priv *priv);
678extern void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv); 613extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
679extern void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv);
680extern int iwl4965_hw_rxq_stop(struct iwl_priv *priv);
681extern int iwl4965_hw_set_hw_params(struct iwl_priv *priv);
682extern int iwl4965_hw_nic_init(struct iwl_priv *priv);
683extern int iwl4965_hw_nic_stop_master(struct iwl_priv *priv);
684extern void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv);
685extern void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv);
686extern int iwl4965_hw_nic_reset(struct iwl_priv *priv);
687extern int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *tfd,
688 dma_addr_t addr, u16 len);
689extern int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq);
690extern int iwl4965_hw_get_temperature(struct iwl_priv *priv);
691extern int iwl4965_hw_tx_queue_init(struct iwl_priv *priv,
692 struct iwl4965_tx_queue *txq);
693extern unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv, 614extern unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
694 struct iwl4965_frame *frame, u8 rate); 615 struct iwl_frame *frame, u8 rate);
695extern int iwl4965_hw_get_rx_read(struct iwl_priv *priv);
696extern void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
697 struct iwl_cmd *cmd,
698 struct ieee80211_tx_control *ctrl,
699 struct ieee80211_hdr *hdr,
700 int sta_id, int tx_id);
701extern int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv);
702extern int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power);
703extern void iwl4965_hw_rx_statistics(struct iwl_priv *priv,
704 struct iwl4965_rx_mem_buffer *rxb);
705extern void iwl4965_disable_events(struct iwl_priv *priv); 616extern void iwl4965_disable_events(struct iwl_priv *priv);
706extern int iwl4965_get_temperature(const struct iwl_priv *priv);
707
708/**
709 * iwl4965_hw_find_station - Find station id for a given BSSID
710 * @bssid: MAC address of station ID to find
711 *
712 * NOTE: This should not be hardware specific but the code has
713 * not yet been merged into a single common layer for managing the
714 * station tables.
715 */
716extern u8 iwl4965_hw_find_station(struct iwl_priv *priv, const u8 *bssid);
717 617
718extern int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel); 618extern int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel);
719extern int iwl4965_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index); 619extern int iwl_queue_space(const struct iwl_queue *q);
720extern int iwl4965_queue_space(const struct iwl4965_queue *q); 620static inline int iwl_queue_used(const struct iwl_queue *q, int i)
621{
622 return q->write_ptr > q->read_ptr ?
623 (i >= q->read_ptr && i < q->write_ptr) :
624 !(i < q->read_ptr && i >= q->write_ptr);
625}
626
627
628static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
629{
630 /* This is for scan command, the big buffer at end of command array */
631 if (is_huge)
632 return q->n_window; /* must be power of 2 */
633
634 /* Otherwise, use normal size buffers */
635 return index & (q->n_window - 1);
636}
637
638
721struct iwl_priv; 639struct iwl_priv;
722 640
723extern void iwl4965_radio_kill_sw(struct iwl_priv *priv, int disable_radio);
724/* 641/*
725 * Forward declare iwl-4965.c functions for iwl-base.c 642 * Forward declare iwl-4965.c functions for iwl-base.c
726 */ 643 */
727extern int iwl4965_tx_queue_update_wr_ptr(struct iwl_priv *priv,
728 struct iwl4965_tx_queue *txq,
729 u16 byte_cnt);
730extern void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr,
731 int is_ap);
732extern void iwl4965_set_rxon_chain(struct iwl_priv *priv);
733extern int iwl4965_alive_notify(struct iwl_priv *priv);
734extern void iwl4965_update_rate_scaling(struct iwl_priv *priv, u8 mode);
735extern void iwl4965_chain_noise_reset(struct iwl_priv *priv);
736extern void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags,
737 u8 force);
738extern void iwl4965_rf_kill_ct_config(struct iwl_priv *priv); 644extern void iwl4965_rf_kill_ct_config(struct iwl_priv *priv);
739extern void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, 645
740 u32 rate_n_flags,
741 struct ieee80211_tx_control *control);
742
743#ifdef CONFIG_IWL4965_HT
744void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
745 struct ieee80211_ht_info *ht_info,
746 enum ieee80211_band band);
747void iwl4965_set_rxon_ht(struct iwl_priv *priv,
748 struct iwl_ht_info *ht_info);
749void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
750 struct ieee80211_ht_info *sta_ht_inf);
751int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw, 646int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
752 enum ieee80211_ampdu_mlme_action action, 647 enum ieee80211_ampdu_mlme_action action,
753 const u8 *addr, u16 tid, u16 *ssn); 648 const u8 *addr, u16 tid, u16 *ssn);
754int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id, 649int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
755 u8 tid, int txq_id); 650 u8 tid, int txq_id);
756#else
757static inline void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
758 struct ieee80211_ht_info *ht_info,
759 enum ieee80211_band band) {}
760 651
761#endif /*CONFIG_IWL4965_HT */
762/* Structures, enum, and defines specific to the 4965 */ 652/* Structures, enum, and defines specific to the 4965 */
763 653
764#define IWL4965_KW_SIZE 0x1000 /*4k */ 654#define IWL_KW_SIZE 0x1000 /*4k */
765 655
766struct iwl4965_kw { 656struct iwl_kw {
767 dma_addr_t dma_addr; 657 dma_addr_t dma_addr;
768 void *v_addr; 658 void *v_addr;
769 size_t size; 659 size_t size;
@@ -782,13 +672,8 @@ struct iwl4965_kw {
782#define IWL_OPERATION_MODE_MIXED 2 672#define IWL_OPERATION_MODE_MIXED 2
783#define IWL_OPERATION_MODE_20MHZ 3 673#define IWL_OPERATION_MODE_20MHZ 3
784 674
785#define IWL_EXT_CHANNEL_OFFSET_NONE 0 675#define IWL_TX_CRC_SIZE 4
786#define IWL_EXT_CHANNEL_OFFSET_ABOVE 1 676#define IWL_TX_DELIMITER_SIZE 4
787#define IWL_EXT_CHANNEL_OFFSET_RESERVE1 2
788#define IWL_EXT_CHANNEL_OFFSET_BELOW 3
789
790#define NRG_NUM_PREV_STAT_L 20
791#define NUM_RX_CHAINS (3)
792 677
793#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000 678#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
794 679
@@ -802,7 +687,6 @@ struct iwl4965_lq_mngr {
802 unsigned long stamp_last; 687 unsigned long stamp_last;
803 u32 flush_time; 688 u32 flush_time;
804 u32 tx_packets; 689 u32 tx_packets;
805 u8 lq_ready;
806}; 690};
807 691
808/* Sensitivity and chain noise calibration */ 692/* Sensitivity and chain noise calibration */
@@ -818,23 +702,8 @@ struct iwl4965_lq_mngr {
818#define MAX_FA_CCK 50 702#define MAX_FA_CCK 50
819#define MIN_FA_CCK 5 703#define MIN_FA_CCK 5
820 704
821#define NRG_MIN_CCK 97
822#define NRG_MAX_CCK 0
823
824#define AUTO_CORR_MIN_OFDM 85
825#define AUTO_CORR_MIN_OFDM_MRC 170
826#define AUTO_CORR_MIN_OFDM_X1 105
827#define AUTO_CORR_MIN_OFDM_MRC_X1 220
828#define AUTO_CORR_MAX_OFDM 120
829#define AUTO_CORR_MAX_OFDM_MRC 210
830#define AUTO_CORR_MAX_OFDM_X1 140
831#define AUTO_CORR_MAX_OFDM_MRC_X1 270
832#define AUTO_CORR_STEP_OFDM 1 705#define AUTO_CORR_STEP_OFDM 1
833 706
834#define AUTO_CORR_MIN_CCK (125)
835#define AUTO_CORR_MAX_CCK (200)
836#define AUTO_CORR_MIN_CCK_MRC 200
837#define AUTO_CORR_MAX_CCK_MRC 400
838#define AUTO_CORR_STEP_CCK 3 707#define AUTO_CORR_STEP_CCK 3
839#define AUTO_CORR_MAX_TH_CCK 160 708#define AUTO_CORR_MAX_TH_CCK 160
840 709
@@ -853,6 +722,9 @@ struct iwl4965_lq_mngr {
853#define IN_BAND_FILTER 0xFF 722#define IN_BAND_FILTER 0xFF
854#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF 723#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
855 724
725#define NRG_NUM_PREV_STAT_L 20
726#define NUM_RX_CHAINS 3
727
856enum iwl4965_false_alarm_state { 728enum iwl4965_false_alarm_state {
857 IWL_FA_TOO_MANY = 0, 729 IWL_FA_TOO_MANY = 0,
858 IWL_FA_TOO_FEW = 1, 730 IWL_FA_TOO_FEW = 1,
@@ -865,11 +737,6 @@ enum iwl4965_chain_noise_state {
865 IWL_CHAIN_NOISE_CALIBRATED = 2, 737 IWL_CHAIN_NOISE_CALIBRATED = 2,
866}; 738};
867 739
868enum iwl4965_sensitivity_state {
869 IWL_SENS_CALIB_ALLOWED = 0,
870 IWL_SENS_CALIB_NEED_REINIT = 1,
871};
872
873enum iwl4965_calib_enabled_state { 740enum iwl4965_calib_enabled_state {
874 IWL_CALIB_DISABLED = 0, /* must be 0 */ 741 IWL_CALIB_DISABLED = 0, /* must be 0 */
875 IWL_CALIB_ENABLED = 1, 742 IWL_CALIB_ENABLED = 1,
@@ -884,8 +751,23 @@ struct statistics_general_data {
884 u32 beacon_energy_c; 751 u32 beacon_energy_c;
885}; 752};
886 753
754struct iwl_calib_results {
755 void *tx_iq_res;
756 void *tx_iq_perd_res;
757 void *lo_res;
758 u32 tx_iq_res_len;
759 u32 tx_iq_perd_res_len;
760 u32 lo_res_len;
761};
762
763enum ucode_type {
764 UCODE_NONE = 0,
765 UCODE_INIT,
766 UCODE_RT
767};
768
887/* Sensitivity calib data */ 769/* Sensitivity calib data */
888struct iwl4965_sensitivity_data { 770struct iwl_sensitivity_data {
889 u32 auto_corr_ofdm; 771 u32 auto_corr_ofdm;
890 u32 auto_corr_ofdm_mrc; 772 u32 auto_corr_ofdm_mrc;
891 u32 auto_corr_ofdm_x1; 773 u32 auto_corr_ofdm_x1;
@@ -909,12 +791,10 @@ struct iwl4965_sensitivity_data {
909 s32 nrg_auto_corr_silence_diff; 791 s32 nrg_auto_corr_silence_diff;
910 u32 num_in_cck_no_fa; 792 u32 num_in_cck_no_fa;
911 u32 nrg_th_ofdm; 793 u32 nrg_th_ofdm;
912
913 u8 state;
914}; 794};
915 795
916/* Chain noise (differential Rx gain) calib data */ 796/* Chain noise (differential Rx gain) calib data */
917struct iwl4965_chain_noise_data { 797struct iwl_chain_noise_data {
918 u8 state; 798 u8 state;
919 u16 beacon_count; 799 u16 beacon_count;
920 u32 chain_noise_a; 800 u32 chain_noise_a;
@@ -960,7 +840,7 @@ struct iwl_priv {
960 bool add_radiotap; 840 bool add_radiotap;
961 841
962 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv, 842 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
963 struct iwl4965_rx_mem_buffer *rxb); 843 struct iwl_rx_mem_buffer *rxb);
964 844
965 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; 845 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
966 846
@@ -985,6 +865,9 @@ struct iwl_priv {
985 s32 temperature; /* degrees Kelvin */ 865 s32 temperature; /* degrees Kelvin */
986 s32 last_temperature; 866 s32 last_temperature;
987 867
868 /* init calibration results */
869 struct iwl_calib_results calib_results;
870
988 /* Scan related variables */ 871 /* Scan related variables */
989 unsigned long last_scan_jiffies; 872 unsigned long last_scan_jiffies;
990 unsigned long next_scan_jiffies; 873 unsigned long next_scan_jiffies;
@@ -995,7 +878,8 @@ struct iwl_priv {
995 int one_direct_scan; 878 int one_direct_scan;
996 u8 direct_ssid_len; 879 u8 direct_ssid_len;
997 u8 direct_ssid[IW_ESSID_MAX_SIZE]; 880 u8 direct_ssid[IW_ESSID_MAX_SIZE];
998 struct iwl4965_scan_cmd *scan; 881 struct iwl_scan_cmd *scan;
882 u32 scan_tx_ant[IEEE80211_NUM_BANDS];
999 883
1000 /* spinlock */ 884 /* spinlock */
1001 spinlock_t lock; /* protect general shared data */ 885 spinlock_t lock; /* protect general shared data */
@@ -1007,6 +891,9 @@ struct iwl_priv {
1007 891
1008 /* pci hardware address support */ 892 /* pci hardware address support */
1009 void __iomem *hw_base; 893 void __iomem *hw_base;
894 u32 hw_rev;
895 u32 hw_wa_rev;
896 u8 rev_id;
1010 897
1011 /* uCode images, save to reload in case of failure */ 898 /* uCode images, save to reload in case of failure */
1012 struct fw_desc ucode_code; /* runtime inst */ 899 struct fw_desc ucode_code; /* runtime inst */
@@ -1015,6 +902,8 @@ struct iwl_priv {
1015 struct fw_desc ucode_init; /* initialization inst */ 902 struct fw_desc ucode_init; /* initialization inst */
1016 struct fw_desc ucode_init_data; /* initialization data */ 903 struct fw_desc ucode_init_data; /* initialization data */
1017 struct fw_desc ucode_boot; /* bootstrap inst */ 904 struct fw_desc ucode_boot; /* bootstrap inst */
905 enum ucode_type ucode_type;
906 u8 ucode_write_complete; /* the image write is complete */
1018 907
1019 908
1020 struct iwl4965_rxon_time_cmd rxon_timing; 909 struct iwl4965_rxon_time_cmd rxon_timing;
@@ -1023,22 +912,22 @@ struct iwl_priv {
1023 * changed via explicit cast within the 912 * changed via explicit cast within the
1024 * routines that actually update the physical 913 * routines that actually update the physical
1025 * hardware */ 914 * hardware */
1026 const struct iwl4965_rxon_cmd active_rxon; 915 const struct iwl_rxon_cmd active_rxon;
1027 struct iwl4965_rxon_cmd staging_rxon; 916 struct iwl_rxon_cmd staging_rxon;
1028 917
1029 int error_recovering; 918 int error_recovering;
1030 struct iwl4965_rxon_cmd recovery_rxon; 919 struct iwl_rxon_cmd recovery_rxon;
1031 920
1032 /* 1st responses from initialize and runtime uCode images. 921 /* 1st responses from initialize and runtime uCode images.
1033 * 4965's initialize alive response contains some calibration data. */ 922 * 4965's initialize alive response contains some calibration data. */
1034 struct iwl4965_init_alive_resp card_alive_init; 923 struct iwl_init_alive_resp card_alive_init;
1035 struct iwl4965_alive_resp card_alive; 924 struct iwl_alive_resp card_alive;
1036#ifdef CONFIG_IWLWIFI_RFKILL 925#ifdef CONFIG_IWLWIFI_RFKILL
1037 struct iwl_rfkill_mngr rfkill_mngr; 926 struct rfkill *rfkill;
1038#endif 927#endif
1039 928
1040#ifdef CONFIG_IWLWIFI_LEDS 929#ifdef CONFIG_IWLWIFI_LEDS
1041 struct iwl4965_led led[IWL_LED_TRG_MAX]; 930 struct iwl_led led[IWL_LED_TRG_MAX];
1042 unsigned long last_blink_time; 931 unsigned long last_blink_time;
1043 u8 last_blink_rate; 932 u8 last_blink_rate;
1044 u8 allow_blinking; 933 u8 allow_blinking;
@@ -1050,17 +939,12 @@ struct iwl_priv {
1050 939
1051 u8 assoc_station_added; 940 u8 assoc_station_added;
1052 u8 use_ant_b_for_management_frame; /* Tx antenna selection */ 941 u8 use_ant_b_for_management_frame; /* Tx antenna selection */
1053 u8 valid_antenna; /* Bit mask of antennas actually connected */
1054#ifdef CONFIG_IWL4965_SENSITIVITY
1055 struct iwl4965_sensitivity_data sensitivity_data;
1056 struct iwl4965_chain_noise_data chain_noise_data;
1057 u8 start_calib; 942 u8 start_calib;
943 struct iwl_sensitivity_data sensitivity_data;
944 struct iwl_chain_noise_data chain_noise_data;
1058 __le16 sensitivity_tbl[HD_TABLE_SIZE]; 945 __le16 sensitivity_tbl[HD_TABLE_SIZE];
1059#endif /*CONFIG_IWL4965_SENSITIVITY*/
1060 946
1061#ifdef CONFIG_IWL4965_HT
1062 struct iwl_ht_info current_ht_config; 947 struct iwl_ht_info current_ht_config;
1063#endif
1064 u8 last_phy_res[100]; 948 u8 last_phy_res[100];
1065 949
1066 /* Rate scaling data */ 950 /* Rate scaling data */
@@ -1075,10 +959,10 @@ struct iwl_priv {
1075 int activity_timer_active; 959 int activity_timer_active;
1076 960
1077 /* Rx and Tx DMA processing queues */ 961 /* Rx and Tx DMA processing queues */
1078 struct iwl4965_rx_queue rxq; 962 struct iwl_rx_queue rxq;
1079 struct iwl4965_tx_queue txq[IWL_MAX_NUM_QUEUES]; 963 struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES];
1080 unsigned long txq_ctx_active_msk; 964 unsigned long txq_ctx_active_msk;
1081 struct iwl4965_kw kw; /* keep warm address */ 965 struct iwl_kw kw; /* keep warm address */
1082 u32 scd_base_addr; /* scheduler sram base address */ 966 u32 scd_base_addr; /* scheduler sram base address */
1083 967
1084 unsigned long status; 968 unsigned long status;
@@ -1092,9 +976,9 @@ struct iwl_priv {
1092 u64 bytes; 976 u64 bytes;
1093 } tx_stats[3], rx_stats[3]; 977 } tx_stats[3], rx_stats[3];
1094 978
1095 struct iwl4965_power_mgr power_data; 979 struct iwl_power_mgr power_data;
1096 980
1097 struct iwl4965_notif_statistics statistics; 981 struct iwl_notif_statistics statistics;
1098 unsigned long last_statistics_time; 982 unsigned long last_statistics_time;
1099 983
1100 /* context information */ 984 /* context information */
@@ -1111,7 +995,7 @@ struct iwl_priv {
1111 /*station table variables */ 995 /*station table variables */
1112 spinlock_t sta_lock; 996 spinlock_t sta_lock;
1113 int num_stations; 997 int num_stations;
1114 struct iwl4965_station_entry stations[IWL_STATION_COUNT]; 998 struct iwl_station_entry stations[IWL_STATION_COUNT];
1115 struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; 999 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1116 u8 default_wep_key; 1000 u8 default_wep_key;
1117 u8 key_mapping_key; 1001 u8 key_mapping_key;
@@ -1122,22 +1006,13 @@ struct iwl_priv {
1122 1006
1123 u8 mac80211_registered; 1007 u8 mac80211_registered;
1124 1008
1125 u32 notif_missed_beacons;
1126
1127 /* Rx'd packet timing information */ 1009 /* Rx'd packet timing information */
1128 u32 last_beacon_time; 1010 u32 last_beacon_time;
1129 u64 last_tsf; 1011 u64 last_tsf;
1130 1012
1131 /* Duplicate packet detection */
1132 u16 last_seq_num;
1133 u16 last_frag_num;
1134 unsigned long last_packet_time;
1135
1136 /* Hash table for finding stations in IBSS network */
1137 struct list_head ibss_mac_hash[IWL_IBSS_MAC_HASH_SIZE];
1138
1139 /* eeprom */ 1013 /* eeprom */
1140 struct iwl4965_eeprom eeprom; 1014 u8 *eeprom;
1015 struct iwl_eeprom_calib_info *calib_info;
1141 1016
1142 enum ieee80211_if_types iw_mode; 1017 enum ieee80211_if_types iw_mode;
1143 1018
@@ -1151,6 +1026,7 @@ struct iwl_priv {
1151 struct iwl_hw_params hw_params; 1026 struct iwl_hw_params hw_params;
1152 /* driver/uCode shared Tx Byte Counts and Rx status */ 1027 /* driver/uCode shared Tx Byte Counts and Rx status */
1153 void *shared_virt; 1028 void *shared_virt;
1029 int rb_closed_offset;
1154 /* Physical Pointer to Tx Byte Counts and Rx status */ 1030 /* Physical Pointer to Tx Byte Counts and Rx status */
1155 dma_addr_t shared_phys; 1031 dma_addr_t shared_phys;
1156 1032
@@ -1160,7 +1036,7 @@ struct iwl_priv {
1160 u16 assoc_capability; 1036 u16 assoc_capability;
1161 u8 ps_mode; 1037 u8 ps_mode;
1162 1038
1163 struct iwl4965_qos_info qos_data; 1039 struct iwl_qos_info qos_data;
1164 1040
1165 struct workqueue_struct *workqueue; 1041 struct workqueue_struct *workqueue;
1166 1042
@@ -1176,20 +1052,16 @@ struct iwl_priv {
1176 struct work_struct report_work; 1052 struct work_struct report_work;
1177 struct work_struct request_scan; 1053 struct work_struct request_scan;
1178 struct work_struct beacon_update; 1054 struct work_struct beacon_update;
1055 struct work_struct set_monitor;
1179 1056
1180 struct tasklet_struct irq_tasklet; 1057 struct tasklet_struct irq_tasklet;
1181 1058
1182 struct delayed_work init_alive_start; 1059 struct delayed_work init_alive_start;
1183 struct delayed_work alive_start; 1060 struct delayed_work alive_start;
1184 struct delayed_work activity_timer;
1185 struct delayed_work thermal_periodic;
1186 struct delayed_work gather_stats;
1187 struct delayed_work scan_check; 1061 struct delayed_work scan_check;
1188 struct delayed_work post_associate; 1062 /* TX Power */
1189 1063 s8 tx_power_user_lmt;
1190#define IWL_DEFAULT_TX_POWER 0x0F 1064 s8 tx_power_channel_lmt;
1191 s8 user_txpower_limit;
1192 s8 max_channel_txpower_limit;
1193 1065
1194#ifdef CONFIG_PM 1066#ifdef CONFIG_PM
1195 u32 pm_state[16]; 1067 u32 pm_state[16];
@@ -1197,6 +1069,7 @@ struct iwl_priv {
1197 1069
1198#ifdef CONFIG_IWLWIFI_DEBUG 1070#ifdef CONFIG_IWLWIFI_DEBUG
1199 /* debugging info */ 1071 /* debugging info */
1072 u32 debug_level;
1200 u32 framecnt_to_us; 1073 u32 framecnt_to_us;
1201 atomic_t restrict_refcnt; 1074 atomic_t restrict_refcnt;
1202#ifdef CONFIG_IWLWIFI_DEBUGFS 1075#ifdef CONFIG_IWLWIFI_DEBUGFS
@@ -1206,12 +1079,40 @@ struct iwl_priv {
1206#endif /* CONFIG_IWLWIFI_DEBUG */ 1079#endif /* CONFIG_IWLWIFI_DEBUG */
1207 1080
1208 struct work_struct txpower_work; 1081 struct work_struct txpower_work;
1209#ifdef CONFIG_IWL4965_SENSITIVITY 1082 u32 disable_sens_cal;
1210 struct work_struct sensitivity_work; 1083 u32 disable_chain_noise_cal;
1211#endif 1084 u32 disable_tx_power_cal;
1085 struct work_struct run_time_calib_work;
1212 struct timer_list statistics_periodic; 1086 struct timer_list statistics_periodic;
1213}; /*iwl_priv */ 1087}; /*iwl_priv */
1214 1088
1089static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1090{
1091 set_bit(txq_id, &priv->txq_ctx_active_msk);
1092}
1093
1094static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1095{
1096 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1097}
1098
1099#ifdef CONFIG_IWLWIFI_DEBUG
1100const char *iwl_get_tx_fail_reason(u32 status);
1101#else
1102static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; }
1103#endif
1104
1105
1106static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1107 int txq_id, int idx)
1108{
1109 if (priv->txq[txq_id].txb[idx].skb[0])
1110 return (struct ieee80211_hdr *)priv->txq[txq_id].
1111 txb[idx].skb[0]->data;
1112 return NULL;
1113}
1114
1115
1215static inline int iwl_is_associated(struct iwl_priv *priv) 1116static inline int iwl_is_associated(struct iwl_priv *priv)
1216{ 1117{
1217 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0; 1118 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
@@ -1224,11 +1125,6 @@ static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
1224 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; 1125 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1225} 1126}
1226 1127
1227static inline int is_channel_narrow(const struct iwl_channel_info *ch_info)
1228{
1229 return (ch_info->flags & EEPROM_CHANNEL_NARROW) ? 1 : 0;
1230}
1231
1232static inline int is_channel_radar(const struct iwl_channel_info *ch_info) 1128static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
1233{ 1129{
1234 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; 1130 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
@@ -1254,9 +1150,26 @@ static inline int is_channel_ibss(const struct iwl_channel_info *ch)
1254 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0; 1150 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1255} 1151}
1256 1152
1153#ifdef CONFIG_IWLWIFI_DEBUG
1154static inline void iwl_print_hex_dump(struct iwl_priv *priv, int level,
1155 void *p, u32 len)
1156{
1157 if (!(priv->debug_level & level))
1158 return;
1159
1160 print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
1161 p, len, 1);
1162}
1163#else
1164static inline void iwl_print_hex_dump(struct iwl_priv *priv, int level,
1165 void *p, u32 len)
1166{
1167}
1168#endif
1169
1257extern const struct iwl_channel_info *iwl_get_channel_info( 1170extern const struct iwl_channel_info *iwl_get_channel_info(
1258 const struct iwl_priv *priv, enum ieee80211_band band, u16 channel); 1171 const struct iwl_priv *priv, enum ieee80211_band band, u16 channel);
1259 1172
1260/* Requires full declaration of iwl_priv before including */ 1173/* Requires full declaration of iwl_priv before including */
1261 1174
1262#endif /* __iwl4965_4965_h__ */ 1175#endif /* __iwl_dev_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index a07d5dcb7abc..4a08a1b50979 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -68,8 +68,8 @@
68 68
69#include <net/mac80211.h> 69#include <net/mac80211.h>
70 70
71#include "iwl-4965-commands.h" 71#include "iwl-commands.h"
72#include "iwl-4965.h" 72#include "iwl-dev.h"
73#include "iwl-core.h" 73#include "iwl-core.h"
74#include "iwl-debug.h" 74#include "iwl-debug.h"
75#include "iwl-eeprom.h" 75#include "iwl-eeprom.h"
@@ -193,6 +193,12 @@ void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv)
193} 193}
194EXPORT_SYMBOL(iwlcore_eeprom_release_semaphore); 194EXPORT_SYMBOL(iwlcore_eeprom_release_semaphore);
195 195
196const u8 *iwlcore_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
197{
198 BUG_ON(offset >= priv->cfg->eeprom_size);
199 return &priv->eeprom[offset];
200}
201EXPORT_SYMBOL(iwlcore_eeprom_query_addr);
196 202
197/** 203/**
198 * iwl_eeprom_init - read EEPROM contents 204 * iwl_eeprom_init - read EEPROM contents
@@ -203,30 +209,35 @@ EXPORT_SYMBOL(iwlcore_eeprom_release_semaphore);
203 */ 209 */
204int iwl_eeprom_init(struct iwl_priv *priv) 210int iwl_eeprom_init(struct iwl_priv *priv)
205{ 211{
206 u16 *e = (u16 *)&priv->eeprom; 212 u16 *e;
207 u32 gp = iwl_read32(priv, CSR_EEPROM_GP); 213 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
208 u32 r; 214 u32 r;
209 int sz = sizeof(priv->eeprom); 215 int sz = priv->cfg->eeprom_size;
210 int ret; 216 int ret;
211 int i; 217 int i;
212 u16 addr; 218 u16 addr;
213 219
214 /* The EEPROM structure has several padding buffers within it 220 /* allocate eeprom */
215 * and when adding new EEPROM maps is subject to programmer errors 221 priv->eeprom = kzalloc(sz, GFP_KERNEL);
216 * which may be very difficult to identify without explicitly 222 if (!priv->eeprom) {
217 * checking the resulting size of the eeprom map. */ 223 ret = -ENOMEM;
218 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE); 224 goto alloc_err;
225 }
226 e = (u16 *)priv->eeprom;
219 227
220 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { 228 ret = priv->cfg->ops->lib->eeprom_ops.verify_signature(priv);
229 if (ret < 0) {
221 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp); 230 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
222 return -ENOENT; 231 ret = -ENOENT;
232 goto err;
223 } 233 }
224 234
225 /* Make sure driver (instead of uCode) is allowed to read EEPROM */ 235 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
226 ret = priv->cfg->ops->lib->eeprom_ops.acquire_semaphore(priv); 236 ret = priv->cfg->ops->lib->eeprom_ops.acquire_semaphore(priv);
227 if (ret < 0) { 237 if (ret < 0) {
228 IWL_ERROR("Failed to acquire EEPROM semaphore.\n"); 238 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
229 return -ENOENT; 239 ret = -ENOENT;
240 goto err;
230 } 241 }
231 242
232 /* eeprom is an array of 16bit values */ 243 /* eeprom is an array of 16bit values */
@@ -250,61 +261,98 @@ int iwl_eeprom_init(struct iwl_priv *priv)
250 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16)); 261 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
251 } 262 }
252 ret = 0; 263 ret = 0;
253
254done: 264done:
255 priv->cfg->ops->lib->eeprom_ops.release_semaphore(priv); 265 priv->cfg->ops->lib->eeprom_ops.release_semaphore(priv);
266err:
267 if (ret)
268 kfree(priv->eeprom);
269alloc_err:
256 return ret; 270 return ret;
257} 271}
258EXPORT_SYMBOL(iwl_eeprom_init); 272EXPORT_SYMBOL(iwl_eeprom_init);
259 273
274void iwl_eeprom_free(struct iwl_priv *priv)
275{
276 if(priv->eeprom)
277 kfree(priv->eeprom);
278 priv->eeprom = NULL;
279}
280EXPORT_SYMBOL(iwl_eeprom_free);
281
282int iwl_eeprom_check_version(struct iwl_priv *priv)
283{
284 return priv->cfg->ops->lib->eeprom_ops.check_version(priv);
285}
286EXPORT_SYMBOL(iwl_eeprom_check_version);
287
288const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
289{
290 return priv->cfg->ops->lib->eeprom_ops.query_addr(priv, offset);
291}
292EXPORT_SYMBOL(iwl_eeprom_query_addr);
293
294u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
295{
296 return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8);
297}
298EXPORT_SYMBOL(iwl_eeprom_query16);
260 299
261void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac) 300void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac)
262{ 301{
263 memcpy(mac, priv->eeprom.mac_address, 6); 302 const u8 *addr = priv->cfg->ops->lib->eeprom_ops.query_addr(priv,
303 EEPROM_MAC_ADDRESS);
304 memcpy(mac, addr, ETH_ALEN);
264} 305}
265EXPORT_SYMBOL(iwl_eeprom_get_mac); 306EXPORT_SYMBOL(iwl_eeprom_get_mac);
266 307
267static void iwl_init_band_reference(const struct iwl_priv *priv, 308static void iwl_init_band_reference(const struct iwl_priv *priv,
268 int band, 309 int eep_band, int *eeprom_ch_count,
269 int *eeprom_ch_count, 310 const struct iwl_eeprom_channel **eeprom_ch_info,
270 const struct iwl4965_eeprom_channel 311 const u8 **eeprom_ch_index)
271 **eeprom_ch_info,
272 const u8 **eeprom_ch_index)
273{ 312{
274 switch (band) { 313 u32 offset = priv->cfg->ops->lib->
314 eeprom_ops.regulatory_bands[eep_band - 1];
315 switch (eep_band) {
275 case 1: /* 2.4GHz band */ 316 case 1: /* 2.4GHz band */
276 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1); 317 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
277 *eeprom_ch_info = priv->eeprom.band_1_channels; 318 *eeprom_ch_info = (struct iwl_eeprom_channel *)
319 iwl_eeprom_query_addr(priv, offset);
278 *eeprom_ch_index = iwl_eeprom_band_1; 320 *eeprom_ch_index = iwl_eeprom_band_1;
279 break; 321 break;
280 case 2: /* 4.9GHz band */ 322 case 2: /* 4.9GHz band */
281 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2); 323 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
282 *eeprom_ch_info = priv->eeprom.band_2_channels; 324 *eeprom_ch_info = (struct iwl_eeprom_channel *)
325 iwl_eeprom_query_addr(priv, offset);
283 *eeprom_ch_index = iwl_eeprom_band_2; 326 *eeprom_ch_index = iwl_eeprom_band_2;
284 break; 327 break;
285 case 3: /* 5.2GHz band */ 328 case 3: /* 5.2GHz band */
286 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3); 329 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
287 *eeprom_ch_info = priv->eeprom.band_3_channels; 330 *eeprom_ch_info = (struct iwl_eeprom_channel *)
331 iwl_eeprom_query_addr(priv, offset);
288 *eeprom_ch_index = iwl_eeprom_band_3; 332 *eeprom_ch_index = iwl_eeprom_band_3;
289 break; 333 break;
290 case 4: /* 5.5GHz band */ 334 case 4: /* 5.5GHz band */
291 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4); 335 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
292 *eeprom_ch_info = priv->eeprom.band_4_channels; 336 *eeprom_ch_info = (struct iwl_eeprom_channel *)
337 iwl_eeprom_query_addr(priv, offset);
293 *eeprom_ch_index = iwl_eeprom_band_4; 338 *eeprom_ch_index = iwl_eeprom_band_4;
294 break; 339 break;
295 case 5: /* 5.7GHz band */ 340 case 5: /* 5.7GHz band */
296 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5); 341 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
297 *eeprom_ch_info = priv->eeprom.band_5_channels; 342 *eeprom_ch_info = (struct iwl_eeprom_channel *)
343 iwl_eeprom_query_addr(priv, offset);
298 *eeprom_ch_index = iwl_eeprom_band_5; 344 *eeprom_ch_index = iwl_eeprom_band_5;
299 break; 345 break;
300 case 6: /* 2.4GHz FAT channels */ 346 case 6: /* 2.4GHz FAT channels */
301 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6); 347 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
302 *eeprom_ch_info = priv->eeprom.band_24_channels; 348 *eeprom_ch_info = (struct iwl_eeprom_channel *)
349 iwl_eeprom_query_addr(priv, offset);
303 *eeprom_ch_index = iwl_eeprom_band_6; 350 *eeprom_ch_index = iwl_eeprom_band_6;
304 break; 351 break;
305 case 7: /* 5 GHz FAT channels */ 352 case 7: /* 5 GHz FAT channels */
306 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7); 353 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
307 *eeprom_ch_info = priv->eeprom.band_52_channels; 354 *eeprom_ch_info = (struct iwl_eeprom_channel *)
355 iwl_eeprom_query_addr(priv, offset);
308 *eeprom_ch_index = iwl_eeprom_band_7; 356 *eeprom_ch_index = iwl_eeprom_band_7;
309 break; 357 break;
310 default: 358 default:
@@ -317,13 +365,13 @@ static void iwl_init_band_reference(const struct iwl_priv *priv,
317 ? # x " " : "") 365 ? # x " " : "")
318 366
319/** 367/**
320 * iwl4965_set_fat_chan_info - Copy fat channel info into driver's priv. 368 * iwl_set_fat_chan_info - Copy fat channel info into driver's priv.
321 * 369 *
322 * Does not set up a command, or touch hardware. 370 * Does not set up a command, or touch hardware.
323 */ 371 */
324static int iwl4965_set_fat_chan_info(struct iwl_priv *priv, 372static int iwl_set_fat_chan_info(struct iwl_priv *priv,
325 enum ieee80211_band band, u16 channel, 373 enum ieee80211_band band, u16 channel,
326 const struct iwl4965_eeprom_channel *eeprom_ch, 374 const struct iwl_eeprom_channel *eeprom_ch,
327 u8 fat_extension_channel) 375 u8 fat_extension_channel)
328{ 376{
329 struct iwl_channel_info *ch_info; 377 struct iwl_channel_info *ch_info;
@@ -334,8 +382,8 @@ static int iwl4965_set_fat_chan_info(struct iwl_priv *priv,
334 if (!is_channel_valid(ch_info)) 382 if (!is_channel_valid(ch_info))
335 return -1; 383 return -1;
336 384
337 IWL_DEBUG_INFO("FAT Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x" 385 IWL_DEBUG_INFO("FAT Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
338 " %ddBm): Ad-Hoc %ssupported\n", 386 " Ad-Hoc %ssupported\n",
339 ch_info->channel, 387 ch_info->channel,
340 is_channel_a_band(ch_info) ? 388 is_channel_a_band(ch_info) ?
341 "5.2" : "2.4", 389 "5.2" : "2.4",
@@ -343,7 +391,6 @@ static int iwl4965_set_fat_chan_info(struct iwl_priv *priv,
343 CHECK_AND_PRINT(ACTIVE), 391 CHECK_AND_PRINT(ACTIVE),
344 CHECK_AND_PRINT(RADAR), 392 CHECK_AND_PRINT(RADAR),
345 CHECK_AND_PRINT(WIDE), 393 CHECK_AND_PRINT(WIDE),
346 CHECK_AND_PRINT(NARROW),
347 CHECK_AND_PRINT(DFS), 394 CHECK_AND_PRINT(DFS),
348 eeprom_ch->flags, 395 eeprom_ch->flags,
349 eeprom_ch->max_power_avg, 396 eeprom_ch->max_power_avg,
@@ -372,7 +419,7 @@ int iwl_init_channel_map(struct iwl_priv *priv)
372{ 419{
373 int eeprom_ch_count = 0; 420 int eeprom_ch_count = 0;
374 const u8 *eeprom_ch_index = NULL; 421 const u8 *eeprom_ch_index = NULL;
375 const struct iwl4965_eeprom_channel *eeprom_ch_info = NULL; 422 const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
376 int band, ch; 423 int band, ch;
377 struct iwl_channel_info *ch_info; 424 struct iwl_channel_info *ch_info;
378 425
@@ -381,12 +428,6 @@ int iwl_init_channel_map(struct iwl_priv *priv)
381 return 0; 428 return 0;
382 } 429 }
383 430
384 if (priv->eeprom.version < 0x2f) {
385 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
386 priv->eeprom.version);
387 return -EINVAL;
388 }
389
390 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n"); 431 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
391 432
392 priv->channel_count = 433 priv->channel_count =
@@ -429,6 +470,11 @@ int iwl_init_channel_map(struct iwl_priv *priv)
429 /* Copy the run-time flags so they are there even on 470 /* Copy the run-time flags so they are there even on
430 * invalid channels */ 471 * invalid channels */
431 ch_info->flags = eeprom_ch_info[ch].flags; 472 ch_info->flags = eeprom_ch_info[ch].flags;
473 /* First write that fat is not enabled, and then enable
474 * one by one */
475 ch_info->fat_extension_channel =
476 (IEEE80211_CHAN_NO_FAT_ABOVE |
477 IEEE80211_CHAN_NO_FAT_BELOW);
432 478
433 if (!(is_channel_valid(ch_info))) { 479 if (!(is_channel_valid(ch_info))) {
434 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - " 480 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
@@ -447,8 +493,8 @@ int iwl_init_channel_map(struct iwl_priv *priv)
447 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg; 493 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
448 ch_info->min_power = 0; 494 ch_info->min_power = 0;
449 495
450 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x" 496 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm):"
451 " %ddBm): Ad-Hoc %ssupported\n", 497 " Ad-Hoc %ssupported\n",
452 ch_info->channel, 498 ch_info->channel,
453 is_channel_a_band(ch_info) ? 499 is_channel_a_band(ch_info) ?
454 "5.2" : "2.4", 500 "5.2" : "2.4",
@@ -457,7 +503,6 @@ int iwl_init_channel_map(struct iwl_priv *priv)
457 CHECK_AND_PRINT_I(ACTIVE), 503 CHECK_AND_PRINT_I(ACTIVE),
458 CHECK_AND_PRINT_I(RADAR), 504 CHECK_AND_PRINT_I(RADAR),
459 CHECK_AND_PRINT_I(WIDE), 505 CHECK_AND_PRINT_I(WIDE),
460 CHECK_AND_PRINT_I(NARROW),
461 CHECK_AND_PRINT_I(DFS), 506 CHECK_AND_PRINT_I(DFS),
462 eeprom_ch_info[ch].flags, 507 eeprom_ch_info[ch].flags,
463 eeprom_ch_info[ch].max_power_avg, 508 eeprom_ch_info[ch].max_power_avg,
@@ -470,8 +515,8 @@ int iwl_init_channel_map(struct iwl_priv *priv)
470 /* Set the user_txpower_limit to the highest power 515 /* Set the user_txpower_limit to the highest power
471 * supported by any channel */ 516 * supported by any channel */
472 if (eeprom_ch_info[ch].max_power_avg > 517 if (eeprom_ch_info[ch].max_power_avg >
473 priv->user_txpower_limit) 518 priv->tx_power_user_lmt)
474 priv->user_txpower_limit = 519 priv->tx_power_user_lmt =
475 eeprom_ch_info[ch].max_power_avg; 520 eeprom_ch_info[ch].max_power_avg;
476 521
477 ch_info++; 522 ch_info++;
@@ -494,24 +539,26 @@ int iwl_init_channel_map(struct iwl_priv *priv)
494 for (ch = 0; ch < eeprom_ch_count; ch++) { 539 for (ch = 0; ch < eeprom_ch_count; ch++) {
495 540
496 if ((band == 6) && 541 if ((band == 6) &&
497 ((eeprom_ch_index[ch] == 5) || 542 ((eeprom_ch_index[ch] == 5) ||
498 (eeprom_ch_index[ch] == 6) || 543 (eeprom_ch_index[ch] == 6) ||
499 (eeprom_ch_index[ch] == 7))) 544 (eeprom_ch_index[ch] == 7)))
500 fat_extension_chan = HT_IE_EXT_CHANNEL_MAX; 545 /* both are allowed: above and below */
546 fat_extension_chan = 0;
501 else 547 else
502 fat_extension_chan = HT_IE_EXT_CHANNEL_ABOVE; 548 fat_extension_chan =
549 IEEE80211_CHAN_NO_FAT_BELOW;
503 550
504 /* Set up driver's info for lower half */ 551 /* Set up driver's info for lower half */
505 iwl4965_set_fat_chan_info(priv, ieeeband, 552 iwl_set_fat_chan_info(priv, ieeeband,
506 eeprom_ch_index[ch], 553 eeprom_ch_index[ch],
507 &(eeprom_ch_info[ch]), 554 &(eeprom_ch_info[ch]),
508 fat_extension_chan); 555 fat_extension_chan);
509 556
510 /* Set up driver's info for upper half */ 557 /* Set up driver's info for upper half */
511 iwl4965_set_fat_chan_info(priv, ieeeband, 558 iwl_set_fat_chan_info(priv, ieeeband,
512 (eeprom_ch_index[ch] + 4), 559 (eeprom_ch_index[ch] + 4),
513 &(eeprom_ch_info[ch]), 560 &(eeprom_ch_info[ch]),
514 HT_IE_EXT_CHANNEL_BELOW); 561 IEEE80211_CHAN_NO_FAT_ABOVE);
515 } 562 }
516 } 563 }
517 564
@@ -520,23 +567,21 @@ int iwl_init_channel_map(struct iwl_priv *priv)
520EXPORT_SYMBOL(iwl_init_channel_map); 567EXPORT_SYMBOL(iwl_init_channel_map);
521 568
522/* 569/*
523 * iwl_free_channel_map - undo allocations in iwl4965_init_channel_map 570 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
524 */ 571 */
525void iwl_free_channel_map(struct iwl_priv *priv) 572void iwl_free_channel_map(struct iwl_priv *priv)
526{ 573{
527 kfree(priv->channel_info); 574 kfree(priv->channel_info);
528 priv->channel_count = 0; 575 priv->channel_count = 0;
529} 576}
530EXPORT_SYMBOL(iwl_free_channel_map);
531 577
532/** 578/**
533 * iwl_get_channel_info - Find driver's private channel info 579 * iwl_get_channel_info - Find driver's private channel info
534 * 580 *
535 * Based on band and channel number. 581 * Based on band and channel number.
536 */ 582 */
537const struct iwl_channel_info *iwl_get_channel_info( 583const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
538 const struct iwl_priv *priv, 584 enum ieee80211_band band, u16 channel)
539 enum ieee80211_band band, u16 channel)
540{ 585{
541 int i; 586 int i;
542 587
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.h b/drivers/net/wireless/iwlwifi/iwl-eeprom.h
index bd0a042ca77f..d3a2a5b4ac56 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.h
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.h
@@ -106,7 +106,7 @@ enum {
106 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ 106 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
107 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ 107 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
108 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ 108 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
109 EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel (not used) */ 109 /* Bit 6 Reserved (was Narrow Channel) */
110 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ 110 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
111}; 111};
112 112
@@ -116,7 +116,7 @@ enum {
116 116
117/* *regulatory* channel data format in eeprom, one for each channel. 117/* *regulatory* channel data format in eeprom, one for each channel.
118 * There are separate entries for FAT (40 MHz) vs. normal (20 MHz) channels. */ 118 * There are separate entries for FAT (40 MHz) vs. normal (20 MHz) channels. */
119struct iwl4965_eeprom_channel { 119struct iwl_eeprom_channel {
120 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */ 120 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
121 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ 121 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
122} __attribute__ ((packed)); 122} __attribute__ ((packed));
@@ -131,17 +131,55 @@ struct iwl4965_eeprom_channel {
131 * each of 3 target output levels */ 131 * each of 3 target output levels */
132#define EEPROM_TX_POWER_MEASUREMENTS (3) 132#define EEPROM_TX_POWER_MEASUREMENTS (3)
133 133
134#define EEPROM_4965_TX_POWER_VERSION (2) 134/* 4965 Specific */
135/* 4965 driver does not work with txpower calibration version < 5 */
136#define EEPROM_4965_TX_POWER_VERSION (5)
137#define EEPROM_4965_EEPROM_VERSION (0x2f)
138#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
139#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
140#define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
141#define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
142
143/* 5000 Specific */
144#define EEPROM_5000_TX_POWER_VERSION (4)
145#define EEPROM_5000_EEPROM_VERSION (0x11A)
146
147/*5000 calibrations */
148#define EEPROM_5000_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION)
149#define EEPROM_5000_XTAL ((2*0x128) | EEPROM_5000_CALIB_ALL)
150
151/* 5000 links */
152#define EEPROM_5000_LINK_HOST (2*0x64)
153#define EEPROM_5000_LINK_GENERAL (2*0x65)
154#define EEPROM_5000_LINK_REGULATORY (2*0x66)
155#define EEPROM_5000_LINK_CALIBRATION (2*0x67)
156#define EEPROM_5000_LINK_PROCESS_ADJST (2*0x68)
157#define EEPROM_5000_LINK_OTHERS (2*0x69)
158
159/* 5000 regulatory - indirect access */
160#define EEPROM_5000_REG_SKU_ID ((0x02)\
161 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 4 bytes */
162#define EEPROM_5000_REG_BAND_1_CHANNELS ((0x08)\
163 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 28 bytes */
164#define EEPROM_5000_REG_BAND_2_CHANNELS ((0x26)\
165 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 26 bytes */
166#define EEPROM_5000_REG_BAND_3_CHANNELS ((0x42)\
167 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 24 bytes */
168#define EEPROM_5000_REG_BAND_4_CHANNELS ((0x5C)\
169 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */
170#define EEPROM_5000_REG_BAND_5_CHANNELS ((0x74)\
171 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 12 bytes */
172#define EEPROM_5000_REG_BAND_24_FAT_CHANNELS ((0x82)\
173 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */
174#define EEPROM_5000_REG_BAND_52_FAT_CHANNELS ((0x92)\
175 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */
135 176
136/* 4965 driver does not work with txpower calibration version < 5.
137 * Look for this in calib_version member of struct iwl4965_eeprom. */
138#define EEPROM_TX_POWER_VERSION_NEW (5)
139 177
140/* 2.4 GHz */ 178/* 2.4 GHz */
141extern const u8 iwl_eeprom_band_1[14]; 179extern const u8 iwl_eeprom_band_1[14];
142 180
143/* 181/*
144 * 4965 factory calibration data for one txpower level, on one channel, 182 * factory calibration data for one txpower level, on one channel,
145 * measured on one of the 2 tx chains (radio transmitter and associated 183 * measured on one of the 2 tx chains (radio transmitter and associated
146 * antenna). EEPROM contains: 184 * antenna). EEPROM contains:
147 * 185 *
@@ -154,7 +192,7 @@ extern const u8 iwl_eeprom_band_1[14];
154 * 192 *
155 * 4) RF power amplifier detector level measurement (not used). 193 * 4) RF power amplifier detector level measurement (not used).
156 */ 194 */
157struct iwl4965_eeprom_calib_measure { 195struct iwl_eeprom_calib_measure {
158 u8 temperature; /* Device temperature (Celsius) */ 196 u8 temperature; /* Device temperature (Celsius) */
159 u8 gain_idx; /* Index into gain table */ 197 u8 gain_idx; /* Index into gain table */
160 u8 actual_pow; /* Measured RF output power, half-dBm */ 198 u8 actual_pow; /* Measured RF output power, half-dBm */
@@ -163,22 +201,22 @@ struct iwl4965_eeprom_calib_measure {
163 201
164 202
165/* 203/*
166 * 4965 measurement set for one channel. EEPROM contains: 204 * measurement set for one channel. EEPROM contains:
167 * 205 *
168 * 1) Channel number measured 206 * 1) Channel number measured
169 * 207 *
170 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters 208 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
171 * (a.k.a. "tx chains") (6 measurements altogether) 209 * (a.k.a. "tx chains") (6 measurements altogether)
172 */ 210 */
173struct iwl4965_eeprom_calib_ch_info { 211struct iwl_eeprom_calib_ch_info {
174 u8 ch_num; 212 u8 ch_num;
175 struct iwl4965_eeprom_calib_measure 213 struct iwl_eeprom_calib_measure
176 measurements[EEPROM_TX_POWER_TX_CHAINS] 214 measurements[EEPROM_TX_POWER_TX_CHAINS]
177 [EEPROM_TX_POWER_MEASUREMENTS]; 215 [EEPROM_TX_POWER_MEASUREMENTS];
178} __attribute__ ((packed)); 216} __attribute__ ((packed));
179 217
180/* 218/*
181 * 4965 txpower subband info. 219 * txpower subband info.
182 * 220 *
183 * For each frequency subband, EEPROM contains the following: 221 * For each frequency subband, EEPROM contains the following:
184 * 222 *
@@ -187,16 +225,16 @@ struct iwl4965_eeprom_calib_ch_info {
187 * 225 *
188 * 2) Sample measurement sets for 2 channels close to the range endpoints. 226 * 2) Sample measurement sets for 2 channels close to the range endpoints.
189 */ 227 */
190struct iwl4965_eeprom_calib_subband_info { 228struct iwl_eeprom_calib_subband_info {
191 u8 ch_from; /* channel number of lowest channel in subband */ 229 u8 ch_from; /* channel number of lowest channel in subband */
192 u8 ch_to; /* channel number of highest channel in subband */ 230 u8 ch_to; /* channel number of highest channel in subband */
193 struct iwl4965_eeprom_calib_ch_info ch1; 231 struct iwl_eeprom_calib_ch_info ch1;
194 struct iwl4965_eeprom_calib_ch_info ch2; 232 struct iwl_eeprom_calib_ch_info ch2;
195} __attribute__ ((packed)); 233} __attribute__ ((packed));
196 234
197 235
198/* 236/*
199 * 4965 txpower calibration info. EEPROM contains: 237 * txpower calibration info. EEPROM contains:
200 * 238 *
201 * 1) Factory-measured saturation power levels (maximum levels at which 239 * 1) Factory-measured saturation power levels (maximum levels at which
202 * tx power amplifier can output a signal without too much distortion). 240 * tx power amplifier can output a signal without too much distortion).
@@ -212,55 +250,58 @@ struct iwl4965_eeprom_calib_subband_info {
212 * characteristics of the analog radio circuitry vary with frequency. 250 * characteristics of the analog radio circuitry vary with frequency.
213 * 251 *
214 * Not all sets need to be filled with data; 252 * Not all sets need to be filled with data;
215 * struct iwl4965_eeprom_calib_subband_info contains range of channels 253 * struct iwl_eeprom_calib_subband_info contains range of channels
216 * (0 if unused) for each set of data. 254 * (0 if unused) for each set of data.
217 */ 255 */
218struct iwl4965_eeprom_calib_info { 256struct iwl_eeprom_calib_info {
219 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */ 257 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
220 u8 saturation_power52; /* half-dBm */ 258 u8 saturation_power52; /* half-dBm */
221 s16 voltage; /* signed */ 259 s16 voltage; /* signed */
222 struct iwl4965_eeprom_calib_subband_info 260 struct iwl_eeprom_calib_subband_info
223 band_info[EEPROM_TX_POWER_BANDS]; 261 band_info[EEPROM_TX_POWER_BANDS];
224} __attribute__ ((packed)); 262} __attribute__ ((packed));
225 263
226 264
227 265#define ADDRESS_MSK 0x0000FFFF
228/* 266#define INDIRECT_TYPE_MSK 0x000F0000
229 * 4965 EEPROM map 267#define INDIRECT_HOST 0x00010000
230 */ 268#define INDIRECT_GENERAL 0x00020000
231struct iwl4965_eeprom { 269#define INDIRECT_REGULATORY 0x00030000
232 u8 reserved0[16]; 270#define INDIRECT_CALIBRATION 0x00040000
233 u16 device_id; /* abs.ofs: 16 */ 271#define INDIRECT_PROCESS_ADJST 0x00050000
234 u8 reserved1[2]; 272#define INDIRECT_OTHERS 0x00060000
235 u16 pmc; /* abs.ofs: 20 */ 273#define INDIRECT_ADDRESS 0x00100000
236 u8 reserved2[20]; 274
237 u8 mac_address[6]; /* abs.ofs: 42 */ 275/* General */
238 u8 reserved3[58]; 276#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
239 u16 board_revision; /* abs.ofs: 106 */ 277#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
240 u8 reserved4[11]; 278#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
241 u8 board_pba_number[9]; /* abs.ofs: 119 */ 279#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
242 u8 reserved5[8]; 280#define EEPROM_VERSION (2*0x44) /* 2 bytes */
243 u16 version; /* abs.ofs: 136 */ 281#define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */
244 u8 sku_cap; /* abs.ofs: 138 */ 282#define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */
245 u8 leds_mode; /* abs.ofs: 139 */ 283#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
246 u16 oem_mode; 284#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
247 u16 wowlan_mode; /* abs.ofs: 142 */ 285#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
248 u16 leds_time_interval; /* abs.ofs: 144 */ 286#define EEPROM_3945_M_VERSION (2*0x4A) /* 1 bytes */
249 u8 leds_off_time; /* abs.ofs: 146 */ 287#define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */
250 u8 leds_on_time; /* abs.ofs: 147 */ 288
251 u8 almgor_m_version; /* abs.ofs: 148 */ 289/* The following masks are to be applied on EEPROM_RADIO_CONFIG */
252 u8 antenna_switch_type; /* abs.ofs: 149 */ 290#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
253 u8 reserved6[8]; 291#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
254 u16 board_revision_4965; /* abs.ofs: 158 */ 292#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
255 u8 reserved7[13]; 293#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
256 u8 board_pba_number_4965[9]; /* abs.ofs: 173 */ 294#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
257 u8 reserved8[10]; 295#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
258 u8 sku_id[4]; /* abs.ofs: 192 */ 296
297#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
298#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
299#define EEPROM_5000_RF_CFG_TYPE_MAX 0x3
259 300
260/* 301/*
261 * Per-channel regulatory data. 302 * Per-channel regulatory data.
262 * 303 *
263 * Each channel that *might* be supported by 3945 or 4965 has a fixed location 304 * Each channel that *might* be supported by iwl has a fixed location
264 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory 305 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
265 * txpower (MSB). 306 * txpower (MSB).
266 * 307 *
@@ -269,40 +310,38 @@ struct iwl4965_eeprom {
269 * 310 *
270 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 311 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
271 */ 312 */
272 u16 band_1_count; /* abs.ofs: 196 */ 313#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
273 struct iwl4965_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */ 314#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
315#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
274 316
275/* 317/*
276 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, 318 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
277 * 5.0 GHz channels 7, 8, 11, 12, 16 319 * 5.0 GHz channels 7, 8, 11, 12, 16
278 * (4915-5080MHz) (none of these is ever supported) 320 * (4915-5080MHz) (none of these is ever supported)
279 */ 321 */
280 u16 band_2_count; /* abs.ofs: 226 */ 322#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
281 struct iwl4965_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ 323#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
282 324
283/* 325/*
284 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 326 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
285 * (5170-5320MHz) 327 * (5170-5320MHz)
286 */ 328 */
287 u16 band_3_count; /* abs.ofs: 254 */ 329#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
288 struct iwl4965_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ 330#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
289 331
290/* 332/*
291 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 333 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
292 * (5500-5700MHz) 334 * (5500-5700MHz)
293 */ 335 */
294 u16 band_4_count; /* abs.ofs: 280 */ 336#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
295 struct iwl4965_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ 337#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
296 338
297/* 339/*
298 * 5.7 GHz channels 145, 149, 153, 157, 161, 165 340 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
299 * (5725-5825MHz) 341 * (5725-5825MHz)
300 */ 342 */
301 u16 band_5_count; /* abs.ofs: 304 */ 343#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
302 struct iwl4965_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ 344#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
303
304 u8 reserved10[2];
305
306 345
307/* 346/*
308 * 2.4 GHz FAT channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11) 347 * 2.4 GHz FAT channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
@@ -319,52 +358,35 @@ struct iwl4965_eeprom {
319 * 358 *
320 * NOTE: 4965 does not support FAT channels on 2.4 GHz. 359 * NOTE: 4965 does not support FAT channels on 2.4 GHz.
321 */ 360 */
322 struct iwl4965_eeprom_channel band_24_channels[7]; /* abs.ofs: 320 */ 361#define EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS (2*0xA0) /* 14 bytes */
323 u8 reserved11[2];
324 362
325/* 363/*
326 * 5.2 GHz FAT channels 36 (40), 44 (48), 52 (56), 60 (64), 364 * 5.2 GHz FAT channels 36 (40), 44 (48), 52 (56), 60 (64),
327 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161) 365 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
328 */ 366 */
329 struct iwl4965_eeprom_channel band_52_channels[11]; /* abs.ofs: 336 */ 367#define EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS (2*0xA8) /* 22 bytes */
330 u8 reserved12[6];
331
332/*
333 * 4965 driver requires txpower calibration format version 5 or greater.
334 * Driver does not work with txpower calibration version < 5.
335 * This value is simply a 16-bit number, no major/minor versions here.
336 */
337 u16 calib_version; /* abs.ofs: 364 */
338 u8 reserved13[2];
339 u8 reserved14[96]; /* abs.ofs: 368 */
340
341/*
342 * 4965 Txpower calibration data.
343 */
344 struct iwl4965_eeprom_calib_info calib_info; /* abs.ofs: 464 */
345
346 u8 reserved16[140]; /* fill out to full 1024 byte block */
347
348
349} __attribute__ ((packed));
350
351#define IWL_EEPROM_IMAGE_SIZE 1024
352
353/* End of EEPROM */
354 368
355struct iwl_eeprom_ops { 369struct iwl_eeprom_ops {
370 const u32 regulatory_bands[7];
356 int (*verify_signature) (struct iwl_priv *priv); 371 int (*verify_signature) (struct iwl_priv *priv);
357 int (*acquire_semaphore) (struct iwl_priv *priv); 372 int (*acquire_semaphore) (struct iwl_priv *priv);
358 void (*release_semaphore) (struct iwl_priv *priv); 373 void (*release_semaphore) (struct iwl_priv *priv);
374 int (*check_version) (struct iwl_priv *priv);
375 const u8* (*query_addr) (const struct iwl_priv *priv, size_t offset);
359}; 376};
360 377
361 378
362void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac); 379void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac);
363int iwl_eeprom_init(struct iwl_priv *priv); 380int iwl_eeprom_init(struct iwl_priv *priv);
381void iwl_eeprom_free(struct iwl_priv *priv);
382int iwl_eeprom_check_version(struct iwl_priv *priv);
383const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset);
384u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset);
364 385
365int iwlcore_eeprom_verify_signature(struct iwl_priv *priv); 386int iwlcore_eeprom_verify_signature(struct iwl_priv *priv);
366int iwlcore_eeprom_acquire_semaphore(struct iwl_priv *priv); 387int iwlcore_eeprom_acquire_semaphore(struct iwl_priv *priv);
367void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv); 388void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv);
389const u8 *iwlcore_eeprom_query_addr(const struct iwl_priv *priv, size_t offset);
368 390
369int iwl_init_channel_map(struct iwl_priv *priv); 391int iwl_init_channel_map(struct iwl_priv *priv);
370void iwl_free_channel_map(struct iwl_priv *priv); 392void iwl_free_channel_map(struct iwl_priv *priv);
diff --git a/drivers/net/wireless/iwlwifi/iwl-fh.h b/drivers/net/wireless/iwlwifi/iwl-fh.h
new file mode 100644
index 000000000000..944642450d3d
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-fh.h
@@ -0,0 +1,391 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63
64/****************************/
65/* Flow Handler Definitions */
66/****************************/
67
68/**
69 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
70 * Addresses are offsets from device's PCI hardware base address.
71 */
72#define FH_MEM_LOWER_BOUND (0x1000)
73#define FH_MEM_UPPER_BOUND (0x1EF0)
74
75/**
76 * Keep-Warm (KW) buffer base address.
77 *
78 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
79 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
80 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
81 * from going into a power-savings mode that would cause higher DRAM latency,
82 * and possible data over/under-runs, before all Tx/Rx is complete.
83 *
84 * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
85 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
86 * automatically invokes keep-warm accesses when normal accesses might not
87 * be sufficient to maintain fast DRAM response.
88 *
89 * Bit fields:
90 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
91 */
92#define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
93
94
95/**
96 * TFD Circular Buffers Base (CBBC) addresses
97 *
98 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
99 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
100 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
101 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
102 * aligned (address bits 0-7 must be 0).
103 *
104 * Bit fields in each pointer register:
105 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
106 */
107#define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
108#define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
109
110/* Find TFD CB base pointer for given queue (range 0-15). */
111#define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
112
113
114/**
115 * Rx SRAM Control and Status Registers (RSCSR)
116 *
117 * These registers provide handshake between driver and 4965 for the Rx queue
118 * (this queue handles *all* command responses, notifications, Rx data, etc.
119 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
120 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
121 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
122 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
123 * mapping between RBDs and RBs.
124 *
125 * Driver must allocate host DRAM memory for the following, and set the
126 * physical address of each into 4965 registers:
127 *
128 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
129 * entries (although any power of 2, up to 4096, is selectable by driver).
130 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
131 * (typically 4K, although 8K or 16K are also selectable by driver).
132 * Driver sets up RB size and number of RBDs in the CB via Rx config
133 * register FH_MEM_RCSR_CHNL0_CONFIG_REG.
134 *
135 * Bit fields within one RBD:
136 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
137 *
138 * Driver sets physical address [35:8] of base of RBD circular buffer
139 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
140 *
141 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
142 * (RBs) have been filled, via a "write pointer", actually the index of
143 * the RB's corresponding RBD within the circular buffer. Driver sets
144 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
145 *
146 * Bit fields in lower dword of Rx status buffer (upper dword not used
147 * by driver; see struct iwl4965_shared, val0):
148 * 31-12: Not used by driver
149 * 11- 0: Index of last filled Rx buffer descriptor
150 * (4965 writes, driver reads this value)
151 *
152 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
153 * enter pointers to these RBs into contiguous RBD circular buffer entries,
154 * and update the 4965's "write" index register,
155 * FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
156 *
157 * This "write" index corresponds to the *next* RBD that the driver will make
158 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
159 * the circular buffer. This value should initially be 0 (before preparing any
160 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
161 * wrap back to 0 at the end of the circular buffer (but don't wrap before
162 * "read" index has advanced past 1! See below).
163 * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
164 *
165 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
166 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
167 * to tell the driver the index of the latest filled RBD. The driver must
168 * read this "read" index from DRAM after receiving an Rx interrupt from 4965.
169 *
170 * The driver must also internally keep track of a third index, which is the
171 * next RBD to process. When receiving an Rx interrupt, driver should process
172 * all filled but unprocessed RBs up to, but not including, the RB
173 * corresponding to the "read" index. For example, if "read" index becomes "1",
174 * driver may process the RB pointed to by RBD 0. Depending on volume of
175 * traffic, there may be many RBs to process.
176 *
177 * If read index == write index, 4965 thinks there is no room to put new data.
178 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
179 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
180 * and "read" indexes; that is, make sure that there are no more than 254
181 * buffers waiting to be filled.
182 */
183#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
184#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
185#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
186
187/**
188 * Physical base address of 8-byte Rx Status buffer.
189 * Bit fields:
190 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
191 */
192#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
193
194/**
195 * Physical base address of Rx Buffer Descriptor Circular Buffer.
196 * Bit fields:
197 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
198 */
199#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
200
201/**
202 * Rx write pointer (index, really!).
203 * Bit fields:
204 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
205 * NOTE: For 256-entry circular buffer, use only bits [7:0].
206 */
207#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
208#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
209
210
211/**
212 * Rx Config/Status Registers (RCSR)
213 * Rx Config Reg for channel 0 (only channel used)
214 *
215 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
216 * normal operation (see bit fields).
217 *
218 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
219 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
220 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
221 *
222 * Bit fields:
223 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
224 * '10' operate normally
225 * 29-24: reserved
226 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
227 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
228 * 19-18: reserved
229 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
230 * '10' 12K, '11' 16K.
231 * 15-14: reserved
232 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
233 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
234 * typical value 0x10 (about 1/2 msec)
235 * 3- 0: reserved
236 */
237#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
238#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
239#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
240
241#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
242
243#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
244#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
245#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
246#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
247#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
248#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
249
250#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
251#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT (4)
252#define RX_RB_TIMEOUT (0x10)
253
254#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
255#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
256#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
257
258#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
259#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
260#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
261#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
262
263#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
264#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
265
266
267/**
268 * Rx Shared Status Registers (RSSR)
269 *
270 * After stopping Rx DMA channel (writing 0 to
271 * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
272 * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
273 *
274 * Bit fields:
275 * 24: 1 = Channel 0 is idle
276 *
277 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
278 * contain default values that should not be altered by the driver.
279 */
280#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
281#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
282
283#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
284#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
285#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
286 (FH_MEM_RSSR_LOWER_BOUND + 0x008)
287
288#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
289
290
291/**
292 * Transmit DMA Channel Control/Status Registers (TCSR)
293 *
294 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
295 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
296 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
297 *
298 * To use a Tx DMA channel, driver must initialize its
299 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
300 *
301 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
302 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
303 *
304 * All other bits should be 0.
305 *
306 * Bit fields:
307 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
308 * '10' operate normally
309 * 29- 4: Reserved, set to "0"
310 * 3: Enable internal DMA requests (1, normal operation), disable (0)
311 * 2- 0: Reserved, set to "0"
312 */
313#define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
314#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
315
316/* Find Control/Status reg for given Tx DMA/FIFO channel */
317#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
318 (FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
319
320#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
321#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
322
323#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
324#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
325#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
326
327#define FH_TCSR_CHNL_NUM (7)
328
329#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
330#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
331#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
332
333#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
334#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
335#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
336
337#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
338#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
339#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
340 (FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
341#define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
342 (FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x4)
343#define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
344 (FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x8)
345
346/**
347 * Tx Shared Status Registers (TSSR)
348 *
349 * After stopping Tx DMA channel (writing 0 to
350 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
351 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
352 * (channel's buffers empty | no pending requests).
353 *
354 * Bit fields:
355 * 31-24: 1 = Channel buffers empty (channel 7:0)
356 * 23-16: 1 = No pending requests (channel 7:0)
357 */
358#define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
359#define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
360
361#define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010)
362
363#define FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) ((1 << (_chnl)) << 24)
364#define FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) ((1 << (_chnl)) << 16)
365
366#define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
367 (FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
368 FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
369
370
371
372#define FH_REGS_LOWER_BOUND (0x1000)
373#define FH_REGS_UPPER_BOUND (0x2000)
374
375/* Tx service channels */
376#define FH_SRVC_CHNL (9)
377#define FH_SRVC_LOWER_BOUND (FH_REGS_LOWER_BOUND + 0x9C8)
378#define FH_SRVC_UPPER_BOUND (FH_REGS_LOWER_BOUND + 0x9D0)
379#define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
380 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
381
382/* TFDB Area - TFDs buffer table */
383#define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
384#define FH_TFDIB_LOWER_BOUND (FH_REGS_LOWER_BOUND + 0x900)
385#define FH_TFDIB_UPPER_BOUND (FH_REGS_LOWER_BOUND + 0x958)
386#define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
387#define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
388
389/* TCSR: tx_config register values */
390#define FH_RSCSR_FRAME_SIZE_MSK (0x00003FFF) /* bits 0-13 */
391
diff --git a/drivers/net/wireless/iwlwifi/iwl-hcmd.c b/drivers/net/wireless/iwlwifi/iwl-hcmd.c
index fdb27f1cdc08..8fa991b7202a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-hcmd.c
+++ b/drivers/net/wireless/iwlwifi/iwl-hcmd.c
@@ -31,7 +31,7 @@
31#include <linux/version.h> 31#include <linux/version.h>
32#include <net/mac80211.h> 32#include <net/mac80211.h>
33 33
34#include "iwl-4965.h" /* FIXME: remove */ 34#include "iwl-dev.h" /* FIXME: remove */
35#include "iwl-debug.h" 35#include "iwl-debug.h"
36#include "iwl-eeprom.h" 36#include "iwl-eeprom.h"
37#include "iwl-core.h" 37#include "iwl-core.h"
@@ -56,6 +56,7 @@ const char *get_cmd_string(u8 cmd)
56 IWL_CMD(REPLY_RATE_SCALE); 56 IWL_CMD(REPLY_RATE_SCALE);
57 IWL_CMD(REPLY_LEDS_CMD); 57 IWL_CMD(REPLY_LEDS_CMD);
58 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD); 58 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
59 IWL_CMD(COEX_PRIORITY_TABLE_CMD);
59 IWL_CMD(RADAR_NOTIFICATION); 60 IWL_CMD(RADAR_NOTIFICATION);
60 IWL_CMD(REPLY_QUIET_CMD); 61 IWL_CMD(REPLY_QUIET_CMD);
61 IWL_CMD(REPLY_CHANNEL_SWITCH); 62 IWL_CMD(REPLY_CHANNEL_SWITCH);
@@ -89,6 +90,10 @@ const char *get_cmd_string(u8 cmd)
89 IWL_CMD(REPLY_RX_MPDU_CMD); 90 IWL_CMD(REPLY_RX_MPDU_CMD);
90 IWL_CMD(REPLY_RX); 91 IWL_CMD(REPLY_RX);
91 IWL_CMD(REPLY_COMPRESSED_BA); 92 IWL_CMD(REPLY_COMPRESSED_BA);
93 IWL_CMD(CALIBRATION_CFG_CMD);
94 IWL_CMD(CALIBRATION_RES_NOTIFICATION);
95 IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION);
96 IWL_CMD(REPLY_TX_POWER_DBM_CMD);
92 default: 97 default:
93 return "UNKNOWN"; 98 return "UNKNOWN";
94 99
@@ -101,7 +106,7 @@ EXPORT_SYMBOL(get_cmd_string);
101static int iwl_generic_cmd_callback(struct iwl_priv *priv, 106static int iwl_generic_cmd_callback(struct iwl_priv *priv,
102 struct iwl_cmd *cmd, struct sk_buff *skb) 107 struct iwl_cmd *cmd, struct sk_buff *skb)
103{ 108{
104 struct iwl4965_rx_packet *pkt = NULL; 109 struct iwl_rx_packet *pkt = NULL;
105 110
106 if (!skb) { 111 if (!skb) {
107 IWL_ERROR("Error: Response NULL in %s.\n", 112 IWL_ERROR("Error: Response NULL in %s.\n",
@@ -109,7 +114,7 @@ static int iwl_generic_cmd_callback(struct iwl_priv *priv,
109 return 1; 114 return 1;
110 } 115 }
111 116
112 pkt = (struct iwl4965_rx_packet *)skb->data; 117 pkt = (struct iwl_rx_packet *)skb->data;
113 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { 118 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
114 IWL_ERROR("Bad return from %s (0x%08X)\n", 119 IWL_ERROR("Bad return from %s (0x%08X)\n",
115 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); 120 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
@@ -139,7 +144,7 @@ static int iwl_send_cmd_async(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
139 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 144 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
140 return -EBUSY; 145 return -EBUSY;
141 146
142 ret = priv->cfg->ops->utils->enqueue_hcmd(priv, cmd); 147 ret = iwl_enqueue_hcmd(priv, cmd);
143 if (ret < 0) { 148 if (ret < 0) {
144 IWL_ERROR("Error sending %s: enqueue_hcmd failed: %d\n", 149 IWL_ERROR("Error sending %s: enqueue_hcmd failed: %d\n",
145 get_cmd_string(cmd->id), ret); 150 get_cmd_string(cmd->id), ret);
@@ -170,7 +175,7 @@ int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
170 if (cmd->meta.flags & CMD_WANT_SKB) 175 if (cmd->meta.flags & CMD_WANT_SKB)
171 cmd->meta.source = &cmd->meta; 176 cmd->meta.source = &cmd->meta;
172 177
173 cmd_idx = priv->cfg->ops->utils->enqueue_hcmd(priv, cmd); 178 cmd_idx = iwl_enqueue_hcmd(priv, cmd);
174 if (cmd_idx < 0) { 179 if (cmd_idx < 0) {
175 ret = cmd_idx; 180 ret = cmd_idx;
176 IWL_ERROR("Error sending %s: enqueue_hcmd failed: %d\n", 181 IWL_ERROR("Error sending %s: enqueue_hcmd failed: %d\n",
diff --git a/drivers/net/wireless/iwlwifi/iwl-helpers.h b/drivers/net/wireless/iwlwifi/iwl-helpers.h
index a443472bea62..41eed6793328 100644
--- a/drivers/net/wireless/iwlwifi/iwl-helpers.h
+++ b/drivers/net/wireless/iwlwifi/iwl-helpers.h
@@ -136,8 +136,8 @@ static inline void iwl_set_bits16(__le16 *dst, u8 pos, u8 len, int val)
136 136
137#define KELVIN_TO_CELSIUS(x) ((x)-273) 137#define KELVIN_TO_CELSIUS(x) ((x)-273)
138#define CELSIUS_TO_KELVIN(x) ((x)+273) 138#define CELSIUS_TO_KELVIN(x) ((x)+273)
139#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
139 140
140#define IEEE80211_CHAN_W_RADAR_DETECT 0x00000010
141 141
142static inline struct ieee80211_conf *ieee80211_get_hw_conf( 142static inline struct ieee80211_conf *ieee80211_get_hw_conf(
143 struct ieee80211_hw *hw) 143 struct ieee80211_hw *hw)
@@ -145,96 +145,6 @@ static inline struct ieee80211_conf *ieee80211_get_hw_conf(
145 return &hw->conf; 145 return &hw->conf;
146} 146}
147 147
148#define QOS_CONTROL_LEN 2
149
150
151static inline int ieee80211_is_management(u16 fc)
152{
153 return (fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT;
154}
155
156static inline int ieee80211_is_control(u16 fc)
157{
158 return (fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL;
159}
160
161static inline int ieee80211_is_data(u16 fc)
162{
163 return (fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA;
164}
165
166static inline int ieee80211_is_back_request(u16 fc)
167{
168 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL) &&
169 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_BACK_REQ);
170}
171
172static inline int ieee80211_is_probe_response(u16 fc)
173{
174 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
175 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_PROBE_RESP);
176}
177
178static inline int ieee80211_is_probe_request(u16 fc)
179{
180 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
181 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_PROBE_REQ);
182}
183
184static inline int ieee80211_is_beacon(u16 fc)
185{
186 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
187 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_BEACON);
188}
189
190static inline int ieee80211_is_atim(u16 fc)
191{
192 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
193 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ATIM);
194}
195
196static inline int ieee80211_is_assoc_request(u16 fc)
197{
198 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
199 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ);
200}
201
202static inline int ieee80211_is_assoc_response(u16 fc)
203{
204 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
205 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_RESP);
206}
207
208static inline int ieee80211_is_auth(u16 fc)
209{
210 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
211 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ);
212}
213
214static inline int ieee80211_is_deauth(u16 fc)
215{
216 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
217 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ);
218}
219
220static inline int ieee80211_is_disassoc(u16 fc)
221{
222 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
223 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ);
224}
225
226static inline int ieee80211_is_reassoc_request(u16 fc)
227{
228 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
229 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ);
230}
231
232static inline int ieee80211_is_reassoc_response(u16 fc)
233{
234 return ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
235 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_RESP);
236}
237
238static inline int iwl_check_bits(unsigned long field, unsigned long mask) 148static inline int iwl_check_bits(unsigned long field, unsigned long mask)
239{ 149{
240 return ((field & mask) == mask) ? 1 : 0; 150 return ((field & mask) == mask) ? 1 : 0;
diff --git a/drivers/net/wireless/iwlwifi/iwl-led.c b/drivers/net/wireless/iwlwifi/iwl-led.c
index 03fdf5b434a1..899d7a2567a8 100644
--- a/drivers/net/wireless/iwlwifi/iwl-led.c
+++ b/drivers/net/wireless/iwlwifi/iwl-led.c
@@ -39,19 +39,26 @@
39#include <linux/etherdevice.h> 39#include <linux/etherdevice.h>
40#include <asm/unaligned.h> 40#include <asm/unaligned.h>
41 41
42#include "iwl-4965.h" 42#include "iwl-dev.h"
43#include "iwl-core.h" 43#include "iwl-core.h"
44#include "iwl-io.h" 44#include "iwl-io.h"
45#include "iwl-helpers.h" 45#include "iwl-helpers.h"
46 46
47#define IWL_1MB_RATE (128 * 1024) 47#ifdef CONFIG_IWLWIFI_DEBUG
48#define IWL_LED_THRESHOLD (16) 48static const char *led_type_str[] = {
49#define IWL_MAX_BLINK_TBL (10) 49 __stringify(IWL_LED_TRG_TX),
50 __stringify(IWL_LED_TRG_RX),
51 __stringify(IWL_LED_TRG_ASSOC),
52 __stringify(IWL_LED_TRG_RADIO),
53 NULL
54};
55#endif /* CONFIG_IWLWIFI_DEBUG */
56
50 57
51static const struct { 58static const struct {
52 u16 tpt; 59 u16 tpt;
53 u8 on_time; 60 u8 on_time;
54 u8 of_time; 61 u8 off_time;
55} blink_tbl[] = 62} blink_tbl[] =
56{ 63{
57 {300, 25, 25}, 64 {300, 25, 25},
@@ -63,26 +70,31 @@ static const struct {
63 {15, 95, 95 }, 70 {15, 95, 95 },
64 {10, 110, 110}, 71 {10, 110, 110},
65 {5, 130, 130}, 72 {5, 130, 130},
66 {0, 167, 167} 73 {0, 167, 167},
74/* SOLID_ON */
75 {-1, IWL_LED_SOLID, 0}
67}; 76};
68 77
69static int iwl_led_cmd_callback(struct iwl_priv *priv, 78#define IWL_1MB_RATE (128 * 1024)
70 struct iwl_cmd *cmd, struct sk_buff *skb) 79#define IWL_LED_THRESHOLD (16)
80#define IWL_MAX_BLINK_TBL (ARRAY_SIZE(blink_tbl) - 1) /* exclude SOLID_ON */
81#define IWL_SOLID_BLINK_IDX (ARRAY_SIZE(blink_tbl) - 1)
82
83/* [0-256] -> [0..8] FIXME: we need [0..10] */
84static inline int iwl_brightness_to_idx(enum led_brightness brightness)
71{ 85{
72 return 1; 86 return fls(0x000000FF & (u32)brightness);
73} 87}
74 88
75
76/* Send led command */ 89/* Send led command */
77static int iwl_send_led_cmd(struct iwl_priv *priv, 90static int iwl_send_led_cmd(struct iwl_priv *priv, struct iwl_led_cmd *led_cmd)
78 struct iwl4965_led_cmd *led_cmd)
79{ 91{
80 struct iwl_host_cmd cmd = { 92 struct iwl_host_cmd cmd = {
81 .id = REPLY_LEDS_CMD, 93 .id = REPLY_LEDS_CMD,
82 .len = sizeof(struct iwl4965_led_cmd), 94 .len = sizeof(struct iwl_led_cmd),
83 .data = led_cmd, 95 .data = led_cmd,
84 .meta.flags = CMD_ASYNC, 96 .meta.flags = CMD_ASYNC,
85 .meta.u.callback = iwl_led_cmd_callback 97 .meta.u.callback = NULL,
86 }; 98 };
87 u32 reg; 99 u32 reg;
88 100
@@ -93,33 +105,20 @@ static int iwl_send_led_cmd(struct iwl_priv *priv,
93 return iwl_send_cmd(priv, &cmd); 105 return iwl_send_cmd(priv, &cmd);
94} 106}
95 107
96 108/* Set led pattern command */
97/* Set led on command */
98static int iwl4965_led_on(struct iwl_priv *priv, int led_id)
99{
100 struct iwl4965_led_cmd led_cmd = {
101 .id = led_id,
102 .on = IWL_LED_SOLID,
103 .off = 0,
104 .interval = IWL_DEF_LED_INTRVL
105 };
106 return iwl_send_led_cmd(priv, &led_cmd);
107}
108
109/* Set led on command */
110static int iwl4965_led_pattern(struct iwl_priv *priv, int led_id, 109static int iwl4965_led_pattern(struct iwl_priv *priv, int led_id,
111 enum led_brightness brightness) 110 unsigned int idx)
112{ 111{
113 struct iwl4965_led_cmd led_cmd = { 112 struct iwl_led_cmd led_cmd = {
114 .id = led_id, 113 .id = led_id,
115 .on = brightness,
116 .off = brightness,
117 .interval = IWL_DEF_LED_INTRVL 114 .interval = IWL_DEF_LED_INTRVL
118 }; 115 };
119 if (brightness == LED_FULL) { 116
120 led_cmd.on = IWL_LED_SOLID; 117 BUG_ON(idx > IWL_MAX_BLINK_TBL);
121 led_cmd.off = 0; 118
122 } 119 led_cmd.on = blink_tbl[idx].on_time;
120 led_cmd.off = blink_tbl[idx].off_time;
121
123 return iwl_send_led_cmd(priv, &led_cmd); 122 return iwl_send_led_cmd(priv, &led_cmd);
124} 123}
125 124
@@ -132,10 +131,22 @@ static int iwl4965_led_on_reg(struct iwl_priv *priv, int led_id)
132} 131}
133 132
134#if 0 133#if 0
134/* Set led on command */
135static int iwl4965_led_on(struct iwl_priv *priv, int led_id)
136{
137 struct iwl_led_cmd led_cmd = {
138 .id = led_id,
139 .on = IWL_LED_SOLID,
140 .off = 0,
141 .interval = IWL_DEF_LED_INTRVL
142 };
143 return iwl_send_led_cmd(priv, &led_cmd);
144}
145
135/* Set led off command */ 146/* Set led off command */
136int iwl4965_led_off(struct iwl_priv *priv, int led_id) 147int iwl4965_led_off(struct iwl_priv *priv, int led_id)
137{ 148{
138 struct iwl4965_led_cmd led_cmd = { 149 struct iwl_led_cmd led_cmd = {
139 .id = led_id, 150 .id = led_id,
140 .on = 0, 151 .on = 0,
141 .off = 0, 152 .off = 0,
@@ -155,25 +166,10 @@ static int iwl4965_led_off_reg(struct iwl_priv *priv, int led_id)
155 return 0; 166 return 0;
156} 167}
157 168
158/* Set led blink command */
159static int iwl4965_led_not_solid(struct iwl_priv *priv, int led_id,
160 u8 brightness)
161{
162 struct iwl4965_led_cmd led_cmd = {
163 .id = led_id,
164 .on = brightness,
165 .off = brightness,
166 .interval = IWL_DEF_LED_INTRVL
167 };
168
169 return iwl_send_led_cmd(priv, &led_cmd);
170}
171
172
173/* 169/*
174 * brightness call back function for Tx/Rx LED 170 * brightness call back function for Tx/Rx LED
175 */ 171 */
176static int iwl4965_led_associated(struct iwl_priv *priv, int led_id) 172static int iwl_led_associated(struct iwl_priv *priv, int led_id)
177{ 173{
178 if (test_bit(STATUS_EXIT_PENDING, &priv->status) || 174 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
179 !test_bit(STATUS_READY, &priv->status)) 175 !test_bit(STATUS_READY, &priv->status))
@@ -189,16 +185,18 @@ static int iwl4965_led_associated(struct iwl_priv *priv, int led_id)
189/* 185/*
190 * brightness call back for association and radio 186 * brightness call back for association and radio
191 */ 187 */
192static void iwl4965_led_brightness_set(struct led_classdev *led_cdev, 188static void iwl_led_brightness_set(struct led_classdev *led_cdev,
193 enum led_brightness brightness) 189 enum led_brightness brightness)
194{ 190{
195 struct iwl4965_led *led = container_of(led_cdev, 191 struct iwl_led *led = container_of(led_cdev, struct iwl_led, led_dev);
196 struct iwl4965_led, led_dev);
197 struct iwl_priv *priv = led->priv; 192 struct iwl_priv *priv = led->priv;
198 193
199 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 194 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
200 return; 195 return;
201 196
197
198 IWL_DEBUG_LED("Led type = %s brightness = %d\n",
199 led_type_str[led->type], brightness);
202 switch (brightness) { 200 switch (brightness) {
203 case LED_FULL: 201 case LED_FULL:
204 if (led->type == IWL_LED_TRG_ASSOC) 202 if (led->type == IWL_LED_TRG_ASSOC)
@@ -215,8 +213,10 @@ static void iwl4965_led_brightness_set(struct led_classdev *led_cdev,
215 led->led_off(priv, IWL_LED_LINK); 213 led->led_off(priv, IWL_LED_LINK);
216 break; 214 break;
217 default: 215 default:
218 if (led->led_pattern) 216 if (led->led_pattern) {
219 led->led_pattern(priv, IWL_LED_LINK, brightness); 217 int idx = iwl_brightness_to_idx(brightness);
218 led->led_pattern(priv, IWL_LED_LINK, idx);
219 }
220 break; 220 break;
221 } 221 }
222} 222}
@@ -226,8 +226,7 @@ static void iwl4965_led_brightness_set(struct led_classdev *led_cdev,
226/* 226/*
227 * Register led class with the system 227 * Register led class with the system
228 */ 228 */
229static int iwl_leds_register_led(struct iwl_priv *priv, 229static int iwl_leds_register_led(struct iwl_priv *priv, struct iwl_led *led,
230 struct iwl4965_led *led,
231 enum led_type type, u8 set_led, 230 enum led_type type, u8 set_led,
232 const char *name, char *trigger) 231 const char *name, char *trigger)
233{ 232{
@@ -235,7 +234,7 @@ static int iwl_leds_register_led(struct iwl_priv *priv,
235 int ret; 234 int ret;
236 235
237 led->led_dev.name = name; 236 led->led_dev.name = name;
238 led->led_dev.brightness_set = iwl4965_led_brightness_set; 237 led->led_dev.brightness_set = iwl_led_brightness_set;
239 led->led_dev.default_trigger = trigger; 238 led->led_dev.default_trigger = trigger;
240 239
241 led->priv = priv; 240 led->priv = priv;
@@ -259,32 +258,28 @@ static int iwl_leds_register_led(struct iwl_priv *priv,
259/* 258/*
260 * calculate blink rate according to last 2 sec Tx/Rx activities 259 * calculate blink rate according to last 2 sec Tx/Rx activities
261 */ 260 */
262static inline u8 get_blink_rate(struct iwl_priv *priv) 261static int iwl_get_blink_rate(struct iwl_priv *priv)
263{ 262{
264 int i; 263 int i;
265 u8 blink_rate; 264 u64 current_tpt = priv->tx_stats[2].bytes;
266 u64 current_tpt = priv->tx_stats[2].bytes + priv->rx_stats[2].bytes; 265 /* FIXME: + priv->rx_stats[2].bytes; */
267 s64 tpt = current_tpt - priv->led_tpt; 266 s64 tpt = current_tpt - priv->led_tpt;
268 267
269 if (tpt < 0) /* wrapparound */ 268 if (tpt < 0) /* wrapparound */
270 tpt = -tpt; 269 tpt = -tpt;
271 270
271 IWL_DEBUG_LED("tpt %lld current_tpt %lld\n", tpt, current_tpt);
272 priv->led_tpt = current_tpt; 272 priv->led_tpt = current_tpt;
273 273
274 if (tpt < IWL_LED_THRESHOLD) { 274 if (!priv->allow_blinking)
275 i = IWL_MAX_BLINK_TBL; 275 i = IWL_MAX_BLINK_TBL;
276 } else { 276 else
277 for (i = 0; i < IWL_MAX_BLINK_TBL; i++) 277 for (i = 0; i < IWL_MAX_BLINK_TBL; i++)
278 if (tpt > (blink_tbl[i].tpt * IWL_1MB_RATE)) 278 if (tpt > (blink_tbl[i].tpt * IWL_1MB_RATE))
279 break; 279 break;
280 }
281 /* if 0 frame is transfered */
282 if ((i == IWL_MAX_BLINK_TBL) || !priv->allow_blinking)
283 blink_rate = IWL_LED_SOLID;
284 else
285 blink_rate = blink_tbl[i].on_time;
286 280
287 return blink_rate; 281 IWL_DEBUG_LED("LED BLINK IDX=%d", i);
282 return i;
288} 283}
289 284
290static inline int is_rf_kill(struct iwl_priv *priv) 285static inline int is_rf_kill(struct iwl_priv *priv)
@@ -300,7 +295,7 @@ static inline int is_rf_kill(struct iwl_priv *priv)
300 */ 295 */
301void iwl_leds_background(struct iwl_priv *priv) 296void iwl_leds_background(struct iwl_priv *priv)
302{ 297{
303 u8 blink_rate; 298 u8 blink_idx;
304 299
305 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { 300 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
306 priv->last_blink_time = 0; 301 priv->last_blink_time = 0;
@@ -313,9 +308,10 @@ void iwl_leds_background(struct iwl_priv *priv)
313 308
314 if (!priv->allow_blinking) { 309 if (!priv->allow_blinking) {
315 priv->last_blink_time = 0; 310 priv->last_blink_time = 0;
316 if (priv->last_blink_rate != IWL_LED_SOLID) { 311 if (priv->last_blink_rate != IWL_SOLID_BLINK_IDX) {
317 priv->last_blink_rate = IWL_LED_SOLID; 312 priv->last_blink_rate = IWL_SOLID_BLINK_IDX;
318 iwl4965_led_on(priv, IWL_LED_LINK); 313 iwl4965_led_pattern(priv, IWL_LED_LINK,
314 IWL_SOLID_BLINK_IDX);
319 } 315 }
320 return; 316 return;
321 } 317 }
@@ -324,21 +320,14 @@ void iwl_leds_background(struct iwl_priv *priv)
324 msecs_to_jiffies(1000))) 320 msecs_to_jiffies(1000)))
325 return; 321 return;
326 322
327 blink_rate = get_blink_rate(priv); 323 blink_idx = iwl_get_blink_rate(priv);
328 324
329 /* call only if blink rate change */ 325 /* call only if blink rate change */
330 if (blink_rate != priv->last_blink_rate) { 326 if (blink_idx != priv->last_blink_rate)
331 if (blink_rate != IWL_LED_SOLID) { 327 iwl4965_led_pattern(priv, IWL_LED_LINK, blink_idx);
332 priv->last_blink_time = jiffies +
333 msecs_to_jiffies(1000);
334 iwl4965_led_not_solid(priv, IWL_LED_LINK, blink_rate);
335 } else {
336 priv->last_blink_time = 0;
337 iwl4965_led_on(priv, IWL_LED_LINK);
338 }
339 }
340 328
341 priv->last_blink_rate = blink_rate; 329 priv->last_blink_time = jiffies;
330 priv->last_blink_rate = blink_idx;
342} 331}
343EXPORT_SYMBOL(iwl_leds_background); 332EXPORT_SYMBOL(iwl_leds_background);
344 333
@@ -362,10 +351,8 @@ int iwl_leds_register(struct iwl_priv *priv)
362 priv->led[IWL_LED_TRG_RADIO].led_off = iwl4965_led_off_reg; 351 priv->led[IWL_LED_TRG_RADIO].led_off = iwl4965_led_off_reg;
363 priv->led[IWL_LED_TRG_RADIO].led_pattern = NULL; 352 priv->led[IWL_LED_TRG_RADIO].led_pattern = NULL;
364 353
365 ret = iwl_leds_register_led(priv, 354 ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_RADIO],
366 &priv->led[IWL_LED_TRG_RADIO], 355 IWL_LED_TRG_RADIO, 1, name, trigger);
367 IWL_LED_TRG_RADIO, 1,
368 name, trigger);
369 if (ret) 356 if (ret)
370 goto exit_fail; 357 goto exit_fail;
371 358
@@ -373,10 +360,9 @@ int iwl_leds_register(struct iwl_priv *priv)
373 snprintf(name, sizeof(name), "iwl-%s:assoc", 360 snprintf(name, sizeof(name), "iwl-%s:assoc",
374 wiphy_name(priv->hw->wiphy)); 361 wiphy_name(priv->hw->wiphy));
375 362
376 ret = iwl_leds_register_led(priv, 363 ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_ASSOC],
377 &priv->led[IWL_LED_TRG_ASSOC], 364 IWL_LED_TRG_ASSOC, 0, name, trigger);
378 IWL_LED_TRG_ASSOC, 0, 365
379 name, trigger);
380 /* for assoc always turn led on */ 366 /* for assoc always turn led on */
381 priv->led[IWL_LED_TRG_ASSOC].led_on = iwl4965_led_on_reg; 367 priv->led[IWL_LED_TRG_ASSOC].led_on = iwl4965_led_on_reg;
382 priv->led[IWL_LED_TRG_ASSOC].led_off = iwl4965_led_on_reg; 368 priv->led[IWL_LED_TRG_ASSOC].led_off = iwl4965_led_on_reg;
@@ -386,31 +372,26 @@ int iwl_leds_register(struct iwl_priv *priv)
386 goto exit_fail; 372 goto exit_fail;
387 373
388 trigger = ieee80211_get_rx_led_name(priv->hw); 374 trigger = ieee80211_get_rx_led_name(priv->hw);
389 snprintf(name, sizeof(name), "iwl-%s:RX", 375 snprintf(name, sizeof(name), "iwl-%s:RX", wiphy_name(priv->hw->wiphy));
390 wiphy_name(priv->hw->wiphy));
391 376
392 377
393 ret = iwl_leds_register_led(priv, 378 ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_RX],
394 &priv->led[IWL_LED_TRG_RX], 379 IWL_LED_TRG_RX, 0, name, trigger);
395 IWL_LED_TRG_RX, 0,
396 name, trigger);
397 380
398 priv->led[IWL_LED_TRG_RX].led_on = iwl4965_led_associated; 381 priv->led[IWL_LED_TRG_RX].led_on = iwl_led_associated;
399 priv->led[IWL_LED_TRG_RX].led_off = iwl4965_led_associated; 382 priv->led[IWL_LED_TRG_RX].led_off = iwl_led_associated;
400 priv->led[IWL_LED_TRG_RX].led_pattern = iwl4965_led_pattern; 383 priv->led[IWL_LED_TRG_RX].led_pattern = iwl4965_led_pattern;
401 384
402 if (ret) 385 if (ret)
403 goto exit_fail; 386 goto exit_fail;
404 387
405 trigger = ieee80211_get_tx_led_name(priv->hw); 388 trigger = ieee80211_get_tx_led_name(priv->hw);
406 snprintf(name, sizeof(name), "iwl-%s:TX", 389 snprintf(name, sizeof(name), "iwl-%s:TX", wiphy_name(priv->hw->wiphy));
407 wiphy_name(priv->hw->wiphy)); 390 ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_TX],
408 ret = iwl_leds_register_led(priv, 391 IWL_LED_TRG_TX, 0, name, trigger);
409 &priv->led[IWL_LED_TRG_TX], 392
410 IWL_LED_TRG_TX, 0, 393 priv->led[IWL_LED_TRG_TX].led_on = iwl_led_associated;
411 name, trigger); 394 priv->led[IWL_LED_TRG_TX].led_off = iwl_led_associated;
412 priv->led[IWL_LED_TRG_TX].led_on = iwl4965_led_associated;
413 priv->led[IWL_LED_TRG_TX].led_off = iwl4965_led_associated;
414 priv->led[IWL_LED_TRG_TX].led_pattern = iwl4965_led_pattern; 395 priv->led[IWL_LED_TRG_TX].led_pattern = iwl4965_led_pattern;
415 396
416 if (ret) 397 if (ret)
@@ -425,7 +406,7 @@ exit_fail:
425EXPORT_SYMBOL(iwl_leds_register); 406EXPORT_SYMBOL(iwl_leds_register);
426 407
427/* unregister led class */ 408/* unregister led class */
428static void iwl_leds_unregister_led(struct iwl4965_led *led, u8 set_led) 409static void iwl_leds_unregister_led(struct iwl_led *led, u8 set_led)
429{ 410{
430 if (!led->registered) 411 if (!led->registered)
431 return; 412 return;
diff --git a/drivers/net/wireless/iwlwifi/iwl-led.h b/drivers/net/wireless/iwlwifi/iwl-led.h
index 5bb04128cd65..1980ae5a7e82 100644
--- a/drivers/net/wireless/iwlwifi/iwl-led.h
+++ b/drivers/net/wireless/iwlwifi/iwl-led.h
@@ -49,14 +49,13 @@ enum led_type {
49}; 49};
50 50
51 51
52struct iwl4965_led { 52struct iwl_led {
53 struct iwl_priv *priv; 53 struct iwl_priv *priv;
54 struct led_classdev led_dev; 54 struct led_classdev led_dev;
55 55
56 int (*led_on) (struct iwl_priv *priv, int led_id); 56 int (*led_on) (struct iwl_priv *priv, int led_id);
57 int (*led_off) (struct iwl_priv *priv, int led_id); 57 int (*led_off) (struct iwl_priv *priv, int led_id);
58 int (*led_pattern) (struct iwl_priv *priv, int led_id, 58 int (*led_pattern) (struct iwl_priv *priv, int led_id, unsigned int idx);
59 enum led_brightness brightness);
60 59
61 enum led_type type; 60 enum led_type type;
62 unsigned int registered; 61 unsigned int registered;
diff --git a/drivers/net/wireless/iwlwifi/iwl-power.c b/drivers/net/wireless/iwlwifi/iwl-power.c
new file mode 100644
index 000000000000..2e71803e09ba
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-power.c
@@ -0,0 +1,423 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34
35#include <net/mac80211.h>
36
37#include "iwl-eeprom.h"
38#include "iwl-dev.h"
39#include "iwl-core.h"
40#include "iwl-commands.h"
41#include "iwl-debug.h"
42#include "iwl-power.h"
43#include "iwl-helpers.h"
44
45/*
46 * Setting power level allow the card to go to sleep when not busy
47 * there are three factor that decide the power level to go to, they
48 * are list here with its priority
49 * 1- critical_power_setting this will be set according to card temperature.
50 * 2- system_power_setting this will be set by system PM manager.
51 * 3- user_power_setting this will be set by user either by writing to sys or
52 * mac80211
53 *
54 * if system_power_setting and user_power_setting is set to auto
55 * the power level will be decided according to association status and battery
56 * status.
57 *
58 */
59
60#define MSEC_TO_USEC 1024
61#define IWL_POWER_RANGE_0_MAX (2)
62#define IWL_POWER_RANGE_1_MAX (10)
63
64
65#define NOSLP __constant_cpu_to_le16(0), 0, 0
66#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
67#define SLP_TOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
68#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
69 __constant_cpu_to_le32(X1), \
70 __constant_cpu_to_le32(X2), \
71 __constant_cpu_to_le32(X3), \
72 __constant_cpu_to_le32(X4)}
73
74#define IWL_POWER_ON_BATTERY IWL_POWER_INDEX_5
75#define IWL_POWER_ON_AC_DISASSOC IWL_POWER_MODE_CAM
76#define IWL_POWER_ON_AC_ASSOC IWL_POWER_MODE_CAM
77
78
79#define IWL_CT_KILL_TEMPERATURE 110
80#define IWL_MIN_POWER_TEMPERATURE 100
81#define IWL_REDUCED_POWER_TEMPERATURE 95
82
83/* default power management (not Tx power) table values */
84/* for tim 0-10 */
85static struct iwl_power_vec_entry range_0[IWL_POWER_AC] = {
86 {{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
87 {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
88 {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
89 {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
90 {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
91 {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
92};
93
94
95/* for tim = 3-10 */
96static struct iwl_power_vec_entry range_1[IWL_POWER_AC] = {
97 {{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
98 {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
99 {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
100 {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
101 {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
102 {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 7, 10, 10)}, 2}
103};
104
105/* for tim > 11 */
106static struct iwl_power_vec_entry range_2[IWL_POWER_AC] = {
107 {{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
108 {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
109 {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
110 {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
111 {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
112 {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
113};
114
115/* decide the right power level according to association status
116 * and battery status
117 */
118static u16 iwl_get_auto_power_mode(struct iwl_priv *priv)
119{
120 u16 mode = priv->power_data.user_power_setting;
121
122 switch (priv->power_data.user_power_setting) {
123 case IWL_POWER_AUTO:
124 /* if running on battery */
125 if (priv->power_data.is_battery_active)
126 mode = IWL_POWER_ON_BATTERY;
127 else if (iwl_is_associated(priv))
128 mode = IWL_POWER_ON_AC_ASSOC;
129 else
130 mode = IWL_POWER_ON_AC_DISASSOC;
131 break;
132 case IWL_POWER_BATTERY:
133 mode = IWL_POWER_INDEX_3;
134 break;
135 case IWL_POWER_AC:
136 mode = IWL_POWER_MODE_CAM;
137 break;
138 }
139 return mode;
140}
141
142/* initialize to default */
143static int iwl_power_init_handle(struct iwl_priv *priv)
144{
145 int ret = 0, i;
146 struct iwl_power_mgr *pow_data;
147 int size = sizeof(struct iwl_power_vec_entry) * IWL_POWER_AC;
148 u16 pci_pm;
149
150 IWL_DEBUG_POWER("Initialize power \n");
151
152 pow_data = &(priv->power_data);
153
154 memset(pow_data, 0, sizeof(*pow_data));
155
156 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
157 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
158 memcpy(&pow_data->pwr_range_2[0], &range_2[0], size);
159
160 ret = pci_read_config_word(priv->pci_dev,
161 PCI_LINK_CTRL, &pci_pm);
162 if (ret != 0)
163 return 0;
164 else {
165 struct iwl4965_powertable_cmd *cmd;
166
167 IWL_DEBUG_POWER("adjust power command flags\n");
168
169 for (i = 0; i < IWL_POWER_AC; i++) {
170 cmd = &pow_data->pwr_range_0[i].cmd;
171
172 if (pci_pm & 0x1)
173 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
174 else
175 cmd->flags |= IWL_POWER_PCI_PM_MSK;
176 }
177 }
178 return ret;
179}
180
181/* adjust power command according to dtim period and power level*/
182static int iwl_update_power_command(struct iwl_priv *priv,
183 struct iwl4965_powertable_cmd *cmd,
184 u16 mode)
185{
186 int ret = 0, i;
187 u8 skip;
188 u32 max_sleep = 0;
189 struct iwl_power_vec_entry *range;
190 u8 period = 0;
191 struct iwl_power_mgr *pow_data;
192
193 if (mode > IWL_POWER_INDEX_5) {
194 IWL_DEBUG_POWER("Error invalid power mode \n");
195 return -1;
196 }
197 pow_data = &(priv->power_data);
198
199 if (pow_data->dtim_period <= IWL_POWER_RANGE_0_MAX)
200 range = &pow_data->pwr_range_0[0];
201 else if (pow_data->dtim_period <= IWL_POWER_RANGE_1_MAX)
202 range = &pow_data->pwr_range_1[0];
203 else
204 range = &pow_data->pwr_range_2[0];
205
206 period = pow_data->dtim_period;
207 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl4965_powertable_cmd));
208
209 if (period == 0) {
210 period = 1;
211 skip = 0;
212 } else
213 skip = range[mode].no_dtim;
214
215 if (skip == 0) {
216 max_sleep = period;
217 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
218 } else {
219 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
220 max_sleep = le32_to_cpu(slp_itrvl);
221 if (max_sleep == 0xFF)
222 max_sleep = period * (skip + 1);
223 else if (max_sleep > period)
224 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
225 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
226 }
227
228 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
229 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
230 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
231 }
232
233 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
234 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
235 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
236 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
237 le32_to_cpu(cmd->sleep_interval[0]),
238 le32_to_cpu(cmd->sleep_interval[1]),
239 le32_to_cpu(cmd->sleep_interval[2]),
240 le32_to_cpu(cmd->sleep_interval[3]),
241 le32_to_cpu(cmd->sleep_interval[4]));
242
243 return ret;
244}
245
246
247/*
248 * calucaute the final power mode index
249 */
250int iwl_power_update_mode(struct iwl_priv *priv, u8 refresh)
251{
252 struct iwl_power_mgr *setting = &(priv->power_data);
253 int ret = 0;
254 u16 uninitialized_var(final_mode);
255
256 /* If on battery, set to 3,
257 * if plugged into AC power, set to CAM ("continuously aware mode"),
258 * else user level */
259
260 switch (setting->system_power_setting) {
261 case IWL_POWER_AUTO:
262 final_mode = iwl_get_auto_power_mode(priv);
263 break;
264 case IWL_POWER_BATTERY:
265 final_mode = IWL_POWER_INDEX_3;
266 break;
267 case IWL_POWER_AC:
268 final_mode = IWL_POWER_MODE_CAM;
269 break;
270 default:
271 final_mode = setting->system_power_setting;
272 }
273
274 if (setting->critical_power_setting > final_mode)
275 final_mode = setting->critical_power_setting;
276
277 /* driver only support CAM for non STA network */
278 if (priv->iw_mode != IEEE80211_IF_TYPE_STA)
279 final_mode = IWL_POWER_MODE_CAM;
280
281 if (!iwl_is_rfkill(priv) && !setting->power_disabled &&
282 ((setting->power_mode != final_mode) || refresh)) {
283 struct iwl4965_powertable_cmd cmd;
284
285 if (final_mode != IWL_POWER_MODE_CAM)
286 set_bit(STATUS_POWER_PMI, &priv->status);
287
288 iwl_update_power_command(priv, &cmd, final_mode);
289 cmd.keep_alive_beacons = 0;
290
291 if (final_mode == IWL_POWER_INDEX_5)
292 cmd.flags |= IWL_POWER_FAST_PD;
293
294 if (priv->cfg->ops->lib->set_power)
295 ret = priv->cfg->ops->lib->set_power(priv, &cmd);
296
297 if (final_mode == IWL_POWER_MODE_CAM)
298 clear_bit(STATUS_POWER_PMI, &priv->status);
299 else
300 set_bit(STATUS_POWER_PMI, &priv->status);
301
302 if (priv->cfg->ops->lib->update_chain_flags)
303 priv->cfg->ops->lib->update_chain_flags(priv);
304
305 if (!ret)
306 setting->power_mode = final_mode;
307 }
308
309 return ret;
310}
311EXPORT_SYMBOL(iwl_power_update_mode);
312
313/* Allow other iwl code to disable/enable power management active
314 * this will be usefull for rate scale to disable PM during heavy
315 * Tx/Rx activities
316 */
317int iwl_power_disable_management(struct iwl_priv *priv)
318{
319 u16 prev_mode;
320 int ret = 0;
321
322 if (priv->power_data.power_disabled)
323 return -EBUSY;
324
325 prev_mode = priv->power_data.user_power_setting;
326 priv->power_data.user_power_setting = IWL_POWER_MODE_CAM;
327 ret = iwl_power_update_mode(priv, 0);
328 priv->power_data.power_disabled = 1;
329 priv->power_data.user_power_setting = prev_mode;
330
331 return ret;
332}
333EXPORT_SYMBOL(iwl_power_disable_management);
334
335/* Allow other iwl code to disable/enable power management active
336 * this will be usefull for rate scale to disable PM during hight
337 * valume activities
338 */
339int iwl_power_enable_management(struct iwl_priv *priv)
340{
341 int ret = 0;
342
343 priv->power_data.power_disabled = 0;
344 ret = iwl_power_update_mode(priv, 0);
345 return ret;
346}
347EXPORT_SYMBOL(iwl_power_enable_management);
348
349/* set user_power_setting */
350int iwl_power_set_user_mode(struct iwl_priv *priv, u16 mode)
351{
352 int ret = 0;
353
354 if (mode > IWL_POWER_LIMIT)
355 return -EINVAL;
356
357 priv->power_data.user_power_setting = mode;
358
359 ret = iwl_power_update_mode(priv, 0);
360
361 return ret;
362}
363EXPORT_SYMBOL(iwl_power_set_user_mode);
364
365
366/* set system_power_setting. This should be set by over all
367 * PM application.
368 */
369int iwl_power_set_system_mode(struct iwl_priv *priv, u16 mode)
370{
371 int ret = 0;
372
373 if (mode > IWL_POWER_LIMIT)
374 return -EINVAL;
375
376 priv->power_data.system_power_setting = mode;
377
378 ret = iwl_power_update_mode(priv, 0);
379
380 return ret;
381}
382EXPORT_SYMBOL(iwl_power_set_system_mode);
383
384/* initilize to default */
385void iwl_power_initialize(struct iwl_priv *priv)
386{
387
388 iwl_power_init_handle(priv);
389 priv->power_data.user_power_setting = IWL_POWER_AUTO;
390 priv->power_data.power_disabled = 0;
391 priv->power_data.system_power_setting = IWL_POWER_AUTO;
392 priv->power_data.is_battery_active = 0;
393 priv->power_data.power_disabled = 0;
394 priv->power_data.critical_power_setting = 0;
395}
396EXPORT_SYMBOL(iwl_power_initialize);
397
398/* set critical_power_setting according to temperature value */
399int iwl_power_temperature_change(struct iwl_priv *priv)
400{
401 int ret = 0;
402 u16 new_critical = priv->power_data.critical_power_setting;
403 s32 temperature = KELVIN_TO_CELSIUS(priv->last_temperature);
404
405 if (temperature > IWL_CT_KILL_TEMPERATURE)
406 return 0;
407 else if (temperature > IWL_MIN_POWER_TEMPERATURE)
408 new_critical = IWL_POWER_INDEX_5;
409 else if (temperature > IWL_REDUCED_POWER_TEMPERATURE)
410 new_critical = IWL_POWER_INDEX_3;
411 else
412 new_critical = IWL_POWER_MODE_CAM;
413
414 if (new_critical != priv->power_data.critical_power_setting)
415 priv->power_data.critical_power_setting = new_critical;
416
417 if (priv->power_data.critical_power_setting >
418 priv->power_data.power_mode)
419 ret = iwl_power_update_mode(priv, 0);
420
421 return ret;
422}
423EXPORT_SYMBOL(iwl_power_temperature_change);
diff --git a/drivers/net/wireless/iwlwifi/iwl-power.h b/drivers/net/wireless/iwlwifi/iwl-power.h
new file mode 100644
index 000000000000..b066724a1c2b
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-power.h
@@ -0,0 +1,76 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28#ifndef __iwl_power_setting_h__
29#define __iwl_power_setting_h__
30
31#include <net/mac80211.h>
32#include "iwl-commands.h"
33
34struct iwl_priv;
35
36#define IWL_POWER_MODE_CAM 0x00 /* Continuously Aware Mode, always on */
37#define IWL_POWER_INDEX_3 0x03
38#define IWL_POWER_INDEX_5 0x05
39#define IWL_POWER_AC 0x06
40#define IWL_POWER_BATTERY 0x07
41#define IWL_POWER_AUTO 0x08
42#define IWL_POWER_LIMIT 0x08
43#define IWL_POWER_MASK 0x0F
44#define IWL_POWER_ENABLED 0x10
45
46/* Power management (not Tx power) structures */
47
48struct iwl_power_vec_entry {
49 struct iwl4965_powertable_cmd cmd;
50 u8 no_dtim;
51};
52
53struct iwl_power_mgr {
54 spinlock_t lock;
55 struct iwl_power_vec_entry pwr_range_0[IWL_POWER_AC];
56 struct iwl_power_vec_entry pwr_range_1[IWL_POWER_AC];
57 struct iwl_power_vec_entry pwr_range_2[IWL_POWER_AC];
58 u32 dtim_period;
59 /* final power level that used to calculate final power command */
60 u8 power_mode;
61 u8 user_power_setting; /* set by user through mac80211 or sysfs */
62 u8 system_power_setting; /* set by kernel syatem tools */
63 u8 critical_power_setting; /* set if driver over heated */
64 u8 is_battery_active; /* DC/AC power */
65 u8 power_disabled; /* flag to disable using power saving level */
66};
67
68int iwl_power_update_mode(struct iwl_priv *priv, u8 refresh);
69int iwl_power_disable_management(struct iwl_priv *priv);
70int iwl_power_enable_management(struct iwl_priv *priv);
71int iwl_power_set_user_mode(struct iwl_priv *priv, u16 mode);
72int iwl_power_set_system_mode(struct iwl_priv *priv, u16 mode);
73void iwl_power_initialize(struct iwl_priv *priv);
74int iwl_power_temperature_change(struct iwl_priv *priv);
75
76#endif /* __iwl_power_setting_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h
index c9cf8eef1a90..70d9c7568b98 100644
--- a/drivers/net/wireless/iwlwifi/iwl-prph.h
+++ b/drivers/net/wireless/iwlwifi/iwl-prph.h
@@ -239,40 +239,307 @@
239#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C) 239#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
240#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030) 240#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
241 241
242/**
243 * Tx Scheduler
244 *
245 * The Tx Scheduler selects the next frame to be transmitted, chosing TFDs
246 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
247 * host DRAM. It steers each frame's Tx command (which contains the frame
248 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
249 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
250 * but one DMA channel may take input from several queues.
251 *
252 * Tx DMA channels have dedicated purposes. For 4965, they are used as follows:
253 *
254 * 0 -- EDCA BK (background) frames, lowest priority
255 * 1 -- EDCA BE (best effort) frames, normal priority
256 * 2 -- EDCA VI (video) frames, higher priority
257 * 3 -- EDCA VO (voice) and management frames, highest priority
258 * 4 -- Commands (e.g. RXON, etc.)
259 * 5 -- HCCA short frames
260 * 6 -- HCCA long frames
261 * 7 -- not used by driver (device-internal only)
262 *
263 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
264 * In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to
265 * support 11n aggregation via EDCA DMA channels.
266 *
267 * The driver sets up each queue to work in one of two modes:
268 *
269 * 1) Scheduler-Ack, in which the scheduler automatically supports a
270 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
271 * contains TFDs for a unique combination of Recipient Address (RA)
272 * and Traffic Identifier (TID), that is, traffic of a given
273 * Quality-Of-Service (QOS) priority, destined for a single station.
274 *
275 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
276 * each frame within the BA window, including whether it's been transmitted,
277 * and whether it's been acknowledged by the receiving station. The device
278 * automatically processes block-acks received from the receiving STA,
279 * and reschedules un-acked frames to be retransmitted (successful
280 * Tx completion may end up being out-of-order).
281 *
282 * The driver must maintain the queue's Byte Count table in host DRAM
283 * (struct iwl4965_sched_queue_byte_cnt_tbl) for this mode.
284 * This mode does not support fragmentation.
285 *
286 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
287 * The device may automatically retry Tx, but will retry only one frame
288 * at a time, until receiving ACK from receiving station, or reaching
289 * retry limit and giving up.
290 *
291 * The command queue (#4) must use this mode!
292 * This mode does not require use of the Byte Count table in host DRAM.
293 *
294 * Driver controls scheduler operation via 3 means:
295 * 1) Scheduler registers
296 * 2) Shared scheduler data base in internal 4956 SRAM
297 * 3) Shared data in host DRAM
298 *
299 * Initialization:
300 *
301 * When loading, driver should allocate memory for:
302 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
303 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
304 * (1024 bytes for each queue).
305 *
306 * After receiving "Alive" response from uCode, driver must initialize
307 * the scheduler (especially for queue #4, the command queue, otherwise
308 * the driver can't issue commands!):
309 */
310
311/**
312 * Max Tx window size is the max number of contiguous TFDs that the scheduler
313 * can keep track of at one time when creating block-ack chains of frames.
314 * Note that "64" matches the number of ack bits in a block-ack packet.
315 * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize
316 * IWL49_SCD_CONTEXT_QUEUE_OFFSET(x) values.
317 */
318#define SCD_WIN_SIZE 64
319#define SCD_FRAME_LIMIT 64
320
321/* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */
322#define IWL49_SCD_START_OFFSET 0xa02c00
323
324/*
325 * 4965 tells driver SRAM address for internal scheduler structs via this reg.
326 * Value is valid only after "Alive" response from uCode.
327 */
328#define IWL49_SCD_SRAM_BASE_ADDR (IWL49_SCD_START_OFFSET + 0x0)
329
330/*
331 * Driver may need to update queue-empty bits after changing queue's
332 * write and read pointers (indexes) during (re-)initialization (i.e. when
333 * scheduler is not tracking what's happening).
334 * Bit fields:
335 * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit
336 * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty
337 * NOTE: This register is not used by Linux driver.
338 */
339#define IWL49_SCD_EMPTY_BITS (IWL49_SCD_START_OFFSET + 0x4)
340
341/*
342 * Physical base address of array of byte count (BC) circular buffers (CBs).
343 * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode.
344 * This register points to BC CB for queue 0, must be on 1024-byte boundary.
345 * Others are spaced by 1024 bytes.
346 * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad.
347 * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff).
348 * Bit fields:
349 * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned.
350 */
351#define IWL49_SCD_DRAM_BASE_ADDR (IWL49_SCD_START_OFFSET + 0x10)
352
353/*
354 * Enables any/all Tx DMA/FIFO channels.
355 * Scheduler generates requests for only the active channels.
356 * Set this to 0xff to enable all 8 channels (normal usage).
357 * Bit fields:
358 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7
359 */
360#define IWL49_SCD_TXFACT (IWL49_SCD_START_OFFSET + 0x1c)
361/*
362 * Queue (x) Write Pointers (indexes, really!), one for each Tx queue.
363 * Initialized and updated by driver as new TFDs are added to queue.
364 * NOTE: If using Block Ack, index must correspond to frame's
365 * Start Sequence Number; index = (SSN & 0xff)
366 * NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses?
367 */
368#define IWL49_SCD_QUEUE_WRPTR(x) (IWL49_SCD_START_OFFSET + 0x24 + (x) * 4)
369
370/*
371 * Queue (x) Read Pointers (indexes, really!), one for each Tx queue.
372 * For FIFO mode, index indicates next frame to transmit.
373 * For Scheduler-ACK mode, index indicates first frame in Tx window.
374 * Initialized by driver, updated by scheduler.
375 */
376#define IWL49_SCD_QUEUE_RDPTR(x) (IWL49_SCD_START_OFFSET + 0x64 + (x) * 4)
377
378/*
379 * Select which queues work in chain mode (1) vs. not (0).
380 * Use chain mode to build chains of aggregated frames.
381 * Bit fields:
382 * 31-16: Reserved
383 * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time
384 * NOTE: If driver sets up queue for chain mode, it should be also set up
385 * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x).
386 */
387#define IWL49_SCD_QUEUECHAIN_SEL (IWL49_SCD_START_OFFSET + 0xd0)
388
389/*
390 * Select which queues interrupt driver when scheduler increments
391 * a queue's read pointer (index).
392 * Bit fields:
393 * 31-16: Reserved
394 * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled
395 * NOTE: This functionality is apparently a no-op; driver relies on interrupts
396 * from Rx queue to read Tx command responses and update Tx queues.
397 */
398#define IWL49_SCD_INTERRUPT_MASK (IWL49_SCD_START_OFFSET + 0xe4)
399
400/*
401 * Queue search status registers. One for each queue.
402 * Sets up queue mode and assigns queue to Tx DMA channel.
403 * Bit fields:
404 * 19-10: Write mask/enable bits for bits 0-9
405 * 9: Driver should init to "0"
406 * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0).
407 * Driver should init to "1" for aggregation mode, or "0" otherwise.
408 * 7-6: Driver should init to "0"
409 * 5: Window Size Left; indicates whether scheduler can request
410 * another TFD, based on window size, etc. Driver should init
411 * this bit to "1" for aggregation mode, or "0" for non-agg.
412 * 4-1: Tx FIFO to use (range 0-7).
413 * 0: Queue is active (1), not active (0).
414 * Other bits should be written as "0"
415 *
416 * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled
417 * via SCD_QUEUECHAIN_SEL.
418 */
419#define IWL49_SCD_QUEUE_STATUS_BITS(x)\
420 (IWL49_SCD_START_OFFSET + 0x104 + (x) * 4)
421
422/* Bit field positions */
423#define IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE (0)
424#define IWL49_SCD_QUEUE_STTS_REG_POS_TXF (1)
425#define IWL49_SCD_QUEUE_STTS_REG_POS_WSL (5)
426#define IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)
427
428/* Write masks */
429#define IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)
430#define IWL49_SCD_QUEUE_STTS_REG_MSK (0x0007FC00)
431
432/**
433 * 4965 internal SRAM structures for scheduler, shared with driver ...
434 *
435 * Driver should clear and initialize the following areas after receiving
436 * "Alive" response from 4965 uCode, i.e. after initial
437 * uCode load, or after a uCode load done for error recovery:
438 *
439 * SCD_CONTEXT_DATA_OFFSET (size 128 bytes)
440 * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes)
441 * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes)
442 *
443 * Driver accesses SRAM via HBUS_TARG_MEM_* registers.
444 * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR.
445 * All OFFSET values must be added to this base address.
446 */
447
448/*
449 * Queue context. One 8-byte entry for each of 16 queues.
450 *
451 * Driver should clear this entire area (size 0x80) to 0 after receiving
452 * "Alive" notification from uCode. Additionally, driver should init
453 * each queue's entry as follows:
454 *
455 * LS Dword bit fields:
456 * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64.
457 *
458 * MS Dword bit fields:
459 * 16-22: Frame limit. Driver should init to 10 (0xa).
460 *
461 * Driver should init all other bits to 0.
462 *
463 * Init must be done after driver receives "Alive" response from 4965 uCode,
464 * and when setting up queue for aggregation.
465 */
466#define IWL49_SCD_CONTEXT_DATA_OFFSET 0x380
467#define IWL49_SCD_CONTEXT_QUEUE_OFFSET(x) \
468 (IWL49_SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
469
470#define IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)
471#define IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)
472#define IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
473#define IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
474
475/*
476 * Tx Status Bitmap
477 *
478 * Driver should clear this entire area (size 0x100) to 0 after receiving
479 * "Alive" notification from uCode. Area is used only by device itself;
480 * no other support (besides clearing) is required from driver.
481 */
482#define IWL49_SCD_TX_STTS_BITMAP_OFFSET 0x400
483
242/* 484/*
243 * 4965 Tx Scheduler registers. 485 * RAxTID to queue translation mapping.
244 * Details are documented in iwl-4965-hw.h 486 *
487 * When queue is in Scheduler-ACK mode, frames placed in a that queue must be
488 * for only one combination of receiver address (RA) and traffic ID (TID), i.e.
489 * one QOS priority level destined for one station (for this wireless link,
490 * not final destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit
491 * mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK
492 * mode, the device ignores the mapping value.
493 *
494 * Bit fields, for each 16-bit map:
495 * 15-9: Reserved, set to 0
496 * 8-4: Index into device's station table for recipient station
497 * 3-0: Traffic ID (tid), range 0-15
498 *
499 * Driver should clear this entire area (size 32 bytes) to 0 after receiving
500 * "Alive" notification from uCode. To update a 16-bit map value, driver
501 * must read a dword-aligned value from device SRAM, replace the 16-bit map
502 * value of interest, and write the dword value back into device SRAM.
245 */ 503 */
246#define IWL49_SCD_BASE (PRPH_BASE + 0xa02c00) 504#define IWL49_SCD_TRANSLATE_TBL_OFFSET 0x500
247 505
248#define IWL49_SCD_SRAM_BASE_ADDR (IWL49_SCD_BASE + 0x0) 506/* Find translation table dword to read/write for given queue */
249#define IWL49_SCD_EMPTY_BITS (IWL49_SCD_BASE + 0x4) 507#define IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
250#define IWL49_SCD_DRAM_BASE_ADDR (IWL49_SCD_BASE + 0x10) 508 ((IWL49_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
251#define IWL49_SCD_AIT (IWL49_SCD_BASE + 0x18) 509
252#define IWL49_SCD_TXFACT (IWL49_SCD_BASE + 0x1c) 510#define IWL_SCD_TXFIFO_POS_TID (0)
253#define IWL49_SCD_QUEUE_WRPTR(x) (IWL49_SCD_BASE + 0x24 + (x) * 4) 511#define IWL_SCD_TXFIFO_POS_RA (4)
254#define IWL49_SCD_QUEUE_RDPTR(x) (IWL49_SCD_BASE + 0x64 + (x) * 4) 512#define IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
255#define IWL49_SCD_SETQUEUENUM (IWL49_SCD_BASE + 0xa4) 513
256#define IWL49_SCD_SET_TXSTAT_TXED (IWL49_SCD_BASE + 0xa8) 514/* 5000 SCD */
257#define IWL49_SCD_SET_TXSTAT_DONE (IWL49_SCD_BASE + 0xac) 515#define IWL50_SCD_QUEUE_STTS_REG_POS_TXF (0)
258#define IWL49_SCD_SET_TXSTAT_NOT_SCHD (IWL49_SCD_BASE + 0xb0) 516#define IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
259#define IWL49_SCD_DECREASE_CREDIT (IWL49_SCD_BASE + 0xb4) 517#define IWL50_SCD_QUEUE_STTS_REG_POS_WSL (4)
260#define IWL49_SCD_DECREASE_SCREDIT (IWL49_SCD_BASE + 0xb8) 518#define IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
261#define IWL49_SCD_LOAD_CREDIT (IWL49_SCD_BASE + 0xbc) 519#define IWL50_SCD_QUEUE_STTS_REG_MSK (0x00FF0000)
262#define IWL49_SCD_LOAD_SCREDIT (IWL49_SCD_BASE + 0xc0) 520
263#define IWL49_SCD_BAR (IWL49_SCD_BASE + 0xc4) 521#define IWL50_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
264#define IWL49_SCD_BAR_DW0 (IWL49_SCD_BASE + 0xc8) 522#define IWL50_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
265#define IWL49_SCD_BAR_DW1 (IWL49_SCD_BASE + 0xcc) 523#define IWL50_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
266#define IWL49_SCD_QUEUECHAIN_SEL (IWL49_SCD_BASE + 0xd0) 524#define IWL50_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
267#define IWL49_SCD_QUERY_REQ (IWL49_SCD_BASE + 0xd8) 525#define IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
268#define IWL49_SCD_QUERY_RES (IWL49_SCD_BASE + 0xdc) 526#define IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
269#define IWL49_SCD_PENDING_FRAMES (IWL49_SCD_BASE + 0xe0) 527#define IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
270#define IWL49_SCD_INTERRUPT_MASK (IWL49_SCD_BASE + 0xe4) 528#define IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
271#define IWL49_SCD_INTERRUPT_THRESHOLD (IWL49_SCD_BASE + 0xe8) 529
272#define IWL49_SCD_QUERY_MIN_FRAME_SIZE (IWL49_SCD_BASE + 0x100) 530#define IWL50_SCD_CONTEXT_DATA_OFFSET (0x600)
273#define IWL49_SCD_QUEUE_STATUS_BITS(x) (IWL49_SCD_BASE + 0x104 + (x) * 4) 531#define IWL50_SCD_TX_STTS_BITMAP_OFFSET (0x7B1)
274 532#define IWL50_SCD_TRANSLATE_TBL_OFFSET (0x7E0)
275/* SP SCD */ 533
534#define IWL50_SCD_CONTEXT_QUEUE_OFFSET(x)\
535 (IWL50_SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
536
537#define IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
538 ((IWL50_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffc)
539
540#define IWL50_SCD_QUEUECHAIN_SEL_ALL(x) (((1<<(x)) - 1) &\
541 (~(1<<IWL_CMD_QUEUE_NUM)))
542
276#define IWL50_SCD_BASE (PRPH_BASE + 0xa02c00) 543#define IWL50_SCD_BASE (PRPH_BASE + 0xa02c00)
277 544
278#define IWL50_SCD_SRAM_BASE_ADDR (IWL50_SCD_BASE + 0x0) 545#define IWL50_SCD_SRAM_BASE_ADDR (IWL50_SCD_BASE + 0x0)
@@ -287,4 +554,6 @@
287#define IWL50_SCD_INTERRUPT_MASK (IWL50_SCD_BASE + 0x108) 554#define IWL50_SCD_INTERRUPT_MASK (IWL50_SCD_BASE + 0x108)
288#define IWL50_SCD_QUEUE_STATUS_BITS(x) (IWL50_SCD_BASE + 0x10c + (x) * 4) 555#define IWL50_SCD_QUEUE_STATUS_BITS(x) (IWL50_SCD_BASE + 0x10c + (x) * 4)
289 556
557/*********************** END TX SCHEDULER *************************************/
558
290#endif /* __iwl_prph_h__ */ 559#endif /* __iwl_prph_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-rfkill.c b/drivers/net/wireless/iwlwifi/iwl-rfkill.c
index 5980a5621cb8..e5e5846e9f25 100644
--- a/drivers/net/wireless/iwlwifi/iwl-rfkill.c
+++ b/drivers/net/wireless/iwlwifi/iwl-rfkill.c
@@ -33,7 +33,7 @@
33#include <net/mac80211.h> 33#include <net/mac80211.h>
34 34
35#include "iwl-eeprom.h" 35#include "iwl-eeprom.h"
36#include "iwl-4965.h" 36#include "iwl-dev.h"
37#include "iwl-core.h" 37#include "iwl-core.h"
38#include "iwl-helpers.h" 38#include "iwl-helpers.h"
39 39
@@ -44,28 +44,31 @@ static int iwl_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
44 struct iwl_priv *priv = data; 44 struct iwl_priv *priv = data;
45 int err = 0; 45 int err = 0;
46 46
47 if (!priv->rfkill_mngr.rfkill) 47 if (!priv->rfkill)
48 return 0; 48 return 0;
49 49
50 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 50 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
51 return 0; 51 return 0;
52 52
53 IWL_DEBUG_RF_KILL("we recieved soft RFKILL set to state %d\n", state); 53 IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
54 mutex_lock(&priv->mutex); 54 mutex_lock(&priv->mutex);
55 55
56 switch (state) { 56 switch (state) {
57 case RFKILL_STATE_ON: 57 case RFKILL_STATE_UNBLOCKED:
58 priv->cfg->ops->lib->radio_kill_sw(priv, 0); 58 if (iwl_is_rfkill_hw(priv)) {
59 /* if HW rf-kill is set dont allow ON state */
60 if (iwl_is_rfkill(priv))
61 err = -EBUSY; 59 err = -EBUSY;
60 goto out_unlock;
61 }
62 iwl_radio_kill_sw_enable_radio(priv);
62 break; 63 break;
63 case RFKILL_STATE_OFF: 64 case RFKILL_STATE_SOFT_BLOCKED:
64 priv->cfg->ops->lib->radio_kill_sw(priv, 1); 65 iwl_radio_kill_sw_disable_radio(priv);
65 if (!iwl_is_rfkill(priv)) 66 break;
66 err = -EBUSY; 67 default:
68 IWL_WARNING("we recieved unexpected RFKILL state %d\n", state);
67 break; 69 break;
68 } 70 }
71out_unlock:
69 mutex_unlock(&priv->mutex); 72 mutex_unlock(&priv->mutex);
70 73
71 return err; 74 return err;
@@ -79,64 +82,35 @@ int iwl_rfkill_init(struct iwl_priv *priv)
79 BUG_ON(device == NULL); 82 BUG_ON(device == NULL);
80 83
81 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n"); 84 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
82 priv->rfkill_mngr.rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN); 85 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
83 if (!priv->rfkill_mngr.rfkill) { 86 if (!priv->rfkill) {
84 IWL_ERROR("Unable to allocate rfkill device.\n"); 87 IWL_ERROR("Unable to allocate rfkill device.\n");
85 ret = -ENOMEM; 88 ret = -ENOMEM;
86 goto error; 89 goto error;
87 } 90 }
88 91
89 priv->rfkill_mngr.rfkill->name = priv->cfg->name; 92 priv->rfkill->name = priv->cfg->name;
90 priv->rfkill_mngr.rfkill->data = priv; 93 priv->rfkill->data = priv;
91 priv->rfkill_mngr.rfkill->state = RFKILL_STATE_ON; 94 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
92 priv->rfkill_mngr.rfkill->toggle_radio = iwl_rfkill_soft_rf_kill; 95 priv->rfkill->toggle_radio = iwl_rfkill_soft_rf_kill;
93 priv->rfkill_mngr.rfkill->user_claim_unsupported = 1; 96 priv->rfkill->user_claim_unsupported = 1;
94 97
95 priv->rfkill_mngr.rfkill->dev.class->suspend = NULL; 98 priv->rfkill->dev.class->suspend = NULL;
96 priv->rfkill_mngr.rfkill->dev.class->resume = NULL; 99 priv->rfkill->dev.class->resume = NULL;
97 100
98 priv->rfkill_mngr.input_dev = input_allocate_device(); 101 ret = rfkill_register(priv->rfkill);
99 if (!priv->rfkill_mngr.input_dev) {
100 IWL_ERROR("Unable to allocate rfkill input device.\n");
101 ret = -ENOMEM;
102 goto freed_rfkill;
103 }
104
105 priv->rfkill_mngr.input_dev->name = priv->cfg->name;
106 priv->rfkill_mngr.input_dev->phys = wiphy_name(priv->hw->wiphy);
107 priv->rfkill_mngr.input_dev->id.bustype = BUS_HOST;
108 priv->rfkill_mngr.input_dev->id.vendor = priv->pci_dev->vendor;
109 priv->rfkill_mngr.input_dev->dev.parent = device;
110 priv->rfkill_mngr.input_dev->evbit[0] = BIT(EV_KEY);
111 set_bit(KEY_WLAN, priv->rfkill_mngr.input_dev->keybit);
112
113 ret = rfkill_register(priv->rfkill_mngr.rfkill);
114 if (ret) { 102 if (ret) {
115 IWL_ERROR("Unable to register rfkill: %d\n", ret); 103 IWL_ERROR("Unable to register rfkill: %d\n", ret);
116 goto free_input_dev; 104 goto free_rfkill;
117 }
118
119 ret = input_register_device(priv->rfkill_mngr.input_dev);
120 if (ret) {
121 IWL_ERROR("Unable to register rfkill input device: %d\n", ret);
122 goto unregister_rfkill;
123 } 105 }
124 106
125 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n"); 107 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
126 return ret; 108 return ret;
127 109
128unregister_rfkill: 110free_rfkill:
129 rfkill_unregister(priv->rfkill_mngr.rfkill); 111 if (priv->rfkill != NULL)
130 priv->rfkill_mngr.rfkill = NULL; 112 rfkill_free(priv->rfkill);
131 113 priv->rfkill = NULL;
132free_input_dev:
133 input_free_device(priv->rfkill_mngr.input_dev);
134 priv->rfkill_mngr.input_dev = NULL;
135
136freed_rfkill:
137 if (priv->rfkill_mngr.rfkill != NULL)
138 rfkill_free(priv->rfkill_mngr.rfkill);
139 priv->rfkill_mngr.rfkill = NULL;
140 114
141error: 115error:
142 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n"); 116 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
@@ -147,27 +121,27 @@ EXPORT_SYMBOL(iwl_rfkill_init);
147void iwl_rfkill_unregister(struct iwl_priv *priv) 121void iwl_rfkill_unregister(struct iwl_priv *priv)
148{ 122{
149 123
150 if (priv->rfkill_mngr.input_dev) 124 if (priv->rfkill)
151 input_unregister_device(priv->rfkill_mngr.input_dev); 125 rfkill_unregister(priv->rfkill);
152 126
153 if (priv->rfkill_mngr.rfkill) 127 priv->rfkill = NULL;
154 rfkill_unregister(priv->rfkill_mngr.rfkill);
155
156 priv->rfkill_mngr.input_dev = NULL;
157 priv->rfkill_mngr.rfkill = NULL;
158} 128}
159EXPORT_SYMBOL(iwl_rfkill_unregister); 129EXPORT_SYMBOL(iwl_rfkill_unregister);
160 130
161/* set rf-kill to the right state. */ 131/* set rf-kill to the right state. */
162void iwl_rfkill_set_hw_state(struct iwl_priv *priv) 132void iwl_rfkill_set_hw_state(struct iwl_priv *priv)
163{ 133{
134 if (!priv->rfkill)
135 return;
164 136
165 if (!priv->rfkill_mngr.rfkill) 137 if (iwl_is_rfkill_hw(priv)) {
138 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
166 return; 139 return;
140 }
167 141
168 if (!iwl_is_rfkill(priv)) 142 if (!iwl_is_rfkill_sw(priv))
169 priv->rfkill_mngr.rfkill->state = RFKILL_STATE_ON; 143 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
170 else 144 else
171 priv->rfkill_mngr.rfkill->state = RFKILL_STATE_OFF; 145 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
172} 146}
173EXPORT_SYMBOL(iwl_rfkill_set_hw_state); 147EXPORT_SYMBOL(iwl_rfkill_set_hw_state);
diff --git a/drivers/net/wireless/iwlwifi/iwl-rfkill.h b/drivers/net/wireless/iwlwifi/iwl-rfkill.h
index a7f04b855403..402fd4c781da 100644
--- a/drivers/net/wireless/iwlwifi/iwl-rfkill.h
+++ b/drivers/net/wireless/iwlwifi/iwl-rfkill.h
@@ -31,14 +31,8 @@
31struct iwl_priv; 31struct iwl_priv;
32 32
33#include <linux/rfkill.h> 33#include <linux/rfkill.h>
34#include <linux/input.h>
35
36 34
37#ifdef CONFIG_IWLWIFI_RFKILL 35#ifdef CONFIG_IWLWIFI_RFKILL
38struct iwl_rfkill_mngr {
39 struct rfkill *rfkill;
40 struct input_dev *input_dev;
41};
42 36
43void iwl_rfkill_set_hw_state(struct iwl_priv *priv); 37void iwl_rfkill_set_hw_state(struct iwl_priv *priv);
44void iwl_rfkill_unregister(struct iwl_priv *priv); 38void iwl_rfkill_unregister(struct iwl_priv *priv);
diff --git a/drivers/net/wireless/iwlwifi/iwl-rx.c b/drivers/net/wireless/iwlwifi/iwl-rx.c
new file mode 100644
index 000000000000..e2d9afba38a5
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-rx.c
@@ -0,0 +1,1321 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#include <linux/etherdevice.h>
31#include <net/mac80211.h>
32#include <asm/unaligned.h>
33#include "iwl-eeprom.h"
34#include "iwl-dev.h"
35#include "iwl-core.h"
36#include "iwl-sta.h"
37#include "iwl-io.h"
38#include "iwl-calib.h"
39#include "iwl-helpers.h"
40/************************** RX-FUNCTIONS ****************************/
41/*
42 * Rx theory of operation
43 *
44 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
45 * each of which point to Receive Buffers to be filled by the NIC. These get
46 * used not only for Rx frames, but for any command response or notification
47 * from the NIC. The driver and NIC manage the Rx buffers by means
48 * of indexes into the circular buffer.
49 *
50 * Rx Queue Indexes
51 * The host/firmware share two index registers for managing the Rx buffers.
52 *
53 * The READ index maps to the first position that the firmware may be writing
54 * to -- the driver can read up to (but not including) this position and get
55 * good data.
56 * The READ index is managed by the firmware once the card is enabled.
57 *
58 * The WRITE index maps to the last position the driver has read from -- the
59 * position preceding WRITE is the last slot the firmware can place a packet.
60 *
61 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
62 * WRITE = READ.
63 *
64 * During initialization, the host sets up the READ queue position to the first
65 * INDEX position, and WRITE to the last (READ - 1 wrapped)
66 *
67 * When the firmware places a packet in a buffer, it will advance the READ index
68 * and fire the RX interrupt. The driver can then query the READ index and
69 * process as many packets as possible, moving the WRITE index forward as it
70 * resets the Rx queue buffers with new memory.
71 *
72 * The management in the driver is as follows:
73 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
74 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
75 * to replenish the iwl->rxq->rx_free.
76 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
77 * iwl->rxq is replenished and the READ INDEX is updated (updating the
78 * 'processed' and 'read' driver indexes as well)
79 * + A received packet is processed and handed to the kernel network stack,
80 * detached from the iwl->rxq. The driver 'processed' index is updated.
81 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
82 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
83 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
84 * were enough free buffers and RX_STALLED is set it is cleared.
85 *
86 *
87 * Driver sequence:
88 *
89 * iwl_rx_queue_alloc() Allocates rx_free
90 * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
91 * iwl_rx_queue_restock
92 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
93 * queue, updates firmware pointers, and updates
94 * the WRITE index. If insufficient rx_free buffers
95 * are available, schedules iwl_rx_replenish
96 *
97 * -- enable interrupts --
98 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
99 * READ INDEX, detaching the SKB from the pool.
100 * Moves the packet buffer from queue to rx_used.
101 * Calls iwl_rx_queue_restock to refill any empty
102 * slots.
103 * ...
104 *
105 */
106
107/**
108 * iwl_rx_queue_space - Return number of free slots available in queue.
109 */
110int iwl_rx_queue_space(const struct iwl_rx_queue *q)
111{
112 int s = q->read - q->write;
113 if (s <= 0)
114 s += RX_QUEUE_SIZE;
115 /* keep some buffer to not confuse full and empty queue */
116 s -= 2;
117 if (s < 0)
118 s = 0;
119 return s;
120}
121EXPORT_SYMBOL(iwl_rx_queue_space);
122
123/**
124 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
125 */
126int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
127{
128 u32 reg = 0;
129 int ret = 0;
130 unsigned long flags;
131
132 spin_lock_irqsave(&q->lock, flags);
133
134 if (q->need_update == 0)
135 goto exit_unlock;
136
137 /* If power-saving is in use, make sure device is awake */
138 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
139 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
140
141 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
142 iwl_set_bit(priv, CSR_GP_CNTRL,
143 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
144 goto exit_unlock;
145 }
146
147 ret = iwl_grab_nic_access(priv);
148 if (ret)
149 goto exit_unlock;
150
151 /* Device expects a multiple of 8 */
152 iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
153 q->write & ~0x7);
154 iwl_release_nic_access(priv);
155
156 /* Else device is assumed to be awake */
157 } else
158 /* Device expects a multiple of 8 */
159 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
160
161
162 q->need_update = 0;
163
164 exit_unlock:
165 spin_unlock_irqrestore(&q->lock, flags);
166 return ret;
167}
168EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
169/**
170 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
171 */
172static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv,
173 dma_addr_t dma_addr)
174{
175 return cpu_to_le32((u32)(dma_addr >> 8));
176}
177
178/**
179 * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
180 *
181 * If there are slots in the RX queue that need to be restocked,
182 * and we have free pre-allocated buffers, fill the ranks as much
183 * as we can, pulling from rx_free.
184 *
185 * This moves the 'write' index forward to catch up with 'processed', and
186 * also updates the memory address in the firmware to reference the new
187 * target buffer.
188 */
189int iwl_rx_queue_restock(struct iwl_priv *priv)
190{
191 struct iwl_rx_queue *rxq = &priv->rxq;
192 struct list_head *element;
193 struct iwl_rx_mem_buffer *rxb;
194 unsigned long flags;
195 int write;
196 int ret = 0;
197
198 spin_lock_irqsave(&rxq->lock, flags);
199 write = rxq->write & ~0x7;
200 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
201 /* Get next free Rx buffer, remove from free list */
202 element = rxq->rx_free.next;
203 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
204 list_del(element);
205
206 /* Point to Rx buffer via next RBD in circular buffer */
207 rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->dma_addr);
208 rxq->queue[rxq->write] = rxb;
209 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
210 rxq->free_count--;
211 }
212 spin_unlock_irqrestore(&rxq->lock, flags);
213 /* If the pre-allocated buffer pool is dropping low, schedule to
214 * refill it */
215 if (rxq->free_count <= RX_LOW_WATERMARK)
216 queue_work(priv->workqueue, &priv->rx_replenish);
217
218
219 /* If we've added more space for the firmware to place data, tell it.
220 * Increment device's write pointer in multiples of 8. */
221 if ((write != (rxq->write & ~0x7))
222 || (abs(rxq->write - rxq->read) > 7)) {
223 spin_lock_irqsave(&rxq->lock, flags);
224 rxq->need_update = 1;
225 spin_unlock_irqrestore(&rxq->lock, flags);
226 ret = iwl_rx_queue_update_write_ptr(priv, rxq);
227 }
228
229 return ret;
230}
231EXPORT_SYMBOL(iwl_rx_queue_restock);
232
233
234/**
235 * iwl_rx_replenish - Move all used packet from rx_used to rx_free
236 *
237 * When moving to rx_free an SKB is allocated for the slot.
238 *
239 * Also restock the Rx queue via iwl_rx_queue_restock.
240 * This is called as a scheduled work item (except for during initialization)
241 */
242void iwl_rx_allocate(struct iwl_priv *priv)
243{
244 struct iwl_rx_queue *rxq = &priv->rxq;
245 struct list_head *element;
246 struct iwl_rx_mem_buffer *rxb;
247 unsigned long flags;
248 spin_lock_irqsave(&rxq->lock, flags);
249 while (!list_empty(&rxq->rx_used)) {
250 element = rxq->rx_used.next;
251 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
252
253 /* Alloc a new receive buffer */
254 rxb->skb = alloc_skb(priv->hw_params.rx_buf_size,
255 __GFP_NOWARN | GFP_ATOMIC);
256 if (!rxb->skb) {
257 if (net_ratelimit())
258 printk(KERN_CRIT DRV_NAME
259 ": Can not allocate SKB buffers\n");
260 /* We don't reschedule replenish work here -- we will
261 * call the restock method and if it still needs
262 * more buffers it will schedule replenish */
263 break;
264 }
265 priv->alloc_rxb_skb++;
266 list_del(element);
267
268 /* Get physical address of RB/SKB */
269 rxb->dma_addr =
270 pci_map_single(priv->pci_dev, rxb->skb->data,
271 priv->hw_params.rx_buf_size, PCI_DMA_FROMDEVICE);
272 list_add_tail(&rxb->list, &rxq->rx_free);
273 rxq->free_count++;
274 }
275 spin_unlock_irqrestore(&rxq->lock, flags);
276}
277EXPORT_SYMBOL(iwl_rx_allocate);
278
279void iwl_rx_replenish(struct iwl_priv *priv)
280{
281 unsigned long flags;
282
283 iwl_rx_allocate(priv);
284
285 spin_lock_irqsave(&priv->lock, flags);
286 iwl_rx_queue_restock(priv);
287 spin_unlock_irqrestore(&priv->lock, flags);
288}
289EXPORT_SYMBOL(iwl_rx_replenish);
290
291
292/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
293 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
294 * This free routine walks the list of POOL entries and if SKB is set to
295 * non NULL it is unmapped and freed
296 */
297void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
298{
299 int i;
300 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
301 if (rxq->pool[i].skb != NULL) {
302 pci_unmap_single(priv->pci_dev,
303 rxq->pool[i].dma_addr,
304 priv->hw_params.rx_buf_size,
305 PCI_DMA_FROMDEVICE);
306 dev_kfree_skb(rxq->pool[i].skb);
307 }
308 }
309
310 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
311 rxq->dma_addr);
312 rxq->bd = NULL;
313}
314EXPORT_SYMBOL(iwl_rx_queue_free);
315
316int iwl_rx_queue_alloc(struct iwl_priv *priv)
317{
318 struct iwl_rx_queue *rxq = &priv->rxq;
319 struct pci_dev *dev = priv->pci_dev;
320 int i;
321
322 spin_lock_init(&rxq->lock);
323 INIT_LIST_HEAD(&rxq->rx_free);
324 INIT_LIST_HEAD(&rxq->rx_used);
325
326 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
327 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
328 if (!rxq->bd)
329 return -ENOMEM;
330
331 /* Fill the rx_used queue with _all_ of the Rx buffers */
332 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
333 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
334
335 /* Set us so that we have processed and used all buffers, but have
336 * not restocked the Rx queue with fresh buffers */
337 rxq->read = rxq->write = 0;
338 rxq->free_count = 0;
339 rxq->need_update = 0;
340 return 0;
341}
342EXPORT_SYMBOL(iwl_rx_queue_alloc);
343
344void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
345{
346 unsigned long flags;
347 int i;
348 spin_lock_irqsave(&rxq->lock, flags);
349 INIT_LIST_HEAD(&rxq->rx_free);
350 INIT_LIST_HEAD(&rxq->rx_used);
351 /* Fill the rx_used queue with _all_ of the Rx buffers */
352 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
353 /* In the reset function, these buffers may have been allocated
354 * to an SKB, so we need to unmap and free potential storage */
355 if (rxq->pool[i].skb != NULL) {
356 pci_unmap_single(priv->pci_dev,
357 rxq->pool[i].dma_addr,
358 priv->hw_params.rx_buf_size,
359 PCI_DMA_FROMDEVICE);
360 priv->alloc_rxb_skb--;
361 dev_kfree_skb(rxq->pool[i].skb);
362 rxq->pool[i].skb = NULL;
363 }
364 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
365 }
366
367 /* Set us so that we have processed and used all buffers, but have
368 * not restocked the Rx queue with fresh buffers */
369 rxq->read = rxq->write = 0;
370 rxq->free_count = 0;
371 spin_unlock_irqrestore(&rxq->lock, flags);
372}
373EXPORT_SYMBOL(iwl_rx_queue_reset);
374
375int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
376{
377 int ret;
378 unsigned long flags;
379 unsigned int rb_size;
380
381 spin_lock_irqsave(&priv->lock, flags);
382 ret = iwl_grab_nic_access(priv);
383 if (ret) {
384 spin_unlock_irqrestore(&priv->lock, flags);
385 return ret;
386 }
387
388 if (priv->cfg->mod_params->amsdu_size_8K)
389 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
390 else
391 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
392
393 /* Stop Rx DMA */
394 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
395
396 /* Reset driver's Rx queue write index */
397 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
398
399 /* Tell device where to find RBD circular buffer in DRAM */
400 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
401 rxq->dma_addr >> 8);
402
403 /* Tell device where in DRAM to update its Rx status */
404 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
405 (priv->shared_phys + priv->rb_closed_offset) >> 4);
406
407 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
408 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
409 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
410 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
411 rb_size |
412 /* 0x10 << 4 | */
413 (RX_QUEUE_SIZE_LOG <<
414 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
415
416 /*
417 * iwl_write32(priv,CSR_INT_COAL_REG,0);
418 */
419
420 iwl_release_nic_access(priv);
421 spin_unlock_irqrestore(&priv->lock, flags);
422
423 return 0;
424}
425
426int iwl_rxq_stop(struct iwl_priv *priv)
427{
428 int ret;
429 unsigned long flags;
430
431 spin_lock_irqsave(&priv->lock, flags);
432 ret = iwl_grab_nic_access(priv);
433 if (unlikely(ret)) {
434 spin_unlock_irqrestore(&priv->lock, flags);
435 return ret;
436 }
437
438 /* stop Rx DMA */
439 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
440 ret = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
441 (1 << 24), 1000);
442 if (ret < 0)
443 IWL_ERROR("Can't stop Rx DMA.\n");
444
445 iwl_release_nic_access(priv);
446 spin_unlock_irqrestore(&priv->lock, flags);
447
448 return 0;
449}
450EXPORT_SYMBOL(iwl_rxq_stop);
451
452void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
453 struct iwl_rx_mem_buffer *rxb)
454
455{
456 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
457 struct iwl4965_missed_beacon_notif *missed_beacon;
458
459 missed_beacon = &pkt->u.missed_beacon;
460 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
461 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
462 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
463 le32_to_cpu(missed_beacon->total_missed_becons),
464 le32_to_cpu(missed_beacon->num_recvd_beacons),
465 le32_to_cpu(missed_beacon->num_expected_beacons));
466 if (!test_bit(STATUS_SCANNING, &priv->status))
467 iwl_init_sensitivity(priv);
468 }
469}
470EXPORT_SYMBOL(iwl_rx_missed_beacon_notif);
471
472int iwl_rx_agg_start(struct iwl_priv *priv, const u8 *addr, int tid, u16 ssn)
473{
474 unsigned long flags;
475 int sta_id;
476
477 sta_id = iwl_find_station(priv, addr);
478 if (sta_id == IWL_INVALID_STATION)
479 return -ENXIO;
480
481 spin_lock_irqsave(&priv->sta_lock, flags);
482 priv->stations[sta_id].sta.station_flags_msk = 0;
483 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
484 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
485 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
486 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
487 spin_unlock_irqrestore(&priv->sta_lock, flags);
488
489 return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
490 CMD_ASYNC);
491}
492EXPORT_SYMBOL(iwl_rx_agg_start);
493
494int iwl_rx_agg_stop(struct iwl_priv *priv, const u8 *addr, int tid)
495{
496 unsigned long flags;
497 int sta_id;
498
499 sta_id = iwl_find_station(priv, addr);
500 if (sta_id == IWL_INVALID_STATION)
501 return -ENXIO;
502
503 spin_lock_irqsave(&priv->sta_lock, flags);
504 priv->stations[sta_id].sta.station_flags_msk = 0;
505 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
506 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
507 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
508 spin_unlock_irqrestore(&priv->sta_lock, flags);
509
510 return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
511 CMD_ASYNC);
512}
513EXPORT_SYMBOL(iwl_rx_agg_stop);
514
515
516/* Calculate noise level, based on measurements during network silence just
517 * before arriving beacon. This measurement can be done only if we know
518 * exactly when to expect beacons, therefore only when we're associated. */
519static void iwl_rx_calc_noise(struct iwl_priv *priv)
520{
521 struct statistics_rx_non_phy *rx_info
522 = &(priv->statistics.rx.general);
523 int num_active_rx = 0;
524 int total_silence = 0;
525 int bcn_silence_a =
526 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
527 int bcn_silence_b =
528 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
529 int bcn_silence_c =
530 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
531
532 if (bcn_silence_a) {
533 total_silence += bcn_silence_a;
534 num_active_rx++;
535 }
536 if (bcn_silence_b) {
537 total_silence += bcn_silence_b;
538 num_active_rx++;
539 }
540 if (bcn_silence_c) {
541 total_silence += bcn_silence_c;
542 num_active_rx++;
543 }
544
545 /* Average among active antennas */
546 if (num_active_rx)
547 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
548 else
549 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
550
551 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
552 bcn_silence_a, bcn_silence_b, bcn_silence_c,
553 priv->last_rx_noise);
554}
555
556#define REG_RECALIB_PERIOD (60)
557
558void iwl_rx_statistics(struct iwl_priv *priv,
559 struct iwl_rx_mem_buffer *rxb)
560{
561 int change;
562 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
563
564 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
565 (int)sizeof(priv->statistics), pkt->len);
566
567 change = ((priv->statistics.general.temperature !=
568 pkt->u.stats.general.temperature) ||
569 ((priv->statistics.flag &
570 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
571 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
572
573 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
574
575 set_bit(STATUS_STATISTICS, &priv->status);
576
577 /* Reschedule the statistics timer to occur in
578 * REG_RECALIB_PERIOD seconds to ensure we get a
579 * thermal update even if the uCode doesn't give
580 * us one */
581 mod_timer(&priv->statistics_periodic, jiffies +
582 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
583
584 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
585 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
586 iwl_rx_calc_noise(priv);
587 queue_work(priv->workqueue, &priv->run_time_calib_work);
588 }
589
590 iwl_leds_background(priv);
591
592 if (priv->cfg->ops->lib->temperature && change)
593 priv->cfg->ops->lib->temperature(priv);
594}
595EXPORT_SYMBOL(iwl_rx_statistics);
596
597#define PERFECT_RSSI (-20) /* dBm */
598#define WORST_RSSI (-95) /* dBm */
599#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
600
601/* Calculate an indication of rx signal quality (a percentage, not dBm!).
602 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
603 * about formulas used below. */
604static int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm)
605{
606 int sig_qual;
607 int degradation = PERFECT_RSSI - rssi_dbm;
608
609 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
610 * as indicator; formula is (signal dbm - noise dbm).
611 * SNR at or above 40 is a great signal (100%).
612 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
613 * Weakest usable signal is usually 10 - 15 dB SNR. */
614 if (noise_dbm) {
615 if (rssi_dbm - noise_dbm >= 40)
616 return 100;
617 else if (rssi_dbm < noise_dbm)
618 return 0;
619 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
620
621 /* Else use just the signal level.
622 * This formula is a least squares fit of data points collected and
623 * compared with a reference system that had a percentage (%) display
624 * for signal quality. */
625 } else
626 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
627 (15 * RSSI_RANGE + 62 * degradation)) /
628 (RSSI_RANGE * RSSI_RANGE);
629
630 if (sig_qual > 100)
631 sig_qual = 100;
632 else if (sig_qual < 1)
633 sig_qual = 0;
634
635 return sig_qual;
636}
637
638#ifdef CONFIG_IWLWIFI_DEBUG
639
640/**
641 * iwl_dbg_report_frame - dump frame to syslog during debug sessions
642 *
643 * You may hack this function to show different aspects of received frames,
644 * including selective frame dumps.
645 * group100 parameter selects whether to show 1 out of 100 good frames.
646 *
647 * TODO: This was originally written for 3945, need to audit for
648 * proper operation with 4965.
649 */
650static void iwl_dbg_report_frame(struct iwl_priv *priv,
651 struct iwl_rx_packet *pkt,
652 struct ieee80211_hdr *header, int group100)
653{
654 u32 to_us;
655 u32 print_summary = 0;
656 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
657 u32 hundred = 0;
658 u32 dataframe = 0;
659 __le16 fc;
660 u16 seq_ctl;
661 u16 channel;
662 u16 phy_flags;
663 int rate_sym;
664 u16 length;
665 u16 status;
666 u16 bcn_tmr;
667 u32 tsf_low;
668 u64 tsf;
669 u8 rssi;
670 u8 agc;
671 u16 sig_avg;
672 u16 noise_diff;
673 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
674 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
675 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
676 u8 *data = IWL_RX_DATA(pkt);
677
678 if (likely(!(priv->debug_level & IWL_DL_RX)))
679 return;
680
681 /* MAC header */
682 fc = header->frame_control;
683 seq_ctl = le16_to_cpu(header->seq_ctrl);
684
685 /* metadata */
686 channel = le16_to_cpu(rx_hdr->channel);
687 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
688 rate_sym = rx_hdr->rate;
689 length = le16_to_cpu(rx_hdr->len);
690
691 /* end-of-frame status and timestamp */
692 status = le32_to_cpu(rx_end->status);
693 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
694 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
695 tsf = le64_to_cpu(rx_end->timestamp);
696
697 /* signal statistics */
698 rssi = rx_stats->rssi;
699 agc = rx_stats->agc;
700 sig_avg = le16_to_cpu(rx_stats->sig_avg);
701 noise_diff = le16_to_cpu(rx_stats->noise_diff);
702
703 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
704
705 /* if data frame is to us and all is good,
706 * (optionally) print summary for only 1 out of every 100 */
707 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
708 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
709 dataframe = 1;
710 if (!group100)
711 print_summary = 1; /* print each frame */
712 else if (priv->framecnt_to_us < 100) {
713 priv->framecnt_to_us++;
714 print_summary = 0;
715 } else {
716 priv->framecnt_to_us = 0;
717 print_summary = 1;
718 hundred = 1;
719 }
720 } else {
721 /* print summary for all other frames */
722 print_summary = 1;
723 }
724
725 if (print_summary) {
726 char *title;
727 int rate_idx;
728 u32 bitrate;
729
730 if (hundred)
731 title = "100Frames";
732 else if (ieee80211_has_retry(fc))
733 title = "Retry";
734 else if (ieee80211_is_assoc_resp(fc))
735 title = "AscRsp";
736 else if (ieee80211_is_reassoc_resp(fc))
737 title = "RasRsp";
738 else if (ieee80211_is_probe_resp(fc)) {
739 title = "PrbRsp";
740 print_dump = 1; /* dump frame contents */
741 } else if (ieee80211_is_beacon(fc)) {
742 title = "Beacon";
743 print_dump = 1; /* dump frame contents */
744 } else if (ieee80211_is_atim(fc))
745 title = "ATIM";
746 else if (ieee80211_is_auth(fc))
747 title = "Auth";
748 else if (ieee80211_is_deauth(fc))
749 title = "DeAuth";
750 else if (ieee80211_is_disassoc(fc))
751 title = "DisAssoc";
752 else
753 title = "Frame";
754
755 rate_idx = iwl_hwrate_to_plcp_idx(rate_sym);
756 if (unlikely(rate_idx == -1))
757 bitrate = 0;
758 else
759 bitrate = iwl_rates[rate_idx].ieee / 2;
760
761 /* print frame summary.
762 * MAC addresses show just the last byte (for brevity),
763 * but you can hack it to show more, if you'd like to. */
764 if (dataframe)
765 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
766 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
767 title, le16_to_cpu(fc), header->addr1[5],
768 length, rssi, channel, bitrate);
769 else {
770 /* src/dst addresses assume managed mode */
771 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
772 "src=0x%02x, rssi=%u, tim=%lu usec, "
773 "phy=0x%02x, chnl=%d\n",
774 title, le16_to_cpu(fc), header->addr1[5],
775 header->addr3[5], rssi,
776 tsf_low - priv->scan_start_tsf,
777 phy_flags, channel);
778 }
779 }
780 if (print_dump)
781 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
782}
783#else
784static inline void iwl_dbg_report_frame(struct iwl_priv *priv,
785 struct iwl_rx_packet *pkt,
786 struct ieee80211_hdr *header,
787 int group100)
788{
789}
790#endif
791
792static void iwl_add_radiotap(struct iwl_priv *priv,
793 struct sk_buff *skb,
794 struct iwl4965_rx_phy_res *rx_start,
795 struct ieee80211_rx_status *stats,
796 u32 ampdu_status)
797{
798 s8 signal = stats->signal;
799 s8 noise = 0;
800 int rate = stats->rate_idx;
801 u64 tsf = stats->mactime;
802 __le16 antenna;
803 __le16 phy_flags_hw = rx_start->phy_flags;
804 struct iwl4965_rt_rx_hdr {
805 struct ieee80211_radiotap_header rt_hdr;
806 __le64 rt_tsf; /* TSF */
807 u8 rt_flags; /* radiotap packet flags */
808 u8 rt_rate; /* rate in 500kb/s */
809 __le16 rt_channelMHz; /* channel in MHz */
810 __le16 rt_chbitmask; /* channel bitfield */
811 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
812 s8 rt_dbmnoise;
813 u8 rt_antenna; /* antenna number */
814 } __attribute__ ((packed)) *iwl4965_rt;
815
816 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
817 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
818 if (net_ratelimit())
819 printk(KERN_ERR "not enough headroom [%d] for "
820 "radiotap head [%zd]\n",
821 skb_headroom(skb), sizeof(*iwl4965_rt));
822 return;
823 }
824
825 /* put radiotap header in front of 802.11 header and data */
826 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
827
828 /* initialise radiotap header */
829 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
830 iwl4965_rt->rt_hdr.it_pad = 0;
831
832 /* total header + data */
833 put_unaligned_le16(sizeof(*iwl4965_rt), &iwl4965_rt->rt_hdr.it_len);
834
835 /* Indicate all the fields we add to the radiotap header */
836 put_unaligned_le32((1 << IEEE80211_RADIOTAP_TSFT) |
837 (1 << IEEE80211_RADIOTAP_FLAGS) |
838 (1 << IEEE80211_RADIOTAP_RATE) |
839 (1 << IEEE80211_RADIOTAP_CHANNEL) |
840 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
841 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
842 (1 << IEEE80211_RADIOTAP_ANTENNA),
843 &(iwl4965_rt->rt_hdr.it_present));
844
845 /* Zero the flags, we'll add to them as we go */
846 iwl4965_rt->rt_flags = 0;
847
848 put_unaligned_le64(tsf, &iwl4965_rt->rt_tsf);
849
850 iwl4965_rt->rt_dbmsignal = signal;
851 iwl4965_rt->rt_dbmnoise = noise;
852
853 /* Convert the channel frequency and set the flags */
854 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
855 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
856 put_unaligned_le16(IEEE80211_CHAN_OFDM | IEEE80211_CHAN_5GHZ,
857 &iwl4965_rt->rt_chbitmask);
858 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
859 put_unaligned_le16(IEEE80211_CHAN_CCK | IEEE80211_CHAN_2GHZ,
860 &iwl4965_rt->rt_chbitmask);
861 else /* 802.11g */
862 put_unaligned_le16(IEEE80211_CHAN_OFDM | IEEE80211_CHAN_2GHZ,
863 &iwl4965_rt->rt_chbitmask);
864
865 if (rate == -1)
866 iwl4965_rt->rt_rate = 0;
867 else
868 iwl4965_rt->rt_rate = iwl_rates[rate].ieee;
869
870 /*
871 * "antenna number"
872 *
873 * It seems that the antenna field in the phy flags value
874 * is actually a bitfield. This is undefined by radiotap,
875 * it wants an actual antenna number but I always get "7"
876 * for most legacy frames I receive indicating that the
877 * same frame was received on all three RX chains.
878 *
879 * I think this field should be removed in favour of a
880 * new 802.11n radiotap field "RX chains" that is defined
881 * as a bitmask.
882 */
883 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
884 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
885
886 /* set the preamble flag if appropriate */
887 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
888 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
889
890 stats->flag |= RX_FLAG_RADIOTAP;
891}
892
893static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
894{
895 /* 0 - mgmt, 1 - cnt, 2 - data */
896 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
897 priv->rx_stats[idx].cnt++;
898 priv->rx_stats[idx].bytes += len;
899}
900
901/*
902 * returns non-zero if packet should be dropped
903 */
904static int iwl_set_decrypted_flag(struct iwl_priv *priv,
905 struct ieee80211_hdr *hdr,
906 u32 decrypt_res,
907 struct ieee80211_rx_status *stats)
908{
909 u16 fc = le16_to_cpu(hdr->frame_control);
910
911 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
912 return 0;
913
914 if (!(fc & IEEE80211_FCTL_PROTECTED))
915 return 0;
916
917 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
918 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
919 case RX_RES_STATUS_SEC_TYPE_TKIP:
920 /* The uCode has got a bad phase 1 Key, pushes the packet.
921 * Decryption will be done in SW. */
922 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
923 RX_RES_STATUS_BAD_KEY_TTAK)
924 break;
925
926 case RX_RES_STATUS_SEC_TYPE_WEP:
927 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
928 RX_RES_STATUS_BAD_ICV_MIC) {
929 /* bad ICV, the packet is destroyed since the
930 * decryption is inplace, drop it */
931 IWL_DEBUG_RX("Packet destroyed\n");
932 return -1;
933 }
934 case RX_RES_STATUS_SEC_TYPE_CCMP:
935 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
936 RX_RES_STATUS_DECRYPT_OK) {
937 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
938 stats->flag |= RX_FLAG_DECRYPTED;
939 }
940 break;
941
942 default:
943 break;
944 }
945 return 0;
946}
947
948static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
949{
950 u32 decrypt_out = 0;
951
952 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
953 RX_RES_STATUS_STATION_FOUND)
954 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
955 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
956
957 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
958
959 /* packet was not encrypted */
960 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
961 RX_RES_STATUS_SEC_TYPE_NONE)
962 return decrypt_out;
963
964 /* packet was encrypted with unknown alg */
965 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
966 RX_RES_STATUS_SEC_TYPE_ERR)
967 return decrypt_out;
968
969 /* decryption was not done in HW */
970 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
971 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
972 return decrypt_out;
973
974 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
975
976 case RX_RES_STATUS_SEC_TYPE_CCMP:
977 /* alg is CCM: check MIC only */
978 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
979 /* Bad MIC */
980 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
981 else
982 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
983
984 break;
985
986 case RX_RES_STATUS_SEC_TYPE_TKIP:
987 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
988 /* Bad TTAK */
989 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
990 break;
991 }
992 /* fall through if TTAK OK */
993 default:
994 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
995 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
996 else
997 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
998 break;
999 };
1000
1001 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
1002 decrypt_in, decrypt_out);
1003
1004 return decrypt_out;
1005}
1006
1007static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
1008 int include_phy,
1009 struct iwl_rx_mem_buffer *rxb,
1010 struct ieee80211_rx_status *stats)
1011{
1012 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1013 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
1014 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
1015 struct ieee80211_hdr *hdr;
1016 u16 len;
1017 __le32 *rx_end;
1018 unsigned int skblen;
1019 u32 ampdu_status;
1020 u32 ampdu_status_legacy;
1021
1022 if (!include_phy && priv->last_phy_res[0])
1023 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
1024
1025 if (!rx_start) {
1026 IWL_ERROR("MPDU frame without a PHY data\n");
1027 return;
1028 }
1029 if (include_phy) {
1030 hdr = (struct ieee80211_hdr *)((u8 *) &rx_start[1] +
1031 rx_start->cfg_phy_cnt);
1032
1033 len = le16_to_cpu(rx_start->byte_count);
1034
1035 rx_end = (__le32 *) ((u8 *) &pkt->u.raw[0] +
1036 sizeof(struct iwl4965_rx_phy_res) +
1037 rx_start->cfg_phy_cnt + len);
1038
1039 } else {
1040 struct iwl4965_rx_mpdu_res_start *amsdu =
1041 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
1042
1043 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
1044 sizeof(struct iwl4965_rx_mpdu_res_start));
1045 len = le16_to_cpu(amsdu->byte_count);
1046 rx_start->byte_count = amsdu->byte_count;
1047 rx_end = (__le32 *) (((u8 *) hdr) + len);
1048 }
1049
1050 ampdu_status = le32_to_cpu(*rx_end);
1051 skblen = ((u8 *) rx_end - (u8 *) &pkt->u.raw[0]) + sizeof(u32);
1052
1053 if (!include_phy) {
1054 /* New status scheme, need to translate */
1055 ampdu_status_legacy = ampdu_status;
1056 ampdu_status = iwl_translate_rx_status(priv, ampdu_status);
1057 }
1058
1059 /* start from MAC */
1060 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
1061 skb_put(rxb->skb, len); /* end where data ends */
1062
1063 /* We only process data packets if the interface is open */
1064 if (unlikely(!priv->is_open)) {
1065 IWL_DEBUG_DROP_LIMIT
1066 ("Dropping packet while interface is not open.\n");
1067 return;
1068 }
1069
1070 hdr = (struct ieee80211_hdr *)rxb->skb->data;
1071
1072 /* in case of HW accelerated crypto and bad decryption, drop */
1073 if (!priv->hw_params.sw_crypto &&
1074 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
1075 return;
1076
1077 if (priv->add_radiotap)
1078 iwl_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
1079
1080 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
1081 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
1082 priv->alloc_rxb_skb--;
1083 rxb->skb = NULL;
1084}
1085
1086/* Calc max signal level (dBm) among 3 possible receivers */
1087static int iwl_calc_rssi(struct iwl_priv *priv,
1088 struct iwl4965_rx_phy_res *rx_resp)
1089{
1090 /* data from PHY/DSP regarding signal strength, etc.,
1091 * contents are always there, not configurable by host. */
1092 struct iwl4965_rx_non_cfg_phy *ncphy =
1093 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
1094 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
1095 >> IWL_AGC_DB_POS;
1096
1097 u32 valid_antennae =
1098 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
1099 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
1100 u8 max_rssi = 0;
1101 u32 i;
1102
1103 /* Find max rssi among 3 possible receivers.
1104 * These values are measured by the digital signal processor (DSP).
1105 * They should stay fairly constant even as the signal strength varies,
1106 * if the radio's automatic gain control (AGC) is working right.
1107 * AGC value (see below) will provide the "interesting" info. */
1108 for (i = 0; i < 3; i++)
1109 if (valid_antennae & (1 << i))
1110 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
1111
1112 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1113 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
1114 max_rssi, agc);
1115
1116 /* dBm = max_rssi dB - agc dB - constant.
1117 * Higher AGC (higher radio gain) means lower signal. */
1118 return max_rssi - agc - IWL_RSSI_OFFSET;
1119}
1120
1121static void iwl_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
1122{
1123 unsigned long flags;
1124
1125 spin_lock_irqsave(&priv->sta_lock, flags);
1126 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
1127 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
1128 priv->stations[sta_id].sta.sta.modify_mask = 0;
1129 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1130 spin_unlock_irqrestore(&priv->sta_lock, flags);
1131
1132 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
1133}
1134
1135static void iwl_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
1136{
1137 /* FIXME: need locking over ps_status ??? */
1138 u8 sta_id = iwl_find_station(priv, addr);
1139
1140 if (sta_id != IWL_INVALID_STATION) {
1141 u8 sta_awake = priv->stations[sta_id].
1142 ps_status == STA_PS_STATUS_WAKE;
1143
1144 if (sta_awake && ps_bit)
1145 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
1146 else if (!sta_awake && !ps_bit) {
1147 iwl_sta_modify_ps_wake(priv, sta_id);
1148 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
1149 }
1150 }
1151}
1152
1153/* This is necessary only for a number of statistics, see the caller. */
1154static int iwl_is_network_packet(struct iwl_priv *priv,
1155 struct ieee80211_hdr *header)
1156{
1157 /* Filter incoming packets to determine if they are targeted toward
1158 * this network, discarding packets coming from ourselves */
1159 switch (priv->iw_mode) {
1160 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
1161 /* packets to our IBSS update information */
1162 return !compare_ether_addr(header->addr3, priv->bssid);
1163 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
1164 /* packets to our IBSS update information */
1165 return !compare_ether_addr(header->addr2, priv->bssid);
1166 default:
1167 return 1;
1168 }
1169}
1170
1171/* Called for REPLY_RX (legacy ABG frames), or
1172 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1173void iwl_rx_reply_rx(struct iwl_priv *priv,
1174 struct iwl_rx_mem_buffer *rxb)
1175{
1176 struct ieee80211_hdr *header;
1177 struct ieee80211_rx_status rx_status;
1178 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1179 /* Use phy data (Rx signal strength, etc.) contained within
1180 * this rx packet for legacy frames,
1181 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
1182 int include_phy = (pkt->hdr.cmd == REPLY_RX);
1183 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
1184 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
1185 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
1186 __le32 *rx_end;
1187 unsigned int len = 0;
1188 u16 fc;
1189 u8 network_packet;
1190
1191 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
1192 rx_status.freq =
1193 ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
1194 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
1195 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1196 rx_status.rate_idx =
1197 iwl_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
1198 if (rx_status.band == IEEE80211_BAND_5GHZ)
1199 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
1200
1201 rx_status.antenna = 0;
1202 rx_status.flag = 0;
1203 rx_status.flag |= RX_FLAG_TSFT;
1204
1205 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
1206 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
1207 rx_start->cfg_phy_cnt);
1208 return;
1209 }
1210
1211 if (!include_phy) {
1212 if (priv->last_phy_res[0])
1213 rx_start = (struct iwl4965_rx_phy_res *)
1214 &priv->last_phy_res[1];
1215 else
1216 rx_start = NULL;
1217 }
1218
1219 if (!rx_start) {
1220 IWL_ERROR("MPDU frame without a PHY data\n");
1221 return;
1222 }
1223
1224 if (include_phy) {
1225 header = (struct ieee80211_hdr *)((u8 *) &rx_start[1]
1226 + rx_start->cfg_phy_cnt);
1227
1228 len = le16_to_cpu(rx_start->byte_count);
1229 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
1230 sizeof(struct iwl4965_rx_phy_res) + len);
1231 } else {
1232 struct iwl4965_rx_mpdu_res_start *amsdu =
1233 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
1234
1235 header = (void *)(pkt->u.raw +
1236 sizeof(struct iwl4965_rx_mpdu_res_start));
1237 len = le16_to_cpu(amsdu->byte_count);
1238 rx_end = (__le32 *) (pkt->u.raw +
1239 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
1240 }
1241
1242 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
1243 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1244 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
1245 le32_to_cpu(*rx_end));
1246 return;
1247 }
1248
1249 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
1250
1251 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1252 rx_status.signal = iwl_calc_rssi(priv, rx_start);
1253
1254 /* Meaningful noise values are available only from beacon statistics,
1255 * which are gathered only when associated, and indicate noise
1256 * only for the associated network channel ...
1257 * Ignore these noise values while scanning (other channels) */
1258 if (iwl_is_associated(priv) &&
1259 !test_bit(STATUS_SCANNING, &priv->status)) {
1260 rx_status.noise = priv->last_rx_noise;
1261 rx_status.qual = iwl_calc_sig_qual(rx_status.signal,
1262 rx_status.noise);
1263 } else {
1264 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
1265 rx_status.qual = iwl_calc_sig_qual(rx_status.signal, 0);
1266 }
1267
1268 /* Reset beacon noise level if not associated. */
1269 if (!iwl_is_associated(priv))
1270 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
1271
1272 /* Set "1" to report good data frames in groups of 100 */
1273 /* FIXME: need to optimze the call: */
1274 iwl_dbg_report_frame(priv, pkt, header, 1);
1275
1276 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
1277 rx_status.signal, rx_status.noise, rx_status.signal,
1278 (unsigned long long)rx_status.mactime);
1279
1280 /* Take shortcut when only in monitor mode */
1281 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
1282 iwl_pass_packet_to_mac80211(priv, include_phy,
1283 rxb, &rx_status);
1284 return;
1285 }
1286
1287 network_packet = iwl_is_network_packet(priv, header);
1288 if (network_packet) {
1289 priv->last_rx_rssi = rx_status.signal;
1290 priv->last_beacon_time = priv->ucode_beacon_time;
1291 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
1292 }
1293
1294 fc = le16_to_cpu(header->frame_control);
1295 switch (fc & IEEE80211_FCTL_FTYPE) {
1296 case IEEE80211_FTYPE_MGMT:
1297 case IEEE80211_FTYPE_DATA:
1298 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
1299 iwl_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
1300 header->addr2);
1301 /* fall through */
1302 default:
1303 iwl_pass_packet_to_mac80211(priv, include_phy, rxb,
1304 &rx_status);
1305 break;
1306
1307 }
1308}
1309EXPORT_SYMBOL(iwl_rx_reply_rx);
1310
1311/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1312 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1313void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
1314 struct iwl_rx_mem_buffer *rxb)
1315{
1316 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1317 priv->last_phy_res[0] = 1;
1318 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
1319 sizeof(struct iwl4965_rx_phy_res));
1320}
1321EXPORT_SYMBOL(iwl_rx_reply_rx_phy);
diff --git a/drivers/net/wireless/iwlwifi/iwl-scan.c b/drivers/net/wireless/iwlwifi/iwl-scan.c
new file mode 100644
index 000000000000..efc750d2fc5c
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-scan.c
@@ -0,0 +1,931 @@
1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28#include <net/mac80211.h>
29#include <linux/etherdevice.h>
30
31#include "iwl-eeprom.h"
32#include "iwl-dev.h"
33#include "iwl-core.h"
34#include "iwl-sta.h"
35#include "iwl-io.h"
36#include "iwl-helpers.h"
37
38/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
39 * sending probe req. This should be set long enough to hear probe responses
40 * from more than one AP. */
41#define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
42#define IWL_ACTIVE_DWELL_TIME_52 (20)
43
44#define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
45#define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
46
47/* For faster active scanning, scan will move to the next channel if fewer than
48 * PLCP_QUIET_THRESH packets are heard on this channel within
49 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
50 * time if it's a quiet channel (nothing responded to our probe, and there's
51 * no other traffic).
52 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
53#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
54#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
55
56/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
57 * Must be set longer than active dwell time.
58 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
59#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
60#define IWL_PASSIVE_DWELL_TIME_52 (10)
61#define IWL_PASSIVE_DWELL_BASE (100)
62#define IWL_CHANNEL_TUNE_TIME 5
63
64#define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
65
66
67static int scan_tx_ant[3] = {
68 RATE_MCS_ANT_A_MSK, RATE_MCS_ANT_B_MSK, RATE_MCS_ANT_C_MSK
69};
70
71
72
73static int iwl_is_empty_essid(const char *essid, int essid_len)
74{
75 /* Single white space is for Linksys APs */
76 if (essid_len == 1 && essid[0] == ' ')
77 return 1;
78
79 /* Otherwise, if the entire essid is 0, we assume it is hidden */
80 while (essid_len) {
81 essid_len--;
82 if (essid[essid_len] != '\0')
83 return 0;
84 }
85
86 return 1;
87}
88
89
90
91const char *iwl_escape_essid(const char *essid, u8 essid_len)
92{
93 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
94 const char *s = essid;
95 char *d = escaped;
96
97 if (iwl_is_empty_essid(essid, essid_len)) {
98 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
99 return escaped;
100 }
101
102 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
103 while (essid_len--) {
104 if (*s == '\0') {
105 *d++ = '\\';
106 *d++ = '0';
107 s++;
108 } else
109 *d++ = *s++;
110 }
111 *d = '\0';
112 return escaped;
113}
114EXPORT_SYMBOL(iwl_escape_essid);
115
116/**
117 * iwl_scan_cancel - Cancel any currently executing HW scan
118 *
119 * NOTE: priv->mutex is not required before calling this function
120 */
121int iwl_scan_cancel(struct iwl_priv *priv)
122{
123 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
124 clear_bit(STATUS_SCANNING, &priv->status);
125 return 0;
126 }
127
128 if (test_bit(STATUS_SCANNING, &priv->status)) {
129 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
130 IWL_DEBUG_SCAN("Queuing scan abort.\n");
131 set_bit(STATUS_SCAN_ABORTING, &priv->status);
132 queue_work(priv->workqueue, &priv->abort_scan);
133
134 } else
135 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
136
137 return test_bit(STATUS_SCANNING, &priv->status);
138 }
139
140 return 0;
141}
142EXPORT_SYMBOL(iwl_scan_cancel);
143/**
144 * iwl_scan_cancel_timeout - Cancel any currently executing HW scan
145 * @ms: amount of time to wait (in milliseconds) for scan to abort
146 *
147 * NOTE: priv->mutex must be held before calling this function
148 */
149int iwl_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
150{
151 unsigned long now = jiffies;
152 int ret;
153
154 ret = iwl_scan_cancel(priv);
155 if (ret && ms) {
156 mutex_unlock(&priv->mutex);
157 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
158 test_bit(STATUS_SCANNING, &priv->status))
159 msleep(1);
160 mutex_lock(&priv->mutex);
161
162 return test_bit(STATUS_SCANNING, &priv->status);
163 }
164
165 return ret;
166}
167EXPORT_SYMBOL(iwl_scan_cancel_timeout);
168
169static int iwl_send_scan_abort(struct iwl_priv *priv)
170{
171 int ret = 0;
172 struct iwl_rx_packet *res;
173 struct iwl_host_cmd cmd = {
174 .id = REPLY_SCAN_ABORT_CMD,
175 .meta.flags = CMD_WANT_SKB,
176 };
177
178 /* If there isn't a scan actively going on in the hardware
179 * then we are in between scan bands and not actually
180 * actively scanning, so don't send the abort command */
181 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
182 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
183 return 0;
184 }
185
186 ret = iwl_send_cmd_sync(priv, &cmd);
187 if (ret) {
188 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
189 return ret;
190 }
191
192 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
193 if (res->u.status != CAN_ABORT_STATUS) {
194 /* The scan abort will return 1 for success or
195 * 2 for "failure". A failure condition can be
196 * due to simply not being in an active scan which
197 * can occur if we send the scan abort before we
198 * the microcode has notified us that a scan is
199 * completed. */
200 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
201 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
202 clear_bit(STATUS_SCAN_HW, &priv->status);
203 }
204
205 dev_kfree_skb_any(cmd.meta.u.skb);
206
207 return ret;
208}
209
210
211/* Service response to REPLY_SCAN_CMD (0x80) */
212static void iwl_rx_reply_scan(struct iwl_priv *priv,
213 struct iwl_rx_mem_buffer *rxb)
214{
215#ifdef CONFIG_IWLWIFI_DEBUG
216 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
217 struct iwl_scanreq_notification *notif =
218 (struct iwl_scanreq_notification *)pkt->u.raw;
219
220 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
221#endif
222}
223
224/* Service SCAN_START_NOTIFICATION (0x82) */
225static void iwl_rx_scan_start_notif(struct iwl_priv *priv,
226 struct iwl_rx_mem_buffer *rxb)
227{
228 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
229 struct iwl_scanstart_notification *notif =
230 (struct iwl_scanstart_notification *)pkt->u.raw;
231 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
232 IWL_DEBUG_SCAN("Scan start: "
233 "%d [802.11%s] "
234 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
235 notif->channel,
236 notif->band ? "bg" : "a",
237 le32_to_cpu(notif->tsf_high),
238 le32_to_cpu(notif->tsf_low),
239 notif->status, notif->beacon_timer);
240}
241
242/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
243static void iwl_rx_scan_results_notif(struct iwl_priv *priv,
244 struct iwl_rx_mem_buffer *rxb)
245{
246#ifdef CONFIG_IWLWIFI_DEBUG
247 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
248 struct iwl_scanresults_notification *notif =
249 (struct iwl_scanresults_notification *)pkt->u.raw;
250
251 IWL_DEBUG_SCAN("Scan ch.res: "
252 "%d [802.11%s] "
253 "(TSF: 0x%08X:%08X) - %d "
254 "elapsed=%lu usec (%dms since last)\n",
255 notif->channel,
256 notif->band ? "bg" : "a",
257 le32_to_cpu(notif->tsf_high),
258 le32_to_cpu(notif->tsf_low),
259 le32_to_cpu(notif->statistics[0]),
260 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
261 jiffies_to_msecs(elapsed_jiffies
262 (priv->last_scan_jiffies, jiffies)));
263#endif
264
265 priv->last_scan_jiffies = jiffies;
266 priv->next_scan_jiffies = 0;
267}
268
269/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
270static void iwl_rx_scan_complete_notif(struct iwl_priv *priv,
271 struct iwl_rx_mem_buffer *rxb)
272{
273 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
274 struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
275
276 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
277 scan_notif->scanned_channels,
278 scan_notif->tsf_low,
279 scan_notif->tsf_high, scan_notif->status);
280
281 /* The HW is no longer scanning */
282 clear_bit(STATUS_SCAN_HW, &priv->status);
283
284 /* The scan completion notification came in, so kill that timer... */
285 cancel_delayed_work(&priv->scan_check);
286
287 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
288 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
289 "2.4" : "5.2",
290 jiffies_to_msecs(elapsed_jiffies
291 (priv->scan_pass_start, jiffies)));
292
293 /* Remove this scanned band from the list of pending
294 * bands to scan, band G precedes A in order of scanning
295 * as seen in iwl_bg_request_scan */
296 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
297 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
298 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
299 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
300
301 /* If a request to abort was given, or the scan did not succeed
302 * then we reset the scan state machine and terminate,
303 * re-queuing another scan if one has been requested */
304 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
305 IWL_DEBUG_INFO("Aborted scan completed.\n");
306 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
307 } else {
308 /* If there are more bands on this scan pass reschedule */
309 if (priv->scan_bands)
310 goto reschedule;
311 }
312
313 priv->last_scan_jiffies = jiffies;
314 priv->next_scan_jiffies = 0;
315 IWL_DEBUG_INFO("Setting scan to off\n");
316
317 clear_bit(STATUS_SCANNING, &priv->status);
318
319 IWL_DEBUG_INFO("Scan took %dms\n",
320 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
321
322 queue_work(priv->workqueue, &priv->scan_completed);
323
324 return;
325
326reschedule:
327 priv->scan_pass_start = jiffies;
328 queue_work(priv->workqueue, &priv->request_scan);
329}
330
331void iwl_setup_rx_scan_handlers(struct iwl_priv *priv)
332{
333 /* scan handlers */
334 priv->rx_handlers[REPLY_SCAN_CMD] = iwl_rx_reply_scan;
335 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl_rx_scan_start_notif;
336 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
337 iwl_rx_scan_results_notif;
338 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
339 iwl_rx_scan_complete_notif;
340}
341EXPORT_SYMBOL(iwl_setup_rx_scan_handlers);
342
343static inline u16 iwl_get_active_dwell_time(struct iwl_priv *priv,
344 enum ieee80211_band band,
345 u8 n_probes)
346{
347 if (band == IEEE80211_BAND_5GHZ)
348 return IWL_ACTIVE_DWELL_TIME_52 +
349 IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
350 else
351 return IWL_ACTIVE_DWELL_TIME_24 +
352 IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
353}
354
355static u16 iwl_get_passive_dwell_time(struct iwl_priv *priv,
356 enum ieee80211_band band)
357{
358 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
359 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
360 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
361
362 if (iwl_is_associated(priv)) {
363 /* If we're associated, we clamp the maximum passive
364 * dwell time to be 98% of the beacon interval (minus
365 * 2 * channel tune time) */
366 passive = priv->beacon_int;
367 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
368 passive = IWL_PASSIVE_DWELL_BASE;
369 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
370 }
371
372 return passive;
373}
374
375static int iwl_get_channels_for_scan(struct iwl_priv *priv,
376 enum ieee80211_band band,
377 u8 is_active, u8 n_probes,
378 struct iwl_scan_channel *scan_ch)
379{
380 const struct ieee80211_channel *channels = NULL;
381 const struct ieee80211_supported_band *sband;
382 const struct iwl_channel_info *ch_info;
383 u16 passive_dwell = 0;
384 u16 active_dwell = 0;
385 int added, i;
386 u16 channel;
387
388 sband = iwl_get_hw_mode(priv, band);
389 if (!sband)
390 return 0;
391
392 channels = sband->channels;
393
394 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
395 passive_dwell = iwl_get_passive_dwell_time(priv, band);
396
397 if (passive_dwell <= active_dwell)
398 passive_dwell = active_dwell + 1;
399
400 for (i = 0, added = 0; i < sband->n_channels; i++) {
401 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
402 continue;
403
404 channel =
405 ieee80211_frequency_to_channel(channels[i].center_freq);
406 scan_ch->channel = cpu_to_le16(channel);
407
408 ch_info = iwl_get_channel_info(priv, band, channel);
409 if (!is_channel_valid(ch_info)) {
410 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
411 channel);
412 continue;
413 }
414
415 if (!is_active || is_channel_passive(ch_info) ||
416 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
417 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
418 else
419 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
420
421 if ((scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) && n_probes)
422 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
423
424 scan_ch->active_dwell = cpu_to_le16(active_dwell);
425 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
426
427 /* Set txpower levels to defaults */
428 scan_ch->dsp_atten = 110;
429
430 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
431 * power level:
432 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
433 */
434 if (band == IEEE80211_BAND_5GHZ)
435 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
436 else
437 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
438
439 IWL_DEBUG_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n",
440 channel, le32_to_cpu(scan_ch->type),
441 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
442 "ACTIVE" : "PASSIVE",
443 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
444 active_dwell : passive_dwell);
445
446 scan_ch++;
447 added++;
448 }
449
450 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
451 return added;
452}
453
454void iwl_init_scan_params(struct iwl_priv *priv)
455{
456 if (!priv->scan_tx_ant[IEEE80211_BAND_5GHZ])
457 priv->scan_tx_ant[IEEE80211_BAND_5GHZ] = RATE_MCS_ANT_INIT_IND;
458 if (!priv->scan_tx_ant[IEEE80211_BAND_2GHZ])
459 priv->scan_tx_ant[IEEE80211_BAND_2GHZ] = RATE_MCS_ANT_INIT_IND;
460}
461
462int iwl_scan_initiate(struct iwl_priv *priv)
463{
464 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
465 IWL_ERROR("APs don't scan.\n");
466 return 0;
467 }
468
469 if (!iwl_is_ready_rf(priv)) {
470 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
471 return -EIO;
472 }
473
474 if (test_bit(STATUS_SCANNING, &priv->status)) {
475 IWL_DEBUG_SCAN("Scan already in progress.\n");
476 return -EAGAIN;
477 }
478
479 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
480 IWL_DEBUG_SCAN("Scan request while abort pending. "
481 "Queuing.\n");
482 return -EAGAIN;
483 }
484
485 IWL_DEBUG_INFO("Starting scan...\n");
486 if (priv->cfg->sku & IWL_SKU_G)
487 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
488 if (priv->cfg->sku & IWL_SKU_A)
489 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
490 set_bit(STATUS_SCANNING, &priv->status);
491 priv->scan_start = jiffies;
492 priv->scan_pass_start = priv->scan_start;
493
494 queue_work(priv->workqueue, &priv->request_scan);
495
496 return 0;
497}
498EXPORT_SYMBOL(iwl_scan_initiate);
499
500#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
501
502static void iwl_bg_scan_check(struct work_struct *data)
503{
504 struct iwl_priv *priv =
505 container_of(data, struct iwl_priv, scan_check.work);
506
507 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
508 return;
509
510 mutex_lock(&priv->mutex);
511 if (test_bit(STATUS_SCANNING, &priv->status) ||
512 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
513 IWL_DEBUG(IWL_DL_SCAN, "Scan completion watchdog resetting "
514 "adapter (%dms)\n",
515 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
516
517 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
518 iwl_send_scan_abort(priv);
519 }
520 mutex_unlock(&priv->mutex);
521}
522/**
523 * iwl_supported_rate_to_ie - fill in the supported rate in IE field
524 *
525 * return : set the bit for each supported rate insert in ie
526 */
527static u16 iwl_supported_rate_to_ie(u8 *ie, u16 supported_rate,
528 u16 basic_rate, int *left)
529{
530 u16 ret_rates = 0, bit;
531 int i;
532 u8 *cnt = ie;
533 u8 *rates = ie + 1;
534
535 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
536 if (bit & supported_rate) {
537 ret_rates |= bit;
538 rates[*cnt] = iwl_rates[i].ieee |
539 ((bit & basic_rate) ? 0x80 : 0x00);
540 (*cnt)++;
541 (*left)--;
542 if ((*left <= 0) ||
543 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
544 break;
545 }
546 }
547
548 return ret_rates;
549}
550
551
552static void iwl_ht_cap_to_ie(const struct ieee80211_supported_band *sband,
553 u8 *pos, int *left)
554{
555 struct ieee80211_ht_cap *ht_cap;
556
557 if (!sband || !sband->ht_info.ht_supported)
558 return;
559
560 if (*left < sizeof(struct ieee80211_ht_cap))
561 return;
562
563 *pos++ = sizeof(struct ieee80211_ht_cap);
564 ht_cap = (struct ieee80211_ht_cap *) pos;
565
566 ht_cap->cap_info = cpu_to_le16(sband->ht_info.cap);
567 memcpy(ht_cap->supp_mcs_set, sband->ht_info.supp_mcs_set, 16);
568 ht_cap->ampdu_params_info =
569 (sband->ht_info.ampdu_factor & IEEE80211_HT_CAP_AMPDU_FACTOR) |
570 ((sband->ht_info.ampdu_density << 2) &
571 IEEE80211_HT_CAP_AMPDU_DENSITY);
572 *left -= sizeof(struct ieee80211_ht_cap);
573}
574
575/**
576 * iwl_fill_probe_req - fill in all required fields and IE for probe request
577 */
578
579static u16 iwl_fill_probe_req(struct iwl_priv *priv,
580 enum ieee80211_band band,
581 struct ieee80211_mgmt *frame,
582 int left)
583{
584 int len = 0;
585 u8 *pos = NULL;
586 u16 active_rates, ret_rates, cck_rates, active_rate_basic;
587 const struct ieee80211_supported_band *sband =
588 iwl_get_hw_mode(priv, band);
589
590
591 /* Make sure there is enough space for the probe request,
592 * two mandatory IEs and the data */
593 left -= 24;
594 if (left < 0)
595 return 0;
596
597 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
598 memcpy(frame->da, iwl_bcast_addr, ETH_ALEN);
599 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
600 memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN);
601 frame->seq_ctrl = 0;
602
603 len += 24;
604
605 /* ...next IE... */
606 pos = &frame->u.probe_req.variable[0];
607
608 /* fill in our indirect SSID IE */
609 left -= 2;
610 if (left < 0)
611 return 0;
612 *pos++ = WLAN_EID_SSID;
613 *pos++ = 0;
614
615 len += 2;
616
617 /* fill in supported rate */
618 left -= 2;
619 if (left < 0)
620 return 0;
621
622 *pos++ = WLAN_EID_SUPP_RATES;
623 *pos = 0;
624
625 /* exclude 60M rate */
626 active_rates = priv->rates_mask;
627 active_rates &= ~IWL_RATE_60M_MASK;
628
629 active_rate_basic = active_rates & IWL_BASIC_RATES_MASK;
630
631 cck_rates = IWL_CCK_RATES_MASK & active_rates;
632 ret_rates = iwl_supported_rate_to_ie(pos, cck_rates,
633 active_rate_basic, &left);
634 active_rates &= ~ret_rates;
635
636 ret_rates = iwl_supported_rate_to_ie(pos, active_rates,
637 active_rate_basic, &left);
638 active_rates &= ~ret_rates;
639
640 len += 2 + *pos;
641 pos += (*pos) + 1;
642
643 if (active_rates == 0)
644 goto fill_end;
645
646 /* fill in supported extended rate */
647 /* ...next IE... */
648 left -= 2;
649 if (left < 0)
650 return 0;
651 /* ... fill it in... */
652 *pos++ = WLAN_EID_EXT_SUPP_RATES;
653 *pos = 0;
654 iwl_supported_rate_to_ie(pos, active_rates, active_rate_basic, &left);
655 if (*pos > 0) {
656 len += 2 + *pos;
657 pos += (*pos) + 1;
658 } else {
659 pos--;
660 }
661
662 fill_end:
663
664 left -= 2;
665 if (left < 0)
666 return 0;
667
668 *pos++ = WLAN_EID_HT_CAPABILITY;
669 *pos = 0;
670 iwl_ht_cap_to_ie(sband, pos, &left);
671 if (*pos > 0)
672 len += 2 + *pos;
673
674 return (u16)len;
675}
676
677static u32 iwl_scan_tx_ant(struct iwl_priv *priv, enum ieee80211_band band)
678{
679 int i, ind;
680
681 ind = priv->scan_tx_ant[band];
682 for (i = 0; i < priv->hw_params.tx_chains_num; i++) {
683 ind = (ind+1) >= priv->hw_params.tx_chains_num ? 0 : ind+1;
684 if (priv->hw_params.valid_tx_ant & (1 << ind)) {
685 priv->scan_tx_ant[band] = ind;
686 break;
687 }
688 }
689 IWL_DEBUG_SCAN("select TX ANT = %c\n", 'A' + ind);
690 return scan_tx_ant[ind];
691}
692
693
694static void iwl_bg_request_scan(struct work_struct *data)
695{
696 struct iwl_priv *priv =
697 container_of(data, struct iwl_priv, request_scan);
698 struct iwl_host_cmd cmd = {
699 .id = REPLY_SCAN_CMD,
700 .len = sizeof(struct iwl_scan_cmd),
701 .meta.flags = CMD_SIZE_HUGE,
702 };
703 struct iwl_scan_cmd *scan;
704 struct ieee80211_conf *conf = NULL;
705 int ret = 0;
706 u32 tx_ant;
707 u16 cmd_len;
708 enum ieee80211_band band;
709 u8 n_probes = 2;
710 u8 rx_chain = 0x7; /* bitmap: ABC chains */
711
712 conf = ieee80211_get_hw_conf(priv->hw);
713
714 mutex_lock(&priv->mutex);
715
716 if (!iwl_is_ready(priv)) {
717 IWL_WARNING("request scan called when driver not ready.\n");
718 goto done;
719 }
720
721 /* Make sure the scan wasn't cancelled before this queued work
722 * was given the chance to run... */
723 if (!test_bit(STATUS_SCANNING, &priv->status))
724 goto done;
725
726 /* This should never be called or scheduled if there is currently
727 * a scan active in the hardware. */
728 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
729 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
730 "Ignoring second request.\n");
731 ret = -EIO;
732 goto done;
733 }
734
735 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
736 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
737 goto done;
738 }
739
740 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
741 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
742 goto done;
743 }
744
745 if (iwl_is_rfkill(priv)) {
746 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
747 goto done;
748 }
749
750 if (!test_bit(STATUS_READY, &priv->status)) {
751 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
752 goto done;
753 }
754
755 if (!priv->scan_bands) {
756 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
757 goto done;
758 }
759
760 if (!priv->scan) {
761 priv->scan = kmalloc(sizeof(struct iwl_scan_cmd) +
762 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
763 if (!priv->scan) {
764 ret = -ENOMEM;
765 goto done;
766 }
767 }
768 scan = priv->scan;
769 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
770
771 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
772 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
773
774 if (iwl_is_associated(priv)) {
775 u16 interval = 0;
776 u32 extra;
777 u32 suspend_time = 100;
778 u32 scan_suspend_time = 100;
779 unsigned long flags;
780
781 IWL_DEBUG_INFO("Scanning while associated...\n");
782
783 spin_lock_irqsave(&priv->lock, flags);
784 interval = priv->beacon_int;
785 spin_unlock_irqrestore(&priv->lock, flags);
786
787 scan->suspend_time = 0;
788 scan->max_out_time = cpu_to_le32(200 * 1024);
789 if (!interval)
790 interval = suspend_time;
791
792 extra = (suspend_time / interval) << 22;
793 scan_suspend_time = (extra |
794 ((suspend_time % interval) * 1024));
795 scan->suspend_time = cpu_to_le32(scan_suspend_time);
796 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
797 scan_suspend_time, interval);
798 }
799
800 /* We should add the ability for user to lock to PASSIVE ONLY */
801 if (priv->one_direct_scan) {
802 IWL_DEBUG_SCAN("Start direct scan for '%s'\n",
803 iwl_escape_essid(priv->direct_ssid,
804 priv->direct_ssid_len));
805 scan->direct_scan[0].id = WLAN_EID_SSID;
806 scan->direct_scan[0].len = priv->direct_ssid_len;
807 memcpy(scan->direct_scan[0].ssid,
808 priv->direct_ssid, priv->direct_ssid_len);
809 n_probes++;
810 } else if (!iwl_is_associated(priv) && priv->essid_len) {
811 IWL_DEBUG_SCAN("Start direct scan for '%s' (not associated)\n",
812 iwl_escape_essid(priv->essid, priv->essid_len));
813 scan->direct_scan[0].id = WLAN_EID_SSID;
814 scan->direct_scan[0].len = priv->essid_len;
815 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
816 n_probes++;
817 } else {
818 IWL_DEBUG_SCAN("Start indirect scan.\n");
819 }
820
821 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
822 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
823 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
824
825
826 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
827 band = IEEE80211_BAND_2GHZ;
828 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
829 tx_ant = iwl_scan_tx_ant(priv, band);
830 if (priv->active_rxon.flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK)
831 scan->tx_cmd.rate_n_flags =
832 iwl_hw_set_rate_n_flags(IWL_RATE_6M_PLCP,
833 tx_ant);
834 else
835 scan->tx_cmd.rate_n_flags =
836 iwl_hw_set_rate_n_flags(IWL_RATE_1M_PLCP,
837 tx_ant |
838 RATE_MCS_CCK_MSK);
839 scan->good_CRC_th = 0;
840 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
841 band = IEEE80211_BAND_5GHZ;
842 tx_ant = iwl_scan_tx_ant(priv, band);
843 scan->tx_cmd.rate_n_flags =
844 iwl_hw_set_rate_n_flags(IWL_RATE_6M_PLCP,
845 tx_ant);
846 scan->good_CRC_th = IWL_GOOD_CRC_TH;
847
848 /* Force use of chains B and C (0x6) for scan Rx for 4965
849 * Avoid A (0x1) because of its off-channel reception on A-band.
850 * MIMO is not used here, but value is required */
851 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)
852 rx_chain = 0x6;
853 } else {
854 IWL_WARNING("Invalid scan band count\n");
855 goto done;
856 }
857
858 scan->rx_chain = RXON_RX_CHAIN_DRIVER_FORCE_MSK |
859 cpu_to_le16((0x7 << RXON_RX_CHAIN_VALID_POS) |
860 (rx_chain << RXON_RX_CHAIN_FORCE_SEL_POS) |
861 (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS));
862
863 cmd_len = iwl_fill_probe_req(priv, band,
864 (struct ieee80211_mgmt *)scan->data,
865 IWL_MAX_SCAN_SIZE - sizeof(*scan));
866
867 scan->tx_cmd.len = cpu_to_le16(cmd_len);
868
869 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
870 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
871
872 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
873 RXON_FILTER_BCON_AWARE_MSK);
874
875 scan->channel_count =
876 iwl_get_channels_for_scan(priv, band, 1, /* active */
877 n_probes,
878 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
879
880 if (scan->channel_count == 0) {
881 IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
882 goto done;
883 }
884
885 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
886 scan->channel_count * sizeof(struct iwl_scan_channel);
887 cmd.data = scan;
888 scan->len = cpu_to_le16(cmd.len);
889
890 set_bit(STATUS_SCAN_HW, &priv->status);
891 ret = iwl_send_cmd_sync(priv, &cmd);
892 if (ret)
893 goto done;
894
895 queue_delayed_work(priv->workqueue, &priv->scan_check,
896 IWL_SCAN_CHECK_WATCHDOG);
897
898 mutex_unlock(&priv->mutex);
899 return;
900
901 done:
902 /* inform mac80211 scan aborted */
903 queue_work(priv->workqueue, &priv->scan_completed);
904 mutex_unlock(&priv->mutex);
905}
906
907static void iwl_bg_abort_scan(struct work_struct *work)
908{
909 struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
910
911 if (!iwl_is_ready(priv))
912 return;
913
914 mutex_lock(&priv->mutex);
915
916 set_bit(STATUS_SCAN_ABORTING, &priv->status);
917 iwl_send_scan_abort(priv);
918
919 mutex_unlock(&priv->mutex);
920}
921
922void iwl_setup_scan_deferred_work(struct iwl_priv *priv)
923{
924 /* FIXME: move here when resolved PENDING
925 * INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed); */
926 INIT_WORK(&priv->request_scan, iwl_bg_request_scan);
927 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
928 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
929}
930EXPORT_SYMBOL(iwl_setup_scan_deferred_work);
931
diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.c b/drivers/net/wireless/iwlwifi/iwl-sta.c
index e4fdfaa2b9b2..6d1467d0bd9d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-sta.c
+++ b/drivers/net/wireless/iwlwifi/iwl-sta.c
@@ -28,17 +28,446 @@
28 *****************************************************************************/ 28 *****************************************************************************/
29 29
30#include <net/mac80211.h> 30#include <net/mac80211.h>
31#include <linux/etherdevice.h>
31 32
32#include "iwl-eeprom.h" 33#include "iwl-dev.h"
33#include "iwl-4965.h"
34#include "iwl-core.h" 34#include "iwl-core.h"
35#include "iwl-sta.h" 35#include "iwl-sta.h"
36#include "iwl-io.h"
37#include "iwl-helpers.h" 36#include "iwl-helpers.h"
38#include "iwl-4965.h"
39#include "iwl-sta.h"
40 37
41int iwl_get_free_ucode_key_index(struct iwl_priv *priv) 38
39#define IWL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */
40#define IWL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */
41
42u8 iwl_find_station(struct iwl_priv *priv, const u8 *addr)
43{
44 int i;
45 int start = 0;
46 int ret = IWL_INVALID_STATION;
47 unsigned long flags;
48 DECLARE_MAC_BUF(mac);
49
50 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
51 (priv->iw_mode == IEEE80211_IF_TYPE_AP))
52 start = IWL_STA_ID;
53
54 if (is_broadcast_ether_addr(addr))
55 return priv->hw_params.bcast_sta_id;
56
57 spin_lock_irqsave(&priv->sta_lock, flags);
58 for (i = start; i < priv->hw_params.max_stations; i++)
59 if (priv->stations[i].used &&
60 (!compare_ether_addr(priv->stations[i].sta.sta.addr,
61 addr))) {
62 ret = i;
63 goto out;
64 }
65
66 IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
67 print_mac(mac, addr), priv->num_stations);
68
69 out:
70 spin_unlock_irqrestore(&priv->sta_lock, flags);
71 return ret;
72}
73EXPORT_SYMBOL(iwl_find_station);
74
75int iwl_get_ra_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
76{
77 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
78 return IWL_AP_ID;
79 } else {
80 u8 *da = ieee80211_get_DA(hdr);
81 return iwl_find_station(priv, da);
82 }
83}
84EXPORT_SYMBOL(iwl_get_ra_sta_id);
85
86static void iwl_sta_ucode_activate(struct iwl_priv *priv, u8 sta_id)
87{
88 unsigned long flags;
89 DECLARE_MAC_BUF(mac);
90
91 spin_lock_irqsave(&priv->sta_lock, flags);
92
93 if (!(priv->stations[sta_id].used & IWL_STA_DRIVER_ACTIVE))
94 IWL_ERROR("ACTIVATE a non DRIVER active station %d\n", sta_id);
95
96 priv->stations[sta_id].used |= IWL_STA_UCODE_ACTIVE;
97 IWL_DEBUG_ASSOC("Added STA to Ucode: %s\n",
98 print_mac(mac, priv->stations[sta_id].sta.sta.addr));
99
100 spin_unlock_irqrestore(&priv->sta_lock, flags);
101}
102
103static int iwl_add_sta_callback(struct iwl_priv *priv,
104 struct iwl_cmd *cmd, struct sk_buff *skb)
105{
106 struct iwl_rx_packet *res = NULL;
107 u8 sta_id = cmd->cmd.addsta.sta.sta_id;
108
109 if (!skb) {
110 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
111 return 1;
112 }
113
114 res = (struct iwl_rx_packet *)skb->data;
115 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
116 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
117 res->hdr.flags);
118 return 1;
119 }
120
121 switch (res->u.add_sta.status) {
122 case ADD_STA_SUCCESS_MSK:
123 iwl_sta_ucode_activate(priv, sta_id);
124 /* fall through */
125 default:
126 IWL_DEBUG_HC("Received REPLY_ADD_STA:(0x%08X)\n",
127 res->u.add_sta.status);
128 break;
129 }
130
131 /* We didn't cache the SKB; let the caller free it */
132 return 1;
133}
134
135int iwl_send_add_sta(struct iwl_priv *priv,
136 struct iwl_addsta_cmd *sta, u8 flags)
137{
138 struct iwl_rx_packet *res = NULL;
139 int ret = 0;
140 u8 data[sizeof(*sta)];
141 struct iwl_host_cmd cmd = {
142 .id = REPLY_ADD_STA,
143 .meta.flags = flags,
144 .data = data,
145 };
146
147 if (flags & CMD_ASYNC)
148 cmd.meta.u.callback = iwl_add_sta_callback;
149 else
150 cmd.meta.flags |= CMD_WANT_SKB;
151
152 cmd.len = priv->cfg->ops->utils->build_addsta_hcmd(sta, data);
153 ret = iwl_send_cmd(priv, &cmd);
154
155 if (ret || (flags & CMD_ASYNC))
156 return ret;
157
158 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
159 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
160 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
161 res->hdr.flags);
162 ret = -EIO;
163 }
164
165 if (ret == 0) {
166 switch (res->u.add_sta.status) {
167 case ADD_STA_SUCCESS_MSK:
168 iwl_sta_ucode_activate(priv, sta->sta.sta_id);
169 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
170 break;
171 default:
172 ret = -EIO;
173 IWL_WARNING("REPLY_ADD_STA failed\n");
174 break;
175 }
176 }
177
178 priv->alloc_rxb_skb--;
179 dev_kfree_skb_any(cmd.meta.u.skb);
180
181 return ret;
182}
183EXPORT_SYMBOL(iwl_send_add_sta);
184
185static void iwl_set_ht_add_station(struct iwl_priv *priv, u8 index,
186 struct ieee80211_ht_info *sta_ht_inf)
187{
188 __le32 sta_flags;
189 u8 mimo_ps_mode;
190
191 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
192 goto done;
193
194 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
195
196 sta_flags = priv->stations[index].sta.station_flags;
197
198 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
199
200 switch (mimo_ps_mode) {
201 case WLAN_HT_CAP_MIMO_PS_STATIC:
202 sta_flags |= STA_FLG_MIMO_DIS_MSK;
203 break;
204 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
205 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
206 break;
207 case WLAN_HT_CAP_MIMO_PS_DISABLED:
208 break;
209 default:
210 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
211 break;
212 }
213
214 sta_flags |= cpu_to_le32(
215 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
216
217 sta_flags |= cpu_to_le32(
218 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
219
220 if (iwl_is_fat_tx_allowed(priv, sta_ht_inf))
221 sta_flags |= STA_FLG_FAT_EN_MSK;
222 else
223 sta_flags &= ~STA_FLG_FAT_EN_MSK;
224
225 priv->stations[index].sta.station_flags = sta_flags;
226 done:
227 return;
228}
229
230/**
231 * iwl_add_station_flags - Add station to tables in driver and device
232 */
233u8 iwl_add_station_flags(struct iwl_priv *priv, const u8 *addr, int is_ap,
234 u8 flags, struct ieee80211_ht_info *ht_info)
235{
236 int i;
237 int sta_id = IWL_INVALID_STATION;
238 struct iwl_station_entry *station;
239 unsigned long flags_spin;
240 DECLARE_MAC_BUF(mac);
241
242 spin_lock_irqsave(&priv->sta_lock, flags_spin);
243 if (is_ap)
244 sta_id = IWL_AP_ID;
245 else if (is_broadcast_ether_addr(addr))
246 sta_id = priv->hw_params.bcast_sta_id;
247 else
248 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
249 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
250 addr)) {
251 sta_id = i;
252 break;
253 }
254
255 if (!priv->stations[i].used &&
256 sta_id == IWL_INVALID_STATION)
257 sta_id = i;
258 }
259
260 /* These two conditions have the same outcome, but keep them separate
261 since they have different meanings */
262 if (unlikely(sta_id == IWL_INVALID_STATION)) {
263 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
264 return sta_id;
265 }
266
267 if (priv->stations[sta_id].used &&
268 !compare_ether_addr(priv->stations[sta_id].sta.sta.addr, addr)) {
269 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
270 return sta_id;
271 }
272
273
274 station = &priv->stations[sta_id];
275 station->used = IWL_STA_DRIVER_ACTIVE;
276 IWL_DEBUG_ASSOC("Add STA to driver ID %d: %s\n",
277 sta_id, print_mac(mac, addr));
278 priv->num_stations++;
279
280 /* Set up the REPLY_ADD_STA command to send to device */
281 memset(&station->sta, 0, sizeof(struct iwl_addsta_cmd));
282 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
283 station->sta.mode = 0;
284 station->sta.sta.sta_id = sta_id;
285 station->sta.station_flags = 0;
286
287 /* BCAST station and IBSS stations do not work in HT mode */
288 if (sta_id != priv->hw_params.bcast_sta_id &&
289 priv->iw_mode != IEEE80211_IF_TYPE_IBSS)
290 iwl_set_ht_add_station(priv, sta_id, ht_info);
291
292 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
293
294 /* Add station to device's station table */
295 iwl_send_add_sta(priv, &station->sta, flags);
296 return sta_id;
297
298}
299EXPORT_SYMBOL(iwl_add_station_flags);
300
301static void iwl_sta_ucode_deactivate(struct iwl_priv *priv, const char *addr)
302{
303 unsigned long flags;
304 DECLARE_MAC_BUF(mac);
305
306 u8 sta_id = iwl_find_station(priv, addr);
307
308 BUG_ON(sta_id == IWL_INVALID_STATION);
309
310 IWL_DEBUG_ASSOC("Removed STA from Ucode: %s\n",
311 print_mac(mac, addr));
312
313 spin_lock_irqsave(&priv->sta_lock, flags);
314
315 /* Ucode must be active and driver must be non active */
316 if (priv->stations[sta_id].used != IWL_STA_UCODE_ACTIVE)
317 IWL_ERROR("removed non active STA %d\n", sta_id);
318
319 priv->stations[sta_id].used &= ~IWL_STA_UCODE_ACTIVE;
320
321 memset(&priv->stations[sta_id], 0, sizeof(struct iwl_station_entry));
322 spin_unlock_irqrestore(&priv->sta_lock, flags);
323}
324
325static int iwl_remove_sta_callback(struct iwl_priv *priv,
326 struct iwl_cmd *cmd, struct sk_buff *skb)
327{
328 struct iwl_rx_packet *res = NULL;
329 const char *addr = cmd->cmd.rm_sta.addr;
330
331 if (!skb) {
332 IWL_ERROR("Error: Response NULL in REPLY_REMOVE_STA.\n");
333 return 1;
334 }
335
336 res = (struct iwl_rx_packet *)skb->data;
337 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
338 IWL_ERROR("Bad return from REPLY_REMOVE_STA (0x%08X)\n",
339 res->hdr.flags);
340 return 1;
341 }
342
343 switch (res->u.rem_sta.status) {
344 case REM_STA_SUCCESS_MSK:
345 iwl_sta_ucode_deactivate(priv, addr);
346 break;
347 default:
348 IWL_ERROR("REPLY_REMOVE_STA failed\n");
349 break;
350 }
351
352 /* We didn't cache the SKB; let the caller free it */
353 return 1;
354}
355
356static int iwl_send_remove_station(struct iwl_priv *priv, const u8 *addr,
357 u8 flags)
358{
359 struct iwl_rx_packet *res = NULL;
360 int ret;
361
362 struct iwl_rem_sta_cmd rm_sta_cmd;
363
364 struct iwl_host_cmd cmd = {
365 .id = REPLY_REMOVE_STA,
366 .len = sizeof(struct iwl_rem_sta_cmd),
367 .meta.flags = flags,
368 .data = &rm_sta_cmd,
369 };
370
371 memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
372 rm_sta_cmd.num_sta = 1;
373 memcpy(&rm_sta_cmd.addr, addr , ETH_ALEN);
374
375 if (flags & CMD_ASYNC)
376 cmd.meta.u.callback = iwl_remove_sta_callback;
377 else
378 cmd.meta.flags |= CMD_WANT_SKB;
379 ret = iwl_send_cmd(priv, &cmd);
380
381 if (ret || (flags & CMD_ASYNC))
382 return ret;
383
384 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
385 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
386 IWL_ERROR("Bad return from REPLY_REMOVE_STA (0x%08X)\n",
387 res->hdr.flags);
388 ret = -EIO;
389 }
390
391 if (!ret) {
392 switch (res->u.rem_sta.status) {
393 case REM_STA_SUCCESS_MSK:
394 iwl_sta_ucode_deactivate(priv, addr);
395 IWL_DEBUG_ASSOC("REPLY_REMOVE_STA PASSED\n");
396 break;
397 default:
398 ret = -EIO;
399 IWL_ERROR("REPLY_REMOVE_STA failed\n");
400 break;
401 }
402 }
403
404 priv->alloc_rxb_skb--;
405 dev_kfree_skb_any(cmd.meta.u.skb);
406
407 return ret;
408}
409
410/**
411 * iwl_remove_station - Remove driver's knowledge of station.
412 */
413int iwl_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
414{
415 int sta_id = IWL_INVALID_STATION;
416 int i, ret = -EINVAL;
417 unsigned long flags;
418 DECLARE_MAC_BUF(mac);
419
420 spin_lock_irqsave(&priv->sta_lock, flags);
421
422 if (is_ap)
423 sta_id = IWL_AP_ID;
424 else if (is_broadcast_ether_addr(addr))
425 sta_id = priv->hw_params.bcast_sta_id;
426 else
427 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
428 if (priv->stations[i].used &&
429 !compare_ether_addr(priv->stations[i].sta.sta.addr,
430 addr)) {
431 sta_id = i;
432 break;
433 }
434
435 if (unlikely(sta_id == IWL_INVALID_STATION))
436 goto out;
437
438 IWL_DEBUG_ASSOC("Removing STA from driver:%d %s\n",
439 sta_id, print_mac(mac, addr));
440
441 if (!(priv->stations[sta_id].used & IWL_STA_DRIVER_ACTIVE)) {
442 IWL_ERROR("Removing %s but non DRIVER active\n",
443 print_mac(mac, addr));
444 goto out;
445 }
446
447 if (!(priv->stations[sta_id].used & IWL_STA_UCODE_ACTIVE)) {
448 IWL_ERROR("Removing %s but non UCODE active\n",
449 print_mac(mac, addr));
450 goto out;
451 }
452
453
454 priv->stations[sta_id].used &= ~IWL_STA_DRIVER_ACTIVE;
455
456 priv->num_stations--;
457
458 BUG_ON(priv->num_stations < 0);
459
460 spin_unlock_irqrestore(&priv->sta_lock, flags);
461
462 ret = iwl_send_remove_station(priv, addr, CMD_ASYNC);
463 return ret;
464out:
465 spin_unlock_irqrestore(&priv->sta_lock, flags);
466 return ret;
467}
468EXPORT_SYMBOL(iwl_remove_station);
469
470static int iwl_get_free_ucode_key_index(struct iwl_priv *priv)
42{ 471{
43 int i; 472 int i;
44 473
@@ -91,6 +520,7 @@ int iwl_send_static_wepkey_cmd(struct iwl_priv *priv, u8 send_if_empty)
91 else 520 else
92 return 0; 521 return 0;
93} 522}
523EXPORT_SYMBOL(iwl_send_static_wepkey_cmd);
94 524
95int iwl_remove_default_wep_key(struct iwl_priv *priv, 525int iwl_remove_default_wep_key(struct iwl_priv *priv,
96 struct ieee80211_key_conf *keyconf) 526 struct ieee80211_key_conf *keyconf)
@@ -107,10 +537,13 @@ int iwl_remove_default_wep_key(struct iwl_priv *priv,
107 priv->default_wep_key--; 537 priv->default_wep_key--;
108 memset(&priv->wep_keys[keyconf->keyidx], 0, sizeof(priv->wep_keys[0])); 538 memset(&priv->wep_keys[keyconf->keyidx], 0, sizeof(priv->wep_keys[0]));
109 ret = iwl_send_static_wepkey_cmd(priv, 1); 539 ret = iwl_send_static_wepkey_cmd(priv, 1);
540 IWL_DEBUG_WEP("Remove default WEP key: idx=%d ret=%d\n",
541 keyconf->keyidx, ret);
110 spin_unlock_irqrestore(&priv->sta_lock, flags); 542 spin_unlock_irqrestore(&priv->sta_lock, flags);
111 543
112 return ret; 544 return ret;
113} 545}
546EXPORT_SYMBOL(iwl_remove_default_wep_key);
114 547
115int iwl_set_default_wep_key(struct iwl_priv *priv, 548int iwl_set_default_wep_key(struct iwl_priv *priv,
116 struct ieee80211_key_conf *keyconf) 549 struct ieee80211_key_conf *keyconf)
@@ -118,8 +551,14 @@ int iwl_set_default_wep_key(struct iwl_priv *priv,
118 int ret; 551 int ret;
119 unsigned long flags; 552 unsigned long flags;
120 553
554 if (keyconf->keylen != WEP_KEY_LEN_128 &&
555 keyconf->keylen != WEP_KEY_LEN_64) {
556 IWL_DEBUG_WEP("Bad WEP key length %d\n", keyconf->keylen);
557 return -EINVAL;
558 }
559
121 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; 560 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
122 keyconf->hw_key_idx = keyconf->keyidx; 561 keyconf->hw_key_idx = HW_KEY_DEFAULT;
123 priv->stations[IWL_AP_ID].keyinfo.alg = ALG_WEP; 562 priv->stations[IWL_AP_ID].keyinfo.alg = ALG_WEP;
124 563
125 spin_lock_irqsave(&priv->sta_lock, flags); 564 spin_lock_irqsave(&priv->sta_lock, flags);
@@ -134,10 +573,13 @@ int iwl_set_default_wep_key(struct iwl_priv *priv,
134 keyconf->keylen); 573 keyconf->keylen);
135 574
136 ret = iwl_send_static_wepkey_cmd(priv, 0); 575 ret = iwl_send_static_wepkey_cmd(priv, 0);
576 IWL_DEBUG_WEP("Set default WEP key: len=%d idx=%d ret=%d\n",
577 keyconf->keylen, keyconf->keyidx, ret);
137 spin_unlock_irqrestore(&priv->sta_lock, flags); 578 spin_unlock_irqrestore(&priv->sta_lock, flags);
138 579
139 return ret; 580 return ret;
140} 581}
582EXPORT_SYMBOL(iwl_set_default_wep_key);
141 583
142static int iwl_set_wep_dynamic_key_info(struct iwl_priv *priv, 584static int iwl_set_wep_dynamic_key_info(struct iwl_priv *priv,
143 struct ieee80211_key_conf *keyconf, 585 struct ieee80211_key_conf *keyconf,
@@ -148,7 +590,6 @@ static int iwl_set_wep_dynamic_key_info(struct iwl_priv *priv,
148 int ret; 590 int ret;
149 591
150 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; 592 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
151 keyconf->hw_key_idx = keyconf->keyidx;
152 593
153 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK); 594 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
154 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 595 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
@@ -172,15 +613,18 @@ static int iwl_set_wep_dynamic_key_info(struct iwl_priv *priv,
172 memcpy(&priv->stations[sta_id].sta.key.key[3], 613 memcpy(&priv->stations[sta_id].sta.key.key[3],
173 keyconf->key, keyconf->keylen); 614 keyconf->key, keyconf->keylen);
174 615
175 priv->stations[sta_id].sta.key.key_offset = 616 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
617 == STA_KEY_FLG_NO_ENC)
618 priv->stations[sta_id].sta.key.key_offset =
176 iwl_get_free_ucode_key_index(priv); 619 iwl_get_free_ucode_key_index(priv);
177 priv->stations[sta_id].sta.key.key_flags = key_flags; 620 /* else, we are overriding an existing key => no need to allocated room
621 * in uCode. */
178 622
623 priv->stations[sta_id].sta.key.key_flags = key_flags;
179 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 624 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
180 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 625 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
181 626
182 ret = iwl4965_send_add_station(priv, 627 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
183 &priv->stations[sta_id].sta, CMD_ASYNC);
184 628
185 spin_unlock_irqrestore(&priv->sta_lock, flags); 629 spin_unlock_irqrestore(&priv->sta_lock, flags);
186 630
@@ -202,7 +646,6 @@ static int iwl_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
202 key_flags |= STA_KEY_MULTICAST_MSK; 646 key_flags |= STA_KEY_MULTICAST_MSK;
203 647
204 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 648 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
205 keyconf->hw_key_idx = keyconf->keyidx;
206 649
207 spin_lock_irqsave(&priv->sta_lock, flags); 650 spin_lock_irqsave(&priv->sta_lock, flags);
208 priv->stations[sta_id].keyinfo.alg = keyconf->alg; 651 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
@@ -214,8 +657,13 @@ static int iwl_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
214 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, 657 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
215 keyconf->keylen); 658 keyconf->keylen);
216 659
217 priv->stations[sta_id].sta.key.key_offset = 660 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
218 iwl_get_free_ucode_key_index(priv); 661 == STA_KEY_FLG_NO_ENC)
662 priv->stations[sta_id].sta.key.key_offset =
663 iwl_get_free_ucode_key_index(priv);
664 /* else, we are overriding an existing key => no need to allocated room
665 * in uCode. */
666
219 priv->stations[sta_id].sta.key.key_flags = key_flags; 667 priv->stations[sta_id].sta.key.key_flags = key_flags;
220 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 668 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
221 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 669 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
@@ -223,8 +671,7 @@ static int iwl_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
223 spin_unlock_irqrestore(&priv->sta_lock, flags); 671 spin_unlock_irqrestore(&priv->sta_lock, flags);
224 672
225 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n"); 673 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
226 return iwl4965_send_add_station(priv, 674 return iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
227 &priv->stations[sta_id].sta, CMD_ASYNC);
228} 675}
229 676
230static int iwl_set_tkip_dynamic_key_info(struct iwl_priv *priv, 677static int iwl_set_tkip_dynamic_key_info(struct iwl_priv *priv,
@@ -236,15 +683,18 @@ static int iwl_set_tkip_dynamic_key_info(struct iwl_priv *priv,
236 683
237 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 684 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
238 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 685 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
239 keyconf->hw_key_idx = keyconf->keyidx;
240 686
241 spin_lock_irqsave(&priv->sta_lock, flags); 687 spin_lock_irqsave(&priv->sta_lock, flags);
242 688
243 priv->stations[sta_id].keyinfo.alg = keyconf->alg; 689 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
244 priv->stations[sta_id].keyinfo.conf = keyconf;
245 priv->stations[sta_id].keyinfo.keylen = 16; 690 priv->stations[sta_id].keyinfo.keylen = 16;
246 priv->stations[sta_id].sta.key.key_offset = 691
692 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
693 == STA_KEY_FLG_NO_ENC)
694 priv->stations[sta_id].sta.key.key_offset =
247 iwl_get_free_ucode_key_index(priv); 695 iwl_get_free_ucode_key_index(priv);
696 /* else, we are overriding an existing key => no need to allocated room
697 * in uCode. */
248 698
249 /* This copy is acutally not needed: we get the key with each TX */ 699 /* This copy is acutally not needed: we get the key with each TX */
250 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, 16); 700 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, 16);
@@ -256,54 +706,84 @@ static int iwl_set_tkip_dynamic_key_info(struct iwl_priv *priv,
256 return ret; 706 return ret;
257} 707}
258 708
259int iwl_remove_dynamic_key(struct iwl_priv *priv, u8 sta_id) 709int iwl_remove_dynamic_key(struct iwl_priv *priv,
710 struct ieee80211_key_conf *keyconf,
711 u8 sta_id)
260{ 712{
261 unsigned long flags; 713 unsigned long flags;
714 int ret = 0;
715 u16 key_flags;
716 u8 keyidx;
262 717
263 priv->key_mapping_key = 0; 718 priv->key_mapping_key--;
264 719
265 spin_lock_irqsave(&priv->sta_lock, flags); 720 spin_lock_irqsave(&priv->sta_lock, flags);
721 key_flags = le16_to_cpu(priv->stations[sta_id].sta.key.key_flags);
722 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
723
724 IWL_DEBUG_WEP("Remove dynamic key: idx=%d sta=%d\n",
725 keyconf->keyidx, sta_id);
726
727 if (keyconf->keyidx != keyidx) {
728 /* We need to remove a key with index different that the one
729 * in the uCode. This means that the key we need to remove has
730 * been replaced by another one with different index.
731 * Don't do anything and return ok
732 */
733 spin_unlock_irqrestore(&priv->sta_lock, flags);
734 return 0;
735 }
736
266 if (!test_and_clear_bit(priv->stations[sta_id].sta.key.key_offset, 737 if (!test_and_clear_bit(priv->stations[sta_id].sta.key.key_offset,
267 &priv->ucode_key_table)) 738 &priv->ucode_key_table))
268 IWL_ERROR("index %d not used in uCode key table.\n", 739 IWL_ERROR("index %d not used in uCode key table.\n",
269 priv->stations[sta_id].sta.key.key_offset); 740 priv->stations[sta_id].sta.key.key_offset);
270 memset(&priv->stations[sta_id].keyinfo, 0, 741 memset(&priv->stations[sta_id].keyinfo, 0,
271 sizeof(struct iwl4965_hw_key)); 742 sizeof(struct iwl_hw_key));
272 memset(&priv->stations[sta_id].sta.key, 0, 743 memset(&priv->stations[sta_id].sta.key, 0,
273 sizeof(struct iwl4965_keyinfo)); 744 sizeof(struct iwl4965_keyinfo));
274 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; 745 priv->stations[sta_id].sta.key.key_flags =
746 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
747 priv->stations[sta_id].sta.key.key_offset = WEP_INVALID_OFFSET;
275 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 748 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
276 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 749 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
277 spin_unlock_irqrestore(&priv->sta_lock, flags);
278 750
279 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n"); 751 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
280 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, 0); 752 spin_unlock_irqrestore(&priv->sta_lock, flags);
753 return ret;
281} 754}
755EXPORT_SYMBOL(iwl_remove_dynamic_key);
282 756
283int iwl_set_dynamic_key(struct iwl_priv *priv, 757int iwl_set_dynamic_key(struct iwl_priv *priv,
284 struct ieee80211_key_conf *key, u8 sta_id) 758 struct ieee80211_key_conf *keyconf, u8 sta_id)
285{ 759{
286 int ret; 760 int ret;
287 761
288 priv->key_mapping_key = 1; 762 priv->key_mapping_key++;
763 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
289 764
290 switch (key->alg) { 765 switch (keyconf->alg) {
291 case ALG_CCMP: 766 case ALG_CCMP:
292 ret = iwl_set_ccmp_dynamic_key_info(priv, key, sta_id); 767 ret = iwl_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
293 break; 768 break;
294 case ALG_TKIP: 769 case ALG_TKIP:
295 ret = iwl_set_tkip_dynamic_key_info(priv, key, sta_id); 770 ret = iwl_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
296 break; 771 break;
297 case ALG_WEP: 772 case ALG_WEP:
298 ret = iwl_set_wep_dynamic_key_info(priv, key, sta_id); 773 ret = iwl_set_wep_dynamic_key_info(priv, keyconf, sta_id);
299 break; 774 break;
300 default: 775 default:
301 IWL_ERROR("Unknown alg: %s alg = %d\n", __func__, key->alg); 776 IWL_ERROR("Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
302 ret = -EINVAL; 777 ret = -EINVAL;
303 } 778 }
304 779
780 IWL_DEBUG_WEP("Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
781 keyconf->alg, keyconf->keylen, keyconf->keyidx,
782 sta_id, ret);
783
305 return ret; 784 return ret;
306} 785}
786EXPORT_SYMBOL(iwl_set_dynamic_key);
307 787
308#ifdef CONFIG_IWLWIFI_DEBUG 788#ifdef CONFIG_IWLWIFI_DEBUG
309static void iwl_dump_lq_cmd(struct iwl_priv *priv, 789static void iwl_dump_lq_cmd(struct iwl_priv *priv,
@@ -345,11 +825,171 @@ int iwl_send_lq_cmd(struct iwl_priv *priv,
345 825
346 iwl_dump_lq_cmd(priv,lq); 826 iwl_dump_lq_cmd(priv,lq);
347 827
348 if (iwl_is_associated(priv) && priv->assoc_station_added && 828 if (iwl_is_associated(priv) && priv->assoc_station_added)
349 priv->lq_mngr.lq_ready)
350 return iwl_send_cmd(priv, &cmd); 829 return iwl_send_cmd(priv, &cmd);
351 830
352 return 0; 831 return 0;
353} 832}
354EXPORT_SYMBOL(iwl_send_lq_cmd); 833EXPORT_SYMBOL(iwl_send_lq_cmd);
355 834
835/**
836 * iwl_sta_init_lq - Initialize a station's hardware rate table
837 *
838 * The uCode's station table contains a table of fallback rates
839 * for automatic fallback during transmission.
840 *
841 * NOTE: This sets up a default set of values. These will be replaced later
842 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
843 * rc80211_simple.
844 *
845 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
846 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
847 * which requires station table entry to exist).
848 */
849static void iwl_sta_init_lq(struct iwl_priv *priv, const u8 *addr, int is_ap)
850{
851 int i, r;
852 struct iwl_link_quality_cmd link_cmd = {
853 .reserved1 = 0,
854 };
855 u16 rate_flags;
856
857 /* Set up the rate scaling to start at selected rate, fall back
858 * all the way down to 1M in IEEE order, and then spin on 1M */
859 if (is_ap)
860 r = IWL_RATE_54M_INDEX;
861 else if (priv->band == IEEE80211_BAND_5GHZ)
862 r = IWL_RATE_6M_INDEX;
863 else
864 r = IWL_RATE_1M_INDEX;
865
866 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
867 rate_flags = 0;
868 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
869 rate_flags |= RATE_MCS_CCK_MSK;
870
871 /* Use Tx antenna B only */
872 rate_flags |= RATE_MCS_ANT_B_MSK; /*FIXME:RS*/
873
874 link_cmd.rs_table[i].rate_n_flags =
875 iwl_hw_set_rate_n_flags(iwl_rates[r].plcp, rate_flags);
876 r = iwl4965_get_prev_ieee_rate(r);
877 }
878
879 link_cmd.general_params.single_stream_ant_msk = 2;
880 link_cmd.general_params.dual_stream_ant_msk = 3;
881 link_cmd.agg_params.agg_dis_start_th = 3;
882 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
883
884 /* Update the rate scaling for control frame Tx to AP */
885 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
886
887 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
888 sizeof(link_cmd), &link_cmd, NULL);
889}
890
891/**
892 * iwl_rxon_add_station - add station into station table.
893 *
894 * there is only one AP station with id= IWL_AP_ID
895 * NOTE: mutex must be held before calling this fnction
896 */
897int iwl_rxon_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
898{
899 u8 sta_id;
900
901 /* Add station to device's station table */
902 struct ieee80211_conf *conf = &priv->hw->conf;
903 struct ieee80211_ht_info *cur_ht_config = &conf->ht_conf;
904
905 if ((is_ap) &&
906 (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) &&
907 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
908 sta_id = iwl_add_station_flags(priv, addr, is_ap,
909 0, cur_ht_config);
910 else
911 sta_id = iwl_add_station_flags(priv, addr, is_ap,
912 0, NULL);
913
914 /* Set up default rate scaling table in device's station table */
915 iwl_sta_init_lq(priv, addr, is_ap);
916
917 return sta_id;
918}
919EXPORT_SYMBOL(iwl_rxon_add_station);
920
921/**
922 * iwl_get_sta_id - Find station's index within station table
923 *
924 * If new IBSS station, create new entry in station table
925 */
926int iwl_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
927{
928 int sta_id;
929 u16 fc = le16_to_cpu(hdr->frame_control);
930 DECLARE_MAC_BUF(mac);
931
932 /* If this frame is broadcast or management, use broadcast station id */
933 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
934 is_multicast_ether_addr(hdr->addr1))
935 return priv->hw_params.bcast_sta_id;
936
937 switch (priv->iw_mode) {
938
939 /* If we are a client station in a BSS network, use the special
940 * AP station entry (that's the only station we communicate with) */
941 case IEEE80211_IF_TYPE_STA:
942 return IWL_AP_ID;
943
944 /* If we are an AP, then find the station, or use BCAST */
945 case IEEE80211_IF_TYPE_AP:
946 sta_id = iwl_find_station(priv, hdr->addr1);
947 if (sta_id != IWL_INVALID_STATION)
948 return sta_id;
949 return priv->hw_params.bcast_sta_id;
950
951 /* If this frame is going out to an IBSS network, find the station,
952 * or create a new station table entry */
953 case IEEE80211_IF_TYPE_IBSS:
954 sta_id = iwl_find_station(priv, hdr->addr1);
955 if (sta_id != IWL_INVALID_STATION)
956 return sta_id;
957
958 /* Create new station table entry */
959 sta_id = iwl_add_station_flags(priv, hdr->addr1,
960 0, CMD_ASYNC, NULL);
961
962 if (sta_id != IWL_INVALID_STATION)
963 return sta_id;
964
965 IWL_DEBUG_DROP("Station %s not in station map. "
966 "Defaulting to broadcast...\n",
967 print_mac(mac, hdr->addr1));
968 iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
969 return priv->hw_params.bcast_sta_id;
970
971 default:
972 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
973 return priv->hw_params.bcast_sta_id;
974 }
975}
976EXPORT_SYMBOL(iwl_get_sta_id);
977
978/**
979 * iwl_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
980 */
981void iwl_sta_modify_enable_tid_tx(struct iwl_priv *priv, int sta_id, int tid)
982{
983 unsigned long flags;
984
985 /* Remove "disable" flag, to enable Tx for this TID */
986 spin_lock_irqsave(&priv->sta_lock, flags);
987 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
988 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
989 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
990 spin_unlock_irqrestore(&priv->sta_lock, flags);
991
992 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
993}
994EXPORT_SYMBOL(iwl_sta_modify_enable_tid_tx);
995
diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.h b/drivers/net/wireless/iwlwifi/iwl-sta.h
index 44f272ecc827..221b93e670a6 100644
--- a/drivers/net/wireless/iwlwifi/iwl-sta.h
+++ b/drivers/net/wireless/iwlwifi/iwl-sta.h
@@ -29,21 +29,27 @@
29#ifndef __iwl_sta_h__ 29#ifndef __iwl_sta_h__
30#define __iwl_sta_h__ 30#define __iwl_sta_h__
31 31
32#include <net/mac80211.h> 32#define HW_KEY_DYNAMIC 0
33#define HW_KEY_DEFAULT 1
33 34
34#include "iwl-eeprom.h" 35/**
35#include "iwl-core.h" 36 * iwl_find_station - Find station id for a given BSSID
36#include "iwl-4965.h" 37 * @bssid: MAC address of station ID to find
37#include "iwl-io.h" 38 */
38#include "iwl-helpers.h" 39u8 iwl_find_station(struct iwl_priv *priv, const u8 *bssid);
39 40
40int iwl_get_free_ucode_key_index(struct iwl_priv *priv);
41int iwl_send_static_wepkey_cmd(struct iwl_priv *priv, u8 send_if_empty); 41int iwl_send_static_wepkey_cmd(struct iwl_priv *priv, u8 send_if_empty);
42int iwl_remove_default_wep_key(struct iwl_priv *priv, 42int iwl_remove_default_wep_key(struct iwl_priv *priv,
43 struct ieee80211_key_conf *key); 43 struct ieee80211_key_conf *key);
44int iwl_set_default_wep_key(struct iwl_priv *priv, 44int iwl_set_default_wep_key(struct iwl_priv *priv,
45 struct ieee80211_key_conf *key); 45 struct ieee80211_key_conf *key);
46int iwl_remove_dynamic_key(struct iwl_priv *priv, u8 sta_id);
47int iwl_set_dynamic_key(struct iwl_priv *priv, 46int iwl_set_dynamic_key(struct iwl_priv *priv,
48 struct ieee80211_key_conf *key, u8 sta_id); 47 struct ieee80211_key_conf *key, u8 sta_id);
48int iwl_remove_dynamic_key(struct iwl_priv *priv,
49 struct ieee80211_key_conf *key, u8 sta_id);
50int iwl_rxon_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap);
51int iwl_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap);
52int iwl_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr);
53void iwl_sta_modify_enable_tid_tx(struct iwl_priv *priv, int sta_id, int tid);
54int iwl_get_ra_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr);
49#endif /* __iwl_sta_h__ */ 55#endif /* __iwl_sta_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c
new file mode 100644
index 000000000000..9b50b1052b09
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-tx.c
@@ -0,0 +1,1519 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#include <linux/etherdevice.h>
31#include <net/mac80211.h>
32#include "iwl-eeprom.h"
33#include "iwl-dev.h"
34#include "iwl-core.h"
35#include "iwl-sta.h"
36#include "iwl-io.h"
37#include "iwl-helpers.h"
38
39static const u16 default_tid_to_tx_fifo[] = {
40 IWL_TX_FIFO_AC1,
41 IWL_TX_FIFO_AC0,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC1,
44 IWL_TX_FIFO_AC2,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC3,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_NONE,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_AC3
57};
58
59
60/**
61 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
62 *
63 * Does NOT advance any TFD circular buffer read/write indexes
64 * Does NOT free the TFD itself (which is within circular buffer)
65 */
66int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
67{
68 struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
69 struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
70 struct pci_dev *dev = priv->pci_dev;
71 int i;
72 int counter = 0;
73 int index, is_odd;
74
75 /* Host command buffers stay mapped in memory, nothing to clean */
76 if (txq->q.id == IWL_CMD_QUEUE_NUM)
77 return 0;
78
79 /* Sanity check on number of chunks */
80 counter = IWL_GET_BITS(*bd, num_tbs);
81 if (counter > MAX_NUM_OF_TBS) {
82 IWL_ERROR("Too many chunks: %i\n", counter);
83 /* @todo issue fatal error, it is quite serious situation */
84 return 0;
85 }
86
87 /* Unmap chunks, if any.
88 * TFD info for odd chunks is different format than for even chunks. */
89 for (i = 0; i < counter; i++) {
90 index = i / 2;
91 is_odd = i & 0x1;
92
93 if (is_odd)
94 pci_unmap_single(
95 dev,
96 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
97 (IWL_GET_BITS(bd->pa[index],
98 tb2_addr_hi20) << 16),
99 IWL_GET_BITS(bd->pa[index], tb2_len),
100 PCI_DMA_TODEVICE);
101
102 else if (i > 0)
103 pci_unmap_single(dev,
104 le32_to_cpu(bd->pa[index].tb1_addr),
105 IWL_GET_BITS(bd->pa[index], tb1_len),
106 PCI_DMA_TODEVICE);
107
108 /* Free SKB, if any, for this chunk */
109 if (txq->txb[txq->q.read_ptr].skb[i]) {
110 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
111
112 dev_kfree_skb(skb);
113 txq->txb[txq->q.read_ptr].skb[i] = NULL;
114 }
115 }
116 return 0;
117}
118EXPORT_SYMBOL(iwl_hw_txq_free_tfd);
119
120
121int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
122 dma_addr_t addr, u16 len)
123{
124 int index, is_odd;
125 struct iwl_tfd_frame *tfd = ptr;
126 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
127
128 /* Each TFD can point to a maximum 20 Tx buffers */
129 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
130 IWL_ERROR("Error can not send more than %d chunks\n",
131 MAX_NUM_OF_TBS);
132 return -EINVAL;
133 }
134
135 index = num_tbs / 2;
136 is_odd = num_tbs & 0x1;
137
138 if (!is_odd) {
139 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
140 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
141 iwl_get_dma_hi_address(addr));
142 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
143 } else {
144 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
145 (u32) (addr & 0xffff));
146 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
147 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
148 }
149
150 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
151
152 return 0;
153}
154EXPORT_SYMBOL(iwl_hw_txq_attach_buf_to_tfd);
155
156/**
157 * iwl_txq_update_write_ptr - Send new write index to hardware
158 */
159int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
160{
161 u32 reg = 0;
162 int ret = 0;
163 int txq_id = txq->q.id;
164
165 if (txq->need_update == 0)
166 return ret;
167
168 /* if we're trying to save power */
169 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
170 /* wake up nic if it's powered down ...
171 * uCode will wake up, and interrupt us again, so next
172 * time we'll skip this part. */
173 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
174
175 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
176 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
177 iwl_set_bit(priv, CSR_GP_CNTRL,
178 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
179 return ret;
180 }
181
182 /* restore this queue's parameters in nic hardware. */
183 ret = iwl_grab_nic_access(priv);
184 if (ret)
185 return ret;
186 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
187 txq->q.write_ptr | (txq_id << 8));
188 iwl_release_nic_access(priv);
189
190 /* else not in power-save mode, uCode will never sleep when we're
191 * trying to tx (during RFKILL, we're not trying to tx). */
192 } else
193 iwl_write32(priv, HBUS_TARG_WRPTR,
194 txq->q.write_ptr | (txq_id << 8));
195
196 txq->need_update = 0;
197
198 return ret;
199}
200EXPORT_SYMBOL(iwl_txq_update_write_ptr);
201
202
203/**
204 * iwl_tx_queue_free - Deallocate DMA queue.
205 * @txq: Transmit queue to deallocate.
206 *
207 * Empty queue by removing and destroying all BD's.
208 * Free all buffers.
209 * 0-fill, but do not free "txq" descriptor structure.
210 */
211static void iwl_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
212{
213 struct iwl_queue *q = &txq->q;
214 struct pci_dev *dev = priv->pci_dev;
215 int len;
216
217 if (q->n_bd == 0)
218 return;
219
220 /* first, empty all BD's */
221 for (; q->write_ptr != q->read_ptr;
222 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
223 iwl_hw_txq_free_tfd(priv, txq);
224
225 len = sizeof(struct iwl_cmd) * q->n_window;
226 if (q->id == IWL_CMD_QUEUE_NUM)
227 len += IWL_MAX_SCAN_SIZE;
228
229 /* De-alloc array of command/tx buffers */
230 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
231
232 /* De-alloc circular buffer of TFDs */
233 if (txq->q.n_bd)
234 pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) *
235 txq->q.n_bd, txq->bd, txq->q.dma_addr);
236
237 /* De-alloc array of per-TFD driver data */
238 kfree(txq->txb);
239 txq->txb = NULL;
240
241 /* 0-fill queue descriptor structure */
242 memset(txq, 0, sizeof(*txq));
243}
244
245/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
246 * DMA services
247 *
248 * Theory of operation
249 *
250 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
251 * of buffer descriptors, each of which points to one or more data buffers for
252 * the device to read from or fill. Driver and device exchange status of each
253 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
254 * entries in each circular buffer, to protect against confusing empty and full
255 * queue states.
256 *
257 * The device reads or writes the data in the queues via the device's several
258 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
259 *
260 * For Tx queue, there are low mark and high mark limits. If, after queuing
261 * the packet for Tx, free space become < low mark, Tx queue stopped. When
262 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
263 * Tx queue resumed.
264 *
265 * See more detailed info in iwl-4965-hw.h.
266 ***************************************************/
267
268int iwl_queue_space(const struct iwl_queue *q)
269{
270 int s = q->read_ptr - q->write_ptr;
271
272 if (q->read_ptr > q->write_ptr)
273 s -= q->n_bd;
274
275 if (s <= 0)
276 s += q->n_window;
277 /* keep some reserve to not confuse empty and full situations */
278 s -= 2;
279 if (s < 0)
280 s = 0;
281 return s;
282}
283EXPORT_SYMBOL(iwl_queue_space);
284
285
286/**
287 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
288 */
289static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
290 int count, int slots_num, u32 id)
291{
292 q->n_bd = count;
293 q->n_window = slots_num;
294 q->id = id;
295
296 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
297 * and iwl_queue_dec_wrap are broken. */
298 BUG_ON(!is_power_of_2(count));
299
300 /* slots_num must be power-of-two size, otherwise
301 * get_cmd_index is broken. */
302 BUG_ON(!is_power_of_2(slots_num));
303
304 q->low_mark = q->n_window / 4;
305 if (q->low_mark < 4)
306 q->low_mark = 4;
307
308 q->high_mark = q->n_window / 8;
309 if (q->high_mark < 2)
310 q->high_mark = 2;
311
312 q->write_ptr = q->read_ptr = 0;
313
314 return 0;
315}
316
317/**
318 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
319 */
320static int iwl_tx_queue_alloc(struct iwl_priv *priv,
321 struct iwl_tx_queue *txq, u32 id)
322{
323 struct pci_dev *dev = priv->pci_dev;
324
325 /* Driver private data, only for Tx (not command) queues,
326 * not shared with device. */
327 if (id != IWL_CMD_QUEUE_NUM) {
328 txq->txb = kmalloc(sizeof(txq->txb[0]) *
329 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
330 if (!txq->txb) {
331 IWL_ERROR("kmalloc for auxiliary BD "
332 "structures failed\n");
333 goto error;
334 }
335 } else
336 txq->txb = NULL;
337
338 /* Circular buffer of transmit frame descriptors (TFDs),
339 * shared with device */
340 txq->bd = pci_alloc_consistent(dev,
341 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
342 &txq->q.dma_addr);
343
344 if (!txq->bd) {
345 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
346 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
347 goto error;
348 }
349 txq->q.id = id;
350
351 return 0;
352
353 error:
354 kfree(txq->txb);
355 txq->txb = NULL;
356
357 return -ENOMEM;
358}
359
360/*
361 * Tell nic where to find circular buffer of Tx Frame Descriptors for
362 * given Tx queue, and enable the DMA channel used for that queue.
363 *
364 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
365 * channels supported in hardware.
366 */
367static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
368 struct iwl_tx_queue *txq)
369{
370 int rc;
371 unsigned long flags;
372 int txq_id = txq->q.id;
373
374 spin_lock_irqsave(&priv->lock, flags);
375 rc = iwl_grab_nic_access(priv);
376 if (rc) {
377 spin_unlock_irqrestore(&priv->lock, flags);
378 return rc;
379 }
380
381 /* Circular buffer (TFD queue in DRAM) physical base address */
382 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
383 txq->q.dma_addr >> 8);
384
385 /* Enable DMA channel, using same id as for TFD queue */
386 iwl_write_direct32(
387 priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
388 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
389 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
390 iwl_release_nic_access(priv);
391 spin_unlock_irqrestore(&priv->lock, flags);
392
393 return 0;
394}
395
396/**
397 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
398 */
399static int iwl_tx_queue_init(struct iwl_priv *priv,
400 struct iwl_tx_queue *txq,
401 int slots_num, u32 txq_id)
402{
403 struct pci_dev *dev = priv->pci_dev;
404 int len;
405 int rc = 0;
406
407 /*
408 * Alloc buffer array for commands (Tx or other types of commands).
409 * For the command queue (#4), allocate command space + one big
410 * command for scan, since scan command is very huge; the system will
411 * not have two scans at the same time, so only one is needed.
412 * For normal Tx queues (all other queues), no super-size command
413 * space is needed.
414 */
415 len = sizeof(struct iwl_cmd) * slots_num;
416 if (txq_id == IWL_CMD_QUEUE_NUM)
417 len += IWL_MAX_SCAN_SIZE;
418 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
419 if (!txq->cmd)
420 return -ENOMEM;
421
422 /* Alloc driver data array and TFD circular buffer */
423 rc = iwl_tx_queue_alloc(priv, txq, txq_id);
424 if (rc) {
425 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
426
427 return -ENOMEM;
428 }
429 txq->need_update = 0;
430
431 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
432 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
433 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
434
435 /* Initialize queue's high/low-water marks, and head/tail indexes */
436 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
437
438 /* Tell device where to find queue */
439 iwl_hw_tx_queue_init(priv, txq);
440
441 return 0;
442}
443/**
444 * iwl_hw_txq_ctx_free - Free TXQ Context
445 *
446 * Destroy all TX DMA queues and structures
447 */
448void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
449{
450 int txq_id;
451
452 /* Tx queues */
453 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
454 iwl_tx_queue_free(priv, &priv->txq[txq_id]);
455
456 /* Keep-warm buffer */
457 iwl_kw_free(priv);
458}
459EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
460
461
462/**
463 * iwl_txq_ctx_reset - Reset TX queue context
464 * Destroys all DMA structures and initialise them again
465 *
466 * @param priv
467 * @return error code
468 */
469int iwl_txq_ctx_reset(struct iwl_priv *priv)
470{
471 int ret = 0;
472 int txq_id, slots_num;
473 unsigned long flags;
474
475 iwl_kw_free(priv);
476
477 /* Free all tx/cmd queues and keep-warm buffer */
478 iwl_hw_txq_ctx_free(priv);
479
480 /* Alloc keep-warm buffer */
481 ret = iwl_kw_alloc(priv);
482 if (ret) {
483 IWL_ERROR("Keep Warm allocation failed");
484 goto error_kw;
485 }
486 spin_lock_irqsave(&priv->lock, flags);
487 ret = iwl_grab_nic_access(priv);
488 if (unlikely(ret)) {
489 spin_unlock_irqrestore(&priv->lock, flags);
490 goto error_reset;
491 }
492
493 /* Turn off all Tx DMA fifos */
494 priv->cfg->ops->lib->txq_set_sched(priv, 0);
495
496 iwl_release_nic_access(priv);
497 spin_unlock_irqrestore(&priv->lock, flags);
498
499
500 /* Tell nic where to find the keep-warm buffer */
501 ret = iwl_kw_init(priv);
502 if (ret) {
503 IWL_ERROR("kw_init failed\n");
504 goto error_reset;
505 }
506
507 /* Alloc and init all Tx queues, including the command queue (#4) */
508 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
509 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
510 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
511 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
512 txq_id);
513 if (ret) {
514 IWL_ERROR("Tx %d queue init failed\n", txq_id);
515 goto error;
516 }
517 }
518
519 return ret;
520
521 error:
522 iwl_hw_txq_ctx_free(priv);
523 error_reset:
524 iwl_kw_free(priv);
525 error_kw:
526 return ret;
527}
528/**
529 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
530 */
531void iwl_txq_ctx_stop(struct iwl_priv *priv)
532{
533
534 int txq_id;
535 unsigned long flags;
536
537
538 /* Turn off all Tx DMA fifos */
539 spin_lock_irqsave(&priv->lock, flags);
540 if (iwl_grab_nic_access(priv)) {
541 spin_unlock_irqrestore(&priv->lock, flags);
542 return;
543 }
544
545 priv->cfg->ops->lib->txq_set_sched(priv, 0);
546
547 /* Stop each Tx DMA channel, and wait for it to be idle */
548 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
549 iwl_write_direct32(priv,
550 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
551 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
552 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
553 (txq_id), 200);
554 }
555 iwl_release_nic_access(priv);
556 spin_unlock_irqrestore(&priv->lock, flags);
557
558 /* Deallocate memory for all Tx queues */
559 iwl_hw_txq_ctx_free(priv);
560}
561EXPORT_SYMBOL(iwl_txq_ctx_stop);
562
563/*
564 * handle build REPLY_TX command notification.
565 */
566static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
567 struct iwl_tx_cmd *tx_cmd,
568 struct ieee80211_tx_info *info,
569 struct ieee80211_hdr *hdr,
570 int is_unicast, u8 std_id)
571{
572 __le16 fc = hdr->frame_control;
573 __le32 tx_flags = tx_cmd->tx_flags;
574
575 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
576 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
577 tx_flags |= TX_CMD_FLG_ACK_MSK;
578 if (ieee80211_is_mgmt(fc))
579 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
580 if (ieee80211_is_probe_resp(fc) &&
581 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
582 tx_flags |= TX_CMD_FLG_TSF_MSK;
583 } else {
584 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
585 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
586 }
587
588 if (ieee80211_is_back_req(fc))
589 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
590
591
592 tx_cmd->sta_id = std_id;
593 if (ieee80211_has_morefrags(fc))
594 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
595
596 if (ieee80211_is_data_qos(fc)) {
597 u8 *qc = ieee80211_get_qos_ctl(hdr);
598 tx_cmd->tid_tspec = qc[0] & 0xf;
599 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
600 } else {
601 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
602 }
603
604 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
605
606 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
607 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
608
609 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
610 if (ieee80211_is_mgmt(fc)) {
611 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
612 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
613 else
614 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
615 } else {
616 tx_cmd->timeout.pm_frame_timeout = 0;
617 }
618
619 tx_cmd->driver_txop = 0;
620 tx_cmd->tx_flags = tx_flags;
621 tx_cmd->next_frame_len = 0;
622}
623
624#define RTS_HCCA_RETRY_LIMIT 3
625#define RTS_DFAULT_RETRY_LIMIT 60
626
627static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
628 struct iwl_tx_cmd *tx_cmd,
629 struct ieee80211_tx_info *info,
630 __le16 fc, int sta_id,
631 int is_hcca)
632{
633 u8 rts_retry_limit = 0;
634 u8 data_retry_limit = 0;
635 u8 rate_plcp;
636 u16 rate_flags = 0;
637 int rate_idx;
638
639 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
640 IWL_RATE_COUNT - 1);
641
642 rate_plcp = iwl_rates[rate_idx].plcp;
643
644 rts_retry_limit = (is_hcca) ?
645 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
646
647 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
648 rate_flags |= RATE_MCS_CCK_MSK;
649
650
651 if (ieee80211_is_probe_resp(fc)) {
652 data_retry_limit = 3;
653 if (data_retry_limit < rts_retry_limit)
654 rts_retry_limit = data_retry_limit;
655 } else
656 data_retry_limit = IWL_DEFAULT_TX_RETRY;
657
658 if (priv->data_retry_limit != -1)
659 data_retry_limit = priv->data_retry_limit;
660
661
662 if (ieee80211_is_data(fc)) {
663 tx_cmd->initial_rate_index = 0;
664 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
665 } else {
666 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
667 case cpu_to_le16(IEEE80211_STYPE_AUTH):
668 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
669 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
670 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
671 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
672 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
673 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
674 }
675 break;
676 default:
677 break;
678 }
679
680 /* Alternate between antenna A and B for successive frames */
681 if (priv->use_ant_b_for_management_frame) {
682 priv->use_ant_b_for_management_frame = 0;
683 rate_flags |= RATE_MCS_ANT_B_MSK;
684 } else {
685 priv->use_ant_b_for_management_frame = 1;
686 rate_flags |= RATE_MCS_ANT_A_MSK;
687 }
688 }
689
690 tx_cmd->rts_retry_limit = rts_retry_limit;
691 tx_cmd->data_retry_limit = data_retry_limit;
692 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
693}
694
695static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
696 struct ieee80211_tx_info *info,
697 struct iwl_tx_cmd *tx_cmd,
698 struct sk_buff *skb_frag,
699 int sta_id)
700{
701 struct ieee80211_key_conf *keyconf = info->control.hw_key;
702
703 switch (keyconf->alg) {
704 case ALG_CCMP:
705 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
706 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
707 if (info->flags & IEEE80211_TX_CTL_AMPDU)
708 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
709 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
710 break;
711
712 case ALG_TKIP:
713 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
714 ieee80211_get_tkip_key(keyconf, skb_frag,
715 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
716 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
717 break;
718
719 case ALG_WEP:
720 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
721 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
722
723 if (keyconf->keylen == WEP_KEY_LEN_128)
724 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
725
726 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
727
728 IWL_DEBUG_TX("Configuring packet for WEP encryption "
729 "with key %d\n", keyconf->keyidx);
730 break;
731
732 default:
733 printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg);
734 break;
735 }
736}
737
738static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
739{
740 /* 0 - mgmt, 1 - cnt, 2 - data */
741 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
742 priv->tx_stats[idx].cnt++;
743 priv->tx_stats[idx].bytes += len;
744}
745
746/*
747 * start REPLY_TX command process
748 */
749int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
750{
751 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
752 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
753 struct iwl_tfd_frame *tfd;
754 u32 *control_flags;
755 int txq_id = skb_get_queue_mapping(skb);
756 struct iwl_tx_queue *txq = NULL;
757 struct iwl_queue *q = NULL;
758 dma_addr_t phys_addr;
759 dma_addr_t txcmd_phys;
760 dma_addr_t scratch_phys;
761 struct iwl_cmd *out_cmd = NULL;
762 struct iwl_tx_cmd *tx_cmd;
763 u16 len, idx, len_org;
764 u16 seq_number = 0;
765 u8 id, hdr_len, unicast;
766 u8 sta_id;
767 __le16 fc;
768 u8 wait_write_ptr = 0;
769 u8 tid = 0;
770 u8 *qc = NULL;
771 unsigned long flags;
772 int ret;
773
774 spin_lock_irqsave(&priv->lock, flags);
775 if (iwl_is_rfkill(priv)) {
776 IWL_DEBUG_DROP("Dropping - RF KILL\n");
777 goto drop_unlock;
778 }
779
780 if (!priv->vif) {
781 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
782 goto drop_unlock;
783 }
784
785 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
786 IWL_INVALID_RATE) {
787 IWL_ERROR("ERROR: No TX rate available.\n");
788 goto drop_unlock;
789 }
790
791 unicast = !is_multicast_ether_addr(hdr->addr1);
792 id = 0;
793
794 fc = hdr->frame_control;
795
796#ifdef CONFIG_IWLWIFI_DEBUG
797 if (ieee80211_is_auth(fc))
798 IWL_DEBUG_TX("Sending AUTH frame\n");
799 else if (ieee80211_is_assoc_req(fc))
800 IWL_DEBUG_TX("Sending ASSOC frame\n");
801 else if (ieee80211_is_reassoc_req(fc))
802 IWL_DEBUG_TX("Sending REASSOC frame\n");
803#endif
804
805 /* drop all data frame if we are not associated */
806 if (ieee80211_is_data(fc) &&
807 (!iwl_is_associated(priv) ||
808 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) ||
809 !priv->assoc_station_added)) {
810 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
811 goto drop_unlock;
812 }
813
814 spin_unlock_irqrestore(&priv->lock, flags);
815
816 hdr_len = ieee80211_get_hdrlen(le16_to_cpu(fc));
817
818 /* Find (or create) index into station table for destination station */
819 sta_id = iwl_get_sta_id(priv, hdr);
820 if (sta_id == IWL_INVALID_STATION) {
821 DECLARE_MAC_BUF(mac);
822
823 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
824 print_mac(mac, hdr->addr1));
825 goto drop;
826 }
827
828 IWL_DEBUG_TX("station Id %d\n", sta_id);
829
830 if (ieee80211_is_data_qos(fc)) {
831 qc = ieee80211_get_qos_ctl(hdr);
832 tid = qc[0] & 0xf;
833 seq_number = priv->stations[sta_id].tid[tid].seq_number &
834 IEEE80211_SCTL_SEQ;
835 hdr->seq_ctrl = cpu_to_le16(seq_number) |
836 (hdr->seq_ctrl &
837 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
838 seq_number += 0x10;
839 /* aggregation is on for this <sta,tid> */
840 if (info->flags & IEEE80211_TX_CTL_AMPDU)
841 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
842 priv->stations[sta_id].tid[tid].tfds_in_queue++;
843 }
844
845 /* Descriptor for chosen Tx queue */
846 txq = &priv->txq[txq_id];
847 q = &txq->q;
848
849 spin_lock_irqsave(&priv->lock, flags);
850
851 /* Set up first empty TFD within this queue's circular TFD buffer */
852 tfd = &txq->bd[q->write_ptr];
853 memset(tfd, 0, sizeof(*tfd));
854 control_flags = (u32 *) tfd;
855 idx = get_cmd_index(q, q->write_ptr, 0);
856
857 /* Set up driver data for this TFD */
858 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
859 txq->txb[q->write_ptr].skb[0] = skb;
860
861 /* Set up first empty entry in queue's array of Tx/cmd buffers */
862 out_cmd = &txq->cmd[idx];
863 tx_cmd = &out_cmd->cmd.tx;
864 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
865 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
866
867 /*
868 * Set up the Tx-command (not MAC!) header.
869 * Store the chosen Tx queue and TFD index within the sequence field;
870 * after Tx, uCode's Tx response will return this value so driver can
871 * locate the frame within the tx queue and do post-tx processing.
872 */
873 out_cmd->hdr.cmd = REPLY_TX;
874 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
875 INDEX_TO_SEQ(q->write_ptr)));
876
877 /* Copy MAC header from skb into command buffer */
878 memcpy(tx_cmd->hdr, hdr, hdr_len);
879
880 /*
881 * Use the first empty entry in this queue's command buffer array
882 * to contain the Tx command and MAC header concatenated together
883 * (payload data will be in another buffer).
884 * Size of this varies, due to varying MAC header length.
885 * If end is not dword aligned, we'll have 2 extra bytes at the end
886 * of the MAC header (device reads on dword boundaries).
887 * We'll tell device about this padding later.
888 */
889 len = sizeof(struct iwl_tx_cmd) +
890 sizeof(struct iwl_cmd_header) + hdr_len;
891
892 len_org = len;
893 len = (len + 3) & ~3;
894
895 if (len_org != len)
896 len_org = 1;
897 else
898 len_org = 0;
899
900 /* Physical address of this Tx command's header (not MAC header!),
901 * within command buffer array. */
902 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx +
903 offsetof(struct iwl_cmd, hdr);
904
905 /* Add buffer containing Tx command and MAC(!) header to TFD's
906 * first entry */
907 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
908
909 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT))
910 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
911
912 /* Set up TFD's 2nd entry to point directly to remainder of skb,
913 * if any (802.11 null frames have no payload). */
914 len = skb->len - hdr_len;
915 if (len) {
916 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
917 len, PCI_DMA_TODEVICE);
918 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
919 }
920
921 /* Tell NIC about any 2-byte padding after MAC header */
922 if (len_org)
923 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
924
925 /* Total # bytes to be transmitted */
926 len = (u16)skb->len;
927 tx_cmd->len = cpu_to_le16(len);
928 /* TODO need this for burst mode later on */
929 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id);
930
931 /* set is_hcca to 0; it probably will never be implemented */
932 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
933
934 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
935
936 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
937 offsetof(struct iwl_tx_cmd, scratch);
938 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
939 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys);
940
941 if (!ieee80211_has_morefrags(hdr->frame_control)) {
942 txq->need_update = 1;
943 if (qc)
944 priv->stations[sta_id].tid[tid].seq_number = seq_number;
945 } else {
946 wait_write_ptr = 1;
947 txq->need_update = 0;
948 }
949
950 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
951
952 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
953
954 /* Set up entry for this TFD in Tx byte-count array */
955 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
956
957 /* Tell device the write index *just past* this latest filled TFD */
958 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
959 ret = iwl_txq_update_write_ptr(priv, txq);
960 spin_unlock_irqrestore(&priv->lock, flags);
961
962 if (ret)
963 return ret;
964
965 if ((iwl_queue_space(q) < q->high_mark)
966 && priv->mac80211_registered) {
967 if (wait_write_ptr) {
968 spin_lock_irqsave(&priv->lock, flags);
969 txq->need_update = 1;
970 iwl_txq_update_write_ptr(priv, txq);
971 spin_unlock_irqrestore(&priv->lock, flags);
972 }
973
974 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
975 }
976
977 return 0;
978
979drop_unlock:
980 spin_unlock_irqrestore(&priv->lock, flags);
981drop:
982 return -1;
983}
984EXPORT_SYMBOL(iwl_tx_skb);
985
986/*************** HOST COMMAND QUEUE FUNCTIONS *****/
987
988/**
989 * iwl_enqueue_hcmd - enqueue a uCode command
990 * @priv: device private data point
991 * @cmd: a point to the ucode command structure
992 *
993 * The function returns < 0 values to indicate the operation is
994 * failed. On success, it turns the index (> 0) of command in the
995 * command queue.
996 */
997int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
998{
999 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1000 struct iwl_queue *q = &txq->q;
1001 struct iwl_tfd_frame *tfd;
1002 u32 *control_flags;
1003 struct iwl_cmd *out_cmd;
1004 u32 idx;
1005 u16 fix_size;
1006 dma_addr_t phys_addr;
1007 int ret;
1008 unsigned long flags;
1009
1010 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1011 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1012
1013 /* If any of the command structures end up being larger than
1014 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1015 * we will need to increase the size of the TFD entries */
1016 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1017 !(cmd->meta.flags & CMD_SIZE_HUGE));
1018
1019 if (iwl_is_rfkill(priv)) {
1020 IWL_DEBUG_INFO("Not sending command - RF KILL");
1021 return -EIO;
1022 }
1023
1024 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
1025 IWL_ERROR("No space for Tx\n");
1026 return -ENOSPC;
1027 }
1028
1029 spin_lock_irqsave(&priv->hcmd_lock, flags);
1030
1031 tfd = &txq->bd[q->write_ptr];
1032 memset(tfd, 0, sizeof(*tfd));
1033
1034 control_flags = (u32 *) tfd;
1035
1036 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
1037 out_cmd = &txq->cmd[idx];
1038
1039 out_cmd->hdr.cmd = cmd->id;
1040 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
1041 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1042
1043 /* At this point, the out_cmd now has all of the incoming cmd
1044 * information */
1045
1046 out_cmd->hdr.flags = 0;
1047 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1048 INDEX_TO_SEQ(q->write_ptr));
1049 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
1050 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
1051
1052 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
1053 offsetof(struct iwl_cmd, hdr);
1054 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
1055
1056 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1057 "%d bytes at %d[%d]:%d\n",
1058 get_cmd_string(out_cmd->hdr.cmd),
1059 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1060 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1061
1062 txq->need_update = 1;
1063
1064 /* Set up entry in queue's byte count circular buffer */
1065 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1066
1067 /* Increment and update queue's write index */
1068 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1069 ret = iwl_txq_update_write_ptr(priv, txq);
1070
1071 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1072 return ret ? ret : idx;
1073}
1074
1075int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1076{
1077 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1078 struct iwl_queue *q = &txq->q;
1079 struct iwl_tx_info *tx_info;
1080 int nfreed = 0;
1081
1082 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1083 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1084 "is out of range [0-%d] %d %d.\n", txq_id,
1085 index, q->n_bd, q->write_ptr, q->read_ptr);
1086 return 0;
1087 }
1088
1089 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1090 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1091
1092 tx_info = &txq->txb[txq->q.read_ptr];
1093 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1094 tx_info->skb[0] = NULL;
1095
1096 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1097 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1098
1099 iwl_hw_txq_free_tfd(priv, txq);
1100 nfreed++;
1101 }
1102 return nfreed;
1103}
1104EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1105
1106
1107/**
1108 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1109 *
1110 * When FW advances 'R' index, all entries between old and new 'R' index
1111 * need to be reclaimed. As result, some free space forms. If there is
1112 * enough free space (> low mark), wake the stack that feeds us.
1113 */
1114static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1115{
1116 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1117 struct iwl_queue *q = &txq->q;
1118 int nfreed = 0;
1119
1120 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1121 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1122 "is out of range [0-%d] %d %d.\n", txq_id,
1123 index, q->n_bd, q->write_ptr, q->read_ptr);
1124 return;
1125 }
1126
1127 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1128 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1129
1130 if (nfreed > 1) {
1131 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
1132 q->write_ptr, q->read_ptr);
1133 queue_work(priv->workqueue, &priv->restart);
1134 }
1135 nfreed++;
1136 }
1137}
1138
1139/**
1140 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1141 * @rxb: Rx buffer to reclaim
1142 *
1143 * If an Rx buffer has an async callback associated with it the callback
1144 * will be executed. The attached skb (if present) will only be freed
1145 * if the callback returns 1
1146 */
1147void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1148{
1149 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1150 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1151 int txq_id = SEQ_TO_QUEUE(sequence);
1152 int index = SEQ_TO_INDEX(sequence);
1153 int huge = sequence & SEQ_HUGE_FRAME;
1154 int cmd_index;
1155 struct iwl_cmd *cmd;
1156
1157 /* If a Tx command is being handled and it isn't in the actual
1158 * command queue then there a command routing bug has been introduced
1159 * in the queue management code. */
1160 if (txq_id != IWL_CMD_QUEUE_NUM)
1161 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
1162 txq_id, pkt->hdr.cmd);
1163 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
1164
1165 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1166 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1167
1168 /* Input error checking is done when commands are added to queue. */
1169 if (cmd->meta.flags & CMD_WANT_SKB) {
1170 cmd->meta.source->u.skb = rxb->skb;
1171 rxb->skb = NULL;
1172 } else if (cmd->meta.u.callback &&
1173 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1174 rxb->skb = NULL;
1175
1176 iwl_hcmd_queue_reclaim(priv, txq_id, index);
1177
1178 if (!(cmd->meta.flags & CMD_ASYNC)) {
1179 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1180 wake_up_interruptible(&priv->wait_command_queue);
1181 }
1182}
1183EXPORT_SYMBOL(iwl_tx_cmd_complete);
1184
1185/*
1186 * Find first available (lowest unused) Tx Queue, mark it "active".
1187 * Called only when finding queue for aggregation.
1188 * Should never return anything < 7, because they should already
1189 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1190 */
1191static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1192{
1193 int txq_id;
1194
1195 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1196 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1197 return txq_id;
1198 return -1;
1199}
1200
1201int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1202{
1203 int sta_id;
1204 int tx_fifo;
1205 int txq_id;
1206 int ret;
1207 unsigned long flags;
1208 struct iwl_tid_data *tid_data;
1209 DECLARE_MAC_BUF(mac);
1210
1211 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1212 tx_fifo = default_tid_to_tx_fifo[tid];
1213 else
1214 return -EINVAL;
1215
1216 IWL_WARNING("%s on ra = %s tid = %d\n",
1217 __func__, print_mac(mac, ra), tid);
1218
1219 sta_id = iwl_find_station(priv, ra);
1220 if (sta_id == IWL_INVALID_STATION)
1221 return -ENXIO;
1222
1223 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1224 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
1225 return -ENXIO;
1226 }
1227
1228 txq_id = iwl_txq_ctx_activate_free(priv);
1229 if (txq_id == -1)
1230 return -ENXIO;
1231
1232 spin_lock_irqsave(&priv->sta_lock, flags);
1233 tid_data = &priv->stations[sta_id].tid[tid];
1234 *ssn = SEQ_TO_SN(tid_data->seq_number);
1235 tid_data->agg.txq_id = txq_id;
1236 spin_unlock_irqrestore(&priv->sta_lock, flags);
1237
1238 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1239 sta_id, tid, *ssn);
1240 if (ret)
1241 return ret;
1242
1243 if (tid_data->tfds_in_queue == 0) {
1244 printk(KERN_ERR "HW queue is empty\n");
1245 tid_data->agg.state = IWL_AGG_ON;
1246 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1247 } else {
1248 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1249 tid_data->tfds_in_queue);
1250 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1251 }
1252 return ret;
1253}
1254EXPORT_SYMBOL(iwl_tx_agg_start);
1255
1256int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1257{
1258 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1259 struct iwl_tid_data *tid_data;
1260 int ret, write_ptr, read_ptr;
1261 unsigned long flags;
1262 DECLARE_MAC_BUF(mac);
1263
1264 if (!ra) {
1265 IWL_ERROR("ra = NULL\n");
1266 return -EINVAL;
1267 }
1268
1269 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1270 tx_fifo_id = default_tid_to_tx_fifo[tid];
1271 else
1272 return -EINVAL;
1273
1274 sta_id = iwl_find_station(priv, ra);
1275
1276 if (sta_id == IWL_INVALID_STATION)
1277 return -ENXIO;
1278
1279 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1280 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
1281
1282 tid_data = &priv->stations[sta_id].tid[tid];
1283 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1284 txq_id = tid_data->agg.txq_id;
1285 write_ptr = priv->txq[txq_id].q.write_ptr;
1286 read_ptr = priv->txq[txq_id].q.read_ptr;
1287
1288 /* The queue is not empty */
1289 if (write_ptr != read_ptr) {
1290 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1291 priv->stations[sta_id].tid[tid].agg.state =
1292 IWL_EMPTYING_HW_QUEUE_DELBA;
1293 return 0;
1294 }
1295
1296 IWL_DEBUG_HT("HW queue is empty\n");
1297 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1298
1299 spin_lock_irqsave(&priv->lock, flags);
1300 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1301 tx_fifo_id);
1302 spin_unlock_irqrestore(&priv->lock, flags);
1303
1304 if (ret)
1305 return ret;
1306
1307 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1308
1309 return 0;
1310}
1311EXPORT_SYMBOL(iwl_tx_agg_stop);
1312
1313int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1314{
1315 struct iwl_queue *q = &priv->txq[txq_id].q;
1316 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1317 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1318
1319 switch (priv->stations[sta_id].tid[tid].agg.state) {
1320 case IWL_EMPTYING_HW_QUEUE_DELBA:
1321 /* We are reclaiming the last packet of the */
1322 /* aggregated HW queue */
1323 if (txq_id == tid_data->agg.txq_id &&
1324 q->read_ptr == q->write_ptr) {
1325 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1326 int tx_fifo = default_tid_to_tx_fifo[tid];
1327 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1328 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1329 ssn, tx_fifo);
1330 tid_data->agg.state = IWL_AGG_OFF;
1331 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1332 }
1333 break;
1334 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1335 /* We are reclaiming the last packet of the queue */
1336 if (tid_data->tfds_in_queue == 0) {
1337 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1338 tid_data->agg.state = IWL_AGG_ON;
1339 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1340 }
1341 break;
1342 }
1343 return 0;
1344}
1345EXPORT_SYMBOL(iwl_txq_check_empty);
1346
1347/**
1348 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1349 *
1350 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1351 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1352 */
1353static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1354 struct iwl_ht_agg *agg,
1355 struct iwl_compressed_ba_resp *ba_resp)
1356
1357{
1358 int i, sh, ack;
1359 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1360 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1361 u64 bitmap;
1362 int successes = 0;
1363 struct ieee80211_tx_info *info;
1364
1365 if (unlikely(!agg->wait_for_ba)) {
1366 IWL_ERROR("Received BA when not expected\n");
1367 return -EINVAL;
1368 }
1369
1370 /* Mark that the expected block-ack response arrived */
1371 agg->wait_for_ba = 0;
1372 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1373
1374 /* Calculate shift to align block-ack bits with our Tx window bits */
1375 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
1376 if (sh < 0) /* tbw something is wrong with indices */
1377 sh += 0x100;
1378
1379 /* don't use 64-bit values for now */
1380 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1381
1382 if (agg->frame_count > (64 - sh)) {
1383 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
1384 return -1;
1385 }
1386
1387 /* check for success or failure according to the
1388 * transmitted bitmap and block-ack bitmap */
1389 bitmap &= agg->bitmap;
1390
1391 /* For each frame attempted in aggregation,
1392 * update driver's record of tx frame's status. */
1393 for (i = 0; i < agg->frame_count ; i++) {
1394 ack = bitmap & (1 << i);
1395 successes += !!ack;
1396 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
1397 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
1398 agg->start_idx + i);
1399 }
1400
1401 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1402 memset(&info->status, 0, sizeof(info->status));
1403 info->flags = IEEE80211_TX_STAT_ACK;
1404 info->flags |= IEEE80211_TX_STAT_AMPDU;
1405 info->status.ampdu_ack_map = successes;
1406 info->status.ampdu_ack_len = agg->frame_count;
1407 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1408
1409 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
1410
1411 return 0;
1412}
1413
1414/**
1415 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1416 *
1417 * Handles block-acknowledge notification from device, which reports success
1418 * of frames sent via aggregation.
1419 */
1420void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1421 struct iwl_rx_mem_buffer *rxb)
1422{
1423 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1424 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1425 int index;
1426 struct iwl_tx_queue *txq = NULL;
1427 struct iwl_ht_agg *agg;
1428 DECLARE_MAC_BUF(mac);
1429
1430 /* "flow" corresponds to Tx queue */
1431 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1432
1433 /* "ssn" is start of block-ack Tx window, corresponds to index
1434 * (in Tx queue's circular buffer) of first TFD/frame in window */
1435 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1436
1437 if (scd_flow >= priv->hw_params.max_txq_num) {
1438 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
1439 return;
1440 }
1441
1442 txq = &priv->txq[scd_flow];
1443 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
1444
1445 /* Find index just before block-ack window */
1446 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1447
1448 /* TODO: Need to get this copy more safely - now good for debug */
1449
1450 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
1451 "sta_id = %d\n",
1452 agg->wait_for_ba,
1453 print_mac(mac, (u8 *) &ba_resp->sta_addr_lo32),
1454 ba_resp->sta_id);
1455 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1456 "%d, scd_ssn = %d\n",
1457 ba_resp->tid,
1458 ba_resp->seq_ctl,
1459 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1460 ba_resp->scd_flow,
1461 ba_resp->scd_ssn);
1462 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
1463 agg->start_idx,
1464 (unsigned long long)agg->bitmap);
1465
1466 /* Update driver's record of ACK vs. not for each frame in window */
1467 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1468
1469 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1470 * block-ack window (we assume that they've been successfully
1471 * transmitted ... if not, it's too late anyway). */
1472 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1473 /* calculate mac80211 ampdu sw queue to wake */
1474 int ampdu_q =
1475 scd_flow - priv->hw_params.first_ampdu_q + priv->hw->queues;
1476 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1477 priv->stations[ba_resp->sta_id].
1478 tid[ba_resp->tid].tfds_in_queue -= freed;
1479 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1480 priv->mac80211_registered &&
1481 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
1482 ieee80211_wake_queue(priv->hw, ampdu_q);
1483
1484 iwl_txq_check_empty(priv, ba_resp->sta_id,
1485 ba_resp->tid, scd_flow);
1486 }
1487}
1488EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1489
1490#ifdef CONFIG_IWLWIFI_DEBUG
1491#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1492
1493const char *iwl_get_tx_fail_reason(u32 status)
1494{
1495 switch (status & TX_STATUS_MSK) {
1496 case TX_STATUS_SUCCESS:
1497 return "SUCCESS";
1498 TX_STATUS_ENTRY(SHORT_LIMIT);
1499 TX_STATUS_ENTRY(LONG_LIMIT);
1500 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1501 TX_STATUS_ENTRY(MGMNT_ABORT);
1502 TX_STATUS_ENTRY(NEXT_FRAG);
1503 TX_STATUS_ENTRY(LIFE_EXPIRE);
1504 TX_STATUS_ENTRY(DEST_PS);
1505 TX_STATUS_ENTRY(ABORTED);
1506 TX_STATUS_ENTRY(BT_RETRY);
1507 TX_STATUS_ENTRY(STA_INVALID);
1508 TX_STATUS_ENTRY(FRAG_DROPPED);
1509 TX_STATUS_ENTRY(TID_DISABLE);
1510 TX_STATUS_ENTRY(FRAME_FLUSHED);
1511 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1512 TX_STATUS_ENTRY(TX_LOCKED);
1513 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1514 }
1515
1516 return "UNKNOWN";
1517}
1518EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1519#endif /* CONFIG_IWLWIFI_DEBUG */
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index 6027e1119c3f..4a22d3fba75b 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -102,16 +102,6 @@ MODULE_VERSION(DRV_VERSION);
102MODULE_AUTHOR(DRV_COPYRIGHT); 102MODULE_AUTHOR(DRV_COPYRIGHT);
103MODULE_LICENSE("GPL"); 103MODULE_LICENSE("GPL");
104 104
105static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
106{
107 u16 fc = le16_to_cpu(hdr->frame_control);
108 int hdr_len = ieee80211_get_hdrlen(fc);
109
110 if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
111 return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
112 return NULL;
113}
114
115static const struct ieee80211_supported_band *iwl3945_get_band( 105static const struct ieee80211_supported_band *iwl3945_get_band(
116 struct iwl3945_priv *priv, enum ieee80211_band band) 106 struct iwl3945_priv *priv, enum ieee80211_band band)
117{ 107{
@@ -547,10 +537,20 @@ static inline int iwl3945_is_init(struct iwl3945_priv *priv)
547 return test_bit(STATUS_INIT, &priv->status); 537 return test_bit(STATUS_INIT, &priv->status);
548} 538}
549 539
540static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
541{
542 return test_bit(STATUS_RF_KILL_SW, &priv->status);
543}
544
545static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
546{
547 return test_bit(STATUS_RF_KILL_HW, &priv->status);
548}
549
550static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv) 550static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
551{ 551{
552 return test_bit(STATUS_RF_KILL_HW, &priv->status) || 552 return iwl3945_is_rfkill_hw(priv) ||
553 test_bit(STATUS_RF_KILL_SW, &priv->status); 553 iwl3945_is_rfkill_sw(priv);
554} 554}
555 555
556static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv) 556static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
@@ -980,7 +980,7 @@ static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
980{ 980{
981 981
982 /* These items are only settable from the full RXON command */ 982 /* These items are only settable from the full RXON command */
983 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) || 983 if (!(iwl3945_is_associated(priv)) ||
984 compare_ether_addr(priv->staging_rxon.bssid_addr, 984 compare_ether_addr(priv->staging_rxon.bssid_addr,
985 priv->active_rxon.bssid_addr) || 985 priv->active_rxon.bssid_addr) ||
986 compare_ether_addr(priv->staging_rxon.node_addr, 986 compare_ether_addr(priv->staging_rxon.node_addr,
@@ -2035,36 +2035,6 @@ static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
2035 return rc; 2035 return rc;
2036} 2036}
2037 2037
2038int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
2039{
2040 /* Filter incoming packets to determine if they are targeted toward
2041 * this network, discarding packets coming from ourselves */
2042 switch (priv->iw_mode) {
2043 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2044 /* packets from our adapter are dropped (echo) */
2045 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2046 return 0;
2047 /* {broad,multi}cast packets to our IBSS go through */
2048 if (is_multicast_ether_addr(header->addr1))
2049 return !compare_ether_addr(header->addr3, priv->bssid);
2050 /* packets to our adapter go through */
2051 return !compare_ether_addr(header->addr1, priv->mac_addr);
2052 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2053 /* packets from our adapter are dropped (echo) */
2054 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2055 return 0;
2056 /* {broad,multi}cast packets to our BSS go through */
2057 if (is_multicast_ether_addr(header->addr1))
2058 return !compare_ether_addr(header->addr2, priv->bssid);
2059 /* packets to our adapter go through */
2060 return !compare_ether_addr(header->addr1, priv->mac_addr);
2061 default:
2062 return 1;
2063 }
2064
2065 return 1;
2066}
2067
2068/** 2038/**
2069 * iwl3945_scan_cancel - Cancel any currently executing HW scan 2039 * iwl3945_scan_cancel - Cancel any currently executing HW scan
2070 * 2040 *
@@ -2117,20 +2087,6 @@ static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long
2117 return ret; 2087 return ret;
2118} 2088}
2119 2089
2120static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
2121{
2122 /* Reset ieee stats */
2123
2124 /* We don't reset the net_device_stats (ieee->stats) on
2125 * re-association */
2126
2127 priv->last_seq_num = -1;
2128 priv->last_frag_num = -1;
2129 priv->last_packet_time = 0;
2130
2131 iwl3945_scan_cancel(priv);
2132}
2133
2134#define MAX_UCODE_BEACON_INTERVAL 1024 2090#define MAX_UCODE_BEACON_INTERVAL 1024
2135#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA) 2091#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2136 2092
@@ -2322,7 +2278,7 @@ static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
2322#endif 2278#endif
2323 2279
2324 ch_info = iwl3945_get_channel_info(priv, priv->band, 2280 ch_info = iwl3945_get_channel_info(priv, priv->band,
2325 le16_to_cpu(priv->staging_rxon.channel)); 2281 le16_to_cpu(priv->active_rxon.channel));
2326 2282
2327 if (!ch_info) 2283 if (!ch_info)
2328 ch_info = &priv->channel_info[0]; 2284 ch_info = &priv->channel_info[0];
@@ -2389,12 +2345,13 @@ static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
2389} 2345}
2390 2346
2391static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv, 2347static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
2392 struct ieee80211_tx_control *ctl, 2348 struct ieee80211_tx_info *info,
2393 struct iwl3945_cmd *cmd, 2349 struct iwl3945_cmd *cmd,
2394 struct sk_buff *skb_frag, 2350 struct sk_buff *skb_frag,
2395 int last_frag) 2351 int last_frag)
2396{ 2352{
2397 struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo; 2353 struct iwl3945_hw_key *keyinfo =
2354 &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
2398 2355
2399 switch (keyinfo->alg) { 2356 switch (keyinfo->alg) {
2400 case ALG_CCMP: 2357 case ALG_CCMP:
@@ -2417,7 +2374,7 @@ static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
2417 2374
2418 case ALG_WEP: 2375 case ALG_WEP:
2419 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP | 2376 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
2420 (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; 2377 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
2421 2378
2422 if (keyinfo->keylen == 13) 2379 if (keyinfo->keylen == 13)
2423 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128; 2380 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
@@ -2425,7 +2382,7 @@ static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
2425 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen); 2382 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2426 2383
2427 IWL_DEBUG_TX("Configuring packet for WEP encryption " 2384 IWL_DEBUG_TX("Configuring packet for WEP encryption "
2428 "with key %d\n", ctl->key_idx); 2385 "with key %d\n", info->control.hw_key->hw_key_idx);
2429 break; 2386 break;
2430 2387
2431 default: 2388 default:
@@ -2439,20 +2396,19 @@ static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
2439 */ 2396 */
2440static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv, 2397static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2441 struct iwl3945_cmd *cmd, 2398 struct iwl3945_cmd *cmd,
2442 struct ieee80211_tx_control *ctrl, 2399 struct ieee80211_tx_info *info,
2443 struct ieee80211_hdr *hdr, 2400 struct ieee80211_hdr *hdr,
2444 int is_unicast, u8 std_id) 2401 int is_unicast, u8 std_id)
2445{ 2402{
2446 __le16 *qc; 2403 __le16 fc = hdr->frame_control;
2447 u16 fc = le16_to_cpu(hdr->frame_control);
2448 __le32 tx_flags = cmd->cmd.tx.tx_flags; 2404 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2449 2405
2450 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 2406 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2451 if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) { 2407 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
2452 tx_flags |= TX_CMD_FLG_ACK_MSK; 2408 tx_flags |= TX_CMD_FLG_ACK_MSK;
2453 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) 2409 if (ieee80211_is_mgmt(fc))
2454 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 2410 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2455 if (ieee80211_is_probe_response(fc) && 2411 if (ieee80211_is_probe_resp(fc) &&
2456 !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) 2412 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2457 tx_flags |= TX_CMD_FLG_TSF_MSK; 2413 tx_flags |= TX_CMD_FLG_TSF_MSK;
2458 } else { 2414 } else {
@@ -2461,20 +2417,21 @@ static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2461 } 2417 }
2462 2418
2463 cmd->cmd.tx.sta_id = std_id; 2419 cmd->cmd.tx.sta_id = std_id;
2464 if (ieee80211_get_morefrag(hdr)) 2420 if (ieee80211_has_morefrags(fc))
2465 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; 2421 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2466 2422
2467 qc = ieee80211_get_qos_ctrl(hdr); 2423 if (ieee80211_is_data_qos(fc)) {
2468 if (qc) { 2424 u8 *qc = ieee80211_get_qos_ctl(hdr);
2469 cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf); 2425 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
2470 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; 2426 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2471 } else 2427 } else {
2472 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 2428 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2429 }
2473 2430
2474 if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) { 2431 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
2475 tx_flags |= TX_CMD_FLG_RTS_MSK; 2432 tx_flags |= TX_CMD_FLG_RTS_MSK;
2476 tx_flags &= ~TX_CMD_FLG_CTS_MSK; 2433 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2477 } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) { 2434 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
2478 tx_flags &= ~TX_CMD_FLG_RTS_MSK; 2435 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2479 tx_flags |= TX_CMD_FLG_CTS_MSK; 2436 tx_flags |= TX_CMD_FLG_CTS_MSK;
2480 } 2437 }
@@ -2483,9 +2440,8 @@ static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2483 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; 2440 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2484 2441
2485 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); 2442 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2486 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) { 2443 if (ieee80211_is_mgmt(fc)) {
2487 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ || 2444 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
2488 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
2489 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3); 2445 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
2490 else 2446 else
2491 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2); 2447 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
@@ -2549,6 +2505,11 @@ static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *h
2549 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr)); 2505 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
2550 return priv->hw_setting.bcast_sta_id; 2506 return priv->hw_setting.bcast_sta_id;
2551 } 2507 }
2508 /* If we are in monitor mode, use BCAST. This is required for
2509 * packet injection. */
2510 case IEEE80211_IF_TYPE_MNTR:
2511 return priv->hw_setting.bcast_sta_id;
2512
2552 default: 2513 default:
2553 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode); 2514 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
2554 return priv->hw_setting.bcast_sta_id; 2515 return priv->hw_setting.bcast_sta_id;
@@ -2558,25 +2519,27 @@ static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *h
2558/* 2519/*
2559 * start REPLY_TX command process 2520 * start REPLY_TX command process
2560 */ 2521 */
2561static int iwl3945_tx_skb(struct iwl3945_priv *priv, 2522static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
2562 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2563{ 2523{
2564 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2524 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2525 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2565 struct iwl3945_tfd_frame *tfd; 2526 struct iwl3945_tfd_frame *tfd;
2566 u32 *control_flags; 2527 u32 *control_flags;
2567 int txq_id = ctl->queue; 2528 int txq_id = skb_get_queue_mapping(skb);
2568 struct iwl3945_tx_queue *txq = NULL; 2529 struct iwl3945_tx_queue *txq = NULL;
2569 struct iwl3945_queue *q = NULL; 2530 struct iwl3945_queue *q = NULL;
2570 dma_addr_t phys_addr; 2531 dma_addr_t phys_addr;
2571 dma_addr_t txcmd_phys; 2532 dma_addr_t txcmd_phys;
2572 struct iwl3945_cmd *out_cmd = NULL; 2533 struct iwl3945_cmd *out_cmd = NULL;
2573 u16 len, idx, len_org; 2534 u16 len, idx, len_org, hdr_len;
2574 u8 id, hdr_len, unicast; 2535 u8 id;
2536 u8 unicast;
2575 u8 sta_id; 2537 u8 sta_id;
2538 u8 tid = 0;
2576 u16 seq_number = 0; 2539 u16 seq_number = 0;
2577 u16 fc; 2540 __le16 fc;
2578 __le16 *qc;
2579 u8 wait_write_ptr = 0; 2541 u8 wait_write_ptr = 0;
2542 u8 *qc = NULL;
2580 unsigned long flags; 2543 unsigned long flags;
2581 int rc; 2544 int rc;
2582 2545
@@ -2586,12 +2549,7 @@ static int iwl3945_tx_skb(struct iwl3945_priv *priv,
2586 goto drop_unlock; 2549 goto drop_unlock;
2587 } 2550 }
2588 2551
2589 if (!priv->vif) { 2552 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
2590 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
2591 goto drop_unlock;
2592 }
2593
2594 if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
2595 IWL_ERROR("ERROR: No TX rate available.\n"); 2553 IWL_ERROR("ERROR: No TX rate available.\n");
2596 goto drop_unlock; 2554 goto drop_unlock;
2597 } 2555 }
@@ -2599,28 +2557,29 @@ static int iwl3945_tx_skb(struct iwl3945_priv *priv,
2599 unicast = !is_multicast_ether_addr(hdr->addr1); 2557 unicast = !is_multicast_ether_addr(hdr->addr1);
2600 id = 0; 2558 id = 0;
2601 2559
2602 fc = le16_to_cpu(hdr->frame_control); 2560 fc = hdr->frame_control;
2603 2561
2604#ifdef CONFIG_IWL3945_DEBUG 2562#ifdef CONFIG_IWL3945_DEBUG
2605 if (ieee80211_is_auth(fc)) 2563 if (ieee80211_is_auth(fc))
2606 IWL_DEBUG_TX("Sending AUTH frame\n"); 2564 IWL_DEBUG_TX("Sending AUTH frame\n");
2607 else if (ieee80211_is_assoc_request(fc)) 2565 else if (ieee80211_is_assoc_req(fc))
2608 IWL_DEBUG_TX("Sending ASSOC frame\n"); 2566 IWL_DEBUG_TX("Sending ASSOC frame\n");
2609 else if (ieee80211_is_reassoc_request(fc)) 2567 else if (ieee80211_is_reassoc_req(fc))
2610 IWL_DEBUG_TX("Sending REASSOC frame\n"); 2568 IWL_DEBUG_TX("Sending REASSOC frame\n");
2611#endif 2569#endif
2612 2570
2613 /* drop all data frame if we are not associated */ 2571 /* drop all data frame if we are not associated */
2614 if ((!iwl3945_is_associated(priv) || 2572 if (ieee80211_is_data(fc) &&
2615 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) && 2573 (priv->iw_mode != IEEE80211_IF_TYPE_MNTR) && /* packet injection */
2616 ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) { 2574 (!iwl3945_is_associated(priv) ||
2575 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id))) {
2617 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n"); 2576 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
2618 goto drop_unlock; 2577 goto drop_unlock;
2619 } 2578 }
2620 2579
2621 spin_unlock_irqrestore(&priv->lock, flags); 2580 spin_unlock_irqrestore(&priv->lock, flags);
2622 2581
2623 hdr_len = ieee80211_get_hdrlen(fc); 2582 hdr_len = ieee80211_get_hdrlen(le16_to_cpu(fc));
2624 2583
2625 /* Find (or create) index into station table for destination station */ 2584 /* Find (or create) index into station table for destination station */
2626 sta_id = iwl3945_get_sta_id(priv, hdr); 2585 sta_id = iwl3945_get_sta_id(priv, hdr);
@@ -2634,9 +2593,9 @@ static int iwl3945_tx_skb(struct iwl3945_priv *priv,
2634 2593
2635 IWL_DEBUG_RATE("station Id %d\n", sta_id); 2594 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2636 2595
2637 qc = ieee80211_get_qos_ctrl(hdr); 2596 if (ieee80211_is_data_qos(fc)) {
2638 if (qc) { 2597 qc = ieee80211_get_qos_ctl(hdr);
2639 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf); 2598 tid = qc[0] & 0xf;
2640 seq_number = priv->stations[sta_id].tid[tid].seq_number & 2599 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2641 IEEE80211_SCTL_SEQ; 2600 IEEE80211_SCTL_SEQ;
2642 hdr->seq_ctrl = cpu_to_le16(seq_number) | 2601 hdr->seq_ctrl = cpu_to_le16(seq_number) |
@@ -2660,8 +2619,6 @@ static int iwl3945_tx_skb(struct iwl3945_priv *priv,
2660 /* Set up driver data for this TFD */ 2619 /* Set up driver data for this TFD */
2661 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info)); 2620 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
2662 txq->txb[q->write_ptr].skb[0] = skb; 2621 txq->txb[q->write_ptr].skb[0] = skb;
2663 memcpy(&(txq->txb[q->write_ptr].status.control),
2664 ctl, sizeof(struct ieee80211_tx_control));
2665 2622
2666 /* Init first empty entry in queue's array of Tx/cmd buffers */ 2623 /* Init first empty entry in queue's array of Tx/cmd buffers */
2667 out_cmd = &txq->cmd[idx]; 2624 out_cmd = &txq->cmd[idx];
@@ -2710,8 +2667,8 @@ static int iwl3945_tx_skb(struct iwl3945_priv *priv,
2710 * first entry */ 2667 * first entry */
2711 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); 2668 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
2712 2669
2713 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) 2670 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT))
2714 iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0); 2671 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
2715 2672
2716 /* Set up TFD's 2nd entry to point directly to remainder of skb, 2673 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2717 * if any (802.11 null frames have no payload). */ 2674 * if any (802.11 null frames have no payload). */
@@ -2736,18 +2693,17 @@ static int iwl3945_tx_skb(struct iwl3945_priv *priv,
2736 out_cmd->cmd.tx.len = cpu_to_le16(len); 2693 out_cmd->cmd.tx.len = cpu_to_le16(len);
2737 2694
2738 /* TODO need this for burst mode later on */ 2695 /* TODO need this for burst mode later on */
2739 iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id); 2696 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
2740 2697
2741 /* set is_hcca to 0; it probably will never be implemented */ 2698 /* set is_hcca to 0; it probably will never be implemented */
2742 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0); 2699 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
2743 2700
2744 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; 2701 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2745 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; 2702 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2746 2703
2747 if (!ieee80211_get_morefrag(hdr)) { 2704 if (!ieee80211_has_morefrags(hdr->frame_control)) {
2748 txq->need_update = 1; 2705 txq->need_update = 1;
2749 if (qc) { 2706 if (qc) {
2750 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2751 priv->stations[sta_id].tid[tid].seq_number = seq_number; 2707 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2752 } 2708 }
2753 } else { 2709 } else {
@@ -2759,7 +2715,7 @@ static int iwl3945_tx_skb(struct iwl3945_priv *priv,
2759 sizeof(out_cmd->cmd.tx)); 2715 sizeof(out_cmd->cmd.tx));
2760 2716
2761 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr, 2717 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
2762 ieee80211_get_hdrlen(fc)); 2718 ieee80211_get_hdrlen(le16_to_cpu(fc)));
2763 2719
2764 /* Tell device the write index *just past* this latest filled TFD */ 2720 /* Tell device the write index *just past* this latest filled TFD */
2765 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); 2721 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
@@ -2778,7 +2734,7 @@ static int iwl3945_tx_skb(struct iwl3945_priv *priv,
2778 spin_unlock_irqrestore(&priv->lock, flags); 2734 spin_unlock_irqrestore(&priv->lock, flags);
2779 } 2735 }
2780 2736
2781 ieee80211_stop_queue(priv->hw, ctl->queue); 2737 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
2782 } 2738 }
2783 2739
2784 return 0; 2740 return 0;
@@ -2888,7 +2844,8 @@ static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
2888 return; 2844 return;
2889 } 2845 }
2890 2846
2891 queue_work(priv->workqueue, &priv->restart); 2847 if (priv->is_open)
2848 queue_work(priv->workqueue, &priv->restart);
2892 return; 2849 return;
2893} 2850}
2894 2851
@@ -2924,72 +2881,6 @@ void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
2924 } 2881 }
2925} 2882}
2926 2883
2927#define IWL_PACKET_RETRY_TIME HZ
2928
2929int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
2930{
2931 u16 sc = le16_to_cpu(header->seq_ctrl);
2932 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
2933 u16 frag = sc & IEEE80211_SCTL_FRAG;
2934 u16 *last_seq, *last_frag;
2935 unsigned long *last_time;
2936
2937 switch (priv->iw_mode) {
2938 case IEEE80211_IF_TYPE_IBSS:{
2939 struct list_head *p;
2940 struct iwl3945_ibss_seq *entry = NULL;
2941 u8 *mac = header->addr2;
2942 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
2943
2944 __list_for_each(p, &priv->ibss_mac_hash[index]) {
2945 entry = list_entry(p, struct iwl3945_ibss_seq, list);
2946 if (!compare_ether_addr(entry->mac, mac))
2947 break;
2948 }
2949 if (p == &priv->ibss_mac_hash[index]) {
2950 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2951 if (!entry) {
2952 IWL_ERROR("Cannot malloc new mac entry\n");
2953 return 0;
2954 }
2955 memcpy(entry->mac, mac, ETH_ALEN);
2956 entry->seq_num = seq;
2957 entry->frag_num = frag;
2958 entry->packet_time = jiffies;
2959 list_add(&entry->list, &priv->ibss_mac_hash[index]);
2960 return 0;
2961 }
2962 last_seq = &entry->seq_num;
2963 last_frag = &entry->frag_num;
2964 last_time = &entry->packet_time;
2965 break;
2966 }
2967 case IEEE80211_IF_TYPE_STA:
2968 last_seq = &priv->last_seq_num;
2969 last_frag = &priv->last_frag_num;
2970 last_time = &priv->last_packet_time;
2971 break;
2972 default:
2973 return 0;
2974 }
2975 if ((*last_seq == seq) &&
2976 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
2977 if (*last_frag == frag)
2978 goto drop;
2979 if (*last_frag + 1 != frag)
2980 /* out-of-order fragment */
2981 goto drop;
2982 } else
2983 *last_seq = seq;
2984
2985 *last_frag = frag;
2986 *last_time = jiffies;
2987 return 0;
2988
2989 drop:
2990 return 1;
2991}
2992
2993#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT 2884#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
2994 2885
2995#include "iwl-spectrum.h" 2886#include "iwl-spectrum.h"
@@ -3241,7 +3132,7 @@ static void iwl3945_bg_beacon_update(struct work_struct *work)
3241 struct sk_buff *beacon; 3132 struct sk_buff *beacon;
3242 3133
3243 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ 3134 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
3244 beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL); 3135 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
3245 3136
3246 if (!beacon) { 3137 if (!beacon) {
3247 IWL_ERROR("update beacon failed\n"); 3138 IWL_ERROR("update beacon failed\n");
@@ -4848,7 +4739,7 @@ static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
4848 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg; 4739 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4849 ch_info->min_power = 0; 4740 ch_info->min_power = 0;
4850 4741
4851 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x" 4742 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
4852 " %ddBm): Ad-Hoc %ssupported\n", 4743 " %ddBm): Ad-Hoc %ssupported\n",
4853 ch_info->channel, 4744 ch_info->channel,
4854 is_channel_a_band(ch_info) ? 4745 is_channel_a_band(ch_info) ?
@@ -4858,7 +4749,6 @@ static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
4858 CHECK_AND_PRINT(ACTIVE), 4749 CHECK_AND_PRINT(ACTIVE),
4859 CHECK_AND_PRINT(RADAR), 4750 CHECK_AND_PRINT(RADAR),
4860 CHECK_AND_PRINT(WIDE), 4751 CHECK_AND_PRINT(WIDE),
4861 CHECK_AND_PRINT(NARROW),
4862 CHECK_AND_PRINT(DFS), 4752 CHECK_AND_PRINT(DFS),
4863 eeprom_ch_info[ch].flags, 4753 eeprom_ch_info[ch].flags,
4864 eeprom_ch_info[ch].max_power_avg, 4754 eeprom_ch_info[ch].max_power_avg,
@@ -4994,9 +4884,6 @@ static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4994 if (scan_ch->type & 1) 4884 if (scan_ch->type & 1)
4995 scan_ch->type |= (direct_mask << 1); 4885 scan_ch->type |= (direct_mask << 1);
4996 4886
4997 if (is_channel_narrow(ch_info))
4998 scan_ch->type |= (1 << 7);
4999
5000 scan_ch->active_dwell = cpu_to_le16(active_dwell); 4887 scan_ch->active_dwell = cpu_to_le16(active_dwell);
5001 scan_ch->passive_dwell = cpu_to_le16(passive_dwell); 4888 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
5002 4889
@@ -5843,7 +5730,7 @@ static void iwl3945_alive_start(struct iwl3945_priv *priv)
5843 if (iwl3945_is_rfkill(priv)) 5730 if (iwl3945_is_rfkill(priv))
5844 return; 5731 return;
5845 5732
5846 ieee80211_start_queues(priv->hw); 5733 ieee80211_wake_queues(priv->hw);
5847 5734
5848 priv->active_rate = priv->rates_mask; 5735 priv->active_rate = priv->rates_mask;
5849 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; 5736 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
@@ -5869,9 +5756,6 @@ static void iwl3945_alive_start(struct iwl3945_priv *priv)
5869 /* Configure the adapter for unassociated operation */ 5756 /* Configure the adapter for unassociated operation */
5870 iwl3945_commit_rxon(priv); 5757 iwl3945_commit_rxon(priv);
5871 5758
5872 /* At this point, the NIC is initialized and operational */
5873 priv->notif_missed_beacons = 0;
5874
5875 iwl3945_reg_txpower_periodic(priv); 5759 iwl3945_reg_txpower_periodic(priv);
5876 5760
5877 iwl3945_led_register(priv); 5761 iwl3945_led_register(priv);
@@ -5938,7 +5822,9 @@ static void __iwl3945_down(struct iwl3945_priv *priv)
5938 test_bit(STATUS_GEO_CONFIGURED, &priv->status) << 5822 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5939 STATUS_GEO_CONFIGURED | 5823 STATUS_GEO_CONFIGURED |
5940 test_bit(STATUS_IN_SUSPEND, &priv->status) << 5824 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5941 STATUS_IN_SUSPEND; 5825 STATUS_IN_SUSPEND |
5826 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5827 STATUS_EXIT_PENDING;
5942 goto exit; 5828 goto exit;
5943 } 5829 }
5944 5830
@@ -5953,7 +5839,9 @@ static void __iwl3945_down(struct iwl3945_priv *priv)
5953 test_bit(STATUS_IN_SUSPEND, &priv->status) << 5839 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5954 STATUS_IN_SUSPEND | 5840 STATUS_IN_SUSPEND |
5955 test_bit(STATUS_FW_ERROR, &priv->status) << 5841 test_bit(STATUS_FW_ERROR, &priv->status) <<
5956 STATUS_FW_ERROR; 5842 STATUS_FW_ERROR |
5843 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5844 STATUS_EXIT_PENDING;
5957 5845
5958 spin_lock_irqsave(&priv->lock, flags); 5846 spin_lock_irqsave(&priv->lock, flags);
5959 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 5847 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
@@ -6085,6 +5973,7 @@ static int __iwl3945_up(struct iwl3945_priv *priv)
6085 5973
6086 set_bit(STATUS_EXIT_PENDING, &priv->status); 5974 set_bit(STATUS_EXIT_PENDING, &priv->status);
6087 __iwl3945_down(priv); 5975 __iwl3945_down(priv);
5976 clear_bit(STATUS_EXIT_PENDING, &priv->status);
6088 5977
6089 /* tried to restart and config the device for as long as our 5978 /* tried to restart and config the device for as long as our
6090 * patience could withstand */ 5979 * patience could withstand */
@@ -6152,6 +6041,26 @@ static void iwl3945_bg_rf_kill(struct work_struct *work)
6152 "Kill switch must be turned off for " 6041 "Kill switch must be turned off for "
6153 "wireless networking to work.\n"); 6042 "wireless networking to work.\n");
6154 } 6043 }
6044
6045 mutex_unlock(&priv->mutex);
6046 iwl3945_rfkill_set_hw_state(priv);
6047}
6048
6049static void iwl3945_bg_set_monitor(struct work_struct *work)
6050{
6051 struct iwl3945_priv *priv = container_of(work,
6052 struct iwl3945_priv, set_monitor);
6053
6054 IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
6055
6056 mutex_lock(&priv->mutex);
6057
6058 if (!iwl3945_is_ready(priv))
6059 IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
6060 else
6061 if (iwl3945_set_mode(priv, IEEE80211_IF_TYPE_MNTR) != 0)
6062 IWL_ERROR("iwl3945_set_mode() failed\n");
6063
6155 mutex_unlock(&priv->mutex); 6064 mutex_unlock(&priv->mutex);
6156} 6065}
6157 6066
@@ -6388,6 +6297,7 @@ static void iwl3945_bg_up(struct work_struct *data)
6388 mutex_lock(&priv->mutex); 6297 mutex_lock(&priv->mutex);
6389 __iwl3945_up(priv); 6298 __iwl3945_up(priv);
6390 mutex_unlock(&priv->mutex); 6299 mutex_unlock(&priv->mutex);
6300 iwl3945_rfkill_set_hw_state(priv);
6391} 6301}
6392 6302
6393static void iwl3945_bg_restart(struct work_struct *data) 6303static void iwl3945_bg_restart(struct work_struct *data)
@@ -6511,8 +6421,6 @@ static void iwl3945_bg_post_associate(struct work_struct *data)
6511 break; 6421 break;
6512 } 6422 }
6513 6423
6514 iwl3945_sequence_reset(priv);
6515
6516 iwl3945_activate_qos(priv, 0); 6424 iwl3945_activate_qos(priv, 0);
6517 6425
6518 /* we have just associated, don't start scan too early */ 6426 /* we have just associated, don't start scan too early */
@@ -6608,6 +6516,8 @@ static int iwl3945_mac_start(struct ieee80211_hw *hw)
6608 6516
6609 mutex_unlock(&priv->mutex); 6517 mutex_unlock(&priv->mutex);
6610 6518
6519 iwl3945_rfkill_set_hw_state(priv);
6520
6611 if (ret) 6521 if (ret)
6612 goto out_release_irq; 6522 goto out_release_irq;
6613 6523
@@ -6678,8 +6588,7 @@ static void iwl3945_mac_stop(struct ieee80211_hw *hw)
6678 IWL_DEBUG_MAC80211("leave\n"); 6588 IWL_DEBUG_MAC80211("leave\n");
6679} 6589}
6680 6590
6681static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb, 6591static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
6682 struct ieee80211_tx_control *ctl)
6683{ 6592{
6684 struct iwl3945_priv *priv = hw->priv; 6593 struct iwl3945_priv *priv = hw->priv;
6685 6594
@@ -6692,9 +6601,9 @@ static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
6692 } 6601 }
6693 6602
6694 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, 6603 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
6695 ctl->tx_rate->bitrate); 6604 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
6696 6605
6697 if (iwl3945_tx_skb(priv, skb, ctl)) 6606 if (iwl3945_tx_skb(priv, skb))
6698 dev_kfree_skb_any(skb); 6607 dev_kfree_skb_any(skb);
6699 6608
6700 IWL_DEBUG_MAC80211("leave\n"); 6609 IWL_DEBUG_MAC80211("leave\n");
@@ -6837,7 +6746,7 @@ static void iwl3945_config_ap(struct iwl3945_priv *priv)
6837 return; 6746 return;
6838 6747
6839 /* The following should be done only at AP bring up */ 6748 /* The following should be done only at AP bring up */
6840 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) { 6749 if (!(iwl3945_is_associated(priv))) {
6841 6750
6842 /* RXON - unassoc (to set timing command) */ 6751 /* RXON - unassoc (to set timing command) */
6843 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; 6752 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
@@ -6886,6 +6795,9 @@ static void iwl3945_config_ap(struct iwl3945_priv *priv)
6886 * clear sta table, add BCAST sta... */ 6795 * clear sta table, add BCAST sta... */
6887} 6796}
6888 6797
6798/* temporary */
6799static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb);
6800
6889static int iwl3945_mac_config_interface(struct ieee80211_hw *hw, 6801static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6890 struct ieee80211_vif *vif, 6802 struct ieee80211_vif *vif,
6891 struct ieee80211_if_conf *conf) 6803 struct ieee80211_if_conf *conf)
@@ -6903,10 +6815,21 @@ static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6903 return 0; 6815 return 0;
6904 } 6816 }
6905 6817
6818 /* handle this temporarily here */
6819 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
6820 conf->changed & IEEE80211_IFCC_BEACON) {
6821 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
6822 if (!beacon)
6823 return -ENOMEM;
6824 rc = iwl3945_mac_beacon_update(hw, beacon);
6825 if (rc)
6826 return rc;
6827 }
6828
6906 /* XXX: this MUST use conf->mac_addr */ 6829 /* XXX: this MUST use conf->mac_addr */
6907 6830
6908 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && 6831 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
6909 (!conf->beacon || !conf->ssid_len)) { 6832 (!conf->ssid_len)) {
6910 IWL_DEBUG_MAC80211 6833 IWL_DEBUG_MAC80211
6911 ("Leaving in AP mode because HostAPD is not ready.\n"); 6834 ("Leaving in AP mode because HostAPD is not ready.\n");
6912 return 0; 6835 return 0;
@@ -6938,7 +6861,7 @@ static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6938 if (priv->ibss_beacon) 6861 if (priv->ibss_beacon)
6939 dev_kfree_skb(priv->ibss_beacon); 6862 dev_kfree_skb(priv->ibss_beacon);
6940 6863
6941 priv->ibss_beacon = conf->beacon; 6864 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
6942 } 6865 }
6943 6866
6944 if (iwl3945_is_rfkill(priv)) 6867 if (iwl3945_is_rfkill(priv))
@@ -6999,11 +6922,18 @@ static void iwl3945_configure_filter(struct ieee80211_hw *hw,
6999 unsigned int *total_flags, 6922 unsigned int *total_flags,
7000 int mc_count, struct dev_addr_list *mc_list) 6923 int mc_count, struct dev_addr_list *mc_list)
7001{ 6924{
7002 /* 6925 struct iwl3945_priv *priv = hw->priv;
7003 * XXX: dummy 6926
7004 * see also iwl3945_connection_init_rx_config 6927 if (changed_flags & (*total_flags) & FIF_OTHER_BSS) {
7005 */ 6928 IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
7006 *total_flags = 0; 6929 IEEE80211_IF_TYPE_MNTR,
6930 changed_flags, *total_flags);
6931 /* queue work 'cuz mac80211 is holding a lock which
6932 * prevents us from issuing (synchronous) f/w cmds */
6933 queue_work(priv->workqueue, &priv->set_monitor);
6934 }
6935 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI |
6936 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
7007} 6937}
7008 6938
7009static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw, 6939static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
@@ -7061,9 +6991,10 @@ static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
7061 rc = -EAGAIN; 6991 rc = -EAGAIN;
7062 goto out_unlock; 6992 goto out_unlock;
7063 } 6993 }
7064 /* if we just finished scan ask for delay */ 6994 /* if we just finished scan ask for delay for a broadcast scan */
7065 if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies + 6995 if ((len == 0) && priv->last_scan_jiffies &&
7066 IWL_DELAY_NEXT_SCAN, jiffies)) { 6996 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
6997 jiffies)) {
7067 rc = -EAGAIN; 6998 rc = -EAGAIN;
7068 goto out_unlock; 6999 goto out_unlock;
7069 } 7000 }
@@ -7150,7 +7081,7 @@ static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7150 return rc; 7081 return rc;
7151} 7082}
7152 7083
7153static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue, 7084static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
7154 const struct ieee80211_tx_queue_params *params) 7085 const struct ieee80211_tx_queue_params *params)
7155{ 7086{
7156 struct iwl3945_priv *priv = hw->priv; 7087 struct iwl3945_priv *priv = hw->priv;
@@ -7224,9 +7155,9 @@ static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
7224 q = &txq->q; 7155 q = &txq->q;
7225 avail = iwl3945_queue_space(q); 7156 avail = iwl3945_queue_space(q);
7226 7157
7227 stats->data[i].len = q->n_window - avail; 7158 stats[i].len = q->n_window - avail;
7228 stats->data[i].limit = q->n_window - q->high_mark; 7159 stats[i].limit = q->n_window - q->high_mark;
7229 stats->data[i].count = q->n_window; 7160 stats[i].count = q->n_window;
7230 7161
7231 } 7162 }
7232 spin_unlock_irqrestore(&priv->lock, flags); 7163 spin_unlock_irqrestore(&priv->lock, flags);
@@ -7315,8 +7246,7 @@ static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
7315 7246
7316} 7247}
7317 7248
7318static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, 7249static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
7319 struct ieee80211_tx_control *control)
7320{ 7250{
7321 struct iwl3945_priv *priv = hw->priv; 7251 struct iwl3945_priv *priv = hw->priv;
7322 unsigned long flags; 7252 unsigned long flags;
@@ -7398,37 +7328,6 @@ static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7398 7328
7399#endif /* CONFIG_IWL3945_DEBUG */ 7329#endif /* CONFIG_IWL3945_DEBUG */
7400 7330
7401static ssize_t show_rf_kill(struct device *d,
7402 struct device_attribute *attr, char *buf)
7403{
7404 /*
7405 * 0 - RF kill not enabled
7406 * 1 - SW based RF kill active (sysfs)
7407 * 2 - HW based RF kill active
7408 * 3 - Both HW and SW based RF kill active
7409 */
7410 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7411 int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
7412 (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
7413
7414 return sprintf(buf, "%i\n", val);
7415}
7416
7417static ssize_t store_rf_kill(struct device *d,
7418 struct device_attribute *attr,
7419 const char *buf, size_t count)
7420{
7421 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7422
7423 mutex_lock(&priv->mutex);
7424 iwl3945_radio_kill_sw(priv, buf[0] == '1');
7425 mutex_unlock(&priv->mutex);
7426
7427 return count;
7428}
7429
7430static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
7431
7432static ssize_t show_temperature(struct device *d, 7331static ssize_t show_temperature(struct device *d,
7433 struct device_attribute *attr, char *buf) 7332 struct device_attribute *attr, char *buf)
7434{ 7333{
@@ -7879,6 +7778,7 @@ static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
7879 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan); 7778 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7880 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill); 7779 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7881 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); 7780 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
7781 INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
7882 INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate); 7782 INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
7883 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); 7783 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7884 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); 7784 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
@@ -7913,7 +7813,6 @@ static struct attribute *iwl3945_sysfs_entries[] = {
7913#endif 7813#endif
7914 &dev_attr_power_level.attr, 7814 &dev_attr_power_level.attr,
7915 &dev_attr_retry_rate.attr, 7815 &dev_attr_retry_rate.attr,
7916 &dev_attr_rf_kill.attr,
7917 &dev_attr_rs_window.attr, 7816 &dev_attr_rs_window.attr,
7918 &dev_attr_statistics.attr, 7817 &dev_attr_statistics.attr,
7919 &dev_attr_status.attr, 7818 &dev_attr_status.attr,
@@ -7943,7 +7842,6 @@ static struct ieee80211_ops iwl3945_hw_ops = {
7943 .conf_tx = iwl3945_mac_conf_tx, 7842 .conf_tx = iwl3945_mac_conf_tx,
7944 .get_tsf = iwl3945_mac_get_tsf, 7843 .get_tsf = iwl3945_mac_get_tsf,
7945 .reset_tsf = iwl3945_mac_reset_tsf, 7844 .reset_tsf = iwl3945_mac_reset_tsf,
7946 .beacon_update = iwl3945_mac_beacon_update,
7947 .hw_scan = iwl3945_mac_hw_scan 7845 .hw_scan = iwl3945_mac_hw_scan
7948}; 7846};
7949 7847
@@ -7953,7 +7851,6 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
7953 struct iwl3945_priv *priv; 7851 struct iwl3945_priv *priv;
7954 struct ieee80211_hw *hw; 7852 struct ieee80211_hw *hw;
7955 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data); 7853 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
7956 int i;
7957 unsigned long flags; 7854 unsigned long flags;
7958 DECLARE_MAC_BUF(mac); 7855 DECLARE_MAC_BUF(mac);
7959 7856
@@ -8001,17 +7898,10 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
8001 7898
8002 priv->ibss_beacon = NULL; 7899 priv->ibss_beacon = NULL;
8003 7900
8004 /* Tell mac80211 and its clients (e.g. Wireless Extensions) 7901 /* Tell mac80211 our characteristics */
8005 * the range of signal quality values that we'll provide. 7902 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
8006 * Negative values for level/noise indicate that we'll provide dBm. 7903 IEEE80211_HW_SIGNAL_DBM |
8007 * For WE, at least, non-0 values here *enable* display of values 7904 IEEE80211_HW_NOISE_DBM;
8008 * in app (iwconfig). */
8009 hw->max_rssi = -20; /* signal level, negative indicates dBm */
8010 hw->max_noise = -20; /* noise level, negative indicates dBm */
8011 hw->max_signal = 100; /* link quality indication (%) */
8012
8013 /* Tell mac80211 our Tx characteristics */
8014 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
8015 7905
8016 /* 4 EDCA QOS priorities */ 7906 /* 4 EDCA QOS priorities */
8017 hw->queues = 4; 7907 hw->queues = 4;
@@ -8021,9 +7911,6 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
8021 spin_lock_init(&priv->sta_lock); 7911 spin_lock_init(&priv->sta_lock);
8022 spin_lock_init(&priv->hcmd_lock); 7912 spin_lock_init(&priv->hcmd_lock);
8023 7913
8024 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
8025 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
8026
8027 INIT_LIST_HEAD(&priv->free_frames); 7914 INIT_LIST_HEAD(&priv->free_frames);
8028 7915
8029 mutex_init(&priv->mutex); 7916 mutex_init(&priv->mutex);
@@ -8161,6 +8048,11 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
8161 pci_save_state(pdev); 8048 pci_save_state(pdev);
8162 pci_disable_device(pdev); 8049 pci_disable_device(pdev);
8163 8050
8051 err = iwl3945_rfkill_init(priv);
8052 if (err)
8053 IWL_ERROR("Unable to initialize RFKILL system. "
8054 "Ignoring error: %d\n", err);
8055
8164 return 0; 8056 return 0;
8165 8057
8166 out_free_geos: 8058 out_free_geos:
@@ -8191,8 +8083,6 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
8191static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) 8083static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
8192{ 8084{
8193 struct iwl3945_priv *priv = pci_get_drvdata(pdev); 8085 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
8194 struct list_head *p, *q;
8195 int i;
8196 unsigned long flags; 8086 unsigned long flags;
8197 8087
8198 if (!priv) 8088 if (!priv)
@@ -8213,16 +8103,9 @@ static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
8213 8103
8214 iwl_synchronize_irq(priv); 8104 iwl_synchronize_irq(priv);
8215 8105
8216 /* Free MAC hash list for ADHOC */
8217 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8218 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8219 list_del(p);
8220 kfree(list_entry(p, struct iwl3945_ibss_seq, list));
8221 }
8222 }
8223
8224 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); 8106 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
8225 8107
8108 iwl3945_rfkill_unregister(priv);
8226 iwl3945_dealloc_ucode_pci(priv); 8109 iwl3945_dealloc_ucode_pci(priv);
8227 8110
8228 if (priv->rxq.bd) 8111 if (priv->rxq.bd)
@@ -8252,7 +8135,7 @@ static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
8252 8135
8253 iwl3945_free_channel_map(priv); 8136 iwl3945_free_channel_map(priv);
8254 iwl3945_free_geos(priv); 8137 iwl3945_free_geos(priv);
8255 8138 kfree(priv->scan);
8256 if (priv->ibss_beacon) 8139 if (priv->ibss_beacon)
8257 dev_kfree_skb(priv->ibss_beacon); 8140 dev_kfree_skb(priv->ibss_beacon);
8258 8141
@@ -8291,6 +8174,114 @@ static int iwl3945_pci_resume(struct pci_dev *pdev)
8291 8174
8292#endif /* CONFIG_PM */ 8175#endif /* CONFIG_PM */
8293 8176
8177/*************** RFKILL FUNCTIONS **********/
8178#ifdef CONFIG_IWL3945_RFKILL
8179/* software rf-kill from user */
8180static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
8181{
8182 struct iwl3945_priv *priv = data;
8183 int err = 0;
8184
8185 if (!priv->rfkill)
8186 return 0;
8187
8188 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
8189 return 0;
8190
8191 IWL_DEBUG_RF_KILL("we recieved soft RFKILL set to state %d\n", state);
8192 mutex_lock(&priv->mutex);
8193
8194 switch (state) {
8195 case RFKILL_STATE_UNBLOCKED:
8196 if (iwl3945_is_rfkill_hw(priv)) {
8197 err = -EBUSY;
8198 goto out_unlock;
8199 }
8200 iwl3945_radio_kill_sw(priv, 0);
8201 break;
8202 case RFKILL_STATE_SOFT_BLOCKED:
8203 iwl3945_radio_kill_sw(priv, 1);
8204 break;
8205 default:
8206 IWL_WARNING("we recieved unexpected RFKILL state %d\n", state);
8207 break;
8208 }
8209out_unlock:
8210 mutex_unlock(&priv->mutex);
8211
8212 return err;
8213}
8214
8215int iwl3945_rfkill_init(struct iwl3945_priv *priv)
8216{
8217 struct device *device = wiphy_dev(priv->hw->wiphy);
8218 int ret = 0;
8219
8220 BUG_ON(device == NULL);
8221
8222 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
8223 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
8224 if (!priv->rfkill) {
8225 IWL_ERROR("Unable to allocate rfkill device.\n");
8226 ret = -ENOMEM;
8227 goto error;
8228 }
8229
8230 priv->rfkill->name = priv->cfg->name;
8231 priv->rfkill->data = priv;
8232 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
8233 priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
8234 priv->rfkill->user_claim_unsupported = 1;
8235
8236 priv->rfkill->dev.class->suspend = NULL;
8237 priv->rfkill->dev.class->resume = NULL;
8238
8239 ret = rfkill_register(priv->rfkill);
8240 if (ret) {
8241 IWL_ERROR("Unable to register rfkill: %d\n", ret);
8242 goto freed_rfkill;
8243 }
8244
8245 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8246 return ret;
8247
8248freed_rfkill:
8249 if (priv->rfkill != NULL)
8250 rfkill_free(priv->rfkill);
8251 priv->rfkill = NULL;
8252
8253error:
8254 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8255 return ret;
8256}
8257
8258void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
8259{
8260 if (priv->rfkill)
8261 rfkill_unregister(priv->rfkill);
8262
8263 priv->rfkill = NULL;
8264}
8265
8266/* set rf-kill to the right state. */
8267void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
8268{
8269
8270 if (!priv->rfkill)
8271 return;
8272
8273 if (iwl3945_is_rfkill_hw(priv)) {
8274 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
8275 return;
8276 }
8277
8278 if (!iwl3945_is_rfkill_sw(priv))
8279 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
8280 else
8281 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
8282}
8283#endif
8284
8294/***************************************************************************** 8285/*****************************************************************************
8295 * 8286 *
8296 * driver and module entry point 8287 * driver and module entry point
diff --git a/drivers/net/wireless/iwlwifi/iwl4965-base.c b/drivers/net/wireless/iwlwifi/iwl4965-base.c
index 0bd55bb19739..71f5da3fe5c4 100644
--- a/drivers/net/wireless/iwlwifi/iwl4965-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl4965-base.c
@@ -46,14 +46,13 @@
46#include <asm/div64.h> 46#include <asm/div64.h>
47 47
48#include "iwl-eeprom.h" 48#include "iwl-eeprom.h"
49#include "iwl-4965.h" 49#include "iwl-dev.h"
50#include "iwl-core.h" 50#include "iwl-core.h"
51#include "iwl-io.h" 51#include "iwl-io.h"
52#include "iwl-helpers.h" 52#include "iwl-helpers.h"
53#include "iwl-sta.h" 53#include "iwl-sta.h"
54#include "iwl-calib.h"
54 55
55static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv,
56 struct iwl4965_tx_queue *txq);
57 56
58/****************************************************************************** 57/******************************************************************************
59 * 58 *
@@ -88,292 +87,6 @@ MODULE_VERSION(DRV_VERSION);
88MODULE_AUTHOR(DRV_COPYRIGHT); 87MODULE_AUTHOR(DRV_COPYRIGHT);
89MODULE_LICENSE("GPL"); 88MODULE_LICENSE("GPL");
90 89
91__le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
92{
93 u16 fc = le16_to_cpu(hdr->frame_control);
94 int hdr_len = ieee80211_get_hdrlen(fc);
95
96 if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
97 return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
98 return NULL;
99}
100
101static const struct ieee80211_supported_band *iwl4965_get_hw_mode(
102 struct iwl_priv *priv, enum ieee80211_band band)
103{
104 return priv->hw->wiphy->bands[band];
105}
106
107static int iwl4965_is_empty_essid(const char *essid, int essid_len)
108{
109 /* Single white space is for Linksys APs */
110 if (essid_len == 1 && essid[0] == ' ')
111 return 1;
112
113 /* Otherwise, if the entire essid is 0, we assume it is hidden */
114 while (essid_len) {
115 essid_len--;
116 if (essid[essid_len] != '\0')
117 return 0;
118 }
119
120 return 1;
121}
122
123static const char *iwl4965_escape_essid(const char *essid, u8 essid_len)
124{
125 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
126 const char *s = essid;
127 char *d = escaped;
128
129 if (iwl4965_is_empty_essid(essid, essid_len)) {
130 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
131 return escaped;
132 }
133
134 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
135 while (essid_len--) {
136 if (*s == '\0') {
137 *d++ = '\\';
138 *d++ = '0';
139 s++;
140 } else
141 *d++ = *s++;
142 }
143 *d = '\0';
144 return escaped;
145}
146
147/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
148 * DMA services
149 *
150 * Theory of operation
151 *
152 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
153 * of buffer descriptors, each of which points to one or more data buffers for
154 * the device to read from or fill. Driver and device exchange status of each
155 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
156 * entries in each circular buffer, to protect against confusing empty and full
157 * queue states.
158 *
159 * The device reads or writes the data in the queues via the device's several
160 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
161 *
162 * For Tx queue, there are low mark and high mark limits. If, after queuing
163 * the packet for Tx, free space become < low mark, Tx queue stopped. When
164 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
165 * Tx queue resumed.
166 *
167 * The 4965 operates with up to 17 queues: One receive queue, one transmit
168 * queue (#4) for sending commands to the device firmware, and 15 other
169 * Tx queues that may be mapped to prioritized Tx DMA/FIFO channels.
170 *
171 * See more detailed info in iwl-4965-hw.h.
172 ***************************************************/
173
174int iwl4965_queue_space(const struct iwl4965_queue *q)
175{
176 int s = q->read_ptr - q->write_ptr;
177
178 if (q->read_ptr > q->write_ptr)
179 s -= q->n_bd;
180
181 if (s <= 0)
182 s += q->n_window;
183 /* keep some reserve to not confuse empty and full situations */
184 s -= 2;
185 if (s < 0)
186 s = 0;
187 return s;
188}
189
190
191static inline int x2_queue_used(const struct iwl4965_queue *q, int i)
192{
193 return q->write_ptr > q->read_ptr ?
194 (i >= q->read_ptr && i < q->write_ptr) :
195 !(i < q->read_ptr && i >= q->write_ptr);
196}
197
198static inline u8 get_cmd_index(struct iwl4965_queue *q, u32 index, int is_huge)
199{
200 /* This is for scan command, the big buffer at end of command array */
201 if (is_huge)
202 return q->n_window; /* must be power of 2 */
203
204 /* Otherwise, use normal size buffers */
205 return index & (q->n_window - 1);
206}
207
208/**
209 * iwl4965_queue_init - Initialize queue's high/low-water and read/write indexes
210 */
211static int iwl4965_queue_init(struct iwl_priv *priv, struct iwl4965_queue *q,
212 int count, int slots_num, u32 id)
213{
214 q->n_bd = count;
215 q->n_window = slots_num;
216 q->id = id;
217
218 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
219 * and iwl_queue_dec_wrap are broken. */
220 BUG_ON(!is_power_of_2(count));
221
222 /* slots_num must be power-of-two size, otherwise
223 * get_cmd_index is broken. */
224 BUG_ON(!is_power_of_2(slots_num));
225
226 q->low_mark = q->n_window / 4;
227 if (q->low_mark < 4)
228 q->low_mark = 4;
229
230 q->high_mark = q->n_window / 8;
231 if (q->high_mark < 2)
232 q->high_mark = 2;
233
234 q->write_ptr = q->read_ptr = 0;
235
236 return 0;
237}
238
239/**
240 * iwl4965_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
241 */
242static int iwl4965_tx_queue_alloc(struct iwl_priv *priv,
243 struct iwl4965_tx_queue *txq, u32 id)
244{
245 struct pci_dev *dev = priv->pci_dev;
246
247 /* Driver private data, only for Tx (not command) queues,
248 * not shared with device. */
249 if (id != IWL_CMD_QUEUE_NUM) {
250 txq->txb = kmalloc(sizeof(txq->txb[0]) *
251 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
252 if (!txq->txb) {
253 IWL_ERROR("kmalloc for auxiliary BD "
254 "structures failed\n");
255 goto error;
256 }
257 } else
258 txq->txb = NULL;
259
260 /* Circular buffer of transmit frame descriptors (TFDs),
261 * shared with device */
262 txq->bd = pci_alloc_consistent(dev,
263 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
264 &txq->q.dma_addr);
265
266 if (!txq->bd) {
267 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
268 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
269 goto error;
270 }
271 txq->q.id = id;
272
273 return 0;
274
275 error:
276 if (txq->txb) {
277 kfree(txq->txb);
278 txq->txb = NULL;
279 }
280
281 return -ENOMEM;
282}
283
284/**
285 * iwl4965_tx_queue_init - Allocate and initialize one tx/cmd queue
286 */
287int iwl4965_tx_queue_init(struct iwl_priv *priv,
288 struct iwl4965_tx_queue *txq, int slots_num, u32 txq_id)
289{
290 struct pci_dev *dev = priv->pci_dev;
291 int len;
292 int rc = 0;
293
294 /*
295 * Alloc buffer array for commands (Tx or other types of commands).
296 * For the command queue (#4), allocate command space + one big
297 * command for scan, since scan command is very huge; the system will
298 * not have two scans at the same time, so only one is needed.
299 * For normal Tx queues (all other queues), no super-size command
300 * space is needed.
301 */
302 len = sizeof(struct iwl_cmd) * slots_num;
303 if (txq_id == IWL_CMD_QUEUE_NUM)
304 len += IWL_MAX_SCAN_SIZE;
305 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
306 if (!txq->cmd)
307 return -ENOMEM;
308
309 /* Alloc driver data array and TFD circular buffer */
310 rc = iwl4965_tx_queue_alloc(priv, txq, txq_id);
311 if (rc) {
312 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
313
314 return -ENOMEM;
315 }
316 txq->need_update = 0;
317
318 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
319 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
320 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
321
322 /* Initialize queue's high/low-water marks, and head/tail indexes */
323 iwl4965_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
324
325 /* Tell device where to find queue */
326 iwl4965_hw_tx_queue_init(priv, txq);
327
328 return 0;
329}
330
331/**
332 * iwl4965_tx_queue_free - Deallocate DMA queue.
333 * @txq: Transmit queue to deallocate.
334 *
335 * Empty queue by removing and destroying all BD's.
336 * Free all buffers.
337 * 0-fill, but do not free "txq" descriptor structure.
338 */
339void iwl4965_tx_queue_free(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
340{
341 struct iwl4965_queue *q = &txq->q;
342 struct pci_dev *dev = priv->pci_dev;
343 int len;
344
345 if (q->n_bd == 0)
346 return;
347
348 /* first, empty all BD's */
349 for (; q->write_ptr != q->read_ptr;
350 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
351 iwl4965_hw_txq_free_tfd(priv, txq);
352
353 len = sizeof(struct iwl_cmd) * q->n_window;
354 if (q->id == IWL_CMD_QUEUE_NUM)
355 len += IWL_MAX_SCAN_SIZE;
356
357 /* De-alloc array of command/tx buffers */
358 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
359
360 /* De-alloc circular buffer of TFDs */
361 if (txq->q.n_bd)
362 pci_free_consistent(dev, sizeof(struct iwl4965_tfd_frame) *
363 txq->q.n_bd, txq->bd, txq->q.dma_addr);
364
365 /* De-alloc array of per-TFD driver data */
366 if (txq->txb) {
367 kfree(txq->txb);
368 txq->txb = NULL;
369 }
370
371 /* 0-fill queue descriptor structure */
372 memset(txq, 0, sizeof(*txq));
373}
374
375const u8 iwl4965_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
376
377/*************** STATION TABLE MANAGEMENT **** 90/*************** STATION TABLE MANAGEMENT ****
378 * mac80211 should be examined to determine if sta_info is duplicating 91 * mac80211 should be examined to determine if sta_info is duplicating
379 * the functionality provided here 92 * the functionality provided here
@@ -381,213 +94,11 @@ const u8 iwl4965_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
381 94
382/**************************************************************/ 95/**************************************************************/
383 96
384#if 0 /* temporary disable till we add real remove station */
385/**
386 * iwl4965_remove_station - Remove driver's knowledge of station.
387 *
388 * NOTE: This does not remove station from device's station table.
389 */
390static u8 iwl4965_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
391{
392 int index = IWL_INVALID_STATION;
393 int i;
394 unsigned long flags;
395
396 spin_lock_irqsave(&priv->sta_lock, flags);
397
398 if (is_ap)
399 index = IWL_AP_ID;
400 else if (is_broadcast_ether_addr(addr))
401 index = priv->hw_params.bcast_sta_id;
402 else
403 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
404 if (priv->stations[i].used &&
405 !compare_ether_addr(priv->stations[i].sta.sta.addr,
406 addr)) {
407 index = i;
408 break;
409 }
410
411 if (unlikely(index == IWL_INVALID_STATION))
412 goto out;
413
414 if (priv->stations[index].used) {
415 priv->stations[index].used = 0;
416 priv->num_stations--;
417 }
418
419 BUG_ON(priv->num_stations < 0);
420
421out:
422 spin_unlock_irqrestore(&priv->sta_lock, flags);
423 return 0;
424}
425#endif
426
427/**
428 * iwl4965_add_station_flags - Add station to tables in driver and device
429 */
430u8 iwl4965_add_station_flags(struct iwl_priv *priv, const u8 *addr,
431 int is_ap, u8 flags, void *ht_data)
432{
433 int i;
434 int index = IWL_INVALID_STATION;
435 struct iwl4965_station_entry *station;
436 unsigned long flags_spin;
437 DECLARE_MAC_BUF(mac);
438
439 spin_lock_irqsave(&priv->sta_lock, flags_spin);
440 if (is_ap)
441 index = IWL_AP_ID;
442 else if (is_broadcast_ether_addr(addr))
443 index = priv->hw_params.bcast_sta_id;
444 else
445 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
446 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
447 addr)) {
448 index = i;
449 break;
450 }
451
452 if (!priv->stations[i].used &&
453 index == IWL_INVALID_STATION)
454 index = i;
455 }
456
457
458 /* These two conditions have the same outcome, but keep them separate
459 since they have different meanings */
460 if (unlikely(index == IWL_INVALID_STATION)) {
461 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
462 return index;
463 }
464
465 if (priv->stations[index].used &&
466 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
467 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
468 return index;
469 }
470
471
472 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
473 station = &priv->stations[index];
474 station->used = 1;
475 priv->num_stations++;
476
477 /* Set up the REPLY_ADD_STA command to send to device */
478 memset(&station->sta, 0, sizeof(struct iwl4965_addsta_cmd));
479 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
480 station->sta.mode = 0;
481 station->sta.sta.sta_id = index;
482 station->sta.station_flags = 0;
483
484#ifdef CONFIG_IWL4965_HT
485 /* BCAST station and IBSS stations do not work in HT mode */
486 if (index != priv->hw_params.bcast_sta_id &&
487 priv->iw_mode != IEEE80211_IF_TYPE_IBSS)
488 iwl4965_set_ht_add_station(priv, index,
489 (struct ieee80211_ht_info *) ht_data);
490#endif /*CONFIG_IWL4965_HT*/
491
492 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
493
494 /* Add station to device's station table */
495 iwl4965_send_add_station(priv, &station->sta, flags);
496 return index;
497
498}
499
500
501
502/*************** HOST COMMAND QUEUE FUNCTIONS *****/
503
504/**
505 * iwl4965_enqueue_hcmd - enqueue a uCode command
506 * @priv: device private data point
507 * @cmd: a point to the ucode command structure
508 *
509 * The function returns < 0 values to indicate the operation is
510 * failed. On success, it turns the index (> 0) of command in the
511 * command queue.
512 */
513int iwl4965_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
514{
515 struct iwl4965_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
516 struct iwl4965_queue *q = &txq->q;
517 struct iwl4965_tfd_frame *tfd;
518 u32 *control_flags;
519 struct iwl_cmd *out_cmd;
520 u32 idx;
521 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
522 dma_addr_t phys_addr;
523 int ret;
524 unsigned long flags;
525
526 /* If any of the command structures end up being larger than
527 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
528 * we will need to increase the size of the TFD entries */
529 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
530 !(cmd->meta.flags & CMD_SIZE_HUGE));
531
532 if (iwl_is_rfkill(priv)) {
533 IWL_DEBUG_INFO("Not sending command - RF KILL");
534 return -EIO;
535 }
536
537 if (iwl4965_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
538 IWL_ERROR("No space for Tx\n");
539 return -ENOSPC;
540 }
541
542 spin_lock_irqsave(&priv->hcmd_lock, flags);
543
544 tfd = &txq->bd[q->write_ptr];
545 memset(tfd, 0, sizeof(*tfd));
546
547 control_flags = (u32 *) tfd;
548 97
549 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
550 out_cmd = &txq->cmd[idx];
551
552 out_cmd->hdr.cmd = cmd->id;
553 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
554 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
555
556 /* At this point, the out_cmd now has all of the incoming cmd
557 * information */
558
559 out_cmd->hdr.flags = 0;
560 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
561 INDEX_TO_SEQ(q->write_ptr));
562 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
563 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
564
565 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
566 offsetof(struct iwl_cmd, hdr);
567 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
568
569 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
570 "%d bytes at %d[%d]:%d\n",
571 get_cmd_string(out_cmd->hdr.cmd),
572 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
573 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
574
575 txq->need_update = 1;
576
577 /* Set up entry in queue's byte count circular buffer */
578 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
579
580 /* Increment and update queue's write index */
581 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
582 ret = iwl4965_tx_queue_update_write_ptr(priv, txq);
583
584 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
585 return ret ? ret : idx;
586}
587 98
588static void iwl4965_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt) 99static void iwl4965_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
589{ 100{
590 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon; 101 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
591 102
592 if (hw_decrypt) 103 if (hw_decrypt)
593 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; 104 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
@@ -597,45 +108,13 @@ static void iwl4965_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
597} 108}
598 109
599/** 110/**
600 * iwl4965_rxon_add_station - add station into station table.
601 *
602 * there is only one AP station with id= IWL_AP_ID
603 * NOTE: mutex must be held before calling this fnction
604 */
605static int iwl4965_rxon_add_station(struct iwl_priv *priv,
606 const u8 *addr, int is_ap)
607{
608 u8 sta_id;
609
610 /* Add station to device's station table */
611#ifdef CONFIG_IWL4965_HT
612 struct ieee80211_conf *conf = &priv->hw->conf;
613 struct ieee80211_ht_info *cur_ht_config = &conf->ht_conf;
614
615 if ((is_ap) &&
616 (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) &&
617 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
618 sta_id = iwl4965_add_station_flags(priv, addr, is_ap,
619 0, cur_ht_config);
620 else
621#endif /* CONFIG_IWL4965_HT */
622 sta_id = iwl4965_add_station_flags(priv, addr, is_ap,
623 0, NULL);
624
625 /* Set up default rate scaling table in device's station table */
626 iwl4965_add_station(priv, addr, is_ap);
627
628 return sta_id;
629}
630
631/**
632 * iwl4965_check_rxon_cmd - validate RXON structure is valid 111 * iwl4965_check_rxon_cmd - validate RXON structure is valid
633 * 112 *
634 * NOTE: This is really only useful during development and can eventually 113 * NOTE: This is really only useful during development and can eventually
635 * be #ifdef'd out once the driver is stable and folks aren't actively 114 * be #ifdef'd out once the driver is stable and folks aren't actively
636 * making changes 115 * making changes
637 */ 116 */
638static int iwl4965_check_rxon_cmd(struct iwl4965_rxon_cmd *rxon) 117static int iwl4965_check_rxon_cmd(struct iwl_rxon_cmd *rxon)
639{ 118{
640 int error = 0; 119 int error = 0;
641 int counter = 1; 120 int counter = 1;
@@ -713,7 +192,7 @@ static int iwl4965_full_rxon_required(struct iwl_priv *priv)
713{ 192{
714 193
715 /* These items are only settable from the full RXON command */ 194 /* These items are only settable from the full RXON command */
716 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) || 195 if (!(iwl_is_associated(priv)) ||
717 compare_ether_addr(priv->staging_rxon.bssid_addr, 196 compare_ether_addr(priv->staging_rxon.bssid_addr,
718 priv->active_rxon.bssid_addr) || 197 priv->active_rxon.bssid_addr) ||
719 compare_ether_addr(priv->staging_rxon.node_addr, 198 compare_ether_addr(priv->staging_rxon.node_addr,
@@ -760,18 +239,23 @@ static int iwl4965_full_rxon_required(struct iwl_priv *priv)
760static int iwl4965_commit_rxon(struct iwl_priv *priv) 239static int iwl4965_commit_rxon(struct iwl_priv *priv)
761{ 240{
762 /* cast away the const for active_rxon in this function */ 241 /* cast away the const for active_rxon in this function */
763 struct iwl4965_rxon_cmd *active_rxon = (void *)&priv->active_rxon; 242 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
764 DECLARE_MAC_BUF(mac); 243 DECLARE_MAC_BUF(mac);
765 int rc = 0; 244 int ret;
245 bool new_assoc =
246 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
766 247
767 if (!iwl_is_alive(priv)) 248 if (!iwl_is_alive(priv))
768 return -1; 249 return -EBUSY;
769 250
770 /* always get timestamp with Rx frame */ 251 /* always get timestamp with Rx frame */
771 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; 252 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
253 /* allow CTS-to-self if possible. this is relevant only for
254 * 5000, but will not damage 4965 */
255 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
772 256
773 rc = iwl4965_check_rxon_cmd(&priv->staging_rxon); 257 ret = iwl4965_check_rxon_cmd(&priv->staging_rxon);
774 if (rc) { 258 if (ret) {
775 IWL_ERROR("Invalid RXON configuration. Not committing.\n"); 259 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
776 return -EINVAL; 260 return -EINVAL;
777 } 261 }
@@ -780,49 +264,37 @@ static int iwl4965_commit_rxon(struct iwl_priv *priv)
780 * iwl4965_rxon_assoc_cmd which is used to reconfigure filter 264 * iwl4965_rxon_assoc_cmd which is used to reconfigure filter
781 * and other flags for the current radio configuration. */ 265 * and other flags for the current radio configuration. */
782 if (!iwl4965_full_rxon_required(priv)) { 266 if (!iwl4965_full_rxon_required(priv)) {
783 rc = iwl_send_rxon_assoc(priv); 267 ret = iwl_send_rxon_assoc(priv);
784 if (rc) { 268 if (ret) {
785 IWL_ERROR("Error setting RXON_ASSOC " 269 IWL_ERROR("Error setting RXON_ASSOC (%d)\n", ret);
786 "configuration (%d).\n", rc); 270 return ret;
787 return rc;
788 } 271 }
789 272
790 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); 273 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
791
792 return 0; 274 return 0;
793 } 275 }
794 276
795 /* station table will be cleared */ 277 /* station table will be cleared */
796 priv->assoc_station_added = 0; 278 priv->assoc_station_added = 0;
797 279
798#ifdef CONFIG_IWL4965_SENSITIVITY
799 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
800 if (!priv->error_recovering)
801 priv->start_calib = 0;
802
803 iwl4965_init_sensitivity(priv, CMD_ASYNC, 1);
804#endif /* CONFIG_IWL4965_SENSITIVITY */
805
806 /* If we are currently associated and the new config requires 280 /* If we are currently associated and the new config requires
807 * an RXON_ASSOC and the new config wants the associated mask enabled, 281 * an RXON_ASSOC and the new config wants the associated mask enabled,
808 * we must clear the associated from the active configuration 282 * we must clear the associated from the active configuration
809 * before we apply the new config */ 283 * before we apply the new config */
810 if (iwl_is_associated(priv) && 284 if (iwl_is_associated(priv) && new_assoc) {
811 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
812 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n"); 285 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
813 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; 286 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
814 287
815 rc = iwl_send_cmd_pdu(priv, REPLY_RXON, 288 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
816 sizeof(struct iwl4965_rxon_cmd), 289 sizeof(struct iwl_rxon_cmd),
817 &priv->active_rxon); 290 &priv->active_rxon);
818 291
819 /* If the mask clearing failed then we set 292 /* If the mask clearing failed then we set
820 * active_rxon back to what it was previously */ 293 * active_rxon back to what it was previously */
821 if (rc) { 294 if (ret) {
822 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; 295 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
823 IWL_ERROR("Error clearing ASSOC_MSK on current " 296 IWL_ERROR("Error clearing ASSOC_MSK (%d)\n", ret);
824 "configuration (%d).\n", rc); 297 return ret;
825 return rc;
826 } 298 }
827 } 299 }
828 300
@@ -830,65 +302,87 @@ static int iwl4965_commit_rxon(struct iwl_priv *priv)
830 "* with%s RXON_FILTER_ASSOC_MSK\n" 302 "* with%s RXON_FILTER_ASSOC_MSK\n"
831 "* channel = %d\n" 303 "* channel = %d\n"
832 "* bssid = %s\n", 304 "* bssid = %s\n",
833 ((priv->staging_rxon.filter_flags & 305 (new_assoc ? "" : "out"),
834 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
835 le16_to_cpu(priv->staging_rxon.channel), 306 le16_to_cpu(priv->staging_rxon.channel),
836 print_mac(mac, priv->staging_rxon.bssid_addr)); 307 print_mac(mac, priv->staging_rxon.bssid_addr));
837 308
838 iwl4965_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto); 309 iwl4965_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
839 /* Apply the new configuration */ 310
840 rc = iwl_send_cmd_pdu(priv, REPLY_RXON, 311 /* Apply the new configuration
841 sizeof(struct iwl4965_rxon_cmd), &priv->staging_rxon); 312 * RXON unassoc clears the station table in uCode, send it before
842 if (rc) { 313 * we add the bcast station. If assoc bit is set, we will send RXON
843 IWL_ERROR("Error setting new configuration (%d).\n", rc); 314 * after having added the bcast and bssid station.
844 return rc; 315 */
316 if (!new_assoc) {
317 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
318 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
319 if (ret) {
320 IWL_ERROR("Error setting new RXON (%d)\n", ret);
321 return ret;
322 }
323 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
845 } 324 }
846 325
847 iwlcore_clear_stations_table(priv); 326 iwl_clear_stations_table(priv);
848 327
849#ifdef CONFIG_IWL4965_SENSITIVITY
850 if (!priv->error_recovering) 328 if (!priv->error_recovering)
851 priv->start_calib = 0; 329 priv->start_calib = 0;
852 330
853 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
854 iwl4965_init_sensitivity(priv, CMD_ASYNC, 1);
855#endif /* CONFIG_IWL4965_SENSITIVITY */
856
857 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
858
859 /* If we issue a new RXON command which required a tune then we must
860 * send a new TXPOWER command or we won't be able to Tx any frames */
861 rc = iwl4965_hw_reg_send_txpower(priv);
862 if (rc) {
863 IWL_ERROR("Error setting Tx power (%d).\n", rc);
864 return rc;
865 }
866
867 /* Add the broadcast address so we can send broadcast frames */ 331 /* Add the broadcast address so we can send broadcast frames */
868 if (iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0) == 332 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
869 IWL_INVALID_STATION) { 333 IWL_INVALID_STATION) {
870 IWL_ERROR("Error adding BROADCAST address for transmit.\n"); 334 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
871 return -EIO; 335 return -EIO;
872 } 336 }
873 337
874 /* If we have set the ASSOC_MSK and we are in BSS mode then 338 /* If we have set the ASSOC_MSK and we are in BSS mode then
875 * add the IWL_AP_ID to the station rate table */ 339 * add the IWL_AP_ID to the station rate table */
876 if (iwl_is_associated(priv) && 340 if (new_assoc) {
877 (priv->iw_mode == IEEE80211_IF_TYPE_STA)) { 341 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
878 if (iwl4965_rxon_add_station(priv, priv->active_rxon.bssid_addr, 1) 342 ret = iwl_rxon_add_station(priv,
879 == IWL_INVALID_STATION) { 343 priv->active_rxon.bssid_addr, 1);
880 IWL_ERROR("Error adding AP address for transmit.\n"); 344 if (ret == IWL_INVALID_STATION) {
881 return -EIO; 345 IWL_ERROR("Error adding AP address for TX.\n");
346 return -EIO;
347 }
348 priv->assoc_station_added = 1;
349 if (priv->default_wep_key &&
350 iwl_send_static_wepkey_cmd(priv, 0))
351 IWL_ERROR("Could not send WEP static key.\n");
882 } 352 }
883 priv->assoc_station_added = 1; 353
884 if (priv->default_wep_key && 354 /* Apply the new configuration
885 iwl_send_static_wepkey_cmd(priv, 0)) 355 * RXON assoc doesn't clear the station table in uCode,
886 IWL_ERROR("Could not send WEP static key.\n"); 356 */
357 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
358 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
359 if (ret) {
360 IWL_ERROR("Error setting new RXON (%d)\n", ret);
361 return ret;
362 }
363 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
364 }
365
366 iwl_init_sensitivity(priv);
367
368 /* If we issue a new RXON command which required a tune then we must
369 * send a new TXPOWER command or we won't be able to Tx any frames */
370 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
371 if (ret) {
372 IWL_ERROR("Error sending TX power (%d)\n", ret);
373 return ret;
887 } 374 }
888 375
889 return 0; 376 return 0;
890} 377}
891 378
379void iwl4965_update_chain_flags(struct iwl_priv *priv)
380{
381
382 iwl_set_rxon_chain(priv);
383 iwl4965_commit_rxon(priv);
384}
385
892static int iwl4965_send_bt_config(struct iwl_priv *priv) 386static int iwl4965_send_bt_config(struct iwl_priv *priv)
893{ 387{
894 struct iwl4965_bt_cmd bt_cmd = { 388 struct iwl4965_bt_cmd bt_cmd = {
@@ -903,155 +397,7 @@ static int iwl4965_send_bt_config(struct iwl_priv *priv)
903 sizeof(struct iwl4965_bt_cmd), &bt_cmd); 397 sizeof(struct iwl4965_bt_cmd), &bt_cmd);
904} 398}
905 399
906static int iwl4965_send_scan_abort(struct iwl_priv *priv) 400static void iwl_clear_free_frames(struct iwl_priv *priv)
907{
908 int rc = 0;
909 struct iwl4965_rx_packet *res;
910 struct iwl_host_cmd cmd = {
911 .id = REPLY_SCAN_ABORT_CMD,
912 .meta.flags = CMD_WANT_SKB,
913 };
914
915 /* If there isn't a scan actively going on in the hardware
916 * then we are in between scan bands and not actually
917 * actively scanning, so don't send the abort command */
918 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
919 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
920 return 0;
921 }
922
923 rc = iwl_send_cmd_sync(priv, &cmd);
924 if (rc) {
925 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
926 return rc;
927 }
928
929 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
930 if (res->u.status != CAN_ABORT_STATUS) {
931 /* The scan abort will return 1 for success or
932 * 2 for "failure". A failure condition can be
933 * due to simply not being in an active scan which
934 * can occur if we send the scan abort before we
935 * the microcode has notified us that a scan is
936 * completed. */
937 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
938 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
939 clear_bit(STATUS_SCAN_HW, &priv->status);
940 }
941
942 dev_kfree_skb_any(cmd.meta.u.skb);
943
944 return rc;
945}
946
947static int iwl4965_card_state_sync_callback(struct iwl_priv *priv,
948 struct iwl_cmd *cmd,
949 struct sk_buff *skb)
950{
951 return 1;
952}
953
954/*
955 * CARD_STATE_CMD
956 *
957 * Use: Sets the device's internal card state to enable, disable, or halt
958 *
959 * When in the 'enable' state the card operates as normal.
960 * When in the 'disable' state, the card enters into a low power mode.
961 * When in the 'halt' state, the card is shut down and must be fully
962 * restarted to come back on.
963 */
964static int iwl4965_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
965{
966 struct iwl_host_cmd cmd = {
967 .id = REPLY_CARD_STATE_CMD,
968 .len = sizeof(u32),
969 .data = &flags,
970 .meta.flags = meta_flag,
971 };
972
973 if (meta_flag & CMD_ASYNC)
974 cmd.meta.u.callback = iwl4965_card_state_sync_callback;
975
976 return iwl_send_cmd(priv, &cmd);
977}
978
979static int iwl4965_add_sta_sync_callback(struct iwl_priv *priv,
980 struct iwl_cmd *cmd, struct sk_buff *skb)
981{
982 struct iwl4965_rx_packet *res = NULL;
983
984 if (!skb) {
985 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
986 return 1;
987 }
988
989 res = (struct iwl4965_rx_packet *)skb->data;
990 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
991 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
992 res->hdr.flags);
993 return 1;
994 }
995
996 switch (res->u.add_sta.status) {
997 case ADD_STA_SUCCESS_MSK:
998 break;
999 default:
1000 break;
1001 }
1002
1003 /* We didn't cache the SKB; let the caller free it */
1004 return 1;
1005}
1006
1007int iwl4965_send_add_station(struct iwl_priv *priv,
1008 struct iwl4965_addsta_cmd *sta, u8 flags)
1009{
1010 struct iwl4965_rx_packet *res = NULL;
1011 int rc = 0;
1012 struct iwl_host_cmd cmd = {
1013 .id = REPLY_ADD_STA,
1014 .len = sizeof(struct iwl4965_addsta_cmd),
1015 .meta.flags = flags,
1016 .data = sta,
1017 };
1018
1019 if (flags & CMD_ASYNC)
1020 cmd.meta.u.callback = iwl4965_add_sta_sync_callback;
1021 else
1022 cmd.meta.flags |= CMD_WANT_SKB;
1023
1024 rc = iwl_send_cmd(priv, &cmd);
1025
1026 if (rc || (flags & CMD_ASYNC))
1027 return rc;
1028
1029 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
1030 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1031 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1032 res->hdr.flags);
1033 rc = -EIO;
1034 }
1035
1036 if (rc == 0) {
1037 switch (res->u.add_sta.status) {
1038 case ADD_STA_SUCCESS_MSK:
1039 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1040 break;
1041 default:
1042 rc = -EIO;
1043 IWL_WARNING("REPLY_ADD_STA failed\n");
1044 break;
1045 }
1046 }
1047
1048 priv->alloc_rxb_skb--;
1049 dev_kfree_skb_any(cmd.meta.u.skb);
1050
1051 return rc;
1052}
1053
1054static void iwl4965_clear_free_frames(struct iwl_priv *priv)
1055{ 401{
1056 struct list_head *element; 402 struct list_head *element;
1057 403
@@ -1061,7 +407,7 @@ static void iwl4965_clear_free_frames(struct iwl_priv *priv)
1061 while (!list_empty(&priv->free_frames)) { 407 while (!list_empty(&priv->free_frames)) {
1062 element = priv->free_frames.next; 408 element = priv->free_frames.next;
1063 list_del(element); 409 list_del(element);
1064 kfree(list_entry(element, struct iwl4965_frame, list)); 410 kfree(list_entry(element, struct iwl_frame, list));
1065 priv->frames_count--; 411 priv->frames_count--;
1066 } 412 }
1067 413
@@ -1072,9 +418,9 @@ static void iwl4965_clear_free_frames(struct iwl_priv *priv)
1072 } 418 }
1073} 419}
1074 420
1075static struct iwl4965_frame *iwl4965_get_free_frame(struct iwl_priv *priv) 421static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
1076{ 422{
1077 struct iwl4965_frame *frame; 423 struct iwl_frame *frame;
1078 struct list_head *element; 424 struct list_head *element;
1079 if (list_empty(&priv->free_frames)) { 425 if (list_empty(&priv->free_frames)) {
1080 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 426 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
@@ -1089,10 +435,10 @@ static struct iwl4965_frame *iwl4965_get_free_frame(struct iwl_priv *priv)
1089 435
1090 element = priv->free_frames.next; 436 element = priv->free_frames.next;
1091 list_del(element); 437 list_del(element);
1092 return list_entry(element, struct iwl4965_frame, list); 438 return list_entry(element, struct iwl_frame, list);
1093} 439}
1094 440
1095static void iwl4965_free_frame(struct iwl_priv *priv, struct iwl4965_frame *frame) 441static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
1096{ 442{
1097 memset(frame, 0, sizeof(*frame)); 443 memset(frame, 0, sizeof(*frame));
1098 list_add(&frame->list, &priv->free_frames); 444 list_add(&frame->list, &priv->free_frames);
@@ -1116,27 +462,39 @@ unsigned int iwl4965_fill_beacon_frame(struct iwl_priv *priv,
1116 return priv->ibss_beacon->len; 462 return priv->ibss_beacon->len;
1117} 463}
1118 464
1119static u8 iwl4965_rate_get_lowest_plcp(int rate_mask) 465static u8 iwl4965_rate_get_lowest_plcp(struct iwl_priv *priv)
1120{ 466{
1121 u8 i; 467 int i;
468 int rate_mask;
469
470 /* Set rate mask*/
471 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
472 rate_mask = priv->active_rate_basic & 0xF;
473 else
474 rate_mask = priv->active_rate_basic & 0xFF0;
1122 475
476 /* Find lowest valid rate */
1123 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; 477 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
1124 i = iwl4965_rates[i].next_ieee) { 478 i = iwl_rates[i].next_ieee) {
1125 if (rate_mask & (1 << i)) 479 if (rate_mask & (1 << i))
1126 return iwl4965_rates[i].plcp; 480 return iwl_rates[i].plcp;
1127 } 481 }
1128 482
1129 return IWL_RATE_INVALID; 483 /* No valid rate was found. Assign the lowest one */
484 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
485 return IWL_RATE_1M_PLCP;
486 else
487 return IWL_RATE_6M_PLCP;
1130} 488}
1131 489
1132static int iwl4965_send_beacon_cmd(struct iwl_priv *priv) 490static int iwl4965_send_beacon_cmd(struct iwl_priv *priv)
1133{ 491{
1134 struct iwl4965_frame *frame; 492 struct iwl_frame *frame;
1135 unsigned int frame_size; 493 unsigned int frame_size;
1136 int rc; 494 int rc;
1137 u8 rate; 495 u8 rate;
1138 496
1139 frame = iwl4965_get_free_frame(priv); 497 frame = iwl_get_free_frame(priv);
1140 498
1141 if (!frame) { 499 if (!frame) {
1142 IWL_ERROR("Could not obtain free frame buffer for beacon " 500 IWL_ERROR("Could not obtain free frame buffer for beacon "
@@ -1144,23 +502,14 @@ static int iwl4965_send_beacon_cmd(struct iwl_priv *priv)
1144 return -ENOMEM; 502 return -ENOMEM;
1145 } 503 }
1146 504
1147 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) { 505 rate = iwl4965_rate_get_lowest_plcp(priv);
1148 rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic &
1149 0xFF0);
1150 if (rate == IWL_INVALID_RATE)
1151 rate = IWL_RATE_6M_PLCP;
1152 } else {
1153 rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
1154 if (rate == IWL_INVALID_RATE)
1155 rate = IWL_RATE_1M_PLCP;
1156 }
1157 506
1158 frame_size = iwl4965_hw_get_beacon_cmd(priv, frame, rate); 507 frame_size = iwl4965_hw_get_beacon_cmd(priv, frame, rate);
1159 508
1160 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, 509 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
1161 &frame->u.cmd[0]); 510 &frame->u.cmd[0]);
1162 511
1163 iwl4965_free_frame(priv, frame); 512 iwl_free_frame(priv, frame);
1164 513
1165 return rc; 514 return rc;
1166} 515}
@@ -1171,184 +520,69 @@ static int iwl4965_send_beacon_cmd(struct iwl_priv *priv)
1171 * 520 *
1172 ******************************************************************************/ 521 ******************************************************************************/
1173 522
1174static void iwl4965_unset_hw_params(struct iwl_priv *priv) 523static void iwl4965_ht_conf(struct iwl_priv *priv,
1175{ 524 struct ieee80211_bss_conf *bss_conf)
1176 if (priv->shared_virt)
1177 pci_free_consistent(priv->pci_dev,
1178 sizeof(struct iwl4965_shared),
1179 priv->shared_virt,
1180 priv->shared_phys);
1181}
1182
1183/**
1184 * iwl4965_supported_rate_to_ie - fill in the supported rate in IE field
1185 *
1186 * return : set the bit for each supported rate insert in ie
1187 */
1188static u16 iwl4965_supported_rate_to_ie(u8 *ie, u16 supported_rate,
1189 u16 basic_rate, int *left)
1190{
1191 u16 ret_rates = 0, bit;
1192 int i;
1193 u8 *cnt = ie;
1194 u8 *rates = ie + 1;
1195
1196 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1197 if (bit & supported_rate) {
1198 ret_rates |= bit;
1199 rates[*cnt] = iwl4965_rates[i].ieee |
1200 ((bit & basic_rate) ? 0x80 : 0x00);
1201 (*cnt)++;
1202 (*left)--;
1203 if ((*left <= 0) ||
1204 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
1205 break;
1206 }
1207 }
1208
1209 return ret_rates;
1210}
1211
1212/**
1213 * iwl4965_fill_probe_req - fill in all required fields and IE for probe request
1214 */
1215static u16 iwl4965_fill_probe_req(struct iwl_priv *priv,
1216 enum ieee80211_band band,
1217 struct ieee80211_mgmt *frame,
1218 int left, int is_direct)
1219{ 525{
1220 int len = 0; 526 struct ieee80211_ht_info *ht_conf = bss_conf->ht_conf;
1221 u8 *pos = NULL; 527 struct ieee80211_ht_bss_info *ht_bss_conf = bss_conf->ht_bss_conf;
1222 u16 active_rates, ret_rates, cck_rates, active_rate_basic; 528 struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
1223#ifdef CONFIG_IWL4965_HT
1224 const struct ieee80211_supported_band *sband =
1225 iwl4965_get_hw_mode(priv, band);
1226#endif /* CONFIG_IWL4965_HT */
1227
1228 /* Make sure there is enough space for the probe request,
1229 * two mandatory IEs and the data */
1230 left -= 24;
1231 if (left < 0)
1232 return 0;
1233 len += 24;
1234 529
1235 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); 530 IWL_DEBUG_MAC80211("enter: \n");
1236 memcpy(frame->da, iwl4965_broadcast_addr, ETH_ALEN);
1237 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
1238 memcpy(frame->bssid, iwl4965_broadcast_addr, ETH_ALEN);
1239 frame->seq_ctrl = 0;
1240 531
1241 /* fill in our indirect SSID IE */ 532 iwl_conf->is_ht = bss_conf->assoc_ht;
1242 /* ...next IE... */
1243 533
1244 left -= 2; 534 if (!iwl_conf->is_ht)
1245 if (left < 0) 535 return;
1246 return 0;
1247 len += 2;
1248 pos = &(frame->u.probe_req.variable[0]);
1249 *pos++ = WLAN_EID_SSID;
1250 *pos++ = 0;
1251
1252 /* fill in our direct SSID IE... */
1253 if (is_direct) {
1254 /* ...next IE... */
1255 left -= 2 + priv->essid_len;
1256 if (left < 0)
1257 return 0;
1258 /* ... fill it in... */
1259 *pos++ = WLAN_EID_SSID;
1260 *pos++ = priv->essid_len;
1261 memcpy(pos, priv->essid, priv->essid_len);
1262 pos += priv->essid_len;
1263 len += 2 + priv->essid_len;
1264 }
1265
1266 /* fill in supported rate */
1267 /* ...next IE... */
1268 left -= 2;
1269 if (left < 0)
1270 return 0;
1271 536
1272 /* ... fill it in... */ 537 priv->ps_mode = (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2);
1273 *pos++ = WLAN_EID_SUPP_RATES;
1274 *pos = 0;
1275 538
1276 /* exclude 60M rate */ 539 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20)
1277 active_rates = priv->rates_mask; 540 iwl_conf->sgf |= HT_SHORT_GI_20MHZ;
1278 active_rates &= ~IWL_RATE_60M_MASK; 541 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40)
542 iwl_conf->sgf |= HT_SHORT_GI_40MHZ;
1279 543
1280 active_rate_basic = active_rates & IWL_BASIC_RATES_MASK; 544 iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD);
545 iwl_conf->max_amsdu_size =
546 !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU);
1281 547
1282 cck_rates = IWL_CCK_RATES_MASK & active_rates; 548 iwl_conf->supported_chan_width =
1283 ret_rates = iwl4965_supported_rate_to_ie(pos, cck_rates, 549 !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH);
1284 active_rate_basic, &left); 550 iwl_conf->extension_chan_offset =
1285 active_rates &= ~ret_rates; 551 ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_SEC_OFFSET;
552 /* If no above or below channel supplied disable FAT channel */
553 if (iwl_conf->extension_chan_offset != IEEE80211_HT_IE_CHA_SEC_ABOVE &&
554 iwl_conf->extension_chan_offset != IEEE80211_HT_IE_CHA_SEC_BELOW) {
555 iwl_conf->extension_chan_offset = IEEE80211_HT_IE_CHA_SEC_NONE;
556 iwl_conf->supported_chan_width = 0;
557 }
1286 558
1287 ret_rates = iwl4965_supported_rate_to_ie(pos, active_rates, 559 iwl_conf->tx_mimo_ps_mode =
1288 active_rate_basic, &left); 560 (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2);
1289 active_rates &= ~ret_rates; 561 memcpy(iwl_conf->supp_mcs_set, ht_conf->supp_mcs_set, 16);
1290 562
1291 len += 2 + *pos; 563 iwl_conf->control_channel = ht_bss_conf->primary_channel;
1292 pos += (*pos) + 1; 564 iwl_conf->tx_chan_width =
1293 if (active_rates == 0) 565 !!(ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_WIDTH);
1294 goto fill_end; 566 iwl_conf->ht_protection =
567 ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_HT_PROTECTION;
568 iwl_conf->non_GF_STA_present =
569 !!(ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_NON_GF_STA_PRSNT);
1295 570
1296 /* fill in supported extended rate */ 571 IWL_DEBUG_MAC80211("control channel %d\n", iwl_conf->control_channel);
1297 /* ...next IE... */ 572 IWL_DEBUG_MAC80211("leave\n");
1298 left -= 2;
1299 if (left < 0)
1300 return 0;
1301 /* ... fill it in... */
1302 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1303 *pos = 0;
1304 iwl4965_supported_rate_to_ie(pos, active_rates,
1305 active_rate_basic, &left);
1306 if (*pos > 0)
1307 len += 2 + *pos;
1308
1309#ifdef CONFIG_IWL4965_HT
1310 if (sband && sband->ht_info.ht_supported) {
1311 struct ieee80211_ht_cap *ht_cap;
1312 pos += (*pos) + 1;
1313 *pos++ = WLAN_EID_HT_CAPABILITY;
1314 *pos++ = sizeof(struct ieee80211_ht_cap);
1315 ht_cap = (struct ieee80211_ht_cap *)pos;
1316 ht_cap->cap_info = cpu_to_le16(sband->ht_info.cap);
1317 memcpy(ht_cap->supp_mcs_set, sband->ht_info.supp_mcs_set, 16);
1318 ht_cap->ampdu_params_info =(sband->ht_info.ampdu_factor &
1319 IEEE80211_HT_CAP_AMPDU_FACTOR) |
1320 ((sband->ht_info.ampdu_density << 2) &
1321 IEEE80211_HT_CAP_AMPDU_DENSITY);
1322 len += 2 + sizeof(struct ieee80211_ht_cap);
1323 }
1324#endif /*CONFIG_IWL4965_HT */
1325
1326 fill_end:
1327 return (u16)len;
1328} 573}
1329 574
1330/* 575/*
1331 * QoS support 576 * QoS support
1332*/ 577*/
1333static int iwl4965_send_qos_params_command(struct iwl_priv *priv, 578static void iwl_activate_qos(struct iwl_priv *priv, u8 force)
1334 struct iwl4965_qosparam_cmd *qos)
1335{
1336
1337 return iwl_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1338 sizeof(struct iwl4965_qosparam_cmd), qos);
1339}
1340
1341static void iwl4965_activate_qos(struct iwl_priv *priv, u8 force)
1342{ 579{
1343 unsigned long flags;
1344
1345 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 580 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1346 return; 581 return;
1347 582
1348 if (!priv->qos_data.qos_enable) 583 if (!priv->qos_data.qos_enable)
1349 return; 584 return;
1350 585
1351 spin_lock_irqsave(&priv->lock, flags);
1352 priv->qos_data.def_qos_parm.qos_flags = 0; 586 priv->qos_data.def_qos_parm.qos_flags = 0;
1353 587
1354 if (priv->qos_data.qos_cap.q_AP.queue_request && 588 if (priv->qos_data.qos_cap.q_AP.queue_request &&
@@ -1359,323 +593,18 @@ static void iwl4965_activate_qos(struct iwl_priv *priv, u8 force)
1359 priv->qos_data.def_qos_parm.qos_flags |= 593 priv->qos_data.def_qos_parm.qos_flags |=
1360 QOS_PARAM_FLG_UPDATE_EDCA_MSK; 594 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1361 595
1362#ifdef CONFIG_IWL4965_HT
1363 if (priv->current_ht_config.is_ht) 596 if (priv->current_ht_config.is_ht)
1364 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK; 597 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
1365#endif /* CONFIG_IWL4965_HT */
1366
1367 spin_unlock_irqrestore(&priv->lock, flags);
1368 598
1369 if (force || iwl_is_associated(priv)) { 599 if (force || iwl_is_associated(priv)) {
1370 IWL_DEBUG_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n", 600 IWL_DEBUG_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
1371 priv->qos_data.qos_active, 601 priv->qos_data.qos_active,
1372 priv->qos_data.def_qos_parm.qos_flags); 602 priv->qos_data.def_qos_parm.qos_flags);
1373 603
1374 iwl4965_send_qos_params_command(priv, 604 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
1375 &(priv->qos_data.def_qos_parm)); 605 sizeof(struct iwl_qosparam_cmd),
1376 } 606 &priv->qos_data.def_qos_parm, NULL);
1377}
1378
1379/*
1380 * Power management (not Tx power!) functions
1381 */
1382#define MSEC_TO_USEC 1024
1383
1384#define NOSLP __constant_cpu_to_le16(0), 0, 0
1385#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
1386#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1387#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1388 __constant_cpu_to_le32(X1), \
1389 __constant_cpu_to_le32(X2), \
1390 __constant_cpu_to_le32(X3), \
1391 __constant_cpu_to_le32(X4)}
1392
1393
1394/* default power management (not Tx power) table values */
1395/* for tim 0-10 */
1396static struct iwl4965_power_vec_entry range_0[IWL_POWER_AC] = {
1397 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1398 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1399 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1400 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1401 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1402 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1403};
1404
1405/* for tim > 10 */
1406static struct iwl4965_power_vec_entry range_1[IWL_POWER_AC] = {
1407 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1408 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1409 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1410 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1411 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1412 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1413 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1414 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1415 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1416 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1417};
1418
1419int iwl4965_power_init_handle(struct iwl_priv *priv)
1420{
1421 int rc = 0, i;
1422 struct iwl4965_power_mgr *pow_data;
1423 int size = sizeof(struct iwl4965_power_vec_entry) * IWL_POWER_AC;
1424 u16 pci_pm;
1425
1426 IWL_DEBUG_POWER("Initialize power \n");
1427
1428 pow_data = &(priv->power_data);
1429
1430 memset(pow_data, 0, sizeof(*pow_data));
1431
1432 pow_data->active_index = IWL_POWER_RANGE_0;
1433 pow_data->dtim_val = 0xffff;
1434
1435 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1436 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1437
1438 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1439 if (rc != 0)
1440 return 0;
1441 else {
1442 struct iwl4965_powertable_cmd *cmd;
1443
1444 IWL_DEBUG_POWER("adjust power command flags\n");
1445
1446 for (i = 0; i < IWL_POWER_AC; i++) {
1447 cmd = &pow_data->pwr_range_0[i].cmd;
1448
1449 if (pci_pm & 0x1)
1450 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1451 else
1452 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1453 }
1454 } 607 }
1455 return rc;
1456}
1457
1458static int iwl4965_update_power_cmd(struct iwl_priv *priv,
1459 struct iwl4965_powertable_cmd *cmd, u32 mode)
1460{
1461 int rc = 0, i;
1462 u8 skip;
1463 u32 max_sleep = 0;
1464 struct iwl4965_power_vec_entry *range;
1465 u8 period = 0;
1466 struct iwl4965_power_mgr *pow_data;
1467
1468 if (mode > IWL_POWER_INDEX_5) {
1469 IWL_DEBUG_POWER("Error invalid power mode \n");
1470 return -1;
1471 }
1472 pow_data = &(priv->power_data);
1473
1474 if (pow_data->active_index == IWL_POWER_RANGE_0)
1475 range = &pow_data->pwr_range_0[0];
1476 else
1477 range = &pow_data->pwr_range_1[1];
1478
1479 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl4965_powertable_cmd));
1480
1481#ifdef IWL_MAC80211_DISABLE
1482 if (priv->assoc_network != NULL) {
1483 unsigned long flags;
1484
1485 period = priv->assoc_network->tim.tim_period;
1486 }
1487#endif /*IWL_MAC80211_DISABLE */
1488 skip = range[mode].no_dtim;
1489
1490 if (period == 0) {
1491 period = 1;
1492 skip = 0;
1493 }
1494
1495 if (skip == 0) {
1496 max_sleep = period;
1497 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1498 } else {
1499 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1500 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1501 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1502 }
1503
1504 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1505 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1506 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1507 }
1508
1509 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1510 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1511 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1512 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1513 le32_to_cpu(cmd->sleep_interval[0]),
1514 le32_to_cpu(cmd->sleep_interval[1]),
1515 le32_to_cpu(cmd->sleep_interval[2]),
1516 le32_to_cpu(cmd->sleep_interval[3]),
1517 le32_to_cpu(cmd->sleep_interval[4]));
1518
1519 return rc;
1520}
1521
1522static int iwl4965_send_power_mode(struct iwl_priv *priv, u32 mode)
1523{
1524 u32 uninitialized_var(final_mode);
1525 int rc;
1526 struct iwl4965_powertable_cmd cmd;
1527
1528 /* If on battery, set to 3,
1529 * if plugged into AC power, set to CAM ("continuously aware mode"),
1530 * else user level */
1531 switch (mode) {
1532 case IWL_POWER_BATTERY:
1533 final_mode = IWL_POWER_INDEX_3;
1534 break;
1535 case IWL_POWER_AC:
1536 final_mode = IWL_POWER_MODE_CAM;
1537 break;
1538 default:
1539 final_mode = mode;
1540 break;
1541 }
1542
1543 cmd.keep_alive_beacons = 0;
1544
1545 iwl4965_update_power_cmd(priv, &cmd, final_mode);
1546
1547 rc = iwl_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
1548
1549 if (final_mode == IWL_POWER_MODE_CAM)
1550 clear_bit(STATUS_POWER_PMI, &priv->status);
1551 else
1552 set_bit(STATUS_POWER_PMI, &priv->status);
1553
1554 return rc;
1555}
1556
1557int iwl4965_is_network_packet(struct iwl_priv *priv, struct ieee80211_hdr *header)
1558{
1559 /* Filter incoming packets to determine if they are targeted toward
1560 * this network, discarding packets coming from ourselves */
1561 switch (priv->iw_mode) {
1562 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
1563 /* packets from our adapter are dropped (echo) */
1564 if (!compare_ether_addr(header->addr2, priv->mac_addr))
1565 return 0;
1566 /* {broad,multi}cast packets to our IBSS go through */
1567 if (is_multicast_ether_addr(header->addr1))
1568 return !compare_ether_addr(header->addr3, priv->bssid);
1569 /* packets to our adapter go through */
1570 return !compare_ether_addr(header->addr1, priv->mac_addr);
1571 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
1572 /* packets from our adapter are dropped (echo) */
1573 if (!compare_ether_addr(header->addr3, priv->mac_addr))
1574 return 0;
1575 /* {broad,multi}cast packets to our BSS go through */
1576 if (is_multicast_ether_addr(header->addr1))
1577 return !compare_ether_addr(header->addr2, priv->bssid);
1578 /* packets to our adapter go through */
1579 return !compare_ether_addr(header->addr1, priv->mac_addr);
1580 default:
1581 break;
1582 }
1583
1584 return 1;
1585}
1586
1587#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1588
1589static const char *iwl4965_get_tx_fail_reason(u32 status)
1590{
1591 switch (status & TX_STATUS_MSK) {
1592 case TX_STATUS_SUCCESS:
1593 return "SUCCESS";
1594 TX_STATUS_ENTRY(SHORT_LIMIT);
1595 TX_STATUS_ENTRY(LONG_LIMIT);
1596 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1597 TX_STATUS_ENTRY(MGMNT_ABORT);
1598 TX_STATUS_ENTRY(NEXT_FRAG);
1599 TX_STATUS_ENTRY(LIFE_EXPIRE);
1600 TX_STATUS_ENTRY(DEST_PS);
1601 TX_STATUS_ENTRY(ABORTED);
1602 TX_STATUS_ENTRY(BT_RETRY);
1603 TX_STATUS_ENTRY(STA_INVALID);
1604 TX_STATUS_ENTRY(FRAG_DROPPED);
1605 TX_STATUS_ENTRY(TID_DISABLE);
1606 TX_STATUS_ENTRY(FRAME_FLUSHED);
1607 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1608 TX_STATUS_ENTRY(TX_LOCKED);
1609 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1610 }
1611
1612 return "UNKNOWN";
1613}
1614
1615/**
1616 * iwl4965_scan_cancel - Cancel any currently executing HW scan
1617 *
1618 * NOTE: priv->mutex is not required before calling this function
1619 */
1620static int iwl4965_scan_cancel(struct iwl_priv *priv)
1621{
1622 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1623 clear_bit(STATUS_SCANNING, &priv->status);
1624 return 0;
1625 }
1626
1627 if (test_bit(STATUS_SCANNING, &priv->status)) {
1628 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1629 IWL_DEBUG_SCAN("Queuing scan abort.\n");
1630 set_bit(STATUS_SCAN_ABORTING, &priv->status);
1631 queue_work(priv->workqueue, &priv->abort_scan);
1632
1633 } else
1634 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
1635
1636 return test_bit(STATUS_SCANNING, &priv->status);
1637 }
1638
1639 return 0;
1640}
1641
1642/**
1643 * iwl4965_scan_cancel_timeout - Cancel any currently executing HW scan
1644 * @ms: amount of time to wait (in milliseconds) for scan to abort
1645 *
1646 * NOTE: priv->mutex must be held before calling this function
1647 */
1648static int iwl4965_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
1649{
1650 unsigned long now = jiffies;
1651 int ret;
1652
1653 ret = iwl4965_scan_cancel(priv);
1654 if (ret && ms) {
1655 mutex_unlock(&priv->mutex);
1656 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
1657 test_bit(STATUS_SCANNING, &priv->status))
1658 msleep(1);
1659 mutex_lock(&priv->mutex);
1660
1661 return test_bit(STATUS_SCANNING, &priv->status);
1662 }
1663
1664 return ret;
1665}
1666
1667static void iwl4965_sequence_reset(struct iwl_priv *priv)
1668{
1669 /* Reset ieee stats */
1670
1671 /* We don't reset the net_device_stats (ieee->stats) on
1672 * re-association */
1673
1674 priv->last_seq_num = -1;
1675 priv->last_frag_num = -1;
1676 priv->last_packet_time = 0;
1677
1678 iwl4965_scan_cancel(priv);
1679} 608}
1680 609
1681#define MAX_UCODE_BEACON_INTERVAL 4096 610#define MAX_UCODE_BEACON_INTERVAL 4096
@@ -1750,46 +679,8 @@ static void iwl4965_setup_rxon_timing(struct iwl_priv *priv)
1750 le16_to_cpu(priv->rxon_timing.atim_window)); 679 le16_to_cpu(priv->rxon_timing.atim_window));
1751} 680}
1752 681
1753static int iwl4965_scan_initiate(struct iwl_priv *priv) 682static void iwl_set_flags_for_band(struct iwl_priv *priv,
1754{ 683 enum ieee80211_band band)
1755 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1756 IWL_ERROR("APs don't scan.\n");
1757 return 0;
1758 }
1759
1760 if (!iwl_is_ready_rf(priv)) {
1761 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
1762 return -EIO;
1763 }
1764
1765 if (test_bit(STATUS_SCANNING, &priv->status)) {
1766 IWL_DEBUG_SCAN("Scan already in progress.\n");
1767 return -EAGAIN;
1768 }
1769
1770 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1771 IWL_DEBUG_SCAN("Scan request while abort pending. "
1772 "Queuing.\n");
1773 return -EAGAIN;
1774 }
1775
1776 IWL_DEBUG_INFO("Starting scan...\n");
1777 if (priv->cfg->sku & IWL_SKU_G)
1778 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
1779 if (priv->cfg->sku & IWL_SKU_A)
1780 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
1781 set_bit(STATUS_SCANNING, &priv->status);
1782 priv->scan_start = jiffies;
1783 priv->scan_pass_start = priv->scan_start;
1784
1785 queue_work(priv->workqueue, &priv->request_scan);
1786
1787 return 0;
1788}
1789
1790
1791static void iwl4965_set_flags_for_phymode(struct iwl_priv *priv,
1792 enum ieee80211_band band)
1793{ 684{
1794 if (band == IEEE80211_BAND_5GHZ) { 685 if (band == IEEE80211_BAND_5GHZ) {
1795 priv->staging_rxon.flags &= 686 priv->staging_rxon.flags &=
@@ -1858,7 +749,7 @@ static void iwl4965_connection_init_rx_config(struct iwl_priv *priv)
1858#endif 749#endif
1859 750
1860 ch_info = iwl_get_channel_info(priv, priv->band, 751 ch_info = iwl_get_channel_info(priv, priv->band,
1861 le16_to_cpu(priv->staging_rxon.channel)); 752 le16_to_cpu(priv->active_rxon.channel));
1862 753
1863 if (!ch_info) 754 if (!ch_info)
1864 ch_info = &priv->channel_info[0]; 755 ch_info = &priv->channel_info[0];
@@ -1874,7 +765,7 @@ static void iwl4965_connection_init_rx_config(struct iwl_priv *priv)
1874 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel); 765 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1875 priv->band = ch_info->band; 766 priv->band = ch_info->band;
1876 767
1877 iwl4965_set_flags_for_phymode(priv, priv->band); 768 iwl_set_flags_for_band(priv, priv->band);
1878 769
1879 priv->staging_rxon.ofdm_basic_rates = 770 priv->staging_rxon.ofdm_basic_rates =
1880 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; 771 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
@@ -1887,38 +778,24 @@ static void iwl4965_connection_init_rx_config(struct iwl_priv *priv)
1887 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN); 778 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1888 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff; 779 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1889 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff; 780 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
1890 iwl4965_set_rxon_chain(priv); 781 iwl_set_rxon_chain(priv);
1891} 782}
1892 783
1893static int iwl4965_set_mode(struct iwl_priv *priv, int mode) 784static int iwl4965_set_mode(struct iwl_priv *priv, int mode)
1894{ 785{
1895 if (mode == IEEE80211_IF_TYPE_IBSS) {
1896 const struct iwl_channel_info *ch_info;
1897
1898 ch_info = iwl_get_channel_info(priv,
1899 priv->band,
1900 le16_to_cpu(priv->staging_rxon.channel));
1901
1902 if (!ch_info || !is_channel_ibss(ch_info)) {
1903 IWL_ERROR("channel %d not IBSS channel\n",
1904 le16_to_cpu(priv->staging_rxon.channel));
1905 return -EINVAL;
1906 }
1907 }
1908
1909 priv->iw_mode = mode; 786 priv->iw_mode = mode;
1910 787
1911 iwl4965_connection_init_rx_config(priv); 788 iwl4965_connection_init_rx_config(priv);
1912 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); 789 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1913 790
1914 iwlcore_clear_stations_table(priv); 791 iwl_clear_stations_table(priv);
1915 792
1916 /* dont commit rxon if rf-kill is on*/ 793 /* dont commit rxon if rf-kill is on*/
1917 if (!iwl_is_ready_rf(priv)) 794 if (!iwl_is_ready_rf(priv))
1918 return -EAGAIN; 795 return -EAGAIN;
1919 796
1920 cancel_delayed_work(&priv->scan_check); 797 cancel_delayed_work(&priv->scan_check);
1921 if (iwl4965_scan_cancel_timeout(priv, 100)) { 798 if (iwl_scan_cancel_timeout(priv, 100)) {
1922 IWL_WARNING("Aborted scan still in progress after 100ms\n"); 799 IWL_WARNING("Aborted scan still in progress after 100ms\n");
1923 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); 800 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
1924 return -EAGAIN; 801 return -EAGAIN;
@@ -1929,448 +806,13 @@ static int iwl4965_set_mode(struct iwl_priv *priv, int mode)
1929 return 0; 806 return 0;
1930} 807}
1931 808
1932static void iwl4965_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
1933 struct ieee80211_tx_control *ctl,
1934 struct iwl_cmd *cmd,
1935 struct sk_buff *skb_frag,
1936 int sta_id)
1937{
1938 struct iwl4965_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
1939 struct iwl_wep_key *wepkey;
1940 int keyidx = 0;
1941
1942 BUG_ON(ctl->key_idx > 3);
1943
1944 switch (keyinfo->alg) {
1945 case ALG_CCMP:
1946 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
1947 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
1948 if (ctl->flags & IEEE80211_TXCTL_AMPDU)
1949 cmd->cmd.tx.tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1950 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
1951 break;
1952
1953 case ALG_TKIP:
1954 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
1955 ieee80211_get_tkip_key(keyinfo->conf, skb_frag,
1956 IEEE80211_TKIP_P2_KEY, cmd->cmd.tx.key);
1957 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
1958 break;
1959
1960 case ALG_WEP:
1961 wepkey = &priv->wep_keys[ctl->key_idx];
1962 cmd->cmd.tx.sec_ctl = 0;
1963 if (priv->default_wep_key) {
1964 /* the WEP key was sent as static */
1965 keyidx = ctl->key_idx;
1966 memcpy(&cmd->cmd.tx.key[3], wepkey->key,
1967 wepkey->key_size);
1968 if (wepkey->key_size == WEP_KEY_LEN_128)
1969 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
1970 } else {
1971 /* the WEP key was sent as dynamic */
1972 keyidx = keyinfo->keyidx;
1973 memcpy(&cmd->cmd.tx.key[3], keyinfo->key,
1974 keyinfo->keylen);
1975 if (keyinfo->keylen == WEP_KEY_LEN_128)
1976 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
1977 }
1978
1979 cmd->cmd.tx.sec_ctl |= (TX_CMD_SEC_WEP |
1980 (keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
1981
1982 IWL_DEBUG_TX("Configuring packet for WEP encryption "
1983 "with key %d\n", keyidx);
1984 break;
1985
1986 default:
1987 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
1988 break;
1989 }
1990}
1991
1992/*
1993 * handle build REPLY_TX command notification.
1994 */
1995static void iwl4965_build_tx_cmd_basic(struct iwl_priv *priv,
1996 struct iwl_cmd *cmd,
1997 struct ieee80211_tx_control *ctrl,
1998 struct ieee80211_hdr *hdr,
1999 int is_unicast, u8 std_id)
2000{
2001 __le16 *qc;
2002 u16 fc = le16_to_cpu(hdr->frame_control);
2003 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2004
2005 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2006 if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
2007 tx_flags |= TX_CMD_FLG_ACK_MSK;
2008 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
2009 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2010 if (ieee80211_is_probe_response(fc) &&
2011 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2012 tx_flags |= TX_CMD_FLG_TSF_MSK;
2013 } else {
2014 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2015 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2016 }
2017
2018 if (ieee80211_is_back_request(fc))
2019 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
2020
2021
2022 cmd->cmd.tx.sta_id = std_id;
2023 if (ieee80211_get_morefrag(hdr))
2024 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2025
2026 qc = ieee80211_get_qos_ctrl(hdr);
2027 if (qc) {
2028 cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
2029 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2030 } else
2031 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2032
2033 if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
2034 tx_flags |= TX_CMD_FLG_RTS_MSK;
2035 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2036 } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
2037 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2038 tx_flags |= TX_CMD_FLG_CTS_MSK;
2039 }
2040
2041 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2042 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2043
2044 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2045 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
2046 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
2047 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
2048 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
2049 else
2050 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
2051 } else {
2052 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
2053 }
2054
2055 cmd->cmd.tx.driver_txop = 0;
2056 cmd->cmd.tx.tx_flags = tx_flags;
2057 cmd->cmd.tx.next_frame_len = 0;
2058}
2059static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2060{
2061 /* 0 - mgmt, 1 - cnt, 2 - data */
2062 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2063 priv->tx_stats[idx].cnt++;
2064 priv->tx_stats[idx].bytes += len;
2065}
2066/**
2067 * iwl4965_get_sta_id - Find station's index within station table
2068 *
2069 * If new IBSS station, create new entry in station table
2070 */
2071static int iwl4965_get_sta_id(struct iwl_priv *priv,
2072 struct ieee80211_hdr *hdr)
2073{
2074 int sta_id;
2075 u16 fc = le16_to_cpu(hdr->frame_control);
2076 DECLARE_MAC_BUF(mac);
2077
2078 /* If this frame is broadcast or management, use broadcast station id */
2079 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2080 is_multicast_ether_addr(hdr->addr1))
2081 return priv->hw_params.bcast_sta_id;
2082
2083 switch (priv->iw_mode) {
2084
2085 /* If we are a client station in a BSS network, use the special
2086 * AP station entry (that's the only station we communicate with) */
2087 case IEEE80211_IF_TYPE_STA:
2088 return IWL_AP_ID;
2089
2090 /* If we are an AP, then find the station, or use BCAST */
2091 case IEEE80211_IF_TYPE_AP:
2092 sta_id = iwl4965_hw_find_station(priv, hdr->addr1);
2093 if (sta_id != IWL_INVALID_STATION)
2094 return sta_id;
2095 return priv->hw_params.bcast_sta_id;
2096
2097 /* If this frame is going out to an IBSS network, find the station,
2098 * or create a new station table entry */
2099 case IEEE80211_IF_TYPE_IBSS:
2100 sta_id = iwl4965_hw_find_station(priv, hdr->addr1);
2101 if (sta_id != IWL_INVALID_STATION)
2102 return sta_id;
2103
2104 /* Create new station table entry */
2105 sta_id = iwl4965_add_station_flags(priv, hdr->addr1,
2106 0, CMD_ASYNC, NULL);
2107
2108 if (sta_id != IWL_INVALID_STATION)
2109 return sta_id;
2110
2111 IWL_DEBUG_DROP("Station %s not in station map. "
2112 "Defaulting to broadcast...\n",
2113 print_mac(mac, hdr->addr1));
2114 iwl_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
2115 return priv->hw_params.bcast_sta_id;
2116
2117 default:
2118 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
2119 return priv->hw_params.bcast_sta_id;
2120 }
2121}
2122
2123/*
2124 * start REPLY_TX command process
2125 */
2126static int iwl4965_tx_skb(struct iwl_priv *priv,
2127 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2128{
2129 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2130 struct iwl4965_tfd_frame *tfd;
2131 u32 *control_flags;
2132 int txq_id = ctl->queue;
2133 struct iwl4965_tx_queue *txq = NULL;
2134 struct iwl4965_queue *q = NULL;
2135 dma_addr_t phys_addr;
2136 dma_addr_t txcmd_phys;
2137 dma_addr_t scratch_phys;
2138 struct iwl_cmd *out_cmd = NULL;
2139 u16 len, idx, len_org;
2140 u8 id, hdr_len, unicast;
2141 u8 sta_id;
2142 u16 seq_number = 0;
2143 u16 fc;
2144 __le16 *qc;
2145 u8 wait_write_ptr = 0;
2146 unsigned long flags;
2147 int rc;
2148
2149 spin_lock_irqsave(&priv->lock, flags);
2150 if (iwl_is_rfkill(priv)) {
2151 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2152 goto drop_unlock;
2153 }
2154
2155 if (!priv->vif) {
2156 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
2157 goto drop_unlock;
2158 }
2159
2160 if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
2161 IWL_ERROR("ERROR: No TX rate available.\n");
2162 goto drop_unlock;
2163 }
2164
2165 unicast = !is_multicast_ether_addr(hdr->addr1);
2166 id = 0;
2167
2168 fc = le16_to_cpu(hdr->frame_control);
2169
2170#ifdef CONFIG_IWLWIFI_DEBUG
2171 if (ieee80211_is_auth(fc))
2172 IWL_DEBUG_TX("Sending AUTH frame\n");
2173 else if (ieee80211_is_assoc_request(fc))
2174 IWL_DEBUG_TX("Sending ASSOC frame\n");
2175 else if (ieee80211_is_reassoc_request(fc))
2176 IWL_DEBUG_TX("Sending REASSOC frame\n");
2177#endif
2178
2179 /* drop all data frame if we are not associated */
2180 if (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) &&
2181 (!iwl_is_associated(priv) ||
2182 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) ||
2183 !priv->assoc_station_added)) {
2184 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
2185 goto drop_unlock;
2186 }
2187
2188 spin_unlock_irqrestore(&priv->lock, flags);
2189
2190 hdr_len = ieee80211_get_hdrlen(fc);
2191
2192 /* Find (or create) index into station table for destination station */
2193 sta_id = iwl4965_get_sta_id(priv, hdr);
2194 if (sta_id == IWL_INVALID_STATION) {
2195 DECLARE_MAC_BUF(mac);
2196
2197 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2198 print_mac(mac, hdr->addr1));
2199 goto drop;
2200 }
2201
2202 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2203
2204 qc = ieee80211_get_qos_ctrl(hdr);
2205 if (qc) {
2206 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2207 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2208 IEEE80211_SCTL_SEQ;
2209 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2210 (hdr->seq_ctrl &
2211 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2212 seq_number += 0x10;
2213#ifdef CONFIG_IWL4965_HT
2214 /* aggregation is on for this <sta,tid> */
2215 if (ctl->flags & IEEE80211_TXCTL_AMPDU)
2216 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
2217 priv->stations[sta_id].tid[tid].tfds_in_queue++;
2218#endif /* CONFIG_IWL4965_HT */
2219 }
2220
2221 /* Descriptor for chosen Tx queue */
2222 txq = &priv->txq[txq_id];
2223 q = &txq->q;
2224
2225 spin_lock_irqsave(&priv->lock, flags);
2226
2227 /* Set up first empty TFD within this queue's circular TFD buffer */
2228 tfd = &txq->bd[q->write_ptr];
2229 memset(tfd, 0, sizeof(*tfd));
2230 control_flags = (u32 *) tfd;
2231 idx = get_cmd_index(q, q->write_ptr, 0);
2232
2233 /* Set up driver data for this TFD */
2234 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl4965_tx_info));
2235 txq->txb[q->write_ptr].skb[0] = skb;
2236 memcpy(&(txq->txb[q->write_ptr].status.control),
2237 ctl, sizeof(struct ieee80211_tx_control));
2238
2239 /* Set up first empty entry in queue's array of Tx/cmd buffers */
2240 out_cmd = &txq->cmd[idx];
2241 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2242 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
2243
2244 /*
2245 * Set up the Tx-command (not MAC!) header.
2246 * Store the chosen Tx queue and TFD index within the sequence field;
2247 * after Tx, uCode's Tx response will return this value so driver can
2248 * locate the frame within the tx queue and do post-tx processing.
2249 */
2250 out_cmd->hdr.cmd = REPLY_TX;
2251 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2252 INDEX_TO_SEQ(q->write_ptr)));
2253
2254 /* Copy MAC header from skb into command buffer */
2255 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2256
2257 /*
2258 * Use the first empty entry in this queue's command buffer array
2259 * to contain the Tx command and MAC header concatenated together
2260 * (payload data will be in another buffer).
2261 * Size of this varies, due to varying MAC header length.
2262 * If end is not dword aligned, we'll have 2 extra bytes at the end
2263 * of the MAC header (device reads on dword boundaries).
2264 * We'll tell device about this padding later.
2265 */
2266 len = priv->hw_params.tx_cmd_len +
2267 sizeof(struct iwl_cmd_header) + hdr_len;
2268
2269 len_org = len;
2270 len = (len + 3) & ~3;
2271
2272 if (len_org != len)
2273 len_org = 1;
2274 else
2275 len_org = 0;
2276
2277 /* Physical address of this Tx command's header (not MAC header!),
2278 * within command buffer array. */
2279 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx +
2280 offsetof(struct iwl_cmd, hdr);
2281
2282 /* Add buffer containing Tx command and MAC(!) header to TFD's
2283 * first entry */
2284 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
2285
2286 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
2287 iwl4965_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, sta_id);
2288
2289 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2290 * if any (802.11 null frames have no payload). */
2291 len = skb->len - hdr_len;
2292 if (len) {
2293 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2294 len, PCI_DMA_TODEVICE);
2295 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
2296 }
2297
2298 /* Tell 4965 about any 2-byte padding after MAC header */
2299 if (len_org)
2300 out_cmd->cmd.tx.tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
2301
2302 /* Total # bytes to be transmitted */
2303 len = (u16)skb->len;
2304 out_cmd->cmd.tx.len = cpu_to_le16(len);
2305
2306 /* TODO need this for burst mode later on */
2307 iwl4965_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
2308
2309 /* set is_hcca to 0; it probably will never be implemented */
2310 iwl4965_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
2311
2312 iwl_update_tx_stats(priv, fc, len);
2313
2314 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
2315 offsetof(struct iwl4965_tx_cmd, scratch);
2316 out_cmd->cmd.tx.dram_lsb_ptr = cpu_to_le32(scratch_phys);
2317 out_cmd->cmd.tx.dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys);
2318
2319 if (!ieee80211_get_morefrag(hdr)) {
2320 txq->need_update = 1;
2321 if (qc) {
2322 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2323 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2324 }
2325 } else {
2326 wait_write_ptr = 1;
2327 txq->need_update = 0;
2328 }
2329
2330 iwl_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
2331 sizeof(out_cmd->cmd.tx));
2332
2333 iwl_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
2334 ieee80211_get_hdrlen(fc));
2335
2336 /* Set up entry for this TFD in Tx byte-count array */
2337 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
2338
2339 /* Tell device the write index *just past* this latest filled TFD */
2340 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
2341 rc = iwl4965_tx_queue_update_write_ptr(priv, txq);
2342 spin_unlock_irqrestore(&priv->lock, flags);
2343
2344 if (rc)
2345 return rc;
2346
2347 if ((iwl4965_queue_space(q) < q->high_mark)
2348 && priv->mac80211_registered) {
2349 if (wait_write_ptr) {
2350 spin_lock_irqsave(&priv->lock, flags);
2351 txq->need_update = 1;
2352 iwl4965_tx_queue_update_write_ptr(priv, txq);
2353 spin_unlock_irqrestore(&priv->lock, flags);
2354 }
2355
2356 ieee80211_stop_queue(priv->hw, ctl->queue);
2357 }
2358
2359 return 0;
2360
2361drop_unlock:
2362 spin_unlock_irqrestore(&priv->lock, flags);
2363drop:
2364 return -1;
2365}
2366
2367static void iwl4965_set_rate(struct iwl_priv *priv) 809static void iwl4965_set_rate(struct iwl_priv *priv)
2368{ 810{
2369 const struct ieee80211_supported_band *hw = NULL; 811 const struct ieee80211_supported_band *hw = NULL;
2370 struct ieee80211_rate *rate; 812 struct ieee80211_rate *rate;
2371 int i; 813 int i;
2372 814
2373 hw = iwl4965_get_hw_mode(priv, priv->band); 815 hw = iwl_get_hw_mode(priv, priv->band);
2374 if (!hw) { 816 if (!hw) {
2375 IWL_ERROR("Failed to set rate: unable to get hw mode\n"); 817 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2376 return; 818 return;
@@ -2411,169 +853,6 @@ static void iwl4965_set_rate(struct iwl_priv *priv)
2411 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; 853 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2412} 854}
2413 855
2414void iwl4965_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
2415{
2416 unsigned long flags;
2417
2418 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2419 return;
2420
2421 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2422 disable_radio ? "OFF" : "ON");
2423
2424 if (disable_radio) {
2425 iwl4965_scan_cancel(priv);
2426 /* FIXME: This is a workaround for AP */
2427 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
2428 spin_lock_irqsave(&priv->lock, flags);
2429 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
2430 CSR_UCODE_SW_BIT_RFKILL);
2431 spin_unlock_irqrestore(&priv->lock, flags);
2432 /* call the host command only if no hw rf-kill set */
2433 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
2434 iwl_is_ready(priv))
2435 iwl4965_send_card_state(priv,
2436 CARD_STATE_CMD_DISABLE,
2437 0);
2438 set_bit(STATUS_RF_KILL_SW, &priv->status);
2439
2440 /* make sure mac80211 stop sending Tx frame */
2441 if (priv->mac80211_registered)
2442 ieee80211_stop_queues(priv->hw);
2443 }
2444 return;
2445 }
2446
2447 spin_lock_irqsave(&priv->lock, flags);
2448 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2449
2450 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2451 spin_unlock_irqrestore(&priv->lock, flags);
2452
2453 /* wake up ucode */
2454 msleep(10);
2455
2456 spin_lock_irqsave(&priv->lock, flags);
2457 iwl_read32(priv, CSR_UCODE_DRV_GP1);
2458 if (!iwl_grab_nic_access(priv))
2459 iwl_release_nic_access(priv);
2460 spin_unlock_irqrestore(&priv->lock, flags);
2461
2462 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2463 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2464 "disabled by HW switch\n");
2465 return;
2466 }
2467
2468 queue_work(priv->workqueue, &priv->restart);
2469 return;
2470}
2471
2472void iwl4965_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
2473 u32 decrypt_res, struct ieee80211_rx_status *stats)
2474{
2475 u16 fc =
2476 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2477
2478 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2479 return;
2480
2481 if (!(fc & IEEE80211_FCTL_PROTECTED))
2482 return;
2483
2484 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2485 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2486 case RX_RES_STATUS_SEC_TYPE_TKIP:
2487 /* The uCode has got a bad phase 1 Key, pushes the packet.
2488 * Decryption will be done in SW. */
2489 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2490 RX_RES_STATUS_BAD_KEY_TTAK)
2491 break;
2492
2493 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2494 RX_RES_STATUS_BAD_ICV_MIC)
2495 stats->flag |= RX_FLAG_MMIC_ERROR;
2496 case RX_RES_STATUS_SEC_TYPE_WEP:
2497 case RX_RES_STATUS_SEC_TYPE_CCMP:
2498 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2499 RX_RES_STATUS_DECRYPT_OK) {
2500 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2501 stats->flag |= RX_FLAG_DECRYPTED;
2502 }
2503 break;
2504
2505 default:
2506 break;
2507 }
2508}
2509
2510
2511#define IWL_PACKET_RETRY_TIME HZ
2512
2513int iwl4965_is_duplicate_packet(struct iwl_priv *priv, struct ieee80211_hdr *header)
2514{
2515 u16 sc = le16_to_cpu(header->seq_ctrl);
2516 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
2517 u16 frag = sc & IEEE80211_SCTL_FRAG;
2518 u16 *last_seq, *last_frag;
2519 unsigned long *last_time;
2520
2521 switch (priv->iw_mode) {
2522 case IEEE80211_IF_TYPE_IBSS:{
2523 struct list_head *p;
2524 struct iwl4965_ibss_seq *entry = NULL;
2525 u8 *mac = header->addr2;
2526 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
2527
2528 __list_for_each(p, &priv->ibss_mac_hash[index]) {
2529 entry = list_entry(p, struct iwl4965_ibss_seq, list);
2530 if (!compare_ether_addr(entry->mac, mac))
2531 break;
2532 }
2533 if (p == &priv->ibss_mac_hash[index]) {
2534 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2535 if (!entry) {
2536 IWL_ERROR("Cannot malloc new mac entry\n");
2537 return 0;
2538 }
2539 memcpy(entry->mac, mac, ETH_ALEN);
2540 entry->seq_num = seq;
2541 entry->frag_num = frag;
2542 entry->packet_time = jiffies;
2543 list_add(&entry->list, &priv->ibss_mac_hash[index]);
2544 return 0;
2545 }
2546 last_seq = &entry->seq_num;
2547 last_frag = &entry->frag_num;
2548 last_time = &entry->packet_time;
2549 break;
2550 }
2551 case IEEE80211_IF_TYPE_STA:
2552 last_seq = &priv->last_seq_num;
2553 last_frag = &priv->last_frag_num;
2554 last_time = &priv->last_packet_time;
2555 break;
2556 default:
2557 return 0;
2558 }
2559 if ((*last_seq == seq) &&
2560 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
2561 if (*last_frag == frag)
2562 goto drop;
2563 if (*last_frag + 1 != frag)
2564 /* out-of-order fragment */
2565 goto drop;
2566 } else
2567 *last_seq = seq;
2568
2569 *last_frag = frag;
2570 *last_time = jiffies;
2571 return 0;
2572
2573 drop:
2574 return 1;
2575}
2576
2577#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT 856#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
2578 857
2579#include "iwl-spectrum.h" 858#include "iwl-spectrum.h"
@@ -2632,7 +911,7 @@ static int iwl4965_get_measurement(struct iwl_priv *priv,
2632 u8 type) 911 u8 type)
2633{ 912{
2634 struct iwl4965_spectrum_cmd spectrum; 913 struct iwl4965_spectrum_cmd spectrum;
2635 struct iwl4965_rx_packet *res; 914 struct iwl_rx_packet *res;
2636 struct iwl_host_cmd cmd = { 915 struct iwl_host_cmd cmd = {
2637 .id = REPLY_SPECTRUM_MEASUREMENT_CMD, 916 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2638 .data = (void *)&spectrum, 917 .data = (void *)&spectrum,
@@ -2677,7 +956,7 @@ static int iwl4965_get_measurement(struct iwl_priv *priv,
2677 if (rc) 956 if (rc)
2678 return rc; 957 return rc;
2679 958
2680 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data; 959 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
2681 if (res->hdr.flags & IWL_CMD_FAILED_MSK) { 960 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
2682 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n"); 961 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
2683 rc = -EIO; 962 rc = -EIO;
@@ -2707,352 +986,16 @@ static int iwl4965_get_measurement(struct iwl_priv *priv,
2707} 986}
2708#endif 987#endif
2709 988
2710static void iwl4965_txstatus_to_ieee(struct iwl_priv *priv,
2711 struct iwl4965_tx_info *tx_sta)
2712{
2713
2714 tx_sta->status.ack_signal = 0;
2715 tx_sta->status.excessive_retries = 0;
2716 tx_sta->status.queue_length = 0;
2717 tx_sta->status.queue_number = 0;
2718
2719 if (in_interrupt())
2720 ieee80211_tx_status_irqsafe(priv->hw,
2721 tx_sta->skb[0], &(tx_sta->status));
2722 else
2723 ieee80211_tx_status(priv->hw,
2724 tx_sta->skb[0], &(tx_sta->status));
2725
2726 tx_sta->skb[0] = NULL;
2727}
2728
2729/**
2730 * iwl4965_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
2731 *
2732 * When FW advances 'R' index, all entries between old and new 'R' index
2733 * need to be reclaimed. As result, some free space forms. If there is
2734 * enough free space (> low mark), wake the stack that feeds us.
2735 */
2736int iwl4965_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
2737{
2738 struct iwl4965_tx_queue *txq = &priv->txq[txq_id];
2739 struct iwl4965_queue *q = &txq->q;
2740 int nfreed = 0;
2741
2742 if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
2743 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
2744 "is out of range [0-%d] %d %d.\n", txq_id,
2745 index, q->n_bd, q->write_ptr, q->read_ptr);
2746 return 0;
2747 }
2748
2749 for (index = iwl_queue_inc_wrap(index, q->n_bd);
2750 q->read_ptr != index;
2751 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2752 if (txq_id != IWL_CMD_QUEUE_NUM) {
2753 iwl4965_txstatus_to_ieee(priv,
2754 &(txq->txb[txq->q.read_ptr]));
2755 iwl4965_hw_txq_free_tfd(priv, txq);
2756 } else if (nfreed > 1) {
2757 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
2758 q->write_ptr, q->read_ptr);
2759 queue_work(priv->workqueue, &priv->restart);
2760 }
2761 nfreed++;
2762 }
2763
2764/* if (iwl4965_queue_space(q) > q->low_mark && (txq_id >= 0) &&
2765 (txq_id != IWL_CMD_QUEUE_NUM) &&
2766 priv->mac80211_registered)
2767 ieee80211_wake_queue(priv->hw, txq_id); */
2768
2769
2770 return nfreed;
2771}
2772
2773static int iwl4965_is_tx_success(u32 status)
2774{
2775 status &= TX_STATUS_MSK;
2776 return (status == TX_STATUS_SUCCESS)
2777 || (status == TX_STATUS_DIRECT_DONE);
2778}
2779
2780/****************************************************************************** 989/******************************************************************************
2781 * 990 *
2782 * Generic RX handler implementations 991 * Generic RX handler implementations
2783 * 992 *
2784 ******************************************************************************/ 993 ******************************************************************************/
2785#ifdef CONFIG_IWL4965_HT 994static void iwl_rx_reply_alive(struct iwl_priv *priv,
2786 995 struct iwl_rx_mem_buffer *rxb)
2787static inline int iwl4965_get_ra_sta_id(struct iwl_priv *priv,
2788 struct ieee80211_hdr *hdr)
2789{ 996{
2790 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) 997 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2791 return IWL_AP_ID; 998 struct iwl_alive_resp *palive;
2792 else {
2793 u8 *da = ieee80211_get_DA(hdr);
2794 return iwl4965_hw_find_station(priv, da);
2795 }
2796}
2797
2798static struct ieee80211_hdr *iwl4965_tx_queue_get_hdr(
2799 struct iwl_priv *priv, int txq_id, int idx)
2800{
2801 if (priv->txq[txq_id].txb[idx].skb[0])
2802 return (struct ieee80211_hdr *)priv->txq[txq_id].
2803 txb[idx].skb[0]->data;
2804 return NULL;
2805}
2806
2807static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
2808{
2809 __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status +
2810 tx_resp->frame_count);
2811 return le32_to_cpu(*scd_ssn) & MAX_SN;
2812
2813}
2814
2815/**
2816 * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
2817 */
2818static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
2819 struct iwl4965_ht_agg *agg,
2820 struct iwl4965_tx_resp_agg *tx_resp,
2821 u16 start_idx)
2822{
2823 u16 status;
2824 struct agg_tx_status *frame_status = &tx_resp->status;
2825 struct ieee80211_tx_status *tx_status = NULL;
2826 struct ieee80211_hdr *hdr = NULL;
2827 int i, sh;
2828 int txq_id, idx;
2829 u16 seq;
2830
2831 if (agg->wait_for_ba)
2832 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
2833
2834 agg->frame_count = tx_resp->frame_count;
2835 agg->start_idx = start_idx;
2836 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
2837 agg->bitmap = 0;
2838
2839 /* # frames attempted by Tx command */
2840 if (agg->frame_count == 1) {
2841 /* Only one frame was attempted; no block-ack will arrive */
2842 status = le16_to_cpu(frame_status[0].status);
2843 seq = le16_to_cpu(frame_status[0].sequence);
2844 idx = SEQ_TO_INDEX(seq);
2845 txq_id = SEQ_TO_QUEUE(seq);
2846
2847 /* FIXME: code repetition */
2848 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2849 agg->frame_count, agg->start_idx, idx);
2850
2851 tx_status = &(priv->txq[txq_id].txb[idx].status);
2852 tx_status->retry_count = tx_resp->failure_frame;
2853 tx_status->queue_number = status & 0xff;
2854 tx_status->queue_length = tx_resp->failure_rts;
2855 tx_status->control.flags &= ~IEEE80211_TXCTL_AMPDU;
2856 tx_status->flags = iwl4965_is_tx_success(status)?
2857 IEEE80211_TX_STATUS_ACK : 0;
2858 iwl4965_hwrate_to_tx_control(priv,
2859 le32_to_cpu(tx_resp->rate_n_flags),
2860 &tx_status->control);
2861 /* FIXME: code repetition end */
2862
2863 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
2864 status & 0xff, tx_resp->failure_frame);
2865 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
2866 iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
2867
2868 agg->wait_for_ba = 0;
2869 } else {
2870 /* Two or more frames were attempted; expect block-ack */
2871 u64 bitmap = 0;
2872 int start = agg->start_idx;
2873
2874 /* Construct bit-map of pending frames within Tx window */
2875 for (i = 0; i < agg->frame_count; i++) {
2876 u16 sc;
2877 status = le16_to_cpu(frame_status[i].status);
2878 seq = le16_to_cpu(frame_status[i].sequence);
2879 idx = SEQ_TO_INDEX(seq);
2880 txq_id = SEQ_TO_QUEUE(seq);
2881
2882 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
2883 AGG_TX_STATE_ABORT_MSK))
2884 continue;
2885
2886 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2887 agg->frame_count, txq_id, idx);
2888
2889 hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, idx);
2890
2891 sc = le16_to_cpu(hdr->seq_ctrl);
2892 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2893 IWL_ERROR("BUG_ON idx doesn't match seq control"
2894 " idx=%d, seq_idx=%d, seq=%d\n",
2895 idx, SEQ_TO_SN(sc),
2896 hdr->seq_ctrl);
2897 return -1;
2898 }
2899
2900 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
2901 i, idx, SEQ_TO_SN(sc));
2902
2903 sh = idx - start;
2904 if (sh > 64) {
2905 sh = (start - idx) + 0xff;
2906 bitmap = bitmap << sh;
2907 sh = 0;
2908 start = idx;
2909 } else if (sh < -64)
2910 sh = 0xff - (start - idx);
2911 else if (sh < 0) {
2912 sh = start - idx;
2913 start = idx;
2914 bitmap = bitmap << sh;
2915 sh = 0;
2916 }
2917 bitmap |= (1 << sh);
2918 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
2919 start, (u32)(bitmap & 0xFFFFFFFF));
2920 }
2921
2922 agg->bitmap = bitmap;
2923 agg->start_idx = start;
2924 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
2925 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2926 agg->frame_count, agg->start_idx,
2927 (unsigned long long)agg->bitmap);
2928
2929 if (bitmap)
2930 agg->wait_for_ba = 1;
2931 }
2932 return 0;
2933}
2934#endif
2935
2936/**
2937 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
2938 */
2939static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2940 struct iwl4965_rx_mem_buffer *rxb)
2941{
2942 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
2943 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2944 int txq_id = SEQ_TO_QUEUE(sequence);
2945 int index = SEQ_TO_INDEX(sequence);
2946 struct iwl4965_tx_queue *txq = &priv->txq[txq_id];
2947 struct ieee80211_tx_status *tx_status;
2948 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2949 u32 status = le32_to_cpu(tx_resp->status);
2950#ifdef CONFIG_IWL4965_HT
2951 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
2952 struct ieee80211_hdr *hdr;
2953 __le16 *qc;
2954#endif
2955
2956 if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
2957 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
2958 "is out of range [0-%d] %d %d\n", txq_id,
2959 index, txq->q.n_bd, txq->q.write_ptr,
2960 txq->q.read_ptr);
2961 return;
2962 }
2963
2964#ifdef CONFIG_IWL4965_HT
2965 hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, index);
2966 qc = ieee80211_get_qos_ctrl(hdr);
2967
2968 if (qc)
2969 tid = le16_to_cpu(*qc) & 0xf;
2970
2971 sta_id = iwl4965_get_ra_sta_id(priv, hdr);
2972 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2973 IWL_ERROR("Station not known\n");
2974 return;
2975 }
2976
2977 if (txq->sched_retry) {
2978 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2979 struct iwl4965_ht_agg *agg = NULL;
2980
2981 if (!qc)
2982 return;
2983
2984 agg = &priv->stations[sta_id].tid[tid].agg;
2985
2986 iwl4965_tx_status_reply_tx(priv, agg,
2987 (struct iwl4965_tx_resp_agg *)tx_resp, index);
2988
2989 if ((tx_resp->frame_count == 1) &&
2990 !iwl4965_is_tx_success(status)) {
2991 /* TODO: send BAR */
2992 }
2993
2994 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2995 int freed;
2996 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2997 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
2998 "%d index %d\n", scd_ssn , index);
2999 freed = iwl4965_tx_queue_reclaim(priv, txq_id, index);
3000 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3001
3002 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3003 txq_id >= 0 && priv->mac80211_registered &&
3004 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3005 ieee80211_wake_queue(priv->hw, txq_id);
3006
3007 iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id);
3008 }
3009 } else {
3010#endif /* CONFIG_IWL4965_HT */
3011 tx_status = &(txq->txb[txq->q.read_ptr].status);
3012
3013 tx_status->retry_count = tx_resp->failure_frame;
3014 tx_status->queue_number = status;
3015 tx_status->queue_length = tx_resp->bt_kill_count;
3016 tx_status->queue_length |= tx_resp->failure_rts;
3017 tx_status->flags =
3018 iwl4965_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
3019 iwl4965_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
3020 &tx_status->control);
3021
3022 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags 0x%x "
3023 "retries %d\n", txq_id, iwl4965_get_tx_fail_reason(status),
3024 status, le32_to_cpu(tx_resp->rate_n_flags),
3025 tx_resp->failure_frame);
3026
3027 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
3028 if (index != -1) {
3029#ifdef CONFIG_IWL4965_HT
3030 int freed = iwl4965_tx_queue_reclaim(priv, txq_id, index);
3031
3032 if (tid != MAX_TID_COUNT)
3033 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3034 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3035 (txq_id >= 0) &&
3036 priv->mac80211_registered)
3037 ieee80211_wake_queue(priv->hw, txq_id);
3038 if (tid != MAX_TID_COUNT)
3039 iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id);
3040#endif
3041 }
3042#ifdef CONFIG_IWL4965_HT
3043 }
3044#endif /* CONFIG_IWL4965_HT */
3045
3046 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
3047 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
3048}
3049
3050
3051static void iwl4965_rx_reply_alive(struct iwl_priv *priv,
3052 struct iwl4965_rx_mem_buffer *rxb)
3053{
3054 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3055 struct iwl4965_alive_resp *palive;
3056 struct delayed_work *pwork; 999 struct delayed_work *pwork;
3057 1000
3058 palive = &pkt->u.alive_frame; 1001 palive = &pkt->u.alive_frame;
@@ -3066,12 +1009,12 @@ static void iwl4965_rx_reply_alive(struct iwl_priv *priv,
3066 IWL_DEBUG_INFO("Initialization Alive received.\n"); 1009 IWL_DEBUG_INFO("Initialization Alive received.\n");
3067 memcpy(&priv->card_alive_init, 1010 memcpy(&priv->card_alive_init,
3068 &pkt->u.alive_frame, 1011 &pkt->u.alive_frame,
3069 sizeof(struct iwl4965_init_alive_resp)); 1012 sizeof(struct iwl_init_alive_resp));
3070 pwork = &priv->init_alive_start; 1013 pwork = &priv->init_alive_start;
3071 } else { 1014 } else {
3072 IWL_DEBUG_INFO("Runtime Alive received.\n"); 1015 IWL_DEBUG_INFO("Runtime Alive received.\n");
3073 memcpy(&priv->card_alive, &pkt->u.alive_frame, 1016 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3074 sizeof(struct iwl4965_alive_resp)); 1017 sizeof(struct iwl_alive_resp));
3075 pwork = &priv->alive_start; 1018 pwork = &priv->alive_start;
3076 } 1019 }
3077 1020
@@ -3084,19 +1027,10 @@ static void iwl4965_rx_reply_alive(struct iwl_priv *priv,
3084 IWL_WARNING("uCode did not respond OK.\n"); 1027 IWL_WARNING("uCode did not respond OK.\n");
3085} 1028}
3086 1029
3087static void iwl4965_rx_reply_add_sta(struct iwl_priv *priv,
3088 struct iwl4965_rx_mem_buffer *rxb)
3089{
3090 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3091
3092 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3093 return;
3094}
3095
3096static void iwl4965_rx_reply_error(struct iwl_priv *priv, 1030static void iwl4965_rx_reply_error(struct iwl_priv *priv,
3097 struct iwl4965_rx_mem_buffer *rxb) 1031 struct iwl_rx_mem_buffer *rxb)
3098{ 1032{
3099 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; 1033 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3100 1034
3101 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) " 1035 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3102 "seq 0x%04X ser 0x%08X\n", 1036 "seq 0x%04X ser 0x%08X\n",
@@ -3109,10 +1043,10 @@ static void iwl4965_rx_reply_error(struct iwl_priv *priv,
3109 1043
3110#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x 1044#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3111 1045
3112static void iwl4965_rx_csa(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb) 1046static void iwl4965_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
3113{ 1047{
3114 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; 1048 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3115 struct iwl4965_rxon_cmd *rxon = (void *)&priv->active_rxon; 1049 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
3116 struct iwl4965_csa_notification *csa = &(pkt->u.csa_notif); 1050 struct iwl4965_csa_notification *csa = &(pkt->u.csa_notif);
3117 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n", 1051 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3118 le16_to_cpu(csa->channel), le32_to_cpu(csa->status)); 1052 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
@@ -3121,15 +1055,15 @@ static void iwl4965_rx_csa(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *
3121} 1055}
3122 1056
3123static void iwl4965_rx_spectrum_measure_notif(struct iwl_priv *priv, 1057static void iwl4965_rx_spectrum_measure_notif(struct iwl_priv *priv,
3124 struct iwl4965_rx_mem_buffer *rxb) 1058 struct iwl_rx_mem_buffer *rxb)
3125{ 1059{
3126#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT 1060#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
3127 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; 1061 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3128 struct iwl4965_spectrum_notification *report = &(pkt->u.spectrum_notif); 1062 struct iwl4965_spectrum_notification *report = &(pkt->u.spectrum_notif);
3129 1063
3130 if (!report->state) { 1064 if (!report->state) {
3131 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO, 1065 IWL_DEBUG(IWL_DL_11H,
3132 "Spectrum Measure Notification: Start\n"); 1066 "Spectrum Measure Notification: Start\n");
3133 return; 1067 return;
3134 } 1068 }
3135 1069
@@ -3139,10 +1073,10 @@ static void iwl4965_rx_spectrum_measure_notif(struct iwl_priv *priv,
3139} 1073}
3140 1074
3141static void iwl4965_rx_pm_sleep_notif(struct iwl_priv *priv, 1075static void iwl4965_rx_pm_sleep_notif(struct iwl_priv *priv,
3142 struct iwl4965_rx_mem_buffer *rxb) 1076 struct iwl_rx_mem_buffer *rxb)
3143{ 1077{
3144#ifdef CONFIG_IWLWIFI_DEBUG 1078#ifdef CONFIG_IWLWIFI_DEBUG
3145 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; 1079 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3146 struct iwl4965_sleep_notification *sleep = &(pkt->u.sleep_notif); 1080 struct iwl4965_sleep_notification *sleep = &(pkt->u.sleep_notif);
3147 IWL_DEBUG_RX("sleep mode: %d, src: %d\n", 1081 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3148 sleep->pm_sleep_mode, sleep->pm_wakeup_src); 1082 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
@@ -3150,13 +1084,13 @@ static void iwl4965_rx_pm_sleep_notif(struct iwl_priv *priv,
3150} 1084}
3151 1085
3152static void iwl4965_rx_pm_debug_statistics_notif(struct iwl_priv *priv, 1086static void iwl4965_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
3153 struct iwl4965_rx_mem_buffer *rxb) 1087 struct iwl_rx_mem_buffer *rxb)
3154{ 1088{
3155 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; 1089 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3156 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled " 1090 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3157 "notification for %s:\n", 1091 "notification for %s:\n",
3158 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd)); 1092 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
3159 iwl_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len)); 1093 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
3160} 1094}
3161 1095
3162static void iwl4965_bg_beacon_update(struct work_struct *work) 1096static void iwl4965_bg_beacon_update(struct work_struct *work)
@@ -3166,7 +1100,7 @@ static void iwl4965_bg_beacon_update(struct work_struct *work)
3166 struct sk_buff *beacon; 1100 struct sk_buff *beacon;
3167 1101
3168 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ 1102 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
3169 beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL); 1103 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
3170 1104
3171 if (!beacon) { 1105 if (!beacon) {
3172 IWL_ERROR("update beacon failed\n"); 1106 IWL_ERROR("update beacon failed\n");
@@ -3184,17 +1118,37 @@ static void iwl4965_bg_beacon_update(struct work_struct *work)
3184 iwl4965_send_beacon_cmd(priv); 1118 iwl4965_send_beacon_cmd(priv);
3185} 1119}
3186 1120
1121/**
1122 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
1123 *
1124 * This callback is provided in order to send a statistics request.
1125 *
1126 * This timer function is continually reset to execute within
1127 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
1128 * was received. We need to ensure we receive the statistics in order
1129 * to update the temperature used for calibrating the TXPOWER.
1130 */
1131static void iwl4965_bg_statistics_periodic(unsigned long data)
1132{
1133 struct iwl_priv *priv = (struct iwl_priv *)data;
1134
1135 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1136 return;
1137
1138 iwl_send_statistics_request(priv, CMD_ASYNC);
1139}
1140
3187static void iwl4965_rx_beacon_notif(struct iwl_priv *priv, 1141static void iwl4965_rx_beacon_notif(struct iwl_priv *priv,
3188 struct iwl4965_rx_mem_buffer *rxb) 1142 struct iwl_rx_mem_buffer *rxb)
3189{ 1143{
3190#ifdef CONFIG_IWLWIFI_DEBUG 1144#ifdef CONFIG_IWLWIFI_DEBUG
3191 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; 1145 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3192 struct iwl4965_beacon_notif *beacon = &(pkt->u.beacon_status); 1146 struct iwl4965_beacon_notif *beacon = &(pkt->u.beacon_status);
3193 u8 rate = iwl4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); 1147 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
3194 1148
3195 IWL_DEBUG_RX("beacon status %x retries %d iss %d " 1149 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3196 "tsf %d %d rate %d\n", 1150 "tsf %d %d rate %d\n",
3197 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, 1151 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
3198 beacon->beacon_notify_hdr.failure_frame, 1152 beacon->beacon_notify_hdr.failure_frame,
3199 le32_to_cpu(beacon->ibss_mgr_status), 1153 le32_to_cpu(beacon->ibss_mgr_status),
3200 le32_to_cpu(beacon->high_tsf), 1154 le32_to_cpu(beacon->high_tsf),
@@ -3206,129 +1160,12 @@ static void iwl4965_rx_beacon_notif(struct iwl_priv *priv,
3206 queue_work(priv->workqueue, &priv->beacon_update); 1160 queue_work(priv->workqueue, &priv->beacon_update);
3207} 1161}
3208 1162
3209/* Service response to REPLY_SCAN_CMD (0x80) */
3210static void iwl4965_rx_reply_scan(struct iwl_priv *priv,
3211 struct iwl4965_rx_mem_buffer *rxb)
3212{
3213#ifdef CONFIG_IWLWIFI_DEBUG
3214 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3215 struct iwl4965_scanreq_notification *notif =
3216 (struct iwl4965_scanreq_notification *)pkt->u.raw;
3217
3218 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3219#endif
3220}
3221
3222/* Service SCAN_START_NOTIFICATION (0x82) */
3223static void iwl4965_rx_scan_start_notif(struct iwl_priv *priv,
3224 struct iwl4965_rx_mem_buffer *rxb)
3225{
3226 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3227 struct iwl4965_scanstart_notification *notif =
3228 (struct iwl4965_scanstart_notification *)pkt->u.raw;
3229 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3230 IWL_DEBUG_SCAN("Scan start: "
3231 "%d [802.11%s] "
3232 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3233 notif->channel,
3234 notif->band ? "bg" : "a",
3235 notif->tsf_high,
3236 notif->tsf_low, notif->status, notif->beacon_timer);
3237}
3238
3239/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
3240static void iwl4965_rx_scan_results_notif(struct iwl_priv *priv,
3241 struct iwl4965_rx_mem_buffer *rxb)
3242{
3243 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3244 struct iwl4965_scanresults_notification *notif =
3245 (struct iwl4965_scanresults_notification *)pkt->u.raw;
3246
3247 IWL_DEBUG_SCAN("Scan ch.res: "
3248 "%d [802.11%s] "
3249 "(TSF: 0x%08X:%08X) - %d "
3250 "elapsed=%lu usec (%dms since last)\n",
3251 notif->channel,
3252 notif->band ? "bg" : "a",
3253 le32_to_cpu(notif->tsf_high),
3254 le32_to_cpu(notif->tsf_low),
3255 le32_to_cpu(notif->statistics[0]),
3256 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3257 jiffies_to_msecs(elapsed_jiffies
3258 (priv->last_scan_jiffies, jiffies)));
3259
3260 priv->last_scan_jiffies = jiffies;
3261 priv->next_scan_jiffies = 0;
3262}
3263
3264/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
3265static void iwl4965_rx_scan_complete_notif(struct iwl_priv *priv,
3266 struct iwl4965_rx_mem_buffer *rxb)
3267{
3268 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3269 struct iwl4965_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
3270
3271 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3272 scan_notif->scanned_channels,
3273 scan_notif->tsf_low,
3274 scan_notif->tsf_high, scan_notif->status);
3275
3276 /* The HW is no longer scanning */
3277 clear_bit(STATUS_SCAN_HW, &priv->status);
3278
3279 /* The scan completion notification came in, so kill that timer... */
3280 cancel_delayed_work(&priv->scan_check);
3281
3282 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3283 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
3284 "2.4" : "5.2",
3285 jiffies_to_msecs(elapsed_jiffies
3286 (priv->scan_pass_start, jiffies)));
3287
3288 /* Remove this scanned band from the list of pending
3289 * bands to scan, band G precedes A in order of scanning
3290 * as seen in iwl_bg_request_scan */
3291 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
3292 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
3293 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
3294 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
3295
3296 /* If a request to abort was given, or the scan did not succeed
3297 * then we reset the scan state machine and terminate,
3298 * re-queuing another scan if one has been requested */
3299 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3300 IWL_DEBUG_INFO("Aborted scan completed.\n");
3301 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3302 } else {
3303 /* If there are more bands on this scan pass reschedule */
3304 if (priv->scan_bands)
3305 goto reschedule;
3306 }
3307
3308 priv->last_scan_jiffies = jiffies;
3309 priv->next_scan_jiffies = 0;
3310 IWL_DEBUG_INFO("Setting scan to off\n");
3311
3312 clear_bit(STATUS_SCANNING, &priv->status);
3313
3314 IWL_DEBUG_INFO("Scan took %dms\n",
3315 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3316
3317 queue_work(priv->workqueue, &priv->scan_completed);
3318
3319 return;
3320
3321reschedule:
3322 priv->scan_pass_start = jiffies;
3323 queue_work(priv->workqueue, &priv->request_scan);
3324}
3325
3326/* Handle notification from uCode that card's power state is changing 1163/* Handle notification from uCode that card's power state is changing
3327 * due to software, hardware, or critical temperature RFKILL */ 1164 * due to software, hardware, or critical temperature RFKILL */
3328static void iwl4965_rx_card_state_notif(struct iwl_priv *priv, 1165static void iwl4965_rx_card_state_notif(struct iwl_priv *priv,
3329 struct iwl4965_rx_mem_buffer *rxb) 1166 struct iwl_rx_mem_buffer *rxb)
3330{ 1167{
3331 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; 1168 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3332 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); 1169 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3333 unsigned long status = priv->status; 1170 unsigned long status = priv->status;
3334 1171
@@ -3383,7 +1220,7 @@ static void iwl4965_rx_card_state_notif(struct iwl_priv *priv,
3383 clear_bit(STATUS_RF_KILL_SW, &priv->status); 1220 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3384 1221
3385 if (!(flags & RXON_CARD_DISABLED)) 1222 if (!(flags & RXON_CARD_DISABLED))
3386 iwl4965_scan_cancel(priv); 1223 iwl_scan_cancel(priv);
3387 1224
3388 if ((test_bit(STATUS_RF_KILL_HW, &status) != 1225 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3389 test_bit(STATUS_RF_KILL_HW, &priv->status)) || 1226 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
@@ -3403,10 +1240,9 @@ static void iwl4965_rx_card_state_notif(struct iwl_priv *priv,
3403 * This function chains into the hardware specific files for them to setup 1240 * This function chains into the hardware specific files for them to setup
3404 * any hardware specific handlers as well. 1241 * any hardware specific handlers as well.
3405 */ 1242 */
3406static void iwl4965_setup_rx_handlers(struct iwl_priv *priv) 1243static void iwl_setup_rx_handlers(struct iwl_priv *priv)
3407{ 1244{
3408 priv->rx_handlers[REPLY_ALIVE] = iwl4965_rx_reply_alive; 1245 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
3409 priv->rx_handlers[REPLY_ADD_STA] = iwl4965_rx_reply_add_sta;
3410 priv->rx_handlers[REPLY_ERROR] = iwl4965_rx_reply_error; 1246 priv->rx_handlers[REPLY_ERROR] = iwl4965_rx_reply_error;
3411 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl4965_rx_csa; 1247 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl4965_rx_csa;
3412 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = 1248 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
@@ -3421,500 +1257,47 @@ static void iwl4965_setup_rx_handlers(struct iwl_priv *priv)
3421 * statistics request from the host as well as for the periodic 1257 * statistics request from the host as well as for the periodic
3422 * statistics notifications (after received beacons) from the uCode. 1258 * statistics notifications (after received beacons) from the uCode.
3423 */ 1259 */
3424 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl4965_hw_rx_statistics; 1260 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
3425 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl4965_hw_rx_statistics; 1261 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
3426
3427 priv->rx_handlers[REPLY_SCAN_CMD] = iwl4965_rx_reply_scan;
3428 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl4965_rx_scan_start_notif;
3429 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
3430 iwl4965_rx_scan_results_notif;
3431 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
3432 iwl4965_rx_scan_complete_notif;
3433 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl4965_rx_card_state_notif;
3434 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
3435
3436 /* Set up hardware specific Rx handlers */
3437 iwl4965_hw_rx_handler_setup(priv);
3438}
3439
3440/**
3441 * iwl4965_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
3442 * @rxb: Rx buffer to reclaim
3443 *
3444 * If an Rx buffer has an async callback associated with it the callback
3445 * will be executed. The attached skb (if present) will only be freed
3446 * if the callback returns 1
3447 */
3448static void iwl4965_tx_cmd_complete(struct iwl_priv *priv,
3449 struct iwl4965_rx_mem_buffer *rxb)
3450{
3451 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
3452 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3453 int txq_id = SEQ_TO_QUEUE(sequence);
3454 int index = SEQ_TO_INDEX(sequence);
3455 int huge = sequence & SEQ_HUGE_FRAME;
3456 int cmd_index;
3457 struct iwl_cmd *cmd;
3458
3459 /* If a Tx command is being handled and it isn't in the actual
3460 * command queue then there a command routing bug has been introduced
3461 * in the queue management code. */
3462 if (txq_id != IWL_CMD_QUEUE_NUM)
3463 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
3464 txq_id, pkt->hdr.cmd);
3465 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3466
3467 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3468 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3469
3470 /* Input error checking is done when commands are added to queue. */
3471 if (cmd->meta.flags & CMD_WANT_SKB) {
3472 cmd->meta.source->u.skb = rxb->skb;
3473 rxb->skb = NULL;
3474 } else if (cmd->meta.u.callback &&
3475 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3476 rxb->skb = NULL;
3477
3478 iwl4965_tx_queue_reclaim(priv, txq_id, index);
3479
3480 if (!(cmd->meta.flags & CMD_ASYNC)) {
3481 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3482 wake_up_interruptible(&priv->wait_command_queue);
3483 }
3484}
3485
3486/************************** RX-FUNCTIONS ****************************/
3487/*
3488 * Rx theory of operation
3489 *
3490 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
3491 * each of which point to Receive Buffers to be filled by 4965. These get
3492 * used not only for Rx frames, but for any command response or notification
3493 * from the 4965. The driver and 4965 manage the Rx buffers by means
3494 * of indexes into the circular buffer.
3495 *
3496 * Rx Queue Indexes
3497 * The host/firmware share two index registers for managing the Rx buffers.
3498 *
3499 * The READ index maps to the first position that the firmware may be writing
3500 * to -- the driver can read up to (but not including) this position and get
3501 * good data.
3502 * The READ index is managed by the firmware once the card is enabled.
3503 *
3504 * The WRITE index maps to the last position the driver has read from -- the
3505 * position preceding WRITE is the last slot the firmware can place a packet.
3506 *
3507 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3508 * WRITE = READ.
3509 *
3510 * During initialization, the host sets up the READ queue position to the first
3511 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3512 *
3513 * When the firmware places a packet in a buffer, it will advance the READ index
3514 * and fire the RX interrupt. The driver can then query the READ index and
3515 * process as many packets as possible, moving the WRITE index forward as it
3516 * resets the Rx queue buffers with new memory.
3517 *
3518 * The management in the driver is as follows:
3519 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3520 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
3521 * to replenish the iwl->rxq->rx_free.
3522 * + In iwl4965_rx_replenish (scheduled) if 'processed' != 'read' then the
3523 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3524 * 'processed' and 'read' driver indexes as well)
3525 * + A received packet is processed and handed to the kernel network stack,
3526 * detached from the iwl->rxq. The driver 'processed' index is updated.
3527 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3528 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3529 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3530 * were enough free buffers and RX_STALLED is set it is cleared.
3531 *
3532 *
3533 * Driver sequence:
3534 *
3535 * iwl4965_rx_queue_alloc() Allocates rx_free
3536 * iwl4965_rx_replenish() Replenishes rx_free list from rx_used, and calls
3537 * iwl4965_rx_queue_restock
3538 * iwl4965_rx_queue_restock() Moves available buffers from rx_free into Rx
3539 * queue, updates firmware pointers, and updates
3540 * the WRITE index. If insufficient rx_free buffers
3541 * are available, schedules iwl4965_rx_replenish
3542 *
3543 * -- enable interrupts --
3544 * ISR - iwl4965_rx() Detach iwl4965_rx_mem_buffers from pool up to the
3545 * READ INDEX, detaching the SKB from the pool.
3546 * Moves the packet buffer from queue to rx_used.
3547 * Calls iwl4965_rx_queue_restock to refill any empty
3548 * slots.
3549 * ...
3550 *
3551 */
3552
3553/**
3554 * iwl4965_rx_queue_space - Return number of free slots available in queue.
3555 */
3556static int iwl4965_rx_queue_space(const struct iwl4965_rx_queue *q)
3557{
3558 int s = q->read - q->write;
3559 if (s <= 0)
3560 s += RX_QUEUE_SIZE;
3561 /* keep some buffer to not confuse full and empty queue */
3562 s -= 2;
3563 if (s < 0)
3564 s = 0;
3565 return s;
3566}
3567
3568/**
3569 * iwl4965_rx_queue_update_write_ptr - Update the write pointer for the RX queue
3570 */
3571int iwl4965_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl4965_rx_queue *q)
3572{
3573 u32 reg = 0;
3574 int rc = 0;
3575 unsigned long flags;
3576
3577 spin_lock_irqsave(&q->lock, flags);
3578
3579 if (q->need_update == 0)
3580 goto exit_unlock;
3581
3582 /* If power-saving is in use, make sure device is awake */
3583 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3584 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
3585
3586 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3587 iwl_set_bit(priv, CSR_GP_CNTRL,
3588 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3589 goto exit_unlock;
3590 }
3591
3592 rc = iwl_grab_nic_access(priv);
3593 if (rc)
3594 goto exit_unlock;
3595
3596 /* Device expects a multiple of 8 */
3597 iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
3598 q->write & ~0x7);
3599 iwl_release_nic_access(priv);
3600
3601 /* Else device is assumed to be awake */
3602 } else
3603 /* Device expects a multiple of 8 */
3604 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
3605 1262
1263 iwl_setup_rx_scan_handlers(priv);
3606 1264
3607 q->need_update = 0; 1265 /* status change handler */
3608 1266 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl4965_rx_card_state_notif;
3609 exit_unlock:
3610 spin_unlock_irqrestore(&q->lock, flags);
3611 return rc;
3612}
3613
3614/**
3615 * iwl4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
3616 */
3617static inline __le32 iwl4965_dma_addr2rbd_ptr(struct iwl_priv *priv,
3618 dma_addr_t dma_addr)
3619{
3620 return cpu_to_le32((u32)(dma_addr >> 8));
3621}
3622
3623
3624/**
3625 * iwl4965_rx_queue_restock - refill RX queue from pre-allocated pool
3626 *
3627 * If there are slots in the RX queue that need to be restocked,
3628 * and we have free pre-allocated buffers, fill the ranks as much
3629 * as we can, pulling from rx_free.
3630 *
3631 * This moves the 'write' index forward to catch up with 'processed', and
3632 * also updates the memory address in the firmware to reference the new
3633 * target buffer.
3634 */
3635static int iwl4965_rx_queue_restock(struct iwl_priv *priv)
3636{
3637 struct iwl4965_rx_queue *rxq = &priv->rxq;
3638 struct list_head *element;
3639 struct iwl4965_rx_mem_buffer *rxb;
3640 unsigned long flags;
3641 int write, rc;
3642
3643 spin_lock_irqsave(&rxq->lock, flags);
3644 write = rxq->write & ~0x7;
3645 while ((iwl4965_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
3646 /* Get next free Rx buffer, remove from free list */
3647 element = rxq->rx_free.next;
3648 rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list);
3649 list_del(element);
3650
3651 /* Point to Rx buffer via next RBD in circular buffer */
3652 rxq->bd[rxq->write] = iwl4965_dma_addr2rbd_ptr(priv, rxb->dma_addr);
3653 rxq->queue[rxq->write] = rxb;
3654 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3655 rxq->free_count--;
3656 }
3657 spin_unlock_irqrestore(&rxq->lock, flags);
3658 /* If the pre-allocated buffer pool is dropping low, schedule to
3659 * refill it */
3660 if (rxq->free_count <= RX_LOW_WATERMARK)
3661 queue_work(priv->workqueue, &priv->rx_replenish);
3662
3663
3664 /* If we've added more space for the firmware to place data, tell it.
3665 * Increment device's write pointer in multiples of 8. */
3666 if ((write != (rxq->write & ~0x7))
3667 || (abs(rxq->write - rxq->read) > 7)) {
3668 spin_lock_irqsave(&rxq->lock, flags);
3669 rxq->need_update = 1;
3670 spin_unlock_irqrestore(&rxq->lock, flags);
3671 rc = iwl4965_rx_queue_update_write_ptr(priv, rxq);
3672 if (rc)
3673 return rc;
3674 }
3675
3676 return 0;
3677}
3678
3679/**
3680 * iwl4965_rx_replenish - Move all used packet from rx_used to rx_free
3681 *
3682 * When moving to rx_free an SKB is allocated for the slot.
3683 *
3684 * Also restock the Rx queue via iwl4965_rx_queue_restock.
3685 * This is called as a scheduled work item (except for during initialization)
3686 */
3687static void iwl4965_rx_allocate(struct iwl_priv *priv)
3688{
3689 struct iwl4965_rx_queue *rxq = &priv->rxq;
3690 struct list_head *element;
3691 struct iwl4965_rx_mem_buffer *rxb;
3692 unsigned long flags;
3693 spin_lock_irqsave(&rxq->lock, flags);
3694 while (!list_empty(&rxq->rx_used)) {
3695 element = rxq->rx_used.next;
3696 rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list);
3697
3698 /* Alloc a new receive buffer */
3699 rxb->skb =
3700 alloc_skb(priv->hw_params.rx_buf_size,
3701 __GFP_NOWARN | GFP_ATOMIC);
3702 if (!rxb->skb) {
3703 if (net_ratelimit())
3704 printk(KERN_CRIT DRV_NAME
3705 ": Can not allocate SKB buffers\n");
3706 /* We don't reschedule replenish work here -- we will
3707 * call the restock method and if it still needs
3708 * more buffers it will schedule replenish */
3709 break;
3710 }
3711 priv->alloc_rxb_skb++;
3712 list_del(element);
3713 1267
3714 /* Get physical address of RB/SKB */ 1268 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
3715 rxb->dma_addr = 1269 iwl_rx_missed_beacon_notif;
3716 pci_map_single(priv->pci_dev, rxb->skb->data, 1270 /* Rx handlers */
3717 priv->hw_params.rx_buf_size, PCI_DMA_FROMDEVICE); 1271 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
3718 list_add_tail(&rxb->list, &rxq->rx_free); 1272 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
3719 rxq->free_count++; 1273 /* block ack */
3720 } 1274 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
3721 spin_unlock_irqrestore(&rxq->lock, flags); 1275 /* Set up hardware specific Rx handlers */
1276 priv->cfg->ops->lib->rx_handler_setup(priv);
3722} 1277}
3723 1278
3724/* 1279/*
3725 * this should be called while priv->lock is locked 1280 * this should be called while priv->lock is locked
3726*/ 1281*/
3727static void __iwl4965_rx_replenish(void *data) 1282static void __iwl_rx_replenish(struct iwl_priv *priv)
3728{ 1283{
3729 struct iwl_priv *priv = data; 1284 iwl_rx_allocate(priv);
3730 1285 iwl_rx_queue_restock(priv);
3731 iwl4965_rx_allocate(priv);
3732 iwl4965_rx_queue_restock(priv);
3733} 1286}
3734 1287
3735 1288
3736void iwl4965_rx_replenish(void *data)
3737{
3738 struct iwl_priv *priv = data;
3739 unsigned long flags;
3740
3741 iwl4965_rx_allocate(priv);
3742
3743 spin_lock_irqsave(&priv->lock, flags);
3744 iwl4965_rx_queue_restock(priv);
3745 spin_unlock_irqrestore(&priv->lock, flags);
3746}
3747
3748/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
3749 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
3750 * This free routine walks the list of POOL entries and if SKB is set to
3751 * non NULL it is unmapped and freed
3752 */
3753static void iwl4965_rx_queue_free(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
3754{
3755 int i;
3756 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3757 if (rxq->pool[i].skb != NULL) {
3758 pci_unmap_single(priv->pci_dev,
3759 rxq->pool[i].dma_addr,
3760 priv->hw_params.rx_buf_size,
3761 PCI_DMA_FROMDEVICE);
3762 dev_kfree_skb(rxq->pool[i].skb);
3763 }
3764 }
3765
3766 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3767 rxq->dma_addr);
3768 rxq->bd = NULL;
3769}
3770
3771int iwl4965_rx_queue_alloc(struct iwl_priv *priv)
3772{
3773 struct iwl4965_rx_queue *rxq = &priv->rxq;
3774 struct pci_dev *dev = priv->pci_dev;
3775 int i;
3776
3777 spin_lock_init(&rxq->lock);
3778 INIT_LIST_HEAD(&rxq->rx_free);
3779 INIT_LIST_HEAD(&rxq->rx_used);
3780
3781 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
3782 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3783 if (!rxq->bd)
3784 return -ENOMEM;
3785
3786 /* Fill the rx_used queue with _all_ of the Rx buffers */
3787 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3788 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3789
3790 /* Set us so that we have processed and used all buffers, but have
3791 * not restocked the Rx queue with fresh buffers */
3792 rxq->read = rxq->write = 0;
3793 rxq->free_count = 0;
3794 rxq->need_update = 0;
3795 return 0;
3796}
3797
3798void iwl4965_rx_queue_reset(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
3799{
3800 unsigned long flags;
3801 int i;
3802 spin_lock_irqsave(&rxq->lock, flags);
3803 INIT_LIST_HEAD(&rxq->rx_free);
3804 INIT_LIST_HEAD(&rxq->rx_used);
3805 /* Fill the rx_used queue with _all_ of the Rx buffers */
3806 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3807 /* In the reset function, these buffers may have been allocated
3808 * to an SKB, so we need to unmap and free potential storage */
3809 if (rxq->pool[i].skb != NULL) {
3810 pci_unmap_single(priv->pci_dev,
3811 rxq->pool[i].dma_addr,
3812 priv->hw_params.rx_buf_size,
3813 PCI_DMA_FROMDEVICE);
3814 priv->alloc_rxb_skb--;
3815 dev_kfree_skb(rxq->pool[i].skb);
3816 rxq->pool[i].skb = NULL;
3817 }
3818 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3819 }
3820
3821 /* Set us so that we have processed and used all buffers, but have
3822 * not restocked the Rx queue with fresh buffers */
3823 rxq->read = rxq->write = 0;
3824 rxq->free_count = 0;
3825 spin_unlock_irqrestore(&rxq->lock, flags);
3826}
3827
3828/* Convert linear signal-to-noise ratio into dB */
3829static u8 ratio2dB[100] = {
3830/* 0 1 2 3 4 5 6 7 8 9 */
3831 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3832 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3833 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3834 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3835 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3836 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3837 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3838 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3839 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3840 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3841};
3842
3843/* Calculates a relative dB value from a ratio of linear
3844 * (i.e. not dB) signal levels.
3845 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
3846int iwl4965_calc_db_from_ratio(int sig_ratio)
3847{
3848 /* 1000:1 or higher just report as 60 dB */
3849 if (sig_ratio >= 1000)
3850 return 60;
3851
3852 /* 100:1 or higher, divide by 10 and use table,
3853 * add 20 dB to make up for divide by 10 */
3854 if (sig_ratio >= 100)
3855 return (20 + (int)ratio2dB[sig_ratio/10]);
3856
3857 /* We shouldn't see this */
3858 if (sig_ratio < 1)
3859 return 0;
3860
3861 /* Use table for ratios 1:1 - 99:1 */
3862 return (int)ratio2dB[sig_ratio];
3863}
3864
3865#define PERFECT_RSSI (-20) /* dBm */
3866#define WORST_RSSI (-95) /* dBm */
3867#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3868
3869/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3870 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3871 * about formulas used below. */
3872int iwl4965_calc_sig_qual(int rssi_dbm, int noise_dbm)
3873{
3874 int sig_qual;
3875 int degradation = PERFECT_RSSI - rssi_dbm;
3876
3877 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3878 * as indicator; formula is (signal dbm - noise dbm).
3879 * SNR at or above 40 is a great signal (100%).
3880 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3881 * Weakest usable signal is usually 10 - 15 dB SNR. */
3882 if (noise_dbm) {
3883 if (rssi_dbm - noise_dbm >= 40)
3884 return 100;
3885 else if (rssi_dbm < noise_dbm)
3886 return 0;
3887 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3888
3889 /* Else use just the signal level.
3890 * This formula is a least squares fit of data points collected and
3891 * compared with a reference system that had a percentage (%) display
3892 * for signal quality. */
3893 } else
3894 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3895 (15 * RSSI_RANGE + 62 * degradation)) /
3896 (RSSI_RANGE * RSSI_RANGE);
3897
3898 if (sig_qual > 100)
3899 sig_qual = 100;
3900 else if (sig_qual < 1)
3901 sig_qual = 0;
3902
3903 return sig_qual;
3904}
3905
3906/** 1289/**
3907 * iwl4965_rx_handle - Main entry function for receiving responses from uCode 1290 * iwl_rx_handle - Main entry function for receiving responses from uCode
3908 * 1291 *
3909 * Uses the priv->rx_handlers callback function array to invoke 1292 * Uses the priv->rx_handlers callback function array to invoke
3910 * the appropriate handlers, including command responses, 1293 * the appropriate handlers, including command responses,
3911 * frame-received notifications, and other notifications. 1294 * frame-received notifications, and other notifications.
3912 */ 1295 */
3913static void iwl4965_rx_handle(struct iwl_priv *priv) 1296void iwl_rx_handle(struct iwl_priv *priv)
3914{ 1297{
3915 struct iwl4965_rx_mem_buffer *rxb; 1298 struct iwl_rx_mem_buffer *rxb;
3916 struct iwl4965_rx_packet *pkt; 1299 struct iwl_rx_packet *pkt;
3917 struct iwl4965_rx_queue *rxq = &priv->rxq; 1300 struct iwl_rx_queue *rxq = &priv->rxq;
3918 u32 r, i; 1301 u32 r, i;
3919 int reclaim; 1302 int reclaim;
3920 unsigned long flags; 1303 unsigned long flags;
@@ -3923,14 +1306,14 @@ static void iwl4965_rx_handle(struct iwl_priv *priv)
3923 1306
3924 /* uCode's read index (stored in shared DRAM) indicates the last Rx 1307 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3925 * buffer that the driver may process (last buffer filled by ucode). */ 1308 * buffer that the driver may process (last buffer filled by ucode). */
3926 r = iwl4965_hw_get_rx_read(priv); 1309 r = priv->cfg->ops->lib->shared_mem_rx_idx(priv);
3927 i = rxq->read; 1310 i = rxq->read;
3928 1311
3929 /* Rx interrupt, but nothing sent from uCode */ 1312 /* Rx interrupt, but nothing sent from uCode */
3930 if (i == r) 1313 if (i == r)
3931 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i); 1314 IWL_DEBUG(IWL_DL_RX, "r = %d, i = %d\n", r, i);
3932 1315
3933 if (iwl4965_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) 1316 if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3934 fill_rx = 1; 1317 fill_rx = 1;
3935 1318
3936 while (i != r) { 1319 while (i != r) {
@@ -3946,7 +1329,7 @@ static void iwl4965_rx_handle(struct iwl_priv *priv)
3946 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr, 1329 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
3947 priv->hw_params.rx_buf_size, 1330 priv->hw_params.rx_buf_size,
3948 PCI_DMA_FROMDEVICE); 1331 PCI_DMA_FROMDEVICE);
3949 pkt = (struct iwl4965_rx_packet *)rxb->skb->data; 1332 pkt = (struct iwl_rx_packet *)rxb->skb->data;
3950 1333
3951 /* Reclaim a command buffer only if this packet is a response 1334 /* Reclaim a command buffer only if this packet is a response
3952 * to a (driver-originated) command. 1335 * to a (driver-originated) command.
@@ -3965,13 +1348,12 @@ static void iwl4965_rx_handle(struct iwl_priv *priv)
3965 * handle those that need handling via function in 1348 * handle those that need handling via function in
3966 * rx_handlers table. See iwl4965_setup_rx_handlers() */ 1349 * rx_handlers table. See iwl4965_setup_rx_handlers() */
3967 if (priv->rx_handlers[pkt->hdr.cmd]) { 1350 if (priv->rx_handlers[pkt->hdr.cmd]) {
3968 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, 1351 IWL_DEBUG(IWL_DL_RX, "r = %d, i = %d, %s, 0x%02x\n", r,
3969 "r = %d, i = %d, %s, 0x%02x\n", r, i, 1352 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3970 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3971 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); 1353 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3972 } else { 1354 } else {
3973 /* No handling needed */ 1355 /* No handling needed */
3974 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, 1356 IWL_DEBUG(IWL_DL_RX,
3975 "r %d i %d No handler needed for %s, 0x%02x\n", 1357 "r %d i %d No handler needed for %s, 0x%02x\n",
3976 r, i, get_cmd_string(pkt->hdr.cmd), 1358 r, i, get_cmd_string(pkt->hdr.cmd),
3977 pkt->hdr.cmd); 1359 pkt->hdr.cmd);
@@ -3982,7 +1364,7 @@ static void iwl4965_rx_handle(struct iwl_priv *priv)
3982 * fire off the (possibly) blocking iwl_send_cmd() 1364 * fire off the (possibly) blocking iwl_send_cmd()
3983 * as we reclaim the driver command queue */ 1365 * as we reclaim the driver command queue */
3984 if (rxb && rxb->skb) 1366 if (rxb && rxb->skb)
3985 iwl4965_tx_cmd_complete(priv, rxb); 1367 iwl_tx_cmd_complete(priv, rxb);
3986 else 1368 else
3987 IWL_WARNING("Claim null rxb?\n"); 1369 IWL_WARNING("Claim null rxb?\n");
3988 } 1370 }
@@ -4009,7 +1391,7 @@ static void iwl4965_rx_handle(struct iwl_priv *priv)
4009 count++; 1391 count++;
4010 if (count >= 8) { 1392 if (count >= 8) {
4011 priv->rxq.read = i; 1393 priv->rxq.read = i;
4012 __iwl4965_rx_replenish(priv); 1394 __iwl_rx_replenish(priv);
4013 count = 0; 1395 count = 0;
4014 } 1396 }
4015 } 1397 }
@@ -4017,62 +1399,17 @@ static void iwl4965_rx_handle(struct iwl_priv *priv)
4017 1399
4018 /* Backtrack one entry */ 1400 /* Backtrack one entry */
4019 priv->rxq.read = i; 1401 priv->rxq.read = i;
4020 iwl4965_rx_queue_restock(priv); 1402 iwl_rx_queue_restock(priv);
4021}
4022
4023/**
4024 * iwl4965_tx_queue_update_write_ptr - Send new write index to hardware
4025 */
4026static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv,
4027 struct iwl4965_tx_queue *txq)
4028{
4029 u32 reg = 0;
4030 int rc = 0;
4031 int txq_id = txq->q.id;
4032
4033 if (txq->need_update == 0)
4034 return rc;
4035
4036 /* if we're trying to save power */
4037 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4038 /* wake up nic if it's powered down ...
4039 * uCode will wake up, and interrupt us again, so next
4040 * time we'll skip this part. */
4041 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
4042
4043 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4044 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
4045 iwl_set_bit(priv, CSR_GP_CNTRL,
4046 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4047 return rc;
4048 }
4049
4050 /* restore this queue's parameters in nic hardware. */
4051 rc = iwl_grab_nic_access(priv);
4052 if (rc)
4053 return rc;
4054 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
4055 txq->q.write_ptr | (txq_id << 8));
4056 iwl_release_nic_access(priv);
4057
4058 /* else not in power-save mode, uCode will never sleep when we're
4059 * trying to tx (during RFKILL, we're not trying to tx). */
4060 } else
4061 iwl_write32(priv, HBUS_TARG_WRPTR,
4062 txq->q.write_ptr | (txq_id << 8));
4063
4064 txq->need_update = 0;
4065
4066 return rc;
4067} 1403}
4068 1404
4069#ifdef CONFIG_IWLWIFI_DEBUG 1405#ifdef CONFIG_IWLWIFI_DEBUG
4070static void iwl4965_print_rx_config_cmd(struct iwl4965_rxon_cmd *rxon) 1406static void iwl4965_print_rx_config_cmd(struct iwl_priv *priv)
4071{ 1407{
1408 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
4072 DECLARE_MAC_BUF(mac); 1409 DECLARE_MAC_BUF(mac);
4073 1410
4074 IWL_DEBUG_RADIO("RX CONFIG:\n"); 1411 IWL_DEBUG_RADIO("RX CONFIG:\n");
4075 iwl_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); 1412 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
4076 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); 1413 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4077 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); 1414 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4078 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n", 1415 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
@@ -4118,173 +1455,6 @@ static inline void iwl4965_disable_interrupts(struct iwl_priv *priv)
4118 IWL_DEBUG_ISR("Disabled interrupts\n"); 1455 IWL_DEBUG_ISR("Disabled interrupts\n");
4119} 1456}
4120 1457
4121static const char *desc_lookup(int i)
4122{
4123 switch (i) {
4124 case 1:
4125 return "FAIL";
4126 case 2:
4127 return "BAD_PARAM";
4128 case 3:
4129 return "BAD_CHECKSUM";
4130 case 4:
4131 return "NMI_INTERRUPT";
4132 case 5:
4133 return "SYSASSERT";
4134 case 6:
4135 return "FATAL_ERROR";
4136 }
4137
4138 return "UNKNOWN";
4139}
4140
4141#define ERROR_START_OFFSET (1 * sizeof(u32))
4142#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4143
4144static void iwl4965_dump_nic_error_log(struct iwl_priv *priv)
4145{
4146 u32 data2, line;
4147 u32 desc, time, count, base, data1;
4148 u32 blink1, blink2, ilink1, ilink2;
4149 int rc;
4150
4151 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4152
4153 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
4154 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4155 return;
4156 }
4157
4158 rc = iwl_grab_nic_access(priv);
4159 if (rc) {
4160 IWL_WARNING("Can not read from adapter at this time.\n");
4161 return;
4162 }
4163
4164 count = iwl_read_targ_mem(priv, base);
4165
4166 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4167 IWL_ERROR("Start IWL Error Log Dump:\n");
4168 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
4169 }
4170
4171 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
4172 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
4173 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
4174 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
4175 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
4176 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
4177 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
4178 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
4179 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
4180
4181 IWL_ERROR("Desc Time "
4182 "data1 data2 line\n");
4183 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
4184 desc_lookup(desc), desc, time, data1, data2, line);
4185 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
4186 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
4187 ilink1, ilink2);
4188
4189 iwl_release_nic_access(priv);
4190}
4191
4192#define EVENT_START_OFFSET (4 * sizeof(u32))
4193
4194/**
4195 * iwl4965_print_event_log - Dump error event log to syslog
4196 *
4197 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
4198 */
4199static void iwl4965_print_event_log(struct iwl_priv *priv, u32 start_idx,
4200 u32 num_events, u32 mode)
4201{
4202 u32 i;
4203 u32 base; /* SRAM byte address of event log header */
4204 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4205 u32 ptr; /* SRAM byte address of log data */
4206 u32 ev, time, data; /* event log data */
4207
4208 if (num_events == 0)
4209 return;
4210
4211 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4212
4213 if (mode == 0)
4214 event_size = 2 * sizeof(u32);
4215 else
4216 event_size = 3 * sizeof(u32);
4217
4218 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4219
4220 /* "time" is actually "data" for mode 0 (no timestamp).
4221 * place event id # at far right for easier visual parsing. */
4222 for (i = 0; i < num_events; i++) {
4223 ev = iwl_read_targ_mem(priv, ptr);
4224 ptr += sizeof(u32);
4225 time = iwl_read_targ_mem(priv, ptr);
4226 ptr += sizeof(u32);
4227 if (mode == 0)
4228 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4229 else {
4230 data = iwl_read_targ_mem(priv, ptr);
4231 ptr += sizeof(u32);
4232 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4233 }
4234 }
4235}
4236
4237static void iwl4965_dump_nic_event_log(struct iwl_priv *priv)
4238{
4239 int rc;
4240 u32 base; /* SRAM byte address of event log header */
4241 u32 capacity; /* event log capacity in # entries */
4242 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4243 u32 num_wraps; /* # times uCode wrapped to top of log */
4244 u32 next_entry; /* index of next entry to be written by uCode */
4245 u32 size; /* # entries that we'll print */
4246
4247 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4248 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
4249 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4250 return;
4251 }
4252
4253 rc = iwl_grab_nic_access(priv);
4254 if (rc) {
4255 IWL_WARNING("Can not read from adapter at this time.\n");
4256 return;
4257 }
4258
4259 /* event log header */
4260 capacity = iwl_read_targ_mem(priv, base);
4261 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
4262 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
4263 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
4264
4265 size = num_wraps ? capacity : next_entry;
4266
4267 /* bail out if nothing in log */
4268 if (size == 0) {
4269 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
4270 iwl_release_nic_access(priv);
4271 return;
4272 }
4273
4274 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
4275 size, num_wraps);
4276
4277 /* if uCode has wrapped back to top of log, start at the oldest entry,
4278 * i.e the next one that uCode would fill. */
4279 if (num_wraps)
4280 iwl4965_print_event_log(priv, next_entry,
4281 capacity - next_entry, mode);
4282
4283 /* (then/else) start at top of log */
4284 iwl4965_print_event_log(priv, 0, next_entry, mode);
4285
4286 iwl_release_nic_access(priv);
4287}
4288 1458
4289/** 1459/**
4290 * iwl4965_irq_handle_error - called for HW or SW error interrupt from card 1460 * iwl4965_irq_handle_error - called for HW or SW error interrupt from card
@@ -4298,10 +1468,10 @@ static void iwl4965_irq_handle_error(struct iwl_priv *priv)
4298 clear_bit(STATUS_HCMD_ACTIVE, &priv->status); 1468 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4299 1469
4300#ifdef CONFIG_IWLWIFI_DEBUG 1470#ifdef CONFIG_IWLWIFI_DEBUG
4301 if (iwl_debug_level & IWL_DL_FW_ERRORS) { 1471 if (priv->debug_level & IWL_DL_FW_ERRORS) {
4302 iwl4965_dump_nic_error_log(priv); 1472 iwl_dump_nic_error_log(priv);
4303 iwl4965_dump_nic_event_log(priv); 1473 iwl_dump_nic_event_log(priv);
4304 iwl4965_print_rx_config_cmd(&priv->staging_rxon); 1474 iwl4965_print_rx_config_cmd(priv);
4305 } 1475 }
4306#endif 1476#endif
4307 1477
@@ -4312,7 +1482,7 @@ static void iwl4965_irq_handle_error(struct iwl_priv *priv)
4312 clear_bit(STATUS_READY, &priv->status); 1482 clear_bit(STATUS_READY, &priv->status);
4313 1483
4314 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { 1484 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4315 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS, 1485 IWL_DEBUG(IWL_DL_FW_ERRORS,
4316 "Restarting adapter due to uCode error.\n"); 1486 "Restarting adapter due to uCode error.\n");
4317 1487
4318 if (iwl_is_associated(priv)) { 1488 if (iwl_is_associated(priv)) {
@@ -4320,7 +1490,8 @@ static void iwl4965_irq_handle_error(struct iwl_priv *priv)
4320 sizeof(priv->recovery_rxon)); 1490 sizeof(priv->recovery_rxon));
4321 priv->error_recovering = 1; 1491 priv->error_recovering = 1;
4322 } 1492 }
4323 queue_work(priv->workqueue, &priv->restart); 1493 if (priv->cfg->mod_params->restart_fw)
1494 queue_work(priv->workqueue, &priv->restart);
4324 } 1495 }
4325} 1496}
4326 1497
@@ -4333,7 +1504,7 @@ static void iwl4965_error_recovery(struct iwl_priv *priv)
4333 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; 1504 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
4334 iwl4965_commit_rxon(priv); 1505 iwl4965_commit_rxon(priv);
4335 1506
4336 iwl4965_rxon_add_station(priv, priv->bssid, 1); 1507 iwl_rxon_add_station(priv, priv->bssid, 1);
4337 1508
4338 spin_lock_irqsave(&priv->lock, flags); 1509 spin_lock_irqsave(&priv->lock, flags);
4339 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id); 1510 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
@@ -4365,7 +1536,7 @@ static void iwl4965_irq_tasklet(struct iwl_priv *priv)
4365 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); 1536 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
4366 1537
4367#ifdef CONFIG_IWLWIFI_DEBUG 1538#ifdef CONFIG_IWLWIFI_DEBUG
4368 if (iwl_debug_level & IWL_DL_ISR) { 1539 if (priv->debug_level & IWL_DL_ISR) {
4369 /* just for debug */ 1540 /* just for debug */
4370 inta_mask = iwl_read32(priv, CSR_INT_MASK); 1541 inta_mask = iwl_read32(priv, CSR_INT_MASK);
4371 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", 1542 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
@@ -4399,7 +1570,7 @@ static void iwl4965_irq_tasklet(struct iwl_priv *priv)
4399 } 1570 }
4400 1571
4401#ifdef CONFIG_IWLWIFI_DEBUG 1572#ifdef CONFIG_IWLWIFI_DEBUG
4402 if (iwl_debug_level & (IWL_DL_ISR)) { 1573 if (priv->debug_level & (IWL_DL_ISR)) {
4403 /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1574 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4404 if (inta & CSR_INT_BIT_SCD) 1575 if (inta & CSR_INT_BIT_SCD)
4405 IWL_DEBUG_ISR("Scheduler finished to transmit " 1576 IWL_DEBUG_ISR("Scheduler finished to transmit "
@@ -4420,18 +1591,15 @@ static void iwl4965_irq_tasklet(struct iwl_priv *priv)
4420 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) 1591 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4421 hw_rf_kill = 1; 1592 hw_rf_kill = 1;
4422 1593
4423 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR, 1594 IWL_DEBUG(IWL_DL_RF_KILL, "RF_KILL bit toggled to %s.\n",
4424 "RF_KILL bit toggled to %s.\n",
4425 hw_rf_kill ? "disable radio":"enable radio"); 1595 hw_rf_kill ? "disable radio":"enable radio");
4426 1596
4427 /* Queue restart only if RF_KILL switch was set to "kill" 1597 /* driver only loads ucode once setting the interface up.
4428 * when we loaded driver, and is now set to "enable". 1598 * the driver as well won't allow loading if RFKILL is set
4429 * After we're Alive, RF_KILL gets handled by 1599 * therefore no need to restart the driver from this handler
4430 * iwl4965_rx_card_state_notif() */ 1600 */
4431 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) { 1601 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status))
4432 clear_bit(STATUS_RF_KILL_HW, &priv->status); 1602 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4433 queue_work(priv->workqueue, &priv->restart);
4434 }
4435 1603
4436 handled |= CSR_INT_BIT_RF_KILL; 1604 handled |= CSR_INT_BIT_RF_KILL;
4437 } 1605 }
@@ -4453,13 +1621,13 @@ static void iwl4965_irq_tasklet(struct iwl_priv *priv)
4453 /* uCode wakes up after power-down sleep */ 1621 /* uCode wakes up after power-down sleep */
4454 if (inta & CSR_INT_BIT_WAKEUP) { 1622 if (inta & CSR_INT_BIT_WAKEUP) {
4455 IWL_DEBUG_ISR("Wakeup interrupt\n"); 1623 IWL_DEBUG_ISR("Wakeup interrupt\n");
4456 iwl4965_rx_queue_update_write_ptr(priv, &priv->rxq); 1624 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4457 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[0]); 1625 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
4458 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[1]); 1626 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
4459 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[2]); 1627 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
4460 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[3]); 1628 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
4461 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[4]); 1629 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
4462 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[5]); 1630 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
4463 1631
4464 handled |= CSR_INT_BIT_WAKEUP; 1632 handled |= CSR_INT_BIT_WAKEUP;
4465 } 1633 }
@@ -4468,13 +1636,16 @@ static void iwl4965_irq_tasklet(struct iwl_priv *priv)
4468 * Rx "responses" (frame-received notification), and other 1636 * Rx "responses" (frame-received notification), and other
4469 * notifications from uCode come through here*/ 1637 * notifications from uCode come through here*/
4470 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1638 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
4471 iwl4965_rx_handle(priv); 1639 iwl_rx_handle(priv);
4472 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1640 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4473 } 1641 }
4474 1642
4475 if (inta & CSR_INT_BIT_FH_TX) { 1643 if (inta & CSR_INT_BIT_FH_TX) {
4476 IWL_DEBUG_ISR("Tx interrupt\n"); 1644 IWL_DEBUG_ISR("Tx interrupt\n");
4477 handled |= CSR_INT_BIT_FH_TX; 1645 handled |= CSR_INT_BIT_FH_TX;
1646 /* FH finished to write, send event */
1647 priv->ucode_write_complete = 1;
1648 wake_up_interruptible(&priv->wait_command_queue);
4478 } 1649 }
4479 1650
4480 if (inta & ~handled) 1651 if (inta & ~handled)
@@ -4492,7 +1663,7 @@ static void iwl4965_irq_tasklet(struct iwl_priv *priv)
4492 iwl4965_enable_interrupts(priv); 1663 iwl4965_enable_interrupts(priv);
4493 1664
4494#ifdef CONFIG_IWLWIFI_DEBUG 1665#ifdef CONFIG_IWLWIFI_DEBUG
4495 if (iwl_debug_level & (IWL_DL_ISR)) { 1666 if (priv->debug_level & (IWL_DL_ISR)) {
4496 inta = iwl_read32(priv, CSR_INT); 1667 inta = iwl_read32(priv, CSR_INT);
4497 inta_mask = iwl_read32(priv, CSR_INT_MASK); 1668 inta_mask = iwl_read32(priv, CSR_INT_MASK);
4498 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); 1669 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
@@ -4561,297 +1732,6 @@ static irqreturn_t iwl4965_isr(int irq, void *data)
4561 return IRQ_NONE; 1732 return IRQ_NONE;
4562} 1733}
4563 1734
4564/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4565 * sending probe req. This should be set long enough to hear probe responses
4566 * from more than one AP. */
4567#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
4568#define IWL_ACTIVE_DWELL_TIME_52 (10)
4569
4570/* For faster active scanning, scan will move to the next channel if fewer than
4571 * PLCP_QUIET_THRESH packets are heard on this channel within
4572 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4573 * time if it's a quiet channel (nothing responded to our probe, and there's
4574 * no other traffic).
4575 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4576#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
4577#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
4578
4579/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4580 * Must be set longer than active dwell time.
4581 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4582#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4583#define IWL_PASSIVE_DWELL_TIME_52 (10)
4584#define IWL_PASSIVE_DWELL_BASE (100)
4585#define IWL_CHANNEL_TUNE_TIME 5
4586
4587static inline u16 iwl4965_get_active_dwell_time(struct iwl_priv *priv,
4588 enum ieee80211_band band)
4589{
4590 if (band == IEEE80211_BAND_5GHZ)
4591 return IWL_ACTIVE_DWELL_TIME_52;
4592 else
4593 return IWL_ACTIVE_DWELL_TIME_24;
4594}
4595
4596static u16 iwl4965_get_passive_dwell_time(struct iwl_priv *priv,
4597 enum ieee80211_band band)
4598{
4599 u16 active = iwl4965_get_active_dwell_time(priv, band);
4600 u16 passive = (band != IEEE80211_BAND_5GHZ) ?
4601 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4602 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4603
4604 if (iwl_is_associated(priv)) {
4605 /* If we're associated, we clamp the maximum passive
4606 * dwell time to be 98% of the beacon interval (minus
4607 * 2 * channel tune time) */
4608 passive = priv->beacon_int;
4609 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4610 passive = IWL_PASSIVE_DWELL_BASE;
4611 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4612 }
4613
4614 if (passive <= active)
4615 passive = active + 1;
4616
4617 return passive;
4618}
4619
4620static int iwl4965_get_channels_for_scan(struct iwl_priv *priv,
4621 enum ieee80211_band band,
4622 u8 is_active, u8 direct_mask,
4623 struct iwl4965_scan_channel *scan_ch)
4624{
4625 const struct ieee80211_channel *channels = NULL;
4626 const struct ieee80211_supported_band *sband;
4627 const struct iwl_channel_info *ch_info;
4628 u16 passive_dwell = 0;
4629 u16 active_dwell = 0;
4630 int added, i;
4631
4632 sband = iwl4965_get_hw_mode(priv, band);
4633 if (!sband)
4634 return 0;
4635
4636 channels = sband->channels;
4637
4638 active_dwell = iwl4965_get_active_dwell_time(priv, band);
4639 passive_dwell = iwl4965_get_passive_dwell_time(priv, band);
4640
4641 for (i = 0, added = 0; i < sband->n_channels; i++) {
4642 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4643 continue;
4644
4645 scan_ch->channel = ieee80211_frequency_to_channel(channels[i].center_freq);
4646
4647 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
4648 if (!is_channel_valid(ch_info)) {
4649 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
4650 scan_ch->channel);
4651 continue;
4652 }
4653
4654 if (!is_active || is_channel_passive(ch_info) ||
4655 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
4656 scan_ch->type = 0; /* passive */
4657 else
4658 scan_ch->type = 1; /* active */
4659
4660 if (scan_ch->type & 1)
4661 scan_ch->type |= (direct_mask << 1);
4662
4663 if (is_channel_narrow(ch_info))
4664 scan_ch->type |= (1 << 7);
4665
4666 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4667 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4668
4669 /* Set txpower levels to defaults */
4670 scan_ch->tpc.dsp_atten = 110;
4671 /* scan_pwr_info->tpc.dsp_atten; */
4672
4673 /*scan_pwr_info->tpc.tx_gain; */
4674 if (band == IEEE80211_BAND_5GHZ)
4675 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4676 else {
4677 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4678 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
4679 * power level:
4680 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
4681 */
4682 }
4683
4684 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4685 scan_ch->channel,
4686 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4687 (scan_ch->type & 1) ?
4688 active_dwell : passive_dwell);
4689
4690 scan_ch++;
4691 added++;
4692 }
4693
4694 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4695 return added;
4696}
4697
4698static void iwl4965_init_hw_rates(struct iwl_priv *priv,
4699 struct ieee80211_rate *rates)
4700{
4701 int i;
4702
4703 for (i = 0; i < IWL_RATE_COUNT; i++) {
4704 rates[i].bitrate = iwl4965_rates[i].ieee * 5;
4705 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4706 rates[i].hw_value_short = i;
4707 rates[i].flags = 0;
4708 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
4709 /*
4710 * If CCK != 1M then set short preamble rate flag.
4711 */
4712 rates[i].flags |=
4713 (iwl4965_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4714 0 : IEEE80211_RATE_SHORT_PREAMBLE;
4715 }
4716 }
4717}
4718
4719/**
4720 * iwl4965_init_geos - Initialize mac80211's geo/channel info based from eeprom
4721 */
4722int iwl4965_init_geos(struct iwl_priv *priv)
4723{
4724 struct iwl_channel_info *ch;
4725 struct ieee80211_supported_band *sband;
4726 struct ieee80211_channel *channels;
4727 struct ieee80211_channel *geo_ch;
4728 struct ieee80211_rate *rates;
4729 int i = 0;
4730
4731 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4732 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
4733 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4734 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4735 return 0;
4736 }
4737
4738 channels = kzalloc(sizeof(struct ieee80211_channel) *
4739 priv->channel_count, GFP_KERNEL);
4740 if (!channels)
4741 return -ENOMEM;
4742
4743 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
4744 GFP_KERNEL);
4745 if (!rates) {
4746 kfree(channels);
4747 return -ENOMEM;
4748 }
4749
4750 /* 5.2GHz channels start after the 2.4GHz channels */
4751 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4752 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
4753 /* just OFDM */
4754 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4755 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
4756
4757 iwl4965_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ);
4758
4759 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4760 sband->channels = channels;
4761 /* OFDM & CCK */
4762 sband->bitrates = rates;
4763 sband->n_bitrates = IWL_RATE_COUNT;
4764
4765 iwl4965_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ);
4766
4767 priv->ieee_channels = channels;
4768 priv->ieee_rates = rates;
4769
4770 iwl4965_init_hw_rates(priv, rates);
4771
4772 for (i = 0; i < priv->channel_count; i++) {
4773 ch = &priv->channel_info[i];
4774
4775 /* FIXME: might be removed if scan is OK */
4776 if (!is_channel_valid(ch))
4777 continue;
4778
4779 if (is_channel_a_band(ch))
4780 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4781 else
4782 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4783
4784 geo_ch = &sband->channels[sband->n_channels++];
4785
4786 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
4787 geo_ch->max_power = ch->max_power_avg;
4788 geo_ch->max_antenna_gain = 0xff;
4789 geo_ch->hw_value = ch->channel;
4790
4791 if (is_channel_valid(ch)) {
4792 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4793 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
4794
4795 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4796 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
4797
4798 if (ch->flags & EEPROM_CHANNEL_RADAR)
4799 geo_ch->flags |= IEEE80211_CHAN_RADAR;
4800
4801 if (ch->max_power_avg > priv->max_channel_txpower_limit)
4802 priv->max_channel_txpower_limit =
4803 ch->max_power_avg;
4804 } else {
4805 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
4806 }
4807
4808 /* Save flags for reg domain usage */
4809 geo_ch->orig_flags = geo_ch->flags;
4810
4811 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
4812 ch->channel, geo_ch->center_freq,
4813 is_channel_a_band(ch) ? "5.2" : "2.4",
4814 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
4815 "restricted" : "valid",
4816 geo_ch->flags);
4817 }
4818
4819 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
4820 priv->cfg->sku & IWL_SKU_A) {
4821 printk(KERN_INFO DRV_NAME
4822 ": Incorrectly detected BG card as ABG. Please send "
4823 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
4824 priv->pci_dev->device, priv->pci_dev->subsystem_device);
4825 priv->cfg->sku &= ~IWL_SKU_A;
4826 }
4827
4828 printk(KERN_INFO DRV_NAME
4829 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
4830 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
4831 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
4832
4833 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
4834 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
4835 &priv->bands[IEEE80211_BAND_2GHZ];
4836 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
4837 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
4838 &priv->bands[IEEE80211_BAND_5GHZ];
4839
4840 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4841
4842 return 0;
4843}
4844
4845/*
4846 * iwl4965_free_geos - undo allocations in iwl4965_init_geos
4847 */
4848void iwl4965_free_geos(struct iwl_priv *priv)
4849{
4850 kfree(priv->ieee_channels);
4851 kfree(priv->ieee_rates);
4852 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
4853}
4854
4855/****************************************************************************** 1735/******************************************************************************
4856 * 1736 *
4857 * uCode download functions 1737 * uCode download functions
@@ -4868,146 +1748,6 @@ static void iwl4965_dealloc_ucode_pci(struct iwl_priv *priv)
4868 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); 1748 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
4869} 1749}
4870 1750
4871/**
4872 * iwl4965_verify_inst_full - verify runtime uCode image in card vs. host,
4873 * looking at all data.
4874 */
4875static int iwl4965_verify_inst_full(struct iwl_priv *priv, __le32 *image,
4876 u32 len)
4877{
4878 u32 val;
4879 u32 save_len = len;
4880 int rc = 0;
4881 u32 errcnt;
4882
4883 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
4884
4885 rc = iwl_grab_nic_access(priv);
4886 if (rc)
4887 return rc;
4888
4889 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
4890
4891 errcnt = 0;
4892 for (; len > 0; len -= sizeof(u32), image++) {
4893 /* read data comes through single port, auto-incr addr */
4894 /* NOTE: Use the debugless read so we don't flood kernel log
4895 * if IWL_DL_IO is set */
4896 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
4897 if (val != le32_to_cpu(*image)) {
4898 IWL_ERROR("uCode INST section is invalid at "
4899 "offset 0x%x, is 0x%x, s/b 0x%x\n",
4900 save_len - len, val, le32_to_cpu(*image));
4901 rc = -EIO;
4902 errcnt++;
4903 if (errcnt >= 20)
4904 break;
4905 }
4906 }
4907
4908 iwl_release_nic_access(priv);
4909
4910 if (!errcnt)
4911 IWL_DEBUG_INFO
4912 ("ucode image in INSTRUCTION memory is good\n");
4913
4914 return rc;
4915}
4916
4917
4918/**
4919 * iwl4965_verify_inst_sparse - verify runtime uCode image in card vs. host,
4920 * using sample data 100 bytes apart. If these sample points are good,
4921 * it's a pretty good bet that everything between them is good, too.
4922 */
4923static int iwl4965_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
4924{
4925 u32 val;
4926 int rc = 0;
4927 u32 errcnt = 0;
4928 u32 i;
4929
4930 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
4931
4932 rc = iwl_grab_nic_access(priv);
4933 if (rc)
4934 return rc;
4935
4936 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
4937 /* read data comes through single port, auto-incr addr */
4938 /* NOTE: Use the debugless read so we don't flood kernel log
4939 * if IWL_DL_IO is set */
4940 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
4941 i + RTC_INST_LOWER_BOUND);
4942 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
4943 if (val != le32_to_cpu(*image)) {
4944#if 0 /* Enable this if you want to see details */
4945 IWL_ERROR("uCode INST section is invalid at "
4946 "offset 0x%x, is 0x%x, s/b 0x%x\n",
4947 i, val, *image);
4948#endif
4949 rc = -EIO;
4950 errcnt++;
4951 if (errcnt >= 3)
4952 break;
4953 }
4954 }
4955
4956 iwl_release_nic_access(priv);
4957
4958 return rc;
4959}
4960
4961
4962/**
4963 * iwl4965_verify_ucode - determine which instruction image is in SRAM,
4964 * and verify its contents
4965 */
4966static int iwl4965_verify_ucode(struct iwl_priv *priv)
4967{
4968 __le32 *image;
4969 u32 len;
4970 int rc = 0;
4971
4972 /* Try bootstrap */
4973 image = (__le32 *)priv->ucode_boot.v_addr;
4974 len = priv->ucode_boot.len;
4975 rc = iwl4965_verify_inst_sparse(priv, image, len);
4976 if (rc == 0) {
4977 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
4978 return 0;
4979 }
4980
4981 /* Try initialize */
4982 image = (__le32 *)priv->ucode_init.v_addr;
4983 len = priv->ucode_init.len;
4984 rc = iwl4965_verify_inst_sparse(priv, image, len);
4985 if (rc == 0) {
4986 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
4987 return 0;
4988 }
4989
4990 /* Try runtime/protocol */
4991 image = (__le32 *)priv->ucode_code.v_addr;
4992 len = priv->ucode_code.len;
4993 rc = iwl4965_verify_inst_sparse(priv, image, len);
4994 if (rc == 0) {
4995 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
4996 return 0;
4997 }
4998
4999 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5000
5001 /* Since nothing seems to match, show first several data entries in
5002 * instruction SRAM, so maybe visual inspection will give a clue.
5003 * Selection of bootstrap image (vs. other images) is arbitrary. */
5004 image = (__le32 *)priv->ucode_boot.v_addr;
5005 len = priv->ucode_boot.len;
5006 rc = iwl4965_verify_inst_full(priv, image, len);
5007
5008 return rc;
5009}
5010
5011static void iwl4965_nic_start(struct iwl_priv *priv) 1751static void iwl4965_nic_start(struct iwl_priv *priv)
5012{ 1752{
5013 /* Remove all resets to allow NIC to operate */ 1753 /* Remove all resets to allow NIC to operate */
@@ -5022,7 +1762,7 @@ static void iwl4965_nic_start(struct iwl_priv *priv)
5022 */ 1762 */
5023static int iwl4965_read_ucode(struct iwl_priv *priv) 1763static int iwl4965_read_ucode(struct iwl_priv *priv)
5024{ 1764{
5025 struct iwl4965_ucode *ucode; 1765 struct iwl_ucode *ucode;
5026 int ret; 1766 int ret;
5027 const struct firmware *ucode_raw; 1767 const struct firmware *ucode_raw;
5028 const char *name = priv->cfg->fw_name; 1768 const char *name = priv->cfg->fw_name;
@@ -5083,34 +1823,34 @@ static int iwl4965_read_ucode(struct iwl_priv *priv)
5083 } 1823 }
5084 1824
5085 /* Verify that uCode images will fit in card's SRAM */ 1825 /* Verify that uCode images will fit in card's SRAM */
5086 if (inst_size > IWL_MAX_INST_SIZE) { 1826 if (inst_size > priv->hw_params.max_inst_size) {
5087 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n", 1827 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5088 inst_size); 1828 inst_size);
5089 ret = -EINVAL; 1829 ret = -EINVAL;
5090 goto err_release; 1830 goto err_release;
5091 } 1831 }
5092 1832
5093 if (data_size > IWL_MAX_DATA_SIZE) { 1833 if (data_size > priv->hw_params.max_data_size) {
5094 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n", 1834 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5095 data_size); 1835 data_size);
5096 ret = -EINVAL; 1836 ret = -EINVAL;
5097 goto err_release; 1837 goto err_release;
5098 } 1838 }
5099 if (init_size > IWL_MAX_INST_SIZE) { 1839 if (init_size > priv->hw_params.max_inst_size) {
5100 IWL_DEBUG_INFO 1840 IWL_DEBUG_INFO
5101 ("uCode init instr len %d too large to fit in\n", 1841 ("uCode init instr len %d too large to fit in\n",
5102 init_size); 1842 init_size);
5103 ret = -EINVAL; 1843 ret = -EINVAL;
5104 goto err_release; 1844 goto err_release;
5105 } 1845 }
5106 if (init_data_size > IWL_MAX_DATA_SIZE) { 1846 if (init_data_size > priv->hw_params.max_data_size) {
5107 IWL_DEBUG_INFO 1847 IWL_DEBUG_INFO
5108 ("uCode init data len %d too large to fit in\n", 1848 ("uCode init data len %d too large to fit in\n",
5109 init_data_size); 1849 init_data_size);
5110 ret = -EINVAL; 1850 ret = -EINVAL;
5111 goto err_release; 1851 goto err_release;
5112 } 1852 }
5113 if (boot_size > IWL_MAX_BSM_SIZE) { 1853 if (boot_size > priv->hw_params.max_bsm_size) {
5114 IWL_DEBUG_INFO 1854 IWL_DEBUG_INFO
5115 ("uCode boot instr len %d too large to fit in\n", 1855 ("uCode boot instr len %d too large to fit in\n",
5116 boot_size); 1856 boot_size);
@@ -5211,111 +1951,12 @@ static int iwl4965_read_ucode(struct iwl_priv *priv)
5211 return ret; 1951 return ret;
5212} 1952}
5213 1953
5214
5215/**
5216 * iwl4965_set_ucode_ptrs - Set uCode address location
5217 *
5218 * Tell initialization uCode where to find runtime uCode.
5219 *
5220 * BSM registers initially contain pointers to initialization uCode.
5221 * We need to replace them to load runtime uCode inst and data,
5222 * and to save runtime data when powering down.
5223 */
5224static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
5225{
5226 dma_addr_t pinst;
5227 dma_addr_t pdata;
5228 int rc = 0;
5229 unsigned long flags;
5230
5231 /* bits 35:4 for 4965 */
5232 pinst = priv->ucode_code.p_addr >> 4;
5233 pdata = priv->ucode_data_backup.p_addr >> 4;
5234
5235 spin_lock_irqsave(&priv->lock, flags);
5236 rc = iwl_grab_nic_access(priv);
5237 if (rc) {
5238 spin_unlock_irqrestore(&priv->lock, flags);
5239 return rc;
5240 }
5241
5242 /* Tell bootstrap uCode where to find image to load */
5243 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5244 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5245 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
5246 priv->ucode_data.len);
5247
5248 /* Inst bytecount must be last to set up, bit 31 signals uCode
5249 * that all new ptr/size info is in place */
5250 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
5251 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5252
5253 iwl_release_nic_access(priv);
5254
5255 spin_unlock_irqrestore(&priv->lock, flags);
5256
5257 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5258
5259 return rc;
5260}
5261
5262/**
5263 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
5264 *
5265 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5266 *
5267 * The 4965 "initialize" ALIVE reply contains calibration data for:
5268 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
5269 * (3945 does not contain this data).
5270 *
5271 * Tell "initialize" uCode to go ahead and load the runtime uCode.
5272*/
5273static void iwl4965_init_alive_start(struct iwl_priv *priv)
5274{
5275 /* Check alive response for "valid" sign from uCode */
5276 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5277 /* We had an error bringing up the hardware, so take it
5278 * all the way back down so we can try again */
5279 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5280 goto restart;
5281 }
5282
5283 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5284 * This is a paranoid check, because we would not have gotten the
5285 * "initialize" alive if code weren't properly loaded. */
5286 if (iwl4965_verify_ucode(priv)) {
5287 /* Runtime instruction load was bad;
5288 * take it all the way back down so we can try again */
5289 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5290 goto restart;
5291 }
5292
5293 /* Calculate temperature */
5294 priv->temperature = iwl4965_get_temperature(priv);
5295
5296 /* Send pointers to protocol/runtime uCode image ... init code will
5297 * load and launch runtime uCode, which will send us another "Alive"
5298 * notification. */
5299 IWL_DEBUG_INFO("Initialization Alive received.\n");
5300 if (iwl4965_set_ucode_ptrs(priv)) {
5301 /* Runtime instruction load won't happen;
5302 * take it all the way back down so we can try again */
5303 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5304 goto restart;
5305 }
5306 return;
5307
5308 restart:
5309 queue_work(priv->workqueue, &priv->restart);
5310}
5311
5312
5313/** 1954/**
5314 * iwl4965_alive_start - called after REPLY_ALIVE notification received 1955 * iwl_alive_start - called after REPLY_ALIVE notification received
5315 * from protocol/runtime uCode (initialization uCode's 1956 * from protocol/runtime uCode (initialization uCode's
5316 * Alive gets handled by iwl4965_init_alive_start()). 1957 * Alive gets handled by iwl_init_alive_start()).
5317 */ 1958 */
5318static void iwl4965_alive_start(struct iwl_priv *priv) 1959static void iwl_alive_start(struct iwl_priv *priv)
5319{ 1960{
5320 int ret = 0; 1961 int ret = 0;
5321 1962
@@ -5331,15 +1972,14 @@ static void iwl4965_alive_start(struct iwl_priv *priv)
5331 /* Initialize uCode has loaded Runtime uCode ... verify inst image. 1972 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5332 * This is a paranoid check, because we would not have gotten the 1973 * This is a paranoid check, because we would not have gotten the
5333 * "runtime" alive if code weren't properly loaded. */ 1974 * "runtime" alive if code weren't properly loaded. */
5334 if (iwl4965_verify_ucode(priv)) { 1975 if (iwl_verify_ucode(priv)) {
5335 /* Runtime instruction load was bad; 1976 /* Runtime instruction load was bad;
5336 * take it all the way back down so we can try again */ 1977 * take it all the way back down so we can try again */
5337 IWL_DEBUG_INFO("Bad runtime uCode load.\n"); 1978 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5338 goto restart; 1979 goto restart;
5339 } 1980 }
5340 1981
5341 iwlcore_clear_stations_table(priv); 1982 iwl_clear_stations_table(priv);
5342
5343 ret = priv->cfg->ops->lib->alive_notify(priv); 1983 ret = priv->cfg->ops->lib->alive_notify(priv);
5344 if (ret) { 1984 if (ret) {
5345 IWL_WARNING("Could not complete ALIVE transition [ntf]: %d\n", 1985 IWL_WARNING("Could not complete ALIVE transition [ntf]: %d\n",
@@ -5350,22 +1990,17 @@ static void iwl4965_alive_start(struct iwl_priv *priv)
5350 /* After the ALIVE response, we can send host commands to 4965 uCode */ 1990 /* After the ALIVE response, we can send host commands to 4965 uCode */
5351 set_bit(STATUS_ALIVE, &priv->status); 1991 set_bit(STATUS_ALIVE, &priv->status);
5352 1992
5353 /* Clear out the uCode error bit if it is set */
5354 clear_bit(STATUS_FW_ERROR, &priv->status);
5355
5356 if (iwl_is_rfkill(priv)) 1993 if (iwl_is_rfkill(priv))
5357 return; 1994 return;
5358 1995
5359 ieee80211_start_queues(priv->hw); 1996 ieee80211_wake_queues(priv->hw);
5360 1997
5361 priv->active_rate = priv->rates_mask; 1998 priv->active_rate = priv->rates_mask;
5362 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; 1999 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5363 2000
5364 iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
5365
5366 if (iwl_is_associated(priv)) { 2001 if (iwl_is_associated(priv)) {
5367 struct iwl4965_rxon_cmd *active_rxon = 2002 struct iwl_rxon_cmd *active_rxon =
5368 (struct iwl4965_rxon_cmd *)(&priv->active_rxon); 2003 (struct iwl_rxon_cmd *)&priv->active_rxon;
5369 2004
5370 memcpy(&priv->staging_rxon, &priv->active_rxon, 2005 memcpy(&priv->staging_rxon, &priv->active_rxon,
5371 sizeof(priv->staging_rxon)); 2006 sizeof(priv->staging_rxon));
@@ -5379,13 +2014,13 @@ static void iwl4965_alive_start(struct iwl_priv *priv)
5379 /* Configure Bluetooth device coexistence support */ 2014 /* Configure Bluetooth device coexistence support */
5380 iwl4965_send_bt_config(priv); 2015 iwl4965_send_bt_config(priv);
5381 2016
2017 iwl_reset_run_time_calib(priv);
2018
5382 /* Configure the adapter for unassociated operation */ 2019 /* Configure the adapter for unassociated operation */
5383 iwl4965_commit_rxon(priv); 2020 iwl4965_commit_rxon(priv);
5384 2021
5385 /* At this point, the NIC is initialized and operational */ 2022 /* At this point, the NIC is initialized and operational */
5386 priv->notif_missed_beacons = 0; 2023 iwl_rf_kill_ct_config(priv);
5387
5388 iwl4965_rf_kill_ct_config(priv);
5389 2024
5390 iwl_leds_register(priv); 2025 iwl_leds_register(priv);
5391 2026
@@ -5396,34 +2031,33 @@ static void iwl4965_alive_start(struct iwl_priv *priv)
5396 if (priv->error_recovering) 2031 if (priv->error_recovering)
5397 iwl4965_error_recovery(priv); 2032 iwl4965_error_recovery(priv);
5398 2033
5399 iwlcore_low_level_notify(priv, IWLCORE_START_EVT); 2034 iwl_power_update_mode(priv, 1);
5400 ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC); 2035 ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
2036
2037 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
2038 iwl4965_set_mode(priv, priv->iw_mode);
2039
5401 return; 2040 return;
5402 2041
5403 restart: 2042 restart:
5404 queue_work(priv->workqueue, &priv->restart); 2043 queue_work(priv->workqueue, &priv->restart);
5405} 2044}
5406 2045
5407static void iwl4965_cancel_deferred_work(struct iwl_priv *priv); 2046static void iwl_cancel_deferred_work(struct iwl_priv *priv);
5408 2047
5409static void __iwl4965_down(struct iwl_priv *priv) 2048static void __iwl4965_down(struct iwl_priv *priv)
5410{ 2049{
5411 unsigned long flags; 2050 unsigned long flags;
5412 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); 2051 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5413 struct ieee80211_conf *conf = NULL;
5414 2052
5415 IWL_DEBUG_INFO(DRV_NAME " is going down\n"); 2053 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5416 2054
5417 conf = ieee80211_get_hw_conf(priv->hw);
5418
5419 if (!exit_pending) 2055 if (!exit_pending)
5420 set_bit(STATUS_EXIT_PENDING, &priv->status); 2056 set_bit(STATUS_EXIT_PENDING, &priv->status);
5421 2057
5422 iwl_leds_unregister(priv); 2058 iwl_leds_unregister(priv);
5423 2059
5424 iwlcore_low_level_notify(priv, IWLCORE_STOP_EVT); 2060 iwl_clear_stations_table(priv);
5425
5426 iwlcore_clear_stations_table(priv);
5427 2061
5428 /* Unblock any waiting calls */ 2062 /* Unblock any waiting calls */
5429 wake_up_interruptible_all(&priv->wait_command_queue); 2063 wake_up_interruptible_all(&priv->wait_command_queue);
@@ -5455,7 +2089,9 @@ static void __iwl4965_down(struct iwl_priv *priv)
5455 test_bit(STATUS_GEO_CONFIGURED, &priv->status) << 2089 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5456 STATUS_GEO_CONFIGURED | 2090 STATUS_GEO_CONFIGURED |
5457 test_bit(STATUS_IN_SUSPEND, &priv->status) << 2091 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5458 STATUS_IN_SUSPEND; 2092 STATUS_IN_SUSPEND |
2093 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2094 STATUS_EXIT_PENDING;
5459 goto exit; 2095 goto exit;
5460 } 2096 }
5461 2097
@@ -5470,15 +2106,17 @@ static void __iwl4965_down(struct iwl_priv *priv)
5470 test_bit(STATUS_IN_SUSPEND, &priv->status) << 2106 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5471 STATUS_IN_SUSPEND | 2107 STATUS_IN_SUSPEND |
5472 test_bit(STATUS_FW_ERROR, &priv->status) << 2108 test_bit(STATUS_FW_ERROR, &priv->status) <<
5473 STATUS_FW_ERROR; 2109 STATUS_FW_ERROR |
2110 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2111 STATUS_EXIT_PENDING;
5474 2112
5475 spin_lock_irqsave(&priv->lock, flags); 2113 spin_lock_irqsave(&priv->lock, flags);
5476 iwl_clear_bit(priv, CSR_GP_CNTRL, 2114 iwl_clear_bit(priv, CSR_GP_CNTRL,
5477 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2115 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
5478 spin_unlock_irqrestore(&priv->lock, flags); 2116 spin_unlock_irqrestore(&priv->lock, flags);
5479 2117
5480 iwl4965_hw_txq_ctx_stop(priv); 2118 iwl_txq_ctx_stop(priv);
5481 iwl4965_hw_rxq_stop(priv); 2119 iwl_rxq_stop(priv);
5482 2120
5483 spin_lock_irqsave(&priv->lock, flags); 2121 spin_lock_irqsave(&priv->lock, flags);
5484 if (!iwl_grab_nic_access(priv)) { 2122 if (!iwl_grab_nic_access(priv)) {
@@ -5490,19 +2128,19 @@ static void __iwl4965_down(struct iwl_priv *priv)
5490 2128
5491 udelay(5); 2129 udelay(5);
5492 2130
5493 iwl4965_hw_nic_stop_master(priv); 2131 /* FIXME: apm_ops.suspend(priv) */
5494 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 2132 priv->cfg->ops->lib->apm_ops.reset(priv);
5495 iwl4965_hw_nic_reset(priv); 2133 priv->cfg->ops->lib->free_shared_mem(priv);
5496 2134
5497 exit: 2135 exit:
5498 memset(&priv->card_alive, 0, sizeof(struct iwl4965_alive_resp)); 2136 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
5499 2137
5500 if (priv->ibss_beacon) 2138 if (priv->ibss_beacon)
5501 dev_kfree_skb(priv->ibss_beacon); 2139 dev_kfree_skb(priv->ibss_beacon);
5502 priv->ibss_beacon = NULL; 2140 priv->ibss_beacon = NULL;
5503 2141
5504 /* clear out any free frames */ 2142 /* clear out any free frames */
5505 iwl4965_clear_free_frames(priv); 2143 iwl_clear_free_frames(priv);
5506} 2144}
5507 2145
5508static void iwl4965_down(struct iwl_priv *priv) 2146static void iwl4965_down(struct iwl_priv *priv)
@@ -5511,7 +2149,7 @@ static void iwl4965_down(struct iwl_priv *priv)
5511 __iwl4965_down(priv); 2149 __iwl4965_down(priv);
5512 mutex_unlock(&priv->mutex); 2150 mutex_unlock(&priv->mutex);
5513 2151
5514 iwl4965_cancel_deferred_work(priv); 2152 iwl_cancel_deferred_work(priv);
5515} 2153}
5516 2154
5517#define MAX_HW_RESTARTS 5 2155#define MAX_HW_RESTARTS 5
@@ -5526,13 +2164,6 @@ static int __iwl4965_up(struct iwl_priv *priv)
5526 return -EIO; 2164 return -EIO;
5527 } 2165 }
5528 2166
5529 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5530 IWL_WARNING("Radio disabled by SW RF kill (module "
5531 "parameter)\n");
5532 iwl_rfkill_set_hw_state(priv);
5533 return -ENODEV;
5534 }
5535
5536 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { 2167 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
5537 IWL_ERROR("ucode not available for device bringup\n"); 2168 IWL_ERROR("ucode not available for device bringup\n");
5538 return -EIO; 2169 return -EIO;
@@ -5542,19 +2173,25 @@ static int __iwl4965_up(struct iwl_priv *priv)
5542 if (iwl_read32(priv, CSR_GP_CNTRL) & 2173 if (iwl_read32(priv, CSR_GP_CNTRL) &
5543 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 2174 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5544 clear_bit(STATUS_RF_KILL_HW, &priv->status); 2175 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5545 else { 2176 else
5546 set_bit(STATUS_RF_KILL_HW, &priv->status); 2177 set_bit(STATUS_RF_KILL_HW, &priv->status);
5547 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) { 2178
5548 iwl_rfkill_set_hw_state(priv); 2179 if (!test_bit(STATUS_IN_SUSPEND, &priv->status) &&
5549 IWL_WARNING("Radio disabled by HW RF Kill switch\n"); 2180 iwl_is_rfkill(priv)) {
5550 return -ENODEV; 2181 IWL_WARNING("Radio disabled by %s RF Kill switch\n",
5551 } 2182 test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW");
2183 return -ENODEV;
5552 } 2184 }
5553 2185
5554 iwl_rfkill_set_hw_state(priv);
5555 iwl_write32(priv, CSR_INT, 0xFFFFFFFF); 2186 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5556 2187
5557 ret = priv->cfg->ops->lib->hw_nic_init(priv); 2188 ret = priv->cfg->ops->lib->alloc_shared_mem(priv);
2189 if (ret) {
2190 IWL_ERROR("Unable to allocate shared memory\n");
2191 return ret;
2192 }
2193
2194 ret = iwl_hw_nic_init(priv);
5558 if (ret) { 2195 if (ret) {
5559 IWL_ERROR("Unable to init nic\n"); 2196 IWL_ERROR("Unable to init nic\n");
5560 return ret; 2197 return ret;
@@ -5580,12 +2217,13 @@ static int __iwl4965_up(struct iwl_priv *priv)
5580 priv->ucode_data.len); 2217 priv->ucode_data.len);
5581 2218
5582 /* We return success when we resume from suspend and rf_kill is on. */ 2219 /* We return success when we resume from suspend and rf_kill is on. */
5583 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) 2220 if (test_bit(STATUS_RF_KILL_HW, &priv->status) ||
2221 test_bit(STATUS_RF_KILL_SW, &priv->status))
5584 return 0; 2222 return 0;
5585 2223
5586 for (i = 0; i < MAX_HW_RESTARTS; i++) { 2224 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5587 2225
5588 iwlcore_clear_stations_table(priv); 2226 iwl_clear_stations_table(priv);
5589 2227
5590 /* load bootstrap state machine, 2228 /* load bootstrap state machine,
5591 * load bootstrap program into processor's memory, 2229 * load bootstrap program into processor's memory,
@@ -5597,6 +2235,9 @@ static int __iwl4965_up(struct iwl_priv *priv)
5597 continue; 2235 continue;
5598 } 2236 }
5599 2237
2238 /* Clear out the uCode error bit if it is set */
2239 clear_bit(STATUS_FW_ERROR, &priv->status);
2240
5600 /* start card; "initialize" will load runtime ucode */ 2241 /* start card; "initialize" will load runtime ucode */
5601 iwl4965_nic_start(priv); 2242 iwl4965_nic_start(priv);
5602 2243
@@ -5607,6 +2248,7 @@ static int __iwl4965_up(struct iwl_priv *priv)
5607 2248
5608 set_bit(STATUS_EXIT_PENDING, &priv->status); 2249 set_bit(STATUS_EXIT_PENDING, &priv->status);
5609 __iwl4965_down(priv); 2250 __iwl4965_down(priv);
2251 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5610 2252
5611 /* tried to restart and config the device for as long as our 2253 /* tried to restart and config the device for as long as our
5612 * patience could withstand */ 2254 * patience could withstand */
@@ -5621,7 +2263,7 @@ static int __iwl4965_up(struct iwl_priv *priv)
5621 * 2263 *
5622 *****************************************************************************/ 2264 *****************************************************************************/
5623 2265
5624static void iwl4965_bg_init_alive_start(struct work_struct *data) 2266static void iwl_bg_init_alive_start(struct work_struct *data)
5625{ 2267{
5626 struct iwl_priv *priv = 2268 struct iwl_priv *priv =
5627 container_of(data, struct iwl_priv, init_alive_start.work); 2269 container_of(data, struct iwl_priv, init_alive_start.work);
@@ -5630,11 +2272,11 @@ static void iwl4965_bg_init_alive_start(struct work_struct *data)
5630 return; 2272 return;
5631 2273
5632 mutex_lock(&priv->mutex); 2274 mutex_lock(&priv->mutex);
5633 iwl4965_init_alive_start(priv); 2275 priv->cfg->ops->lib->init_alive_start(priv);
5634 mutex_unlock(&priv->mutex); 2276 mutex_unlock(&priv->mutex);
5635} 2277}
5636 2278
5637static void iwl4965_bg_alive_start(struct work_struct *data) 2279static void iwl_bg_alive_start(struct work_struct *data)
5638{ 2280{
5639 struct iwl_priv *priv = 2281 struct iwl_priv *priv =
5640 container_of(data, struct iwl_priv, alive_start.work); 2282 container_of(data, struct iwl_priv, alive_start.work);
@@ -5643,7 +2285,7 @@ static void iwl4965_bg_alive_start(struct work_struct *data)
5643 return; 2285 return;
5644 2286
5645 mutex_lock(&priv->mutex); 2287 mutex_lock(&priv->mutex);
5646 iwl4965_alive_start(priv); 2288 iwl_alive_start(priv);
5647 mutex_unlock(&priv->mutex); 2289 mutex_unlock(&priv->mutex);
5648} 2290}
5649 2291
@@ -5659,7 +2301,7 @@ static void iwl4965_bg_rf_kill(struct work_struct *work)
5659 mutex_lock(&priv->mutex); 2301 mutex_lock(&priv->mutex);
5660 2302
5661 if (!iwl_is_rfkill(priv)) { 2303 if (!iwl_is_rfkill(priv)) {
5662 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL, 2304 IWL_DEBUG(IWL_DL_RF_KILL,
5663 "HW and/or SW RF Kill no longer active, restarting " 2305 "HW and/or SW RF Kill no longer active, restarting "
5664 "device\n"); 2306 "device\n");
5665 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) 2307 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
@@ -5677,239 +2319,53 @@ static void iwl4965_bg_rf_kill(struct work_struct *work)
5677 "Kill switch must be turned off for " 2319 "Kill switch must be turned off for "
5678 "wireless networking to work.\n"); 2320 "wireless networking to work.\n");
5679 } 2321 }
5680 iwl_rfkill_set_hw_state(priv);
5681
5682 mutex_unlock(&priv->mutex); 2322 mutex_unlock(&priv->mutex);
2323 iwl_rfkill_set_hw_state(priv);
5683} 2324}
5684 2325
5685#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) 2326static void iwl4965_bg_set_monitor(struct work_struct *work)
5686
5687static void iwl4965_bg_scan_check(struct work_struct *data)
5688{ 2327{
5689 struct iwl_priv *priv = 2328 struct iwl_priv *priv = container_of(work,
5690 container_of(data, struct iwl_priv, scan_check.work); 2329 struct iwl_priv, set_monitor);
2330 int ret;
5691 2331
5692 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 2332 IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
5693 return;
5694 2333
5695 mutex_lock(&priv->mutex); 2334 mutex_lock(&priv->mutex);
5696 if (test_bit(STATUS_SCANNING, &priv->status) ||
5697 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
5698 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
5699 "Scan completion watchdog resetting adapter (%dms)\n",
5700 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
5701 2335
5702 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) 2336 ret = iwl4965_set_mode(priv, IEEE80211_IF_TYPE_MNTR);
5703 iwl4965_send_scan_abort(priv); 2337
2338 if (ret) {
2339 if (ret == -EAGAIN)
2340 IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
2341 else
2342 IWL_ERROR("iwl4965_set_mode() failed ret = %d\n", ret);
5704 } 2343 }
2344
5705 mutex_unlock(&priv->mutex); 2345 mutex_unlock(&priv->mutex);
5706} 2346}
5707 2347
5708static void iwl4965_bg_request_scan(struct work_struct *data) 2348static void iwl_bg_run_time_calib_work(struct work_struct *work)
5709{ 2349{
5710 struct iwl_priv *priv = 2350 struct iwl_priv *priv = container_of(work, struct iwl_priv,
5711 container_of(data, struct iwl_priv, request_scan); 2351 run_time_calib_work);
5712 struct iwl_host_cmd cmd = {
5713 .id = REPLY_SCAN_CMD,
5714 .len = sizeof(struct iwl4965_scan_cmd),
5715 .meta.flags = CMD_SIZE_HUGE,
5716 };
5717 struct iwl4965_scan_cmd *scan;
5718 struct ieee80211_conf *conf = NULL;
5719 u16 cmd_len;
5720 enum ieee80211_band band;
5721 u8 direct_mask;
5722 int ret = 0;
5723
5724 conf = ieee80211_get_hw_conf(priv->hw);
5725 2352
5726 mutex_lock(&priv->mutex); 2353 mutex_lock(&priv->mutex);
5727 2354
5728 if (!iwl_is_ready(priv)) { 2355 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
5729 IWL_WARNING("request scan called when driver not ready.\n"); 2356 test_bit(STATUS_SCANNING, &priv->status)) {
5730 goto done; 2357 mutex_unlock(&priv->mutex);
5731 } 2358 return;
5732
5733 /* Make sure the scan wasn't cancelled before this queued work
5734 * was given the chance to run... */
5735 if (!test_bit(STATUS_SCANNING, &priv->status))
5736 goto done;
5737
5738 /* This should never be called or scheduled if there is currently
5739 * a scan active in the hardware. */
5740 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
5741 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
5742 "Ignoring second request.\n");
5743 ret = -EIO;
5744 goto done;
5745 }
5746
5747 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5748 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
5749 goto done;
5750 }
5751
5752 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
5753 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
5754 goto done;
5755 }
5756
5757 if (iwl_is_rfkill(priv)) {
5758 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
5759 goto done;
5760 }
5761
5762 if (!test_bit(STATUS_READY, &priv->status)) {
5763 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
5764 goto done;
5765 }
5766
5767 if (!priv->scan_bands) {
5768 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
5769 goto done;
5770 }
5771
5772 if (!priv->scan) {
5773 priv->scan = kmalloc(sizeof(struct iwl4965_scan_cmd) +
5774 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
5775 if (!priv->scan) {
5776 ret = -ENOMEM;
5777 goto done;
5778 }
5779 } 2359 }
5780 scan = priv->scan;
5781 memset(scan, 0, sizeof(struct iwl4965_scan_cmd) + IWL_MAX_SCAN_SIZE);
5782 2360
5783 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; 2361 if (priv->start_calib) {
5784 scan->quiet_time = IWL_ACTIVE_QUIET_TIME; 2362 iwl_chain_noise_calibration(priv, &priv->statistics);
5785 2363
5786 if (iwl_is_associated(priv)) { 2364 iwl_sensitivity_calibration(priv, &priv->statistics);
5787 u16 interval = 0;
5788 u32 extra;
5789 u32 suspend_time = 100;
5790 u32 scan_suspend_time = 100;
5791 unsigned long flags;
5792
5793 IWL_DEBUG_INFO("Scanning while associated...\n");
5794
5795 spin_lock_irqsave(&priv->lock, flags);
5796 interval = priv->beacon_int;
5797 spin_unlock_irqrestore(&priv->lock, flags);
5798
5799 scan->suspend_time = 0;
5800 scan->max_out_time = cpu_to_le32(200 * 1024);
5801 if (!interval)
5802 interval = suspend_time;
5803
5804 extra = (suspend_time / interval) << 22;
5805 scan_suspend_time = (extra |
5806 ((suspend_time % interval) * 1024));
5807 scan->suspend_time = cpu_to_le32(scan_suspend_time);
5808 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
5809 scan_suspend_time, interval);
5810 }
5811
5812 /* We should add the ability for user to lock to PASSIVE ONLY */
5813 if (priv->one_direct_scan) {
5814 IWL_DEBUG_SCAN
5815 ("Kicking off one direct scan for '%s'\n",
5816 iwl4965_escape_essid(priv->direct_ssid,
5817 priv->direct_ssid_len));
5818 scan->direct_scan[0].id = WLAN_EID_SSID;
5819 scan->direct_scan[0].len = priv->direct_ssid_len;
5820 memcpy(scan->direct_scan[0].ssid,
5821 priv->direct_ssid, priv->direct_ssid_len);
5822 direct_mask = 1;
5823 } else if (!iwl_is_associated(priv) && priv->essid_len) {
5824 IWL_DEBUG_SCAN
5825 ("Kicking off one direct scan for '%s' when not associated\n",
5826 iwl4965_escape_essid(priv->essid, priv->essid_len));
5827 scan->direct_scan[0].id = WLAN_EID_SSID;
5828 scan->direct_scan[0].len = priv->essid_len;
5829 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
5830 direct_mask = 1;
5831 } else {
5832 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
5833 direct_mask = 0;
5834 } 2365 }
5835 2366
5836 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
5837 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
5838 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
5839
5840
5841 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
5842 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
5843 scan->tx_cmd.rate_n_flags =
5844 iwl4965_hw_set_rate_n_flags(IWL_RATE_1M_PLCP,
5845 RATE_MCS_ANT_B_MSK|RATE_MCS_CCK_MSK);
5846
5847 scan->good_CRC_th = 0;
5848 band = IEEE80211_BAND_2GHZ;
5849 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
5850 scan->tx_cmd.rate_n_flags =
5851 iwl4965_hw_set_rate_n_flags(IWL_RATE_6M_PLCP,
5852 RATE_MCS_ANT_B_MSK);
5853 scan->good_CRC_th = IWL_GOOD_CRC_TH;
5854 band = IEEE80211_BAND_5GHZ;
5855 } else {
5856 IWL_WARNING("Invalid scan band count\n");
5857 goto done;
5858 }
5859
5860 /* We don't build a direct scan probe request; the uCode will do
5861 * that based on the direct_mask added to each channel entry */
5862 cmd_len = iwl4965_fill_probe_req(priv, band,
5863 (struct ieee80211_mgmt *)scan->data,
5864 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0);
5865
5866 scan->tx_cmd.len = cpu_to_le16(cmd_len);
5867 /* select Rx chains */
5868
5869 /* Force use of chains B and C (0x6) for scan Rx.
5870 * Avoid A (0x1) because of its off-channel reception on A-band.
5871 * MIMO is not used here, but value is required to make uCode happy. */
5872 scan->rx_chain = RXON_RX_CHAIN_DRIVER_FORCE_MSK |
5873 cpu_to_le16((0x7 << RXON_RX_CHAIN_VALID_POS) |
5874 (0x6 << RXON_RX_CHAIN_FORCE_SEL_POS) |
5875 (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS));
5876
5877 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
5878 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
5879
5880 if (direct_mask)
5881 scan->channel_count =
5882 iwl4965_get_channels_for_scan(
5883 priv, band, 1, /* active */
5884 direct_mask,
5885 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
5886 else
5887 scan->channel_count =
5888 iwl4965_get_channels_for_scan(
5889 priv, band, 0, /* passive */
5890 direct_mask,
5891 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
5892
5893 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
5894 scan->channel_count * sizeof(struct iwl4965_scan_channel);
5895 cmd.data = scan;
5896 scan->len = cpu_to_le16(cmd.len);
5897
5898 set_bit(STATUS_SCAN_HW, &priv->status);
5899 ret = iwl_send_cmd_sync(priv, &cmd);
5900 if (ret)
5901 goto done;
5902
5903 queue_delayed_work(priv->workqueue, &priv->scan_check,
5904 IWL_SCAN_CHECK_WATCHDOG);
5905
5906 mutex_unlock(&priv->mutex); 2367 mutex_unlock(&priv->mutex);
5907 return; 2368 return;
5908
5909 done:
5910 /* inform mac80211 scan aborted */
5911 queue_work(priv->workqueue, &priv->scan_completed);
5912 mutex_unlock(&priv->mutex);
5913} 2369}
5914 2370
5915static void iwl4965_bg_up(struct work_struct *data) 2371static void iwl4965_bg_up(struct work_struct *data)
@@ -5922,6 +2378,7 @@ static void iwl4965_bg_up(struct work_struct *data)
5922 mutex_lock(&priv->mutex); 2378 mutex_lock(&priv->mutex);
5923 __iwl4965_up(priv); 2379 __iwl4965_up(priv);
5924 mutex_unlock(&priv->mutex); 2380 mutex_unlock(&priv->mutex);
2381 iwl_rfkill_set_hw_state(priv);
5925} 2382}
5926 2383
5927static void iwl4965_bg_restart(struct work_struct *data) 2384static void iwl4965_bg_restart(struct work_struct *data)
@@ -5944,7 +2401,7 @@ static void iwl4965_bg_rx_replenish(struct work_struct *data)
5944 return; 2401 return;
5945 2402
5946 mutex_lock(&priv->mutex); 2403 mutex_lock(&priv->mutex);
5947 iwl4965_rx_replenish(priv); 2404 iwl_rx_replenish(priv);
5948 mutex_unlock(&priv->mutex); 2405 mutex_unlock(&priv->mutex);
5949} 2406}
5950 2407
@@ -5955,6 +2412,7 @@ static void iwl4965_post_associate(struct iwl_priv *priv)
5955 struct ieee80211_conf *conf = NULL; 2412 struct ieee80211_conf *conf = NULL;
5956 int ret = 0; 2413 int ret = 0;
5957 DECLARE_MAC_BUF(mac); 2414 DECLARE_MAC_BUF(mac);
2415 unsigned long flags;
5958 2416
5959 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { 2417 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
5960 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__); 2418 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
@@ -5973,7 +2431,7 @@ static void iwl4965_post_associate(struct iwl_priv *priv)
5973 if (!priv->vif || !priv->is_open) 2431 if (!priv->vif || !priv->is_open)
5974 return; 2432 return;
5975 2433
5976 iwl4965_scan_cancel_timeout(priv, 200); 2434 iwl_scan_cancel_timeout(priv, 200);
5977 2435
5978 conf = ieee80211_get_hw_conf(priv->hw); 2436 conf = ieee80211_get_hw_conf(priv->hw);
5979 2437
@@ -5990,11 +2448,10 @@ static void iwl4965_post_associate(struct iwl_priv *priv)
5990 2448
5991 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; 2449 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
5992 2450
5993#ifdef CONFIG_IWL4965_HT
5994 if (priv->current_ht_config.is_ht) 2451 if (priv->current_ht_config.is_ht)
5995 iwl4965_set_rxon_ht(priv, &priv->current_ht_config); 2452 iwl_set_rxon_ht(priv, &priv->current_ht_config);
5996#endif /* CONFIG_IWL4965_HT*/ 2453
5997 iwl4965_set_rxon_chain(priv); 2454 iwl_set_rxon_chain(priv);
5998 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); 2455 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
5999 2456
6000 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n", 2457 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
@@ -6020,17 +2477,14 @@ static void iwl4965_post_associate(struct iwl_priv *priv)
6020 2477
6021 switch (priv->iw_mode) { 2478 switch (priv->iw_mode) {
6022 case IEEE80211_IF_TYPE_STA: 2479 case IEEE80211_IF_TYPE_STA:
6023 iwl4965_rate_scale_init(priv->hw, IWL_AP_ID);
6024 break; 2480 break;
6025 2481
6026 case IEEE80211_IF_TYPE_IBSS: 2482 case IEEE80211_IF_TYPE_IBSS:
6027 2483
6028 /* clear out the station table */ 2484 /* assume default assoc id */
6029 iwlcore_clear_stations_table(priv); 2485 priv->assoc_id = 1;
6030 2486
6031 iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0); 2487 iwl_rxon_add_station(priv, priv->bssid, 0);
6032 iwl4965_rxon_add_station(priv, priv->bssid, 0);
6033 iwl4965_rate_scale_init(priv->hw, IWL_STA_ID);
6034 iwl4965_send_beacon_cmd(priv); 2488 iwl4965_send_beacon_cmd(priv);
6035 2489
6036 break; 2490 break;
@@ -6041,58 +2495,30 @@ static void iwl4965_post_associate(struct iwl_priv *priv)
6041 break; 2495 break;
6042 } 2496 }
6043 2497
6044 iwl4965_sequence_reset(priv);
6045
6046#ifdef CONFIG_IWL4965_SENSITIVITY
6047 /* Enable Rx differential gain and sensitivity calibrations */ 2498 /* Enable Rx differential gain and sensitivity calibrations */
6048 iwl4965_chain_noise_reset(priv); 2499 iwl_chain_noise_reset(priv);
6049 priv->start_calib = 1; 2500 priv->start_calib = 1;
6050#endif /* CONFIG_IWL4965_SENSITIVITY */
6051 2501
6052 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) 2502 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6053 priv->assoc_station_added = 1; 2503 priv->assoc_station_added = 1;
6054 2504
6055 iwl4965_activate_qos(priv, 0); 2505 spin_lock_irqsave(&priv->lock, flags);
2506 iwl_activate_qos(priv, 0);
2507 spin_unlock_irqrestore(&priv->lock, flags);
6056 2508
2509 iwl_power_update_mode(priv, 0);
6057 /* we have just associated, don't start scan too early */ 2510 /* we have just associated, don't start scan too early */
6058 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; 2511 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
6059} 2512}
6060 2513
6061
6062static void iwl4965_bg_post_associate(struct work_struct *data)
6063{
6064 struct iwl_priv *priv = container_of(data, struct iwl_priv,
6065 post_associate.work);
6066
6067 mutex_lock(&priv->mutex);
6068 iwl4965_post_associate(priv);
6069 mutex_unlock(&priv->mutex);
6070
6071}
6072
6073static void iwl4965_bg_abort_scan(struct work_struct *work)
6074{
6075 struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
6076
6077 if (!iwl_is_ready(priv))
6078 return;
6079
6080 mutex_lock(&priv->mutex);
6081
6082 set_bit(STATUS_SCAN_ABORTING, &priv->status);
6083 iwl4965_send_scan_abort(priv);
6084
6085 mutex_unlock(&priv->mutex);
6086}
6087
6088static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf); 2514static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
6089 2515
6090static void iwl4965_bg_scan_completed(struct work_struct *work) 2516static void iwl_bg_scan_completed(struct work_struct *work)
6091{ 2517{
6092 struct iwl_priv *priv = 2518 struct iwl_priv *priv =
6093 container_of(work, struct iwl_priv, scan_completed); 2519 container_of(work, struct iwl_priv, scan_completed);
6094 2520
6095 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n"); 2521 IWL_DEBUG_SCAN("SCAN complete scan\n");
6096 2522
6097 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 2523 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6098 return; 2524 return;
@@ -6105,7 +2531,7 @@ static void iwl4965_bg_scan_completed(struct work_struct *work)
6105 /* Since setting the TXPOWER may have been deferred while 2531 /* Since setting the TXPOWER may have been deferred while
6106 * performing the scan, fire one off */ 2532 * performing the scan, fire one off */
6107 mutex_lock(&priv->mutex); 2533 mutex_lock(&priv->mutex);
6108 iwl4965_hw_reg_send_txpower(priv); 2534 iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
6109 mutex_unlock(&priv->mutex); 2535 mutex_unlock(&priv->mutex);
6110} 2536}
6111 2537
@@ -6115,7 +2541,7 @@ static void iwl4965_bg_scan_completed(struct work_struct *work)
6115 * 2541 *
6116 *****************************************************************************/ 2542 *****************************************************************************/
6117 2543
6118#define UCODE_READY_TIMEOUT (2 * HZ) 2544#define UCODE_READY_TIMEOUT (4 * HZ)
6119 2545
6120static int iwl4965_mac_start(struct ieee80211_hw *hw) 2546static int iwl4965_mac_start(struct ieee80211_hw *hw)
6121{ 2547{
@@ -6141,7 +2567,7 @@ static int iwl4965_mac_start(struct ieee80211_hw *hw)
6141 /* we should be verifying the device is ready to be opened */ 2567 /* we should be verifying the device is ready to be opened */
6142 mutex_lock(&priv->mutex); 2568 mutex_lock(&priv->mutex);
6143 2569
6144 memset(&priv->staging_rxon, 0, sizeof(struct iwl4965_rxon_cmd)); 2570 memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd));
6145 /* fetch ucode file from disk, alloc and copy to bus-master buffers ... 2571 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6146 * ucode filename and max sizes are card-specific. */ 2572 * ucode filename and max sizes are card-specific. */
6147 2573
@@ -6158,6 +2584,8 @@ static int iwl4965_mac_start(struct ieee80211_hw *hw)
6158 2584
6159 mutex_unlock(&priv->mutex); 2585 mutex_unlock(&priv->mutex);
6160 2586
2587 iwl_rfkill_set_hw_state(priv);
2588
6161 if (ret) 2589 if (ret)
6162 goto out_release_irq; 2590 goto out_release_irq;
6163 2591
@@ -6166,15 +2594,15 @@ static int iwl4965_mac_start(struct ieee80211_hw *hw)
6166 if (test_bit(STATUS_IN_SUSPEND, &priv->status)) 2594 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6167 return 0; 2595 return 0;
6168 2596
6169 /* Wait for START_ALIVE from ucode. Otherwise callbacks from 2597 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
6170 * mac80211 will not be run successfully. */ 2598 * mac80211 will not be run successfully. */
6171 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 2599 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6172 test_bit(STATUS_READY, &priv->status), 2600 test_bit(STATUS_READY, &priv->status),
6173 UCODE_READY_TIMEOUT); 2601 UCODE_READY_TIMEOUT);
6174 if (!ret) { 2602 if (!ret) {
6175 if (!test_bit(STATUS_READY, &priv->status)) { 2603 if (!test_bit(STATUS_READY, &priv->status)) {
6176 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n", 2604 IWL_ERROR("START_ALIVE timeout after %dms.\n",
6177 jiffies_to_msecs(UCODE_READY_TIMEOUT)); 2605 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6178 ret = -ETIMEDOUT; 2606 ret = -ETIMEDOUT;
6179 goto out_release_irq; 2607 goto out_release_irq;
6180 } 2608 }
@@ -6212,8 +2640,7 @@ static void iwl4965_mac_stop(struct ieee80211_hw *hw)
6212 * RXON_FILTER_ASSOC_MSK BIT 2640 * RXON_FILTER_ASSOC_MSK BIT
6213 */ 2641 */
6214 mutex_lock(&priv->mutex); 2642 mutex_lock(&priv->mutex);
6215 iwl4965_scan_cancel_timeout(priv, 100); 2643 iwl_scan_cancel_timeout(priv, 100);
6216 cancel_delayed_work(&priv->post_associate);
6217 mutex_unlock(&priv->mutex); 2644 mutex_unlock(&priv->mutex);
6218 } 2645 }
6219 2646
@@ -6228,8 +2655,7 @@ static void iwl4965_mac_stop(struct ieee80211_hw *hw)
6228 IWL_DEBUG_MAC80211("leave\n"); 2655 IWL_DEBUG_MAC80211("leave\n");
6229} 2656}
6230 2657
6231static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb, 2658static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
6232 struct ieee80211_tx_control *ctl)
6233{ 2659{
6234 struct iwl_priv *priv = hw->priv; 2660 struct iwl_priv *priv = hw->priv;
6235 2661
@@ -6242,9 +2668,9 @@ static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
6242 } 2668 }
6243 2669
6244 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, 2670 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
6245 ctl->tx_rate->bitrate); 2671 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
6246 2672
6247 if (iwl4965_tx_skb(priv, skb, ctl)) 2673 if (iwl_tx_skb(priv, skb))
6248 dev_kfree_skb_any(skb); 2674 dev_kfree_skb_any(skb);
6249 2675
6250 IWL_DEBUG_MAC80211("leave\n"); 2676 IWL_DEBUG_MAC80211("leave\n");
@@ -6277,8 +2703,9 @@ static int iwl4965_mac_add_interface(struct ieee80211_hw *hw,
6277 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); 2703 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6278 } 2704 }
6279 2705
6280 if (iwl_is_ready(priv)) 2706 if (iwl4965_set_mode(priv, conf->type) == -EAGAIN)
6281 iwl4965_set_mode(priv, conf->type); 2707 /* we are not ready, will run again when ready */
2708 set_bit(STATUS_MODE_PENDING, &priv->status);
6282 2709
6283 mutex_unlock(&priv->mutex); 2710 mutex_unlock(&priv->mutex);
6284 2711
@@ -6299,12 +2726,21 @@ static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *co
6299 const struct iwl_channel_info *ch_info; 2726 const struct iwl_channel_info *ch_info;
6300 unsigned long flags; 2727 unsigned long flags;
6301 int ret = 0; 2728 int ret = 0;
2729 u16 channel;
6302 2730
6303 mutex_lock(&priv->mutex); 2731 mutex_lock(&priv->mutex);
6304 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value); 2732 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
6305 2733
6306 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP); 2734 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
6307 2735
2736 if (conf->radio_enabled && iwl_radio_kill_sw_enable_radio(priv)) {
2737 IWL_DEBUG_MAC80211("leave - RF-KILL - waiting for uCode\n");
2738 goto out;
2739 }
2740
2741 if (!conf->radio_enabled)
2742 iwl_radio_kill_sw_disable_radio(priv);
2743
6308 if (!iwl_is_ready(priv)) { 2744 if (!iwl_is_ready(priv)) {
6309 IWL_DEBUG_MAC80211("leave - not ready\n"); 2745 IWL_DEBUG_MAC80211("leave - not ready\n");
6310 ret = -EIO; 2746 ret = -EIO;
@@ -6319,33 +2755,37 @@ static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *co
6319 return 0; 2755 return 0;
6320 } 2756 }
6321 2757
6322 spin_lock_irqsave(&priv->lock, flags); 2758 channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
6323 2759 ch_info = iwl_get_channel_info(priv, conf->channel->band, channel);
6324 ch_info = iwl_get_channel_info(priv, conf->channel->band,
6325 ieee80211_frequency_to_channel(conf->channel->center_freq));
6326 if (!is_channel_valid(ch_info)) { 2760 if (!is_channel_valid(ch_info)) {
6327 IWL_DEBUG_MAC80211("leave - invalid channel\n"); 2761 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6328 spin_unlock_irqrestore(&priv->lock, flags);
6329 ret = -EINVAL; 2762 ret = -EINVAL;
6330 goto out; 2763 goto out;
6331 } 2764 }
6332 2765
6333#ifdef CONFIG_IWL4965_HT 2766 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
2767 !is_channel_ibss(ch_info)) {
2768 IWL_ERROR("channel %d in band %d not IBSS channel\n",
2769 conf->channel->hw_value, conf->channel->band);
2770 ret = -EINVAL;
2771 goto out;
2772 }
2773
2774 spin_lock_irqsave(&priv->lock, flags);
2775
6334 /* if we are switching from ht to 2.4 clear flags 2776 /* if we are switching from ht to 2.4 clear flags
6335 * from any ht related info since 2.4 does not 2777 * from any ht related info since 2.4 does not
6336 * support ht */ 2778 * support ht */
6337 if ((le16_to_cpu(priv->staging_rxon.channel) != conf->channel->hw_value) 2779 if ((le16_to_cpu(priv->staging_rxon.channel) != channel)
6338#ifdef IEEE80211_CONF_CHANNEL_SWITCH 2780#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6339 && !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) 2781 && !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH)
6340#endif 2782#endif
6341 ) 2783 )
6342 priv->staging_rxon.flags = 0; 2784 priv->staging_rxon.flags = 0;
6343#endif /* CONFIG_IWL4965_HT */
6344 2785
6345 iwlcore_set_rxon_channel(priv, conf->channel->band, 2786 iwl_set_rxon_channel(priv, conf->channel->band, channel);
6346 ieee80211_frequency_to_channel(conf->channel->center_freq));
6347 2787
6348 iwl4965_set_flags_for_phymode(priv, conf->channel->band); 2788 iwl_set_flags_for_band(priv, conf->channel->band);
6349 2789
6350 /* The list of supported rates and rate mask can be different 2790 /* The list of supported rates and rate mask can be different
6351 * for each band; since the band may have changed, reset 2791 * for each band; since the band may have changed, reset
@@ -6361,9 +2801,6 @@ static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *co
6361 } 2801 }
6362#endif 2802#endif
6363 2803
6364 if (priv->cfg->ops->lib->radio_kill_sw)
6365 priv->cfg->ops->lib->radio_kill_sw(priv, !conf->radio_enabled);
6366
6367 if (!conf->radio_enabled) { 2804 if (!conf->radio_enabled) {
6368 IWL_DEBUG_MAC80211("leave - radio disabled\n"); 2805 IWL_DEBUG_MAC80211("leave - radio disabled\n");
6369 goto out; 2806 goto out;
@@ -6375,6 +2812,11 @@ static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *co
6375 goto out; 2812 goto out;
6376 } 2813 }
6377 2814
2815 IWL_DEBUG_MAC80211("TX Power old=%d new=%d\n",
2816 priv->tx_power_user_lmt, conf->power_level);
2817
2818 iwl_set_tx_power(priv, conf->power_level, false);
2819
6378 iwl4965_set_rate(priv); 2820 iwl4965_set_rate(priv);
6379 2821
6380 if (memcmp(&priv->active_rxon, 2822 if (memcmp(&priv->active_rxon,
@@ -6394,12 +2836,13 @@ out:
6394static void iwl4965_config_ap(struct iwl_priv *priv) 2836static void iwl4965_config_ap(struct iwl_priv *priv)
6395{ 2837{
6396 int ret = 0; 2838 int ret = 0;
2839 unsigned long flags;
6397 2840
6398 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 2841 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6399 return; 2842 return;
6400 2843
6401 /* The following should be done only at AP bring up */ 2844 /* The following should be done only at AP bring up */
6402 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) { 2845 if (!(iwl_is_associated(priv))) {
6403 2846
6404 /* RXON - unassoc (to set timing command) */ 2847 /* RXON - unassoc (to set timing command) */
6405 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; 2848 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
@@ -6414,7 +2857,7 @@ static void iwl4965_config_ap(struct iwl_priv *priv)
6414 IWL_WARNING("REPLY_RXON_TIMING failed - " 2857 IWL_WARNING("REPLY_RXON_TIMING failed - "
6415 "Attempting to continue.\n"); 2858 "Attempting to continue.\n");
6416 2859
6417 iwl4965_set_rxon_chain(priv); 2860 iwl_set_rxon_chain(priv);
6418 2861
6419 /* FIXME: what should be the assoc_id for AP? */ 2862 /* FIXME: what should be the assoc_id for AP? */
6420 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); 2863 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
@@ -6441,8 +2884,10 @@ static void iwl4965_config_ap(struct iwl_priv *priv)
6441 /* restore RXON assoc */ 2884 /* restore RXON assoc */
6442 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; 2885 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6443 iwl4965_commit_rxon(priv); 2886 iwl4965_commit_rxon(priv);
6444 iwl4965_activate_qos(priv, 1); 2887 spin_lock_irqsave(&priv->lock, flags);
6445 iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0); 2888 iwl_activate_qos(priv, 1);
2889 spin_unlock_irqrestore(&priv->lock, flags);
2890 iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
6446 } 2891 }
6447 iwl4965_send_beacon_cmd(priv); 2892 iwl4965_send_beacon_cmd(priv);
6448 2893
@@ -6451,6 +2896,9 @@ static void iwl4965_config_ap(struct iwl_priv *priv)
6451 * clear sta table, add BCAST sta... */ 2896 * clear sta table, add BCAST sta... */
6452} 2897}
6453 2898
2899/* temporary */
2900static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb);
2901
6454static int iwl4965_mac_config_interface(struct ieee80211_hw *hw, 2902static int iwl4965_mac_config_interface(struct ieee80211_hw *hw,
6455 struct ieee80211_vif *vif, 2903 struct ieee80211_vif *vif,
6456 struct ieee80211_if_conf *conf) 2904 struct ieee80211_if_conf *conf)
@@ -6468,8 +2916,18 @@ static int iwl4965_mac_config_interface(struct ieee80211_hw *hw,
6468 return 0; 2916 return 0;
6469 } 2917 }
6470 2918
2919 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
2920 conf->changed & IEEE80211_IFCC_BEACON) {
2921 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2922 if (!beacon)
2923 return -ENOMEM;
2924 rc = iwl4965_mac_beacon_update(hw, beacon);
2925 if (rc)
2926 return rc;
2927 }
2928
6471 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && 2929 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
6472 (!conf->beacon || !conf->ssid_len)) { 2930 (!conf->ssid_len)) {
6473 IWL_DEBUG_MAC80211 2931 IWL_DEBUG_MAC80211
6474 ("Leaving in AP mode because HostAPD is not ready.\n"); 2932 ("Leaving in AP mode because HostAPD is not ready.\n");
6475 return 0; 2933 return 0;
@@ -6501,7 +2959,7 @@ static int iwl4965_mac_config_interface(struct ieee80211_hw *hw,
6501 if (priv->ibss_beacon) 2959 if (priv->ibss_beacon)
6502 dev_kfree_skb(priv->ibss_beacon); 2960 dev_kfree_skb(priv->ibss_beacon);
6503 2961
6504 priv->ibss_beacon = conf->beacon; 2962 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
6505 } 2963 }
6506 2964
6507 if (iwl_is_rfkill(priv)) 2965 if (iwl_is_rfkill(priv))
@@ -6511,7 +2969,7 @@ static int iwl4965_mac_config_interface(struct ieee80211_hw *hw,
6511 !is_multicast_ether_addr(conf->bssid)) { 2969 !is_multicast_ether_addr(conf->bssid)) {
6512 /* If there is currently a HW scan going on in the background 2970 /* If there is currently a HW scan going on in the background
6513 * then we need to cancel it else the RXON below will fail. */ 2971 * then we need to cancel it else the RXON below will fail. */
6514 if (iwl4965_scan_cancel_timeout(priv, 100)) { 2972 if (iwl_scan_cancel_timeout(priv, 100)) {
6515 IWL_WARNING("Aborted scan still in progress " 2973 IWL_WARNING("Aborted scan still in progress "
6516 "after 100ms\n"); 2974 "after 100ms\n");
6517 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); 2975 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
@@ -6531,12 +2989,12 @@ static int iwl4965_mac_config_interface(struct ieee80211_hw *hw,
6531 else { 2989 else {
6532 rc = iwl4965_commit_rxon(priv); 2990 rc = iwl4965_commit_rxon(priv);
6533 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc) 2991 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
6534 iwl4965_rxon_add_station( 2992 iwl_rxon_add_station(
6535 priv, priv->active_rxon.bssid_addr, 1); 2993 priv, priv->active_rxon.bssid_addr, 1);
6536 } 2994 }
6537 2995
6538 } else { 2996 } else {
6539 iwl4965_scan_cancel_timeout(priv, 100); 2997 iwl_scan_cancel_timeout(priv, 100);
6540 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; 2998 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6541 iwl4965_commit_rxon(priv); 2999 iwl4965_commit_rxon(priv);
6542 } 3000 }
@@ -6562,11 +3020,18 @@ static void iwl4965_configure_filter(struct ieee80211_hw *hw,
6562 unsigned int *total_flags, 3020 unsigned int *total_flags,
6563 int mc_count, struct dev_addr_list *mc_list) 3021 int mc_count, struct dev_addr_list *mc_list)
6564{ 3022{
6565 /* 3023 struct iwl_priv *priv = hw->priv;
6566 * XXX: dummy 3024
6567 * see also iwl4965_connection_init_rx_config 3025 if (changed_flags & (*total_flags) & FIF_OTHER_BSS) {
6568 */ 3026 IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
6569 *total_flags = 0; 3027 IEEE80211_IF_TYPE_MNTR,
3028 changed_flags, *total_flags);
3029 /* queue work 'cuz mac80211 is holding a lock which
3030 * prevents us from issuing (synchronous) f/w cmds */
3031 queue_work(priv->workqueue, &priv->set_monitor);
3032 }
3033 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI |
3034 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
6570} 3035}
6571 3036
6572static void iwl4965_mac_remove_interface(struct ieee80211_hw *hw, 3037static void iwl4965_mac_remove_interface(struct ieee80211_hw *hw,
@@ -6579,8 +3044,7 @@ static void iwl4965_mac_remove_interface(struct ieee80211_hw *hw,
6579 mutex_lock(&priv->mutex); 3044 mutex_lock(&priv->mutex);
6580 3045
6581 if (iwl_is_ready_rf(priv)) { 3046 if (iwl_is_ready_rf(priv)) {
6582 iwl4965_scan_cancel_timeout(priv, 100); 3047 iwl_scan_cancel_timeout(priv, 100);
6583 cancel_delayed_work(&priv->post_associate);
6584 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; 3048 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6585 iwl4965_commit_rxon(priv); 3049 iwl4965_commit_rxon(priv);
6586 } 3050 }
@@ -6596,64 +3060,6 @@ static void iwl4965_mac_remove_interface(struct ieee80211_hw *hw,
6596 3060
6597} 3061}
6598 3062
6599
6600#ifdef CONFIG_IWL4965_HT
6601static void iwl4965_ht_conf(struct iwl_priv *priv,
6602 struct ieee80211_bss_conf *bss_conf)
6603{
6604 struct ieee80211_ht_info *ht_conf = bss_conf->ht_conf;
6605 struct ieee80211_ht_bss_info *ht_bss_conf = bss_conf->ht_bss_conf;
6606 struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
6607
6608 IWL_DEBUG_MAC80211("enter: \n");
6609
6610 iwl_conf->is_ht = bss_conf->assoc_ht;
6611
6612 if (!iwl_conf->is_ht)
6613 return;
6614
6615 priv->ps_mode = (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2);
6616
6617 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20)
6618 iwl_conf->sgf |= 0x1;
6619 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40)
6620 iwl_conf->sgf |= 0x2;
6621
6622 iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD);
6623 iwl_conf->max_amsdu_size =
6624 !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU);
6625
6626 iwl_conf->supported_chan_width =
6627 !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH);
6628 iwl_conf->extension_chan_offset =
6629 ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_SEC_OFFSET;
6630 /* If no above or below channel supplied disable FAT channel */
6631 if (iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_ABOVE &&
6632 iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_BELOW)
6633 iwl_conf->supported_chan_width = 0;
6634
6635 iwl_conf->tx_mimo_ps_mode =
6636 (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2);
6637 memcpy(iwl_conf->supp_mcs_set, ht_conf->supp_mcs_set, 16);
6638
6639 iwl_conf->control_channel = ht_bss_conf->primary_channel;
6640 iwl_conf->tx_chan_width =
6641 !!(ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_WIDTH);
6642 iwl_conf->ht_protection =
6643 ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_HT_PROTECTION;
6644 iwl_conf->non_GF_STA_present =
6645 !!(ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_NON_GF_STA_PRSNT);
6646
6647 IWL_DEBUG_MAC80211("control channel %d\n", iwl_conf->control_channel);
6648 IWL_DEBUG_MAC80211("leave\n");
6649}
6650#else
6651static inline void iwl4965_ht_conf(struct iwl_priv *priv,
6652 struct ieee80211_bss_conf *bss_conf)
6653{
6654}
6655#endif
6656
6657#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) 3063#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
6658static void iwl4965_bss_info_changed(struct ieee80211_hw *hw, 3064static void iwl4965_bss_info_changed(struct ieee80211_hw *hw,
6659 struct ieee80211_vif *vif, 3065 struct ieee80211_vif *vif,
@@ -6684,7 +3090,7 @@ static void iwl4965_bss_info_changed(struct ieee80211_hw *hw,
6684 if (changes & BSS_CHANGED_HT) { 3090 if (changes & BSS_CHANGED_HT) {
6685 IWL_DEBUG_MAC80211("HT %d\n", bss_conf->assoc_ht); 3091 IWL_DEBUG_MAC80211("HT %d\n", bss_conf->assoc_ht);
6686 iwl4965_ht_conf(priv, bss_conf); 3092 iwl4965_ht_conf(priv, bss_conf);
6687 iwl4965_set_rxon_chain(priv); 3093 iwl_set_rxon_chain(priv);
6688 } 3094 }
6689 3095
6690 if (changes & BSS_CHANGED_ASSOC) { 3096 if (changes & BSS_CHANGED_ASSOC) {
@@ -6751,7 +3157,7 @@ static int iwl4965_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
6751 } 3157 }
6752 if (len) { 3158 if (len) {
6753 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ", 3159 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
6754 iwl4965_escape_essid(ssid, len), (int)len); 3160 iwl_escape_essid(ssid, len), (int)len);
6755 3161
6756 priv->one_direct_scan = 1; 3162 priv->one_direct_scan = 1;
6757 priv->direct_ssid_len = (u8) 3163 priv->direct_ssid_len = (u8)
@@ -6760,7 +3166,7 @@ static int iwl4965_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
6760 } else 3166 } else
6761 priv->one_direct_scan = 0; 3167 priv->one_direct_scan = 0;
6762 3168
6763 rc = iwl4965_scan_initiate(priv); 3169 rc = iwl_scan_initiate(priv);
6764 3170
6765 IWL_DEBUG_MAC80211("leave\n"); 3171 IWL_DEBUG_MAC80211("leave\n");
6766 3172
@@ -6784,14 +3190,14 @@ static void iwl4965_mac_update_tkip_key(struct ieee80211_hw *hw,
6784 3190
6785 IWL_DEBUG_MAC80211("enter\n"); 3191 IWL_DEBUG_MAC80211("enter\n");
6786 3192
6787 sta_id = iwl4965_hw_find_station(priv, addr); 3193 sta_id = iwl_find_station(priv, addr);
6788 if (sta_id == IWL_INVALID_STATION) { 3194 if (sta_id == IWL_INVALID_STATION) {
6789 IWL_DEBUG_MAC80211("leave - %s not in station map.\n", 3195 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
6790 print_mac(mac, addr)); 3196 print_mac(mac, addr));
6791 return; 3197 return;
6792 } 3198 }
6793 3199
6794 iwl4965_scan_cancel_timeout(priv, 100); 3200 iwl_scan_cancel_timeout(priv, 100);
6795 3201
6796 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); 3202 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
6797 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 3203 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
@@ -6812,7 +3218,7 @@ static void iwl4965_mac_update_tkip_key(struct ieee80211_hw *hw,
6812 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3218 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
6813 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3219 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
6814 3220
6815 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC); 3221 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
6816 3222
6817 spin_unlock_irqrestore(&priv->sta_lock, flags); 3223 spin_unlock_irqrestore(&priv->sta_lock, flags);
6818 3224
@@ -6831,7 +3237,7 @@ static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6831 3237
6832 IWL_DEBUG_MAC80211("enter\n"); 3238 IWL_DEBUG_MAC80211("enter\n");
6833 3239
6834 if (priv->cfg->mod_params->sw_crypto) { 3240 if (priv->hw_params.sw_crypto) {
6835 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n"); 3241 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
6836 return -EOPNOTSUPP; 3242 return -EOPNOTSUPP;
6837 } 3243 }
@@ -6840,7 +3246,7 @@ static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6840 /* only support pairwise keys */ 3246 /* only support pairwise keys */
6841 return -EOPNOTSUPP; 3247 return -EOPNOTSUPP;
6842 3248
6843 sta_id = iwl4965_hw_find_station(priv, addr); 3249 sta_id = iwl_find_station(priv, addr);
6844 if (sta_id == IWL_INVALID_STATION) { 3250 if (sta_id == IWL_INVALID_STATION) {
6845 IWL_DEBUG_MAC80211("leave - %s not in station map.\n", 3251 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
6846 print_mac(mac, addr)); 3252 print_mac(mac, addr));
@@ -6849,7 +3255,7 @@ static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6849 } 3255 }
6850 3256
6851 mutex_lock(&priv->mutex); 3257 mutex_lock(&priv->mutex);
6852 iwl4965_scan_cancel_timeout(priv, 100); 3258 iwl_scan_cancel_timeout(priv, 100);
6853 mutex_unlock(&priv->mutex); 3259 mutex_unlock(&priv->mutex);
6854 3260
6855 /* If we are getting WEP group key and we didn't receive any key mapping 3261 /* If we are getting WEP group key and we didn't receive any key mapping
@@ -6861,7 +3267,8 @@ static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6861 if (cmd == SET_KEY) 3267 if (cmd == SET_KEY)
6862 is_default_wep_key = !priv->key_mapping_key; 3268 is_default_wep_key = !priv->key_mapping_key;
6863 else 3269 else
6864 is_default_wep_key = priv->default_wep_key; 3270 is_default_wep_key =
3271 (key->hw_key_idx == HW_KEY_DEFAULT);
6865 } 3272 }
6866 3273
6867 switch (cmd) { 3274 switch (cmd) {
@@ -6877,7 +3284,7 @@ static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6877 if (is_default_wep_key) 3284 if (is_default_wep_key)
6878 ret = iwl_remove_default_wep_key(priv, key); 3285 ret = iwl_remove_default_wep_key(priv, key);
6879 else 3286 else
6880 ret = iwl_remove_dynamic_key(priv, sta_id); 3287 ret = iwl_remove_dynamic_key(priv, key, sta_id);
6881 3288
6882 IWL_DEBUG_MAC80211("disable hwcrypto key\n"); 3289 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
6883 break; 3290 break;
@@ -6890,7 +3297,7 @@ static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6890 return ret; 3297 return ret;
6891} 3298}
6892 3299
6893static int iwl4965_mac_conf_tx(struct ieee80211_hw *hw, int queue, 3300static int iwl4965_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
6894 const struct ieee80211_tx_queue_params *params) 3301 const struct ieee80211_tx_queue_params *params)
6895{ 3302{
6896 struct iwl_priv *priv = hw->priv; 3303 struct iwl_priv *priv = hw->priv;
@@ -6927,15 +3334,12 @@ static int iwl4965_mac_conf_tx(struct ieee80211_hw *hw, int queue,
6927 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; 3334 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
6928 priv->qos_data.qos_active = 1; 3335 priv->qos_data.qos_active = 1;
6929 3336
6930 spin_unlock_irqrestore(&priv->lock, flags);
6931
6932 mutex_lock(&priv->mutex);
6933 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) 3337 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
6934 iwl4965_activate_qos(priv, 1); 3338 iwl_activate_qos(priv, 1);
6935 else if (priv->assoc_id && iwl_is_associated(priv)) 3339 else if (priv->assoc_id && iwl_is_associated(priv))
6936 iwl4965_activate_qos(priv, 0); 3340 iwl_activate_qos(priv, 0);
6937 3341
6938 mutex_unlock(&priv->mutex); 3342 spin_unlock_irqrestore(&priv->lock, flags);
6939 3343
6940 IWL_DEBUG_MAC80211("leave\n"); 3344 IWL_DEBUG_MAC80211("leave\n");
6941 return 0; 3345 return 0;
@@ -6946,8 +3350,8 @@ static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw,
6946{ 3350{
6947 struct iwl_priv *priv = hw->priv; 3351 struct iwl_priv *priv = hw->priv;
6948 int i, avail; 3352 int i, avail;
6949 struct iwl4965_tx_queue *txq; 3353 struct iwl_tx_queue *txq;
6950 struct iwl4965_queue *q; 3354 struct iwl_queue *q;
6951 unsigned long flags; 3355 unsigned long flags;
6952 3356
6953 IWL_DEBUG_MAC80211("enter\n"); 3357 IWL_DEBUG_MAC80211("enter\n");
@@ -6962,11 +3366,11 @@ static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw,
6962 for (i = 0; i < AC_NUM; i++) { 3366 for (i = 0; i < AC_NUM; i++) {
6963 txq = &priv->txq[i]; 3367 txq = &priv->txq[i];
6964 q = &txq->q; 3368 q = &txq->q;
6965 avail = iwl4965_queue_space(q); 3369 avail = iwl_queue_space(q);
6966 3370
6967 stats->data[i].len = q->n_window - avail; 3371 stats[i].len = q->n_window - avail;
6968 stats->data[i].limit = q->n_window - q->high_mark; 3372 stats[i].limit = q->n_window - q->high_mark;
6969 stats->data[i].count = q->n_window; 3373 stats[i].count = q->n_window;
6970 3374
6971 } 3375 }
6972 spin_unlock_irqrestore(&priv->lock, flags); 3376 spin_unlock_irqrestore(&priv->lock, flags);
@@ -6979,14 +3383,9 @@ static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw,
6979static int iwl4965_mac_get_stats(struct ieee80211_hw *hw, 3383static int iwl4965_mac_get_stats(struct ieee80211_hw *hw,
6980 struct ieee80211_low_level_stats *stats) 3384 struct ieee80211_low_level_stats *stats)
6981{ 3385{
6982 IWL_DEBUG_MAC80211("enter\n"); 3386 struct iwl_priv *priv = hw->priv;
6983 IWL_DEBUG_MAC80211("leave\n");
6984
6985 return 0;
6986}
6987 3387
6988static u64 iwl4965_mac_get_tsf(struct ieee80211_hw *hw) 3388 priv = hw->priv;
6989{
6990 IWL_DEBUG_MAC80211("enter\n"); 3389 IWL_DEBUG_MAC80211("enter\n");
6991 IWL_DEBUG_MAC80211("leave\n"); 3390 IWL_DEBUG_MAC80211("leave\n");
6992 3391
@@ -7001,16 +3400,11 @@ static void iwl4965_mac_reset_tsf(struct ieee80211_hw *hw)
7001 mutex_lock(&priv->mutex); 3400 mutex_lock(&priv->mutex);
7002 IWL_DEBUG_MAC80211("enter\n"); 3401 IWL_DEBUG_MAC80211("enter\n");
7003 3402
7004 priv->lq_mngr.lq_ready = 0;
7005#ifdef CONFIG_IWL4965_HT
7006 spin_lock_irqsave(&priv->lock, flags); 3403 spin_lock_irqsave(&priv->lock, flags);
7007 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info)); 3404 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
7008 spin_unlock_irqrestore(&priv->lock, flags); 3405 spin_unlock_irqrestore(&priv->lock, flags);
7009#endif /* CONFIG_IWL4965_HT */
7010
7011 iwlcore_reset_qos(priv);
7012 3406
7013 cancel_delayed_work(&priv->post_associate); 3407 iwl_reset_qos(priv);
7014 3408
7015 spin_lock_irqsave(&priv->lock, flags); 3409 spin_lock_irqsave(&priv->lock, flags);
7016 priv->assoc_id = 0; 3410 priv->assoc_id = 0;
@@ -7040,11 +3434,13 @@ static void iwl4965_mac_reset_tsf(struct ieee80211_hw *hw)
7040 * clear RXON_FILTER_ASSOC_MSK bit 3434 * clear RXON_FILTER_ASSOC_MSK bit
7041 */ 3435 */
7042 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { 3436 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
7043 iwl4965_scan_cancel_timeout(priv, 100); 3437 iwl_scan_cancel_timeout(priv, 100);
7044 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; 3438 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
7045 iwl4965_commit_rxon(priv); 3439 iwl4965_commit_rxon(priv);
7046 } 3440 }
7047 3441
3442 iwl_power_update_mode(priv, 0);
3443
7048 /* Per mac80211.h: This is only used in IBSS mode... */ 3444 /* Per mac80211.h: This is only used in IBSS mode... */
7049 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) { 3445 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7050 3446
@@ -7060,11 +3456,11 @@ static void iwl4965_mac_reset_tsf(struct ieee80211_hw *hw)
7060 IWL_DEBUG_MAC80211("leave\n"); 3456 IWL_DEBUG_MAC80211("leave\n");
7061} 3457}
7062 3458
7063static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, 3459static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
7064 struct ieee80211_tx_control *control)
7065{ 3460{
7066 struct iwl_priv *priv = hw->priv; 3461 struct iwl_priv *priv = hw->priv;
7067 unsigned long flags; 3462 unsigned long flags;
3463 __le64 timestamp;
7068 3464
7069 mutex_lock(&priv->mutex); 3465 mutex_lock(&priv->mutex);
7070 IWL_DEBUG_MAC80211("enter\n"); 3466 IWL_DEBUG_MAC80211("enter\n");
@@ -7089,13 +3485,15 @@ static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *sk
7089 priv->ibss_beacon = skb; 3485 priv->ibss_beacon = skb;
7090 3486
7091 priv->assoc_id = 0; 3487 priv->assoc_id = 0;
3488 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
3489 priv->timestamp = le64_to_cpu(timestamp) + (priv->beacon_int * 1000);
7092 3490
7093 IWL_DEBUG_MAC80211("leave\n"); 3491 IWL_DEBUG_MAC80211("leave\n");
7094 spin_unlock_irqrestore(&priv->lock, flags); 3492 spin_unlock_irqrestore(&priv->lock, flags);
7095 3493
7096 iwlcore_reset_qos(priv); 3494 iwl_reset_qos(priv);
7097 3495
7098 queue_work(priv->workqueue, &priv->post_associate.work); 3496 iwl4965_post_associate(priv);
7099 3497
7100 mutex_unlock(&priv->mutex); 3498 mutex_unlock(&priv->mutex);
7101 3499
@@ -7118,13 +3516,18 @@ static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *sk
7118 * See the level definitions in iwl for details. 3516 * See the level definitions in iwl for details.
7119 */ 3517 */
7120 3518
7121static ssize_t show_debug_level(struct device_driver *d, char *buf) 3519static ssize_t show_debug_level(struct device *d,
3520 struct device_attribute *attr, char *buf)
7122{ 3521{
7123 return sprintf(buf, "0x%08X\n", iwl_debug_level); 3522 struct iwl_priv *priv = d->driver_data;
3523
3524 return sprintf(buf, "0x%08X\n", priv->debug_level);
7124} 3525}
7125static ssize_t store_debug_level(struct device_driver *d, 3526static ssize_t store_debug_level(struct device *d,
3527 struct device_attribute *attr,
7126 const char *buf, size_t count) 3528 const char *buf, size_t count)
7127{ 3529{
3530 struct iwl_priv *priv = d->driver_data;
7128 char *p = (char *)buf; 3531 char *p = (char *)buf;
7129 u32 val; 3532 u32 val;
7130 3533
@@ -7133,17 +3536,49 @@ static ssize_t store_debug_level(struct device_driver *d,
7133 printk(KERN_INFO DRV_NAME 3536 printk(KERN_INFO DRV_NAME
7134 ": %s is not in hex or decimal form.\n", buf); 3537 ": %s is not in hex or decimal form.\n", buf);
7135 else 3538 else
7136 iwl_debug_level = val; 3539 priv->debug_level = val;
7137 3540
7138 return strnlen(buf, count); 3541 return strnlen(buf, count);
7139} 3542}
7140 3543
7141static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO, 3544static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
7142 show_debug_level, store_debug_level); 3545 show_debug_level, store_debug_level);
3546
7143 3547
7144#endif /* CONFIG_IWLWIFI_DEBUG */ 3548#endif /* CONFIG_IWLWIFI_DEBUG */
7145 3549
7146 3550
3551static ssize_t show_version(struct device *d,
3552 struct device_attribute *attr, char *buf)
3553{
3554 struct iwl_priv *priv = d->driver_data;
3555 struct iwl_alive_resp *palive = &priv->card_alive;
3556 ssize_t pos = 0;
3557 u16 eeprom_ver;
3558
3559 if (palive->is_valid)
3560 pos += sprintf(buf + pos,
3561 "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
3562 "fw type: 0x%01X 0x%01X\n",
3563 palive->ucode_major, palive->ucode_minor,
3564 palive->sw_rev[0], palive->sw_rev[1],
3565 palive->ver_type, palive->ver_subtype);
3566 else
3567 pos += sprintf(buf + pos, "fw not loaded\n");
3568
3569 if (priv->eeprom) {
3570 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
3571 pos += sprintf(buf + pos, "EEPROM version: 0x%x\n",
3572 eeprom_ver);
3573 } else {
3574 pos += sprintf(buf + pos, "EEPROM not initialzed\n");
3575 }
3576
3577 return pos;
3578}
3579
3580static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
3581
7147static ssize_t show_temperature(struct device *d, 3582static ssize_t show_temperature(struct device *d,
7148 struct device_attribute *attr, char *buf) 3583 struct device_attribute *attr, char *buf)
7149{ 3584{
@@ -7152,7 +3587,7 @@ static ssize_t show_temperature(struct device *d,
7152 if (!iwl_is_alive(priv)) 3587 if (!iwl_is_alive(priv))
7153 return -EAGAIN; 3588 return -EAGAIN;
7154 3589
7155 return sprintf(buf, "%d\n", iwl4965_hw_get_temperature(priv)); 3590 return sprintf(buf, "%d\n", priv->temperature);
7156} 3591}
7157 3592
7158static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); 3593static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
@@ -7170,7 +3605,7 @@ static ssize_t show_tx_power(struct device *d,
7170 struct device_attribute *attr, char *buf) 3605 struct device_attribute *attr, char *buf)
7171{ 3606{
7172 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; 3607 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
7173 return sprintf(buf, "%d\n", priv->user_txpower_limit); 3608 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
7174} 3609}
7175 3610
7176static ssize_t store_tx_power(struct device *d, 3611static ssize_t store_tx_power(struct device *d,
@@ -7186,7 +3621,7 @@ static ssize_t store_tx_power(struct device *d,
7186 printk(KERN_INFO DRV_NAME 3621 printk(KERN_INFO DRV_NAME
7187 ": %s is not in decimal form.\n", buf); 3622 ": %s is not in decimal form.\n", buf);
7188 else 3623 else
7189 iwl4965_hw_reg_set_txpower(priv, val); 3624 iwl_set_tx_power(priv, val, false);
7190 3625
7191 return count; 3626 return count;
7192} 3627}
@@ -7211,7 +3646,7 @@ static ssize_t store_flags(struct device *d,
7211 mutex_lock(&priv->mutex); 3646 mutex_lock(&priv->mutex);
7212 if (le32_to_cpu(priv->staging_rxon.flags) != flags) { 3647 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7213 /* Cancel any currently running scans... */ 3648 /* Cancel any currently running scans... */
7214 if (iwl4965_scan_cancel_timeout(priv, 100)) 3649 if (iwl_scan_cancel_timeout(priv, 100))
7215 IWL_WARNING("Could not cancel scan.\n"); 3650 IWL_WARNING("Could not cancel scan.\n");
7216 else { 3651 else {
7217 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n", 3652 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
@@ -7246,7 +3681,7 @@ static ssize_t store_filter_flags(struct device *d,
7246 mutex_lock(&priv->mutex); 3681 mutex_lock(&priv->mutex);
7247 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { 3682 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7248 /* Cancel any currently running scans... */ 3683 /* Cancel any currently running scans... */
7249 if (iwl4965_scan_cancel_timeout(priv, 100)) 3684 if (iwl_scan_cancel_timeout(priv, 100))
7250 IWL_WARNING("Could not cancel scan.\n"); 3685 IWL_WARNING("Could not cancel scan.\n");
7251 else { 3686 else {
7252 IWL_DEBUG_INFO("Committing rxon.filter_flags = " 3687 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
@@ -7376,20 +3811,11 @@ static ssize_t store_power_level(struct device *d,
7376 goto out; 3811 goto out;
7377 } 3812 }
7378 3813
7379 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC)) 3814 rc = iwl_power_set_user_mode(priv, mode);
7380 mode = IWL_POWER_AC; 3815 if (rc) {
7381 else 3816 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7382 mode |= IWL_POWER_ENABLED; 3817 goto out;
7383
7384 if (mode != priv->power_mode) {
7385 rc = iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(mode));
7386 if (rc) {
7387 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7388 goto out;
7389 }
7390 priv->power_mode = mode;
7391 } 3818 }
7392
7393 rc = count; 3819 rc = count;
7394 3820
7395 out: 3821 out:
@@ -7419,7 +3845,7 @@ static ssize_t show_power_level(struct device *d,
7419 struct device_attribute *attr, char *buf) 3845 struct device_attribute *attr, char *buf)
7420{ 3846{
7421 struct iwl_priv *priv = dev_get_drvdata(d); 3847 struct iwl_priv *priv = dev_get_drvdata(d);
7422 int level = IWL_POWER_LEVEL(priv->power_mode); 3848 int level = priv->power_data.power_mode;
7423 char *p = buf; 3849 char *p = buf;
7424 3850
7425 p += sprintf(p, "%d ", level); 3851 p += sprintf(p, "%d ", level);
@@ -7437,14 +3863,14 @@ static ssize_t show_power_level(struct device *d,
7437 timeout_duration[level - 1] / 1000, 3863 timeout_duration[level - 1] / 1000,
7438 period_duration[level - 1] / 1000); 3864 period_duration[level - 1] / 1000);
7439 } 3865 }
7440 3866/*
7441 if (!(priv->power_mode & IWL_POWER_ENABLED)) 3867 if (!(priv->power_mode & IWL_POWER_ENABLED))
7442 p += sprintf(p, " OFF\n"); 3868 p += sprintf(p, " OFF\n");
7443 else 3869 else
7444 p += sprintf(p, " \n"); 3870 p += sprintf(p, " \n");
7445 3871*/
3872 p += sprintf(p, " \n");
7446 return (p - buf + 1); 3873 return (p - buf + 1);
7447
7448} 3874}
7449 3875
7450static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, 3876static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
@@ -7453,8 +3879,62 @@ static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7453static ssize_t show_channels(struct device *d, 3879static ssize_t show_channels(struct device *d,
7454 struct device_attribute *attr, char *buf) 3880 struct device_attribute *attr, char *buf)
7455{ 3881{
7456 /* all this shit doesn't belong into sysfs anyway */ 3882
7457 return 0; 3883 struct iwl_priv *priv = dev_get_drvdata(d);
3884 struct ieee80211_channel *channels = NULL;
3885 const struct ieee80211_supported_band *supp_band = NULL;
3886 int len = 0, i;
3887 int count = 0;
3888
3889 if (!test_bit(STATUS_GEO_CONFIGURED, &priv->status))
3890 return -EAGAIN;
3891
3892 supp_band = iwl_get_hw_mode(priv, IEEE80211_BAND_2GHZ);
3893 channels = supp_band->channels;
3894 count = supp_band->n_channels;
3895
3896 len += sprintf(&buf[len],
3897 "Displaying %d channels in 2.4GHz band "
3898 "(802.11bg):\n", count);
3899
3900 for (i = 0; i < count; i++)
3901 len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
3902 ieee80211_frequency_to_channel(
3903 channels[i].center_freq),
3904 channels[i].max_power,
3905 channels[i].flags & IEEE80211_CHAN_RADAR ?
3906 " (IEEE 802.11h required)" : "",
3907 (!(channels[i].flags & IEEE80211_CHAN_NO_IBSS)
3908 || (channels[i].flags &
3909 IEEE80211_CHAN_RADAR)) ? "" :
3910 ", IBSS",
3911 channels[i].flags &
3912 IEEE80211_CHAN_PASSIVE_SCAN ?
3913 "passive only" : "active/passive");
3914
3915 supp_band = iwl_get_hw_mode(priv, IEEE80211_BAND_5GHZ);
3916 channels = supp_band->channels;
3917 count = supp_band->n_channels;
3918
3919 len += sprintf(&buf[len], "Displaying %d channels in 5.2GHz band "
3920 "(802.11a):\n", count);
3921
3922 for (i = 0; i < count; i++)
3923 len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
3924 ieee80211_frequency_to_channel(
3925 channels[i].center_freq),
3926 channels[i].max_power,
3927 channels[i].flags & IEEE80211_CHAN_RADAR ?
3928 " (IEEE 802.11h required)" : "",
3929 ((channels[i].flags & IEEE80211_CHAN_NO_IBSS)
3930 || (channels[i].flags &
3931 IEEE80211_CHAN_RADAR)) ? "" :
3932 ", IBSS",
3933 channels[i].flags &
3934 IEEE80211_CHAN_PASSIVE_SCAN ?
3935 "passive only" : "active/passive");
3936
3937 return len;
7458} 3938}
7459 3939
7460static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); 3940static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
@@ -7463,7 +3943,7 @@ static ssize_t show_statistics(struct device *d,
7463 struct device_attribute *attr, char *buf) 3943 struct device_attribute *attr, char *buf)
7464{ 3944{
7465 struct iwl_priv *priv = dev_get_drvdata(d); 3945 struct iwl_priv *priv = dev_get_drvdata(d);
7466 u32 size = sizeof(struct iwl4965_notif_statistics); 3946 u32 size = sizeof(struct iwl_notif_statistics);
7467 u32 len = 0, ofs = 0; 3947 u32 len = 0, ofs = 0;
7468 u8 *data = (u8 *) & priv->statistics; 3948 u8 *data = (u8 *) & priv->statistics;
7469 int rc = 0; 3949 int rc = 0;
@@ -7497,44 +3977,6 @@ static ssize_t show_statistics(struct device *d,
7497 3977
7498static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); 3978static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7499 3979
7500static ssize_t show_antenna(struct device *d,
7501 struct device_attribute *attr, char *buf)
7502{
7503 struct iwl_priv *priv = dev_get_drvdata(d);
7504
7505 if (!iwl_is_alive(priv))
7506 return -EAGAIN;
7507
7508 return sprintf(buf, "%d\n", priv->antenna);
7509}
7510
7511static ssize_t store_antenna(struct device *d,
7512 struct device_attribute *attr,
7513 const char *buf, size_t count)
7514{
7515 int ant;
7516 struct iwl_priv *priv = dev_get_drvdata(d);
7517
7518 if (count == 0)
7519 return 0;
7520
7521 if (sscanf(buf, "%1i", &ant) != 1) {
7522 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7523 return count;
7524 }
7525
7526 if ((ant >= 0) && (ant <= 2)) {
7527 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
7528 priv->antenna = (enum iwl4965_antenna)ant;
7529 } else
7530 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7531
7532
7533 return count;
7534}
7535
7536static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7537
7538static ssize_t show_status(struct device *d, 3980static ssize_t show_status(struct device *d,
7539 struct device_attribute *attr, char *buf) 3981 struct device_attribute *attr, char *buf)
7540{ 3982{
@@ -7546,41 +3988,13 @@ static ssize_t show_status(struct device *d,
7546 3988
7547static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); 3989static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7548 3990
7549static ssize_t dump_error_log(struct device *d,
7550 struct device_attribute *attr,
7551 const char *buf, size_t count)
7552{
7553 char *p = (char *)buf;
7554
7555 if (p[0] == '1')
7556 iwl4965_dump_nic_error_log((struct iwl_priv *)d->driver_data);
7557
7558 return strnlen(buf, count);
7559}
7560
7561static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7562
7563static ssize_t dump_event_log(struct device *d,
7564 struct device_attribute *attr,
7565 const char *buf, size_t count)
7566{
7567 char *p = (char *)buf;
7568
7569 if (p[0] == '1')
7570 iwl4965_dump_nic_event_log((struct iwl_priv *)d->driver_data);
7571
7572 return strnlen(buf, count);
7573}
7574
7575static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7576
7577/***************************************************************************** 3991/*****************************************************************************
7578 * 3992 *
7579 * driver setup and teardown 3993 * driver setup and teardown
7580 * 3994 *
7581 *****************************************************************************/ 3995 *****************************************************************************/
7582 3996
7583static void iwl4965_setup_deferred_work(struct iwl_priv *priv) 3997static void iwl_setup_deferred_work(struct iwl_priv *priv)
7584{ 3998{
7585 priv->workqueue = create_workqueue(DRV_NAME); 3999 priv->workqueue = create_workqueue(DRV_NAME);
7586 4000
@@ -7589,38 +4003,42 @@ static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
7589 INIT_WORK(&priv->up, iwl4965_bg_up); 4003 INIT_WORK(&priv->up, iwl4965_bg_up);
7590 INIT_WORK(&priv->restart, iwl4965_bg_restart); 4004 INIT_WORK(&priv->restart, iwl4965_bg_restart);
7591 INIT_WORK(&priv->rx_replenish, iwl4965_bg_rx_replenish); 4005 INIT_WORK(&priv->rx_replenish, iwl4965_bg_rx_replenish);
7592 INIT_WORK(&priv->scan_completed, iwl4965_bg_scan_completed);
7593 INIT_WORK(&priv->request_scan, iwl4965_bg_request_scan);
7594 INIT_WORK(&priv->abort_scan, iwl4965_bg_abort_scan);
7595 INIT_WORK(&priv->rf_kill, iwl4965_bg_rf_kill); 4006 INIT_WORK(&priv->rf_kill, iwl4965_bg_rf_kill);
7596 INIT_WORK(&priv->beacon_update, iwl4965_bg_beacon_update); 4007 INIT_WORK(&priv->beacon_update, iwl4965_bg_beacon_update);
7597 INIT_DELAYED_WORK(&priv->post_associate, iwl4965_bg_post_associate); 4008 INIT_WORK(&priv->set_monitor, iwl4965_bg_set_monitor);
7598 INIT_DELAYED_WORK(&priv->init_alive_start, iwl4965_bg_init_alive_start); 4009 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
7599 INIT_DELAYED_WORK(&priv->alive_start, iwl4965_bg_alive_start); 4010 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
7600 INIT_DELAYED_WORK(&priv->scan_check, iwl4965_bg_scan_check); 4011 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
4012
4013 /* FIXME : remove when resolved PENDING */
4014 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
4015 iwl_setup_scan_deferred_work(priv);
4016
4017 if (priv->cfg->ops->lib->setup_deferred_work)
4018 priv->cfg->ops->lib->setup_deferred_work(priv);
7601 4019
7602 iwl4965_hw_setup_deferred_work(priv); 4020 init_timer(&priv->statistics_periodic);
4021 priv->statistics_periodic.data = (unsigned long)priv;
4022 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
7603 4023
7604 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) 4024 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
7605 iwl4965_irq_tasklet, (unsigned long)priv); 4025 iwl4965_irq_tasklet, (unsigned long)priv);
7606} 4026}
7607 4027
7608static void iwl4965_cancel_deferred_work(struct iwl_priv *priv) 4028static void iwl_cancel_deferred_work(struct iwl_priv *priv)
7609{ 4029{
7610 iwl4965_hw_cancel_deferred_work(priv); 4030 if (priv->cfg->ops->lib->cancel_deferred_work)
4031 priv->cfg->ops->lib->cancel_deferred_work(priv);
7611 4032
7612 cancel_delayed_work_sync(&priv->init_alive_start); 4033 cancel_delayed_work_sync(&priv->init_alive_start);
7613 cancel_delayed_work(&priv->scan_check); 4034 cancel_delayed_work(&priv->scan_check);
7614 cancel_delayed_work(&priv->alive_start); 4035 cancel_delayed_work(&priv->alive_start);
7615 cancel_delayed_work(&priv->post_associate);
7616 cancel_work_sync(&priv->beacon_update); 4036 cancel_work_sync(&priv->beacon_update);
4037 del_timer_sync(&priv->statistics_periodic);
7617} 4038}
7618 4039
7619static struct attribute *iwl4965_sysfs_entries[] = { 4040static struct attribute *iwl4965_sysfs_entries[] = {
7620 &dev_attr_antenna.attr,
7621 &dev_attr_channels.attr, 4041 &dev_attr_channels.attr,
7622 &dev_attr_dump_errors.attr,
7623 &dev_attr_dump_events.attr,
7624 &dev_attr_flags.attr, 4042 &dev_attr_flags.attr,
7625 &dev_attr_filter_flags.attr, 4043 &dev_attr_filter_flags.attr,
7626#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT 4044#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
@@ -7633,6 +4051,10 @@ static struct attribute *iwl4965_sysfs_entries[] = {
7633 &dev_attr_status.attr, 4051 &dev_attr_status.attr,
7634 &dev_attr_temperature.attr, 4052 &dev_attr_temperature.attr,
7635 &dev_attr_tx_power.attr, 4053 &dev_attr_tx_power.attr,
4054#ifdef CONFIG_IWLWIFI_DEBUG
4055 &dev_attr_debug_level.attr,
4056#endif
4057 &dev_attr_version.attr,
7636 4058
7637 NULL 4059 NULL
7638}; 4060};
@@ -7656,13 +4078,9 @@ static struct ieee80211_ops iwl4965_hw_ops = {
7656 .get_stats = iwl4965_mac_get_stats, 4078 .get_stats = iwl4965_mac_get_stats,
7657 .get_tx_stats = iwl4965_mac_get_tx_stats, 4079 .get_tx_stats = iwl4965_mac_get_tx_stats,
7658 .conf_tx = iwl4965_mac_conf_tx, 4080 .conf_tx = iwl4965_mac_conf_tx,
7659 .get_tsf = iwl4965_mac_get_tsf,
7660 .reset_tsf = iwl4965_mac_reset_tsf, 4081 .reset_tsf = iwl4965_mac_reset_tsf,
7661 .beacon_update = iwl4965_mac_beacon_update,
7662 .bss_info_changed = iwl4965_bss_info_changed, 4082 .bss_info_changed = iwl4965_bss_info_changed,
7663#ifdef CONFIG_IWL4965_HT
7664 .ampdu_action = iwl4965_mac_ampdu_action, 4083 .ampdu_action = iwl4965_mac_ampdu_action,
7665#endif /* CONFIG_IWL4965_HT */
7666 .hw_scan = iwl4965_mac_hw_scan 4084 .hw_scan = iwl4965_mac_hw_scan
7667}; 4085};
7668 4086
@@ -7682,7 +4100,9 @@ static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
7682 /* Disabling hardware scan means that mac80211 will perform scans 4100 /* Disabling hardware scan means that mac80211 will perform scans
7683 * "the hard way", rather than using device's scan. */ 4101 * "the hard way", rather than using device's scan. */
7684 if (cfg->mod_params->disable_hw_scan) { 4102 if (cfg->mod_params->disable_hw_scan) {
7685 IWL_DEBUG_INFO("Disabling hw_scan\n"); 4103 if (cfg->mod_params->debug & IWL_DL_INFO)
4104 dev_printk(KERN_DEBUG, &(pdev->dev),
4105 "Disabling hw_scan\n");
7686 iwl4965_hw_ops.hw_scan = NULL; 4106 iwl4965_hw_ops.hw_scan = NULL;
7687 } 4107 }
7688 4108
@@ -7701,7 +4121,7 @@ static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
7701 priv->pci_dev = pdev; 4121 priv->pci_dev = pdev;
7702 4122
7703#ifdef CONFIG_IWLWIFI_DEBUG 4123#ifdef CONFIG_IWLWIFI_DEBUG
7704 iwl_debug_level = priv->cfg->mod_params->debug; 4124 priv->debug_level = priv->cfg->mod_params->debug;
7705 atomic_set(&priv->restrict_refcnt, 0); 4125 atomic_set(&priv->restrict_refcnt, 0);
7706#endif 4126#endif
7707 4127
@@ -7715,13 +4135,19 @@ static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
7715 4135
7716 pci_set_master(pdev); 4136 pci_set_master(pdev);
7717 4137
7718 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 4138 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
7719 if (!err) 4139 if (!err)
7720 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 4140 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4141 if (err) {
4142 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4143 if (!err)
4144 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4145 /* both attempts failed: */
7721 if (err) { 4146 if (err) {
7722 printk(KERN_WARNING DRV_NAME 4147 printk(KERN_WARNING "%s: No suitable DMA available.\n",
7723 ": No suitable DMA available.\n"); 4148 DRV_NAME);
7724 goto out_pci_disable_device; 4149 goto out_pci_disable_device;
4150 }
7725 } 4151 }
7726 4152
7727 err = pci_request_regions(pdev, DRV_NAME); 4153 err = pci_request_regions(pdev, DRV_NAME);
@@ -7747,31 +4173,31 @@ static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
7747 (unsigned long long) pci_resource_len(pdev, 0)); 4173 (unsigned long long) pci_resource_len(pdev, 0));
7748 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base); 4174 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
7749 4175
4176 iwl_hw_detect(priv);
7750 printk(KERN_INFO DRV_NAME 4177 printk(KERN_INFO DRV_NAME
7751 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name); 4178 ": Detected Intel Wireless WiFi Link %s REV=0x%X\n",
4179 priv->cfg->name, priv->hw_rev);
7752 4180
7753 /***************** 4181 /* amp init */
7754 * 4. Read EEPROM 4182 err = priv->cfg->ops->lib->apm_ops.init(priv);
7755 *****************/
7756 /* nic init */
7757 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
7758 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
7759
7760 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
7761 err = iwl_poll_bit(priv, CSR_GP_CNTRL,
7762 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
7763 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
7764 if (err < 0) { 4183 if (err < 0) {
7765 IWL_DEBUG_INFO("Failed to init the card\n"); 4184 IWL_DEBUG_INFO("Failed to init APMG\n");
7766 goto out_iounmap; 4185 goto out_iounmap;
7767 } 4186 }
4187 /*****************
4188 * 4. Read EEPROM
4189 *****************/
7768 /* Read the EEPROM */ 4190 /* Read the EEPROM */
7769 err = iwl_eeprom_init(priv); 4191 err = iwl_eeprom_init(priv);
7770 if (err) { 4192 if (err) {
7771 IWL_ERROR("Unable to init EEPROM\n"); 4193 IWL_ERROR("Unable to init EEPROM\n");
7772 goto out_iounmap; 4194 goto out_iounmap;
7773 } 4195 }
7774 /* MAC Address location in EEPROM same for 3945/4965 */ 4196 err = iwl_eeprom_check_version(priv);
4197 if (err)
4198 goto out_iounmap;
4199
4200 /* extract MAC Address */
7775 iwl_eeprom_get_mac(priv, priv->mac_addr); 4201 iwl_eeprom_get_mac(priv, priv->mac_addr);
7776 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr)); 4202 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
7777 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); 4203 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
@@ -7779,19 +4205,18 @@ static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
7779 /************************ 4205 /************************
7780 * 5. Setup HW constants 4206 * 5. Setup HW constants
7781 ************************/ 4207 ************************/
7782 /* Device-specific setup */ 4208 if (iwl_set_hw_params(priv)) {
7783 if (priv->cfg->ops->lib->set_hw_params(priv)) {
7784 IWL_ERROR("failed to set hw parameters\n"); 4209 IWL_ERROR("failed to set hw parameters\n");
7785 goto out_iounmap; 4210 goto out_free_eeprom;
7786 } 4211 }
7787 4212
7788 /******************* 4213 /*******************
7789 * 6. Setup hw/priv 4214 * 6. Setup priv
7790 *******************/ 4215 *******************/
7791 4216
7792 err = iwl_setup(priv); 4217 err = iwl_init_drv(priv);
7793 if (err) 4218 if (err)
7794 goto out_unset_hw_params; 4219 goto out_free_eeprom;
7795 /* At this point both hw and priv are initialized. */ 4220 /* At this point both hw and priv are initialized. */
7796 4221
7797 /********************************** 4222 /**********************************
@@ -7804,9 +4229,6 @@ static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
7804 IWL_DEBUG_INFO("Radio disabled.\n"); 4229 IWL_DEBUG_INFO("Radio disabled.\n");
7805 } 4230 }
7806 4231
7807 if (priv->cfg->mod_params->enable_qos)
7808 priv->qos_data.qos_enable = 1;
7809
7810 /******************** 4232 /********************
7811 * 8. Setup services 4233 * 8. Setup services
7812 ********************/ 4234 ********************/
@@ -7817,17 +4239,12 @@ static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
7817 err = sysfs_create_group(&pdev->dev.kobj, &iwl4965_attribute_group); 4239 err = sysfs_create_group(&pdev->dev.kobj, &iwl4965_attribute_group);
7818 if (err) { 4240 if (err) {
7819 IWL_ERROR("failed to create sysfs device attributes\n"); 4241 IWL_ERROR("failed to create sysfs device attributes\n");
7820 goto out_unset_hw_params; 4242 goto out_uninit_drv;
7821 } 4243 }
7822 4244
7823 err = iwl_dbgfs_register(priv, DRV_NAME);
7824 if (err) {
7825 IWL_ERROR("failed to create debugfs files\n");
7826 goto out_remove_sysfs;
7827 }
7828 4245
7829 iwl4965_setup_deferred_work(priv); 4246 iwl_setup_deferred_work(priv);
7830 iwl4965_setup_rx_handlers(priv); 4247 iwl_setup_rx_handlers(priv);
7831 4248
7832 /******************** 4249 /********************
7833 * 9. Conclude 4250 * 9. Conclude
@@ -7835,14 +4252,31 @@ static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
7835 pci_save_state(pdev); 4252 pci_save_state(pdev);
7836 pci_disable_device(pdev); 4253 pci_disable_device(pdev);
7837 4254
7838 /* notify iwlcore to init */ 4255 /**********************************
7839 iwlcore_low_level_notify(priv, IWLCORE_INIT_EVT); 4256 * 10. Setup and register mac80211
4257 **********************************/
4258
4259 err = iwl_setup_mac(priv);
4260 if (err)
4261 goto out_remove_sysfs;
4262
4263 err = iwl_dbgfs_register(priv, DRV_NAME);
4264 if (err)
4265 IWL_ERROR("failed to create debugfs files\n");
4266
4267 err = iwl_rfkill_init(priv);
4268 if (err)
4269 IWL_ERROR("Unable to initialize RFKILL system. "
4270 "Ignoring error: %d\n", err);
4271 iwl_power_initialize(priv);
7840 return 0; 4272 return 0;
7841 4273
7842 out_remove_sysfs: 4274 out_remove_sysfs:
7843 sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group); 4275 sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group);
7844 out_unset_hw_params: 4276 out_uninit_drv:
7845 iwl4965_unset_hw_params(priv); 4277 iwl_uninit_drv(priv);
4278 out_free_eeprom:
4279 iwl_eeprom_free(priv);
7846 out_iounmap: 4280 out_iounmap:
7847 pci_iounmap(pdev, priv->hw_base); 4281 pci_iounmap(pdev, priv->hw_base);
7848 out_pci_release_regions: 4282 out_pci_release_regions:
@@ -7859,8 +4293,6 @@ static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
7859static void __devexit iwl4965_pci_remove(struct pci_dev *pdev) 4293static void __devexit iwl4965_pci_remove(struct pci_dev *pdev)
7860{ 4294{
7861 struct iwl_priv *priv = pci_get_drvdata(pdev); 4295 struct iwl_priv *priv = pci_get_drvdata(pdev);
7862 struct list_head *p, *q;
7863 int i;
7864 unsigned long flags; 4296 unsigned long flags;
7865 4297
7866 if (!priv) 4298 if (!priv)
@@ -7868,6 +4300,9 @@ static void __devexit iwl4965_pci_remove(struct pci_dev *pdev)
7868 4300
7869 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n"); 4301 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
7870 4302
4303 iwl_dbgfs_unregister(priv);
4304 sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group);
4305
7871 if (priv->mac80211_registered) { 4306 if (priv->mac80211_registered) {
7872 ieee80211_unregister_hw(priv->hw); 4307 ieee80211_unregister_hw(priv->hw);
7873 priv->mac80211_registered = 0; 4308 priv->mac80211_registered = 0;
@@ -7886,26 +4321,15 @@ static void __devexit iwl4965_pci_remove(struct pci_dev *pdev)
7886 4321
7887 iwl_synchronize_irq(priv); 4322 iwl_synchronize_irq(priv);
7888 4323
7889 /* Free MAC hash list for ADHOC */ 4324 iwl_rfkill_unregister(priv);
7890 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
7891 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
7892 list_del(p);
7893 kfree(list_entry(p, struct iwl4965_ibss_seq, list));
7894 }
7895 }
7896
7897 iwlcore_low_level_notify(priv, IWLCORE_REMOVE_EVT);
7898 iwl_dbgfs_unregister(priv);
7899 sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group);
7900
7901 iwl4965_dealloc_ucode_pci(priv); 4325 iwl4965_dealloc_ucode_pci(priv);
7902 4326
7903 if (priv->rxq.bd) 4327 if (priv->rxq.bd)
7904 iwl4965_rx_queue_free(priv, &priv->rxq); 4328 iwl_rx_queue_free(priv, &priv->rxq);
7905 iwl4965_hw_txq_ctx_free(priv); 4329 iwl_hw_txq_ctx_free(priv);
7906 4330
7907 iwl4965_unset_hw_params(priv); 4331 iwl_clear_stations_table(priv);
7908 iwlcore_clear_stations_table(priv); 4332 iwl_eeprom_free(priv);
7909 4333
7910 4334
7911 /*netif_stop_queue(dev); */ 4335 /*netif_stop_queue(dev); */
@@ -7922,8 +4346,7 @@ static void __devexit iwl4965_pci_remove(struct pci_dev *pdev)
7922 pci_disable_device(pdev); 4346 pci_disable_device(pdev);
7923 pci_set_drvdata(pdev, NULL); 4347 pci_set_drvdata(pdev, NULL);
7924 4348
7925 iwl_free_channel_map(priv); 4349 iwl_uninit_drv(priv);
7926 iwl4965_free_geos(priv);
7927 4350
7928 if (priv->ibss_beacon) 4351 if (priv->ibss_beacon)
7929 dev_kfree_skb(priv->ibss_beacon); 4352 dev_kfree_skb(priv->ibss_beacon);
@@ -7973,6 +4396,19 @@ static int iwl4965_pci_resume(struct pci_dev *pdev)
7973static struct pci_device_id iwl_hw_card_ids[] = { 4396static struct pci_device_id iwl_hw_card_ids[] = {
7974 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, 4397 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
7975 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, 4398 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4399#ifdef CONFIG_IWL5000
4400 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
4401 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
4402 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
4403 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
4404 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
4405 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
4406 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
4407 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
4408 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
4409 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
4410 {IWL_PCI_DEVICE(0x423A, PCI_ANY_ID, iwl5350_agn_cfg)},
4411#endif /* CONFIG_IWL5000 */
7976 {0} 4412 {0}
7977}; 4413};
7978MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); 4414MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
@@ -8006,20 +4442,9 @@ static int __init iwl4965_init(void)
8006 IWL_ERROR("Unable to initialize PCI module\n"); 4442 IWL_ERROR("Unable to initialize PCI module\n");
8007 goto error_register; 4443 goto error_register;
8008 } 4444 }
8009#ifdef CONFIG_IWLWIFI_DEBUG
8010 ret = driver_create_file(&iwl_driver.driver, &driver_attr_debug_level);
8011 if (ret) {
8012 IWL_ERROR("Unable to create driver sysfs file\n");
8013 goto error_debug;
8014 }
8015#endif
8016 4445
8017 return ret; 4446 return ret;
8018 4447
8019#ifdef CONFIG_IWLWIFI_DEBUG
8020error_debug:
8021 pci_unregister_driver(&iwl_driver);
8022#endif
8023error_register: 4448error_register:
8024 iwl4965_rate_control_unregister(); 4449 iwl4965_rate_control_unregister();
8025 return ret; 4450 return ret;
@@ -8027,9 +4452,6 @@ error_register:
8027 4452
8028static void __exit iwl4965_exit(void) 4453static void __exit iwl4965_exit(void)
8029{ 4454{
8030#ifdef CONFIG_IWLWIFI_DEBUG
8031 driver_remove_file(&iwl_driver.driver, &driver_attr_debug_level);
8032#endif
8033 pci_unregister_driver(&iwl_driver); 4455 pci_unregister_driver(&iwl_driver);
8034 iwl4965_rate_control_unregister(); 4456 iwl4965_rate_control_unregister();
8035} 4457}
diff --git a/drivers/net/wireless/libertas/Makefile b/drivers/net/wireless/libertas/Makefile
index f0724e31adfd..02080a3682a9 100644
--- a/drivers/net/wireless/libertas/Makefile
+++ b/drivers/net/wireless/libertas/Makefile
@@ -1,9 +1,5 @@
1libertas-objs := main.o wext.o \ 1libertas-objs := main.o wext.o rx.o tx.o cmd.o cmdresp.o scan.o 11d.o \
2 rx.o tx.o cmd.o \ 2 debugfs.o persistcfg.o ethtool.o assoc.o
3 cmdresp.o scan.o \
4 11d.o \
5 debugfs.o \
6 ethtool.o assoc.o
7 3
8usb8xxx-objs += if_usb.o 4usb8xxx-objs += if_usb.o
9libertas_cs-objs += if_cs.o 5libertas_cs-objs += if_cs.o
diff --git a/drivers/net/wireless/libertas/assoc.c b/drivers/net/wireless/libertas/assoc.c
index c9c3640ce9fb..a267d6e65f03 100644
--- a/drivers/net/wireless/libertas/assoc.c
+++ b/drivers/net/wireless/libertas/assoc.c
@@ -603,7 +603,8 @@ static int assoc_helper_channel(struct lbs_private *priv,
603 /* Change mesh channel first; 21.p21 firmware won't let 603 /* Change mesh channel first; 21.p21 firmware won't let
604 you change channel otherwise (even though it'll return 604 you change channel otherwise (even though it'll return
605 an error to this */ 605 an error to this */
606 lbs_mesh_config(priv, 0, assoc_req->channel); 606 lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_STOP,
607 assoc_req->channel);
607 } 608 }
608 609
609 lbs_deb_assoc("ASSOC: channel: %d -> %d\n", 610 lbs_deb_assoc("ASSOC: channel: %d -> %d\n",
@@ -642,7 +643,8 @@ static int assoc_helper_channel(struct lbs_private *priv,
642 643
643 restore_mesh: 644 restore_mesh:
644 if (priv->mesh_dev) 645 if (priv->mesh_dev)
645 lbs_mesh_config(priv, 1, priv->curbssparams.channel); 646 lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START,
647 priv->curbssparams.channel);
646 648
647 done: 649 done:
648 lbs_deb_leave_args(LBS_DEB_ASSOC, "ret %d", ret); 650 lbs_deb_leave_args(LBS_DEB_ASSOC, "ret %d", ret);
@@ -1248,7 +1250,7 @@ static int get_common_rates(struct lbs_private *priv,
1248 lbs_deb_hex(LBS_DEB_JOIN, "common rates", tmp, tmp_size); 1250 lbs_deb_hex(LBS_DEB_JOIN, "common rates", tmp, tmp_size);
1249 lbs_deb_join("TX data rate 0x%02x\n", priv->cur_rate); 1251 lbs_deb_join("TX data rate 0x%02x\n", priv->cur_rate);
1250 1252
1251 if (!priv->auto_rate) { 1253 if (!priv->enablehwauto) {
1252 for (i = 0; i < tmp_size; i++) { 1254 for (i = 0; i < tmp_size; i++) {
1253 if (tmp[i] == priv->cur_rate) 1255 if (tmp[i] == priv->cur_rate)
1254 goto done; 1256 goto done;
diff --git a/drivers/net/wireless/libertas/cmd.c b/drivers/net/wireless/libertas/cmd.c
index 8124fd9b1353..75427e61898d 100644
--- a/drivers/net/wireless/libertas/cmd.c
+++ b/drivers/net/wireless/libertas/cmd.c
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6#include <net/iw_handler.h> 6#include <net/iw_handler.h>
7#include <net/ieee80211.h>
7#include <linux/kfifo.h> 8#include <linux/kfifo.h>
8#include "host.h" 9#include "host.h"
9#include "hostcmd.h" 10#include "hostcmd.h"
@@ -109,7 +110,7 @@ int lbs_update_hw_spec(struct lbs_private *priv)
109 * CF card firmware 5.0.16p0: cap 0x00000303 110 * CF card firmware 5.0.16p0: cap 0x00000303
110 * USB dongle firmware 5.110.17p2: cap 0x00000303 111 * USB dongle firmware 5.110.17p2: cap 0x00000303
111 */ 112 */
112 printk("libertas: %s, fw %u.%u.%up%u, cap 0x%08x\n", 113 lbs_pr_info("%s, fw %u.%u.%up%u, cap 0x%08x\n",
113 print_mac(mac, cmd.permanentaddr), 114 print_mac(mac, cmd.permanentaddr),
114 priv->fwrelease >> 24 & 0xff, 115 priv->fwrelease >> 24 & 0xff,
115 priv->fwrelease >> 16 & 0xff, 116 priv->fwrelease >> 16 & 0xff,
@@ -675,58 +676,60 @@ static int lbs_cmd_802_11_monitor_mode(struct cmd_ds_command *cmd,
675 return 0; 676 return 0;
676} 677}
677 678
678static int lbs_cmd_802_11_rate_adapt_rateset(struct lbs_private *priv, 679static __le16 lbs_rate_to_fw_bitmap(int rate, int lower_rates_ok)
679 struct cmd_ds_command *cmd,
680 u16 cmd_action)
681{ 680{
682 struct cmd_ds_802_11_rate_adapt_rateset 681/* Bit Rate
683 *rateadapt = &cmd->params.rateset; 682* 15:13 Reserved
684 683* 12 54 Mbps
685 lbs_deb_enter(LBS_DEB_CMD); 684* 11 48 Mbps
686 cmd->size = 685* 10 36 Mbps
687 cpu_to_le16(sizeof(struct cmd_ds_802_11_rate_adapt_rateset) 686* 9 24 Mbps
688 + S_DS_GEN); 687* 8 18 Mbps
689 cmd->command = cpu_to_le16(CMD_802_11_RATE_ADAPT_RATESET); 688* 7 12 Mbps
690 689* 6 9 Mbps
691 rateadapt->action = cpu_to_le16(cmd_action); 690* 5 6 Mbps
692 rateadapt->enablehwauto = cpu_to_le16(priv->enablehwauto); 691* 4 Reserved
693 rateadapt->bitmap = cpu_to_le16(priv->ratebitmap); 692* 3 11 Mbps
694 693* 2 5.5 Mbps
695 lbs_deb_leave(LBS_DEB_CMD); 694* 1 2 Mbps
696 return 0; 695* 0 1 Mbps
696**/
697
698 uint16_t ratemask;
699 int i = lbs_data_rate_to_fw_index(rate);
700 if (lower_rates_ok)
701 ratemask = (0x1fef >> (12 - i));
702 else
703 ratemask = (1 << i);
704 return cpu_to_le16(ratemask);
697} 705}
698 706
699/** 707int lbs_cmd_802_11_rate_adapt_rateset(struct lbs_private *priv,
700 * @brief Get the current data rate 708 uint16_t cmd_action)
701 *
702 * @param priv A pointer to struct lbs_private structure
703 *
704 * @return The data rate on success, error on failure
705 */
706int lbs_get_data_rate(struct lbs_private *priv)
707{ 709{
708 struct cmd_ds_802_11_data_rate cmd; 710 struct cmd_ds_802_11_rate_adapt_rateset cmd;
709 int ret = -1; 711 int ret;
710 712
711 lbs_deb_enter(LBS_DEB_CMD); 713 lbs_deb_enter(LBS_DEB_CMD);
712 714
713 memset(&cmd, 0, sizeof(cmd)); 715 if (!priv->cur_rate && !priv->enablehwauto)
714 cmd.hdr.size = cpu_to_le16(sizeof(cmd)); 716 return -EINVAL;
715 cmd.action = cpu_to_le16(CMD_ACT_GET_TX_RATE);
716
717 ret = lbs_cmd_with_response(priv, CMD_802_11_DATA_RATE, &cmd);
718 if (ret)
719 goto out;
720 717
721 lbs_deb_hex(LBS_DEB_CMD, "DATA_RATE_RESP", (u8 *) &cmd, sizeof (cmd)); 718 cmd.hdr.size = cpu_to_le16(sizeof(cmd));
722 719
723 ret = (int) lbs_fw_index_to_data_rate(cmd.rates[0]); 720 cmd.action = cpu_to_le16(cmd_action);
724 lbs_deb_cmd("DATA_RATE: current rate 0x%02x\n", ret); 721 cmd.enablehwauto = cpu_to_le16(priv->enablehwauto);
722 cmd.bitmap = lbs_rate_to_fw_bitmap(priv->cur_rate, priv->enablehwauto);
723 ret = lbs_cmd_with_response(priv, CMD_802_11_RATE_ADAPT_RATESET, &cmd);
724 if (!ret && cmd_action == CMD_ACT_GET) {
725 priv->ratebitmap = le16_to_cpu(cmd.bitmap);
726 priv->enablehwauto = le16_to_cpu(cmd.enablehwauto);
727 }
725 728
726out:
727 lbs_deb_leave_args(LBS_DEB_CMD, "ret %d", ret); 729 lbs_deb_leave_args(LBS_DEB_CMD, "ret %d", ret);
728 return ret; 730 return ret;
729} 731}
732EXPORT_SYMBOL_GPL(lbs_cmd_802_11_rate_adapt_rateset);
730 733
731/** 734/**
732 * @brief Set the data rate 735 * @brief Set the data rate
@@ -778,28 +781,6 @@ out:
778 return ret; 781 return ret;
779} 782}
780 783
781static int lbs_cmd_mac_multicast_adr(struct lbs_private *priv,
782 struct cmd_ds_command *cmd,
783 u16 cmd_action)
784{
785 struct cmd_ds_mac_multicast_adr *pMCastAdr = &cmd->params.madr;
786
787 lbs_deb_enter(LBS_DEB_CMD);
788 cmd->size = cpu_to_le16(sizeof(struct cmd_ds_mac_multicast_adr) +
789 S_DS_GEN);
790 cmd->command = cpu_to_le16(CMD_MAC_MULTICAST_ADR);
791
792 lbs_deb_cmd("MULTICAST_ADR: setting %d addresses\n", pMCastAdr->nr_of_adrs);
793 pMCastAdr->action = cpu_to_le16(cmd_action);
794 pMCastAdr->nr_of_adrs =
795 cpu_to_le16((u16) priv->nr_of_multicastmacaddr);
796 memcpy(pMCastAdr->maclist, priv->multicastlist,
797 priv->nr_of_multicastmacaddr * ETH_ALEN);
798
799 lbs_deb_leave(LBS_DEB_CMD);
800 return 0;
801}
802
803/** 784/**
804 * @brief Get the radio channel 785 * @brief Get the radio channel
805 * 786 *
@@ -1052,24 +1033,69 @@ int lbs_mesh_access(struct lbs_private *priv, uint16_t cmd_action,
1052 return ret; 1033 return ret;
1053} 1034}
1054 1035
1055int lbs_mesh_config(struct lbs_private *priv, uint16_t enable, uint16_t chan) 1036int lbs_mesh_config_send(struct lbs_private *priv,
1037 struct cmd_ds_mesh_config *cmd,
1038 uint16_t action, uint16_t type)
1039{
1040 int ret;
1041
1042 lbs_deb_enter(LBS_DEB_CMD);
1043
1044 cmd->hdr.command = cpu_to_le16(CMD_MESH_CONFIG);
1045 cmd->hdr.size = cpu_to_le16(sizeof(struct cmd_ds_mesh_config));
1046 cmd->hdr.result = 0;
1047
1048 cmd->type = cpu_to_le16(type);
1049 cmd->action = cpu_to_le16(action);
1050
1051 ret = lbs_cmd_with_response(priv, CMD_MESH_CONFIG, cmd);
1052
1053 lbs_deb_leave(LBS_DEB_CMD);
1054 return ret;
1055}
1056
1057/* This function is the CMD_MESH_CONFIG legacy function. It only handles the
1058 * START and STOP actions. The extended actions supported by CMD_MESH_CONFIG
1059 * are all handled by preparing a struct cmd_ds_mesh_config and passing it to
1060 * lbs_mesh_config_send.
1061 */
1062int lbs_mesh_config(struct lbs_private *priv, uint16_t action, uint16_t chan)
1056{ 1063{
1057 struct cmd_ds_mesh_config cmd; 1064 struct cmd_ds_mesh_config cmd;
1065 struct mrvl_meshie *ie;
1058 1066
1059 memset(&cmd, 0, sizeof(cmd)); 1067 memset(&cmd, 0, sizeof(cmd));
1060 cmd.action = cpu_to_le16(enable);
1061 cmd.channel = cpu_to_le16(chan); 1068 cmd.channel = cpu_to_le16(chan);
1062 cmd.type = cpu_to_le16(priv->mesh_tlv); 1069 ie = (struct mrvl_meshie *)cmd.data;
1063 cmd.hdr.size = cpu_to_le16(sizeof(cmd)); 1070
1064 1071 switch (action) {
1065 if (enable) { 1072 case CMD_ACT_MESH_CONFIG_START:
1066 cmd.length = cpu_to_le16(priv->mesh_ssid_len); 1073 ie->hdr.id = MFIE_TYPE_GENERIC;
1067 memcpy(cmd.data, priv->mesh_ssid, priv->mesh_ssid_len); 1074 ie->val.oui[0] = 0x00;
1075 ie->val.oui[1] = 0x50;
1076 ie->val.oui[2] = 0x43;
1077 ie->val.type = MARVELL_MESH_IE_TYPE;
1078 ie->val.subtype = MARVELL_MESH_IE_SUBTYPE;
1079 ie->val.version = MARVELL_MESH_IE_VERSION;
1080 ie->val.active_protocol_id = MARVELL_MESH_PROTO_ID_HWMP;
1081 ie->val.active_metric_id = MARVELL_MESH_METRIC_ID;
1082 ie->val.mesh_capability = MARVELL_MESH_CAPABILITY;
1083 ie->val.mesh_id_len = priv->mesh_ssid_len;
1084 memcpy(ie->val.mesh_id, priv->mesh_ssid, priv->mesh_ssid_len);
1085 ie->hdr.len = sizeof(struct mrvl_meshie_val) -
1086 IW_ESSID_MAX_SIZE + priv->mesh_ssid_len;
1087 cmd.length = cpu_to_le16(sizeof(struct mrvl_meshie_val));
1088 break;
1089 case CMD_ACT_MESH_CONFIG_STOP:
1090 break;
1091 default:
1092 return -1;
1068 } 1093 }
1069 lbs_deb_cmd("mesh config enable %d TLV %x channel %d SSID %s\n", 1094 lbs_deb_cmd("mesh config action %d type %x channel %d SSID %s\n",
1070 enable, priv->mesh_tlv, chan, 1095 action, priv->mesh_tlv, chan,
1071 escape_essid(priv->mesh_ssid, priv->mesh_ssid_len)); 1096 escape_essid(priv->mesh_ssid, priv->mesh_ssid_len));
1072 return lbs_cmd_with_response(priv, CMD_MESH_CONFIG, &cmd); 1097
1098 return lbs_mesh_config_send(priv, &cmd, action, priv->mesh_tlv);
1073} 1099}
1074 1100
1075static int lbs_cmd_bcn_ctrl(struct lbs_private * priv, 1101static int lbs_cmd_bcn_ctrl(struct lbs_private * priv,
@@ -1144,7 +1170,7 @@ static void lbs_submit_command(struct lbs_private *priv,
1144 struct cmd_header *cmd; 1170 struct cmd_header *cmd;
1145 uint16_t cmdsize; 1171 uint16_t cmdsize;
1146 uint16_t command; 1172 uint16_t command;
1147 int timeo = 5 * HZ; 1173 int timeo = 3 * HZ;
1148 int ret; 1174 int ret;
1149 1175
1150 lbs_deb_enter(LBS_DEB_HOST); 1176 lbs_deb_enter(LBS_DEB_HOST);
@@ -1162,7 +1188,7 @@ static void lbs_submit_command(struct lbs_private *priv,
1162 /* These commands take longer */ 1188 /* These commands take longer */
1163 if (command == CMD_802_11_SCAN || command == CMD_802_11_ASSOCIATE || 1189 if (command == CMD_802_11_SCAN || command == CMD_802_11_ASSOCIATE ||
1164 command == CMD_802_11_AUTHENTICATE) 1190 command == CMD_802_11_AUTHENTICATE)
1165 timeo = 10 * HZ; 1191 timeo = 5 * HZ;
1166 1192
1167 lbs_deb_cmd("DNLD_CMD: command 0x%04x, seq %d, size %d\n", 1193 lbs_deb_cmd("DNLD_CMD: command 0x%04x, seq %d, size %d\n",
1168 command, le16_to_cpu(cmd->seqnum), cmdsize); 1194 command, le16_to_cpu(cmd->seqnum), cmdsize);
@@ -1174,7 +1200,7 @@ static void lbs_submit_command(struct lbs_private *priv,
1174 lbs_pr_info("DNLD_CMD: hw_host_to_card failed: %d\n", ret); 1200 lbs_pr_info("DNLD_CMD: hw_host_to_card failed: %d\n", ret);
1175 /* Let the timer kick in and retry, and potentially reset 1201 /* Let the timer kick in and retry, and potentially reset
1176 the whole thing if the condition persists */ 1202 the whole thing if the condition persists */
1177 timeo = HZ; 1203 timeo = HZ/4;
1178 } 1204 }
1179 1205
1180 /* Setup the timer after transmit command */ 1206 /* Setup the timer after transmit command */
@@ -1279,8 +1305,7 @@ void lbs_set_mac_control(struct lbs_private *priv)
1279 cmd.action = cpu_to_le16(priv->mac_control); 1305 cmd.action = cpu_to_le16(priv->mac_control);
1280 cmd.reserved = 0; 1306 cmd.reserved = 0;
1281 1307
1282 lbs_cmd_async(priv, CMD_MAC_CONTROL, 1308 lbs_cmd_async(priv, CMD_MAC_CONTROL, &cmd.hdr, sizeof(cmd));
1283 &cmd.hdr, sizeof(cmd));
1284 1309
1285 lbs_deb_leave(LBS_DEB_CMD); 1310 lbs_deb_leave(LBS_DEB_CMD);
1286} 1311}
@@ -1387,15 +1412,6 @@ int lbs_prepare_and_send_command(struct lbs_private *priv,
1387 cmd_action, pdata_buf); 1412 cmd_action, pdata_buf);
1388 break; 1413 break;
1389 1414
1390 case CMD_802_11_RATE_ADAPT_RATESET:
1391 ret = lbs_cmd_802_11_rate_adapt_rateset(priv,
1392 cmdptr, cmd_action);
1393 break;
1394
1395 case CMD_MAC_MULTICAST_ADR:
1396 ret = lbs_cmd_mac_multicast_adr(priv, cmdptr, cmd_action);
1397 break;
1398
1399 case CMD_802_11_MONITOR_MODE: 1415 case CMD_802_11_MONITOR_MODE:
1400 ret = lbs_cmd_802_11_monitor_mode(cmdptr, 1416 ret = lbs_cmd_802_11_monitor_mode(cmdptr,
1401 cmd_action, pdata_buf); 1417 cmd_action, pdata_buf);
@@ -1484,7 +1500,7 @@ int lbs_prepare_and_send_command(struct lbs_private *priv,
1484 ret = lbs_cmd_bcn_ctrl(priv, cmdptr, cmd_action); 1500 ret = lbs_cmd_bcn_ctrl(priv, cmdptr, cmd_action);
1485 break; 1501 break;
1486 default: 1502 default:
1487 lbs_deb_host("PREP_CMD: unknown command 0x%04x\n", cmd_no); 1503 lbs_pr_err("PREP_CMD: unknown command 0x%04x\n", cmd_no);
1488 ret = -1; 1504 ret = -1;
1489 break; 1505 break;
1490 } 1506 }
diff --git a/drivers/net/wireless/libertas/cmd.h b/drivers/net/wireless/libertas/cmd.h
index 3dfc2d43c224..a53b51f8bdb4 100644
--- a/drivers/net/wireless/libertas/cmd.h
+++ b/drivers/net/wireless/libertas/cmd.h
@@ -34,18 +34,22 @@ int lbs_update_hw_spec(struct lbs_private *priv);
34int lbs_mesh_access(struct lbs_private *priv, uint16_t cmd_action, 34int lbs_mesh_access(struct lbs_private *priv, uint16_t cmd_action,
35 struct cmd_ds_mesh_access *cmd); 35 struct cmd_ds_mesh_access *cmd);
36 36
37int lbs_get_data_rate(struct lbs_private *priv);
38int lbs_set_data_rate(struct lbs_private *priv, u8 rate); 37int lbs_set_data_rate(struct lbs_private *priv, u8 rate);
39 38
40int lbs_get_channel(struct lbs_private *priv); 39int lbs_get_channel(struct lbs_private *priv);
41int lbs_set_channel(struct lbs_private *priv, u8 channel); 40int lbs_set_channel(struct lbs_private *priv, u8 channel);
42 41
42int lbs_mesh_config_send(struct lbs_private *priv,
43 struct cmd_ds_mesh_config *cmd,
44 uint16_t action, uint16_t type);
43int lbs_mesh_config(struct lbs_private *priv, uint16_t enable, uint16_t chan); 45int lbs_mesh_config(struct lbs_private *priv, uint16_t enable, uint16_t chan);
44 46
45int lbs_host_sleep_cfg(struct lbs_private *priv, uint32_t criteria); 47int lbs_host_sleep_cfg(struct lbs_private *priv, uint32_t criteria);
46int lbs_suspend(struct lbs_private *priv); 48int lbs_suspend(struct lbs_private *priv);
47int lbs_resume(struct lbs_private *priv); 49void lbs_resume(struct lbs_private *priv);
48 50
51int lbs_cmd_802_11_rate_adapt_rateset(struct lbs_private *priv,
52 uint16_t cmd_action);
49int lbs_cmd_802_11_inactivity_timeout(struct lbs_private *priv, 53int lbs_cmd_802_11_inactivity_timeout(struct lbs_private *priv,
50 uint16_t cmd_action, uint16_t *timeout); 54 uint16_t cmd_action, uint16_t *timeout);
51int lbs_cmd_802_11_sleep_params(struct lbs_private *priv, uint16_t cmd_action, 55int lbs_cmd_802_11_sleep_params(struct lbs_private *priv, uint16_t cmd_action,
diff --git a/drivers/net/wireless/libertas/cmdresp.c b/drivers/net/wireless/libertas/cmdresp.c
index 5abecb7673e6..24de3c3cf877 100644
--- a/drivers/net/wireless/libertas/cmdresp.c
+++ b/drivers/net/wireless/libertas/cmdresp.c
@@ -203,22 +203,6 @@ static int lbs_ret_802_11_rf_tx_power(struct lbs_private *priv,
203 return 0; 203 return 0;
204} 204}
205 205
206static int lbs_ret_802_11_rate_adapt_rateset(struct lbs_private *priv,
207 struct cmd_ds_command *resp)
208{
209 struct cmd_ds_802_11_rate_adapt_rateset *rates = &resp->params.rateset;
210
211 lbs_deb_enter(LBS_DEB_CMD);
212
213 if (rates->action == CMD_ACT_GET) {
214 priv->enablehwauto = le16_to_cpu(rates->enablehwauto);
215 priv->ratebitmap = le16_to_cpu(rates->bitmap);
216 }
217
218 lbs_deb_leave(LBS_DEB_CMD);
219 return 0;
220}
221
222static int lbs_ret_802_11_rssi(struct lbs_private *priv, 206static int lbs_ret_802_11_rssi(struct lbs_private *priv,
223 struct cmd_ds_command *resp) 207 struct cmd_ds_command *resp)
224{ 208{
@@ -316,16 +300,11 @@ static inline int handle_cmd_response(struct lbs_private *priv,
316 300
317 break; 301 break;
318 302
319 case CMD_RET(CMD_MAC_MULTICAST_ADR):
320 case CMD_RET(CMD_802_11_RESET): 303 case CMD_RET(CMD_802_11_RESET):
321 case CMD_RET(CMD_802_11_AUTHENTICATE): 304 case CMD_RET(CMD_802_11_AUTHENTICATE):
322 case CMD_RET(CMD_802_11_BEACON_STOP): 305 case CMD_RET(CMD_802_11_BEACON_STOP):
323 break; 306 break;
324 307
325 case CMD_RET(CMD_802_11_RATE_ADAPT_RATESET):
326 ret = lbs_ret_802_11_rate_adapt_rateset(priv, resp);
327 break;
328
329 case CMD_RET(CMD_802_11_RSSI): 308 case CMD_RET(CMD_802_11_RSSI):
330 ret = lbs_ret_802_11_rssi(priv, resp); 309 ret = lbs_ret_802_11_rssi(priv, resp);
331 break; 310 break;
@@ -376,8 +355,8 @@ static inline int handle_cmd_response(struct lbs_private *priv,
376 break; 355 break;
377 356
378 default: 357 default:
379 lbs_deb_host("CMD_RESP: unknown cmd response 0x%04x\n", 358 lbs_pr_err("CMD_RESP: unknown cmd response 0x%04x\n",
380 le16_to_cpu(resp->command)); 359 le16_to_cpu(resp->command));
381 break; 360 break;
382 } 361 }
383 lbs_deb_leave(LBS_DEB_HOST); 362 lbs_deb_leave(LBS_DEB_HOST);
diff --git a/drivers/net/wireless/libertas/decl.h b/drivers/net/wireless/libertas/decl.h
index b652fa301e19..a8ac974dacac 100644
--- a/drivers/net/wireless/libertas/decl.h
+++ b/drivers/net/wireless/libertas/decl.h
@@ -60,13 +60,17 @@ void lbs_mac_event_disconnected(struct lbs_private *priv);
60 60
61void lbs_send_iwevcustom_event(struct lbs_private *priv, s8 *str); 61void lbs_send_iwevcustom_event(struct lbs_private *priv, s8 *str);
62 62
63/* persistcfg.c */
64void lbs_persist_config_init(struct net_device *net);
65void lbs_persist_config_remove(struct net_device *net);
66
63/* main.c */ 67/* main.c */
64struct chan_freq_power *lbs_get_region_cfp_table(u8 region, 68struct chan_freq_power *lbs_get_region_cfp_table(u8 region,
65 int *cfp_no); 69 int *cfp_no);
66struct lbs_private *lbs_add_card(void *card, struct device *dmdev); 70struct lbs_private *lbs_add_card(void *card, struct device *dmdev);
67int lbs_remove_card(struct lbs_private *priv); 71void lbs_remove_card(struct lbs_private *priv);
68int lbs_start_card(struct lbs_private *priv); 72int lbs_start_card(struct lbs_private *priv);
69int lbs_stop_card(struct lbs_private *priv); 73void lbs_stop_card(struct lbs_private *priv);
70void lbs_host_to_card_done(struct lbs_private *priv); 74void lbs_host_to_card_done(struct lbs_private *priv);
71 75
72int lbs_update_channel(struct lbs_private *priv); 76int lbs_update_channel(struct lbs_private *priv);
diff --git a/drivers/net/wireless/libertas/defs.h b/drivers/net/wireless/libertas/defs.h
index d39520111062..12e687550bce 100644
--- a/drivers/net/wireless/libertas/defs.h
+++ b/drivers/net/wireless/libertas/defs.h
@@ -40,6 +40,7 @@
40#define LBS_DEB_THREAD 0x00100000 40#define LBS_DEB_THREAD 0x00100000
41#define LBS_DEB_HEX 0x00200000 41#define LBS_DEB_HEX 0x00200000
42#define LBS_DEB_SDIO 0x00400000 42#define LBS_DEB_SDIO 0x00400000
43#define LBS_DEB_SYSFS 0x00800000
43 44
44extern unsigned int lbs_debug; 45extern unsigned int lbs_debug;
45 46
@@ -81,7 +82,8 @@ do { if ((lbs_debug & (grp)) == (grp)) \
81#define lbs_deb_usbd(dev, fmt, args...) LBS_DEB_LL(LBS_DEB_USB, " usbd", "%s:" fmt, (dev)->bus_id, ##args) 82#define lbs_deb_usbd(dev, fmt, args...) LBS_DEB_LL(LBS_DEB_USB, " usbd", "%s:" fmt, (dev)->bus_id, ##args)
82#define lbs_deb_cs(fmt, args...) LBS_DEB_LL(LBS_DEB_CS, " cs", fmt, ##args) 83#define lbs_deb_cs(fmt, args...) LBS_DEB_LL(LBS_DEB_CS, " cs", fmt, ##args)
83#define lbs_deb_thread(fmt, args...) LBS_DEB_LL(LBS_DEB_THREAD, " thread", fmt, ##args) 84#define lbs_deb_thread(fmt, args...) LBS_DEB_LL(LBS_DEB_THREAD, " thread", fmt, ##args)
84#define lbs_deb_sdio(fmt, args...) LBS_DEB_LL(LBS_DEB_SDIO, " thread", fmt, ##args) 85#define lbs_deb_sdio(fmt, args...) LBS_DEB_LL(LBS_DEB_SDIO, " sdio", fmt, ##args)
86#define lbs_deb_sysfs(fmt, args...) LBS_DEB_LL(LBS_DEB_SYSFS, " sysfs", fmt, ##args)
85 87
86#define lbs_pr_info(format, args...) \ 88#define lbs_pr_info(format, args...) \
87 printk(KERN_INFO DRV_NAME": " format, ## args) 89 printk(KERN_INFO DRV_NAME": " format, ## args)
@@ -170,6 +172,16 @@ static inline void lbs_deb_hex(unsigned int grp, const char *prompt, u8 *buf, in
170 172
171#define MARVELL_MESH_IE_LENGTH 9 173#define MARVELL_MESH_IE_LENGTH 9
172 174
175/* Values used to populate the struct mrvl_mesh_ie. The only time you need this
176 * is when enabling the mesh using CMD_MESH_CONFIG.
177 */
178#define MARVELL_MESH_IE_TYPE 4
179#define MARVELL_MESH_IE_SUBTYPE 0
180#define MARVELL_MESH_IE_VERSION 0
181#define MARVELL_MESH_PROTO_ID_HWMP 0
182#define MARVELL_MESH_METRIC_ID 0
183#define MARVELL_MESH_CAPABILITY 0
184
173/** INT status Bit Definition*/ 185/** INT status Bit Definition*/
174#define MRVDRV_TX_DNLD_RDY 0x0001 186#define MRVDRV_TX_DNLD_RDY 0x0001
175#define MRVDRV_RX_UPLD_RDY 0x0002 187#define MRVDRV_RX_UPLD_RDY 0x0002
diff --git a/drivers/net/wireless/libertas/dev.h b/drivers/net/wireless/libertas/dev.h
index 0d9edb9b11f5..f5bb40c54d85 100644
--- a/drivers/net/wireless/libertas/dev.h
+++ b/drivers/net/wireless/libertas/dev.h
@@ -140,6 +140,8 @@ struct lbs_private {
140 wait_queue_head_t waitq; 140 wait_queue_head_t waitq;
141 struct workqueue_struct *work_thread; 141 struct workqueue_struct *work_thread;
142 142
143 struct work_struct mcast_work;
144
143 /** Scanning */ 145 /** Scanning */
144 struct delayed_work scan_work; 146 struct delayed_work scan_work;
145 struct delayed_work assoc_work; 147 struct delayed_work assoc_work;
@@ -151,6 +153,7 @@ struct lbs_private {
151 153
152 /** Hardware access */ 154 /** Hardware access */
153 int (*hw_host_to_card) (struct lbs_private *priv, u8 type, u8 *payload, u16 nb); 155 int (*hw_host_to_card) (struct lbs_private *priv, u8 type, u8 *payload, u16 nb);
156 void (*reset_card) (struct lbs_private *priv);
154 157
155 /* Wake On LAN */ 158 /* Wake On LAN */
156 uint32_t wol_criteria; 159 uint32_t wol_criteria;
@@ -234,8 +237,8 @@ struct lbs_private {
234 /** 802.11 statistics */ 237 /** 802.11 statistics */
235// struct cmd_DS_802_11_GET_STAT wlan802_11Stat; 238// struct cmd_DS_802_11_GET_STAT wlan802_11Stat;
236 239
237 u16 enablehwauto; 240 uint16_t enablehwauto;
238 u16 ratebitmap; 241 uint16_t ratebitmap;
239 242
240 u32 fragthsd; 243 u32 fragthsd;
241 u32 rtsthsd; 244 u32 rtsthsd;
@@ -293,7 +296,6 @@ struct lbs_private {
293 296
294 /** data rate stuff */ 297 /** data rate stuff */
295 u8 cur_rate; 298 u8 cur_rate;
296 u8 auto_rate;
297 299
298 /** RF calibration data */ 300 /** RF calibration data */
299 301
diff --git a/drivers/net/wireless/libertas/host.h b/drivers/net/wireless/libertas/host.h
index 3915c3144fad..c92e41b4faf4 100644
--- a/drivers/net/wireless/libertas/host.h
+++ b/drivers/net/wireless/libertas/host.h
@@ -256,6 +256,23 @@ enum cmd_mesh_access_opts {
256 CMD_ACT_MESH_GET_AUTOSTART_ENABLED, 256 CMD_ACT_MESH_GET_AUTOSTART_ENABLED,
257}; 257};
258 258
259/* Define actions and types for CMD_MESH_CONFIG */
260enum cmd_mesh_config_actions {
261 CMD_ACT_MESH_CONFIG_STOP = 0,
262 CMD_ACT_MESH_CONFIG_START,
263 CMD_ACT_MESH_CONFIG_SET,
264 CMD_ACT_MESH_CONFIG_GET,
265};
266
267enum cmd_mesh_config_types {
268 CMD_TYPE_MESH_SET_BOOTFLAG = 1,
269 CMD_TYPE_MESH_SET_BOOTTIME,
270 CMD_TYPE_MESH_SET_DEF_CHANNEL,
271 CMD_TYPE_MESH_SET_MESH_IE,
272 CMD_TYPE_MESH_GET_DEFAULTS,
273 CMD_TYPE_MESH_GET_MESH_IE, /* GET_DEFAULTS is superset of GET_MESHIE */
274};
275
259/** Card Event definition */ 276/** Card Event definition */
260#define MACREG_INT_CODE_TX_PPA_FREE 0 277#define MACREG_INT_CODE_TX_PPA_FREE 0
261#define MACREG_INT_CODE_TX_DMA_DONE 1 278#define MACREG_INT_CODE_TX_DMA_DONE 1
diff --git a/drivers/net/wireless/libertas/hostcmd.h b/drivers/net/wireless/libertas/hostcmd.h
index f29bc5bbda3e..913b480211a9 100644
--- a/drivers/net/wireless/libertas/hostcmd.h
+++ b/drivers/net/wireless/libertas/hostcmd.h
@@ -219,6 +219,7 @@ struct cmd_ds_mac_control {
219}; 219};
220 220
221struct cmd_ds_mac_multicast_adr { 221struct cmd_ds_mac_multicast_adr {
222 struct cmd_header hdr;
222 __le16 action; 223 __le16 action;
223 __le16 nr_of_adrs; 224 __le16 nr_of_adrs;
224 u8 maclist[ETH_ALEN * MRVDRV_MAX_MULTICAST_LIST_SIZE]; 225 u8 maclist[ETH_ALEN * MRVDRV_MAX_MULTICAST_LIST_SIZE];
@@ -499,6 +500,7 @@ struct cmd_ds_802_11_data_rate {
499}; 500};
500 501
501struct cmd_ds_802_11_rate_adapt_rateset { 502struct cmd_ds_802_11_rate_adapt_rateset {
503 struct cmd_header hdr;
502 __le16 action; 504 __le16 action;
503 __le16 enablehwauto; 505 __le16 enablehwauto;
504 __le16 bitmap; 506 __le16 bitmap;
@@ -702,8 +704,6 @@ struct cmd_ds_command {
702 struct cmd_ds_802_11_rf_tx_power txp; 704 struct cmd_ds_802_11_rf_tx_power txp;
703 struct cmd_ds_802_11_rf_antenna rant; 705 struct cmd_ds_802_11_rf_antenna rant;
704 struct cmd_ds_802_11_monitor_mode monitor; 706 struct cmd_ds_802_11_monitor_mode monitor;
705 struct cmd_ds_802_11_rate_adapt_rateset rateset;
706 struct cmd_ds_mac_multicast_adr madr;
707 struct cmd_ds_802_11_ad_hoc_join adj; 707 struct cmd_ds_802_11_ad_hoc_join adj;
708 struct cmd_ds_802_11_rssi rssi; 708 struct cmd_ds_802_11_rssi rssi;
709 struct cmd_ds_802_11_rssi_rsp rssirsp; 709 struct cmd_ds_802_11_rssi_rsp rssirsp;
diff --git a/drivers/net/wireless/libertas/if_cs.c b/drivers/net/wireless/libertas/if_cs.c
index d075b448da94..04d7a251e3f0 100644
--- a/drivers/net/wireless/libertas/if_cs.c
+++ b/drivers/net/wireless/libertas/if_cs.c
@@ -148,76 +148,149 @@ static int if_cs_poll_while_fw_download(struct if_cs_card *card, uint addr, u8 r
148{ 148{
149 int i; 149 int i;
150 150
151 for (i = 0; i < 1000; i++) { 151 for (i = 0; i < 100000; i++) {
152 u8 val = if_cs_read8(card, addr); 152 u8 val = if_cs_read8(card, addr);
153 if (val == reg) 153 if (val == reg)
154 return i; 154 return i;
155 udelay(500); 155 udelay(5);
156 } 156 }
157 return -ETIME; 157 return -ETIME;
158} 158}
159 159
160 160
161 161
162/* Host control registers and their bit definitions */ 162/*
163 163 * First the bitmasks for the host/card interrupt/status registers:
164#define IF_CS_H_STATUS 0x00000000 164 */
165#define IF_CS_H_STATUS_TX_OVER 0x0001 165#define IF_CS_BIT_TX 0x0001
166#define IF_CS_H_STATUS_RX_OVER 0x0002 166#define IF_CS_BIT_RX 0x0002
167#define IF_CS_H_STATUS_DNLD_OVER 0x0004 167#define IF_CS_BIT_COMMAND 0x0004
168 168#define IF_CS_BIT_RESP 0x0008
169#define IF_CS_H_INT_CAUSE 0x00000002 169#define IF_CS_BIT_EVENT 0x0010
170#define IF_CS_H_IC_TX_OVER 0x0001 170#define IF_CS_BIT_MASK 0x001f
171#define IF_CS_H_IC_RX_OVER 0x0002
172#define IF_CS_H_IC_DNLD_OVER 0x0004
173#define IF_CS_H_IC_POWER_DOWN 0x0008
174#define IF_CS_H_IC_HOST_EVENT 0x0010
175#define IF_CS_H_IC_MASK 0x001f
176
177#define IF_CS_H_INT_MASK 0x00000004
178#define IF_CS_H_IM_MASK 0x001f
179
180#define IF_CS_H_WRITE_LEN 0x00000014
181
182#define IF_CS_H_WRITE 0x00000016
183 171
184#define IF_CS_H_CMD_LEN 0x00000018
185 172
186#define IF_CS_H_CMD 0x0000001A
187 173
188#define IF_CS_C_READ_LEN 0x00000024 174/*
175 * It's not really clear to me what the host status register is for. It
176 * needs to be set almost in union with "host int cause". The following
177 * bits from above are used:
178 *
179 * IF_CS_BIT_TX driver downloaded a data packet
180 * IF_CS_BIT_RX driver got a data packet
181 * IF_CS_BIT_COMMAND driver downloaded a command
182 * IF_CS_BIT_RESP not used (has some meaning with powerdown)
183 * IF_CS_BIT_EVENT driver read a host event
184 */
185#define IF_CS_HOST_STATUS 0x00000000
189 186
190#define IF_CS_H_READ 0x00000010 187/*
188 * With the host int cause register can the host (that is, Linux) cause
189 * an interrupt in the firmware, to tell the firmware about those events:
190 *
191 * IF_CS_BIT_TX a data packet has been downloaded
192 * IF_CS_BIT_RX a received data packet has retrieved
193 * IF_CS_BIT_COMMAND a firmware block or a command has been downloaded
194 * IF_CS_BIT_RESP not used (has some meaning with powerdown)
195 * IF_CS_BIT_EVENT a host event (link lost etc) has been retrieved
196 */
197#define IF_CS_HOST_INT_CAUSE 0x00000002
191 198
192/* Card control registers and their bit definitions */ 199/*
200 * The host int mask register is used to enable/disable interrupt. However,
201 * I have the suspicion that disabled interrupts are lost.
202 */
203#define IF_CS_HOST_INT_MASK 0x00000004
193 204
194#define IF_CS_C_STATUS 0x00000020 205/*
195#define IF_CS_C_S_TX_DNLD_RDY 0x0001 206 * Used to send or receive data packets:
196#define IF_CS_C_S_RX_UPLD_RDY 0x0002 207 */
197#define IF_CS_C_S_CMD_DNLD_RDY 0x0004 208#define IF_CS_WRITE 0x00000016
198#define IF_CS_C_S_CMD_UPLD_RDY 0x0008 209#define IF_CS_WRITE_LEN 0x00000014
199#define IF_CS_C_S_CARDEVENT 0x0010 210#define IF_CS_READ 0x00000010
200#define IF_CS_C_S_MASK 0x001f 211#define IF_CS_READ_LEN 0x00000024
201#define IF_CS_C_S_STATUS_MASK 0x7f00
202 212
203#define IF_CS_C_INT_CAUSE 0x00000022 213/*
204#define IF_CS_C_IC_MASK 0x001f 214 * Used to send commands (and to send firmware block) and to
215 * receive command responses:
216 */
217#define IF_CS_CMD 0x0000001A
218#define IF_CS_CMD_LEN 0x00000018
219#define IF_CS_RESP 0x00000012
220#define IF_CS_RESP_LEN 0x00000030
205 221
206#define IF_CS_C_SQ_READ_LOW 0x00000028 222/*
207#define IF_CS_C_SQ_HELPER_OK 0x10 223 * The card status registers shows what the card/firmware actually
224 * accepts:
225 *
226 * IF_CS_BIT_TX you may send a data packet
227 * IF_CS_BIT_RX you may retrieve a data packet
228 * IF_CS_BIT_COMMAND you may send a command
229 * IF_CS_BIT_RESP you may retrieve a command response
230 * IF_CS_BIT_EVENT the card has a event for use (link lost, snr low etc)
231 *
232 * When reading this register several times, you will get back the same
233 * results --- with one exception: the IF_CS_BIT_EVENT clear itself
234 * automatically.
235 *
236 * Not that we don't rely on BIT_RX,_BIT_RESP or BIT_EVENT because
237 * we handle this via the card int cause register.
238 */
239#define IF_CS_CARD_STATUS 0x00000020
240#define IF_CS_CARD_STATUS_MASK 0x7f00
208 241
209#define IF_CS_C_CMD_LEN 0x00000030 242/*
243 * The card int cause register is used by the card/firmware to notify us
244 * about the following events:
245 *
246 * IF_CS_BIT_TX a data packet has successfully been sentx
247 * IF_CS_BIT_RX a data packet has been received and can be retrieved
248 * IF_CS_BIT_COMMAND not used
249 * IF_CS_BIT_RESP the firmware has a command response for us
250 * IF_CS_BIT_EVENT the card has a event for use (link lost, snr low etc)
251 */
252#define IF_CS_CARD_INT_CAUSE 0x00000022
210 253
211#define IF_CS_C_CMD 0x00000012 254/*
255 * This is used to for handshaking with the card's bootloader/helper image
256 * to synchronize downloading of firmware blocks.
257 */
258#define IF_CS_SQ_READ_LOW 0x00000028
259#define IF_CS_SQ_HELPER_OK 0x10
212 260
261/*
262 * The scratch register tells us ...
263 *
264 * IF_CS_SCRATCH_BOOT_OK the bootloader runs
265 * IF_CS_SCRATCH_HELPER_OK the helper firmware already runs
266 */
213#define IF_CS_SCRATCH 0x0000003F 267#define IF_CS_SCRATCH 0x0000003F
268#define IF_CS_SCRATCH_BOOT_OK 0x00
269#define IF_CS_SCRATCH_HELPER_OK 0x5a
214 270
271/*
272 * Used to detect ancient chips:
273 */
274#define IF_CS_PRODUCT_ID 0x0000001C
275#define IF_CS_CF8385_B1_REV 0x12
215 276
216 277
217/********************************************************************/ 278/********************************************************************/
218/* I/O */ 279/* I/O and interrupt handling */
219/********************************************************************/ 280/********************************************************************/
220 281
282static inline void if_cs_enable_ints(struct if_cs_card *card)
283{
284 lbs_deb_enter(LBS_DEB_CS);
285 if_cs_write16(card, IF_CS_HOST_INT_MASK, 0);
286}
287
288static inline void if_cs_disable_ints(struct if_cs_card *card)
289{
290 lbs_deb_enter(LBS_DEB_CS);
291 if_cs_write16(card, IF_CS_HOST_INT_MASK, IF_CS_BIT_MASK);
292}
293
221/* 294/*
222 * Called from if_cs_host_to_card to send a command to the hardware 295 * Called from if_cs_host_to_card to send a command to the hardware
223 */ 296 */
@@ -228,11 +301,12 @@ static int if_cs_send_cmd(struct lbs_private *priv, u8 *buf, u16 nb)
228 int loops = 0; 301 int loops = 0;
229 302
230 lbs_deb_enter(LBS_DEB_CS); 303 lbs_deb_enter(LBS_DEB_CS);
304 if_cs_disable_ints(card);
231 305
232 /* Is hardware ready? */ 306 /* Is hardware ready? */
233 while (1) { 307 while (1) {
234 u16 val = if_cs_read16(card, IF_CS_C_STATUS); 308 u16 status = if_cs_read16(card, IF_CS_CARD_STATUS);
235 if (val & IF_CS_C_S_CMD_DNLD_RDY) 309 if (status & IF_CS_BIT_COMMAND)
236 break; 310 break;
237 if (++loops > 100) { 311 if (++loops > 100) {
238 lbs_pr_err("card not ready for commands\n"); 312 lbs_pr_err("card not ready for commands\n");
@@ -241,51 +315,56 @@ static int if_cs_send_cmd(struct lbs_private *priv, u8 *buf, u16 nb)
241 mdelay(1); 315 mdelay(1);
242 } 316 }
243 317
244 if_cs_write16(card, IF_CS_H_CMD_LEN, nb); 318 if_cs_write16(card, IF_CS_CMD_LEN, nb);
245 319
246 if_cs_write16_rep(card, IF_CS_H_CMD, buf, nb / 2); 320 if_cs_write16_rep(card, IF_CS_CMD, buf, nb / 2);
247 /* Are we supposed to transfer an odd amount of bytes? */ 321 /* Are we supposed to transfer an odd amount of bytes? */
248 if (nb & 1) 322 if (nb & 1)
249 if_cs_write8(card, IF_CS_H_CMD, buf[nb-1]); 323 if_cs_write8(card, IF_CS_CMD, buf[nb-1]);
250 324
251 /* "Assert the download over interrupt command in the Host 325 /* "Assert the download over interrupt command in the Host
252 * status register" */ 326 * status register" */
253 if_cs_write16(card, IF_CS_H_STATUS, IF_CS_H_STATUS_DNLD_OVER); 327 if_cs_write16(card, IF_CS_HOST_STATUS, IF_CS_BIT_COMMAND);
254 328
255 /* "Assert the download over interrupt command in the Card 329 /* "Assert the download over interrupt command in the Card
256 * interrupt case register" */ 330 * interrupt case register" */
257 if_cs_write16(card, IF_CS_H_INT_CAUSE, IF_CS_H_IC_DNLD_OVER); 331 if_cs_write16(card, IF_CS_HOST_INT_CAUSE, IF_CS_BIT_COMMAND);
258 ret = 0; 332 ret = 0;
259 333
260done: 334done:
335 if_cs_enable_ints(card);
261 lbs_deb_leave_args(LBS_DEB_CS, "ret %d", ret); 336 lbs_deb_leave_args(LBS_DEB_CS, "ret %d", ret);
262 return ret; 337 return ret;
263} 338}
264 339
265
266/* 340/*
267 * Called from if_cs_host_to_card to send a data to the hardware 341 * Called from if_cs_host_to_card to send a data to the hardware
268 */ 342 */
269static void if_cs_send_data(struct lbs_private *priv, u8 *buf, u16 nb) 343static void if_cs_send_data(struct lbs_private *priv, u8 *buf, u16 nb)
270{ 344{
271 struct if_cs_card *card = (struct if_cs_card *)priv->card; 345 struct if_cs_card *card = (struct if_cs_card *)priv->card;
346 u16 status;
272 347
273 lbs_deb_enter(LBS_DEB_CS); 348 lbs_deb_enter(LBS_DEB_CS);
349 if_cs_disable_ints(card);
350
351 status = if_cs_read16(card, IF_CS_CARD_STATUS);
352 BUG_ON((status & IF_CS_BIT_TX) == 0);
274 353
275 if_cs_write16(card, IF_CS_H_WRITE_LEN, nb); 354 if_cs_write16(card, IF_CS_WRITE_LEN, nb);
276 355
277 /* write even number of bytes, then odd byte if necessary */ 356 /* write even number of bytes, then odd byte if necessary */
278 if_cs_write16_rep(card, IF_CS_H_WRITE, buf, nb / 2); 357 if_cs_write16_rep(card, IF_CS_WRITE, buf, nb / 2);
279 if (nb & 1) 358 if (nb & 1)
280 if_cs_write8(card, IF_CS_H_WRITE, buf[nb-1]); 359 if_cs_write8(card, IF_CS_WRITE, buf[nb-1]);
281 360
282 if_cs_write16(card, IF_CS_H_STATUS, IF_CS_H_STATUS_TX_OVER); 361 if_cs_write16(card, IF_CS_HOST_STATUS, IF_CS_BIT_TX);
283 if_cs_write16(card, IF_CS_H_INT_CAUSE, IF_CS_H_STATUS_TX_OVER); 362 if_cs_write16(card, IF_CS_HOST_INT_CAUSE, IF_CS_BIT_TX);
363 if_cs_enable_ints(card);
284 364
285 lbs_deb_leave(LBS_DEB_CS); 365 lbs_deb_leave(LBS_DEB_CS);
286} 366}
287 367
288
289/* 368/*
290 * Get the command result out of the card. 369 * Get the command result out of the card.
291 */ 370 */
@@ -293,27 +372,28 @@ static int if_cs_receive_cmdres(struct lbs_private *priv, u8 *data, u32 *len)
293{ 372{
294 unsigned long flags; 373 unsigned long flags;
295 int ret = -1; 374 int ret = -1;
296 u16 val; 375 u16 status;
297 376
298 lbs_deb_enter(LBS_DEB_CS); 377 lbs_deb_enter(LBS_DEB_CS);
299 378
300 /* is hardware ready? */ 379 /* is hardware ready? */
301 val = if_cs_read16(priv->card, IF_CS_C_STATUS); 380 status = if_cs_read16(priv->card, IF_CS_CARD_STATUS);
302 if ((val & IF_CS_C_S_CMD_UPLD_RDY) == 0) { 381 if ((status & IF_CS_BIT_RESP) == 0) {
303 lbs_pr_err("card not ready for CMD\n"); 382 lbs_pr_err("no cmd response in card\n");
383 *len = 0;
304 goto out; 384 goto out;
305 } 385 }
306 386
307 *len = if_cs_read16(priv->card, IF_CS_C_CMD_LEN); 387 *len = if_cs_read16(priv->card, IF_CS_RESP_LEN);
308 if ((*len == 0) || (*len > LBS_CMD_BUFFER_SIZE)) { 388 if ((*len == 0) || (*len > LBS_CMD_BUFFER_SIZE)) {
309 lbs_pr_err("card cmd buffer has invalid # of bytes (%d)\n", *len); 389 lbs_pr_err("card cmd buffer has invalid # of bytes (%d)\n", *len);
310 goto out; 390 goto out;
311 } 391 }
312 392
313 /* read even number of bytes, then odd byte if necessary */ 393 /* read even number of bytes, then odd byte if necessary */
314 if_cs_read16_rep(priv->card, IF_CS_C_CMD, data, *len/sizeof(u16)); 394 if_cs_read16_rep(priv->card, IF_CS_RESP, data, *len/sizeof(u16));
315 if (*len & 1) 395 if (*len & 1)
316 data[*len-1] = if_cs_read8(priv->card, IF_CS_C_CMD); 396 data[*len-1] = if_cs_read8(priv->card, IF_CS_RESP);
317 397
318 /* This is a workaround for a firmware that reports too much 398 /* This is a workaround for a firmware that reports too much
319 * bytes */ 399 * bytes */
@@ -330,7 +410,6 @@ out:
330 return ret; 410 return ret;
331} 411}
332 412
333
334static struct sk_buff *if_cs_receive_data(struct lbs_private *priv) 413static struct sk_buff *if_cs_receive_data(struct lbs_private *priv)
335{ 414{
336 struct sk_buff *skb = NULL; 415 struct sk_buff *skb = NULL;
@@ -339,7 +418,7 @@ static struct sk_buff *if_cs_receive_data(struct lbs_private *priv)
339 418
340 lbs_deb_enter(LBS_DEB_CS); 419 lbs_deb_enter(LBS_DEB_CS);
341 420
342 len = if_cs_read16(priv->card, IF_CS_C_READ_LEN); 421 len = if_cs_read16(priv->card, IF_CS_READ_LEN);
343 if (len == 0 || len > MRVDRV_ETH_RX_PACKET_BUFFER_SIZE) { 422 if (len == 0 || len > MRVDRV_ETH_RX_PACKET_BUFFER_SIZE) {
344 lbs_pr_err("card data buffer has invalid # of bytes (%d)\n", len); 423 lbs_pr_err("card data buffer has invalid # of bytes (%d)\n", len);
345 priv->stats.rx_dropped++; 424 priv->stats.rx_dropped++;
@@ -354,38 +433,19 @@ static struct sk_buff *if_cs_receive_data(struct lbs_private *priv)
354 data = skb->data; 433 data = skb->data;
355 434
356 /* read even number of bytes, then odd byte if necessary */ 435 /* read even number of bytes, then odd byte if necessary */
357 if_cs_read16_rep(priv->card, IF_CS_H_READ, data, len/sizeof(u16)); 436 if_cs_read16_rep(priv->card, IF_CS_READ, data, len/sizeof(u16));
358 if (len & 1) 437 if (len & 1)
359 data[len-1] = if_cs_read8(priv->card, IF_CS_H_READ); 438 data[len-1] = if_cs_read8(priv->card, IF_CS_READ);
360 439
361dat_err: 440dat_err:
362 if_cs_write16(priv->card, IF_CS_H_STATUS, IF_CS_H_STATUS_RX_OVER); 441 if_cs_write16(priv->card, IF_CS_HOST_STATUS, IF_CS_BIT_RX);
363 if_cs_write16(priv->card, IF_CS_H_INT_CAUSE, IF_CS_H_IC_RX_OVER); 442 if_cs_write16(priv->card, IF_CS_HOST_INT_CAUSE, IF_CS_BIT_RX);
364 443
365out: 444out:
366 lbs_deb_leave_args(LBS_DEB_CS, "ret %p", skb); 445 lbs_deb_leave_args(LBS_DEB_CS, "ret %p", skb);
367 return skb; 446 return skb;
368} 447}
369 448
370
371
372/********************************************************************/
373/* Interrupts */
374/********************************************************************/
375
376static inline void if_cs_enable_ints(struct if_cs_card *card)
377{
378 lbs_deb_enter(LBS_DEB_CS);
379 if_cs_write16(card, IF_CS_H_INT_MASK, 0);
380}
381
382static inline void if_cs_disable_ints(struct if_cs_card *card)
383{
384 lbs_deb_enter(LBS_DEB_CS);
385 if_cs_write16(card, IF_CS_H_INT_MASK, IF_CS_H_IM_MASK);
386}
387
388
389static irqreturn_t if_cs_interrupt(int irq, void *data) 449static irqreturn_t if_cs_interrupt(int irq, void *data)
390{ 450{
391 struct if_cs_card *card = data; 451 struct if_cs_card *card = data;
@@ -394,10 +454,10 @@ static irqreturn_t if_cs_interrupt(int irq, void *data)
394 454
395 lbs_deb_enter(LBS_DEB_CS); 455 lbs_deb_enter(LBS_DEB_CS);
396 456
397 cause = if_cs_read16(card, IF_CS_C_INT_CAUSE); 457 /* Ask card interrupt cause register if there is something for us */
398 if_cs_write16(card, IF_CS_C_INT_CAUSE, cause & IF_CS_C_IC_MASK); 458 cause = if_cs_read16(card, IF_CS_CARD_INT_CAUSE);
399
400 lbs_deb_cs("cause 0x%04x\n", cause); 459 lbs_deb_cs("cause 0x%04x\n", cause);
460
401 if (cause == 0) { 461 if (cause == 0) {
402 /* Not for us */ 462 /* Not for us */
403 return IRQ_NONE; 463 return IRQ_NONE;
@@ -409,11 +469,7 @@ static irqreturn_t if_cs_interrupt(int irq, void *data)
409 return IRQ_HANDLED; 469 return IRQ_HANDLED;
410 } 470 }
411 471
412 /* TODO: I'm not sure what the best ordering is */ 472 if (cause & IF_CS_BIT_RX) {
413
414 cause = if_cs_read16(card, IF_CS_C_STATUS) & IF_CS_C_S_MASK;
415
416 if (cause & IF_CS_C_S_RX_UPLD_RDY) {
417 struct sk_buff *skb; 473 struct sk_buff *skb;
418 lbs_deb_cs("rx packet\n"); 474 lbs_deb_cs("rx packet\n");
419 skb = if_cs_receive_data(priv); 475 skb = if_cs_receive_data(priv);
@@ -421,16 +477,16 @@ static irqreturn_t if_cs_interrupt(int irq, void *data)
421 lbs_process_rxed_packet(priv, skb); 477 lbs_process_rxed_packet(priv, skb);
422 } 478 }
423 479
424 if (cause & IF_CS_H_IC_TX_OVER) { 480 if (cause & IF_CS_BIT_TX) {
425 lbs_deb_cs("tx over\n"); 481 lbs_deb_cs("tx done\n");
426 lbs_host_to_card_done(priv); 482 lbs_host_to_card_done(priv);
427 } 483 }
428 484
429 if (cause & IF_CS_C_S_CMD_UPLD_RDY) { 485 if (cause & IF_CS_BIT_RESP) {
430 unsigned long flags; 486 unsigned long flags;
431 u8 i; 487 u8 i;
432 488
433 lbs_deb_cs("cmd upload ready\n"); 489 lbs_deb_cs("cmd resp\n");
434 spin_lock_irqsave(&priv->driver_lock, flags); 490 spin_lock_irqsave(&priv->driver_lock, flags);
435 i = (priv->resp_idx == 0) ? 1 : 0; 491 i = (priv->resp_idx == 0) ? 1 : 0;
436 spin_unlock_irqrestore(&priv->driver_lock, flags); 492 spin_unlock_irqrestore(&priv->driver_lock, flags);
@@ -444,15 +500,17 @@ static irqreturn_t if_cs_interrupt(int irq, void *data)
444 spin_unlock_irqrestore(&priv->driver_lock, flags); 500 spin_unlock_irqrestore(&priv->driver_lock, flags);
445 } 501 }
446 502
447 if (cause & IF_CS_H_IC_HOST_EVENT) { 503 if (cause & IF_CS_BIT_EVENT) {
448 u16 event = if_cs_read16(priv->card, IF_CS_C_STATUS) 504 u16 status = if_cs_read16(priv->card, IF_CS_CARD_STATUS);
449 & IF_CS_C_S_STATUS_MASK; 505 if_cs_write16(priv->card, IF_CS_HOST_INT_CAUSE,
450 if_cs_write16(priv->card, IF_CS_H_INT_CAUSE, 506 IF_CS_BIT_EVENT);
451 IF_CS_H_IC_HOST_EVENT); 507 lbs_queue_event(priv, (status & IF_CS_CARD_STATUS_MASK) >> 8);
452 lbs_deb_cs("eventcause 0x%04x\n", event);
453 lbs_queue_event(priv, event >> 8 & 0xff);
454 } 508 }
455 509
510 /* Clear interrupt cause */
511 if_cs_write16(card, IF_CS_CARD_INT_CAUSE, cause & IF_CS_BIT_MASK);
512
513 lbs_deb_leave(LBS_DEB_CS);
456 return IRQ_HANDLED; 514 return IRQ_HANDLED;
457} 515}
458 516
@@ -482,11 +540,11 @@ static int if_cs_prog_helper(struct if_cs_card *card)
482 /* "If the value is 0x5a, the firmware is already 540 /* "If the value is 0x5a, the firmware is already
483 * downloaded successfully" 541 * downloaded successfully"
484 */ 542 */
485 if (scratch == 0x5a) 543 if (scratch == IF_CS_SCRATCH_HELPER_OK)
486 goto done; 544 goto done;
487 545
488 /* "If the value is != 00, it is invalid value of register */ 546 /* "If the value is != 00, it is invalid value of register */
489 if (scratch != 0x00) { 547 if (scratch != IF_CS_SCRATCH_BOOT_OK) {
490 ret = -ENODEV; 548 ret = -ENODEV;
491 goto done; 549 goto done;
492 } 550 }
@@ -514,26 +572,26 @@ static int if_cs_prog_helper(struct if_cs_card *card)
514 572
515 /* "write the number of bytes to be sent to the I/O Command 573 /* "write the number of bytes to be sent to the I/O Command
516 * write length register" */ 574 * write length register" */
517 if_cs_write16(card, IF_CS_H_CMD_LEN, count); 575 if_cs_write16(card, IF_CS_CMD_LEN, count);
518 576
519 /* "write this to I/O Command port register as 16 bit writes */ 577 /* "write this to I/O Command port register as 16 bit writes */
520 if (count) 578 if (count)
521 if_cs_write16_rep(card, IF_CS_H_CMD, 579 if_cs_write16_rep(card, IF_CS_CMD,
522 &fw->data[sent], 580 &fw->data[sent],
523 count >> 1); 581 count >> 1);
524 582
525 /* "Assert the download over interrupt command in the Host 583 /* "Assert the download over interrupt command in the Host
526 * status register" */ 584 * status register" */
527 if_cs_write8(card, IF_CS_H_STATUS, IF_CS_H_STATUS_DNLD_OVER); 585 if_cs_write8(card, IF_CS_HOST_STATUS, IF_CS_BIT_COMMAND);
528 586
529 /* "Assert the download over interrupt command in the Card 587 /* "Assert the download over interrupt command in the Card
530 * interrupt case register" */ 588 * interrupt case register" */
531 if_cs_write16(card, IF_CS_H_INT_CAUSE, IF_CS_H_IC_DNLD_OVER); 589 if_cs_write16(card, IF_CS_HOST_INT_CAUSE, IF_CS_BIT_COMMAND);
532 590
533 /* "The host polls the Card Status register ... for 50 ms before 591 /* "The host polls the Card Status register ... for 50 ms before
534 declaring a failure */ 592 declaring a failure */
535 ret = if_cs_poll_while_fw_download(card, IF_CS_C_STATUS, 593 ret = if_cs_poll_while_fw_download(card, IF_CS_CARD_STATUS,
536 IF_CS_C_S_CMD_DNLD_RDY); 594 IF_CS_BIT_COMMAND);
537 if (ret < 0) { 595 if (ret < 0) {
538 lbs_pr_err("can't download helper at 0x%x, ret %d\n", 596 lbs_pr_err("can't download helper at 0x%x, ret %d\n",
539 sent, ret); 597 sent, ret);
@@ -575,14 +633,15 @@ static int if_cs_prog_real(struct if_cs_card *card)
575 } 633 }
576 lbs_deb_cs("fw size %td\n", fw->size); 634 lbs_deb_cs("fw size %td\n", fw->size);
577 635
578 ret = if_cs_poll_while_fw_download(card, IF_CS_C_SQ_READ_LOW, IF_CS_C_SQ_HELPER_OK); 636 ret = if_cs_poll_while_fw_download(card, IF_CS_SQ_READ_LOW,
637 IF_CS_SQ_HELPER_OK);
579 if (ret < 0) { 638 if (ret < 0) {
580 lbs_pr_err("helper firmware doesn't answer\n"); 639 lbs_pr_err("helper firmware doesn't answer\n");
581 goto err_release; 640 goto err_release;
582 } 641 }
583 642
584 for (sent = 0; sent < fw->size; sent += len) { 643 for (sent = 0; sent < fw->size; sent += len) {
585 len = if_cs_read16(card, IF_CS_C_SQ_READ_LOW); 644 len = if_cs_read16(card, IF_CS_SQ_READ_LOW);
586 if (len & 1) { 645 if (len & 1) {
587 retry++; 646 retry++;
588 lbs_pr_info("odd, need to retry this firmware block\n"); 647 lbs_pr_info("odd, need to retry this firmware block\n");
@@ -600,16 +659,16 @@ static int if_cs_prog_real(struct if_cs_card *card)
600 } 659 }
601 660
602 661
603 if_cs_write16(card, IF_CS_H_CMD_LEN, len); 662 if_cs_write16(card, IF_CS_CMD_LEN, len);
604 663
605 if_cs_write16_rep(card, IF_CS_H_CMD, 664 if_cs_write16_rep(card, IF_CS_CMD,
606 &fw->data[sent], 665 &fw->data[sent],
607 (len+1) >> 1); 666 (len+1) >> 1);
608 if_cs_write8(card, IF_CS_H_STATUS, IF_CS_H_STATUS_DNLD_OVER); 667 if_cs_write8(card, IF_CS_HOST_STATUS, IF_CS_BIT_COMMAND);
609 if_cs_write16(card, IF_CS_H_INT_CAUSE, IF_CS_H_IC_DNLD_OVER); 668 if_cs_write16(card, IF_CS_HOST_INT_CAUSE, IF_CS_BIT_COMMAND);
610 669
611 ret = if_cs_poll_while_fw_download(card, IF_CS_C_STATUS, 670 ret = if_cs_poll_while_fw_download(card, IF_CS_CARD_STATUS,
612 IF_CS_C_S_CMD_DNLD_RDY); 671 IF_CS_BIT_COMMAND);
613 if (ret < 0) { 672 if (ret < 0) {
614 lbs_pr_err("can't download firmware at 0x%x\n", sent); 673 lbs_pr_err("can't download firmware at 0x%x\n", sent);
615 goto err_release; 674 goto err_release;
@@ -806,6 +865,12 @@ static int if_cs_probe(struct pcmcia_device *p_dev)
806 p_dev->irq.AssignedIRQ, p_dev->io.BasePort1, 865 p_dev->irq.AssignedIRQ, p_dev->io.BasePort1,
807 p_dev->io.BasePort1 + p_dev->io.NumPorts1 - 1); 866 p_dev->io.BasePort1 + p_dev->io.NumPorts1 - 1);
808 867
868 /* Check if we have a current silicon */
869 if (if_cs_read8(card, IF_CS_PRODUCT_ID) < IF_CS_CF8385_B1_REV) {
870 lbs_pr_err("old chips like 8385 rev B1 aren't supported\n");
871 ret = -ENODEV;
872 goto out2;
873 }
809 874
810 /* Load the firmware early, before calling into libertas.ko */ 875 /* Load the firmware early, before calling into libertas.ko */
811 ret = if_cs_prog_helper(card); 876 ret = if_cs_prog_helper(card);
@@ -837,7 +902,7 @@ static int if_cs_probe(struct pcmcia_device *p_dev)
837 902
838 /* Clear any interrupt cause that happend while sending 903 /* Clear any interrupt cause that happend while sending
839 * firmware/initializing card */ 904 * firmware/initializing card */
840 if_cs_write16(card, IF_CS_C_INT_CAUSE, IF_CS_C_IC_MASK); 905 if_cs_write16(card, IF_CS_CARD_INT_CAUSE, IF_CS_BIT_MASK);
841 if_cs_enable_ints(card); 906 if_cs_enable_ints(card);
842 907
843 /* And finally bring the card up */ 908 /* And finally bring the card up */
diff --git a/drivers/net/wireless/libertas/if_usb.c b/drivers/net/wireless/libertas/if_usb.c
index 4dcd4092e0f0..632c291404ab 100644
--- a/drivers/net/wireless/libertas/if_usb.c
+++ b/drivers/net/wireless/libertas/if_usb.c
@@ -7,6 +7,10 @@
7#include <linux/netdevice.h> 7#include <linux/netdevice.h>
8#include <linux/usb.h> 8#include <linux/usb.h>
9 9
10#ifdef CONFIG_OLPC
11#include <asm/olpc.h>
12#endif
13
10#define DRV_NAME "usb8xxx" 14#define DRV_NAME "usb8xxx"
11 15
12#include "host.h" 16#include "host.h"
@@ -146,6 +150,14 @@ static void if_usb_fw_timeo(unsigned long priv)
146 wake_up(&cardp->fw_wq); 150 wake_up(&cardp->fw_wq);
147} 151}
148 152
153#ifdef CONFIG_OLPC
154static void if_usb_reset_olpc_card(struct lbs_private *priv)
155{
156 printk(KERN_CRIT "Resetting OLPC wireless via EC...\n");
157 olpc_ec_cmd(0x25, NULL, 0, NULL, 0);
158}
159#endif
160
149/** 161/**
150 * @brief sets the configuration values 162 * @brief sets the configuration values
151 * @param ifnum interface number 163 * @param ifnum interface number
@@ -231,6 +243,11 @@ static int if_usb_probe(struct usb_interface *intf,
231 cardp->priv->fw_ready = 1; 243 cardp->priv->fw_ready = 1;
232 244
233 priv->hw_host_to_card = if_usb_host_to_card; 245 priv->hw_host_to_card = if_usb_host_to_card;
246#ifdef CONFIG_OLPC
247 if (machine_is_olpc())
248 priv->reset_card = if_usb_reset_olpc_card;
249#endif
250
234 cardp->boot2_version = udev->descriptor.bcdDevice; 251 cardp->boot2_version = udev->descriptor.bcdDevice;
235 252
236 if_usb_submit_rx_urb(cardp); 253 if_usb_submit_rx_urb(cardp);
@@ -364,6 +381,11 @@ static int if_usb_reset_device(struct if_usb_card *cardp)
364 ret = usb_reset_device(cardp->udev); 381 ret = usb_reset_device(cardp->udev);
365 msleep(100); 382 msleep(100);
366 383
384#ifdef CONFIG_OLPC
385 if (ret && machine_is_olpc())
386 if_usb_reset_olpc_card(NULL);
387#endif
388
367 lbs_deb_leave_args(LBS_DEB_USB, "ret %d", ret); 389 lbs_deb_leave_args(LBS_DEB_USB, "ret %d", ret);
368 390
369 return ret; 391 return ret;
diff --git a/drivers/net/wireless/libertas/main.c b/drivers/net/wireless/libertas/main.c
index acfc4bfcc262..14d5d61cec4c 100644
--- a/drivers/net/wireless/libertas/main.c
+++ b/drivers/net/wireless/libertas/main.c
@@ -11,6 +11,7 @@
11#include <linux/if_arp.h> 11#include <linux/if_arp.h>
12#include <linux/kthread.h> 12#include <linux/kthread.h>
13#include <linux/kfifo.h> 13#include <linux/kfifo.h>
14#include <linux/stddef.h>
14 15
15#include <net/iw_handler.h> 16#include <net/iw_handler.h>
16#include <net/ieee80211.h> 17#include <net/ieee80211.h>
@@ -343,14 +344,15 @@ static ssize_t lbs_mesh_set(struct device *dev,
343{ 344{
344 struct lbs_private *priv = to_net_dev(dev)->priv; 345 struct lbs_private *priv = to_net_dev(dev)->priv;
345 int enable; 346 int enable;
346 int ret; 347 int ret, action = CMD_ACT_MESH_CONFIG_STOP;
347 348
348 sscanf(buf, "%x", &enable); 349 sscanf(buf, "%x", &enable);
349 enable = !!enable; 350 enable = !!enable;
350 if (enable == !!priv->mesh_dev) 351 if (enable == !!priv->mesh_dev)
351 return count; 352 return count;
352 353 if (enable)
353 ret = lbs_mesh_config(priv, enable, priv->curbssparams.channel); 354 action = CMD_ACT_MESH_CONFIG_START;
355 ret = lbs_mesh_config(priv, action, priv->curbssparams.channel);
354 if (ret) 356 if (ret)
355 return ret; 357 return ret;
356 358
@@ -446,6 +448,8 @@ static int lbs_mesh_stop(struct net_device *dev)
446 448
447 spin_unlock_irq(&priv->driver_lock); 449 spin_unlock_irq(&priv->driver_lock);
448 450
451 schedule_work(&priv->mcast_work);
452
449 lbs_deb_leave(LBS_DEB_MESH); 453 lbs_deb_leave(LBS_DEB_MESH);
450 return 0; 454 return 0;
451} 455}
@@ -467,6 +471,8 @@ static int lbs_eth_stop(struct net_device *dev)
467 netif_stop_queue(dev); 471 netif_stop_queue(dev);
468 spin_unlock_irq(&priv->driver_lock); 472 spin_unlock_irq(&priv->driver_lock);
469 473
474 schedule_work(&priv->mcast_work);
475
470 lbs_deb_leave(LBS_DEB_NET); 476 lbs_deb_leave(LBS_DEB_NET);
471 return 0; 477 return 0;
472} 478}
@@ -563,89 +569,116 @@ done:
563 return ret; 569 return ret;
564} 570}
565 571
566static int lbs_copy_multicast_address(struct lbs_private *priv, 572
567 struct net_device *dev) 573static inline int mac_in_list(unsigned char *list, int list_len,
574 unsigned char *mac)
568{ 575{
569 int i = 0; 576 while (list_len) {
570 struct dev_mc_list *mcptr = dev->mc_list; 577 if (!memcmp(list, mac, ETH_ALEN))
578 return 1;
579 list += ETH_ALEN;
580 list_len--;
581 }
582 return 0;
583}
584
585
586static int lbs_add_mcast_addrs(struct cmd_ds_mac_multicast_adr *cmd,
587 struct net_device *dev, int nr_addrs)
588{
589 int i = nr_addrs;
590 struct dev_mc_list *mc_list;
591 DECLARE_MAC_BUF(mac);
592
593 if ((dev->flags & (IFF_UP|IFF_MULTICAST)) != (IFF_UP|IFF_MULTICAST))
594 return nr_addrs;
595
596 netif_addr_lock_bh(dev);
597 for (mc_list = dev->mc_list; mc_list; mc_list = mc_list->next) {
598 if (mac_in_list(cmd->maclist, nr_addrs, mc_list->dmi_addr)) {
599 lbs_deb_net("mcast address %s:%s skipped\n", dev->name,
600 print_mac(mac, mc_list->dmi_addr));
601 continue;
602 }
571 603
572 for (i = 0; i < dev->mc_count; i++) { 604 if (i == MRVDRV_MAX_MULTICAST_LIST_SIZE)
573 memcpy(&priv->multicastlist[i], mcptr->dmi_addr, ETH_ALEN); 605 break;
574 mcptr = mcptr->next; 606 memcpy(&cmd->maclist[6*i], mc_list->dmi_addr, ETH_ALEN);
607 lbs_deb_net("mcast address %s:%s added to filter\n", dev->name,
608 print_mac(mac, mc_list->dmi_addr));
609 i++;
575 } 610 }
611 netif_addr_unlock_bh(dev);
612 if (mc_list)
613 return -EOVERFLOW;
614
576 return i; 615 return i;
577} 616}
578 617
579static void lbs_set_multicast_list(struct net_device *dev) 618static void lbs_set_mcast_worker(struct work_struct *work)
580{ 619{
581 struct lbs_private *priv = dev->priv; 620 struct lbs_private *priv = container_of(work, struct lbs_private, mcast_work);
582 int old_mac_control; 621 struct cmd_ds_mac_multicast_adr mcast_cmd;
583 DECLARE_MAC_BUF(mac); 622 int dev_flags;
623 int nr_addrs;
624 int old_mac_control = priv->mac_control;
584 625
585 lbs_deb_enter(LBS_DEB_NET); 626 lbs_deb_enter(LBS_DEB_NET);
586 627
587 old_mac_control = priv->mac_control; 628 dev_flags = priv->dev->flags;
588 629 if (priv->mesh_dev)
589 if (dev->flags & IFF_PROMISC) { 630 dev_flags |= priv->mesh_dev->flags;
590 lbs_deb_net("enable promiscuous mode\n"); 631
591 priv->mac_control |= 632 if (dev_flags & IFF_PROMISC) {
592 CMD_ACT_MAC_PROMISCUOUS_ENABLE; 633 priv->mac_control |= CMD_ACT_MAC_PROMISCUOUS_ENABLE;
593 priv->mac_control &= 634 priv->mac_control &= ~(CMD_ACT_MAC_ALL_MULTICAST_ENABLE |
594 ~(CMD_ACT_MAC_ALL_MULTICAST_ENABLE | 635 CMD_ACT_MAC_MULTICAST_ENABLE);
595 CMD_ACT_MAC_MULTICAST_ENABLE); 636 goto out_set_mac_control;
596 } else { 637 } else if (dev_flags & IFF_ALLMULTI) {
597 /* Multicast */ 638 do_allmulti:
598 priv->mac_control &= 639 priv->mac_control |= CMD_ACT_MAC_ALL_MULTICAST_ENABLE;
599 ~CMD_ACT_MAC_PROMISCUOUS_ENABLE; 640 priv->mac_control &= ~(CMD_ACT_MAC_PROMISCUOUS_ENABLE |
600 641 CMD_ACT_MAC_MULTICAST_ENABLE);
601 if (dev->flags & IFF_ALLMULTI || dev->mc_count > 642 goto out_set_mac_control;
602 MRVDRV_MAX_MULTICAST_LIST_SIZE) {
603 lbs_deb_net( "enabling all multicast\n");
604 priv->mac_control |=
605 CMD_ACT_MAC_ALL_MULTICAST_ENABLE;
606 priv->mac_control &=
607 ~CMD_ACT_MAC_MULTICAST_ENABLE;
608 } else {
609 priv->mac_control &=
610 ~CMD_ACT_MAC_ALL_MULTICAST_ENABLE;
611
612 if (!dev->mc_count) {
613 lbs_deb_net("no multicast addresses, "
614 "disabling multicast\n");
615 priv->mac_control &=
616 ~CMD_ACT_MAC_MULTICAST_ENABLE;
617 } else {
618 int i;
619
620 priv->mac_control |=
621 CMD_ACT_MAC_MULTICAST_ENABLE;
622
623 priv->nr_of_multicastmacaddr =
624 lbs_copy_multicast_address(priv, dev);
625
626 lbs_deb_net("multicast addresses: %d\n",
627 dev->mc_count);
628
629 for (i = 0; i < dev->mc_count; i++) {
630 lbs_deb_net("Multicast address %d: %s\n",
631 i, print_mac(mac,
632 priv->multicastlist[i]));
633 }
634 /* send multicast addresses to firmware */
635 lbs_prepare_and_send_command(priv,
636 CMD_MAC_MULTICAST_ADR,
637 CMD_ACT_SET, 0, 0,
638 NULL);
639 }
640 }
641 } 643 }
642 644
645 /* Once for priv->dev, again for priv->mesh_dev if it exists */
646 nr_addrs = lbs_add_mcast_addrs(&mcast_cmd, priv->dev, 0);
647 if (nr_addrs >= 0 && priv->mesh_dev)
648 nr_addrs = lbs_add_mcast_addrs(&mcast_cmd, priv->mesh_dev, nr_addrs);
649 if (nr_addrs < 0)
650 goto do_allmulti;
651
652 if (nr_addrs) {
653 int size = offsetof(struct cmd_ds_mac_multicast_adr,
654 maclist[6*nr_addrs]);
655
656 mcast_cmd.action = cpu_to_le16(CMD_ACT_SET);
657 mcast_cmd.hdr.size = cpu_to_le16(size);
658 mcast_cmd.nr_of_adrs = cpu_to_le16(nr_addrs);
659
660 lbs_cmd_async(priv, CMD_MAC_MULTICAST_ADR, &mcast_cmd.hdr, size);
661
662 priv->mac_control |= CMD_ACT_MAC_MULTICAST_ENABLE;
663 } else
664 priv->mac_control &= ~CMD_ACT_MAC_MULTICAST_ENABLE;
665
666 priv->mac_control &= ~(CMD_ACT_MAC_PROMISCUOUS_ENABLE |
667 CMD_ACT_MAC_ALL_MULTICAST_ENABLE);
668 out_set_mac_control:
643 if (priv->mac_control != old_mac_control) 669 if (priv->mac_control != old_mac_control)
644 lbs_set_mac_control(priv); 670 lbs_set_mac_control(priv);
645 671
646 lbs_deb_leave(LBS_DEB_NET); 672 lbs_deb_leave(LBS_DEB_NET);
647} 673}
648 674
675static void lbs_set_multicast_list(struct net_device *dev)
676{
677 struct lbs_private *priv = dev->priv;
678
679 schedule_work(&priv->mcast_work);
680}
681
649/** 682/**
650 * @brief This function handles the major jobs in the LBS driver. 683 * @brief This function handles the major jobs in the LBS driver.
651 * It handles all events generated by firmware, RX data received 684 * It handles all events generated by firmware, RX data received
@@ -689,20 +722,20 @@ static int lbs_thread(void *data)
689 shouldsleep = 1; /* Something is en route to the device already */ 722 shouldsleep = 1; /* Something is en route to the device already */
690 else if (priv->tx_pending_len > 0) 723 else if (priv->tx_pending_len > 0)
691 shouldsleep = 0; /* We've a packet to send */ 724 shouldsleep = 0; /* We've a packet to send */
725 else if (priv->resp_len[priv->resp_idx])
726 shouldsleep = 0; /* We have a command response */
692 else if (priv->cur_cmd) 727 else if (priv->cur_cmd)
693 shouldsleep = 1; /* Can't send a command; one already running */ 728 shouldsleep = 1; /* Can't send a command; one already running */
694 else if (!list_empty(&priv->cmdpendingq)) 729 else if (!list_empty(&priv->cmdpendingq))
695 shouldsleep = 0; /* We have a command to send */ 730 shouldsleep = 0; /* We have a command to send */
696 else if (__kfifo_len(priv->event_fifo)) 731 else if (__kfifo_len(priv->event_fifo))
697 shouldsleep = 0; /* We have an event to process */ 732 shouldsleep = 0; /* We have an event to process */
698 else if (priv->resp_len[priv->resp_idx])
699 shouldsleep = 0; /* We have a command response */
700 else 733 else
701 shouldsleep = 1; /* No command */ 734 shouldsleep = 1; /* No command */
702 735
703 if (shouldsleep) { 736 if (shouldsleep) {
704 lbs_deb_thread("sleeping, connect_status %d, " 737 lbs_deb_thread("sleeping, connect_status %d, "
705 "ps_mode %d, ps_state %d\n", 738 "psmode %d, psstate %d\n",
706 priv->connect_status, 739 priv->connect_status,
707 priv->psmode, priv->psstate); 740 priv->psmode, priv->psstate);
708 spin_unlock_irq(&priv->driver_lock); 741 spin_unlock_irq(&priv->driver_lock);
@@ -749,16 +782,21 @@ static int lbs_thread(void *data)
749 if (priv->cmd_timed_out && priv->cur_cmd) { 782 if (priv->cmd_timed_out && priv->cur_cmd) {
750 struct cmd_ctrl_node *cmdnode = priv->cur_cmd; 783 struct cmd_ctrl_node *cmdnode = priv->cur_cmd;
751 784
752 if (++priv->nr_retries > 10) { 785 if (++priv->nr_retries > 3) {
753 lbs_pr_info("Excessive timeouts submitting command %x\n", 786 lbs_pr_info("Excessive timeouts submitting "
754 le16_to_cpu(cmdnode->cmdbuf->command)); 787 "command 0x%04x\n",
788 le16_to_cpu(cmdnode->cmdbuf->command));
755 lbs_complete_command(priv, cmdnode, -ETIMEDOUT); 789 lbs_complete_command(priv, cmdnode, -ETIMEDOUT);
756 priv->nr_retries = 0; 790 priv->nr_retries = 0;
791 if (priv->reset_card)
792 priv->reset_card(priv);
757 } else { 793 } else {
758 priv->cur_cmd = NULL; 794 priv->cur_cmd = NULL;
759 priv->dnld_sent = DNLD_RES_RECEIVED; 795 priv->dnld_sent = DNLD_RES_RECEIVED;
760 lbs_pr_info("requeueing command %x due to timeout (#%d)\n", 796 lbs_pr_info("requeueing command 0x%04x due "
761 le16_to_cpu(cmdnode->cmdbuf->command), priv->nr_retries); 797 "to timeout (#%d)\n",
798 le16_to_cpu(cmdnode->cmdbuf->command),
799 priv->nr_retries);
762 800
763 /* Stick it back at the _top_ of the pending queue 801 /* Stick it back at the _top_ of the pending queue
764 for immediate resubmission */ 802 for immediate resubmission */
@@ -890,7 +928,7 @@ int lbs_suspend(struct lbs_private *priv)
890} 928}
891EXPORT_SYMBOL_GPL(lbs_suspend); 929EXPORT_SYMBOL_GPL(lbs_suspend);
892 930
893int lbs_resume(struct lbs_private *priv) 931void lbs_resume(struct lbs_private *priv)
894{ 932{
895 lbs_deb_enter(LBS_DEB_FW); 933 lbs_deb_enter(LBS_DEB_FW);
896 934
@@ -906,7 +944,6 @@ int lbs_resume(struct lbs_private *priv)
906 netif_device_attach(priv->mesh_dev); 944 netif_device_attach(priv->mesh_dev);
907 945
908 lbs_deb_leave(LBS_DEB_FW); 946 lbs_deb_leave(LBS_DEB_FW);
909 return 0;
910} 947}
911EXPORT_SYMBOL_GPL(lbs_resume); 948EXPORT_SYMBOL_GPL(lbs_resume);
912 949
@@ -929,20 +966,10 @@ static int lbs_setup_firmware(struct lbs_private *priv)
929 */ 966 */
930 memset(priv->current_addr, 0xff, ETH_ALEN); 967 memset(priv->current_addr, 0xff, ETH_ALEN);
931 ret = lbs_update_hw_spec(priv); 968 ret = lbs_update_hw_spec(priv);
932 if (ret) { 969 if (ret)
933 ret = -1;
934 goto done; 970 goto done;
935 }
936 971
937 lbs_set_mac_control(priv); 972 lbs_set_mac_control(priv);
938
939 ret = lbs_get_data_rate(priv);
940 if (ret < 0) {
941 ret = -1;
942 goto done;
943 }
944
945 ret = 0;
946done: 973done:
947 lbs_deb_leave_args(LBS_DEB_FW, "ret %d", ret); 974 lbs_deb_leave_args(LBS_DEB_FW, "ret %d", ret);
948 return ret; 975 return ret;
@@ -960,12 +987,11 @@ static void command_timer_fn(unsigned long data)
960 lbs_deb_enter(LBS_DEB_CMD); 987 lbs_deb_enter(LBS_DEB_CMD);
961 spin_lock_irqsave(&priv->driver_lock, flags); 988 spin_lock_irqsave(&priv->driver_lock, flags);
962 989
963 if (!priv->cur_cmd) { 990 if (!priv->cur_cmd)
964 lbs_pr_info("Command timer expired; no pending command\n");
965 goto out; 991 goto out;
966 }
967 992
968 lbs_pr_info("Command %x timed out\n", le16_to_cpu(priv->cur_cmd->cmdbuf->command)); 993 lbs_pr_info("command 0x%04x timed out\n",
994 le16_to_cpu(priv->cur_cmd->cmdbuf->command));
969 995
970 priv->cmd_timed_out = 1; 996 priv->cmd_timed_out = 1;
971 wake_up_interruptible(&priv->waitq); 997 wake_up_interruptible(&priv->waitq);
@@ -1019,7 +1045,7 @@ static int lbs_init_adapter(struct lbs_private *priv)
1019 priv->curbssparams.channel = DEFAULT_AD_HOC_CHANNEL; 1045 priv->curbssparams.channel = DEFAULT_AD_HOC_CHANNEL;
1020 priv->mac_control = CMD_ACT_MAC_RX_ON | CMD_ACT_MAC_TX_ON; 1046 priv->mac_control = CMD_ACT_MAC_RX_ON | CMD_ACT_MAC_TX_ON;
1021 priv->radioon = RADIO_ON; 1047 priv->radioon = RADIO_ON;
1022 priv->auto_rate = 1; 1048 priv->enablehwauto = 1;
1023 priv->capability = WLAN_CAPABILITY_SHORT_PREAMBLE; 1049 priv->capability = WLAN_CAPABILITY_SHORT_PREAMBLE;
1024 priv->psmode = LBS802_11POWERMODECAM; 1050 priv->psmode = LBS802_11POWERMODECAM;
1025 priv->psstate = PS_STATE_FULL_POWER; 1051 priv->psstate = PS_STATE_FULL_POWER;
@@ -1134,6 +1160,7 @@ struct lbs_private *lbs_add_card(void *card, struct device *dmdev)
1134 priv->work_thread = create_singlethread_workqueue("lbs_worker"); 1160 priv->work_thread = create_singlethread_workqueue("lbs_worker");
1135 INIT_DELAYED_WORK(&priv->assoc_work, lbs_association_worker); 1161 INIT_DELAYED_WORK(&priv->assoc_work, lbs_association_worker);
1136 INIT_DELAYED_WORK(&priv->scan_work, lbs_scan_worker); 1162 INIT_DELAYED_WORK(&priv->scan_work, lbs_scan_worker);
1163 INIT_WORK(&priv->mcast_work, lbs_set_mcast_worker);
1137 INIT_WORK(&priv->sync_channel, lbs_sync_channel_worker); 1164 INIT_WORK(&priv->sync_channel, lbs_sync_channel_worker);
1138 1165
1139 sprintf(priv->mesh_ssid, "mesh"); 1166 sprintf(priv->mesh_ssid, "mesh");
@@ -1156,7 +1183,7 @@ done:
1156EXPORT_SYMBOL_GPL(lbs_add_card); 1183EXPORT_SYMBOL_GPL(lbs_add_card);
1157 1184
1158 1185
1159int lbs_remove_card(struct lbs_private *priv) 1186void lbs_remove_card(struct lbs_private *priv)
1160{ 1187{
1161 struct net_device *dev = priv->dev; 1188 struct net_device *dev = priv->dev;
1162 union iwreq_data wrqu; 1189 union iwreq_data wrqu;
@@ -1168,8 +1195,9 @@ int lbs_remove_card(struct lbs_private *priv)
1168 1195
1169 dev = priv->dev; 1196 dev = priv->dev;
1170 1197
1171 cancel_delayed_work(&priv->scan_work); 1198 cancel_delayed_work_sync(&priv->scan_work);
1172 cancel_delayed_work(&priv->assoc_work); 1199 cancel_delayed_work_sync(&priv->assoc_work);
1200 cancel_work_sync(&priv->mcast_work);
1173 destroy_workqueue(priv->work_thread); 1201 destroy_workqueue(priv->work_thread);
1174 1202
1175 if (priv->psmode == LBS802_11POWERMODEMAX_PSP) { 1203 if (priv->psmode == LBS802_11POWERMODEMAX_PSP) {
@@ -1191,7 +1219,6 @@ int lbs_remove_card(struct lbs_private *priv)
1191 free_netdev(dev); 1219 free_netdev(dev);
1192 1220
1193 lbs_deb_leave(LBS_DEB_MAIN); 1221 lbs_deb_leave(LBS_DEB_MAIN);
1194 return 0;
1195} 1222}
1196EXPORT_SYMBOL_GPL(lbs_remove_card); 1223EXPORT_SYMBOL_GPL(lbs_remove_card);
1197 1224
@@ -1236,9 +1263,11 @@ int lbs_start_card(struct lbs_private *priv)
1236 useful */ 1263 useful */
1237 1264
1238 priv->mesh_tlv = 0x100 + 291; 1265 priv->mesh_tlv = 0x100 + 291;
1239 if (lbs_mesh_config(priv, 1, priv->curbssparams.channel)) { 1266 if (lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START,
1267 priv->curbssparams.channel)) {
1240 priv->mesh_tlv = 0x100 + 37; 1268 priv->mesh_tlv = 0x100 + 37;
1241 if (lbs_mesh_config(priv, 1, priv->curbssparams.channel)) 1269 if (lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START,
1270 priv->curbssparams.channel))
1242 priv->mesh_tlv = 0; 1271 priv->mesh_tlv = 0;
1243 } 1272 }
1244 if (priv->mesh_tlv) { 1273 if (priv->mesh_tlv) {
@@ -1262,24 +1291,28 @@ done:
1262EXPORT_SYMBOL_GPL(lbs_start_card); 1291EXPORT_SYMBOL_GPL(lbs_start_card);
1263 1292
1264 1293
1265int lbs_stop_card(struct lbs_private *priv) 1294void lbs_stop_card(struct lbs_private *priv)
1266{ 1295{
1267 struct net_device *dev = priv->dev; 1296 struct net_device *dev = priv->dev;
1268 int ret = -1;
1269 struct cmd_ctrl_node *cmdnode; 1297 struct cmd_ctrl_node *cmdnode;
1270 unsigned long flags; 1298 unsigned long flags;
1271 1299
1272 lbs_deb_enter(LBS_DEB_MAIN); 1300 lbs_deb_enter(LBS_DEB_MAIN);
1273 1301
1302 if (!priv)
1303 goto out;
1304
1274 netif_stop_queue(priv->dev); 1305 netif_stop_queue(priv->dev);
1275 netif_carrier_off(priv->dev); 1306 netif_carrier_off(priv->dev);
1276 1307
1277 lbs_debugfs_remove_one(priv); 1308 lbs_debugfs_remove_one(priv);
1278 device_remove_file(&dev->dev, &dev_attr_lbs_rtap); 1309 device_remove_file(&dev->dev, &dev_attr_lbs_rtap);
1279 if (priv->mesh_tlv) 1310 if (priv->mesh_tlv) {
1280 device_remove_file(&dev->dev, &dev_attr_lbs_mesh); 1311 device_remove_file(&dev->dev, &dev_attr_lbs_mesh);
1312 }
1281 1313
1282 /* Flush pending command nodes */ 1314 /* Flush pending command nodes */
1315 del_timer_sync(&priv->command_timer);
1283 spin_lock_irqsave(&priv->driver_lock, flags); 1316 spin_lock_irqsave(&priv->driver_lock, flags);
1284 list_for_each_entry(cmdnode, &priv->cmdpendingq, list) { 1317 list_for_each_entry(cmdnode, &priv->cmdpendingq, list) {
1285 cmdnode->result = -ENOENT; 1318 cmdnode->result = -ENOENT;
@@ -1290,8 +1323,8 @@ int lbs_stop_card(struct lbs_private *priv)
1290 1323
1291 unregister_netdev(dev); 1324 unregister_netdev(dev);
1292 1325
1293 lbs_deb_leave_args(LBS_DEB_MAIN, "ret %d", ret); 1326out:
1294 return ret; 1327 lbs_deb_leave(LBS_DEB_MAIN);
1295} 1328}
1296EXPORT_SYMBOL_GPL(lbs_stop_card); 1329EXPORT_SYMBOL_GPL(lbs_stop_card);
1297 1330
@@ -1332,6 +1365,8 @@ static int lbs_add_mesh(struct lbs_private *priv)
1332#ifdef WIRELESS_EXT 1365#ifdef WIRELESS_EXT
1333 mesh_dev->wireless_handlers = (struct iw_handler_def *)&mesh_handler_def; 1366 mesh_dev->wireless_handlers = (struct iw_handler_def *)&mesh_handler_def;
1334#endif 1367#endif
1368 mesh_dev->flags |= IFF_BROADCAST | IFF_MULTICAST;
1369 mesh_dev->set_multicast_list = lbs_set_multicast_list;
1335 /* Register virtual mesh interface */ 1370 /* Register virtual mesh interface */
1336 ret = register_netdev(mesh_dev); 1371 ret = register_netdev(mesh_dev);
1337 if (ret) { 1372 if (ret) {
@@ -1343,6 +1378,8 @@ static int lbs_add_mesh(struct lbs_private *priv)
1343 if (ret) 1378 if (ret)
1344 goto err_unregister; 1379 goto err_unregister;
1345 1380
1381 lbs_persist_config_init(mesh_dev);
1382
1346 /* Everything successful */ 1383 /* Everything successful */
1347 ret = 0; 1384 ret = 0;
1348 goto done; 1385 goto done;
@@ -1369,8 +1406,9 @@ static void lbs_remove_mesh(struct lbs_private *priv)
1369 1406
1370 lbs_deb_enter(LBS_DEB_MESH); 1407 lbs_deb_enter(LBS_DEB_MESH);
1371 netif_stop_queue(mesh_dev); 1408 netif_stop_queue(mesh_dev);
1372 netif_carrier_off(priv->mesh_dev); 1409 netif_carrier_off(mesh_dev);
1373 sysfs_remove_group(&(mesh_dev->dev.kobj), &lbs_mesh_attr_group); 1410 sysfs_remove_group(&(mesh_dev->dev.kobj), &lbs_mesh_attr_group);
1411 lbs_persist_config_remove(mesh_dev);
1374 unregister_netdev(mesh_dev); 1412 unregister_netdev(mesh_dev);
1375 priv->mesh_dev = NULL; 1413 priv->mesh_dev = NULL;
1376 free_netdev(mesh_dev); 1414 free_netdev(mesh_dev);
@@ -1533,10 +1571,11 @@ static void lbs_remove_rtap(struct lbs_private *priv)
1533{ 1571{
1534 lbs_deb_enter(LBS_DEB_MAIN); 1572 lbs_deb_enter(LBS_DEB_MAIN);
1535 if (priv->rtap_net_dev == NULL) 1573 if (priv->rtap_net_dev == NULL)
1536 return; 1574 goto out;
1537 unregister_netdev(priv->rtap_net_dev); 1575 unregister_netdev(priv->rtap_net_dev);
1538 free_netdev(priv->rtap_net_dev); 1576 free_netdev(priv->rtap_net_dev);
1539 priv->rtap_net_dev = NULL; 1577 priv->rtap_net_dev = NULL;
1578out:
1540 lbs_deb_leave(LBS_DEB_MAIN); 1579 lbs_deb_leave(LBS_DEB_MAIN);
1541} 1580}
1542 1581
@@ -1563,7 +1602,6 @@ static int lbs_add_rtap(struct lbs_private *priv)
1563 rtap_dev->stop = lbs_rtap_stop; 1602 rtap_dev->stop = lbs_rtap_stop;
1564 rtap_dev->get_stats = lbs_rtap_get_stats; 1603 rtap_dev->get_stats = lbs_rtap_get_stats;
1565 rtap_dev->hard_start_xmit = lbs_rtap_hard_start_xmit; 1604 rtap_dev->hard_start_xmit = lbs_rtap_hard_start_xmit;
1566 rtap_dev->set_multicast_list = lbs_set_multicast_list;
1567 rtap_dev->priv = priv; 1605 rtap_dev->priv = priv;
1568 SET_NETDEV_DEV(rtap_dev, priv->dev->dev.parent); 1606 SET_NETDEV_DEV(rtap_dev, priv->dev->dev.parent);
1569 1607
diff --git a/drivers/net/wireless/libertas/persistcfg.c b/drivers/net/wireless/libertas/persistcfg.c
new file mode 100644
index 000000000000..6d0ff8decaf7
--- /dev/null
+++ b/drivers/net/wireless/libertas/persistcfg.c
@@ -0,0 +1,453 @@
1#include <linux/moduleparam.h>
2#include <linux/delay.h>
3#include <linux/etherdevice.h>
4#include <linux/netdevice.h>
5#include <linux/if_arp.h>
6#include <linux/kthread.h>
7#include <linux/kfifo.h>
8
9#include "host.h"
10#include "decl.h"
11#include "dev.h"
12#include "wext.h"
13#include "debugfs.h"
14#include "scan.h"
15#include "assoc.h"
16#include "cmd.h"
17
18static int mesh_get_default_parameters(struct device *dev,
19 struct mrvl_mesh_defaults *defs)
20{
21 struct lbs_private *priv = to_net_dev(dev)->priv;
22 struct cmd_ds_mesh_config cmd;
23 int ret;
24
25 memset(&cmd, 0, sizeof(struct cmd_ds_mesh_config));
26 ret = lbs_mesh_config_send(priv, &cmd, CMD_ACT_MESH_CONFIG_GET,
27 CMD_TYPE_MESH_GET_DEFAULTS);
28
29 if (ret)
30 return -EOPNOTSUPP;
31
32 memcpy(defs, &cmd.data[0], sizeof(struct mrvl_mesh_defaults));
33
34 return 0;
35}
36
37/**
38 * @brief Get function for sysfs attribute bootflag
39 */
40static ssize_t bootflag_get(struct device *dev,
41 struct device_attribute *attr, char *buf)
42{
43 struct mrvl_mesh_defaults defs;
44 int ret;
45
46 ret = mesh_get_default_parameters(dev, &defs);
47
48 if (ret)
49 return ret;
50
51 return snprintf(buf, 12, "0x%x\n", le32_to_cpu(defs.bootflag));
52}
53
54/**
55 * @brief Set function for sysfs attribute bootflag
56 */
57static ssize_t bootflag_set(struct device *dev, struct device_attribute *attr,
58 const char *buf, size_t count)
59{
60 struct lbs_private *priv = to_net_dev(dev)->priv;
61 struct cmd_ds_mesh_config cmd;
62 uint32_t datum;
63 int ret;
64
65 memset(&cmd, 0, sizeof(cmd));
66 ret = sscanf(buf, "%x", &datum);
67 if (ret != 1)
68 return -EINVAL;
69
70 *((__le32 *)&cmd.data[0]) = cpu_to_le32(!!datum);
71 cmd.length = cpu_to_le16(sizeof(uint32_t));
72 ret = lbs_mesh_config_send(priv, &cmd, CMD_ACT_MESH_CONFIG_SET,
73 CMD_TYPE_MESH_SET_BOOTFLAG);
74 if (ret)
75 return ret;
76
77 return strlen(buf);
78}
79
80/**
81 * @brief Get function for sysfs attribute boottime
82 */
83static ssize_t boottime_get(struct device *dev,
84 struct device_attribute *attr, char *buf)
85{
86 struct mrvl_mesh_defaults defs;
87 int ret;
88
89 ret = mesh_get_default_parameters(dev, &defs);
90
91 if (ret)
92 return ret;
93
94 return snprintf(buf, 12, "0x%x\n", defs.boottime);
95}
96
97/**
98 * @brief Set function for sysfs attribute boottime
99 */
100static ssize_t boottime_set(struct device *dev,
101 struct device_attribute *attr, const char *buf, size_t count)
102{
103 struct lbs_private *priv = to_net_dev(dev)->priv;
104 struct cmd_ds_mesh_config cmd;
105 uint32_t datum;
106 int ret;
107
108 memset(&cmd, 0, sizeof(cmd));
109 ret = sscanf(buf, "%x", &datum);
110 if (ret != 1)
111 return -EINVAL;
112
113 /* A too small boot time will result in the device booting into
114 * standalone (no-host) mode before the host can take control of it,
115 * so the change will be hard to revert. This may be a desired
116 * feature (e.g to configure a very fast boot time for devices that
117 * will not be attached to a host), but dangerous. So I'm enforcing a
118 * lower limit of 20 seconds: remove and recompile the driver if this
119 * does not work for you.
120 */
121 datum = (datum < 20) ? 20 : datum;
122 cmd.data[0] = datum;
123 cmd.length = cpu_to_le16(sizeof(uint8_t));
124 ret = lbs_mesh_config_send(priv, &cmd, CMD_ACT_MESH_CONFIG_SET,
125 CMD_TYPE_MESH_SET_BOOTTIME);
126 if (ret)
127 return ret;
128
129 return strlen(buf);
130}
131
132/**
133 * @brief Get function for sysfs attribute channel
134 */
135static ssize_t channel_get(struct device *dev,
136 struct device_attribute *attr, char *buf)
137{
138 struct mrvl_mesh_defaults defs;
139 int ret;
140
141 ret = mesh_get_default_parameters(dev, &defs);
142
143 if (ret)
144 return ret;
145
146 return snprintf(buf, 12, "0x%x\n", le16_to_cpu(defs.channel));
147}
148
149/**
150 * @brief Set function for sysfs attribute channel
151 */
152static ssize_t channel_set(struct device *dev, struct device_attribute *attr,
153 const char *buf, size_t count)
154{
155 struct lbs_private *priv = to_net_dev(dev)->priv;
156 struct cmd_ds_mesh_config cmd;
157 uint16_t datum;
158 int ret;
159
160 memset(&cmd, 0, sizeof(cmd));
161 ret = sscanf(buf, "%hx", &datum);
162 if (ret != 1 || datum < 1 || datum > 11)
163 return -EINVAL;
164
165 *((__le16 *)&cmd.data[0]) = cpu_to_le16(datum);
166 cmd.length = cpu_to_le16(sizeof(uint16_t));
167 ret = lbs_mesh_config_send(priv, &cmd, CMD_ACT_MESH_CONFIG_SET,
168 CMD_TYPE_MESH_SET_DEF_CHANNEL);
169 if (ret)
170 return ret;
171
172 return strlen(buf);
173}
174
175/**
176 * @brief Get function for sysfs attribute mesh_id
177 */
178static ssize_t mesh_id_get(struct device *dev, struct device_attribute *attr,
179 char *buf)
180{
181 struct mrvl_mesh_defaults defs;
182 int maxlen;
183 int ret;
184
185 ret = mesh_get_default_parameters(dev, &defs);
186
187 if (ret)
188 return ret;
189
190 if (defs.meshie.val.mesh_id_len > IW_ESSID_MAX_SIZE) {
191 lbs_pr_err("inconsistent mesh ID length");
192 defs.meshie.val.mesh_id_len = IW_ESSID_MAX_SIZE;
193 }
194
195 /* SSID not null terminated: reserve room for \0 + \n */
196 maxlen = defs.meshie.val.mesh_id_len + 2;
197 maxlen = (PAGE_SIZE > maxlen) ? maxlen : PAGE_SIZE;
198
199 defs.meshie.val.mesh_id[defs.meshie.val.mesh_id_len] = '\0';
200
201 return snprintf(buf, maxlen, "%s\n", defs.meshie.val.mesh_id);
202}
203
204/**
205 * @brief Set function for sysfs attribute mesh_id
206 */
207static ssize_t mesh_id_set(struct device *dev, struct device_attribute *attr,
208 const char *buf, size_t count)
209{
210 struct cmd_ds_mesh_config cmd;
211 struct mrvl_mesh_defaults defs;
212 struct mrvl_meshie *ie;
213 struct lbs_private *priv = to_net_dev(dev)->priv;
214 int len;
215 int ret;
216
217 if (count < 2 || count > IW_ESSID_MAX_SIZE + 1)
218 return -EINVAL;
219
220 memset(&cmd, 0, sizeof(struct cmd_ds_mesh_config));
221 ie = (struct mrvl_meshie *) &cmd.data[0];
222
223 /* fetch all other Information Element parameters */
224 ret = mesh_get_default_parameters(dev, &defs);
225
226 cmd.length = cpu_to_le16(sizeof(struct mrvl_meshie));
227
228 /* transfer IE elements */
229 memcpy(ie, &defs.meshie, sizeof(struct mrvl_meshie));
230
231 len = count - 1;
232 memcpy(ie->val.mesh_id, buf, len);
233 /* SSID len */
234 ie->val.mesh_id_len = len;
235 /* IE len */
236 ie->hdr.len = sizeof(struct mrvl_meshie_val) - IW_ESSID_MAX_SIZE + len;
237
238 ret = lbs_mesh_config_send(priv, &cmd, CMD_ACT_MESH_CONFIG_SET,
239 CMD_TYPE_MESH_SET_MESH_IE);
240 if (ret)
241 return ret;
242
243 return strlen(buf);
244}
245
246/**
247 * @brief Get function for sysfs attribute protocol_id
248 */
249static ssize_t protocol_id_get(struct device *dev,
250 struct device_attribute *attr, char *buf)
251{
252 struct mrvl_mesh_defaults defs;
253 int ret;
254
255 ret = mesh_get_default_parameters(dev, &defs);
256
257 if (ret)
258 return ret;
259
260 return snprintf(buf, 5, "%d\n", defs.meshie.val.active_protocol_id);
261}
262
263/**
264 * @brief Set function for sysfs attribute protocol_id
265 */
266static ssize_t protocol_id_set(struct device *dev,
267 struct device_attribute *attr, const char *buf, size_t count)
268{
269 struct cmd_ds_mesh_config cmd;
270 struct mrvl_mesh_defaults defs;
271 struct mrvl_meshie *ie;
272 struct lbs_private *priv = to_net_dev(dev)->priv;
273 uint32_t datum;
274 int ret;
275
276 memset(&cmd, 0, sizeof(cmd));
277 ret = sscanf(buf, "%x", &datum);
278 if (ret != 1)
279 return -EINVAL;
280
281 /* fetch all other Information Element parameters */
282 ret = mesh_get_default_parameters(dev, &defs);
283
284 cmd.length = cpu_to_le16(sizeof(struct mrvl_meshie));
285
286 /* transfer IE elements */
287 ie = (struct mrvl_meshie *) &cmd.data[0];
288 memcpy(ie, &defs.meshie, sizeof(struct mrvl_meshie));
289 /* update protocol id */
290 ie->val.active_protocol_id = datum;
291
292 ret = lbs_mesh_config_send(priv, &cmd, CMD_ACT_MESH_CONFIG_SET,
293 CMD_TYPE_MESH_SET_MESH_IE);
294 if (ret)
295 return ret;
296
297 return strlen(buf);
298}
299
300/**
301 * @brief Get function for sysfs attribute metric_id
302 */
303static ssize_t metric_id_get(struct device *dev,
304 struct device_attribute *attr, char *buf)
305{
306 struct mrvl_mesh_defaults defs;
307 int ret;
308
309 ret = mesh_get_default_parameters(dev, &defs);
310
311 if (ret)
312 return ret;
313
314 return snprintf(buf, 5, "%d\n", defs.meshie.val.active_metric_id);
315}
316
317/**
318 * @brief Set function for sysfs attribute metric_id
319 */
320static ssize_t metric_id_set(struct device *dev, struct device_attribute *attr,
321 const char *buf, size_t count)
322{
323 struct cmd_ds_mesh_config cmd;
324 struct mrvl_mesh_defaults defs;
325 struct mrvl_meshie *ie;
326 struct lbs_private *priv = to_net_dev(dev)->priv;
327 uint32_t datum;
328 int ret;
329
330 memset(&cmd, 0, sizeof(cmd));
331 ret = sscanf(buf, "%x", &datum);
332 if (ret != 1)
333 return -EINVAL;
334
335 /* fetch all other Information Element parameters */
336 ret = mesh_get_default_parameters(dev, &defs);
337
338 cmd.length = cpu_to_le16(sizeof(struct mrvl_meshie));
339
340 /* transfer IE elements */
341 ie = (struct mrvl_meshie *) &cmd.data[0];
342 memcpy(ie, &defs.meshie, sizeof(struct mrvl_meshie));
343 /* update metric id */
344 ie->val.active_metric_id = datum;
345
346 ret = lbs_mesh_config_send(priv, &cmd, CMD_ACT_MESH_CONFIG_SET,
347 CMD_TYPE_MESH_SET_MESH_IE);
348 if (ret)
349 return ret;
350
351 return strlen(buf);
352}
353
354/**
355 * @brief Get function for sysfs attribute capability
356 */
357static ssize_t capability_get(struct device *dev,
358 struct device_attribute *attr, char *buf)
359{
360 struct mrvl_mesh_defaults defs;
361 int ret;
362
363 ret = mesh_get_default_parameters(dev, &defs);
364
365 if (ret)
366 return ret;
367
368 return snprintf(buf, 5, "%d\n", defs.meshie.val.mesh_capability);
369}
370
371/**
372 * @brief Set function for sysfs attribute capability
373 */
374static ssize_t capability_set(struct device *dev, struct device_attribute *attr,
375 const char *buf, size_t count)
376{
377 struct cmd_ds_mesh_config cmd;
378 struct mrvl_mesh_defaults defs;
379 struct mrvl_meshie *ie;
380 struct lbs_private *priv = to_net_dev(dev)->priv;
381 uint32_t datum;
382 int ret;
383
384 memset(&cmd, 0, sizeof(cmd));
385 ret = sscanf(buf, "%x", &datum);
386 if (ret != 1)
387 return -EINVAL;
388
389 /* fetch all other Information Element parameters */
390 ret = mesh_get_default_parameters(dev, &defs);
391
392 cmd.length = cpu_to_le16(sizeof(struct mrvl_meshie));
393
394 /* transfer IE elements */
395 ie = (struct mrvl_meshie *) &cmd.data[0];
396 memcpy(ie, &defs.meshie, sizeof(struct mrvl_meshie));
397 /* update value */
398 ie->val.mesh_capability = datum;
399
400 ret = lbs_mesh_config_send(priv, &cmd, CMD_ACT_MESH_CONFIG_SET,
401 CMD_TYPE_MESH_SET_MESH_IE);
402 if (ret)
403 return ret;
404
405 return strlen(buf);
406}
407
408
409static DEVICE_ATTR(bootflag, 0644, bootflag_get, bootflag_set);
410static DEVICE_ATTR(boottime, 0644, boottime_get, boottime_set);
411static DEVICE_ATTR(channel, 0644, channel_get, channel_set);
412static DEVICE_ATTR(mesh_id, 0644, mesh_id_get, mesh_id_set);
413static DEVICE_ATTR(protocol_id, 0644, protocol_id_get, protocol_id_set);
414static DEVICE_ATTR(metric_id, 0644, metric_id_get, metric_id_set);
415static DEVICE_ATTR(capability, 0644, capability_get, capability_set);
416
417static struct attribute *boot_opts_attrs[] = {
418 &dev_attr_bootflag.attr,
419 &dev_attr_boottime.attr,
420 &dev_attr_channel.attr,
421 NULL
422};
423
424static struct attribute_group boot_opts_group = {
425 .name = "boot_options",
426 .attrs = boot_opts_attrs,
427};
428
429static struct attribute *mesh_ie_attrs[] = {
430 &dev_attr_mesh_id.attr,
431 &dev_attr_protocol_id.attr,
432 &dev_attr_metric_id.attr,
433 &dev_attr_capability.attr,
434 NULL
435};
436
437static struct attribute_group mesh_ie_group = {
438 .name = "mesh_ie",
439 .attrs = mesh_ie_attrs,
440};
441
442void lbs_persist_config_init(struct net_device *dev)
443{
444 int ret;
445 ret = sysfs_create_group(&(dev->dev.kobj), &boot_opts_group);
446 ret = sysfs_create_group(&(dev->dev.kobj), &mesh_ie_group);
447}
448
449void lbs_persist_config_remove(struct net_device *dev)
450{
451 sysfs_remove_group(&(dev->dev.kobj), &boot_opts_group);
452 sysfs_remove_group(&(dev->dev.kobj), &mesh_ie_group);
453}
diff --git a/drivers/net/wireless/libertas/rx.c b/drivers/net/wireless/libertas/rx.c
index 05af7316f698..5749f22b296f 100644
--- a/drivers/net/wireless/libertas/rx.c
+++ b/drivers/net/wireless/libertas/rx.c
@@ -237,7 +237,7 @@ int lbs_process_rxed_packet(struct lbs_private *priv, struct sk_buff *skb)
237 /* Take the data rate from the rxpd structure 237 /* Take the data rate from the rxpd structure
238 * only if the rate is auto 238 * only if the rate is auto
239 */ 239 */
240 if (priv->auto_rate) 240 if (priv->enablehwauto)
241 priv->cur_rate = lbs_fw_index_to_data_rate(p_rx_pd->rx_rate); 241 priv->cur_rate = lbs_fw_index_to_data_rate(p_rx_pd->rx_rate);
242 242
243 lbs_compute_rssi(priv, p_rx_pd); 243 lbs_compute_rssi(priv, p_rx_pd);
@@ -383,7 +383,7 @@ static int process_rxed_802_11_packet(struct lbs_private *priv,
383 /* Take the data rate from the rxpd structure 383 /* Take the data rate from the rxpd structure
384 * only if the rate is auto 384 * only if the rate is auto
385 */ 385 */
386 if (priv->auto_rate) 386 if (priv->enablehwauto)
387 priv->cur_rate = lbs_fw_index_to_data_rate(prxpd->rx_rate); 387 priv->cur_rate = lbs_fw_index_to_data_rate(prxpd->rx_rate);
388 388
389 lbs_compute_rssi(priv, prxpd); 389 lbs_compute_rssi(priv, prxpd);
diff --git a/drivers/net/wireless/libertas/scan.c b/drivers/net/wireless/libertas/scan.c
index 387d4878af2f..4b274562f965 100644
--- a/drivers/net/wireless/libertas/scan.c
+++ b/drivers/net/wireless/libertas/scan.c
@@ -776,8 +776,9 @@ out:
776#define MAX_CUSTOM_LEN 64 776#define MAX_CUSTOM_LEN 64
777 777
778static inline char *lbs_translate_scan(struct lbs_private *priv, 778static inline char *lbs_translate_scan(struct lbs_private *priv,
779 char *start, char *stop, 779 struct iw_request_info *info,
780 struct bss_descriptor *bss) 780 char *start, char *stop,
781 struct bss_descriptor *bss)
781{ 782{
782 struct chan_freq_power *cfp; 783 struct chan_freq_power *cfp;
783 char *current_val; /* For rates */ 784 char *current_val; /* For rates */
@@ -801,24 +802,24 @@ static inline char *lbs_translate_scan(struct lbs_private *priv,
801 iwe.cmd = SIOCGIWAP; 802 iwe.cmd = SIOCGIWAP;
802 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 803 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
803 memcpy(iwe.u.ap_addr.sa_data, &bss->bssid, ETH_ALEN); 804 memcpy(iwe.u.ap_addr.sa_data, &bss->bssid, ETH_ALEN);
804 start = iwe_stream_add_event(start, stop, &iwe, IW_EV_ADDR_LEN); 805 start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_ADDR_LEN);
805 806
806 /* SSID */ 807 /* SSID */
807 iwe.cmd = SIOCGIWESSID; 808 iwe.cmd = SIOCGIWESSID;
808 iwe.u.data.flags = 1; 809 iwe.u.data.flags = 1;
809 iwe.u.data.length = min((uint32_t) bss->ssid_len, (uint32_t) IW_ESSID_MAX_SIZE); 810 iwe.u.data.length = min((uint32_t) bss->ssid_len, (uint32_t) IW_ESSID_MAX_SIZE);
810 start = iwe_stream_add_point(start, stop, &iwe, bss->ssid); 811 start = iwe_stream_add_point(info, start, stop, &iwe, bss->ssid);
811 812
812 /* Mode */ 813 /* Mode */
813 iwe.cmd = SIOCGIWMODE; 814 iwe.cmd = SIOCGIWMODE;
814 iwe.u.mode = bss->mode; 815 iwe.u.mode = bss->mode;
815 start = iwe_stream_add_event(start, stop, &iwe, IW_EV_UINT_LEN); 816 start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_UINT_LEN);
816 817
817 /* Frequency */ 818 /* Frequency */
818 iwe.cmd = SIOCGIWFREQ; 819 iwe.cmd = SIOCGIWFREQ;
819 iwe.u.freq.m = (long)cfp->freq * 100000; 820 iwe.u.freq.m = (long)cfp->freq * 100000;
820 iwe.u.freq.e = 1; 821 iwe.u.freq.e = 1;
821 start = iwe_stream_add_event(start, stop, &iwe, IW_EV_FREQ_LEN); 822 start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_FREQ_LEN);
822 823
823 /* Add quality statistics */ 824 /* Add quality statistics */
824 iwe.cmd = IWEVQUAL; 825 iwe.cmd = IWEVQUAL;
@@ -852,7 +853,7 @@ static inline char *lbs_translate_scan(struct lbs_private *priv,
852 nf = priv->NF[TYPE_RXPD][TYPE_AVG] / AVG_SCALE; 853 nf = priv->NF[TYPE_RXPD][TYPE_AVG] / AVG_SCALE;
853 iwe.u.qual.level = CAL_RSSI(snr, nf); 854 iwe.u.qual.level = CAL_RSSI(snr, nf);
854 } 855 }
855 start = iwe_stream_add_event(start, stop, &iwe, IW_EV_QUAL_LEN); 856 start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_QUAL_LEN);
856 857
857 /* Add encryption capability */ 858 /* Add encryption capability */
858 iwe.cmd = SIOCGIWENCODE; 859 iwe.cmd = SIOCGIWENCODE;
@@ -862,9 +863,9 @@ static inline char *lbs_translate_scan(struct lbs_private *priv,
862 iwe.u.data.flags = IW_ENCODE_DISABLED; 863 iwe.u.data.flags = IW_ENCODE_DISABLED;
863 } 864 }
864 iwe.u.data.length = 0; 865 iwe.u.data.length = 0;
865 start = iwe_stream_add_point(start, stop, &iwe, bss->ssid); 866 start = iwe_stream_add_point(info, start, stop, &iwe, bss->ssid);
866 867
867 current_val = start + IW_EV_LCP_LEN; 868 current_val = start + iwe_stream_lcp_len(info);
868 869
869 iwe.cmd = SIOCGIWRATE; 870 iwe.cmd = SIOCGIWRATE;
870 iwe.u.bitrate.fixed = 0; 871 iwe.u.bitrate.fixed = 0;
@@ -874,19 +875,19 @@ static inline char *lbs_translate_scan(struct lbs_private *priv,
874 for (j = 0; bss->rates[j] && (j < sizeof(bss->rates)); j++) { 875 for (j = 0; bss->rates[j] && (j < sizeof(bss->rates)); j++) {
875 /* Bit rate given in 500 kb/s units */ 876 /* Bit rate given in 500 kb/s units */
876 iwe.u.bitrate.value = bss->rates[j] * 500000; 877 iwe.u.bitrate.value = bss->rates[j] * 500000;
877 current_val = iwe_stream_add_value(start, current_val, 878 current_val = iwe_stream_add_value(info, start, current_val,
878 stop, &iwe, IW_EV_PARAM_LEN); 879 stop, &iwe, IW_EV_PARAM_LEN);
879 } 880 }
880 if ((bss->mode == IW_MODE_ADHOC) && priv->adhoccreate 881 if ((bss->mode == IW_MODE_ADHOC) && priv->adhoccreate
881 && !lbs_ssid_cmp(priv->curbssparams.ssid, 882 && !lbs_ssid_cmp(priv->curbssparams.ssid,
882 priv->curbssparams.ssid_len, 883 priv->curbssparams.ssid_len,
883 bss->ssid, bss->ssid_len)) { 884 bss->ssid, bss->ssid_len)) {
884 iwe.u.bitrate.value = 22 * 500000; 885 iwe.u.bitrate.value = 22 * 500000;
885 current_val = iwe_stream_add_value(start, current_val, 886 current_val = iwe_stream_add_value(info, start, current_val,
886 stop, &iwe, IW_EV_PARAM_LEN); 887 stop, &iwe, IW_EV_PARAM_LEN);
887 } 888 }
888 /* Check if we added any event */ 889 /* Check if we added any event */
889 if((current_val - start) > IW_EV_LCP_LEN) 890 if ((current_val - start) > iwe_stream_lcp_len(info))
890 start = current_val; 891 start = current_val;
891 892
892 memset(&iwe, 0, sizeof(iwe)); 893 memset(&iwe, 0, sizeof(iwe));
@@ -895,7 +896,7 @@ static inline char *lbs_translate_scan(struct lbs_private *priv,
895 memcpy(buf, bss->wpa_ie, bss->wpa_ie_len); 896 memcpy(buf, bss->wpa_ie, bss->wpa_ie_len);
896 iwe.cmd = IWEVGENIE; 897 iwe.cmd = IWEVGENIE;
897 iwe.u.data.length = bss->wpa_ie_len; 898 iwe.u.data.length = bss->wpa_ie_len;
898 start = iwe_stream_add_point(start, stop, &iwe, buf); 899 start = iwe_stream_add_point(info, start, stop, &iwe, buf);
899 } 900 }
900 901
901 memset(&iwe, 0, sizeof(iwe)); 902 memset(&iwe, 0, sizeof(iwe));
@@ -904,7 +905,7 @@ static inline char *lbs_translate_scan(struct lbs_private *priv,
904 memcpy(buf, bss->rsn_ie, bss->rsn_ie_len); 905 memcpy(buf, bss->rsn_ie, bss->rsn_ie_len);
905 iwe.cmd = IWEVGENIE; 906 iwe.cmd = IWEVGENIE;
906 iwe.u.data.length = bss->rsn_ie_len; 907 iwe.u.data.length = bss->rsn_ie_len;
907 start = iwe_stream_add_point(start, stop, &iwe, buf); 908 start = iwe_stream_add_point(info, start, stop, &iwe, buf);
908 } 909 }
909 910
910 if (bss->mesh) { 911 if (bss->mesh) {
@@ -915,7 +916,8 @@ static inline char *lbs_translate_scan(struct lbs_private *priv,
915 p += snprintf(p, MAX_CUSTOM_LEN, "mesh-type: olpc"); 916 p += snprintf(p, MAX_CUSTOM_LEN, "mesh-type: olpc");
916 iwe.u.data.length = p - custom; 917 iwe.u.data.length = p - custom;
917 if (iwe.u.data.length) 918 if (iwe.u.data.length)
918 start = iwe_stream_add_point(start, stop, &iwe, custom); 919 start = iwe_stream_add_point(info, start, stop,
920 &iwe, custom);
919 } 921 }
920 922
921out: 923out:
@@ -1036,7 +1038,7 @@ int lbs_get_scan(struct net_device *dev, struct iw_request_info *info,
1036 } 1038 }
1037 1039
1038 /* Translate to WE format this entry */ 1040 /* Translate to WE format this entry */
1039 next_ev = lbs_translate_scan(priv, ev, stop, iter_bss); 1041 next_ev = lbs_translate_scan(priv, info, ev, stop, iter_bss);
1040 if (next_ev == NULL) 1042 if (next_ev == NULL)
1041 continue; 1043 continue;
1042 ev = next_ev; 1044 ev = next_ev;
diff --git a/drivers/net/wireless/libertas/types.h b/drivers/net/wireless/libertas/types.h
index 4031be420862..e0c2599da92f 100644
--- a/drivers/net/wireless/libertas/types.h
+++ b/drivers/net/wireless/libertas/types.h
@@ -6,6 +6,8 @@
6 6
7#include <linux/if_ether.h> 7#include <linux/if_ether.h>
8#include <asm/byteorder.h> 8#include <asm/byteorder.h>
9#include <linux/wireless.h>
10#include <net/ieee80211.h>
9 11
10struct ieeetypes_cfparamset { 12struct ieeetypes_cfparamset {
11 u8 elementid; 13 u8 elementid;
@@ -252,4 +254,32 @@ struct mrvlietypes_ledbhv {
252 struct led_bhv ledbhv[1]; 254 struct led_bhv ledbhv[1];
253} __attribute__ ((packed)); 255} __attribute__ ((packed));
254 256
257/* Meant to be packed as the value member of a struct ieee80211_info_element.
258 * Note that the len member of the ieee80211_info_element varies depending on
259 * the mesh_id_len */
260struct mrvl_meshie_val {
261 uint8_t oui[P80211_OUI_LEN];
262 uint8_t type;
263 uint8_t subtype;
264 uint8_t version;
265 uint8_t active_protocol_id;
266 uint8_t active_metric_id;
267 uint8_t mesh_capability;
268 uint8_t mesh_id_len;
269 uint8_t mesh_id[IW_ESSID_MAX_SIZE];
270} __attribute__ ((packed));
271
272struct mrvl_meshie {
273 struct ieee80211_info_element hdr;
274 struct mrvl_meshie_val val;
275} __attribute__ ((packed));
276
277struct mrvl_mesh_defaults {
278 __le32 bootflag;
279 uint8_t boottime;
280 uint8_t reserved;
281 __le16 channel;
282 struct mrvl_meshie meshie;
283} __attribute__ ((packed));
284
255#endif 285#endif
diff --git a/drivers/net/wireless/libertas/wext.c b/drivers/net/wireless/libertas/wext.c
index 0973d015a520..8b3ed77860b3 100644
--- a/drivers/net/wireless/libertas/wext.c
+++ b/drivers/net/wireless/libertas/wext.c
@@ -1002,7 +1002,7 @@ static int lbs_mesh_set_freq(struct net_device *dev,
1002 else if (priv->mode == IW_MODE_ADHOC) 1002 else if (priv->mode == IW_MODE_ADHOC)
1003 lbs_stop_adhoc_network(priv); 1003 lbs_stop_adhoc_network(priv);
1004 } 1004 }
1005 lbs_mesh_config(priv, 1, fwrq->m); 1005 lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START, fwrq->m);
1006 lbs_update_channel(priv); 1006 lbs_update_channel(priv);
1007 ret = 0; 1007 ret = 0;
1008 1008
@@ -1021,29 +1021,38 @@ static int lbs_set_rate(struct net_device *dev, struct iw_request_info *info,
1021 1021
1022 lbs_deb_enter(LBS_DEB_WEXT); 1022 lbs_deb_enter(LBS_DEB_WEXT);
1023 lbs_deb_wext("vwrq->value %d\n", vwrq->value); 1023 lbs_deb_wext("vwrq->value %d\n", vwrq->value);
1024 lbs_deb_wext("vwrq->fixed %d\n", vwrq->fixed);
1025
1026 if (vwrq->fixed && vwrq->value == -1)
1027 goto out;
1024 1028
1025 /* Auto rate? */ 1029 /* Auto rate? */
1026 if (vwrq->value == -1) { 1030 priv->enablehwauto = !vwrq->fixed;
1027 priv->auto_rate = 1; 1031
1032 if (vwrq->value == -1)
1028 priv->cur_rate = 0; 1033 priv->cur_rate = 0;
1029 } else { 1034 else {
1030 if (vwrq->value % 100000) 1035 if (vwrq->value % 100000)
1031 goto out; 1036 goto out;
1032 1037
1038 new_rate = vwrq->value / 500000;
1039 priv->cur_rate = new_rate;
1040 /* the rest is only needed for lbs_set_data_rate() */
1033 memset(rates, 0, sizeof(rates)); 1041 memset(rates, 0, sizeof(rates));
1034 copy_active_data_rates(priv, rates); 1042 copy_active_data_rates(priv, rates);
1035 new_rate = vwrq->value / 500000;
1036 if (!memchr(rates, new_rate, sizeof(rates))) { 1043 if (!memchr(rates, new_rate, sizeof(rates))) {
1037 lbs_pr_alert("fixed data rate 0x%X out of range\n", 1044 lbs_pr_alert("fixed data rate 0x%X out of range\n",
1038 new_rate); 1045 new_rate);
1039 goto out; 1046 goto out;
1040 } 1047 }
1041
1042 priv->cur_rate = new_rate;
1043 priv->auto_rate = 0;
1044 } 1048 }
1045 1049
1046 ret = lbs_set_data_rate(priv, new_rate); 1050 /* Try the newer command first (Firmware Spec 5.1 and above) */
1051 ret = lbs_cmd_802_11_rate_adapt_rateset(priv, CMD_ACT_SET);
1052
1053 /* Fallback to older version */
1054 if (ret)
1055 ret = lbs_set_data_rate(priv, new_rate);
1047 1056
1048out: 1057out:
1049 lbs_deb_leave_args(LBS_DEB_WEXT, "ret %d", ret); 1058 lbs_deb_leave_args(LBS_DEB_WEXT, "ret %d", ret);
@@ -1060,7 +1069,7 @@ static int lbs_get_rate(struct net_device *dev, struct iw_request_info *info,
1060 if (priv->connect_status == LBS_CONNECTED) { 1069 if (priv->connect_status == LBS_CONNECTED) {
1061 vwrq->value = priv->cur_rate * 500000; 1070 vwrq->value = priv->cur_rate * 500000;
1062 1071
1063 if (priv->auto_rate) 1072 if (priv->enablehwauto)
1064 vwrq->fixed = 0; 1073 vwrq->fixed = 0;
1065 else 1074 else
1066 vwrq->fixed = 1; 1075 vwrq->fixed = 1;
@@ -2011,7 +2020,8 @@ static int lbs_mesh_set_essid(struct net_device *dev,
2011 priv->mesh_ssid_len = dwrq->length; 2020 priv->mesh_ssid_len = dwrq->length;
2012 } 2021 }
2013 2022
2014 lbs_mesh_config(priv, 1, priv->curbssparams.channel); 2023 lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START,
2024 priv->curbssparams.channel);
2015 out: 2025 out:
2016 lbs_deb_leave_args(LBS_DEB_WEXT, "ret %d", ret); 2026 lbs_deb_leave_args(LBS_DEB_WEXT, "ret %d", ret);
2017 return ret; 2027 return ret;
diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c
new file mode 100644
index 000000000000..913dc9fe08f9
--- /dev/null
+++ b/drivers/net/wireless/mac80211_hwsim.c
@@ -0,0 +1,515 @@
1/*
2 * mac80211_hwsim - software simulator of 802.11 radio(s) for mac80211
3 * Copyright (c) 2008, Jouni Malinen <j@w1.fi>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10/*
11 * TODO:
12 * - IBSS mode simulation (Beacon transmission with competition for "air time")
13 * - IEEE 802.11a and 802.11n modes
14 * - RX filtering based on filter configuration (data->rx_filter)
15 */
16
17#include <net/mac80211.h>
18#include <net/ieee80211_radiotap.h>
19#include <linux/if_arp.h>
20#include <linux/rtnetlink.h>
21#include <linux/etherdevice.h>
22
23MODULE_AUTHOR("Jouni Malinen");
24MODULE_DESCRIPTION("Software simulator of 802.11 radio(s) for mac80211");
25MODULE_LICENSE("GPL");
26
27static int radios = 2;
28module_param(radios, int, 0444);
29MODULE_PARM_DESC(radios, "Number of simulated radios");
30
31
32static struct class *hwsim_class;
33
34static struct ieee80211_hw **hwsim_radios;
35static int hwsim_radio_count;
36static struct net_device *hwsim_mon; /* global monitor netdev */
37
38
39static const struct ieee80211_channel hwsim_channels[] = {
40 { .center_freq = 2412 },
41 { .center_freq = 2417 },
42 { .center_freq = 2422 },
43 { .center_freq = 2427 },
44 { .center_freq = 2432 },
45 { .center_freq = 2437 },
46 { .center_freq = 2442 },
47 { .center_freq = 2447 },
48 { .center_freq = 2452 },
49 { .center_freq = 2457 },
50 { .center_freq = 2462 },
51 { .center_freq = 2467 },
52 { .center_freq = 2472 },
53 { .center_freq = 2484 },
54};
55
56static const struct ieee80211_rate hwsim_rates[] = {
57 { .bitrate = 10 },
58 { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
59 { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
60 { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
61 { .bitrate = 60 },
62 { .bitrate = 90 },
63 { .bitrate = 120 },
64 { .bitrate = 180 },
65 { .bitrate = 240 },
66 { .bitrate = 360 },
67 { .bitrate = 480 },
68 { .bitrate = 540 }
69};
70
71struct mac80211_hwsim_data {
72 struct device *dev;
73 struct ieee80211_supported_band band;
74 struct ieee80211_channel channels[ARRAY_SIZE(hwsim_channels)];
75 struct ieee80211_rate rates[ARRAY_SIZE(hwsim_rates)];
76
77 struct ieee80211_channel *channel;
78 int radio_enabled;
79 unsigned long beacon_int; /* in jiffies unit */
80 unsigned int rx_filter;
81 int started;
82 struct timer_list beacon_timer;
83};
84
85
86struct hwsim_radiotap_hdr {
87 struct ieee80211_radiotap_header hdr;
88 u8 rt_flags;
89 u8 rt_rate;
90 __le16 rt_channel;
91 __le16 rt_chbitmask;
92} __attribute__ ((packed));
93
94
95static int hwsim_mon_xmit(struct sk_buff *skb, struct net_device *dev)
96{
97 /* TODO: allow packet injection */
98 dev_kfree_skb(skb);
99 return 0;
100}
101
102
103static void mac80211_hwsim_monitor_rx(struct ieee80211_hw *hw,
104 struct sk_buff *tx_skb)
105{
106 struct mac80211_hwsim_data *data = hw->priv;
107 struct sk_buff *skb;
108 struct hwsim_radiotap_hdr *hdr;
109 u16 flags;
110 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_skb);
111 struct ieee80211_rate *txrate = ieee80211_get_tx_rate(hw, info);
112
113 if (!netif_running(hwsim_mon))
114 return;
115
116 skb = skb_copy_expand(tx_skb, sizeof(*hdr), 0, GFP_ATOMIC);
117 if (skb == NULL)
118 return;
119
120 hdr = (struct hwsim_radiotap_hdr *) skb_push(skb, sizeof(*hdr));
121 hdr->hdr.it_version = PKTHDR_RADIOTAP_VERSION;
122 hdr->hdr.it_pad = 0;
123 hdr->hdr.it_len = cpu_to_le16(sizeof(*hdr));
124 hdr->hdr.it_present = cpu_to_le32((1 << IEEE80211_RADIOTAP_FLAGS) |
125 (1 << IEEE80211_RADIOTAP_RATE) |
126 (1 << IEEE80211_RADIOTAP_CHANNEL));
127 hdr->rt_flags = 0;
128 hdr->rt_rate = txrate->bitrate / 5;
129 hdr->rt_channel = cpu_to_le16(data->channel->center_freq);
130 flags = IEEE80211_CHAN_2GHZ;
131 if (txrate->flags & IEEE80211_RATE_ERP_G)
132 flags |= IEEE80211_CHAN_OFDM;
133 else
134 flags |= IEEE80211_CHAN_CCK;
135 hdr->rt_chbitmask = cpu_to_le16(flags);
136
137 skb->dev = hwsim_mon;
138 skb_set_mac_header(skb, 0);
139 skb->ip_summed = CHECKSUM_UNNECESSARY;
140 skb->pkt_type = PACKET_OTHERHOST;
141 skb->protocol = htons(ETH_P_802_2);
142 memset(skb->cb, 0, sizeof(skb->cb));
143 netif_rx(skb);
144}
145
146
147static int mac80211_hwsim_tx_frame(struct ieee80211_hw *hw,
148 struct sk_buff *skb)
149{
150 struct mac80211_hwsim_data *data = hw->priv;
151 int i, ack = 0;
152 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
153 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
154 struct ieee80211_rx_status rx_status;
155
156 memset(&rx_status, 0, sizeof(rx_status));
157 /* TODO: set mactime */
158 rx_status.freq = data->channel->center_freq;
159 rx_status.band = data->channel->band;
160 rx_status.rate_idx = info->tx_rate_idx;
161 /* TODO: simulate signal strength (and optional packet drop) */
162
163 /* Copy skb to all enabled radios that are on the current frequency */
164 for (i = 0; i < hwsim_radio_count; i++) {
165 struct mac80211_hwsim_data *data2;
166 struct sk_buff *nskb;
167
168 if (hwsim_radios[i] == NULL || hwsim_radios[i] == hw)
169 continue;
170 data2 = hwsim_radios[i]->priv;
171 if (!data2->started || !data2->radio_enabled ||
172 data->channel->center_freq != data2->channel->center_freq)
173 continue;
174
175 nskb = skb_copy(skb, GFP_ATOMIC);
176 if (nskb == NULL)
177 continue;
178
179 if (memcmp(hdr->addr1, hwsim_radios[i]->wiphy->perm_addr,
180 ETH_ALEN) == 0)
181 ack = 1;
182 ieee80211_rx_irqsafe(hwsim_radios[i], nskb, &rx_status);
183 }
184
185 return ack;
186}
187
188
189static int mac80211_hwsim_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
190{
191 struct mac80211_hwsim_data *data = hw->priv;
192 int ack;
193 struct ieee80211_tx_info *txi;
194
195 mac80211_hwsim_monitor_rx(hw, skb);
196
197 if (skb->len < 10) {
198 /* Should not happen; just a sanity check for addr1 use */
199 dev_kfree_skb(skb);
200 return NETDEV_TX_OK;
201 }
202
203 if (!data->radio_enabled) {
204 printk(KERN_DEBUG "%s: dropped TX frame since radio "
205 "disabled\n", wiphy_name(hw->wiphy));
206 dev_kfree_skb(skb);
207 return NETDEV_TX_OK;
208 }
209
210 ack = mac80211_hwsim_tx_frame(hw, skb);
211
212 txi = IEEE80211_SKB_CB(skb);
213 memset(&txi->status, 0, sizeof(txi->status));
214 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK)) {
215 if (ack)
216 txi->flags |= IEEE80211_TX_STAT_ACK;
217 else
218 txi->status.excessive_retries = 1;
219 }
220 ieee80211_tx_status_irqsafe(hw, skb);
221 return NETDEV_TX_OK;
222}
223
224
225static int mac80211_hwsim_start(struct ieee80211_hw *hw)
226{
227 struct mac80211_hwsim_data *data = hw->priv;
228 printk(KERN_DEBUG "%s:%s\n", wiphy_name(hw->wiphy), __func__);
229 data->started = 1;
230 return 0;
231}
232
233
234static void mac80211_hwsim_stop(struct ieee80211_hw *hw)
235{
236 struct mac80211_hwsim_data *data = hw->priv;
237 data->started = 0;
238 printk(KERN_DEBUG "%s:%s\n", wiphy_name(hw->wiphy), __func__);
239}
240
241
242static int mac80211_hwsim_add_interface(struct ieee80211_hw *hw,
243 struct ieee80211_if_init_conf *conf)
244{
245 DECLARE_MAC_BUF(mac);
246 printk(KERN_DEBUG "%s:%s (type=%d mac_addr=%s)\n",
247 wiphy_name(hw->wiphy), __func__, conf->type,
248 print_mac(mac, conf->mac_addr));
249 return 0;
250}
251
252
253static void mac80211_hwsim_remove_interface(
254 struct ieee80211_hw *hw, struct ieee80211_if_init_conf *conf)
255{
256 DECLARE_MAC_BUF(mac);
257 printk(KERN_DEBUG "%s:%s (type=%d mac_addr=%s)\n",
258 wiphy_name(hw->wiphy), __func__, conf->type,
259 print_mac(mac, conf->mac_addr));
260}
261
262
263static void mac80211_hwsim_beacon_tx(void *arg, u8 *mac,
264 struct ieee80211_vif *vif)
265{
266 struct ieee80211_hw *hw = arg;
267 struct sk_buff *skb;
268 struct ieee80211_tx_info *info;
269
270 if (vif->type != IEEE80211_IF_TYPE_AP)
271 return;
272
273 skb = ieee80211_beacon_get(hw, vif);
274 if (skb == NULL)
275 return;
276 info = IEEE80211_SKB_CB(skb);
277
278 mac80211_hwsim_monitor_rx(hw, skb);
279 mac80211_hwsim_tx_frame(hw, skb);
280 dev_kfree_skb(skb);
281}
282
283
284static void mac80211_hwsim_beacon(unsigned long arg)
285{
286 struct ieee80211_hw *hw = (struct ieee80211_hw *) arg;
287 struct mac80211_hwsim_data *data = hw->priv;
288
289 if (!data->started || !data->radio_enabled)
290 return;
291
292 ieee80211_iterate_active_interfaces_atomic(
293 hw, mac80211_hwsim_beacon_tx, hw);
294
295 data->beacon_timer.expires = jiffies + data->beacon_int;
296 add_timer(&data->beacon_timer);
297}
298
299
300static int mac80211_hwsim_config(struct ieee80211_hw *hw,
301 struct ieee80211_conf *conf)
302{
303 struct mac80211_hwsim_data *data = hw->priv;
304
305 printk(KERN_DEBUG "%s:%s (freq=%d radio_enabled=%d beacon_int=%d)\n",
306 wiphy_name(hw->wiphy), __func__,
307 conf->channel->center_freq, conf->radio_enabled,
308 conf->beacon_int);
309
310 data->channel = conf->channel;
311 data->radio_enabled = conf->radio_enabled;
312 data->beacon_int = 1024 * conf->beacon_int / 1000 * HZ / 1000;
313 if (data->beacon_int < 1)
314 data->beacon_int = 1;
315
316 if (!data->started || !data->radio_enabled)
317 del_timer(&data->beacon_timer);
318 else
319 mod_timer(&data->beacon_timer, jiffies + data->beacon_int);
320
321 return 0;
322}
323
324
325static void mac80211_hwsim_configure_filter(struct ieee80211_hw *hw,
326 unsigned int changed_flags,
327 unsigned int *total_flags,
328 int mc_count,
329 struct dev_addr_list *mc_list)
330{
331 struct mac80211_hwsim_data *data = hw->priv;
332
333 printk(KERN_DEBUG "%s:%s\n", wiphy_name(hw->wiphy), __func__);
334
335 data->rx_filter = 0;
336 if (*total_flags & FIF_PROMISC_IN_BSS)
337 data->rx_filter |= FIF_PROMISC_IN_BSS;
338 if (*total_flags & FIF_ALLMULTI)
339 data->rx_filter |= FIF_ALLMULTI;
340
341 *total_flags = data->rx_filter;
342}
343
344
345
346static const struct ieee80211_ops mac80211_hwsim_ops =
347{
348 .tx = mac80211_hwsim_tx,
349 .start = mac80211_hwsim_start,
350 .stop = mac80211_hwsim_stop,
351 .add_interface = mac80211_hwsim_add_interface,
352 .remove_interface = mac80211_hwsim_remove_interface,
353 .config = mac80211_hwsim_config,
354 .configure_filter = mac80211_hwsim_configure_filter,
355};
356
357
358static void mac80211_hwsim_free(void)
359{
360 int i;
361
362 for (i = 0; i < hwsim_radio_count; i++) {
363 if (hwsim_radios[i]) {
364 struct mac80211_hwsim_data *data;
365 data = hwsim_radios[i]->priv;
366 ieee80211_unregister_hw(hwsim_radios[i]);
367 if (!IS_ERR(data->dev))
368 device_unregister(data->dev);
369 ieee80211_free_hw(hwsim_radios[i]);
370 }
371 }
372 kfree(hwsim_radios);
373 class_destroy(hwsim_class);
374}
375
376
377static struct device_driver mac80211_hwsim_driver = {
378 .name = "mac80211_hwsim"
379};
380
381
382static void hwsim_mon_setup(struct net_device *dev)
383{
384 dev->hard_start_xmit = hwsim_mon_xmit;
385 dev->destructor = free_netdev;
386 ether_setup(dev);
387 dev->tx_queue_len = 0;
388 dev->type = ARPHRD_IEEE80211_RADIOTAP;
389 memset(dev->dev_addr, 0, ETH_ALEN);
390 dev->dev_addr[0] = 0x12;
391}
392
393
394static int __init init_mac80211_hwsim(void)
395{
396 int i, err = 0;
397 u8 addr[ETH_ALEN];
398 struct mac80211_hwsim_data *data;
399 struct ieee80211_hw *hw;
400 DECLARE_MAC_BUF(mac);
401
402 if (radios < 1 || radios > 65535)
403 return -EINVAL;
404
405 hwsim_radio_count = radios;
406 hwsim_radios = kcalloc(hwsim_radio_count,
407 sizeof(struct ieee80211_hw *), GFP_KERNEL);
408 if (hwsim_radios == NULL)
409 return -ENOMEM;
410
411 hwsim_class = class_create(THIS_MODULE, "mac80211_hwsim");
412 if (IS_ERR(hwsim_class)) {
413 kfree(hwsim_radios);
414 return PTR_ERR(hwsim_class);
415 }
416
417 memset(addr, 0, ETH_ALEN);
418 addr[0] = 0x02;
419
420 for (i = 0; i < hwsim_radio_count; i++) {
421 printk(KERN_DEBUG "mac80211_hwsim: Initializing radio %d\n",
422 i);
423 hw = ieee80211_alloc_hw(sizeof(*data), &mac80211_hwsim_ops);
424 if (hw == NULL) {
425 printk(KERN_DEBUG "mac80211_hwsim: ieee80211_alloc_hw "
426 "failed\n");
427 err = -ENOMEM;
428 goto failed;
429 }
430 hwsim_radios[i] = hw;
431
432 data = hw->priv;
433 data->dev = device_create_drvdata(hwsim_class, NULL, 0, hw,
434 "hwsim%d", i);
435 if (IS_ERR(data->dev)) {
436 printk(KERN_DEBUG
437 "mac80211_hwsim: device_create_drvdata "
438 "failed (%ld)\n", PTR_ERR(data->dev));
439 err = -ENOMEM;
440 goto failed;
441 }
442 data->dev->driver = &mac80211_hwsim_driver;
443
444 SET_IEEE80211_DEV(hw, data->dev);
445 addr[3] = i >> 8;
446 addr[4] = i;
447 SET_IEEE80211_PERM_ADDR(hw, addr);
448
449 hw->channel_change_time = 1;
450 hw->queues = 1;
451
452 memcpy(data->channels, hwsim_channels, sizeof(hwsim_channels));
453 memcpy(data->rates, hwsim_rates, sizeof(hwsim_rates));
454 data->band.channels = data->channels;
455 data->band.n_channels = ARRAY_SIZE(hwsim_channels);
456 data->band.bitrates = data->rates;
457 data->band.n_bitrates = ARRAY_SIZE(hwsim_rates);
458 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &data->band;
459
460 err = ieee80211_register_hw(hw);
461 if (err < 0) {
462 printk(KERN_DEBUG "mac80211_hwsim: "
463 "ieee80211_register_hw failed (%d)\n", err);
464 goto failed;
465 }
466
467 printk(KERN_DEBUG "%s: hwaddr %s registered\n",
468 wiphy_name(hw->wiphy),
469 print_mac(mac, hw->wiphy->perm_addr));
470
471 setup_timer(&data->beacon_timer, mac80211_hwsim_beacon,
472 (unsigned long) hw);
473 }
474
475 hwsim_mon = alloc_netdev(0, "hwsim%d", hwsim_mon_setup);
476 if (hwsim_mon == NULL)
477 goto failed;
478
479 rtnl_lock();
480
481 err = dev_alloc_name(hwsim_mon, hwsim_mon->name);
482 if (err < 0) {
483 goto failed_mon;
484 }
485
486 err = register_netdevice(hwsim_mon);
487 if (err < 0)
488 goto failed_mon;
489
490 rtnl_unlock();
491
492 return 0;
493
494failed_mon:
495 rtnl_unlock();
496 free_netdev(hwsim_mon);
497
498failed:
499 mac80211_hwsim_free();
500 return err;
501}
502
503
504static void __exit exit_mac80211_hwsim(void)
505{
506 printk(KERN_DEBUG "mac80211_hwsim: unregister %d radios\n",
507 hwsim_radio_count);
508
509 unregister_netdev(hwsim_mon);
510 mac80211_hwsim_free();
511}
512
513
514module_init(init_mac80211_hwsim);
515module_exit(exit_mac80211_hwsim);
diff --git a/drivers/net/wireless/orinoco.c b/drivers/net/wireless/orinoco.c
index 6d13a0d15a0c..b047306bf386 100644
--- a/drivers/net/wireless/orinoco.c
+++ b/drivers/net/wireless/orinoco.c
@@ -4046,6 +4046,7 @@ static int orinoco_ioctl_setscan(struct net_device *dev,
4046 * format that the Wireless Tools will understand - Jean II 4046 * format that the Wireless Tools will understand - Jean II
4047 * Return message length or -errno for fatal errors */ 4047 * Return message length or -errno for fatal errors */
4048static inline char *orinoco_translate_scan(struct net_device *dev, 4048static inline char *orinoco_translate_scan(struct net_device *dev,
4049 struct iw_request_info *info,
4049 char *current_ev, 4050 char *current_ev,
4050 char *end_buf, 4051 char *end_buf,
4051 union hermes_scan_info *bss, 4052 union hermes_scan_info *bss,
@@ -4062,7 +4063,8 @@ static inline char *orinoco_translate_scan(struct net_device *dev,
4062 iwe.cmd = SIOCGIWAP; 4063 iwe.cmd = SIOCGIWAP;
4063 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 4064 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
4064 memcpy(iwe.u.ap_addr.sa_data, bss->a.bssid, ETH_ALEN); 4065 memcpy(iwe.u.ap_addr.sa_data, bss->a.bssid, ETH_ALEN);
4065 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_ADDR_LEN); 4066 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
4067 &iwe, IW_EV_ADDR_LEN);
4066 4068
4067 /* Other entries will be displayed in the order we give them */ 4069 /* Other entries will be displayed in the order we give them */
4068 4070
@@ -4072,7 +4074,8 @@ static inline char *orinoco_translate_scan(struct net_device *dev,
4072 iwe.u.data.length = 32; 4074 iwe.u.data.length = 32;
4073 iwe.cmd = SIOCGIWESSID; 4075 iwe.cmd = SIOCGIWESSID;
4074 iwe.u.data.flags = 1; 4076 iwe.u.data.flags = 1;
4075 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, bss->a.essid); 4077 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
4078 &iwe, bss->a.essid);
4076 4079
4077 /* Add mode */ 4080 /* Add mode */
4078 iwe.cmd = SIOCGIWMODE; 4081 iwe.cmd = SIOCGIWMODE;
@@ -4082,7 +4085,8 @@ static inline char *orinoco_translate_scan(struct net_device *dev,
4082 iwe.u.mode = IW_MODE_MASTER; 4085 iwe.u.mode = IW_MODE_MASTER;
4083 else 4086 else
4084 iwe.u.mode = IW_MODE_ADHOC; 4087 iwe.u.mode = IW_MODE_ADHOC;
4085 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_UINT_LEN); 4088 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
4089 &iwe, IW_EV_UINT_LEN);
4086 } 4090 }
4087 4091
4088 channel = bss->s.channel; 4092 channel = bss->s.channel;
@@ -4091,7 +4095,7 @@ static inline char *orinoco_translate_scan(struct net_device *dev,
4091 iwe.cmd = SIOCGIWFREQ; 4095 iwe.cmd = SIOCGIWFREQ;
4092 iwe.u.freq.m = channel_frequency[channel-1] * 100000; 4096 iwe.u.freq.m = channel_frequency[channel-1] * 100000;
4093 iwe.u.freq.e = 1; 4097 iwe.u.freq.e = 1;
4094 current_ev = iwe_stream_add_event(current_ev, end_buf, 4098 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
4095 &iwe, IW_EV_FREQ_LEN); 4099 &iwe, IW_EV_FREQ_LEN);
4096 } 4100 }
4097 4101
@@ -4106,7 +4110,8 @@ static inline char *orinoco_translate_scan(struct net_device *dev,
4106 iwe.u.qual.qual = iwe.u.qual.level - iwe.u.qual.noise; 4110 iwe.u.qual.qual = iwe.u.qual.level - iwe.u.qual.noise;
4107 else 4111 else
4108 iwe.u.qual.qual = 0; 4112 iwe.u.qual.qual = 0;
4109 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_QUAL_LEN); 4113 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
4114 &iwe, IW_EV_QUAL_LEN);
4110 4115
4111 /* Add encryption capability */ 4116 /* Add encryption capability */
4112 iwe.cmd = SIOCGIWENCODE; 4117 iwe.cmd = SIOCGIWENCODE;
@@ -4115,7 +4120,8 @@ static inline char *orinoco_translate_scan(struct net_device *dev,
4115 else 4120 else
4116 iwe.u.data.flags = IW_ENCODE_DISABLED; 4121 iwe.u.data.flags = IW_ENCODE_DISABLED;
4117 iwe.u.data.length = 0; 4122 iwe.u.data.length = 0;
4118 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, bss->a.essid); 4123 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
4124 &iwe, bss->a.essid);
4119 4125
4120 /* Add EXTRA: Age to display seconds since last beacon/probe response 4126 /* Add EXTRA: Age to display seconds since last beacon/probe response
4121 * for given network. */ 4127 * for given network. */
@@ -4126,11 +4132,12 @@ static inline char *orinoco_translate_scan(struct net_device *dev,
4126 jiffies_to_msecs(jiffies - last_scanned)); 4132 jiffies_to_msecs(jiffies - last_scanned));
4127 iwe.u.data.length = p - custom; 4133 iwe.u.data.length = p - custom;
4128 if (iwe.u.data.length) 4134 if (iwe.u.data.length)
4129 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, custom); 4135 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
4136 &iwe, custom);
4130 4137
4131 /* Bit rate is not available in Lucent/Agere firmwares */ 4138 /* Bit rate is not available in Lucent/Agere firmwares */
4132 if (priv->firmware_type != FIRMWARE_TYPE_AGERE) { 4139 if (priv->firmware_type != FIRMWARE_TYPE_AGERE) {
4133 char *current_val = current_ev + IW_EV_LCP_LEN; 4140 char *current_val = current_ev + iwe_stream_lcp_len(info);
4134 int i; 4141 int i;
4135 int step; 4142 int step;
4136 4143
@@ -4149,12 +4156,13 @@ static inline char *orinoco_translate_scan(struct net_device *dev,
4149 break; 4156 break;
4150 /* Bit rate given in 500 kb/s units (+ 0x80) */ 4157 /* Bit rate given in 500 kb/s units (+ 0x80) */
4151 iwe.u.bitrate.value = ((bss->p.rates[i] & 0x7f) * 500000); 4158 iwe.u.bitrate.value = ((bss->p.rates[i] & 0x7f) * 500000);
4152 current_val = iwe_stream_add_value(current_ev, current_val, 4159 current_val = iwe_stream_add_value(info, current_ev,
4160 current_val,
4153 end_buf, &iwe, 4161 end_buf, &iwe,
4154 IW_EV_PARAM_LEN); 4162 IW_EV_PARAM_LEN);
4155 } 4163 }
4156 /* Check if we added any event */ 4164 /* Check if we added any event */
4157 if ((current_val - current_ev) > IW_EV_LCP_LEN) 4165 if ((current_val - current_ev) > iwe_stream_lcp_len(info))
4158 current_ev = current_val; 4166 current_ev = current_val;
4159 } 4167 }
4160 4168
@@ -4190,7 +4198,7 @@ static int orinoco_ioctl_getscan(struct net_device *dev,
4190 4198
4191 list_for_each_entry(bss, &priv->bss_list, list) { 4199 list_for_each_entry(bss, &priv->bss_list, list) {
4192 /* Translate to WE format this entry */ 4200 /* Translate to WE format this entry */
4193 current_ev = orinoco_translate_scan(dev, current_ev, 4201 current_ev = orinoco_translate_scan(dev, info, current_ev,
4194 extra + srq->length, 4202 extra + srq->length,
4195 &bss->bss, 4203 &bss->bss,
4196 bss->last_scanned); 4204 bss->last_scanned);
diff --git a/drivers/net/wireless/p54/p54.h b/drivers/net/wireless/p54/p54.h
index 06d2c67f4c81..c6f27b9022f9 100644
--- a/drivers/net/wireless/p54/p54.h
+++ b/drivers/net/wireless/p54/p54.h
@@ -64,7 +64,7 @@ struct p54_common {
64 unsigned int tx_hdr_len; 64 unsigned int tx_hdr_len;
65 void *cached_vdcf; 65 void *cached_vdcf;
66 unsigned int fw_var; 66 unsigned int fw_var;
67 struct ieee80211_tx_queue_stats tx_stats; 67 struct ieee80211_tx_queue_stats tx_stats[4];
68}; 68};
69 69
70int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb); 70int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb);
diff --git a/drivers/net/wireless/p54/p54common.c b/drivers/net/wireless/p54/p54common.c
index 63f9badf3f52..ffaf7a6b6810 100644
--- a/drivers/net/wireless/p54/p54common.c
+++ b/drivers/net/wireless/p54/p54common.c
@@ -146,10 +146,10 @@ void p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
146 146
147 if (priv->fw_var >= 0x300) { 147 if (priv->fw_var >= 0x300) {
148 /* Firmware supports QoS, use it! */ 148 /* Firmware supports QoS, use it! */
149 priv->tx_stats.data[0].limit = 3; 149 priv->tx_stats[0].limit = 3;
150 priv->tx_stats.data[1].limit = 4; 150 priv->tx_stats[1].limit = 4;
151 priv->tx_stats.data[2].limit = 3; 151 priv->tx_stats[2].limit = 3;
152 priv->tx_stats.data[3].limit = 1; 152 priv->tx_stats[3].limit = 1;
153 dev->queues = 4; 153 dev->queues = 4;
154 } 154 }
155} 155}
@@ -355,8 +355,9 @@ static void p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
355 struct ieee80211_rx_status rx_status = {0}; 355 struct ieee80211_rx_status rx_status = {0};
356 u16 freq = le16_to_cpu(hdr->freq); 356 u16 freq = le16_to_cpu(hdr->freq);
357 357
358 rx_status.ssi = hdr->rssi; 358 rx_status.signal = hdr->rssi;
359 /* XX correct? */ 359 /* XX correct? */
360 rx_status.qual = (100 * hdr->rssi) / 127;
360 rx_status.rate_idx = hdr->rate & 0xf; 361 rx_status.rate_idx = hdr->rate & 0xf;
361 rx_status.freq = freq; 362 rx_status.freq = freq;
362 rx_status.band = IEEE80211_BAND_2GHZ; 363 rx_status.band = IEEE80211_BAND_2GHZ;
@@ -375,11 +376,8 @@ static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
375 struct p54_common *priv = dev->priv; 376 struct p54_common *priv = dev->priv;
376 int i; 377 int i;
377 378
378 /* ieee80211_start_queues is great if all queues are really empty.
379 * But, what if some are full? */
380
381 for (i = 0; i < dev->queues; i++) 379 for (i = 0; i < dev->queues; i++)
382 if (priv->tx_stats.data[i].len < priv->tx_stats.data[i].limit) 380 if (priv->tx_stats[i].len < priv->tx_stats[i].limit)
383 ieee80211_wake_queue(dev, i); 381 ieee80211_wake_queue(dev, i);
384} 382}
385 383
@@ -395,45 +393,42 @@ static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
395 u32 last_addr = priv->rx_start; 393 u32 last_addr = priv->rx_start;
396 394
397 while (entry != (struct sk_buff *)&priv->tx_queue) { 395 while (entry != (struct sk_buff *)&priv->tx_queue) {
398 range = (struct memrecord *)&entry->cb; 396 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
397 range = (void *)info->driver_data;
399 if (range->start_addr == addr) { 398 if (range->start_addr == addr) {
400 struct ieee80211_tx_status status;
401 struct p54_control_hdr *entry_hdr; 399 struct p54_control_hdr *entry_hdr;
402 struct p54_tx_control_allocdata *entry_data; 400 struct p54_tx_control_allocdata *entry_data;
403 int pad = 0; 401 int pad = 0;
404 402
405 if (entry->next != (struct sk_buff *)&priv->tx_queue) 403 if (entry->next != (struct sk_buff *)&priv->tx_queue) {
406 freed = ((struct memrecord *)&entry->next->cb)->start_addr - last_addr; 404 struct ieee80211_tx_info *ni;
407 else 405 struct memrecord *mr;
406
407 ni = IEEE80211_SKB_CB(entry->next);
408 mr = (struct memrecord *)ni->driver_data;
409 freed = mr->start_addr - last_addr;
410 } else
408 freed = priv->rx_end - last_addr; 411 freed = priv->rx_end - last_addr;
409 412
410 last_addr = range->end_addr; 413 last_addr = range->end_addr;
411 __skb_unlink(entry, &priv->tx_queue); 414 __skb_unlink(entry, &priv->tx_queue);
412 if (!range->control) { 415 memset(&info->status, 0, sizeof(info->status));
413 kfree_skb(entry); 416 priv->tx_stats[skb_get_queue_mapping(skb)].len--;
414 break;
415 }
416 memset(&status, 0, sizeof(status));
417 memcpy(&status.control, range->control,
418 sizeof(status.control));
419 kfree(range->control);
420 priv->tx_stats.data[status.control.queue].len--;
421
422 entry_hdr = (struct p54_control_hdr *) entry->data; 417 entry_hdr = (struct p54_control_hdr *) entry->data;
423 entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data; 418 entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data;
424 if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0) 419 if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0)
425 pad = entry_data->align[0]; 420 pad = entry_data->align[0];
426 421
427 if (!(status.control.flags & IEEE80211_TXCTL_NO_ACK)) { 422 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
428 if (!(payload->status & 0x01)) 423 if (!(payload->status & 0x01))
429 status.flags |= IEEE80211_TX_STATUS_ACK; 424 info->flags |= IEEE80211_TX_STAT_ACK;
430 else 425 else
431 status.excessive_retries = 1; 426 info->status.excessive_retries = 1;
432 } 427 }
433 status.retry_count = payload->retries - 1; 428 info->status.retry_count = payload->retries - 1;
434 status.ack_signal = le16_to_cpu(payload->ack_rssi); 429 info->status.ack_signal = le16_to_cpu(payload->ack_rssi);
435 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data)); 430 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
436 ieee80211_tx_status_irqsafe(dev, entry, &status); 431 ieee80211_tx_status_irqsafe(dev, entry);
437 break; 432 break;
438 } else 433 } else
439 last_addr = range->end_addr; 434 last_addr = range->end_addr;
@@ -498,13 +493,11 @@ EXPORT_SYMBOL_GPL(p54_rx);
498 * allocated areas. 493 * allocated areas.
499 */ 494 */
500static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb, 495static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
501 struct p54_control_hdr *data, u32 len, 496 struct p54_control_hdr *data, u32 len)
502 struct ieee80211_tx_control *control)
503{ 497{
504 struct p54_common *priv = dev->priv; 498 struct p54_common *priv = dev->priv;
505 struct sk_buff *entry = priv->tx_queue.next; 499 struct sk_buff *entry = priv->tx_queue.next;
506 struct sk_buff *target_skb = NULL; 500 struct sk_buff *target_skb = NULL;
507 struct memrecord *range;
508 u32 last_addr = priv->rx_start; 501 u32 last_addr = priv->rx_start;
509 u32 largest_hole = 0; 502 u32 largest_hole = 0;
510 u32 target_addr = priv->rx_start; 503 u32 target_addr = priv->rx_start;
@@ -516,7 +509,8 @@ static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
516 left = skb_queue_len(&priv->tx_queue); 509 left = skb_queue_len(&priv->tx_queue);
517 while (left--) { 510 while (left--) {
518 u32 hole_size; 511 u32 hole_size;
519 range = (struct memrecord *)&entry->cb; 512 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
513 struct memrecord *range = (void *)info->driver_data;
520 hole_size = range->start_addr - last_addr; 514 hole_size = range->start_addr - last_addr;
521 if (!target_skb && hole_size >= len) { 515 if (!target_skb && hole_size >= len) {
522 target_skb = entry->prev; 516 target_skb = entry->prev;
@@ -531,17 +525,18 @@ static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
531 target_skb = priv->tx_queue.prev; 525 target_skb = priv->tx_queue.prev;
532 largest_hole = max(largest_hole, priv->rx_end - last_addr - len); 526 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
533 if (!skb_queue_empty(&priv->tx_queue)) { 527 if (!skb_queue_empty(&priv->tx_queue)) {
534 range = (struct memrecord *)&target_skb->cb; 528 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(target_skb);
529 struct memrecord *range = (void *)info->driver_data;
535 target_addr = range->end_addr; 530 target_addr = range->end_addr;
536 } 531 }
537 } else 532 } else
538 largest_hole = max(largest_hole, priv->rx_end - last_addr); 533 largest_hole = max(largest_hole, priv->rx_end - last_addr);
539 534
540 if (skb) { 535 if (skb) {
541 range = (struct memrecord *)&skb->cb; 536 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
537 struct memrecord *range = (void *)info->driver_data;
542 range->start_addr = target_addr; 538 range->start_addr = target_addr;
543 range->end_addr = target_addr + len; 539 range->end_addr = target_addr + len;
544 range->control = control;
545 __skb_queue_after(&priv->tx_queue, target_skb, skb); 540 __skb_queue_after(&priv->tx_queue, target_skb, skb);
546 if (largest_hole < IEEE80211_MAX_RTS_THRESHOLD + 0x170 + 541 if (largest_hole < IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
547 sizeof(struct p54_control_hdr)) 542 sizeof(struct p54_control_hdr))
@@ -552,32 +547,27 @@ static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
552 data->req_id = cpu_to_le32(target_addr + 0x70); 547 data->req_id = cpu_to_le32(target_addr + 0x70);
553} 548}
554 549
555static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb, 550static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
556 struct ieee80211_tx_control *control)
557{ 551{
558 struct ieee80211_tx_queue_stats_data *current_queue; 552 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
553 struct ieee80211_tx_queue_stats *current_queue;
559 struct p54_common *priv = dev->priv; 554 struct p54_common *priv = dev->priv;
560 struct p54_control_hdr *hdr; 555 struct p54_control_hdr *hdr;
561 struct p54_tx_control_allocdata *txhdr; 556 struct p54_tx_control_allocdata *txhdr;
562 struct ieee80211_tx_control *control_copy;
563 size_t padding, len; 557 size_t padding, len;
564 u8 rate; 558 u8 rate;
565 559
566 current_queue = &priv->tx_stats.data[control->queue]; 560 current_queue = &priv->tx_stats[skb_get_queue_mapping(skb)];
567 if (unlikely(current_queue->len > current_queue->limit)) 561 if (unlikely(current_queue->len > current_queue->limit))
568 return NETDEV_TX_BUSY; 562 return NETDEV_TX_BUSY;
569 current_queue->len++; 563 current_queue->len++;
570 current_queue->count++; 564 current_queue->count++;
571 if (current_queue->len == current_queue->limit) 565 if (current_queue->len == current_queue->limit)
572 ieee80211_stop_queue(dev, control->queue); 566 ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
573 567
574 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3; 568 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
575 len = skb->len; 569 len = skb->len;
576 570
577 control_copy = kmalloc(sizeof(*control), GFP_ATOMIC);
578 if (control_copy)
579 memcpy(control_copy, control, sizeof(*control));
580
581 txhdr = (struct p54_tx_control_allocdata *) 571 txhdr = (struct p54_tx_control_allocdata *)
582 skb_push(skb, sizeof(*txhdr) + padding); 572 skb_push(skb, sizeof(*txhdr) + padding);
583 hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr)); 573 hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr));
@@ -587,35 +577,37 @@ static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
587 else 577 else
588 hdr->magic1 = cpu_to_le16(0x0010); 578 hdr->magic1 = cpu_to_le16(0x0010);
589 hdr->len = cpu_to_le16(len); 579 hdr->len = cpu_to_le16(len);
590 hdr->type = (control->flags & IEEE80211_TXCTL_NO_ACK) ? 0 : cpu_to_le16(1); 580 hdr->type = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 0 : cpu_to_le16(1);
591 hdr->retry1 = hdr->retry2 = control->retry_limit; 581 hdr->retry1 = hdr->retry2 = info->control.retry_limit;
592 p54_assign_address(dev, skb, hdr, skb->len, control_copy);
593 582
594 memset(txhdr->wep_key, 0x0, 16); 583 memset(txhdr->wep_key, 0x0, 16);
595 txhdr->padding = 0; 584 txhdr->padding = 0;
596 txhdr->padding2 = 0; 585 txhdr->padding2 = 0;
597 586
598 /* TODO: add support for alternate retry TX rates */ 587 /* TODO: add support for alternate retry TX rates */
599 rate = control->tx_rate->hw_value; 588 rate = ieee80211_get_tx_rate(dev, info)->hw_value;
600 if (control->flags & IEEE80211_TXCTL_SHORT_PREAMBLE) 589 if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE)
601 rate |= 0x10; 590 rate |= 0x10;
602 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS) 591 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
603 rate |= 0x40; 592 rate |= 0x40;
604 else if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) 593 else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT)
605 rate |= 0x20; 594 rate |= 0x20;
606 memset(txhdr->rateset, rate, 8); 595 memset(txhdr->rateset, rate, 8);
607 txhdr->wep_key_present = 0; 596 txhdr->wep_key_present = 0;
608 txhdr->wep_key_len = 0; 597 txhdr->wep_key_len = 0;
609 txhdr->frame_type = cpu_to_le32(control->queue + 4); 598 txhdr->frame_type = cpu_to_le32(skb_get_queue_mapping(skb) + 4);
610 txhdr->magic4 = 0; 599 txhdr->magic4 = 0;
611 txhdr->antenna = (control->antenna_sel_tx == 0) ? 600 txhdr->antenna = (info->antenna_sel_tx == 0) ?
612 2 : control->antenna_sel_tx - 1; 601 2 : info->antenna_sel_tx - 1;
613 txhdr->output_power = 0x7f; // HW Maximum 602 txhdr->output_power = 0x7f; // HW Maximum
614 txhdr->magic5 = (control->flags & IEEE80211_TXCTL_NO_ACK) ? 603 txhdr->magic5 = (info->flags & IEEE80211_TX_CTL_NO_ACK) ?
615 0 : ((rate > 0x3) ? cpu_to_le32(0x33) : cpu_to_le32(0x23)); 604 0 : ((rate > 0x3) ? cpu_to_le32(0x33) : cpu_to_le32(0x23));
616 if (padding) 605 if (padding)
617 txhdr->align[0] = padding; 606 txhdr->align[0] = padding;
618 607
608 /* modifies skb->cb and with it info, so must be last! */
609 p54_assign_address(dev, skb, hdr, skb->len);
610
619 priv->tx(dev, hdr, skb->len, 0); 611 priv->tx(dev, hdr, skb->len, 0);
620 return 0; 612 return 0;
621} 613}
@@ -638,7 +630,7 @@ static int p54_set_filter(struct ieee80211_hw *dev, u16 filter_type,
638 filter = (struct p54_tx_control_filter *) hdr->data; 630 filter = (struct p54_tx_control_filter *) hdr->data;
639 hdr->magic1 = cpu_to_le16(0x8001); 631 hdr->magic1 = cpu_to_le16(0x8001);
640 hdr->len = cpu_to_le16(sizeof(*filter)); 632 hdr->len = cpu_to_le16(sizeof(*filter));
641 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*filter), NULL); 633 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*filter));
642 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET); 634 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET);
643 635
644 filter->filter_type = cpu_to_le16(filter_type); 636 filter->filter_type = cpu_to_le16(filter_type);
@@ -682,7 +674,7 @@ static int p54_set_freq(struct ieee80211_hw *dev, __le16 freq)
682 hdr->magic1 = cpu_to_le16(0x8001); 674 hdr->magic1 = cpu_to_le16(0x8001);
683 hdr->len = cpu_to_le16(sizeof(*chan)); 675 hdr->len = cpu_to_le16(sizeof(*chan));
684 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE); 676 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE);
685 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + payload_len, NULL); 677 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + payload_len);
686 678
687 chan->magic1 = cpu_to_le16(0x1); 679 chan->magic1 = cpu_to_le16(0x1);
688 chan->magic2 = cpu_to_le16(0x0); 680 chan->magic2 = cpu_to_le16(0x0);
@@ -755,7 +747,7 @@ static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
755 hdr->magic1 = cpu_to_le16(0x8001); 747 hdr->magic1 = cpu_to_le16(0x8001);
756 hdr->len = cpu_to_le16(sizeof(*led)); 748 hdr->len = cpu_to_le16(sizeof(*led));
757 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED); 749 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED);
758 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led), NULL); 750 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led));
759 751
760 led = (struct p54_tx_control_led *) hdr->data; 752 led = (struct p54_tx_control_led *) hdr->data;
761 led->mode = cpu_to_le16(mode); 753 led->mode = cpu_to_le16(mode);
@@ -805,7 +797,7 @@ static void p54_set_vdcf(struct ieee80211_hw *dev)
805 797
806 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len; 798 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
807 799
808 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf), NULL); 800 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf));
809 801
810 vdcf = (struct p54_tx_control_vdcf *) hdr->data; 802 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
811 803
@@ -841,12 +833,8 @@ static void p54_stop(struct ieee80211_hw *dev)
841{ 833{
842 struct p54_common *priv = dev->priv; 834 struct p54_common *priv = dev->priv;
843 struct sk_buff *skb; 835 struct sk_buff *skb;
844 while ((skb = skb_dequeue(&priv->tx_queue))) { 836 while ((skb = skb_dequeue(&priv->tx_queue)))
845 struct memrecord *range = (struct memrecord *)&skb->cb;
846 if (range->control)
847 kfree(range->control);
848 kfree_skb(skb); 837 kfree_skb(skb);
849 }
850 priv->stop(dev); 838 priv->stop(dev);
851 priv->mode = IEEE80211_IF_TYPE_INVALID; 839 priv->mode = IEEE80211_IF_TYPE_INVALID;
852} 840}
@@ -936,7 +924,7 @@ static void p54_configure_filter(struct ieee80211_hw *dev,
936 } 924 }
937} 925}
938 926
939static int p54_conf_tx(struct ieee80211_hw *dev, int queue, 927static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue,
940 const struct ieee80211_tx_queue_params *params) 928 const struct ieee80211_tx_queue_params *params)
941{ 929{
942 struct p54_common *priv = dev->priv; 930 struct p54_common *priv = dev->priv;
@@ -945,7 +933,7 @@ static int p54_conf_tx(struct ieee80211_hw *dev, int queue,
945 vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *) 933 vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *)
946 ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data); 934 ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data);
947 935
948 if ((params) && !((queue < 0) || (queue > 4))) { 936 if ((params) && !(queue > 4)) {
949 P54_SET_QUEUE(vdcf->queue[queue], params->aifs, 937 P54_SET_QUEUE(vdcf->queue[queue], params->aifs,
950 params->cw_min, params->cw_max, params->txop); 938 params->cw_min, params->cw_max, params->txop);
951 } else 939 } else
@@ -967,11 +955,8 @@ static int p54_get_tx_stats(struct ieee80211_hw *dev,
967 struct ieee80211_tx_queue_stats *stats) 955 struct ieee80211_tx_queue_stats *stats)
968{ 956{
969 struct p54_common *priv = dev->priv; 957 struct p54_common *priv = dev->priv;
970 unsigned int i;
971 958
972 for (i = 0; i < dev->queues; i++) 959 memcpy(stats, &priv->tx_stats, sizeof(stats[0]) * dev->queues);
973 memcpy(&stats->data[i], &priv->tx_stats.data[i],
974 sizeof(stats->data[i]));
975 960
976 return 0; 961 return 0;
977} 962}
@@ -1004,11 +989,12 @@ struct ieee80211_hw *p54_init_common(size_t priv_data_len)
1004 skb_queue_head_init(&priv->tx_queue); 989 skb_queue_head_init(&priv->tx_queue);
1005 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz; 990 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz;
1006 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */ 991 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */
1007 IEEE80211_HW_RX_INCLUDES_FCS; 992 IEEE80211_HW_RX_INCLUDES_FCS |
993 IEEE80211_HW_SIGNAL_UNSPEC;
1008 dev->channel_change_time = 1000; /* TODO: find actual value */ 994 dev->channel_change_time = 1000; /* TODO: find actual value */
1009 dev->max_rssi = 127; 995 dev->max_signal = 127;
1010 996
1011 priv->tx_stats.data[0].limit = 5; 997 priv->tx_stats[0].limit = 5;
1012 dev->queues = 1; 998 dev->queues = 1;
1013 999
1014 dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 + 1000 dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 +
diff --git a/drivers/net/wireless/p54/p54common.h b/drivers/net/wireless/p54/p54common.h
index c15b56e1d75e..2245fcce92dc 100644
--- a/drivers/net/wireless/p54/p54common.h
+++ b/drivers/net/wireless/p54/p54common.h
@@ -152,7 +152,6 @@ struct pda_pa_curve_data {
152struct memrecord { 152struct memrecord {
153 u32 start_addr; 153 u32 start_addr;
154 u32 end_addr; 154 u32 end_addr;
155 struct ieee80211_tx_control *control;
156}; 155};
157 156
158struct p54_eeprom_lm86 { 157struct p54_eeprom_lm86 {
diff --git a/drivers/net/wireless/p54/p54pci.c b/drivers/net/wireless/p54/p54pci.c
index fa527723fbe0..7dd4add4bf4e 100644
--- a/drivers/net/wireless/p54/p54pci.c
+++ b/drivers/net/wireless/p54/p54pci.c
@@ -665,7 +665,7 @@ static int p54p_resume(struct pci_dev *pdev)
665 665
666 if (priv->common.mode != IEEE80211_IF_TYPE_INVALID) { 666 if (priv->common.mode != IEEE80211_IF_TYPE_INVALID) {
667 p54p_open(dev); 667 p54p_open(dev);
668 ieee80211_start_queues(dev); 668 ieee80211_wake_queues(dev);
669 } 669 }
670 670
671 return 0; 671 return 0;
diff --git a/drivers/net/wireless/prism54/isl_ioctl.c b/drivers/net/wireless/prism54/isl_ioctl.c
index 5b375b289036..97fa14e0a479 100644
--- a/drivers/net/wireless/prism54/isl_ioctl.c
+++ b/drivers/net/wireless/prism54/isl_ioctl.c
@@ -571,8 +571,9 @@ prism54_set_scan(struct net_device *dev, struct iw_request_info *info,
571 */ 571 */
572 572
573static char * 573static char *
574prism54_translate_bss(struct net_device *ndev, char *current_ev, 574prism54_translate_bss(struct net_device *ndev, struct iw_request_info *info,
575 char *end_buf, struct obj_bss *bss, char noise) 575 char *current_ev, char *end_buf, struct obj_bss *bss,
576 char noise)
576{ 577{
577 struct iw_event iwe; /* Temporary buffer */ 578 struct iw_event iwe; /* Temporary buffer */
578 short cap; 579 short cap;
@@ -584,8 +585,8 @@ prism54_translate_bss(struct net_device *ndev, char *current_ev,
584 memcpy(iwe.u.ap_addr.sa_data, bss->address, 6); 585 memcpy(iwe.u.ap_addr.sa_data, bss->address, 6);
585 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 586 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
586 iwe.cmd = SIOCGIWAP; 587 iwe.cmd = SIOCGIWAP;
587 current_ev = 588 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
588 iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_ADDR_LEN); 589 &iwe, IW_EV_ADDR_LEN);
589 590
590 /* The following entries will be displayed in the same order we give them */ 591 /* The following entries will be displayed in the same order we give them */
591 592
@@ -593,7 +594,7 @@ prism54_translate_bss(struct net_device *ndev, char *current_ev,
593 iwe.u.data.length = bss->ssid.length; 594 iwe.u.data.length = bss->ssid.length;
594 iwe.u.data.flags = 1; 595 iwe.u.data.flags = 1;
595 iwe.cmd = SIOCGIWESSID; 596 iwe.cmd = SIOCGIWESSID;
596 current_ev = iwe_stream_add_point(current_ev, end_buf, 597 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
597 &iwe, bss->ssid.octets); 598 &iwe, bss->ssid.octets);
598 599
599 /* Capabilities */ 600 /* Capabilities */
@@ -610,9 +611,8 @@ prism54_translate_bss(struct net_device *ndev, char *current_ev,
610 iwe.u.mode = IW_MODE_ADHOC; 611 iwe.u.mode = IW_MODE_ADHOC;
611 iwe.cmd = SIOCGIWMODE; 612 iwe.cmd = SIOCGIWMODE;
612 if (iwe.u.mode) 613 if (iwe.u.mode)
613 current_ev = 614 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
614 iwe_stream_add_event(current_ev, end_buf, &iwe, 615 &iwe, IW_EV_UINT_LEN);
615 IW_EV_UINT_LEN);
616 616
617 /* Encryption capability */ 617 /* Encryption capability */
618 if (cap & CAP_CRYPT) 618 if (cap & CAP_CRYPT)
@@ -621,14 +621,15 @@ prism54_translate_bss(struct net_device *ndev, char *current_ev,
621 iwe.u.data.flags = IW_ENCODE_DISABLED; 621 iwe.u.data.flags = IW_ENCODE_DISABLED;
622 iwe.u.data.length = 0; 622 iwe.u.data.length = 0;
623 iwe.cmd = SIOCGIWENCODE; 623 iwe.cmd = SIOCGIWENCODE;
624 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, NULL); 624 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
625 &iwe, NULL);
625 626
626 /* Add frequency. (short) bss->channel is the frequency in MHz */ 627 /* Add frequency. (short) bss->channel is the frequency in MHz */
627 iwe.u.freq.m = bss->channel; 628 iwe.u.freq.m = bss->channel;
628 iwe.u.freq.e = 6; 629 iwe.u.freq.e = 6;
629 iwe.cmd = SIOCGIWFREQ; 630 iwe.cmd = SIOCGIWFREQ;
630 current_ev = 631 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
631 iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_FREQ_LEN); 632 &iwe, IW_EV_FREQ_LEN);
632 633
633 /* Add quality statistics */ 634 /* Add quality statistics */
634 iwe.u.qual.level = bss->rssi; 635 iwe.u.qual.level = bss->rssi;
@@ -636,20 +637,20 @@ prism54_translate_bss(struct net_device *ndev, char *current_ev,
636 /* do a simple SNR for quality */ 637 /* do a simple SNR for quality */
637 iwe.u.qual.qual = bss->rssi - noise; 638 iwe.u.qual.qual = bss->rssi - noise;
638 iwe.cmd = IWEVQUAL; 639 iwe.cmd = IWEVQUAL;
639 current_ev = 640 current_ev = iwe_stream_add_event(info, current_ev, end_buf,
640 iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_QUAL_LEN); 641 &iwe, IW_EV_QUAL_LEN);
641 642
642 /* Add WPA/RSN Information Element, if any */ 643 /* Add WPA/RSN Information Element, if any */
643 wpa_ie_len = prism54_wpa_bss_ie_get(priv, bss->address, wpa_ie); 644 wpa_ie_len = prism54_wpa_bss_ie_get(priv, bss->address, wpa_ie);
644 if (wpa_ie_len > 0) { 645 if (wpa_ie_len > 0) {
645 iwe.cmd = IWEVGENIE; 646 iwe.cmd = IWEVGENIE;
646 iwe.u.data.length = min(wpa_ie_len, (size_t)MAX_WPA_IE_LEN); 647 iwe.u.data.length = min(wpa_ie_len, (size_t)MAX_WPA_IE_LEN);
647 current_ev = iwe_stream_add_point(current_ev, end_buf, 648 current_ev = iwe_stream_add_point(info, current_ev, end_buf,
648 &iwe, wpa_ie); 649 &iwe, wpa_ie);
649 } 650 }
650 /* Do the bitrates */ 651 /* Do the bitrates */
651 { 652 {
652 char * current_val = current_ev + IW_EV_LCP_LEN; 653 char *current_val = current_ev + iwe_stream_lcp_len(info);
653 int i; 654 int i;
654 int mask; 655 int mask;
655 656
@@ -662,14 +663,14 @@ prism54_translate_bss(struct net_device *ndev, char *current_ev,
662 for(i = 0; i < sizeof(scan_rate_list); i++) { 663 for(i = 0; i < sizeof(scan_rate_list); i++) {
663 if(bss->rates & mask) { 664 if(bss->rates & mask) {
664 iwe.u.bitrate.value = (scan_rate_list[i] * 500000); 665 iwe.u.bitrate.value = (scan_rate_list[i] * 500000);
665 current_val = iwe_stream_add_value(current_ev, current_val, 666 current_val = iwe_stream_add_value(
666 end_buf, &iwe, 667 info, current_ev, current_val,
667 IW_EV_PARAM_LEN); 668 end_buf, &iwe, IW_EV_PARAM_LEN);
668 } 669 }
669 mask <<= 1; 670 mask <<= 1;
670 } 671 }
671 /* Check if we added any event */ 672 /* Check if we added any event */
672 if ((current_val - current_ev) > IW_EV_LCP_LEN) 673 if ((current_val - current_ev) > iwe_stream_lcp_len(info))
673 current_ev = current_val; 674 current_ev = current_val;
674 } 675 }
675 676
@@ -710,7 +711,7 @@ prism54_get_scan(struct net_device *ndev, struct iw_request_info *info,
710 711
711 /* ok now, scan the list and translate its info */ 712 /* ok now, scan the list and translate its info */
712 for (i = 0; i < (int) bsslist->nr; i++) { 713 for (i = 0; i < (int) bsslist->nr; i++) {
713 current_ev = prism54_translate_bss(ndev, current_ev, 714 current_ev = prism54_translate_bss(ndev, info, current_ev,
714 extra + dwrq->length, 715 extra + dwrq->length,
715 &(bsslist->bsslist[i]), 716 &(bsslist->bsslist[i]),
716 noise); 717 noise);
@@ -2704,6 +2705,7 @@ prism2_ioctl_scan_req(struct net_device *ndev,
2704 struct prism2_hostapd_param *param) 2705 struct prism2_hostapd_param *param)
2705{ 2706{
2706 islpci_private *priv = netdev_priv(ndev); 2707 islpci_private *priv = netdev_priv(ndev);
2708 struct iw_request_info info;
2707 int i, rvalue; 2709 int i, rvalue;
2708 struct obj_bsslist *bsslist; 2710 struct obj_bsslist *bsslist;
2709 u32 noise = 0; 2711 u32 noise = 0;
@@ -2727,9 +2729,12 @@ prism2_ioctl_scan_req(struct net_device *ndev,
2727 rvalue |= mgt_get_request(priv, DOT11_OID_BSSLIST, 0, NULL, &r); 2729 rvalue |= mgt_get_request(priv, DOT11_OID_BSSLIST, 0, NULL, &r);
2728 bsslist = r.ptr; 2730 bsslist = r.ptr;
2729 2731
2732 info.cmd = PRISM54_HOSTAPD;
2733 info.flags = 0;
2734
2730 /* ok now, scan the list and translate its info */ 2735 /* ok now, scan the list and translate its info */
2731 for (i = 0; i < min(IW_MAX_AP, (int) bsslist->nr); i++) 2736 for (i = 0; i < min(IW_MAX_AP, (int) bsslist->nr); i++)
2732 current_ev = prism54_translate_bss(ndev, current_ev, 2737 current_ev = prism54_translate_bss(ndev, &info, current_ev,
2733 extra + IW_SCAN_MAX_DATA, 2738 extra + IW_SCAN_MAX_DATA,
2734 &(bsslist->bsslist[i]), 2739 &(bsslist->bsslist[i]),
2735 noise); 2740 noise);
diff --git a/drivers/net/wireless/rndis_wlan.c b/drivers/net/wireless/rndis_wlan.c
index 18c9931e3267..00e965b9da75 100644
--- a/drivers/net/wireless/rndis_wlan.c
+++ b/drivers/net/wireless/rndis_wlan.c
@@ -310,8 +310,11 @@ enum wpa_key_mgmt { KEY_MGMT_802_1X, KEY_MGMT_PSK, KEY_MGMT_NONE,
310#define CAP_MODE_MASK 7 310#define CAP_MODE_MASK 7
311#define CAP_SUPPORT_TXPOWER 8 311#define CAP_SUPPORT_TXPOWER 8
312 312
313#define WORK_CONNECTION_EVENT (1<<0) 313#define WORK_LINK_UP (1<<0)
314#define WORK_SET_MULTICAST_LIST (1<<1) 314#define WORK_LINK_DOWN (1<<1)
315#define WORK_SET_MULTICAST_LIST (1<<2)
316
317#define COMMAND_BUFFER_SIZE (CONTROL_BUFFER_SIZE + sizeof(struct rndis_set))
315 318
316/* RNDIS device private data */ 319/* RNDIS device private data */
317struct rndis_wext_private { 320struct rndis_wext_private {
@@ -361,6 +364,8 @@ struct rndis_wext_private {
361 u8 *wpa_ie; 364 u8 *wpa_ie;
362 int wpa_cipher_pair; 365 int wpa_cipher_pair;
363 int wpa_cipher_group; 366 int wpa_cipher_group;
367
368 u8 command_buffer[COMMAND_BUFFER_SIZE];
364}; 369};
365 370
366 371
@@ -427,18 +432,23 @@ static int rndis_query_oid(struct usbnet *dev, __le32 oid, void *data, int *len)
427 buflen = *len + sizeof(*u.get); 432 buflen = *len + sizeof(*u.get);
428 if (buflen < CONTROL_BUFFER_SIZE) 433 if (buflen < CONTROL_BUFFER_SIZE)
429 buflen = CONTROL_BUFFER_SIZE; 434 buflen = CONTROL_BUFFER_SIZE;
430 u.buf = kmalloc(buflen, GFP_KERNEL); 435
431 if (!u.buf) 436 if (buflen > COMMAND_BUFFER_SIZE) {
432 return -ENOMEM; 437 u.buf = kmalloc(buflen, GFP_KERNEL);
438 if (!u.buf)
439 return -ENOMEM;
440 } else {
441 u.buf = priv->command_buffer;
442 }
443
444 mutex_lock(&priv->command_lock);
445
433 memset(u.get, 0, sizeof *u.get); 446 memset(u.get, 0, sizeof *u.get);
434 u.get->msg_type = RNDIS_MSG_QUERY; 447 u.get->msg_type = RNDIS_MSG_QUERY;
435 u.get->msg_len = ccpu2(sizeof *u.get); 448 u.get->msg_len = ccpu2(sizeof *u.get);
436 u.get->oid = oid; 449 u.get->oid = oid;
437 450
438 mutex_lock(&priv->command_lock); 451 ret = rndis_command(dev, u.header, buflen);
439 ret = rndis_command(dev, u.header);
440 mutex_unlock(&priv->command_lock);
441
442 if (ret == 0) { 452 if (ret == 0) {
443 ret = le32_to_cpu(u.get_c->len); 453 ret = le32_to_cpu(u.get_c->len);
444 *len = (*len > ret) ? ret : *len; 454 *len = (*len > ret) ? ret : *len;
@@ -446,7 +456,10 @@ static int rndis_query_oid(struct usbnet *dev, __le32 oid, void *data, int *len)
446 ret = rndis_error_status(u.get_c->status); 456 ret = rndis_error_status(u.get_c->status);
447 } 457 }
448 458
449 kfree(u.buf); 459 mutex_unlock(&priv->command_lock);
460
461 if (u.buf != priv->command_buffer)
462 kfree(u.buf);
450 return ret; 463 return ret;
451} 464}
452 465
@@ -465,9 +478,16 @@ static int rndis_set_oid(struct usbnet *dev, __le32 oid, void *data, int len)
465 buflen = len + sizeof(*u.set); 478 buflen = len + sizeof(*u.set);
466 if (buflen < CONTROL_BUFFER_SIZE) 479 if (buflen < CONTROL_BUFFER_SIZE)
467 buflen = CONTROL_BUFFER_SIZE; 480 buflen = CONTROL_BUFFER_SIZE;
468 u.buf = kmalloc(buflen, GFP_KERNEL); 481
469 if (!u.buf) 482 if (buflen > COMMAND_BUFFER_SIZE) {
470 return -ENOMEM; 483 u.buf = kmalloc(buflen, GFP_KERNEL);
484 if (!u.buf)
485 return -ENOMEM;
486 } else {
487 u.buf = priv->command_buffer;
488 }
489
490 mutex_lock(&priv->command_lock);
471 491
472 memset(u.set, 0, sizeof *u.set); 492 memset(u.set, 0, sizeof *u.set);
473 u.set->msg_type = RNDIS_MSG_SET; 493 u.set->msg_type = RNDIS_MSG_SET;
@@ -478,14 +498,14 @@ static int rndis_set_oid(struct usbnet *dev, __le32 oid, void *data, int len)
478 u.set->handle = ccpu2(0); 498 u.set->handle = ccpu2(0);
479 memcpy(u.buf + sizeof(*u.set), data, len); 499 memcpy(u.buf + sizeof(*u.set), data, len);
480 500
481 mutex_lock(&priv->command_lock); 501 ret = rndis_command(dev, u.header, buflen);
482 ret = rndis_command(dev, u.header);
483 mutex_unlock(&priv->command_lock);
484
485 if (ret == 0) 502 if (ret == 0)
486 ret = rndis_error_status(u.set_c->status); 503 ret = rndis_error_status(u.set_c->status);
487 504
488 kfree(u.buf); 505 mutex_unlock(&priv->command_lock);
506
507 if (u.buf != priv->command_buffer)
508 kfree(u.buf);
489 return ret; 509 return ret;
490} 510}
491 511
@@ -620,8 +640,7 @@ static void dsconfig_to_freq(unsigned int dsconfig, struct iw_freq *freq)
620static int freq_to_dsconfig(struct iw_freq *freq, unsigned int *dsconfig) 640static int freq_to_dsconfig(struct iw_freq *freq, unsigned int *dsconfig)
621{ 641{
622 if (freq->m < 1000 && freq->e == 0) { 642 if (freq->m < 1000 && freq->e == 0) {
623 if (freq->m >= 1 && 643 if (freq->m >= 1 && freq->m <= ARRAY_SIZE(freq_chan))
624 freq->m <= (sizeof(freq_chan) / sizeof(freq_chan[0])))
625 *dsconfig = freq_chan[freq->m - 1] * 1000; 644 *dsconfig = freq_chan[freq->m - 1] * 1000;
626 else 645 else
627 return -1; 646 return -1;
@@ -1135,7 +1154,7 @@ static int rndis_iw_get_range(struct net_device *dev,
1135 /* fill in 802.11g rates */ 1154 /* fill in 802.11g rates */
1136 if (has_80211g_rates) { 1155 if (has_80211g_rates) {
1137 num = range->num_bitrates; 1156 num = range->num_bitrates;
1138 for (i = 0; i < sizeof(rates_80211g); i++) { 1157 for (i = 0; i < ARRAY_SIZE(rates_80211g); i++) {
1139 for (j = 0; j < num; j++) { 1158 for (j = 0; j < num; j++) {
1140 if (range->bitrate[j] == 1159 if (range->bitrate[j] ==
1141 rates_80211g[i] * 1000000) 1160 rates_80211g[i] * 1000000)
@@ -1159,10 +1178,9 @@ static int rndis_iw_get_range(struct net_device *dev,
1159 range->throughput = 11 * 1000 * 1000 / 2; 1178 range->throughput = 11 * 1000 * 1000 / 2;
1160 } 1179 }
1161 1180
1162 range->num_channels = (sizeof(freq_chan)/sizeof(freq_chan[0])); 1181 range->num_channels = ARRAY_SIZE(freq_chan);
1163 1182
1164 for (i = 0; i < (sizeof(freq_chan)/sizeof(freq_chan[0])) && 1183 for (i = 0; i < ARRAY_SIZE(freq_chan) && i < IW_MAX_FREQUENCIES; i++) {
1165 i < IW_MAX_FREQUENCIES; i++) {
1166 range->freq[i].i = i + 1; 1184 range->freq[i].i = i + 1;
1167 range->freq[i].m = freq_chan[i] * 100000; 1185 range->freq[i].m = freq_chan[i] * 100000;
1168 range->freq[i].e = 1; 1186 range->freq[i].e = 1;
@@ -1630,7 +1648,9 @@ static int rndis_iw_set_scan(struct net_device *dev,
1630 1648
1631 1649
1632static char *rndis_translate_scan(struct net_device *dev, 1650static char *rndis_translate_scan(struct net_device *dev,
1633 char *cev, char *end_buf, struct ndis_80211_bssid_ex *bssid) 1651 struct iw_request_info *info, char *cev,
1652 char *end_buf,
1653 struct ndis_80211_bssid_ex *bssid)
1634{ 1654{
1635#ifdef DEBUG 1655#ifdef DEBUG
1636 struct usbnet *usbdev = dev->priv; 1656 struct usbnet *usbdev = dev->priv;
@@ -1649,14 +1669,14 @@ static char *rndis_translate_scan(struct net_device *dev,
1649 iwe.cmd = SIOCGIWAP; 1669 iwe.cmd = SIOCGIWAP;
1650 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 1670 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
1651 memcpy(iwe.u.ap_addr.sa_data, bssid->mac, ETH_ALEN); 1671 memcpy(iwe.u.ap_addr.sa_data, bssid->mac, ETH_ALEN);
1652 cev = iwe_stream_add_event(cev, end_buf, &iwe, IW_EV_ADDR_LEN); 1672 cev = iwe_stream_add_event(info, cev, end_buf, &iwe, IW_EV_ADDR_LEN);
1653 1673
1654 devdbg(usbdev, "SSID(%d) %s", le32_to_cpu(bssid->ssid.length), 1674 devdbg(usbdev, "SSID(%d) %s", le32_to_cpu(bssid->ssid.length),
1655 bssid->ssid.essid); 1675 bssid->ssid.essid);
1656 iwe.cmd = SIOCGIWESSID; 1676 iwe.cmd = SIOCGIWESSID;
1657 iwe.u.essid.length = le32_to_cpu(bssid->ssid.length); 1677 iwe.u.essid.length = le32_to_cpu(bssid->ssid.length);
1658 iwe.u.essid.flags = 1; 1678 iwe.u.essid.flags = 1;
1659 cev = iwe_stream_add_point(cev, end_buf, &iwe, bssid->ssid.essid); 1679 cev = iwe_stream_add_point(info, cev, end_buf, &iwe, bssid->ssid.essid);
1660 1680
1661 devdbg(usbdev, "MODE %d", le32_to_cpu(bssid->net_infra)); 1681 devdbg(usbdev, "MODE %d", le32_to_cpu(bssid->net_infra));
1662 iwe.cmd = SIOCGIWMODE; 1682 iwe.cmd = SIOCGIWMODE;
@@ -1672,12 +1692,12 @@ static char *rndis_translate_scan(struct net_device *dev,
1672 iwe.u.mode = IW_MODE_AUTO; 1692 iwe.u.mode = IW_MODE_AUTO;
1673 break; 1693 break;
1674 } 1694 }
1675 cev = iwe_stream_add_event(cev, end_buf, &iwe, IW_EV_UINT_LEN); 1695 cev = iwe_stream_add_event(info, cev, end_buf, &iwe, IW_EV_UINT_LEN);
1676 1696
1677 devdbg(usbdev, "FREQ %d kHz", le32_to_cpu(bssid->config.ds_config)); 1697 devdbg(usbdev, "FREQ %d kHz", le32_to_cpu(bssid->config.ds_config));
1678 iwe.cmd = SIOCGIWFREQ; 1698 iwe.cmd = SIOCGIWFREQ;
1679 dsconfig_to_freq(le32_to_cpu(bssid->config.ds_config), &iwe.u.freq); 1699 dsconfig_to_freq(le32_to_cpu(bssid->config.ds_config), &iwe.u.freq);
1680 cev = iwe_stream_add_event(cev, end_buf, &iwe, IW_EV_FREQ_LEN); 1700 cev = iwe_stream_add_event(info, cev, end_buf, &iwe, IW_EV_FREQ_LEN);
1681 1701
1682 devdbg(usbdev, "QUAL %d", le32_to_cpu(bssid->rssi)); 1702 devdbg(usbdev, "QUAL %d", le32_to_cpu(bssid->rssi));
1683 iwe.cmd = IWEVQUAL; 1703 iwe.cmd = IWEVQUAL;
@@ -1686,7 +1706,7 @@ static char *rndis_translate_scan(struct net_device *dev,
1686 iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED 1706 iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED
1687 | IW_QUAL_LEVEL_UPDATED 1707 | IW_QUAL_LEVEL_UPDATED
1688 | IW_QUAL_NOISE_INVALID; 1708 | IW_QUAL_NOISE_INVALID;
1689 cev = iwe_stream_add_event(cev, end_buf, &iwe, IW_EV_QUAL_LEN); 1709 cev = iwe_stream_add_event(info, cev, end_buf, &iwe, IW_EV_QUAL_LEN);
1690 1710
1691 devdbg(usbdev, "ENCODE %d", le32_to_cpu(bssid->privacy)); 1711 devdbg(usbdev, "ENCODE %d", le32_to_cpu(bssid->privacy));
1692 iwe.cmd = SIOCGIWENCODE; 1712 iwe.cmd = SIOCGIWENCODE;
@@ -1696,10 +1716,10 @@ static char *rndis_translate_scan(struct net_device *dev,
1696 else 1716 else
1697 iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; 1717 iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
1698 1718
1699 cev = iwe_stream_add_point(cev, end_buf, &iwe, NULL); 1719 cev = iwe_stream_add_point(info, cev, end_buf, &iwe, NULL);
1700 1720
1701 devdbg(usbdev, "RATES:"); 1721 devdbg(usbdev, "RATES:");
1702 current_val = cev + IW_EV_LCP_LEN; 1722 current_val = cev + iwe_stream_lcp_len(info);
1703 iwe.cmd = SIOCGIWRATE; 1723 iwe.cmd = SIOCGIWRATE;
1704 for (i = 0; i < sizeof(bssid->rates); i++) { 1724 for (i = 0; i < sizeof(bssid->rates); i++) {
1705 if (bssid->rates[i] & 0x7f) { 1725 if (bssid->rates[i] & 0x7f) {
@@ -1707,13 +1727,13 @@ static char *rndis_translate_scan(struct net_device *dev,
1707 ((bssid->rates[i] & 0x7f) * 1727 ((bssid->rates[i] & 0x7f) *
1708 500000); 1728 500000);
1709 devdbg(usbdev, " %d", iwe.u.bitrate.value); 1729 devdbg(usbdev, " %d", iwe.u.bitrate.value);
1710 current_val = iwe_stream_add_value(cev, 1730 current_val = iwe_stream_add_value(info, cev,
1711 current_val, end_buf, &iwe, 1731 current_val, end_buf, &iwe,
1712 IW_EV_PARAM_LEN); 1732 IW_EV_PARAM_LEN);
1713 } 1733 }
1714 } 1734 }
1715 1735
1716 if ((current_val - cev) > IW_EV_LCP_LEN) 1736 if ((current_val - cev) > iwe_stream_lcp_len(info))
1717 cev = current_val; 1737 cev = current_val;
1718 1738
1719 beacon = le32_to_cpu(bssid->config.beacon_period); 1739 beacon = le32_to_cpu(bssid->config.beacon_period);
@@ -1721,14 +1741,14 @@ static char *rndis_translate_scan(struct net_device *dev,
1721 iwe.cmd = IWEVCUSTOM; 1741 iwe.cmd = IWEVCUSTOM;
1722 snprintf(sbuf, sizeof(sbuf), "bcn_int=%d", beacon); 1742 snprintf(sbuf, sizeof(sbuf), "bcn_int=%d", beacon);
1723 iwe.u.data.length = strlen(sbuf); 1743 iwe.u.data.length = strlen(sbuf);
1724 cev = iwe_stream_add_point(cev, end_buf, &iwe, sbuf); 1744 cev = iwe_stream_add_point(info, cev, end_buf, &iwe, sbuf);
1725 1745
1726 atim = le32_to_cpu(bssid->config.atim_window); 1746 atim = le32_to_cpu(bssid->config.atim_window);
1727 devdbg(usbdev, "ATIM %d", atim); 1747 devdbg(usbdev, "ATIM %d", atim);
1728 iwe.cmd = IWEVCUSTOM; 1748 iwe.cmd = IWEVCUSTOM;
1729 snprintf(sbuf, sizeof(sbuf), "atim=%u", atim); 1749 snprintf(sbuf, sizeof(sbuf), "atim=%u", atim);
1730 iwe.u.data.length = strlen(sbuf); 1750 iwe.u.data.length = strlen(sbuf);
1731 cev = iwe_stream_add_point(cev, end_buf, &iwe, sbuf); 1751 cev = iwe_stream_add_point(info, cev, end_buf, &iwe, sbuf);
1732 1752
1733 ie = (void *)(bssid->ies + sizeof(struct ndis_80211_fixed_ies)); 1753 ie = (void *)(bssid->ies + sizeof(struct ndis_80211_fixed_ies));
1734 ie_len = min(bssid_len - (int)sizeof(*bssid), 1754 ie_len = min(bssid_len - (int)sizeof(*bssid),
@@ -1742,7 +1762,7 @@ static char *rndis_translate_scan(struct net_device *dev,
1742 (ie->id == MFIE_TYPE_RSN) ? 2 : 1); 1762 (ie->id == MFIE_TYPE_RSN) ? 2 : 1);
1743 iwe.cmd = IWEVGENIE; 1763 iwe.cmd = IWEVGENIE;
1744 iwe.u.data.length = min(ie->len + 2, MAX_WPA_IE_LEN); 1764 iwe.u.data.length = min(ie->len + 2, MAX_WPA_IE_LEN);
1745 cev = iwe_stream_add_point(cev, end_buf, &iwe, 1765 cev = iwe_stream_add_point(info, cev, end_buf, &iwe,
1746 (u8 *)ie); 1766 (u8 *)ie);
1747 } 1767 }
1748 1768
@@ -1785,8 +1805,8 @@ static int rndis_iw_get_scan(struct net_device *dev,
1785 devdbg(usbdev, "SIOCGIWSCAN: %d BSSIDs found", count); 1805 devdbg(usbdev, "SIOCGIWSCAN: %d BSSIDs found", count);
1786 1806
1787 while (count && ((void *)bssid + bssid_len) <= (buf + len)) { 1807 while (count && ((void *)bssid + bssid_len) <= (buf + len)) {
1788 cev = rndis_translate_scan(dev, cev, extra + IW_SCAN_MAX_DATA, 1808 cev = rndis_translate_scan(dev, info, cev,
1789 bssid); 1809 extra + IW_SCAN_MAX_DATA, bssid);
1790 bssid = (void *)bssid + bssid_len; 1810 bssid = (void *)bssid + bssid_len;
1791 bssid_len = le32_to_cpu(bssid->length); 1811 bssid_len = le32_to_cpu(bssid->length);
1792 count--; 1812 count--;
@@ -2213,7 +2233,9 @@ static void rndis_wext_worker(struct work_struct *work)
2213 int assoc_size = sizeof(*info) + IW_CUSTOM_MAX + 32; 2233 int assoc_size = sizeof(*info) + IW_CUSTOM_MAX + 32;
2214 int ret, offset; 2234 int ret, offset;
2215 2235
2216 if (test_and_clear_bit(WORK_CONNECTION_EVENT, &priv->work_pending)) { 2236 if (test_and_clear_bit(WORK_LINK_UP, &priv->work_pending)) {
2237 netif_carrier_on(usbdev->net);
2238
2217 info = kzalloc(assoc_size, GFP_KERNEL); 2239 info = kzalloc(assoc_size, GFP_KERNEL);
2218 if (!info) 2240 if (!info)
2219 goto get_bssid; 2241 goto get_bssid;
@@ -2251,6 +2273,15 @@ get_bssid:
2251 } 2273 }
2252 } 2274 }
2253 2275
2276 if (test_and_clear_bit(WORK_LINK_DOWN, &priv->work_pending)) {
2277 netif_carrier_off(usbdev->net);
2278
2279 evt.data.flags = 0;
2280 evt.data.length = 0;
2281 memset(evt.ap_addr.sa_data, 0, ETH_ALEN);
2282 wireless_send_event(usbdev->net, SIOCGIWAP, &evt, NULL);
2283 }
2284
2254 if (test_and_clear_bit(WORK_SET_MULTICAST_LIST, &priv->work_pending)) 2285 if (test_and_clear_bit(WORK_SET_MULTICAST_LIST, &priv->work_pending))
2255 set_multicast_list(usbdev); 2286 set_multicast_list(usbdev);
2256} 2287}
@@ -2260,29 +2291,24 @@ static void rndis_wext_set_multicast_list(struct net_device *dev)
2260 struct usbnet *usbdev = dev->priv; 2291 struct usbnet *usbdev = dev->priv;
2261 struct rndis_wext_private *priv = get_rndis_wext_priv(usbdev); 2292 struct rndis_wext_private *priv = get_rndis_wext_priv(usbdev);
2262 2293
2294 if (test_bit(WORK_SET_MULTICAST_LIST, &priv->work_pending))
2295 return;
2296
2263 set_bit(WORK_SET_MULTICAST_LIST, &priv->work_pending); 2297 set_bit(WORK_SET_MULTICAST_LIST, &priv->work_pending);
2264 queue_work(priv->workqueue, &priv->work); 2298 queue_work(priv->workqueue, &priv->work);
2265} 2299}
2266 2300
2267static void rndis_wext_link_change(struct usbnet *dev, int state) 2301static void rndis_wext_link_change(struct usbnet *usbdev, int state)
2268{ 2302{
2269 struct rndis_wext_private *priv = get_rndis_wext_priv(dev); 2303 struct rndis_wext_private *priv = get_rndis_wext_priv(usbdev);
2270 union iwreq_data evt;
2271 2304
2272 if (state) { 2305 /* queue work to avoid recursive calls into rndis_command */
2273 /* queue work to avoid recursive calls into rndis_command */ 2306 set_bit(state ? WORK_LINK_UP : WORK_LINK_DOWN, &priv->work_pending);
2274 set_bit(WORK_CONNECTION_EVENT, &priv->work_pending); 2307 queue_work(priv->workqueue, &priv->work);
2275 queue_work(priv->workqueue, &priv->work);
2276 } else {
2277 evt.data.flags = 0;
2278 evt.data.length = 0;
2279 memset(evt.ap_addr.sa_data, 0, ETH_ALEN);
2280 wireless_send_event(dev->net, SIOCGIWAP, &evt, NULL);
2281 }
2282} 2308}
2283 2309
2284 2310
2285static int rndis_wext_get_caps(struct usbnet *dev) 2311static int rndis_wext_get_caps(struct usbnet *usbdev)
2286{ 2312{
2287 struct { 2313 struct {
2288 __le32 num_items; 2314 __le32 num_items;
@@ -2290,18 +2316,18 @@ static int rndis_wext_get_caps(struct usbnet *dev)
2290 } networks_supported; 2316 } networks_supported;
2291 int len, retval, i, n; 2317 int len, retval, i, n;
2292 __le32 tx_power; 2318 __le32 tx_power;
2293 struct rndis_wext_private *priv = get_rndis_wext_priv(dev); 2319 struct rndis_wext_private *priv = get_rndis_wext_priv(usbdev);
2294 2320
2295 /* determine if supports setting txpower */ 2321 /* determine if supports setting txpower */
2296 len = sizeof(tx_power); 2322 len = sizeof(tx_power);
2297 retval = rndis_query_oid(dev, OID_802_11_TX_POWER_LEVEL, &tx_power, 2323 retval = rndis_query_oid(usbdev, OID_802_11_TX_POWER_LEVEL, &tx_power,
2298 &len); 2324 &len);
2299 if (retval == 0 && le32_to_cpu(tx_power) != 0xFF) 2325 if (retval == 0 && le32_to_cpu(tx_power) != 0xFF)
2300 priv->caps |= CAP_SUPPORT_TXPOWER; 2326 priv->caps |= CAP_SUPPORT_TXPOWER;
2301 2327
2302 /* determine supported modes */ 2328 /* determine supported modes */
2303 len = sizeof(networks_supported); 2329 len = sizeof(networks_supported);
2304 retval = rndis_query_oid(dev, OID_802_11_NETWORK_TYPES_SUPPORTED, 2330 retval = rndis_query_oid(usbdev, OID_802_11_NETWORK_TYPES_SUPPORTED,
2305 &networks_supported, &len); 2331 &networks_supported, &len);
2306 if (retval >= 0) { 2332 if (retval >= 0) {
2307 n = le32_to_cpu(networks_supported.num_items); 2333 n = le32_to_cpu(networks_supported.num_items);
@@ -2440,9 +2466,9 @@ end:
2440} 2466}
2441 2467
2442 2468
2443static int bcm4320_early_init(struct usbnet *dev) 2469static int bcm4320_early_init(struct usbnet *usbdev)
2444{ 2470{
2445 struct rndis_wext_private *priv = get_rndis_wext_priv(dev); 2471 struct rndis_wext_private *priv = get_rndis_wext_priv(usbdev);
2446 char buf[8]; 2472 char buf[8];
2447 2473
2448 /* Early initialization settings, setting these won't have effect 2474 /* Early initialization settings, setting these won't have effect
@@ -2490,51 +2516,48 @@ static int bcm4320_early_init(struct usbnet *dev)
2490 else 2516 else
2491 priv->param_workaround_interval = modparam_workaround_interval; 2517 priv->param_workaround_interval = modparam_workaround_interval;
2492 2518
2493 rndis_set_config_parameter_str(dev, "Country", priv->param_country); 2519 rndis_set_config_parameter_str(usbdev, "Country", priv->param_country);
2494 rndis_set_config_parameter_str(dev, "FrameBursting", 2520 rndis_set_config_parameter_str(usbdev, "FrameBursting",
2495 priv->param_frameburst ? "1" : "0"); 2521 priv->param_frameburst ? "1" : "0");
2496 rndis_set_config_parameter_str(dev, "Afterburner", 2522 rndis_set_config_parameter_str(usbdev, "Afterburner",
2497 priv->param_afterburner ? "1" : "0"); 2523 priv->param_afterburner ? "1" : "0");
2498 sprintf(buf, "%d", priv->param_power_save); 2524 sprintf(buf, "%d", priv->param_power_save);
2499 rndis_set_config_parameter_str(dev, "PowerSaveMode", buf); 2525 rndis_set_config_parameter_str(usbdev, "PowerSaveMode", buf);
2500 sprintf(buf, "%d", priv->param_power_output); 2526 sprintf(buf, "%d", priv->param_power_output);
2501 rndis_set_config_parameter_str(dev, "PwrOut", buf); 2527 rndis_set_config_parameter_str(usbdev, "PwrOut", buf);
2502 sprintf(buf, "%d", priv->param_roamtrigger); 2528 sprintf(buf, "%d", priv->param_roamtrigger);
2503 rndis_set_config_parameter_str(dev, "RoamTrigger", buf); 2529 rndis_set_config_parameter_str(usbdev, "RoamTrigger", buf);
2504 sprintf(buf, "%d", priv->param_roamdelta); 2530 sprintf(buf, "%d", priv->param_roamdelta);
2505 rndis_set_config_parameter_str(dev, "RoamDelta", buf); 2531 rndis_set_config_parameter_str(usbdev, "RoamDelta", buf);
2506 2532
2507 return 0; 2533 return 0;
2508} 2534}
2509 2535
2510 2536
2511static int rndis_wext_bind(struct usbnet *dev, struct usb_interface *intf) 2537static int rndis_wext_bind(struct usbnet *usbdev, struct usb_interface *intf)
2512{ 2538{
2513 struct net_device *net = dev->net;
2514 struct rndis_wext_private *priv; 2539 struct rndis_wext_private *priv;
2515 int retval, len; 2540 int retval, len;
2516 __le32 tmp; 2541 __le32 tmp;
2517 2542
2518 /* allocate rndis private data */ 2543 /* allocate rndis private data */
2519 priv = kmalloc(sizeof(struct rndis_wext_private), GFP_KERNEL); 2544 priv = kzalloc(sizeof(struct rndis_wext_private), GFP_KERNEL);
2520 if (!priv) 2545 if (!priv)
2521 return -ENOMEM; 2546 return -ENOMEM;
2522 2547
2523 /* These have to be initialized before calling generic_rndis_bind(). 2548 /* These have to be initialized before calling generic_rndis_bind().
2524 * Otherwise we'll be in big trouble in rndis_wext_early_init(). 2549 * Otherwise we'll be in big trouble in rndis_wext_early_init().
2525 */ 2550 */
2526 dev->driver_priv = priv; 2551 usbdev->driver_priv = priv;
2527 memset(priv, 0, sizeof(*priv));
2528 memset(priv->name, 0, sizeof(priv->name));
2529 strcpy(priv->name, "IEEE802.11"); 2552 strcpy(priv->name, "IEEE802.11");
2530 net->wireless_handlers = &rndis_iw_handlers; 2553 usbdev->net->wireless_handlers = &rndis_iw_handlers;
2531 priv->usbdev = dev; 2554 priv->usbdev = usbdev;
2532 2555
2533 mutex_init(&priv->command_lock); 2556 mutex_init(&priv->command_lock);
2534 spin_lock_init(&priv->stats_lock); 2557 spin_lock_init(&priv->stats_lock);
2535 2558
2536 /* try bind rndis_host */ 2559 /* try bind rndis_host */
2537 retval = generic_rndis_bind(dev, intf, FLAG_RNDIS_PHYM_WIRELESS); 2560 retval = generic_rndis_bind(usbdev, intf, FLAG_RNDIS_PHYM_WIRELESS);
2538 if (retval < 0) 2561 if (retval < 0)
2539 goto fail; 2562 goto fail;
2540 2563
@@ -2545,20 +2568,21 @@ static int rndis_wext_bind(struct usbnet *dev, struct usb_interface *intf)
2545 * rndis_host wants to avoid all OID as much as possible 2568 * rndis_host wants to avoid all OID as much as possible
2546 * so do promisc/multicast handling in rndis_wext. 2569 * so do promisc/multicast handling in rndis_wext.
2547 */ 2570 */
2548 dev->net->set_multicast_list = rndis_wext_set_multicast_list; 2571 usbdev->net->set_multicast_list = rndis_wext_set_multicast_list;
2549 tmp = RNDIS_PACKET_TYPE_DIRECTED | RNDIS_PACKET_TYPE_BROADCAST; 2572 tmp = RNDIS_PACKET_TYPE_DIRECTED | RNDIS_PACKET_TYPE_BROADCAST;
2550 retval = rndis_set_oid(dev, OID_GEN_CURRENT_PACKET_FILTER, &tmp, 2573 retval = rndis_set_oid(usbdev, OID_GEN_CURRENT_PACKET_FILTER, &tmp,
2551 sizeof(tmp)); 2574 sizeof(tmp));
2552 2575
2553 len = sizeof(tmp); 2576 len = sizeof(tmp);
2554 retval = rndis_query_oid(dev, OID_802_3_MAXIMUM_LIST_SIZE, &tmp, &len); 2577 retval = rndis_query_oid(usbdev, OID_802_3_MAXIMUM_LIST_SIZE, &tmp,
2578 &len);
2555 priv->multicast_size = le32_to_cpu(tmp); 2579 priv->multicast_size = le32_to_cpu(tmp);
2556 if (retval < 0 || priv->multicast_size < 0) 2580 if (retval < 0 || priv->multicast_size < 0)
2557 priv->multicast_size = 0; 2581 priv->multicast_size = 0;
2558 if (priv->multicast_size > 0) 2582 if (priv->multicast_size > 0)
2559 dev->net->flags |= IFF_MULTICAST; 2583 usbdev->net->flags |= IFF_MULTICAST;
2560 else 2584 else
2561 dev->net->flags &= ~IFF_MULTICAST; 2585 usbdev->net->flags &= ~IFF_MULTICAST;
2562 2586
2563 priv->iwstats.qual.qual = 0; 2587 priv->iwstats.qual.qual = 0;
2564 priv->iwstats.qual.level = 0; 2588 priv->iwstats.qual.level = 0;
@@ -2568,12 +2592,13 @@ static int rndis_wext_bind(struct usbnet *dev, struct usb_interface *intf)
2568 | IW_QUAL_QUAL_INVALID 2592 | IW_QUAL_QUAL_INVALID
2569 | IW_QUAL_LEVEL_INVALID; 2593 | IW_QUAL_LEVEL_INVALID;
2570 2594
2571 rndis_wext_get_caps(dev); 2595 rndis_wext_get_caps(usbdev);
2572 set_default_iw_params(dev); 2596 set_default_iw_params(usbdev);
2573 2597
2574 /* turn radio on */ 2598 /* turn radio on */
2575 priv->radio_on = 1; 2599 priv->radio_on = 1;
2576 disassociate(dev, 1); 2600 disassociate(usbdev, 1);
2601 netif_carrier_off(usbdev->net);
2577 2602
2578 /* because rndis_command() sleeps we need to use workqueue */ 2603 /* because rndis_command() sleeps we need to use workqueue */
2579 priv->workqueue = create_singlethread_workqueue("rndis_wlan"); 2604 priv->workqueue = create_singlethread_workqueue("rndis_wlan");
@@ -2590,12 +2615,12 @@ fail:
2590} 2615}
2591 2616
2592 2617
2593static void rndis_wext_unbind(struct usbnet *dev, struct usb_interface *intf) 2618static void rndis_wext_unbind(struct usbnet *usbdev, struct usb_interface *intf)
2594{ 2619{
2595 struct rndis_wext_private *priv = get_rndis_wext_priv(dev); 2620 struct rndis_wext_private *priv = get_rndis_wext_priv(usbdev);
2596 2621
2597 /* turn radio off */ 2622 /* turn radio off */
2598 disassociate(dev, 0); 2623 disassociate(usbdev, 0);
2599 2624
2600 cancel_delayed_work_sync(&priv->stats_work); 2625 cancel_delayed_work_sync(&priv->stats_work);
2601 cancel_work_sync(&priv->work); 2626 cancel_work_sync(&priv->work);
@@ -2606,13 +2631,13 @@ static void rndis_wext_unbind(struct usbnet *dev, struct usb_interface *intf)
2606 kfree(priv->wpa_ie); 2631 kfree(priv->wpa_ie);
2607 kfree(priv); 2632 kfree(priv);
2608 2633
2609 rndis_unbind(dev, intf); 2634 rndis_unbind(usbdev, intf);
2610} 2635}
2611 2636
2612 2637
2613static int rndis_wext_reset(struct usbnet *dev) 2638static int rndis_wext_reset(struct usbnet *usbdev)
2614{ 2639{
2615 return deauthenticate(dev); 2640 return deauthenticate(usbdev);
2616} 2641}
2617 2642
2618 2643
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index 2d611876bbe0..d485a86bba75 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -5,12 +5,16 @@ config RT2X00
5 This will enable the experimental support for the Ralink drivers, 5 This will enable the experimental support for the Ralink drivers,
6 developed in the rt2x00 project <http://rt2x00.serialmonkey.com>. 6 developed in the rt2x00 project <http://rt2x00.serialmonkey.com>.
7 7
8 These drivers will make use of the mac80211 stack. 8 These drivers make use of the mac80211 stack.
9 9
10 When building one of the individual drivers, the rt2x00 library 10 When building one of the individual drivers, the rt2x00 library
11 will also be created. That library (when the driver is built as 11 will also be created. That library (when the driver is built as
12 a module) will be called "rt2x00lib.ko". 12 a module) will be called "rt2x00lib.ko".
13 13
14 Additionally PCI and USB libraries will also be build depending
15 on the types of drivers being selected, these libraries will be
16 called "rt2x00pci.ko" and "rt2x00usb.ko".
17
14if RT2X00 18if RT2X00
15 19
16config RT2X00_LIB 20config RT2X00_LIB
@@ -32,35 +36,34 @@ config RT2X00_LIB_FIRMWARE
32config RT2X00_LIB_RFKILL 36config RT2X00_LIB_RFKILL
33 boolean 37 boolean
34 depends on RT2X00_LIB 38 depends on RT2X00_LIB
35 depends on INPUT
36 select RFKILL 39 select RFKILL
37 select INPUT_POLLDEV
38 40
39config RT2X00_LIB_LEDS 41config RT2X00_LIB_LEDS
40 boolean 42 boolean
41 depends on RT2X00_LIB && NEW_LEDS 43 depends on RT2X00_LIB && NEW_LEDS
42 44
43config RT2400PCI 45config RT2400PCI
44 tristate "Ralink rt2400 pci/pcmcia support" 46 tristate "Ralink rt2400 (PCI/PCMCIA) support"
45 depends on PCI 47 depends on PCI
46 select RT2X00_LIB_PCI 48 select RT2X00_LIB_PCI
47 select EEPROM_93CX6 49 select EEPROM_93CX6
48 ---help--- 50 ---help---
49 This is an experimental driver for the Ralink rt2400 wireless chip. 51 This adds support for rt2400 wireless chipset family.
52 Supported chips: RT2460.
50 53
51 When compiled as a module, this driver will be called "rt2400pci.ko". 54 When compiled as a module, this driver will be called "rt2400pci.ko".
52 55
53config RT2400PCI_RFKILL 56config RT2400PCI_RFKILL
54 bool "RT2400 rfkill support" 57 bool "Ralink rt2400 rfkill support"
55 depends on RT2400PCI && INPUT 58 depends on RT2400PCI
56 select RT2X00_LIB_RFKILL 59 select RT2X00_LIB_RFKILL
57 ---help--- 60 ---help---
58 This adds support for integrated rt2400 devices that feature a 61 This adds support for integrated rt2400 hardware that features a
59 hardware button to control the radio state. 62 hardware button to control the radio state.
60 This feature depends on the RF switch subsystem rfkill. 63 This feature depends on the RF switch subsystem rfkill.
61 64
62config RT2400PCI_LEDS 65config RT2400PCI_LEDS
63 bool "RT2400 leds support" 66 bool "Ralink rt2400 leds support"
64 depends on RT2400PCI && NEW_LEDS 67 depends on RT2400PCI && NEW_LEDS
65 select LEDS_CLASS 68 select LEDS_CLASS
66 select RT2X00_LIB_LEDS 69 select RT2X00_LIB_LEDS
@@ -68,26 +71,27 @@ config RT2400PCI_LEDS
68 This adds support for led triggers provided my mac80211. 71 This adds support for led triggers provided my mac80211.
69 72
70config RT2500PCI 73config RT2500PCI
71 tristate "Ralink rt2500 pci/pcmcia support" 74 tristate "Ralink rt2500 (PCI/PCMCIA) support"
72 depends on PCI 75 depends on PCI
73 select RT2X00_LIB_PCI 76 select RT2X00_LIB_PCI
74 select EEPROM_93CX6 77 select EEPROM_93CX6
75 ---help--- 78 ---help---
76 This is an experimental driver for the Ralink rt2500 wireless chip. 79 This adds support for rt2500 wireless chipset family.
80 Supported chips: RT2560.
77 81
78 When compiled as a module, this driver will be called "rt2500pci.ko". 82 When compiled as a module, this driver will be called "rt2500pci.ko".
79 83
80config RT2500PCI_RFKILL 84config RT2500PCI_RFKILL
81 bool "RT2500 rfkill support" 85 bool "Ralink rt2500 rfkill support"
82 depends on RT2500PCI && INPUT 86 depends on RT2500PCI
83 select RT2X00_LIB_RFKILL 87 select RT2X00_LIB_RFKILL
84 ---help--- 88 ---help---
85 This adds support for integrated rt2500 devices that feature a 89 This adds support for integrated rt2500 hardware that features a
86 hardware button to control the radio state. 90 hardware button to control the radio state.
87 This feature depends on the RF switch subsystem rfkill. 91 This feature depends on the RF switch subsystem rfkill.
88 92
89config RT2500PCI_LEDS 93config RT2500PCI_LEDS
90 bool "RT2500 leds support" 94 bool "Ralink rt2500 leds support"
91 depends on RT2500PCI && NEW_LEDS 95 depends on RT2500PCI && NEW_LEDS
92 select LEDS_CLASS 96 select LEDS_CLASS
93 select RT2X00_LIB_LEDS 97 select RT2X00_LIB_LEDS
@@ -95,28 +99,29 @@ config RT2500PCI_LEDS
95 This adds support for led triggers provided my mac80211. 99 This adds support for led triggers provided my mac80211.
96 100
97config RT61PCI 101config RT61PCI
98 tristate "Ralink rt61 pci/pcmcia support" 102 tristate "Ralink rt2501/rt61 (PCI/PCMCIA) support"
99 depends on PCI 103 depends on PCI
100 select RT2X00_LIB_PCI 104 select RT2X00_LIB_PCI
101 select RT2X00_LIB_FIRMWARE 105 select RT2X00_LIB_FIRMWARE
102 select CRC_ITU_T 106 select CRC_ITU_T
103 select EEPROM_93CX6 107 select EEPROM_93CX6
104 ---help--- 108 ---help---
105 This is an experimental driver for the Ralink rt61 wireless chip. 109 This adds support for rt2501 wireless chipset family.
110 Supported chips: RT2561, RT2561S & RT2661.
106 111
107 When compiled as a module, this driver will be called "rt61pci.ko". 112 When compiled as a module, this driver will be called "rt61pci.ko".
108 113
109config RT61PCI_RFKILL 114config RT61PCI_RFKILL
110 bool "RT61 rfkill support" 115 bool "Ralink rt2501/rt61 rfkill support"
111 depends on RT61PCI && INPUT 116 depends on RT61PCI
112 select RT2X00_LIB_RFKILL 117 select RT2X00_LIB_RFKILL
113 ---help--- 118 ---help---
114 This adds support for integrated rt61 devices that feature a 119 This adds support for integrated rt61 hardware that features a
115 hardware button to control the radio state. 120 hardware button to control the radio state.
116 This feature depends on the RF switch subsystem rfkill. 121 This feature depends on the RF switch subsystem rfkill.
117 122
118config RT61PCI_LEDS 123config RT61PCI_LEDS
119 bool "RT61 leds support" 124 bool "Ralink rt2501/rt61 leds support"
120 depends on RT61PCI && NEW_LEDS 125 depends on RT61PCI && NEW_LEDS
121 select LEDS_CLASS 126 select LEDS_CLASS
122 select RT2X00_LIB_LEDS 127 select RT2X00_LIB_LEDS
@@ -124,16 +129,17 @@ config RT61PCI_LEDS
124 This adds support for led triggers provided my mac80211. 129 This adds support for led triggers provided my mac80211.
125 130
126config RT2500USB 131config RT2500USB
127 tristate "Ralink rt2500 usb support" 132 tristate "Ralink rt2500 (USB) support"
128 depends on USB 133 depends on USB
129 select RT2X00_LIB_USB 134 select RT2X00_LIB_USB
130 ---help--- 135 ---help---
131 This is an experimental driver for the Ralink rt2500 wireless chip. 136 This adds support for rt2500 wireless chipset family.
137 Supported chips: RT2571 & RT2572.
132 138
133 When compiled as a module, this driver will be called "rt2500usb.ko". 139 When compiled as a module, this driver will be called "rt2500usb.ko".
134 140
135config RT2500USB_LEDS 141config RT2500USB_LEDS
136 bool "RT2500 leds support" 142 bool "Ralink rt2500 leds support"
137 depends on RT2500USB && NEW_LEDS 143 depends on RT2500USB && NEW_LEDS
138 select LEDS_CLASS 144 select LEDS_CLASS
139 select RT2X00_LIB_LEDS 145 select RT2X00_LIB_LEDS
@@ -141,18 +147,19 @@ config RT2500USB_LEDS
141 This adds support for led triggers provided my mac80211. 147 This adds support for led triggers provided my mac80211.
142 148
143config RT73USB 149config RT73USB
144 tristate "Ralink rt73 usb support" 150 tristate "Ralink rt2501/rt73 (USB) support"
145 depends on USB 151 depends on USB
146 select RT2X00_LIB_USB 152 select RT2X00_LIB_USB
147 select RT2X00_LIB_FIRMWARE 153 select RT2X00_LIB_FIRMWARE
148 select CRC_ITU_T 154 select CRC_ITU_T
149 ---help--- 155 ---help---
150 This is an experimental driver for the Ralink rt73 wireless chip. 156 This adds support for rt2501 wireless chipset family.
157 Supported chips: RT2571W, RT2573 & RT2671.
151 158
152 When compiled as a module, this driver will be called "rt73usb.ko". 159 When compiled as a module, this driver will be called "rt73usb.ko".
153 160
154config RT73USB_LEDS 161config RT73USB_LEDS
155 bool "RT73 leds support" 162 bool "Ralink rt2501/rt73 leds support"
156 depends on RT73USB && NEW_LEDS 163 depends on RT73USB && NEW_LEDS
157 select LEDS_CLASS 164 select LEDS_CLASS
158 select RT2X00_LIB_LEDS 165 select RT2X00_LIB_LEDS
@@ -165,7 +172,7 @@ config RT2X00_LIB_DEBUGFS
165 ---help--- 172 ---help---
166 Enable creation of debugfs files for the rt2x00 drivers. 173 Enable creation of debugfs files for the rt2x00 drivers.
167 These debugfs files support both reading and writing of the 174 These debugfs files support both reading and writing of the
168 most important register types of the rt2x00 devices. 175 most important register types of the rt2x00 hardware.
169 176
170config RT2X00_DEBUG 177config RT2X00_DEBUG
171 bool "Ralink debug output" 178 bool "Ralink debug output"
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index b36ed1c6c746..4c0538d6099b 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -277,6 +277,17 @@ static int rt2400pci_blink_set(struct led_classdev *led_cdev,
277 277
278 return 0; 278 return 0;
279} 279}
280
281static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
282 struct rt2x00_led *led,
283 enum led_type type)
284{
285 led->rt2x00dev = rt2x00dev;
286 led->type = type;
287 led->led_dev.brightness_set = rt2400pci_brightness_set;
288 led->led_dev.blink_set = rt2400pci_blink_set;
289 led->flags = LED_INITIALIZED;
290}
280#endif /* CONFIG_RT2400PCI_LEDS */ 291#endif /* CONFIG_RT2400PCI_LEDS */
281 292
282/* 293/*
@@ -620,48 +631,38 @@ static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
620static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev, 631static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
621 struct queue_entry *entry) 632 struct queue_entry *entry)
622{ 633{
623 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 634 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
635 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
624 u32 word; 636 u32 word;
625 637
626 rt2x00_desc_read(priv_rx->desc, 2, &word); 638 rt2x00_desc_read(entry_priv->desc, 2, &word);
627 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, 639 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
628 entry->queue->data_size); 640 rt2x00_desc_write(entry_priv->desc, 2, word);
629 rt2x00_desc_write(priv_rx->desc, 2, word);
630 641
631 rt2x00_desc_read(priv_rx->desc, 1, &word); 642 rt2x00_desc_read(entry_priv->desc, 1, &word);
632 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma); 643 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
633 rt2x00_desc_write(priv_rx->desc, 1, word); 644 rt2x00_desc_write(entry_priv->desc, 1, word);
634 645
635 rt2x00_desc_read(priv_rx->desc, 0, &word); 646 rt2x00_desc_read(entry_priv->desc, 0, &word);
636 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 647 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
637 rt2x00_desc_write(priv_rx->desc, 0, word); 648 rt2x00_desc_write(entry_priv->desc, 0, word);
638} 649}
639 650
640static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev, 651static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
641 struct queue_entry *entry) 652 struct queue_entry *entry)
642{ 653{
643 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data; 654 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
644 u32 word; 655 u32 word;
645 656
646 rt2x00_desc_read(priv_tx->desc, 1, &word); 657 rt2x00_desc_read(entry_priv->desc, 0, &word);
647 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
648 rt2x00_desc_write(priv_tx->desc, 1, word);
649
650 rt2x00_desc_read(priv_tx->desc, 2, &word);
651 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
652 entry->queue->data_size);
653 rt2x00_desc_write(priv_tx->desc, 2, word);
654
655 rt2x00_desc_read(priv_tx->desc, 0, &word);
656 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 658 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
657 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 659 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
658 rt2x00_desc_write(priv_tx->desc, 0, word); 660 rt2x00_desc_write(entry_priv->desc, 0, word);
659} 661}
660 662
661static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) 663static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
662{ 664{
663 struct queue_entry_priv_pci_rx *priv_rx; 665 struct queue_entry_priv_pci *entry_priv;
664 struct queue_entry_priv_pci_tx *priv_tx;
665 u32 reg; 666 u32 reg;
666 667
667 /* 668 /*
@@ -674,28 +675,28 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
674 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 675 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
675 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 676 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
676 677
677 priv_tx = rt2x00dev->tx[1].entries[0].priv_data; 678 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
678 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg); 679 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
679 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, 680 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
680 priv_tx->desc_dma); 681 entry_priv->desc_dma);
681 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); 682 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
682 683
683 priv_tx = rt2x00dev->tx[0].entries[0].priv_data; 684 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
684 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg); 685 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
685 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, 686 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
686 priv_tx->desc_dma); 687 entry_priv->desc_dma);
687 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 688 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
688 689
689 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data; 690 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
690 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 691 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
691 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 692 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
692 priv_tx->desc_dma); 693 entry_priv->desc_dma);
693 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 694 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
694 695
695 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data; 696 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
696 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 697 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
697 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 698 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
698 priv_tx->desc_dma); 699 entry_priv->desc_dma);
699 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); 700 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
700 701
701 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg); 702 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
@@ -703,9 +704,10 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
703 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); 704 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
704 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); 705 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
705 706
706 priv_rx = rt2x00dev->rx->entries[0].priv_data; 707 entry_priv = rt2x00dev->rx->entries[0].priv_data;
707 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg); 708 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
708 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma); 709 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
710 entry_priv->desc_dma);
709 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); 711 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
710 712
711 return 0; 713 return 0;
@@ -801,25 +803,32 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
801 return 0; 803 return 0;
802} 804}
803 805
804static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev) 806static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
805{ 807{
806 unsigned int i; 808 unsigned int i;
807 u16 eeprom;
808 u8 reg_id;
809 u8 value; 809 u8 value;
810 810
811 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 811 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
812 rt2400pci_bbp_read(rt2x00dev, 0, &value); 812 rt2400pci_bbp_read(rt2x00dev, 0, &value);
813 if ((value != 0xff) && (value != 0x00)) 813 if ((value != 0xff) && (value != 0x00))
814 goto continue_csr_init; 814 return 0;
815 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
816 udelay(REGISTER_BUSY_DELAY); 815 udelay(REGISTER_BUSY_DELAY);
817 } 816 }
818 817
819 ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); 818 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
820 return -EACCES; 819 return -EACCES;
820}
821
822static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
823{
824 unsigned int i;
825 u16 eeprom;
826 u8 reg_id;
827 u8 value;
828
829 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
830 return -EACCES;
821 831
822continue_csr_init:
823 rt2400pci_bbp_write(rt2x00dev, 1, 0x00); 832 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
824 rt2400pci_bbp_write(rt2x00dev, 3, 0x27); 833 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
825 rt2400pci_bbp_write(rt2x00dev, 4, 0x08); 834 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
@@ -858,7 +867,8 @@ static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
858 867
859 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg); 868 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
860 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 869 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
861 state == STATE_RADIO_RX_OFF); 870 (state == STATE_RADIO_RX_OFF) ||
871 (state == STATE_RADIO_RX_OFF_LINK));
862 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); 872 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
863} 873}
864 874
@@ -895,17 +905,10 @@ static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
895 /* 905 /*
896 * Initialize all registers. 906 * Initialize all registers.
897 */ 907 */
898 if (rt2400pci_init_queues(rt2x00dev) || 908 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
899 rt2400pci_init_registers(rt2x00dev) || 909 rt2400pci_init_registers(rt2x00dev) ||
900 rt2400pci_init_bbp(rt2x00dev)) { 910 rt2400pci_init_bbp(rt2x00dev)))
901 ERROR(rt2x00dev, "Register initialization failed.\n");
902 return -EIO; 911 return -EIO;
903 }
904
905 /*
906 * Enable interrupts.
907 */
908 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
909 912
910 return 0; 913 return 0;
911} 914}
@@ -927,11 +930,6 @@ static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
927 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 930 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
928 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1); 931 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
929 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); 932 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
930
931 /*
932 * Disable interrupts.
933 */
934 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
935} 933}
936 934
937static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, 935static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
@@ -966,10 +964,6 @@ static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
966 msleep(10); 964 msleep(10);
967 } 965 }
968 966
969 NOTICE(rt2x00dev, "Device failed to enter state %d, "
970 "current device state: bbp %d and rf %d.\n",
971 state, bbp_state, rf_state);
972
973 return -EBUSY; 967 return -EBUSY;
974} 968}
975 969
@@ -987,11 +981,13 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
987 break; 981 break;
988 case STATE_RADIO_RX_ON: 982 case STATE_RADIO_RX_ON:
989 case STATE_RADIO_RX_ON_LINK: 983 case STATE_RADIO_RX_ON_LINK:
990 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
991 break;
992 case STATE_RADIO_RX_OFF: 984 case STATE_RADIO_RX_OFF:
993 case STATE_RADIO_RX_OFF_LINK: 985 case STATE_RADIO_RX_OFF_LINK:
994 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); 986 rt2400pci_toggle_rx(rt2x00dev, state);
987 break;
988 case STATE_RADIO_IRQ_ON:
989 case STATE_RADIO_IRQ_OFF:
990 rt2400pci_toggle_irq(rt2x00dev, state);
995 break; 991 break;
996 case STATE_DEEP_SLEEP: 992 case STATE_DEEP_SLEEP:
997 case STATE_SLEEP: 993 case STATE_SLEEP:
@@ -1004,6 +1000,10 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1004 break; 1000 break;
1005 } 1001 }
1006 1002
1003 if (unlikely(retval))
1004 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1005 state, retval);
1006
1007 return retval; 1007 return retval;
1008} 1008}
1009 1009
@@ -1012,18 +1012,23 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1012 */ 1012 */
1013static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1013static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1014 struct sk_buff *skb, 1014 struct sk_buff *skb,
1015 struct txentry_desc *txdesc, 1015 struct txentry_desc *txdesc)
1016 struct ieee80211_tx_control *control)
1017{ 1016{
1018 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1017 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1018 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1019 __le32 *txd = skbdesc->desc; 1019 __le32 *txd = skbdesc->desc;
1020 u32 word; 1020 u32 word;
1021 1021
1022 /* 1022 /*
1023 * Start writing the descriptor words. 1023 * Start writing the descriptor words.
1024 */ 1024 */
1025 rt2x00_desc_read(entry_priv->desc, 1, &word);
1026 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1027 rt2x00_desc_write(entry_priv->desc, 1, word);
1028
1025 rt2x00_desc_read(txd, 2, &word); 1029 rt2x00_desc_read(txd, 2, &word);
1026 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len); 1030 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1031 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1027 rt2x00_desc_write(txd, 2, word); 1032 rt2x00_desc_write(txd, 2, word);
1028 1033
1029 rt2x00_desc_read(txd, 3, &word); 1034 rt2x00_desc_read(txd, 3, &word);
@@ -1057,20 +1062,53 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1057 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); 1062 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1058 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1063 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1059 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1064 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1060 !!(control->flags & 1065 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1061 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1062 rt2x00_desc_write(txd, 0, word); 1066 rt2x00_desc_write(txd, 0, word);
1063} 1067}
1064 1068
1065/* 1069/*
1066 * TX data initialization 1070 * TX data initialization
1067 */ 1071 */
1072static void rt2400pci_write_beacon(struct queue_entry *entry)
1073{
1074 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1075 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1076 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1077 u32 word;
1078 u32 reg;
1079
1080 /*
1081 * Disable beaconing while we are reloading the beacon data,
1082 * otherwise we might be sending out invalid data.
1083 */
1084 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1085 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1086 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1087 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1088 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1089
1090 /*
1091 * Replace rt2x00lib allocated descriptor with the
1092 * pointer to the _real_ hardware descriptor.
1093 * After that, map the beacon to DMA and update the
1094 * descriptor.
1095 */
1096 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1097 skbdesc->desc = entry_priv->desc;
1098
1099 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1100
1101 rt2x00_desc_read(entry_priv->desc, 1, &word);
1102 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1103 rt2x00_desc_write(entry_priv->desc, 1, word);
1104}
1105
1068static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1106static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1069 const unsigned int queue) 1107 const enum data_queue_qid queue)
1070{ 1108{
1071 u32 reg; 1109 u32 reg;
1072 1110
1073 if (queue == RT2X00_BCN_QUEUE_BEACON) { 1111 if (queue == QID_BEACON) {
1074 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 1112 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1075 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) { 1113 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1076 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1); 1114 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
@@ -1082,12 +1120,9 @@ static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1082 } 1120 }
1083 1121
1084 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 1122 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1085 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1123 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1086 (queue == IEEE80211_TX_QUEUE_DATA0)); 1124 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1087 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1125 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1088 (queue == IEEE80211_TX_QUEUE_DATA1));
1089 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1090 (queue == RT2X00_BCN_QUEUE_ATIM));
1091 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); 1126 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1092} 1127}
1093 1128
@@ -1097,32 +1132,54 @@ static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1097static void rt2400pci_fill_rxdone(struct queue_entry *entry, 1132static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1098 struct rxdone_entry_desc *rxdesc) 1133 struct rxdone_entry_desc *rxdesc)
1099{ 1134{
1100 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 1135 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1136 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1101 u32 word0; 1137 u32 word0;
1102 u32 word2; 1138 u32 word2;
1103 u32 word3; 1139 u32 word3;
1140 u32 word4;
1141 u64 tsf;
1142 u32 rx_low;
1143 u32 rx_high;
1104 1144
1105 rt2x00_desc_read(priv_rx->desc, 0, &word0); 1145 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1106 rt2x00_desc_read(priv_rx->desc, 2, &word2); 1146 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1107 rt2x00_desc_read(priv_rx->desc, 3, &word3); 1147 rt2x00_desc_read(entry_priv->desc, 3, &word3);
1148 rt2x00_desc_read(entry_priv->desc, 4, &word4);
1108 1149
1109 rxdesc->flags = 0;
1110 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1150 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1111 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1151 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1112 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) 1152 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1113 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; 1153 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1114 1154
1115 /* 1155 /*
1156 * We only get the lower 32bits from the timestamp,
1157 * to get the full 64bits we must complement it with
1158 * the timestamp from get_tsf().
1159 * Note that when a wraparound of the lower 32bits
1160 * has occurred between the frame arrival and the get_tsf()
1161 * call, we must decrease the higher 32bits with 1 to get
1162 * to correct value.
1163 */
1164 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1165 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1166 rx_high = upper_32_bits(tsf);
1167
1168 if ((u32)tsf <= rx_low)
1169 rx_high--;
1170
1171 /*
1116 * Obtain the status about this packet. 1172 * Obtain the status about this packet.
1117 * The signal is the PLCP value, and needs to be stripped 1173 * The signal is the PLCP value, and needs to be stripped
1118 * of the preamble bit (0x08). 1174 * of the preamble bit (0x08).
1119 */ 1175 */
1176 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1120 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08; 1177 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1121 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) - 1178 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1122 entry->queue->rt2x00dev->rssi_offset; 1179 entry->queue->rt2x00dev->rssi_offset;
1123 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1180 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1124 1181
1125 rxdesc->dev_flags = RXDONE_SIGNAL_PLCP; 1182 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1126 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 1183 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1127 rxdesc->dev_flags |= RXDONE_MY_BSS; 1184 rxdesc->dev_flags |= RXDONE_MY_BSS;
1128} 1185}
@@ -1131,18 +1188,18 @@ static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1131 * Interrupt functions. 1188 * Interrupt functions.
1132 */ 1189 */
1133static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, 1190static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1134 const enum ieee80211_tx_queue queue_idx) 1191 const enum data_queue_qid queue_idx)
1135{ 1192{
1136 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 1193 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1137 struct queue_entry_priv_pci_tx *priv_tx; 1194 struct queue_entry_priv_pci *entry_priv;
1138 struct queue_entry *entry; 1195 struct queue_entry *entry;
1139 struct txdone_entry_desc txdesc; 1196 struct txdone_entry_desc txdesc;
1140 u32 word; 1197 u32 word;
1141 1198
1142 while (!rt2x00queue_empty(queue)) { 1199 while (!rt2x00queue_empty(queue)) {
1143 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1200 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1144 priv_tx = entry->priv_data; 1201 entry_priv = entry->priv_data;
1145 rt2x00_desc_read(priv_tx->desc, 0, &word); 1202 rt2x00_desc_read(entry_priv->desc, 0, &word);
1146 1203
1147 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1204 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1148 !rt2x00_get_field32(word, TXD_W0_VALID)) 1205 !rt2x00_get_field32(word, TXD_W0_VALID))
@@ -1151,10 +1208,21 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1151 /* 1208 /*
1152 * Obtain the status about this packet. 1209 * Obtain the status about this packet.
1153 */ 1210 */
1154 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT); 1211 txdesc.flags = 0;
1212 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1213 case 0: /* Success */
1214 case 1: /* Success with retry */
1215 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1216 break;
1217 case 2: /* Failure, excessive retries */
1218 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1219 /* Don't break, this is a failed frame! */
1220 default: /* Failure */
1221 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1222 }
1155 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); 1223 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1156 1224
1157 rt2x00pci_txdone(rt2x00dev, entry, &txdesc); 1225 rt2x00lib_txdone(entry, &txdesc);
1158 } 1226 }
1159} 1227}
1160 1228
@@ -1198,19 +1266,19 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1198 * 3 - Atim ring transmit done interrupt. 1266 * 3 - Atim ring transmit done interrupt.
1199 */ 1267 */
1200 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) 1268 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1201 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM); 1269 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1202 1270
1203 /* 1271 /*
1204 * 4 - Priority ring transmit done interrupt. 1272 * 4 - Priority ring transmit done interrupt.
1205 */ 1273 */
1206 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) 1274 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1207 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0); 1275 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1208 1276
1209 /* 1277 /*
1210 * 5 - Tx ring transmit done interrupt. 1278 * 5 - Tx ring transmit done interrupt.
1211 */ 1279 */
1212 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) 1280 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1213 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1); 1281 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1214 1282
1215 return IRQ_HANDLED; 1283 return IRQ_HANDLED;
1216} 1284}
@@ -1309,23 +1377,10 @@ static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1309#ifdef CONFIG_RT2400PCI_LEDS 1377#ifdef CONFIG_RT2400PCI_LEDS
1310 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); 1378 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1311 1379
1312 rt2x00dev->led_radio.rt2x00dev = rt2x00dev; 1380 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1313 rt2x00dev->led_radio.type = LED_TYPE_RADIO; 1381 if (value == LED_MODE_TXRX_ACTIVITY)
1314 rt2x00dev->led_radio.led_dev.brightness_set = 1382 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1315 rt2400pci_brightness_set; 1383 LED_TYPE_ACTIVITY);
1316 rt2x00dev->led_radio.led_dev.blink_set =
1317 rt2400pci_blink_set;
1318 rt2x00dev->led_radio.flags = LED_INITIALIZED;
1319
1320 if (value == LED_MODE_TXRX_ACTIVITY) {
1321 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1322 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1323 rt2x00dev->led_qual.led_dev.brightness_set =
1324 rt2400pci_brightness_set;
1325 rt2x00dev->led_qual.led_dev.blink_set =
1326 rt2400pci_blink_set;
1327 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1328 }
1329#endif /* CONFIG_RT2400PCI_LEDS */ 1384#endif /* CONFIG_RT2400PCI_LEDS */
1330 1385
1331 /* 1386 /*
@@ -1375,13 +1430,11 @@ static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1375 /* 1430 /*
1376 * Initialize all hw fields. 1431 * Initialize all hw fields.
1377 */ 1432 */
1378 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; 1433 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1434 IEEE80211_HW_SIGNAL_DBM;
1379 rt2x00dev->hw->extra_tx_headroom = 0; 1435 rt2x00dev->hw->extra_tx_headroom = 0;
1380 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1381 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1382 rt2x00dev->hw->queues = 2;
1383 1436
1384 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev); 1437 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1385 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 1438 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1386 rt2x00_eeprom_addr(rt2x00dev, 1439 rt2x00_eeprom_addr(rt2x00dev,
1387 EEPROM_MAC_ADDR_0)); 1440 EEPROM_MAC_ADDR_0));
@@ -1427,9 +1480,10 @@ static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1427 rt2400pci_probe_hw_mode(rt2x00dev); 1480 rt2400pci_probe_hw_mode(rt2x00dev);
1428 1481
1429 /* 1482 /*
1430 * This device requires the atim queue 1483 * This device requires the atim queue and DMA-mapped skbs.
1431 */ 1484 */
1432 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 1485 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1486 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1433 1487
1434 /* 1488 /*
1435 * Set the rssi offset. 1489 * Set the rssi offset.
@@ -1456,8 +1510,7 @@ static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1456 return 0; 1510 return 0;
1457} 1511}
1458 1512
1459static int rt2400pci_conf_tx(struct ieee80211_hw *hw, 1513static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1460 int queue,
1461 const struct ieee80211_tx_queue_params *params) 1514 const struct ieee80211_tx_queue_params *params)
1462{ 1515{
1463 struct rt2x00_dev *rt2x00dev = hw->priv; 1516 struct rt2x00_dev *rt2x00dev = hw->priv;
@@ -1467,7 +1520,7 @@ static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1467 * per queue. So by default we only configure the TX queue, 1520 * per queue. So by default we only configure the TX queue,
1468 * and ignore all other configurations. 1521 * and ignore all other configurations.
1469 */ 1522 */
1470 if (queue != IEEE80211_TX_QUEUE_DATA0) 1523 if (queue != 0)
1471 return -EINVAL; 1524 return -EINVAL;
1472 1525
1473 if (rt2x00mac_conf_tx(hw, queue, params)) 1526 if (rt2x00mac_conf_tx(hw, queue, params))
@@ -1496,60 +1549,6 @@ static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1496 return tsf; 1549 return tsf;
1497} 1550}
1498 1551
1499static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1500 struct ieee80211_tx_control *control)
1501{
1502 struct rt2x00_dev *rt2x00dev = hw->priv;
1503 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1504 struct queue_entry_priv_pci_tx *priv_tx;
1505 struct skb_frame_desc *skbdesc;
1506 u32 reg;
1507
1508 if (unlikely(!intf->beacon))
1509 return -ENOBUFS;
1510 priv_tx = intf->beacon->priv_data;
1511
1512 /*
1513 * Fill in skb descriptor
1514 */
1515 skbdesc = get_skb_frame_desc(skb);
1516 memset(skbdesc, 0, sizeof(*skbdesc));
1517 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1518 skbdesc->data = skb->data;
1519 skbdesc->data_len = skb->len;
1520 skbdesc->desc = priv_tx->desc;
1521 skbdesc->desc_len = intf->beacon->queue->desc_size;
1522 skbdesc->entry = intf->beacon;
1523
1524 /*
1525 * Disable beaconing while we are reloading the beacon data,
1526 * otherwise we might be sending out invalid data.
1527 */
1528 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1529 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1530 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1531 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1532 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1533
1534 /*
1535 * mac80211 doesn't provide the control->queue variable
1536 * for beacons. Set our own queue identification so
1537 * it can be used during descriptor initialization.
1538 */
1539 control->queue = RT2X00_BCN_QUEUE_BEACON;
1540 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1541
1542 /*
1543 * Enable beacon generation.
1544 * Write entire beacon with descriptor to register,
1545 * and kick the beacon generator.
1546 */
1547 memcpy(priv_tx->data, skb->data, skb->len);
1548 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1549
1550 return 0;
1551}
1552
1553static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw) 1552static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1554{ 1553{
1555 struct rt2x00_dev *rt2x00dev = hw->priv; 1554 struct rt2x00_dev *rt2x00dev = hw->priv;
@@ -1574,7 +1573,6 @@ static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1574 .conf_tx = rt2400pci_conf_tx, 1573 .conf_tx = rt2400pci_conf_tx,
1575 .get_tx_stats = rt2x00mac_get_tx_stats, 1574 .get_tx_stats = rt2x00mac_get_tx_stats,
1576 .get_tsf = rt2400pci_get_tsf, 1575 .get_tsf = rt2400pci_get_tsf,
1577 .beacon_update = rt2400pci_beacon_update,
1578 .tx_last_beacon = rt2400pci_tx_last_beacon, 1576 .tx_last_beacon = rt2400pci_tx_last_beacon,
1579}; 1577};
1580 1578
@@ -1592,6 +1590,7 @@ static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1592 .link_tuner = rt2400pci_link_tuner, 1590 .link_tuner = rt2400pci_link_tuner,
1593 .write_tx_desc = rt2400pci_write_tx_desc, 1591 .write_tx_desc = rt2400pci_write_tx_desc,
1594 .write_tx_data = rt2x00pci_write_tx_data, 1592 .write_tx_data = rt2x00pci_write_tx_data,
1593 .write_beacon = rt2400pci_write_beacon,
1595 .kick_tx_queue = rt2400pci_kick_tx_queue, 1594 .kick_tx_queue = rt2400pci_kick_tx_queue,
1596 .fill_rxdone = rt2400pci_fill_rxdone, 1595 .fill_rxdone = rt2400pci_fill_rxdone,
1597 .config_filter = rt2400pci_config_filter, 1596 .config_filter = rt2400pci_config_filter,
@@ -1604,28 +1603,28 @@ static const struct data_queue_desc rt2400pci_queue_rx = {
1604 .entry_num = RX_ENTRIES, 1603 .entry_num = RX_ENTRIES,
1605 .data_size = DATA_FRAME_SIZE, 1604 .data_size = DATA_FRAME_SIZE,
1606 .desc_size = RXD_DESC_SIZE, 1605 .desc_size = RXD_DESC_SIZE,
1607 .priv_size = sizeof(struct queue_entry_priv_pci_rx), 1606 .priv_size = sizeof(struct queue_entry_priv_pci),
1608}; 1607};
1609 1608
1610static const struct data_queue_desc rt2400pci_queue_tx = { 1609static const struct data_queue_desc rt2400pci_queue_tx = {
1611 .entry_num = TX_ENTRIES, 1610 .entry_num = TX_ENTRIES,
1612 .data_size = DATA_FRAME_SIZE, 1611 .data_size = DATA_FRAME_SIZE,
1613 .desc_size = TXD_DESC_SIZE, 1612 .desc_size = TXD_DESC_SIZE,
1614 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1613 .priv_size = sizeof(struct queue_entry_priv_pci),
1615}; 1614};
1616 1615
1617static const struct data_queue_desc rt2400pci_queue_bcn = { 1616static const struct data_queue_desc rt2400pci_queue_bcn = {
1618 .entry_num = BEACON_ENTRIES, 1617 .entry_num = BEACON_ENTRIES,
1619 .data_size = MGMT_FRAME_SIZE, 1618 .data_size = MGMT_FRAME_SIZE,
1620 .desc_size = TXD_DESC_SIZE, 1619 .desc_size = TXD_DESC_SIZE,
1621 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1620 .priv_size = sizeof(struct queue_entry_priv_pci),
1622}; 1621};
1623 1622
1624static const struct data_queue_desc rt2400pci_queue_atim = { 1623static const struct data_queue_desc rt2400pci_queue_atim = {
1625 .entry_num = ATIM_ENTRIES, 1624 .entry_num = ATIM_ENTRIES,
1626 .data_size = DATA_FRAME_SIZE, 1625 .data_size = DATA_FRAME_SIZE,
1627 .desc_size = TXD_DESC_SIZE, 1626 .desc_size = TXD_DESC_SIZE,
1628 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1627 .priv_size = sizeof(struct queue_entry_priv_pci),
1629}; 1628};
1630 1629
1631static const struct rt2x00_ops rt2400pci_ops = { 1630static const struct rt2x00_ops rt2400pci_ops = {
@@ -1634,6 +1633,7 @@ static const struct rt2x00_ops rt2400pci_ops = {
1634 .max_ap_intf = 1, 1633 .max_ap_intf = 1,
1635 .eeprom_size = EEPROM_SIZE, 1634 .eeprom_size = EEPROM_SIZE,
1636 .rf_size = RF_SIZE, 1635 .rf_size = RF_SIZE,
1636 .tx_queues = NUM_TX_QUEUES,
1637 .rx = &rt2400pci_queue_rx, 1637 .rx = &rt2400pci_queue_rx,
1638 .tx = &rt2400pci_queue_tx, 1638 .tx = &rt2400pci_queue_tx,
1639 .bcn = &rt2400pci_queue_bcn, 1639 .bcn = &rt2400pci_queue_bcn,
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.h b/drivers/net/wireless/rt2x00/rt2400pci.h
index a5210f9a3360..bc5564258228 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.h
+++ b/drivers/net/wireless/rt2x00/rt2400pci.h
@@ -37,8 +37,6 @@
37 * Signal information. 37 * Signal information.
38 * Defaul offset is required for RSSI <-> dBm conversion. 38 * Defaul offset is required for RSSI <-> dBm conversion.
39 */ 39 */
40#define MAX_SIGNAL 100
41#define MAX_RX_SSI -1
42#define DEFAULT_RSSI_OFFSET 100 40#define DEFAULT_RSSI_OFFSET 100
43 41
44/* 42/*
@@ -52,6 +50,11 @@
52#define RF_SIZE 0x0010 50#define RF_SIZE 0x0010
53 51
54/* 52/*
53 * Number of TX queues.
54 */
55#define NUM_TX_QUEUES 2
56
57/*
55 * Control/Status Registers(CSR). 58 * Control/Status Registers(CSR).
56 * Some values are set in TU, whereas 1 TU == 1024 us. 59 * Some values are set in TU, whereas 1 TU == 1024 us.
57 */ 60 */
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index f7731fb82555..aa6dfb811c71 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -277,6 +277,17 @@ static int rt2500pci_blink_set(struct led_classdev *led_cdev,
277 277
278 return 0; 278 return 0;
279} 279}
280
281static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
282 struct rt2x00_led *led,
283 enum led_type type)
284{
285 led->rt2x00dev = rt2x00dev;
286 led->type = type;
287 led->led_dev.brightness_set = rt2500pci_brightness_set;
288 led->led_dev.blink_set = rt2500pci_blink_set;
289 led->flags = LED_INITIALIZED;
290}
280#endif /* CONFIG_RT2500PCI_LEDS */ 291#endif /* CONFIG_RT2500PCI_LEDS */
281 292
282/* 293/*
@@ -317,8 +328,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
317 struct rt2x00intf_conf *conf, 328 struct rt2x00intf_conf *conf,
318 const unsigned int flags) 329 const unsigned int flags)
319{ 330{
320 struct data_queue *queue = 331 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
321 rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
322 unsigned int bcn_preload; 332 unsigned int bcn_preload;
323 u32 reg; 333 u32 reg;
324 334
@@ -716,38 +726,34 @@ dynamic_cca_tune:
716static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev, 726static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
717 struct queue_entry *entry) 727 struct queue_entry *entry)
718{ 728{
719 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 729 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
730 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
720 u32 word; 731 u32 word;
721 732
722 rt2x00_desc_read(priv_rx->desc, 1, &word); 733 rt2x00_desc_read(entry_priv->desc, 1, &word);
723 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma); 734 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
724 rt2x00_desc_write(priv_rx->desc, 1, word); 735 rt2x00_desc_write(entry_priv->desc, 1, word);
725 736
726 rt2x00_desc_read(priv_rx->desc, 0, &word); 737 rt2x00_desc_read(entry_priv->desc, 0, &word);
727 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 738 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
728 rt2x00_desc_write(priv_rx->desc, 0, word); 739 rt2x00_desc_write(entry_priv->desc, 0, word);
729} 740}
730 741
731static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev, 742static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
732 struct queue_entry *entry) 743 struct queue_entry *entry)
733{ 744{
734 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data; 745 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
735 u32 word; 746 u32 word;
736 747
737 rt2x00_desc_read(priv_tx->desc, 1, &word); 748 rt2x00_desc_read(entry_priv->desc, 0, &word);
738 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
739 rt2x00_desc_write(priv_tx->desc, 1, word);
740
741 rt2x00_desc_read(priv_tx->desc, 0, &word);
742 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 749 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
743 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 750 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
744 rt2x00_desc_write(priv_tx->desc, 0, word); 751 rt2x00_desc_write(entry_priv->desc, 0, word);
745} 752}
746 753
747static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) 754static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
748{ 755{
749 struct queue_entry_priv_pci_rx *priv_rx; 756 struct queue_entry_priv_pci *entry_priv;
750 struct queue_entry_priv_pci_tx *priv_tx;
751 u32 reg; 757 u32 reg;
752 758
753 /* 759 /*
@@ -760,28 +766,28 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
760 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 766 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
761 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 767 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
762 768
763 priv_tx = rt2x00dev->tx[1].entries[0].priv_data; 769 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
764 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg); 770 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
765 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, 771 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
766 priv_tx->desc_dma); 772 entry_priv->desc_dma);
767 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); 773 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
768 774
769 priv_tx = rt2x00dev->tx[0].entries[0].priv_data; 775 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
770 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg); 776 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
771 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, 777 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
772 priv_tx->desc_dma); 778 entry_priv->desc_dma);
773 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 779 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
774 780
775 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data; 781 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
776 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 782 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
777 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 783 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
778 priv_tx->desc_dma); 784 entry_priv->desc_dma);
779 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 785 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
780 786
781 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data; 787 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
782 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 788 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
783 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 789 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
784 priv_tx->desc_dma); 790 entry_priv->desc_dma);
785 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); 791 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
786 792
787 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg); 793 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
@@ -789,9 +795,10 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
789 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); 795 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
790 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); 796 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
791 797
792 priv_rx = rt2x00dev->rx->entries[0].priv_data; 798 entry_priv = rt2x00dev->rx->entries[0].priv_data;
793 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg); 799 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
794 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma); 800 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
801 entry_priv->desc_dma);
795 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); 802 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
796 803
797 return 0; 804 return 0;
@@ -940,25 +947,32 @@ static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
940 return 0; 947 return 0;
941} 948}
942 949
943static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev) 950static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
944{ 951{
945 unsigned int i; 952 unsigned int i;
946 u16 eeprom;
947 u8 reg_id;
948 u8 value; 953 u8 value;
949 954
950 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 955 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
951 rt2500pci_bbp_read(rt2x00dev, 0, &value); 956 rt2500pci_bbp_read(rt2x00dev, 0, &value);
952 if ((value != 0xff) && (value != 0x00)) 957 if ((value != 0xff) && (value != 0x00))
953 goto continue_csr_init; 958 return 0;
954 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
955 udelay(REGISTER_BUSY_DELAY); 959 udelay(REGISTER_BUSY_DELAY);
956 } 960 }
957 961
958 ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); 962 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
959 return -EACCES; 963 return -EACCES;
964}
965
966static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
967{
968 unsigned int i;
969 u16 eeprom;
970 u8 reg_id;
971 u8 value;
972
973 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
974 return -EACCES;
960 975
961continue_csr_init:
962 rt2500pci_bbp_write(rt2x00dev, 3, 0x02); 976 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
963 rt2500pci_bbp_write(rt2x00dev, 4, 0x19); 977 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
964 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c); 978 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
@@ -1013,7 +1027,8 @@ static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1013 1027
1014 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg); 1028 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1015 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1029 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1016 state == STATE_RADIO_RX_OFF); 1030 (state == STATE_RADIO_RX_OFF) ||
1031 (state == STATE_RADIO_RX_OFF_LINK));
1017 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); 1032 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1018} 1033}
1019 1034
@@ -1050,17 +1065,10 @@ static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1050 /* 1065 /*
1051 * Initialize all registers. 1066 * Initialize all registers.
1052 */ 1067 */
1053 if (rt2500pci_init_queues(rt2x00dev) || 1068 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1054 rt2500pci_init_registers(rt2x00dev) || 1069 rt2500pci_init_registers(rt2x00dev) ||
1055 rt2500pci_init_bbp(rt2x00dev)) { 1070 rt2500pci_init_bbp(rt2x00dev)))
1056 ERROR(rt2x00dev, "Register initialization failed.\n");
1057 return -EIO; 1071 return -EIO;
1058 }
1059
1060 /*
1061 * Enable interrupts.
1062 */
1063 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1064 1072
1065 return 0; 1073 return 0;
1066} 1074}
@@ -1082,11 +1090,6 @@ static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1082 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 1090 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1083 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1); 1091 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1084 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); 1092 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1085
1086 /*
1087 * Disable interrupts.
1088 */
1089 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1090} 1093}
1091 1094
1092static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev, 1095static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
@@ -1121,10 +1124,6 @@ static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1121 msleep(10); 1124 msleep(10);
1122 } 1125 }
1123 1126
1124 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1125 "current device state: bbp %d and rf %d.\n",
1126 state, bbp_state, rf_state);
1127
1128 return -EBUSY; 1127 return -EBUSY;
1129} 1128}
1130 1129
@@ -1142,11 +1141,13 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1142 break; 1141 break;
1143 case STATE_RADIO_RX_ON: 1142 case STATE_RADIO_RX_ON:
1144 case STATE_RADIO_RX_ON_LINK: 1143 case STATE_RADIO_RX_ON_LINK:
1145 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1146 break;
1147 case STATE_RADIO_RX_OFF: 1144 case STATE_RADIO_RX_OFF:
1148 case STATE_RADIO_RX_OFF_LINK: 1145 case STATE_RADIO_RX_OFF_LINK:
1149 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); 1146 rt2500pci_toggle_rx(rt2x00dev, state);
1147 break;
1148 case STATE_RADIO_IRQ_ON:
1149 case STATE_RADIO_IRQ_OFF:
1150 rt2500pci_toggle_irq(rt2x00dev, state);
1150 break; 1151 break;
1151 case STATE_DEEP_SLEEP: 1152 case STATE_DEEP_SLEEP:
1152 case STATE_SLEEP: 1153 case STATE_SLEEP:
@@ -1159,6 +1160,10 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1159 break; 1160 break;
1160 } 1161 }
1161 1162
1163 if (unlikely(retval))
1164 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1165 state, retval);
1166
1162 return retval; 1167 return retval;
1163} 1168}
1164 1169
@@ -1167,16 +1172,20 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1167 */ 1172 */
1168static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1173static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1169 struct sk_buff *skb, 1174 struct sk_buff *skb,
1170 struct txentry_desc *txdesc, 1175 struct txentry_desc *txdesc)
1171 struct ieee80211_tx_control *control)
1172{ 1176{
1173 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1177 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1178 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1174 __le32 *txd = skbdesc->desc; 1179 __le32 *txd = skbdesc->desc;
1175 u32 word; 1180 u32 word;
1176 1181
1177 /* 1182 /*
1178 * Start writing the descriptor words. 1183 * Start writing the descriptor words.
1179 */ 1184 */
1185 rt2x00_desc_read(entry_priv->desc, 1, &word);
1186 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1187 rt2x00_desc_write(entry_priv->desc, 1, word);
1188
1180 rt2x00_desc_read(txd, 2, &word); 1189 rt2x00_desc_read(txd, 2, &word);
1181 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); 1190 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1182 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs); 1191 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
@@ -1210,9 +1219,7 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1210 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); 1219 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1211 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1220 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1212 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1221 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1213 !!(control->flags & 1222 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1214 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1215 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1216 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); 1223 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1217 rt2x00_desc_write(txd, 0, word); 1224 rt2x00_desc_write(txd, 0, word);
1218} 1225}
@@ -1220,12 +1227,46 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1220/* 1227/*
1221 * TX data initialization 1228 * TX data initialization
1222 */ 1229 */
1230static void rt2500pci_write_beacon(struct queue_entry *entry)
1231{
1232 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1233 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1234 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1235 u32 word;
1236 u32 reg;
1237
1238 /*
1239 * Disable beaconing while we are reloading the beacon data,
1240 * otherwise we might be sending out invalid data.
1241 */
1242 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1243 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1244 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1245 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1246 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1247
1248 /*
1249 * Replace rt2x00lib allocated descriptor with the
1250 * pointer to the _real_ hardware descriptor.
1251 * After that, map the beacon to DMA and update the
1252 * descriptor.
1253 */
1254 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1255 skbdesc->desc = entry_priv->desc;
1256
1257 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1258
1259 rt2x00_desc_read(entry_priv->desc, 1, &word);
1260 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1261 rt2x00_desc_write(entry_priv->desc, 1, word);
1262}
1263
1223static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1264static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1224 const unsigned int queue) 1265 const enum data_queue_qid queue)
1225{ 1266{
1226 u32 reg; 1267 u32 reg;
1227 1268
1228 if (queue == RT2X00_BCN_QUEUE_BEACON) { 1269 if (queue == QID_BEACON) {
1229 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 1270 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1230 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) { 1271 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1231 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1); 1272 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
@@ -1237,12 +1278,9 @@ static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1237 } 1278 }
1238 1279
1239 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 1280 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1240 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1281 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1241 (queue == IEEE80211_TX_QUEUE_DATA0)); 1282 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1242 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1283 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1243 (queue == IEEE80211_TX_QUEUE_DATA1));
1244 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1245 (queue == RT2X00_BCN_QUEUE_ATIM));
1246 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); 1284 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1247} 1285}
1248 1286
@@ -1252,14 +1290,13 @@ static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1252static void rt2500pci_fill_rxdone(struct queue_entry *entry, 1290static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1253 struct rxdone_entry_desc *rxdesc) 1291 struct rxdone_entry_desc *rxdesc)
1254{ 1292{
1255 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 1293 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1256 u32 word0; 1294 u32 word0;
1257 u32 word2; 1295 u32 word2;
1258 1296
1259 rt2x00_desc_read(priv_rx->desc, 0, &word0); 1297 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1260 rt2x00_desc_read(priv_rx->desc, 2, &word2); 1298 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1261 1299
1262 rxdesc->flags = 0;
1263 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1300 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1264 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1301 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1265 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) 1302 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
@@ -1276,7 +1313,6 @@ static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1276 entry->queue->rt2x00dev->rssi_offset; 1313 entry->queue->rt2x00dev->rssi_offset;
1277 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1314 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1278 1315
1279 rxdesc->dev_flags = 0;
1280 if (rt2x00_get_field32(word0, RXD_W0_OFDM)) 1316 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1281 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; 1317 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1282 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 1318 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
@@ -1287,18 +1323,18 @@ static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1287 * Interrupt functions. 1323 * Interrupt functions.
1288 */ 1324 */
1289static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, 1325static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1290 const enum ieee80211_tx_queue queue_idx) 1326 const enum data_queue_qid queue_idx)
1291{ 1327{
1292 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 1328 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1293 struct queue_entry_priv_pci_tx *priv_tx; 1329 struct queue_entry_priv_pci *entry_priv;
1294 struct queue_entry *entry; 1330 struct queue_entry *entry;
1295 struct txdone_entry_desc txdesc; 1331 struct txdone_entry_desc txdesc;
1296 u32 word; 1332 u32 word;
1297 1333
1298 while (!rt2x00queue_empty(queue)) { 1334 while (!rt2x00queue_empty(queue)) {
1299 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1335 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1300 priv_tx = entry->priv_data; 1336 entry_priv = entry->priv_data;
1301 rt2x00_desc_read(priv_tx->desc, 0, &word); 1337 rt2x00_desc_read(entry_priv->desc, 0, &word);
1302 1338
1303 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1339 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1304 !rt2x00_get_field32(word, TXD_W0_VALID)) 1340 !rt2x00_get_field32(word, TXD_W0_VALID))
@@ -1307,10 +1343,21 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1307 /* 1343 /*
1308 * Obtain the status about this packet. 1344 * Obtain the status about this packet.
1309 */ 1345 */
1310 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT); 1346 txdesc.flags = 0;
1347 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1348 case 0: /* Success */
1349 case 1: /* Success with retry */
1350 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1351 break;
1352 case 2: /* Failure, excessive retries */
1353 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1354 /* Don't break, this is a failed frame! */
1355 default: /* Failure */
1356 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1357 }
1311 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); 1358 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1312 1359
1313 rt2x00pci_txdone(rt2x00dev, entry, &txdesc); 1360 rt2x00lib_txdone(entry, &txdesc);
1314 } 1361 }
1315} 1362}
1316 1363
@@ -1354,19 +1401,19 @@ static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1354 * 3 - Atim ring transmit done interrupt. 1401 * 3 - Atim ring transmit done interrupt.
1355 */ 1402 */
1356 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) 1403 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1357 rt2500pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM); 1404 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1358 1405
1359 /* 1406 /*
1360 * 4 - Priority ring transmit done interrupt. 1407 * 4 - Priority ring transmit done interrupt.
1361 */ 1408 */
1362 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) 1409 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1363 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0); 1410 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1364 1411
1365 /* 1412 /*
1366 * 5 - Tx ring transmit done interrupt. 1413 * 5 - Tx ring transmit done interrupt.
1367 */ 1414 */
1368 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) 1415 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1369 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1); 1416 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1370 1417
1371 return IRQ_HANDLED; 1418 return IRQ_HANDLED;
1372} 1419}
@@ -1486,23 +1533,10 @@ static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1486#ifdef CONFIG_RT2500PCI_LEDS 1533#ifdef CONFIG_RT2500PCI_LEDS
1487 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); 1534 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1488 1535
1489 rt2x00dev->led_radio.rt2x00dev = rt2x00dev; 1536 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1490 rt2x00dev->led_radio.type = LED_TYPE_RADIO; 1537 if (value == LED_MODE_TXRX_ACTIVITY)
1491 rt2x00dev->led_radio.led_dev.brightness_set = 1538 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1492 rt2500pci_brightness_set; 1539 LED_TYPE_ACTIVITY);
1493 rt2x00dev->led_radio.led_dev.blink_set =
1494 rt2500pci_blink_set;
1495 rt2x00dev->led_radio.flags = LED_INITIALIZED;
1496
1497 if (value == LED_MODE_TXRX_ACTIVITY) {
1498 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1499 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1500 rt2x00dev->led_qual.led_dev.brightness_set =
1501 rt2500pci_brightness_set;
1502 rt2x00dev->led_qual.led_dev.blink_set =
1503 rt2500pci_blink_set;
1504 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1505 }
1506#endif /* CONFIG_RT2500PCI_LEDS */ 1540#endif /* CONFIG_RT2500PCI_LEDS */
1507 1541
1508 /* 1542 /*
@@ -1695,13 +1729,12 @@ static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1695 /* 1729 /*
1696 * Initialize all hw fields. 1730 * Initialize all hw fields.
1697 */ 1731 */
1698 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; 1732 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1733 IEEE80211_HW_SIGNAL_DBM;
1734
1699 rt2x00dev->hw->extra_tx_headroom = 0; 1735 rt2x00dev->hw->extra_tx_headroom = 0;
1700 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1701 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1702 rt2x00dev->hw->queues = 2;
1703 1736
1704 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev); 1737 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1705 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 1738 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1706 rt2x00_eeprom_addr(rt2x00dev, 1739 rt2x00_eeprom_addr(rt2x00dev,
1707 EEPROM_MAC_ADDR_0)); 1740 EEPROM_MAC_ADDR_0));
@@ -1765,9 +1798,10 @@ static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1765 rt2500pci_probe_hw_mode(rt2x00dev); 1798 rt2500pci_probe_hw_mode(rt2x00dev);
1766 1799
1767 /* 1800 /*
1768 * This device requires the atim queue 1801 * This device requires the atim queue and DMA-mapped skbs.
1769 */ 1802 */
1770 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 1803 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1804 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1771 1805
1772 /* 1806 /*
1773 * Set the rssi offset. 1807 * Set the rssi offset.
@@ -1808,61 +1842,6 @@ static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1808 return tsf; 1842 return tsf;
1809} 1843}
1810 1844
1811static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1812 struct ieee80211_tx_control *control)
1813{
1814 struct rt2x00_dev *rt2x00dev = hw->priv;
1815 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1816 struct queue_entry_priv_pci_tx *priv_tx;
1817 struct skb_frame_desc *skbdesc;
1818 u32 reg;
1819
1820 if (unlikely(!intf->beacon))
1821 return -ENOBUFS;
1822
1823 priv_tx = intf->beacon->priv_data;
1824
1825 /*
1826 * Fill in skb descriptor
1827 */
1828 skbdesc = get_skb_frame_desc(skb);
1829 memset(skbdesc, 0, sizeof(*skbdesc));
1830 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1831 skbdesc->data = skb->data;
1832 skbdesc->data_len = skb->len;
1833 skbdesc->desc = priv_tx->desc;
1834 skbdesc->desc_len = intf->beacon->queue->desc_size;
1835 skbdesc->entry = intf->beacon;
1836
1837 /*
1838 * Disable beaconing while we are reloading the beacon data,
1839 * otherwise we might be sending out invalid data.
1840 */
1841 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1842 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1843 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1844 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1845 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1846
1847 /*
1848 * mac80211 doesn't provide the control->queue variable
1849 * for beacons. Set our own queue identification so
1850 * it can be used during descriptor initialization.
1851 */
1852 control->queue = RT2X00_BCN_QUEUE_BEACON;
1853 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1854
1855 /*
1856 * Enable beacon generation.
1857 * Write entire beacon with descriptor to register,
1858 * and kick the beacon generator.
1859 */
1860 memcpy(priv_tx->data, skb->data, skb->len);
1861 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1862
1863 return 0;
1864}
1865
1866static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw) 1845static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1867{ 1846{
1868 struct rt2x00_dev *rt2x00dev = hw->priv; 1847 struct rt2x00_dev *rt2x00dev = hw->priv;
@@ -1887,7 +1866,6 @@ static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1887 .conf_tx = rt2x00mac_conf_tx, 1866 .conf_tx = rt2x00mac_conf_tx,
1888 .get_tx_stats = rt2x00mac_get_tx_stats, 1867 .get_tx_stats = rt2x00mac_get_tx_stats,
1889 .get_tsf = rt2500pci_get_tsf, 1868 .get_tsf = rt2500pci_get_tsf,
1890 .beacon_update = rt2500pci_beacon_update,
1891 .tx_last_beacon = rt2500pci_tx_last_beacon, 1869 .tx_last_beacon = rt2500pci_tx_last_beacon,
1892}; 1870};
1893 1871
@@ -1905,6 +1883,7 @@ static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1905 .link_tuner = rt2500pci_link_tuner, 1883 .link_tuner = rt2500pci_link_tuner,
1906 .write_tx_desc = rt2500pci_write_tx_desc, 1884 .write_tx_desc = rt2500pci_write_tx_desc,
1907 .write_tx_data = rt2x00pci_write_tx_data, 1885 .write_tx_data = rt2x00pci_write_tx_data,
1886 .write_beacon = rt2500pci_write_beacon,
1908 .kick_tx_queue = rt2500pci_kick_tx_queue, 1887 .kick_tx_queue = rt2500pci_kick_tx_queue,
1909 .fill_rxdone = rt2500pci_fill_rxdone, 1888 .fill_rxdone = rt2500pci_fill_rxdone,
1910 .config_filter = rt2500pci_config_filter, 1889 .config_filter = rt2500pci_config_filter,
@@ -1917,28 +1896,28 @@ static const struct data_queue_desc rt2500pci_queue_rx = {
1917 .entry_num = RX_ENTRIES, 1896 .entry_num = RX_ENTRIES,
1918 .data_size = DATA_FRAME_SIZE, 1897 .data_size = DATA_FRAME_SIZE,
1919 .desc_size = RXD_DESC_SIZE, 1898 .desc_size = RXD_DESC_SIZE,
1920 .priv_size = sizeof(struct queue_entry_priv_pci_rx), 1899 .priv_size = sizeof(struct queue_entry_priv_pci),
1921}; 1900};
1922 1901
1923static const struct data_queue_desc rt2500pci_queue_tx = { 1902static const struct data_queue_desc rt2500pci_queue_tx = {
1924 .entry_num = TX_ENTRIES, 1903 .entry_num = TX_ENTRIES,
1925 .data_size = DATA_FRAME_SIZE, 1904 .data_size = DATA_FRAME_SIZE,
1926 .desc_size = TXD_DESC_SIZE, 1905 .desc_size = TXD_DESC_SIZE,
1927 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1906 .priv_size = sizeof(struct queue_entry_priv_pci),
1928}; 1907};
1929 1908
1930static const struct data_queue_desc rt2500pci_queue_bcn = { 1909static const struct data_queue_desc rt2500pci_queue_bcn = {
1931 .entry_num = BEACON_ENTRIES, 1910 .entry_num = BEACON_ENTRIES,
1932 .data_size = MGMT_FRAME_SIZE, 1911 .data_size = MGMT_FRAME_SIZE,
1933 .desc_size = TXD_DESC_SIZE, 1912 .desc_size = TXD_DESC_SIZE,
1934 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1913 .priv_size = sizeof(struct queue_entry_priv_pci),
1935}; 1914};
1936 1915
1937static const struct data_queue_desc rt2500pci_queue_atim = { 1916static const struct data_queue_desc rt2500pci_queue_atim = {
1938 .entry_num = ATIM_ENTRIES, 1917 .entry_num = ATIM_ENTRIES,
1939 .data_size = DATA_FRAME_SIZE, 1918 .data_size = DATA_FRAME_SIZE,
1940 .desc_size = TXD_DESC_SIZE, 1919 .desc_size = TXD_DESC_SIZE,
1941 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1920 .priv_size = sizeof(struct queue_entry_priv_pci),
1942}; 1921};
1943 1922
1944static const struct rt2x00_ops rt2500pci_ops = { 1923static const struct rt2x00_ops rt2500pci_ops = {
@@ -1947,6 +1926,7 @@ static const struct rt2x00_ops rt2500pci_ops = {
1947 .max_ap_intf = 1, 1926 .max_ap_intf = 1,
1948 .eeprom_size = EEPROM_SIZE, 1927 .eeprom_size = EEPROM_SIZE,
1949 .rf_size = RF_SIZE, 1928 .rf_size = RF_SIZE,
1929 .tx_queues = NUM_TX_QUEUES,
1950 .rx = &rt2500pci_queue_rx, 1930 .rx = &rt2500pci_queue_rx,
1951 .tx = &rt2500pci_queue_tx, 1931 .tx = &rt2500pci_queue_tx,
1952 .bcn = &rt2500pci_queue_bcn, 1932 .bcn = &rt2500pci_queue_bcn,
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.h b/drivers/net/wireless/rt2x00/rt2500pci.h
index 13899550465a..42f376929ea9 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.h
+++ b/drivers/net/wireless/rt2x00/rt2500pci.h
@@ -48,8 +48,6 @@
48 * Signal information. 48 * Signal information.
49 * Defaul offset is required for RSSI <-> dBm conversion. 49 * Defaul offset is required for RSSI <-> dBm conversion.
50 */ 50 */
51#define MAX_SIGNAL 100
52#define MAX_RX_SSI -1
53#define DEFAULT_RSSI_OFFSET 121 51#define DEFAULT_RSSI_OFFSET 121
54 52
55/* 53/*
@@ -63,6 +61,11 @@
63#define RF_SIZE 0x0014 61#define RF_SIZE 0x0014
64 62
65/* 63/*
64 * Number of TX queues.
65 */
66#define NUM_TX_QUEUES 2
67
68/*
66 * Control/Status Registers(CSR). 69 * Control/Status Registers(CSR).
67 * Some values are set in TU, whereas 1 TU == 1024 us. 70 * Some values are set in TU, whereas 1 TU == 1024 us.
68 */ 71 */
@@ -748,7 +751,7 @@
748#define LEDCSR_LED_DEFAULT FIELD32(0x00100000) 751#define LEDCSR_LED_DEFAULT FIELD32(0x00100000)
749 752
750/* 753/*
751 * AES control register. 754 * SECCSR3: AES control register.
752 */ 755 */
753#define SECCSR3 0x00fc 756#define SECCSR3 0x00fc
754 757
@@ -892,7 +895,7 @@
892#define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000) 895#define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000)
893 896
894/* 897/*
895 * SECCSR1_RT2509: WEP control register. 898 * SECCSR1: WEP control register.
896 * KICK_ENCRYPT: Kick encryption engine, self-clear. 899 * KICK_ENCRYPT: Kick encryption engine, self-clear.
897 * ONE_SHOT: 0: ring mode, 1: One shot only mode. 900 * ONE_SHOT: 0: ring mode, 1: One shot only mode.
898 * DESC_ADDRESS: Descriptor physical address of frame. 901 * DESC_ADDRESS: Descriptor physical address of frame.
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c
index d90512f97b39..3558cb210747 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.c
+++ b/drivers/net/wireless/rt2x00/rt2500usb.c
@@ -76,10 +76,10 @@ static inline void rt2500usb_register_multiread(struct rt2x00_dev *rt2x00dev,
76 const unsigned int offset, 76 const unsigned int offset,
77 void *value, const u16 length) 77 void *value, const u16 length)
78{ 78{
79 int timeout = REGISTER_TIMEOUT * (length / sizeof(u16));
80 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ, 79 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
81 USB_VENDOR_REQUEST_IN, offset, 80 USB_VENDOR_REQUEST_IN, offset,
82 value, length, timeout); 81 value, length,
82 REGISTER_TIMEOUT16(length));
83} 83}
84 84
85static inline void rt2500usb_register_write(struct rt2x00_dev *rt2x00dev, 85static inline void rt2500usb_register_write(struct rt2x00_dev *rt2x00dev,
@@ -106,10 +106,10 @@ static inline void rt2500usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
106 const unsigned int offset, 106 const unsigned int offset,
107 void *value, const u16 length) 107 void *value, const u16 length)
108{ 108{
109 int timeout = REGISTER_TIMEOUT * (length / sizeof(u16));
110 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE, 109 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
111 USB_VENDOR_REQUEST_OUT, offset, 110 USB_VENDOR_REQUEST_OUT, offset,
112 value, length, timeout); 111 value, length,
112 REGISTER_TIMEOUT16(length));
113} 113}
114 114
115static u16 rt2500usb_bbp_check(struct rt2x00_dev *rt2x00dev) 115static u16 rt2500usb_bbp_check(struct rt2x00_dev *rt2x00dev)
@@ -322,6 +322,17 @@ static int rt2500usb_blink_set(struct led_classdev *led_cdev,
322 322
323 return 0; 323 return 0;
324} 324}
325
326static void rt2500usb_init_led(struct rt2x00_dev *rt2x00dev,
327 struct rt2x00_led *led,
328 enum led_type type)
329{
330 led->rt2x00dev = rt2x00dev;
331 led->type = type;
332 led->led_dev.brightness_set = rt2500usb_brightness_set;
333 led->led_dev.blink_set = rt2500usb_blink_set;
334 led->flags = LED_INITIALIZED;
335}
325#endif /* CONFIG_RT2500USB_LEDS */ 336#endif /* CONFIG_RT2500USB_LEDS */
326 337
327/* 338/*
@@ -860,25 +871,32 @@ static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
860 return 0; 871 return 0;
861} 872}
862 873
863static int rt2500usb_init_bbp(struct rt2x00_dev *rt2x00dev) 874static int rt2500usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
864{ 875{
865 unsigned int i; 876 unsigned int i;
866 u16 eeprom;
867 u8 value; 877 u8 value;
868 u8 reg_id;
869 878
870 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 879 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
871 rt2500usb_bbp_read(rt2x00dev, 0, &value); 880 rt2500usb_bbp_read(rt2x00dev, 0, &value);
872 if ((value != 0xff) && (value != 0x00)) 881 if ((value != 0xff) && (value != 0x00))
873 goto continue_csr_init; 882 return 0;
874 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
875 udelay(REGISTER_BUSY_DELAY); 883 udelay(REGISTER_BUSY_DELAY);
876 } 884 }
877 885
878 ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); 886 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
879 return -EACCES; 887 return -EACCES;
888}
889
890static int rt2500usb_init_bbp(struct rt2x00_dev *rt2x00dev)
891{
892 unsigned int i;
893 u16 eeprom;
894 u8 value;
895 u8 reg_id;
896
897 if (unlikely(rt2500usb_wait_bbp_ready(rt2x00dev)))
898 return -EACCES;
880 899
881continue_csr_init:
882 rt2500usb_bbp_write(rt2x00dev, 3, 0x02); 900 rt2500usb_bbp_write(rt2x00dev, 3, 0x02);
883 rt2500usb_bbp_write(rt2x00dev, 4, 0x19); 901 rt2500usb_bbp_write(rt2x00dev, 4, 0x19);
884 rt2500usb_bbp_write(rt2x00dev, 14, 0x1c); 902 rt2500usb_bbp_write(rt2x00dev, 14, 0x1c);
@@ -934,7 +952,8 @@ static void rt2500usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
934 952
935 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg); 953 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
936 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 954 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX,
937 state == STATE_RADIO_RX_OFF); 955 (state == STATE_RADIO_RX_OFF) ||
956 (state == STATE_RADIO_RX_OFF_LINK));
938 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg); 957 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
939} 958}
940 959
@@ -943,11 +962,9 @@ static int rt2500usb_enable_radio(struct rt2x00_dev *rt2x00dev)
943 /* 962 /*
944 * Initialize all registers. 963 * Initialize all registers.
945 */ 964 */
946 if (rt2500usb_init_registers(rt2x00dev) || 965 if (unlikely(rt2500usb_init_registers(rt2x00dev) ||
947 rt2500usb_init_bbp(rt2x00dev)) { 966 rt2500usb_init_bbp(rt2x00dev)))
948 ERROR(rt2x00dev, "Register initialization failed.\n");
949 return -EIO; 967 return -EIO;
950 }
951 968
952 return 0; 969 return 0;
953} 970}
@@ -1000,10 +1017,6 @@ static int rt2500usb_set_state(struct rt2x00_dev *rt2x00dev,
1000 msleep(30); 1017 msleep(30);
1001 } 1018 }
1002 1019
1003 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1004 "current device state: bbp %d and rf %d.\n",
1005 state, bbp_state, rf_state);
1006
1007 return -EBUSY; 1020 return -EBUSY;
1008} 1021}
1009 1022
@@ -1021,11 +1034,13 @@ static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1021 break; 1034 break;
1022 case STATE_RADIO_RX_ON: 1035 case STATE_RADIO_RX_ON:
1023 case STATE_RADIO_RX_ON_LINK: 1036 case STATE_RADIO_RX_ON_LINK:
1024 rt2500usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1025 break;
1026 case STATE_RADIO_RX_OFF: 1037 case STATE_RADIO_RX_OFF:
1027 case STATE_RADIO_RX_OFF_LINK: 1038 case STATE_RADIO_RX_OFF_LINK:
1028 rt2500usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); 1039 rt2500usb_toggle_rx(rt2x00dev, state);
1040 break;
1041 case STATE_RADIO_IRQ_ON:
1042 case STATE_RADIO_IRQ_OFF:
1043 /* No support, but no error either */
1029 break; 1044 break;
1030 case STATE_DEEP_SLEEP: 1045 case STATE_DEEP_SLEEP:
1031 case STATE_SLEEP: 1046 case STATE_SLEEP:
@@ -1038,6 +1053,10 @@ static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1038 break; 1053 break;
1039 } 1054 }
1040 1055
1056 if (unlikely(retval))
1057 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1058 state, retval);
1059
1041 return retval; 1060 return retval;
1042} 1061}
1043 1062
@@ -1046,8 +1065,7 @@ static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1046 */ 1065 */
1047static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1066static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1048 struct sk_buff *skb, 1067 struct sk_buff *skb,
1049 struct txentry_desc *txdesc, 1068 struct txentry_desc *txdesc)
1050 struct ieee80211_tx_control *control)
1051{ 1069{
1052 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1070 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1053 __le32 *txd = skbdesc->desc; 1071 __le32 *txd = skbdesc->desc;
@@ -1071,7 +1089,7 @@ static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1071 rt2x00_desc_write(txd, 2, word); 1089 rt2x00_desc_write(txd, 2, word);
1072 1090
1073 rt2x00_desc_read(txd, 0, &word); 1091 rt2x00_desc_read(txd, 0, &word);
1074 rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, control->retry_limit); 1092 rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit);
1075 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, 1093 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1076 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 1094 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1077 rt2x00_set_field32(&word, TXD_W0_ACK, 1095 rt2x00_set_field32(&word, TXD_W0_ACK,
@@ -1081,13 +1099,73 @@ static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1081 rt2x00_set_field32(&word, TXD_W0_OFDM, 1099 rt2x00_set_field32(&word, TXD_W0_OFDM,
1082 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags)); 1100 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1083 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ, 1101 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
1084 !!(control->flags & IEEE80211_TXCTL_FIRST_FRAGMENT)); 1102 test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
1085 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1103 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1086 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len); 1104 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT,
1105 skb->len - skbdesc->desc_len);
1087 rt2x00_set_field32(&word, TXD_W0_CIPHER, CIPHER_NONE); 1106 rt2x00_set_field32(&word, TXD_W0_CIPHER, CIPHER_NONE);
1088 rt2x00_desc_write(txd, 0, word); 1107 rt2x00_desc_write(txd, 0, word);
1089} 1108}
1090 1109
1110/*
1111 * TX data initialization
1112 */
1113static void rt2500usb_beacondone(struct urb *urb);
1114
1115static void rt2500usb_write_beacon(struct queue_entry *entry)
1116{
1117 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1118 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
1119 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
1120 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1121 int pipe = usb_sndbulkpipe(usb_dev, 1);
1122 int length;
1123 u16 reg;
1124
1125 /*
1126 * Add the descriptor in front of the skb.
1127 */
1128 skb_push(entry->skb, entry->queue->desc_size);
1129 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1130 skbdesc->desc = entry->skb->data;
1131
1132 /*
1133 * Disable beaconing while we are reloading the beacon data,
1134 * otherwise we might be sending out invalid data.
1135 */
1136 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
1137 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0);
1138 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0);
1139 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
1140 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1141
1142 /*
1143 * USB devices cannot blindly pass the skb->len as the
1144 * length of the data to usb_fill_bulk_urb. Pass the skb
1145 * to the driver to determine what the length should be.
1146 */
1147 length = rt2x00dev->ops->lib->get_tx_data_len(rt2x00dev, entry->skb);
1148
1149 usb_fill_bulk_urb(bcn_priv->urb, usb_dev, pipe,
1150 entry->skb->data, length, rt2500usb_beacondone,
1151 entry);
1152
1153 /*
1154 * Second we need to create the guardian byte.
1155 * We only need a single byte, so lets recycle
1156 * the 'flags' field we are not using for beacons.
1157 */
1158 bcn_priv->guardian_data = 0;
1159 usb_fill_bulk_urb(bcn_priv->guardian_urb, usb_dev, pipe,
1160 &bcn_priv->guardian_data, 1, rt2500usb_beacondone,
1161 entry);
1162
1163 /*
1164 * Send out the guardian byte.
1165 */
1166 usb_submit_urb(bcn_priv->guardian_urb, GFP_ATOMIC);
1167}
1168
1091static int rt2500usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev, 1169static int rt2500usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1092 struct sk_buff *skb) 1170 struct sk_buff *skb)
1093{ 1171{
@@ -1103,16 +1181,15 @@ static int rt2500usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1103 return length; 1181 return length;
1104} 1182}
1105 1183
1106/*
1107 * TX data initialization
1108 */
1109static void rt2500usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1184static void rt2500usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1110 const unsigned int queue) 1185 const enum data_queue_qid queue)
1111{ 1186{
1112 u16 reg; 1187 u16 reg;
1113 1188
1114 if (queue != RT2X00_BCN_QUEUE_BEACON) 1189 if (queue != QID_BEACON) {
1190 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1115 return; 1191 return;
1192 }
1116 1193
1117 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg); 1194 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
1118 if (!rt2x00_get_field16(reg, TXRX_CSR19_BEACON_GEN)) { 1195 if (!rt2x00_get_field16(reg, TXRX_CSR19_BEACON_GEN)) {
@@ -1138,30 +1215,28 @@ static void rt2500usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1138static void rt2500usb_fill_rxdone(struct queue_entry *entry, 1215static void rt2500usb_fill_rxdone(struct queue_entry *entry,
1139 struct rxdone_entry_desc *rxdesc) 1216 struct rxdone_entry_desc *rxdesc)
1140{ 1217{
1141 struct queue_entry_priv_usb_rx *priv_rx = entry->priv_data; 1218 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
1142 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1219 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1143 __le32 *rxd = 1220 __le32 *rxd =
1144 (__le32 *)(entry->skb->data + 1221 (__le32 *)(entry->skb->data +
1145 (priv_rx->urb->actual_length - entry->queue->desc_size)); 1222 (entry_priv->urb->actual_length -
1146 unsigned int offset = entry->queue->desc_size + 2; 1223 entry->queue->desc_size));
1147 u32 word0; 1224 u32 word0;
1148 u32 word1; 1225 u32 word1;
1149 1226
1150 /* 1227 /*
1151 * Copy descriptor to the available headroom inside the skbuffer. 1228 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1229 * frame data in rt2x00usb.
1152 */ 1230 */
1153 skb_push(entry->skb, offset); 1231 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1154 memcpy(entry->skb->data, rxd, entry->queue->desc_size); 1232 rxd = (__le32 *)skbdesc->desc;
1155 rxd = (__le32 *)entry->skb->data;
1156 1233
1157 /* 1234 /*
1158 * The descriptor is now aligned to 4 bytes and thus it is 1235 * It is now safe to read the descriptor on all architectures.
1159 * now safe to read it on all architectures.
1160 */ 1236 */
1161 rt2x00_desc_read(rxd, 0, &word0); 1237 rt2x00_desc_read(rxd, 0, &word0);
1162 rt2x00_desc_read(rxd, 1, &word1); 1238 rt2x00_desc_read(rxd, 1, &word1);
1163 1239
1164 rxdesc->flags = 0;
1165 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1240 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1166 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1241 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1167 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) 1242 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
@@ -1178,7 +1253,6 @@ static void rt2500usb_fill_rxdone(struct queue_entry *entry,
1178 entry->queue->rt2x00dev->rssi_offset; 1253 entry->queue->rt2x00dev->rssi_offset;
1179 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1254 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1180 1255
1181 rxdesc->dev_flags = 0;
1182 if (rt2x00_get_field32(word0, RXD_W0_OFDM)) 1256 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1183 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; 1257 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1184 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 1258 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
@@ -1187,16 +1261,7 @@ static void rt2500usb_fill_rxdone(struct queue_entry *entry,
1187 /* 1261 /*
1188 * Adjust the skb memory window to the frame boundaries. 1262 * Adjust the skb memory window to the frame boundaries.
1189 */ 1263 */
1190 skb_pull(entry->skb, offset);
1191 skb_trim(entry->skb, rxdesc->size); 1264 skb_trim(entry->skb, rxdesc->size);
1192
1193 /*
1194 * Set descriptor and data pointer.
1195 */
1196 skbdesc->data = entry->skb->data;
1197 skbdesc->data_len = rxdesc->size;
1198 skbdesc->desc = rxd;
1199 skbdesc->desc_len = entry->queue->desc_size;
1200} 1265}
1201 1266
1202/* 1267/*
@@ -1205,7 +1270,7 @@ static void rt2500usb_fill_rxdone(struct queue_entry *entry,
1205static void rt2500usb_beacondone(struct urb *urb) 1270static void rt2500usb_beacondone(struct urb *urb)
1206{ 1271{
1207 struct queue_entry *entry = (struct queue_entry *)urb->context; 1272 struct queue_entry *entry = (struct queue_entry *)urb->context;
1208 struct queue_entry_priv_usb_bcn *priv_bcn = entry->priv_data; 1273 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
1209 1274
1210 if (!test_bit(DEVICE_ENABLED_RADIO, &entry->queue->rt2x00dev->flags)) 1275 if (!test_bit(DEVICE_ENABLED_RADIO, &entry->queue->rt2x00dev->flags))
1211 return; 1276 return;
@@ -1216,9 +1281,9 @@ static void rt2500usb_beacondone(struct urb *urb)
1216 * Otherwise we should free the sk_buffer, the device 1281 * Otherwise we should free the sk_buffer, the device
1217 * should be doing the rest of the work now. 1282 * should be doing the rest of the work now.
1218 */ 1283 */
1219 if (priv_bcn->guardian_urb == urb) { 1284 if (bcn_priv->guardian_urb == urb) {
1220 usb_submit_urb(priv_bcn->urb, GFP_ATOMIC); 1285 usb_submit_urb(bcn_priv->urb, GFP_ATOMIC);
1221 } else if (priv_bcn->urb == urb) { 1286 } else if (bcn_priv->urb == urb) {
1222 dev_kfree_skb(entry->skb); 1287 dev_kfree_skb(entry->skb);
1223 entry->skb = NULL; 1288 entry->skb = NULL;
1224 } 1289 }
@@ -1397,23 +1462,10 @@ static int rt2500usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1397#ifdef CONFIG_RT2500USB_LEDS 1462#ifdef CONFIG_RT2500USB_LEDS
1398 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); 1463 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1399 1464
1400 rt2x00dev->led_radio.rt2x00dev = rt2x00dev; 1465 rt2500usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1401 rt2x00dev->led_radio.type = LED_TYPE_RADIO; 1466 if (value == LED_MODE_TXRX_ACTIVITY)
1402 rt2x00dev->led_radio.led_dev.brightness_set = 1467 rt2500usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1403 rt2500usb_brightness_set; 1468 LED_TYPE_ACTIVITY);
1404 rt2x00dev->led_radio.led_dev.blink_set =
1405 rt2500usb_blink_set;
1406 rt2x00dev->led_radio.flags = LED_INITIALIZED;
1407
1408 if (value == LED_MODE_TXRX_ACTIVITY) {
1409 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1410 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1411 rt2x00dev->led_qual.led_dev.brightness_set =
1412 rt2500usb_brightness_set;
1413 rt2x00dev->led_qual.led_dev.blink_set =
1414 rt2500usb_blink_set;
1415 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1416 }
1417#endif /* CONFIG_RT2500USB_LEDS */ 1469#endif /* CONFIG_RT2500USB_LEDS */
1418 1470
1419 /* 1471 /*
@@ -1600,13 +1652,12 @@ static void rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1600 rt2x00dev->hw->flags = 1652 rt2x00dev->hw->flags =
1601 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | 1653 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1602 IEEE80211_HW_RX_INCLUDES_FCS | 1654 IEEE80211_HW_RX_INCLUDES_FCS |
1603 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; 1655 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1656 IEEE80211_HW_SIGNAL_DBM;
1657
1604 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE; 1658 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1605 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1606 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1607 rt2x00dev->hw->queues = 2;
1608 1659
1609 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev); 1660 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1610 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 1661 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1611 rt2x00_eeprom_addr(rt2x00dev, 1662 rt2x00_eeprom_addr(rt2x00dev,
1612 EEPROM_MAC_ADDR_0)); 1663 EEPROM_MAC_ADDR_0));
@@ -1684,97 +1735,6 @@ static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1684 return 0; 1735 return 0;
1685} 1736}
1686 1737
1687/*
1688 * IEEE80211 stack callback functions.
1689 */
1690static int rt2500usb_beacon_update(struct ieee80211_hw *hw,
1691 struct sk_buff *skb,
1692 struct ieee80211_tx_control *control)
1693{
1694 struct rt2x00_dev *rt2x00dev = hw->priv;
1695 struct usb_device *usb_dev = rt2x00dev_usb_dev(rt2x00dev);
1696 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1697 struct queue_entry_priv_usb_bcn *priv_bcn;
1698 struct skb_frame_desc *skbdesc;
1699 int pipe = usb_sndbulkpipe(usb_dev, 1);
1700 int length;
1701 u16 reg;
1702
1703 if (unlikely(!intf->beacon))
1704 return -ENOBUFS;
1705
1706 priv_bcn = intf->beacon->priv_data;
1707
1708 /*
1709 * Add the descriptor in front of the skb.
1710 */
1711 skb_push(skb, intf->beacon->queue->desc_size);
1712 memset(skb->data, 0, intf->beacon->queue->desc_size);
1713
1714 /*
1715 * Fill in skb descriptor
1716 */
1717 skbdesc = get_skb_frame_desc(skb);
1718 memset(skbdesc, 0, sizeof(*skbdesc));
1719 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1720 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
1721 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
1722 skbdesc->desc = skb->data;
1723 skbdesc->desc_len = intf->beacon->queue->desc_size;
1724 skbdesc->entry = intf->beacon;
1725
1726 /*
1727 * Disable beaconing while we are reloading the beacon data,
1728 * otherwise we might be sending out invalid data.
1729 */
1730 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
1731 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0);
1732 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0);
1733 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
1734 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1735
1736 /*
1737 * mac80211 doesn't provide the control->queue variable
1738 * for beacons. Set our own queue identification so
1739 * it can be used during descriptor initialization.
1740 */
1741 control->queue = RT2X00_BCN_QUEUE_BEACON;
1742 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1743
1744 /*
1745 * USB devices cannot blindly pass the skb->len as the
1746 * length of the data to usb_fill_bulk_urb. Pass the skb
1747 * to the driver to determine what the length should be.
1748 */
1749 length = rt2500usb_get_tx_data_len(rt2x00dev, skb);
1750
1751 usb_fill_bulk_urb(priv_bcn->urb, usb_dev, pipe,
1752 skb->data, length, rt2500usb_beacondone,
1753 intf->beacon);
1754
1755 /*
1756 * Second we need to create the guardian byte.
1757 * We only need a single byte, so lets recycle
1758 * the 'flags' field we are not using for beacons.
1759 */
1760 priv_bcn->guardian_data = 0;
1761 usb_fill_bulk_urb(priv_bcn->guardian_urb, usb_dev, pipe,
1762 &priv_bcn->guardian_data, 1, rt2500usb_beacondone,
1763 intf->beacon);
1764
1765 /*
1766 * Send out the guardian byte.
1767 */
1768 usb_submit_urb(priv_bcn->guardian_urb, GFP_ATOMIC);
1769
1770 /*
1771 * Enable beacon generation.
1772 */
1773 rt2500usb_kick_tx_queue(rt2x00dev, control->queue);
1774
1775 return 0;
1776}
1777
1778static const struct ieee80211_ops rt2500usb_mac80211_ops = { 1738static const struct ieee80211_ops rt2500usb_mac80211_ops = {
1779 .tx = rt2x00mac_tx, 1739 .tx = rt2x00mac_tx,
1780 .start = rt2x00mac_start, 1740 .start = rt2x00mac_start,
@@ -1788,7 +1748,6 @@ static const struct ieee80211_ops rt2500usb_mac80211_ops = {
1788 .bss_info_changed = rt2x00mac_bss_info_changed, 1748 .bss_info_changed = rt2x00mac_bss_info_changed,
1789 .conf_tx = rt2x00mac_conf_tx, 1749 .conf_tx = rt2x00mac_conf_tx,
1790 .get_tx_stats = rt2x00mac_get_tx_stats, 1750 .get_tx_stats = rt2x00mac_get_tx_stats,
1791 .beacon_update = rt2500usb_beacon_update,
1792}; 1751};
1793 1752
1794static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = { 1753static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
@@ -1803,6 +1762,7 @@ static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
1803 .link_tuner = rt2500usb_link_tuner, 1762 .link_tuner = rt2500usb_link_tuner,
1804 .write_tx_desc = rt2500usb_write_tx_desc, 1763 .write_tx_desc = rt2500usb_write_tx_desc,
1805 .write_tx_data = rt2x00usb_write_tx_data, 1764 .write_tx_data = rt2x00usb_write_tx_data,
1765 .write_beacon = rt2500usb_write_beacon,
1806 .get_tx_data_len = rt2500usb_get_tx_data_len, 1766 .get_tx_data_len = rt2500usb_get_tx_data_len,
1807 .kick_tx_queue = rt2500usb_kick_tx_queue, 1767 .kick_tx_queue = rt2500usb_kick_tx_queue,
1808 .fill_rxdone = rt2500usb_fill_rxdone, 1768 .fill_rxdone = rt2500usb_fill_rxdone,
@@ -1816,14 +1776,14 @@ static const struct data_queue_desc rt2500usb_queue_rx = {
1816 .entry_num = RX_ENTRIES, 1776 .entry_num = RX_ENTRIES,
1817 .data_size = DATA_FRAME_SIZE, 1777 .data_size = DATA_FRAME_SIZE,
1818 .desc_size = RXD_DESC_SIZE, 1778 .desc_size = RXD_DESC_SIZE,
1819 .priv_size = sizeof(struct queue_entry_priv_usb_rx), 1779 .priv_size = sizeof(struct queue_entry_priv_usb),
1820}; 1780};
1821 1781
1822static const struct data_queue_desc rt2500usb_queue_tx = { 1782static const struct data_queue_desc rt2500usb_queue_tx = {
1823 .entry_num = TX_ENTRIES, 1783 .entry_num = TX_ENTRIES,
1824 .data_size = DATA_FRAME_SIZE, 1784 .data_size = DATA_FRAME_SIZE,
1825 .desc_size = TXD_DESC_SIZE, 1785 .desc_size = TXD_DESC_SIZE,
1826 .priv_size = sizeof(struct queue_entry_priv_usb_tx), 1786 .priv_size = sizeof(struct queue_entry_priv_usb),
1827}; 1787};
1828 1788
1829static const struct data_queue_desc rt2500usb_queue_bcn = { 1789static const struct data_queue_desc rt2500usb_queue_bcn = {
@@ -1837,7 +1797,7 @@ static const struct data_queue_desc rt2500usb_queue_atim = {
1837 .entry_num = ATIM_ENTRIES, 1797 .entry_num = ATIM_ENTRIES,
1838 .data_size = DATA_FRAME_SIZE, 1798 .data_size = DATA_FRAME_SIZE,
1839 .desc_size = TXD_DESC_SIZE, 1799 .desc_size = TXD_DESC_SIZE,
1840 .priv_size = sizeof(struct queue_entry_priv_usb_tx), 1800 .priv_size = sizeof(struct queue_entry_priv_usb),
1841}; 1801};
1842 1802
1843static const struct rt2x00_ops rt2500usb_ops = { 1803static const struct rt2x00_ops rt2500usb_ops = {
@@ -1846,6 +1806,7 @@ static const struct rt2x00_ops rt2500usb_ops = {
1846 .max_ap_intf = 1, 1806 .max_ap_intf = 1,
1847 .eeprom_size = EEPROM_SIZE, 1807 .eeprom_size = EEPROM_SIZE,
1848 .rf_size = RF_SIZE, 1808 .rf_size = RF_SIZE,
1809 .tx_queues = NUM_TX_QUEUES,
1849 .rx = &rt2500usb_queue_rx, 1810 .rx = &rt2500usb_queue_rx,
1850 .tx = &rt2500usb_queue_tx, 1811 .tx = &rt2500usb_queue_tx,
1851 .bcn = &rt2500usb_queue_bcn, 1812 .bcn = &rt2500usb_queue_bcn,
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.h b/drivers/net/wireless/rt2x00/rt2500usb.h
index a37a068d0c71..4769ffeb4cc6 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.h
+++ b/drivers/net/wireless/rt2x00/rt2500usb.h
@@ -48,8 +48,6 @@
48 * Signal information. 48 * Signal information.
49 * Defaul offset is required for RSSI <-> dBm conversion. 49 * Defaul offset is required for RSSI <-> dBm conversion.
50 */ 50 */
51#define MAX_SIGNAL 100
52#define MAX_RX_SSI -1
53#define DEFAULT_RSSI_OFFSET 120 51#define DEFAULT_RSSI_OFFSET 120
54 52
55/* 53/*
@@ -63,6 +61,11 @@
63#define RF_SIZE 0x0014 61#define RF_SIZE 0x0014
64 62
65/* 63/*
64 * Number of TX queues.
65 */
66#define NUM_TX_QUEUES 2
67
68/*
66 * Control/Status Registers(CSR). 69 * Control/Status Registers(CSR).
67 * Some values are set in TU, whereas 1 TU == 1024 us. 70 * Some values are set in TU, whereas 1 TU == 1024 us.
68 */ 71 */
@@ -206,7 +209,7 @@
206#define MAC_CSR21_OFF_PERIOD FIELD16(0xff00) 209#define MAC_CSR21_OFF_PERIOD FIELD16(0xff00)
207 210
208/* 211/*
209 * Collision window control register. 212 * MAC_CSR22: Collision window control register.
210 */ 213 */
211#define MAC_CSR22 0x042c 214#define MAC_CSR22 0x042c
212 215
@@ -293,7 +296,7 @@
293#define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000) 296#define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000)
294 297
295/* 298/*
296 * TXRX_CSR5: OFDM TX BBP ID1. 299 * TXRX_CSR8: OFDM TX BBP ID1.
297 */ 300 */
298#define TXRX_CSR8 0x0450 301#define TXRX_CSR8 0x0450
299#define TXRX_CSR8_BBP_ID0 FIELD16(0x007f) 302#define TXRX_CSR8_BBP_ID0 FIELD16(0x007f)
@@ -367,7 +370,14 @@
367 */ 370 */
368 371
369/* 372/*
370 * SEC_CSR0-SEC_CSR7: Shared key 0, word 0-7 373 * SEC_CSR0: Shared key 0, word 0
374 * SEC_CSR1: Shared key 0, word 1
375 * SEC_CSR2: Shared key 0, word 2
376 * SEC_CSR3: Shared key 0, word 3
377 * SEC_CSR4: Shared key 0, word 4
378 * SEC_CSR5: Shared key 0, word 5
379 * SEC_CSR6: Shared key 0, word 6
380 * SEC_CSR7: Shared key 0, word 7
371 */ 381 */
372#define SEC_CSR0 0x0480 382#define SEC_CSR0 0x0480
373#define SEC_CSR1 0x0482 383#define SEC_CSR1 0x0482
@@ -379,7 +389,14 @@
379#define SEC_CSR7 0x048e 389#define SEC_CSR7 0x048e
380 390
381/* 391/*
382 * SEC_CSR8-SEC_CSR15: Shared key 1, word 0-7 392 * SEC_CSR8: Shared key 1, word 0
393 * SEC_CSR9: Shared key 1, word 1
394 * SEC_CSR10: Shared key 1, word 2
395 * SEC_CSR11: Shared key 1, word 3
396 * SEC_CSR12: Shared key 1, word 4
397 * SEC_CSR13: Shared key 1, word 5
398 * SEC_CSR14: Shared key 1, word 6
399 * SEC_CSR15: Shared key 1, word 7
383 */ 400 */
384#define SEC_CSR8 0x0490 401#define SEC_CSR8 0x0490
385#define SEC_CSR9 0x0492 402#define SEC_CSR9 0x0492
@@ -391,7 +408,14 @@
391#define SEC_CSR15 0x049e 408#define SEC_CSR15 0x049e
392 409
393/* 410/*
394 * SEC_CSR16-SEC_CSR23: Shared key 2, word 0-7 411 * SEC_CSR16: Shared key 2, word 0
412 * SEC_CSR17: Shared key 2, word 1
413 * SEC_CSR18: Shared key 2, word 2
414 * SEC_CSR19: Shared key 2, word 3
415 * SEC_CSR20: Shared key 2, word 4
416 * SEC_CSR21: Shared key 2, word 5
417 * SEC_CSR22: Shared key 2, word 6
418 * SEC_CSR23: Shared key 2, word 7
395 */ 419 */
396#define SEC_CSR16 0x04a0 420#define SEC_CSR16 0x04a0
397#define SEC_CSR17 0x04a2 421#define SEC_CSR17 0x04a2
@@ -403,7 +427,14 @@
403#define SEC_CSR23 0x04ae 427#define SEC_CSR23 0x04ae
404 428
405/* 429/*
406 * SEC_CSR24-SEC_CSR31: Shared key 3, word 0-7 430 * SEC_CSR24: Shared key 3, word 0
431 * SEC_CSR25: Shared key 3, word 1
432 * SEC_CSR26: Shared key 3, word 2
433 * SEC_CSR27: Shared key 3, word 3
434 * SEC_CSR28: Shared key 3, word 4
435 * SEC_CSR29: Shared key 3, word 5
436 * SEC_CSR30: Shared key 3, word 6
437 * SEC_CSR31: Shared key 3, word 7
407 */ 438 */
408#define SEC_CSR24 0x04b0 439#define SEC_CSR24 0x04b0
409#define SEC_CSR25 0x04b2 440#define SEC_CSR25 0x04b2
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index a74e1a5c56fd..07b03b3c7ef1 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -44,7 +44,7 @@
44/* 44/*
45 * Module information. 45 * Module information.
46 */ 46 */
47#define DRV_VERSION "2.1.4" 47#define DRV_VERSION "2.1.8"
48#define DRV_PROJECT "http://rt2x00.serialmonkey.com" 48#define DRV_PROJECT "http://rt2x00.serialmonkey.com"
49 49
50/* 50/*
@@ -111,33 +111,6 @@
111#define EIFS ( SIFS + (8 * (IEEE80211_HEADER + ACK_SIZE)) ) 111#define EIFS ( SIFS + (8 * (IEEE80211_HEADER + ACK_SIZE)) )
112 112
113/* 113/*
114 * IEEE802.11 header defines
115 */
116static inline int is_rts_frame(u16 fc)
117{
118 return (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL) &&
119 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_RTS));
120}
121
122static inline int is_cts_frame(u16 fc)
123{
124 return (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL) &&
125 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_CTS));
126}
127
128static inline int is_probe_resp(u16 fc)
129{
130 return (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
131 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_PROBE_RESP));
132}
133
134static inline int is_beacon(u16 fc)
135{
136 return (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
137 ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_BEACON));
138}
139
140/*
141 * Chipset identification 114 * Chipset identification
142 * The chipset on the device is composed of a RT and RF chip. 115 * The chipset on the device is composed of a RT and RF chip.
143 * The chipset combination is important for determining device capabilities. 116 * The chipset combination is important for determining device capabilities.
@@ -391,6 +364,8 @@ struct rt2x00_intf {
391#define DELAYED_UPDATE_BEACON 0x00000001 364#define DELAYED_UPDATE_BEACON 0x00000001
392#define DELAYED_CONFIG_ERP 0x00000002 365#define DELAYED_CONFIG_ERP 0x00000002
393#define DELAYED_LED_ASSOC 0x00000004 366#define DELAYED_LED_ASSOC 0x00000004
367
368 u16 seqno;
394}; 369};
395 370
396static inline struct rt2x00_intf* vif_to_intf(struct ieee80211_vif *vif) 371static inline struct rt2x00_intf* vif_to_intf(struct ieee80211_vif *vif)
@@ -409,7 +384,7 @@ static inline struct rt2x00_intf* vif_to_intf(struct ieee80211_vif *vif)
409 * @supported_rates: Rate types which are supported (CCK, OFDM). 384 * @supported_rates: Rate types which are supported (CCK, OFDM).
410 * @num_channels: Number of supported channels. This is used as array size 385 * @num_channels: Number of supported channels. This is used as array size
411 * for @tx_power_a, @tx_power_bg and @channels. 386 * for @tx_power_a, @tx_power_bg and @channels.
412 * channels: Device/chipset specific channel values (See &struct rf_channel). 387 * @channels: Device/chipset specific channel values (See &struct rf_channel).
413 * @tx_power_a: TX power values for all 5.2GHz channels (may be NULL). 388 * @tx_power_a: TX power values for all 5.2GHz channels (may be NULL).
414 * @tx_power_bg: TX power values for all 2.4GHz channels (may be NULL). 389 * @tx_power_bg: TX power values for all 2.4GHz channels (may be NULL).
415 * @tx_power_default: Default TX power value to use when either 390 * @tx_power_default: Default TX power value to use when either
@@ -461,6 +436,7 @@ struct rt2x00lib_conf {
461 */ 436 */
462struct rt2x00lib_erp { 437struct rt2x00lib_erp {
463 int short_preamble; 438 int short_preamble;
439 int cts_protection;
464 440
465 int ack_timeout; 441 int ack_timeout;
466 int ack_consume_time; 442 int ack_consume_time;
@@ -545,15 +521,13 @@ struct rt2x00lib_ops {
545 */ 521 */
546 void (*write_tx_desc) (struct rt2x00_dev *rt2x00dev, 522 void (*write_tx_desc) (struct rt2x00_dev *rt2x00dev,
547 struct sk_buff *skb, 523 struct sk_buff *skb,
548 struct txentry_desc *txdesc, 524 struct txentry_desc *txdesc);
549 struct ieee80211_tx_control *control); 525 int (*write_tx_data) (struct queue_entry *entry);
550 int (*write_tx_data) (struct rt2x00_dev *rt2x00dev, 526 void (*write_beacon) (struct queue_entry *entry);
551 struct data_queue *queue, struct sk_buff *skb,
552 struct ieee80211_tx_control *control);
553 int (*get_tx_data_len) (struct rt2x00_dev *rt2x00dev, 527 int (*get_tx_data_len) (struct rt2x00_dev *rt2x00dev,
554 struct sk_buff *skb); 528 struct sk_buff *skb);
555 void (*kick_tx_queue) (struct rt2x00_dev *rt2x00dev, 529 void (*kick_tx_queue) (struct rt2x00_dev *rt2x00dev,
556 const unsigned int queue); 530 const enum data_queue_qid queue);
557 531
558 /* 532 /*
559 * RX control handlers 533 * RX control handlers
@@ -597,6 +571,7 @@ struct rt2x00_ops {
597 const unsigned int max_ap_intf; 571 const unsigned int max_ap_intf;
598 const unsigned int eeprom_size; 572 const unsigned int eeprom_size;
599 const unsigned int rf_size; 573 const unsigned int rf_size;
574 const unsigned int tx_queues;
600 const struct data_queue_desc *rx; 575 const struct data_queue_desc *rx;
601 const struct data_queue_desc *tx; 576 const struct data_queue_desc *tx;
602 const struct data_queue_desc *bcn; 577 const struct data_queue_desc *bcn;
@@ -626,11 +601,11 @@ enum rt2x00_flags {
626 /* 601 /*
627 * Driver features 602 * Driver features
628 */ 603 */
629 DRIVER_SUPPORT_MIXED_INTERFACES,
630 DRIVER_REQUIRE_FIRMWARE, 604 DRIVER_REQUIRE_FIRMWARE,
631 DRIVER_REQUIRE_BEACON_GUARD, 605 DRIVER_REQUIRE_BEACON_GUARD,
632 DRIVER_REQUIRE_ATIM_QUEUE, 606 DRIVER_REQUIRE_ATIM_QUEUE,
633 DRIVER_REQUIRE_SCHEDULED, 607 DRIVER_REQUIRE_SCHEDULED,
608 DRIVER_REQUIRE_DMA,
634 609
635 /* 610 /*
636 * Driver configuration 611 * Driver configuration
@@ -655,11 +630,7 @@ struct rt2x00_dev {
655 * When accessing this variable, the rt2x00dev_{pci,usb} 630 * When accessing this variable, the rt2x00dev_{pci,usb}
656 * macro's should be used for correct typecasting. 631 * macro's should be used for correct typecasting.
657 */ 632 */
658 void *dev; 633 struct device *dev;
659#define rt2x00dev_pci(__dev) ( (struct pci_dev *)(__dev)->dev )
660#define rt2x00dev_usb(__dev) ( (struct usb_interface *)(__dev)->dev )
661#define rt2x00dev_usb_dev(__dev)\
662 ( (struct usb_device *)interface_to_usbdev(rt2x00dev_usb(__dev)) )
663 634
664 /* 635 /*
665 * Callback functions. 636 * Callback functions.
@@ -682,7 +653,7 @@ struct rt2x00_dev {
682#define RFKILL_STATE_ALLOCATED 1 653#define RFKILL_STATE_ALLOCATED 1
683#define RFKILL_STATE_REGISTERED 2 654#define RFKILL_STATE_REGISTERED 2
684 struct rfkill *rfkill; 655 struct rfkill *rfkill;
685 struct input_polled_dev *poll_dev; 656 struct delayed_work rfkill_work;
686#endif /* CONFIG_RT2X00_LIB_RFKILL */ 657#endif /* CONFIG_RT2X00_LIB_RFKILL */
687 658
688 /* 659 /*
@@ -820,8 +791,10 @@ struct rt2x00_dev {
820 791
821 /* 792 /*
822 * Scheduled work. 793 * Scheduled work.
794 * NOTE: intf_work will use ieee80211_iterate_active_interfaces()
795 * which means it cannot be placed on the hw->workqueue
796 * due to RTNL locking requirements.
823 */ 797 */
824 struct workqueue_struct *workqueue;
825 struct work_struct intf_work; 798 struct work_struct intf_work;
826 struct work_struct filter_work; 799 struct work_struct filter_work;
827 800
@@ -830,7 +803,7 @@ struct rt2x00_dev {
830 * The Beacon array also contains the Atim queue 803 * The Beacon array also contains the Atim queue
831 * if that is supported by the device. 804 * if that is supported by the device.
832 */ 805 */
833 int data_queues; 806 unsigned int data_queues;
834 struct data_queue *rx; 807 struct data_queue *rx;
835 struct data_queue *tx; 808 struct data_queue *tx;
836 struct data_queue *bcn; 809 struct data_queue *bcn;
@@ -934,55 +907,41 @@ static inline u16 get_duration_res(const unsigned int size, const u8 rate)
934} 907}
935 908
936/** 909/**
937 * rt2x00queue_get_queue - Convert mac80211 queue index to rt2x00 queue 910 * rt2x00queue_map_txskb - Map a skb into DMA for TX purposes.
938 * @rt2x00dev: Pointer to &struct rt2x00_dev. 911 * @rt2x00dev: Pointer to &struct rt2x00_dev.
939 * @queue: mac80211/rt2x00 queue index 912 * @skb: The skb to map.
940 * (see &enum ieee80211_tx_queue and &enum rt2x00_bcn_queue). 913 */
914void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb);
915
916/**
917 * rt2x00queue_get_queue - Convert queue index to queue pointer
918 * @rt2x00dev: Pointer to &struct rt2x00_dev.
919 * @queue: rt2x00 queue index (see &enum data_queue_qid).
941 */ 920 */
942struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev, 921struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
943 const unsigned int queue); 922 const enum data_queue_qid queue);
944 923
945/** 924/**
946 * rt2x00queue_get_entry - Get queue entry where the given index points to. 925 * rt2x00queue_get_entry - Get queue entry where the given index points to.
947 * @rt2x00dev: Pointer to &struct rt2x00_dev. 926 * @queue: Pointer to &struct data_queue from where we obtain the entry.
948 * @index: Index identifier for obtaining the correct index. 927 * @index: Index identifier for obtaining the correct index.
949 */ 928 */
950struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue, 929struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
951 enum queue_index index); 930 enum queue_index index);
952 931
953/**
954 * rt2x00queue_index_inc - Index incrementation function
955 * @queue: Queue (&struct data_queue) to perform the action on.
956 * @action: Index type (&enum queue_index) to perform the action on.
957 *
958 * This function will increase the requested index on the queue,
959 * it will grab the appropriate locks and handle queue overflow events by
960 * resetting the index to the start of the queue.
961 */
962void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index);
963
964
965/* 932/*
966 * Interrupt context handlers. 933 * Interrupt context handlers.
967 */ 934 */
968void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev); 935void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev);
969void rt2x00lib_txdone(struct queue_entry *entry, 936void rt2x00lib_txdone(struct queue_entry *entry,
970 struct txdone_entry_desc *txdesc); 937 struct txdone_entry_desc *txdesc);
971void rt2x00lib_rxdone(struct queue_entry *entry, 938void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
972 struct rxdone_entry_desc *rxdesc); 939 struct queue_entry *entry);
973
974/*
975 * TX descriptor initializer
976 */
977void rt2x00lib_write_tx_desc(struct rt2x00_dev *rt2x00dev,
978 struct sk_buff *skb,
979 struct ieee80211_tx_control *control);
980 940
981/* 941/*
982 * mac80211 handlers. 942 * mac80211 handlers.
983 */ 943 */
984int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb, 944int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
985 struct ieee80211_tx_control *control);
986int rt2x00mac_start(struct ieee80211_hw *hw); 945int rt2x00mac_start(struct ieee80211_hw *hw);
987void rt2x00mac_stop(struct ieee80211_hw *hw); 946void rt2x00mac_stop(struct ieee80211_hw *hw);
988int rt2x00mac_add_interface(struct ieee80211_hw *hw, 947int rt2x00mac_add_interface(struct ieee80211_hw *hw,
@@ -1005,7 +964,7 @@ void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
1005 struct ieee80211_vif *vif, 964 struct ieee80211_vif *vif,
1006 struct ieee80211_bss_conf *bss_conf, 965 struct ieee80211_bss_conf *bss_conf,
1007 u32 changes); 966 u32 changes);
1008int rt2x00mac_conf_tx(struct ieee80211_hw *hw, int queue, 967int rt2x00mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
1009 const struct ieee80211_tx_queue_params *params); 968 const struct ieee80211_tx_queue_params *params);
1010 969
1011/* 970/*
diff --git a/drivers/net/wireless/rt2x00/rt2x00config.c b/drivers/net/wireless/rt2x00/rt2x00config.c
index 48608e8cc8b4..f20ca712504f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00config.c
+++ b/drivers/net/wireless/rt2x00/rt2x00config.c
@@ -84,6 +84,8 @@ void rt2x00lib_config_erp(struct rt2x00_dev *rt2x00dev,
84 memset(&erp, 0, sizeof(erp)); 84 memset(&erp, 0, sizeof(erp));
85 85
86 erp.short_preamble = bss_conf->use_short_preamble; 86 erp.short_preamble = bss_conf->use_short_preamble;
87 erp.cts_protection = bss_conf->use_cts_prot;
88
87 erp.ack_timeout = PLCP + get_duration(ACK_SIZE, 10); 89 erp.ack_timeout = PLCP + get_duration(ACK_SIZE, 10);
88 erp.ack_consume_time = SIFS + PLCP + get_duration(ACK_SIZE, 10); 90 erp.ack_consume_time = SIFS + PLCP + get_duration(ACK_SIZE, 10);
89 91
diff --git a/drivers/net/wireless/rt2x00/rt2x00debug.c b/drivers/net/wireless/rt2x00/rt2x00debug.c
index bfab3b8780d6..300cf061035f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00debug.c
+++ b/drivers/net/wireless/rt2x00/rt2x00debug.c
@@ -115,7 +115,7 @@ struct rt2x00debug_intf {
115}; 115};
116 116
117void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev, 117void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
118 struct sk_buff *skb) 118 enum rt2x00_dump_type type, struct sk_buff *skb)
119{ 119{
120 struct rt2x00debug_intf *intf = rt2x00dev->debugfs_intf; 120 struct rt2x00debug_intf *intf = rt2x00dev->debugfs_intf;
121 struct skb_frame_desc *desc = get_skb_frame_desc(skb); 121 struct skb_frame_desc *desc = get_skb_frame_desc(skb);
@@ -133,7 +133,7 @@ void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
133 return; 133 return;
134 } 134 }
135 135
136 skbcopy = alloc_skb(sizeof(*dump_hdr) + desc->desc_len + desc->data_len, 136 skbcopy = alloc_skb(sizeof(*dump_hdr) + desc->desc_len + skb->len,
137 GFP_ATOMIC); 137 GFP_ATOMIC);
138 if (!skbcopy) { 138 if (!skbcopy) {
139 DEBUG(rt2x00dev, "Failed to copy skb for dump.\n"); 139 DEBUG(rt2x00dev, "Failed to copy skb for dump.\n");
@@ -144,18 +144,18 @@ void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
144 dump_hdr->version = cpu_to_le32(DUMP_HEADER_VERSION); 144 dump_hdr->version = cpu_to_le32(DUMP_HEADER_VERSION);
145 dump_hdr->header_length = cpu_to_le32(sizeof(*dump_hdr)); 145 dump_hdr->header_length = cpu_to_le32(sizeof(*dump_hdr));
146 dump_hdr->desc_length = cpu_to_le32(desc->desc_len); 146 dump_hdr->desc_length = cpu_to_le32(desc->desc_len);
147 dump_hdr->data_length = cpu_to_le32(desc->data_len); 147 dump_hdr->data_length = cpu_to_le32(skb->len);
148 dump_hdr->chip_rt = cpu_to_le16(rt2x00dev->chip.rt); 148 dump_hdr->chip_rt = cpu_to_le16(rt2x00dev->chip.rt);
149 dump_hdr->chip_rf = cpu_to_le16(rt2x00dev->chip.rf); 149 dump_hdr->chip_rf = cpu_to_le16(rt2x00dev->chip.rf);
150 dump_hdr->chip_rev = cpu_to_le32(rt2x00dev->chip.rev); 150 dump_hdr->chip_rev = cpu_to_le32(rt2x00dev->chip.rev);
151 dump_hdr->type = cpu_to_le16(desc->frame_type); 151 dump_hdr->type = cpu_to_le16(type);
152 dump_hdr->queue_index = desc->entry->queue->qid; 152 dump_hdr->queue_index = desc->entry->queue->qid;
153 dump_hdr->entry_index = desc->entry->entry_idx; 153 dump_hdr->entry_index = desc->entry->entry_idx;
154 dump_hdr->timestamp_sec = cpu_to_le32(timestamp.tv_sec); 154 dump_hdr->timestamp_sec = cpu_to_le32(timestamp.tv_sec);
155 dump_hdr->timestamp_usec = cpu_to_le32(timestamp.tv_usec); 155 dump_hdr->timestamp_usec = cpu_to_le32(timestamp.tv_usec);
156 156
157 memcpy(skb_put(skbcopy, desc->desc_len), desc->desc, desc->desc_len); 157 memcpy(skb_put(skbcopy, desc->desc_len), desc->desc, desc->desc_len);
158 memcpy(skb_put(skbcopy, desc->data_len), desc->data, desc->data_len); 158 memcpy(skb_put(skbcopy, skb->len), skb->data, skb->len);
159 159
160 skb_queue_tail(&intf->frame_dump_skbqueue, skbcopy); 160 skb_queue_tail(&intf->frame_dump_skbqueue, skbcopy);
161 wake_up_interruptible(&intf->frame_dump_waitqueue); 161 wake_up_interruptible(&intf->frame_dump_waitqueue);
diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c
index c997d4f28ab3..8c93eb8353b0 100644
--- a/drivers/net/wireless/rt2x00/rt2x00dev.c
+++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
@@ -28,7 +28,6 @@
28 28
29#include "rt2x00.h" 29#include "rt2x00.h"
30#include "rt2x00lib.h" 30#include "rt2x00lib.h"
31#include "rt2x00dump.h"
32 31
33/* 32/*
34 * Link tuning handlers 33 * Link tuning handlers
@@ -75,7 +74,7 @@ static void rt2x00lib_start_link_tuner(struct rt2x00_dev *rt2x00dev)
75 74
76 rt2x00lib_reset_link_tuner(rt2x00dev); 75 rt2x00lib_reset_link_tuner(rt2x00dev);
77 76
78 queue_delayed_work(rt2x00dev->workqueue, 77 queue_delayed_work(rt2x00dev->hw->workqueue,
79 &rt2x00dev->link.work, LINK_TUNE_INTERVAL); 78 &rt2x00dev->link.work, LINK_TUNE_INTERVAL);
80} 79}
81 80
@@ -113,6 +112,8 @@ int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev)
113 if (status) 112 if (status)
114 return status; 113 return status;
115 114
115 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_ON);
116
116 rt2x00leds_led_radio(rt2x00dev, true); 117 rt2x00leds_led_radio(rt2x00dev, true);
117 rt2x00led_led_activity(rt2x00dev, true); 118 rt2x00led_led_activity(rt2x00dev, true);
118 119
@@ -126,7 +127,7 @@ int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev)
126 /* 127 /*
127 * Start the TX queues. 128 * Start the TX queues.
128 */ 129 */
129 ieee80211_start_queues(rt2x00dev->hw); 130 ieee80211_wake_queues(rt2x00dev->hw);
130 131
131 return 0; 132 return 0;
132} 133}
@@ -150,6 +151,7 @@ void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev)
150 * Disable radio. 151 * Disable radio.
151 */ 152 */
152 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_OFF); 153 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_OFF);
154 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
153 rt2x00led_led_activity(rt2x00dev, false); 155 rt2x00led_led_activity(rt2x00dev, false);
154 rt2x00leds_led_radio(rt2x00dev, false); 156 rt2x00leds_led_radio(rt2x00dev, false);
155} 157}
@@ -390,7 +392,7 @@ static void rt2x00lib_link_tuner(struct work_struct *work)
390 * Increase tuner counter, and reschedule the next link tuner run. 392 * Increase tuner counter, and reschedule the next link tuner run.
391 */ 393 */
392 rt2x00dev->link.count++; 394 rt2x00dev->link.count++;
393 queue_delayed_work(rt2x00dev->workqueue, 395 queue_delayed_work(rt2x00dev->hw->workqueue,
394 &rt2x00dev->link.work, LINK_TUNE_INTERVAL); 396 &rt2x00dev->link.work, LINK_TUNE_INTERVAL);
395} 397}
396 398
@@ -407,8 +409,6 @@ static void rt2x00lib_intf_scheduled_iter(void *data, u8 *mac,
407{ 409{
408 struct rt2x00_dev *rt2x00dev = data; 410 struct rt2x00_dev *rt2x00dev = data;
409 struct rt2x00_intf *intf = vif_to_intf(vif); 411 struct rt2x00_intf *intf = vif_to_intf(vif);
410 struct sk_buff *skb;
411 struct ieee80211_tx_control control;
412 struct ieee80211_bss_conf conf; 412 struct ieee80211_bss_conf conf;
413 int delayed_flags; 413 int delayed_flags;
414 414
@@ -434,12 +434,8 @@ static void rt2x00lib_intf_scheduled_iter(void *data, u8 *mac,
434 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags)) 434 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
435 return; 435 return;
436 436
437 if (delayed_flags & DELAYED_UPDATE_BEACON) { 437 if (delayed_flags & DELAYED_UPDATE_BEACON)
438 skb = ieee80211_beacon_get(rt2x00dev->hw, vif, &control); 438 rt2x00queue_update_beacon(rt2x00dev, vif);
439 if (skb && rt2x00dev->ops->hw->beacon_update(rt2x00dev->hw,
440 skb, &control))
441 dev_kfree_skb(skb);
442 }
443 439
444 if (delayed_flags & DELAYED_CONFIG_ERP) 440 if (delayed_flags & DELAYED_CONFIG_ERP)
445 rt2x00lib_config_erp(rt2x00dev, intf, &conf); 441 rt2x00lib_config_erp(rt2x00dev, intf, &conf);
@@ -468,12 +464,19 @@ static void rt2x00lib_intf_scheduled(struct work_struct *work)
468static void rt2x00lib_beacondone_iter(void *data, u8 *mac, 464static void rt2x00lib_beacondone_iter(void *data, u8 *mac,
469 struct ieee80211_vif *vif) 465 struct ieee80211_vif *vif)
470{ 466{
467 struct rt2x00_dev *rt2x00dev = data;
471 struct rt2x00_intf *intf = vif_to_intf(vif); 468 struct rt2x00_intf *intf = vif_to_intf(vif);
472 469
473 if (vif->type != IEEE80211_IF_TYPE_AP && 470 if (vif->type != IEEE80211_IF_TYPE_AP &&
474 vif->type != IEEE80211_IF_TYPE_IBSS) 471 vif->type != IEEE80211_IF_TYPE_IBSS)
475 return; 472 return;
476 473
474 /*
475 * Clean up the beacon skb.
476 */
477 rt2x00queue_free_skb(rt2x00dev, intf->beacon->skb);
478 intf->beacon->skb = NULL;
479
477 spin_lock(&intf->lock); 480 spin_lock(&intf->lock);
478 intf->delayed_flags |= DELAYED_UPDATE_BEACON; 481 intf->delayed_flags |= DELAYED_UPDATE_BEACON;
479 spin_unlock(&intf->lock); 482 spin_unlock(&intf->lock);
@@ -488,7 +491,7 @@ void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev)
488 rt2x00lib_beacondone_iter, 491 rt2x00lib_beacondone_iter,
489 rt2x00dev); 492 rt2x00dev);
490 493
491 queue_work(rt2x00dev->workqueue, &rt2x00dev->intf_work); 494 schedule_work(&rt2x00dev->intf_work);
492} 495}
493EXPORT_SYMBOL_GPL(rt2x00lib_beacondone); 496EXPORT_SYMBOL_GPL(rt2x00lib_beacondone);
494 497
@@ -496,79 +499,132 @@ void rt2x00lib_txdone(struct queue_entry *entry,
496 struct txdone_entry_desc *txdesc) 499 struct txdone_entry_desc *txdesc)
497{ 500{
498 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 501 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
499 struct skb_frame_desc *skbdesc; 502 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
500 struct ieee80211_tx_status tx_status; 503 enum data_queue_qid qid = skb_get_queue_mapping(entry->skb);
501 int success = !!(txdesc->status == TX_SUCCESS || 504
502 txdesc->status == TX_SUCCESS_RETRY); 505 /*
503 int fail = !!(txdesc->status == TX_FAIL_RETRY || 506 * Unmap the skb.
504 txdesc->status == TX_FAIL_INVALID || 507 */
505 txdesc->status == TX_FAIL_OTHER); 508 rt2x00queue_unmap_skb(rt2x00dev, entry->skb);
509
510 /*
511 * Send frame to debugfs immediately, after this call is completed
512 * we are going to overwrite the skb->cb array.
513 */
514 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TXDONE, entry->skb);
506 515
507 /* 516 /*
508 * Update TX statistics. 517 * Update TX statistics.
509 */ 518 */
510 rt2x00dev->link.qual.tx_success += success; 519 rt2x00dev->link.qual.tx_success +=
511 rt2x00dev->link.qual.tx_failed += fail; 520 test_bit(TXDONE_SUCCESS, &txdesc->flags);
521 rt2x00dev->link.qual.tx_failed +=
522 test_bit(TXDONE_FAILURE, &txdesc->flags);
512 523
513 /* 524 /*
514 * Initialize TX status 525 * Initialize TX status
515 */ 526 */
516 tx_status.flags = 0; 527 memset(&tx_info->status, 0, sizeof(tx_info->status));
517 tx_status.ack_signal = 0; 528 tx_info->status.ack_signal = 0;
518 tx_status.excessive_retries = (txdesc->status == TX_FAIL_RETRY); 529 tx_info->status.excessive_retries =
519 tx_status.retry_count = txdesc->retry; 530 test_bit(TXDONE_EXCESSIVE_RETRY, &txdesc->flags);
520 memcpy(&tx_status.control, txdesc->control, sizeof(*txdesc->control)); 531 tx_info->status.retry_count = txdesc->retry;
521 532
522 if (!(tx_status.control.flags & IEEE80211_TXCTL_NO_ACK)) { 533 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) {
523 if (success) 534 if (test_bit(TXDONE_SUCCESS, &txdesc->flags))
524 tx_status.flags |= IEEE80211_TX_STATUS_ACK; 535 tx_info->flags |= IEEE80211_TX_STAT_ACK;
525 else 536 else if (test_bit(TXDONE_FAILURE, &txdesc->flags))
526 rt2x00dev->low_level_stats.dot11ACKFailureCount++; 537 rt2x00dev->low_level_stats.dot11ACKFailureCount++;
527 } 538 }
528 539
529 tx_status.queue_length = entry->queue->limit; 540 if (tx_info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
530 tx_status.queue_number = tx_status.control.queue; 541 if (test_bit(TXDONE_SUCCESS, &txdesc->flags))
531
532 if (tx_status.control.flags & IEEE80211_TXCTL_USE_RTS_CTS) {
533 if (success)
534 rt2x00dev->low_level_stats.dot11RTSSuccessCount++; 542 rt2x00dev->low_level_stats.dot11RTSSuccessCount++;
535 else 543 else if (test_bit(TXDONE_FAILURE, &txdesc->flags))
536 rt2x00dev->low_level_stats.dot11RTSFailureCount++; 544 rt2x00dev->low_level_stats.dot11RTSFailureCount++;
537 } 545 }
538 546
539 /* 547 /*
540 * Send the tx_status to debugfs. Only send the status report 548 * Only send the status report to mac80211 when TX status was
541 * to mac80211 when the frame originated from there. If this was 549 * requested by it. If this was a extra frame coming through
542 * a extra frame coming through a mac80211 library call (RTS/CTS) 550 * a mac80211 library call (RTS/CTS) then we should not send the
543 * then we should not send the status report back. 551 * status report back.
544 * If send to mac80211, mac80211 will clean up the skb structure,
545 * otherwise we have to do it ourself.
546 */ 552 */
547 skbdesc = get_skb_frame_desc(entry->skb); 553 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS)
548 skbdesc->frame_type = DUMP_FRAME_TXDONE; 554 ieee80211_tx_status_irqsafe(rt2x00dev->hw, entry->skb);
549
550 rt2x00debug_dump_frame(rt2x00dev, entry->skb);
551
552 if (!(skbdesc->flags & FRAME_DESC_DRIVER_GENERATED))
553 ieee80211_tx_status_irqsafe(rt2x00dev->hw,
554 entry->skb, &tx_status);
555 else 555 else
556 dev_kfree_skb(entry->skb); 556 dev_kfree_skb_irq(entry->skb);
557
558 /*
559 * Make this entry available for reuse.
560 */
557 entry->skb = NULL; 561 entry->skb = NULL;
562 entry->flags = 0;
563
564 rt2x00dev->ops->lib->init_txentry(rt2x00dev, entry);
565
566 __clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
567 rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);
568
569 /*
570 * If the data queue was below the threshold before the txdone
571 * handler we must make sure the packet queue in the mac80211 stack
572 * is reenabled when the txdone handler has finished.
573 */
574 if (!rt2x00queue_threshold(entry->queue))
575 ieee80211_wake_queue(rt2x00dev->hw, qid);
558} 576}
559EXPORT_SYMBOL_GPL(rt2x00lib_txdone); 577EXPORT_SYMBOL_GPL(rt2x00lib_txdone);
560 578
561void rt2x00lib_rxdone(struct queue_entry *entry, 579void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
562 struct rxdone_entry_desc *rxdesc) 580 struct queue_entry *entry)
563{ 581{
564 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 582 struct rxdone_entry_desc rxdesc;
583 struct sk_buff *skb;
565 struct ieee80211_rx_status *rx_status = &rt2x00dev->rx_status; 584 struct ieee80211_rx_status *rx_status = &rt2x00dev->rx_status;
566 struct ieee80211_supported_band *sband; 585 struct ieee80211_supported_band *sband;
567 struct ieee80211_hdr *hdr; 586 struct ieee80211_hdr *hdr;
568 const struct rt2x00_rate *rate; 587 const struct rt2x00_rate *rate;
588 unsigned int header_size;
589 unsigned int align;
569 unsigned int i; 590 unsigned int i;
570 int idx = -1; 591 int idx = -1;
571 u16 fc; 592
593 /*
594 * Allocate a new sk_buffer. If no new buffer available, drop the
595 * received frame and reuse the existing buffer.
596 */
597 skb = rt2x00queue_alloc_rxskb(rt2x00dev, entry);
598 if (!skb)
599 return;
600
601 /*
602 * Unmap the skb.
603 */
604 rt2x00queue_unmap_skb(rt2x00dev, entry->skb);
605
606 /*
607 * Extract the RXD details.
608 */
609 memset(&rxdesc, 0, sizeof(rxdesc));
610 rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
611
612 /*
613 * The data behind the ieee80211 header must be
614 * aligned on a 4 byte boundary.
615 */
616 header_size = ieee80211_get_hdrlen_from_skb(entry->skb);
617 align = ((unsigned long)(entry->skb->data + header_size)) & 3;
618
619 if (align) {
620 skb_push(entry->skb, align);
621 /* Move entire frame in 1 command */
622 memmove(entry->skb->data, entry->skb->data + align,
623 rxdesc.size);
624 }
625
626 /* Update data pointers, trim buffer to correct size */
627 skb_trim(entry->skb, rxdesc.size);
572 628
573 /* 629 /*
574 * Update RX statistics. 630 * Update RX statistics.
@@ -577,10 +633,10 @@ void rt2x00lib_rxdone(struct queue_entry *entry,
577 for (i = 0; i < sband->n_bitrates; i++) { 633 for (i = 0; i < sband->n_bitrates; i++) {
578 rate = rt2x00_get_rate(sband->bitrates[i].hw_value); 634 rate = rt2x00_get_rate(sband->bitrates[i].hw_value);
579 635
580 if (((rxdesc->dev_flags & RXDONE_SIGNAL_PLCP) && 636 if (((rxdesc.dev_flags & RXDONE_SIGNAL_PLCP) &&
581 (rate->plcp == rxdesc->signal)) || 637 (rate->plcp == rxdesc.signal)) ||
582 (!(rxdesc->dev_flags & RXDONE_SIGNAL_PLCP) && 638 (!(rxdesc.dev_flags & RXDONE_SIGNAL_PLCP) &&
583 (rate->bitrate == rxdesc->signal))) { 639 (rate->bitrate == rxdesc.signal))) {
584 idx = i; 640 idx = i;
585 break; 641 break;
586 } 642 }
@@ -588,8 +644,8 @@ void rt2x00lib_rxdone(struct queue_entry *entry,
588 644
589 if (idx < 0) { 645 if (idx < 0) {
590 WARNING(rt2x00dev, "Frame received with unrecognized signal," 646 WARNING(rt2x00dev, "Frame received with unrecognized signal,"
591 "signal=0x%.2x, plcp=%d.\n", rxdesc->signal, 647 "signal=0x%.2x, plcp=%d.\n", rxdesc.signal,
592 !!(rxdesc->dev_flags & RXDONE_SIGNAL_PLCP)); 648 !!(rxdesc.dev_flags & RXDONE_SIGNAL_PLCP));
593 idx = 0; 649 idx = 0;
594 } 650 }
595 651
@@ -597,170 +653,38 @@ void rt2x00lib_rxdone(struct queue_entry *entry,
597 * Only update link status if this is a beacon frame carrying our bssid. 653 * Only update link status if this is a beacon frame carrying our bssid.
598 */ 654 */
599 hdr = (struct ieee80211_hdr *)entry->skb->data; 655 hdr = (struct ieee80211_hdr *)entry->skb->data;
600 fc = le16_to_cpu(hdr->frame_control); 656 if (ieee80211_is_beacon(hdr->frame_control) &&
601 if (is_beacon(fc) && (rxdesc->dev_flags & RXDONE_MY_BSS)) 657 (rxdesc.dev_flags & RXDONE_MY_BSS))
602 rt2x00lib_update_link_stats(&rt2x00dev->link, rxdesc->rssi); 658 rt2x00lib_update_link_stats(&rt2x00dev->link, rxdesc.rssi);
603 659
604 rt2x00dev->link.qual.rx_success++; 660 rt2x00dev->link.qual.rx_success++;
605 661
662 rx_status->mactime = rxdesc.timestamp;
606 rx_status->rate_idx = idx; 663 rx_status->rate_idx = idx;
607 rx_status->signal = 664 rx_status->qual =
608 rt2x00lib_calculate_link_signal(rt2x00dev, rxdesc->rssi); 665 rt2x00lib_calculate_link_signal(rt2x00dev, rxdesc.rssi);
609 rx_status->ssi = rxdesc->rssi; 666 rx_status->signal = rxdesc.rssi;
610 rx_status->flag = rxdesc->flags; 667 rx_status->flag = rxdesc.flags;
611 rx_status->antenna = rt2x00dev->link.ant.active.rx; 668 rx_status->antenna = rt2x00dev->link.ant.active.rx;
612 669
613 /* 670 /*
614 * Send frame to mac80211 & debugfs. 671 * Send frame to mac80211 & debugfs.
615 * mac80211 will clean up the skb structure. 672 * mac80211 will clean up the skb structure.
616 */ 673 */
617 get_skb_frame_desc(entry->skb)->frame_type = DUMP_FRAME_RXDONE; 674 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_RXDONE, entry->skb);
618 rt2x00debug_dump_frame(rt2x00dev, entry->skb);
619 ieee80211_rx_irqsafe(rt2x00dev->hw, entry->skb, rx_status); 675 ieee80211_rx_irqsafe(rt2x00dev->hw, entry->skb, rx_status);
620 entry->skb = NULL;
621}
622EXPORT_SYMBOL_GPL(rt2x00lib_rxdone);
623
624/*
625 * TX descriptor initializer
626 */
627void rt2x00lib_write_tx_desc(struct rt2x00_dev *rt2x00dev,
628 struct sk_buff *skb,
629 struct ieee80211_tx_control *control)
630{
631 struct txentry_desc txdesc;
632 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
633 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skbdesc->data;
634 const struct rt2x00_rate *rate;
635 int tx_rate;
636 int length;
637 int duration;
638 int residual;
639 u16 frame_control;
640 u16 seq_ctrl;
641
642 memset(&txdesc, 0, sizeof(txdesc));
643
644 txdesc.queue = skbdesc->entry->queue->qid;
645 txdesc.cw_min = skbdesc->entry->queue->cw_min;
646 txdesc.cw_max = skbdesc->entry->queue->cw_max;
647 txdesc.aifs = skbdesc->entry->queue->aifs;
648
649 /*
650 * Read required fields from ieee80211 header.
651 */
652 frame_control = le16_to_cpu(hdr->frame_control);
653 seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
654
655 tx_rate = control->tx_rate->hw_value;
656 676
657 /* 677 /*
658 * Check whether this frame is to be acked 678 * Replace the skb with the freshly allocated one.
659 */ 679 */
660 if (!(control->flags & IEEE80211_TXCTL_NO_ACK)) 680 entry->skb = skb;
661 __set_bit(ENTRY_TXD_ACK, &txdesc.flags); 681 entry->flags = 0;
662
663 /*
664 * Check if this is a RTS/CTS frame
665 */
666 if (is_rts_frame(frame_control) || is_cts_frame(frame_control)) {
667 __set_bit(ENTRY_TXD_BURST, &txdesc.flags);
668 if (is_rts_frame(frame_control)) {
669 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc.flags);
670 __set_bit(ENTRY_TXD_ACK, &txdesc.flags);
671 } else
672 __clear_bit(ENTRY_TXD_ACK, &txdesc.flags);
673 if (control->rts_cts_rate)
674 tx_rate = control->rts_cts_rate->hw_value;
675 }
676
677 rate = rt2x00_get_rate(tx_rate);
678
679 /*
680 * Check if more fragments are pending
681 */
682 if (ieee80211_get_morefrag(hdr)) {
683 __set_bit(ENTRY_TXD_BURST, &txdesc.flags);
684 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc.flags);
685 }
686
687 /*
688 * Beacons and probe responses require the tsf timestamp
689 * to be inserted into the frame.
690 */
691 if (control->queue == RT2X00_BCN_QUEUE_BEACON ||
692 is_probe_resp(frame_control))
693 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc.flags);
694
695 /*
696 * Determine with what IFS priority this frame should be send.
697 * Set ifs to IFS_SIFS when the this is not the first fragment,
698 * or this fragment came after RTS/CTS.
699 */
700 if ((seq_ctrl & IEEE80211_SCTL_FRAG) > 0 ||
701 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc.flags))
702 txdesc.ifs = IFS_SIFS;
703 else
704 txdesc.ifs = IFS_BACKOFF;
705
706 /*
707 * PLCP setup
708 * Length calculation depends on OFDM/CCK rate.
709 */
710 txdesc.signal = rate->plcp;
711 txdesc.service = 0x04;
712
713 length = skbdesc->data_len + FCS_LEN;
714 if (rate->flags & DEV_RATE_OFDM) {
715 __set_bit(ENTRY_TXD_OFDM_RATE, &txdesc.flags);
716
717 txdesc.length_high = (length >> 6) & 0x3f;
718 txdesc.length_low = length & 0x3f;
719 } else {
720 /*
721 * Convert length to microseconds.
722 */
723 residual = get_duration_res(length, rate->bitrate);
724 duration = get_duration(length, rate->bitrate);
725
726 if (residual != 0) {
727 duration++;
728
729 /*
730 * Check if we need to set the Length Extension
731 */
732 if (rate->bitrate == 110 && residual <= 30)
733 txdesc.service |= 0x80;
734 }
735
736 txdesc.length_high = (duration >> 8) & 0xff;
737 txdesc.length_low = duration & 0xff;
738
739 /*
740 * When preamble is enabled we should set the
741 * preamble bit for the signal.
742 */
743 if (rt2x00_get_rate_preamble(tx_rate))
744 txdesc.signal |= 0x08;
745 }
746
747 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, skb, &txdesc, control);
748 682
749 /* 683 rt2x00dev->ops->lib->init_rxentry(rt2x00dev, entry);
750 * Update queue entry.
751 */
752 skbdesc->entry->skb = skb;
753 684
754 /* 685 rt2x00queue_index_inc(entry->queue, Q_INDEX);
755 * The frame has been completely initialized and ready
756 * for sending to the device. The caller will push the
757 * frame to the device, but we are going to push the
758 * frame to debugfs here.
759 */
760 skbdesc->frame_type = DUMP_FRAME_TX;
761 rt2x00debug_dump_frame(rt2x00dev, skb);
762} 686}
763EXPORT_SYMBOL_GPL(rt2x00lib_write_tx_desc); 687EXPORT_SYMBOL_GPL(rt2x00lib_rxdone);
764 688
765/* 689/*
766 * Driver initialization handlers. 690 * Driver initialization handlers.
@@ -978,6 +902,11 @@ static int rt2x00lib_probe_hw(struct rt2x00_dev *rt2x00dev)
978 return status; 902 return status;
979 903
980 /* 904 /*
905 * Initialize HW fields.
906 */
907 rt2x00dev->hw->queues = rt2x00dev->ops->tx_queues;
908
909 /*
981 * Register HW. 910 * Register HW.
982 */ 911 */
983 status = ieee80211_register_hw(rt2x00dev->hw); 912 status = ieee80211_register_hw(rt2x00dev->hw);
@@ -1131,10 +1060,6 @@ int rt2x00lib_probe_dev(struct rt2x00_dev *rt2x00dev)
1131 /* 1060 /*
1132 * Initialize configuration work. 1061 * Initialize configuration work.
1133 */ 1062 */
1134 rt2x00dev->workqueue = create_singlethread_workqueue("rt2x00lib");
1135 if (!rt2x00dev->workqueue)
1136 goto exit;
1137
1138 INIT_WORK(&rt2x00dev->intf_work, rt2x00lib_intf_scheduled); 1063 INIT_WORK(&rt2x00dev->intf_work, rt2x00lib_intf_scheduled);
1139 INIT_WORK(&rt2x00dev->filter_work, rt2x00lib_packetfilter_scheduled); 1064 INIT_WORK(&rt2x00dev->filter_work, rt2x00lib_packetfilter_scheduled);
1140 INIT_DELAYED_WORK(&rt2x00dev->link.work, rt2x00lib_link_tuner); 1065 INIT_DELAYED_WORK(&rt2x00dev->link.work, rt2x00lib_link_tuner);
@@ -1195,13 +1120,6 @@ void rt2x00lib_remove_dev(struct rt2x00_dev *rt2x00dev)
1195 rt2x00leds_unregister(rt2x00dev); 1120 rt2x00leds_unregister(rt2x00dev);
1196 1121
1197 /* 1122 /*
1198 * Stop all queued work. Note that most tasks will already be halted
1199 * during rt2x00lib_disable_radio() and rt2x00lib_uninitialize().
1200 */
1201 flush_workqueue(rt2x00dev->workqueue);
1202 destroy_workqueue(rt2x00dev->workqueue);
1203
1204 /*
1205 * Free ieee80211_hw memory. 1123 * Free ieee80211_hw memory.
1206 */ 1124 */
1207 rt2x00lib_remove_hw(rt2x00dev); 1125 rt2x00lib_remove_hw(rt2x00dev);
@@ -1246,7 +1164,6 @@ int rt2x00lib_suspend(struct rt2x00_dev *rt2x00dev, pm_message_t state)
1246 * Suspend/disable extra components. 1164 * Suspend/disable extra components.
1247 */ 1165 */
1248 rt2x00leds_suspend(rt2x00dev); 1166 rt2x00leds_suspend(rt2x00dev);
1249 rt2x00rfkill_suspend(rt2x00dev);
1250 rt2x00debug_deregister(rt2x00dev); 1167 rt2x00debug_deregister(rt2x00dev);
1251 1168
1252exit: 1169exit:
@@ -1302,7 +1219,6 @@ int rt2x00lib_resume(struct rt2x00_dev *rt2x00dev)
1302 * Restore/enable extra components. 1219 * Restore/enable extra components.
1303 */ 1220 */
1304 rt2x00debug_register(rt2x00dev); 1221 rt2x00debug_register(rt2x00dev);
1305 rt2x00rfkill_resume(rt2x00dev);
1306 rt2x00leds_resume(rt2x00dev); 1222 rt2x00leds_resume(rt2x00dev);
1307 1223
1308 /* 1224 /*
@@ -1343,7 +1259,7 @@ int rt2x00lib_resume(struct rt2x00_dev *rt2x00dev)
1343 * In that case we have disabled the TX queue and should 1259 * In that case we have disabled the TX queue and should
1344 * now enable it again 1260 * now enable it again
1345 */ 1261 */
1346 ieee80211_start_queues(rt2x00dev->hw); 1262 ieee80211_wake_queues(rt2x00dev->hw);
1347 1263
1348 /* 1264 /*
1349 * During interface iteration we might have changed the 1265 * During interface iteration we might have changed the
diff --git a/drivers/net/wireless/rt2x00/rt2x00firmware.c b/drivers/net/wireless/rt2x00/rt2x00firmware.c
index b971bc6e7ee2..bab05a56e7a0 100644
--- a/drivers/net/wireless/rt2x00/rt2x00firmware.c
+++ b/drivers/net/wireless/rt2x00/rt2x00firmware.c
@@ -100,6 +100,14 @@ int rt2x00lib_load_firmware(struct rt2x00_dev *rt2x00dev)
100 retval = rt2x00dev->ops->lib->load_firmware(rt2x00dev, 100 retval = rt2x00dev->ops->lib->load_firmware(rt2x00dev,
101 rt2x00dev->fw->data, 101 rt2x00dev->fw->data,
102 rt2x00dev->fw->size); 102 rt2x00dev->fw->size);
103
104 /*
105 * When the firmware is uploaded to the hardware the LED
106 * association status might have been triggered, for correct
107 * LED handling it should now be reset.
108 */
109 rt2x00leds_led_assoc(rt2x00dev, false);
110
103 return retval; 111 return retval;
104} 112}
105 113
diff --git a/drivers/net/wireless/rt2x00/rt2x00lib.h b/drivers/net/wireless/rt2x00/rt2x00lib.h
index 41ee02cd2825..f2c9b0e79b5f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00lib.h
+++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
@@ -26,12 +26,14 @@
26#ifndef RT2X00LIB_H 26#ifndef RT2X00LIB_H
27#define RT2X00LIB_H 27#define RT2X00LIB_H
28 28
29#include "rt2x00dump.h"
30
29/* 31/*
30 * Interval defines 32 * Interval defines
31 * Both the link tuner as the rfkill will be called once per second. 33 * Both the link tuner as the rfkill will be called once per second.
32 */ 34 */
33#define LINK_TUNE_INTERVAL ( round_jiffies_relative(HZ) ) 35#define LINK_TUNE_INTERVAL ( round_jiffies_relative(HZ) )
34#define RFKILL_POLL_INTERVAL ( 1000 ) 36#define RFKILL_POLL_INTERVAL ( round_jiffies_relative(HZ) )
35 37
36/* 38/*
37 * rt2x00_rate: Per rate device information 39 * rt2x00_rate: Per rate device information
@@ -96,9 +98,65 @@ void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev,
96void rt2x00lib_config(struct rt2x00_dev *rt2x00dev, 98void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
97 struct ieee80211_conf *conf, const int force_config); 99 struct ieee80211_conf *conf, const int force_config);
98 100
99/* 101/**
100 * Queue handlers. 102 * DOC: Queue handlers
103 */
104
105/**
106 * rt2x00queue_alloc_rxskb - allocate a skb for RX purposes.
107 * @rt2x00dev: Pointer to &struct rt2x00_dev.
108 * @queue: The queue for which the skb will be applicable.
109 */
110struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
111 struct queue_entry *entry);
112
113/**
114 * rt2x00queue_unmap_skb - Unmap a skb from DMA.
115 * @rt2x00dev: Pointer to &struct rt2x00_dev.
116 * @skb: The skb to unmap.
117 */
118void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb);
119
120/**
121 * rt2x00queue_free_skb - free a skb
122 * @rt2x00dev: Pointer to &struct rt2x00_dev.
123 * @skb: The skb to free.
124 */
125void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb);
126
127/**
128 * rt2x00queue_free_skb - free a skb
129 * @rt2x00dev: Pointer to &struct rt2x00_dev.
130 * @skb: The skb to free.
131 */
132void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb);
133
134/**
135 * rt2x00queue_write_tx_frame - Write TX frame to hardware
136 * @queue: Queue over which the frame should be send
137 * @skb: The skb to send
138 */
139int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb);
140
141/**
142 * rt2x00queue_update_beacon - Send new beacon from mac80211 to hardware
143 * @rt2x00dev: Pointer to &struct rt2x00_dev.
144 * @vif: Interface for which the beacon should be updated.
101 */ 145 */
146int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
147 struct ieee80211_vif *vif);
148
149/**
150 * rt2x00queue_index_inc - Index incrementation function
151 * @queue: Queue (&struct data_queue) to perform the action on.
152 * @index: Index type (&enum queue_index) to perform the action on.
153 *
154 * This function will increase the requested index on the queue,
155 * it will grab the appropriate locks and handle queue overflow events by
156 * resetting the index to the start of the queue.
157 */
158void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index);
159
102void rt2x00queue_init_rx(struct rt2x00_dev *rt2x00dev); 160void rt2x00queue_init_rx(struct rt2x00_dev *rt2x00dev);
103void rt2x00queue_init_tx(struct rt2x00_dev *rt2x00dev); 161void rt2x00queue_init_tx(struct rt2x00_dev *rt2x00dev);
104int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev); 162int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev);
@@ -128,7 +186,8 @@ static inline void rt2x00lib_free_firmware(struct rt2x00_dev *rt2x00dev)
128#ifdef CONFIG_RT2X00_LIB_DEBUGFS 186#ifdef CONFIG_RT2X00_LIB_DEBUGFS
129void rt2x00debug_register(struct rt2x00_dev *rt2x00dev); 187void rt2x00debug_register(struct rt2x00_dev *rt2x00dev);
130void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev); 188void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev);
131void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb); 189void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
190 enum rt2x00_dump_type type, struct sk_buff *skb);
132#else 191#else
133static inline void rt2x00debug_register(struct rt2x00_dev *rt2x00dev) 192static inline void rt2x00debug_register(struct rt2x00_dev *rt2x00dev)
134{ 193{
@@ -139,6 +198,7 @@ static inline void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev)
139} 198}
140 199
141static inline void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev, 200static inline void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
201 enum rt2x00_dump_type type,
142 struct sk_buff *skb) 202 struct sk_buff *skb)
143{ 203{
144} 204}
@@ -152,8 +212,6 @@ void rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev);
152void rt2x00rfkill_unregister(struct rt2x00_dev *rt2x00dev); 212void rt2x00rfkill_unregister(struct rt2x00_dev *rt2x00dev);
153void rt2x00rfkill_allocate(struct rt2x00_dev *rt2x00dev); 213void rt2x00rfkill_allocate(struct rt2x00_dev *rt2x00dev);
154void rt2x00rfkill_free(struct rt2x00_dev *rt2x00dev); 214void rt2x00rfkill_free(struct rt2x00_dev *rt2x00dev);
155void rt2x00rfkill_suspend(struct rt2x00_dev *rt2x00dev);
156void rt2x00rfkill_resume(struct rt2x00_dev *rt2x00dev);
157#else 215#else
158static inline void rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev) 216static inline void rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev)
159{ 217{
@@ -170,14 +228,6 @@ static inline void rt2x00rfkill_allocate(struct rt2x00_dev *rt2x00dev)
170static inline void rt2x00rfkill_free(struct rt2x00_dev *rt2x00dev) 228static inline void rt2x00rfkill_free(struct rt2x00_dev *rt2x00dev)
171{ 229{
172} 230}
173
174static inline void rt2x00rfkill_suspend(struct rt2x00_dev *rt2x00dev)
175{
176}
177
178static inline void rt2x00rfkill_resume(struct rt2x00_dev *rt2x00dev)
179{
180}
181#endif /* CONFIG_RT2X00_LIB_RFKILL */ 231#endif /* CONFIG_RT2X00_LIB_RFKILL */
182 232
183/* 233/*
diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c
index 9cb023edd2e9..f1dcbaa80c3c 100644
--- a/drivers/net/wireless/rt2x00/rt2x00mac.c
+++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
@@ -31,14 +31,14 @@
31 31
32static int rt2x00mac_tx_rts_cts(struct rt2x00_dev *rt2x00dev, 32static int rt2x00mac_tx_rts_cts(struct rt2x00_dev *rt2x00dev,
33 struct data_queue *queue, 33 struct data_queue *queue,
34 struct sk_buff *frag_skb, 34 struct sk_buff *frag_skb)
35 struct ieee80211_tx_control *control)
36{ 35{
37 struct skb_frame_desc *skbdesc; 36 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(frag_skb);
37 struct ieee80211_tx_info *rts_info;
38 struct sk_buff *skb; 38 struct sk_buff *skb;
39 int size; 39 int size;
40 40
41 if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) 41 if (tx_info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT)
42 size = sizeof(struct ieee80211_cts); 42 size = sizeof(struct ieee80211_cts);
43 else 43 else
44 size = sizeof(struct ieee80211_rts); 44 size = sizeof(struct ieee80211_rts);
@@ -52,23 +52,37 @@ static int rt2x00mac_tx_rts_cts(struct rt2x00_dev *rt2x00dev,
52 skb_reserve(skb, rt2x00dev->hw->extra_tx_headroom); 52 skb_reserve(skb, rt2x00dev->hw->extra_tx_headroom);
53 skb_put(skb, size); 53 skb_put(skb, size);
54 54
55 if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) 55 /*
56 ieee80211_ctstoself_get(rt2x00dev->hw, control->vif, 56 * Copy TX information over from original frame to
57 frag_skb->data, frag_skb->len, control, 57 * RTS/CTS frame. Note that we set the no encryption flag
58 * since we don't want this frame to be encrypted.
59 * RTS frames should be acked, while CTS-to-self frames
60 * should not. The ready for TX flag is cleared to prevent
61 * it being automatically send when the descriptor is
62 * written to the hardware.
63 */
64 memcpy(skb->cb, frag_skb->cb, sizeof(skb->cb));
65 rts_info = IEEE80211_SKB_CB(skb);
66 rts_info->flags |= IEEE80211_TX_CTL_DO_NOT_ENCRYPT;
67 rts_info->flags &= ~IEEE80211_TX_CTL_USE_RTS_CTS;
68 rts_info->flags &= ~IEEE80211_TX_CTL_USE_CTS_PROTECT;
69 rts_info->flags &= ~IEEE80211_TX_CTL_REQ_TX_STATUS;
70
71 if (tx_info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT)
72 rts_info->flags |= IEEE80211_TX_CTL_NO_ACK;
73 else
74 rts_info->flags &= ~IEEE80211_TX_CTL_NO_ACK;
75
76 if (tx_info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT)
77 ieee80211_ctstoself_get(rt2x00dev->hw, tx_info->control.vif,
78 frag_skb->data, size, tx_info,
58 (struct ieee80211_cts *)(skb->data)); 79 (struct ieee80211_cts *)(skb->data));
59 else 80 else
60 ieee80211_rts_get(rt2x00dev->hw, control->vif, 81 ieee80211_rts_get(rt2x00dev->hw, tx_info->control.vif,
61 frag_skb->data, frag_skb->len, control, 82 frag_skb->data, size, tx_info,
62 (struct ieee80211_rts *)(skb->data)); 83 (struct ieee80211_rts *)(skb->data));
63 84
64 /* 85 if (rt2x00queue_write_tx_frame(queue, skb)) {
65 * Initialize skb descriptor
66 */
67 skbdesc = get_skb_frame_desc(skb);
68 memset(skbdesc, 0, sizeof(*skbdesc));
69 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
70
71 if (rt2x00dev->ops->lib->write_tx_data(rt2x00dev, queue, skb, control)) {
72 WARNING(rt2x00dev, "Failed to send RTS/CTS frame.\n"); 86 WARNING(rt2x00dev, "Failed to send RTS/CTS frame.\n");
73 return NETDEV_TX_BUSY; 87 return NETDEV_TX_BUSY;
74 } 88 }
@@ -76,13 +90,14 @@ static int rt2x00mac_tx_rts_cts(struct rt2x00_dev *rt2x00dev,
76 return NETDEV_TX_OK; 90 return NETDEV_TX_OK;
77} 91}
78 92
79int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb, 93int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
80 struct ieee80211_tx_control *control)
81{ 94{
82 struct rt2x00_dev *rt2x00dev = hw->priv; 95 struct rt2x00_dev *rt2x00dev = hw->priv;
96 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
83 struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data; 97 struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data;
98 enum data_queue_qid qid = skb_get_queue_mapping(skb);
99 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
84 struct data_queue *queue; 100 struct data_queue *queue;
85 struct skb_frame_desc *skbdesc;
86 u16 frame_control; 101 u16 frame_control;
87 102
88 /* 103 /*
@@ -100,57 +115,62 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
100 /* 115 /*
101 * Determine which queue to put packet on. 116 * Determine which queue to put packet on.
102 */ 117 */
103 if (control->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM && 118 if (tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM &&
104 test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) 119 test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags))
105 queue = rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_ATIM); 120 queue = rt2x00queue_get_queue(rt2x00dev, QID_ATIM);
106 else 121 else
107 queue = rt2x00queue_get_queue(rt2x00dev, control->queue); 122 queue = rt2x00queue_get_queue(rt2x00dev, qid);
108 if (unlikely(!queue)) { 123 if (unlikely(!queue)) {
109 ERROR(rt2x00dev, 124 ERROR(rt2x00dev,
110 "Attempt to send packet over invalid queue %d.\n" 125 "Attempt to send packet over invalid queue %d.\n"
111 "Please file bug report to %s.\n", 126 "Please file bug report to %s.\n", qid, DRV_PROJECT);
112 control->queue, DRV_PROJECT);
113 dev_kfree_skb_any(skb); 127 dev_kfree_skb_any(skb);
114 return NETDEV_TX_OK; 128 return NETDEV_TX_OK;
115 } 129 }
116 130
117 /* 131 /*
118 * If CTS/RTS is required. and this frame is not CTS or RTS, 132 * If CTS/RTS is required. create and queue that frame first.
119 * create and queue that frame first. But make sure we have 133 * Make sure we have at least enough entries available to send
120 * at least enough entries available to send this CTS/RTS 134 * this CTS/RTS frame as well as the data frame.
121 * frame as well as the data frame. 135 * Note that when the driver has set the set_rts_threshold()
136 * callback function it doesn't need software generation of
137 * either RTS or CTS-to-self frame and handles everything
138 * inside the hardware.
122 */ 139 */
123 frame_control = le16_to_cpu(ieee80211hdr->frame_control); 140 frame_control = le16_to_cpu(ieee80211hdr->frame_control);
124 if (!is_rts_frame(frame_control) && !is_cts_frame(frame_control) && 141 if ((tx_info->flags & (IEEE80211_TX_CTL_USE_RTS_CTS |
125 (control->flags & (IEEE80211_TXCTL_USE_RTS_CTS | 142 IEEE80211_TX_CTL_USE_CTS_PROTECT)) &&
126 IEEE80211_TXCTL_USE_CTS_PROTECT))) { 143 !rt2x00dev->ops->hw->set_rts_threshold) {
127 if (rt2x00queue_available(queue) <= 1) { 144 if (rt2x00queue_available(queue) <= 1) {
128 ieee80211_stop_queue(rt2x00dev->hw, control->queue); 145 ieee80211_stop_queue(rt2x00dev->hw, qid);
129 return NETDEV_TX_BUSY; 146 return NETDEV_TX_BUSY;
130 } 147 }
131 148
132 if (rt2x00mac_tx_rts_cts(rt2x00dev, queue, skb, control)) { 149 if (rt2x00mac_tx_rts_cts(rt2x00dev, queue, skb)) {
133 ieee80211_stop_queue(rt2x00dev->hw, control->queue); 150 ieee80211_stop_queue(rt2x00dev->hw, qid);
134 return NETDEV_TX_BUSY; 151 return NETDEV_TX_BUSY;
135 } 152 }
136 } 153 }
137 154
138 /* 155 /*
139 * Initialize skb descriptor 156 * XXX: This is as wrong as the old mac80211 code was,
157 * due to beacons not getting sequence numbers assigned
158 * properly.
140 */ 159 */
141 skbdesc = get_skb_frame_desc(skb); 160 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
142 memset(skbdesc, 0, sizeof(*skbdesc)); 161 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
162 intf->seqno += 0x10;
163 ieee80211hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
164 ieee80211hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
165 }
143 166
144 if (rt2x00dev->ops->lib->write_tx_data(rt2x00dev, queue, skb, control)) { 167 if (rt2x00queue_write_tx_frame(queue, skb)) {
145 ieee80211_stop_queue(rt2x00dev->hw, control->queue); 168 ieee80211_stop_queue(rt2x00dev->hw, qid);
146 return NETDEV_TX_BUSY; 169 return NETDEV_TX_BUSY;
147 } 170 }
148 171
149 if (rt2x00queue_full(queue)) 172 if (rt2x00queue_threshold(queue))
150 ieee80211_stop_queue(rt2x00dev->hw, control->queue); 173 ieee80211_stop_queue(rt2x00dev->hw, qid);
151
152 if (rt2x00dev->ops->lib->kick_tx_queue)
153 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
154 174
155 return NETDEV_TX_OK; 175 return NETDEV_TX_OK;
156} 176}
@@ -183,8 +203,7 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
183{ 203{
184 struct rt2x00_dev *rt2x00dev = hw->priv; 204 struct rt2x00_dev *rt2x00dev = hw->priv;
185 struct rt2x00_intf *intf = vif_to_intf(conf->vif); 205 struct rt2x00_intf *intf = vif_to_intf(conf->vif);
186 struct data_queue *queue = 206 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
187 rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
188 struct queue_entry *entry = NULL; 207 struct queue_entry *entry = NULL;
189 unsigned int i; 208 unsigned int i;
190 209
@@ -197,13 +216,12 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
197 return -ENODEV; 216 return -ENODEV;
198 217
199 /* 218 /*
200 * When we don't support mixed interfaces (a combination 219 * We don't support mixed combinations of sta and ap virtual
201 * of sta and ap virtual interfaces) then we can only 220 * interfaces. We can only add this interface when the rival
202 * add this interface when the rival interface count is 0. 221 * interface count is 0.
203 */ 222 */
204 if (!test_bit(DRIVER_SUPPORT_MIXED_INTERFACES, &rt2x00dev->flags) && 223 if ((conf->type == IEEE80211_IF_TYPE_AP && rt2x00dev->intf_sta_count) ||
205 ((conf->type == IEEE80211_IF_TYPE_AP && rt2x00dev->intf_sta_count) || 224 (conf->type != IEEE80211_IF_TYPE_AP && rt2x00dev->intf_ap_count))
206 (conf->type != IEEE80211_IF_TYPE_AP && rt2x00dev->intf_ap_count)))
207 return -ENOBUFS; 225 return -ENOBUFS;
208 226
209 /* 227 /*
@@ -343,7 +361,8 @@ int rt2x00mac_config_interface(struct ieee80211_hw *hw,
343{ 361{
344 struct rt2x00_dev *rt2x00dev = hw->priv; 362 struct rt2x00_dev *rt2x00dev = hw->priv;
345 struct rt2x00_intf *intf = vif_to_intf(vif); 363 struct rt2x00_intf *intf = vif_to_intf(vif);
346 int status; 364 int update_bssid = 0;
365 int status = 0;
347 366
348 /* 367 /*
349 * Mac80211 might be calling this function while we are trying 368 * Mac80211 might be calling this function while we are trying
@@ -355,12 +374,13 @@ int rt2x00mac_config_interface(struct ieee80211_hw *hw,
355 spin_lock(&intf->lock); 374 spin_lock(&intf->lock);
356 375
357 /* 376 /*
358 * If the interface does not work in master mode, 377 * conf->bssid can be NULL if coming from the internal
359 * then the bssid value in the interface structure 378 * beacon update routine.
360 * should now be set.
361 */ 379 */
362 if (conf->type != IEEE80211_IF_TYPE_AP) 380 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
381 update_bssid = 1;
363 memcpy(&intf->bssid, conf->bssid, ETH_ALEN); 382 memcpy(&intf->bssid, conf->bssid, ETH_ALEN);
383 }
364 384
365 spin_unlock(&intf->lock); 385 spin_unlock(&intf->lock);
366 386
@@ -370,19 +390,14 @@ int rt2x00mac_config_interface(struct ieee80211_hw *hw,
370 * values as arguments we make keep access to rt2x00_intf thread safe 390 * values as arguments we make keep access to rt2x00_intf thread safe
371 * even without the lock. 391 * even without the lock.
372 */ 392 */
373 rt2x00lib_config_intf(rt2x00dev, intf, conf->type, NULL, conf->bssid); 393 rt2x00lib_config_intf(rt2x00dev, intf, vif->type, NULL,
394 update_bssid ? conf->bssid : NULL);
374 395
375 /* 396 /*
376 * We only need to initialize the beacon when master mode is enabled. 397 * Update the beacon.
377 */ 398 */
378 if (conf->type != IEEE80211_IF_TYPE_AP || !conf->beacon) 399 if (conf->changed & IEEE80211_IFCC_BEACON)
379 return 0; 400 status = rt2x00queue_update_beacon(rt2x00dev, vif);
380
381 status = rt2x00dev->ops->hw->beacon_update(rt2x00dev->hw,
382 conf->beacon,
383 conf->beacon_control);
384 if (status)
385 dev_kfree_skb(conf->beacon);
386 401
387 return status; 402 return status;
388} 403}
@@ -428,7 +443,7 @@ void rt2x00mac_configure_filter(struct ieee80211_hw *hw,
428 if (!test_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags)) 443 if (!test_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags))
429 rt2x00dev->ops->lib->config_filter(rt2x00dev, *total_flags); 444 rt2x00dev->ops->lib->config_filter(rt2x00dev, *total_flags);
430 else 445 else
431 queue_work(rt2x00dev->workqueue, &rt2x00dev->filter_work); 446 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
432} 447}
433EXPORT_SYMBOL_GPL(rt2x00mac_configure_filter); 448EXPORT_SYMBOL_GPL(rt2x00mac_configure_filter);
434 449
@@ -454,10 +469,10 @@ int rt2x00mac_get_tx_stats(struct ieee80211_hw *hw,
454 struct rt2x00_dev *rt2x00dev = hw->priv; 469 struct rt2x00_dev *rt2x00dev = hw->priv;
455 unsigned int i; 470 unsigned int i;
456 471
457 for (i = 0; i < hw->queues; i++) { 472 for (i = 0; i < rt2x00dev->ops->tx_queues; i++) {
458 stats->data[i].len = rt2x00dev->tx[i].length; 473 stats[i].len = rt2x00dev->tx[i].length;
459 stats->data[i].limit = rt2x00dev->tx[i].limit; 474 stats[i].limit = rt2x00dev->tx[i].limit;
460 stats->data[i].count = rt2x00dev->tx[i].count; 475 stats[i].count = rt2x00dev->tx[i].count;
461 } 476 }
462 477
463 return 0; 478 return 0;
@@ -498,7 +513,7 @@ void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
498 * When the erp information has changed, we should perform 513 * When the erp information has changed, we should perform
499 * additional configuration steps. For all other changes we are done. 514 * additional configuration steps. For all other changes we are done.
500 */ 515 */
501 if (changes & BSS_CHANGED_ERP_PREAMBLE) { 516 if (changes & (BSS_CHANGED_ERP_PREAMBLE | BSS_CHANGED_ERP_CTS_PROT)) {
502 if (!test_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags)) 517 if (!test_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags))
503 rt2x00lib_config_erp(rt2x00dev, intf, bss_conf); 518 rt2x00lib_config_erp(rt2x00dev, intf, bss_conf);
504 else 519 else
@@ -509,13 +524,13 @@ void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
509 memcpy(&intf->conf, bss_conf, sizeof(*bss_conf)); 524 memcpy(&intf->conf, bss_conf, sizeof(*bss_conf));
510 if (delayed) { 525 if (delayed) {
511 intf->delayed_flags |= delayed; 526 intf->delayed_flags |= delayed;
512 queue_work(rt2x00dev->workqueue, &rt2x00dev->intf_work); 527 schedule_work(&rt2x00dev->intf_work);
513 } 528 }
514 spin_unlock(&intf->lock); 529 spin_unlock(&intf->lock);
515} 530}
516EXPORT_SYMBOL_GPL(rt2x00mac_bss_info_changed); 531EXPORT_SYMBOL_GPL(rt2x00mac_bss_info_changed);
517 532
518int rt2x00mac_conf_tx(struct ieee80211_hw *hw, int queue_idx, 533int rt2x00mac_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
519 const struct ieee80211_tx_queue_params *params) 534 const struct ieee80211_tx_queue_params *params)
520{ 535{
521 struct rt2x00_dev *rt2x00dev = hw->priv; 536 struct rt2x00_dev *rt2x00dev = hw->priv;
@@ -539,10 +554,7 @@ int rt2x00mac_conf_tx(struct ieee80211_hw *hw, int queue_idx,
539 else 554 else
540 queue->cw_max = 10; /* cw_min: 2^10 = 1024. */ 555 queue->cw_max = 10; /* cw_min: 2^10 = 1024. */
541 556
542 if (params->aifs >= 0) 557 queue->aifs = params->aifs;
543 queue->aifs = params->aifs;
544 else
545 queue->aifs = 2;
546 558
547 INFO(rt2x00dev, 559 INFO(rt2x00dev,
548 "Configured TX queue %d - CWmin: %d, CWmax: %d, Aifs: %d.\n", 560 "Configured TX queue %d - CWmin: %d, CWmax: %d, Aifs: %d.\n",
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index 60893de3bf8f..adf2876ed8ab 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -34,44 +34,34 @@
34/* 34/*
35 * TX data handlers. 35 * TX data handlers.
36 */ 36 */
37int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev, 37int rt2x00pci_write_tx_data(struct queue_entry *entry)
38 struct data_queue *queue, struct sk_buff *skb,
39 struct ieee80211_tx_control *control)
40{ 38{
41 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX); 39 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
42 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
43 struct skb_frame_desc *skbdesc; 40 struct skb_frame_desc *skbdesc;
44 u32 word; 41 u32 word;
45 42
46 if (rt2x00queue_full(queue)) 43 rt2x00_desc_read(entry_priv->desc, 0, &word);
47 return -EINVAL;
48
49 rt2x00_desc_read(priv_tx->desc, 0, &word);
50 44
51 if (rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) || 45 /*
52 rt2x00_get_field32(word, TXD_ENTRY_VALID)) { 46 * This should not happen, we already checked the entry
53 ERROR(rt2x00dev, 47 * was ours. When the hardware disagrees there has been
54 "Arrived at non-free entry in the non-full queue %d.\n" 48 * a queue corruption!
49 */
50 if (unlikely(rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) ||
51 rt2x00_get_field32(word, TXD_ENTRY_VALID))) {
52 ERROR(entry->queue->rt2x00dev,
53 "Corrupt queue %d, accessing entry which is not ours.\n"
55 "Please file bug report to %s.\n", 54 "Please file bug report to %s.\n",
56 control->queue, DRV_PROJECT); 55 entry->queue->qid, DRV_PROJECT);
57 return -EINVAL; 56 return -EINVAL;
58 } 57 }
59 58
60 /* 59 /*
61 * Fill in skb descriptor 60 * Fill in skb descriptor
62 */ 61 */
63 skbdesc = get_skb_frame_desc(skb); 62 skbdesc = get_skb_frame_desc(entry->skb);
64 skbdesc->data = skb->data; 63 skbdesc->desc = entry_priv->desc;
65 skbdesc->data_len = skb->len; 64 skbdesc->desc_len = entry->queue->desc_size;
66 skbdesc->desc = priv_tx->desc;
67 skbdesc->desc_len = queue->desc_size;
68 skbdesc->entry = entry;
69
70 memcpy(&priv_tx->control, control, sizeof(priv_tx->control));
71 memcpy(priv_tx->data, skb->data, skb->len);
72 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
73
74 rt2x00queue_index_inc(queue, Q_INDEX);
75 65
76 return 0; 66 return 0;
77} 67}
@@ -84,180 +74,62 @@ void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
84{ 74{
85 struct data_queue *queue = rt2x00dev->rx; 75 struct data_queue *queue = rt2x00dev->rx;
86 struct queue_entry *entry; 76 struct queue_entry *entry;
87 struct queue_entry_priv_pci_rx *priv_rx; 77 struct queue_entry_priv_pci *entry_priv;
88 struct ieee80211_hdr *hdr;
89 struct skb_frame_desc *skbdesc; 78 struct skb_frame_desc *skbdesc;
90 struct rxdone_entry_desc rxdesc;
91 int header_size;
92 int align;
93 u32 word; 79 u32 word;
94 80
95 while (1) { 81 while (1) {
96 entry = rt2x00queue_get_entry(queue, Q_INDEX); 82 entry = rt2x00queue_get_entry(queue, Q_INDEX);
97 priv_rx = entry->priv_data; 83 entry_priv = entry->priv_data;
98 rt2x00_desc_read(priv_rx->desc, 0, &word); 84 rt2x00_desc_read(entry_priv->desc, 0, &word);
99 85
100 if (rt2x00_get_field32(word, RXD_ENTRY_OWNER_NIC)) 86 if (rt2x00_get_field32(word, RXD_ENTRY_OWNER_NIC))
101 break; 87 break;
102 88
103 memset(&rxdesc, 0, sizeof(rxdesc));
104 rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
105
106 hdr = (struct ieee80211_hdr *)priv_rx->data;
107 header_size =
108 ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control));
109
110 /* 89 /*
111 * The data behind the ieee80211 header must be 90 * Fill in desc fields of the skb descriptor
112 * aligned on a 4 byte boundary.
113 */
114 align = header_size % 4;
115
116 /*
117 * Allocate the sk_buffer, initialize it and copy
118 * all data into it.
119 */
120 entry->skb = dev_alloc_skb(rxdesc.size + align);
121 if (!entry->skb)
122 return;
123
124 skb_reserve(entry->skb, align);
125 memcpy(skb_put(entry->skb, rxdesc.size),
126 priv_rx->data, rxdesc.size);
127
128 /*
129 * Fill in skb descriptor
130 */ 91 */
131 skbdesc = get_skb_frame_desc(entry->skb); 92 skbdesc = get_skb_frame_desc(entry->skb);
132 memset(skbdesc, 0, sizeof(*skbdesc)); 93 skbdesc->desc = entry_priv->desc;
133 skbdesc->data = entry->skb->data; 94 skbdesc->desc_len = entry->queue->desc_size;
134 skbdesc->data_len = entry->skb->len;
135 skbdesc->desc = priv_rx->desc;
136 skbdesc->desc_len = queue->desc_size;
137 skbdesc->entry = entry;
138 95
139 /* 96 /*
140 * Send the frame to rt2x00lib for further processing. 97 * Send the frame to rt2x00lib for further processing.
141 */ 98 */
142 rt2x00lib_rxdone(entry, &rxdesc); 99 rt2x00lib_rxdone(rt2x00dev, entry);
143
144 if (test_bit(DEVICE_ENABLED_RADIO, &queue->rt2x00dev->flags)) {
145 rt2x00_set_field32(&word, RXD_ENTRY_OWNER_NIC, 1);
146 rt2x00_desc_write(priv_rx->desc, 0, word);
147 }
148
149 rt2x00queue_index_inc(queue, Q_INDEX);
150 } 100 }
151} 101}
152EXPORT_SYMBOL_GPL(rt2x00pci_rxdone); 102EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
153 103
154void rt2x00pci_txdone(struct rt2x00_dev *rt2x00dev, struct queue_entry *entry,
155 struct txdone_entry_desc *txdesc)
156{
157 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
158 u32 word;
159
160 txdesc->control = &priv_tx->control;
161 rt2x00lib_txdone(entry, txdesc);
162
163 /*
164 * Make this entry available for reuse.
165 */
166 entry->flags = 0;
167
168 rt2x00_desc_read(priv_tx->desc, 0, &word);
169 rt2x00_set_field32(&word, TXD_ENTRY_OWNER_NIC, 0);
170 rt2x00_set_field32(&word, TXD_ENTRY_VALID, 0);
171 rt2x00_desc_write(priv_tx->desc, 0, word);
172
173 rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);
174
175 /*
176 * If the data queue was full before the txdone handler
177 * we must make sure the packet queue in the mac80211 stack
178 * is reenabled when the txdone handler has finished.
179 */
180 if (!rt2x00queue_full(entry->queue))
181 ieee80211_wake_queue(rt2x00dev->hw, priv_tx->control.queue);
182
183}
184EXPORT_SYMBOL_GPL(rt2x00pci_txdone);
185
186/* 104/*
187 * Device initialization handlers. 105 * Device initialization handlers.
188 */ 106 */
189#define desc_size(__queue) \
190({ \
191 ((__queue)->limit * (__queue)->desc_size);\
192})
193
194#define data_size(__queue) \
195({ \
196 ((__queue)->limit * (__queue)->data_size);\
197})
198
199#define dma_size(__queue) \
200({ \
201 data_size(__queue) + desc_size(__queue);\
202})
203
204#define desc_offset(__queue, __base, __i) \
205({ \
206 (__base) + data_size(__queue) + \
207 ((__i) * (__queue)->desc_size); \
208})
209
210#define data_offset(__queue, __base, __i) \
211({ \
212 (__base) + \
213 ((__i) * (__queue)->data_size); \
214})
215
216static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev, 107static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
217 struct data_queue *queue) 108 struct data_queue *queue)
218{ 109{
219 struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev); 110 struct queue_entry_priv_pci *entry_priv;
220 struct queue_entry_priv_pci_rx *priv_rx;
221 struct queue_entry_priv_pci_tx *priv_tx;
222 void *addr; 111 void *addr;
223 dma_addr_t dma; 112 dma_addr_t dma;
224 void *desc_addr;
225 dma_addr_t desc_dma;
226 void *data_addr;
227 dma_addr_t data_dma;
228 unsigned int i; 113 unsigned int i;
229 114
230 /* 115 /*
231 * Allocate DMA memory for descriptor and buffer. 116 * Allocate DMA memory for descriptor and buffer.
232 */ 117 */
233 addr = pci_alloc_consistent(pci_dev, dma_size(queue), &dma); 118 addr = dma_alloc_coherent(rt2x00dev->dev,
119 queue->limit * queue->desc_size,
120 &dma, GFP_KERNEL | GFP_DMA);
234 if (!addr) 121 if (!addr)
235 return -ENOMEM; 122 return -ENOMEM;
236 123
237 memset(addr, 0, dma_size(queue)); 124 memset(addr, 0, queue->limit * queue->desc_size);
238 125
239 /* 126 /*
240 * Initialize all queue entries to contain valid addresses. 127 * Initialize all queue entries to contain valid addresses.
241 */ 128 */
242 for (i = 0; i < queue->limit; i++) { 129 for (i = 0; i < queue->limit; i++) {
243 desc_addr = desc_offset(queue, addr, i); 130 entry_priv = queue->entries[i].priv_data;
244 desc_dma = desc_offset(queue, dma, i); 131 entry_priv->desc = addr + i * queue->desc_size;
245 data_addr = data_offset(queue, addr, i); 132 entry_priv->desc_dma = dma + i * queue->desc_size;
246 data_dma = data_offset(queue, dma, i);
247
248 if (queue->qid == QID_RX) {
249 priv_rx = queue->entries[i].priv_data;
250 priv_rx->desc = desc_addr;
251 priv_rx->desc_dma = desc_dma;
252 priv_rx->data = data_addr;
253 priv_rx->data_dma = data_dma;
254 } else {
255 priv_tx = queue->entries[i].priv_data;
256 priv_tx->desc = desc_addr;
257 priv_tx->desc_dma = desc_dma;
258 priv_tx->data = data_addr;
259 priv_tx->data_dma = data_dma;
260 }
261 } 133 }
262 134
263 return 0; 135 return 0;
@@ -266,34 +138,19 @@ static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
266static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev, 138static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
267 struct data_queue *queue) 139 struct data_queue *queue)
268{ 140{
269 struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev); 141 struct queue_entry_priv_pci *entry_priv =
270 struct queue_entry_priv_pci_rx *priv_rx; 142 queue->entries[0].priv_data;
271 struct queue_entry_priv_pci_tx *priv_tx; 143
272 void *data_addr; 144 if (entry_priv->desc)
273 dma_addr_t data_dma; 145 dma_free_coherent(rt2x00dev->dev,
274 146 queue->limit * queue->desc_size,
275 if (queue->qid == QID_RX) { 147 entry_priv->desc, entry_priv->desc_dma);
276 priv_rx = queue->entries[0].priv_data; 148 entry_priv->desc = NULL;
277 data_addr = priv_rx->data;
278 data_dma = priv_rx->data_dma;
279
280 priv_rx->data = NULL;
281 } else {
282 priv_tx = queue->entries[0].priv_data;
283 data_addr = priv_tx->data;
284 data_dma = priv_tx->data_dma;
285
286 priv_tx->data = NULL;
287 }
288
289 if (data_addr)
290 pci_free_consistent(pci_dev, dma_size(queue),
291 data_addr, data_dma);
292} 149}
293 150
294int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev) 151int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
295{ 152{
296 struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev); 153 struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);
297 struct data_queue *queue; 154 struct data_queue *queue;
298 int status; 155 int status;
299 156
@@ -334,7 +191,7 @@ void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
334 /* 191 /*
335 * Free irq line. 192 * Free irq line.
336 */ 193 */
337 free_irq(rt2x00dev_pci(rt2x00dev)->irq, rt2x00dev); 194 free_irq(to_pci_dev(rt2x00dev->dev)->irq, rt2x00dev);
338 195
339 /* 196 /*
340 * Free DMA 197 * Free DMA
@@ -363,7 +220,7 @@ static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
363 220
364static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev) 221static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
365{ 222{
366 struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev); 223 struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);
367 224
368 rt2x00dev->csr.base = ioremap(pci_resource_start(pci_dev, 0), 225 rt2x00dev->csr.base = ioremap(pci_resource_start(pci_dev, 0),
369 pci_resource_len(pci_dev, 0)); 226 pci_resource_len(pci_dev, 0));
@@ -412,7 +269,7 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
412 if (pci_set_mwi(pci_dev)) 269 if (pci_set_mwi(pci_dev))
413 ERROR_PROBE("MWI not available.\n"); 270 ERROR_PROBE("MWI not available.\n");
414 271
415 if (pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) { 272 if (dma_set_mask(&pci_dev->dev, DMA_32BIT_MASK)) {
416 ERROR_PROBE("PCI DMA not supported.\n"); 273 ERROR_PROBE("PCI DMA not supported.\n");
417 retval = -EIO; 274 retval = -EIO;
418 goto exit_disable_device; 275 goto exit_disable_device;
@@ -428,7 +285,7 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
428 pci_set_drvdata(pci_dev, hw); 285 pci_set_drvdata(pci_dev, hw);
429 286
430 rt2x00dev = hw->priv; 287 rt2x00dev = hw->priv;
431 rt2x00dev->dev = pci_dev; 288 rt2x00dev->dev = &pci_dev->dev;
432 rt2x00dev->ops = ops; 289 rt2x00dev->ops = ops;
433 rt2x00dev->hw = hw; 290 rt2x00dev->hw = hw;
434 291
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.h b/drivers/net/wireless/rt2x00/rt2x00pci.h
index b41967ecbf6d..80bf97c03e2d 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.h
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.h
@@ -87,44 +87,26 @@ rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev,
87 memcpy_toio(rt2x00dev->csr.base + offset, value, length); 87 memcpy_toio(rt2x00dev->csr.base + offset, value, length);
88} 88}
89 89
90/*
91 * TX data handlers.
92 */
93int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
94 struct data_queue *queue, struct sk_buff *skb,
95 struct ieee80211_tx_control *control);
96
97/** 90/**
98 * struct queue_entry_priv_pci_rx: Per RX entry PCI specific information 91 * rt2x00pci_write_tx_data - Initialize data for TX operation
92 * @entry: The entry where the frame is located
99 * 93 *
100 * @desc: Pointer to device descriptor. 94 * This function will initialize the DMA and skb descriptor
101 * @data: Pointer to device's entry memory. 95 * to prepare the entry for the actual TX operation.
102 * @dma: DMA pointer to &data.
103 */ 96 */
104struct queue_entry_priv_pci_rx { 97int rt2x00pci_write_tx_data(struct queue_entry *entry);
105 __le32 *desc;
106 dma_addr_t desc_dma;
107
108 void *data;
109 dma_addr_t data_dma;
110};
111 98
112/** 99/**
113 * struct queue_entry_priv_pci_tx: Per TX entry PCI specific information 100 * struct queue_entry_priv_pci: Per entry PCI specific information
114 * 101 *
115 * @desc: Pointer to device descriptor 102 * @desc: Pointer to device descriptor
103 * @desc_dma: DMA pointer to &desc.
116 * @data: Pointer to device's entry memory. 104 * @data: Pointer to device's entry memory.
117 * @dma: DMA pointer to &data. 105 * @data_dma: DMA pointer to &data.
118 * @control: mac80211 control structure used to transmit data.
119 */ 106 */
120struct queue_entry_priv_pci_tx { 107struct queue_entry_priv_pci {
121 __le32 *desc; 108 __le32 *desc;
122 dma_addr_t desc_dma; 109 dma_addr_t desc_dma;
123
124 void *data;
125 dma_addr_t data_dma;
126
127 struct ieee80211_tx_control control;
128}; 110};
129 111
130/** 112/**
@@ -133,15 +115,6 @@ struct queue_entry_priv_pci_tx {
133 */ 115 */
134void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev); 116void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev);
135 117
136/**
137 * rt2x00pci_txdone - Handle TX done events
138 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
139 * @entry: Entry which has completed the transmission of a frame.
140 * @desc: TX done descriptor
141 */
142void rt2x00pci_txdone(struct rt2x00_dev *rt2x00dev, struct queue_entry *entry,
143 struct txdone_entry_desc *desc);
144
145/* 118/*
146 * Device initialization handlers. 119 * Device initialization handlers.
147 */ 120 */
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c
index 659e9f44c40c..7f442030f5ad 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.c
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
@@ -25,24 +25,370 @@
25 25
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/dma-mapping.h>
28 29
29#include "rt2x00.h" 30#include "rt2x00.h"
30#include "rt2x00lib.h" 31#include "rt2x00lib.h"
31 32
33struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
34 struct queue_entry *entry)
35{
36 unsigned int frame_size;
37 unsigned int reserved_size;
38 struct sk_buff *skb;
39 struct skb_frame_desc *skbdesc;
40
41 /*
42 * The frame size includes descriptor size, because the
43 * hardware directly receive the frame into the skbuffer.
44 */
45 frame_size = entry->queue->data_size + entry->queue->desc_size;
46
47 /*
48 * The payload should be aligned to a 4-byte boundary,
49 * this means we need at least 3 bytes for moving the frame
50 * into the correct offset.
51 */
52 reserved_size = 4;
53
54 /*
55 * Allocate skbuffer.
56 */
57 skb = dev_alloc_skb(frame_size + reserved_size);
58 if (!skb)
59 return NULL;
60
61 skb_reserve(skb, reserved_size);
62 skb_put(skb, frame_size);
63
64 /*
65 * Populate skbdesc.
66 */
67 skbdesc = get_skb_frame_desc(skb);
68 memset(skbdesc, 0, sizeof(*skbdesc));
69 skbdesc->entry = entry;
70
71 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
72 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
73 skb->data,
74 skb->len,
75 DMA_FROM_DEVICE);
76 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
77 }
78
79 return skb;
80}
81
82void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
83{
84 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
85
86 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev, skb->data, skb->len,
87 DMA_TO_DEVICE);
88 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
89}
90EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
91
92void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
93{
94 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
95
96 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
97 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
98 DMA_FROM_DEVICE);
99 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
100 }
101
102 if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
103 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
104 DMA_TO_DEVICE);
105 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
106 }
107}
108
109void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
110{
111 if (!skb)
112 return;
113
114 rt2x00queue_unmap_skb(rt2x00dev, skb);
115 dev_kfree_skb_any(skb);
116}
117
118static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
119 struct txentry_desc *txdesc)
120{
121 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
122 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
123 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
124 struct ieee80211_rate *rate =
125 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
126 const struct rt2x00_rate *hwrate;
127 unsigned int data_length;
128 unsigned int duration;
129 unsigned int residual;
130
131 memset(txdesc, 0, sizeof(*txdesc));
132
133 /*
134 * Initialize information from queue
135 */
136 txdesc->queue = entry->queue->qid;
137 txdesc->cw_min = entry->queue->cw_min;
138 txdesc->cw_max = entry->queue->cw_max;
139 txdesc->aifs = entry->queue->aifs;
140
141 /* Data length should be extended with 4 bytes for CRC */
142 data_length = entry->skb->len + 4;
143
144 /*
145 * Check whether this frame is to be acked.
146 */
147 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
148 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
149
150 /*
151 * Check if this is a RTS/CTS frame
152 */
153 if (ieee80211_is_rts(hdr->frame_control) ||
154 ieee80211_is_cts(hdr->frame_control)) {
155 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
156 if (ieee80211_is_rts(hdr->frame_control))
157 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
158 else
159 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
160 if (tx_info->control.rts_cts_rate_idx >= 0)
161 rate =
162 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
163 }
164
165 /*
166 * Determine retry information.
167 */
168 txdesc->retry_limit = tx_info->control.retry_limit;
169 if (tx_info->flags & IEEE80211_TX_CTL_LONG_RETRY_LIMIT)
170 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
171
172 /*
173 * Check if more fragments are pending
174 */
175 if (ieee80211_has_morefrags(hdr->frame_control)) {
176 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
177 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
178 }
179
180 /*
181 * Beacons and probe responses require the tsf timestamp
182 * to be inserted into the frame.
183 */
184 if (ieee80211_is_beacon(hdr->frame_control) ||
185 ieee80211_is_probe_resp(hdr->frame_control))
186 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
187
188 /*
189 * Determine with what IFS priority this frame should be send.
190 * Set ifs to IFS_SIFS when the this is not the first fragment,
191 * or this fragment came after RTS/CTS.
192 */
193 if (test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
194 txdesc->ifs = IFS_SIFS;
195 } else if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) {
196 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
197 txdesc->ifs = IFS_BACKOFF;
198 } else {
199 txdesc->ifs = IFS_SIFS;
200 }
201
202 /*
203 * PLCP setup
204 * Length calculation depends on OFDM/CCK rate.
205 */
206 hwrate = rt2x00_get_rate(rate->hw_value);
207 txdesc->signal = hwrate->plcp;
208 txdesc->service = 0x04;
209
210 if (hwrate->flags & DEV_RATE_OFDM) {
211 __set_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags);
212
213 txdesc->length_high = (data_length >> 6) & 0x3f;
214 txdesc->length_low = data_length & 0x3f;
215 } else {
216 /*
217 * Convert length to microseconds.
218 */
219 residual = get_duration_res(data_length, hwrate->bitrate);
220 duration = get_duration(data_length, hwrate->bitrate);
221
222 if (residual != 0) {
223 duration++;
224
225 /*
226 * Check if we need to set the Length Extension
227 */
228 if (hwrate->bitrate == 110 && residual <= 30)
229 txdesc->service |= 0x80;
230 }
231
232 txdesc->length_high = (duration >> 8) & 0xff;
233 txdesc->length_low = duration & 0xff;
234
235 /*
236 * When preamble is enabled we should set the
237 * preamble bit for the signal.
238 */
239 if (rt2x00_get_rate_preamble(rate->hw_value))
240 txdesc->signal |= 0x08;
241 }
242}
243
244static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
245 struct txentry_desc *txdesc)
246{
247 struct data_queue *queue = entry->queue;
248 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
249
250 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
251
252 /*
253 * All processing on the frame has been completed, this means
254 * it is now ready to be dumped to userspace through debugfs.
255 */
256 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
257
258 /*
259 * Check if we need to kick the queue, there are however a few rules
260 * 1) Don't kick beacon queue
261 * 2) Don't kick unless this is the last in frame in a burst.
262 * When the burst flag is set, this frame is always followed
263 * by another frame which in some way are related to eachother.
264 * This is true for fragments, RTS or CTS-to-self frames.
265 * 3) Rule 2 can be broken when the available entries
266 * in the queue are less then a certain threshold.
267 */
268 if (entry->queue->qid == QID_BEACON)
269 return;
270
271 if (rt2x00queue_threshold(queue) ||
272 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
273 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
274}
275
276int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
277{
278 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
279 struct txentry_desc txdesc;
280 struct skb_frame_desc *skbdesc;
281
282 if (unlikely(rt2x00queue_full(queue)))
283 return -EINVAL;
284
285 if (__test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
286 ERROR(queue->rt2x00dev,
287 "Arrived at non-free entry in the non-full queue %d.\n"
288 "Please file bug report to %s.\n",
289 queue->qid, DRV_PROJECT);
290 return -EINVAL;
291 }
292
293 /*
294 * Copy all TX descriptor information into txdesc,
295 * after that we are free to use the skb->cb array
296 * for our information.
297 */
298 entry->skb = skb;
299 rt2x00queue_create_tx_descriptor(entry, &txdesc);
300
301 /*
302 * skb->cb array is now ours and we are free to use it.
303 */
304 skbdesc = get_skb_frame_desc(entry->skb);
305 memset(skbdesc, 0, sizeof(*skbdesc));
306 skbdesc->entry = entry;
307
308 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
309 __clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
310 return -EIO;
311 }
312
313 if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
314 rt2x00queue_map_txskb(queue->rt2x00dev, skb);
315
316 __set_bit(ENTRY_DATA_PENDING, &entry->flags);
317
318 rt2x00queue_index_inc(queue, Q_INDEX);
319 rt2x00queue_write_tx_descriptor(entry, &txdesc);
320
321 return 0;
322}
323
324int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
325 struct ieee80211_vif *vif)
326{
327 struct rt2x00_intf *intf = vif_to_intf(vif);
328 struct skb_frame_desc *skbdesc;
329 struct txentry_desc txdesc;
330 __le32 desc[16];
331
332 if (unlikely(!intf->beacon))
333 return -ENOBUFS;
334
335 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
336 if (!intf->beacon->skb)
337 return -ENOMEM;
338
339 /*
340 * Copy all TX descriptor information into txdesc,
341 * after that we are free to use the skb->cb array
342 * for our information.
343 */
344 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
345
346 /*
347 * For the descriptor we use a local array from where the
348 * driver can move it to the correct location required for
349 * the hardware.
350 */
351 memset(desc, 0, sizeof(desc));
352
353 /*
354 * Fill in skb descriptor
355 */
356 skbdesc = get_skb_frame_desc(intf->beacon->skb);
357 memset(skbdesc, 0, sizeof(*skbdesc));
358 skbdesc->desc = desc;
359 skbdesc->desc_len = intf->beacon->queue->desc_size;
360 skbdesc->entry = intf->beacon;
361
362 /*
363 * Write TX descriptor into reserved room in front of the beacon.
364 */
365 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
366
367 /*
368 * Send beacon to hardware.
369 * Also enable beacon generation, which might have been disabled
370 * by the driver during the config_beacon() callback function.
371 */
372 rt2x00dev->ops->lib->write_beacon(intf->beacon);
373 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
374
375 return 0;
376}
377
32struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev, 378struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
33 const unsigned int queue) 379 const enum data_queue_qid queue)
34{ 380{
35 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 381 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
36 382
37 if (queue < rt2x00dev->hw->queues && rt2x00dev->tx) 383 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
38 return &rt2x00dev->tx[queue]; 384 return &rt2x00dev->tx[queue];
39 385
40 if (!rt2x00dev->bcn) 386 if (!rt2x00dev->bcn)
41 return NULL; 387 return NULL;
42 388
43 if (queue == RT2X00_BCN_QUEUE_BEACON) 389 if (queue == QID_BEACON)
44 return &rt2x00dev->bcn[0]; 390 return &rt2x00dev->bcn[0];
45 else if (queue == RT2X00_BCN_QUEUE_ATIM && atim) 391 else if (queue == QID_ATIM && atim)
46 return &rt2x00dev->bcn[1]; 392 return &rt2x00dev->bcn[1];
47 393
48 return NULL; 394 return NULL;
@@ -96,7 +442,6 @@ void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
96 442
97 spin_unlock_irqrestore(&queue->lock, irqflags); 443 spin_unlock_irqrestore(&queue->lock, irqflags);
98} 444}
99EXPORT_SYMBOL_GPL(rt2x00queue_index_inc);
100 445
101static void rt2x00queue_reset(struct data_queue *queue) 446static void rt2x00queue_reset(struct data_queue *queue)
102{ 447{
@@ -153,6 +498,7 @@ static int rt2x00queue_alloc_entries(struct data_queue *queue,
153 rt2x00queue_reset(queue); 498 rt2x00queue_reset(queue);
154 499
155 queue->limit = qdesc->entry_num; 500 queue->limit = qdesc->entry_num;
501 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
156 queue->data_size = qdesc->data_size; 502 queue->data_size = qdesc->data_size;
157 queue->desc_size = qdesc->desc_size; 503 queue->desc_size = qdesc->desc_size;
158 504
@@ -185,12 +531,41 @@ static int rt2x00queue_alloc_entries(struct data_queue *queue,
185 return 0; 531 return 0;
186} 532}
187 533
534static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
535 struct data_queue *queue)
536{
537 unsigned int i;
538
539 if (!queue->entries)
540 return;
541
542 for (i = 0; i < queue->limit; i++) {
543 if (queue->entries[i].skb)
544 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
545 }
546}
547
548static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
549 struct data_queue *queue)
550{
551 unsigned int i;
552 struct sk_buff *skb;
553
554 for (i = 0; i < queue->limit; i++) {
555 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
556 if (!skb)
557 return -ENOMEM;
558 queue->entries[i].skb = skb;
559 }
560
561 return 0;
562}
563
188int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev) 564int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
189{ 565{
190 struct data_queue *queue; 566 struct data_queue *queue;
191 int status; 567 int status;
192 568
193
194 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx); 569 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
195 if (status) 570 if (status)
196 goto exit; 571 goto exit;
@@ -205,11 +580,14 @@ int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
205 if (status) 580 if (status)
206 goto exit; 581 goto exit;
207 582
208 if (!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) 583 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
209 return 0; 584 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
585 rt2x00dev->ops->atim);
586 if (status)
587 goto exit;
588 }
210 589
211 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1], 590 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
212 rt2x00dev->ops->atim);
213 if (status) 591 if (status)
214 goto exit; 592 goto exit;
215 593
@@ -227,6 +605,8 @@ void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
227{ 605{
228 struct data_queue *queue; 606 struct data_queue *queue;
229 607
608 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
609
230 queue_for_each(rt2x00dev, queue) { 610 queue_for_each(rt2x00dev, queue) {
231 kfree(queue->entries); 611 kfree(queue->entries);
232 queue->entries = NULL; 612 queue->entries = NULL;
@@ -255,11 +635,11 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
255 /* 635 /*
256 * We need the following queues: 636 * We need the following queues:
257 * RX: 1 637 * RX: 1
258 * TX: hw->queues 638 * TX: ops->tx_queues
259 * Beacon: 1 639 * Beacon: 1
260 * Atim: 1 (if required) 640 * Atim: 1 (if required)
261 */ 641 */
262 rt2x00dev->data_queues = 2 + rt2x00dev->hw->queues + req_atim; 642 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
263 643
264 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL); 644 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
265 if (!queue) { 645 if (!queue) {
@@ -272,7 +652,7 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
272 */ 652 */
273 rt2x00dev->rx = queue; 653 rt2x00dev->rx = queue;
274 rt2x00dev->tx = &queue[1]; 654 rt2x00dev->tx = &queue[1];
275 rt2x00dev->bcn = &queue[1 + rt2x00dev->hw->queues]; 655 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
276 656
277 /* 657 /*
278 * Initialize queue parameters. 658 * Initialize queue parameters.
@@ -280,7 +660,8 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
280 * TX: qid = QID_AC_BE + index 660 * TX: qid = QID_AC_BE + index
281 * TX: cw_min: 2^5 = 32. 661 * TX: cw_min: 2^5 = 32.
282 * TX: cw_max: 2^10 = 1024. 662 * TX: cw_max: 2^10 = 1024.
283 * BCN & Atim: qid = QID_MGMT 663 * BCN: qid = QID_BEACON
664 * ATIM: qid = QID_ATIM
284 */ 665 */
285 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX); 666 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
286 667
@@ -288,9 +669,9 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
288 tx_queue_for_each(rt2x00dev, queue) 669 tx_queue_for_each(rt2x00dev, queue)
289 rt2x00queue_init(rt2x00dev, queue, qid++); 670 rt2x00queue_init(rt2x00dev, queue, qid++);
290 671
291 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_MGMT); 672 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
292 if (req_atim) 673 if (req_atim)
293 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_MGMT); 674 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
294 675
295 return 0; 676 return 0;
296} 677}
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h
index 7027c9f47d3f..8945945c892e 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.h
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
@@ -42,18 +42,32 @@
42/** 42/**
43 * DOC: Number of entries per queue 43 * DOC: Number of entries per queue
44 * 44 *
45 * After research it was concluded that 12 entries in a RX and TX 45 * Under normal load without fragmentation 12 entries are sufficient
46 * queue would be sufficient. Although this is almost one third of 46 * without the queue being filled up to the maximum. When using fragmentation
47 * the amount the legacy driver allocated, the queues aren't getting 47 * and the queue threshold code we need to add some additional margins to
48 * filled to the maximum even when working with the maximum rate. 48 * make sure the queue will never (or only under extreme load) fill up
49 * completely.
50 * Since we don't use preallocated DMA having a large number of queue entries
51 * will have only minimal impact on the memory requirements for the queue.
49 */ 52 */
50#define RX_ENTRIES 12 53#define RX_ENTRIES 24
51#define TX_ENTRIES 12 54#define TX_ENTRIES 24
52#define BEACON_ENTRIES 1 55#define BEACON_ENTRIES 1
53#define ATIM_ENTRIES 1 56#define ATIM_ENTRIES 8
54 57
55/** 58/**
56 * enum data_queue_qid: Queue identification 59 * enum data_queue_qid: Queue identification
60 *
61 * @QID_AC_BE: AC BE queue
62 * @QID_AC_BK: AC BK queue
63 * @QID_AC_VI: AC VI queue
64 * @QID_AC_VO: AC VO queue
65 * @QID_HCCA: HCCA queue
66 * @QID_MGMT: MGMT queue (prio queue)
67 * @QID_RX: RX queue
68 * @QID_OTHER: None of the above (don't use, only present for completeness)
69 * @QID_BEACON: Beacon queue (value unspecified, don't send it to device)
70 * @QID_ATIM: Atim queue (value unspeficied, don't send it to device)
57 */ 71 */
58enum data_queue_qid { 72enum data_queue_qid {
59 QID_AC_BE = 0, 73 QID_AC_BE = 0,
@@ -64,68 +78,55 @@ enum data_queue_qid {
64 QID_MGMT = 13, 78 QID_MGMT = 13,
65 QID_RX = 14, 79 QID_RX = 14,
66 QID_OTHER = 15, 80 QID_OTHER = 15,
67}; 81 QID_BEACON,
68 82 QID_ATIM,
69/**
70 * enum rt2x00_bcn_queue: Beacon queue index
71 *
72 * Start counting with a high offset, this because this enumeration
73 * supplements &enum ieee80211_tx_queue and we should prevent value
74 * conflicts.
75 *
76 * @RT2X00_BCN_QUEUE_BEACON: Beacon queue
77 * @RT2X00_BCN_QUEUE_ATIM: Atim queue (sends frame after beacon)
78 */
79enum rt2x00_bcn_queue {
80 RT2X00_BCN_QUEUE_BEACON = 100,
81 RT2X00_BCN_QUEUE_ATIM = 101,
82}; 83};
83 84
84/** 85/**
85 * enum skb_frame_desc_flags: Flags for &struct skb_frame_desc 86 * enum skb_frame_desc_flags: Flags for &struct skb_frame_desc
86 * 87 *
87 * @FRAME_DESC_DRIVER_GENERATED: Frame was generated inside driver 88 * @SKBDESC_DMA_MAPPED_RX: &skb_dma field has been mapped for RX
88 * and should not be reported back to mac80211 during txdone. 89 * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX
89 */ 90 */
90enum skb_frame_desc_flags { 91enum skb_frame_desc_flags {
91 FRAME_DESC_DRIVER_GENERATED = 1 << 0, 92 SKBDESC_DMA_MAPPED_RX = (1 << 0),
93 SKBDESC_DMA_MAPPED_TX = (1 << 1),
92}; 94};
93 95
94/** 96/**
95 * struct skb_frame_desc: Descriptor information for the skb buffer 97 * struct skb_frame_desc: Descriptor information for the skb buffer
96 * 98 *
97 * This structure is placed over the skb->cb array, this means that 99 * This structure is placed over the driver_data array, this means that
98 * this structure should not exceed the size of that array (48 bytes). 100 * this structure should not exceed the size of that array (40 bytes).
99 * 101 *
100 * @flags: Frame flags, see &enum skb_frame_desc_flags. 102 * @flags: Frame flags, see &enum skb_frame_desc_flags.
101 * @frame_type: Frame type, see &enum rt2x00_dump_type. 103 * @desc_len: Length of the frame descriptor.
102 * @data: Pointer to data part of frame (Start of ieee80211 header).
103 * @desc: Pointer to descriptor part of the frame. 104 * @desc: Pointer to descriptor part of the frame.
104 * Note that this pointer could point to something outside 105 * Note that this pointer could point to something outside
105 * of the scope of the skb->data pointer. 106 * of the scope of the skb->data pointer.
106 * @data_len: Length of the frame data. 107 * @skb_dma: (PCI-only) the DMA address associated with the sk buffer.
107 * @desc_len: Length of the frame descriptor.
108
109 * @entry: The entry to which this sk buffer belongs. 108 * @entry: The entry to which this sk buffer belongs.
110 */ 109 */
111struct skb_frame_desc { 110struct skb_frame_desc {
112 unsigned int flags; 111 unsigned int flags;
113 112
114 unsigned int frame_type; 113 unsigned int desc_len;
115
116 void *data;
117 void *desc; 114 void *desc;
118 115
119 unsigned int data_len; 116 dma_addr_t skb_dma;
120 unsigned int desc_len;
121 117
122 struct queue_entry *entry; 118 struct queue_entry *entry;
123}; 119};
124 120
121/**
122 * get_skb_frame_desc - Obtain the rt2x00 frame descriptor from a sk_buff.
123 * @skb: &struct sk_buff from where we obtain the &struct skb_frame_desc
124 */
125static inline struct skb_frame_desc* get_skb_frame_desc(struct sk_buff *skb) 125static inline struct skb_frame_desc* get_skb_frame_desc(struct sk_buff *skb)
126{ 126{
127 BUILD_BUG_ON(sizeof(struct skb_frame_desc) > sizeof(skb->cb)); 127 BUILD_BUG_ON(sizeof(struct skb_frame_desc) >
128 return (struct skb_frame_desc *)&skb->cb[0]; 128 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
129 return (struct skb_frame_desc *)&IEEE80211_SKB_CB(skb)->driver_data;
129} 130}
130 131
131/** 132/**
@@ -145,6 +146,7 @@ enum rxdone_entry_desc_flags {
145 * 146 *
146 * Summary of information that has been read from the RX frame descriptor. 147 * Summary of information that has been read from the RX frame descriptor.
147 * 148 *
149 * @timestamp: RX Timestamp
148 * @signal: Signal of the received frame. 150 * @signal: Signal of the received frame.
149 * @rssi: RSSI of the received frame. 151 * @rssi: RSSI of the received frame.
150 * @size: Data size of the received frame. 152 * @size: Data size of the received frame.
@@ -153,6 +155,7 @@ enum rxdone_entry_desc_flags {
153 155
154 */ 156 */
155struct rxdone_entry_desc { 157struct rxdone_entry_desc {
158 u64 timestamp;
156 int signal; 159 int signal;
157 int rssi; 160 int rssi;
158 int size; 161 int size;
@@ -161,18 +164,32 @@ struct rxdone_entry_desc {
161}; 164};
162 165
163/** 166/**
167 * enum txdone_entry_desc_flags: Flags for &struct txdone_entry_desc
168 *
169 * @TXDONE_UNKNOWN: Hardware could not determine success of transmission.
170 * @TXDONE_SUCCESS: Frame was successfully send
171 * @TXDONE_FAILURE: Frame was not successfully send
172 * @TXDONE_EXCESSIVE_RETRY: In addition to &TXDONE_FAILURE, the
173 * frame transmission failed due to excessive retries.
174 */
175enum txdone_entry_desc_flags {
176 TXDONE_UNKNOWN = 1 << 0,
177 TXDONE_SUCCESS = 1 << 1,
178 TXDONE_FAILURE = 1 << 2,
179 TXDONE_EXCESSIVE_RETRY = 1 << 3,
180};
181
182/**
164 * struct txdone_entry_desc: TX done entry descriptor 183 * struct txdone_entry_desc: TX done entry descriptor
165 * 184 *
166 * Summary of information that has been read from the TX frame descriptor 185 * Summary of information that has been read from the TX frame descriptor
167 * after the device is done with transmission. 186 * after the device is done with transmission.
168 * 187 *
169 * @control: Control structure which was used to transmit the frame. 188 * @flags: TX done flags (See &enum txdone_entry_desc_flags).
170 * @status: TX status (See &enum tx_status).
171 * @retry: Retry count. 189 * @retry: Retry count.
172 */ 190 */
173struct txdone_entry_desc { 191struct txdone_entry_desc {
174 struct ieee80211_tx_control *control; 192 unsigned long flags;
175 int status;
176 int retry; 193 int retry;
177}; 194};
178 195
@@ -180,19 +197,25 @@ struct txdone_entry_desc {
180 * enum txentry_desc_flags: Status flags for TX entry descriptor 197 * enum txentry_desc_flags: Status flags for TX entry descriptor
181 * 198 *
182 * @ENTRY_TXD_RTS_FRAME: This frame is a RTS frame. 199 * @ENTRY_TXD_RTS_FRAME: This frame is a RTS frame.
200 * @ENTRY_TXD_CTS_FRAME: This frame is a CTS-to-self frame.
183 * @ENTRY_TXD_OFDM_RATE: This frame is send out with an OFDM rate. 201 * @ENTRY_TXD_OFDM_RATE: This frame is send out with an OFDM rate.
202 * @ENTRY_TXD_FIRST_FRAGMENT: This is the first frame.
184 * @ENTRY_TXD_MORE_FRAG: This frame is followed by another fragment. 203 * @ENTRY_TXD_MORE_FRAG: This frame is followed by another fragment.
185 * @ENTRY_TXD_REQ_TIMESTAMP: Require timestamp to be inserted. 204 * @ENTRY_TXD_REQ_TIMESTAMP: Require timestamp to be inserted.
186 * @ENTRY_TXD_BURST: This frame belongs to the same burst event. 205 * @ENTRY_TXD_BURST: This frame belongs to the same burst event.
187 * @ENTRY_TXD_ACK: An ACK is required for this frame. 206 * @ENTRY_TXD_ACK: An ACK is required for this frame.
207 * @ENTRY_TXD_RETRY_MODE: When set, the long retry count is used.
188 */ 208 */
189enum txentry_desc_flags { 209enum txentry_desc_flags {
190 ENTRY_TXD_RTS_FRAME, 210 ENTRY_TXD_RTS_FRAME,
211 ENTRY_TXD_CTS_FRAME,
191 ENTRY_TXD_OFDM_RATE, 212 ENTRY_TXD_OFDM_RATE,
213 ENTRY_TXD_FIRST_FRAGMENT,
192 ENTRY_TXD_MORE_FRAG, 214 ENTRY_TXD_MORE_FRAG,
193 ENTRY_TXD_REQ_TIMESTAMP, 215 ENTRY_TXD_REQ_TIMESTAMP,
194 ENTRY_TXD_BURST, 216 ENTRY_TXD_BURST,
195 ENTRY_TXD_ACK, 217 ENTRY_TXD_ACK,
218 ENTRY_TXD_RETRY_MODE,
196}; 219};
197 220
198/** 221/**
@@ -206,6 +229,7 @@ enum txentry_desc_flags {
206 * @length_low: PLCP length low word. 229 * @length_low: PLCP length low word.
207 * @signal: PLCP signal. 230 * @signal: PLCP signal.
208 * @service: PLCP service. 231 * @service: PLCP service.
232 * @retry_limit: Max number of retries.
209 * @aifs: AIFS value. 233 * @aifs: AIFS value.
210 * @ifs: IFS value. 234 * @ifs: IFS value.
211 * @cw_min: cwmin value. 235 * @cw_min: cwmin value.
@@ -221,10 +245,11 @@ struct txentry_desc {
221 u16 signal; 245 u16 signal;
222 u16 service; 246 u16 service;
223 247
224 int aifs; 248 short retry_limit;
225 int ifs; 249 short aifs;
226 int cw_min; 250 short ifs;
227 int cw_max; 251 short cw_min;
252 short cw_max;
228}; 253};
229 254
230/** 255/**
@@ -239,12 +264,14 @@ struct txentry_desc {
239 * @ENTRY_OWNER_DEVICE_CRYPTO: This entry is owned by the device for data 264 * @ENTRY_OWNER_DEVICE_CRYPTO: This entry is owned by the device for data
240 * encryption or decryption. The entry should only be touched after 265 * encryption or decryption. The entry should only be touched after
241 * the device has signaled it is done with it. 266 * the device has signaled it is done with it.
267 * @ENTRY_DATA_PENDING: This entry contains a valid frame and is waiting
268 * for the signal to start sending.
242 */ 269 */
243
244enum queue_entry_flags { 270enum queue_entry_flags {
245 ENTRY_BCN_ASSIGNED, 271 ENTRY_BCN_ASSIGNED,
246 ENTRY_OWNER_DEVICE_DATA, 272 ENTRY_OWNER_DEVICE_DATA,
247 ENTRY_OWNER_DEVICE_CRYPTO, 273 ENTRY_OWNER_DEVICE_CRYPTO,
274 ENTRY_DATA_PENDING,
248}; 275};
249 276
250/** 277/**
@@ -302,6 +329,7 @@ enum queue_index {
302 * index corruption due to concurrency. 329 * index corruption due to concurrency.
303 * @count: Number of frames handled in the queue. 330 * @count: Number of frames handled in the queue.
304 * @limit: Maximum number of entries in the queue. 331 * @limit: Maximum number of entries in the queue.
332 * @threshold: Minimum number of free entries before queue is kicked by force.
305 * @length: Number of frames in queue. 333 * @length: Number of frames in queue.
306 * @index: Index pointers to entry positions in the queue, 334 * @index: Index pointers to entry positions in the queue,
307 * use &enum queue_index to get a specific index field. 335 * use &enum queue_index to get a specific index field.
@@ -320,6 +348,7 @@ struct data_queue {
320 spinlock_t lock; 348 spinlock_t lock;
321 unsigned int count; 349 unsigned int count;
322 unsigned short limit; 350 unsigned short limit;
351 unsigned short threshold;
323 unsigned short length; 352 unsigned short length;
324 unsigned short index[Q_INDEX_MAX]; 353 unsigned short index[Q_INDEX_MAX];
325 354
@@ -369,7 +398,7 @@ struct data_queue_desc {
369 * the end of the TX queue array. 398 * the end of the TX queue array.
370 */ 399 */
371#define tx_queue_end(__dev) \ 400#define tx_queue_end(__dev) \
372 &(__dev)->tx[(__dev)->hw->queues] 401 &(__dev)->tx[(__dev)->ops->tx_queues]
373 402
374/** 403/**
375 * queue_loop - Loop through the queues within a specific range (HELPER MACRO). 404 * queue_loop - Loop through the queues within a specific range (HELPER MACRO).
@@ -444,6 +473,15 @@ static inline int rt2x00queue_available(struct data_queue *queue)
444} 473}
445 474
446/** 475/**
476 * rt2x00queue_threshold - Check if the queue is below threshold
477 * @queue: Queue to check.
478 */
479static inline int rt2x00queue_threshold(struct data_queue *queue)
480{
481 return rt2x00queue_available(queue) < queue->threshold;
482}
483
484/**
447 * rt2x00_desc_read - Read a word from the hardware descriptor. 485 * rt2x00_desc_read - Read a word from the hardware descriptor.
448 * @desc: Base descriptor address 486 * @desc: Base descriptor address
449 * @word: Word index from where the descriptor should be read. 487 * @word: Word index from where the descriptor should be read.
diff --git a/drivers/net/wireless/rt2x00/rt2x00reg.h b/drivers/net/wireless/rt2x00/rt2x00reg.h
index 0325bed2fbf5..7e88ce5651b9 100644
--- a/drivers/net/wireless/rt2x00/rt2x00reg.h
+++ b/drivers/net/wireless/rt2x00/rt2x00reg.h
@@ -27,17 +27,6 @@
27#define RT2X00REG_H 27#define RT2X00REG_H
28 28
29/* 29/*
30 * TX result flags.
31 */
32enum tx_status {
33 TX_SUCCESS = 0,
34 TX_SUCCESS_RETRY = 1,
35 TX_FAIL_RETRY = 2,
36 TX_FAIL_INVALID = 3,
37 TX_FAIL_OTHER = 4,
38};
39
40/*
41 * Antenna values 30 * Antenna values
42 */ 31 */
43enum antenna { 32enum antenna {
@@ -141,83 +130,107 @@ struct rt2x00_field32 {
141 130
142/* 131/*
143 * Power of two check, this will check 132 * Power of two check, this will check
144 * if the mask that has been given contains 133 * if the mask that has been given contains and contiguous set of bits.
145 * and contiguous set of bits. 134 * Note that we cannot use the is_power_of_2() function since this
135 * check must be done at compile-time.
146 */ 136 */
147#define is_power_of_two(x) ( !((x) & ((x)-1)) ) 137#define is_power_of_two(x) ( !((x) & ((x)-1)) )
148#define low_bit_mask(x) ( ((x)-1) & ~(x) ) 138#define low_bit_mask(x) ( ((x)-1) & ~(x) )
149#define is_valid_mask(x) is_power_of_two(1 + (x) + low_bit_mask(x)) 139#define is_valid_mask(x) is_power_of_two(1 + (x) + low_bit_mask(x))
150 140
141/*
142 * Macro's to find first set bit in a variable.
143 * These macro's behaves the same as the __ffs() function with
144 * the most important difference that this is done during
145 * compile-time rather then run-time.
146 */
147#define compile_ffs2(__x) \
148 __builtin_choose_expr(((__x) & 0x1), 0, 1)
149
150#define compile_ffs4(__x) \
151 __builtin_choose_expr(((__x) & 0x3), \
152 (compile_ffs2((__x))), \
153 (compile_ffs2((__x) >> 2) + 2))
154
155#define compile_ffs8(__x) \
156 __builtin_choose_expr(((__x) & 0xf), \
157 (compile_ffs4((__x))), \
158 (compile_ffs4((__x) >> 4) + 4))
159
160#define compile_ffs16(__x) \
161 __builtin_choose_expr(((__x) & 0xff), \
162 (compile_ffs8((__x))), \
163 (compile_ffs8((__x) >> 8) + 8))
164
165#define compile_ffs32(__x) \
166 __builtin_choose_expr(((__x) & 0xffff), \
167 (compile_ffs16((__x))), \
168 (compile_ffs16((__x) >> 16) + 16))
169
170/*
171 * This macro will check the requirements for the FIELD{8,16,32} macros
172 * The mask should be a constant non-zero contiguous set of bits which
173 * does not exceed the given typelimit.
174 */
175#define FIELD_CHECK(__mask, __type) \
176 BUILD_BUG_ON(!__builtin_constant_p(__mask) || \
177 !(__mask) || \
178 !is_valid_mask(__mask) || \
179 (__mask) != (__type)(__mask)) \
180
151#define FIELD8(__mask) \ 181#define FIELD8(__mask) \
152({ \ 182({ \
153 BUILD_BUG_ON(!(__mask) || \ 183 FIELD_CHECK(__mask, u8); \
154 !is_valid_mask(__mask) || \
155 (__mask) != (u8)(__mask)); \
156 (struct rt2x00_field8) { \ 184 (struct rt2x00_field8) { \
157 __ffs(__mask), (__mask) \ 185 compile_ffs8(__mask), (__mask) \
158 }; \ 186 }; \
159}) 187})
160 188
161#define FIELD16(__mask) \ 189#define FIELD16(__mask) \
162({ \ 190({ \
163 BUILD_BUG_ON(!(__mask) || \ 191 FIELD_CHECK(__mask, u16); \
164 !is_valid_mask(__mask) || \
165 (__mask) != (u16)(__mask));\
166 (struct rt2x00_field16) { \ 192 (struct rt2x00_field16) { \
167 __ffs(__mask), (__mask) \ 193 compile_ffs16(__mask), (__mask) \
168 }; \ 194 }; \
169}) 195})
170 196
171#define FIELD32(__mask) \ 197#define FIELD32(__mask) \
172({ \ 198({ \
173 BUILD_BUG_ON(!(__mask) || \ 199 FIELD_CHECK(__mask, u32); \
174 !is_valid_mask(__mask) || \
175 (__mask) != (u32)(__mask));\
176 (struct rt2x00_field32) { \ 200 (struct rt2x00_field32) { \
177 __ffs(__mask), (__mask) \ 201 compile_ffs32(__mask), (__mask) \
178 }; \ 202 }; \
179}) 203})
180 204
181static inline void rt2x00_set_field32(u32 *reg, 205#define SET_FIELD(__reg, __type, __field, __value)\
182 const struct rt2x00_field32 field, 206({ \
183 const u32 value) 207 typecheck(__type, __field); \
184{ 208 *(__reg) &= ~((__field).bit_mask); \
185 *reg &= ~(field.bit_mask); 209 *(__reg) |= ((__value) << \
186 *reg |= (value << field.bit_offset) & field.bit_mask; 210 ((__field).bit_offset)) & \
187} 211 ((__field).bit_mask); \
188 212})
189static inline u32 rt2x00_get_field32(const u32 reg, 213
190 const struct rt2x00_field32 field) 214#define GET_FIELD(__reg, __type, __field) \
191{ 215({ \
192 return (reg & field.bit_mask) >> field.bit_offset; 216 typecheck(__type, __field); \
193} 217 ((__reg) & ((__field).bit_mask)) >> \
194 218 ((__field).bit_offset); \
195static inline void rt2x00_set_field16(u16 *reg, 219})
196 const struct rt2x00_field16 field, 220
197 const u16 value) 221#define rt2x00_set_field32(__reg, __field, __value) \
198{ 222 SET_FIELD(__reg, struct rt2x00_field32, __field, __value)
199 *reg &= ~(field.bit_mask); 223#define rt2x00_get_field32(__reg, __field) \
200 *reg |= (value << field.bit_offset) & field.bit_mask; 224 GET_FIELD(__reg, struct rt2x00_field32, __field)
201} 225
202 226#define rt2x00_set_field16(__reg, __field, __value) \
203static inline u16 rt2x00_get_field16(const u16 reg, 227 SET_FIELD(__reg, struct rt2x00_field16, __field, __value)
204 const struct rt2x00_field16 field) 228#define rt2x00_get_field16(__reg, __field) \
205{ 229 GET_FIELD(__reg, struct rt2x00_field16, __field)
206 return (reg & field.bit_mask) >> field.bit_offset; 230
207} 231#define rt2x00_set_field8(__reg, __field, __value) \
208 232 SET_FIELD(__reg, struct rt2x00_field8, __field, __value)
209static inline void rt2x00_set_field8(u8 *reg, 233#define rt2x00_get_field8(__reg, __field) \
210 const struct rt2x00_field8 field, 234 GET_FIELD(__reg, struct rt2x00_field8, __field)
211 const u8 value)
212{
213 *reg &= ~(field.bit_mask);
214 *reg |= (value << field.bit_offset) & field.bit_mask;
215}
216
217static inline u8 rt2x00_get_field8(const u8 reg,
218 const struct rt2x00_field8 field)
219{
220 return (reg & field.bit_mask) >> field.bit_offset;
221}
222 235
223#endif /* RT2X00REG_H */ 236#endif /* RT2X00REG_H */
diff --git a/drivers/net/wireless/rt2x00/rt2x00rfkill.c b/drivers/net/wireless/rt2x00/rt2x00rfkill.c
index fcef9885ab5e..04b29716d356 100644
--- a/drivers/net/wireless/rt2x00/rt2x00rfkill.c
+++ b/drivers/net/wireless/rt2x00/rt2x00rfkill.c
@@ -23,7 +23,6 @@
23 Abstract: rt2x00 rfkill routines. 23 Abstract: rt2x00 rfkill routines.
24 */ 24 */
25 25
26#include <linux/input-polldev.h>
27#include <linux/kernel.h> 26#include <linux/kernel.h>
28#include <linux/module.h> 27#include <linux/module.h>
29#include <linux/rfkill.h> 28#include <linux/rfkill.h>
@@ -45,28 +44,51 @@ static int rt2x00rfkill_toggle_radio(void *data, enum rfkill_state state)
45 if (!test_bit(DEVICE_STARTED, &rt2x00dev->flags)) 44 if (!test_bit(DEVICE_STARTED, &rt2x00dev->flags))
46 return 0; 45 return 0;
47 46
48 if (state == RFKILL_STATE_ON) { 47 if (state == RFKILL_STATE_UNBLOCKED) {
49 INFO(rt2x00dev, "Hardware button pressed, enabling radio.\n"); 48 INFO(rt2x00dev, "Hardware button pressed, enabling radio.\n");
50 __clear_bit(DEVICE_DISABLED_RADIO_HW, &rt2x00dev->flags); 49 __clear_bit(DEVICE_DISABLED_RADIO_HW, &rt2x00dev->flags);
51 retval = rt2x00lib_enable_radio(rt2x00dev); 50 retval = rt2x00lib_enable_radio(rt2x00dev);
52 } else if (state == RFKILL_STATE_OFF) { 51 } else if (state == RFKILL_STATE_SOFT_BLOCKED) {
53 INFO(rt2x00dev, "Hardware button pressed, disabling radio.\n"); 52 INFO(rt2x00dev, "Hardware button pressed, disabling radio.\n");
54 __set_bit(DEVICE_DISABLED_RADIO_HW, &rt2x00dev->flags); 53 __set_bit(DEVICE_DISABLED_RADIO_HW, &rt2x00dev->flags);
55 rt2x00lib_disable_radio(rt2x00dev); 54 rt2x00lib_disable_radio(rt2x00dev);
55 } else {
56 WARNING(rt2x00dev, "Received unexpected rfkill state %d.\n",
57 state);
56 } 58 }
57 59
58 return retval; 60 return retval;
59} 61}
60 62
61static void rt2x00rfkill_poll(struct input_polled_dev *poll_dev) 63static int rt2x00rfkill_get_state(void *data, enum rfkill_state *state)
62{ 64{
63 struct rt2x00_dev *rt2x00dev = poll_dev->private; 65 struct rt2x00_dev *rt2x00dev = data;
64 int state = rt2x00dev->ops->lib->rfkill_poll(rt2x00dev);
65 66
66 if (rt2x00dev->rfkill->state != state) { 67 *state = rt2x00dev->rfkill->state;
67 input_report_key(poll_dev->input, KEY_WLAN, 1); 68
68 input_report_key(poll_dev->input, KEY_WLAN, 0); 69 return 0;
69 } 70}
71
72static void rt2x00rfkill_poll(struct work_struct *work)
73{
74 struct rt2x00_dev *rt2x00dev =
75 container_of(work, struct rt2x00_dev, rfkill_work.work);
76 int state;
77
78 if (!test_bit(RFKILL_STATE_REGISTERED, &rt2x00dev->rfkill_state))
79 return;
80
81 /*
82 * rfkill_poll reports 1 when the key has been pressed and the
83 * radio should be blocked.
84 */
85 state = !rt2x00dev->ops->lib->rfkill_poll(rt2x00dev) ?
86 RFKILL_STATE_UNBLOCKED : RFKILL_STATE_SOFT_BLOCKED;
87
88 rfkill_force_state(rt2x00dev->rfkill, state);
89
90 queue_delayed_work(rt2x00dev->hw->workqueue,
91 &rt2x00dev->rfkill_work, RFKILL_POLL_INTERVAL);
70} 92}
71 93
72void rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev) 94void rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev)
@@ -80,12 +102,6 @@ void rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev)
80 return; 102 return;
81 } 103 }
82 104
83 if (input_register_polled_device(rt2x00dev->poll_dev)) {
84 ERROR(rt2x00dev, "Failed to register polled device.\n");
85 rfkill_unregister(rt2x00dev->rfkill);
86 return;
87 }
88
89 __set_bit(RFKILL_STATE_REGISTERED, &rt2x00dev->rfkill_state); 105 __set_bit(RFKILL_STATE_REGISTERED, &rt2x00dev->rfkill_state);
90 106
91 /* 107 /*
@@ -93,7 +109,7 @@ void rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev)
93 * and correctly sends the signal to the rfkill layer about this 109 * and correctly sends the signal to the rfkill layer about this
94 * state. 110 * state.
95 */ 111 */
96 rt2x00rfkill_poll(rt2x00dev->poll_dev); 112 rt2x00rfkill_poll(&rt2x00dev->rfkill_work.work);
97} 113}
98 114
99void rt2x00rfkill_unregister(struct rt2x00_dev *rt2x00dev) 115void rt2x00rfkill_unregister(struct rt2x00_dev *rt2x00dev)
@@ -102,38 +118,13 @@ void rt2x00rfkill_unregister(struct rt2x00_dev *rt2x00dev)
102 !test_bit(RFKILL_STATE_REGISTERED, &rt2x00dev->rfkill_state)) 118 !test_bit(RFKILL_STATE_REGISTERED, &rt2x00dev->rfkill_state))
103 return; 119 return;
104 120
105 input_unregister_polled_device(rt2x00dev->poll_dev); 121 cancel_delayed_work_sync(&rt2x00dev->rfkill_work);
122
106 rfkill_unregister(rt2x00dev->rfkill); 123 rfkill_unregister(rt2x00dev->rfkill);
107 124
108 __clear_bit(RFKILL_STATE_REGISTERED, &rt2x00dev->rfkill_state); 125 __clear_bit(RFKILL_STATE_REGISTERED, &rt2x00dev->rfkill_state);
109} 126}
110 127
111static struct input_polled_dev *
112rt2x00rfkill_allocate_polldev(struct rt2x00_dev *rt2x00dev)
113{
114 struct input_polled_dev *poll_dev;
115
116 poll_dev = input_allocate_polled_device();
117 if (!poll_dev)
118 return NULL;
119
120 poll_dev->private = rt2x00dev;
121 poll_dev->poll = rt2x00rfkill_poll;
122 poll_dev->poll_interval = RFKILL_POLL_INTERVAL;
123
124 poll_dev->input->name = rt2x00dev->ops->name;
125 poll_dev->input->phys = wiphy_name(rt2x00dev->hw->wiphy);
126 poll_dev->input->id.bustype = BUS_HOST;
127 poll_dev->input->id.vendor = 0x1814;
128 poll_dev->input->id.product = rt2x00dev->chip.rt;
129 poll_dev->input->id.version = rt2x00dev->chip.rev;
130 poll_dev->input->dev.parent = wiphy_dev(rt2x00dev->hw->wiphy);
131 poll_dev->input->evbit[0] = BIT(EV_KEY);
132 set_bit(KEY_WLAN, poll_dev->input->keybit);
133
134 return poll_dev;
135}
136
137void rt2x00rfkill_allocate(struct rt2x00_dev *rt2x00dev) 128void rt2x00rfkill_allocate(struct rt2x00_dev *rt2x00dev)
138{ 129{
139 if (!test_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags)) 130 if (!test_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags))
@@ -150,14 +141,9 @@ void rt2x00rfkill_allocate(struct rt2x00_dev *rt2x00dev)
150 rt2x00dev->rfkill->data = rt2x00dev; 141 rt2x00dev->rfkill->data = rt2x00dev;
151 rt2x00dev->rfkill->state = -1; 142 rt2x00dev->rfkill->state = -1;
152 rt2x00dev->rfkill->toggle_radio = rt2x00rfkill_toggle_radio; 143 rt2x00dev->rfkill->toggle_radio = rt2x00rfkill_toggle_radio;
144 rt2x00dev->rfkill->get_state = rt2x00rfkill_get_state;
153 145
154 rt2x00dev->poll_dev = rt2x00rfkill_allocate_polldev(rt2x00dev); 146 INIT_DELAYED_WORK(&rt2x00dev->rfkill_work, rt2x00rfkill_poll);
155 if (!rt2x00dev->poll_dev) {
156 ERROR(rt2x00dev, "Failed to allocate polled device.\n");
157 rfkill_free(rt2x00dev->rfkill);
158 rt2x00dev->rfkill = NULL;
159 return;
160 }
161 147
162 return; 148 return;
163} 149}
@@ -168,32 +154,8 @@ void rt2x00rfkill_free(struct rt2x00_dev *rt2x00dev)
168 !test_bit(RFKILL_STATE_ALLOCATED, &rt2x00dev->rfkill_state)) 154 !test_bit(RFKILL_STATE_ALLOCATED, &rt2x00dev->rfkill_state))
169 return; 155 return;
170 156
171 input_free_polled_device(rt2x00dev->poll_dev); 157 cancel_delayed_work_sync(&rt2x00dev->rfkill_work);
172 rt2x00dev->poll_dev = NULL;
173 158
174 rfkill_free(rt2x00dev->rfkill); 159 rfkill_free(rt2x00dev->rfkill);
175 rt2x00dev->rfkill = NULL; 160 rt2x00dev->rfkill = NULL;
176} 161}
177
178void rt2x00rfkill_suspend(struct rt2x00_dev *rt2x00dev)
179{
180 if (!test_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags) ||
181 !test_bit(RFKILL_STATE_ALLOCATED, &rt2x00dev->rfkill_state))
182 return;
183
184 input_free_polled_device(rt2x00dev->poll_dev);
185 rt2x00dev->poll_dev = NULL;
186}
187
188void rt2x00rfkill_resume(struct rt2x00_dev *rt2x00dev)
189{
190 if (!test_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags) ||
191 !test_bit(RFKILL_STATE_ALLOCATED, &rt2x00dev->rfkill_state))
192 return;
193
194 rt2x00dev->poll_dev = rt2x00rfkill_allocate_polldev(rt2x00dev);
195 if (!rt2x00dev->poll_dev) {
196 ERROR(rt2x00dev, "Failed to allocate polled device.\n");
197 return;
198 }
199}
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index e5ceae805b57..83862e7f7aec 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -40,7 +40,7 @@ int rt2x00usb_vendor_request(struct rt2x00_dev *rt2x00dev,
40 void *buffer, const u16 buffer_length, 40 void *buffer, const u16 buffer_length,
41 const int timeout) 41 const int timeout)
42{ 42{
43 struct usb_device *usb_dev = rt2x00dev_usb_dev(rt2x00dev); 43 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
44 int status; 44 int status;
45 unsigned int i; 45 unsigned int i;
46 unsigned int pipe = 46 unsigned int pipe =
@@ -129,17 +129,12 @@ static void rt2x00usb_interrupt_txdone(struct urb *urb)
129{ 129{
130 struct queue_entry *entry = (struct queue_entry *)urb->context; 130 struct queue_entry *entry = (struct queue_entry *)urb->context;
131 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 131 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
132 struct queue_entry_priv_usb_tx *priv_tx = entry->priv_data;
133 struct txdone_entry_desc txdesc; 132 struct txdone_entry_desc txdesc;
134 __le32 *txd = (__le32 *)entry->skb->data;
135 u32 word;
136 133
137 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags) || 134 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags) ||
138 !__test_and_clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) 135 !test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
139 return; 136 return;
140 137
141 rt2x00_desc_read(txd, 0, &word);
142
143 /* 138 /*
144 * Remove the descriptor data from the buffer. 139 * Remove the descriptor data from the buffer.
145 */ 140 */
@@ -147,128 +142,116 @@ static void rt2x00usb_interrupt_txdone(struct urb *urb)
147 142
148 /* 143 /*
149 * Obtain the status about this packet. 144 * Obtain the status about this packet.
145 * Note that when the status is 0 it does not mean the
146 * frame was send out correctly. It only means the frame
147 * was succesfully pushed to the hardware, we have no
148 * way to determine the transmission status right now.
149 * (Only indirectly by looking at the failed TX counters
150 * in the register).
150 */ 151 */
151 txdesc.status = !urb->status ? TX_SUCCESS : TX_FAIL_RETRY; 152 if (!urb->status)
153 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
154 else
155 __set_bit(TXDONE_FAILURE, &txdesc.flags);
152 txdesc.retry = 0; 156 txdesc.retry = 0;
153 txdesc.control = &priv_tx->control;
154 157
155 rt2x00lib_txdone(entry, &txdesc); 158 rt2x00lib_txdone(entry, &txdesc);
156
157 /*
158 * Make this entry available for reuse.
159 */
160 entry->flags = 0;
161 rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);
162
163 /*
164 * If the data queue was full before the txdone handler
165 * we must make sure the packet queue in the mac80211 stack
166 * is reenabled when the txdone handler has finished.
167 */
168 if (!rt2x00queue_full(entry->queue))
169 ieee80211_wake_queue(rt2x00dev->hw, priv_tx->control.queue);
170} 159}
171 160
172int rt2x00usb_write_tx_data(struct rt2x00_dev *rt2x00dev, 161int rt2x00usb_write_tx_data(struct queue_entry *entry)
173 struct data_queue *queue, struct sk_buff *skb,
174 struct ieee80211_tx_control *control)
175{ 162{
176 struct usb_device *usb_dev = rt2x00dev_usb_dev(rt2x00dev); 163 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
177 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX); 164 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
178 struct queue_entry_priv_usb_tx *priv_tx = entry->priv_data; 165 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
179 struct skb_frame_desc *skbdesc; 166 struct skb_frame_desc *skbdesc;
180 u32 length; 167 u32 length;
181 168
182 if (rt2x00queue_full(queue))
183 return -EINVAL;
184
185 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
186 ERROR(rt2x00dev,
187 "Arrived at non-free entry in the non-full queue %d.\n"
188 "Please file bug report to %s.\n",
189 control->queue, DRV_PROJECT);
190 return -EINVAL;
191 }
192
193 /* 169 /*
194 * Add the descriptor in front of the skb. 170 * Add the descriptor in front of the skb.
195 */ 171 */
196 skb_push(skb, queue->desc_size); 172 skb_push(entry->skb, entry->queue->desc_size);
197 memset(skb->data, 0, queue->desc_size); 173 memset(entry->skb->data, 0, entry->queue->desc_size);
198 174
199 /* 175 /*
200 * Fill in skb descriptor 176 * Fill in skb descriptor
201 */ 177 */
202 skbdesc = get_skb_frame_desc(skb); 178 skbdesc = get_skb_frame_desc(entry->skb);
203 skbdesc->data = skb->data + queue->desc_size; 179 skbdesc->desc = entry->skb->data;
204 skbdesc->data_len = skb->len - queue->desc_size; 180 skbdesc->desc_len = entry->queue->desc_size;
205 skbdesc->desc = skb->data;
206 skbdesc->desc_len = queue->desc_size;
207 skbdesc->entry = entry;
208
209 memcpy(&priv_tx->control, control, sizeof(priv_tx->control));
210 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
211 181
212 /* 182 /*
213 * USB devices cannot blindly pass the skb->len as the 183 * USB devices cannot blindly pass the skb->len as the
214 * length of the data to usb_fill_bulk_urb. Pass the skb 184 * length of the data to usb_fill_bulk_urb. Pass the skb
215 * to the driver to determine what the length should be. 185 * to the driver to determine what the length should be.
216 */ 186 */
217 length = rt2x00dev->ops->lib->get_tx_data_len(rt2x00dev, skb); 187 length = rt2x00dev->ops->lib->get_tx_data_len(rt2x00dev, entry->skb);
218
219 /*
220 * Initialize URB and send the frame to the device.
221 */
222 __set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
223 usb_fill_bulk_urb(priv_tx->urb, usb_dev, usb_sndbulkpipe(usb_dev, 1),
224 skb->data, length, rt2x00usb_interrupt_txdone, entry);
225 usb_submit_urb(priv_tx->urb, GFP_ATOMIC);
226 188
227 rt2x00queue_index_inc(queue, Q_INDEX); 189 usb_fill_bulk_urb(entry_priv->urb, usb_dev,
190 usb_sndbulkpipe(usb_dev, 1),
191 entry->skb->data, length,
192 rt2x00usb_interrupt_txdone, entry);
228 193
229 return 0; 194 return 0;
230} 195}
231EXPORT_SYMBOL_GPL(rt2x00usb_write_tx_data); 196EXPORT_SYMBOL_GPL(rt2x00usb_write_tx_data);
232 197
233/* 198static inline void rt2x00usb_kick_tx_entry(struct queue_entry *entry)
234 * RX data handlers.
235 */
236static struct sk_buff* rt2x00usb_alloc_rxskb(struct data_queue *queue)
237{ 199{
238 struct sk_buff *skb; 200 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
239 unsigned int frame_size; 201
202 if (__test_and_clear_bit(ENTRY_DATA_PENDING, &entry->flags))
203 usb_submit_urb(entry_priv->urb, GFP_ATOMIC);
204}
205
206void rt2x00usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
207 const enum data_queue_qid qid)
208{
209 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, qid);
210 unsigned long irqflags;
211 unsigned int index;
212 unsigned int index_done;
213 unsigned int i;
240 214
241 /* 215 /*
242 * As alignment we use 2 and not NET_IP_ALIGN because we need 216 * Only protect the range we are going to loop over,
243 * to be sure we have 2 bytes room in the head. (NET_IP_ALIGN 217 * if during our loop a extra entry is set to pending
244 * can be 0 on some hardware). We use these 2 bytes for frame 218 * it should not be kicked during this run, since it
245 * alignment later, we assume that the chance that 219 * is part of another TX operation.
246 * header_size % 4 == 2 is bigger then header_size % 2 == 0
247 * and thus optimize alignment by reserving the 2 bytes in
248 * advance.
249 */ 220 */
250 frame_size = queue->data_size + queue->desc_size; 221 spin_lock_irqsave(&queue->lock, irqflags);
251 skb = dev_alloc_skb(queue->desc_size + frame_size + 2); 222 index = queue->index[Q_INDEX];
252 if (!skb) 223 index_done = queue->index[Q_INDEX_DONE];
253 return NULL; 224 spin_unlock_irqrestore(&queue->lock, irqflags);
254
255 skb_reserve(skb, queue->desc_size + 2);
256 skb_put(skb, frame_size);
257 225
258 return skb; 226 /*
227 * Start from the TX done pointer, this guarentees that we will
228 * send out all frames in the correct order.
229 */
230 if (index_done < index) {
231 for (i = index_done; i < index; i++)
232 rt2x00usb_kick_tx_entry(&queue->entries[i]);
233 } else {
234 for (i = index_done; i < queue->limit; i++)
235 rt2x00usb_kick_tx_entry(&queue->entries[i]);
236
237 for (i = 0; i < index; i++)
238 rt2x00usb_kick_tx_entry(&queue->entries[i]);
239 }
259} 240}
241EXPORT_SYMBOL_GPL(rt2x00usb_kick_tx_queue);
260 242
243/*
244 * RX data handlers.
245 */
261static void rt2x00usb_interrupt_rxdone(struct urb *urb) 246static void rt2x00usb_interrupt_rxdone(struct urb *urb)
262{ 247{
263 struct queue_entry *entry = (struct queue_entry *)urb->context; 248 struct queue_entry *entry = (struct queue_entry *)urb->context;
264 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 249 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
265 struct sk_buff *skb; 250 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
266 struct skb_frame_desc *skbdesc; 251 u8 rxd[32];
267 struct rxdone_entry_desc rxdesc;
268 int header_size;
269 252
270 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags) || 253 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags) ||
271 !test_and_clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) 254 !test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
272 return; 255 return;
273 256
274 /* 257 /*
@@ -276,61 +259,22 @@ static void rt2x00usb_interrupt_rxdone(struct urb *urb)
276 * to be actually valid, or if the urb is signaling 259 * to be actually valid, or if the urb is signaling
277 * a problem. 260 * a problem.
278 */ 261 */
279 if (urb->actual_length < entry->queue->desc_size || urb->status) 262 if (urb->actual_length < entry->queue->desc_size || urb->status) {
280 goto skip_entry; 263 __set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
281 264 usb_submit_urb(urb, GFP_ATOMIC);
282 /* 265 return;
283 * Fill in skb descriptor
284 */
285 skbdesc = get_skb_frame_desc(entry->skb);
286 memset(skbdesc, 0, sizeof(*skbdesc));
287 skbdesc->entry = entry;
288
289 memset(&rxdesc, 0, sizeof(rxdesc));
290 rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
291
292 /*
293 * The data behind the ieee80211 header must be
294 * aligned on a 4 byte boundary.
295 */
296 header_size = ieee80211_get_hdrlen_from_skb(entry->skb);
297 if (header_size % 4 == 0) {
298 skb_push(entry->skb, 2);
299 memmove(entry->skb->data, entry->skb->data + 2,
300 entry->skb->len - 2);
301 skbdesc->data = entry->skb->data;
302 skb_trim(entry->skb,entry->skb->len - 2);
303 } 266 }
304 267
305 /* 268 /*
306 * Allocate a new sk buffer to replace the current one. 269 * Fill in desc fields of the skb descriptor
307 * If allocation fails, we should drop the current frame
308 * so we can recycle the existing sk buffer for the new frame.
309 */ 270 */
310 skb = rt2x00usb_alloc_rxskb(entry->queue); 271 skbdesc->desc = rxd;
311 if (!skb) 272 skbdesc->desc_len = entry->queue->desc_size;
312 goto skip_entry;
313 273
314 /* 274 /*
315 * Send the frame to rt2x00lib for further processing. 275 * Send the frame to rt2x00lib for further processing.
316 */ 276 */
317 rt2x00lib_rxdone(entry, &rxdesc); 277 rt2x00lib_rxdone(rt2x00dev, entry);
318
319 /*
320 * Replace current entry's skb with the newly allocated one,
321 * and reinitialize the urb.
322 */
323 entry->skb = skb;
324 urb->transfer_buffer = entry->skb->data;
325 urb->transfer_buffer_length = entry->skb->len;
326
327skip_entry:
328 if (test_bit(DEVICE_ENABLED_RADIO, &entry->queue->rt2x00dev->flags)) {
329 __set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
330 usb_submit_urb(urb, GFP_ATOMIC);
331 }
332
333 rt2x00queue_index_inc(entry->queue, Q_INDEX);
334} 278}
335 279
336/* 280/*
@@ -338,27 +282,21 @@ skip_entry:
338 */ 282 */
339void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev) 283void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev)
340{ 284{
341 struct queue_entry_priv_usb_rx *priv_rx; 285 struct queue_entry_priv_usb *entry_priv;
342 struct queue_entry_priv_usb_tx *priv_tx; 286 struct queue_entry_priv_usb_bcn *bcn_priv;
343 struct queue_entry_priv_usb_bcn *priv_bcn;
344 struct data_queue *queue; 287 struct data_queue *queue;
345 unsigned int i; 288 unsigned int i;
346 289
347 rt2x00usb_vendor_request_sw(rt2x00dev, USB_RX_CONTROL, 0x0000, 0x0000, 290 rt2x00usb_vendor_request_sw(rt2x00dev, USB_RX_CONTROL, 0, 0,
348 REGISTER_TIMEOUT); 291 REGISTER_TIMEOUT);
349 292
350 /* 293 /*
351 * Cancel all queues. 294 * Cancel all queues.
352 */ 295 */
353 for (i = 0; i < rt2x00dev->rx->limit; i++) { 296 queue_for_each(rt2x00dev, queue) {
354 priv_rx = rt2x00dev->rx->entries[i].priv_data;
355 usb_kill_urb(priv_rx->urb);
356 }
357
358 tx_queue_for_each(rt2x00dev, queue) {
359 for (i = 0; i < queue->limit; i++) { 297 for (i = 0; i < queue->limit; i++) {
360 priv_tx = queue->entries[i].priv_data; 298 entry_priv = queue->entries[i].priv_data;
361 usb_kill_urb(priv_tx->urb); 299 usb_kill_urb(entry_priv->urb);
362 } 300 }
363 } 301 }
364 302
@@ -369,19 +307,9 @@ void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev)
369 return; 307 return;
370 308
371 for (i = 0; i < rt2x00dev->bcn->limit; i++) { 309 for (i = 0; i < rt2x00dev->bcn->limit; i++) {
372 priv_bcn = rt2x00dev->bcn->entries[i].priv_data; 310 bcn_priv = rt2x00dev->bcn->entries[i].priv_data;
373 usb_kill_urb(priv_bcn->urb); 311 if (bcn_priv->guardian_urb)
374 312 usb_kill_urb(bcn_priv->guardian_urb);
375 if (priv_bcn->guardian_urb)
376 usb_kill_urb(priv_bcn->guardian_urb);
377 }
378
379 if (!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags))
380 return;
381
382 for (i = 0; i < rt2x00dev->bcn[1].limit; i++) {
383 priv_tx = rt2x00dev->bcn[1].entries[i].priv_data;
384 usb_kill_urb(priv_tx->urb);
385 } 313 }
386} 314}
387EXPORT_SYMBOL_GPL(rt2x00usb_disable_radio); 315EXPORT_SYMBOL_GPL(rt2x00usb_disable_radio);
@@ -392,16 +320,16 @@ EXPORT_SYMBOL_GPL(rt2x00usb_disable_radio);
392void rt2x00usb_init_rxentry(struct rt2x00_dev *rt2x00dev, 320void rt2x00usb_init_rxentry(struct rt2x00_dev *rt2x00dev,
393 struct queue_entry *entry) 321 struct queue_entry *entry)
394{ 322{
395 struct usb_device *usb_dev = rt2x00dev_usb_dev(rt2x00dev); 323 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
396 struct queue_entry_priv_usb_rx *priv_rx = entry->priv_data; 324 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
397 325
398 usb_fill_bulk_urb(priv_rx->urb, usb_dev, 326 usb_fill_bulk_urb(entry_priv->urb, usb_dev,
399 usb_rcvbulkpipe(usb_dev, 1), 327 usb_rcvbulkpipe(usb_dev, 1),
400 entry->skb->data, entry->skb->len, 328 entry->skb->data, entry->skb->len,
401 rt2x00usb_interrupt_rxdone, entry); 329 rt2x00usb_interrupt_rxdone, entry);
402 330
403 __set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags); 331 __set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
404 usb_submit_urb(priv_rx->urb, GFP_ATOMIC); 332 usb_submit_urb(entry_priv->urb, GFP_ATOMIC);
405} 333}
406EXPORT_SYMBOL_GPL(rt2x00usb_init_rxentry); 334EXPORT_SYMBOL_GPL(rt2x00usb_init_rxentry);
407 335
@@ -415,38 +343,31 @@ EXPORT_SYMBOL_GPL(rt2x00usb_init_txentry);
415static int rt2x00usb_alloc_urb(struct rt2x00_dev *rt2x00dev, 343static int rt2x00usb_alloc_urb(struct rt2x00_dev *rt2x00dev,
416 struct data_queue *queue) 344 struct data_queue *queue)
417{ 345{
418 struct queue_entry_priv_usb_rx *priv_rx; 346 struct queue_entry_priv_usb *entry_priv;
419 struct queue_entry_priv_usb_tx *priv_tx; 347 struct queue_entry_priv_usb_bcn *bcn_priv;
420 struct queue_entry_priv_usb_bcn *priv_bcn;
421 struct urb *urb;
422 unsigned int guardian =
423 test_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags);
424 unsigned int i; 348 unsigned int i;
425 349
350 for (i = 0; i < queue->limit; i++) {
351 entry_priv = queue->entries[i].priv_data;
352 entry_priv->urb = usb_alloc_urb(0, GFP_KERNEL);
353 if (!entry_priv->urb)
354 return -ENOMEM;
355 }
356
426 /* 357 /*
427 * Allocate the URB's 358 * If this is not the beacon queue or
359 * no guardian byte was required for the beacon,
360 * then we are done.
428 */ 361 */
362 if (rt2x00dev->bcn != queue ||
363 !test_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags))
364 return 0;
365
429 for (i = 0; i < queue->limit; i++) { 366 for (i = 0; i < queue->limit; i++) {
430 urb = usb_alloc_urb(0, GFP_KERNEL); 367 bcn_priv = queue->entries[i].priv_data;
431 if (!urb) 368 bcn_priv->guardian_urb = usb_alloc_urb(0, GFP_KERNEL);
369 if (!bcn_priv->guardian_urb)
432 return -ENOMEM; 370 return -ENOMEM;
433
434 if (queue->qid == QID_RX) {
435 priv_rx = queue->entries[i].priv_data;
436 priv_rx->urb = urb;
437 } else if (queue->qid == QID_MGMT && guardian) {
438 priv_bcn = queue->entries[i].priv_data;
439 priv_bcn->urb = urb;
440
441 urb = usb_alloc_urb(0, GFP_KERNEL);
442 if (!urb)
443 return -ENOMEM;
444
445 priv_bcn->guardian_urb = urb;
446 } else {
447 priv_tx = queue->entries[i].priv_data;
448 priv_tx->urb = urb;
449 }
450 } 371 }
451 372
452 return 0; 373 return 0;
@@ -455,47 +376,39 @@ static int rt2x00usb_alloc_urb(struct rt2x00_dev *rt2x00dev,
455static void rt2x00usb_free_urb(struct rt2x00_dev *rt2x00dev, 376static void rt2x00usb_free_urb(struct rt2x00_dev *rt2x00dev,
456 struct data_queue *queue) 377 struct data_queue *queue)
457{ 378{
458 struct queue_entry_priv_usb_rx *priv_rx; 379 struct queue_entry_priv_usb *entry_priv;
459 struct queue_entry_priv_usb_tx *priv_tx; 380 struct queue_entry_priv_usb_bcn *bcn_priv;
460 struct queue_entry_priv_usb_bcn *priv_bcn;
461 struct urb *urb;
462 unsigned int guardian =
463 test_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags);
464 unsigned int i; 381 unsigned int i;
465 382
466 if (!queue->entries) 383 if (!queue->entries)
467 return; 384 return;
468 385
469 for (i = 0; i < queue->limit; i++) { 386 for (i = 0; i < queue->limit; i++) {
470 if (queue->qid == QID_RX) { 387 entry_priv = queue->entries[i].priv_data;
471 priv_rx = queue->entries[i].priv_data; 388 usb_kill_urb(entry_priv->urb);
472 urb = priv_rx->urb; 389 usb_free_urb(entry_priv->urb);
473 } else if (queue->qid == QID_MGMT && guardian) { 390 }
474 priv_bcn = queue->entries[i].priv_data;
475
476 usb_kill_urb(priv_bcn->guardian_urb);
477 usb_free_urb(priv_bcn->guardian_urb);
478
479 urb = priv_bcn->urb;
480 } else {
481 priv_tx = queue->entries[i].priv_data;
482 urb = priv_tx->urb;
483 }
484 391
485 usb_kill_urb(urb); 392 /*
486 usb_free_urb(urb); 393 * If this is not the beacon queue or
487 if (queue->entries[i].skb) 394 * no guardian byte was required for the beacon,
488 kfree_skb(queue->entries[i].skb); 395 * then we are done.
396 */
397 if (rt2x00dev->bcn != queue ||
398 !test_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags))
399 return;
400
401 for (i = 0; i < queue->limit; i++) {
402 bcn_priv = queue->entries[i].priv_data;
403 usb_kill_urb(bcn_priv->guardian_urb);
404 usb_free_urb(bcn_priv->guardian_urb);
489 } 405 }
490} 406}
491 407
492int rt2x00usb_initialize(struct rt2x00_dev *rt2x00dev) 408int rt2x00usb_initialize(struct rt2x00_dev *rt2x00dev)
493{ 409{
494 struct data_queue *queue; 410 struct data_queue *queue;
495 struct sk_buff *skb; 411 int status;
496 unsigned int entry_size;
497 unsigned int i;
498 int uninitialized_var(status);
499 412
500 /* 413 /*
501 * Allocate DMA 414 * Allocate DMA
@@ -506,18 +419,6 @@ int rt2x00usb_initialize(struct rt2x00_dev *rt2x00dev)
506 goto exit; 419 goto exit;
507 } 420 }
508 421
509 /*
510 * For the RX queue, skb's should be allocated.
511 */
512 entry_size = rt2x00dev->rx->data_size + rt2x00dev->rx->desc_size;
513 for (i = 0; i < rt2x00dev->rx->limit; i++) {
514 skb = rt2x00usb_alloc_rxskb(rt2x00dev->rx);
515 if (!skb)
516 goto exit;
517
518 rt2x00dev->rx->entries[i].skb = skb;
519 }
520
521 return 0; 422 return 0;
522 423
523exit: 424exit:
@@ -596,7 +497,7 @@ int rt2x00usb_probe(struct usb_interface *usb_intf,
596 usb_set_intfdata(usb_intf, hw); 497 usb_set_intfdata(usb_intf, hw);
597 498
598 rt2x00dev = hw->priv; 499 rt2x00dev = hw->priv;
599 rt2x00dev->dev = usb_intf; 500 rt2x00dev->dev = &usb_intf->dev;
600 rt2x00dev->ops = ops; 501 rt2x00dev->ops = ops;
601 rt2x00dev->hw = hw; 502 rt2x00dev->hw = hw;
602 mutex_init(&rt2x00dev->usb_cache_mutex); 503 mutex_init(&rt2x00dev->usb_cache_mutex);
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.h b/drivers/net/wireless/rt2x00/rt2x00usb.h
index 11e55180cbaf..aad794adf52c 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.h
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.h
@@ -26,6 +26,12 @@
26#ifndef RT2X00USB_H 26#ifndef RT2X00USB_H
27#define RT2X00USB_H 27#define RT2X00USB_H
28 28
29#define to_usb_device_intf(d) \
30({ \
31 struct usb_interface *intf = to_usb_interface(d); \
32 interface_to_usbdev(intf); \
33})
34
29/* 35/*
30 * This variable should be used with the 36 * This variable should be used with the
31 * usb_driver structure initialization. 37 * usb_driver structure initialization.
@@ -47,6 +53,20 @@
47#define REGISTER_TIMEOUT 500 53#define REGISTER_TIMEOUT 500
48#define REGISTER_TIMEOUT_FIRMWARE 1000 54#define REGISTER_TIMEOUT_FIRMWARE 1000
49 55
56/**
57 * REGISTER_TIMEOUT16 - Determine the timeout for 16bit register access
58 * @__datalen: Data length
59 */
60#define REGISTER_TIMEOUT16(__datalen) \
61 ( REGISTER_TIMEOUT * ((__datalen) / sizeof(u16)) )
62
63/**
64 * REGISTER_TIMEOUT32 - Determine the timeout for 32bit register access
65 * @__datalen: Data length
66 */
67#define REGISTER_TIMEOUT32(__datalen) \
68 ( REGISTER_TIMEOUT * ((__datalen) / sizeof(u32)) )
69
50/* 70/*
51 * Cache size 71 * Cache size
52 */ 72 */
@@ -185,13 +205,12 @@ static inline int rt2x00usb_vendor_request_sw(struct rt2x00_dev *rt2x00dev,
185 * kmalloc for correct handling inside the kernel USB layer. 205 * kmalloc for correct handling inside the kernel USB layer.
186 */ 206 */
187static inline int rt2x00usb_eeprom_read(struct rt2x00_dev *rt2x00dev, 207static inline int rt2x00usb_eeprom_read(struct rt2x00_dev *rt2x00dev,
188 __le16 *eeprom, const u16 lenght) 208 __le16 *eeprom, const u16 length)
189{ 209{
190 int timeout = REGISTER_TIMEOUT * (lenght / sizeof(u16));
191
192 return rt2x00usb_vendor_request(rt2x00dev, USB_EEPROM_READ, 210 return rt2x00usb_vendor_request(rt2x00dev, USB_EEPROM_READ,
193 USB_VENDOR_REQUEST_IN, 0, 0, 211 USB_VENDOR_REQUEST_IN, 0, 0,
194 eeprom, lenght, timeout); 212 eeprom, length,
213 REGISTER_TIMEOUT16(length));
195} 214}
196 215
197/* 216/*
@@ -199,55 +218,53 @@ static inline int rt2x00usb_eeprom_read(struct rt2x00_dev *rt2x00dev,
199 */ 218 */
200void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev); 219void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev);
201 220
202/*
203 * TX data handlers.
204 */
205int rt2x00usb_write_tx_data(struct rt2x00_dev *rt2x00dev,
206 struct data_queue *queue, struct sk_buff *skb,
207 struct ieee80211_tx_control *control);
208
209/** 221/**
210 * struct queue_entry_priv_usb_rx: Per RX entry USB specific information 222 * rt2x00usb_write_tx_data - Initialize URB for TX operation
223 * @entry: The entry where the frame is located
211 * 224 *
212 * @urb: Urb structure used for device communication. 225 * This function will initialize the URB and skb descriptor
226 * to prepare the entry for the actual TX operation.
213 */ 227 */
214struct queue_entry_priv_usb_rx { 228int rt2x00usb_write_tx_data(struct queue_entry *entry);
215 struct urb *urb;
216};
217 229
218/** 230/**
219 * struct queue_entry_priv_usb_tx: Per TX entry USB specific information 231 * struct queue_entry_priv_usb: Per entry USB specific information
220 * 232 *
221 * @urb: Urb structure used for device communication. 233 * @urb: Urb structure used for device communication.
222 * @control: mac80211 control structure used to transmit data.
223 */ 234 */
224struct queue_entry_priv_usb_tx { 235struct queue_entry_priv_usb {
225 struct urb *urb; 236 struct urb *urb;
226
227 struct ieee80211_tx_control control;
228}; 237};
229 238
230/** 239/**
231 * struct queue_entry_priv_usb_tx: Per TX entry USB specific information 240 * struct queue_entry_priv_usb_bcn: Per TX entry USB specific information
232 * 241 *
233 * The first section should match &struct queue_entry_priv_usb_tx exactly. 242 * The first section should match &struct queue_entry_priv_usb exactly.
234 * rt2500usb can use this structure to send a guardian byte when working 243 * rt2500usb can use this structure to send a guardian byte when working
235 * with beacons. 244 * with beacons.
236 * 245 *
237 * @urb: Urb structure used for device communication. 246 * @urb: Urb structure used for device communication.
238 * @control: mac80211 control structure used to transmit data.
239 * @guardian_data: Set to 0, used for sending the guardian data. 247 * @guardian_data: Set to 0, used for sending the guardian data.
240 * @guardian_urb: Urb structure used to send the guardian data. 248 * @guardian_urb: Urb structure used to send the guardian data.
241 */ 249 */
242struct queue_entry_priv_usb_bcn { 250struct queue_entry_priv_usb_bcn {
243 struct urb *urb; 251 struct urb *urb;
244 252
245 struct ieee80211_tx_control control;
246
247 unsigned int guardian_data; 253 unsigned int guardian_data;
248 struct urb *guardian_urb; 254 struct urb *guardian_urb;
249}; 255};
250 256
257/**
258 * rt2x00usb_kick_tx_queue - Kick data queue
259 * @rt2x00dev: Pointer to &struct rt2x00_dev
260 * @qid: Data queue to kick
261 *
262 * This will walk through all entries of the queue and push all pending
263 * frames to the hardware as a single burst.
264 */
265void rt2x00usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
266 const enum data_queue_qid qid);
267
251/* 268/*
252 * Device initialization handlers. 269 * Device initialization handlers.
253 */ 270 */
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 580f90b63de7..f7c1f92c1448 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -330,6 +330,17 @@ static int rt61pci_blink_set(struct led_classdev *led_cdev,
330 330
331 return 0; 331 return 0;
332} 332}
333
334static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
335 struct rt2x00_led *led,
336 enum led_type type)
337{
338 led->rt2x00dev = rt2x00dev;
339 led->type = type;
340 led->led_dev.brightness_set = rt61pci_brightness_set;
341 led->led_dev.blink_set = rt61pci_blink_set;
342 led->flags = LED_INITIALIZED;
343}
333#endif /* CONFIG_RT61PCI_LEDS */ 344#endif /* CONFIG_RT61PCI_LEDS */
334 345
335/* 346/*
@@ -1018,49 +1029,35 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1018static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev, 1029static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1019 struct queue_entry *entry) 1030 struct queue_entry *entry)
1020{ 1031{
1021 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 1032 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1033 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1022 u32 word; 1034 u32 word;
1023 1035
1024 rt2x00_desc_read(priv_rx->desc, 5, &word); 1036 rt2x00_desc_read(entry_priv->desc, 5, &word);
1025 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, 1037 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1026 priv_rx->data_dma); 1038 skbdesc->skb_dma);
1027 rt2x00_desc_write(priv_rx->desc, 5, word); 1039 rt2x00_desc_write(entry_priv->desc, 5, word);
1028 1040
1029 rt2x00_desc_read(priv_rx->desc, 0, &word); 1041 rt2x00_desc_read(entry_priv->desc, 0, &word);
1030 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 1042 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1031 rt2x00_desc_write(priv_rx->desc, 0, word); 1043 rt2x00_desc_write(entry_priv->desc, 0, word);
1032} 1044}
1033 1045
1034static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev, 1046static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1035 struct queue_entry *entry) 1047 struct queue_entry *entry)
1036{ 1048{
1037 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data; 1049 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1038 u32 word; 1050 u32 word;
1039 1051
1040 rt2x00_desc_read(priv_tx->desc, 1, &word); 1052 rt2x00_desc_read(entry_priv->desc, 0, &word);
1041 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1042 rt2x00_desc_write(priv_tx->desc, 1, word);
1043
1044 rt2x00_desc_read(priv_tx->desc, 5, &word);
1045 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1046 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
1047 rt2x00_desc_write(priv_tx->desc, 5, word);
1048
1049 rt2x00_desc_read(priv_tx->desc, 6, &word);
1050 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1051 priv_tx->data_dma);
1052 rt2x00_desc_write(priv_tx->desc, 6, word);
1053
1054 rt2x00_desc_read(priv_tx->desc, 0, &word);
1055 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 1053 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1056 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 1054 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1057 rt2x00_desc_write(priv_tx->desc, 0, word); 1055 rt2x00_desc_write(entry_priv->desc, 0, word);
1058} 1056}
1059 1057
1060static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) 1058static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1061{ 1059{
1062 struct queue_entry_priv_pci_rx *priv_rx; 1060 struct queue_entry_priv_pci *entry_priv;
1063 struct queue_entry_priv_pci_tx *priv_tx;
1064 u32 reg; 1061 u32 reg;
1065 1062
1066 /* 1063 /*
@@ -1082,28 +1079,28 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1082 rt2x00dev->tx[0].desc_size / 4); 1079 rt2x00dev->tx[0].desc_size / 4);
1083 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg); 1080 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1084 1081
1085 priv_tx = rt2x00dev->tx[0].entries[0].priv_data; 1082 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1086 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg); 1083 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1087 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, 1084 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1088 priv_tx->desc_dma); 1085 entry_priv->desc_dma);
1089 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg); 1086 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1090 1087
1091 priv_tx = rt2x00dev->tx[1].entries[0].priv_data; 1088 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1092 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg); 1089 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1093 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, 1090 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1094 priv_tx->desc_dma); 1091 entry_priv->desc_dma);
1095 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg); 1092 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1096 1093
1097 priv_tx = rt2x00dev->tx[2].entries[0].priv_data; 1094 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1098 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg); 1095 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1099 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, 1096 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1100 priv_tx->desc_dma); 1097 entry_priv->desc_dma);
1101 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg); 1098 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1102 1099
1103 priv_tx = rt2x00dev->tx[3].entries[0].priv_data; 1100 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1104 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg); 1101 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1105 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, 1102 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1106 priv_tx->desc_dma); 1103 entry_priv->desc_dma);
1107 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg); 1104 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1108 1105
1109 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg); 1106 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
@@ -1113,10 +1110,10 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1113 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); 1110 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1114 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg); 1111 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1115 1112
1116 priv_rx = rt2x00dev->rx->entries[0].priv_data; 1113 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1117 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg); 1114 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1118 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, 1115 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1119 priv_rx->desc_dma); 1116 entry_priv->desc_dma);
1120 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg); 1117 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1121 1118
1122 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg); 1119 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
@@ -1294,25 +1291,32 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1294 return 0; 1291 return 0;
1295} 1292}
1296 1293
1297static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev) 1294static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1298{ 1295{
1299 unsigned int i; 1296 unsigned int i;
1300 u16 eeprom;
1301 u8 reg_id;
1302 u8 value; 1297 u8 value;
1303 1298
1304 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1299 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1305 rt61pci_bbp_read(rt2x00dev, 0, &value); 1300 rt61pci_bbp_read(rt2x00dev, 0, &value);
1306 if ((value != 0xff) && (value != 0x00)) 1301 if ((value != 0xff) && (value != 0x00))
1307 goto continue_csr_init; 1302 return 0;
1308 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1309 udelay(REGISTER_BUSY_DELAY); 1303 udelay(REGISTER_BUSY_DELAY);
1310 } 1304 }
1311 1305
1312 ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); 1306 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1313 return -EACCES; 1307 return -EACCES;
1308}
1309
1310static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1311{
1312 unsigned int i;
1313 u16 eeprom;
1314 u8 reg_id;
1315 u8 value;
1316
1317 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1318 return -EACCES;
1314 1319
1315continue_csr_init:
1316 rt61pci_bbp_write(rt2x00dev, 3, 0x00); 1320 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1317 rt61pci_bbp_write(rt2x00dev, 15, 0x30); 1321 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1318 rt61pci_bbp_write(rt2x00dev, 21, 0xc8); 1322 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
@@ -1361,7 +1365,8 @@ static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1361 1365
1362 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg); 1366 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1363 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1367 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1364 state == STATE_RADIO_RX_OFF); 1368 (state == STATE_RADIO_RX_OFF) ||
1369 (state == STATE_RADIO_RX_OFF_LINK));
1365 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 1370 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1366} 1371}
1367 1372
@@ -1413,17 +1418,10 @@ static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1413 /* 1418 /*
1414 * Initialize all registers. 1419 * Initialize all registers.
1415 */ 1420 */
1416 if (rt61pci_init_queues(rt2x00dev) || 1421 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1417 rt61pci_init_registers(rt2x00dev) || 1422 rt61pci_init_registers(rt2x00dev) ||
1418 rt61pci_init_bbp(rt2x00dev)) { 1423 rt61pci_init_bbp(rt2x00dev)))
1419 ERROR(rt2x00dev, "Register initialization failed.\n");
1420 return -EIO; 1424 return -EIO;
1421 }
1422
1423 /*
1424 * Enable interrupts.
1425 */
1426 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1427 1425
1428 /* 1426 /*
1429 * Enable RX. 1427 * Enable RX.
@@ -1455,11 +1453,6 @@ static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1455 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1); 1453 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1456 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1); 1454 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1457 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1455 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1458
1459 /*
1460 * Disable interrupts.
1461 */
1462 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1463} 1456}
1464 1457
1465static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) 1458static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
@@ -1467,7 +1460,6 @@ static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1467 u32 reg; 1460 u32 reg;
1468 unsigned int i; 1461 unsigned int i;
1469 char put_to_sleep; 1462 char put_to_sleep;
1470 char current_state;
1471 1463
1472 put_to_sleep = (state != STATE_AWAKE); 1464 put_to_sleep = (state != STATE_AWAKE);
1473 1465
@@ -1483,16 +1475,12 @@ static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1483 */ 1475 */
1484 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1476 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1485 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg); 1477 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1486 current_state = 1478 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1487 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE); 1479 if (state == !put_to_sleep)
1488 if (current_state == !put_to_sleep)
1489 return 0; 1480 return 0;
1490 msleep(10); 1481 msleep(10);
1491 } 1482 }
1492 1483
1493 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1494 "current device state %d.\n", !put_to_sleep, current_state);
1495
1496 return -EBUSY; 1484 return -EBUSY;
1497} 1485}
1498 1486
@@ -1510,11 +1498,13 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1510 break; 1498 break;
1511 case STATE_RADIO_RX_ON: 1499 case STATE_RADIO_RX_ON:
1512 case STATE_RADIO_RX_ON_LINK: 1500 case STATE_RADIO_RX_ON_LINK:
1513 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1514 break;
1515 case STATE_RADIO_RX_OFF: 1501 case STATE_RADIO_RX_OFF:
1516 case STATE_RADIO_RX_OFF_LINK: 1502 case STATE_RADIO_RX_OFF_LINK:
1517 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); 1503 rt61pci_toggle_rx(rt2x00dev, state);
1504 break;
1505 case STATE_RADIO_IRQ_ON:
1506 case STATE_RADIO_IRQ_OFF:
1507 rt61pci_toggle_irq(rt2x00dev, state);
1518 break; 1508 break;
1519 case STATE_DEEP_SLEEP: 1509 case STATE_DEEP_SLEEP:
1520 case STATE_SLEEP: 1510 case STATE_SLEEP:
@@ -1527,6 +1517,10 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1527 break; 1517 break;
1528 } 1518 }
1529 1519
1520 if (unlikely(retval))
1521 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1522 state, retval);
1523
1530 return retval; 1524 return retval;
1531} 1525}
1532 1526
@@ -1535,8 +1529,7 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1535 */ 1529 */
1536static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1530static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1537 struct sk_buff *skb, 1531 struct sk_buff *skb,
1538 struct txentry_desc *txdesc, 1532 struct txentry_desc *txdesc)
1539 struct ieee80211_tx_control *control)
1540{ 1533{
1541 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1534 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1542 __le32 *txd = skbdesc->desc; 1535 __le32 *txd = skbdesc->desc;
@@ -1552,6 +1545,7 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1552 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); 1545 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1553 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER); 1546 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1554 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1); 1547 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1548 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1555 rt2x00_desc_write(txd, 1, word); 1549 rt2x00_desc_write(txd, 1, word);
1556 1550
1557 rt2x00_desc_read(txd, 2, &word); 1551 rt2x00_desc_read(txd, 2, &word);
@@ -1562,14 +1556,22 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1562 rt2x00_desc_write(txd, 2, word); 1556 rt2x00_desc_write(txd, 2, word);
1563 1557
1564 rt2x00_desc_read(txd, 5, &word); 1558 rt2x00_desc_read(txd, 5, &word);
1559 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1560 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1561 skbdesc->entry->entry_idx);
1565 rt2x00_set_field32(&word, TXD_W5_TX_POWER, 1562 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1566 TXPOWER_TO_DEV(rt2x00dev->tx_power)); 1563 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1567 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); 1564 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1568 rt2x00_desc_write(txd, 5, word); 1565 rt2x00_desc_write(txd, 5, word);
1569 1566
1567 rt2x00_desc_read(txd, 6, &word);
1568 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1569 skbdesc->skb_dma);
1570 rt2x00_desc_write(txd, 6, word);
1571
1570 if (skbdesc->desc_len > TXINFO_SIZE) { 1572 if (skbdesc->desc_len > TXINFO_SIZE) {
1571 rt2x00_desc_read(txd, 11, &word); 1573 rt2x00_desc_read(txd, 11, &word);
1572 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len); 1574 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1573 rt2x00_desc_write(txd, 11, word); 1575 rt2x00_desc_write(txd, 11, word);
1574 } 1576 }
1575 1577
@@ -1586,10 +1588,9 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1586 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags)); 1588 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1587 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1589 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1588 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1590 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1589 !!(control->flags & 1591 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1590 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1591 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0); 1592 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1592 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len); 1593 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1593 rt2x00_set_field32(&word, TXD_W0_BURST, 1594 rt2x00_set_field32(&word, TXD_W0_BURST,
1594 test_bit(ENTRY_TXD_BURST, &txdesc->flags)); 1595 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1595 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); 1596 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
@@ -1599,12 +1600,47 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1599/* 1600/*
1600 * TX data initialization 1601 * TX data initialization
1601 */ 1602 */
1603static void rt61pci_write_beacon(struct queue_entry *entry)
1604{
1605 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1606 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1607 unsigned int beacon_base;
1608 u32 reg;
1609
1610 /*
1611 * Disable beaconing while we are reloading the beacon data,
1612 * otherwise we might be sending out invalid data.
1613 */
1614 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1615 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1616 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1617 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1618 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1619
1620 /*
1621 * Write entire beacon with descriptor to register.
1622 */
1623 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1624 rt2x00pci_register_multiwrite(rt2x00dev,
1625 beacon_base,
1626 skbdesc->desc, skbdesc->desc_len);
1627 rt2x00pci_register_multiwrite(rt2x00dev,
1628 beacon_base + skbdesc->desc_len,
1629 entry->skb->data, entry->skb->len);
1630
1631 /*
1632 * Clean up beacon skb.
1633 */
1634 dev_kfree_skb_any(entry->skb);
1635 entry->skb = NULL;
1636}
1637
1602static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1638static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1603 const unsigned int queue) 1639 const enum data_queue_qid queue)
1604{ 1640{
1605 u32 reg; 1641 u32 reg;
1606 1642
1607 if (queue == RT2X00_BCN_QUEUE_BEACON) { 1643 if (queue == QID_BEACON) {
1608 /* 1644 /*
1609 * For Wi-Fi faily generated beacons between participating 1645 * For Wi-Fi faily generated beacons between participating
1610 * stations. Set TBTT phase adaptive adjustment step to 8us. 1646 * stations. Set TBTT phase adaptive adjustment step to 8us.
@@ -1622,14 +1658,10 @@ static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1622 } 1658 }
1623 1659
1624 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 1660 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1625 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1661 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1626 (queue == IEEE80211_TX_QUEUE_DATA0)); 1662 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1627 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1663 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1628 (queue == IEEE80211_TX_QUEUE_DATA1)); 1664 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1629 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1630 (queue == IEEE80211_TX_QUEUE_DATA2));
1631 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1632 (queue == IEEE80211_TX_QUEUE_DATA3));
1633 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1665 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1634} 1666}
1635 1667
@@ -1680,14 +1712,13 @@ static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1680static void rt61pci_fill_rxdone(struct queue_entry *entry, 1712static void rt61pci_fill_rxdone(struct queue_entry *entry,
1681 struct rxdone_entry_desc *rxdesc) 1713 struct rxdone_entry_desc *rxdesc)
1682{ 1714{
1683 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 1715 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1684 u32 word0; 1716 u32 word0;
1685 u32 word1; 1717 u32 word1;
1686 1718
1687 rt2x00_desc_read(priv_rx->desc, 0, &word0); 1719 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1688 rt2x00_desc_read(priv_rx->desc, 1, &word1); 1720 rt2x00_desc_read(entry_priv->desc, 1, &word1);
1689 1721
1690 rxdesc->flags = 0;
1691 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1722 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1692 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1723 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1693 1724
@@ -1701,7 +1732,6 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry,
1701 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1); 1732 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1702 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1733 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1703 1734
1704 rxdesc->dev_flags = 0;
1705 if (rt2x00_get_field32(word0, RXD_W0_OFDM)) 1735 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1706 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; 1736 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1707 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 1737 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
@@ -1716,7 +1746,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1716 struct data_queue *queue; 1746 struct data_queue *queue;
1717 struct queue_entry *entry; 1747 struct queue_entry *entry;
1718 struct queue_entry *entry_done; 1748 struct queue_entry *entry_done;
1719 struct queue_entry_priv_pci_tx *priv_tx; 1749 struct queue_entry_priv_pci *entry_priv;
1720 struct txdone_entry_desc txdesc; 1750 struct txdone_entry_desc txdesc;
1721 u32 word; 1751 u32 word;
1722 u32 reg; 1752 u32 reg;
@@ -1761,8 +1791,8 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1761 continue; 1791 continue;
1762 1792
1763 entry = &queue->entries[index]; 1793 entry = &queue->entries[index];
1764 priv_tx = entry->priv_data; 1794 entry_priv = entry->priv_data;
1765 rt2x00_desc_read(priv_tx->desc, 0, &word); 1795 rt2x00_desc_read(entry_priv->desc, 0, &word);
1766 1796
1767 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1797 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1768 !rt2x00_get_field32(word, TXD_W0_VALID)) 1798 !rt2x00_get_field32(word, TXD_W0_VALID))
@@ -1777,20 +1807,31 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1777 "TX status report missed for entry %d\n", 1807 "TX status report missed for entry %d\n",
1778 entry_done->entry_idx); 1808 entry_done->entry_idx);
1779 1809
1780 txdesc.status = TX_FAIL_OTHER; 1810 txdesc.flags = 0;
1811 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
1781 txdesc.retry = 0; 1812 txdesc.retry = 0;
1782 1813
1783 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc); 1814 rt2x00lib_txdone(entry_done, &txdesc);
1784 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1815 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1785 } 1816 }
1786 1817
1787 /* 1818 /*
1788 * Obtain the status about this packet. 1819 * Obtain the status about this packet.
1789 */ 1820 */
1790 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT); 1821 txdesc.flags = 0;
1822 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
1823 case 0: /* Success, maybe with retry */
1824 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1825 break;
1826 case 6: /* Failure, excessive retries */
1827 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1828 /* Don't break, this is a failed frame! */
1829 default: /* Failure */
1830 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1831 }
1791 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); 1832 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1792 1833
1793 rt2x00pci_txdone(rt2x00dev, entry, &txdesc); 1834 rt2x00lib_txdone(entry, &txdesc);
1794 } 1835 }
1795} 1836}
1796 1837
@@ -1976,7 +2017,7 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1976 * To determine the RT chip we have to read the 2017 * To determine the RT chip we have to read the
1977 * PCI header of the device. 2018 * PCI header of the device.
1978 */ 2019 */
1979 pci_read_config_word(rt2x00dev_pci(rt2x00dev), 2020 pci_read_config_word(to_pci_dev(rt2x00dev->dev),
1980 PCI_CONFIG_HEADER_DEVICE, &device); 2021 PCI_CONFIG_HEADER_DEVICE, &device);
1981 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 2022 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1982 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 2023 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
@@ -2078,31 +2119,11 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2078 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); 2119 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2079 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE); 2120 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2080 2121
2081 rt2x00dev->led_radio.rt2x00dev = rt2x00dev; 2122 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2082 rt2x00dev->led_radio.type = LED_TYPE_RADIO; 2123 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2083 rt2x00dev->led_radio.led_dev.brightness_set = 2124 if (value == LED_MODE_SIGNAL_STRENGTH)
2084 rt61pci_brightness_set; 2125 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2085 rt2x00dev->led_radio.led_dev.blink_set = 2126 LED_TYPE_QUALITY);
2086 rt61pci_blink_set;
2087 rt2x00dev->led_radio.flags = LED_INITIALIZED;
2088
2089 rt2x00dev->led_assoc.rt2x00dev = rt2x00dev;
2090 rt2x00dev->led_assoc.type = LED_TYPE_ASSOC;
2091 rt2x00dev->led_assoc.led_dev.brightness_set =
2092 rt61pci_brightness_set;
2093 rt2x00dev->led_assoc.led_dev.blink_set =
2094 rt61pci_blink_set;
2095 rt2x00dev->led_assoc.flags = LED_INITIALIZED;
2096
2097 if (value == LED_MODE_SIGNAL_STRENGTH) {
2098 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
2099 rt2x00dev->led_qual.type = LED_TYPE_QUALITY;
2100 rt2x00dev->led_qual.led_dev.brightness_set =
2101 rt61pci_brightness_set;
2102 rt2x00dev->led_qual.led_dev.blink_set =
2103 rt61pci_blink_set;
2104 rt2x00dev->led_qual.flags = LED_INITIALIZED;
2105 }
2106 2127
2107 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); 2128 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2108 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, 2129 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
@@ -2258,13 +2279,11 @@ static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2258 */ 2279 */
2259 rt2x00dev->hw->flags = 2280 rt2x00dev->hw->flags =
2260 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | 2281 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2261 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; 2282 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2283 IEEE80211_HW_SIGNAL_DBM;
2262 rt2x00dev->hw->extra_tx_headroom = 0; 2284 rt2x00dev->hw->extra_tx_headroom = 0;
2263 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2264 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2265 rt2x00dev->hw->queues = 4;
2266 2285
2267 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev); 2286 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2268 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 2287 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2269 rt2x00_eeprom_addr(rt2x00dev, 2288 rt2x00_eeprom_addr(rt2x00dev,
2270 EEPROM_MAC_ADDR_0)); 2289 EEPROM_MAC_ADDR_0));
@@ -2327,9 +2346,10 @@ static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2327 rt61pci_probe_hw_mode(rt2x00dev); 2346 rt61pci_probe_hw_mode(rt2x00dev);
2328 2347
2329 /* 2348 /*
2330 * This device requires firmware. 2349 * This device requires firmware and DMA mapped skbs.
2331 */ 2350 */
2332 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); 2351 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2352 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2333 2353
2334 /* 2354 /*
2335 * Set the rssi offset. 2355 * Set the rssi offset.
@@ -2370,67 +2390,6 @@ static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2370 return tsf; 2390 return tsf;
2371} 2391}
2372 2392
2373static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2374 struct ieee80211_tx_control *control)
2375{
2376 struct rt2x00_dev *rt2x00dev = hw->priv;
2377 struct rt2x00_intf *intf = vif_to_intf(control->vif);
2378 struct queue_entry_priv_pci_tx *priv_tx;
2379 struct skb_frame_desc *skbdesc;
2380 unsigned int beacon_base;
2381 u32 reg;
2382
2383 if (unlikely(!intf->beacon))
2384 return -ENOBUFS;
2385
2386 priv_tx = intf->beacon->priv_data;
2387 memset(priv_tx->desc, 0, intf->beacon->queue->desc_size);
2388
2389 /*
2390 * Fill in skb descriptor
2391 */
2392 skbdesc = get_skb_frame_desc(skb);
2393 memset(skbdesc, 0, sizeof(*skbdesc));
2394 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2395 skbdesc->data = skb->data;
2396 skbdesc->data_len = skb->len;
2397 skbdesc->desc = priv_tx->desc;
2398 skbdesc->desc_len = intf->beacon->queue->desc_size;
2399 skbdesc->entry = intf->beacon;
2400
2401 /*
2402 * Disable beaconing while we are reloading the beacon data,
2403 * otherwise we might be sending out invalid data.
2404 */
2405 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2406 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2407 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2408 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2409 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2410
2411 /*
2412 * mac80211 doesn't provide the control->queue variable
2413 * for beacons. Set our own queue identification so
2414 * it can be used during descriptor initialization.
2415 */
2416 control->queue = RT2X00_BCN_QUEUE_BEACON;
2417 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2418
2419 /*
2420 * Write entire beacon with descriptor to register,
2421 * and kick the beacon generator.
2422 */
2423 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2424 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2425 skbdesc->desc, skbdesc->desc_len);
2426 rt2x00pci_register_multiwrite(rt2x00dev,
2427 beacon_base + skbdesc->desc_len,
2428 skbdesc->data, skbdesc->data_len);
2429 rt61pci_kick_tx_queue(rt2x00dev, control->queue);
2430
2431 return 0;
2432}
2433
2434static const struct ieee80211_ops rt61pci_mac80211_ops = { 2393static const struct ieee80211_ops rt61pci_mac80211_ops = {
2435 .tx = rt2x00mac_tx, 2394 .tx = rt2x00mac_tx,
2436 .start = rt2x00mac_start, 2395 .start = rt2x00mac_start,
@@ -2446,7 +2405,6 @@ static const struct ieee80211_ops rt61pci_mac80211_ops = {
2446 .conf_tx = rt2x00mac_conf_tx, 2405 .conf_tx = rt2x00mac_conf_tx,
2447 .get_tx_stats = rt2x00mac_get_tx_stats, 2406 .get_tx_stats = rt2x00mac_get_tx_stats,
2448 .get_tsf = rt61pci_get_tsf, 2407 .get_tsf = rt61pci_get_tsf,
2449 .beacon_update = rt61pci_beacon_update,
2450}; 2408};
2451 2409
2452static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { 2410static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
@@ -2466,6 +2424,7 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2466 .link_tuner = rt61pci_link_tuner, 2424 .link_tuner = rt61pci_link_tuner,
2467 .write_tx_desc = rt61pci_write_tx_desc, 2425 .write_tx_desc = rt61pci_write_tx_desc,
2468 .write_tx_data = rt2x00pci_write_tx_data, 2426 .write_tx_data = rt2x00pci_write_tx_data,
2427 .write_beacon = rt61pci_write_beacon,
2469 .kick_tx_queue = rt61pci_kick_tx_queue, 2428 .kick_tx_queue = rt61pci_kick_tx_queue,
2470 .fill_rxdone = rt61pci_fill_rxdone, 2429 .fill_rxdone = rt61pci_fill_rxdone,
2471 .config_filter = rt61pci_config_filter, 2430 .config_filter = rt61pci_config_filter,
@@ -2478,21 +2437,21 @@ static const struct data_queue_desc rt61pci_queue_rx = {
2478 .entry_num = RX_ENTRIES, 2437 .entry_num = RX_ENTRIES,
2479 .data_size = DATA_FRAME_SIZE, 2438 .data_size = DATA_FRAME_SIZE,
2480 .desc_size = RXD_DESC_SIZE, 2439 .desc_size = RXD_DESC_SIZE,
2481 .priv_size = sizeof(struct queue_entry_priv_pci_rx), 2440 .priv_size = sizeof(struct queue_entry_priv_pci),
2482}; 2441};
2483 2442
2484static const struct data_queue_desc rt61pci_queue_tx = { 2443static const struct data_queue_desc rt61pci_queue_tx = {
2485 .entry_num = TX_ENTRIES, 2444 .entry_num = TX_ENTRIES,
2486 .data_size = DATA_FRAME_SIZE, 2445 .data_size = DATA_FRAME_SIZE,
2487 .desc_size = TXD_DESC_SIZE, 2446 .desc_size = TXD_DESC_SIZE,
2488 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 2447 .priv_size = sizeof(struct queue_entry_priv_pci),
2489}; 2448};
2490 2449
2491static const struct data_queue_desc rt61pci_queue_bcn = { 2450static const struct data_queue_desc rt61pci_queue_bcn = {
2492 .entry_num = 4 * BEACON_ENTRIES, 2451 .entry_num = 4 * BEACON_ENTRIES,
2493 .data_size = 0, /* No DMA required for beacons */ 2452 .data_size = 0, /* No DMA required for beacons */
2494 .desc_size = TXINFO_SIZE, 2453 .desc_size = TXINFO_SIZE,
2495 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 2454 .priv_size = sizeof(struct queue_entry_priv_pci),
2496}; 2455};
2497 2456
2498static const struct rt2x00_ops rt61pci_ops = { 2457static const struct rt2x00_ops rt61pci_ops = {
@@ -2501,6 +2460,7 @@ static const struct rt2x00_ops rt61pci_ops = {
2501 .max_ap_intf = 4, 2460 .max_ap_intf = 4,
2502 .eeprom_size = EEPROM_SIZE, 2461 .eeprom_size = EEPROM_SIZE,
2503 .rf_size = RF_SIZE, 2462 .rf_size = RF_SIZE,
2463 .tx_queues = NUM_TX_QUEUES,
2504 .rx = &rt61pci_queue_rx, 2464 .rx = &rt61pci_queue_rx,
2505 .tx = &rt61pci_queue_tx, 2465 .tx = &rt61pci_queue_tx,
2506 .bcn = &rt61pci_queue_bcn, 2466 .bcn = &rt61pci_queue_bcn,
diff --git a/drivers/net/wireless/rt2x00/rt61pci.h b/drivers/net/wireless/rt2x00/rt61pci.h
index 3511bba7ff65..1004d5b899e6 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.h
+++ b/drivers/net/wireless/rt2x00/rt61pci.h
@@ -39,8 +39,6 @@
39 * Signal information. 39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion. 40 * Defaul offset is required for RSSI <-> dBm conversion.
41 */ 41 */
42#define MAX_SIGNAL 100
43#define MAX_RX_SSI -1
44#define DEFAULT_RSSI_OFFSET 120 42#define DEFAULT_RSSI_OFFSET 120
45 43
46/* 44/*
@@ -54,6 +52,11 @@
54#define RF_SIZE 0x0014 52#define RF_SIZE 0x0014
55 53
56/* 54/*
55 * Number of TX queues.
56 */
57#define NUM_TX_QUEUES 4
58
59/*
57 * PCI registers. 60 * PCI registers.
58 */ 61 */
59 62
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index 6a62d6bb96fe..d383735ab8f2 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -74,10 +74,10 @@ static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
74 const unsigned int offset, 74 const unsigned int offset,
75 void *value, const u32 length) 75 void *value, const u32 length)
76{ 76{
77 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
78 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ, 77 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
79 USB_VENDOR_REQUEST_IN, offset, 78 USB_VENDOR_REQUEST_IN, offset,
80 value, length, timeout); 79 value, length,
80 REGISTER_TIMEOUT32(length));
81} 81}
82 82
83static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev, 83static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
@@ -102,10 +102,10 @@ static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
102 const unsigned int offset, 102 const unsigned int offset,
103 void *value, const u32 length) 103 void *value, const u32 length)
104{ 104{
105 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
106 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE, 105 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
107 USB_VENDOR_REQUEST_OUT, offset, 106 USB_VENDOR_REQUEST_OUT, offset,
108 value, length, timeout); 107 value, length,
108 REGISTER_TIMEOUT32(length));
109} 109}
110 110
111static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev) 111static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
@@ -341,6 +341,17 @@ static int rt73usb_blink_set(struct led_classdev *led_cdev,
341 341
342 return 0; 342 return 0;
343} 343}
344
345static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
346 struct rt2x00_led *led,
347 enum led_type type)
348{
349 led->rt2x00dev = rt2x00dev;
350 led->type = type;
351 led->led_dev.brightness_set = rt73usb_brightness_set;
352 led->led_dev.blink_set = rt73usb_blink_set;
353 led->flags = LED_INITIALIZED;
354}
344#endif /* CONFIG_RT73USB_LEDS */ 355#endif /* CONFIG_RT73USB_LEDS */
345 356
346/* 357/*
@@ -882,7 +893,6 @@ static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
882 const char *ptr = data; 893 const char *ptr = data;
883 char *cache; 894 char *cache;
884 int buflen; 895 int buflen;
885 int timeout;
886 896
887 /* 897 /*
888 * Wait for stable hardware. 898 * Wait for stable hardware.
@@ -913,14 +923,14 @@ static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
913 923
914 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) { 924 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
915 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE); 925 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
916 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
917 926
918 memcpy(cache, ptr, buflen); 927 memcpy(cache, ptr, buflen);
919 928
920 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE, 929 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
921 USB_VENDOR_REQUEST_OUT, 930 USB_VENDOR_REQUEST_OUT,
922 FIRMWARE_IMAGE_BASE + i, 0, 931 FIRMWARE_IMAGE_BASE + i, 0,
923 cache, buflen, timeout); 932 cache, buflen,
933 REGISTER_TIMEOUT32(buflen));
924 934
925 ptr += buflen; 935 ptr += buflen;
926 } 936 }
@@ -1100,25 +1110,32 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1100 return 0; 1110 return 0;
1101} 1111}
1102 1112
1103static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev) 1113static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1104{ 1114{
1105 unsigned int i; 1115 unsigned int i;
1106 u16 eeprom;
1107 u8 reg_id;
1108 u8 value; 1116 u8 value;
1109 1117
1110 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1118 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1111 rt73usb_bbp_read(rt2x00dev, 0, &value); 1119 rt73usb_bbp_read(rt2x00dev, 0, &value);
1112 if ((value != 0xff) && (value != 0x00)) 1120 if ((value != 0xff) && (value != 0x00))
1113 goto continue_csr_init; 1121 return 0;
1114 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1115 udelay(REGISTER_BUSY_DELAY); 1122 udelay(REGISTER_BUSY_DELAY);
1116 } 1123 }
1117 1124
1118 ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); 1125 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1119 return -EACCES; 1126 return -EACCES;
1127}
1128
1129static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1130{
1131 unsigned int i;
1132 u16 eeprom;
1133 u8 reg_id;
1134 u8 value;
1135
1136 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1137 return -EACCES;
1120 1138
1121continue_csr_init:
1122 rt73usb_bbp_write(rt2x00dev, 3, 0x80); 1139 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1123 rt73usb_bbp_write(rt2x00dev, 15, 0x30); 1140 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1124 rt73usb_bbp_write(rt2x00dev, 21, 0xc8); 1141 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
@@ -1168,7 +1185,8 @@ static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1168 1185
1169 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 1186 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1170 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1187 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1171 state == STATE_RADIO_RX_OFF); 1188 (state == STATE_RADIO_RX_OFF) ||
1189 (state == STATE_RADIO_RX_OFF_LINK));
1172 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 1190 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1173} 1191}
1174 1192
@@ -1177,11 +1195,9 @@ static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1177 /* 1195 /*
1178 * Initialize all registers. 1196 * Initialize all registers.
1179 */ 1197 */
1180 if (rt73usb_init_registers(rt2x00dev) || 1198 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1181 rt73usb_init_bbp(rt2x00dev)) { 1199 rt73usb_init_bbp(rt2x00dev)))
1182 ERROR(rt2x00dev, "Register initialization failed.\n");
1183 return -EIO; 1200 return -EIO;
1184 }
1185 1201
1186 return 0; 1202 return 0;
1187} 1203}
@@ -1203,7 +1219,6 @@ static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1203 u32 reg; 1219 u32 reg;
1204 unsigned int i; 1220 unsigned int i;
1205 char put_to_sleep; 1221 char put_to_sleep;
1206 char current_state;
1207 1222
1208 put_to_sleep = (state != STATE_AWAKE); 1223 put_to_sleep = (state != STATE_AWAKE);
1209 1224
@@ -1219,16 +1234,12 @@ static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1219 */ 1234 */
1220 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1235 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1221 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg); 1236 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1222 current_state = 1237 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1223 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE); 1238 if (state == !put_to_sleep)
1224 if (current_state == !put_to_sleep)
1225 return 0; 1239 return 0;
1226 msleep(10); 1240 msleep(10);
1227 } 1241 }
1228 1242
1229 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1230 "current device state %d.\n", !put_to_sleep, current_state);
1231
1232 return -EBUSY; 1243 return -EBUSY;
1233} 1244}
1234 1245
@@ -1246,11 +1257,13 @@ static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1246 break; 1257 break;
1247 case STATE_RADIO_RX_ON: 1258 case STATE_RADIO_RX_ON:
1248 case STATE_RADIO_RX_ON_LINK: 1259 case STATE_RADIO_RX_ON_LINK:
1249 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1250 break;
1251 case STATE_RADIO_RX_OFF: 1260 case STATE_RADIO_RX_OFF:
1252 case STATE_RADIO_RX_OFF_LINK: 1261 case STATE_RADIO_RX_OFF_LINK:
1253 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); 1262 rt73usb_toggle_rx(rt2x00dev, state);
1263 break;
1264 case STATE_RADIO_IRQ_ON:
1265 case STATE_RADIO_IRQ_OFF:
1266 /* No support, but no error either */
1254 break; 1267 break;
1255 case STATE_DEEP_SLEEP: 1268 case STATE_DEEP_SLEEP:
1256 case STATE_SLEEP: 1269 case STATE_SLEEP:
@@ -1263,6 +1276,10 @@ static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1263 break; 1276 break;
1264 } 1277 }
1265 1278
1279 if (unlikely(retval))
1280 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1281 state, retval);
1282
1266 return retval; 1283 return retval;
1267} 1284}
1268 1285
@@ -1271,8 +1288,7 @@ static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1271 */ 1288 */
1272static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1289static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1273 struct sk_buff *skb, 1290 struct sk_buff *skb,
1274 struct txentry_desc *txdesc, 1291 struct txentry_desc *txdesc)
1275 struct ieee80211_tx_control *control)
1276{ 1292{
1277 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1293 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1278 __le32 *txd = skbdesc->desc; 1294 __le32 *txd = skbdesc->desc;
@@ -1317,16 +1333,59 @@ static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1317 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags)); 1333 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1318 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1334 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1319 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1335 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1320 !!(control->flags & 1336 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1321 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1322 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0); 1337 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1323 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len); 1338 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT,
1339 skb->len - skbdesc->desc_len);
1324 rt2x00_set_field32(&word, TXD_W0_BURST2, 1340 rt2x00_set_field32(&word, TXD_W0_BURST2,
1325 test_bit(ENTRY_TXD_BURST, &txdesc->flags)); 1341 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1326 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); 1342 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1327 rt2x00_desc_write(txd, 0, word); 1343 rt2x00_desc_write(txd, 0, word);
1328} 1344}
1329 1345
1346/*
1347 * TX data initialization
1348 */
1349static void rt73usb_write_beacon(struct queue_entry *entry)
1350{
1351 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1352 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1353 unsigned int beacon_base;
1354 u32 reg;
1355
1356 /*
1357 * Add the descriptor in front of the skb.
1358 */
1359 skb_push(entry->skb, entry->queue->desc_size);
1360 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1361 skbdesc->desc = entry->skb->data;
1362
1363 /*
1364 * Disable beaconing while we are reloading the beacon data,
1365 * otherwise we might be sending out invalid data.
1366 */
1367 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1368 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1369 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1370 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1371 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1372
1373 /*
1374 * Write entire beacon with descriptor to register.
1375 */
1376 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1377 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
1378 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
1379 entry->skb->data, entry->skb->len,
1380 REGISTER_TIMEOUT32(entry->skb->len));
1381
1382 /*
1383 * Clean up the beacon skb.
1384 */
1385 dev_kfree_skb(entry->skb);
1386 entry->skb = NULL;
1387}
1388
1330static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev, 1389static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1331 struct sk_buff *skb) 1390 struct sk_buff *skb)
1332{ 1391{
@@ -1342,16 +1401,15 @@ static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1342 return length; 1401 return length;
1343} 1402}
1344 1403
1345/*
1346 * TX data initialization
1347 */
1348static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1404static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1349 const unsigned int queue) 1405 const enum data_queue_qid queue)
1350{ 1406{
1351 u32 reg; 1407 u32 reg;
1352 1408
1353 if (queue != RT2X00_BCN_QUEUE_BEACON) 1409 if (queue != QID_BEACON) {
1410 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1354 return; 1411 return;
1412 }
1355 1413
1356 /* 1414 /*
1357 * For Wi-Fi faily generated beacons between participating stations. 1415 * For Wi-Fi faily generated beacons between participating stations.
@@ -1421,25 +1479,22 @@ static void rt73usb_fill_rxdone(struct queue_entry *entry,
1421{ 1479{
1422 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1480 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1423 __le32 *rxd = (__le32 *)entry->skb->data; 1481 __le32 *rxd = (__le32 *)entry->skb->data;
1424 unsigned int offset = entry->queue->desc_size + 2;
1425 u32 word0; 1482 u32 word0;
1426 u32 word1; 1483 u32 word1;
1427 1484
1428 /* 1485 /*
1429 * Copy descriptor to the available headroom inside the skbuffer. 1486 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1487 * frame data in rt2x00usb.
1430 */ 1488 */
1431 skb_push(entry->skb, offset); 1489 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1432 memcpy(entry->skb->data, rxd, entry->queue->desc_size); 1490 rxd = (__le32 *)skbdesc->desc;
1433 rxd = (__le32 *)entry->skb->data;
1434 1491
1435 /* 1492 /*
1436 * The descriptor is now aligned to 4 bytes and thus it is 1493 * It is now safe to read the descriptor on all architectures.
1437 * now safe to read it on all architectures.
1438 */ 1494 */
1439 rt2x00_desc_read(rxd, 0, &word0); 1495 rt2x00_desc_read(rxd, 0, &word0);
1440 rt2x00_desc_read(rxd, 1, &word1); 1496 rt2x00_desc_read(rxd, 1, &word1);
1441 1497
1442 rxdesc->flags = 0;
1443 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1498 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1444 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1499 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1445 1500
@@ -1453,25 +1508,16 @@ static void rt73usb_fill_rxdone(struct queue_entry *entry,
1453 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1); 1508 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
1454 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1509 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1455 1510
1456 rxdesc->dev_flags = 0;
1457 if (rt2x00_get_field32(word0, RXD_W0_OFDM)) 1511 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1458 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; 1512 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1459 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 1513 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1460 rxdesc->dev_flags |= RXDONE_MY_BSS; 1514 rxdesc->dev_flags |= RXDONE_MY_BSS;
1461 1515
1462 /* 1516 /*
1463 * Adjust the skb memory window to the frame boundaries. 1517 * Set skb pointers, and update frame information.
1464 */ 1518 */
1465 skb_pull(entry->skb, offset + entry->queue->desc_size); 1519 skb_pull(entry->skb, entry->queue->desc_size);
1466 skb_trim(entry->skb, rxdesc->size); 1520 skb_trim(entry->skb, rxdesc->size);
1467
1468 /*
1469 * Set descriptor and data pointer.
1470 */
1471 skbdesc->data = entry->skb->data;
1472 skbdesc->data_len = rxdesc->size;
1473 skbdesc->desc = rxd;
1474 skbdesc->desc_len = entry->queue->desc_size;
1475} 1521}
1476 1522
1477/* 1523/*
@@ -1644,31 +1690,11 @@ static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1644#ifdef CONFIG_RT73USB_LEDS 1690#ifdef CONFIG_RT73USB_LEDS
1645 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); 1691 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1646 1692
1647 rt2x00dev->led_radio.rt2x00dev = rt2x00dev; 1693 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1648 rt2x00dev->led_radio.type = LED_TYPE_RADIO; 1694 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1649 rt2x00dev->led_radio.led_dev.brightness_set = 1695 if (value == LED_MODE_SIGNAL_STRENGTH)
1650 rt73usb_brightness_set; 1696 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1651 rt2x00dev->led_radio.led_dev.blink_set = 1697 LED_TYPE_QUALITY);
1652 rt73usb_blink_set;
1653 rt2x00dev->led_radio.flags = LED_INITIALIZED;
1654
1655 rt2x00dev->led_assoc.rt2x00dev = rt2x00dev;
1656 rt2x00dev->led_assoc.type = LED_TYPE_ASSOC;
1657 rt2x00dev->led_assoc.led_dev.brightness_set =
1658 rt73usb_brightness_set;
1659 rt2x00dev->led_assoc.led_dev.blink_set =
1660 rt73usb_blink_set;
1661 rt2x00dev->led_assoc.flags = LED_INITIALIZED;
1662
1663 if (value == LED_MODE_SIGNAL_STRENGTH) {
1664 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1665 rt2x00dev->led_qual.type = LED_TYPE_QUALITY;
1666 rt2x00dev->led_qual.led_dev.brightness_set =
1667 rt73usb_brightness_set;
1668 rt2x00dev->led_qual.led_dev.blink_set =
1669 rt73usb_blink_set;
1670 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1671 }
1672 1698
1673 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); 1699 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1674 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, 1700 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
@@ -1846,13 +1872,11 @@ static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1846 */ 1872 */
1847 rt2x00dev->hw->flags = 1873 rt2x00dev->hw->flags =
1848 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | 1874 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1849 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; 1875 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1876 IEEE80211_HW_SIGNAL_DBM;
1850 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE; 1877 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1851 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1852 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1853 rt2x00dev->hw->queues = 4;
1854 1878
1855 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev); 1879 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1856 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 1880 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1857 rt2x00_eeprom_addr(rt2x00dev, 1881 rt2x00_eeprom_addr(rt2x00dev,
1858 EEPROM_MAC_ADDR_0)); 1882 EEPROM_MAC_ADDR_0));
@@ -1974,69 +1998,6 @@ static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1974#define rt73usb_get_tsf NULL 1998#define rt73usb_get_tsf NULL
1975#endif 1999#endif
1976 2000
1977static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1978 struct ieee80211_tx_control *control)
1979{
1980 struct rt2x00_dev *rt2x00dev = hw->priv;
1981 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1982 struct skb_frame_desc *skbdesc;
1983 unsigned int beacon_base;
1984 unsigned int timeout;
1985 u32 reg;
1986
1987 if (unlikely(!intf->beacon))
1988 return -ENOBUFS;
1989
1990 /*
1991 * Add the descriptor in front of the skb.
1992 */
1993 skb_push(skb, intf->beacon->queue->desc_size);
1994 memset(skb->data, 0, intf->beacon->queue->desc_size);
1995
1996 /*
1997 * Fill in skb descriptor
1998 */
1999 skbdesc = get_skb_frame_desc(skb);
2000 memset(skbdesc, 0, sizeof(*skbdesc));
2001 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2002 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2003 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
2004 skbdesc->desc = skb->data;
2005 skbdesc->desc_len = intf->beacon->queue->desc_size;
2006 skbdesc->entry = intf->beacon;
2007
2008 /*
2009 * Disable beaconing while we are reloading the beacon data,
2010 * otherwise we might be sending out invalid data.
2011 */
2012 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
2013 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2014 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2015 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2016 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
2017
2018 /*
2019 * mac80211 doesn't provide the control->queue variable
2020 * for beacons. Set our own queue identification so
2021 * it can be used during descriptor initialization.
2022 */
2023 control->queue = RT2X00_BCN_QUEUE_BEACON;
2024 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2025
2026 /*
2027 * Write entire beacon with descriptor to register,
2028 * and kick the beacon generator.
2029 */
2030 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2031 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
2032 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
2033 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
2034 skb->data, skb->len, timeout);
2035 rt73usb_kick_tx_queue(rt2x00dev, control->queue);
2036
2037 return 0;
2038}
2039
2040static const struct ieee80211_ops rt73usb_mac80211_ops = { 2001static const struct ieee80211_ops rt73usb_mac80211_ops = {
2041 .tx = rt2x00mac_tx, 2002 .tx = rt2x00mac_tx,
2042 .start = rt2x00mac_start, 2003 .start = rt2x00mac_start,
@@ -2052,7 +2013,6 @@ static const struct ieee80211_ops rt73usb_mac80211_ops = {
2052 .conf_tx = rt2x00mac_conf_tx, 2013 .conf_tx = rt2x00mac_conf_tx,
2053 .get_tx_stats = rt2x00mac_get_tx_stats, 2014 .get_tx_stats = rt2x00mac_get_tx_stats,
2054 .get_tsf = rt73usb_get_tsf, 2015 .get_tsf = rt73usb_get_tsf,
2055 .beacon_update = rt73usb_beacon_update,
2056}; 2016};
2057 2017
2058static const struct rt2x00lib_ops rt73usb_rt2x00_ops = { 2018static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
@@ -2070,6 +2030,7 @@ static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2070 .link_tuner = rt73usb_link_tuner, 2030 .link_tuner = rt73usb_link_tuner,
2071 .write_tx_desc = rt73usb_write_tx_desc, 2031 .write_tx_desc = rt73usb_write_tx_desc,
2072 .write_tx_data = rt2x00usb_write_tx_data, 2032 .write_tx_data = rt2x00usb_write_tx_data,
2033 .write_beacon = rt73usb_write_beacon,
2073 .get_tx_data_len = rt73usb_get_tx_data_len, 2034 .get_tx_data_len = rt73usb_get_tx_data_len,
2074 .kick_tx_queue = rt73usb_kick_tx_queue, 2035 .kick_tx_queue = rt73usb_kick_tx_queue,
2075 .fill_rxdone = rt73usb_fill_rxdone, 2036 .fill_rxdone = rt73usb_fill_rxdone,
@@ -2083,21 +2044,21 @@ static const struct data_queue_desc rt73usb_queue_rx = {
2083 .entry_num = RX_ENTRIES, 2044 .entry_num = RX_ENTRIES,
2084 .data_size = DATA_FRAME_SIZE, 2045 .data_size = DATA_FRAME_SIZE,
2085 .desc_size = RXD_DESC_SIZE, 2046 .desc_size = RXD_DESC_SIZE,
2086 .priv_size = sizeof(struct queue_entry_priv_usb_rx), 2047 .priv_size = sizeof(struct queue_entry_priv_usb),
2087}; 2048};
2088 2049
2089static const struct data_queue_desc rt73usb_queue_tx = { 2050static const struct data_queue_desc rt73usb_queue_tx = {
2090 .entry_num = TX_ENTRIES, 2051 .entry_num = TX_ENTRIES,
2091 .data_size = DATA_FRAME_SIZE, 2052 .data_size = DATA_FRAME_SIZE,
2092 .desc_size = TXD_DESC_SIZE, 2053 .desc_size = TXD_DESC_SIZE,
2093 .priv_size = sizeof(struct queue_entry_priv_usb_tx), 2054 .priv_size = sizeof(struct queue_entry_priv_usb),
2094}; 2055};
2095 2056
2096static const struct data_queue_desc rt73usb_queue_bcn = { 2057static const struct data_queue_desc rt73usb_queue_bcn = {
2097 .entry_num = 4 * BEACON_ENTRIES, 2058 .entry_num = 4 * BEACON_ENTRIES,
2098 .data_size = MGMT_FRAME_SIZE, 2059 .data_size = MGMT_FRAME_SIZE,
2099 .desc_size = TXINFO_SIZE, 2060 .desc_size = TXINFO_SIZE,
2100 .priv_size = sizeof(struct queue_entry_priv_usb_tx), 2061 .priv_size = sizeof(struct queue_entry_priv_usb),
2101}; 2062};
2102 2063
2103static const struct rt2x00_ops rt73usb_ops = { 2064static const struct rt2x00_ops rt73usb_ops = {
@@ -2106,6 +2067,7 @@ static const struct rt2x00_ops rt73usb_ops = {
2106 .max_ap_intf = 4, 2067 .max_ap_intf = 4,
2107 .eeprom_size = EEPROM_SIZE, 2068 .eeprom_size = EEPROM_SIZE,
2108 .rf_size = RF_SIZE, 2069 .rf_size = RF_SIZE,
2070 .tx_queues = NUM_TX_QUEUES,
2109 .rx = &rt73usb_queue_rx, 2071 .rx = &rt73usb_queue_rx,
2110 .tx = &rt73usb_queue_tx, 2072 .tx = &rt73usb_queue_tx,
2111 .bcn = &rt73usb_queue_bcn, 2073 .bcn = &rt73usb_queue_bcn,
diff --git a/drivers/net/wireless/rt2x00/rt73usb.h b/drivers/net/wireless/rt2x00/rt73usb.h
index 06d687425fef..148493501011 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.h
+++ b/drivers/net/wireless/rt2x00/rt73usb.h
@@ -39,8 +39,6 @@
39 * Signal information. 39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion. 40 * Defaul offset is required for RSSI <-> dBm conversion.
41 */ 41 */
42#define MAX_SIGNAL 100
43#define MAX_RX_SSI -1
44#define DEFAULT_RSSI_OFFSET 120 42#define DEFAULT_RSSI_OFFSET 120
45 43
46/* 44/*
@@ -54,6 +52,11 @@
54#define RF_SIZE 0x0014 52#define RF_SIZE 0x0014
55 53
56/* 54/*
55 * Number of TX queues.
56 */
57#define NUM_TX_QUEUES 4
58
59/*
57 * USB registers. 60 * USB registers.
58 */ 61 */
59 62
diff --git a/drivers/net/wireless/rtl8180_dev.c b/drivers/net/wireless/rtl8180_dev.c
index c181f23e930d..b7172a12c057 100644
--- a/drivers/net/wireless/rtl8180_dev.c
+++ b/drivers/net/wireless/rtl8180_dev.c
@@ -132,8 +132,8 @@ static void rtl8180_handle_rx(struct ieee80211_hw *dev)
132 132
133 rx_status.antenna = (flags2 >> 15) & 1; 133 rx_status.antenna = (flags2 >> 15) & 1;
134 /* TODO: improve signal/rssi reporting */ 134 /* TODO: improve signal/rssi reporting */
135 rx_status.signal = flags2 & 0xFF; 135 rx_status.qual = flags2 & 0xFF;
136 rx_status.ssi = (flags2 >> 8) & 0x7F; 136 rx_status.signal = (flags2 >> 8) & 0x7F;
137 /* XXX: is this correct? */ 137 /* XXX: is this correct? */
138 rx_status.rate_idx = (flags >> 20) & 0xF; 138 rx_status.rate_idx = (flags >> 20) & 0xF;
139 rx_status.freq = dev->conf.channel->center_freq; 139 rx_status.freq = dev->conf.channel->center_freq;
@@ -170,34 +170,29 @@ static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
170 while (skb_queue_len(&ring->queue)) { 170 while (skb_queue_len(&ring->queue)) {
171 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx]; 171 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
172 struct sk_buff *skb; 172 struct sk_buff *skb;
173 struct ieee80211_tx_status status; 173 struct ieee80211_tx_info *info;
174 struct ieee80211_tx_control *control;
175 u32 flags = le32_to_cpu(entry->flags); 174 u32 flags = le32_to_cpu(entry->flags);
176 175
177 if (flags & RTL8180_TX_DESC_FLAG_OWN) 176 if (flags & RTL8180_TX_DESC_FLAG_OWN)
178 return; 177 return;
179 178
180 memset(&status, 0, sizeof(status));
181
182 ring->idx = (ring->idx + 1) % ring->entries; 179 ring->idx = (ring->idx + 1) % ring->entries;
183 skb = __skb_dequeue(&ring->queue); 180 skb = __skb_dequeue(&ring->queue);
184 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf), 181 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
185 skb->len, PCI_DMA_TODEVICE); 182 skb->len, PCI_DMA_TODEVICE);
186 183
187 control = *((struct ieee80211_tx_control **)skb->cb); 184 info = IEEE80211_SKB_CB(skb);
188 if (control) 185 memset(&info->status, 0, sizeof(info->status));
189 memcpy(&status.control, control, sizeof(*control));
190 kfree(control);
191 186
192 if (!(status.control.flags & IEEE80211_TXCTL_NO_ACK)) { 187 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
193 if (flags & RTL8180_TX_DESC_FLAG_TX_OK) 188 if (flags & RTL8180_TX_DESC_FLAG_TX_OK)
194 status.flags = IEEE80211_TX_STATUS_ACK; 189 info->flags |= IEEE80211_TX_STAT_ACK;
195 else 190 else
196 status.excessive_retries = 1; 191 info->status.excessive_retries = 1;
197 } 192 }
198 status.retry_count = flags & 0xFF; 193 info->status.retry_count = flags & 0xFF;
199 194
200 ieee80211_tx_status_irqsafe(dev, skb, &status); 195 ieee80211_tx_status_irqsafe(dev, skb);
201 if (ring->entries - skb_queue_len(&ring->queue) == 2) 196 if (ring->entries - skb_queue_len(&ring->queue) == 2)
202 ieee80211_wake_queue(dev, prio); 197 ieee80211_wake_queue(dev, prio);
203 } 198 }
@@ -238,9 +233,9 @@ static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
238 return IRQ_HANDLED; 233 return IRQ_HANDLED;
239} 234}
240 235
241static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb, 236static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
242 struct ieee80211_tx_control *control)
243{ 237{
238 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
244 struct rtl8180_priv *priv = dev->priv; 239 struct rtl8180_priv *priv = dev->priv;
245 struct rtl8180_tx_ring *ring; 240 struct rtl8180_tx_ring *ring;
246 struct rtl8180_tx_desc *entry; 241 struct rtl8180_tx_desc *entry;
@@ -251,46 +246,40 @@ static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
251 u16 plcp_len = 0; 246 u16 plcp_len = 0;
252 __le16 rts_duration = 0; 247 __le16 rts_duration = 0;
253 248
254 prio = control->queue; 249 prio = skb_get_queue_mapping(skb);
255 ring = &priv->tx_ring[prio]; 250 ring = &priv->tx_ring[prio];
256 251
257 mapping = pci_map_single(priv->pdev, skb->data, 252 mapping = pci_map_single(priv->pdev, skb->data,
258 skb->len, PCI_DMA_TODEVICE); 253 skb->len, PCI_DMA_TODEVICE);
259 254
260 BUG_ON(!control->tx_rate);
261
262 tx_flags = RTL8180_TX_DESC_FLAG_OWN | RTL8180_TX_DESC_FLAG_FS | 255 tx_flags = RTL8180_TX_DESC_FLAG_OWN | RTL8180_TX_DESC_FLAG_FS |
263 RTL8180_TX_DESC_FLAG_LS | 256 RTL8180_TX_DESC_FLAG_LS |
264 (control->tx_rate->hw_value << 24) | skb->len; 257 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
258 skb->len;
265 259
266 if (priv->r8185) 260 if (priv->r8185)
267 tx_flags |= RTL8180_TX_DESC_FLAG_DMA | 261 tx_flags |= RTL8180_TX_DESC_FLAG_DMA |
268 RTL8180_TX_DESC_FLAG_NO_ENC; 262 RTL8180_TX_DESC_FLAG_NO_ENC;
269 263
270 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS) { 264 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
271 BUG_ON(!control->rts_cts_rate);
272 tx_flags |= RTL8180_TX_DESC_FLAG_RTS; 265 tx_flags |= RTL8180_TX_DESC_FLAG_RTS;
273 tx_flags |= control->rts_cts_rate->hw_value << 19; 266 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
274 } else if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) { 267 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
275 BUG_ON(!control->rts_cts_rate);
276 tx_flags |= RTL8180_TX_DESC_FLAG_CTS; 268 tx_flags |= RTL8180_TX_DESC_FLAG_CTS;
277 tx_flags |= control->rts_cts_rate->hw_value << 19; 269 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
278 } 270 }
279 271
280 *((struct ieee80211_tx_control **) skb->cb) = 272 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
281 kmemdup(control, sizeof(*control), GFP_ATOMIC);
282
283 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
284 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len, 273 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
285 control); 274 info);
286 275
287 if (!priv->r8185) { 276 if (!priv->r8185) {
288 unsigned int remainder; 277 unsigned int remainder;
289 278
290 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4), 279 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
291 (control->tx_rate->bitrate * 2) / 10); 280 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
292 remainder = (16 * (skb->len + 4)) % 281 remainder = (16 * (skb->len + 4)) %
293 ((control->tx_rate->bitrate * 2) / 10); 282 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
294 if (remainder > 0 && remainder <= 6) 283 if (remainder > 0 && remainder <= 6)
295 plcp_len |= 1 << 15; 284 plcp_len |= 1 << 15;
296 } 285 }
@@ -303,13 +292,13 @@ static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
303 entry->plcp_len = cpu_to_le16(plcp_len); 292 entry->plcp_len = cpu_to_le16(plcp_len);
304 entry->tx_buf = cpu_to_le32(mapping); 293 entry->tx_buf = cpu_to_le32(mapping);
305 entry->frame_len = cpu_to_le32(skb->len); 294 entry->frame_len = cpu_to_le32(skb->len);
306 entry->flags2 = control->alt_retry_rate != NULL ? 295 entry->flags2 = info->control.alt_retry_rate_idx >= 0 ?
307 control->alt_retry_rate->bitrate << 4 : 0; 296 ieee80211_get_alt_retry_rate(dev, info)->bitrate << 4 : 0;
308 entry->retry_limit = control->retry_limit; 297 entry->retry_limit = info->control.retry_limit;
309 entry->flags = cpu_to_le32(tx_flags); 298 entry->flags = cpu_to_le32(tx_flags);
310 __skb_queue_tail(&ring->queue, skb); 299 __skb_queue_tail(&ring->queue, skb);
311 if (ring->entries - skb_queue_len(&ring->queue) < 2) 300 if (ring->entries - skb_queue_len(&ring->queue) < 2)
312 ieee80211_stop_queue(dev, control->queue); 301 ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
313 spin_unlock_irqrestore(&priv->lock, flags); 302 spin_unlock_irqrestore(&priv->lock, flags);
314 303
315 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4))); 304 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
@@ -525,7 +514,6 @@ static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
525 514
526 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf), 515 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
527 skb->len, PCI_DMA_TODEVICE); 516 skb->len, PCI_DMA_TODEVICE);
528 kfree(*((struct ieee80211_tx_control **) skb->cb));
529 kfree_skb(skb); 517 kfree_skb(skb);
530 ring->idx = (ring->idx + 1) % ring->entries; 518 ring->idx = (ring->idx + 1) % ring->entries;
531 } 519 }
@@ -894,9 +882,10 @@ static int __devinit rtl8180_probe(struct pci_dev *pdev,
894 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; 882 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
895 883
896 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 884 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
897 IEEE80211_HW_RX_INCLUDES_FCS; 885 IEEE80211_HW_RX_INCLUDES_FCS |
886 IEEE80211_HW_SIGNAL_UNSPEC;
898 dev->queues = 1; 887 dev->queues = 1;
899 dev->max_rssi = 65; 888 dev->max_signal = 65;
900 889
901 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); 890 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
902 reg &= RTL818X_TX_CONF_HWVER_MASK; 891 reg &= RTL818X_TX_CONF_HWVER_MASK;
diff --git a/drivers/net/wireless/rtl8187.h b/drivers/net/wireless/rtl8187.h
index 076d88b6db0e..3afb49f8866a 100644
--- a/drivers/net/wireless/rtl8187.h
+++ b/drivers/net/wireless/rtl8187.h
@@ -44,23 +44,48 @@ struct rtl8187_rx_hdr {
44 __le64 mac_time; 44 __le64 mac_time;
45} __attribute__((packed)); 45} __attribute__((packed));
46 46
47struct rtl8187_tx_info { 47struct rtl8187b_rx_hdr {
48 struct ieee80211_tx_control *control;
49 struct urb *urb;
50 struct ieee80211_hw *dev;
51};
52
53struct rtl8187_tx_hdr {
54 __le32 flags; 48 __le32 flags;
49 __le64 mac_time;
50 u8 noise;
51 u8 signal;
52 u8 agc;
53 u8 reserved;
54 __le32 unused;
55} __attribute__((packed));
56
57/* {rtl8187,rtl8187b}_tx_info is in skb */
58
59/* Tx flags are common between rtl8187 and rtl8187b */
55#define RTL8187_TX_FLAG_NO_ENCRYPT (1 << 15) 60#define RTL8187_TX_FLAG_NO_ENCRYPT (1 << 15)
56#define RTL8187_TX_FLAG_MORE_FRAG (1 << 17) 61#define RTL8187_TX_FLAG_MORE_FRAG (1 << 17)
57#define RTL8187_TX_FLAG_CTS (1 << 18) 62#define RTL8187_TX_FLAG_CTS (1 << 18)
58#define RTL8187_TX_FLAG_RTS (1 << 23) 63#define RTL8187_TX_FLAG_RTS (1 << 23)
64
65struct rtl8187_tx_hdr {
66 __le32 flags;
67 __le16 rts_duration;
68 __le16 len;
69 __le32 retry;
70} __attribute__((packed));
71
72struct rtl8187b_tx_hdr {
73 __le32 flags;
59 __le16 rts_duration; 74 __le16 rts_duration;
60 __le16 len; 75 __le16 len;
76 __le32 unused_1;
77 __le16 unused_2;
78 __le16 tx_duration;
79 __le32 unused_3;
61 __le32 retry; 80 __le32 retry;
81 __le32 unused_4[2];
62} __attribute__((packed)); 82} __attribute__((packed));
63 83
84enum {
85 DEVICE_RTL8187,
86 DEVICE_RTL8187B
87};
88
64struct rtl8187_priv { 89struct rtl8187_priv {
65 /* common between rtl818x drivers */ 90 /* common between rtl818x drivers */
66 struct rtl818x_csr *map; 91 struct rtl818x_csr *map;
@@ -76,70 +101,120 @@ struct rtl8187_priv {
76 u32 rx_conf; 101 u32 rx_conf;
77 u16 txpwr_base; 102 u16 txpwr_base;
78 u8 asic_rev; 103 u8 asic_rev;
104 u8 is_rtl8187b;
105 enum {
106 RTL8187BvB,
107 RTL8187BvD,
108 RTL8187BvE
109 } hw_rev;
79 struct sk_buff_head rx_queue; 110 struct sk_buff_head rx_queue;
111 u8 signal;
112 u8 quality;
113 u8 noise;
80}; 114};
81 115
82void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data); 116void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data);
83 117
84static inline u8 rtl818x_ioread8(struct rtl8187_priv *priv, u8 *addr) 118static inline u8 rtl818x_ioread8_idx(struct rtl8187_priv *priv,
119 u8 *addr, u8 idx)
85{ 120{
86 u8 val; 121 u8 val;
87 122
88 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), 123 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
89 RTL8187_REQ_GET_REG, RTL8187_REQT_READ, 124 RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
90 (unsigned long)addr, 0, &val, sizeof(val), HZ / 2); 125 (unsigned long)addr, idx & 0x03, &val,
126 sizeof(val), HZ / 2);
91 127
92 return val; 128 return val;
93} 129}
94 130
95static inline u16 rtl818x_ioread16(struct rtl8187_priv *priv, __le16 *addr) 131static inline u8 rtl818x_ioread8(struct rtl8187_priv *priv, u8 *addr)
132{
133 return rtl818x_ioread8_idx(priv, addr, 0);
134}
135
136static inline u16 rtl818x_ioread16_idx(struct rtl8187_priv *priv,
137 __le16 *addr, u8 idx)
96{ 138{
97 __le16 val; 139 __le16 val;
98 140
99 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), 141 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
100 RTL8187_REQ_GET_REG, RTL8187_REQT_READ, 142 RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
101 (unsigned long)addr, 0, &val, sizeof(val), HZ / 2); 143 (unsigned long)addr, idx & 0x03, &val,
144 sizeof(val), HZ / 2);
102 145
103 return le16_to_cpu(val); 146 return le16_to_cpu(val);
104} 147}
105 148
106static inline u32 rtl818x_ioread32(struct rtl8187_priv *priv, __le32 *addr) 149static inline u16 rtl818x_ioread16(struct rtl8187_priv *priv, __le16 *addr)
150{
151 return rtl818x_ioread16_idx(priv, addr, 0);
152}
153
154static inline u32 rtl818x_ioread32_idx(struct rtl8187_priv *priv,
155 __le32 *addr, u8 idx)
107{ 156{
108 __le32 val; 157 __le32 val;
109 158
110 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), 159 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
111 RTL8187_REQ_GET_REG, RTL8187_REQT_READ, 160 RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
112 (unsigned long)addr, 0, &val, sizeof(val), HZ / 2); 161 (unsigned long)addr, idx & 0x03, &val,
162 sizeof(val), HZ / 2);
113 163
114 return le32_to_cpu(val); 164 return le32_to_cpu(val);
115} 165}
116 166
117static inline void rtl818x_iowrite8(struct rtl8187_priv *priv, 167static inline u32 rtl818x_ioread32(struct rtl8187_priv *priv, __le32 *addr)
118 u8 *addr, u8 val) 168{
169 return rtl818x_ioread32_idx(priv, addr, 0);
170}
171
172static inline void rtl818x_iowrite8_idx(struct rtl8187_priv *priv,
173 u8 *addr, u8 val, u8 idx)
119{ 174{
120 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0), 175 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
121 RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE, 176 RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
122 (unsigned long)addr, 0, &val, sizeof(val), HZ / 2); 177 (unsigned long)addr, idx & 0x03, &val,
178 sizeof(val), HZ / 2);
179}
180
181static inline void rtl818x_iowrite8(struct rtl8187_priv *priv, u8 *addr, u8 val)
182{
183 rtl818x_iowrite8_idx(priv, addr, val, 0);
123} 184}
124 185
125static inline void rtl818x_iowrite16(struct rtl8187_priv *priv, 186static inline void rtl818x_iowrite16_idx(struct rtl8187_priv *priv,
126 __le16 *addr, u16 val) 187 __le16 *addr, u16 val, u8 idx)
127{ 188{
128 __le16 buf = cpu_to_le16(val); 189 __le16 buf = cpu_to_le16(val);
129 190
130 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0), 191 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
131 RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE, 192 RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
132 (unsigned long)addr, 0, &buf, sizeof(buf), HZ / 2); 193 (unsigned long)addr, idx & 0x03, &buf, sizeof(buf),
194 HZ / 2);
133} 195}
134 196
135static inline void rtl818x_iowrite32(struct rtl8187_priv *priv, 197static inline void rtl818x_iowrite16(struct rtl8187_priv *priv, __le16 *addr,
136 __le32 *addr, u32 val) 198 u16 val)
199{
200 rtl818x_iowrite16_idx(priv, addr, val, 0);
201}
202
203static inline void rtl818x_iowrite32_idx(struct rtl8187_priv *priv,
204 __le32 *addr, u32 val, u8 idx)
137{ 205{
138 __le32 buf = cpu_to_le32(val); 206 __le32 buf = cpu_to_le32(val);
139 207
140 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0), 208 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
141 RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE, 209 RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
142 (unsigned long)addr, 0, &buf, sizeof(buf), HZ / 2); 210 (unsigned long)addr, idx & 0x03, &buf, sizeof(buf),
211 HZ / 2);
212}
213
214static inline void rtl818x_iowrite32(struct rtl8187_priv *priv, __le32 *addr,
215 u32 val)
216{
217 rtl818x_iowrite32_idx(priv, addr, val, 0);
143} 218}
144 219
145#endif /* RTL8187_H */ 220#endif /* RTL8187_H */
diff --git a/drivers/net/wireless/rtl8187_dev.c b/drivers/net/wireless/rtl8187_dev.c
index 9223ada5f00e..d3067b1216ca 100644
--- a/drivers/net/wireless/rtl8187_dev.c
+++ b/drivers/net/wireless/rtl8187_dev.c
@@ -27,19 +27,21 @@
27 27
28MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); 28MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
29MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>"); 29MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
30MODULE_DESCRIPTION("RTL8187 USB wireless driver"); 30MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
31MODULE_LICENSE("GPL"); 31MODULE_LICENSE("GPL");
32 32
33static struct usb_device_id rtl8187_table[] __devinitdata = { 33static struct usb_device_id rtl8187_table[] __devinitdata = {
34 /* Realtek */ 34 /* Realtek */
35 {USB_DEVICE(0x0bda, 0x8187)}, 35 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
36 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
37 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
36 /* Netgear */ 38 /* Netgear */
37 {USB_DEVICE(0x0846, 0x6100)}, 39 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
38 {USB_DEVICE(0x0846, 0x6a00)}, 40 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
39 /* HP */ 41 /* HP */
40 {USB_DEVICE(0x03f0, 0xca02)}, 42 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
41 /* Sitecom */ 43 /* Sitecom */
42 {USB_DEVICE(0x0df6, 0x000d)}, 44 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
43 {} 45 {}
44}; 46};
45 47
@@ -150,27 +152,25 @@ void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
150 152
151static void rtl8187_tx_cb(struct urb *urb) 153static void rtl8187_tx_cb(struct urb *urb)
152{ 154{
153 struct ieee80211_tx_status status;
154 struct sk_buff *skb = (struct sk_buff *)urb->context; 155 struct sk_buff *skb = (struct sk_buff *)urb->context;
155 struct rtl8187_tx_info *info = (struct rtl8187_tx_info *)skb->cb; 156 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
156 157 struct ieee80211_hw *hw = info->driver_data[0];
157 memset(&status, 0, sizeof(status)); 158 struct rtl8187_priv *priv = hw->priv;
158 159
159 usb_free_urb(info->urb); 160 usb_free_urb(info->driver_data[1]);
160 if (info->control) 161 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
161 memcpy(&status.control, info->control, sizeof(status.control)); 162 sizeof(struct rtl8187_tx_hdr));
162 kfree(info->control); 163 memset(&info->status, 0, sizeof(info->status));
163 skb_pull(skb, sizeof(struct rtl8187_tx_hdr)); 164 info->flags |= IEEE80211_TX_STAT_ACK;
164 status.flags |= IEEE80211_TX_STATUS_ACK; 165 ieee80211_tx_status_irqsafe(hw, skb);
165 ieee80211_tx_status_irqsafe(info->dev, skb, &status);
166} 166}
167 167
168static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb, 168static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
169 struct ieee80211_tx_control *control)
170{ 169{
171 struct rtl8187_priv *priv = dev->priv; 170 struct rtl8187_priv *priv = dev->priv;
172 struct rtl8187_tx_hdr *hdr; 171 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
173 struct rtl8187_tx_info *info; 172 unsigned int ep;
173 void *buf;
174 struct urb *urb; 174 struct urb *urb;
175 __le16 rts_dur = 0; 175 __le16 rts_dur = 0;
176 u32 flags; 176 u32 flags;
@@ -185,35 +185,60 @@ static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
185 flags = skb->len; 185 flags = skb->len;
186 flags |= RTL8187_TX_FLAG_NO_ENCRYPT; 186 flags |= RTL8187_TX_FLAG_NO_ENCRYPT;
187 187
188 BUG_ON(!control->tx_rate); 188 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
189 189 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
190 flags |= control->tx_rate->hw_value << 24;
191 if (ieee80211_get_morefrag((struct ieee80211_hdr *)skb->data))
192 flags |= RTL8187_TX_FLAG_MORE_FRAG; 190 flags |= RTL8187_TX_FLAG_MORE_FRAG;
193 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS) { 191 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
194 BUG_ON(!control->rts_cts_rate);
195 flags |= RTL8187_TX_FLAG_RTS; 192 flags |= RTL8187_TX_FLAG_RTS;
196 flags |= control->rts_cts_rate->hw_value << 19; 193 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
197 rts_dur = ieee80211_rts_duration(dev, priv->vif, 194 rts_dur = ieee80211_rts_duration(dev, priv->vif,
198 skb->len, control); 195 skb->len, info);
199 } else if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) { 196 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
200 BUG_ON(!control->rts_cts_rate);
201 flags |= RTL8187_TX_FLAG_CTS; 197 flags |= RTL8187_TX_FLAG_CTS;
202 flags |= control->rts_cts_rate->hw_value << 19; 198 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
203 } 199 }
204 200
205 hdr = (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr)); 201 if (!priv->is_rtl8187b) {
206 hdr->flags = cpu_to_le32(flags); 202 struct rtl8187_tx_hdr *hdr =
207 hdr->len = 0; 203 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
208 hdr->rts_duration = rts_dur; 204 hdr->flags = cpu_to_le32(flags);
209 hdr->retry = cpu_to_le32(control->retry_limit << 8); 205 hdr->len = 0;
206 hdr->rts_duration = rts_dur;
207 hdr->retry = cpu_to_le32(info->control.retry_limit << 8);
208 buf = hdr;
210 209
211 info = (struct rtl8187_tx_info *)skb->cb; 210 ep = 2;
212 info->control = kmemdup(control, sizeof(*control), GFP_ATOMIC); 211 } else {
213 info->urb = urb; 212 /* fc needs to be calculated before skb_push() */
214 info->dev = dev; 213 unsigned int epmap[4] = { 6, 7, 5, 4 };
215 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, 2), 214 struct ieee80211_hdr *tx_hdr =
216 hdr, skb->len, rtl8187_tx_cb, skb); 215 (struct ieee80211_hdr *)(skb->data);
216 u16 fc = le16_to_cpu(tx_hdr->frame_control);
217
218 struct rtl8187b_tx_hdr *hdr =
219 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
220 struct ieee80211_rate *txrate =
221 ieee80211_get_tx_rate(dev, info);
222 memset(hdr, 0, sizeof(*hdr));
223 hdr->flags = cpu_to_le32(flags);
224 hdr->rts_duration = rts_dur;
225 hdr->retry = cpu_to_le32(info->control.retry_limit << 8);
226 hdr->tx_duration =
227 ieee80211_generic_frame_duration(dev, priv->vif,
228 skb->len, txrate);
229 buf = hdr;
230
231 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
232 ep = 12;
233 else
234 ep = epmap[skb_get_queue_mapping(skb)];
235 }
236
237 info->driver_data[0] = dev;
238 info->driver_data[1] = urb;
239
240 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
241 buf, skb->len, rtl8187_tx_cb, skb);
217 rc = usb_submit_urb(urb, GFP_ATOMIC); 242 rc = usb_submit_urb(urb, GFP_ATOMIC);
218 if (rc < 0) { 243 if (rc < 0) {
219 usb_free_urb(urb); 244 usb_free_urb(urb);
@@ -229,7 +254,6 @@ static void rtl8187_rx_cb(struct urb *urb)
229 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb; 254 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
230 struct ieee80211_hw *dev = info->dev; 255 struct ieee80211_hw *dev = info->dev;
231 struct rtl8187_priv *priv = dev->priv; 256 struct rtl8187_priv *priv = dev->priv;
232 struct rtl8187_rx_hdr *hdr;
233 struct ieee80211_rx_status rx_status = { 0 }; 257 struct ieee80211_rx_status rx_status = { 0 };
234 int rate, signal; 258 int rate, signal;
235 u32 flags; 259 u32 flags;
@@ -250,11 +274,33 @@ static void rtl8187_rx_cb(struct urb *urb)
250 } 274 }
251 275
252 skb_put(skb, urb->actual_length); 276 skb_put(skb, urb->actual_length);
253 hdr = (struct rtl8187_rx_hdr *)(skb_tail_pointer(skb) - sizeof(*hdr)); 277 if (!priv->is_rtl8187b) {
254 flags = le32_to_cpu(hdr->flags); 278 struct rtl8187_rx_hdr *hdr =
255 skb_trim(skb, flags & 0x0FFF); 279 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
280 flags = le32_to_cpu(hdr->flags);
281 signal = hdr->signal & 0x7f;
282 rx_status.antenna = (hdr->signal >> 7) & 1;
283 rx_status.signal = signal;
284 rx_status.noise = hdr->noise;
285 rx_status.mactime = le64_to_cpu(hdr->mac_time);
286 priv->signal = signal;
287 priv->quality = signal;
288 priv->noise = hdr->noise;
289 } else {
290 struct rtl8187b_rx_hdr *hdr =
291 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
292 flags = le32_to_cpu(hdr->flags);
293 signal = hdr->agc >> 1;
294 rx_status.antenna = (hdr->signal >> 7) & 1;
295 rx_status.signal = 64 - min(hdr->noise, (u8)64);
296 rx_status.noise = hdr->noise;
297 rx_status.mactime = le64_to_cpu(hdr->mac_time);
298 priv->signal = hdr->signal;
299 priv->quality = hdr->agc >> 1;
300 priv->noise = hdr->noise;
301 }
256 302
257 signal = hdr->agc >> 1; 303 skb_trim(skb, flags & 0x0FFF);
258 rate = (flags >> 20) & 0xF; 304 rate = (flags >> 20) & 0xF;
259 if (rate > 3) { /* OFDM rate */ 305 if (rate > 3) { /* OFDM rate */
260 if (signal > 90) 306 if (signal > 90)
@@ -270,13 +316,11 @@ static void rtl8187_rx_cb(struct urb *urb)
270 signal = 95 - signal; 316 signal = 95 - signal;
271 } 317 }
272 318
273 rx_status.antenna = (hdr->signal >> 7) & 1; 319 rx_status.qual = priv->quality;
274 rx_status.signal = 64 - min(hdr->noise, (u8)64); 320 rx_status.signal = signal;
275 rx_status.ssi = signal;
276 rx_status.rate_idx = rate; 321 rx_status.rate_idx = rate;
277 rx_status.freq = dev->conf.channel->center_freq; 322 rx_status.freq = dev->conf.channel->center_freq;
278 rx_status.band = dev->conf.channel->band; 323 rx_status.band = dev->conf.channel->band;
279 rx_status.mactime = le64_to_cpu(hdr->mac_time);
280 rx_status.flag |= RX_FLAG_TSFT; 324 rx_status.flag |= RX_FLAG_TSFT;
281 if (flags & (1 << 13)) 325 if (flags & (1 << 13))
282 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC; 326 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
@@ -316,7 +360,8 @@ static int rtl8187_init_urbs(struct ieee80211_hw *dev)
316 break; 360 break;
317 } 361 }
318 usb_fill_bulk_urb(entry, priv->udev, 362 usb_fill_bulk_urb(entry, priv->udev,
319 usb_rcvbulkpipe(priv->udev, 1), 363 usb_rcvbulkpipe(priv->udev,
364 priv->is_rtl8187b ? 3 : 1),
320 skb_tail_pointer(skb), 365 skb_tail_pointer(skb),
321 RTL8187_MAX_RX, rtl8187_rx_cb, skb); 366 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
322 info = (struct rtl8187_rx_info *)skb->cb; 367 info = (struct rtl8187_rx_info *)skb->cb;
@@ -329,29 +374,12 @@ static int rtl8187_init_urbs(struct ieee80211_hw *dev)
329 return 0; 374 return 0;
330} 375}
331 376
332static int rtl8187_init_hw(struct ieee80211_hw *dev) 377static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
333{ 378{
334 struct rtl8187_priv *priv = dev->priv; 379 struct rtl8187_priv *priv = dev->priv;
335 u8 reg; 380 u8 reg;
336 int i; 381 int i;
337 382
338 /* reset */
339 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
340 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
341 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
342 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_ON);
343 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON);
344 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
345 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
346
347 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
348
349 msleep(200);
350 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
351 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
352 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
353 msleep(200);
354
355 reg = rtl818x_ioread8(priv, &priv->map->CMD); 383 reg = rtl818x_ioread8(priv, &priv->map->CMD);
356 reg &= (1 << 1); 384 reg &= (1 << 1);
357 reg |= RTL818X_CMD_RESET; 385 reg |= RTL818X_CMD_RESET;
@@ -387,12 +415,52 @@ static int rtl8187_init_hw(struct ieee80211_hw *dev)
387 return -ETIMEDOUT; 415 return -ETIMEDOUT;
388 } 416 }
389 417
418 return 0;
419}
420
421static int rtl8187_init_hw(struct ieee80211_hw *dev)
422{
423 struct rtl8187_priv *priv = dev->priv;
424 u8 reg;
425 int res;
426
427 /* reset */
428 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
429 RTL818X_EEPROM_CMD_CONFIG);
430 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
431 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
432 RTL818X_CONFIG3_ANAPARAM_WRITE);
433 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
434 RTL8187_RTL8225_ANAPARAM_ON);
435 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
436 RTL8187_RTL8225_ANAPARAM2_ON);
437 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
438 ~RTL818X_CONFIG3_ANAPARAM_WRITE);
439 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
440 RTL818X_EEPROM_CMD_NORMAL);
441
442 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
443
444 msleep(200);
445 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
446 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
447 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
448 msleep(200);
449
450 res = rtl8187_cmd_reset(dev);
451 if (res)
452 return res;
453
390 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); 454 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
391 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); 455 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
392 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE); 456 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
393 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_ON); 457 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
394 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON); 458 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
395 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); 459 RTL8187_RTL8225_ANAPARAM_ON);
460 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
461 RTL8187_RTL8225_ANAPARAM2_ON);
462 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
463 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
396 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); 464 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
397 465
398 /* setup card */ 466 /* setup card */
@@ -437,9 +505,11 @@ static int rtl8187_init_hw(struct ieee80211_hw *dev)
437 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008); 505 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
438 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF); 506 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
439 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044); 507 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
440 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); 508 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
509 RTL818X_EEPROM_CMD_CONFIG);
441 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44); 510 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
442 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); 511 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
512 RTL818X_EEPROM_CMD_NORMAL);
443 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7); 513 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
444 msleep(100); 514 msleep(100);
445 515
@@ -456,16 +526,201 @@ static int rtl8187_init_hw(struct ieee80211_hw *dev)
456 return 0; 526 return 0;
457} 527}
458 528
529static const u8 rtl8187b_reg_table[][3] = {
530 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
531 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
532 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
533 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
534
535 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
536 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
537 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
538 {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
539 {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
540 {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
541
542 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
543 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
544 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
545 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
546 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
547 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
548 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
549 {0x73, 0x9A, 2},
550
551 {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
552 {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
553 {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
554 {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
555 {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x91, 0x03, 0},
556
557 {0x4C, 0x00, 2}, {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0},
558 {0x8E, 0x08, 0}, {0x8F, 0x00, 0}
559};
560
561static int rtl8187b_init_hw(struct ieee80211_hw *dev)
562{
563 struct rtl8187_priv *priv = dev->priv;
564 int res, i;
565 u8 reg;
566
567 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
568 RTL818X_EEPROM_CMD_CONFIG);
569
570 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
571 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
572 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
573 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
574 RTL8187B_RTL8225_ANAPARAM2_ON);
575 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
576 RTL8187B_RTL8225_ANAPARAM_ON);
577 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
578 RTL8187B_RTL8225_ANAPARAM3_ON);
579
580 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
581 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
582 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
583 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
584
585 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
586 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
587 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
588
589 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
590 RTL818X_EEPROM_CMD_NORMAL);
591
592 res = rtl8187_cmd_reset(dev);
593 if (res)
594 return res;
595
596 rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
597 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
598 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
599 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
600 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
601 reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
602 RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
603 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
604
605 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
606 reg = rtl818x_ioread8(priv, &priv->map->RATE_FALLBACK);
607 reg |= RTL818X_RATE_FALLBACK_ENABLE;
608 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, reg);
609
610 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
611 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
612 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
613
614 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
615 RTL818X_EEPROM_CMD_CONFIG);
616 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
617 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
618 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
619 RTL818X_EEPROM_CMD_NORMAL);
620
621 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
622 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
623 rtl818x_iowrite8_idx(priv,
624 (u8 *)(uintptr_t)
625 (rtl8187b_reg_table[i][0] | 0xFF00),
626 rtl8187b_reg_table[i][1],
627 rtl8187b_reg_table[i][2]);
628 }
629
630 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
631 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
632
633 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
634 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
635 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
636
637 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
638
639 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
640
641 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
642 RTL818X_EEPROM_CMD_CONFIG);
643 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
644 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
645 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
646 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
647 RTL818X_EEPROM_CMD_NORMAL);
648
649 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
650 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
651 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
652 msleep(1100);
653
654 priv->rf->init(dev);
655
656 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
657 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
658 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
659
660 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
661 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
662 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
663 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
664 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
665 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
666 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
667
668 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
669 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
670 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
671 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
672 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
673 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
674 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
675 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
676 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
677 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
678 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
679 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
680 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
681
682 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
683
684 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
685
686 return 0;
687}
688
459static int rtl8187_start(struct ieee80211_hw *dev) 689static int rtl8187_start(struct ieee80211_hw *dev)
460{ 690{
461 struct rtl8187_priv *priv = dev->priv; 691 struct rtl8187_priv *priv = dev->priv;
462 u32 reg; 692 u32 reg;
463 int ret; 693 int ret;
464 694
465 ret = rtl8187_init_hw(dev); 695 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
696 rtl8187b_init_hw(dev);
466 if (ret) 697 if (ret)
467 return ret; 698 return ret;
468 699
700 if (priv->is_rtl8187b) {
701 reg = RTL818X_RX_CONF_MGMT |
702 RTL818X_RX_CONF_DATA |
703 RTL818X_RX_CONF_BROADCAST |
704 RTL818X_RX_CONF_NICMAC |
705 RTL818X_RX_CONF_BSSID |
706 (7 << 13 /* RX FIFO threshold NONE */) |
707 (7 << 10 /* MAX RX DMA */) |
708 RTL818X_RX_CONF_RX_AUTORESETPHY |
709 RTL818X_RX_CONF_ONLYERLPKT |
710 RTL818X_RX_CONF_MULTICAST;
711 priv->rx_conf = reg;
712 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
713
714 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
715 RTL818X_TX_CONF_HW_SEQNUM |
716 RTL818X_TX_CONF_DISREQQSIZE |
717 (7 << 8 /* short retry limit */) |
718 (7 << 0 /* long retry limit */) |
719 (7 << 21 /* MAX TX DMA */));
720 rtl8187_init_urbs(dev);
721 return 0;
722 }
723
469 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); 724 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
470 725
471 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0); 726 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
@@ -592,18 +847,20 @@ static int rtl8187_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
592 msleep(10); 847 msleep(10);
593 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); 848 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
594 849
595 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22); 850 if (!priv->is_rtl8187b) {
596 851 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
597 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) { 852
598 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9); 853 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
599 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14); 854 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
600 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14); 855 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
601 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0x73); 856 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
602 } else { 857 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0x73);
603 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14); 858 } else {
604 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24); 859 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
605 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24); 860 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
606 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0xa5); 861 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
862 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0xa5);
863 }
607 } 864 }
608 865
609 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2); 866 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
@@ -619,14 +876,20 @@ static int rtl8187_config_interface(struct ieee80211_hw *dev,
619{ 876{
620 struct rtl8187_priv *priv = dev->priv; 877 struct rtl8187_priv *priv = dev->priv;
621 int i; 878 int i;
879 u8 reg;
622 880
623 for (i = 0; i < ETH_ALEN; i++) 881 for (i = 0; i < ETH_ALEN; i++)
624 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]); 882 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
625 883
626 if (is_valid_ether_addr(conf->bssid)) 884 if (is_valid_ether_addr(conf->bssid)) {
627 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_INFRA); 885 reg = RTL818X_MSR_INFRA;
628 else 886 if (priv->is_rtl8187b)
629 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_NO_LINK); 887 reg |= RTL818X_MSR_ENEDCA;
888 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
889 } else {
890 reg = RTL818X_MSR_NO_LINK;
891 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
892 }
630 893
631 return 0; 894 return 0;
632} 895}
@@ -713,6 +976,7 @@ static int __devinit rtl8187_probe(struct usb_interface *intf,
713 struct rtl8187_priv *priv; 976 struct rtl8187_priv *priv;
714 struct eeprom_93cx6 eeprom; 977 struct eeprom_93cx6 eeprom;
715 struct ieee80211_channel *channel; 978 struct ieee80211_channel *channel;
979 const char *chip_name;
716 u16 txpwr, reg; 980 u16 txpwr, reg;
717 int err, i; 981 int err, i;
718 DECLARE_MAC_BUF(mac); 982 DECLARE_MAC_BUF(mac);
@@ -724,6 +988,7 @@ static int __devinit rtl8187_probe(struct usb_interface *intf,
724 } 988 }
725 989
726 priv = dev->priv; 990 priv = dev->priv;
991 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
727 992
728 SET_IEEE80211_DEV(dev, &intf->dev); 993 SET_IEEE80211_DEV(dev, &intf->dev);
729 usb_set_intfdata(intf, dev); 994 usb_set_intfdata(intf, dev);
@@ -750,11 +1015,9 @@ static int __devinit rtl8187_probe(struct usb_interface *intf,
750 1015
751 priv->mode = IEEE80211_IF_TYPE_MNTR; 1016 priv->mode = IEEE80211_IF_TYPE_MNTR;
752 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 1017 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
753 IEEE80211_HW_RX_INCLUDES_FCS; 1018 IEEE80211_HW_RX_INCLUDES_FCS |
754 dev->extra_tx_headroom = sizeof(struct rtl8187_tx_hdr); 1019 IEEE80211_HW_SIGNAL_UNSPEC;
755 dev->queues = 1; 1020 dev->max_signal = 65;
756 dev->max_rssi = 65;
757 dev->max_signal = 64;
758 1021
759 eeprom.data = dev; 1022 eeprom.data = dev;
760 eeprom.register_read = rtl8187_eeprom_register_read; 1023 eeprom.register_read = rtl8187_eeprom_register_read;
@@ -788,12 +1051,6 @@ static int __devinit rtl8187_probe(struct usb_interface *intf,
788 (*channel++).hw_value = txpwr & 0xFF; 1051 (*channel++).hw_value = txpwr & 0xFF;
789 (*channel++).hw_value = txpwr >> 8; 1052 (*channel++).hw_value = txpwr >> 8;
790 } 1053 }
791 for (i = 0; i < 2; i++) {
792 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6 + i,
793 &txpwr);
794 (*channel++).hw_value = txpwr & 0xFF;
795 (*channel++).hw_value = txpwr >> 8;
796 }
797 1054
798 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE, 1055 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
799 &priv->txpwr_base); 1056 &priv->txpwr_base);
@@ -807,7 +1064,90 @@ static int __devinit rtl8187_probe(struct usb_interface *intf,
807 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg); 1064 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
808 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); 1065 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
809 1066
1067 if (!priv->is_rtl8187b) {
1068 u32 reg32;
1069 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1070 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1071 switch (reg32) {
1072 case RTL818X_TX_CONF_R8187vD_B:
1073 /* Some RTL8187B devices have a USB ID of 0x8187
1074 * detect them here */
1075 chip_name = "RTL8187BvB(early)";
1076 priv->is_rtl8187b = 1;
1077 priv->hw_rev = RTL8187BvB;
1078 break;
1079 case RTL818X_TX_CONF_R8187vD:
1080 chip_name = "RTL8187vD";
1081 break;
1082 default:
1083 chip_name = "RTL8187vB (default)";
1084 }
1085 } else {
1086 /*
1087 * Force USB request to write radio registers for 8187B, Realtek
1088 * only uses it in their sources
1089 */
1090 /*if (priv->asic_rev == 0) {
1091 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1092 "requests to write to radio registers\n");
1093 priv->asic_rev = 1;
1094 }*/
1095 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1096 case RTL818X_R8187B_B:
1097 chip_name = "RTL8187BvB";
1098 priv->hw_rev = RTL8187BvB;
1099 break;
1100 case RTL818X_R8187B_D:
1101 chip_name = "RTL8187BvD";
1102 priv->hw_rev = RTL8187BvD;
1103 break;
1104 case RTL818X_R8187B_E:
1105 chip_name = "RTL8187BvE";
1106 priv->hw_rev = RTL8187BvE;
1107 break;
1108 default:
1109 chip_name = "RTL8187BvB (default)";
1110 priv->hw_rev = RTL8187BvB;
1111 }
1112 }
1113
1114 if (!priv->is_rtl8187b) {
1115 for (i = 0; i < 2; i++) {
1116 eeprom_93cx6_read(&eeprom,
1117 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1118 &txpwr);
1119 (*channel++).hw_value = txpwr & 0xFF;
1120 (*channel++).hw_value = txpwr >> 8;
1121 }
1122 } else {
1123 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1124 &txpwr);
1125 (*channel++).hw_value = txpwr & 0xFF;
1126
1127 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1128 (*channel++).hw_value = txpwr & 0xFF;
1129
1130 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1131 (*channel++).hw_value = txpwr & 0xFF;
1132 (*channel++).hw_value = txpwr >> 8;
1133 }
1134
1135 if (priv->is_rtl8187b)
1136 printk(KERN_WARNING "rtl8187: 8187B chip detected. Support "
1137 "is EXPERIMENTAL, and could damage your\n"
1138 " hardware, use at your own risk\n");
1139 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1140 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1141 " info!\n");
1142
810 priv->rf = rtl8187_detect_rf(dev); 1143 priv->rf = rtl8187_detect_rf(dev);
1144 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1145 sizeof(struct rtl8187_tx_hdr) :
1146 sizeof(struct rtl8187b_tx_hdr);
1147 if (!priv->is_rtl8187b)
1148 dev->queues = 1;
1149 else
1150 dev->queues = 4;
811 1151
812 err = ieee80211_register_hw(dev); 1152 err = ieee80211_register_hw(dev);
813 if (err) { 1153 if (err) {
@@ -815,9 +1155,9 @@ static int __devinit rtl8187_probe(struct usb_interface *intf,
815 goto err_free_dev; 1155 goto err_free_dev;
816 } 1156 }
817 1157
818 printk(KERN_INFO "%s: hwaddr %s, rtl8187 V%d + %s\n", 1158 printk(KERN_INFO "%s: hwaddr %s, %s V%d + %s\n",
819 wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr), 1159 wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
820 priv->asic_rev, priv->rf->name); 1160 chip_name, priv->asic_rev, priv->rf->name);
821 1161
822 return 0; 1162 return 0;
823 1163
@@ -847,7 +1187,7 @@ static struct usb_driver rtl8187_driver = {
847 .name = KBUILD_MODNAME, 1187 .name = KBUILD_MODNAME,
848 .id_table = rtl8187_table, 1188 .id_table = rtl8187_table,
849 .probe = rtl8187_probe, 1189 .probe = rtl8187_probe,
850 .disconnect = rtl8187_disconnect, 1190 .disconnect = __devexit_p(rtl8187_disconnect),
851}; 1191};
852 1192
853static int __init rtl8187_init(void) 1193static int __init rtl8187_init(void)
diff --git a/drivers/net/wireless/rtl8187_rtl8225.c b/drivers/net/wireless/rtl8187_rtl8225.c
index 9146387b4c5e..1bae89903410 100644
--- a/drivers/net/wireless/rtl8187_rtl8225.c
+++ b/drivers/net/wireless/rtl8187_rtl8225.c
@@ -305,9 +305,12 @@ static void rtl8225_rf_set_tx_power(struct ieee80211_hw *dev, int channel)
305 /* anaparam2 on */ 305 /* anaparam2 on */
306 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); 306 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
307 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); 307 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
308 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE); 308 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
309 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON); 309 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
310 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); 310 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
311 RTL8187_RTL8225_ANAPARAM2_ON);
312 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
313 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
311 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); 314 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
312 315
313 rtl8225_write_phy_ofdm(dev, 2, 0x42); 316 rtl8225_write_phy_ofdm(dev, 2, 0x42);
@@ -471,12 +474,42 @@ static void rtl8225_rf_init(struct ieee80211_hw *dev)
471 rtl8225_write_phy_cck(dev, 0x41, rtl8225_threshold[2]); 474 rtl8225_write_phy_cck(dev, 0x41, rtl8225_threshold[2]);
472} 475}
473 476
477static const u8 rtl8225z2_agc[] = {
478 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51, 0x4f,
479 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37,
480 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25, 0x23, 0x21, 0x1f,
481 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07,
482 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
483 0x01, 0x01, 0x01, 0x01, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
484 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28,
485 0x28, 0x29, 0x2a, 0x2a, 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d,
486 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30,
487 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
488 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
489};
490static const u8 rtl8225z2_ofdm[] = {
491 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60,
492 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00,
493 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26,
494 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3,
495 0x0a, 0xe1, 0x2C, 0x8a, 0x86, 0x83, 0x34, 0x0f,
496 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00,
497 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e,
498 0x6d, 0x3c, 0xfb, 0x07
499};
500
474static const u8 rtl8225z2_tx_power_cck_ch14[] = { 501static const u8 rtl8225z2_tx_power_cck_ch14[] = {
475 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 502 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
503 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
504 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
505 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
476}; 506};
477 507
478static const u8 rtl8225z2_tx_power_cck[] = { 508static const u8 rtl8225z2_tx_power_cck[] = {
479 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 509 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
510 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
511 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
512 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
480}; 513};
481 514
482static const u8 rtl8225z2_tx_power_ofdm[] = { 515static const u8 rtl8225z2_tx_power_ofdm[] = {
@@ -526,9 +559,12 @@ static void rtl8225z2_rf_set_tx_power(struct ieee80211_hw *dev, int channel)
526 /* anaparam2 on */ 559 /* anaparam2 on */
527 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); 560 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
528 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); 561 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
529 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE); 562 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
530 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON); 563 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
531 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); 564 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
565 RTL8187_RTL8225_ANAPARAM2_ON);
566 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
567 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
532 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); 568 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
533 569
534 rtl8225_write_phy_ofdm(dev, 2, 0x42); 570 rtl8225_write_phy_ofdm(dev, 2, 0x42);
@@ -542,6 +578,85 @@ static void rtl8225z2_rf_set_tx_power(struct ieee80211_hw *dev, int channel)
542 msleep(1); 578 msleep(1);
543} 579}
544 580
581static void rtl8225z2_b_rf_set_tx_power(struct ieee80211_hw *dev, int channel)
582{
583 struct rtl8187_priv *priv = dev->priv;
584 u8 cck_power, ofdm_power;
585 const u8 *tmp;
586 int i;
587
588 cck_power = priv->channels[channel - 1].hw_value & 0xF;
589 ofdm_power = priv->channels[channel - 1].hw_value >> 4;
590
591 if (cck_power > 15)
592 cck_power = (priv->hw_rev == RTL8187BvB) ? 15 : 22;
593 else
594 cck_power += (priv->hw_rev == RTL8187BvB) ? 0 : 7;
595 cck_power += priv->txpwr_base & 0xF;
596 cck_power = min(cck_power, (u8)35);
597
598 if (ofdm_power > 15)
599 ofdm_power = (priv->hw_rev == RTL8187BvB) ? 17 : 25;
600 else
601 ofdm_power += (priv->hw_rev == RTL8187BvB) ? 2 : 10;
602 ofdm_power += (priv->txpwr_base >> 4) & 0xF;
603 ofdm_power = min(ofdm_power, (u8)35);
604
605 if (channel == 14)
606 tmp = rtl8225z2_tx_power_cck_ch14;
607 else
608 tmp = rtl8225z2_tx_power_cck;
609
610 if (priv->hw_rev == RTL8187BvB) {
611 if (cck_power <= 6)
612 ; /* do nothing */
613 else if (cck_power <= 11)
614 tmp += 8;
615 else
616 tmp += 16;
617 } else {
618 if (cck_power <= 5)
619 ; /* do nothing */
620 else if (cck_power <= 11)
621 tmp += 8;
622 else if (cck_power <= 17)
623 tmp += 16;
624 else
625 tmp += 24;
626 }
627
628 for (i = 0; i < 8; i++)
629 rtl8225_write_phy_cck(dev, 0x44 + i, *tmp++);
630
631 rtl818x_iowrite8(priv, &priv->map->TX_GAIN_CCK,
632 rtl8225z2_tx_gain_cck_ofdm[cck_power]);
633 msleep(1);
634
635 rtl818x_iowrite8(priv, &priv->map->TX_GAIN_OFDM,
636 rtl8225z2_tx_gain_cck_ofdm[ofdm_power] << 1);
637 if (priv->hw_rev == RTL8187BvB) {
638 if (ofdm_power <= 11) {
639 rtl8225_write_phy_ofdm(dev, 0x87, 0x60);
640 rtl8225_write_phy_ofdm(dev, 0x89, 0x60);
641 } else {
642 rtl8225_write_phy_ofdm(dev, 0x87, 0x5c);
643 rtl8225_write_phy_ofdm(dev, 0x89, 0x5c);
644 }
645 } else {
646 if (ofdm_power <= 11) {
647 rtl8225_write_phy_ofdm(dev, 0x87, 0x5c);
648 rtl8225_write_phy_ofdm(dev, 0x89, 0x5c);
649 } else if (ofdm_power <= 17) {
650 rtl8225_write_phy_ofdm(dev, 0x87, 0x54);
651 rtl8225_write_phy_ofdm(dev, 0x89, 0x54);
652 } else {
653 rtl8225_write_phy_ofdm(dev, 0x87, 0x50);
654 rtl8225_write_phy_ofdm(dev, 0x89, 0x50);
655 }
656 }
657 msleep(1);
658}
659
545static const u16 rtl8225z2_rxgain[] = { 660static const u16 rtl8225z2_rxgain[] = {
546 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 661 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
547 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 662 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
@@ -715,6 +830,81 @@ static void rtl8225z2_rf_init(struct ieee80211_hw *dev)
715 rtl818x_iowrite32(priv, (__le32 *)0xFF94, 0x3dc00002); 830 rtl818x_iowrite32(priv, (__le32 *)0xFF94, 0x3dc00002);
716} 831}
717 832
833static void rtl8225z2_b_rf_init(struct ieee80211_hw *dev)
834{
835 struct rtl8187_priv *priv = dev->priv;
836 int i;
837
838 rtl8225_write(dev, 0x0, 0x0B7); msleep(1);
839 rtl8225_write(dev, 0x1, 0xEE0); msleep(1);
840 rtl8225_write(dev, 0x2, 0x44D); msleep(1);
841 rtl8225_write(dev, 0x3, 0x441); msleep(1);
842 rtl8225_write(dev, 0x4, 0x8C3); msleep(1);
843 rtl8225_write(dev, 0x5, 0xC72); msleep(1);
844 rtl8225_write(dev, 0x6, 0x0E6); msleep(1);
845 rtl8225_write(dev, 0x7, 0x82A); msleep(1);
846 rtl8225_write(dev, 0x8, 0x03F); msleep(1);
847 rtl8225_write(dev, 0x9, 0x335); msleep(1);
848 rtl8225_write(dev, 0xa, 0x9D4); msleep(1);
849 rtl8225_write(dev, 0xb, 0x7BB); msleep(1);
850 rtl8225_write(dev, 0xc, 0x850); msleep(1);
851 rtl8225_write(dev, 0xd, 0xCDF); msleep(1);
852 rtl8225_write(dev, 0xe, 0x02B); msleep(1);
853 rtl8225_write(dev, 0xf, 0x114); msleep(1);
854
855 rtl8225_write(dev, 0x0, 0x1B7); msleep(1);
856
857 for (i = 0; i < ARRAY_SIZE(rtl8225z2_rxgain); i++) {
858 rtl8225_write(dev, 0x1, i + 1); msleep(1);
859 rtl8225_write(dev, 0x2, rtl8225z2_rxgain[i]); msleep(1);
860 }
861
862 rtl8225_write(dev, 0x3, 0x080); msleep(1);
863 rtl8225_write(dev, 0x5, 0x004); msleep(1);
864 rtl8225_write(dev, 0x0, 0x0B7); msleep(1);
865 msleep(3000);
866
867 rtl8225_write(dev, 0x2, 0xC4D); msleep(1);
868 msleep(2000);
869
870 rtl8225_write(dev, 0x2, 0x44D); msleep(1);
871 rtl8225_write(dev, 0x0, 0x2BF); msleep(1);
872
873 rtl818x_iowrite8(priv, &priv->map->TX_GAIN_CCK, 0x03);
874 rtl818x_iowrite8(priv, &priv->map->TX_GAIN_OFDM, 0x07);
875 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03);
876
877 rtl8225_write_phy_ofdm(dev, 0x80, 0x12);
878 for (i = 0; i < ARRAY_SIZE(rtl8225z2_agc); i++) {
879 rtl8225_write_phy_ofdm(dev, 0xF, rtl8225z2_agc[i]);
880 rtl8225_write_phy_ofdm(dev, 0xE, 0x80 + i);
881 rtl8225_write_phy_ofdm(dev, 0xE, 0);
882 }
883 rtl8225_write_phy_ofdm(dev, 0x80, 0x10);
884
885 for (i = 0; i < ARRAY_SIZE(rtl8225z2_ofdm); i++)
886 rtl8225_write_phy_ofdm(dev, i, rtl8225z2_ofdm[i]);
887
888 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
889 rtl818x_iowrite8(priv, &priv->map->SLOT, 9);
890 rtl818x_iowrite8(priv, (u8 *)0xFFF0, 28);
891 rtl818x_iowrite8(priv, (u8 *)0xFFF4, 28);
892 rtl818x_iowrite8(priv, (u8 *)0xFFF8, 28);
893 rtl818x_iowrite8(priv, (u8 *)0xFFFC, 28);
894 rtl818x_iowrite8(priv, (u8 *)0xFF2D, 0x5B);
895 rtl818x_iowrite8(priv, (u8 *)0xFF79, 0x5B);
896 rtl818x_iowrite32(priv, (__le32 *)0xFFF0, (7 << 12) | (3 << 8) | 28);
897 rtl818x_iowrite32(priv, (__le32 *)0xFFF4, (7 << 12) | (3 << 8) | 28);
898 rtl818x_iowrite32(priv, (__le32 *)0xFFF8, (7 << 12) | (3 << 8) | 28);
899 rtl818x_iowrite32(priv, (__le32 *)0xFFFC, (7 << 12) | (3 << 8) | 28);
900 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
901
902 rtl8225_write_phy_ofdm(dev, 0x97, 0x46); msleep(1);
903 rtl8225_write_phy_ofdm(dev, 0xa4, 0xb6); msleep(1);
904 rtl8225_write_phy_ofdm(dev, 0x85, 0xfc); msleep(1);
905 rtl8225_write_phy_cck(dev, 0xc1, 0x88); msleep(1);
906}
907
718static void rtl8225_rf_stop(struct ieee80211_hw *dev) 908static void rtl8225_rf_stop(struct ieee80211_hw *dev)
719{ 909{
720 u8 reg; 910 u8 reg;
@@ -725,8 +915,19 @@ static void rtl8225_rf_stop(struct ieee80211_hw *dev)
725 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); 915 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
726 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); 916 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
727 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE); 917 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
728 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_OFF); 918 if (!priv->is_rtl8187b) {
729 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_OFF); 919 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
920 RTL8187_RTL8225_ANAPARAM2_OFF);
921 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
922 RTL8187_RTL8225_ANAPARAM_OFF);
923 } else {
924 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
925 RTL8187B_RTL8225_ANAPARAM2_OFF);
926 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
927 RTL8187B_RTL8225_ANAPARAM_OFF);
928 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
929 RTL8187B_RTL8225_ANAPARAM3_OFF);
930 }
730 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); 931 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
731 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); 932 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
732} 933}
@@ -739,8 +940,10 @@ static void rtl8225_rf_set_channel(struct ieee80211_hw *dev,
739 940
740 if (priv->rf->init == rtl8225_rf_init) 941 if (priv->rf->init == rtl8225_rf_init)
741 rtl8225_rf_set_tx_power(dev, chan); 942 rtl8225_rf_set_tx_power(dev, chan);
742 else 943 else if (priv->rf->init == rtl8225z2_rf_init)
743 rtl8225z2_rf_set_tx_power(dev, chan); 944 rtl8225z2_rf_set_tx_power(dev, chan);
945 else
946 rtl8225z2_b_rf_set_tx_power(dev, chan);
744 947
745 rtl8225_write(dev, 0x7, rtl8225_chan[chan - 1]); 948 rtl8225_write(dev, 0x7, rtl8225_chan[chan - 1]);
746 msleep(10); 949 msleep(10);
@@ -760,19 +963,30 @@ static const struct rtl818x_rf_ops rtl8225z2_ops = {
760 .set_chan = rtl8225_rf_set_channel 963 .set_chan = rtl8225_rf_set_channel
761}; 964};
762 965
966static const struct rtl818x_rf_ops rtl8225z2_b_ops = {
967 .name = "rtl8225z2",
968 .init = rtl8225z2_b_rf_init,
969 .stop = rtl8225_rf_stop,
970 .set_chan = rtl8225_rf_set_channel
971};
972
763const struct rtl818x_rf_ops * rtl8187_detect_rf(struct ieee80211_hw *dev) 973const struct rtl818x_rf_ops * rtl8187_detect_rf(struct ieee80211_hw *dev)
764{ 974{
765 u16 reg8, reg9; 975 u16 reg8, reg9;
976 struct rtl8187_priv *priv = dev->priv;
766 977
767 rtl8225_write(dev, 0, 0x1B7); 978 if (!priv->is_rtl8187b) {
979 rtl8225_write(dev, 0, 0x1B7);
768 980
769 reg8 = rtl8225_read(dev, 8); 981 reg8 = rtl8225_read(dev, 8);
770 reg9 = rtl8225_read(dev, 9); 982 reg9 = rtl8225_read(dev, 9);
771 983
772 rtl8225_write(dev, 0, 0x0B7); 984 rtl8225_write(dev, 0, 0x0B7);
773 985
774 if (reg8 != 0x588 || reg9 != 0x700) 986 if (reg8 != 0x588 || reg9 != 0x700)
775 return &rtl8225_ops; 987 return &rtl8225_ops;
776 988
777 return &rtl8225z2_ops; 989 return &rtl8225z2_ops;
990 } else
991 return &rtl8225z2_b_ops;
778} 992}
diff --git a/drivers/net/wireless/rtl8187_rtl8225.h b/drivers/net/wireless/rtl8187_rtl8225.h
index d39ed0295b6e..20c5b6ead0f6 100644
--- a/drivers/net/wireless/rtl8187_rtl8225.h
+++ b/drivers/net/wireless/rtl8187_rtl8225.h
@@ -15,10 +15,17 @@
15#ifndef RTL8187_RTL8225_H 15#ifndef RTL8187_RTL8225_H
16#define RTL8187_RTL8225_H 16#define RTL8187_RTL8225_H
17 17
18#define RTL8225_ANAPARAM_ON 0xa0000a59 18#define RTL8187_RTL8225_ANAPARAM_ON 0xa0000a59
19#define RTL8225_ANAPARAM2_ON 0x860c7312 19#define RTL8187_RTL8225_ANAPARAM2_ON 0x860c7312
20#define RTL8225_ANAPARAM_OFF 0xa00beb59 20#define RTL8187_RTL8225_ANAPARAM_OFF 0xa00beb59
21#define RTL8225_ANAPARAM2_OFF 0x840dec11 21#define RTL8187_RTL8225_ANAPARAM2_OFF 0x840dec11
22
23#define RTL8187B_RTL8225_ANAPARAM_ON 0x45090658
24#define RTL8187B_RTL8225_ANAPARAM2_ON 0x727f3f52
25#define RTL8187B_RTL8225_ANAPARAM3_ON 0x00
26#define RTL8187B_RTL8225_ANAPARAM_OFF 0x55480658
27#define RTL8187B_RTL8225_ANAPARAM2_OFF 0x72003f50
28#define RTL8187B_RTL8225_ANAPARAM3_OFF 0x00
22 29
23const struct rtl818x_rf_ops * rtl8187_detect_rf(struct ieee80211_hw *); 30const struct rtl818x_rf_ops * rtl8187_detect_rf(struct ieee80211_hw *);
24 31
diff --git a/drivers/net/wireless/rtl818x.h b/drivers/net/wireless/rtl818x.h
index 4f7d38f506eb..00900fe16fce 100644
--- a/drivers/net/wireless/rtl818x.h
+++ b/drivers/net/wireless/rtl818x.h
@@ -66,7 +66,10 @@ struct rtl818x_csr {
66#define RTL818X_TX_CONF_R8180_F (3 << 25) 66#define RTL818X_TX_CONF_R8180_F (3 << 25)
67#define RTL818X_TX_CONF_R8185_ABC (4 << 25) 67#define RTL818X_TX_CONF_R8185_ABC (4 << 25)
68#define RTL818X_TX_CONF_R8185_D (5 << 25) 68#define RTL818X_TX_CONF_R8185_D (5 << 25)
69#define RTL818X_TX_CONF_R8187vD (5 << 25)
70#define RTL818X_TX_CONF_R8187vD_B (6 << 25)
69#define RTL818X_TX_CONF_HWVER_MASK (7 << 25) 71#define RTL818X_TX_CONF_HWVER_MASK (7 << 25)
72#define RTL818X_TX_CONF_DISREQQSIZE (1 << 28)
70#define RTL818X_TX_CONF_PROBE_DTS (1 << 29) 73#define RTL818X_TX_CONF_PROBE_DTS (1 << 29)
71#define RTL818X_TX_CONF_HW_SEQNUM (1 << 30) 74#define RTL818X_TX_CONF_HW_SEQNUM (1 << 30)
72#define RTL818X_TX_CONF_CW_MIN (1 << 31) 75#define RTL818X_TX_CONF_CW_MIN (1 << 31)
@@ -106,8 +109,11 @@ struct rtl818x_csr {
106#define RTL818X_MSR_NO_LINK (0 << 2) 109#define RTL818X_MSR_NO_LINK (0 << 2)
107#define RTL818X_MSR_ADHOC (1 << 2) 110#define RTL818X_MSR_ADHOC (1 << 2)
108#define RTL818X_MSR_INFRA (2 << 2) 111#define RTL818X_MSR_INFRA (2 << 2)
112#define RTL818X_MSR_MASTER (3 << 2)
113#define RTL818X_MSR_ENEDCA (4 << 2)
109 u8 CONFIG3; 114 u8 CONFIG3;
110#define RTL818X_CONFIG3_ANAPARAM_WRITE (1 << 6) 115#define RTL818X_CONFIG3_ANAPARAM_WRITE (1 << 6)
116#define RTL818X_CONFIG3_GNT_SELECT (1 << 7)
111 u8 CONFIG4; 117 u8 CONFIG4;
112#define RTL818X_CONFIG4_POWEROFF (1 << 6) 118#define RTL818X_CONFIG4_POWEROFF (1 << 6)
113#define RTL818X_CONFIG4_VCOOFF (1 << 7) 119#define RTL818X_CONFIG4_VCOOFF (1 << 7)
@@ -133,7 +139,9 @@ struct rtl818x_csr {
133 __le32 RF_TIMING; 139 __le32 RF_TIMING;
134 u8 GP_ENABLE; 140 u8 GP_ENABLE;
135 u8 GPIO; 141 u8 GPIO;
136 u8 reserved_12[10]; 142 u8 reserved_12[2];
143 __le32 HSSI_PARA;
144 u8 reserved_13[4];
137 u8 TX_AGC_CTL; 145 u8 TX_AGC_CTL;
138#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT (1 << 0) 146#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT (1 << 0)
139#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT (1 << 1) 147#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT (1 << 1)
@@ -141,29 +149,39 @@ struct rtl818x_csr {
141 u8 TX_GAIN_CCK; 149 u8 TX_GAIN_CCK;
142 u8 TX_GAIN_OFDM; 150 u8 TX_GAIN_OFDM;
143 u8 TX_ANTENNA; 151 u8 TX_ANTENNA;
144 u8 reserved_13[16]; 152 u8 reserved_14[16];
145 u8 WPA_CONF; 153 u8 WPA_CONF;
146 u8 reserved_14[3]; 154 u8 reserved_15[3];
147 u8 SIFS; 155 u8 SIFS;
148 u8 DIFS; 156 u8 DIFS;
149 u8 SLOT; 157 u8 SLOT;
150 u8 reserved_15[5]; 158 u8 reserved_16[5];
151 u8 CW_CONF; 159 u8 CW_CONF;
152#define RTL818X_CW_CONF_PERPACKET_CW_SHIFT (1 << 0) 160#define RTL818X_CW_CONF_PERPACKET_CW_SHIFT (1 << 0)
153#define RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT (1 << 1) 161#define RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT (1 << 1)
154 u8 CW_VAL; 162 u8 CW_VAL;
155 u8 RATE_FALLBACK; 163 u8 RATE_FALLBACK;
156 u8 reserved_16[25]; 164#define RTL818X_RATE_FALLBACK_ENABLE (1 << 7)
165 u8 ACM_CONTROL;
166 u8 reserved_17[24];
157 u8 CONFIG5; 167 u8 CONFIG5;
158 u8 TX_DMA_POLLING; 168 u8 TX_DMA_POLLING;
159 u8 reserved_17[2]; 169 u8 reserved_18[2];
160 __le16 CWR; 170 __le16 CWR;
161 u8 RETRY_CTR; 171 u8 RETRY_CTR;
162 u8 reserved_18[5]; 172 u8 reserved_19[3];
173 __le16 INT_MIG;
174/* RTL818X_R8187B_*: magic numbers from ioregisters */
175#define RTL818X_R8187B_B 0
176#define RTL818X_R8187B_D 1
177#define RTL818X_R8187B_E 2
163 __le32 RDSAR; 178 __le32 RDSAR;
164 u8 reserved_19[12]; 179 __le16 TID_AC_MAP;
165 __le16 FEMR;
166 u8 reserved_20[4]; 180 u8 reserved_20[4];
181 u8 ANAPARAM3;
182 u8 reserved_21[5];
183 __le16 FEMR;
184 u8 reserved_22[4];
167 __le16 TALLY_CNT; 185 __le16 TALLY_CNT;
168 u8 TALLY_SEL; 186 u8 TALLY_SEL;
169} __attribute__((packed)); 187} __attribute__((packed));
diff --git a/drivers/net/wireless/wl3501_cs.c b/drivers/net/wireless/wl3501_cs.c
index 42a36b3f3ff7..377141995e36 100644
--- a/drivers/net/wireless/wl3501_cs.c
+++ b/drivers/net/wireless/wl3501_cs.c
@@ -1624,25 +1624,25 @@ static int wl3501_get_scan(struct net_device *dev, struct iw_request_info *info,
1624 iwe.cmd = SIOCGIWAP; 1624 iwe.cmd = SIOCGIWAP;
1625 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 1625 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
1626 memcpy(iwe.u.ap_addr.sa_data, this->bss_set[i].bssid, ETH_ALEN); 1626 memcpy(iwe.u.ap_addr.sa_data, this->bss_set[i].bssid, ETH_ALEN);
1627 current_ev = iwe_stream_add_event(current_ev, 1627 current_ev = iwe_stream_add_event(info, current_ev,
1628 extra + IW_SCAN_MAX_DATA, 1628 extra + IW_SCAN_MAX_DATA,
1629 &iwe, IW_EV_ADDR_LEN); 1629 &iwe, IW_EV_ADDR_LEN);
1630 iwe.cmd = SIOCGIWESSID; 1630 iwe.cmd = SIOCGIWESSID;
1631 iwe.u.data.flags = 1; 1631 iwe.u.data.flags = 1;
1632 iwe.u.data.length = this->bss_set[i].ssid.el.len; 1632 iwe.u.data.length = this->bss_set[i].ssid.el.len;
1633 current_ev = iwe_stream_add_point(current_ev, 1633 current_ev = iwe_stream_add_point(info, current_ev,
1634 extra + IW_SCAN_MAX_DATA, 1634 extra + IW_SCAN_MAX_DATA,
1635 &iwe, 1635 &iwe,
1636 this->bss_set[i].ssid.essid); 1636 this->bss_set[i].ssid.essid);
1637 iwe.cmd = SIOCGIWMODE; 1637 iwe.cmd = SIOCGIWMODE;
1638 iwe.u.mode = this->bss_set[i].bss_type; 1638 iwe.u.mode = this->bss_set[i].bss_type;
1639 current_ev = iwe_stream_add_event(current_ev, 1639 current_ev = iwe_stream_add_event(info, current_ev,
1640 extra + IW_SCAN_MAX_DATA, 1640 extra + IW_SCAN_MAX_DATA,
1641 &iwe, IW_EV_UINT_LEN); 1641 &iwe, IW_EV_UINT_LEN);
1642 iwe.cmd = SIOCGIWFREQ; 1642 iwe.cmd = SIOCGIWFREQ;
1643 iwe.u.freq.m = this->bss_set[i].ds_pset.chan; 1643 iwe.u.freq.m = this->bss_set[i].ds_pset.chan;
1644 iwe.u.freq.e = 0; 1644 iwe.u.freq.e = 0;
1645 current_ev = iwe_stream_add_event(current_ev, 1645 current_ev = iwe_stream_add_event(info, current_ev,
1646 extra + IW_SCAN_MAX_DATA, 1646 extra + IW_SCAN_MAX_DATA,
1647 &iwe, IW_EV_FREQ_LEN); 1647 &iwe, IW_EV_FREQ_LEN);
1648 iwe.cmd = SIOCGIWENCODE; 1648 iwe.cmd = SIOCGIWENCODE;
@@ -1651,7 +1651,7 @@ static int wl3501_get_scan(struct net_device *dev, struct iw_request_info *info,
1651 else 1651 else
1652 iwe.u.data.flags = IW_ENCODE_DISABLED; 1652 iwe.u.data.flags = IW_ENCODE_DISABLED;
1653 iwe.u.data.length = 0; 1653 iwe.u.data.length = 0;
1654 current_ev = iwe_stream_add_point(current_ev, 1654 current_ev = iwe_stream_add_point(info, current_ev,
1655 extra + IW_SCAN_MAX_DATA, 1655 extra + IW_SCAN_MAX_DATA,
1656 &iwe, NULL); 1656 &iwe, NULL);
1657 } 1657 }
diff --git a/drivers/net/wireless/zd1201.c b/drivers/net/wireless/zd1201.c
index 78baa0f7926d..b16ec6e5f0e3 100644
--- a/drivers/net/wireless/zd1201.c
+++ b/drivers/net/wireless/zd1201.c
@@ -1152,32 +1152,36 @@ static int zd1201_get_scan(struct net_device *dev,
1152 iwe.cmd = SIOCGIWAP; 1152 iwe.cmd = SIOCGIWAP;
1153 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 1153 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
1154 memcpy(iwe.u.ap_addr.sa_data, zd->rxdata+i+6, 6); 1154 memcpy(iwe.u.ap_addr.sa_data, zd->rxdata+i+6, 6);
1155 cev = iwe_stream_add_event(cev, end_buf, &iwe, IW_EV_ADDR_LEN); 1155 cev = iwe_stream_add_event(info, cev, end_buf,
1156 &iwe, IW_EV_ADDR_LEN);
1156 1157
1157 iwe.cmd = SIOCGIWESSID; 1158 iwe.cmd = SIOCGIWESSID;
1158 iwe.u.data.length = zd->rxdata[i+16]; 1159 iwe.u.data.length = zd->rxdata[i+16];
1159 iwe.u.data.flags = 1; 1160 iwe.u.data.flags = 1;
1160 cev = iwe_stream_add_point(cev, end_buf, &iwe, zd->rxdata+i+18); 1161 cev = iwe_stream_add_point(info, cev, end_buf,
1162 &iwe, zd->rxdata+i+18);
1161 1163
1162 iwe.cmd = SIOCGIWMODE; 1164 iwe.cmd = SIOCGIWMODE;
1163 if (zd->rxdata[i+14]&0x01) 1165 if (zd->rxdata[i+14]&0x01)
1164 iwe.u.mode = IW_MODE_MASTER; 1166 iwe.u.mode = IW_MODE_MASTER;
1165 else 1167 else
1166 iwe.u.mode = IW_MODE_ADHOC; 1168 iwe.u.mode = IW_MODE_ADHOC;
1167 cev = iwe_stream_add_event(cev, end_buf, &iwe, IW_EV_UINT_LEN); 1169 cev = iwe_stream_add_event(info, cev, end_buf,
1170 &iwe, IW_EV_UINT_LEN);
1168 1171
1169 iwe.cmd = SIOCGIWFREQ; 1172 iwe.cmd = SIOCGIWFREQ;
1170 iwe.u.freq.m = zd->rxdata[i+0]; 1173 iwe.u.freq.m = zd->rxdata[i+0];
1171 iwe.u.freq.e = 0; 1174 iwe.u.freq.e = 0;
1172 cev = iwe_stream_add_event(cev, end_buf, &iwe, IW_EV_FREQ_LEN); 1175 cev = iwe_stream_add_event(info, cev, end_buf,
1176 &iwe, IW_EV_FREQ_LEN);
1173 1177
1174 iwe.cmd = SIOCGIWRATE; 1178 iwe.cmd = SIOCGIWRATE;
1175 iwe.u.bitrate.fixed = 0; 1179 iwe.u.bitrate.fixed = 0;
1176 iwe.u.bitrate.disabled = 0; 1180 iwe.u.bitrate.disabled = 0;
1177 for (j=0; j<10; j++) if (zd->rxdata[i+50+j]) { 1181 for (j=0; j<10; j++) if (zd->rxdata[i+50+j]) {
1178 iwe.u.bitrate.value = (zd->rxdata[i+50+j]&0x7f)*500000; 1182 iwe.u.bitrate.value = (zd->rxdata[i+50+j]&0x7f)*500000;
1179 cev=iwe_stream_add_event(cev, end_buf, &iwe, 1183 cev = iwe_stream_add_event(info, cev, end_buf,
1180 IW_EV_PARAM_LEN); 1184 &iwe, IW_EV_PARAM_LEN);
1181 } 1185 }
1182 1186
1183 iwe.cmd = SIOCGIWENCODE; 1187 iwe.cmd = SIOCGIWENCODE;
@@ -1186,14 +1190,15 @@ static int zd1201_get_scan(struct net_device *dev,
1186 iwe.u.data.flags = IW_ENCODE_ENABLED; 1190 iwe.u.data.flags = IW_ENCODE_ENABLED;
1187 else 1191 else
1188 iwe.u.data.flags = IW_ENCODE_DISABLED; 1192 iwe.u.data.flags = IW_ENCODE_DISABLED;
1189 cev = iwe_stream_add_point(cev, end_buf, &iwe, NULL); 1193 cev = iwe_stream_add_point(info, cev, end_buf, &iwe, NULL);
1190 1194
1191 iwe.cmd = IWEVQUAL; 1195 iwe.cmd = IWEVQUAL;
1192 iwe.u.qual.qual = zd->rxdata[i+4]; 1196 iwe.u.qual.qual = zd->rxdata[i+4];
1193 iwe.u.qual.noise= zd->rxdata[i+2]/10-100; 1197 iwe.u.qual.noise= zd->rxdata[i+2]/10-100;
1194 iwe.u.qual.level = (256+zd->rxdata[i+4]*100)/255-100; 1198 iwe.u.qual.level = (256+zd->rxdata[i+4]*100)/255-100;
1195 iwe.u.qual.updated = 7; 1199 iwe.u.qual.updated = 7;
1196 cev = iwe_stream_add_event(cev, end_buf, &iwe, IW_EV_QUAL_LEN); 1200 cev = iwe_stream_add_event(info, cev, end_buf,
1201 &iwe, IW_EV_QUAL_LEN);
1197 } 1202 }
1198 1203
1199 if (!enabled_save) 1204 if (!enabled_save)
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.c b/drivers/net/wireless/zd1211rw/zd_mac.c
index 694e95d35fd4..fcc532bb6a7e 100644
--- a/drivers/net/wireless/zd1211rw/zd_mac.c
+++ b/drivers/net/wireless/zd1211rw/zd_mac.c
@@ -224,36 +224,6 @@ out:
224 return r; 224 return r;
225} 225}
226 226
227/**
228 * clear_tx_skb_control_block - clears the control block of tx skbuffs
229 * @skb: a &struct sk_buff pointer
230 *
231 * This clears the control block of skbuff buffers, which were transmitted to
232 * the device. Notify that the function is not thread-safe, so prevent
233 * multiple calls.
234 */
235static void clear_tx_skb_control_block(struct sk_buff *skb)
236{
237 struct zd_tx_skb_control_block *cb =
238 (struct zd_tx_skb_control_block *)skb->cb;
239
240 kfree(cb->control);
241 cb->control = NULL;
242}
243
244/**
245 * kfree_tx_skb - frees a tx skbuff
246 * @skb: a &struct sk_buff pointer
247 *
248 * Frees the tx skbuff. Frees also the allocated control structure in the
249 * control block if necessary.
250 */
251static void kfree_tx_skb(struct sk_buff *skb)
252{
253 clear_tx_skb_control_block(skb);
254 dev_kfree_skb_any(skb);
255}
256
257static void zd_op_stop(struct ieee80211_hw *hw) 227static void zd_op_stop(struct ieee80211_hw *hw)
258{ 228{
259 struct zd_mac *mac = zd_hw_mac(hw); 229 struct zd_mac *mac = zd_hw_mac(hw);
@@ -276,40 +246,15 @@ static void zd_op_stop(struct ieee80211_hw *hw)
276 246
277 247
278 while ((skb = skb_dequeue(ack_wait_queue))) 248 while ((skb = skb_dequeue(ack_wait_queue)))
279 kfree_tx_skb(skb); 249 dev_kfree_skb_any(skb);
280}
281
282/**
283 * init_tx_skb_control_block - initializes skb control block
284 * @skb: a &sk_buff pointer
285 * @dev: pointer to the mac80221 device
286 * @control: mac80211 tx control applying for the frame in @skb
287 *
288 * Initializes the control block of the skbuff to be transmitted.
289 */
290static int init_tx_skb_control_block(struct sk_buff *skb,
291 struct ieee80211_hw *hw,
292 struct ieee80211_tx_control *control)
293{
294 struct zd_tx_skb_control_block *cb =
295 (struct zd_tx_skb_control_block *)skb->cb;
296
297 ZD_ASSERT(sizeof(*cb) <= sizeof(skb->cb));
298 memset(cb, 0, sizeof(*cb));
299 cb->hw= hw;
300 cb->control = kmalloc(sizeof(*control), GFP_ATOMIC);
301 if (cb->control == NULL)
302 return -ENOMEM;
303 memcpy(cb->control, control, sizeof(*control));
304
305 return 0;
306} 250}
307 251
308/** 252/**
309 * tx_status - reports tx status of a packet if required 253 * tx_status - reports tx status of a packet if required
310 * @hw - a &struct ieee80211_hw pointer 254 * @hw - a &struct ieee80211_hw pointer
311 * @skb - a sk-buffer 255 * @skb - a sk-buffer
312 * @status - the tx status of the packet without control information 256 * @flags: extra flags to set in the TX status info
257 * @ackssi: ACK signal strength
313 * @success - True for successfull transmission of the frame 258 * @success - True for successfull transmission of the frame
314 * 259 *
315 * This information calls ieee80211_tx_status_irqsafe() if required by the 260 * This information calls ieee80211_tx_status_irqsafe() if required by the
@@ -319,18 +264,17 @@ static int init_tx_skb_control_block(struct sk_buff *skb,
319 * If no status information has been requested, the skb is freed. 264 * If no status information has been requested, the skb is freed.
320 */ 265 */
321static void tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, 266static void tx_status(struct ieee80211_hw *hw, struct sk_buff *skb,
322 struct ieee80211_tx_status *status, 267 u32 flags, int ackssi, bool success)
323 bool success)
324{ 268{
325 struct zd_tx_skb_control_block *cb = (struct zd_tx_skb_control_block *) 269 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
326 skb->cb; 270
271 memset(&info->status, 0, sizeof(info->status));
327 272
328 ZD_ASSERT(cb->control != NULL);
329 memcpy(&status->control, cb->control, sizeof(status->control));
330 if (!success) 273 if (!success)
331 status->excessive_retries = 1; 274 info->status.excessive_retries = 1;
332 clear_tx_skb_control_block(skb); 275 info->flags |= flags;
333 ieee80211_tx_status_irqsafe(hw, skb, status); 276 info->status.ack_signal = ackssi;
277 ieee80211_tx_status_irqsafe(hw, skb);
334} 278}
335 279
336/** 280/**
@@ -345,15 +289,12 @@ void zd_mac_tx_failed(struct ieee80211_hw *hw)
345{ 289{
346 struct sk_buff_head *q = &zd_hw_mac(hw)->ack_wait_queue; 290 struct sk_buff_head *q = &zd_hw_mac(hw)->ack_wait_queue;
347 struct sk_buff *skb; 291 struct sk_buff *skb;
348 struct ieee80211_tx_status status;
349 292
350 skb = skb_dequeue(q); 293 skb = skb_dequeue(q);
351 if (skb == NULL) 294 if (skb == NULL)
352 return; 295 return;
353 296
354 memset(&status, 0, sizeof(status)); 297 tx_status(hw, skb, 0, 0, 0);
355
356 tx_status(hw, skb, &status, 0);
357} 298}
358 299
359/** 300/**
@@ -368,28 +309,20 @@ void zd_mac_tx_failed(struct ieee80211_hw *hw)
368 */ 309 */
369void zd_mac_tx_to_dev(struct sk_buff *skb, int error) 310void zd_mac_tx_to_dev(struct sk_buff *skb, int error)
370{ 311{
371 struct zd_tx_skb_control_block *cb = 312 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
372 (struct zd_tx_skb_control_block *)skb->cb; 313 struct ieee80211_hw *hw = info->driver_data[0];
373 struct ieee80211_hw *hw = cb->hw;
374
375 if (likely(cb->control)) {
376 skb_pull(skb, sizeof(struct zd_ctrlset));
377 if (unlikely(error ||
378 (cb->control->flags & IEEE80211_TXCTL_NO_ACK)))
379 {
380 struct ieee80211_tx_status status;
381 memset(&status, 0, sizeof(status));
382 tx_status(hw, skb, &status, !error);
383 } else {
384 struct sk_buff_head *q =
385 &zd_hw_mac(hw)->ack_wait_queue;
386 314
387 skb_queue_tail(q, skb); 315 skb_pull(skb, sizeof(struct zd_ctrlset));
388 while (skb_queue_len(q) > ZD_MAC_MAX_ACK_WAITERS) 316 if (unlikely(error ||
389 zd_mac_tx_failed(hw); 317 (info->flags & IEEE80211_TX_CTL_NO_ACK))) {
390 } 318 tx_status(hw, skb, 0, 0, !error);
391 } else { 319 } else {
392 kfree_tx_skb(skb); 320 struct sk_buff_head *q =
321 &zd_hw_mac(hw)->ack_wait_queue;
322
323 skb_queue_tail(q, skb);
324 while (skb_queue_len(q) > ZD_MAC_MAX_ACK_WAITERS)
325 zd_mac_tx_failed(hw);
393 } 326 }
394} 327}
395 328
@@ -443,8 +376,6 @@ static int zd_calc_tx_length_us(u8 *service, u8 zd_rate, u16 tx_length)
443static void cs_set_control(struct zd_mac *mac, struct zd_ctrlset *cs, 376static void cs_set_control(struct zd_mac *mac, struct zd_ctrlset *cs,
444 struct ieee80211_hdr *header, u32 flags) 377 struct ieee80211_hdr *header, u32 flags)
445{ 378{
446 u16 fctl = le16_to_cpu(header->frame_control);
447
448 /* 379 /*
449 * CONTROL TODO: 380 * CONTROL TODO:
450 * - if backoff needed, enable bit 0 381 * - if backoff needed, enable bit 0
@@ -454,7 +385,7 @@ static void cs_set_control(struct zd_mac *mac, struct zd_ctrlset *cs,
454 cs->control = 0; 385 cs->control = 0;
455 386
456 /* First fragment */ 387 /* First fragment */
457 if (flags & IEEE80211_TXCTL_FIRST_FRAGMENT) 388 if (flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
458 cs->control |= ZD_CS_NEED_RANDOM_BACKOFF; 389 cs->control |= ZD_CS_NEED_RANDOM_BACKOFF;
459 390
460 /* Multicast */ 391 /* Multicast */
@@ -462,79 +393,104 @@ static void cs_set_control(struct zd_mac *mac, struct zd_ctrlset *cs,
462 cs->control |= ZD_CS_MULTICAST; 393 cs->control |= ZD_CS_MULTICAST;
463 394
464 /* PS-POLL */ 395 /* PS-POLL */
465 if ((fctl & (IEEE80211_FCTL_FTYPE|IEEE80211_FCTL_STYPE)) == 396 if (ieee80211_is_pspoll(header->frame_control))
466 (IEEE80211_FTYPE_CTL|IEEE80211_STYPE_PSPOLL))
467 cs->control |= ZD_CS_PS_POLL_FRAME; 397 cs->control |= ZD_CS_PS_POLL_FRAME;
468 398
469 if (flags & IEEE80211_TXCTL_USE_RTS_CTS) 399 if (flags & IEEE80211_TX_CTL_USE_RTS_CTS)
470 cs->control |= ZD_CS_RTS; 400 cs->control |= ZD_CS_RTS;
471 401
472 if (flags & IEEE80211_TXCTL_USE_CTS_PROTECT) 402 if (flags & IEEE80211_TX_CTL_USE_CTS_PROTECT)
473 cs->control |= ZD_CS_SELF_CTS; 403 cs->control |= ZD_CS_SELF_CTS;
474 404
475 /* FIXME: Management frame? */ 405 /* FIXME: Management frame? */
476} 406}
477 407
478void zd_mac_config_beacon(struct ieee80211_hw *hw, struct sk_buff *beacon) 408static int zd_mac_config_beacon(struct ieee80211_hw *hw, struct sk_buff *beacon)
479{ 409{
480 struct zd_mac *mac = zd_hw_mac(hw); 410 struct zd_mac *mac = zd_hw_mac(hw);
411 int r;
481 u32 tmp, j = 0; 412 u32 tmp, j = 0;
482 /* 4 more bytes for tail CRC */ 413 /* 4 more bytes for tail CRC */
483 u32 full_len = beacon->len + 4; 414 u32 full_len = beacon->len + 4;
484 zd_iowrite32(&mac->chip, CR_BCN_FIFO_SEMAPHORE, 0); 415
485 zd_ioread32(&mac->chip, CR_BCN_FIFO_SEMAPHORE, &tmp); 416 r = zd_iowrite32(&mac->chip, CR_BCN_FIFO_SEMAPHORE, 0);
417 if (r < 0)
418 return r;
419 r = zd_ioread32(&mac->chip, CR_BCN_FIFO_SEMAPHORE, &tmp);
420 if (r < 0)
421 return r;
422
486 while (tmp & 0x2) { 423 while (tmp & 0x2) {
487 zd_ioread32(&mac->chip, CR_BCN_FIFO_SEMAPHORE, &tmp); 424 r = zd_ioread32(&mac->chip, CR_BCN_FIFO_SEMAPHORE, &tmp);
425 if (r < 0)
426 return r;
488 if ((++j % 100) == 0) { 427 if ((++j % 100) == 0) {
489 printk(KERN_ERR "CR_BCN_FIFO_SEMAPHORE not ready\n"); 428 printk(KERN_ERR "CR_BCN_FIFO_SEMAPHORE not ready\n");
490 if (j >= 500) { 429 if (j >= 500) {
491 printk(KERN_ERR "Giving up beacon config.\n"); 430 printk(KERN_ERR "Giving up beacon config.\n");
492 return; 431 return -ETIMEDOUT;
493 } 432 }
494 } 433 }
495 msleep(1); 434 msleep(1);
496 } 435 }
497 436
498 zd_iowrite32(&mac->chip, CR_BCN_FIFO, full_len - 1); 437 r = zd_iowrite32(&mac->chip, CR_BCN_FIFO, full_len - 1);
499 if (zd_chip_is_zd1211b(&mac->chip)) 438 if (r < 0)
500 zd_iowrite32(&mac->chip, CR_BCN_LENGTH, full_len - 1); 439 return r;
440 if (zd_chip_is_zd1211b(&mac->chip)) {
441 r = zd_iowrite32(&mac->chip, CR_BCN_LENGTH, full_len - 1);
442 if (r < 0)
443 return r;
444 }
501 445
502 for (j = 0 ; j < beacon->len; j++) 446 for (j = 0 ; j < beacon->len; j++) {
503 zd_iowrite32(&mac->chip, CR_BCN_FIFO, 447 r = zd_iowrite32(&mac->chip, CR_BCN_FIFO,
504 *((u8 *)(beacon->data + j))); 448 *((u8 *)(beacon->data + j)));
449 if (r < 0)
450 return r;
451 }
452
453 for (j = 0; j < 4; j++) {
454 r = zd_iowrite32(&mac->chip, CR_BCN_FIFO, 0x0);
455 if (r < 0)
456 return r;
457 }
505 458
506 for (j = 0; j < 4; j++) 459 r = zd_iowrite32(&mac->chip, CR_BCN_FIFO_SEMAPHORE, 1);
507 zd_iowrite32(&mac->chip, CR_BCN_FIFO, 0x0); 460 if (r < 0)
461 return r;
508 462
509 zd_iowrite32(&mac->chip, CR_BCN_FIFO_SEMAPHORE, 1);
510 /* 802.11b/g 2.4G CCK 1Mb 463 /* 802.11b/g 2.4G CCK 1Mb
511 * 802.11a, not yet implemented, uses different values (see GPL vendor 464 * 802.11a, not yet implemented, uses different values (see GPL vendor
512 * driver) 465 * driver)
513 */ 466 */
514 zd_iowrite32(&mac->chip, CR_BCN_PLCP_CFG, 0x00000400 | 467 return zd_iowrite32(&mac->chip, CR_BCN_PLCP_CFG, 0x00000400 |
515 (full_len << 19)); 468 (full_len << 19));
516} 469}
517 470
518static int fill_ctrlset(struct zd_mac *mac, 471static int fill_ctrlset(struct zd_mac *mac,
519 struct sk_buff *skb, 472 struct sk_buff *skb)
520 struct ieee80211_tx_control *control)
521{ 473{
522 int r; 474 int r;
523 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 475 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
524 unsigned int frag_len = skb->len + FCS_LEN; 476 unsigned int frag_len = skb->len + FCS_LEN;
525 unsigned int packet_length; 477 unsigned int packet_length;
478 struct ieee80211_rate *txrate;
526 struct zd_ctrlset *cs = (struct zd_ctrlset *) 479 struct zd_ctrlset *cs = (struct zd_ctrlset *)
527 skb_push(skb, sizeof(struct zd_ctrlset)); 480 skb_push(skb, sizeof(struct zd_ctrlset));
481 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
528 482
529 ZD_ASSERT(frag_len <= 0xffff); 483 ZD_ASSERT(frag_len <= 0xffff);
530 484
531 cs->modulation = control->tx_rate->hw_value; 485 txrate = ieee80211_get_tx_rate(mac->hw, info);
532 if (control->flags & IEEE80211_TXCTL_SHORT_PREAMBLE) 486
533 cs->modulation = control->tx_rate->hw_value_short; 487 cs->modulation = txrate->hw_value;
488 if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE)
489 cs->modulation = txrate->hw_value_short;
534 490
535 cs->tx_length = cpu_to_le16(frag_len); 491 cs->tx_length = cpu_to_le16(frag_len);
536 492
537 cs_set_control(mac, cs, hdr, control->flags); 493 cs_set_control(mac, cs, hdr, info->flags);
538 494
539 packet_length = frag_len + sizeof(struct zd_ctrlset) + 10; 495 packet_length = frag_len + sizeof(struct zd_ctrlset) + 10;
540 ZD_ASSERT(packet_length <= 0xffff); 496 ZD_ASSERT(packet_length <= 0xffff);
@@ -579,24 +535,21 @@ static int fill_ctrlset(struct zd_mac *mac,
579 * control block of the skbuff will be initialized. If necessary the incoming 535 * control block of the skbuff will be initialized. If necessary the incoming
580 * mac80211 queues will be stopped. 536 * mac80211 queues will be stopped.
581 */ 537 */
582static int zd_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb, 538static int zd_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
583 struct ieee80211_tx_control *control)
584{ 539{
585 struct zd_mac *mac = zd_hw_mac(hw); 540 struct zd_mac *mac = zd_hw_mac(hw);
541 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
586 int r; 542 int r;
587 543
588 r = fill_ctrlset(mac, skb, control); 544 r = fill_ctrlset(mac, skb);
589 if (r) 545 if (r)
590 return r; 546 return r;
591 547
592 r = init_tx_skb_control_block(skb, hw, control); 548 info->driver_data[0] = hw;
593 if (r) 549
594 return r;
595 r = zd_usb_tx(&mac->chip.usb, skb); 550 r = zd_usb_tx(&mac->chip.usb, skb);
596 if (r) { 551 if (r)
597 clear_tx_skb_control_block(skb);
598 return r; 552 return r;
599 }
600 return 0; 553 return 0;
601} 554}
602 555
@@ -617,13 +570,11 @@ static int zd_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
617static int filter_ack(struct ieee80211_hw *hw, struct ieee80211_hdr *rx_hdr, 570static int filter_ack(struct ieee80211_hw *hw, struct ieee80211_hdr *rx_hdr,
618 struct ieee80211_rx_status *stats) 571 struct ieee80211_rx_status *stats)
619{ 572{
620 u16 fc = le16_to_cpu(rx_hdr->frame_control);
621 struct sk_buff *skb; 573 struct sk_buff *skb;
622 struct sk_buff_head *q; 574 struct sk_buff_head *q;
623 unsigned long flags; 575 unsigned long flags;
624 576
625 if ((fc & (IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) != 577 if (!ieee80211_is_ack(rx_hdr->frame_control))
626 (IEEE80211_FTYPE_CTL | IEEE80211_STYPE_ACK))
627 return 0; 578 return 0;
628 579
629 q = &zd_hw_mac(hw)->ack_wait_queue; 580 q = &zd_hw_mac(hw)->ack_wait_queue;
@@ -634,13 +585,8 @@ static int filter_ack(struct ieee80211_hw *hw, struct ieee80211_hdr *rx_hdr,
634 tx_hdr = (struct ieee80211_hdr *)skb->data; 585 tx_hdr = (struct ieee80211_hdr *)skb->data;
635 if (likely(!compare_ether_addr(tx_hdr->addr2, rx_hdr->addr1))) 586 if (likely(!compare_ether_addr(tx_hdr->addr2, rx_hdr->addr1)))
636 { 587 {
637 struct ieee80211_tx_status status;
638
639 memset(&status, 0, sizeof(status));
640 status.flags = IEEE80211_TX_STATUS_ACK;
641 status.ack_signal = stats->ssi;
642 __skb_unlink(skb, q); 588 __skb_unlink(skb, q);
643 tx_status(hw, skb, &status, 1); 589 tx_status(hw, skb, IEEE80211_TX_STAT_ACK, stats->signal, 1);
644 goto out; 590 goto out;
645 } 591 }
646 } 592 }
@@ -656,8 +602,8 @@ int zd_mac_rx(struct ieee80211_hw *hw, const u8 *buffer, unsigned int length)
656 const struct rx_status *status; 602 const struct rx_status *status;
657 struct sk_buff *skb; 603 struct sk_buff *skb;
658 int bad_frame = 0; 604 int bad_frame = 0;
659 u16 fc; 605 __le16 fc;
660 bool is_qos, is_4addr, need_padding; 606 int need_padding;
661 int i; 607 int i;
662 u8 rate; 608 u8 rate;
663 609
@@ -691,8 +637,8 @@ int zd_mac_rx(struct ieee80211_hw *hw, const u8 *buffer, unsigned int length)
691 637
692 stats.freq = zd_channels[_zd_chip_get_channel(&mac->chip) - 1].center_freq; 638 stats.freq = zd_channels[_zd_chip_get_channel(&mac->chip) - 1].center_freq;
693 stats.band = IEEE80211_BAND_2GHZ; 639 stats.band = IEEE80211_BAND_2GHZ;
694 stats.ssi = status->signal_strength; 640 stats.signal = status->signal_strength;
695 stats.signal = zd_rx_qual_percent(buffer, 641 stats.qual = zd_rx_qual_percent(buffer,
696 length - sizeof(struct rx_status), 642 length - sizeof(struct rx_status),
697 status); 643 status);
698 644
@@ -716,13 +662,8 @@ int zd_mac_rx(struct ieee80211_hw *hw, const u8 *buffer, unsigned int length)
716 && !mac->pass_ctrl) 662 && !mac->pass_ctrl)
717 return 0; 663 return 0;
718 664
719 fc = le16_to_cpu(*((__le16 *) buffer)); 665 fc = *(__le16 *)buffer;
720 666 need_padding = ieee80211_is_data_qos(fc) ^ ieee80211_has_a4(fc);
721 is_qos = ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) &&
722 (fc & IEEE80211_STYPE_QOS_DATA);
723 is_4addr = (fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) ==
724 (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS);
725 need_padding = is_qos ^ is_4addr;
726 667
727 skb = dev_alloc_skb(length + (need_padding ? 2 : 0)); 668 skb = dev_alloc_skb(length + (need_padding ? 2 : 0));
728 if (skb == NULL) 669 if (skb == NULL)
@@ -751,6 +692,7 @@ static int zd_op_add_interface(struct ieee80211_hw *hw,
751 case IEEE80211_IF_TYPE_MNTR: 692 case IEEE80211_IF_TYPE_MNTR:
752 case IEEE80211_IF_TYPE_MESH_POINT: 693 case IEEE80211_IF_TYPE_MESH_POINT:
753 case IEEE80211_IF_TYPE_STA: 694 case IEEE80211_IF_TYPE_STA:
695 case IEEE80211_IF_TYPE_IBSS:
754 mac->type = conf->type; 696 mac->type = conf->type;
755 break; 697 break;
756 default: 698 default:
@@ -781,14 +723,24 @@ static int zd_op_config_interface(struct ieee80211_hw *hw,
781{ 723{
782 struct zd_mac *mac = zd_hw_mac(hw); 724 struct zd_mac *mac = zd_hw_mac(hw);
783 int associated; 725 int associated;
726 int r;
784 727
785 if (mac->type == IEEE80211_IF_TYPE_MESH_POINT) { 728 if (mac->type == IEEE80211_IF_TYPE_MESH_POINT ||
729 mac->type == IEEE80211_IF_TYPE_IBSS) {
786 associated = true; 730 associated = true;
787 if (conf->beacon) { 731 if (conf->changed & IEEE80211_IFCC_BEACON) {
788 zd_mac_config_beacon(hw, conf->beacon); 732 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
789 kfree_skb(conf->beacon); 733
790 zd_set_beacon_interval(&mac->chip, BCN_MODE_IBSS | 734 if (!beacon)
735 return -ENOMEM;
736 r = zd_mac_config_beacon(hw, beacon);
737 if (r < 0)
738 return r;
739 r = zd_set_beacon_interval(&mac->chip, BCN_MODE_IBSS |
791 hw->conf.beacon_int); 740 hw->conf.beacon_int);
741 if (r < 0)
742 return r;
743 kfree_skb(beacon);
792 } 744 }
793 } else 745 } else
794 associated = is_valid_ether_addr(conf->bssid); 746 associated = is_valid_ether_addr(conf->bssid);
@@ -983,10 +935,10 @@ struct ieee80211_hw *zd_mac_alloc_hw(struct usb_interface *intf)
983 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &mac->band; 935 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &mac->band;
984 936
985 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 937 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
986 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE; 938 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
987 hw->max_rssi = 100; 939 IEEE80211_HW_SIGNAL_DB;
988 hw->max_signal = 100;
989 940
941 hw->max_signal = 100;
990 hw->queues = 1; 942 hw->queues = 1;
991 hw->extra_tx_headroom = sizeof(struct zd_ctrlset); 943 hw->extra_tx_headroom = sizeof(struct zd_ctrlset);
992 944
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.h b/drivers/net/wireless/zd1211rw/zd_mac.h
index 71170244d2c9..18c1d56d3dd7 100644
--- a/drivers/net/wireless/zd1211rw/zd_mac.h
+++ b/drivers/net/wireless/zd1211rw/zd_mac.h
@@ -149,22 +149,6 @@ struct housekeeping {
149 struct delayed_work link_led_work; 149 struct delayed_work link_led_work;
150}; 150};
151 151
152/**
153 * struct zd_tx_skb_control_block - control block for tx skbuffs
154 * @control: &struct ieee80211_tx_control pointer
155 * @context: context pointer
156 *
157 * This structure is used to fill the cb field in an &sk_buff to transmit.
158 * The control field is NULL, if there is no requirement from the mac80211
159 * stack to report about the packet ACK. This is the case if the flag
160 * IEEE80211_TXCTL_NO_ACK is not set in &struct ieee80211_tx_control.
161 */
162struct zd_tx_skb_control_block {
163 struct ieee80211_tx_control *control;
164 struct ieee80211_hw *hw;
165 void *context;
166};
167
168#define ZD_MAC_STATS_BUFFER_SIZE 16 152#define ZD_MAC_STATS_BUFFER_SIZE 16
169 153
170#define ZD_MAC_MAX_ACK_WAITERS 10 154#define ZD_MAC_MAX_ACK_WAITERS 10
diff --git a/drivers/net/wireless/zd1211rw/zd_usb.c b/drivers/net/wireless/zd1211rw/zd_usb.c
index 6cdad9764604..da8b7433e3a6 100644
--- a/drivers/net/wireless/zd1211rw/zd_usb.c
+++ b/drivers/net/wireless/zd1211rw/zd_usb.c
@@ -170,10 +170,11 @@ static int upload_code(struct usb_device *udev,
170 if (flags & REBOOT) { 170 if (flags & REBOOT) {
171 u8 ret; 171 u8 ret;
172 172
173 /* Use "DMA-aware" buffer. */
173 r = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 174 r = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
174 USB_REQ_FIRMWARE_CONFIRM, 175 USB_REQ_FIRMWARE_CONFIRM,
175 USB_DIR_IN | USB_TYPE_VENDOR, 176 USB_DIR_IN | USB_TYPE_VENDOR,
176 0, 0, &ret, sizeof(ret), 5000 /* ms */); 177 0, 0, p, sizeof(ret), 5000 /* ms */);
177 if (r != sizeof(ret)) { 178 if (r != sizeof(ret)) {
178 dev_err(&udev->dev, 179 dev_err(&udev->dev,
179 "control request firmeware confirmation failed." 180 "control request firmeware confirmation failed."
@@ -182,6 +183,7 @@ static int upload_code(struct usb_device *udev,
182 r = -ENODEV; 183 r = -ENODEV;
183 goto error; 184 goto error;
184 } 185 }
186 ret = p[0];
185 if (ret & 0x80) { 187 if (ret & 0x80) {
186 dev_err(&udev->dev, 188 dev_err(&udev->dev,
187 "Internal error while downloading." 189 "Internal error while downloading."
@@ -313,22 +315,31 @@ int zd_usb_read_fw(struct zd_usb *usb, zd_addr_t addr, u8 *data, u16 len)
313{ 315{
314 int r; 316 int r;
315 struct usb_device *udev = zd_usb_to_usbdev(usb); 317 struct usb_device *udev = zd_usb_to_usbdev(usb);
318 u8 *buf;
316 319
320 /* Use "DMA-aware" buffer. */
321 buf = kmalloc(len, GFP_KERNEL);
322 if (!buf)
323 return -ENOMEM;
317 r = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 324 r = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
318 USB_REQ_FIRMWARE_READ_DATA, USB_DIR_IN | 0x40, addr, 0, 325 USB_REQ_FIRMWARE_READ_DATA, USB_DIR_IN | 0x40, addr, 0,
319 data, len, 5000); 326 buf, len, 5000);
320 if (r < 0) { 327 if (r < 0) {
321 dev_err(&udev->dev, 328 dev_err(&udev->dev,
322 "read over firmware interface failed: %d\n", r); 329 "read over firmware interface failed: %d\n", r);
323 return r; 330 goto exit;
324 } else if (r != len) { 331 } else if (r != len) {
325 dev_err(&udev->dev, 332 dev_err(&udev->dev,
326 "incomplete read over firmware interface: %d/%d\n", 333 "incomplete read over firmware interface: %d/%d\n",
327 r, len); 334 r, len);
328 return -EIO; 335 r = -EIO;
336 goto exit;
329 } 337 }
330 338 r = 0;
331 return 0; 339 memcpy(data, buf, len);
340exit:
341 kfree(buf);
342 return r;
332} 343}
333 344
334#define urb_dev(urb) (&(urb)->dev->dev) 345#define urb_dev(urb) (&(urb)->dev->dev)
@@ -870,7 +881,7 @@ static void tx_urb_complete(struct urb *urb)
870{ 881{
871 int r; 882 int r;
872 struct sk_buff *skb; 883 struct sk_buff *skb;
873 struct zd_tx_skb_control_block *cb; 884 struct ieee80211_tx_info *info;
874 struct zd_usb *usb; 885 struct zd_usb *usb;
875 886
876 switch (urb->status) { 887 switch (urb->status) {
@@ -894,8 +905,8 @@ free_urb:
894 * grab 'usb' pointer before handing off the skb (since 905 * grab 'usb' pointer before handing off the skb (since
895 * it might be freed by zd_mac_tx_to_dev or mac80211) 906 * it might be freed by zd_mac_tx_to_dev or mac80211)
896 */ 907 */
897 cb = (struct zd_tx_skb_control_block *)skb->cb; 908 info = IEEE80211_SKB_CB(skb);
898 usb = &zd_hw_mac(cb->hw)->chip.usb; 909 usb = &zd_hw_mac(info->driver_data[0])->chip.usb;
899 zd_mac_tx_to_dev(skb, urb->status); 910 zd_mac_tx_to_dev(skb, urb->status);
900 free_tx_urb(usb, urb); 911 free_tx_urb(usb, urb);
901 tx_dec_submitted_urbs(usb); 912 tx_dec_submitted_urbs(usb);