diff options
author | David S. Miller <davem@davemloft.net> | 2008-10-10 17:43:54 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-10-10 17:43:54 -0400 |
commit | 6861ff35ec5b60fafaf8651754c9a75142bfa9a4 (patch) | |
tree | 27e634a97c0325e1b1f8f08562be2e9c12cc5247 /drivers/net | |
parent | 2ef3783608668a32e497a16cb8696cee9b0aa47c (diff) | |
parent | 1765f95d2db0a516b5816e016fdf459c4bb5affb (diff) |
Merge branch 'r8169' of git://git.kernel.org/pub/scm/linux/kernel/git/romieu/netdev-2.6
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/r8169.c | 457 |
1 files changed, 434 insertions, 23 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 59fbc64d7c47..bdae2c59a750 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c | |||
@@ -109,7 +109,12 @@ enum mac_version { | |||
109 | RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf | 109 | RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf |
110 | RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP | 110 | RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP |
111 | RTL_GIGA_MAC_VER_19 = 0x13, // 8168C | 111 | RTL_GIGA_MAC_VER_19 = 0x13, // 8168C |
112 | RTL_GIGA_MAC_VER_20 = 0x14 // 8168C | 112 | RTL_GIGA_MAC_VER_20 = 0x14, // 8168C |
113 | RTL_GIGA_MAC_VER_21 = 0x15, // 8168C | ||
114 | RTL_GIGA_MAC_VER_22 = 0x16, // 8168C | ||
115 | RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP | ||
116 | RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP | ||
117 | RTL_GIGA_MAC_VER_25 = 0x19 // 8168D | ||
113 | }; | 118 | }; |
114 | 119 | ||
115 | #define _R(NAME,MAC,MASK) \ | 120 | #define _R(NAME,MAC,MASK) \ |
@@ -139,7 +144,12 @@ static const struct { | |||
139 | _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E | 144 | _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E |
140 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E | 145 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E |
141 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E | 146 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E |
142 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E | 147 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E |
148 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E | ||
149 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E | ||
150 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E | ||
151 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E | ||
152 | _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E | ||
143 | }; | 153 | }; |
144 | #undef _R | 154 | #undef _R |
145 | 155 | ||
@@ -865,9 +875,13 @@ static int rtl8169_set_speed_xmii(struct net_device *dev, | |||
865 | 875 | ||
866 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | 876 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
867 | 877 | ||
868 | if ((tp->mac_version == RTL_GIGA_MAC_VER_12) || | 878 | if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || |
869 | (tp->mac_version == RTL_GIGA_MAC_VER_17)) { | 879 | (tp->mac_version == RTL_GIGA_MAC_VER_12) || |
870 | /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */ | 880 | (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { |
881 | /* | ||
882 | * Wake up the PHY. | ||
883 | * Vendor specific (0x1f) and reserved (0x0e) MII registers. | ||
884 | */ | ||
871 | mdio_write(ioaddr, 0x1f, 0x0000); | 885 | mdio_write(ioaddr, 0x1f, 0x0000); |
872 | mdio_write(ioaddr, 0x0e, 0x0000); | 886 | mdio_write(ioaddr, 0x0e, 0x0000); |
873 | } | 887 | } |
@@ -1212,11 +1226,19 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, | |||
1212 | u32 val; | 1226 | u32 val; |
1213 | int mac_version; | 1227 | int mac_version; |
1214 | } mac_info[] = { | 1228 | } mac_info[] = { |
1215 | /* 8168B family. */ | 1229 | /* 8168D family. */ |
1216 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, | 1230 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 }, |
1231 | |||
1232 | /* 8168C family. */ | ||
1233 | { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 }, | ||
1234 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, | ||
1235 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, | ||
1236 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, | ||
1217 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, | 1237 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
1218 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | 1238 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, |
1219 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 }, | 1239 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
1240 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, | ||
1241 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, | ||
1220 | 1242 | ||
1221 | /* 8168B family. */ | 1243 | /* 8168B family. */ |
1222 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | 1244 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, |
@@ -1346,7 +1368,31 @@ static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) | |||
1346 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | 1368 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1347 | } | 1369 | } |
1348 | 1370 | ||
1349 | static void rtl8168cp_hw_phy_config(void __iomem *ioaddr) | 1371 | static void rtl8168bb_hw_phy_config(void __iomem *ioaddr) |
1372 | { | ||
1373 | struct phy_reg phy_reg_init[] = { | ||
1374 | { 0x10, 0xf41b }, | ||
1375 | { 0x1f, 0x0000 } | ||
1376 | }; | ||
1377 | |||
1378 | mdio_write(ioaddr, 0x1f, 0x0001); | ||
1379 | mdio_patch(ioaddr, 0x16, 1 << 0); | ||
1380 | |||
1381 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | ||
1382 | } | ||
1383 | |||
1384 | static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) | ||
1385 | { | ||
1386 | struct phy_reg phy_reg_init[] = { | ||
1387 | { 0x1f, 0x0001 }, | ||
1388 | { 0x10, 0xf41b }, | ||
1389 | { 0x1f, 0x0000 } | ||
1390 | }; | ||
1391 | |||
1392 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | ||
1393 | } | ||
1394 | |||
1395 | static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) | ||
1350 | { | 1396 | { |
1351 | struct phy_reg phy_reg_init[] = { | 1397 | struct phy_reg phy_reg_init[] = { |
1352 | { 0x1f, 0x0000 }, | 1398 | { 0x1f, 0x0000 }, |
@@ -1359,7 +1405,22 @@ static void rtl8168cp_hw_phy_config(void __iomem *ioaddr) | |||
1359 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | 1405 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1360 | } | 1406 | } |
1361 | 1407 | ||
1362 | static void rtl8168c_hw_phy_config(void __iomem *ioaddr) | 1408 | static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) |
1409 | { | ||
1410 | struct phy_reg phy_reg_init[] = { | ||
1411 | { 0x1f, 0x0001 }, | ||
1412 | { 0x1d, 0x3d98 }, | ||
1413 | { 0x1f, 0x0000 } | ||
1414 | }; | ||
1415 | |||
1416 | mdio_write(ioaddr, 0x1f, 0x0000); | ||
1417 | mdio_patch(ioaddr, 0x14, 1 << 5); | ||
1418 | mdio_patch(ioaddr, 0x0d, 1 << 5); | ||
1419 | |||
1420 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | ||
1421 | } | ||
1422 | |||
1423 | static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) | ||
1363 | { | 1424 | { |
1364 | struct phy_reg phy_reg_init[] = { | 1425 | struct phy_reg phy_reg_init[] = { |
1365 | { 0x1f, 0x0001 }, | 1426 | { 0x1f, 0x0001 }, |
@@ -1375,26 +1436,142 @@ static void rtl8168c_hw_phy_config(void __iomem *ioaddr) | |||
1375 | { 0x1f, 0x0003 }, | 1436 | { 0x1f, 0x0003 }, |
1376 | { 0x12, 0xc096 }, | 1437 | { 0x12, 0xc096 }, |
1377 | { 0x16, 0x000a }, | 1438 | { 0x16, 0x000a }, |
1378 | { 0x1f, 0x0000 } | 1439 | { 0x1f, 0x0000 }, |
1440 | { 0x1f, 0x0000 }, | ||
1441 | { 0x09, 0x2000 }, | ||
1442 | { 0x09, 0x0000 } | ||
1379 | }; | 1443 | }; |
1380 | 1444 | ||
1381 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | 1445 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1446 | |||
1447 | mdio_patch(ioaddr, 0x14, 1 << 5); | ||
1448 | mdio_patch(ioaddr, 0x0d, 1 << 5); | ||
1449 | mdio_write(ioaddr, 0x1f, 0x0000); | ||
1382 | } | 1450 | } |
1383 | 1451 | ||
1384 | static void rtl8168cx_hw_phy_config(void __iomem *ioaddr) | 1452 | static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) |
1385 | { | 1453 | { |
1386 | struct phy_reg phy_reg_init[] = { | 1454 | struct phy_reg phy_reg_init[] = { |
1387 | { 0x1f, 0x0000 }, | 1455 | { 0x1f, 0x0001 }, |
1388 | { 0x12, 0x2300 }, | 1456 | { 0x12, 0x2300 }, |
1457 | { 0x03, 0x802f }, | ||
1458 | { 0x02, 0x4f02 }, | ||
1459 | { 0x01, 0x0409 }, | ||
1460 | { 0x00, 0xf099 }, | ||
1461 | { 0x04, 0x9800 }, | ||
1462 | { 0x04, 0x9000 }, | ||
1463 | { 0x1d, 0x3d98 }, | ||
1464 | { 0x1f, 0x0002 }, | ||
1465 | { 0x0c, 0x7eb8 }, | ||
1466 | { 0x06, 0x0761 }, | ||
1389 | { 0x1f, 0x0003 }, | 1467 | { 0x1f, 0x0003 }, |
1390 | { 0x16, 0x0f0a }, | 1468 | { 0x16, 0x0f0a }, |
1391 | { 0x1f, 0x0000 }, | 1469 | { 0x1f, 0x0000 } |
1470 | }; | ||
1471 | |||
1472 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | ||
1473 | |||
1474 | mdio_patch(ioaddr, 0x16, 1 << 0); | ||
1475 | mdio_patch(ioaddr, 0x14, 1 << 5); | ||
1476 | mdio_patch(ioaddr, 0x0d, 1 << 5); | ||
1477 | mdio_write(ioaddr, 0x1f, 0x0000); | ||
1478 | } | ||
1479 | |||
1480 | static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) | ||
1481 | { | ||
1482 | struct phy_reg phy_reg_init[] = { | ||
1483 | { 0x1f, 0x0001 }, | ||
1484 | { 0x12, 0x2300 }, | ||
1485 | { 0x1d, 0x3d98 }, | ||
1392 | { 0x1f, 0x0002 }, | 1486 | { 0x1f, 0x0002 }, |
1393 | { 0x0c, 0x7eb8 }, | 1487 | { 0x0c, 0x7eb8 }, |
1488 | { 0x06, 0x5461 }, | ||
1489 | { 0x1f, 0x0003 }, | ||
1490 | { 0x16, 0x0f0a }, | ||
1394 | { 0x1f, 0x0000 } | 1491 | { 0x1f, 0x0000 } |
1395 | }; | 1492 | }; |
1396 | 1493 | ||
1397 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | 1494 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1495 | |||
1496 | mdio_patch(ioaddr, 0x16, 1 << 0); | ||
1497 | mdio_patch(ioaddr, 0x14, 1 << 5); | ||
1498 | mdio_patch(ioaddr, 0x0d, 1 << 5); | ||
1499 | mdio_write(ioaddr, 0x1f, 0x0000); | ||
1500 | } | ||
1501 | |||
1502 | static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr) | ||
1503 | { | ||
1504 | rtl8168c_3_hw_phy_config(ioaddr); | ||
1505 | } | ||
1506 | |||
1507 | static void rtl8168d_hw_phy_config(void __iomem *ioaddr) | ||
1508 | { | ||
1509 | struct phy_reg phy_reg_init_0[] = { | ||
1510 | { 0x1f, 0x0001 }, | ||
1511 | { 0x09, 0x2770 }, | ||
1512 | { 0x08, 0x04d0 }, | ||
1513 | { 0x0b, 0xad15 }, | ||
1514 | { 0x0c, 0x5bf0 }, | ||
1515 | { 0x1c, 0xf101 }, | ||
1516 | { 0x1f, 0x0003 }, | ||
1517 | { 0x14, 0x94d7 }, | ||
1518 | { 0x12, 0xf4d6 }, | ||
1519 | { 0x09, 0xca0f }, | ||
1520 | { 0x1f, 0x0002 }, | ||
1521 | { 0x0b, 0x0b10 }, | ||
1522 | { 0x0c, 0xd1f7 }, | ||
1523 | { 0x1f, 0x0002 }, | ||
1524 | { 0x06, 0x5461 }, | ||
1525 | { 0x1f, 0x0002 }, | ||
1526 | { 0x05, 0x6662 }, | ||
1527 | { 0x1f, 0x0000 }, | ||
1528 | { 0x14, 0x0060 }, | ||
1529 | { 0x1f, 0x0000 }, | ||
1530 | { 0x0d, 0xf8a0 }, | ||
1531 | { 0x1f, 0x0005 }, | ||
1532 | { 0x05, 0xffc2 } | ||
1533 | }; | ||
1534 | |||
1535 | rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); | ||
1536 | |||
1537 | if (mdio_read(ioaddr, 0x06) == 0xc400) { | ||
1538 | struct phy_reg phy_reg_init_1[] = { | ||
1539 | { 0x1f, 0x0005 }, | ||
1540 | { 0x01, 0x0300 }, | ||
1541 | { 0x1f, 0x0000 }, | ||
1542 | { 0x11, 0x401c }, | ||
1543 | { 0x16, 0x4100 }, | ||
1544 | { 0x1f, 0x0005 }, | ||
1545 | { 0x07, 0x0010 }, | ||
1546 | { 0x05, 0x83dc }, | ||
1547 | { 0x06, 0x087d }, | ||
1548 | { 0x05, 0x8300 }, | ||
1549 | { 0x06, 0x0101 }, | ||
1550 | { 0x06, 0x05f8 }, | ||
1551 | { 0x06, 0xf9fa }, | ||
1552 | { 0x06, 0xfbef }, | ||
1553 | { 0x06, 0x79e2 }, | ||
1554 | { 0x06, 0x835f }, | ||
1555 | { 0x06, 0xe0f8 }, | ||
1556 | { 0x06, 0x9ae1 }, | ||
1557 | { 0x06, 0xf89b }, | ||
1558 | { 0x06, 0xef31 }, | ||
1559 | { 0x06, 0x3b65 }, | ||
1560 | { 0x06, 0xaa07 }, | ||
1561 | { 0x06, 0x81e4 }, | ||
1562 | { 0x06, 0xf89a }, | ||
1563 | { 0x06, 0xe5f8 }, | ||
1564 | { 0x06, 0x9baf }, | ||
1565 | { 0x06, 0x06ae }, | ||
1566 | { 0x05, 0x83dc }, | ||
1567 | { 0x06, 0x8300 }, | ||
1568 | }; | ||
1569 | |||
1570 | rtl_phy_write(ioaddr, phy_reg_init_1, | ||
1571 | ARRAY_SIZE(phy_reg_init_1)); | ||
1572 | } | ||
1573 | |||
1574 | mdio_write(ioaddr, 0x1f, 0x0000); | ||
1398 | } | 1575 | } |
1399 | 1576 | ||
1400 | static void rtl8102e_hw_phy_config(void __iomem *ioaddr) | 1577 | static void rtl8102e_hw_phy_config(void __iomem *ioaddr) |
@@ -1435,15 +1612,38 @@ static void rtl_hw_phy_config(struct net_device *dev) | |||
1435 | case RTL_GIGA_MAC_VER_09: | 1612 | case RTL_GIGA_MAC_VER_09: |
1436 | rtl8102e_hw_phy_config(ioaddr); | 1613 | rtl8102e_hw_phy_config(ioaddr); |
1437 | break; | 1614 | break; |
1615 | case RTL_GIGA_MAC_VER_11: | ||
1616 | rtl8168bb_hw_phy_config(ioaddr); | ||
1617 | break; | ||
1618 | case RTL_GIGA_MAC_VER_12: | ||
1619 | rtl8168bef_hw_phy_config(ioaddr); | ||
1620 | break; | ||
1621 | case RTL_GIGA_MAC_VER_17: | ||
1622 | rtl8168bef_hw_phy_config(ioaddr); | ||
1623 | break; | ||
1438 | case RTL_GIGA_MAC_VER_18: | 1624 | case RTL_GIGA_MAC_VER_18: |
1439 | rtl8168cp_hw_phy_config(ioaddr); | 1625 | rtl8168cp_1_hw_phy_config(ioaddr); |
1440 | break; | 1626 | break; |
1441 | case RTL_GIGA_MAC_VER_19: | 1627 | case RTL_GIGA_MAC_VER_19: |
1442 | rtl8168c_hw_phy_config(ioaddr); | 1628 | rtl8168c_1_hw_phy_config(ioaddr); |
1443 | break; | 1629 | break; |
1444 | case RTL_GIGA_MAC_VER_20: | 1630 | case RTL_GIGA_MAC_VER_20: |
1445 | rtl8168cx_hw_phy_config(ioaddr); | 1631 | rtl8168c_2_hw_phy_config(ioaddr); |
1632 | break; | ||
1633 | case RTL_GIGA_MAC_VER_21: | ||
1634 | rtl8168c_3_hw_phy_config(ioaddr); | ||
1635 | break; | ||
1636 | case RTL_GIGA_MAC_VER_22: | ||
1637 | rtl8168c_4_hw_phy_config(ioaddr); | ||
1638 | break; | ||
1639 | case RTL_GIGA_MAC_VER_23: | ||
1640 | case RTL_GIGA_MAC_VER_24: | ||
1641 | rtl8168cp_2_hw_phy_config(ioaddr); | ||
1642 | break; | ||
1643 | case RTL_GIGA_MAC_VER_25: | ||
1644 | rtl8168d_hw_phy_config(ioaddr); | ||
1446 | break; | 1645 | break; |
1646 | |||
1447 | default: | 1647 | default: |
1448 | break; | 1648 | break; |
1449 | } | 1649 | } |
@@ -2328,6 +2528,164 @@ static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len) | |||
2328 | } | 2528 | } |
2329 | } | 2529 | } |
2330 | 2530 | ||
2531 | static void rtl_disable_clock_request(struct pci_dev *pdev) | ||
2532 | { | ||
2533 | struct net_device *dev = pci_get_drvdata(pdev); | ||
2534 | struct rtl8169_private *tp = netdev_priv(dev); | ||
2535 | int cap = tp->pcie_cap; | ||
2536 | |||
2537 | if (cap) { | ||
2538 | u16 ctl; | ||
2539 | |||
2540 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | ||
2541 | ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | ||
2542 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | ||
2543 | } | ||
2544 | } | ||
2545 | |||
2546 | #define R8168_CPCMD_QUIRK_MASK (\ | ||
2547 | EnableBist | \ | ||
2548 | Mac_dbgo_oe | \ | ||
2549 | Force_half_dup | \ | ||
2550 | Force_rxflow_en | \ | ||
2551 | Force_txflow_en | \ | ||
2552 | Cxpl_dbg_sel | \ | ||
2553 | ASF | \ | ||
2554 | PktCntrDisable | \ | ||
2555 | Mac_dbgo_sel) | ||
2556 | |||
2557 | static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2558 | { | ||
2559 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | ||
2560 | |||
2561 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | ||
2562 | |||
2563 | rtl_tx_performance_tweak(pdev, | ||
2564 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | ||
2565 | } | ||
2566 | |||
2567 | static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2568 | { | ||
2569 | rtl_hw_start_8168bb(ioaddr, pdev); | ||
2570 | |||
2571 | RTL_W8(EarlyTxThres, EarlyTxThld); | ||
2572 | |||
2573 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | ||
2574 | } | ||
2575 | |||
2576 | static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2577 | { | ||
2578 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); | ||
2579 | |||
2580 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | ||
2581 | |||
2582 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | ||
2583 | |||
2584 | rtl_disable_clock_request(pdev); | ||
2585 | |||
2586 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | ||
2587 | } | ||
2588 | |||
2589 | static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2590 | { | ||
2591 | static struct ephy_info e_info_8168cp[] = { | ||
2592 | { 0x01, 0, 0x0001 }, | ||
2593 | { 0x02, 0x0800, 0x1000 }, | ||
2594 | { 0x03, 0, 0x0042 }, | ||
2595 | { 0x06, 0x0080, 0x0000 }, | ||
2596 | { 0x07, 0, 0x2000 } | ||
2597 | }; | ||
2598 | |||
2599 | rtl_csi_access_enable(ioaddr); | ||
2600 | |||
2601 | rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); | ||
2602 | |||
2603 | __rtl_hw_start_8168cp(ioaddr, pdev); | ||
2604 | } | ||
2605 | |||
2606 | static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2607 | { | ||
2608 | rtl_csi_access_enable(ioaddr); | ||
2609 | |||
2610 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | ||
2611 | |||
2612 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | ||
2613 | |||
2614 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | ||
2615 | } | ||
2616 | |||
2617 | static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2618 | { | ||
2619 | rtl_csi_access_enable(ioaddr); | ||
2620 | |||
2621 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | ||
2622 | |||
2623 | /* Magic. */ | ||
2624 | RTL_W8(DBG_REG, 0x20); | ||
2625 | |||
2626 | RTL_W8(EarlyTxThres, EarlyTxThld); | ||
2627 | |||
2628 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | ||
2629 | |||
2630 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | ||
2631 | } | ||
2632 | |||
2633 | static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2634 | { | ||
2635 | static struct ephy_info e_info_8168c_1[] = { | ||
2636 | { 0x02, 0x0800, 0x1000 }, | ||
2637 | { 0x03, 0, 0x0002 }, | ||
2638 | { 0x06, 0x0080, 0x0000 } | ||
2639 | }; | ||
2640 | |||
2641 | rtl_csi_access_enable(ioaddr); | ||
2642 | |||
2643 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | ||
2644 | |||
2645 | rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); | ||
2646 | |||
2647 | __rtl_hw_start_8168cp(ioaddr, pdev); | ||
2648 | } | ||
2649 | |||
2650 | static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2651 | { | ||
2652 | static struct ephy_info e_info_8168c_2[] = { | ||
2653 | { 0x01, 0, 0x0001 }, | ||
2654 | { 0x03, 0x0400, 0x0220 } | ||
2655 | }; | ||
2656 | |||
2657 | rtl_csi_access_enable(ioaddr); | ||
2658 | |||
2659 | rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); | ||
2660 | |||
2661 | __rtl_hw_start_8168cp(ioaddr, pdev); | ||
2662 | } | ||
2663 | |||
2664 | static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2665 | { | ||
2666 | rtl_hw_start_8168c_2(ioaddr, pdev); | ||
2667 | } | ||
2668 | |||
2669 | static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2670 | { | ||
2671 | rtl_csi_access_enable(ioaddr); | ||
2672 | |||
2673 | __rtl_hw_start_8168cp(ioaddr, pdev); | ||
2674 | } | ||
2675 | |||
2676 | static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2677 | { | ||
2678 | rtl_csi_access_enable(ioaddr); | ||
2679 | |||
2680 | rtl_disable_clock_request(pdev); | ||
2681 | |||
2682 | RTL_W8(EarlyTxThres, EarlyTxThld); | ||
2683 | |||
2684 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | ||
2685 | |||
2686 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | ||
2687 | } | ||
2688 | |||
2331 | static void rtl_hw_start_8168(struct net_device *dev) | 2689 | static void rtl_hw_start_8168(struct net_device *dev) |
2332 | { | 2690 | { |
2333 | struct rtl8169_private *tp = netdev_priv(dev); | 2691 | struct rtl8169_private *tp = netdev_priv(dev); |
@@ -2340,14 +2698,10 @@ static void rtl_hw_start_8168(struct net_device *dev) | |||
2340 | 2698 | ||
2341 | rtl_set_rx_max_size(ioaddr); | 2699 | rtl_set_rx_max_size(ioaddr); |
2342 | 2700 | ||
2343 | rtl_set_rx_tx_config_registers(tp); | ||
2344 | |||
2345 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; | 2701 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2346 | 2702 | ||
2347 | RTL_W16(CPlusCmd, tp->cp_cmd); | 2703 | RTL_W16(CPlusCmd, tp->cp_cmd); |
2348 | 2704 | ||
2349 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | ||
2350 | |||
2351 | RTL_W16(IntrMitigate, 0x5151); | 2705 | RTL_W16(IntrMitigate, 0x5151); |
2352 | 2706 | ||
2353 | /* Work around for RxFIFO overflow. */ | 2707 | /* Work around for RxFIFO overflow. */ |
@@ -2358,14 +2712,65 @@ static void rtl_hw_start_8168(struct net_device *dev) | |||
2358 | 2712 | ||
2359 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | 2713 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
2360 | 2714 | ||
2361 | RTL_W8(Cfg9346, Cfg9346_Lock); | 2715 | rtl_set_rx_mode(dev); |
2716 | |||
2717 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | ||
2718 | (InterFrameGap << TxInterFrameGapShift)); | ||
2362 | 2719 | ||
2363 | RTL_R8(IntrMask); | 2720 | RTL_R8(IntrMask); |
2364 | 2721 | ||
2365 | rtl_set_rx_mode(dev); | 2722 | switch (tp->mac_version) { |
2723 | case RTL_GIGA_MAC_VER_11: | ||
2724 | rtl_hw_start_8168bb(ioaddr, pdev); | ||
2725 | break; | ||
2726 | |||
2727 | case RTL_GIGA_MAC_VER_12: | ||
2728 | case RTL_GIGA_MAC_VER_17: | ||
2729 | rtl_hw_start_8168bef(ioaddr, pdev); | ||
2730 | break; | ||
2731 | |||
2732 | case RTL_GIGA_MAC_VER_18: | ||
2733 | rtl_hw_start_8168cp_1(ioaddr, pdev); | ||
2734 | break; | ||
2735 | |||
2736 | case RTL_GIGA_MAC_VER_19: | ||
2737 | rtl_hw_start_8168c_1(ioaddr, pdev); | ||
2738 | break; | ||
2739 | |||
2740 | case RTL_GIGA_MAC_VER_20: | ||
2741 | rtl_hw_start_8168c_2(ioaddr, pdev); | ||
2742 | break; | ||
2743 | |||
2744 | case RTL_GIGA_MAC_VER_21: | ||
2745 | rtl_hw_start_8168c_3(ioaddr, pdev); | ||
2746 | break; | ||
2747 | |||
2748 | case RTL_GIGA_MAC_VER_22: | ||
2749 | rtl_hw_start_8168c_4(ioaddr, pdev); | ||
2750 | break; | ||
2751 | |||
2752 | case RTL_GIGA_MAC_VER_23: | ||
2753 | rtl_hw_start_8168cp_2(ioaddr, pdev); | ||
2754 | break; | ||
2755 | |||
2756 | case RTL_GIGA_MAC_VER_24: | ||
2757 | rtl_hw_start_8168cp_3(ioaddr, pdev); | ||
2758 | break; | ||
2759 | |||
2760 | case RTL_GIGA_MAC_VER_25: | ||
2761 | rtl_hw_start_8168d(ioaddr, pdev); | ||
2762 | break; | ||
2763 | |||
2764 | default: | ||
2765 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | ||
2766 | dev->name, tp->mac_version); | ||
2767 | break; | ||
2768 | } | ||
2366 | 2769 | ||
2367 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | 2770 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
2368 | 2771 | ||
2772 | RTL_W8(Cfg9346, Cfg9346_Lock); | ||
2773 | |||
2369 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | 2774 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
2370 | 2775 | ||
2371 | RTL_W16(IntrMask, tp->intr_event); | 2776 | RTL_W16(IntrMask, tp->intr_event); |
@@ -3469,6 +3874,11 @@ out: | |||
3469 | return 0; | 3874 | return 0; |
3470 | } | 3875 | } |
3471 | 3876 | ||
3877 | static void rtl_shutdown(struct pci_dev *pdev) | ||
3878 | { | ||
3879 | rtl8169_suspend(pdev, PMSG_SUSPEND); | ||
3880 | } | ||
3881 | |||
3472 | #endif /* CONFIG_PM */ | 3882 | #endif /* CONFIG_PM */ |
3473 | 3883 | ||
3474 | static struct pci_driver rtl8169_pci_driver = { | 3884 | static struct pci_driver rtl8169_pci_driver = { |
@@ -3479,6 +3889,7 @@ static struct pci_driver rtl8169_pci_driver = { | |||
3479 | #ifdef CONFIG_PM | 3889 | #ifdef CONFIG_PM |
3480 | .suspend = rtl8169_suspend, | 3890 | .suspend = rtl8169_suspend, |
3481 | .resume = rtl8169_resume, | 3891 | .resume = rtl8169_resume, |
3892 | .shutdown = rtl_shutdown, | ||
3482 | #endif | 3893 | #endif |
3483 | }; | 3894 | }; |
3484 | 3895 | ||