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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/yellowfin.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/yellowfin.c')
-rw-r--r--drivers/net/yellowfin.c1499
1 files changed, 1499 insertions, 0 deletions
diff --git a/drivers/net/yellowfin.c b/drivers/net/yellowfin.c
new file mode 100644
index 000000000000..9da925430109
--- /dev/null
+++ b/drivers/net/yellowfin.c
@@ -0,0 +1,1499 @@
1/* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
2/*
3 Written 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
22
23
24 Linux kernel changelog:
25 -----------------------
26
27 LK1.1.1 (jgarzik): Port to 2.4 kernel
28
29 LK1.1.2 (jgarzik):
30 * Merge in becker version 1.05
31
32 LK1.1.3 (jgarzik):
33 * Various cleanups
34 * Update yellowfin_timer to correctly calculate duplex.
35 (suggested by Manfred Spraul)
36
37 LK1.1.4 (val@nmt.edu):
38 * Fix three endian-ness bugs
39 * Support dual function SYM53C885E ethernet chip
40
41 LK1.1.5 (val@nmt.edu):
42 * Fix forced full-duplex bug I introduced
43
44 LK1.1.6 (val@nmt.edu):
45 * Only print warning on truly "oversized" packets
46 * Fix theoretical bug on gigabit cards - return to 1.1.3 behavior
47
48*/
49
50#define DRV_NAME "yellowfin"
51#define DRV_VERSION "1.05+LK1.1.6"
52#define DRV_RELDATE "Feb 11, 2002"
53
54#define PFX DRV_NAME ": "
55
56/* The user-configurable values.
57 These may be modified when a driver module is loaded.*/
58
59static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
60/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
61static int max_interrupt_work = 20;
62static int mtu;
63#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
64/* System-wide count of bogus-rx frames. */
65static int bogus_rx;
66static int dma_ctrl = 0x004A0263; /* Constrained by errata */
67static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
68#elif defined(YF_NEW) /* A future perfect board :->. */
69static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
70static int fifo_cfg = 0x0028;
71#else
72static int dma_ctrl = 0x004A0263; /* Constrained by errata */
73static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
74#endif
75
76/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
77 Setting to > 1514 effectively disables this feature. */
78static int rx_copybreak;
79
80/* Used to pass the media type, etc.
81 No media types are currently defined. These exist for driver
82 interoperability.
83*/
84#define MAX_UNITS 8 /* More are supported, limit only on options */
85static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
86static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
87
88/* Do ugly workaround for GX server chipset errata. */
89static int gx_fix;
90
91/* Operational parameters that are set at compile time. */
92
93/* Keep the ring sizes a power of two for efficiency.
94 Making the Tx ring too long decreases the effectiveness of channel
95 bonding and packet priority.
96 There are no ill effects from too-large receive rings. */
97#define TX_RING_SIZE 16
98#define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
99#define RX_RING_SIZE 64
100#define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
101#define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
102#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
103
104/* Operational parameters that usually are not changed. */
105/* Time in jiffies before concluding the transmitter is hung. */
106#define TX_TIMEOUT (2*HZ)
107#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
108
109#define yellowfin_debug debug
110
111#include <linux/module.h>
112#include <linux/kernel.h>
113#include <linux/string.h>
114#include <linux/timer.h>
115#include <linux/errno.h>
116#include <linux/ioport.h>
117#include <linux/slab.h>
118#include <linux/interrupt.h>
119#include <linux/pci.h>
120#include <linux/init.h>
121#include <linux/mii.h>
122#include <linux/netdevice.h>
123#include <linux/etherdevice.h>
124#include <linux/skbuff.h>
125#include <linux/ethtool.h>
126#include <linux/crc32.h>
127#include <linux/bitops.h>
128#include <asm/uaccess.h>
129#include <asm/processor.h> /* Processor type for cache alignment. */
130#include <asm/unaligned.h>
131#include <asm/io.h>
132
133/* These identify the driver base version and may not be removed. */
134static char version[] __devinitdata =
135KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
136KERN_INFO " http://www.scyld.com/network/yellowfin.html\n"
137KERN_INFO " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
138
139MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
140MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
141MODULE_LICENSE("GPL");
142
143module_param(max_interrupt_work, int, 0);
144module_param(mtu, int, 0);
145module_param(debug, int, 0);
146module_param(rx_copybreak, int, 0);
147module_param_array(options, int, NULL, 0);
148module_param_array(full_duplex, int, NULL, 0);
149module_param(gx_fix, int, 0);
150MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
151MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
152MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
153MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
154MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
155MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
156MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
157
158/*
159 Theory of Operation
160
161I. Board Compatibility
162
163This device driver is designed for the Packet Engines "Yellowfin" Gigabit
164Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
165Symbios 53C885E dual function chip.
166
167II. Board-specific settings
168
169PCI bus devices are configured by the system at boot time, so no jumpers
170need to be set on the board. The system BIOS preferably should assign the
171PCI INTA signal to an otherwise unused system IRQ line.
172Note: Kernel versions earlier than 1.3.73 do not support shared PCI
173interrupt lines.
174
175III. Driver operation
176
177IIIa. Ring buffers
178
179The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
180This is a descriptor list scheme similar to that used by the EEPro100 and
181Tulip. This driver uses two statically allocated fixed-size descriptor lists
182formed into rings by a branch from the final descriptor to the beginning of
183the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
184
185The driver allocates full frame size skbuffs for the Rx ring buffers at
186open() time and passes the skb->data field to the Yellowfin as receive data
187buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
188a fresh skbuff is allocated and the frame is copied to the new skbuff.
189When the incoming frame is larger, the skbuff is passed directly up the
190protocol stack and replaced by a newly allocated skbuff.
191
192The RX_COPYBREAK value is chosen to trade-off the memory wasted by
193using a full-sized skbuff for small frames vs. the copying costs of larger
194frames. For small frames the copying cost is negligible (esp. considering
195that we are pre-loading the cache with immediately useful header
196information). For large frames the copying cost is non-trivial, and the
197larger copy might flush the cache of useful data.
198
199IIIC. Synchronization
200
201The driver runs as two independent, single-threaded flows of control. One
202is the send-packet routine, which enforces single-threaded use by the
203dev->tbusy flag. The other thread is the interrupt handler, which is single
204threaded by the hardware and other software.
205
206The send packet thread has partial control over the Tx ring and 'dev->tbusy'
207flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
208queue slot is empty, it clears the tbusy flag when finished otherwise it sets
209the 'yp->tx_full' flag.
210
211The interrupt handler has exclusive control over the Rx ring and records stats
212from the Tx ring. After reaping the stats, it marks the Tx queue entry as
213empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
214clears both the tx_full and tbusy flags.
215
216IV. Notes
217
218Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
219Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
220and an AlphaStation to verifty the Alpha port!
221
222IVb. References
223
224Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
225Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
226 Data Manual v3.0
227http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
228http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
229
230IVc. Errata
231
232See Packet Engines confidential appendix (prototype chips only).
233*/
234
235
236
237enum pci_id_flags_bits {
238 /* Set PCI command register bits before calling probe1(). */
239 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
240 /* Read and map the single following PCI BAR. */
241 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
242 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
243 PCI_UNUSED_IRQ=0x800,
244};
245enum capability_flags {
246 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
247 HasMACAddrBug=32, /* Only on early revs. */
248 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
249};
250/* The PCI I/O space extent. */
251#define YELLOWFIN_SIZE 0x100
252#ifdef USE_IO_OPS
253#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0)
254#else
255#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
256#endif
257
258struct pci_id_info {
259 const char *name;
260 struct match_info {
261 int pci, pci_mask, subsystem, subsystem_mask;
262 int revision, revision_mask; /* Only 8 bits. */
263 } id;
264 enum pci_id_flags_bits pci_flags;
265 int io_size; /* Needed for I/O region check or ioremap(). */
266 int drv_flags; /* Driver use, intended as capability flags. */
267};
268
269static struct pci_id_info pci_id_tbl[] = {
270 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
271 PCI_IOTYPE, YELLOWFIN_SIZE,
272 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
273 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
274 PCI_IOTYPE, YELLOWFIN_SIZE, HasMII | DontUseEeprom },
275 {NULL,},
276};
277
278static struct pci_device_id yellowfin_pci_tbl[] = {
279 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
280 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
281 { 0, }
282};
283MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
284
285
286/* Offsets to the Yellowfin registers. Various sizes and alignments. */
287enum yellowfin_offsets {
288 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
289 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
290 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
291 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
292 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
293 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
294 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
295 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
296 MII_Status=0xAE,
297 RxDepth=0xB8, FlowCtrl=0xBC,
298 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
299 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
300 EEFeature=0xF5,
301};
302
303/* The Yellowfin Rx and Tx buffer descriptors.
304 Elements are written as 32 bit for endian portability. */
305struct yellowfin_desc {
306 u32 dbdma_cmd;
307 u32 addr;
308 u32 branch_addr;
309 u32 result_status;
310};
311
312struct tx_status_words {
313#ifdef __BIG_ENDIAN
314 u16 tx_errs;
315 u16 tx_cnt;
316 u16 paused;
317 u16 total_tx_cnt;
318#else /* Little endian chips. */
319 u16 tx_cnt;
320 u16 tx_errs;
321 u16 total_tx_cnt;
322 u16 paused;
323#endif /* __BIG_ENDIAN */
324};
325
326/* Bits in yellowfin_desc.cmd */
327enum desc_cmd_bits {
328 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
329 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
330 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
331 BRANCH_IFTRUE=0x040000,
332};
333
334/* Bits in yellowfin_desc.status */
335enum desc_status_bits { RX_EOP=0x0040, };
336
337/* Bits in the interrupt status/mask registers. */
338enum intr_status_bits {
339 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
340 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
341 IntrEarlyRx=0x100, IntrWakeup=0x200, };
342
343#define PRIV_ALIGN 31 /* Required alignment mask */
344#define MII_CNT 4
345struct yellowfin_private {
346 /* Descriptor rings first for alignment.
347 Tx requires a second descriptor for status. */
348 struct yellowfin_desc *rx_ring;
349 struct yellowfin_desc *tx_ring;
350 struct sk_buff* rx_skbuff[RX_RING_SIZE];
351 struct sk_buff* tx_skbuff[TX_RING_SIZE];
352 dma_addr_t rx_ring_dma;
353 dma_addr_t tx_ring_dma;
354
355 struct tx_status_words *tx_status;
356 dma_addr_t tx_status_dma;
357
358 struct timer_list timer; /* Media selection timer. */
359 struct net_device_stats stats;
360 /* Frequently used and paired value: keep adjacent for cache effect. */
361 int chip_id, drv_flags;
362 struct pci_dev *pci_dev;
363 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
364 unsigned int rx_buf_sz; /* Based on MTU+slack. */
365 struct tx_status_words *tx_tail_desc;
366 unsigned int cur_tx, dirty_tx;
367 int tx_threshold;
368 unsigned int tx_full:1; /* The Tx queue is full. */
369 unsigned int full_duplex:1; /* Full-duplex operation requested. */
370 unsigned int duplex_lock:1;
371 unsigned int medialock:1; /* Do not sense media. */
372 unsigned int default_port:4; /* Last dev->if_port value. */
373 /* MII transceiver section. */
374 int mii_cnt; /* MII device addresses. */
375 u16 advertising; /* NWay media advertisement */
376 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
377 spinlock_t lock;
378 void __iomem *base;
379};
380
381static int read_eeprom(void __iomem *ioaddr, int location);
382static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
383static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
384static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
385static int yellowfin_open(struct net_device *dev);
386static void yellowfin_timer(unsigned long data);
387static void yellowfin_tx_timeout(struct net_device *dev);
388static void yellowfin_init_ring(struct net_device *dev);
389static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev);
390static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
391static int yellowfin_rx(struct net_device *dev);
392static void yellowfin_error(struct net_device *dev, int intr_status);
393static int yellowfin_close(struct net_device *dev);
394static struct net_device_stats *yellowfin_get_stats(struct net_device *dev);
395static void set_rx_mode(struct net_device *dev);
396static struct ethtool_ops ethtool_ops;
397
398
399static int __devinit yellowfin_init_one(struct pci_dev *pdev,
400 const struct pci_device_id *ent)
401{
402 struct net_device *dev;
403 struct yellowfin_private *np;
404 int irq;
405 int chip_idx = ent->driver_data;
406 static int find_cnt;
407 void __iomem *ioaddr;
408 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
409 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
410 void *ring_space;
411 dma_addr_t ring_dma;
412#ifdef USE_IO_OPS
413 int bar = 0;
414#else
415 int bar = 1;
416#endif
417
418/* when built into the kernel, we only print version if device is found */
419#ifndef MODULE
420 static int printed_version;
421 if (!printed_version++)
422 printk(version);
423#endif
424
425 i = pci_enable_device(pdev);
426 if (i) return i;
427
428 dev = alloc_etherdev(sizeof(*np));
429 if (!dev) {
430 printk (KERN_ERR PFX "cannot allocate ethernet device\n");
431 return -ENOMEM;
432 }
433 SET_MODULE_OWNER(dev);
434 SET_NETDEV_DEV(dev, &pdev->dev);
435
436 np = netdev_priv(dev);
437
438 if (pci_request_regions(pdev, DRV_NAME))
439 goto err_out_free_netdev;
440
441 pci_set_master (pdev);
442
443 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
444 if (!ioaddr)
445 goto err_out_free_res;
446
447 irq = pdev->irq;
448
449 if (drv_flags & DontUseEeprom)
450 for (i = 0; i < 6; i++)
451 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
452 else {
453 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
454 for (i = 0; i < 6; i++)
455 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
456 }
457
458 /* Reset the chip. */
459 iowrite32(0x80000000, ioaddr + DMACtrl);
460
461 dev->base_addr = (unsigned long)ioaddr;
462 dev->irq = irq;
463
464 pci_set_drvdata(pdev, dev);
465 spin_lock_init(&np->lock);
466
467 np->pci_dev = pdev;
468 np->chip_id = chip_idx;
469 np->drv_flags = drv_flags;
470 np->base = ioaddr;
471
472 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
473 if (!ring_space)
474 goto err_out_cleardev;
475 np->tx_ring = (struct yellowfin_desc *)ring_space;
476 np->tx_ring_dma = ring_dma;
477
478 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
479 if (!ring_space)
480 goto err_out_unmap_tx;
481 np->rx_ring = (struct yellowfin_desc *)ring_space;
482 np->rx_ring_dma = ring_dma;
483
484 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
485 if (!ring_space)
486 goto err_out_unmap_rx;
487 np->tx_status = (struct tx_status_words *)ring_space;
488 np->tx_status_dma = ring_dma;
489
490 if (dev->mem_start)
491 option = dev->mem_start;
492
493 /* The lower four bits are the media type. */
494 if (option > 0) {
495 if (option & 0x200)
496 np->full_duplex = 1;
497 np->default_port = option & 15;
498 if (np->default_port)
499 np->medialock = 1;
500 }
501 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
502 np->full_duplex = 1;
503
504 if (np->full_duplex)
505 np->duplex_lock = 1;
506
507 /* The Yellowfin-specific entries in the device structure. */
508 dev->open = &yellowfin_open;
509 dev->hard_start_xmit = &yellowfin_start_xmit;
510 dev->stop = &yellowfin_close;
511 dev->get_stats = &yellowfin_get_stats;
512 dev->set_multicast_list = &set_rx_mode;
513 dev->do_ioctl = &netdev_ioctl;
514 SET_ETHTOOL_OPS(dev, &ethtool_ops);
515 dev->tx_timeout = yellowfin_tx_timeout;
516 dev->watchdog_timeo = TX_TIMEOUT;
517
518 if (mtu)
519 dev->mtu = mtu;
520
521 i = register_netdev(dev);
522 if (i)
523 goto err_out_unmap_status;
524
525 printk(KERN_INFO "%s: %s type %8x at %p, ",
526 dev->name, pci_id_tbl[chip_idx].name,
527 ioread32(ioaddr + ChipRev), ioaddr);
528 for (i = 0; i < 5; i++)
529 printk("%2.2x:", dev->dev_addr[i]);
530 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
531
532 if (np->drv_flags & HasMII) {
533 int phy, phy_idx = 0;
534 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
535 int mii_status = mdio_read(ioaddr, phy, 1);
536 if (mii_status != 0xffff && mii_status != 0x0000) {
537 np->phys[phy_idx++] = phy;
538 np->advertising = mdio_read(ioaddr, phy, 4);
539 printk(KERN_INFO "%s: MII PHY found at address %d, status "
540 "0x%4.4x advertising %4.4x.\n",
541 dev->name, phy, mii_status, np->advertising);
542 }
543 }
544 np->mii_cnt = phy_idx;
545 }
546
547 find_cnt++;
548
549 return 0;
550
551err_out_unmap_status:
552 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
553 np->tx_status_dma);
554err_out_unmap_rx:
555 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
556err_out_unmap_tx:
557 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
558err_out_cleardev:
559 pci_set_drvdata(pdev, NULL);
560 pci_iounmap(pdev, ioaddr);
561err_out_free_res:
562 pci_release_regions(pdev);
563err_out_free_netdev:
564 free_netdev (dev);
565 return -ENODEV;
566}
567
568static int __devinit read_eeprom(void __iomem *ioaddr, int location)
569{
570 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
571
572 iowrite8(location, ioaddr + EEAddr);
573 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
574 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
575 ;
576 return ioread8(ioaddr + EERead);
577}
578
579/* MII Managemen Data I/O accesses.
580 These routines assume the MDIO controller is idle, and do not exit until
581 the command is finished. */
582
583static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
584{
585 int i;
586
587 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
588 iowrite16(1, ioaddr + MII_Cmd);
589 for (i = 10000; i >= 0; i--)
590 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
591 break;
592 return ioread16(ioaddr + MII_Rd_Data);
593}
594
595static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
596{
597 int i;
598
599 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
600 iowrite16(value, ioaddr + MII_Wr_Data);
601
602 /* Wait for the command to finish. */
603 for (i = 10000; i >= 0; i--)
604 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
605 break;
606 return;
607}
608
609
610static int yellowfin_open(struct net_device *dev)
611{
612 struct yellowfin_private *yp = netdev_priv(dev);
613 void __iomem *ioaddr = yp->base;
614 int i;
615
616 /* Reset the chip. */
617 iowrite32(0x80000000, ioaddr + DMACtrl);
618
619 i = request_irq(dev->irq, &yellowfin_interrupt, SA_SHIRQ, dev->name, dev);
620 if (i) return i;
621
622 if (yellowfin_debug > 1)
623 printk(KERN_DEBUG "%s: yellowfin_open() irq %d.\n",
624 dev->name, dev->irq);
625
626 yellowfin_init_ring(dev);
627
628 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
629 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
630
631 for (i = 0; i < 6; i++)
632 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
633
634 /* Set up various condition 'select' registers.
635 There are no options here. */
636 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
637 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
638 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
639 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
640 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
641 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
642
643 /* Initialize other registers: with so many this eventually this will
644 converted to an offset/value list. */
645 iowrite32(dma_ctrl, ioaddr + DMACtrl);
646 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
647 /* Enable automatic generation of flow control frames, period 0xffff. */
648 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
649
650 yp->tx_threshold = 32;
651 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
652
653 if (dev->if_port == 0)
654 dev->if_port = yp->default_port;
655
656 netif_start_queue(dev);
657
658 /* Setting the Rx mode will start the Rx process. */
659 if (yp->drv_flags & IsGigabit) {
660 /* We are always in full-duplex mode with gigabit! */
661 yp->full_duplex = 1;
662 iowrite16(0x01CF, ioaddr + Cnfg);
663 } else {
664 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
665 iowrite16(0x1018, ioaddr + FrameGap1);
666 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
667 }
668 set_rx_mode(dev);
669
670 /* Enable interrupts by setting the interrupt mask. */
671 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
672 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
673 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
674 iowrite32(0x80008000, ioaddr + TxCtrl);
675
676 if (yellowfin_debug > 2) {
677 printk(KERN_DEBUG "%s: Done yellowfin_open().\n",
678 dev->name);
679 }
680
681 /* Set the timer to check for link beat. */
682 init_timer(&yp->timer);
683 yp->timer.expires = jiffies + 3*HZ;
684 yp->timer.data = (unsigned long)dev;
685 yp->timer.function = &yellowfin_timer; /* timer handler */
686 add_timer(&yp->timer);
687
688 return 0;
689}
690
691static void yellowfin_timer(unsigned long data)
692{
693 struct net_device *dev = (struct net_device *)data;
694 struct yellowfin_private *yp = netdev_priv(dev);
695 void __iomem *ioaddr = yp->base;
696 int next_tick = 60*HZ;
697
698 if (yellowfin_debug > 3) {
699 printk(KERN_DEBUG "%s: Yellowfin timer tick, status %8.8x.\n",
700 dev->name, ioread16(ioaddr + IntrStatus));
701 }
702
703 if (yp->mii_cnt) {
704 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
705 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
706 int negotiated = lpa & yp->advertising;
707 if (yellowfin_debug > 1)
708 printk(KERN_DEBUG "%s: MII #%d status register is %4.4x, "
709 "link partner capability %4.4x.\n",
710 dev->name, yp->phys[0], bmsr, lpa);
711
712 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
713
714 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
715
716 if (bmsr & BMSR_LSTATUS)
717 next_tick = 60*HZ;
718 else
719 next_tick = 3*HZ;
720 }
721
722 yp->timer.expires = jiffies + next_tick;
723 add_timer(&yp->timer);
724}
725
726static void yellowfin_tx_timeout(struct net_device *dev)
727{
728 struct yellowfin_private *yp = netdev_priv(dev);
729 void __iomem *ioaddr = yp->base;
730
731 printk(KERN_WARNING "%s: Yellowfin transmit timed out at %d/%d Tx "
732 "status %4.4x, Rx status %4.4x, resetting...\n",
733 dev->name, yp->cur_tx, yp->dirty_tx,
734 ioread32(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
735
736 /* Note: these should be KERN_DEBUG. */
737 if (yellowfin_debug) {
738 int i;
739 printk(KERN_WARNING " Rx ring %p: ", yp->rx_ring);
740 for (i = 0; i < RX_RING_SIZE; i++)
741 printk(" %8.8x", yp->rx_ring[i].result_status);
742 printk("\n"KERN_WARNING" Tx ring %p: ", yp->tx_ring);
743 for (i = 0; i < TX_RING_SIZE; i++)
744 printk(" %4.4x /%8.8x", yp->tx_status[i].tx_errs,
745 yp->tx_ring[i].result_status);
746 printk("\n");
747 }
748
749 /* If the hardware is found to hang regularly, we will update the code
750 to reinitialize the chip here. */
751 dev->if_port = 0;
752
753 /* Wake the potentially-idle transmit channel. */
754 iowrite32(0x10001000, yp->base + TxCtrl);
755 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
756 netif_wake_queue (dev); /* Typical path */
757
758 dev->trans_start = jiffies;
759 yp->stats.tx_errors++;
760}
761
762/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
763static void yellowfin_init_ring(struct net_device *dev)
764{
765 struct yellowfin_private *yp = netdev_priv(dev);
766 int i;
767
768 yp->tx_full = 0;
769 yp->cur_rx = yp->cur_tx = 0;
770 yp->dirty_tx = 0;
771
772 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
773
774 for (i = 0; i < RX_RING_SIZE; i++) {
775 yp->rx_ring[i].dbdma_cmd =
776 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
777 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
778 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
779 }
780
781 for (i = 0; i < RX_RING_SIZE; i++) {
782 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
783 yp->rx_skbuff[i] = skb;
784 if (skb == NULL)
785 break;
786 skb->dev = dev; /* Mark as being used by this device. */
787 skb_reserve(skb, 2); /* 16 byte align the IP header. */
788 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
789 skb->tail, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
790 }
791 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
792 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
793
794#define NO_TXSTATS
795#ifdef NO_TXSTATS
796 /* In this mode the Tx ring needs only a single descriptor. */
797 for (i = 0; i < TX_RING_SIZE; i++) {
798 yp->tx_skbuff[i] = NULL;
799 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
800 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
801 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
802 }
803 /* Wrap ring */
804 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
805#else
806{
807 int j;
808
809 /* Tx ring needs a pair of descriptors, the second for the status. */
810 for (i = 0; i < TX_RING_SIZE; i++) {
811 j = 2*i;
812 yp->tx_skbuff[i] = 0;
813 /* Branch on Tx error. */
814 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
815 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
816 (j+1)*sizeof(struct yellowfin_desc);
817 j++;
818 if (yp->flags & FullTxStatus) {
819 yp->tx_ring[j].dbdma_cmd =
820 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
821 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
822 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
823 i*sizeof(struct tx_status_words);
824 } else {
825 /* Symbios chips write only tx_errs word. */
826 yp->tx_ring[j].dbdma_cmd =
827 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
828 yp->tx_ring[j].request_cnt = 2;
829 /* Om pade ummmmm... */
830 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
831 i*sizeof(struct tx_status_words) +
832 &(yp->tx_status[0].tx_errs) -
833 &(yp->tx_status[0]));
834 }
835 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
836 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
837 }
838 /* Wrap ring */
839 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
840}
841#endif
842 yp->tx_tail_desc = &yp->tx_status[0];
843 return;
844}
845
846static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev)
847{
848 struct yellowfin_private *yp = netdev_priv(dev);
849 unsigned entry;
850 int len = skb->len;
851
852 netif_stop_queue (dev);
853
854 /* Note: Ordering is important here, set the field with the
855 "ownership" bit last, and only then increment cur_tx. */
856
857 /* Calculate the next Tx descriptor entry. */
858 entry = yp->cur_tx % TX_RING_SIZE;
859
860 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
861 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
862 /* Fix GX chipset errata. */
863 if (cacheline_end > 24 || cacheline_end == 0) {
864 len = skb->len + 32 - cacheline_end + 1;
865 if (len != skb->len)
866 skb = skb_padto(skb, len);
867 }
868 if (skb == NULL) {
869 yp->tx_skbuff[entry] = NULL;
870 netif_wake_queue(dev);
871 return 0;
872 }
873 }
874 yp->tx_skbuff[entry] = skb;
875
876#ifdef NO_TXSTATS
877 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
878 skb->data, len, PCI_DMA_TODEVICE));
879 yp->tx_ring[entry].result_status = 0;
880 if (entry >= TX_RING_SIZE-1) {
881 /* New stop command. */
882 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
883 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
884 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
885 } else {
886 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
887 yp->tx_ring[entry].dbdma_cmd =
888 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
889 }
890 yp->cur_tx++;
891#else
892 yp->tx_ring[entry<<1].request_cnt = len;
893 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
894 skb->data, len, PCI_DMA_TODEVICE));
895 /* The input_last (status-write) command is constant, but we must
896 rewrite the subsequent 'stop' command. */
897
898 yp->cur_tx++;
899 {
900 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
901 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
902 }
903 /* Final step -- overwrite the old 'stop' command. */
904
905 yp->tx_ring[entry<<1].dbdma_cmd =
906 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
907 CMD_TX_PKT | BRANCH_IFTRUE) | len);
908#endif
909
910 /* Non-x86 Todo: explicitly flush cache lines here. */
911
912 /* Wake the potentially-idle transmit channel. */
913 iowrite32(0x10001000, yp->base + TxCtrl);
914
915 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
916 netif_start_queue (dev); /* Typical path */
917 else
918 yp->tx_full = 1;
919 dev->trans_start = jiffies;
920
921 if (yellowfin_debug > 4) {
922 printk(KERN_DEBUG "%s: Yellowfin transmit frame #%d queued in slot %d.\n",
923 dev->name, yp->cur_tx, entry);
924 }
925 return 0;
926}
927
928/* The interrupt handler does all of the Rx thread work and cleans up
929 after the Tx thread. */
930static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
931{
932 struct net_device *dev = dev_instance;
933 struct yellowfin_private *yp;
934 void __iomem *ioaddr;
935 int boguscnt = max_interrupt_work;
936 unsigned int handled = 0;
937
938#ifndef final_version /* Can never occur. */
939 if (dev == NULL) {
940 printk (KERN_ERR "yellowfin_interrupt(): irq %d for unknown device.\n", irq);
941 return IRQ_NONE;
942 }
943#endif
944
945 yp = netdev_priv(dev);
946 ioaddr = yp->base;
947
948 spin_lock (&yp->lock);
949
950 do {
951 u16 intr_status = ioread16(ioaddr + IntrClear);
952
953 if (yellowfin_debug > 4)
954 printk(KERN_DEBUG "%s: Yellowfin interrupt, status %4.4x.\n",
955 dev->name, intr_status);
956
957 if (intr_status == 0)
958 break;
959 handled = 1;
960
961 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
962 yellowfin_rx(dev);
963 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
964 }
965
966#ifdef NO_TXSTATS
967 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
968 int entry = yp->dirty_tx % TX_RING_SIZE;
969 struct sk_buff *skb;
970
971 if (yp->tx_ring[entry].result_status == 0)
972 break;
973 skb = yp->tx_skbuff[entry];
974 yp->stats.tx_packets++;
975 yp->stats.tx_bytes += skb->len;
976 /* Free the original skb. */
977 pci_unmap_single(yp->pci_dev, yp->tx_ring[entry].addr,
978 skb->len, PCI_DMA_TODEVICE);
979 dev_kfree_skb_irq(skb);
980 yp->tx_skbuff[entry] = NULL;
981 }
982 if (yp->tx_full
983 && yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
984 /* The ring is no longer full, clear tbusy. */
985 yp->tx_full = 0;
986 netif_wake_queue(dev);
987 }
988#else
989 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
990 unsigned dirty_tx = yp->dirty_tx;
991
992 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
993 dirty_tx++) {
994 /* Todo: optimize this. */
995 int entry = dirty_tx % TX_RING_SIZE;
996 u16 tx_errs = yp->tx_status[entry].tx_errs;
997 struct sk_buff *skb;
998
999#ifndef final_version
1000 if (yellowfin_debug > 5)
1001 printk(KERN_DEBUG "%s: Tx queue %d check, Tx status "
1002 "%4.4x %4.4x %4.4x %4.4x.\n",
1003 dev->name, entry,
1004 yp->tx_status[entry].tx_cnt,
1005 yp->tx_status[entry].tx_errs,
1006 yp->tx_status[entry].total_tx_cnt,
1007 yp->tx_status[entry].paused);
1008#endif
1009 if (tx_errs == 0)
1010 break; /* It still hasn't been Txed */
1011 skb = yp->tx_skbuff[entry];
1012 if (tx_errs & 0xF810) {
1013 /* There was an major error, log it. */
1014#ifndef final_version
1015 if (yellowfin_debug > 1)
1016 printk(KERN_DEBUG "%s: Transmit error, Tx status %4.4x.\n",
1017 dev->name, tx_errs);
1018#endif
1019 yp->stats.tx_errors++;
1020 if (tx_errs & 0xF800) yp->stats.tx_aborted_errors++;
1021 if (tx_errs & 0x0800) yp->stats.tx_carrier_errors++;
1022 if (tx_errs & 0x2000) yp->stats.tx_window_errors++;
1023 if (tx_errs & 0x8000) yp->stats.tx_fifo_errors++;
1024 } else {
1025#ifndef final_version
1026 if (yellowfin_debug > 4)
1027 printk(KERN_DEBUG "%s: Normal transmit, Tx status %4.4x.\n",
1028 dev->name, tx_errs);
1029#endif
1030 yp->stats.tx_bytes += skb->len;
1031 yp->stats.collisions += tx_errs & 15;
1032 yp->stats.tx_packets++;
1033 }
1034 /* Free the original skb. */
1035 pci_unmap_single(yp->pci_dev,
1036 yp->tx_ring[entry<<1].addr, skb->len,
1037 PCI_DMA_TODEVICE);
1038 dev_kfree_skb_irq(skb);
1039 yp->tx_skbuff[entry] = 0;
1040 /* Mark status as empty. */
1041 yp->tx_status[entry].tx_errs = 0;
1042 }
1043
1044#ifndef final_version
1045 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
1046 printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1047 dev->name, dirty_tx, yp->cur_tx, yp->tx_full);
1048 dirty_tx += TX_RING_SIZE;
1049 }
1050#endif
1051
1052 if (yp->tx_full
1053 && yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1054 /* The ring is no longer full, clear tbusy. */
1055 yp->tx_full = 0;
1056 netif_wake_queue(dev);
1057 }
1058
1059 yp->dirty_tx = dirty_tx;
1060 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1061 }
1062#endif
1063
1064 /* Log errors and other uncommon events. */
1065 if (intr_status & 0x2ee) /* Abnormal error summary. */
1066 yellowfin_error(dev, intr_status);
1067
1068 if (--boguscnt < 0) {
1069 printk(KERN_WARNING "%s: Too much work at interrupt, "
1070 "status=0x%4.4x.\n",
1071 dev->name, intr_status);
1072 break;
1073 }
1074 } while (1);
1075
1076 if (yellowfin_debug > 3)
1077 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1078 dev->name, ioread16(ioaddr + IntrStatus));
1079
1080 spin_unlock (&yp->lock);
1081 return IRQ_RETVAL(handled);
1082}
1083
1084/* This routine is logically part of the interrupt handler, but separated
1085 for clarity and better register allocation. */
1086static int yellowfin_rx(struct net_device *dev)
1087{
1088 struct yellowfin_private *yp = netdev_priv(dev);
1089 int entry = yp->cur_rx % RX_RING_SIZE;
1090 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1091
1092 if (yellowfin_debug > 4) {
1093 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %8.8x.\n",
1094 entry, yp->rx_ring[entry].result_status);
1095 printk(KERN_DEBUG " #%d desc. %8.8x %8.8x %8.8x.\n",
1096 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1097 yp->rx_ring[entry].result_status);
1098 }
1099
1100 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1101 while (1) {
1102 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1103 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1104 s16 frame_status;
1105 u16 desc_status;
1106 int data_size;
1107 u8 *buf_addr;
1108
1109 if(!desc->result_status)
1110 break;
1111 pci_dma_sync_single_for_cpu(yp->pci_dev, desc->addr,
1112 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1113 desc_status = le32_to_cpu(desc->result_status) >> 16;
1114 buf_addr = rx_skb->tail;
1115 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1116 le32_to_cpu(desc->result_status)) & 0xffff;
1117 frame_status = le16_to_cpu(get_unaligned((s16*)&(buf_addr[data_size - 2])));
1118 if (yellowfin_debug > 4)
1119 printk(KERN_DEBUG " yellowfin_rx() status was %4.4x.\n",
1120 frame_status);
1121 if (--boguscnt < 0)
1122 break;
1123 if ( ! (desc_status & RX_EOP)) {
1124 if (data_size != 0)
1125 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned multiple buffers,"
1126 " status %4.4x, data_size %d!\n", dev->name, desc_status, data_size);
1127 yp->stats.rx_length_errors++;
1128 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1129 /* There was a error. */
1130 if (yellowfin_debug > 3)
1131 printk(KERN_DEBUG " yellowfin_rx() Rx error was %4.4x.\n",
1132 frame_status);
1133 yp->stats.rx_errors++;
1134 if (frame_status & 0x0060) yp->stats.rx_length_errors++;
1135 if (frame_status & 0x0008) yp->stats.rx_frame_errors++;
1136 if (frame_status & 0x0010) yp->stats.rx_crc_errors++;
1137 if (frame_status < 0) yp->stats.rx_dropped++;
1138 } else if ( !(yp->drv_flags & IsGigabit) &&
1139 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1140 u8 status1 = buf_addr[data_size-2];
1141 u8 status2 = buf_addr[data_size-1];
1142 yp->stats.rx_errors++;
1143 if (status1 & 0xC0) yp->stats.rx_length_errors++;
1144 if (status2 & 0x03) yp->stats.rx_frame_errors++;
1145 if (status2 & 0x04) yp->stats.rx_crc_errors++;
1146 if (status2 & 0x80) yp->stats.rx_dropped++;
1147#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1148 } else if ((yp->flags & HasMACAddrBug) &&
1149 memcmp(le32_to_cpu(yp->rx_ring_dma +
1150 entry*sizeof(struct yellowfin_desc)),
1151 dev->dev_addr, 6) != 0 &&
1152 memcmp(le32_to_cpu(yp->rx_ring_dma +
1153 entry*sizeof(struct yellowfin_desc)),
1154 "\377\377\377\377\377\377", 6) != 0) {
1155 if (bogus_rx++ == 0)
1156 printk(KERN_WARNING "%s: Bad frame to %2.2x:%2.2x:%2.2x:%2.2x:"
1157 "%2.2x:%2.2x.\n",
1158 dev->name, buf_addr[0], buf_addr[1], buf_addr[2],
1159 buf_addr[3], buf_addr[4], buf_addr[5]);
1160#endif
1161 } else {
1162 struct sk_buff *skb;
1163 int pkt_len = data_size -
1164 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1165 /* To verify: Yellowfin Length should omit the CRC! */
1166
1167#ifndef final_version
1168 if (yellowfin_debug > 4)
1169 printk(KERN_DEBUG " yellowfin_rx() normal Rx pkt length %d"
1170 " of %d, bogus_cnt %d.\n",
1171 pkt_len, data_size, boguscnt);
1172#endif
1173 /* Check if the packet is long enough to just pass up the skbuff
1174 without copying to a properly sized skbuff. */
1175 if (pkt_len > rx_copybreak) {
1176 skb_put(skb = rx_skb, pkt_len);
1177 pci_unmap_single(yp->pci_dev,
1178 yp->rx_ring[entry].addr,
1179 yp->rx_buf_sz,
1180 PCI_DMA_FROMDEVICE);
1181 yp->rx_skbuff[entry] = NULL;
1182 } else {
1183 skb = dev_alloc_skb(pkt_len + 2);
1184 if (skb == NULL)
1185 break;
1186 skb->dev = dev;
1187 skb_reserve(skb, 2); /* 16 byte align the IP header */
1188 eth_copy_and_sum(skb, rx_skb->tail, pkt_len, 0);
1189 skb_put(skb, pkt_len);
1190 pci_dma_sync_single_for_device(yp->pci_dev, desc->addr,
1191 yp->rx_buf_sz,
1192 PCI_DMA_FROMDEVICE);
1193 }
1194 skb->protocol = eth_type_trans(skb, dev);
1195 netif_rx(skb);
1196 dev->last_rx = jiffies;
1197 yp->stats.rx_packets++;
1198 yp->stats.rx_bytes += pkt_len;
1199 }
1200 entry = (++yp->cur_rx) % RX_RING_SIZE;
1201 }
1202
1203 /* Refill the Rx ring buffers. */
1204 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1205 entry = yp->dirty_rx % RX_RING_SIZE;
1206 if (yp->rx_skbuff[entry] == NULL) {
1207 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
1208 if (skb == NULL)
1209 break; /* Better luck next round. */
1210 yp->rx_skbuff[entry] = skb;
1211 skb->dev = dev; /* Mark as being used by this device. */
1212 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1213 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1214 skb->tail, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1215 }
1216 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1217 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1218 if (entry != 0)
1219 yp->rx_ring[entry - 1].dbdma_cmd =
1220 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1221 else
1222 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1223 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1224 | yp->rx_buf_sz);
1225 }
1226
1227 return 0;
1228}
1229
1230static void yellowfin_error(struct net_device *dev, int intr_status)
1231{
1232 struct yellowfin_private *yp = netdev_priv(dev);
1233
1234 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1235 dev->name, intr_status);
1236 /* Hmmmmm, it's not clear what to do here. */
1237 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1238 yp->stats.tx_errors++;
1239 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1240 yp->stats.rx_errors++;
1241}
1242
1243static int yellowfin_close(struct net_device *dev)
1244{
1245 struct yellowfin_private *yp = netdev_priv(dev);
1246 void __iomem *ioaddr = yp->base;
1247 int i;
1248
1249 netif_stop_queue (dev);
1250
1251 if (yellowfin_debug > 1) {
1252 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x "
1253 "Rx %4.4x Int %2.2x.\n",
1254 dev->name, ioread16(ioaddr + TxStatus),
1255 ioread16(ioaddr + RxStatus),
1256 ioread16(ioaddr + IntrStatus));
1257 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1258 dev->name, yp->cur_tx, yp->dirty_tx, yp->cur_rx, yp->dirty_rx);
1259 }
1260
1261 /* Disable interrupts by clearing the interrupt mask. */
1262 iowrite16(0x0000, ioaddr + IntrEnb);
1263
1264 /* Stop the chip's Tx and Rx processes. */
1265 iowrite32(0x80000000, ioaddr + RxCtrl);
1266 iowrite32(0x80000000, ioaddr + TxCtrl);
1267
1268 del_timer(&yp->timer);
1269
1270#if defined(__i386__)
1271 if (yellowfin_debug > 2) {
1272 printk("\n"KERN_DEBUG" Tx ring at %8.8llx:\n",
1273 (unsigned long long)yp->tx_ring_dma);
1274 for (i = 0; i < TX_RING_SIZE*2; i++)
1275 printk(" %c #%d desc. %8.8x %8.8x %8.8x %8.8x.\n",
1276 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1277 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1278 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1279 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1280 for (i = 0; i < TX_RING_SIZE; i++)
1281 printk(" #%d status %4.4x %4.4x %4.4x %4.4x.\n",
1282 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1283 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1284
1285 printk("\n"KERN_DEBUG " Rx ring %8.8llx:\n",
1286 (unsigned long long)yp->rx_ring_dma);
1287 for (i = 0; i < RX_RING_SIZE; i++) {
1288 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x\n",
1289 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1290 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1291 yp->rx_ring[i].result_status);
1292 if (yellowfin_debug > 6) {
1293 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1294 int j;
1295 for (j = 0; j < 0x50; j++)
1296 printk(" %4.4x",
1297 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1298 printk("\n");
1299 }
1300 }
1301 }
1302 }
1303#endif /* __i386__ debugging only */
1304
1305 free_irq(dev->irq, dev);
1306
1307 /* Free all the skbuffs in the Rx queue. */
1308 for (i = 0; i < RX_RING_SIZE; i++) {
1309 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1310 yp->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
1311 if (yp->rx_skbuff[i]) {
1312 dev_kfree_skb(yp->rx_skbuff[i]);
1313 }
1314 yp->rx_skbuff[i] = NULL;
1315 }
1316 for (i = 0; i < TX_RING_SIZE; i++) {
1317 if (yp->tx_skbuff[i])
1318 dev_kfree_skb(yp->tx_skbuff[i]);
1319 yp->tx_skbuff[i] = NULL;
1320 }
1321
1322#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1323 if (yellowfin_debug > 0) {
1324 printk(KERN_DEBUG "%s: Received %d frames that we should not have.\n",
1325 dev->name, bogus_rx);
1326 }
1327#endif
1328
1329 return 0;
1330}
1331
1332static struct net_device_stats *yellowfin_get_stats(struct net_device *dev)
1333{
1334 struct yellowfin_private *yp = netdev_priv(dev);
1335 return &yp->stats;
1336}
1337
1338/* Set or clear the multicast filter for this adaptor. */
1339
1340static void set_rx_mode(struct net_device *dev)
1341{
1342 struct yellowfin_private *yp = netdev_priv(dev);
1343 void __iomem *ioaddr = yp->base;
1344 u16 cfg_value = ioread16(ioaddr + Cnfg);
1345
1346 /* Stop the Rx process to change any value. */
1347 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1348 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1349 /* Unconditionally log net taps. */
1350 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1351 iowrite16(0x000F, ioaddr + AddrMode);
1352 } else if ((dev->mc_count > 64) || (dev->flags & IFF_ALLMULTI)) {
1353 /* Too many to filter well, or accept all multicasts. */
1354 iowrite16(0x000B, ioaddr + AddrMode);
1355 } else if (dev->mc_count > 0) { /* Must use the multicast hash table. */
1356 struct dev_mc_list *mclist;
1357 u16 hash_table[4];
1358 int i;
1359 memset(hash_table, 0, sizeof(hash_table));
1360 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1361 i++, mclist = mclist->next) {
1362 unsigned int bit;
1363
1364 /* Due to a bug in the early chip versions, multiple filter
1365 slots must be set for each address. */
1366 if (yp->drv_flags & HasMulticastBug) {
1367 bit = (ether_crc_le(3, mclist->dmi_addr) >> 3) & 0x3f;
1368 hash_table[bit >> 4] |= (1 << bit);
1369 bit = (ether_crc_le(4, mclist->dmi_addr) >> 3) & 0x3f;
1370 hash_table[bit >> 4] |= (1 << bit);
1371 bit = (ether_crc_le(5, mclist->dmi_addr) >> 3) & 0x3f;
1372 hash_table[bit >> 4] |= (1 << bit);
1373 }
1374 bit = (ether_crc_le(6, mclist->dmi_addr) >> 3) & 0x3f;
1375 hash_table[bit >> 4] |= (1 << bit);
1376 }
1377 /* Copy the hash table to the chip. */
1378 for (i = 0; i < 4; i++)
1379 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1380 iowrite16(0x0003, ioaddr + AddrMode);
1381 } else { /* Normal, unicast/broadcast-only mode. */
1382 iowrite16(0x0001, ioaddr + AddrMode);
1383 }
1384 /* Restart the Rx process. */
1385 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1386}
1387
1388static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1389{
1390 struct yellowfin_private *np = netdev_priv(dev);
1391 strcpy(info->driver, DRV_NAME);
1392 strcpy(info->version, DRV_VERSION);
1393 strcpy(info->bus_info, pci_name(np->pci_dev));
1394}
1395
1396static struct ethtool_ops ethtool_ops = {
1397 .get_drvinfo = yellowfin_get_drvinfo
1398};
1399
1400static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1401{
1402 struct yellowfin_private *np = netdev_priv(dev);
1403 void __iomem *ioaddr = np->base;
1404 struct mii_ioctl_data *data = if_mii(rq);
1405
1406 switch(cmd) {
1407 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1408 data->phy_id = np->phys[0] & 0x1f;
1409 /* Fall Through */
1410
1411 case SIOCGMIIREG: /* Read MII PHY register. */
1412 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1413 return 0;
1414
1415 case SIOCSMIIREG: /* Write MII PHY register. */
1416 if (!capable(CAP_NET_ADMIN))
1417 return -EPERM;
1418 if (data->phy_id == np->phys[0]) {
1419 u16 value = data->val_in;
1420 switch (data->reg_num) {
1421 case 0:
1422 /* Check for autonegotiation on or reset. */
1423 np->medialock = (value & 0x9000) ? 0 : 1;
1424 if (np->medialock)
1425 np->full_duplex = (value & 0x0100) ? 1 : 0;
1426 break;
1427 case 4: np->advertising = value; break;
1428 }
1429 /* Perhaps check_duplex(dev), depending on chip semantics. */
1430 }
1431 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1432 return 0;
1433 default:
1434 return -EOPNOTSUPP;
1435 }
1436}
1437
1438
1439static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1440{
1441 struct net_device *dev = pci_get_drvdata(pdev);
1442 struct yellowfin_private *np;
1443
1444 if (!dev)
1445 BUG();
1446 np = netdev_priv(dev);
1447
1448 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1449 np->tx_status_dma);
1450 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1451 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1452 unregister_netdev (dev);
1453
1454 pci_iounmap(pdev, np->base);
1455
1456 pci_release_regions (pdev);
1457
1458 free_netdev (dev);
1459 pci_set_drvdata(pdev, NULL);
1460}
1461
1462
1463static struct pci_driver yellowfin_driver = {
1464 .name = DRV_NAME,
1465 .id_table = yellowfin_pci_tbl,
1466 .probe = yellowfin_init_one,
1467 .remove = __devexit_p(yellowfin_remove_one),
1468};
1469
1470
1471static int __init yellowfin_init (void)
1472{
1473/* when a module, this is printed whether or not devices are found in probe */
1474#ifdef MODULE
1475 printk(version);
1476#endif
1477 return pci_module_init (&yellowfin_driver);
1478}
1479
1480
1481static void __exit yellowfin_cleanup (void)
1482{
1483 pci_unregister_driver (&yellowfin_driver);
1484}
1485
1486
1487module_init(yellowfin_init);
1488module_exit(yellowfin_cleanup);
1489
1490/*
1491 * Local variables:
1492 * compile-command: "gcc -DMODULE -Wall -Wstrict-prototypes -O6 -c yellowfin.c"
1493 * compile-command-alphaLX: "gcc -DMODULE -Wall -Wstrict-prototypes -O2 -c yellowfin.c -fomit-frame-pointer -fno-strength-reduce -mno-fp-regs -Wa,-m21164a -DBWX_USABLE -DBWIO_ENABLED"
1494 * simple-compile-command: "gcc -DMODULE -O6 -c yellowfin.c"
1495 * c-indent-level: 4
1496 * c-basic-offset: 4
1497 * tab-width: 4
1498 * End:
1499 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 11:12:32 -0500