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authorSujith <Sujith.Manoharan@atheros.com>2009-02-09 02:57:26 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-02-13 13:45:10 -0500
commit2660b81a378ab227b78c4cc618453fa7e19a7c7b (patch)
treeea305af43f0e27c86538fecce6c9a4e0151dbc78 /drivers/net/wireless
parentf74df6fbe31561091bf42be0ed30232be2b9d3ac (diff)
ath9k: Remove all the useless ah_ variable prefixes
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/ath9k/ani.c186
-rw-r--r--drivers/net/wireless/ath9k/ani.h6
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h6
-rw-r--r--drivers/net/wireless/ath9k/beacon.c26
-rw-r--r--drivers/net/wireless/ath9k/calib.c122
-rw-r--r--drivers/net/wireless/ath9k/calib.h14
-rw-r--r--drivers/net/wireless/ath9k/eeprom.c102
-rw-r--r--drivers/net/wireless/ath9k/eeprom.h2
-rw-r--r--drivers/net/wireless/ath9k/hw.c602
-rw-r--r--drivers/net/wireless/ath9k/hw.h216
-rw-r--r--drivers/net/wireless/ath9k/mac.c94
-rw-r--r--drivers/net/wireless/ath9k/main.c92
-rw-r--r--drivers/net/wireless/ath9k/pci.c4
-rw-r--r--drivers/net/wireless/ath9k/phy.c176
-rw-r--r--drivers/net/wireless/ath9k/phy.h2
-rw-r--r--drivers/net/wireless/ath9k/rc.c12
-rw-r--r--drivers/net/wireless/ath9k/recv.c18
-rw-r--r--drivers/net/wireless/ath9k/xmit.c6
18 files changed, 841 insertions, 845 deletions
diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c
index 6bd2d5766019..d4df7e611df5 100644
--- a/drivers/net/wireless/ath9k/ani.c
+++ b/drivers/net/wireless/ath9k/ani.c
@@ -21,12 +21,12 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
21{ 21{
22 int i; 22 int i;
23 23
24 for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { 24 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
25 if (ah->ah_ani[i].c && 25 if (ah->ani[i].c &&
26 ah->ah_ani[i].c->channel == chan->channel) 26 ah->ani[i].c->channel == chan->channel)
27 return i; 27 return i;
28 if (ah->ah_ani[i].c == NULL) { 28 if (ah->ani[i].c == NULL) {
29 ah->ah_ani[i].c = chan; 29 ah->ani[i].c = chan;
30 return i; 30 return i;
31 } 31 }
32 } 32 }
@@ -40,37 +40,37 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
40static bool ath9k_hw_ani_control(struct ath_hw *ah, 40static bool ath9k_hw_ani_control(struct ath_hw *ah,
41 enum ath9k_ani_cmd cmd, int param) 41 enum ath9k_ani_cmd cmd, int param)
42{ 42{
43 struct ar5416AniState *aniState = ah->ah_curani; 43 struct ar5416AniState *aniState = ah->curani;
44 44
45 switch (cmd & ah->ah_ani_function) { 45 switch (cmd & ah->ani_function) {
46 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ 46 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
47 u32 level = param; 47 u32 level = param;
48 48
49 if (level >= ARRAY_SIZE(ah->ah_totalSizeDesired)) { 49 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
50 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 50 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
51 "level out of range (%u > %u)\n", 51 "level out of range (%u > %u)\n",
52 level, 52 level,
53 (unsigned)ARRAY_SIZE(ah->ah_totalSizeDesired)); 53 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
54 return false; 54 return false;
55 } 55 }
56 56
57 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 57 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
58 AR_PHY_DESIRED_SZ_TOT_DES, 58 AR_PHY_DESIRED_SZ_TOT_DES,
59 ah->ah_totalSizeDesired[level]); 59 ah->totalSizeDesired[level]);
60 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 60 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
61 AR_PHY_AGC_CTL1_COARSE_LOW, 61 AR_PHY_AGC_CTL1_COARSE_LOW,
62 ah->ah_coarseLow[level]); 62 ah->coarse_low[level]);
63 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 63 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
64 AR_PHY_AGC_CTL1_COARSE_HIGH, 64 AR_PHY_AGC_CTL1_COARSE_HIGH,
65 ah->ah_coarseHigh[level]); 65 ah->coarse_high[level]);
66 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 66 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
67 AR_PHY_FIND_SIG_FIRPWR, 67 AR_PHY_FIND_SIG_FIRPWR,
68 ah->ah_firpwr[level]); 68 ah->firpwr[level]);
69 69
70 if (level > aniState->noiseImmunityLevel) 70 if (level > aniState->noiseImmunityLevel)
71 ah->ah_stats.ast_ani_niup++; 71 ah->stats.ast_ani_niup++;
72 else if (level < aniState->noiseImmunityLevel) 72 else if (level < aniState->noiseImmunityLevel)
73 ah->ah_stats.ast_ani_nidown++; 73 ah->stats.ast_ani_nidown++;
74 aniState->noiseImmunityLevel = level; 74 aniState->noiseImmunityLevel = level;
75 break; 75 break;
76 } 76 }
@@ -124,9 +124,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
124 124
125 if (!on != aniState->ofdmWeakSigDetectOff) { 125 if (!on != aniState->ofdmWeakSigDetectOff) {
126 if (on) 126 if (on)
127 ah->ah_stats.ast_ani_ofdmon++; 127 ah->stats.ast_ani_ofdmon++;
128 else 128 else
129 ah->ah_stats.ast_ani_ofdmoff++; 129 ah->stats.ast_ani_ofdmoff++;
130 aniState->ofdmWeakSigDetectOff = !on; 130 aniState->ofdmWeakSigDetectOff = !on;
131 } 131 }
132 break; 132 break;
@@ -140,9 +140,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
140 weakSigThrCck[high]); 140 weakSigThrCck[high]);
141 if (high != aniState->cckWeakSigThreshold) { 141 if (high != aniState->cckWeakSigThreshold) {
142 if (high) 142 if (high)
143 ah->ah_stats.ast_ani_cckhigh++; 143 ah->stats.ast_ani_cckhigh++;
144 else 144 else
145 ah->ah_stats.ast_ani_ccklow++; 145 ah->stats.ast_ani_ccklow++;
146 aniState->cckWeakSigThreshold = high; 146 aniState->cckWeakSigThreshold = high;
147 } 147 }
148 break; 148 break;
@@ -162,9 +162,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
162 AR_PHY_FIND_SIG_FIRSTEP, 162 AR_PHY_FIND_SIG_FIRSTEP,
163 firstep[level]); 163 firstep[level]);
164 if (level > aniState->firstepLevel) 164 if (level > aniState->firstepLevel)
165 ah->ah_stats.ast_ani_stepup++; 165 ah->stats.ast_ani_stepup++;
166 else if (level < aniState->firstepLevel) 166 else if (level < aniState->firstepLevel)
167 ah->ah_stats.ast_ani_stepdown++; 167 ah->stats.ast_ani_stepdown++;
168 aniState->firstepLevel = level; 168 aniState->firstepLevel = level;
169 break; 169 break;
170 } 170 }
@@ -185,9 +185,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
185 AR_PHY_TIMING5_CYCPWR_THR1, 185 AR_PHY_TIMING5_CYCPWR_THR1,
186 cycpwrThr1[level]); 186 cycpwrThr1[level]);
187 if (level > aniState->spurImmunityLevel) 187 if (level > aniState->spurImmunityLevel)
188 ah->ah_stats.ast_ani_spurup++; 188 ah->stats.ast_ani_spurup++;
189 else if (level < aniState->spurImmunityLevel) 189 else if (level < aniState->spurImmunityLevel)
190 ah->ah_stats.ast_ani_spurdown++; 190 ah->stats.ast_ani_spurdown++;
191 aniState->spurImmunityLevel = level; 191 aniState->spurImmunityLevel = level;
192 break; 192 break;
193 } 193 }
@@ -235,10 +235,10 @@ static void ath9k_ani_restart(struct ath_hw *ah)
235 if (!DO_ANI(ah)) 235 if (!DO_ANI(ah))
236 return; 236 return;
237 237
238 aniState = ah->ah_curani; 238 aniState = ah->curani;
239 239
240 aniState->listenTime = 0; 240 aniState->listenTime = 0;
241 if (ah->ah_hasHwPhyCounters) { 241 if (ah->has_hw_phycounters) {
242 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { 242 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
243 aniState->ofdmPhyErrBase = 0; 243 aniState->ofdmPhyErrBase = 0;
244 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 244 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
@@ -279,7 +279,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
279 if (!DO_ANI(ah)) 279 if (!DO_ANI(ah))
280 return; 280 return;
281 281
282 aniState = ah->ah_curani; 282 aniState = ah->curani;
283 283
284 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { 284 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
285 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 285 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
@@ -295,7 +295,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
295 } 295 }
296 } 296 }
297 297
298 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 298 if (ah->opmode == NL80211_IFTYPE_AP) {
299 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { 299 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
300 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 300 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
301 aniState->firstepLevel + 1); 301 aniState->firstepLevel + 1);
@@ -350,14 +350,14 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
350 if (!DO_ANI(ah)) 350 if (!DO_ANI(ah))
351 return; 351 return;
352 352
353 aniState = ah->ah_curani; 353 aniState = ah->curani;
354 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { 354 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
355 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 355 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
356 aniState->noiseImmunityLevel + 1)) { 356 aniState->noiseImmunityLevel + 1)) {
357 return; 357 return;
358 } 358 }
359 } 359 }
360 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 360 if (ah->opmode == NL80211_IFTYPE_AP) {
361 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { 361 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
362 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 362 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
363 aniState->firstepLevel + 1); 363 aniState->firstepLevel + 1);
@@ -383,9 +383,9 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
383 struct ar5416AniState *aniState; 383 struct ar5416AniState *aniState;
384 int32_t rssi; 384 int32_t rssi;
385 385
386 aniState = ah->ah_curani; 386 aniState = ah->curani;
387 387
388 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 388 if (ah->opmode == NL80211_IFTYPE_AP) {
389 if (aniState->firstepLevel > 0) { 389 if (aniState->firstepLevel > 0) {
390 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 390 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
391 aniState->firstepLevel - 1)) 391 aniState->firstepLevel - 1))
@@ -441,11 +441,11 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
441 rxFrameCount = REG_READ(ah, AR_RFCNT); 441 rxFrameCount = REG_READ(ah, AR_RFCNT);
442 cycleCount = REG_READ(ah, AR_CCCNT); 442 cycleCount = REG_READ(ah, AR_CCCNT);
443 443
444 aniState = ah->ah_curani; 444 aniState = ah->curani;
445 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { 445 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
446 446
447 listenTime = 0; 447 listenTime = 0;
448 ah->ah_stats.ast_ani_lzero++; 448 ah->stats.ast_ani_lzero++;
449 } else { 449 } else {
450 int32_t ccdelta = cycleCount - aniState->cycleCount; 450 int32_t ccdelta = cycleCount - aniState->cycleCount;
451 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; 451 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
@@ -462,21 +462,21 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
462void ath9k_ani_reset(struct ath_hw *ah) 462void ath9k_ani_reset(struct ath_hw *ah)
463{ 463{
464 struct ar5416AniState *aniState; 464 struct ar5416AniState *aniState;
465 struct ath9k_channel *chan = ah->ah_curchan; 465 struct ath9k_channel *chan = ah->curchan;
466 int index; 466 int index;
467 467
468 if (!DO_ANI(ah)) 468 if (!DO_ANI(ah))
469 return; 469 return;
470 470
471 index = ath9k_hw_get_ani_channel_idx(ah, chan); 471 index = ath9k_hw_get_ani_channel_idx(ah, chan);
472 aniState = &ah->ah_ani[index]; 472 aniState = &ah->ani[index];
473 ah->ah_curani = aniState; 473 ah->curani = aniState;
474 474
475 if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION 475 if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
476 && ah->ah_opmode != NL80211_IFTYPE_ADHOC) { 476 && ah->opmode != NL80211_IFTYPE_ADHOC) {
477 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 477 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
478 "Reset ANI state opmode %u\n", ah->ah_opmode); 478 "Reset ANI state opmode %u\n", ah->opmode);
479 ah->ah_stats.ast_ani_reset++; 479 ah->stats.ast_ani_reset++;
480 480
481 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); 481 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
482 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); 482 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
@@ -489,15 +489,15 @@ void ath9k_ani_reset(struct ath_hw *ah)
489 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) | 489 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
490 ATH9K_RX_FILTER_PHYERR); 490 ATH9K_RX_FILTER_PHYERR);
491 491
492 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 492 if (ah->opmode == NL80211_IFTYPE_AP) {
493 ah->ah_curani->ofdmTrigHigh = 493 ah->curani->ofdmTrigHigh =
494 ah->ah_config.ofdm_trig_high; 494 ah->config.ofdm_trig_high;
495 ah->ah_curani->ofdmTrigLow = 495 ah->curani->ofdmTrigLow =
496 ah->ah_config.ofdm_trig_low; 496 ah->config.ofdm_trig_low;
497 ah->ah_curani->cckTrigHigh = 497 ah->curani->cckTrigHigh =
498 ah->ah_config.cck_trig_high; 498 ah->config.cck_trig_high;
499 ah->ah_curani->cckTrigLow = 499 ah->curani->cckTrigLow =
500 ah->ah_config.cck_trig_low; 500 ah->config.cck_trig_low;
501 } 501 }
502 ath9k_ani_restart(ah); 502 ath9k_ani_restart(ah);
503 return; 503 return;
@@ -518,7 +518,7 @@ void ath9k_ani_reset(struct ath_hw *ah)
518 if (aniState->firstepLevel != 0) 518 if (aniState->firstepLevel != 0)
519 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 519 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
520 aniState->firstepLevel); 520 aniState->firstepLevel);
521 if (ah->ah_hasHwPhyCounters) { 521 if (ah->has_hw_phycounters) {
522 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & 522 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
523 ~ATH9K_RX_FILTER_PHYERR); 523 ~ATH9K_RX_FILTER_PHYERR);
524 ath9k_ani_restart(ah); 524 ath9k_ani_restart(ah);
@@ -542,19 +542,19 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
542 if (!DO_ANI(ah)) 542 if (!DO_ANI(ah))
543 return; 543 return;
544 544
545 aniState = ah->ah_curani; 545 aniState = ah->curani;
546 ah->ah_stats.ast_nodestats = *stats; 546 ah->stats.ast_nodestats = *stats;
547 547
548 listenTime = ath9k_hw_ani_get_listen_time(ah); 548 listenTime = ath9k_hw_ani_get_listen_time(ah);
549 if (listenTime < 0) { 549 if (listenTime < 0) {
550 ah->ah_stats.ast_ani_lneg++; 550 ah->stats.ast_ani_lneg++;
551 ath9k_ani_restart(ah); 551 ath9k_ani_restart(ah);
552 return; 552 return;
553 } 553 }
554 554
555 aniState->listenTime += listenTime; 555 aniState->listenTime += listenTime;
556 556
557 if (ah->ah_hasHwPhyCounters) { 557 if (ah->has_hw_phycounters) {
558 u32 phyCnt1, phyCnt2; 558 u32 phyCnt1, phyCnt2;
559 u32 ofdmPhyErrCnt, cckPhyErrCnt; 559 u32 ofdmPhyErrCnt, cckPhyErrCnt;
560 560
@@ -591,24 +591,24 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
591 } 591 }
592 592
593 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; 593 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
594 ah->ah_stats.ast_ani_ofdmerrs += 594 ah->stats.ast_ani_ofdmerrs +=
595 ofdmPhyErrCnt - aniState->ofdmPhyErrCount; 595 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
596 aniState->ofdmPhyErrCount = ofdmPhyErrCnt; 596 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
597 597
598 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; 598 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
599 ah->ah_stats.ast_ani_cckerrs += 599 ah->stats.ast_ani_cckerrs +=
600 cckPhyErrCnt - aniState->cckPhyErrCount; 600 cckPhyErrCnt - aniState->cckPhyErrCount;
601 aniState->cckPhyErrCount = cckPhyErrCnt; 601 aniState->cckPhyErrCount = cckPhyErrCnt;
602 } 602 }
603 603
604 if (aniState->listenTime > 5 * ah->ah_aniPeriod) { 604 if (aniState->listenTime > 5 * ah->aniperiod) {
605 if (aniState->ofdmPhyErrCount <= aniState->listenTime * 605 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
606 aniState->ofdmTrigLow / 1000 && 606 aniState->ofdmTrigLow / 1000 &&
607 aniState->cckPhyErrCount <= aniState->listenTime * 607 aniState->cckPhyErrCount <= aniState->listenTime *
608 aniState->cckTrigLow / 1000) 608 aniState->cckTrigLow / 1000)
609 ath9k_hw_ani_lower_immunity(ah); 609 ath9k_hw_ani_lower_immunity(ah);
610 ath9k_ani_restart(ah); 610 ath9k_ani_restart(ah);
611 } else if (aniState->listenTime > ah->ah_aniPeriod) { 611 } else if (aniState->listenTime > ah->aniperiod) {
612 if (aniState->ofdmPhyErrCount > aniState->listenTime * 612 if (aniState->ofdmPhyErrCount > aniState->listenTime *
613 aniState->ofdmTrigHigh / 1000) { 613 aniState->ofdmTrigHigh / 1000) {
614 ath9k_hw_ani_ofdm_err_trigger(ah); 614 ath9k_hw_ani_ofdm_err_trigger(ah);
@@ -624,7 +624,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
624 624
625bool ath9k_hw_phycounters(struct ath_hw *ah) 625bool ath9k_hw_phycounters(struct ath_hw *ah)
626{ 626{
627 return ah->ah_hasHwPhyCounters ? true : false; 627 return ah->has_hw_phycounters ? true : false;
628} 628}
629 629
630void ath9k_enable_mib_counters(struct ath_hw *ah) 630void ath9k_enable_mib_counters(struct ath_hw *ah)
@@ -712,7 +712,7 @@ void ath9k_hw_procmibevent(struct ath_hw *ah,
712 712
713 /* Clear the mib counters and save them in the stats */ 713 /* Clear the mib counters and save them in the stats */
714 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 714 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
715 ah->ah_stats.ast_nodestats = *stats; 715 ah->stats.ast_nodestats = *stats;
716 716
717 if (!DO_ANI(ah)) 717 if (!DO_ANI(ah))
718 return; 718 return;
@@ -722,17 +722,17 @@ void ath9k_hw_procmibevent(struct ath_hw *ah,
722 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 722 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
723 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || 723 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
724 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { 724 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
725 struct ar5416AniState *aniState = ah->ah_curani; 725 struct ar5416AniState *aniState = ah->curani;
726 u32 ofdmPhyErrCnt, cckPhyErrCnt; 726 u32 ofdmPhyErrCnt, cckPhyErrCnt;
727 727
728 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ 728 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
729 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; 729 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
730 ah->ah_stats.ast_ani_ofdmerrs += 730 ah->stats.ast_ani_ofdmerrs +=
731 ofdmPhyErrCnt - aniState->ofdmPhyErrCount; 731 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
732 aniState->ofdmPhyErrCount = ofdmPhyErrCnt; 732 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
733 733
734 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; 734 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
735 ah->ah_stats.ast_ani_cckerrs += 735 ah->stats.ast_ani_cckerrs +=
736 cckPhyErrCnt - aniState->cckPhyErrCount; 736 cckPhyErrCnt - aniState->cckPhyErrCount;
737 aniState->cckPhyErrCount = cckPhyErrCnt; 737 aniState->cckPhyErrCount = cckPhyErrCnt;
738 738
@@ -761,10 +761,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah)
761 const int firpwr[] = { -78, -78, -78, -78, -80 }; 761 const int firpwr[] = { -78, -78, -78, -78, -80 };
762 762
763 for (i = 0; i < 5; i++) { 763 for (i = 0; i < 5; i++) {
764 ah->ah_totalSizeDesired[i] = totalSizeDesired[i]; 764 ah->totalSizeDesired[i] = totalSizeDesired[i];
765 ah->ah_coarseHigh[i] = coarseHigh[i]; 765 ah->coarse_high[i] = coarseHigh[i];
766 ah->ah_coarseLow[i] = coarseLow[i]; 766 ah->coarse_low[i] = coarseLow[i];
767 ah->ah_firpwr[i] = firpwr[i]; 767 ah->firpwr[i] = firpwr[i];
768 } 768 }
769} 769}
770 770
@@ -774,50 +774,50 @@ void ath9k_hw_ani_attach(struct ath_hw *ah)
774 774
775 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n"); 775 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n");
776 776
777 ah->ah_hasHwPhyCounters = 1; 777 ah->has_hw_phycounters = 1;
778 778
779 memset(ah->ah_ani, 0, sizeof(ah->ah_ani)); 779 memset(ah->ani, 0, sizeof(ah->ani));
780 for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { 780 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
781 ah->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; 781 ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
782 ah->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; 782 ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
783 ah->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; 783 ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
784 ah->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; 784 ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
785 ah->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; 785 ah->ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
786 ah->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; 786 ah->ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
787 ah->ah_ani[i].ofdmWeakSigDetectOff = 787 ah->ani[i].ofdmWeakSigDetectOff =
788 !ATH9K_ANI_USE_OFDM_WEAK_SIG; 788 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
789 ah->ah_ani[i].cckWeakSigThreshold = 789 ah->ani[i].cckWeakSigThreshold =
790 ATH9K_ANI_CCK_WEAK_SIG_THR; 790 ATH9K_ANI_CCK_WEAK_SIG_THR;
791 ah->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 791 ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
792 ah->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 792 ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
793 if (ah->ah_hasHwPhyCounters) { 793 if (ah->has_hw_phycounters) {
794 ah->ah_ani[i].ofdmPhyErrBase = 794 ah->ani[i].ofdmPhyErrBase =
795 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; 795 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
796 ah->ah_ani[i].cckPhyErrBase = 796 ah->ani[i].cckPhyErrBase =
797 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; 797 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
798 } 798 }
799 } 799 }
800 if (ah->ah_hasHwPhyCounters) { 800 if (ah->has_hw_phycounters) {
801 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 801 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
802 "Setting OfdmErrBase = 0x%08x\n", 802 "Setting OfdmErrBase = 0x%08x\n",
803 ah->ah_ani[0].ofdmPhyErrBase); 803 ah->ani[0].ofdmPhyErrBase);
804 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", 804 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
805 ah->ah_ani[0].cckPhyErrBase); 805 ah->ani[0].cckPhyErrBase);
806 806
807 REG_WRITE(ah, AR_PHY_ERR_1, ah->ah_ani[0].ofdmPhyErrBase); 807 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
808 REG_WRITE(ah, AR_PHY_ERR_2, ah->ah_ani[0].cckPhyErrBase); 808 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
809 ath9k_enable_mib_counters(ah); 809 ath9k_enable_mib_counters(ah);
810 } 810 }
811 ah->ah_aniPeriod = ATH9K_ANI_PERIOD; 811 ah->aniperiod = ATH9K_ANI_PERIOD;
812 if (ah->ah_config.enable_ani) 812 if (ah->config.enable_ani)
813 ah->ah_procPhyErr |= HAL_PROCESS_ANI; 813 ah->proc_phyerr |= HAL_PROCESS_ANI;
814} 814}
815 815
816void ath9k_hw_ani_detach(struct ath_hw *ah) 816void ath9k_hw_ani_detach(struct ath_hw *ah)
817{ 817{
818 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n"); 818 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n");
819 819
820 if (ah->ah_hasHwPhyCounters) { 820 if (ah->has_hw_phycounters) {
821 ath9k_hw_disable_mib_counters(ah); 821 ath9k_hw_disable_mib_counters(ah);
822 REG_WRITE(ah, AR_PHY_ERR_1, 0); 822 REG_WRITE(ah, AR_PHY_ERR_1, 0);
823 REG_WRITE(ah, AR_PHY_ERR_2, 0); 823 REG_WRITE(ah, AR_PHY_ERR_2, 0);
diff --git a/drivers/net/wireless/ath9k/ani.h b/drivers/net/wireless/ath9k/ani.h
index 7e9ca9519799..7315761f6d74 100644
--- a/drivers/net/wireless/ath9k/ani.h
+++ b/drivers/net/wireless/ath9k/ani.h
@@ -20,12 +20,12 @@
20#define HAL_PROCESS_ANI 0x00000001 20#define HAL_PROCESS_ANI 0x00000001
21#define ATH9K_RSSI_EP_MULTIPLIER (1<<7) 21#define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
22 22
23#define DO_ANI(ah) (((ah)->ah_procPhyErr & HAL_PROCESS_ANI)) 23#define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI))
24 24
25#define HAL_EP_RND(x, mul) \ 25#define HAL_EP_RND(x, mul) \
26 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 26 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
27#define BEACON_RSSI(ahp) \ 27#define BEACON_RSSI(ahp) \
28 HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \ 28 HAL_EP_RND(ahp->stats.ast_nodestats.ns_avgbrssi, \
29 ATH9K_RSSI_EP_MULTIPLIER) 29 ATH9K_RSSI_EP_MULTIPLIER)
30 30
31#define ATH9K_ANI_OFDM_TRIG_HIGH 500 31#define ATH9K_ANI_OFDM_TRIG_HIGH 500
@@ -118,7 +118,7 @@ struct ar5416Stats {
118 struct ath9k_mib_stats ast_mibstats; 118 struct ath9k_mib_stats ast_mibstats;
119 struct ath9k_node_stats ast_nodestats; 119 struct ath9k_node_stats ast_nodestats;
120}; 120};
121#define ah_mibStats ah_stats.ast_mibstats 121#define ah_mibStats stats.ast_mibstats
122 122
123void ath9k_ani_reset(struct ath_hw *ah); 123void ath9k_ani_reset(struct ath_hw *ah);
124void ath9k_hw_ani_monitor(struct ath_hw *ah, 124void ath9k_hw_ani_monitor(struct ath_hw *ah,
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index 91140b7214b1..0b0f82c83ffc 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -670,8 +670,8 @@ static inline void ath_ahb_exit(void) {};
670static inline void ath9k_ps_wakeup(struct ath_softc *sc) 670static inline void ath9k_ps_wakeup(struct ath_softc *sc)
671{ 671{
672 if (atomic_inc_return(&sc->ps_usecount) == 1) 672 if (atomic_inc_return(&sc->ps_usecount) == 1)
673 if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) { 673 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) {
674 sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode; 674 sc->sc_ah->restore_mode = sc->sc_ah->power_mode;
675 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 675 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
676 } 676 }
677} 677}
@@ -681,6 +681,6 @@ static inline void ath9k_ps_restore(struct ath_softc *sc)
681 if (atomic_dec_and_test(&sc->ps_usecount)) 681 if (atomic_dec_and_test(&sc->ps_usecount))
682 if (sc->hw->conf.flags & IEEE80211_CONF_PS) 682 if (sc->hw->conf.flags & IEEE80211_CONF_PS)
683 ath9k_hw_setpower(sc->sc_ah, 683 ath9k_hw_setpower(sc->sc_ah,
684 sc->sc_ah->ah_restore_mode); 684 sc->sc_ah->restore_mode);
685} 685}
686#endif /* ATH9K_H */ 686#endif /* ATH9K_H */
diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c
index 19ec4e8791b4..2e2ef3529135 100644
--- a/drivers/net/wireless/ath9k/beacon.c
+++ b/drivers/net/wireless/ath9k/beacon.c
@@ -27,7 +27,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
27 struct ath9k_tx_queue_info qi; 27 struct ath9k_tx_queue_info qi;
28 28
29 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); 29 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
30 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { 30 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
31 /* Always burst out beacon and CAB traffic. */ 31 /* Always burst out beacon and CAB traffic. */
32 qi.tqi_aifs = 1; 32 qi.tqi_aifs = 1;
33 qi.tqi_cwmin = 0; 33 qi.tqi_cwmin = 0;
@@ -82,8 +82,8 @@ static void ath_beacon_setup(struct ath_softc *sc,
82 82
83 flags = ATH9K_TXDESC_NOACK; 83 flags = ATH9K_TXDESC_NOACK;
84 84
85 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC && 85 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC &&
86 (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { 86 (ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
87 ds->ds_link = bf->bf_daddr; /* self-linked */ 87 ds->ds_link = bf->bf_daddr; /* self-linked */
88 flags |= ATH9K_TXDESC_VEOL; 88 flags |= ATH9K_TXDESC_VEOL;
89 /* Let hardware handle antenna switching. */ 89 /* Let hardware handle antenna switching. */
@@ -310,8 +310,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
310 struct ath_buf, list); 310 struct ath_buf, list);
311 list_del(&avp->av_bcbuf->list); 311 list_del(&avp->av_bcbuf->list);
312 312
313 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || 313 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
314 !(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { 314 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
315 int slot; 315 int slot;
316 /* 316 /*
317 * Assign the vif to a beacon xmit slot. As 317 * Assign the vif to a beacon xmit slot. As
@@ -631,7 +631,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
631 avp = (void *)vif->drv_priv; 631 avp = (void *)vif->drv_priv;
632 opmode = avp->av_opmode; 632 opmode = avp->av_opmode;
633 } else { 633 } else {
634 opmode = sc->sc_ah->ah_opmode; 634 opmode = sc->sc_ah->opmode;
635 } 635 }
636 636
637 memset(&conf, 0, sizeof(struct ath_beacon_config)); 637 memset(&conf, 0, sizeof(struct ath_beacon_config));
@@ -647,7 +647,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
647 nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp); 647 nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp);
648 648
649 /* XXX conditionalize multi-bss support? */ 649 /* XXX conditionalize multi-bss support? */
650 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { 650 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
651 /* 651 /*
652 * For multi-bss ap support beacons are either staggered 652 * For multi-bss ap support beacons are either staggered
653 * evenly over N slots or burst together. For the former 653 * evenly over N slots or burst together. For the former
@@ -670,7 +670,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
670 nexttbtt, intval, conf.beacon_interval); 670 nexttbtt, intval, conf.beacon_interval);
671 671
672 /* Check for NL80211_IFTYPE_AP and sc_nostabeacons for WDS client */ 672 /* Check for NL80211_IFTYPE_AP and sc_nostabeacons for WDS client */
673 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) { 673 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
674 struct ath9k_beacon_state bs; 674 struct ath9k_beacon_state bs;
675 u64 tsf; 675 u64 tsf;
676 u32 tsftu; 676 u32 tsftu;
@@ -789,7 +789,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
789 ath9k_hw_set_interrupts(ah, 0); 789 ath9k_hw_set_interrupts(ah, 0);
790 if (nexttbtt == intval) 790 if (nexttbtt == intval)
791 intval |= ATH9K_BEACON_RESET_TSF; 791 intval |= ATH9K_BEACON_RESET_TSF;
792 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { 792 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
793 /* 793 /*
794 * Pull nexttbtt forward to reflect the current 794 * Pull nexttbtt forward to reflect the current
795 * TSF 795 * TSF
@@ -818,10 +818,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
818 * deal with things. 818 * deal with things.
819 */ 819 */
820 intval |= ATH9K_BEACON_ENA; 820 intval |= ATH9K_BEACON_ENA;
821 if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) 821 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_VEOL))
822 sc->imask |= ATH9K_INT_SWBA; 822 sc->imask |= ATH9K_INT_SWBA;
823 ath_beaconq_config(sc); 823 ath_beaconq_config(sc);
824 } else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { 824 } else if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
825 /* 825 /*
826 * In AP mode we enable the beacon timers and 826 * In AP mode we enable the beacon timers and
827 * SWBA interrupts to prepare beacon frames. 827 * SWBA interrupts to prepare beacon frames.
@@ -837,8 +837,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
837 * When using a self-linked beacon descriptor in 837 * When using a self-linked beacon descriptor in
838 * ibss mode load it once here. 838 * ibss mode load it once here.
839 */ 839 */
840 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC && 840 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC &&
841 (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) 841 (ah->caps.hw_caps & ATH9K_HW_CAP_VEOL))
842 ath_beacon_start_adhoc(sc, 0); 842 ath_beacon_start_adhoc(sc, 0);
843 } 843 }
844} 844}
diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c
index 7e70a81e21de..1fc3a08e85c6 100644
--- a/drivers/net/wireless/ath9k/calib.c
+++ b/drivers/net/wireless/ath9k/calib.c
@@ -229,13 +229,13 @@ static void ath9k_hw_reset_calibration(struct ath_hw *ah,
229 currCal->calState = CAL_RUNNING; 229 currCal->calState = CAL_RUNNING;
230 230
231 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 231 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
232 ah->ah_Meas0.sign[i] = 0; 232 ah->meas0.sign[i] = 0;
233 ah->ah_Meas1.sign[i] = 0; 233 ah->meas1.sign[i] = 0;
234 ah->ah_Meas2.sign[i] = 0; 234 ah->meas2.sign[i] = 0;
235 ah->ah_Meas3.sign[i] = 0; 235 ah->meas3.sign[i] = 0;
236 } 236 }
237 237
238 ah->ah_CalSamples = 0; 238 ah->cal_samples = 0;
239} 239}
240 240
241static void ath9k_hw_per_calibration(struct ath_hw *ah, 241static void ath9k_hw_per_calibration(struct ath_hw *ah,
@@ -251,9 +251,9 @@ static void ath9k_hw_per_calibration(struct ath_hw *ah,
251 AR_PHY_TIMING_CTRL4_DO_CAL)) { 251 AR_PHY_TIMING_CTRL4_DO_CAL)) {
252 252
253 currCal->calData->calCollect(ah); 253 currCal->calData->calCollect(ah);
254 ah->ah_CalSamples++; 254 ah->cal_samples++;
255 255
256 if (ah->ah_CalSamples >= currCal->calData->calNumSamples) { 256 if (ah->cal_samples >= currCal->calData->calNumSamples) {
257 int i, numChains = 0; 257 int i, numChains = 0;
258 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 258 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
259 if (rxchainmask & (1 << i)) 259 if (rxchainmask & (1 << i))
@@ -279,7 +279,7 @@ static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
279{ 279{
280 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 280 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
281 281
282 switch (calType & ah->ah_suppCals) { 282 switch (calType & ah->supp_cals) {
283 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ 283 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
284 return true; 284 return true;
285 case ADC_GAIN_CAL: 285 case ADC_GAIN_CAL:
@@ -297,17 +297,17 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
297 int i; 297 int i;
298 298
299 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 299 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
300 ah->ah_totalPowerMeasI[i] += 300 ah->totalPowerMeasI[i] +=
301 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 301 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
302 ah->ah_totalPowerMeasQ[i] += 302 ah->totalPowerMeasQ[i] +=
303 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 303 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
304 ah->ah_totalIqCorrMeas[i] += 304 ah->totalIqCorrMeas[i] +=
305 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 305 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
306 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 306 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
307 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", 307 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
308 ah->ah_CalSamples, i, ah->ah_totalPowerMeasI[i], 308 ah->cal_samples, i, ah->totalPowerMeasI[i],
309 ah->ah_totalPowerMeasQ[i], 309 ah->totalPowerMeasQ[i],
310 ah->ah_totalIqCorrMeas[i]); 310 ah->totalIqCorrMeas[i]);
311 } 311 }
312} 312}
313 313
@@ -316,23 +316,23 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
316 int i; 316 int i;
317 317
318 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 318 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
319 ah->ah_totalAdcIOddPhase[i] += 319 ah->totalAdcIOddPhase[i] +=
320 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 320 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
321 ah->ah_totalAdcIEvenPhase[i] += 321 ah->totalAdcIEvenPhase[i] +=
322 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 322 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
323 ah->ah_totalAdcQOddPhase[i] += 323 ah->totalAdcQOddPhase[i] +=
324 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 324 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
325 ah->ah_totalAdcQEvenPhase[i] += 325 ah->totalAdcQEvenPhase[i] +=
326 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 326 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
327 327
328 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 328 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
329 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 329 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
330 "oddq=0x%08x; evenq=0x%08x;\n", 330 "oddq=0x%08x; evenq=0x%08x;\n",
331 ah->ah_CalSamples, i, 331 ah->cal_samples, i,
332 ah->ah_totalAdcIOddPhase[i], 332 ah->totalAdcIOddPhase[i],
333 ah->ah_totalAdcIEvenPhase[i], 333 ah->totalAdcIEvenPhase[i],
334 ah->ah_totalAdcQOddPhase[i], 334 ah->totalAdcQOddPhase[i],
335 ah->ah_totalAdcQEvenPhase[i]); 335 ah->totalAdcQEvenPhase[i]);
336 } 336 }
337} 337}
338 338
@@ -341,23 +341,23 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
341 int i; 341 int i;
342 342
343 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 343 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
344 ah->ah_totalAdcDcOffsetIOddPhase[i] += 344 ah->totalAdcDcOffsetIOddPhase[i] +=
345 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 345 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
346 ah->ah_totalAdcDcOffsetIEvenPhase[i] += 346 ah->totalAdcDcOffsetIEvenPhase[i] +=
347 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 347 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
348 ah->ah_totalAdcDcOffsetQOddPhase[i] += 348 ah->totalAdcDcOffsetQOddPhase[i] +=
349 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 349 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
350 ah->ah_totalAdcDcOffsetQEvenPhase[i] += 350 ah->totalAdcDcOffsetQEvenPhase[i] +=
351 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 351 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
352 352
353 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 353 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
354 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 354 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
355 "oddq=0x%08x; evenq=0x%08x;\n", 355 "oddq=0x%08x; evenq=0x%08x;\n",
356 ah->ah_CalSamples, i, 356 ah->cal_samples, i,
357 ah->ah_totalAdcDcOffsetIOddPhase[i], 357 ah->totalAdcDcOffsetIOddPhase[i],
358 ah->ah_totalAdcDcOffsetIEvenPhase[i], 358 ah->totalAdcDcOffsetIEvenPhase[i],
359 ah->ah_totalAdcDcOffsetQOddPhase[i], 359 ah->totalAdcDcOffsetQOddPhase[i],
360 ah->ah_totalAdcDcOffsetQEvenPhase[i]); 360 ah->totalAdcDcOffsetQEvenPhase[i]);
361 } 361 }
362} 362}
363 363
@@ -369,9 +369,9 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
369 int iqCorrNeg, i; 369 int iqCorrNeg, i;
370 370
371 for (i = 0; i < numChains; i++) { 371 for (i = 0; i < numChains; i++) {
372 powerMeasI = ah->ah_totalPowerMeasI[i]; 372 powerMeasI = ah->totalPowerMeasI[i];
373 powerMeasQ = ah->ah_totalPowerMeasQ[i]; 373 powerMeasQ = ah->totalPowerMeasQ[i];
374 iqCorrMeas = ah->ah_totalIqCorrMeas[i]; 374 iqCorrMeas = ah->totalIqCorrMeas[i];
375 375
376 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 376 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
377 "Starting IQ Cal and Correction for Chain %d\n", 377 "Starting IQ Cal and Correction for Chain %d\n",
@@ -379,7 +379,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
379 379
380 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 380 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
381 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 381 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
382 i, ah->ah_totalIqCorrMeas[i]); 382 i, ah->totalIqCorrMeas[i]);
383 383
384 iqCorrNeg = 0; 384 iqCorrNeg = 0;
385 385
@@ -443,10 +443,10 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
443 u32 qGainMismatch, iGainMismatch, val, i; 443 u32 qGainMismatch, iGainMismatch, val, i;
444 444
445 for (i = 0; i < numChains; i++) { 445 for (i = 0; i < numChains; i++) {
446 iOddMeasOffset = ah->ah_totalAdcIOddPhase[i]; 446 iOddMeasOffset = ah->totalAdcIOddPhase[i];
447 iEvenMeasOffset = ah->ah_totalAdcIEvenPhase[i]; 447 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
448 qOddMeasOffset = ah->ah_totalAdcQOddPhase[i]; 448 qOddMeasOffset = ah->totalAdcQOddPhase[i];
449 qEvenMeasOffset = ah->ah_totalAdcQEvenPhase[i]; 449 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
450 450
451 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 451 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
452 "Starting ADC Gain Cal for Chain %d\n", i); 452 "Starting ADC Gain Cal for Chain %d\n", i);
@@ -499,15 +499,15 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
499 u32 iOddMeasOffset, iEvenMeasOffset, val, i; 499 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
500 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; 500 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
501 const struct hal_percal_data *calData = 501 const struct hal_percal_data *calData =
502 ah->ah_cal_list_curr->calData; 502 ah->cal_list_curr->calData;
503 u32 numSamples = 503 u32 numSamples =
504 (1 << (calData->calCountMax + 5)) * calData->calNumSamples; 504 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
505 505
506 for (i = 0; i < numChains; i++) { 506 for (i = 0; i < numChains; i++) {
507 iOddMeasOffset = ah->ah_totalAdcDcOffsetIOddPhase[i]; 507 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
508 iEvenMeasOffset = ah->ah_totalAdcDcOffsetIEvenPhase[i]; 508 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
509 qOddMeasOffset = ah->ah_totalAdcDcOffsetQOddPhase[i]; 509 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
510 qEvenMeasOffset = ah->ah_totalAdcDcOffsetQEvenPhase[i]; 510 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
511 511
512 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 512 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
513 "Starting ADC DC Offset Cal for Chain %d\n", i); 513 "Starting ADC DC Offset Cal for Chain %d\n", i);
@@ -555,9 +555,9 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
555bool ath9k_hw_reset_calvalid(struct ath_hw *ah) 555bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
556{ 556{
557 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 557 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
558 struct hal_cal_list *currCal = ah->ah_cal_list_curr; 558 struct hal_cal_list *currCal = ah->cal_list_curr;
559 559
560 if (!ah->ah_curchan) 560 if (!ah->curchan)
561 return true; 561 return true;
562 562
563 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah)) 563 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
@@ -580,7 +580,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
580 "Resetting Cal %d state for channel %u\n", 580 "Resetting Cal %d state for channel %u\n",
581 currCal->calData->calType, conf->channel->center_freq); 581 currCal->calData->calType, conf->channel->center_freq);
582 582
583 ah->ah_curchan->CalValid &= ~currCal->calData->calType; 583 ah->curchan->CalValid &= ~currCal->calData->calType;
584 currCal->calState = CAL_WAITING; 584 currCal->calState = CAL_WAITING;
585 585
586 return false; 586 return false;
@@ -722,7 +722,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
722 u8 rxchainmask, bool longcal, 722 u8 rxchainmask, bool longcal,
723 bool *isCalDone) 723 bool *isCalDone)
724{ 724{
725 struct hal_cal_list *currCal = ah->ah_cal_list_curr; 725 struct hal_cal_list *currCal = ah->cal_list_curr;
726 726
727 *isCalDone = true; 727 *isCalDone = true;
728 728
@@ -732,7 +732,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
732 ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, 732 ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
733 isCalDone); 733 isCalDone);
734 if (*isCalDone) { 734 if (*isCalDone) {
735 ah->ah_cal_list_curr = currCal = currCal->calNext; 735 ah->cal_list_curr = currCal = currCal->calNext;
736 736
737 if (currCal->calState == CAL_WAITING) { 737 if (currCal->calState == CAL_WAITING) {
738 *isCalDone = false; 738 *isCalDone = false;
@@ -743,7 +743,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
743 743
744 if (longcal) { 744 if (longcal) {
745 ath9k_hw_getnf(ah, chan); 745 ath9k_hw_getnf(ah, chan);
746 ath9k_hw_loadnf(ah, ah->ah_curchan); 746 ath9k_hw_loadnf(ah, ah->curchan);
747 ath9k_hw_start_nfcal(ah); 747 ath9k_hw_start_nfcal(ah);
748 748
749 if (chan->channelFlags & CHANNEL_CW_INT) 749 if (chan->channelFlags & CHANNEL_CW_INT)
@@ -869,32 +869,32 @@ bool ath9k_hw_init_cal(struct ath_hw *ah,
869 REG_READ(ah, AR_PHY_AGC_CONTROL) | 869 REG_READ(ah, AR_PHY_AGC_CONTROL) |
870 AR_PHY_AGC_CONTROL_NF); 870 AR_PHY_AGC_CONTROL_NF);
871 871
872 ah->ah_cal_list = ah->ah_cal_list_last = ah->ah_cal_list_curr = NULL; 872 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
873 873
874 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { 874 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
875 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { 875 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
876 INIT_CAL(&ah->ah_adcGainCalData); 876 INIT_CAL(&ah->adcgain_caldata);
877 INSERT_CAL(ah, &ah->ah_adcGainCalData); 877 INSERT_CAL(ah, &ah->adcgain_caldata);
878 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 878 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
879 "enabling ADC Gain Calibration.\n"); 879 "enabling ADC Gain Calibration.\n");
880 } 880 }
881 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { 881 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
882 INIT_CAL(&ah->ah_adcDcCalData); 882 INIT_CAL(&ah->adcdc_caldata);
883 INSERT_CAL(ah, &ah->ah_adcDcCalData); 883 INSERT_CAL(ah, &ah->adcdc_caldata);
884 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 884 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
885 "enabling ADC DC Calibration.\n"); 885 "enabling ADC DC Calibration.\n");
886 } 886 }
887 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { 887 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
888 INIT_CAL(&ah->ah_iqCalData); 888 INIT_CAL(&ah->iq_caldata);
889 INSERT_CAL(ah, &ah->ah_iqCalData); 889 INSERT_CAL(ah, &ah->iq_caldata);
890 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 890 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
891 "enabling IQ Calibration.\n"); 891 "enabling IQ Calibration.\n");
892 } 892 }
893 893
894 ah->ah_cal_list_curr = ah->ah_cal_list; 894 ah->cal_list_curr = ah->cal_list;
895 895
896 if (ah->ah_cal_list_curr) 896 if (ah->cal_list_curr)
897 ath9k_hw_reset_calibration(ah, ah->ah_cal_list_curr); 897 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
898 } 898 }
899 899
900 chan->CalValid = 0; 900 chan->CalValid = 0;
diff --git a/drivers/net/wireless/ath9k/calib.h b/drivers/net/wireless/ath9k/calib.h
index e2c614098545..d2448f049c1d 100644
--- a/drivers/net/wireless/ath9k/calib.h
+++ b/drivers/net/wireless/ath9k/calib.h
@@ -56,14 +56,14 @@ struct ar5416IniArray {
56 56
57#define INSERT_CAL(_ahp, _perCal) \ 57#define INSERT_CAL(_ahp, _perCal) \
58 do { \ 58 do { \
59 if ((_ahp)->ah_cal_list_last == NULL) { \ 59 if ((_ahp)->cal_list_last == NULL) { \
60 (_ahp)->ah_cal_list = \ 60 (_ahp)->cal_list = \
61 (_ahp)->ah_cal_list_last = (_perCal); \ 61 (_ahp)->cal_list_last = (_perCal); \
62 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ 62 ((_ahp)->cal_list_last)->calNext = (_perCal); \
63 } else { \ 63 } else { \
64 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ 64 ((_ahp)->cal_list_last)->calNext = (_perCal); \
65 (_ahp)->ah_cal_list_last = (_perCal); \ 65 (_ahp)->cal_list_last = (_perCal); \
66 (_perCal)->calNext = (_ahp)->ah_cal_list; \ 66 (_perCal)->calNext = (_ahp)->cal_list; \
67 } \ 67 } \
68 } while (0) 68 } while (0)
69 69
diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c
index 2e604e1fb3e1..c0359ad2bc7b 100644
--- a/drivers/net/wireless/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath9k/eeprom.c
@@ -27,7 +27,7 @@ static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah,
27 27
28 REG_WRITE(ah, reg, regVal); 28 REG_WRITE(ah, reg, regVal);
29 29
30 if (ah->ah_config.analog_shiftreg) 30 if (ah->config.analog_shiftreg)
31 udelay(100); 31 udelay(100);
32 32
33 return; 33 return;
@@ -268,18 +268,18 @@ static u16 ath9k_hw_get_max_edge_power(u16 freq,
268 268
269static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) 269static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
270{ 270{
271 return ((ah->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF); 271 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
272} 272}
273 273
274static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah) 274static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
275{ 275{
276 return ((ah->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF); 276 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
277} 277}
278 278
279static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) 279static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
280{ 280{
281#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 281#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
282 struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; 282 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
283 u16 *eep_data; 283 u16 *eep_data;
284 int addr, eep_start_loc = 0; 284 int addr, eep_start_loc = 0;
285 285
@@ -308,7 +308,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
308{ 308{
309#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 309#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
310 struct ar5416_eeprom_4k *eep = 310 struct ar5416_eeprom_4k *eep =
311 (struct ar5416_eeprom_4k *) &ah->ah_eeprom.map4k; 311 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
312 u16 *eepdata, temp, magic, magic2; 312 u16 *eepdata, temp, magic, magic2;
313 u32 sum = 0, el; 313 u32 sum = 0, el;
314 bool need_swap = false; 314 bool need_swap = false;
@@ -332,7 +332,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
332 332
333 if (magic2 == AR5416_EEPROM_MAGIC) { 333 if (magic2 == AR5416_EEPROM_MAGIC) {
334 need_swap = true; 334 need_swap = true;
335 eepdata = (u16 *) (&ah->ah_eeprom); 335 eepdata = (u16 *) (&ah->eeprom);
336 336
337 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { 337 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
338 temp = swab16(*eepdata); 338 temp = swab16(*eepdata);
@@ -359,16 +359,16 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
359 need_swap ? "True" : "False"); 359 need_swap ? "True" : "False");
360 360
361 if (need_swap) 361 if (need_swap)
362 el = swab16(ah->ah_eeprom.map4k.baseEepHeader.length); 362 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
363 else 363 else
364 el = ah->ah_eeprom.map4k.baseEepHeader.length; 364 el = ah->eeprom.map4k.baseEepHeader.length;
365 365
366 if (el > sizeof(struct ar5416_eeprom_def)) 366 if (el > sizeof(struct ar5416_eeprom_def))
367 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); 367 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
368 else 368 else
369 el = el / sizeof(u16); 369 el = el / sizeof(u16);
370 370
371 eepdata = (u16 *)(&ah->ah_eeprom); 371 eepdata = (u16 *)(&ah->eeprom);
372 372
373 for (i = 0; i < el; i++) 373 for (i = 0; i < el; i++)
374 sum ^= *eepdata++; 374 sum ^= *eepdata++;
@@ -433,7 +433,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
433static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, 433static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
434 enum eeprom_param param) 434 enum eeprom_param param)
435{ 435{
436 struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; 436 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
437 struct modal_eep_4k_header *pModal = &eep->modalHeader; 437 struct modal_eep_4k_header *pModal = &eep->modalHeader;
438 struct base_eep_header_4k *pBase = &eep->baseEepHeader; 438 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
439 439
@@ -643,7 +643,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
643 struct ath9k_channel *chan, 643 struct ath9k_channel *chan,
644 int16_t *pTxPowerIndexOffset) 644 int16_t *pTxPowerIndexOffset)
645{ 645{
646 struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; 646 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
647 struct cal_data_per_freq_4k *pRawDataset; 647 struct cal_data_per_freq_4k *pRawDataset;
648 u8 *pCalBChans = NULL; 648 u8 *pCalBChans = NULL;
649 u16 pdGainOverlap_t2; 649 u16 pdGainOverlap_t2;
@@ -692,7 +692,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
692 692
693 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 693 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
694 if (AR_SREV_5416_V20_OR_LATER(ah) && 694 if (AR_SREV_5416_V20_OR_LATER(ah) &&
695 (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && 695 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
696 (i != 0)) { 696 (i != 0)) {
697 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 697 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
698 } else 698 } else
@@ -763,7 +763,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
763 u16 twiceMaxRegulatoryPower, 763 u16 twiceMaxRegulatoryPower,
764 u16 powerLimit) 764 u16 powerLimit)
765{ 765{
766 struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; 766 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
767 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 767 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
768 static const u16 tpScaleReductionTable[5] = 768 static const u16 tpScaleReductionTable[5] =
769 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 769 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
@@ -791,7 +791,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
791 int tx_chainmask; 791 int tx_chainmask;
792 u16 twiceMinEdgePower; 792 u16 twiceMinEdgePower;
793 793
794 tx_chainmask = ah->ah_txchainmask; 794 tx_chainmask = ah->txchainmask;
795 795
796 ath9k_hw_get_channel_centers(ah, chan, &centers); 796 ath9k_hw_get_channel_centers(ah, chan, &centers);
797 797
@@ -997,7 +997,7 @@ static int ath9k_hw_4k_set_txpower(struct ath_hw *ah,
997 u8 twiceMaxRegulatoryPower, 997 u8 twiceMaxRegulatoryPower,
998 u8 powerLimit) 998 u8 powerLimit)
999{ 999{
1000 struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; 1000 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
1001 struct modal_eep_4k_header *pModal = &pEepData->modalHeader; 1001 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
1002 int16_t ratesArray[Ar5416RateSize]; 1002 int16_t ratesArray[Ar5416RateSize];
1003 int16_t txPowerIndexOffset = 0; 1003 int16_t txPowerIndexOffset = 0;
@@ -1121,7 +1121,7 @@ static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1121 struct ath9k_channel *chan) 1121 struct ath9k_channel *chan)
1122{ 1122{
1123 struct modal_eep_4k_header *pModal; 1123 struct modal_eep_4k_header *pModal;
1124 struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; 1124 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1125 u8 biaslevel; 1125 u8 biaslevel;
1126 1126
1127 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) 1127 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
@@ -1134,8 +1134,8 @@ static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1134 1134
1135 if (pModal->xpaBiasLvl != 0xff) { 1135 if (pModal->xpaBiasLvl != 0xff) {
1136 biaslevel = pModal->xpaBiasLvl; 1136 biaslevel = pModal->xpaBiasLvl;
1137 INI_RA(&ah->ah_iniAddac, 7, 1) = 1137 INI_RA(&ah->iniAddac, 7, 1) =
1138 (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; 1138 (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
1139 } 1139 }
1140} 1140}
1141 1141
@@ -1143,7 +1143,7 @@ static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1143 struct ath9k_channel *chan) 1143 struct ath9k_channel *chan)
1144{ 1144{
1145 struct modal_eep_4k_header *pModal; 1145 struct modal_eep_4k_header *pModal;
1146 struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; 1146 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1147 int regChainOffset; 1147 int regChainOffset;
1148 u8 txRxAttenLocal; 1148 u8 txRxAttenLocal;
1149 u8 ob[5], db1[5], db2[5]; 1149 u8 ob[5], db1[5], db2[5];
@@ -1328,7 +1328,7 @@ static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1328static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah, 1328static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1329 struct ath9k_channel *chan) 1329 struct ath9k_channel *chan)
1330{ 1330{
1331 struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; 1331 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1332 struct modal_eep_4k_header *pModal = &eep->modalHeader; 1332 struct modal_eep_4k_header *pModal = &eep->modalHeader;
1333 1333
1334 return pModal->antCtrlCommon & 0xFFFF; 1334 return pModal->antCtrlCommon & 0xFFFF;
@@ -1343,19 +1343,19 @@ static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1343u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) 1343u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1344{ 1344{
1345#define EEP_MAP4K_SPURCHAN \ 1345#define EEP_MAP4K_SPURCHAN \
1346 (ah->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) 1346 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1347 1347
1348 u16 spur_val = AR_NO_SPUR; 1348 u16 spur_val = AR_NO_SPUR;
1349 1349
1350 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1350 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1351 "Getting spur idx %d is2Ghz. %d val %x\n", 1351 "Getting spur idx %d is2Ghz. %d val %x\n",
1352 i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); 1352 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1353 1353
1354 switch (ah->ah_config.spurmode) { 1354 switch (ah->config.spurmode) {
1355 case SPUR_DISABLE: 1355 case SPUR_DISABLE:
1356 break; 1356 break;
1357 case SPUR_ENABLE_IOCTL: 1357 case SPUR_ENABLE_IOCTL:
1358 spur_val = ah->ah_config.spurchans[i][is2GHz]; 1358 spur_val = ah->config.spurchans[i][is2GHz];
1359 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1359 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1360 "Getting spur val from new loc. %d\n", spur_val); 1360 "Getting spur val from new loc. %d\n", spur_val);
1361 break; 1361 break;
@@ -1389,18 +1389,18 @@ struct eeprom_ops eep_4k_ops = {
1389 1389
1390static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah) 1390static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
1391{ 1391{
1392 return ((ah->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF); 1392 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
1393} 1393}
1394 1394
1395static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah) 1395static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
1396{ 1396{
1397 return ((ah->ah_eeprom.def.baseEepHeader.version) & 0xFFF); 1397 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
1398} 1398}
1399 1399
1400static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) 1400static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
1401{ 1401{
1402#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) 1402#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
1403 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; 1403 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1404 u16 *eep_data; 1404 u16 *eep_data;
1405 int addr, ar5416_eep_start_loc = 0x100; 1405 int addr, ar5416_eep_start_loc = 0x100;
1406 1406
@@ -1422,7 +1422,7 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
1422static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) 1422static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1423{ 1423{
1424 struct ar5416_eeprom_def *eep = 1424 struct ar5416_eeprom_def *eep =
1425 (struct ar5416_eeprom_def *) &ah->ah_eeprom.def; 1425 (struct ar5416_eeprom_def *) &ah->eeprom.def;
1426 u16 *eepdata, temp, magic, magic2; 1426 u16 *eepdata, temp, magic, magic2;
1427 u32 sum = 0, el; 1427 u32 sum = 0, el;
1428 bool need_swap = false; 1428 bool need_swap = false;
@@ -1446,7 +1446,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1446 if (magic2 == AR5416_EEPROM_MAGIC) { 1446 if (magic2 == AR5416_EEPROM_MAGIC) {
1447 size = sizeof(struct ar5416_eeprom_def); 1447 size = sizeof(struct ar5416_eeprom_def);
1448 need_swap = true; 1448 need_swap = true;
1449 eepdata = (u16 *) (&ah->ah_eeprom); 1449 eepdata = (u16 *) (&ah->eeprom);
1450 1450
1451 for (addr = 0; addr < size / sizeof(u16); addr++) { 1451 for (addr = 0; addr < size / sizeof(u16); addr++) {
1452 temp = swab16(*eepdata); 1452 temp = swab16(*eepdata);
@@ -1473,16 +1473,16 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1473 need_swap ? "True" : "False"); 1473 need_swap ? "True" : "False");
1474 1474
1475 if (need_swap) 1475 if (need_swap)
1476 el = swab16(ah->ah_eeprom.def.baseEepHeader.length); 1476 el = swab16(ah->eeprom.def.baseEepHeader.length);
1477 else 1477 else
1478 el = ah->ah_eeprom.def.baseEepHeader.length; 1478 el = ah->eeprom.def.baseEepHeader.length;
1479 1479
1480 if (el > sizeof(struct ar5416_eeprom_def)) 1480 if (el > sizeof(struct ar5416_eeprom_def))
1481 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); 1481 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
1482 else 1482 else
1483 el = el / sizeof(u16); 1483 el = el / sizeof(u16);
1484 1484
1485 eepdata = (u16 *)(&ah->ah_eeprom); 1485 eepdata = (u16 *)(&ah->eeprom);
1486 1486
1487 for (i = 0; i < el; i++) 1487 for (i = 0; i < el; i++)
1488 sum ^= *eepdata++; 1488 sum ^= *eepdata++;
@@ -1551,7 +1551,7 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
1551 enum eeprom_param param) 1551 enum eeprom_param param)
1552{ 1552{
1553#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) 1553#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK)
1554 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; 1554 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1555 struct modal_eep_header *pModal = eep->modalHeader; 1555 struct modal_eep_header *pModal = eep->modalHeader;
1556 struct base_eep_header *pBase = &eep->baseEepHeader; 1556 struct base_eep_header *pBase = &eep->baseEepHeader;
1557 1557
@@ -1611,7 +1611,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1611{ 1611{
1612#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) 1612#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
1613 struct modal_eep_header *pModal; 1613 struct modal_eep_header *pModal;
1614 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; 1614 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1615 int i, regChainOffset; 1615 int i, regChainOffset;
1616 u8 txRxAttenLocal; 1616 u8 txRxAttenLocal;
1617 1617
@@ -1629,7 +1629,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1629 } 1629 }
1630 1630
1631 if (AR_SREV_5416_V20_OR_LATER(ah) && 1631 if (AR_SREV_5416_V20_OR_LATER(ah) &&
1632 (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) 1632 (ah->rxchainmask == 5 || ah->txchainmask == 5)
1633 && (i != 0)) 1633 && (i != 0))
1634 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1634 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1635 else 1635 else
@@ -1855,7 +1855,7 @@ static void ath9k_hw_def_set_addac(struct ath_hw *ah,
1855{ 1855{
1856#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) 1856#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
1857 struct modal_eep_header *pModal; 1857 struct modal_eep_header *pModal;
1858 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; 1858 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1859 u8 biaslevel; 1859 u8 biaslevel;
1860 1860
1861 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) 1861 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
@@ -1895,10 +1895,10 @@ static void ath9k_hw_def_set_addac(struct ath_hw *ah,
1895 } 1895 }
1896 1896
1897 if (IS_CHAN_2GHZ(chan)) { 1897 if (IS_CHAN_2GHZ(chan)) {
1898 INI_RA(&ah->ah_iniAddac, 7, 1) = (INI_RA(&ah->ah_iniAddac, 1898 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
1899 7, 1) & (~0x18)) | biaslevel << 3; 1899 7, 1) & (~0x18)) | biaslevel << 3;
1900 } else { 1900 } else {
1901 INI_RA(&ah->ah_iniAddac, 6, 1) = (INI_RA(&ah->ah_iniAddac, 1901 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
1902 6, 1) & (~0xc0)) | biaslevel << 6; 1902 6, 1) & (~0xc0)) | biaslevel << 6;
1903 } 1903 }
1904#undef XPA_LVL_FREQ 1904#undef XPA_LVL_FREQ
@@ -2073,7 +2073,7 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2073 struct ath9k_channel *chan, 2073 struct ath9k_channel *chan,
2074 int16_t *pTxPowerIndexOffset) 2074 int16_t *pTxPowerIndexOffset)
2075{ 2075{
2076 struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; 2076 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2077 struct cal_data_per_freq *pRawDataset; 2077 struct cal_data_per_freq *pRawDataset;
2078 u8 *pCalBChans = NULL; 2078 u8 *pCalBChans = NULL;
2079 u16 pdGainOverlap_t2; 2079 u16 pdGainOverlap_t2;
@@ -2129,7 +2129,7 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2129 2129
2130 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 2130 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2131 if (AR_SREV_5416_V20_OR_LATER(ah) && 2131 if (AR_SREV_5416_V20_OR_LATER(ah) &&
2132 (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && 2132 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
2133 (i != 0)) { 2133 (i != 0)) {
2134 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 2134 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2135 } else 2135 } else
@@ -2206,7 +2206,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2206#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ 2206#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
2207#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ 2207#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
2208 2208
2209 struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; 2209 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2210 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 2210 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2211 static const u16 tpScaleReductionTable[5] = 2211 static const u16 tpScaleReductionTable[5] =
2212 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 2212 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
@@ -2236,7 +2236,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2236 int tx_chainmask; 2236 int tx_chainmask;
2237 u16 twiceMinEdgePower; 2237 u16 twiceMinEdgePower;
2238 2238
2239 tx_chainmask = ah->ah_txchainmask; 2239 tx_chainmask = ah->txchainmask;
2240 2240
2241 ath9k_hw_get_channel_centers(ah, chan, &centers); 2241 ath9k_hw_get_channel_centers(ah, chan, &centers);
2242 2242
@@ -2493,7 +2493,7 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
2493 u8 twiceMaxRegulatoryPower, 2493 u8 twiceMaxRegulatoryPower,
2494 u8 powerLimit) 2494 u8 powerLimit)
2495{ 2495{
2496 struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; 2496 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2497 struct modal_eep_header *pModal = 2497 struct modal_eep_header *pModal =
2498 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); 2498 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
2499 int16_t ratesArray[Ar5416RateSize]; 2499 int16_t ratesArray[Ar5416RateSize];
@@ -2621,7 +2621,7 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
2621static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah, 2621static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
2622 enum ieee80211_band freq_band) 2622 enum ieee80211_band freq_band)
2623{ 2623{
2624 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; 2624 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2625 struct modal_eep_header *pModal = 2625 struct modal_eep_header *pModal =
2626 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]); 2626 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
2627 struct base_eep_header *pBase = &eep->baseEepHeader; 2627 struct base_eep_header *pBase = &eep->baseEepHeader;
@@ -2639,7 +2639,7 @@ static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
2639static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah, 2639static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
2640 struct ath9k_channel *chan) 2640 struct ath9k_channel *chan)
2641{ 2641{
2642 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; 2642 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2643 struct modal_eep_header *pModal = 2643 struct modal_eep_header *pModal =
2644 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 2644 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2645 2645
@@ -2649,19 +2649,19 @@ static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
2649u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) 2649u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
2650{ 2650{
2651#define EEP_DEF_SPURCHAN \ 2651#define EEP_DEF_SPURCHAN \
2652 (ah->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) 2652 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
2653 2653
2654 u16 spur_val = AR_NO_SPUR; 2654 u16 spur_val = AR_NO_SPUR;
2655 2655
2656 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 2656 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2657 "Getting spur idx %d is2Ghz. %d val %x\n", 2657 "Getting spur idx %d is2Ghz. %d val %x\n",
2658 i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); 2658 i, is2GHz, ah->config.spurchans[i][is2GHz]);
2659 2659
2660 switch (ah->ah_config.spurmode) { 2660 switch (ah->config.spurmode) {
2661 case SPUR_DISABLE: 2661 case SPUR_DISABLE:
2662 break; 2662 break;
2663 case SPUR_ENABLE_IOCTL: 2663 case SPUR_ENABLE_IOCTL:
2664 spur_val = ah->ah_config.spurchans[i][is2GHz]; 2664 spur_val = ah->config.spurchans[i][is2GHz];
2665 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 2665 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2666 "Getting spur val from new loc. %d\n", spur_val); 2666 "Getting spur val from new loc. %d\n", spur_val);
2667 break; 2667 break;
@@ -2694,10 +2694,10 @@ int ath9k_hw_eeprom_attach(struct ath_hw *ah)
2694 int status; 2694 int status;
2695 2695
2696 if (AR_SREV_9285(ah)) { 2696 if (AR_SREV_9285(ah)) {
2697 ah->ah_eep_map = EEP_MAP_4KBITS; 2697 ah->eep_map = EEP_MAP_4KBITS;
2698 ah->eep_ops = &eep_4k_ops; 2698 ah->eep_ops = &eep_4k_ops;
2699 } else { 2699 } else {
2700 ah->ah_eep_map = EEP_MAP_DEFAULT; 2700 ah->eep_map = EEP_MAP_DEFAULT;
2701 ah->eep_ops = &eep_def_ops; 2701 ah->eep_ops = &eep_def_ops;
2702 } 2702 }
2703 2703
diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h
index 7a4266f29eaa..99863b570441 100644
--- a/drivers/net/wireless/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath9k/eeprom.h
@@ -441,7 +441,7 @@ struct ath9k_country_entry {
441 u8 iso[3]; 441 u8 iso[3];
442}; 442};
443 443
444enum hal_eep_map { 444enum ath9k_eep_map {
445 EEP_MAP_DEFAULT = 0x0, 445 EEP_MAP_DEFAULT = 0x0,
446 EEP_MAP_4KBITS, 446 EEP_MAP_4KBITS,
447 EEP_MAP_MAX 447 EEP_MAP_MAX
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index f744d8cd8307..72ca1c8ff090 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -45,7 +45,7 @@ static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45{ 45{
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47 47
48 if (!ah->ah_curchan) /* should really check for CCK instead */ 48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK; 49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ) 50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM; 51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
@@ -67,7 +67,7 @@ static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67{ 67{
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69 69
70 if (!ah->ah_curchan) /* should really check for CCK instead */ 70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK; 71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ) 72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; 73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
@@ -118,7 +118,7 @@ bool ath9k_get_channel_edges(struct ath_hw *ah,
118 u16 flags, u16 *low, 118 u16 flags, u16 *low,
119 u16 *high) 119 u16 *high)
120{ 120{
121 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 121 struct ath9k_hw_capabilities *pCap = &ah->caps;
122 122
123 if (flags & CHANNEL_5GHZ) { 123 if (flags & CHANNEL_5GHZ) {
124 *low = pCap->low_5ghz_chan; 124 *low = pCap->low_5ghz_chan;
@@ -155,15 +155,15 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
155 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 155 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
156 break; 156 break;
157 case WLAN_RC_PHY_OFDM: 157 case WLAN_RC_PHY_OFDM:
158 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) { 158 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
159 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 159 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
160 numBits = OFDM_PLCP_BITS + (frameLen << 3); 160 numBits = OFDM_PLCP_BITS + (frameLen << 3);
161 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 161 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
162 txTime = OFDM_SIFS_TIME_QUARTER 162 txTime = OFDM_SIFS_TIME_QUARTER
163 + OFDM_PREAMBLE_TIME_QUARTER 163 + OFDM_PREAMBLE_TIME_QUARTER
164 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 164 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
165 } else if (ah->ah_curchan && 165 } else if (ah->curchan &&
166 IS_CHAN_HALF_RATE(ah->ah_curchan)) { 166 IS_CHAN_HALF_RATE(ah->curchan)) {
167 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 167 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
168 numBits = OFDM_PLCP_BITS + (frameLen << 3); 168 numBits = OFDM_PLCP_BITS + (frameLen << 3);
169 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 169 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
@@ -216,7 +216,7 @@ void ath9k_hw_get_channel_centers(struct ath_hw *ah,
216 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 216 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
217 centers->ext_center = 217 centers->ext_center =
218 centers->synth_center + (extoff * 218 centers->synth_center + (extoff *
219 ((ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? 219 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
220 HT40_CHANNEL_CENTER_SHIFT : 15)); 220 HT40_CHANNEL_CENTER_SHIFT : 15));
221} 221}
222 222
@@ -235,7 +235,7 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
235 ah->hw_version.macVersion = 235 ah->hw_version.macVersion =
236 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 236 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
237 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 237 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
238 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 238 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
239 } else { 239 } else {
240 if (!AR_SREV_9100(ah)) 240 if (!AR_SREV_9100(ah))
241 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 241 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
@@ -243,7 +243,7 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
243 ah->hw_version.macRev = val & AR_SREV_REVISION; 243 ah->hw_version.macRev = val & AR_SREV_REVISION;
244 244
245 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 245 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
246 ah->ah_isPciExpress = true; 246 ah->is_pciexpress = true;
247 } 247 }
248} 248}
249 249
@@ -355,40 +355,40 @@ static void ath9k_hw_set_defaults(struct ath_hw *ah)
355{ 355{
356 int i; 356 int i;
357 357
358 ah->ah_config.dma_beacon_response_time = 2; 358 ah->config.dma_beacon_response_time = 2;
359 ah->ah_config.sw_beacon_response_time = 10; 359 ah->config.sw_beacon_response_time = 10;
360 ah->ah_config.additional_swba_backoff = 0; 360 ah->config.additional_swba_backoff = 0;
361 ah->ah_config.ack_6mb = 0x0; 361 ah->config.ack_6mb = 0x0;
362 ah->ah_config.cwm_ignore_extcca = 0; 362 ah->config.cwm_ignore_extcca = 0;
363 ah->ah_config.pcie_powersave_enable = 0; 363 ah->config.pcie_powersave_enable = 0;
364 ah->ah_config.pcie_l1skp_enable = 0; 364 ah->config.pcie_l1skp_enable = 0;
365 ah->ah_config.pcie_clock_req = 0; 365 ah->config.pcie_clock_req = 0;
366 ah->ah_config.pcie_power_reset = 0x100; 366 ah->config.pcie_power_reset = 0x100;
367 ah->ah_config.pcie_restore = 0; 367 ah->config.pcie_restore = 0;
368 ah->ah_config.pcie_waen = 0; 368 ah->config.pcie_waen = 0;
369 ah->ah_config.analog_shiftreg = 1; 369 ah->config.analog_shiftreg = 1;
370 ah->ah_config.ht_enable = 1; 370 ah->config.ht_enable = 1;
371 ah->ah_config.ofdm_trig_low = 200; 371 ah->config.ofdm_trig_low = 200;
372 ah->ah_config.ofdm_trig_high = 500; 372 ah->config.ofdm_trig_high = 500;
373 ah->ah_config.cck_trig_high = 200; 373 ah->config.cck_trig_high = 200;
374 ah->ah_config.cck_trig_low = 100; 374 ah->config.cck_trig_low = 100;
375 ah->ah_config.enable_ani = 1; 375 ah->config.enable_ani = 1;
376 ah->ah_config.noise_immunity_level = 4; 376 ah->config.noise_immunity_level = 4;
377 ah->ah_config.ofdm_weaksignal_det = 1; 377 ah->config.ofdm_weaksignal_det = 1;
378 ah->ah_config.cck_weaksignal_thr = 0; 378 ah->config.cck_weaksignal_thr = 0;
379 ah->ah_config.spur_immunity_level = 2; 379 ah->config.spur_immunity_level = 2;
380 ah->ah_config.firstep_level = 0; 380 ah->config.firstep_level = 0;
381 ah->ah_config.rssi_thr_high = 40; 381 ah->config.rssi_thr_high = 40;
382 ah->ah_config.rssi_thr_low = 7; 382 ah->config.rssi_thr_low = 7;
383 ah->ah_config.diversity_control = 0; 383 ah->config.diversity_control = 0;
384 ah->ah_config.antenna_switch_swap = 0; 384 ah->config.antenna_switch_swap = 0;
385 385
386 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 386 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
387 ah->ah_config.spurchans[i][0] = AR_NO_SPUR; 387 ah->config.spurchans[i][0] = AR_NO_SPUR;
388 ah->ah_config.spurchans[i][1] = AR_NO_SPUR; 388 ah->config.spurchans[i][1] = AR_NO_SPUR;
389 } 389 }
390 390
391 ah->ah_config.intr_mitigation = 1; 391 ah->config.intr_mitigation = 1;
392} 392}
393 393
394static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc, 394static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
@@ -418,19 +418,19 @@ static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
418 418
419 ah->regulatory.power_limit = MAX_RATE_POWER; 419 ah->regulatory.power_limit = MAX_RATE_POWER;
420 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX; 420 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
421 ah->ah_atimWindow = 0; 421 ah->atim_window = 0;
422 ah->ah_diversityControl = ah->ah_config.diversity_control; 422 ah->diversity_control = ah->config.diversity_control;
423 ah->ah_antennaSwitchSwap = 423 ah->antenna_switch_swap =
424 ah->ah_config.antenna_switch_swap; 424 ah->config.antenna_switch_swap;
425 ah->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 425 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
426 ah->ah_beaconInterval = 100; 426 ah->beacon_interval = 100;
427 ah->ah_enable32kHzClock = DONT_USE_32KHZ; 427 ah->enable_32kHz_clock = DONT_USE_32KHZ;
428 ah->ah_slottime = (u32) -1; 428 ah->slottime = (u32) -1;
429 ah->ah_acktimeout = (u32) -1; 429 ah->acktimeout = (u32) -1;
430 ah->ah_ctstimeout = (u32) -1; 430 ah->ctstimeout = (u32) -1;
431 ah->ah_globaltxtimeout = (u32) -1; 431 ah->globaltxtimeout = (u32) -1;
432 432
433 ah->ah_gBeaconRate = 0; 433 ah->gbeacon_rate = 0;
434 434
435 return ah; 435 return ah;
436} 436}
@@ -510,19 +510,19 @@ static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
510 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); 510 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
511 511
512 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 512 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
513 INIT_INI_ARRAY(&ah->ah_iniModesRxGain, 513 INIT_INI_ARRAY(&ah->iniModesRxGain,
514 ar9280Modes_backoff_13db_rxgain_9280_2, 514 ar9280Modes_backoff_13db_rxgain_9280_2,
515 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); 515 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
516 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 516 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
517 INIT_INI_ARRAY(&ah->ah_iniModesRxGain, 517 INIT_INI_ARRAY(&ah->iniModesRxGain,
518 ar9280Modes_backoff_23db_rxgain_9280_2, 518 ar9280Modes_backoff_23db_rxgain_9280_2,
519 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); 519 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
520 else 520 else
521 INIT_INI_ARRAY(&ah->ah_iniModesRxGain, 521 INIT_INI_ARRAY(&ah->iniModesRxGain,
522 ar9280Modes_original_rxgain_9280_2, 522 ar9280Modes_original_rxgain_9280_2,
523 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 523 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
524 } else { 524 } else {
525 INIT_INI_ARRAY(&ah->ah_iniModesRxGain, 525 INIT_INI_ARRAY(&ah->iniModesRxGain,
526 ar9280Modes_original_rxgain_9280_2, 526 ar9280Modes_original_rxgain_9280_2,
527 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 527 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
528 } 528 }
@@ -536,15 +536,15 @@ static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
536 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); 536 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
537 537
538 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 538 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
539 INIT_INI_ARRAY(&ah->ah_iniModesTxGain, 539 INIT_INI_ARRAY(&ah->iniModesTxGain,
540 ar9280Modes_high_power_tx_gain_9280_2, 540 ar9280Modes_high_power_tx_gain_9280_2,
541 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); 541 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
542 else 542 else
543 INIT_INI_ARRAY(&ah->ah_iniModesTxGain, 543 INIT_INI_ARRAY(&ah->iniModesTxGain,
544 ar9280Modes_original_tx_gain_9280_2, 544 ar9280Modes_original_tx_gain_9280_2,
545 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 545 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
546 } else { 546 } else {
547 INIT_INI_ARRAY(&ah->ah_iniModesTxGain, 547 INIT_INI_ARRAY(&ah->iniModesTxGain,
548 ar9280Modes_original_tx_gain_9280_2, 548 ar9280Modes_original_tx_gain_9280_2,
549 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 549 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
550 } 550 }
@@ -592,8 +592,8 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
592 592
593 ath9k_hw_set_defaults(ah); 593 ath9k_hw_set_defaults(ah);
594 594
595 if (ah->ah_config.intr_mitigation != 0) 595 if (ah->config.intr_mitigation != 0)
596 ah->ah_intrMitigation = true; 596 ah->intr_mitigation = true;
597 597
598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
599 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n"); 599 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
@@ -607,18 +607,18 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
607 goto bad; 607 goto bad;
608 } 608 }
609 609
610 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) { 610 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
611 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) { 611 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) {
612 ah->ah_config.serialize_regmode = 612 ah->config.serialize_regmode =
613 SER_REG_MODE_ON; 613 SER_REG_MODE_ON;
614 } else { 614 } else {
615 ah->ah_config.serialize_regmode = 615 ah->config.serialize_regmode =
616 SER_REG_MODE_OFF; 616 SER_REG_MODE_OFF;
617 } 617 }
618 } 618 }
619 619
620 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n", 620 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
621 ah->ah_config.serialize_regmode); 621 ah->config.serialize_regmode);
622 622
623 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) && 623 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
624 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && 624 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
@@ -633,41 +633,41 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
633 } 633 }
634 634
635 if (AR_SREV_9100(ah)) { 635 if (AR_SREV_9100(ah)) {
636 ah->ah_iqCalData.calData = &iq_cal_multi_sample; 636 ah->iq_caldata.calData = &iq_cal_multi_sample;
637 ah->ah_suppCals = IQ_MISMATCH_CAL; 637 ah->supp_cals = IQ_MISMATCH_CAL;
638 ah->ah_isPciExpress = false; 638 ah->is_pciexpress = false;
639 } 639 }
640 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 640 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
641 641
642 if (AR_SREV_9160_10_OR_LATER(ah)) { 642 if (AR_SREV_9160_10_OR_LATER(ah)) {
643 if (AR_SREV_9280_10_OR_LATER(ah)) { 643 if (AR_SREV_9280_10_OR_LATER(ah)) {
644 ah->ah_iqCalData.calData = &iq_cal_single_sample; 644 ah->iq_caldata.calData = &iq_cal_single_sample;
645 ah->ah_adcGainCalData.calData = 645 ah->adcgain_caldata.calData =
646 &adc_gain_cal_single_sample; 646 &adc_gain_cal_single_sample;
647 ah->ah_adcDcCalData.calData = 647 ah->adcdc_caldata.calData =
648 &adc_dc_cal_single_sample; 648 &adc_dc_cal_single_sample;
649 ah->ah_adcDcCalInitData.calData = 649 ah->adcdc_calinitdata.calData =
650 &adc_init_dc_cal; 650 &adc_init_dc_cal;
651 } else { 651 } else {
652 ah->ah_iqCalData.calData = &iq_cal_multi_sample; 652 ah->iq_caldata.calData = &iq_cal_multi_sample;
653 ah->ah_adcGainCalData.calData = 653 ah->adcgain_caldata.calData =
654 &adc_gain_cal_multi_sample; 654 &adc_gain_cal_multi_sample;
655 ah->ah_adcDcCalData.calData = 655 ah->adcdc_caldata.calData =
656 &adc_dc_cal_multi_sample; 656 &adc_dc_cal_multi_sample;
657 ah->ah_adcDcCalInitData.calData = 657 ah->adcdc_calinitdata.calData =
658 &adc_init_dc_cal; 658 &adc_init_dc_cal;
659 } 659 }
660 ah->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 660 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
661 } 661 }
662 662
663 if (AR_SREV_9160(ah)) { 663 if (AR_SREV_9160(ah)) {
664 ah->ah_config.enable_ani = 1; 664 ah->config.enable_ani = 1;
665 ah->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | 665 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
666 ATH9K_ANI_FIRSTEP_LEVEL); 666 ATH9K_ANI_FIRSTEP_LEVEL);
667 } else { 667 } else {
668 ah->ah_ani_function = ATH9K_ANI_ALL; 668 ah->ani_function = ATH9K_ANI_ALL;
669 if (AR_SREV_9280_10_OR_LATER(ah)) { 669 if (AR_SREV_9280_10_OR_LATER(ah)) {
670 ah->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 670 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
671 } 671 }
672 } 672 }
673 673
@@ -676,137 +676,137 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
676 ah->hw_version.macVersion, ah->hw_version.macRev); 676 ah->hw_version.macVersion, ah->hw_version.macRev);
677 677
678 if (AR_SREV_9285_12_OR_LATER(ah)) { 678 if (AR_SREV_9285_12_OR_LATER(ah)) {
679 INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285_1_2, 679 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
680 ARRAY_SIZE(ar9285Modes_9285_1_2), 6); 680 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
681 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285_1_2, 681 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
682 ARRAY_SIZE(ar9285Common_9285_1_2), 2); 682 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
683 683
684 if (ah->ah_config.pcie_clock_req) { 684 if (ah->config.pcie_clock_req) {
685 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, 685 INIT_INI_ARRAY(&ah->iniPcieSerdes,
686 ar9285PciePhy_clkreq_off_L1_9285_1_2, 686 ar9285PciePhy_clkreq_off_L1_9285_1_2,
687 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); 687 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
688 } else { 688 } else {
689 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, 689 INIT_INI_ARRAY(&ah->iniPcieSerdes,
690 ar9285PciePhy_clkreq_always_on_L1_9285_1_2, 690 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
691 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 691 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
692 2); 692 2);
693 } 693 }
694 } else if (AR_SREV_9285_10_OR_LATER(ah)) { 694 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
695 INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285, 695 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
696 ARRAY_SIZE(ar9285Modes_9285), 6); 696 ARRAY_SIZE(ar9285Modes_9285), 6);
697 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285, 697 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
698 ARRAY_SIZE(ar9285Common_9285), 2); 698 ARRAY_SIZE(ar9285Common_9285), 2);
699 699
700 if (ah->ah_config.pcie_clock_req) { 700 if (ah->config.pcie_clock_req) {
701 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, 701 INIT_INI_ARRAY(&ah->iniPcieSerdes,
702 ar9285PciePhy_clkreq_off_L1_9285, 702 ar9285PciePhy_clkreq_off_L1_9285,
703 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); 703 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
704 } else { 704 } else {
705 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, 705 INIT_INI_ARRAY(&ah->iniPcieSerdes,
706 ar9285PciePhy_clkreq_always_on_L1_9285, 706 ar9285PciePhy_clkreq_always_on_L1_9285,
707 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); 707 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
708 } 708 }
709 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 709 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
710 INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280_2, 710 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
711 ARRAY_SIZE(ar9280Modes_9280_2), 6); 711 ARRAY_SIZE(ar9280Modes_9280_2), 6);
712 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280_2, 712 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
713 ARRAY_SIZE(ar9280Common_9280_2), 2); 713 ARRAY_SIZE(ar9280Common_9280_2), 2);
714 714
715 if (ah->ah_config.pcie_clock_req) { 715 if (ah->config.pcie_clock_req) {
716 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, 716 INIT_INI_ARRAY(&ah->iniPcieSerdes,
717 ar9280PciePhy_clkreq_off_L1_9280, 717 ar9280PciePhy_clkreq_off_L1_9280,
718 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); 718 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
719 } else { 719 } else {
720 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, 720 INIT_INI_ARRAY(&ah->iniPcieSerdes,
721 ar9280PciePhy_clkreq_always_on_L1_9280, 721 ar9280PciePhy_clkreq_always_on_L1_9280,
722 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); 722 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
723 } 723 }
724 INIT_INI_ARRAY(&ah->ah_iniModesAdditional, 724 INIT_INI_ARRAY(&ah->iniModesAdditional,
725 ar9280Modes_fast_clock_9280_2, 725 ar9280Modes_fast_clock_9280_2,
726 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); 726 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
727 } else if (AR_SREV_9280_10_OR_LATER(ah)) { 727 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
728 INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280, 728 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
729 ARRAY_SIZE(ar9280Modes_9280), 6); 729 ARRAY_SIZE(ar9280Modes_9280), 6);
730 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280, 730 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
731 ARRAY_SIZE(ar9280Common_9280), 2); 731 ARRAY_SIZE(ar9280Common_9280), 2);
732 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 732 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
733 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9160, 733 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
734 ARRAY_SIZE(ar5416Modes_9160), 6); 734 ARRAY_SIZE(ar5416Modes_9160), 6);
735 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9160, 735 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
736 ARRAY_SIZE(ar5416Common_9160), 2); 736 ARRAY_SIZE(ar5416Common_9160), 2);
737 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9160, 737 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
738 ARRAY_SIZE(ar5416Bank0_9160), 2); 738 ARRAY_SIZE(ar5416Bank0_9160), 2);
739 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9160, 739 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
740 ARRAY_SIZE(ar5416BB_RfGain_9160), 3); 740 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
741 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9160, 741 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
742 ARRAY_SIZE(ar5416Bank1_9160), 2); 742 ARRAY_SIZE(ar5416Bank1_9160), 2);
743 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9160, 743 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
744 ARRAY_SIZE(ar5416Bank2_9160), 2); 744 ARRAY_SIZE(ar5416Bank2_9160), 2);
745 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9160, 745 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
746 ARRAY_SIZE(ar5416Bank3_9160), 3); 746 ARRAY_SIZE(ar5416Bank3_9160), 3);
747 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9160, 747 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
748 ARRAY_SIZE(ar5416Bank6_9160), 3); 748 ARRAY_SIZE(ar5416Bank6_9160), 3);
749 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9160, 749 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
750 ARRAY_SIZE(ar5416Bank6TPC_9160), 3); 750 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
751 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9160, 751 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
752 ARRAY_SIZE(ar5416Bank7_9160), 2); 752 ARRAY_SIZE(ar5416Bank7_9160), 2);
753 if (AR_SREV_9160_11(ah)) { 753 if (AR_SREV_9160_11(ah)) {
754 INIT_INI_ARRAY(&ah->ah_iniAddac, 754 INIT_INI_ARRAY(&ah->iniAddac,
755 ar5416Addac_91601_1, 755 ar5416Addac_91601_1,
756 ARRAY_SIZE(ar5416Addac_91601_1), 2); 756 ARRAY_SIZE(ar5416Addac_91601_1), 2);
757 } else { 757 } else {
758 INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9160, 758 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
759 ARRAY_SIZE(ar5416Addac_9160), 2); 759 ARRAY_SIZE(ar5416Addac_9160), 2);
760 } 760 }
761 } else if (AR_SREV_9100_OR_LATER(ah)) { 761 } else if (AR_SREV_9100_OR_LATER(ah)) {
762 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9100, 762 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
763 ARRAY_SIZE(ar5416Modes_9100), 6); 763 ARRAY_SIZE(ar5416Modes_9100), 6);
764 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9100, 764 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
765 ARRAY_SIZE(ar5416Common_9100), 2); 765 ARRAY_SIZE(ar5416Common_9100), 2);
766 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9100, 766 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
767 ARRAY_SIZE(ar5416Bank0_9100), 2); 767 ARRAY_SIZE(ar5416Bank0_9100), 2);
768 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9100, 768 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
769 ARRAY_SIZE(ar5416BB_RfGain_9100), 3); 769 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
770 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9100, 770 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
771 ARRAY_SIZE(ar5416Bank1_9100), 2); 771 ARRAY_SIZE(ar5416Bank1_9100), 2);
772 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9100, 772 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
773 ARRAY_SIZE(ar5416Bank2_9100), 2); 773 ARRAY_SIZE(ar5416Bank2_9100), 2);
774 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9100, 774 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
775 ARRAY_SIZE(ar5416Bank3_9100), 3); 775 ARRAY_SIZE(ar5416Bank3_9100), 3);
776 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9100, 776 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
777 ARRAY_SIZE(ar5416Bank6_9100), 3); 777 ARRAY_SIZE(ar5416Bank6_9100), 3);
778 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9100, 778 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
779 ARRAY_SIZE(ar5416Bank6TPC_9100), 3); 779 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
780 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9100, 780 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
781 ARRAY_SIZE(ar5416Bank7_9100), 2); 781 ARRAY_SIZE(ar5416Bank7_9100), 2);
782 INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9100, 782 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
783 ARRAY_SIZE(ar5416Addac_9100), 2); 783 ARRAY_SIZE(ar5416Addac_9100), 2);
784 } else { 784 } else {
785 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes, 785 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
786 ARRAY_SIZE(ar5416Modes), 6); 786 ARRAY_SIZE(ar5416Modes), 6);
787 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common, 787 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
788 ARRAY_SIZE(ar5416Common), 2); 788 ARRAY_SIZE(ar5416Common), 2);
789 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0, 789 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
790 ARRAY_SIZE(ar5416Bank0), 2); 790 ARRAY_SIZE(ar5416Bank0), 2);
791 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain, 791 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
792 ARRAY_SIZE(ar5416BB_RfGain), 3); 792 ARRAY_SIZE(ar5416BB_RfGain), 3);
793 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1, 793 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
794 ARRAY_SIZE(ar5416Bank1), 2); 794 ARRAY_SIZE(ar5416Bank1), 2);
795 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2, 795 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
796 ARRAY_SIZE(ar5416Bank2), 2); 796 ARRAY_SIZE(ar5416Bank2), 2);
797 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3, 797 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
798 ARRAY_SIZE(ar5416Bank3), 3); 798 ARRAY_SIZE(ar5416Bank3), 3);
799 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6, 799 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
800 ARRAY_SIZE(ar5416Bank6), 3); 800 ARRAY_SIZE(ar5416Bank6), 3);
801 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC, 801 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
802 ARRAY_SIZE(ar5416Bank6TPC), 3); 802 ARRAY_SIZE(ar5416Bank6TPC), 3);
803 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7, 803 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
804 ARRAY_SIZE(ar5416Bank7), 2); 804 ARRAY_SIZE(ar5416Bank7), 2);
805 INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac, 805 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
806 ARRAY_SIZE(ar5416Addac), 2); 806 ARRAY_SIZE(ar5416Addac), 2);
807 } 807 }
808 808
809 if (ah->ah_isPciExpress) 809 if (ah->is_pciexpress)
810 ath9k_hw_configpcipowersave(ah, 0); 810 ath9k_hw_configpcipowersave(ah, 0);
811 else 811 else
812 ath9k_hw_disablepcie(ah); 812 ath9k_hw_disablepcie(ah);
@@ -824,15 +824,15 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
824 ath9k_hw_init_txgain_ini(ah); 824 ath9k_hw_init_txgain_ini(ah);
825 825
826 if (ah->hw_version.devid == AR9280_DEVID_PCI) { 826 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
827 for (i = 0; i < ah->ah_iniModes.ia_rows; i++) { 827 for (i = 0; i < ah->iniModes.ia_rows; i++) {
828 u32 reg = INI_RA(&ah->ah_iniModes, i, 0); 828 u32 reg = INI_RA(&ah->iniModes, i, 0);
829 829
830 for (j = 1; j < ah->ah_iniModes.ia_columns; j++) { 830 for (j = 1; j < ah->iniModes.ia_columns; j++) {
831 u32 val = INI_RA(&ah->ah_iniModes, i, j); 831 u32 val = INI_RA(&ah->iniModes, i, j);
832 832
833 INI_RA(&ah->ah_iniModes, i, j) = 833 INI_RA(&ah->iniModes, i, j) =
834 ath9k_hw_ini_fixup(ah, 834 ath9k_hw_ini_fixup(ah,
835 &ah->ah_eeprom.def, 835 &ah->eeprom.def,
836 reg, val); 836 reg, val);
837 } 837 }
838 } 838 }
@@ -853,9 +853,9 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
853 } 853 }
854 854
855 if (AR_SREV_9285(ah)) 855 if (AR_SREV_9285(ah))
856 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S); 856 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
857 else 857 else
858 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S); 858 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
859 859
860 ath9k_init_nfcal_hist_buffer(ah); 860 ath9k_init_nfcal_hist_buffer(ah);
861 861
@@ -974,8 +974,8 @@ static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
974{ 974{
975 int rx_chainmask, tx_chainmask; 975 int rx_chainmask, tx_chainmask;
976 976
977 rx_chainmask = ah->ah_rxchainmask; 977 rx_chainmask = ah->rxchainmask;
978 tx_chainmask = ah->ah_txchainmask; 978 tx_chainmask = ah->txchainmask;
979 979
980 switch (rx_chainmask) { 980 switch (rx_chainmask) {
981 case 0x5: 981 case 0x5:
@@ -1010,23 +1010,23 @@ static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1010static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 1010static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1011 enum nl80211_iftype opmode) 1011 enum nl80211_iftype opmode)
1012{ 1012{
1013 ah->ah_maskReg = AR_IMR_TXERR | 1013 ah->mask_reg = AR_IMR_TXERR |
1014 AR_IMR_TXURN | 1014 AR_IMR_TXURN |
1015 AR_IMR_RXERR | 1015 AR_IMR_RXERR |
1016 AR_IMR_RXORN | 1016 AR_IMR_RXORN |
1017 AR_IMR_BCNMISC; 1017 AR_IMR_BCNMISC;
1018 1018
1019 if (ah->ah_intrMitigation) 1019 if (ah->intr_mitigation)
1020 ah->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 1020 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1021 else 1021 else
1022 ah->ah_maskReg |= AR_IMR_RXOK; 1022 ah->mask_reg |= AR_IMR_RXOK;
1023 1023
1024 ah->ah_maskReg |= AR_IMR_TXOK; 1024 ah->mask_reg |= AR_IMR_TXOK;
1025 1025
1026 if (opmode == NL80211_IFTYPE_AP) 1026 if (opmode == NL80211_IFTYPE_AP)
1027 ah->ah_maskReg |= AR_IMR_MIB; 1027 ah->mask_reg |= AR_IMR_MIB;
1028 1028
1029 REG_WRITE(ah, AR_IMR, ah->ah_maskReg); 1029 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1030 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); 1030 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1031 1031
1032 if (!AR_SREV_9100(ah)) { 1032 if (!AR_SREV_9100(ah)) {
@@ -1040,12 +1040,12 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1040{ 1040{
1041 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 1041 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1042 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); 1042 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1043 ah->ah_acktimeout = (u32) -1; 1043 ah->acktimeout = (u32) -1;
1044 return false; 1044 return false;
1045 } else { 1045 } else {
1046 REG_RMW_FIELD(ah, AR_TIME_OUT, 1046 REG_RMW_FIELD(ah, AR_TIME_OUT,
1047 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); 1047 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1048 ah->ah_acktimeout = us; 1048 ah->acktimeout = us;
1049 return true; 1049 return true;
1050 } 1050 }
1051} 1051}
@@ -1054,12 +1054,12 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1054{ 1054{
1055 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 1055 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1056 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); 1056 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1057 ah->ah_ctstimeout = (u32) -1; 1057 ah->ctstimeout = (u32) -1;
1058 return false; 1058 return false;
1059 } else { 1059 } else {
1060 REG_RMW_FIELD(ah, AR_TIME_OUT, 1060 REG_RMW_FIELD(ah, AR_TIME_OUT,
1061 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); 1061 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1062 ah->ah_ctstimeout = us; 1062 ah->ctstimeout = us;
1063 return true; 1063 return true;
1064 } 1064 }
1065} 1065}
@@ -1069,31 +1069,31 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1069 if (tu > 0xFFFF) { 1069 if (tu > 0xFFFF) {
1070 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 1070 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1071 "bad global tx timeout %u\n", tu); 1071 "bad global tx timeout %u\n", tu);
1072 ah->ah_globaltxtimeout = (u32) -1; 1072 ah->globaltxtimeout = (u32) -1;
1073 return false; 1073 return false;
1074 } else { 1074 } else {
1075 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1075 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1076 ah->ah_globaltxtimeout = tu; 1076 ah->globaltxtimeout = tu;
1077 return true; 1077 return true;
1078 } 1078 }
1079} 1079}
1080 1080
1081static void ath9k_hw_init_user_settings(struct ath_hw *ah) 1081static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1082{ 1082{
1083 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->ah_miscMode 0x%x\n", 1083 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1084 ah->ah_miscMode); 1084 ah->misc_mode);
1085 1085
1086 if (ah->ah_miscMode != 0) 1086 if (ah->misc_mode != 0)
1087 REG_WRITE(ah, AR_PCU_MISC, 1087 REG_WRITE(ah, AR_PCU_MISC,
1088 REG_READ(ah, AR_PCU_MISC) | ah->ah_miscMode); 1088 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1089 if (ah->ah_slottime != (u32) -1) 1089 if (ah->slottime != (u32) -1)
1090 ath9k_hw_setslottime(ah, ah->ah_slottime); 1090 ath9k_hw_setslottime(ah, ah->slottime);
1091 if (ah->ah_acktimeout != (u32) -1) 1091 if (ah->acktimeout != (u32) -1)
1092 ath9k_hw_set_ack_timeout(ah, ah->ah_acktimeout); 1092 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1093 if (ah->ah_ctstimeout != (u32) -1) 1093 if (ah->ctstimeout != (u32) -1)
1094 ath9k_hw_set_cts_timeout(ah, ah->ah_ctstimeout); 1094 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1095 if (ah->ah_globaltxtimeout != (u32) -1) 1095 if (ah->globaltxtimeout != (u32) -1)
1096 ath9k_hw_set_global_txtimeout(ah, ah->ah_globaltxtimeout); 1096 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1097} 1097}
1098 1098
1099const char *ath9k_hw_probe(u16 vendorid, u16 devid) 1099const char *ath9k_hw_probe(u16 vendorid, u16 devid)
@@ -1194,7 +1194,7 @@ static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1194 struct ar5416_eeprom_def *pEepData, 1194 struct ar5416_eeprom_def *pEepData,
1195 u32 reg, u32 value) 1195 u32 reg, u32 value)
1196{ 1196{
1197 if (ah->ah_eep_map == EEP_MAP_4KBITS) 1197 if (ah->eep_map == EEP_MAP_4KBITS)
1198 return value; 1198 return value;
1199 else 1199 else
1200 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); 1200 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
@@ -1241,34 +1241,34 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1241 ah->eep_ops->set_addac(ah, chan); 1241 ah->eep_ops->set_addac(ah, chan);
1242 1242
1243 if (AR_SREV_5416_V22_OR_LATER(ah)) { 1243 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1244 REG_WRITE_ARRAY(&ah->ah_iniAddac, 1, regWrites); 1244 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1245 } else { 1245 } else {
1246 struct ar5416IniArray temp; 1246 struct ar5416IniArray temp;
1247 u32 addacSize = 1247 u32 addacSize =
1248 sizeof(u32) * ah->ah_iniAddac.ia_rows * 1248 sizeof(u32) * ah->iniAddac.ia_rows *
1249 ah->ah_iniAddac.ia_columns; 1249 ah->iniAddac.ia_columns;
1250 1250
1251 memcpy(ah->ah_addac5416_21, 1251 memcpy(ah->addac5416_21,
1252 ah->ah_iniAddac.ia_array, addacSize); 1252 ah->iniAddac.ia_array, addacSize);
1253 1253
1254 (ah->ah_addac5416_21)[31 * ah->ah_iniAddac.ia_columns + 1] = 0; 1254 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1255 1255
1256 temp.ia_array = ah->ah_addac5416_21; 1256 temp.ia_array = ah->addac5416_21;
1257 temp.ia_columns = ah->ah_iniAddac.ia_columns; 1257 temp.ia_columns = ah->iniAddac.ia_columns;
1258 temp.ia_rows = ah->ah_iniAddac.ia_rows; 1258 temp.ia_rows = ah->iniAddac.ia_rows;
1259 REG_WRITE_ARRAY(&temp, 1, regWrites); 1259 REG_WRITE_ARRAY(&temp, 1, regWrites);
1260 } 1260 }
1261 1261
1262 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 1262 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1263 1263
1264 for (i = 0; i < ah->ah_iniModes.ia_rows; i++) { 1264 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1265 u32 reg = INI_RA(&ah->ah_iniModes, i, 0); 1265 u32 reg = INI_RA(&ah->iniModes, i, 0);
1266 u32 val = INI_RA(&ah->ah_iniModes, i, modesIndex); 1266 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1267 1267
1268 REG_WRITE(ah, reg, val); 1268 REG_WRITE(ah, reg, val);
1269 1269
1270 if (reg >= 0x7800 && reg < 0x78a0 1270 if (reg >= 0x7800 && reg < 0x78a0
1271 && ah->ah_config.analog_shiftreg) { 1271 && ah->config.analog_shiftreg) {
1272 udelay(100); 1272 udelay(100);
1273 } 1273 }
1274 1274
@@ -1276,19 +1276,19 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1276 } 1276 }
1277 1277
1278 if (AR_SREV_9280(ah)) 1278 if (AR_SREV_9280(ah))
1279 REG_WRITE_ARRAY(&ah->ah_iniModesRxGain, modesIndex, regWrites); 1279 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1280 1280
1281 if (AR_SREV_9280(ah)) 1281 if (AR_SREV_9280(ah))
1282 REG_WRITE_ARRAY(&ah->ah_iniModesTxGain, modesIndex, regWrites); 1282 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1283 1283
1284 for (i = 0; i < ah->ah_iniCommon.ia_rows; i++) { 1284 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1285 u32 reg = INI_RA(&ah->ah_iniCommon, i, 0); 1285 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1286 u32 val = INI_RA(&ah->ah_iniCommon, i, 1); 1286 u32 val = INI_RA(&ah->iniCommon, i, 1);
1287 1287
1288 REG_WRITE(ah, reg, val); 1288 REG_WRITE(ah, reg, val);
1289 1289
1290 if (reg >= 0x7800 && reg < 0x78a0 1290 if (reg >= 0x7800 && reg < 0x78a0
1291 && ah->ah_config.analog_shiftreg) { 1291 && ah->config.analog_shiftreg) {
1292 udelay(100); 1292 udelay(100);
1293 } 1293 }
1294 1294
@@ -1298,7 +1298,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1298 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); 1298 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1299 1299
1300 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1300 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1301 REG_WRITE_ARRAY(&ah->ah_iniModesAdditional, modesIndex, 1301 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1302 regWrites); 1302 regWrites);
1303 } 1303 }
1304 1304
@@ -1366,7 +1366,7 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1366 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 1366 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1367 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 1367 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1368 1368
1369 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel); 1369 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1370 1370
1371 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 1371 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1372 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 1372 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
@@ -1566,7 +1566,7 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1566 (chan->chanmode == CHANNEL_G_HT40PLUS)) 1566 (chan->chanmode == CHANNEL_G_HT40PLUS))
1567 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 1567 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1568 1568
1569 if (ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) 1569 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1570 phymode |= AR_PHY_FC_DYN2040_EXT_CH; 1570 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1571 } 1571 }
1572 REG_WRITE(ah, AR_PHY_TURBO, phymode); 1572 REG_WRITE(ah, AR_PHY_TURBO, phymode);
@@ -1586,7 +1586,7 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1586 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1586 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1587 return false; 1587 return false;
1588 1588
1589 ah->ah_chipFullSleep = false; 1589 ah->chip_fullsleep = false;
1590 ath9k_hw_init_pll(ah, chan); 1590 ath9k_hw_init_pll(ah, chan);
1591 ath9k_hw_set_rfmode(ah, chan); 1591 ath9k_hw_set_rfmode(ah, chan);
1592 1592
@@ -1701,7 +1701,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel
1701 ath9k_hw_get_channel_centers(ah, chan, &centers); 1701 ath9k_hw_get_channel_centers(ah, chan, &centers);
1702 freq = centers.synth_center; 1702 freq = centers.synth_center;
1703 1703
1704 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM; 1704 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1705 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 1705 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1706 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 1706 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1707 1707
@@ -2123,21 +2123,21 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2123{ 2123{
2124 u32 saveLedState; 2124 u32 saveLedState;
2125 struct ath_softc *sc = ah->ah_sc; 2125 struct ath_softc *sc = ah->ah_sc;
2126 struct ath9k_channel *curchan = ah->ah_curchan; 2126 struct ath9k_channel *curchan = ah->curchan;
2127 u32 saveDefAntenna; 2127 u32 saveDefAntenna;
2128 u32 macStaId1; 2128 u32 macStaId1;
2129 int i, rx_chainmask, r; 2129 int i, rx_chainmask, r;
2130 2130
2131 ah->ah_extprotspacing = sc->ht_extprotspacing; 2131 ah->extprotspacing = sc->ht_extprotspacing;
2132 ah->ah_txchainmask = sc->tx_chainmask; 2132 ah->txchainmask = sc->tx_chainmask;
2133 ah->ah_rxchainmask = sc->rx_chainmask; 2133 ah->rxchainmask = sc->rx_chainmask;
2134 2134
2135 if (AR_SREV_9285(ah)) { 2135 if (AR_SREV_9285(ah)) {
2136 ah->ah_txchainmask &= 0x1; 2136 ah->txchainmask &= 0x1;
2137 ah->ah_rxchainmask &= 0x1; 2137 ah->rxchainmask &= 0x1;
2138 } else if (AR_SREV_9280(ah)) { 2138 } else if (AR_SREV_9280(ah)) {
2139 ah->ah_txchainmask &= 0x3; 2139 ah->txchainmask &= 0x3;
2140 ah->ah_rxchainmask &= 0x3; 2140 ah->rxchainmask &= 0x3;
2141 } 2141 }
2142 2142
2143 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2143 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
@@ -2147,16 +2147,16 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2147 ath9k_hw_getnf(ah, curchan); 2147 ath9k_hw_getnf(ah, curchan);
2148 2148
2149 if (bChannelChange && 2149 if (bChannelChange &&
2150 (ah->ah_chipFullSleep != true) && 2150 (ah->chip_fullsleep != true) &&
2151 (ah->ah_curchan != NULL) && 2151 (ah->curchan != NULL) &&
2152 (chan->channel != ah->ah_curchan->channel) && 2152 (chan->channel != ah->curchan->channel) &&
2153 ((chan->channelFlags & CHANNEL_ALL) == 2153 ((chan->channelFlags & CHANNEL_ALL) ==
2154 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) && 2154 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2155 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && 2155 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2156 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) { 2156 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2157 2157
2158 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) { 2158 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2159 ath9k_hw_loadnf(ah, ah->ah_curchan); 2159 ath9k_hw_loadnf(ah, ah->curchan);
2160 ath9k_hw_start_nfcal(ah); 2160 ath9k_hw_start_nfcal(ah);
2161 return 0; 2161 return 0;
2162 } 2162 }
@@ -2223,10 +2223,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2223 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4) 2223 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2224 | macStaId1 2224 | macStaId1
2225 | AR_STA_ID1_RTS_USE_DEF 2225 | AR_STA_ID1_RTS_USE_DEF
2226 | (ah->ah_config. 2226 | (ah->config.
2227 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 2227 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2228 | ah->ah_staId1Defaults); 2228 | ah->sta_id1_defaults);
2229 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); 2229 ath9k_hw_set_operating_mode(ah, ah->opmode);
2230 2230
2231 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); 2231 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2232 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4)); 2232 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
@@ -2252,15 +2252,15 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2252 for (i = 0; i < AR_NUM_DCU; i++) 2252 for (i = 0; i < AR_NUM_DCU; i++)
2253 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2253 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2254 2254
2255 ah->ah_intrTxqs = 0; 2255 ah->intr_txqs = 0;
2256 for (i = 0; i < ah->ah_caps.total_queues; i++) 2256 for (i = 0; i < ah->caps.total_queues; i++)
2257 ath9k_hw_resettxqueue(ah, i); 2257 ath9k_hw_resettxqueue(ah, i);
2258 2258
2259 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode); 2259 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2260 ath9k_hw_init_qos(ah); 2260 ath9k_hw_init_qos(ah);
2261 2261
2262#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2262#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2263 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2263 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2264 ath9k_enable_rfkill(ah); 2264 ath9k_enable_rfkill(ah);
2265#endif 2265#endif
2266 ath9k_hw_init_user_settings(ah); 2266 ath9k_hw_init_user_settings(ah);
@@ -2272,7 +2272,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2272 2272
2273 REG_WRITE(ah, AR_OBS, 8); 2273 REG_WRITE(ah, AR_OBS, 8);
2274 2274
2275 if (ah->ah_intrMitigation) { 2275 if (ah->intr_mitigation) {
2276 2276
2277 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2277 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2278 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2278 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
@@ -2283,7 +2283,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2283 if (!ath9k_hw_init_cal(ah, chan)) 2283 if (!ath9k_hw_init_cal(ah, chan))
2284 return -EIO;; 2284 return -EIO;;
2285 2285
2286 rx_chainmask = ah->ah_rxchainmask; 2286 rx_chainmask = ah->rxchainmask;
2287 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 2287 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2288 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 2288 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2289 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 2289 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
@@ -2321,7 +2321,7 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2321{ 2321{
2322 u32 keyType; 2322 u32 keyType;
2323 2323
2324 if (entry >= ah->ah_caps.keycache_size) { 2324 if (entry >= ah->caps.keycache_size) {
2325 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2325 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2326 "entry %u out of range\n", entry); 2326 "entry %u out of range\n", entry);
2327 return false; 2327 return false;
@@ -2348,7 +2348,7 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2348 2348
2349 } 2349 }
2350 2350
2351 if (ah->ah_curchan == NULL) 2351 if (ah->curchan == NULL)
2352 return true; 2352 return true;
2353 2353
2354 return true; 2354 return true;
@@ -2358,7 +2358,7 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2358{ 2358{
2359 u32 macHi, macLo; 2359 u32 macHi, macLo;
2360 2360
2361 if (entry >= ah->ah_caps.keycache_size) { 2361 if (entry >= ah->caps.keycache_size) {
2362 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2362 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2363 "entry %u out of range\n", entry); 2363 "entry %u out of range\n", entry);
2364 return false; 2364 return false;
@@ -2386,7 +2386,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2386 const struct ath9k_keyval *k, 2386 const struct ath9k_keyval *k,
2387 const u8 *mac, int xorKey) 2387 const u8 *mac, int xorKey)
2388{ 2388{
2389 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2389 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2390 u32 key0, key1, key2, key3, key4; 2390 u32 key0, key1, key2, key3, key4;
2391 u32 keyType; 2391 u32 keyType;
2392 u32 xorMask = xorKey ? 2392 u32 xorMask = xorKey ?
@@ -2462,7 +2462,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2462 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2462 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2463 (void) ath9k_hw_keysetmac(ah, entry, mac); 2463 (void) ath9k_hw_keysetmac(ah, entry, mac);
2464 2464
2465 if (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { 2465 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2466 u32 mic0, mic1, mic2, mic3, mic4; 2466 u32 mic0, mic1, mic2, mic3, mic4;
2467 2467
2468 mic0 = get_unaligned_le32(k->kv_mic + 0); 2468 mic0 = get_unaligned_le32(k->kv_mic + 0);
@@ -2506,7 +2506,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2506 (void) ath9k_hw_keysetmac(ah, entry, mac); 2506 (void) ath9k_hw_keysetmac(ah, entry, mac);
2507 } 2507 }
2508 2508
2509 if (ah->ah_curchan == NULL) 2509 if (ah->curchan == NULL)
2510 return true; 2510 return true;
2511 2511
2512 return true; 2512 return true;
@@ -2514,7 +2514,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2514 2514
2515bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) 2515bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2516{ 2516{
2517 if (entry < ah->ah_caps.keycache_size) { 2517 if (entry < ah->caps.keycache_size) {
2518 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 2518 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2519 if (val & AR_KEYTABLE_VALID) 2519 if (val & AR_KEYTABLE_VALID)
2520 return true; 2520 return true;
@@ -2544,7 +2544,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2544{ 2544{
2545 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2545 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2546 if (setChip) { 2546 if (setChip) {
2547 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2547 struct ath9k_hw_capabilities *pCap = &ah->caps;
2548 2548
2549 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2549 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2550 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2550 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
@@ -2608,7 +2608,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2608 }; 2608 };
2609 2609
2610 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n", 2610 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2611 modes[ah->ah_power_mode], modes[mode], 2611 modes[ah->power_mode], modes[mode],
2612 setChip ? "set chip " : ""); 2612 setChip ? "set chip " : "");
2613 2613
2614 switch (mode) { 2614 switch (mode) {
@@ -2617,7 +2617,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2617 break; 2617 break;
2618 case ATH9K_PM_FULL_SLEEP: 2618 case ATH9K_PM_FULL_SLEEP:
2619 ath9k_set_power_sleep(ah, setChip); 2619 ath9k_set_power_sleep(ah, setChip);
2620 ah->ah_chipFullSleep = true; 2620 ah->chip_fullsleep = true;
2621 break; 2621 break;
2622 case ATH9K_PM_NETWORK_SLEEP: 2622 case ATH9K_PM_NETWORK_SLEEP:
2623 ath9k_set_power_network_sleep(ah, setChip); 2623 ath9k_set_power_network_sleep(ah, setChip);
@@ -2627,7 +2627,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2627 "Unknown power mode %u\n", mode); 2627 "Unknown power mode %u\n", mode);
2628 return false; 2628 return false;
2629 } 2629 }
2630 ah->ah_power_mode = mode; 2630 ah->power_mode = mode;
2631 2631
2632 return status; 2632 return status;
2633} 2633}
@@ -2636,19 +2636,19 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2636{ 2636{
2637 u8 i; 2637 u8 i;
2638 2638
2639 if (ah->ah_isPciExpress != true) 2639 if (ah->is_pciexpress != true)
2640 return; 2640 return;
2641 2641
2642 if (ah->ah_config.pcie_powersave_enable == 2) 2642 if (ah->config.pcie_powersave_enable == 2)
2643 return; 2643 return;
2644 2644
2645 if (restore) 2645 if (restore)
2646 return; 2646 return;
2647 2647
2648 if (AR_SREV_9280_20_OR_LATER(ah)) { 2648 if (AR_SREV_9280_20_OR_LATER(ah)) {
2649 for (i = 0; i < ah->ah_iniPcieSerdes.ia_rows; i++) { 2649 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2650 REG_WRITE(ah, INI_RA(&ah->ah_iniPcieSerdes, i, 0), 2650 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2651 INI_RA(&ah->ah_iniPcieSerdes, i, 1)); 2651 INI_RA(&ah->iniPcieSerdes, i, 1));
2652 } 2652 }
2653 udelay(1000); 2653 udelay(1000);
2654 } else if (AR_SREV_9280(ah) && 2654 } else if (AR_SREV_9280(ah) &&
@@ -2660,7 +2660,7 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2660 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); 2660 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2661 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); 2661 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2662 2662
2663 if (ah->ah_config.pcie_clock_req) 2663 if (ah->config.pcie_clock_req)
2664 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); 2664 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2665 else 2665 else
2666 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); 2666 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
@@ -2687,8 +2687,8 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2687 2687
2688 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 2688 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2689 2689
2690 if (ah->ah_config.pcie_waen) { 2690 if (ah->config.pcie_waen) {
2691 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen); 2691 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2692 } else { 2692 } else {
2693 if (AR_SREV_9285(ah)) 2693 if (AR_SREV_9285(ah))
2694 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); 2694 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
@@ -2726,7 +2726,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2726{ 2726{
2727 u32 isr = 0; 2727 u32 isr = 0;
2728 u32 mask2 = 0; 2728 u32 mask2 = 0;
2729 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2729 struct ath9k_hw_capabilities *pCap = &ah->caps;
2730 u32 sync_cause = 0; 2730 u32 sync_cause = 0;
2731 bool fatal_int = false; 2731 bool fatal_int = false;
2732 2732
@@ -2776,7 +2776,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2776 2776
2777 *masked = isr & ATH9K_INT_COMMON; 2777 *masked = isr & ATH9K_INT_COMMON;
2778 2778
2779 if (ah->ah_intrMitigation) { 2779 if (ah->intr_mitigation) {
2780 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 2780 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2781 *masked |= ATH9K_INT_RX; 2781 *masked |= ATH9K_INT_RX;
2782 } 2782 }
@@ -2791,12 +2791,12 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2791 *masked |= ATH9K_INT_TX; 2791 *masked |= ATH9K_INT_TX;
2792 2792
2793 s0_s = REG_READ(ah, AR_ISR_S0_S); 2793 s0_s = REG_READ(ah, AR_ISR_S0_S);
2794 ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); 2794 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2795 ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); 2795 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2796 2796
2797 s1_s = REG_READ(ah, AR_ISR_S1_S); 2797 s1_s = REG_READ(ah, AR_ISR_S1_S);
2798 ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); 2798 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2799 ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); 2799 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2800 } 2800 }
2801 2801
2802 if (isr & AR_ISR_RXORN) { 2802 if (isr & AR_ISR_RXORN) {
@@ -2855,14 +2855,14 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2855 2855
2856enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah) 2856enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
2857{ 2857{
2858 return ah->ah_maskReg; 2858 return ah->mask_reg;
2859} 2859}
2860 2860
2861enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) 2861enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2862{ 2862{
2863 u32 omask = ah->ah_maskReg; 2863 u32 omask = ah->mask_reg;
2864 u32 mask, mask2; 2864 u32 mask, mask2;
2865 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2865 struct ath9k_hw_capabilities *pCap = &ah->caps;
2866 2866
2867 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 2867 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2868 2868
@@ -2883,18 +2883,18 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2883 mask2 = 0; 2883 mask2 = 0;
2884 2884
2885 if (ints & ATH9K_INT_TX) { 2885 if (ints & ATH9K_INT_TX) {
2886 if (ah->ah_txOkInterruptMask) 2886 if (ah->txok_interrupt_mask)
2887 mask |= AR_IMR_TXOK; 2887 mask |= AR_IMR_TXOK;
2888 if (ah->ah_txDescInterruptMask) 2888 if (ah->txdesc_interrupt_mask)
2889 mask |= AR_IMR_TXDESC; 2889 mask |= AR_IMR_TXDESC;
2890 if (ah->ah_txErrInterruptMask) 2890 if (ah->txerr_interrupt_mask)
2891 mask |= AR_IMR_TXERR; 2891 mask |= AR_IMR_TXERR;
2892 if (ah->ah_txEolInterruptMask) 2892 if (ah->txeol_interrupt_mask)
2893 mask |= AR_IMR_TXEOL; 2893 mask |= AR_IMR_TXEOL;
2894 } 2894 }
2895 if (ints & ATH9K_INT_RX) { 2895 if (ints & ATH9K_INT_RX) {
2896 mask |= AR_IMR_RXERR; 2896 mask |= AR_IMR_RXERR;
2897 if (ah->ah_intrMitigation) 2897 if (ah->intr_mitigation)
2898 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 2898 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2899 else 2899 else
2900 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 2900 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
@@ -2932,7 +2932,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2932 AR_IMR_S2_TSFOOR | 2932 AR_IMR_S2_TSFOOR |
2933 AR_IMR_S2_GTT | AR_IMR_S2_CST); 2933 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2934 REG_WRITE(ah, AR_IMR_S2, mask | mask2); 2934 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2935 ah->ah_maskReg = ints; 2935 ah->mask_reg = ints;
2936 2936
2937 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2937 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2938 if (ints & ATH9K_INT_TIM_TIMER) 2938 if (ints & ATH9K_INT_TIM_TIMER)
@@ -2970,9 +2970,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2970{ 2970{
2971 int flags = 0; 2971 int flags = 0;
2972 2972
2973 ah->ah_beaconInterval = beacon_period; 2973 ah->beacon_interval = beacon_period;
2974 2974
2975 switch (ah->ah_opmode) { 2975 switch (ah->opmode) {
2976 case NL80211_IFTYPE_STATION: 2976 case NL80211_IFTYPE_STATION:
2977 case NL80211_IFTYPE_MONITOR: 2977 case NL80211_IFTYPE_MONITOR:
2978 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 2978 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
@@ -2985,18 +2985,18 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2985 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2985 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2986 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 2986 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2987 TU_TO_USEC(next_beacon + 2987 TU_TO_USEC(next_beacon +
2988 (ah->ah_atimWindow ? ah-> 2988 (ah->atim_window ? ah->
2989 ah_atimWindow : 1))); 2989 atim_window : 1)));
2990 flags |= AR_NDP_TIMER_EN; 2990 flags |= AR_NDP_TIMER_EN;
2991 case NL80211_IFTYPE_AP: 2991 case NL80211_IFTYPE_AP:
2992 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 2992 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2993 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 2993 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2994 TU_TO_USEC(next_beacon - 2994 TU_TO_USEC(next_beacon -
2995 ah->ah_config. 2995 ah->config.
2996 dma_beacon_response_time)); 2996 dma_beacon_response_time));
2997 REG_WRITE(ah, AR_NEXT_SWBA, 2997 REG_WRITE(ah, AR_NEXT_SWBA,
2998 TU_TO_USEC(next_beacon - 2998 TU_TO_USEC(next_beacon -
2999 ah->ah_config. 2999 ah->config.
3000 sw_beacon_response_time)); 3000 sw_beacon_response_time));
3001 flags |= 3001 flags |=
3002 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 3002 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
@@ -3004,7 +3004,7 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3004 default: 3004 default:
3005 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, 3005 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3006 "%s: unsupported opmode: %d\n", 3006 "%s: unsupported opmode: %d\n",
3007 __func__, ah->ah_opmode); 3007 __func__, ah->opmode);
3008 return; 3008 return;
3009 break; 3009 break;
3010 } 3010 }
@@ -3027,7 +3027,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3027 const struct ath9k_beacon_state *bs) 3027 const struct ath9k_beacon_state *bs)
3028{ 3028{
3029 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3029 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3030 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3030 struct ath9k_hw_capabilities *pCap = &ah->caps;
3031 3031
3032 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 3032 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3033 3033
@@ -3089,7 +3089,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3089 3089
3090bool ath9k_hw_fill_cap_info(struct ath_hw *ah) 3090bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3091{ 3091{
3092 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3092 struct ath9k_hw_capabilities *pCap = &ah->caps;
3093 u16 capField = 0, eeval; 3093 u16 capField = 0, eeval;
3094 3094
3095 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 3095 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
@@ -3101,7 +3101,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3101 3101
3102 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); 3102 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3103 3103
3104 if (ah->ah_opmode != NL80211_IFTYPE_AP && 3104 if (ah->opmode != NL80211_IFTYPE_AP &&
3105 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 3105 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3106 if (ah->regulatory.current_rd == 0x64 || 3106 if (ah->regulatory.current_rd == 0x64 ||
3107 ah->regulatory.current_rd == 0x65) 3107 ah->regulatory.current_rd == 0x65)
@@ -3117,7 +3117,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3117 3117
3118 if (eeval & AR5416_OPFLAGS_11A) { 3118 if (eeval & AR5416_OPFLAGS_11A) {
3119 set_bit(ATH9K_MODE_11A, pCap->wireless_modes); 3119 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3120 if (ah->ah_config.ht_enable) { 3120 if (ah->config.ht_enable) {
3121 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) 3121 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3122 set_bit(ATH9K_MODE_11NA_HT20, 3122 set_bit(ATH9K_MODE_11NA_HT20,
3123 pCap->wireless_modes); 3123 pCap->wireless_modes);
@@ -3133,7 +3133,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3133 if (eeval & AR5416_OPFLAGS_11G) { 3133 if (eeval & AR5416_OPFLAGS_11G) {
3134 set_bit(ATH9K_MODE_11B, pCap->wireless_modes); 3134 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3135 set_bit(ATH9K_MODE_11G, pCap->wireless_modes); 3135 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3136 if (ah->ah_config.ht_enable) { 3136 if (ah->config.ht_enable) {
3137 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) 3137 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3138 set_bit(ATH9K_MODE_11NG_HT20, 3138 set_bit(ATH9K_MODE_11NG_HT20,
3139 pCap->wireless_modes); 3139 pCap->wireless_modes);
@@ -3147,7 +3147,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3147 } 3147 }
3148 3148
3149 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 3149 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3150 if ((ah->ah_isPciExpress) 3150 if ((ah->is_pciexpress)
3151 || (eeval & AR5416_OPFLAGS_11A)) { 3151 || (eeval & AR5416_OPFLAGS_11A)) {
3152 pCap->rx_chainmask = 3152 pCap->rx_chainmask =
3153 ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 3153 ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
@@ -3157,7 +3157,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3157 } 3157 }
3158 3158
3159 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) 3159 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3160 ah->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; 3160 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3161 3161
3162 pCap->low_2ghz_chan = 2312; 3162 pCap->low_2ghz_chan = 2312;
3163 pCap->high_2ghz_chan = 2732; 3163 pCap->high_2ghz_chan = 2732;
@@ -3175,7 +3175,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3175 3175
3176 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD; 3176 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3177 3177
3178 if (ah->ah_config.ht_enable) 3178 if (ah->config.ht_enable)
3179 pCap->hw_caps |= ATH9K_HW_CAP_HT; 3179 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3180 else 3180 else
3181 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 3181 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
@@ -3226,12 +3226,12 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3226 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 3226 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3227 3227
3228#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 3228#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3229 ah->ah_rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 3229 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3230 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { 3230 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3231 ah->ah_rfkill_gpio = 3231 ah->rfkill_gpio =
3232 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); 3232 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3233 ah->ah_rfkill_polarity = 3233 ah->rfkill_polarity =
3234 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY); 3234 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3235 3235
3236 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 3236 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3237 } 3237 }
@@ -3272,8 +3272,8 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3272 3272
3273 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) { 3273 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3274 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX; 3274 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3275 ah->ah_btactive_gpio = 6; 3275 ah->btactive_gpio = 6;
3276 ah->ah_wlanactive_gpio = 5; 3276 ah->wlanactive_gpio = 5;
3277 } 3277 }
3278 3278
3279 return true; 3279 return true;
@@ -3282,7 +3282,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3282bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, 3282bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3283 u32 capability, u32 *result) 3283 u32 capability, u32 *result)
3284{ 3284{
3285 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3285 const struct ath9k_hw_capabilities *pCap = &ah->caps;
3286 3286
3287 switch (type) { 3287 switch (type) {
3288 case ATH9K_CAP_CIPHER: 3288 case ATH9K_CAP_CIPHER:
@@ -3302,17 +3302,17 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3302 case 0: 3302 case 0:
3303 return true; 3303 return true;
3304 case 1: 3304 case 1:
3305 return (ah->ah_staId1Defaults & 3305 return (ah->sta_id1_defaults &
3306 AR_STA_ID1_CRPT_MIC_ENABLE) ? true : 3306 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3307 false; 3307 false;
3308 } 3308 }
3309 case ATH9K_CAP_TKIP_SPLIT: 3309 case ATH9K_CAP_TKIP_SPLIT:
3310 return (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? 3310 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3311 false : true; 3311 false : true;
3312 case ATH9K_CAP_WME_TKIPMIC: 3312 case ATH9K_CAP_WME_TKIPMIC:
3313 return 0; 3313 return 0;
3314 case ATH9K_CAP_PHYCOUNTERS: 3314 case ATH9K_CAP_PHYCOUNTERS:
3315 return ah->ah_hasHwPhyCounters ? 0 : -ENXIO; 3315 return ah->has_hw_phycounters ? 0 : -ENXIO;
3316 case ATH9K_CAP_DIVERSITY: 3316 case ATH9K_CAP_DIVERSITY:
3317 return (REG_READ(ah, AR_PHY_CCK_DETECT) & 3317 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3318 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 3318 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
@@ -3327,14 +3327,14 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3327 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 3327 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3328 return false; 3328 return false;
3329 } else { 3329 } else {
3330 return (ah->ah_staId1Defaults & 3330 return (ah->sta_id1_defaults &
3331 AR_STA_ID1_MCAST_KSRCH) ? true : 3331 AR_STA_ID1_MCAST_KSRCH) ? true :
3332 false; 3332 false;
3333 } 3333 }
3334 } 3334 }
3335 return false; 3335 return false;
3336 case ATH9K_CAP_TSF_ADJUST: 3336 case ATH9K_CAP_TSF_ADJUST:
3337 return (ah->ah_miscMode & AR_PCU_TX_ADD_TSF) ? 3337 return (ah->misc_mode & AR_PCU_TX_ADD_TSF) ?
3338 true : false; 3338 true : false;
3339 case ATH9K_CAP_RFSILENT: 3339 case ATH9K_CAP_RFSILENT:
3340 if (capability == 3) 3340 if (capability == 3)
@@ -3373,10 +3373,10 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3373 switch (type) { 3373 switch (type) {
3374 case ATH9K_CAP_TKIP_MIC: 3374 case ATH9K_CAP_TKIP_MIC:
3375 if (setting) 3375 if (setting)
3376 ah->ah_staId1Defaults |= 3376 ah->sta_id1_defaults |=
3377 AR_STA_ID1_CRPT_MIC_ENABLE; 3377 AR_STA_ID1_CRPT_MIC_ENABLE;
3378 else 3378 else
3379 ah->ah_staId1Defaults &= 3379 ah->sta_id1_defaults &=
3380 ~AR_STA_ID1_CRPT_MIC_ENABLE; 3380 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3381 return true; 3381 return true;
3382 case ATH9K_CAP_DIVERSITY: 3382 case ATH9K_CAP_DIVERSITY:
@@ -3389,15 +3389,15 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3389 return true; 3389 return true;
3390 case ATH9K_CAP_MCAST_KEYSRCH: 3390 case ATH9K_CAP_MCAST_KEYSRCH:
3391 if (setting) 3391 if (setting)
3392 ah->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; 3392 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3393 else 3393 else
3394 ah->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; 3394 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3395 return true; 3395 return true;
3396 case ATH9K_CAP_TSF_ADJUST: 3396 case ATH9K_CAP_TSF_ADJUST:
3397 if (setting) 3397 if (setting)
3398 ah->ah_miscMode |= AR_PCU_TX_ADD_TSF; 3398 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3399 else 3399 else
3400 ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; 3400 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3401 return true; 3401 return true;
3402 default: 3402 default:
3403 return false; 3403 return false;
@@ -3440,7 +3440,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3440{ 3440{
3441 u32 gpio_shift; 3441 u32 gpio_shift;
3442 3442
3443 ASSERT(gpio < ah->ah_caps.num_gpio_pins); 3443 ASSERT(gpio < ah->caps.num_gpio_pins);
3444 3444
3445 gpio_shift = gpio << 1; 3445 gpio_shift = gpio << 1;
3446 3446
@@ -3455,7 +3455,7 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3455#define MS_REG_READ(x, y) \ 3455#define MS_REG_READ(x, y) \
3456 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 3456 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3457 3457
3458 if (gpio >= ah->ah_caps.num_gpio_pins) 3458 if (gpio >= ah->caps.num_gpio_pins)
3459 return 0xffffffff; 3459 return 0xffffffff;
3460 3460
3461 if (AR_SREV_9285_10_OR_LATER(ah)) 3461 if (AR_SREV_9285_10_OR_LATER(ah))
@@ -3496,7 +3496,7 @@ void ath9k_enable_rfkill(struct ath_hw *ah)
3496 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, 3496 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3497 AR_GPIO_INPUT_MUX2_RFSILENT); 3497 AR_GPIO_INPUT_MUX2_RFSILENT);
3498 3498
3499 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio); 3499 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3500 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 3500 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3501} 3501}
3502#endif 3502#endif
@@ -3534,7 +3534,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3534 *antenna_cfgd = true; 3534 *antenna_cfgd = true;
3535 break; 3535 break;
3536 case ATH9K_ANT_FIXED_B: 3536 case ATH9K_ANT_FIXED_B:
3537 if (ah->ah_caps.tx_chainmask > 3537 if (ah->caps.tx_chainmask >
3538 ATH9K_ANTENNA1_CHAINMASK) { 3538 ATH9K_ANTENNA1_CHAINMASK) {
3539 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK; 3539 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3540 } 3540 }
@@ -3550,7 +3550,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3550 break; 3550 break;
3551 } 3551 }
3552 } else { 3552 } else {
3553 ah->ah_diversityControl = settings; 3553 ah->diversity_control = settings;
3554 } 3554 }
3555 3555
3556 return true; 3556 return true;
@@ -3608,7 +3608,7 @@ bool ath9k_hw_disable(struct ath_hw *ah)
3608 3608
3609bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) 3609bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3610{ 3610{
3611 struct ath9k_channel *chan = ah->ah_curchan; 3611 struct ath9k_channel *chan = ah->curchan;
3612 struct ieee80211_channel *channel = chan->chan; 3612 struct ieee80211_channel *channel = chan->chan;
3613 3613
3614 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER); 3614 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
@@ -3631,7 +3631,7 @@ void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3631 3631
3632void ath9k_hw_setopmode(struct ath_hw *ah) 3632void ath9k_hw_setopmode(struct ath_hw *ah)
3633{ 3633{
3634 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); 3634 ath9k_hw_set_operating_mode(ah, ah->opmode);
3635} 3635}
3636 3636
3637void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 3637void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
@@ -3690,9 +3690,9 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
3690bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 3690bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3691{ 3691{
3692 if (setting) 3692 if (setting)
3693 ah->ah_miscMode |= AR_PCU_TX_ADD_TSF; 3693 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3694 else 3694 else
3695 ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; 3695 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3696 3696
3697 return true; 3697 return true;
3698} 3698}
@@ -3701,11 +3701,11 @@ bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3701{ 3701{
3702 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { 3702 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3703 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); 3703 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3704 ah->ah_slottime = (u32) -1; 3704 ah->slottime = (u32) -1;
3705 return false; 3705 return false;
3706 } else { 3706 } else {
3707 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); 3707 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3708 ah->ah_slottime = us; 3708 ah->slottime = us;
3709 return true; 3709 return true;
3710 } 3710 }
3711} 3711}
@@ -3715,7 +3715,7 @@ void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3715 u32 macmode; 3715 u32 macmode;
3716 3716
3717 if (mode == ATH9K_HT_MACMODE_2040 && 3717 if (mode == ATH9K_HT_MACMODE_2040 &&
3718 !ah->ah_config.cwm_ignore_extcca) 3718 !ah->config.cwm_ignore_extcca)
3719 macmode = AR_2040_JOINED_RX_CLEAR; 3719 macmode = AR_2040_JOINED_RX_CLEAR;
3720 else 3720 else
3721 macmode = 0; 3721 macmode = 0;
@@ -3740,12 +3740,12 @@ void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3740 /* Set input mux for bt_active to gpio pin */ 3740 /* Set input mux for bt_active to gpio pin */
3741 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, 3741 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3742 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 3742 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3743 ah->ah_btactive_gpio); 3743 ah->btactive_gpio);
3744 3744
3745 /* Configure the desired gpio port for input */ 3745 /* Configure the desired gpio port for input */
3746 ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio); 3746 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3747 3747
3748 /* Configure the desired GPIO port for TX_FRAME output */ 3748 /* Configure the desired GPIO port for TX_FRAME output */
3749 ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio, 3749 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3750 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 3750 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3751} 3751}
diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h
index f8f46db665c2..82111636c693 100644
--- a/drivers/net/wireless/ath9k/hw.h
+++ b/drivers/net/wireless/ath9k/hw.h
@@ -420,152 +420,148 @@ struct ath9k_hw_version {
420struct ath_hw { 420struct ath_hw {
421 struct ath_softc *ah_sc; 421 struct ath_softc *ah_sc;
422 struct ath9k_hw_version hw_version; 422 struct ath9k_hw_version hw_version;
423 struct ath9k_ops_config ah_config; 423 struct ath9k_ops_config config;
424 struct ath9k_hw_capabilities ah_caps; 424 struct ath9k_hw_capabilities caps;
425 struct ath9k_regulatory regulatory; 425 struct ath9k_regulatory regulatory;
426 struct ath9k_channel ah_channels[38]; 426 struct ath9k_channel channels[38];
427 struct ath9k_channel *ah_curchan; 427 struct ath9k_channel *curchan;
428 428
429 union { 429 union {
430 struct ar5416_eeprom_def def; 430 struct ar5416_eeprom_def def;
431 struct ar5416_eeprom_4k map4k; 431 struct ar5416_eeprom_4k map4k;
432 } ah_eeprom; 432 } eeprom;
433 const struct eeprom_ops *eep_ops; 433 const struct eeprom_ops *eep_ops;
434 enum ath9k_eep_map eep_map;
434 435
435 bool sw_mgmt_crypto; 436 bool sw_mgmt_crypto;
436 bool ah_isPciExpress; 437 bool is_pciexpress;
437 u8 macaddr[ETH_ALEN]; 438 u8 macaddr[ETH_ALEN];
438 u16 ah_txTrigLevel; 439 u16 tx_trig_level;
439 u16 ah_rfsilent; 440 u16 rfsilent;
440 u32 ah_rfkill_gpio; 441 u32 rfkill_gpio;
441 u32 ah_rfkill_polarity; 442 u32 rfkill_polarity;
442 u32 ah_btactive_gpio; 443 u32 btactive_gpio;
443 u32 ah_wlanactive_gpio; 444 u32 wlanactive_gpio;
444 u32 ah_flags; 445 u32 ah_flags;
445 enum nl80211_iftype ah_opmode;
446 446
447 enum ath9k_power_mode ah_power_mode; 447 enum nl80211_iftype opmode;
448 enum ath9k_power_mode ah_restore_mode; 448 enum ath9k_power_mode power_mode;
449 enum ath9k_power_mode restore_mode;
449 450
450 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 451 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
451 struct ar5416Stats ah_stats; 452 struct ar5416Stats stats;
452 struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES]; 453 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
453 454
454 int16_t ah_curchanRadIndex; 455 int16_t curchan_rad_index;
455 u32 ah_maskReg; 456 u32 mask_reg;
456 u32 ah_txOkInterruptMask; 457 u32 txok_interrupt_mask;
457 u32 ah_txErrInterruptMask; 458 u32 txerr_interrupt_mask;
458 u32 ah_txDescInterruptMask; 459 u32 txdesc_interrupt_mask;
459 u32 ah_txEolInterruptMask; 460 u32 txeol_interrupt_mask;
460 u32 ah_txUrnInterruptMask; 461 u32 txurn_interrupt_mask;
461 bool ah_chipFullSleep; 462 bool chip_fullsleep;
462 u32 ah_atimWindow; 463 u32 atim_window;
463 u16 ah_antennaSwitchSwap; 464 u16 antenna_switch_swap;
464 enum ath9k_ant_setting ah_diversityControl; 465 enum ath9k_ant_setting diversity_control;
465 466
466 /* Calibration */ 467 /* Calibration */
467 enum hal_cal_types ah_suppCals; 468 enum hal_cal_types supp_cals;
468 struct hal_cal_list ah_iqCalData; 469 struct hal_cal_list iq_caldata;
469 struct hal_cal_list ah_adcGainCalData; 470 struct hal_cal_list adcgain_caldata;
470 struct hal_cal_list ah_adcDcCalInitData; 471 struct hal_cal_list adcdc_calinitdata;
471 struct hal_cal_list ah_adcDcCalData; 472 struct hal_cal_list adcdc_caldata;
472 struct hal_cal_list *ah_cal_list; 473 struct hal_cal_list *cal_list;
473 struct hal_cal_list *ah_cal_list_last; 474 struct hal_cal_list *cal_list_last;
474 struct hal_cal_list *ah_cal_list_curr; 475 struct hal_cal_list *cal_list_curr;
475#define ah_totalPowerMeasI ah_Meas0.unsign 476#define totalPowerMeasI meas0.unsign
476#define ah_totalPowerMeasQ ah_Meas1.unsign 477#define totalPowerMeasQ meas1.unsign
477#define ah_totalIqCorrMeas ah_Meas2.sign 478#define totalIqCorrMeas meas2.sign
478#define ah_totalAdcIOddPhase ah_Meas0.unsign 479#define totalAdcIOddPhase meas0.unsign
479#define ah_totalAdcIEvenPhase ah_Meas1.unsign 480#define totalAdcIEvenPhase meas1.unsign
480#define ah_totalAdcQOddPhase ah_Meas2.unsign 481#define totalAdcQOddPhase meas2.unsign
481#define ah_totalAdcQEvenPhase ah_Meas3.unsign 482#define totalAdcQEvenPhase meas3.unsign
482#define ah_totalAdcDcOffsetIOddPhase ah_Meas0.sign 483#define totalAdcDcOffsetIOddPhase meas0.sign
483#define ah_totalAdcDcOffsetIEvenPhase ah_Meas1.sign 484#define totalAdcDcOffsetIEvenPhase meas1.sign
484#define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign 485#define totalAdcDcOffsetQOddPhase meas2.sign
485#define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign 486#define totalAdcDcOffsetQEvenPhase meas3.sign
486 union { 487 union {
487 u32 unsign[AR5416_MAX_CHAINS]; 488 u32 unsign[AR5416_MAX_CHAINS];
488 int32_t sign[AR5416_MAX_CHAINS]; 489 int32_t sign[AR5416_MAX_CHAINS];
489 } ah_Meas0; 490 } meas0;
490 union { 491 union {
491 u32 unsign[AR5416_MAX_CHAINS]; 492 u32 unsign[AR5416_MAX_CHAINS];
492 int32_t sign[AR5416_MAX_CHAINS]; 493 int32_t sign[AR5416_MAX_CHAINS];
493 } ah_Meas1; 494 } meas1;
494 union { 495 union {
495 u32 unsign[AR5416_MAX_CHAINS]; 496 u32 unsign[AR5416_MAX_CHAINS];
496 int32_t sign[AR5416_MAX_CHAINS]; 497 int32_t sign[AR5416_MAX_CHAINS];
497 } ah_Meas2; 498 } meas2;
498 union { 499 union {
499 u32 unsign[AR5416_MAX_CHAINS]; 500 u32 unsign[AR5416_MAX_CHAINS];
500 int32_t sign[AR5416_MAX_CHAINS]; 501 int32_t sign[AR5416_MAX_CHAINS];
501 } ah_Meas3; 502 } meas3;
502 u16 ah_CalSamples; 503 u16 cal_samples;
503 504
504 u32 ah_staId1Defaults; 505 u32 sta_id1_defaults;
505 u32 ah_miscMode; 506 u32 misc_mode;
506 enum { 507 enum {
507 AUTO_32KHZ, 508 AUTO_32KHZ,
508 USE_32KHZ, 509 USE_32KHZ,
509 DONT_USE_32KHZ, 510 DONT_USE_32KHZ,
510 } ah_enable32kHzClock; 511 } enable_32kHz_clock;
511 512
512 /* RF */ 513 /* RF */
513 u32 *ah_analogBank0Data; 514 u32 *analogBank0Data;
514 u32 *ah_analogBank1Data; 515 u32 *analogBank1Data;
515 u32 *ah_analogBank2Data; 516 u32 *analogBank2Data;
516 u32 *ah_analogBank3Data; 517 u32 *analogBank3Data;
517 u32 *ah_analogBank6Data; 518 u32 *analogBank6Data;
518 u32 *ah_analogBank6TPCData; 519 u32 *analogBank6TPCData;
519 u32 *ah_analogBank7Data; 520 u32 *analogBank7Data;
520 u32 *ah_addac5416_21; 521 u32 *addac5416_21;
521 u32 *ah_bank6Temp; 522 u32 *bank6Temp;
522 523
523 int16_t ah_txPowerIndexOffset; 524 int16_t txpower_indexoffset;
524 u32 ah_beaconInterval; 525 u32 beacon_interval;
525 u32 ah_slottime; 526 u32 slottime;
526 u32 ah_acktimeout; 527 u32 acktimeout;
527 u32 ah_ctstimeout; 528 u32 ctstimeout;
528 u32 ah_globaltxtimeout; 529 u32 globaltxtimeout;
529 u8 ah_gBeaconRate; 530 u8 gbeacon_rate;
530 u32 ah_gpioSelect;
531 u32 ah_polarity;
532 u32 ah_gpioBit;
533 531
534 /* ANI */ 532 /* ANI */
535 u32 ah_procPhyErr; 533 u32 proc_phyerr;
536 bool ah_hasHwPhyCounters; 534 bool has_hw_phycounters;
537 u32 ah_aniPeriod; 535 u32 aniperiod;
538 struct ar5416AniState *ah_curani; 536 struct ar5416AniState *curani;
539 struct ar5416AniState ah_ani[255]; 537 struct ar5416AniState ani[255];
540 int ah_totalSizeDesired[5]; 538 int totalSizeDesired[5];
541 int ah_coarseHigh[5]; 539 int coarse_high[5];
542 int ah_coarseLow[5]; 540 int coarse_low[5];
543 int ah_firpwr[5]; 541 int firpwr[5];
544 enum ath9k_ani_cmd ah_ani_function; 542 enum ath9k_ani_cmd ani_function;
545 543
546 u32 ah_intrTxqs; 544 u32 intr_txqs;
547 bool ah_intrMitigation; 545 bool intr_mitigation;
548 enum ath9k_ht_extprotspacing ah_extprotspacing; 546 enum ath9k_ht_extprotspacing extprotspacing;
549 u8 ah_txchainmask; 547 u8 txchainmask;
550 u8 ah_rxchainmask; 548 u8 rxchainmask;
551 549
552 struct ar5416IniArray ah_iniModes; 550 struct ar5416IniArray iniModes;
553 struct ar5416IniArray ah_iniCommon; 551 struct ar5416IniArray iniCommon;
554 struct ar5416IniArray ah_iniBank0; 552 struct ar5416IniArray iniBank0;
555 struct ar5416IniArray ah_iniBB_RfGain; 553 struct ar5416IniArray iniBB_RfGain;
556 struct ar5416IniArray ah_iniBank1; 554 struct ar5416IniArray iniBank1;
557 struct ar5416IniArray ah_iniBank2; 555 struct ar5416IniArray iniBank2;
558 struct ar5416IniArray ah_iniBank3; 556 struct ar5416IniArray iniBank3;
559 struct ar5416IniArray ah_iniBank6; 557 struct ar5416IniArray iniBank6;
560 struct ar5416IniArray ah_iniBank6TPC; 558 struct ar5416IniArray iniBank6TPC;
561 struct ar5416IniArray ah_iniBank7; 559 struct ar5416IniArray iniBank7;
562 struct ar5416IniArray ah_iniAddac; 560 struct ar5416IniArray iniAddac;
563 struct ar5416IniArray ah_iniPcieSerdes; 561 struct ar5416IniArray iniPcieSerdes;
564 struct ar5416IniArray ah_iniModesAdditional; 562 struct ar5416IniArray iniModesAdditional;
565 struct ar5416IniArray ah_iniModesRxGain; 563 struct ar5416IniArray iniModesRxGain;
566 struct ar5416IniArray ah_iniModesTxGain; 564 struct ar5416IniArray iniModesTxGain;
567 /* To indicate EEPROM mapping used */
568 enum hal_eep_map ah_eep_map;
569}; 565};
570 566
571/* Attach, Detach, Reset */ 567/* Attach, Detach, Reset */
diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c
index ac2071444017..f32c622db6e7 100644
--- a/drivers/net/wireless/ath9k/mac.c
+++ b/drivers/net/wireless/ath9k/mac.c
@@ -21,18 +21,18 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
21{ 21{
22 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 22 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", 23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
24 ah->ah_txOkInterruptMask, ah->ah_txErrInterruptMask, 24 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
25 ah->ah_txDescInterruptMask, ah->ah_txEolInterruptMask, 25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
26 ah->ah_txUrnInterruptMask); 26 ah->txurn_interrupt_mask);
27 27
28 REG_WRITE(ah, AR_IMR_S0, 28 REG_WRITE(ah, AR_IMR_S0,
29 SM(ah->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) 29 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
30 | SM(ah->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)); 30 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
31 REG_WRITE(ah, AR_IMR_S1, 31 REG_WRITE(ah, AR_IMR_S1,
32 SM(ah->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) 32 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
33 | SM(ah->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)); 33 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
34 REG_RMW_FIELD(ah, AR_IMR_S2, 34 REG_RMW_FIELD(ah, AR_IMR_S2,
35 AR_IMR_S2_QCU_TXURN, ah->ah_txUrnInterruptMask); 35 AR_IMR_S2_QCU_TXURN, ah->txurn_interrupt_mask);
36} 36}
37 37
38u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) 38u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
@@ -75,10 +75,10 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
75 u32 txcfg, curLevel, newLevel; 75 u32 txcfg, curLevel, newLevel;
76 enum ath9k_int omask; 76 enum ath9k_int omask;
77 77
78 if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD) 78 if (ah->tx_trig_level >= MAX_TX_FIFO_THRESHOLD)
79 return false; 79 return false;
80 80
81 omask = ath9k_hw_set_interrupts(ah, ah->ah_maskReg & ~ATH9K_INT_GLOBAL); 81 omask = ath9k_hw_set_interrupts(ah, ah->mask_reg & ~ATH9K_INT_GLOBAL);
82 82
83 txcfg = REG_READ(ah, AR_TXCFG); 83 txcfg = REG_READ(ah, AR_TXCFG);
84 curLevel = MS(txcfg, AR_FTRIG); 84 curLevel = MS(txcfg, AR_FTRIG);
@@ -94,7 +94,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
94 94
95 ath9k_hw_set_interrupts(ah, omask); 95 ath9k_hw_set_interrupts(ah, omask);
96 96
97 ah->ah_txTrigLevel = newLevel; 97 ah->tx_trig_level = newLevel;
98 98
99 return newLevel != curLevel; 99 return newLevel != curLevel;
100} 100}
@@ -104,7 +104,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
104#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 104#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
105#define ATH9K_TIME_QUANTUM 100 /* usec */ 105#define ATH9K_TIME_QUANTUM 100 /* usec */
106 106
107 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 107 struct ath9k_hw_capabilities *pCap = &ah->caps;
108 struct ath9k_tx_queue_info *qi; 108 struct ath9k_tx_queue_info *qi;
109 u32 tsfLow, j, wait; 109 u32 tsfLow, j, wait;
110 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; 110 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
@@ -114,7 +114,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
114 return false; 114 return false;
115 } 115 }
116 116
117 qi = &ah->ah_txq[q]; 117 qi = &ah->txq[q];
118 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 118 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
119 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); 119 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
120 return false; 120 return false;
@@ -296,7 +296,7 @@ void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
296{ 296{
297 struct ar5416_desc *ads = AR5416DESC(ds); 297 struct ar5416_desc *ads = AR5416DESC(ds);
298 298
299 txPower += ah->ah_txPowerIndexOffset; 299 txPower += ah->txpower_indexoffset;
300 if (txPower > 63) 300 if (txPower > 63)
301 txPower = 63; 301 txPower = 63;
302 302
@@ -442,15 +442,15 @@ void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
442 442
443void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs) 443void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
444{ 444{
445 *txqs &= ah->ah_intrTxqs; 445 *txqs &= ah->intr_txqs;
446 ah->ah_intrTxqs &= ~(*txqs); 446 ah->intr_txqs &= ~(*txqs);
447} 447}
448 448
449bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 449bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
450 const struct ath9k_tx_queue_info *qinfo) 450 const struct ath9k_tx_queue_info *qinfo)
451{ 451{
452 u32 cw; 452 u32 cw;
453 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 453 struct ath9k_hw_capabilities *pCap = &ah->caps;
454 struct ath9k_tx_queue_info *qi; 454 struct ath9k_tx_queue_info *qi;
455 455
456 if (q >= pCap->total_queues) { 456 if (q >= pCap->total_queues) {
@@ -458,7 +458,7 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
458 return false; 458 return false;
459 } 459 }
460 460
461 qi = &ah->ah_txq[q]; 461 qi = &ah->txq[q];
462 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 462 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
463 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); 463 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
464 return false; 464 return false;
@@ -517,7 +517,7 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
517bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 517bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
518 struct ath9k_tx_queue_info *qinfo) 518 struct ath9k_tx_queue_info *qinfo)
519{ 519{
520 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 520 struct ath9k_hw_capabilities *pCap = &ah->caps;
521 struct ath9k_tx_queue_info *qi; 521 struct ath9k_tx_queue_info *qi;
522 522
523 if (q >= pCap->total_queues) { 523 if (q >= pCap->total_queues) {
@@ -525,7 +525,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
525 return false; 525 return false;
526 } 526 }
527 527
528 qi = &ah->ah_txq[q]; 528 qi = &ah->txq[q];
529 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 529 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
530 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); 530 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
531 return false; 531 return false;
@@ -553,7 +553,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
553 const struct ath9k_tx_queue_info *qinfo) 553 const struct ath9k_tx_queue_info *qinfo)
554{ 554{
555 struct ath9k_tx_queue_info *qi; 555 struct ath9k_tx_queue_info *qi;
556 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 556 struct ath9k_hw_capabilities *pCap = &ah->caps;
557 int q; 557 int q;
558 558
559 switch (type) { 559 switch (type) {
@@ -571,7 +571,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
571 break; 571 break;
572 case ATH9K_TX_QUEUE_DATA: 572 case ATH9K_TX_QUEUE_DATA:
573 for (q = 0; q < pCap->total_queues; q++) 573 for (q = 0; q < pCap->total_queues; q++)
574 if (ah->ah_txq[q].tqi_type == 574 if (ah->txq[q].tqi_type ==
575 ATH9K_TX_QUEUE_INACTIVE) 575 ATH9K_TX_QUEUE_INACTIVE)
576 break; 576 break;
577 if (q == pCap->total_queues) { 577 if (q == pCap->total_queues) {
@@ -587,7 +587,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
587 587
588 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); 588 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q);
589 589
590 qi = &ah->ah_txq[q]; 590 qi = &ah->txq[q];
591 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 591 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
592 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 592 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
593 "tx queue %u already active\n", q); 593 "tx queue %u already active\n", q);
@@ -616,14 +616,14 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
616 616
617bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) 617bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
618{ 618{
619 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 619 struct ath9k_hw_capabilities *pCap = &ah->caps;
620 struct ath9k_tx_queue_info *qi; 620 struct ath9k_tx_queue_info *qi;
621 621
622 if (q >= pCap->total_queues) { 622 if (q >= pCap->total_queues) {
623 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); 623 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
624 return false; 624 return false;
625 } 625 }
626 qi = &ah->ah_txq[q]; 626 qi = &ah->txq[q];
627 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 627 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
628 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); 628 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
629 return false; 629 return false;
@@ -632,11 +632,11 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
632 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q); 632 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q);
633 633
634 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 634 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
635 ah->ah_txOkInterruptMask &= ~(1 << q); 635 ah->txok_interrupt_mask &= ~(1 << q);
636 ah->ah_txErrInterruptMask &= ~(1 << q); 636 ah->txerr_interrupt_mask &= ~(1 << q);
637 ah->ah_txDescInterruptMask &= ~(1 << q); 637 ah->txdesc_interrupt_mask &= ~(1 << q);
638 ah->ah_txEolInterruptMask &= ~(1 << q); 638 ah->txeol_interrupt_mask &= ~(1 << q);
639 ah->ah_txUrnInterruptMask &= ~(1 << q); 639 ah->txurn_interrupt_mask &= ~(1 << q);
640 ath9k_hw_set_txq_interrupts(ah, qi); 640 ath9k_hw_set_txq_interrupts(ah, qi);
641 641
642 return true; 642 return true;
@@ -644,8 +644,8 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
644 644
645bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) 645bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
646{ 646{
647 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 647 struct ath9k_hw_capabilities *pCap = &ah->caps;
648 struct ath9k_channel *chan = ah->ah_curchan; 648 struct ath9k_channel *chan = ah->curchan;
649 struct ath9k_tx_queue_info *qi; 649 struct ath9k_tx_queue_info *qi;
650 u32 cwMin, chanCwMin, value; 650 u32 cwMin, chanCwMin, value;
651 651
@@ -654,7 +654,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
654 return false; 654 return false;
655 } 655 }
656 656
657 qi = &ah->ah_txq[q]; 657 qi = &ah->txq[q];
658 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 658 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
659 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); 659 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
660 return true; 660 return true;
@@ -742,9 +742,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
742 | AR_Q_MISC_CBR_INCR_DIS1 742 | AR_Q_MISC_CBR_INCR_DIS1
743 | AR_Q_MISC_CBR_INCR_DIS0); 743 | AR_Q_MISC_CBR_INCR_DIS0);
744 value = (qi->tqi_readyTime - 744 value = (qi->tqi_readyTime -
745 (ah->ah_config.sw_beacon_response_time - 745 (ah->config.sw_beacon_response_time -
746 ah->ah_config.dma_beacon_response_time) - 746 ah->config.dma_beacon_response_time) -
747 ah->ah_config.additional_swba_backoff) * 1024; 747 ah->config.additional_swba_backoff) * 1024;
748 REG_WRITE(ah, AR_QRDYTIMECFG(q), 748 REG_WRITE(ah, AR_QRDYTIMECFG(q),
749 value | AR_Q_RDYTIMECFG_EN); 749 value | AR_Q_RDYTIMECFG_EN);
750 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) 750 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
@@ -772,25 +772,25 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
772 } 772 }
773 773
774 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) 774 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
775 ah->ah_txOkInterruptMask |= 1 << q; 775 ah->txok_interrupt_mask |= 1 << q;
776 else 776 else
777 ah->ah_txOkInterruptMask &= ~(1 << q); 777 ah->txok_interrupt_mask &= ~(1 << q);
778 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) 778 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
779 ah->ah_txErrInterruptMask |= 1 << q; 779 ah->txerr_interrupt_mask |= 1 << q;
780 else 780 else
781 ah->ah_txErrInterruptMask &= ~(1 << q); 781 ah->txerr_interrupt_mask &= ~(1 << q);
782 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) 782 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
783 ah->ah_txDescInterruptMask |= 1 << q; 783 ah->txdesc_interrupt_mask |= 1 << q;
784 else 784 else
785 ah->ah_txDescInterruptMask &= ~(1 << q); 785 ah->txdesc_interrupt_mask &= ~(1 << q);
786 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) 786 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
787 ah->ah_txEolInterruptMask |= 1 << q; 787 ah->txeol_interrupt_mask |= 1 << q;
788 else 788 else
789 ah->ah_txEolInterruptMask &= ~(1 << q); 789 ah->txeol_interrupt_mask &= ~(1 << q);
790 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) 790 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
791 ah->ah_txUrnInterruptMask |= 1 << q; 791 ah->txurn_interrupt_mask |= 1 << q;
792 else 792 else
793 ah->ah_txUrnInterruptMask &= ~(1 << q); 793 ah->txurn_interrupt_mask &= ~(1 << q);
794 ath9k_hw_set_txq_interrupts(ah, qi); 794 ath9k_hw_set_txq_interrupts(ah, qi);
795 795
796 return true; 796 return true;
@@ -865,7 +865,7 @@ bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
865 u32 size, u32 flags) 865 u32 size, u32 flags)
866{ 866{
867 struct ar5416_desc *ads = AR5416DESC(ds); 867 struct ar5416_desc *ads = AR5416DESC(ds);
868 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 868 struct ath9k_hw_capabilities *pCap = &ah->caps;
869 869
870 ads->ds_ctl1 = size & AR_BufLen; 870 ads->ds_ctl1 = size & AR_BufLen;
871 if (flags & ATH9K_RXDESC_INTREQ) 871 if (flags & ATH9K_RXDESC_INTREQ)
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index a50f989abd6c..fc3460f8f7fc 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -267,7 +267,7 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
267 267
268 DPRINTF(sc, ATH_DBG_CONFIG, 268 DPRINTF(sc, ATH_DBG_CONFIG,
269 "(%u MHz) -> (%u MHz), chanwidth: %d\n", 269 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
270 sc->sc_ah->ah_curchan->channel, 270 sc->sc_ah->curchan->channel,
271 channel->center_freq, sc->tx_chan_width); 271 channel->center_freq, sc->tx_chan_width);
272 272
273 spin_lock_bh(&sc->sc_resetlock); 273 spin_lock_bh(&sc->sc_resetlock);
@@ -363,30 +363,30 @@ static void ath_ani_calibrate(unsigned long data)
363 /* Call ANI routine if necessary */ 363 /* Call ANI routine if necessary */
364 if (aniflag) 364 if (aniflag)
365 ath9k_hw_ani_monitor(ah, &sc->nodestats, 365 ath9k_hw_ani_monitor(ah, &sc->nodestats,
366 ah->ah_curchan); 366 ah->curchan);
367 367
368 /* Perform calibration if necessary */ 368 /* Perform calibration if necessary */
369 if (longcal || shortcal) { 369 if (longcal || shortcal) {
370 bool iscaldone = false; 370 bool iscaldone = false;
371 371
372 if (ath9k_hw_calibrate(ah, ah->ah_curchan, 372 if (ath9k_hw_calibrate(ah, ah->curchan,
373 sc->rx_chainmask, longcal, 373 sc->rx_chainmask, longcal,
374 &iscaldone)) { 374 &iscaldone)) {
375 if (longcal) 375 if (longcal)
376 sc->ani.noise_floor = 376 sc->ani.noise_floor =
377 ath9k_hw_getchan_noise(ah, 377 ath9k_hw_getchan_noise(ah,
378 ah->ah_curchan); 378 ah->curchan);
379 379
380 DPRINTF(sc, ATH_DBG_ANI, 380 DPRINTF(sc, ATH_DBG_ANI,
381 "calibrate chan %u/%x nf: %d\n", 381 "calibrate chan %u/%x nf: %d\n",
382 ah->ah_curchan->channel, 382 ah->curchan->channel,
383 ah->ah_curchan->channelFlags, 383 ah->curchan->channelFlags,
384 sc->ani.noise_floor); 384 sc->ani.noise_floor);
385 } else { 385 } else {
386 DPRINTF(sc, ATH_DBG_ANY, 386 DPRINTF(sc, ATH_DBG_ANY,
387 "calibrate chan %u/%x failed\n", 387 "calibrate chan %u/%x failed\n",
388 ah->ah_curchan->channel, 388 ah->curchan->channel,
389 ah->ah_curchan->channelFlags); 389 ah->curchan->channelFlags);
390 } 390 }
391 sc->ani.caldone = iscaldone; 391 sc->ani.caldone = iscaldone;
392 } 392 }
@@ -398,7 +398,7 @@ static void ath_ani_calibrate(unsigned long data)
398 * short calibration and long calibration. 398 * short calibration and long calibration.
399 */ 399 */
400 cal_interval = ATH_LONG_CALINTERVAL; 400 cal_interval = ATH_LONG_CALINTERVAL;
401 if (sc->sc_ah->ah_config.enable_ani) 401 if (sc->sc_ah->config.enable_ani)
402 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); 402 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
403 if (!sc->ani.caldone) 403 if (!sc->ani.caldone)
404 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL); 404 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
@@ -416,9 +416,9 @@ static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
416{ 416{
417 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE; 417 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
418 if (is_ht || 418 if (is_ht ||
419 (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { 419 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask; 420 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421 sc->rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask; 421 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
422 } else { 422 } else {
423 sc->tx_chainmask = 1; 423 sc->tx_chainmask = 1;
424 sc->rx_chainmask = 1; 424 sc->rx_chainmask = 1;
@@ -564,7 +564,7 @@ irqreturn_t ath_isr(int irq, void *dev)
564 ath9k_hw_set_interrupts(ah, sc->imask); 564 ath9k_hw_set_interrupts(ah, sc->imask);
565 } 565 }
566 if (status & ATH9K_INT_TIM_TIMER) { 566 if (status & ATH9K_INT_TIM_TIMER) {
567 if (!(ah->ah_caps.hw_caps & 567 if (!(ah->caps.hw_caps &
568 ATH9K_HW_CAP_AUTOSLEEP)) { 568 ATH9K_HW_CAP_AUTOSLEEP)) {
569 /* Clear RxAbort bit so that we can 569 /* Clear RxAbort bit so that we can
570 * receive frames */ 570 * receive frames */
@@ -1098,7 +1098,7 @@ static void ath_radio_enable(struct ath_softc *sc)
1098 ath9k_ps_wakeup(sc); 1098 ath9k_ps_wakeup(sc);
1099 spin_lock_bh(&sc->sc_resetlock); 1099 spin_lock_bh(&sc->sc_resetlock);
1100 1100
1101 r = ath9k_hw_reset(ah, ah->ah_curchan, false); 1101 r = ath9k_hw_reset(ah, ah->curchan, false);
1102 1102
1103 if (r) { 1103 if (r) {
1104 DPRINTF(sc, ATH_DBG_FATAL, 1104 DPRINTF(sc, ATH_DBG_FATAL,
@@ -1151,7 +1151,7 @@ static void ath_radio_disable(struct ath_softc *sc)
1151 ath_flushrecv(sc); /* flush recv queue */ 1151 ath_flushrecv(sc); /* flush recv queue */
1152 1152
1153 spin_lock_bh(&sc->sc_resetlock); 1153 spin_lock_bh(&sc->sc_resetlock);
1154 r = ath9k_hw_reset(ah, ah->ah_curchan, false); 1154 r = ath9k_hw_reset(ah, ah->curchan, false);
1155 if (r) { 1155 if (r) {
1156 DPRINTF(sc, ATH_DBG_FATAL, 1156 DPRINTF(sc, ATH_DBG_FATAL,
1157 "Unable to reset channel %u (%uMhz) " 1157 "Unable to reset channel %u (%uMhz) "
@@ -1169,8 +1169,8 @@ static bool ath_is_rfkill_set(struct ath_softc *sc)
1169{ 1169{
1170 struct ath_hw *ah = sc->sc_ah; 1170 struct ath_hw *ah = sc->sc_ah;
1171 1171
1172 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) == 1172 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1173 ah->ah_rfkill_polarity; 1173 ah->rfkill_polarity;
1174} 1174}
1175 1175
1176/* h/w rfkill poll function */ 1176/* h/w rfkill poll function */
@@ -1267,7 +1267,7 @@ static int ath_init_sw_rfkill(struct ath_softc *sc)
1267/* Deinitialize rfkill */ 1267/* Deinitialize rfkill */
1268static void ath_deinit_rfkill(struct ath_softc *sc) 1268static void ath_deinit_rfkill(struct ath_softc *sc)
1269{ 1269{
1270 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1270 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1271 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); 1271 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1272 1272
1273 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) { 1273 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
@@ -1279,7 +1279,7 @@ static void ath_deinit_rfkill(struct ath_softc *sc)
1279 1279
1280static int ath_start_rfkill_poll(struct ath_softc *sc) 1280static int ath_start_rfkill_poll(struct ath_softc *sc)
1281{ 1281{
1282 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1282 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1283 queue_delayed_work(sc->hw->workqueue, 1283 queue_delayed_work(sc->hw->workqueue,
1284 &sc->rf_kill.rfkill_poll, 0); 1284 &sc->rf_kill.rfkill_poll, 0);
1285 1285
@@ -1380,7 +1380,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1380 sc->sc_ah = ah; 1380 sc->sc_ah = ah;
1381 1381
1382 /* Get the hardware key cache size. */ 1382 /* Get the hardware key cache size. */
1383 sc->keymax = ah->ah_caps.keycache_size; 1383 sc->keymax = ah->caps.keycache_size;
1384 if (sc->keymax > ATH_KEYMAX) { 1384 if (sc->keymax > ATH_KEYMAX) {
1385 DPRINTF(sc, ATH_DBG_KEYCACHE, 1385 DPRINTF(sc, ATH_DBG_KEYCACHE,
1386 "Warning, using only %u entries in %u key cache\n", 1386 "Warning, using only %u entries in %u key cache\n",
@@ -1399,7 +1399,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1399 goto bad; 1399 goto bad;
1400 1400
1401 /* default to MONITOR mode */ 1401 /* default to MONITOR mode */
1402 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR; 1402 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1403 1403
1404 /* Setup rate tables */ 1404 /* Setup rate tables */
1405 1405
@@ -1502,18 +1502,18 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1502 sc->config.txpowlimit = ATH_TXPOWER_MAX; 1502 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1503 1503
1504 /* 11n Capabilities */ 1504 /* 11n Capabilities */
1505 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { 1505 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1506 sc->sc_flags |= SC_OP_TXAGGR; 1506 sc->sc_flags |= SC_OP_TXAGGR;
1507 sc->sc_flags |= SC_OP_RXAGGR; 1507 sc->sc_flags |= SC_OP_RXAGGR;
1508 } 1508 }
1509 1509
1510 sc->tx_chainmask = ah->ah_caps.tx_chainmask; 1510 sc->tx_chainmask = ah->caps.tx_chainmask;
1511 sc->rx_chainmask = ah->ah_caps.rx_chainmask; 1511 sc->rx_chainmask = ah->caps.rx_chainmask;
1512 1512
1513 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); 1513 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1514 sc->rx.defant = ath9k_hw_getdefantenna(ah); 1514 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1515 1515
1516 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { 1516 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1517 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); 1517 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1518 ATH_SET_VIF_BSSID_MASK(sc->bssidmask); 1518 ATH_SET_VIF_BSSID_MASK(sc->bssidmask);
1519 ath9k_hw_setbssidmask(sc); 1519 ath9k_hw_setbssidmask(sc);
@@ -1537,7 +1537,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1537 sc->sbands[IEEE80211_BAND_2GHZ].n_channels = 1537 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1538 ARRAY_SIZE(ath9k_2ghz_chantable); 1538 ARRAY_SIZE(ath9k_2ghz_chantable);
1539 1539
1540 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) { 1540 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1541 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable; 1541 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1542 sc->sbands[IEEE80211_BAND_5GHZ].bitrates = 1542 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1543 sc->rates[IEEE80211_BAND_5GHZ]; 1543 sc->rates[IEEE80211_BAND_5GHZ];
@@ -1546,7 +1546,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1546 ARRAY_SIZE(ath9k_5ghz_chantable); 1546 ARRAY_SIZE(ath9k_5ghz_chantable);
1547 } 1547 }
1548 1548
1549 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX) 1549 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1550 ath9k_hw_btcoex_enable(sc->sc_ah); 1550 ath9k_hw_btcoex_enable(sc->sc_ah);
1551 1551
1552 return 0; 1552 return 0;
@@ -1603,14 +1603,14 @@ int ath_attach(u16 devid, struct ath_softc *sc)
1603 1603
1604 hw->rate_control_algorithm = "ath9k_rate_control"; 1604 hw->rate_control_algorithm = "ath9k_rate_control";
1605 1605
1606 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { 1606 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1607 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); 1607 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1608 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) 1608 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1609 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); 1609 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1610 } 1610 }
1611 1611
1612 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ]; 1612 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1613 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) 1613 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1614 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 1614 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1615 &sc->sbands[IEEE80211_BAND_5GHZ]; 1615 &sc->sbands[IEEE80211_BAND_5GHZ];
1616 1616
@@ -1625,7 +1625,7 @@ int ath_attach(u16 devid, struct ath_softc *sc)
1625 1625
1626#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 1626#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1627 /* Initialze h/w Rfkill */ 1627 /* Initialze h/w Rfkill */
1628 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1628 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1629 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll); 1629 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1630 1630
1631 /* Initialize s/w rfkill */ 1631 /* Initialize s/w rfkill */
@@ -1681,7 +1681,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1681 ath_flushrecv(sc); 1681 ath_flushrecv(sc);
1682 1682
1683 spin_lock_bh(&sc->sc_resetlock); 1683 spin_lock_bh(&sc->sc_resetlock);
1684 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false); 1684 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1685 if (r) 1685 if (r)
1686 DPRINTF(sc, ATH_DBG_FATAL, 1686 DPRINTF(sc, ATH_DBG_FATAL,
1687 "Unable to reset hardware; reset status %u\n", r); 1687 "Unable to reset hardware; reset status %u\n", r);
@@ -1755,7 +1755,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1755 * descriptors that cross the 4K page boundary. Assume 1755 * descriptors that cross the 4K page boundary. Assume
1756 * one skipped descriptor per 4K page. 1756 * one skipped descriptor per 4K page.
1757 */ 1757 */
1758 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 1758 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1759 u32 ndesc_skipped = 1759 u32 ndesc_skipped =
1760 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 1760 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1761 u32 dma_len; 1761 u32 dma_len;
@@ -1795,7 +1795,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1795 bf->bf_desc = ds; 1795 bf->bf_desc = ds;
1796 bf->bf_daddr = DS2PHYS(dd, ds); 1796 bf->bf_daddr = DS2PHYS(dd, ds);
1797 1797
1798 if (!(sc->sc_ah->ah_caps.hw_caps & 1798 if (!(sc->sc_ah->caps.hw_caps &
1799 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 1799 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1800 /* 1800 /*
1801 * Skip descriptor addresses which can cause 4KB 1801 * Skip descriptor addresses which can cause 4KB
@@ -1939,7 +1939,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1939 1939
1940 pos = curchan->hw_value; 1940 pos = curchan->hw_value;
1941 1941
1942 init_channel = &sc->sc_ah->ah_channels[pos]; 1942 init_channel = &sc->sc_ah->channels[pos];
1943 ath9k_update_ichannel(sc, init_channel); 1943 ath9k_update_ichannel(sc, init_channel);
1944 1944
1945 /* Reset SERDES registers */ 1945 /* Reset SERDES registers */
@@ -1989,10 +1989,10 @@ static int ath9k_start(struct ieee80211_hw *hw)
1989 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN 1989 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1990 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; 1990 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1991 1991
1992 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT) 1992 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1993 sc->imask |= ATH9K_INT_GTT; 1993 sc->imask |= ATH9K_INT_GTT;
1994 1994
1995 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) 1995 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1996 sc->imask |= ATH9K_INT_CST; 1996 sc->imask |= ATH9K_INT_CST;
1997 1997
1998 ath_cache_conf_rate(sc, &hw->conf); 1998 ath_cache_conf_rate(sc, &hw->conf);
@@ -2092,7 +2092,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2092 sc->rx.rxlink = NULL; 2092 sc->rx.rxlink = NULL;
2093 2093
2094#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2094#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2095 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2095 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2096 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); 2096 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2097#endif 2097#endif
2098 /* disable HAL and put h/w to sleep */ 2098 /* disable HAL and put h/w to sleep */
@@ -2149,7 +2149,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2149 sc->nvifs++; 2149 sc->nvifs++;
2150 2150
2151 /* Set the device opmode */ 2151 /* Set the device opmode */
2152 sc->sc_ah->ah_opmode = ic_opmode; 2152 sc->sc_ah->opmode = ic_opmode;
2153 2153
2154 /* 2154 /*
2155 * Enable MIB interrupts when there are hardware phy counters. 2155 * Enable MIB interrupts when there are hardware phy counters.
@@ -2165,7 +2165,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2165 * that does, if not overridden by configuration, 2165 * that does, if not overridden by configuration,
2166 * enable the TIM interrupt when operating as station. 2166 * enable the TIM interrupt when operating as station.
2167 */ 2167 */
2168 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) && 2168 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2169 (conf->type == NL80211_IFTYPE_STATION) && 2169 (conf->type == NL80211_IFTYPE_STATION) &&
2170 !sc->config.swBeaconProcess) 2170 !sc->config.swBeaconProcess)
2171 sc->imask |= ATH9K_INT_TIM; 2171 sc->imask |= ATH9K_INT_TIM;
@@ -2198,8 +2198,8 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
2198 del_timer_sync(&sc->ani.timer); 2198 del_timer_sync(&sc->ani.timer);
2199 2199
2200 /* Reclaim beacon resources */ 2200 /* Reclaim beacon resources */
2201 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || 2201 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2202 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { 2202 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
2203 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 2203 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2204 ath_beacon_return(sc, avp); 2204 ath_beacon_return(sc, avp);
2205 } 2205 }
@@ -2248,11 +2248,11 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2248 curchan->center_freq); 2248 curchan->center_freq);
2249 2249
2250 /* XXX: remove me eventualy */ 2250 /* XXX: remove me eventualy */
2251 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]); 2251 ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]);
2252 2252
2253 ath_update_chainmask(sc, conf_is_ht(conf)); 2253 ath_update_chainmask(sc, conf_is_ht(conf));
2254 2254
2255 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) { 2255 if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) {
2256 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n"); 2256 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2257 mutex_unlock(&sc->mutex); 2257 mutex_unlock(&sc->mutex);
2258 return -EINVAL; 2258 return -EINVAL;
@@ -2280,8 +2280,8 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
2280 /* TODO: Need to decide which hw opmode to use for multi-interface 2280 /* TODO: Need to decide which hw opmode to use for multi-interface
2281 * cases */ 2281 * cases */
2282 if (vif->type == NL80211_IFTYPE_AP && 2282 if (vif->type == NL80211_IFTYPE_AP &&
2283 ah->ah_opmode != NL80211_IFTYPE_AP) { 2283 ah->opmode != NL80211_IFTYPE_AP) {
2284 ah->ah_opmode = NL80211_IFTYPE_STATION; 2284 ah->opmode = NL80211_IFTYPE_STATION;
2285 ath9k_hw_setopmode(ah); 2285 ath9k_hw_setopmode(ah);
2286 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN); 2286 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2287 sc->curaid = 0; 2287 sc->curaid = 0;
diff --git a/drivers/net/wireless/ath9k/pci.c b/drivers/net/wireless/ath9k/pci.c
index eac8db742602..c28afe42b269 100644
--- a/drivers/net/wireless/ath9k/pci.c
+++ b/drivers/net/wireless/ath9k/pci.c
@@ -228,7 +228,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
228 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); 228 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
229 229
230#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 230#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
231 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 231 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
232 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); 232 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
233#endif 233#endif
234 234
@@ -269,7 +269,7 @@ static int ath_pci_resume(struct pci_dev *pdev)
269 * check the h/w rfkill state on resume 269 * check the h/w rfkill state on resume
270 * and start the rfkill poll timer 270 * and start the rfkill poll timer
271 */ 271 */
272 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 272 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
273 queue_delayed_work(sc->hw->workqueue, 273 queue_delayed_work(sc->hw->workqueue,
274 &sc->rf_kill.rfkill_poll, 0); 274 &sc->rf_kill.rfkill_poll, 0);
275#endif 275#endif
diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c
index 5a42969b35a6..52aa2a7abe7a 100644
--- a/drivers/net/wireless/ath9k/phy.c
+++ b/drivers/net/wireless/ath9k/phy.c
@@ -20,7 +20,7 @@ void
20ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, 20ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
21 int regWrites) 21 int regWrites)
22{ 22{
23 REG_WRITE_ARRAY(&ah->ah_iniBB_RfGain, freqIndex, regWrites); 23 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
24} 24}
25 25
26bool 26bool
@@ -90,8 +90,8 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
90 90
91 REG_WRITE(ah, AR_PHY(0x37), reg32); 91 REG_WRITE(ah, AR_PHY(0x37), reg32);
92 92
93 ah->ah_curchan = chan; 93 ah->curchan = chan;
94 ah->ah_curchanRadIndex = -1; 94 ah->curchan_rad_index = -1;
95 95
96 return true; 96 return true;
97} 97}
@@ -160,8 +160,8 @@ ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
160 160
161 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 161 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
162 162
163 ah->ah_curchan = chan; 163 ah->curchan = chan;
164 ah->ah_curchanRadIndex = -1; 164 ah->curchan_rad_index = -1;
165 165
166 return true; 166 return true;
167} 167}
@@ -207,19 +207,19 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
207 207
208 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 208 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
209 209
210 RF_BANK_SETUP(ah->ah_analogBank0Data, &ah->ah_iniBank0, 1); 210 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
211 211
212 RF_BANK_SETUP(ah->ah_analogBank1Data, &ah->ah_iniBank1, 1); 212 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
213 213
214 RF_BANK_SETUP(ah->ah_analogBank2Data, &ah->ah_iniBank2, 1); 214 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
215 215
216 RF_BANK_SETUP(ah->ah_analogBank3Data, &ah->ah_iniBank3, 216 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
217 modesIndex); 217 modesIndex);
218 { 218 {
219 int i; 219 int i;
220 for (i = 0; i < ah->ah_iniBank6TPC.ia_rows; i++) { 220 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
221 ah->ah_analogBank6Data[i] = 221 ah->analogBank6Data[i] =
222 INI_RA(&ah->ah_iniBank6TPC, i, modesIndex); 222 INI_RA(&ah->iniBank6TPC, i, modesIndex);
223 } 223 }
224 } 224 }
225 225
@@ -227,33 +227,33 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
227 if (IS_CHAN_2GHZ(chan)) { 227 if (IS_CHAN_2GHZ(chan)) {
228 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 228 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
229 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); 229 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
230 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, 230 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
231 ob2GHz, 3, 197, 0); 231 ob2GHz, 3, 197, 0);
232 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, 232 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
233 db2GHz, 3, 194, 0); 233 db2GHz, 3, 194, 0);
234 } else { 234 } else {
235 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); 235 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
236 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); 236 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
237 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, 237 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
238 ob5GHz, 3, 203, 0); 238 ob5GHz, 3, 203, 0);
239 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, 239 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
240 db5GHz, 3, 200, 0); 240 db5GHz, 3, 200, 0);
241 } 241 }
242 } 242 }
243 243
244 RF_BANK_SETUP(ah->ah_analogBank7Data, &ah->ah_iniBank7, 1); 244 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
245 245
246 REG_WRITE_RF_ARRAY(&ah->ah_iniBank0, ah->ah_analogBank0Data, 246 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
247 regWrites); 247 regWrites);
248 REG_WRITE_RF_ARRAY(&ah->ah_iniBank1, ah->ah_analogBank1Data, 248 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
249 regWrites); 249 regWrites);
250 REG_WRITE_RF_ARRAY(&ah->ah_iniBank2, ah->ah_analogBank2Data, 250 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
251 regWrites); 251 regWrites);
252 REG_WRITE_RF_ARRAY(&ah->ah_iniBank3, ah->ah_analogBank3Data, 252 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
253 regWrites); 253 regWrites);
254 REG_WRITE_RF_ARRAY(&ah->ah_iniBank6TPC, ah->ah_analogBank6Data, 254 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
255 regWrites); 255 regWrites);
256 REG_WRITE_RF_ARRAY(&ah->ah_iniBank7, ah->ah_analogBank7Data, 256 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
257 regWrites); 257 regWrites);
258 258
259 return true; 259 return true;
@@ -262,99 +262,99 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
262void 262void
263ath9k_hw_rfdetach(struct ath_hw *ah) 263ath9k_hw_rfdetach(struct ath_hw *ah)
264{ 264{
265 if (ah->ah_analogBank0Data != NULL) { 265 if (ah->analogBank0Data != NULL) {
266 kfree(ah->ah_analogBank0Data); 266 kfree(ah->analogBank0Data);
267 ah->ah_analogBank0Data = NULL; 267 ah->analogBank0Data = NULL;
268 } 268 }
269 if (ah->ah_analogBank1Data != NULL) { 269 if (ah->analogBank1Data != NULL) {
270 kfree(ah->ah_analogBank1Data); 270 kfree(ah->analogBank1Data);
271 ah->ah_analogBank1Data = NULL; 271 ah->analogBank1Data = NULL;
272 } 272 }
273 if (ah->ah_analogBank2Data != NULL) { 273 if (ah->analogBank2Data != NULL) {
274 kfree(ah->ah_analogBank2Data); 274 kfree(ah->analogBank2Data);
275 ah->ah_analogBank2Data = NULL; 275 ah->analogBank2Data = NULL;
276 } 276 }
277 if (ah->ah_analogBank3Data != NULL) { 277 if (ah->analogBank3Data != NULL) {
278 kfree(ah->ah_analogBank3Data); 278 kfree(ah->analogBank3Data);
279 ah->ah_analogBank3Data = NULL; 279 ah->analogBank3Data = NULL;
280 } 280 }
281 if (ah->ah_analogBank6Data != NULL) { 281 if (ah->analogBank6Data != NULL) {
282 kfree(ah->ah_analogBank6Data); 282 kfree(ah->analogBank6Data);
283 ah->ah_analogBank6Data = NULL; 283 ah->analogBank6Data = NULL;
284 } 284 }
285 if (ah->ah_analogBank6TPCData != NULL) { 285 if (ah->analogBank6TPCData != NULL) {
286 kfree(ah->ah_analogBank6TPCData); 286 kfree(ah->analogBank6TPCData);
287 ah->ah_analogBank6TPCData = NULL; 287 ah->analogBank6TPCData = NULL;
288 } 288 }
289 if (ah->ah_analogBank7Data != NULL) { 289 if (ah->analogBank7Data != NULL) {
290 kfree(ah->ah_analogBank7Data); 290 kfree(ah->analogBank7Data);
291 ah->ah_analogBank7Data = NULL; 291 ah->analogBank7Data = NULL;
292 } 292 }
293 if (ah->ah_addac5416_21 != NULL) { 293 if (ah->addac5416_21 != NULL) {
294 kfree(ah->ah_addac5416_21); 294 kfree(ah->addac5416_21);
295 ah->ah_addac5416_21 = NULL; 295 ah->addac5416_21 = NULL;
296 } 296 }
297 if (ah->ah_bank6Temp != NULL) { 297 if (ah->bank6Temp != NULL) {
298 kfree(ah->ah_bank6Temp); 298 kfree(ah->bank6Temp);
299 ah->ah_bank6Temp = NULL; 299 ah->bank6Temp = NULL;
300 } 300 }
301} 301}
302 302
303bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) 303bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
304{ 304{
305 if (!AR_SREV_9280_10_OR_LATER(ah)) { 305 if (!AR_SREV_9280_10_OR_LATER(ah)) {
306 ah->ah_analogBank0Data = 306 ah->analogBank0Data =
307 kzalloc((sizeof(u32) * 307 kzalloc((sizeof(u32) *
308 ah->ah_iniBank0.ia_rows), GFP_KERNEL); 308 ah->iniBank0.ia_rows), GFP_KERNEL);
309 ah->ah_analogBank1Data = 309 ah->analogBank1Data =
310 kzalloc((sizeof(u32) * 310 kzalloc((sizeof(u32) *
311 ah->ah_iniBank1.ia_rows), GFP_KERNEL); 311 ah->iniBank1.ia_rows), GFP_KERNEL);
312 ah->ah_analogBank2Data = 312 ah->analogBank2Data =
313 kzalloc((sizeof(u32) * 313 kzalloc((sizeof(u32) *
314 ah->ah_iniBank2.ia_rows), GFP_KERNEL); 314 ah->iniBank2.ia_rows), GFP_KERNEL);
315 ah->ah_analogBank3Data = 315 ah->analogBank3Data =
316 kzalloc((sizeof(u32) * 316 kzalloc((sizeof(u32) *
317 ah->ah_iniBank3.ia_rows), GFP_KERNEL); 317 ah->iniBank3.ia_rows), GFP_KERNEL);
318 ah->ah_analogBank6Data = 318 ah->analogBank6Data =
319 kzalloc((sizeof(u32) * 319 kzalloc((sizeof(u32) *
320 ah->ah_iniBank6.ia_rows), GFP_KERNEL); 320 ah->iniBank6.ia_rows), GFP_KERNEL);
321 ah->ah_analogBank6TPCData = 321 ah->analogBank6TPCData =
322 kzalloc((sizeof(u32) * 322 kzalloc((sizeof(u32) *
323 ah->ah_iniBank6TPC.ia_rows), GFP_KERNEL); 323 ah->iniBank6TPC.ia_rows), GFP_KERNEL);
324 ah->ah_analogBank7Data = 324 ah->analogBank7Data =
325 kzalloc((sizeof(u32) * 325 kzalloc((sizeof(u32) *
326 ah->ah_iniBank7.ia_rows), GFP_KERNEL); 326 ah->iniBank7.ia_rows), GFP_KERNEL);
327 327
328 if (ah->ah_analogBank0Data == NULL 328 if (ah->analogBank0Data == NULL
329 || ah->ah_analogBank1Data == NULL 329 || ah->analogBank1Data == NULL
330 || ah->ah_analogBank2Data == NULL 330 || ah->analogBank2Data == NULL
331 || ah->ah_analogBank3Data == NULL 331 || ah->analogBank3Data == NULL
332 || ah->ah_analogBank6Data == NULL 332 || ah->analogBank6Data == NULL
333 || ah->ah_analogBank6TPCData == NULL 333 || ah->analogBank6TPCData == NULL
334 || ah->ah_analogBank7Data == NULL) { 334 || ah->analogBank7Data == NULL) {
335 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 335 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
336 "Cannot allocate RF banks\n"); 336 "Cannot allocate RF banks\n");
337 *status = -ENOMEM; 337 *status = -ENOMEM;
338 return false; 338 return false;
339 } 339 }
340 340
341 ah->ah_addac5416_21 = 341 ah->addac5416_21 =
342 kzalloc((sizeof(u32) * 342 kzalloc((sizeof(u32) *
343 ah->ah_iniAddac.ia_rows * 343 ah->iniAddac.ia_rows *
344 ah->ah_iniAddac.ia_columns), GFP_KERNEL); 344 ah->iniAddac.ia_columns), GFP_KERNEL);
345 if (ah->ah_addac5416_21 == NULL) { 345 if (ah->addac5416_21 == NULL) {
346 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 346 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
347 "Cannot allocate ah_addac5416_21\n"); 347 "Cannot allocate addac5416_21\n");
348 *status = -ENOMEM; 348 *status = -ENOMEM;
349 return false; 349 return false;
350 } 350 }
351 351
352 ah->ah_bank6Temp = 352 ah->bank6Temp =
353 kzalloc((sizeof(u32) * 353 kzalloc((sizeof(u32) *
354 ah->ah_iniBank6.ia_rows), GFP_KERNEL); 354 ah->iniBank6.ia_rows), GFP_KERNEL);
355 if (ah->ah_bank6Temp == NULL) { 355 if (ah->bank6Temp == NULL) {
356 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 356 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
357 "Cannot allocate ah_bank6Temp\n"); 357 "Cannot allocate bank6Temp\n");
358 *status = -ENOMEM; 358 *status = -ENOMEM;
359 return false; 359 return false;
360 } 360 }
@@ -368,19 +368,19 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
368{ 368{
369 int i, regWrites = 0; 369 int i, regWrites = 0;
370 u32 bank6SelMask; 370 u32 bank6SelMask;
371 u32 *bank6Temp = ah->ah_bank6Temp; 371 u32 *bank6Temp = ah->bank6Temp;
372 372
373 switch (ah->ah_diversityControl) { 373 switch (ah->diversity_control) {
374 case ATH9K_ANT_FIXED_A: 374 case ATH9K_ANT_FIXED_A:
375 bank6SelMask = 375 bank6SelMask =
376 (ah-> 376 (ah->
377 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : 377 antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
378 REDUCE_CHAIN_1; 378 REDUCE_CHAIN_1;
379 break; 379 break;
380 case ATH9K_ANT_FIXED_B: 380 case ATH9K_ANT_FIXED_B:
381 bank6SelMask = 381 bank6SelMask =
382 (ah-> 382 (ah->
383 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : 383 antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
384 REDUCE_CHAIN_0; 384 REDUCE_CHAIN_0;
385 break; 385 break;
386 case ATH9K_ANT_VARIABLE: 386 case ATH9K_ANT_VARIABLE:
@@ -391,8 +391,8 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
391 break; 391 break;
392 } 392 }
393 393
394 for (i = 0; i < ah->ah_iniBank6.ia_rows; i++) 394 for (i = 0; i < ah->iniBank6.ia_rows; i++)
395 bank6Temp[i] = ah->ah_analogBank6Data[i]; 395 bank6Temp[i] = ah->analogBank6Data[i];
396 396
397 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); 397 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
398 398
@@ -406,7 +406,7 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
406 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0); 406 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
407 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0); 407 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
408 408
409 REG_WRITE_RF_ARRAY(&ah->ah_iniBank6, bank6Temp, regWrites); 409 REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
410 410
411 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); 411 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
412#ifdef ALTER_SWITCH 412#ifdef ALTER_SWITCH
diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h
index 71a7f5af7004..837a598a7ae5 100644
--- a/drivers/net/wireless/ath9k/phy.h
+++ b/drivers/net/wireless/ath9k/phy.h
@@ -533,7 +533,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
533#define ATH9K_KEY_XOR 0xaa 533#define ATH9K_KEY_XOR 0xaa
534 534
535#define ATH9K_IS_MIC_ENABLED(ah) \ 535#define ATH9K_IS_MIC_ENABLED(ah) \
536 ((ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) 536 ((ah)->sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
537 537
538#define ANTSWAP_AB 0x0001 538#define ANTSWAP_AB 0x0001
539#define REDUCE_CHAIN_0 0x00000050 539#define REDUCE_CHAIN_0 0x00000050
diff --git a/drivers/net/wireless/ath9k/rc.c b/drivers/net/wireless/ath9k/rc.c
index 060a7cf6f75a..a4e863191766 100644
--- a/drivers/net/wireless/ath9k/rc.c
+++ b/drivers/net/wireless/ath9k/rc.c
@@ -1394,13 +1394,13 @@ static void ath_rc_init(struct ath_softc *sc,
1394 u8 i, j, k, hi = 0, hthi = 0; 1394 u8 i, j, k, hi = 0, hthi = 0;
1395 1395
1396 /* FIXME: Adhoc */ 1396 /* FIXME: Adhoc */
1397 if ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) || 1397 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) ||
1398 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)) { 1398 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)) {
1399 bool is_cw_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40; 1399 bool is_cw_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40;
1400 rate_table = ath_choose_rate_table(sc, sband->band, 1400 rate_table = ath_choose_rate_table(sc, sband->band,
1401 sta->ht_cap.ht_supported, 1401 sta->ht_cap.ht_supported,
1402 is_cw_40); 1402 is_cw_40);
1403 } else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { 1403 } else if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
1404 /* cur_rate_table would be set on init through config() */ 1404 /* cur_rate_table would be set on init through config() */
1405 rate_table = sc->cur_rate_table; 1405 rate_table = sc->cur_rate_table;
1406 } 1406 }
@@ -1412,7 +1412,7 @@ static void ath_rc_init(struct ath_softc *sc,
1412 1412
1413 if (sta->ht_cap.ht_supported) { 1413 if (sta->ht_cap.ht_supported) {
1414 ath_rc_priv->ht_cap = WLAN_RC_HT_FLAG; 1414 ath_rc_priv->ht_cap = WLAN_RC_HT_FLAG;
1415 if (sc->sc_ah->ah_caps.tx_chainmask != 1) 1415 if (sc->sc_ah->caps.tx_chainmask != 1)
1416 ath_rc_priv->ht_cap |= WLAN_RC_DS_FLAG; 1416 ath_rc_priv->ht_cap |= WLAN_RC_DS_FLAG;
1417 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 1417 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1418 ath_rc_priv->ht_cap |= WLAN_RC_40_FLAG; 1418 ath_rc_priv->ht_cap |= WLAN_RC_40_FLAG;
@@ -1519,7 +1519,7 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1519 */ 1519 */
1520 if (tx_info_priv->tx.ts_flags & 1520 if (tx_info_priv->tx.ts_flags &
1521 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) && 1521 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) &&
1522 ((sc->sc_ah->ah_txTrigLevel) >= ath_rc_priv->tx_triglevel_max)) { 1522 ((sc->sc_ah->tx_trig_level) >= ath_rc_priv->tx_triglevel_max)) {
1523 tx_status = 1; 1523 tx_status = 1;
1524 is_underrun = 1; 1524 is_underrun = 1;
1525 } 1525 }
@@ -1628,7 +1628,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
1628 } 1628 }
1629 1629
1630 rate_priv->rssi_down_time = jiffies_to_msecs(jiffies); 1630 rate_priv->rssi_down_time = jiffies_to_msecs(jiffies);
1631 rate_priv->tx_triglevel_max = sc->sc_ah->ah_caps.tx_triglevel_max; 1631 rate_priv->tx_triglevel_max = sc->sc_ah->caps.tx_triglevel_max;
1632 1632
1633 return rate_priv; 1633 return rate_priv;
1634} 1634}
diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c
index 7c011b1ba333..08f676af894f 100644
--- a/drivers/net/wireless/ath9k/recv.c
+++ b/drivers/net/wireless/ath9k/recv.c
@@ -135,7 +135,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
135 * discard the frame. Enable this if you want to see 135 * discard the frame. Enable this if you want to see
136 * error frames in Monitor mode. 136 * error frames in Monitor mode.
137 */ 137 */
138 if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_MONITOR) 138 if (sc->sc_ah->opmode != NL80211_IFTYPE_MONITOR)
139 goto rx_next; 139 goto rx_next;
140 } else if (ds->ds_rxstat.rs_status != 0) { 140 } else if (ds->ds_rxstat.rs_status != 0) {
141 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) 141 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
@@ -161,7 +161,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
161 * decryption and MIC failures. For monitor mode, 161 * decryption and MIC failures. For monitor mode,
162 * we also ignore the CRC error. 162 * we also ignore the CRC error.
163 */ 163 */
164 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR) { 164 if (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR) {
165 if (ds->ds_rxstat.rs_status & 165 if (ds->ds_rxstat.rs_status &
166 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | 166 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
167 ATH9K_RXERR_CRC)) 167 ATH9K_RXERR_CRC))
@@ -241,7 +241,7 @@ static void ath_opmode_init(struct ath_softc *sc)
241 ath9k_hw_setrxfilter(ah, rfilt); 241 ath9k_hw_setrxfilter(ah, rfilt);
242 242
243 /* configure bssid mask */ 243 /* configure bssid mask */
244 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) 244 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
245 ath9k_hw_setbssidmask(sc); 245 ath9k_hw_setbssidmask(sc);
246 246
247 /* configure operational mode */ 247 /* configure operational mode */
@@ -360,13 +360,13 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
360 | ATH9K_RX_FILTER_MCAST; 360 | ATH9K_RX_FILTER_MCAST;
361 361
362 /* If not a STA, enable processing of Probe Requests */ 362 /* If not a STA, enable processing of Probe Requests */
363 if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_STATION) 363 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
364 rfilt |= ATH9K_RX_FILTER_PROBEREQ; 364 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
365 365
366 /* Can't set HOSTAP into promiscous mode */ 366 /* Can't set HOSTAP into promiscous mode */
367 if (((sc->sc_ah->ah_opmode != NL80211_IFTYPE_AP) && 367 if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
368 (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || 368 (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
369 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR)) { 369 (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) {
370 rfilt |= ATH9K_RX_FILTER_PROM; 370 rfilt |= ATH9K_RX_FILTER_PROM;
371 /* ??? To prevent from sending ACK */ 371 /* ??? To prevent from sending ACK */
372 rfilt &= ~ATH9K_RX_FILTER_UCAST; 372 rfilt &= ~ATH9K_RX_FILTER_UCAST;
@@ -375,13 +375,13 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
375 if (sc->rx.rxfilter & FIF_CONTROL) 375 if (sc->rx.rxfilter & FIF_CONTROL)
376 rfilt |= ATH9K_RX_FILTER_CONTROL; 376 rfilt |= ATH9K_RX_FILTER_CONTROL;
377 377
378 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION || 378 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION ||
379 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) 379 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
380 rfilt |= ATH9K_RX_FILTER_BEACON; 380 rfilt |= ATH9K_RX_FILTER_BEACON;
381 381
382 /* If in HOSTAP mode, want to enable reception of PSPOLL frames 382 /* If in HOSTAP mode, want to enable reception of PSPOLL frames
383 & beacon frames */ 383 & beacon frames */
384 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) 384 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP)
385 rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL); 385 rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL);
386 386
387 return rfilt; 387 return rfilt;
diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c
index 3fff3344b2ee..3f70b1e58ae4 100644
--- a/drivers/net/wireless/ath9k/xmit.c
+++ b/drivers/net/wireless/ath9k/xmit.c
@@ -308,7 +308,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
308 * when perform internal reset in this routine. 308 * when perform internal reset in this routine.
309 * Only enable reset in STA mode for now. 309 * Only enable reset in STA mode for now.
310 */ 310 */
311 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) 311 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
312 needreset = 1; 312 needreset = 1;
313 } 313 }
314 } 314 }
@@ -1072,7 +1072,7 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1072 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); 1072 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1073 1073
1074 spin_lock_bh(&sc->sc_resetlock); 1074 spin_lock_bh(&sc->sc_resetlock);
1075 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, true); 1075 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1076 if (r) 1076 if (r)
1077 DPRINTF(sc, ATH_DBG_FATAL, 1077 DPRINTF(sc, ATH_DBG_FATAL,
1078 "Unable to reset hardware; reset status %u\n", 1078 "Unable to reset hardware; reset status %u\n",
@@ -1477,7 +1477,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1477 } 1477 }
1478 1478
1479 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1479 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1480 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->ah_caps.rts_aggr_limit)) 1480 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1481 flags &= ~(ATH9K_TXDESC_RTSENA); 1481 flags &= ~(ATH9K_TXDESC_RTSENA);
1482 1482
1483 for (i = 0; i < 4; i++) { 1483 for (i = 0; i < 4; i++) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 03:11:57 -0500