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authorChristoph Hellwig <hch@lst.de>2007-10-25 05:15:50 -0400
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:03:24 -0500
commit5d08cd1dfdc57dc834c47eb9f023fcf861f3d6bf (patch)
treeabac0496b2ab958970c58c459070a8ca5f5fdde7 /drivers/net/wireless
parent416e1438d5a921046fda6fc5673d5f2c69841c06 (diff)
iwlwifi: keep 3945 and 4965 headers separate
The iwl3945 and iwl4965 devices share some common structure, but with a lot of difference split all over. Currently the two drivers share a lot of headers and use ugly preprocessor magic to manage the difference. This patch keeps two entirely separate copies of the headers to get rid of these hacks an ease future development. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-commands.h1467
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-debug.h (renamed from drivers/net/wireless/iwlwifi/iwl-debug.h)0
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-hw.h627
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-io.h (renamed from drivers/net/wireless/iwlwifi/iwl-io.h)2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-rs.c4
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.c5
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.h960
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-commands.h (renamed from drivers/net/wireless/iwlwifi/iwl-commands.h)152
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-debug.h152
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-hw.h677
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-io.h431
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-rs.c4
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c3
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.h1019
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-channel.h161
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.h336
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-hw.h537
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-priv.h307
-rw-r--r--drivers/net/wireless/iwlwifi/iwl3945-base.c3
-rw-r--r--drivers/net/wireless/iwlwifi/iwl4965-base.c3
-rw-r--r--drivers/net/wireless/iwlwifi/iwlwifi.h695
21 files changed, 5337 insertions, 2208 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-commands.h b/drivers/net/wireless/iwlwifi/iwl-3945-commands.h
new file mode 100644
index 000000000000..2c71195a08e3
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-commands.h
@@ -0,0 +1,1467 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63
64#ifndef __iwl_3945_commands_h__
65#define __iwl_3945_commands_h__
66
67enum {
68 REPLY_ALIVE = 0x1,
69 REPLY_ERROR = 0x2,
70
71 /* RXON and QOS commands */
72 REPLY_RXON = 0x10,
73 REPLY_RXON_ASSOC = 0x11,
74 REPLY_QOS_PARAM = 0x13,
75 REPLY_RXON_TIMING = 0x14,
76
77 /* Multi-Station support */
78 REPLY_ADD_STA = 0x18,
79 REPLY_REMOVE_STA = 0x19, /* not used */
80 REPLY_REMOVE_ALL_STA = 0x1a, /* not used */
81
82 /* RX, TX, LEDs */
83 REPLY_3945_RX = 0x1b, /* 3945 only */
84 REPLY_TX = 0x1c,
85 REPLY_RATE_SCALE = 0x47, /* 3945 only */
86 REPLY_LEDS_CMD = 0x48,
87 REPLY_TX_LINK_QUALITY_CMD = 0x4e, /* 4965 only */
88
89 /* 802.11h related */
90 RADAR_NOTIFICATION = 0x70, /* not used */
91 REPLY_QUIET_CMD = 0x71, /* not used */
92 REPLY_CHANNEL_SWITCH = 0x72,
93 CHANNEL_SWITCH_NOTIFICATION = 0x73,
94 REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74,
95 SPECTRUM_MEASURE_NOTIFICATION = 0x75,
96
97 /* Power Management */
98 POWER_TABLE_CMD = 0x77,
99 PM_SLEEP_NOTIFICATION = 0x7A,
100 PM_DEBUG_STATISTIC_NOTIFIC = 0x7B,
101
102 /* Scan commands and notifications */
103 REPLY_SCAN_CMD = 0x80,
104 REPLY_SCAN_ABORT_CMD = 0x81,
105 SCAN_START_NOTIFICATION = 0x82,
106 SCAN_RESULTS_NOTIFICATION = 0x83,
107 SCAN_COMPLETE_NOTIFICATION = 0x84,
108
109 /* IBSS/AP commands */
110 BEACON_NOTIFICATION = 0x90,
111 REPLY_TX_BEACON = 0x91,
112 WHO_IS_AWAKE_NOTIFICATION = 0x94, /* not used */
113
114 /* Miscellaneous commands */
115 QUIET_NOTIFICATION = 0x96, /* not used */
116 REPLY_TX_PWR_TABLE_CMD = 0x97,
117 MEASURE_ABORT_NOTIFICATION = 0x99, /* not used */
118
119 /* BT config command */
120 REPLY_BT_CONFIG = 0x9b,
121
122 /* 4965 Statistics */
123 REPLY_STATISTICS_CMD = 0x9c,
124 STATISTICS_NOTIFICATION = 0x9d,
125
126 /* RF-KILL commands and notifications */
127 REPLY_CARD_STATE_CMD = 0xa0,
128 CARD_STATE_NOTIFICATION = 0xa1,
129
130 /* Missed beacons notification */
131 MISSED_BEACONS_NOTIFICATION = 0xa2,
132
133 REPLY_MAX = 0xff
134};
135
136/******************************************************************************
137 * (0)
138 * Header
139 *
140 *****************************************************************************/
141
142#define IWL_CMD_FAILED_MSK 0x40
143
144struct iwl_cmd_header {
145 u8 cmd;
146 u8 flags;
147 /* We have 15 LSB to use as we please (MSB indicates
148 * a frame Rx'd from the HW). We encode the following
149 * information into the sequence field:
150 *
151 * 0:7 index in fifo
152 * 8:13 fifo selection
153 * 14:14 bit indicating if this packet references the 'extra'
154 * storage at the end of the memory queue
155 * 15:15 (Rx indication)
156 *
157 */
158 __le16 sequence;
159
160 /* command data follows immediately */
161 u8 data[0];
162} __attribute__ ((packed));
163
164/******************************************************************************
165 * (0a)
166 * Alive and Error Commands & Responses:
167 *
168 *****************************************************************************/
169
170#define UCODE_VALID_OK __constant_cpu_to_le32(0x1)
171#define INITIALIZE_SUBTYPE (9)
172
173/*
174 * REPLY_ALIVE = 0x1 (response only, not a command)
175 */
176struct iwl_alive_resp {
177 u8 ucode_minor;
178 u8 ucode_major;
179 __le16 reserved1;
180 u8 sw_rev[8];
181 u8 ver_type;
182 u8 ver_subtype;
183 __le16 reserved2;
184 __le32 log_event_table_ptr;
185 __le32 error_event_table_ptr;
186 __le32 timestamp;
187 __le32 is_valid;
188} __attribute__ ((packed));
189
190struct iwl_init_alive_resp {
191 u8 ucode_minor;
192 u8 ucode_major;
193 __le16 reserved1;
194 u8 sw_rev[8];
195 u8 ver_type;
196 u8 ver_subtype;
197 __le16 reserved2;
198 __le32 log_event_table_ptr;
199 __le32 error_event_table_ptr;
200 __le32 timestamp;
201 __le32 is_valid;
202} __attribute__ ((packed));
203
204union tsf {
205 u8 byte[8];
206 __le16 word[4];
207 __le32 dw[2];
208};
209
210/*
211 * REPLY_ERROR = 0x2 (response only, not a command)
212 */
213struct iwl_error_resp {
214 __le32 error_type;
215 u8 cmd_id;
216 u8 reserved1;
217 __le16 bad_cmd_seq_num;
218 __le16 reserved2;
219 __le32 error_info;
220 union tsf timestamp;
221} __attribute__ ((packed));
222
223/******************************************************************************
224 * (1)
225 * RXON Commands & Responses:
226 *
227 *****************************************************************************/
228
229/*
230 * Rx config defines & structure
231 */
232/* rx_config device types */
233enum {
234 RXON_DEV_TYPE_AP = 1,
235 RXON_DEV_TYPE_ESS = 3,
236 RXON_DEV_TYPE_IBSS = 4,
237 RXON_DEV_TYPE_SNIFFER = 6,
238};
239
240/* rx_config flags */
241/* band & modulation selection */
242#define RXON_FLG_BAND_24G_MSK __constant_cpu_to_le32(1 << 0)
243#define RXON_FLG_CCK_MSK __constant_cpu_to_le32(1 << 1)
244/* auto detection enable */
245#define RXON_FLG_AUTO_DETECT_MSK __constant_cpu_to_le32(1 << 2)
246/* TGg protection when tx */
247#define RXON_FLG_TGG_PROTECT_MSK __constant_cpu_to_le32(1 << 3)
248/* cck short slot & preamble */
249#define RXON_FLG_SHORT_SLOT_MSK __constant_cpu_to_le32(1 << 4)
250#define RXON_FLG_SHORT_PREAMBLE_MSK __constant_cpu_to_le32(1 << 5)
251/* antenna selection */
252#define RXON_FLG_DIS_DIV_MSK __constant_cpu_to_le32(1 << 7)
253#define RXON_FLG_ANT_SEL_MSK __constant_cpu_to_le32(0x0f00)
254#define RXON_FLG_ANT_A_MSK __constant_cpu_to_le32(1 << 8)
255#define RXON_FLG_ANT_B_MSK __constant_cpu_to_le32(1 << 9)
256/* radar detection enable */
257#define RXON_FLG_RADAR_DETECT_MSK __constant_cpu_to_le32(1 << 12)
258#define RXON_FLG_TGJ_NARROW_BAND_MSK __constant_cpu_to_le32(1 << 13)
259/* rx response to host with 8-byte TSF
260* (according to ON_AIR deassertion) */
261#define RXON_FLG_TSF2HOST_MSK __constant_cpu_to_le32(1 << 15)
262
263/* rx_config filter flags */
264/* accept all data frames */
265#define RXON_FILTER_PROMISC_MSK __constant_cpu_to_le32(1 << 0)
266/* pass control & management to host */
267#define RXON_FILTER_CTL2HOST_MSK __constant_cpu_to_le32(1 << 1)
268/* accept multi-cast */
269#define RXON_FILTER_ACCEPT_GRP_MSK __constant_cpu_to_le32(1 << 2)
270/* don't decrypt uni-cast frames */
271#define RXON_FILTER_DIS_DECRYPT_MSK __constant_cpu_to_le32(1 << 3)
272/* don't decrypt multi-cast frames */
273#define RXON_FILTER_DIS_GRP_DECRYPT_MSK __constant_cpu_to_le32(1 << 4)
274/* STA is associated */
275#define RXON_FILTER_ASSOC_MSK __constant_cpu_to_le32(1 << 5)
276/* transfer to host non bssid beacons in associated state */
277#define RXON_FILTER_BCON_AWARE_MSK __constant_cpu_to_le32(1 << 6)
278
279/*
280 * REPLY_RXON = 0x10 (command, has simple generic response)
281 */
282struct iwl_rxon_cmd {
283 u8 node_addr[6];
284 __le16 reserved1;
285 u8 bssid_addr[6];
286 __le16 reserved2;
287 u8 wlap_bssid_addr[6];
288 __le16 reserved3;
289 u8 dev_type;
290 u8 air_propagation;
291 __le16 reserved4;
292 u8 ofdm_basic_rates;
293 u8 cck_basic_rates;
294 __le16 assoc_id;
295 __le32 flags;
296 __le32 filter_flags;
297 __le16 channel;
298 __le16 reserved5;
299} __attribute__ ((packed));
300
301/*
302 * REPLY_RXON_ASSOC = 0x11 (command, has simple generic response)
303 */
304struct iwl_rxon_assoc_cmd {
305 __le32 flags;
306 __le32 filter_flags;
307 u8 ofdm_basic_rates;
308 u8 cck_basic_rates;
309 __le16 reserved;
310} __attribute__ ((packed));
311
312/*
313 * REPLY_RXON_TIMING = 0x14 (command, has simple generic response)
314 */
315struct iwl_rxon_time_cmd {
316 union tsf timestamp;
317 __le16 beacon_interval;
318 __le16 atim_window;
319 __le32 beacon_init_val;
320 __le16 listen_interval;
321 __le16 reserved;
322} __attribute__ ((packed));
323
324struct iwl_tx_power {
325 u8 tx_gain; /* gain for analog radio */
326 u8 dsp_atten; /* gain for DSP */
327} __attribute__ ((packed));
328
329struct iwl_power_per_rate {
330 u8 rate; /* plcp */
331 struct iwl_tx_power tpc;
332 u8 reserved;
333} __attribute__ ((packed));
334
335/*
336 * REPLY_CHANNEL_SWITCH = 0x72 (command, has simple generic response)
337 */
338struct iwl_channel_switch_cmd {
339 u8 band;
340 u8 expect_beacon;
341 __le16 channel;
342 __le32 rxon_flags;
343 __le32 rxon_filter_flags;
344 __le32 switch_time;
345 struct iwl_power_per_rate power[IWL_MAX_RATES];
346} __attribute__ ((packed));
347
348/*
349 * CHANNEL_SWITCH_NOTIFICATION = 0x73 (notification only, not a command)
350 */
351struct iwl_csa_notification {
352 __le16 band;
353 __le16 channel;
354 __le32 status; /* 0 - OK, 1 - fail */
355} __attribute__ ((packed));
356
357/******************************************************************************
358 * (2)
359 * Quality-of-Service (QOS) Commands & Responses:
360 *
361 *****************************************************************************/
362struct iwl_ac_qos {
363 __le16 cw_min;
364 __le16 cw_max;
365 u8 aifsn;
366 u8 reserved1;
367 __le16 edca_txop;
368} __attribute__ ((packed));
369
370/* QoS flags defines */
371#define QOS_PARAM_FLG_UPDATE_EDCA_MSK __constant_cpu_to_le32(0x01)
372#define QOS_PARAM_FLG_TGN_MSK __constant_cpu_to_le32(0x02)
373#define QOS_PARAM_FLG_TXOP_TYPE_MSK __constant_cpu_to_le32(0x10)
374
375/*
376 * TXFIFO Queue number defines
377 */
378/* number of Access categories (AC) (EDCA), queues 0..3 */
379#define AC_NUM 4
380
381/*
382 * REPLY_QOS_PARAM = 0x13 (command, has simple generic response)
383 */
384struct iwl_qosparam_cmd {
385 __le32 qos_flags;
386 struct iwl_ac_qos ac[AC_NUM];
387} __attribute__ ((packed));
388
389/******************************************************************************
390 * (3)
391 * Add/Modify Stations Commands & Responses:
392 *
393 *****************************************************************************/
394/*
395 * Multi station support
396 */
397#define IWL_AP_ID 0
398#define IWL_MULTICAST_ID 1
399#define IWL_STA_ID 2
400
401#define IWL3945_BROADCAST_ID 24
402#define IWL3945_STATION_COUNT 25
403
404#define IWL4965_BROADCAST_ID 31
405#define IWL4965_STATION_COUNT 32
406
407#define IWL_STATION_COUNT 32 /* MAX(3945,4965)*/
408#define IWL_INVALID_STATION 255
409
410#define STA_FLG_TX_RATE_MSK __constant_cpu_to_le32(1<<2);
411#define STA_FLG_PWR_SAVE_MSK __constant_cpu_to_le32(1<<8);
412
413#define STA_CONTROL_MODIFY_MSK 0x01
414
415/* key flags __le16*/
416#define STA_KEY_FLG_ENCRYPT_MSK __constant_cpu_to_le16(0x7)
417#define STA_KEY_FLG_NO_ENC __constant_cpu_to_le16(0x0)
418#define STA_KEY_FLG_WEP __constant_cpu_to_le16(0x1)
419#define STA_KEY_FLG_CCMP __constant_cpu_to_le16(0x2)
420#define STA_KEY_FLG_TKIP __constant_cpu_to_le16(0x3)
421
422#define STA_KEY_FLG_KEYID_POS 8
423#define STA_KEY_FLG_INVALID __constant_cpu_to_le16(0x0800)
424
425/* modify flags */
426#define STA_MODIFY_KEY_MASK 0x01
427#define STA_MODIFY_TID_DISABLE_TX 0x02
428#define STA_MODIFY_TX_RATE_MSK 0x04
429#define STA_MODIFY_ADDBA_TID_MSK 0x08
430#define STA_MODIFY_DELBA_TID_MSK 0x10
431#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
432
433/*
434 * Antenna masks:
435 * bit14:15 01 B inactive, A active
436 * 10 B active, A inactive
437 * 11 Both active
438 */
439#define RATE_MCS_ANT_A_POS 14
440#define RATE_MCS_ANT_B_POS 15
441#define RATE_MCS_ANT_A_MSK 0x4000
442#define RATE_MCS_ANT_B_MSK 0x8000
443#define RATE_MCS_ANT_AB_MSK 0xc000
444
445struct iwl_keyinfo {
446 __le16 key_flags;
447 u8 tkip_rx_tsc_byte2; /* TSC[2] for key mix ph1 detection */
448 u8 reserved1;
449 __le16 tkip_rx_ttak[5]; /* 10-byte unicast TKIP TTAK */
450 __le16 reserved2;
451 u8 key[16]; /* 16-byte unicast decryption key */
452} __attribute__ ((packed));
453
454struct sta_id_modify {
455 u8 addr[ETH_ALEN];
456 __le16 reserved1;
457 u8 sta_id;
458 u8 modify_mask;
459 __le16 reserved2;
460} __attribute__ ((packed));
461
462/*
463 * REPLY_ADD_STA = 0x18 (command)
464 */
465struct iwl_addsta_cmd {
466 u8 mode;
467 u8 reserved[3];
468 struct sta_id_modify sta;
469 struct iwl_keyinfo key;
470 __le32 station_flags;
471 __le32 station_flags_msk;
472 __le16 tid_disable_tx;
473 __le16 rate_n_flags;
474 u8 add_immediate_ba_tid;
475 u8 remove_immediate_ba_tid;
476 __le16 add_immediate_ba_ssn;
477} __attribute__ ((packed));
478
479/*
480 * REPLY_ADD_STA = 0x18 (response)
481 */
482struct iwl_add_sta_resp {
483 u8 status;
484} __attribute__ ((packed));
485
486#define ADD_STA_SUCCESS_MSK 0x1
487
488/******************************************************************************
489 * (4)
490 * Rx Responses:
491 *
492 *****************************************************************************/
493
494struct iwl_rx_frame_stats {
495 u8 phy_count;
496 u8 id;
497 u8 rssi;
498 u8 agc;
499 __le16 sig_avg;
500 __le16 noise_diff;
501 u8 payload[0];
502} __attribute__ ((packed));
503
504struct iwl_rx_frame_hdr {
505 __le16 channel;
506 __le16 phy_flags;
507 u8 reserved1;
508 u8 rate;
509 __le16 len;
510 u8 payload[0];
511} __attribute__ ((packed));
512
513#define RX_RES_STATUS_NO_CRC32_ERROR __constant_cpu_to_le32(1 << 0)
514#define RX_RES_STATUS_NO_RXE_OVERFLOW __constant_cpu_to_le32(1 << 1)
515
516#define RX_RES_PHY_FLAGS_BAND_24_MSK __constant_cpu_to_le16(1 << 0)
517#define RX_RES_PHY_FLAGS_MOD_CCK_MSK __constant_cpu_to_le16(1 << 1)
518#define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK __constant_cpu_to_le16(1 << 2)
519#define RX_RES_PHY_FLAGS_NARROW_BAND_MSK __constant_cpu_to_le16(1 << 3)
520#define RX_RES_PHY_FLAGS_ANTENNA_MSK __constant_cpu_to_le16(0xf0)
521
522#define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
523#define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
524#define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
525#define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
526#define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
527
528#define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
529#define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
530#define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
531#define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
532#define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
533
534struct iwl_rx_frame_end {
535 __le32 status;
536 __le64 timestamp;
537 __le32 beacon_timestamp;
538} __attribute__ ((packed));
539
540/*
541 * REPLY_3945_RX = 0x1b (response only, not a command)
542 *
543 * NOTE: DO NOT dereference from casts to this structure
544 * It is provided only for calculating minimum data set size.
545 * The actual offsets of the hdr and end are dynamic based on
546 * stats.phy_count
547 */
548struct iwl_rx_frame {
549 struct iwl_rx_frame_stats stats;
550 struct iwl_rx_frame_hdr hdr;
551 struct iwl_rx_frame_end end;
552} __attribute__ ((packed));
553
554/* Fixed (non-configurable) rx data from phy */
555#define RX_PHY_FLAGS_ANTENNAE_OFFSET (4)
556#define RX_PHY_FLAGS_ANTENNAE_MASK (0x70)
557#define IWL_AGC_DB_MASK (0x3f80) /* MASK(7,13) */
558#define IWL_AGC_DB_POS (7)
559struct iwl4965_rx_non_cfg_phy {
560 __le16 ant_selection; /* ant A bit 4, ant B bit 5, ant C bit 6 */
561 __le16 agc_info; /* agc code 0:6, agc dB 7:13, reserved 14:15 */
562 u8 rssi_info[6]; /* we use even entries, 0/2/4 for A/B/C rssi */
563 u8 pad[0];
564} __attribute__ ((packed));
565
566/*
567 * REPLY_4965_RX = 0xc3 (response only, not a command)
568 * Used only for legacy (non 11n) frames.
569 */
570#define RX_RES_PHY_CNT 14
571struct iwl4965_rx_phy_res {
572 u8 non_cfg_phy_cnt; /* non configurable DSP phy data byte count */
573 u8 cfg_phy_cnt; /* configurable DSP phy data byte count */
574 u8 stat_id; /* configurable DSP phy data set ID */
575 u8 reserved1;
576 __le64 timestamp; /* TSF at on air rise */
577 __le32 beacon_time_stamp; /* beacon at on-air rise */
578 __le16 phy_flags; /* general phy flags: band, modulation, ... */
579 __le16 channel; /* channel number */
580 __le16 non_cfg_phy[RX_RES_PHY_CNT]; /* upto 14 phy entries */
581 __le32 reserved2;
582 __le32 rate_n_flags;
583 __le16 byte_count; /* frame's byte-count */
584 __le16 reserved3;
585} __attribute__ ((packed));
586
587struct iwl4965_rx_mpdu_res_start {
588 __le16 byte_count;
589 __le16 reserved;
590} __attribute__ ((packed));
591
592
593/******************************************************************************
594 * (5)
595 * Tx Commands & Responses:
596 *
597 *****************************************************************************/
598
599/* Tx flags */
600#define TX_CMD_FLG_RTS_MSK __constant_cpu_to_le32(1 << 1)
601#define TX_CMD_FLG_CTS_MSK __constant_cpu_to_le32(1 << 2)
602#define TX_CMD_FLG_ACK_MSK __constant_cpu_to_le32(1 << 3)
603#define TX_CMD_FLG_STA_RATE_MSK __constant_cpu_to_le32(1 << 4)
604#define TX_CMD_FLG_IMM_BA_RSP_MASK __constant_cpu_to_le32(1 << 6)
605#define TX_CMD_FLG_FULL_TXOP_PROT_MSK __constant_cpu_to_le32(1 << 7)
606#define TX_CMD_FLG_ANT_SEL_MSK __constant_cpu_to_le32(0xf00)
607#define TX_CMD_FLG_ANT_A_MSK __constant_cpu_to_le32(1 << 8)
608#define TX_CMD_FLG_ANT_B_MSK __constant_cpu_to_le32(1 << 9)
609
610/* ucode ignores BT priority for this frame */
611#define TX_CMD_FLG_BT_DIS_MSK __constant_cpu_to_le32(1 << 12)
612
613/* ucode overrides sequence control */
614#define TX_CMD_FLG_SEQ_CTL_MSK __constant_cpu_to_le32(1 << 13)
615
616/* signal that this frame is non-last MPDU */
617#define TX_CMD_FLG_MORE_FRAG_MSK __constant_cpu_to_le32(1 << 14)
618
619/* calculate TSF in outgoing frame */
620#define TX_CMD_FLG_TSF_MSK __constant_cpu_to_le32(1 << 16)
621
622/* activate TX calibration. */
623#define TX_CMD_FLG_CALIB_MSK __constant_cpu_to_le32(1 << 17)
624
625/* signals that 2 bytes pad was inserted
626 after the MAC header */
627#define TX_CMD_FLG_MH_PAD_MSK __constant_cpu_to_le32(1 << 20)
628
629/* HCCA-AP - disable duration overwriting. */
630#define TX_CMD_FLG_DUR_MSK __constant_cpu_to_le32(1 << 25)
631
632/*
633 * TX command security control
634 */
635#define TX_CMD_SEC_WEP 0x01
636#define TX_CMD_SEC_CCM 0x02
637#define TX_CMD_SEC_TKIP 0x03
638#define TX_CMD_SEC_MSK 0x03
639#define TX_CMD_SEC_SHIFT 6
640#define TX_CMD_SEC_KEY128 0x08
641
642/*
643 * TX command Frame life time
644 */
645
646struct iwl_dram_scratch {
647 u8 try_cnt;
648 u8 bt_kill_cnt;
649 __le16 reserved;
650} __attribute__ ((packed));
651
652/*
653 * REPLY_TX = 0x1c (command)
654 */
655struct iwl_tx_cmd {
656 __le16 len;
657 __le16 next_frame_len;
658 __le32 tx_flags;
659 u8 rate;
660 u8 sta_id;
661 u8 tid_tspec;
662 u8 sec_ctl;
663 u8 key[16];
664 union {
665 u8 byte[8];
666 __le16 word[4];
667 __le32 dw[2];
668 } tkip_mic;
669 __le32 next_frame_info;
670 union {
671 __le32 life_time;
672 __le32 attempt;
673 } stop_time;
674 u8 supp_rates[2];
675 u8 rts_retry_limit; /*byte 50 */
676 u8 data_retry_limit; /*byte 51 */
677 union {
678 __le16 pm_frame_timeout;
679 __le16 attempt_duration;
680 } timeout;
681 __le16 driver_txop;
682 u8 payload[0];
683 struct ieee80211_hdr hdr[0];
684} __attribute__ ((packed));
685
686/* TX command response is sent after *all* transmission attempts.
687 *
688 * NOTES:
689 *
690 * TX_STATUS_FAIL_NEXT_FRAG
691 *
692 * If the fragment flag in the MAC header for the frame being transmitted
693 * is set and there is insufficient time to transmit the next frame, the
694 * TX status will be returned with 'TX_STATUS_FAIL_NEXT_FRAG'.
695 *
696 * TX_STATUS_FIFO_UNDERRUN
697 *
698 * Indicates the host did not provide bytes to the FIFO fast enough while
699 * a TX was in progress.
700 *
701 * TX_STATUS_FAIL_MGMNT_ABORT
702 *
703 * This status is only possible if the ABORT ON MGMT RX parameter was
704 * set to true with the TX command.
705 *
706 * If the MSB of the status parameter is set then an abort sequence is
707 * required. This sequence consists of the host activating the TX Abort
708 * control line, and then waiting for the TX Abort command response. This
709 * indicates that a the device is no longer in a transmit state, and that the
710 * command FIFO has been cleared. The host must then deactivate the TX Abort
711 * control line. Receiving is still allowed in this case.
712 */
713enum {
714 TX_STATUS_SUCCESS = 0x01,
715 TX_STATUS_DIRECT_DONE = 0x02,
716 TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
717 TX_STATUS_FAIL_LONG_LIMIT = 0x83,
718 TX_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
719 TX_STATUS_FAIL_MGMNT_ABORT = 0x85,
720 TX_STATUS_FAIL_NEXT_FRAG = 0x86,
721 TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
722 TX_STATUS_FAIL_DEST_PS = 0x88,
723 TX_STATUS_FAIL_ABORTED = 0x89,
724 TX_STATUS_FAIL_BT_RETRY = 0x8a,
725 TX_STATUS_FAIL_STA_INVALID = 0x8b,
726 TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
727 TX_STATUS_FAIL_TID_DISABLE = 0x8d,
728 TX_STATUS_FAIL_FRAME_FLUSHED = 0x8e,
729 TX_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
730 TX_STATUS_FAIL_TX_LOCKED = 0x90,
731 TX_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
732};
733
734#define TX_PACKET_MODE_REGULAR 0x0000
735#define TX_PACKET_MODE_BURST_SEQ 0x0100
736#define TX_PACKET_MODE_BURST_FIRST 0x0200
737
738enum {
739 TX_POWER_PA_NOT_ACTIVE = 0x0,
740};
741
742enum {
743 TX_STATUS_MSK = 0x000000ff, /* bits 0:7 */
744 TX_STATUS_DELAY_MSK = 0x00000040,
745 TX_STATUS_ABORT_MSK = 0x00000080,
746 TX_PACKET_MODE_MSK = 0x0000ff00, /* bits 8:15 */
747 TX_FIFO_NUMBER_MSK = 0x00070000, /* bits 16:18 */
748 TX_RESERVED = 0x00780000, /* bits 19:22 */
749 TX_POWER_PA_DETECT_MSK = 0x7f800000, /* bits 23:30 */
750 TX_ABORT_REQUIRED_MSK = 0x80000000, /* bits 31:31 */
751};
752
753/* *******************************
754 * TX aggregation state
755 ******************************* */
756
757enum {
758 AGG_TX_STATE_TRANSMITTED = 0x00,
759 AGG_TX_STATE_UNDERRUN_MSK = 0x01,
760 AGG_TX_STATE_BT_PRIO_MSK = 0x02,
761 AGG_TX_STATE_FEW_BYTES_MSK = 0x04,
762 AGG_TX_STATE_ABORT_MSK = 0x08,
763 AGG_TX_STATE_LAST_SENT_TTL_MSK = 0x10,
764 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK = 0x20,
765 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK = 0x40,
766 AGG_TX_STATE_SCD_QUERY_MSK = 0x80,
767 AGG_TX_STATE_TEST_BAD_CRC32_MSK = 0x100,
768 AGG_TX_STATE_RESPONSE_MSK = 0x1ff,
769 AGG_TX_STATE_DUMP_TX_MSK = 0x200,
770 AGG_TX_STATE_DELAY_TX_MSK = 0x400
771};
772
773#define AGG_TX_STATE_LAST_SENT_MSK \
774(AGG_TX_STATE_LAST_SENT_TTL_MSK | \
775 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK | \
776 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK)
777
778#define AGG_TX_STATE_TRY_CNT_POS 12
779#define AGG_TX_STATE_TRY_CNT_MSK 0xf000
780
781#define AGG_TX_STATE_SEQ_NUM_POS 16
782#define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
783
784/*
785 * REPLY_TX = 0x1c (response)
786 */
787struct iwl_tx_resp {
788 u8 failure_rts;
789 u8 failure_frame;
790 u8 bt_kill_count;
791 u8 rate;
792 __le32 wireless_media_time;
793 __le32 status; /* TX status (for aggregation status of 1st frame) */
794} __attribute__ ((packed));
795
796/*
797 * REPLY_COMPRESSED_BA = 0xc5 (response only, not a command)
798 */
799struct iwl_compressed_ba_resp {
800 __le32 sta_addr_lo32;
801 __le16 sta_addr_hi16;
802 __le16 reserved;
803 u8 sta_id;
804 u8 tid;
805 __le16 ba_seq_ctl;
806 __le32 ba_bitmap0;
807 __le32 ba_bitmap1;
808 __le16 scd_flow;
809 __le16 scd_ssn;
810} __attribute__ ((packed));
811
812/*
813 * REPLY_TX_PWR_TABLE_CMD = 0x97 (command, has simple generic response)
814 */
815struct iwl_txpowertable_cmd {
816 u8 band; /* 0: 5 GHz, 1: 2.4 GHz */
817 u8 reserved;
818 __le16 channel;
819 struct iwl_power_per_rate power[IWL_MAX_RATES];
820} __attribute__ ((packed));
821
822struct iwl_rate_scaling_info {
823 __le16 rate_n_flags;
824 u8 try_cnt;
825 u8 next_rate_index;
826} __attribute__ ((packed));
827
828/**
829 * struct iwl_rate_scaling_cmd - Rate Scaling Command & Response
830 *
831 * REPLY_RATE_SCALE = 0x47 (command, has simple generic response)
832 *
833 * NOTE: The table of rates passed to the uCode via the
834 * RATE_SCALE command sets up the corresponding order of
835 * rates used for all related commands, including rate
836 * masks, etc.
837 *
838 * For example, if you set 9MB (PLCP 0x0f) as the first
839 * rate in the rate table, the bit mask for that rate
840 * when passed through ofdm_basic_rates on the REPLY_RXON
841 * command would be bit 0 (1<<0)
842 */
843struct iwl_rate_scaling_cmd {
844 u8 table_id;
845 u8 reserved[3];
846 struct iwl_rate_scaling_info table[IWL_MAX_RATES];
847} __attribute__ ((packed));
848
849/*
850 * REPLY_BT_CONFIG = 0x9b (command, has simple generic response)
851 */
852struct iwl_bt_cmd {
853 u8 flags;
854 u8 lead_time;
855 u8 max_kill;
856 u8 reserved;
857 __le32 kill_ack_mask;
858 __le32 kill_cts_mask;
859} __attribute__ ((packed));
860
861/******************************************************************************
862 * (6)
863 * Spectrum Management (802.11h) Commands, Responses, Notifications:
864 *
865 *****************************************************************************/
866
867/*
868 * Spectrum Management
869 */
870#define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK | \
871 RXON_FILTER_CTL2HOST_MSK | \
872 RXON_FILTER_ACCEPT_GRP_MSK | \
873 RXON_FILTER_DIS_DECRYPT_MSK | \
874 RXON_FILTER_DIS_GRP_DECRYPT_MSK | \
875 RXON_FILTER_ASSOC_MSK | \
876 RXON_FILTER_BCON_AWARE_MSK)
877
878struct iwl_measure_channel {
879 __le32 duration; /* measurement duration in extended beacon
880 * format */
881 u8 channel; /* channel to measure */
882 u8 type; /* see enum iwl_measure_type */
883 __le16 reserved;
884} __attribute__ ((packed));
885
886/*
887 * REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74 (command)
888 */
889struct iwl_spectrum_cmd {
890 __le16 len; /* number of bytes starting from token */
891 u8 token; /* token id */
892 u8 id; /* measurement id -- 0 or 1 */
893 u8 origin; /* 0 = TGh, 1 = other, 2 = TGk */
894 u8 periodic; /* 1 = periodic */
895 __le16 path_loss_timeout;
896 __le32 start_time; /* start time in extended beacon format */
897 __le32 reserved2;
898 __le32 flags; /* rxon flags */
899 __le32 filter_flags; /* rxon filter flags */
900 __le16 channel_count; /* minimum 1, maximum 10 */
901 __le16 reserved3;
902 struct iwl_measure_channel channels[10];
903} __attribute__ ((packed));
904
905/*
906 * REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74 (response)
907 */
908struct iwl_spectrum_resp {
909 u8 token;
910 u8 id; /* id of the prior command replaced, or 0xff */
911 __le16 status; /* 0 - command will be handled
912 * 1 - cannot handle (conflicts with another
913 * measurement) */
914} __attribute__ ((packed));
915
916enum iwl_measurement_state {
917 IWL_MEASUREMENT_START = 0,
918 IWL_MEASUREMENT_STOP = 1,
919};
920
921enum iwl_measurement_status {
922 IWL_MEASUREMENT_OK = 0,
923 IWL_MEASUREMENT_CONCURRENT = 1,
924 IWL_MEASUREMENT_CSA_CONFLICT = 2,
925 IWL_MEASUREMENT_TGH_CONFLICT = 3,
926 /* 4-5 reserved */
927 IWL_MEASUREMENT_STOPPED = 6,
928 IWL_MEASUREMENT_TIMEOUT = 7,
929 IWL_MEASUREMENT_PERIODIC_FAILED = 8,
930};
931
932#define NUM_ELEMENTS_IN_HISTOGRAM 8
933
934struct iwl_measurement_histogram {
935 __le32 ofdm[NUM_ELEMENTS_IN_HISTOGRAM]; /* in 0.8usec counts */
936 __le32 cck[NUM_ELEMENTS_IN_HISTOGRAM]; /* in 1usec counts */
937} __attribute__ ((packed));
938
939/* clear channel availability counters */
940struct iwl_measurement_cca_counters {
941 __le32 ofdm;
942 __le32 cck;
943} __attribute__ ((packed));
944
945enum iwl_measure_type {
946 IWL_MEASURE_BASIC = (1 << 0),
947 IWL_MEASURE_CHANNEL_LOAD = (1 << 1),
948 IWL_MEASURE_HISTOGRAM_RPI = (1 << 2),
949 IWL_MEASURE_HISTOGRAM_NOISE = (1 << 3),
950 IWL_MEASURE_FRAME = (1 << 4),
951 /* bits 5:6 are reserved */
952 IWL_MEASURE_IDLE = (1 << 7),
953};
954
955/*
956 * SPECTRUM_MEASURE_NOTIFICATION = 0x75 (notification only, not a command)
957 */
958struct iwl_spectrum_notification {
959 u8 id; /* measurement id -- 0 or 1 */
960 u8 token;
961 u8 channel_index; /* index in measurement channel list */
962 u8 state; /* 0 - start, 1 - stop */
963 __le32 start_time; /* lower 32-bits of TSF */
964 u8 band; /* 0 - 5.2GHz, 1 - 2.4GHz */
965 u8 channel;
966 u8 type; /* see enum iwl_measurement_type */
967 u8 reserved1;
968 /* NOTE: cca_ofdm, cca_cck, basic_type, and histogram are only only
969 * valid if applicable for measurement type requested. */
970 __le32 cca_ofdm; /* cca fraction time in 40Mhz clock periods */
971 __le32 cca_cck; /* cca fraction time in 44Mhz clock periods */
972 __le32 cca_time; /* channel load time in usecs */
973 u8 basic_type; /* 0 - bss, 1 - ofdm preamble, 2 -
974 * unidentified */
975 u8 reserved2[3];
976 struct iwl_measurement_histogram histogram;
977 __le32 stop_time; /* lower 32-bits of TSF */
978 __le32 status; /* see iwl_measurement_status */
979} __attribute__ ((packed));
980
981/******************************************************************************
982 * (7)
983 * Power Management Commands, Responses, Notifications:
984 *
985 *****************************************************************************/
986
987/**
988 * struct iwl_powertable_cmd - Power Table Command
989 * @flags: See below:
990 *
991 * POWER_TABLE_CMD = 0x77 (command, has simple generic response)
992 *
993 * PM allow:
994 * bit 0 - '0' Driver not allow power management
995 * '1' Driver allow PM (use rest of parameters)
996 * uCode send sleep notifications:
997 * bit 1 - '0' Don't send sleep notification
998 * '1' send sleep notification (SEND_PM_NOTIFICATION)
999 * Sleep over DTIM
1000 * bit 2 - '0' PM have to walk up every DTIM
1001 * '1' PM could sleep over DTIM till listen Interval.
1002 * PCI power managed
1003 * bit 3 - '0' (PCI_LINK_CTRL & 0x1)
1004 * '1' !(PCI_LINK_CTRL & 0x1)
1005 * Force sleep Modes
1006 * bit 31/30- '00' use both mac/xtal sleeps
1007 * '01' force Mac sleep
1008 * '10' force xtal sleep
1009 * '11' Illegal set
1010 *
1011 * NOTE: if sleep_interval[SLEEP_INTRVL_TABLE_SIZE-1] > DTIM period then
1012 * ucode assume sleep over DTIM is allowed and we don't need to wakeup
1013 * for every DTIM.
1014 */
1015#define IWL_POWER_VEC_SIZE 5
1016
1017#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK __constant_cpu_to_le32(1<<0)
1018#define IWL_POWER_SLEEP_OVER_DTIM_MSK __constant_cpu_to_le32(1<<2)
1019#define IWL_POWER_PCI_PM_MSK __constant_cpu_to_le32(1<<3)
1020struct iwl_powertable_cmd {
1021 __le32 flags;
1022 __le32 rx_data_timeout;
1023 __le32 tx_data_timeout;
1024 __le32 sleep_interval[IWL_POWER_VEC_SIZE];
1025} __attribute__((packed));
1026
1027/*
1028 * PM_SLEEP_NOTIFICATION = 0x7A (notification only, not a command)
1029 * 3945 and 4965 identical.
1030 */
1031struct iwl_sleep_notification {
1032 u8 pm_sleep_mode;
1033 u8 pm_wakeup_src;
1034 __le16 reserved;
1035 __le32 sleep_time;
1036 __le32 tsf_low;
1037 __le32 bcon_timer;
1038} __attribute__ ((packed));
1039
1040/* Sleep states. 3945 and 4965 identical. */
1041enum {
1042 IWL_PM_NO_SLEEP = 0,
1043 IWL_PM_SLP_MAC = 1,
1044 IWL_PM_SLP_FULL_MAC_UNASSOCIATE = 2,
1045 IWL_PM_SLP_FULL_MAC_CARD_STATE = 3,
1046 IWL_PM_SLP_PHY = 4,
1047 IWL_PM_SLP_REPENT = 5,
1048 IWL_PM_WAKEUP_BY_TIMER = 6,
1049 IWL_PM_WAKEUP_BY_DRIVER = 7,
1050 IWL_PM_WAKEUP_BY_RFKILL = 8,
1051 /* 3 reserved */
1052 IWL_PM_NUM_OF_MODES = 12,
1053};
1054
1055/*
1056 * REPLY_CARD_STATE_CMD = 0xa0 (command, has simple generic response)
1057 */
1058#define CARD_STATE_CMD_DISABLE 0x00 /* Put card to sleep */
1059#define CARD_STATE_CMD_ENABLE 0x01 /* Wake up card */
1060#define CARD_STATE_CMD_HALT 0x02 /* Power down permanently */
1061struct iwl_card_state_cmd {
1062 __le32 status; /* CARD_STATE_CMD_* request new power state */
1063} __attribute__ ((packed));
1064
1065/*
1066 * CARD_STATE_NOTIFICATION = 0xa1 (notification only, not a command)
1067 */
1068struct iwl_card_state_notif {
1069 __le32 flags;
1070} __attribute__ ((packed));
1071
1072#define HW_CARD_DISABLED 0x01
1073#define SW_CARD_DISABLED 0x02
1074#define RF_CARD_DISABLED 0x04
1075#define RXON_CARD_DISABLED 0x10
1076
1077struct iwl_ct_kill_config {
1078 __le32 reserved;
1079 __le32 critical_temperature_M;
1080 __le32 critical_temperature_R;
1081} __attribute__ ((packed));
1082
1083/******************************************************************************
1084 * (8)
1085 * Scan Commands, Responses, Notifications:
1086 *
1087 *****************************************************************************/
1088
1089struct iwl_scan_channel {
1090 /* type is defined as:
1091 * 0:0 active (0 - passive)
1092 * 1:4 SSID direct
1093 * If 1 is set then corresponding SSID IE is transmitted in probe
1094 * 5:7 reserved
1095 */
1096 u8 type;
1097 u8 channel;
1098 struct iwl_tx_power tpc;
1099 __le16 active_dwell;
1100 __le16 passive_dwell;
1101} __attribute__ ((packed));
1102
1103struct iwl_ssid_ie {
1104 u8 id;
1105 u8 len;
1106 u8 ssid[32];
1107} __attribute__ ((packed));
1108
1109#define PROBE_OPTION_MAX 0x4
1110#define TX_CMD_LIFE_TIME_INFINITE __constant_cpu_to_le32(0xFFFFFFFF)
1111#define IWL_GOOD_CRC_TH __constant_cpu_to_le16(1)
1112#define IWL_MAX_SCAN_SIZE 1024
1113
1114/*
1115 * REPLY_SCAN_CMD = 0x80 (command)
1116 */
1117struct iwl_scan_cmd {
1118 __le16 len;
1119 u8 reserved0;
1120 u8 channel_count;
1121 __le16 quiet_time; /* dwell only this long on quiet chnl
1122 * (active scan) */
1123 __le16 quiet_plcp_th; /* quiet chnl is < this # pkts (typ. 1) */
1124 __le16 good_CRC_th; /* passive -> active promotion threshold */
1125 __le16 reserved1;
1126 __le32 max_out_time; /* max usec to be out of associated (service)
1127 * chnl */
1128 __le32 suspend_time; /* pause scan this long when returning to svc
1129 * chnl.
1130 * 3945 -- 31:24 # beacons, 19:0 additional usec,
1131 * 4965 -- 31:22 # beacons, 21:0 additional usec.
1132 */
1133 __le32 flags;
1134 __le32 filter_flags;
1135
1136 struct iwl_tx_cmd tx_cmd;
1137 struct iwl_ssid_ie direct_scan[PROBE_OPTION_MAX];
1138
1139 u8 data[0];
1140 /*
1141 * The channels start after the probe request payload and are of type:
1142 *
1143 * struct iwl_scan_channel channels[0];
1144 *
1145 * NOTE: Only one band of channels can be scanned per pass. You
1146 * can not mix 2.4GHz channels and 5.2GHz channels and must
1147 * request a scan multiple times (not concurrently)
1148 *
1149 */
1150} __attribute__ ((packed));
1151
1152/* Can abort will notify by complete notification with abort status. */
1153#define CAN_ABORT_STATUS __constant_cpu_to_le32(0x1)
1154/* complete notification statuses */
1155#define ABORT_STATUS 0x2
1156
1157/*
1158 * REPLY_SCAN_CMD = 0x80 (response)
1159 */
1160struct iwl_scanreq_notification {
1161 __le32 status; /* 1: okay, 2: cannot fulfill request */
1162} __attribute__ ((packed));
1163
1164/*
1165 * SCAN_START_NOTIFICATION = 0x82 (notification only, not a command)
1166 */
1167struct iwl_scanstart_notification {
1168 __le32 tsf_low;
1169 __le32 tsf_high;
1170 __le32 beacon_timer;
1171 u8 channel;
1172 u8 band;
1173 u8 reserved[2];
1174 __le32 status;
1175} __attribute__ ((packed));
1176
1177#define SCAN_OWNER_STATUS 0x1;
1178#define MEASURE_OWNER_STATUS 0x2;
1179
1180#define NUMBER_OF_STATISTICS 1 /* first __le32 is good CRC */
1181/*
1182 * SCAN_RESULTS_NOTIFICATION = 0x83 (notification only, not a command)
1183 */
1184struct iwl_scanresults_notification {
1185 u8 channel;
1186 u8 band;
1187 u8 reserved[2];
1188 __le32 tsf_low;
1189 __le32 tsf_high;
1190 __le32 statistics[NUMBER_OF_STATISTICS];
1191} __attribute__ ((packed));
1192
1193/*
1194 * SCAN_COMPLETE_NOTIFICATION = 0x84 (notification only, not a command)
1195 */
1196struct iwl_scancomplete_notification {
1197 u8 scanned_channels;
1198 u8 status;
1199 u8 reserved;
1200 u8 last_channel;
1201 __le32 tsf_low;
1202 __le32 tsf_high;
1203} __attribute__ ((packed));
1204
1205
1206/******************************************************************************
1207 * (9)
1208 * IBSS/AP Commands and Notifications:
1209 *
1210 *****************************************************************************/
1211
1212/*
1213 * BEACON_NOTIFICATION = 0x90 (notification only, not a command)
1214 */
1215struct iwl_beacon_notif {
1216 struct iwl_tx_resp beacon_notify_hdr;
1217 __le32 low_tsf;
1218 __le32 high_tsf;
1219 __le32 ibss_mgr_status;
1220} __attribute__ ((packed));
1221
1222/*
1223 * REPLY_TX_BEACON = 0x91 (command, has simple generic response)
1224 */
1225struct iwl_tx_beacon_cmd {
1226 struct iwl_tx_cmd tx;
1227 __le16 tim_idx;
1228 u8 tim_size;
1229 u8 reserved1;
1230 struct ieee80211_hdr frame[0]; /* beacon frame */
1231} __attribute__ ((packed));
1232
1233/******************************************************************************
1234 * (10)
1235 * Statistics Commands and Notifications:
1236 *
1237 *****************************************************************************/
1238
1239#define IWL_TEMP_CONVERT 260
1240
1241#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
1242#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
1243#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
1244
1245/* Used for passing to driver number of successes and failures per rate */
1246struct rate_histogram {
1247 union {
1248 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
1249 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
1250 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
1251 } success;
1252 union {
1253 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
1254 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
1255 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
1256 } failed;
1257} __attribute__ ((packed));
1258
1259/* statistics command response */
1260
1261struct statistics_rx_phy {
1262 __le32 ina_cnt;
1263 __le32 fina_cnt;
1264 __le32 plcp_err;
1265 __le32 crc32_err;
1266 __le32 overrun_err;
1267 __le32 early_overrun_err;
1268 __le32 crc32_good;
1269 __le32 false_alarm_cnt;
1270 __le32 fina_sync_err_cnt;
1271 __le32 sfd_timeout;
1272 __le32 fina_timeout;
1273 __le32 unresponded_rts;
1274 __le32 rxe_frame_limit_overrun;
1275 __le32 sent_ack_cnt;
1276 __le32 sent_cts_cnt;
1277} __attribute__ ((packed));
1278
1279struct statistics_rx_non_phy {
1280 __le32 bogus_cts; /* CTS received when not expecting CTS */
1281 __le32 bogus_ack; /* ACK received when not expecting ACK */
1282 __le32 non_bssid_frames; /* number of frames with BSSID that
1283 * doesn't belong to the STA BSSID */
1284 __le32 filtered_frames; /* count frames that were dumped in the
1285 * filtering process */
1286 __le32 non_channel_beacons; /* beacons with our bss id but not on
1287 * our serving channel */
1288} __attribute__ ((packed));
1289
1290struct statistics_rx {
1291 struct statistics_rx_phy ofdm;
1292 struct statistics_rx_phy cck;
1293 struct statistics_rx_non_phy general;
1294} __attribute__ ((packed));
1295
1296struct statistics_tx {
1297 __le32 preamble_cnt;
1298 __le32 rx_detected_cnt;
1299 __le32 bt_prio_defer_cnt;
1300 __le32 bt_prio_kill_cnt;
1301 __le32 few_bytes_cnt;
1302 __le32 cts_timeout;
1303 __le32 ack_timeout;
1304 __le32 expected_ack_cnt;
1305 __le32 actual_ack_cnt;
1306} __attribute__ ((packed));
1307
1308struct statistics_dbg {
1309 __le32 burst_check;
1310 __le32 burst_count;
1311 __le32 reserved[4];
1312} __attribute__ ((packed));
1313
1314struct statistics_div {
1315 __le32 tx_on_a;
1316 __le32 tx_on_b;
1317 __le32 exec_time;
1318 __le32 probe_time;
1319} __attribute__ ((packed));
1320
1321struct statistics_general {
1322 __le32 temperature;
1323 struct statistics_dbg dbg;
1324 __le32 sleep_time;
1325 __le32 slots_out;
1326 __le32 slots_idle;
1327 __le32 ttl_timestamp;
1328 struct statistics_div div;
1329} __attribute__ ((packed));
1330
1331/*
1332 * REPLY_STATISTICS_CMD = 0x9c,
1333 * 3945 and 4965 identical.
1334 *
1335 * This command triggers an immediate response containing uCode statistics.
1336 * The response is in the same format as STATISTICS_NOTIFICATION 0x9d, below.
1337 *
1338 * If the CLEAR_STATS configuration flag is set, uCode will clear its
1339 * internal copy of the statistics (counters) after issuing the response.
1340 * This flag does not affect STATISTICS_NOTIFICATIONs after beacons (see below).
1341 *
1342 * If the DISABLE_NOTIF configuration flag is set, uCode will not issue
1343 * STATISTICS_NOTIFICATIONs after received beacons (see below). This flag
1344 * does not affect the response to the REPLY_STATISTICS_CMD 0x9c itself.
1345 */
1346#define IWL_STATS_CONF_CLEAR_STATS __constant_cpu_to_le32(0x1) /* see above */
1347#define IWL_STATS_CONF_DISABLE_NOTIF __constant_cpu_to_le32(0x2)/* see above */
1348struct iwl_statistics_cmd {
1349 __le32 configuration_flags; /* IWL_STATS_CONF_* */
1350} __attribute__ ((packed));
1351
1352/*
1353 * STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
1354 *
1355 * By default, uCode issues this notification after receiving a beacon
1356 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
1357 * REPLY_STATISTICS_CMD 0x9c, above.
1358 *
1359 * Statistics counters continue to increment beacon after beacon, but are
1360 * cleared when changing channels or when driver issues REPLY_STATISTICS_CMD
1361 * 0x9c with CLEAR_STATS bit set (see above).
1362 *
1363 * uCode also issues this notification during scans. uCode clears statistics
1364 * appropriately so that each notification contains statistics for only the
1365 * one channel that has just been scanned.
1366 */
1367#define STATISTICS_REPLY_FLG_BAND_24G_MSK __constant_cpu_to_le32(0x2)
1368#define STATISTICS_REPLY_FLG_FAT_MODE_MSK __constant_cpu_to_le32(0x8)
1369struct iwl_notif_statistics {
1370 __le32 flag;
1371 struct statistics_rx rx;
1372 struct statistics_tx tx;
1373 struct statistics_general general;
1374} __attribute__ ((packed));
1375
1376
1377/*
1378 * MISSED_BEACONS_NOTIFICATION = 0xa2 (notification only, not a command)
1379 */
1380/* if ucode missed CONSECUTIVE_MISSED_BCONS_TH beacons in a row,
1381 * then this notification will be sent. */
1382#define CONSECUTIVE_MISSED_BCONS_TH 20
1383
1384struct iwl_missed_beacon_notif {
1385 __le32 consequtive_missed_beacons;
1386 __le32 total_missed_becons;
1387 __le32 num_expected_beacons;
1388 __le32 num_recvd_beacons;
1389} __attribute__ ((packed));
1390
1391/******************************************************************************
1392 * (11)
1393 * Rx Calibration Commands:
1394 *
1395 *****************************************************************************/
1396
1397#define PHY_CALIBRATE_DIFF_GAIN_CMD (7)
1398#define HD_TABLE_SIZE (11)
1399
1400struct iwl_sensitivity_cmd {
1401 __le16 control;
1402 __le16 table[HD_TABLE_SIZE];
1403} __attribute__ ((packed));
1404
1405struct iwl_calibration_cmd {
1406 u8 opCode;
1407 u8 flags;
1408 __le16 reserved;
1409 s8 diff_gain_a;
1410 s8 diff_gain_b;
1411 s8 diff_gain_c;
1412 u8 reserved1;
1413} __attribute__ ((packed));
1414
1415/******************************************************************************
1416 * (12)
1417 * Miscellaneous Commands:
1418 *
1419 *****************************************************************************/
1420
1421/*
1422 * LEDs Command & Response
1423 * REPLY_LEDS_CMD = 0x48 (command, has simple generic response)
1424 *
1425 * For each of 3 possible LEDs (Activity/Link/Tech, selected by "id" field),
1426 * this command turns it on or off, or sets up a periodic blinking cycle.
1427 */
1428struct iwl_led_cmd {
1429 __le32 interval; /* "interval" in uSec */
1430 u8 id; /* 1: Activity, 2: Link, 3: Tech */
1431 u8 off; /* # intervals off while blinking;
1432 * "0", with >0 "on" value, turns LED on */
1433 u8 on; /* # intervals on while blinking;
1434 * "0", regardless of "off", turns LED off */
1435 u8 reserved;
1436} __attribute__ ((packed));
1437
1438/******************************************************************************
1439 * (13)
1440 * Union of all expected notifications/responses:
1441 *
1442 *****************************************************************************/
1443
1444struct iwl_rx_packet {
1445 __le32 len;
1446 struct iwl_cmd_header hdr;
1447 union {
1448 struct iwl_alive_resp alive_frame;
1449 struct iwl_rx_frame rx_frame;
1450 struct iwl_tx_resp tx_resp;
1451 struct iwl_spectrum_notification spectrum_notif;
1452 struct iwl_csa_notification csa_notif;
1453 struct iwl_error_resp err_resp;
1454 struct iwl_card_state_notif card_state_notif;
1455 struct iwl_beacon_notif beacon_status;
1456 struct iwl_add_sta_resp add_sta;
1457 struct iwl_sleep_notification sleep_notif;
1458 struct iwl_spectrum_resp spectrum;
1459 struct iwl_notif_statistics stats;
1460 __le32 status;
1461 u8 raw[0];
1462 } u;
1463} __attribute__ ((packed));
1464
1465#define IWL_RX_FRAME_SIZE (4 + sizeof(struct iwl_rx_frame))
1466
1467#endif /* __iwl_3945_commands_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-debug.h b/drivers/net/wireless/iwlwifi/iwl-3945-debug.h
index 72318d78957e..72318d78957e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debug.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-debug.h
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
index 90d4249fa7f2..0a5a08d19f55 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
@@ -64,6 +64,633 @@
64#ifndef __iwl_3945_hw__ 64#ifndef __iwl_3945_hw__
65#define __iwl_3945_hw__ 65#define __iwl_3945_hw__
66 66
67/* uCode queue management definitions */
68#define IWL_CMD_QUEUE_NUM 4
69#define IWL_CMD_FIFO_NUM 4
70#define IWL_BACK_QUEUE_FIRST_ID 7
71
72/* Tx rates */
73#define IWL_CCK_RATES 4
74#define IWL_OFDM_RATES 8
75
76#define IWL_HT_RATES 0
77
78#define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
79
80/* Time constants */
81#define SHORT_SLOT_TIME 9
82#define LONG_SLOT_TIME 20
83
84/* RSSI to dBm */
85#define IWL_RSSI_OFFSET 95
86
87/*
88 * This file defines EEPROM related constants, enums, and inline functions.
89 *
90 */
91
92#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
93#define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */
94/* EEPROM field values */
95#define ANTENNA_SWITCH_NORMAL 0
96#define ANTENNA_SWITCH_INVERSE 1
97
98enum {
99 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
100 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
101 /* Bit 2 Reserved */
102 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
103 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
104 EEPROM_CHANNEL_WIDE = (1 << 5),
105 EEPROM_CHANNEL_NARROW = (1 << 6),
106 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
107};
108
109/* EEPROM field lengths */
110#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
111
112/* EEPROM field lengths */
113#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
114#define EEPROM_REGULATORY_SKU_ID_LENGTH 4
115#define EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH 14
116#define EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH 13
117#define EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH 12
118#define EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH 11
119#define EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH 6
120
121#define EEPROM_REGULATORY_CHANNELS_LENGTH ( \
122 EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH + \
123 EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH + \
124 EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH + \
125 EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH + \
126 EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH)
127
128#define EEPROM_REGULATORY_NUMBER_OF_BANDS 5
129
130/* SKU Capabilities */
131#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
132#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
133#define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7)
134
135/* *regulatory* channel data from eeprom, one for each channel */
136struct iwl_eeprom_channel {
137 u8 flags; /* flags copied from EEPROM */
138 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
139} __attribute__ ((packed));
140
141/*
142 * Mapping of a Tx power level, at factory calibration temperature,
143 * to a radio/DSP gain table index.
144 * One for each of 5 "sample" power levels in each band.
145 * v_det is measured at the factory, using the 3945's built-in power amplifier
146 * (PA) output voltage detector. This same detector is used during Tx of
147 * long packets in normal operation to provide feedback as to proper output
148 * level.
149 * Data copied from EEPROM.
150 */
151struct iwl_eeprom_txpower_sample {
152 u8 gain_index; /* index into power (gain) setup table ... */
153 s8 power; /* ... for this pwr level for this chnl group */
154 u16 v_det; /* PA output voltage */
155} __attribute__ ((packed));
156
157/*
158 * Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
159 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
160 * Tx power setup code interpolates between the 5 "sample" power levels
161 * to determine the nominal setup for a requested power level.
162 * Data copied from EEPROM.
163 * DO NOT ALTER THIS STRUCTURE!!!
164 */
165struct iwl_eeprom_txpower_group {
166 struct iwl_eeprom_txpower_sample samples[5]; /* 5 power levels */
167 s32 a, b, c, d, e; /* coefficients for voltage->power
168 * formula (signed) */
169 s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
170 * frequency (signed) */
171 s8 saturation_power; /* highest power possible by h/w in this
172 * band */
173 u8 group_channel; /* "representative" channel # in this band */
174 s16 temperature; /* h/w temperature at factory calib this band
175 * (signed) */
176} __attribute__ ((packed));
177
178/*
179 * Temperature-based Tx-power compensation data, not band-specific.
180 * These coefficients are use to modify a/b/c/d/e coeffs based on
181 * difference between current temperature and factory calib temperature.
182 * Data copied from EEPROM.
183 */
184struct iwl_eeprom_temperature_corr {
185 u32 Ta;
186 u32 Tb;
187 u32 Tc;
188 u32 Td;
189 u32 Te;
190} __attribute__ ((packed));
191
192struct iwl_eeprom {
193 u8 reserved0[16];
194#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
195 u16 device_id; /* abs.ofs: 16 */
196 u8 reserved1[2];
197#define EEPROM_PMC (2*0x0A) /* 2 bytes */
198 u16 pmc; /* abs.ofs: 20 */
199 u8 reserved2[20];
200#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
201 u8 mac_address[6]; /* abs.ofs: 42 */
202 u8 reserved3[58];
203#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
204 u16 board_revision; /* abs.ofs: 106 */
205 u8 reserved4[11];
206#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
207 u8 board_pba_number[9]; /* abs.ofs: 119 */
208 u8 reserved5[8];
209#define EEPROM_VERSION (2*0x44) /* 2 bytes */
210 u16 version; /* abs.ofs: 136 */
211#define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */
212 u8 sku_cap; /* abs.ofs: 138 */
213#define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */
214 u8 leds_mode; /* abs.ofs: 139 */
215#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
216 u16 oem_mode;
217#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
218 u16 wowlan_mode; /* abs.ofs: 142 */
219#define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */
220 u16 leds_time_interval; /* abs.ofs: 144 */
221#define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */
222 u8 leds_off_time; /* abs.ofs: 146 */
223#define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */
224 u8 leds_on_time; /* abs.ofs: 147 */
225#define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */
226 u8 almgor_m_version; /* abs.ofs: 148 */
227#define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */
228 u8 antenna_switch_type; /* abs.ofs: 149 */
229 u8 reserved6[42];
230#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
231 u8 sku_id[4]; /* abs.ofs: 192 */
232#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
233 u16 band_1_count; /* abs.ofs: 196 */
234#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
235 struct iwl_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */
236#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
237 u16 band_2_count; /* abs.ofs: 226 */
238#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
239 struct iwl_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */
240#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
241 u16 band_3_count; /* abs.ofs: 254 */
242#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
243 struct iwl_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */
244#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
245 u16 band_4_count; /* abs.ofs: 280 */
246#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
247 struct iwl_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */
248#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
249 u16 band_5_count; /* abs.ofs: 304 */
250#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
251 struct iwl_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */
252
253 u8 reserved9[194];
254
255#define EEPROM_TXPOWER_CALIB_GROUP0 0x200
256#define EEPROM_TXPOWER_CALIB_GROUP1 0x240
257#define EEPROM_TXPOWER_CALIB_GROUP2 0x280
258#define EEPROM_TXPOWER_CALIB_GROUP3 0x2c0
259#define EEPROM_TXPOWER_CALIB_GROUP4 0x300
260#define IWL_NUM_TX_CALIB_GROUPS 5
261 struct iwl_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS];
262/* abs.ofs: 512 */
263#define EEPROM_CALIB_TEMPERATURE_CORRECT 0x340
264 struct iwl_eeprom_temperature_corr corrections; /* abs.ofs: 832 */
265 u8 reserved16[172]; /* fill out to full 1024 byte block */
266} __attribute__ ((packed));
267
268#define IWL_EEPROM_IMAGE_SIZE 1024
269
270
271#include "iwl-3945-commands.h"
272
273#define PCI_LINK_CTRL 0x0F0
274#define PCI_POWER_SOURCE 0x0C8
275#define PCI_REG_WUM8 0x0E8
276#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
277
278/*=== CSR (control and status registers) ===*/
279#define CSR_BASE (0x000)
280
281#define CSR_SW_VER (CSR_BASE+0x000)
282#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
283#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
284#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
285#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
286#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
287#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
288#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
289#define CSR_GP_CNTRL (CSR_BASE+0x024)
290#define CSR_HW_REV (CSR_BASE+0x028)
291#define CSR_EEPROM_REG (CSR_BASE+0x02c)
292#define CSR_EEPROM_GP (CSR_BASE+0x030)
293#define CSR_GP_UCODE (CSR_BASE+0x044)
294#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
295#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
296#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
297#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
298#define CSR_LED_REG (CSR_BASE+0x094)
299#define CSR_DRAM_INT_TBL_CTL (CSR_BASE+0x0A0)
300#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
301#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
302#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
303
304/* HW I/F configuration */
305#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100)
306#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200)
307#define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
308#define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
309#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
310#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
311#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
312
313/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
314 * acknowledged (reset) by host writing "1" to flagged bits. */
315#define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */
316#define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */
317#define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */
318#define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */
319#define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */
320#define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */
321#define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */
322#define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */
323#define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */
324#define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */
325#define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */
326
327#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
328 CSR_INT_BIT_HW_ERR | \
329 CSR_INT_BIT_FH_TX | \
330 CSR_INT_BIT_SW_ERR | \
331 CSR_INT_BIT_RF_KILL | \
332 CSR_INT_BIT_SW_RX | \
333 CSR_INT_BIT_WAKEUP | \
334 CSR_INT_BIT_ALIVE)
335
336/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
337#define CSR_FH_INT_BIT_ERR (1<<31) /* Error */
338#define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */
339#define CSR_FH_INT_BIT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */
340#define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */
341#define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */
342#define CSR_FH_INT_BIT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */
343#define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */
344#define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */
345
346#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
347 CSR_FH_INT_BIT_RX_CHNL2 | \
348 CSR_FH_INT_BIT_RX_CHNL1 | \
349 CSR_FH_INT_BIT_RX_CHNL0)
350
351#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL6 | \
352 CSR_FH_INT_BIT_TX_CHNL1 | \
353 CSR_FH_INT_BIT_TX_CHNL0 )
354
355
356/* RESET */
357#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
358#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
359#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
360#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
361#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
362
363/* GP (general purpose) CONTROL */
364#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
365#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
366#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
367#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
368
369#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
370
371#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
372#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
373#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
374
375
376/* EEPROM REG */
377#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
378#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
379
380/* EEPROM GP */
381#define CSR_EEPROM_GP_VALID_MSK (0x00000006)
382#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
383#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
384
385/* UCODE DRV GP */
386#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
387#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
388#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
389#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
390
391/* GPIO */
392#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
393#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
394#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
395
396/* GI Chicken Bits */
397#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
398#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
399
400/* CSR_ANA_PLL_CFG */
401#define CSR_ANA_PLL_CFG_SH (0x00880300)
402
403#define CSR_LED_REG_TRUN_ON (0x00000078)
404#define CSR_LED_REG_TRUN_OFF (0x00000038)
405#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
406
407/* DRAM_INT_TBL_CTRL */
408#define CSR_DRAM_INT_TBL_CTRL_EN (1<<31)
409#define CSR_DRAM_INT_TBL_CTRL_WRAP_CHK (1<<27)
410
411/*=== HBUS (Host-side Bus) ===*/
412#define HBUS_BASE (0x400)
413
414#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
415#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
416#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
417#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
418#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
419#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
420#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
421#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
422#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
423
424#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
425
426
427/* SCD (Scheduler) */
428#define SCD_BASE (CSR_BASE + 0x2E00)
429
430#define SCD_MODE_REG (SCD_BASE + 0x000)
431#define SCD_ARASTAT_REG (SCD_BASE + 0x004)
432#define SCD_TXFACT_REG (SCD_BASE + 0x010)
433#define SCD_TXF4MF_REG (SCD_BASE + 0x014)
434#define SCD_TXF5MF_REG (SCD_BASE + 0x020)
435#define SCD_SBYP_MODE_1_REG (SCD_BASE + 0x02C)
436#define SCD_SBYP_MODE_2_REG (SCD_BASE + 0x030)
437
438/*=== FH (data Flow Handler) ===*/
439#define FH_BASE (0x800)
440
441#define FH_CBCC_TABLE (FH_BASE+0x140)
442#define FH_TFDB_TABLE (FH_BASE+0x180)
443#define FH_RCSR_TABLE (FH_BASE+0x400)
444#define FH_RSSR_TABLE (FH_BASE+0x4c0)
445#define FH_TCSR_TABLE (FH_BASE+0x500)
446#define FH_TSSR_TABLE (FH_BASE+0x680)
447
448/* TFDB (Transmit Frame Buffer Descriptor) */
449#define FH_TFDB(_channel, buf) \
450 (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
451#define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
452 (FH_TFDB_TABLE + 0x50 * _channel)
453/* CBCC _channel is [0,2] */
454#define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8)
455#define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00)
456#define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04)
457
458/* RCSR _channel is [0,2] */
459#define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40)
460#define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00)
461#define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04)
462#define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20)
463#define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
464
465#define FH_RSCSR_CHNL0_WPTR (FH_RCSR_WPTR(0))
466
467/* RSSR */
468#define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000)
469#define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004)
470/* TCSR */
471#define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20)
472#define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00)
473#define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04)
474#define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
475/* TSSR */
476#define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000)
477#define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008)
478#define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010)
479/* 18 - reserved */
480
481/* card static random access memory (SRAM) for processor data and instructs */
482#define RTC_INST_LOWER_BOUND (0x000000)
483#define RTC_DATA_LOWER_BOUND (0x800000)
484
485
486/* DBM */
487
488#define ALM_FH_SRVC_CHNL (6)
489
490#define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
491#define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
492
493#define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
494
495#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
496
497#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
498
499#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
500
501#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
502
503#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
504
505#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
506#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
507
508#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
509#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
510
511#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
512
513#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
514
515#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
516#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
517
518#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
519
520#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
521
522#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
523#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
524
525#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
526
527#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
528#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
529
530#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
531#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
532
533#define ALM_TB_MAX_BYTES_COUNT (0xFFF0)
534
535#define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
536 ((1LU << _channel) << 24)
537#define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
538 ((1LU << _channel) << 16)
539
540#define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
541 (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
542 ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
543#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
544#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
545
546#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
547
548#define TFD_QUEUE_MIN 0
549#define TFD_QUEUE_MAX 6
550#define TFD_QUEUE_SIZE_MAX (256)
551
552/* spectrum and channel data structures */
553#define IWL_NUM_SCAN_RATES (2)
554
555#define IWL_SCAN_FLAG_24GHZ (1<<0)
556#define IWL_SCAN_FLAG_52GHZ (1<<1)
557#define IWL_SCAN_FLAG_ACTIVE (1<<2)
558#define IWL_SCAN_FLAG_DIRECT (1<<3)
559
560#define IWL_MAX_CMD_SIZE 1024
561
562#define IWL_DEFAULT_TX_RETRY 15
563#define IWL_MAX_TX_RETRY 16
564
565/*********************************************/
566
567#define RFD_SIZE 4
568#define NUM_TFD_CHUNKS 4
569
570#define RX_QUEUE_SIZE 256
571#define RX_QUEUE_MASK 255
572#define RX_QUEUE_SIZE_LOG 8
573
574/* QoS definitions */
575
576#define CW_MIN_OFDM 15
577#define CW_MAX_OFDM 1023
578#define CW_MIN_CCK 31
579#define CW_MAX_CCK 1023
580
581#define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM
582#define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM
583#define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
584#define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1)
585
586#define QOS_TX0_CW_MIN_CCK CW_MIN_CCK
587#define QOS_TX1_CW_MIN_CCK CW_MIN_CCK
588#define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1)
589#define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1)
590
591#define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM
592#define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM
593#define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM
594#define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
595
596#define QOS_TX0_CW_MAX_CCK CW_MAX_CCK
597#define QOS_TX1_CW_MAX_CCK CW_MAX_CCK
598#define QOS_TX2_CW_MAX_CCK CW_MIN_CCK
599#define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1)
600
601#define QOS_TX0_AIFS 3
602#define QOS_TX1_AIFS 7
603#define QOS_TX2_AIFS 2
604#define QOS_TX3_AIFS 2
605
606#define QOS_TX0_ACM 0
607#define QOS_TX1_ACM 0
608#define QOS_TX2_ACM 0
609#define QOS_TX3_ACM 0
610
611#define QOS_TX0_TXOP_LIMIT_CCK 0
612#define QOS_TX1_TXOP_LIMIT_CCK 0
613#define QOS_TX2_TXOP_LIMIT_CCK 6016
614#define QOS_TX3_TXOP_LIMIT_CCK 3264
615
616#define QOS_TX0_TXOP_LIMIT_OFDM 0
617#define QOS_TX1_TXOP_LIMIT_OFDM 0
618#define QOS_TX2_TXOP_LIMIT_OFDM 3008
619#define QOS_TX3_TXOP_LIMIT_OFDM 1504
620
621#define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM
622#define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM
623#define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM
624#define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM
625
626#define DEF_TX0_CW_MIN_CCK CW_MIN_CCK
627#define DEF_TX1_CW_MIN_CCK CW_MIN_CCK
628#define DEF_TX2_CW_MIN_CCK CW_MIN_CCK
629#define DEF_TX3_CW_MIN_CCK CW_MIN_CCK
630
631#define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM
632#define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM
633#define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM
634#define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM
635
636#define DEF_TX0_CW_MAX_CCK CW_MAX_CCK
637#define DEF_TX1_CW_MAX_CCK CW_MAX_CCK
638#define DEF_TX2_CW_MAX_CCK CW_MAX_CCK
639#define DEF_TX3_CW_MAX_CCK CW_MAX_CCK
640
641#define DEF_TX0_AIFS (2)
642#define DEF_TX1_AIFS (2)
643#define DEF_TX2_AIFS (2)
644#define DEF_TX3_AIFS (2)
645
646#define DEF_TX0_ACM 0
647#define DEF_TX1_ACM 0
648#define DEF_TX2_ACM 0
649#define DEF_TX3_ACM 0
650
651#define DEF_TX0_TXOP_LIMIT_CCK 0
652#define DEF_TX1_TXOP_LIMIT_CCK 0
653#define DEF_TX2_TXOP_LIMIT_CCK 0
654#define DEF_TX3_TXOP_LIMIT_CCK 0
655
656#define DEF_TX0_TXOP_LIMIT_OFDM 0
657#define DEF_TX1_TXOP_LIMIT_OFDM 0
658#define DEF_TX2_TXOP_LIMIT_OFDM 0
659#define DEF_TX3_TXOP_LIMIT_OFDM 0
660
661#define QOS_QOS_SETS 3
662#define QOS_PARAM_SET_ACTIVE 0
663#define QOS_PARAM_SET_DEF_CCK 1
664#define QOS_PARAM_SET_DEF_OFDM 2
665
666#define CTRL_QOS_NO_ACK (0x0020)
667#define DCT_FLAG_EXT_QOS_ENABLED (0x10)
668
669#define U32_PAD(n) ((4-(n))&0x3)
670
671/*
672 * Generic queue structure
673 *
674 * Contains common data for Rx and Tx queues
675 */
676#define TFD_CTL_COUNT_SET(n) (n<<24)
677#define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7)
678#define TFD_CTL_PAD_SET(n) (n<<28)
679#define TFD_CTL_PAD_GET(ctl) (ctl>>28)
680
681#define TFD_TX_CMD_SLOTS 256
682#define TFD_CMD_SLOTS 32
683
684#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
685 sizeof(struct iwl_cmd_meta))
686
687/*
688 * RX related structures and functions
689 */
690#define RX_FREE_BUFFERS 64
691#define RX_LOW_WATERMARK 8
692
693
67#define IWL_RX_BUF_SIZE 3000 694#define IWL_RX_BUF_SIZE 3000
68/* card static random access memory (SRAM) for processor data and instructs */ 695/* card static random access memory (SRAM) for processor data and instructs */
69#define ALM_RTC_INST_UPPER_BOUND (0x014000) 696#define ALM_RTC_INST_UPPER_BOUND (0x014000)
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.h b/drivers/net/wireless/iwlwifi/iwl-3945-io.h
index 43afcda6f73e..89253e133533 100644
--- a/drivers/net/wireless/iwlwifi/iwl-io.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-io.h
@@ -31,7 +31,7 @@
31 31
32#include <linux/io.h> 32#include <linux/io.h>
33 33
34#include "iwl-debug.h" 34#include "iwl-3945-debug.h"
35 35
36/* 36/*
37 * IO, register, and NIC memory access functions 37 * IO, register, and NIC memory access functions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-rs.c b/drivers/net/wireless/iwlwifi/iwl-3945-rs.c
index a6cb97ac43ef..e3a507513e8b 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945-rs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-rs.c
@@ -37,11 +37,9 @@
37 37
38#include <linux/workqueue.h> 38#include <linux/workqueue.h>
39 39
40#define IWL 3945
41
42#include "../net/mac80211/ieee80211_rate.h" 40#include "../net/mac80211/ieee80211_rate.h"
43 41
44#include "iwlwifi.h" 42#include "iwl-3945.h"
45 43
46#define RS_NAME "iwl-3945-rs" 44#define RS_NAME "iwl-3945-rs"
47 45
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index faaba2927177..53fe9c1c1747 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -39,11 +39,8 @@
39 39
40#include <linux/etherdevice.h> 40#include <linux/etherdevice.h>
41 41
42#define IWL 3945
43
44#include "iwlwifi.h"
45#include "iwl-helpers.h"
46#include "iwl-3945.h" 42#include "iwl-3945.h"
43#include "iwl-helpers.h"
47#include "iwl-3945-rs.h" 44#include "iwl-3945-rs.h"
48 45
49#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \ 46#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.h b/drivers/net/wireless/iwlwifi/iwl-3945.h
index adb5d672e711..ab8412270f6f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.h
@@ -27,6 +27,684 @@
27#ifndef __iwl_3945_h__ 27#ifndef __iwl_3945_h__
28#define __iwl_3945_h__ 28#define __iwl_3945_h__
29 29
30#include <linux/pci.h> /* for struct pci_device_id */
31#include <linux/kernel.h>
32#include <net/ieee80211_radiotap.h>
33
34struct iwl_priv;
35
36/* Hardware specific file defines the PCI IDs table for that hardware module */
37extern struct pci_device_id iwl_hw_card_ids[];
38
39#define DRV_NAME "iwl3945"
40#include "iwl-3945-hw.h"
41#include "iwl-prph.h"
42#include "iwl-3945-debug.h"
43
44/* Default noise level to report when noise measurement is not available.
45 * This may be because we're:
46 * 1) Not associated (4965, no beacon statistics being sent to driver)
47 * 2) Scanning (noise measurement does not apply to associated channel)
48 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
49 * Use default noise value of -127 ... this is below the range of measurable
50 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
51 * Also, -127 works better than 0 when averaging frames with/without
52 * noise info (e.g. averaging might be done in app); measured dBm values are
53 * always negative ... using a negative value as the default keeps all
54 * averages within an s8's (used in some apps) range of negative values. */
55#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
56
57/* Module parameters accessible from iwl-*.c */
58extern int iwl_param_hwcrypto;
59extern int iwl_param_queues_num;
60
61enum iwl_antenna {
62 IWL_ANTENNA_DIVERSITY,
63 IWL_ANTENNA_MAIN,
64 IWL_ANTENNA_AUX
65};
66
67/*
68 * RTS threshold here is total size [2347] minus 4 FCS bytes
69 * Per spec:
70 * a value of 0 means RTS on all data/management packets
71 * a value > max MSDU size means no RTS
72 * else RTS for data/management frames where MPDU is larger
73 * than RTS value.
74 */
75#define DEFAULT_RTS_THRESHOLD 2347U
76#define MIN_RTS_THRESHOLD 0U
77#define MAX_RTS_THRESHOLD 2347U
78#define MAX_MSDU_SIZE 2304U
79#define MAX_MPDU_SIZE 2346U
80#define DEFAULT_BEACON_INTERVAL 100U
81#define DEFAULT_SHORT_RETRY_LIMIT 7U
82#define DEFAULT_LONG_RETRY_LIMIT 4U
83
84struct iwl_rx_mem_buffer {
85 dma_addr_t dma_addr;
86 struct sk_buff *skb;
87 struct list_head list;
88};
89
90struct iwl_rt_rx_hdr {
91 struct ieee80211_radiotap_header rt_hdr;
92 __le64 rt_tsf; /* TSF */
93 u8 rt_flags; /* radiotap packet flags */
94 u8 rt_rate; /* rate in 500kb/s */
95 __le16 rt_channelMHz; /* channel in MHz */
96 __le16 rt_chbitmask; /* channel bitfield */
97 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
98 s8 rt_dbmnoise;
99 u8 rt_antenna; /* antenna number */
100 u8 payload[0]; /* payload... */
101} __attribute__ ((packed));
102
103struct iwl_rt_tx_hdr {
104 struct ieee80211_radiotap_header rt_hdr;
105 u8 rt_rate; /* rate in 500kb/s */
106 __le16 rt_channel; /* channel in mHz */
107 __le16 rt_chbitmask; /* channel bitfield */
108 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
109 u8 rt_antenna; /* antenna number */
110 u8 payload[0]; /* payload... */
111} __attribute__ ((packed));
112
113/*
114 * Generic queue structure
115 *
116 * Contains common data for Rx and Tx queues
117 */
118struct iwl_queue {
119 int n_bd; /* number of BDs in this queue */
120 int write_ptr; /* 1-st empty entry (index) host_w*/
121 int read_ptr; /* last used entry (index) host_r*/
122 dma_addr_t dma_addr; /* physical addr for BD's */
123 int n_window; /* safe queue window */
124 u32 id;
125 int low_mark; /* low watermark, resume queue if free
126 * space more than this */
127 int high_mark; /* high watermark, stop queue if free
128 * space less than this */
129} __attribute__ ((packed));
130
131#define MAX_NUM_OF_TBS (20)
132
133struct iwl_tx_info {
134 struct ieee80211_tx_status status;
135 struct sk_buff *skb[MAX_NUM_OF_TBS];
136};
137
138/**
139 * struct iwl_tx_queue - Tx Queue for DMA
140 * @need_update: need to update read/write index
141 * @shed_retry: queue is HT AGG enabled
142 *
143 * Queue consists of circular buffer of BD's and required locking structures.
144 */
145struct iwl_tx_queue {
146 struct iwl_queue q;
147 struct iwl_tfd_frame *bd;
148 struct iwl_cmd *cmd;
149 dma_addr_t dma_addr_cmd;
150 struct iwl_tx_info *txb;
151 int need_update;
152 int sched_retry;
153 int active;
154};
155
156#define IWL_NUM_SCAN_RATES (2)
157
158struct iwl_channel_tgd_info {
159 u8 type;
160 s8 max_power;
161};
162
163struct iwl_channel_tgh_info {
164 s64 last_radar_time;
165};
166
167/* current Tx power values to use, one for each rate for each channel.
168 * requested power is limited by:
169 * -- regulatory EEPROM limits for this channel
170 * -- hardware capabilities (clip-powers)
171 * -- spectrum management
172 * -- user preference (e.g. iwconfig)
173 * when requested power is set, base power index must also be set. */
174struct iwl_channel_power_info {
175 struct iwl_tx_power tpc; /* actual radio and DSP gain settings */
176 s8 power_table_index; /* actual (compenst'd) index into gain table */
177 s8 base_power_index; /* gain index for power at factory temp. */
178 s8 requested_power; /* power (dBm) requested for this chnl/rate */
179};
180
181/* current scan Tx power values to use, one for each scan rate for each
182 * channel. */
183struct iwl_scan_power_info {
184 struct iwl_tx_power tpc; /* actual radio and DSP gain settings */
185 s8 power_table_index; /* actual (compenst'd) index into gain table */
186 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
187};
188
189/* Channel unlock period is 15 seconds. If no beacon or probe response
190 * has been received within 15 seconds on a locked channel then the channel
191 * remains locked. */
192#define TX_UNLOCK_PERIOD 15
193
194/* CSA lock period is 15 seconds. If a CSA has been received on a channel in
195 * the last 15 seconds, the channel is locked */
196#define CSA_LOCK_PERIOD 15
197/*
198 * One for each channel, holds all channel setup data
199 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
200 * with one another!
201 */
202#define IWL4965_MAX_RATE (33)
203
204struct iwl_channel_info {
205 struct iwl_channel_tgd_info tgd;
206 struct iwl_channel_tgh_info tgh;
207 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
208 struct iwl_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for
209 * FAT channel */
210
211 u8 channel; /* channel number */
212 u8 flags; /* flags copied from EEPROM */
213 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
214 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */
215 s8 min_power; /* always 0 */
216 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
217
218 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
219 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
220 u8 phymode; /* MODE_IEEE80211{A,B,G} */
221
222 /* Radio/DSP gain settings for each "normal" data Tx rate.
223 * These include, in addition to RF and DSP gain, a few fields for
224 * remembering/modifying gain settings (indexes). */
225 struct iwl_channel_power_info power_info[IWL4965_MAX_RATE];
226
227 /* Radio/DSP gain settings for each scan rate, for directed scans. */
228 struct iwl_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
229};
230
231struct iwl_clip_group {
232 /* maximum power level to prevent clipping for each rate, derived by
233 * us from this band's saturation power in EEPROM */
234 const s8 clip_powers[IWL_MAX_RATES];
235};
236
237#include "iwl-3945-rs.h"
238
239#define IWL_TX_FIFO_AC0 0
240#define IWL_TX_FIFO_AC1 1
241#define IWL_TX_FIFO_AC2 2
242#define IWL_TX_FIFO_AC3 3
243#define IWL_TX_FIFO_HCCA_1 5
244#define IWL_TX_FIFO_HCCA_2 6
245#define IWL_TX_FIFO_NONE 7
246
247/* Minimum number of queues. MAX_NUM is defined in hw specific files */
248#define IWL_MIN_NUM_QUEUES 4
249
250/* Power management (not Tx power) structures */
251
252struct iwl_power_vec_entry {
253 struct iwl_powertable_cmd cmd;
254 u8 no_dtim;
255};
256#define IWL_POWER_RANGE_0 (0)
257#define IWL_POWER_RANGE_1 (1)
258
259#define IWL_POWER_MODE_CAM 0x00 /* Continuously Aware Mode, always on */
260#define IWL_POWER_INDEX_3 0x03
261#define IWL_POWER_INDEX_5 0x05
262#define IWL_POWER_AC 0x06
263#define IWL_POWER_BATTERY 0x07
264#define IWL_POWER_LIMIT 0x07
265#define IWL_POWER_MASK 0x0F
266#define IWL_POWER_ENABLED 0x10
267#define IWL_POWER_LEVEL(x) ((x) & IWL_POWER_MASK)
268
269struct iwl_power_mgr {
270 spinlock_t lock;
271 struct iwl_power_vec_entry pwr_range_0[IWL_POWER_AC];
272 struct iwl_power_vec_entry pwr_range_1[IWL_POWER_AC];
273 u8 active_index;
274 u32 dtim_val;
275};
276
277#define IEEE80211_DATA_LEN 2304
278#define IEEE80211_4ADDR_LEN 30
279#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
280#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
281
282struct iwl_frame {
283 union {
284 struct ieee80211_hdr frame;
285 struct iwl_tx_beacon_cmd beacon;
286 u8 raw[IEEE80211_FRAME_LEN];
287 u8 cmd[360];
288 } u;
289 struct list_head list;
290};
291
292#define SEQ_TO_QUEUE(x) ((x >> 8) & 0xbf)
293#define QUEUE_TO_SEQ(x) ((x & 0xbf) << 8)
294#define SEQ_TO_INDEX(x) (x & 0xff)
295#define INDEX_TO_SEQ(x) (x & 0xff)
296#define SEQ_HUGE_FRAME (0x4000)
297#define SEQ_RX_FRAME __constant_cpu_to_le16(0x8000)
298#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
299#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
300#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
301
302enum {
303 /* CMD_SIZE_NORMAL = 0, */
304 CMD_SIZE_HUGE = (1 << 0),
305 /* CMD_SYNC = 0, */
306 CMD_ASYNC = (1 << 1),
307 /* CMD_NO_SKB = 0, */
308 CMD_WANT_SKB = (1 << 2),
309};
310
311struct iwl_cmd;
312struct iwl_priv;
313
314struct iwl_cmd_meta {
315 struct iwl_cmd_meta *source;
316 union {
317 struct sk_buff *skb;
318 int (*callback)(struct iwl_priv *priv,
319 struct iwl_cmd *cmd, struct sk_buff *skb);
320 } __attribute__ ((packed)) u;
321
322 /* The CMD_SIZE_HUGE flag bit indicates that the command
323 * structure is stored at the end of the shared queue memory. */
324 u32 flags;
325
326} __attribute__ ((packed));
327
328struct iwl_cmd {
329 struct iwl_cmd_meta meta;
330 struct iwl_cmd_header hdr;
331 union {
332 struct iwl_addsta_cmd addsta;
333 struct iwl_led_cmd led;
334 u32 flags;
335 u8 val8;
336 u16 val16;
337 u32 val32;
338 struct iwl_bt_cmd bt;
339 struct iwl_rxon_time_cmd rxon_time;
340 struct iwl_powertable_cmd powertable;
341 struct iwl_qosparam_cmd qosparam;
342 struct iwl_tx_cmd tx;
343 struct iwl_tx_beacon_cmd tx_beacon;
344 struct iwl_rxon_assoc_cmd rxon_assoc;
345 u8 *indirect;
346 u8 payload[360];
347 } __attribute__ ((packed)) cmd;
348} __attribute__ ((packed));
349
350struct iwl_host_cmd {
351 u8 id;
352 u16 len;
353 struct iwl_cmd_meta meta;
354 const void *data;
355};
356
357#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
358 sizeof(struct iwl_cmd_meta))
359
360/*
361 * RX related structures and functions
362 */
363#define RX_FREE_BUFFERS 64
364#define RX_LOW_WATERMARK 8
365
366#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
367#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
368#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
369
370/**
371 * struct iwl_rx_queue - Rx queue
372 * @processed: Internal index to last handled Rx packet
373 * @read: Shared index to newest available Rx buffer
374 * @write: Shared index to oldest written Rx packet
375 * @free_count: Number of pre-allocated buffers in rx_free
376 * @rx_free: list of free SKBs for use
377 * @rx_used: List of Rx buffers with no SKB
378 * @need_update: flag to indicate we need to update read/write index
379 *
380 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
381 */
382struct iwl_rx_queue {
383 __le32 *bd;
384 dma_addr_t dma_addr;
385 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
386 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
387 u32 processed;
388 u32 read;
389 u32 write;
390 u32 free_count;
391 struct list_head rx_free;
392 struct list_head rx_used;
393 int need_update;
394 spinlock_t lock;
395};
396
397#define IWL_SUPPORTED_RATES_IE_LEN 8
398
399#define SCAN_INTERVAL 100
400
401#define MAX_A_CHANNELS 252
402#define MIN_A_CHANNELS 7
403
404#define MAX_B_CHANNELS 14
405#define MIN_B_CHANNELS 1
406
407#define STATUS_HCMD_ACTIVE 0 /* host command in progress */
408#define STATUS_INT_ENABLED 1
409#define STATUS_RF_KILL_HW 2
410#define STATUS_RF_KILL_SW 3
411#define STATUS_INIT 4
412#define STATUS_ALIVE 5
413#define STATUS_READY 6
414#define STATUS_TEMPERATURE 7
415#define STATUS_GEO_CONFIGURED 8
416#define STATUS_EXIT_PENDING 9
417#define STATUS_IN_SUSPEND 10
418#define STATUS_STATISTICS 11
419#define STATUS_SCANNING 12
420#define STATUS_SCAN_ABORTING 13
421#define STATUS_SCAN_HW 14
422#define STATUS_POWER_PMI 15
423#define STATUS_FW_ERROR 16
424
425#define MAX_TID_COUNT 9
426
427#define IWL_INVALID_RATE 0xFF
428#define IWL_INVALID_VALUE -1
429
430struct iwl_tid_data {
431 u16 seq_number;
432};
433
434struct iwl_hw_key {
435 enum ieee80211_key_alg alg;
436 int keylen;
437 u8 key[32];
438};
439
440union iwl_ht_rate_supp {
441 u16 rates;
442 struct {
443 u8 siso_rate;
444 u8 mimo_rate;
445 };
446};
447
448#ifdef CONFIG_IWLWIFI_HT
449#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
450#define HT_IE_MAX_AMSDU_SIZE_4K (0)
451#define CFG_HT_MPDU_DENSITY_2USEC (0x5)
452#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC
453
454struct sta_ht_info {
455 u8 is_ht;
456 u16 rx_mimo_ps_mode;
457 u16 tx_mimo_ps_mode;
458 u16 control_channel;
459 u8 max_amsdu_size;
460 u8 ampdu_factor;
461 u8 mpdu_density;
462 u8 operating_mode;
463 u8 supported_chan_width;
464 u8 extension_chan_offset;
465 u8 is_green_field;
466 u8 sgf;
467 u8 supp_rates[16];
468 u8 tx_chan_width;
469 u8 chan_width_cap;
470};
471#endif /*CONFIG_IWLWIFI_HT */
472
473#ifdef CONFIG_IWLWIFI_QOS
474
475union iwl_qos_capabity {
476 struct {
477 u8 edca_count:4; /* bit 0-3 */
478 u8 q_ack:1; /* bit 4 */
479 u8 queue_request:1; /* bit 5 */
480 u8 txop_request:1; /* bit 6 */
481 u8 reserved:1; /* bit 7 */
482 } q_AP;
483 struct {
484 u8 acvo_APSD:1; /* bit 0 */
485 u8 acvi_APSD:1; /* bit 1 */
486 u8 ac_bk_APSD:1; /* bit 2 */
487 u8 ac_be_APSD:1; /* bit 3 */
488 u8 q_ack:1; /* bit 4 */
489 u8 max_len:2; /* bit 5-6 */
490 u8 more_data_ack:1; /* bit 7 */
491 } q_STA;
492 u8 val;
493};
494
495/* QoS structures */
496struct iwl_qos_info {
497 int qos_enable;
498 int qos_active;
499 union iwl_qos_capabity qos_cap;
500 struct iwl_qosparam_cmd def_qos_parm;
501};
502#endif /*CONFIG_IWLWIFI_QOS */
503
504#define STA_PS_STATUS_WAKE 0
505#define STA_PS_STATUS_SLEEP 1
506
507struct iwl_station_entry {
508 struct iwl_addsta_cmd sta;
509 struct iwl_tid_data tid[MAX_TID_COUNT];
510 union {
511 struct {
512 u8 rate;
513 u8 flags;
514 } s;
515 u16 rate_n_flags;
516 } current_rate;
517 u8 used;
518 u8 ps_status;
519 struct iwl_hw_key keyinfo;
520};
521
522/* one for each uCode image (inst/data, boot/init/runtime) */
523struct fw_desc {
524 void *v_addr; /* access by driver */
525 dma_addr_t p_addr; /* access by card's busmaster DMA */
526 u32 len; /* bytes */
527};
528
529/* uCode file layout */
530struct iwl_ucode {
531 __le32 ver; /* major/minor/subminor */
532 __le32 inst_size; /* bytes of runtime instructions */
533 __le32 data_size; /* bytes of runtime data */
534 __le32 init_size; /* bytes of initialization instructions */
535 __le32 init_data_size; /* bytes of initialization data */
536 __le32 boot_size; /* bytes of bootstrap instructions */
537 u8 data[0]; /* data in same order as "size" elements */
538};
539
540#define IWL_IBSS_MAC_HASH_SIZE 32
541
542struct iwl_ibss_seq {
543 u8 mac[ETH_ALEN];
544 u16 seq_num;
545 u16 frag_num;
546 unsigned long packet_time;
547 struct list_head list;
548};
549
550struct iwl_driver_hw_info {
551 u16 max_txq_num;
552 u16 ac_queue_count;
553 u16 tx_cmd_len;
554 u16 max_rxq_size;
555 u32 rx_buffer_size;
556 u16 max_rxq_log;
557 u8 max_stations;
558 u8 bcast_sta_id;
559 void *shared_virt;
560 dma_addr_t shared_phys;
561};
562
563
564#define STA_FLG_RTS_MIMO_PROT_MSK __constant_cpu_to_le32(1 << 17)
565#define STA_FLG_AGG_MPDU_8US_MSK __constant_cpu_to_le32(1 << 18)
566#define STA_FLG_MAX_AGG_SIZE_POS (19)
567#define STA_FLG_MAX_AGG_SIZE_MSK __constant_cpu_to_le32(3 << 19)
568#define STA_FLG_FAT_EN_MSK __constant_cpu_to_le32(1 << 21)
569#define STA_FLG_MIMO_DIS_MSK __constant_cpu_to_le32(1 << 22)
570#define STA_FLG_AGG_MPDU_DENSITY_POS (23)
571#define STA_FLG_AGG_MPDU_DENSITY_MSK __constant_cpu_to_le32(7 << 23)
572#define HT_SHORT_GI_20MHZ_ONLY (1 << 0)
573#define HT_SHORT_GI_40MHZ_ONLY (1 << 1)
574
575
576#define IWL_RX_HDR(x) ((struct iwl_rx_frame_hdr *)(\
577 x->u.rx_frame.stats.payload + \
578 x->u.rx_frame.stats.phy_count))
579#define IWL_RX_END(x) ((struct iwl_rx_frame_end *)(\
580 IWL_RX_HDR(x)->payload + \
581 le16_to_cpu(IWL_RX_HDR(x)->len)))
582#define IWL_RX_STATS(x) (&x->u.rx_frame.stats)
583#define IWL_RX_DATA(x) (IWL_RX_HDR(x)->payload)
584
585
586/******************************************************************************
587 *
588 * Functions implemented in iwl-base.c which are forward declared here
589 * for use by iwl-*.c
590 *
591 *****************************************************************************/
592struct iwl_addsta_cmd;
593extern int iwl_send_add_station(struct iwl_priv *priv,
594 struct iwl_addsta_cmd *sta, u8 flags);
595extern u8 iwl_add_station(struct iwl_priv *priv, const u8 *bssid,
596 int is_ap, u8 flags);
597extern int iwl_is_network_packet(struct iwl_priv *priv,
598 struct ieee80211_hdr *header);
599extern int iwl_power_init_handle(struct iwl_priv *priv);
600extern int iwl_eeprom_init(struct iwl_priv *priv);
601#ifdef CONFIG_IWLWIFI_DEBUG
602extern void iwl_report_frame(struct iwl_priv *priv,
603 struct iwl_rx_packet *pkt,
604 struct ieee80211_hdr *header, int group100);
605#else
606static inline void iwl_report_frame(struct iwl_priv *priv,
607 struct iwl_rx_packet *pkt,
608 struct ieee80211_hdr *header,
609 int group100) {}
610#endif
611extern void iwl_handle_data_packet_monitor(struct iwl_priv *priv,
612 struct iwl_rx_mem_buffer *rxb,
613 void *data, short len,
614 struct ieee80211_rx_status *stats,
615 u16 phy_flags);
616extern int is_duplicate_packet(struct iwl_priv *priv, struct ieee80211_hdr
617 *header);
618extern int iwl_rx_queue_alloc(struct iwl_priv *priv);
619extern void iwl_rx_queue_reset(struct iwl_priv *priv,
620 struct iwl_rx_queue *rxq);
621extern int iwl_calc_db_from_ratio(int sig_ratio);
622extern int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm);
623extern int iwl_tx_queue_init(struct iwl_priv *priv,
624 struct iwl_tx_queue *txq, int count, u32 id);
625extern void iwl_rx_replenish(void *data);
626extern void iwl_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq);
627extern int iwl_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len,
628 const void *data);
629extern int __must_check iwl_send_cmd(struct iwl_priv *priv,
630 struct iwl_host_cmd *cmd);
631extern unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
632 struct ieee80211_hdr *hdr,
633 const u8 *dest, int left);
634extern int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
635 struct iwl_rx_queue *q);
636extern int iwl_send_statistics_request(struct iwl_priv *priv);
637extern void iwl_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
638 u32 decrypt_res,
639 struct ieee80211_rx_status *stats);
640extern const u8 BROADCAST_ADDR[ETH_ALEN];
641
642/*
643 * Currently used by iwl-3945-rs... look at restructuring so that it doesn't
644 * call this... todo... fix that.
645*/
646extern u8 iwl_sync_station(struct iwl_priv *priv, int sta_id,
647 u16 tx_rate, u8 flags);
648
649/******************************************************************************
650 *
651 * Functions implemented in iwl-[34]*.c which are forward declared here
652 * for use by iwl-base.c
653 *
654 * NOTE: The implementation of these functions are hardware specific
655 * which is why they are in the hardware specific files (vs. iwl-base.c)
656 *
657 * Naming convention --
658 * iwl_ <-- Its part of iwlwifi (should be changed to iwl_)
659 * iwl_hw_ <-- Hardware specific (implemented in iwl-XXXX.c by all HW)
660 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
661 * iwl_bg_ <-- Called from work queue context
662 * iwl_mac_ <-- mac80211 callback
663 *
664 ****************************************************************************/
665extern void iwl_hw_rx_handler_setup(struct iwl_priv *priv);
666extern void iwl_hw_setup_deferred_work(struct iwl_priv *priv);
667extern void iwl_hw_cancel_deferred_work(struct iwl_priv *priv);
668extern int iwl_hw_rxq_stop(struct iwl_priv *priv);
669extern int iwl_hw_set_hw_setting(struct iwl_priv *priv);
670extern int iwl_hw_nic_init(struct iwl_priv *priv);
671extern int iwl_hw_nic_stop_master(struct iwl_priv *priv);
672extern void iwl_hw_txq_ctx_free(struct iwl_priv *priv);
673extern void iwl_hw_txq_ctx_stop(struct iwl_priv *priv);
674extern int iwl_hw_nic_reset(struct iwl_priv *priv);
675extern int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *tfd,
676 dma_addr_t addr, u16 len);
677extern int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq);
678extern int iwl_hw_get_temperature(struct iwl_priv *priv);
679extern int iwl_hw_tx_queue_init(struct iwl_priv *priv,
680 struct iwl_tx_queue *txq);
681extern unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
682 struct iwl_frame *frame, u8 rate);
683extern int iwl_hw_get_rx_read(struct iwl_priv *priv);
684extern void iwl_hw_build_tx_cmd_rate(struct iwl_priv *priv,
685 struct iwl_cmd *cmd,
686 struct ieee80211_tx_control *ctrl,
687 struct ieee80211_hdr *hdr,
688 int sta_id, int tx_id);
689extern int iwl_hw_reg_send_txpower(struct iwl_priv *priv);
690extern int iwl_hw_reg_set_txpower(struct iwl_priv *priv, s8 power);
691extern void iwl_hw_rx_statistics(struct iwl_priv *priv,
692 struct iwl_rx_mem_buffer *rxb);
693extern void iwl_disable_events(struct iwl_priv *priv);
694extern int iwl4965_get_temperature(const struct iwl_priv *priv);
695
696/**
697 * iwl_hw_find_station - Find station id for a given BSSID
698 * @bssid: MAC address of station ID to find
699 *
700 * NOTE: This should not be hardware specific but the code has
701 * not yet been merged into a single common layer for managing the
702 * station tables.
703 */
704extern u8 iwl_hw_find_station(struct iwl_priv *priv, const u8 *bssid);
705
706extern int iwl_hw_channel_switch(struct iwl_priv *priv, u16 channel);
707
30/* 708/*
31 * Forward declare iwl-3945.c functions for iwl-base.c 709 * Forward declare iwl-3945.c functions for iwl-base.c
32 */ 710 */
@@ -37,4 +715,286 @@ extern void iwl3945_reg_txpower_periodic(struct iwl_priv *priv);
37extern int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv); 715extern int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv);
38extern u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, 716extern u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id,
39 u16 tx_rate, u8 flags); 717 u16 tx_rate, u8 flags);
718
719
720#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
721
722enum {
723 MEASUREMENT_READY = (1 << 0),
724 MEASUREMENT_ACTIVE = (1 << 1),
725};
726
727#endif
728
729struct iwl_priv {
730
731 /* ieee device used by generic ieee processing code */
732 struct ieee80211_hw *hw;
733 struct ieee80211_channel *ieee_channels;
734 struct ieee80211_rate *ieee_rates;
735
736 /* temporary frame storage list */
737 struct list_head free_frames;
738 int frames_count;
739
740 u8 phymode;
741 int alloc_rxb_skb;
742
743 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
744 struct iwl_rx_mem_buffer *rxb);
745
746 const struct ieee80211_hw_mode *modes;
747
748#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
749 /* spectrum measurement report caching */
750 struct iwl_spectrum_notification measure_report;
751 u8 measurement_status;
752#endif
753 /* ucode beacon time */
754 u32 ucode_beacon_time;
755
756 /* we allocate array of iwl_channel_info for NIC's valid channels.
757 * Access via channel # using indirect index array */
758 struct iwl_channel_info *channel_info; /* channel info array */
759 u8 channel_count; /* # of channels */
760
761 /* each calibration channel group in the EEPROM has a derived
762 * clip setting for each rate. */
763 const struct iwl_clip_group clip_groups[5];
764
765 /* thermal calibration */
766 s32 temperature; /* degrees Kelvin */
767 s32 last_temperature;
768
769 /* Scan related variables */
770 unsigned long last_scan_jiffies;
771 unsigned long scan_start;
772 unsigned long scan_pass_start;
773 unsigned long scan_start_tsf;
774 int scan_bands;
775 int one_direct_scan;
776 u8 direct_ssid_len;
777 u8 direct_ssid[IW_ESSID_MAX_SIZE];
778 struct iwl_scan_cmd *scan;
779 u8 only_active_channel;
780
781 /* spinlock */
782 spinlock_t lock; /* protect general shared data */
783 spinlock_t hcmd_lock; /* protect hcmd */
784 struct mutex mutex;
785
786 /* basic pci-network driver stuff */
787 struct pci_dev *pci_dev;
788
789 /* pci hardware address support */
790 void __iomem *hw_base;
791
792 /* uCode images, save to reload in case of failure */
793 struct fw_desc ucode_code; /* runtime inst */
794 struct fw_desc ucode_data; /* runtime data original */
795 struct fw_desc ucode_data_backup; /* runtime data save/restore */
796 struct fw_desc ucode_init; /* initialization inst */
797 struct fw_desc ucode_init_data; /* initialization data */
798 struct fw_desc ucode_boot; /* bootstrap inst */
799
800
801 struct iwl_rxon_time_cmd rxon_timing;
802
803 /* We declare this const so it can only be
804 * changed via explicit cast within the
805 * routines that actually update the physical
806 * hardware */
807 const struct iwl_rxon_cmd active_rxon;
808 struct iwl_rxon_cmd staging_rxon;
809
810 int error_recovering;
811 struct iwl_rxon_cmd recovery_rxon;
812
813 /* 1st responses from initialize and runtime uCode images.
814 * 4965's initialize alive response contains some calibration data. */
815 struct iwl_init_alive_resp card_alive_init;
816 struct iwl_alive_resp card_alive;
817
818#ifdef LED
819 /* LED related variables */
820 struct iwl_activity_blink activity;
821 unsigned long led_packets;
822 int led_state;
823#endif
824
825 u16 active_rate;
826 u16 active_rate_basic;
827
828 u8 call_post_assoc_from_beacon;
829 u8 assoc_station_added;
830 /* Rate scaling data */
831 s8 data_retry_limit;
832 u8 retry_rate;
833
834 wait_queue_head_t wait_command_queue;
835
836 int activity_timer_active;
837
838 /* Rx and Tx DMA processing queues */
839 struct iwl_rx_queue rxq;
840 struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES];
841
842 unsigned long status;
843 u32 config;
844
845 int last_rx_rssi; /* From Rx packet statisitics */
846 int last_rx_noise; /* From beacon statistics */
847
848 struct iwl_power_mgr power_data;
849
850 struct iwl_notif_statistics statistics;
851 unsigned long last_statistics_time;
852
853 /* context information */
854 u8 essid[IW_ESSID_MAX_SIZE];
855 u8 essid_len;
856 u16 rates_mask;
857
858 u32 power_mode;
859 u32 antenna;
860 u8 bssid[ETH_ALEN];
861 u16 rts_threshold;
862 u8 mac_addr[ETH_ALEN];
863
864 /*station table variables */
865 spinlock_t sta_lock;
866 int num_stations;
867 struct iwl_station_entry stations[IWL_STATION_COUNT];
868
869 /* Indication if ieee80211_ops->open has been called */
870 int is_open;
871
872 u8 mac80211_registered;
873 int is_abg;
874
875 u32 notif_missed_beacons;
876
877 /* Rx'd packet timing information */
878 u32 last_beacon_time;
879 u64 last_tsf;
880
881 /* Duplicate packet detection */
882 u16 last_seq_num;
883 u16 last_frag_num;
884 unsigned long last_packet_time;
885 struct list_head ibss_mac_hash[IWL_IBSS_MAC_HASH_SIZE];
886
887 /* eeprom */
888 struct iwl_eeprom eeprom;
889
890 int iw_mode;
891
892 struct sk_buff *ibss_beacon;
893
894 /* Last Rx'd beacon timestamp */
895 u32 timestamp0;
896 u32 timestamp1;
897 u16 beacon_int;
898 struct iwl_driver_hw_info hw_setting;
899 int interface_id;
900
901 /* Current association information needed to configure the
902 * hardware */
903 u16 assoc_id;
904 u16 assoc_capability;
905 u8 ps_mode;
906
907#ifdef CONFIG_IWLWIFI_QOS
908 struct iwl_qos_info qos_data;
909#endif /*CONFIG_IWLWIFI_QOS */
910
911 struct workqueue_struct *workqueue;
912
913 struct work_struct up;
914 struct work_struct restart;
915 struct work_struct calibrated_work;
916 struct work_struct scan_completed;
917 struct work_struct rx_replenish;
918 struct work_struct rf_kill;
919 struct work_struct abort_scan;
920 struct work_struct update_link_led;
921 struct work_struct auth_work;
922 struct work_struct report_work;
923 struct work_struct request_scan;
924 struct work_struct beacon_update;
925
926 struct tasklet_struct irq_tasklet;
927
928 struct delayed_work init_alive_start;
929 struct delayed_work alive_start;
930 struct delayed_work activity_timer;
931 struct delayed_work thermal_periodic;
932 struct delayed_work gather_stats;
933 struct delayed_work scan_check;
934 struct delayed_work post_associate;
935
936#define IWL_DEFAULT_TX_POWER 0x0F
937 s8 user_txpower_limit;
938 s8 max_channel_txpower_limit;
939
940#ifdef CONFIG_PM
941 u32 pm_state[16];
942#endif
943
944#ifdef CONFIG_IWLWIFI_DEBUG
945 /* debugging info */
946 u32 framecnt_to_us;
947 atomic_t restrict_refcnt;
948#endif
949}; /*iwl_priv */
950
951static inline int iwl_is_associated(struct iwl_priv *priv)
952{
953 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
954}
955
956static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
957{
958 if (ch_info == NULL)
959 return 0;
960 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
961}
962
963static inline int is_channel_narrow(const struct iwl_channel_info *ch_info)
964{
965 return (ch_info->flags & EEPROM_CHANNEL_NARROW) ? 1 : 0;
966}
967
968static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
969{
970 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
971}
972
973static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
974{
975 return ch_info->phymode == MODE_IEEE80211A;
976}
977
978static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
979{
980 return ((ch_info->phymode == MODE_IEEE80211B) ||
981 (ch_info->phymode == MODE_IEEE80211G));
982}
983
984static inline int is_channel_passive(const struct iwl_channel_info *ch)
985{
986 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
987}
988
989static inline int is_channel_ibss(const struct iwl_channel_info *ch)
990{
991 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
992}
993
994extern const struct iwl_channel_info *iwl_get_channel_info(
995 const struct iwl_priv *priv, int phymode, u16 channel);
996
997/* Requires full declaration of iwl_priv before including */
998#include "iwl-3945-io.h"
999
40#endif 1000#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-commands.h b/drivers/net/wireless/iwlwifi/iwl-4965-commands.h
index d852a77d112e..5524bf77e882 100644
--- a/drivers/net/wireless/iwlwifi/iwl-commands.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-commands.h
@@ -80,9 +80,6 @@ enum {
80 REPLY_REMOVE_ALL_STA = 0x1a, /* not used */ 80 REPLY_REMOVE_ALL_STA = 0x1a, /* not used */
81 81
82 /* RX, TX, LEDs */ 82 /* RX, TX, LEDs */
83#if IWL == 3945
84 REPLY_3945_RX = 0x1b, /* 3945 only */
85#endif
86 REPLY_TX = 0x1c, 83 REPLY_TX = 0x1c,
87 REPLY_RATE_SCALE = 0x47, /* 3945 only */ 84 REPLY_RATE_SCALE = 0x47, /* 3945 only */
88 REPLY_LEDS_CMD = 0x48, 85 REPLY_LEDS_CMD = 0x48,
@@ -132,7 +129,6 @@ enum {
132 /* Missed beacons notification */ 129 /* Missed beacons notification */
133 MISSED_BEACONS_NOTIFICATION = 0xa2, 130 MISSED_BEACONS_NOTIFICATION = 0xa2,
134 131
135#if IWL == 4965
136 REPLY_CT_KILL_CONFIG_CMD = 0xa4, 132 REPLY_CT_KILL_CONFIG_CMD = 0xa4,
137 SENSITIVITY_CMD = 0xa8, 133 SENSITIVITY_CMD = 0xa8,
138 REPLY_PHY_CALIBRATION_CMD = 0xb0, 134 REPLY_PHY_CALIBRATION_CMD = 0xb0,
@@ -140,7 +136,6 @@ enum {
140 REPLY_RX_MPDU_CMD = 0xc1, 136 REPLY_RX_MPDU_CMD = 0xc1,
141 REPLY_4965_RX = 0xc3, 137 REPLY_4965_RX = 0xc3,
142 REPLY_COMPRESSED_BA = 0xc5, 138 REPLY_COMPRESSED_BA = 0xc5,
143#endif
144 REPLY_MAX = 0xff 139 REPLY_MAX = 0xff
145}; 140};
146 141
@@ -211,7 +206,6 @@ struct iwl_init_alive_resp {
211 __le32 timestamp; 206 __le32 timestamp;
212 __le32 is_valid; 207 __le32 is_valid;
213 208
214#if IWL == 4965
215 /* calibration values from "initialize" uCode */ 209 /* calibration values from "initialize" uCode */
216 __le32 voltage; /* signed */ 210 __le32 voltage; /* signed */
217 __le32 therm_r1[2]; /* signed 1st for normal, 2nd for FAT channel */ 211 __le32 therm_r1[2]; /* signed 1st for normal, 2nd for FAT channel */
@@ -220,7 +214,6 @@ struct iwl_init_alive_resp {
220 __le32 therm_r4[2]; /* signed */ 214 __le32 therm_r4[2]; /* signed */
221 __le32 tx_atten[5][2]; /* signed MIMO gain comp, 5 freq groups, 215 __le32 tx_atten[5][2]; /* signed MIMO gain comp, 5 freq groups,
222 * 2 Tx chains */ 216 * 2 Tx chains */
223#endif
224} __attribute__ ((packed)); 217} __attribute__ ((packed));
225 218
226union tsf { 219union tsf {
@@ -237,9 +230,6 @@ struct iwl_error_resp {
237 u8 cmd_id; 230 u8 cmd_id;
238 u8 reserved1; 231 u8 reserved1;
239 __le16 bad_cmd_seq_num; 232 __le16 bad_cmd_seq_num;
240#if IWL == 3945
241 __le16 reserved2;
242#endif
243 __le32 error_info; 233 __le32 error_info;
244 union tsf timestamp; 234 union tsf timestamp;
245} __attribute__ ((packed)); 235} __attribute__ ((packed));
@@ -312,23 +302,15 @@ struct iwl_rxon_cmd {
312 __le16 reserved3; 302 __le16 reserved3;
313 u8 dev_type; 303 u8 dev_type;
314 u8 air_propagation; 304 u8 air_propagation;
315#if IWL == 3945
316 __le16 reserved4;
317#elif IWL == 4965
318 __le16 rx_chain; 305 __le16 rx_chain;
319#endif
320 u8 ofdm_basic_rates; 306 u8 ofdm_basic_rates;
321 u8 cck_basic_rates; 307 u8 cck_basic_rates;
322 __le16 assoc_id; 308 __le16 assoc_id;
323 __le32 flags; 309 __le32 flags;
324 __le32 filter_flags; 310 __le32 filter_flags;
325 __le16 channel; 311 __le16 channel;
326#if IWL == 3945
327 __le16 reserved5;
328#elif IWL == 4965
329 u8 ofdm_ht_single_stream_basic_rates; 312 u8 ofdm_ht_single_stream_basic_rates;
330 u8 ofdm_ht_dual_stream_basic_rates; 313 u8 ofdm_ht_dual_stream_basic_rates;
331#endif
332} __attribute__ ((packed)); 314} __attribute__ ((packed));
333 315
334/* 316/*
@@ -339,11 +321,9 @@ struct iwl_rxon_assoc_cmd {
339 __le32 filter_flags; 321 __le32 filter_flags;
340 u8 ofdm_basic_rates; 322 u8 ofdm_basic_rates;
341 u8 cck_basic_rates; 323 u8 cck_basic_rates;
342#if IWL == 4965
343 u8 ofdm_ht_single_stream_basic_rates; 324 u8 ofdm_ht_single_stream_basic_rates;
344 u8 ofdm_ht_dual_stream_basic_rates; 325 u8 ofdm_ht_dual_stream_basic_rates;
345 __le16 rx_chain_select_flags; 326 __le16 rx_chain_select_flags;
346#endif
347 __le16 reserved; 327 __le16 reserved;
348} __attribute__ ((packed)); 328} __attribute__ ((packed));
349 329
@@ -364,14 +344,6 @@ struct iwl_tx_power {
364 u8 dsp_atten; /* gain for DSP */ 344 u8 dsp_atten; /* gain for DSP */
365} __attribute__ ((packed)); 345} __attribute__ ((packed));
366 346
367#if IWL == 3945
368struct iwl_power_per_rate {
369 u8 rate; /* plcp */
370 struct iwl_tx_power tpc;
371 u8 reserved;
372} __attribute__ ((packed));
373
374#elif IWL == 4965
375#define POWER_TABLE_NUM_ENTRIES 33 347#define POWER_TABLE_NUM_ENTRIES 33
376#define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32 348#define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32
377#define POWER_TABLE_CCK_ENTRY 32 349#define POWER_TABLE_CCK_ENTRY 32
@@ -382,7 +354,6 @@ struct tx_power_dual_stream {
382struct iwl_tx_power_db { 354struct iwl_tx_power_db {
383 struct tx_power_dual_stream power_tbl[POWER_TABLE_NUM_ENTRIES]; 355 struct tx_power_dual_stream power_tbl[POWER_TABLE_NUM_ENTRIES];
384} __attribute__ ((packed)); 356} __attribute__ ((packed));
385#endif
386 357
387/* 358/*
388 * REPLY_CHANNEL_SWITCH = 0x72 (command, has simple generic response) 359 * REPLY_CHANNEL_SWITCH = 0x72 (command, has simple generic response)
@@ -394,11 +365,7 @@ struct iwl_channel_switch_cmd {
394 __le32 rxon_flags; 365 __le32 rxon_flags;
395 __le32 rxon_filter_flags; 366 __le32 rxon_filter_flags;
396 __le32 switch_time; 367 __le32 switch_time;
397#if IWL == 3945
398 struct iwl_power_per_rate power[IWL_MAX_RATES];
399#elif IWL == 4965
400 struct iwl_tx_power_db tx_power; 368 struct iwl_tx_power_db tx_power;
401#endif
402} __attribute__ ((packed)); 369} __attribute__ ((packed));
403 370
404/* 371/*
@@ -463,9 +430,6 @@ struct iwl_qosparam_cmd {
463#define IWL_STATION_COUNT 32 /* MAX(3945,4965)*/ 430#define IWL_STATION_COUNT 32 /* MAX(3945,4965)*/
464#define IWL_INVALID_STATION 255 431#define IWL_INVALID_STATION 255
465 432
466#if IWL == 3945
467#define STA_FLG_TX_RATE_MSK __constant_cpu_to_le32(1<<2);
468#endif
469#define STA_FLG_PWR_SAVE_MSK __constant_cpu_to_le32(1<<8); 433#define STA_FLG_PWR_SAVE_MSK __constant_cpu_to_le32(1<<8);
470 434
471#define STA_CONTROL_MODIFY_MSK 0x01 435#define STA_CONTROL_MODIFY_MSK 0x01
@@ -528,17 +492,11 @@ struct iwl_addsta_cmd {
528 __le32 station_flags; 492 __le32 station_flags;
529 __le32 station_flags_msk; 493 __le32 station_flags_msk;
530 __le16 tid_disable_tx; 494 __le16 tid_disable_tx;
531#if IWL == 3945
532 __le16 rate_n_flags;
533#else
534 __le16 reserved1; 495 __le16 reserved1;
535#endif
536 u8 add_immediate_ba_tid; 496 u8 add_immediate_ba_tid;
537 u8 remove_immediate_ba_tid; 497 u8 remove_immediate_ba_tid;
538 __le16 add_immediate_ba_ssn; 498 __le16 add_immediate_ba_ssn;
539#if IWL == 4965
540 __le32 reserved2; 499 __le32 reserved2;
541#endif
542} __attribute__ ((packed)); 500} __attribute__ ((packed));
543 501
544/* 502/*
@@ -721,47 +679,24 @@ struct iwl_tx_cmd {
721 __le16 len; 679 __le16 len;
722 __le16 next_frame_len; 680 __le16 next_frame_len;
723 __le32 tx_flags; 681 __le32 tx_flags;
724#if IWL == 3945
725 u8 rate;
726 u8 sta_id;
727 u8 tid_tspec;
728#elif IWL == 4965
729 struct iwl_dram_scratch scratch; 682 struct iwl_dram_scratch scratch;
730 __le32 rate_n_flags; 683 __le32 rate_n_flags;
731 u8 sta_id; 684 u8 sta_id;
732#endif
733 u8 sec_ctl; 685 u8 sec_ctl;
734#if IWL == 4965
735 u8 initial_rate_index; 686 u8 initial_rate_index;
736 u8 reserved; 687 u8 reserved;
737#endif
738 u8 key[16]; 688 u8 key[16];
739#if IWL == 3945
740 union {
741 u8 byte[8];
742 __le16 word[4];
743 __le32 dw[2];
744 } tkip_mic;
745 __le32 next_frame_info;
746#elif IWL == 4965
747 __le16 next_frame_flags; 689 __le16 next_frame_flags;
748 __le16 reserved2; 690 __le16 reserved2;
749#endif
750 union { 691 union {
751 __le32 life_time; 692 __le32 life_time;
752 __le32 attempt; 693 __le32 attempt;
753 } stop_time; 694 } stop_time;
754#if IWL == 3945
755 u8 supp_rates[2];
756#elif IWL == 4965
757 __le32 dram_lsb_ptr; 695 __le32 dram_lsb_ptr;
758 u8 dram_msb_ptr; 696 u8 dram_msb_ptr;
759#endif
760 u8 rts_retry_limit; /*byte 50 */ 697 u8 rts_retry_limit; /*byte 50 */
761 u8 data_retry_limit; /*byte 51 */ 698 u8 data_retry_limit; /*byte 51 */
762#if IWL == 4965
763 u8 tid_tspec; 699 u8 tid_tspec;
764#endif
765 union { 700 union {
766 __le16 pm_frame_timeout; 701 __le16 pm_frame_timeout;
767 __le16 attempt_duration; 702 __le16 attempt_duration;
@@ -872,7 +807,6 @@ enum {
872/* 807/*
873 * REPLY_TX = 0x1c (response) 808 * REPLY_TX = 0x1c (response)
874 */ 809 */
875#if IWL == 4965
876struct iwl_tx_resp { 810struct iwl_tx_resp {
877 u8 frame_count; /* 1 no aggregation, >1 aggregation */ 811 u8 frame_count; /* 1 no aggregation, >1 aggregation */
878 u8 bt_kill_count; 812 u8 bt_kill_count;
@@ -886,17 +820,6 @@ struct iwl_tx_resp {
886 __le32 status; /* TX status (for aggregation status of 1st frame) */ 820 __le32 status; /* TX status (for aggregation status of 1st frame) */
887} __attribute__ ((packed)); 821} __attribute__ ((packed));
888 822
889#elif IWL == 3945
890struct iwl_tx_resp {
891 u8 failure_rts;
892 u8 failure_frame;
893 u8 bt_kill_count;
894 u8 rate;
895 __le32 wireless_media_time;
896 __le32 status; /* TX status (for aggregation status of 1st frame) */
897} __attribute__ ((packed));
898#endif
899
900/* 823/*
901 * REPLY_COMPRESSED_BA = 0xc5 (response only, not a command) 824 * REPLY_COMPRESSED_BA = 0xc5 (response only, not a command)
902 */ 825 */
@@ -920,43 +843,9 @@ struct iwl_txpowertable_cmd {
920 u8 band; /* 0: 5 GHz, 1: 2.4 GHz */ 843 u8 band; /* 0: 5 GHz, 1: 2.4 GHz */
921 u8 reserved; 844 u8 reserved;
922 __le16 channel; 845 __le16 channel;
923#if IWL == 3945
924 struct iwl_power_per_rate power[IWL_MAX_RATES];
925#elif IWL == 4965
926 struct iwl_tx_power_db tx_power; 846 struct iwl_tx_power_db tx_power;
927#endif
928} __attribute__ ((packed));
929
930#if IWL == 3945
931struct iwl_rate_scaling_info {
932 __le16 rate_n_flags;
933 u8 try_cnt;
934 u8 next_rate_index;
935} __attribute__ ((packed)); 847} __attribute__ ((packed));
936 848
937/**
938 * struct iwl_rate_scaling_cmd - Rate Scaling Command & Response
939 *
940 * REPLY_RATE_SCALE = 0x47 (command, has simple generic response)
941 *
942 * NOTE: The table of rates passed to the uCode via the
943 * RATE_SCALE command sets up the corresponding order of
944 * rates used for all related commands, including rate
945 * masks, etc.
946 *
947 * For example, if you set 9MB (PLCP 0x0f) as the first
948 * rate in the rate table, the bit mask for that rate
949 * when passed through ofdm_basic_rates on the REPLY_RXON
950 * command would be bit 0 (1<<0)
951 */
952struct iwl_rate_scaling_cmd {
953 u8 table_id;
954 u8 reserved[3];
955 struct iwl_rate_scaling_info table[IWL_MAX_RATES];
956} __attribute__ ((packed));
957
958#elif IWL == 4965
959
960/*RS_NEW_API: only TLC_RTS remains and moved to bit 0 */ 849/*RS_NEW_API: only TLC_RTS remains and moved to bit 0 */
961#define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1<<0) 850#define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1<<0)
962 851
@@ -996,7 +885,6 @@ struct iwl_link_quality_cmd {
996 } rs_table[LINK_QUAL_MAX_RETRY_NUM]; 885 } rs_table[LINK_QUAL_MAX_RETRY_NUM];
997 __le32 reserved2; 886 __le32 reserved2;
998} __attribute__ ((packed)); 887} __attribute__ ((packed));
999#endif
1000 888
1001/* 889/*
1002 * REPLY_BT_CONFIG = 0x9b (command, has simple generic response) 890 * REPLY_BT_CONFIG = 0x9b (command, has simple generic response)
@@ -1166,21 +1054,6 @@ struct iwl_spectrum_notification {
1166 */ 1054 */
1167#define IWL_POWER_VEC_SIZE 5 1055#define IWL_POWER_VEC_SIZE 5
1168 1056
1169
1170#if IWL == 3945
1171
1172#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK __constant_cpu_to_le32(1<<0)
1173#define IWL_POWER_SLEEP_OVER_DTIM_MSK __constant_cpu_to_le32(1<<2)
1174#define IWL_POWER_PCI_PM_MSK __constant_cpu_to_le32(1<<3)
1175struct iwl_powertable_cmd {
1176 __le32 flags;
1177 __le32 rx_data_timeout;
1178 __le32 tx_data_timeout;
1179 __le32 sleep_interval[IWL_POWER_VEC_SIZE];
1180} __attribute__((packed));
1181
1182#elif IWL == 4965
1183
1184#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK __constant_cpu_to_le16(1<<0) 1057#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK __constant_cpu_to_le16(1<<0)
1185#define IWL_POWER_SLEEP_OVER_DTIM_MSK __constant_cpu_to_le16(1<<2) 1058#define IWL_POWER_SLEEP_OVER_DTIM_MSK __constant_cpu_to_le16(1<<2)
1186#define IWL_POWER_PCI_PM_MSK __constant_cpu_to_le16(1<<3) 1059#define IWL_POWER_PCI_PM_MSK __constant_cpu_to_le16(1<<3)
@@ -1194,7 +1067,6 @@ struct iwl_powertable_cmd {
1194 __le32 sleep_interval[IWL_POWER_VEC_SIZE]; 1067 __le32 sleep_interval[IWL_POWER_VEC_SIZE];
1195 __le32 keep_alive_beacons; 1068 __le32 keep_alive_beacons;
1196} __attribute__ ((packed)); 1069} __attribute__ ((packed));
1197#endif
1198 1070
1199/* 1071/*
1200 * PM_SLEEP_NOTIFICATION = 0x7A (notification only, not a command) 1072 * PM_SLEEP_NOTIFICATION = 0x7A (notification only, not a command)
@@ -1294,11 +1166,7 @@ struct iwl_scan_cmd {
1294 * (active scan) */ 1166 * (active scan) */
1295 __le16 quiet_plcp_th; /* quiet chnl is < this # pkts (typ. 1) */ 1167 __le16 quiet_plcp_th; /* quiet chnl is < this # pkts (typ. 1) */
1296 __le16 good_CRC_th; /* passive -> active promotion threshold */ 1168 __le16 good_CRC_th; /* passive -> active promotion threshold */
1297#if IWL == 3945
1298 __le16 reserved1;
1299#elif IWL == 4965
1300 __le16 rx_chain; 1169 __le16 rx_chain;
1301#endif
1302 __le32 max_out_time; /* max usec to be out of associated (service) 1170 __le32 max_out_time; /* max usec to be out of associated (service)
1303 * chnl */ 1171 * chnl */
1304 __le32 suspend_time; /* pause scan this long when returning to svc 1172 __le32 suspend_time; /* pause scan this long when returning to svc
@@ -1450,16 +1318,13 @@ struct statistics_rx_phy {
1450 __le32 rxe_frame_limit_overrun; 1318 __le32 rxe_frame_limit_overrun;
1451 __le32 sent_ack_cnt; 1319 __le32 sent_ack_cnt;
1452 __le32 sent_cts_cnt; 1320 __le32 sent_cts_cnt;
1453#if IWL == 4965
1454 __le32 sent_ba_rsp_cnt; 1321 __le32 sent_ba_rsp_cnt;
1455 __le32 dsp_self_kill; 1322 __le32 dsp_self_kill;
1456 __le32 mh_format_err; 1323 __le32 mh_format_err;
1457 __le32 re_acq_main_rssi_sum; 1324 __le32 re_acq_main_rssi_sum;
1458 __le32 reserved3; 1325 __le32 reserved3;
1459#endif
1460} __attribute__ ((packed)); 1326} __attribute__ ((packed));
1461 1327
1462#if IWL == 4965
1463struct statistics_rx_ht_phy { 1328struct statistics_rx_ht_phy {
1464 __le32 plcp_err; 1329 __le32 plcp_err;
1465 __le32 overrun_err; 1330 __le32 overrun_err;
@@ -1472,7 +1337,6 @@ struct statistics_rx_ht_phy {
1472 __le32 agg_cnt; 1337 __le32 agg_cnt;
1473 __le32 reserved2; 1338 __le32 reserved2;
1474} __attribute__ ((packed)); 1339} __attribute__ ((packed));
1475#endif
1476 1340
1477struct statistics_rx_non_phy { 1341struct statistics_rx_non_phy {
1478 __le32 bogus_cts; /* CTS received when not expecting CTS */ 1342 __le32 bogus_cts; /* CTS received when not expecting CTS */
@@ -1483,7 +1347,6 @@ struct statistics_rx_non_phy {
1483 * filtering process */ 1347 * filtering process */
1484 __le32 non_channel_beacons; /* beacons with our bss id but not on 1348 __le32 non_channel_beacons; /* beacons with our bss id but not on
1485 * our serving channel */ 1349 * our serving channel */
1486#if IWL == 4965
1487 __le32 channel_beacons; /* beacons with our bss id and in our 1350 __le32 channel_beacons; /* beacons with our bss id and in our
1488 * serving channel */ 1351 * serving channel */
1489 __le32 num_missed_bcon; /* number of missed beacons */ 1352 __le32 num_missed_bcon; /* number of missed beacons */
@@ -1506,19 +1369,15 @@ struct statistics_rx_non_phy {
1506 __le32 beacon_energy_a; 1369 __le32 beacon_energy_a;
1507 __le32 beacon_energy_b; 1370 __le32 beacon_energy_b;
1508 __le32 beacon_energy_c; 1371 __le32 beacon_energy_c;
1509#endif
1510} __attribute__ ((packed)); 1372} __attribute__ ((packed));
1511 1373
1512struct statistics_rx { 1374struct statistics_rx {
1513 struct statistics_rx_phy ofdm; 1375 struct statistics_rx_phy ofdm;
1514 struct statistics_rx_phy cck; 1376 struct statistics_rx_phy cck;
1515 struct statistics_rx_non_phy general; 1377 struct statistics_rx_non_phy general;
1516#if IWL == 4965
1517 struct statistics_rx_ht_phy ofdm_ht; 1378 struct statistics_rx_ht_phy ofdm_ht;
1518#endif
1519} __attribute__ ((packed)); 1379} __attribute__ ((packed));
1520 1380
1521#if IWL == 4965
1522struct statistics_tx_non_phy_agg { 1381struct statistics_tx_non_phy_agg {
1523 __le32 ba_timeout; 1382 __le32 ba_timeout;
1524 __le32 ba_reschedule_frames; 1383 __le32 ba_reschedule_frames;
@@ -1533,7 +1392,6 @@ struct statistics_tx_non_phy_agg {
1533 __le32 reserved2; 1392 __le32 reserved2;
1534 __le32 reserved3; 1393 __le32 reserved3;
1535} __attribute__ ((packed)); 1394} __attribute__ ((packed));
1536#endif
1537 1395
1538struct statistics_tx { 1396struct statistics_tx {
1539 __le32 preamble_cnt; 1397 __le32 preamble_cnt;
@@ -1545,14 +1403,12 @@ struct statistics_tx {
1545 __le32 ack_timeout; 1403 __le32 ack_timeout;
1546 __le32 expected_ack_cnt; 1404 __le32 expected_ack_cnt;
1547 __le32 actual_ack_cnt; 1405 __le32 actual_ack_cnt;
1548#if IWL == 4965
1549 __le32 dump_msdu_cnt; 1406 __le32 dump_msdu_cnt;
1550 __le32 burst_abort_next_frame_mismatch_cnt; 1407 __le32 burst_abort_next_frame_mismatch_cnt;
1551 __le32 burst_abort_missing_next_frame_cnt; 1408 __le32 burst_abort_missing_next_frame_cnt;
1552 __le32 cts_timeout_collision; 1409 __le32 cts_timeout_collision;
1553 __le32 ack_or_ba_timeout_collision; 1410 __le32 ack_or_ba_timeout_collision;
1554 struct statistics_tx_non_phy_agg agg; 1411 struct statistics_tx_non_phy_agg agg;
1555#endif
1556} __attribute__ ((packed)); 1412} __attribute__ ((packed));
1557 1413
1558struct statistics_dbg { 1414struct statistics_dbg {
@@ -1566,29 +1422,23 @@ struct statistics_div {
1566 __le32 tx_on_b; 1422 __le32 tx_on_b;
1567 __le32 exec_time; 1423 __le32 exec_time;
1568 __le32 probe_time; 1424 __le32 probe_time;
1569#if IWL == 4965
1570 __le32 reserved1; 1425 __le32 reserved1;
1571 __le32 reserved2; 1426 __le32 reserved2;
1572#endif
1573} __attribute__ ((packed)); 1427} __attribute__ ((packed));
1574 1428
1575struct statistics_general { 1429struct statistics_general {
1576 __le32 temperature; 1430 __le32 temperature;
1577#if IWL == 4965
1578 __le32 temperature_m; 1431 __le32 temperature_m;
1579#endif
1580 struct statistics_dbg dbg; 1432 struct statistics_dbg dbg;
1581 __le32 sleep_time; 1433 __le32 sleep_time;
1582 __le32 slots_out; 1434 __le32 slots_out;
1583 __le32 slots_idle; 1435 __le32 slots_idle;
1584 __le32 ttl_timestamp; 1436 __le32 ttl_timestamp;
1585 struct statistics_div div; 1437 struct statistics_div div;
1586#if IWL == 4965
1587 __le32 rx_enable_counter; 1438 __le32 rx_enable_counter;
1588 __le32 reserved1; 1439 __le32 reserved1;
1589 __le32 reserved2; 1440 __le32 reserved2;
1590 __le32 reserved3; 1441 __le32 reserved3;
1591#endif
1592} __attribute__ ((packed)); 1442} __attribute__ ((packed));
1593 1443
1594/* 1444/*
@@ -1720,10 +1570,8 @@ struct iwl_rx_packet {
1720 struct iwl_sleep_notification sleep_notif; 1570 struct iwl_sleep_notification sleep_notif;
1721 struct iwl_spectrum_resp spectrum; 1571 struct iwl_spectrum_resp spectrum;
1722 struct iwl_notif_statistics stats; 1572 struct iwl_notif_statistics stats;
1723#if IWL == 4965
1724 struct iwl_compressed_ba_resp compressed_ba; 1573 struct iwl_compressed_ba_resp compressed_ba;
1725 struct iwl_missed_beacon_notif missed_beacon; 1574 struct iwl_missed_beacon_notif missed_beacon;
1726#endif
1727 __le32 status; 1575 __le32 status;
1728 u8 raw[0]; 1576 u8 raw[0];
1729 } u; 1577 } u;
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-debug.h b/drivers/net/wireless/iwlwifi/iwl-4965-debug.h
new file mode 100644
index 000000000000..72318d78957e
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-debug.h
@@ -0,0 +1,152 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 *
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
22 *
23 * Contact Information:
24 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *
27 *****************************************************************************/
28
29#ifndef __iwl_debug_h__
30#define __iwl_debug_h__
31
32#ifdef CONFIG_IWLWIFI_DEBUG
33extern u32 iwl_debug_level;
34#define IWL_DEBUG(level, fmt, args...) \
35do { if (iwl_debug_level & (level)) \
36 printk(KERN_ERR DRV_NAME": %c %s " fmt, \
37 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
38
39#define IWL_DEBUG_LIMIT(level, fmt, args...) \
40do { if ((iwl_debug_level & (level)) && net_ratelimit()) \
41 printk(KERN_ERR DRV_NAME": %c %s " fmt, \
42 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
43#else
44static inline void IWL_DEBUG(int level, const char *fmt, ...)
45{
46}
47static inline void IWL_DEBUG_LIMIT(int level, const char *fmt, ...)
48{
49}
50#endif /* CONFIG_IWLWIFI_DEBUG */
51
52/*
53 * To use the debug system;
54 *
55 * If you are defining a new debug classification, simply add it to the #define
56 * list here in the form of:
57 *
58 * #define IWL_DL_xxxx VALUE
59 *
60 * shifting value to the left one bit from the previous entry. xxxx should be
61 * the name of the classification (for example, WEP)
62 *
63 * You then need to either add a IWL_xxxx_DEBUG() macro definition for your
64 * classification, or use IWL_DEBUG(IWL_DL_xxxx, ...) whenever you want
65 * to send output to that classification.
66 *
67 * To add your debug level to the list of levels seen when you perform
68 *
69 * % cat /proc/net/iwl/debug_level
70 *
71 * you simply need to add your entry to the iwl_debug_levels array.
72 *
73 * If you do not see debug_level in /proc/net/iwl then you do not have
74 * CONFIG_IWLWIFI_DEBUG defined in your kernel configuration
75 *
76 */
77
78#define IWL_DL_INFO (1<<0)
79#define IWL_DL_MAC80211 (1<<1)
80#define IWL_DL_HOST_COMMAND (1<<2)
81#define IWL_DL_STATE (1<<3)
82
83#define IWL_DL_RADIO (1<<7)
84#define IWL_DL_POWER (1<<8)
85#define IWL_DL_TEMP (1<<9)
86
87#define IWL_DL_NOTIF (1<<10)
88#define IWL_DL_SCAN (1<<11)
89#define IWL_DL_ASSOC (1<<12)
90#define IWL_DL_DROP (1<<13)
91
92#define IWL_DL_TXPOWER (1<<14)
93
94#define IWL_DL_AP (1<<15)
95
96#define IWL_DL_FW (1<<16)
97#define IWL_DL_RF_KILL (1<<17)
98#define IWL_DL_FW_ERRORS (1<<18)
99
100#define IWL_DL_LED (1<<19)
101
102#define IWL_DL_RATE (1<<20)
103
104#define IWL_DL_CALIB (1<<21)
105#define IWL_DL_WEP (1<<22)
106#define IWL_DL_TX (1<<23)
107#define IWL_DL_RX (1<<24)
108#define IWL_DL_ISR (1<<25)
109#define IWL_DL_HT (1<<26)
110#define IWL_DL_IO (1<<27)
111#define IWL_DL_11H (1<<28)
112
113#define IWL_DL_STATS (1<<29)
114#define IWL_DL_TX_REPLY (1<<30)
115#define IWL_DL_QOS (1<<31)
116
117#define IWL_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
118#define IWL_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
119#define IWL_DEBUG_INFO(f, a...) IWL_DEBUG(IWL_DL_INFO, f, ## a)
120
121#define IWL_DEBUG_MAC80211(f, a...) IWL_DEBUG(IWL_DL_MAC80211, f, ## a)
122#define IWL_DEBUG_TEMP(f, a...) IWL_DEBUG(IWL_DL_TEMP, f, ## a)
123#define IWL_DEBUG_SCAN(f, a...) IWL_DEBUG(IWL_DL_SCAN, f, ## a)
124#define IWL_DEBUG_RX(f, a...) IWL_DEBUG(IWL_DL_RX, f, ## a)
125#define IWL_DEBUG_TX(f, a...) IWL_DEBUG(IWL_DL_TX, f, ## a)
126#define IWL_DEBUG_ISR(f, a...) IWL_DEBUG(IWL_DL_ISR, f, ## a)
127#define IWL_DEBUG_LED(f, a...) IWL_DEBUG(IWL_DL_LED, f, ## a)
128#define IWL_DEBUG_WEP(f, a...) IWL_DEBUG(IWL_DL_WEP, f, ## a)
129#define IWL_DEBUG_HC(f, a...) IWL_DEBUG(IWL_DL_HOST_COMMAND, f, ## a)
130#define IWL_DEBUG_CALIB(f, a...) IWL_DEBUG(IWL_DL_CALIB, f, ## a)
131#define IWL_DEBUG_FW(f, a...) IWL_DEBUG(IWL_DL_FW, f, ## a)
132#define IWL_DEBUG_RF_KILL(f, a...) IWL_DEBUG(IWL_DL_RF_KILL, f, ## a)
133#define IWL_DEBUG_DROP(f, a...) IWL_DEBUG(IWL_DL_DROP, f, ## a)
134#define IWL_DEBUG_DROP_LIMIT(f, a...) IWL_DEBUG_LIMIT(IWL_DL_DROP, f, ## a)
135#define IWL_DEBUG_AP(f, a...) IWL_DEBUG(IWL_DL_AP, f, ## a)
136#define IWL_DEBUG_TXPOWER(f, a...) IWL_DEBUG(IWL_DL_TXPOWER, f, ## a)
137#define IWL_DEBUG_IO(f, a...) IWL_DEBUG(IWL_DL_IO, f, ## a)
138#define IWL_DEBUG_RATE(f, a...) IWL_DEBUG(IWL_DL_RATE, f, ## a)
139#define IWL_DEBUG_RATE_LIMIT(f, a...) IWL_DEBUG_LIMIT(IWL_DL_RATE, f, ## a)
140#define IWL_DEBUG_NOTIF(f, a...) IWL_DEBUG(IWL_DL_NOTIF, f, ## a)
141#define IWL_DEBUG_ASSOC(f, a...) IWL_DEBUG(IWL_DL_ASSOC | IWL_DL_INFO, f, ## a)
142#define IWL_DEBUG_ASSOC_LIMIT(f, a...) \
143 IWL_DEBUG_LIMIT(IWL_DL_ASSOC | IWL_DL_INFO, f, ## a)
144#define IWL_DEBUG_HT(f, a...) IWL_DEBUG(IWL_DL_HT, f, ## a)
145#define IWL_DEBUG_STATS(f, a...) IWL_DEBUG(IWL_DL_STATS, f, ## a)
146#define IWL_DEBUG_TX_REPLY(f, a...) IWL_DEBUG(IWL_DL_TX_REPLY, f, ## a)
147#define IWL_DEBUG_QOS(f, a...) IWL_DEBUG(IWL_DL_QOS, f, ## a)
148#define IWL_DEBUG_RADIO(f, a...) IWL_DEBUG(IWL_DL_RADIO, f, ## a)
149#define IWL_DEBUG_POWER(f, a...) IWL_DEBUG(IWL_DL_POWER, f, ## a)
150#define IWL_DEBUG_11H(f, a...) IWL_DEBUG(IWL_DL_11H, f, ## a)
151
152#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
index 5fc707b1ea7d..21c75774cf4e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
@@ -64,6 +64,683 @@
64#ifndef __iwl_4965_hw_h__ 64#ifndef __iwl_4965_hw_h__
65#define __iwl_4965_hw_h__ 65#define __iwl_4965_hw_h__
66 66
67/* uCode queue management definitions */
68#define IWL_CMD_QUEUE_NUM 4
69#define IWL_CMD_FIFO_NUM 4
70#define IWL_BACK_QUEUE_FIRST_ID 7
71
72/* Tx rates */
73#define IWL_CCK_RATES 4
74#define IWL_OFDM_RATES 8
75
76#define IWL_HT_RATES 16
77
78#define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
79
80/* Time constants */
81#define SHORT_SLOT_TIME 9
82#define LONG_SLOT_TIME 20
83
84/* RSSI to dBm */
85#define IWL_RSSI_OFFSET 44
86
87/*
88 * This file defines EEPROM related constants, enums, and inline functions.
89 *
90 */
91
92#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
93#define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */
94/* EEPROM field values */
95#define ANTENNA_SWITCH_NORMAL 0
96#define ANTENNA_SWITCH_INVERSE 1
97
98enum {
99 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
100 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
101 /* Bit 2 Reserved */
102 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
103 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
104 EEPROM_CHANNEL_WIDE = (1 << 5),
105 EEPROM_CHANNEL_NARROW = (1 << 6),
106 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
107};
108
109/* EEPROM field lengths */
110#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
111
112/* EEPROM field lengths */
113#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
114#define EEPROM_REGULATORY_SKU_ID_LENGTH 4
115#define EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH 14
116#define EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH 13
117#define EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH 12
118#define EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH 11
119#define EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH 6
120
121#define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS_LENGTH 7
122#define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS_LENGTH 11
123#define EEPROM_REGULATORY_CHANNELS_LENGTH ( \
124 EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH + \
125 EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH + \
126 EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH + \
127 EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH + \
128 EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH + \
129 EEPROM_REGULATORY_BAND_24_FAT_CHANNELS_LENGTH + \
130 EEPROM_REGULATORY_BAND_52_FAT_CHANNELS_LENGTH)
131
132#define EEPROM_REGULATORY_NUMBER_OF_BANDS 5
133
134/* SKU Capabilities */
135#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
136#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
137#define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7)
138
139/* *regulatory* channel data from eeprom, one for each channel */
140struct iwl_eeprom_channel {
141 u8 flags; /* flags copied from EEPROM */
142 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
143} __attribute__ ((packed));
144
145/*
146 * Mapping of a Tx power level, at factory calibration temperature,
147 * to a radio/DSP gain table index.
148 * One for each of 5 "sample" power levels in each band.
149 * v_det is measured at the factory, using the 3945's built-in power amplifier
150 * (PA) output voltage detector. This same detector is used during Tx of
151 * long packets in normal operation to provide feedback as to proper output
152 * level.
153 * Data copied from EEPROM.
154 */
155struct iwl_eeprom_txpower_sample {
156 u8 gain_index; /* index into power (gain) setup table ... */
157 s8 power; /* ... for this pwr level for this chnl group */
158 u16 v_det; /* PA output voltage */
159} __attribute__ ((packed));
160
161/*
162 * Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
163 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
164 * Tx power setup code interpolates between the 5 "sample" power levels
165 * to determine the nominal setup for a requested power level.
166 * Data copied from EEPROM.
167 * DO NOT ALTER THIS STRUCTURE!!!
168 */
169struct iwl_eeprom_txpower_group {
170 struct iwl_eeprom_txpower_sample samples[5]; /* 5 power levels */
171 s32 a, b, c, d, e; /* coefficients for voltage->power
172 * formula (signed) */
173 s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
174 * frequency (signed) */
175 s8 saturation_power; /* highest power possible by h/w in this
176 * band */
177 u8 group_channel; /* "representative" channel # in this band */
178 s16 temperature; /* h/w temperature at factory calib this band
179 * (signed) */
180} __attribute__ ((packed));
181
182/*
183 * Temperature-based Tx-power compensation data, not band-specific.
184 * These coefficients are use to modify a/b/c/d/e coeffs based on
185 * difference between current temperature and factory calib temperature.
186 * Data copied from EEPROM.
187 */
188struct iwl_eeprom_temperature_corr {
189 u32 Ta;
190 u32 Tb;
191 u32 Tc;
192 u32 Td;
193 u32 Te;
194} __attribute__ ((packed));
195
196#define EEPROM_TX_POWER_TX_CHAINS (2)
197#define EEPROM_TX_POWER_BANDS (8)
198#define EEPROM_TX_POWER_MEASUREMENTS (3)
199#define EEPROM_TX_POWER_VERSION (2)
200#define EEPROM_TX_POWER_VERSION_NEW (5)
201
202struct iwl_eeprom_calib_measure {
203 u8 temperature;
204 u8 gain_idx;
205 u8 actual_pow;
206 s8 pa_det;
207} __attribute__ ((packed));
208
209struct iwl_eeprom_calib_ch_info {
210 u8 ch_num;
211 struct iwl_eeprom_calib_measure measurements[EEPROM_TX_POWER_TX_CHAINS]
212 [EEPROM_TX_POWER_MEASUREMENTS];
213} __attribute__ ((packed));
214
215struct iwl_eeprom_calib_subband_info {
216 u8 ch_from;
217 u8 ch_to;
218 struct iwl_eeprom_calib_ch_info ch1;
219 struct iwl_eeprom_calib_ch_info ch2;
220} __attribute__ ((packed));
221
222struct iwl_eeprom_calib_info {
223 u8 saturation_power24;
224 u8 saturation_power52;
225 s16 voltage; /* signed */
226 struct iwl_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
227} __attribute__ ((packed));
228
229
230struct iwl_eeprom {
231 u8 reserved0[16];
232#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
233 u16 device_id; /* abs.ofs: 16 */
234 u8 reserved1[2];
235#define EEPROM_PMC (2*0x0A) /* 2 bytes */
236 u16 pmc; /* abs.ofs: 20 */
237 u8 reserved2[20];
238#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
239 u8 mac_address[6]; /* abs.ofs: 42 */
240 u8 reserved3[58];
241#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
242 u16 board_revision; /* abs.ofs: 106 */
243 u8 reserved4[11];
244#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
245 u8 board_pba_number[9]; /* abs.ofs: 119 */
246 u8 reserved5[8];
247#define EEPROM_VERSION (2*0x44) /* 2 bytes */
248 u16 version; /* abs.ofs: 136 */
249#define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */
250 u8 sku_cap; /* abs.ofs: 138 */
251#define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */
252 u8 leds_mode; /* abs.ofs: 139 */
253#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
254 u16 oem_mode;
255#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
256 u16 wowlan_mode; /* abs.ofs: 142 */
257#define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */
258 u16 leds_time_interval; /* abs.ofs: 144 */
259#define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */
260 u8 leds_off_time; /* abs.ofs: 146 */
261#define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */
262 u8 leds_on_time; /* abs.ofs: 147 */
263#define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */
264 u8 almgor_m_version; /* abs.ofs: 148 */
265#define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */
266 u8 antenna_switch_type; /* abs.ofs: 149 */
267 u8 reserved6[8];
268#define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
269 u16 board_revision_4965; /* abs.ofs: 158 */
270 u8 reserved7[13];
271#define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
272 u8 board_pba_number_4965[9]; /* abs.ofs: 173 */
273 u8 reserved8[10];
274#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
275 u8 sku_id[4]; /* abs.ofs: 192 */
276#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
277 u16 band_1_count; /* abs.ofs: 196 */
278#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
279 struct iwl_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */
280#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
281 u16 band_2_count; /* abs.ofs: 226 */
282#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
283 struct iwl_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */
284#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
285 u16 band_3_count; /* abs.ofs: 254 */
286#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
287 struct iwl_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */
288#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
289 u16 band_4_count; /* abs.ofs: 280 */
290#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
291 struct iwl_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */
292#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
293 u16 band_5_count; /* abs.ofs: 304 */
294#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
295 struct iwl_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */
296
297 u8 reserved10[2];
298#define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS (2*0xA0) /* 14 bytes */
299 struct iwl_eeprom_channel band_24_channels[7]; /* abs.ofs: 320 */
300 u8 reserved11[2];
301#define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS (2*0xA8) /* 22 bytes */
302 struct iwl_eeprom_channel band_52_channels[11]; /* abs.ofs: 336 */
303 u8 reserved12[6];
304#define EEPROM_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
305 u16 calib_version; /* abs.ofs: 364 */
306 u8 reserved13[2];
307#define EEPROM_SATURATION_POWER_OFFSET (2*0xB8) /* 2 bytes */
308 u16 satruation_power; /* abs.ofs: 368 */
309 u8 reserved14[94];
310#define EEPROM_IWL_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
311 struct iwl_eeprom_calib_info calib_info; /* abs.ofs: 464 */
312
313 u8 reserved16[140]; /* fill out to full 1024 byte block */
314
315
316} __attribute__ ((packed));
317
318#define IWL_EEPROM_IMAGE_SIZE 1024
319
320
321#include "iwl-4965-commands.h"
322
323#define PCI_LINK_CTRL 0x0F0
324#define PCI_POWER_SOURCE 0x0C8
325#define PCI_REG_WUM8 0x0E8
326#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
327
328/*=== CSR (control and status registers) ===*/
329#define CSR_BASE (0x000)
330
331#define CSR_SW_VER (CSR_BASE+0x000)
332#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
333#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
334#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
335#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
336#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
337#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
338#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
339#define CSR_GP_CNTRL (CSR_BASE+0x024)
340#define CSR_HW_REV (CSR_BASE+0x028)
341#define CSR_EEPROM_REG (CSR_BASE+0x02c)
342#define CSR_EEPROM_GP (CSR_BASE+0x030)
343#define CSR_GP_UCODE (CSR_BASE+0x044)
344#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
345#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
346#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
347#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
348#define CSR_LED_REG (CSR_BASE+0x094)
349#define CSR_DRAM_INT_TBL_CTL (CSR_BASE+0x0A0)
350#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
351#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
352#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
353
354/* HW I/F configuration */
355#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100)
356#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200)
357#define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
358#define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
359#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
360#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
361#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
362
363/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
364 * acknowledged (reset) by host writing "1" to flagged bits. */
365#define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */
366#define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */
367#define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */
368#define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */
369#define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */
370#define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */
371#define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */
372#define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */
373#define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */
374#define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */
375#define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */
376
377#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
378 CSR_INT_BIT_HW_ERR | \
379 CSR_INT_BIT_FH_TX | \
380 CSR_INT_BIT_SW_ERR | \
381 CSR_INT_BIT_RF_KILL | \
382 CSR_INT_BIT_SW_RX | \
383 CSR_INT_BIT_WAKEUP | \
384 CSR_INT_BIT_ALIVE)
385
386/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
387#define CSR_FH_INT_BIT_ERR (1<<31) /* Error */
388#define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */
389#define CSR_FH_INT_BIT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */
390#define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */
391#define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */
392#define CSR_FH_INT_BIT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */
393#define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */
394#define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */
395
396#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
397 CSR_FH_INT_BIT_RX_CHNL2 | \
398 CSR_FH_INT_BIT_RX_CHNL1 | \
399 CSR_FH_INT_BIT_RX_CHNL0)
400
401#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL6 | \
402 CSR_FH_INT_BIT_TX_CHNL1 | \
403 CSR_FH_INT_BIT_TX_CHNL0 )
404
405
406/* RESET */
407#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
408#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
409#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
410#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
411#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
412
413/* GP (general purpose) CONTROL */
414#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
415#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
416#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
417#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
418
419#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
420
421#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
422#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
423#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
424
425
426/* EEPROM REG */
427#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
428#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
429
430/* EEPROM GP */
431#define CSR_EEPROM_GP_VALID_MSK (0x00000006)
432#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
433#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
434
435/* UCODE DRV GP */
436#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
437#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
438#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
439#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
440
441/* GPIO */
442#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
443#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
444#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
445
446/* GI Chicken Bits */
447#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
448#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
449
450/* CSR_ANA_PLL_CFG */
451#define CSR_ANA_PLL_CFG_SH (0x00880300)
452
453#define CSR_LED_REG_TRUN_ON (0x00000078)
454#define CSR_LED_REG_TRUN_OFF (0x00000038)
455#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
456
457/* DRAM_INT_TBL_CTRL */
458#define CSR_DRAM_INT_TBL_CTRL_EN (1<<31)
459#define CSR_DRAM_INT_TBL_CTRL_WRAP_CHK (1<<27)
460
461/*=== HBUS (Host-side Bus) ===*/
462#define HBUS_BASE (0x400)
463
464#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
465#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
466#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
467#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
468#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
469#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
470#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
471#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
472#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
473
474#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
475
476
477/* SCD (Scheduler) */
478#define SCD_BASE (CSR_BASE + 0x2E00)
479
480#define SCD_MODE_REG (SCD_BASE + 0x000)
481#define SCD_ARASTAT_REG (SCD_BASE + 0x004)
482#define SCD_TXFACT_REG (SCD_BASE + 0x010)
483#define SCD_TXF4MF_REG (SCD_BASE + 0x014)
484#define SCD_TXF5MF_REG (SCD_BASE + 0x020)
485#define SCD_SBYP_MODE_1_REG (SCD_BASE + 0x02C)
486#define SCD_SBYP_MODE_2_REG (SCD_BASE + 0x030)
487
488/*=== FH (data Flow Handler) ===*/
489#define FH_BASE (0x800)
490
491#define FH_CBCC_TABLE (FH_BASE+0x140)
492#define FH_TFDB_TABLE (FH_BASE+0x180)
493#define FH_RCSR_TABLE (FH_BASE+0x400)
494#define FH_RSSR_TABLE (FH_BASE+0x4c0)
495#define FH_TCSR_TABLE (FH_BASE+0x500)
496#define FH_TSSR_TABLE (FH_BASE+0x680)
497
498/* TFDB (Transmit Frame Buffer Descriptor) */
499#define FH_TFDB(_channel, buf) \
500 (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
501#define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
502 (FH_TFDB_TABLE + 0x50 * _channel)
503/* CBCC _channel is [0,2] */
504#define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8)
505#define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00)
506#define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04)
507
508/* RCSR _channel is [0,2] */
509#define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40)
510#define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00)
511#define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04)
512#define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20)
513#define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
514
515#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
516
517/* RSSR */
518#define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000)
519#define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004)
520/* TCSR */
521#define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20)
522#define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00)
523#define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04)
524#define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
525/* TSSR */
526#define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000)
527#define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008)
528#define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010)
529/* 18 - reserved */
530
531/* card static random access memory (SRAM) for processor data and instructs */
532#define RTC_INST_LOWER_BOUND (0x000000)
533#define RTC_DATA_LOWER_BOUND (0x800000)
534
535
536/* DBM */
537
538#define ALM_FH_SRVC_CHNL (6)
539
540#define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
541#define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
542
543#define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
544
545#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
546
547#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
548
549#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
550
551#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
552
553#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
554
555#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
556#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
557
558#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
559#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
560
561#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
562
563#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
564
565#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
566#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
567
568#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
569
570#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
571
572#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
573#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
574
575#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
576
577#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
578#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
579
580#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
581#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
582
583#define ALM_TB_MAX_BYTES_COUNT (0xFFF0)
584
585#define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
586 ((1LU << _channel) << 24)
587#define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
588 ((1LU << _channel) << 16)
589
590#define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
591 (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
592 ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
593#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
594#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
595
596#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
597
598#define TFD_QUEUE_MIN 0
599#define TFD_QUEUE_MAX 6
600#define TFD_QUEUE_SIZE_MAX (256)
601
602/* spectrum and channel data structures */
603#define IWL_NUM_SCAN_RATES (2)
604
605#define IWL_SCAN_FLAG_24GHZ (1<<0)
606#define IWL_SCAN_FLAG_52GHZ (1<<1)
607#define IWL_SCAN_FLAG_ACTIVE (1<<2)
608#define IWL_SCAN_FLAG_DIRECT (1<<3)
609
610#define IWL_MAX_CMD_SIZE 1024
611
612#define IWL_DEFAULT_TX_RETRY 15
613#define IWL_MAX_TX_RETRY 16
614
615/*********************************************/
616
617#define RFD_SIZE 4
618#define NUM_TFD_CHUNKS 4
619
620#define RX_QUEUE_SIZE 256
621#define RX_QUEUE_MASK 255
622#define RX_QUEUE_SIZE_LOG 8
623
624/* QoS definitions */
625
626#define CW_MIN_OFDM 15
627#define CW_MAX_OFDM 1023
628#define CW_MIN_CCK 31
629#define CW_MAX_CCK 1023
630
631#define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM
632#define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM
633#define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
634#define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1)
635
636#define QOS_TX0_CW_MIN_CCK CW_MIN_CCK
637#define QOS_TX1_CW_MIN_CCK CW_MIN_CCK
638#define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1)
639#define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1)
640
641#define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM
642#define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM
643#define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM
644#define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
645
646#define QOS_TX0_CW_MAX_CCK CW_MAX_CCK
647#define QOS_TX1_CW_MAX_CCK CW_MAX_CCK
648#define QOS_TX2_CW_MAX_CCK CW_MIN_CCK
649#define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1)
650
651#define QOS_TX0_AIFS 3
652#define QOS_TX1_AIFS 7
653#define QOS_TX2_AIFS 2
654#define QOS_TX3_AIFS 2
655
656#define QOS_TX0_ACM 0
657#define QOS_TX1_ACM 0
658#define QOS_TX2_ACM 0
659#define QOS_TX3_ACM 0
660
661#define QOS_TX0_TXOP_LIMIT_CCK 0
662#define QOS_TX1_TXOP_LIMIT_CCK 0
663#define QOS_TX2_TXOP_LIMIT_CCK 6016
664#define QOS_TX3_TXOP_LIMIT_CCK 3264
665
666#define QOS_TX0_TXOP_LIMIT_OFDM 0
667#define QOS_TX1_TXOP_LIMIT_OFDM 0
668#define QOS_TX2_TXOP_LIMIT_OFDM 3008
669#define QOS_TX3_TXOP_LIMIT_OFDM 1504
670
671#define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM
672#define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM
673#define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM
674#define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM
675
676#define DEF_TX0_CW_MIN_CCK CW_MIN_CCK
677#define DEF_TX1_CW_MIN_CCK CW_MIN_CCK
678#define DEF_TX2_CW_MIN_CCK CW_MIN_CCK
679#define DEF_TX3_CW_MIN_CCK CW_MIN_CCK
680
681#define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM
682#define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM
683#define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM
684#define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM
685
686#define DEF_TX0_CW_MAX_CCK CW_MAX_CCK
687#define DEF_TX1_CW_MAX_CCK CW_MAX_CCK
688#define DEF_TX2_CW_MAX_CCK CW_MAX_CCK
689#define DEF_TX3_CW_MAX_CCK CW_MAX_CCK
690
691#define DEF_TX0_AIFS (2)
692#define DEF_TX1_AIFS (2)
693#define DEF_TX2_AIFS (2)
694#define DEF_TX3_AIFS (2)
695
696#define DEF_TX0_ACM 0
697#define DEF_TX1_ACM 0
698#define DEF_TX2_ACM 0
699#define DEF_TX3_ACM 0
700
701#define DEF_TX0_TXOP_LIMIT_CCK 0
702#define DEF_TX1_TXOP_LIMIT_CCK 0
703#define DEF_TX2_TXOP_LIMIT_CCK 0
704#define DEF_TX3_TXOP_LIMIT_CCK 0
705
706#define DEF_TX0_TXOP_LIMIT_OFDM 0
707#define DEF_TX1_TXOP_LIMIT_OFDM 0
708#define DEF_TX2_TXOP_LIMIT_OFDM 0
709#define DEF_TX3_TXOP_LIMIT_OFDM 0
710
711#define QOS_QOS_SETS 3
712#define QOS_PARAM_SET_ACTIVE 0
713#define QOS_PARAM_SET_DEF_CCK 1
714#define QOS_PARAM_SET_DEF_OFDM 2
715
716#define CTRL_QOS_NO_ACK (0x0020)
717#define DCT_FLAG_EXT_QOS_ENABLED (0x10)
718
719#define U32_PAD(n) ((4-(n))&0x3)
720
721/*
722 * Generic queue structure
723 *
724 * Contains common data for Rx and Tx queues
725 */
726#define TFD_CTL_COUNT_SET(n) (n<<24)
727#define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7)
728#define TFD_CTL_PAD_SET(n) (n<<28)
729#define TFD_CTL_PAD_GET(ctl) (ctl>>28)
730
731#define TFD_TX_CMD_SLOTS 256
732#define TFD_CMD_SLOTS 32
733
734#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
735 sizeof(struct iwl_cmd_meta))
736
737/*
738 * RX related structures and functions
739 */
740#define RX_FREE_BUFFERS 64
741#define RX_LOW_WATERMARK 8
742
743
67#define IWL_RX_BUF_SIZE (4 * 1024) 744#define IWL_RX_BUF_SIZE (4 * 1024)
68#define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE 745#define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
69#define KDR_RTC_INST_UPPER_BOUND (0x018000) 746#define KDR_RTC_INST_UPPER_BOUND (0x018000)
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-io.h b/drivers/net/wireless/iwlwifi/iwl-4965-io.h
new file mode 100644
index 000000000000..1ffa8f1e17c4
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-io.h
@@ -0,0 +1,431 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 *
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
22 *
23 * Contact Information:
24 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *
27 *****************************************************************************/
28
29#ifndef __iwl_io_h__
30#define __iwl_io_h__
31
32#include <linux/io.h>
33
34#include "iwl-4965-debug.h"
35
36/*
37 * IO, register, and NIC memory access functions
38 *
39 * NOTE on naming convention and macro usage for these
40 *
41 * A single _ prefix before a an access function means that no state
42 * check or debug information is printed when that function is called.
43 *
44 * A double __ prefix before an access function means that state is checked
45 * and the current line number is printed in addition to any other debug output.
46 *
47 * The non-prefixed name is the #define that maps the caller into a
48 * #define that provides the caller's __LINE__ to the double prefix version.
49 *
50 * If you wish to call the function without any debug or state checking,
51 * you should use the single _ prefix version (as is used by dependent IO
52 * routines, for example _iwl_read_direct32 calls the non-check version of
53 * _iwl_read32.)
54 *
55 * These declarations are *extremely* useful in quickly isolating code deltas
56 * which result in misconfiguring of the hardware I/O. In combination with
57 * git-bisect and the IO debug level you can quickly determine the specific
58 * commit which breaks the IO sequence to the hardware.
59 *
60 */
61
62#define _iwl_write32(iwl, ofs, val) writel((val), (iwl)->hw_base + (ofs))
63#ifdef CONFIG_IWLWIFI_DEBUG
64static inline void __iwl_write32(const char *f, u32 l, struct iwl_priv *iwl,
65 u32 ofs, u32 val)
66{
67 IWL_DEBUG_IO("write32(0x%08X, 0x%08X) - %s %d\n", ofs, val, f, l);
68 _iwl_write32(iwl, ofs, val);
69}
70#define iwl_write32(iwl, ofs, val) \
71 __iwl_write32(__FILE__, __LINE__, iwl, ofs, val)
72#else
73#define iwl_write32(iwl, ofs, val) _iwl_write32(iwl, ofs, val)
74#endif
75
76#define _iwl_read32(iwl, ofs) readl((iwl)->hw_base + (ofs))
77#ifdef CONFIG_IWLWIFI_DEBUG
78static inline u32 __iwl_read32(char *f, u32 l, struct iwl_priv *iwl, u32 ofs)
79{
80 IWL_DEBUG_IO("read_direct32(0x%08X) - %s %d\n", ofs, f, l);
81 return _iwl_read32(iwl, ofs);
82}
83#define iwl_read32(iwl, ofs) __iwl_read32(__FILE__, __LINE__, iwl, ofs)
84#else
85#define iwl_read32(p, o) _iwl_read32(p, o)
86#endif
87
88static inline int _iwl_poll_bit(struct iwl_priv *priv, u32 addr,
89 u32 bits, u32 mask, int timeout)
90{
91 int i = 0;
92
93 do {
94 if ((_iwl_read32(priv, addr) & mask) == (bits & mask))
95 return i;
96 mdelay(10);
97 i += 10;
98 } while (i < timeout);
99
100 return -ETIMEDOUT;
101}
102#ifdef CONFIG_IWLWIFI_DEBUG
103static inline int __iwl_poll_bit(const char *f, u32 l,
104 struct iwl_priv *priv, u32 addr,
105 u32 bits, u32 mask, int timeout)
106{
107 int ret = _iwl_poll_bit(priv, addr, bits, mask, timeout);
108 if (unlikely(ret == -ETIMEDOUT))
109 IWL_DEBUG_IO
110 ("poll_bit(0x%08X, 0x%08X, 0x%08X) - timedout - %s %d\n",
111 addr, bits, mask, f, l);
112 else
113 IWL_DEBUG_IO
114 ("poll_bit(0x%08X, 0x%08X, 0x%08X) = 0x%08X - %s %d\n",
115 addr, bits, mask, ret, f, l);
116 return ret;
117}
118#define iwl_poll_bit(iwl, addr, bits, mask, timeout) \
119 __iwl_poll_bit(__FILE__, __LINE__, iwl, addr, bits, mask, timeout)
120#else
121#define iwl_poll_bit(p, a, b, m, t) _iwl_poll_bit(p, a, b, m, t)
122#endif
123
124static inline void _iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
125{
126 _iwl_write32(priv, reg, _iwl_read32(priv, reg) | mask);
127}
128#ifdef CONFIG_IWLWIFI_DEBUG
129static inline void __iwl_set_bit(const char *f, u32 l,
130 struct iwl_priv *priv, u32 reg, u32 mask)
131{
132 u32 val = _iwl_read32(priv, reg) | mask;
133 IWL_DEBUG_IO("set_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
134 _iwl_write32(priv, reg, val);
135}
136#define iwl_set_bit(p, r, m) __iwl_set_bit(__FILE__, __LINE__, p, r, m)
137#else
138#define iwl_set_bit(p, r, m) _iwl_set_bit(p, r, m)
139#endif
140
141static inline void _iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
142{
143 _iwl_write32(priv, reg, _iwl_read32(priv, reg) & ~mask);
144}
145#ifdef CONFIG_IWLWIFI_DEBUG
146static inline void __iwl_clear_bit(const char *f, u32 l,
147 struct iwl_priv *priv, u32 reg, u32 mask)
148{
149 u32 val = _iwl_read32(priv, reg) & ~mask;
150 IWL_DEBUG_IO("clear_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
151 _iwl_write32(priv, reg, val);
152}
153#define iwl_clear_bit(p, r, m) __iwl_clear_bit(__FILE__, __LINE__, p, r, m)
154#else
155#define iwl_clear_bit(p, r, m) _iwl_clear_bit(p, r, m)
156#endif
157
158static inline int _iwl_grab_nic_access(struct iwl_priv *priv)
159{
160 int ret;
161 u32 gp_ctl;
162
163#ifdef CONFIG_IWLWIFI_DEBUG
164 if (atomic_read(&priv->restrict_refcnt))
165 return 0;
166#endif
167 if (test_bit(STATUS_RF_KILL_HW, &priv->status) ||
168 test_bit(STATUS_RF_KILL_SW, &priv->status)) {
169 IWL_WARNING("WARNING: Requesting MAC access during RFKILL "
170 "wakes up NIC\n");
171
172 /* 10 msec allows time for NIC to complete its data save */
173 gp_ctl = _iwl_read32(priv, CSR_GP_CNTRL);
174 if (gp_ctl & CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY) {
175 IWL_DEBUG_RF_KILL("Wait for complete power-down, "
176 "gpctl = 0x%08x\n", gp_ctl);
177 mdelay(10);
178 } else
179 IWL_DEBUG_RF_KILL("power-down complete, "
180 "gpctl = 0x%08x\n", gp_ctl);
181 }
182
183 /* this bit wakes up the NIC */
184 _iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
185 ret = _iwl_poll_bit(priv, CSR_GP_CNTRL,
186 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
187 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
188 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 50);
189 if (ret < 0) {
190 IWL_ERROR("MAC is in deep sleep!\n");
191 return -EIO;
192 }
193
194#ifdef CONFIG_IWLWIFI_DEBUG
195 atomic_inc(&priv->restrict_refcnt);
196#endif
197 return 0;
198}
199
200#ifdef CONFIG_IWLWIFI_DEBUG
201static inline int __iwl_grab_nic_access(const char *f, u32 l,
202 struct iwl_priv *priv)
203{
204 if (atomic_read(&priv->restrict_refcnt))
205 IWL_DEBUG_INFO("Grabbing access while already held at "
206 "line %d.\n", l);
207
208 IWL_DEBUG_IO("grabbing nic access - %s %d\n", f, l);
209 return _iwl_grab_nic_access(priv);
210}
211#define iwl_grab_nic_access(priv) \
212 __iwl_grab_nic_access(__FILE__, __LINE__, priv)
213#else
214#define iwl_grab_nic_access(priv) \
215 _iwl_grab_nic_access(priv)
216#endif
217
218static inline void _iwl_release_nic_access(struct iwl_priv *priv)
219{
220#ifdef CONFIG_IWLWIFI_DEBUG
221 if (atomic_dec_and_test(&priv->restrict_refcnt))
222#endif
223 _iwl_clear_bit(priv, CSR_GP_CNTRL,
224 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
225}
226#ifdef CONFIG_IWLWIFI_DEBUG
227static inline void __iwl_release_nic_access(const char *f, u32 l,
228 struct iwl_priv *priv)
229{
230 if (atomic_read(&priv->restrict_refcnt) <= 0)
231 IWL_ERROR("Release unheld nic access at line %d.\n", l);
232
233 IWL_DEBUG_IO("releasing nic access - %s %d\n", f, l);
234 _iwl_release_nic_access(priv);
235}
236#define iwl_release_nic_access(priv) \
237 __iwl_release_nic_access(__FILE__, __LINE__, priv)
238#else
239#define iwl_release_nic_access(priv) \
240 _iwl_release_nic_access(priv)
241#endif
242
243static inline u32 _iwl_read_direct32(struct iwl_priv *priv, u32 reg)
244{
245 return _iwl_read32(priv, reg);
246}
247#ifdef CONFIG_IWLWIFI_DEBUG
248static inline u32 __iwl_read_direct32(const char *f, u32 l,
249 struct iwl_priv *priv, u32 reg)
250{
251 u32 value = _iwl_read_direct32(priv, reg);
252 if (!atomic_read(&priv->restrict_refcnt))
253 IWL_ERROR("Nic access not held from %s %d\n", f, l);
254 IWL_DEBUG_IO("read_direct32(0x%4X) = 0x%08x - %s %d \n", reg, value,
255 f, l);
256 return value;
257}
258#define iwl_read_direct32(priv, reg) \
259 __iwl_read_direct32(__FILE__, __LINE__, priv, reg)
260#else
261#define iwl_read_direct32 _iwl_read_direct32
262#endif
263
264static inline void _iwl_write_direct32(struct iwl_priv *priv,
265 u32 reg, u32 value)
266{
267 _iwl_write32(priv, reg, value);
268}
269#ifdef CONFIG_IWLWIFI_DEBUG
270static void __iwl_write_direct32(u32 line,
271 struct iwl_priv *priv, u32 reg, u32 value)
272{
273 if (!atomic_read(&priv->restrict_refcnt))
274 IWL_ERROR("Nic access not held from line %d\n", line);
275 _iwl_write_direct32(priv, reg, value);
276}
277#define iwl_write_direct32(priv, reg, value) \
278 __iwl_write_direct32(__LINE__, priv, reg, value)
279#else
280#define iwl_write_direct32 _iwl_write_direct32
281#endif
282
283static inline void iwl_write_reg_buf(struct iwl_priv *priv,
284 u32 reg, u32 len, u32 *values)
285{
286 u32 count = sizeof(u32);
287
288 if ((priv != NULL) && (values != NULL)) {
289 for (; 0 < len; len -= count, reg += count, values++)
290 _iwl_write_direct32(priv, reg, *values);
291 }
292}
293
294static inline int _iwl_poll_direct_bit(struct iwl_priv *priv,
295 u32 addr, u32 mask, int timeout)
296{
297 int i = 0;
298
299 do {
300 if ((_iwl_read_direct32(priv, addr) & mask) == mask)
301 return i;
302 mdelay(10);
303 i += 10;
304 } while (i < timeout);
305
306 return -ETIMEDOUT;
307}
308
309#ifdef CONFIG_IWLWIFI_DEBUG
310static inline int __iwl_poll_direct_bit(const char *f, u32 l,
311 struct iwl_priv *priv,
312 u32 addr, u32 mask, int timeout)
313{
314 int ret = _iwl_poll_direct_bit(priv, addr, mask, timeout);
315
316 if (unlikely(ret == -ETIMEDOUT))
317 IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) - "
318 "timedout - %s %d\n", addr, mask, f, l);
319 else
320 IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) = 0x%08X "
321 "- %s %d\n", addr, mask, ret, f, l);
322 return ret;
323}
324#define iwl_poll_direct_bit(iwl, addr, mask, timeout) \
325 __iwl_poll_direct_bit(__FILE__, __LINE__, iwl, addr, mask, timeout)
326#else
327#define iwl_poll_direct_bit _iwl_poll_direct_bit
328#endif
329
330static inline u32 _iwl_read_prph(struct iwl_priv *priv, u32 reg)
331{
332 _iwl_write_direct32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
333 return _iwl_read_direct32(priv, HBUS_TARG_PRPH_RDAT);
334}
335#ifdef CONFIG_IWLWIFI_DEBUG
336static inline u32 __iwl_read_prph(u32 line, struct iwl_priv *priv, u32 reg)
337{
338 if (!atomic_read(&priv->restrict_refcnt))
339 IWL_ERROR("Nic access not held from line %d\n", line);
340 return _iwl_read_prph(priv, reg);
341}
342
343#define iwl_read_prph(priv, reg) \
344 __iwl_read_prph(__LINE__, priv, reg)
345#else
346#define iwl_read_prph _iwl_read_prph
347#endif
348
349static inline void _iwl_write_prph(struct iwl_priv *priv,
350 u32 addr, u32 val)
351{
352 _iwl_write_direct32(priv, HBUS_TARG_PRPH_WADDR,
353 ((addr & 0x0000FFFF) | (3 << 24)));
354 _iwl_write_direct32(priv, HBUS_TARG_PRPH_WDAT, val);
355}
356#ifdef CONFIG_IWLWIFI_DEBUG
357static inline void __iwl_write_prph(u32 line, struct iwl_priv *priv,
358 u32 addr, u32 val)
359{
360 if (!atomic_read(&priv->restrict_refcnt))
361 IWL_ERROR("Nic access from line %d\n", line);
362 _iwl_write_prph(priv, addr, val);
363}
364
365#define iwl_write_prph(priv, addr, val) \
366 __iwl_write_prph(__LINE__, priv, addr, val);
367#else
368#define iwl_write_prph _iwl_write_prph
369#endif
370
371#define _iwl_set_bits_prph(priv, reg, mask) \
372 _iwl_write_prph(priv, reg, (_iwl_read_prph(priv, reg) | mask))
373#ifdef CONFIG_IWLWIFI_DEBUG
374static inline void __iwl_set_bits_prph(u32 line, struct iwl_priv *priv,
375 u32 reg, u32 mask)
376{
377 if (!atomic_read(&priv->restrict_refcnt))
378 IWL_ERROR("Nic access not held from line %d\n", line);
379
380 _iwl_set_bits_prph(priv, reg, mask);
381}
382#define iwl_set_bits_prph(priv, reg, mask) \
383 __iwl_set_bits_prph(__LINE__, priv, reg, mask)
384#else
385#define iwl_set_bits_prph _iwl_set_bits_prph
386#endif
387
388#define _iwl_set_bits_mask_prph(priv, reg, bits, mask) \
389 _iwl_write_prph(priv, reg, ((_iwl_read_prph(priv, reg) & mask) | bits))
390
391#ifdef CONFIG_IWLWIFI_DEBUG
392static inline void __iwl_set_bits_mask_prph(u32 line,
393 struct iwl_priv *priv, u32 reg, u32 bits, u32 mask)
394{
395 if (!atomic_read(&priv->restrict_refcnt))
396 IWL_ERROR("Nic access not held from line %d\n", line);
397 _iwl_set_bits_mask_prph(priv, reg, bits, mask);
398}
399#define iwl_set_bits_mask_prph(priv, reg, bits, mask) \
400 __iwl_set_bits_mask_prph(__LINE__, priv, reg, bits, mask)
401#else
402#define iwl_set_bits_mask_prph _iwl_set_bits_mask_prph
403#endif
404
405static inline void iwl_clear_bits_prph(struct iwl_priv
406 *priv, u32 reg, u32 mask)
407{
408 u32 val = _iwl_read_prph(priv, reg);
409 _iwl_write_prph(priv, reg, (val & ~mask));
410}
411
412static inline u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
413{
414 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, addr);
415 return iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
416}
417
418static inline void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
419{
420 iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
421 iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, val);
422}
423
424static inline void iwl_write_targ_mem_buf(struct iwl_priv *priv, u32 addr,
425 u32 len, u32 *values)
426{
427 iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
428 for (; 0 < len; len -= sizeof(u32), values++)
429 iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, *values);
430}
431#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-rs.c b/drivers/net/wireless/iwlwifi/iwl-4965-rs.c
index b557faa6ff08..0e384e60648e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-rs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-rs.c
@@ -36,11 +36,9 @@
36 36
37#include <linux/workqueue.h> 37#include <linux/workqueue.h>
38 38
39#define IWL 4965
40
41#include "../net/mac80211/ieee80211_rate.h" 39#include "../net/mac80211/ieee80211_rate.h"
42 40
43#include "iwlwifi.h" 41#include "iwl-4965.h"
44#include "iwl-helpers.h" 42#include "iwl-helpers.h"
45 43
46#define RS_NAME "iwl-4965-rs" 44#define RS_NAME "iwl-4965-rs"
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 28f7aa802fde..f8f77fe41283 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -37,9 +37,6 @@
37#include <net/mac80211.h> 37#include <net/mac80211.h>
38#include <linux/etherdevice.h> 38#include <linux/etherdevice.h>
39 39
40#define IWL 4965
41
42#include "iwlwifi.h"
43#include "iwl-4965.h" 40#include "iwl-4965.h"
44#include "iwl-helpers.h" 41#include "iwl-helpers.h"
45 42
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.h b/drivers/net/wireless/iwlwifi/iwl-4965.h
index b31a7e4b7d78..bf174d3b8fbf 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.h
@@ -26,6 +26,707 @@
26#ifndef __iwl_4965_h__ 26#ifndef __iwl_4965_h__
27#define __iwl_4965_h__ 27#define __iwl_4965_h__
28 28
29#include <linux/pci.h> /* for struct pci_device_id */
30#include <linux/kernel.h>
31#include <net/ieee80211_radiotap.h>
32
33struct iwl_priv;
34
35/* Hardware specific file defines the PCI IDs table for that hardware module */
36extern struct pci_device_id iwl_hw_card_ids[];
37
38#define DRV_NAME "iwl4965"
39#include "iwl-4965-hw.h"
40#include "iwl-prph.h"
41#include "iwl-4965-debug.h"
42
43/* Default noise level to report when noise measurement is not available.
44 * This may be because we're:
45 * 1) Not associated (4965, no beacon statistics being sent to driver)
46 * 2) Scanning (noise measurement does not apply to associated channel)
47 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
48 * Use default noise value of -127 ... this is below the range of measurable
49 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
50 * Also, -127 works better than 0 when averaging frames with/without
51 * noise info (e.g. averaging might be done in app); measured dBm values are
52 * always negative ... using a negative value as the default keeps all
53 * averages within an s8's (used in some apps) range of negative values. */
54#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
55
56/* Module parameters accessible from iwl-*.c */
57extern int iwl_param_hwcrypto;
58extern int iwl_param_queues_num;
59
60enum iwl_antenna {
61 IWL_ANTENNA_DIVERSITY,
62 IWL_ANTENNA_MAIN,
63 IWL_ANTENNA_AUX
64};
65
66/*
67 * RTS threshold here is total size [2347] minus 4 FCS bytes
68 * Per spec:
69 * a value of 0 means RTS on all data/management packets
70 * a value > max MSDU size means no RTS
71 * else RTS for data/management frames where MPDU is larger
72 * than RTS value.
73 */
74#define DEFAULT_RTS_THRESHOLD 2347U
75#define MIN_RTS_THRESHOLD 0U
76#define MAX_RTS_THRESHOLD 2347U
77#define MAX_MSDU_SIZE 2304U
78#define MAX_MPDU_SIZE 2346U
79#define DEFAULT_BEACON_INTERVAL 100U
80#define DEFAULT_SHORT_RETRY_LIMIT 7U
81#define DEFAULT_LONG_RETRY_LIMIT 4U
82
83struct iwl_rx_mem_buffer {
84 dma_addr_t dma_addr;
85 struct sk_buff *skb;
86 struct list_head list;
87};
88
89struct iwl_rt_rx_hdr {
90 struct ieee80211_radiotap_header rt_hdr;
91 __le64 rt_tsf; /* TSF */
92 u8 rt_flags; /* radiotap packet flags */
93 u8 rt_rate; /* rate in 500kb/s */
94 __le16 rt_channelMHz; /* channel in MHz */
95 __le16 rt_chbitmask; /* channel bitfield */
96 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
97 s8 rt_dbmnoise;
98 u8 rt_antenna; /* antenna number */
99 u8 payload[0]; /* payload... */
100} __attribute__ ((packed));
101
102struct iwl_rt_tx_hdr {
103 struct ieee80211_radiotap_header rt_hdr;
104 u8 rt_rate; /* rate in 500kb/s */
105 __le16 rt_channel; /* channel in mHz */
106 __le16 rt_chbitmask; /* channel bitfield */
107 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
108 u8 rt_antenna; /* antenna number */
109 u8 payload[0]; /* payload... */
110} __attribute__ ((packed));
111
112/*
113 * Generic queue structure
114 *
115 * Contains common data for Rx and Tx queues
116 */
117struct iwl_queue {
118 int n_bd; /* number of BDs in this queue */
119 int write_ptr; /* 1-st empty entry (index) host_w*/
120 int read_ptr; /* last used entry (index) host_r*/
121 dma_addr_t dma_addr; /* physical addr for BD's */
122 int n_window; /* safe queue window */
123 u32 id;
124 int low_mark; /* low watermark, resume queue if free
125 * space more than this */
126 int high_mark; /* high watermark, stop queue if free
127 * space less than this */
128} __attribute__ ((packed));
129
130#define MAX_NUM_OF_TBS (20)
131
132struct iwl_tx_info {
133 struct ieee80211_tx_status status;
134 struct sk_buff *skb[MAX_NUM_OF_TBS];
135};
136
137/**
138 * struct iwl_tx_queue - Tx Queue for DMA
139 * @need_update: need to update read/write index
140 * @shed_retry: queue is HT AGG enabled
141 *
142 * Queue consists of circular buffer of BD's and required locking structures.
143 */
144struct iwl_tx_queue {
145 struct iwl_queue q;
146 struct iwl_tfd_frame *bd;
147 struct iwl_cmd *cmd;
148 dma_addr_t dma_addr_cmd;
149 struct iwl_tx_info *txb;
150 int need_update;
151 int sched_retry;
152 int active;
153};
154
155#define IWL_NUM_SCAN_RATES (2)
156
157struct iwl_channel_tgd_info {
158 u8 type;
159 s8 max_power;
160};
161
162struct iwl_channel_tgh_info {
163 s64 last_radar_time;
164};
165
166/* current Tx power values to use, one for each rate for each channel.
167 * requested power is limited by:
168 * -- regulatory EEPROM limits for this channel
169 * -- hardware capabilities (clip-powers)
170 * -- spectrum management
171 * -- user preference (e.g. iwconfig)
172 * when requested power is set, base power index must also be set. */
173struct iwl_channel_power_info {
174 struct iwl_tx_power tpc; /* actual radio and DSP gain settings */
175 s8 power_table_index; /* actual (compenst'd) index into gain table */
176 s8 base_power_index; /* gain index for power at factory temp. */
177 s8 requested_power; /* power (dBm) requested for this chnl/rate */
178};
179
180/* current scan Tx power values to use, one for each scan rate for each
181 * channel. */
182struct iwl_scan_power_info {
183 struct iwl_tx_power tpc; /* actual radio and DSP gain settings */
184 s8 power_table_index; /* actual (compenst'd) index into gain table */
185 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
186};
187
188/* Channel unlock period is 15 seconds. If no beacon or probe response
189 * has been received within 15 seconds on a locked channel then the channel
190 * remains locked. */
191#define TX_UNLOCK_PERIOD 15
192
193/* CSA lock period is 15 seconds. If a CSA has been received on a channel in
194 * the last 15 seconds, the channel is locked */
195#define CSA_LOCK_PERIOD 15
196/*
197 * One for each channel, holds all channel setup data
198 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
199 * with one another!
200 */
201#define IWL4965_MAX_RATE (33)
202
203struct iwl_channel_info {
204 struct iwl_channel_tgd_info tgd;
205 struct iwl_channel_tgh_info tgh;
206 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
207 struct iwl_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for
208 * FAT channel */
209
210 u8 channel; /* channel number */
211 u8 flags; /* flags copied from EEPROM */
212 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
213 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */
214 s8 min_power; /* always 0 */
215 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
216
217 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
218 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
219 u8 phymode; /* MODE_IEEE80211{A,B,G} */
220
221 /* Radio/DSP gain settings for each "normal" data Tx rate.
222 * These include, in addition to RF and DSP gain, a few fields for
223 * remembering/modifying gain settings (indexes). */
224 struct iwl_channel_power_info power_info[IWL4965_MAX_RATE];
225
226 /* FAT channel info */
227 s8 fat_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
228 s8 fat_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */
229 s8 fat_min_power; /* always 0 */
230 s8 fat_scan_power; /* (dBm) eeprom, direct scans, any rate */
231 u8 fat_flags; /* flags copied from EEPROM */
232 u8 fat_extension_channel;
233
234 /* Radio/DSP gain settings for each scan rate, for directed scans. */
235 struct iwl_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
236};
237
238struct iwl_clip_group {
239 /* maximum power level to prevent clipping for each rate, derived by
240 * us from this band's saturation power in EEPROM */
241 const s8 clip_powers[IWL_MAX_RATES];
242};
243
244#include "iwl-4965-rs.h"
245
246#define IWL_TX_FIFO_AC0 0
247#define IWL_TX_FIFO_AC1 1
248#define IWL_TX_FIFO_AC2 2
249#define IWL_TX_FIFO_AC3 3
250#define IWL_TX_FIFO_HCCA_1 5
251#define IWL_TX_FIFO_HCCA_2 6
252#define IWL_TX_FIFO_NONE 7
253
254/* Minimum number of queues. MAX_NUM is defined in hw specific files */
255#define IWL_MIN_NUM_QUEUES 4
256
257/* Power management (not Tx power) structures */
258
259struct iwl_power_vec_entry {
260 struct iwl_powertable_cmd cmd;
261 u8 no_dtim;
262};
263#define IWL_POWER_RANGE_0 (0)
264#define IWL_POWER_RANGE_1 (1)
265
266#define IWL_POWER_MODE_CAM 0x00 /* Continuously Aware Mode, always on */
267#define IWL_POWER_INDEX_3 0x03
268#define IWL_POWER_INDEX_5 0x05
269#define IWL_POWER_AC 0x06
270#define IWL_POWER_BATTERY 0x07
271#define IWL_POWER_LIMIT 0x07
272#define IWL_POWER_MASK 0x0F
273#define IWL_POWER_ENABLED 0x10
274#define IWL_POWER_LEVEL(x) ((x) & IWL_POWER_MASK)
275
276struct iwl_power_mgr {
277 spinlock_t lock;
278 struct iwl_power_vec_entry pwr_range_0[IWL_POWER_AC];
279 struct iwl_power_vec_entry pwr_range_1[IWL_POWER_AC];
280 u8 active_index;
281 u32 dtim_val;
282};
283
284#define IEEE80211_DATA_LEN 2304
285#define IEEE80211_4ADDR_LEN 30
286#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
287#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
288
289struct iwl_frame {
290 union {
291 struct ieee80211_hdr frame;
292 struct iwl_tx_beacon_cmd beacon;
293 u8 raw[IEEE80211_FRAME_LEN];
294 u8 cmd[360];
295 } u;
296 struct list_head list;
297};
298
299#define SEQ_TO_QUEUE(x) ((x >> 8) & 0xbf)
300#define QUEUE_TO_SEQ(x) ((x & 0xbf) << 8)
301#define SEQ_TO_INDEX(x) (x & 0xff)
302#define INDEX_TO_SEQ(x) (x & 0xff)
303#define SEQ_HUGE_FRAME (0x4000)
304#define SEQ_RX_FRAME __constant_cpu_to_le16(0x8000)
305#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
306#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
307#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
308
309enum {
310 /* CMD_SIZE_NORMAL = 0, */
311 CMD_SIZE_HUGE = (1 << 0),
312 /* CMD_SYNC = 0, */
313 CMD_ASYNC = (1 << 1),
314 /* CMD_NO_SKB = 0, */
315 CMD_WANT_SKB = (1 << 2),
316};
317
318struct iwl_cmd;
319struct iwl_priv;
320
321struct iwl_cmd_meta {
322 struct iwl_cmd_meta *source;
323 union {
324 struct sk_buff *skb;
325 int (*callback)(struct iwl_priv *priv,
326 struct iwl_cmd *cmd, struct sk_buff *skb);
327 } __attribute__ ((packed)) u;
328
329 /* The CMD_SIZE_HUGE flag bit indicates that the command
330 * structure is stored at the end of the shared queue memory. */
331 u32 flags;
332
333} __attribute__ ((packed));
334
335struct iwl_cmd {
336 struct iwl_cmd_meta meta;
337 struct iwl_cmd_header hdr;
338 union {
339 struct iwl_addsta_cmd addsta;
340 struct iwl_led_cmd led;
341 u32 flags;
342 u8 val8;
343 u16 val16;
344 u32 val32;
345 struct iwl_bt_cmd bt;
346 struct iwl_rxon_time_cmd rxon_time;
347 struct iwl_powertable_cmd powertable;
348 struct iwl_qosparam_cmd qosparam;
349 struct iwl_tx_cmd tx;
350 struct iwl_tx_beacon_cmd tx_beacon;
351 struct iwl_rxon_assoc_cmd rxon_assoc;
352 u8 *indirect;
353 u8 payload[360];
354 } __attribute__ ((packed)) cmd;
355} __attribute__ ((packed));
356
357struct iwl_host_cmd {
358 u8 id;
359 u16 len;
360 struct iwl_cmd_meta meta;
361 const void *data;
362};
363
364#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
365 sizeof(struct iwl_cmd_meta))
366
367/*
368 * RX related structures and functions
369 */
370#define RX_FREE_BUFFERS 64
371#define RX_LOW_WATERMARK 8
372
373#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
374#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
375#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
376
377/**
378 * struct iwl_rx_queue - Rx queue
379 * @processed: Internal index to last handled Rx packet
380 * @read: Shared index to newest available Rx buffer
381 * @write: Shared index to oldest written Rx packet
382 * @free_count: Number of pre-allocated buffers in rx_free
383 * @rx_free: list of free SKBs for use
384 * @rx_used: List of Rx buffers with no SKB
385 * @need_update: flag to indicate we need to update read/write index
386 *
387 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
388 */
389struct iwl_rx_queue {
390 __le32 *bd;
391 dma_addr_t dma_addr;
392 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
393 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
394 u32 processed;
395 u32 read;
396 u32 write;
397 u32 free_count;
398 struct list_head rx_free;
399 struct list_head rx_used;
400 int need_update;
401 spinlock_t lock;
402};
403
404#define IWL_SUPPORTED_RATES_IE_LEN 8
405
406#define SCAN_INTERVAL 100
407
408#define MAX_A_CHANNELS 252
409#define MIN_A_CHANNELS 7
410
411#define MAX_B_CHANNELS 14
412#define MIN_B_CHANNELS 1
413
414#define STATUS_HCMD_ACTIVE 0 /* host command in progress */
415#define STATUS_INT_ENABLED 1
416#define STATUS_RF_KILL_HW 2
417#define STATUS_RF_KILL_SW 3
418#define STATUS_INIT 4
419#define STATUS_ALIVE 5
420#define STATUS_READY 6
421#define STATUS_TEMPERATURE 7
422#define STATUS_GEO_CONFIGURED 8
423#define STATUS_EXIT_PENDING 9
424#define STATUS_IN_SUSPEND 10
425#define STATUS_STATISTICS 11
426#define STATUS_SCANNING 12
427#define STATUS_SCAN_ABORTING 13
428#define STATUS_SCAN_HW 14
429#define STATUS_POWER_PMI 15
430#define STATUS_FW_ERROR 16
431
432#define MAX_TID_COUNT 9
433
434#define IWL_INVALID_RATE 0xFF
435#define IWL_INVALID_VALUE -1
436
437#ifdef CONFIG_IWLWIFI_HT
438#ifdef CONFIG_IWLWIFI_HT_AGG
439struct iwl_ht_agg {
440 u16 txq_id;
441 u16 frame_count;
442 u16 wait_for_ba;
443 u16 start_idx;
444 u32 bitmap0;
445 u32 bitmap1;
446 u32 rate_n_flags;
447};
448#endif /* CONFIG_IWLWIFI_HT_AGG */
449#endif /* CONFIG_IWLWIFI_HT */
450
451struct iwl_tid_data {
452 u16 seq_number;
453#ifdef CONFIG_IWLWIFI_HT
454#ifdef CONFIG_IWLWIFI_HT_AGG
455 struct iwl_ht_agg agg;
456#endif /* CONFIG_IWLWIFI_HT_AGG */
457#endif /* CONFIG_IWLWIFI_HT */
458};
459
460struct iwl_hw_key {
461 enum ieee80211_key_alg alg;
462 int keylen;
463 u8 key[32];
464};
465
466union iwl_ht_rate_supp {
467 u16 rates;
468 struct {
469 u8 siso_rate;
470 u8 mimo_rate;
471 };
472};
473
474#ifdef CONFIG_IWLWIFI_HT
475#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
476#define HT_IE_MAX_AMSDU_SIZE_4K (0)
477#define CFG_HT_MPDU_DENSITY_2USEC (0x5)
478#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC
479
480struct sta_ht_info {
481 u8 is_ht;
482 u16 rx_mimo_ps_mode;
483 u16 tx_mimo_ps_mode;
484 u16 control_channel;
485 u8 max_amsdu_size;
486 u8 ampdu_factor;
487 u8 mpdu_density;
488 u8 operating_mode;
489 u8 supported_chan_width;
490 u8 extension_chan_offset;
491 u8 is_green_field;
492 u8 sgf;
493 u8 supp_rates[16];
494 u8 tx_chan_width;
495 u8 chan_width_cap;
496};
497#endif /*CONFIG_IWLWIFI_HT */
498
499#ifdef CONFIG_IWLWIFI_QOS
500
501union iwl_qos_capabity {
502 struct {
503 u8 edca_count:4; /* bit 0-3 */
504 u8 q_ack:1; /* bit 4 */
505 u8 queue_request:1; /* bit 5 */
506 u8 txop_request:1; /* bit 6 */
507 u8 reserved:1; /* bit 7 */
508 } q_AP;
509 struct {
510 u8 acvo_APSD:1; /* bit 0 */
511 u8 acvi_APSD:1; /* bit 1 */
512 u8 ac_bk_APSD:1; /* bit 2 */
513 u8 ac_be_APSD:1; /* bit 3 */
514 u8 q_ack:1; /* bit 4 */
515 u8 max_len:2; /* bit 5-6 */
516 u8 more_data_ack:1; /* bit 7 */
517 } q_STA;
518 u8 val;
519};
520
521/* QoS structures */
522struct iwl_qos_info {
523 int qos_enable;
524 int qos_active;
525 union iwl_qos_capabity qos_cap;
526 struct iwl_qosparam_cmd def_qos_parm;
527};
528#endif /*CONFIG_IWLWIFI_QOS */
529
530#define STA_PS_STATUS_WAKE 0
531#define STA_PS_STATUS_SLEEP 1
532
533struct iwl_station_entry {
534 struct iwl_addsta_cmd sta;
535 struct iwl_tid_data tid[MAX_TID_COUNT];
536 u8 used;
537 u8 ps_status;
538 struct iwl_hw_key keyinfo;
539};
540
541/* one for each uCode image (inst/data, boot/init/runtime) */
542struct fw_desc {
543 void *v_addr; /* access by driver */
544 dma_addr_t p_addr; /* access by card's busmaster DMA */
545 u32 len; /* bytes */
546};
547
548/* uCode file layout */
549struct iwl_ucode {
550 __le32 ver; /* major/minor/subminor */
551 __le32 inst_size; /* bytes of runtime instructions */
552 __le32 data_size; /* bytes of runtime data */
553 __le32 init_size; /* bytes of initialization instructions */
554 __le32 init_data_size; /* bytes of initialization data */
555 __le32 boot_size; /* bytes of bootstrap instructions */
556 u8 data[0]; /* data in same order as "size" elements */
557};
558
559#define IWL_IBSS_MAC_HASH_SIZE 32
560
561struct iwl_ibss_seq {
562 u8 mac[ETH_ALEN];
563 u16 seq_num;
564 u16 frag_num;
565 unsigned long packet_time;
566 struct list_head list;
567};
568
569struct iwl_driver_hw_info {
570 u16 max_txq_num;
571 u16 ac_queue_count;
572 u16 tx_cmd_len;
573 u16 max_rxq_size;
574 u32 rx_buffer_size;
575 u16 max_rxq_log;
576 u8 max_stations;
577 u8 bcast_sta_id;
578 void *shared_virt;
579 dma_addr_t shared_phys;
580};
581
582
583#define STA_FLG_RTS_MIMO_PROT_MSK __constant_cpu_to_le32(1 << 17)
584#define STA_FLG_AGG_MPDU_8US_MSK __constant_cpu_to_le32(1 << 18)
585#define STA_FLG_MAX_AGG_SIZE_POS (19)
586#define STA_FLG_MAX_AGG_SIZE_MSK __constant_cpu_to_le32(3 << 19)
587#define STA_FLG_FAT_EN_MSK __constant_cpu_to_le32(1 << 21)
588#define STA_FLG_MIMO_DIS_MSK __constant_cpu_to_le32(1 << 22)
589#define STA_FLG_AGG_MPDU_DENSITY_POS (23)
590#define STA_FLG_AGG_MPDU_DENSITY_MSK __constant_cpu_to_le32(7 << 23)
591#define HT_SHORT_GI_20MHZ_ONLY (1 << 0)
592#define HT_SHORT_GI_40MHZ_ONLY (1 << 1)
593
594
595#define IWL_RX_HDR(x) ((struct iwl_rx_frame_hdr *)(\
596 x->u.rx_frame.stats.payload + \
597 x->u.rx_frame.stats.phy_count))
598#define IWL_RX_END(x) ((struct iwl_rx_frame_end *)(\
599 IWL_RX_HDR(x)->payload + \
600 le16_to_cpu(IWL_RX_HDR(x)->len)))
601#define IWL_RX_STATS(x) (&x->u.rx_frame.stats)
602#define IWL_RX_DATA(x) (IWL_RX_HDR(x)->payload)
603
604
605/******************************************************************************
606 *
607 * Functions implemented in iwl-base.c which are forward declared here
608 * for use by iwl-*.c
609 *
610 *****************************************************************************/
611struct iwl_addsta_cmd;
612extern int iwl_send_add_station(struct iwl_priv *priv,
613 struct iwl_addsta_cmd *sta, u8 flags);
614extern u8 iwl_add_station(struct iwl_priv *priv, const u8 *bssid,
615 int is_ap, u8 flags);
616extern int iwl_is_network_packet(struct iwl_priv *priv,
617 struct ieee80211_hdr *header);
618extern int iwl_power_init_handle(struct iwl_priv *priv);
619extern int iwl_eeprom_init(struct iwl_priv *priv);
620#ifdef CONFIG_IWLWIFI_DEBUG
621extern void iwl_report_frame(struct iwl_priv *priv,
622 struct iwl_rx_packet *pkt,
623 struct ieee80211_hdr *header, int group100);
624#else
625static inline void iwl_report_frame(struct iwl_priv *priv,
626 struct iwl_rx_packet *pkt,
627 struct ieee80211_hdr *header,
628 int group100) {}
629#endif
630extern void iwl_handle_data_packet_monitor(struct iwl_priv *priv,
631 struct iwl_rx_mem_buffer *rxb,
632 void *data, short len,
633 struct ieee80211_rx_status *stats,
634 u16 phy_flags);
635extern int is_duplicate_packet(struct iwl_priv *priv, struct ieee80211_hdr
636 *header);
637extern int iwl_rx_queue_alloc(struct iwl_priv *priv);
638extern void iwl_rx_queue_reset(struct iwl_priv *priv,
639 struct iwl_rx_queue *rxq);
640extern int iwl_calc_db_from_ratio(int sig_ratio);
641extern int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm);
642extern int iwl_tx_queue_init(struct iwl_priv *priv,
643 struct iwl_tx_queue *txq, int count, u32 id);
644extern void iwl_rx_replenish(void *data);
645extern void iwl_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq);
646extern int iwl_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len,
647 const void *data);
648extern int __must_check iwl_send_cmd(struct iwl_priv *priv,
649 struct iwl_host_cmd *cmd);
650extern unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
651 struct ieee80211_hdr *hdr,
652 const u8 *dest, int left);
653extern int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
654 struct iwl_rx_queue *q);
655extern int iwl_send_statistics_request(struct iwl_priv *priv);
656extern void iwl_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
657 u32 decrypt_res,
658 struct ieee80211_rx_status *stats);
659extern __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr);
660
661extern const u8 BROADCAST_ADDR[ETH_ALEN];
662
663/*
664 * Currently used by iwl-3945-rs... look at restructuring so that it doesn't
665 * call this... todo... fix that.
666*/
667extern u8 iwl_sync_station(struct iwl_priv *priv, int sta_id,
668 u16 tx_rate, u8 flags);
669
670/******************************************************************************
671 *
672 * Functions implemented in iwl-[34]*.c which are forward declared here
673 * for use by iwl-base.c
674 *
675 * NOTE: The implementation of these functions are hardware specific
676 * which is why they are in the hardware specific files (vs. iwl-base.c)
677 *
678 * Naming convention --
679 * iwl_ <-- Its part of iwlwifi (should be changed to iwl_)
680 * iwl_hw_ <-- Hardware specific (implemented in iwl-XXXX.c by all HW)
681 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
682 * iwl_bg_ <-- Called from work queue context
683 * iwl_mac_ <-- mac80211 callback
684 *
685 ****************************************************************************/
686extern void iwl_hw_rx_handler_setup(struct iwl_priv *priv);
687extern void iwl_hw_setup_deferred_work(struct iwl_priv *priv);
688extern void iwl_hw_cancel_deferred_work(struct iwl_priv *priv);
689extern int iwl_hw_rxq_stop(struct iwl_priv *priv);
690extern int iwl_hw_set_hw_setting(struct iwl_priv *priv);
691extern int iwl_hw_nic_init(struct iwl_priv *priv);
692extern int iwl_hw_nic_stop_master(struct iwl_priv *priv);
693extern void iwl_hw_txq_ctx_free(struct iwl_priv *priv);
694extern void iwl_hw_txq_ctx_stop(struct iwl_priv *priv);
695extern int iwl_hw_nic_reset(struct iwl_priv *priv);
696extern int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *tfd,
697 dma_addr_t addr, u16 len);
698extern int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq);
699extern int iwl_hw_get_temperature(struct iwl_priv *priv);
700extern int iwl_hw_tx_queue_init(struct iwl_priv *priv,
701 struct iwl_tx_queue *txq);
702extern unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
703 struct iwl_frame *frame, u8 rate);
704extern int iwl_hw_get_rx_read(struct iwl_priv *priv);
705extern void iwl_hw_build_tx_cmd_rate(struct iwl_priv *priv,
706 struct iwl_cmd *cmd,
707 struct ieee80211_tx_control *ctrl,
708 struct ieee80211_hdr *hdr,
709 int sta_id, int tx_id);
710extern int iwl_hw_reg_send_txpower(struct iwl_priv *priv);
711extern int iwl_hw_reg_set_txpower(struct iwl_priv *priv, s8 power);
712extern void iwl_hw_rx_statistics(struct iwl_priv *priv,
713 struct iwl_rx_mem_buffer *rxb);
714extern void iwl_disable_events(struct iwl_priv *priv);
715extern int iwl4965_get_temperature(const struct iwl_priv *priv);
716
717/**
718 * iwl_hw_find_station - Find station id for a given BSSID
719 * @bssid: MAC address of station ID to find
720 *
721 * NOTE: This should not be hardware specific but the code has
722 * not yet been merged into a single common layer for managing the
723 * station tables.
724 */
725extern u8 iwl_hw_find_station(struct iwl_priv *priv, const u8 *bssid);
726
727extern int iwl_hw_channel_switch(struct iwl_priv *priv, u16 channel);
728extern int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index);
729
29struct iwl_priv; 730struct iwl_priv;
30struct sta_ht_info; 731struct sta_ht_info;
31 732
@@ -338,4 +1039,322 @@ struct iwl_chain_noise_data {
338#define EEPROM_SEM_TIMEOUT 10 1039#define EEPROM_SEM_TIMEOUT 10
339#define EEPROM_SEM_RETRY_LIMIT 1000 1040#define EEPROM_SEM_RETRY_LIMIT 1000
340 1041
1042
1043#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
1044
1045enum {
1046 MEASUREMENT_READY = (1 << 0),
1047 MEASUREMENT_ACTIVE = (1 << 1),
1048};
1049
1050#endif
1051
1052struct iwl_priv {
1053
1054 /* ieee device used by generic ieee processing code */
1055 struct ieee80211_hw *hw;
1056 struct ieee80211_channel *ieee_channels;
1057 struct ieee80211_rate *ieee_rates;
1058
1059 /* temporary frame storage list */
1060 struct list_head free_frames;
1061 int frames_count;
1062
1063 u8 phymode;
1064 int alloc_rxb_skb;
1065
1066 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
1067 struct iwl_rx_mem_buffer *rxb);
1068
1069 const struct ieee80211_hw_mode *modes;
1070
1071#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
1072 /* spectrum measurement report caching */
1073 struct iwl_spectrum_notification measure_report;
1074 u8 measurement_status;
1075#endif
1076 /* ucode beacon time */
1077 u32 ucode_beacon_time;
1078
1079 /* we allocate array of iwl_channel_info for NIC's valid channels.
1080 * Access via channel # using indirect index array */
1081 struct iwl_channel_info *channel_info; /* channel info array */
1082 u8 channel_count; /* # of channels */
1083
1084 /* each calibration channel group in the EEPROM has a derived
1085 * clip setting for each rate. */
1086 const struct iwl_clip_group clip_groups[5];
1087
1088 /* thermal calibration */
1089 s32 temperature; /* degrees Kelvin */
1090 s32 last_temperature;
1091
1092 /* Scan related variables */
1093 unsigned long last_scan_jiffies;
1094 unsigned long scan_start;
1095 unsigned long scan_pass_start;
1096 unsigned long scan_start_tsf;
1097 int scan_bands;
1098 int one_direct_scan;
1099 u8 direct_ssid_len;
1100 u8 direct_ssid[IW_ESSID_MAX_SIZE];
1101 struct iwl_scan_cmd *scan;
1102 u8 only_active_channel;
1103
1104 /* spinlock */
1105 spinlock_t lock; /* protect general shared data */
1106 spinlock_t hcmd_lock; /* protect hcmd */
1107 struct mutex mutex;
1108
1109 /* basic pci-network driver stuff */
1110 struct pci_dev *pci_dev;
1111
1112 /* pci hardware address support */
1113 void __iomem *hw_base;
1114
1115 /* uCode images, save to reload in case of failure */
1116 struct fw_desc ucode_code; /* runtime inst */
1117 struct fw_desc ucode_data; /* runtime data original */
1118 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1119 struct fw_desc ucode_init; /* initialization inst */
1120 struct fw_desc ucode_init_data; /* initialization data */
1121 struct fw_desc ucode_boot; /* bootstrap inst */
1122
1123
1124 struct iwl_rxon_time_cmd rxon_timing;
1125
1126 /* We declare this const so it can only be
1127 * changed via explicit cast within the
1128 * routines that actually update the physical
1129 * hardware */
1130 const struct iwl_rxon_cmd active_rxon;
1131 struct iwl_rxon_cmd staging_rxon;
1132
1133 int error_recovering;
1134 struct iwl_rxon_cmd recovery_rxon;
1135
1136 /* 1st responses from initialize and runtime uCode images.
1137 * 4965's initialize alive response contains some calibration data. */
1138 struct iwl_init_alive_resp card_alive_init;
1139 struct iwl_alive_resp card_alive;
1140
1141#ifdef LED
1142 /* LED related variables */
1143 struct iwl_activity_blink activity;
1144 unsigned long led_packets;
1145 int led_state;
1146#endif
1147
1148 u16 active_rate;
1149 u16 active_rate_basic;
1150
1151 u8 call_post_assoc_from_beacon;
1152 u8 assoc_station_added;
1153 u8 use_ant_b_for_management_frame; /* Tx antenna selection */
1154 /* HT variables */
1155 u8 is_dup;
1156 u8 is_ht_enabled;
1157 u8 channel_width; /* 0=20MHZ, 1=40MHZ */
1158 u8 current_channel_width;
1159 u8 valid_antenna; /* Bit mask of antennas actually connected */
1160#ifdef CONFIG_IWLWIFI_SENSITIVITY
1161 struct iwl_sensitivity_data sensitivity_data;
1162 struct iwl_chain_noise_data chain_noise_data;
1163 u8 start_calib;
1164 __le16 sensitivity_tbl[HD_TABLE_SIZE];
1165#endif /*CONFIG_IWLWIFI_SENSITIVITY*/
1166
1167#ifdef CONFIG_IWLWIFI_HT
1168 struct sta_ht_info current_assoc_ht;
1169#endif
1170 u8 active_rate_ht[2];
1171 u8 last_phy_res[100];
1172
1173 /* Rate scaling data */
1174 struct iwl_lq_mngr lq_mngr;
1175
1176 /* Rate scaling data */
1177 s8 data_retry_limit;
1178 u8 retry_rate;
1179
1180 wait_queue_head_t wait_command_queue;
1181
1182 int activity_timer_active;
1183
1184 /* Rx and Tx DMA processing queues */
1185 struct iwl_rx_queue rxq;
1186 struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES];
1187 unsigned long txq_ctx_active_msk;
1188 struct iwl_kw kw; /* keep warm address */
1189 u32 scd_base_addr; /* scheduler sram base address */
1190
1191 unsigned long status;
1192 u32 config;
1193
1194 int last_rx_rssi; /* From Rx packet statisitics */
1195 int last_rx_noise; /* From beacon statistics */
1196
1197 struct iwl_power_mgr power_data;
1198
1199 struct iwl_notif_statistics statistics;
1200 unsigned long last_statistics_time;
1201
1202 /* context information */
1203 u8 essid[IW_ESSID_MAX_SIZE];
1204 u8 essid_len;
1205 u16 rates_mask;
1206
1207 u32 power_mode;
1208 u32 antenna;
1209 u8 bssid[ETH_ALEN];
1210 u16 rts_threshold;
1211 u8 mac_addr[ETH_ALEN];
1212
1213 /*station table variables */
1214 spinlock_t sta_lock;
1215 int num_stations;
1216 struct iwl_station_entry stations[IWL_STATION_COUNT];
1217
1218 /* Indication if ieee80211_ops->open has been called */
1219 int is_open;
1220
1221 u8 mac80211_registered;
1222 int is_abg;
1223
1224 u32 notif_missed_beacons;
1225
1226 /* Rx'd packet timing information */
1227 u32 last_beacon_time;
1228 u64 last_tsf;
1229
1230 /* Duplicate packet detection */
1231 u16 last_seq_num;
1232 u16 last_frag_num;
1233 unsigned long last_packet_time;
1234 struct list_head ibss_mac_hash[IWL_IBSS_MAC_HASH_SIZE];
1235
1236 /* eeprom */
1237 struct iwl_eeprom eeprom;
1238
1239 int iw_mode;
1240
1241 struct sk_buff *ibss_beacon;
1242
1243 /* Last Rx'd beacon timestamp */
1244 u32 timestamp0;
1245 u32 timestamp1;
1246 u16 beacon_int;
1247 struct iwl_driver_hw_info hw_setting;
1248 int interface_id;
1249
1250 /* Current association information needed to configure the
1251 * hardware */
1252 u16 assoc_id;
1253 u16 assoc_capability;
1254 u8 ps_mode;
1255
1256#ifdef CONFIG_IWLWIFI_QOS
1257 struct iwl_qos_info qos_data;
1258#endif /*CONFIG_IWLWIFI_QOS */
1259
1260 struct workqueue_struct *workqueue;
1261
1262 struct work_struct up;
1263 struct work_struct restart;
1264 struct work_struct calibrated_work;
1265 struct work_struct scan_completed;
1266 struct work_struct rx_replenish;
1267 struct work_struct rf_kill;
1268 struct work_struct abort_scan;
1269 struct work_struct update_link_led;
1270 struct work_struct auth_work;
1271 struct work_struct report_work;
1272 struct work_struct request_scan;
1273 struct work_struct beacon_update;
1274
1275 struct tasklet_struct irq_tasklet;
1276
1277 struct delayed_work init_alive_start;
1278 struct delayed_work alive_start;
1279 struct delayed_work activity_timer;
1280 struct delayed_work thermal_periodic;
1281 struct delayed_work gather_stats;
1282 struct delayed_work scan_check;
1283 struct delayed_work post_associate;
1284
1285#define IWL_DEFAULT_TX_POWER 0x0F
1286 s8 user_txpower_limit;
1287 s8 max_channel_txpower_limit;
1288
1289#ifdef CONFIG_PM
1290 u32 pm_state[16];
1291#endif
1292
1293#ifdef CONFIG_IWLWIFI_DEBUG
1294 /* debugging info */
1295 u32 framecnt_to_us;
1296 atomic_t restrict_refcnt;
1297#endif
1298
1299 struct work_struct txpower_work;
1300#ifdef CONFIG_IWLWIFI_SENSITIVITY
1301 struct work_struct sensitivity_work;
1302#endif
1303 struct work_struct statistics_work;
1304 struct timer_list statistics_periodic;
1305
1306#ifdef CONFIG_IWLWIFI_HT_AGG
1307 struct work_struct agg_work;
1308#endif
1309}; /*iwl_priv */
1310
1311static inline int iwl_is_associated(struct iwl_priv *priv)
1312{
1313 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1314}
1315
1316static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
1317{
1318 if (ch_info == NULL)
1319 return 0;
1320 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1321}
1322
1323static inline int is_channel_narrow(const struct iwl_channel_info *ch_info)
1324{
1325 return (ch_info->flags & EEPROM_CHANNEL_NARROW) ? 1 : 0;
1326}
1327
1328static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
1329{
1330 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1331}
1332
1333static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
1334{
1335 return ch_info->phymode == MODE_IEEE80211A;
1336}
1337
1338static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
1339{
1340 return ((ch_info->phymode == MODE_IEEE80211B) ||
1341 (ch_info->phymode == MODE_IEEE80211G));
1342}
1343
1344static inline int is_channel_passive(const struct iwl_channel_info *ch)
1345{
1346 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1347}
1348
1349static inline int is_channel_ibss(const struct iwl_channel_info *ch)
1350{
1351 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1352}
1353
1354extern const struct iwl_channel_info *iwl_get_channel_info(
1355 const struct iwl_priv *priv, int phymode, u16 channel);
1356
1357/* Requires full declaration of iwl_priv before including */
1358#include "iwl-4965-io.h"
1359
341#endif /* __iwl_4965_h__ */ 1360#endif /* __iwl_4965_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-channel.h b/drivers/net/wireless/iwlwifi/iwl-channel.h
deleted file mode 100644
index 023c3f240cea..000000000000
--- a/drivers/net/wireless/iwlwifi/iwl-channel.h
+++ /dev/null
@@ -1,161 +0,0 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26#ifndef __iwl_channel_h__
27#define __iwl_channel_h__
28
29#define IWL_NUM_SCAN_RATES (2)
30
31struct iwl_channel_tgd_info {
32 u8 type;
33 s8 max_power;
34};
35
36struct iwl_channel_tgh_info {
37 s64 last_radar_time;
38};
39
40/* current Tx power values to use, one for each rate for each channel.
41 * requested power is limited by:
42 * -- regulatory EEPROM limits for this channel
43 * -- hardware capabilities (clip-powers)
44 * -- spectrum management
45 * -- user preference (e.g. iwconfig)
46 * when requested power is set, base power index must also be set. */
47struct iwl_channel_power_info {
48 struct iwl_tx_power tpc; /* actual radio and DSP gain settings */
49 s8 power_table_index; /* actual (compenst'd) index into gain table */
50 s8 base_power_index; /* gain index for power at factory temp. */
51 s8 requested_power; /* power (dBm) requested for this chnl/rate */
52};
53
54/* current scan Tx power values to use, one for each scan rate for each
55 * channel. */
56struct iwl_scan_power_info {
57 struct iwl_tx_power tpc; /* actual radio and DSP gain settings */
58 s8 power_table_index; /* actual (compenst'd) index into gain table */
59 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
60};
61
62/* Channel unlock period is 15 seconds. If no beacon or probe response
63 * has been received within 15 seconds on a locked channel then the channel
64 * remains locked. */
65#define TX_UNLOCK_PERIOD 15
66
67/* CSA lock period is 15 seconds. If a CSA has been received on a channel in
68 * the last 15 seconds, the channel is locked */
69#define CSA_LOCK_PERIOD 15
70/*
71 * One for each channel, holds all channel setup data
72 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
73 * with one another!
74 */
75#define IWL4965_MAX_RATE (33)
76
77struct iwl_channel_info {
78 struct iwl_channel_tgd_info tgd;
79 struct iwl_channel_tgh_info tgh;
80 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
81 struct iwl_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for
82 * FAT channel */
83
84 u8 channel; /* channel number */
85 u8 flags; /* flags copied from EEPROM */
86 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
87 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */
88 s8 min_power; /* always 0 */
89 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
90
91 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
92 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
93 u8 phymode; /* MODE_IEEE80211{A,B,G} */
94
95 /* Radio/DSP gain settings for each "normal" data Tx rate.
96 * These include, in addition to RF and DSP gain, a few fields for
97 * remembering/modifying gain settings (indexes). */
98 struct iwl_channel_power_info power_info[IWL4965_MAX_RATE];
99
100#if IWL == 4965
101 /* FAT channel info */
102 s8 fat_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
103 s8 fat_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */
104 s8 fat_min_power; /* always 0 */
105 s8 fat_scan_power; /* (dBm) eeprom, direct scans, any rate */
106 u8 fat_flags; /* flags copied from EEPROM */
107 u8 fat_extension_channel;
108#endif
109
110 /* Radio/DSP gain settings for each scan rate, for directed scans. */
111 struct iwl_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
112};
113
114struct iwl_clip_group {
115 /* maximum power level to prevent clipping for each rate, derived by
116 * us from this band's saturation power in EEPROM */
117 const s8 clip_powers[IWL_MAX_RATES];
118};
119
120static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
121{
122 if (ch_info == NULL)
123 return 0;
124 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
125}
126
127static inline int is_channel_narrow(const struct iwl_channel_info *ch_info)
128{
129 return (ch_info->flags & EEPROM_CHANNEL_NARROW) ? 1 : 0;
130}
131
132static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
133{
134 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
135}
136
137static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
138{
139 return ch_info->phymode == MODE_IEEE80211A;
140}
141
142static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
143{
144 return ((ch_info->phymode == MODE_IEEE80211B) ||
145 (ch_info->phymode == MODE_IEEE80211G));
146}
147
148static inline int is_channel_passive(const struct iwl_channel_info *ch)
149{
150 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
151}
152
153static inline int is_channel_ibss(const struct iwl_channel_info *ch)
154{
155 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
156}
157
158extern const struct iwl_channel_info *iwl_get_channel_info(
159 const struct iwl_priv *priv, int phymode, u16 channel);
160
161#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.h b/drivers/net/wireless/iwlwifi/iwl-eeprom.h
deleted file mode 100644
index 22cbe278add1..000000000000
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.h
+++ /dev/null
@@ -1,336 +0,0 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63
64#ifndef __iwl_eeprom_h__
65#define __iwl_eeprom_h__
66
67/*
68 * This file defines EEPROM related constants, enums, and inline functions.
69 *
70 */
71
72#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
73#define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */
74/* EEPROM field values */
75#define ANTENNA_SWITCH_NORMAL 0
76#define ANTENNA_SWITCH_INVERSE 1
77
78enum {
79 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
80 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
81 /* Bit 2 Reserved */
82 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
83 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
84 EEPROM_CHANNEL_WIDE = (1 << 5),
85 EEPROM_CHANNEL_NARROW = (1 << 6),
86 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
87};
88
89/* EEPROM field lengths */
90#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
91
92/* EEPROM field lengths */
93#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
94#define EEPROM_REGULATORY_SKU_ID_LENGTH 4
95#define EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH 14
96#define EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH 13
97#define EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH 12
98#define EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH 11
99#define EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH 6
100
101#if IWL == 3945
102#define EEPROM_REGULATORY_CHANNELS_LENGTH ( \
103 EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH + \
104 EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH + \
105 EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH + \
106 EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH + \
107 EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH)
108#elif IWL == 4965
109#define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS_LENGTH 7
110#define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS_LENGTH 11
111#define EEPROM_REGULATORY_CHANNELS_LENGTH ( \
112 EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH + \
113 EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH + \
114 EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH + \
115 EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH + \
116 EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH + \
117 EEPROM_REGULATORY_BAND_24_FAT_CHANNELS_LENGTH + \
118 EEPROM_REGULATORY_BAND_52_FAT_CHANNELS_LENGTH)
119#endif
120
121#define EEPROM_REGULATORY_NUMBER_OF_BANDS 5
122
123/* SKU Capabilities */
124#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
125#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
126#define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7)
127
128/* *regulatory* channel data from eeprom, one for each channel */
129struct iwl_eeprom_channel {
130 u8 flags; /* flags copied from EEPROM */
131 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
132} __attribute__ ((packed));
133
134/*
135 * Mapping of a Tx power level, at factory calibration temperature,
136 * to a radio/DSP gain table index.
137 * One for each of 5 "sample" power levels in each band.
138 * v_det is measured at the factory, using the 3945's built-in power amplifier
139 * (PA) output voltage detector. This same detector is used during Tx of
140 * long packets in normal operation to provide feedback as to proper output
141 * level.
142 * Data copied from EEPROM.
143 */
144struct iwl_eeprom_txpower_sample {
145 u8 gain_index; /* index into power (gain) setup table ... */
146 s8 power; /* ... for this pwr level for this chnl group */
147 u16 v_det; /* PA output voltage */
148} __attribute__ ((packed));
149
150/*
151 * Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
152 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
153 * Tx power setup code interpolates between the 5 "sample" power levels
154 * to determine the nominal setup for a requested power level.
155 * Data copied from EEPROM.
156 * DO NOT ALTER THIS STRUCTURE!!!
157 */
158struct iwl_eeprom_txpower_group {
159 struct iwl_eeprom_txpower_sample samples[5]; /* 5 power levels */
160 s32 a, b, c, d, e; /* coefficients for voltage->power
161 * formula (signed) */
162 s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
163 * frequency (signed) */
164 s8 saturation_power; /* highest power possible by h/w in this
165 * band */
166 u8 group_channel; /* "representative" channel # in this band */
167 s16 temperature; /* h/w temperature at factory calib this band
168 * (signed) */
169} __attribute__ ((packed));
170
171/*
172 * Temperature-based Tx-power compensation data, not band-specific.
173 * These coefficients are use to modify a/b/c/d/e coeffs based on
174 * difference between current temperature and factory calib temperature.
175 * Data copied from EEPROM.
176 */
177struct iwl_eeprom_temperature_corr {
178 u32 Ta;
179 u32 Tb;
180 u32 Tc;
181 u32 Td;
182 u32 Te;
183} __attribute__ ((packed));
184
185#if IWL == 4965
186#define EEPROM_TX_POWER_TX_CHAINS (2)
187#define EEPROM_TX_POWER_BANDS (8)
188#define EEPROM_TX_POWER_MEASUREMENTS (3)
189#define EEPROM_TX_POWER_VERSION (2)
190#define EEPROM_TX_POWER_VERSION_NEW (5)
191
192struct iwl_eeprom_calib_measure {
193 u8 temperature;
194 u8 gain_idx;
195 u8 actual_pow;
196 s8 pa_det;
197} __attribute__ ((packed));
198
199struct iwl_eeprom_calib_ch_info {
200 u8 ch_num;
201 struct iwl_eeprom_calib_measure measurements[EEPROM_TX_POWER_TX_CHAINS]
202 [EEPROM_TX_POWER_MEASUREMENTS];
203} __attribute__ ((packed));
204
205struct iwl_eeprom_calib_subband_info {
206 u8 ch_from;
207 u8 ch_to;
208 struct iwl_eeprom_calib_ch_info ch1;
209 struct iwl_eeprom_calib_ch_info ch2;
210} __attribute__ ((packed));
211
212struct iwl_eeprom_calib_info {
213 u8 saturation_power24;
214 u8 saturation_power52;
215 s16 voltage; /* signed */
216 struct iwl_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
217} __attribute__ ((packed));
218
219#endif
220
221struct iwl_eeprom {
222 u8 reserved0[16];
223#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
224 u16 device_id; /* abs.ofs: 16 */
225 u8 reserved1[2];
226#define EEPROM_PMC (2*0x0A) /* 2 bytes */
227 u16 pmc; /* abs.ofs: 20 */
228 u8 reserved2[20];
229#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
230 u8 mac_address[6]; /* abs.ofs: 42 */
231 u8 reserved3[58];
232#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
233 u16 board_revision; /* abs.ofs: 106 */
234 u8 reserved4[11];
235#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
236 u8 board_pba_number[9]; /* abs.ofs: 119 */
237 u8 reserved5[8];
238#define EEPROM_VERSION (2*0x44) /* 2 bytes */
239 u16 version; /* abs.ofs: 136 */
240#define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */
241 u8 sku_cap; /* abs.ofs: 138 */
242#define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */
243 u8 leds_mode; /* abs.ofs: 139 */
244#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
245 u16 oem_mode;
246#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
247 u16 wowlan_mode; /* abs.ofs: 142 */
248#define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */
249 u16 leds_time_interval; /* abs.ofs: 144 */
250#define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */
251 u8 leds_off_time; /* abs.ofs: 146 */
252#define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */
253 u8 leds_on_time; /* abs.ofs: 147 */
254#define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */
255 u8 almgor_m_version; /* abs.ofs: 148 */
256#define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */
257 u8 antenna_switch_type; /* abs.ofs: 149 */
258#if IWL == 3945
259 u8 reserved6[42];
260#else
261 u8 reserved6[8];
262#define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
263 u16 board_revision_4965; /* abs.ofs: 158 */
264 u8 reserved7[13];
265#define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
266 u8 board_pba_number_4965[9]; /* abs.ofs: 173 */
267 u8 reserved8[10];
268#endif
269#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
270 u8 sku_id[4]; /* abs.ofs: 192 */
271#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
272 u16 band_1_count; /* abs.ofs: 196 */
273#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
274 struct iwl_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */
275#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
276 u16 band_2_count; /* abs.ofs: 226 */
277#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
278 struct iwl_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */
279#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
280 u16 band_3_count; /* abs.ofs: 254 */
281#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
282 struct iwl_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */
283#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
284 u16 band_4_count; /* abs.ofs: 280 */
285#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
286 struct iwl_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */
287#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
288 u16 band_5_count; /* abs.ofs: 304 */
289#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
290 struct iwl_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */
291
292/* From here on out the EEPROM diverges between the 4965 and the 3945 */
293#if IWL == 3945
294
295 u8 reserved9[194];
296
297#define EEPROM_TXPOWER_CALIB_GROUP0 0x200
298#define EEPROM_TXPOWER_CALIB_GROUP1 0x240
299#define EEPROM_TXPOWER_CALIB_GROUP2 0x280
300#define EEPROM_TXPOWER_CALIB_GROUP3 0x2c0
301#define EEPROM_TXPOWER_CALIB_GROUP4 0x300
302#define IWL_NUM_TX_CALIB_GROUPS 5
303 struct iwl_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS];
304/* abs.ofs: 512 */
305#define EEPROM_CALIB_TEMPERATURE_CORRECT 0x340
306 struct iwl_eeprom_temperature_corr corrections; /* abs.ofs: 832 */
307 u8 reserved16[172]; /* fill out to full 1024 byte block */
308
309/* 4965AGN adds fat channel support */
310#elif IWL == 4965
311
312 u8 reserved10[2];
313#define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS (2*0xA0) /* 14 bytes */
314 struct iwl_eeprom_channel band_24_channels[7]; /* abs.ofs: 320 */
315 u8 reserved11[2];
316#define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS (2*0xA8) /* 22 bytes */
317 struct iwl_eeprom_channel band_52_channels[11]; /* abs.ofs: 336 */
318 u8 reserved12[6];
319#define EEPROM_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
320 u16 calib_version; /* abs.ofs: 364 */
321 u8 reserved13[2];
322#define EEPROM_SATURATION_POWER_OFFSET (2*0xB8) /* 2 bytes */
323 u16 satruation_power; /* abs.ofs: 368 */
324 u8 reserved14[94];
325#define EEPROM_IWL_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
326 struct iwl_eeprom_calib_info calib_info; /* abs.ofs: 464 */
327
328 u8 reserved16[140]; /* fill out to full 1024 byte block */
329
330#endif
331
332} __attribute__ ((packed));
333
334#define IWL_EEPROM_IMAGE_SIZE 1024
335
336#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-hw.h b/drivers/net/wireless/iwlwifi/iwl-hw.h
deleted file mode 100644
index 8968a95352d9..000000000000
--- a/drivers/net/wireless/iwlwifi/iwl-hw.h
+++ /dev/null
@@ -1,537 +0,0 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
62
63#ifndef __iwlwifi_hw_h__
64#define __iwlwifi_hw_h__
65
66/*
67 * This file defines hardware constants common to 3945 and 4965.
68 *
69 * Device-specific constants are defined in iwl-3945-hw.h and iwl-4965-hw.h,
70 * although this file contains a few definitions for which the .c
71 * implementation is the same for 3945 and 4965, except for the value of
72 * a constant.
73 *
74 * uCode API constants are defined in iwl-commands.h.
75 *
76 * NOTE: DO NOT PUT OS IMPLEMENTATION-SPECIFIC DECLARATIONS HERE
77 *
78 * The iwl-*hw.h (and files they include) files should remain OS/driver
79 * implementation independent, declaring only the hardware interface.
80 */
81
82/* uCode queue management definitions */
83#define IWL_CMD_QUEUE_NUM 4
84#define IWL_CMD_FIFO_NUM 4
85#define IWL_BACK_QUEUE_FIRST_ID 7
86
87/* Tx rates */
88#define IWL_CCK_RATES 4
89#define IWL_OFDM_RATES 8
90
91#if IWL == 3945
92#define IWL_HT_RATES 0
93#elif IWL == 4965
94#define IWL_HT_RATES 16
95#endif
96
97#define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
98
99/* Time constants */
100#define SHORT_SLOT_TIME 9
101#define LONG_SLOT_TIME 20
102
103/* RSSI to dBm */
104#if IWL == 3945
105#define IWL_RSSI_OFFSET 95
106#elif IWL == 4965
107#define IWL_RSSI_OFFSET 44
108#endif
109
110#include "iwl-eeprom.h"
111#include "iwl-commands.h"
112
113#define PCI_LINK_CTRL 0x0F0
114#define PCI_POWER_SOURCE 0x0C8
115#define PCI_REG_WUM8 0x0E8
116#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
117
118/*=== CSR (control and status registers) ===*/
119#define CSR_BASE (0x000)
120
121#define CSR_SW_VER (CSR_BASE+0x000)
122#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
123#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
124#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
125#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
126#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
127#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
128#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
129#define CSR_GP_CNTRL (CSR_BASE+0x024)
130#define CSR_HW_REV (CSR_BASE+0x028)
131#define CSR_EEPROM_REG (CSR_BASE+0x02c)
132#define CSR_EEPROM_GP (CSR_BASE+0x030)
133#define CSR_GP_UCODE (CSR_BASE+0x044)
134#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
135#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
136#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
137#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
138#define CSR_LED_REG (CSR_BASE+0x094)
139#define CSR_DRAM_INT_TBL_CTL (CSR_BASE+0x0A0)
140#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
141#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
142#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
143
144/* HW I/F configuration */
145#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100)
146#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200)
147#define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
148#define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
149#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
150#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
151#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
152
153/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
154 * acknowledged (reset) by host writing "1" to flagged bits. */
155#define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */
156#define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */
157#define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */
158#define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */
159#define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */
160#define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */
161#define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */
162#define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */
163#define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */
164#define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */
165#define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */
166
167#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
168 CSR_INT_BIT_HW_ERR | \
169 CSR_INT_BIT_FH_TX | \
170 CSR_INT_BIT_SW_ERR | \
171 CSR_INT_BIT_RF_KILL | \
172 CSR_INT_BIT_SW_RX | \
173 CSR_INT_BIT_WAKEUP | \
174 CSR_INT_BIT_ALIVE)
175
176/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
177#define CSR_FH_INT_BIT_ERR (1<<31) /* Error */
178#define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */
179#define CSR_FH_INT_BIT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */
180#define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */
181#define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */
182#define CSR_FH_INT_BIT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */
183#define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */
184#define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */
185
186#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
187 CSR_FH_INT_BIT_RX_CHNL2 | \
188 CSR_FH_INT_BIT_RX_CHNL1 | \
189 CSR_FH_INT_BIT_RX_CHNL0)
190
191#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL6 | \
192 CSR_FH_INT_BIT_TX_CHNL1 | \
193 CSR_FH_INT_BIT_TX_CHNL0 )
194
195
196/* RESET */
197#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
198#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
199#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
200#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
201#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
202
203/* GP (general purpose) CONTROL */
204#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
205#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
206#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
207#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
208
209#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
210
211#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
212#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
213#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
214
215
216/* EEPROM REG */
217#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
218#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
219
220/* EEPROM GP */
221#define CSR_EEPROM_GP_VALID_MSK (0x00000006)
222#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
223#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
224
225/* UCODE DRV GP */
226#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
227#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
228#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
229#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
230
231/* GPIO */
232#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
233#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
234#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
235
236/* GI Chicken Bits */
237#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
238#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
239
240/* CSR_ANA_PLL_CFG */
241#define CSR_ANA_PLL_CFG_SH (0x00880300)
242
243#define CSR_LED_REG_TRUN_ON (0x00000078)
244#define CSR_LED_REG_TRUN_OFF (0x00000038)
245#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
246
247/* DRAM_INT_TBL_CTRL */
248#define CSR_DRAM_INT_TBL_CTRL_EN (1<<31)
249#define CSR_DRAM_INT_TBL_CTRL_WRAP_CHK (1<<27)
250
251/*=== HBUS (Host-side Bus) ===*/
252#define HBUS_BASE (0x400)
253
254#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
255#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
256#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
257#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
258#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
259#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
260#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
261#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
262#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
263
264#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
265
266
267/* SCD (Scheduler) */
268#define SCD_BASE (CSR_BASE + 0x2E00)
269
270#define SCD_MODE_REG (SCD_BASE + 0x000)
271#define SCD_ARASTAT_REG (SCD_BASE + 0x004)
272#define SCD_TXFACT_REG (SCD_BASE + 0x010)
273#define SCD_TXF4MF_REG (SCD_BASE + 0x014)
274#define SCD_TXF5MF_REG (SCD_BASE + 0x020)
275#define SCD_SBYP_MODE_1_REG (SCD_BASE + 0x02C)
276#define SCD_SBYP_MODE_2_REG (SCD_BASE + 0x030)
277
278/*=== FH (data Flow Handler) ===*/
279#define FH_BASE (0x800)
280
281#define FH_CBCC_TABLE (FH_BASE+0x140)
282#define FH_TFDB_TABLE (FH_BASE+0x180)
283#define FH_RCSR_TABLE (FH_BASE+0x400)
284#define FH_RSSR_TABLE (FH_BASE+0x4c0)
285#define FH_TCSR_TABLE (FH_BASE+0x500)
286#define FH_TSSR_TABLE (FH_BASE+0x680)
287
288/* TFDB (Transmit Frame Buffer Descriptor) */
289#define FH_TFDB(_channel, buf) \
290 (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
291#define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
292 (FH_TFDB_TABLE + 0x50 * _channel)
293/* CBCC _channel is [0,2] */
294#define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8)
295#define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00)
296#define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04)
297
298/* RCSR _channel is [0,2] */
299#define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40)
300#define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00)
301#define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04)
302#define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20)
303#define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
304
305#if IWL == 3945
306#define FH_RSCSR_CHNL0_WPTR (FH_RCSR_WPTR(0))
307#elif IWL == 4965
308#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
309#endif
310
311/* RSSR */
312#define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000)
313#define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004)
314/* TCSR */
315#define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20)
316#define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00)
317#define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04)
318#define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
319/* TSSR */
320#define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000)
321#define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008)
322#define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010)
323/* 18 - reserved */
324
325/* card static random access memory (SRAM) for processor data and instructs */
326#define RTC_INST_LOWER_BOUND (0x000000)
327#define RTC_DATA_LOWER_BOUND (0x800000)
328
329
330/* DBM */
331
332#define ALM_FH_SRVC_CHNL (6)
333
334#define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
335#define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
336
337#define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
338
339#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
340
341#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
342
343#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
344
345#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
346
347#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
348
349#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
350#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
351
352#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
353#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
354
355#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
356
357#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
358
359#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
360#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
361
362#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
363
364#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
365
366#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
367#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
368
369#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
370
371#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
372#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
373
374#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
375#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
376
377#define ALM_TB_MAX_BYTES_COUNT (0xFFF0)
378
379#define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
380 ((1LU << _channel) << 24)
381#define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
382 ((1LU << _channel) << 16)
383
384#define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
385 (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
386 ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
387#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
388#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
389
390#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
391
392#define TFD_QUEUE_MIN 0
393#define TFD_QUEUE_MAX 6
394#define TFD_QUEUE_SIZE_MAX (256)
395
396/* spectrum and channel data structures */
397#define IWL_NUM_SCAN_RATES (2)
398
399#define IWL_SCAN_FLAG_24GHZ (1<<0)
400#define IWL_SCAN_FLAG_52GHZ (1<<1)
401#define IWL_SCAN_FLAG_ACTIVE (1<<2)
402#define IWL_SCAN_FLAG_DIRECT (1<<3)
403
404#define IWL_MAX_CMD_SIZE 1024
405
406#define IWL_DEFAULT_TX_RETRY 15
407#define IWL_MAX_TX_RETRY 16
408
409/*********************************************/
410
411#define RFD_SIZE 4
412#define NUM_TFD_CHUNKS 4
413
414#define RX_QUEUE_SIZE 256
415#define RX_QUEUE_MASK 255
416#define RX_QUEUE_SIZE_LOG 8
417
418/* QoS definitions */
419
420#define CW_MIN_OFDM 15
421#define CW_MAX_OFDM 1023
422#define CW_MIN_CCK 31
423#define CW_MAX_CCK 1023
424
425#define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM
426#define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM
427#define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
428#define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1)
429
430#define QOS_TX0_CW_MIN_CCK CW_MIN_CCK
431#define QOS_TX1_CW_MIN_CCK CW_MIN_CCK
432#define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1)
433#define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1)
434
435#define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM
436#define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM
437#define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM
438#define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
439
440#define QOS_TX0_CW_MAX_CCK CW_MAX_CCK
441#define QOS_TX1_CW_MAX_CCK CW_MAX_CCK
442#define QOS_TX2_CW_MAX_CCK CW_MIN_CCK
443#define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1)
444
445#define QOS_TX0_AIFS 3
446#define QOS_TX1_AIFS 7
447#define QOS_TX2_AIFS 2
448#define QOS_TX3_AIFS 2
449
450#define QOS_TX0_ACM 0
451#define QOS_TX1_ACM 0
452#define QOS_TX2_ACM 0
453#define QOS_TX3_ACM 0
454
455#define QOS_TX0_TXOP_LIMIT_CCK 0
456#define QOS_TX1_TXOP_LIMIT_CCK 0
457#define QOS_TX2_TXOP_LIMIT_CCK 6016
458#define QOS_TX3_TXOP_LIMIT_CCK 3264
459
460#define QOS_TX0_TXOP_LIMIT_OFDM 0
461#define QOS_TX1_TXOP_LIMIT_OFDM 0
462#define QOS_TX2_TXOP_LIMIT_OFDM 3008
463#define QOS_TX3_TXOP_LIMIT_OFDM 1504
464
465#define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM
466#define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM
467#define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM
468#define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM
469
470#define DEF_TX0_CW_MIN_CCK CW_MIN_CCK
471#define DEF_TX1_CW_MIN_CCK CW_MIN_CCK
472#define DEF_TX2_CW_MIN_CCK CW_MIN_CCK
473#define DEF_TX3_CW_MIN_CCK CW_MIN_CCK
474
475#define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM
476#define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM
477#define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM
478#define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM
479
480#define DEF_TX0_CW_MAX_CCK CW_MAX_CCK
481#define DEF_TX1_CW_MAX_CCK CW_MAX_CCK
482#define DEF_TX2_CW_MAX_CCK CW_MAX_CCK
483#define DEF_TX3_CW_MAX_CCK CW_MAX_CCK
484
485#define DEF_TX0_AIFS (2)
486#define DEF_TX1_AIFS (2)
487#define DEF_TX2_AIFS (2)
488#define DEF_TX3_AIFS (2)
489
490#define DEF_TX0_ACM 0
491#define DEF_TX1_ACM 0
492#define DEF_TX2_ACM 0
493#define DEF_TX3_ACM 0
494
495#define DEF_TX0_TXOP_LIMIT_CCK 0
496#define DEF_TX1_TXOP_LIMIT_CCK 0
497#define DEF_TX2_TXOP_LIMIT_CCK 0
498#define DEF_TX3_TXOP_LIMIT_CCK 0
499
500#define DEF_TX0_TXOP_LIMIT_OFDM 0
501#define DEF_TX1_TXOP_LIMIT_OFDM 0
502#define DEF_TX2_TXOP_LIMIT_OFDM 0
503#define DEF_TX3_TXOP_LIMIT_OFDM 0
504
505#define QOS_QOS_SETS 3
506#define QOS_PARAM_SET_ACTIVE 0
507#define QOS_PARAM_SET_DEF_CCK 1
508#define QOS_PARAM_SET_DEF_OFDM 2
509
510#define CTRL_QOS_NO_ACK (0x0020)
511#define DCT_FLAG_EXT_QOS_ENABLED (0x10)
512
513#define U32_PAD(n) ((4-(n))&0x3)
514
515/*
516 * Generic queue structure
517 *
518 * Contains common data for Rx and Tx queues
519 */
520#define TFD_CTL_COUNT_SET(n) (n<<24)
521#define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7)
522#define TFD_CTL_PAD_SET(n) (n<<28)
523#define TFD_CTL_PAD_GET(ctl) (ctl>>28)
524
525#define TFD_TX_CMD_SLOTS 256
526#define TFD_CMD_SLOTS 32
527
528#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
529 sizeof(struct iwl_cmd_meta))
530
531/*
532 * RX related structures and functions
533 */
534#define RX_FREE_BUFFERS 64
535#define RX_LOW_WATERMARK 8
536
537#endif /* __iwlwifi_hw_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-priv.h b/drivers/net/wireless/iwlwifi/iwl-priv.h
deleted file mode 100644
index c25f2ffccfff..000000000000
--- a/drivers/net/wireless/iwlwifi/iwl-priv.h
+++ /dev/null
@@ -1,307 +0,0 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#ifndef __iwl_priv_h__
28#define __iwl_priv_h__
29
30#include <linux/workqueue.h>
31
32#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
33
34enum {
35 MEASUREMENT_READY = (1 << 0),
36 MEASUREMENT_ACTIVE = (1 << 1),
37};
38
39#endif
40
41struct iwl_priv {
42
43 /* ieee device used by generic ieee processing code */
44 struct ieee80211_hw *hw;
45 struct ieee80211_channel *ieee_channels;
46 struct ieee80211_rate *ieee_rates;
47
48 /* temporary frame storage list */
49 struct list_head free_frames;
50 int frames_count;
51
52 u8 phymode;
53 int alloc_rxb_skb;
54
55 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
56 struct iwl_rx_mem_buffer *rxb);
57
58 const struct ieee80211_hw_mode *modes;
59
60#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
61 /* spectrum measurement report caching */
62 struct iwl_spectrum_notification measure_report;
63 u8 measurement_status;
64#endif
65 /* ucode beacon time */
66 u32 ucode_beacon_time;
67
68 /* we allocate array of iwl_channel_info for NIC's valid channels.
69 * Access via channel # using indirect index array */
70 struct iwl_channel_info *channel_info; /* channel info array */
71 u8 channel_count; /* # of channels */
72
73 /* each calibration channel group in the EEPROM has a derived
74 * clip setting for each rate. */
75 const struct iwl_clip_group clip_groups[5];
76
77 /* thermal calibration */
78 s32 temperature; /* degrees Kelvin */
79 s32 last_temperature;
80
81 /* Scan related variables */
82 unsigned long last_scan_jiffies;
83 unsigned long scan_start;
84 unsigned long scan_pass_start;
85 unsigned long scan_start_tsf;
86 int scan_bands;
87 int one_direct_scan;
88 u8 direct_ssid_len;
89 u8 direct_ssid[IW_ESSID_MAX_SIZE];
90 struct iwl_scan_cmd *scan;
91 u8 only_active_channel;
92
93 /* spinlock */
94 spinlock_t lock; /* protect general shared data */
95 spinlock_t hcmd_lock; /* protect hcmd */
96 struct mutex mutex;
97
98 /* basic pci-network driver stuff */
99 struct pci_dev *pci_dev;
100
101 /* pci hardware address support */
102 void __iomem *hw_base;
103
104 /* uCode images, save to reload in case of failure */
105 struct fw_desc ucode_code; /* runtime inst */
106 struct fw_desc ucode_data; /* runtime data original */
107 struct fw_desc ucode_data_backup; /* runtime data save/restore */
108 struct fw_desc ucode_init; /* initialization inst */
109 struct fw_desc ucode_init_data; /* initialization data */
110 struct fw_desc ucode_boot; /* bootstrap inst */
111
112
113 struct iwl_rxon_time_cmd rxon_timing;
114
115 /* We declare this const so it can only be
116 * changed via explicit cast within the
117 * routines that actually update the physical
118 * hardware */
119 const struct iwl_rxon_cmd active_rxon;
120 struct iwl_rxon_cmd staging_rxon;
121
122 int error_recovering;
123 struct iwl_rxon_cmd recovery_rxon;
124
125 /* 1st responses from initialize and runtime uCode images.
126 * 4965's initialize alive response contains some calibration data. */
127 struct iwl_init_alive_resp card_alive_init;
128 struct iwl_alive_resp card_alive;
129
130#ifdef LED
131 /* LED related variables */
132 struct iwl_activity_blink activity;
133 unsigned long led_packets;
134 int led_state;
135#endif
136
137 u16 active_rate;
138 u16 active_rate_basic;
139
140 u8 call_post_assoc_from_beacon;
141 u8 assoc_station_added;
142#if IWL == 4965
143 u8 use_ant_b_for_management_frame; /* Tx antenna selection */
144 /* HT variables */
145 u8 is_dup;
146 u8 is_ht_enabled;
147 u8 channel_width; /* 0=20MHZ, 1=40MHZ */
148 u8 current_channel_width;
149 u8 valid_antenna; /* Bit mask of antennas actually connected */
150#ifdef CONFIG_IWLWIFI_SENSITIVITY
151 struct iwl_sensitivity_data sensitivity_data;
152 struct iwl_chain_noise_data chain_noise_data;
153 u8 start_calib;
154 __le16 sensitivity_tbl[HD_TABLE_SIZE];
155#endif /*CONFIG_IWLWIFI_SENSITIVITY*/
156
157#ifdef CONFIG_IWLWIFI_HT
158 struct sta_ht_info current_assoc_ht;
159#endif
160 u8 active_rate_ht[2];
161 u8 last_phy_res[100];
162
163 /* Rate scaling data */
164 struct iwl_lq_mngr lq_mngr;
165#endif
166
167 /* Rate scaling data */
168 s8 data_retry_limit;
169 u8 retry_rate;
170
171 wait_queue_head_t wait_command_queue;
172
173 int activity_timer_active;
174
175 /* Rx and Tx DMA processing queues */
176 struct iwl_rx_queue rxq;
177 struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES];
178#if IWL == 4965
179 unsigned long txq_ctx_active_msk;
180 struct iwl_kw kw; /* keep warm address */
181 u32 scd_base_addr; /* scheduler sram base address */
182#endif
183
184 unsigned long status;
185 u32 config;
186
187 int last_rx_rssi; /* From Rx packet statisitics */
188 int last_rx_noise; /* From beacon statistics */
189
190 struct iwl_power_mgr power_data;
191
192 struct iwl_notif_statistics statistics;
193 unsigned long last_statistics_time;
194
195 /* context information */
196 u8 essid[IW_ESSID_MAX_SIZE];
197 u8 essid_len;
198 u16 rates_mask;
199
200 u32 power_mode;
201 u32 antenna;
202 u8 bssid[ETH_ALEN];
203 u16 rts_threshold;
204 u8 mac_addr[ETH_ALEN];
205
206 /*station table variables */
207 spinlock_t sta_lock;
208 int num_stations;
209 struct iwl_station_entry stations[IWL_STATION_COUNT];
210
211 /* Indication if ieee80211_ops->open has been called */
212 int is_open;
213
214 u8 mac80211_registered;
215 int is_abg;
216
217 u32 notif_missed_beacons;
218
219 /* Rx'd packet timing information */
220 u32 last_beacon_time;
221 u64 last_tsf;
222
223 /* Duplicate packet detection */
224 u16 last_seq_num;
225 u16 last_frag_num;
226 unsigned long last_packet_time;
227 struct list_head ibss_mac_hash[IWL_IBSS_MAC_HASH_SIZE];
228
229 /* eeprom */
230 struct iwl_eeprom eeprom;
231
232 int iw_mode;
233
234 struct sk_buff *ibss_beacon;
235
236 /* Last Rx'd beacon timestamp */
237 u32 timestamp0;
238 u32 timestamp1;
239 u16 beacon_int;
240 struct iwl_driver_hw_info hw_setting;
241 int interface_id;
242
243 /* Current association information needed to configure the
244 * hardware */
245 u16 assoc_id;
246 u16 assoc_capability;
247 u8 ps_mode;
248
249#ifdef CONFIG_IWLWIFI_QOS
250 struct iwl_qos_info qos_data;
251#endif /*CONFIG_IWLWIFI_QOS */
252
253 struct workqueue_struct *workqueue;
254
255 struct work_struct up;
256 struct work_struct restart;
257 struct work_struct calibrated_work;
258 struct work_struct scan_completed;
259 struct work_struct rx_replenish;
260 struct work_struct rf_kill;
261 struct work_struct abort_scan;
262 struct work_struct update_link_led;
263 struct work_struct auth_work;
264 struct work_struct report_work;
265 struct work_struct request_scan;
266 struct work_struct beacon_update;
267
268 struct tasklet_struct irq_tasklet;
269
270 struct delayed_work init_alive_start;
271 struct delayed_work alive_start;
272 struct delayed_work activity_timer;
273 struct delayed_work thermal_periodic;
274 struct delayed_work gather_stats;
275 struct delayed_work scan_check;
276 struct delayed_work post_associate;
277
278#define IWL_DEFAULT_TX_POWER 0x0F
279 s8 user_txpower_limit;
280 s8 max_channel_txpower_limit;
281
282#ifdef CONFIG_PM
283 u32 pm_state[16];
284#endif
285
286#ifdef CONFIG_IWLWIFI_DEBUG
287 /* debugging info */
288 u32 framecnt_to_us;
289 atomic_t restrict_refcnt;
290#endif
291
292#if IWL == 4965
293 struct work_struct txpower_work;
294#ifdef CONFIG_IWLWIFI_SENSITIVITY
295 struct work_struct sensitivity_work;
296#endif
297 struct work_struct statistics_work;
298 struct timer_list statistics_periodic;
299
300#ifdef CONFIG_IWLWIFI_HT_AGG
301 struct work_struct agg_work;
302#endif
303
304#endif /* 4965 */
305}; /*iwl_priv */
306
307#endif /* __iwl_priv_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index 3cccb3db6ff7..b9b67e617fff 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -56,9 +56,6 @@
56 56
57#include <asm/div64.h> 57#include <asm/div64.h>
58 58
59#define IWL 3945
60
61#include "iwlwifi.h"
62#include "iwl-3945.h" 59#include "iwl-3945.h"
63#include "iwl-helpers.h" 60#include "iwl-helpers.h"
64 61
diff --git a/drivers/net/wireless/iwlwifi/iwl4965-base.c b/drivers/net/wireless/iwlwifi/iwl4965-base.c
index 0e46ffde22a7..1e7b589ac865 100644
--- a/drivers/net/wireless/iwlwifi/iwl4965-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl4965-base.c
@@ -56,9 +56,6 @@
56 56
57#include <asm/div64.h> 57#include <asm/div64.h>
58 58
59#define IWL 4965
60
61#include "iwlwifi.h"
62#include "iwl-4965.h" 59#include "iwl-4965.h"
63#include "iwl-helpers.h" 60#include "iwl-helpers.h"
64 61
diff --git a/drivers/net/wireless/iwlwifi/iwlwifi.h b/drivers/net/wireless/iwlwifi/iwlwifi.h
deleted file mode 100644
index 96558cc60ae6..000000000000
--- a/drivers/net/wireless/iwlwifi/iwlwifi.h
+++ /dev/null
@@ -1,695 +0,0 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#ifndef __iwlwifi_h__
31#define __iwlwifi_h__
32
33#include <linux/pci.h> /* for struct pci_device_id */
34#include <linux/kernel.h>
35#include <net/ieee80211_radiotap.h>
36
37struct iwl_priv;
38
39/* Hardware specific file defines the PCI IDs table for that hardware module */
40extern struct pci_device_id iwl_hw_card_ids[];
41
42#include "iwl-hw.h"
43#if IWL == 3945
44#define DRV_NAME "iwl3945"
45#include "iwl-3945-hw.h"
46#elif IWL == 4965
47#define DRV_NAME "iwl4965"
48#include "iwl-4965-hw.h"
49#endif
50
51#include "iwl-prph.h"
52
53/*
54 * Driver implementation data structures, constants, inline
55 * functions
56 *
57 * NOTE: DO NOT PUT HARDWARE/UCODE SPECIFIC DECLARATIONS HERE
58 *
59 * Hardware specific declarations go into iwl-*hw.h
60 *
61 */
62
63#include "iwl-debug.h"
64
65/* Default noise level to report when noise measurement is not available.
66 * This may be because we're:
67 * 1) Not associated (4965, no beacon statistics being sent to driver)
68 * 2) Scanning (noise measurement does not apply to associated channel)
69 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
70 * Use default noise value of -127 ... this is below the range of measurable
71 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
72 * Also, -127 works better than 0 when averaging frames with/without
73 * noise info (e.g. averaging might be done in app); measured dBm values are
74 * always negative ... using a negative value as the default keeps all
75 * averages within an s8's (used in some apps) range of negative values. */
76#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
77
78/* Module parameters accessible from iwl-*.c */
79extern int iwl_param_hwcrypto;
80extern int iwl_param_queues_num;
81
82enum iwl_antenna {
83 IWL_ANTENNA_DIVERSITY,
84 IWL_ANTENNA_MAIN,
85 IWL_ANTENNA_AUX
86};
87
88/*
89 * RTS threshold here is total size [2347] minus 4 FCS bytes
90 * Per spec:
91 * a value of 0 means RTS on all data/management packets
92 * a value > max MSDU size means no RTS
93 * else RTS for data/management frames where MPDU is larger
94 * than RTS value.
95 */
96#define DEFAULT_RTS_THRESHOLD 2347U
97#define MIN_RTS_THRESHOLD 0U
98#define MAX_RTS_THRESHOLD 2347U
99#define MAX_MSDU_SIZE 2304U
100#define MAX_MPDU_SIZE 2346U
101#define DEFAULT_BEACON_INTERVAL 100U
102#define DEFAULT_SHORT_RETRY_LIMIT 7U
103#define DEFAULT_LONG_RETRY_LIMIT 4U
104
105struct iwl_rx_mem_buffer {
106 dma_addr_t dma_addr;
107 struct sk_buff *skb;
108 struct list_head list;
109};
110
111struct iwl_rt_rx_hdr {
112 struct ieee80211_radiotap_header rt_hdr;
113 __le64 rt_tsf; /* TSF */
114 u8 rt_flags; /* radiotap packet flags */
115 u8 rt_rate; /* rate in 500kb/s */
116 __le16 rt_channelMHz; /* channel in MHz */
117 __le16 rt_chbitmask; /* channel bitfield */
118 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
119 s8 rt_dbmnoise;
120 u8 rt_antenna; /* antenna number */
121 u8 payload[0]; /* payload... */
122} __attribute__ ((packed));
123
124struct iwl_rt_tx_hdr {
125 struct ieee80211_radiotap_header rt_hdr;
126 u8 rt_rate; /* rate in 500kb/s */
127 __le16 rt_channel; /* channel in mHz */
128 __le16 rt_chbitmask; /* channel bitfield */
129 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
130 u8 rt_antenna; /* antenna number */
131 u8 payload[0]; /* payload... */
132} __attribute__ ((packed));
133
134/*
135 * Generic queue structure
136 *
137 * Contains common data for Rx and Tx queues
138 */
139struct iwl_queue {
140 int n_bd; /* number of BDs in this queue */
141 int write_ptr; /* 1-st empty entry (index) host_w*/
142 int read_ptr; /* last used entry (index) host_r*/
143 dma_addr_t dma_addr; /* physical addr for BD's */
144 int n_window; /* safe queue window */
145 u32 id;
146 int low_mark; /* low watermark, resume queue if free
147 * space more than this */
148 int high_mark; /* high watermark, stop queue if free
149 * space less than this */
150} __attribute__ ((packed));
151
152#define MAX_NUM_OF_TBS (20)
153
154struct iwl_tx_info {
155 struct ieee80211_tx_status status;
156 struct sk_buff *skb[MAX_NUM_OF_TBS];
157};
158
159/**
160 * struct iwl_tx_queue - Tx Queue for DMA
161 * @need_update: need to update read/write index
162 * @shed_retry: queue is HT AGG enabled
163 *
164 * Queue consists of circular buffer of BD's and required locking structures.
165 */
166struct iwl_tx_queue {
167 struct iwl_queue q;
168 struct iwl_tfd_frame *bd;
169 struct iwl_cmd *cmd;
170 dma_addr_t dma_addr_cmd;
171 struct iwl_tx_info *txb;
172 int need_update;
173 int sched_retry;
174 int active;
175};
176
177#include "iwl-channel.h"
178
179#if IWL == 3945
180#include "iwl-3945-rs.h"
181#else
182#include "iwl-4965-rs.h"
183#endif
184
185#define IWL_TX_FIFO_AC0 0
186#define IWL_TX_FIFO_AC1 1
187#define IWL_TX_FIFO_AC2 2
188#define IWL_TX_FIFO_AC3 3
189#define IWL_TX_FIFO_HCCA_1 5
190#define IWL_TX_FIFO_HCCA_2 6
191#define IWL_TX_FIFO_NONE 7
192
193/* Minimum number of queues. MAX_NUM is defined in hw specific files */
194#define IWL_MIN_NUM_QUEUES 4
195
196/* Power management (not Tx power) structures */
197
198struct iwl_power_vec_entry {
199 struct iwl_powertable_cmd cmd;
200 u8 no_dtim;
201};
202#define IWL_POWER_RANGE_0 (0)
203#define IWL_POWER_RANGE_1 (1)
204
205#define IWL_POWER_MODE_CAM 0x00 /* Continuously Aware Mode, always on */
206#define IWL_POWER_INDEX_3 0x03
207#define IWL_POWER_INDEX_5 0x05
208#define IWL_POWER_AC 0x06
209#define IWL_POWER_BATTERY 0x07
210#define IWL_POWER_LIMIT 0x07
211#define IWL_POWER_MASK 0x0F
212#define IWL_POWER_ENABLED 0x10
213#define IWL_POWER_LEVEL(x) ((x) & IWL_POWER_MASK)
214
215struct iwl_power_mgr {
216 spinlock_t lock;
217 struct iwl_power_vec_entry pwr_range_0[IWL_POWER_AC];
218 struct iwl_power_vec_entry pwr_range_1[IWL_POWER_AC];
219 u8 active_index;
220 u32 dtim_val;
221};
222
223#define IEEE80211_DATA_LEN 2304
224#define IEEE80211_4ADDR_LEN 30
225#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
226#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
227
228struct iwl_frame {
229 union {
230 struct ieee80211_hdr frame;
231 struct iwl_tx_beacon_cmd beacon;
232 u8 raw[IEEE80211_FRAME_LEN];
233 u8 cmd[360];
234 } u;
235 struct list_head list;
236};
237
238#define SEQ_TO_QUEUE(x) ((x >> 8) & 0xbf)
239#define QUEUE_TO_SEQ(x) ((x & 0xbf) << 8)
240#define SEQ_TO_INDEX(x) (x & 0xff)
241#define INDEX_TO_SEQ(x) (x & 0xff)
242#define SEQ_HUGE_FRAME (0x4000)
243#define SEQ_RX_FRAME __constant_cpu_to_le16(0x8000)
244#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
245#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
246#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
247
248enum {
249 /* CMD_SIZE_NORMAL = 0, */
250 CMD_SIZE_HUGE = (1 << 0),
251 /* CMD_SYNC = 0, */
252 CMD_ASYNC = (1 << 1),
253 /* CMD_NO_SKB = 0, */
254 CMD_WANT_SKB = (1 << 2),
255};
256
257struct iwl_cmd;
258struct iwl_priv;
259
260struct iwl_cmd_meta {
261 struct iwl_cmd_meta *source;
262 union {
263 struct sk_buff *skb;
264 int (*callback)(struct iwl_priv *priv,
265 struct iwl_cmd *cmd, struct sk_buff *skb);
266 } __attribute__ ((packed)) u;
267
268 /* The CMD_SIZE_HUGE flag bit indicates that the command
269 * structure is stored at the end of the shared queue memory. */
270 u32 flags;
271
272} __attribute__ ((packed));
273
274struct iwl_cmd {
275 struct iwl_cmd_meta meta;
276 struct iwl_cmd_header hdr;
277 union {
278 struct iwl_addsta_cmd addsta;
279 struct iwl_led_cmd led;
280 u32 flags;
281 u8 val8;
282 u16 val16;
283 u32 val32;
284 struct iwl_bt_cmd bt;
285 struct iwl_rxon_time_cmd rxon_time;
286 struct iwl_powertable_cmd powertable;
287 struct iwl_qosparam_cmd qosparam;
288 struct iwl_tx_cmd tx;
289 struct iwl_tx_beacon_cmd tx_beacon;
290 struct iwl_rxon_assoc_cmd rxon_assoc;
291 u8 *indirect;
292 u8 payload[360];
293 } __attribute__ ((packed)) cmd;
294} __attribute__ ((packed));
295
296struct iwl_host_cmd {
297 u8 id;
298 u16 len;
299 struct iwl_cmd_meta meta;
300 const void *data;
301};
302
303#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
304 sizeof(struct iwl_cmd_meta))
305
306/*
307 * RX related structures and functions
308 */
309#define RX_FREE_BUFFERS 64
310#define RX_LOW_WATERMARK 8
311
312#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
313#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
314#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
315
316/**
317 * struct iwl_rx_queue - Rx queue
318 * @processed: Internal index to last handled Rx packet
319 * @read: Shared index to newest available Rx buffer
320 * @write: Shared index to oldest written Rx packet
321 * @free_count: Number of pre-allocated buffers in rx_free
322 * @rx_free: list of free SKBs for use
323 * @rx_used: List of Rx buffers with no SKB
324 * @need_update: flag to indicate we need to update read/write index
325 *
326 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
327 */
328struct iwl_rx_queue {
329 __le32 *bd;
330 dma_addr_t dma_addr;
331 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
332 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
333 u32 processed;
334 u32 read;
335 u32 write;
336 u32 free_count;
337 struct list_head rx_free;
338 struct list_head rx_used;
339 int need_update;
340 spinlock_t lock;
341};
342
343#define IWL_SUPPORTED_RATES_IE_LEN 8
344
345#define SCAN_INTERVAL 100
346
347#define MAX_A_CHANNELS 252
348#define MIN_A_CHANNELS 7
349
350#define MAX_B_CHANNELS 14
351#define MIN_B_CHANNELS 1
352
353#define STATUS_HCMD_ACTIVE 0 /* host command in progress */
354#define STATUS_INT_ENABLED 1
355#define STATUS_RF_KILL_HW 2
356#define STATUS_RF_KILL_SW 3
357#define STATUS_INIT 4
358#define STATUS_ALIVE 5
359#define STATUS_READY 6
360#define STATUS_TEMPERATURE 7
361#define STATUS_GEO_CONFIGURED 8
362#define STATUS_EXIT_PENDING 9
363#define STATUS_IN_SUSPEND 10
364#define STATUS_STATISTICS 11
365#define STATUS_SCANNING 12
366#define STATUS_SCAN_ABORTING 13
367#define STATUS_SCAN_HW 14
368#define STATUS_POWER_PMI 15
369#define STATUS_FW_ERROR 16
370
371#define MAX_TID_COUNT 9
372
373#define IWL_INVALID_RATE 0xFF
374#define IWL_INVALID_VALUE -1
375
376#if IWL == 4965
377#ifdef CONFIG_IWLWIFI_HT
378#ifdef CONFIG_IWLWIFI_HT_AGG
379struct iwl_ht_agg {
380 u16 txq_id;
381 u16 frame_count;
382 u16 wait_for_ba;
383 u16 start_idx;
384 u32 bitmap0;
385 u32 bitmap1;
386 u32 rate_n_flags;
387};
388#endif /* CONFIG_IWLWIFI_HT_AGG */
389#endif /* CONFIG_IWLWIFI_HT */
390#endif
391
392struct iwl_tid_data {
393 u16 seq_number;
394#if IWL == 4965
395#ifdef CONFIG_IWLWIFI_HT
396#ifdef CONFIG_IWLWIFI_HT_AGG
397 struct iwl_ht_agg agg;
398#endif /* CONFIG_IWLWIFI_HT_AGG */
399#endif /* CONFIG_IWLWIFI_HT */
400#endif
401};
402
403struct iwl_hw_key {
404 enum ieee80211_key_alg alg;
405 int keylen;
406 u8 key[32];
407};
408
409union iwl_ht_rate_supp {
410 u16 rates;
411 struct {
412 u8 siso_rate;
413 u8 mimo_rate;
414 };
415};
416
417#ifdef CONFIG_IWLWIFI_HT
418#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
419#define HT_IE_MAX_AMSDU_SIZE_4K (0)
420#define CFG_HT_MPDU_DENSITY_2USEC (0x5)
421#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC
422
423struct sta_ht_info {
424 u8 is_ht;
425 u16 rx_mimo_ps_mode;
426 u16 tx_mimo_ps_mode;
427 u16 control_channel;
428 u8 max_amsdu_size;
429 u8 ampdu_factor;
430 u8 mpdu_density;
431 u8 operating_mode;
432 u8 supported_chan_width;
433 u8 extension_chan_offset;
434 u8 is_green_field;
435 u8 sgf;
436 u8 supp_rates[16];
437 u8 tx_chan_width;
438 u8 chan_width_cap;
439};
440#endif /*CONFIG_IWLWIFI_HT */
441
442#ifdef CONFIG_IWLWIFI_QOS
443
444union iwl_qos_capabity {
445 struct {
446 u8 edca_count:4; /* bit 0-3 */
447 u8 q_ack:1; /* bit 4 */
448 u8 queue_request:1; /* bit 5 */
449 u8 txop_request:1; /* bit 6 */
450 u8 reserved:1; /* bit 7 */
451 } q_AP;
452 struct {
453 u8 acvo_APSD:1; /* bit 0 */
454 u8 acvi_APSD:1; /* bit 1 */
455 u8 ac_bk_APSD:1; /* bit 2 */
456 u8 ac_be_APSD:1; /* bit 3 */
457 u8 q_ack:1; /* bit 4 */
458 u8 max_len:2; /* bit 5-6 */
459 u8 more_data_ack:1; /* bit 7 */
460 } q_STA;
461 u8 val;
462};
463
464/* QoS structures */
465struct iwl_qos_info {
466 int qos_enable;
467 int qos_active;
468 union iwl_qos_capabity qos_cap;
469 struct iwl_qosparam_cmd def_qos_parm;
470};
471#endif /*CONFIG_IWLWIFI_QOS */
472
473#define STA_PS_STATUS_WAKE 0
474#define STA_PS_STATUS_SLEEP 1
475
476struct iwl_station_entry {
477 struct iwl_addsta_cmd sta;
478 struct iwl_tid_data tid[MAX_TID_COUNT];
479#if IWL == 3945
480 union {
481 struct {
482 u8 rate;
483 u8 flags;
484 } s;
485 u16 rate_n_flags;
486 } current_rate;
487#endif
488 u8 used;
489 u8 ps_status;
490 struct iwl_hw_key keyinfo;
491};
492
493/* one for each uCode image (inst/data, boot/init/runtime) */
494struct fw_desc {
495 void *v_addr; /* access by driver */
496 dma_addr_t p_addr; /* access by card's busmaster DMA */
497 u32 len; /* bytes */
498};
499
500/* uCode file layout */
501struct iwl_ucode {
502 __le32 ver; /* major/minor/subminor */
503 __le32 inst_size; /* bytes of runtime instructions */
504 __le32 data_size; /* bytes of runtime data */
505 __le32 init_size; /* bytes of initialization instructions */
506 __le32 init_data_size; /* bytes of initialization data */
507 __le32 boot_size; /* bytes of bootstrap instructions */
508 u8 data[0]; /* data in same order as "size" elements */
509};
510
511#define IWL_IBSS_MAC_HASH_SIZE 32
512
513struct iwl_ibss_seq {
514 u8 mac[ETH_ALEN];
515 u16 seq_num;
516 u16 frag_num;
517 unsigned long packet_time;
518 struct list_head list;
519};
520
521struct iwl_driver_hw_info {
522 u16 max_txq_num;
523 u16 ac_queue_count;
524 u16 tx_cmd_len;
525 u16 max_rxq_size;
526 u32 rx_buffer_size;
527 u16 max_rxq_log;
528 u8 max_stations;
529 u8 bcast_sta_id;
530 void *shared_virt;
531 dma_addr_t shared_phys;
532};
533
534
535#define STA_FLG_RTS_MIMO_PROT_MSK __constant_cpu_to_le32(1 << 17)
536#define STA_FLG_AGG_MPDU_8US_MSK __constant_cpu_to_le32(1 << 18)
537#define STA_FLG_MAX_AGG_SIZE_POS (19)
538#define STA_FLG_MAX_AGG_SIZE_MSK __constant_cpu_to_le32(3 << 19)
539#define STA_FLG_FAT_EN_MSK __constant_cpu_to_le32(1 << 21)
540#define STA_FLG_MIMO_DIS_MSK __constant_cpu_to_le32(1 << 22)
541#define STA_FLG_AGG_MPDU_DENSITY_POS (23)
542#define STA_FLG_AGG_MPDU_DENSITY_MSK __constant_cpu_to_le32(7 << 23)
543#define HT_SHORT_GI_20MHZ_ONLY (1 << 0)
544#define HT_SHORT_GI_40MHZ_ONLY (1 << 1)
545
546
547#include "iwl-priv.h"
548
549/* Requires full declaration of iwl_priv before including */
550#include "iwl-io.h"
551
552#define IWL_RX_HDR(x) ((struct iwl_rx_frame_hdr *)(\
553 x->u.rx_frame.stats.payload + \
554 x->u.rx_frame.stats.phy_count))
555#define IWL_RX_END(x) ((struct iwl_rx_frame_end *)(\
556 IWL_RX_HDR(x)->payload + \
557 le16_to_cpu(IWL_RX_HDR(x)->len)))
558#define IWL_RX_STATS(x) (&x->u.rx_frame.stats)
559#define IWL_RX_DATA(x) (IWL_RX_HDR(x)->payload)
560
561
562/******************************************************************************
563 *
564 * Functions implemented in iwl-base.c which are forward declared here
565 * for use by iwl-*.c
566 *
567 *****************************************************************************/
568struct iwl_addsta_cmd;
569extern int iwl_send_add_station(struct iwl_priv *priv,
570 struct iwl_addsta_cmd *sta, u8 flags);
571extern u8 iwl_add_station(struct iwl_priv *priv, const u8 *bssid,
572 int is_ap, u8 flags);
573extern int iwl_is_network_packet(struct iwl_priv *priv,
574 struct ieee80211_hdr *header);
575extern int iwl_power_init_handle(struct iwl_priv *priv);
576extern int iwl_eeprom_init(struct iwl_priv *priv);
577#ifdef CONFIG_IWLWIFI_DEBUG
578extern void iwl_report_frame(struct iwl_priv *priv,
579 struct iwl_rx_packet *pkt,
580 struct ieee80211_hdr *header, int group100);
581#else
582static inline void iwl_report_frame(struct iwl_priv *priv,
583 struct iwl_rx_packet *pkt,
584 struct ieee80211_hdr *header,
585 int group100) {}
586#endif
587extern void iwl_handle_data_packet_monitor(struct iwl_priv *priv,
588 struct iwl_rx_mem_buffer *rxb,
589 void *data, short len,
590 struct ieee80211_rx_status *stats,
591 u16 phy_flags);
592extern int is_duplicate_packet(struct iwl_priv *priv, struct ieee80211_hdr
593 *header);
594extern int iwl_rx_queue_alloc(struct iwl_priv *priv);
595extern void iwl_rx_queue_reset(struct iwl_priv *priv,
596 struct iwl_rx_queue *rxq);
597extern int iwl_calc_db_from_ratio(int sig_ratio);
598extern int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm);
599extern int iwl_tx_queue_init(struct iwl_priv *priv,
600 struct iwl_tx_queue *txq, int count, u32 id);
601extern void iwl_rx_replenish(void *data);
602extern void iwl_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq);
603extern int iwl_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len,
604 const void *data);
605extern int __must_check iwl_send_cmd(struct iwl_priv *priv,
606 struct iwl_host_cmd *cmd);
607extern unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
608 struct ieee80211_hdr *hdr,
609 const u8 *dest, int left);
610extern int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
611 struct iwl_rx_queue *q);
612extern int iwl_send_statistics_request(struct iwl_priv *priv);
613extern void iwl_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
614 u32 decrypt_res,
615 struct ieee80211_rx_status *stats);
616#if IWL == 4965
617extern __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr);
618#endif
619
620extern const u8 BROADCAST_ADDR[ETH_ALEN];
621
622/*
623 * Currently used by iwl-3945-rs... look at restructuring so that it doesn't
624 * call this... todo... fix that.
625*/
626extern u8 iwl_sync_station(struct iwl_priv *priv, int sta_id,
627 u16 tx_rate, u8 flags);
628
629static inline int iwl_is_associated(struct iwl_priv *priv)
630{
631 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
632}
633
634/******************************************************************************
635 *
636 * Functions implemented in iwl-[34]*.c which are forward declared here
637 * for use by iwl-base.c
638 *
639 * NOTE: The implementation of these functions are hardware specific
640 * which is why they are in the hardware specific files (vs. iwl-base.c)
641 *
642 * Naming convention --
643 * iwl_ <-- Its part of iwlwifi (should be changed to iwl_)
644 * iwl_hw_ <-- Hardware specific (implemented in iwl-XXXX.c by all HW)
645 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
646 * iwl_bg_ <-- Called from work queue context
647 * iwl_mac_ <-- mac80211 callback
648 *
649 ****************************************************************************/
650extern void iwl_hw_rx_handler_setup(struct iwl_priv *priv);
651extern void iwl_hw_setup_deferred_work(struct iwl_priv *priv);
652extern void iwl_hw_cancel_deferred_work(struct iwl_priv *priv);
653extern int iwl_hw_rxq_stop(struct iwl_priv *priv);
654extern int iwl_hw_set_hw_setting(struct iwl_priv *priv);
655extern int iwl_hw_nic_init(struct iwl_priv *priv);
656extern int iwl_hw_nic_stop_master(struct iwl_priv *priv);
657extern void iwl_hw_txq_ctx_free(struct iwl_priv *priv);
658extern void iwl_hw_txq_ctx_stop(struct iwl_priv *priv);
659extern int iwl_hw_nic_reset(struct iwl_priv *priv);
660extern int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *tfd,
661 dma_addr_t addr, u16 len);
662extern int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq);
663extern int iwl_hw_get_temperature(struct iwl_priv *priv);
664extern int iwl_hw_tx_queue_init(struct iwl_priv *priv,
665 struct iwl_tx_queue *txq);
666extern unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
667 struct iwl_frame *frame, u8 rate);
668extern int iwl_hw_get_rx_read(struct iwl_priv *priv);
669extern void iwl_hw_build_tx_cmd_rate(struct iwl_priv *priv,
670 struct iwl_cmd *cmd,
671 struct ieee80211_tx_control *ctrl,
672 struct ieee80211_hdr *hdr,
673 int sta_id, int tx_id);
674extern int iwl_hw_reg_send_txpower(struct iwl_priv *priv);
675extern int iwl_hw_reg_set_txpower(struct iwl_priv *priv, s8 power);
676extern void iwl_hw_rx_statistics(struct iwl_priv *priv,
677 struct iwl_rx_mem_buffer *rxb);
678extern void iwl_disable_events(struct iwl_priv *priv);
679extern int iwl4965_get_temperature(const struct iwl_priv *priv);
680
681/**
682 * iwl_hw_find_station - Find station id for a given BSSID
683 * @bssid: MAC address of station ID to find
684 *
685 * NOTE: This should not be hardware specific but the code has
686 * not yet been merged into a single common layer for managing the
687 * station tables.
688 */
689extern u8 iwl_hw_find_station(struct iwl_priv *priv, const u8 *bssid);
690
691extern int iwl_hw_channel_switch(struct iwl_priv *priv, u16 channel);
692#if IWL == 4965
693extern int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index);
694#endif
695#endif