aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless
diff options
context:
space:
mode:
authorDavid S. Miller <davem@davemloft.net>2009-11-09 14:17:24 -0500
committerDavid S. Miller <davem@davemloft.net>2009-11-09 14:17:24 -0500
commitf6d773cd4f3c18c40ab25a5cb92453756237840e (patch)
tree5631a6ea4495ae2eb5058fb63b25dea3b197d61b /drivers/net/wireless
parentd0e1e88d6e7dbd8e1661cb6a058ca30f54ee39e4 (diff)
parentbcb628d579a61d0ab0cac4c6cc8a403de5254920 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/Kconfig140
-rw-r--r--drivers/net/wireless/Makefile10
-rw-r--r--drivers/net/wireless/arlan-main.c1887
-rw-r--r--drivers/net/wireless/arlan-proc.c1253
-rw-r--r--drivers/net/wireless/arlan.h539
-rw-r--r--drivers/net/wireless/ath/Kconfig1
-rw-r--r--drivers/net/wireless/ath/ar9170/Kconfig2
-rw-r--r--drivers/net/wireless/ath/ath5k/Kconfig2
-rw-r--r--drivers/net/wireless/ath/ath5k/led.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/Kconfig2
-rw-r--r--drivers/net/wireless/ath/ath9k/ahb.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c669
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h22
-rw-r--r--drivers/net/wireless/ath/ath9k/initvals.h29
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c58
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.c1100
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.h40
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c3
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h3
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c3
-rw-r--r--drivers/net/wireless/b43/Kconfig2
-rw-r--r--drivers/net/wireless/b43/b43.h2
-rw-r--r--drivers/net/wireless/b43/main.c2
-rw-r--r--drivers/net/wireless/b43/phy_lp.c783
-rw-r--r--drivers/net/wireless/b43/phy_lp.h11
-rw-r--r--drivers/net/wireless/b43/xmit.c1
-rw-r--r--drivers/net/wireless/b43legacy/Kconfig2
-rw-r--r--drivers/net/wireless/b43legacy/b43legacy.h2
-rw-r--r--drivers/net/wireless/b43legacy/dma.c17
-rw-r--r--drivers/net/wireless/b43legacy/main.c2
-rw-r--r--drivers/net/wireless/b43legacy/xmit.c1
-rw-r--r--drivers/net/wireless/hostap/Kconfig1
-rw-r--r--drivers/net/wireless/i82586.h413
-rw-r--r--drivers/net/wireless/i82593.h229
-rw-r--r--drivers/net/wireless/ipw2x00/Kconfig6
-rw-r--r--drivers/net/wireless/iwlwifi/Kconfig2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-1000.c4
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-rs.c102
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.h35
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-5000.c12
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-6000.c25
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-rs.c13
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn.c143
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-calib.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-commands.h161
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-core.c236
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-core.h7
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-dev.h1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.c11
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-hcmd.c2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-scan.c1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-sta.c69
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-sta.h1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-tx.c13
-rw-r--r--drivers/net/wireless/iwlwifi/iwl3945-base.c15
-rw-r--r--drivers/net/wireless/iwmc3200wifi/Kconfig2
-rw-r--r--drivers/net/wireless/libertas/Kconfig2
-rw-r--r--drivers/net/wireless/libertas/if_spi.c136
-rw-r--r--drivers/net/wireless/mac80211_hwsim.c67
-rw-r--r--drivers/net/wireless/mwl8k.c1258
-rw-r--r--drivers/net/wireless/netwave_cs.c1389
-rw-r--r--drivers/net/wireless/orinoco/Kconfig2
-rw-r--r--drivers/net/wireless/p54/Kconfig2
-rw-r--r--drivers/net/wireless/p54/eeprom.c31
-rw-r--r--drivers/net/wireless/rt2x00/Kconfig18
-rw-r--r--drivers/net/wireless/rt2x00/Makefile1
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h1816
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c1817
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.h134
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c1908
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.h1780
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c1828
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.h1818
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h43
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00leds.h4
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.h24
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.c2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.h17
-rw-r--r--drivers/net/wireless/rtl818x/rtl8187.h1
-rw-r--r--drivers/net/wireless/rtl818x/rtl8187_dev.c13
-rw-r--r--drivers/net/wireless/strip.c2822
-rw-r--r--drivers/net/wireless/wavelan.c4383
-rw-r--r--drivers/net/wireless/wavelan.h370
-rw-r--r--drivers/net/wireless/wavelan.p.h696
-rw-r--r--drivers/net/wireless/wavelan_cs.c4635
-rw-r--r--drivers/net/wireless/wavelan_cs.h386
-rw-r--r--drivers/net/wireless/wavelan_cs.p.h766
-rw-r--r--drivers/net/wireless/wl12xx/Kconfig3
-rw-r--r--drivers/net/wireless/wl12xx/wl1251_main.c3
-rw-r--r--drivers/net/wireless/wl12xx/wl1271.h3
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_acx.c2
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_boot.c5
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_cmd.c99
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_cmd.h3
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_conf.h8
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_event.c53
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_event.h7
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_init.c7
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_main.c19
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_rx.c2
-rw-r--r--drivers/net/wireless/zd1211rw/Kconfig2
104 files changed, 7596 insertions, 28910 deletions
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index 85f8bf4112c1..56dd6650c97a 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -16,118 +16,9 @@ menuconfig WLAN
16 16
17if WLAN 17if WLAN
18 18
19menuconfig WLAN_PRE80211
20 bool "Wireless LAN (pre-802.11)"
21 depends on NETDEVICES
22 ---help---
23 Say Y if you have any pre-802.11 wireless LAN hardware.
24
25 This option does not affect the kernel build, it only
26 lets you choose drivers.
27
28config STRIP
29 tristate "STRIP (Metricom starmode radio IP)"
30 depends on INET && WLAN_PRE80211
31 select WIRELESS_EXT
32 ---help---
33 Say Y if you have a Metricom radio and intend to use Starmode Radio
34 IP. STRIP is a radio protocol developed for the MosquitoNet project
35 to send Internet traffic using Metricom radios. Metricom radios are
36 small, battery powered, 100kbit/sec packet radio transceivers, about
37 the size and weight of a cellular telephone. (You may also have heard
38 them called "Metricom modems" but we avoid the term "modem" because
39 it misleads many people into thinking that you can plug a Metricom
40 modem into a phone line and use it as a modem.)
41
42 You can use STRIP on any Linux machine with a serial port, although
43 it is obviously most useful for people with laptop computers. If you
44 think you might get a Metricom radio in the future, there is no harm
45 in saying Y to STRIP now, except that it makes the kernel a bit
46 bigger.
47
48 To compile this as a module, choose M here: the module will be
49 called strip.
50
51config ARLAN
52 tristate "Aironet Arlan 655 & IC2200 DS support"
53 depends on ISA && !64BIT && WLAN_PRE80211
54 select WIRELESS_EXT
55 ---help---
56 Aironet makes Arlan, a class of wireless LAN adapters. These use the
57 www.Telxon.com chip, which is also used on several similar cards.
58 This driver is tested on the 655 and IC2200 series cards. Look at
59 <http://www.ylenurme.ee/~elmer/655/> for the latest information.
60
61 The driver is built as two modules, arlan and arlan-proc. The latter
62 is the /proc interface and is not needed most of time.
63
64 On some computers the card ends up in non-valid state after some
65 time. Use a ping-reset script to clear it.
66
67config WAVELAN
68 tristate "AT&T/Lucent old WaveLAN & DEC RoamAbout DS ISA support"
69 depends on ISA && WLAN_PRE80211
70 select WIRELESS_EXT
71 select WEXT_SPY
72 select WEXT_PRIV
73 ---help---
74 The Lucent WaveLAN (formerly NCR and AT&T; or DEC RoamAbout DS) is
75 a Radio LAN (wireless Ethernet-like Local Area Network) using the
76 radio frequencies 900 MHz and 2.4 GHz.
77
78 If you want to use an ISA WaveLAN card under Linux, say Y and read
79 the Ethernet-HOWTO, available from
80 <http://www.tldp.org/docs.html#howto>. Some more specific
81 information is contained in
82 <file:Documentation/networking/wavelan.txt> and in the source code
83 <file:drivers/net/wireless/wavelan.p.h>.
84
85 You will also need the wireless tools package available from
86 <http://www.hpl.hp.com/personal/Jean_Tourrilhes/Linux/Tools.html>.
87 Please read the man pages contained therein.
88
89 To compile this driver as a module, choose M here: the module will be
90 called wavelan.
91
92config PCMCIA_WAVELAN
93 tristate "AT&T/Lucent old WaveLAN Pcmcia wireless support"
94 depends on PCMCIA && WLAN_PRE80211
95 select WIRELESS_EXT
96 select WEXT_SPY
97 select WEXT_PRIV
98 help
99 Say Y here if you intend to attach an AT&T/Lucent Wavelan PCMCIA
100 (PC-card) wireless Ethernet networking card to your computer. This
101 driver is for the non-IEEE-802.11 Wavelan cards.
102
103 To compile this driver as a module, choose M here: the module will be
104 called wavelan_cs. If unsure, say N.
105
106config PCMCIA_NETWAVE
107 tristate "Xircom Netwave AirSurfer Pcmcia wireless support"
108 depends on PCMCIA && WLAN_PRE80211
109 select WIRELESS_EXT
110 select WEXT_PRIV
111 help
112 Say Y here if you intend to attach this type of PCMCIA (PC-card)
113 wireless Ethernet networking card to your computer.
114
115 To compile this driver as a module, choose M here: the module will be
116 called netwave_cs. If unsure, say N.
117
118
119menuconfig WLAN_80211
120 bool "Wireless LAN (IEEE 802.11)"
121 depends on NETDEVICES
122 ---help---
123 Say Y if you have any 802.11 wireless LAN hardware.
124
125 This option does not affect the kernel build, it only
126 lets you choose drivers.
127
128config PCMCIA_RAYCS 19config PCMCIA_RAYCS
129 tristate "Aviator/Raytheon 2.4GHz wireless support" 20 tristate "Aviator/Raytheon 2.4GHz wireless support"
130 depends on PCMCIA && WLAN_80211 21 depends on PCMCIA
131 select WIRELESS_EXT 22 select WIRELESS_EXT
132 select WEXT_SPY 23 select WEXT_SPY
133 select WEXT_PRIV 24 select WEXT_PRIV
@@ -142,7 +33,7 @@ config PCMCIA_RAYCS
142 33
143config LIBERTAS_THINFIRM 34config LIBERTAS_THINFIRM
144 tristate "Marvell 8xxx Libertas WLAN driver support with thin firmware" 35 tristate "Marvell 8xxx Libertas WLAN driver support with thin firmware"
145 depends on WLAN_80211 && MAC80211 36 depends on MAC80211
146 select FW_LOADER 37 select FW_LOADER
147 ---help--- 38 ---help---
148 A library for Marvell Libertas 8xxx devices using thinfirm. 39 A library for Marvell Libertas 8xxx devices using thinfirm.
@@ -155,7 +46,7 @@ config LIBERTAS_THINFIRM_USB
155 46
156config AIRO 47config AIRO
157 tristate "Cisco/Aironet 34X/35X/4500/4800 ISA and PCI cards" 48 tristate "Cisco/Aironet 34X/35X/4500/4800 ISA and PCI cards"
158 depends on ISA_DMA_API && WLAN_80211 && (PCI || BROKEN) 49 depends on ISA_DMA_API && (PCI || BROKEN)
159 select WIRELESS_EXT 50 select WIRELESS_EXT
160 select CRYPTO 51 select CRYPTO
161 select WEXT_SPY 52 select WEXT_SPY
@@ -175,7 +66,7 @@ config AIRO
175 66
176config ATMEL 67config ATMEL
177 tristate "Atmel at76c50x chipset 802.11b support" 68 tristate "Atmel at76c50x chipset 802.11b support"
178 depends on (PCI || PCMCIA) && WLAN_80211 69 depends on (PCI || PCMCIA)
179 select WIRELESS_EXT 70 select WIRELESS_EXT
180 select WEXT_PRIV 71 select WEXT_PRIV
181 select FW_LOADER 72 select FW_LOADER
@@ -210,7 +101,7 @@ config PCMCIA_ATMEL
210 101
211config AT76C50X_USB 102config AT76C50X_USB
212 tristate "Atmel at76c503/at76c505/at76c505a USB cards" 103 tristate "Atmel at76c503/at76c505/at76c505a USB cards"
213 depends on MAC80211 && WLAN_80211 && USB 104 depends on MAC80211 && USB
214 select FW_LOADER 105 select FW_LOADER
215 ---help--- 106 ---help---
216 Enable support for USB Wireless devices using Atmel at76c503, 107 Enable support for USB Wireless devices using Atmel at76c503,
@@ -218,8 +109,9 @@ config AT76C50X_USB
218 109
219config AIRO_CS 110config AIRO_CS
220 tristate "Cisco/Aironet 34X/35X/4500/4800 PCMCIA cards" 111 tristate "Cisco/Aironet 34X/35X/4500/4800 PCMCIA cards"
221 depends on PCMCIA && (BROKEN || !M32R) && WLAN_80211 112 depends on PCMCIA && (BROKEN || !M32R)
222 select WIRELESS_EXT 113 select WIRELESS_EXT
114 select WEXT_SPY
223 select CRYPTO 115 select CRYPTO
224 select CRYPTO_AES 116 select CRYPTO_AES
225 ---help--- 117 ---help---
@@ -238,7 +130,7 @@ config AIRO_CS
238 130
239config PCMCIA_WL3501 131config PCMCIA_WL3501
240 tristate "Planet WL3501 PCMCIA cards" 132 tristate "Planet WL3501 PCMCIA cards"
241 depends on EXPERIMENTAL && PCMCIA && WLAN_80211 133 depends on EXPERIMENTAL && PCMCIA
242 select WIRELESS_EXT 134 select WIRELESS_EXT
243 select WEXT_SPY 135 select WEXT_SPY
244 help 136 help
@@ -248,7 +140,7 @@ config PCMCIA_WL3501
248 140
249config PRISM54 141config PRISM54
250 tristate 'Intersil Prism GT/Duette/Indigo PCI/Cardbus (DEPRECATED)' 142 tristate 'Intersil Prism GT/Duette/Indigo PCI/Cardbus (DEPRECATED)'
251 depends on PCI && EXPERIMENTAL && WLAN_80211 143 depends on PCI && EXPERIMENTAL
252 select WIRELESS_EXT 144 select WIRELESS_EXT
253 select WEXT_SPY 145 select WEXT_SPY
254 select WEXT_PRIV 146 select WEXT_PRIV
@@ -272,7 +164,7 @@ config PRISM54
272 164
273config USB_ZD1201 165config USB_ZD1201
274 tristate "USB ZD1201 based Wireless device support" 166 tristate "USB ZD1201 based Wireless device support"
275 depends on USB && WLAN_80211 167 depends on USB
276 select WIRELESS_EXT 168 select WIRELESS_EXT
277 select WEXT_PRIV 169 select WEXT_PRIV
278 select FW_LOADER 170 select FW_LOADER
@@ -291,7 +183,7 @@ config USB_ZD1201
291 183
292config USB_NET_RNDIS_WLAN 184config USB_NET_RNDIS_WLAN
293 tristate "Wireless RNDIS USB support" 185 tristate "Wireless RNDIS USB support"
294 depends on USB && WLAN_80211 && EXPERIMENTAL 186 depends on USB && EXPERIMENTAL
295 depends on CFG80211 187 depends on CFG80211
296 select USB_USBNET 188 select USB_USBNET
297 select USB_NET_CDCETHER 189 select USB_NET_CDCETHER
@@ -319,7 +211,7 @@ config USB_NET_RNDIS_WLAN
319 211
320config RTL8180 212config RTL8180
321 tristate "Realtek 8180/8185 PCI support" 213 tristate "Realtek 8180/8185 PCI support"
322 depends on MAC80211 && PCI && WLAN_80211 && EXPERIMENTAL 214 depends on MAC80211 && PCI && EXPERIMENTAL
323 select EEPROM_93CX6 215 select EEPROM_93CX6
324 ---help--- 216 ---help---
325 This is a driver for RTL8180 and RTL8185 based cards. 217 This is a driver for RTL8180 and RTL8185 based cards.
@@ -375,7 +267,7 @@ config RTL8180
375 267
376config RTL8187 268config RTL8187
377 tristate "Realtek 8187 and 8187B USB support" 269 tristate "Realtek 8187 and 8187B USB support"
378 depends on MAC80211 && USB && WLAN_80211 270 depends on MAC80211 && USB
379 select EEPROM_93CX6 271 select EEPROM_93CX6
380 ---help--- 272 ---help---
381 This is a driver for RTL8187 and RTL8187B based cards. 273 This is a driver for RTL8187 and RTL8187B based cards.
@@ -404,7 +296,7 @@ config RTL8187_LEDS
404 296
405config ADM8211 297config ADM8211
406 tristate "ADMtek ADM8211 support" 298 tristate "ADMtek ADM8211 support"
407 depends on MAC80211 && PCI && WLAN_80211 && EXPERIMENTAL 299 depends on MAC80211 && PCI && EXPERIMENTAL
408 select CRC32 300 select CRC32
409 select EEPROM_93CX6 301 select EEPROM_93CX6
410 ---help--- 302 ---help---
@@ -431,7 +323,7 @@ config ADM8211
431 323
432config MAC80211_HWSIM 324config MAC80211_HWSIM
433 tristate "Simulated radio testing tool for mac80211" 325 tristate "Simulated radio testing tool for mac80211"
434 depends on MAC80211 && WLAN_80211 326 depends on MAC80211
435 ---help--- 327 ---help---
436 This driver is a developer testing tool that can be used to test 328 This driver is a developer testing tool that can be used to test
437 IEEE 802.11 networking stack (mac80211) functionality. This is not 329 IEEE 802.11 networking stack (mac80211) functionality. This is not
@@ -444,7 +336,7 @@ config MAC80211_HWSIM
444 336
445config MWL8K 337config MWL8K
446 tristate "Marvell 88W8xxx PCI/PCIe Wireless support" 338 tristate "Marvell 88W8xxx PCI/PCIe Wireless support"
447 depends on MAC80211 && PCI && WLAN_80211 && EXPERIMENTAL 339 depends on MAC80211 && PCI && EXPERIMENTAL
448 ---help--- 340 ---help---
449 This driver supports Marvell TOPDOG 802.11 wireless cards. 341 This driver supports Marvell TOPDOG 802.11 wireless cards.
450 342
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
index 7a4647e78fd3..5d4ce4d2b32b 100644
--- a/drivers/net/wireless/Makefile
+++ b/drivers/net/wireless/Makefile
@@ -5,16 +5,6 @@
5obj-$(CONFIG_IPW2100) += ipw2x00/ 5obj-$(CONFIG_IPW2100) += ipw2x00/
6obj-$(CONFIG_IPW2200) += ipw2x00/ 6obj-$(CONFIG_IPW2200) += ipw2x00/
7 7
8obj-$(CONFIG_STRIP) += strip.o
9obj-$(CONFIG_ARLAN) += arlan.o
10
11arlan-objs := arlan-main.o arlan-proc.o
12
13# Obsolete cards
14obj-$(CONFIG_WAVELAN) += wavelan.o
15obj-$(CONFIG_PCMCIA_NETWAVE) += netwave_cs.o
16obj-$(CONFIG_PCMCIA_WAVELAN) += wavelan_cs.o
17
18obj-$(CONFIG_HERMES) += orinoco/ 8obj-$(CONFIG_HERMES) += orinoco/
19 9
20obj-$(CONFIG_AIRO) += airo.o 10obj-$(CONFIG_AIRO) += airo.o
diff --git a/drivers/net/wireless/arlan-main.c b/drivers/net/wireless/arlan-main.c
deleted file mode 100644
index 921a082487a1..000000000000
--- a/drivers/net/wireless/arlan-main.c
+++ /dev/null
@@ -1,1887 +0,0 @@
1/*
2 * Copyright (C) 1997 Cullen Jennings
3 * Copyright (C) 1998 Elmer Joandiu, elmer@ylenurme.ee
4 * GNU General Public License applies
5 * This module provides support for the Arlan 655 card made by Aironet
6 */
7
8#include "arlan.h"
9
10#if BITS_PER_LONG != 32
11# error FIXME: this driver requires a 32-bit platform
12#endif
13
14static const char *arlan_version = "C.Jennigs 97 & Elmer.Joandi@ut.ee Oct'98, http://www.ylenurme.ee/~elmer/655/";
15
16struct net_device *arlan_device[MAX_ARLANS];
17
18static int SID = SIDUNKNOWN;
19static int radioNodeId = radioNodeIdUNKNOWN;
20static char encryptionKey[12] = {'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h'};
21int arlan_debug = debugUNKNOWN;
22static int spreadingCode = spreadingCodeUNKNOWN;
23static int channelNumber = channelNumberUNKNOWN;
24static int channelSet = channelSetUNKNOWN;
25static int systemId = systemIdUNKNOWN;
26static int registrationMode = registrationModeUNKNOWN;
27static int keyStart;
28static int tx_delay_ms;
29static int retries = 5;
30static int tx_queue_len = 1;
31static int arlan_EEPROM_bad;
32
33#ifdef ARLAN_DEBUGGING
34
35static int testMemory = testMemoryUNKNOWN;
36static int irq = irqUNKNOWN;
37static int txScrambled = 1;
38static int mdebug;
39
40module_param(irq, int, 0);
41module_param(mdebug, int, 0);
42module_param(testMemory, int, 0);
43module_param(txScrambled, int, 0);
44MODULE_PARM_DESC(irq, "(unused)");
45MODULE_PARM_DESC(testMemory, "(unused)");
46MODULE_PARM_DESC(mdebug, "Arlan multicast debugging (0-1)");
47#endif
48
49module_param_named(debug, arlan_debug, int, 0);
50module_param(spreadingCode, int, 0);
51module_param(channelNumber, int, 0);
52module_param(channelSet, int, 0);
53module_param(systemId, int, 0);
54module_param(registrationMode, int, 0);
55module_param(radioNodeId, int, 0);
56module_param(SID, int, 0);
57module_param(keyStart, int, 0);
58module_param(tx_delay_ms, int, 0);
59module_param(retries, int, 0);
60module_param(tx_queue_len, int, 0);
61module_param_named(EEPROM_bad, arlan_EEPROM_bad, int, 0);
62MODULE_PARM_DESC(debug, "Arlan debug enable (0-1)");
63MODULE_PARM_DESC(retries, "Arlan maximum packet retransmisions");
64#ifdef ARLAN_ENTRY_EXIT_DEBUGGING
65static int arlan_entry_debug;
66static int arlan_exit_debug;
67static int arlan_entry_and_exit_debug;
68module_param_named(entry_debug, arlan_entry_debug, int, 0);
69module_param_named(exit_debug, arlan_exit_debug, int, 0);
70module_param_named(entry_and_exit_debug, arlan_entry_and_exit_debug, int, 0);
71MODULE_PARM_DESC(entry_debug, "Arlan driver function entry debugging");
72MODULE_PARM_DESC(exit_debug, "Arlan driver function exit debugging");
73MODULE_PARM_DESC(entry_and_exit_debug, "Arlan driver function entry and exit debugging");
74#endif
75
76struct arlan_conf_stru arlan_conf[MAX_ARLANS];
77static int arlans_found;
78
79static int arlan_open(struct net_device *dev);
80static netdev_tx_t arlan_tx(struct sk_buff *skb, struct net_device *dev);
81static irqreturn_t arlan_interrupt(int irq, void *dev_id);
82static int arlan_close(struct net_device *dev);
83static struct net_device_stats *
84 arlan_statistics (struct net_device *dev);
85static void arlan_set_multicast (struct net_device *dev);
86static int arlan_hw_tx (struct net_device* dev, char *buf, int length );
87static int arlan_hw_config (struct net_device * dev);
88static void arlan_tx_done_interrupt (struct net_device * dev, int status);
89static void arlan_rx_interrupt (struct net_device * dev, u_char rxStatus, u_short, u_short);
90static void arlan_process_interrupt (struct net_device * dev);
91static void arlan_tx_timeout (struct net_device *dev);
92
93static inline long us2ticks(int us)
94{
95 return us * (1000000 / HZ);
96}
97
98
99#ifdef ARLAN_ENTRY_EXIT_DEBUGGING
100#define ARLAN_DEBUG_ENTRY(name) \
101 {\
102 struct timeval timev;\
103 do_gettimeofday(&timev);\
104 if (arlan_entry_debug || arlan_entry_and_exit_debug)\
105 printk("--->>>" name " %ld " "\n",((long int) timev.tv_sec * 1000000 + timev.tv_usec));\
106 }
107#define ARLAN_DEBUG_EXIT(name) \
108 {\
109 struct timeval timev;\
110 do_gettimeofday(&timev);\
111 if (arlan_exit_debug || arlan_entry_and_exit_debug)\
112 printk("<<<---" name " %ld " "\n",((long int) timev.tv_sec * 1000000 + timev.tv_usec) );\
113 }
114#else
115#define ARLAN_DEBUG_ENTRY(name)
116#define ARLAN_DEBUG_EXIT(name)
117#endif
118
119
120#define arlan_interrupt_ack(dev)\
121 clearClearInterrupt(dev);\
122 setClearInterrupt(dev);
123
124static inline int arlan_drop_tx(struct net_device *dev)
125{
126 struct arlan_private *priv = netdev_priv(dev);
127
128 dev->stats.tx_errors++;
129 if (priv->Conf->tx_delay_ms)
130 {
131 priv->tx_done_delayed = jiffies + priv->Conf->tx_delay_ms * HZ / 1000 + 1;
132 }
133 else
134 {
135 priv->waiting_command_mask &= ~ARLAN_COMMAND_TX;
136 TXHEAD(dev).offset = 0;
137 TXTAIL(dev).offset = 0;
138 priv->txLast = 0;
139 priv->bad = 0;
140 if (!priv->under_reset && !priv->under_config)
141 netif_wake_queue (dev);
142 }
143 return 1;
144}
145
146
147int arlan_command(struct net_device *dev, int command_p)
148{
149 struct arlan_private *priv = netdev_priv(dev);
150 volatile struct arlan_shmem __iomem *arlan = priv->card;
151 struct arlan_conf_stru *conf = priv->Conf;
152 int udelayed = 0;
153 int i = 0;
154 unsigned long flags;
155
156 ARLAN_DEBUG_ENTRY("arlan_command");
157
158 if (priv->card_polling_interval)
159 priv->card_polling_interval = 1;
160
161 if (arlan_debug & ARLAN_DEBUG_CHAIN_LOCKS)
162 printk(KERN_DEBUG "arlan_command, %lx commandByte %x waiting %lx incoming %x \n",
163 jiffies, READSHMB(arlan->commandByte),
164 priv->waiting_command_mask, command_p);
165
166 priv->waiting_command_mask |= command_p;
167
168 if (priv->waiting_command_mask & ARLAN_COMMAND_RESET)
169 if (time_after(jiffies, priv->lastReset + 5 * HZ))
170 priv->waiting_command_mask &= ~ARLAN_COMMAND_RESET;
171
172 if (priv->waiting_command_mask & ARLAN_COMMAND_INT_ACK)
173 {
174 arlan_interrupt_ack(dev);
175 priv->waiting_command_mask &= ~ARLAN_COMMAND_INT_ACK;
176 }
177 if (priv->waiting_command_mask & ARLAN_COMMAND_INT_ENABLE)
178 {
179 setInterruptEnable(dev);
180 priv->waiting_command_mask &= ~ARLAN_COMMAND_INT_ENABLE;
181 }
182
183 /* Card access serializing lock */
184 spin_lock_irqsave(&priv->lock, flags);
185
186 /* Check cards status and waiting */
187
188 if (priv->waiting_command_mask & (ARLAN_COMMAND_LONG_WAIT_NOW | ARLAN_COMMAND_WAIT_NOW))
189 {
190 while (priv->waiting_command_mask & (ARLAN_COMMAND_LONG_WAIT_NOW | ARLAN_COMMAND_WAIT_NOW))
191 {
192 if (READSHMB(arlan->resetFlag) ||
193 READSHMB(arlan->commandByte)) /* ||
194 (readControlRegister(dev) & ARLAN_ACCESS))
195 */
196 udelay(40);
197 else
198 priv->waiting_command_mask &= ~(ARLAN_COMMAND_LONG_WAIT_NOW | ARLAN_COMMAND_WAIT_NOW);
199
200 udelayed++;
201
202 if (priv->waiting_command_mask & ARLAN_COMMAND_LONG_WAIT_NOW)
203 {
204 if (udelayed * 40 > 1000000)
205 {
206 printk(KERN_ERR "%s long wait too long \n", dev->name);
207 priv->waiting_command_mask |= ARLAN_COMMAND_RESET;
208 break;
209 }
210 }
211 else if (priv->waiting_command_mask & ARLAN_COMMAND_WAIT_NOW)
212 {
213 if (udelayed * 40 > 1000)
214 {
215 printk(KERN_ERR "%s short wait too long \n", dev->name);
216 goto bad_end;
217 }
218 }
219 }
220 }
221 else
222 {
223 i = 0;
224 while ((READSHMB(arlan->resetFlag) ||
225 READSHMB(arlan->commandByte)) &&
226 conf->pre_Command_Wait > (i++) * 10)
227 udelay(10);
228
229
230 if ((READSHMB(arlan->resetFlag) ||
231 READSHMB(arlan->commandByte)) &&
232 !(priv->waiting_command_mask & ARLAN_COMMAND_RESET))
233 {
234 goto card_busy_end;
235 }
236 }
237 if (priv->waiting_command_mask & ARLAN_COMMAND_RESET)
238 priv->under_reset = 1;
239 if (priv->waiting_command_mask & ARLAN_COMMAND_CONF)
240 priv->under_config = 1;
241
242 /* Issuing command */
243 arlan_lock_card_access(dev);
244 if (priv->waiting_command_mask & ARLAN_COMMAND_POWERUP)
245 {
246 // if (readControlRegister(dev) & (ARLAN_ACCESS && ARLAN_POWER))
247 setPowerOn(dev);
248 arlan_interrupt_lancpu(dev);
249 priv->waiting_command_mask &= ~ARLAN_COMMAND_POWERUP;
250 priv->waiting_command_mask |= ARLAN_COMMAND_RESET;
251 priv->card_polling_interval = HZ / 10;
252 }
253 else if (priv->waiting_command_mask & ARLAN_COMMAND_ACTIVATE)
254 {
255 WRITESHMB(arlan->commandByte, ARLAN_COM_ACTIVATE);
256 arlan_interrupt_lancpu(dev);
257 priv->waiting_command_mask &= ~ARLAN_COMMAND_ACTIVATE;
258 priv->card_polling_interval = HZ / 10;
259 }
260 else if (priv->waiting_command_mask & ARLAN_COMMAND_RX_ABORT)
261 {
262 if (priv->rx_command_given)
263 {
264 WRITESHMB(arlan->commandByte, ARLAN_COM_RX_ABORT);
265 arlan_interrupt_lancpu(dev);
266 priv->rx_command_given = 0;
267 }
268 priv->waiting_command_mask &= ~ARLAN_COMMAND_RX_ABORT;
269 priv->card_polling_interval = 1;
270 }
271 else if (priv->waiting_command_mask & ARLAN_COMMAND_TX_ABORT)
272 {
273 if (priv->tx_command_given)
274 {
275 WRITESHMB(arlan->commandByte, ARLAN_COM_TX_ABORT);
276 arlan_interrupt_lancpu(dev);
277 priv->tx_command_given = 0;
278 }
279 priv->waiting_command_mask &= ~ARLAN_COMMAND_TX_ABORT;
280 priv->card_polling_interval = 1;
281 }
282 else if (priv->waiting_command_mask & ARLAN_COMMAND_RESET)
283 {
284 priv->under_reset=1;
285 netif_stop_queue (dev);
286
287 arlan_drop_tx(dev);
288 if (priv->tx_command_given || priv->rx_command_given)
289 {
290 printk(KERN_ERR "%s: Reset under tx or rx command \n", dev->name);
291 }
292 netif_stop_queue (dev);
293 if (arlan_debug & ARLAN_DEBUG_RESET)
294 printk(KERN_ERR "%s: Doing chip reset\n", dev->name);
295 priv->lastReset = jiffies;
296 WRITESHM(arlan->commandByte, 0, u_char);
297 /* hold card in reset state */
298 setHardwareReset(dev);
299 /* set reset flag and then release reset */
300 WRITESHM(arlan->resetFlag, 0xff, u_char);
301 clearChannelAttention(dev);
302 clearHardwareReset(dev);
303 priv->card_polling_interval = HZ / 4;
304 priv->waiting_command_mask &= ~ARLAN_COMMAND_RESET;
305 priv->waiting_command_mask |= ARLAN_COMMAND_INT_RACK;
306// priv->waiting_command_mask |= ARLAN_COMMAND_INT_RENABLE;
307// priv->waiting_command_mask |= ARLAN_COMMAND_RX;
308 }
309 else if (priv->waiting_command_mask & ARLAN_COMMAND_INT_RACK)
310 {
311 clearHardwareReset(dev);
312 clearClearInterrupt(dev);
313 setClearInterrupt(dev);
314 setInterruptEnable(dev);
315 priv->waiting_command_mask &= ~ARLAN_COMMAND_INT_RACK;
316 priv->waiting_command_mask |= ARLAN_COMMAND_CONF;
317 priv->under_config = 1;
318 priv->under_reset = 0;
319 }
320 else if (priv->waiting_command_mask & ARLAN_COMMAND_INT_RENABLE)
321 {
322 setInterruptEnable(dev);
323 priv->waiting_command_mask &= ~ARLAN_COMMAND_INT_RENABLE;
324 }
325 else if (priv->waiting_command_mask & ARLAN_COMMAND_CONF)
326 {
327 if (priv->tx_command_given || priv->rx_command_given)
328 {
329 printk(KERN_ERR "%s: Reset under tx or rx command \n", dev->name);
330 }
331 arlan_drop_tx(dev);
332 setInterruptEnable(dev);
333 arlan_hw_config(dev);
334 arlan_interrupt_lancpu(dev);
335 priv->waiting_command_mask &= ~ARLAN_COMMAND_CONF;
336 priv->card_polling_interval = HZ / 10;
337// priv->waiting_command_mask |= ARLAN_COMMAND_INT_RACK;
338// priv->waiting_command_mask |= ARLAN_COMMAND_INT_ENABLE;
339 priv->waiting_command_mask |= ARLAN_COMMAND_CONF_WAIT;
340 }
341 else if (priv->waiting_command_mask & ARLAN_COMMAND_CONF_WAIT)
342 {
343 if (READSHMB(arlan->configuredStatusFlag) != 0 &&
344 READSHMB(arlan->diagnosticInfo) == 0xff)
345 {
346 priv->waiting_command_mask &= ~ARLAN_COMMAND_CONF_WAIT;
347 priv->waiting_command_mask |= ARLAN_COMMAND_RX;
348 priv->waiting_command_mask |= ARLAN_COMMAND_TBUSY_CLEAR;
349 priv->card_polling_interval = HZ / 10;
350 priv->tx_command_given = 0;
351 priv->under_config = 0;
352 }
353 else
354 {
355 priv->card_polling_interval = 1;
356 if (arlan_debug & ARLAN_DEBUG_TIMING)
357 printk(KERN_ERR "configure delayed \n");
358 }
359 }
360 else if (priv->waiting_command_mask & ARLAN_COMMAND_RX)
361 {
362 if (!registrationBad(dev))
363 {
364 setInterruptEnable(dev);
365 memset_io(arlan->commandParameter, 0, 0xf);
366 WRITESHMB(arlan->commandByte, ARLAN_COM_INT | ARLAN_COM_RX_ENABLE);
367 WRITESHMB(arlan->commandParameter[0], conf->rxParameter);
368 arlan_interrupt_lancpu(dev);
369 priv->rx_command_given = 0; // mnjah, bad
370 priv->waiting_command_mask &= ~ARLAN_COMMAND_RX;
371 priv->card_polling_interval = 1;
372 }
373 else
374 priv->card_polling_interval = 2;
375 }
376 else if (priv->waiting_command_mask & ARLAN_COMMAND_TBUSY_CLEAR)
377 {
378 if ( !registrationBad(dev) &&
379 (netif_queue_stopped(dev) || !netif_running(dev)) )
380 {
381 priv->waiting_command_mask &= ~ARLAN_COMMAND_TBUSY_CLEAR;
382 netif_wake_queue (dev);
383 }
384 }
385 else if (priv->waiting_command_mask & ARLAN_COMMAND_TX)
386 {
387 if (!test_and_set_bit(0, (void *) &priv->tx_command_given))
388 {
389 if (time_after(jiffies,
390 priv->tx_last_sent + us2ticks(conf->rx_tweak1))
391 || time_before(jiffies,
392 priv->last_rx_int_ack_time + us2ticks(conf->rx_tweak2)))
393 {
394 setInterruptEnable(dev);
395 memset_io(arlan->commandParameter, 0, 0xf);
396 WRITESHMB(arlan->commandByte, ARLAN_COM_TX_ENABLE | ARLAN_COM_INT);
397 memcpy_toio(arlan->commandParameter, &TXLAST(dev), 14);
398// for ( i=1 ; i < 15 ; i++) printk("%02x:",READSHMB(arlan->commandParameter[i]));
399 priv->tx_last_sent = jiffies;
400 arlan_interrupt_lancpu(dev);
401 priv->tx_command_given = 1;
402 priv->waiting_command_mask &= ~ARLAN_COMMAND_TX;
403 priv->card_polling_interval = 1;
404 }
405 else
406 {
407 priv->tx_command_given = 0;
408 priv->card_polling_interval = 1;
409 }
410 }
411 else if (arlan_debug & ARLAN_DEBUG_CHAIN_LOCKS)
412 printk(KERN_ERR "tx command when tx chain locked \n");
413 }
414 else if (priv->waiting_command_mask & ARLAN_COMMAND_NOOPINT)
415 {
416 {
417 WRITESHMB(arlan->commandByte, ARLAN_COM_NOP | ARLAN_COM_INT);
418 }
419 arlan_interrupt_lancpu(dev);
420 priv->waiting_command_mask &= ~ARLAN_COMMAND_NOOPINT;
421 priv->card_polling_interval = HZ / 3;
422 }
423 else if (priv->waiting_command_mask & ARLAN_COMMAND_NOOP)
424 {
425 WRITESHMB(arlan->commandByte, ARLAN_COM_NOP);
426 arlan_interrupt_lancpu(dev);
427 priv->waiting_command_mask &= ~ARLAN_COMMAND_NOOP;
428 priv->card_polling_interval = HZ / 3;
429 }
430 else if (priv->waiting_command_mask & ARLAN_COMMAND_SLOW_POLL)
431 {
432 WRITESHMB(arlan->commandByte, ARLAN_COM_GOTO_SLOW_POLL);
433 arlan_interrupt_lancpu(dev);
434 priv->waiting_command_mask &= ~ARLAN_COMMAND_SLOW_POLL;
435 priv->card_polling_interval = HZ / 3;
436 }
437 else if (priv->waiting_command_mask & ARLAN_COMMAND_POWERDOWN)
438 {
439 setPowerOff(dev);
440 if (arlan_debug & ARLAN_DEBUG_CARD_STATE)
441 printk(KERN_WARNING "%s: Arlan Going Standby\n", dev->name);
442 priv->waiting_command_mask &= ~ARLAN_COMMAND_POWERDOWN;
443 priv->card_polling_interval = 3 * HZ;
444 }
445 arlan_unlock_card_access(dev);
446 for (i = 0; READSHMB(arlan->commandByte) && i < 20; i++)
447 udelay(10);
448 if (READSHMB(arlan->commandByte))
449 if (arlan_debug & ARLAN_DEBUG_CARD_STATE)
450 printk(KERN_ERR "card busy leaving command %lx\n", priv->waiting_command_mask);
451
452 spin_unlock_irqrestore(&priv->lock, flags);
453 ARLAN_DEBUG_EXIT("arlan_command");
454 priv->last_command_buff_free_time = jiffies;
455 return 0;
456
457card_busy_end:
458 if (time_after(jiffies, priv->last_command_buff_free_time + HZ))
459 priv->waiting_command_mask |= ARLAN_COMMAND_CLEAN_AND_RESET;
460
461 if (arlan_debug & ARLAN_DEBUG_CARD_STATE)
462 printk(KERN_ERR "%s arlan_command card busy end \n", dev->name);
463 spin_unlock_irqrestore(&priv->lock, flags);
464 ARLAN_DEBUG_EXIT("arlan_command");
465 return 1;
466
467bad_end:
468 printk(KERN_ERR "%s arlan_command bad end \n", dev->name);
469
470 spin_unlock_irqrestore(&priv->lock, flags);
471 ARLAN_DEBUG_EXIT("arlan_command");
472
473 return -1;
474}
475
476static inline void arlan_command_process(struct net_device *dev)
477{
478 struct arlan_private *priv = netdev_priv(dev);
479
480 int times = 0;
481 while (priv->waiting_command_mask && times < 8)
482 {
483 if (priv->waiting_command_mask)
484 {
485 if (arlan_command(dev, 0))
486 break;
487 times++;
488 }
489 /* if long command, we won't repeat trying */ ;
490 if (priv->card_polling_interval > 1)
491 break;
492 times++;
493 }
494}
495
496
497static inline void arlan_retransmit_now(struct net_device *dev)
498{
499 struct arlan_private *priv = netdev_priv(dev);
500
501
502 ARLAN_DEBUG_ENTRY("arlan_retransmit_now");
503 if (TXLAST(dev).offset == 0)
504 {
505 if (TXHEAD(dev).offset)
506 {
507 priv->txLast = 0;
508 IFDEBUG(ARLAN_DEBUG_TX_CHAIN) printk(KERN_DEBUG "TX buff switch to head \n");
509
510 }
511 else if (TXTAIL(dev).offset)
512 {
513 IFDEBUG(ARLAN_DEBUG_TX_CHAIN) printk(KERN_DEBUG "TX buff switch to tail \n");
514 priv->txLast = 1;
515 }
516 else
517 IFDEBUG(ARLAN_DEBUG_TX_CHAIN) printk(KERN_ERR "ReTransmit buff empty");
518 netif_wake_queue (dev);
519 return;
520
521 }
522 arlan_command(dev, ARLAN_COMMAND_TX);
523
524 priv->Conf->driverRetransmissions++;
525 priv->retransmissions++;
526
527 IFDEBUG(ARLAN_DEBUG_TX_CHAIN) printk("Retransmit %d bytes \n", TXLAST(dev).length);
528
529 ARLAN_DEBUG_EXIT("arlan_retransmit_now");
530}
531
532
533
534static void arlan_registration_timer(unsigned long data)
535{
536 struct net_device *dev = (struct net_device *) data;
537 struct arlan_private *priv = netdev_priv(dev);
538 int bh_mark_needed = 0;
539 int next_tick = 1;
540 long lostTime = ((long)jiffies - (long)priv->registrationLastSeen)
541 * (1000/HZ);
542
543 if (registrationBad(dev))
544 {
545 priv->registrationLostCount++;
546 if (lostTime > 7000 && lostTime < 7200)
547 {
548 printk(KERN_NOTICE "%s registration Lost \n", dev->name);
549 }
550 if (lostTime / priv->reRegisterExp > 2000)
551 arlan_command(dev, ARLAN_COMMAND_CLEAN_AND_CONF);
552 if (lostTime / (priv->reRegisterExp) > 3500)
553 arlan_command(dev, ARLAN_COMMAND_CLEAN_AND_RESET);
554 if (priv->reRegisterExp < 400)
555 priv->reRegisterExp += 2;
556 if (lostTime > 7200)
557 {
558 next_tick = HZ;
559 arlan_command(dev, ARLAN_COMMAND_CLEAN_AND_RESET);
560 }
561 }
562 else
563 {
564 if (priv->Conf->registrationMode && lostTime > 10000 &&
565 priv->registrationLostCount)
566 {
567 printk(KERN_NOTICE "%s registration is back after %ld milliseconds\n",
568 dev->name, lostTime);
569 }
570 priv->registrationLastSeen = jiffies;
571 priv->registrationLostCount = 0;
572 priv->reRegisterExp = 1;
573 if (!netif_running(dev) )
574 netif_wake_queue(dev);
575 if (time_after(priv->tx_last_sent,priv->tx_last_cleared) &&
576 time_after(jiffies, priv->tx_last_sent * 5*HZ) ){
577 arlan_command(dev, ARLAN_COMMAND_CLEAN_AND_RESET);
578 priv->tx_last_cleared = jiffies;
579 }
580 }
581
582
583 if (!registrationBad(dev) && priv->ReTransmitRequested)
584 {
585 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
586 printk(KERN_ERR "Retransmit from timer \n");
587 priv->ReTransmitRequested = 0;
588 arlan_retransmit_now(dev);
589 }
590 if (!registrationBad(dev) &&
591 time_after(jiffies, priv->tx_done_delayed) &&
592 priv->tx_done_delayed != 0)
593 {
594 TXLAST(dev).offset = 0;
595 if (priv->txLast)
596 priv->txLast = 0;
597 else if (TXTAIL(dev).offset)
598 priv->txLast = 1;
599 if (TXLAST(dev).offset)
600 {
601 arlan_retransmit_now(dev);
602 dev->trans_start = jiffies;
603 }
604 if (!(TXHEAD(dev).offset && TXTAIL(dev).offset))
605 {
606 netif_wake_queue (dev);
607 }
608 priv->tx_done_delayed = 0;
609 bh_mark_needed = 1;
610 }
611 if (bh_mark_needed)
612 {
613 netif_wake_queue (dev);
614 }
615 arlan_process_interrupt(dev);
616
617 if (next_tick < priv->card_polling_interval)
618 next_tick = priv->card_polling_interval;
619
620 priv->timer.expires = jiffies + next_tick;
621
622 add_timer(&priv->timer);
623}
624
625
626#ifdef ARLAN_DEBUGGING
627
628static void arlan_print_registers(struct net_device *dev, int line)
629{
630 struct arlan_private *priv = netdev_priv(dev);
631 volatile struct arlan_shmem *arlan = priv->card;
632
633 u_char hostcpuLock, lancpuLock, controlRegister, cntrlRegImage,
634 txStatus, rxStatus, interruptInProgress, commandByte;
635
636
637 ARLAN_DEBUG_ENTRY("arlan_print_registers");
638 READSHM(interruptInProgress, arlan->interruptInProgress, u_char);
639 READSHM(hostcpuLock, arlan->hostcpuLock, u_char);
640 READSHM(lancpuLock, arlan->lancpuLock, u_char);
641 READSHM(controlRegister, arlan->controlRegister, u_char);
642 READSHM(cntrlRegImage, arlan->cntrlRegImage, u_char);
643 READSHM(txStatus, arlan->txStatus, u_char);
644 READSHM(rxStatus, arlan->rxStatus, u_char);
645 READSHM(commandByte, arlan->commandByte, u_char);
646
647 printk(KERN_WARNING "line %04d IP %02x HL %02x LL %02x CB %02x CR %02x CRI %02x TX %02x RX %02x\n",
648 line, interruptInProgress, hostcpuLock, lancpuLock, commandByte,
649 controlRegister, cntrlRegImage, txStatus, rxStatus);
650
651 ARLAN_DEBUG_EXIT("arlan_print_registers");
652}
653#endif
654
655
656static int arlan_hw_tx(struct net_device *dev, char *buf, int length)
657{
658 int i;
659
660 struct arlan_private *priv = netdev_priv(dev);
661 volatile struct arlan_shmem __iomem *arlan = priv->card;
662 struct arlan_conf_stru *conf = priv->Conf;
663
664 int tailStarts = 0x800;
665 int headEnds = 0x0;
666
667
668 ARLAN_DEBUG_ENTRY("arlan_hw_tx");
669 if (TXHEAD(dev).offset)
670 headEnds = (((TXHEAD(dev).offset + TXHEAD(dev).length - offsetof(struct arlan_shmem, txBuffer)) / 64) + 1) * 64;
671 if (TXTAIL(dev).offset)
672 tailStarts = 0x800 - (((TXTAIL(dev).offset - offsetof(struct arlan_shmem, txBuffer)) / 64) + 2) * 64;
673
674
675 if (!TXHEAD(dev).offset && length < tailStarts)
676 {
677 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
678 printk(KERN_ERR "TXHEAD insert, tailStart %d\n", tailStarts);
679
680 TXHEAD(dev).offset =
681 offsetof(struct arlan_shmem, txBuffer);
682 TXHEAD(dev).length = length - ARLAN_FAKE_HDR_LEN;
683 for (i = 0; i < 6; i++)
684 TXHEAD(dev).dest[i] = buf[i];
685 TXHEAD(dev).clear = conf->txClear;
686 TXHEAD(dev).retries = conf->txRetries; /* 0 is use default */
687 TXHEAD(dev).routing = conf->txRouting;
688 TXHEAD(dev).scrambled = conf->txScrambled;
689 memcpy_toio((char __iomem *)arlan + TXHEAD(dev).offset, buf + ARLAN_FAKE_HDR_LEN, TXHEAD(dev).length);
690 }
691 else if (!TXTAIL(dev).offset && length < (0x800 - headEnds))
692 {
693 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
694 printk(KERN_ERR "TXTAIL insert, headEnd %d\n", headEnds);
695
696 TXTAIL(dev).offset =
697 offsetof(struct arlan_shmem, txBuffer) + 0x800 - (length / 64 + 2) * 64;
698 TXTAIL(dev).length = length - ARLAN_FAKE_HDR_LEN;
699 for (i = 0; i < 6; i++)
700 TXTAIL(dev).dest[i] = buf[i];
701 TXTAIL(dev).clear = conf->txClear;
702 TXTAIL(dev).retries = conf->txRetries;
703 TXTAIL(dev).routing = conf->txRouting;
704 TXTAIL(dev).scrambled = conf->txScrambled;
705 memcpy_toio(((char __iomem *)arlan + TXTAIL(dev).offset), buf + ARLAN_FAKE_HDR_LEN, TXTAIL(dev).length);
706 }
707 else
708 {
709 netif_stop_queue (dev);
710 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
711 printk(KERN_ERR "TX TAIL & HEAD full, return, tailStart %d headEnd %d\n", tailStarts, headEnds);
712 return -1;
713 }
714 priv->out_bytes += length;
715 priv->out_bytes10 += length;
716 if (conf->measure_rate < 1)
717 conf->measure_rate = 1;
718 if (time_after(jiffies, priv->out_time + conf->measure_rate * HZ))
719 {
720 conf->out_speed = priv->out_bytes / conf->measure_rate;
721 priv->out_bytes = 0;
722 priv->out_time = jiffies;
723 }
724 if (time_after(jiffies, priv->out_time10 + conf->measure_rate * 10*HZ))
725 {
726 conf->out_speed10 = priv->out_bytes10 / (10 * conf->measure_rate);
727 priv->out_bytes10 = 0;
728 priv->out_time10 = jiffies;
729 }
730 if (TXHEAD(dev).offset && TXTAIL(dev).offset)
731 {
732 netif_stop_queue (dev);
733 return 0;
734 }
735 else
736 netif_start_queue (dev);
737
738
739 IFDEBUG(ARLAN_DEBUG_HEADER_DUMP)
740 printk(KERN_WARNING "%s Transmit t %2x:%2x:%2x:%2x:%2x:%2x f %2x:%2x:%2x:%2x:%2x:%2x \n", dev->name,
741 (unsigned char) buf[0], (unsigned char) buf[1], (unsigned char) buf[2], (unsigned char) buf[3],
742 (unsigned char) buf[4], (unsigned char) buf[5], (unsigned char) buf[6], (unsigned char) buf[7],
743 (unsigned char) buf[8], (unsigned char) buf[9], (unsigned char) buf[10], (unsigned char) buf[11]);
744
745 IFDEBUG(ARLAN_DEBUG_TX_CHAIN) printk(KERN_ERR "TX command prepare for buffer %d\n", priv->txLast);
746
747 arlan_command(dev, ARLAN_COMMAND_TX);
748
749 priv->tx_last_sent = jiffies;
750
751 IFDEBUG(ARLAN_DEBUG_TX_CHAIN) printk("%s TX Qued %d bytes \n", dev->name, length);
752
753 ARLAN_DEBUG_EXIT("arlan_hw_tx");
754
755 return 0;
756}
757
758
759static int arlan_hw_config(struct net_device *dev)
760{
761 struct arlan_private *priv = netdev_priv(dev);
762 volatile struct arlan_shmem __iomem *arlan = priv->card;
763 struct arlan_conf_stru *conf = priv->Conf;
764
765 ARLAN_DEBUG_ENTRY("arlan_hw_config");
766
767 printk(KERN_NOTICE "%s arlan configure called \n", dev->name);
768 if (arlan_EEPROM_bad)
769 printk(KERN_NOTICE "arlan configure with eeprom bad option \n");
770
771
772 WRITESHM(arlan->spreadingCode, conf->spreadingCode, u_char);
773 WRITESHM(arlan->channelSet, conf->channelSet, u_char);
774
775 if (arlan_EEPROM_bad)
776 WRITESHM(arlan->defaultChannelSet, conf->channelSet, u_char);
777
778 WRITESHM(arlan->channelNumber, conf->channelNumber, u_char);
779
780 WRITESHM(arlan->scramblingDisable, conf->scramblingDisable, u_char);
781 WRITESHM(arlan->txAttenuation, conf->txAttenuation, u_char);
782
783 WRITESHM(arlan->systemId, conf->systemId, u_int);
784
785 WRITESHM(arlan->maxRetries, conf->maxRetries, u_char);
786 WRITESHM(arlan->receiveMode, conf->receiveMode, u_char);
787 WRITESHM(arlan->priority, conf->priority, u_char);
788 WRITESHM(arlan->rootOrRepeater, conf->rootOrRepeater, u_char);
789 WRITESHM(arlan->SID, conf->SID, u_int);
790
791 WRITESHM(arlan->registrationMode, conf->registrationMode, u_char);
792
793 WRITESHM(arlan->registrationFill, conf->registrationFill, u_char);
794 WRITESHM(arlan->localTalkAddress, conf->localTalkAddress, u_char);
795 WRITESHM(arlan->codeFormat, conf->codeFormat, u_char);
796 WRITESHM(arlan->numChannels, conf->numChannels, u_char);
797 WRITESHM(arlan->channel1, conf->channel1, u_char);
798 WRITESHM(arlan->channel2, conf->channel2, u_char);
799 WRITESHM(arlan->channel3, conf->channel3, u_char);
800 WRITESHM(arlan->channel4, conf->channel4, u_char);
801 WRITESHM(arlan->radioNodeId, conf->radioNodeId, u_short);
802 WRITESHM(arlan->SID, conf->SID, u_int);
803 WRITESHM(arlan->waitTime, conf->waitTime, u_short);
804 WRITESHM(arlan->lParameter, conf->lParameter, u_short);
805 memcpy_toio(&(arlan->_15), &(conf->_15), 3);
806 WRITESHM(arlan->_15, conf->_15, u_short);
807 WRITESHM(arlan->headerSize, conf->headerSize, u_short);
808 if (arlan_EEPROM_bad)
809 WRITESHM(arlan->hardwareType, conf->hardwareType, u_char);
810 WRITESHM(arlan->radioType, conf->radioType, u_char);
811 if (arlan_EEPROM_bad)
812 WRITESHM(arlan->radioModule, conf->radioType, u_char);
813
814 memcpy_toio(arlan->encryptionKey + keyStart, encryptionKey, 8);
815 memcpy_toio(arlan->name, conf->siteName, 16);
816
817 WRITESHMB(arlan->commandByte, ARLAN_COM_INT | ARLAN_COM_CONF); /* do configure */
818 memset_io(arlan->commandParameter, 0, 0xf); /* 0xf */
819 memset_io(arlan->commandParameter + 1, 0, 2);
820 if (conf->writeEEPROM)
821 {
822 memset_io(arlan->commandParameter, conf->writeEEPROM, 1);
823// conf->writeEEPROM=0;
824 }
825 if (conf->registrationMode && conf->registrationInterrupts)
826 memset_io(arlan->commandParameter + 3, 1, 1);
827 else
828 memset_io(arlan->commandParameter + 3, 0, 1);
829
830 priv->irq_test_done = 0;
831
832 if (conf->tx_queue_len)
833 dev->tx_queue_len = conf->tx_queue_len;
834 udelay(100);
835
836 ARLAN_DEBUG_EXIT("arlan_hw_config");
837 return 0;
838}
839
840
841static int arlan_read_card_configuration(struct net_device *dev)
842{
843 u_char tlx415;
844 struct arlan_private *priv = netdev_priv(dev);
845 volatile struct arlan_shmem __iomem *arlan = priv->card;
846 struct arlan_conf_stru *conf = priv->Conf;
847
848 ARLAN_DEBUG_ENTRY("arlan_read_card_configuration");
849
850 if (radioNodeId == radioNodeIdUNKNOWN)
851 {
852 READSHM(conf->radioNodeId, arlan->radioNodeId, u_short);
853 }
854 else
855 conf->radioNodeId = radioNodeId;
856
857 if (SID == SIDUNKNOWN)
858 {
859 READSHM(conf->SID, arlan->SID, u_int);
860 }
861 else conf->SID = SID;
862
863 if (spreadingCode == spreadingCodeUNKNOWN)
864 {
865 READSHM(conf->spreadingCode, arlan->spreadingCode, u_char);
866 }
867 else
868 conf->spreadingCode = spreadingCode;
869
870 if (channelSet == channelSetUNKNOWN)
871 {
872 READSHM(conf->channelSet, arlan->channelSet, u_char);
873 }
874 else conf->channelSet = channelSet;
875
876 if (channelNumber == channelNumberUNKNOWN)
877 {
878 READSHM(conf->channelNumber, arlan->channelNumber, u_char);
879 }
880 else conf->channelNumber = channelNumber;
881
882 READSHM(conf->scramblingDisable, arlan->scramblingDisable, u_char);
883 READSHM(conf->txAttenuation, arlan->txAttenuation, u_char);
884
885 if (systemId == systemIdUNKNOWN)
886 {
887 READSHM(conf->systemId, arlan->systemId, u_int);
888 }
889 else conf->systemId = systemId;
890
891 READSHM(conf->maxDatagramSize, arlan->maxDatagramSize, u_short);
892 READSHM(conf->maxFrameSize, arlan->maxFrameSize, u_short);
893 READSHM(conf->maxRetries, arlan->maxRetries, u_char);
894 READSHM(conf->receiveMode, arlan->receiveMode, u_char);
895 READSHM(conf->priority, arlan->priority, u_char);
896 READSHM(conf->rootOrRepeater, arlan->rootOrRepeater, u_char);
897
898 if (SID == SIDUNKNOWN)
899 {
900 READSHM(conf->SID, arlan->SID, u_int);
901 }
902 else conf->SID = SID;
903
904 if (registrationMode == registrationModeUNKNOWN)
905 {
906 READSHM(conf->registrationMode, arlan->registrationMode, u_char);
907 }
908 else conf->registrationMode = registrationMode;
909
910 READSHM(conf->registrationFill, arlan->registrationFill, u_char);
911 READSHM(conf->localTalkAddress, arlan->localTalkAddress, u_char);
912 READSHM(conf->codeFormat, arlan->codeFormat, u_char);
913 READSHM(conf->numChannels, arlan->numChannels, u_char);
914 READSHM(conf->channel1, arlan->channel1, u_char);
915 READSHM(conf->channel2, arlan->channel2, u_char);
916 READSHM(conf->channel3, arlan->channel3, u_char);
917 READSHM(conf->channel4, arlan->channel4, u_char);
918 READSHM(conf->waitTime, arlan->waitTime, u_short);
919 READSHM(conf->lParameter, arlan->lParameter, u_short);
920 READSHM(conf->_15, arlan->_15, u_short);
921 READSHM(conf->headerSize, arlan->headerSize, u_short);
922 READSHM(conf->hardwareType, arlan->hardwareType, u_char);
923 READSHM(conf->radioType, arlan->radioModule, u_char);
924
925 if (conf->radioType == 0)
926 conf->radioType = 0xc;
927
928 WRITESHM(arlan->configStatus, 0xA5, u_char);
929 READSHM(tlx415, arlan->configStatus, u_char);
930
931 if (tlx415 != 0xA5)
932 printk(KERN_INFO "%s tlx415 chip \n", dev->name);
933
934 conf->txClear = 0;
935 conf->txRetries = 1;
936 conf->txRouting = 1;
937 conf->txScrambled = 0;
938 conf->rxParameter = 1;
939 conf->txTimeoutMs = 4000;
940 conf->waitCardTimeout = 100000;
941 conf->receiveMode = ARLAN_RCV_CLEAN;
942 memcpy_fromio(conf->siteName, arlan->name, 16);
943 conf->siteName[16] = '\0';
944 conf->retries = retries;
945 conf->tx_delay_ms = tx_delay_ms;
946 conf->ReTransmitPacketMaxSize = 200;
947 conf->waitReTransmitPacketMaxSize = 200;
948 conf->txAckTimeoutMs = 900;
949 conf->fastReTransCount = 3;
950
951 ARLAN_DEBUG_EXIT("arlan_read_card_configuration");
952
953 return 0;
954}
955
956
957static int lastFoundAt = 0xbe000;
958
959
960/*
961 * This is the real probe routine. Linux has a history of friendly device
962 * probes on the ISA bus. A good device probes avoids doing writes, and
963 * verifies that the correct device exists and functions.
964 */
965#define ARLAN_SHMEM_SIZE 0x2000
966static int __init arlan_check_fingerprint(unsigned long memaddr)
967{
968 static const char probeText[] = "TELESYSTEM SLW INC. ARLAN \0";
969 volatile struct arlan_shmem __iomem *arlan = (struct arlan_shmem *) memaddr;
970 unsigned long paddr = virt_to_phys((void *) memaddr);
971 char tempBuf[49];
972
973 ARLAN_DEBUG_ENTRY("arlan_check_fingerprint");
974
975 if (!request_mem_region(paddr, ARLAN_SHMEM_SIZE, "arlan")) {
976 // printk(KERN_WARNING "arlan: memory region %lx excluded from probing \n",paddr);
977 return -ENODEV;
978 }
979
980 memcpy_fromio(tempBuf, arlan->textRegion, 29);
981 tempBuf[30] = 0;
982
983 /* check for card at this address */
984 if (0 != strncmp(tempBuf, probeText, 29)){
985 release_mem_region(paddr, ARLAN_SHMEM_SIZE);
986 return -ENODEV;
987 }
988
989// printk(KERN_INFO "arlan found at 0x%x \n",memaddr);
990 ARLAN_DEBUG_EXIT("arlan_check_fingerprint");
991
992 return 0;
993}
994
995static int arlan_change_mtu(struct net_device *dev, int new_mtu)
996{
997 struct arlan_private *priv = netdev_priv(dev);
998 struct arlan_conf_stru *conf = priv->Conf;
999
1000 ARLAN_DEBUG_ENTRY("arlan_change_mtu");
1001 if (new_mtu > 2032)
1002 return -EINVAL;
1003 dev->mtu = new_mtu;
1004 if (new_mtu < 256)
1005 new_mtu = 256; /* cards book suggests 1600 */
1006 conf->maxDatagramSize = new_mtu;
1007 conf->maxFrameSize = new_mtu + 48;
1008
1009 arlan_command(dev, ARLAN_COMMAND_CLEAN_AND_CONF);
1010 printk(KERN_NOTICE "%s mtu changed to %d \n", dev->name, new_mtu);
1011
1012 ARLAN_DEBUG_EXIT("arlan_change_mtu");
1013
1014 return 0;
1015}
1016
1017static int arlan_mac_addr(struct net_device *dev, void *p)
1018{
1019 struct sockaddr *addr = p;
1020
1021
1022 ARLAN_DEBUG_ENTRY("arlan_mac_addr");
1023 return -EINVAL;
1024
1025 if (netif_running(dev))
1026 return -EBUSY;
1027 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1028
1029 ARLAN_DEBUG_EXIT("arlan_mac_addr");
1030 return 0;
1031}
1032
1033static const struct net_device_ops arlan_netdev_ops = {
1034 .ndo_open = arlan_open,
1035 .ndo_stop = arlan_close,
1036 .ndo_start_xmit = arlan_tx,
1037 .ndo_get_stats = arlan_statistics,
1038 .ndo_set_multicast_list = arlan_set_multicast,
1039 .ndo_change_mtu = arlan_change_mtu,
1040 .ndo_set_mac_address = arlan_mac_addr,
1041 .ndo_tx_timeout = arlan_tx_timeout,
1042 .ndo_validate_addr = eth_validate_addr,
1043};
1044
1045static int __init arlan_setup_device(struct net_device *dev, int num)
1046{
1047 struct arlan_private *ap = netdev_priv(dev);
1048 int err;
1049
1050 ARLAN_DEBUG_ENTRY("arlan_setup_device");
1051
1052 ap->conf = (struct arlan_shmem *)(ap+1);
1053
1054 dev->tx_queue_len = tx_queue_len;
1055 dev->netdev_ops = &arlan_netdev_ops;
1056 dev->watchdog_timeo = 3*HZ;
1057
1058 ap->irq_test_done = 0;
1059 ap->Conf = &arlan_conf[num];
1060
1061 ap->Conf->pre_Command_Wait = 40;
1062 ap->Conf->rx_tweak1 = 30;
1063 ap->Conf->rx_tweak2 = 0;
1064
1065
1066 err = register_netdev(dev);
1067 if (err) {
1068 release_mem_region(virt_to_phys((void *) dev->mem_start),
1069 ARLAN_SHMEM_SIZE);
1070 free_netdev(dev);
1071 return err;
1072 }
1073 arlan_device[num] = dev;
1074 ARLAN_DEBUG_EXIT("arlan_setup_device");
1075 return 0;
1076}
1077
1078static int __init arlan_probe_here(struct net_device *dev,
1079 unsigned long memaddr)
1080{
1081 struct arlan_private *ap = netdev_priv(dev);
1082
1083 ARLAN_DEBUG_ENTRY("arlan_probe_here");
1084
1085 if (arlan_check_fingerprint(memaddr))
1086 return -ENODEV;
1087
1088 printk(KERN_NOTICE "%s: Arlan found at %llx, \n ", dev->name,
1089 (u64) virt_to_phys((void*)memaddr));
1090
1091 ap->card = (void *) memaddr;
1092 dev->mem_start = memaddr;
1093 dev->mem_end = memaddr + ARLAN_SHMEM_SIZE-1;
1094
1095 if (dev->irq < 2)
1096 {
1097 READSHM(dev->irq, ap->card->irqLevel, u_char);
1098 } else if (dev->irq == 2)
1099 dev->irq = 9;
1100
1101 arlan_read_card_configuration(dev);
1102
1103 ARLAN_DEBUG_EXIT("arlan_probe_here");
1104 return 0;
1105}
1106
1107
1108static int arlan_open(struct net_device *dev)
1109{
1110 struct arlan_private *priv = netdev_priv(dev);
1111 volatile struct arlan_shmem __iomem *arlan = priv->card;
1112 int ret = 0;
1113
1114 ARLAN_DEBUG_ENTRY("arlan_open");
1115
1116 ret = request_irq(dev->irq, &arlan_interrupt, 0, dev->name, dev);
1117 if (ret)
1118 {
1119 printk(KERN_ERR "%s: unable to get IRQ %d .\n",
1120 dev->name, dev->irq);
1121 return ret;
1122 }
1123
1124
1125 priv->bad = 0;
1126 priv->lastReset = 0;
1127 priv->reset = 0;
1128 memcpy_fromio(dev->dev_addr, arlan->lanCardNodeId, 6);
1129 memset(dev->broadcast, 0xff, 6);
1130 dev->tx_queue_len = tx_queue_len;
1131 priv->interrupt_processing_active = 0;
1132 spin_lock_init(&priv->lock);
1133
1134 netif_start_queue (dev);
1135
1136 priv->registrationLostCount = 0;
1137 priv->registrationLastSeen = jiffies;
1138 priv->txLast = 0;
1139 priv->tx_command_given = 0;
1140 priv->rx_command_given = 0;
1141
1142 priv->reRegisterExp = 1;
1143 priv->tx_last_sent = jiffies - 1;
1144 priv->tx_last_cleared = jiffies;
1145 priv->Conf->writeEEPROM = 0;
1146 priv->Conf->registrationInterrupts = 1;
1147
1148 init_timer(&priv->timer);
1149 priv->timer.expires = jiffies + HZ / 10;
1150 priv->timer.data = (unsigned long) dev;
1151 priv->timer.function = &arlan_registration_timer; /* timer handler */
1152
1153 arlan_command(dev, ARLAN_COMMAND_POWERUP | ARLAN_COMMAND_LONG_WAIT_NOW);
1154 mdelay(200);
1155 add_timer(&priv->timer);
1156
1157 ARLAN_DEBUG_EXIT("arlan_open");
1158 return 0;
1159}
1160
1161
1162static void arlan_tx_timeout (struct net_device *dev)
1163{
1164 printk(KERN_ERR "%s: arlan transmit timed out, kernel decided\n", dev->name);
1165 /* Try to restart the adaptor. */
1166 arlan_command(dev, ARLAN_COMMAND_CLEAN_AND_RESET);
1167 // dev->trans_start = jiffies;
1168 // netif_start_queue (dev);
1169}
1170
1171
1172static netdev_tx_t arlan_tx(struct sk_buff *skb, struct net_device *dev)
1173{
1174 short length;
1175 unsigned char *buf;
1176
1177 ARLAN_DEBUG_ENTRY("arlan_tx");
1178
1179 length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
1180 buf = skb->data;
1181
1182 if (length + 0x12 > 0x800) {
1183 printk(KERN_ERR "TX RING overflow \n");
1184 netif_stop_queue (dev);
1185 }
1186
1187 if (arlan_hw_tx(dev, buf, length) == -1)
1188 goto bad_end;
1189
1190 dev->trans_start = jiffies;
1191
1192 dev_kfree_skb(skb);
1193
1194 arlan_process_interrupt(dev);
1195 ARLAN_DEBUG_EXIT("arlan_tx");
1196 return NETDEV_TX_OK;
1197
1198bad_end:
1199 arlan_process_interrupt(dev);
1200 netif_stop_queue (dev);
1201 ARLAN_DEBUG_EXIT("arlan_tx");
1202 return NETDEV_TX_BUSY;
1203}
1204
1205
1206static inline int DoNotReTransmitCrap(struct net_device *dev)
1207{
1208 struct arlan_private *priv = netdev_priv(dev);
1209
1210 if (TXLAST(dev).length < priv->Conf->ReTransmitPacketMaxSize)
1211 return 1;
1212 return 0;
1213
1214}
1215
1216static inline int DoNotWaitReTransmitCrap(struct net_device *dev)
1217{
1218 struct arlan_private *priv = netdev_priv(dev);
1219
1220 if (TXLAST(dev).length < priv->Conf->waitReTransmitPacketMaxSize)
1221 return 1;
1222 return 0;
1223}
1224
1225static inline void arlan_queue_retransmit(struct net_device *dev)
1226{
1227 struct arlan_private *priv = netdev_priv(dev);
1228
1229 ARLAN_DEBUG_ENTRY("arlan_queue_retransmit");
1230
1231 if (DoNotWaitReTransmitCrap(dev))
1232 {
1233 arlan_drop_tx(dev);
1234 } else
1235 priv->ReTransmitRequested++;
1236
1237 ARLAN_DEBUG_EXIT("arlan_queue_retransmit");
1238}
1239
1240static inline void RetryOrFail(struct net_device *dev)
1241{
1242 struct arlan_private *priv = netdev_priv(dev);
1243
1244 ARLAN_DEBUG_ENTRY("RetryOrFail");
1245
1246 if (priv->retransmissions > priv->Conf->retries ||
1247 DoNotReTransmitCrap(dev))
1248 {
1249 arlan_drop_tx(dev);
1250 }
1251 else if (priv->bad <= priv->Conf->fastReTransCount)
1252 {
1253 arlan_retransmit_now(dev);
1254 }
1255 else arlan_queue_retransmit(dev);
1256
1257 ARLAN_DEBUG_EXIT("RetryOrFail");
1258}
1259
1260
1261static void arlan_tx_done_interrupt(struct net_device *dev, int status)
1262{
1263 struct arlan_private *priv = netdev_priv(dev);
1264
1265 ARLAN_DEBUG_ENTRY("arlan_tx_done_interrupt");
1266
1267 priv->tx_last_cleared = jiffies;
1268 priv->tx_command_given = 0;
1269 switch (status)
1270 {
1271 case 1:
1272 {
1273 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
1274 printk("arlan intr: transmit OK\n");
1275 dev->stats.tx_packets++;
1276 priv->bad = 0;
1277 priv->reset = 0;
1278 priv->retransmissions = 0;
1279 if (priv->Conf->tx_delay_ms)
1280 {
1281 priv->tx_done_delayed = jiffies + (priv->Conf->tx_delay_ms * HZ) / 1000 + 1;
1282 }
1283 else
1284 {
1285 TXLAST(dev).offset = 0;
1286 if (priv->txLast)
1287 priv->txLast = 0;
1288 else if (TXTAIL(dev).offset)
1289 priv->txLast = 1;
1290 if (TXLAST(dev).offset)
1291 {
1292 arlan_retransmit_now(dev);
1293 dev->trans_start = jiffies;
1294 }
1295 if (!TXHEAD(dev).offset || !TXTAIL(dev).offset)
1296 {
1297 netif_wake_queue (dev);
1298 }
1299 }
1300 }
1301 break;
1302
1303 case 2:
1304 {
1305 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
1306 printk("arlan intr: transmit timed out\n");
1307 priv->bad += 1;
1308 //arlan_queue_retransmit(dev);
1309 RetryOrFail(dev);
1310 }
1311 break;
1312
1313 case 3:
1314 {
1315 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
1316 printk("arlan intr: transmit max retries\n");
1317 priv->bad += 1;
1318 priv->reset = 0;
1319 //arlan_queue_retransmit(dev);
1320 RetryOrFail(dev);
1321 }
1322 break;
1323
1324 case 4:
1325 {
1326 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
1327 printk("arlan intr: transmit aborted\n");
1328 priv->bad += 1;
1329 arlan_queue_retransmit(dev);
1330 //RetryOrFail(dev);
1331 }
1332 break;
1333
1334 case 5:
1335 {
1336 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
1337 printk("arlan intr: transmit not registered\n");
1338 priv->bad += 1;
1339 //debug=101;
1340 arlan_queue_retransmit(dev);
1341 }
1342 break;
1343
1344 case 6:
1345 {
1346 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
1347 printk("arlan intr: transmit destination full\n");
1348 priv->bad += 1;
1349 priv->reset = 0;
1350 //arlan_drop_tx(dev);
1351 arlan_queue_retransmit(dev);
1352 }
1353 break;
1354
1355 case 7:
1356 {
1357 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
1358 printk("arlan intr: transmit unknown ack\n");
1359 priv->bad += 1;
1360 priv->reset = 0;
1361 arlan_queue_retransmit(dev);
1362 }
1363 break;
1364
1365 case 8:
1366 {
1367 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
1368 printk("arlan intr: transmit dest mail box full\n");
1369 priv->bad += 1;
1370 priv->reset = 0;
1371 //arlan_drop_tx(dev);
1372 arlan_queue_retransmit(dev);
1373 }
1374 break;
1375
1376 case 9:
1377 {
1378 IFDEBUG(ARLAN_DEBUG_TX_CHAIN)
1379 printk("arlan intr: transmit root dest not reg.\n");
1380 priv->bad += 1;
1381 priv->reset = 1;
1382 //arlan_drop_tx(dev);
1383 arlan_queue_retransmit(dev);
1384 }
1385 break;
1386
1387 default:
1388 {
1389 printk(KERN_ERR "arlan intr: transmit status unknown\n");
1390 priv->bad += 1;
1391 priv->reset = 1;
1392 arlan_drop_tx(dev);
1393 }
1394 }
1395
1396 ARLAN_DEBUG_EXIT("arlan_tx_done_interrupt");
1397}
1398
1399
1400static void arlan_rx_interrupt(struct net_device *dev, u_char rxStatus, u_short rxOffset, u_short pkt_len)
1401{
1402 char *skbtmp;
1403 int i = 0;
1404
1405 struct arlan_private *priv = netdev_priv(dev);
1406 volatile struct arlan_shmem __iomem *arlan = priv->card;
1407 struct arlan_conf_stru *conf = priv->Conf;
1408
1409
1410 ARLAN_DEBUG_ENTRY("arlan_rx_interrupt");
1411 // by spec, not WRITESHMB(arlan->rxStatus,0x00);
1412 // prohibited here arlan_command(dev, ARLAN_COMMAND_RX);
1413
1414 if (pkt_len < 10 || pkt_len > 2048)
1415 {
1416 printk(KERN_WARNING "%s: got too short or long packet, len %d \n", dev->name, pkt_len);
1417 return;
1418 }
1419 if (rxOffset + pkt_len > 0x2000)
1420 {
1421 printk("%s: got too long packet, len %d offset %x\n", dev->name, pkt_len, rxOffset);
1422 return;
1423 }
1424 priv->in_bytes += pkt_len;
1425 priv->in_bytes10 += pkt_len;
1426 if (conf->measure_rate < 1)
1427 conf->measure_rate = 1;
1428 if (time_after(jiffies, priv->in_time + conf->measure_rate * HZ))
1429 {
1430 conf->in_speed = priv->in_bytes / conf->measure_rate;
1431 priv->in_bytes = 0;
1432 priv->in_time = jiffies;
1433 }
1434 if (time_after(jiffies, priv->in_time10 + conf->measure_rate * 10*HZ))
1435 {
1436 conf->in_speed10 = priv->in_bytes10 / (10 * conf->measure_rate);
1437 priv->in_bytes10 = 0;
1438 priv->in_time10 = jiffies;
1439 }
1440 DEBUGSHM(1, "arlan rcv pkt rxStatus= %d ", arlan->rxStatus, u_char);
1441 switch (rxStatus)
1442 {
1443 case 1:
1444 case 2:
1445 case 3:
1446 {
1447 /* Malloc up new buffer. */
1448 struct sk_buff *skb;
1449
1450 DEBUGSHM(50, "arlan recv pkt offs=%d\n", arlan->rxOffset, u_short);
1451 DEBUGSHM(1, "arlan rxFrmType = %d \n", arlan->rxFrmType, u_char);
1452 DEBUGSHM(1, KERN_INFO "arlan rx scrambled = %d \n", arlan->scrambled, u_char);
1453
1454 /* here we do multicast filtering to avoid slow 8-bit memcopy */
1455#ifdef ARLAN_MULTICAST
1456 if (!(dev->flags & IFF_ALLMULTI) &&
1457 !(dev->flags & IFF_PROMISC) &&
1458 dev->mc_list)
1459 {
1460 char hw_dst_addr[6];
1461 struct dev_mc_list *dmi = dev->mc_list;
1462 int i;
1463
1464 memcpy_fromio(hw_dst_addr, arlan->ultimateDestAddress, 6);
1465 if (hw_dst_addr[0] == 0x01)
1466 {
1467 if (mdebug)
1468 if (hw_dst_addr[1] == 0x00)
1469 printk(KERN_ERR "%s mcast 0x0100 \n", dev->name);
1470 else if (hw_dst_addr[1] == 0x40)
1471 printk(KERN_ERR "%s m/bcast 0x0140 \n", dev->name);
1472 while (dmi)
1473 {
1474 if (dmi->dmi_addrlen == 6) {
1475 if (arlan_debug & ARLAN_DEBUG_HEADER_DUMP)
1476 printk(KERN_ERR "%s mcl %pM\n",
1477 dev->name, dmi->dmi_addr);
1478 for (i = 0; i < 6; i++)
1479 if (dmi->dmi_addr[i] != hw_dst_addr[i])
1480 break;
1481 if (i == 6)
1482 break;
1483 } else
1484 printk(KERN_ERR "%s: invalid multicast address length given.\n", dev->name);
1485 dmi = dmi->next;
1486 }
1487 /* we reach here if multicast filtering is on and packet
1488 * is multicast and not for receive */
1489 goto end_of_interrupt;
1490 }
1491 }
1492#endif // ARLAN_MULTICAST
1493 /* multicast filtering ends here */
1494 pkt_len += ARLAN_FAKE_HDR_LEN;
1495
1496 skb = dev_alloc_skb(pkt_len + 4);
1497 if (skb == NULL)
1498 {
1499 printk(KERN_ERR "%s: Memory squeeze, dropping packet.\n", dev->name);
1500 dev->stats.rx_dropped++;
1501 break;
1502 }
1503 skb_reserve(skb, 2);
1504 skbtmp = skb_put(skb, pkt_len);
1505
1506 memcpy_fromio(skbtmp + ARLAN_FAKE_HDR_LEN, ((char __iomem *) arlan) + rxOffset, pkt_len - ARLAN_FAKE_HDR_LEN);
1507 memcpy_fromio(skbtmp, arlan->ultimateDestAddress, 6);
1508 memcpy_fromio(skbtmp + 6, arlan->rxSrc, 6);
1509 WRITESHMB(arlan->rxStatus, 0x00);
1510 arlan_command(dev, ARLAN_COMMAND_RX);
1511
1512 IFDEBUG(ARLAN_DEBUG_HEADER_DUMP)
1513 {
1514 char immedDestAddress[6];
1515 char immedSrcAddress[6];
1516 memcpy_fromio(immedDestAddress, arlan->immedDestAddress, 6);
1517 memcpy_fromio(immedSrcAddress, arlan->immedSrcAddress, 6);
1518
1519 printk(KERN_WARNING "%s t %pM f %pM imd %pM ims %pM\n",
1520 dev->name, skbtmp,
1521 &skbtmp[6],
1522 immedDestAddress,
1523 immedSrcAddress);
1524 }
1525 skb->protocol = eth_type_trans(skb, dev);
1526 IFDEBUG(ARLAN_DEBUG_HEADER_DUMP)
1527 if (skb->protocol != 0x608 && skb->protocol != 0x8)
1528 {
1529 for (i = 0; i <= 22; i++)
1530 printk("%02x:", (u_char) skbtmp[i + 12]);
1531 printk(KERN_ERR "\n");
1532 printk(KERN_WARNING "arlan kernel pkt type trans %x \n", skb->protocol);
1533 }
1534 netif_rx(skb);
1535 dev->stats.rx_packets++;
1536 dev->stats.rx_bytes += pkt_len;
1537 }
1538 break;
1539
1540 default:
1541 printk(KERN_ERR "arlan intr: received unknown status\n");
1542 dev->stats.rx_crc_errors++;
1543 break;
1544 }
1545 ARLAN_DEBUG_EXIT("arlan_rx_interrupt");
1546}
1547
1548static void arlan_process_interrupt(struct net_device *dev)
1549{
1550 struct arlan_private *priv = netdev_priv(dev);
1551 volatile struct arlan_shmem __iomem *arlan = priv->card;
1552 u_char rxStatus = READSHMB(arlan->rxStatus);
1553 u_char txStatus = READSHMB(arlan->txStatus);
1554 u_short rxOffset = READSHMS(arlan->rxOffset);
1555 u_short pkt_len = READSHMS(arlan->rxLength);
1556 int interrupt_count = 0;
1557
1558 ARLAN_DEBUG_ENTRY("arlan_process_interrupt");
1559
1560 if (test_and_set_bit(0, (void *) &priv->interrupt_processing_active))
1561 {
1562 if (arlan_debug & ARLAN_DEBUG_CHAIN_LOCKS)
1563 printk(KERN_ERR "interrupt chain reentering \n");
1564 goto end_int_process;
1565 }
1566 while ((rxStatus || txStatus || priv->interrupt_ack_requested)
1567 && (interrupt_count < 5))
1568 {
1569 if (rxStatus)
1570 priv->last_rx_int_ack_time = jiffies;
1571
1572 arlan_command(dev, ARLAN_COMMAND_INT_ACK);
1573 arlan_command(dev, ARLAN_COMMAND_INT_ENABLE);
1574
1575 IFDEBUG(ARLAN_DEBUG_INTERRUPT)
1576 printk(KERN_ERR "%s: got IRQ rx %x tx %x comm %x rxOff %x rxLen %x \n",
1577 dev->name, rxStatus, txStatus, READSHMB(arlan->commandByte),
1578 rxOffset, pkt_len);
1579
1580 if (rxStatus == 0 && txStatus == 0)
1581 {
1582 if (priv->irq_test_done)
1583 {
1584 if (!registrationBad(dev))
1585 IFDEBUG(ARLAN_DEBUG_INTERRUPT) printk(KERN_ERR "%s unknown interrupt(nop? regLost ?) reason tx %d rx %d ",
1586 dev->name, txStatus, rxStatus);
1587 } else {
1588 IFDEBUG(ARLAN_DEBUG_INTERRUPT)
1589 printk(KERN_INFO "%s irq $%d test OK \n", dev->name, dev->irq);
1590
1591 }
1592 priv->interrupt_ack_requested = 0;
1593 goto ends;
1594 }
1595 if (txStatus != 0)
1596 {
1597 WRITESHMB(arlan->txStatus, 0x00);
1598 arlan_tx_done_interrupt(dev, txStatus);
1599 goto ends;
1600 }
1601 if (rxStatus == 1 || rxStatus == 2)
1602 { /* a packet waiting */
1603 arlan_rx_interrupt(dev, rxStatus, rxOffset, pkt_len);
1604 goto ends;
1605 }
1606 if (rxStatus > 2 && rxStatus < 0xff)
1607 {
1608 WRITESHMB(arlan->rxStatus, 0x00);
1609 printk(KERN_ERR "%s unknown rxStatus reason tx %d rx %d ",
1610 dev->name, txStatus, rxStatus);
1611 goto ends;
1612 }
1613 if (rxStatus == 0xff)
1614 {
1615 WRITESHMB(arlan->rxStatus, 0x00);
1616 arlan_command(dev, ARLAN_COMMAND_RX);
1617 if (registrationBad(dev))
1618 netif_device_detach(dev);
1619 if (!registrationBad(dev))
1620 {
1621 priv->registrationLastSeen = jiffies;
1622 if (!netif_queue_stopped(dev) && !priv->under_reset && !priv->under_config)
1623 netif_wake_queue (dev);
1624 }
1625 goto ends;
1626 }
1627ends:
1628
1629 arlan_command_process(dev);
1630
1631 rxStatus = READSHMB(arlan->rxStatus);
1632 txStatus = READSHMB(arlan->txStatus);
1633 rxOffset = READSHMS(arlan->rxOffset);
1634 pkt_len = READSHMS(arlan->rxLength);
1635
1636
1637 priv->irq_test_done = 1;
1638
1639 interrupt_count++;
1640 }
1641 priv->interrupt_processing_active = 0;
1642
1643end_int_process:
1644 arlan_command_process(dev);
1645
1646 ARLAN_DEBUG_EXIT("arlan_process_interrupt");
1647 return;
1648}
1649
1650static irqreturn_t arlan_interrupt(int irq, void *dev_id)
1651{
1652 struct net_device *dev = dev_id;
1653 struct arlan_private *priv = netdev_priv(dev);
1654 volatile struct arlan_shmem __iomem *arlan = priv->card;
1655 u_char rxStatus = READSHMB(arlan->rxStatus);
1656 u_char txStatus = READSHMB(arlan->txStatus);
1657
1658 ARLAN_DEBUG_ENTRY("arlan_interrupt");
1659
1660
1661 if (!rxStatus && !txStatus)
1662 priv->interrupt_ack_requested++;
1663
1664 arlan_process_interrupt(dev);
1665
1666 priv->irq_test_done = 1;
1667
1668 ARLAN_DEBUG_EXIT("arlan_interrupt");
1669 return IRQ_HANDLED;
1670
1671}
1672
1673
1674static int arlan_close(struct net_device *dev)
1675{
1676 struct arlan_private *priv = netdev_priv(dev);
1677
1678 ARLAN_DEBUG_ENTRY("arlan_close");
1679
1680 del_timer_sync(&priv->timer);
1681
1682 arlan_command(dev, ARLAN_COMMAND_POWERDOWN);
1683
1684 IFDEBUG(ARLAN_DEBUG_STARTUP)
1685 printk(KERN_NOTICE "%s: Closing device\n", dev->name);
1686
1687 netif_stop_queue(dev);
1688 free_irq(dev->irq, dev);
1689
1690 ARLAN_DEBUG_EXIT("arlan_close");
1691 return 0;
1692}
1693
1694#ifdef ARLAN_DEBUGGING
1695static long alignLong(volatile u_char * ptr)
1696{
1697 long ret;
1698 memcpy_fromio(&ret, (void *) ptr, 4);
1699 return ret;
1700}
1701#endif
1702
1703/*
1704 * Get the current statistics.
1705 * This may be called with the card open or closed.
1706 */
1707
1708static struct net_device_stats *arlan_statistics(struct net_device *dev)
1709{
1710 struct arlan_private *priv = netdev_priv(dev);
1711 volatile struct arlan_shmem __iomem *arlan = priv->card;
1712
1713
1714 ARLAN_DEBUG_ENTRY("arlan_statistics");
1715
1716 /* Update the statistics from the device registers. */
1717
1718 READSHM(dev->stats.collisions, arlan->numReTransmissions, u_int);
1719 READSHM(dev->stats.rx_crc_errors, arlan->numCRCErrors, u_int);
1720 READSHM(dev->stats.rx_dropped, arlan->numFramesDiscarded, u_int);
1721 READSHM(dev->stats.rx_fifo_errors, arlan->numRXBufferOverflows, u_int);
1722 READSHM(dev->stats.rx_frame_errors, arlan->numReceiveFramesLost, u_int);
1723 READSHM(dev->stats.rx_over_errors, arlan->numRXOverruns, u_int);
1724 READSHM(dev->stats.rx_packets, arlan->numDatagramsReceived, u_int);
1725 READSHM(dev->stats.tx_aborted_errors, arlan->numAbortErrors, u_int);
1726 READSHM(dev->stats.tx_carrier_errors, arlan->numStatusTimeouts, u_int);
1727 READSHM(dev->stats.tx_dropped, arlan->numDatagramsDiscarded, u_int);
1728 READSHM(dev->stats.tx_fifo_errors, arlan->numTXUnderruns, u_int);
1729 READSHM(dev->stats.tx_packets, arlan->numDatagramsTransmitted, u_int);
1730 READSHM(dev->stats.tx_window_errors, arlan->numHoldOffs, u_int);
1731
1732 ARLAN_DEBUG_EXIT("arlan_statistics");
1733
1734 return &dev->stats;
1735}
1736
1737
1738static void arlan_set_multicast(struct net_device *dev)
1739{
1740 struct arlan_private *priv = netdev_priv(dev);
1741 volatile struct arlan_shmem __iomem *arlan = priv->card;
1742 struct arlan_conf_stru *conf = priv->Conf;
1743 int board_conf_needed = 0;
1744
1745
1746 ARLAN_DEBUG_ENTRY("arlan_set_multicast");
1747
1748 if (dev->flags & IFF_PROMISC)
1749 {
1750 unsigned char recMode;
1751 READSHM(recMode, arlan->receiveMode, u_char);
1752 conf->receiveMode = (ARLAN_RCV_PROMISC | ARLAN_RCV_CONTROL);
1753 if (conf->receiveMode != recMode)
1754 board_conf_needed = 1;
1755 }
1756 else
1757 {
1758 /* turn off promiscuous mode */
1759 unsigned char recMode;
1760 READSHM(recMode, arlan->receiveMode, u_char);
1761 conf->receiveMode = ARLAN_RCV_CLEAN | ARLAN_RCV_CONTROL;
1762 if (conf->receiveMode != recMode)
1763 board_conf_needed = 1;
1764 }
1765 if (board_conf_needed)
1766 arlan_command(dev, ARLAN_COMMAND_CONF);
1767
1768 ARLAN_DEBUG_EXIT("arlan_set_multicast");
1769}
1770
1771
1772struct net_device * __init arlan_probe(int unit)
1773{
1774 struct net_device *dev;
1775 int err;
1776 int m;
1777
1778 ARLAN_DEBUG_ENTRY("arlan_probe");
1779
1780 if (arlans_found == MAX_ARLANS)
1781 return ERR_PTR(-ENODEV);
1782
1783 /*
1784 * Reserve space for local data and a copy of the shared memory
1785 * that is used by the /proc interface.
1786 */
1787 dev = alloc_etherdev(sizeof(struct arlan_private)
1788 + sizeof(struct arlan_shmem));
1789 if (!dev)
1790 return ERR_PTR(-ENOMEM);
1791
1792 if (unit >= 0) {
1793 sprintf(dev->name, "eth%d", unit);
1794 netdev_boot_setup_check(dev);
1795
1796 if (dev->mem_start) {
1797 if (arlan_probe_here(dev, dev->mem_start) == 0)
1798 goto found;
1799 goto not_found;
1800 }
1801
1802 }
1803
1804
1805 for (m = (int)phys_to_virt(lastFoundAt) + ARLAN_SHMEM_SIZE;
1806 m <= (int)phys_to_virt(0xDE000);
1807 m += ARLAN_SHMEM_SIZE)
1808 {
1809 if (arlan_probe_here(dev, m) == 0)
1810 {
1811 lastFoundAt = (int)virt_to_phys((void*)m);
1812 goto found;
1813 }
1814 }
1815
1816 if (lastFoundAt == 0xbe000)
1817 printk(KERN_ERR "arlan: No Arlan devices found \n");
1818
1819 not_found:
1820 free_netdev(dev);
1821 return ERR_PTR(-ENODEV);
1822
1823 found:
1824 err = arlan_setup_device(dev, arlans_found);
1825 if (err)
1826 dev = ERR_PTR(err);
1827 else if (!arlans_found++)
1828 printk(KERN_INFO "Arlan driver %s\n", arlan_version);
1829
1830 return dev;
1831}
1832
1833#ifdef MODULE
1834int __init init_module(void)
1835{
1836 int i = 0;
1837
1838 ARLAN_DEBUG_ENTRY("init_module");
1839
1840 if (channelSet != channelSetUNKNOWN || channelNumber != channelNumberUNKNOWN || systemId != systemIdUNKNOWN)
1841 return -EINVAL;
1842
1843 for (i = 0; i < MAX_ARLANS; i++) {
1844 struct net_device *dev = arlan_probe(i);
1845
1846 if (IS_ERR(dev))
1847 return PTR_ERR(dev);
1848 }
1849 init_arlan_proc();
1850 printk(KERN_INFO "Arlan driver %s\n", arlan_version);
1851 ARLAN_DEBUG_EXIT("init_module");
1852 return 0;
1853}
1854
1855
1856void __exit cleanup_module(void)
1857{
1858 int i = 0;
1859 struct net_device *dev;
1860
1861 ARLAN_DEBUG_ENTRY("cleanup_module");
1862
1863 IFDEBUG(ARLAN_DEBUG_SHUTDOWN)
1864 printk(KERN_INFO "arlan: unloading module\n");
1865
1866 cleanup_arlan_proc();
1867
1868 for (i = 0; i < MAX_ARLANS; i++)
1869 {
1870 dev = arlan_device[i];
1871 if (dev) {
1872 arlan_command(dev, ARLAN_COMMAND_POWERDOWN );
1873
1874 unregister_netdev(dev);
1875 release_mem_region(virt_to_phys((void *) dev->mem_start),
1876 ARLAN_SHMEM_SIZE);
1877 free_netdev(dev);
1878 arlan_device[i] = NULL;
1879 }
1880 }
1881
1882 ARLAN_DEBUG_EXIT("cleanup_module");
1883}
1884
1885
1886#endif
1887MODULE_LICENSE("GPL");
diff --git a/drivers/net/wireless/arlan-proc.c b/drivers/net/wireless/arlan-proc.c
deleted file mode 100644
index a8b689635a3b..000000000000
--- a/drivers/net/wireless/arlan-proc.c
+++ /dev/null
@@ -1,1253 +0,0 @@
1#include "arlan.h"
2
3#include <linux/sysctl.h>
4
5#ifdef CONFIG_PROC_FS
6
7/* void enableReceive(struct net_device* dev);
8*/
9
10
11
12#define ARLAN_STR_SIZE 0x2ff0
13#define DEV_ARLAN_INFO 1
14#define DEV_ARLAN 1
15#define SARLG(type,var) {\
16 pos += sprintf(arlan_drive_info+pos, "%s\t=\t0x%x\n", #var, READSHMB(priva->card->var)); \
17 }
18
19#define SARLBN(type,var,nn) {\
20 pos += sprintf(arlan_drive_info+pos, "%s\t=\t0x",#var);\
21 for (i=0; i < nn; i++ ) pos += sprintf(arlan_drive_info+pos, "%02x",READSHMB(priva->card->var[i]));\
22 pos += sprintf(arlan_drive_info+pos, "\n"); \
23 }
24
25#define SARLBNpln(type,var,nn) {\
26 for (i=0; i < nn; i++ ) pos += sprintf(arlan_drive_info+pos, "%02x",READSHMB(priva->card->var[i]));\
27 }
28
29#define SARLSTR(var,nn) {\
30 char tmpStr[400];\
31 int tmpLn = nn;\
32 if (nn > 399 ) tmpLn = 399; \
33 memcpy(tmpStr,(char *) priva->conf->var,tmpLn);\
34 tmpStr[tmpLn] = 0; \
35 pos += sprintf(arlan_drive_info+pos, "%s\t=\t%s \n",#var,priva->conf->var);\
36 }
37
38#define SARLUC(var) SARLG(u_char, var)
39#define SARLUCN(var,nn) SARLBN(u_char,var, nn)
40#define SARLUS(var) SARLG(u_short, var)
41#define SARLUSN(var,nn) SARLBN(u_short,var, nn)
42#define SARLUI(var) SARLG(u_int, var)
43
44#define SARLUSA(var) {\
45 u_short tmpVar;\
46 memcpy(&tmpVar, (short *) priva->conf->var,2); \
47 pos += sprintf(arlan_drive_info+pos, "%s\t=\t0x%x\n",#var, tmpVar);\
48}
49
50#define SARLUIA(var) {\
51 u_int tmpVar;\
52 memcpy(&tmpVar, (int* )priva->conf->var,4); \
53 pos += sprintf(arlan_drive_info+pos, "%s\t=\t0x%x\n",#var, tmpVar);\
54}
55
56
57static const char *arlan_diagnostic_info_string(struct net_device *dev)
58{
59
60 struct arlan_private *priv = netdev_priv(dev);
61 volatile struct arlan_shmem __iomem *arlan = priv->card;
62 u_char diagnosticInfo;
63
64 READSHM(diagnosticInfo, arlan->diagnosticInfo, u_char);
65
66 switch (diagnosticInfo)
67 {
68 case 0xFF:
69 return "Diagnostic info is OK";
70 case 0xFE:
71 return "ERROR EPROM Checksum error ";
72 case 0xFD:
73 return "ERROR Local Ram Test Failed ";
74 case 0xFC:
75 return "ERROR SCC failure ";
76 case 0xFB:
77 return "ERROR BackBone failure ";
78 case 0xFA:
79 return "ERROR transceiver not found ";
80 case 0xF9:
81 return "ERROR no more address space ";
82 case 0xF8:
83 return "ERROR Checksum error ";
84 case 0xF7:
85 return "ERROR Missing SS Code";
86 case 0xF6:
87 return "ERROR Invalid config format";
88 case 0xF5:
89 return "ERROR Reserved errorcode F5";
90 case 0xF4:
91 return "ERROR Invalid spreading code/channel number";
92 case 0xF3:
93 return "ERROR Load Code Error";
94 case 0xF2:
95 return "ERROR Reserver errorcode F2 ";
96 case 0xF1:
97 return "ERROR Invalid command receivec by LAN card ";
98 case 0xF0:
99 return "ERROR Invalid parameter found in command ";
100 case 0xEF:
101 return "ERROR On-chip timer failure ";
102 case 0xEE:
103 return "ERROR T410 timer failure ";
104 case 0xED:
105 return "ERROR Too Many TxEnable commands ";
106 case 0xEC:
107 return "ERROR EEPROM error on radio module ";
108 default:
109 return "ERROR unknown Diagnostic info reply code ";
110 }
111}
112
113static const char *arlan_hardware_type_string(struct net_device *dev)
114{
115 u_char hardwareType;
116 struct arlan_private *priv = netdev_priv(dev);
117 volatile struct arlan_shmem __iomem *arlan = priv->card;
118
119 READSHM(hardwareType, arlan->hardwareType, u_char);
120 switch (hardwareType)
121 {
122 case 0x00:
123 return "type A450";
124 case 0x01:
125 return "type A650 ";
126 case 0x04:
127 return "type TMA coproc";
128 case 0x0D:
129 return "type A650E ";
130 case 0x18:
131 return "type TMA coproc Australian";
132 case 0x19:
133 return "type A650A ";
134 case 0x26:
135 return "type TMA coproc European";
136 case 0x2E:
137 return "type A655 ";
138 case 0x2F:
139 return "type A655A ";
140 case 0x30:
141 return "type A655E ";
142 case 0x0B:
143 return "type A670 ";
144 case 0x0C:
145 return "type A670E ";
146 case 0x2D:
147 return "type A670A ";
148 case 0x0F:
149 return "type A411T";
150 case 0x16:
151 return "type A411TA";
152 case 0x1B:
153 return "type A440T";
154 case 0x1C:
155 return "type A412T";
156 case 0x1E:
157 return "type A412TA";
158 case 0x22:
159 return "type A411TE";
160 case 0x24:
161 return "type A412TE";
162 case 0x27:
163 return "type A671T ";
164 case 0x29:
165 return "type A671TA ";
166 case 0x2B:
167 return "type A671TE ";
168 case 0x31:
169 return "type A415T ";
170 case 0x33:
171 return "type A415TA ";
172 case 0x35:
173 return "type A415TE ";
174 case 0x37:
175 return "type A672";
176 case 0x39:
177 return "type A672A ";
178 case 0x3B:
179 return "type A672T";
180 case 0x6B:
181 return "type IC2200";
182 default:
183 return "type A672T";
184 }
185}
186#ifdef ARLAN_DEBUGGING
187static void arlan_print_diagnostic_info(struct net_device *dev)
188{
189 int i;
190 u_char diagnosticInfo;
191 u_short diagnosticOffset;
192 u_char hardwareType;
193 struct arlan_private *priv = netdev_priv(dev);
194 volatile struct arlan_shmem __iomem *arlan = priv->card;
195
196 // ARLAN_DEBUG_ENTRY("arlan_print_diagnostic_info");
197
198 if (READSHMB(arlan->configuredStatusFlag) == 0)
199 printk("Arlan: Card NOT configured\n");
200 else
201 printk("Arlan: Card is configured\n");
202
203 READSHM(diagnosticInfo, arlan->diagnosticInfo, u_char);
204 READSHM(diagnosticOffset, arlan->diagnosticOffset, u_short);
205
206 printk(KERN_INFO "%s\n", arlan_diagnostic_info_string(dev));
207
208 if (diagnosticInfo != 0xff)
209 printk("%s arlan: Diagnostic Offset %d \n", dev->name, diagnosticOffset);
210
211 printk("arlan: LAN CODE ID = ");
212 for (i = 0; i < 6; i++)
213 DEBUGSHM(1, "%03d:", arlan->lanCardNodeId[i], u_char);
214 printk("\n");
215
216 printk("arlan: Arlan BroadCast address = ");
217 for (i = 0; i < 6; i++)
218 DEBUGSHM(1, "%03d:", arlan->broadcastAddress[i], u_char);
219 printk("\n");
220
221 READSHM(hardwareType, arlan->hardwareType, u_char);
222 printk(KERN_INFO "%s\n", arlan_hardware_type_string(dev));
223
224
225 DEBUGSHM(1, "arlan: channelNumber=%d\n", arlan->channelNumber, u_char);
226 DEBUGSHM(1, "arlan: channelSet=%d\n", arlan->channelSet, u_char);
227 DEBUGSHM(1, "arlan: spreadingCode=%d\n", arlan->spreadingCode, u_char);
228 DEBUGSHM(1, "arlan: radioNodeId=%d\n", arlan->radioNodeId, u_short);
229 DEBUGSHM(1, "arlan: SID =%d\n", arlan->SID, u_short);
230 DEBUGSHM(1, "arlan: rxOffset=%d\n", arlan->rxOffset, u_short);
231
232 DEBUGSHM(1, "arlan: registration mode is %d\n", arlan->registrationMode, u_char);
233
234 printk("arlan: name= ");
235 IFDEBUG(1)
236
237 for (i = 0; i < 16; i++)
238 {
239 char c;
240 READSHM(c, arlan->name[i], char);
241 if (c)
242 printk("%c", c);
243 }
244 printk("\n");
245
246// ARLAN_DEBUG_EXIT("arlan_print_diagnostic_info");
247
248}
249
250
251/****************************** TEST MEMORY **************/
252
253static int arlan_hw_test_memory(struct net_device *dev)
254{
255 u_char *ptr;
256 int i;
257 int memlen = sizeof(struct arlan_shmem) - 0xF; /* avoid control register */
258 volatile char *arlan_mem = (char *) (dev->mem_start);
259 struct arlan_private *priv = netdev_priv(dev);
260 volatile struct arlan_shmem __iomem *arlan = priv->card;
261 char pattern;
262
263 ptr = NULL;
264
265 /* hold card in reset state */
266 setHardwareReset(dev);
267
268 /* test memory */
269 pattern = 0;
270 for (i = 0; i < memlen; i++)
271 WRITESHM(arlan_mem[i], ((u_char) pattern++), u_char);
272
273 pattern = 0;
274 for (i = 0; i < memlen; i++)
275 {
276 char res;
277 READSHM(res, arlan_mem[i], char);
278 if (res != pattern++)
279 {
280 printk(KERN_ERR "Arlan driver memory test 1 failed \n");
281 return -1;
282 }
283 }
284
285 pattern = 0;
286 for (i = 0; i < memlen; i++)
287 WRITESHM(arlan_mem[i], ~(pattern++), char);
288
289 pattern = 0;
290 for (i = 0; i < memlen; i++)
291 {
292 char res;
293 READSHM(res, arlan_mem[i], char);
294 if (res != ~(pattern++))
295 {
296 printk(KERN_ERR "Arlan driver memory test 2 failed \n");
297 return -1;
298 }
299 }
300
301 /* zero memory */
302 for (i = 0; i < memlen; i++)
303 WRITESHM(arlan_mem[i], 0x00, char);
304
305 IFDEBUG(1) printk(KERN_INFO "Arlan: memory tests ok\n");
306
307 /* set reset flag and then release reset */
308 WRITESHM(arlan->resetFlag, 0xff, u_char);
309
310 clearChannelAttention(dev);
311 clearHardwareReset(dev);
312
313 /* wait for reset flag to become zero, we'll wait for two seconds */
314 if (arlan_command(dev, ARLAN_COMMAND_LONG_WAIT_NOW))
315 {
316 printk(KERN_ERR "%s arlan: failed to come back from memory test\n", dev->name);
317 return -1;
318 }
319 return 0;
320}
321
322static int arlan_setup_card_by_book(struct net_device *dev)
323{
324 u_char irqLevel, configuredStatusFlag;
325 struct arlan_private *priv = netdev_priv(dev);
326 volatile struct arlan_shmem __iomem *arlan = priv->card;
327
328// ARLAN_DEBUG_ENTRY("arlan_setup_card");
329
330 READSHM(configuredStatusFlag, arlan->configuredStatusFlag, u_char);
331
332 IFDEBUG(10)
333 if (configuredStatusFlag != 0)
334 IFDEBUG(10) printk("arlan: CARD IS CONFIGURED\n");
335 else
336 IFDEBUG(10) printk("arlan: card is NOT configured\n");
337
338 if (testMemory || (READSHMB(arlan->diagnosticInfo) != 0xff))
339 if (arlan_hw_test_memory(dev))
340 return -1;
341
342 DEBUGSHM(4, "arlan configuredStatus = %d \n", arlan->configuredStatusFlag, u_char);
343 DEBUGSHM(4, "arlan driver diagnostic: 0x%2x\n", arlan->diagnosticInfo, u_char);
344
345 /* issue nop command - no interrupt */
346 arlan_command(dev, ARLAN_COMMAND_NOOP);
347 if (arlan_command(dev, ARLAN_COMMAND_WAIT_NOW) != 0)
348 return -1;
349
350 IFDEBUG(50) printk("1st Noop successfully executed !!\n");
351
352 /* try to turn on the arlan interrupts */
353 clearClearInterrupt(dev);
354 setClearInterrupt(dev);
355 setInterruptEnable(dev);
356
357 /* issue nop command - with interrupt */
358
359 arlan_command(dev, ARLAN_COMMAND_NOOPINT);
360 if (arlan_command(dev, ARLAN_COMMAND_WAIT_NOW) != 0)
361 return -1;
362
363
364 IFDEBUG(50) printk("2nd Noop successfully executed !!\n");
365
366 READSHM(irqLevel, arlan->irqLevel, u_char)
367
368 if (irqLevel != dev->irq)
369 {
370 IFDEBUG(1) printk(KERN_WARNING "arlan dip switches set irq to %d\n", irqLevel);
371 printk(KERN_WARNING "device driver irq set to %d - does not match\n", dev->irq);
372 dev->irq = irqLevel;
373 }
374 else
375 IFDEBUG(2) printk("irq level is OK\n");
376
377
378 IFDEBUG(3) arlan_print_diagnostic_info(dev);
379
380 arlan_command(dev, ARLAN_COMMAND_CONF);
381
382 READSHM(configuredStatusFlag, arlan->configuredStatusFlag, u_char);
383 if (configuredStatusFlag == 0)
384 {
385 printk(KERN_WARNING "arlan configure failed\n");
386 return -1;
387 }
388 arlan_command(dev, ARLAN_COMMAND_LONG_WAIT_NOW);
389 arlan_command(dev, ARLAN_COMMAND_RX);
390 arlan_command(dev, ARLAN_COMMAND_LONG_WAIT_NOW);
391 printk(KERN_NOTICE "%s: arlan driver version %s loaded\n",
392 dev->name, arlan_version);
393
394// ARLAN_DEBUG_EXIT("arlan_setup_card");
395
396 return 0; /* no errors */
397}
398#endif
399
400#ifdef ARLAN_PROC_INTERFACE
401#ifdef ARLAN_PROC_SHM_DUMP
402
403static char arlan_drive_info[ARLAN_STR_SIZE] = "A655\n\0";
404
405static int arlan_sysctl_info(ctl_table * ctl, int write,
406 void __user *buffer, size_t * lenp, loff_t *ppos)
407{
408 int i;
409 int retv, pos, devnum;
410 struct arlan_private *priva = NULL;
411 struct net_device *dev;
412 pos = 0;
413 if (write)
414 {
415 printk("wrirte: ");
416 for (i = 0; i < 100; i++)
417 printk("adi %x \n", arlan_drive_info[i]);
418 }
419 if (ctl->procname == NULL || arlan_drive_info == NULL)
420 {
421 printk(KERN_WARNING " procname is NULL in sysctl_table or arlan_drive_info is NULL \n at arlan module\n ");
422 return -1;
423 }
424 devnum = ctl->procname[5] - '0';
425 if (devnum < 0 || devnum > MAX_ARLANS - 1)
426 {
427 printk(KERN_WARNING "too strange devnum in procfs parse\n ");
428 return -1;
429 }
430 else if (arlan_device[devnum] == NULL)
431 {
432 if (ctl->procname)
433 pos += sprintf(arlan_drive_info + pos, "\t%s\n\n", ctl->procname);
434 pos += sprintf(arlan_drive_info + pos, "No device found here \n");
435 goto final;
436 }
437 else
438 priva = netdev_priv(arlan_device[devnum]);
439
440 if (priva == NULL)
441 {
442 printk(KERN_WARNING " Could not find the device private in arlan procsys, bad\n ");
443 return -1;
444 }
445 dev = arlan_device[devnum];
446
447 memcpy_fromio(priva->conf, priva->card, sizeof(struct arlan_shmem));
448
449 pos = sprintf(arlan_drive_info, "Arlan info \n");
450 /* Header Signature */
451 SARLSTR(textRegion, 48);
452 SARLUC(resetFlag);
453 pos += sprintf(arlan_drive_info + pos, "diagnosticInfo\t=\t%s \n", arlan_diagnostic_info_string(dev));
454 SARLUC(diagnosticInfo);
455 SARLUS(diagnosticOffset);
456 SARLUCN(_1, 12);
457 SARLUCN(lanCardNodeId, 6);
458 SARLUCN(broadcastAddress, 6);
459 pos += sprintf(arlan_drive_info + pos, "hardwareType =\t %s \n", arlan_hardware_type_string(dev));
460 SARLUC(hardwareType);
461 SARLUC(majorHardwareVersion);
462 SARLUC(minorHardwareVersion);
463 SARLUC(radioModule);
464 SARLUC(defaultChannelSet);
465 SARLUCN(_2, 47);
466
467 /* Control/Status Block - 0x0080 */
468 SARLUC(interruptInProgress);
469 SARLUC(cntrlRegImage);
470
471 SARLUCN(_3, 14);
472 SARLUC(commandByte);
473 SARLUCN(commandParameter, 15);
474
475 /* Receive Status - 0x00a0 */
476 SARLUC(rxStatus);
477 SARLUC(rxFrmType);
478 SARLUS(rxOffset);
479 SARLUS(rxLength);
480 SARLUCN(rxSrc, 6);
481 SARLUC(rxBroadcastFlag);
482 SARLUC(rxQuality);
483 SARLUC(scrambled);
484 SARLUCN(_4, 1);
485
486 /* Transmit Status - 0x00b0 */
487 SARLUC(txStatus);
488 SARLUC(txAckQuality);
489 SARLUC(numRetries);
490 SARLUCN(_5, 14);
491 SARLUCN(registeredRouter, 6);
492 SARLUCN(backboneRouter, 6);
493 SARLUC(registrationStatus);
494 SARLUC(configuredStatusFlag);
495 SARLUCN(_6, 1);
496 SARLUCN(ultimateDestAddress, 6);
497 SARLUCN(immedDestAddress, 6);
498 SARLUCN(immedSrcAddress, 6);
499 SARLUS(rxSequenceNumber);
500 SARLUC(assignedLocaltalkAddress);
501 SARLUCN(_7, 27);
502
503 /* System Parameter Block */
504
505 /* - Driver Parameters (Novell Specific) */
506
507 SARLUS(txTimeout);
508 SARLUS(transportTime);
509 SARLUCN(_8, 4);
510
511 /* - Configuration Parameters */
512 SARLUC(irqLevel);
513 SARLUC(spreadingCode);
514 SARLUC(channelSet);
515 SARLUC(channelNumber);
516 SARLUS(radioNodeId);
517 SARLUCN(_9, 2);
518 SARLUC(scramblingDisable);
519 SARLUC(radioType);
520 SARLUS(routerId);
521 SARLUCN(_10, 9);
522 SARLUC(txAttenuation);
523 SARLUIA(systemId);
524 SARLUS(globalChecksum);
525 SARLUCN(_11, 4);
526 SARLUS(maxDatagramSize);
527 SARLUS(maxFrameSize);
528 SARLUC(maxRetries);
529 SARLUC(receiveMode);
530 SARLUC(priority);
531 SARLUC(rootOrRepeater);
532 SARLUCN(specifiedRouter, 6);
533 SARLUS(fastPollPeriod);
534 SARLUC(pollDecay);
535 SARLUSA(fastPollDelay);
536 SARLUC(arlThreshold);
537 SARLUC(arlDecay);
538 SARLUCN(_12, 1);
539 SARLUS(specRouterTimeout);
540 SARLUCN(_13, 5);
541
542 /* Scrambled Area */
543 SARLUIA(SID);
544 SARLUCN(encryptionKey, 12);
545 SARLUIA(_14);
546 SARLUSA(waitTime);
547 SARLUSA(lParameter);
548 SARLUCN(_15, 3);
549 SARLUS(headerSize);
550 SARLUS(sectionChecksum);
551
552 SARLUC(registrationMode);
553 SARLUC(registrationFill);
554 SARLUS(pollPeriod);
555 SARLUS(refreshPeriod);
556 SARLSTR(name, 16);
557 SARLUCN(NID, 6);
558 SARLUC(localTalkAddress);
559 SARLUC(codeFormat);
560 SARLUC(numChannels);
561 SARLUC(channel1);
562 SARLUC(channel2);
563 SARLUC(channel3);
564 SARLUC(channel4);
565 SARLUCN(SSCode, 59);
566
567/* SARLUCN( _16, 0x140);
568 */
569 /* Statistics Block - 0x0300 */
570 SARLUC(hostcpuLock);
571 SARLUC(lancpuLock);
572 SARLUCN(resetTime, 18);
573 SARLUIA(numDatagramsTransmitted);
574 SARLUIA(numReTransmissions);
575 SARLUIA(numFramesDiscarded);
576 SARLUIA(numDatagramsReceived);
577 SARLUIA(numDuplicateReceivedFrames);
578 SARLUIA(numDatagramsDiscarded);
579 SARLUS(maxNumReTransmitDatagram);
580 SARLUS(maxNumReTransmitFrames);
581 SARLUS(maxNumConsecutiveDuplicateFrames);
582 /* misaligned here so we have to go to characters */
583 SARLUIA(numBytesTransmitted);
584 SARLUIA(numBytesReceived);
585 SARLUIA(numCRCErrors);
586 SARLUIA(numLengthErrors);
587 SARLUIA(numAbortErrors);
588 SARLUIA(numTXUnderruns);
589 SARLUIA(numRXOverruns);
590 SARLUIA(numHoldOffs);
591 SARLUIA(numFramesTransmitted);
592 SARLUIA(numFramesReceived);
593 SARLUIA(numReceiveFramesLost);
594 SARLUIA(numRXBufferOverflows);
595 SARLUIA(numFramesDiscardedAddrMismatch);
596 SARLUIA(numFramesDiscardedSIDMismatch);
597 SARLUIA(numPollsTransmistted);
598 SARLUIA(numPollAcknowledges);
599 SARLUIA(numStatusTimeouts);
600 SARLUIA(numNACKReceived);
601 SARLUS(auxCmd);
602 SARLUCN(dumpPtr, 4);
603 SARLUC(dumpVal);
604 SARLUC(wireTest);
605
606 /* next 4 seems too long for procfs, over single page ?
607 SARLUCN( _17, 0x86);
608 SARLUCN( txBuffer, 0x800);
609 SARLUCN( rxBuffer, 0x800);
610 SARLUCN( _18, 0x0bff);
611 */
612
613 pos += sprintf(arlan_drive_info + pos, "rxRing\t=\t0x");
614 for (i = 0; i < 0x50; i++)
615 pos += sprintf(arlan_drive_info + pos, "%02x", ((char *) priva->conf)[priva->conf->rxOffset + i]);
616 pos += sprintf(arlan_drive_info + pos, "\n");
617
618 SARLUC(configStatus);
619 SARLUC(_22);
620 SARLUC(progIOCtrl);
621 SARLUC(shareMBase);
622 SARLUC(controlRegister);
623
624 pos += sprintf(arlan_drive_info + pos, " total %d chars\n", pos);
625 if (ctl)
626 if (ctl->procname)
627 pos += sprintf(arlan_drive_info + pos, " driver name : %s\n", ctl->procname);
628final:
629 *lenp = pos;
630
631 if (!write)
632 retv = proc_dostring(ctl, write, buffer, lenp, ppos);
633 else
634 {
635 *lenp = 0;
636 return -1;
637 }
638 return retv;
639}
640
641
642static int arlan_sysctl_info161719(ctl_table * ctl, int write,
643 void __user *buffer, size_t * lenp, loff_t *ppos)
644{
645 int i;
646 int retv, pos, devnum;
647 struct arlan_private *priva = NULL;
648
649 pos = 0;
650 devnum = ctl->procname[5] - '0';
651 if (arlan_device[devnum] == NULL)
652 {
653 pos += sprintf(arlan_drive_info + pos, "No device found here \n");
654 goto final;
655 }
656 else
657 priva = netdev_priv(arlan_device[devnum]);
658 if (priva == NULL)
659 {
660 printk(KERN_WARNING " Could not find the device private in arlan procsys, bad\n ");
661 return -1;
662 }
663 memcpy_fromio(priva->conf, priva->card, sizeof(struct arlan_shmem));
664 SARLUCN(_16, 0xC0);
665 SARLUCN(_17, 0x6A);
666 SARLUCN(_18, 14);
667 SARLUCN(_19, 0x86);
668 SARLUCN(_21, 0x3fd);
669
670final:
671 *lenp = pos;
672 retv = proc_dostring(ctl, write, buffer, lenp, ppos);
673 return retv;
674}
675
676static int arlan_sysctl_infotxRing(ctl_table * ctl, int write,
677 void __user *buffer, size_t * lenp, loff_t *ppos)
678{
679 int i;
680 int retv, pos, devnum;
681 struct arlan_private *priva = NULL;
682
683 pos = 0;
684 devnum = ctl->procname[5] - '0';
685 if (arlan_device[devnum] == NULL)
686 {
687 pos += sprintf(arlan_drive_info + pos, "No device found here \n");
688 goto final;
689 }
690 else
691 priva = netdev_priv(arlan_device[devnum]);
692 if (priva == NULL)
693 {
694 printk(KERN_WARNING " Could not find the device private in arlan procsys, bad\n ");
695 return -1;
696 }
697 memcpy_fromio(priva->conf, priva->card, sizeof(struct arlan_shmem));
698 SARLBNpln(u_char, txBuffer, 0x800);
699final:
700 *lenp = pos;
701 retv = proc_dostring(ctl, write, buffer, lenp, ppos);
702 return retv;
703}
704
705static int arlan_sysctl_inforxRing(ctl_table * ctl, int write,
706 void __user *buffer, size_t * lenp, loff_t *ppos)
707{
708 int i;
709 int retv, pos, devnum;
710 struct arlan_private *priva = NULL;
711
712 pos = 0;
713 devnum = ctl->procname[5] - '0';
714 if (arlan_device[devnum] == NULL)
715 {
716 pos += sprintf(arlan_drive_info + pos, "No device found here \n");
717 goto final;
718 } else
719 priva = netdev_priv(arlan_device[devnum]);
720 if (priva == NULL)
721 {
722 printk(KERN_WARNING " Could not find the device private in arlan procsys, bad\n ");
723 return -1;
724 }
725 memcpy_fromio(priva->conf, priva->card, sizeof(struct arlan_shmem));
726 SARLBNpln(u_char, rxBuffer, 0x800);
727final:
728 *lenp = pos;
729 retv = proc_dostring(ctl, write, buffer, lenp, ppos);
730 return retv;
731}
732
733static int arlan_sysctl_info18(ctl_table * ctl, int write,
734 void __user *buffer, size_t * lenp, loff_t *ppos)
735{
736 int i;
737 int retv, pos, devnum;
738 struct arlan_private *priva = NULL;
739
740 pos = 0;
741 devnum = ctl->procname[5] - '0';
742 if (arlan_device[devnum] == NULL)
743 {
744 pos += sprintf(arlan_drive_info + pos, "No device found here \n");
745 goto final;
746 }
747 else
748 priva = netdev_priv(arlan_device[devnum]);
749 if (priva == NULL)
750 {
751 printk(KERN_WARNING " Could not find the device private in arlan procsys, bad\n ");
752 return -1;
753 }
754 memcpy_fromio(priva->conf, priva->card, sizeof(struct arlan_shmem));
755 SARLBNpln(u_char, _18, 0x800);
756
757final:
758 *lenp = pos;
759 retv = proc_dostring(ctl, write, buffer, lenp, ppos);
760 return retv;
761}
762
763
764#endif /* #ifdef ARLAN_PROC_SHM_DUMP */
765
766
767static char conf_reset_result[200];
768
769static int arlan_configure(ctl_table * ctl, int write,
770 void __user *buffer, size_t * lenp, loff_t *ppos)
771{
772 int pos = 0;
773 int devnum = ctl->procname[6] - '0';
774 struct arlan_private *priv;
775
776 if (devnum < 0 || devnum > MAX_ARLANS - 1)
777 {
778 printk(KERN_WARNING "too strange devnum in procfs parse\n ");
779 return -1;
780 }
781 else if (arlan_device[devnum] != NULL)
782 {
783 priv = netdev_priv(arlan_device[devnum]);
784
785 arlan_command(arlan_device[devnum], ARLAN_COMMAND_CLEAN_AND_CONF);
786 }
787 else
788 return -1;
789
790 *lenp = pos;
791 return proc_dostring(ctl, write, buffer, lenp, ppos);
792}
793
794static int arlan_sysctl_reset(ctl_table * ctl, int write,
795 void __user *buffer, size_t * lenp, loff_t *ppos)
796{
797 int pos = 0;
798 int devnum = ctl->procname[5] - '0';
799 struct arlan_private *priv;
800
801 if (devnum < 0 || devnum > MAX_ARLANS - 1)
802 {
803 printk(KERN_WARNING "too strange devnum in procfs parse\n ");
804 return -1;
805 }
806 else if (arlan_device[devnum] != NULL)
807 {
808 priv = netdev_priv(arlan_device[devnum]);
809 arlan_command(arlan_device[devnum], ARLAN_COMMAND_CLEAN_AND_RESET);
810
811 } else
812 return -1;
813 *lenp = pos + 3;
814 return proc_dostring(ctl, write, buffer, lenp, ppos);
815}
816
817
818/* Place files in /proc/sys/dev/arlan */
819#define CTBLN(num,card,nam) \
820 { .ctl_name = num,\
821 .procname = #nam,\
822 .data = &(arlan_conf[card].nam),\
823 .maxlen = sizeof(int), .mode = 0600, .proc_handler = &proc_dointvec}
824#ifdef ARLAN_DEBUGGING
825
826#define ARLAN_PROC_DEBUG_ENTRIES \
827 { .ctl_name = 48, .procname = "entry_exit_debug",\
828 .data = &arlan_entry_and_exit_debug,\
829 .maxlen = sizeof(int), .mode = 0600, .proc_handler = &proc_dointvec},\
830 { .ctl_name = 49, .procname = "debug", .data = &arlan_debug,\
831 .maxlen = sizeof(int), .mode = 0600, .proc_handler = &proc_dointvec},
832#else
833#define ARLAN_PROC_DEBUG_ENTRIES
834#endif
835
836#define ARLAN_SYSCTL_TABLE_TOTAL(cardNo)\
837 CTBLN(1,cardNo,spreadingCode),\
838 CTBLN(2,cardNo, channelNumber),\
839 CTBLN(3,cardNo, scramblingDisable),\
840 CTBLN(4,cardNo, txAttenuation),\
841 CTBLN(5,cardNo, systemId), \
842 CTBLN(6,cardNo, maxDatagramSize),\
843 CTBLN(7,cardNo, maxFrameSize),\
844 CTBLN(8,cardNo, maxRetries),\
845 CTBLN(9,cardNo, receiveMode),\
846 CTBLN(10,cardNo, priority),\
847 CTBLN(11,cardNo, rootOrRepeater),\
848 CTBLN(12,cardNo, SID),\
849 CTBLN(13,cardNo, registrationMode),\
850 CTBLN(14,cardNo, registrationFill),\
851 CTBLN(15,cardNo, localTalkAddress),\
852 CTBLN(16,cardNo, codeFormat),\
853 CTBLN(17,cardNo, numChannels),\
854 CTBLN(18,cardNo, channel1),\
855 CTBLN(19,cardNo, channel2),\
856 CTBLN(20,cardNo, channel3),\
857 CTBLN(21,cardNo, channel4),\
858 CTBLN(22,cardNo, txClear),\
859 CTBLN(23,cardNo, txRetries),\
860 CTBLN(24,cardNo, txRouting),\
861 CTBLN(25,cardNo, txScrambled),\
862 CTBLN(26,cardNo, rxParameter),\
863 CTBLN(27,cardNo, txTimeoutMs),\
864 CTBLN(28,cardNo, waitCardTimeout),\
865 CTBLN(29,cardNo, channelSet), \
866 {.ctl_name = 30, .procname = "name",\
867 .data = arlan_conf[cardNo].siteName,\
868 .maxlen = 16, .mode = 0600, .proc_handler = &proc_dostring},\
869 CTBLN(31,cardNo,waitTime),\
870 CTBLN(32,cardNo,lParameter),\
871 CTBLN(33,cardNo,_15),\
872 CTBLN(34,cardNo,headerSize),\
873 CTBLN(36,cardNo,tx_delay_ms),\
874 CTBLN(37,cardNo,retries),\
875 CTBLN(38,cardNo,ReTransmitPacketMaxSize),\
876 CTBLN(39,cardNo,waitReTransmitPacketMaxSize),\
877 CTBLN(40,cardNo,fastReTransCount),\
878 CTBLN(41,cardNo,driverRetransmissions),\
879 CTBLN(42,cardNo,txAckTimeoutMs),\
880 CTBLN(43,cardNo,registrationInterrupts),\
881 CTBLN(44,cardNo,hardwareType),\
882 CTBLN(45,cardNo,radioType),\
883 CTBLN(46,cardNo,writeEEPROM),\
884 CTBLN(47,cardNo,writeRadioType),\
885 ARLAN_PROC_DEBUG_ENTRIES\
886 CTBLN(50,cardNo,in_speed),\
887 CTBLN(51,cardNo,out_speed),\
888 CTBLN(52,cardNo,in_speed10),\
889 CTBLN(53,cardNo,out_speed10),\
890 CTBLN(54,cardNo,in_speed_max),\
891 CTBLN(55,cardNo,out_speed_max),\
892 CTBLN(56,cardNo,measure_rate),\
893 CTBLN(57,cardNo,pre_Command_Wait),\
894 CTBLN(58,cardNo,rx_tweak1),\
895 CTBLN(59,cardNo,rx_tweak2),\
896 CTBLN(60,cardNo,tx_queue_len),\
897
898
899
900static ctl_table arlan_conf_table0[] =
901{
902 ARLAN_SYSCTL_TABLE_TOTAL(0)
903
904#ifdef ARLAN_PROC_SHM_DUMP
905 {
906 .ctl_name = 150,
907 .procname = "arlan0-txRing",
908 .data = &arlan_drive_info,
909 .maxlen = ARLAN_STR_SIZE,
910 .mode = 0400,
911 .proc_handler = &arlan_sysctl_infotxRing,
912 },
913 {
914 .ctl_name = 151,
915 .procname = "arlan0-rxRing",
916 .data = &arlan_drive_info,
917 .maxlen = ARLAN_STR_SIZE,
918 .mode = 0400,
919 .proc_handler = &arlan_sysctl_inforxRing,
920 },
921 {
922 .ctl_name = 152,
923 .procname = "arlan0-18",
924 .data = &arlan_drive_info,
925 .maxlen = ARLAN_STR_SIZE,
926 .mode = 0400,
927 .proc_handler = &arlan_sysctl_info18,
928 },
929 {
930 .ctl_name = 153,
931 .procname = "arlan0-ring",
932 .data = &arlan_drive_info,
933 .maxlen = ARLAN_STR_SIZE,
934 .mode = 0400,
935 .proc_handler = &arlan_sysctl_info161719,
936 },
937 {
938 .ctl_name = 154,
939 .procname = "arlan0-shm-cpy",
940 .data = &arlan_drive_info,
941 .maxlen = ARLAN_STR_SIZE,
942 .mode = 0400,
943 .proc_handler = &arlan_sysctl_info,
944 },
945#endif
946 {
947 .ctl_name = 155,
948 .procname = "config0",
949 .data = &conf_reset_result,
950 .maxlen = 100,
951 .mode = 0400,
952 .proc_handler = &arlan_configure
953 },
954 {
955 .ctl_name = 156,
956 .procname = "reset0",
957 .data = &conf_reset_result,
958 .maxlen = 100,
959 .mode = 0400,
960 .proc_handler = &arlan_sysctl_reset,
961 },
962 { .ctl_name = 0 }
963};
964
965static ctl_table arlan_conf_table1[] =
966{
967
968 ARLAN_SYSCTL_TABLE_TOTAL(1)
969
970#ifdef ARLAN_PROC_SHM_DUMP
971 {
972 .ctl_name = 150,
973 .procname = "arlan1-txRing",
974 .data = &arlan_drive_info,
975 .maxlen = ARLAN_STR_SIZE,
976 .mode = 0400,
977 .proc_handler = &arlan_sysctl_infotxRing,
978 },
979 {
980 .ctl_name = 151,
981 .procname = "arlan1-rxRing",
982 .data = &arlan_drive_info,
983 .maxlen = ARLAN_STR_SIZE,
984 .mode = 0400,
985 .proc_handler = &arlan_sysctl_inforxRing,
986 },
987 {
988 .ctl_name = 152,
989 .procname = "arlan1-18",
990 .data = &arlan_drive_info,
991 .maxlen = ARLAN_STR_SIZE,
992 .mode = 0400,
993 .proc_handler = &arlan_sysctl_info18,
994 },
995 {
996 .ctl_name = 153,
997 .procname = "arlan1-ring",
998 .data = &arlan_drive_info,
999 .maxlen = ARLAN_STR_SIZE,
1000 .mode = 0400,
1001 .proc_handler = &arlan_sysctl_info161719,
1002 },
1003 {
1004 .ctl_name = 154,
1005 .procname = "arlan1-shm-cpy",
1006 .data = &arlan_drive_info,
1007 .maxlen = ARLAN_STR_SIZE,
1008 .mode = 0400,
1009 .proc_handler = &arlan_sysctl_info,
1010 },
1011#endif
1012 {
1013 .ctl_name = 155,
1014 .procname = "config1",
1015 .data = &conf_reset_result,
1016 .maxlen = 100,
1017 .mode = 0400,
1018 .proc_handler = &arlan_configure,
1019 },
1020 {
1021 .ctl_name = 156,
1022 .procname = "reset1",
1023 .data = &conf_reset_result,
1024 .maxlen = 100,
1025 .mode = 0400,
1026 .proc_handler = &arlan_sysctl_reset,
1027 },
1028 { .ctl_name = 0 }
1029};
1030
1031static ctl_table arlan_conf_table2[] =
1032{
1033
1034 ARLAN_SYSCTL_TABLE_TOTAL(2)
1035
1036#ifdef ARLAN_PROC_SHM_DUMP
1037 {
1038 .ctl_name = 150,
1039 .procname = "arlan2-txRing",
1040 .data = &arlan_drive_info,
1041 .maxlen = ARLAN_STR_SIZE,
1042 .mode = 0400,
1043 .proc_handler = &arlan_sysctl_infotxRing,
1044 },
1045 {
1046 .ctl_name = 151,
1047 .procname = "arlan2-rxRing",
1048 .data = &arlan_drive_info,
1049 .maxlen = ARLAN_STR_SIZE,
1050 .mode = 0400,
1051 .proc_handler = &arlan_sysctl_inforxRing,
1052 },
1053 {
1054 .ctl_name = 152,
1055 .procname = "arlan2-18",
1056 .data = &arlan_drive_info,
1057 .maxlen = ARLAN_STR_SIZE,
1058 .mode = 0400,
1059 .proc_handler = &arlan_sysctl_info18,
1060 },
1061 {
1062 .ctl_name = 153,
1063 .procname = "arlan2-ring",
1064 .data = &arlan_drive_info,
1065 .maxlen = ARLAN_STR_SIZE,
1066 .mode = 0400,
1067 .proc_handler = &arlan_sysctl_info161719,
1068 },
1069 {
1070 .ctl_name = 154,
1071 .procname = "arlan2-shm-cpy",
1072 .data = &arlan_drive_info,
1073 .maxlen = ARLAN_STR_SIZE,
1074 .mode = 0400,
1075 .proc_handler = &arlan_sysctl_info,
1076 },
1077#endif
1078 {
1079 .ctl_name = 155,
1080 .procname = "config2",
1081 .data = &conf_reset_result,
1082 .maxlen = 100,
1083 .mode = 0400,
1084 .proc_handler = &arlan_configure,
1085 },
1086 {
1087 .ctl_name = 156,
1088 .procname = "reset2",
1089 .data = &conf_reset_result,
1090 .maxlen = 100,
1091 .mode = 0400,
1092 .proc_handler = &arlan_sysctl_reset,
1093 },
1094 { .ctl_name = 0 }
1095};
1096
1097static ctl_table arlan_conf_table3[] =
1098{
1099
1100 ARLAN_SYSCTL_TABLE_TOTAL(3)
1101
1102#ifdef ARLAN_PROC_SHM_DUMP
1103 {
1104 .ctl_name = 150,
1105 .procname = "arlan3-txRing",
1106 .data = &arlan_drive_info,
1107 .maxlen = ARLAN_STR_SIZE,
1108 .mode = 0400,
1109 .proc_handler = &arlan_sysctl_infotxRing,
1110 },
1111 {
1112 .ctl_name = 151,
1113 .procname = "arlan3-rxRing",
1114 .data = &arlan_drive_info,
1115 .maxlen = ARLAN_STR_SIZE,
1116 .mode = 0400,
1117 .proc_handler = &arlan_sysctl_inforxRing,
1118 },
1119 {
1120 .ctl_name = 152,
1121 .procname = "arlan3-18",
1122 .data = &arlan_drive_info,
1123 .maxlen = ARLAN_STR_SIZE,
1124 .mode = 0400,
1125 .proc_handler = &arlan_sysctl_info18,
1126 },
1127 {
1128 .ctl_name = 153,
1129 .procname = "arlan3-ring",
1130 .data = &arlan_drive_info,
1131 .maxlen = ARLAN_STR_SIZE,
1132 .mode = 0400,
1133 .proc_handler = &arlan_sysctl_info161719,
1134 },
1135 {
1136 .ctl_name = 154,
1137 .procname = "arlan3-shm-cpy",
1138 .data = &arlan_drive_info,
1139 .maxlen = ARLAN_STR_SIZE,
1140 .mode = 0400,
1141 .proc_handler = &arlan_sysctl_info,
1142 },
1143#endif
1144 {
1145 .ctl_name = 155,
1146 .procname = "config3",
1147 .data = &conf_reset_result,
1148 .maxlen = 100,
1149 .mode = 0400,
1150 .proc_handler = &arlan_configure,
1151 },
1152 {
1153 .ctl_name = 156,
1154 .procname = "reset3",
1155 .data = &conf_reset_result,
1156 .maxlen = 100,
1157 .mode = 0400,
1158 .proc_handler = &arlan_sysctl_reset,
1159 },
1160 { .ctl_name = 0 }
1161};
1162
1163
1164
1165static ctl_table arlan_table[] =
1166{
1167 {
1168 .ctl_name = 0,
1169 .procname = "arlan0",
1170 .maxlen = 0,
1171 .mode = 0600,
1172 .child = arlan_conf_table0,
1173 },
1174 {
1175 .ctl_name = 0,
1176 .procname = "arlan1",
1177 .maxlen = 0,
1178 .mode = 0600,
1179 .child = arlan_conf_table1,
1180 },
1181 {
1182 .ctl_name = 0,
1183 .procname = "arlan2",
1184 .maxlen = 0,
1185 .mode = 0600,
1186 .child = arlan_conf_table2,
1187 },
1188 {
1189 .ctl_name = 0,
1190 .procname = "arlan3",
1191 .maxlen = 0,
1192 .mode = 0600,
1193 .child = arlan_conf_table3,
1194 },
1195 { .ctl_name = 0 }
1196};
1197
1198#else
1199
1200static ctl_table arlan_table[MAX_ARLANS + 1] =
1201{
1202 { .ctl_name = 0 }
1203};
1204#endif
1205
1206
1207// static int mmtu = 1234;
1208
1209static ctl_table arlan_root_table[] =
1210{
1211 {
1212 .ctl_name = CTL_ARLAN,
1213 .procname = "arlan",
1214 .maxlen = 0,
1215 .mode = 0555,
1216 .child = arlan_table,
1217 },
1218 { .ctl_name = 0 }
1219};
1220
1221/* Make sure that /proc/sys/dev is there */
1222//static ctl_table arlan_device_root_table[] =
1223//{
1224// {CTL_DEV, "dev", NULL, 0, 0555, arlan_root_table},
1225// {0}
1226//};
1227
1228
1229static struct ctl_table_header *arlan_device_sysctl_header;
1230
1231int __init init_arlan_proc(void)
1232{
1233
1234 int i = 0;
1235 if (arlan_device_sysctl_header)
1236 return 0;
1237 for (i = 0; i < MAX_ARLANS && arlan_device[i]; i++)
1238 arlan_table[i].ctl_name = i + 1;
1239 arlan_device_sysctl_header = register_sysctl_table(arlan_root_table);
1240 if (!arlan_device_sysctl_header)
1241 return -1;
1242
1243 return 0;
1244
1245}
1246
1247void __exit cleanup_arlan_proc(void)
1248{
1249 unregister_sysctl_table(arlan_device_sysctl_header);
1250 arlan_device_sysctl_header = NULL;
1251
1252}
1253#endif
diff --git a/drivers/net/wireless/arlan.h b/drivers/net/wireless/arlan.h
deleted file mode 100644
index fb3ad51a1caf..000000000000
--- a/drivers/net/wireless/arlan.h
+++ /dev/null
@@ -1,539 +0,0 @@
1/*
2 * Copyright (C) 1997 Cullen Jennings
3 * Copyright (C) 1998 Elmer.Joandi@ut.ee, +37-255-13500
4 * GNU General Public License applies
5 */
6
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/skbuff.h>
11#include <linux/if_ether.h> /* For the statistics structure. */
12#include <linux/if_arp.h> /* For ARPHRD_ETHER */
13#include <linux/ptrace.h>
14#include <linux/ioport.h>
15#include <linux/in.h>
16#include <linux/slab.h>
17#include <linux/string.h>
18#include <linux/timer.h>
19
20#include <linux/init.h>
21#include <linux/bitops.h>
22#include <asm/system.h>
23#include <asm/io.h>
24#include <linux/errno.h>
25#include <linux/delay.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28
29
30//#define ARLAN_DEBUGGING 1
31
32#define ARLAN_PROC_INTERFACE
33#define MAX_ARLANS 4 /* not more than 4 ! */
34#define ARLAN_PROC_SHM_DUMP /* shows all card registers, makes driver way larger */
35
36#define ARLAN_MAX_MULTICAST_ADDRS 16
37#define ARLAN_RCV_CLEAN 0
38#define ARLAN_RCV_PROMISC 1
39#define ARLAN_RCV_CONTROL 2
40
41#ifdef CONFIG_PROC_FS
42extern int init_arlan_proc(void);
43extern void cleanup_arlan_proc(void);
44#else
45#define init_arlan_proc() ({ 0; })
46#define cleanup_arlan_proc() do { } while (0)
47#endif
48
49extern struct net_device *arlan_device[MAX_ARLANS];
50extern int arlan_debug;
51extern int arlan_entry_debug;
52extern int arlan_exit_debug;
53extern int testMemory;
54extern int arlan_command(struct net_device * dev, int command);
55
56#define SIDUNKNOWN -1
57#define radioNodeIdUNKNOWN -1
58#define irqUNKNOWN 0
59#define debugUNKNOWN 0
60#define testMemoryUNKNOWN 1
61#define spreadingCodeUNKNOWN 0
62#define channelNumberUNKNOWN 0
63#define channelSetUNKNOWN 0
64#define systemIdUNKNOWN -1
65#define registrationModeUNKNOWN -1
66
67
68#define IFDEBUG( L ) if ( (L) & arlan_debug )
69#define ARLAN_FAKE_HDR_LEN 12
70
71#ifdef ARLAN_DEBUGGING
72 #define DEBUG 1
73 #define ARLAN_ENTRY_EXIT_DEBUGGING 1
74 #define ARLAN_DEBUG(a,b) printk(KERN_DEBUG a, b)
75#else
76 #define ARLAN_DEBUG(a,b)
77#endif
78
79#define ARLAN_SHMEM_SIZE 0x2000
80
81struct arlan_shmem
82{
83 /* Header Signature */
84 volatile char textRegion[48];
85 volatile u_char resetFlag;
86 volatile u_char diagnosticInfo;
87 volatile u_short diagnosticOffset;
88 volatile u_char _1[12];
89 volatile u_char lanCardNodeId[6];
90 volatile u_char broadcastAddress[6];
91 volatile u_char hardwareType;
92 volatile u_char majorHardwareVersion;
93 volatile u_char minorHardwareVersion;
94 volatile u_char radioModule;// shows EEPROM, can be overridden at 0x111
95 volatile u_char defaultChannelSet; // shows EEProm, can be overriiden at 0x10A
96 volatile u_char _2[47];
97
98 /* Control/Status Block - 0x0080 */
99 volatile u_char interruptInProgress; /* not used by lancpu */
100 volatile u_char cntrlRegImage; /* not used by lancpu */
101 volatile u_char _3[13];
102 volatile u_char dumpByte;
103 volatile u_char commandByte; /* non-zero = active */
104 volatile u_char commandParameter[15];
105
106 /* Receive Status - 0x00a0 */
107 volatile u_char rxStatus; /* 1- data, 2-control, 0xff - registr change */
108 volatile u_char rxFrmType;
109 volatile u_short rxOffset;
110 volatile u_short rxLength;
111 volatile u_char rxSrc[6];
112 volatile u_char rxBroadcastFlag;
113 volatile u_char rxQuality;
114 volatile u_char scrambled;
115 volatile u_char _4[1];
116
117 /* Transmit Status - 0x00b0 */
118 volatile u_char txStatus;
119 volatile u_char txAckQuality;
120 volatile u_char numRetries;
121 volatile u_char _5[14];
122 volatile u_char registeredRouter[6];
123 volatile u_char backboneRouter[6];
124 volatile u_char registrationStatus;
125 volatile u_char configuredStatusFlag;
126 volatile u_char _6[1];
127 volatile u_char ultimateDestAddress[6];
128 volatile u_char immedDestAddress[6];
129 volatile u_char immedSrcAddress[6];
130 volatile u_short rxSequenceNumber;
131 volatile u_char assignedLocaltalkAddress;
132 volatile u_char _7[27];
133
134 /* System Parameter Block */
135
136 /* - Driver Parameters (Novell Specific) */
137
138 volatile u_short txTimeout;
139 volatile u_short transportTime;
140 volatile u_char _8[4];
141
142 /* - Configuration Parameters */
143 volatile u_char irqLevel;
144 volatile u_char spreadingCode;
145 volatile u_char channelSet;
146 volatile u_char channelNumber;
147 volatile u_short radioNodeId;
148 volatile u_char _9[2];
149 volatile u_char scramblingDisable;
150 volatile u_char radioType;
151 volatile u_short routerId;
152 volatile u_char _10[9];
153 volatile u_char txAttenuation;
154 volatile u_char systemId[4];
155 volatile u_short globalChecksum;
156 volatile u_char _11[4];
157 volatile u_short maxDatagramSize;
158 volatile u_short maxFrameSize;
159 volatile u_char maxRetries;
160 volatile u_char receiveMode;
161 volatile u_char priority;
162 volatile u_char rootOrRepeater;
163 volatile u_char specifiedRouter[6];
164 volatile u_short fastPollPeriod;
165 volatile u_char pollDecay;
166 volatile u_char fastPollDelay[2];
167 volatile u_char arlThreshold;
168 volatile u_char arlDecay;
169 volatile u_char _12[1];
170 volatile u_short specRouterTimeout;
171 volatile u_char _13[5];
172
173 /* Scrambled Area */
174 volatile u_char SID[4];
175 volatile u_char encryptionKey[12];
176 volatile u_char _14[2];
177 volatile u_char waitTime[2];
178 volatile u_char lParameter[2];
179 volatile u_char _15[3];
180 volatile u_short headerSize;
181 volatile u_short sectionChecksum;
182
183 volatile u_char registrationMode;
184 volatile u_char registrationFill;
185 volatile u_short pollPeriod;
186 volatile u_short refreshPeriod;
187 volatile u_char name[16];
188 volatile u_char NID[6];
189 volatile u_char localTalkAddress;
190 volatile u_char codeFormat;
191 volatile u_char numChannels;
192 volatile u_char channel1;
193 volatile u_char channel2;
194 volatile u_char channel3;
195 volatile u_char channel4;
196 volatile u_char SSCode[59];
197
198 volatile u_char _16[0xC0];
199 volatile u_short auxCmd;
200 volatile u_char dumpPtr[4];
201 volatile u_char dumpVal;
202 volatile u_char _17[0x6A];
203 volatile u_char wireTest;
204 volatile u_char _18[14];
205
206 /* Statistics Block - 0x0300 */
207 volatile u_char hostcpuLock;
208 volatile u_char lancpuLock;
209 volatile u_char resetTime[18];
210
211 volatile u_char numDatagramsTransmitted[4];
212 volatile u_char numReTransmissions[4];
213 volatile u_char numFramesDiscarded[4];
214 volatile u_char numDatagramsReceived[4];
215 volatile u_char numDuplicateReceivedFrames[4];
216 volatile u_char numDatagramsDiscarded[4];
217
218 volatile u_short maxNumReTransmitDatagram;
219 volatile u_short maxNumReTransmitFrames;
220 volatile u_short maxNumConsecutiveDuplicateFrames;
221 /* misaligned here so we have to go to characters */
222
223 volatile u_char numBytesTransmitted[4];
224 volatile u_char numBytesReceived[4];
225 volatile u_char numCRCErrors[4];
226 volatile u_char numLengthErrors[4];
227 volatile u_char numAbortErrors[4];
228 volatile u_char numTXUnderruns[4];
229 volatile u_char numRXOverruns[4];
230 volatile u_char numHoldOffs[4];
231 volatile u_char numFramesTransmitted[4];
232 volatile u_char numFramesReceived[4];
233 volatile u_char numReceiveFramesLost[4];
234 volatile u_char numRXBufferOverflows[4];
235 volatile u_char numFramesDiscardedAddrMismatch[4];
236 volatile u_char numFramesDiscardedSIDMismatch[4];
237 volatile u_char numPollsTransmistted[4];
238 volatile u_char numPollAcknowledges[4];
239 volatile u_char numStatusTimeouts[4];
240 volatile u_char numNACKReceived[4];
241
242 volatile u_char _19[0x86];
243
244 volatile u_char txBuffer[0x800];
245 volatile u_char rxBuffer[0x800];
246
247 volatile u_char _20[0x800];
248 volatile u_char _21[0x3fb];
249 volatile u_char configStatus;
250 volatile u_char _22;
251 volatile u_char progIOCtrl;
252 volatile u_char shareMBase;
253 volatile u_char controlRegister;
254};
255
256struct arlan_conf_stru {
257 int spreadingCode;
258 int channelSet;
259 int channelNumber;
260 int scramblingDisable;
261 int txAttenuation;
262 int systemId;
263 int maxDatagramSize;
264 int maxFrameSize;
265 int maxRetries;
266 int receiveMode;
267 int priority;
268 int rootOrRepeater;
269 int SID;
270 int radioNodeId;
271 int registrationMode;
272 int registrationFill;
273 int localTalkAddress;
274 int codeFormat;
275 int numChannels;
276 int channel1;
277 int channel2;
278 int channel3;
279 int channel4;
280 int txClear;
281 int txRetries;
282 int txRouting;
283 int txScrambled;
284 int rxParameter;
285 int txTimeoutMs;
286 int txAckTimeoutMs;
287 int waitCardTimeout;
288 int waitTime;
289 int lParameter;
290 int _15;
291 int headerSize;
292 int retries;
293 int tx_delay_ms;
294 int waitReTransmitPacketMaxSize;
295 int ReTransmitPacketMaxSize;
296 int fastReTransCount;
297 int driverRetransmissions;
298 int registrationInterrupts;
299 int hardwareType;
300 int radioType;
301 int writeRadioType;
302 int writeEEPROM;
303 char siteName[17];
304 int measure_rate;
305 int in_speed;
306 int out_speed;
307 int in_speed10;
308 int out_speed10;
309 int in_speed_max;
310 int out_speed_max;
311 int pre_Command_Wait;
312 int rx_tweak1;
313 int rx_tweak2;
314 int tx_queue_len;
315};
316
317extern struct arlan_conf_stru arlan_conf[MAX_ARLANS];
318
319struct TxParam
320{
321 volatile short offset;
322 volatile short length;
323 volatile u_char dest[6];
324 volatile unsigned char clear;
325 volatile unsigned char retries;
326 volatile unsigned char routing;
327 volatile unsigned char scrambled;
328};
329
330#define TX_RING_SIZE 2
331/* Information that need to be kept for each board. */
332struct arlan_private {
333 struct arlan_shmem __iomem * card;
334 struct arlan_shmem * conf;
335
336 struct arlan_conf_stru * Conf;
337 int bad;
338 int reset;
339 unsigned long lastReset;
340 struct timer_list timer;
341 struct timer_list tx_delay_timer;
342 struct timer_list tx_retry_timer;
343 struct timer_list rx_check_timer;
344
345 int registrationLostCount;
346 int reRegisterExp;
347 int irq_test_done;
348
349 struct TxParam txRing[TX_RING_SIZE];
350 char reTransmitBuff[0x800];
351 int txLast;
352 unsigned ReTransmitRequested;
353 unsigned long tx_done_delayed;
354 unsigned long registrationLastSeen;
355
356 unsigned long tx_last_sent;
357 unsigned long tx_last_cleared;
358 unsigned long retransmissions;
359 unsigned long interrupt_ack_requested;
360 spinlock_t lock;
361 unsigned long waiting_command_mask;
362 unsigned long card_polling_interval;
363 unsigned long last_command_buff_free_time;
364
365 int under_reset;
366 int under_config;
367 int rx_command_given;
368 int tx_command_given;
369 unsigned long interrupt_processing_active;
370 unsigned long last_rx_int_ack_time;
371 unsigned long in_bytes;
372 unsigned long out_bytes;
373 unsigned long in_time;
374 unsigned long out_time;
375 unsigned long in_time10;
376 unsigned long out_time10;
377 unsigned long in_bytes10;
378 unsigned long out_bytes10;
379 int init_etherdev_alloc;
380};
381
382
383
384#define ARLAN_CLEAR 0x00
385#define ARLAN_RESET 0x01
386#define ARLAN_CHANNEL_ATTENTION 0x02
387#define ARLAN_INTERRUPT_ENABLE 0x04
388#define ARLAN_CLEAR_INTERRUPT 0x08
389#define ARLAN_POWER 0x40
390#define ARLAN_ACCESS 0x80
391
392#define ARLAN_COM_CONF 0x01
393#define ARLAN_COM_RX_ENABLE 0x03
394#define ARLAN_COM_RX_ABORT 0x04
395#define ARLAN_COM_TX_ENABLE 0x05
396#define ARLAN_COM_TX_ABORT 0x06
397#define ARLAN_COM_NOP 0x07
398#define ARLAN_COM_STANDBY 0x08
399#define ARLAN_COM_ACTIVATE 0x09
400#define ARLAN_COM_GOTO_SLOW_POLL 0x0a
401#define ARLAN_COM_INT 0x80
402
403
404#define TXLAST(dev) (((struct arlan_private *)netdev_priv(dev))->txRing[((struct arlan_private *)netdev_priv(dev))->txLast])
405#define TXHEAD(dev) (((struct arlan_private *)netdev_priv(dev))->txRing[0])
406#define TXTAIL(dev) (((struct arlan_private *)netdev_priv(dev))->txRing[1])
407
408#define TXBuffStart(dev) offsetof(struct arlan_shmem, txBuffer)
409#define TXBuffEnd(dev) offsetof(struct arlan_shmem, xxBuffer)
410
411#define READSHM(to,from,atype) {\
412 atype tmp;\
413 memcpy_fromio(&(tmp),&(from),sizeof(atype));\
414 to = tmp;\
415 }
416
417#define READSHMEM(from,atype)\
418 atype from; \
419 READSHM(from, arlan->from, atype);
420
421#define WRITESHM(to,from,atype) \
422 { atype tmpSHM = from;\
423 memcpy_toio(&(to),&tmpSHM,sizeof(atype));\
424 }
425
426#define DEBUGSHM(levelSHM,stringSHM,stuff,atype) \
427 { atype tmpSHM; \
428 memcpy_fromio(&tmpSHM,&(stuff),sizeof(atype));\
429 IFDEBUG(levelSHM) printk(stringSHM,tmpSHM);\
430 }
431
432#define WRITESHMB(to, val) \
433 writeb(val,&(to))
434#define READSHMB(to) \
435 readb(&(to))
436#define WRITESHMS(to, val) \
437 writew(val,&(to))
438#define READSHMS(to) \
439 readw(&(to))
440#define WRITESHMI(to, val) \
441 writel(val,&(to))
442#define READSHMI(to) \
443 readl(&(to))
444
445
446
447
448
449#define registrationBad(dev)\
450 ( ( READSHMB(((struct arlan_private *)netdev_priv(dev))->card->registrationMode) > 0) && \
451 ( READSHMB(((struct arlan_private *)netdev_priv(dev))->card->registrationStatus) == 0) )
452
453
454#define readControlRegister(dev)\
455 READSHMB(((struct arlan_private *)netdev_priv(dev))->card->cntrlRegImage)
456
457#define writeControlRegister(dev, v){\
458 WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->cntrlRegImage ,((v) &0xF) );\
459 WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->controlRegister ,(v) );}
460
461
462#define arlan_interrupt_lancpu(dev) {\
463 int cr; \
464 \
465 cr = readControlRegister(dev);\
466 if (cr & ARLAN_CHANNEL_ATTENTION){ \
467 writeControlRegister(dev, (cr & ~ARLAN_CHANNEL_ATTENTION));\
468 }else \
469 writeControlRegister(dev, (cr | ARLAN_CHANNEL_ATTENTION));\
470}
471
472#define clearChannelAttention(dev){ \
473 writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_CHANNEL_ATTENTION);}
474#define setHardwareReset(dev) {\
475 writeControlRegister(dev,readControlRegister(dev) | ARLAN_RESET);}
476#define clearHardwareReset(dev) {\
477 writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_RESET);}
478#define setInterruptEnable(dev){\
479 writeControlRegister(dev,readControlRegister(dev) | ARLAN_INTERRUPT_ENABLE) ;}
480#define clearInterruptEnable(dev){\
481 writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_INTERRUPT_ENABLE) ;}
482#define setClearInterrupt(dev){\
483 writeControlRegister(dev,readControlRegister(dev) | ARLAN_CLEAR_INTERRUPT) ;}
484#define clearClearInterrupt(dev){\
485 writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_CLEAR_INTERRUPT);}
486#define setPowerOff(dev){\
487 writeControlRegister(dev,readControlRegister(dev) | (ARLAN_POWER && ARLAN_ACCESS));\
488 writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_ACCESS);}
489#define setPowerOn(dev){\
490 writeControlRegister(dev,readControlRegister(dev) & ~(ARLAN_POWER)); }
491#define arlan_lock_card_access(dev){\
492 writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_ACCESS);}
493#define arlan_unlock_card_access(dev){\
494 writeControlRegister(dev,readControlRegister(dev) | ARLAN_ACCESS ); }
495
496
497
498
499#define ARLAN_COMMAND_RX 0x000001
500#define ARLAN_COMMAND_NOOP 0x000002
501#define ARLAN_COMMAND_NOOPINT 0x000004
502#define ARLAN_COMMAND_TX 0x000008
503#define ARLAN_COMMAND_CONF 0x000010
504#define ARLAN_COMMAND_RESET 0x000020
505#define ARLAN_COMMAND_TX_ABORT 0x000040
506#define ARLAN_COMMAND_RX_ABORT 0x000080
507#define ARLAN_COMMAND_POWERDOWN 0x000100
508#define ARLAN_COMMAND_POWERUP 0x000200
509#define ARLAN_COMMAND_SLOW_POLL 0x000400
510#define ARLAN_COMMAND_ACTIVATE 0x000800
511#define ARLAN_COMMAND_INT_ACK 0x001000
512#define ARLAN_COMMAND_INT_ENABLE 0x002000
513#define ARLAN_COMMAND_WAIT_NOW 0x004000
514#define ARLAN_COMMAND_LONG_WAIT_NOW 0x008000
515#define ARLAN_COMMAND_STANDBY 0x010000
516#define ARLAN_COMMAND_INT_RACK 0x020000
517#define ARLAN_COMMAND_INT_RENABLE 0x040000
518#define ARLAN_COMMAND_CONF_WAIT 0x080000
519#define ARLAN_COMMAND_TBUSY_CLEAR 0x100000
520#define ARLAN_COMMAND_CLEAN_AND_CONF (ARLAN_COMMAND_TX_ABORT\
521 | ARLAN_COMMAND_RX_ABORT\
522 | ARLAN_COMMAND_CONF)
523#define ARLAN_COMMAND_CLEAN_AND_RESET (ARLAN_COMMAND_TX_ABORT\
524 | ARLAN_COMMAND_RX_ABORT\
525 | ARLAN_COMMAND_RESET)
526
527
528
529#define ARLAN_DEBUG_CHAIN_LOCKS 0x00001
530#define ARLAN_DEBUG_RESET 0x00002
531#define ARLAN_DEBUG_TIMING 0x00004
532#define ARLAN_DEBUG_CARD_STATE 0x00008
533#define ARLAN_DEBUG_TX_CHAIN 0x00010
534#define ARLAN_DEBUG_MULTICAST 0x00020
535#define ARLAN_DEBUG_HEADER_DUMP 0x00040
536#define ARLAN_DEBUG_INTERRUPT 0x00080
537#define ARLAN_DEBUG_STARTUP 0x00100
538#define ARLAN_DEBUG_SHUTDOWN 0x00200
539
diff --git a/drivers/net/wireless/ath/Kconfig b/drivers/net/wireless/ath/Kconfig
index 6ce86cb37654..4e7a7fd695c8 100644
--- a/drivers/net/wireless/ath/Kconfig
+++ b/drivers/net/wireless/ath/Kconfig
@@ -1,6 +1,5 @@
1menuconfig ATH_COMMON 1menuconfig ATH_COMMON
2 tristate "Atheros Wireless Cards" 2 tristate "Atheros Wireless Cards"
3 depends on WLAN_80211
4 depends on CFG80211 3 depends on CFG80211
5 ---help--- 4 ---help---
6 This will enable the support for the Atheros wireless drivers. 5 This will enable the support for the Atheros wireless drivers.
diff --git a/drivers/net/wireless/ath/ar9170/Kconfig b/drivers/net/wireless/ath/ar9170/Kconfig
index 05918f1e685a..d7a4799d20fb 100644
--- a/drivers/net/wireless/ath/ar9170/Kconfig
+++ b/drivers/net/wireless/ath/ar9170/Kconfig
@@ -1,6 +1,6 @@
1config AR9170_USB 1config AR9170_USB
2 tristate "Atheros AR9170 802.11n USB support" 2 tristate "Atheros AR9170 802.11n USB support"
3 depends on USB && MAC80211 && WLAN_80211 3 depends on USB && MAC80211
4 select FW_LOADER 4 select FW_LOADER
5 help 5 help
6 This is a driver for the Atheros "otus" 802.11n USB devices. 6 This is a driver for the Atheros "otus" 802.11n USB devices.
diff --git a/drivers/net/wireless/ath/ath5k/Kconfig b/drivers/net/wireless/ath/ath5k/Kconfig
index 06d006675d7d..eb83b7b4d0e3 100644
--- a/drivers/net/wireless/ath/ath5k/Kconfig
+++ b/drivers/net/wireless/ath/ath5k/Kconfig
@@ -1,6 +1,6 @@
1config ATH5K 1config ATH5K
2 tristate "Atheros 5xxx wireless cards support" 2 tristate "Atheros 5xxx wireless cards support"
3 depends on PCI && MAC80211 && WLAN_80211 3 depends on PCI && MAC80211
4 select MAC80211_LEDS 4 select MAC80211_LEDS
5 select LEDS_CLASS 5 select LEDS_CLASS
6 select NEW_LEDS 6 select NEW_LEDS
diff --git a/drivers/net/wireless/ath/ath5k/led.c b/drivers/net/wireless/ath/ath5k/led.c
index b767c3b67b24..7ce98bd7c749 100644
--- a/drivers/net/wireless/ath/ath5k/led.c
+++ b/drivers/net/wireless/ath/ath5k/led.c
@@ -59,6 +59,8 @@ static const struct pci_device_id ath5k_led_devices[] = {
59 { ATH_SDEVICE(PCI_VENDOR_ID_COMPAQ, PCI_ANY_ID), ATH_LED(1, 1) }, 59 { ATH_SDEVICE(PCI_VENDOR_ID_COMPAQ, PCI_ANY_ID), ATH_LED(1, 1) },
60 /* Acer Aspire One A150 (maximlevitsky@gmail.com) */ 60 /* Acer Aspire One A150 (maximlevitsky@gmail.com) */
61 { ATH_SDEVICE(PCI_VENDOR_ID_FOXCONN, 0xe008), ATH_LED(3, 0) }, 61 { ATH_SDEVICE(PCI_VENDOR_ID_FOXCONN, 0xe008), ATH_LED(3, 0) },
62 /* Acer Aspire One AO531h AO751h (keng-yu.lin@canonical.com) */
63 { ATH_SDEVICE(PCI_VENDOR_ID_FOXCONN, 0xe00d), ATH_LED(3, 0) },
62 /* Acer Ferrari 5000 (russ.dill@gmail.com) */ 64 /* Acer Ferrari 5000 (russ.dill@gmail.com) */
63 { ATH_SDEVICE(PCI_VENDOR_ID_AMBIT, 0x0422), ATH_LED(1, 1) }, 65 { ATH_SDEVICE(PCI_VENDOR_ID_AMBIT, 0x0422), ATH_LED(1, 1) },
64 /* E-machines E510 (tuliom@gmail.com) */ 66 /* E-machines E510 (tuliom@gmail.com) */
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index 99ce066392a7..b735fb399fb1 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -3,7 +3,7 @@ config ATH9K_HW
3 3
4config ATH9K 4config ATH9K
5 tristate "Atheros 802.11n wireless cards support" 5 tristate "Atheros 802.11n wireless cards support"
6 depends on PCI && MAC80211 && WLAN_80211 6 depends on PCI && MAC80211
7 select ATH9K_HW 7 select ATH9K_HW
8 select MAC80211_LEDS 8 select MAC80211_LEDS
9 select LEDS_CLASS 9 select LEDS_CLASS
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 25531f231b67..329e6bc137ab 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -69,6 +69,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
69 int irq; 69 int irq;
70 int ret = 0; 70 int ret = 0;
71 struct ath_hw *ah; 71 struct ath_hw *ah;
72 char hw_name[64];
72 73
73 if (!pdev->dev.platform_data) { 74 if (!pdev->dev.platform_data) {
74 dev_err(&pdev->dev, "no platform data specified\n"); 75 dev_err(&pdev->dev, "no platform data specified\n");
@@ -133,14 +134,11 @@ static int ath_ahb_probe(struct platform_device *pdev)
133 } 134 }
134 135
135 ah = sc->sc_ah; 136 ah = sc->sc_ah;
137 ath9k_hw_name(ah, hw_name, sizeof(hw_name));
136 printk(KERN_INFO 138 printk(KERN_INFO
137 "%s: Atheros AR%s MAC/BB Rev:%x, " 139 "%s: %s mem=0x%lx, irq=%d\n",
138 "AR%s RF Rev:%x, mem=0x%lx, irq=%d\n",
139 wiphy_name(hw->wiphy), 140 wiphy_name(hw->wiphy),
140 ath_mac_bb_name(ah->hw_version.macVersion), 141 hw_name,
141 ah->hw_version.macRev,
142 ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
143 ah->hw_version.phyRev,
144 (unsigned long)mem, irq); 142 (unsigned long)mem, irq);
145 143
146 return 0; 144 return 0;
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 551f8801459f..238a5744d8e9 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -877,7 +877,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
877 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0); 877 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
878 878
879 /* find off_6_1; */ 879 /* find off_6_1; */
880 for (i = 6; i >= 0; i--) { 880 for (i = 6; i > 0; i--) {
881 regVal = REG_READ(ah, 0x7834); 881 regVal = REG_READ(ah, 0x7834);
882 regVal |= (1 << (20 + i)); 882 regVal |= (1 << (20 + i));
883 REG_WRITE(ah, 0x7834, regVal); 883 REG_WRITE(ah, 0x7834, regVal);
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 58167d861dc6..68db16690abf 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -1112,6 +1112,10 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1112 1112
1113 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1113 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1114 pModal->txEndToRxOn); 1114 pModal->txEndToRxOn);
1115
1116 if (AR_SREV_9271_10(ah))
1117 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1118 pModal->txEndToRxOn);
1115 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1119 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1116 pModal->thresh62); 1120 pModal->thresh62);
1117 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1121 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index cab17c6c8a37..111ff049f75d 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -30,8 +30,6 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, 30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31 struct ar5416_eeprom_def *pEepData, 31 struct ar5416_eeprom_def *pEepData,
32 u32 reg, u32 value); 32 u32 reg, u32 value);
33static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
34static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35 33
36MODULE_AUTHOR("Atheros Communications"); 34MODULE_AUTHOR("Atheros Communications");
37MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
@@ -454,21 +452,6 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
454 ah->power_mode = ATH9K_PM_UNDEFINED; 452 ah->power_mode = ATH9K_PM_UNDEFINED;
455} 453}
456 454
457static int ath9k_hw_rfattach(struct ath_hw *ah)
458{
459 bool rfStatus = false;
460 int ecode = 0;
461
462 rfStatus = ath9k_hw_init_rf(ah, &ecode);
463 if (!rfStatus) {
464 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
465 "RF setup failed, status: %u\n", ecode);
466 return ecode;
467 }
468
469 return 0;
470}
471
472static int ath9k_hw_rf_claim(struct ath_hw *ah) 455static int ath9k_hw_rf_claim(struct ath_hw *ah)
473{ 456{
474 u32 val; 457 u32 val;
@@ -585,9 +568,15 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
585 ah->eep_ops->get_eeprom_ver(ah), 568 ah->eep_ops->get_eeprom_ver(ah),
586 ah->eep_ops->get_eeprom_rev(ah)); 569 ah->eep_ops->get_eeprom_rev(ah));
587 570
588 ecode = ath9k_hw_rfattach(ah); 571 if (!AR_SREV_9280_10_OR_LATER(ah)) {
589 if (ecode != 0) 572 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
590 return ecode; 573 if (ecode) {
574 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
575 "Failed allocating banks for "
576 "external radio\n");
577 return ecode;
578 }
579 }
591 580
592 if (!AR_SREV_9100(ah)) { 581 if (!AR_SREV_9100(ah)) {
593 ath9k_hw_ani_setup(ah); 582 ath9k_hw_ani_setup(ah);
@@ -662,10 +651,13 @@ static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
662static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 651static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
663{ 652{
664 if (AR_SREV_9271(ah)) { 653 if (AR_SREV_9271(ah)) {
665 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0, 654 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
666 ARRAY_SIZE(ar9271Modes_9271_1_0), 6); 655 ARRAY_SIZE(ar9271Modes_9271), 6);
667 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0, 656 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
668 ARRAY_SIZE(ar9271Common_9271_1_0), 2); 657 ARRAY_SIZE(ar9271Common_9271), 2);
658 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
659 ar9271Modes_9271_1_0_only,
660 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
669 return; 661 return;
670 } 662 }
671 663
@@ -957,8 +949,14 @@ int ath9k_hw_init(struct ath_hw *ah)
957 ath9k_hw_init_cal_settings(ah); 949 ath9k_hw_init_cal_settings(ah);
958 950
959 ah->ani_function = ATH9K_ANI_ALL; 951 ah->ani_function = ATH9K_ANI_ALL;
960 if (AR_SREV_9280_10_OR_LATER(ah)) 952 if (AR_SREV_9280_10_OR_LATER(ah)) {
961 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 953 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
954 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
955 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
956 } else {
957 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
958 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
959 }
962 960
963 ath9k_hw_init_mode_regs(ah); 961 ath9k_hw_init_mode_regs(ah);
964 962
@@ -1037,6 +1035,22 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
1037 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 1035 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1038} 1036}
1039 1037
1038static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
1039{
1040 u32 lcr;
1041 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
1042
1043 lcr = REG_READ(ah , 0x5100c);
1044 lcr |= 0x80;
1045
1046 REG_WRITE(ah, 0x5100c, lcr);
1047 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1048 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1049
1050 lcr &= ~0x80;
1051 REG_WRITE(ah, 0x5100c, lcr);
1052}
1053
1040static void ath9k_hw_init_pll(struct ath_hw *ah, 1054static void ath9k_hw_init_pll(struct ath_hw *ah,
1041 struct ath9k_channel *chan) 1055 struct ath9k_channel *chan)
1042{ 1056{
@@ -1100,6 +1114,26 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
1100 } 1114 }
1101 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1115 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1102 1116
1117 /* Switch the core clock for ar9271 to 117Mhz */
1118 if (AR_SREV_9271(ah)) {
1119 if ((pll == 0x142c) || (pll == 0x2850) ) {
1120 udelay(500);
1121 /* set CLKOBS to output AHB clock */
1122 REG_WRITE(ah, 0x7020, 0xe);
1123 /*
1124 * 0x304: 117Mhz, ahb_ratio: 1x1
1125 * 0x306: 40Mhz, ahb_ratio: 1x1
1126 */
1127 REG_WRITE(ah, 0x50040, 0x304);
1128 /*
1129 * makes adjustments for the baud dividor to keep the
1130 * targetted baud rate based on the used core clock.
1131 */
1132 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1133 AR9271_TARGET_BAUD_RATE);
1134 }
1135 }
1136
1103 udelay(RTC_PLL_SETTLE_DELAY); 1137 udelay(RTC_PLL_SETTLE_DELAY);
1104 1138
1105 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 1139 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
@@ -1252,7 +1286,8 @@ void ath9k_hw_detach(struct ath_hw *ah)
1252 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1286 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1253 1287
1254free_hw: 1288free_hw:
1255 ath9k_hw_rf_free(ah); 1289 if (!AR_SREV_9280_10_OR_LATER(ah))
1290 ath9k_hw_rf_free_ext_banks(ah);
1256 kfree(ah); 1291 kfree(ah);
1257 ah = NULL; 1292 ah = NULL;
1258} 1293}
@@ -1274,7 +1309,8 @@ static void ath9k_hw_override_ini(struct ath_hw *ah,
1274 * AR9271 1.1 1309 * AR9271 1.1
1275 */ 1310 */
1276 if (AR_SREV_9271_10(ah)) { 1311 if (AR_SREV_9271_10(ah)) {
1277 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE; 1312 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1313 AR_PHY_SPECTRAL_SCAN_ENABLE;
1278 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val); 1314 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1279 } 1315 }
1280 else if (AR_SREV_9271_11(ah)) 1316 else if (AR_SREV_9271_11(ah))
@@ -1489,7 +1525,11 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1489 DO_DELAY(regWrites); 1525 DO_DELAY(regWrites);
1490 } 1526 }
1491 1527
1492 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); 1528 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1529
1530 if (AR_SREV_9271_10(ah))
1531 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1532 modesIndex, regWrites);
1493 1533
1494 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1534 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1495 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, 1535 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
@@ -1832,6 +1872,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1832 struct ath_common *common = ath9k_hw_common(ah); 1872 struct ath_common *common = ath9k_hw_common(ah);
1833 struct ieee80211_channel *channel = chan->chan; 1873 struct ieee80211_channel *channel = chan->chan;
1834 u32 synthDelay, qnum; 1874 u32 synthDelay, qnum;
1875 int r;
1835 1876
1836 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1877 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1837 if (ath9k_hw_numtxpending(ah, qnum)) { 1878 if (ath9k_hw_numtxpending(ah, qnum)) {
@@ -1852,14 +1893,11 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1852 1893
1853 ath9k_hw_set_regs(ah, chan); 1894 ath9k_hw_set_regs(ah, chan);
1854 1895
1855 if (AR_SREV_9280_10_OR_LATER(ah)) { 1896 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1856 ath9k_hw_ar9280_set_channel(ah, chan); 1897 if (r) {
1857 } else { 1898 ath_print(common, ATH_DBG_FATAL,
1858 if (!(ath9k_hw_set_channel(ah, chan))) { 1899 "Failed to set channel\n");
1859 ath_print(common, ATH_DBG_FATAL, 1900 return false;
1860 "Failed to set channel\n");
1861 return false;
1862 }
1863 } 1901 }
1864 1902
1865 ah->eep_ops->set_txpower(ah, chan, 1903 ah->eep_ops->set_txpower(ah, chan,
@@ -1882,10 +1920,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1882 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1920 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1883 ath9k_hw_set_delta_slope(ah, chan); 1921 ath9k_hw_set_delta_slope(ah, chan);
1884 1922
1885 if (AR_SREV_9280_10_OR_LATER(ah)) 1923 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1886 ath9k_hw_9280_spur_mitigate(ah, chan);
1887 else
1888 ath9k_hw_spur_mitigate(ah, chan);
1889 1924
1890 if (!chan->oneTimeCalsDone) 1925 if (!chan->oneTimeCalsDone)
1891 chan->oneTimeCalsDone = true; 1926 chan->oneTimeCalsDone = true;
@@ -1893,457 +1928,6 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1893 return true; 1928 return true;
1894} 1929}
1895 1930
1896static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1897{
1898 int bb_spur = AR_NO_SPUR;
1899 int freq;
1900 int bin, cur_bin;
1901 int bb_spur_off, spur_subchannel_sd;
1902 int spur_freq_sd;
1903 int spur_delta_phase;
1904 int denominator;
1905 int upper, lower, cur_vit_mask;
1906 int tmp, newVal;
1907 int i;
1908 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1909 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1910 };
1911 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1912 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1913 };
1914 int inc[4] = { 0, 100, 0, 0 };
1915 struct chan_centers centers;
1916
1917 int8_t mask_m[123];
1918 int8_t mask_p[123];
1919 int8_t mask_amt;
1920 int tmp_mask;
1921 int cur_bb_spur;
1922 bool is2GHz = IS_CHAN_2GHZ(chan);
1923
1924 memset(&mask_m, 0, sizeof(int8_t) * 123);
1925 memset(&mask_p, 0, sizeof(int8_t) * 123);
1926
1927 ath9k_hw_get_channel_centers(ah, chan, &centers);
1928 freq = centers.synth_center;
1929
1930 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1931 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1932 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1933
1934 if (is2GHz)
1935 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1936 else
1937 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1938
1939 if (AR_NO_SPUR == cur_bb_spur)
1940 break;
1941 cur_bb_spur = cur_bb_spur - freq;
1942
1943 if (IS_CHAN_HT40(chan)) {
1944 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1945 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1946 bb_spur = cur_bb_spur;
1947 break;
1948 }
1949 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1950 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1951 bb_spur = cur_bb_spur;
1952 break;
1953 }
1954 }
1955
1956 if (AR_NO_SPUR == bb_spur) {
1957 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1958 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1959 return;
1960 } else {
1961 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1962 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1963 }
1964
1965 bin = bb_spur * 320;
1966
1967 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1968
1969 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1970 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1971 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1972 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1973 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1974
1975 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1976 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1977 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1978 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1979 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1980 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1981
1982 if (IS_CHAN_HT40(chan)) {
1983 if (bb_spur < 0) {
1984 spur_subchannel_sd = 1;
1985 bb_spur_off = bb_spur + 10;
1986 } else {
1987 spur_subchannel_sd = 0;
1988 bb_spur_off = bb_spur - 10;
1989 }
1990 } else {
1991 spur_subchannel_sd = 0;
1992 bb_spur_off = bb_spur;
1993 }
1994
1995 if (IS_CHAN_HT40(chan))
1996 spur_delta_phase =
1997 ((bb_spur * 262144) /
1998 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1999 else
2000 spur_delta_phase =
2001 ((bb_spur * 524288) /
2002 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2003
2004 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
2005 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
2006
2007 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2008 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2009 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2010 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
2011
2012 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
2013 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
2014
2015 cur_bin = -6000;
2016 upper = bin + 100;
2017 lower = bin - 100;
2018
2019 for (i = 0; i < 4; i++) {
2020 int pilot_mask = 0;
2021 int chan_mask = 0;
2022 int bp = 0;
2023 for (bp = 0; bp < 30; bp++) {
2024 if ((cur_bin > lower) && (cur_bin < upper)) {
2025 pilot_mask = pilot_mask | 0x1 << bp;
2026 chan_mask = chan_mask | 0x1 << bp;
2027 }
2028 cur_bin += 100;
2029 }
2030 cur_bin += inc[i];
2031 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2032 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2033 }
2034
2035 cur_vit_mask = 6100;
2036 upper = bin + 120;
2037 lower = bin - 120;
2038
2039 for (i = 0; i < 123; i++) {
2040 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2041
2042 /* workaround for gcc bug #37014 */
2043 volatile int tmp_v = abs(cur_vit_mask - bin);
2044
2045 if (tmp_v < 75)
2046 mask_amt = 1;
2047 else
2048 mask_amt = 0;
2049 if (cur_vit_mask < 0)
2050 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2051 else
2052 mask_p[cur_vit_mask / 100] = mask_amt;
2053 }
2054 cur_vit_mask -= 100;
2055 }
2056
2057 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2058 | (mask_m[48] << 26) | (mask_m[49] << 24)
2059 | (mask_m[50] << 22) | (mask_m[51] << 20)
2060 | (mask_m[52] << 18) | (mask_m[53] << 16)
2061 | (mask_m[54] << 14) | (mask_m[55] << 12)
2062 | (mask_m[56] << 10) | (mask_m[57] << 8)
2063 | (mask_m[58] << 6) | (mask_m[59] << 4)
2064 | (mask_m[60] << 2) | (mask_m[61] << 0);
2065 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2066 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2067
2068 tmp_mask = (mask_m[31] << 28)
2069 | (mask_m[32] << 26) | (mask_m[33] << 24)
2070 | (mask_m[34] << 22) | (mask_m[35] << 20)
2071 | (mask_m[36] << 18) | (mask_m[37] << 16)
2072 | (mask_m[48] << 14) | (mask_m[39] << 12)
2073 | (mask_m[40] << 10) | (mask_m[41] << 8)
2074 | (mask_m[42] << 6) | (mask_m[43] << 4)
2075 | (mask_m[44] << 2) | (mask_m[45] << 0);
2076 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2077 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2078
2079 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2080 | (mask_m[18] << 26) | (mask_m[18] << 24)
2081 | (mask_m[20] << 22) | (mask_m[20] << 20)
2082 | (mask_m[22] << 18) | (mask_m[22] << 16)
2083 | (mask_m[24] << 14) | (mask_m[24] << 12)
2084 | (mask_m[25] << 10) | (mask_m[26] << 8)
2085 | (mask_m[27] << 6) | (mask_m[28] << 4)
2086 | (mask_m[29] << 2) | (mask_m[30] << 0);
2087 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2088 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2089
2090 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2091 | (mask_m[2] << 26) | (mask_m[3] << 24)
2092 | (mask_m[4] << 22) | (mask_m[5] << 20)
2093 | (mask_m[6] << 18) | (mask_m[7] << 16)
2094 | (mask_m[8] << 14) | (mask_m[9] << 12)
2095 | (mask_m[10] << 10) | (mask_m[11] << 8)
2096 | (mask_m[12] << 6) | (mask_m[13] << 4)
2097 | (mask_m[14] << 2) | (mask_m[15] << 0);
2098 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2099 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2100
2101 tmp_mask = (mask_p[15] << 28)
2102 | (mask_p[14] << 26) | (mask_p[13] << 24)
2103 | (mask_p[12] << 22) | (mask_p[11] << 20)
2104 | (mask_p[10] << 18) | (mask_p[9] << 16)
2105 | (mask_p[8] << 14) | (mask_p[7] << 12)
2106 | (mask_p[6] << 10) | (mask_p[5] << 8)
2107 | (mask_p[4] << 6) | (mask_p[3] << 4)
2108 | (mask_p[2] << 2) | (mask_p[1] << 0);
2109 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2110 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2111
2112 tmp_mask = (mask_p[30] << 28)
2113 | (mask_p[29] << 26) | (mask_p[28] << 24)
2114 | (mask_p[27] << 22) | (mask_p[26] << 20)
2115 | (mask_p[25] << 18) | (mask_p[24] << 16)
2116 | (mask_p[23] << 14) | (mask_p[22] << 12)
2117 | (mask_p[21] << 10) | (mask_p[20] << 8)
2118 | (mask_p[19] << 6) | (mask_p[18] << 4)
2119 | (mask_p[17] << 2) | (mask_p[16] << 0);
2120 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2121 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2122
2123 tmp_mask = (mask_p[45] << 28)
2124 | (mask_p[44] << 26) | (mask_p[43] << 24)
2125 | (mask_p[42] << 22) | (mask_p[41] << 20)
2126 | (mask_p[40] << 18) | (mask_p[39] << 16)
2127 | (mask_p[38] << 14) | (mask_p[37] << 12)
2128 | (mask_p[36] << 10) | (mask_p[35] << 8)
2129 | (mask_p[34] << 6) | (mask_p[33] << 4)
2130 | (mask_p[32] << 2) | (mask_p[31] << 0);
2131 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2132 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2133
2134 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2135 | (mask_p[59] << 26) | (mask_p[58] << 24)
2136 | (mask_p[57] << 22) | (mask_p[56] << 20)
2137 | (mask_p[55] << 18) | (mask_p[54] << 16)
2138 | (mask_p[53] << 14) | (mask_p[52] << 12)
2139 | (mask_p[51] << 10) | (mask_p[50] << 8)
2140 | (mask_p[49] << 6) | (mask_p[48] << 4)
2141 | (mask_p[47] << 2) | (mask_p[46] << 0);
2142 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2143 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2144}
2145
2146static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2147{
2148 int bb_spur = AR_NO_SPUR;
2149 int bin, cur_bin;
2150 int spur_freq_sd;
2151 int spur_delta_phase;
2152 int denominator;
2153 int upper, lower, cur_vit_mask;
2154 int tmp, new;
2155 int i;
2156 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2157 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2158 };
2159 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2160 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2161 };
2162 int inc[4] = { 0, 100, 0, 0 };
2163
2164 int8_t mask_m[123];
2165 int8_t mask_p[123];
2166 int8_t mask_amt;
2167 int tmp_mask;
2168 int cur_bb_spur;
2169 bool is2GHz = IS_CHAN_2GHZ(chan);
2170
2171 memset(&mask_m, 0, sizeof(int8_t) * 123);
2172 memset(&mask_p, 0, sizeof(int8_t) * 123);
2173
2174 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2175 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2176 if (AR_NO_SPUR == cur_bb_spur)
2177 break;
2178 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2179 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2180 bb_spur = cur_bb_spur;
2181 break;
2182 }
2183 }
2184
2185 if (AR_NO_SPUR == bb_spur)
2186 return;
2187
2188 bin = bb_spur * 32;
2189
2190 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2191 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2192 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2193 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2194 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2195
2196 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2197
2198 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2199 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2200 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2201 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2202 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2203 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2204
2205 spur_delta_phase = ((bb_spur * 524288) / 100) &
2206 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2207
2208 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2209 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2210
2211 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2212 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2213 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2214 REG_WRITE(ah, AR_PHY_TIMING11, new);
2215
2216 cur_bin = -6000;
2217 upper = bin + 100;
2218 lower = bin - 100;
2219
2220 for (i = 0; i < 4; i++) {
2221 int pilot_mask = 0;
2222 int chan_mask = 0;
2223 int bp = 0;
2224 for (bp = 0; bp < 30; bp++) {
2225 if ((cur_bin > lower) && (cur_bin < upper)) {
2226 pilot_mask = pilot_mask | 0x1 << bp;
2227 chan_mask = chan_mask | 0x1 << bp;
2228 }
2229 cur_bin += 100;
2230 }
2231 cur_bin += inc[i];
2232 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2233 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2234 }
2235
2236 cur_vit_mask = 6100;
2237 upper = bin + 120;
2238 lower = bin - 120;
2239
2240 for (i = 0; i < 123; i++) {
2241 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2242
2243 /* workaround for gcc bug #37014 */
2244 volatile int tmp_v = abs(cur_vit_mask - bin);
2245
2246 if (tmp_v < 75)
2247 mask_amt = 1;
2248 else
2249 mask_amt = 0;
2250 if (cur_vit_mask < 0)
2251 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2252 else
2253 mask_p[cur_vit_mask / 100] = mask_amt;
2254 }
2255 cur_vit_mask -= 100;
2256 }
2257
2258 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2259 | (mask_m[48] << 26) | (mask_m[49] << 24)
2260 | (mask_m[50] << 22) | (mask_m[51] << 20)
2261 | (mask_m[52] << 18) | (mask_m[53] << 16)
2262 | (mask_m[54] << 14) | (mask_m[55] << 12)
2263 | (mask_m[56] << 10) | (mask_m[57] << 8)
2264 | (mask_m[58] << 6) | (mask_m[59] << 4)
2265 | (mask_m[60] << 2) | (mask_m[61] << 0);
2266 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2267 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2268
2269 tmp_mask = (mask_m[31] << 28)
2270 | (mask_m[32] << 26) | (mask_m[33] << 24)
2271 | (mask_m[34] << 22) | (mask_m[35] << 20)
2272 | (mask_m[36] << 18) | (mask_m[37] << 16)
2273 | (mask_m[48] << 14) | (mask_m[39] << 12)
2274 | (mask_m[40] << 10) | (mask_m[41] << 8)
2275 | (mask_m[42] << 6) | (mask_m[43] << 4)
2276 | (mask_m[44] << 2) | (mask_m[45] << 0);
2277 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2278 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2279
2280 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2281 | (mask_m[18] << 26) | (mask_m[18] << 24)
2282 | (mask_m[20] << 22) | (mask_m[20] << 20)
2283 | (mask_m[22] << 18) | (mask_m[22] << 16)
2284 | (mask_m[24] << 14) | (mask_m[24] << 12)
2285 | (mask_m[25] << 10) | (mask_m[26] << 8)
2286 | (mask_m[27] << 6) | (mask_m[28] << 4)
2287 | (mask_m[29] << 2) | (mask_m[30] << 0);
2288 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2289 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2290
2291 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2292 | (mask_m[2] << 26) | (mask_m[3] << 24)
2293 | (mask_m[4] << 22) | (mask_m[5] << 20)
2294 | (mask_m[6] << 18) | (mask_m[7] << 16)
2295 | (mask_m[8] << 14) | (mask_m[9] << 12)
2296 | (mask_m[10] << 10) | (mask_m[11] << 8)
2297 | (mask_m[12] << 6) | (mask_m[13] << 4)
2298 | (mask_m[14] << 2) | (mask_m[15] << 0);
2299 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2300 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2301
2302 tmp_mask = (mask_p[15] << 28)
2303 | (mask_p[14] << 26) | (mask_p[13] << 24)
2304 | (mask_p[12] << 22) | (mask_p[11] << 20)
2305 | (mask_p[10] << 18) | (mask_p[9] << 16)
2306 | (mask_p[8] << 14) | (mask_p[7] << 12)
2307 | (mask_p[6] << 10) | (mask_p[5] << 8)
2308 | (mask_p[4] << 6) | (mask_p[3] << 4)
2309 | (mask_p[2] << 2) | (mask_p[1] << 0);
2310 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2311 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2312
2313 tmp_mask = (mask_p[30] << 28)
2314 | (mask_p[29] << 26) | (mask_p[28] << 24)
2315 | (mask_p[27] << 22) | (mask_p[26] << 20)
2316 | (mask_p[25] << 18) | (mask_p[24] << 16)
2317 | (mask_p[23] << 14) | (mask_p[22] << 12)
2318 | (mask_p[21] << 10) | (mask_p[20] << 8)
2319 | (mask_p[19] << 6) | (mask_p[18] << 4)
2320 | (mask_p[17] << 2) | (mask_p[16] << 0);
2321 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2322 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2323
2324 tmp_mask = (mask_p[45] << 28)
2325 | (mask_p[44] << 26) | (mask_p[43] << 24)
2326 | (mask_p[42] << 22) | (mask_p[41] << 20)
2327 | (mask_p[40] << 18) | (mask_p[39] << 16)
2328 | (mask_p[38] << 14) | (mask_p[37] << 12)
2329 | (mask_p[36] << 10) | (mask_p[35] << 8)
2330 | (mask_p[34] << 6) | (mask_p[33] << 4)
2331 | (mask_p[32] << 2) | (mask_p[31] << 0);
2332 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2333 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2334
2335 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2336 | (mask_p[59] << 26) | (mask_p[58] << 24)
2337 | (mask_p[57] << 22) | (mask_p[56] << 20)
2338 | (mask_p[55] << 18) | (mask_p[54] << 16)
2339 | (mask_p[53] << 14) | (mask_p[52] << 12)
2340 | (mask_p[51] << 10) | (mask_p[50] << 8)
2341 | (mask_p[49] << 6) | (mask_p[48] << 4)
2342 | (mask_p[47] << 2) | (mask_p[46] << 0);
2343 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2344 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2345}
2346
2347static void ath9k_enable_rfkill(struct ath_hw *ah) 1931static void ath9k_enable_rfkill(struct ath_hw *ah)
2348{ 1932{
2349 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 1933 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
@@ -2469,14 +2053,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2469 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 2053 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2470 ath9k_hw_set_delta_slope(ah, chan); 2054 ath9k_hw_set_delta_slope(ah, chan);
2471 2055
2472 if (AR_SREV_9280_10_OR_LATER(ah)) 2056 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2473 ath9k_hw_9280_spur_mitigate(ah, chan);
2474 else
2475 ath9k_hw_spur_mitigate(ah, chan);
2476
2477 ah->eep_ops->set_board_values(ah, chan); 2057 ah->eep_ops->set_board_values(ah, chan);
2478 2058
2479 ath9k_hw_decrease_chain_power(ah, chan); 2059 if (AR_SREV_5416(ah))
2060 ath9k_hw_decrease_chain_power(ah, chan);
2480 2061
2481 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 2062 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2482 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 2063 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
@@ -2497,11 +2078,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2497 2078
2498 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 2079 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2499 2080
2500 if (AR_SREV_9280_10_OR_LATER(ah)) 2081 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2501 ath9k_hw_ar9280_set_channel(ah, chan); 2082 if (r)
2502 else 2083 return r;
2503 if (!(ath9k_hw_set_channel(ah, chan)))
2504 return -EIO;
2505 2084
2506 for (i = 0; i < AR_NUM_DCU; i++) 2085 for (i = 0; i < AR_NUM_DCU; i++)
2507 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2086 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
@@ -4350,3 +3929,89 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4350 } 3929 }
4351} 3930}
4352EXPORT_SYMBOL(ath_gen_timer_isr); 3931EXPORT_SYMBOL(ath_gen_timer_isr);
3932
3933static struct {
3934 u32 version;
3935 const char * name;
3936} ath_mac_bb_names[] = {
3937 /* Devices with external radios */
3938 { AR_SREV_VERSION_5416_PCI, "5416" },
3939 { AR_SREV_VERSION_5416_PCIE, "5418" },
3940 { AR_SREV_VERSION_9100, "9100" },
3941 { AR_SREV_VERSION_9160, "9160" },
3942 /* Single-chip solutions */
3943 { AR_SREV_VERSION_9280, "9280" },
3944 { AR_SREV_VERSION_9285, "9285" },
3945 { AR_SREV_VERSION_9287, "9287" },
3946 { AR_SREV_VERSION_9271, "9271" },
3947};
3948
3949/* For devices with external radios */
3950static struct {
3951 u16 version;
3952 const char * name;
3953} ath_rf_names[] = {
3954 { 0, "5133" },
3955 { AR_RAD5133_SREV_MAJOR, "5133" },
3956 { AR_RAD5122_SREV_MAJOR, "5122" },
3957 { AR_RAD2133_SREV_MAJOR, "2133" },
3958 { AR_RAD2122_SREV_MAJOR, "2122" }
3959};
3960
3961/*
3962 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3963 */
3964static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3965{
3966 int i;
3967
3968 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3969 if (ath_mac_bb_names[i].version == mac_bb_version) {
3970 return ath_mac_bb_names[i].name;
3971 }
3972 }
3973
3974 return "????";
3975}
3976
3977/*
3978 * Return the RF name. "????" is returned if the RF is unknown.
3979 * Used for devices with external radios.
3980 */
3981static const char *ath9k_hw_rf_name(u16 rf_version)
3982{
3983 int i;
3984
3985 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3986 if (ath_rf_names[i].version == rf_version) {
3987 return ath_rf_names[i].name;
3988 }
3989 }
3990
3991 return "????";
3992}
3993
3994void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3995{
3996 int used;
3997
3998 /* chipsets >= AR9280 are single-chip */
3999 if (AR_SREV_9280_10_OR_LATER(ah)) {
4000 used = snprintf(hw_name, len,
4001 "Atheros AR%s Rev:%x",
4002 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
4003 ah->hw_version.macRev);
4004 }
4005 else {
4006 used = snprintf(hw_name, len,
4007 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
4008 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
4009 ah->hw_version.macRev,
4010 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
4011 AR_RADIO_SREV_MAJOR)),
4012 ah->hw_version.phyRev);
4013 }
4014
4015 hw_name[used] = '\0';
4016}
4017EXPORT_SYMBOL(ath9k_hw_name);
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index cdaec526db35..c7b0c4d5f75a 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -148,6 +148,15 @@ enum wireless_mode {
148 ATH9K_MODE_MAX, 148 ATH9K_MODE_MAX,
149}; 149};
150 150
151/**
152 * ath9k_ant_setting - transmit antenna settings
153 *
154 * Configures the antenna setting to use for transmit.
155 *
156 * @ATH9K_ANT_VARIABLE: this means transmit on all active antennas
157 * @ATH9K_ANT_FIXED_A: this means transmit on the first antenna only
158 * @ATH9K_ANT_FIXED_B: this means transmit on the second antenna only
159 */
151enum ath9k_ant_setting { 160enum ath9k_ant_setting {
152 ATH9K_ANT_VARIABLE = 0, 161 ATH9K_ANT_VARIABLE = 0,
153 ATH9K_ANT_FIXED_A, 162 ATH9K_ANT_FIXED_A,
@@ -539,7 +548,14 @@ struct ath_hw {
539 DONT_USE_32KHZ, 548 DONT_USE_32KHZ,
540 } enable_32kHz_clock; 549 } enable_32kHz_clock;
541 550
542 /* RF */ 551 /* Callback for radio frequency change */
552 int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
553
554 /* Callback for baseband spur frequency */
555 void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
556 struct ath9k_channel *chan);
557
558 /* Used to program the radio on non single-chip devices */
543 u32 *analogBank0Data; 559 u32 *analogBank0Data;
544 u32 *analogBank1Data; 560 u32 *analogBank1Data;
545 u32 *analogBank2Data; 561 u32 *analogBank2Data;
@@ -596,6 +612,7 @@ struct ath_hw {
596 struct ar5416IniArray iniModesAdditional; 612 struct ar5416IniArray iniModesAdditional;
597 struct ar5416IniArray iniModesRxGain; 613 struct ar5416IniArray iniModesRxGain;
598 struct ar5416IniArray iniModesTxGain; 614 struct ar5416IniArray iniModesTxGain;
615 struct ar5416IniArray iniModes_9271_1_0_only;
599 struct ar5416IniArray iniCckfirNormal; 616 struct ar5416IniArray iniCckfirNormal;
600 struct ar5416IniArray iniCckfirJapan2484; 617 struct ar5416IniArray iniCckfirJapan2484;
601 618
@@ -618,7 +635,6 @@ static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
618const char *ath9k_hw_probe(u16 vendorid, u16 devid); 635const char *ath9k_hw_probe(u16 vendorid, u16 devid);
619void ath9k_hw_detach(struct ath_hw *ah); 636void ath9k_hw_detach(struct ath_hw *ah);
620int ath9k_hw_init(struct ath_hw *ah); 637int ath9k_hw_init(struct ath_hw *ah);
621void ath9k_hw_rf_free(struct ath_hw *ah);
622int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 638int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
623 bool bChannelChange); 639 bool bChannelChange);
624void ath9k_hw_fill_cap_info(struct ath_hw *ah); 640void ath9k_hw_fill_cap_info(struct ath_hw *ah);
@@ -704,6 +720,8 @@ void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
704void ath_gen_timer_isr(struct ath_hw *hw); 720void ath_gen_timer_isr(struct ath_hw *hw);
705u32 ath9k_hw_gettsf32(struct ath_hw *ah); 721u32 ath9k_hw_gettsf32(struct ath_hw *ah);
706 722
723void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
724
707#define ATH_PCIE_CAP_LINK_CTRL 0x70 725#define ATH_PCIE_CAP_LINK_CTRL 0x70
708#define ATH_PCIE_CAP_LINK_L0S 1 726#define ATH_PCIE_CAP_LINK_L0S 1
709#define ATH_PCIE_CAP_LINK_L1 2 727#define ATH_PCIE_CAP_LINK_L1 2
diff --git a/drivers/net/wireless/ath/ath9k/initvals.h b/drivers/net/wireless/ath/ath9k/initvals.h
index 3ee6658d809b..8a3bf3ab998d 100644
--- a/drivers/net/wireless/ath/ath9k/initvals.h
+++ b/drivers/net/wireless/ath/ath9k/initvals.h
@@ -6379,8 +6379,8 @@ static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
6379}; 6379};
6380 6380
6381 6381
6382/* AR9271 initialization values automaticaly created: 03/23/09 */ 6382/* AR9271 initialization values automaticaly created: 06/04/09 */
6383static const u_int32_t ar9271Modes_9271_1_0[][6] = { 6383static const u_int32_t ar9271Modes_9271[][6] = {
6384 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, 6384 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
6385 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, 6385 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
6386 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, 6386 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
@@ -6390,8 +6390,8 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6390 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 }, 6390 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
6391 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, 6391 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
6392 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, 6392 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
6393 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 6393 { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
6394 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, 6394 { 0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001 },
6395 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 6395 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
6396 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, 6396 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
6397 { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e }, 6397 { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
@@ -6405,6 +6405,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6405 { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, 6405 { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
6406 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 }, 6406 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
6407 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 }, 6407 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
6408 { 0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310, 0x30002310 },
6408 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 }, 6409 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
6409 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 }, 6410 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
6410 { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d }, 6411 { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
@@ -6415,7 +6416,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6415 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 }, 6416 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
6416 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 }, 6417 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
6417 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, 6418 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
6418 { 0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329 }, 6419 { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
6419 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, 6420 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
6420 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, 6421 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
6421 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 6422 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
@@ -6704,7 +6705,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6704 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, 6705 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
6705}; 6706};
6706 6707
6707static const u_int32_t ar9271Common_9271_1_0[][2] = { 6708static const u_int32_t ar9271Common_9271[][2] = {
6708 { 0x0000000c, 0x00000000 }, 6709 { 0x0000000c, 0x00000000 },
6709 { 0x00000030, 0x00020045 }, 6710 { 0x00000030, 0x00020045 },
6710 { 0x00000034, 0x00000005 }, 6711 { 0x00000034, 0x00000005 },
@@ -6800,7 +6801,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6800 { 0x0000803c, 0x00000000 }, 6801 { 0x0000803c, 0x00000000 },
6801 { 0x00008048, 0x00000000 }, 6802 { 0x00008048, 0x00000000 },
6802 { 0x00008054, 0x00000000 }, 6803 { 0x00008054, 0x00000000 },
6803 { 0x00008058, 0x02000000 }, 6804 { 0x00008058, 0x00000000 },
6804 { 0x0000805c, 0x000fc78f }, 6805 { 0x0000805c, 0x000fc78f },
6805 { 0x00008060, 0x0000000f }, 6806 { 0x00008060, 0x0000000f },
6806 { 0x00008064, 0x00000000 }, 6807 { 0x00008064, 0x00000000 },
@@ -6831,7 +6832,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6831 { 0x00008110, 0x00000168 }, 6832 { 0x00008110, 0x00000168 },
6832 { 0x00008118, 0x000100aa }, 6833 { 0x00008118, 0x000100aa },
6833 { 0x0000811c, 0x00003210 }, 6834 { 0x0000811c, 0x00003210 },
6834 { 0x00008120, 0x08f04814 }, 6835 { 0x00008120, 0x08f04810 },
6835 { 0x00008124, 0x00000000 }, 6836 { 0x00008124, 0x00000000 },
6836 { 0x00008128, 0x00000000 }, 6837 { 0x00008128, 0x00000000 },
6837 { 0x0000812c, 0x00000000 }, 6838 { 0x0000812c, 0x00000000 },
@@ -6878,7 +6879,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6878 { 0x00008258, 0x00000000 }, 6879 { 0x00008258, 0x00000000 },
6879 { 0x0000825c, 0x400000ff }, 6880 { 0x0000825c, 0x400000ff },
6880 { 0x00008260, 0x00080922 }, 6881 { 0x00008260, 0x00080922 },
6881 { 0x00008264, 0xa8a00010 }, 6882 { 0x00008264, 0x88a00010 },
6882 { 0x00008270, 0x00000000 }, 6883 { 0x00008270, 0x00000000 },
6883 { 0x00008274, 0x40000000 }, 6884 { 0x00008274, 0x40000000 },
6884 { 0x00008278, 0x003e4180 }, 6885 { 0x00008278, 0x003e4180 },
@@ -6910,7 +6911,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6910 { 0x00007814, 0x924934a8 }, 6911 { 0x00007814, 0x924934a8 },
6911 { 0x0000781c, 0x00000000 }, 6912 { 0x0000781c, 0x00000000 },
6912 { 0x00007820, 0x00000c04 }, 6913 { 0x00007820, 0x00000c04 },
6913 { 0x00007824, 0x00d86bff }, 6914 { 0x00007824, 0x00d8abff },
6914 { 0x00007828, 0x66964300 }, 6915 { 0x00007828, 0x66964300 },
6915 { 0x0000782c, 0x8db6d961 }, 6916 { 0x0000782c, 0x8db6d961 },
6916 { 0x00007830, 0x8db6d96c }, 6917 { 0x00007830, 0x8db6d96c },
@@ -6944,7 +6945,6 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6944 { 0x00009904, 0x00000000 }, 6945 { 0x00009904, 0x00000000 },
6945 { 0x00009908, 0x00000000 }, 6946 { 0x00009908, 0x00000000 },
6946 { 0x0000990c, 0x00000000 }, 6947 { 0x0000990c, 0x00000000 },
6947 { 0x00009910, 0x30002310 },
6948 { 0x0000991c, 0x10000fff }, 6948 { 0x0000991c, 0x10000fff },
6949 { 0x00009920, 0x04900000 }, 6949 { 0x00009920, 0x04900000 },
6950 { 0x00009928, 0x00000001 }, 6950 { 0x00009928, 0x00000001 },
@@ -6958,7 +6958,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6958 { 0x00009954, 0x5f3ca3de }, 6958 { 0x00009954, 0x5f3ca3de },
6959 { 0x00009958, 0x0108ecff }, 6959 { 0x00009958, 0x0108ecff },
6960 { 0x00009968, 0x000003ce }, 6960 { 0x00009968, 0x000003ce },
6961 { 0x00009970, 0x192bb515 }, 6961 { 0x00009970, 0x192bb514 },
6962 { 0x00009974, 0x00000000 }, 6962 { 0x00009974, 0x00000000 },
6963 { 0x00009978, 0x00000001 }, 6963 { 0x00009978, 0x00000001 },
6964 { 0x0000997c, 0x00000000 }, 6964 { 0x0000997c, 0x00000000 },
@@ -7045,3 +7045,8 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
7045 { 0x0000d380, 0x7f3c7bba }, 7045 { 0x0000d380, 0x7f3c7bba },
7046 { 0x0000d384, 0xf3307ff0 }, 7046 { 0x0000d384, 0xf3307ff0 },
7047}; 7047};
7048
7049static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
7050 { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 },
7051 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
7052};
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 69cf702b18c2..9fefc51aec17 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -3191,64 +3191,6 @@ struct ieee80211_ops ath9k_ops = {
3191 .rfkill_poll = ath9k_rfkill_poll_state, 3191 .rfkill_poll = ath9k_rfkill_poll_state,
3192}; 3192};
3193 3193
3194static struct {
3195 u32 version;
3196 const char * name;
3197} ath_mac_bb_names[] = {
3198 { AR_SREV_VERSION_5416_PCI, "5416" },
3199 { AR_SREV_VERSION_5416_PCIE, "5418" },
3200 { AR_SREV_VERSION_9100, "9100" },
3201 { AR_SREV_VERSION_9160, "9160" },
3202 { AR_SREV_VERSION_9280, "9280" },
3203 { AR_SREV_VERSION_9285, "9285" },
3204 { AR_SREV_VERSION_9287, "9287" }
3205};
3206
3207static struct {
3208 u16 version;
3209 const char * name;
3210} ath_rf_names[] = {
3211 { 0, "5133" },
3212 { AR_RAD5133_SREV_MAJOR, "5133" },
3213 { AR_RAD5122_SREV_MAJOR, "5122" },
3214 { AR_RAD2133_SREV_MAJOR, "2133" },
3215 { AR_RAD2122_SREV_MAJOR, "2122" }
3216};
3217
3218/*
3219 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3220 */
3221const char *
3222ath_mac_bb_name(u32 mac_bb_version)
3223{
3224 int i;
3225
3226 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3227 if (ath_mac_bb_names[i].version == mac_bb_version) {
3228 return ath_mac_bb_names[i].name;
3229 }
3230 }
3231
3232 return "????";
3233}
3234
3235/*
3236 * Return the RF name. "????" is returned if the RF is unknown.
3237 */
3238const char *
3239ath_rf_name(u16 rf_version)
3240{
3241 int i;
3242
3243 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3244 if (ath_rf_names[i].version == rf_version) {
3245 return ath_rf_names[i].name;
3246 }
3247 }
3248
3249 return "????";
3250}
3251
3252static int __init ath9k_init(void) 3194static int __init ath9k_init(void)
3253{ 3195{
3254 int error; 3196 int error;
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index 63059b6a90da..5321f735e5a0 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -114,6 +114,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
114 u32 val; 114 u32 val;
115 int ret = 0; 115 int ret = 0;
116 struct ath_hw *ah; 116 struct ath_hw *ah;
117 char hw_name[64];
117 118
118 if (pci_enable_device(pdev)) 119 if (pci_enable_device(pdev))
119 return -EIO; 120 return -EIO;
@@ -218,14 +219,11 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
218 sc->irq = pdev->irq; 219 sc->irq = pdev->irq;
219 220
220 ah = sc->sc_ah; 221 ah = sc->sc_ah;
222 ath9k_hw_name(ah, hw_name, sizeof(hw_name));
221 printk(KERN_INFO 223 printk(KERN_INFO
222 "%s: Atheros AR%s MAC/BB Rev:%x " 224 "%s: %s mem=0x%lx, irq=%d\n",
223 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
224 wiphy_name(hw->wiphy), 225 wiphy_name(hw->wiphy),
225 ath_mac_bb_name(ah->hw_version.macVersion), 226 hw_name,
226 ah->hw_version.macRev,
227 ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
228 ah->hw_version.phyRev,
229 (unsigned long)mem, pdev->irq); 227 (unsigned long)mem, pdev->irq);
230 228
231 return 0; 229 return 0;
diff --git a/drivers/net/wireless/ath/ath9k/phy.c b/drivers/net/wireless/ath/ath9k/phy.c
index 72a17c43a5a0..13ab4d7eb7aa 100644
--- a/drivers/net/wireless/ath/ath9k/phy.c
+++ b/drivers/net/wireless/ath/ath9k/phy.c
@@ -14,91 +14,70 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17/**
18 * DOC: Programming Atheros 802.11n analog front end radios
19 *
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
24 *
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
28 *
29 * The following single-chips exist with a respective embedded radio:
30 *
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
35 *
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
38 *
39 * AR9287 - 11n single-band 1x1 MIMO for USB
40 */
41
17#include "hw.h" 42#include "hw.h"
18 43
19void 44/**
20ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, 45 * ath9k_hw_write_regs - ??
21 int regWrites) 46 *
47 * @ah: atheros hardware structure
48 * @freqIndex:
49 * @regWrites:
50 *
51 * Used for both the chipsets with an external AR2133/AR5133 radios and
52 * single-chip devices.
53 */
54void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites)
22{ 55{
23 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 56 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
24} 57}
25 58
26bool 59/**
27ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 60 * ath9k_hw_ar9280_set_channel - set channel on single-chip device
28{ 61 * @ah: atheros hardware structure
29 struct ath_common *common = ath9k_hw_common(ah); 62 * @chan:
30 u32 channelSel = 0; 63 *
31 u32 bModeSynth = 0; 64 * This is the function to change channel on single-chip devices, that is
32 u32 aModeRefSel = 0; 65 * all devices after ar9280.
33 u32 reg32 = 0; 66 *
34 u16 freq; 67 * This function takes the channel value in MHz and sets
35 struct chan_centers centers; 68 * hardware channel value. Assumes writes have been enabled to analog bus.
36 69 *
37 ath9k_hw_get_channel_centers(ah, chan, &centers); 70 * Actual Expression,
38 freq = centers.synth_center; 71 *
39 72 * For 2GHz channel,
40 if (freq < 4800) { 73 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
41 u32 txctl; 74 * (freq_ref = 40MHz)
42 75 *
43 if (((freq - 2192) % 5) == 0) { 76 * For 5GHz channel,
44 channelSel = ((freq - 672) * 2 - 3040) / 10; 77 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
45 bModeSynth = 0; 78 * (freq_ref = 40MHz/(24>>amodeRefSel))
46 } else if (((freq - 2224) % 5) == 0) { 79 */
47 channelSel = ((freq - 704) * 2 - 3040) / 10; 80int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
48 bModeSynth = 1;
49 } else {
50 ath_print(common, ATH_DBG_FATAL,
51 "Invalid channel %u MHz\n", freq);
52 return false;
53 }
54
55 channelSel = (channelSel << 2) & 0xff;
56 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
57
58 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
59 if (freq == 2484) {
60
61 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
62 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
63 } else {
64 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
65 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
66 }
67
68 } else if ((freq % 20) == 0 && freq >= 5120) {
69 channelSel =
70 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
71 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
72 } else if ((freq % 10) == 0) {
73 channelSel =
74 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
75 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
76 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
77 else
78 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
79 } else if ((freq % 5) == 0) {
80 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
81 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
82 } else {
83 ath_print(common, ATH_DBG_FATAL,
84 "Invalid channel %u MHz\n", freq);
85 return false;
86 }
87
88 reg32 =
89 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
90 (1 << 5) | 0x1;
91
92 REG_WRITE(ah, AR_PHY(0x37), reg32);
93
94 ah->curchan = chan;
95 ah->curchan_rad_index = -1;
96
97 return true;
98}
99
100void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
101 struct ath9k_channel *chan)
102{ 81{
103 u16 bMode, fracMode, aModeRefSel = 0; 82 u16 bMode, fracMode, aModeRefSel = 0;
104 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; 83 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
@@ -111,7 +90,7 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
111 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); 90 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
112 reg32 &= 0xc0000000; 91 reg32 &= 0xc0000000;
113 92
114 if (freq < 4800) { 93 if (freq < 4800) { /* 2 GHz, fractional mode */
115 u32 txctl; 94 u32 txctl;
116 int regWrites = 0; 95 int regWrites = 0;
117 96
@@ -122,6 +101,7 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
122 101
123 if (AR_SREV_9287_11_OR_LATER(ah)) { 102 if (AR_SREV_9287_11_OR_LATER(ah)) {
124 if (freq == 2484) { 103 if (freq == 2484) {
104 /* Enable channel spreading for channel 14 */
125 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484, 105 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
126 1, regWrites); 106 1, regWrites);
127 } else { 107 } else {
@@ -155,10 +135,15 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
155 case 1: 135 case 1:
156 default: 136 default:
157 aModeRefSel = 0; 137 aModeRefSel = 0;
138 /*
139 * Enable 2G (fractional) mode for channels
140 * which are 5MHz spaced.
141 */
158 fracMode = 1; 142 fracMode = 1;
159 refDivA = 1; 143 refDivA = 1;
160 channelSel = (freq * 0x8000) / 15; 144 channelSel = (freq * 0x8000) / 15;
161 145
146 /* RefDivA setting */
162 REG_RMW_FIELD(ah, AR_AN_SYNTH9, 147 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
163 AR_AN_SYNTH9_REFDIVA, refDivA); 148 AR_AN_SYNTH9_REFDIVA, refDivA);
164 149
@@ -180,12 +165,284 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
180 165
181 ah->curchan = chan; 166 ah->curchan = chan;
182 ah->curchan_rad_index = -1; 167 ah->curchan_rad_index = -1;
168
169 return 0;
170}
171
172/**
173 * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
174 * @ah: atheros hardware structure
175 * @chan:
176 *
177 * For single-chip solutions. Converts to baseband spur frequency given the
178 * input channel frequency and compute register settings below.
179 */
180void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
181{
182 int bb_spur = AR_NO_SPUR;
183 int freq;
184 int bin, cur_bin;
185 int bb_spur_off, spur_subchannel_sd;
186 int spur_freq_sd;
187 int spur_delta_phase;
188 int denominator;
189 int upper, lower, cur_vit_mask;
190 int tmp, newVal;
191 int i;
192 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
193 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
194 };
195 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
196 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
197 };
198 int inc[4] = { 0, 100, 0, 0 };
199 struct chan_centers centers;
200
201 int8_t mask_m[123];
202 int8_t mask_p[123];
203 int8_t mask_amt;
204 int tmp_mask;
205 int cur_bb_spur;
206 bool is2GHz = IS_CHAN_2GHZ(chan);
207
208 memset(&mask_m, 0, sizeof(int8_t) * 123);
209 memset(&mask_p, 0, sizeof(int8_t) * 123);
210
211 ath9k_hw_get_channel_centers(ah, chan, &centers);
212 freq = centers.synth_center;
213
214 ah->config.spurmode = SPUR_ENABLE_EEPROM;
215 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
216 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
217
218 if (is2GHz)
219 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
220 else
221 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
222
223 if (AR_NO_SPUR == cur_bb_spur)
224 break;
225 cur_bb_spur = cur_bb_spur - freq;
226
227 if (IS_CHAN_HT40(chan)) {
228 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
229 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
230 bb_spur = cur_bb_spur;
231 break;
232 }
233 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
234 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
235 bb_spur = cur_bb_spur;
236 break;
237 }
238 }
239
240 if (AR_NO_SPUR == bb_spur) {
241 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
242 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
243 return;
244 } else {
245 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
246 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
247 }
248
249 bin = bb_spur * 320;
250
251 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
252
253 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
254 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
255 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
256 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
257 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
258
259 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
260 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
261 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
262 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
263 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
264 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
265
266 if (IS_CHAN_HT40(chan)) {
267 if (bb_spur < 0) {
268 spur_subchannel_sd = 1;
269 bb_spur_off = bb_spur + 10;
270 } else {
271 spur_subchannel_sd = 0;
272 bb_spur_off = bb_spur - 10;
273 }
274 } else {
275 spur_subchannel_sd = 0;
276 bb_spur_off = bb_spur;
277 }
278
279 if (IS_CHAN_HT40(chan))
280 spur_delta_phase =
281 ((bb_spur * 262144) /
282 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
283 else
284 spur_delta_phase =
285 ((bb_spur * 524288) /
286 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
287
288 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
289 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
290
291 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
292 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
293 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
294 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
295
296 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
297 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
298
299 cur_bin = -6000;
300 upper = bin + 100;
301 lower = bin - 100;
302
303 for (i = 0; i < 4; i++) {
304 int pilot_mask = 0;
305 int chan_mask = 0;
306 int bp = 0;
307 for (bp = 0; bp < 30; bp++) {
308 if ((cur_bin > lower) && (cur_bin < upper)) {
309 pilot_mask = pilot_mask | 0x1 << bp;
310 chan_mask = chan_mask | 0x1 << bp;
311 }
312 cur_bin += 100;
313 }
314 cur_bin += inc[i];
315 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
316 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
317 }
318
319 cur_vit_mask = 6100;
320 upper = bin + 120;
321 lower = bin - 120;
322
323 for (i = 0; i < 123; i++) {
324 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
325
326 /* workaround for gcc bug #37014 */
327 volatile int tmp_v = abs(cur_vit_mask - bin);
328
329 if (tmp_v < 75)
330 mask_amt = 1;
331 else
332 mask_amt = 0;
333 if (cur_vit_mask < 0)
334 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
335 else
336 mask_p[cur_vit_mask / 100] = mask_amt;
337 }
338 cur_vit_mask -= 100;
339 }
340
341 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
342 | (mask_m[48] << 26) | (mask_m[49] << 24)
343 | (mask_m[50] << 22) | (mask_m[51] << 20)
344 | (mask_m[52] << 18) | (mask_m[53] << 16)
345 | (mask_m[54] << 14) | (mask_m[55] << 12)
346 | (mask_m[56] << 10) | (mask_m[57] << 8)
347 | (mask_m[58] << 6) | (mask_m[59] << 4)
348 | (mask_m[60] << 2) | (mask_m[61] << 0);
349 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
350 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
351
352 tmp_mask = (mask_m[31] << 28)
353 | (mask_m[32] << 26) | (mask_m[33] << 24)
354 | (mask_m[34] << 22) | (mask_m[35] << 20)
355 | (mask_m[36] << 18) | (mask_m[37] << 16)
356 | (mask_m[48] << 14) | (mask_m[39] << 12)
357 | (mask_m[40] << 10) | (mask_m[41] << 8)
358 | (mask_m[42] << 6) | (mask_m[43] << 4)
359 | (mask_m[44] << 2) | (mask_m[45] << 0);
360 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
361 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
362
363 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
364 | (mask_m[18] << 26) | (mask_m[18] << 24)
365 | (mask_m[20] << 22) | (mask_m[20] << 20)
366 | (mask_m[22] << 18) | (mask_m[22] << 16)
367 | (mask_m[24] << 14) | (mask_m[24] << 12)
368 | (mask_m[25] << 10) | (mask_m[26] << 8)
369 | (mask_m[27] << 6) | (mask_m[28] << 4)
370 | (mask_m[29] << 2) | (mask_m[30] << 0);
371 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
372 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
373
374 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
375 | (mask_m[2] << 26) | (mask_m[3] << 24)
376 | (mask_m[4] << 22) | (mask_m[5] << 20)
377 | (mask_m[6] << 18) | (mask_m[7] << 16)
378 | (mask_m[8] << 14) | (mask_m[9] << 12)
379 | (mask_m[10] << 10) | (mask_m[11] << 8)
380 | (mask_m[12] << 6) | (mask_m[13] << 4)
381 | (mask_m[14] << 2) | (mask_m[15] << 0);
382 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
383 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
384
385 tmp_mask = (mask_p[15] << 28)
386 | (mask_p[14] << 26) | (mask_p[13] << 24)
387 | (mask_p[12] << 22) | (mask_p[11] << 20)
388 | (mask_p[10] << 18) | (mask_p[9] << 16)
389 | (mask_p[8] << 14) | (mask_p[7] << 12)
390 | (mask_p[6] << 10) | (mask_p[5] << 8)
391 | (mask_p[4] << 6) | (mask_p[3] << 4)
392 | (mask_p[2] << 2) | (mask_p[1] << 0);
393 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
394 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
395
396 tmp_mask = (mask_p[30] << 28)
397 | (mask_p[29] << 26) | (mask_p[28] << 24)
398 | (mask_p[27] << 22) | (mask_p[26] << 20)
399 | (mask_p[25] << 18) | (mask_p[24] << 16)
400 | (mask_p[23] << 14) | (mask_p[22] << 12)
401 | (mask_p[21] << 10) | (mask_p[20] << 8)
402 | (mask_p[19] << 6) | (mask_p[18] << 4)
403 | (mask_p[17] << 2) | (mask_p[16] << 0);
404 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
405 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
406
407 tmp_mask = (mask_p[45] << 28)
408 | (mask_p[44] << 26) | (mask_p[43] << 24)
409 | (mask_p[42] << 22) | (mask_p[41] << 20)
410 | (mask_p[40] << 18) | (mask_p[39] << 16)
411 | (mask_p[38] << 14) | (mask_p[37] << 12)
412 | (mask_p[36] << 10) | (mask_p[35] << 8)
413 | (mask_p[34] << 6) | (mask_p[33] << 4)
414 | (mask_p[32] << 2) | (mask_p[31] << 0);
415 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
416 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
417
418 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
419 | (mask_p[59] << 26) | (mask_p[58] << 24)
420 | (mask_p[57] << 22) | (mask_p[56] << 20)
421 | (mask_p[55] << 18) | (mask_p[54] << 16)
422 | (mask_p[53] << 14) | (mask_p[52] << 12)
423 | (mask_p[51] << 10) | (mask_p[50] << 8)
424 | (mask_p[49] << 6) | (mask_p[48] << 4)
425 | (mask_p[47] << 2) | (mask_p[46] << 0);
426 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
427 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
183} 428}
184 429
185static void 430/* All code below is for non single-chip solutions */
186ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 431
187 u32 numBits, u32 firstBit, 432/**
188 u32 column) 433 * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
434 * @rfbuf:
435 * @reg32:
436 * @numBits:
437 * @firstBit:
438 * @column:
439 *
440 * Performs analog "swizzling" of parameters into their location.
441 * Used on external AR2133/AR5133 radios.
442 */
443static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
444 u32 numBits, u32 firstBit,
445 u32 column)
189{ 446{
190 u32 tmp32, mask, arrayEntry, lastBit; 447 u32 tmp32, mask, arrayEntry, lastBit;
191 int32_t bitPosition, bitsLeft; 448 int32_t bitPosition, bitsLeft;
@@ -209,26 +466,556 @@ ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
209 } 466 }
210} 467}
211 468
212bool 469/*
213ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, 470 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
214 u16 modesIndex) 471 * rf_pwd_icsyndiv.
472 *
473 * Theoretical Rules:
474 * if 2 GHz band
475 * if forceBiasAuto
476 * if synth_freq < 2412
477 * bias = 0
478 * else if 2412 <= synth_freq <= 2422
479 * bias = 1
480 * else // synth_freq > 2422
481 * bias = 2
482 * else if forceBias > 0
483 * bias = forceBias & 7
484 * else
485 * no change, use value from ini file
486 * else
487 * no change, invalid band
488 *
489 * 1st Mod:
490 * 2422 also uses value of 2
491 * <approved>
492 *
493 * 2nd Mod:
494 * Less than 2412 uses value of 0, 2412 and above uses value of 2
495 */
496static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
497{
498 struct ath_common *common = ath9k_hw_common(ah);
499 u32 tmp_reg;
500 int reg_writes = 0;
501 u32 new_bias = 0;
502
503 if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
504 return;
505 }
506
507 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
508
509 if (synth_freq < 2412)
510 new_bias = 0;
511 else if (synth_freq < 2422)
512 new_bias = 1;
513 else
514 new_bias = 2;
515
516 /* pre-reverse this field */
517 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
518
519 ath_print(common, ATH_DBG_CONFIG,
520 "Force rf_pwd_icsyndiv to %1d on %4d\n",
521 new_bias, synth_freq);
522
523 /* swizzle rf_pwd_icsyndiv */
524 ath9k_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
525
526 /* write Bank 6 with new params */
527 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
528}
529
530/**
531 * ath9k_hw_decrease_chain_power()
532 *
533 * @ah: atheros hardware structure
534 * @chan:
535 *
536 * Only used on the AR5416 and AR5418 with the external AR2133/AR5133 radios.
537 *
538 * Sets a chain internal RF path to the lowest output power. Any
539 * further writes to bank6 after this setting will override these
540 * changes. Thus this function must be the last function in the
541 * sequence to modify bank 6.
542 *
543 * This function must be called after ar5416SetRfRegs() which is
544 * called from ath9k_hw_process_ini() due to swizzling of bank 6.
545 * Depends on ah->analogBank6Data being initialized by
546 * ath9k_hw_set_rf_regs()
547 *
548 * Additional additive reduction in power -
549 * change chain's switch table so chain's tx state is actually the rx
550 * state value. May produce different results in 2GHz/5GHz as well as
551 * board to board but in general should be a reduction.
552 *
553 * Activated by #ifdef ALTER_SWITCH. Not tried yet. If so, must be
554 * called after ah->eep_ops->set_board_values() due to RMW of
555 * PHY_SWITCH_CHAIN_0.
556 */
557void ath9k_hw_decrease_chain_power(struct ath_hw *ah,
558 struct ath9k_channel *chan)
559{
560 int i, regWrites = 0;
561 u32 bank6SelMask;
562 u32 *bank6Temp = ah->bank6Temp;
563
564 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
565
566 switch (ah->config.diversity_control) {
567 case ATH9K_ANT_FIXED_A:
568 bank6SelMask =
569 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
570 REDUCE_CHAIN_0 : /* swapped, reduce chain 0 */
571 REDUCE_CHAIN_1; /* normal, select chain 1/2 to reduce */
572 break;
573 case ATH9K_ANT_FIXED_B:
574 bank6SelMask =
575 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
576 REDUCE_CHAIN_1 : /* swapped, reduce chain 1/2 */
577 REDUCE_CHAIN_0; /* normal, select chain 0 to reduce */
578 break;
579 case ATH9K_ANT_VARIABLE:
580 return; /* do not change anything */
581 break;
582 default:
583 return; /* do not change anything */
584 break;
585 }
586
587 for (i = 0; i < ah->iniBank6.ia_rows; i++)
588 bank6Temp[i] = ah->analogBank6Data[i];
589
590 /* Write Bank 5 to switch Bank 6 write to selected chain only */
591 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
592
593 /*
594 * Modify Bank6 selected chain to use lowest amplification.
595 * Modifies the parameters to a value of 1.
596 * Depends on existing bank 6 values to be cached in
597 * ah->analogBank6Data
598 */
599 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
600 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
601 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
602 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
603 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
604 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
605 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
606 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
607 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
608
609 REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
610
611 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
612#ifdef ALTER_SWITCH
613 REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
614 (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
615 | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
616#endif
617}
618
619/**
620 * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
621 * @ah: atheros hardware stucture
622 * @chan:
623 *
624 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
625 * the channel value. Assumes writes enabled to analog bus and bank6 register
626 * cache in ah->analogBank6Data.
627 */
628int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
629{
630 struct ath_common *common = ath9k_hw_common(ah);
631 u32 channelSel = 0;
632 u32 bModeSynth = 0;
633 u32 aModeRefSel = 0;
634 u32 reg32 = 0;
635 u16 freq;
636 struct chan_centers centers;
637
638 ath9k_hw_get_channel_centers(ah, chan, &centers);
639 freq = centers.synth_center;
640
641 if (freq < 4800) {
642 u32 txctl;
643
644 if (((freq - 2192) % 5) == 0) {
645 channelSel = ((freq - 672) * 2 - 3040) / 10;
646 bModeSynth = 0;
647 } else if (((freq - 2224) % 5) == 0) {
648 channelSel = ((freq - 704) * 2 - 3040) / 10;
649 bModeSynth = 1;
650 } else {
651 ath_print(common, ATH_DBG_FATAL,
652 "Invalid channel %u MHz\n", freq);
653 return -EINVAL;
654 }
655
656 channelSel = (channelSel << 2) & 0xff;
657 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
658
659 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
660 if (freq == 2484) {
661
662 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
663 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
664 } else {
665 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
666 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
667 }
668
669 } else if ((freq % 20) == 0 && freq >= 5120) {
670 channelSel =
671 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
672 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
673 } else if ((freq % 10) == 0) {
674 channelSel =
675 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
676 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
677 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
678 else
679 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
680 } else if ((freq % 5) == 0) {
681 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
682 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
683 } else {
684 ath_print(common, ATH_DBG_FATAL,
685 "Invalid channel %u MHz\n", freq);
686 return -EINVAL;
687 }
688
689 ath9k_hw_force_bias(ah, freq);
690 ath9k_hw_decrease_chain_power(ah, chan);
691
692 reg32 =
693 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
694 (1 << 5) | 0x1;
695
696 REG_WRITE(ah, AR_PHY(0x37), reg32);
697
698 ah->curchan = chan;
699 ah->curchan_rad_index = -1;
700
701 return 0;
702}
703
704/**
705 * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
706 * @ah: atheros hardware structure
707 * @chan:
708 *
709 * For non single-chip solutions. Converts to baseband spur frequency given the
710 * input channel frequency and compute register settings below.
711 */
712void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
713{
714 int bb_spur = AR_NO_SPUR;
715 int bin, cur_bin;
716 int spur_freq_sd;
717 int spur_delta_phase;
718 int denominator;
719 int upper, lower, cur_vit_mask;
720 int tmp, new;
721 int i;
722 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
723 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
724 };
725 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
726 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
727 };
728 int inc[4] = { 0, 100, 0, 0 };
729
730 int8_t mask_m[123];
731 int8_t mask_p[123];
732 int8_t mask_amt;
733 int tmp_mask;
734 int cur_bb_spur;
735 bool is2GHz = IS_CHAN_2GHZ(chan);
736
737 memset(&mask_m, 0, sizeof(int8_t) * 123);
738 memset(&mask_p, 0, sizeof(int8_t) * 123);
739
740 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
741 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
742 if (AR_NO_SPUR == cur_bb_spur)
743 break;
744 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
745 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
746 bb_spur = cur_bb_spur;
747 break;
748 }
749 }
750
751 if (AR_NO_SPUR == bb_spur)
752 return;
753
754 bin = bb_spur * 32;
755
756 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
757 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
758 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
759 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
760 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
761
762 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
763
764 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
765 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
766 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
767 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
768 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
769 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
770
771 spur_delta_phase = ((bb_spur * 524288) / 100) &
772 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
773
774 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
775 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
776
777 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
778 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
779 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
780 REG_WRITE(ah, AR_PHY_TIMING11, new);
781
782 cur_bin = -6000;
783 upper = bin + 100;
784 lower = bin - 100;
785
786 for (i = 0; i < 4; i++) {
787 int pilot_mask = 0;
788 int chan_mask = 0;
789 int bp = 0;
790 for (bp = 0; bp < 30; bp++) {
791 if ((cur_bin > lower) && (cur_bin < upper)) {
792 pilot_mask = pilot_mask | 0x1 << bp;
793 chan_mask = chan_mask | 0x1 << bp;
794 }
795 cur_bin += 100;
796 }
797 cur_bin += inc[i];
798 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
799 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
800 }
801
802 cur_vit_mask = 6100;
803 upper = bin + 120;
804 lower = bin - 120;
805
806 for (i = 0; i < 123; i++) {
807 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
808
809 /* workaround for gcc bug #37014 */
810 volatile int tmp_v = abs(cur_vit_mask - bin);
811
812 if (tmp_v < 75)
813 mask_amt = 1;
814 else
815 mask_amt = 0;
816 if (cur_vit_mask < 0)
817 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
818 else
819 mask_p[cur_vit_mask / 100] = mask_amt;
820 }
821 cur_vit_mask -= 100;
822 }
823
824 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
825 | (mask_m[48] << 26) | (mask_m[49] << 24)
826 | (mask_m[50] << 22) | (mask_m[51] << 20)
827 | (mask_m[52] << 18) | (mask_m[53] << 16)
828 | (mask_m[54] << 14) | (mask_m[55] << 12)
829 | (mask_m[56] << 10) | (mask_m[57] << 8)
830 | (mask_m[58] << 6) | (mask_m[59] << 4)
831 | (mask_m[60] << 2) | (mask_m[61] << 0);
832 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
833 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
834
835 tmp_mask = (mask_m[31] << 28)
836 | (mask_m[32] << 26) | (mask_m[33] << 24)
837 | (mask_m[34] << 22) | (mask_m[35] << 20)
838 | (mask_m[36] << 18) | (mask_m[37] << 16)
839 | (mask_m[48] << 14) | (mask_m[39] << 12)
840 | (mask_m[40] << 10) | (mask_m[41] << 8)
841 | (mask_m[42] << 6) | (mask_m[43] << 4)
842 | (mask_m[44] << 2) | (mask_m[45] << 0);
843 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
844 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
845
846 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
847 | (mask_m[18] << 26) | (mask_m[18] << 24)
848 | (mask_m[20] << 22) | (mask_m[20] << 20)
849 | (mask_m[22] << 18) | (mask_m[22] << 16)
850 | (mask_m[24] << 14) | (mask_m[24] << 12)
851 | (mask_m[25] << 10) | (mask_m[26] << 8)
852 | (mask_m[27] << 6) | (mask_m[28] << 4)
853 | (mask_m[29] << 2) | (mask_m[30] << 0);
854 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
855 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
856
857 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
858 | (mask_m[2] << 26) | (mask_m[3] << 24)
859 | (mask_m[4] << 22) | (mask_m[5] << 20)
860 | (mask_m[6] << 18) | (mask_m[7] << 16)
861 | (mask_m[8] << 14) | (mask_m[9] << 12)
862 | (mask_m[10] << 10) | (mask_m[11] << 8)
863 | (mask_m[12] << 6) | (mask_m[13] << 4)
864 | (mask_m[14] << 2) | (mask_m[15] << 0);
865 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
866 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
867
868 tmp_mask = (mask_p[15] << 28)
869 | (mask_p[14] << 26) | (mask_p[13] << 24)
870 | (mask_p[12] << 22) | (mask_p[11] << 20)
871 | (mask_p[10] << 18) | (mask_p[9] << 16)
872 | (mask_p[8] << 14) | (mask_p[7] << 12)
873 | (mask_p[6] << 10) | (mask_p[5] << 8)
874 | (mask_p[4] << 6) | (mask_p[3] << 4)
875 | (mask_p[2] << 2) | (mask_p[1] << 0);
876 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
877 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
878
879 tmp_mask = (mask_p[30] << 28)
880 | (mask_p[29] << 26) | (mask_p[28] << 24)
881 | (mask_p[27] << 22) | (mask_p[26] << 20)
882 | (mask_p[25] << 18) | (mask_p[24] << 16)
883 | (mask_p[23] << 14) | (mask_p[22] << 12)
884 | (mask_p[21] << 10) | (mask_p[20] << 8)
885 | (mask_p[19] << 6) | (mask_p[18] << 4)
886 | (mask_p[17] << 2) | (mask_p[16] << 0);
887 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
888 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
889
890 tmp_mask = (mask_p[45] << 28)
891 | (mask_p[44] << 26) | (mask_p[43] << 24)
892 | (mask_p[42] << 22) | (mask_p[41] << 20)
893 | (mask_p[40] << 18) | (mask_p[39] << 16)
894 | (mask_p[38] << 14) | (mask_p[37] << 12)
895 | (mask_p[36] << 10) | (mask_p[35] << 8)
896 | (mask_p[34] << 6) | (mask_p[33] << 4)
897 | (mask_p[32] << 2) | (mask_p[31] << 0);
898 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
899 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
900
901 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
902 | (mask_p[59] << 26) | (mask_p[58] << 24)
903 | (mask_p[57] << 22) | (mask_p[56] << 20)
904 | (mask_p[55] << 18) | (mask_p[54] << 16)
905 | (mask_p[53] << 14) | (mask_p[52] << 12)
906 | (mask_p[51] << 10) | (mask_p[50] << 8)
907 | (mask_p[49] << 6) | (mask_p[48] << 4)
908 | (mask_p[47] << 2) | (mask_p[46] << 0);
909 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
910 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
911}
912
913/**
914 * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
915 * @ah: atheros hardware structure
916 *
917 * Only required for older devices with external AR2133/AR5133 radios.
918 */
919int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
920{
921#define ATH_ALLOC_BANK(bank, size) do { \
922 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
923 if (!bank) { \
924 ath_print(common, ATH_DBG_FATAL, \
925 "Cannot allocate RF banks\n"); \
926 return -ENOMEM; \
927 } \
928 } while (0);
929
930 struct ath_common *common = ath9k_hw_common(ah);
931
932 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
933
934 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
935 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
936 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
937 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
938 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
939 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
940 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
941 ATH_ALLOC_BANK(ah->addac5416_21,
942 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
943 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
944
945 return 0;
946#undef ATH_ALLOC_BANK
947}
948
949
950/**
951 * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
952 * @ah: atheros hardware struture
953 * For the external AR2133/AR5133 radios banks.
954 */
955void
956ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
957{
958#define ATH_FREE_BANK(bank) do { \
959 kfree(bank); \
960 bank = NULL; \
961 } while (0);
962
963 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
964
965 ATH_FREE_BANK(ah->analogBank0Data);
966 ATH_FREE_BANK(ah->analogBank1Data);
967 ATH_FREE_BANK(ah->analogBank2Data);
968 ATH_FREE_BANK(ah->analogBank3Data);
969 ATH_FREE_BANK(ah->analogBank6Data);
970 ATH_FREE_BANK(ah->analogBank6TPCData);
971 ATH_FREE_BANK(ah->analogBank7Data);
972 ATH_FREE_BANK(ah->addac5416_21);
973 ATH_FREE_BANK(ah->bank6Temp);
974
975#undef ATH_FREE_BANK
976}
977
978/* *
979 * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
980 * @ah: atheros hardware structure
981 * @chan:
982 * @modesIndex:
983 *
984 * Used for the external AR2133/AR5133 radios.
985 *
986 * Reads the EEPROM header info from the device structure and programs
987 * all rf registers. This routine requires access to the analog
988 * rf device. This is not required for single-chip devices.
989 */
990bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
991 u16 modesIndex)
215{ 992{
216 u32 eepMinorRev; 993 u32 eepMinorRev;
217 u32 ob5GHz = 0, db5GHz = 0; 994 u32 ob5GHz = 0, db5GHz = 0;
218 u32 ob2GHz = 0, db2GHz = 0; 995 u32 ob2GHz = 0, db2GHz = 0;
219 int regWrites = 0; 996 int regWrites = 0;
220 997
998 /*
999 * Software does not need to program bank data
1000 * for single chip devices, that is AR9280 or anything
1001 * after that.
1002 */
221 if (AR_SREV_9280_10_OR_LATER(ah)) 1003 if (AR_SREV_9280_10_OR_LATER(ah))
222 return true; 1004 return true;
223 1005
1006 /* Setup rf parameters */
224 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 1007 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
225 1008
1009 /* Setup Bank 0 Write */
226 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1); 1010 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
227 1011
1012 /* Setup Bank 1 Write */
228 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1); 1013 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
229 1014
1015 /* Setup Bank 2 Write */
230 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1); 1016 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
231 1017
1018 /* Setup Bank 6 Write */
232 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3, 1019 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
233 modesIndex); 1020 modesIndex);
234 { 1021 {
@@ -239,6 +1026,7 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
239 } 1026 }
240 } 1027 }
241 1028
1029 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
242 if (eepMinorRev >= 2) { 1030 if (eepMinorRev >= 2) {
243 if (IS_CHAN_2GHZ(chan)) { 1031 if (IS_CHAN_2GHZ(chan)) {
244 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 1032 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
@@ -257,8 +1045,10 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
257 } 1045 }
258 } 1046 }
259 1047
1048 /* Setup Bank 7 Setup */
260 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1); 1049 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
261 1050
1051 /* Write Analog registers */
262 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, 1052 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
263 regWrites); 1053 regWrites);
264 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, 1054 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
@@ -274,139 +1064,3 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
274 1064
275 return true; 1065 return true;
276} 1066}
277
278void
279ath9k_hw_rf_free(struct ath_hw *ah)
280{
281#define ATH_FREE_BANK(bank) do { \
282 kfree(bank); \
283 bank = NULL; \
284 } while (0);
285
286 ATH_FREE_BANK(ah->analogBank0Data);
287 ATH_FREE_BANK(ah->analogBank1Data);
288 ATH_FREE_BANK(ah->analogBank2Data);
289 ATH_FREE_BANK(ah->analogBank3Data);
290 ATH_FREE_BANK(ah->analogBank6Data);
291 ATH_FREE_BANK(ah->analogBank6TPCData);
292 ATH_FREE_BANK(ah->analogBank7Data);
293 ATH_FREE_BANK(ah->addac5416_21);
294 ATH_FREE_BANK(ah->bank6Temp);
295#undef ATH_FREE_BANK
296}
297
298bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
299{
300 struct ath_common *common = ath9k_hw_common(ah);
301
302 if (!AR_SREV_9280_10_OR_LATER(ah)) {
303 ah->analogBank0Data =
304 kzalloc((sizeof(u32) *
305 ah->iniBank0.ia_rows), GFP_KERNEL);
306 ah->analogBank1Data =
307 kzalloc((sizeof(u32) *
308 ah->iniBank1.ia_rows), GFP_KERNEL);
309 ah->analogBank2Data =
310 kzalloc((sizeof(u32) *
311 ah->iniBank2.ia_rows), GFP_KERNEL);
312 ah->analogBank3Data =
313 kzalloc((sizeof(u32) *
314 ah->iniBank3.ia_rows), GFP_KERNEL);
315 ah->analogBank6Data =
316 kzalloc((sizeof(u32) *
317 ah->iniBank6.ia_rows), GFP_KERNEL);
318 ah->analogBank6TPCData =
319 kzalloc((sizeof(u32) *
320 ah->iniBank6TPC.ia_rows), GFP_KERNEL);
321 ah->analogBank7Data =
322 kzalloc((sizeof(u32) *
323 ah->iniBank7.ia_rows), GFP_KERNEL);
324
325 if (ah->analogBank0Data == NULL
326 || ah->analogBank1Data == NULL
327 || ah->analogBank2Data == NULL
328 || ah->analogBank3Data == NULL
329 || ah->analogBank6Data == NULL
330 || ah->analogBank6TPCData == NULL
331 || ah->analogBank7Data == NULL) {
332 ath_print(common, ATH_DBG_FATAL,
333 "Cannot allocate RF banks\n");
334 *status = -ENOMEM;
335 return false;
336 }
337
338 ah->addac5416_21 =
339 kzalloc((sizeof(u32) *
340 ah->iniAddac.ia_rows *
341 ah->iniAddac.ia_columns), GFP_KERNEL);
342 if (ah->addac5416_21 == NULL) {
343 ath_print(common, ATH_DBG_FATAL,
344 "Cannot allocate addac5416_21\n");
345 *status = -ENOMEM;
346 return false;
347 }
348
349 ah->bank6Temp =
350 kzalloc((sizeof(u32) *
351 ah->iniBank6.ia_rows), GFP_KERNEL);
352 if (ah->bank6Temp == NULL) {
353 ath_print(common, ATH_DBG_FATAL,
354 "Cannot allocate bank6Temp\n");
355 *status = -ENOMEM;
356 return false;
357 }
358 }
359
360 return true;
361}
362
363void
364ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
365{
366 int i, regWrites = 0;
367 u32 bank6SelMask;
368 u32 *bank6Temp = ah->bank6Temp;
369
370 switch (ah->config.diversity_control) {
371 case ATH9K_ANT_FIXED_A:
372 bank6SelMask =
373 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
374 REDUCE_CHAIN_0 : REDUCE_CHAIN_1;
375 break;
376 case ATH9K_ANT_FIXED_B:
377 bank6SelMask =
378 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
379 REDUCE_CHAIN_1 : REDUCE_CHAIN_0;
380 break;
381 case ATH9K_ANT_VARIABLE:
382 return;
383 break;
384 default:
385 return;
386 break;
387 }
388
389 for (i = 0; i < ah->iniBank6.ia_rows; i++)
390 bank6Temp[i] = ah->analogBank6Data[i];
391
392 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
393
394 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
395 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
396 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
397 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
398 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
399 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
400 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
401 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
402 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
403
404 REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
405
406 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
407#ifdef ALTER_SWITCH
408 REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
409 (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
410 | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
411#endif
412}
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index 140fef74c666..dc145a135dc7 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -17,20 +17,26 @@
17#ifndef PHY_H 17#ifndef PHY_H
18#define PHY_H 18#define PHY_H
19 19
20void ath9k_hw_ar9280_set_channel(struct ath_hw *ah, 20/* Common between single chip and non single-chip solutions */
21 struct ath9k_channel 21void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites);
22 *chan); 22
23bool ath9k_hw_set_channel(struct ath_hw *ah, 23/* Single chip radio settings */
24 struct ath9k_channel *chan); 24int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
25void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, 25void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
26 u32 freqIndex, int regWrites); 26
27/* Routines below are for non single-chip solutions */
28int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
29void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
30
31int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
32void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
33
27bool ath9k_hw_set_rf_regs(struct ath_hw *ah, 34bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
28 struct ath9k_channel *chan, 35 struct ath9k_channel *chan,
29 u16 modesIndex); 36 u16 modesIndex);
37
30void ath9k_hw_decrease_chain_power(struct ath_hw *ah, 38void ath9k_hw_decrease_chain_power(struct ath_hw *ah,
31 struct ath9k_channel *chan); 39 struct ath9k_channel *chan);
32bool ath9k_hw_init_rf(struct ath_hw *ah,
33 int *status);
34 40
35#define AR_PHY_BASE 0x9800 41#define AR_PHY_BASE 0x9800
36#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 42#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
@@ -186,8 +192,20 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
186#define AR_PHY_PLL_CTL_44_2133 0xeb 192#define AR_PHY_PLL_CTL_44_2133 0xeb
187#define AR_PHY_PLL_CTL_40_2133 0xea 193#define AR_PHY_PLL_CTL_40_2133 0xea
188 194
189#define AR_PHY_SPECTRAL_SCAN 0x9912 195#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
190#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1 196#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
197#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
198#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
199#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
200#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
201#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
202#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
203#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
204#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
205#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
206#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
207#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
208#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
191 209
192#define AR_PHY_RX_DELAY 0x9914 210#define AR_PHY_RX_DELAY 0x9914
193#define AR_PHY_SEARCH_START_DELAY 0x9918 211#define AR_PHY_SEARCH_START_DELAY 0x9918
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index c880a55939bf..355dd1834e1d 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -202,7 +202,8 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
202 } 202 }
203 203
204 rcu_read_lock(); 204 rcu_read_lock();
205 sta = ieee80211_find_sta(sc->hw, hdr->addr2); 205 /* XXX: use ieee80211_find_sta! */
206 sta = ieee80211_find_sta_by_hw(sc->hw, hdr->addr2);
206 if (sta) { 207 if (sta) {
207 an = (struct ath_node *) sta->drv_priv; 208 an = (struct ath_node *) sta->drv_priv;
208 if (ds->ds_rxstat.rs_rssi != ATH9K_RSSI_BAD && 209 if (ds->ds_rxstat.rs_rssi != ATH9K_RSSI_BAD &&
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index ceed0095efac..061e12ce0b24 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -1704,4 +1704,7 @@ enum {
1704#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) 1704#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24)
1705#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) 1705#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28)
1706 1706
1707#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
1708#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
1709
1707#endif 1710#endif
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 2a4efcbced60..8e052f406c35 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -282,7 +282,8 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
282 282
283 rcu_read_lock(); 283 rcu_read_lock();
284 284
285 sta = ieee80211_find_sta(sc->hw, hdr->addr1); 285 /* XXX: use ieee80211_find_sta! */
286 sta = ieee80211_find_sta_by_hw(sc->hw, hdr->addr1);
286 if (!sta) { 287 if (!sta) {
287 rcu_read_unlock(); 288 rcu_read_unlock();
288 return; 289 return;
diff --git a/drivers/net/wireless/b43/Kconfig b/drivers/net/wireless/b43/Kconfig
index 54ea61c15d8b..64c12e1bced3 100644
--- a/drivers/net/wireless/b43/Kconfig
+++ b/drivers/net/wireless/b43/Kconfig
@@ -1,6 +1,6 @@
1config B43 1config B43
2 tristate "Broadcom 43xx wireless support (mac80211 stack)" 2 tristate "Broadcom 43xx wireless support (mac80211 stack)"
3 depends on SSB_POSSIBLE && MAC80211 && WLAN_80211 && HAS_DMA 3 depends on SSB_POSSIBLE && MAC80211 && HAS_DMA
4 select SSB 4 select SSB
5 select FW_LOADER 5 select FW_LOADER
6 ---help--- 6 ---help---
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index 65b23f725a04..fe3bf9491997 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -26,8 +26,6 @@
26# define B43_DEBUG 0 26# define B43_DEBUG 0
27#endif 27#endif
28 28
29#define B43_RX_MAX_SSI 60
30
31/* MMIO offsets */ 29/* MMIO offsets */
32#define B43_MMIO_DMA0_REASON 0x20 30#define B43_MMIO_DMA0_REASON 0x20
33#define B43_MMIO_DMA0_IRQ_MASK 0x24 31#define B43_MMIO_DMA0_IRQ_MASK 0x24
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index ed6e96a34743..c806924c7b5c 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -3573,7 +3573,7 @@ static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3573 if (conf->channel->hw_value != phy->channel) 3573 if (conf->channel->hw_value != phy->channel)
3574 b43_switch_channel(dev, conf->channel->hw_value); 3574 b43_switch_channel(dev, conf->channel->hw_value);
3575 3575
3576 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP); 3576 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3577 3577
3578 /* Adjust the desired TX power level. */ 3578 /* Adjust the desired TX power level. */
3579 if (conf->power_level != 0) { 3579 if (conf->power_level != 0) {
diff --git a/drivers/net/wireless/b43/phy_lp.c b/drivers/net/wireless/b43/phy_lp.c
index c6987b147af4..3e046ec1ff86 100644
--- a/drivers/net/wireless/b43/phy_lp.c
+++ b/drivers/net/wireless/b43/phy_lp.c
@@ -67,6 +67,7 @@ static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
67 struct b43_phy_lp *lpphy = phy->lp; 67 struct b43_phy_lp *lpphy = phy->lp;
68 68
69 memset(lpphy, 0, sizeof(*lpphy)); 69 memset(lpphy, 0, sizeof(*lpphy));
70 lpphy->antenna = B43_ANTENNA_DEFAULT;
70 71
71 //TODO 72 //TODO
72} 73}
@@ -379,8 +380,6 @@ static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
379 } 380 }
380} 381}
381 382
382/* lpphy_restore_dig_flt_state is unused but kept as a reference */
383#if 0
384static void lpphy_restore_dig_flt_state(struct b43_wldev *dev) 383static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
385{ 384{
386 static const u16 addr[] = { 385 static const u16 addr[] = {
@@ -401,7 +400,6 @@ static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
401 for (i = 0; i < ARRAY_SIZE(addr); i++) 400 for (i = 0; i < ARRAY_SIZE(addr); i++)
402 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]); 401 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
403} 402}
404#endif
405 403
406static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev) 404static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
407{ 405{
@@ -754,11 +752,17 @@ static void lpphy_clear_deaf(struct b43_wldev *dev, bool user)
754 } 752 }
755} 753}
756 754
755static void lpphy_set_trsw_over(struct b43_wldev *dev, bool tx, bool rx)
756{
757 u16 trsw = (tx << 1) | rx;
758 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, trsw);
759 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
760}
761
757static void lpphy_disable_crs(struct b43_wldev *dev, bool user) 762static void lpphy_disable_crs(struct b43_wldev *dev, bool user)
758{ 763{
759 lpphy_set_deaf(dev, user); 764 lpphy_set_deaf(dev, user);
760 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1); 765 lpphy_set_trsw_over(dev, false, true);
761 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
762 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB); 766 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
763 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4); 767 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
764 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7); 768 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7);
@@ -793,6 +797,60 @@ static void lpphy_restore_crs(struct b43_wldev *dev, bool user)
793 797
794struct lpphy_tx_gains { u16 gm, pga, pad, dac; }; 798struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
795 799
800static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
801{
802 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
803 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
804 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
805 if (dev->phy.rev >= 2) {
806 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
807 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
808 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
809 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
810 }
811 } else {
812 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
813 }
814}
815
816static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
817{
818 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
819 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
820 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
821 if (dev->phy.rev >= 2) {
822 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
823 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
824 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
825 b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
826 }
827 } else {
828 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
829 }
830}
831
832static void lpphy_disable_tx_gain_override(struct b43_wldev *dev)
833{
834 if (dev->phy.rev < 2)
835 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
836 else {
837 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F);
838 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF);
839 }
840 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF);
841}
842
843static void lpphy_enable_tx_gain_override(struct b43_wldev *dev)
844{
845 if (dev->phy.rev < 2)
846 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
847 else {
848 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x80);
849 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x4000);
850 }
851 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x40);
852}
853
796static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev) 854static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
797{ 855{
798 struct lpphy_tx_gains gains; 856 struct lpphy_tx_gains gains;
@@ -822,6 +880,17 @@ static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
822 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl); 880 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
823} 881}
824 882
883static u16 lpphy_get_pa_gain(struct b43_wldev *dev)
884{
885 return b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F;
886}
887
888static void lpphy_set_pa_gain(struct b43_wldev *dev, u16 gain)
889{
890 b43_phy_maskset(dev, B43_PHY_OFDM(0xFB), 0xE03F, gain << 6);
891 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD), 0x80FF, gain << 8);
892}
893
825static void lpphy_set_tx_gains(struct b43_wldev *dev, 894static void lpphy_set_tx_gains(struct b43_wldev *dev,
826 struct lpphy_tx_gains gains) 895 struct lpphy_tx_gains gains)
827{ 896{
@@ -832,25 +901,22 @@ static void lpphy_set_tx_gains(struct b43_wldev *dev,
832 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 901 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
833 0xF800, rf_gain); 902 0xF800, rf_gain);
834 } else { 903 } else {
835 pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x1FC0; 904 pa_gain = lpphy_get_pa_gain(dev);
836 pa_gain <<= 2;
837 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 905 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
838 (gains.pga << 8) | gains.gm); 906 (gains.pga << 8) | gains.gm);
907 /*
908 * SPEC FIXME The spec calls for (pa_gain << 8) here, but that
909 * conflicts with the spec for set_pa_gain! Vendor driver bug?
910 */
839 b43_phy_maskset(dev, B43_PHY_OFDM(0xFB), 911 b43_phy_maskset(dev, B43_PHY_OFDM(0xFB),
840 0x8000, gains.pad | pa_gain); 912 0x8000, gains.pad | (pa_gain << 6));
841 b43_phy_write(dev, B43_PHY_OFDM(0xFC), 913 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
842 (gains.pga << 8) | gains.gm); 914 (gains.pga << 8) | gains.gm);
843 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD), 915 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
844 0x8000, gains.pad | pa_gain); 916 0x8000, gains.pad | (pa_gain << 8));
845 } 917 }
846 lpphy_set_dac_gain(dev, gains.dac); 918 lpphy_set_dac_gain(dev, gains.dac);
847 if (dev->phy.rev < 2) { 919 lpphy_enable_tx_gain_override(dev);
848 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
849 } else {
850 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
851 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
852 }
853 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF, 1 << 6);
854} 920}
855 921
856static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain) 922static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
@@ -890,41 +956,6 @@ static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
890 } 956 }
891} 957}
892 958
893/* lpphy_disable_rx_gain_override is unused but kept as a reference */
894#if 0
895static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
896{
897 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
898 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
899 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
900 if (dev->phy.rev >= 2) {
901 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
902 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
903 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
904 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
905 }
906 } else {
907 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
908 }
909}
910#endif
911
912static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
913{
914 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
915 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
916 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
917 if (dev->phy.rev >= 2) {
918 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
919 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
920 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
921 b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
922 }
923 } else {
924 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
925 }
926}
927
928static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain) 959static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
929{ 960{
930 if (dev->phy.rev < 2) 961 if (dev->phy.rev < 2)
@@ -1009,8 +1040,7 @@ static int lpphy_loopback(struct b43_wldev *dev)
1009 1040
1010 memset(&iq_est, 0, sizeof(iq_est)); 1041 memset(&iq_est, 0, sizeof(iq_est));
1011 1042
1012 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3); 1043 lpphy_set_trsw_over(dev, true, true);
1013 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
1014 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1); 1044 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1);
1015 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE); 1045 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
1016 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800); 1046 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
@@ -1132,7 +1162,7 @@ static void lpphy_set_tx_power_control(struct b43_wldev *dev,
1132 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 1162 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1133 0x8FFF, ((u16)lpphy->tssi_npt << 16)); 1163 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1134 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count 1164 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1135 //TODO Disable TX gain override 1165 lpphy_disable_tx_gain_override(dev);
1136 lpphy->tx_pwr_idx_over = -1; 1166 lpphy->tx_pwr_idx_over = -1;
1137 } 1167 }
1138 } 1168 }
@@ -1318,15 +1348,73 @@ static void lpphy_calibrate_rc(struct b43_wldev *dev)
1318 } 1348 }
1319} 1349}
1320 1350
1351static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
1352{
1353 if (dev->phy.rev >= 2)
1354 return; // rev2+ doesn't support antenna diversity
1355
1356 if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1))
1357 return;
1358
1359 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);
1360
1361 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2);
1362 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1);
1363
1364 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);
1365
1366 dev->phy.lp->antenna = antenna;
1367}
1368
1369static void lpphy_set_tx_iqcc(struct b43_wldev *dev, u16 a, u16 b)
1370{
1371 u16 tmp[2];
1372
1373 tmp[0] = a;
1374 tmp[1] = b;
1375 b43_lptab_write_bulk(dev, B43_LPTAB16(0, 80), 2, tmp);
1376}
1377
1321static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index) 1378static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1322{ 1379{
1323 struct b43_phy_lp *lpphy = dev->phy.lp; 1380 struct b43_phy_lp *lpphy = dev->phy.lp;
1381 struct lpphy_tx_gains gains;
1382 u32 iq_comp, tx_gain, coeff, rf_power;
1324 1383
1325 lpphy->tx_pwr_idx_over = index; 1384 lpphy->tx_pwr_idx_over = index;
1385 lpphy_read_tx_pctl_mode_from_hardware(dev);
1326 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF) 1386 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1327 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW); 1387 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1328 1388 if (dev->phy.rev >= 2) {
1329 //TODO 1389 iq_comp = b43_lptab_read(dev, B43_LPTAB32(7, index + 320));
1390 tx_gain = b43_lptab_read(dev, B43_LPTAB32(7, index + 192));
1391 gains.pad = (tx_gain >> 16) & 0xFF;
1392 gains.gm = tx_gain & 0xFF;
1393 gains.pga = (tx_gain >> 8) & 0xFF;
1394 gains.dac = (iq_comp >> 28) & 0xFF;
1395 lpphy_set_tx_gains(dev, gains);
1396 } else {
1397 iq_comp = b43_lptab_read(dev, B43_LPTAB32(10, index + 320));
1398 tx_gain = b43_lptab_read(dev, B43_LPTAB32(10, index + 192));
1399 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
1400 0xF800, (tx_gain >> 4) & 0x7FFF);
1401 lpphy_set_dac_gain(dev, tx_gain & 0x7);
1402 lpphy_set_pa_gain(dev, (tx_gain >> 24) & 0x7F);
1403 }
1404 lpphy_set_bb_mult(dev, (iq_comp >> 20) & 0xFF);
1405 lpphy_set_tx_iqcc(dev, (iq_comp >> 10) & 0x3FF, iq_comp & 0x3FF);
1406 if (dev->phy.rev >= 2) {
1407 coeff = b43_lptab_read(dev, B43_LPTAB32(7, index + 448));
1408 } else {
1409 coeff = b43_lptab_read(dev, B43_LPTAB32(10, index + 448));
1410 }
1411 b43_lptab_write(dev, B43_LPTAB16(0, 85), coeff & 0xFFFF);
1412 if (dev->phy.rev >= 2) {
1413 rf_power = b43_lptab_read(dev, B43_LPTAB32(7, index + 576));
1414 b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00,
1415 rf_power & 0xFFFF);//SPEC FIXME mask & set != 0
1416 }
1417 lpphy_enable_tx_gain_override(dev);
1330} 1418}
1331 1419
1332static void lpphy_btcoex_override(struct b43_wldev *dev) 1420static void lpphy_btcoex_override(struct b43_wldev *dev)
@@ -1335,58 +1423,45 @@ static void lpphy_btcoex_override(struct b43_wldev *dev)
1335 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF); 1423 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1336} 1424}
1337 1425
1338static void lpphy_pr41573_workaround(struct b43_wldev *dev) 1426static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
1427 bool blocked)
1339{ 1428{
1340 struct b43_phy_lp *lpphy = dev->phy.lp; 1429 //TODO check MAC control register
1341 u32 *saved_tab; 1430 if (blocked) {
1342 const unsigned int saved_tab_size = 256; 1431 if (dev->phy.rev >= 2) {
1343 enum b43_lpphy_txpctl_mode txpctl_mode; 1432 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF);
1344 s8 tx_pwr_idx_over; 1433 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
1345 u16 tssi_npt, tssi_idx; 1434 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF);
1346 1435 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF);
1347 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL); 1436 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0808);
1348 if (!saved_tab) { 1437 } else {
1349 b43err(dev->wl, "PR41573 failed. Out of memory!\n"); 1438 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF);
1350 return; 1439 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
1351 } 1440 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF);
1352 1441 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0018);
1353 lpphy_read_tx_pctl_mode_from_hardware(dev); 1442 }
1354 txpctl_mode = lpphy->txpctl_mode;
1355 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1356 tssi_npt = lpphy->tssi_npt;
1357 tssi_idx = lpphy->tssi_idx;
1358
1359 if (dev->phy.rev < 2) {
1360 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1361 saved_tab_size, saved_tab);
1362 } else { 1443 } else {
1363 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140), 1444 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF);
1364 saved_tab_size, saved_tab); 1445 if (dev->phy.rev >= 2)
1446 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7);
1447 else
1448 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7);
1365 } 1449 }
1366 //TODO
1367
1368 kfree(saved_tab);
1369} 1450}
1370 1451
1371static void lpphy_calibration(struct b43_wldev *dev) 1452/* This was previously called lpphy_japan_filter */
1453static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
1372{ 1454{
1373 struct b43_phy_lp *lpphy = dev->phy.lp; 1455 struct b43_phy_lp *lpphy = dev->phy.lp;
1374 enum b43_lpphy_txpctl_mode saved_pctl_mode; 1456 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
1375
1376 b43_mac_suspend(dev);
1377
1378 lpphy_btcoex_override(dev);
1379 lpphy_read_tx_pctl_mode_from_hardware(dev);
1380 saved_pctl_mode = lpphy->txpctl_mode;
1381 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1382 //TODO Perform transmit power table I/Q LO calibration
1383 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1384 lpphy_pr41573_workaround(dev);
1385 //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
1386 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1387 //TODO Perform I/Q calibration with a single control value set
1388 1457
1389 b43_mac_enable(dev); 1458 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
1459 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
1460 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
1461 lpphy_set_rc_cap(dev);
1462 } else {
1463 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
1464 }
1390} 1465}
1391 1466
1392static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode) 1467static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
@@ -1495,6 +1570,473 @@ static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1495 } 1570 }
1496} 1571}
1497 1572
1573static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1574{
1575 struct b43_phy_lp *lpphy = dev->phy.lp;
1576 u32 *saved_tab;
1577 const unsigned int saved_tab_size = 256;
1578 enum b43_lpphy_txpctl_mode txpctl_mode;
1579 s8 tx_pwr_idx_over;
1580 u16 tssi_npt, tssi_idx;
1581
1582 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1583 if (!saved_tab) {
1584 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1585 return;
1586 }
1587
1588 lpphy_read_tx_pctl_mode_from_hardware(dev);
1589 txpctl_mode = lpphy->txpctl_mode;
1590 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1591 tssi_npt = lpphy->tssi_npt;
1592 tssi_idx = lpphy->tssi_idx;
1593
1594 if (dev->phy.rev < 2) {
1595 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1596 saved_tab_size, saved_tab);
1597 } else {
1598 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1599 saved_tab_size, saved_tab);
1600 }
1601 //FIXME PHY reset
1602 lpphy_table_init(dev); //FIXME is table init needed?
1603 lpphy_baseband_init(dev);
1604 lpphy_tx_pctl_init(dev);
1605 b43_lpphy_op_software_rfkill(dev, false);
1606 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1607 if (dev->phy.rev < 2) {
1608 b43_lptab_write_bulk(dev, B43_LPTAB32(10, 0x140),
1609 saved_tab_size, saved_tab);
1610 } else {
1611 b43_lptab_write_bulk(dev, B43_LPTAB32(7, 0x140),
1612 saved_tab_size, saved_tab);
1613 }
1614 b43_write16(dev, B43_MMIO_CHANNEL, lpphy->channel);
1615 lpphy->tssi_npt = tssi_npt;
1616 lpphy->tssi_idx = tssi_idx;
1617 lpphy_set_analog_filter(dev, lpphy->channel);
1618 if (tx_pwr_idx_over != -1)
1619 lpphy_set_tx_power_by_index(dev, tx_pwr_idx_over);
1620 if (lpphy->rc_cap)
1621 lpphy_set_rc_cap(dev);
1622 b43_lpphy_op_set_rx_antenna(dev, lpphy->antenna);
1623 lpphy_set_tx_power_control(dev, txpctl_mode);
1624 kfree(saved_tab);
1625}
1626
1627struct lpphy_rx_iq_comp { u8 chan; s8 c1, c0; };
1628
1629static const struct lpphy_rx_iq_comp lpphy_5354_iq_table[] = {
1630 { .chan = 1, .c1 = -66, .c0 = 15, },
1631 { .chan = 2, .c1 = -66, .c0 = 15, },
1632 { .chan = 3, .c1 = -66, .c0 = 15, },
1633 { .chan = 4, .c1 = -66, .c0 = 15, },
1634 { .chan = 5, .c1 = -66, .c0 = 15, },
1635 { .chan = 6, .c1 = -66, .c0 = 15, },
1636 { .chan = 7, .c1 = -66, .c0 = 14, },
1637 { .chan = 8, .c1 = -66, .c0 = 14, },
1638 { .chan = 9, .c1 = -66, .c0 = 14, },
1639 { .chan = 10, .c1 = -66, .c0 = 14, },
1640 { .chan = 11, .c1 = -66, .c0 = 14, },
1641 { .chan = 12, .c1 = -66, .c0 = 13, },
1642 { .chan = 13, .c1 = -66, .c0 = 13, },
1643 { .chan = 14, .c1 = -66, .c0 = 13, },
1644};
1645
1646static const struct lpphy_rx_iq_comp lpphy_rev0_1_iq_table[] = {
1647 { .chan = 1, .c1 = -64, .c0 = 13, },
1648 { .chan = 2, .c1 = -64, .c0 = 13, },
1649 { .chan = 3, .c1 = -64, .c0 = 13, },
1650 { .chan = 4, .c1 = -64, .c0 = 13, },
1651 { .chan = 5, .c1 = -64, .c0 = 12, },
1652 { .chan = 6, .c1 = -64, .c0 = 12, },
1653 { .chan = 7, .c1 = -64, .c0 = 12, },
1654 { .chan = 8, .c1 = -64, .c0 = 12, },
1655 { .chan = 9, .c1 = -64, .c0 = 12, },
1656 { .chan = 10, .c1 = -64, .c0 = 11, },
1657 { .chan = 11, .c1 = -64, .c0 = 11, },
1658 { .chan = 12, .c1 = -64, .c0 = 11, },
1659 { .chan = 13, .c1 = -64, .c0 = 11, },
1660 { .chan = 14, .c1 = -64, .c0 = 10, },
1661 { .chan = 34, .c1 = -62, .c0 = 24, },
1662 { .chan = 38, .c1 = -62, .c0 = 24, },
1663 { .chan = 42, .c1 = -62, .c0 = 24, },
1664 { .chan = 46, .c1 = -62, .c0 = 23, },
1665 { .chan = 36, .c1 = -62, .c0 = 24, },
1666 { .chan = 40, .c1 = -62, .c0 = 24, },
1667 { .chan = 44, .c1 = -62, .c0 = 23, },
1668 { .chan = 48, .c1 = -62, .c0 = 23, },
1669 { .chan = 52, .c1 = -62, .c0 = 23, },
1670 { .chan = 56, .c1 = -62, .c0 = 22, },
1671 { .chan = 60, .c1 = -62, .c0 = 22, },
1672 { .chan = 64, .c1 = -62, .c0 = 22, },
1673 { .chan = 100, .c1 = -62, .c0 = 16, },
1674 { .chan = 104, .c1 = -62, .c0 = 16, },
1675 { .chan = 108, .c1 = -62, .c0 = 15, },
1676 { .chan = 112, .c1 = -62, .c0 = 14, },
1677 { .chan = 116, .c1 = -62, .c0 = 14, },
1678 { .chan = 120, .c1 = -62, .c0 = 13, },
1679 { .chan = 124, .c1 = -62, .c0 = 12, },
1680 { .chan = 128, .c1 = -62, .c0 = 12, },
1681 { .chan = 132, .c1 = -62, .c0 = 12, },
1682 { .chan = 136, .c1 = -62, .c0 = 11, },
1683 { .chan = 140, .c1 = -62, .c0 = 10, },
1684 { .chan = 149, .c1 = -61, .c0 = 9, },
1685 { .chan = 153, .c1 = -61, .c0 = 9, },
1686 { .chan = 157, .c1 = -61, .c0 = 9, },
1687 { .chan = 161, .c1 = -61, .c0 = 8, },
1688 { .chan = 165, .c1 = -61, .c0 = 8, },
1689 { .chan = 184, .c1 = -62, .c0 = 25, },
1690 { .chan = 188, .c1 = -62, .c0 = 25, },
1691 { .chan = 192, .c1 = -62, .c0 = 25, },
1692 { .chan = 196, .c1 = -62, .c0 = 25, },
1693 { .chan = 200, .c1 = -62, .c0 = 25, },
1694 { .chan = 204, .c1 = -62, .c0 = 25, },
1695 { .chan = 208, .c1 = -62, .c0 = 25, },
1696 { .chan = 212, .c1 = -62, .c0 = 25, },
1697 { .chan = 216, .c1 = -62, .c0 = 26, },
1698};
1699
1700static const struct lpphy_rx_iq_comp lpphy_rev2plus_iq_comp = {
1701 .chan = 0,
1702 .c1 = -64,
1703 .c0 = 0,
1704};
1705
1706static u8 lpphy_nbits(s32 val)
1707{
1708 u32 tmp = abs(val);
1709 u8 nbits = 0;
1710
1711 while (tmp != 0) {
1712 nbits++;
1713 tmp >>= 1;
1714 }
1715
1716 return nbits;
1717}
1718
1719static int lpphy_calc_rx_iq_comp(struct b43_wldev *dev, u16 samples)
1720{
1721 struct lpphy_iq_est iq_est;
1722 u16 c0, c1;
1723 int prod, ipwr, qpwr, prod_msb, q_msb, tmp1, tmp2, tmp3, tmp4, ret;
1724
1725 c1 = b43_phy_read(dev, B43_LPPHY_RX_COMP_COEFF_S);
1726 c0 = c1 >> 8;
1727 c1 |= 0xFF;
1728
1729 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, 0x00C0);
1730 b43_phy_mask(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF);
1731
1732 ret = lpphy_rx_iq_est(dev, samples, 32, &iq_est);
1733 if (!ret)
1734 goto out;
1735
1736 prod = iq_est.iq_prod;
1737 ipwr = iq_est.i_pwr;
1738 qpwr = iq_est.q_pwr;
1739
1740 if (ipwr + qpwr < 2) {
1741 ret = 0;
1742 goto out;
1743 }
1744
1745 prod_msb = lpphy_nbits(prod);
1746 q_msb = lpphy_nbits(qpwr);
1747 tmp1 = prod_msb - 20;
1748
1749 if (tmp1 >= 0) {
1750 tmp3 = ((prod << (30 - prod_msb)) + (ipwr >> (1 + tmp1))) /
1751 (ipwr >> tmp1);
1752 } else {
1753 tmp3 = ((prod << (30 - prod_msb)) + (ipwr << (-1 - tmp1))) /
1754 (ipwr << -tmp1);
1755 }
1756
1757 tmp2 = q_msb - 11;
1758
1759 if (tmp2 >= 0)
1760 tmp4 = (qpwr << (31 - q_msb)) / (ipwr >> tmp2);
1761 else
1762 tmp4 = (qpwr << (31 - q_msb)) / (ipwr << -tmp2);
1763
1764 tmp4 -= tmp3 * tmp3;
1765 tmp4 = -int_sqrt(tmp4);
1766
1767 c0 = tmp3 >> 3;
1768 c1 = tmp4 >> 4;
1769
1770out:
1771 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, c1);
1772 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF, c0 << 8);
1773 return ret;
1774}
1775
1776/* Complex number using 2 32-bit signed integers */
1777typedef struct {s32 i, q;} lpphy_c32;
1778
1779static lpphy_c32 lpphy_cordic(int theta)
1780{
1781 u32 arctg[] = { 2949120, 1740967, 919879, 466945, 234379, 117304,
1782 58666, 29335, 14668, 7334, 3667, 1833, 917, 458,
1783 229, 115, 57, 29, };
1784 int i, tmp, signx = 1, angle = 0;
1785 lpphy_c32 ret = { .i = 39797, .q = 0, };
1786
1787 theta = clamp_t(int, theta, -180, 180);
1788
1789 if (theta > 90) {
1790 theta -= 180;
1791 signx = -1;
1792 } else if (theta < -90) {
1793 theta += 180;
1794 signx = -1;
1795 }
1796
1797 for (i = 0; i <= 17; i++) {
1798 if (theta > angle) {
1799 tmp = ret.i - (ret.q >> i);
1800 ret.q += ret.i >> i;
1801 ret.i = tmp;
1802 angle += arctg[i];
1803 } else {
1804 tmp = ret.i + (ret.q >> i);
1805 ret.q -= ret.i >> i;
1806 ret.i = tmp;
1807 angle -= arctg[i];
1808 }
1809 }
1810
1811 ret.i *= signx;
1812 ret.q *= signx;
1813
1814 return ret;
1815}
1816
1817static void lpphy_run_samples(struct b43_wldev *dev, u16 samples, u16 loops,
1818 u16 wait)
1819{
1820 b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL,
1821 0xFFC0, samples - 1);
1822 if (loops != 0xFFFF)
1823 loops--;
1824 b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000, loops);
1825 b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL, 0x3F, wait << 6);
1826 b43_phy_set(dev, B43_LPPHY_A_PHY_CTL_ADDR, 0x1);
1827}
1828
1829//SPEC FIXME what does a negative freq mean?
1830static void lpphy_start_tx_tone(struct b43_wldev *dev, s32 freq, u16 max)
1831{
1832 struct b43_phy_lp *lpphy = dev->phy.lp;
1833 u16 buf[64];
1834 int i, samples = 0, angle = 0, rotation = (9 * freq) / 500;
1835 lpphy_c32 sample;
1836
1837 lpphy->tx_tone_freq = freq;
1838
1839 if (freq) {
1840 /* Find i for which abs(freq) integrally divides 20000 * i */
1841 for (i = 1; samples * abs(freq) != 20000 * i; i++) {
1842 samples = (20000 * i) / abs(freq);
1843 if(B43_WARN_ON(samples > 63))
1844 return;
1845 }
1846 } else {
1847 samples = 2;
1848 }
1849
1850 for (i = 0; i < samples; i++) {
1851 sample = lpphy_cordic(angle);
1852 angle += rotation;
1853 buf[i] = ((sample.i * max) & 0xFF) << 8;
1854 buf[i] |= (sample.q * max) & 0xFF;
1855 }
1856
1857 b43_lptab_write_bulk(dev, B43_LPTAB16(5, 0), samples, buf);
1858
1859 lpphy_run_samples(dev, samples, 0xFFFF, 0);
1860}
1861
1862static void lpphy_stop_tx_tone(struct b43_wldev *dev)
1863{
1864 struct b43_phy_lp *lpphy = dev->phy.lp;
1865 int i;
1866
1867 lpphy->tx_tone_freq = 0;
1868
1869 b43_phy_mask(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000);
1870 for (i = 0; i < 31; i++) {
1871 if (!(b43_phy_read(dev, B43_LPPHY_A_PHY_CTL_ADDR) & 0x1))
1872 break;
1873 udelay(100);
1874 }
1875}
1876
1877
1878static void lpphy_papd_cal(struct b43_wldev *dev, struct lpphy_tx_gains gains,
1879 int mode, bool useindex, u8 index)
1880{
1881 //TODO
1882}
1883
1884static void lpphy_papd_cal_txpwr(struct b43_wldev *dev)
1885{
1886 struct b43_phy_lp *lpphy = dev->phy.lp;
1887 struct ssb_bus *bus = dev->dev->bus;
1888 struct lpphy_tx_gains gains, oldgains;
1889 int old_txpctl, old_afe_ovr, old_rf, old_bbmult;
1890
1891 lpphy_read_tx_pctl_mode_from_hardware(dev);
1892 old_txpctl = lpphy->txpctl_mode;
1893 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40;
1894 if (old_afe_ovr)
1895 oldgains = lpphy_get_tx_gains(dev);
1896 old_rf = b43_phy_read(dev, B43_LPPHY_RF_PWR_OVERRIDE) & 0xFF;
1897 old_bbmult = lpphy_get_bb_mult(dev);
1898
1899 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1900
1901 if (bus->chip_id == 0x4325 && bus->chip_rev == 0)
1902 lpphy_papd_cal(dev, gains, 0, 1, 30);
1903 else
1904 lpphy_papd_cal(dev, gains, 0, 1, 65);
1905
1906 if (old_afe_ovr)
1907 lpphy_set_tx_gains(dev, oldgains);
1908 lpphy_set_bb_mult(dev, old_bbmult);
1909 lpphy_set_tx_power_control(dev, old_txpctl);
1910 b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00, old_rf);
1911}
1912
1913static int lpphy_rx_iq_cal(struct b43_wldev *dev, bool noise, bool tx,
1914 bool rx, bool pa, struct lpphy_tx_gains *gains)
1915{
1916 struct b43_phy_lp *lpphy = dev->phy.lp;
1917 struct ssb_bus *bus = dev->dev->bus;
1918 const struct lpphy_rx_iq_comp *iqcomp = NULL;
1919 struct lpphy_tx_gains nogains, oldgains;
1920 u16 tmp;
1921 int i, ret;
1922
1923 memset(&nogains, 0, sizeof(nogains));
1924 memset(&oldgains, 0, sizeof(oldgains));
1925
1926 if (bus->chip_id == 0x5354) {
1927 for (i = 0; i < ARRAY_SIZE(lpphy_5354_iq_table); i++) {
1928 if (lpphy_5354_iq_table[i].chan == lpphy->channel) {
1929 iqcomp = &lpphy_5354_iq_table[i];
1930 }
1931 }
1932 } else if (dev->phy.rev >= 2) {
1933 iqcomp = &lpphy_rev2plus_iq_comp;
1934 } else {
1935 for (i = 0; i < ARRAY_SIZE(lpphy_rev0_1_iq_table); i++) {
1936 if (lpphy_rev0_1_iq_table[i].chan == lpphy->channel) {
1937 iqcomp = &lpphy_rev0_1_iq_table[i];
1938 }
1939 }
1940 }
1941
1942 if (B43_WARN_ON(!iqcomp))
1943 return 0;
1944
1945 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, iqcomp->c1);
1946 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S,
1947 0x00FF, iqcomp->c0 << 8);
1948
1949 if (noise) {
1950 tx = true;
1951 rx = false;
1952 pa = false;
1953 }
1954
1955 lpphy_set_trsw_over(dev, tx, rx);
1956
1957 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1958 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
1959 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0,
1960 0xFFF7, pa << 3);
1961 } else {
1962 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
1963 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0,
1964 0xFFDF, pa << 5);
1965 }
1966
1967 tmp = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40;
1968
1969 if (noise)
1970 lpphy_set_rx_gain(dev, 0x2D5D);
1971 else {
1972 if (tmp)
1973 oldgains = lpphy_get_tx_gains(dev);
1974 if (!gains)
1975 gains = &nogains;
1976 lpphy_set_tx_gains(dev, *gains);
1977 }
1978
1979 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
1980 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
1981 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
1982 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
1983 lpphy_set_deaf(dev, false);
1984 if (noise)
1985 ret = lpphy_calc_rx_iq_comp(dev, 0xFFF0);
1986 else {
1987 lpphy_start_tx_tone(dev, 4000, 100);
1988 ret = lpphy_calc_rx_iq_comp(dev, 0x4000);
1989 lpphy_stop_tx_tone(dev);
1990 }
1991 lpphy_clear_deaf(dev, false);
1992 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFC);
1993 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
1994 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFDF);
1995 if (!noise) {
1996 if (tmp)
1997 lpphy_set_tx_gains(dev, oldgains);
1998 else
1999 lpphy_disable_tx_gain_override(dev);
2000 }
2001 lpphy_disable_rx_gain_override(dev);
2002 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
2003 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xF7FF);
2004 return ret;
2005}
2006
2007static void lpphy_calibration(struct b43_wldev *dev)
2008{
2009 struct b43_phy_lp *lpphy = dev->phy.lp;
2010 enum b43_lpphy_txpctl_mode saved_pctl_mode;
2011 bool full_cal = false;
2012
2013 if (lpphy->full_calib_chan != lpphy->channel) {
2014 full_cal = true;
2015 lpphy->full_calib_chan = lpphy->channel;
2016 }
2017
2018 b43_mac_suspend(dev);
2019
2020 lpphy_btcoex_override(dev);
2021 if (dev->phy.rev >= 2)
2022 lpphy_save_dig_flt_state(dev);
2023 lpphy_read_tx_pctl_mode_from_hardware(dev);
2024 saved_pctl_mode = lpphy->txpctl_mode;
2025 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
2026 //TODO Perform transmit power table I/Q LO calibration
2027 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
2028 lpphy_pr41573_workaround(dev);
2029 if ((dev->phy.rev >= 2) && full_cal) {
2030 lpphy_papd_cal_txpwr(dev);
2031 }
2032 lpphy_set_tx_power_control(dev, saved_pctl_mode);
2033 if (dev->phy.rev >= 2)
2034 lpphy_restore_dig_flt_state(dev);
2035 lpphy_rx_iq_cal(dev, true, true, false, false, NULL);
2036
2037 b43_mac_enable(dev);
2038}
2039
1498static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg) 2040static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1499{ 2041{
1500 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); 2042 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
@@ -1539,12 +2081,6 @@ static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1539 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); 2081 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1540} 2082}
1541 2083
1542static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
1543 bool blocked)
1544{
1545 //TODO
1546}
1547
1548struct b206x_channel { 2084struct b206x_channel {
1549 u8 channel; 2085 u8 channel;
1550 u16 freq; 2086 u16 freq;
@@ -2010,22 +2546,6 @@ static int lpphy_b2062_tune(struct b43_wldev *dev,
2010 return err; 2546 return err;
2011} 2547}
2012 2548
2013
2014/* This was previously called lpphy_japan_filter */
2015static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
2016{
2017 struct b43_phy_lp *lpphy = dev->phy.lp;
2018 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
2019
2020 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
2021 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
2022 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
2023 lpphy_set_rc_cap(dev);
2024 } else {
2025 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
2026 }
2027}
2028
2029static void lpphy_b2063_vco_calib(struct b43_wldev *dev) 2549static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
2030{ 2550{
2031 u16 tmp; 2551 u16 tmp;
@@ -2210,18 +2730,6 @@ static int b43_lpphy_op_init(struct b43_wldev *dev)
2210 return 0; 2730 return 0;
2211} 2731}
2212 2732
2213static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2214{
2215 if (dev->phy.rev >= 2)
2216 return; // rev2+ doesn't support antenna diversity
2217
2218 if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1))
2219 return;
2220
2221 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2);
2222 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1);
2223}
2224
2225static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev) 2733static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
2226{ 2734{
2227 //TODO 2735 //TODO
@@ -2244,6 +2752,11 @@ void b43_lpphy_op_switch_analog(struct b43_wldev *dev, bool on)
2244 } 2752 }
2245} 2753}
2246 2754
2755static void b43_lpphy_op_pwork_15sec(struct b43_wldev *dev)
2756{
2757 //TODO
2758}
2759
2247const struct b43_phy_operations b43_phyops_lp = { 2760const struct b43_phy_operations b43_phyops_lp = {
2248 .allocate = b43_lpphy_op_allocate, 2761 .allocate = b43_lpphy_op_allocate,
2249 .free = b43_lpphy_op_free, 2762 .free = b43_lpphy_op_free,
@@ -2261,4 +2774,6 @@ const struct b43_phy_operations b43_phyops_lp = {
2261 .set_rx_antenna = b43_lpphy_op_set_rx_antenna, 2774 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
2262 .recalc_txpower = b43_lpphy_op_recalc_txpower, 2775 .recalc_txpower = b43_lpphy_op_recalc_txpower,
2263 .adjust_txpower = b43_lpphy_op_adjust_txpower, 2776 .adjust_txpower = b43_lpphy_op_adjust_txpower,
2777 .pwork_15sec = b43_lpphy_op_pwork_15sec,
2778 .pwork_60sec = lpphy_calibration,
2264}; 2779};
diff --git a/drivers/net/wireless/b43/phy_lp.h b/drivers/net/wireless/b43/phy_lp.h
index c3232c17b60a..62737f700cbc 100644
--- a/drivers/net/wireless/b43/phy_lp.h
+++ b/drivers/net/wireless/b43/phy_lp.h
@@ -286,6 +286,7 @@
286#define B43_LPPHY_TR_LOOKUP_6 B43_PHY_OFDM(0xC8) /* TR Lookup 6 */ 286#define B43_LPPHY_TR_LOOKUP_6 B43_PHY_OFDM(0xC8) /* TR Lookup 6 */
287#define B43_LPPHY_TR_LOOKUP_7 B43_PHY_OFDM(0xC9) /* TR Lookup 7 */ 287#define B43_LPPHY_TR_LOOKUP_7 B43_PHY_OFDM(0xC9) /* TR Lookup 7 */
288#define B43_LPPHY_TR_LOOKUP_8 B43_PHY_OFDM(0xCA) /* TR Lookup 8 */ 288#define B43_LPPHY_TR_LOOKUP_8 B43_PHY_OFDM(0xCA) /* TR Lookup 8 */
289#define B43_LPPHY_RF_PWR_OVERRIDE B43_PHY_OFDM(0xD3) /* RF power override */
289 290
290 291
291 292
@@ -871,12 +872,12 @@ struct b43_phy_lp {
871 u8 rssi_gs; 872 u8 rssi_gs;
872 873
873 /* RC cap */ 874 /* RC cap */
874 u8 rc_cap; /* FIXME initial value? */ 875 u8 rc_cap;
875 /* BX arch */ 876 /* BX arch */
876 u8 bx_arch; 877 u8 bx_arch;
877 878
878 /* Full calibration channel */ 879 /* Full calibration channel */
879 u8 full_calib_chan; /* FIXME initial value? */ 880 u8 full_calib_chan;
880 881
881 /* Transmit iqlocal best coeffs */ 882 /* Transmit iqlocal best coeffs */
882 bool tx_iqloc_best_coeffs_valid; 883 bool tx_iqloc_best_coeffs_valid;
@@ -891,6 +892,12 @@ struct b43_phy_lp {
891 892
892 /* The channel we are tuned to */ 893 /* The channel we are tuned to */
893 u8 channel; 894 u8 channel;
895
896 /* The active antenna diversity mode */
897 int antenna;
898
899 /* Frequency of the active TX tone */
900 int tx_tone_freq;
894}; 901};
895 902
896enum tssi_mux_mode { 903enum tssi_mux_mode {
diff --git a/drivers/net/wireless/b43/xmit.c b/drivers/net/wireless/b43/xmit.c
index 7a5e294be2bc..eda06529ef5f 100644
--- a/drivers/net/wireless/b43/xmit.c
+++ b/drivers/net/wireless/b43/xmit.c
@@ -621,7 +621,6 @@ void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr)
621 (phystat0 & B43_RX_PHYST0_OFDM), 621 (phystat0 & B43_RX_PHYST0_OFDM),
622 (phystat0 & B43_RX_PHYST0_GAINCTL), 622 (phystat0 & B43_RX_PHYST0_GAINCTL),
623 (phystat3 & B43_RX_PHYST3_TRSTATE)); 623 (phystat3 & B43_RX_PHYST3_TRSTATE));
624 status.qual = (rxhdr->jssi * 100) / B43_RX_MAX_SSI;
625 } 624 }
626 625
627 if (phystat0 & B43_RX_PHYST0_OFDM) 626 if (phystat0 & B43_RX_PHYST0_OFDM)
diff --git a/drivers/net/wireless/b43legacy/Kconfig b/drivers/net/wireless/b43legacy/Kconfig
index 94a463478053..1ffa28835c58 100644
--- a/drivers/net/wireless/b43legacy/Kconfig
+++ b/drivers/net/wireless/b43legacy/Kconfig
@@ -1,6 +1,6 @@
1config B43LEGACY 1config B43LEGACY
2 tristate "Broadcom 43xx-legacy wireless support (mac80211 stack)" 2 tristate "Broadcom 43xx-legacy wireless support (mac80211 stack)"
3 depends on SSB_POSSIBLE && MAC80211 && WLAN_80211 && HAS_DMA 3 depends on SSB_POSSIBLE && MAC80211 && HAS_DMA
4 select SSB 4 select SSB
5 select FW_LOADER 5 select FW_LOADER
6 ---help--- 6 ---help---
diff --git a/drivers/net/wireless/b43legacy/b43legacy.h b/drivers/net/wireless/b43legacy/b43legacy.h
index 038baa8869e2..89fe2f972c72 100644
--- a/drivers/net/wireless/b43legacy/b43legacy.h
+++ b/drivers/net/wireless/b43legacy/b43legacy.h
@@ -29,8 +29,6 @@
29 29
30#define B43legacy_IRQWAIT_MAX_RETRIES 20 30#define B43legacy_IRQWAIT_MAX_RETRIES 20
31 31
32#define B43legacy_RX_MAX_SSI 60 /* best guess at max ssi */
33
34/* MMIO offsets */ 32/* MMIO offsets */
35#define B43legacy_MMIO_DMA0_REASON 0x20 33#define B43legacy_MMIO_DMA0_REASON 0x20
36#define B43legacy_MMIO_DMA0_IRQ_MASK 0x24 34#define B43legacy_MMIO_DMA0_IRQ_MASK 0x24
diff --git a/drivers/net/wireless/b43legacy/dma.c b/drivers/net/wireless/b43legacy/dma.c
index 866403415811..0a86bdf53154 100644
--- a/drivers/net/wireless/b43legacy/dma.c
+++ b/drivers/net/wireless/b43legacy/dma.c
@@ -1240,8 +1240,9 @@ struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev,
1240} 1240}
1241 1241
1242static int dma_tx_fragment(struct b43legacy_dmaring *ring, 1242static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1243 struct sk_buff *skb) 1243 struct sk_buff **in_skb)
1244{ 1244{
1245 struct sk_buff *skb = *in_skb;
1245 const struct b43legacy_dma_ops *ops = ring->ops; 1246 const struct b43legacy_dma_ops *ops = ring->ops;
1246 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1247 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1247 u8 *header; 1248 u8 *header;
@@ -1305,8 +1306,14 @@ static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1305 } 1306 }
1306 1307
1307 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len); 1308 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1309 memcpy(bounce_skb->cb, skb->cb, sizeof(skb->cb));
1310 bounce_skb->dev = skb->dev;
1311 skb_set_queue_mapping(bounce_skb, skb_get_queue_mapping(skb));
1312 info = IEEE80211_SKB_CB(bounce_skb);
1313
1308 dev_kfree_skb_any(skb); 1314 dev_kfree_skb_any(skb);
1309 skb = bounce_skb; 1315 skb = bounce_skb;
1316 *in_skb = bounce_skb;
1310 meta->skb = skb; 1317 meta->skb = skb;
1311 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); 1318 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1312 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) { 1319 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
@@ -1360,8 +1367,10 @@ int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1360 struct sk_buff *skb) 1367 struct sk_buff *skb)
1361{ 1368{
1362 struct b43legacy_dmaring *ring; 1369 struct b43legacy_dmaring *ring;
1370 struct ieee80211_hdr *hdr;
1363 int err = 0; 1371 int err = 0;
1364 unsigned long flags; 1372 unsigned long flags;
1373 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1365 1374
1366 ring = priority_to_txring(dev, skb_get_queue_mapping(skb)); 1375 ring = priority_to_txring(dev, skb_get_queue_mapping(skb));
1367 spin_lock_irqsave(&ring->lock, flags); 1376 spin_lock_irqsave(&ring->lock, flags);
@@ -1386,7 +1395,11 @@ int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1386 goto out_unlock; 1395 goto out_unlock;
1387 } 1396 }
1388 1397
1389 err = dma_tx_fragment(ring, skb); 1398 /* dma_tx_fragment might reallocate the skb, so invalidate pointers pointing
1399 * into the skb data or cb now. */
1400 hdr = NULL;
1401 info = NULL;
1402 err = dma_tx_fragment(ring, &skb);
1390 if (unlikely(err == -ENOKEY)) { 1403 if (unlikely(err == -ENOKEY)) {
1391 /* Drop this packet, as we don't have the encryption key 1404 /* Drop this packet, as we don't have the encryption key
1392 * anymore and must not transmit it unencrypted. */ 1405 * anymore and must not transmit it unencrypted. */
diff --git a/drivers/net/wireless/b43legacy/main.c b/drivers/net/wireless/b43legacy/main.c
index 0983406f4630..d579bb9035c4 100644
--- a/drivers/net/wireless/b43legacy/main.c
+++ b/drivers/net/wireless/b43legacy/main.c
@@ -2676,7 +2676,7 @@ static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2676 if (conf->channel->hw_value != phy->channel) 2676 if (conf->channel->hw_value != phy->channel)
2677 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0); 2677 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
2678 2678
2679 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP); 2679 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
2680 2680
2681 /* Adjust the desired TX power level. */ 2681 /* Adjust the desired TX power level. */
2682 if (conf->power_level != 0) { 2682 if (conf->power_level != 0) {
diff --git a/drivers/net/wireless/b43legacy/xmit.c b/drivers/net/wireless/b43legacy/xmit.c
index 103f3c9e7f58..9c8882d9275e 100644
--- a/drivers/net/wireless/b43legacy/xmit.c
+++ b/drivers/net/wireless/b43legacy/xmit.c
@@ -549,7 +549,6 @@ void b43legacy_rx(struct b43legacy_wldev *dev,
549 (phystat0 & B43legacy_RX_PHYST0_GAINCTL), 549 (phystat0 & B43legacy_RX_PHYST0_GAINCTL),
550 (phystat3 & B43legacy_RX_PHYST3_TRSTATE)); 550 (phystat3 & B43legacy_RX_PHYST3_TRSTATE));
551 status.noise = dev->stats.link_noise; 551 status.noise = dev->stats.link_noise;
552 status.qual = (jssi * 100) / B43legacy_RX_MAX_SSI;
553 /* change to support A PHY */ 552 /* change to support A PHY */
554 if (phystat0 & B43legacy_RX_PHYST0_OFDM) 553 if (phystat0 & B43legacy_RX_PHYST0_OFDM)
555 status.rate_idx = b43legacy_plcp_get_bitrate_idx_ofdm(plcp, false); 554 status.rate_idx = b43legacy_plcp_get_bitrate_idx_ofdm(plcp, false);
diff --git a/drivers/net/wireless/hostap/Kconfig b/drivers/net/wireless/hostap/Kconfig
index 08f1e989653d..287d82728bc3 100644
--- a/drivers/net/wireless/hostap/Kconfig
+++ b/drivers/net/wireless/hostap/Kconfig
@@ -1,6 +1,5 @@
1config HOSTAP 1config HOSTAP
2 tristate "IEEE 802.11 for Host AP (Prism2/2.5/3 and WEP/TKIP/CCMP)" 2 tristate "IEEE 802.11 for Host AP (Prism2/2.5/3 and WEP/TKIP/CCMP)"
3 depends on WLAN_80211
4 select WIRELESS_EXT 3 select WIRELESS_EXT
5 select WEXT_SPY 4 select WEXT_SPY
6 select WEXT_PRIV 5 select WEXT_PRIV
diff --git a/drivers/net/wireless/i82586.h b/drivers/net/wireless/i82586.h
deleted file mode 100644
index 5f65b250646f..000000000000
--- a/drivers/net/wireless/i82586.h
+++ /dev/null
@@ -1,413 +0,0 @@
1/*
2 * Intel 82586 IEEE 802.3 Ethernet LAN Coprocessor.
3 *
4 * See:
5 * Intel Microcommunications 1991
6 * p1-1 to p1-37
7 * Intel order No. 231658
8 * ISBN 1-55512-119-5
9 *
10 * Unfortunately, the above chapter mentions neither
11 * the System Configuration Pointer (SCP) nor the
12 * Intermediate System Configuration Pointer (ISCP),
13 * so we probably need to look elsewhere for the
14 * whole story -- some recommend the "Intel LAN
15 * Components manual" but I have neither a copy
16 * nor a full reference. But "elsewhere" may be
17 * in the same publication...
18 * The description of a later device, the
19 * "82596CA High-Performance 32-Bit Local Area Network
20 * Coprocessor", (ibid. p1-38 to p1-109) does mention
21 * the SCP and ISCP and also has an i82586 compatibility
22 * mode. Even more useful is "AP-235 An 82586 Data Link
23 * Driver" (ibid. p1-337 to p1-417).
24 */
25
26#define I82586_MEMZ (64 * 1024)
27
28#define I82586_SCP_ADDR (I82586_MEMZ - sizeof(scp_t))
29
30#define ADDR_LEN 6
31#define I82586NULL 0xFFFF
32
33#define toff(t,p,f) (unsigned short)((void *)(&((t *)((void *)0 + (p)))->f) - (void *)0)
34
35/*
36 * System Configuration Pointer (SCP).
37 */
38typedef struct scp_t scp_t;
39struct scp_t
40{
41 unsigned short scp_sysbus; /* 82586 bus width: */
42#define SCP_SY_16BBUS (0x0 << 0) /* 16 bits */
43#define SCP_SY_8BBUS (0x1 << 0) /* 8 bits. */
44 unsigned short scp_junk[2]; /* Unused */
45 unsigned short scp_iscpl; /* lower 16 bits of ISCP_ADDR */
46 unsigned short scp_iscph; /* upper 16 bits of ISCP_ADDR */
47};
48
49/*
50 * Intermediate System Configuration Pointer (ISCP).
51 */
52typedef struct iscp_t iscp_t;
53struct iscp_t
54{
55 unsigned short iscp_busy; /* set by CPU before first CA, */
56 /* cleared by 82586 after read. */
57 unsigned short iscp_offset; /* offset of SCB */
58 unsigned short iscp_basel; /* base of SCB */
59 unsigned short iscp_baseh; /* " */
60};
61
62/*
63 * System Control Block (SCB).
64 * The 82586 writes its status to scb_status and then
65 * raises an interrupt to alert the CPU.
66 * The CPU writes a command to scb_command and
67 * then issues a Channel Attention (CA) to alert the 82586.
68 */
69typedef struct scb_t scb_t;
70struct scb_t
71{
72 unsigned short scb_status; /* Status of 82586 */
73#define SCB_ST_INT (0xF << 12) /* Some of: */
74#define SCB_ST_CX (0x1 << 15) /* Cmd completed */
75#define SCB_ST_FR (0x1 << 14) /* Frame received */
76#define SCB_ST_CNA (0x1 << 13) /* Cmd unit not active */
77#define SCB_ST_RNR (0x1 << 12) /* Rcv unit not ready */
78#define SCB_ST_JUNK0 (0x1 << 11) /* 0 */
79#define SCB_ST_CUS (0x7 << 8) /* Cmd unit status */
80#define SCB_ST_CUS_IDLE (0 << 8) /* Idle */
81#define SCB_ST_CUS_SUSP (1 << 8) /* Suspended */
82#define SCB_ST_CUS_ACTV (2 << 8) /* Active */
83#define SCB_ST_JUNK1 (0x1 << 7) /* 0 */
84#define SCB_ST_RUS (0x7 << 4) /* Rcv unit status */
85#define SCB_ST_RUS_IDLE (0 << 4) /* Idle */
86#define SCB_ST_RUS_SUSP (1 << 4) /* Suspended */
87#define SCB_ST_RUS_NRES (2 << 4) /* No resources */
88#define SCB_ST_RUS_RDY (4 << 4) /* Ready */
89 unsigned short scb_command; /* Next command */
90#define SCB_CMD_ACK_CX (0x1 << 15) /* Ack cmd completion */
91#define SCB_CMD_ACK_FR (0x1 << 14) /* Ack frame received */
92#define SCB_CMD_ACK_CNA (0x1 << 13) /* Ack CU not active */
93#define SCB_CMD_ACK_RNR (0x1 << 12) /* Ack RU not ready */
94#define SCB_CMD_JUNKX (0x1 << 11) /* Unused */
95#define SCB_CMD_CUC (0x7 << 8) /* Command Unit command */
96#define SCB_CMD_CUC_NOP (0 << 8) /* Nop */
97#define SCB_CMD_CUC_GO (1 << 8) /* Start cbl_offset */
98#define SCB_CMD_CUC_RES (2 << 8) /* Resume execution */
99#define SCB_CMD_CUC_SUS (3 << 8) /* Suspend " */
100#define SCB_CMD_CUC_ABT (4 << 8) /* Abort " */
101#define SCB_CMD_RESET (0x1 << 7) /* Reset chip (hardware) */
102#define SCB_CMD_RUC (0x7 << 4) /* Receive Unit command */
103#define SCB_CMD_RUC_NOP (0 << 4) /* Nop */
104#define SCB_CMD_RUC_GO (1 << 4) /* Start rfa_offset */
105#define SCB_CMD_RUC_RES (2 << 4) /* Resume reception */
106#define SCB_CMD_RUC_SUS (3 << 4) /* Suspend " */
107#define SCB_CMD_RUC_ABT (4 << 4) /* Abort " */
108 unsigned short scb_cbl_offset; /* Offset of first command unit */
109 /* Action Command */
110 unsigned short scb_rfa_offset; /* Offset of first Receive */
111 /* Frame Descriptor in the */
112 /* Receive Frame Area */
113 unsigned short scb_crcerrs; /* Properly aligned frames */
114 /* received with a CRC error */
115 unsigned short scb_alnerrs; /* Misaligned frames received */
116 /* with a CRC error */
117 unsigned short scb_rscerrs; /* Frames lost due to no space */
118 unsigned short scb_ovrnerrs; /* Frames lost due to slow bus */
119};
120
121#define scboff(p,f) toff(scb_t, p, f)
122
123/*
124 * The eight Action Commands.
125 */
126typedef enum acmd_e acmd_e;
127enum acmd_e
128{
129 acmd_nop = 0, /* Do nothing */
130 acmd_ia_setup = 1, /* Load an (ethernet) address into the */
131 /* 82586 */
132 acmd_configure = 2, /* Update the 82586 operating parameters */
133 acmd_mc_setup = 3, /* Load a list of (ethernet) multicast */
134 /* addresses into the 82586 */
135 acmd_transmit = 4, /* Transmit a frame */
136 acmd_tdr = 5, /* Perform a Time Domain Reflectometer */
137 /* test on the serial link */
138 acmd_dump = 6, /* Copy 82586 registers to memory */
139 acmd_diagnose = 7, /* Run an internal self test */
140};
141
142/*
143 * Generic Action Command header.
144 */
145typedef struct ach_t ach_t;
146struct ach_t
147{
148 unsigned short ac_status; /* Command status: */
149#define AC_SFLD_C (0x1 << 15) /* Command completed */
150#define AC_SFLD_B (0x1 << 14) /* Busy executing */
151#define AC_SFLD_OK (0x1 << 13) /* Completed error free */
152#define AC_SFLD_A (0x1 << 12) /* Command aborted */
153#define AC_SFLD_FAIL (0x1 << 11) /* Selftest failed */
154#define AC_SFLD_S10 (0x1 << 10) /* No carrier sense */
155 /* during transmission */
156#define AC_SFLD_S9 (0x1 << 9) /* Tx unsuccessful: */
157 /* (stopped) lost CTS */
158#define AC_SFLD_S8 (0x1 << 8) /* Tx unsuccessful: */
159 /* (stopped) slow DMA */
160#define AC_SFLD_S7 (0x1 << 7) /* Tx deferred: */
161 /* other link traffic */
162#define AC_SFLD_S6 (0x1 << 6) /* Heart Beat: collision */
163 /* detect after last tx */
164#define AC_SFLD_S5 (0x1 << 5) /* Tx stopped: */
165 /* excessive collisions */
166#define AC_SFLD_MAXCOL (0xF << 0) /* Collision count */
167 unsigned short ac_command; /* Command specifier: */
168#define AC_CFLD_EL (0x1 << 15) /* End of command list */
169#define AC_CFLD_S (0x1 << 14) /* Suspend on completion */
170#define AC_CFLD_I (0x1 << 13) /* Interrupt on completion */
171#define AC_CFLD_CMD (0x7 << 0) /* acmd_e */
172 unsigned short ac_link; /* Next Action Command */
173};
174
175#define acoff(p,f) toff(ach_t, p, f)
176
177/*
178 * The Nop Action Command.
179 */
180typedef struct ac_nop_t ac_nop_t;
181struct ac_nop_t
182{
183 ach_t nop_h;
184};
185
186/*
187 * The IA-Setup Action Command.
188 */
189typedef struct ac_ias_t ac_ias_t;
190struct ac_ias_t
191{
192 ach_t ias_h;
193 unsigned char ias_addr[ADDR_LEN]; /* The (ethernet) address */
194};
195
196/*
197 * The Configure Action Command.
198 */
199typedef struct ac_cfg_t ac_cfg_t;
200struct ac_cfg_t
201{
202 ach_t cfg_h;
203 unsigned char cfg_byte_cnt; /* Size foll data: 4-12 */
204#define AC_CFG_BYTE_CNT(v) (((v) & 0xF) << 0)
205 unsigned char cfg_fifolim; /* FIFO threshold */
206#define AC_CFG_FIFOLIM(v) (((v) & 0xF) << 0)
207 unsigned char cfg_byte8;
208#define AC_CFG_SAV_BF(v) (((v) & 0x1) << 7) /* Save rxd bad frames */
209#define AC_CFG_SRDY(v) (((v) & 0x1) << 6) /* SRDY/ARDY pin means */
210 /* external sync. */
211 unsigned char cfg_byte9;
212#define AC_CFG_ELPBCK(v) (((v) & 0x1) << 7) /* External loopback */
213#define AC_CFG_ILPBCK(v) (((v) & 0x1) << 6) /* Internal loopback */
214#define AC_CFG_PRELEN(v) (((v) & 0x3) << 4) /* Preamble length */
215#define AC_CFG_PLEN_2 0 /* 2 bytes */
216#define AC_CFG_PLEN_4 1 /* 4 bytes */
217#define AC_CFG_PLEN_8 2 /* 8 bytes */
218#define AC_CFG_PLEN_16 3 /* 16 bytes */
219#define AC_CFG_ALOC(v) (((v) & 0x1) << 3) /* Addr/len data is */
220 /* explicit in buffers */
221#define AC_CFG_ADDRLEN(v) (((v) & 0x7) << 0) /* Bytes per address */
222 unsigned char cfg_byte10;
223#define AC_CFG_BOFMET(v) (((v) & 0x1) << 7) /* Use alternate expo. */
224 /* backoff method */
225#define AC_CFG_ACR(v) (((v) & 0x7) << 4) /* Accelerated cont. res. */
226#define AC_CFG_LINPRIO(v) (((v) & 0x7) << 0) /* Linear priority */
227 unsigned char cfg_ifs; /* Interframe spacing */
228 unsigned char cfg_slotl; /* Slot time (low byte) */
229 unsigned char cfg_byte13;
230#define AC_CFG_RETRYNUM(v) (((v) & 0xF) << 4) /* Max. collision retry */
231#define AC_CFG_SLTTMHI(v) (((v) & 0x7) << 0) /* Slot time (high bits) */
232 unsigned char cfg_byte14;
233#define AC_CFG_FLGPAD(v) (((v) & 0x1) << 7) /* Pad with HDLC flags */
234#define AC_CFG_BTSTF(v) (((v) & 0x1) << 6) /* Do HDLC bitstuffing */
235#define AC_CFG_CRC16(v) (((v) & 0x1) << 5) /* 16 bit CCITT CRC */
236#define AC_CFG_NCRC(v) (((v) & 0x1) << 4) /* Insert no CRC */
237#define AC_CFG_TNCRS(v) (((v) & 0x1) << 3) /* Tx even if no carrier */
238#define AC_CFG_MANCH(v) (((v) & 0x1) << 2) /* Manchester coding */
239#define AC_CFG_BCDIS(v) (((v) & 0x1) << 1) /* Disable broadcast */
240#define AC_CFG_PRM(v) (((v) & 0x1) << 0) /* Promiscuous mode */
241 unsigned char cfg_byte15;
242#define AC_CFG_ICDS(v) (((v) & 0x1) << 7) /* Internal collision */
243 /* detect source */
244#define AC_CFG_CDTF(v) (((v) & 0x7) << 4) /* Collision detect */
245 /* filter in bit times */
246#define AC_CFG_ICSS(v) (((v) & 0x1) << 3) /* Internal carrier */
247 /* sense source */
248#define AC_CFG_CSTF(v) (((v) & 0x7) << 0) /* Carrier sense */
249 /* filter in bit times */
250 unsigned short cfg_min_frm_len;
251#define AC_CFG_MNFRM(v) (((v) & 0xFF) << 0) /* Min. bytes/frame (<= 255) */
252};
253
254/*
255 * The MC-Setup Action Command.
256 */
257typedef struct ac_mcs_t ac_mcs_t;
258struct ac_mcs_t
259{
260 ach_t mcs_h;
261 unsigned short mcs_cnt; /* No. of bytes of MC addresses */
262#if 0
263 unsigned char mcs_data[ADDR_LEN]; /* The first MC address .. */
264 ...
265#endif
266};
267
268#define I82586_MAX_MULTICAST_ADDRESSES 128 /* Hardware hashed filter */
269
270/*
271 * The Transmit Action Command.
272 */
273typedef struct ac_tx_t ac_tx_t;
274struct ac_tx_t
275{
276 ach_t tx_h;
277 unsigned short tx_tbd_offset; /* Address of list of buffers. */
278#if 0
279Linux packets are passed down with the destination MAC address
280and length/type field already prepended to the data,
281so we do not need to insert it. Consistent with this
282we must also set the AC_CFG_ALOC(..) flag during the
283ac_cfg_t action command.
284 unsigned char tx_addr[ADDR_LEN]; /* The frame dest. address */
285 unsigned short tx_length; /* The frame length */
286#endif /* 0 */
287};
288
289/*
290 * The Time Domain Reflectometer Action Command.
291 */
292typedef struct ac_tdr_t ac_tdr_t;
293struct ac_tdr_t
294{
295 ach_t tdr_h;
296 unsigned short tdr_result; /* Result. */
297#define AC_TDR_LNK_OK (0x1 << 15) /* No link problem */
298#define AC_TDR_XCVR_PRB (0x1 << 14) /* Txcvr cable problem */
299#define AC_TDR_ET_OPN (0x1 << 13) /* Open on the link */
300#define AC_TDR_ET_SRT (0x1 << 12) /* Short on the link */
301#define AC_TDR_TIME (0x7FF << 0) /* Distance to problem */
302 /* site in transmit */
303 /* clock cycles */
304};
305
306/*
307 * The Dump Action Command.
308 */
309typedef struct ac_dmp_t ac_dmp_t;
310struct ac_dmp_t
311{
312 ach_t dmp_h;
313 unsigned short dmp_offset; /* Result. */
314};
315
316/*
317 * Size of the result of the dump command.
318 */
319#define DUMPBYTES 170
320
321/*
322 * The Diagnose Action Command.
323 */
324typedef struct ac_dgn_t ac_dgn_t;
325struct ac_dgn_t
326{
327 ach_t dgn_h;
328};
329
330/*
331 * Transmit Buffer Descriptor (TBD).
332 */
333typedef struct tbd_t tbd_t;
334struct tbd_t
335{
336 unsigned short tbd_status; /* Written by the CPU */
337#define TBD_STATUS_EOF (0x1 << 15) /* This TBD is the */
338 /* last for this frame */
339#define TBD_STATUS_ACNT (0x3FFF << 0) /* Actual count of data */
340 /* bytes in this buffer */
341 unsigned short tbd_next_bd_offset; /* Next in list */
342 unsigned short tbd_bufl; /* Buffer address (low) */
343 unsigned short tbd_bufh; /* " " (high) */
344};
345
346/*
347 * Receive Buffer Descriptor (RBD).
348 */
349typedef struct rbd_t rbd_t;
350struct rbd_t
351{
352 unsigned short rbd_status; /* Written by the 82586 */
353#define RBD_STATUS_EOF (0x1 << 15) /* This RBD is the */
354 /* last for this frame */
355#define RBD_STATUS_F (0x1 << 14) /* ACNT field is valid */
356#define RBD_STATUS_ACNT (0x3FFF << 0) /* Actual no. of data */
357 /* bytes in this buffer */
358 unsigned short rbd_next_rbd_offset; /* Next rbd in list */
359 unsigned short rbd_bufl; /* Data pointer (low) */
360 unsigned short rbd_bufh; /* " " (high) */
361 unsigned short rbd_el_size; /* EL+Data buf. size */
362#define RBD_EL (0x1 << 15) /* This BD is the */
363 /* last in the list */
364#define RBD_SIZE (0x3FFF << 0) /* No. of bytes the */
365 /* buffer can hold */
366};
367
368#define rbdoff(p,f) toff(rbd_t, p, f)
369
370/*
371 * Frame Descriptor (FD).
372 */
373typedef struct fd_t fd_t;
374struct fd_t
375{
376 unsigned short fd_status; /* Written by the 82586 */
377#define FD_STATUS_C (0x1 << 15) /* Completed storing frame */
378#define FD_STATUS_B (0x1 << 14) /* FD was consumed by RU */
379#define FD_STATUS_OK (0x1 << 13) /* Frame rxd successfully */
380#define FD_STATUS_S11 (0x1 << 11) /* CRC error */
381#define FD_STATUS_S10 (0x1 << 10) /* Alignment error */
382#define FD_STATUS_S9 (0x1 << 9) /* Ran out of resources */
383#define FD_STATUS_S8 (0x1 << 8) /* Rx DMA overrun */
384#define FD_STATUS_S7 (0x1 << 7) /* Frame too short */
385#define FD_STATUS_S6 (0x1 << 6) /* No EOF flag */
386 unsigned short fd_command; /* Command */
387#define FD_COMMAND_EL (0x1 << 15) /* Last FD in list */
388#define FD_COMMAND_S (0x1 << 14) /* Suspend RU after rx */
389 unsigned short fd_link_offset; /* Next FD */
390 unsigned short fd_rbd_offset; /* First RBD (data) */
391 /* Prepared by CPU, */
392 /* updated by 82586 */
393#if 0
394I think the rest is unused since we
395have set AC_CFG_ALOC(..). However, just
396in case, we leave the space.
397#endif /* 0 */
398 unsigned char fd_dest[ADDR_LEN]; /* Destination address */
399 /* Written by 82586 */
400 unsigned char fd_src[ADDR_LEN]; /* Source address */
401 /* Written by 82586 */
402 unsigned short fd_length; /* Frame length or type */
403 /* Written by 82586 */
404};
405
406#define fdoff(p,f) toff(fd_t, p, f)
407
408/*
409 * This software may only be used and distributed
410 * according to the terms of the GNU General Public License.
411 *
412 * For more details, see wavelan.c.
413 */
diff --git a/drivers/net/wireless/i82593.h b/drivers/net/wireless/i82593.h
deleted file mode 100644
index afac5c7a323d..000000000000
--- a/drivers/net/wireless/i82593.h
+++ /dev/null
@@ -1,229 +0,0 @@
1/*
2 * Definitions for Intel 82593 CSMA/CD Core LAN Controller
3 * The definitions are taken from the 1992 users manual with Intel
4 * order number 297125-001.
5 *
6 * /usr/src/pc/RCS/i82593.h,v 1.1 1996/07/17 15:23:12 root Exp
7 *
8 * Copyright 1994, Anders Klemets <klemets@it.kth.se>
9 *
10 * HISTORY
11 * i82593.h,v
12 * Revision 1.4 2005/11/4 09:15:00 baroniunas
13 * Modified copyright with permission of author as follows:
14 *
15 * "If I82539.H is the only file with my copyright statement
16 * that is included in the Source Forge project, then you have
17 * my approval to change the copyright statement to be a GPL
18 * license, in the way you proposed on October 10."
19 *
20 * Revision 1.1 1996/07/17 15:23:12 root
21 * Initial revision
22 *
23 * Revision 1.3 1995/04/05 15:13:58 adj
24 * Initial alpha release
25 *
26 * Revision 1.2 1994/06/16 23:57:31 klemets
27 * Mirrored all the fields in the configuration block.
28 *
29 * Revision 1.1 1994/06/02 20:25:34 klemets
30 * Initial revision
31 *
32 *
33 */
34#ifndef _I82593_H
35#define _I82593_H
36
37/* Intel 82593 CSMA/CD Core LAN Controller */
38
39/* Port 0 Command Register definitions */
40
41/* Execution operations */
42#define OP0_NOP 0 /* CHNL = 0 */
43#define OP0_SWIT_TO_PORT_1 0 /* CHNL = 1 */
44#define OP0_IA_SETUP 1
45#define OP0_CONFIGURE 2
46#define OP0_MC_SETUP 3
47#define OP0_TRANSMIT 4
48#define OP0_TDR 5
49#define OP0_DUMP 6
50#define OP0_DIAGNOSE 7
51#define OP0_TRANSMIT_NO_CRC 9
52#define OP0_RETRANSMIT 12
53#define OP0_ABORT 13
54/* Reception operations */
55#define OP0_RCV_ENABLE 8
56#define OP0_RCV_DISABLE 10
57#define OP0_STOP_RCV 11
58/* Status pointer control operations */
59#define OP0_FIX_PTR 15 /* CHNL = 1 */
60#define OP0_RLS_PTR 15 /* CHNL = 0 */
61#define OP0_RESET 14
62
63#define CR0_CHNL (1 << 4) /* 0=Channel 0, 1=Channel 1 */
64#define CR0_STATUS_0 0x00
65#define CR0_STATUS_1 0x20
66#define CR0_STATUS_2 0x40
67#define CR0_STATUS_3 0x60
68#define CR0_INT_ACK (1 << 7) /* 0=No ack, 1=acknowledge */
69
70/* Port 0 Status Register definitions */
71
72#define SR0_NO_RESULT 0 /* dummy */
73#define SR0_EVENT_MASK 0x0f
74#define SR0_IA_SETUP_DONE 1
75#define SR0_CONFIGURE_DONE 2
76#define SR0_MC_SETUP_DONE 3
77#define SR0_TRANSMIT_DONE 4
78#define SR0_TDR_DONE 5
79#define SR0_DUMP_DONE 6
80#define SR0_DIAGNOSE_PASSED 7
81#define SR0_TRANSMIT_NO_CRC_DONE 9
82#define SR0_RETRANSMIT_DONE 12
83#define SR0_EXECUTION_ABORTED 13
84#define SR0_END_OF_FRAME 8
85#define SR0_RECEPTION_ABORTED 10
86#define SR0_DIAGNOSE_FAILED 15
87#define SR0_STOP_REG_HIT 11
88
89#define SR0_CHNL (1 << 4)
90#define SR0_EXECUTION (1 << 5)
91#define SR0_RECEPTION (1 << 6)
92#define SR0_INTERRUPT (1 << 7)
93#define SR0_BOTH_RX_TX (SR0_EXECUTION | SR0_RECEPTION)
94
95#define SR3_EXEC_STATE_MASK 0x03
96#define SR3_EXEC_IDLE 0
97#define SR3_TX_ABORT_IN_PROGRESS 1
98#define SR3_EXEC_ACTIVE 2
99#define SR3_ABORT_IN_PROGRESS 3
100#define SR3_EXEC_CHNL (1 << 2)
101#define SR3_STP_ON_NO_RSRC (1 << 3)
102#define SR3_RCVING_NO_RSRC (1 << 4)
103#define SR3_RCV_STATE_MASK 0x60
104#define SR3_RCV_IDLE 0x00
105#define SR3_RCV_READY 0x20
106#define SR3_RCV_ACTIVE 0x40
107#define SR3_RCV_STOP_IN_PROG 0x60
108#define SR3_RCV_CHNL (1 << 7)
109
110/* Port 1 Command Register definitions */
111
112#define OP1_NOP 0
113#define OP1_SWIT_TO_PORT_0 1
114#define OP1_INT_DISABLE 2
115#define OP1_INT_ENABLE 3
116#define OP1_SET_TS 5
117#define OP1_RST_TS 7
118#define OP1_POWER_DOWN 8
119#define OP1_RESET_RING_MNGMT 11
120#define OP1_RESET 14
121#define OP1_SEL_RST 15
122
123#define CR1_STATUS_4 0x00
124#define CR1_STATUS_5 0x20
125#define CR1_STATUS_6 0x40
126#define CR1_STOP_REG_UPDATE (1 << 7)
127
128/* Receive frame status bits */
129
130#define RX_RCLD (1 << 0)
131#define RX_IA_MATCH (1 << 1)
132#define RX_NO_AD_MATCH (1 << 2)
133#define RX_NO_SFD (1 << 3)
134#define RX_SRT_FRM (1 << 7)
135#define RX_OVRRUN (1 << 8)
136#define RX_ALG_ERR (1 << 10)
137#define RX_CRC_ERR (1 << 11)
138#define RX_LEN_ERR (1 << 12)
139#define RX_RCV_OK (1 << 13)
140#define RX_TYP_LEN (1 << 15)
141
142/* Transmit status bits */
143
144#define TX_NCOL_MASK 0x0f
145#define TX_FRTL (1 << 4)
146#define TX_MAX_COL (1 << 5)
147#define TX_HRT_BEAT (1 << 6)
148#define TX_DEFER (1 << 7)
149#define TX_UND_RUN (1 << 8)
150#define TX_LOST_CTS (1 << 9)
151#define TX_LOST_CRS (1 << 10)
152#define TX_LTCOL (1 << 11)
153#define TX_OK (1 << 13)
154#define TX_COLL (1 << 15)
155
156struct i82593_conf_block {
157 u_char fifo_limit : 4,
158 forgnesi : 1,
159 fifo_32 : 1,
160 d6mod : 1,
161 throttle_enb : 1;
162 u_char throttle : 6,
163 cntrxint : 1,
164 contin : 1;
165 u_char addr_len : 3,
166 acloc : 1,
167 preamb_len : 2,
168 loopback : 2;
169 u_char lin_prio : 3,
170 tbofstop : 1,
171 exp_prio : 3,
172 bof_met : 1;
173 u_char : 4,
174 ifrm_spc : 4;
175 u_char : 5,
176 slottim_low : 3;
177 u_char slottim_hi : 3,
178 : 1,
179 max_retr : 4;
180 u_char prmisc : 1,
181 bc_dis : 1,
182 : 1,
183 crs_1 : 1,
184 nocrc_ins : 1,
185 crc_1632 : 1,
186 : 1,
187 crs_cdt : 1;
188 u_char cs_filter : 3,
189 crs_src : 1,
190 cd_filter : 3,
191 : 1;
192 u_char : 2,
193 min_fr_len : 6;
194 u_char lng_typ : 1,
195 lng_fld : 1,
196 rxcrc_xf : 1,
197 artx : 1,
198 sarec : 1,
199 tx_jabber : 1, /* why is this called max_len in the manual? */
200 hash_1 : 1,
201 lbpkpol : 1;
202 u_char : 6,
203 fdx : 1,
204 : 1;
205 u_char dummy_6 : 6, /* supposed to be ones */
206 mult_ia : 1,
207 dis_bof : 1;
208 u_char dummy_1 : 1, /* supposed to be one */
209 tx_ifs_retrig : 2,
210 mc_all : 1,
211 rcv_mon : 2,
212 frag_acpt : 1,
213 tstrttrs : 1;
214 u_char fretx : 1,
215 runt_eop : 1,
216 hw_sw_pin : 1,
217 big_endn : 1,
218 syncrqs : 1,
219 sttlen : 1,
220 tx_eop : 1,
221 rx_eop : 1;
222 u_char rbuf_size : 5,
223 rcvstop : 1,
224 : 2;
225};
226
227#define I82593_MAX_MULTICAST_ADDRESSES 128 /* Hardware hashed filter */
228
229#endif /* _I82593_H */
diff --git a/drivers/net/wireless/ipw2x00/Kconfig b/drivers/net/wireless/ipw2x00/Kconfig
index 59ec9eec5024..2715b101aded 100644
--- a/drivers/net/wireless/ipw2x00/Kconfig
+++ b/drivers/net/wireless/ipw2x00/Kconfig
@@ -4,7 +4,7 @@
4 4
5config IPW2100 5config IPW2100
6 tristate "Intel PRO/Wireless 2100 Network Connection" 6 tristate "Intel PRO/Wireless 2100 Network Connection"
7 depends on PCI && WLAN_80211 && CFG80211 7 depends on PCI && CFG80211
8 select WIRELESS_EXT 8 select WIRELESS_EXT
9 select WEXT_SPY 9 select WEXT_SPY
10 select WEXT_PRIV 10 select WEXT_PRIV
@@ -65,7 +65,7 @@ config IPW2100_DEBUG
65 65
66config IPW2200 66config IPW2200
67 tristate "Intel PRO/Wireless 2200BG and 2915ABG Network Connection" 67 tristate "Intel PRO/Wireless 2200BG and 2915ABG Network Connection"
68 depends on PCI && WLAN_80211 && CFG80211 && CFG80211_WEXT 68 depends on PCI && CFG80211 && CFG80211_WEXT
69 select WIRELESS_EXT 69 select WIRELESS_EXT
70 select WEXT_SPY 70 select WEXT_SPY
71 select WEXT_PRIV 71 select WEXT_PRIV
@@ -154,7 +154,7 @@ config IPW2200_DEBUG
154 154
155config LIBIPW 155config LIBIPW
156 tristate 156 tristate
157 depends on PCI && WLAN_80211 && CFG80211 157 depends on PCI && CFG80211
158 select WIRELESS_EXT 158 select WIRELESS_EXT
159 select WEXT_SPY 159 select WEXT_SPY
160 select CRYPTO 160 select CRYPTO
diff --git a/drivers/net/wireless/iwlwifi/Kconfig b/drivers/net/wireless/iwlwifi/Kconfig
index c82c97be7bfa..b16b06c2031f 100644
--- a/drivers/net/wireless/iwlwifi/Kconfig
+++ b/drivers/net/wireless/iwlwifi/Kconfig
@@ -1,6 +1,6 @@
1config IWLWIFI 1config IWLWIFI
2 tristate "Intel Wireless Wifi" 2 tristate "Intel Wireless Wifi"
3 depends on PCI && MAC80211 && WLAN_80211 && EXPERIMENTAL 3 depends on PCI && MAC80211 && EXPERIMENTAL
4 select FW_LOADER 4 select FW_LOADER
5 5
6config IWLWIFI_SPECTRUM_MEASUREMENT 6config IWLWIFI_SPECTRUM_MEASUREMENT
diff --git a/drivers/net/wireless/iwlwifi/iwl-1000.c b/drivers/net/wireless/iwlwifi/iwl-1000.c
index 3a645e485dda..1e387b9dce1e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-1000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-1000.c
@@ -164,7 +164,7 @@ struct iwl_cfg iwl1000_bgn_cfg = {
164 .valid_tx_ant = ANT_A, 164 .valid_tx_ant = ANT_A,
165 .valid_rx_ant = ANT_AB, 165 .valid_rx_ant = ANT_AB,
166 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 166 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
167 .set_l0s = false, 167 .set_l0s = true,
168 .use_bsm = false, 168 .use_bsm = false,
169 .max_ll_items = OTP_MAX_LL_ITEMS_1000, 169 .max_ll_items = OTP_MAX_LL_ITEMS_1000,
170 .shadow_ram_support = false, 170 .shadow_ram_support = false,
@@ -190,7 +190,7 @@ struct iwl_cfg iwl1000_bg_cfg = {
190 .valid_tx_ant = ANT_A, 190 .valid_tx_ant = ANT_A,
191 .valid_rx_ant = ANT_AB, 191 .valid_rx_ant = ANT_AB,
192 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 192 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
193 .set_l0s = false, 193 .set_l0s = true,
194 .use_bsm = false, 194 .use_bsm = false,
195 .max_ll_items = OTP_MAX_LL_ITEMS_1000, 195 .max_ll_items = OTP_MAX_LL_ITEMS_1000,
196 .shadow_ram_support = false, 196 .shadow_ram_support = false,
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-rs.c b/drivers/net/wireless/iwlwifi/iwl-3945-rs.c
index cbb0585083a9..dc81e19674f7 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945-rs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-rs.c
@@ -42,38 +42,6 @@
42 42
43#define RS_NAME "iwl-3945-rs" 43#define RS_NAME "iwl-3945-rs"
44 44
45struct iwl3945_rate_scale_data {
46 u64 data;
47 s32 success_counter;
48 s32 success_ratio;
49 s32 counter;
50 s32 average_tpt;
51 unsigned long stamp;
52};
53
54struct iwl3945_rs_sta {
55 spinlock_t lock;
56 struct iwl_priv *priv;
57 s32 *expected_tpt;
58 unsigned long last_partial_flush;
59 unsigned long last_flush;
60 u32 flush_time;
61 u32 last_tx_packets;
62 u32 tx_packets;
63 u8 tgg;
64 u8 flush_pending;
65 u8 start_rate;
66 u8 ibss_sta_added;
67 struct timer_list rate_scale_flush;
68 struct iwl3945_rate_scale_data win[IWL_RATE_COUNT_3945];
69#ifdef CONFIG_MAC80211_DEBUGFS
70 struct dentry *rs_sta_dbgfs_stats_table_file;
71#endif
72
73 /* used to be in sta_info */
74 int last_txrate_idx;
75};
76
77static s32 iwl3945_expected_tpt_g[IWL_RATE_COUNT_3945] = { 45static s32 iwl3945_expected_tpt_g[IWL_RATE_COUNT_3945] = {
78 7, 13, 35, 58, 0, 0, 76, 104, 130, 168, 191, 202 46 7, 13, 35, 58, 0, 0, 76, 104, 130, 168, 191, 202
79}; 47};
@@ -370,6 +338,28 @@ static void rs_rate_init(void *priv_r, struct ieee80211_supported_band *sband,
370 338
371 IWL_DEBUG_RATE(priv, "enter\n"); 339 IWL_DEBUG_RATE(priv, "enter\n");
372 340
341 spin_lock_init(&rs_sta->lock);
342
343 rs_sta->priv = priv;
344
345 rs_sta->start_rate = IWL_RATE_INVALID;
346
347 /* default to just 802.11b */
348 rs_sta->expected_tpt = iwl3945_expected_tpt_b;
349
350 rs_sta->last_partial_flush = jiffies;
351 rs_sta->last_flush = jiffies;
352 rs_sta->flush_time = IWL_RATE_FLUSH;
353 rs_sta->last_tx_packets = 0;
354 rs_sta->ibss_sta_added = 0;
355
356 init_timer(&rs_sta->rate_scale_flush);
357 rs_sta->rate_scale_flush.data = (unsigned long)rs_sta;
358 rs_sta->rate_scale_flush.function = &iwl3945_bg_rate_scale_flush;
359
360 for (i = 0; i < IWL_RATE_COUNT_3945; i++)
361 iwl3945_clear_window(&rs_sta->win[i]);
362
373 /* TODO: what is a good starting rate for STA? About middle? Maybe not 363 /* TODO: what is a good starting rate for STA? About middle? Maybe not
374 * the lowest or the highest rate.. Could consider using RSSI from 364 * the lowest or the highest rate.. Could consider using RSSI from
375 * previous packets? Need to have IEEE 802.1X auth succeed immediately 365 * previous packets? Need to have IEEE 802.1X auth succeed immediately
@@ -409,45 +399,11 @@ static void *rs_alloc_sta(void *iwl_priv, struct ieee80211_sta *sta, gfp_t gfp)
409{ 399{
410 struct iwl3945_rs_sta *rs_sta; 400 struct iwl3945_rs_sta *rs_sta;
411 struct iwl3945_sta_priv *psta = (void *) sta->drv_priv; 401 struct iwl3945_sta_priv *psta = (void *) sta->drv_priv;
412 struct iwl_priv *priv = iwl_priv; 402 struct iwl_priv *priv __maybe_unused = iwl_priv;
413 int i;
414
415 /*
416 * XXX: If it's using sta->drv_priv anyway, it might
417 * as well just put all the information there.
418 */
419 403
420 IWL_DEBUG_RATE(priv, "enter\n"); 404 IWL_DEBUG_RATE(priv, "enter\n");
421 405
422 rs_sta = kzalloc(sizeof(struct iwl3945_rs_sta), gfp); 406 rs_sta = &psta->rs_sta;
423 if (!rs_sta) {
424 IWL_DEBUG_RATE(priv, "leave: ENOMEM\n");
425 return NULL;
426 }
427
428 psta->rs_sta = rs_sta;
429
430 spin_lock_init(&rs_sta->lock);
431
432 rs_sta->priv = priv;
433
434 rs_sta->start_rate = IWL_RATE_INVALID;
435
436 /* default to just 802.11b */
437 rs_sta->expected_tpt = iwl3945_expected_tpt_b;
438
439 rs_sta->last_partial_flush = jiffies;
440 rs_sta->last_flush = jiffies;
441 rs_sta->flush_time = IWL_RATE_FLUSH;
442 rs_sta->last_tx_packets = 0;
443 rs_sta->ibss_sta_added = 0;
444
445 init_timer(&rs_sta->rate_scale_flush);
446 rs_sta->rate_scale_flush.data = (unsigned long)rs_sta;
447 rs_sta->rate_scale_flush.function = &iwl3945_bg_rate_scale_flush;
448
449 for (i = 0; i < IWL_RATE_COUNT_3945; i++)
450 iwl3945_clear_window(&rs_sta->win[i]);
451 407
452 IWL_DEBUG_RATE(priv, "leave\n"); 408 IWL_DEBUG_RATE(priv, "leave\n");
453 409
@@ -458,14 +414,11 @@ static void rs_free_sta(void *iwl_priv, struct ieee80211_sta *sta,
458 void *priv_sta) 414 void *priv_sta)
459{ 415{
460 struct iwl3945_sta_priv *psta = (void *) sta->drv_priv; 416 struct iwl3945_sta_priv *psta = (void *) sta->drv_priv;
461 struct iwl3945_rs_sta *rs_sta = priv_sta; 417 struct iwl3945_rs_sta *rs_sta = &psta->rs_sta;
462 struct iwl_priv *priv __maybe_unused = rs_sta->priv; 418 struct iwl_priv *priv __maybe_unused = rs_sta->priv;
463 419
464 psta->rs_sta = NULL;
465
466 IWL_DEBUG_RATE(priv, "enter\n"); 420 IWL_DEBUG_RATE(priv, "enter\n");
467 del_timer_sync(&rs_sta->rate_scale_flush); 421 del_timer_sync(&rs_sta->rate_scale_flush);
468 kfree(rs_sta);
469 IWL_DEBUG_RATE(priv, "leave\n"); 422 IWL_DEBUG_RATE(priv, "leave\n");
470} 423}
471 424
@@ -960,14 +913,15 @@ void iwl3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id)
960 913
961 rcu_read_lock(); 914 rcu_read_lock();
962 915
963 sta = ieee80211_find_sta(hw, priv->stations[sta_id].sta.sta.addr); 916 sta = ieee80211_find_sta(priv->vif,
917 priv->stations[sta_id].sta.sta.addr);
964 if (!sta) { 918 if (!sta) {
965 rcu_read_unlock(); 919 rcu_read_unlock();
966 return; 920 return;
967 } 921 }
968 922
969 psta = (void *) sta->drv_priv; 923 psta = (void *) sta->drv_priv;
970 rs_sta = psta->rs_sta; 924 rs_sta = &psta->rs_sta;
971 925
972 spin_lock_irqsave(&rs_sta->lock, flags); 926 spin_lock_irqsave(&rs_sta->lock, flags);
973 927
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.h b/drivers/net/wireless/iwlwifi/iwl-3945.h
index ebb999a51b58..2b0d65c5780a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.h
@@ -74,8 +74,41 @@ extern struct pci_device_id iwl3945_hw_card_ids[];
74/* Module parameters accessible from iwl-*.c */ 74/* Module parameters accessible from iwl-*.c */
75extern struct iwl_mod_params iwl3945_mod_params; 75extern struct iwl_mod_params iwl3945_mod_params;
76 76
77struct iwl3945_rate_scale_data {
78 u64 data;
79 s32 success_counter;
80 s32 success_ratio;
81 s32 counter;
82 s32 average_tpt;
83 unsigned long stamp;
84};
85
86struct iwl3945_rs_sta {
87 spinlock_t lock;
88 struct iwl_priv *priv;
89 s32 *expected_tpt;
90 unsigned long last_partial_flush;
91 unsigned long last_flush;
92 u32 flush_time;
93 u32 last_tx_packets;
94 u32 tx_packets;
95 u8 tgg;
96 u8 flush_pending;
97 u8 start_rate;
98 u8 ibss_sta_added;
99 struct timer_list rate_scale_flush;
100 struct iwl3945_rate_scale_data win[IWL_RATE_COUNT_3945];
101#ifdef CONFIG_MAC80211_DEBUGFS
102 struct dentry *rs_sta_dbgfs_stats_table_file;
103#endif
104
105 /* used to be in sta_info */
106 int last_txrate_idx;
107};
108
109
77struct iwl3945_sta_priv { 110struct iwl3945_sta_priv {
78 struct iwl3945_rs_sta *rs_sta; 111 struct iwl3945_rs_sta rs_sta;
79}; 112};
80 113
81enum iwl3945_antenna { 114enum iwl3945_antenna {
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index d256fecc6cda..910217f0ad8a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -591,16 +591,6 @@ static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
591 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 591 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
592} 592}
593 593
594static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
595{
596 struct iwl_wimax_coex_cmd coex_cmd;
597
598 memset(&coex_cmd, 0, sizeof(coex_cmd));
599
600 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
601 sizeof(coex_cmd), &coex_cmd);
602}
603
604int iwl5000_alive_notify(struct iwl_priv *priv) 594int iwl5000_alive_notify(struct iwl_priv *priv)
605{ 595{
606 u32 a; 596 u32 a;
@@ -681,7 +671,7 @@ int iwl5000_alive_notify(struct iwl_priv *priv)
681 spin_unlock_irqrestore(&priv->lock, flags); 671 spin_unlock_irqrestore(&priv->lock, flags);
682 672
683 673
684 iwl5000_send_wimax_coex(priv); 674 iwl_send_wimax_coex(priv);
685 675
686 iwl5000_set_Xtal_calib(priv); 676 iwl5000_set_Xtal_calib(priv);
687 iwl_send_calib_results(priv); 677 iwl_send_calib_results(priv);
diff --git a/drivers/net/wireless/iwlwifi/iwl-6000.c b/drivers/net/wireless/iwlwifi/iwl-6000.c
index 32466d38d1ae..70e117f8d0c4 100644
--- a/drivers/net/wireless/iwlwifi/iwl-6000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-6000.c
@@ -299,7 +299,7 @@ struct iwl_cfg iwl6000h_2agn_cfg = {
299 .valid_tx_ant = ANT_AB, 299 .valid_tx_ant = ANT_AB,
300 .valid_rx_ant = ANT_AB, 300 .valid_rx_ant = ANT_AB,
301 .pll_cfg_val = 0, 301 .pll_cfg_val = 0,
302 .set_l0s = false, 302 .set_l0s = true,
303 .use_bsm = false, 303 .use_bsm = false,
304 .pa_type = IWL_PA_HYBRID, 304 .pa_type = IWL_PA_HYBRID,
305 .max_ll_items = OTP_MAX_LL_ITEMS_6x00, 305 .max_ll_items = OTP_MAX_LL_ITEMS_6x00,
@@ -329,7 +329,7 @@ struct iwl_cfg iwl6000h_2abg_cfg = {
329 .valid_tx_ant = ANT_AB, 329 .valid_tx_ant = ANT_AB,
330 .valid_rx_ant = ANT_AB, 330 .valid_rx_ant = ANT_AB,
331 .pll_cfg_val = 0, 331 .pll_cfg_val = 0,
332 .set_l0s = false, 332 .set_l0s = true,
333 .use_bsm = false, 333 .use_bsm = false,
334 .pa_type = IWL_PA_HYBRID, 334 .pa_type = IWL_PA_HYBRID,
335 .max_ll_items = OTP_MAX_LL_ITEMS_6x00, 335 .max_ll_items = OTP_MAX_LL_ITEMS_6x00,
@@ -358,7 +358,7 @@ struct iwl_cfg iwl6000h_2bg_cfg = {
358 .valid_tx_ant = ANT_AB, 358 .valid_tx_ant = ANT_AB,
359 .valid_rx_ant = ANT_AB, 359 .valid_rx_ant = ANT_AB,
360 .pll_cfg_val = 0, 360 .pll_cfg_val = 0,
361 .set_l0s = false, 361 .set_l0s = true,
362 .use_bsm = false, 362 .use_bsm = false,
363 .pa_type = IWL_PA_HYBRID, 363 .pa_type = IWL_PA_HYBRID,
364 .max_ll_items = OTP_MAX_LL_ITEMS_6x00, 364 .max_ll_items = OTP_MAX_LL_ITEMS_6x00,
@@ -390,7 +390,7 @@ struct iwl_cfg iwl6000i_2agn_cfg = {
390 .valid_tx_ant = ANT_BC, 390 .valid_tx_ant = ANT_BC,
391 .valid_rx_ant = ANT_BC, 391 .valid_rx_ant = ANT_BC,
392 .pll_cfg_val = 0, 392 .pll_cfg_val = 0,
393 .set_l0s = false, 393 .set_l0s = true,
394 .use_bsm = false, 394 .use_bsm = false,
395 .pa_type = IWL_PA_INTERNAL, 395 .pa_type = IWL_PA_INTERNAL,
396 .max_ll_items = OTP_MAX_LL_ITEMS_6x00, 396 .max_ll_items = OTP_MAX_LL_ITEMS_6x00,
@@ -420,7 +420,7 @@ struct iwl_cfg iwl6000i_2abg_cfg = {
420 .valid_tx_ant = ANT_BC, 420 .valid_tx_ant = ANT_BC,
421 .valid_rx_ant = ANT_BC, 421 .valid_rx_ant = ANT_BC,
422 .pll_cfg_val = 0, 422 .pll_cfg_val = 0,
423 .set_l0s = false, 423 .set_l0s = true,
424 .use_bsm = false, 424 .use_bsm = false,
425 .pa_type = IWL_PA_INTERNAL, 425 .pa_type = IWL_PA_INTERNAL,
426 .max_ll_items = OTP_MAX_LL_ITEMS_6x00, 426 .max_ll_items = OTP_MAX_LL_ITEMS_6x00,
@@ -449,7 +449,7 @@ struct iwl_cfg iwl6000i_2bg_cfg = {
449 .valid_tx_ant = ANT_BC, 449 .valid_tx_ant = ANT_BC,
450 .valid_rx_ant = ANT_BC, 450 .valid_rx_ant = ANT_BC,
451 .pll_cfg_val = 0, 451 .pll_cfg_val = 0,
452 .set_l0s = false, 452 .set_l0s = true,
453 .use_bsm = false, 453 .use_bsm = false,
454 .pa_type = IWL_PA_INTERNAL, 454 .pa_type = IWL_PA_INTERNAL,
455 .max_ll_items = OTP_MAX_LL_ITEMS_6x00, 455 .max_ll_items = OTP_MAX_LL_ITEMS_6x00,
@@ -478,7 +478,7 @@ struct iwl_cfg iwl6050_2agn_cfg = {
478 .valid_tx_ant = ANT_AB, 478 .valid_tx_ant = ANT_AB,
479 .valid_rx_ant = ANT_AB, 479 .valid_rx_ant = ANT_AB,
480 .pll_cfg_val = 0, 480 .pll_cfg_val = 0,
481 .set_l0s = false, 481 .set_l0s = true,
482 .use_bsm = false, 482 .use_bsm = false,
483 .pa_type = IWL_PA_SYSTEM, 483 .pa_type = IWL_PA_SYSTEM,
484 .max_ll_items = OTP_MAX_LL_ITEMS_6x50, 484 .max_ll_items = OTP_MAX_LL_ITEMS_6x50,
@@ -490,6 +490,8 @@ struct iwl_cfg iwl6050_2agn_cfg = {
490 .supports_idle = true, 490 .supports_idle = true,
491 .adv_thermal_throttle = true, 491 .adv_thermal_throttle = true,
492 .support_ct_kill_exit = true, 492 .support_ct_kill_exit = true,
493 .support_sm_ps = true,
494 .support_wimax_coexist = true,
493}; 495};
494 496
495struct iwl_cfg iwl6050_2abg_cfg = { 497struct iwl_cfg iwl6050_2abg_cfg = {
@@ -508,7 +510,7 @@ struct iwl_cfg iwl6050_2abg_cfg = {
508 .valid_tx_ant = ANT_AB, 510 .valid_tx_ant = ANT_AB,
509 .valid_rx_ant = ANT_AB, 511 .valid_rx_ant = ANT_AB,
510 .pll_cfg_val = 0, 512 .pll_cfg_val = 0,
511 .set_l0s = false, 513 .set_l0s = true,
512 .use_bsm = false, 514 .use_bsm = false,
513 .pa_type = IWL_PA_SYSTEM, 515 .pa_type = IWL_PA_SYSTEM,
514 .max_ll_items = OTP_MAX_LL_ITEMS_6x50, 516 .max_ll_items = OTP_MAX_LL_ITEMS_6x50,
@@ -519,6 +521,7 @@ struct iwl_cfg iwl6050_2abg_cfg = {
519 .supports_idle = true, 521 .supports_idle = true,
520 .adv_thermal_throttle = true, 522 .adv_thermal_throttle = true,
521 .support_ct_kill_exit = true, 523 .support_ct_kill_exit = true,
524 .support_wimax_coexist = true,
522}; 525};
523 526
524struct iwl_cfg iwl6000_3agn_cfg = { 527struct iwl_cfg iwl6000_3agn_cfg = {
@@ -537,7 +540,7 @@ struct iwl_cfg iwl6000_3agn_cfg = {
537 .valid_tx_ant = ANT_ABC, 540 .valid_tx_ant = ANT_ABC,
538 .valid_rx_ant = ANT_ABC, 541 .valid_rx_ant = ANT_ABC,
539 .pll_cfg_val = 0, 542 .pll_cfg_val = 0,
540 .set_l0s = false, 543 .set_l0s = true,
541 .use_bsm = false, 544 .use_bsm = false,
542 .pa_type = IWL_PA_SYSTEM, 545 .pa_type = IWL_PA_SYSTEM,
543 .max_ll_items = OTP_MAX_LL_ITEMS_6x00, 546 .max_ll_items = OTP_MAX_LL_ITEMS_6x00,
@@ -567,7 +570,7 @@ struct iwl_cfg iwl6050_3agn_cfg = {
567 .valid_tx_ant = ANT_ABC, 570 .valid_tx_ant = ANT_ABC,
568 .valid_rx_ant = ANT_ABC, 571 .valid_rx_ant = ANT_ABC,
569 .pll_cfg_val = 0, 572 .pll_cfg_val = 0,
570 .set_l0s = false, 573 .set_l0s = true,
571 .use_bsm = false, 574 .use_bsm = false,
572 .pa_type = IWL_PA_SYSTEM, 575 .pa_type = IWL_PA_SYSTEM,
573 .max_ll_items = OTP_MAX_LL_ITEMS_6x50, 576 .max_ll_items = OTP_MAX_LL_ITEMS_6x50,
@@ -579,6 +582,8 @@ struct iwl_cfg iwl6050_3agn_cfg = {
579 .supports_idle = true, 582 .supports_idle = true,
580 .adv_thermal_throttle = true, 583 .adv_thermal_throttle = true,
581 .support_ct_kill_exit = true, 584 .support_ct_kill_exit = true,
585 .support_sm_ps = true,
586 .support_wimax_coexist = true,
582}; 587};
583 588
584MODULE_FIRMWARE(IWL6000_MODULE_FIRMWARE(IWL6000_UCODE_API_MAX)); 589MODULE_FIRMWARE(IWL6000_MODULE_FIRMWARE(IWL6000_UCODE_API_MAX));
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-rs.c b/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
index 27d4ece4d467..43edd8fd4405 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
@@ -2477,19 +2477,12 @@ static void *rs_alloc_sta(void *priv_rate, struct ieee80211_sta *sta,
2477 struct iwl_lq_sta *lq_sta; 2477 struct iwl_lq_sta *lq_sta;
2478 struct iwl_station_priv *sta_priv = (struct iwl_station_priv *) sta->drv_priv; 2478 struct iwl_station_priv *sta_priv = (struct iwl_station_priv *) sta->drv_priv;
2479 struct iwl_priv *priv; 2479 struct iwl_priv *priv;
2480 int i, j;
2481 2480
2482 priv = (struct iwl_priv *)priv_rate; 2481 priv = (struct iwl_priv *)priv_rate;
2483 IWL_DEBUG_RATE(priv, "create station rate scale window\n"); 2482 IWL_DEBUG_RATE(priv, "create station rate scale window\n");
2484 2483
2485 lq_sta = &sta_priv->lq_sta; 2484 lq_sta = &sta_priv->lq_sta;
2486 2485
2487 lq_sta->lq.sta_id = 0xff;
2488
2489 for (j = 0; j < LQ_SIZE; j++)
2490 for (i = 0; i < IWL_RATE_COUNT; i++)
2491 rs_rate_scale_clear_window(&lq_sta->lq_info[j].win[i]);
2492
2493 return lq_sta; 2486 return lq_sta;
2494} 2487}
2495 2488
@@ -2502,6 +2495,12 @@ static void rs_rate_init(void *priv_r, struct ieee80211_supported_band *sband,
2502 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap; 2495 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
2503 struct iwl_lq_sta *lq_sta = priv_sta; 2496 struct iwl_lq_sta *lq_sta = priv_sta;
2504 2497
2498 lq_sta->lq.sta_id = 0xff;
2499
2500 for (j = 0; j < LQ_SIZE; j++)
2501 for (i = 0; i < IWL_RATE_COUNT; i++)
2502 rs_rate_scale_clear_window(&lq_sta->lq_info[j].win[i]);
2503
2505 lq_sta->flush_timer = 0; 2504 lq_sta->flush_timer = 0;
2506 lq_sta->supp_rates = sta->supp_rates[sband->band]; 2505 lq_sta->supp_rates = sta->supp_rates[sband->band];
2507 for (j = 0; j < LQ_SIZE; j++) 2506 for (j = 0; j < LQ_SIZE; j++)
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index fa1672e99e4b..b5fe8f87aa7e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -190,11 +190,7 @@ int iwl_commit_rxon(struct iwl_priv *priv)
190 priv->start_calib = 0; 190 priv->start_calib = 0;
191 191
192 /* Add the broadcast address so we can send broadcast frames */ 192 /* Add the broadcast address so we can send broadcast frames */
193 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) == 193 iwl_add_bcast_station(priv);
194 IWL_INVALID_STATION) {
195 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
196 return -EIO;
197 }
198 194
199 /* If we have set the ASSOC_MSK and we are in BSS mode then 195 /* If we have set the ASSOC_MSK and we are in BSS mode then
200 * add the IWL_AP_ID to the station rate table */ 196 * add the IWL_AP_ID to the station rate table */
@@ -890,6 +886,7 @@ static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
890 u32 inta, handled = 0; 886 u32 inta, handled = 0;
891 u32 inta_fh; 887 u32 inta_fh;
892 unsigned long flags; 888 unsigned long flags;
889 u32 i;
893#ifdef CONFIG_IWLWIFI_DEBUG 890#ifdef CONFIG_IWLWIFI_DEBUG
894 u32 inta_mask; 891 u32 inta_mask;
895#endif 892#endif
@@ -1007,19 +1004,17 @@ static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1007 handled |= CSR_INT_BIT_SW_ERR; 1004 handled |= CSR_INT_BIT_SW_ERR;
1008 } 1005 }
1009 1006
1010 /* uCode wakes up after power-down sleep */ 1007 /*
1008 * uCode wakes up after power-down sleep.
1009 * Tell device about any new tx or host commands enqueued,
1010 * and about any Rx buffers made available while asleep.
1011 */
1011 if (inta & CSR_INT_BIT_WAKEUP) { 1012 if (inta & CSR_INT_BIT_WAKEUP) {
1012 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); 1013 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1013 iwl_rx_queue_update_write_ptr(priv, &priv->rxq); 1014 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1014 iwl_txq_update_write_ptr(priv, &priv->txq[0]); 1015 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1015 iwl_txq_update_write_ptr(priv, &priv->txq[1]); 1016 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1016 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1017 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1018 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1019 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1020
1021 priv->isr_stats.wakeup++; 1017 priv->isr_stats.wakeup++;
1022
1023 handled |= CSR_INT_BIT_WAKEUP; 1018 handled |= CSR_INT_BIT_WAKEUP;
1024 } 1019 }
1025 1020
@@ -1033,11 +1028,12 @@ static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1033 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1028 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1034 } 1029 }
1035 1030
1031 /* This "Tx" DMA channel is used only for loading uCode */
1036 if (inta & CSR_INT_BIT_FH_TX) { 1032 if (inta & CSR_INT_BIT_FH_TX) {
1037 IWL_DEBUG_ISR(priv, "Tx interrupt\n"); 1033 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1038 priv->isr_stats.tx++; 1034 priv->isr_stats.tx++;
1039 handled |= CSR_INT_BIT_FH_TX; 1035 handled |= CSR_INT_BIT_FH_TX;
1040 /* FH finished to write, send event */ 1036 /* Wake up uCode load routine, now that load is complete */
1041 priv->ucode_write_complete = 1; 1037 priv->ucode_write_complete = 1;
1042 wake_up_interruptible(&priv->wait_command_queue); 1038 wake_up_interruptible(&priv->wait_command_queue);
1043 } 1039 }
@@ -1234,12 +1230,13 @@ static void iwl_irq_tasklet(struct iwl_priv *priv)
1234 iwl_leds_background(priv); 1230 iwl_leds_background(priv);
1235 } 1231 }
1236 1232
1233 /* This "Tx" DMA channel is used only for loading uCode */
1237 if (inta & CSR_INT_BIT_FH_TX) { 1234 if (inta & CSR_INT_BIT_FH_TX) {
1238 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); 1235 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1239 IWL_DEBUG_ISR(priv, "Tx interrupt\n"); 1236 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1240 priv->isr_stats.tx++; 1237 priv->isr_stats.tx++;
1241 handled |= CSR_INT_BIT_FH_TX; 1238 handled |= CSR_INT_BIT_FH_TX;
1242 /* FH finished to write, send event */ 1239 /* Wake up uCode load routine, now that load is complete */
1243 priv->ucode_write_complete = 1; 1240 priv->ucode_write_complete = 1;
1244 wake_up_interruptible(&priv->wait_command_queue); 1241 wake_up_interruptible(&priv->wait_command_queue);
1245 } 1242 }
@@ -1377,6 +1374,14 @@ static int iwl_read_ucode(struct iwl_priv *priv)
1377 IWL_UCODE_API(priv->ucode_ver), 1374 IWL_UCODE_API(priv->ucode_ver),
1378 IWL_UCODE_SERIAL(priv->ucode_ver)); 1375 IWL_UCODE_SERIAL(priv->ucode_ver));
1379 1376
1377 snprintf(priv->hw->wiphy->fw_version,
1378 sizeof(priv->hw->wiphy->fw_version),
1379 "%u.%u.%u.%u",
1380 IWL_UCODE_MAJOR(priv->ucode_ver),
1381 IWL_UCODE_MINOR(priv->ucode_ver),
1382 IWL_UCODE_API(priv->ucode_ver),
1383 IWL_UCODE_SERIAL(priv->ucode_ver));
1384
1380 if (build) 1385 if (build)
1381 IWL_DEBUG_INFO(priv, "Build %u\n", build); 1386 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1382 1387
@@ -2515,7 +2520,7 @@ void iwl_config_ap(struct iwl_priv *priv)
2515 spin_lock_irqsave(&priv->lock, flags); 2520 spin_lock_irqsave(&priv->lock, flags);
2516 iwl_activate_qos(priv, 1); 2521 iwl_activate_qos(priv, 1);
2517 spin_unlock_irqrestore(&priv->lock, flags); 2522 spin_unlock_irqrestore(&priv->lock, flags);
2518 iwl_rxon_add_station(priv, iwl_bcast_addr, 0); 2523 iwl_add_bcast_station(priv);
2519 } 2524 }
2520 iwl_send_beacon_cmd(priv); 2525 iwl_send_beacon_cmd(priv);
2521 2526
@@ -2963,6 +2968,100 @@ static void iwl_cancel_deferred_work(struct iwl_priv *priv)
2963 del_timer_sync(&priv->statistics_periodic); 2968 del_timer_sync(&priv->statistics_periodic);
2964} 2969}
2965 2970
2971static void iwl_init_hw_rates(struct iwl_priv *priv,
2972 struct ieee80211_rate *rates)
2973{
2974 int i;
2975
2976 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
2977 rates[i].bitrate = iwl_rates[i].ieee * 5;
2978 rates[i].hw_value = i; /* Rate scaling will work on indexes */
2979 rates[i].hw_value_short = i;
2980 rates[i].flags = 0;
2981 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
2982 /*
2983 * If CCK != 1M then set short preamble rate flag.
2984 */
2985 rates[i].flags |=
2986 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
2987 0 : IEEE80211_RATE_SHORT_PREAMBLE;
2988 }
2989 }
2990}
2991
2992static int iwl_init_drv(struct iwl_priv *priv)
2993{
2994 int ret;
2995
2996 priv->ibss_beacon = NULL;
2997
2998 spin_lock_init(&priv->lock);
2999 spin_lock_init(&priv->sta_lock);
3000 spin_lock_init(&priv->hcmd_lock);
3001
3002 INIT_LIST_HEAD(&priv->free_frames);
3003
3004 mutex_init(&priv->mutex);
3005
3006 /* Clear the driver's (not device's) station table */
3007 iwl_clear_stations_table(priv);
3008
3009 priv->ieee_channels = NULL;
3010 priv->ieee_rates = NULL;
3011 priv->band = IEEE80211_BAND_2GHZ;
3012
3013 priv->iw_mode = NL80211_IFTYPE_STATION;
3014 if (priv->cfg->support_sm_ps)
3015 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DYNAMIC;
3016 else
3017 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
3018
3019 /* Choose which receivers/antennas to use */
3020 if (priv->cfg->ops->hcmd->set_rxon_chain)
3021 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3022
3023 iwl_init_scan_params(priv);
3024
3025 iwl_reset_qos(priv);
3026
3027 priv->qos_data.qos_active = 0;
3028 priv->qos_data.qos_cap.val = 0;
3029
3030 priv->rates_mask = IWL_RATES_MASK;
3031 /* Set the tx_power_user_lmt to the lowest power level
3032 * this value will get overwritten by channel max power avg
3033 * from eeprom */
3034 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
3035
3036 ret = iwl_init_channel_map(priv);
3037 if (ret) {
3038 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3039 goto err;
3040 }
3041
3042 ret = iwlcore_init_geos(priv);
3043 if (ret) {
3044 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3045 goto err_free_channel_map;
3046 }
3047 iwl_init_hw_rates(priv, priv->ieee_rates);
3048
3049 return 0;
3050
3051err_free_channel_map:
3052 iwl_free_channel_map(priv);
3053err:
3054 return ret;
3055}
3056
3057static void iwl_uninit_drv(struct iwl_priv *priv)
3058{
3059 iwl_calib_free_results(priv);
3060 iwlcore_free_geos(priv);
3061 iwl_free_channel_map(priv);
3062 kfree(priv->scan);
3063}
3064
2966static struct attribute *iwl_sysfs_entries[] = { 3065static struct attribute *iwl_sysfs_entries[] = {
2967 &dev_attr_flags.attr, 3066 &dev_attr_flags.attr,
2968 &dev_attr_filter_flags.attr, 3067 &dev_attr_filter_flags.attr,
@@ -3105,12 +3204,6 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3105 goto out_iounmap; 3204 goto out_iounmap;
3106 } 3205 }
3107 3206
3108 /* amp init */
3109 err = priv->cfg->ops->lib->apm_ops.init(priv);
3110 if (err < 0) {
3111 IWL_ERR(priv, "Failed to init APMG\n");
3112 goto out_iounmap;
3113 }
3114 /***************** 3207 /*****************
3115 * 4. Read EEPROM 3208 * 4. Read EEPROM
3116 *****************/ 3209 *****************/
diff --git a/drivers/net/wireless/iwlwifi/iwl-calib.c b/drivers/net/wireless/iwlwifi/iwl-calib.c
index 1f801eb9fbff..d994de7438d8 100644
--- a/drivers/net/wireless/iwlwifi/iwl-calib.c
+++ b/drivers/net/wireless/iwlwifi/iwl-calib.c
@@ -132,6 +132,7 @@ void iwl_calib_free_results(struct iwl_priv *priv)
132 priv->calib_results[i].buf_len = 0; 132 priv->calib_results[i].buf_len = 0;
133 } 133 }
134} 134}
135EXPORT_SYMBOL(iwl_calib_free_results);
135 136
136/***************************************************************************** 137/*****************************************************************************
137 * RUNTIME calibrations framework 138 * RUNTIME calibrations framework
diff --git a/drivers/net/wireless/iwlwifi/iwl-commands.h b/drivers/net/wireless/iwlwifi/iwl-commands.h
index 954bad60355d..b62c90ec9e1e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-commands.h
+++ b/drivers/net/wireless/iwlwifi/iwl-commands.h
@@ -3503,30 +3503,134 @@ struct iwl_led_cmd {
3503} __attribute__ ((packed)); 3503} __attribute__ ((packed));
3504 3504
3505/* 3505/*
3506 * Coexistence WIFI/WIMAX Command 3506 * station priority table entries
3507 * COEX_PRIORITY_TABLE_CMD = 0x5a 3507 * also used as potential "events" value for both
3508 * 3508 * COEX_MEDIUM_NOTIFICATION and COEX_EVENT_CMD
3509 */ 3509 */
3510
3511/*
3512 * COEX events entry flag masks
3513 * RP - Requested Priority
3514 * WP - Win Medium Priority: priority assigned when the contention has been won
3515 */
3516#define COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG (0x1)
3517#define COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG (0x2)
3518#define COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG (0x4)
3519
3520#define COEX_CU_UNASSOC_IDLE_RP 4
3521#define COEX_CU_UNASSOC_MANUAL_SCAN_RP 4
3522#define COEX_CU_UNASSOC_AUTO_SCAN_RP 4
3523#define COEX_CU_CALIBRATION_RP 4
3524#define COEX_CU_PERIODIC_CALIBRATION_RP 4
3525#define COEX_CU_CONNECTION_ESTAB_RP 4
3526#define COEX_CU_ASSOCIATED_IDLE_RP 4
3527#define COEX_CU_ASSOC_MANUAL_SCAN_RP 4
3528#define COEX_CU_ASSOC_AUTO_SCAN_RP 4
3529#define COEX_CU_ASSOC_ACTIVE_LEVEL_RP 4
3530#define COEX_CU_RF_ON_RP 6
3531#define COEX_CU_RF_OFF_RP 4
3532#define COEX_CU_STAND_ALONE_DEBUG_RP 6
3533#define COEX_CU_IPAN_ASSOC_LEVEL_RP 4
3534#define COEX_CU_RSRVD1_RP 4
3535#define COEX_CU_RSRVD2_RP 4
3536
3537#define COEX_CU_UNASSOC_IDLE_WP 3
3538#define COEX_CU_UNASSOC_MANUAL_SCAN_WP 3
3539#define COEX_CU_UNASSOC_AUTO_SCAN_WP 3
3540#define COEX_CU_CALIBRATION_WP 3
3541#define COEX_CU_PERIODIC_CALIBRATION_WP 3
3542#define COEX_CU_CONNECTION_ESTAB_WP 3
3543#define COEX_CU_ASSOCIATED_IDLE_WP 3
3544#define COEX_CU_ASSOC_MANUAL_SCAN_WP 3
3545#define COEX_CU_ASSOC_AUTO_SCAN_WP 3
3546#define COEX_CU_ASSOC_ACTIVE_LEVEL_WP 3
3547#define COEX_CU_RF_ON_WP 3
3548#define COEX_CU_RF_OFF_WP 3
3549#define COEX_CU_STAND_ALONE_DEBUG_WP 6
3550#define COEX_CU_IPAN_ASSOC_LEVEL_WP 3
3551#define COEX_CU_RSRVD1_WP 3
3552#define COEX_CU_RSRVD2_WP 3
3553
3554#define COEX_UNASSOC_IDLE_FLAGS 0
3555#define COEX_UNASSOC_MANUAL_SCAN_FLAGS \
3556 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3557 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3558#define COEX_UNASSOC_AUTO_SCAN_FLAGS \
3559 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3560 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3561#define COEX_CALIBRATION_FLAGS \
3562 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3563 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3564#define COEX_PERIODIC_CALIBRATION_FLAGS 0
3565/*
3566 * COEX_CONNECTION_ESTAB:
3567 * we need DELAY_MEDIUM_FREE_NTFY to let WiMAX disconnect from network.
3568 */
3569#define COEX_CONNECTION_ESTAB_FLAGS \
3570 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3571 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3572 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3573#define COEX_ASSOCIATED_IDLE_FLAGS 0
3574#define COEX_ASSOC_MANUAL_SCAN_FLAGS \
3575 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3576 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3577#define COEX_ASSOC_AUTO_SCAN_FLAGS \
3578 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3579 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3580#define COEX_ASSOC_ACTIVE_LEVEL_FLAGS 0
3581#define COEX_RF_ON_FLAGS 0
3582#define COEX_RF_OFF_FLAGS 0
3583#define COEX_STAND_ALONE_DEBUG_FLAGS \
3584 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3585 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3586#define COEX_IPAN_ASSOC_LEVEL_FLAGS \
3587 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3588 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3589 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3590#define COEX_RSRVD1_FLAGS 0
3591#define COEX_RSRVD2_FLAGS 0
3592/*
3593 * COEX_CU_RF_ON is the event wrapping all radio ownership.
3594 * We need DELAY_MEDIUM_FREE_NTFY to let WiMAX disconnect from network.
3595 */
3596#define COEX_CU_RF_ON_FLAGS \
3597 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3598 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3599 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3600
3601
3510enum { 3602enum {
3603 /* un-association part */
3511 COEX_UNASSOC_IDLE = 0, 3604 COEX_UNASSOC_IDLE = 0,
3512 COEX_UNASSOC_MANUAL_SCAN = 1, 3605 COEX_UNASSOC_MANUAL_SCAN = 1,
3513 COEX_UNASSOC_AUTO_SCAN = 2, 3606 COEX_UNASSOC_AUTO_SCAN = 2,
3607 /* calibration */
3514 COEX_CALIBRATION = 3, 3608 COEX_CALIBRATION = 3,
3515 COEX_PERIODIC_CALIBRATION = 4, 3609 COEX_PERIODIC_CALIBRATION = 4,
3610 /* connection */
3516 COEX_CONNECTION_ESTAB = 5, 3611 COEX_CONNECTION_ESTAB = 5,
3612 /* association part */
3517 COEX_ASSOCIATED_IDLE = 6, 3613 COEX_ASSOCIATED_IDLE = 6,
3518 COEX_ASSOC_MANUAL_SCAN = 7, 3614 COEX_ASSOC_MANUAL_SCAN = 7,
3519 COEX_ASSOC_AUTO_SCAN = 8, 3615 COEX_ASSOC_AUTO_SCAN = 8,
3520 COEX_ASSOC_ACTIVE_LEVEL = 9, 3616 COEX_ASSOC_ACTIVE_LEVEL = 9,
3617 /* RF ON/OFF */
3521 COEX_RF_ON = 10, 3618 COEX_RF_ON = 10,
3522 COEX_RF_OFF = 11, 3619 COEX_RF_OFF = 11,
3523 COEX_STAND_ALONE_DEBUG = 12, 3620 COEX_STAND_ALONE_DEBUG = 12,
3621 /* IPAN */
3524 COEX_IPAN_ASSOC_LEVEL = 13, 3622 COEX_IPAN_ASSOC_LEVEL = 13,
3623 /* reserved */
3525 COEX_RSRVD1 = 14, 3624 COEX_RSRVD1 = 14,
3526 COEX_RSRVD2 = 15, 3625 COEX_RSRVD2 = 15,
3527 COEX_NUM_OF_EVENTS = 16 3626 COEX_NUM_OF_EVENTS = 16
3528}; 3627};
3529 3628
3629/*
3630 * Coexistence WIFI/WIMAX Command
3631 * COEX_PRIORITY_TABLE_CMD = 0x5a
3632 *
3633 */
3530struct iwl_wimax_coex_event_entry { 3634struct iwl_wimax_coex_event_entry {
3531 u8 request_prio; 3635 u8 request_prio;
3532 u8 win_medium_prio; 3636 u8 win_medium_prio;
@@ -3551,6 +3655,55 @@ struct iwl_wimax_coex_cmd {
3551 struct iwl_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS]; 3655 struct iwl_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS];
3552} __attribute__ ((packed)); 3656} __attribute__ ((packed));
3553 3657
3658/*
3659 * Coexistence MEDIUM NOTIFICATION
3660 * COEX_MEDIUM_NOTIFICATION = 0x5b
3661 *
3662 * notification from uCode to host to indicate medium changes
3663 *
3664 */
3665/*
3666 * status field
3667 * bit 0 - 2: medium status
3668 * bit 3: medium change indication
3669 * bit 4 - 31: reserved
3670 */
3671/* status option values, (0 - 2 bits) */
3672#define COEX_MEDIUM_BUSY (0x0) /* radio belongs to WiMAX */
3673#define COEX_MEDIUM_ACTIVE (0x1) /* radio belongs to WiFi */
3674#define COEX_MEDIUM_PRE_RELEASE (0x2) /* received radio release */
3675#define COEX_MEDIUM_MSK (0x7)
3676
3677/* send notification status (1 bit) */
3678#define COEX_MEDIUM_CHANGED (0x8)
3679#define COEX_MEDIUM_CHANGED_MSK (0x8)
3680#define COEX_MEDIUM_SHIFT (3)
3681
3682struct iwl_coex_medium_notification {
3683 __le32 status;
3684 __le32 events;
3685} __attribute__ ((packed));
3686
3687/*
3688 * Coexistence EVENT Command
3689 * COEX_EVENT_CMD = 0x5c
3690 *
3691 * send from host to uCode for coex event request.
3692 */
3693/* flags options */
3694#define COEX_EVENT_REQUEST_MSK (0x1)
3695
3696struct iwl_coex_event_cmd {
3697 u8 flags;
3698 u8 event;
3699 __le16 reserved;
3700} __attribute__ ((packed));
3701
3702struct iwl_coex_event_resp {
3703 __le32 status;
3704} __attribute__ ((packed));
3705
3706
3554/****************************************************************************** 3707/******************************************************************************
3555 * (13) 3708 * (13)
3556 * Union of all expected notifications/responses: 3709 * Union of all expected notifications/responses:
@@ -3587,6 +3740,8 @@ struct iwl_rx_packet {
3587 struct iwl_notif_statistics stats; 3740 struct iwl_notif_statistics stats;
3588 struct iwl_compressed_ba_resp compressed_ba; 3741 struct iwl_compressed_ba_resp compressed_ba;
3589 struct iwl_missed_beacon_notif missed_beacon; 3742 struct iwl_missed_beacon_notif missed_beacon;
3743 struct iwl_coex_medium_notification coex_medium_notif;
3744 struct iwl_coex_event_resp coex_event;
3590 __le32 status; 3745 __le32 status;
3591 u8 raw[0]; 3746 u8 raw[0];
3592 } u; 3747 } u;
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c
index d2b56baf98fb..e0b5b4aef41d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.c
+++ b/drivers/net/wireless/iwlwifi/iwl-core.c
@@ -46,6 +46,37 @@ MODULE_VERSION(IWLWIFI_VERSION);
46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); 46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
47MODULE_LICENSE("GPL"); 47MODULE_LICENSE("GPL");
48 48
49static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
50 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
51 0, COEX_UNASSOC_IDLE_FLAGS},
52 {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
53 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
54 {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
55 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
56 {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
57 0, COEX_CALIBRATION_FLAGS},
58 {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
59 0, COEX_PERIODIC_CALIBRATION_FLAGS},
60 {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
61 0, COEX_CONNECTION_ESTAB_FLAGS},
62 {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
63 0, COEX_ASSOCIATED_IDLE_FLAGS},
64 {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
65 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
66 {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
67 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
68 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
69 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
70 {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
71 {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
72 {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
73 0, COEX_STAND_ALONE_DEBUG_FLAGS},
74 {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
75 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
76 {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
77 {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
78};
79
49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \ 80#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \ 81 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \ 82 IWL_RATE_SISO_##s##M_PLCP, \
@@ -414,8 +445,12 @@ static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
414 if (priv->cfg->ht_greenfield_support) 445 if (priv->cfg->ht_greenfield_support)
415 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD; 446 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
416 ht_info->cap |= IEEE80211_HT_CAP_SGI_20; 447 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
417 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS & 448 if (priv->cfg->support_sm_ps)
418 (WLAN_HT_CAP_SM_PS_DISABLED << 2)); 449 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
450 (WLAN_HT_CAP_SM_PS_DYNAMIC << 2));
451 else
452 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
453 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
419 454
420 max_bit_rate = MAX_BIT_RATE_20_MHZ; 455 max_bit_rate = MAX_BIT_RATE_20_MHZ;
421 if (priv->hw_params.ht40_channel & BIT(band)) { 456 if (priv->hw_params.ht40_channel & BIT(band)) {
@@ -451,28 +486,6 @@ static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
451 } 486 }
452} 487}
453 488
454static void iwlcore_init_hw_rates(struct iwl_priv *priv,
455 struct ieee80211_rate *rates)
456{
457 int i;
458
459 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
460 rates[i].bitrate = iwl_rates[i].ieee * 5;
461 rates[i].hw_value = i; /* Rate scaling will work on indexes */
462 rates[i].hw_value_short = i;
463 rates[i].flags = 0;
464 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
465 /*
466 * If CCK != 1M then set short preamble rate flag.
467 */
468 rates[i].flags |=
469 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
470 0 : IEEE80211_RATE_SHORT_PREAMBLE;
471 }
472 }
473}
474
475
476/** 489/**
477 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom 490 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
478 */ 491 */
@@ -985,17 +998,35 @@ static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
985} 998}
986 999
987/* 1000/*
988 * When we are in power saving, there's no difference between 1001 * When we are in power saving mode, unless device support spatial
989 * using multiple chains or just a single chain, but due to the 1002 * multiplexing power save, use the active count for rx chain count.
990 * lack of SM PS we lose a lot of throughput if we use just a
991 * single chain.
992 *
993 * Therefore, use the active count here (which will use multiple
994 * chains unless connected to a legacy AP).
995 */ 1003 */
996static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt) 1004static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
997{ 1005{
998 return active_cnt; 1006 int idle_cnt = active_cnt;
1007 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
1008
1009 if (priv->cfg->support_sm_ps) {
1010 /* # Rx chains when idling and maybe trying to save power */
1011 switch (priv->current_ht_config.sm_ps) {
1012 case WLAN_HT_CAP_SM_PS_STATIC:
1013 case WLAN_HT_CAP_SM_PS_DYNAMIC:
1014 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
1015 IWL_NUM_IDLE_CHAINS_SINGLE;
1016 break;
1017 case WLAN_HT_CAP_SM_PS_DISABLED:
1018 idle_cnt = (is_cam) ? active_cnt :
1019 IWL_NUM_IDLE_CHAINS_SINGLE;
1020 break;
1021 case WLAN_HT_CAP_SM_PS_INVALID:
1022 default:
1023 IWL_ERR(priv, "invalid sm_ps mode %d\n",
1024 priv->current_ht_config.sm_ps);
1025 WARN_ON(1);
1026 break;
1027 }
1028 }
1029 return idle_cnt;
999} 1030}
1000 1031
1001/* up to 4 chains */ 1032/* up to 4 chains */
@@ -1353,39 +1384,39 @@ EXPORT_SYMBOL(iwl_irq_handle_error);
1353 1384
1354int iwl_apm_stop_master(struct iwl_priv *priv) 1385int iwl_apm_stop_master(struct iwl_priv *priv)
1355{ 1386{
1356 unsigned long flags; 1387 int ret = 0;
1357
1358 spin_lock_irqsave(&priv->lock, flags);
1359 1388
1360 /* set stop master bit */ 1389 /* stop device's busmaster DMA activity */
1361 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 1390 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1362 1391
1363 iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED, 1392 ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
1364 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 1393 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1394 if (ret)
1395 IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
1365 1396
1366 spin_unlock_irqrestore(&priv->lock, flags);
1367 IWL_DEBUG_INFO(priv, "stop master\n"); 1397 IWL_DEBUG_INFO(priv, "stop master\n");
1368 1398
1369 return 0; 1399 return ret;
1370} 1400}
1371EXPORT_SYMBOL(iwl_apm_stop_master); 1401EXPORT_SYMBOL(iwl_apm_stop_master);
1372 1402
1373void iwl_apm_stop(struct iwl_priv *priv) 1403void iwl_apm_stop(struct iwl_priv *priv)
1374{ 1404{
1375 unsigned long flags;
1376
1377 IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n"); 1405 IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
1378 1406
1407 /* Stop device's DMA activity */
1379 iwl_apm_stop_master(priv); 1408 iwl_apm_stop_master(priv);
1380 1409
1381 spin_lock_irqsave(&priv->lock, flags); 1410 /* Reset the entire device */
1382
1383 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1411 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1384 1412
1385 udelay(10); 1413 udelay(10);
1386 /* clear "init complete" move adapter D0A* --> D0U state */ 1414
1415 /*
1416 * Clear "initialization complete" bit to move adapter from
1417 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
1418 */
1387 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1419 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1388 spin_unlock_irqrestore(&priv->lock, flags);
1389} 1420}
1390EXPORT_SYMBOL(iwl_apm_stop); 1421EXPORT_SYMBOL(iwl_apm_stop);
1391 1422
@@ -1430,8 +1461,12 @@ int iwl_apm_init(struct iwl_priv *priv)
1430 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 1461 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
1431 1462
1432 /* 1463 /*
1433 * HW bug W/A - costs negligible power consumption ... 1464 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
1434 * Check if BIOS (or OS) enabled L1-ASPM on this device 1465 * Check if BIOS (or OS) enabled L1-ASPM on this device.
1466 * If so (likely), disable L0S, so device moves directly L0->L1;
1467 * costs negligible amount of power savings.
1468 * If not (unlikely), enable L0S, so there is at least some
1469 * power savings, even without L1.
1435 */ 1470 */
1436 if (priv->cfg->set_l0s) { 1471 if (priv->cfg->set_l0s) {
1437 lctl = iwl_pcie_link_ctl(priv); 1472 lctl = iwl_pcie_link_ctl(priv);
@@ -1567,68 +1602,6 @@ int iwl_set_hw_params(struct iwl_priv *priv)
1567} 1602}
1568EXPORT_SYMBOL(iwl_set_hw_params); 1603EXPORT_SYMBOL(iwl_set_hw_params);
1569 1604
1570int iwl_init_drv(struct iwl_priv *priv)
1571{
1572 int ret;
1573
1574 priv->ibss_beacon = NULL;
1575
1576 spin_lock_init(&priv->lock);
1577 spin_lock_init(&priv->sta_lock);
1578 spin_lock_init(&priv->hcmd_lock);
1579
1580 INIT_LIST_HEAD(&priv->free_frames);
1581
1582 mutex_init(&priv->mutex);
1583
1584 /* Clear the driver's (not device's) station table */
1585 iwl_clear_stations_table(priv);
1586
1587 priv->ieee_channels = NULL;
1588 priv->ieee_rates = NULL;
1589 priv->band = IEEE80211_BAND_2GHZ;
1590
1591 priv->iw_mode = NL80211_IFTYPE_STATION;
1592
1593 /* Choose which receivers/antennas to use */
1594 if (priv->cfg->ops->hcmd->set_rxon_chain)
1595 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1596
1597 iwl_init_scan_params(priv);
1598
1599 iwl_reset_qos(priv);
1600
1601 priv->qos_data.qos_active = 0;
1602 priv->qos_data.qos_cap.val = 0;
1603
1604 priv->rates_mask = IWL_RATES_MASK;
1605 /* Set the tx_power_user_lmt to the lowest power level
1606 * this value will get overwritten by channel max power avg
1607 * from eeprom */
1608 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
1609
1610 ret = iwl_init_channel_map(priv);
1611 if (ret) {
1612 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
1613 goto err;
1614 }
1615
1616 ret = iwlcore_init_geos(priv);
1617 if (ret) {
1618 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
1619 goto err_free_channel_map;
1620 }
1621 iwlcore_init_hw_rates(priv, priv->ieee_rates);
1622
1623 return 0;
1624
1625err_free_channel_map:
1626 iwl_free_channel_map(priv);
1627err:
1628 return ret;
1629}
1630EXPORT_SYMBOL(iwl_init_drv);
1631
1632int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force) 1605int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1633{ 1606{
1634 int ret = 0; 1607 int ret = 0;
@@ -1676,15 +1649,6 @@ int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1676} 1649}
1677EXPORT_SYMBOL(iwl_set_tx_power); 1650EXPORT_SYMBOL(iwl_set_tx_power);
1678 1651
1679void iwl_uninit_drv(struct iwl_priv *priv)
1680{
1681 iwl_calib_free_results(priv);
1682 iwlcore_free_geos(priv);
1683 iwl_free_channel_map(priv);
1684 kfree(priv->scan);
1685}
1686EXPORT_SYMBOL(iwl_uninit_drv);
1687
1688#define ICT_COUNT (PAGE_SIZE/sizeof(u32)) 1652#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1689 1653
1690/* Free dram table */ 1654/* Free dram table */
@@ -2336,7 +2300,7 @@ static void iwl_ht_conf(struct iwl_priv *priv,
2336 switch (priv->iw_mode) { 2300 switch (priv->iw_mode) {
2337 case NL80211_IFTYPE_STATION: 2301 case NL80211_IFTYPE_STATION:
2338 rcu_read_lock(); 2302 rcu_read_lock();
2339 sta = ieee80211_find_sta(priv->hw, priv->bssid); 2303 sta = ieee80211_find_sta(priv->vif, priv->bssid);
2340 if (sta) { 2304 if (sta) {
2341 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap; 2305 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
2342 int maxstreams; 2306 int maxstreams;
@@ -2346,6 +2310,12 @@ static void iwl_ht_conf(struct iwl_priv *priv,
2346 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 2310 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2347 maxstreams += 1; 2311 maxstreams += 1;
2348 2312
2313 ht_conf->sm_ps =
2314 (u8)((ht_cap->cap & IEEE80211_HT_CAP_SM_PS)
2315 >> 2);
2316 IWL_DEBUG_MAC80211(priv, "sm_ps: 0x%x\n",
2317 ht_conf->sm_ps);
2318
2349 if ((ht_cap->mcs.rx_mask[1] == 0) && 2319 if ((ht_cap->mcs.rx_mask[1] == 0) &&
2350 (ht_cap->mcs.rx_mask[2] == 0)) 2320 (ht_cap->mcs.rx_mask[2] == 0))
2351 ht_conf->single_chain_sufficient = true; 2321 ht_conf->single_chain_sufficient = true;
@@ -2926,6 +2896,34 @@ void iwl_free_txq_mem(struct iwl_priv *priv)
2926} 2896}
2927EXPORT_SYMBOL(iwl_free_txq_mem); 2897EXPORT_SYMBOL(iwl_free_txq_mem);
2928 2898
2899int iwl_send_wimax_coex(struct iwl_priv *priv)
2900{
2901 struct iwl_wimax_coex_cmd uninitialized_var(coex_cmd);
2902
2903 if (priv->cfg->support_wimax_coexist) {
2904 /* UnMask wake up src at associated sleep */
2905 coex_cmd.flags |= COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
2906
2907 /* UnMask wake up src at unassociated sleep */
2908 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
2909 memcpy(coex_cmd.sta_prio, cu_priorities,
2910 sizeof(struct iwl_wimax_coex_event_entry) *
2911 COEX_NUM_OF_EVENTS);
2912
2913 /* enabling the coexistence feature */
2914 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
2915
2916 /* enabling the priorities tables */
2917 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
2918 } else {
2919 /* coexistence is disabled */
2920 memset(&coex_cmd, 0, sizeof(coex_cmd));
2921 }
2922 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
2923 sizeof(coex_cmd), &coex_cmd);
2924}
2925EXPORT_SYMBOL(iwl_send_wimax_coex);
2926
2929#ifdef CONFIG_IWLWIFI_DEBUGFS 2927#ifdef CONFIG_IWLWIFI_DEBUGFS
2930 2928
2931#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES) 2929#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.h b/drivers/net/wireless/iwlwifi/iwl-core.h
index b875dcfca2d6..9574d8f33537 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.h
+++ b/drivers/net/wireless/iwlwifi/iwl-core.h
@@ -228,6 +228,8 @@ struct iwl_mod_params {
228 * @chain_noise_num_beacons: number of beacons used to compute chain noise 228 * @chain_noise_num_beacons: number of beacons used to compute chain noise
229 * @adv_thermal_throttle: support advance thermal throttle 229 * @adv_thermal_throttle: support advance thermal throttle
230 * @support_ct_kill_exit: support ct kill exit condition 230 * @support_ct_kill_exit: support ct kill exit condition
231 * @support_sm_ps: support spatial multiplexing power save
232 * @support_wimax_coexist: support wimax/wifi co-exist
231 * 233 *
232 * We enable the driver to be backward compatible wrt API version. The 234 * We enable the driver to be backward compatible wrt API version. The
233 * driver specifies which APIs it supports (with @ucode_api_max being the 235 * driver specifies which APIs it supports (with @ucode_api_max being the
@@ -283,6 +285,8 @@ struct iwl_cfg {
283 const bool supports_idle; 285 const bool supports_idle;
284 bool adv_thermal_throttle; 286 bool adv_thermal_throttle;
285 bool support_ct_kill_exit; 287 bool support_ct_kill_exit;
288 bool support_sm_ps;
289 const bool support_wimax_coexist;
286}; 290};
287 291
288/*************************** 292/***************************
@@ -316,8 +320,6 @@ void iwl_configure_filter(struct ieee80211_hw *hw,
316 unsigned int *total_flags, u64 multicast); 320 unsigned int *total_flags, u64 multicast);
317int iwl_hw_nic_init(struct iwl_priv *priv); 321int iwl_hw_nic_init(struct iwl_priv *priv);
318int iwl_set_hw_params(struct iwl_priv *priv); 322int iwl_set_hw_params(struct iwl_priv *priv);
319int iwl_init_drv(struct iwl_priv *priv);
320void iwl_uninit_drv(struct iwl_priv *priv);
321bool iwl_is_monitor_mode(struct iwl_priv *priv); 323bool iwl_is_monitor_mode(struct iwl_priv *priv);
322void iwl_post_associate(struct iwl_priv *priv); 324void iwl_post_associate(struct iwl_priv *priv);
323void iwl_bss_info_changed(struct ieee80211_hw *hw, 325void iwl_bss_info_changed(struct ieee80211_hw *hw,
@@ -340,6 +342,7 @@ int iwl_alloc_txq_mem(struct iwl_priv *priv);
340void iwl_free_txq_mem(struct iwl_priv *priv); 342void iwl_free_txq_mem(struct iwl_priv *priv);
341void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info, 343void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
342 __le32 *tx_flags); 344 __le32 *tx_flags);
345int iwl_send_wimax_coex(struct iwl_priv *priv);
343#ifdef CONFIG_IWLWIFI_DEBUGFS 346#ifdef CONFIG_IWLWIFI_DEBUGFS
344int iwl_alloc_traffic_mem(struct iwl_priv *priv); 347int iwl_alloc_traffic_mem(struct iwl_priv *priv);
345void iwl_free_traffic_mem(struct iwl_priv *priv); 348void iwl_free_traffic_mem(struct iwl_priv *priv);
diff --git a/drivers/net/wireless/iwlwifi/iwl-dev.h b/drivers/net/wireless/iwlwifi/iwl-dev.h
index e7ce67387662..cb2642c18da4 100644
--- a/drivers/net/wireless/iwlwifi/iwl-dev.h
+++ b/drivers/net/wireless/iwlwifi/iwl-dev.h
@@ -517,6 +517,7 @@ struct iwl_ht_config {
517 bool is_ht; 517 bool is_ht;
518 bool is_40mhz; 518 bool is_40mhz;
519 bool single_chain_sufficient; 519 bool single_chain_sufficient;
520 u8 sm_ps;
520 /* BSS related data */ 521 /* BSS related data */
521 u8 extension_chan_offset; 522 u8 extension_chan_offset;
522 u8 ht_protection; 523 u8 ht_protection;
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index 9429cb1c69bd..8a0709e81a9f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -533,6 +533,10 @@ int iwl_eeprom_init(struct iwl_priv *priv)
533 goto err; 533 goto err;
534 } 534 }
535 if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) { 535 if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
536
537 /* OTP reads require powered-up chip */
538 priv->cfg->ops->lib->apm_ops.init(priv);
539
536 ret = iwl_init_otp_access(priv); 540 ret = iwl_init_otp_access(priv);
537 if (ret) { 541 if (ret) {
538 IWL_ERR(priv, "Failed to initialize OTP access.\n"); 542 IWL_ERR(priv, "Failed to initialize OTP access.\n");
@@ -563,6 +567,13 @@ int iwl_eeprom_init(struct iwl_priv *priv)
563 e[cache_addr / 2] = eeprom_data; 567 e[cache_addr / 2] = eeprom_data;
564 cache_addr += sizeof(u16); 568 cache_addr += sizeof(u16);
565 } 569 }
570
571 /*
572 * Now that OTP reads are complete, reset chip to save
573 * power until we load uCode during "up".
574 */
575 priv->cfg->ops->lib->apm_ops.stop(priv);
576
566 } else { 577 } else {
567 /* eeprom is an array of 16bit values */ 578 /* eeprom is an array of 16bit values */
568 for (addr = 0; addr < sz; addr += sizeof(u16)) { 579 for (addr = 0; addr < sz; addr += sizeof(u16)) {
diff --git a/drivers/net/wireless/iwlwifi/iwl-hcmd.c b/drivers/net/wireless/iwlwifi/iwl-hcmd.c
index f2a60dc4109f..905645d15a9b 100644
--- a/drivers/net/wireless/iwlwifi/iwl-hcmd.c
+++ b/drivers/net/wireless/iwlwifi/iwl-hcmd.c
@@ -55,6 +55,8 @@ const char *get_cmd_string(u8 cmd)
55 IWL_CMD(REPLY_LEDS_CMD); 55 IWL_CMD(REPLY_LEDS_CMD);
56 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD); 56 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
57 IWL_CMD(COEX_PRIORITY_TABLE_CMD); 57 IWL_CMD(COEX_PRIORITY_TABLE_CMD);
58 IWL_CMD(COEX_MEDIUM_NOTIFICATION);
59 IWL_CMD(COEX_EVENT_CMD);
58 IWL_CMD(RADAR_NOTIFICATION); 60 IWL_CMD(RADAR_NOTIFICATION);
59 IWL_CMD(REPLY_QUIET_CMD); 61 IWL_CMD(REPLY_QUIET_CMD);
60 IWL_CMD(REPLY_CHANNEL_SWITCH); 62 IWL_CMD(REPLY_CHANNEL_SWITCH);
diff --git a/drivers/net/wireless/iwlwifi/iwl-scan.c b/drivers/net/wireless/iwlwifi/iwl-scan.c
index 4fca65a2fe9c..1eb0d0bf1fe4 100644
--- a/drivers/net/wireless/iwlwifi/iwl-scan.c
+++ b/drivers/net/wireless/iwlwifi/iwl-scan.c
@@ -401,6 +401,7 @@ void iwl_init_scan_params(struct iwl_priv *priv)
401 if (!priv->scan_tx_ant[IEEE80211_BAND_2GHZ]) 401 if (!priv->scan_tx_ant[IEEE80211_BAND_2GHZ])
402 priv->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx; 402 priv->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
403} 403}
404EXPORT_SYMBOL(iwl_init_scan_params);
404 405
405static int iwl_scan_initiate(struct iwl_priv *priv) 406static int iwl_scan_initiate(struct iwl_priv *priv)
406{ 407{
diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.c b/drivers/net/wireless/iwlwifi/iwl-sta.c
index dc74c16d36a8..eba36f737388 100644
--- a/drivers/net/wireless/iwlwifi/iwl-sta.c
+++ b/drivers/net/wireless/iwlwifi/iwl-sta.c
@@ -182,6 +182,11 @@ static void iwl_set_ht_add_station(struct iwl_priv *priv, u8 index,
182 goto done; 182 goto done;
183 183
184 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2; 184 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2;
185 IWL_DEBUG_ASSOC(priv, "spatial multiplexing power save mode: %s\n",
186 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_STATIC) ?
187 "static" :
188 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_DYNAMIC) ?
189 "dynamic" : "disabled");
185 190
186 sta_flags = priv->stations[index].sta.station_flags; 191 sta_flags = priv->stations[index].sta.station_flags;
187 192
@@ -1012,7 +1017,7 @@ int iwl_rxon_add_station(struct iwl_priv *priv, const u8 *addr, bool is_ap)
1012 */ 1017 */
1013 if (priv->current_ht_config.is_ht) { 1018 if (priv->current_ht_config.is_ht) {
1014 rcu_read_lock(); 1019 rcu_read_lock();
1015 sta = ieee80211_find_sta(priv->hw, addr); 1020 sta = ieee80211_find_sta(priv->vif, addr);
1016 if (sta) { 1021 if (sta) {
1017 memcpy(&ht_config, &sta->ht_cap, sizeof(ht_config)); 1022 memcpy(&ht_config, &sta->ht_cap, sizeof(ht_config));
1018 cur_ht_config = &ht_config; 1023 cur_ht_config = &ht_config;
@@ -1030,6 +1035,68 @@ int iwl_rxon_add_station(struct iwl_priv *priv, const u8 *addr, bool is_ap)
1030EXPORT_SYMBOL(iwl_rxon_add_station); 1035EXPORT_SYMBOL(iwl_rxon_add_station);
1031 1036
1032/** 1037/**
1038 * iwl_sta_init_bcast_lq - Initialize a bcast station's hardware rate table
1039 *
1040 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
1041 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
1042 * which requires station table entry to exist).
1043 */
1044static void iwl_sta_init_bcast_lq(struct iwl_priv *priv)
1045{
1046 int i, r;
1047 struct iwl_link_quality_cmd link_cmd = {
1048 .reserved1 = 0,
1049 };
1050 u32 rate_flags;
1051
1052 /* Set up the rate scaling to start at selected rate, fall back
1053 * all the way down to 1M in IEEE order, and then spin on 1M */
1054 if (priv->band == IEEE80211_BAND_5GHZ)
1055 r = IWL_RATE_6M_INDEX;
1056 else
1057 r = IWL_RATE_1M_INDEX;
1058
1059 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
1060 rate_flags = 0;
1061 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
1062 rate_flags |= RATE_MCS_CCK_MSK;
1063
1064 rate_flags |= first_antenna(priv->hw_params.valid_tx_ant) <<
1065 RATE_MCS_ANT_POS;
1066
1067 link_cmd.rs_table[i].rate_n_flags =
1068 iwl_hw_set_rate_n_flags(iwl_rates[r].plcp, rate_flags);
1069 r = iwl_get_prev_ieee_rate(r);
1070 }
1071
1072 link_cmd.general_params.single_stream_ant_msk =
1073 first_antenna(priv->hw_params.valid_tx_ant);
1074 link_cmd.general_params.dual_stream_ant_msk = 3;
1075 link_cmd.agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
1076 link_cmd.agg_params.agg_time_limit =
1077 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
1078
1079 /* Update the rate scaling for control frame Tx to AP */
1080 link_cmd.sta_id = priv->hw_params.bcast_sta_id;
1081
1082 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
1083 sizeof(link_cmd), &link_cmd, NULL);
1084}
1085
1086
1087/**
1088 * iwl_add_bcast_station - add broadcast station into station table.
1089 */
1090void iwl_add_bcast_station(struct iwl_priv *priv)
1091{
1092 iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL);
1093
1094 /* Set up default rate scaling table in device's station table */
1095 iwl_sta_init_bcast_lq(priv);
1096}
1097EXPORT_SYMBOL(iwl_add_bcast_station);
1098
1099/**
1033 * iwl_get_sta_id - Find station's index within station table 1100 * iwl_get_sta_id - Find station's index within station table
1034 * 1101 *
1035 * If new IBSS station, create new entry in station table 1102 * If new IBSS station, create new entry in station table
diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.h b/drivers/net/wireless/iwlwifi/iwl-sta.h
index 6deebade6361..1c382de80d49 100644
--- a/drivers/net/wireless/iwlwifi/iwl-sta.h
+++ b/drivers/net/wireless/iwlwifi/iwl-sta.h
@@ -52,6 +52,7 @@ void iwl_update_tkip_key(struct iwl_priv *priv,
52 const u8 *addr, u32 iv32, u16 *phase1key); 52 const u8 *addr, u32 iv32, u16 *phase1key);
53 53
54int iwl_rxon_add_station(struct iwl_priv *priv, const u8 *addr, bool is_ap); 54int iwl_rxon_add_station(struct iwl_priv *priv, const u8 *addr, bool is_ap);
55void iwl_add_bcast_station(struct iwl_priv *priv);
55int iwl_remove_station(struct iwl_priv *priv, const u8 *addr, bool is_ap); 56int iwl_remove_station(struct iwl_priv *priv, const u8 *addr, bool is_ap);
56void iwl_clear_stations_table(struct iwl_priv *priv); 57void iwl_clear_stations_table(struct iwl_priv *priv);
57int iwl_get_free_ucode_key_index(struct iwl_priv *priv); 58int iwl_get_free_ucode_key_index(struct iwl_priv *priv);
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c
index 8ae4c9b614e7..05e75109d842 100644
--- a/drivers/net/wireless/iwlwifi/iwl-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-tx.c
@@ -979,7 +979,8 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
979 !(cmd->flags & CMD_SIZE_HUGE)); 979 !(cmd->flags & CMD_SIZE_HUGE));
980 980
981 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { 981 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
982 IWL_DEBUG_INFO(priv, "Not sending command - RF/CT KILL\n"); 982 IWL_WARN(priv, "Not sending command - %s KILL\n",
983 iwl_is_rfkill(priv) ? "RF" : "CT");
983 return -EIO; 984 return -EIO;
984 } 985 }
985 986
@@ -1121,11 +1122,6 @@ static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1121 return; 1122 return;
1122 } 1123 }
1123 1124
1124 pci_unmap_single(priv->pci_dev,
1125 pci_unmap_addr(&txq->meta[cmd_idx], mapping),
1126 pci_unmap_len(&txq->meta[cmd_idx], len),
1127 PCI_DMA_BIDIRECTIONAL);
1128
1129 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; 1125 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1130 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { 1126 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1131 1127
@@ -1173,6 +1169,11 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1173 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; 1169 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1174 meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index]; 1170 meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index];
1175 1171
1172 pci_unmap_single(priv->pci_dev,
1173 pci_unmap_addr(meta, mapping),
1174 pci_unmap_len(meta, len),
1175 PCI_DMA_BIDIRECTIONAL);
1176
1176 /* Input error checking is done when commands are added to queue. */ 1177 /* Input error checking is done when commands are added to queue. */
1177 if (meta->flags & CMD_WANT_SKB) { 1178 if (meta->flags & CMD_WANT_SKB) {
1178 meta->source->reply_page = (unsigned long)rxb_addr(rxb); 1179 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index bfd7f497157f..23b31e6dcacd 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -2160,6 +2160,14 @@ static int iwl3945_read_ucode(struct iwl_priv *priv)
2160 IWL_UCODE_API(priv->ucode_ver), 2160 IWL_UCODE_API(priv->ucode_ver),
2161 IWL_UCODE_SERIAL(priv->ucode_ver)); 2161 IWL_UCODE_SERIAL(priv->ucode_ver));
2162 2162
2163 snprintf(priv->hw->wiphy->fw_version,
2164 sizeof(priv->hw->wiphy->fw_version),
2165 "%u.%u.%u.%u",
2166 IWL_UCODE_MAJOR(priv->ucode_ver),
2167 IWL_UCODE_MINOR(priv->ucode_ver),
2168 IWL_UCODE_API(priv->ucode_ver),
2169 IWL_UCODE_SERIAL(priv->ucode_ver));
2170
2163 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", 2171 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2164 priv->ucode_ver); 2172 priv->ucode_ver);
2165 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", 2173 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
@@ -3992,13 +4000,6 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
3992 */ 4000 */
3993 spin_lock_init(&priv->reg_lock); 4001 spin_lock_init(&priv->reg_lock);
3994 4002
3995 /* amp init */
3996 err = priv->cfg->ops->lib->apm_ops.init(priv);
3997 if (err < 0) {
3998 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
3999 goto out_iounmap;
4000 }
4001
4002 /*********************** 4003 /***********************
4003 * 4. Read EEPROM 4004 * 4. Read EEPROM
4004 * ********************/ 4005 * ********************/
diff --git a/drivers/net/wireless/iwmc3200wifi/Kconfig b/drivers/net/wireless/iwmc3200wifi/Kconfig
index 9606b3100fde..b9d34a766964 100644
--- a/drivers/net/wireless/iwmc3200wifi/Kconfig
+++ b/drivers/net/wireless/iwmc3200wifi/Kconfig
@@ -1,6 +1,6 @@
1config IWM 1config IWM
2 tristate "Intel Wireless Multicomm 3200 WiFi driver" 2 tristate "Intel Wireless Multicomm 3200 WiFi driver"
3 depends on MMC && WLAN_80211 && EXPERIMENTAL 3 depends on MMC && EXPERIMENTAL
4 depends on CFG80211 4 depends on CFG80211
5 select FW_LOADER 5 select FW_LOADER
6 select IWMC3200TOP 6 select IWMC3200TOP
diff --git a/drivers/net/wireless/libertas/Kconfig b/drivers/net/wireless/libertas/Kconfig
index 8f8d75b61ea9..30aa9d48d67e 100644
--- a/drivers/net/wireless/libertas/Kconfig
+++ b/drivers/net/wireless/libertas/Kconfig
@@ -1,6 +1,6 @@
1config LIBERTAS 1config LIBERTAS
2 tristate "Marvell 8xxx Libertas WLAN driver support" 2 tristate "Marvell 8xxx Libertas WLAN driver support"
3 depends on WLAN_80211 && CFG80211 3 depends on CFG80211
4 select WIRELESS_EXT 4 select WIRELESS_EXT
5 select WEXT_SPY 5 select WEXT_SPY
6 select LIB80211 6 select LIB80211
diff --git a/drivers/net/wireless/libertas/if_spi.c b/drivers/net/wireless/libertas/if_spi.c
index 30d9d0ea28eb..d6a48dd3652c 100644
--- a/drivers/net/wireless/libertas/if_spi.c
+++ b/drivers/net/wireless/libertas/if_spi.c
@@ -32,12 +32,6 @@
32#include "dev.h" 32#include "dev.h"
33#include "if_spi.h" 33#include "if_spi.h"
34 34
35struct if_spi_packet {
36 struct list_head list;
37 u16 blen;
38 u8 buffer[0] __attribute__((aligned(4)));
39};
40
41struct if_spi_card { 35struct if_spi_card {
42 struct spi_device *spi; 36 struct spi_device *spi;
43 struct lbs_private *priv; 37 struct lbs_private *priv;
@@ -66,33 +60,10 @@ struct if_spi_card {
66 struct semaphore spi_thread_terminated; 60 struct semaphore spi_thread_terminated;
67 61
68 u8 cmd_buffer[IF_SPI_CMD_BUF_SIZE]; 62 u8 cmd_buffer[IF_SPI_CMD_BUF_SIZE];
69
70 /* A buffer of incoming packets from libertas core.
71 * Since we can't sleep in hw_host_to_card, we have to buffer
72 * them. */
73 struct list_head cmd_packet_list;
74 struct list_head data_packet_list;
75
76 /* Protects cmd_packet_list and data_packet_list */
77 spinlock_t buffer_lock;
78}; 63};
79 64
80static void free_if_spi_card(struct if_spi_card *card) 65static void free_if_spi_card(struct if_spi_card *card)
81{ 66{
82 struct list_head *cursor, *next;
83 struct if_spi_packet *packet;
84
85 BUG_ON(card->run_thread);
86 list_for_each_safe(cursor, next, &card->cmd_packet_list) {
87 packet = container_of(cursor, struct if_spi_packet, list);
88 list_del(&packet->list);
89 kfree(packet);
90 }
91 list_for_each_safe(cursor, next, &card->data_packet_list) {
92 packet = container_of(cursor, struct if_spi_packet, list);
93 list_del(&packet->list);
94 kfree(packet);
95 }
96 spi_set_drvdata(card->spi, NULL); 67 spi_set_drvdata(card->spi, NULL);
97 kfree(card); 68 kfree(card);
98} 69}
@@ -774,40 +745,6 @@ out:
774 return err; 745 return err;
775} 746}
776 747
777/* Move data or a command from the host to the card. */
778static void if_spi_h2c(struct if_spi_card *card,
779 struct if_spi_packet *packet, int type)
780{
781 int err = 0;
782 u16 int_type, port_reg;
783
784 switch (type) {
785 case MVMS_DAT:
786 int_type = IF_SPI_CIC_TX_DOWNLOAD_OVER;
787 port_reg = IF_SPI_DATA_RDWRPORT_REG;
788 break;
789 case MVMS_CMD:
790 int_type = IF_SPI_CIC_CMD_DOWNLOAD_OVER;
791 port_reg = IF_SPI_CMD_RDWRPORT_REG;
792 break;
793 default:
794 lbs_pr_err("can't transfer buffer of type %d\n", type);
795 err = -EINVAL;
796 goto out;
797 }
798
799 /* Write the data to the card */
800 err = spu_write(card, port_reg, packet->buffer, packet->blen);
801 if (err)
802 goto out;
803
804out:
805 kfree(packet);
806
807 if (err)
808 lbs_pr_err("%s: error %d\n", __func__, err);
809}
810
811/* Inform the host about a card event */ 748/* Inform the host about a card event */
812static void if_spi_e2h(struct if_spi_card *card) 749static void if_spi_e2h(struct if_spi_card *card)
813{ 750{
@@ -837,8 +774,6 @@ static int lbs_spi_thread(void *data)
837 int err; 774 int err;
838 struct if_spi_card *card = data; 775 struct if_spi_card *card = data;
839 u16 hiStatus; 776 u16 hiStatus;
840 unsigned long flags;
841 struct if_spi_packet *packet;
842 777
843 while (1) { 778 while (1) {
844 /* Wait to be woken up by one of two things. First, our ISR 779 /* Wait to be woken up by one of two things. First, our ISR
@@ -877,43 +812,9 @@ static int lbs_spi_thread(void *data)
877 if (hiStatus & IF_SPI_HIST_CMD_DOWNLOAD_RDY || 812 if (hiStatus & IF_SPI_HIST_CMD_DOWNLOAD_RDY ||
878 (card->priv->psstate != PS_STATE_FULL_POWER && 813 (card->priv->psstate != PS_STATE_FULL_POWER &&
879 (hiStatus & IF_SPI_HIST_TX_DOWNLOAD_RDY))) { 814 (hiStatus & IF_SPI_HIST_TX_DOWNLOAD_RDY))) {
880 /* This means two things. First of all,
881 * if there was a previous command sent, the card has
882 * successfully received it.
883 * Secondly, it is now ready to download another
884 * command.
885 */
886 lbs_host_to_card_done(card->priv); 815 lbs_host_to_card_done(card->priv);
887
888 /* Do we have any command packets from the host to
889 * send? */
890 packet = NULL;
891 spin_lock_irqsave(&card->buffer_lock, flags);
892 if (!list_empty(&card->cmd_packet_list)) {
893 packet = (struct if_spi_packet *)(card->
894 cmd_packet_list.next);
895 list_del(&packet->list);
896 }
897 spin_unlock_irqrestore(&card->buffer_lock, flags);
898
899 if (packet)
900 if_spi_h2c(card, packet, MVMS_CMD);
901 } 816 }
902 if (hiStatus & IF_SPI_HIST_TX_DOWNLOAD_RDY) {
903 /* Do we have any data packets from the host to
904 * send? */
905 packet = NULL;
906 spin_lock_irqsave(&card->buffer_lock, flags);
907 if (!list_empty(&card->data_packet_list)) {
908 packet = (struct if_spi_packet *)(card->
909 data_packet_list.next);
910 list_del(&packet->list);
911 }
912 spin_unlock_irqrestore(&card->buffer_lock, flags);
913 817
914 if (packet)
915 if_spi_h2c(card, packet, MVMS_DAT);
916 }
917 if (hiStatus & IF_SPI_HIST_CARD_EVENT) 818 if (hiStatus & IF_SPI_HIST_CARD_EVENT)
918 if_spi_e2h(card); 819 if_spi_e2h(card);
919 820
@@ -942,40 +843,18 @@ static int if_spi_host_to_card(struct lbs_private *priv,
942 u8 type, u8 *buf, u16 nb) 843 u8 type, u8 *buf, u16 nb)
943{ 844{
944 int err = 0; 845 int err = 0;
945 unsigned long flags;
946 struct if_spi_card *card = priv->card; 846 struct if_spi_card *card = priv->card;
947 struct if_spi_packet *packet;
948 u16 blen;
949 847
950 lbs_deb_enter_args(LBS_DEB_SPI, "type %d, bytes %d", type, nb); 848 lbs_deb_enter_args(LBS_DEB_SPI, "type %d, bytes %d", type, nb);
951 849
952 if (nb == 0) { 850 nb = ALIGN(nb, 4);
953 lbs_pr_err("%s: invalid size requested: %d\n", __func__, nb);
954 err = -EINVAL;
955 goto out;
956 }
957 blen = ALIGN(nb, 4);
958 packet = kzalloc(sizeof(struct if_spi_packet) + blen, GFP_ATOMIC);
959 if (!packet) {
960 err = -ENOMEM;
961 goto out;
962 }
963 packet->blen = blen;
964 memcpy(packet->buffer, buf, nb);
965 memset(packet->buffer + nb, 0, blen - nb);
966 851
967 switch (type) { 852 switch (type) {
968 case MVMS_CMD: 853 case MVMS_CMD:
969 priv->dnld_sent = DNLD_CMD_SENT; 854 err = spu_write(card, IF_SPI_CMD_RDWRPORT_REG, buf, nb);
970 spin_lock_irqsave(&card->buffer_lock, flags);
971 list_add_tail(&packet->list, &card->cmd_packet_list);
972 spin_unlock_irqrestore(&card->buffer_lock, flags);
973 break; 855 break;
974 case MVMS_DAT: 856 case MVMS_DAT:
975 priv->dnld_sent = DNLD_DATA_SENT; 857 err = spu_write(card, IF_SPI_DATA_RDWRPORT_REG, buf, nb);
976 spin_lock_irqsave(&card->buffer_lock, flags);
977 list_add_tail(&packet->list, &card->data_packet_list);
978 spin_unlock_irqrestore(&card->buffer_lock, flags);
979 break; 858 break;
980 default: 859 default:
981 lbs_pr_err("can't transfer buffer of type %d", type); 860 lbs_pr_err("can't transfer buffer of type %d", type);
@@ -983,9 +862,6 @@ static int if_spi_host_to_card(struct lbs_private *priv,
983 break; 862 break;
984 } 863 }
985 864
986 /* Wake up the spi thread */
987 up(&card->spi_ready);
988out:
989 lbs_deb_leave_args(LBS_DEB_SPI, "err=%d", err); 865 lbs_deb_leave_args(LBS_DEB_SPI, "err=%d", err);
990 return err; 866 return err;
991} 867}
@@ -1062,9 +938,6 @@ static int __devinit if_spi_probe(struct spi_device *spi)
1062 938
1063 sema_init(&card->spi_ready, 0); 939 sema_init(&card->spi_ready, 0);
1064 sema_init(&card->spi_thread_terminated, 0); 940 sema_init(&card->spi_thread_terminated, 0);
1065 INIT_LIST_HEAD(&card->cmd_packet_list);
1066 INIT_LIST_HEAD(&card->data_packet_list);
1067 spin_lock_init(&card->buffer_lock);
1068 941
1069 /* Initialize the SPI Interface Unit */ 942 /* Initialize the SPI Interface Unit */
1070 err = spu_init(card, pdata->use_dummy_writes); 943 err = spu_init(card, pdata->use_dummy_writes);
@@ -1141,6 +1014,9 @@ static int __devinit if_spi_probe(struct spi_device *spi)
1141 goto terminate_thread; 1014 goto terminate_thread;
1142 } 1015 }
1143 1016
1017 /* poke the IRQ handler so that we don't miss the first interrupt */
1018 up(&card->spi_ready);
1019
1144 /* Start the card. 1020 /* Start the card.
1145 * This will call register_netdev, and we'll start 1021 * This will call register_netdev, and we'll start
1146 * getting interrupts... */ 1022 * getting interrupts... */
diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c
index 38cfd79e0590..fc4ec48eda12 100644
--- a/drivers/net/wireless/mac80211_hwsim.c
+++ b/drivers/net/wireless/mac80211_hwsim.c
@@ -284,7 +284,7 @@ struct mac80211_hwsim_data {
284 struct ieee80211_channel *channel; 284 struct ieee80211_channel *channel;
285 unsigned long beacon_int; /* in jiffies unit */ 285 unsigned long beacon_int; /* in jiffies unit */
286 unsigned int rx_filter; 286 unsigned int rx_filter;
287 int started; 287 bool started, idle;
288 struct timer_list beacon_timer; 288 struct timer_list beacon_timer;
289 enum ps_mode { 289 enum ps_mode {
290 PS_DISABLED, PS_ENABLED, PS_AUTO_POLL, PS_MANUAL_POLL 290 PS_DISABLED, PS_ENABLED, PS_AUTO_POLL, PS_MANUAL_POLL
@@ -365,6 +365,49 @@ static void mac80211_hwsim_monitor_rx(struct ieee80211_hw *hw,
365} 365}
366 366
367 367
368static void mac80211_hwsim_monitor_ack(struct ieee80211_hw *hw, const u8 *addr)
369{
370 struct mac80211_hwsim_data *data = hw->priv;
371 struct sk_buff *skb;
372 struct hwsim_radiotap_hdr *hdr;
373 u16 flags;
374 struct ieee80211_hdr *hdr11;
375
376 if (!netif_running(hwsim_mon))
377 return;
378
379 skb = dev_alloc_skb(100);
380 if (skb == NULL)
381 return;
382
383 hdr = (struct hwsim_radiotap_hdr *) skb_put(skb, sizeof(*hdr));
384 hdr->hdr.it_version = PKTHDR_RADIOTAP_VERSION;
385 hdr->hdr.it_pad = 0;
386 hdr->hdr.it_len = cpu_to_le16(sizeof(*hdr));
387 hdr->hdr.it_present = cpu_to_le32((1 << IEEE80211_RADIOTAP_FLAGS) |
388 (1 << IEEE80211_RADIOTAP_CHANNEL));
389 hdr->rt_flags = 0;
390 hdr->rt_rate = 0;
391 hdr->rt_channel = cpu_to_le16(data->channel->center_freq);
392 flags = IEEE80211_CHAN_2GHZ;
393 hdr->rt_chbitmask = cpu_to_le16(flags);
394
395 hdr11 = (struct ieee80211_hdr *) skb_put(skb, 10);
396 hdr11->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
397 IEEE80211_STYPE_ACK);
398 hdr11->duration_id = cpu_to_le16(0);
399 memcpy(hdr11->addr1, addr, ETH_ALEN);
400
401 skb->dev = hwsim_mon;
402 skb_set_mac_header(skb, 0);
403 skb->ip_summed = CHECKSUM_UNNECESSARY;
404 skb->pkt_type = PACKET_OTHERHOST;
405 skb->protocol = htons(ETH_P_802_2);
406 memset(skb->cb, 0, sizeof(skb->cb));
407 netif_rx(skb);
408}
409
410
368static bool hwsim_ps_rx_ok(struct mac80211_hwsim_data *data, 411static bool hwsim_ps_rx_ok(struct mac80211_hwsim_data *data,
369 struct sk_buff *skb) 412 struct sk_buff *skb)
370{ 413{
@@ -402,6 +445,12 @@ static bool mac80211_hwsim_tx_frame(struct ieee80211_hw *hw,
402 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 445 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
403 struct ieee80211_rx_status rx_status; 446 struct ieee80211_rx_status rx_status;
404 447
448 if (data->idle) {
449 printk(KERN_DEBUG "%s: Trying to TX when idle - reject\n",
450 wiphy_name(hw->wiphy));
451 return false;
452 }
453
405 memset(&rx_status, 0, sizeof(rx_status)); 454 memset(&rx_status, 0, sizeof(rx_status));
406 /* TODO: set mactime */ 455 /* TODO: set mactime */
407 rx_status.freq = data->channel->center_freq; 456 rx_status.freq = data->channel->center_freq;
@@ -428,7 +477,8 @@ static bool mac80211_hwsim_tx_frame(struct ieee80211_hw *hw,
428 if (data == data2) 477 if (data == data2)
429 continue; 478 continue;
430 479
431 if (!data2->started || !hwsim_ps_rx_ok(data2, skb) || 480 if (data2->idle || !data2->started ||
481 !hwsim_ps_rx_ok(data2, skb) ||
432 !data->channel || !data2->channel || 482 !data->channel || !data2->channel ||
433 data->channel->center_freq != data2->channel->center_freq || 483 data->channel->center_freq != data2->channel->center_freq ||
434 !(data->group & data2->group)) 484 !(data->group & data2->group))
@@ -464,6 +514,10 @@ static int mac80211_hwsim_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
464 } 514 }
465 515
466 ack = mac80211_hwsim_tx_frame(hw, skb); 516 ack = mac80211_hwsim_tx_frame(hw, skb);
517 if (ack && skb->len >= 16) {
518 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
519 mac80211_hwsim_monitor_ack(hw, hdr->addr2);
520 }
467 521
468 txi = IEEE80211_SKB_CB(skb); 522 txi = IEEE80211_SKB_CB(skb);
469 523
@@ -571,6 +625,8 @@ static int mac80211_hwsim_config(struct ieee80211_hw *hw, u32 changed)
571 !!(conf->flags & IEEE80211_CONF_IDLE), 625 !!(conf->flags & IEEE80211_CONF_IDLE),
572 !!(conf->flags & IEEE80211_CONF_PS)); 626 !!(conf->flags & IEEE80211_CONF_PS));
573 627
628 data->idle = !!(conf->flags & IEEE80211_CONF_IDLE);
629
574 data->channel = conf->channel; 630 data->channel = conf->channel;
575 if (!data->started || !data->beacon_int) 631 if (!data->started || !data->beacon_int)
576 del_timer(&data->beacon_timer); 632 del_timer(&data->beacon_timer);
@@ -1045,19 +1101,20 @@ static int __init init_mac80211_hwsim(void)
1045 sband->channels = data->channels_2ghz; 1101 sband->channels = data->channels_2ghz;
1046 sband->n_channels = 1102 sband->n_channels =
1047 ARRAY_SIZE(hwsim_channels_2ghz); 1103 ARRAY_SIZE(hwsim_channels_2ghz);
1104 sband->bitrates = data->rates;
1105 sband->n_bitrates = ARRAY_SIZE(hwsim_rates);
1048 break; 1106 break;
1049 case IEEE80211_BAND_5GHZ: 1107 case IEEE80211_BAND_5GHZ:
1050 sband->channels = data->channels_5ghz; 1108 sband->channels = data->channels_5ghz;
1051 sband->n_channels = 1109 sband->n_channels =
1052 ARRAY_SIZE(hwsim_channels_5ghz); 1110 ARRAY_SIZE(hwsim_channels_5ghz);
1111 sband->bitrates = data->rates + 4;
1112 sband->n_bitrates = ARRAY_SIZE(hwsim_rates) - 4;
1053 break; 1113 break;
1054 default: 1114 default:
1055 break; 1115 break;
1056 } 1116 }
1057 1117
1058 sband->bitrates = data->rates;
1059 sband->n_bitrates = ARRAY_SIZE(hwsim_rates);
1060
1061 sband->ht_cap.ht_supported = true; 1118 sband->ht_cap.ht_supported = true;
1062 sband->ht_cap.cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1119 sband->ht_cap.cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1063 IEEE80211_HT_CAP_GRN_FLD | 1120 IEEE80211_HT_CAP_GRN_FLD |
diff --git a/drivers/net/wireless/mwl8k.c b/drivers/net/wireless/mwl8k.c
index 746532ebe5a8..2ebfee4da3fa 100644
--- a/drivers/net/wireless/mwl8k.c
+++ b/drivers/net/wireless/mwl8k.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/sched.h>
15#include <linux/spinlock.h> 16#include <linux/spinlock.h>
16#include <linux/list.h> 17#include <linux/list.h>
17#include <linux/pci.h> 18#include <linux/pci.h>
@@ -27,18 +28,6 @@
27#define MWL8K_NAME KBUILD_MODNAME 28#define MWL8K_NAME KBUILD_MODNAME
28#define MWL8K_VERSION "0.10" 29#define MWL8K_VERSION "0.10"
29 30
30MODULE_DESCRIPTION(MWL8K_DESC);
31MODULE_VERSION(MWL8K_VERSION);
32MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
33MODULE_LICENSE("GPL");
34
35static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
36 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
37 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
38 { }
39};
40MODULE_DEVICE_TABLE(pci, mwl8k_table);
41
42/* Register definitions */ 31/* Register definitions */
43#define MWL8K_HIU_GEN_PTR 0x00000c10 32#define MWL8K_HIU_GEN_PTR 0x00000c10
44#define MWL8K_MODE_STA 0x0000005a 33#define MWL8K_MODE_STA 0x0000005a
@@ -88,72 +77,89 @@ MODULE_DEVICE_TABLE(pci, mwl8k_table);
88 MWL8K_A2H_INT_RX_READY | \ 77 MWL8K_A2H_INT_RX_READY | \
89 MWL8K_A2H_INT_TX_DONE) 78 MWL8K_A2H_INT_TX_DONE)
90 79
91/* WME stream classes */
92#define WME_AC_BE 0 /* best effort */
93#define WME_AC_BK 1 /* background */
94#define WME_AC_VI 2 /* video */
95#define WME_AC_VO 3 /* voice */
96
97#define MWL8K_RX_QUEUES 1 80#define MWL8K_RX_QUEUES 1
98#define MWL8K_TX_QUEUES 4 81#define MWL8K_TX_QUEUES 4
99 82
83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status);
88};
89
90struct mwl8k_device_info {
91 char *part_name;
92 char *helper_image;
93 char *fw_image;
94 struct rxd_ops *rxd_ops;
95 u16 modes;
96};
97
100struct mwl8k_rx_queue { 98struct mwl8k_rx_queue {
101 int rx_desc_count; 99 int rxd_count;
102 100
103 /* hw receives here */ 101 /* hw receives here */
104 int rx_head; 102 int head;
105 103
106 /* refill descs here */ 104 /* refill descs here */
107 int rx_tail; 105 int tail;
108 106
109 struct mwl8k_rx_desc *rx_desc_area; 107 void *rxd;
110 dma_addr_t rx_desc_dma; 108 dma_addr_t rxd_dma;
111 struct sk_buff **rx_skb; 109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
112}; 113};
113 114
114struct mwl8k_tx_queue { 115struct mwl8k_tx_queue {
115 /* hw transmits here */ 116 /* hw transmits here */
116 int tx_head; 117 int head;
117 118
118 /* sw appends here */ 119 /* sw appends here */
119 int tx_tail; 120 int tail;
120 121
121 struct ieee80211_tx_queue_stats tx_stats; 122 struct ieee80211_tx_queue_stats stats;
122 struct mwl8k_tx_desc *tx_desc_area; 123 struct mwl8k_tx_desc *txd;
123 dma_addr_t tx_desc_dma; 124 dma_addr_t txd_dma;
124 struct sk_buff **tx_skb; 125 struct sk_buff **skb;
125}; 126};
126 127
127/* Pointers to the firmware data and meta information about it. */ 128/* Pointers to the firmware data and meta information about it. */
128struct mwl8k_firmware { 129struct mwl8k_firmware {
129 /* Microcode */
130 struct firmware *ucode;
131
132 /* Boot helper code */ 130 /* Boot helper code */
133 struct firmware *helper; 131 struct firmware *helper;
132
133 /* Microcode */
134 struct firmware *ucode;
134}; 135};
135 136
136struct mwl8k_priv { 137struct mwl8k_priv {
138 void __iomem *sram;
137 void __iomem *regs; 139 void __iomem *regs;
138 struct ieee80211_hw *hw; 140 struct ieee80211_hw *hw;
139 141
140 struct pci_dev *pdev; 142 struct pci_dev *pdev;
141 u8 name[16]; 143
144 struct mwl8k_device_info *device_info;
145 bool ap_fw;
146 struct rxd_ops *rxd_ops;
142 147
143 /* firmware files and meta data */ 148 /* firmware files and meta data */
144 struct mwl8k_firmware fw; 149 struct mwl8k_firmware fw;
145 u32 part_num;
146 150
147 /* firmware access */ 151 /* firmware access */
148 struct mutex fw_mutex; 152 struct mutex fw_mutex;
149 struct task_struct *fw_mutex_owner; 153 struct task_struct *fw_mutex_owner;
150 int fw_mutex_depth; 154 int fw_mutex_depth;
151 struct completion *tx_wait;
152 struct completion *hostcmd_wait; 155 struct completion *hostcmd_wait;
153 156
154 /* lock held over TX and TX reap */ 157 /* lock held over TX and TX reap */
155 spinlock_t tx_lock; 158 spinlock_t tx_lock;
156 159
160 /* TX quiesce completion, protected by fw_mutex and tx_lock */
161 struct completion *tx_wait;
162
157 struct ieee80211_vif *vif; 163 struct ieee80211_vif *vif;
158 164
159 struct ieee80211_channel *current_channel; 165 struct ieee80211_channel *current_channel;
@@ -178,10 +184,11 @@ struct mwl8k_priv {
178 /* PHY parameters */ 184 /* PHY parameters */
179 struct ieee80211_supported_band band; 185 struct ieee80211_supported_band band;
180 struct ieee80211_channel channels[14]; 186 struct ieee80211_channel channels[14];
181 struct ieee80211_rate rates[12]; 187 struct ieee80211_rate rates[13];
182 188
183 bool radio_on; 189 bool radio_on;
184 bool radio_short_preamble; 190 bool radio_short_preamble;
191 bool sniffer_enabled;
185 bool wmm_enabled; 192 bool wmm_enabled;
186 193
187 /* XXX need to convert this to handle multiple interfaces */ 194 /* XXX need to convert this to handle multiple interfaces */
@@ -199,9 +206,6 @@ struct mwl8k_priv {
199 206
200 /* Tasklet to reclaim TX descriptors and buffers after tx */ 207 /* Tasklet to reclaim TX descriptors and buffers after tx */
201 struct tasklet_struct tx_reclaim_task; 208 struct tasklet_struct tx_reclaim_task;
202
203 /* Work thread to serialize configuration requests */
204 struct workqueue_struct *config_wq;
205}; 209};
206 210
207/* Per interface specific private data */ 211/* Per interface specific private data */
@@ -220,7 +224,7 @@ struct mwl8k_vif {
220 * Subset of supported legacy rates. 224 * Subset of supported legacy rates.
221 * Intersection of AP and STA supported rates. 225 * Intersection of AP and STA supported rates.
222 */ 226 */
223 struct ieee80211_rate legacy_rates[12]; 227 struct ieee80211_rate legacy_rates[13];
224 228
225 /* number of supported legacy rates */ 229 /* number of supported legacy rates */
226 u8 legacy_nrates; 230 u8 legacy_nrates;
@@ -252,9 +256,10 @@ static const struct ieee80211_rate mwl8k_rates[] = {
252 { .bitrate = 10, .hw_value = 2, }, 256 { .bitrate = 10, .hw_value = 2, },
253 { .bitrate = 20, .hw_value = 4, }, 257 { .bitrate = 20, .hw_value = 4, },
254 { .bitrate = 55, .hw_value = 11, }, 258 { .bitrate = 55, .hw_value = 11, },
259 { .bitrate = 110, .hw_value = 22, },
260 { .bitrate = 220, .hw_value = 44, },
255 { .bitrate = 60, .hw_value = 12, }, 261 { .bitrate = 60, .hw_value = 12, },
256 { .bitrate = 90, .hw_value = 18, }, 262 { .bitrate = 90, .hw_value = 18, },
257 { .bitrate = 110, .hw_value = 22, },
258 { .bitrate = 120, .hw_value = 24, }, 263 { .bitrate = 120, .hw_value = 24, },
259 { .bitrate = 180, .hw_value = 36, }, 264 { .bitrate = 180, .hw_value = 36, },
260 { .bitrate = 240, .hw_value = 48, }, 265 { .bitrate = 240, .hw_value = 48, },
@@ -270,10 +275,12 @@ static const struct ieee80211_rate mwl8k_rates[] = {
270/* Firmware command codes */ 275/* Firmware command codes */
271#define MWL8K_CMD_CODE_DNLD 0x0001 276#define MWL8K_CMD_CODE_DNLD 0x0001
272#define MWL8K_CMD_GET_HW_SPEC 0x0003 277#define MWL8K_CMD_GET_HW_SPEC 0x0003
278#define MWL8K_CMD_SET_HW_SPEC 0x0004
273#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010 279#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
274#define MWL8K_CMD_GET_STAT 0x0014 280#define MWL8K_CMD_GET_STAT 0x0014
275#define MWL8K_CMD_RADIO_CONTROL 0x001c 281#define MWL8K_CMD_RADIO_CONTROL 0x001c
276#define MWL8K_CMD_RF_TX_POWER 0x001e 282#define MWL8K_CMD_RF_TX_POWER 0x001e
283#define MWL8K_CMD_RF_ANTENNA 0x0020
277#define MWL8K_CMD_SET_PRE_SCAN 0x0107 284#define MWL8K_CMD_SET_PRE_SCAN 0x0107
278#define MWL8K_CMD_SET_POST_SCAN 0x0108 285#define MWL8K_CMD_SET_POST_SCAN 0x0108
279#define MWL8K_CMD_SET_RF_CHANNEL 0x010a 286#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
@@ -287,6 +294,7 @@ static const struct ieee80211_rate mwl8k_rates[] = {
287#define MWL8K_CMD_MIMO_CONFIG 0x0125 294#define MWL8K_CMD_MIMO_CONFIG 0x0125
288#define MWL8K_CMD_USE_FIXED_RATE 0x0126 295#define MWL8K_CMD_USE_FIXED_RATE 0x0126
289#define MWL8K_CMD_ENABLE_SNIFFER 0x0150 296#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
297#define MWL8K_CMD_SET_MAC_ADDR 0x0202
290#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203 298#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
291#define MWL8K_CMD_UPDATE_STADB 0x1123 299#define MWL8K_CMD_UPDATE_STADB 0x1123
292 300
@@ -299,10 +307,12 @@ static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
299 switch (cmd & ~0x8000) { 307 switch (cmd & ~0x8000) {
300 MWL8K_CMDNAME(CODE_DNLD); 308 MWL8K_CMDNAME(CODE_DNLD);
301 MWL8K_CMDNAME(GET_HW_SPEC); 309 MWL8K_CMDNAME(GET_HW_SPEC);
310 MWL8K_CMDNAME(SET_HW_SPEC);
302 MWL8K_CMDNAME(MAC_MULTICAST_ADR); 311 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
303 MWL8K_CMDNAME(GET_STAT); 312 MWL8K_CMDNAME(GET_STAT);
304 MWL8K_CMDNAME(RADIO_CONTROL); 313 MWL8K_CMDNAME(RADIO_CONTROL);
305 MWL8K_CMDNAME(RF_TX_POWER); 314 MWL8K_CMDNAME(RF_TX_POWER);
315 MWL8K_CMDNAME(RF_ANTENNA);
306 MWL8K_CMDNAME(SET_PRE_SCAN); 316 MWL8K_CMDNAME(SET_PRE_SCAN);
307 MWL8K_CMDNAME(SET_POST_SCAN); 317 MWL8K_CMDNAME(SET_POST_SCAN);
308 MWL8K_CMDNAME(SET_RF_CHANNEL); 318 MWL8K_CMDNAME(SET_RF_CHANNEL);
@@ -316,6 +326,7 @@ static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
316 MWL8K_CMDNAME(MIMO_CONFIG); 326 MWL8K_CMDNAME(MIMO_CONFIG);
317 MWL8K_CMDNAME(USE_FIXED_RATE); 327 MWL8K_CMDNAME(USE_FIXED_RATE);
318 MWL8K_CMDNAME(ENABLE_SNIFFER); 328 MWL8K_CMDNAME(ENABLE_SNIFFER);
329 MWL8K_CMDNAME(SET_MAC_ADDR);
319 MWL8K_CMDNAME(SET_RATEADAPT_MODE); 330 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
320 MWL8K_CMDNAME(UPDATE_STADB); 331 MWL8K_CMDNAME(UPDATE_STADB);
321 default: 332 default:
@@ -353,41 +364,35 @@ static void mwl8k_release_firmware(struct mwl8k_priv *priv)
353 364
354/* Request fw image */ 365/* Request fw image */
355static int mwl8k_request_fw(struct mwl8k_priv *priv, 366static int mwl8k_request_fw(struct mwl8k_priv *priv,
356 const char *fname, struct firmware **fw) 367 const char *fname, struct firmware **fw)
357{ 368{
358 /* release current image */ 369 /* release current image */
359 if (*fw != NULL) 370 if (*fw != NULL)
360 mwl8k_release_fw(fw); 371 mwl8k_release_fw(fw);
361 372
362 return request_firmware((const struct firmware **)fw, 373 return request_firmware((const struct firmware **)fw,
363 fname, &priv->pdev->dev); 374 fname, &priv->pdev->dev);
364} 375}
365 376
366static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num) 377static int mwl8k_request_firmware(struct mwl8k_priv *priv)
367{ 378{
368 u8 filename[64]; 379 struct mwl8k_device_info *di = priv->device_info;
369 int rc; 380 int rc;
370 381
371 priv->part_num = part_num; 382 if (di->helper_image != NULL) {
372 383 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
373 snprintf(filename, sizeof(filename), 384 if (rc) {
374 "mwl8k/helper_%u.fw", priv->part_num); 385 printk(KERN_ERR "%s: Error requesting helper "
375 386 "firmware file %s\n", pci_name(priv->pdev),
376 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper); 387 di->helper_image);
377 if (rc) { 388 return rc;
378 printk(KERN_ERR 389 }
379 "%s Error requesting helper firmware file %s\n",
380 pci_name(priv->pdev), filename);
381 return rc;
382 } 390 }
383 391
384 snprintf(filename, sizeof(filename), 392 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
385 "mwl8k/fmimage_%u.fw", priv->part_num);
386
387 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
388 if (rc) { 393 if (rc) {
389 printk(KERN_ERR "%s Error requesting firmware file %s\n", 394 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
390 pci_name(priv->pdev), filename); 395 pci_name(priv->pdev), di->fw_image);
391 mwl8k_release_fw(&priv->fw.helper); 396 mwl8k_release_fw(&priv->fw.helper);
392 return rc; 397 return rc;
393 } 398 }
@@ -434,6 +439,7 @@ mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
434 break; 439 break;
435 } 440 }
436 441
442 cond_resched();
437 udelay(1); 443 udelay(1);
438 } while (--loops); 444 } while (--loops);
439 445
@@ -542,43 +548,62 @@ static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
542 return rc; 548 return rc;
543} 549}
544 550
545static int mwl8k_load_firmware(struct mwl8k_priv *priv) 551static int mwl8k_load_firmware(struct ieee80211_hw *hw)
546{ 552{
547 int loops, rc; 553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
555 struct mwl8k_device_info *di = priv->device_info;
556 int rc;
557 int loops;
558
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
548 561
549 const u8 *ucode = priv->fw.ucode->data; 562 if (helper == NULL) {
550 size_t ucode_len = priv->fw.ucode->size; 563 printk(KERN_ERR "%s: helper image needed but none "
551 const u8 *helper = priv->fw.helper->data; 564 "given\n", pci_name(priv->pdev));
552 size_t helper_len = priv->fw.helper->size; 565 return -EINVAL;
566 }
553 567
554 if (!memcmp(ucode, "\x01\x00\x00\x00", 4)) { 568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
555 rc = mwl8k_load_fw_image(priv, helper, helper_len);
556 if (rc) { 569 if (rc) {
557 printk(KERN_ERR "%s: unable to load firmware " 570 printk(KERN_ERR "%s: unable to load firmware "
558 "helper image\n", pci_name(priv->pdev)); 571 "helper image\n", pci_name(priv->pdev));
559 return rc; 572 return rc;
560 } 573 }
561 msleep(1); 574 msleep(1);
562 575
563 rc = mwl8k_feed_fw_image(priv, ucode, ucode_len); 576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
564 } else { 577 } else {
565 rc = mwl8k_load_fw_image(priv, ucode, ucode_len); 578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
566 } 579 }
567 580
568 if (rc) { 581 if (rc) {
569 printk(KERN_ERR "%s: unable to load firmware data\n", 582 printk(KERN_ERR "%s: unable to load firmware image\n",
570 pci_name(priv->pdev)); 583 pci_name(priv->pdev));
571 return rc; 584 return rc;
572 } 585 }
573 586
574 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR); 587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
589 else
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
575 msleep(1); 591 msleep(1);
576 592
577 loops = 200000; 593 loops = 200000;
578 do { 594 do {
579 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE) 595 u32 ready_code;
580 == MWL8K_FWSTA_READY) 596
597 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
598 if (ready_code == MWL8K_FWAP_READY) {
599 priv->ap_fw = 1;
581 break; 600 break;
601 } else if (ready_code == MWL8K_FWSTA_READY) {
602 priv->ap_fw = 0;
603 break;
604 }
605
606 cond_resched();
582 udelay(1); 607 udelay(1);
583 } while (--loops); 608 } while (--loops);
584 609
@@ -605,7 +630,7 @@ struct ewc_ht_info {
605/* Peer Entry flags - used to define the type of the peer node */ 630/* Peer Entry flags - used to define the type of the peer node */
606#define MWL8K_PEER_TYPE_ACCESSPOINT 2 631#define MWL8K_PEER_TYPE_ACCESSPOINT 2
607 632
608#define MWL8K_IEEE_LEGACY_DATA_RATES 12 633#define MWL8K_IEEE_LEGACY_DATA_RATES 13
609#define MWL8K_MCS_BITMAP_SIZE 16 634#define MWL8K_MCS_BITMAP_SIZE 16
610 635
611struct peer_capability_info { 636struct peer_capability_info {
@@ -731,16 +756,96 @@ static inline void mwl8k_add_dma_header(struct sk_buff *skb)
731 756
732 757
733/* 758/*
734 * Packet reception. 759 * Packet reception for 88w8366.
735 */ 760 */
736#define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02 761struct mwl8k_rxd_8366 {
762 __le16 pkt_len;
763 __u8 sq2;
764 __u8 rate;
765 __le32 pkt_phys_addr;
766 __le32 next_rxd_phys_addr;
767 __le16 qos_control;
768 __le16 htsig2;
769 __le32 hw_rssi_info;
770 __le32 hw_noise_floor_info;
771 __u8 noise_floor;
772 __u8 pad0[3];
773 __u8 rssi;
774 __u8 rx_status;
775 __u8 channel;
776 __u8 rx_ctrl;
777} __attribute__((packed));
737 778
738struct mwl8k_rx_desc { 779#define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
780
781static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
782{
783 struct mwl8k_rxd_8366 *rxd = _rxd;
784
785 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
786 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
787}
788
789static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
790{
791 struct mwl8k_rxd_8366 *rxd = _rxd;
792
793 rxd->pkt_len = cpu_to_le16(len);
794 rxd->pkt_phys_addr = cpu_to_le32(addr);
795 wmb();
796 rxd->rx_ctrl = 0;
797}
798
799static int
800mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status)
801{
802 struct mwl8k_rxd_8366 *rxd = _rxd;
803
804 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
805 return -1;
806 rmb();
807
808 memset(status, 0, sizeof(*status));
809
810 status->signal = -rxd->rssi;
811 status->noise = -rxd->noise_floor;
812
813 if (rxd->rate & 0x80) {
814 status->flag |= RX_FLAG_HT;
815 status->rate_idx = rxd->rate & 0x7f;
816 } else {
817 int i;
818
819 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
820 if (mwl8k_rates[i].hw_value == rxd->rate) {
821 status->rate_idx = i;
822 break;
823 }
824 }
825 }
826
827 status->band = IEEE80211_BAND_2GHZ;
828 status->freq = ieee80211_channel_to_frequency(rxd->channel);
829
830 return le16_to_cpu(rxd->pkt_len);
831}
832
833static struct rxd_ops rxd_8366_ops = {
834 .rxd_size = sizeof(struct mwl8k_rxd_8366),
835 .rxd_init = mwl8k_rxd_8366_init,
836 .rxd_refill = mwl8k_rxd_8366_refill,
837 .rxd_process = mwl8k_rxd_8366_process,
838};
839
840/*
841 * Packet reception for 88w8687.
842 */
843struct mwl8k_rxd_8687 {
739 __le16 pkt_len; 844 __le16 pkt_len;
740 __u8 link_quality; 845 __u8 link_quality;
741 __u8 noise_level; 846 __u8 noise_level;
742 __le32 pkt_phys_addr; 847 __le32 pkt_phys_addr;
743 __le32 next_rx_desc_phys_addr; 848 __le32 next_rxd_phys_addr;
744 __le16 qos_control; 849 __le16 qos_control;
745 __le16 rate_info; 850 __le16 rate_info;
746 __le32 pad0[4]; 851 __le32 pad0[4];
@@ -752,6 +857,76 @@ struct mwl8k_rx_desc {
752 __u8 pad2[2]; 857 __u8 pad2[2];
753} __attribute__((packed)); 858} __attribute__((packed));
754 859
860#define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
861#define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
862#define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
863#define MWL8K_8687_RATE_INFO_40MHZ 0x0004
864#define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
865#define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
866
867#define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
868
869static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
870{
871 struct mwl8k_rxd_8687 *rxd = _rxd;
872
873 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
874 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
875}
876
877static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
878{
879 struct mwl8k_rxd_8687 *rxd = _rxd;
880
881 rxd->pkt_len = cpu_to_le16(len);
882 rxd->pkt_phys_addr = cpu_to_le32(addr);
883 wmb();
884 rxd->rx_ctrl = 0;
885}
886
887static int
888mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status)
889{
890 struct mwl8k_rxd_8687 *rxd = _rxd;
891 u16 rate_info;
892
893 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
894 return -1;
895 rmb();
896
897 rate_info = le16_to_cpu(rxd->rate_info);
898
899 memset(status, 0, sizeof(*status));
900
901 status->signal = -rxd->rssi;
902 status->noise = -rxd->noise_level;
903 status->qual = rxd->link_quality;
904 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
905 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
906
907 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
908 status->flag |= RX_FLAG_SHORTPRE;
909 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
910 status->flag |= RX_FLAG_40MHZ;
911 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
912 status->flag |= RX_FLAG_SHORT_GI;
913 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
914 status->flag |= RX_FLAG_HT;
915
916 status->band = IEEE80211_BAND_2GHZ;
917 status->freq = ieee80211_channel_to_frequency(rxd->channel);
918
919 return le16_to_cpu(rxd->pkt_len);
920}
921
922static struct rxd_ops rxd_8687_ops = {
923 .rxd_size = sizeof(struct mwl8k_rxd_8687),
924 .rxd_init = mwl8k_rxd_8687_init,
925 .rxd_refill = mwl8k_rxd_8687_refill,
926 .rxd_process = mwl8k_rxd_8687_process,
927};
928
929
755#define MWL8K_RX_DESCS 256 930#define MWL8K_RX_DESCS 256
756#define MWL8K_RX_MAXSZ 3800 931#define MWL8K_RX_MAXSZ 3800
757 932
@@ -762,43 +937,44 @@ static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
762 int size; 937 int size;
763 int i; 938 int i;
764 939
765 rxq->rx_desc_count = 0; 940 rxq->rxd_count = 0;
766 rxq->rx_head = 0; 941 rxq->head = 0;
767 rxq->rx_tail = 0; 942 rxq->tail = 0;
768 943
769 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc); 944 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
770 945
771 rxq->rx_desc_area = 946 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
772 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma); 947 if (rxq->rxd == NULL) {
773 if (rxq->rx_desc_area == NULL) {
774 printk(KERN_ERR "%s: failed to alloc RX descriptors\n", 948 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
775 priv->name); 949 wiphy_name(hw->wiphy));
776 return -ENOMEM; 950 return -ENOMEM;
777 } 951 }
778 memset(rxq->rx_desc_area, 0, size); 952 memset(rxq->rxd, 0, size);
779 953
780 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS * 954 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
781 sizeof(*rxq->rx_skb), GFP_KERNEL); 955 if (rxq->buf == NULL) {
782 if (rxq->rx_skb == NULL) {
783 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n", 956 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
784 priv->name); 957 wiphy_name(hw->wiphy));
785 pci_free_consistent(priv->pdev, size, 958 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
786 rxq->rx_desc_area, rxq->rx_desc_dma);
787 return -ENOMEM; 959 return -ENOMEM;
788 } 960 }
789 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb)); 961 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
790 962
791 for (i = 0; i < MWL8K_RX_DESCS; i++) { 963 for (i = 0; i < MWL8K_RX_DESCS; i++) {
792 struct mwl8k_rx_desc *rx_desc; 964 int desc_size;
965 void *rxd;
793 int nexti; 966 int nexti;
967 dma_addr_t next_dma_addr;
794 968
795 rx_desc = rxq->rx_desc_area + i; 969 desc_size = priv->rxd_ops->rxd_size;
796 nexti = (i + 1) % MWL8K_RX_DESCS; 970 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
797 971
798 rx_desc->next_rx_desc_phys_addr = 972 nexti = i + 1;
799 cpu_to_le32(rxq->rx_desc_dma 973 if (nexti == MWL8K_RX_DESCS)
800 + nexti * sizeof(*rx_desc)); 974 nexti = 0;
801 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST; 975 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
976
977 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
802 } 978 }
803 979
804 return 0; 980 return 0;
@@ -811,27 +987,28 @@ static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
811 int refilled; 987 int refilled;
812 988
813 refilled = 0; 989 refilled = 0;
814 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) { 990 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
815 struct sk_buff *skb; 991 struct sk_buff *skb;
992 dma_addr_t addr;
816 int rx; 993 int rx;
994 void *rxd;
817 995
818 skb = dev_alloc_skb(MWL8K_RX_MAXSZ); 996 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
819 if (skb == NULL) 997 if (skb == NULL)
820 break; 998 break;
821 999
822 rxq->rx_desc_count++; 1000 addr = pci_map_single(priv->pdev, skb->data,
823 1001 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
824 rx = rxq->rx_tail;
825 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
826 1002
827 rxq->rx_desc_area[rx].pkt_phys_addr = 1003 rxq->rxd_count++;
828 cpu_to_le32(pci_map_single(priv->pdev, skb->data, 1004 rx = rxq->tail++;
829 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE)); 1005 if (rxq->tail == MWL8K_RX_DESCS)
1006 rxq->tail = 0;
1007 rxq->buf[rx].skb = skb;
1008 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
830 1009
831 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ); 1010 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
832 rxq->rx_skb[rx] = skb; 1011 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
833 wmb();
834 rxq->rx_desc_area[rx].rx_ctrl = 0;
835 1012
836 refilled++; 1013 refilled++;
837 } 1014 }
@@ -847,24 +1024,24 @@ static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
847 int i; 1024 int i;
848 1025
849 for (i = 0; i < MWL8K_RX_DESCS; i++) { 1026 for (i = 0; i < MWL8K_RX_DESCS; i++) {
850 if (rxq->rx_skb[i] != NULL) { 1027 if (rxq->buf[i].skb != NULL) {
851 unsigned long addr; 1028 pci_unmap_single(priv->pdev,
852 1029 pci_unmap_addr(&rxq->buf[i], dma),
853 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr); 1030 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
854 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ, 1031 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
855 PCI_DMA_FROMDEVICE); 1032
856 kfree_skb(rxq->rx_skb[i]); 1033 kfree_skb(rxq->buf[i].skb);
857 rxq->rx_skb[i] = NULL; 1034 rxq->buf[i].skb = NULL;
858 } 1035 }
859 } 1036 }
860 1037
861 kfree(rxq->rx_skb); 1038 kfree(rxq->buf);
862 rxq->rx_skb = NULL; 1039 rxq->buf = NULL;
863 1040
864 pci_free_consistent(priv->pdev, 1041 pci_free_consistent(priv->pdev,
865 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc), 1042 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
866 rxq->rx_desc_area, rxq->rx_desc_dma); 1043 rxq->rxd, rxq->rxd_dma);
867 rxq->rx_desc_area = NULL; 1044 rxq->rxd = NULL;
868} 1045}
869 1046
870 1047
@@ -880,9 +1057,11 @@ mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
880 !compare_ether_addr(wh->addr3, priv->capture_bssid); 1057 !compare_ether_addr(wh->addr3, priv->capture_bssid);
881} 1058}
882 1059
883static inline void mwl8k_save_beacon(struct mwl8k_priv *priv, 1060static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
884 struct sk_buff *skb) 1061 struct sk_buff *skb)
885{ 1062{
1063 struct mwl8k_priv *priv = hw->priv;
1064
886 priv->capture_beacon = false; 1065 priv->capture_beacon = false;
887 memset(priv->capture_bssid, 0, ETH_ALEN); 1066 memset(priv->capture_bssid, 0, ETH_ALEN);
888 1067
@@ -893,8 +1072,7 @@ static inline void mwl8k_save_beacon(struct mwl8k_priv *priv,
893 */ 1072 */
894 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC); 1073 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
895 if (priv->beacon_skb != NULL) 1074 if (priv->beacon_skb != NULL)
896 queue_work(priv->config_wq, 1075 ieee80211_queue_work(hw, &priv->finalize_join_worker);
897 &priv->finalize_join_worker);
898} 1076}
899 1077
900static int rxq_process(struct ieee80211_hw *hw, int index, int limit) 1078static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
@@ -904,53 +1082,46 @@ static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
904 int processed; 1082 int processed;
905 1083
906 processed = 0; 1084 processed = 0;
907 while (rxq->rx_desc_count && limit--) { 1085 while (rxq->rxd_count && limit--) {
908 struct mwl8k_rx_desc *rx_desc;
909 struct sk_buff *skb; 1086 struct sk_buff *skb;
1087 void *rxd;
1088 int pkt_len;
910 struct ieee80211_rx_status status; 1089 struct ieee80211_rx_status status;
911 unsigned long addr;
912 struct ieee80211_hdr *wh;
913 1090
914 rx_desc = rxq->rx_desc_area + rxq->rx_head; 1091 skb = rxq->buf[rxq->head].skb;
915 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST)) 1092 if (skb == NULL)
916 break; 1093 break;
917 rmb();
918 1094
919 skb = rxq->rx_skb[rxq->rx_head]; 1095 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
920 if (skb == NULL) 1096
1097 pkt_len = priv->rxd_ops->rxd_process(rxd, &status);
1098 if (pkt_len < 0)
921 break; 1099 break;
922 rxq->rx_skb[rxq->rx_head] = NULL;
923 1100
924 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS; 1101 rxq->buf[rxq->head].skb = NULL;
925 rxq->rx_desc_count--;
926 1102
927 addr = le32_to_cpu(rx_desc->pkt_phys_addr); 1103 pci_unmap_single(priv->pdev,
928 pci_unmap_single(priv->pdev, addr, 1104 pci_unmap_addr(&rxq->buf[rxq->head], dma),
929 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); 1105 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1106 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
930 1107
931 skb_put(skb, le16_to_cpu(rx_desc->pkt_len)); 1108 rxq->head++;
932 mwl8k_remove_dma_header(skb); 1109 if (rxq->head == MWL8K_RX_DESCS)
1110 rxq->head = 0;
1111
1112 rxq->rxd_count--;
933 1113
934 wh = (struct ieee80211_hdr *)skb->data; 1114 skb_put(skb, pkt_len);
1115 mwl8k_remove_dma_header(skb);
935 1116
936 /* 1117 /*
937 * Check for pending join operation. save a copy of 1118 * Check for a pending join operation. Save a
938 * the beacon and schedule a tasklet to send finalize 1119 * copy of the beacon and schedule a tasklet to
939 * join command to the firmware. 1120 * send a FINALIZE_JOIN command to the firmware.
940 */ 1121 */
941 if (mwl8k_capture_bssid(priv, wh)) 1122 if (mwl8k_capture_bssid(priv, (void *)skb->data))
942 mwl8k_save_beacon(priv, skb); 1123 mwl8k_save_beacon(hw, skb);
943 1124
944 memset(&status, 0, sizeof(status));
945 status.mactime = 0;
946 status.signal = -rx_desc->rssi;
947 status.noise = -rx_desc->noise_level;
948 status.qual = rx_desc->link_quality;
949 status.antenna = 1;
950 status.rate_idx = 1;
951 status.flag = 0;
952 status.band = IEEE80211_BAND_2GHZ;
953 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
954 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status)); 1125 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
955 ieee80211_rx_irqsafe(hw, skb); 1126 ieee80211_rx_irqsafe(hw, skb);
956 1127
@@ -965,24 +1136,10 @@ static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
965 * Packet transmission. 1136 * Packet transmission.
966 */ 1137 */
967 1138
968/* Transmit queue assignment. */
969enum {
970 MWL8K_WME_AC_BK = 0, /* background access */
971 MWL8K_WME_AC_BE = 1, /* best effort access */
972 MWL8K_WME_AC_VI = 2, /* video access */
973 MWL8K_WME_AC_VO = 3, /* voice access */
974};
975
976/* Transmit packet ACK policy */ 1139/* Transmit packet ACK policy */
977#define MWL8K_TXD_ACK_POLICY_NORMAL 0 1140#define MWL8K_TXD_ACK_POLICY_NORMAL 0
978#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3 1141#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
979 1142
980#define GET_TXQ(_ac) (\
981 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
982 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
983 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
984 MWL8K_WME_AC_BE)
985
986#define MWL8K_TXD_STATUS_OK 0x00000001 1143#define MWL8K_TXD_STATUS_OK 0x00000001
987#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002 1144#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
988#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004 1145#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
@@ -997,7 +1154,7 @@ struct mwl8k_tx_desc {
997 __le32 pkt_phys_addr; 1154 __le32 pkt_phys_addr;
998 __le16 pkt_len; 1155 __le16 pkt_len;
999 __u8 dest_MAC_addr[ETH_ALEN]; 1156 __u8 dest_MAC_addr[ETH_ALEN];
1000 __le32 next_tx_desc_phys_addr; 1157 __le32 next_txd_phys_addr;
1001 __le32 reserved; 1158 __le32 reserved;
1002 __le16 rate_info; 1159 __le16 rate_info;
1003 __u8 peer_id; 1160 __u8 peer_id;
@@ -1013,44 +1170,40 @@ static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1013 int size; 1170 int size;
1014 int i; 1171 int i;
1015 1172
1016 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats)); 1173 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1017 txq->tx_stats.limit = MWL8K_TX_DESCS; 1174 txq->stats.limit = MWL8K_TX_DESCS;
1018 txq->tx_head = 0; 1175 txq->head = 0;
1019 txq->tx_tail = 0; 1176 txq->tail = 0;
1020 1177
1021 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc); 1178 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1022 1179
1023 txq->tx_desc_area = 1180 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1024 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma); 1181 if (txq->txd == NULL) {
1025 if (txq->tx_desc_area == NULL) {
1026 printk(KERN_ERR "%s: failed to alloc TX descriptors\n", 1182 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1027 priv->name); 1183 wiphy_name(hw->wiphy));
1028 return -ENOMEM; 1184 return -ENOMEM;
1029 } 1185 }
1030 memset(txq->tx_desc_area, 0, size); 1186 memset(txq->txd, 0, size);
1031 1187
1032 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb), 1188 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1033 GFP_KERNEL); 1189 if (txq->skb == NULL) {
1034 if (txq->tx_skb == NULL) {
1035 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n", 1190 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1036 priv->name); 1191 wiphy_name(hw->wiphy));
1037 pci_free_consistent(priv->pdev, size, 1192 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1038 txq->tx_desc_area, txq->tx_desc_dma);
1039 return -ENOMEM; 1193 return -ENOMEM;
1040 } 1194 }
1041 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb)); 1195 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1042 1196
1043 for (i = 0; i < MWL8K_TX_DESCS; i++) { 1197 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1044 struct mwl8k_tx_desc *tx_desc; 1198 struct mwl8k_tx_desc *tx_desc;
1045 int nexti; 1199 int nexti;
1046 1200
1047 tx_desc = txq->tx_desc_area + i; 1201 tx_desc = txq->txd + i;
1048 nexti = (i + 1) % MWL8K_TX_DESCS; 1202 nexti = (i + 1) % MWL8K_TX_DESCS;
1049 1203
1050 tx_desc->status = 0; 1204 tx_desc->status = 0;
1051 tx_desc->next_tx_desc_phys_addr = 1205 tx_desc->next_txd_phys_addr =
1052 cpu_to_le32(txq->tx_desc_dma + 1206 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1053 nexti * sizeof(*tx_desc));
1054 } 1207 }
1055 1208
1056 return 0; 1209 return 0;
@@ -1065,11 +1218,6 @@ static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1065 ioread32(priv->regs + MWL8K_HIU_INT_CODE); 1218 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1066} 1219}
1067 1220
1068static inline int mwl8k_txq_busy(struct mwl8k_priv *priv)
1069{
1070 return priv->pending_tx_pkts;
1071}
1072
1073struct mwl8k_txq_info { 1221struct mwl8k_txq_info {
1074 u32 fw_owned; 1222 u32 fw_owned;
1075 u32 drv_owned; 1223 u32 drv_owned;
@@ -1089,14 +1237,13 @@ static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1089 1237
1090 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info)); 1238 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1091 1239
1092 spin_lock_bh(&priv->tx_lock);
1093 for (count = 0; count < MWL8K_TX_QUEUES; count++) { 1240 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1094 txq = priv->txq + count; 1241 txq = priv->txq + count;
1095 txinfo[count].len = txq->tx_stats.len; 1242 txinfo[count].len = txq->stats.len;
1096 txinfo[count].head = txq->tx_head; 1243 txinfo[count].head = txq->head;
1097 txinfo[count].tail = txq->tx_tail; 1244 txinfo[count].tail = txq->tail;
1098 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) { 1245 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1099 tx_desc = txq->tx_desc_area + desc; 1246 tx_desc = txq->txd + desc;
1100 status = le32_to_cpu(tx_desc->status); 1247 status = le32_to_cpu(tx_desc->status);
1101 1248
1102 if (status & MWL8K_TXD_STATUS_FW_OWNED) 1249 if (status & MWL8K_TXD_STATUS_FW_OWNED)
@@ -1108,30 +1255,26 @@ static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1108 txinfo[count].unused++; 1255 txinfo[count].unused++;
1109 } 1256 }
1110 } 1257 }
1111 spin_unlock_bh(&priv->tx_lock);
1112 1258
1113 return ndescs; 1259 return ndescs;
1114} 1260}
1115 1261
1116/* 1262/*
1117 * Must be called with hw->fw_mutex held and tx queues stopped. 1263 * Must be called with priv->fw_mutex held and tx queues stopped.
1118 */ 1264 */
1119static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw) 1265static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1120{ 1266{
1121 struct mwl8k_priv *priv = hw->priv; 1267 struct mwl8k_priv *priv = hw->priv;
1122 DECLARE_COMPLETION_ONSTACK(cmd_wait); 1268 DECLARE_COMPLETION_ONSTACK(tx_wait);
1123 u32 count; 1269 u32 count;
1124 unsigned long timeout; 1270 unsigned long timeout;
1125 1271
1126 might_sleep(); 1272 might_sleep();
1127 1273
1128 spin_lock_bh(&priv->tx_lock); 1274 spin_lock_bh(&priv->tx_lock);
1129 count = mwl8k_txq_busy(priv); 1275 count = priv->pending_tx_pkts;
1130 if (count) { 1276 if (count)
1131 priv->tx_wait = &cmd_wait; 1277 priv->tx_wait = &tx_wait;
1132 if (priv->radio_on)
1133 mwl8k_tx_start(priv);
1134 }
1135 spin_unlock_bh(&priv->tx_lock); 1278 spin_unlock_bh(&priv->tx_lock);
1136 1279
1137 if (count) { 1280 if (count) {
@@ -1139,23 +1282,23 @@ static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1139 int index; 1282 int index;
1140 int newcount; 1283 int newcount;
1141 1284
1142 timeout = wait_for_completion_timeout(&cmd_wait, 1285 timeout = wait_for_completion_timeout(&tx_wait,
1143 msecs_to_jiffies(5000)); 1286 msecs_to_jiffies(5000));
1144 if (timeout) 1287 if (timeout)
1145 return 0; 1288 return 0;
1146 1289
1147 spin_lock_bh(&priv->tx_lock); 1290 spin_lock_bh(&priv->tx_lock);
1148 priv->tx_wait = NULL; 1291 priv->tx_wait = NULL;
1149 newcount = mwl8k_txq_busy(priv); 1292 newcount = priv->pending_tx_pkts;
1293 mwl8k_scan_tx_ring(priv, txinfo);
1150 spin_unlock_bh(&priv->tx_lock); 1294 spin_unlock_bh(&priv->tx_lock);
1151 1295
1152 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n", 1296 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1153 __func__, __LINE__, count, newcount); 1297 __func__, __LINE__, count, newcount);
1154 1298
1155 mwl8k_scan_tx_ring(priv, txinfo);
1156 for (index = 0; index < MWL8K_TX_QUEUES; index++) 1299 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1157 printk(KERN_ERR 1300 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1158 "TXQ:%u L:%u H:%u T:%u FW:%u DRV:%u U:%u\n", 1301 "DRV:%u U:%u\n",
1159 index, 1302 index,
1160 txinfo[index].len, 1303 txinfo[index].len,
1161 txinfo[index].head, 1304 txinfo[index].head,
@@ -1181,7 +1324,7 @@ static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1181 struct mwl8k_tx_queue *txq = priv->txq + index; 1324 struct mwl8k_tx_queue *txq = priv->txq + index;
1182 int wake = 0; 1325 int wake = 0;
1183 1326
1184 while (txq->tx_stats.len > 0) { 1327 while (txq->stats.len > 0) {
1185 int tx; 1328 int tx;
1186 struct mwl8k_tx_desc *tx_desc; 1329 struct mwl8k_tx_desc *tx_desc;
1187 unsigned long addr; 1330 unsigned long addr;
@@ -1190,8 +1333,8 @@ static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1190 struct ieee80211_tx_info *info; 1333 struct ieee80211_tx_info *info;
1191 u32 status; 1334 u32 status;
1192 1335
1193 tx = txq->tx_head; 1336 tx = txq->head;
1194 tx_desc = txq->tx_desc_area + tx; 1337 tx_desc = txq->txd + tx;
1195 1338
1196 status = le32_to_cpu(tx_desc->status); 1339 status = le32_to_cpu(tx_desc->status);
1197 1340
@@ -1202,15 +1345,15 @@ static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1202 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED); 1345 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1203 } 1346 }
1204 1347
1205 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS; 1348 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1206 BUG_ON(txq->tx_stats.len == 0); 1349 BUG_ON(txq->stats.len == 0);
1207 txq->tx_stats.len--; 1350 txq->stats.len--;
1208 priv->pending_tx_pkts--; 1351 priv->pending_tx_pkts--;
1209 1352
1210 addr = le32_to_cpu(tx_desc->pkt_phys_addr); 1353 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1211 size = le16_to_cpu(tx_desc->pkt_len); 1354 size = le16_to_cpu(tx_desc->pkt_len);
1212 skb = txq->tx_skb[tx]; 1355 skb = txq->skb[tx];
1213 txq->tx_skb[tx] = NULL; 1356 txq->skb[tx] = NULL;
1214 1357
1215 BUG_ON(skb == NULL); 1358 BUG_ON(skb == NULL);
1216 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE); 1359 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
@@ -1243,13 +1386,13 @@ static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1243 1386
1244 mwl8k_txq_reclaim(hw, index, 1); 1387 mwl8k_txq_reclaim(hw, index, 1);
1245 1388
1246 kfree(txq->tx_skb); 1389 kfree(txq->skb);
1247 txq->tx_skb = NULL; 1390 txq->skb = NULL;
1248 1391
1249 pci_free_consistent(priv->pdev, 1392 pci_free_consistent(priv->pdev,
1250 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc), 1393 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1251 txq->tx_desc_area, txq->tx_desc_dma); 1394 txq->txd, txq->txd_dma);
1252 txq->tx_desc_area = NULL; 1395 txq->txd = NULL;
1253} 1396}
1254 1397
1255static int 1398static int
@@ -1317,7 +1460,7 @@ mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1317 1460
1318 if (pci_dma_mapping_error(priv->pdev, dma)) { 1461 if (pci_dma_mapping_error(priv->pdev, dma)) {
1319 printk(KERN_DEBUG "%s: failed to dma map skb, " 1462 printk(KERN_DEBUG "%s: failed to dma map skb, "
1320 "dropping TX frame.\n", priv->name); 1463 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1321 dev_kfree_skb(skb); 1464 dev_kfree_skb(skb);
1322 return NETDEV_TX_OK; 1465 return NETDEV_TX_OK;
1323 } 1466 }
@@ -1326,10 +1469,10 @@ mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1326 1469
1327 txq = priv->txq + index; 1470 txq = priv->txq + index;
1328 1471
1329 BUG_ON(txq->tx_skb[txq->tx_tail] != NULL); 1472 BUG_ON(txq->skb[txq->tail] != NULL);
1330 txq->tx_skb[txq->tx_tail] = skb; 1473 txq->skb[txq->tail] = skb;
1331 1474
1332 tx = txq->tx_desc_area + txq->tx_tail; 1475 tx = txq->txd + txq->tail;
1333 tx->data_rate = txdatarate; 1476 tx->data_rate = txdatarate;
1334 tx->tx_priority = index; 1477 tx->tx_priority = index;
1335 tx->qos_control = cpu_to_le16(qos); 1478 tx->qos_control = cpu_to_le16(qos);
@@ -1340,15 +1483,15 @@ mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1340 wmb(); 1483 wmb();
1341 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus); 1484 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1342 1485
1343 txq->tx_stats.count++; 1486 txq->stats.count++;
1344 txq->tx_stats.len++; 1487 txq->stats.len++;
1345 priv->pending_tx_pkts++; 1488 priv->pending_tx_pkts++;
1346 1489
1347 txq->tx_tail++; 1490 txq->tail++;
1348 if (txq->tx_tail == MWL8K_TX_DESCS) 1491 if (txq->tail == MWL8K_TX_DESCS)
1349 txq->tx_tail = 0; 1492 txq->tail = 0;
1350 1493
1351 if (txq->tx_head == txq->tx_tail) 1494 if (txq->head == txq->tail)
1352 ieee80211_stop_queue(hw, index); 1495 ieee80211_stop_queue(hw, index);
1353 1496
1354 mwl8k_tx_start(priv); 1497 mwl8k_tx_start(priv);
@@ -1431,7 +1574,7 @@ static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1431 unsigned long timeout = 0; 1574 unsigned long timeout = 0;
1432 u8 buf[32]; 1575 u8 buf[32];
1433 1576
1434 cmd->result = 0xFFFF; 1577 cmd->result = 0xffff;
1435 dma_size = le16_to_cpu(cmd->length); 1578 dma_size = le16_to_cpu(cmd->length);
1436 dma_addr = pci_map_single(priv->pdev, cmd, dma_size, 1579 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1437 PCI_DMA_BIDIRECTIONAL); 1580 PCI_DMA_BIDIRECTIONAL);
@@ -1464,7 +1607,7 @@ static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1464 1607
1465 if (!timeout) { 1608 if (!timeout) {
1466 printk(KERN_ERR "%s: Command %s timeout after %u ms\n", 1609 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1467 priv->name, 1610 wiphy_name(hw->wiphy),
1468 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), 1611 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1469 MWL8K_CMD_TIMEOUT_MS); 1612 MWL8K_CMD_TIMEOUT_MS);
1470 rc = -ETIMEDOUT; 1613 rc = -ETIMEDOUT;
@@ -1472,7 +1615,7 @@ static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1472 rc = cmd->result ? -EINVAL : 0; 1615 rc = cmd->result ? -EINVAL : 0;
1473 if (rc) 1616 if (rc)
1474 printk(KERN_ERR "%s: Command %s error 0x%x\n", 1617 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1475 priv->name, 1618 wiphy_name(hw->wiphy),
1476 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), 1619 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1477 le16_to_cpu(cmd->result)); 1620 le16_to_cpu(cmd->result));
1478 } 1621 }
@@ -1481,9 +1624,9 @@ static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1481} 1624}
1482 1625
1483/* 1626/*
1484 * GET_HW_SPEC. 1627 * CMD_GET_HW_SPEC (STA version).
1485 */ 1628 */
1486struct mwl8k_cmd_get_hw_spec { 1629struct mwl8k_cmd_get_hw_spec_sta {
1487 struct mwl8k_cmd_pkt header; 1630 struct mwl8k_cmd_pkt header;
1488 __u8 hw_rev; 1631 __u8 hw_rev;
1489 __u8 host_interface; 1632 __u8 host_interface;
@@ -1499,13 +1642,13 @@ struct mwl8k_cmd_get_hw_spec {
1499 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; 1642 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1500 __le32 caps2; 1643 __le32 caps2;
1501 __le32 num_tx_desc_per_queue; 1644 __le32 num_tx_desc_per_queue;
1502 __le32 total_rx_desc; 1645 __le32 total_rxd;
1503} __attribute__((packed)); 1646} __attribute__((packed));
1504 1647
1505static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw) 1648static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
1506{ 1649{
1507 struct mwl8k_priv *priv = hw->priv; 1650 struct mwl8k_priv *priv = hw->priv;
1508 struct mwl8k_cmd_get_hw_spec *cmd; 1651 struct mwl8k_cmd_get_hw_spec_sta *cmd;
1509 int rc; 1652 int rc;
1510 int i; 1653 int i;
1511 1654
@@ -1518,12 +1661,12 @@ static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1518 1661
1519 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); 1662 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1520 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); 1663 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1521 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma); 1664 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1522 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); 1665 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1523 for (i = 0; i < MWL8K_TX_QUEUES; i++) 1666 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1524 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma); 1667 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1525 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); 1668 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1526 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS); 1669 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1527 1670
1528 rc = mwl8k_post_cmd(hw, &cmd->header); 1671 rc = mwl8k_post_cmd(hw, &cmd->header);
1529 1672
@@ -1539,6 +1682,129 @@ static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1539} 1682}
1540 1683
1541/* 1684/*
1685 * CMD_GET_HW_SPEC (AP version).
1686 */
1687struct mwl8k_cmd_get_hw_spec_ap {
1688 struct mwl8k_cmd_pkt header;
1689 __u8 hw_rev;
1690 __u8 host_interface;
1691 __le16 num_wcb;
1692 __le16 num_mcaddrs;
1693 __u8 perm_addr[ETH_ALEN];
1694 __le16 region_code;
1695 __le16 num_antenna;
1696 __le32 fw_rev;
1697 __le32 wcbbase0;
1698 __le32 rxwrptr;
1699 __le32 rxrdptr;
1700 __le32 ps_cookie;
1701 __le32 wcbbase1;
1702 __le32 wcbbase2;
1703 __le32 wcbbase3;
1704} __attribute__((packed));
1705
1706static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1707{
1708 struct mwl8k_priv *priv = hw->priv;
1709 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1710 int rc;
1711
1712 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1713 if (cmd == NULL)
1714 return -ENOMEM;
1715
1716 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1717 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1718
1719 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1720 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1721
1722 rc = mwl8k_post_cmd(hw, &cmd->header);
1723
1724 if (!rc) {
1725 int off;
1726
1727 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1728 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1729 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1730 priv->hw_rev = cmd->hw_rev;
1731
1732 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1733 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1734
1735 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1736 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1737
1738 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1739 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1740
1741 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1742 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1743
1744 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1745 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1746
1747 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1748 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1749 }
1750
1751 kfree(cmd);
1752 return rc;
1753}
1754
1755/*
1756 * CMD_SET_HW_SPEC.
1757 */
1758struct mwl8k_cmd_set_hw_spec {
1759 struct mwl8k_cmd_pkt header;
1760 __u8 hw_rev;
1761 __u8 host_interface;
1762 __le16 num_mcaddrs;
1763 __u8 perm_addr[ETH_ALEN];
1764 __le16 region_code;
1765 __le32 fw_rev;
1766 __le32 ps_cookie;
1767 __le32 caps;
1768 __le32 rx_queue_ptr;
1769 __le32 num_tx_queues;
1770 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1771 __le32 flags;
1772 __le32 num_tx_desc_per_queue;
1773 __le32 total_rxd;
1774} __attribute__((packed));
1775
1776#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1777
1778static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1779{
1780 struct mwl8k_priv *priv = hw->priv;
1781 struct mwl8k_cmd_set_hw_spec *cmd;
1782 int rc;
1783 int i;
1784
1785 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1786 if (cmd == NULL)
1787 return -ENOMEM;
1788
1789 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1790 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1791
1792 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1793 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1794 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1795 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1796 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1797 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1798 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1799 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1800
1801 rc = mwl8k_post_cmd(hw, &cmd->header);
1802 kfree(cmd);
1803
1804 return rc;
1805}
1806
1807/*
1542 * CMD_MAC_MULTICAST_ADR. 1808 * CMD_MAC_MULTICAST_ADR.
1543 */ 1809 */
1544struct mwl8k_cmd_mac_multicast_adr { 1810struct mwl8k_cmd_mac_multicast_adr {
@@ -1548,19 +1814,23 @@ struct mwl8k_cmd_mac_multicast_adr {
1548 __u8 addr[0][ETH_ALEN]; 1814 __u8 addr[0][ETH_ALEN];
1549}; 1815};
1550 1816
1551#define MWL8K_ENABLE_RX_MULTICAST 0x000F 1817#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1818#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1819#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1820#define MWL8K_ENABLE_RX_BROADCAST 0x0008
1552 1821
1553static struct mwl8k_cmd_pkt * 1822static struct mwl8k_cmd_pkt *
1554__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, 1823__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1555 int mc_count, struct dev_addr_list *mclist) 1824 int mc_count, struct dev_addr_list *mclist)
1556{ 1825{
1557 struct mwl8k_priv *priv = hw->priv; 1826 struct mwl8k_priv *priv = hw->priv;
1558 struct mwl8k_cmd_mac_multicast_adr *cmd; 1827 struct mwl8k_cmd_mac_multicast_adr *cmd;
1559 int size; 1828 int size;
1560 int i;
1561 1829
1562 if (mc_count > priv->num_mcaddrs) 1830 if (allmulti || mc_count > priv->num_mcaddrs) {
1563 mc_count = priv->num_mcaddrs; 1831 allmulti = 1;
1832 mc_count = 0;
1833 }
1564 1834
1565 size = sizeof(*cmd) + mc_count * ETH_ALEN; 1835 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1566 1836
@@ -1570,16 +1840,24 @@ __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw,
1570 1840
1571 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR); 1841 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1572 cmd->header.length = cpu_to_le16(size); 1842 cmd->header.length = cpu_to_le16(size);
1573 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST); 1843 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1574 cmd->numaddr = cpu_to_le16(mc_count); 1844 MWL8K_ENABLE_RX_BROADCAST);
1575 1845
1576 for (i = 0; i < mc_count && mclist; i++) { 1846 if (allmulti) {
1577 if (mclist->da_addrlen != ETH_ALEN) { 1847 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1578 kfree(cmd); 1848 } else if (mc_count) {
1579 return NULL; 1849 int i;
1850
1851 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1852 cmd->numaddr = cpu_to_le16(mc_count);
1853 for (i = 0; i < mc_count && mclist; i++) {
1854 if (mclist->da_addrlen != ETH_ALEN) {
1855 kfree(cmd);
1856 return NULL;
1857 }
1858 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1859 mclist = mclist->next;
1580 } 1860 }
1581 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1582 mclist = mclist->next;
1583 } 1861 }
1584 1862
1585 return &cmd->header; 1863 return &cmd->header;
@@ -1590,7 +1868,6 @@ __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw,
1590 */ 1868 */
1591struct mwl8k_cmd_802_11_get_stat { 1869struct mwl8k_cmd_802_11_get_stat {
1592 struct mwl8k_cmd_pkt header; 1870 struct mwl8k_cmd_pkt header;
1593 __le16 action;
1594 __le32 stats[64]; 1871 __le32 stats[64];
1595} __attribute__((packed)); 1872} __attribute__((packed));
1596 1873
@@ -1611,7 +1888,6 @@ static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1611 1888
1612 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT); 1889 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1613 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1890 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1614 cmd->action = cpu_to_le16(MWL8K_CMD_GET);
1615 1891
1616 rc = mwl8k_post_cmd(hw, &cmd->header); 1892 rc = mwl8k_post_cmd(hw, &cmd->header);
1617 if (!rc) { 1893 if (!rc) {
@@ -1727,6 +2003,39 @@ static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1727} 2003}
1728 2004
1729/* 2005/*
2006 * CMD_RF_ANTENNA.
2007 */
2008struct mwl8k_cmd_rf_antenna {
2009 struct mwl8k_cmd_pkt header;
2010 __le16 antenna;
2011 __le16 mode;
2012} __attribute__((packed));
2013
2014#define MWL8K_RF_ANTENNA_RX 1
2015#define MWL8K_RF_ANTENNA_TX 2
2016
2017static int
2018mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2019{
2020 struct mwl8k_cmd_rf_antenna *cmd;
2021 int rc;
2022
2023 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2024 if (cmd == NULL)
2025 return -ENOMEM;
2026
2027 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2028 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2029 cmd->antenna = cpu_to_le16(antenna);
2030 cmd->mode = cpu_to_le16(mask);
2031
2032 rc = mwl8k_post_cmd(hw, &cmd->header);
2033 kfree(cmd);
2034
2035 return rc;
2036}
2037
2038/*
1730 * CMD_SET_PRE_SCAN. 2039 * CMD_SET_PRE_SCAN.
1731 */ 2040 */
1732struct mwl8k_cmd_set_pre_scan { 2041struct mwl8k_cmd_set_pre_scan {
@@ -1904,6 +2213,46 @@ static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1904} 2213}
1905 2214
1906/* 2215/*
2216 * CMD_SET_MAC_ADDR.
2217 */
2218struct mwl8k_cmd_set_mac_addr {
2219 struct mwl8k_cmd_pkt header;
2220 union {
2221 struct {
2222 __le16 mac_type;
2223 __u8 mac_addr[ETH_ALEN];
2224 } mbss;
2225 __u8 mac_addr[ETH_ALEN];
2226 };
2227} __attribute__((packed));
2228
2229static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2230{
2231 struct mwl8k_priv *priv = hw->priv;
2232 struct mwl8k_cmd_set_mac_addr *cmd;
2233 int rc;
2234
2235 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2236 if (cmd == NULL)
2237 return -ENOMEM;
2238
2239 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2240 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2241 if (priv->ap_fw) {
2242 cmd->mbss.mac_type = 0;
2243 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2244 } else {
2245 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2246 }
2247
2248 rc = mwl8k_post_cmd(hw, &cmd->header);
2249 kfree(cmd);
2250
2251 return rc;
2252}
2253
2254
2255/*
1907 * CMD_SET_RATEADAPT_MODE. 2256 * CMD_SET_RATEADAPT_MODE.
1908 */ 2257 */
1909struct mwl8k_cmd_set_rate_adapt_mode { 2258struct mwl8k_cmd_set_rate_adapt_mode {
@@ -2005,17 +2354,34 @@ struct mwl8k_cmd_set_edca_params {
2005 /* TX opportunity in units of 32 us */ 2354 /* TX opportunity in units of 32 us */
2006 __le16 txop; 2355 __le16 txop;
2007 2356
2008 /* Log exponent of max contention period: 0...15*/ 2357 union {
2009 __u8 log_cw_max; 2358 struct {
2359 /* Log exponent of max contention period: 0...15 */
2360 __le32 log_cw_max;
2361
2362 /* Log exponent of min contention period: 0...15 */
2363 __le32 log_cw_min;
2364
2365 /* Adaptive interframe spacing in units of 32us */
2366 __u8 aifs;
2367
2368 /* TX queue to configure */
2369 __u8 txq;
2370 } ap;
2371 struct {
2372 /* Log exponent of max contention period: 0...15 */
2373 __u8 log_cw_max;
2010 2374
2011 /* Log exponent of min contention period: 0...15 */ 2375 /* Log exponent of min contention period: 0...15 */
2012 __u8 log_cw_min; 2376 __u8 log_cw_min;
2013 2377
2014 /* Adaptive interframe spacing in units of 32us */ 2378 /* Adaptive interframe spacing in units of 32us */
2015 __u8 aifs; 2379 __u8 aifs;
2016 2380
2017 /* TX queue to configure */ 2381 /* TX queue to configure */
2018 __u8 txq; 2382 __u8 txq;
2383 } sta;
2384 };
2019} __attribute__((packed)); 2385} __attribute__((packed));
2020 2386
2021#define MWL8K_SET_EDCA_CW 0x01 2387#define MWL8K_SET_EDCA_CW 0x01
@@ -2031,6 +2397,7 @@ mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2031 __u16 cw_min, __u16 cw_max, 2397 __u16 cw_min, __u16 cw_max,
2032 __u8 aifs, __u16 txop) 2398 __u8 aifs, __u16 txop)
2033{ 2399{
2400 struct mwl8k_priv *priv = hw->priv;
2034 struct mwl8k_cmd_set_edca_params *cmd; 2401 struct mwl8k_cmd_set_edca_params *cmd;
2035 int rc; 2402 int rc;
2036 2403
@@ -2038,14 +2405,27 @@ mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2038 if (cmd == NULL) 2405 if (cmd == NULL)
2039 return -ENOMEM; 2406 return -ENOMEM;
2040 2407
2408 /*
2409 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2410 * this call.
2411 */
2412 qnum ^= !(qnum >> 1);
2413
2041 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS); 2414 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2042 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2415 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2043 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL); 2416 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2044 cmd->txop = cpu_to_le16(txop); 2417 cmd->txop = cpu_to_le16(txop);
2045 cmd->log_cw_max = (u8)ilog2(cw_max + 1); 2418 if (priv->ap_fw) {
2046 cmd->log_cw_min = (u8)ilog2(cw_min + 1); 2419 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2047 cmd->aifs = aifs; 2420 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2048 cmd->txq = qnum; 2421 cmd->ap.aifs = aifs;
2422 cmd->ap.txq = qnum;
2423 } else {
2424 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2425 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2426 cmd->sta.aifs = aifs;
2427 cmd->sta.txq = qnum;
2428 }
2049 2429
2050 rc = mwl8k_post_cmd(hw, &cmd->header); 2430 rc = mwl8k_post_cmd(hw, &cmd->header);
2051 kfree(cmd); 2431 kfree(cmd);
@@ -2093,8 +2473,8 @@ static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2093 /* XXX TBD Might just have to abort and return an error */ 2473 /* XXX TBD Might just have to abort and return an error */
2094 if (payload_len > MWL8K_FJ_BEACON_MAXLEN) 2474 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2095 printk(KERN_ERR "%s(): WARNING: Incomplete beacon " 2475 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2096 "sent to firmware. Sz=%u MAX=%u\n", __func__, 2476 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2097 payload_len, MWL8K_FJ_BEACON_MAXLEN); 2477 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2098 2478
2099 if (payload_len > MWL8K_FJ_BEACON_MAXLEN) 2479 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2100 payload_len = MWL8K_FJ_BEACON_MAXLEN; 2480 payload_len = MWL8K_FJ_BEACON_MAXLEN;
@@ -2341,9 +2721,10 @@ static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2341 cmd->rate_type = cpu_to_le32(rate_type); 2721 cmd->rate_type = cpu_to_le32(rate_type);
2342 2722
2343 if (rate_table != NULL) { 2723 if (rate_table != NULL) {
2344 /* Copy over each field manually so 2724 /*
2345 * that bitflipping can be done 2725 * Copy over each field manually so that endian
2346 */ 2726 * conversion can be done.
2727 */
2347 cmd->rate_table.allow_rate_drop = 2728 cmd->rate_table.allow_rate_drop =
2348 cpu_to_le32(rate_table->allow_rate_drop); 2729 cpu_to_le32(rate_table->allow_rate_drop);
2349 cmd->rate_table.num_rates = 2730 cmd->rate_table.num_rates =
@@ -2399,7 +2780,7 @@ static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2399 2780
2400 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) { 2781 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2401 if (!mutex_is_locked(&priv->fw_mutex) && 2782 if (!mutex_is_locked(&priv->fw_mutex) &&
2402 priv->radio_on && mwl8k_txq_busy(priv)) 2783 priv->radio_on && priv->pending_tx_pkts)
2403 mwl8k_tx_start(priv); 2784 mwl8k_tx_start(priv);
2404 } 2785 }
2405 2786
@@ -2418,7 +2799,7 @@ static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2418 2799
2419 if (priv->current_channel == NULL) { 2800 if (priv->current_channel == NULL) {
2420 printk(KERN_DEBUG "%s: dropped TX frame since radio " 2801 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2421 "disabled\n", priv->name); 2802 "disabled\n", wiphy_name(hw->wiphy));
2422 dev_kfree_skb(skb); 2803 dev_kfree_skb(skb);
2423 return NETDEV_TX_OK; 2804 return NETDEV_TX_OK;
2424 } 2805 }
@@ -2437,7 +2818,7 @@ static int mwl8k_start(struct ieee80211_hw *hw)
2437 IRQF_SHARED, MWL8K_NAME, hw); 2818 IRQF_SHARED, MWL8K_NAME, hw);
2438 if (rc) { 2819 if (rc) {
2439 printk(KERN_ERR "%s: failed to register IRQ handler\n", 2820 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2440 priv->name); 2821 wiphy_name(hw->wiphy));
2441 return -EIO; 2822 return -EIO;
2442 } 2823 }
2443 2824
@@ -2451,12 +2832,17 @@ static int mwl8k_start(struct ieee80211_hw *hw)
2451 if (!rc) { 2832 if (!rc) {
2452 rc = mwl8k_cmd_802_11_radio_enable(hw); 2833 rc = mwl8k_cmd_802_11_radio_enable(hw);
2453 2834
2454 if (!rc) 2835 if (!priv->ap_fw) {
2455 rc = mwl8k_cmd_set_pre_scan(hw); 2836 if (!rc)
2837 rc = mwl8k_enable_sniffer(hw, 0);
2456 2838
2457 if (!rc) 2839 if (!rc)
2458 rc = mwl8k_cmd_set_post_scan(hw, 2840 rc = mwl8k_cmd_set_pre_scan(hw);
2459 "\x00\x00\x00\x00\x00\x00"); 2841
2842 if (!rc)
2843 rc = mwl8k_cmd_set_post_scan(hw,
2844 "\x00\x00\x00\x00\x00\x00");
2845 }
2460 2846
2461 if (!rc) 2847 if (!rc)
2462 rc = mwl8k_cmd_setrateadaptmode(hw, 0); 2848 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
@@ -2464,9 +2850,6 @@ static int mwl8k_start(struct ieee80211_hw *hw)
2464 if (!rc) 2850 if (!rc)
2465 rc = mwl8k_set_wmm(hw, 0); 2851 rc = mwl8k_set_wmm(hw, 0);
2466 2852
2467 if (!rc)
2468 rc = mwl8k_enable_sniffer(hw, 0);
2469
2470 mwl8k_fw_unlock(hw); 2853 mwl8k_fw_unlock(hw);
2471 } 2854 }
2472 2855
@@ -2500,9 +2883,6 @@ static void mwl8k_stop(struct ieee80211_hw *hw)
2500 /* Stop tx reclaim tasklet */ 2883 /* Stop tx reclaim tasklet */
2501 tasklet_disable(&priv->tx_reclaim_task); 2884 tasklet_disable(&priv->tx_reclaim_task);
2502 2885
2503 /* Stop config thread */
2504 flush_workqueue(priv->config_wq);
2505
2506 /* Return all skbs to mac80211 */ 2886 /* Return all skbs to mac80211 */
2507 for (i = 0; i < MWL8K_TX_QUEUES; i++) 2887 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2508 mwl8k_txq_reclaim(hw, i, 1); 2888 mwl8k_txq_reclaim(hw, i, 1);
@@ -2526,11 +2906,24 @@ static int mwl8k_add_interface(struct ieee80211_hw *hw,
2526 if (conf->type != NL80211_IFTYPE_STATION) 2906 if (conf->type != NL80211_IFTYPE_STATION)
2527 return -EINVAL; 2907 return -EINVAL;
2528 2908
2909 /*
2910 * Reject interface creation if sniffer mode is active, as
2911 * STA operation is mutually exclusive with hardware sniffer
2912 * mode.
2913 */
2914 if (priv->sniffer_enabled) {
2915 printk(KERN_INFO "%s: unable to create STA "
2916 "interface due to sniffer mode being enabled\n",
2917 wiphy_name(hw->wiphy));
2918 return -EINVAL;
2919 }
2920
2529 /* Clean out driver private area */ 2921 /* Clean out driver private area */
2530 mwl8k_vif = MWL8K_VIF(conf->vif); 2922 mwl8k_vif = MWL8K_VIF(conf->vif);
2531 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif)); 2923 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2532 2924
2533 /* Save the mac address */ 2925 /* Set and save the mac address */
2926 mwl8k_set_mac_addr(hw, conf->mac_addr);
2534 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN); 2927 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2535 2928
2536 /* Back pointer to parent config block */ 2929 /* Back pointer to parent config block */
@@ -2558,6 +2951,8 @@ static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2558 if (priv->vif == NULL) 2951 if (priv->vif == NULL)
2559 return; 2952 return;
2560 2953
2954 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2955
2561 priv->vif = NULL; 2956 priv->vif = NULL;
2562} 2957}
2563 2958
@@ -2593,8 +2988,13 @@ static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2593 if (rc) 2988 if (rc)
2594 goto out; 2989 goto out;
2595 2990
2596 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7)) 2991 if (priv->ap_fw) {
2597 rc = -EINVAL; 2992 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2993 if (!rc)
2994 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2995 } else {
2996 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2997 }
2598 2998
2599out: 2999out:
2600 mwl8k_fw_unlock(hw); 3000 mwl8k_fw_unlock(hw);
@@ -2681,32 +3081,108 @@ static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2681{ 3081{
2682 struct mwl8k_cmd_pkt *cmd; 3082 struct mwl8k_cmd_pkt *cmd;
2683 3083
2684 cmd = __mwl8k_cmd_mac_multicast_adr(hw, mc_count, mclist); 3084 /*
3085 * Synthesize and return a command packet that programs the
3086 * hardware multicast address filter. At this point we don't
3087 * know whether FIF_ALLMULTI is being requested, but if it is,
3088 * we'll end up throwing this packet away and creating a new
3089 * one in mwl8k_configure_filter().
3090 */
3091 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
2685 3092
2686 return (unsigned long)cmd; 3093 return (unsigned long)cmd;
2687} 3094}
2688 3095
3096static int
3097mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3098 unsigned int changed_flags,
3099 unsigned int *total_flags)
3100{
3101 struct mwl8k_priv *priv = hw->priv;
3102
3103 /*
3104 * Hardware sniffer mode is mutually exclusive with STA
3105 * operation, so refuse to enable sniffer mode if a STA
3106 * interface is active.
3107 */
3108 if (priv->vif != NULL) {
3109 if (net_ratelimit())
3110 printk(KERN_INFO "%s: not enabling sniffer "
3111 "mode because STA interface is active\n",
3112 wiphy_name(hw->wiphy));
3113 return 0;
3114 }
3115
3116 if (!priv->sniffer_enabled) {
3117 if (mwl8k_enable_sniffer(hw, 1))
3118 return 0;
3119 priv->sniffer_enabled = true;
3120 }
3121
3122 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3123 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3124 FIF_OTHER_BSS;
3125
3126 return 1;
3127}
3128
2689static void mwl8k_configure_filter(struct ieee80211_hw *hw, 3129static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2690 unsigned int changed_flags, 3130 unsigned int changed_flags,
2691 unsigned int *total_flags, 3131 unsigned int *total_flags,
2692 u64 multicast) 3132 u64 multicast)
2693{ 3133{
2694 struct mwl8k_priv *priv = hw->priv; 3134 struct mwl8k_priv *priv = hw->priv;
2695 struct mwl8k_cmd_pkt *multicast_adr_cmd; 3135 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3136
3137 /*
3138 * AP firmware doesn't allow fine-grained control over
3139 * the receive filter.
3140 */
3141 if (priv->ap_fw) {
3142 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3143 kfree(cmd);
3144 return;
3145 }
3146
3147 /*
3148 * Enable hardware sniffer mode if FIF_CONTROL or
3149 * FIF_OTHER_BSS is requested.
3150 */
3151 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3152 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3153 kfree(cmd);
3154 return;
3155 }
2696 3156
2697 /* Clear unsupported feature flags */ 3157 /* Clear unsupported feature flags */
2698 *total_flags &= FIF_BCN_PRBRESP_PROMISC; 3158 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
2699 3159
2700 if (mwl8k_fw_lock(hw)) 3160 if (mwl8k_fw_lock(hw))
2701 return; 3161 return;
2702 3162
3163 if (priv->sniffer_enabled) {
3164 mwl8k_enable_sniffer(hw, 0);
3165 priv->sniffer_enabled = false;
3166 }
3167
2703 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { 3168 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2704 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) 3169 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3170 /*
3171 * Disable the BSS filter.
3172 */
2705 mwl8k_cmd_set_pre_scan(hw); 3173 mwl8k_cmd_set_pre_scan(hw);
2706 else { 3174 } else {
2707 u8 *bssid; 3175 u8 *bssid;
2708 3176
2709 bssid = "\x00\x00\x00\x00\x00\x00"; 3177 /*
3178 * Enable the BSS filter.
3179 *
3180 * If there is an active STA interface, use that
3181 * interface's BSSID, otherwise use a dummy one
3182 * (where the OUI part needs to be nonzero for
3183 * the BSSID to be accepted by POST_SCAN).
3184 */
3185 bssid = "\x01\x00\x00\x00\x00\x00";
2710 if (priv->vif != NULL) 3186 if (priv->vif != NULL)
2711 bssid = MWL8K_VIF(priv->vif)->bssid; 3187 bssid = MWL8K_VIF(priv->vif)->bssid;
2712 3188
@@ -2714,10 +3190,20 @@ static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2714 } 3190 }
2715 } 3191 }
2716 3192
2717 multicast_adr_cmd = (void *)(unsigned long)multicast; 3193 /*
2718 if (multicast_adr_cmd != NULL) { 3194 * If FIF_ALLMULTI is being requested, throw away the command
2719 mwl8k_post_cmd(hw, multicast_adr_cmd); 3195 * packet that ->prepare_multicast() built and replace it with
2720 kfree(multicast_adr_cmd); 3196 * a command packet that enables reception of all multicast
3197 * packets.
3198 */
3199 if (*total_flags & FIF_ALLMULTI) {
3200 kfree(cmd);
3201 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3202 }
3203
3204 if (cmd != NULL) {
3205 mwl8k_post_cmd(hw, cmd);
3206 kfree(cmd);
2721 } 3207 }
2722 3208
2723 mwl8k_fw_unlock(hw); 3209 mwl8k_fw_unlock(hw);
@@ -2762,7 +3248,7 @@ static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2762 spin_lock_bh(&priv->tx_lock); 3248 spin_lock_bh(&priv->tx_lock);
2763 for (index = 0; index < MWL8K_TX_QUEUES; index++) { 3249 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2764 txq = priv->txq + index; 3250 txq = priv->txq + index;
2765 memcpy(&stats[index], &txq->tx_stats, 3251 memcpy(&stats[index], &txq->stats,
2766 sizeof(struct ieee80211_tx_queue_stats)); 3252 sizeof(struct ieee80211_tx_queue_stats));
2767 } 3253 }
2768 spin_unlock_bh(&priv->tx_lock); 3254 spin_unlock_bh(&priv->tx_lock);
@@ -2802,7 +3288,7 @@ static void mwl8k_tx_reclaim_handler(unsigned long data)
2802 for (i = 0; i < MWL8K_TX_QUEUES; i++) 3288 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2803 mwl8k_txq_reclaim(hw, i, 0); 3289 mwl8k_txq_reclaim(hw, i, 0);
2804 3290
2805 if (priv->tx_wait != NULL && mwl8k_txq_busy(priv) == 0) { 3291 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
2806 complete(priv->tx_wait); 3292 complete(priv->tx_wait);
2807 priv->tx_wait = NULL; 3293 priv->tx_wait = NULL;
2808 } 3294 }
@@ -2822,6 +3308,36 @@ static void mwl8k_finalize_join_worker(struct work_struct *work)
2822 priv->beacon_skb = NULL; 3308 priv->beacon_skb = NULL;
2823} 3309}
2824 3310
3311enum {
3312 MWL8687 = 0,
3313 MWL8366,
3314};
3315
3316static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3317 {
3318 .part_name = "88w8687",
3319 .helper_image = "mwl8k/helper_8687.fw",
3320 .fw_image = "mwl8k/fmimage_8687.fw",
3321 .rxd_ops = &rxd_8687_ops,
3322 .modes = BIT(NL80211_IFTYPE_STATION),
3323 },
3324 {
3325 .part_name = "88w8366",
3326 .helper_image = "mwl8k/helper_8366.fw",
3327 .fw_image = "mwl8k/fmimage_8366.fw",
3328 .rxd_ops = &rxd_8366_ops,
3329 .modes = 0,
3330 },
3331};
3332
3333static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3334 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3335 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3336 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3337 { },
3338};
3339MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3340
2825static int __devinit mwl8k_probe(struct pci_dev *pdev, 3341static int __devinit mwl8k_probe(struct pci_dev *pdev,
2826 const struct pci_device_id *id) 3342 const struct pci_device_id *id)
2827{ 3343{
@@ -2862,17 +3378,34 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
2862 priv = hw->priv; 3378 priv = hw->priv;
2863 priv->hw = hw; 3379 priv->hw = hw;
2864 priv->pdev = pdev; 3380 priv->pdev = pdev;
3381 priv->device_info = &mwl8k_info_tbl[id->driver_data];
3382 priv->rxd_ops = priv->device_info->rxd_ops;
3383 priv->sniffer_enabled = false;
2865 priv->wmm_enabled = false; 3384 priv->wmm_enabled = false;
2866 priv->pending_tx_pkts = 0; 3385 priv->pending_tx_pkts = 0;
2867 strncpy(priv->name, MWL8K_NAME, sizeof(priv->name));
2868 3386
2869 SET_IEEE80211_DEV(hw, &pdev->dev); 3387 SET_IEEE80211_DEV(hw, &pdev->dev);
2870 pci_set_drvdata(pdev, hw); 3388 pci_set_drvdata(pdev, hw);
2871 3389
3390 priv->sram = pci_iomap(pdev, 0, 0x10000);
3391 if (priv->sram == NULL) {
3392 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3393 wiphy_name(hw->wiphy));
3394 goto err_iounmap;
3395 }
3396
3397 /*
3398 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3399 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3400 */
2872 priv->regs = pci_iomap(pdev, 1, 0x10000); 3401 priv->regs = pci_iomap(pdev, 1, 0x10000);
2873 if (priv->regs == NULL) { 3402 if (priv->regs == NULL) {
2874 printk(KERN_ERR "%s: Cannot map device memory\n", priv->name); 3403 priv->regs = pci_iomap(pdev, 2, 0x10000);
2875 goto err_iounmap; 3404 if (priv->regs == NULL) {
3405 printk(KERN_ERR "%s: Cannot map device registers\n",
3406 wiphy_name(hw->wiphy));
3407 goto err_iounmap;
3408 }
2876 } 3409 }
2877 3410
2878 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels)); 3411 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
@@ -2897,7 +3430,7 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
2897 3430
2898 hw->queues = MWL8K_TX_QUEUES; 3431 hw->queues = MWL8K_TX_QUEUES;
2899 3432
2900 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 3433 hw->wiphy->interface_modes = priv->device_info->modes;
2901 3434
2902 /* Set rssi and noise values to dBm */ 3435 /* Set rssi and noise values to dBm */
2903 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM; 3436 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
@@ -2916,11 +3449,6 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
2916 mwl8k_tx_reclaim_handler, (unsigned long)hw); 3449 mwl8k_tx_reclaim_handler, (unsigned long)hw);
2917 tasklet_disable(&priv->tx_reclaim_task); 3450 tasklet_disable(&priv->tx_reclaim_task);
2918 3451
2919 /* Config workthread */
2920 priv->config_wq = create_singlethread_workqueue("mwl8k_config");
2921 if (priv->config_wq == NULL)
2922 goto err_iounmap;
2923
2924 /* Power management cookie */ 3452 /* Power management cookie */
2925 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma); 3453 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
2926 if (priv->cookie == NULL) 3454 if (priv->cookie == NULL)
@@ -2934,11 +3462,12 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
2934 mutex_init(&priv->fw_mutex); 3462 mutex_init(&priv->fw_mutex);
2935 priv->fw_mutex_owner = NULL; 3463 priv->fw_mutex_owner = NULL;
2936 priv->fw_mutex_depth = 0; 3464 priv->fw_mutex_depth = 0;
2937 priv->tx_wait = NULL;
2938 priv->hostcmd_wait = NULL; 3465 priv->hostcmd_wait = NULL;
2939 3466
2940 spin_lock_init(&priv->tx_lock); 3467 spin_lock_init(&priv->tx_lock);
2941 3468
3469 priv->tx_wait = NULL;
3470
2942 for (i = 0; i < MWL8K_TX_QUEUES; i++) { 3471 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
2943 rc = mwl8k_txq_init(hw, i); 3472 rc = mwl8k_txq_init(hw, i);
2944 if (rc) 3473 if (rc)
@@ -2954,7 +3483,7 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
2954 IRQF_SHARED, MWL8K_NAME, hw); 3483 IRQF_SHARED, MWL8K_NAME, hw);
2955 if (rc) { 3484 if (rc) {
2956 printk(KERN_ERR "%s: failed to register IRQ handler\n", 3485 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2957 priv->name); 3486 wiphy_name(hw->wiphy));
2958 goto err_free_queues; 3487 goto err_free_queues;
2959 } 3488 }
2960 3489
@@ -2962,16 +3491,18 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
2962 mwl8k_hw_reset(priv); 3491 mwl8k_hw_reset(priv);
2963 3492
2964 /* Ask userland hotplug daemon for the device firmware */ 3493 /* Ask userland hotplug daemon for the device firmware */
2965 rc = mwl8k_request_firmware(priv, (u32)id->driver_data); 3494 rc = mwl8k_request_firmware(priv);
2966 if (rc) { 3495 if (rc) {
2967 printk(KERN_ERR "%s: Firmware files not found\n", priv->name); 3496 printk(KERN_ERR "%s: Firmware files not found\n",
3497 wiphy_name(hw->wiphy));
2968 goto err_free_irq; 3498 goto err_free_irq;
2969 } 3499 }
2970 3500
2971 /* Load firmware into hardware */ 3501 /* Load firmware into hardware */
2972 rc = mwl8k_load_firmware(priv); 3502 rc = mwl8k_load_firmware(hw);
2973 if (rc) { 3503 if (rc) {
2974 printk(KERN_ERR "%s: Cannot start firmware\n", priv->name); 3504 printk(KERN_ERR "%s: Cannot start firmware\n",
3505 wiphy_name(hw->wiphy));
2975 goto err_stop_firmware; 3506 goto err_stop_firmware;
2976 } 3507 }
2977 3508
@@ -2986,16 +3517,31 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
2986 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 3517 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2987 3518
2988 /* Get config data, mac addrs etc */ 3519 /* Get config data, mac addrs etc */
2989 rc = mwl8k_cmd_get_hw_spec(hw); 3520 if (priv->ap_fw) {
3521 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3522 if (!rc)
3523 rc = mwl8k_cmd_set_hw_spec(hw);
3524 } else {
3525 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3526 }
2990 if (rc) { 3527 if (rc) {
2991 printk(KERN_ERR "%s: Cannot initialise firmware\n", priv->name); 3528 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3529 wiphy_name(hw->wiphy));
2992 goto err_stop_firmware; 3530 goto err_stop_firmware;
2993 } 3531 }
2994 3532
2995 /* Turn radio off */ 3533 /* Turn radio off */
2996 rc = mwl8k_cmd_802_11_radio_disable(hw); 3534 rc = mwl8k_cmd_802_11_radio_disable(hw);
2997 if (rc) { 3535 if (rc) {
2998 printk(KERN_ERR "%s: Cannot disable\n", priv->name); 3536 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3537 goto err_stop_firmware;
3538 }
3539
3540 /* Clear MAC address */
3541 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3542 if (rc) {
3543 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3544 wiphy_name(hw->wiphy));
2999 goto err_stop_firmware; 3545 goto err_stop_firmware;
3000 } 3546 }
3001 3547
@@ -3005,13 +3551,15 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
3005 3551
3006 rc = ieee80211_register_hw(hw); 3552 rc = ieee80211_register_hw(hw);
3007 if (rc) { 3553 if (rc) {
3008 printk(KERN_ERR "%s: Cannot register device\n", priv->name); 3554 printk(KERN_ERR "%s: Cannot register device\n",
3555 wiphy_name(hw->wiphy));
3009 goto err_stop_firmware; 3556 goto err_stop_firmware;
3010 } 3557 }
3011 3558
3012 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n", 3559 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3013 wiphy_name(hw->wiphy), priv->part_num, priv->hw_rev, 3560 wiphy_name(hw->wiphy), priv->device_info->part_name,
3014 hw->wiphy->perm_addr, 3561 priv->hw_rev, hw->wiphy->perm_addr,
3562 priv->ap_fw ? "AP" : "STA",
3015 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff, 3563 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3016 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff); 3564 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3017 3565
@@ -3038,8 +3586,8 @@ err_iounmap:
3038 if (priv->regs != NULL) 3586 if (priv->regs != NULL)
3039 pci_iounmap(pdev, priv->regs); 3587 pci_iounmap(pdev, priv->regs);
3040 3588
3041 if (priv->config_wq != NULL) 3589 if (priv->sram != NULL)
3042 destroy_workqueue(priv->config_wq); 3590 pci_iounmap(pdev, priv->sram);
3043 3591
3044 pci_set_drvdata(pdev, NULL); 3592 pci_set_drvdata(pdev, NULL);
3045 ieee80211_free_hw(hw); 3593 ieee80211_free_hw(hw);
@@ -3073,9 +3621,6 @@ static void __devexit mwl8k_remove(struct pci_dev *pdev)
3073 /* Remove tx reclaim tasklet */ 3621 /* Remove tx reclaim tasklet */
3074 tasklet_kill(&priv->tx_reclaim_task); 3622 tasklet_kill(&priv->tx_reclaim_task);
3075 3623
3076 /* Stop config thread */
3077 destroy_workqueue(priv->config_wq);
3078
3079 /* Stop hardware */ 3624 /* Stop hardware */
3080 mwl8k_hw_reset(priv); 3625 mwl8k_hw_reset(priv);
3081 3626
@@ -3088,10 +3633,10 @@ static void __devexit mwl8k_remove(struct pci_dev *pdev)
3088 3633
3089 mwl8k_rxq_deinit(hw, 0); 3634 mwl8k_rxq_deinit(hw, 0);
3090 3635
3091 pci_free_consistent(priv->pdev, 4, 3636 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3092 priv->cookie, priv->cookie_dma);
3093 3637
3094 pci_iounmap(pdev, priv->regs); 3638 pci_iounmap(pdev, priv->regs);
3639 pci_iounmap(pdev, priv->sram);
3095 pci_set_drvdata(pdev, NULL); 3640 pci_set_drvdata(pdev, NULL);
3096 ieee80211_free_hw(hw); 3641 ieee80211_free_hw(hw);
3097 pci_release_regions(pdev); 3642 pci_release_regions(pdev);
@@ -3100,7 +3645,7 @@ static void __devexit mwl8k_remove(struct pci_dev *pdev)
3100 3645
3101static struct pci_driver mwl8k_driver = { 3646static struct pci_driver mwl8k_driver = {
3102 .name = MWL8K_NAME, 3647 .name = MWL8K_NAME,
3103 .id_table = mwl8k_table, 3648 .id_table = mwl8k_pci_id_table,
3104 .probe = mwl8k_probe, 3649 .probe = mwl8k_probe,
3105 .remove = __devexit_p(mwl8k_remove), 3650 .remove = __devexit_p(mwl8k_remove),
3106 .shutdown = __devexit_p(mwl8k_shutdown), 3651 .shutdown = __devexit_p(mwl8k_shutdown),
@@ -3118,3 +3663,8 @@ static void __exit mwl8k_exit(void)
3118 3663
3119module_init(mwl8k_init); 3664module_init(mwl8k_init);
3120module_exit(mwl8k_exit); 3665module_exit(mwl8k_exit);
3666
3667MODULE_DESCRIPTION(MWL8K_DESC);
3668MODULE_VERSION(MWL8K_VERSION);
3669MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3670MODULE_LICENSE("GPL");
diff --git a/drivers/net/wireless/netwave_cs.c b/drivers/net/wireless/netwave_cs.c
deleted file mode 100644
index 9498b46c99a4..000000000000
--- a/drivers/net/wireless/netwave_cs.c
+++ /dev/null
@@ -1,1389 +0,0 @@
1/*********************************************************************
2 *
3 * Filename: netwave_cs.c
4 * Version: 0.4.1
5 * Description: Netwave AirSurfer Wireless LAN PC Card driver
6 * Status: Experimental.
7 * Authors: John Markus Bjørndalen <johnm@cs.uit.no>
8 * Dag Brattli <dagb@cs.uit.no>
9 * David Hinds <dahinds@users.sourceforge.net>
10 * Created at: A long time ago!
11 * Modified at: Mon Nov 10 11:54:37 1997
12 * Modified by: Dag Brattli <dagb@cs.uit.no>
13 *
14 * Copyright (c) 1997 University of Tromsø, Norway
15 *
16 * Revision History:
17 *
18 * 08-Nov-97 15:14:47 John Markus Bjørndalen <johnm@cs.uit.no>
19 * - Fixed some bugs in netwave_rx and cleaned it up a bit.
20 * (One of the bugs would have destroyed packets when receiving
21 * multiple packets per interrupt).
22 * - Cleaned up parts of newave_hw_xmit.
23 * - A few general cleanups.
24 * 24-Oct-97 13:17:36 Dag Brattli <dagb@cs.uit.no>
25 * - Fixed netwave_rx receive function (got updated docs)
26 * Others:
27 * - Changed name from xircnw to netwave, take a look at
28 * http://www.netwave-wireless.com
29 * - Some reorganizing of the code
30 * - Removed possible race condition between interrupt handler and transmit
31 * function
32 * - Started to add wireless extensions, but still needs some coding
33 * - Added watchdog for better handling of transmission timeouts
34 * (hopefully this works better)
35 ********************************************************************/
36
37/* To have statistics (just packets sent) define this */
38#undef NETWAVE_STATS
39
40#include <linux/module.h>
41#include <linux/kernel.h>
42#include <linux/init.h>
43#include <linux/types.h>
44#include <linux/fcntl.h>
45#include <linux/interrupt.h>
46#include <linux/ptrace.h>
47#include <linux/ioport.h>
48#include <linux/in.h>
49#include <linux/slab.h>
50#include <linux/string.h>
51#include <linux/timer.h>
52#include <linux/errno.h>
53#include <linux/netdevice.h>
54#include <linux/etherdevice.h>
55#include <linux/skbuff.h>
56#include <linux/bitops.h>
57#include <linux/wireless.h>
58#include <net/iw_handler.h>
59
60#include <pcmcia/cs_types.h>
61#include <pcmcia/cs.h>
62#include <pcmcia/cistpl.h>
63#include <pcmcia/cisreg.h>
64#include <pcmcia/ds.h>
65#include <pcmcia/mem_op.h>
66
67#include <asm/system.h>
68#include <asm/io.h>
69#include <asm/dma.h>
70
71#define NETWAVE_REGOFF 0x8000
72/* The Netwave IO registers, offsets to iobase */
73#define NETWAVE_REG_COR 0x0
74#define NETWAVE_REG_CCSR 0x2
75#define NETWAVE_REG_ASR 0x4
76#define NETWAVE_REG_IMR 0xa
77#define NETWAVE_REG_PMR 0xc
78#define NETWAVE_REG_IOLOW 0x6
79#define NETWAVE_REG_IOHI 0x7
80#define NETWAVE_REG_IOCONTROL 0x8
81#define NETWAVE_REG_DATA 0xf
82/* The Netwave Extended IO registers, offsets to RamBase */
83#define NETWAVE_EREG_ASCC 0x114
84#define NETWAVE_EREG_RSER 0x120
85#define NETWAVE_EREG_RSERW 0x124
86#define NETWAVE_EREG_TSER 0x130
87#define NETWAVE_EREG_TSERW 0x134
88#define NETWAVE_EREG_CB 0x100
89#define NETWAVE_EREG_SPCQ 0x154
90#define NETWAVE_EREG_SPU 0x155
91#define NETWAVE_EREG_LIF 0x14e
92#define NETWAVE_EREG_ISPLQ 0x156
93#define NETWAVE_EREG_HHC 0x158
94#define NETWAVE_EREG_NI 0x16e
95#define NETWAVE_EREG_MHS 0x16b
96#define NETWAVE_EREG_TDP 0x140
97#define NETWAVE_EREG_RDP 0x150
98#define NETWAVE_EREG_PA 0x160
99#define NETWAVE_EREG_EC 0x180
100#define NETWAVE_EREG_CRBP 0x17a
101#define NETWAVE_EREG_ARW 0x166
102
103/*
104 * Commands used in the extended command buffer
105 * NETWAVE_EREG_CB (0x100-0x10F)
106 */
107#define NETWAVE_CMD_NOP 0x00
108#define NETWAVE_CMD_SRC 0x01
109#define NETWAVE_CMD_STC 0x02
110#define NETWAVE_CMD_AMA 0x03
111#define NETWAVE_CMD_DMA 0x04
112#define NETWAVE_CMD_SAMA 0x05
113#define NETWAVE_CMD_ER 0x06
114#define NETWAVE_CMD_DR 0x07
115#define NETWAVE_CMD_TL 0x08
116#define NETWAVE_CMD_SRP 0x09
117#define NETWAVE_CMD_SSK 0x0a
118#define NETWAVE_CMD_SMD 0x0b
119#define NETWAVE_CMD_SAPD 0x0c
120#define NETWAVE_CMD_SSS 0x11
121/* End of Command marker */
122#define NETWAVE_CMD_EOC 0x00
123
124/* ASR register bits */
125#define NETWAVE_ASR_RXRDY 0x80
126#define NETWAVE_ASR_TXBA 0x01
127
128#define TX_TIMEOUT ((32*HZ)/100)
129
130static const unsigned int imrConfRFU1 = 0x10; /* RFU interrupt mask, keep high */
131static const unsigned int imrConfIENA = 0x02; /* Interrupt enable */
132
133static const unsigned int corConfIENA = 0x01; /* Interrupt enable */
134static const unsigned int corConfLVLREQ = 0x40; /* Keep high */
135
136static const unsigned int rxConfRxEna = 0x80; /* Receive Enable */
137static const unsigned int rxConfMAC = 0x20; /* MAC host receive mode*/
138static const unsigned int rxConfPro = 0x10; /* Promiscuous */
139static const unsigned int rxConfAMP = 0x08; /* Accept Multicast Packets */
140static const unsigned int rxConfBcast = 0x04; /* Accept Broadcast Packets */
141
142static const unsigned int txConfTxEna = 0x80; /* Transmit Enable */
143static const unsigned int txConfMAC = 0x20; /* Host sends MAC mode */
144static const unsigned int txConfEUD = 0x10; /* Enable Uni-Data packets */
145static const unsigned int txConfKey = 0x02; /* Scramble data packets */
146static const unsigned int txConfLoop = 0x01; /* Loopback mode */
147
148/*
149 All the PCMCIA modules use PCMCIA_DEBUG to control debugging. If
150 you do not define PCMCIA_DEBUG at all, all the debug code will be
151 left out. If you compile with PCMCIA_DEBUG=0, the debug code will
152 be present but disabled -- but it can then be enabled for specific
153 modules at load time with a 'pc_debug=#' option to insmod.
154*/
155
156#ifdef PCMCIA_DEBUG
157static int pc_debug = PCMCIA_DEBUG;
158module_param(pc_debug, int, 0);
159#define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
160static char *version =
161"netwave_cs.c 0.3.0 Thu Jul 17 14:36:02 1997 (John Markus Bjørndalen)\n";
162#else
163#define DEBUG(n, args...)
164#endif
165
166/*====================================================================*/
167
168/* Parameters that can be set with 'insmod' */
169
170/* Choose the domain, default is 0x100 */
171static u_int domain = 0x100;
172
173/* Scramble key, range from 0x0 to 0xffff.
174 * 0x0 is no scrambling.
175 */
176static u_int scramble_key = 0x0;
177
178/* Shared memory speed, in ns. The documentation states that
179 * the card should not be read faster than every 400ns.
180 * This timing should be provided by the HBA. If it becomes a
181 * problem, try setting mem_speed to 400.
182 */
183static int mem_speed;
184
185module_param(domain, int, 0);
186module_param(scramble_key, int, 0);
187module_param(mem_speed, int, 0);
188
189/*====================================================================*/
190
191/* PCMCIA (Card Services) related functions */
192static void netwave_release(struct pcmcia_device *link); /* Card removal */
193static int netwave_pcmcia_config(struct pcmcia_device *arg); /* Runs after card
194 insertion */
195static void netwave_detach(struct pcmcia_device *p_dev); /* Destroy instance */
196
197/* Hardware configuration */
198static void netwave_doreset(unsigned int iobase, u_char __iomem *ramBase);
199static void netwave_reset(struct net_device *dev);
200
201/* Misc device stuff */
202static int netwave_open(struct net_device *dev); /* Open the device */
203static int netwave_close(struct net_device *dev); /* Close the device */
204
205/* Packet transmission and Packet reception */
206static netdev_tx_t netwave_start_xmit( struct sk_buff *skb,
207 struct net_device *dev);
208static int netwave_rx( struct net_device *dev);
209
210/* Interrupt routines */
211static irqreturn_t netwave_interrupt(int irq, void *dev_id);
212static void netwave_watchdog(struct net_device *);
213
214/* Wireless extensions */
215static struct iw_statistics* netwave_get_wireless_stats(struct net_device *dev);
216
217static void set_multicast_list(struct net_device *dev);
218
219/*
220 A struct pcmcia_device structure has fields for most things that are needed
221 to keep track of a socket, but there will usually be some device
222 specific information that also needs to be kept track of. The
223 'priv' pointer in a struct pcmcia_device structure can be used to point to
224 a device-specific private data structure, like this.
225
226 A driver needs to provide a dev_node_t structure for each device
227 on a card. In some cases, there is only one device per card (for
228 example, ethernet cards, modems). In other cases, there may be
229 many actual or logical devices (SCSI adapters, memory cards with
230 multiple partitions). The dev_node_t structures need to be kept
231 in a linked list starting at the 'dev' field of a struct pcmcia_device
232 structure. We allocate them in the card's private data structure,
233 because they generally can't be allocated dynamically.
234*/
235
236static const struct iw_handler_def netwave_handler_def;
237
238#define SIOCGIPSNAP SIOCIWFIRSTPRIV + 1 /* Site Survey Snapshot */
239
240#define MAX_ESA 10
241
242typedef struct net_addr {
243 u_char addr48[6];
244} net_addr;
245
246struct site_survey {
247 u_short length;
248 u_char struct_revision;
249 u_char roaming_state;
250
251 u_char sp_existsFlag;
252 u_char sp_link_quality;
253 u_char sp_max_link_quality;
254 u_char linkQualityGoodFairBoundary;
255 u_char linkQualityFairPoorBoundary;
256 u_char sp_utilization;
257 u_char sp_goodness;
258 u_char sp_hotheadcount;
259 u_char roaming_condition;
260
261 net_addr sp;
262 u_char numAPs;
263 net_addr nearByAccessPoints[MAX_ESA];
264};
265
266typedef struct netwave_private {
267 struct pcmcia_device *p_dev;
268 spinlock_t spinlock; /* Serialize access to the hardware (SMP) */
269 dev_node_t node;
270 u_char __iomem *ramBase;
271 int timeoutCounter;
272 int lastExec;
273 struct timer_list watchdog; /* To avoid blocking state */
274 struct site_survey nss;
275 struct iw_statistics iw_stats; /* Wireless stats */
276} netwave_private;
277
278/*
279 * The Netwave card is little-endian, so won't work for big endian
280 * systems.
281 */
282static inline unsigned short get_uint16(u_char __iomem *staddr)
283{
284 return readw(staddr); /* Return only 16 bits */
285}
286
287static inline short get_int16(u_char __iomem * staddr)
288{
289 return readw(staddr);
290}
291
292/*
293 * Wait until the WOC (Write Operation Complete) bit in the
294 * ASR (Adapter Status Register) is asserted.
295 * This should have aborted if it takes too long time.
296 */
297static inline void wait_WOC(unsigned int iobase)
298{
299 /* Spin lock */
300 while ((inb(iobase + NETWAVE_REG_ASR) & 0x8) != 0x8) ;
301}
302
303static void netwave_snapshot(netwave_private *priv, u_char __iomem *ramBase,
304 unsigned int iobase) {
305 u_short resultBuffer;
306
307 /* if time since last snapshot is > 1 sec. (100 jiffies?) then take
308 * new snapshot, else return cached data. This is the recommended rate.
309 */
310 if ( jiffies - priv->lastExec > 100) {
311 /* Take site survey snapshot */
312 /*printk( KERN_DEBUG "Taking new snapshot. %ld\n", jiffies -
313 priv->lastExec); */
314 wait_WOC(iobase);
315 writeb(NETWAVE_CMD_SSS, ramBase + NETWAVE_EREG_CB + 0);
316 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 1);
317 wait_WOC(iobase);
318
319 /* Get result and copy to cach */
320 resultBuffer = readw(ramBase + NETWAVE_EREG_CRBP);
321 copy_from_pc( &priv->nss, ramBase+resultBuffer,
322 sizeof(struct site_survey));
323 }
324}
325
326/*
327 * Function netwave_get_wireless_stats (dev)
328 *
329 * Wireless extensions statistics
330 *
331 */
332static struct iw_statistics *netwave_get_wireless_stats(struct net_device *dev)
333{
334 unsigned long flags;
335 unsigned int iobase = dev->base_addr;
336 netwave_private *priv = netdev_priv(dev);
337 u_char __iomem *ramBase = priv->ramBase;
338 struct iw_statistics* wstats;
339
340 wstats = &priv->iw_stats;
341
342 spin_lock_irqsave(&priv->spinlock, flags);
343
344 netwave_snapshot( priv, ramBase, iobase);
345
346 wstats->status = priv->nss.roaming_state;
347 wstats->qual.qual = readb( ramBase + NETWAVE_EREG_SPCQ);
348 wstats->qual.level = readb( ramBase + NETWAVE_EREG_ISPLQ);
349 wstats->qual.noise = readb( ramBase + NETWAVE_EREG_SPU) & 0x3f;
350 wstats->discard.nwid = 0L;
351 wstats->discard.code = 0L;
352 wstats->discard.misc = 0L;
353
354 spin_unlock_irqrestore(&priv->spinlock, flags);
355
356 return &priv->iw_stats;
357}
358
359static const struct net_device_ops netwave_netdev_ops = {
360 .ndo_open = netwave_open,
361 .ndo_stop = netwave_close,
362 .ndo_start_xmit = netwave_start_xmit,
363 .ndo_set_multicast_list = set_multicast_list,
364 .ndo_tx_timeout = netwave_watchdog,
365 .ndo_change_mtu = eth_change_mtu,
366 .ndo_set_mac_address = eth_mac_addr,
367 .ndo_validate_addr = eth_validate_addr,
368};
369
370/*
371 * Function netwave_attach (void)
372 *
373 * Creates an "instance" of the driver, allocating local data
374 * structures for one device. The device is registered with Card
375 * Services.
376 *
377 * The dev_link structure is initialized, but we don't actually
378 * configure the card at this point -- we wait until we receive a
379 * card insertion event.
380 */
381static int netwave_probe(struct pcmcia_device *link)
382{
383 struct net_device *dev;
384 netwave_private *priv;
385
386 DEBUG(0, "netwave_attach()\n");
387
388 /* Initialize the struct pcmcia_device structure */
389 dev = alloc_etherdev(sizeof(netwave_private));
390 if (!dev)
391 return -ENOMEM;
392 priv = netdev_priv(dev);
393 priv->p_dev = link;
394 link->priv = dev;
395
396 /* The io structure describes IO port mapping */
397 link->io.NumPorts1 = 16;
398 link->io.Attributes1 = IO_DATA_PATH_WIDTH_16;
399 /* link->io.NumPorts2 = 16;
400 link->io.Attributes2 = IO_DATA_PATH_WIDTH_16; */
401 link->io.IOAddrLines = 5;
402
403 /* Interrupt setup */
404 link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING | IRQ_HANDLE_PRESENT;
405 link->irq.IRQInfo1 = IRQ_LEVEL_ID;
406 link->irq.Handler = &netwave_interrupt;
407
408 /* General socket configuration */
409 link->conf.Attributes = CONF_ENABLE_IRQ;
410 link->conf.IntType = INT_MEMORY_AND_IO;
411 link->conf.ConfigIndex = 1;
412
413 /* Netwave private struct init. link/dev/node already taken care of,
414 * other stuff zero'd - Jean II */
415 spin_lock_init(&priv->spinlock);
416
417 /* Netwave specific entries in the device structure */
418 dev->netdev_ops = &netwave_netdev_ops;
419 /* wireless extensions */
420 dev->wireless_handlers = &netwave_handler_def;
421
422 dev->watchdog_timeo = TX_TIMEOUT;
423
424 link->irq.Instance = dev;
425
426 return netwave_pcmcia_config( link);
427} /* netwave_attach */
428
429/*
430 * Function netwave_detach (link)
431 *
432 * This deletes a driver "instance". The device is de-registered
433 * with Card Services. If it has been released, all local data
434 * structures are freed. Otherwise, the structures will be freed
435 * when the device is released.
436 */
437static void netwave_detach(struct pcmcia_device *link)
438{
439 struct net_device *dev = link->priv;
440
441 DEBUG(0, "netwave_detach(0x%p)\n", link);
442
443 netwave_release(link);
444
445 if (link->dev_node)
446 unregister_netdev(dev);
447
448 free_netdev(dev);
449} /* netwave_detach */
450
451/*
452 * Wireless Handler : get protocol name
453 */
454static int netwave_get_name(struct net_device *dev,
455 struct iw_request_info *info,
456 union iwreq_data *wrqu,
457 char *extra)
458{
459 strcpy(wrqu->name, "Netwave");
460 return 0;
461}
462
463/*
464 * Wireless Handler : set Network ID
465 */
466static int netwave_set_nwid(struct net_device *dev,
467 struct iw_request_info *info,
468 union iwreq_data *wrqu,
469 char *extra)
470{
471 unsigned long flags;
472 unsigned int iobase = dev->base_addr;
473 netwave_private *priv = netdev_priv(dev);
474 u_char __iomem *ramBase = priv->ramBase;
475
476 /* Disable interrupts & save flags */
477 spin_lock_irqsave(&priv->spinlock, flags);
478
479 if(!wrqu->nwid.disabled) {
480 domain = wrqu->nwid.value;
481 printk( KERN_DEBUG "Setting domain to 0x%x%02x\n",
482 (domain >> 8) & 0x01, domain & 0xff);
483 wait_WOC(iobase);
484 writeb(NETWAVE_CMD_SMD, ramBase + NETWAVE_EREG_CB + 0);
485 writeb( domain & 0xff, ramBase + NETWAVE_EREG_CB + 1);
486 writeb((domain >>8 ) & 0x01,ramBase + NETWAVE_EREG_CB+2);
487 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 3);
488 }
489
490 /* ReEnable interrupts & restore flags */
491 spin_unlock_irqrestore(&priv->spinlock, flags);
492
493 return 0;
494}
495
496/*
497 * Wireless Handler : get Network ID
498 */
499static int netwave_get_nwid(struct net_device *dev,
500 struct iw_request_info *info,
501 union iwreq_data *wrqu,
502 char *extra)
503{
504 wrqu->nwid.value = domain;
505 wrqu->nwid.disabled = 0;
506 wrqu->nwid.fixed = 1;
507 return 0;
508}
509
510/*
511 * Wireless Handler : set scramble key
512 */
513static int netwave_set_scramble(struct net_device *dev,
514 struct iw_request_info *info,
515 union iwreq_data *wrqu,
516 char *key)
517{
518 unsigned long flags;
519 unsigned int iobase = dev->base_addr;
520 netwave_private *priv = netdev_priv(dev);
521 u_char __iomem *ramBase = priv->ramBase;
522
523 /* Disable interrupts & save flags */
524 spin_lock_irqsave(&priv->spinlock, flags);
525
526 scramble_key = (key[0] << 8) | key[1];
527 wait_WOC(iobase);
528 writeb(NETWAVE_CMD_SSK, ramBase + NETWAVE_EREG_CB + 0);
529 writeb(scramble_key & 0xff, ramBase + NETWAVE_EREG_CB + 1);
530 writeb((scramble_key>>8) & 0xff, ramBase + NETWAVE_EREG_CB + 2);
531 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 3);
532
533 /* ReEnable interrupts & restore flags */
534 spin_unlock_irqrestore(&priv->spinlock, flags);
535
536 return 0;
537}
538
539/*
540 * Wireless Handler : get scramble key
541 */
542static int netwave_get_scramble(struct net_device *dev,
543 struct iw_request_info *info,
544 union iwreq_data *wrqu,
545 char *key)
546{
547 key[1] = scramble_key & 0xff;
548 key[0] = (scramble_key>>8) & 0xff;
549 wrqu->encoding.flags = IW_ENCODE_ENABLED;
550 wrqu->encoding.length = 2;
551 return 0;
552}
553
554/*
555 * Wireless Handler : get mode
556 */
557static int netwave_get_mode(struct net_device *dev,
558 struct iw_request_info *info,
559 union iwreq_data *wrqu,
560 char *extra)
561{
562 if(domain & 0x100)
563 wrqu->mode = IW_MODE_INFRA;
564 else
565 wrqu->mode = IW_MODE_ADHOC;
566
567 return 0;
568}
569
570/*
571 * Wireless Handler : get range info
572 */
573static int netwave_get_range(struct net_device *dev,
574 struct iw_request_info *info,
575 union iwreq_data *wrqu,
576 char *extra)
577{
578 struct iw_range *range = (struct iw_range *) extra;
579 int ret = 0;
580
581 /* Set the length (very important for backward compatibility) */
582 wrqu->data.length = sizeof(struct iw_range);
583
584 /* Set all the info we don't care or don't know about to zero */
585 memset(range, 0, sizeof(struct iw_range));
586
587 /* Set the Wireless Extension versions */
588 range->we_version_compiled = WIRELESS_EXT;
589 range->we_version_source = 9; /* Nothing for us in v10 and v11 */
590
591 /* Set information in the range struct */
592 range->throughput = 450 * 1000; /* don't argue on this ! */
593 range->min_nwid = 0x0000;
594 range->max_nwid = 0x01FF;
595
596 range->num_channels = range->num_frequency = 0;
597
598 range->sensitivity = 0x3F;
599 range->max_qual.qual = 255;
600 range->max_qual.level = 255;
601 range->max_qual.noise = 0;
602
603 range->num_bitrates = 1;
604 range->bitrate[0] = 1000000; /* 1 Mb/s */
605
606 range->encoding_size[0] = 2; /* 16 bits scrambling */
607 range->num_encoding_sizes = 1;
608 range->max_encoding_tokens = 1; /* Only one key possible */
609
610 return ret;
611}
612
613/*
614 * Wireless Private Handler : get snapshot
615 */
616static int netwave_get_snap(struct net_device *dev,
617 struct iw_request_info *info,
618 union iwreq_data *wrqu,
619 char *extra)
620{
621 unsigned long flags;
622 unsigned int iobase = dev->base_addr;
623 netwave_private *priv = netdev_priv(dev);
624 u_char __iomem *ramBase = priv->ramBase;
625
626 /* Disable interrupts & save flags */
627 spin_lock_irqsave(&priv->spinlock, flags);
628
629 /* Take snapshot of environment */
630 netwave_snapshot( priv, ramBase, iobase);
631 wrqu->data.length = priv->nss.length;
632 memcpy(extra, (u_char *) &priv->nss, sizeof( struct site_survey));
633
634 priv->lastExec = jiffies;
635
636 /* ReEnable interrupts & restore flags */
637 spin_unlock_irqrestore(&priv->spinlock, flags);
638
639 return(0);
640}
641
642/*
643 * Structures to export the Wireless Handlers
644 * This is the stuff that are treated the wireless extensions (iwconfig)
645 */
646
647static const struct iw_priv_args netwave_private_args[] = {
648/*{ cmd, set_args, get_args, name } */
649 { SIOCGIPSNAP, 0,
650 IW_PRIV_TYPE_BYTE | IW_PRIV_SIZE_FIXED | sizeof(struct site_survey),
651 "getsitesurvey" },
652};
653
654static const iw_handler netwave_handler[] =
655{
656 NULL, /* SIOCSIWNAME */
657 netwave_get_name, /* SIOCGIWNAME */
658 netwave_set_nwid, /* SIOCSIWNWID */
659 netwave_get_nwid, /* SIOCGIWNWID */
660 NULL, /* SIOCSIWFREQ */
661 NULL, /* SIOCGIWFREQ */
662 NULL, /* SIOCSIWMODE */
663 netwave_get_mode, /* SIOCGIWMODE */
664 NULL, /* SIOCSIWSENS */
665 NULL, /* SIOCGIWSENS */
666 NULL, /* SIOCSIWRANGE */
667 netwave_get_range, /* SIOCGIWRANGE */
668 NULL, /* SIOCSIWPRIV */
669 NULL, /* SIOCGIWPRIV */
670 NULL, /* SIOCSIWSTATS */
671 NULL, /* SIOCGIWSTATS */
672 NULL, /* SIOCSIWSPY */
673 NULL, /* SIOCGIWSPY */
674 NULL, /* -- hole -- */
675 NULL, /* -- hole -- */
676 NULL, /* SIOCSIWAP */
677 NULL, /* SIOCGIWAP */
678 NULL, /* -- hole -- */
679 NULL, /* SIOCGIWAPLIST */
680 NULL, /* -- hole -- */
681 NULL, /* -- hole -- */
682 NULL, /* SIOCSIWESSID */
683 NULL, /* SIOCGIWESSID */
684 NULL, /* SIOCSIWNICKN */
685 NULL, /* SIOCGIWNICKN */
686 NULL, /* -- hole -- */
687 NULL, /* -- hole -- */
688 NULL, /* SIOCSIWRATE */
689 NULL, /* SIOCGIWRATE */
690 NULL, /* SIOCSIWRTS */
691 NULL, /* SIOCGIWRTS */
692 NULL, /* SIOCSIWFRAG */
693 NULL, /* SIOCGIWFRAG */
694 NULL, /* SIOCSIWTXPOW */
695 NULL, /* SIOCGIWTXPOW */
696 NULL, /* SIOCSIWRETRY */
697 NULL, /* SIOCGIWRETRY */
698 netwave_set_scramble, /* SIOCSIWENCODE */
699 netwave_get_scramble, /* SIOCGIWENCODE */
700};
701
702static const iw_handler netwave_private_handler[] =
703{
704 NULL, /* SIOCIWFIRSTPRIV */
705 netwave_get_snap, /* SIOCIWFIRSTPRIV + 1 */
706};
707
708static const struct iw_handler_def netwave_handler_def =
709{
710 .num_standard = ARRAY_SIZE(netwave_handler),
711 .num_private = ARRAY_SIZE(netwave_private_handler),
712 .num_private_args = ARRAY_SIZE(netwave_private_args),
713 .standard = (iw_handler *) netwave_handler,
714 .private = (iw_handler *) netwave_private_handler,
715 .private_args = (struct iw_priv_args *) netwave_private_args,
716 .get_wireless_stats = netwave_get_wireless_stats,
717};
718
719/*
720 * Function netwave_pcmcia_config (link)
721 *
722 * netwave_pcmcia_config() is scheduled to run after a CARD_INSERTION
723 * event is received, to configure the PCMCIA socket, and to make the
724 * device available to the system.
725 *
726 */
727
728#define CS_CHECK(fn, ret) \
729do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
730
731static int netwave_pcmcia_config(struct pcmcia_device *link) {
732 struct net_device *dev = link->priv;
733 netwave_private *priv = netdev_priv(dev);
734 int i, j, last_ret, last_fn;
735 win_req_t req;
736 memreq_t mem;
737 u_char __iomem *ramBase = NULL;
738
739 DEBUG(0, "netwave_pcmcia_config(0x%p)\n", link);
740
741 /*
742 * Try allocating IO ports. This tries a few fixed addresses.
743 * If you want, you can also read the card's config table to
744 * pick addresses -- see the serial driver for an example.
745 */
746 for (i = j = 0x0; j < 0x400; j += 0x20) {
747 link->io.BasePort1 = j ^ 0x300;
748 i = pcmcia_request_io(link, &link->io);
749 if (i == 0)
750 break;
751 }
752 if (i != 0) {
753 cs_error(link, RequestIO, i);
754 goto failed;
755 }
756
757 /*
758 * Now allocate an interrupt line. Note that this does not
759 * actually assign a handler to the interrupt.
760 */
761 CS_CHECK(RequestIRQ, pcmcia_request_irq(link, &link->irq));
762
763 /*
764 * This actually configures the PCMCIA socket -- setting up
765 * the I/O windows and the interrupt mapping.
766 */
767 CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf));
768
769 /*
770 * Allocate a 32K memory window. Note that the struct pcmcia_device
771 * structure provides space for one window handle -- if your
772 * device needs several windows, you'll need to keep track of
773 * the handles in your private data structure, dev->priv.
774 */
775 DEBUG(1, "Setting mem speed of %d\n", mem_speed);
776
777 req.Attributes = WIN_DATA_WIDTH_8|WIN_MEMORY_TYPE_CM|WIN_ENABLE;
778 req.Base = 0; req.Size = 0x8000;
779 req.AccessSpeed = mem_speed;
780 CS_CHECK(RequestWindow, pcmcia_request_window(&link, &req, &link->win));
781 mem.CardOffset = 0x20000; mem.Page = 0;
782 CS_CHECK(MapMemPage, pcmcia_map_mem_page(link->win, &mem));
783
784 /* Store base address of the common window frame */
785 ramBase = ioremap(req.Base, 0x8000);
786 priv->ramBase = ramBase;
787
788 dev->irq = link->irq.AssignedIRQ;
789 dev->base_addr = link->io.BasePort1;
790 SET_NETDEV_DEV(dev, &handle_to_dev(link));
791
792 if (register_netdev(dev) != 0) {
793 printk(KERN_DEBUG "netwave_cs: register_netdev() failed\n");
794 goto failed;
795 }
796
797 strcpy(priv->node.dev_name, dev->name);
798 link->dev_node = &priv->node;
799
800 /* Reset card before reading physical address */
801 netwave_doreset(dev->base_addr, ramBase);
802
803 /* Read the ethernet address and fill in the Netwave registers. */
804 for (i = 0; i < 6; i++)
805 dev->dev_addr[i] = readb(ramBase + NETWAVE_EREG_PA + i);
806
807 printk(KERN_INFO "%s: Netwave: port %#3lx, irq %d, mem %lx, "
808 "id %c%c, hw_addr %pM\n",
809 dev->name, dev->base_addr, dev->irq,
810 (u_long) ramBase,
811 (int) readb(ramBase+NETWAVE_EREG_NI),
812 (int) readb(ramBase+NETWAVE_EREG_NI+1),
813 dev->dev_addr);
814
815 /* get revision words */
816 printk(KERN_DEBUG "Netwave_reset: revision %04x %04x\n",
817 get_uint16(ramBase + NETWAVE_EREG_ARW),
818 get_uint16(ramBase + NETWAVE_EREG_ARW+2));
819 return 0;
820
821cs_failed:
822 cs_error(link, last_fn, last_ret);
823failed:
824 netwave_release(link);
825 return -ENODEV;
826} /* netwave_pcmcia_config */
827
828/*
829 * Function netwave_release (arg)
830 *
831 * After a card is removed, netwave_release() will unregister the net
832 * device, and release the PCMCIA configuration. If the device is
833 * still open, this will be postponed until it is closed.
834 */
835static void netwave_release(struct pcmcia_device *link)
836{
837 struct net_device *dev = link->priv;
838 netwave_private *priv = netdev_priv(dev);
839
840 DEBUG(0, "netwave_release(0x%p)\n", link);
841
842 pcmcia_disable_device(link);
843 if (link->win)
844 iounmap(priv->ramBase);
845}
846
847static int netwave_suspend(struct pcmcia_device *link)
848{
849 struct net_device *dev = link->priv;
850
851 if (link->open)
852 netif_device_detach(dev);
853
854 return 0;
855}
856
857static int netwave_resume(struct pcmcia_device *link)
858{
859 struct net_device *dev = link->priv;
860
861 if (link->open) {
862 netwave_reset(dev);
863 netif_device_attach(dev);
864 }
865
866 return 0;
867}
868
869
870/*
871 * Function netwave_doreset (ioBase, ramBase)
872 *
873 * Proper hardware reset of the card.
874 */
875static void netwave_doreset(unsigned int ioBase, u_char __iomem *ramBase)
876{
877 /* Reset card */
878 wait_WOC(ioBase);
879 outb(0x80, ioBase + NETWAVE_REG_PMR);
880 writeb(0x08, ramBase + NETWAVE_EREG_ASCC); /* Bit 3 is WOC */
881 outb(0x0, ioBase + NETWAVE_REG_PMR); /* release reset */
882}
883
884/*
885 * Function netwave_reset (dev)
886 *
887 * Reset and restore all of the netwave registers
888 */
889static void netwave_reset(struct net_device *dev) {
890 /* u_char state; */
891 netwave_private *priv = netdev_priv(dev);
892 u_char __iomem *ramBase = priv->ramBase;
893 unsigned int iobase = dev->base_addr;
894
895 DEBUG(0, "netwave_reset: Done with hardware reset\n");
896
897 priv->timeoutCounter = 0;
898
899 /* Reset card */
900 netwave_doreset(iobase, ramBase);
901 printk(KERN_DEBUG "netwave_reset: Done with hardware reset\n");
902
903 /* Write a NOP to check the card */
904 wait_WOC(iobase);
905 writeb(NETWAVE_CMD_NOP, ramBase + NETWAVE_EREG_CB + 0);
906 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 1);
907
908 /* Set receive conf */
909 wait_WOC(iobase);
910 writeb(NETWAVE_CMD_SRC, ramBase + NETWAVE_EREG_CB + 0);
911 writeb(rxConfRxEna + rxConfBcast, ramBase + NETWAVE_EREG_CB + 1);
912 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 2);
913
914 /* Set transmit conf */
915 wait_WOC(iobase);
916 writeb(NETWAVE_CMD_STC, ramBase + NETWAVE_EREG_CB + 0);
917 writeb(txConfTxEna, ramBase + NETWAVE_EREG_CB + 1);
918 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 2);
919
920 /* Now set the MU Domain */
921 printk(KERN_DEBUG "Setting domain to 0x%x%02x\n", (domain >> 8) & 0x01, domain & 0xff);
922 wait_WOC(iobase);
923 writeb(NETWAVE_CMD_SMD, ramBase + NETWAVE_EREG_CB + 0);
924 writeb(domain & 0xff, ramBase + NETWAVE_EREG_CB + 1);
925 writeb((domain>>8) & 0x01, ramBase + NETWAVE_EREG_CB + 2);
926 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 3);
927
928 /* Set scramble key */
929 printk(KERN_DEBUG "Setting scramble key to 0x%x\n", scramble_key);
930 wait_WOC(iobase);
931 writeb(NETWAVE_CMD_SSK, ramBase + NETWAVE_EREG_CB + 0);
932 writeb(scramble_key & 0xff, ramBase + NETWAVE_EREG_CB + 1);
933 writeb((scramble_key>>8) & 0xff, ramBase + NETWAVE_EREG_CB + 2);
934 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 3);
935
936 /* Enable interrupts, bit 4 high to keep unused
937 * source from interrupting us, bit 2 high to
938 * set interrupt enable, 567 to enable TxDN,
939 * RxErr and RxRdy
940 */
941 wait_WOC(iobase);
942 outb(imrConfIENA+imrConfRFU1, iobase + NETWAVE_REG_IMR);
943
944 /* Hent 4 bytes fra 0x170. Skal vaere 0a,29,88,36
945 * waitWOC
946 * skriv 80 til d000:3688
947 * sjekk om det ble 80
948 */
949
950 /* Enable Receiver */
951 wait_WOC(iobase);
952 writeb(NETWAVE_CMD_ER, ramBase + NETWAVE_EREG_CB + 0);
953 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 1);
954
955 /* Set the IENA bit in COR */
956 wait_WOC(iobase);
957 outb(corConfIENA + corConfLVLREQ, iobase + NETWAVE_REG_COR);
958}
959
960/*
961 * Function netwave_hw_xmit (data, len, dev)
962 */
963static int netwave_hw_xmit(unsigned char* data, int len,
964 struct net_device* dev) {
965 unsigned long flags;
966 unsigned int TxFreeList,
967 curBuff,
968 MaxData,
969 DataOffset;
970 int tmpcount;
971
972 netwave_private *priv = netdev_priv(dev);
973 u_char __iomem * ramBase = priv->ramBase;
974 unsigned int iobase = dev->base_addr;
975
976 /* Disable interrupts & save flags */
977 spin_lock_irqsave(&priv->spinlock, flags);
978
979 /* Check if there are transmit buffers available */
980 wait_WOC(iobase);
981 if ((inb(iobase+NETWAVE_REG_ASR) & NETWAVE_ASR_TXBA) == 0) {
982 /* No buffers available */
983 printk(KERN_DEBUG "netwave_hw_xmit: %s - no xmit buffers available.\n",
984 dev->name);
985 spin_unlock_irqrestore(&priv->spinlock, flags);
986 return 1;
987 }
988
989 dev->stats.tx_bytes += len;
990
991 DEBUG(3, "Transmitting with SPCQ %x SPU %x LIF %x ISPLQ %x\n",
992 readb(ramBase + NETWAVE_EREG_SPCQ),
993 readb(ramBase + NETWAVE_EREG_SPU),
994 readb(ramBase + NETWAVE_EREG_LIF),
995 readb(ramBase + NETWAVE_EREG_ISPLQ));
996
997 /* Now try to insert it into the adapters free memory */
998 wait_WOC(iobase);
999 TxFreeList = get_uint16(ramBase + NETWAVE_EREG_TDP);
1000 MaxData = get_uint16(ramBase + NETWAVE_EREG_TDP+2);
1001 DataOffset = get_uint16(ramBase + NETWAVE_EREG_TDP+4);
1002
1003 DEBUG(3, "TxFreeList %x, MaxData %x, DataOffset %x\n",
1004 TxFreeList, MaxData, DataOffset);
1005
1006 /* Copy packet to the adapter fragment buffers */
1007 curBuff = TxFreeList;
1008 tmpcount = 0;
1009 while (tmpcount < len) {
1010 int tmplen = len - tmpcount;
1011 copy_to_pc(ramBase + curBuff + DataOffset, data + tmpcount,
1012 (tmplen < MaxData) ? tmplen : MaxData);
1013 tmpcount += MaxData;
1014
1015 /* Advance to next buffer */
1016 curBuff = get_uint16(ramBase + curBuff);
1017 }
1018
1019 /* Now issue transmit list */
1020 wait_WOC(iobase);
1021 writeb(NETWAVE_CMD_TL, ramBase + NETWAVE_EREG_CB + 0);
1022 writeb(len & 0xff, ramBase + NETWAVE_EREG_CB + 1);
1023 writeb((len>>8) & 0xff, ramBase + NETWAVE_EREG_CB + 2);
1024 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 3);
1025
1026 spin_unlock_irqrestore(&priv->spinlock, flags);
1027 return 0;
1028}
1029
1030static netdev_tx_t netwave_start_xmit(struct sk_buff *skb,
1031 struct net_device *dev) {
1032 /* This flag indicate that the hardware can't perform a transmission.
1033 * Theoritically, NET3 check it before sending a packet to the driver,
1034 * but in fact it never do that and pool continuously.
1035 * As the watchdog will abort too long transmissions, we are quite safe...
1036 */
1037
1038 netif_stop_queue(dev);
1039
1040 {
1041 short length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
1042 unsigned char* buf = skb->data;
1043
1044 if (netwave_hw_xmit( buf, length, dev) == 1) {
1045 /* Some error, let's make them call us another time? */
1046 netif_start_queue(dev);
1047 }
1048 dev->trans_start = jiffies;
1049 }
1050 dev_kfree_skb(skb);
1051
1052 return NETDEV_TX_OK;
1053} /* netwave_start_xmit */
1054
1055/*
1056 * Function netwave_interrupt (irq, dev_id)
1057 *
1058 * This function is the interrupt handler for the Netwave card. This
1059 * routine will be called whenever:
1060 * 1. A packet is received.
1061 * 2. A packet has successfully been transferred and the unit is
1062 * ready to transmit another packet.
1063 * 3. A command has completed execution.
1064 */
1065static irqreturn_t netwave_interrupt(int irq, void* dev_id)
1066{
1067 unsigned int iobase;
1068 u_char __iomem *ramBase;
1069 struct net_device *dev = (struct net_device *)dev_id;
1070 struct netwave_private *priv = netdev_priv(dev);
1071 struct pcmcia_device *link = priv->p_dev;
1072 int i;
1073
1074 if (!netif_device_present(dev))
1075 return IRQ_NONE;
1076
1077 iobase = dev->base_addr;
1078 ramBase = priv->ramBase;
1079
1080 /* Now find what caused the interrupt, check while interrupts ready */
1081 for (i = 0; i < 10; i++) {
1082 u_char status;
1083
1084 wait_WOC(iobase);
1085 if (!(inb(iobase+NETWAVE_REG_CCSR) & 0x02))
1086 break; /* None of the interrupt sources asserted (normal exit) */
1087
1088 status = inb(iobase + NETWAVE_REG_ASR);
1089
1090 if (!pcmcia_dev_present(link)) {
1091 DEBUG(1, "netwave_interrupt: Interrupt with status 0x%x "
1092 "from removed or suspended card!\n", status);
1093 break;
1094 }
1095
1096 /* RxRdy */
1097 if (status & 0x80) {
1098 netwave_rx(dev);
1099 /* wait_WOC(iobase); */
1100 /* RxRdy cannot be reset directly by the host */
1101 }
1102 /* RxErr */
1103 if (status & 0x40) {
1104 u_char rser;
1105
1106 rser = readb(ramBase + NETWAVE_EREG_RSER);
1107
1108 if (rser & 0x04) {
1109 ++dev->stats.rx_dropped;
1110 ++dev->stats.rx_crc_errors;
1111 }
1112 if (rser & 0x02)
1113 ++dev->stats.rx_frame_errors;
1114
1115 /* Clear the RxErr bit in RSER. RSER+4 is the
1116 * write part. Also clear the RxCRC (0x04) and
1117 * RxBig (0x02) bits if present */
1118 wait_WOC(iobase);
1119 writeb(0x40 | (rser & 0x06), ramBase + NETWAVE_EREG_RSER + 4);
1120
1121 /* Write bit 6 high to ASCC to clear RxErr in ASR,
1122 * WOC must be set first!
1123 */
1124 wait_WOC(iobase);
1125 writeb(0x40, ramBase + NETWAVE_EREG_ASCC);
1126
1127 /* Remember to count up dev->stats on error packets */
1128 ++dev->stats.rx_errors;
1129 }
1130 /* TxDN */
1131 if (status & 0x20) {
1132 int txStatus;
1133
1134 txStatus = readb(ramBase + NETWAVE_EREG_TSER);
1135 DEBUG(3, "Transmit done. TSER = %x id %x\n",
1136 txStatus, readb(ramBase + NETWAVE_EREG_TSER + 1));
1137
1138 if (txStatus & 0x20) {
1139 /* Transmitting was okay, clear bits */
1140 wait_WOC(iobase);
1141 writeb(0x2f, ramBase + NETWAVE_EREG_TSER + 4);
1142 ++dev->stats.tx_packets;
1143 }
1144
1145 if (txStatus & 0xd0) {
1146 if (txStatus & 0x80) {
1147 ++dev->stats.collisions; /* Because of /proc/net/dev*/
1148 /* ++dev->stats.tx_aborted_errors; */
1149 /* printk("Collision. %ld\n", jiffies - dev->trans_start); */
1150 }
1151 if (txStatus & 0x40)
1152 ++dev->stats.tx_carrier_errors;
1153 /* 0x80 TxGU Transmit giveup - nine times and no luck
1154 * 0x40 TxNOAP No access point. Discarded packet.
1155 * 0x10 TxErr Transmit error. Always set when
1156 * TxGU and TxNOAP is set. (Those are the only ones
1157 * to set TxErr).
1158 */
1159 DEBUG(3, "netwave_interrupt: TxDN with error status %x\n",
1160 txStatus);
1161
1162 /* Clear out TxGU, TxNOAP, TxErr and TxTrys */
1163 wait_WOC(iobase);
1164 writeb(0xdf & txStatus, ramBase+NETWAVE_EREG_TSER+4);
1165 ++dev->stats.tx_errors;
1166 }
1167 DEBUG(3, "New status is TSER %x ASR %x\n",
1168 readb(ramBase + NETWAVE_EREG_TSER),
1169 inb(iobase + NETWAVE_REG_ASR));
1170
1171 netif_wake_queue(dev);
1172 }
1173 /* TxBA, this would trigger on all error packets received */
1174 /* if (status & 0x01) {
1175 DEBUG(4, "Transmit buffers available, %x\n", status);
1176 }
1177 */
1178 }
1179 /* Handled if we looped at least one time - Jean II */
1180 return IRQ_RETVAL(i);
1181} /* netwave_interrupt */
1182
1183/*
1184 * Function netwave_watchdog (a)
1185 *
1186 * Watchdog : when we start a transmission, we set a timer in the
1187 * kernel. If the transmission complete, this timer is disabled. If
1188 * it expire, we reset the card.
1189 *
1190 */
1191static void netwave_watchdog(struct net_device *dev) {
1192
1193 DEBUG(1, "%s: netwave_watchdog: watchdog timer expired\n", dev->name);
1194 netwave_reset(dev);
1195 dev->trans_start = jiffies;
1196 netif_wake_queue(dev);
1197} /* netwave_watchdog */
1198
1199static int netwave_rx(struct net_device *dev)
1200{
1201 netwave_private *priv = netdev_priv(dev);
1202 u_char __iomem *ramBase = priv->ramBase;
1203 unsigned int iobase = dev->base_addr;
1204 u_char rxStatus;
1205 struct sk_buff *skb = NULL;
1206 unsigned int curBuffer,
1207 rcvList;
1208 int rcvLen;
1209 int tmpcount = 0;
1210 int dataCount, dataOffset;
1211 int i;
1212 u_char *ptr;
1213
1214 DEBUG(3, "xinw_rx: Receiving ... \n");
1215
1216 /* Receive max 10 packets for now. */
1217 for (i = 0; i < 10; i++) {
1218 /* Any packets? */
1219 wait_WOC(iobase);
1220 rxStatus = readb(ramBase + NETWAVE_EREG_RSER);
1221 if ( !( rxStatus & 0x80)) /* No more packets */
1222 break;
1223
1224 /* Check if multicast/broadcast or other */
1225 /* multicast = (rxStatus & 0x20); */
1226
1227 /* The receive list pointer and length of the packet */
1228 wait_WOC(iobase);
1229 rcvLen = get_int16( ramBase + NETWAVE_EREG_RDP);
1230 rcvList = get_uint16( ramBase + NETWAVE_EREG_RDP + 2);
1231
1232 if (rcvLen < 0) {
1233 printk(KERN_DEBUG "netwave_rx: Receive packet with len %d\n",
1234 rcvLen);
1235 return 0;
1236 }
1237
1238 skb = dev_alloc_skb(rcvLen+5);
1239 if (skb == NULL) {
1240 DEBUG(1, "netwave_rx: Could not allocate an sk_buff of "
1241 "length %d\n", rcvLen);
1242 ++dev->stats.rx_dropped;
1243 /* Tell the adapter to skip the packet */
1244 wait_WOC(iobase);
1245 writeb(NETWAVE_CMD_SRP, ramBase + NETWAVE_EREG_CB + 0);
1246 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 1);
1247 return 0;
1248 }
1249
1250 skb_reserve( skb, 2); /* Align IP on 16 byte */
1251 skb_put( skb, rcvLen);
1252
1253 /* Copy packet fragments to the skb data area */
1254 ptr = (u_char*) skb->data;
1255 curBuffer = rcvList;
1256 tmpcount = 0;
1257 while ( tmpcount < rcvLen) {
1258 /* Get length and offset of current buffer */
1259 dataCount = get_uint16( ramBase+curBuffer+2);
1260 dataOffset = get_uint16( ramBase+curBuffer+4);
1261
1262 copy_from_pc( ptr + tmpcount,
1263 ramBase+curBuffer+dataOffset, dataCount);
1264
1265 tmpcount += dataCount;
1266
1267 /* Point to next buffer */
1268 curBuffer = get_uint16(ramBase + curBuffer);
1269 }
1270
1271 skb->protocol = eth_type_trans(skb,dev);
1272 /* Queue packet for network layer */
1273 netif_rx(skb);
1274
1275 dev->stats.rx_packets++;
1276 dev->stats.rx_bytes += rcvLen;
1277
1278 /* Got the packet, tell the adapter to skip it */
1279 wait_WOC(iobase);
1280 writeb(NETWAVE_CMD_SRP, ramBase + NETWAVE_EREG_CB + 0);
1281 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 1);
1282 DEBUG(3, "Packet reception ok\n");
1283 }
1284 return 0;
1285}
1286
1287static int netwave_open(struct net_device *dev) {
1288 netwave_private *priv = netdev_priv(dev);
1289 struct pcmcia_device *link = priv->p_dev;
1290
1291 DEBUG(1, "netwave_open: starting.\n");
1292
1293 if (!pcmcia_dev_present(link))
1294 return -ENODEV;
1295
1296 link->open++;
1297
1298 netif_start_queue(dev);
1299 netwave_reset(dev);
1300
1301 return 0;
1302}
1303
1304static int netwave_close(struct net_device *dev) {
1305 netwave_private *priv = netdev_priv(dev);
1306 struct pcmcia_device *link = priv->p_dev;
1307
1308 DEBUG(1, "netwave_close: finishing.\n");
1309
1310 link->open--;
1311 netif_stop_queue(dev);
1312
1313 return 0;
1314}
1315
1316static struct pcmcia_device_id netwave_ids[] = {
1317 PCMCIA_DEVICE_PROD_ID12("Xircom", "CreditCard Netwave", 0x2e3ee845, 0x54e28a28),
1318 PCMCIA_DEVICE_NULL,
1319};
1320MODULE_DEVICE_TABLE(pcmcia, netwave_ids);
1321
1322static struct pcmcia_driver netwave_driver = {
1323 .owner = THIS_MODULE,
1324 .drv = {
1325 .name = "netwave_cs",
1326 },
1327 .probe = netwave_probe,
1328 .remove = netwave_detach,
1329 .id_table = netwave_ids,
1330 .suspend = netwave_suspend,
1331 .resume = netwave_resume,
1332};
1333
1334static int __init init_netwave_cs(void)
1335{
1336 return pcmcia_register_driver(&netwave_driver);
1337}
1338
1339static void __exit exit_netwave_cs(void)
1340{
1341 pcmcia_unregister_driver(&netwave_driver);
1342}
1343
1344module_init(init_netwave_cs);
1345module_exit(exit_netwave_cs);
1346
1347/* Set or clear the multicast filter for this adaptor.
1348 num_addrs == -1 Promiscuous mode, receive all packets
1349 num_addrs == 0 Normal mode, clear multicast list
1350 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1351 best-effort filtering.
1352 */
1353static void set_multicast_list(struct net_device *dev)
1354{
1355 unsigned int iobase = dev->base_addr;
1356 netwave_private *priv = netdev_priv(dev);
1357 u_char __iomem * ramBase = priv->ramBase;
1358 u_char rcvMode = 0;
1359
1360#ifdef PCMCIA_DEBUG
1361 if (pc_debug > 2) {
1362 static int old;
1363 if (old != dev->mc_count) {
1364 old = dev->mc_count;
1365 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1366 dev->name, dev->mc_count);
1367 }
1368 }
1369#endif
1370
1371 if (dev->mc_count || (dev->flags & IFF_ALLMULTI)) {
1372 /* Multicast Mode */
1373 rcvMode = rxConfRxEna + rxConfAMP + rxConfBcast;
1374 } else if (dev->flags & IFF_PROMISC) {
1375 /* Promiscous mode */
1376 rcvMode = rxConfRxEna + rxConfPro + rxConfAMP + rxConfBcast;
1377 } else {
1378 /* Normal mode */
1379 rcvMode = rxConfRxEna + rxConfBcast;
1380 }
1381
1382 /* printk("netwave set_multicast_list: rcvMode to %x\n", rcvMode);*/
1383 /* Now set receive mode */
1384 wait_WOC(iobase);
1385 writeb(NETWAVE_CMD_SRC, ramBase + NETWAVE_EREG_CB + 0);
1386 writeb(rcvMode, ramBase + NETWAVE_EREG_CB + 1);
1387 writeb(NETWAVE_CMD_EOC, ramBase + NETWAVE_EREG_CB + 2);
1388}
1389MODULE_LICENSE("GPL");
diff --git a/drivers/net/wireless/orinoco/Kconfig b/drivers/net/wireless/orinoco/Kconfig
index dce652054afd..e2a2c18920aa 100644
--- a/drivers/net/wireless/orinoco/Kconfig
+++ b/drivers/net/wireless/orinoco/Kconfig
@@ -1,6 +1,6 @@
1config HERMES 1config HERMES
2 tristate "Hermes chipset 802.11b support (Orinoco/Prism2/Symbol)" 2 tristate "Hermes chipset 802.11b support (Orinoco/Prism2/Symbol)"
3 depends on (PPC_PMAC || PCI || PCMCIA) && WLAN_80211 3 depends on (PPC_PMAC || PCI || PCMCIA)
4 depends on CFG80211 && CFG80211_WEXT 4 depends on CFG80211 && CFG80211_WEXT
5 select WIRELESS_EXT 5 select WIRELESS_EXT
6 select WEXT_SPY 6 select WEXT_SPY
diff --git a/drivers/net/wireless/p54/Kconfig b/drivers/net/wireless/p54/Kconfig
index b45d6a4ed1e8..b0342a520bf1 100644
--- a/drivers/net/wireless/p54/Kconfig
+++ b/drivers/net/wireless/p54/Kconfig
@@ -1,6 +1,6 @@
1config P54_COMMON 1config P54_COMMON
2 tristate "Softmac Prism54 support" 2 tristate "Softmac Prism54 support"
3 depends on MAC80211 && WLAN_80211 && EXPERIMENTAL 3 depends on MAC80211 && EXPERIMENTAL
4 select FW_LOADER 4 select FW_LOADER
5 ---help--- 5 ---help---
6 This is common code for isl38xx/stlc45xx based modules. 6 This is common code for isl38xx/stlc45xx based modules.
diff --git a/drivers/net/wireless/p54/eeprom.c b/drivers/net/wireless/p54/eeprom.c
index 0efe67deedee..8e3818f6832e 100644
--- a/drivers/net/wireless/p54/eeprom.c
+++ b/drivers/net/wireless/p54/eeprom.c
@@ -126,7 +126,7 @@ static int p54_generate_band(struct ieee80211_hw *dev,
126 int ret = -ENOMEM; 126 int ret = -ENOMEM;
127 127
128 if ((!list->entries) || (!list->band_channel_num[band])) 128 if ((!list->entries) || (!list->band_channel_num[band]))
129 return 0; 129 return -EINVAL;
130 130
131 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 131 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
132 if (!tmp) 132 if (!tmp)
@@ -158,6 +158,7 @@ static int p54_generate_band(struct ieee80211_hw *dev,
158 (list->channels[i].data & CHAN_HAS_CURVE ? "" : 158 (list->channels[i].data & CHAN_HAS_CURVE ? "" :
159 " [curve data]"), 159 " [curve data]"),
160 list->channels[i].index, list->channels[i].freq); 160 list->channels[i].index, list->channels[i].freq);
161 continue;
161 } 162 }
162 163
163 tmp->channels[j].band = list->channels[i].band; 164 tmp->channels[j].band = list->channels[i].band;
@@ -165,7 +166,16 @@ static int p54_generate_band(struct ieee80211_hw *dev,
165 j++; 166 j++;
166 } 167 }
167 168
168 tmp->n_channels = list->band_channel_num[band]; 169 if (j == 0) {
170 printk(KERN_ERR "%s: Disabling totally damaged %s band.\n",
171 wiphy_name(dev->wiphy), (band == IEEE80211_BAND_2GHZ) ?
172 "2 GHz" : "5 GHz");
173
174 ret = -ENODATA;
175 goto err_out;
176 }
177
178 tmp->n_channels = j;
169 old = priv->band_table[band]; 179 old = priv->band_table[band];
170 priv->band_table[band] = tmp; 180 priv->band_table[band] = tmp;
171 if (old) { 181 if (old) {
@@ -228,13 +238,13 @@ static int p54_generate_channel_lists(struct ieee80211_hw *dev)
228 struct p54_common *priv = dev->priv; 238 struct p54_common *priv = dev->priv;
229 struct p54_channel_list *list; 239 struct p54_channel_list *list;
230 unsigned int i, j, max_channel_num; 240 unsigned int i, j, max_channel_num;
231 int ret = -ENOMEM; 241 int ret = 0;
232 u16 freq; 242 u16 freq;
233 243
234 if ((priv->iq_autocal_len != priv->curve_data->entries) || 244 if ((priv->iq_autocal_len != priv->curve_data->entries) ||
235 (priv->iq_autocal_len != priv->output_limit->entries)) 245 (priv->iq_autocal_len != priv->output_limit->entries))
236 printk(KERN_ERR "%s: EEPROM is damaged... you may not be able" 246 printk(KERN_ERR "%s: Unsupported or damaged EEPROM detected. "
237 "to use all channels with this device.\n", 247 "You may not be able to use all channels.\n",
238 wiphy_name(dev->wiphy)); 248 wiphy_name(dev->wiphy));
239 249
240 max_channel_num = max_t(unsigned int, priv->output_limit->entries, 250 max_channel_num = max_t(unsigned int, priv->output_limit->entries,
@@ -243,8 +253,10 @@ static int p54_generate_channel_lists(struct ieee80211_hw *dev)
243 priv->curve_data->entries); 253 priv->curve_data->entries);
244 254
245 list = kzalloc(sizeof(*list), GFP_KERNEL); 255 list = kzalloc(sizeof(*list), GFP_KERNEL);
246 if (!list) 256 if (!list) {
257 ret = -ENOMEM;
247 goto free; 258 goto free;
259 }
248 260
249 list->max_entries = max_channel_num; 261 list->max_entries = max_channel_num;
250 list->channels = kzalloc(sizeof(struct p54_channel_entry) * 262 list->channels = kzalloc(sizeof(struct p54_channel_entry) *
@@ -282,13 +294,8 @@ static int p54_generate_channel_lists(struct ieee80211_hw *dev)
282 p54_compare_channels, NULL); 294 p54_compare_channels, NULL);
283 295
284 for (i = 0, j = 0; i < IEEE80211_NUM_BANDS; i++) { 296 for (i = 0, j = 0; i < IEEE80211_NUM_BANDS; i++) {
285 if (list->band_channel_num[i]) { 297 if (p54_generate_band(dev, list, i) == 0)
286 ret = p54_generate_band(dev, list, i);
287 if (ret)
288 goto free;
289
290 j++; 298 j++;
291 }
292 } 299 }
293 if (j == 0) { 300 if (j == 0) {
294 /* no useable band available. */ 301 /* no useable band available. */
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index 390c0c7b3ac2..bf60689aaabb 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -1,6 +1,6 @@
1menuconfig RT2X00 1menuconfig RT2X00
2 tristate "Ralink driver support" 2 tristate "Ralink driver support"
3 depends on MAC80211 && WLAN_80211 3 depends on MAC80211
4 ---help--- 4 ---help---
5 This will enable the support for the Ralink drivers, 5 This will enable the support for the Ralink drivers,
6 developed in the rt2x00 project <http://rt2x00.serialmonkey.com>. 6 developed in the rt2x00 project <http://rt2x00.serialmonkey.com>.
@@ -64,8 +64,9 @@ config RT2800PCI_SOC
64 default y 64 default y
65 65
66config RT2800PCI 66config RT2800PCI
67 tristate "Ralink rt2800 (PCI/PCMCIA) support" 67 tristate "Ralink rt2800 (PCI/PCMCIA) support (VERY EXPERIMENTAL)"
68 depends on (RT2800PCI_PCI || RT2800PCI_SOC) && EXPERIMENTAL 68 depends on (RT2800PCI_PCI || RT2800PCI_SOC) && EXPERIMENTAL
69 select RT2800_LIB
69 select RT2X00_LIB_PCI if RT2800PCI_PCI 70 select RT2X00_LIB_PCI if RT2800PCI_PCI
70 select RT2X00_LIB_SOC if RT2800PCI_SOC 71 select RT2X00_LIB_SOC if RT2800PCI_SOC
71 select RT2X00_LIB_HT 72 select RT2X00_LIB_HT
@@ -77,6 +78,9 @@ config RT2800PCI
77 This adds support for rt2800 wireless chipset family. 78 This adds support for rt2800 wireless chipset family.
78 Supported chips: RT2760, RT2790, RT2860, RT2880, RT2890 & RT3052 79 Supported chips: RT2760, RT2790, RT2860, RT2880, RT2890 & RT3052
79 80
81 This driver is non-functional at the moment and is intended for
82 developers.
83
80 When compiled as a module, this driver will be called "rt2800pci.ko". 84 When compiled as a module, this driver will be called "rt2800pci.ko".
81 85
82config RT2500USB 86config RT2500USB
@@ -104,8 +108,9 @@ config RT73USB
104 When compiled as a module, this driver will be called rt73usb. 108 When compiled as a module, this driver will be called rt73usb.
105 109
106config RT2800USB 110config RT2800USB
107 tristate "Ralink rt2800 (USB) support" 111 tristate "Ralink rt2800 (USB) support (EXPERIMENTAL)"
108 depends on USB && EXPERIMENTAL 112 depends on USB && EXPERIMENTAL
113 select RT2800_LIB
109 select RT2X00_LIB_USB 114 select RT2X00_LIB_USB
110 select RT2X00_LIB_HT 115 select RT2X00_LIB_HT
111 select RT2X00_LIB_FIRMWARE 116 select RT2X00_LIB_FIRMWARE
@@ -115,8 +120,15 @@ config RT2800USB
115 This adds experimental support for rt2800 wireless chipset family. 120 This adds experimental support for rt2800 wireless chipset family.
116 Supported chips: RT2770, RT2870 & RT3070. 121 Supported chips: RT2770, RT2870 & RT3070.
117 122
123 Known issues:
124 - support for RT2870 chips doesn't work with 802.11n APs yet
125 - support for RT3070 chips is non-functional at the moment
126
118 When compiled as a module, this driver will be called "rt2800usb.ko". 127 When compiled as a module, this driver will be called "rt2800usb.ko".
119 128
129config RT2800_LIB
130 tristate
131
120config RT2X00_LIB_PCI 132config RT2X00_LIB_PCI
121 tristate 133 tristate
122 select RT2X00_LIB 134 select RT2X00_LIB
diff --git a/drivers/net/wireless/rt2x00/Makefile b/drivers/net/wireless/rt2x00/Makefile
index 912f5f67e159..971339858297 100644
--- a/drivers/net/wireless/rt2x00/Makefile
+++ b/drivers/net/wireless/rt2x00/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_RT2X00_LIB) += rt2x00lib.o
13obj-$(CONFIG_RT2X00_LIB_PCI) += rt2x00pci.o 13obj-$(CONFIG_RT2X00_LIB_PCI) += rt2x00pci.o
14obj-$(CONFIG_RT2X00_LIB_SOC) += rt2x00soc.o 14obj-$(CONFIG_RT2X00_LIB_SOC) += rt2x00soc.o
15obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00usb.o 15obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00usb.o
16obj-$(CONFIG_RT2800_LIB) += rt2800lib.o
16obj-$(CONFIG_RT2400PCI) += rt2400pci.o 17obj-$(CONFIG_RT2400PCI) += rt2400pci.o
17obj-$(CONFIG_RT2500PCI) += rt2500pci.o 18obj-$(CONFIG_RT2500PCI) += rt2500pci.o
18obj-$(CONFIG_RT61PCI) += rt61pci.o 19obj-$(CONFIG_RT61PCI) += rt61pci.o
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
new file mode 100644
index 000000000000..d9b6a72e6d27
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -0,0 +1,1816 @@
1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800
23 Abstract: Data structures and registers for the rt2800 modules.
24 Supported chipsets: RT2800E, RT2800ED & RT2800U.
25 */
26
27#ifndef RT2800_H
28#define RT2800_H
29
30/*
31 * RF chip defines.
32 *
33 * RF2820 2.4G 2T3R
34 * RF2850 2.4G/5G 2T3R
35 * RF2720 2.4G 1T2R
36 * RF2750 2.4G/5G 1T2R
37 * RF3020 2.4G 1T1R
38 * RF2020 2.4G B/G
39 * RF3021 2.4G 1T2R
40 * RF3022 2.4G 2T2R
41 * RF3052 2.4G 2T2R
42 */
43#define RF2820 0x0001
44#define RF2850 0x0002
45#define RF2720 0x0003
46#define RF2750 0x0004
47#define RF3020 0x0005
48#define RF2020 0x0006
49#define RF3021 0x0007
50#define RF3022 0x0008
51#define RF3052 0x0009
52
53/*
54 * Chipset version.
55 */
56#define RT2860C_VERSION 0x28600100
57#define RT2860D_VERSION 0x28600101
58#define RT2880E_VERSION 0x28720200
59#define RT2883_VERSION 0x28830300
60#define RT3070_VERSION 0x30700200
61
62/*
63 * Signal information.
64 * Default offset is required for RSSI <-> dBm conversion.
65 */
66#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
67
68/*
69 * Register layout information.
70 */
71#define CSR_REG_BASE 0x1000
72#define CSR_REG_SIZE 0x0800
73#define EEPROM_BASE 0x0000
74#define EEPROM_SIZE 0x0110
75#define BBP_BASE 0x0000
76#define BBP_SIZE 0x0080
77#define RF_BASE 0x0004
78#define RF_SIZE 0x0010
79
80/*
81 * Number of TX queues.
82 */
83#define NUM_TX_QUEUES 4
84
85/*
86 * USB registers.
87 */
88
89/*
90 * INT_SOURCE_CSR: Interrupt source register.
91 * Write one to clear corresponding bit.
92 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
93 */
94#define INT_SOURCE_CSR 0x0200
95#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
96#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
97#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
98#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
99#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
100#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
101#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
102#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
103#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
104#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
105#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
106#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
107#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
108#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
109#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
110#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
111#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
112#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
113
114/*
115 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
116 */
117#define INT_MASK_CSR 0x0204
118#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
119#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
120#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
121#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
122#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
123#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
124#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
125#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
126#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
127#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
128#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
129#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
130#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
131#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
132#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
133#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
134#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
135#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
136
137/*
138 * WPDMA_GLO_CFG
139 */
140#define WPDMA_GLO_CFG 0x0208
141#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
142#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
143#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
144#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
145#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
146#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
147#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
148#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
149#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
150
151/*
152 * WPDMA_RST_IDX
153 */
154#define WPDMA_RST_IDX 0x020c
155#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
156#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
157#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
158#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
159#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
160#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
161#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
162
163/*
164 * DELAY_INT_CFG
165 */
166#define DELAY_INT_CFG 0x0210
167#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
168#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
169#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
170#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
171#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
172#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
173
174/*
175 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
176 * AIFSN0: AC_BE
177 * AIFSN1: AC_BK
178 * AIFSN2: AC_VI
179 * AIFSN3: AC_VO
180 */
181#define WMM_AIFSN_CFG 0x0214
182#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
183#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
184#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
185#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
186
187/*
188 * WMM_CWMIN_CSR: CWmin for each EDCA AC
189 * CWMIN0: AC_BE
190 * CWMIN1: AC_BK
191 * CWMIN2: AC_VI
192 * CWMIN3: AC_VO
193 */
194#define WMM_CWMIN_CFG 0x0218
195#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
196#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
197#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
198#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
199
200/*
201 * WMM_CWMAX_CSR: CWmax for each EDCA AC
202 * CWMAX0: AC_BE
203 * CWMAX1: AC_BK
204 * CWMAX2: AC_VI
205 * CWMAX3: AC_VO
206 */
207#define WMM_CWMAX_CFG 0x021c
208#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
209#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
210#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
211#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
212
213/*
214 * AC_TXOP0: AC_BK/AC_BE TXOP register
215 * AC0TXOP: AC_BK in unit of 32us
216 * AC1TXOP: AC_BE in unit of 32us
217 */
218#define WMM_TXOP0_CFG 0x0220
219#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
220#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
221
222/*
223 * AC_TXOP1: AC_VO/AC_VI TXOP register
224 * AC2TXOP: AC_VI in unit of 32us
225 * AC3TXOP: AC_VO in unit of 32us
226 */
227#define WMM_TXOP1_CFG 0x0224
228#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
229#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
230
231/*
232 * GPIO_CTRL_CFG:
233 */
234#define GPIO_CTRL_CFG 0x0228
235#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
236#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
237#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
238#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
239#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
240#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
241#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
242#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
243#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
244
245/*
246 * MCU_CMD_CFG
247 */
248#define MCU_CMD_CFG 0x022c
249
250/*
251 * AC_BK register offsets
252 */
253#define TX_BASE_PTR0 0x0230
254#define TX_MAX_CNT0 0x0234
255#define TX_CTX_IDX0 0x0238
256#define TX_DTX_IDX0 0x023c
257
258/*
259 * AC_BE register offsets
260 */
261#define TX_BASE_PTR1 0x0240
262#define TX_MAX_CNT1 0x0244
263#define TX_CTX_IDX1 0x0248
264#define TX_DTX_IDX1 0x024c
265
266/*
267 * AC_VI register offsets
268 */
269#define TX_BASE_PTR2 0x0250
270#define TX_MAX_CNT2 0x0254
271#define TX_CTX_IDX2 0x0258
272#define TX_DTX_IDX2 0x025c
273
274/*
275 * AC_VO register offsets
276 */
277#define TX_BASE_PTR3 0x0260
278#define TX_MAX_CNT3 0x0264
279#define TX_CTX_IDX3 0x0268
280#define TX_DTX_IDX3 0x026c
281
282/*
283 * HCCA register offsets
284 */
285#define TX_BASE_PTR4 0x0270
286#define TX_MAX_CNT4 0x0274
287#define TX_CTX_IDX4 0x0278
288#define TX_DTX_IDX4 0x027c
289
290/*
291 * MGMT register offsets
292 */
293#define TX_BASE_PTR5 0x0280
294#define TX_MAX_CNT5 0x0284
295#define TX_CTX_IDX5 0x0288
296#define TX_DTX_IDX5 0x028c
297
298/*
299 * RX register offsets
300 */
301#define RX_BASE_PTR 0x0290
302#define RX_MAX_CNT 0x0294
303#define RX_CRX_IDX 0x0298
304#define RX_DRX_IDX 0x029c
305
306/*
307 * PBF_SYS_CTRL
308 * HOST_RAM_WRITE: enable Host program ram write selection
309 */
310#define PBF_SYS_CTRL 0x0400
311#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
312#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
313
314/*
315 * HOST-MCU shared memory
316 */
317#define HOST_CMD_CSR 0x0404
318#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
319
320/*
321 * PBF registers
322 * Most are for debug. Driver doesn't touch PBF register.
323 */
324#define PBF_CFG 0x0408
325#define PBF_MAX_PCNT 0x040c
326#define PBF_CTRL 0x0410
327#define PBF_INT_STA 0x0414
328#define PBF_INT_ENA 0x0418
329
330/*
331 * BCN_OFFSET0:
332 */
333#define BCN_OFFSET0 0x042c
334#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
335#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
336#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
337#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
338
339/*
340 * BCN_OFFSET1:
341 */
342#define BCN_OFFSET1 0x0430
343#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
344#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
345#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
346#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
347
348/*
349 * PBF registers
350 * Most are for debug. Driver doesn't touch PBF register.
351 */
352#define TXRXQ_PCNT 0x0438
353#define PBF_DBG 0x043c
354
355/*
356 * RF registers
357 */
358#define RF_CSR_CFG 0x0500
359#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
360#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
361#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
362#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
363
364/*
365 * MAC Control/Status Registers(CSR).
366 * Some values are set in TU, whereas 1 TU == 1024 us.
367 */
368
369/*
370 * MAC_CSR0: ASIC revision number.
371 * ASIC_REV: 0
372 * ASIC_VER: 2860 or 2870
373 */
374#define MAC_CSR0 0x1000
375#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
376#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
377
378/*
379 * MAC_SYS_CTRL:
380 */
381#define MAC_SYS_CTRL 0x1004
382#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
383#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
384#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
385#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
386#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
387#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
388#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
389#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
390
391/*
392 * MAC_ADDR_DW0: STA MAC register 0
393 */
394#define MAC_ADDR_DW0 0x1008
395#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
396#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
397#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
398#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
399
400/*
401 * MAC_ADDR_DW1: STA MAC register 1
402 * UNICAST_TO_ME_MASK:
403 * Used to mask off bits from byte 5 of the MAC address
404 * to determine the UNICAST_TO_ME bit for RX frames.
405 * The full mask is complemented by BSS_ID_MASK:
406 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
407 */
408#define MAC_ADDR_DW1 0x100c
409#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
410#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
411#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
412
413/*
414 * MAC_BSSID_DW0: BSSID register 0
415 */
416#define MAC_BSSID_DW0 0x1010
417#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
418#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
419#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
420#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
421
422/*
423 * MAC_BSSID_DW1: BSSID register 1
424 * BSS_ID_MASK:
425 * 0: 1-BSSID mode (BSS index = 0)
426 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
427 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
428 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
429 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
430 * BSSID. This will make sure that those bits will be ignored
431 * when determining the MY_BSS of RX frames.
432 */
433#define MAC_BSSID_DW1 0x1014
434#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
435#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
436#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
437#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
438
439/*
440 * MAX_LEN_CFG: Maximum frame length register.
441 * MAX_MPDU: rt2860b max 16k bytes
442 * MAX_PSDU: Maximum PSDU length
443 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
444 */
445#define MAX_LEN_CFG 0x1018
446#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
447#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
448#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
449#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
450
451/*
452 * BBP_CSR_CFG: BBP serial control register
453 * VALUE: Register value to program into BBP
454 * REG_NUM: Selected BBP register
455 * READ_CONTROL: 0 write BBP, 1 read BBP
456 * BUSY: ASIC is busy executing BBP commands
457 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
458 * BBP_RW_MODE: 0 serial, 1 paralell
459 */
460#define BBP_CSR_CFG 0x101c
461#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
462#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
463#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
464#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
465#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
466#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
467
468/*
469 * RF_CSR_CFG0: RF control register
470 * REGID_AND_VALUE: Register value to program into RF
471 * BITWIDTH: Selected RF register
472 * STANDBYMODE: 0 high when standby, 1 low when standby
473 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
474 * BUSY: ASIC is busy executing RF commands
475 */
476#define RF_CSR_CFG0 0x1020
477#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
478#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
479#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
480#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
481#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
482#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
483
484/*
485 * RF_CSR_CFG1: RF control register
486 * REGID_AND_VALUE: Register value to program into RF
487 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
488 * 0: 3 system clock cycle (37.5usec)
489 * 1: 5 system clock cycle (62.5usec)
490 */
491#define RF_CSR_CFG1 0x1024
492#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
493#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
494
495/*
496 * RF_CSR_CFG2: RF control register
497 * VALUE: Register value to program into RF
498 */
499#define RF_CSR_CFG2 0x1028
500#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
501
502/*
503 * LED_CFG: LED control
504 * color LED's:
505 * 0: off
506 * 1: blinking upon TX2
507 * 2: periodic slow blinking
508 * 3: always on
509 * LED polarity:
510 * 0: active low
511 * 1: active high
512 */
513#define LED_CFG 0x102c
514#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
515#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
516#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
517#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
518#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
519#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
520#define LED_CFG_LED_POLAR FIELD32(0x40000000)
521
522/*
523 * XIFS_TIME_CFG: MAC timing
524 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
525 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
526 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
527 * when MAC doesn't reference BBP signal BBRXEND
528 * EIFS: unit 1us
529 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
530 *
531 */
532#define XIFS_TIME_CFG 0x1100
533#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
534#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
535#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
536#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
537#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
538
539/*
540 * BKOFF_SLOT_CFG:
541 */
542#define BKOFF_SLOT_CFG 0x1104
543#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
544#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
545
546/*
547 * NAV_TIME_CFG:
548 */
549#define NAV_TIME_CFG 0x1108
550#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
551#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
552#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
553#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
554
555/*
556 * CH_TIME_CFG: count as channel busy
557 */
558#define CH_TIME_CFG 0x110c
559
560/*
561 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
562 */
563#define PBF_LIFE_TIMER 0x1110
564
565/*
566 * BCN_TIME_CFG:
567 * BEACON_INTERVAL: in unit of 1/16 TU
568 * TSF_TICKING: Enable TSF auto counting
569 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
570 * BEACON_GEN: Enable beacon generator
571 */
572#define BCN_TIME_CFG 0x1114
573#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
574#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
575#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
576#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
577#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
578#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
579
580/*
581 * TBTT_SYNC_CFG:
582 */
583#define TBTT_SYNC_CFG 0x1118
584
585/*
586 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
587 */
588#define TSF_TIMER_DW0 0x111c
589#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
590
591/*
592 * TSF_TIMER_DW1: Local msb TSF timer, read-only
593 */
594#define TSF_TIMER_DW1 0x1120
595#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
596
597/*
598 * TBTT_TIMER: TImer remains till next TBTT, read-only
599 */
600#define TBTT_TIMER 0x1124
601
602/*
603 * INT_TIMER_CFG:
604 */
605#define INT_TIMER_CFG 0x1128
606
607/*
608 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
609 */
610#define INT_TIMER_EN 0x112c
611
612/*
613 * CH_IDLE_STA: channel idle time
614 */
615#define CH_IDLE_STA 0x1130
616
617/*
618 * CH_BUSY_STA: channel busy time
619 */
620#define CH_BUSY_STA 0x1134
621
622/*
623 * MAC_STATUS_CFG:
624 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
625 * if 1 or higher one of the 2 registers is busy.
626 */
627#define MAC_STATUS_CFG 0x1200
628#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
629
630/*
631 * PWR_PIN_CFG:
632 */
633#define PWR_PIN_CFG 0x1204
634
635/*
636 * AUTOWAKEUP_CFG: Manual power control / status register
637 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
638 * AUTOWAKE: 0:sleep, 1:awake
639 */
640#define AUTOWAKEUP_CFG 0x1208
641#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
642#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
643#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
644
645/*
646 * EDCA_AC0_CFG:
647 */
648#define EDCA_AC0_CFG 0x1300
649#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
650#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
651#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
652#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
653
654/*
655 * EDCA_AC1_CFG:
656 */
657#define EDCA_AC1_CFG 0x1304
658#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
659#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
660#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
661#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
662
663/*
664 * EDCA_AC2_CFG:
665 */
666#define EDCA_AC2_CFG 0x1308
667#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
668#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
669#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
670#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
671
672/*
673 * EDCA_AC3_CFG:
674 */
675#define EDCA_AC3_CFG 0x130c
676#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
677#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
678#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
679#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
680
681/*
682 * EDCA_TID_AC_MAP:
683 */
684#define EDCA_TID_AC_MAP 0x1310
685
686/*
687 * TX_PWR_CFG_0:
688 */
689#define TX_PWR_CFG_0 0x1314
690#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
691#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
692#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
693#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
694#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
695#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
696#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
697#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
698
699/*
700 * TX_PWR_CFG_1:
701 */
702#define TX_PWR_CFG_1 0x1318
703#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
704#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
705#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
706#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
707#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
708#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
709#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
710#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
711
712/*
713 * TX_PWR_CFG_2:
714 */
715#define TX_PWR_CFG_2 0x131c
716#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
717#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
718#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
719#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
720#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
721#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
722#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
723#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
724
725/*
726 * TX_PWR_CFG_3:
727 */
728#define TX_PWR_CFG_3 0x1320
729#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
730#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
731#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
732#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
733#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
734#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
735#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
736#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
737
738/*
739 * TX_PWR_CFG_4:
740 */
741#define TX_PWR_CFG_4 0x1324
742#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
743#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
744#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
745#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
746
747/*
748 * TX_PIN_CFG:
749 */
750#define TX_PIN_CFG 0x1328
751#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
752#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
753#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
754#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
755#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
756#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
757#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
758#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
759#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
760#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
761#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
762#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
763#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
764#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
765#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
766#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
767#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
768#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
769#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
770#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
771
772/*
773 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
774 */
775#define TX_BAND_CFG 0x132c
776#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
777#define TX_BAND_CFG_A FIELD32(0x00000002)
778#define TX_BAND_CFG_BG FIELD32(0x00000004)
779
780/*
781 * TX_SW_CFG0:
782 */
783#define TX_SW_CFG0 0x1330
784
785/*
786 * TX_SW_CFG1:
787 */
788#define TX_SW_CFG1 0x1334
789
790/*
791 * TX_SW_CFG2:
792 */
793#define TX_SW_CFG2 0x1338
794
795/*
796 * TXOP_THRES_CFG:
797 */
798#define TXOP_THRES_CFG 0x133c
799
800/*
801 * TXOP_CTRL_CFG:
802 */
803#define TXOP_CTRL_CFG 0x1340
804
805/*
806 * TX_RTS_CFG:
807 * RTS_THRES: unit:byte
808 * RTS_FBK_EN: enable rts rate fallback
809 */
810#define TX_RTS_CFG 0x1344
811#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
812#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
813#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
814
815/*
816 * TX_TIMEOUT_CFG:
817 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
818 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
819 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
820 * it is recommended that:
821 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
822 */
823#define TX_TIMEOUT_CFG 0x1348
824#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
825#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
826#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
827
828/*
829 * TX_RTY_CFG:
830 * SHORT_RTY_LIMIT: short retry limit
831 * LONG_RTY_LIMIT: long retry limit
832 * LONG_RTY_THRE: Long retry threshoold
833 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
834 * 0:expired by retry limit, 1: expired by mpdu life timer
835 * AGG_RTY_MODE: Aggregate MPDU retry mode
836 * 0:expired by retry limit, 1: expired by mpdu life timer
837 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
838 */
839#define TX_RTY_CFG 0x134c
840#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
841#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
842#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
843#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
844#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
845#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
846
847/*
848 * TX_LINK_CFG:
849 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
850 * MFB_ENABLE: TX apply remote MFB 1:enable
851 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
852 * 0: not apply remote remote unsolicit (MFS=7)
853 * TX_MRQ_EN: MCS request TX enable
854 * TX_RDG_EN: RDG TX enable
855 * TX_CF_ACK_EN: Piggyback CF-ACK enable
856 * REMOTE_MFB: remote MCS feedback
857 * REMOTE_MFS: remote MCS feedback sequence number
858 */
859#define TX_LINK_CFG 0x1350
860#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
861#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
862#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
863#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
864#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
865#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
866#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
867#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
868
869/*
870 * HT_FBK_CFG0:
871 */
872#define HT_FBK_CFG0 0x1354
873#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
874#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
875#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
876#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
877#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
878#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
879#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
880#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
881
882/*
883 * HT_FBK_CFG1:
884 */
885#define HT_FBK_CFG1 0x1358
886#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
887#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
888#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
889#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
890#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
891#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
892#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
893#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
894
895/*
896 * LG_FBK_CFG0:
897 */
898#define LG_FBK_CFG0 0x135c
899#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
900#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
901#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
902#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
903#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
904#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
905#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
906#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
907
908/*
909 * LG_FBK_CFG1:
910 */
911#define LG_FBK_CFG1 0x1360
912#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
913#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
914#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
915#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
916
917/*
918 * CCK_PROT_CFG: CCK Protection
919 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
920 * PROTECT_CTRL: Protection control frame type for CCK TX
921 * 0:none, 1:RTS/CTS, 2:CTS-to-self
922 * PROTECT_NAV: TXOP protection type for CCK TX
923 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
924 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
925 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
926 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
927 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
928 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
929 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
930 * RTS_TH_EN: RTS threshold enable on CCK TX
931 */
932#define CCK_PROT_CFG 0x1364
933#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
934#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
935#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
936#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
937#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
938#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
939#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
940#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
941#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
942#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
943
944/*
945 * OFDM_PROT_CFG: OFDM Protection
946 */
947#define OFDM_PROT_CFG 0x1368
948#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
949#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
950#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
951#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
952#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
953#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
954#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
955#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
956#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
957#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
958
959/*
960 * MM20_PROT_CFG: MM20 Protection
961 */
962#define MM20_PROT_CFG 0x136c
963#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
964#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
965#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
966#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
967#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
968#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
969#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
970#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
971#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
972#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
973
974/*
975 * MM40_PROT_CFG: MM40 Protection
976 */
977#define MM40_PROT_CFG 0x1370
978#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
979#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
980#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
981#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
982#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
983#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
984#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
985#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
986#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
987#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
988
989/*
990 * GF20_PROT_CFG: GF20 Protection
991 */
992#define GF20_PROT_CFG 0x1374
993#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
994#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
995#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
996#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
997#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
998#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
999#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1000#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1001#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1002#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1003
1004/*
1005 * GF40_PROT_CFG: GF40 Protection
1006 */
1007#define GF40_PROT_CFG 0x1378
1008#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1009#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1010#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1011#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1012#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1013#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1014#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1015#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1016#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1017#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1018
1019/*
1020 * EXP_CTS_TIME:
1021 */
1022#define EXP_CTS_TIME 0x137c
1023
1024/*
1025 * EXP_ACK_TIME:
1026 */
1027#define EXP_ACK_TIME 0x1380
1028
1029/*
1030 * RX_FILTER_CFG: RX configuration register.
1031 */
1032#define RX_FILTER_CFG 0x1400
1033#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1034#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1035#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1036#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1037#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1038#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1039#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1040#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1041#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1042#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1043#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1044#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1045#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1046#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1047#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1048#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1049#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1050
1051/*
1052 * AUTO_RSP_CFG:
1053 * AUTORESPONDER: 0: disable, 1: enable
1054 * BAC_ACK_POLICY: 0:long, 1:short preamble
1055 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1056 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1057 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1058 * DUAL_CTS_EN: Power bit value in control frame
1059 * ACK_CTS_PSM_BIT:Power bit value in control frame
1060 */
1061#define AUTO_RSP_CFG 0x1404
1062#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1063#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1064#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1065#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1066#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1067#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1068#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1069
1070/*
1071 * LEGACY_BASIC_RATE:
1072 */
1073#define LEGACY_BASIC_RATE 0x1408
1074
1075/*
1076 * HT_BASIC_RATE:
1077 */
1078#define HT_BASIC_RATE 0x140c
1079
1080/*
1081 * HT_CTRL_CFG:
1082 */
1083#define HT_CTRL_CFG 0x1410
1084
1085/*
1086 * SIFS_COST_CFG:
1087 */
1088#define SIFS_COST_CFG 0x1414
1089
1090/*
1091 * RX_PARSER_CFG:
1092 * Set NAV for all received frames
1093 */
1094#define RX_PARSER_CFG 0x1418
1095
1096/*
1097 * TX_SEC_CNT0:
1098 */
1099#define TX_SEC_CNT0 0x1500
1100
1101/*
1102 * RX_SEC_CNT0:
1103 */
1104#define RX_SEC_CNT0 0x1504
1105
1106/*
1107 * CCMP_FC_MUTE:
1108 */
1109#define CCMP_FC_MUTE 0x1508
1110
1111/*
1112 * TXOP_HLDR_ADDR0:
1113 */
1114#define TXOP_HLDR_ADDR0 0x1600
1115
1116/*
1117 * TXOP_HLDR_ADDR1:
1118 */
1119#define TXOP_HLDR_ADDR1 0x1604
1120
1121/*
1122 * TXOP_HLDR_ET:
1123 */
1124#define TXOP_HLDR_ET 0x1608
1125
1126/*
1127 * QOS_CFPOLL_RA_DW0:
1128 */
1129#define QOS_CFPOLL_RA_DW0 0x160c
1130
1131/*
1132 * QOS_CFPOLL_RA_DW1:
1133 */
1134#define QOS_CFPOLL_RA_DW1 0x1610
1135
1136/*
1137 * QOS_CFPOLL_QC:
1138 */
1139#define QOS_CFPOLL_QC 0x1614
1140
1141/*
1142 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1143 */
1144#define RX_STA_CNT0 0x1700
1145#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1146#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1147
1148/*
1149 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1150 */
1151#define RX_STA_CNT1 0x1704
1152#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1153#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1154
1155/*
1156 * RX_STA_CNT2:
1157 */
1158#define RX_STA_CNT2 0x1708
1159#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1160#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1161
1162/*
1163 * TX_STA_CNT0: TX Beacon count
1164 */
1165#define TX_STA_CNT0 0x170c
1166#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1167#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1168
1169/*
1170 * TX_STA_CNT1: TX tx count
1171 */
1172#define TX_STA_CNT1 0x1710
1173#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1174#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1175
1176/*
1177 * TX_STA_CNT2: TX tx count
1178 */
1179#define TX_STA_CNT2 0x1714
1180#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1181#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1182
1183/*
1184 * TX_STA_FIFO: TX Result for specific PID status fifo register
1185 */
1186#define TX_STA_FIFO 0x1718
1187#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1188#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1189#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1190#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1191#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1192#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1193#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1194#define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1195#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1196
1197/*
1198 * TX_AGG_CNT: Debug counter
1199 */
1200#define TX_AGG_CNT 0x171c
1201#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1202#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1203
1204/*
1205 * TX_AGG_CNT0:
1206 */
1207#define TX_AGG_CNT0 0x1720
1208#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1209#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1210
1211/*
1212 * TX_AGG_CNT1:
1213 */
1214#define TX_AGG_CNT1 0x1724
1215#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1216#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1217
1218/*
1219 * TX_AGG_CNT2:
1220 */
1221#define TX_AGG_CNT2 0x1728
1222#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1223#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1224
1225/*
1226 * TX_AGG_CNT3:
1227 */
1228#define TX_AGG_CNT3 0x172c
1229#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1230#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1231
1232/*
1233 * TX_AGG_CNT4:
1234 */
1235#define TX_AGG_CNT4 0x1730
1236#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1237#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1238
1239/*
1240 * TX_AGG_CNT5:
1241 */
1242#define TX_AGG_CNT5 0x1734
1243#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1244#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1245
1246/*
1247 * TX_AGG_CNT6:
1248 */
1249#define TX_AGG_CNT6 0x1738
1250#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1251#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1252
1253/*
1254 * TX_AGG_CNT7:
1255 */
1256#define TX_AGG_CNT7 0x173c
1257#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1258#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1259
1260/*
1261 * MPDU_DENSITY_CNT:
1262 * TX_ZERO_DEL: TX zero length delimiter count
1263 * RX_ZERO_DEL: RX zero length delimiter count
1264 */
1265#define MPDU_DENSITY_CNT 0x1740
1266#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1267#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1268
1269/*
1270 * Security key table memory.
1271 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1272 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1273 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1274 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1275 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1276 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1277 */
1278#define MAC_WCID_BASE 0x1800
1279#define PAIRWISE_KEY_TABLE_BASE 0x4000
1280#define MAC_IVEIV_TABLE_BASE 0x6000
1281#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1282#define SHARED_KEY_TABLE_BASE 0x6c00
1283#define SHARED_KEY_MODE_BASE 0x7000
1284
1285#define MAC_WCID_ENTRY(__idx) \
1286 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1287#define PAIRWISE_KEY_ENTRY(__idx) \
1288 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1289#define MAC_IVEIV_ENTRY(__idx) \
1290 ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
1291#define MAC_WCID_ATTR_ENTRY(__idx) \
1292 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1293#define SHARED_KEY_ENTRY(__idx) \
1294 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1295#define SHARED_KEY_MODE_ENTRY(__idx) \
1296 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1297
1298struct mac_wcid_entry {
1299 u8 mac[6];
1300 u8 reserved[2];
1301} __attribute__ ((packed));
1302
1303struct hw_key_entry {
1304 u8 key[16];
1305 u8 tx_mic[8];
1306 u8 rx_mic[8];
1307} __attribute__ ((packed));
1308
1309struct mac_iveiv_entry {
1310 u8 iv[8];
1311} __attribute__ ((packed));
1312
1313/*
1314 * MAC_WCID_ATTRIBUTE:
1315 */
1316#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1317#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1318#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1319#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1320
1321/*
1322 * SHARED_KEY_MODE:
1323 */
1324#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1325#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1326#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1327#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1328#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1329#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1330#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1331#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1332
1333/*
1334 * HOST-MCU communication
1335 */
1336
1337/*
1338 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1339 */
1340#define H2M_MAILBOX_CSR 0x7010
1341#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1342#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1343#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1344#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1345
1346/*
1347 * H2M_MAILBOX_CID:
1348 */
1349#define H2M_MAILBOX_CID 0x7014
1350#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1351#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1352#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1353#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1354
1355/*
1356 * H2M_MAILBOX_STATUS:
1357 */
1358#define H2M_MAILBOX_STATUS 0x701c
1359
1360/*
1361 * H2M_INT_SRC:
1362 */
1363#define H2M_INT_SRC 0x7024
1364
1365/*
1366 * H2M_BBP_AGENT:
1367 */
1368#define H2M_BBP_AGENT 0x7028
1369
1370/*
1371 * MCU_LEDCS: LED control for MCU Mailbox.
1372 */
1373#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1374#define MCU_LEDCS_POLARITY FIELD8(0x01)
1375
1376/*
1377 * HW_CS_CTS_BASE:
1378 * Carrier-sense CTS frame base address.
1379 * It's where mac stores carrier-sense frame for carrier-sense function.
1380 */
1381#define HW_CS_CTS_BASE 0x7700
1382
1383/*
1384 * HW_DFS_CTS_BASE:
1385 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1386 */
1387#define HW_DFS_CTS_BASE 0x7780
1388
1389/*
1390 * TXRX control registers - base address 0x3000
1391 */
1392
1393/*
1394 * TXRX_CSR1:
1395 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1396 */
1397#define TXRX_CSR1 0x77d0
1398
1399/*
1400 * HW_DEBUG_SETTING_BASE:
1401 * since NULL frame won't be that long (256 byte)
1402 * We steal 16 tail bytes to save debugging settings
1403 */
1404#define HW_DEBUG_SETTING_BASE 0x77f0
1405#define HW_DEBUG_SETTING_BASE2 0x7770
1406
1407/*
1408 * HW_BEACON_BASE
1409 * In order to support maximum 8 MBSS and its maximum length
1410 * is 512 bytes for each beacon
1411 * Three section discontinue memory segments will be used.
1412 * 1. The original region for BCN 0~3
1413 * 2. Extract memory from FCE table for BCN 4~5
1414 * 3. Extract memory from Pair-wise key table for BCN 6~7
1415 * It occupied those memory of wcid 238~253 for BCN 6
1416 * and wcid 222~237 for BCN 7
1417 *
1418 * IMPORTANT NOTE: Not sure why legacy driver does this,
1419 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1420 */
1421#define HW_BEACON_BASE0 0x7800
1422#define HW_BEACON_BASE1 0x7a00
1423#define HW_BEACON_BASE2 0x7c00
1424#define HW_BEACON_BASE3 0x7e00
1425#define HW_BEACON_BASE4 0x7200
1426#define HW_BEACON_BASE5 0x7400
1427#define HW_BEACON_BASE6 0x5dc0
1428#define HW_BEACON_BASE7 0x5bc0
1429
1430#define HW_BEACON_OFFSET(__index) \
1431 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1432 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1433 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1434
1435/*
1436 * BBP registers.
1437 * The wordsize of the BBP is 8 bits.
1438 */
1439
1440/*
1441 * BBP 1: TX Antenna
1442 */
1443#define BBP1_TX_POWER FIELD8(0x07)
1444#define BBP1_TX_ANTENNA FIELD8(0x18)
1445
1446/*
1447 * BBP 3: RX Antenna
1448 */
1449#define BBP3_RX_ANTENNA FIELD8(0x18)
1450#define BBP3_HT40_PLUS FIELD8(0x20)
1451
1452/*
1453 * BBP 4: Bandwidth
1454 */
1455#define BBP4_TX_BF FIELD8(0x01)
1456#define BBP4_BANDWIDTH FIELD8(0x18)
1457
1458/*
1459 * RFCSR registers
1460 * The wordsize of the RFCSR is 8 bits.
1461 */
1462
1463/*
1464 * RFCSR 6:
1465 */
1466#define RFCSR6_R FIELD8(0x03)
1467
1468/*
1469 * RFCSR 7:
1470 */
1471#define RFCSR7_RF_TUNING FIELD8(0x01)
1472
1473/*
1474 * RFCSR 12:
1475 */
1476#define RFCSR12_TX_POWER FIELD8(0x1f)
1477
1478/*
1479 * RFCSR 22:
1480 */
1481#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1482
1483/*
1484 * RFCSR 23:
1485 */
1486#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1487
1488/*
1489 * RFCSR 30:
1490 */
1491#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1492
1493/*
1494 * RF registers
1495 */
1496
1497/*
1498 * RF 2
1499 */
1500#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1501#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1502#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1503
1504/*
1505 * RF 3
1506 */
1507#define RF3_TXPOWER_G FIELD32(0x00003e00)
1508#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1509#define RF3_TXPOWER_A FIELD32(0x00003c00)
1510
1511/*
1512 * RF 4
1513 */
1514#define RF4_TXPOWER_G FIELD32(0x000007c0)
1515#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1516#define RF4_TXPOWER_A FIELD32(0x00000780)
1517#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1518#define RF4_HT40 FIELD32(0x00200000)
1519
1520/*
1521 * EEPROM content.
1522 * The wordsize of the EEPROM is 16 bits.
1523 */
1524
1525/*
1526 * EEPROM Version
1527 */
1528#define EEPROM_VERSION 0x0001
1529#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1530#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1531
1532/*
1533 * HW MAC address.
1534 */
1535#define EEPROM_MAC_ADDR_0 0x0002
1536#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1537#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1538#define EEPROM_MAC_ADDR_1 0x0003
1539#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1540#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1541#define EEPROM_MAC_ADDR_2 0x0004
1542#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1543#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1544
1545/*
1546 * EEPROM ANTENNA config
1547 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1548 * TXPATH: 1: 1T, 2: 2T
1549 */
1550#define EEPROM_ANTENNA 0x001a
1551#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1552#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1553#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1554
1555/*
1556 * EEPROM NIC config
1557 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1558 */
1559#define EEPROM_NIC 0x001b
1560#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1561#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1562#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1563#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1564#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1565#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1566#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1567#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1568#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1569#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1570
1571/*
1572 * EEPROM frequency
1573 */
1574#define EEPROM_FREQ 0x001d
1575#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1576#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1577#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1578
1579/*
1580 * EEPROM LED
1581 * POLARITY_RDY_G: Polarity RDY_G setting.
1582 * POLARITY_RDY_A: Polarity RDY_A setting.
1583 * POLARITY_ACT: Polarity ACT setting.
1584 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1585 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1586 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1587 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1588 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1589 * LED_MODE: Led mode.
1590 */
1591#define EEPROM_LED1 0x001e
1592#define EEPROM_LED2 0x001f
1593#define EEPROM_LED3 0x0020
1594#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1595#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1596#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1597#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1598#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1599#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1600#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1601#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1602#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1603
1604/*
1605 * EEPROM LNA
1606 */
1607#define EEPROM_LNA 0x0022
1608#define EEPROM_LNA_BG FIELD16(0x00ff)
1609#define EEPROM_LNA_A0 FIELD16(0xff00)
1610
1611/*
1612 * EEPROM RSSI BG offset
1613 */
1614#define EEPROM_RSSI_BG 0x0023
1615#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1616#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1617
1618/*
1619 * EEPROM RSSI BG2 offset
1620 */
1621#define EEPROM_RSSI_BG2 0x0024
1622#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1623#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1624
1625/*
1626 * EEPROM RSSI A offset
1627 */
1628#define EEPROM_RSSI_A 0x0025
1629#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1630#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1631
1632/*
1633 * EEPROM RSSI A2 offset
1634 */
1635#define EEPROM_RSSI_A2 0x0026
1636#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1637#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1638
1639/*
1640 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1641 * This is delta in 40MHZ.
1642 * VALUE: Tx Power dalta value (MAX=4)
1643 * TYPE: 1: Plus the delta value, 0: minus the delta value
1644 * TXPOWER: Enable:
1645 */
1646#define EEPROM_TXPOWER_DELTA 0x0028
1647#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1648#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1649#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1650
1651/*
1652 * EEPROM TXPOWER 802.11BG
1653 */
1654#define EEPROM_TXPOWER_BG1 0x0029
1655#define EEPROM_TXPOWER_BG2 0x0030
1656#define EEPROM_TXPOWER_BG_SIZE 7
1657#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1658#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1659
1660/*
1661 * EEPROM TXPOWER 802.11A
1662 */
1663#define EEPROM_TXPOWER_A1 0x003c
1664#define EEPROM_TXPOWER_A2 0x0053
1665#define EEPROM_TXPOWER_A_SIZE 6
1666#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1667#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1668
1669/*
1670 * EEPROM TXpower byrate: 20MHZ power
1671 */
1672#define EEPROM_TXPOWER_BYRATE 0x006f
1673
1674/*
1675 * EEPROM BBP.
1676 */
1677#define EEPROM_BBP_START 0x0078
1678#define EEPROM_BBP_SIZE 16
1679#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1680#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1681
1682/*
1683 * MCU mailbox commands.
1684 */
1685#define MCU_SLEEP 0x30
1686#define MCU_WAKEUP 0x31
1687#define MCU_RADIO_OFF 0x35
1688#define MCU_CURRENT 0x36
1689#define MCU_LED 0x50
1690#define MCU_LED_STRENGTH 0x51
1691#define MCU_LED_1 0x52
1692#define MCU_LED_2 0x53
1693#define MCU_LED_3 0x54
1694#define MCU_RADAR 0x60
1695#define MCU_BOOT_SIGNAL 0x72
1696#define MCU_BBP_SIGNAL 0x80
1697#define MCU_POWER_SAVE 0x83
1698
1699/*
1700 * MCU mailbox tokens
1701 */
1702#define TOKEN_WAKUP 3
1703
1704/*
1705 * DMA descriptor defines.
1706 */
1707#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1708#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1709
1710/*
1711 * TX WI structure
1712 */
1713
1714/*
1715 * Word0
1716 * FRAG: 1 To inform TKIP engine this is a fragment.
1717 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1718 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1719 * BW: Channel bandwidth 20MHz or 40 MHz
1720 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1721 */
1722#define TXWI_W0_FRAG FIELD32(0x00000001)
1723#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1724#define TXWI_W0_CF_ACK FIELD32(0x00000004)
1725#define TXWI_W0_TS FIELD32(0x00000008)
1726#define TXWI_W0_AMPDU FIELD32(0x00000010)
1727#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1728#define TXWI_W0_TX_OP FIELD32(0x00000300)
1729#define TXWI_W0_MCS FIELD32(0x007f0000)
1730#define TXWI_W0_BW FIELD32(0x00800000)
1731#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1732#define TXWI_W0_STBC FIELD32(0x06000000)
1733#define TXWI_W0_IFS FIELD32(0x08000000)
1734#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1735
1736/*
1737 * Word1
1738 */
1739#define TXWI_W1_ACK FIELD32(0x00000001)
1740#define TXWI_W1_NSEQ FIELD32(0x00000002)
1741#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1742#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1743#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1744#define TXWI_W1_PACKETID FIELD32(0xf0000000)
1745
1746/*
1747 * Word2
1748 */
1749#define TXWI_W2_IV FIELD32(0xffffffff)
1750
1751/*
1752 * Word3
1753 */
1754#define TXWI_W3_EIV FIELD32(0xffffffff)
1755
1756/*
1757 * RX WI structure
1758 */
1759
1760/*
1761 * Word0
1762 */
1763#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1764#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1765#define RXWI_W0_BSSID FIELD32(0x00001c00)
1766#define RXWI_W0_UDF FIELD32(0x0000e000)
1767#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1768#define RXWI_W0_TID FIELD32(0xf0000000)
1769
1770/*
1771 * Word1
1772 */
1773#define RXWI_W1_FRAG FIELD32(0x0000000f)
1774#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1775#define RXWI_W1_MCS FIELD32(0x007f0000)
1776#define RXWI_W1_BW FIELD32(0x00800000)
1777#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1778#define RXWI_W1_STBC FIELD32(0x06000000)
1779#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1780
1781/*
1782 * Word2
1783 */
1784#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1785#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1786#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1787
1788/*
1789 * Word3
1790 */
1791#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1792#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1793
1794/*
1795 * Macros for converting txpower from EEPROM to mac80211 value
1796 * and from mac80211 value to register value.
1797 */
1798#define MIN_G_TXPOWER 0
1799#define MIN_A_TXPOWER -7
1800#define MAX_G_TXPOWER 31
1801#define MAX_A_TXPOWER 15
1802#define DEFAULT_TXPOWER 5
1803
1804#define TXPOWER_G_FROM_DEV(__txpower) \
1805 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1806
1807#define TXPOWER_G_TO_DEV(__txpower) \
1808 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1809
1810#define TXPOWER_A_FROM_DEV(__txpower) \
1811 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1812
1813#define TXPOWER_A_TO_DEV(__txpower) \
1814 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1815
1816#endif /* RT2800_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
new file mode 100644
index 000000000000..5c7d74a6f16e
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -0,0 +1,1817 @@
1/*
2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz
3
4 Based on the original rt2800pci.c and rt2800usb.c:
5
6 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
7 <http://rt2x00.serialmonkey.com>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the
21 Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 */
24
25/*
26 Module: rt2800lib
27 Abstract: rt2800 generic device routines.
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32
33#include "rt2x00.h"
34#ifdef CONFIG_RT2800USB
35#include "rt2x00usb.h"
36#endif
37#include "rt2800lib.h"
38#include "rt2800.h"
39#include "rt2800usb.h"
40
41MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
42MODULE_DESCRIPTION("rt2800 library");
43MODULE_LICENSE("GPL");
44
45/*
46 * Register access.
47 * All access to the CSR registers will go through the methods
48 * rt2800_register_read and rt2800_register_write.
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers BBPCSR and RFCSR to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
57 * The _lock versions must be used if you already hold the csr_mutex
58 */
59#define WAIT_FOR_BBP(__dev, __reg) \
60 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
61#define WAIT_FOR_RFCSR(__dev, __reg) \
62 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
63#define WAIT_FOR_RF(__dev, __reg) \
64 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
65#define WAIT_FOR_MCU(__dev, __reg) \
66 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
67 H2M_MAILBOX_CSR_OWNER, (__reg))
68
69static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
70 const unsigned int word, const u8 value)
71{
72 u32 reg;
73
74 mutex_lock(&rt2x00dev->csr_mutex);
75
76 /*
77 * Wait until the BBP becomes available, afterwards we
78 * can safely write the new data into the register.
79 */
80 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
81 reg = 0;
82 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
83 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
84 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
85 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
86 if (rt2x00_intf_is_pci(rt2x00dev))
87 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
88
89 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
90 }
91
92 mutex_unlock(&rt2x00dev->csr_mutex);
93}
94
95static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
96 const unsigned int word, u8 *value)
97{
98 u32 reg;
99
100 mutex_lock(&rt2x00dev->csr_mutex);
101
102 /*
103 * Wait until the BBP becomes available, afterwards we
104 * can safely write the read request into the register.
105 * After the data has been written, we wait until hardware
106 * returns the correct value, if at any time the register
107 * doesn't become available in time, reg will be 0xffffffff
108 * which means we return 0xff to the caller.
109 */
110 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
111 reg = 0;
112 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
113 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
114 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
115 if (rt2x00_intf_is_pci(rt2x00dev))
116 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
117
118 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
119
120 WAIT_FOR_BBP(rt2x00dev, &reg);
121 }
122
123 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
124
125 mutex_unlock(&rt2x00dev->csr_mutex);
126}
127
128static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
129 const unsigned int word, const u8 value)
130{
131 u32 reg;
132
133 mutex_lock(&rt2x00dev->csr_mutex);
134
135 /*
136 * Wait until the RFCSR becomes available, afterwards we
137 * can safely write the new data into the register.
138 */
139 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
140 reg = 0;
141 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
142 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
143 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
144 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
145
146 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
147 }
148
149 mutex_unlock(&rt2x00dev->csr_mutex);
150}
151
152static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
153 const unsigned int word, u8 *value)
154{
155 u32 reg;
156
157 mutex_lock(&rt2x00dev->csr_mutex);
158
159 /*
160 * Wait until the RFCSR becomes available, afterwards we
161 * can safely write the read request into the register.
162 * After the data has been written, we wait until hardware
163 * returns the correct value, if at any time the register
164 * doesn't become available in time, reg will be 0xffffffff
165 * which means we return 0xff to the caller.
166 */
167 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
168 reg = 0;
169 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
170 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
171 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
172
173 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
174
175 WAIT_FOR_RFCSR(rt2x00dev, &reg);
176 }
177
178 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
179
180 mutex_unlock(&rt2x00dev->csr_mutex);
181}
182
183static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
184 const unsigned int word, const u32 value)
185{
186 u32 reg;
187
188 mutex_lock(&rt2x00dev->csr_mutex);
189
190 /*
191 * Wait until the RF becomes available, afterwards we
192 * can safely write the new data into the register.
193 */
194 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
195 reg = 0;
196 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
197 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
198 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
199 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
200
201 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
202 rt2x00_rf_write(rt2x00dev, word, value);
203 }
204
205 mutex_unlock(&rt2x00dev->csr_mutex);
206}
207
208void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
209 const u8 command, const u8 token,
210 const u8 arg0, const u8 arg1)
211{
212 u32 reg;
213
214 if (rt2x00_intf_is_pci(rt2x00dev)) {
215 /*
216 * RT2880 and RT3052 don't support MCU requests.
217 */
218 if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
219 rt2x00_rt(&rt2x00dev->chip, RT3052))
220 return;
221 }
222
223 mutex_lock(&rt2x00dev->csr_mutex);
224
225 /*
226 * Wait until the MCU becomes available, afterwards we
227 * can safely write the new data into the register.
228 */
229 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
230 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
231 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
232 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
233 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
234 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
235
236 reg = 0;
237 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
238 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
239 }
240
241 mutex_unlock(&rt2x00dev->csr_mutex);
242}
243EXPORT_SYMBOL_GPL(rt2800_mcu_request);
244
245#ifdef CONFIG_RT2X00_LIB_DEBUGFS
246const struct rt2x00debug rt2800_rt2x00debug = {
247 .owner = THIS_MODULE,
248 .csr = {
249 .read = rt2800_register_read,
250 .write = rt2800_register_write,
251 .flags = RT2X00DEBUGFS_OFFSET,
252 .word_base = CSR_REG_BASE,
253 .word_size = sizeof(u32),
254 .word_count = CSR_REG_SIZE / sizeof(u32),
255 },
256 .eeprom = {
257 .read = rt2x00_eeprom_read,
258 .write = rt2x00_eeprom_write,
259 .word_base = EEPROM_BASE,
260 .word_size = sizeof(u16),
261 .word_count = EEPROM_SIZE / sizeof(u16),
262 },
263 .bbp = {
264 .read = rt2800_bbp_read,
265 .write = rt2800_bbp_write,
266 .word_base = BBP_BASE,
267 .word_size = sizeof(u8),
268 .word_count = BBP_SIZE / sizeof(u8),
269 },
270 .rf = {
271 .read = rt2x00_rf_read,
272 .write = rt2800_rf_write,
273 .word_base = RF_BASE,
274 .word_size = sizeof(u32),
275 .word_count = RF_SIZE / sizeof(u32),
276 },
277};
278EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
279#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
280
281int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
282{
283 u32 reg;
284
285 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
286 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
287}
288EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
289
290#ifdef CONFIG_RT2X00_LIB_LEDS
291static void rt2800_brightness_set(struct led_classdev *led_cdev,
292 enum led_brightness brightness)
293{
294 struct rt2x00_led *led =
295 container_of(led_cdev, struct rt2x00_led, led_dev);
296 unsigned int enabled = brightness != LED_OFF;
297 unsigned int bg_mode =
298 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
299 unsigned int polarity =
300 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
301 EEPROM_FREQ_LED_POLARITY);
302 unsigned int ledmode =
303 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
304 EEPROM_FREQ_LED_MODE);
305
306 if (led->type == LED_TYPE_RADIO) {
307 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
308 enabled ? 0x20 : 0);
309 } else if (led->type == LED_TYPE_ASSOC) {
310 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
311 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
312 } else if (led->type == LED_TYPE_QUALITY) {
313 /*
314 * The brightness is divided into 6 levels (0 - 5),
315 * The specs tell us the following levels:
316 * 0, 1 ,3, 7, 15, 31
317 * to determine the level in a simple way we can simply
318 * work with bitshifting:
319 * (1 << level) - 1
320 */
321 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
322 (1 << brightness / (LED_FULL / 6)) - 1,
323 polarity);
324 }
325}
326
327static int rt2800_blink_set(struct led_classdev *led_cdev,
328 unsigned long *delay_on, unsigned long *delay_off)
329{
330 struct rt2x00_led *led =
331 container_of(led_cdev, struct rt2x00_led, led_dev);
332 u32 reg;
333
334 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
335 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
336 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
337 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
338 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
339 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
340 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
341 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
342 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
343
344 return 0;
345}
346
347void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
348 struct rt2x00_led *led, enum led_type type)
349{
350 led->rt2x00dev = rt2x00dev;
351 led->type = type;
352 led->led_dev.brightness_set = rt2800_brightness_set;
353 led->led_dev.blink_set = rt2800_blink_set;
354 led->flags = LED_INITIALIZED;
355}
356EXPORT_SYMBOL_GPL(rt2800_init_led);
357#endif /* CONFIG_RT2X00_LIB_LEDS */
358
359/*
360 * Configuration handlers.
361 */
362static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
363 struct rt2x00lib_crypto *crypto,
364 struct ieee80211_key_conf *key)
365{
366 struct mac_wcid_entry wcid_entry;
367 struct mac_iveiv_entry iveiv_entry;
368 u32 offset;
369 u32 reg;
370
371 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
372
373 rt2800_register_read(rt2x00dev, offset, &reg);
374 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
375 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
376 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
377 (crypto->cmd == SET_KEY) * crypto->cipher);
378 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
379 (crypto->cmd == SET_KEY) * crypto->bssidx);
380 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
381 rt2800_register_write(rt2x00dev, offset, reg);
382
383 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
384
385 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
386 if ((crypto->cipher == CIPHER_TKIP) ||
387 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
388 (crypto->cipher == CIPHER_AES))
389 iveiv_entry.iv[3] |= 0x20;
390 iveiv_entry.iv[3] |= key->keyidx << 6;
391 rt2800_register_multiwrite(rt2x00dev, offset,
392 &iveiv_entry, sizeof(iveiv_entry));
393
394 offset = MAC_WCID_ENTRY(key->hw_key_idx);
395
396 memset(&wcid_entry, 0, sizeof(wcid_entry));
397 if (crypto->cmd == SET_KEY)
398 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
399 rt2800_register_multiwrite(rt2x00dev, offset,
400 &wcid_entry, sizeof(wcid_entry));
401}
402
403int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
404 struct rt2x00lib_crypto *crypto,
405 struct ieee80211_key_conf *key)
406{
407 struct hw_key_entry key_entry;
408 struct rt2x00_field32 field;
409 u32 offset;
410 u32 reg;
411
412 if (crypto->cmd == SET_KEY) {
413 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
414
415 memcpy(key_entry.key, crypto->key,
416 sizeof(key_entry.key));
417 memcpy(key_entry.tx_mic, crypto->tx_mic,
418 sizeof(key_entry.tx_mic));
419 memcpy(key_entry.rx_mic, crypto->rx_mic,
420 sizeof(key_entry.rx_mic));
421
422 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
423 rt2800_register_multiwrite(rt2x00dev, offset,
424 &key_entry, sizeof(key_entry));
425 }
426
427 /*
428 * The cipher types are stored over multiple registers
429 * starting with SHARED_KEY_MODE_BASE each word will have
430 * 32 bits and contains the cipher types for 2 bssidx each.
431 * Using the correct defines correctly will cause overhead,
432 * so just calculate the correct offset.
433 */
434 field.bit_offset = 4 * (key->hw_key_idx % 8);
435 field.bit_mask = 0x7 << field.bit_offset;
436
437 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
438
439 rt2800_register_read(rt2x00dev, offset, &reg);
440 rt2x00_set_field32(&reg, field,
441 (crypto->cmd == SET_KEY) * crypto->cipher);
442 rt2800_register_write(rt2x00dev, offset, reg);
443
444 /*
445 * Update WCID information
446 */
447 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
448
449 return 0;
450}
451EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
452
453int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
454 struct rt2x00lib_crypto *crypto,
455 struct ieee80211_key_conf *key)
456{
457 struct hw_key_entry key_entry;
458 u32 offset;
459
460 if (crypto->cmd == SET_KEY) {
461 /*
462 * 1 pairwise key is possible per AID, this means that the AID
463 * equals our hw_key_idx. Make sure the WCID starts _after_ the
464 * last possible shared key entry.
465 */
466 if (crypto->aid > (256 - 32))
467 return -ENOSPC;
468
469 key->hw_key_idx = 32 + crypto->aid;
470
471 memcpy(key_entry.key, crypto->key,
472 sizeof(key_entry.key));
473 memcpy(key_entry.tx_mic, crypto->tx_mic,
474 sizeof(key_entry.tx_mic));
475 memcpy(key_entry.rx_mic, crypto->rx_mic,
476 sizeof(key_entry.rx_mic));
477
478 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
479 rt2800_register_multiwrite(rt2x00dev, offset,
480 &key_entry, sizeof(key_entry));
481 }
482
483 /*
484 * Update WCID information
485 */
486 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
487
488 return 0;
489}
490EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
491
492void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
493 const unsigned int filter_flags)
494{
495 u32 reg;
496
497 /*
498 * Start configuration steps.
499 * Note that the version error will always be dropped
500 * and broadcast frames will always be accepted since
501 * there is no filter for it at this time.
502 */
503 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
504 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
505 !(filter_flags & FIF_FCSFAIL));
506 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
507 !(filter_flags & FIF_PLCPFAIL));
508 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
509 !(filter_flags & FIF_PROMISC_IN_BSS));
510 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
511 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
512 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
513 !(filter_flags & FIF_ALLMULTI));
514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
515 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
517 !(filter_flags & FIF_CONTROL));
518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
519 !(filter_flags & FIF_CONTROL));
520 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
521 !(filter_flags & FIF_CONTROL));
522 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
523 !(filter_flags & FIF_CONTROL));
524 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
525 !(filter_flags & FIF_CONTROL));
526 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
527 !(filter_flags & FIF_PSPOLL));
528 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
529 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
530 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
531 !(filter_flags & FIF_CONTROL));
532 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
533}
534EXPORT_SYMBOL_GPL(rt2800_config_filter);
535
536void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
537 struct rt2x00intf_conf *conf, const unsigned int flags)
538{
539 unsigned int beacon_base;
540 u32 reg;
541
542 if (flags & CONFIG_UPDATE_TYPE) {
543 /*
544 * Clear current synchronisation setup.
545 * For the Beacon base registers we only need to clear
546 * the first byte since that byte contains the VALID and OWNER
547 * bits which (when set to 0) will invalidate the entire beacon.
548 */
549 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
550 rt2800_register_write(rt2x00dev, beacon_base, 0);
551
552 /*
553 * Enable synchronisation.
554 */
555 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
556 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
557 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
558 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
559 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
560 }
561
562 if (flags & CONFIG_UPDATE_MAC) {
563 reg = le32_to_cpu(conf->mac[1]);
564 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
565 conf->mac[1] = cpu_to_le32(reg);
566
567 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
568 conf->mac, sizeof(conf->mac));
569 }
570
571 if (flags & CONFIG_UPDATE_BSSID) {
572 reg = le32_to_cpu(conf->bssid[1]);
573 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
574 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
575 conf->bssid[1] = cpu_to_le32(reg);
576
577 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
578 conf->bssid, sizeof(conf->bssid));
579 }
580}
581EXPORT_SYMBOL_GPL(rt2800_config_intf);
582
583void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
584{
585 u32 reg;
586
587 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
588 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
589 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
590
591 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
592 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
593 !!erp->short_preamble);
594 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
595 !!erp->short_preamble);
596 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
597
598 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
599 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
600 erp->cts_protection ? 2 : 0);
601 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
602
603 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
604 erp->basic_rates);
605 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
606
607 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
608 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
609 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
610 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
611
612 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
613 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
614 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
615 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
616 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
617 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
618 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
619
620 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
621 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
622 erp->beacon_int * 16);
623 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
624}
625EXPORT_SYMBOL_GPL(rt2800_config_erp);
626
627void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
628{
629 u8 r1;
630 u8 r3;
631
632 rt2800_bbp_read(rt2x00dev, 1, &r1);
633 rt2800_bbp_read(rt2x00dev, 3, &r3);
634
635 /*
636 * Configure the TX antenna.
637 */
638 switch ((int)ant->tx) {
639 case 1:
640 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
641 if (rt2x00_intf_is_pci(rt2x00dev))
642 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
643 break;
644 case 2:
645 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
646 break;
647 case 3:
648 /* Do nothing */
649 break;
650 }
651
652 /*
653 * Configure the RX antenna.
654 */
655 switch ((int)ant->rx) {
656 case 1:
657 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
658 break;
659 case 2:
660 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
661 break;
662 case 3:
663 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
664 break;
665 }
666
667 rt2800_bbp_write(rt2x00dev, 3, r3);
668 rt2800_bbp_write(rt2x00dev, 1, r1);
669}
670EXPORT_SYMBOL_GPL(rt2800_config_ant);
671
672static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
673 struct rt2x00lib_conf *libconf)
674{
675 u16 eeprom;
676 short lna_gain;
677
678 if (libconf->rf.channel <= 14) {
679 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
680 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
681 } else if (libconf->rf.channel <= 64) {
682 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
683 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
684 } else if (libconf->rf.channel <= 128) {
685 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
686 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
687 } else {
688 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
689 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
690 }
691
692 rt2x00dev->lna_gain = lna_gain;
693}
694
695static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
696 struct ieee80211_conf *conf,
697 struct rf_channel *rf,
698 struct channel_info *info)
699{
700 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
701
702 if (rt2x00dev->default_ant.tx == 1)
703 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
704
705 if (rt2x00dev->default_ant.rx == 1) {
706 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
707 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
708 } else if (rt2x00dev->default_ant.rx == 2)
709 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
710
711 if (rf->channel > 14) {
712 /*
713 * When TX power is below 0, we should increase it by 7 to
714 * make it a positive value (Minumum value is -7).
715 * However this means that values between 0 and 7 have
716 * double meaning, and we should set a 7DBm boost flag.
717 */
718 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
719 (info->tx_power1 >= 0));
720
721 if (info->tx_power1 < 0)
722 info->tx_power1 += 7;
723
724 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
725 TXPOWER_A_TO_DEV(info->tx_power1));
726
727 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
728 (info->tx_power2 >= 0));
729
730 if (info->tx_power2 < 0)
731 info->tx_power2 += 7;
732
733 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
734 TXPOWER_A_TO_DEV(info->tx_power2));
735 } else {
736 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
737 TXPOWER_G_TO_DEV(info->tx_power1));
738 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
739 TXPOWER_G_TO_DEV(info->tx_power2));
740 }
741
742 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
743
744 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
745 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
746 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
747 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
748
749 udelay(200);
750
751 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
752 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
753 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
754 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
755
756 udelay(200);
757
758 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
759 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
760 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
761 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
762}
763
764static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
765 struct ieee80211_conf *conf,
766 struct rf_channel *rf,
767 struct channel_info *info)
768{
769 u8 rfcsr;
770
771 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
772 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf3);
773
774 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
775 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
776 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
777
778 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
779 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
780 TXPOWER_G_TO_DEV(info->tx_power1));
781 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
782
783 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
784 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
785 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
786
787 rt2800_rfcsr_write(rt2x00dev, 24,
788 rt2x00dev->calibration[conf_is_ht40(conf)]);
789
790 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
791 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
792 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
793}
794
795static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
796 struct ieee80211_conf *conf,
797 struct rf_channel *rf,
798 struct channel_info *info)
799{
800 u32 reg;
801 unsigned int tx_pin;
802 u8 bbp;
803
804 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
805 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
806 else
807 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
808
809 /*
810 * Change BBP settings
811 */
812 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
813 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
814 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
815 rt2800_bbp_write(rt2x00dev, 86, 0);
816
817 if (rf->channel <= 14) {
818 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
819 rt2800_bbp_write(rt2x00dev, 82, 0x62);
820 rt2800_bbp_write(rt2x00dev, 75, 0x46);
821 } else {
822 rt2800_bbp_write(rt2x00dev, 82, 0x84);
823 rt2800_bbp_write(rt2x00dev, 75, 0x50);
824 }
825 } else {
826 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
827
828 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
829 rt2800_bbp_write(rt2x00dev, 75, 0x46);
830 else
831 rt2800_bbp_write(rt2x00dev, 75, 0x50);
832 }
833
834 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
835 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
836 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
837 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
838 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
839
840 tx_pin = 0;
841
842 /* Turn on unused PA or LNA when not using 1T or 1R */
843 if (rt2x00dev->default_ant.tx != 1) {
844 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
845 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
846 }
847
848 /* Turn on unused PA or LNA when not using 1T or 1R */
849 if (rt2x00dev->default_ant.rx != 1) {
850 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
851 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
852 }
853
854 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
855 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
856 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
857 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
858 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
859 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
860
861 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
862
863 rt2800_bbp_read(rt2x00dev, 4, &bbp);
864 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
865 rt2800_bbp_write(rt2x00dev, 4, bbp);
866
867 rt2800_bbp_read(rt2x00dev, 3, &bbp);
868 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
869 rt2800_bbp_write(rt2x00dev, 3, bbp);
870
871 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
872 if (conf_is_ht40(conf)) {
873 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
874 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
875 rt2800_bbp_write(rt2x00dev, 73, 0x16);
876 } else {
877 rt2800_bbp_write(rt2x00dev, 69, 0x16);
878 rt2800_bbp_write(rt2x00dev, 70, 0x08);
879 rt2800_bbp_write(rt2x00dev, 73, 0x11);
880 }
881 }
882
883 msleep(1);
884}
885
886static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
887 const int txpower)
888{
889 u32 reg;
890 u32 value = TXPOWER_G_TO_DEV(txpower);
891 u8 r1;
892
893 rt2800_bbp_read(rt2x00dev, 1, &r1);
894 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
895 rt2800_bbp_write(rt2x00dev, 1, r1);
896
897 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
898 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
899 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
900 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
901 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
902 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
903 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
904 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
905 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
906 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
907
908 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
909 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
910 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
911 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
912 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
913 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
914 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
915 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
916 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
917 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
918
919 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
920 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
921 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
922 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
923 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
924 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
925 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
926 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
927 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
928 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
929
930 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
931 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
932 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
933 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
937 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
938 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
939 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
940
941 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
942 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
943 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
944 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
945 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
946 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
947}
948
949static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
950 struct rt2x00lib_conf *libconf)
951{
952 u32 reg;
953
954 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
955 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
956 libconf->conf->short_frame_max_tx_count);
957 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
958 libconf->conf->long_frame_max_tx_count);
959 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
960 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
961 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
962 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
963 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
964}
965
966static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
967 struct rt2x00lib_conf *libconf)
968{
969 enum dev_state state =
970 (libconf->conf->flags & IEEE80211_CONF_PS) ?
971 STATE_SLEEP : STATE_AWAKE;
972 u32 reg;
973
974 if (state == STATE_SLEEP) {
975 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
976
977 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
978 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
979 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
980 libconf->conf->listen_interval - 1);
981 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
982 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
983
984 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
985 } else {
986 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
987
988 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
989 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
990 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
991 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
992 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
993 }
994}
995
996void rt2800_config(struct rt2x00_dev *rt2x00dev,
997 struct rt2x00lib_conf *libconf,
998 const unsigned int flags)
999{
1000 /* Always recalculate LNA gain before changing configuration */
1001 rt2800_config_lna_gain(rt2x00dev, libconf);
1002
1003 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1004 rt2800_config_channel(rt2x00dev, libconf->conf,
1005 &libconf->rf, &libconf->channel);
1006 if (flags & IEEE80211_CONF_CHANGE_POWER)
1007 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1008 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1009 rt2800_config_retry_limit(rt2x00dev, libconf);
1010 if (flags & IEEE80211_CONF_CHANGE_PS)
1011 rt2800_config_ps(rt2x00dev, libconf);
1012}
1013EXPORT_SYMBOL_GPL(rt2800_config);
1014
1015/*
1016 * Link tuning
1017 */
1018void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1019{
1020 u32 reg;
1021
1022 /*
1023 * Update FCS error count from register.
1024 */
1025 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1026 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1027}
1028EXPORT_SYMBOL_GPL(rt2800_link_stats);
1029
1030static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1031{
1032 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1033 if (rt2x00_intf_is_usb(rt2x00dev) &&
1034 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1035 return 0x1c + (2 * rt2x00dev->lna_gain);
1036 else
1037 return 0x2e + rt2x00dev->lna_gain;
1038 }
1039
1040 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1041 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1042 else
1043 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1044}
1045
1046static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1047 struct link_qual *qual, u8 vgc_level)
1048{
1049 if (qual->vgc_level != vgc_level) {
1050 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1051 qual->vgc_level = vgc_level;
1052 qual->vgc_level_reg = vgc_level;
1053 }
1054}
1055
1056void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1057{
1058 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1059}
1060EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1061
1062void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1063 const u32 count)
1064{
1065 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1066 return;
1067
1068 /*
1069 * When RSSI is better then -80 increase VGC level with 0x10
1070 */
1071 rt2800_set_vgc(rt2x00dev, qual,
1072 rt2800_get_default_vgc(rt2x00dev) +
1073 ((qual->rssi > -80) * 0x10));
1074}
1075EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1076
1077/*
1078 * Initialization functions.
1079 */
1080int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1081{
1082 u32 reg;
1083 unsigned int i;
1084
1085 if (rt2x00_intf_is_usb(rt2x00dev)) {
1086 /*
1087 * Wait untill BBP and RF are ready.
1088 */
1089 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1090 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1091 if (reg && reg != ~0)
1092 break;
1093 msleep(1);
1094 }
1095
1096 if (i == REGISTER_BUSY_COUNT) {
1097 ERROR(rt2x00dev, "Unstable hardware.\n");
1098 return -EBUSY;
1099 }
1100
1101 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1102 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1103 reg & ~0x00002000);
1104 } else if (rt2x00_intf_is_pci(rt2x00dev))
1105 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1106
1107 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1108 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1109 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1110 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1111
1112 if (rt2x00_intf_is_usb(rt2x00dev)) {
1113 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1114#ifdef CONFIG_RT2800USB
1115 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1116 USB_MODE_RESET, REGISTER_TIMEOUT);
1117#endif
1118 }
1119
1120 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1121
1122 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1123 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1124 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1125 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1126 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1127 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1128
1129 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1130 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1131 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1132 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1133 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1134 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1135
1136 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1137 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1138
1139 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1140
1141 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1142 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1143 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1144 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1145 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1146 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1147 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1148 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1149
1150 if (rt2x00_intf_is_usb(rt2x00dev) &&
1151 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1152 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1153 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1154 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1155 } else {
1156 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1157 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1158 }
1159
1160 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1161 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1162 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1163 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1164 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1165 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1166 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1167 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1168 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1169 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1170
1171 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1172 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1173 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1174 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1175
1176 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1177 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1178 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1179 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1180 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1181 else
1182 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1183 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1184 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1185 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1186
1187 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1188
1189 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1190 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1191 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1192 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1193 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1194 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1195 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1196
1197 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1198 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1199 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1200 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1201 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1202 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1203 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1204 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1205 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1206 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1207 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1208
1209 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1210 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1211 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1212 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1213 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1214 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1215 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1216 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1217 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1218 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1219 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1220
1221 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1222 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1223 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1224 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1225 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1226 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1227 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1228 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1229 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1230 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1231 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1232
1233 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1234 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1235 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1236 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1237 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1238 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1239 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1240 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1241 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1242 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1243 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1244
1245 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1246 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1247 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1248 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1249 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1250 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1251 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1252 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1253 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1254 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1255 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1256
1257 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1258 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1259 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1260 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1261 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1262 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1263 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1264 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1265 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1266 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1267 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1268
1269 if (rt2x00_intf_is_usb(rt2x00dev)) {
1270 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1271
1272 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1273 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1274 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1275 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1276 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1277 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1278 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1279 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1282 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1283 }
1284
1285 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1286 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1287
1288 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1289 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1290 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1291 IEEE80211_MAX_RTS_THRESHOLD);
1292 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1293 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1294
1295 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1296 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1297
1298 /*
1299 * ASIC will keep garbage value after boot, clear encryption keys.
1300 */
1301 for (i = 0; i < 4; i++)
1302 rt2800_register_write(rt2x00dev,
1303 SHARED_KEY_MODE_ENTRY(i), 0);
1304
1305 for (i = 0; i < 256; i++) {
1306 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1307 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1308 wcid, sizeof(wcid));
1309
1310 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1311 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1312 }
1313
1314 /*
1315 * Clear all beacons
1316 * For the Beacon base registers we only need to clear
1317 * the first byte since that byte contains the VALID and OWNER
1318 * bits which (when set to 0) will invalidate the entire beacon.
1319 */
1320 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1321 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1322 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1323 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1324 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1325 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1326 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1327 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1328
1329 if (rt2x00_intf_is_usb(rt2x00dev)) {
1330 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1331 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1332 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1333 }
1334
1335 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1336 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1337 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1338 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1339 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1340 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1341 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1342 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1343 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1344 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1345
1346 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1347 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1348 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1349 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1350 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1351 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1352 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1353 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1354 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1355 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1356
1357 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1358 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1359 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1360 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1361 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1362 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1363 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1364 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1365 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1366 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1367
1368 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1369 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1370 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1371 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1372 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1373 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1374
1375 /*
1376 * We must clear the error counters.
1377 * These registers are cleared on read,
1378 * so we may pass a useless variable to store the value.
1379 */
1380 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1381 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1382 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1383 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1384 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1385 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1386
1387 return 0;
1388}
1389EXPORT_SYMBOL_GPL(rt2800_init_registers);
1390
1391static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1392{
1393 unsigned int i;
1394 u32 reg;
1395
1396 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1397 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1398 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1399 return 0;
1400
1401 udelay(REGISTER_BUSY_DELAY);
1402 }
1403
1404 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1405 return -EACCES;
1406}
1407
1408static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1409{
1410 unsigned int i;
1411 u8 value;
1412
1413 /*
1414 * BBP was enabled after firmware was loaded,
1415 * but we need to reactivate it now.
1416 */
1417 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1418 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1419 msleep(1);
1420
1421 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1422 rt2800_bbp_read(rt2x00dev, 0, &value);
1423 if ((value != 0xff) && (value != 0x00))
1424 return 0;
1425 udelay(REGISTER_BUSY_DELAY);
1426 }
1427
1428 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1429 return -EACCES;
1430}
1431
1432int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1433{
1434 unsigned int i;
1435 u16 eeprom;
1436 u8 reg_id;
1437 u8 value;
1438
1439 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1440 rt2800_wait_bbp_ready(rt2x00dev)))
1441 return -EACCES;
1442
1443 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1444 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1445 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1446 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1447 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1448 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1449 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1450 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1451 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1452 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1453 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1454 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1455 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1456 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1457
1458 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1459 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1460 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1461 }
1462
1463 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1464 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1465
1466 if (rt2x00_intf_is_usb(rt2x00dev) &&
1467 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1468 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1469 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1470 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1471 }
1472
1473 if (rt2x00_intf_is_pci(rt2x00dev) &&
1474 rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1475 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1476 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1477 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1478 }
1479
1480 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1481 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1482
1483 if (eeprom != 0xffff && eeprom != 0x0000) {
1484 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1485 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1486 rt2800_bbp_write(rt2x00dev, reg_id, value);
1487 }
1488 }
1489
1490 return 0;
1491}
1492EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1493
1494static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1495 bool bw40, u8 rfcsr24, u8 filter_target)
1496{
1497 unsigned int i;
1498 u8 bbp;
1499 u8 rfcsr;
1500 u8 passband;
1501 u8 stopband;
1502 u8 overtuned = 0;
1503
1504 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1505
1506 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1507 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1508 rt2800_bbp_write(rt2x00dev, 4, bbp);
1509
1510 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1511 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1512 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1513
1514 /*
1515 * Set power & frequency of passband test tone
1516 */
1517 rt2800_bbp_write(rt2x00dev, 24, 0);
1518
1519 for (i = 0; i < 100; i++) {
1520 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1521 msleep(1);
1522
1523 rt2800_bbp_read(rt2x00dev, 55, &passband);
1524 if (passband)
1525 break;
1526 }
1527
1528 /*
1529 * Set power & frequency of stopband test tone
1530 */
1531 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1532
1533 for (i = 0; i < 100; i++) {
1534 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1535 msleep(1);
1536
1537 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1538
1539 if ((passband - stopband) <= filter_target) {
1540 rfcsr24++;
1541 overtuned += ((passband - stopband) == filter_target);
1542 } else
1543 break;
1544
1545 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1546 }
1547
1548 rfcsr24 -= !!overtuned;
1549
1550 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1551 return rfcsr24;
1552}
1553
1554int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1555{
1556 u8 rfcsr;
1557 u8 bbp;
1558
1559 if (rt2x00_intf_is_usb(rt2x00dev) &&
1560 rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1561 return 0;
1562
1563 if (rt2x00_intf_is_pci(rt2x00dev)) {
1564 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1565 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1566 !rt2x00_rf(&rt2x00dev->chip, RF3022))
1567 return 0;
1568 }
1569
1570 /*
1571 * Init RF calibration.
1572 */
1573 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1574 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1575 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1576 msleep(1);
1577 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1578 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1579
1580 if (rt2x00_intf_is_usb(rt2x00dev)) {
1581 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1582 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1583 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1584 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1585 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1586 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1587 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1588 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1589 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1590 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1591 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1592 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1593 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1594 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1595 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1596 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1597 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1598 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1599 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1600 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1601 } else if (rt2x00_intf_is_pci(rt2x00dev)) {
1602 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1603 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1604 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1605 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1606 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1607 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1608 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1609 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1610 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1611 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1612 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1613 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1614 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1615 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1616 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1617 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1618 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1619 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1620 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1621 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1622 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1623 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1624 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1625 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1626 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1627 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1628 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1629 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1630 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1631 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1632 }
1633
1634 /*
1635 * Set RX Filter calibration for 20MHz and 40MHz
1636 */
1637 rt2x00dev->calibration[0] =
1638 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1639 rt2x00dev->calibration[1] =
1640 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1641
1642 /*
1643 * Set back to initial state
1644 */
1645 rt2800_bbp_write(rt2x00dev, 24, 0);
1646
1647 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1648 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1649 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1650
1651 /*
1652 * set BBP back to BW20
1653 */
1654 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1655 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1656 rt2800_bbp_write(rt2x00dev, 4, bbp);
1657
1658 return 0;
1659}
1660EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1661
1662/*
1663 * IEEE80211 stack callback functions.
1664 */
1665static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
1666 u32 *iv32, u16 *iv16)
1667{
1668 struct rt2x00_dev *rt2x00dev = hw->priv;
1669 struct mac_iveiv_entry iveiv_entry;
1670 u32 offset;
1671
1672 offset = MAC_IVEIV_ENTRY(hw_key_idx);
1673 rt2800_register_multiread(rt2x00dev, offset,
1674 &iveiv_entry, sizeof(iveiv_entry));
1675
1676 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
1677 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
1678}
1679
1680static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
1681{
1682 struct rt2x00_dev *rt2x00dev = hw->priv;
1683 u32 reg;
1684 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
1685
1686 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1687 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
1688 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1689
1690 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1691 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
1692 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1693
1694 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1695 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
1696 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1697
1698 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1699 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
1700 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1701
1702 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1703 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
1704 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1705
1706 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1707 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
1708 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1709
1710 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1711 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
1712 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1713
1714 return 0;
1715}
1716
1717static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
1718 const struct ieee80211_tx_queue_params *params)
1719{
1720 struct rt2x00_dev *rt2x00dev = hw->priv;
1721 struct data_queue *queue;
1722 struct rt2x00_field32 field;
1723 int retval;
1724 u32 reg;
1725 u32 offset;
1726
1727 /*
1728 * First pass the configuration through rt2x00lib, that will
1729 * update the queue settings and validate the input. After that
1730 * we are free to update the registers based on the value
1731 * in the queue parameter.
1732 */
1733 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
1734 if (retval)
1735 return retval;
1736
1737 /*
1738 * We only need to perform additional register initialization
1739 * for WMM queues/
1740 */
1741 if (queue_idx >= 4)
1742 return 0;
1743
1744 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1745
1746 /* Update WMM TXOP register */
1747 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
1748 field.bit_offset = (queue_idx & 1) * 16;
1749 field.bit_mask = 0xffff << field.bit_offset;
1750
1751 rt2800_register_read(rt2x00dev, offset, &reg);
1752 rt2x00_set_field32(&reg, field, queue->txop);
1753 rt2800_register_write(rt2x00dev, offset, reg);
1754
1755 /* Update WMM registers */
1756 field.bit_offset = queue_idx * 4;
1757 field.bit_mask = 0xf << field.bit_offset;
1758
1759 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
1760 rt2x00_set_field32(&reg, field, queue->aifs);
1761 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
1762
1763 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
1764 rt2x00_set_field32(&reg, field, queue->cw_min);
1765 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
1766
1767 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
1768 rt2x00_set_field32(&reg, field, queue->cw_max);
1769 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
1770
1771 /* Update EDCA registers */
1772 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
1773
1774 rt2800_register_read(rt2x00dev, offset, &reg);
1775 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
1776 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
1777 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
1778 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
1779 rt2800_register_write(rt2x00dev, offset, reg);
1780
1781 return 0;
1782}
1783
1784static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
1785{
1786 struct rt2x00_dev *rt2x00dev = hw->priv;
1787 u64 tsf;
1788 u32 reg;
1789
1790 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
1791 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
1792 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
1793 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
1794
1795 return tsf;
1796}
1797
1798const struct ieee80211_ops rt2800_mac80211_ops = {
1799 .tx = rt2x00mac_tx,
1800 .start = rt2x00mac_start,
1801 .stop = rt2x00mac_stop,
1802 .add_interface = rt2x00mac_add_interface,
1803 .remove_interface = rt2x00mac_remove_interface,
1804 .config = rt2x00mac_config,
1805 .configure_filter = rt2x00mac_configure_filter,
1806 .set_tim = rt2x00mac_set_tim,
1807 .set_key = rt2x00mac_set_key,
1808 .get_stats = rt2x00mac_get_stats,
1809 .get_tkip_seq = rt2800_get_tkip_seq,
1810 .set_rts_threshold = rt2800_set_rts_threshold,
1811 .bss_info_changed = rt2x00mac_bss_info_changed,
1812 .conf_tx = rt2800_conf_tx,
1813 .get_tx_stats = rt2x00mac_get_tx_stats,
1814 .get_tsf = rt2800_get_tsf,
1815 .rfkill_poll = rt2x00mac_rfkill_poll,
1816};
1817EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.h b/drivers/net/wireless/rt2x00/rt2800lib.h
new file mode 100644
index 000000000000..5eea8fcba6cc
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800lib.h
@@ -0,0 +1,134 @@
1/*
2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the
16 Free Software Foundation, Inc.,
17 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20#ifndef RT2800LIB_H
21#define RT2800LIB_H
22
23struct rt2800_ops {
24 void (*register_read)(struct rt2x00_dev *rt2x00dev,
25 const unsigned int offset, u32 *value);
26 void (*register_write)(struct rt2x00_dev *rt2x00dev,
27 const unsigned int offset, u32 value);
28 void (*register_write_lock)(struct rt2x00_dev *rt2x00dev,
29 const unsigned int offset, u32 value);
30
31 void (*register_multiread)(struct rt2x00_dev *rt2x00dev,
32 const unsigned int offset,
33 void *value, const u32 length);
34 void (*register_multiwrite)(struct rt2x00_dev *rt2x00dev,
35 const unsigned int offset,
36 const void *value, const u32 length);
37
38 int (*regbusy_read)(struct rt2x00_dev *rt2x00dev,
39 const unsigned int offset,
40 const struct rt2x00_field32 field, u32 *reg);
41};
42
43static inline void rt2800_register_read(struct rt2x00_dev *rt2x00dev,
44 const unsigned int offset,
45 u32 *value)
46{
47 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
48
49 rt2800ops->register_read(rt2x00dev, offset, value);
50}
51
52static inline void rt2800_register_write(struct rt2x00_dev *rt2x00dev,
53 const unsigned int offset,
54 u32 value)
55{
56 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
57
58 rt2800ops->register_write(rt2x00dev, offset, value);
59}
60
61static inline void rt2800_register_write_lock(struct rt2x00_dev *rt2x00dev,
62 const unsigned int offset,
63 u32 value)
64{
65 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
66
67 rt2800ops->register_write_lock(rt2x00dev, offset, value);
68}
69
70static inline void rt2800_register_multiread(struct rt2x00_dev *rt2x00dev,
71 const unsigned int offset,
72 void *value, const u32 length)
73{
74 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
75
76 rt2800ops->register_multiread(rt2x00dev, offset, value, length);
77}
78
79static inline void rt2800_register_multiwrite(struct rt2x00_dev *rt2x00dev,
80 const unsigned int offset,
81 const void *value,
82 const u32 length)
83{
84 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
85
86 rt2800ops->register_multiwrite(rt2x00dev, offset, value, length);
87}
88
89static inline int rt2800_regbusy_read(struct rt2x00_dev *rt2x00dev,
90 const unsigned int offset,
91 const struct rt2x00_field32 field,
92 u32 *reg)
93{
94 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
95
96 return rt2800ops->regbusy_read(rt2x00dev, offset, field, reg);
97}
98
99void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
100 const u8 command, const u8 token,
101 const u8 arg0, const u8 arg1);
102
103extern const struct rt2x00debug rt2800_rt2x00debug;
104
105int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev);
106void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
107 struct rt2x00_led *led, enum led_type type);
108int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
109 struct rt2x00lib_crypto *crypto,
110 struct ieee80211_key_conf *key);
111int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
112 struct rt2x00lib_crypto *crypto,
113 struct ieee80211_key_conf *key);
114void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
115 const unsigned int filter_flags);
116void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
117 struct rt2x00intf_conf *conf, const unsigned int flags);
118void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp);
119void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant);
120void rt2800_config(struct rt2x00_dev *rt2x00dev,
121 struct rt2x00lib_conf *libconf,
122 const unsigned int flags);
123void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual);
124void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual);
125void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
126 const u32 count);
127
128int rt2800_init_registers(struct rt2x00_dev *rt2x00dev);
129int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev);
130int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev);
131
132extern const struct ieee80211_ops rt2800_mac80211_ops;
133
134#endif /* RT2800LIB_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index be81788b80c7..3c5b875cdee8 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -37,6 +37,8 @@
37#include "rt2x00.h" 37#include "rt2x00.h"
38#include "rt2x00pci.h" 38#include "rt2x00pci.h"
39#include "rt2x00soc.h" 39#include "rt2x00soc.h"
40#include "rt2800lib.h"
41#include "rt2800.h"
40#include "rt2800pci.h" 42#include "rt2800pci.h"
41 43
42#ifdef CONFIG_RT2800PCI_PCI_MODULE 44#ifdef CONFIG_RT2800PCI_PCI_MODULE
@@ -54,205 +56,13 @@ static int modparam_nohwcrypt = 1;
54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 56module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 57MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56 58
57/*
58 * Register access.
59 * BBP and RF register require indirect register access,
60 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
61 * These indirect registers work with busy bits,
62 * and we will try maximal REGISTER_BUSY_COUNT times to access
63 * the register while taking a REGISTER_BUSY_DELAY us delay
64 * between each attampt. When the busy bit is still set at that time,
65 * the access attempt is considered to have failed,
66 * and we will print an error.
67 */
68#define WAIT_FOR_BBP(__dev, __reg) \
69 rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
70#define WAIT_FOR_RFCSR(__dev, __reg) \
71 rt2x00pci_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
72#define WAIT_FOR_RF(__dev, __reg) \
73 rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
74#define WAIT_FOR_MCU(__dev, __reg) \
75 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
76 H2M_MAILBOX_CSR_OWNER, (__reg))
77
78static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
79 const unsigned int word, const u8 value)
80{
81 u32 reg;
82
83 mutex_lock(&rt2x00dev->csr_mutex);
84
85 /*
86 * Wait until the BBP becomes available, afterwards we
87 * can safely write the new data into the register.
88 */
89 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
90 reg = 0;
91 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
92 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
93 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
94 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
95 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
96
97 rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
98 }
99
100 mutex_unlock(&rt2x00dev->csr_mutex);
101}
102
103static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
104 const unsigned int word, u8 *value)
105{
106 u32 reg;
107
108 mutex_lock(&rt2x00dev->csr_mutex);
109
110 /*
111 * Wait until the BBP becomes available, afterwards we
112 * can safely write the read request into the register.
113 * After the data has been written, we wait until hardware
114 * returns the correct value, if at any time the register
115 * doesn't become available in time, reg will be 0xffffffff
116 * which means we return 0xff to the caller.
117 */
118 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
119 reg = 0;
120 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
121 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
122 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
123 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
124
125 rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
126
127 WAIT_FOR_BBP(rt2x00dev, &reg);
128 }
129
130 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
131
132 mutex_unlock(&rt2x00dev->csr_mutex);
133}
134
135static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
136 const unsigned int word, const u8 value)
137{
138 u32 reg;
139
140 mutex_lock(&rt2x00dev->csr_mutex);
141
142 /*
143 * Wait until the RFCSR becomes available, afterwards we
144 * can safely write the new data into the register.
145 */
146 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
147 reg = 0;
148 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
149 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
150 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
151 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
152
153 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
154 }
155
156 mutex_unlock(&rt2x00dev->csr_mutex);
157}
158
159static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
160 const unsigned int word, u8 *value)
161{
162 u32 reg;
163
164 mutex_lock(&rt2x00dev->csr_mutex);
165
166 /*
167 * Wait until the RFCSR becomes available, afterwards we
168 * can safely write the read request into the register.
169 * After the data has been written, we wait until hardware
170 * returns the correct value, if at any time the register
171 * doesn't become available in time, reg will be 0xffffffff
172 * which means we return 0xff to the caller.
173 */
174 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
175 reg = 0;
176 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
177 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
178 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
179
180 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
181
182 WAIT_FOR_RFCSR(rt2x00dev, &reg);
183 }
184
185 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
186
187 mutex_unlock(&rt2x00dev->csr_mutex);
188}
189
190static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
191 const unsigned int word, const u32 value)
192{
193 u32 reg;
194
195 mutex_lock(&rt2x00dev->csr_mutex);
196
197 /*
198 * Wait until the RF becomes available, afterwards we
199 * can safely write the new data into the register.
200 */
201 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
202 reg = 0;
203 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
204 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
205 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
206 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
207
208 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
209 rt2x00_rf_write(rt2x00dev, word, value);
210 }
211
212 mutex_unlock(&rt2x00dev->csr_mutex);
213}
214
215static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
216 const u8 command, const u8 token,
217 const u8 arg0, const u8 arg1)
218{
219 u32 reg;
220
221 /*
222 * RT2880 and RT3052 don't support MCU requests.
223 */
224 if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
225 rt2x00_rt(&rt2x00dev->chip, RT3052))
226 return;
227
228 mutex_lock(&rt2x00dev->csr_mutex);
229
230 /*
231 * Wait until the MCU becomes available, afterwards we
232 * can safely write the new data into the register.
233 */
234 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
235 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
236 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
237 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
238 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
239 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
240
241 reg = 0;
242 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
243 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
244 }
245
246 mutex_unlock(&rt2x00dev->csr_mutex);
247}
248
249static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token) 59static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
250{ 60{
251 unsigned int i; 61 unsigned int i;
252 u32 reg; 62 u32 reg;
253 63
254 for (i = 0; i < 200; i++) { 64 for (i = 0; i < 200; i++) {
255 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg); 65 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
256 66
257 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || 67 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
258 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || 68 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
@@ -266,8 +76,8 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
266 if (i == 200) 76 if (i == 200)
267 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n"); 77 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
268 78
269 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 79 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
270 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 80 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
271} 81}
272 82
273#ifdef CONFIG_RT2800PCI_WISOC 83#ifdef CONFIG_RT2800PCI_WISOC
@@ -289,7 +99,7 @@ static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
289 struct rt2x00_dev *rt2x00dev = eeprom->data; 99 struct rt2x00_dev *rt2x00dev = eeprom->data;
290 u32 reg; 100 u32 reg;
291 101
292 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 102 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
293 103
294 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); 104 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
295 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); 105 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
@@ -311,7 +121,7 @@ static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
311 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT, 121 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
312 !!eeprom->reg_chip_select); 122 !!eeprom->reg_chip_select);
313 123
314 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg); 124 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
315} 125}
316 126
317static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) 127static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
@@ -319,7 +129,7 @@ static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
319 struct eeprom_93cx6 eeprom; 129 struct eeprom_93cx6 eeprom;
320 u32 reg; 130 u32 reg;
321 131
322 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 132 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
323 133
324 eeprom.data = rt2x00dev; 134 eeprom.data = rt2x00dev;
325 eeprom.register_read = rt2800pci_eepromregister_read; 135 eeprom.register_read = rt2800pci_eepromregister_read;
@@ -340,23 +150,23 @@ static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
340{ 150{
341 u32 reg; 151 u32 reg;
342 152
343 rt2x00pci_register_read(rt2x00dev, EFUSE_CTRL, &reg); 153 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
344 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i); 154 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
345 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0); 155 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
346 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1); 156 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
347 rt2x00pci_register_write(rt2x00dev, EFUSE_CTRL, reg); 157 rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
348 158
349 /* Wait until the EEPROM has been loaded */ 159 /* Wait until the EEPROM has been loaded */
350 rt2x00pci_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg); 160 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
351 161
352 /* Apparently the data is read from end to start */ 162 /* Apparently the data is read from end to start */
353 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA3, 163 rt2800_register_read(rt2x00dev, EFUSE_DATA3,
354 (u32 *)&rt2x00dev->eeprom[i]); 164 (u32 *)&rt2x00dev->eeprom[i]);
355 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA2, 165 rt2800_register_read(rt2x00dev, EFUSE_DATA2,
356 (u32 *)&rt2x00dev->eeprom[i + 2]); 166 (u32 *)&rt2x00dev->eeprom[i + 2]);
357 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA1, 167 rt2800_register_read(rt2x00dev, EFUSE_DATA1,
358 (u32 *)&rt2x00dev->eeprom[i + 4]); 168 (u32 *)&rt2x00dev->eeprom[i + 4]);
359 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA0, 169 rt2800_register_read(rt2x00dev, EFUSE_DATA0,
360 (u32 *)&rt2x00dev->eeprom[i + 6]); 170 (u32 *)&rt2x00dev->eeprom[i + 6]);
361} 171}
362 172
@@ -377,829 +187,6 @@ static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
377} 187}
378#endif /* CONFIG_RT2800PCI_PCI */ 188#endif /* CONFIG_RT2800PCI_PCI */
379 189
380#ifdef CONFIG_RT2X00_LIB_DEBUGFS
381static const struct rt2x00debug rt2800pci_rt2x00debug = {
382 .owner = THIS_MODULE,
383 .csr = {
384 .read = rt2x00pci_register_read,
385 .write = rt2x00pci_register_write,
386 .flags = RT2X00DEBUGFS_OFFSET,
387 .word_base = CSR_REG_BASE,
388 .word_size = sizeof(u32),
389 .word_count = CSR_REG_SIZE / sizeof(u32),
390 },
391 .eeprom = {
392 .read = rt2x00_eeprom_read,
393 .write = rt2x00_eeprom_write,
394 .word_base = EEPROM_BASE,
395 .word_size = sizeof(u16),
396 .word_count = EEPROM_SIZE / sizeof(u16),
397 },
398 .bbp = {
399 .read = rt2800pci_bbp_read,
400 .write = rt2800pci_bbp_write,
401 .word_base = BBP_BASE,
402 .word_size = sizeof(u8),
403 .word_count = BBP_SIZE / sizeof(u8),
404 },
405 .rf = {
406 .read = rt2x00_rf_read,
407 .write = rt2800pci_rf_write,
408 .word_base = RF_BASE,
409 .word_size = sizeof(u32),
410 .word_count = RF_SIZE / sizeof(u32),
411 },
412};
413#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
414
415static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
416{
417 u32 reg;
418
419 rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
420 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
421}
422
423#ifdef CONFIG_RT2X00_LIB_LEDS
424static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
425 enum led_brightness brightness)
426{
427 struct rt2x00_led *led =
428 container_of(led_cdev, struct rt2x00_led, led_dev);
429 unsigned int enabled = brightness != LED_OFF;
430 unsigned int bg_mode =
431 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
432 unsigned int polarity =
433 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
434 EEPROM_FREQ_LED_POLARITY);
435 unsigned int ledmode =
436 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
437 EEPROM_FREQ_LED_MODE);
438
439 if (led->type == LED_TYPE_RADIO) {
440 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
441 enabled ? 0x20 : 0);
442 } else if (led->type == LED_TYPE_ASSOC) {
443 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
444 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
445 } else if (led->type == LED_TYPE_QUALITY) {
446 /*
447 * The brightness is divided into 6 levels (0 - 5),
448 * The specs tell us the following levels:
449 * 0, 1 ,3, 7, 15, 31
450 * to determine the level in a simple way we can simply
451 * work with bitshifting:
452 * (1 << level) - 1
453 */
454 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
455 (1 << brightness / (LED_FULL / 6)) - 1,
456 polarity);
457 }
458}
459
460static int rt2800pci_blink_set(struct led_classdev *led_cdev,
461 unsigned long *delay_on,
462 unsigned long *delay_off)
463{
464 struct rt2x00_led *led =
465 container_of(led_cdev, struct rt2x00_led, led_dev);
466 u32 reg;
467
468 rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
469 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
470 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
471 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
472 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
473 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
474 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
475 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
476 rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
477
478 return 0;
479}
480
481static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
482 struct rt2x00_led *led,
483 enum led_type type)
484{
485 led->rt2x00dev = rt2x00dev;
486 led->type = type;
487 led->led_dev.brightness_set = rt2800pci_brightness_set;
488 led->led_dev.blink_set = rt2800pci_blink_set;
489 led->flags = LED_INITIALIZED;
490}
491#endif /* CONFIG_RT2X00_LIB_LEDS */
492
493/*
494 * Configuration handlers.
495 */
496static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
497 struct rt2x00lib_crypto *crypto,
498 struct ieee80211_key_conf *key)
499{
500 struct mac_wcid_entry wcid_entry;
501 struct mac_iveiv_entry iveiv_entry;
502 u32 offset;
503 u32 reg;
504
505 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
506
507 rt2x00pci_register_read(rt2x00dev, offset, &reg);
508 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
509 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
510 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
511 (crypto->cmd == SET_KEY) * crypto->cipher);
512 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
513 (crypto->cmd == SET_KEY) * crypto->bssidx);
514 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
515 rt2x00pci_register_write(rt2x00dev, offset, reg);
516
517 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
518
519 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
520 if ((crypto->cipher == CIPHER_TKIP) ||
521 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
522 (crypto->cipher == CIPHER_AES))
523 iveiv_entry.iv[3] |= 0x20;
524 iveiv_entry.iv[3] |= key->keyidx << 6;
525 rt2x00pci_register_multiwrite(rt2x00dev, offset,
526 &iveiv_entry, sizeof(iveiv_entry));
527
528 offset = MAC_WCID_ENTRY(key->hw_key_idx);
529
530 memset(&wcid_entry, 0, sizeof(wcid_entry));
531 if (crypto->cmd == SET_KEY)
532 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
533 rt2x00pci_register_multiwrite(rt2x00dev, offset,
534 &wcid_entry, sizeof(wcid_entry));
535}
536
537static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
538 struct rt2x00lib_crypto *crypto,
539 struct ieee80211_key_conf *key)
540{
541 struct hw_key_entry key_entry;
542 struct rt2x00_field32 field;
543 u32 offset;
544 u32 reg;
545
546 if (crypto->cmd == SET_KEY) {
547 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
548
549 memcpy(key_entry.key, crypto->key,
550 sizeof(key_entry.key));
551 memcpy(key_entry.tx_mic, crypto->tx_mic,
552 sizeof(key_entry.tx_mic));
553 memcpy(key_entry.rx_mic, crypto->rx_mic,
554 sizeof(key_entry.rx_mic));
555
556 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
557 rt2x00pci_register_multiwrite(rt2x00dev, offset,
558 &key_entry, sizeof(key_entry));
559 }
560
561 /*
562 * The cipher types are stored over multiple registers
563 * starting with SHARED_KEY_MODE_BASE each word will have
564 * 32 bits and contains the cipher types for 2 bssidx each.
565 * Using the correct defines correctly will cause overhead,
566 * so just calculate the correct offset.
567 */
568 field.bit_offset = 4 * (key->hw_key_idx % 8);
569 field.bit_mask = 0x7 << field.bit_offset;
570
571 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
572
573 rt2x00pci_register_read(rt2x00dev, offset, &reg);
574 rt2x00_set_field32(&reg, field,
575 (crypto->cmd == SET_KEY) * crypto->cipher);
576 rt2x00pci_register_write(rt2x00dev, offset, reg);
577
578 /*
579 * Update WCID information
580 */
581 rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
582
583 return 0;
584}
585
586static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
587 struct rt2x00lib_crypto *crypto,
588 struct ieee80211_key_conf *key)
589{
590 struct hw_key_entry key_entry;
591 u32 offset;
592
593 if (crypto->cmd == SET_KEY) {
594 /*
595 * 1 pairwise key is possible per AID, this means that the AID
596 * equals our hw_key_idx. Make sure the WCID starts _after_ the
597 * last possible shared key entry.
598 */
599 if (crypto->aid > (256 - 32))
600 return -ENOSPC;
601
602 key->hw_key_idx = 32 + crypto->aid;
603
604
605 memcpy(key_entry.key, crypto->key,
606 sizeof(key_entry.key));
607 memcpy(key_entry.tx_mic, crypto->tx_mic,
608 sizeof(key_entry.tx_mic));
609 memcpy(key_entry.rx_mic, crypto->rx_mic,
610 sizeof(key_entry.rx_mic));
611
612 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
613 rt2x00pci_register_multiwrite(rt2x00dev, offset,
614 &key_entry, sizeof(key_entry));
615 }
616
617 /*
618 * Update WCID information
619 */
620 rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
621
622 return 0;
623}
624
625static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
626 const unsigned int filter_flags)
627{
628 u32 reg;
629
630 /*
631 * Start configuration steps.
632 * Note that the version error will always be dropped
633 * and broadcast frames will always be accepted since
634 * there is no filter for it at this time.
635 */
636 rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
637 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
638 !(filter_flags & FIF_FCSFAIL));
639 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
640 !(filter_flags & FIF_PLCPFAIL));
641 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
642 !(filter_flags & FIF_PROMISC_IN_BSS));
643 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
644 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
645 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
646 !(filter_flags & FIF_ALLMULTI));
647 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
648 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
649 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
650 !(filter_flags & FIF_CONTROL));
651 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
652 !(filter_flags & FIF_CONTROL));
653 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
654 !(filter_flags & FIF_CONTROL));
655 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
656 !(filter_flags & FIF_CONTROL));
657 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
658 !(filter_flags & FIF_CONTROL));
659 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
660 !(filter_flags & FIF_PSPOLL));
661 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
662 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
663 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
664 !(filter_flags & FIF_CONTROL));
665 rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
666}
667
668static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
669 struct rt2x00_intf *intf,
670 struct rt2x00intf_conf *conf,
671 const unsigned int flags)
672{
673 unsigned int beacon_base;
674 u32 reg;
675
676 if (flags & CONFIG_UPDATE_TYPE) {
677 /*
678 * Clear current synchronisation setup.
679 * For the Beacon base registers we only need to clear
680 * the first byte since that byte contains the VALID and OWNER
681 * bits which (when set to 0) will invalidate the entire beacon.
682 */
683 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
684 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
685
686 /*
687 * Enable synchronisation.
688 */
689 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
690 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
691 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
692 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
693 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
694 }
695
696 if (flags & CONFIG_UPDATE_MAC) {
697 reg = le32_to_cpu(conf->mac[1]);
698 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
699 conf->mac[1] = cpu_to_le32(reg);
700
701 rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
702 conf->mac, sizeof(conf->mac));
703 }
704
705 if (flags & CONFIG_UPDATE_BSSID) {
706 reg = le32_to_cpu(conf->bssid[1]);
707 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
708 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
709 conf->bssid[1] = cpu_to_le32(reg);
710
711 rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
712 conf->bssid, sizeof(conf->bssid));
713 }
714}
715
716static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
717 struct rt2x00lib_erp *erp)
718{
719 u32 reg;
720
721 rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
722 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
723 rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
724
725 rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
726 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
727 !!erp->short_preamble);
728 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
729 !!erp->short_preamble);
730 rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
731
732 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
733 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
734 erp->cts_protection ? 2 : 0);
735 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
736
737 rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
738 erp->basic_rates);
739 rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
740
741 rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
742 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
743 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
744 rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
745
746 rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
747 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
748 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
749 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
750 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
751 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
752 rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
753
754 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
755 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
756 erp->beacon_int * 16);
757 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
758}
759
760static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
761 struct antenna_setup *ant)
762{
763 u8 r1;
764 u8 r3;
765
766 rt2800pci_bbp_read(rt2x00dev, 1, &r1);
767 rt2800pci_bbp_read(rt2x00dev, 3, &r3);
768
769 /*
770 * Configure the TX antenna.
771 */
772 switch ((int)ant->tx) {
773 case 1:
774 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
775 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
776 break;
777 case 2:
778 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
779 break;
780 case 3:
781 /* Do nothing */
782 break;
783 }
784
785 /*
786 * Configure the RX antenna.
787 */
788 switch ((int)ant->rx) {
789 case 1:
790 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
791 break;
792 case 2:
793 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
794 break;
795 case 3:
796 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
797 break;
798 }
799
800 rt2800pci_bbp_write(rt2x00dev, 3, r3);
801 rt2800pci_bbp_write(rt2x00dev, 1, r1);
802}
803
804static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
805 struct rt2x00lib_conf *libconf)
806{
807 u16 eeprom;
808 short lna_gain;
809
810 if (libconf->rf.channel <= 14) {
811 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
812 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
813 } else if (libconf->rf.channel <= 64) {
814 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
815 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
816 } else if (libconf->rf.channel <= 128) {
817 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
818 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
819 } else {
820 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
821 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
822 }
823
824 rt2x00dev->lna_gain = lna_gain;
825}
826
827static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
828 struct ieee80211_conf *conf,
829 struct rf_channel *rf,
830 struct channel_info *info)
831{
832 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
833
834 if (rt2x00dev->default_ant.tx == 1)
835 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
836
837 if (rt2x00dev->default_ant.rx == 1) {
838 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
839 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
840 } else if (rt2x00dev->default_ant.rx == 2)
841 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
842
843 if (rf->channel > 14) {
844 /*
845 * When TX power is below 0, we should increase it by 7 to
846 * make it a positive value (Minumum value is -7).
847 * However this means that values between 0 and 7 have
848 * double meaning, and we should set a 7DBm boost flag.
849 */
850 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
851 (info->tx_power1 >= 0));
852
853 if (info->tx_power1 < 0)
854 info->tx_power1 += 7;
855
856 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
857 TXPOWER_A_TO_DEV(info->tx_power1));
858
859 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
860 (info->tx_power2 >= 0));
861
862 if (info->tx_power2 < 0)
863 info->tx_power2 += 7;
864
865 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
866 TXPOWER_A_TO_DEV(info->tx_power2));
867 } else {
868 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
869 TXPOWER_G_TO_DEV(info->tx_power1));
870 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
871 TXPOWER_G_TO_DEV(info->tx_power2));
872 }
873
874 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
875
876 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
877 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
878 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
879 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
880
881 udelay(200);
882
883 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
884 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
885 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
886 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
887
888 udelay(200);
889
890 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
891 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
892 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
893 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
894}
895
896static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
897 struct ieee80211_conf *conf,
898 struct rf_channel *rf,
899 struct channel_info *info)
900{
901 u8 rfcsr;
902
903 rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf1);
904 rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf3);
905
906 rt2800pci_rfcsr_read(rt2x00dev, 6, &rfcsr);
907 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
908 rt2800pci_rfcsr_write(rt2x00dev, 6, rfcsr);
909
910 rt2800pci_rfcsr_read(rt2x00dev, 12, &rfcsr);
911 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
912 TXPOWER_G_TO_DEV(info->tx_power1));
913 rt2800pci_rfcsr_write(rt2x00dev, 12, rfcsr);
914
915 rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
916 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
917 rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
918
919 rt2800pci_rfcsr_write(rt2x00dev, 24,
920 rt2x00dev->calibration[conf_is_ht40(conf)]);
921
922 rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
923 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
924 rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
925}
926
927static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
928 struct ieee80211_conf *conf,
929 struct rf_channel *rf,
930 struct channel_info *info)
931{
932 u32 reg;
933 unsigned int tx_pin;
934 u8 bbp;
935
936 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
937 rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
938 else
939 rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
940
941 /*
942 * Change BBP settings
943 */
944 rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
945 rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
946 rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
947 rt2800pci_bbp_write(rt2x00dev, 86, 0);
948
949 if (rf->channel <= 14) {
950 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
951 rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
952 rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
953 } else {
954 rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
955 rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
956 }
957 } else {
958 rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
959
960 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
961 rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
962 else
963 rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
964 }
965
966 rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
967 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
968 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
969 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
970 rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
971
972 tx_pin = 0;
973
974 /* Turn on unused PA or LNA when not using 1T or 1R */
975 if (rt2x00dev->default_ant.tx != 1) {
976 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
977 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
978 }
979
980 /* Turn on unused PA or LNA when not using 1T or 1R */
981 if (rt2x00dev->default_ant.rx != 1) {
982 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
983 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
984 }
985
986 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
987 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
988 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
989 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
990 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
991 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
992
993 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
994
995 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
996 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
997 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
998
999 rt2800pci_bbp_read(rt2x00dev, 3, &bbp);
1000 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
1001 rt2800pci_bbp_write(rt2x00dev, 3, bbp);
1002
1003 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1004 if (conf_is_ht40(conf)) {
1005 rt2800pci_bbp_write(rt2x00dev, 69, 0x1a);
1006 rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1007 rt2800pci_bbp_write(rt2x00dev, 73, 0x16);
1008 } else {
1009 rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1010 rt2800pci_bbp_write(rt2x00dev, 70, 0x08);
1011 rt2800pci_bbp_write(rt2x00dev, 73, 0x11);
1012 }
1013 }
1014
1015 msleep(1);
1016}
1017
1018static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1019 const int txpower)
1020{
1021 u32 reg;
1022 u32 value = TXPOWER_G_TO_DEV(txpower);
1023 u8 r1;
1024
1025 rt2800pci_bbp_read(rt2x00dev, 1, &r1);
1026 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1027 rt2800pci_bbp_write(rt2x00dev, 1, r1);
1028
1029 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1030 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1031 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1032 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1033 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1034 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1035 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1036 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1037 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1038 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1039
1040 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1041 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1042 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1043 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1044 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1045 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1046 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1047 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1048 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1049 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1050
1051 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1052 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1053 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1054 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1055 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1056 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1057 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1058 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1059 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1060 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1061
1062 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1063 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1064 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1065 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1066 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1067 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1068 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1069 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1070 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1071 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1072
1073 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1074 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1075 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1076 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1077 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1078 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1079}
1080
1081static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1082 struct rt2x00lib_conf *libconf)
1083{
1084 u32 reg;
1085
1086 rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1087 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1088 libconf->conf->short_frame_max_tx_count);
1089 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1090 libconf->conf->long_frame_max_tx_count);
1091 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1092 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1093 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1094 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1095 rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
1096}
1097
1098static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
1099 struct rt2x00lib_conf *libconf)
1100{
1101 enum dev_state state =
1102 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1103 STATE_SLEEP : STATE_AWAKE;
1104 u32 reg;
1105
1106 if (state == STATE_SLEEP) {
1107 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1108
1109 rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1110 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1111 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1112 libconf->conf->listen_interval - 1);
1113 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1114 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1115
1116 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1117 } else {
1118 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1119
1120 rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1121 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1122 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1123 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1124 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1125 }
1126}
1127
1128static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1129 struct rt2x00lib_conf *libconf,
1130 const unsigned int flags)
1131{
1132 /* Always recalculate LNA gain before changing configuration */
1133 rt2800pci_config_lna_gain(rt2x00dev, libconf);
1134
1135 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1136 rt2800pci_config_channel(rt2x00dev, libconf->conf,
1137 &libconf->rf, &libconf->channel);
1138 if (flags & IEEE80211_CONF_CHANGE_POWER)
1139 rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1140 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1141 rt2800pci_config_retry_limit(rt2x00dev, libconf);
1142 if (flags & IEEE80211_CONF_CHANGE_PS)
1143 rt2800pci_config_ps(rt2x00dev, libconf);
1144}
1145
1146/*
1147 * Link tuning
1148 */
1149static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1150 struct link_qual *qual)
1151{
1152 u32 reg;
1153
1154 /*
1155 * Update FCS error count from register.
1156 */
1157 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1158 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1159}
1160
1161static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1162{
1163 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1164 return 0x2e + rt2x00dev->lna_gain;
1165
1166 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1167 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1168 else
1169 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1170}
1171
1172static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1173 struct link_qual *qual, u8 vgc_level)
1174{
1175 if (qual->vgc_level != vgc_level) {
1176 rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
1177 qual->vgc_level = vgc_level;
1178 qual->vgc_level_reg = vgc_level;
1179 }
1180}
1181
1182static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1183 struct link_qual *qual)
1184{
1185 rt2800pci_set_vgc(rt2x00dev, qual,
1186 rt2800pci_get_default_vgc(rt2x00dev));
1187}
1188
1189static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1190 struct link_qual *qual, const u32 count)
1191{
1192 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1193 return;
1194
1195 /*
1196 * When RSSI is better then -80 increase VGC level with 0x10
1197 */
1198 rt2800pci_set_vgc(rt2x00dev, qual,
1199 rt2800pci_get_default_vgc(rt2x00dev) +
1200 ((qual->rssi > -80) * 0x10));
1201}
1202
1203/* 190/*
1204 * Firmware functions 191 * Firmware functions
1205 */ 192 */
@@ -1257,7 +244,7 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1257 * Wait for stable hardware. 244 * Wait for stable hardware.
1258 */ 245 */
1259 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1260 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 247 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1261 if (reg && reg != ~0) 248 if (reg && reg != ~0)
1262 break; 249 break;
1263 msleep(1); 250 msleep(1);
@@ -1268,42 +255,42 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1268 return -EBUSY; 255 return -EBUSY;
1269 } 256 }
1270 257
1271 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 258 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1272 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 259 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1273 260
1274 /* 261 /*
1275 * Disable DMA, will be reenabled later when enabling 262 * Disable DMA, will be reenabled later when enabling
1276 * the radio. 263 * the radio.
1277 */ 264 */
1278 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 265 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1279 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 266 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 267 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 268 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1282 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 269 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 270 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1284 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 271 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1285 272
1286 /* 273 /*
1287 * enable Host program ram write selection 274 * enable Host program ram write selection
1288 */ 275 */
1289 reg = 0; 276 reg = 0;
1290 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); 277 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1291 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg); 278 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1292 279
1293 /* 280 /*
1294 * Write firmware to device. 281 * Write firmware to device.
1295 */ 282 */
1296 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 283 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1297 data, len); 284 data, len);
1298 285
1299 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000); 286 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1300 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001); 287 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1301 288
1302 /* 289 /*
1303 * Wait for device to stabilize. 290 * Wait for device to stabilize.
1304 */ 291 */
1305 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 292 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1306 rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 293 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1307 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 294 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1308 break; 295 break;
1309 msleep(1); 296 msleep(1);
@@ -1322,8 +309,8 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1322 /* 309 /*
1323 * Initialize BBP R/W access agent 310 * Initialize BBP R/W access agent
1324 */ 311 */
1325 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 312 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1326 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 313 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1327 314
1328 return 0; 315 return 0;
1329} 316}
@@ -1373,7 +360,7 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1373 struct queue_entry_priv_pci *entry_priv; 360 struct queue_entry_priv_pci *entry_priv;
1374 u32 reg; 361 u32 reg;
1375 362
1376 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 363 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1377 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 364 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1378 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 365 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1379 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 366 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -1381,539 +368,54 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1381 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 368 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1382 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 369 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1383 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 370 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1384 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 371 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1385 372
1386 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 373 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1387 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 374 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1388 375
1389 /* 376 /*
1390 * Initialize registers. 377 * Initialize registers.
1391 */ 378 */
1392 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 379 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1393 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma); 380 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1394 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit); 381 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1395 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0); 382 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1396 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0); 383 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1397 384
1398 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 385 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1399 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma); 386 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1400 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit); 387 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1401 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0); 388 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1402 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0); 389 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1403 390
1404 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; 391 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1405 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma); 392 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1406 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit); 393 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1407 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0); 394 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1408 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0); 395 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1409 396
1410 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; 397 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1411 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma); 398 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1412 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit); 399 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1413 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0); 400 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1414 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0); 401 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1415 402
1416 entry_priv = rt2x00dev->rx->entries[0].priv_data; 403 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1417 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma); 404 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1418 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit); 405 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1419 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1); 406 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
1420 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0); 407 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
1421 408
1422 /* 409 /*
1423 * Enable global DMA configuration 410 * Enable global DMA configuration
1424 */ 411 */
1425 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 412 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1426 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 413 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1427 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 414 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1428 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 415 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1429 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 416 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1430
1431 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1432
1433 return 0;
1434}
1435
1436static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1437{
1438 u32 reg;
1439 unsigned int i;
1440
1441 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1442
1443 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1444 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1445 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1446 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1447
1448 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1449
1450 rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1451 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1452 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1453 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1454 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1455 rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1456
1457 rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1458 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1459 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1460 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1461 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1462 rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1463
1464 rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1465 rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1466
1467 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1468
1469 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1470 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1471 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1472 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1473 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1474 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1475 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1476 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1477
1478 rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1479 rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1480
1481 rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1482 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1483 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1484 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1485 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1486 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1487 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1488 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1489 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1490 rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1491
1492 rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1493 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1494 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1495 rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1496
1497 rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1498 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1499 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1500 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1501 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1502 else
1503 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1504 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1505 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1506 rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1507
1508 rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1509
1510 rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1511 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1512 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1513 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1514 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1515 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1516 rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1517
1518 rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1519 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1520 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1521 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1522 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1523 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1524 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1525 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1526 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1527 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1528 rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1529
1530 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1531 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1532 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1533 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1534 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1535 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1536 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1537 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1538 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1539 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1540 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1541
1542 rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1543 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1544 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1545 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1546 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1547 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1548 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1549 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1550 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1551 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1552 rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1553
1554 rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1555 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1556 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1557 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1558 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1559 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1560 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1561 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1562 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1563 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1564 rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1565
1566 rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1567 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1568 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1569 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1570 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1571 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1572 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1573 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1574 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1575 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1576 rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1577
1578 rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1579 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1580 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1581 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1582 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1583 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1584 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1585 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1586 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1587 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1588 rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1589
1590 rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1591 rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1592
1593 rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1594 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1595 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1596 IEEE80211_MAX_RTS_THRESHOLD);
1597 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1598 rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1599
1600 rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1601 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1602
1603 /*
1604 * ASIC will keep garbage value after boot, clear encryption keys.
1605 */
1606 for (i = 0; i < 4; i++)
1607 rt2x00pci_register_write(rt2x00dev,
1608 SHARED_KEY_MODE_ENTRY(i), 0);
1609
1610 for (i = 0; i < 256; i++) {
1611 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1612 rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1613 wcid, sizeof(wcid));
1614
1615 rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1616 rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1617 }
1618
1619 /*
1620 * Clear all beacons
1621 * For the Beacon base registers we only need to clear
1622 * the first byte since that byte contains the VALID and OWNER
1623 * bits which (when set to 0) will invalidate the entire beacon.
1624 */
1625 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1626 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1627 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1628 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1629 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1630 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1631 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1632 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1633
1634 rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1635 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1636 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1637 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1638 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1639 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1640 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1641 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1642 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1643 rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1644
1645 rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1646 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1647 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1648 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1649 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1650 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1651 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1652 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1653 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1654 rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1655
1656 rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1657 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1658 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1659 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1660 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1661 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1662 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1663 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1664 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1665 rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1666
1667 rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1668 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1669 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1670 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1671 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1672 rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1673
1674 /*
1675 * We must clear the error counters.
1676 * These registers are cleared on read,
1677 * so we may pass a useless variable to store the value.
1678 */
1679 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1680 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1681 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1682 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1683 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1684 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1685
1686 return 0;
1687}
1688
1689static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1690{
1691 unsigned int i;
1692 u32 reg;
1693
1694 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1695 rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1696 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1697 return 0;
1698
1699 udelay(REGISTER_BUSY_DELAY);
1700 }
1701
1702 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1703 return -EACCES;
1704}
1705
1706static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1707{
1708 unsigned int i;
1709 u8 value;
1710
1711 /*
1712 * BBP was enabled after firmware was loaded,
1713 * but we need to reactivate it now.
1714 */
1715 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1716 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1717 msleep(1);
1718
1719 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1720 rt2800pci_bbp_read(rt2x00dev, 0, &value);
1721 if ((value != 0xff) && (value != 0x00))
1722 return 0;
1723 udelay(REGISTER_BUSY_DELAY);
1724 }
1725
1726 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1727 return -EACCES;
1728}
1729
1730static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1731{
1732 unsigned int i;
1733 u16 eeprom;
1734 u8 reg_id;
1735 u8 value;
1736
1737 if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1738 rt2800pci_wait_bbp_ready(rt2x00dev)))
1739 return -EACCES;
1740
1741 rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1742 rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1743 rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1744 rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1745 rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1746 rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1747 rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1748 rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1749 rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1750 rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1751 rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1752 rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1753 rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1754 rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1755
1756 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1757 rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1758 rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1759 }
1760
1761 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1762 rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1763
1764 if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1765 rt2800pci_bbp_write(rt2x00dev, 31, 0x08);
1766 rt2800pci_bbp_write(rt2x00dev, 78, 0x0e);
1767 rt2800pci_bbp_write(rt2x00dev, 80, 0x08);
1768 }
1769
1770 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1771 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1772
1773 if (eeprom != 0xffff && eeprom != 0x0000) {
1774 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1775 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1776 rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1777 }
1778 }
1779 417
1780 return 0; 418 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1781}
1782
1783static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1784 bool bw40, u8 rfcsr24, u8 filter_target)
1785{
1786 unsigned int i;
1787 u8 bbp;
1788 u8 rfcsr;
1789 u8 passband;
1790 u8 stopband;
1791 u8 overtuned = 0;
1792
1793 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1794
1795 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1796 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1797 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1798
1799 rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1800 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1801 rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1802
1803 /*
1804 * Set power & frequency of passband test tone
1805 */
1806 rt2800pci_bbp_write(rt2x00dev, 24, 0);
1807
1808 for (i = 0; i < 100; i++) {
1809 rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1810 msleep(1);
1811
1812 rt2800pci_bbp_read(rt2x00dev, 55, &passband);
1813 if (passband)
1814 break;
1815 }
1816
1817 /*
1818 * Set power & frequency of stopband test tone
1819 */
1820 rt2800pci_bbp_write(rt2x00dev, 24, 0x06);
1821
1822 for (i = 0; i < 100; i++) {
1823 rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1824 msleep(1);
1825
1826 rt2800pci_bbp_read(rt2x00dev, 55, &stopband);
1827
1828 if ((passband - stopband) <= filter_target) {
1829 rfcsr24++;
1830 overtuned += ((passband - stopband) == filter_target);
1831 } else
1832 break;
1833
1834 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1835 }
1836
1837 rfcsr24 -= !!overtuned;
1838
1839 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1840 return rfcsr24;
1841}
1842
1843static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1844{
1845 u8 rfcsr;
1846 u8 bbp;
1847
1848 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1849 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1850 !rt2x00_rf(&rt2x00dev->chip, RF3022))
1851 return 0;
1852
1853 /*
1854 * Init RF calibration.
1855 */
1856 rt2800pci_rfcsr_read(rt2x00dev, 30, &rfcsr);
1857 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1858 rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1859 msleep(1);
1860 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1861 rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1862
1863 rt2800pci_rfcsr_write(rt2x00dev, 0, 0x50);
1864 rt2800pci_rfcsr_write(rt2x00dev, 1, 0x01);
1865 rt2800pci_rfcsr_write(rt2x00dev, 2, 0xf7);
1866 rt2800pci_rfcsr_write(rt2x00dev, 3, 0x75);
1867 rt2800pci_rfcsr_write(rt2x00dev, 4, 0x40);
1868 rt2800pci_rfcsr_write(rt2x00dev, 5, 0x03);
1869 rt2800pci_rfcsr_write(rt2x00dev, 6, 0x02);
1870 rt2800pci_rfcsr_write(rt2x00dev, 7, 0x50);
1871 rt2800pci_rfcsr_write(rt2x00dev, 8, 0x39);
1872 rt2800pci_rfcsr_write(rt2x00dev, 9, 0x0f);
1873 rt2800pci_rfcsr_write(rt2x00dev, 10, 0x60);
1874 rt2800pci_rfcsr_write(rt2x00dev, 11, 0x21);
1875 rt2800pci_rfcsr_write(rt2x00dev, 12, 0x75);
1876 rt2800pci_rfcsr_write(rt2x00dev, 13, 0x75);
1877 rt2800pci_rfcsr_write(rt2x00dev, 14, 0x90);
1878 rt2800pci_rfcsr_write(rt2x00dev, 15, 0x58);
1879 rt2800pci_rfcsr_write(rt2x00dev, 16, 0xb3);
1880 rt2800pci_rfcsr_write(rt2x00dev, 17, 0x92);
1881 rt2800pci_rfcsr_write(rt2x00dev, 18, 0x2c);
1882 rt2800pci_rfcsr_write(rt2x00dev, 19, 0x02);
1883 rt2800pci_rfcsr_write(rt2x00dev, 20, 0xba);
1884 rt2800pci_rfcsr_write(rt2x00dev, 21, 0xdb);
1885 rt2800pci_rfcsr_write(rt2x00dev, 22, 0x00);
1886 rt2800pci_rfcsr_write(rt2x00dev, 23, 0x31);
1887 rt2800pci_rfcsr_write(rt2x00dev, 24, 0x08);
1888 rt2800pci_rfcsr_write(rt2x00dev, 25, 0x01);
1889 rt2800pci_rfcsr_write(rt2x00dev, 26, 0x25);
1890 rt2800pci_rfcsr_write(rt2x00dev, 27, 0x23);
1891 rt2800pci_rfcsr_write(rt2x00dev, 28, 0x13);
1892 rt2800pci_rfcsr_write(rt2x00dev, 29, 0x83);
1893
1894 /*
1895 * Set RX Filter calibration for 20MHz and 40MHz
1896 */
1897 rt2x00dev->calibration[0] =
1898 rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1899 rt2x00dev->calibration[1] =
1900 rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1901
1902 /*
1903 * Set back to initial state
1904 */
1905 rt2800pci_bbp_write(rt2x00dev, 24, 0);
1906
1907 rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1908 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1909 rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1910
1911 /*
1912 * set BBP back to BW20
1913 */
1914 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1915 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1916 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1917 419
1918 return 0; 420 return 0;
1919} 421}
@@ -1926,11 +428,11 @@ static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1926{ 428{
1927 u32 reg; 429 u32 reg;
1928 430
1929 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 431 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1930 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 432 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1931 (state == STATE_RADIO_RX_ON) || 433 (state == STATE_RADIO_RX_ON) ||
1932 (state == STATE_RADIO_RX_ON_LINK)); 434 (state == STATE_RADIO_RX_ON_LINK));
1933 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 435 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1934} 436}
1935 437
1936static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 438static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
@@ -1944,11 +446,11 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1944 * should clear the register to assure a clean state. 446 * should clear the register to assure a clean state.
1945 */ 447 */
1946 if (state == STATE_RADIO_IRQ_ON) { 448 if (state == STATE_RADIO_IRQ_ON) {
1947 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 449 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1948 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 450 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1949 } 451 }
1950 452
1951 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 453 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1952 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask); 454 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1953 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask); 455 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1954 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask); 456 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
@@ -1967,7 +469,7 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1967 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask); 469 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1968 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask); 470 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1969 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask); 471 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1970 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 472 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
1971} 473}
1972 474
1973static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 475static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
@@ -1976,7 +478,7 @@ static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1976 u32 reg; 478 u32 reg;
1977 479
1978 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 480 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1979 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 481 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1980 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 482 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1981 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 483 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1982 return 0; 484 return 0;
@@ -1998,50 +500,50 @@ static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1998 */ 500 */
1999 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) || 501 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2000 rt2800pci_init_queues(rt2x00dev) || 502 rt2800pci_init_queues(rt2x00dev) ||
2001 rt2800pci_init_registers(rt2x00dev) || 503 rt2800_init_registers(rt2x00dev) ||
2002 rt2800pci_wait_wpdma_ready(rt2x00dev) || 504 rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2003 rt2800pci_init_bbp(rt2x00dev) || 505 rt2800_init_bbp(rt2x00dev) ||
2004 rt2800pci_init_rfcsr(rt2x00dev))) 506 rt2800_init_rfcsr(rt2x00dev)))
2005 return -EIO; 507 return -EIO;
2006 508
2007 /* 509 /*
2008 * Send signal to firmware during boot time. 510 * Send signal to firmware during boot time.
2009 */ 511 */
2010 rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0); 512 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
2011 513
2012 /* 514 /*
2013 * Enable RX. 515 * Enable RX.
2014 */ 516 */
2015 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 517 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2016 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 518 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2017 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0); 519 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2018 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 520 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2019 521
2020 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 522 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2021 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 523 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2022 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 524 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2023 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); 525 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2024 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 526 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2025 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 527 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2026 528
2027 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 529 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2028 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 530 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2029 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1); 531 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2030 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 532 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2031 533
2032 /* 534 /*
2033 * Initialize LED control 535 * Initialize LED control
2034 */ 536 */
2035 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word); 537 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2036 rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff, 538 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2037 word & 0xff, (word >> 8) & 0xff); 539 word & 0xff, (word >> 8) & 0xff);
2038 540
2039 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word); 541 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2040 rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff, 542 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2041 word & 0xff, (word >> 8) & 0xff); 543 word & 0xff, (word >> 8) & 0xff);
2042 544
2043 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word); 545 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2044 rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff, 546 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2045 word & 0xff, (word >> 8) & 0xff); 547 word & 0xff, (word >> 8) & 0xff);
2046 548
2047 return 0; 549 return 0;
@@ -2051,21 +553,21 @@ static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2051{ 553{
2052 u32 reg; 554 u32 reg;
2053 555
2054 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 556 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2055 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 557 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2056 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 558 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2057 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 559 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2058 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 560 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2059 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 561 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2060 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 562 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2061 563
2062 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 564 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
2063 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0); 565 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2064 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0); 566 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2065 567
2066 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280); 568 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
2067 569
2068 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 570 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2069 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 571 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
2070 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 572 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
2071 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 573 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -2073,10 +575,10 @@ static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2073 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 575 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
2074 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 576 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
2075 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 577 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
2076 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 578 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2077 579
2078 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 580 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
2079 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 581 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
2080 582
2081 /* Wait for DMA, ignore error */ 583 /* Wait for DMA, ignore error */
2082 rt2800pci_wait_wpdma_ready(rt2x00dev); 584 rt2800pci_wait_wpdma_ready(rt2x00dev);
@@ -2090,10 +592,10 @@ static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
2090 * if the device is booting and wasn't asleep it will return 592 * if the device is booting and wasn't asleep it will return
2091 * failure when attempting to wakeup. 593 * failure when attempting to wakeup.
2092 */ 594 */
2093 rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2); 595 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
2094 596
2095 if (state == STATE_AWAKE) { 597 if (state == STATE_AWAKE) {
2096 rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0); 598 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
2097 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP); 599 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
2098 } 600 }
2099 601
@@ -2195,7 +697,7 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2195 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size); 697 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2196 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 698 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2197 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 699 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2198 (skbdesc->entry->entry_idx + 1) : 0xff); 700 txdesc->key_idx : 0xff);
2199 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 701 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2200 skb->len - txdesc->l2pad); 702 skb->len - txdesc->l2pad);
2201 rt2x00_set_field32(&word, TXWI_W1_PACKETID, 703 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
@@ -2204,8 +706,8 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2204 706
2205 /* 707 /*
2206 * Always write 0 to IV/EIV fields, hardware will insert the IV 708 * Always write 0 to IV/EIV fields, hardware will insert the IV
2207 * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0. 709 * from the IVEIV register when TXD_W3_WIV is set to 0.
2208 * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data 710 * When TXD_W3_WIV is set to 1 it will use the IV data
2209 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 711 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2210 * crypto entry in the registers should be used to encrypt the frame. 712 * crypto entry in the registers should be used to encrypt the frame.
2211 */ 713 */
@@ -2265,18 +767,18 @@ static void rt2800pci_write_beacon(struct queue_entry *entry)
2265 * Disable beaconing while we are reloading the beacon data, 767 * Disable beaconing while we are reloading the beacon data,
2266 * otherwise we might be sending out invalid data. 768 * otherwise we might be sending out invalid data.
2267 */ 769 */
2268 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 770 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2269 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 771 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2270 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 772 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2271 773
2272 /* 774 /*
2273 * Write entire beacon with descriptor to register. 775 * Write entire beacon with descriptor to register.
2274 */ 776 */
2275 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 777 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2276 rt2x00pci_register_multiwrite(rt2x00dev, 778 rt2800_register_multiwrite(rt2x00dev,
2277 beacon_base, 779 beacon_base,
2278 skbdesc->desc, skbdesc->desc_len); 780 skbdesc->desc, skbdesc->desc_len);
2279 rt2x00pci_register_multiwrite(rt2x00dev, 781 rt2800_register_multiwrite(rt2x00dev,
2280 beacon_base + skbdesc->desc_len, 782 beacon_base + skbdesc->desc_len,
2281 entry->skb->data, entry->skb->len); 783 entry->skb->data, entry->skb->len);
2282 784
@@ -2295,12 +797,12 @@ static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2295 u32 reg; 797 u32 reg;
2296 798
2297 if (queue_idx == QID_BEACON) { 799 if (queue_idx == QID_BEACON) {
2298 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 800 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2299 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) { 801 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2300 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); 802 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2301 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); 803 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2302 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); 804 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2303 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 805 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2304 } 806 }
2305 return; 807 return;
2306 } 808 }
@@ -2316,7 +818,7 @@ static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2316 else 818 else
2317 qidx = queue_idx; 819 qidx = queue_idx;
2318 820
2319 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx); 821 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2320} 822}
2321 823
2322static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev, 824static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
@@ -2325,16 +827,16 @@ static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2325 u32 reg; 827 u32 reg;
2326 828
2327 if (qid == QID_BEACON) { 829 if (qid == QID_BEACON) {
2328 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0); 830 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2329 return; 831 return;
2330 } 832 }
2331 833
2332 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 834 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2333 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE)); 835 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2334 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK)); 836 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2335 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI)); 837 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2336 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO)); 838 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2337 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 839 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2338} 840}
2339 841
2340/* 842/*
@@ -2430,7 +932,7 @@ static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2430 * Set RX IDX in register to inform hardware that we have handled 932 * Set RX IDX in register to inform hardware that we have handled
2431 * this entry and it is available for reuse again. 933 * this entry and it is available for reuse again.
2432 */ 934 */
2433 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx); 935 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
2434 936
2435 /* 937 /*
2436 * Remove TXWI descriptor from start of buffer. 938 * Remove TXWI descriptor from start of buffer.
@@ -2467,7 +969,7 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2467 old_reg = 0; 969 old_reg = 0;
2468 970
2469 while (1) { 971 while (1) {
2470 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg); 972 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2471 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID)) 973 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2472 break; 974 break;
2473 975
@@ -2551,8 +1053,8 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2551 u32 reg; 1053 u32 reg;
2552 1054
2553 /* Read status and ACK all interrupts */ 1055 /* Read status and ACK all interrupts */
2554 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 1056 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2555 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 1057 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2556 1058
2557 if (!reg) 1059 if (!reg)
2558 return IRQ_NONE; 1060 return IRQ_NONE;
@@ -2709,7 +1211,7 @@ static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2709 * Identify RF chipset. 1211 * Identify RF chipset.
2710 */ 1212 */
2711 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1213 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2712 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 1214 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2713 rt2x00_set_chip_rf(rt2x00dev, value, reg); 1215 rt2x00_set_chip_rf(rt2x00dev, value, reg);
2714 1216
2715 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) && 1217 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
@@ -2758,9 +1260,9 @@ static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2758 * Store led settings, for correct led behaviour. 1260 * Store led settings, for correct led behaviour.
2759 */ 1261 */
2760#ifdef CONFIG_RT2X00_LIB_LEDS 1262#ifdef CONFIG_RT2X00_LIB_LEDS
2761 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 1263 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2762 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 1264 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2763 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 1265 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2764 1266
2765 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg); 1267 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2766#endif /* CONFIG_RT2X00_LIB_LEDS */ 1268#endif /* CONFIG_RT2X00_LIB_LEDS */
@@ -2948,10 +1450,25 @@ static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2948 return 0; 1450 return 0;
2949} 1451}
2950 1452
1453static const struct rt2800_ops rt2800pci_rt2800_ops = {
1454 .register_read = rt2x00pci_register_read,
1455 .register_write = rt2x00pci_register_write,
1456 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1457
1458 .register_multiread = rt2x00pci_register_multiread,
1459 .register_multiwrite = rt2x00pci_register_multiwrite,
1460
1461 .regbusy_read = rt2x00pci_regbusy_read,
1462};
1463
2951static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev) 1464static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2952{ 1465{
2953 int retval; 1466 int retval;
2954 1467
1468 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
1469
1470 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1471
2955 /* 1472 /*
2956 * Allocate eeprom data. 1473 * Allocate eeprom data.
2957 */ 1474 */
@@ -2996,161 +1513,6 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2996 return 0; 1513 return 0;
2997} 1514}
2998 1515
2999/*
3000 * IEEE80211 stack callback functions.
3001 */
3002static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
3003 u32 *iv32, u16 *iv16)
3004{
3005 struct rt2x00_dev *rt2x00dev = hw->priv;
3006 struct mac_iveiv_entry iveiv_entry;
3007 u32 offset;
3008
3009 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3010 rt2x00pci_register_multiread(rt2x00dev, offset,
3011 &iveiv_entry, sizeof(iveiv_entry));
3012
3013 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
3014 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
3015}
3016
3017static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3018{
3019 struct rt2x00_dev *rt2x00dev = hw->priv;
3020 u32 reg;
3021 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3022
3023 rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3024 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3025 rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
3026
3027 rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3028 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3029 rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3030
3031 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3032 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3033 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3034
3035 rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3036 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3037 rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3038
3039 rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3040 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3041 rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3042
3043 rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3044 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3045 rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3046
3047 rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3048 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3049 rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3050
3051 return 0;
3052}
3053
3054static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3055 const struct ieee80211_tx_queue_params *params)
3056{
3057 struct rt2x00_dev *rt2x00dev = hw->priv;
3058 struct data_queue *queue;
3059 struct rt2x00_field32 field;
3060 int retval;
3061 u32 reg;
3062 u32 offset;
3063
3064 /*
3065 * First pass the configuration through rt2x00lib, that will
3066 * update the queue settings and validate the input. After that
3067 * we are free to update the registers based on the value
3068 * in the queue parameter.
3069 */
3070 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3071 if (retval)
3072 return retval;
3073
3074 /*
3075 * We only need to perform additional register initialization
3076 * for WMM queues/
3077 */
3078 if (queue_idx >= 4)
3079 return 0;
3080
3081 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3082
3083 /* Update WMM TXOP register */
3084 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3085 field.bit_offset = (queue_idx & 1) * 16;
3086 field.bit_mask = 0xffff << field.bit_offset;
3087
3088 rt2x00pci_register_read(rt2x00dev, offset, &reg);
3089 rt2x00_set_field32(&reg, field, queue->txop);
3090 rt2x00pci_register_write(rt2x00dev, offset, reg);
3091
3092 /* Update WMM registers */
3093 field.bit_offset = queue_idx * 4;
3094 field.bit_mask = 0xf << field.bit_offset;
3095
3096 rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3097 rt2x00_set_field32(&reg, field, queue->aifs);
3098 rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3099
3100 rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3101 rt2x00_set_field32(&reg, field, queue->cw_min);
3102 rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3103
3104 rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3105 rt2x00_set_field32(&reg, field, queue->cw_max);
3106 rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3107
3108 /* Update EDCA registers */
3109 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3110
3111 rt2x00pci_register_read(rt2x00dev, offset, &reg);
3112 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3113 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3114 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3115 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3116 rt2x00pci_register_write(rt2x00dev, offset, reg);
3117
3118 return 0;
3119}
3120
3121static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
3122{
3123 struct rt2x00_dev *rt2x00dev = hw->priv;
3124 u64 tsf;
3125 u32 reg;
3126
3127 rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3128 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3129 rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3130 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3131
3132 return tsf;
3133}
3134
3135static const struct ieee80211_ops rt2800pci_mac80211_ops = {
3136 .tx = rt2x00mac_tx,
3137 .start = rt2x00mac_start,
3138 .stop = rt2x00mac_stop,
3139 .add_interface = rt2x00mac_add_interface,
3140 .remove_interface = rt2x00mac_remove_interface,
3141 .config = rt2x00mac_config,
3142 .configure_filter = rt2x00mac_configure_filter,
3143 .set_key = rt2x00mac_set_key,
3144 .get_stats = rt2x00mac_get_stats,
3145 .get_tkip_seq = rt2800pci_get_tkip_seq,
3146 .set_rts_threshold = rt2800pci_set_rts_threshold,
3147 .bss_info_changed = rt2x00mac_bss_info_changed,
3148 .conf_tx = rt2800pci_conf_tx,
3149 .get_tx_stats = rt2x00mac_get_tx_stats,
3150 .get_tsf = rt2800pci_get_tsf,
3151 .rfkill_poll = rt2x00mac_rfkill_poll,
3152};
3153
3154static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = { 1516static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3155 .irq_handler = rt2800pci_interrupt, 1517 .irq_handler = rt2800pci_interrupt,
3156 .probe_hw = rt2800pci_probe_hw, 1518 .probe_hw = rt2800pci_probe_hw,
@@ -3162,23 +1524,23 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3162 .get_entry_state = rt2800pci_get_entry_state, 1524 .get_entry_state = rt2800pci_get_entry_state,
3163 .clear_entry = rt2800pci_clear_entry, 1525 .clear_entry = rt2800pci_clear_entry,
3164 .set_device_state = rt2800pci_set_device_state, 1526 .set_device_state = rt2800pci_set_device_state,
3165 .rfkill_poll = rt2800pci_rfkill_poll, 1527 .rfkill_poll = rt2800_rfkill_poll,
3166 .link_stats = rt2800pci_link_stats, 1528 .link_stats = rt2800_link_stats,
3167 .reset_tuner = rt2800pci_reset_tuner, 1529 .reset_tuner = rt2800_reset_tuner,
3168 .link_tuner = rt2800pci_link_tuner, 1530 .link_tuner = rt2800_link_tuner,
3169 .write_tx_desc = rt2800pci_write_tx_desc, 1531 .write_tx_desc = rt2800pci_write_tx_desc,
3170 .write_tx_data = rt2x00pci_write_tx_data, 1532 .write_tx_data = rt2x00pci_write_tx_data,
3171 .write_beacon = rt2800pci_write_beacon, 1533 .write_beacon = rt2800pci_write_beacon,
3172 .kick_tx_queue = rt2800pci_kick_tx_queue, 1534 .kick_tx_queue = rt2800pci_kick_tx_queue,
3173 .kill_tx_queue = rt2800pci_kill_tx_queue, 1535 .kill_tx_queue = rt2800pci_kill_tx_queue,
3174 .fill_rxdone = rt2800pci_fill_rxdone, 1536 .fill_rxdone = rt2800pci_fill_rxdone,
3175 .config_shared_key = rt2800pci_config_shared_key, 1537 .config_shared_key = rt2800_config_shared_key,
3176 .config_pairwise_key = rt2800pci_config_pairwise_key, 1538 .config_pairwise_key = rt2800_config_pairwise_key,
3177 .config_filter = rt2800pci_config_filter, 1539 .config_filter = rt2800_config_filter,
3178 .config_intf = rt2800pci_config_intf, 1540 .config_intf = rt2800_config_intf,
3179 .config_erp = rt2800pci_config_erp, 1541 .config_erp = rt2800_config_erp,
3180 .config_ant = rt2800pci_config_ant, 1542 .config_ant = rt2800_config_ant,
3181 .config = rt2800pci_config, 1543 .config = rt2800_config,
3182}; 1544};
3183 1545
3184static const struct data_queue_desc rt2800pci_queue_rx = { 1546static const struct data_queue_desc rt2800pci_queue_rx = {
@@ -3213,9 +1575,9 @@ static const struct rt2x00_ops rt2800pci_ops = {
3213 .tx = &rt2800pci_queue_tx, 1575 .tx = &rt2800pci_queue_tx,
3214 .bcn = &rt2800pci_queue_bcn, 1576 .bcn = &rt2800pci_queue_bcn,
3215 .lib = &rt2800pci_rt2x00_ops, 1577 .lib = &rt2800pci_rt2x00_ops,
3216 .hw = &rt2800pci_mac80211_ops, 1578 .hw = &rt2800_mac80211_ops,
3217#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1579#ifdef CONFIG_RT2X00_LIB_DEBUGFS
3218 .debugfs = &rt2800pci_rt2x00debug, 1580 .debugfs = &rt2800_rt2x00debug,
3219#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1581#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3220}; 1582};
3221 1583
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.h b/drivers/net/wireless/rt2x00/rt2800pci.h
index 856908815221..1dbf13270cda 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.h
+++ b/drivers/net/wireless/rt2x00/rt2800pci.h
@@ -28,61 +28,6 @@
28#define RT2800PCI_H 28#define RT2800PCI_H
29 29
30/* 30/*
31 * RF chip defines.
32 *
33 * RF2820 2.4G 2T3R
34 * RF2850 2.4G/5G 2T3R
35 * RF2720 2.4G 1T2R
36 * RF2750 2.4G/5G 1T2R
37 * RF3020 2.4G 1T1R
38 * RF2020 2.4G B/G
39 * RF3021 2.4G 1T2R
40 * RF3022 2.4G 2T2R
41 * RF3052 2.4G 2T2R
42 */
43#define RF2820 0x0001
44#define RF2850 0x0002
45#define RF2720 0x0003
46#define RF2750 0x0004
47#define RF3020 0x0005
48#define RF2020 0x0006
49#define RF3021 0x0007
50#define RF3022 0x0008
51#define RF3052 0x0009
52
53/*
54 * RT2860 version
55 */
56#define RT2860C_VERSION 0x28600100
57#define RT2860D_VERSION 0x28600101
58#define RT2880E_VERSION 0x28720200
59#define RT2883_VERSION 0x28830300
60#define RT3070_VERSION 0x30700200
61
62/*
63 * Signal information.
64 * Default offset is required for RSSI <-> dBm conversion.
65 */
66#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
67
68/*
69 * Register layout information.
70 */
71#define CSR_REG_BASE 0x1000
72#define CSR_REG_SIZE 0x0800
73#define EEPROM_BASE 0x0000
74#define EEPROM_SIZE 0x0110
75#define BBP_BASE 0x0000
76#define BBP_SIZE 0x0080
77#define RF_BASE 0x0004
78#define RF_SIZE 0x0010
79
80/*
81 * Number of TX queues.
82 */
83#define NUM_TX_QUEUES 4
84
85/*
86 * PCI registers. 31 * PCI registers.
87 */ 32 */
88 33
@@ -102,215 +47,6 @@
102#define E2PROM_CSR_RELOAD FIELD32(0x00000080) 47#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
103 48
104/* 49/*
105 * INT_SOURCE_CSR: Interrupt source register.
106 * Write one to clear corresponding bit.
107 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
108 */
109#define INT_SOURCE_CSR 0x0200
110#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
111#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
112#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
113#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
114#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
115#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
116#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
117#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
118#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
119#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
120#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
121#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
122#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
123#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
124#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
125#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
126#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
127#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
128
129/*
130 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
131 */
132#define INT_MASK_CSR 0x0204
133#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
134#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
135#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
136#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
137#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
138#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
139#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
140#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
141#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
142#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
143#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
144#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
145#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
146#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
147#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
148#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
149#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
150#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
151
152/*
153 * WPDMA_GLO_CFG
154 */
155#define WPDMA_GLO_CFG 0x0208
156#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
157#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
158#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
159#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
160#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
161#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
162#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
163#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
164#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
165
166/*
167 * WPDMA_RST_IDX
168 */
169#define WPDMA_RST_IDX 0x020c
170#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
171#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
172#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
173#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
174#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
175#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
176#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
177
178/*
179 * DELAY_INT_CFG
180 */
181#define DELAY_INT_CFG 0x0210
182#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
183#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
184#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
185#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
186#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
187#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
188
189/*
190 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
191 * AIFSN0: AC_BE
192 * AIFSN1: AC_BK
193 * AIFSN1: AC_VI
194 * AIFSN1: AC_VO
195 */
196#define WMM_AIFSN_CFG 0x0214
197#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
198#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
199#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
200#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
201
202/*
203 * WMM_CWMIN_CSR: CWmin for each EDCA AC
204 * CWMIN0: AC_BE
205 * CWMIN1: AC_BK
206 * CWMIN1: AC_VI
207 * CWMIN1: AC_VO
208 */
209#define WMM_CWMIN_CFG 0x0218
210#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
211#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
212#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
213#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
214
215/*
216 * WMM_CWMAX_CSR: CWmax for each EDCA AC
217 * CWMAX0: AC_BE
218 * CWMAX1: AC_BK
219 * CWMAX1: AC_VI
220 * CWMAX1: AC_VO
221 */
222#define WMM_CWMAX_CFG 0x021c
223#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
224#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
225#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
226#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
227
228/*
229 * AC_TXOP0: AC_BK/AC_BE TXOP register
230 * AC0TXOP: AC_BK in unit of 32us
231 * AC1TXOP: AC_BE in unit of 32us
232 */
233#define WMM_TXOP0_CFG 0x0220
234#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
235#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
236
237/*
238 * AC_TXOP1: AC_VO/AC_VI TXOP register
239 * AC2TXOP: AC_VI in unit of 32us
240 * AC3TXOP: AC_VO in unit of 32us
241 */
242#define WMM_TXOP1_CFG 0x0224
243#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
244#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
245
246/*
247 * GPIO_CTRL_CFG:
248 */
249#define GPIO_CTRL_CFG 0x0228
250#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
251#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
252#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
253#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
254#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
255#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
256#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
257#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
258#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
259
260/*
261 * MCU_CMD_CFG
262 */
263#define MCU_CMD_CFG 0x022c
264
265/*
266 * AC_BK register offsets
267 */
268#define TX_BASE_PTR0 0x0230
269#define TX_MAX_CNT0 0x0234
270#define TX_CTX_IDX0 0x0238
271#define TX_DTX_IDX0 0x023c
272
273/*
274 * AC_BE register offsets
275 */
276#define TX_BASE_PTR1 0x0240
277#define TX_MAX_CNT1 0x0244
278#define TX_CTX_IDX1 0x0248
279#define TX_DTX_IDX1 0x024c
280
281/*
282 * AC_VI register offsets
283 */
284#define TX_BASE_PTR2 0x0250
285#define TX_MAX_CNT2 0x0254
286#define TX_CTX_IDX2 0x0258
287#define TX_DTX_IDX2 0x025c
288
289/*
290 * AC_VO register offsets
291 */
292#define TX_BASE_PTR3 0x0260
293#define TX_MAX_CNT3 0x0264
294#define TX_CTX_IDX3 0x0268
295#define TX_DTX_IDX3 0x026c
296
297/*
298 * HCCA register offsets
299 */
300#define TX_BASE_PTR4 0x0270
301#define TX_MAX_CNT4 0x0274
302#define TX_CTX_IDX4 0x0278
303#define TX_DTX_IDX4 0x027c
304
305/*
306 * MGMT register offsets
307 */
308#define TX_BASE_PTR5 0x0280
309#define TX_MAX_CNT5 0x0284
310#define TX_CTX_IDX5 0x0288
311#define TX_DTX_IDX5 0x028c
312
313/*
314 * Queue register offset macros 50 * Queue register offset macros
315 */ 51 */
316#define TX_QUEUE_REG_OFFSET 0x10 52#define TX_QUEUE_REG_OFFSET 0x10
@@ -320,72 +56,6 @@
320#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET) 56#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
321 57
322/* 58/*
323 * RX register offsets
324 */
325#define RX_BASE_PTR 0x0290
326#define RX_MAX_CNT 0x0294
327#define RX_CRX_IDX 0x0298
328#define RX_DRX_IDX 0x029c
329
330/*
331 * PBF_SYS_CTRL
332 * HOST_RAM_WRITE: enable Host program ram write selection
333 */
334#define PBF_SYS_CTRL 0x0400
335#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
336#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
337
338/*
339 * HOST-MCU shared memory
340 */
341#define HOST_CMD_CSR 0x0404
342#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
343
344/*
345 * PBF registers
346 * Most are for debug. Driver doesn't touch PBF register.
347 */
348#define PBF_CFG 0x0408
349#define PBF_MAX_PCNT 0x040c
350#define PBF_CTRL 0x0410
351#define PBF_INT_STA 0x0414
352#define PBF_INT_ENA 0x0418
353
354/*
355 * BCN_OFFSET0:
356 */
357#define BCN_OFFSET0 0x042c
358#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
359#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
360#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
361#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
362
363/*
364 * BCN_OFFSET1:
365 */
366#define BCN_OFFSET1 0x0430
367#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
368#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
369#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
370#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
371
372/*
373 * PBF registers
374 * Most are for debug. Driver doesn't touch PBF register.
375 */
376#define TXRXQ_PCNT 0x0438
377#define PBF_DBG 0x043c
378
379/*
380 * RF registers
381 */
382#define RF_CSR_CFG 0x0500
383#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
384#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
385#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
386#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
387
388/*
389 * EFUSE_CSR: RT3090 EEPROM 59 * EFUSE_CSR: RT3090 EEPROM
390 */ 60 */
391#define EFUSE_CTRL 0x0580 61#define EFUSE_CTRL 0x0580
@@ -414,1360 +84,16 @@
414#define EFUSE_DATA3 0x059c 84#define EFUSE_DATA3 0x059c
415 85
416/* 86/*
417 * MAC Control/Status Registers(CSR).
418 * Some values are set in TU, whereas 1 TU == 1024 us.
419 */
420
421/*
422 * MAC_CSR0: ASIC revision number.
423 * ASIC_REV: 0
424 * ASIC_VER: 2860
425 */
426#define MAC_CSR0 0x1000
427#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
428#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
429
430/*
431 * MAC_SYS_CTRL:
432 */
433#define MAC_SYS_CTRL 0x1004
434#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
435#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
436#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
437#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
438#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
439#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
440#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
441#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
442
443/*
444 * MAC_ADDR_DW0: STA MAC register 0
445 */
446#define MAC_ADDR_DW0 0x1008
447#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
448#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
449#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
450#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
451
452/*
453 * MAC_ADDR_DW1: STA MAC register 1
454 * UNICAST_TO_ME_MASK:
455 * Used to mask off bits from byte 5 of the MAC address
456 * to determine the UNICAST_TO_ME bit for RX frames.
457 * The full mask is complemented by BSS_ID_MASK:
458 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
459 */
460#define MAC_ADDR_DW1 0x100c
461#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
462#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
463#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
464
465/*
466 * MAC_BSSID_DW0: BSSID register 0
467 */
468#define MAC_BSSID_DW0 0x1010
469#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
470#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
471#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
472#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
473
474/*
475 * MAC_BSSID_DW1: BSSID register 1
476 * BSS_ID_MASK:
477 * 0: 1-BSSID mode (BSS index = 0)
478 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
479 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
480 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
481 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
482 * BSSID. This will make sure that those bits will be ignored
483 * when determining the MY_BSS of RX frames.
484 */
485#define MAC_BSSID_DW1 0x1014
486#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
487#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
488#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
489#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
490
491/*
492 * MAX_LEN_CFG: Maximum frame length register.
493 * MAX_MPDU: rt2860b max 16k bytes
494 * MAX_PSDU: Maximum PSDU length
495 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
496 */
497#define MAX_LEN_CFG 0x1018
498#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
499#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
500#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
501#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
502
503/*
504 * BBP_CSR_CFG: BBP serial control register
505 * VALUE: Register value to program into BBP
506 * REG_NUM: Selected BBP register
507 * READ_CONTROL: 0 write BBP, 1 read BBP
508 * BUSY: ASIC is busy executing BBP commands
509 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
510 * BBP_RW_MODE: 0 serial, 1 paralell
511 */
512#define BBP_CSR_CFG 0x101c
513#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
514#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
515#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
516#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
517#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
518#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
519
520/*
521 * RF_CSR_CFG0: RF control register
522 * REGID_AND_VALUE: Register value to program into RF
523 * BITWIDTH: Selected RF register
524 * STANDBYMODE: 0 high when standby, 1 low when standby
525 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
526 * BUSY: ASIC is busy executing RF commands
527 */
528#define RF_CSR_CFG0 0x1020
529#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
530#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
531#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
532#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
533#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
534#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
535
536/*
537 * RF_CSR_CFG1: RF control register
538 * REGID_AND_VALUE: Register value to program into RF
539 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
540 * 0: 3 system clock cycle (37.5usec)
541 * 1: 5 system clock cycle (62.5usec)
542 */
543#define RF_CSR_CFG1 0x1024
544#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
545#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
546
547/*
548 * RF_CSR_CFG2: RF control register
549 * VALUE: Register value to program into RF
550 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
551 * 0: 3 system clock cycle (37.5usec)
552 * 1: 5 system clock cycle (62.5usec)
553 */
554#define RF_CSR_CFG2 0x1028
555#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
556
557/*
558 * LED_CFG: LED control
559 * color LED's:
560 * 0: off
561 * 1: blinking upon TX2
562 * 2: periodic slow blinking
563 * 3: always on
564 * LED polarity:
565 * 0: active low
566 * 1: active high
567 */
568#define LED_CFG 0x102c
569#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
570#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
571#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
572#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
573#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
574#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
575#define LED_CFG_LED_POLAR FIELD32(0x40000000)
576
577/*
578 * XIFS_TIME_CFG: MAC timing
579 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
580 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
581 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
582 * when MAC doesn't reference BBP signal BBRXEND
583 * EIFS: unit 1us
584 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
585 *
586 */
587#define XIFS_TIME_CFG 0x1100
588#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
589#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
590#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
591#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
592#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
593
594/*
595 * BKOFF_SLOT_CFG:
596 */
597#define BKOFF_SLOT_CFG 0x1104
598#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
599#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
600
601/*
602 * NAV_TIME_CFG:
603 */
604#define NAV_TIME_CFG 0x1108
605#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
606#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
607#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
608#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
609
610/*
611 * CH_TIME_CFG: count as channel busy
612 */
613#define CH_TIME_CFG 0x110c
614
615/*
616 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
617 */
618#define PBF_LIFE_TIMER 0x1110
619
620/*
621 * BCN_TIME_CFG:
622 * BEACON_INTERVAL: in unit of 1/16 TU
623 * TSF_TICKING: Enable TSF auto counting
624 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
625 * BEACON_GEN: Enable beacon generator
626 */
627#define BCN_TIME_CFG 0x1114
628#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
629#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
630#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
631#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
632#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
633#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
634
635/*
636 * TBTT_SYNC_CFG:
637 */
638#define TBTT_SYNC_CFG 0x1118
639
640/*
641 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
642 */
643#define TSF_TIMER_DW0 0x111c
644#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
645
646/*
647 * TSF_TIMER_DW1: Local msb TSF timer, read-only
648 */
649#define TSF_TIMER_DW1 0x1120
650#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
651
652/*
653 * TBTT_TIMER: TImer remains till next TBTT, read-only
654 */
655#define TBTT_TIMER 0x1124
656
657/*
658 * INT_TIMER_CFG:
659 */
660#define INT_TIMER_CFG 0x1128
661
662/*
663 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
664 */
665#define INT_TIMER_EN 0x112c
666
667/*
668 * CH_IDLE_STA: channel idle time
669 */
670#define CH_IDLE_STA 0x1130
671
672/*
673 * CH_BUSY_STA: channel busy time
674 */
675#define CH_BUSY_STA 0x1134
676
677/*
678 * MAC_STATUS_CFG:
679 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
680 * if 1 or higher one of the 2 registers is busy.
681 */
682#define MAC_STATUS_CFG 0x1200
683#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
684
685/*
686 * PWR_PIN_CFG:
687 */
688#define PWR_PIN_CFG 0x1204
689
690/*
691 * AUTOWAKEUP_CFG: Manual power control / status register
692 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
693 * AUTOWAKE: 0:sleep, 1:awake
694 */
695#define AUTOWAKEUP_CFG 0x1208
696#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
697#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
698#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
699
700/*
701 * EDCA_AC0_CFG:
702 */
703#define EDCA_AC0_CFG 0x1300
704#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
705#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
706#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
707#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
708
709/*
710 * EDCA_AC1_CFG:
711 */
712#define EDCA_AC1_CFG 0x1304
713#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
714#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
715#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
716#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
717
718/*
719 * EDCA_AC2_CFG:
720 */
721#define EDCA_AC2_CFG 0x1308
722#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
723#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
724#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
725#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
726
727/*
728 * EDCA_AC3_CFG:
729 */
730#define EDCA_AC3_CFG 0x130c
731#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
732#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
733#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
734#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
735
736/*
737 * EDCA_TID_AC_MAP:
738 */
739#define EDCA_TID_AC_MAP 0x1310
740
741/*
742 * TX_PWR_CFG_0:
743 */
744#define TX_PWR_CFG_0 0x1314
745#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
746#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
747#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
748#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
749#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
750#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
751#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
752#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
753
754/*
755 * TX_PWR_CFG_1:
756 */
757#define TX_PWR_CFG_1 0x1318
758#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
759#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
760#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
761#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
762#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
763#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
764#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
765#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
766
767/*
768 * TX_PWR_CFG_2:
769 */
770#define TX_PWR_CFG_2 0x131c
771#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
772#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
773#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
774#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
775#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
776#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
777#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
778#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
779
780/*
781 * TX_PWR_CFG_3:
782 */
783#define TX_PWR_CFG_3 0x1320
784#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
785#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
786#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
787#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
788#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
789#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
790#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
791#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
792
793/*
794 * TX_PWR_CFG_4:
795 */
796#define TX_PWR_CFG_4 0x1324
797#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
798#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
799#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
800#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
801
802/*
803 * TX_PIN_CFG:
804 */
805#define TX_PIN_CFG 0x1328
806#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
807#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
808#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
809#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
810#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
811#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
812#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
813#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
814#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
815#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
816#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
817#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
818#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
819#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
820#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
821#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
822#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
823#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
824#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
825#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
826
827/*
828 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
829 */
830#define TX_BAND_CFG 0x132c
831#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
832#define TX_BAND_CFG_A FIELD32(0x00000002)
833#define TX_BAND_CFG_BG FIELD32(0x00000004)
834
835/*
836 * TX_SW_CFG0:
837 */
838#define TX_SW_CFG0 0x1330
839
840/*
841 * TX_SW_CFG1:
842 */
843#define TX_SW_CFG1 0x1334
844
845/*
846 * TX_SW_CFG2:
847 */
848#define TX_SW_CFG2 0x1338
849
850/*
851 * TXOP_THRES_CFG:
852 */
853#define TXOP_THRES_CFG 0x133c
854
855/*
856 * TXOP_CTRL_CFG:
857 */
858#define TXOP_CTRL_CFG 0x1340
859
860/*
861 * TX_RTS_CFG:
862 * RTS_THRES: unit:byte
863 * RTS_FBK_EN: enable rts rate fallback
864 */
865#define TX_RTS_CFG 0x1344
866#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
867#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
868#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
869
870/*
871 * TX_TIMEOUT_CFG:
872 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
873 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
874 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
875 * it is recommended that:
876 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
877 */
878#define TX_TIMEOUT_CFG 0x1348
879#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
880#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
881#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
882
883/*
884 * TX_RTY_CFG:
885 * SHORT_RTY_LIMIT: short retry limit
886 * LONG_RTY_LIMIT: long retry limit
887 * LONG_RTY_THRE: Long retry threshoold
888 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
889 * 0:expired by retry limit, 1: expired by mpdu life timer
890 * AGG_RTY_MODE: Aggregate MPDU retry mode
891 * 0:expired by retry limit, 1: expired by mpdu life timer
892 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
893 */
894#define TX_RTY_CFG 0x134c
895#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
896#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
897#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
898#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
899#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
900#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
901
902/*
903 * TX_LINK_CFG:
904 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
905 * MFB_ENABLE: TX apply remote MFB 1:enable
906 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
907 * 0: not apply remote remote unsolicit (MFS=7)
908 * TX_MRQ_EN: MCS request TX enable
909 * TX_RDG_EN: RDG TX enable
910 * TX_CF_ACK_EN: Piggyback CF-ACK enable
911 * REMOTE_MFB: remote MCS feedback
912 * REMOTE_MFS: remote MCS feedback sequence number
913 */
914#define TX_LINK_CFG 0x1350
915#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
916#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
917#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
918#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
919#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
920#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
921#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
922#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
923
924/*
925 * HT_FBK_CFG0:
926 */
927#define HT_FBK_CFG0 0x1354
928#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
929#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
930#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
931#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
932#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
933#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
934#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
935#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
936
937/*
938 * HT_FBK_CFG1:
939 */
940#define HT_FBK_CFG1 0x1358
941#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
942#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
943#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
944#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
945#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
946#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
947#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
948#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
949
950/*
951 * LG_FBK_CFG0:
952 */
953#define LG_FBK_CFG0 0x135c
954#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
955#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
956#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
957#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
958#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
959#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
960#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
961#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
962
963/*
964 * LG_FBK_CFG1:
965 */
966#define LG_FBK_CFG1 0x1360
967#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
968#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
969#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
970#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
971
972/*
973 * CCK_PROT_CFG: CCK Protection
974 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
975 * PROTECT_CTRL: Protection control frame type for CCK TX
976 * 0:none, 1:RTS/CTS, 2:CTS-to-self
977 * PROTECT_NAV: TXOP protection type for CCK TX
978 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
979 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
980 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
981 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
982 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
983 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
984 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
985 * RTS_TH_EN: RTS threshold enable on CCK TX
986 */
987#define CCK_PROT_CFG 0x1364
988#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
989#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
990#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
991#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
992#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
993#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
994#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
995#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
996#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
997#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
998
999/*
1000 * OFDM_PROT_CFG: OFDM Protection
1001 */
1002#define OFDM_PROT_CFG 0x1368
1003#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1004#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1005#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1006#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1007#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1008#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1009#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1010#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1011#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1012#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1013
1014/*
1015 * MM20_PROT_CFG: MM20 Protection
1016 */
1017#define MM20_PROT_CFG 0x136c
1018#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1019#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1020#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1021#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1022#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1023#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1024#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1025#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1026#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1027#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1028
1029/*
1030 * MM40_PROT_CFG: MM40 Protection
1031 */
1032#define MM40_PROT_CFG 0x1370
1033#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1034#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1035#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1036#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1037#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1038#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1039#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1040#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1041#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1042#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1043
1044/*
1045 * GF20_PROT_CFG: GF20 Protection
1046 */
1047#define GF20_PROT_CFG 0x1374
1048#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1049#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1050#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1051#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1052#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1053#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1054#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1055#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1056#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1057#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1058
1059/*
1060 * GF40_PROT_CFG: GF40 Protection
1061 */
1062#define GF40_PROT_CFG 0x1378
1063#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1064#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1065#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1066#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1067#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1068#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1069#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1070#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1071#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1072#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1073
1074/*
1075 * EXP_CTS_TIME:
1076 */
1077#define EXP_CTS_TIME 0x137c
1078
1079/*
1080 * EXP_ACK_TIME:
1081 */
1082#define EXP_ACK_TIME 0x1380
1083
1084/*
1085 * RX_FILTER_CFG: RX configuration register.
1086 */
1087#define RX_FILTER_CFG 0x1400
1088#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1089#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1090#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1091#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1092#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1093#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1094#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1095#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1096#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1097#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1098#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1099#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1100#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1101#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1102#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1103#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1104#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1105
1106/*
1107 * AUTO_RSP_CFG:
1108 * AUTORESPONDER: 0: disable, 1: enable
1109 * BAC_ACK_POLICY: 0:long, 1:short preamble
1110 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1111 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1112 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1113 * DUAL_CTS_EN: Power bit value in control frame
1114 * ACK_CTS_PSM_BIT:Power bit value in control frame
1115 */
1116#define AUTO_RSP_CFG 0x1404
1117#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1118#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1119#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1120#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1121#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1122#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1123#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1124
1125/*
1126 * LEGACY_BASIC_RATE:
1127 */
1128#define LEGACY_BASIC_RATE 0x1408
1129
1130/*
1131 * HT_BASIC_RATE:
1132 */
1133#define HT_BASIC_RATE 0x140c
1134
1135/*
1136 * HT_CTRL_CFG:
1137 */
1138#define HT_CTRL_CFG 0x1410
1139
1140/*
1141 * SIFS_COST_CFG:
1142 */
1143#define SIFS_COST_CFG 0x1414
1144
1145/*
1146 * RX_PARSER_CFG:
1147 * Set NAV for all received frames
1148 */
1149#define RX_PARSER_CFG 0x1418
1150
1151/*
1152 * TX_SEC_CNT0:
1153 */
1154#define TX_SEC_CNT0 0x1500
1155
1156/*
1157 * RX_SEC_CNT0:
1158 */
1159#define RX_SEC_CNT0 0x1504
1160
1161/*
1162 * CCMP_FC_MUTE:
1163 */
1164#define CCMP_FC_MUTE 0x1508
1165
1166/*
1167 * TXOP_HLDR_ADDR0:
1168 */
1169#define TXOP_HLDR_ADDR0 0x1600
1170
1171/*
1172 * TXOP_HLDR_ADDR1:
1173 */
1174#define TXOP_HLDR_ADDR1 0x1604
1175
1176/*
1177 * TXOP_HLDR_ET:
1178 */
1179#define TXOP_HLDR_ET 0x1608
1180
1181/*
1182 * QOS_CFPOLL_RA_DW0:
1183 */
1184#define QOS_CFPOLL_RA_DW0 0x160c
1185
1186/*
1187 * QOS_CFPOLL_RA_DW1:
1188 */
1189#define QOS_CFPOLL_RA_DW1 0x1610
1190
1191/*
1192 * QOS_CFPOLL_QC:
1193 */
1194#define QOS_CFPOLL_QC 0x1614
1195
1196/*
1197 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1198 */
1199#define RX_STA_CNT0 0x1700
1200#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1201#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1202
1203/*
1204 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1205 */
1206#define RX_STA_CNT1 0x1704
1207#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1208#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1209
1210/*
1211 * RX_STA_CNT2:
1212 */
1213#define RX_STA_CNT2 0x1708
1214#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1215#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1216
1217/*
1218 * TX_STA_CNT0: TX Beacon count
1219 */
1220#define TX_STA_CNT0 0x170c
1221#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1222#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1223
1224/*
1225 * TX_STA_CNT1: TX tx count
1226 */
1227#define TX_STA_CNT1 0x1710
1228#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1229#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1230
1231/*
1232 * TX_STA_CNT2: TX tx count
1233 */
1234#define TX_STA_CNT2 0x1714
1235#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1236#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1237
1238/*
1239 * TX_STA_FIFO: TX Result for specific PID status fifo register
1240 */
1241#define TX_STA_FIFO 0x1718
1242#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1243#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1244#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1245#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1246#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1247#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1248#define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1249#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1250
1251/*
1252 * TX_AGG_CNT: Debug counter
1253 */
1254#define TX_AGG_CNT 0x171c
1255#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1256#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1257
1258/*
1259 * TX_AGG_CNT0:
1260 */
1261#define TX_AGG_CNT0 0x1720
1262#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1263#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1264
1265/*
1266 * TX_AGG_CNT1:
1267 */
1268#define TX_AGG_CNT1 0x1724
1269#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1270#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1271
1272/*
1273 * TX_AGG_CNT2:
1274 */
1275#define TX_AGG_CNT2 0x1728
1276#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1277#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1278
1279/*
1280 * TX_AGG_CNT3:
1281 */
1282#define TX_AGG_CNT3 0x172c
1283#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1284#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1285
1286/*
1287 * TX_AGG_CNT4:
1288 */
1289#define TX_AGG_CNT4 0x1730
1290#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1291#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1292
1293/*
1294 * TX_AGG_CNT5:
1295 */
1296#define TX_AGG_CNT5 0x1734
1297#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1298#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1299
1300/*
1301 * TX_AGG_CNT6:
1302 */
1303#define TX_AGG_CNT6 0x1738
1304#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1305#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1306
1307/*
1308 * TX_AGG_CNT7:
1309 */
1310#define TX_AGG_CNT7 0x173c
1311#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1312#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1313
1314/*
1315 * MPDU_DENSITY_CNT:
1316 * TX_ZERO_DEL: TX zero length delimiter count
1317 * RX_ZERO_DEL: RX zero length delimiter count
1318 */
1319#define MPDU_DENSITY_CNT 0x1740
1320#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1321#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1322
1323/*
1324 * Security key table memory.
1325 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1326 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1327 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1328 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1329 * SHARED_KEY_TABLE_BASE: 32 bytes * 32-entry
1330 * SHARED_KEY_MODE_BASE: 4 bits * 32-entry
1331 */
1332#define MAC_WCID_BASE 0x1800
1333#define PAIRWISE_KEY_TABLE_BASE 0x4000
1334#define MAC_IVEIV_TABLE_BASE 0x6000
1335#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1336#define SHARED_KEY_TABLE_BASE 0x6c00
1337#define SHARED_KEY_MODE_BASE 0x7000
1338
1339#define MAC_WCID_ENTRY(__idx) \
1340 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1341#define PAIRWISE_KEY_ENTRY(__idx) \
1342 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1343#define MAC_IVEIV_ENTRY(__idx) \
1344 ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
1345#define MAC_WCID_ATTR_ENTRY(__idx) \
1346 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1347#define SHARED_KEY_ENTRY(__idx) \
1348 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1349#define SHARED_KEY_MODE_ENTRY(__idx) \
1350 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1351
1352struct mac_wcid_entry {
1353 u8 mac[6];
1354 u8 reserved[2];
1355} __attribute__ ((packed));
1356
1357struct hw_key_entry {
1358 u8 key[16];
1359 u8 tx_mic[8];
1360 u8 rx_mic[8];
1361} __attribute__ ((packed));
1362
1363struct mac_iveiv_entry {
1364 u8 iv[8];
1365} __attribute__ ((packed));
1366
1367/*
1368 * MAC_WCID_ATTRIBUTE:
1369 */
1370#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1371#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1372#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1373#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1374
1375/*
1376 * SHARED_KEY_MODE:
1377 */
1378#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1379#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1380#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1381#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1382#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1383#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1384#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1385#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1386
1387/*
1388 * HOST-MCU communication
1389 */
1390
1391/*
1392 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1393 */
1394#define H2M_MAILBOX_CSR 0x7010
1395#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1396#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1397#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1398#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1399
1400/*
1401 * H2M_MAILBOX_CID:
1402 */
1403#define H2M_MAILBOX_CID 0x7014
1404#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1405#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1406#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1407#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1408
1409/*
1410 * H2M_MAILBOX_STATUS:
1411 */
1412#define H2M_MAILBOX_STATUS 0x701c
1413
1414/*
1415 * H2M_INT_SRC:
1416 */
1417#define H2M_INT_SRC 0x7024
1418
1419/*
1420 * H2M_BBP_AGENT:
1421 */
1422#define H2M_BBP_AGENT 0x7028
1423
1424/*
1425 * MCU_LEDCS: LED control for MCU Mailbox.
1426 */
1427#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1428#define MCU_LEDCS_POLARITY FIELD8(0x01)
1429
1430/*
1431 * HW_CS_CTS_BASE:
1432 * Carrier-sense CTS frame base address.
1433 * It's where mac stores carrier-sense frame for carrier-sense function.
1434 */
1435#define HW_CS_CTS_BASE 0x7700
1436
1437/*
1438 * HW_DFS_CTS_BASE:
1439 * FS CTS frame base address. It's where mac stores CTS frame for DFS.
1440 */
1441#define HW_DFS_CTS_BASE 0x7780
1442
1443/*
1444 * TXRX control registers - base address 0x3000
1445 */
1446
1447/*
1448 * TXRX_CSR1:
1449 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1450 */
1451#define TXRX_CSR1 0x77d0
1452
1453/*
1454 * HW_DEBUG_SETTING_BASE:
1455 * since NULL frame won't be that long (256 byte)
1456 * We steal 16 tail bytes to save debugging settings
1457 */
1458#define HW_DEBUG_SETTING_BASE 0x77f0
1459#define HW_DEBUG_SETTING_BASE2 0x7770
1460
1461/*
1462 * HW_BEACON_BASE
1463 * In order to support maximum 8 MBSS and its maximum length
1464 * is 512 bytes for each beacon
1465 * Three section discontinue memory segments will be used.
1466 * 1. The original region for BCN 0~3
1467 * 2. Extract memory from FCE table for BCN 4~5
1468 * 3. Extract memory from Pair-wise key table for BCN 6~7
1469 * It occupied those memory of wcid 238~253 for BCN 6
1470 * and wcid 222~237 for BCN 7
1471 *
1472 * IMPORTANT NOTE: Not sure why legacy driver does this,
1473 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1474 */
1475#define HW_BEACON_BASE0 0x7800
1476#define HW_BEACON_BASE1 0x7a00
1477#define HW_BEACON_BASE2 0x7c00
1478#define HW_BEACON_BASE3 0x7e00
1479#define HW_BEACON_BASE4 0x7200
1480#define HW_BEACON_BASE5 0x7400
1481#define HW_BEACON_BASE6 0x5dc0
1482#define HW_BEACON_BASE7 0x5bc0
1483
1484#define HW_BEACON_OFFSET(__index) \
1485 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1486 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1487 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1488
1489/*
1490 * 8051 firmware image. 87 * 8051 firmware image.
1491 */ 88 */
1492#define FIRMWARE_RT2860 "rt2860.bin" 89#define FIRMWARE_RT2860 "rt2860.bin"
1493#define FIRMWARE_IMAGE_BASE 0x2000 90#define FIRMWARE_IMAGE_BASE 0x2000
1494 91
1495/* 92/*
1496 * BBP registers.
1497 * The wordsize of the BBP is 8 bits.
1498 */
1499
1500/*
1501 * BBP 1: TX Antenna
1502 */
1503#define BBP1_TX_POWER FIELD8(0x07)
1504#define BBP1_TX_ANTENNA FIELD8(0x18)
1505
1506/*
1507 * BBP 3: RX Antenna
1508 */
1509#define BBP3_RX_ANTENNA FIELD8(0x18)
1510#define BBP3_HT40_PLUS FIELD8(0x20)
1511
1512/*
1513 * BBP 4: Bandwidth
1514 */
1515#define BBP4_TX_BF FIELD8(0x01)
1516#define BBP4_BANDWIDTH FIELD8(0x18)
1517
1518/*
1519 * RFCSR registers
1520 * The wordsize of the RFCSR is 8 bits.
1521 */
1522
1523/*
1524 * RFCSR 6:
1525 */
1526#define RFCSR6_R FIELD8(0x03)
1527
1528/*
1529 * RFCSR 7:
1530 */
1531#define RFCSR7_RF_TUNING FIELD8(0x01)
1532
1533/*
1534 * RFCSR 12:
1535 */
1536#define RFCSR12_TX_POWER FIELD8(0x1f)
1537
1538/*
1539 * RFCSR 22:
1540 */
1541#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1542
1543/*
1544 * RFCSR 23:
1545 */
1546#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1547
1548/*
1549 * RFCSR 30:
1550 */
1551#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1552
1553/*
1554 * RF registers
1555 */
1556
1557/*
1558 * RF 2
1559 */
1560#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1561#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1562#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1563
1564/*
1565 * RF 3
1566 */
1567#define RF3_TXPOWER_G FIELD32(0x00003e00)
1568#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1569#define RF3_TXPOWER_A FIELD32(0x00003c00)
1570
1571/*
1572 * RF 4
1573 */
1574#define RF4_TXPOWER_G FIELD32(0x000007c0)
1575#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1576#define RF4_TXPOWER_A FIELD32(0x00000780)
1577#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1578#define RF4_HT40 FIELD32(0x00200000)
1579
1580/*
1581 * EEPROM content.
1582 * The wordsize of the EEPROM is 16 bits.
1583 */
1584
1585/*
1586 * EEPROM Version
1587 */
1588#define EEPROM_VERSION 0x0001
1589#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1590#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1591
1592/*
1593 * HW MAC address.
1594 */
1595#define EEPROM_MAC_ADDR_0 0x0002
1596#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1597#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1598#define EEPROM_MAC_ADDR_1 0x0003
1599#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1600#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1601#define EEPROM_MAC_ADDR_2 0x0004
1602#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1603#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1604
1605/*
1606 * EEPROM ANTENNA config
1607 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1608 * TXPATH: 1: 1T, 2: 2T
1609 */
1610#define EEPROM_ANTENNA 0x001a
1611#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1612#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1613#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1614
1615/*
1616 * EEPROM NIC config
1617 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1618 */
1619#define EEPROM_NIC 0x001b
1620#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1621#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1622#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1623#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1624#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1625#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1626#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1627#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1628#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1629#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1630
1631/*
1632 * EEPROM frequency
1633 */
1634#define EEPROM_FREQ 0x001d
1635#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1636#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1637#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1638
1639/*
1640 * EEPROM LED
1641 * POLARITY_RDY_G: Polarity RDY_G setting.
1642 * POLARITY_RDY_A: Polarity RDY_A setting.
1643 * POLARITY_ACT: Polarity ACT setting.
1644 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1645 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1646 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1647 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1648 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1649 * LED_MODE: Led mode.
1650 */
1651#define EEPROM_LED1 0x001e
1652#define EEPROM_LED2 0x001f
1653#define EEPROM_LED3 0x0020
1654#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1655#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1656#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1657#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1658#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1659#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1660#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1661#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1662#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1663
1664/*
1665 * EEPROM LNA
1666 */
1667#define EEPROM_LNA 0x0022
1668#define EEPROM_LNA_BG FIELD16(0x00ff)
1669#define EEPROM_LNA_A0 FIELD16(0xff00)
1670
1671/*
1672 * EEPROM RSSI BG offset
1673 */
1674#define EEPROM_RSSI_BG 0x0023
1675#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1676#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1677
1678/*
1679 * EEPROM RSSI BG2 offset
1680 */
1681#define EEPROM_RSSI_BG2 0x0024
1682#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1683#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1684
1685/*
1686 * EEPROM RSSI A offset
1687 */
1688#define EEPROM_RSSI_A 0x0025
1689#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1690#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1691
1692/*
1693 * EEPROM RSSI A2 offset
1694 */
1695#define EEPROM_RSSI_A2 0x0026
1696#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1697#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1698
1699/*
1700 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1701 * This is delta in 40MHZ.
1702 * VALUE: Tx Power dalta value (MAX=4)
1703 * TYPE: 1: Plus the delta value, 0: minus the delta value
1704 * TXPOWER: Enable:
1705 */
1706#define EEPROM_TXPOWER_DELTA 0x0028
1707#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1708#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1709#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1710
1711/*
1712 * EEPROM TXPOWER 802.11BG
1713 */
1714#define EEPROM_TXPOWER_BG1 0x0029
1715#define EEPROM_TXPOWER_BG2 0x0030
1716#define EEPROM_TXPOWER_BG_SIZE 7
1717#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1718#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1719
1720/*
1721 * EEPROM TXPOWER 802.11A
1722 */
1723#define EEPROM_TXPOWER_A1 0x003c
1724#define EEPROM_TXPOWER_A2 0x0053
1725#define EEPROM_TXPOWER_A_SIZE 6
1726#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1727#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1728
1729/*
1730 * EEPROM TXpower byrate: 20MHZ power
1731 */
1732#define EEPROM_TXPOWER_BYRATE 0x006f
1733
1734/*
1735 * EEPROM BBP.
1736 */
1737#define EEPROM_BBP_START 0x0078
1738#define EEPROM_BBP_SIZE 16
1739#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1740#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1741
1742/*
1743 * MCU mailbox commands.
1744 */
1745#define MCU_SLEEP 0x30
1746#define MCU_WAKEUP 0x31
1747#define MCU_RADIO_OFF 0x35
1748#define MCU_CURRENT 0x36
1749#define MCU_LED 0x50
1750#define MCU_LED_STRENGTH 0x51
1751#define MCU_LED_1 0x52
1752#define MCU_LED_2 0x53
1753#define MCU_LED_3 0x54
1754#define MCU_RADAR 0x60
1755#define MCU_BOOT_SIGNAL 0x72
1756#define MCU_BBP_SIGNAL 0x80
1757#define MCU_POWER_SAVE 0x83
1758
1759/*
1760 * MCU mailbox tokens
1761 */
1762#define TOKEN_WAKUP 3
1763
1764/*
1765 * DMA descriptor defines. 93 * DMA descriptor defines.
1766 */ 94 */
1767#define TXD_DESC_SIZE ( 4 * sizeof(__le32) ) 95#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
1768#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1769#define RXD_DESC_SIZE ( 4 * sizeof(__le32) ) 96#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
1770#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1771 97
1772/* 98/*
1773 * TX descriptor format for TX, PRIO and Beacon Ring. 99 * TX descriptor format for TX, PRIO and Beacon Ring.
@@ -1806,52 +132,6 @@ struct mac_iveiv_entry {
1806#define TXD_W3_ICO FIELD32(0x80000000) 132#define TXD_W3_ICO FIELD32(0x80000000)
1807 133
1808/* 134/*
1809 * TX WI structure
1810 */
1811
1812/*
1813 * Word0
1814 * FRAG: 1 To inform TKIP engine this is a fragment.
1815 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1816 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1817 * BW: Channel bandwidth 20MHz or 40 MHz
1818 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1819 */
1820#define TXWI_W0_FRAG FIELD32(0x00000001)
1821#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1822#define TXWI_W0_CF_ACK FIELD32(0x00000004)
1823#define TXWI_W0_TS FIELD32(0x00000008)
1824#define TXWI_W0_AMPDU FIELD32(0x00000010)
1825#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1826#define TXWI_W0_TX_OP FIELD32(0x00000300)
1827#define TXWI_W0_MCS FIELD32(0x007f0000)
1828#define TXWI_W0_BW FIELD32(0x00800000)
1829#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1830#define TXWI_W0_STBC FIELD32(0x06000000)
1831#define TXWI_W0_IFS FIELD32(0x08000000)
1832#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1833
1834/*
1835 * Word1
1836 */
1837#define TXWI_W1_ACK FIELD32(0x00000001)
1838#define TXWI_W1_NSEQ FIELD32(0x00000002)
1839#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1840#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1841#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1842#define TXWI_W1_PACKETID FIELD32(0xf0000000)
1843
1844/*
1845 * Word2
1846 */
1847#define TXWI_W2_IV FIELD32(0xffffffff)
1848
1849/*
1850 * Word3
1851 */
1852#define TXWI_W3_EIV FIELD32(0xffffffff)
1853
1854/*
1855 * RX descriptor format for RX Ring. 135 * RX descriptor format for RX Ring.
1856 */ 136 */
1857 137
@@ -1897,64 +177,4 @@ struct mac_iveiv_entry {
1897#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000) 177#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
1898#define RXD_W3_PLCP_RSSI FIELD32(0x00040000) 178#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
1899 179
1900/*
1901 * RX WI structure
1902 */
1903
1904/*
1905 * Word0
1906 */
1907#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1908#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1909#define RXWI_W0_BSSID FIELD32(0x00001c00)
1910#define RXWI_W0_UDF FIELD32(0x0000e000)
1911#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1912#define RXWI_W0_TID FIELD32(0xf0000000)
1913
1914/*
1915 * Word1
1916 */
1917#define RXWI_W1_FRAG FIELD32(0x0000000f)
1918#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1919#define RXWI_W1_MCS FIELD32(0x007f0000)
1920#define RXWI_W1_BW FIELD32(0x00800000)
1921#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1922#define RXWI_W1_STBC FIELD32(0x06000000)
1923#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1924
1925/*
1926 * Word2
1927 */
1928#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1929#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1930#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1931
1932/*
1933 * Word3
1934 */
1935#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1936#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1937
1938/*
1939 * Macros for converting txpower from EEPROM to mac80211 value
1940 * and from mac80211 value to register value.
1941 */
1942#define MIN_G_TXPOWER 0
1943#define MIN_A_TXPOWER -7
1944#define MAX_G_TXPOWER 31
1945#define MAX_A_TXPOWER 15
1946#define DEFAULT_TXPOWER 5
1947
1948#define TXPOWER_G_FROM_DEV(__txpower) \
1949 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1950
1951#define TXPOWER_G_TO_DEV(__txpower) \
1952 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1953
1954#define TXPOWER_A_FROM_DEV(__txpower) \
1955 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1956
1957#define TXPOWER_A_TO_DEV(__txpower) \
1958 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1959
1960#endif /* RT2800PCI_H */ 180#endif /* RT2800PCI_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index 9fe770f7d7bb..ce2e893856c1 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -34,6 +34,8 @@
34 34
35#include "rt2x00.h" 35#include "rt2x00.h"
36#include "rt2x00usb.h" 36#include "rt2x00usb.h"
37#include "rt2800lib.h"
38#include "rt2800.h"
37#include "rt2800usb.h" 39#include "rt2800usb.h"
38 40
39/* 41/*
@@ -44,1027 +46,6 @@ module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 46MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45 47
46/* 48/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
72{
73 u32 reg;
74
75 mutex_lock(&rt2x00dev->csr_mutex);
76
77 /*
78 * Wait until the BBP becomes available, afterwards we
79 * can safely write the new data into the register.
80 */
81 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
82 reg = 0;
83 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
84 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
85 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
86 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
87
88 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
89 }
90
91 mutex_unlock(&rt2x00dev->csr_mutex);
92}
93
94static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95 const unsigned int word, u8 *value)
96{
97 u32 reg;
98
99 mutex_lock(&rt2x00dev->csr_mutex);
100
101 /*
102 * Wait until the BBP becomes available, afterwards we
103 * can safely write the read request into the register.
104 * After the data has been written, we wait until hardware
105 * returns the correct value, if at any time the register
106 * doesn't become available in time, reg will be 0xffffffff
107 * which means we return 0xff to the caller.
108 */
109 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
110 reg = 0;
111 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
112 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
113 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
114
115 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
116
117 WAIT_FOR_BBP(rt2x00dev, &reg);
118 }
119
120 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
121
122 mutex_unlock(&rt2x00dev->csr_mutex);
123}
124
125static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
126 const unsigned int word, const u8 value)
127{
128 u32 reg;
129
130 mutex_lock(&rt2x00dev->csr_mutex);
131
132 /*
133 * Wait until the RFCSR becomes available, afterwards we
134 * can safely write the new data into the register.
135 */
136 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
137 reg = 0;
138 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
139 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
140 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
141 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
142
143 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
144 }
145
146 mutex_unlock(&rt2x00dev->csr_mutex);
147}
148
149static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
150 const unsigned int word, u8 *value)
151{
152 u32 reg;
153
154 mutex_lock(&rt2x00dev->csr_mutex);
155
156 /*
157 * Wait until the RFCSR becomes available, afterwards we
158 * can safely write the read request into the register.
159 * After the data has been written, we wait until hardware
160 * returns the correct value, if at any time the register
161 * doesn't become available in time, reg will be 0xffffffff
162 * which means we return 0xff to the caller.
163 */
164 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
165 reg = 0;
166 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
167 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
168 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
169
170 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
171
172 WAIT_FOR_RFCSR(rt2x00dev, &reg);
173 }
174
175 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
176
177 mutex_unlock(&rt2x00dev->csr_mutex);
178}
179
180static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
181 const unsigned int word, const u32 value)
182{
183 u32 reg;
184
185 mutex_lock(&rt2x00dev->csr_mutex);
186
187 /*
188 * Wait until the RF becomes available, afterwards we
189 * can safely write the new data into the register.
190 */
191 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
192 reg = 0;
193 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
194 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
195 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
196 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
197
198 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
199 rt2x00_rf_write(rt2x00dev, word, value);
200 }
201
202 mutex_unlock(&rt2x00dev->csr_mutex);
203}
204
205static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
206 const u8 command, const u8 token,
207 const u8 arg0, const u8 arg1)
208{
209 u32 reg;
210
211 mutex_lock(&rt2x00dev->csr_mutex);
212
213 /*
214 * Wait until the MCU becomes available, afterwards we
215 * can safely write the new data into the register.
216 */
217 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
218 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
219 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
220 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
221 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
222 rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
223
224 reg = 0;
225 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
226 rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
227 }
228
229 mutex_unlock(&rt2x00dev->csr_mutex);
230}
231
232#ifdef CONFIG_RT2X00_LIB_DEBUGFS
233static const struct rt2x00debug rt2800usb_rt2x00debug = {
234 .owner = THIS_MODULE,
235 .csr = {
236 .read = rt2x00usb_register_read,
237 .write = rt2x00usb_register_write,
238 .flags = RT2X00DEBUGFS_OFFSET,
239 .word_base = CSR_REG_BASE,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
242 },
243 .eeprom = {
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_base = EEPROM_BASE,
247 .word_size = sizeof(u16),
248 .word_count = EEPROM_SIZE / sizeof(u16),
249 },
250 .bbp = {
251 .read = rt2800usb_bbp_read,
252 .write = rt2800usb_bbp_write,
253 .word_base = BBP_BASE,
254 .word_size = sizeof(u8),
255 .word_count = BBP_SIZE / sizeof(u8),
256 },
257 .rf = {
258 .read = rt2x00_rf_read,
259 .write = rt2800usb_rf_write,
260 .word_base = RF_BASE,
261 .word_size = sizeof(u32),
262 .word_count = RF_SIZE / sizeof(u32),
263 },
264};
265#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
268{
269 u32 reg;
270
271 rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
272 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
273}
274
275#ifdef CONFIG_RT2X00_LIB_LEDS
276static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
277 enum led_brightness brightness)
278{
279 struct rt2x00_led *led =
280 container_of(led_cdev, struct rt2x00_led, led_dev);
281 unsigned int enabled = brightness != LED_OFF;
282 unsigned int bg_mode =
283 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
284 unsigned int polarity =
285 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
286 EEPROM_FREQ_LED_POLARITY);
287 unsigned int ledmode =
288 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
289 EEPROM_FREQ_LED_MODE);
290
291 if (led->type == LED_TYPE_RADIO) {
292 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
293 enabled ? 0x20 : 0);
294 } else if (led->type == LED_TYPE_ASSOC) {
295 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
296 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
297 } else if (led->type == LED_TYPE_QUALITY) {
298 /*
299 * The brightness is divided into 6 levels (0 - 5),
300 * The specs tell us the following levels:
301 * 0, 1 ,3, 7, 15, 31
302 * to determine the level in a simple way we can simply
303 * work with bitshifting:
304 * (1 << level) - 1
305 */
306 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
307 (1 << brightness / (LED_FULL / 6)) - 1,
308 polarity);
309 }
310}
311
312static int rt2800usb_blink_set(struct led_classdev *led_cdev,
313 unsigned long *delay_on,
314 unsigned long *delay_off)
315{
316 struct rt2x00_led *led =
317 container_of(led_cdev, struct rt2x00_led, led_dev);
318 u32 reg;
319
320 rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
321 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
322 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
323 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
324 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
325 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
326 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
327 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
328 rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
329
330 return 0;
331}
332
333static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
334 struct rt2x00_led *led,
335 enum led_type type)
336{
337 led->rt2x00dev = rt2x00dev;
338 led->type = type;
339 led->led_dev.brightness_set = rt2800usb_brightness_set;
340 led->led_dev.blink_set = rt2800usb_blink_set;
341 led->flags = LED_INITIALIZED;
342}
343#endif /* CONFIG_RT2X00_LIB_LEDS */
344
345/*
346 * Configuration handlers.
347 */
348static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
349 struct rt2x00lib_crypto *crypto,
350 struct ieee80211_key_conf *key)
351{
352 struct mac_wcid_entry wcid_entry;
353 struct mac_iveiv_entry iveiv_entry;
354 u32 offset;
355 u32 reg;
356
357 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
358
359 rt2x00usb_register_read(rt2x00dev, offset, &reg);
360 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
361 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
362 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
363 (crypto->cmd == SET_KEY) * crypto->cipher);
364 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
365 (crypto->cmd == SET_KEY) * crypto->bssidx);
366 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
367 rt2x00usb_register_write(rt2x00dev, offset, reg);
368
369 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
370
371 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
372 if ((crypto->cipher == CIPHER_TKIP) ||
373 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
374 (crypto->cipher == CIPHER_AES))
375 iveiv_entry.iv[3] |= 0x20;
376 iveiv_entry.iv[3] |= key->keyidx << 6;
377 rt2x00usb_register_multiwrite(rt2x00dev, offset,
378 &iveiv_entry, sizeof(iveiv_entry));
379
380 offset = MAC_WCID_ENTRY(key->hw_key_idx);
381
382 memset(&wcid_entry, 0, sizeof(wcid_entry));
383 if (crypto->cmd == SET_KEY)
384 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
385 rt2x00usb_register_multiwrite(rt2x00dev, offset,
386 &wcid_entry, sizeof(wcid_entry));
387}
388
389static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
390 struct rt2x00lib_crypto *crypto,
391 struct ieee80211_key_conf *key)
392{
393 struct hw_key_entry key_entry;
394 struct rt2x00_field32 field;
395 int timeout;
396 u32 offset;
397 u32 reg;
398
399 if (crypto->cmd == SET_KEY) {
400 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
401
402 memcpy(key_entry.key, crypto->key,
403 sizeof(key_entry.key));
404 memcpy(key_entry.tx_mic, crypto->tx_mic,
405 sizeof(key_entry.tx_mic));
406 memcpy(key_entry.rx_mic, crypto->rx_mic,
407 sizeof(key_entry.rx_mic));
408
409 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
410 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
411 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
412 USB_VENDOR_REQUEST_OUT,
413 offset, &key_entry,
414 sizeof(key_entry),
415 timeout);
416 }
417
418 /*
419 * The cipher types are stored over multiple registers
420 * starting with SHARED_KEY_MODE_BASE each word will have
421 * 32 bits and contains the cipher types for 2 bssidx each.
422 * Using the correct defines correctly will cause overhead,
423 * so just calculate the correct offset.
424 */
425 field.bit_offset = 4 * (key->hw_key_idx % 8);
426 field.bit_mask = 0x7 << field.bit_offset;
427
428 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
429
430 rt2x00usb_register_read(rt2x00dev, offset, &reg);
431 rt2x00_set_field32(&reg, field,
432 (crypto->cmd == SET_KEY) * crypto->cipher);
433 rt2x00usb_register_write(rt2x00dev, offset, reg);
434
435 /*
436 * Update WCID information
437 */
438 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
439
440 return 0;
441}
442
443static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
444 struct rt2x00lib_crypto *crypto,
445 struct ieee80211_key_conf *key)
446{
447 struct hw_key_entry key_entry;
448 int timeout;
449 u32 offset;
450
451 if (crypto->cmd == SET_KEY) {
452 /*
453 * 1 pairwise key is possible per AID, this means that the AID
454 * equals our hw_key_idx. Make sure the WCID starts _after_ the
455 * last possible shared key entry.
456 */
457 if (crypto->aid > (256 - 32))
458 return -ENOSPC;
459
460 key->hw_key_idx = 32 + crypto->aid;
461
462 memcpy(key_entry.key, crypto->key,
463 sizeof(key_entry.key));
464 memcpy(key_entry.tx_mic, crypto->tx_mic,
465 sizeof(key_entry.tx_mic));
466 memcpy(key_entry.rx_mic, crypto->rx_mic,
467 sizeof(key_entry.rx_mic));
468
469 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
470 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
471 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
472 USB_VENDOR_REQUEST_OUT,
473 offset, &key_entry,
474 sizeof(key_entry),
475 timeout);
476 }
477
478 /*
479 * Update WCID information
480 */
481 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
482
483 return 0;
484}
485
486static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
487 const unsigned int filter_flags)
488{
489 u32 reg;
490
491 /*
492 * Start configuration steps.
493 * Note that the version error will always be dropped
494 * and broadcast frames will always be accepted since
495 * there is no filter for it at this time.
496 */
497 rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
498 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
499 !(filter_flags & FIF_FCSFAIL));
500 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
501 !(filter_flags & FIF_PLCPFAIL));
502 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
503 !(filter_flags & FIF_PROMISC_IN_BSS));
504 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
505 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
506 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
507 !(filter_flags & FIF_ALLMULTI));
508 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
509 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
510 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
511 !(filter_flags & FIF_CONTROL));
512 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
513 !(filter_flags & FIF_CONTROL));
514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
515 !(filter_flags & FIF_CONTROL));
516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
517 !(filter_flags & FIF_CONTROL));
518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
519 !(filter_flags & FIF_CONTROL));
520 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
521 !(filter_flags & FIF_PSPOLL));
522 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
523 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
524 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
525 !(filter_flags & FIF_CONTROL));
526 rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
527}
528
529static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
530 struct rt2x00_intf *intf,
531 struct rt2x00intf_conf *conf,
532 const unsigned int flags)
533{
534 unsigned int beacon_base;
535 u32 reg;
536
537 if (flags & CONFIG_UPDATE_TYPE) {
538 /*
539 * Clear current synchronisation setup.
540 * For the Beacon base registers we only need to clear
541 * the first byte since that byte contains the VALID and OWNER
542 * bits which (when set to 0) will invalidate the entire beacon.
543 */
544 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
545 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
546
547 /*
548 * Enable synchronisation.
549 */
550 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
551 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
552 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
553 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
554 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
555 }
556
557 if (flags & CONFIG_UPDATE_MAC) {
558 reg = le32_to_cpu(conf->mac[1]);
559 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
560 conf->mac[1] = cpu_to_le32(reg);
561
562 rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
563 conf->mac, sizeof(conf->mac));
564 }
565
566 if (flags & CONFIG_UPDATE_BSSID) {
567 reg = le32_to_cpu(conf->bssid[1]);
568 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
569 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
570 conf->bssid[1] = cpu_to_le32(reg);
571
572 rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
573 conf->bssid, sizeof(conf->bssid));
574 }
575}
576
577static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
578 struct rt2x00lib_erp *erp)
579{
580 u32 reg;
581
582 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
583 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
584 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
585
586 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
587 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
588 !!erp->short_preamble);
589 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
590 !!erp->short_preamble);
591 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
592
593 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
594 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
595 erp->cts_protection ? 2 : 0);
596 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
597
598 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
599 erp->basic_rates);
600 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
601
602 rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
603 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
604 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
605 rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
606
607 rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
608 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
609 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
610 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
611 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
612 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
613 rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
614
615 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
616 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
617 erp->beacon_int * 16);
618 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
619}
620
621static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
622 struct antenna_setup *ant)
623{
624 u8 r1;
625 u8 r3;
626
627 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
628 rt2800usb_bbp_read(rt2x00dev, 3, &r3);
629
630 /*
631 * Configure the TX antenna.
632 */
633 switch ((int)ant->tx) {
634 case 1:
635 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
636 break;
637 case 2:
638 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
639 break;
640 case 3:
641 /* Do nothing */
642 break;
643 }
644
645 /*
646 * Configure the RX antenna.
647 */
648 switch ((int)ant->rx) {
649 case 1:
650 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
651 break;
652 case 2:
653 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
654 break;
655 case 3:
656 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
657 break;
658 }
659
660 rt2800usb_bbp_write(rt2x00dev, 3, r3);
661 rt2800usb_bbp_write(rt2x00dev, 1, r1);
662}
663
664static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
665 struct rt2x00lib_conf *libconf)
666{
667 u16 eeprom;
668 short lna_gain;
669
670 if (libconf->rf.channel <= 14) {
671 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
672 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
673 } else if (libconf->rf.channel <= 64) {
674 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
675 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
676 } else if (libconf->rf.channel <= 128) {
677 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
678 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
679 } else {
680 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
681 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
682 }
683
684 rt2x00dev->lna_gain = lna_gain;
685}
686
687static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
688 struct ieee80211_conf *conf,
689 struct rf_channel *rf,
690 struct channel_info *info)
691{
692 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
693
694 if (rt2x00dev->default_ant.tx == 1)
695 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
696
697 if (rt2x00dev->default_ant.rx == 1) {
698 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
699 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
700 } else if (rt2x00dev->default_ant.rx == 2)
701 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
702
703 if (rf->channel > 14) {
704 /*
705 * When TX power is below 0, we should increase it by 7 to
706 * make it a positive value (Minumum value is -7).
707 * However this means that values between 0 and 7 have
708 * double meaning, and we should set a 7DBm boost flag.
709 */
710 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
711 (info->tx_power1 >= 0));
712
713 if (info->tx_power1 < 0)
714 info->tx_power1 += 7;
715
716 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
717 TXPOWER_A_TO_DEV(info->tx_power1));
718
719 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
720 (info->tx_power2 >= 0));
721
722 if (info->tx_power2 < 0)
723 info->tx_power2 += 7;
724
725 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
726 TXPOWER_A_TO_DEV(info->tx_power2));
727 } else {
728 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
729 TXPOWER_G_TO_DEV(info->tx_power1));
730 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
731 TXPOWER_G_TO_DEV(info->tx_power2));
732 }
733
734 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
735
736 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
737 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
738 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
739 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
740
741 udelay(200);
742
743 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
744 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
745 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
746 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
747
748 udelay(200);
749
750 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
751 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
752 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
753 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
754}
755
756static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
757 struct ieee80211_conf *conf,
758 struct rf_channel *rf,
759 struct channel_info *info)
760{
761 u8 rfcsr;
762
763 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
764 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
765
766 rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
767 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
768 rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
769
770 rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
771 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
772 TXPOWER_G_TO_DEV(info->tx_power1));
773 rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
774
775 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
776 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
777 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
778
779 rt2800usb_rfcsr_write(rt2x00dev, 24,
780 rt2x00dev->calibration[conf_is_ht40(conf)]);
781
782 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
783 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
784 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
785}
786
787static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
788 struct ieee80211_conf *conf,
789 struct rf_channel *rf,
790 struct channel_info *info)
791{
792 u32 reg;
793 unsigned int tx_pin;
794 u8 bbp;
795
796 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
797 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
798 else
799 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
800
801 /*
802 * Change BBP settings
803 */
804 rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
805 rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
806 rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
807 rt2800usb_bbp_write(rt2x00dev, 86, 0);
808
809 if (rf->channel <= 14) {
810 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
811 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
812 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
813 } else {
814 rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
815 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
816 }
817 } else {
818 rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
819
820 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
821 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
822 else
823 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
824 }
825
826 rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
827 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
828 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
829 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
830 rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
831
832 tx_pin = 0;
833
834 /* Turn on unused PA or LNA when not using 1T or 1R */
835 if (rt2x00dev->default_ant.tx != 1) {
836 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
837 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
838 }
839
840 /* Turn on unused PA or LNA when not using 1T or 1R */
841 if (rt2x00dev->default_ant.rx != 1) {
842 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
843 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
844 }
845
846 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
847 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
848 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
849 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
850 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
851 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
852
853 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
854
855 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
856 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
857 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
858
859 rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
860 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
861 rt2800usb_bbp_write(rt2x00dev, 3, bbp);
862
863 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
864 if (conf_is_ht40(conf)) {
865 rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
866 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
867 rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
868 } else {
869 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
870 rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
871 rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
872 }
873 }
874
875 msleep(1);
876}
877
878static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
879 const int txpower)
880{
881 u32 reg;
882 u32 value = TXPOWER_G_TO_DEV(txpower);
883 u8 r1;
884
885 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
886 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
887 rt2800usb_bbp_write(rt2x00dev, 1, r1);
888
889 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
890 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
891 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
892 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
893 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
894 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
895 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
896 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
897 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
898 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
899
900 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
901 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
902 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
903 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
904 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
905 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
906 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
907 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
908 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
909 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
910
911 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
912 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
913 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
914 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
915 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
916 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
917 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
918 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
919 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
920 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
921
922 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
923 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
924 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
925 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
926 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
927 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
928 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
929 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
930 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
931 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
932
933 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
937 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
938 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
939}
940
941static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
942 struct rt2x00lib_conf *libconf)
943{
944 u32 reg;
945
946 rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
947 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
948 libconf->conf->short_frame_max_tx_count);
949 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
950 libconf->conf->long_frame_max_tx_count);
951 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
952 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
953 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
954 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
955 rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
956}
957
958static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
959 struct rt2x00lib_conf *libconf)
960{
961 enum dev_state state =
962 (libconf->conf->flags & IEEE80211_CONF_PS) ?
963 STATE_SLEEP : STATE_AWAKE;
964 u32 reg;
965
966 if (state == STATE_SLEEP) {
967 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
968
969 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
970 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
971 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
972 libconf->conf->listen_interval - 1);
973 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
974 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
975
976 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
977 } else {
978 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
979
980 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
981 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
982 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
983 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
984 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
985 }
986}
987
988static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
989 struct rt2x00lib_conf *libconf,
990 const unsigned int flags)
991{
992 /* Always recalculate LNA gain before changing configuration */
993 rt2800usb_config_lna_gain(rt2x00dev, libconf);
994
995 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
996 rt2800usb_config_channel(rt2x00dev, libconf->conf,
997 &libconf->rf, &libconf->channel);
998 if (flags & IEEE80211_CONF_CHANGE_POWER)
999 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1000 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1001 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1002 if (flags & IEEE80211_CONF_CHANGE_PS)
1003 rt2800usb_config_ps(rt2x00dev, libconf);
1004}
1005
1006/*
1007 * Link tuning
1008 */
1009static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1010 struct link_qual *qual)
1011{
1012 u32 reg;
1013
1014 /*
1015 * Update FCS error count from register.
1016 */
1017 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1018 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1019}
1020
1021static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1022{
1023 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1024 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1025 return 0x1c + (2 * rt2x00dev->lna_gain);
1026 else
1027 return 0x2e + rt2x00dev->lna_gain;
1028 }
1029
1030 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1031 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1032 else
1033 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1034}
1035
1036static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1037 struct link_qual *qual, u8 vgc_level)
1038{
1039 if (qual->vgc_level != vgc_level) {
1040 rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1041 qual->vgc_level = vgc_level;
1042 qual->vgc_level_reg = vgc_level;
1043 }
1044}
1045
1046static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1047 struct link_qual *qual)
1048{
1049 rt2800usb_set_vgc(rt2x00dev, qual,
1050 rt2800usb_get_default_vgc(rt2x00dev));
1051}
1052
1053static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1054 struct link_qual *qual, const u32 count)
1055{
1056 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1057 return;
1058
1059 /*
1060 * When RSSI is better then -80 increase VGC level with 0x10
1061 */
1062 rt2800usb_set_vgc(rt2x00dev, qual,
1063 rt2800usb_get_default_vgc(rt2x00dev) +
1064 ((qual->rssi > -80) * 0x10));
1065}
1066
1067/*
1068 * Firmware functions 49 * Firmware functions
1069 */ 50 */
1070static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) 51static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
@@ -1172,7 +153,7 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1172 * Wait for stable hardware. 153 * Wait for stable hardware.
1173 */ 154 */
1174 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 155 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1175 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg); 156 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1176 if (reg && reg != ~0) 157 if (reg && reg != ~0)
1177 break; 158 break;
1178 msleep(1); 159 msleep(1);
@@ -1192,8 +173,8 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1192 data + offset, length, 173 data + offset, length,
1193 REGISTER_TIMEOUT32(length)); 174 REGISTER_TIMEOUT32(length));
1194 175
1195 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 176 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1196 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 177 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1197 178
1198 /* 179 /*
1199 * Send firmware request to device to load firmware, 180 * Send firmware request to device to load firmware,
@@ -1208,18 +189,18 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1208 } 189 }
1209 190
1210 msleep(10); 191 msleep(10);
1211 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 192 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1212 193
1213 /* 194 /*
1214 * Send signal to firmware during boot time. 195 * Send signal to firmware during boot time.
1215 */ 196 */
1216 rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0); 197 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1217 198
1218 if ((chipset == 0x3070) || 199 if ((chipset == 0x3070) ||
1219 (chipset == 0x3071) || 200 (chipset == 0x3071) ||
1220 (chipset == 0x3572)) { 201 (chipset == 0x3572)) {
1221 udelay(200); 202 udelay(200);
1222 rt2800usb_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 203 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1223 udelay(10); 204 udelay(10);
1224 } 205 }
1225 206
@@ -1227,7 +208,7 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1227 * Wait for device to stabilize. 208 * Wait for device to stabilize.
1228 */ 209 */
1229 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 210 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1230 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 211 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1231 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 212 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1232 break; 213 break;
1233 msleep(1); 214 msleep(1);
@@ -1241,536 +222,14 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1241 /* 222 /*
1242 * Initialize firmware. 223 * Initialize firmware.
1243 */ 224 */
1244 rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 225 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1245 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 226 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1246 msleep(1); 227 msleep(1);
1247 228
1248 return 0; 229 return 0;
1249} 230}
1250 231
1251/* 232/*
1252 * Initialization functions.
1253 */
1254static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1255{
1256 u32 reg;
1257 unsigned int i;
1258
1259 /*
1260 * Wait untill BBP and RF are ready.
1261 */
1262 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1263 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1264 if (reg && reg != ~0)
1265 break;
1266 msleep(1);
1267 }
1268
1269 if (i == REGISTER_BUSY_COUNT) {
1270 ERROR(rt2x00dev, "Unstable hardware.\n");
1271 return -EBUSY;
1272 }
1273
1274 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1275 rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1276
1277 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1278 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1279 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1280 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1281
1282 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1283
1284 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1285 USB_MODE_RESET, REGISTER_TIMEOUT);
1286
1287 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1288
1289 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1290 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1291 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1292 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1293 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1294 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1295
1296 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1297 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1298 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1299 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1300 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1301 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1302
1303 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1304 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1305
1306 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1307
1308 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1309 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1310 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1311 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1312 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1313 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1314 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1315 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1316
1317 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1318 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1319 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1320 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1321 } else {
1322 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1323 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1324 }
1325
1326 rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1327 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1328 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1329 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1330 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1331 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1332 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1333 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1334 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1335 rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1336
1337 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1338 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1339 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1340 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1341
1342 rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1343 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1344 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1345 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1346 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1347 else
1348 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1349 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1350 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1351 rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1352
1353 rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1354
1355 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1356 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1357 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1358 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1359 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1360 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1361 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1362
1363 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1364 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1365 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1366 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1367 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1368 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1369 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1370 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1371 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1372 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1373 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1374
1375 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1376 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1377 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1378 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1379 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1380 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1381 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1382 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1383 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1384 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1385 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1386
1387 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1388 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1389 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1390 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1391 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1392 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1393 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1394 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1395 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1396 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1397 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1398
1399 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1400 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1401 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1402 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1403 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1404 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1405 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1406 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1407 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1408 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1409 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1410
1411 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1412 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1413 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1414 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1415 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1416 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1417 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1418 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1419 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1420 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1421 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1422
1423 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1424 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1425 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1426 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1427 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1428 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1429 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1430 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1431 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1432 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1433 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1434
1435 rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1436
1437 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1438 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1439 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1440 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1441 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1442 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1443 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1444 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1445 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1446 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1447 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1448
1449 rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1450 rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1451
1452 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1453 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1454 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1455 IEEE80211_MAX_RTS_THRESHOLD);
1456 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1457 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1458
1459 rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1460 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1461
1462 /*
1463 * ASIC will keep garbage value after boot, clear encryption keys.
1464 */
1465 for (i = 0; i < 4; i++)
1466 rt2x00usb_register_write(rt2x00dev,
1467 SHARED_KEY_MODE_ENTRY(i), 0);
1468
1469 for (i = 0; i < 256; i++) {
1470 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1471 rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1472 wcid, sizeof(wcid));
1473
1474 rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1475 rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1476 }
1477
1478 /*
1479 * Clear all beacons
1480 * For the Beacon base registers we only need to clear
1481 * the first byte since that byte contains the VALID and OWNER
1482 * bits which (when set to 0) will invalidate the entire beacon.
1483 */
1484 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1485 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1486 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1487 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1488 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1489 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1490 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1491 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1492
1493 rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1494 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1495 rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1496
1497 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1498 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1499 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1500 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1501 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1502 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1503 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1504 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1505 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1506 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1507
1508 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1509 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1510 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1511 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1512 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1513 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1514 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1515 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1516 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1517 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1518
1519 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1520 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1521 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1522 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1523 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1524 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1525 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1526 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1527 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1528 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1529
1530 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1531 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1532 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1533 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1534 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1535 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1536
1537 /*
1538 * We must clear the error counters.
1539 * These registers are cleared on read,
1540 * so we may pass a useless variable to store the value.
1541 */
1542 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1543 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1544 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1545 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1546 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1547 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1548
1549 return 0;
1550}
1551
1552static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1553{
1554 unsigned int i;
1555 u32 reg;
1556
1557 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1558 rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1559 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1560 return 0;
1561
1562 udelay(REGISTER_BUSY_DELAY);
1563 }
1564
1565 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1566 return -EACCES;
1567}
1568
1569static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1570{
1571 unsigned int i;
1572 u8 value;
1573
1574 /*
1575 * BBP was enabled after firmware was loaded,
1576 * but we need to reactivate it now.
1577 */
1578 rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1579 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1580 msleep(1);
1581
1582 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1583 rt2800usb_bbp_read(rt2x00dev, 0, &value);
1584 if ((value != 0xff) && (value != 0x00))
1585 return 0;
1586 udelay(REGISTER_BUSY_DELAY);
1587 }
1588
1589 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1590 return -EACCES;
1591}
1592
1593static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1594{
1595 unsigned int i;
1596 u16 eeprom;
1597 u8 reg_id;
1598 u8 value;
1599
1600 if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1601 rt2800usb_wait_bbp_ready(rt2x00dev)))
1602 return -EACCES;
1603
1604 rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1605 rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1606 rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1607 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1608 rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1609 rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1610 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1611 rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1612 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1613 rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1614 rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1615 rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1616 rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1617 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1618
1619 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1620 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1621 rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1622 }
1623
1624 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1625 rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1626 }
1627
1628 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1629 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1630 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1631 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1632 }
1633
1634 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1635 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1636
1637 if (eeprom != 0xffff && eeprom != 0x0000) {
1638 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1639 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1640 rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1641 }
1642 }
1643
1644 return 0;
1645}
1646
1647static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1648 bool bw40, u8 rfcsr24, u8 filter_target)
1649{
1650 unsigned int i;
1651 u8 bbp;
1652 u8 rfcsr;
1653 u8 passband;
1654 u8 stopband;
1655 u8 overtuned = 0;
1656
1657 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1658
1659 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1660 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1661 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1662
1663 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1664 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1665 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1666
1667 /*
1668 * Set power & frequency of passband test tone
1669 */
1670 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1671
1672 for (i = 0; i < 100; i++) {
1673 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1674 msleep(1);
1675
1676 rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1677 if (passband)
1678 break;
1679 }
1680
1681 /*
1682 * Set power & frequency of stopband test tone
1683 */
1684 rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1685
1686 for (i = 0; i < 100; i++) {
1687 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1688 msleep(1);
1689
1690 rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1691
1692 if ((passband - stopband) <= filter_target) {
1693 rfcsr24++;
1694 overtuned += ((passband - stopband) == filter_target);
1695 } else
1696 break;
1697
1698 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1699 }
1700
1701 rfcsr24 -= !!overtuned;
1702
1703 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1704 return rfcsr24;
1705}
1706
1707static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1708{
1709 u8 rfcsr;
1710 u8 bbp;
1711
1712 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1713 return 0;
1714
1715 /*
1716 * Init RF calibration.
1717 */
1718 rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1719 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1720 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1721 msleep(1);
1722 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1723 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1724
1725 rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1726 rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1727 rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1728 rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1729 rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1730 rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1731 rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1732 rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1733 rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1734 rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1735 rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1736 rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1737 rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1738 rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1739 rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1740 rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1741 rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1742 rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1743 rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1744 rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1745
1746 /*
1747 * Set RX Filter calibration for 20MHz and 40MHz
1748 */
1749 rt2x00dev->calibration[0] =
1750 rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1751 rt2x00dev->calibration[1] =
1752 rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1753
1754 /*
1755 * Set back to initial state
1756 */
1757 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1758
1759 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1760 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1761 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1762
1763 /*
1764 * set BBP back to BW20
1765 */
1766 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1767 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1768 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1769
1770 return 0;
1771}
1772
1773/*
1774 * Device state switch handlers. 233 * Device state switch handlers.
1775 */ 234 */
1776static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev, 235static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
@@ -1778,11 +237,11 @@ static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1778{ 237{
1779 u32 reg; 238 u32 reg;
1780 239
1781 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 240 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1782 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 241 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1783 (state == STATE_RADIO_RX_ON) || 242 (state == STATE_RADIO_RX_ON) ||
1784 (state == STATE_RADIO_RX_ON_LINK)); 243 (state == STATE_RADIO_RX_ON_LINK));
1785 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 244 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1786} 245}
1787 246
1788static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 247static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
@@ -1791,7 +250,7 @@ static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1791 u32 reg; 250 u32 reg;
1792 251
1793 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 252 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1794 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 253 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1795 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 254 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1796 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 255 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1797 return 0; 256 return 0;
@@ -1812,25 +271,25 @@ static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1812 * Initialize all registers. 271 * Initialize all registers.
1813 */ 272 */
1814 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) || 273 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1815 rt2800usb_init_registers(rt2x00dev) || 274 rt2800_init_registers(rt2x00dev) ||
1816 rt2800usb_init_bbp(rt2x00dev) || 275 rt2800_init_bbp(rt2x00dev) ||
1817 rt2800usb_init_rfcsr(rt2x00dev))) 276 rt2800_init_rfcsr(rt2x00dev)))
1818 return -EIO; 277 return -EIO;
1819 278
1820 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 279 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1821 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 280 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1822 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 281 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1823 282
1824 udelay(50); 283 udelay(50);
1825 284
1826 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1827 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 286 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1828 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 287 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1829 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 288 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1830 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 289 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1831 290
1832 291
1833 rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg); 292 rt2800_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1834 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0); 293 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1835 /* Don't use bulk in aggregation when working with USB 1.1 */ 294 /* Don't use bulk in aggregation when working with USB 1.1 */
1836 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN, 295 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
@@ -1844,26 +303,26 @@ static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1844 ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3); 303 ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1845 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1); 304 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1846 rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1); 305 rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1847 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg); 306 rt2800_register_write(rt2x00dev, USB_DMA_CFG, reg);
1848 307
1849 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 308 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1850 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 309 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1851 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1); 310 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1852 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 311 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1853 312
1854 /* 313 /*
1855 * Initialize LED control 314 * Initialize LED control
1856 */ 315 */
1857 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word); 316 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1858 rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff, 317 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1859 word & 0xff, (word >> 8) & 0xff); 318 word & 0xff, (word >> 8) & 0xff);
1860 319
1861 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word); 320 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1862 rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff, 321 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1863 word & 0xff, (word >> 8) & 0xff); 322 word & 0xff, (word >> 8) & 0xff);
1864 323
1865 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word); 324 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1866 rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff, 325 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1867 word & 0xff, (word >> 8) & 0xff); 326 word & 0xff, (word >> 8) & 0xff);
1868 327
1869 return 0; 328 return 0;
@@ -1873,14 +332,14 @@ static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1873{ 332{
1874 u32 reg; 333 u32 reg;
1875 334
1876 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 335 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1877 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 336 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1878 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 337 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1879 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 338 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1880 339
1881 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 340 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1882 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0); 341 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1883 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0); 342 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
1884 343
1885 /* Wait for DMA, ignore error */ 344 /* Wait for DMA, ignore error */
1886 rt2800usb_wait_wpdma_ready(rt2x00dev); 345 rt2800usb_wait_wpdma_ready(rt2x00dev);
@@ -1892,9 +351,9 @@ static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1892 enum dev_state state) 351 enum dev_state state)
1893{ 352{
1894 if (state == STATE_AWAKE) 353 if (state == STATE_AWAKE)
1895 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); 354 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1896 else 355 else
1897 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2); 356 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1898 357
1899 return 0; 358 return 0;
1900} 359}
@@ -2048,9 +507,9 @@ static void rt2800usb_write_beacon(struct queue_entry *entry)
2048 * Disable beaconing while we are reloading the beacon data, 507 * Disable beaconing while we are reloading the beacon data,
2049 * otherwise we might be sending out invalid data. 508 * otherwise we might be sending out invalid data.
2050 */ 509 */
2051 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 510 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2052 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 511 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2053 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg); 512 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2054 513
2055 /* 514 /*
2056 * Write entire beacon with descriptor to register. 515 * Write entire beacon with descriptor to register.
@@ -2093,12 +552,12 @@ static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2093 return; 552 return;
2094 } 553 }
2095 554
2096 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 555 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2097 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) { 556 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2098 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); 557 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2099 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); 558 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2100 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); 559 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2101 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg); 560 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2102 } 561 }
2103} 562}
2104 563
@@ -2124,7 +583,7 @@ static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2124 */ 583 */
2125 memcpy(skbdesc->desc, rxd, skbdesc->desc_len); 584 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2126 rxd = (__le32 *)skbdesc->desc; 585 rxd = (__le32 *)skbdesc->desc;
2127 rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)]; 586 rxwi = &rxd[RXINFO_DESC_SIZE / sizeof(__le32)];
2128 587
2129 /* 588 /*
2130 * It is now safe to read the descriptor on all architectures. 589 * It is now safe to read the descriptor on all architectures.
@@ -2326,7 +785,7 @@ static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2326 * Identify RF chipset. 785 * Identify RF chipset.
2327 */ 786 */
2328 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 787 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2329 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg); 788 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2330 rt2x00_set_chip(rt2x00dev, RT2870, value, reg); 789 rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2331 790
2332 /* 791 /*
@@ -2385,9 +844,9 @@ static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2385 * Store led settings, for correct led behaviour. 844 * Store led settings, for correct led behaviour.
2386 */ 845 */
2387#ifdef CONFIG_RT2X00_LIB_LEDS 846#ifdef CONFIG_RT2X00_LIB_LEDS
2388 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 847 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2389 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 848 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2390 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 849 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2391 850
2392 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, 851 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2393 &rt2x00dev->led_mcu_reg); 852 &rt2x00dev->led_mcu_reg);
@@ -2600,10 +1059,25 @@ static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2600 return 0; 1059 return 0;
2601} 1060}
2602 1061
1062static const struct rt2800_ops rt2800usb_rt2800_ops = {
1063 .register_read = rt2x00usb_register_read,
1064 .register_write = rt2x00usb_register_write,
1065 .register_write_lock = rt2x00usb_register_write_lock,
1066
1067 .register_multiread = rt2x00usb_register_multiread,
1068 .register_multiwrite = rt2x00usb_register_multiwrite,
1069
1070 .regbusy_read = rt2x00usb_regbusy_read,
1071};
1072
2603static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev) 1073static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2604{ 1074{
2605 int retval; 1075 int retval;
2606 1076
1077 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_USB);
1078
1079 rt2x00dev->priv = (void *)&rt2800usb_rt2800_ops;
1080
2607 /* 1081 /*
2608 * Allocate eeprom data. 1082 * Allocate eeprom data.
2609 */ 1083 */
@@ -2645,162 +1119,6 @@ static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2645 return 0; 1119 return 0;
2646} 1120}
2647 1121
2648/*
2649 * IEEE80211 stack callback functions.
2650 */
2651static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2652 u32 *iv32, u16 *iv16)
2653{
2654 struct rt2x00_dev *rt2x00dev = hw->priv;
2655 struct mac_iveiv_entry iveiv_entry;
2656 u32 offset;
2657
2658 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2659 rt2x00usb_register_multiread(rt2x00dev, offset,
2660 &iveiv_entry, sizeof(iveiv_entry));
2661
2662 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2663 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2664}
2665
2666static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2667{
2668 struct rt2x00_dev *rt2x00dev = hw->priv;
2669 u32 reg;
2670 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2671
2672 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2673 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2674 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2675
2676 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2677 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2678 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2679
2680 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2681 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2682 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2683
2684 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2685 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2686 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2687
2688 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2689 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2690 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2691
2692 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2693 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2694 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2695
2696 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2697 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2698 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2699
2700 return 0;
2701}
2702
2703static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2704 const struct ieee80211_tx_queue_params *params)
2705{
2706 struct rt2x00_dev *rt2x00dev = hw->priv;
2707 struct data_queue *queue;
2708 struct rt2x00_field32 field;
2709 int retval;
2710 u32 reg;
2711 u32 offset;
2712
2713 /*
2714 * First pass the configuration through rt2x00lib, that will
2715 * update the queue settings and validate the input. After that
2716 * we are free to update the registers based on the value
2717 * in the queue parameter.
2718 */
2719 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2720 if (retval)
2721 return retval;
2722
2723 /*
2724 * We only need to perform additional register initialization
2725 * for WMM queues/
2726 */
2727 if (queue_idx >= 4)
2728 return 0;
2729
2730 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2731
2732 /* Update WMM TXOP register */
2733 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2734 field.bit_offset = (queue_idx & 1) * 16;
2735 field.bit_mask = 0xffff << field.bit_offset;
2736
2737 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2738 rt2x00_set_field32(&reg, field, queue->txop);
2739 rt2x00usb_register_write(rt2x00dev, offset, reg);
2740
2741 /* Update WMM registers */
2742 field.bit_offset = queue_idx * 4;
2743 field.bit_mask = 0xf << field.bit_offset;
2744
2745 rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2746 rt2x00_set_field32(&reg, field, queue->aifs);
2747 rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2748
2749 rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2750 rt2x00_set_field32(&reg, field, queue->cw_min);
2751 rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2752
2753 rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2754 rt2x00_set_field32(&reg, field, queue->cw_max);
2755 rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2756
2757 /* Update EDCA registers */
2758 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2759
2760 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2761 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2762 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2763 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2764 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2765 rt2x00usb_register_write(rt2x00dev, offset, reg);
2766
2767 return 0;
2768}
2769
2770static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2771{
2772 struct rt2x00_dev *rt2x00dev = hw->priv;
2773 u64 tsf;
2774 u32 reg;
2775
2776 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2777 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2778 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2779 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2780
2781 return tsf;
2782}
2783
2784static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2785 .tx = rt2x00mac_tx,
2786 .start = rt2x00mac_start,
2787 .stop = rt2x00mac_stop,
2788 .add_interface = rt2x00mac_add_interface,
2789 .remove_interface = rt2x00mac_remove_interface,
2790 .config = rt2x00mac_config,
2791 .configure_filter = rt2x00mac_configure_filter,
2792 .set_tim = rt2x00mac_set_tim,
2793 .set_key = rt2x00mac_set_key,
2794 .get_stats = rt2x00mac_get_stats,
2795 .get_tkip_seq = rt2800usb_get_tkip_seq,
2796 .set_rts_threshold = rt2800usb_set_rts_threshold,
2797 .bss_info_changed = rt2x00mac_bss_info_changed,
2798 .conf_tx = rt2800usb_conf_tx,
2799 .get_tx_stats = rt2x00mac_get_tx_stats,
2800 .get_tsf = rt2800usb_get_tsf,
2801 .rfkill_poll = rt2x00mac_rfkill_poll,
2802};
2803
2804static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = { 1122static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2805 .probe_hw = rt2800usb_probe_hw, 1123 .probe_hw = rt2800usb_probe_hw,
2806 .get_firmware_name = rt2800usb_get_firmware_name, 1124 .get_firmware_name = rt2800usb_get_firmware_name,
@@ -2810,10 +1128,10 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2810 .uninitialize = rt2x00usb_uninitialize, 1128 .uninitialize = rt2x00usb_uninitialize,
2811 .clear_entry = rt2x00usb_clear_entry, 1129 .clear_entry = rt2x00usb_clear_entry,
2812 .set_device_state = rt2800usb_set_device_state, 1130 .set_device_state = rt2800usb_set_device_state,
2813 .rfkill_poll = rt2800usb_rfkill_poll, 1131 .rfkill_poll = rt2800_rfkill_poll,
2814 .link_stats = rt2800usb_link_stats, 1132 .link_stats = rt2800_link_stats,
2815 .reset_tuner = rt2800usb_reset_tuner, 1133 .reset_tuner = rt2800_reset_tuner,
2816 .link_tuner = rt2800usb_link_tuner, 1134 .link_tuner = rt2800_link_tuner,
2817 .write_tx_desc = rt2800usb_write_tx_desc, 1135 .write_tx_desc = rt2800usb_write_tx_desc,
2818 .write_tx_data = rt2x00usb_write_tx_data, 1136 .write_tx_data = rt2x00usb_write_tx_data,
2819 .write_beacon = rt2800usb_write_beacon, 1137 .write_beacon = rt2800usb_write_beacon,
@@ -2821,19 +1139,19 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2821 .kick_tx_queue = rt2800usb_kick_tx_queue, 1139 .kick_tx_queue = rt2800usb_kick_tx_queue,
2822 .kill_tx_queue = rt2x00usb_kill_tx_queue, 1140 .kill_tx_queue = rt2x00usb_kill_tx_queue,
2823 .fill_rxdone = rt2800usb_fill_rxdone, 1141 .fill_rxdone = rt2800usb_fill_rxdone,
2824 .config_shared_key = rt2800usb_config_shared_key, 1142 .config_shared_key = rt2800_config_shared_key,
2825 .config_pairwise_key = rt2800usb_config_pairwise_key, 1143 .config_pairwise_key = rt2800_config_pairwise_key,
2826 .config_filter = rt2800usb_config_filter, 1144 .config_filter = rt2800_config_filter,
2827 .config_intf = rt2800usb_config_intf, 1145 .config_intf = rt2800_config_intf,
2828 .config_erp = rt2800usb_config_erp, 1146 .config_erp = rt2800_config_erp,
2829 .config_ant = rt2800usb_config_ant, 1147 .config_ant = rt2800_config_ant,
2830 .config = rt2800usb_config, 1148 .config = rt2800_config,
2831}; 1149};
2832 1150
2833static const struct data_queue_desc rt2800usb_queue_rx = { 1151static const struct data_queue_desc rt2800usb_queue_rx = {
2834 .entry_num = RX_ENTRIES, 1152 .entry_num = RX_ENTRIES,
2835 .data_size = AGGREGATION_SIZE, 1153 .data_size = AGGREGATION_SIZE,
2836 .desc_size = RXD_DESC_SIZE + RXWI_DESC_SIZE, 1154 .desc_size = RXINFO_DESC_SIZE + RXWI_DESC_SIZE,
2837 .priv_size = sizeof(struct queue_entry_priv_usb), 1155 .priv_size = sizeof(struct queue_entry_priv_usb),
2838}; 1156};
2839 1157
@@ -2862,9 +1180,9 @@ static const struct rt2x00_ops rt2800usb_ops = {
2862 .tx = &rt2800usb_queue_tx, 1180 .tx = &rt2800usb_queue_tx,
2863 .bcn = &rt2800usb_queue_bcn, 1181 .bcn = &rt2800usb_queue_bcn,
2864 .lib = &rt2800usb_rt2x00_ops, 1182 .lib = &rt2800usb_rt2x00_ops,
2865 .hw = &rt2800usb_mac80211_ops, 1183 .hw = &rt2800_mac80211_ops,
2866#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1184#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2867 .debugfs = &rt2800usb_rt2x00debug, 1185 .debugfs = &rt2800_rt2x00debug,
2868#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1186#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2869}; 1187};
2870 1188
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.h b/drivers/net/wireless/rt2x00/rt2800usb.h
index 4d9991c9a51c..c9d7d40ee5fb 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.h
+++ b/drivers/net/wireless/rt2x00/rt2800usb.h
@@ -28,288 +28,10 @@
28#define RT2800USB_H 28#define RT2800USB_H
29 29
30/* 30/*
31 * RF chip defines.
32 *
33 * RF2820 2.4G 2T3R
34 * RF2850 2.4G/5G 2T3R
35 * RF2720 2.4G 1T2R
36 * RF2750 2.4G/5G 1T2R
37 * RF3020 2.4G 1T1R
38 * RF2020 2.4G B/G
39 * RF3021 2.4G 1T2R
40 * RF3022 2.4G 2T2R
41 * RF3052 2.4G 2T2R
42 */
43#define RF2820 0x0001
44#define RF2850 0x0002
45#define RF2720 0x0003
46#define RF2750 0x0004
47#define RF3020 0x0005
48#define RF2020 0x0006
49#define RF3021 0x0007
50#define RF3022 0x0008
51#define RF3052 0x0009
52
53/*
54 * RT2870 version
55 */
56#define RT2860C_VERSION 0x28600100
57#define RT2860D_VERSION 0x28600101
58#define RT2880E_VERSION 0x28720200
59#define RT2883_VERSION 0x28830300
60#define RT3070_VERSION 0x30700200
61
62/*
63 * Signal information.
64 * Defaul offset is required for RSSI <-> dBm conversion.
65 */
66#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
67
68/*
69 * Register layout information.
70 */
71#define CSR_REG_BASE 0x1000
72#define CSR_REG_SIZE 0x0800
73#define EEPROM_BASE 0x0000
74#define EEPROM_SIZE 0x0110
75#define BBP_BASE 0x0000
76#define BBP_SIZE 0x0080
77#define RF_BASE 0x0004
78#define RF_SIZE 0x0010
79
80/*
81 * Number of TX queues.
82 */
83#define NUM_TX_QUEUES 4
84
85/*
86 * USB registers. 31 * USB registers.
87 */ 32 */
88 33
89/* 34/*
90 * HOST-MCU shared memory
91 */
92#define HOST_CMD_CSR 0x0404
93#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
94
95/*
96 * INT_SOURCE_CSR: Interrupt source register.
97 * Write one to clear corresponding bit.
98 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
99 */
100#define INT_SOURCE_CSR 0x0200
101#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
102#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
103#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
104#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
105#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
106#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
107#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
108#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
109#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
110#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
111#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
112#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
113#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
114#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
115#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
116#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
117#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
118#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
119
120/*
121 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
122 */
123#define INT_MASK_CSR 0x0204
124#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
125#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
126#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
127#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
128#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
129#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
130#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
131#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
132#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
133#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
134#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
135#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
136#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
137#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
138#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
139#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
140#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
141#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
142
143/*
144 * WPDMA_GLO_CFG
145 */
146#define WPDMA_GLO_CFG 0x0208
147#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
148#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
149#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
150#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
151#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
152#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
153#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
154#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
155#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
156
157/*
158 * WPDMA_RST_IDX
159 */
160#define WPDMA_RST_IDX 0x020c
161#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
162#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
163#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
164#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
165#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
166#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
167#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
168
169/*
170 * DELAY_INT_CFG
171 */
172#define DELAY_INT_CFG 0x0210
173#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
174#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
175#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
176#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
177#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
178#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
179
180/*
181 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
182 * AIFSN0: AC_BE
183 * AIFSN1: AC_BK
184 * AIFSN1: AC_VI
185 * AIFSN1: AC_VO
186 */
187#define WMM_AIFSN_CFG 0x0214
188#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
189#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
190#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
191#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
192
193/*
194 * WMM_CWMIN_CSR: CWmin for each EDCA AC
195 * CWMIN0: AC_BE
196 * CWMIN1: AC_BK
197 * CWMIN1: AC_VI
198 * CWMIN1: AC_VO
199 */
200#define WMM_CWMIN_CFG 0x0218
201#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
202#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
203#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
204#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
205
206/*
207 * WMM_CWMAX_CSR: CWmax for each EDCA AC
208 * CWMAX0: AC_BE
209 * CWMAX1: AC_BK
210 * CWMAX1: AC_VI
211 * CWMAX1: AC_VO
212 */
213#define WMM_CWMAX_CFG 0x021c
214#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
215#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
216#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
217#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
218
219/*
220 * AC_TXOP0: AC_BK/AC_BE TXOP register
221 * AC0TXOP: AC_BK in unit of 32us
222 * AC1TXOP: AC_BE in unit of 32us
223 */
224#define WMM_TXOP0_CFG 0x0220
225#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
226#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
227
228/*
229 * AC_TXOP1: AC_VO/AC_VI TXOP register
230 * AC2TXOP: AC_VI in unit of 32us
231 * AC3TXOP: AC_VO in unit of 32us
232 */
233#define WMM_TXOP1_CFG 0x0224
234#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
235#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
236
237/*
238 * GPIO_CTRL_CFG:
239 */
240#define GPIO_CTRL_CFG 0x0228
241#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
242#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
243#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
244#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
245#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
246#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
247#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
248#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
249#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
250
251/*
252 * MCU_CMD_CFG
253 */
254#define MCU_CMD_CFG 0x022c
255
256/*
257 * AC_BK register offsets
258 */
259#define TX_BASE_PTR0 0x0230
260#define TX_MAX_CNT0 0x0234
261#define TX_CTX_IDX0 0x0238
262#define TX_DTX_IDX0 0x023c
263
264/*
265 * AC_BE register offsets
266 */
267#define TX_BASE_PTR1 0x0240
268#define TX_MAX_CNT1 0x0244
269#define TX_CTX_IDX1 0x0248
270#define TX_DTX_IDX1 0x024c
271
272/*
273 * AC_VI register offsets
274 */
275#define TX_BASE_PTR2 0x0250
276#define TX_MAX_CNT2 0x0254
277#define TX_CTX_IDX2 0x0258
278#define TX_DTX_IDX2 0x025c
279
280/*
281 * AC_VO register offsets
282 */
283#define TX_BASE_PTR3 0x0260
284#define TX_MAX_CNT3 0x0264
285#define TX_CTX_IDX3 0x0268
286#define TX_DTX_IDX3 0x026c
287
288/*
289 * HCCA register offsets
290 */
291#define TX_BASE_PTR4 0x0270
292#define TX_MAX_CNT4 0x0274
293#define TX_CTX_IDX4 0x0278
294#define TX_DTX_IDX4 0x027c
295
296/*
297 * MGMT register offsets
298 */
299#define TX_BASE_PTR5 0x0280
300#define TX_MAX_CNT5 0x0284
301#define TX_CTX_IDX5 0x0288
302#define TX_DTX_IDX5 0x028c
303
304/*
305 * RX register offsets
306 */
307#define RX_BASE_PTR 0x0290
308#define RX_MAX_CNT 0x0294
309#define RX_CRX_IDX 0x0298
310#define RX_DRX_IDX 0x029c
311
312/*
313 * USB_DMA_CFG 35 * USB_DMA_CFG
314 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns. 36 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
315 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes. 37 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
@@ -343,1448 +65,16 @@
343#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff) 65#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff)
344 66
345/* 67/*
346 * PBF_SYS_CTRL
347 * HOST_RAM_WRITE: enable Host program ram write selection
348 */
349#define PBF_SYS_CTRL 0x0400
350#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
351#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
352
353/*
354 * PBF registers
355 * Most are for debug. Driver doesn't touch PBF register.
356 */
357#define PBF_CFG 0x0408
358#define PBF_MAX_PCNT 0x040c
359#define PBF_CTRL 0x0410
360#define PBF_INT_STA 0x0414
361#define PBF_INT_ENA 0x0418
362
363/*
364 * BCN_OFFSET0:
365 */
366#define BCN_OFFSET0 0x042c
367#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
368#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
369#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
370#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
371
372/*
373 * BCN_OFFSET1:
374 */
375#define BCN_OFFSET1 0x0430
376#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
377#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
378#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
379#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
380
381/*
382 * PBF registers
383 * Most are for debug. Driver doesn't touch PBF register.
384 */
385#define TXRXQ_PCNT 0x0438
386#define PBF_DBG 0x043c
387
388/*
389 * RF registers
390 */
391#define RF_CSR_CFG 0x0500
392#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
393#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
394#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
395#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
396
397/*
398 * MAC Control/Status Registers(CSR).
399 * Some values are set in TU, whereas 1 TU == 1024 us.
400 */
401
402/*
403 * MAC_CSR0: ASIC revision number.
404 * ASIC_REV: 0
405 * ASIC_VER: 2870
406 */
407#define MAC_CSR0 0x1000
408#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
409#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
410
411/*
412 * MAC_SYS_CTRL:
413 */
414#define MAC_SYS_CTRL 0x1004
415#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
416#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
417#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
418#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
419#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
420#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
421#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
422#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
423
424/*
425 * MAC_ADDR_DW0: STA MAC register 0
426 */
427#define MAC_ADDR_DW0 0x1008
428#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
429#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
430#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
431#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
432
433/*
434 * MAC_ADDR_DW1: STA MAC register 1
435 * UNICAST_TO_ME_MASK:
436 * Used to mask off bits from byte 5 of the MAC address
437 * to determine the UNICAST_TO_ME bit for RX frames.
438 * The full mask is complemented by BSS_ID_MASK:
439 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
440 */
441#define MAC_ADDR_DW1 0x100c
442#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
443#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
444#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
445
446/*
447 * MAC_BSSID_DW0: BSSID register 0
448 */
449#define MAC_BSSID_DW0 0x1010
450#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
451#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
452#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
453#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
454
455/*
456 * MAC_BSSID_DW1: BSSID register 1
457 * BSS_ID_MASK:
458 * 0: 1-BSSID mode (BSS index = 0)
459 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
460 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
461 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
462 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
463 * BSSID. This will make sure that those bits will be ignored
464 * when determining the MY_BSS of RX frames.
465 */
466#define MAC_BSSID_DW1 0x1014
467#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
468#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
469#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
470#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
471
472/*
473 * MAX_LEN_CFG: Maximum frame length register.
474 * MAX_MPDU: rt2860b max 16k bytes
475 * MAX_PSDU: Maximum PSDU length
476 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
477 */
478#define MAX_LEN_CFG 0x1018
479#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
480#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
481#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
482#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
483
484/*
485 * BBP_CSR_CFG: BBP serial control register
486 * VALUE: Register value to program into BBP
487 * REG_NUM: Selected BBP register
488 * READ_CONTROL: 0 write BBP, 1 read BBP
489 * BUSY: ASIC is busy executing BBP commands
490 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
491 * BBP_RW_MODE: 0 serial, 1 paralell
492 */
493#define BBP_CSR_CFG 0x101c
494#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
495#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
496#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
497#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
498#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
499#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
500
501/*
502 * RF_CSR_CFG0: RF control register
503 * REGID_AND_VALUE: Register value to program into RF
504 * BITWIDTH: Selected RF register
505 * STANDBYMODE: 0 high when standby, 1 low when standby
506 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
507 * BUSY: ASIC is busy executing RF commands
508 */
509#define RF_CSR_CFG0 0x1020
510#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
511#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
512#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
513#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
514#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
515#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
516
517/*
518 * RF_CSR_CFG1: RF control register
519 * REGID_AND_VALUE: Register value to program into RF
520 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
521 * 0: 3 system clock cycle (37.5usec)
522 * 1: 5 system clock cycle (62.5usec)
523 */
524#define RF_CSR_CFG1 0x1024
525#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
526#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
527
528/*
529 * RF_CSR_CFG2: RF control register
530 * VALUE: Register value to program into RF
531 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
532 * 0: 3 system clock cycle (37.5usec)
533 * 1: 5 system clock cycle (62.5usec)
534 */
535#define RF_CSR_CFG2 0x1028
536#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
537
538/*
539 * LED_CFG: LED control
540 * color LED's:
541 * 0: off
542 * 1: blinking upon TX2
543 * 2: periodic slow blinking
544 * 3: always on
545 * LED polarity:
546 * 0: active low
547 * 1: active high
548 */
549#define LED_CFG 0x102c
550#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
551#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
552#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
553#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
554#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
555#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
556#define LED_CFG_LED_POLAR FIELD32(0x40000000)
557
558/*
559 * XIFS_TIME_CFG: MAC timing
560 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
561 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
562 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
563 * when MAC doesn't reference BBP signal BBRXEND
564 * EIFS: unit 1us
565 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
566 *
567 */
568#define XIFS_TIME_CFG 0x1100
569#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
570#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
571#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
572#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
573#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
574
575/*
576 * BKOFF_SLOT_CFG:
577 */
578#define BKOFF_SLOT_CFG 0x1104
579#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
580#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
581
582/*
583 * NAV_TIME_CFG:
584 */
585#define NAV_TIME_CFG 0x1108
586#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
587#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
588#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
589#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
590
591/*
592 * CH_TIME_CFG: count as channel busy
593 */
594#define CH_TIME_CFG 0x110c
595
596/*
597 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
598 */
599#define PBF_LIFE_TIMER 0x1110
600
601/*
602 * BCN_TIME_CFG:
603 * BEACON_INTERVAL: in unit of 1/16 TU
604 * TSF_TICKING: Enable TSF auto counting
605 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
606 * BEACON_GEN: Enable beacon generator
607 */
608#define BCN_TIME_CFG 0x1114
609#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
610#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
611#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
612#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
613#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
614#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
615
616/*
617 * TBTT_SYNC_CFG:
618 */
619#define TBTT_SYNC_CFG 0x1118
620
621/*
622 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
623 */
624#define TSF_TIMER_DW0 0x111c
625#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
626
627/*
628 * TSF_TIMER_DW1: Local msb TSF timer, read-only
629 */
630#define TSF_TIMER_DW1 0x1120
631#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
632
633/*
634 * TBTT_TIMER: TImer remains till next TBTT, read-only
635 */
636#define TBTT_TIMER 0x1124
637
638/*
639 * INT_TIMER_CFG:
640 */
641#define INT_TIMER_CFG 0x1128
642
643/*
644 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
645 */
646#define INT_TIMER_EN 0x112c
647
648/*
649 * CH_IDLE_STA: channel idle time
650 */
651#define CH_IDLE_STA 0x1130
652
653/*
654 * CH_BUSY_STA: channel busy time
655 */
656#define CH_BUSY_STA 0x1134
657
658/*
659 * MAC_STATUS_CFG:
660 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
661 * if 1 or higher one of the 2 registers is busy.
662 */
663#define MAC_STATUS_CFG 0x1200
664#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
665
666/*
667 * PWR_PIN_CFG:
668 */
669#define PWR_PIN_CFG 0x1204
670
671/*
672 * AUTOWAKEUP_CFG: Manual power control / status register
673 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
674 * AUTOWAKE: 0:sleep, 1:awake
675 */
676#define AUTOWAKEUP_CFG 0x1208
677#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
678#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
679#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
680
681/*
682 * EDCA_AC0_CFG:
683 */
684#define EDCA_AC0_CFG 0x1300
685#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
686#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
687#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
688#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
689
690/*
691 * EDCA_AC1_CFG:
692 */
693#define EDCA_AC1_CFG 0x1304
694#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
695#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
696#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
697#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
698
699/*
700 * EDCA_AC2_CFG:
701 */
702#define EDCA_AC2_CFG 0x1308
703#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
704#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
705#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
706#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
707
708/*
709 * EDCA_AC3_CFG:
710 */
711#define EDCA_AC3_CFG 0x130c
712#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
713#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
714#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
715#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
716
717/*
718 * EDCA_TID_AC_MAP:
719 */
720#define EDCA_TID_AC_MAP 0x1310
721
722/*
723 * TX_PWR_CFG_0:
724 */
725#define TX_PWR_CFG_0 0x1314
726#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
727#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
728#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
729#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
730#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
731#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
732#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
733#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
734
735/*
736 * TX_PWR_CFG_1:
737 */
738#define TX_PWR_CFG_1 0x1318
739#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
740#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
741#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
742#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
743#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
744#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
745#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
746#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
747
748/*
749 * TX_PWR_CFG_2:
750 */
751#define TX_PWR_CFG_2 0x131c
752#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
753#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
754#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
755#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
756#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
757#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
758#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
759#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
760
761/*
762 * TX_PWR_CFG_3:
763 */
764#define TX_PWR_CFG_3 0x1320
765#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
766#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
767#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
768#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
769#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
770#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
771#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
772#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
773
774/*
775 * TX_PWR_CFG_4:
776 */
777#define TX_PWR_CFG_4 0x1324
778#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
779#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
780#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
781#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
782
783/*
784 * TX_PIN_CFG:
785 */
786#define TX_PIN_CFG 0x1328
787#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
788#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
789#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
790#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
791#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
792#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
793#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
794#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
795#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
796#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
797#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
798#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
799#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
800#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
801#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
802#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
803#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
804#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
805#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
806#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
807
808/*
809 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
810 */
811#define TX_BAND_CFG 0x132c
812#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
813#define TX_BAND_CFG_A FIELD32(0x00000002)
814#define TX_BAND_CFG_BG FIELD32(0x00000004)
815
816/*
817 * TX_SW_CFG0:
818 */
819#define TX_SW_CFG0 0x1330
820
821/*
822 * TX_SW_CFG1:
823 */
824#define TX_SW_CFG1 0x1334
825
826/*
827 * TX_SW_CFG2:
828 */
829#define TX_SW_CFG2 0x1338
830
831/*
832 * TXOP_THRES_CFG:
833 */
834#define TXOP_THRES_CFG 0x133c
835
836/*
837 * TXOP_CTRL_CFG:
838 */
839#define TXOP_CTRL_CFG 0x1340
840
841/*
842 * TX_RTS_CFG:
843 * RTS_THRES: unit:byte
844 * RTS_FBK_EN: enable rts rate fallback
845 */
846#define TX_RTS_CFG 0x1344
847#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
848#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
849#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
850
851/*
852 * TX_TIMEOUT_CFG:
853 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
854 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
855 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
856 * it is recommended that:
857 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
858 */
859#define TX_TIMEOUT_CFG 0x1348
860#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
861#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
862#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
863
864/*
865 * TX_RTY_CFG:
866 * SHORT_RTY_LIMIT: short retry limit
867 * LONG_RTY_LIMIT: long retry limit
868 * LONG_RTY_THRE: Long retry threshoold
869 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
870 * 0:expired by retry limit, 1: expired by mpdu life timer
871 * AGG_RTY_MODE: Aggregate MPDU retry mode
872 * 0:expired by retry limit, 1: expired by mpdu life timer
873 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
874 */
875#define TX_RTY_CFG 0x134c
876#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
877#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
878#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
879#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
880#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
881#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
882
883/*
884 * TX_LINK_CFG:
885 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
886 * MFB_ENABLE: TX apply remote MFB 1:enable
887 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
888 * 0: not apply remote remote unsolicit (MFS=7)
889 * TX_MRQ_EN: MCS request TX enable
890 * TX_RDG_EN: RDG TX enable
891 * TX_CF_ACK_EN: Piggyback CF-ACK enable
892 * REMOTE_MFB: remote MCS feedback
893 * REMOTE_MFS: remote MCS feedback sequence number
894 */
895#define TX_LINK_CFG 0x1350
896#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
897#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
898#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
899#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
900#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
901#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
902#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
903#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
904
905/*
906 * HT_FBK_CFG0:
907 */
908#define HT_FBK_CFG0 0x1354
909#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
910#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
911#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
912#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
913#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
914#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
915#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
916#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
917
918/*
919 * HT_FBK_CFG1:
920 */
921#define HT_FBK_CFG1 0x1358
922#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
923#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
924#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
925#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
926#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
927#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
928#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
929#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
930
931/*
932 * LG_FBK_CFG0:
933 */
934#define LG_FBK_CFG0 0x135c
935#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
936#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
937#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
938#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
939#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
940#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
941#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
942#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
943
944/*
945 * LG_FBK_CFG1:
946 */
947#define LG_FBK_CFG1 0x1360
948#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
949#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
950#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
951#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
952
953/*
954 * CCK_PROT_CFG: CCK Protection
955 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
956 * PROTECT_CTRL: Protection control frame type for CCK TX
957 * 0:none, 1:RTS/CTS, 2:CTS-to-self
958 * PROTECT_NAV: TXOP protection type for CCK TX
959 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
960 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
961 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
962 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
963 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
964 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
965 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
966 * RTS_TH_EN: RTS threshold enable on CCK TX
967 */
968#define CCK_PROT_CFG 0x1364
969#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
970#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
971#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
972#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
973#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
974#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
975#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
976#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
977#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
978#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
979
980/*
981 * OFDM_PROT_CFG: OFDM Protection
982 */
983#define OFDM_PROT_CFG 0x1368
984#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
985#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
986#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
987#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
988#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
989#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
990#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
991#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
992#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
993#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
994
995/*
996 * MM20_PROT_CFG: MM20 Protection
997 */
998#define MM20_PROT_CFG 0x136c
999#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1000#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1001#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1002#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1003#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1004#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1005#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1006#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1007#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1008#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1009
1010/*
1011 * MM40_PROT_CFG: MM40 Protection
1012 */
1013#define MM40_PROT_CFG 0x1370
1014#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1015#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1016#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1017#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1018#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1019#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1020#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1021#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1022#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1023#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1024
1025/*
1026 * GF20_PROT_CFG: GF20 Protection
1027 */
1028#define GF20_PROT_CFG 0x1374
1029#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1030#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1031#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1032#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1033#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1034#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1035#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1036#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1037#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1038#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1039
1040/*
1041 * GF40_PROT_CFG: GF40 Protection
1042 */
1043#define GF40_PROT_CFG 0x1378
1044#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1045#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1046#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1047#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1048#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1049#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1050#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1051#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1052#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1053#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1054
1055/*
1056 * EXP_CTS_TIME:
1057 */
1058#define EXP_CTS_TIME 0x137c
1059
1060/*
1061 * EXP_ACK_TIME:
1062 */
1063#define EXP_ACK_TIME 0x1380
1064
1065/*
1066 * RX_FILTER_CFG: RX configuration register.
1067 */
1068#define RX_FILTER_CFG 0x1400
1069#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1070#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1071#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1072#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1073#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1074#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1075#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1076#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1077#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1078#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1079#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1080#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1081#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1082#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1083#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1084#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1085#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1086
1087/*
1088 * AUTO_RSP_CFG:
1089 * AUTORESPONDER: 0: disable, 1: enable
1090 * BAC_ACK_POLICY: 0:long, 1:short preamble
1091 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1092 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1093 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1094 * DUAL_CTS_EN: Power bit value in control frame
1095 * ACK_CTS_PSM_BIT:Power bit value in control frame
1096 */
1097#define AUTO_RSP_CFG 0x1404
1098#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1099#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1100#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1101#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1102#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1103#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1104#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1105
1106/*
1107 * LEGACY_BASIC_RATE:
1108 */
1109#define LEGACY_BASIC_RATE 0x1408
1110
1111/*
1112 * HT_BASIC_RATE:
1113 */
1114#define HT_BASIC_RATE 0x140c
1115
1116/*
1117 * HT_CTRL_CFG:
1118 */
1119#define HT_CTRL_CFG 0x1410
1120
1121/*
1122 * SIFS_COST_CFG:
1123 */
1124#define SIFS_COST_CFG 0x1414
1125
1126/*
1127 * RX_PARSER_CFG:
1128 * Set NAV for all received frames
1129 */
1130#define RX_PARSER_CFG 0x1418
1131
1132/*
1133 * TX_SEC_CNT0:
1134 */
1135#define TX_SEC_CNT0 0x1500
1136
1137/*
1138 * RX_SEC_CNT0:
1139 */
1140#define RX_SEC_CNT0 0x1504
1141
1142/*
1143 * CCMP_FC_MUTE:
1144 */
1145#define CCMP_FC_MUTE 0x1508
1146
1147/*
1148 * TXOP_HLDR_ADDR0:
1149 */
1150#define TXOP_HLDR_ADDR0 0x1600
1151
1152/*
1153 * TXOP_HLDR_ADDR1:
1154 */
1155#define TXOP_HLDR_ADDR1 0x1604
1156
1157/*
1158 * TXOP_HLDR_ET:
1159 */
1160#define TXOP_HLDR_ET 0x1608
1161
1162/*
1163 * QOS_CFPOLL_RA_DW0:
1164 */
1165#define QOS_CFPOLL_RA_DW0 0x160c
1166
1167/*
1168 * QOS_CFPOLL_RA_DW1:
1169 */
1170#define QOS_CFPOLL_RA_DW1 0x1610
1171
1172/*
1173 * QOS_CFPOLL_QC:
1174 */
1175#define QOS_CFPOLL_QC 0x1614
1176
1177/*
1178 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1179 */
1180#define RX_STA_CNT0 0x1700
1181#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1182#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1183
1184/*
1185 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1186 */
1187#define RX_STA_CNT1 0x1704
1188#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1189#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1190
1191/*
1192 * RX_STA_CNT2:
1193 */
1194#define RX_STA_CNT2 0x1708
1195#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1196#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1197
1198/*
1199 * TX_STA_CNT0: TX Beacon count
1200 */
1201#define TX_STA_CNT0 0x170c
1202#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1203#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1204
1205/*
1206 * TX_STA_CNT1: TX tx count
1207 */
1208#define TX_STA_CNT1 0x1710
1209#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1210#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1211
1212/*
1213 * TX_STA_CNT2: TX tx count
1214 */
1215#define TX_STA_CNT2 0x1714
1216#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1217#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1218
1219/*
1220 * TX_STA_FIFO: TX Result for specific PID status fifo register
1221 */
1222#define TX_STA_FIFO 0x1718
1223#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1224#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1225#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1226#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1227#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1228#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1229#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1230
1231/*
1232 * TX_AGG_CNT: Debug counter
1233 */
1234#define TX_AGG_CNT 0x171c
1235#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1236#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1237
1238/*
1239 * TX_AGG_CNT0:
1240 */
1241#define TX_AGG_CNT0 0x1720
1242#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1243#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1244
1245/*
1246 * TX_AGG_CNT1:
1247 */
1248#define TX_AGG_CNT1 0x1724
1249#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1250#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1251
1252/*
1253 * TX_AGG_CNT2:
1254 */
1255#define TX_AGG_CNT2 0x1728
1256#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1257#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1258
1259/*
1260 * TX_AGG_CNT3:
1261 */
1262#define TX_AGG_CNT3 0x172c
1263#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1264#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1265
1266/*
1267 * TX_AGG_CNT4:
1268 */
1269#define TX_AGG_CNT4 0x1730
1270#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1271#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1272
1273/*
1274 * TX_AGG_CNT5:
1275 */
1276#define TX_AGG_CNT5 0x1734
1277#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1278#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1279
1280/*
1281 * TX_AGG_CNT6:
1282 */
1283#define TX_AGG_CNT6 0x1738
1284#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1285#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1286
1287/*
1288 * TX_AGG_CNT7:
1289 */
1290#define TX_AGG_CNT7 0x173c
1291#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1292#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1293
1294/*
1295 * MPDU_DENSITY_CNT:
1296 * TX_ZERO_DEL: TX zero length delimiter count
1297 * RX_ZERO_DEL: RX zero length delimiter count
1298 */
1299#define MPDU_DENSITY_CNT 0x1740
1300#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1301#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1302
1303/*
1304 * Security key table memory.
1305 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1306 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1307 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1308 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1309 * SHARED_KEY_TABLE_BASE: 32 bytes * 32-entry
1310 * SHARED_KEY_MODE_BASE: 4 bits * 32-entry
1311 */
1312#define MAC_WCID_BASE 0x1800
1313#define PAIRWISE_KEY_TABLE_BASE 0x4000
1314#define MAC_IVEIV_TABLE_BASE 0x6000
1315#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1316#define SHARED_KEY_TABLE_BASE 0x6c00
1317#define SHARED_KEY_MODE_BASE 0x7000
1318
1319#define MAC_WCID_ENTRY(__idx) \
1320 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1321#define PAIRWISE_KEY_ENTRY(__idx) \
1322 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1323#define MAC_IVEIV_ENTRY(__idx) \
1324 ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
1325#define MAC_WCID_ATTR_ENTRY(__idx) \
1326 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1327#define SHARED_KEY_ENTRY(__idx) \
1328 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1329#define SHARED_KEY_MODE_ENTRY(__idx) \
1330 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1331
1332struct mac_wcid_entry {
1333 u8 mac[6];
1334 u8 reserved[2];
1335} __attribute__ ((packed));
1336
1337struct hw_key_entry {
1338 u8 key[16];
1339 u8 tx_mic[8];
1340 u8 rx_mic[8];
1341} __attribute__ ((packed));
1342
1343struct mac_iveiv_entry {
1344 u8 iv[8];
1345} __attribute__ ((packed));
1346
1347/*
1348 * MAC_WCID_ATTRIBUTE:
1349 */
1350#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1351#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1352#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1353#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1354
1355/*
1356 * SHARED_KEY_MODE:
1357 */
1358#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1359#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1360#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1361#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1362#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1363#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1364#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1365#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1366
1367/*
1368 * HOST-MCU communication
1369 */
1370
1371/*
1372 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1373 */
1374#define H2M_MAILBOX_CSR 0x7010
1375#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1376#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1377#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1378#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1379
1380/*
1381 * H2M_MAILBOX_CID:
1382 */
1383#define H2M_MAILBOX_CID 0x7014
1384#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1385#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1386#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1387#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1388
1389/*
1390 * H2M_MAILBOX_STATUS:
1391 */
1392#define H2M_MAILBOX_STATUS 0x701c
1393
1394/*
1395 * H2M_INT_SRC:
1396 */
1397#define H2M_INT_SRC 0x7024
1398
1399/*
1400 * H2M_BBP_AGENT:
1401 */
1402#define H2M_BBP_AGENT 0x7028
1403
1404/*
1405 * MCU_LEDCS: LED control for MCU Mailbox.
1406 */
1407#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1408#define MCU_LEDCS_POLARITY FIELD8(0x01)
1409
1410/*
1411 * HW_CS_CTS_BASE:
1412 * Carrier-sense CTS frame base address.
1413 * It's where mac stores carrier-sense frame for carrier-sense function.
1414 */
1415#define HW_CS_CTS_BASE 0x7700
1416
1417/*
1418 * HW_DFS_CTS_BASE:
1419 * FS CTS frame base address. It's where mac stores CTS frame for DFS.
1420 */
1421#define HW_DFS_CTS_BASE 0x7780
1422
1423/*
1424 * TXRX control registers - base address 0x3000
1425 */
1426
1427/*
1428 * TXRX_CSR1:
1429 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1430 */
1431#define TXRX_CSR1 0x77d0
1432
1433/*
1434 * HW_DEBUG_SETTING_BASE:
1435 * since NULL frame won't be that long (256 byte)
1436 * We steal 16 tail bytes to save debugging settings
1437 */
1438#define HW_DEBUG_SETTING_BASE 0x77f0
1439#define HW_DEBUG_SETTING_BASE2 0x7770
1440
1441/*
1442 * HW_BEACON_BASE
1443 * In order to support maximum 8 MBSS and its maximum length
1444 * is 512 bytes for each beacon
1445 * Three section discontinue memory segments will be used.
1446 * 1. The original region for BCN 0~3
1447 * 2. Extract memory from FCE table for BCN 4~5
1448 * 3. Extract memory from Pair-wise key table for BCN 6~7
1449 * It occupied those memory of wcid 238~253 for BCN 6
1450 * and wcid 222~237 for BCN 7
1451 *
1452 * IMPORTANT NOTE: Not sure why legacy driver does this,
1453 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1454 */
1455#define HW_BEACON_BASE0 0x7800
1456#define HW_BEACON_BASE1 0x7a00
1457#define HW_BEACON_BASE2 0x7c00
1458#define HW_BEACON_BASE3 0x7e00
1459#define HW_BEACON_BASE4 0x7200
1460#define HW_BEACON_BASE5 0x7400
1461#define HW_BEACON_BASE6 0x5dc0
1462#define HW_BEACON_BASE7 0x5bc0
1463
1464#define HW_BEACON_OFFSET(__index) \
1465 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1466 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1467 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1468
1469/*
1470 * 8051 firmware image. 68 * 8051 firmware image.
1471 */ 69 */
1472#define FIRMWARE_RT2870 "rt2870.bin" 70#define FIRMWARE_RT2870 "rt2870.bin"
1473#define FIRMWARE_IMAGE_BASE 0x3000 71#define FIRMWARE_IMAGE_BASE 0x3000
1474 72
1475/* 73/*
1476 * BBP registers.
1477 * The wordsize of the BBP is 8 bits.
1478 */
1479
1480/*
1481 * BBP 1: TX Antenna
1482 */
1483#define BBP1_TX_POWER FIELD8(0x07)
1484#define BBP1_TX_ANTENNA FIELD8(0x18)
1485
1486/*
1487 * BBP 3: RX Antenna
1488 */
1489#define BBP3_RX_ANTENNA FIELD8(0x18)
1490#define BBP3_HT40_PLUS FIELD8(0x20)
1491
1492/*
1493 * BBP 4: Bandwidth
1494 */
1495#define BBP4_TX_BF FIELD8(0x01)
1496#define BBP4_BANDWIDTH FIELD8(0x18)
1497
1498/*
1499 * RFCSR registers
1500 * The wordsize of the RFCSR is 8 bits.
1501 */
1502
1503/*
1504 * RFCSR 6:
1505 */
1506#define RFCSR6_R FIELD8(0x03)
1507
1508/*
1509 * RFCSR 7:
1510 */
1511#define RFCSR7_RF_TUNING FIELD8(0x01)
1512
1513/*
1514 * RFCSR 12:
1515 */
1516#define RFCSR12_TX_POWER FIELD8(0x1f)
1517
1518/*
1519 * RFCSR 22:
1520 */
1521#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1522
1523/*
1524 * RFCSR 23:
1525 */
1526#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1527
1528/*
1529 * RFCSR 30:
1530 */
1531#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1532
1533/*
1534 * RF registers
1535 */
1536
1537/*
1538 * RF 2
1539 */
1540#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1541#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1542#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1543
1544/*
1545 * RF 3
1546 */
1547#define RF3_TXPOWER_G FIELD32(0x00003e00)
1548#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1549#define RF3_TXPOWER_A FIELD32(0x00003c00)
1550
1551/*
1552 * RF 4
1553 */
1554#define RF4_TXPOWER_G FIELD32(0x000007c0)
1555#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1556#define RF4_TXPOWER_A FIELD32(0x00000780)
1557#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1558#define RF4_HT40 FIELD32(0x00200000)
1559
1560/*
1561 * EEPROM content.
1562 * The wordsize of the EEPROM is 16 bits.
1563 */
1564
1565/*
1566 * EEPROM Version
1567 */
1568#define EEPROM_VERSION 0x0001
1569#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1570#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1571
1572/*
1573 * HW MAC address.
1574 */
1575#define EEPROM_MAC_ADDR_0 0x0002
1576#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1577#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1578#define EEPROM_MAC_ADDR_1 0x0003
1579#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1580#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1581#define EEPROM_MAC_ADDR_2 0x0004
1582#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1583#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1584
1585/*
1586 * EEPROM ANTENNA config
1587 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1588 * TXPATH: 1: 1T, 2: 2T
1589 */
1590#define EEPROM_ANTENNA 0x001a
1591#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1592#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1593#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1594
1595/*
1596 * EEPROM NIC config
1597 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1598 */
1599#define EEPROM_NIC 0x001b
1600#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1601#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1602#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1603#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1604#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1605#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1606#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1607#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1608#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1609#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1610
1611/*
1612 * EEPROM frequency
1613 */
1614#define EEPROM_FREQ 0x001d
1615#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1616#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1617#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1618
1619/*
1620 * EEPROM LED
1621 * POLARITY_RDY_G: Polarity RDY_G setting.
1622 * POLARITY_RDY_A: Polarity RDY_A setting.
1623 * POLARITY_ACT: Polarity ACT setting.
1624 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1625 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1626 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1627 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1628 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1629 * LED_MODE: Led mode.
1630 */
1631#define EEPROM_LED1 0x001e
1632#define EEPROM_LED2 0x001f
1633#define EEPROM_LED3 0x0020
1634#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1635#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1636#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1637#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1638#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1639#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1640#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1641#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1642#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1643
1644/*
1645 * EEPROM LNA
1646 */
1647#define EEPROM_LNA 0x0022
1648#define EEPROM_LNA_BG FIELD16(0x00ff)
1649#define EEPROM_LNA_A0 FIELD16(0xff00)
1650
1651/*
1652 * EEPROM RSSI BG offset
1653 */
1654#define EEPROM_RSSI_BG 0x0023
1655#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1656#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1657
1658/*
1659 * EEPROM RSSI BG2 offset
1660 */
1661#define EEPROM_RSSI_BG2 0x0024
1662#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1663#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1664
1665/*
1666 * EEPROM RSSI A offset
1667 */
1668#define EEPROM_RSSI_A 0x0025
1669#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1670#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1671
1672/*
1673 * EEPROM RSSI A2 offset
1674 */
1675#define EEPROM_RSSI_A2 0x0026
1676#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1677#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1678
1679/*
1680 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1681 * This is delta in 40MHZ.
1682 * VALUE: Tx Power dalta value (MAX=4)
1683 * TYPE: 1: Plus the delta value, 0: minus the delta value
1684 * TXPOWER: Enable:
1685 */
1686#define EEPROM_TXPOWER_DELTA 0x0028
1687#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1688#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1689#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1690
1691/*
1692 * EEPROM TXPOWER 802.11BG
1693 */
1694#define EEPROM_TXPOWER_BG1 0x0029
1695#define EEPROM_TXPOWER_BG2 0x0030
1696#define EEPROM_TXPOWER_BG_SIZE 7
1697#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1698#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1699
1700/*
1701 * EEPROM TXPOWER 802.11A
1702 */
1703#define EEPROM_TXPOWER_A1 0x003c
1704#define EEPROM_TXPOWER_A2 0x0053
1705#define EEPROM_TXPOWER_A_SIZE 6
1706#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1707#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1708
1709/*
1710 * EEPROM TXpower byrate: 20MHZ power
1711 */
1712#define EEPROM_TXPOWER_BYRATE 0x006f
1713
1714/*
1715 * EEPROM BBP.
1716 */
1717#define EEPROM_BBP_START 0x0078
1718#define EEPROM_BBP_SIZE 16
1719#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1720#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1721
1722/*
1723 * MCU mailbox commands.
1724 */
1725#define MCU_SLEEP 0x30
1726#define MCU_WAKEUP 0x31
1727#define MCU_RADIO_OFF 0x35
1728#define MCU_CURRENT 0x36
1729#define MCU_LED 0x50
1730#define MCU_LED_STRENGTH 0x51
1731#define MCU_LED_1 0x52
1732#define MCU_LED_2 0x53
1733#define MCU_LED_3 0x54
1734#define MCU_RADAR 0x60
1735#define MCU_BOOT_SIGNAL 0x72
1736#define MCU_BBP_SIGNAL 0x80
1737#define MCU_POWER_SAVE 0x83
1738
1739/*
1740 * MCU mailbox tokens
1741 */
1742#define TOKEN_WAKUP 3
1743
1744/*
1745 * DMA descriptor defines. 74 * DMA descriptor defines.
1746 */ 75 */
1747#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
1748#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) ) 76#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
1749#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) ) 77#define RXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
1750#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
1751#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1752
1753/*
1754 * TX descriptor format for TX, PRIO and Beacon Ring.
1755 */
1756
1757/*
1758 * Word0
1759 */
1760#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
1761
1762/*
1763 * Word1
1764 */
1765#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
1766#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
1767#define TXD_W1_BURST FIELD32(0x00008000)
1768#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
1769#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
1770#define TXD_W1_DMA_DONE FIELD32(0x80000000)
1771
1772/*
1773 * Word2
1774 */
1775#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
1776
1777/*
1778 * Word3
1779 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
1780 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
1781 * 0:MGMT, 1:HCCA 2:EDCA
1782 */
1783#define TXD_W3_WIV FIELD32(0x01000000)
1784#define TXD_W3_QSEL FIELD32(0x06000000)
1785#define TXD_W3_TCO FIELD32(0x20000000)
1786#define TXD_W3_UCO FIELD32(0x40000000)
1787#define TXD_W3_ICO FIELD32(0x80000000)
1788 78
1789/* 79/*
1790 * TX Info structure 80 * TX Info structure
@@ -1807,52 +97,6 @@ struct mac_iveiv_entry {
1807#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000) 97#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
1808 98
1809/* 99/*
1810 * TX WI structure
1811 */
1812
1813/*
1814 * Word0
1815 * FRAG: 1 To inform TKIP engine this is a fragment.
1816 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1817 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1818 * BW: Channel bandwidth 20MHz or 40 MHz
1819 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1820 */
1821#define TXWI_W0_FRAG FIELD32(0x00000001)
1822#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1823#define TXWI_W0_CF_ACK FIELD32(0x00000004)
1824#define TXWI_W0_TS FIELD32(0x00000008)
1825#define TXWI_W0_AMPDU FIELD32(0x00000010)
1826#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1827#define TXWI_W0_TX_OP FIELD32(0x00000300)
1828#define TXWI_W0_MCS FIELD32(0x007f0000)
1829#define TXWI_W0_BW FIELD32(0x00800000)
1830#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1831#define TXWI_W0_STBC FIELD32(0x06000000)
1832#define TXWI_W0_IFS FIELD32(0x08000000)
1833#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1834
1835/*
1836 * Word1
1837 */
1838#define TXWI_W1_ACK FIELD32(0x00000001)
1839#define TXWI_W1_NSEQ FIELD32(0x00000002)
1840#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1841#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1842#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1843#define TXWI_W1_PACKETID FIELD32(0xf0000000)
1844
1845/*
1846 * Word2
1847 */
1848#define TXWI_W2_IV FIELD32(0xffffffff)
1849
1850/*
1851 * Word3
1852 */
1853#define TXWI_W3_EIV FIELD32(0xffffffff)
1854
1855/*
1856 * RX descriptor format for RX Ring. 100 * RX descriptor format for RX Ring.
1857 */ 101 */
1858 102
@@ -1888,64 +132,4 @@ struct mac_iveiv_entry {
1888#define RXD_W0_LAST_AMSDU FIELD32(0x00080000) 132#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
1889#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000) 133#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
1890 134
1891/*
1892 * RX WI structure
1893 */
1894
1895/*
1896 * Word0
1897 */
1898#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1899#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1900#define RXWI_W0_BSSID FIELD32(0x00001c00)
1901#define RXWI_W0_UDF FIELD32(0x0000e000)
1902#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1903#define RXWI_W0_TID FIELD32(0xf0000000)
1904
1905/*
1906 * Word1
1907 */
1908#define RXWI_W1_FRAG FIELD32(0x0000000f)
1909#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1910#define RXWI_W1_MCS FIELD32(0x007f0000)
1911#define RXWI_W1_BW FIELD32(0x00800000)
1912#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1913#define RXWI_W1_STBC FIELD32(0x06000000)
1914#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1915
1916/*
1917 * Word2
1918 */
1919#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1920#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1921#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1922
1923/*
1924 * Word3
1925 */
1926#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1927#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1928
1929/*
1930 * Macros for converting txpower from EEPROM to mac80211 value
1931 * and from mac80211 value to register value.
1932 */
1933#define MIN_G_TXPOWER 0
1934#define MIN_A_TXPOWER -7
1935#define MAX_G_TXPOWER 31
1936#define MAX_A_TXPOWER 15
1937#define DEFAULT_TXPOWER 5
1938
1939#define TXPOWER_G_FROM_DEV(__txpower) \
1940 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1941
1942#define TXPOWER_G_TO_DEV(__txpower) \
1943 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1944
1945#define TXPOWER_A_FROM_DEV(__txpower) \
1946 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1947
1948#define TXPOWER_A_TO_DEV(__txpower) \
1949 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1950
1951#endif /* RT2800USB_H */ 135#endif /* RT2800USB_H */
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index 196de8ab8153..c83dbaefd57a 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -144,6 +144,11 @@ struct avg_val {
144 int avg_weight; 144 int avg_weight;
145}; 145};
146 146
147enum rt2x00_chip_intf {
148 RT2X00_CHIP_INTF_PCI,
149 RT2X00_CHIP_INTF_USB,
150};
151
147/* 152/*
148 * Chipset identification 153 * Chipset identification
149 * The chipset on the device is composed of a RT and RF chip. 154 * The chipset on the device is composed of a RT and RF chip.
@@ -169,6 +174,8 @@ struct rt2x00_chip {
169 174
170 u16 rf; 175 u16 rf;
171 u32 rev; 176 u32 rev;
177
178 enum rt2x00_chip_intf intf;
172}; 179};
173 180
174/* 181/*
@@ -842,9 +849,23 @@ struct rt2x00_dev {
842 * Firmware image. 849 * Firmware image.
843 */ 850 */
844 const struct firmware *fw; 851 const struct firmware *fw;
852
853 /*
854 * Driver specific data.
855 */
856 void *priv;
845}; 857};
846 858
847/* 859/*
860 * Register defines.
861 * Some registers require multiple attempts before success,
862 * in those cases REGISTER_BUSY_COUNT attempts should be
863 * taken with a REGISTER_BUSY_DELAY interval.
864 */
865#define REGISTER_BUSY_COUNT 5
866#define REGISTER_BUSY_DELAY 100
867
868/*
848 * Generic RF access. 869 * Generic RF access.
849 * The RF is being accessed by word index. 870 * The RF is being accessed by word index.
850 */ 871 */
@@ -932,6 +953,28 @@ static inline bool rt2x00_check_rev(const struct rt2x00_chip *chipset,
932 return ((chipset->rev & mask) == rev); 953 return ((chipset->rev & mask) == rev);
933} 954}
934 955
956static inline void rt2x00_set_chip_intf(struct rt2x00_dev *rt2x00dev,
957 enum rt2x00_chip_intf intf)
958{
959 rt2x00dev->chip.intf = intf;
960}
961
962static inline bool rt2x00_intf(const struct rt2x00_chip *chipset,
963 enum rt2x00_chip_intf intf)
964{
965 return (chipset->intf == intf);
966}
967
968static inline bool rt2x00_intf_is_pci(struct rt2x00_dev *rt2x00dev)
969{
970 return rt2x00_intf(&rt2x00dev->chip, RT2X00_CHIP_INTF_PCI);
971}
972
973static inline bool rt2x00_intf_is_usb(struct rt2x00_dev *rt2x00dev)
974{
975 return rt2x00_intf(&rt2x00dev->chip, RT2X00_CHIP_INTF_USB);
976}
977
935/** 978/**
936 * rt2x00queue_map_txskb - Map a skb into DMA for TX purposes. 979 * rt2x00queue_map_txskb - Map a skb into DMA for TX purposes.
937 * @rt2x00dev: Pointer to &struct rt2x00_dev. 980 * @rt2x00dev: Pointer to &struct rt2x00_dev.
diff --git a/drivers/net/wireless/rt2x00/rt2x00leds.h b/drivers/net/wireless/rt2x00/rt2x00leds.h
index 1046977e6a12..8e03c045e037 100644
--- a/drivers/net/wireless/rt2x00/rt2x00leds.h
+++ b/drivers/net/wireless/rt2x00/rt2x00leds.h
@@ -33,8 +33,6 @@ enum led_type {
33 LED_TYPE_QUALITY, 33 LED_TYPE_QUALITY,
34}; 34};
35 35
36#ifdef CONFIG_RT2X00_LIB_LEDS
37
38struct rt2x00_led { 36struct rt2x00_led {
39 struct rt2x00_dev *rt2x00dev; 37 struct rt2x00_dev *rt2x00dev;
40 struct led_classdev led_dev; 38 struct led_classdev led_dev;
@@ -45,6 +43,4 @@ struct rt2x00_led {
45#define LED_REGISTERED ( 1 << 1 ) 43#define LED_REGISTERED ( 1 << 1 )
46}; 44};
47 45
48#endif /* CONFIG_RT2X00_LIB_LEDS */
49
50#endif /* RT2X00LEDS_H */ 46#endif /* RT2X00LEDS_H */
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.h b/drivers/net/wireless/rt2x00/rt2x00pci.h
index 15a12487e04b..ae33eebe9a6f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.h
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.h
@@ -35,15 +35,6 @@
35#define PCI_DEVICE_DATA(__ops) .driver_data = (kernel_ulong_t)(__ops) 35#define PCI_DEVICE_DATA(__ops) .driver_data = (kernel_ulong_t)(__ops)
36 36
37/* 37/*
38 * Register defines.
39 * Some registers require multiple attempts before success,
40 * in those cases REGISTER_BUSY_COUNT attempts should be
41 * taken with a REGISTER_BUSY_DELAY interval.
42 */
43#define REGISTER_BUSY_COUNT 5
44#define REGISTER_BUSY_DELAY 100
45
46/*
47 * Register access. 38 * Register access.
48 */ 39 */
49static inline void rt2x00pci_register_read(struct rt2x00_dev *rt2x00dev, 40static inline void rt2x00pci_register_read(struct rt2x00_dev *rt2x00dev,
@@ -53,10 +44,9 @@ static inline void rt2x00pci_register_read(struct rt2x00_dev *rt2x00dev,
53 *value = readl(rt2x00dev->csr.base + offset); 44 *value = readl(rt2x00dev->csr.base + offset);
54} 45}
55 46
56static inline void 47static inline void rt2x00pci_register_multiread(struct rt2x00_dev *rt2x00dev,
57rt2x00pci_register_multiread(struct rt2x00_dev *rt2x00dev, 48 const unsigned int offset,
58 const unsigned int offset, 49 void *value, const u32 length)
59 void *value, const u16 length)
60{ 50{
61 memcpy_fromio(value, rt2x00dev->csr.base + offset, length); 51 memcpy_fromio(value, rt2x00dev->csr.base + offset, length);
62} 52}
@@ -68,10 +58,10 @@ static inline void rt2x00pci_register_write(struct rt2x00_dev *rt2x00dev,
68 writel(value, rt2x00dev->csr.base + offset); 58 writel(value, rt2x00dev->csr.base + offset);
69} 59}
70 60
71static inline void 61static inline void rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev,
72rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev, 62 const unsigned int offset,
73 const unsigned int offset, 63 const void *value,
74 const void *value, const u16 length) 64 const u32 length)
75{ 65{
76 memcpy_toio(rt2x00dev->csr.base + offset, value, length); 66 memcpy_toio(rt2x00dev->csr.base + offset, value, length);
77} 67}
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index f02b48a90593..c9cbdaa1073f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -160,7 +160,7 @@ EXPORT_SYMBOL_GPL(rt2x00usb_vendor_request_large_buff);
160 160
161int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev, 161int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
162 const unsigned int offset, 162 const unsigned int offset,
163 struct rt2x00_field32 field, 163 const struct rt2x00_field32 field,
164 u32 *reg) 164 u32 *reg)
165{ 165{
166 unsigned int i; 166 unsigned int i;
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.h b/drivers/net/wireless/rt2x00/rt2x00usb.h
index bd2d59c85f1b..9943e428bc21 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.h
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.h
@@ -39,17 +39,11 @@
39#define USB_DEVICE_DATA(__ops) .driver_info = (kernel_ulong_t)(__ops) 39#define USB_DEVICE_DATA(__ops) .driver_info = (kernel_ulong_t)(__ops)
40 40
41/* 41/*
42 * Register defines.
43 * Some registers require multiple attempts before success,
44 * in those cases REGISTER_BUSY_COUNT attempts should be
45 * taken with a REGISTER_BUSY_DELAY interval.
46 * For USB vendor requests we need to pass a timeout 42 * For USB vendor requests we need to pass a timeout
47 * time in ms, for this we use the REGISTER_TIMEOUT, 43 * time in ms, for this we use the REGISTER_TIMEOUT,
48 * however when loading firmware a higher value is 44 * however when loading firmware a higher value is
49 * required. In that case we use the REGISTER_TIMEOUT_FIRMWARE. 45 * required. In that case we use the REGISTER_TIMEOUT_FIRMWARE.
50 */ 46 */
51#define REGISTER_BUSY_COUNT 5
52#define REGISTER_BUSY_DELAY 100
53#define REGISTER_TIMEOUT 500 47#define REGISTER_TIMEOUT 500
54#define REGISTER_TIMEOUT_FIRMWARE 1000 48#define REGISTER_TIMEOUT_FIRMWARE 1000
55 49
@@ -232,7 +226,7 @@ static inline int rt2x00usb_eeprom_read(struct rt2x00_dev *rt2x00dev,
232} 226}
233 227
234/** 228/**
235 * rt2x00usb_regbusy_read - Read 32bit register word 229 * rt2x00usb_register_read - Read 32bit register word
236 * @rt2x00dev: Device pointer, see &struct rt2x00_dev. 230 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
237 * @offset: Register offset 231 * @offset: Register offset
238 * @value: Pointer to where register contents should be stored 232 * @value: Pointer to where register contents should be stored
@@ -340,12 +334,13 @@ static inline void rt2x00usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
340 * through rt2x00usb_vendor_request_buff(). 334 * through rt2x00usb_vendor_request_buff().
341 */ 335 */
342static inline void rt2x00usb_register_multiwrite(struct rt2x00_dev *rt2x00dev, 336static inline void rt2x00usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
343 const unsigned int offset, 337 const unsigned int offset,
344 void *value, const u32 length) 338 const void *value,
339 const u32 length)
345{ 340{
346 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE, 341 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
347 USB_VENDOR_REQUEST_OUT, offset, 342 USB_VENDOR_REQUEST_OUT, offset,
348 value, length, 343 (void *)value, length,
349 REGISTER_TIMEOUT32(length)); 344 REGISTER_TIMEOUT32(length));
350} 345}
351 346
@@ -364,7 +359,7 @@ static inline void rt2x00usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
364 */ 359 */
365int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev, 360int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
366 const unsigned int offset, 361 const unsigned int offset,
367 struct rt2x00_field32 field, 362 const struct rt2x00_field32 field,
368 u32 *reg); 363 u32 *reg);
369 364
370/* 365/*
diff --git a/drivers/net/wireless/rtl818x/rtl8187.h b/drivers/net/wireless/rtl818x/rtl8187.h
index bf9175a8c1f4..abb4907cf296 100644
--- a/drivers/net/wireless/rtl818x/rtl8187.h
+++ b/drivers/net/wireless/rtl818x/rtl8187.h
@@ -119,7 +119,6 @@ struct rtl8187_priv {
119 } hw_rev; 119 } hw_rev;
120 struct sk_buff_head rx_queue; 120 struct sk_buff_head rx_queue;
121 u8 signal; 121 u8 signal;
122 u8 quality;
123 u8 noise; 122 u8 noise;
124 u8 slot_time; 123 u8 slot_time;
125 u8 aifsn[4]; 124 u8 aifsn[4];
diff --git a/drivers/net/wireless/rtl818x/rtl8187_dev.c b/drivers/net/wireless/rtl818x/rtl8187_dev.c
index 2017ccc00145..76973b8c7099 100644
--- a/drivers/net/wireless/rtl818x/rtl8187_dev.c
+++ b/drivers/net/wireless/rtl818x/rtl8187_dev.c
@@ -320,7 +320,6 @@ static void rtl8187_rx_cb(struct urb *urb)
320 struct ieee80211_rx_status rx_status = { 0 }; 320 struct ieee80211_rx_status rx_status = { 0 };
321 int rate, signal; 321 int rate, signal;
322 u32 flags; 322 u32 flags;
323 u32 quality;
324 unsigned long f; 323 unsigned long f;
325 324
326 spin_lock_irqsave(&priv->rx_queue.lock, f); 325 spin_lock_irqsave(&priv->rx_queue.lock, f);
@@ -338,10 +337,9 @@ static void rtl8187_rx_cb(struct urb *urb)
338 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr)); 337 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
339 flags = le32_to_cpu(hdr->flags); 338 flags = le32_to_cpu(hdr->flags);
340 /* As with the RTL8187B below, the AGC is used to calculate 339 /* As with the RTL8187B below, the AGC is used to calculate
341 * signal strength and quality. In this case, the scaling 340 * signal strength. In this case, the scaling
342 * constants are derived from the output of p54usb. 341 * constants are derived from the output of p54usb.
343 */ 342 */
344 quality = 130 - ((41 * hdr->agc) >> 6);
345 signal = -4 - ((27 * hdr->agc) >> 6); 343 signal = -4 - ((27 * hdr->agc) >> 6);
346 rx_status.antenna = (hdr->signal >> 7) & 1; 344 rx_status.antenna = (hdr->signal >> 7) & 1;
347 rx_status.mactime = le64_to_cpu(hdr->mac_time); 345 rx_status.mactime = le64_to_cpu(hdr->mac_time);
@@ -354,23 +352,18 @@ static void rtl8187_rx_cb(struct urb *urb)
354 * In testing, none of these quantities show qualitative 352 * In testing, none of these quantities show qualitative
355 * agreement with AP signal strength, except for the AGC, 353 * agreement with AP signal strength, except for the AGC,
356 * which is inversely proportional to the strength of the 354 * which is inversely proportional to the strength of the
357 * signal. In the following, the quality and signal strength 355 * signal. In the following, the signal strength
358 * are derived from the AGC. The arbitrary scaling constants 356 * is derived from the AGC. The arbitrary scaling constants
359 * are chosen to make the results close to the values obtained 357 * are chosen to make the results close to the values obtained
360 * for a BCM4312 using b43 as the driver. The noise is ignored 358 * for a BCM4312 using b43 as the driver. The noise is ignored
361 * for now. 359 * for now.
362 */ 360 */
363 flags = le32_to_cpu(hdr->flags); 361 flags = le32_to_cpu(hdr->flags);
364 quality = 170 - hdr->agc;
365 signal = 14 - hdr->agc / 2; 362 signal = 14 - hdr->agc / 2;
366 rx_status.antenna = (hdr->rssi >> 7) & 1; 363 rx_status.antenna = (hdr->rssi >> 7) & 1;
367 rx_status.mactime = le64_to_cpu(hdr->mac_time); 364 rx_status.mactime = le64_to_cpu(hdr->mac_time);
368 } 365 }
369 366
370 if (quality > 100)
371 quality = 100;
372 rx_status.qual = quality;
373 priv->quality = quality;
374 rx_status.signal = signal; 367 rx_status.signal = signal;
375 priv->signal = signal; 368 priv->signal = signal;
376 rate = (flags >> 20) & 0xF; 369 rate = (flags >> 20) & 0xF;
diff --git a/drivers/net/wireless/strip.c b/drivers/net/wireless/strip.c
deleted file mode 100644
index 698aade79d40..000000000000
--- a/drivers/net/wireless/strip.c
+++ /dev/null
@@ -1,2822 +0,0 @@
1/*
2 * Copyright 1996 The Board of Trustees of The Leland Stanford
3 * Junior University. All Rights Reserved.
4 *
5 * Permission to use, copy, modify, and distribute this
6 * software and its documentation for any purpose and without
7 * fee is hereby granted, provided that the above copyright
8 * notice appear in all copies. Stanford University
9 * makes no representations about the suitability of this
10 * software for any purpose. It is provided "as is" without
11 * express or implied warranty.
12 *
13 * strip.c This module implements Starmode Radio IP (STRIP)
14 * for kernel-based devices like TTY. It interfaces between a
15 * raw TTY, and the kernel's INET protocol layers (via DDI).
16 *
17 * Version: @(#)strip.c 1.3 July 1997
18 *
19 * Author: Stuart Cheshire <cheshire@cs.stanford.edu>
20 *
21 * Fixes: v0.9 12th Feb 1996 (SC)
22 * New byte stuffing (2+6 run-length encoding)
23 * New watchdog timer task
24 * New Protocol key (SIP0)
25 *
26 * v0.9.1 3rd March 1996 (SC)
27 * Changed to dynamic device allocation -- no more compile
28 * time (or boot time) limit on the number of STRIP devices.
29 *
30 * v0.9.2 13th March 1996 (SC)
31 * Uses arp cache lookups (but doesn't send arp packets yet)
32 *
33 * v0.9.3 17th April 1996 (SC)
34 * Fixed bug where STR_ERROR flag was getting set unneccessarily
35 * (causing otherwise good packets to be unneccessarily dropped)
36 *
37 * v0.9.4 27th April 1996 (SC)
38 * First attempt at using "&COMMAND" Starmode AT commands
39 *
40 * v0.9.5 29th May 1996 (SC)
41 * First attempt at sending (unicast) ARP packets
42 *
43 * v0.9.6 5th June 1996 (Elliot)
44 * Put "message level" tags in every "printk" statement
45 *
46 * v0.9.7 13th June 1996 (laik)
47 * Added support for the /proc fs
48 *
49 * v0.9.8 July 1996 (Mema)
50 * Added packet logging
51 *
52 * v1.0 November 1996 (SC)
53 * Fixed (severe) memory leaks in the /proc fs code
54 * Fixed race conditions in the logging code
55 *
56 * v1.1 January 1997 (SC)
57 * Deleted packet logging (use tcpdump instead)
58 * Added support for Metricom Firmware v204 features
59 * (like message checksums)
60 *
61 * v1.2 January 1997 (SC)
62 * Put portables list back in
63 *
64 * v1.3 July 1997 (SC)
65 * Made STRIP driver set the radio's baud rate automatically.
66 * It is no longer necessarily to manually set the radio's
67 * rate permanently to 115200 -- the driver handles setting
68 * the rate automatically.
69 */
70
71#ifdef MODULE
72static const char StripVersion[] = "1.3A-STUART.CHESHIRE-MODULAR";
73#else
74static const char StripVersion[] = "1.3A-STUART.CHESHIRE";
75#endif
76
77#define TICKLE_TIMERS 0
78#define EXT_COUNTERS 1
79
80
81/************************************************************************/
82/* Header files */
83
84#include <linux/kernel.h>
85#include <linux/module.h>
86#include <linux/init.h>
87#include <linux/bitops.h>
88#include <asm/system.h>
89#include <asm/uaccess.h>
90
91# include <linux/ctype.h>
92#include <linux/string.h>
93#include <linux/mm.h>
94#include <linux/interrupt.h>
95#include <linux/in.h>
96#include <linux/tty.h>
97#include <linux/errno.h>
98#include <linux/netdevice.h>
99#include <linux/inetdevice.h>
100#include <linux/etherdevice.h>
101#include <linux/skbuff.h>
102#include <linux/if_arp.h>
103#include <linux/if_strip.h>
104#include <linux/proc_fs.h>
105#include <linux/seq_file.h>
106#include <linux/serial.h>
107#include <linux/serialP.h>
108#include <linux/rcupdate.h>
109#include <linux/compat.h>
110#include <net/arp.h>
111#include <net/net_namespace.h>
112
113#include <linux/ip.h>
114#include <linux/tcp.h>
115#include <linux/time.h>
116#include <linux/jiffies.h>
117
118/************************************************************************/
119/* Useful structures and definitions */
120
121/*
122 * A MetricomKey identifies the protocol being carried inside a Metricom
123 * Starmode packet.
124 */
125
126typedef union {
127 __u8 c[4];
128 __u32 l;
129} MetricomKey;
130
131/*
132 * An IP address can be viewed as four bytes in memory (which is what it is) or as
133 * a single 32-bit long (which is convenient for assignment, equality testing etc.)
134 */
135
136typedef union {
137 __u8 b[4];
138 __u32 l;
139} IPaddr;
140
141/*
142 * A MetricomAddressString is used to hold a printable representation of
143 * a Metricom address.
144 */
145
146typedef struct {
147 __u8 c[24];
148} MetricomAddressString;
149
150/* Encapsulation can expand packet of size x to 65/64x + 1
151 * Sent packet looks like "<CR>*<address>*<key><encaps payload><CR>"
152 * 1 1 1-18 1 4 ? 1
153 * eg. <CR>*0000-1234*SIP0<encaps payload><CR>
154 * We allow 31 bytes for the stars, the key, the address and the <CR>s
155 */
156#define STRIP_ENCAP_SIZE(X) (32 + (X)*65L/64L)
157
158/*
159 * A STRIP_Header is never really sent over the radio, but making a dummy
160 * header for internal use within the kernel that looks like an Ethernet
161 * header makes certain other software happier. For example, tcpdump
162 * already understands Ethernet headers.
163 */
164
165typedef struct {
166 MetricomAddress dst_addr; /* Destination address, e.g. "0000-1234" */
167 MetricomAddress src_addr; /* Source address, e.g. "0000-5678" */
168 unsigned short protocol; /* The protocol type, using Ethernet codes */
169} STRIP_Header;
170
171typedef struct {
172 char c[60];
173} MetricomNode;
174
175#define NODE_TABLE_SIZE 32
176typedef struct {
177 struct timeval timestamp;
178 int num_nodes;
179 MetricomNode node[NODE_TABLE_SIZE];
180} MetricomNodeTable;
181
182enum { FALSE = 0, TRUE = 1 };
183
184/*
185 * Holds the radio's firmware version.
186 */
187typedef struct {
188 char c[50];
189} FirmwareVersion;
190
191/*
192 * Holds the radio's serial number.
193 */
194typedef struct {
195 char c[18];
196} SerialNumber;
197
198/*
199 * Holds the radio's battery voltage.
200 */
201typedef struct {
202 char c[11];
203} BatteryVoltage;
204
205typedef struct {
206 char c[8];
207} char8;
208
209enum {
210 NoStructure = 0, /* Really old firmware */
211 StructuredMessages = 1, /* Parsable AT response msgs */
212 ChecksummedMessages = 2 /* Parsable AT response msgs with checksums */
213};
214
215struct strip {
216 int magic;
217 /*
218 * These are pointers to the malloc()ed frame buffers.
219 */
220
221 unsigned char *rx_buff; /* buffer for received IP packet */
222 unsigned char *sx_buff; /* buffer for received serial data */
223 int sx_count; /* received serial data counter */
224 int sx_size; /* Serial buffer size */
225 unsigned char *tx_buff; /* transmitter buffer */
226 unsigned char *tx_head; /* pointer to next byte to XMIT */
227 int tx_left; /* bytes left in XMIT queue */
228 int tx_size; /* Serial buffer size */
229
230 /*
231 * STRIP interface statistics.
232 */
233
234 unsigned long rx_packets; /* inbound frames counter */
235 unsigned long tx_packets; /* outbound frames counter */
236 unsigned long rx_errors; /* Parity, etc. errors */
237 unsigned long tx_errors; /* Planned stuff */
238 unsigned long rx_dropped; /* No memory for skb */
239 unsigned long tx_dropped; /* When MTU change */
240 unsigned long rx_over_errors; /* Frame bigger than STRIP buf. */
241
242 unsigned long pps_timer; /* Timer to determine pps */
243 unsigned long rx_pps_count; /* Counter to determine pps */
244 unsigned long tx_pps_count; /* Counter to determine pps */
245 unsigned long sx_pps_count; /* Counter to determine pps */
246 unsigned long rx_average_pps; /* rx packets per second * 8 */
247 unsigned long tx_average_pps; /* tx packets per second * 8 */
248 unsigned long sx_average_pps; /* sent packets per second * 8 */
249
250#ifdef EXT_COUNTERS
251 unsigned long rx_bytes; /* total received bytes */
252 unsigned long tx_bytes; /* total received bytes */
253 unsigned long rx_rbytes; /* bytes thru radio i/f */
254 unsigned long tx_rbytes; /* bytes thru radio i/f */
255 unsigned long rx_sbytes; /* tot bytes thru serial i/f */
256 unsigned long tx_sbytes; /* tot bytes thru serial i/f */
257 unsigned long rx_ebytes; /* tot stat/err bytes */
258 unsigned long tx_ebytes; /* tot stat/err bytes */
259#endif
260
261 /*
262 * Internal variables.
263 */
264
265 struct list_head list; /* Linked list of devices */
266
267 int discard; /* Set if serial error */
268 int working; /* Is radio working correctly? */
269 int firmware_level; /* Message structuring level */
270 int next_command; /* Next periodic command */
271 unsigned int user_baud; /* The user-selected baud rate */
272 int mtu; /* Our mtu (to spot changes!) */
273 long watchdog_doprobe; /* Next time to test the radio */
274 long watchdog_doreset; /* Time to do next reset */
275 long gratuitous_arp; /* Time to send next ARP refresh */
276 long arp_interval; /* Next ARP interval */
277 struct timer_list idle_timer; /* For periodic wakeup calls */
278 MetricomAddress true_dev_addr; /* True address of radio */
279 int manual_dev_addr; /* Hack: See note below */
280
281 FirmwareVersion firmware_version; /* The radio's firmware version */
282 SerialNumber serial_number; /* The radio's serial number */
283 BatteryVoltage battery_voltage; /* The radio's battery voltage */
284
285 /*
286 * Other useful structures.
287 */
288
289 struct tty_struct *tty; /* ptr to TTY structure */
290 struct net_device *dev; /* Our device structure */
291
292 /*
293 * Neighbour radio records
294 */
295
296 MetricomNodeTable portables;
297 MetricomNodeTable poletops;
298};
299
300/*
301 * Note: manual_dev_addr hack
302 *
303 * It is not possible to change the hardware address of a Metricom radio,
304 * or to send packets with a user-specified hardware source address, thus
305 * trying to manually set a hardware source address is a questionable
306 * thing to do. However, if the user *does* manually set the hardware
307 * source address of a STRIP interface, then the kernel will believe it,
308 * and use it in certain places. For example, the hardware address listed
309 * by ifconfig will be the manual address, not the true one.
310 * (Both addresses are listed in /proc/net/strip.)
311 * Also, ARP packets will be sent out giving the user-specified address as
312 * the source address, not the real address. This is dangerous, because
313 * it means you won't receive any replies -- the ARP replies will go to
314 * the specified address, which will be some other radio. The case where
315 * this is useful is when that other radio is also connected to the same
316 * machine. This allows you to connect a pair of radios to one machine,
317 * and to use one exclusively for inbound traffic, and the other
318 * exclusively for outbound traffic. Pretty neat, huh?
319 *
320 * Here's the full procedure to set this up:
321 *
322 * 1. "slattach" two interfaces, e.g. st0 for outgoing packets,
323 * and st1 for incoming packets
324 *
325 * 2. "ifconfig" st0 (outbound radio) to have the hardware address
326 * which is the real hardware address of st1 (inbound radio).
327 * Now when it sends out packets, it will masquerade as st1, and
328 * replies will be sent to that radio, which is exactly what we want.
329 *
330 * 3. Set the route table entry ("route add default ..." or
331 * "route add -net ...", as appropriate) to send packets via the st0
332 * interface (outbound radio). Do not add any route which sends packets
333 * out via the st1 interface -- that radio is for inbound traffic only.
334 *
335 * 4. "ifconfig" st1 (inbound radio) to have hardware address zero.
336 * This tells the STRIP driver to "shut down" that interface and not
337 * send any packets through it. In particular, it stops sending the
338 * periodic gratuitous ARP packets that a STRIP interface normally sends.
339 * Also, when packets arrive on that interface, it will search the
340 * interface list to see if there is another interface who's manual
341 * hardware address matches its own real address (i.e. st0 in this
342 * example) and if so it will transfer ownership of the skbuff to
343 * that interface, so that it looks to the kernel as if the packet
344 * arrived on that interface. This is necessary because when the
345 * kernel sends an ARP packet on st0, it expects to get a reply on
346 * st0, and if it sees the reply come from st1 then it will ignore
347 * it (to be accurate, it puts the entry in the ARP table, but
348 * labelled in such a way that st0 can't use it).
349 *
350 * Thanks to Petros Maniatis for coming up with the idea of splitting
351 * inbound and outbound traffic between two interfaces, which turned
352 * out to be really easy to implement, even if it is a bit of a hack.
353 *
354 * Having set a manual address on an interface, you can restore it
355 * to automatic operation (where the address is automatically kept
356 * consistent with the real address of the radio) by setting a manual
357 * address of all ones, e.g. "ifconfig st0 hw strip FFFFFFFFFFFF"
358 * This 'turns off' manual override mode for the device address.
359 *
360 * Note: The IEEE 802 headers reported in tcpdump will show the *real*
361 * radio addresses the packets were sent and received from, so that you
362 * can see what is really going on with packets, and which interfaces
363 * they are really going through.
364 */
365
366
367/************************************************************************/
368/* Constants */
369
370/*
371 * CommandString1 works on all radios
372 * Other CommandStrings are only used with firmware that provides structured responses.
373 *
374 * ats319=1 Enables Info message for node additions and deletions
375 * ats319=2 Enables Info message for a new best node
376 * ats319=4 Enables checksums
377 * ats319=8 Enables ACK messages
378 */
379
380static const int MaxCommandStringLength = 32;
381static const int CompatibilityCommand = 1;
382
383static const char CommandString0[] = "*&COMMAND*ATS319=7"; /* Turn on checksums & info messages */
384static const char CommandString1[] = "*&COMMAND*ATS305?"; /* Query radio name */
385static const char CommandString2[] = "*&COMMAND*ATS325?"; /* Query battery voltage */
386static const char CommandString3[] = "*&COMMAND*ATS300?"; /* Query version information */
387static const char CommandString4[] = "*&COMMAND*ATS311?"; /* Query poletop list */
388static const char CommandString5[] = "*&COMMAND*AT~LA"; /* Query portables list */
389typedef struct {
390 const char *string;
391 long length;
392} StringDescriptor;
393
394static const StringDescriptor CommandString[] = {
395 {CommandString0, sizeof(CommandString0) - 1},
396 {CommandString1, sizeof(CommandString1) - 1},
397 {CommandString2, sizeof(CommandString2) - 1},
398 {CommandString3, sizeof(CommandString3) - 1},
399 {CommandString4, sizeof(CommandString4) - 1},
400 {CommandString5, sizeof(CommandString5) - 1}
401};
402
403#define GOT_ALL_RADIO_INFO(S) \
404 ((S)->firmware_version.c[0] && \
405 (S)->battery_voltage.c[0] && \
406 memcmp(&(S)->true_dev_addr, zero_address.c, sizeof(zero_address)))
407
408static const char hextable[16] = "0123456789ABCDEF";
409
410static const MetricomAddress zero_address;
411static const MetricomAddress broadcast_address =
412 { {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF} };
413
414static const MetricomKey SIP0Key = { "SIP0" };
415static const MetricomKey ARP0Key = { "ARP0" };
416static const MetricomKey ATR_Key = { "ATR " };
417static const MetricomKey ACK_Key = { "ACK_" };
418static const MetricomKey INF_Key = { "INF_" };
419static const MetricomKey ERR_Key = { "ERR_" };
420
421static const long MaxARPInterval = 60 * HZ; /* One minute */
422
423/*
424 * Maximum Starmode packet length is 1183 bytes. Allowing 4 bytes for
425 * protocol key, 4 bytes for checksum, one byte for CR, and 65/64 expansion
426 * for STRIP encoding, that translates to a maximum payload MTU of 1155.
427 * Note: A standard NFS 1K data packet is a total of 0x480 (1152) bytes
428 * long, including IP header, UDP header, and NFS header. Setting the STRIP
429 * MTU to 1152 allows us to send default sized NFS packets without fragmentation.
430 */
431static const unsigned short MAX_SEND_MTU = 1152;
432static const unsigned short MAX_RECV_MTU = 1500; /* Hoping for Ethernet sized packets in the future! */
433static const unsigned short DEFAULT_STRIP_MTU = 1152;
434static const int STRIP_MAGIC = 0x5303;
435static const long LongTime = 0x7FFFFFFF;
436
437/************************************************************************/
438/* Global variables */
439
440static LIST_HEAD(strip_list);
441static DEFINE_SPINLOCK(strip_lock);
442
443/************************************************************************/
444/* Macros */
445
446/* Returns TRUE if text T begins with prefix P */
447#define has_prefix(T,L,P) (((L) >= sizeof(P)-1) && !strncmp((T), (P), sizeof(P)-1))
448
449/* Returns TRUE if text T of length L is equal to string S */
450#define text_equal(T,L,S) (((L) == sizeof(S)-1) && !strncmp((T), (S), sizeof(S)-1))
451
452#define READHEX(X) ((X)>='0' && (X)<='9' ? (X)-'0' : \
453 (X)>='a' && (X)<='f' ? (X)-'a'+10 : \
454 (X)>='A' && (X)<='F' ? (X)-'A'+10 : 0 )
455
456#define READHEX16(X) ((__u16)(READHEX(X)))
457
458#define READDEC(X) ((X)>='0' && (X)<='9' ? (X)-'0' : 0)
459
460#define ARRAY_END(X) (&((X)[ARRAY_SIZE(X)]))
461
462#define JIFFIE_TO_SEC(X) ((X) / HZ)
463
464
465/************************************************************************/
466/* Utility routines */
467
468static int arp_query(unsigned char *haddr, u32 paddr,
469 struct net_device *dev)
470{
471 struct neighbour *neighbor_entry;
472 int ret = 0;
473
474 neighbor_entry = neigh_lookup(&arp_tbl, &paddr, dev);
475
476 if (neighbor_entry != NULL) {
477 neighbor_entry->used = jiffies;
478 if (neighbor_entry->nud_state & NUD_VALID) {
479 memcpy(haddr, neighbor_entry->ha, dev->addr_len);
480 ret = 1;
481 }
482 neigh_release(neighbor_entry);
483 }
484 return ret;
485}
486
487static void DumpData(char *msg, struct strip *strip_info, __u8 * ptr,
488 __u8 * end)
489{
490 static const int MAX_DumpData = 80;
491 __u8 pkt_text[MAX_DumpData], *p = pkt_text;
492
493 *p++ = '\"';
494
495 while (ptr < end && p < &pkt_text[MAX_DumpData - 4]) {
496 if (*ptr == '\\') {
497 *p++ = '\\';
498 *p++ = '\\';
499 } else {
500 if (*ptr >= 32 && *ptr <= 126) {
501 *p++ = *ptr;
502 } else {
503 sprintf(p, "\\%02X", *ptr);
504 p += 3;
505 }
506 }
507 ptr++;
508 }
509
510 if (ptr == end)
511 *p++ = '\"';
512 *p++ = 0;
513
514 printk(KERN_INFO "%s: %-13s%s\n", strip_info->dev->name, msg, pkt_text);
515}
516
517
518/************************************************************************/
519/* Byte stuffing/unstuffing routines */
520
521/* Stuffing scheme:
522 * 00 Unused (reserved character)
523 * 01-3F Run of 2-64 different characters
524 * 40-7F Run of 1-64 different characters plus a single zero at the end
525 * 80-BF Run of 1-64 of the same character
526 * C0-FF Run of 1-64 zeroes (ASCII 0)
527 */
528
529typedef enum {
530 Stuff_Diff = 0x00,
531 Stuff_DiffZero = 0x40,
532 Stuff_Same = 0x80,
533 Stuff_Zero = 0xC0,
534 Stuff_NoCode = 0xFF, /* Special code, meaning no code selected */
535
536 Stuff_CodeMask = 0xC0,
537 Stuff_CountMask = 0x3F,
538 Stuff_MaxCount = 0x3F,
539 Stuff_Magic = 0x0D /* The value we are eliminating */
540} StuffingCode;
541
542/* StuffData encodes the data starting at "src" for "length" bytes.
543 * It writes it to the buffer pointed to by "dst" (which must be at least
544 * as long as 1 + 65/64 of the input length). The output may be up to 1.6%
545 * larger than the input for pathological input, but will usually be smaller.
546 * StuffData returns the new value of the dst pointer as its result.
547 * "code_ptr_ptr" points to a "__u8 *" which is used to hold encoding state
548 * between calls, allowing an encoded packet to be incrementally built up
549 * from small parts. On the first call, the "__u8 *" pointed to should be
550 * initialized to NULL; between subsequent calls the calling routine should
551 * leave the value alone and simply pass it back unchanged so that the
552 * encoder can recover its current state.
553 */
554
555#define StuffData_FinishBlock(X) \
556(*code_ptr = (X) ^ Stuff_Magic, code = Stuff_NoCode)
557
558static __u8 *StuffData(__u8 * src, __u32 length, __u8 * dst,
559 __u8 ** code_ptr_ptr)
560{
561 __u8 *end = src + length;
562 __u8 *code_ptr = *code_ptr_ptr;
563 __u8 code = Stuff_NoCode, count = 0;
564
565 if (!length)
566 return (dst);
567
568 if (code_ptr) {
569 /*
570 * Recover state from last call, if applicable
571 */
572 code = (*code_ptr ^ Stuff_Magic) & Stuff_CodeMask;
573 count = (*code_ptr ^ Stuff_Magic) & Stuff_CountMask;
574 }
575
576 while (src < end) {
577 switch (code) {
578 /* Stuff_NoCode: If no current code, select one */
579 case Stuff_NoCode:
580 /* Record where we're going to put this code */
581 code_ptr = dst++;
582 count = 0; /* Reset the count (zero means one instance) */
583 /* Tentatively start a new block */
584 if (*src == 0) {
585 code = Stuff_Zero;
586 src++;
587 } else {
588 code = Stuff_Same;
589 *dst++ = *src++ ^ Stuff_Magic;
590 }
591 /* Note: We optimistically assume run of same -- */
592 /* which will be fixed later in Stuff_Same */
593 /* if it turns out not to be true. */
594 break;
595
596 /* Stuff_Zero: We already have at least one zero encoded */
597 case Stuff_Zero:
598 /* If another zero, count it, else finish this code block */
599 if (*src == 0) {
600 count++;
601 src++;
602 } else {
603 StuffData_FinishBlock(Stuff_Zero + count);
604 }
605 break;
606
607 /* Stuff_Same: We already have at least one byte encoded */
608 case Stuff_Same:
609 /* If another one the same, count it */
610 if ((*src ^ Stuff_Magic) == code_ptr[1]) {
611 count++;
612 src++;
613 break;
614 }
615 /* else, this byte does not match this block. */
616 /* If we already have two or more bytes encoded, finish this code block */
617 if (count) {
618 StuffData_FinishBlock(Stuff_Same + count);
619 break;
620 }
621 /* else, we only have one so far, so switch to Stuff_Diff code */
622 code = Stuff_Diff;
623 /* and fall through to Stuff_Diff case below
624 * Note cunning cleverness here: case Stuff_Diff compares
625 * the current character with the previous two to see if it
626 * has a run of three the same. Won't this be an error if
627 * there aren't two previous characters stored to compare with?
628 * No. Because we know the current character is *not* the same
629 * as the previous one, the first test below will necessarily
630 * fail and the send half of the "if" won't be executed.
631 */
632
633 /* Stuff_Diff: We have at least two *different* bytes encoded */
634 case Stuff_Diff:
635 /* If this is a zero, must encode a Stuff_DiffZero, and begin a new block */
636 if (*src == 0) {
637 StuffData_FinishBlock(Stuff_DiffZero +
638 count);
639 }
640 /* else, if we have three in a row, it is worth starting a Stuff_Same block */
641 else if ((*src ^ Stuff_Magic) == dst[-1]
642 && dst[-1] == dst[-2]) {
643 /* Back off the last two characters we encoded */
644 code += count - 2;
645 /* Note: "Stuff_Diff + 0" is an illegal code */
646 if (code == Stuff_Diff + 0) {
647 code = Stuff_Same + 0;
648 }
649 StuffData_FinishBlock(code);
650 code_ptr = dst - 2;
651 /* dst[-1] already holds the correct value */
652 count = 2; /* 2 means three bytes encoded */
653 code = Stuff_Same;
654 }
655 /* else, another different byte, so add it to the block */
656 else {
657 *dst++ = *src ^ Stuff_Magic;
658 count++;
659 }
660 src++; /* Consume the byte */
661 break;
662 }
663 if (count == Stuff_MaxCount) {
664 StuffData_FinishBlock(code + count);
665 }
666 }
667 if (code == Stuff_NoCode) {
668 *code_ptr_ptr = NULL;
669 } else {
670 *code_ptr_ptr = code_ptr;
671 StuffData_FinishBlock(code + count);
672 }
673 return (dst);
674}
675
676/*
677 * UnStuffData decodes the data at "src", up to (but not including) "end".
678 * It writes the decoded data into the buffer pointed to by "dst", up to a
679 * maximum of "dst_length", and returns the new value of "src" so that a
680 * follow-on call can read more data, continuing from where the first left off.
681 *
682 * There are three types of results:
683 * 1. The source data runs out before extracting "dst_length" bytes:
684 * UnStuffData returns NULL to indicate failure.
685 * 2. The source data produces exactly "dst_length" bytes:
686 * UnStuffData returns new_src = end to indicate that all bytes were consumed.
687 * 3. "dst_length" bytes are extracted, with more remaining.
688 * UnStuffData returns new_src < end to indicate that there are more bytes
689 * to be read.
690 *
691 * Note: The decoding may be destructive, in that it may alter the source
692 * data in the process of decoding it (this is necessary to allow a follow-on
693 * call to resume correctly).
694 */
695
696static __u8 *UnStuffData(__u8 * src, __u8 * end, __u8 * dst,
697 __u32 dst_length)
698{
699 __u8 *dst_end = dst + dst_length;
700 /* Sanity check */
701 if (!src || !end || !dst || !dst_length)
702 return (NULL);
703 while (src < end && dst < dst_end) {
704 int count = (*src ^ Stuff_Magic) & Stuff_CountMask;
705 switch ((*src ^ Stuff_Magic) & Stuff_CodeMask) {
706 case Stuff_Diff:
707 if (src + 1 + count >= end)
708 return (NULL);
709 do {
710 *dst++ = *++src ^ Stuff_Magic;
711 }
712 while (--count >= 0 && dst < dst_end);
713 if (count < 0)
714 src += 1;
715 else {
716 if (count == 0)
717 *src = Stuff_Same ^ Stuff_Magic;
718 else
719 *src =
720 (Stuff_Diff +
721 count) ^ Stuff_Magic;
722 }
723 break;
724 case Stuff_DiffZero:
725 if (src + 1 + count >= end)
726 return (NULL);
727 do {
728 *dst++ = *++src ^ Stuff_Magic;
729 }
730 while (--count >= 0 && dst < dst_end);
731 if (count < 0)
732 *src = Stuff_Zero ^ Stuff_Magic;
733 else
734 *src =
735 (Stuff_DiffZero + count) ^ Stuff_Magic;
736 break;
737 case Stuff_Same:
738 if (src + 1 >= end)
739 return (NULL);
740 do {
741 *dst++ = src[1] ^ Stuff_Magic;
742 }
743 while (--count >= 0 && dst < dst_end);
744 if (count < 0)
745 src += 2;
746 else
747 *src = (Stuff_Same + count) ^ Stuff_Magic;
748 break;
749 case Stuff_Zero:
750 do {
751 *dst++ = 0;
752 }
753 while (--count >= 0 && dst < dst_end);
754 if (count < 0)
755 src += 1;
756 else
757 *src = (Stuff_Zero + count) ^ Stuff_Magic;
758 break;
759 }
760 }
761 if (dst < dst_end)
762 return (NULL);
763 else
764 return (src);
765}
766
767
768/************************************************************************/
769/* General routines for STRIP */
770
771/*
772 * set_baud sets the baud rate to the rate defined by baudcode
773 */
774static void set_baud(struct tty_struct *tty, speed_t baudrate)
775{
776 struct ktermios old_termios;
777
778 mutex_lock(&tty->termios_mutex);
779 old_termios =*(tty->termios);
780 tty_encode_baud_rate(tty, baudrate, baudrate);
781 tty->ops->set_termios(tty, &old_termios);
782 mutex_unlock(&tty->termios_mutex);
783}
784
785/*
786 * Convert a string to a Metricom Address.
787 */
788
789#define IS_RADIO_ADDRESS(p) ( \
790 isdigit((p)[0]) && isdigit((p)[1]) && isdigit((p)[2]) && isdigit((p)[3]) && \
791 (p)[4] == '-' && \
792 isdigit((p)[5]) && isdigit((p)[6]) && isdigit((p)[7]) && isdigit((p)[8]) )
793
794static int string_to_radio_address(MetricomAddress * addr, __u8 * p)
795{
796 if (!IS_RADIO_ADDRESS(p))
797 return (1);
798 addr->c[0] = 0;
799 addr->c[1] = 0;
800 addr->c[2] = READHEX(p[0]) << 4 | READHEX(p[1]);
801 addr->c[3] = READHEX(p[2]) << 4 | READHEX(p[3]);
802 addr->c[4] = READHEX(p[5]) << 4 | READHEX(p[6]);
803 addr->c[5] = READHEX(p[7]) << 4 | READHEX(p[8]);
804 return (0);
805}
806
807/*
808 * Convert a Metricom Address to a string.
809 */
810
811static __u8 *radio_address_to_string(const MetricomAddress * addr,
812 MetricomAddressString * p)
813{
814 sprintf(p->c, "%02X%02X-%02X%02X", addr->c[2], addr->c[3],
815 addr->c[4], addr->c[5]);
816 return (p->c);
817}
818
819/*
820 * Note: Must make sure sx_size is big enough to receive a stuffed
821 * MAX_RECV_MTU packet. Additionally, we also want to ensure that it's
822 * big enough to receive a large radio neighbour list (currently 4K).
823 */
824
825static int allocate_buffers(struct strip *strip_info, int mtu)
826{
827 struct net_device *dev = strip_info->dev;
828 int sx_size = max_t(int, STRIP_ENCAP_SIZE(MAX_RECV_MTU), 4096);
829 int tx_size = STRIP_ENCAP_SIZE(mtu) + MaxCommandStringLength;
830 __u8 *r = kmalloc(MAX_RECV_MTU, GFP_ATOMIC);
831 __u8 *s = kmalloc(sx_size, GFP_ATOMIC);
832 __u8 *t = kmalloc(tx_size, GFP_ATOMIC);
833 if (r && s && t) {
834 strip_info->rx_buff = r;
835 strip_info->sx_buff = s;
836 strip_info->tx_buff = t;
837 strip_info->sx_size = sx_size;
838 strip_info->tx_size = tx_size;
839 strip_info->mtu = dev->mtu = mtu;
840 return (1);
841 }
842 kfree(r);
843 kfree(s);
844 kfree(t);
845 return (0);
846}
847
848/*
849 * MTU has been changed by the IP layer.
850 * We could be in
851 * an upcall from the tty driver, or in an ip packet queue.
852 */
853static int strip_change_mtu(struct net_device *dev, int new_mtu)
854{
855 struct strip *strip_info = netdev_priv(dev);
856 int old_mtu = strip_info->mtu;
857 unsigned char *orbuff = strip_info->rx_buff;
858 unsigned char *osbuff = strip_info->sx_buff;
859 unsigned char *otbuff = strip_info->tx_buff;
860
861 if (new_mtu > MAX_SEND_MTU) {
862 printk(KERN_ERR
863 "%s: MTU exceeds maximum allowable (%d), MTU change cancelled.\n",
864 strip_info->dev->name, MAX_SEND_MTU);
865 return -EINVAL;
866 }
867
868 spin_lock_bh(&strip_lock);
869 if (!allocate_buffers(strip_info, new_mtu)) {
870 printk(KERN_ERR "%s: unable to grow strip buffers, MTU change cancelled.\n",
871 strip_info->dev->name);
872 spin_unlock_bh(&strip_lock);
873 return -ENOMEM;
874 }
875
876 if (strip_info->sx_count) {
877 if (strip_info->sx_count <= strip_info->sx_size)
878 memcpy(strip_info->sx_buff, osbuff,
879 strip_info->sx_count);
880 else {
881 strip_info->discard = strip_info->sx_count;
882 strip_info->rx_over_errors++;
883 }
884 }
885
886 if (strip_info->tx_left) {
887 if (strip_info->tx_left <= strip_info->tx_size)
888 memcpy(strip_info->tx_buff, strip_info->tx_head,
889 strip_info->tx_left);
890 else {
891 strip_info->tx_left = 0;
892 strip_info->tx_dropped++;
893 }
894 }
895 strip_info->tx_head = strip_info->tx_buff;
896 spin_unlock_bh(&strip_lock);
897
898 printk(KERN_NOTICE "%s: strip MTU changed fom %d to %d.\n",
899 strip_info->dev->name, old_mtu, strip_info->mtu);
900
901 kfree(orbuff);
902 kfree(osbuff);
903 kfree(otbuff);
904 return 0;
905}
906
907static void strip_unlock(struct strip *strip_info)
908{
909 /*
910 * Set the timer to go off in one second.
911 */
912 strip_info->idle_timer.expires = jiffies + 1 * HZ;
913 add_timer(&strip_info->idle_timer);
914 netif_wake_queue(strip_info->dev);
915}
916
917
918
919/*
920 * If the time is in the near future, time_delta prints the number of
921 * seconds to go into the buffer and returns the address of the buffer.
922 * If the time is not in the near future, it returns the address of the
923 * string "Not scheduled" The buffer must be long enough to contain the
924 * ascii representation of the number plus 9 charactes for the " seconds"
925 * and the null character.
926 */
927#ifdef CONFIG_PROC_FS
928static char *time_delta(char buffer[], long time)
929{
930 time -= jiffies;
931 if (time > LongTime / 2)
932 return ("Not scheduled");
933 if (time < 0)
934 time = 0; /* Don't print negative times */
935 sprintf(buffer, "%ld seconds", time / HZ);
936 return (buffer);
937}
938
939/* get Nth element of the linked list */
940static struct strip *strip_get_idx(loff_t pos)
941{
942 struct strip *str;
943 int i = 0;
944
945 list_for_each_entry_rcu(str, &strip_list, list) {
946 if (pos == i)
947 return str;
948 ++i;
949 }
950 return NULL;
951}
952
953static void *strip_seq_start(struct seq_file *seq, loff_t *pos)
954 __acquires(RCU)
955{
956 rcu_read_lock();
957 return *pos ? strip_get_idx(*pos - 1) : SEQ_START_TOKEN;
958}
959
960static void *strip_seq_next(struct seq_file *seq, void *v, loff_t *pos)
961{
962 struct list_head *l;
963 struct strip *s;
964
965 ++*pos;
966 if (v == SEQ_START_TOKEN)
967 return strip_get_idx(1);
968
969 s = v;
970 l = &s->list;
971 list_for_each_continue_rcu(l, &strip_list) {
972 return list_entry(l, struct strip, list);
973 }
974 return NULL;
975}
976
977static void strip_seq_stop(struct seq_file *seq, void *v)
978 __releases(RCU)
979{
980 rcu_read_unlock();
981}
982
983static void strip_seq_neighbours(struct seq_file *seq,
984 const MetricomNodeTable * table,
985 const char *title)
986{
987 /* We wrap this in a do/while loop, so if the table changes */
988 /* while we're reading it, we just go around and try again. */
989 struct timeval t;
990
991 do {
992 int i;
993 t = table->timestamp;
994 if (table->num_nodes)
995 seq_printf(seq, "\n %s\n", title);
996 for (i = 0; i < table->num_nodes; i++) {
997 MetricomNode node;
998
999 spin_lock_bh(&strip_lock);
1000 node = table->node[i];
1001 spin_unlock_bh(&strip_lock);
1002 seq_printf(seq, " %s\n", node.c);
1003 }
1004 } while (table->timestamp.tv_sec != t.tv_sec
1005 || table->timestamp.tv_usec != t.tv_usec);
1006}
1007
1008/*
1009 * This function prints radio status information via the seq_file
1010 * interface. The interface takes care of buffer size and over
1011 * run issues.
1012 *
1013 * The buffer in seq_file is PAGESIZE (4K)
1014 * so this routine should never print more or it will get truncated.
1015 * With the maximum of 32 portables and 32 poletops
1016 * reported, the routine outputs 3107 bytes into the buffer.
1017 */
1018static void strip_seq_status_info(struct seq_file *seq,
1019 const struct strip *strip_info)
1020{
1021 char temp[32];
1022 MetricomAddressString addr_string;
1023
1024 /* First, we must copy all of our data to a safe place, */
1025 /* in case a serial interrupt comes in and changes it. */
1026 int tx_left = strip_info->tx_left;
1027 unsigned long rx_average_pps = strip_info->rx_average_pps;
1028 unsigned long tx_average_pps = strip_info->tx_average_pps;
1029 unsigned long sx_average_pps = strip_info->sx_average_pps;
1030 int working = strip_info->working;
1031 int firmware_level = strip_info->firmware_level;
1032 long watchdog_doprobe = strip_info->watchdog_doprobe;
1033 long watchdog_doreset = strip_info->watchdog_doreset;
1034 long gratuitous_arp = strip_info->gratuitous_arp;
1035 long arp_interval = strip_info->arp_interval;
1036 FirmwareVersion firmware_version = strip_info->firmware_version;
1037 SerialNumber serial_number = strip_info->serial_number;
1038 BatteryVoltage battery_voltage = strip_info->battery_voltage;
1039 char *if_name = strip_info->dev->name;
1040 MetricomAddress true_dev_addr = strip_info->true_dev_addr;
1041 MetricomAddress dev_dev_addr =
1042 *(MetricomAddress *) strip_info->dev->dev_addr;
1043 int manual_dev_addr = strip_info->manual_dev_addr;
1044#ifdef EXT_COUNTERS
1045 unsigned long rx_bytes = strip_info->rx_bytes;
1046 unsigned long tx_bytes = strip_info->tx_bytes;
1047 unsigned long rx_rbytes = strip_info->rx_rbytes;
1048 unsigned long tx_rbytes = strip_info->tx_rbytes;
1049 unsigned long rx_sbytes = strip_info->rx_sbytes;
1050 unsigned long tx_sbytes = strip_info->tx_sbytes;
1051 unsigned long rx_ebytes = strip_info->rx_ebytes;
1052 unsigned long tx_ebytes = strip_info->tx_ebytes;
1053#endif
1054
1055 seq_printf(seq, "\nInterface name\t\t%s\n", if_name);
1056 seq_printf(seq, " Radio working:\t\t%s\n", working ? "Yes" : "No");
1057 radio_address_to_string(&true_dev_addr, &addr_string);
1058 seq_printf(seq, " Radio address:\t\t%s\n", addr_string.c);
1059 if (manual_dev_addr) {
1060 radio_address_to_string(&dev_dev_addr, &addr_string);
1061 seq_printf(seq, " Device address:\t%s\n", addr_string.c);
1062 }
1063 seq_printf(seq, " Firmware version:\t%s", !working ? "Unknown" :
1064 !firmware_level ? "Should be upgraded" :
1065 firmware_version.c);
1066 if (firmware_level >= ChecksummedMessages)
1067 seq_printf(seq, " (Checksums Enabled)");
1068 seq_printf(seq, "\n");
1069 seq_printf(seq, " Serial number:\t\t%s\n", serial_number.c);
1070 seq_printf(seq, " Battery voltage:\t%s\n", battery_voltage.c);
1071 seq_printf(seq, " Transmit queue (bytes):%d\n", tx_left);
1072 seq_printf(seq, " Receive packet rate: %ld packets per second\n",
1073 rx_average_pps / 8);
1074 seq_printf(seq, " Transmit packet rate: %ld packets per second\n",
1075 tx_average_pps / 8);
1076 seq_printf(seq, " Sent packet rate: %ld packets per second\n",
1077 sx_average_pps / 8);
1078 seq_printf(seq, " Next watchdog probe:\t%s\n",
1079 time_delta(temp, watchdog_doprobe));
1080 seq_printf(seq, " Next watchdog reset:\t%s\n",
1081 time_delta(temp, watchdog_doreset));
1082 seq_printf(seq, " Next gratuitous ARP:\t");
1083
1084 if (!memcmp
1085 (strip_info->dev->dev_addr, zero_address.c,
1086 sizeof(zero_address)))
1087 seq_printf(seq, "Disabled\n");
1088 else {
1089 seq_printf(seq, "%s\n", time_delta(temp, gratuitous_arp));
1090 seq_printf(seq, " Next ARP interval:\t%ld seconds\n",
1091 JIFFIE_TO_SEC(arp_interval));
1092 }
1093
1094 if (working) {
1095#ifdef EXT_COUNTERS
1096 seq_printf(seq, "\n");
1097 seq_printf(seq,
1098 " Total bytes: \trx:\t%lu\ttx:\t%lu\n",
1099 rx_bytes, tx_bytes);
1100 seq_printf(seq,
1101 " thru radio: \trx:\t%lu\ttx:\t%lu\n",
1102 rx_rbytes, tx_rbytes);
1103 seq_printf(seq,
1104 " thru serial port: \trx:\t%lu\ttx:\t%lu\n",
1105 rx_sbytes, tx_sbytes);
1106 seq_printf(seq,
1107 " Total stat/err bytes:\trx:\t%lu\ttx:\t%lu\n",
1108 rx_ebytes, tx_ebytes);
1109#endif
1110 strip_seq_neighbours(seq, &strip_info->poletops,
1111 "Poletops:");
1112 strip_seq_neighbours(seq, &strip_info->portables,
1113 "Portables:");
1114 }
1115}
1116
1117/*
1118 * This function is exports status information from the STRIP driver through
1119 * the /proc file system.
1120 */
1121static int strip_seq_show(struct seq_file *seq, void *v)
1122{
1123 if (v == SEQ_START_TOKEN)
1124 seq_printf(seq, "strip_version: %s\n", StripVersion);
1125 else
1126 strip_seq_status_info(seq, (const struct strip *)v);
1127 return 0;
1128}
1129
1130
1131static const struct seq_operations strip_seq_ops = {
1132 .start = strip_seq_start,
1133 .next = strip_seq_next,
1134 .stop = strip_seq_stop,
1135 .show = strip_seq_show,
1136};
1137
1138static int strip_seq_open(struct inode *inode, struct file *file)
1139{
1140 return seq_open(file, &strip_seq_ops);
1141}
1142
1143static const struct file_operations strip_seq_fops = {
1144 .owner = THIS_MODULE,
1145 .open = strip_seq_open,
1146 .read = seq_read,
1147 .llseek = seq_lseek,
1148 .release = seq_release,
1149};
1150#endif
1151
1152
1153
1154/************************************************************************/
1155/* Sending routines */
1156
1157static void ResetRadio(struct strip *strip_info)
1158{
1159 struct tty_struct *tty = strip_info->tty;
1160 static const char init[] = "ate0q1dt**starmode\r**";
1161 StringDescriptor s = { init, sizeof(init) - 1 };
1162
1163 /*
1164 * If the radio isn't working anymore,
1165 * we should clear the old status information.
1166 */
1167 if (strip_info->working) {
1168 printk(KERN_INFO "%s: No response: Resetting radio.\n",
1169 strip_info->dev->name);
1170 strip_info->firmware_version.c[0] = '\0';
1171 strip_info->serial_number.c[0] = '\0';
1172 strip_info->battery_voltage.c[0] = '\0';
1173 strip_info->portables.num_nodes = 0;
1174 do_gettimeofday(&strip_info->portables.timestamp);
1175 strip_info->poletops.num_nodes = 0;
1176 do_gettimeofday(&strip_info->poletops.timestamp);
1177 }
1178
1179 strip_info->pps_timer = jiffies;
1180 strip_info->rx_pps_count = 0;
1181 strip_info->tx_pps_count = 0;
1182 strip_info->sx_pps_count = 0;
1183 strip_info->rx_average_pps = 0;
1184 strip_info->tx_average_pps = 0;
1185 strip_info->sx_average_pps = 0;
1186
1187 /* Mark radio address as unknown */
1188 *(MetricomAddress *) & strip_info->true_dev_addr = zero_address;
1189 if (!strip_info->manual_dev_addr)
1190 *(MetricomAddress *) strip_info->dev->dev_addr =
1191 zero_address;
1192 strip_info->working = FALSE;
1193 strip_info->firmware_level = NoStructure;
1194 strip_info->next_command = CompatibilityCommand;
1195 strip_info->watchdog_doprobe = jiffies + 10 * HZ;
1196 strip_info->watchdog_doreset = jiffies + 1 * HZ;
1197
1198 /* If the user has selected a baud rate above 38.4 see what magic we have to do */
1199 if (strip_info->user_baud > 38400) {
1200 /*
1201 * Subtle stuff: Pay attention :-)
1202 * If the serial port is currently at the user's selected (>38.4) rate,
1203 * then we temporarily switch to 19.2 and issue the ATS304 command
1204 * to tell the radio to switch to the user's selected rate.
1205 * If the serial port is not currently at that rate, that means we just
1206 * issued the ATS304 command last time through, so this time we restore
1207 * the user's selected rate and issue the normal starmode reset string.
1208 */
1209 if (strip_info->user_baud == tty_get_baud_rate(tty)) {
1210 static const char b0[] = "ate0q1s304=57600\r";
1211 static const char b1[] = "ate0q1s304=115200\r";
1212 static const StringDescriptor baudstring[2] =
1213 { {b0, sizeof(b0) - 1}
1214 , {b1, sizeof(b1) - 1}
1215 };
1216 set_baud(tty, 19200);
1217 if (strip_info->user_baud == 57600)
1218 s = baudstring[0];
1219 else if (strip_info->user_baud == 115200)
1220 s = baudstring[1];
1221 else
1222 s = baudstring[1]; /* For now */
1223 } else
1224 set_baud(tty, strip_info->user_baud);
1225 }
1226
1227 tty->ops->write(tty, s.string, s.length);
1228#ifdef EXT_COUNTERS
1229 strip_info->tx_ebytes += s.length;
1230#endif
1231}
1232
1233/*
1234 * Called by the driver when there's room for more data. If we have
1235 * more packets to send, we send them here.
1236 */
1237
1238static void strip_write_some_more(struct tty_struct *tty)
1239{
1240 struct strip *strip_info = tty->disc_data;
1241
1242 /* First make sure we're connected. */
1243 if (!strip_info || strip_info->magic != STRIP_MAGIC ||
1244 !netif_running(strip_info->dev))
1245 return;
1246
1247 if (strip_info->tx_left > 0) {
1248 int num_written =
1249 tty->ops->write(tty, strip_info->tx_head,
1250 strip_info->tx_left);
1251 strip_info->tx_left -= num_written;
1252 strip_info->tx_head += num_written;
1253#ifdef EXT_COUNTERS
1254 strip_info->tx_sbytes += num_written;
1255#endif
1256 } else { /* Else start transmission of another packet */
1257
1258 clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
1259 strip_unlock(strip_info);
1260 }
1261}
1262
1263static __u8 *add_checksum(__u8 * buffer, __u8 * end)
1264{
1265 __u16 sum = 0;
1266 __u8 *p = buffer;
1267 while (p < end)
1268 sum += *p++;
1269 end[3] = hextable[sum & 0xF];
1270 sum >>= 4;
1271 end[2] = hextable[sum & 0xF];
1272 sum >>= 4;
1273 end[1] = hextable[sum & 0xF];
1274 sum >>= 4;
1275 end[0] = hextable[sum & 0xF];
1276 return (end + 4);
1277}
1278
1279static unsigned char *strip_make_packet(unsigned char *buffer,
1280 struct strip *strip_info,
1281 struct sk_buff *skb)
1282{
1283 __u8 *ptr = buffer;
1284 __u8 *stuffstate = NULL;
1285 STRIP_Header *header = (STRIP_Header *) skb->data;
1286 MetricomAddress haddr = header->dst_addr;
1287 int len = skb->len - sizeof(STRIP_Header);
1288 MetricomKey key;
1289
1290 /*HexDump("strip_make_packet", strip_info, skb->data, skb->data + skb->len); */
1291
1292 if (header->protocol == htons(ETH_P_IP))
1293 key = SIP0Key;
1294 else if (header->protocol == htons(ETH_P_ARP))
1295 key = ARP0Key;
1296 else {
1297 printk(KERN_ERR
1298 "%s: strip_make_packet: Unknown packet type 0x%04X\n",
1299 strip_info->dev->name, ntohs(header->protocol));
1300 return (NULL);
1301 }
1302
1303 if (len > strip_info->mtu) {
1304 printk(KERN_ERR
1305 "%s: Dropping oversized transmit packet: %d bytes\n",
1306 strip_info->dev->name, len);
1307 return (NULL);
1308 }
1309
1310 /*
1311 * If we're sending to ourselves, discard the packet.
1312 * (Metricom radios choke if they try to send a packet to their own address.)
1313 */
1314 if (!memcmp(haddr.c, strip_info->true_dev_addr.c, sizeof(haddr))) {
1315 printk(KERN_ERR "%s: Dropping packet addressed to self\n",
1316 strip_info->dev->name);
1317 return (NULL);
1318 }
1319
1320 /*
1321 * If this is a broadcast packet, send it to our designated Metricom
1322 * 'broadcast hub' radio (First byte of address being 0xFF means broadcast)
1323 */
1324 if (haddr.c[0] == 0xFF) {
1325 __be32 brd = 0;
1326 struct in_device *in_dev;
1327
1328 rcu_read_lock();
1329 in_dev = __in_dev_get_rcu(strip_info->dev);
1330 if (in_dev == NULL) {
1331 rcu_read_unlock();
1332 return NULL;
1333 }
1334 if (in_dev->ifa_list)
1335 brd = in_dev->ifa_list->ifa_broadcast;
1336 rcu_read_unlock();
1337
1338 /* arp_query returns 1 if it succeeds in looking up the address, 0 if it fails */
1339 if (!arp_query(haddr.c, brd, strip_info->dev)) {
1340 printk(KERN_ERR
1341 "%s: Unable to send packet (no broadcast hub configured)\n",
1342 strip_info->dev->name);
1343 return (NULL);
1344 }
1345 /*
1346 * If we are the broadcast hub, don't bother sending to ourselves.
1347 * (Metricom radios choke if they try to send a packet to their own address.)
1348 */
1349 if (!memcmp
1350 (haddr.c, strip_info->true_dev_addr.c, sizeof(haddr)))
1351 return (NULL);
1352 }
1353
1354 *ptr++ = 0x0D;
1355 *ptr++ = '*';
1356 *ptr++ = hextable[haddr.c[2] >> 4];
1357 *ptr++ = hextable[haddr.c[2] & 0xF];
1358 *ptr++ = hextable[haddr.c[3] >> 4];
1359 *ptr++ = hextable[haddr.c[3] & 0xF];
1360 *ptr++ = '-';
1361 *ptr++ = hextable[haddr.c[4] >> 4];
1362 *ptr++ = hextable[haddr.c[4] & 0xF];
1363 *ptr++ = hextable[haddr.c[5] >> 4];
1364 *ptr++ = hextable[haddr.c[5] & 0xF];
1365 *ptr++ = '*';
1366 *ptr++ = key.c[0];
1367 *ptr++ = key.c[1];
1368 *ptr++ = key.c[2];
1369 *ptr++ = key.c[3];
1370
1371 ptr =
1372 StuffData(skb->data + sizeof(STRIP_Header), len, ptr,
1373 &stuffstate);
1374
1375 if (strip_info->firmware_level >= ChecksummedMessages)
1376 ptr = add_checksum(buffer + 1, ptr);
1377
1378 *ptr++ = 0x0D;
1379 return (ptr);
1380}
1381
1382static void strip_send(struct strip *strip_info, struct sk_buff *skb)
1383{
1384 MetricomAddress haddr;
1385 unsigned char *ptr = strip_info->tx_buff;
1386 int doreset = (long) jiffies - strip_info->watchdog_doreset >= 0;
1387 int doprobe = (long) jiffies - strip_info->watchdog_doprobe >= 0
1388 && !doreset;
1389 __be32 addr, brd;
1390
1391 /*
1392 * 1. If we have a packet, encapsulate it and put it in the buffer
1393 */
1394 if (skb) {
1395 char *newptr = strip_make_packet(ptr, strip_info, skb);
1396 strip_info->tx_pps_count++;
1397 if (!newptr)
1398 strip_info->tx_dropped++;
1399 else {
1400 ptr = newptr;
1401 strip_info->sx_pps_count++;
1402 strip_info->tx_packets++; /* Count another successful packet */
1403#ifdef EXT_COUNTERS
1404 strip_info->tx_bytes += skb->len;
1405 strip_info->tx_rbytes += ptr - strip_info->tx_buff;
1406#endif
1407 /*DumpData("Sending:", strip_info, strip_info->tx_buff, ptr); */
1408 /*HexDump("Sending", strip_info, strip_info->tx_buff, ptr); */
1409 }
1410 }
1411
1412 /*
1413 * 2. If it is time for another tickle, tack it on, after the packet
1414 */
1415 if (doprobe) {
1416 StringDescriptor ts = CommandString[strip_info->next_command];
1417#if TICKLE_TIMERS
1418 {
1419 struct timeval tv;
1420 do_gettimeofday(&tv);
1421 printk(KERN_INFO "**** Sending tickle string %d at %02d.%06d\n",
1422 strip_info->next_command, tv.tv_sec % 100,
1423 tv.tv_usec);
1424 }
1425#endif
1426 if (ptr == strip_info->tx_buff)
1427 *ptr++ = 0x0D;
1428
1429 *ptr++ = '*'; /* First send "**" to provoke an error message */
1430 *ptr++ = '*';
1431
1432 /* Then add the command */
1433 memcpy(ptr, ts.string, ts.length);
1434
1435 /* Add a checksum ? */
1436 if (strip_info->firmware_level < ChecksummedMessages)
1437 ptr += ts.length;
1438 else
1439 ptr = add_checksum(ptr, ptr + ts.length);
1440
1441 *ptr++ = 0x0D; /* Terminate the command with a <CR> */
1442
1443 /* Cycle to next periodic command? */
1444 if (strip_info->firmware_level >= StructuredMessages)
1445 if (++strip_info->next_command >=
1446 ARRAY_SIZE(CommandString))
1447 strip_info->next_command = 0;
1448#ifdef EXT_COUNTERS
1449 strip_info->tx_ebytes += ts.length;
1450#endif
1451 strip_info->watchdog_doprobe = jiffies + 10 * HZ;
1452 strip_info->watchdog_doreset = jiffies + 1 * HZ;
1453 /*printk(KERN_INFO "%s: Routine radio test.\n", strip_info->dev->name); */
1454 }
1455
1456 /*
1457 * 3. Set up the strip_info ready to send the data (if any).
1458 */
1459 strip_info->tx_head = strip_info->tx_buff;
1460 strip_info->tx_left = ptr - strip_info->tx_buff;
1461 set_bit(TTY_DO_WRITE_WAKEUP, &strip_info->tty->flags);
1462 /*
1463 * 4. Debugging check to make sure we're not overflowing the buffer.
1464 */
1465 if (strip_info->tx_size - strip_info->tx_left < 20)
1466 printk(KERN_ERR "%s: Sending%5d bytes;%5d bytes free.\n",
1467 strip_info->dev->name, strip_info->tx_left,
1468 strip_info->tx_size - strip_info->tx_left);
1469
1470 /*
1471 * 5. If watchdog has expired, reset the radio. Note: if there's data waiting in
1472 * the buffer, strip_write_some_more will send it after the reset has finished
1473 */
1474 if (doreset) {
1475 ResetRadio(strip_info);
1476 return;
1477 }
1478
1479 if (1) {
1480 struct in_device *in_dev;
1481
1482 brd = addr = 0;
1483 rcu_read_lock();
1484 in_dev = __in_dev_get_rcu(strip_info->dev);
1485 if (in_dev) {
1486 if (in_dev->ifa_list) {
1487 brd = in_dev->ifa_list->ifa_broadcast;
1488 addr = in_dev->ifa_list->ifa_local;
1489 }
1490 }
1491 rcu_read_unlock();
1492 }
1493
1494
1495 /*
1496 * 6. If it is time for a periodic ARP, queue one up to be sent.
1497 * We only do this if:
1498 * 1. The radio is working
1499 * 2. It's time to send another periodic ARP
1500 * 3. We really know what our address is (and it is not manually set to zero)
1501 * 4. We have a designated broadcast address configured
1502 * If we queue up an ARP packet when we don't have a designated broadcast
1503 * address configured, then the packet will just have to be discarded in
1504 * strip_make_packet. This is not fatal, but it causes misleading information
1505 * to be displayed in tcpdump. tcpdump will report that periodic APRs are
1506 * being sent, when in fact they are not, because they are all being dropped
1507 * in the strip_make_packet routine.
1508 */
1509 if (strip_info->working
1510 && (long) jiffies - strip_info->gratuitous_arp >= 0
1511 && memcmp(strip_info->dev->dev_addr, zero_address.c,
1512 sizeof(zero_address))
1513 && arp_query(haddr.c, brd, strip_info->dev)) {
1514 /*printk(KERN_INFO "%s: Sending gratuitous ARP with interval %ld\n",
1515 strip_info->dev->name, strip_info->arp_interval / HZ); */
1516 strip_info->gratuitous_arp =
1517 jiffies + strip_info->arp_interval;
1518 strip_info->arp_interval *= 2;
1519 if (strip_info->arp_interval > MaxARPInterval)
1520 strip_info->arp_interval = MaxARPInterval;
1521 if (addr)
1522 arp_send(ARPOP_REPLY, ETH_P_ARP, addr, /* Target address of ARP packet is our address */
1523 strip_info->dev, /* Device to send packet on */
1524 addr, /* Source IP address this ARP packet comes from */
1525 NULL, /* Destination HW address is NULL (broadcast it) */
1526 strip_info->dev->dev_addr, /* Source HW address is our HW address */
1527 strip_info->dev->dev_addr); /* Target HW address is our HW address (redundant) */
1528 }
1529
1530 /*
1531 * 7. All ready. Start the transmission
1532 */
1533 strip_write_some_more(strip_info->tty);
1534}
1535
1536/* Encapsulate a datagram and kick it into a TTY queue. */
1537static netdev_tx_t strip_xmit(struct sk_buff *skb, struct net_device *dev)
1538{
1539 struct strip *strip_info = netdev_priv(dev);
1540
1541 if (!netif_running(dev)) {
1542 printk(KERN_ERR "%s: xmit call when iface is down\n",
1543 dev->name);
1544 return NETDEV_TX_BUSY;
1545 }
1546
1547 netif_stop_queue(dev);
1548
1549 del_timer(&strip_info->idle_timer);
1550
1551
1552 if (time_after(jiffies, strip_info->pps_timer + HZ)) {
1553 unsigned long t = jiffies - strip_info->pps_timer;
1554 unsigned long rx_pps_count =
1555 DIV_ROUND_CLOSEST(strip_info->rx_pps_count*HZ*8, t);
1556 unsigned long tx_pps_count =
1557 DIV_ROUND_CLOSEST(strip_info->tx_pps_count*HZ*8, t);
1558 unsigned long sx_pps_count =
1559 DIV_ROUND_CLOSEST(strip_info->sx_pps_count*HZ*8, t);
1560
1561 strip_info->pps_timer = jiffies;
1562 strip_info->rx_pps_count = 0;
1563 strip_info->tx_pps_count = 0;
1564 strip_info->sx_pps_count = 0;
1565
1566 strip_info->rx_average_pps = (strip_info->rx_average_pps + rx_pps_count + 1) / 2;
1567 strip_info->tx_average_pps = (strip_info->tx_average_pps + tx_pps_count + 1) / 2;
1568 strip_info->sx_average_pps = (strip_info->sx_average_pps + sx_pps_count + 1) / 2;
1569
1570 if (rx_pps_count / 8 >= 10)
1571 printk(KERN_INFO "%s: WARNING: Receiving %ld packets per second.\n",
1572 strip_info->dev->name, rx_pps_count / 8);
1573 if (tx_pps_count / 8 >= 10)
1574 printk(KERN_INFO "%s: WARNING: Tx %ld packets per second.\n",
1575 strip_info->dev->name, tx_pps_count / 8);
1576 if (sx_pps_count / 8 >= 10)
1577 printk(KERN_INFO "%s: WARNING: Sending %ld packets per second.\n",
1578 strip_info->dev->name, sx_pps_count / 8);
1579 }
1580
1581 spin_lock_bh(&strip_lock);
1582
1583 strip_send(strip_info, skb);
1584
1585 spin_unlock_bh(&strip_lock);
1586
1587 if (skb)
1588 dev_kfree_skb(skb);
1589 return NETDEV_TX_OK;
1590}
1591
1592/*
1593 * IdleTask periodically calls strip_xmit, so even when we have no IP packets
1594 * to send for an extended period of time, the watchdog processing still gets
1595 * done to ensure that the radio stays in Starmode
1596 */
1597
1598static void strip_IdleTask(unsigned long parameter)
1599{
1600 strip_xmit(NULL, (struct net_device *) parameter);
1601}
1602
1603/*
1604 * Create the MAC header for an arbitrary protocol layer
1605 *
1606 * saddr!=NULL means use this specific address (n/a for Metricom)
1607 * saddr==NULL means use default device source address
1608 * daddr!=NULL means use this destination address
1609 * daddr==NULL means leave destination address alone
1610 * (e.g. unresolved arp -- kernel will call
1611 * rebuild_header later to fill in the address)
1612 */
1613
1614static int strip_header(struct sk_buff *skb, struct net_device *dev,
1615 unsigned short type, const void *daddr,
1616 const void *saddr, unsigned len)
1617{
1618 struct strip *strip_info = netdev_priv(dev);
1619 STRIP_Header *header = (STRIP_Header *) skb_push(skb, sizeof(STRIP_Header));
1620
1621 /*printk(KERN_INFO "%s: strip_header 0x%04X %s\n", dev->name, type,
1622 type == ETH_P_IP ? "IP" : type == ETH_P_ARP ? "ARP" : ""); */
1623
1624 header->src_addr = strip_info->true_dev_addr;
1625 header->protocol = htons(type);
1626
1627 /*HexDump("strip_header", netdev_priv(dev), skb->data, skb->data + skb->len); */
1628
1629 if (!daddr)
1630 return (-dev->hard_header_len);
1631
1632 header->dst_addr = *(MetricomAddress *) daddr;
1633 return (dev->hard_header_len);
1634}
1635
1636/*
1637 * Rebuild the MAC header. This is called after an ARP
1638 * (or in future other address resolution) has completed on this
1639 * sk_buff. We now let ARP fill in the other fields.
1640 * I think this should return zero if packet is ready to send,
1641 * or non-zero if it needs more time to do an address lookup
1642 */
1643
1644static int strip_rebuild_header(struct sk_buff *skb)
1645{
1646#ifdef CONFIG_INET
1647 STRIP_Header *header = (STRIP_Header *) skb->data;
1648
1649 /* Arp find returns zero if if knows the address, */
1650 /* or if it doesn't know the address it sends an ARP packet and returns non-zero */
1651 return arp_find(header->dst_addr.c, skb) ? 1 : 0;
1652#else
1653 return 0;
1654#endif
1655}
1656
1657
1658/************************************************************************/
1659/* Receiving routines */
1660
1661/*
1662 * This function parses the response to the ATS300? command,
1663 * extracting the radio version and serial number.
1664 */
1665static void get_radio_version(struct strip *strip_info, __u8 * ptr, __u8 * end)
1666{
1667 __u8 *p, *value_begin, *value_end;
1668 int len;
1669
1670 /* Determine the beginning of the second line of the payload */
1671 p = ptr;
1672 while (p < end && *p != 10)
1673 p++;
1674 if (p >= end)
1675 return;
1676 p++;
1677 value_begin = p;
1678
1679 /* Determine the end of line */
1680 while (p < end && *p != 10)
1681 p++;
1682 if (p >= end)
1683 return;
1684 value_end = p;
1685 p++;
1686
1687 len = value_end - value_begin;
1688 len = min_t(int, len, sizeof(FirmwareVersion) - 1);
1689 if (strip_info->firmware_version.c[0] == 0)
1690 printk(KERN_INFO "%s: Radio Firmware: %.*s\n",
1691 strip_info->dev->name, len, value_begin);
1692 sprintf(strip_info->firmware_version.c, "%.*s", len, value_begin);
1693
1694 /* Look for the first colon */
1695 while (p < end && *p != ':')
1696 p++;
1697 if (p >= end)
1698 return;
1699 /* Skip over the space */
1700 p += 2;
1701 len = sizeof(SerialNumber) - 1;
1702 if (p + len <= end) {
1703 sprintf(strip_info->serial_number.c, "%.*s", len, p);
1704 } else {
1705 printk(KERN_DEBUG
1706 "STRIP: radio serial number shorter (%zd) than expected (%d)\n",
1707 end - p, len);
1708 }
1709}
1710
1711/*
1712 * This function parses the response to the ATS325? command,
1713 * extracting the radio battery voltage.
1714 */
1715static void get_radio_voltage(struct strip *strip_info, __u8 * ptr, __u8 * end)
1716{
1717 int len;
1718
1719 len = sizeof(BatteryVoltage) - 1;
1720 if (ptr + len <= end) {
1721 sprintf(strip_info->battery_voltage.c, "%.*s", len, ptr);
1722 } else {
1723 printk(KERN_DEBUG
1724 "STRIP: radio voltage string shorter (%zd) than expected (%d)\n",
1725 end - ptr, len);
1726 }
1727}
1728
1729/*
1730 * This function parses the responses to the AT~LA and ATS311 commands,
1731 * which list the radio's neighbours.
1732 */
1733static void get_radio_neighbours(MetricomNodeTable * table, __u8 * ptr, __u8 * end)
1734{
1735 table->num_nodes = 0;
1736 while (ptr < end && table->num_nodes < NODE_TABLE_SIZE) {
1737 MetricomNode *node = &table->node[table->num_nodes++];
1738 char *dst = node->c, *limit = dst + sizeof(*node) - 1;
1739 while (ptr < end && *ptr <= 32)
1740 ptr++;
1741 while (ptr < end && dst < limit && *ptr != 10)
1742 *dst++ = *ptr++;
1743 *dst++ = 0;
1744 while (ptr < end && ptr[-1] != 10)
1745 ptr++;
1746 }
1747 do_gettimeofday(&table->timestamp);
1748}
1749
1750static int get_radio_address(struct strip *strip_info, __u8 * p)
1751{
1752 MetricomAddress addr;
1753
1754 if (string_to_radio_address(&addr, p))
1755 return (1);
1756
1757 /* See if our radio address has changed */
1758 if (memcmp(strip_info->true_dev_addr.c, addr.c, sizeof(addr))) {
1759 MetricomAddressString addr_string;
1760 radio_address_to_string(&addr, &addr_string);
1761 printk(KERN_INFO "%s: Radio address = %s\n",
1762 strip_info->dev->name, addr_string.c);
1763 strip_info->true_dev_addr = addr;
1764 if (!strip_info->manual_dev_addr)
1765 *(MetricomAddress *) strip_info->dev->dev_addr =
1766 addr;
1767 /* Give the radio a few seconds to get its head straight, then send an arp */
1768 strip_info->gratuitous_arp = jiffies + 15 * HZ;
1769 strip_info->arp_interval = 1 * HZ;
1770 }
1771 return (0);
1772}
1773
1774static int verify_checksum(struct strip *strip_info)
1775{
1776 __u8 *p = strip_info->sx_buff;
1777 __u8 *end = strip_info->sx_buff + strip_info->sx_count - 4;
1778 u_short sum =
1779 (READHEX16(end[0]) << 12) | (READHEX16(end[1]) << 8) |
1780 (READHEX16(end[2]) << 4) | (READHEX16(end[3]));
1781 while (p < end)
1782 sum -= *p++;
1783 if (sum == 0 && strip_info->firmware_level == StructuredMessages) {
1784 strip_info->firmware_level = ChecksummedMessages;
1785 printk(KERN_INFO "%s: Radio provides message checksums\n",
1786 strip_info->dev->name);
1787 }
1788 return (sum == 0);
1789}
1790
1791static void RecvErr(char *msg, struct strip *strip_info)
1792{
1793 __u8 *ptr = strip_info->sx_buff;
1794 __u8 *end = strip_info->sx_buff + strip_info->sx_count;
1795 DumpData(msg, strip_info, ptr, end);
1796 strip_info->rx_errors++;
1797}
1798
1799static void RecvErr_Message(struct strip *strip_info, __u8 * sendername,
1800 const __u8 * msg, u_long len)
1801{
1802 if (has_prefix(msg, len, "001")) { /* Not in StarMode! */
1803 RecvErr("Error Msg:", strip_info);
1804 printk(KERN_INFO "%s: Radio %s is not in StarMode\n",
1805 strip_info->dev->name, sendername);
1806 }
1807
1808 else if (has_prefix(msg, len, "002")) { /* Remap handle */
1809 /* We ignore "Remap handle" messages for now */
1810 }
1811
1812 else if (has_prefix(msg, len, "003")) { /* Can't resolve name */
1813 RecvErr("Error Msg:", strip_info);
1814 printk(KERN_INFO "%s: Destination radio name is unknown\n",
1815 strip_info->dev->name);
1816 }
1817
1818 else if (has_prefix(msg, len, "004")) { /* Name too small or missing */
1819 strip_info->watchdog_doreset = jiffies + LongTime;
1820#if TICKLE_TIMERS
1821 {
1822 struct timeval tv;
1823 do_gettimeofday(&tv);
1824 printk(KERN_INFO
1825 "**** Got ERR_004 response at %02d.%06d\n",
1826 tv.tv_sec % 100, tv.tv_usec);
1827 }
1828#endif
1829 if (!strip_info->working) {
1830 strip_info->working = TRUE;
1831 printk(KERN_INFO "%s: Radio now in starmode\n",
1832 strip_info->dev->name);
1833 /*
1834 * If the radio has just entered a working state, we should do our first
1835 * probe ASAP, so that we find out our radio address etc. without delay.
1836 */
1837 strip_info->watchdog_doprobe = jiffies;
1838 }
1839 if (strip_info->firmware_level == NoStructure && sendername) {
1840 strip_info->firmware_level = StructuredMessages;
1841 strip_info->next_command = 0; /* Try to enable checksums ASAP */
1842 printk(KERN_INFO
1843 "%s: Radio provides structured messages\n",
1844 strip_info->dev->name);
1845 }
1846 if (strip_info->firmware_level >= StructuredMessages) {
1847 /*
1848 * If this message has a valid checksum on the end, then the call to verify_checksum
1849 * will elevate the firmware_level to ChecksummedMessages for us. (The actual return
1850 * code from verify_checksum is ignored here.)
1851 */
1852 verify_checksum(strip_info);
1853 /*
1854 * If the radio has structured messages but we don't yet have all our information about it,
1855 * we should do probes without delay, until we have gathered all the information
1856 */
1857 if (!GOT_ALL_RADIO_INFO(strip_info))
1858 strip_info->watchdog_doprobe = jiffies;
1859 }
1860 }
1861
1862 else if (has_prefix(msg, len, "005")) /* Bad count specification */
1863 RecvErr("Error Msg:", strip_info);
1864
1865 else if (has_prefix(msg, len, "006")) /* Header too big */
1866 RecvErr("Error Msg:", strip_info);
1867
1868 else if (has_prefix(msg, len, "007")) { /* Body too big */
1869 RecvErr("Error Msg:", strip_info);
1870 printk(KERN_ERR
1871 "%s: Error! Packet size too big for radio.\n",
1872 strip_info->dev->name);
1873 }
1874
1875 else if (has_prefix(msg, len, "008")) { /* Bad character in name */
1876 RecvErr("Error Msg:", strip_info);
1877 printk(KERN_ERR
1878 "%s: Radio name contains illegal character\n",
1879 strip_info->dev->name);
1880 }
1881
1882 else if (has_prefix(msg, len, "009")) /* No count or line terminator */
1883 RecvErr("Error Msg:", strip_info);
1884
1885 else if (has_prefix(msg, len, "010")) /* Invalid checksum */
1886 RecvErr("Error Msg:", strip_info);
1887
1888 else if (has_prefix(msg, len, "011")) /* Checksum didn't match */
1889 RecvErr("Error Msg:", strip_info);
1890
1891 else if (has_prefix(msg, len, "012")) /* Failed to transmit packet */
1892 RecvErr("Error Msg:", strip_info);
1893
1894 else
1895 RecvErr("Error Msg:", strip_info);
1896}
1897
1898static void process_AT_response(struct strip *strip_info, __u8 * ptr,
1899 __u8 * end)
1900{
1901 u_long len;
1902 __u8 *p = ptr;
1903 while (p < end && p[-1] != 10)
1904 p++; /* Skip past first newline character */
1905 /* Now ptr points to the AT command, and p points to the text of the response. */
1906 len = p - ptr;
1907
1908#if TICKLE_TIMERS
1909 {
1910 struct timeval tv;
1911 do_gettimeofday(&tv);
1912 printk(KERN_INFO "**** Got AT response %.7s at %02d.%06d\n",
1913 ptr, tv.tv_sec % 100, tv.tv_usec);
1914 }
1915#endif
1916
1917 if (has_prefix(ptr, len, "ATS300?"))
1918 get_radio_version(strip_info, p, end);
1919 else if (has_prefix(ptr, len, "ATS305?"))
1920 get_radio_address(strip_info, p);
1921 else if (has_prefix(ptr, len, "ATS311?"))
1922 get_radio_neighbours(&strip_info->poletops, p, end);
1923 else if (has_prefix(ptr, len, "ATS319=7"))
1924 verify_checksum(strip_info);
1925 else if (has_prefix(ptr, len, "ATS325?"))
1926 get_radio_voltage(strip_info, p, end);
1927 else if (has_prefix(ptr, len, "AT~LA"))
1928 get_radio_neighbours(&strip_info->portables, p, end);
1929 else
1930 RecvErr("Unknown AT Response:", strip_info);
1931}
1932
1933static void process_ACK(struct strip *strip_info, __u8 * ptr, __u8 * end)
1934{
1935 /* Currently we don't do anything with ACKs from the radio */
1936}
1937
1938static void process_Info(struct strip *strip_info, __u8 * ptr, __u8 * end)
1939{
1940 if (ptr + 16 > end)
1941 RecvErr("Bad Info Msg:", strip_info);
1942}
1943
1944static struct net_device *get_strip_dev(struct strip *strip_info)
1945{
1946 /* If our hardware address is *manually set* to zero, and we know our */
1947 /* real radio hardware address, try to find another strip device that has been */
1948 /* manually set to that address that we can 'transfer ownership' of this packet to */
1949 if (strip_info->manual_dev_addr &&
1950 !memcmp(strip_info->dev->dev_addr, zero_address.c,
1951 sizeof(zero_address))
1952 && memcmp(&strip_info->true_dev_addr, zero_address.c,
1953 sizeof(zero_address))) {
1954 struct net_device *dev;
1955 read_lock_bh(&dev_base_lock);
1956 for_each_netdev(&init_net, dev) {
1957 if (dev->type == strip_info->dev->type &&
1958 !memcmp(dev->dev_addr,
1959 &strip_info->true_dev_addr,
1960 sizeof(MetricomAddress))) {
1961 printk(KERN_INFO
1962 "%s: Transferred packet ownership to %s.\n",
1963 strip_info->dev->name, dev->name);
1964 read_unlock_bh(&dev_base_lock);
1965 return (dev);
1966 }
1967 }
1968 read_unlock_bh(&dev_base_lock);
1969 }
1970 return (strip_info->dev);
1971}
1972
1973/*
1974 * Send one completely decapsulated datagram to the next layer.
1975 */
1976
1977static void deliver_packet(struct strip *strip_info, STRIP_Header * header,
1978 __u16 packetlen)
1979{
1980 struct sk_buff *skb = dev_alloc_skb(sizeof(STRIP_Header) + packetlen);
1981 if (!skb) {
1982 printk(KERN_ERR "%s: memory squeeze, dropping packet.\n",
1983 strip_info->dev->name);
1984 strip_info->rx_dropped++;
1985 } else {
1986 memcpy(skb_put(skb, sizeof(STRIP_Header)), header,
1987 sizeof(STRIP_Header));
1988 memcpy(skb_put(skb, packetlen), strip_info->rx_buff,
1989 packetlen);
1990 skb->dev = get_strip_dev(strip_info);
1991 skb->protocol = header->protocol;
1992 skb_reset_mac_header(skb);
1993
1994 /* Having put a fake header on the front of the sk_buff for the */
1995 /* benefit of tools like tcpdump, skb_pull now 'consumes' that */
1996 /* fake header before we hand the packet up to the next layer. */
1997 skb_pull(skb, sizeof(STRIP_Header));
1998
1999 /* Finally, hand the packet up to the next layer (e.g. IP or ARP, etc.) */
2000 strip_info->rx_packets++;
2001 strip_info->rx_pps_count++;
2002#ifdef EXT_COUNTERS
2003 strip_info->rx_bytes += packetlen;
2004#endif
2005 netif_rx(skb);
2006 }
2007}
2008
2009static void process_IP_packet(struct strip *strip_info,
2010 STRIP_Header * header, __u8 * ptr,
2011 __u8 * end)
2012{
2013 __u16 packetlen;
2014
2015 /* Decode start of the IP packet header */
2016 ptr = UnStuffData(ptr, end, strip_info->rx_buff, 4);
2017 if (!ptr) {
2018 RecvErr("IP Packet too short", strip_info);
2019 return;
2020 }
2021
2022 packetlen = ((__u16) strip_info->rx_buff[2] << 8) | strip_info->rx_buff[3];
2023
2024 if (packetlen > MAX_RECV_MTU) {
2025 printk(KERN_INFO "%s: Dropping oversized received IP packet: %d bytes\n",
2026 strip_info->dev->name, packetlen);
2027 strip_info->rx_dropped++;
2028 return;
2029 }
2030
2031 /*printk(KERN_INFO "%s: Got %d byte IP packet\n", strip_info->dev->name, packetlen); */
2032
2033 /* Decode remainder of the IP packet */
2034 ptr =
2035 UnStuffData(ptr, end, strip_info->rx_buff + 4, packetlen - 4);
2036 if (!ptr) {
2037 RecvErr("IP Packet too short", strip_info);
2038 return;
2039 }
2040
2041 if (ptr < end) {
2042 RecvErr("IP Packet too long", strip_info);
2043 return;
2044 }
2045
2046 header->protocol = htons(ETH_P_IP);
2047
2048 deliver_packet(strip_info, header, packetlen);
2049}
2050
2051static void process_ARP_packet(struct strip *strip_info,
2052 STRIP_Header * header, __u8 * ptr,
2053 __u8 * end)
2054{
2055 __u16 packetlen;
2056 struct arphdr *arphdr = (struct arphdr *) strip_info->rx_buff;
2057
2058 /* Decode start of the ARP packet */
2059 ptr = UnStuffData(ptr, end, strip_info->rx_buff, 8);
2060 if (!ptr) {
2061 RecvErr("ARP Packet too short", strip_info);
2062 return;
2063 }
2064
2065 packetlen = 8 + (arphdr->ar_hln + arphdr->ar_pln) * 2;
2066
2067 if (packetlen > MAX_RECV_MTU) {
2068 printk(KERN_INFO
2069 "%s: Dropping oversized received ARP packet: %d bytes\n",
2070 strip_info->dev->name, packetlen);
2071 strip_info->rx_dropped++;
2072 return;
2073 }
2074
2075 /*printk(KERN_INFO "%s: Got %d byte ARP %s\n",
2076 strip_info->dev->name, packetlen,
2077 ntohs(arphdr->ar_op) == ARPOP_REQUEST ? "request" : "reply"); */
2078
2079 /* Decode remainder of the ARP packet */
2080 ptr =
2081 UnStuffData(ptr, end, strip_info->rx_buff + 8, packetlen - 8);
2082 if (!ptr) {
2083 RecvErr("ARP Packet too short", strip_info);
2084 return;
2085 }
2086
2087 if (ptr < end) {
2088 RecvErr("ARP Packet too long", strip_info);
2089 return;
2090 }
2091
2092 header->protocol = htons(ETH_P_ARP);
2093
2094 deliver_packet(strip_info, header, packetlen);
2095}
2096
2097/*
2098 * process_text_message processes a <CR>-terminated block of data received
2099 * from the radio that doesn't begin with a '*' character. All normal
2100 * Starmode communication messages with the radio begin with a '*',
2101 * so any text that does not indicates a serial port error, a radio that
2102 * is in Hayes command mode instead of Starmode, or a radio with really
2103 * old firmware that doesn't frame its Starmode responses properly.
2104 */
2105static void process_text_message(struct strip *strip_info)
2106{
2107 __u8 *msg = strip_info->sx_buff;
2108 int len = strip_info->sx_count;
2109
2110 /* Check for anything that looks like it might be our radio name */
2111 /* (This is here for backwards compatibility with old firmware) */
2112 if (len == 9 && get_radio_address(strip_info, msg) == 0)
2113 return;
2114
2115 if (text_equal(msg, len, "OK"))
2116 return; /* Ignore 'OK' responses from prior commands */
2117 if (text_equal(msg, len, "ERROR"))
2118 return; /* Ignore 'ERROR' messages */
2119 if (has_prefix(msg, len, "ate0q1"))
2120 return; /* Ignore character echo back from the radio */
2121
2122 /* Catch other error messages */
2123 /* (This is here for backwards compatibility with old firmware) */
2124 if (has_prefix(msg, len, "ERR_")) {
2125 RecvErr_Message(strip_info, NULL, &msg[4], len - 4);
2126 return;
2127 }
2128
2129 RecvErr("No initial *", strip_info);
2130}
2131
2132/*
2133 * process_message processes a <CR>-terminated block of data received
2134 * from the radio. If the radio is not in Starmode or has old firmware,
2135 * it may be a line of text in response to an AT command. Ideally, with
2136 * a current radio that's properly in Starmode, all data received should
2137 * be properly framed and checksummed radio message blocks, containing
2138 * either a starmode packet, or a other communication from the radio
2139 * firmware, like "INF_" Info messages and &COMMAND responses.
2140 */
2141static void process_message(struct strip *strip_info)
2142{
2143 STRIP_Header header = { zero_address, zero_address, 0 };
2144 __u8 *ptr = strip_info->sx_buff;
2145 __u8 *end = strip_info->sx_buff + strip_info->sx_count;
2146 __u8 sendername[32], *sptr = sendername;
2147 MetricomKey key;
2148
2149 /*HexDump("Receiving", strip_info, ptr, end); */
2150
2151 /* Check for start of address marker, and then skip over it */
2152 if (*ptr == '*')
2153 ptr++;
2154 else {
2155 process_text_message(strip_info);
2156 return;
2157 }
2158
2159 /* Copy out the return address */
2160 while (ptr < end && *ptr != '*'
2161 && sptr < ARRAY_END(sendername) - 1)
2162 *sptr++ = *ptr++;
2163 *sptr = 0; /* Null terminate the sender name */
2164
2165 /* Check for end of address marker, and skip over it */
2166 if (ptr >= end || *ptr != '*') {
2167 RecvErr("No second *", strip_info);
2168 return;
2169 }
2170 ptr++; /* Skip the second '*' */
2171
2172 /* If the sender name is "&COMMAND", ignore this 'packet' */
2173 /* (This is here for backwards compatibility with old firmware) */
2174 if (!strcmp(sendername, "&COMMAND")) {
2175 strip_info->firmware_level = NoStructure;
2176 strip_info->next_command = CompatibilityCommand;
2177 return;
2178 }
2179
2180 if (ptr + 4 > end) {
2181 RecvErr("No proto key", strip_info);
2182 return;
2183 }
2184
2185 /* Get the protocol key out of the buffer */
2186 key.c[0] = *ptr++;
2187 key.c[1] = *ptr++;
2188 key.c[2] = *ptr++;
2189 key.c[3] = *ptr++;
2190
2191 /* If we're using checksums, verify the checksum at the end of the packet */
2192 if (strip_info->firmware_level >= ChecksummedMessages) {
2193 end -= 4; /* Chop the last four bytes off the packet (they're the checksum) */
2194 if (ptr > end) {
2195 RecvErr("Missing Checksum", strip_info);
2196 return;
2197 }
2198 if (!verify_checksum(strip_info)) {
2199 RecvErr("Bad Checksum", strip_info);
2200 return;
2201 }
2202 }
2203
2204 /*printk(KERN_INFO "%s: Got packet from \"%s\".\n", strip_info->dev->name, sendername); */
2205
2206 /*
2207 * Fill in (pseudo) source and destination addresses in the packet.
2208 * We assume that the destination address was our address (the radio does not
2209 * tell us this). If the radio supplies a source address, then we use it.
2210 */
2211 header.dst_addr = strip_info->true_dev_addr;
2212 string_to_radio_address(&header.src_addr, sendername);
2213
2214#ifdef EXT_COUNTERS
2215 if (key.l == SIP0Key.l) {
2216 strip_info->rx_rbytes += (end - ptr);
2217 process_IP_packet(strip_info, &header, ptr, end);
2218 } else if (key.l == ARP0Key.l) {
2219 strip_info->rx_rbytes += (end - ptr);
2220 process_ARP_packet(strip_info, &header, ptr, end);
2221 } else if (key.l == ATR_Key.l) {
2222 strip_info->rx_ebytes += (end - ptr);
2223 process_AT_response(strip_info, ptr, end);
2224 } else if (key.l == ACK_Key.l) {
2225 strip_info->rx_ebytes += (end - ptr);
2226 process_ACK(strip_info, ptr, end);
2227 } else if (key.l == INF_Key.l) {
2228 strip_info->rx_ebytes += (end - ptr);
2229 process_Info(strip_info, ptr, end);
2230 } else if (key.l == ERR_Key.l) {
2231 strip_info->rx_ebytes += (end - ptr);
2232 RecvErr_Message(strip_info, sendername, ptr, end - ptr);
2233 } else
2234 RecvErr("Unrecognized protocol key", strip_info);
2235#else
2236 if (key.l == SIP0Key.l)
2237 process_IP_packet(strip_info, &header, ptr, end);
2238 else if (key.l == ARP0Key.l)
2239 process_ARP_packet(strip_info, &header, ptr, end);
2240 else if (key.l == ATR_Key.l)
2241 process_AT_response(strip_info, ptr, end);
2242 else if (key.l == ACK_Key.l)
2243 process_ACK(strip_info, ptr, end);
2244 else if (key.l == INF_Key.l)
2245 process_Info(strip_info, ptr, end);
2246 else if (key.l == ERR_Key.l)
2247 RecvErr_Message(strip_info, sendername, ptr, end - ptr);
2248 else
2249 RecvErr("Unrecognized protocol key", strip_info);
2250#endif
2251}
2252
2253#define TTYERROR(X) ((X) == TTY_BREAK ? "Break" : \
2254 (X) == TTY_FRAME ? "Framing Error" : \
2255 (X) == TTY_PARITY ? "Parity Error" : \
2256 (X) == TTY_OVERRUN ? "Hardware Overrun" : "Unknown Error")
2257
2258/*
2259 * Handle the 'receiver data ready' interrupt.
2260 * This function is called by the 'tty_io' module in the kernel when
2261 * a block of STRIP data has been received, which can now be decapsulated
2262 * and sent on to some IP layer for further processing.
2263 */
2264
2265static void strip_receive_buf(struct tty_struct *tty, const unsigned char *cp,
2266 char *fp, int count)
2267{
2268 struct strip *strip_info = tty->disc_data;
2269 const unsigned char *end = cp + count;
2270
2271 if (!strip_info || strip_info->magic != STRIP_MAGIC
2272 || !netif_running(strip_info->dev))
2273 return;
2274
2275 spin_lock_bh(&strip_lock);
2276#if 0
2277 {
2278 struct timeval tv;
2279 do_gettimeofday(&tv);
2280 printk(KERN_INFO
2281 "**** strip_receive_buf: %3d bytes at %02d.%06d\n",
2282 count, tv.tv_sec % 100, tv.tv_usec);
2283 }
2284#endif
2285
2286#ifdef EXT_COUNTERS
2287 strip_info->rx_sbytes += count;
2288#endif
2289
2290 /* Read the characters out of the buffer */
2291 while (cp < end) {
2292 if (fp && *fp)
2293 printk(KERN_INFO "%s: %s on serial port\n",
2294 strip_info->dev->name, TTYERROR(*fp));
2295 if (fp && *fp++ && !strip_info->discard) { /* If there's a serial error, record it */
2296 /* If we have some characters in the buffer, discard them */
2297 strip_info->discard = strip_info->sx_count;
2298 strip_info->rx_errors++;
2299 }
2300
2301 /* Leading control characters (CR, NL, Tab, etc.) are ignored */
2302 if (strip_info->sx_count > 0 || *cp >= ' ') {
2303 if (*cp == 0x0D) { /* If end of packet, decide what to do with it */
2304 if (strip_info->sx_count > 3000)
2305 printk(KERN_INFO
2306 "%s: Cut a %d byte packet (%zd bytes remaining)%s\n",
2307 strip_info->dev->name,
2308 strip_info->sx_count,
2309 end - cp - 1,
2310 strip_info->
2311 discard ? " (discarded)" :
2312 "");
2313 if (strip_info->sx_count >
2314 strip_info->sx_size) {
2315 strip_info->rx_over_errors++;
2316 printk(KERN_INFO
2317 "%s: sx_buff overflow (%d bytes total)\n",
2318 strip_info->dev->name,
2319 strip_info->sx_count);
2320 } else if (strip_info->discard)
2321 printk(KERN_INFO
2322 "%s: Discarding bad packet (%d/%d)\n",
2323 strip_info->dev->name,
2324 strip_info->discard,
2325 strip_info->sx_count);
2326 else
2327 process_message(strip_info);
2328 strip_info->discard = 0;
2329 strip_info->sx_count = 0;
2330 } else {
2331 /* Make sure we have space in the buffer */
2332 if (strip_info->sx_count <
2333 strip_info->sx_size)
2334 strip_info->sx_buff[strip_info->
2335 sx_count] =
2336 *cp;
2337 strip_info->sx_count++;
2338 }
2339 }
2340 cp++;
2341 }
2342 spin_unlock_bh(&strip_lock);
2343}
2344
2345
2346/************************************************************************/
2347/* General control routines */
2348
2349static int set_mac_address(struct strip *strip_info,
2350 MetricomAddress * addr)
2351{
2352 /*
2353 * We're using a manually specified address if the address is set
2354 * to anything other than all ones. Setting the address to all ones
2355 * disables manual mode and goes back to automatic address determination
2356 * (tracking the true address that the radio has).
2357 */
2358 strip_info->manual_dev_addr =
2359 memcmp(addr->c, broadcast_address.c,
2360 sizeof(broadcast_address));
2361 if (strip_info->manual_dev_addr)
2362 *(MetricomAddress *) strip_info->dev->dev_addr = *addr;
2363 else
2364 *(MetricomAddress *) strip_info->dev->dev_addr =
2365 strip_info->true_dev_addr;
2366 return 0;
2367}
2368
2369static int strip_set_mac_address(struct net_device *dev, void *addr)
2370{
2371 struct strip *strip_info = netdev_priv(dev);
2372 struct sockaddr *sa = addr;
2373 printk(KERN_INFO "%s: strip_set_dev_mac_address called\n", dev->name);
2374 set_mac_address(strip_info, (MetricomAddress *) sa->sa_data);
2375 return 0;
2376}
2377
2378static struct net_device_stats *strip_get_stats(struct net_device *dev)
2379{
2380 struct strip *strip_info = netdev_priv(dev);
2381 static struct net_device_stats stats;
2382
2383 memset(&stats, 0, sizeof(struct net_device_stats));
2384
2385 stats.rx_packets = strip_info->rx_packets;
2386 stats.tx_packets = strip_info->tx_packets;
2387 stats.rx_dropped = strip_info->rx_dropped;
2388 stats.tx_dropped = strip_info->tx_dropped;
2389 stats.tx_errors = strip_info->tx_errors;
2390 stats.rx_errors = strip_info->rx_errors;
2391 stats.rx_over_errors = strip_info->rx_over_errors;
2392 return (&stats);
2393}
2394
2395
2396/************************************************************************/
2397/* Opening and closing */
2398
2399/*
2400 * Here's the order things happen:
2401 * When the user runs "slattach -p strip ..."
2402 * 1. The TTY module calls strip_open;;
2403 * 2. strip_open calls strip_alloc
2404 * 3. strip_alloc calls register_netdev
2405 * 4. register_netdev calls strip_dev_init
2406 * 5. then strip_open finishes setting up the strip_info
2407 *
2408 * When the user runs "ifconfig st<x> up address netmask ..."
2409 * 6. strip_open_low gets called
2410 *
2411 * When the user runs "ifconfig st<x> down"
2412 * 7. strip_close_low gets called
2413 *
2414 * When the user kills the slattach process
2415 * 8. strip_close gets called
2416 * 9. strip_close calls dev_close
2417 * 10. if the device is still up, then dev_close calls strip_close_low
2418 * 11. strip_close calls strip_free
2419 */
2420
2421/* Open the low-level part of the STRIP channel. Easy! */
2422
2423static int strip_open_low(struct net_device *dev)
2424{
2425 struct strip *strip_info = netdev_priv(dev);
2426
2427 if (strip_info->tty == NULL)
2428 return (-ENODEV);
2429
2430 if (!allocate_buffers(strip_info, dev->mtu))
2431 return (-ENOMEM);
2432
2433 strip_info->sx_count = 0;
2434 strip_info->tx_left = 0;
2435
2436 strip_info->discard = 0;
2437 strip_info->working = FALSE;
2438 strip_info->firmware_level = NoStructure;
2439 strip_info->next_command = CompatibilityCommand;
2440 strip_info->user_baud = tty_get_baud_rate(strip_info->tty);
2441
2442 printk(KERN_INFO "%s: Initializing Radio.\n",
2443 strip_info->dev->name);
2444 ResetRadio(strip_info);
2445 strip_info->idle_timer.expires = jiffies + 1 * HZ;
2446 add_timer(&strip_info->idle_timer);
2447 netif_wake_queue(dev);
2448 return (0);
2449}
2450
2451
2452/*
2453 * Close the low-level part of the STRIP channel. Easy!
2454 */
2455
2456static int strip_close_low(struct net_device *dev)
2457{
2458 struct strip *strip_info = netdev_priv(dev);
2459
2460 if (strip_info->tty == NULL)
2461 return -EBUSY;
2462 clear_bit(TTY_DO_WRITE_WAKEUP, &strip_info->tty->flags);
2463 netif_stop_queue(dev);
2464
2465 /*
2466 * Free all STRIP frame buffers.
2467 */
2468 kfree(strip_info->rx_buff);
2469 strip_info->rx_buff = NULL;
2470 kfree(strip_info->sx_buff);
2471 strip_info->sx_buff = NULL;
2472 kfree(strip_info->tx_buff);
2473 strip_info->tx_buff = NULL;
2474
2475 del_timer(&strip_info->idle_timer);
2476 return 0;
2477}
2478
2479static const struct header_ops strip_header_ops = {
2480 .create = strip_header,
2481 .rebuild = strip_rebuild_header,
2482};
2483
2484
2485static const struct net_device_ops strip_netdev_ops = {
2486 .ndo_open = strip_open_low,
2487 .ndo_stop = strip_close_low,
2488 .ndo_start_xmit = strip_xmit,
2489 .ndo_set_mac_address = strip_set_mac_address,
2490 .ndo_get_stats = strip_get_stats,
2491 .ndo_change_mtu = strip_change_mtu,
2492};
2493
2494/*
2495 * This routine is called by DDI when the
2496 * (dynamically assigned) device is registered
2497 */
2498
2499static void strip_dev_setup(struct net_device *dev)
2500{
2501 /*
2502 * Finish setting up the DEVICE info.
2503 */
2504
2505 dev->trans_start = 0;
2506 dev->tx_queue_len = 30; /* Drop after 30 frames queued */
2507
2508 dev->flags = 0;
2509 dev->mtu = DEFAULT_STRIP_MTU;
2510 dev->type = ARPHRD_METRICOM; /* dtang */
2511 dev->hard_header_len = sizeof(STRIP_Header);
2512 /*
2513 * netdev_priv(dev) Already holds a pointer to our struct strip
2514 */
2515
2516 *(MetricomAddress *)dev->broadcast = broadcast_address;
2517 dev->dev_addr[0] = 0;
2518 dev->addr_len = sizeof(MetricomAddress);
2519
2520 dev->header_ops = &strip_header_ops,
2521 dev->netdev_ops = &strip_netdev_ops;
2522}
2523
2524/*
2525 * Free a STRIP channel.
2526 */
2527
2528static void strip_free(struct strip *strip_info)
2529{
2530 spin_lock_bh(&strip_lock);
2531 list_del_rcu(&strip_info->list);
2532 spin_unlock_bh(&strip_lock);
2533
2534 strip_info->magic = 0;
2535
2536 free_netdev(strip_info->dev);
2537}
2538
2539
2540/*
2541 * Allocate a new free STRIP channel
2542 */
2543static struct strip *strip_alloc(void)
2544{
2545 struct list_head *n;
2546 struct net_device *dev;
2547 struct strip *strip_info;
2548
2549 dev = alloc_netdev(sizeof(struct strip), "st%d",
2550 strip_dev_setup);
2551
2552 if (!dev)
2553 return NULL; /* If no more memory, return */
2554
2555
2556 strip_info = netdev_priv(dev);
2557 strip_info->dev = dev;
2558
2559 strip_info->magic = STRIP_MAGIC;
2560 strip_info->tty = NULL;
2561
2562 strip_info->gratuitous_arp = jiffies + LongTime;
2563 strip_info->arp_interval = 0;
2564 init_timer(&strip_info->idle_timer);
2565 strip_info->idle_timer.data = (long) dev;
2566 strip_info->idle_timer.function = strip_IdleTask;
2567
2568
2569 spin_lock_bh(&strip_lock);
2570 rescan:
2571 /*
2572 * Search the list to find where to put our new entry
2573 * (and in the process decide what channel number it is
2574 * going to be)
2575 */
2576 list_for_each(n, &strip_list) {
2577 struct strip *s = hlist_entry(n, struct strip, list);
2578
2579 if (s->dev->base_addr == dev->base_addr) {
2580 ++dev->base_addr;
2581 goto rescan;
2582 }
2583 }
2584
2585 sprintf(dev->name, "st%ld", dev->base_addr);
2586
2587 list_add_tail_rcu(&strip_info->list, &strip_list);
2588 spin_unlock_bh(&strip_lock);
2589
2590 return strip_info;
2591}
2592
2593/*
2594 * Open the high-level part of the STRIP channel.
2595 * This function is called by the TTY module when the
2596 * STRIP line discipline is called for. Because we are
2597 * sure the tty line exists, we only have to link it to
2598 * a free STRIP channel...
2599 */
2600
2601static int strip_open(struct tty_struct *tty)
2602{
2603 struct strip *strip_info = tty->disc_data;
2604
2605 /*
2606 * First make sure we're not already connected.
2607 */
2608
2609 if (strip_info && strip_info->magic == STRIP_MAGIC)
2610 return -EEXIST;
2611
2612 /*
2613 * We need a write method.
2614 */
2615
2616 if (tty->ops->write == NULL || tty->ops->set_termios == NULL)
2617 return -EOPNOTSUPP;
2618
2619 /*
2620 * OK. Find a free STRIP channel to use.
2621 */
2622 if ((strip_info = strip_alloc()) == NULL)
2623 return -ENFILE;
2624
2625 /*
2626 * Register our newly created device so it can be ifconfig'd
2627 * strip_dev_init() will be called as a side-effect
2628 */
2629
2630 if (register_netdev(strip_info->dev) != 0) {
2631 printk(KERN_ERR "strip: register_netdev() failed.\n");
2632 strip_free(strip_info);
2633 return -ENFILE;
2634 }
2635
2636 strip_info->tty = tty;
2637 tty->disc_data = strip_info;
2638 tty->receive_room = 65536;
2639
2640 tty_driver_flush_buffer(tty);
2641
2642 /*
2643 * Restore default settings
2644 */
2645
2646 strip_info->dev->type = ARPHRD_METRICOM; /* dtang */
2647
2648 /*
2649 * Set tty options
2650 */
2651
2652 tty->termios->c_iflag |= IGNBRK | IGNPAR; /* Ignore breaks and parity errors. */
2653 tty->termios->c_cflag |= CLOCAL; /* Ignore modem control signals. */
2654 tty->termios->c_cflag &= ~HUPCL; /* Don't close on hup */
2655
2656 printk(KERN_INFO "STRIP: device \"%s\" activated\n",
2657 strip_info->dev->name);
2658
2659 /*
2660 * Done. We have linked the TTY line to a channel.
2661 */
2662 return (strip_info->dev->base_addr);
2663}
2664
2665/*
2666 * Close down a STRIP channel.
2667 * This means flushing out any pending queues, and then restoring the
2668 * TTY line discipline to what it was before it got hooked to STRIP
2669 * (which usually is TTY again).
2670 */
2671
2672static void strip_close(struct tty_struct *tty)
2673{
2674 struct strip *strip_info = tty->disc_data;
2675
2676 /*
2677 * First make sure we're connected.
2678 */
2679
2680 if (!strip_info || strip_info->magic != STRIP_MAGIC)
2681 return;
2682
2683 unregister_netdev(strip_info->dev);
2684
2685 tty->disc_data = NULL;
2686 strip_info->tty = NULL;
2687 printk(KERN_INFO "STRIP: device \"%s\" closed down\n",
2688 strip_info->dev->name);
2689 strip_free(strip_info);
2690 tty->disc_data = NULL;
2691}
2692
2693
2694/************************************************************************/
2695/* Perform I/O control calls on an active STRIP channel. */
2696
2697static int strip_ioctl(struct tty_struct *tty, struct file *file,
2698 unsigned int cmd, unsigned long arg)
2699{
2700 struct strip *strip_info = tty->disc_data;
2701
2702 /*
2703 * First make sure we're connected.
2704 */
2705
2706 if (!strip_info || strip_info->magic != STRIP_MAGIC)
2707 return -EINVAL;
2708
2709 switch (cmd) {
2710 case SIOCGIFNAME:
2711 if(copy_to_user((void __user *) arg, strip_info->dev->name, strlen(strip_info->dev->name) + 1))
2712 return -EFAULT;
2713 break;
2714 case SIOCSIFHWADDR:
2715 {
2716 MetricomAddress addr;
2717 //printk(KERN_INFO "%s: SIOCSIFHWADDR\n", strip_info->dev->name);
2718 if(copy_from_user(&addr, (void __user *) arg, sizeof(MetricomAddress)))
2719 return -EFAULT;
2720 return set_mac_address(strip_info, &addr);
2721 }
2722 default:
2723 return tty_mode_ioctl(tty, file, cmd, arg);
2724 break;
2725 }
2726 return 0;
2727}
2728
2729#ifdef CONFIG_COMPAT
2730static long strip_compat_ioctl(struct tty_struct *tty, struct file *file,
2731 unsigned int cmd, unsigned long arg)
2732{
2733 switch (cmd) {
2734 case SIOCGIFNAME:
2735 case SIOCSIFHWADDR:
2736 return strip_ioctl(tty, file, cmd,
2737 (unsigned long)compat_ptr(arg));
2738 }
2739 return -ENOIOCTLCMD;
2740}
2741#endif
2742
2743/************************************************************************/
2744/* Initialization */
2745
2746static struct tty_ldisc_ops strip_ldisc = {
2747 .magic = TTY_LDISC_MAGIC,
2748 .name = "strip",
2749 .owner = THIS_MODULE,
2750 .open = strip_open,
2751 .close = strip_close,
2752 .ioctl = strip_ioctl,
2753#ifdef CONFIG_COMPAT
2754 .compat_ioctl = strip_compat_ioctl,
2755#endif
2756 .receive_buf = strip_receive_buf,
2757 .write_wakeup = strip_write_some_more,
2758};
2759
2760/*
2761 * Initialize the STRIP driver.
2762 * This routine is called at boot time, to bootstrap the multi-channel
2763 * STRIP driver
2764 */
2765
2766static char signon[] __initdata =
2767 KERN_INFO "STRIP: Version %s (unlimited channels)\n";
2768
2769static int __init strip_init_driver(void)
2770{
2771 int status;
2772
2773 printk(signon, StripVersion);
2774
2775
2776 /*
2777 * Fill in our line protocol discipline, and register it
2778 */
2779 if ((status = tty_register_ldisc(N_STRIP, &strip_ldisc)))
2780 printk(KERN_ERR "STRIP: can't register line discipline (err = %d)\n",
2781 status);
2782
2783 /*
2784 * Register the status file with /proc
2785 */
2786 proc_net_fops_create(&init_net, "strip", S_IFREG | S_IRUGO, &strip_seq_fops);
2787
2788 return status;
2789}
2790
2791module_init(strip_init_driver);
2792
2793static const char signoff[] __exitdata =
2794 KERN_INFO "STRIP: Module Unloaded\n";
2795
2796static void __exit strip_exit_driver(void)
2797{
2798 int i;
2799 struct list_head *p,*n;
2800
2801 /* module ref count rules assure that all entries are unregistered */
2802 list_for_each_safe(p, n, &strip_list) {
2803 struct strip *s = list_entry(p, struct strip, list);
2804 strip_free(s);
2805 }
2806
2807 /* Unregister with the /proc/net file here. */
2808 proc_net_remove(&init_net, "strip");
2809
2810 if ((i = tty_unregister_ldisc(N_STRIP)))
2811 printk(KERN_ERR "STRIP: can't unregister line discipline (err = %d)\n", i);
2812
2813 printk(signoff);
2814}
2815
2816module_exit(strip_exit_driver);
2817
2818MODULE_AUTHOR("Stuart Cheshire <cheshire@cs.stanford.edu>");
2819MODULE_DESCRIPTION("Starmode Radio IP (STRIP) Device Driver");
2820MODULE_LICENSE("Dual BSD/GPL");
2821
2822MODULE_SUPPORTED_DEVICE("Starmode Radio IP (STRIP) modem");
diff --git a/drivers/net/wireless/wavelan.c b/drivers/net/wireless/wavelan.c
deleted file mode 100644
index d634b2da3b84..000000000000
--- a/drivers/net/wireless/wavelan.c
+++ /dev/null
@@ -1,4383 +0,0 @@
1/*
2 * WaveLAN ISA driver
3 *
4 * Jean II - HPLB '96
5 *
6 * Reorganisation and extension of the driver.
7 * Original copyright follows (also see the end of this file).
8 * See wavelan.p.h for details.
9 *
10 *
11 *
12 * AT&T GIS (nee NCR) WaveLAN card:
13 * An Ethernet-like radio transceiver
14 * controlled by an Intel 82586 coprocessor.
15 */
16
17#include "wavelan.p.h" /* Private header */
18
19/************************* MISC SUBROUTINES **************************/
20/*
21 * Subroutines which won't fit in one of the following category
22 * (WaveLAN modem or i82586)
23 */
24
25/*------------------------------------------------------------------*/
26/*
27 * Translate irq number to PSA irq parameter
28 */
29static u8 wv_irq_to_psa(int irq)
30{
31 if (irq < 0 || irq >= ARRAY_SIZE(irqvals))
32 return 0;
33
34 return irqvals[irq];
35}
36
37/*------------------------------------------------------------------*/
38/*
39 * Translate PSA irq parameter to irq number
40 */
41static int __init wv_psa_to_irq(u8 irqval)
42{
43 int i;
44
45 for (i = 0; i < ARRAY_SIZE(irqvals); i++)
46 if (irqvals[i] == irqval)
47 return i;
48
49 return -1;
50}
51
52/********************* HOST ADAPTER SUBROUTINES *********************/
53/*
54 * Useful subroutines to manage the WaveLAN ISA interface
55 *
56 * One major difference with the PCMCIA hardware (except the port mapping)
57 * is that we have to keep the state of the Host Control Register
58 * because of the interrupt enable & bus size flags.
59 */
60
61/*------------------------------------------------------------------*/
62/*
63 * Read from card's Host Adaptor Status Register.
64 */
65static inline u16 hasr_read(unsigned long ioaddr)
66{
67 return (inw(HASR(ioaddr)));
68} /* hasr_read */
69
70/*------------------------------------------------------------------*/
71/*
72 * Write to card's Host Adapter Command Register.
73 */
74static inline void hacr_write(unsigned long ioaddr, u16 hacr)
75{
76 outw(hacr, HACR(ioaddr));
77} /* hacr_write */
78
79/*------------------------------------------------------------------*/
80/*
81 * Write to card's Host Adapter Command Register. Include a delay for
82 * those times when it is needed.
83 */
84static void hacr_write_slow(unsigned long ioaddr, u16 hacr)
85{
86 hacr_write(ioaddr, hacr);
87 /* delay might only be needed sometimes */
88 mdelay(1);
89} /* hacr_write_slow */
90
91/*------------------------------------------------------------------*/
92/*
93 * Set the channel attention bit.
94 */
95static inline void set_chan_attn(unsigned long ioaddr, u16 hacr)
96{
97 hacr_write(ioaddr, hacr | HACR_CA);
98} /* set_chan_attn */
99
100/*------------------------------------------------------------------*/
101/*
102 * Reset, and then set host adaptor into default mode.
103 */
104static inline void wv_hacr_reset(unsigned long ioaddr)
105{
106 hacr_write_slow(ioaddr, HACR_RESET);
107 hacr_write(ioaddr, HACR_DEFAULT);
108} /* wv_hacr_reset */
109
110/*------------------------------------------------------------------*/
111/*
112 * Set the I/O transfer over the ISA bus to 8-bit mode
113 */
114static inline void wv_16_off(unsigned long ioaddr, u16 hacr)
115{
116 hacr &= ~HACR_16BITS;
117 hacr_write(ioaddr, hacr);
118} /* wv_16_off */
119
120/*------------------------------------------------------------------*/
121/*
122 * Set the I/O transfer over the ISA bus to 8-bit mode
123 */
124static inline void wv_16_on(unsigned long ioaddr, u16 hacr)
125{
126 hacr |= HACR_16BITS;
127 hacr_write(ioaddr, hacr);
128} /* wv_16_on */
129
130/*------------------------------------------------------------------*/
131/*
132 * Disable interrupts on the WaveLAN hardware.
133 * (called by wv_82586_stop())
134 */
135static inline void wv_ints_off(struct net_device * dev)
136{
137 net_local *lp = netdev_priv(dev);
138 unsigned long ioaddr = dev->base_addr;
139
140 lp->hacr &= ~HACR_INTRON;
141 hacr_write(ioaddr, lp->hacr);
142} /* wv_ints_off */
143
144/*------------------------------------------------------------------*/
145/*
146 * Enable interrupts on the WaveLAN hardware.
147 * (called by wv_hw_reset())
148 */
149static inline void wv_ints_on(struct net_device * dev)
150{
151 net_local *lp = netdev_priv(dev);
152 unsigned long ioaddr = dev->base_addr;
153
154 lp->hacr |= HACR_INTRON;
155 hacr_write(ioaddr, lp->hacr);
156} /* wv_ints_on */
157
158/******************* MODEM MANAGEMENT SUBROUTINES *******************/
159/*
160 * Useful subroutines to manage the modem of the WaveLAN
161 */
162
163/*------------------------------------------------------------------*/
164/*
165 * Read the Parameter Storage Area from the WaveLAN card's memory
166 */
167/*
168 * Read bytes from the PSA.
169 */
170static void psa_read(unsigned long ioaddr, u16 hacr, int o, /* offset in PSA */
171 u8 * b, /* buffer to fill */
172 int n)
173{ /* size to read */
174 wv_16_off(ioaddr, hacr);
175
176 while (n-- > 0) {
177 outw(o, PIOR2(ioaddr));
178 o++;
179 *b++ = inb(PIOP2(ioaddr));
180 }
181
182 wv_16_on(ioaddr, hacr);
183} /* psa_read */
184
185/*------------------------------------------------------------------*/
186/*
187 * Write the Parameter Storage Area to the WaveLAN card's memory.
188 */
189static void psa_write(unsigned long ioaddr, u16 hacr, int o, /* Offset in PSA */
190 u8 * b, /* Buffer in memory */
191 int n)
192{ /* Length of buffer */
193 int count = 0;
194
195 wv_16_off(ioaddr, hacr);
196
197 while (n-- > 0) {
198 outw(o, PIOR2(ioaddr));
199 o++;
200
201 outb(*b, PIOP2(ioaddr));
202 b++;
203
204 /* Wait for the memory to finish its write cycle */
205 count = 0;
206 while ((count++ < 100) &&
207 (hasr_read(ioaddr) & HASR_PSA_BUSY)) mdelay(1);
208 }
209
210 wv_16_on(ioaddr, hacr);
211} /* psa_write */
212
213#ifdef SET_PSA_CRC
214/*------------------------------------------------------------------*/
215/*
216 * Calculate the PSA CRC
217 * Thanks to Valster, Nico <NVALSTER@wcnd.nl.lucent.com> for the code
218 * NOTE: By specifying a length including the CRC position the
219 * returned value should be zero. (i.e. a correct checksum in the PSA)
220 *
221 * The Windows drivers don't use the CRC, but the AP and the PtP tool
222 * depend on it.
223 */
224static u16 psa_crc(u8 * psa, /* The PSA */
225 int size)
226{ /* Number of short for CRC */
227 int byte_cnt; /* Loop on the PSA */
228 u16 crc_bytes = 0; /* Data in the PSA */
229 int bit_cnt; /* Loop on the bits of the short */
230
231 for (byte_cnt = 0; byte_cnt < size; byte_cnt++) {
232 crc_bytes ^= psa[byte_cnt]; /* Its an xor */
233
234 for (bit_cnt = 1; bit_cnt < 9; bit_cnt++) {
235 if (crc_bytes & 0x0001)
236 crc_bytes = (crc_bytes >> 1) ^ 0xA001;
237 else
238 crc_bytes >>= 1;
239 }
240 }
241
242 return crc_bytes;
243} /* psa_crc */
244#endif /* SET_PSA_CRC */
245
246/*------------------------------------------------------------------*/
247/*
248 * update the checksum field in the Wavelan's PSA
249 */
250static void update_psa_checksum(struct net_device * dev, unsigned long ioaddr, u16 hacr)
251{
252#ifdef SET_PSA_CRC
253 psa_t psa;
254 u16 crc;
255
256 /* read the parameter storage area */
257 psa_read(ioaddr, hacr, 0, (unsigned char *) &psa, sizeof(psa));
258
259 /* update the checksum */
260 crc = psa_crc((unsigned char *) &psa,
261 sizeof(psa) - sizeof(psa.psa_crc[0]) -
262 sizeof(psa.psa_crc[1])
263 - sizeof(psa.psa_crc_status));
264
265 psa.psa_crc[0] = crc & 0xFF;
266 psa.psa_crc[1] = (crc & 0xFF00) >> 8;
267
268 /* Write it ! */
269 psa_write(ioaddr, hacr, (char *) &psa.psa_crc - (char *) &psa,
270 (unsigned char *) &psa.psa_crc, 2);
271
272#ifdef DEBUG_IOCTL_INFO
273 printk(KERN_DEBUG "%s: update_psa_checksum(): crc = 0x%02x%02x\n",
274 dev->name, psa.psa_crc[0], psa.psa_crc[1]);
275
276 /* Check again (luxury !) */
277 crc = psa_crc((unsigned char *) &psa,
278 sizeof(psa) - sizeof(psa.psa_crc_status));
279
280 if (crc != 0)
281 printk(KERN_WARNING
282 "%s: update_psa_checksum(): CRC does not agree with PSA data (even after recalculating)\n",
283 dev->name);
284#endif /* DEBUG_IOCTL_INFO */
285#endif /* SET_PSA_CRC */
286} /* update_psa_checksum */
287
288/*------------------------------------------------------------------*/
289/*
290 * Write 1 byte to the MMC.
291 */
292static void mmc_out(unsigned long ioaddr, u16 o, u8 d)
293{
294 int count = 0;
295
296 /* Wait for MMC to go idle */
297 while ((count++ < 100) && (inw(HASR(ioaddr)) & HASR_MMC_BUSY))
298 udelay(10);
299
300 outw((u16) (((u16) d << 8) | (o << 1) | 1), MMCR(ioaddr));
301}
302
303/*------------------------------------------------------------------*/
304/*
305 * Routine to write bytes to the Modem Management Controller.
306 * We start at the end because it is the way it should be!
307 */
308static void mmc_write(unsigned long ioaddr, u8 o, u8 * b, int n)
309{
310 o += n;
311 b += n;
312
313 while (n-- > 0)
314 mmc_out(ioaddr, --o, *(--b));
315} /* mmc_write */
316
317/*------------------------------------------------------------------*/
318/*
319 * Read a byte from the MMC.
320 * Optimised version for 1 byte, avoid using memory.
321 */
322static u8 mmc_in(unsigned long ioaddr, u16 o)
323{
324 int count = 0;
325
326 while ((count++ < 100) && (inw(HASR(ioaddr)) & HASR_MMC_BUSY))
327 udelay(10);
328 outw(o << 1, MMCR(ioaddr));
329
330 while ((count++ < 100) && (inw(HASR(ioaddr)) & HASR_MMC_BUSY))
331 udelay(10);
332 return (u8) (inw(MMCR(ioaddr)) >> 8);
333}
334
335/*------------------------------------------------------------------*/
336/*
337 * Routine to read bytes from the Modem Management Controller.
338 * The implementation is complicated by a lack of address lines,
339 * which prevents decoding of the low-order bit.
340 * (code has just been moved in the above function)
341 * We start at the end because it is the way it should be!
342 */
343static inline void mmc_read(unsigned long ioaddr, u8 o, u8 * b, int n)
344{
345 o += n;
346 b += n;
347
348 while (n-- > 0)
349 *(--b) = mmc_in(ioaddr, --o);
350} /* mmc_read */
351
352/*------------------------------------------------------------------*/
353/*
354 * Get the type of encryption available.
355 */
356static inline int mmc_encr(unsigned long ioaddr)
357{ /* I/O port of the card */
358 int temp;
359
360 temp = mmc_in(ioaddr, mmroff(0, mmr_des_avail));
361 if ((temp != MMR_DES_AVAIL_DES) && (temp != MMR_DES_AVAIL_AES))
362 return 0;
363 else
364 return temp;
365}
366
367/*------------------------------------------------------------------*/
368/*
369 * Wait for the frequency EEPROM to complete a command.
370 * I hope this one will be optimally inlined.
371 */
372static inline void fee_wait(unsigned long ioaddr, /* I/O port of the card */
373 int delay, /* Base delay to wait for */
374 int number)
375{ /* Number of time to wait */
376 int count = 0; /* Wait only a limited time */
377
378 while ((count++ < number) &&
379 (mmc_in(ioaddr, mmroff(0, mmr_fee_status)) &
380 MMR_FEE_STATUS_BUSY)) udelay(delay);
381}
382
383/*------------------------------------------------------------------*/
384/*
385 * Read bytes from the Frequency EEPROM (frequency select cards).
386 */
387static void fee_read(unsigned long ioaddr, /* I/O port of the card */
388 u16 o, /* destination offset */
389 u16 * b, /* data buffer */
390 int n)
391{ /* number of registers */
392 b += n; /* Position at the end of the area */
393
394 /* Write the address */
395 mmc_out(ioaddr, mmwoff(0, mmw_fee_addr), o + n - 1);
396
397 /* Loop on all buffer */
398 while (n-- > 0) {
399 /* Write the read command */
400 mmc_out(ioaddr, mmwoff(0, mmw_fee_ctrl),
401 MMW_FEE_CTRL_READ);
402
403 /* Wait until EEPROM is ready (should be quick). */
404 fee_wait(ioaddr, 10, 100);
405
406 /* Read the value. */
407 *--b = ((mmc_in(ioaddr, mmroff(0, mmr_fee_data_h)) << 8) |
408 mmc_in(ioaddr, mmroff(0, mmr_fee_data_l)));
409 }
410}
411
412
413/*------------------------------------------------------------------*/
414/*
415 * Write bytes from the Frequency EEPROM (frequency select cards).
416 * This is a bit complicated, because the frequency EEPROM has to
417 * be unprotected and the write enabled.
418 * Jean II
419 */
420static void fee_write(unsigned long ioaddr, /* I/O port of the card */
421 u16 o, /* destination offset */
422 u16 * b, /* data buffer */
423 int n)
424{ /* number of registers */
425 b += n; /* Position at the end of the area. */
426
427#ifdef EEPROM_IS_PROTECTED /* disabled */
428#ifdef DOESNT_SEEM_TO_WORK /* disabled */
429 /* Ask to read the protected register */
430 mmc_out(ioaddr, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRREAD);
431
432 fee_wait(ioaddr, 10, 100);
433
434 /* Read the protected register. */
435 printk("Protected 2: %02X-%02X\n",
436 mmc_in(ioaddr, mmroff(0, mmr_fee_data_h)),
437 mmc_in(ioaddr, mmroff(0, mmr_fee_data_l)));
438#endif /* DOESNT_SEEM_TO_WORK */
439
440 /* Enable protected register. */
441 mmc_out(ioaddr, mmwoff(0, mmw_fee_addr), MMW_FEE_ADDR_EN);
442 mmc_out(ioaddr, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PREN);
443
444 fee_wait(ioaddr, 10, 100);
445
446 /* Unprotect area. */
447 mmc_out(ioaddr, mmwoff(0, mmw_fee_addr), o + n);
448 mmc_out(ioaddr, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRWRITE);
449#ifdef DOESNT_SEEM_TO_WORK /* disabled */
450 /* or use: */
451 mmc_out(ioaddr, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRCLEAR);
452#endif /* DOESNT_SEEM_TO_WORK */
453
454 fee_wait(ioaddr, 10, 100);
455#endif /* EEPROM_IS_PROTECTED */
456
457 /* Write enable. */
458 mmc_out(ioaddr, mmwoff(0, mmw_fee_addr), MMW_FEE_ADDR_EN);
459 mmc_out(ioaddr, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_WREN);
460
461 fee_wait(ioaddr, 10, 100);
462
463 /* Write the EEPROM address. */
464 mmc_out(ioaddr, mmwoff(0, mmw_fee_addr), o + n - 1);
465
466 /* Loop on all buffer */
467 while (n-- > 0) {
468 /* Write the value. */
469 mmc_out(ioaddr, mmwoff(0, mmw_fee_data_h), (*--b) >> 8);
470 mmc_out(ioaddr, mmwoff(0, mmw_fee_data_l), *b & 0xFF);
471
472 /* Write the write command. */
473 mmc_out(ioaddr, mmwoff(0, mmw_fee_ctrl),
474 MMW_FEE_CTRL_WRITE);
475
476 /* WaveLAN documentation says to wait at least 10 ms for EEBUSY = 0 */
477 mdelay(10);
478 fee_wait(ioaddr, 10, 100);
479 }
480
481 /* Write disable. */
482 mmc_out(ioaddr, mmwoff(0, mmw_fee_addr), MMW_FEE_ADDR_DS);
483 mmc_out(ioaddr, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_WDS);
484
485 fee_wait(ioaddr, 10, 100);
486
487#ifdef EEPROM_IS_PROTECTED /* disabled */
488 /* Reprotect EEPROM. */
489 mmc_out(ioaddr, mmwoff(0, mmw_fee_addr), 0x00);
490 mmc_out(ioaddr, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRWRITE);
491
492 fee_wait(ioaddr, 10, 100);
493#endif /* EEPROM_IS_PROTECTED */
494}
495
496/************************ I82586 SUBROUTINES *************************/
497/*
498 * Useful subroutines to manage the Ethernet controller
499 */
500
501/*------------------------------------------------------------------*/
502/*
503 * Read bytes from the on-board RAM.
504 * Why does inlining this function make it fail?
505 */
506static /*inline */ void obram_read(unsigned long ioaddr,
507 u16 o, u8 * b, int n)
508{
509 outw(o, PIOR1(ioaddr));
510 insw(PIOP1(ioaddr), (unsigned short *) b, (n + 1) >> 1);
511}
512
513/*------------------------------------------------------------------*/
514/*
515 * Write bytes to the on-board RAM.
516 */
517static inline void obram_write(unsigned long ioaddr, u16 o, u8 * b, int n)
518{
519 outw(o, PIOR1(ioaddr));
520 outsw(PIOP1(ioaddr), (unsigned short *) b, (n + 1) >> 1);
521}
522
523/*------------------------------------------------------------------*/
524/*
525 * Acknowledge the reading of the status issued by the i82586.
526 */
527static void wv_ack(struct net_device * dev)
528{
529 net_local *lp = netdev_priv(dev);
530 unsigned long ioaddr = dev->base_addr;
531 u16 scb_cs;
532 int i;
533
534 obram_read(ioaddr, scboff(OFFSET_SCB, scb_status),
535 (unsigned char *) &scb_cs, sizeof(scb_cs));
536 scb_cs &= SCB_ST_INT;
537
538 if (scb_cs == 0)
539 return;
540
541 obram_write(ioaddr, scboff(OFFSET_SCB, scb_command),
542 (unsigned char *) &scb_cs, sizeof(scb_cs));
543
544 set_chan_attn(ioaddr, lp->hacr);
545
546 for (i = 1000; i > 0; i--) {
547 obram_read(ioaddr, scboff(OFFSET_SCB, scb_command),
548 (unsigned char *) &scb_cs, sizeof(scb_cs));
549 if (scb_cs == 0)
550 break;
551
552 udelay(10);
553 }
554 udelay(100);
555
556#ifdef DEBUG_CONFIG_ERROR
557 if (i <= 0)
558 printk(KERN_INFO
559 "%s: wv_ack(): board not accepting command.\n",
560 dev->name);
561#endif
562}
563
564/*------------------------------------------------------------------*/
565/*
566 * Set channel attention bit and busy wait until command has
567 * completed, then acknowledge completion of the command.
568 */
569static int wv_synchronous_cmd(struct net_device * dev, const char *str)
570{
571 net_local *lp = netdev_priv(dev);
572 unsigned long ioaddr = dev->base_addr;
573 u16 scb_cmd;
574 ach_t cb;
575 int i;
576
577 scb_cmd = SCB_CMD_CUC & SCB_CMD_CUC_GO;
578 obram_write(ioaddr, scboff(OFFSET_SCB, scb_command),
579 (unsigned char *) &scb_cmd, sizeof(scb_cmd));
580
581 set_chan_attn(ioaddr, lp->hacr);
582
583 for (i = 1000; i > 0; i--) {
584 obram_read(ioaddr, OFFSET_CU, (unsigned char *) &cb,
585 sizeof(cb));
586 if (cb.ac_status & AC_SFLD_C)
587 break;
588
589 udelay(10);
590 }
591 udelay(100);
592
593 if (i <= 0 || !(cb.ac_status & AC_SFLD_OK)) {
594#ifdef DEBUG_CONFIG_ERROR
595 printk(KERN_INFO "%s: %s failed; status = 0x%x\n",
596 dev->name, str, cb.ac_status);
597#endif
598#ifdef DEBUG_I82586_SHOW
599 wv_scb_show(ioaddr);
600#endif
601 return -1;
602 }
603
604 /* Ack the status */
605 wv_ack(dev);
606
607 return 0;
608}
609
610/*------------------------------------------------------------------*/
611/*
612 * Configuration commands completion interrupt.
613 * Check if done, and if OK.
614 */
615static int
616wv_config_complete(struct net_device * dev, unsigned long ioaddr, net_local * lp)
617{
618 unsigned short mcs_addr;
619 unsigned short status;
620 int ret;
621
622#ifdef DEBUG_INTERRUPT_TRACE
623 printk(KERN_DEBUG "%s: ->wv_config_complete()\n", dev->name);
624#endif
625
626 mcs_addr = lp->tx_first_in_use + sizeof(ac_tx_t) + sizeof(ac_nop_t)
627 + sizeof(tbd_t) + sizeof(ac_cfg_t) + sizeof(ac_ias_t);
628
629 /* Read the status of the last command (set mc list). */
630 obram_read(ioaddr, acoff(mcs_addr, ac_status),
631 (unsigned char *) &status, sizeof(status));
632
633 /* If not completed -> exit */
634 if ((status & AC_SFLD_C) == 0)
635 ret = 0; /* Not ready to be scrapped */
636 else {
637#ifdef DEBUG_CONFIG_ERROR
638 unsigned short cfg_addr;
639 unsigned short ias_addr;
640
641 /* Check mc_config command */
642 if ((status & AC_SFLD_OK) != AC_SFLD_OK)
643 printk(KERN_INFO
644 "%s: wv_config_complete(): set_multicast_address failed; status = 0x%x\n",
645 dev->name, status);
646
647 /* check ia-config command */
648 ias_addr = mcs_addr - sizeof(ac_ias_t);
649 obram_read(ioaddr, acoff(ias_addr, ac_status),
650 (unsigned char *) &status, sizeof(status));
651 if ((status & AC_SFLD_OK) != AC_SFLD_OK)
652 printk(KERN_INFO
653 "%s: wv_config_complete(): set_MAC_address failed; status = 0x%x\n",
654 dev->name, status);
655
656 /* Check config command. */
657 cfg_addr = ias_addr - sizeof(ac_cfg_t);
658 obram_read(ioaddr, acoff(cfg_addr, ac_status),
659 (unsigned char *) &status, sizeof(status));
660 if ((status & AC_SFLD_OK) != AC_SFLD_OK)
661 printk(KERN_INFO
662 "%s: wv_config_complete(): configure failed; status = 0x%x\n",
663 dev->name, status);
664#endif /* DEBUG_CONFIG_ERROR */
665
666 ret = 1; /* Ready to be scrapped */
667 }
668
669#ifdef DEBUG_INTERRUPT_TRACE
670 printk(KERN_DEBUG "%s: <-wv_config_complete() - %d\n", dev->name,
671 ret);
672#endif
673 return ret;
674}
675
676/*------------------------------------------------------------------*/
677/*
678 * Command completion interrupt.
679 * Reclaim as many freed tx buffers as we can.
680 * (called in wavelan_interrupt()).
681 * Note : the spinlock is already grabbed for us.
682 */
683static int wv_complete(struct net_device * dev, unsigned long ioaddr, net_local * lp)
684{
685 int nreaped = 0;
686
687#ifdef DEBUG_INTERRUPT_TRACE
688 printk(KERN_DEBUG "%s: ->wv_complete()\n", dev->name);
689#endif
690
691 /* Loop on all the transmit buffers */
692 while (lp->tx_first_in_use != I82586NULL) {
693 unsigned short tx_status;
694
695 /* Read the first transmit buffer */
696 obram_read(ioaddr, acoff(lp->tx_first_in_use, ac_status),
697 (unsigned char *) &tx_status,
698 sizeof(tx_status));
699
700 /* If not completed -> exit */
701 if ((tx_status & AC_SFLD_C) == 0)
702 break;
703
704 /* Hack for reconfiguration */
705 if (tx_status == 0xFFFF)
706 if (!wv_config_complete(dev, ioaddr, lp))
707 break; /* Not completed */
708
709 /* We now remove this buffer */
710 nreaped++;
711 --lp->tx_n_in_use;
712
713/*
714if (lp->tx_n_in_use > 0)
715 printk("%c", "0123456789abcdefghijk"[lp->tx_n_in_use]);
716*/
717
718 /* Was it the last one? */
719 if (lp->tx_n_in_use <= 0)
720 lp->tx_first_in_use = I82586NULL;
721 else {
722 /* Next one in the chain */
723 lp->tx_first_in_use += TXBLOCKZ;
724 if (lp->tx_first_in_use >=
725 OFFSET_CU +
726 NTXBLOCKS * TXBLOCKZ) lp->tx_first_in_use -=
727 NTXBLOCKS * TXBLOCKZ;
728 }
729
730 /* Hack for reconfiguration */
731 if (tx_status == 0xFFFF)
732 continue;
733
734 /* Now, check status of the finished command */
735 if (tx_status & AC_SFLD_OK) {
736 int ncollisions;
737
738 dev->stats.tx_packets++;
739 ncollisions = tx_status & AC_SFLD_MAXCOL;
740 dev->stats.collisions += ncollisions;
741#ifdef DEBUG_TX_INFO
742 if (ncollisions > 0)
743 printk(KERN_DEBUG
744 "%s: wv_complete(): tx completed after %d collisions.\n",
745 dev->name, ncollisions);
746#endif
747 } else {
748 dev->stats.tx_errors++;
749 if (tx_status & AC_SFLD_S10) {
750 dev->stats.tx_carrier_errors++;
751#ifdef DEBUG_TX_FAIL
752 printk(KERN_DEBUG
753 "%s: wv_complete(): tx error: no CS.\n",
754 dev->name);
755#endif
756 }
757 if (tx_status & AC_SFLD_S9) {
758 dev->stats.tx_carrier_errors++;
759#ifdef DEBUG_TX_FAIL
760 printk(KERN_DEBUG
761 "%s: wv_complete(): tx error: lost CTS.\n",
762 dev->name);
763#endif
764 }
765 if (tx_status & AC_SFLD_S8) {
766 dev->stats.tx_fifo_errors++;
767#ifdef DEBUG_TX_FAIL
768 printk(KERN_DEBUG
769 "%s: wv_complete(): tx error: slow DMA.\n",
770 dev->name);
771#endif
772 }
773 if (tx_status & AC_SFLD_S6) {
774 dev->stats.tx_heartbeat_errors++;
775#ifdef DEBUG_TX_FAIL
776 printk(KERN_DEBUG
777 "%s: wv_complete(): tx error: heart beat.\n",
778 dev->name);
779#endif
780 }
781 if (tx_status & AC_SFLD_S5) {
782 dev->stats.tx_aborted_errors++;
783#ifdef DEBUG_TX_FAIL
784 printk(KERN_DEBUG
785 "%s: wv_complete(): tx error: too many collisions.\n",
786 dev->name);
787#endif
788 }
789 }
790
791#ifdef DEBUG_TX_INFO
792 printk(KERN_DEBUG
793 "%s: wv_complete(): tx completed, tx_status 0x%04x\n",
794 dev->name, tx_status);
795#endif
796 }
797
798#ifdef DEBUG_INTERRUPT_INFO
799 if (nreaped > 1)
800 printk(KERN_DEBUG "%s: wv_complete(): reaped %d\n",
801 dev->name, nreaped);
802#endif
803
804 /*
805 * Inform upper layers.
806 */
807 if (lp->tx_n_in_use < NTXBLOCKS - 1) {
808 netif_wake_queue(dev);
809 }
810#ifdef DEBUG_INTERRUPT_TRACE
811 printk(KERN_DEBUG "%s: <-wv_complete()\n", dev->name);
812#endif
813 return nreaped;
814}
815
816/*------------------------------------------------------------------*/
817/*
818 * Reconfigure the i82586, or at least ask for it.
819 * Because wv_82586_config uses a transmission buffer, we must do it
820 * when we are sure that there is one left, so we do it now
821 * or in wavelan_packet_xmit() (I can't find any better place,
822 * wavelan_interrupt is not an option), so you may experience
823 * delays sometimes.
824 */
825static void wv_82586_reconfig(struct net_device * dev)
826{
827 net_local *lp = netdev_priv(dev);
828 unsigned long flags;
829
830 /* Arm the flag, will be cleard in wv_82586_config() */
831 lp->reconfig_82586 = 1;
832
833 /* Check if we can do it now ! */
834 if((netif_running(dev)) && !(netif_queue_stopped(dev))) {
835 spin_lock_irqsave(&lp->spinlock, flags);
836 /* May fail */
837 wv_82586_config(dev);
838 spin_unlock_irqrestore(&lp->spinlock, flags);
839 }
840 else {
841#ifdef DEBUG_CONFIG_INFO
842 printk(KERN_DEBUG
843 "%s: wv_82586_reconfig(): delayed (state = %lX)\n",
844 dev->name, dev->state);
845#endif
846 }
847}
848
849/********************* DEBUG & INFO SUBROUTINES *********************/
850/*
851 * This routine is used in the code to show information for debugging.
852 * Most of the time, it dumps the contents of hardware structures.
853 */
854
855#ifdef DEBUG_PSA_SHOW
856/*------------------------------------------------------------------*/
857/*
858 * Print the formatted contents of the Parameter Storage Area.
859 */
860static void wv_psa_show(psa_t * p)
861{
862 printk(KERN_DEBUG "##### WaveLAN PSA contents: #####\n");
863 printk(KERN_DEBUG "psa_io_base_addr_1: 0x%02X %02X %02X %02X\n",
864 p->psa_io_base_addr_1,
865 p->psa_io_base_addr_2,
866 p->psa_io_base_addr_3, p->psa_io_base_addr_4);
867 printk(KERN_DEBUG "psa_rem_boot_addr_1: 0x%02X %02X %02X\n",
868 p->psa_rem_boot_addr_1,
869 p->psa_rem_boot_addr_2, p->psa_rem_boot_addr_3);
870 printk(KERN_DEBUG "psa_holi_params: 0x%02x, ", p->psa_holi_params);
871 printk("psa_int_req_no: %d\n", p->psa_int_req_no);
872#ifdef DEBUG_SHOW_UNUSED
873 printk(KERN_DEBUG "psa_unused0[]: %pM\n", p->psa_unused0);
874#endif /* DEBUG_SHOW_UNUSED */
875 printk(KERN_DEBUG "psa_univ_mac_addr[]: %pM\n", p->psa_univ_mac_addr);
876 printk(KERN_DEBUG "psa_local_mac_addr[]: %pM\n", p->psa_local_mac_addr);
877 printk(KERN_DEBUG "psa_univ_local_sel: %d, ",
878 p->psa_univ_local_sel);
879 printk("psa_comp_number: %d, ", p->psa_comp_number);
880 printk("psa_thr_pre_set: 0x%02x\n", p->psa_thr_pre_set);
881 printk(KERN_DEBUG "psa_feature_select/decay_prm: 0x%02x, ",
882 p->psa_feature_select);
883 printk("psa_subband/decay_update_prm: %d\n", p->psa_subband);
884 printk(KERN_DEBUG "psa_quality_thr: 0x%02x, ", p->psa_quality_thr);
885 printk("psa_mod_delay: 0x%02x\n", p->psa_mod_delay);
886 printk(KERN_DEBUG "psa_nwid: 0x%02x%02x, ", p->psa_nwid[0],
887 p->psa_nwid[1]);
888 printk("psa_nwid_select: %d\n", p->psa_nwid_select);
889 printk(KERN_DEBUG "psa_encryption_select: %d, ",
890 p->psa_encryption_select);
891 printk
892 ("psa_encryption_key[]: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
893 p->psa_encryption_key[0], p->psa_encryption_key[1],
894 p->psa_encryption_key[2], p->psa_encryption_key[3],
895 p->psa_encryption_key[4], p->psa_encryption_key[5],
896 p->psa_encryption_key[6], p->psa_encryption_key[7]);
897 printk(KERN_DEBUG "psa_databus_width: %d\n", p->psa_databus_width);
898 printk(KERN_DEBUG "psa_call_code/auto_squelch: 0x%02x, ",
899 p->psa_call_code[0]);
900 printk
901 ("psa_call_code[]: %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
902 p->psa_call_code[0], p->psa_call_code[1], p->psa_call_code[2],
903 p->psa_call_code[3], p->psa_call_code[4], p->psa_call_code[5],
904 p->psa_call_code[6], p->psa_call_code[7]);
905#ifdef DEBUG_SHOW_UNUSED
906 printk(KERN_DEBUG "psa_reserved[]: %02X:%02X\n",
907 p->psa_reserved[0],
908 p->psa_reserved[1]);
909#endif /* DEBUG_SHOW_UNUSED */
910 printk(KERN_DEBUG "psa_conf_status: %d, ", p->psa_conf_status);
911 printk("psa_crc: 0x%02x%02x, ", p->psa_crc[0], p->psa_crc[1]);
912 printk("psa_crc_status: 0x%02x\n", p->psa_crc_status);
913} /* wv_psa_show */
914#endif /* DEBUG_PSA_SHOW */
915
916#ifdef DEBUG_MMC_SHOW
917/*------------------------------------------------------------------*/
918/*
919 * Print the formatted status of the Modem Management Controller.
920 * This function needs to be completed.
921 */
922static void wv_mmc_show(struct net_device * dev)
923{
924 unsigned long ioaddr = dev->base_addr;
925 net_local *lp = netdev_priv(dev);
926 mmr_t m;
927
928 /* Basic check */
929 if (hasr_read(ioaddr) & HASR_NO_CLK) {
930 printk(KERN_WARNING
931 "%s: wv_mmc_show: modem not connected\n",
932 dev->name);
933 return;
934 }
935
936 /* Read the mmc */
937 mmc_out(ioaddr, mmwoff(0, mmw_freeze), 1);
938 mmc_read(ioaddr, 0, (u8 *) & m, sizeof(m));
939 mmc_out(ioaddr, mmwoff(0, mmw_freeze), 0);
940
941 /* Don't forget to update statistics */
942 lp->wstats.discard.nwid +=
943 (m.mmr_wrong_nwid_h << 8) | m.mmr_wrong_nwid_l;
944
945 printk(KERN_DEBUG "##### WaveLAN modem status registers: #####\n");
946#ifdef DEBUG_SHOW_UNUSED
947 printk(KERN_DEBUG
948 "mmc_unused0[]: %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
949 m.mmr_unused0[0], m.mmr_unused0[1], m.mmr_unused0[2],
950 m.mmr_unused0[3], m.mmr_unused0[4], m.mmr_unused0[5],
951 m.mmr_unused0[6], m.mmr_unused0[7]);
952#endif /* DEBUG_SHOW_UNUSED */
953 printk(KERN_DEBUG "Encryption algorithm: %02X - Status: %02X\n",
954 m.mmr_des_avail, m.mmr_des_status);
955#ifdef DEBUG_SHOW_UNUSED
956 printk(KERN_DEBUG "mmc_unused1[]: %02X:%02X:%02X:%02X:%02X\n",
957 m.mmr_unused1[0],
958 m.mmr_unused1[1],
959 m.mmr_unused1[2], m.mmr_unused1[3], m.mmr_unused1[4]);
960#endif /* DEBUG_SHOW_UNUSED */
961 printk(KERN_DEBUG "dce_status: 0x%x [%s%s%s%s]\n",
962 m.mmr_dce_status,
963 (m.
964 mmr_dce_status & MMR_DCE_STATUS_RX_BUSY) ?
965 "energy detected," : "",
966 (m.
967 mmr_dce_status & MMR_DCE_STATUS_LOOPT_IND) ?
968 "loop test indicated," : "",
969 (m.
970 mmr_dce_status & MMR_DCE_STATUS_TX_BUSY) ?
971 "transmitter on," : "",
972 (m.
973 mmr_dce_status & MMR_DCE_STATUS_JBR_EXPIRED) ?
974 "jabber timer expired," : "");
975 printk(KERN_DEBUG "Dsp ID: %02X\n", m.mmr_dsp_id);
976#ifdef DEBUG_SHOW_UNUSED
977 printk(KERN_DEBUG "mmc_unused2[]: %02X:%02X\n",
978 m.mmr_unused2[0], m.mmr_unused2[1]);
979#endif /* DEBUG_SHOW_UNUSED */
980 printk(KERN_DEBUG "# correct_nwid: %d, # wrong_nwid: %d\n",
981 (m.mmr_correct_nwid_h << 8) | m.mmr_correct_nwid_l,
982 (m.mmr_wrong_nwid_h << 8) | m.mmr_wrong_nwid_l);
983 printk(KERN_DEBUG "thr_pre_set: 0x%x [current signal %s]\n",
984 m.mmr_thr_pre_set & MMR_THR_PRE_SET,
985 (m.
986 mmr_thr_pre_set & MMR_THR_PRE_SET_CUR) ? "above" :
987 "below");
988 printk(KERN_DEBUG "signal_lvl: %d [%s], ",
989 m.mmr_signal_lvl & MMR_SIGNAL_LVL,
990 (m.
991 mmr_signal_lvl & MMR_SIGNAL_LVL_VALID) ? "new msg" :
992 "no new msg");
993 printk("silence_lvl: %d [%s], ",
994 m.mmr_silence_lvl & MMR_SILENCE_LVL,
995 (m.
996 mmr_silence_lvl & MMR_SILENCE_LVL_VALID) ? "update done" :
997 "no new update");
998 printk("sgnl_qual: 0x%x [%s]\n", m.mmr_sgnl_qual & MMR_SGNL_QUAL,
999 (m.
1000 mmr_sgnl_qual & MMR_SGNL_QUAL_ANT) ? "Antenna 1" :
1001 "Antenna 0");
1002#ifdef DEBUG_SHOW_UNUSED
1003 printk(KERN_DEBUG "netw_id_l: %x\n", m.mmr_netw_id_l);
1004#endif /* DEBUG_SHOW_UNUSED */
1005} /* wv_mmc_show */
1006#endif /* DEBUG_MMC_SHOW */
1007
1008#ifdef DEBUG_I82586_SHOW
1009/*------------------------------------------------------------------*/
1010/*
1011 * Print the last block of the i82586 memory.
1012 */
1013static void wv_scb_show(unsigned long ioaddr)
1014{
1015 scb_t scb;
1016
1017 obram_read(ioaddr, OFFSET_SCB, (unsigned char *) &scb,
1018 sizeof(scb));
1019
1020 printk(KERN_DEBUG "##### WaveLAN system control block: #####\n");
1021
1022 printk(KERN_DEBUG "status: ");
1023 printk("stat 0x%x[%s%s%s%s] ",
1024 (scb.
1025 scb_status & (SCB_ST_CX | SCB_ST_FR | SCB_ST_CNA |
1026 SCB_ST_RNR)) >> 12,
1027 (scb.
1028 scb_status & SCB_ST_CX) ? "command completion interrupt," :
1029 "", (scb.scb_status & SCB_ST_FR) ? "frame received," : "",
1030 (scb.
1031 scb_status & SCB_ST_CNA) ? "command unit not active," : "",
1032 (scb.
1033 scb_status & SCB_ST_RNR) ? "receiving unit not ready," :
1034 "");
1035 printk("cus 0x%x[%s%s%s] ", (scb.scb_status & SCB_ST_CUS) >> 8,
1036 ((scb.scb_status & SCB_ST_CUS) ==
1037 SCB_ST_CUS_IDLE) ? "idle" : "",
1038 ((scb.scb_status & SCB_ST_CUS) ==
1039 SCB_ST_CUS_SUSP) ? "suspended" : "",
1040 ((scb.scb_status & SCB_ST_CUS) ==
1041 SCB_ST_CUS_ACTV) ? "active" : "");
1042 printk("rus 0x%x[%s%s%s%s]\n", (scb.scb_status & SCB_ST_RUS) >> 4,
1043 ((scb.scb_status & SCB_ST_RUS) ==
1044 SCB_ST_RUS_IDLE) ? "idle" : "",
1045 ((scb.scb_status & SCB_ST_RUS) ==
1046 SCB_ST_RUS_SUSP) ? "suspended" : "",
1047 ((scb.scb_status & SCB_ST_RUS) ==
1048 SCB_ST_RUS_NRES) ? "no resources" : "",
1049 ((scb.scb_status & SCB_ST_RUS) ==
1050 SCB_ST_RUS_RDY) ? "ready" : "");
1051
1052 printk(KERN_DEBUG "command: ");
1053 printk("ack 0x%x[%s%s%s%s] ",
1054 (scb.
1055 scb_command & (SCB_CMD_ACK_CX | SCB_CMD_ACK_FR |
1056 SCB_CMD_ACK_CNA | SCB_CMD_ACK_RNR)) >> 12,
1057 (scb.
1058 scb_command & SCB_CMD_ACK_CX) ? "ack cmd completion," : "",
1059 (scb.
1060 scb_command & SCB_CMD_ACK_FR) ? "ack frame received," : "",
1061 (scb.
1062 scb_command & SCB_CMD_ACK_CNA) ? "ack CU not active," : "",
1063 (scb.
1064 scb_command & SCB_CMD_ACK_RNR) ? "ack RU not ready," : "");
1065 printk("cuc 0x%x[%s%s%s%s%s] ",
1066 (scb.scb_command & SCB_CMD_CUC) >> 8,
1067 ((scb.scb_command & SCB_CMD_CUC) ==
1068 SCB_CMD_CUC_NOP) ? "nop" : "",
1069 ((scb.scb_command & SCB_CMD_CUC) ==
1070 SCB_CMD_CUC_GO) ? "start cbl_offset" : "",
1071 ((scb.scb_command & SCB_CMD_CUC) ==
1072 SCB_CMD_CUC_RES) ? "resume execution" : "",
1073 ((scb.scb_command & SCB_CMD_CUC) ==
1074 SCB_CMD_CUC_SUS) ? "suspend execution" : "",
1075 ((scb.scb_command & SCB_CMD_CUC) ==
1076 SCB_CMD_CUC_ABT) ? "abort execution" : "");
1077 printk("ruc 0x%x[%s%s%s%s%s]\n",
1078 (scb.scb_command & SCB_CMD_RUC) >> 4,
1079 ((scb.scb_command & SCB_CMD_RUC) ==
1080 SCB_CMD_RUC_NOP) ? "nop" : "",
1081 ((scb.scb_command & SCB_CMD_RUC) ==
1082 SCB_CMD_RUC_GO) ? "start rfa_offset" : "",
1083 ((scb.scb_command & SCB_CMD_RUC) ==
1084 SCB_CMD_RUC_RES) ? "resume reception" : "",
1085 ((scb.scb_command & SCB_CMD_RUC) ==
1086 SCB_CMD_RUC_SUS) ? "suspend reception" : "",
1087 ((scb.scb_command & SCB_CMD_RUC) ==
1088 SCB_CMD_RUC_ABT) ? "abort reception" : "");
1089
1090 printk(KERN_DEBUG "cbl_offset 0x%x ", scb.scb_cbl_offset);
1091 printk("rfa_offset 0x%x\n", scb.scb_rfa_offset);
1092
1093 printk(KERN_DEBUG "crcerrs %d ", scb.scb_crcerrs);
1094 printk("alnerrs %d ", scb.scb_alnerrs);
1095 printk("rscerrs %d ", scb.scb_rscerrs);
1096 printk("ovrnerrs %d\n", scb.scb_ovrnerrs);
1097}
1098
1099/*------------------------------------------------------------------*/
1100/*
1101 * Print the formatted status of the i82586's receive unit.
1102 */
1103static void wv_ru_show(struct net_device * dev)
1104{
1105 printk(KERN_DEBUG
1106 "##### WaveLAN i82586 receiver unit status: #####\n");
1107 printk(KERN_DEBUG "ru:");
1108 /*
1109 * Not implemented yet
1110 */
1111 printk("\n");
1112} /* wv_ru_show */
1113
1114/*------------------------------------------------------------------*/
1115/*
1116 * Display info about one control block of the i82586 memory.
1117 */
1118static void wv_cu_show_one(struct net_device * dev, net_local * lp, int i, u16 p)
1119{
1120 unsigned long ioaddr;
1121 ac_tx_t actx;
1122
1123 ioaddr = dev->base_addr;
1124
1125 printk("%d: 0x%x:", i, p);
1126
1127 obram_read(ioaddr, p, (unsigned char *) &actx, sizeof(actx));
1128 printk(" status=0x%x,", actx.tx_h.ac_status);
1129 printk(" command=0x%x,", actx.tx_h.ac_command);
1130
1131 /*
1132 {
1133 tbd_t tbd;
1134
1135 obram_read(ioaddr, actx.tx_tbd_offset, (unsigned char *)&tbd, sizeof(tbd));
1136 printk(" tbd_status=0x%x,", tbd.tbd_status);
1137 }
1138 */
1139
1140 printk("|");
1141}
1142
1143/*------------------------------------------------------------------*/
1144/*
1145 * Print status of the command unit of the i82586.
1146 */
1147static void wv_cu_show(struct net_device * dev)
1148{
1149 net_local *lp = netdev_priv(dev);
1150 unsigned int i;
1151 u16 p;
1152
1153 printk(KERN_DEBUG
1154 "##### WaveLAN i82586 command unit status: #####\n");
1155
1156 printk(KERN_DEBUG);
1157 for (i = 0, p = lp->tx_first_in_use; i < NTXBLOCKS; i++) {
1158 wv_cu_show_one(dev, lp, i, p);
1159
1160 p += TXBLOCKZ;
1161 if (p >= OFFSET_CU + NTXBLOCKS * TXBLOCKZ)
1162 p -= NTXBLOCKS * TXBLOCKZ;
1163 }
1164 printk("\n");
1165}
1166#endif /* DEBUG_I82586_SHOW */
1167
1168#ifdef DEBUG_DEVICE_SHOW
1169/*------------------------------------------------------------------*/
1170/*
1171 * Print the formatted status of the WaveLAN PCMCIA device driver.
1172 */
1173static void wv_dev_show(struct net_device * dev)
1174{
1175 printk(KERN_DEBUG "dev:");
1176 printk(" state=%lX,", dev->state);
1177 printk(" trans_start=%ld,", dev->trans_start);
1178 printk(" flags=0x%x,", dev->flags);
1179 printk("\n");
1180} /* wv_dev_show */
1181
1182/*------------------------------------------------------------------*/
1183/*
1184 * Print the formatted status of the WaveLAN PCMCIA device driver's
1185 * private information.
1186 */
1187static void wv_local_show(struct net_device * dev)
1188{
1189 net_local *lp;
1190
1191 lp = netdev_priv(dev);
1192
1193 printk(KERN_DEBUG "local:");
1194 printk(" tx_n_in_use=%d,", lp->tx_n_in_use);
1195 printk(" hacr=0x%x,", lp->hacr);
1196 printk(" rx_head=0x%x,", lp->rx_head);
1197 printk(" rx_last=0x%x,", lp->rx_last);
1198 printk(" tx_first_free=0x%x,", lp->tx_first_free);
1199 printk(" tx_first_in_use=0x%x,", lp->tx_first_in_use);
1200 printk("\n");
1201} /* wv_local_show */
1202#endif /* DEBUG_DEVICE_SHOW */
1203
1204#if defined(DEBUG_RX_INFO) || defined(DEBUG_TX_INFO)
1205/*------------------------------------------------------------------*/
1206/*
1207 * Dump packet header (and content if necessary) on the screen
1208 */
1209static inline void wv_packet_info(u8 * p, /* Packet to dump */
1210 int length, /* Length of the packet */
1211 char *msg1, /* Name of the device */
1212 char *msg2)
1213{ /* Name of the function */
1214 int i;
1215 int maxi;
1216
1217 printk(KERN_DEBUG
1218 "%s: %s(): dest %pM, length %d\n",
1219 msg1, msg2, p, length);
1220 printk(KERN_DEBUG
1221 "%s: %s(): src %pM, type 0x%02X%02X\n",
1222 msg1, msg2, &p[6], p[12], p[13]);
1223
1224#ifdef DEBUG_PACKET_DUMP
1225
1226 printk(KERN_DEBUG "data=\"");
1227
1228 if ((maxi = length) > DEBUG_PACKET_DUMP)
1229 maxi = DEBUG_PACKET_DUMP;
1230 for (i = 14; i < maxi; i++)
1231 if (p[i] >= ' ' && p[i] <= '~')
1232 printk(" %c", p[i]);
1233 else
1234 printk("%02X", p[i]);
1235 if (maxi < length)
1236 printk("..");
1237 printk("\"\n");
1238 printk(KERN_DEBUG "\n");
1239#endif /* DEBUG_PACKET_DUMP */
1240}
1241#endif /* defined(DEBUG_RX_INFO) || defined(DEBUG_TX_INFO) */
1242
1243/*------------------------------------------------------------------*/
1244/*
1245 * This is the information which is displayed by the driver at startup.
1246 * There are lots of flags for configuring it to your liking.
1247 */
1248static void wv_init_info(struct net_device * dev)
1249{
1250 short ioaddr = dev->base_addr;
1251 net_local *lp = netdev_priv(dev);
1252 psa_t psa;
1253
1254 /* Read the parameter storage area */
1255 psa_read(ioaddr, lp->hacr, 0, (unsigned char *) &psa, sizeof(psa));
1256
1257#ifdef DEBUG_PSA_SHOW
1258 wv_psa_show(&psa);
1259#endif
1260#ifdef DEBUG_MMC_SHOW
1261 wv_mmc_show(dev);
1262#endif
1263#ifdef DEBUG_I82586_SHOW
1264 wv_cu_show(dev);
1265#endif
1266
1267#ifdef DEBUG_BASIC_SHOW
1268 /* Now, let's go for the basic stuff. */
1269 printk(KERN_NOTICE "%s: WaveLAN at %#x, %pM, IRQ %d",
1270 dev->name, ioaddr, dev->dev_addr, dev->irq);
1271
1272 /* Print current network ID. */
1273 if (psa.psa_nwid_select)
1274 printk(", nwid 0x%02X-%02X", psa.psa_nwid[0],
1275 psa.psa_nwid[1]);
1276 else
1277 printk(", nwid off");
1278
1279 /* If 2.00 card */
1280 if (!(mmc_in(ioaddr, mmroff(0, mmr_fee_status)) &
1281 (MMR_FEE_STATUS_DWLD | MMR_FEE_STATUS_BUSY))) {
1282 unsigned short freq;
1283
1284 /* Ask the EEPROM to read the frequency from the first area. */
1285 fee_read(ioaddr, 0x00, &freq, 1);
1286
1287 /* Print frequency */
1288 printk(", 2.00, %ld", (freq >> 6) + 2400L);
1289
1290 /* Hack! */
1291 if (freq & 0x20)
1292 printk(".5");
1293 } else {
1294 printk(", PC");
1295 switch (psa.psa_comp_number) {
1296 case PSA_COMP_PC_AT_915:
1297 case PSA_COMP_PC_AT_2400:
1298 printk("-AT");
1299 break;
1300 case PSA_COMP_PC_MC_915:
1301 case PSA_COMP_PC_MC_2400:
1302 printk("-MC");
1303 break;
1304 case PSA_COMP_PCMCIA_915:
1305 printk("MCIA");
1306 break;
1307 default:
1308 printk("?");
1309 }
1310 printk(", ");
1311 switch (psa.psa_subband) {
1312 case PSA_SUBBAND_915:
1313 printk("915");
1314 break;
1315 case PSA_SUBBAND_2425:
1316 printk("2425");
1317 break;
1318 case PSA_SUBBAND_2460:
1319 printk("2460");
1320 break;
1321 case PSA_SUBBAND_2484:
1322 printk("2484");
1323 break;
1324 case PSA_SUBBAND_2430_5:
1325 printk("2430.5");
1326 break;
1327 default:
1328 printk("?");
1329 }
1330 }
1331
1332 printk(" MHz\n");
1333#endif /* DEBUG_BASIC_SHOW */
1334
1335#ifdef DEBUG_VERSION_SHOW
1336 /* Print version information */
1337 printk(KERN_NOTICE "%s", version);
1338#endif
1339} /* wv_init_info */
1340
1341/********************* IOCTL, STATS & RECONFIG *********************/
1342/*
1343 * We found here routines that are called by Linux on different
1344 * occasions after the configuration and not for transmitting data
1345 * These may be called when the user use ifconfig, /proc/net/dev
1346 * or wireless extensions
1347 */
1348
1349
1350/*------------------------------------------------------------------*/
1351/*
1352 * Set or clear the multicast filter for this adaptor.
1353 * num_addrs == -1 Promiscuous mode, receive all packets
1354 * num_addrs == 0 Normal mode, clear multicast list
1355 * num_addrs > 0 Multicast mode, receive normal and MC packets,
1356 * and do best-effort filtering.
1357 */
1358static void wavelan_set_multicast_list(struct net_device * dev)
1359{
1360 net_local *lp = netdev_priv(dev);
1361
1362#ifdef DEBUG_IOCTL_TRACE
1363 printk(KERN_DEBUG "%s: ->wavelan_set_multicast_list()\n",
1364 dev->name);
1365#endif
1366
1367#ifdef DEBUG_IOCTL_INFO
1368 printk(KERN_DEBUG
1369 "%s: wavelan_set_multicast_list(): setting Rx mode %02X to %d addresses.\n",
1370 dev->name, dev->flags, dev->mc_count);
1371#endif
1372
1373 /* Are we asking for promiscuous mode,
1374 * or all multicast addresses (we don't have that!)
1375 * or too many multicast addresses for the hardware filter? */
1376 if ((dev->flags & IFF_PROMISC) ||
1377 (dev->flags & IFF_ALLMULTI) ||
1378 (dev->mc_count > I82586_MAX_MULTICAST_ADDRESSES)) {
1379 /*
1380 * Enable promiscuous mode: receive all packets.
1381 */
1382 if (!lp->promiscuous) {
1383 lp->promiscuous = 1;
1384 lp->mc_count = 0;
1385
1386 wv_82586_reconfig(dev);
1387 }
1388 } else
1389 /* Are there multicast addresses to send? */
1390 if (dev->mc_list != (struct dev_mc_list *) NULL) {
1391 /*
1392 * Disable promiscuous mode, but receive all packets
1393 * in multicast list
1394 */
1395#ifdef MULTICAST_AVOID
1396 if (lp->promiscuous || (dev->mc_count != lp->mc_count))
1397#endif
1398 {
1399 lp->promiscuous = 0;
1400 lp->mc_count = dev->mc_count;
1401
1402 wv_82586_reconfig(dev);
1403 }
1404 } else {
1405 /*
1406 * Switch to normal mode: disable promiscuous mode and
1407 * clear the multicast list.
1408 */
1409 if (lp->promiscuous || lp->mc_count == 0) {
1410 lp->promiscuous = 0;
1411 lp->mc_count = 0;
1412
1413 wv_82586_reconfig(dev);
1414 }
1415 }
1416#ifdef DEBUG_IOCTL_TRACE
1417 printk(KERN_DEBUG "%s: <-wavelan_set_multicast_list()\n",
1418 dev->name);
1419#endif
1420}
1421
1422/*------------------------------------------------------------------*/
1423/*
1424 * This function doesn't exist.
1425 * (Note : it was a nice way to test the reconfigure stuff...)
1426 */
1427#ifdef SET_MAC_ADDRESS
1428static int wavelan_set_mac_address(struct net_device * dev, void *addr)
1429{
1430 struct sockaddr *mac = addr;
1431
1432 /* Copy the address. */
1433 memcpy(dev->dev_addr, mac->sa_data, WAVELAN_ADDR_SIZE);
1434
1435 /* Reconfigure the beast. */
1436 wv_82586_reconfig(dev);
1437
1438 return 0;
1439}
1440#endif /* SET_MAC_ADDRESS */
1441
1442
1443/*------------------------------------------------------------------*/
1444/*
1445 * Frequency setting (for hardware capable of it)
1446 * It's a bit complicated and you don't really want to look into it.
1447 * (called in wavelan_ioctl)
1448 */
1449static int wv_set_frequency(unsigned long ioaddr, /* I/O port of the card */
1450 iw_freq * frequency)
1451{
1452 const int BAND_NUM = 10; /* Number of bands */
1453 long freq = 0L; /* offset to 2.4 GHz in .5 MHz */
1454#ifdef DEBUG_IOCTL_INFO
1455 int i;
1456#endif
1457
1458 /* Setting by frequency */
1459 /* Theoretically, you may set any frequency between
1460 * the two limits with a 0.5 MHz precision. In practice,
1461 * I don't want you to have trouble with local regulations.
1462 */
1463 if ((frequency->e == 1) &&
1464 (frequency->m >= (int) 2.412e8)
1465 && (frequency->m <= (int) 2.487e8)) {
1466 freq = ((frequency->m / 10000) - 24000L) / 5;
1467 }
1468
1469 /* Setting by channel (same as wfreqsel) */
1470 /* Warning: each channel is 22 MHz wide, so some of the channels
1471 * will interfere. */
1472 if ((frequency->e == 0) && (frequency->m < BAND_NUM)) {
1473 /* Get frequency offset. */
1474 freq = channel_bands[frequency->m] >> 1;
1475 }
1476
1477 /* Verify that the frequency is allowed. */
1478 if (freq != 0L) {
1479 u16 table[10]; /* Authorized frequency table */
1480
1481 /* Read the frequency table. */
1482 fee_read(ioaddr, 0x71, table, 10);
1483
1484#ifdef DEBUG_IOCTL_INFO
1485 printk(KERN_DEBUG "Frequency table: ");
1486 for (i = 0; i < 10; i++) {
1487 printk(" %04X", table[i]);
1488 }
1489 printk("\n");
1490#endif
1491
1492 /* Look in the table to see whether the frequency is allowed. */
1493 if (!(table[9 - ((freq - 24) / 16)] &
1494 (1 << ((freq - 24) % 16)))) return -EINVAL; /* not allowed */
1495 } else
1496 return -EINVAL;
1497
1498 /* if we get a usable frequency */
1499 if (freq != 0L) {
1500 unsigned short area[16];
1501 unsigned short dac[2];
1502 unsigned short area_verify[16];
1503 unsigned short dac_verify[2];
1504 /* Corresponding gain (in the power adjust value table)
1505 * See AT&T WaveLAN Data Manual, REF 407-024689/E, page 3-8
1506 * and WCIN062D.DOC, page 6.2.9. */
1507 unsigned short power_limit[] = { 40, 80, 120, 160, 0 };
1508 int power_band = 0; /* Selected band */
1509 unsigned short power_adjust; /* Correct value */
1510
1511 /* Search for the gain. */
1512 power_band = 0;
1513 while ((freq > power_limit[power_band]) &&
1514 (power_limit[++power_band] != 0));
1515
1516 /* Read the first area. */
1517 fee_read(ioaddr, 0x00, area, 16);
1518
1519 /* Read the DAC. */
1520 fee_read(ioaddr, 0x60, dac, 2);
1521
1522 /* Read the new power adjust value. */
1523 fee_read(ioaddr, 0x6B - (power_band >> 1), &power_adjust,
1524 1);
1525 if (power_band & 0x1)
1526 power_adjust >>= 8;
1527 else
1528 power_adjust &= 0xFF;
1529
1530#ifdef DEBUG_IOCTL_INFO
1531 printk(KERN_DEBUG "WaveLAN EEPROM Area 1: ");
1532 for (i = 0; i < 16; i++) {
1533 printk(" %04X", area[i]);
1534 }
1535 printk("\n");
1536
1537 printk(KERN_DEBUG "WaveLAN EEPROM DAC: %04X %04X\n",
1538 dac[0], dac[1]);
1539#endif
1540
1541 /* Frequency offset (for info only) */
1542 area[0] = ((freq << 5) & 0xFFE0) | (area[0] & 0x1F);
1543
1544 /* Receiver Principle main divider coefficient */
1545 area[3] = (freq >> 1) + 2400L - 352L;
1546 area[2] = ((freq & 0x1) << 4) | (area[2] & 0xFFEF);
1547
1548 /* Transmitter Main divider coefficient */
1549 area[13] = (freq >> 1) + 2400L;
1550 area[12] = ((freq & 0x1) << 4) | (area[2] & 0xFFEF);
1551
1552 /* Other parts of the area are flags, bit streams or unused. */
1553
1554 /* Set the value in the DAC. */
1555 dac[1] = ((power_adjust >> 1) & 0x7F) | (dac[1] & 0xFF80);
1556 dac[0] = ((power_adjust & 0x1) << 4) | (dac[0] & 0xFFEF);
1557
1558 /* Write the first area. */
1559 fee_write(ioaddr, 0x00, area, 16);
1560
1561 /* Write the DAC. */
1562 fee_write(ioaddr, 0x60, dac, 2);
1563
1564 /* We now should verify here that the writing of the EEPROM went OK. */
1565
1566 /* Reread the first area. */
1567 fee_read(ioaddr, 0x00, area_verify, 16);
1568
1569 /* Reread the DAC. */
1570 fee_read(ioaddr, 0x60, dac_verify, 2);
1571
1572 /* Compare. */
1573 if (memcmp(area, area_verify, 16 * 2) ||
1574 memcmp(dac, dac_verify, 2 * 2)) {
1575#ifdef DEBUG_IOCTL_ERROR
1576 printk(KERN_INFO
1577 "WaveLAN: wv_set_frequency: unable to write new frequency to EEPROM(?).\n");
1578#endif
1579 return -EOPNOTSUPP;
1580 }
1581
1582 /* We must download the frequency parameters to the
1583 * synthesizers (from the EEPROM - area 1)
1584 * Note: as the EEPROM is automatically decremented, we set the end
1585 * if the area... */
1586 mmc_out(ioaddr, mmwoff(0, mmw_fee_addr), 0x0F);
1587 mmc_out(ioaddr, mmwoff(0, mmw_fee_ctrl),
1588 MMW_FEE_CTRL_READ | MMW_FEE_CTRL_DWLD);
1589
1590 /* Wait until the download is finished. */
1591 fee_wait(ioaddr, 100, 100);
1592
1593 /* We must now download the power adjust value (gain) to
1594 * the synthesizers (from the EEPROM - area 7 - DAC). */
1595 mmc_out(ioaddr, mmwoff(0, mmw_fee_addr), 0x61);
1596 mmc_out(ioaddr, mmwoff(0, mmw_fee_ctrl),
1597 MMW_FEE_CTRL_READ | MMW_FEE_CTRL_DWLD);
1598
1599 /* Wait for the download to finish. */
1600 fee_wait(ioaddr, 100, 100);
1601
1602#ifdef DEBUG_IOCTL_INFO
1603 /* Verification of what we have done */
1604
1605 printk(KERN_DEBUG "WaveLAN EEPROM Area 1: ");
1606 for (i = 0; i < 16; i++) {
1607 printk(" %04X", area_verify[i]);
1608 }
1609 printk("\n");
1610
1611 printk(KERN_DEBUG "WaveLAN EEPROM DAC: %04X %04X\n",
1612 dac_verify[0], dac_verify[1]);
1613#endif
1614
1615 return 0;
1616 } else
1617 return -EINVAL; /* Bah, never get there... */
1618}
1619
1620/*------------------------------------------------------------------*/
1621/*
1622 * Give the list of available frequencies.
1623 */
1624static int wv_frequency_list(unsigned long ioaddr, /* I/O port of the card */
1625 iw_freq * list, /* List of frequencies to fill */
1626 int max)
1627{ /* Maximum number of frequencies */
1628 u16 table[10]; /* Authorized frequency table */
1629 long freq = 0L; /* offset to 2.4 GHz in .5 MHz + 12 MHz */
1630 int i; /* index in the table */
1631 int c = 0; /* Channel number */
1632
1633 /* Read the frequency table. */
1634 fee_read(ioaddr, 0x71 /* frequency table */ , table, 10);
1635
1636 /* Check all frequencies. */
1637 i = 0;
1638 for (freq = 0; freq < 150; freq++)
1639 /* Look in the table if the frequency is allowed */
1640 if (table[9 - (freq / 16)] & (1 << (freq % 16))) {
1641 /* Compute approximate channel number */
1642 while ((c < ARRAY_SIZE(channel_bands)) &&
1643 (((channel_bands[c] >> 1) - 24) < freq))
1644 c++;
1645 list[i].i = c; /* Set the list index */
1646
1647 /* put in the list */
1648 list[i].m = (((freq + 24) * 5) + 24000L) * 10000;
1649 list[i++].e = 1;
1650
1651 /* Check number. */
1652 if (i >= max)
1653 return (i);
1654 }
1655
1656 return (i);
1657}
1658
1659#ifdef IW_WIRELESS_SPY
1660/*------------------------------------------------------------------*/
1661/*
1662 * Gather wireless spy statistics: for each packet, compare the source
1663 * address with our list, and if they match, get the statistics.
1664 * Sorry, but this function really needs the wireless extensions.
1665 */
1666static inline void wl_spy_gather(struct net_device * dev,
1667 u8 * mac, /* MAC address */
1668 u8 * stats) /* Statistics to gather */
1669{
1670 struct iw_quality wstats;
1671
1672 wstats.qual = stats[2] & MMR_SGNL_QUAL;
1673 wstats.level = stats[0] & MMR_SIGNAL_LVL;
1674 wstats.noise = stats[1] & MMR_SILENCE_LVL;
1675 wstats.updated = 0x7;
1676
1677 /* Update spy records */
1678 wireless_spy_update(dev, mac, &wstats);
1679}
1680#endif /* IW_WIRELESS_SPY */
1681
1682#ifdef HISTOGRAM
1683/*------------------------------------------------------------------*/
1684/*
1685 * This function calculates a histogram of the signal level.
1686 * As the noise is quite constant, it's like doing it on the SNR.
1687 * We have defined a set of interval (lp->his_range), and each time
1688 * the level goes in that interval, we increment the count (lp->his_sum).
1689 * With this histogram you may detect if one WaveLAN is really weak,
1690 * or you may also calculate the mean and standard deviation of the level.
1691 */
1692static inline void wl_his_gather(struct net_device * dev, u8 * stats)
1693{ /* Statistics to gather */
1694 net_local *lp = netdev_priv(dev);
1695 u8 level = stats[0] & MMR_SIGNAL_LVL;
1696 int i;
1697
1698 /* Find the correct interval. */
1699 i = 0;
1700 while ((i < (lp->his_number - 1))
1701 && (level >= lp->his_range[i++]));
1702
1703 /* Increment interval counter. */
1704 (lp->his_sum[i])++;
1705}
1706#endif /* HISTOGRAM */
1707
1708/*------------------------------------------------------------------*/
1709/*
1710 * Wireless Handler : get protocol name
1711 */
1712static int wavelan_get_name(struct net_device *dev,
1713 struct iw_request_info *info,
1714 union iwreq_data *wrqu,
1715 char *extra)
1716{
1717 strcpy(wrqu->name, "WaveLAN");
1718 return 0;
1719}
1720
1721/*------------------------------------------------------------------*/
1722/*
1723 * Wireless Handler : set NWID
1724 */
1725static int wavelan_set_nwid(struct net_device *dev,
1726 struct iw_request_info *info,
1727 union iwreq_data *wrqu,
1728 char *extra)
1729{
1730 unsigned long ioaddr = dev->base_addr;
1731 net_local *lp = netdev_priv(dev); /* lp is not unused */
1732 psa_t psa;
1733 mm_t m;
1734 unsigned long flags;
1735 int ret = 0;
1736
1737 /* Disable interrupts and save flags. */
1738 spin_lock_irqsave(&lp->spinlock, flags);
1739
1740 /* Set NWID in WaveLAN. */
1741 if (!wrqu->nwid.disabled) {
1742 /* Set NWID in psa */
1743 psa.psa_nwid[0] = (wrqu->nwid.value & 0xFF00) >> 8;
1744 psa.psa_nwid[1] = wrqu->nwid.value & 0xFF;
1745 psa.psa_nwid_select = 0x01;
1746 psa_write(ioaddr, lp->hacr,
1747 (char *) psa.psa_nwid - (char *) &psa,
1748 (unsigned char *) psa.psa_nwid, 3);
1749
1750 /* Set NWID in mmc. */
1751 m.w.mmw_netw_id_l = psa.psa_nwid[1];
1752 m.w.mmw_netw_id_h = psa.psa_nwid[0];
1753 mmc_write(ioaddr,
1754 (char *) &m.w.mmw_netw_id_l -
1755 (char *) &m,
1756 (unsigned char *) &m.w.mmw_netw_id_l, 2);
1757 mmc_out(ioaddr, mmwoff(0, mmw_loopt_sel), 0x00);
1758 } else {
1759 /* Disable NWID in the psa. */
1760 psa.psa_nwid_select = 0x00;
1761 psa_write(ioaddr, lp->hacr,
1762 (char *) &psa.psa_nwid_select -
1763 (char *) &psa,
1764 (unsigned char *) &psa.psa_nwid_select,
1765 1);
1766
1767 /* Disable NWID in the mmc (no filtering). */
1768 mmc_out(ioaddr, mmwoff(0, mmw_loopt_sel),
1769 MMW_LOOPT_SEL_DIS_NWID);
1770 }
1771 /* update the Wavelan checksum */
1772 update_psa_checksum(dev, ioaddr, lp->hacr);
1773
1774 /* Enable interrupts and restore flags. */
1775 spin_unlock_irqrestore(&lp->spinlock, flags);
1776
1777 return ret;
1778}
1779
1780/*------------------------------------------------------------------*/
1781/*
1782 * Wireless Handler : get NWID
1783 */
1784static int wavelan_get_nwid(struct net_device *dev,
1785 struct iw_request_info *info,
1786 union iwreq_data *wrqu,
1787 char *extra)
1788{
1789 unsigned long ioaddr = dev->base_addr;
1790 net_local *lp = netdev_priv(dev); /* lp is not unused */
1791 psa_t psa;
1792 unsigned long flags;
1793 int ret = 0;
1794
1795 /* Disable interrupts and save flags. */
1796 spin_lock_irqsave(&lp->spinlock, flags);
1797
1798 /* Read the NWID. */
1799 psa_read(ioaddr, lp->hacr,
1800 (char *) psa.psa_nwid - (char *) &psa,
1801 (unsigned char *) psa.psa_nwid, 3);
1802 wrqu->nwid.value = (psa.psa_nwid[0] << 8) + psa.psa_nwid[1];
1803 wrqu->nwid.disabled = !(psa.psa_nwid_select);
1804 wrqu->nwid.fixed = 1; /* Superfluous */
1805
1806 /* Enable interrupts and restore flags. */
1807 spin_unlock_irqrestore(&lp->spinlock, flags);
1808
1809 return ret;
1810}
1811
1812/*------------------------------------------------------------------*/
1813/*
1814 * Wireless Handler : set frequency
1815 */
1816static int wavelan_set_freq(struct net_device *dev,
1817 struct iw_request_info *info,
1818 union iwreq_data *wrqu,
1819 char *extra)
1820{
1821 unsigned long ioaddr = dev->base_addr;
1822 net_local *lp = netdev_priv(dev); /* lp is not unused */
1823 unsigned long flags;
1824 int ret;
1825
1826 /* Disable interrupts and save flags. */
1827 spin_lock_irqsave(&lp->spinlock, flags);
1828
1829 /* Attempt to recognise 2.00 cards (2.4 GHz frequency selectable). */
1830 if (!(mmc_in(ioaddr, mmroff(0, mmr_fee_status)) &
1831 (MMR_FEE_STATUS_DWLD | MMR_FEE_STATUS_BUSY)))
1832 ret = wv_set_frequency(ioaddr, &(wrqu->freq));
1833 else
1834 ret = -EOPNOTSUPP;
1835
1836 /* Enable interrupts and restore flags. */
1837 spin_unlock_irqrestore(&lp->spinlock, flags);
1838
1839 return ret;
1840}
1841
1842/*------------------------------------------------------------------*/
1843/*
1844 * Wireless Handler : get frequency
1845 */
1846static int wavelan_get_freq(struct net_device *dev,
1847 struct iw_request_info *info,
1848 union iwreq_data *wrqu,
1849 char *extra)
1850{
1851 unsigned long ioaddr = dev->base_addr;
1852 net_local *lp = netdev_priv(dev); /* lp is not unused */
1853 psa_t psa;
1854 unsigned long flags;
1855 int ret = 0;
1856
1857 /* Disable interrupts and save flags. */
1858 spin_lock_irqsave(&lp->spinlock, flags);
1859
1860 /* Attempt to recognise 2.00 cards (2.4 GHz frequency selectable).
1861 * Does it work for everybody, especially old cards? */
1862 if (!(mmc_in(ioaddr, mmroff(0, mmr_fee_status)) &
1863 (MMR_FEE_STATUS_DWLD | MMR_FEE_STATUS_BUSY))) {
1864 unsigned short freq;
1865
1866 /* Ask the EEPROM to read the frequency from the first area. */
1867 fee_read(ioaddr, 0x00, &freq, 1);
1868 wrqu->freq.m = ((freq >> 5) * 5 + 24000L) * 10000;
1869 wrqu->freq.e = 1;
1870 } else {
1871 psa_read(ioaddr, lp->hacr,
1872 (char *) &psa.psa_subband - (char *) &psa,
1873 (unsigned char *) &psa.psa_subband, 1);
1874
1875 if (psa.psa_subband <= 4) {
1876 wrqu->freq.m = fixed_bands[psa.psa_subband];
1877 wrqu->freq.e = (psa.psa_subband != 0);
1878 } else
1879 ret = -EOPNOTSUPP;
1880 }
1881
1882 /* Enable interrupts and restore flags. */
1883 spin_unlock_irqrestore(&lp->spinlock, flags);
1884
1885 return ret;
1886}
1887
1888/*------------------------------------------------------------------*/
1889/*
1890 * Wireless Handler : set level threshold
1891 */
1892static int wavelan_set_sens(struct net_device *dev,
1893 struct iw_request_info *info,
1894 union iwreq_data *wrqu,
1895 char *extra)
1896{
1897 unsigned long ioaddr = dev->base_addr;
1898 net_local *lp = netdev_priv(dev); /* lp is not unused */
1899 psa_t psa;
1900 unsigned long flags;
1901 int ret = 0;
1902
1903 /* Disable interrupts and save flags. */
1904 spin_lock_irqsave(&lp->spinlock, flags);
1905
1906 /* Set the level threshold. */
1907 /* We should complain loudly if wrqu->sens.fixed = 0, because we
1908 * can't set auto mode... */
1909 psa.psa_thr_pre_set = wrqu->sens.value & 0x3F;
1910 psa_write(ioaddr, lp->hacr,
1911 (char *) &psa.psa_thr_pre_set - (char *) &psa,
1912 (unsigned char *) &psa.psa_thr_pre_set, 1);
1913 /* update the Wavelan checksum */
1914 update_psa_checksum(dev, ioaddr, lp->hacr);
1915 mmc_out(ioaddr, mmwoff(0, mmw_thr_pre_set),
1916 psa.psa_thr_pre_set);
1917
1918 /* Enable interrupts and restore flags. */
1919 spin_unlock_irqrestore(&lp->spinlock, flags);
1920
1921 return ret;
1922}
1923
1924/*------------------------------------------------------------------*/
1925/*
1926 * Wireless Handler : get level threshold
1927 */
1928static int wavelan_get_sens(struct net_device *dev,
1929 struct iw_request_info *info,
1930 union iwreq_data *wrqu,
1931 char *extra)
1932{
1933 unsigned long ioaddr = dev->base_addr;
1934 net_local *lp = netdev_priv(dev); /* lp is not unused */
1935 psa_t psa;
1936 unsigned long flags;
1937 int ret = 0;
1938
1939 /* Disable interrupts and save flags. */
1940 spin_lock_irqsave(&lp->spinlock, flags);
1941
1942 /* Read the level threshold. */
1943 psa_read(ioaddr, lp->hacr,
1944 (char *) &psa.psa_thr_pre_set - (char *) &psa,
1945 (unsigned char *) &psa.psa_thr_pre_set, 1);
1946 wrqu->sens.value = psa.psa_thr_pre_set & 0x3F;
1947 wrqu->sens.fixed = 1;
1948
1949 /* Enable interrupts and restore flags. */
1950 spin_unlock_irqrestore(&lp->spinlock, flags);
1951
1952 return ret;
1953}
1954
1955/*------------------------------------------------------------------*/
1956/*
1957 * Wireless Handler : set encryption key
1958 */
1959static int wavelan_set_encode(struct net_device *dev,
1960 struct iw_request_info *info,
1961 union iwreq_data *wrqu,
1962 char *extra)
1963{
1964 unsigned long ioaddr = dev->base_addr;
1965 net_local *lp = netdev_priv(dev); /* lp is not unused */
1966 unsigned long flags;
1967 psa_t psa;
1968 int ret = 0;
1969
1970 /* Disable interrupts and save flags. */
1971 spin_lock_irqsave(&lp->spinlock, flags);
1972
1973 /* Check if capable of encryption */
1974 if (!mmc_encr(ioaddr)) {
1975 ret = -EOPNOTSUPP;
1976 }
1977
1978 /* Check the size of the key */
1979 if((wrqu->encoding.length != 8) && (wrqu->encoding.length != 0)) {
1980 ret = -EINVAL;
1981 }
1982
1983 if(!ret) {
1984 /* Basic checking... */
1985 if (wrqu->encoding.length == 8) {
1986 /* Copy the key in the driver */
1987 memcpy(psa.psa_encryption_key, extra,
1988 wrqu->encoding.length);
1989 psa.psa_encryption_select = 1;
1990
1991 psa_write(ioaddr, lp->hacr,
1992 (char *) &psa.psa_encryption_select -
1993 (char *) &psa,
1994 (unsigned char *) &psa.
1995 psa_encryption_select, 8 + 1);
1996
1997 mmc_out(ioaddr, mmwoff(0, mmw_encr_enable),
1998 MMW_ENCR_ENABLE_EN | MMW_ENCR_ENABLE_MODE);
1999 mmc_write(ioaddr, mmwoff(0, mmw_encr_key),
2000 (unsigned char *) &psa.
2001 psa_encryption_key, 8);
2002 }
2003
2004 /* disable encryption */
2005 if (wrqu->encoding.flags & IW_ENCODE_DISABLED) {
2006 psa.psa_encryption_select = 0;
2007 psa_write(ioaddr, lp->hacr,
2008 (char *) &psa.psa_encryption_select -
2009 (char *) &psa,
2010 (unsigned char *) &psa.
2011 psa_encryption_select, 1);
2012
2013 mmc_out(ioaddr, mmwoff(0, mmw_encr_enable), 0);
2014 }
2015 /* update the Wavelan checksum */
2016 update_psa_checksum(dev, ioaddr, lp->hacr);
2017 }
2018
2019 /* Enable interrupts and restore flags. */
2020 spin_unlock_irqrestore(&lp->spinlock, flags);
2021
2022 return ret;
2023}
2024
2025/*------------------------------------------------------------------*/
2026/*
2027 * Wireless Handler : get encryption key
2028 */
2029static int wavelan_get_encode(struct net_device *dev,
2030 struct iw_request_info *info,
2031 union iwreq_data *wrqu,
2032 char *extra)
2033{
2034 unsigned long ioaddr = dev->base_addr;
2035 net_local *lp = netdev_priv(dev); /* lp is not unused */
2036 psa_t psa;
2037 unsigned long flags;
2038 int ret = 0;
2039
2040 /* Disable interrupts and save flags. */
2041 spin_lock_irqsave(&lp->spinlock, flags);
2042
2043 /* Check if encryption is available */
2044 if (!mmc_encr(ioaddr)) {
2045 ret = -EOPNOTSUPP;
2046 } else {
2047 /* Read the encryption key */
2048 psa_read(ioaddr, lp->hacr,
2049 (char *) &psa.psa_encryption_select -
2050 (char *) &psa,
2051 (unsigned char *) &psa.
2052 psa_encryption_select, 1 + 8);
2053
2054 /* encryption is enabled ? */
2055 if (psa.psa_encryption_select)
2056 wrqu->encoding.flags = IW_ENCODE_ENABLED;
2057 else
2058 wrqu->encoding.flags = IW_ENCODE_DISABLED;
2059 wrqu->encoding.flags |= mmc_encr(ioaddr);
2060
2061 /* Copy the key to the user buffer */
2062 wrqu->encoding.length = 8;
2063 memcpy(extra, psa.psa_encryption_key, wrqu->encoding.length);
2064 }
2065
2066 /* Enable interrupts and restore flags. */
2067 spin_unlock_irqrestore(&lp->spinlock, flags);
2068
2069 return ret;
2070}
2071
2072/*------------------------------------------------------------------*/
2073/*
2074 * Wireless Handler : get range info
2075 */
2076static int wavelan_get_range(struct net_device *dev,
2077 struct iw_request_info *info,
2078 union iwreq_data *wrqu,
2079 char *extra)
2080{
2081 unsigned long ioaddr = dev->base_addr;
2082 net_local *lp = netdev_priv(dev); /* lp is not unused */
2083 struct iw_range *range = (struct iw_range *) extra;
2084 unsigned long flags;
2085 int ret = 0;
2086
2087 /* Set the length (very important for backward compatibility) */
2088 wrqu->data.length = sizeof(struct iw_range);
2089
2090 /* Set all the info we don't care or don't know about to zero */
2091 memset(range, 0, sizeof(struct iw_range));
2092
2093 /* Set the Wireless Extension versions */
2094 range->we_version_compiled = WIRELESS_EXT;
2095 range->we_version_source = 9;
2096
2097 /* Set information in the range struct. */
2098 range->throughput = 1.6 * 1000 * 1000; /* don't argue on this ! */
2099 range->min_nwid = 0x0000;
2100 range->max_nwid = 0xFFFF;
2101
2102 range->sensitivity = 0x3F;
2103 range->max_qual.qual = MMR_SGNL_QUAL;
2104 range->max_qual.level = MMR_SIGNAL_LVL;
2105 range->max_qual.noise = MMR_SILENCE_LVL;
2106 range->avg_qual.qual = MMR_SGNL_QUAL; /* Always max */
2107 /* Need to get better values for those two */
2108 range->avg_qual.level = 30;
2109 range->avg_qual.noise = 8;
2110
2111 range->num_bitrates = 1;
2112 range->bitrate[0] = 2000000; /* 2 Mb/s */
2113
2114 /* Event capability (kernel + driver) */
2115 range->event_capa[0] = (IW_EVENT_CAPA_MASK(0x8B02) |
2116 IW_EVENT_CAPA_MASK(0x8B04));
2117 range->event_capa[1] = IW_EVENT_CAPA_K_1;
2118
2119 /* Disable interrupts and save flags. */
2120 spin_lock_irqsave(&lp->spinlock, flags);
2121
2122 /* Attempt to recognise 2.00 cards (2.4 GHz frequency selectable). */
2123 if (!(mmc_in(ioaddr, mmroff(0, mmr_fee_status)) &
2124 (MMR_FEE_STATUS_DWLD | MMR_FEE_STATUS_BUSY))) {
2125 range->num_channels = 10;
2126 range->num_frequency = wv_frequency_list(ioaddr, range->freq,
2127 IW_MAX_FREQUENCIES);
2128 } else
2129 range->num_channels = range->num_frequency = 0;
2130
2131 /* Encryption supported ? */
2132 if (mmc_encr(ioaddr)) {
2133 range->encoding_size[0] = 8; /* DES = 64 bits key */
2134 range->num_encoding_sizes = 1;
2135 range->max_encoding_tokens = 1; /* Only one key possible */
2136 } else {
2137 range->num_encoding_sizes = 0;
2138 range->max_encoding_tokens = 0;
2139 }
2140
2141 /* Enable interrupts and restore flags. */
2142 spin_unlock_irqrestore(&lp->spinlock, flags);
2143
2144 return ret;
2145}
2146
2147/*------------------------------------------------------------------*/
2148/*
2149 * Wireless Private Handler : set quality threshold
2150 */
2151static int wavelan_set_qthr(struct net_device *dev,
2152 struct iw_request_info *info,
2153 union iwreq_data *wrqu,
2154 char *extra)
2155{
2156 unsigned long ioaddr = dev->base_addr;
2157 net_local *lp = netdev_priv(dev); /* lp is not unused */
2158 psa_t psa;
2159 unsigned long flags;
2160
2161 /* Disable interrupts and save flags. */
2162 spin_lock_irqsave(&lp->spinlock, flags);
2163
2164 psa.psa_quality_thr = *(extra) & 0x0F;
2165 psa_write(ioaddr, lp->hacr,
2166 (char *) &psa.psa_quality_thr - (char *) &psa,
2167 (unsigned char *) &psa.psa_quality_thr, 1);
2168 /* update the Wavelan checksum */
2169 update_psa_checksum(dev, ioaddr, lp->hacr);
2170 mmc_out(ioaddr, mmwoff(0, mmw_quality_thr),
2171 psa.psa_quality_thr);
2172
2173 /* Enable interrupts and restore flags. */
2174 spin_unlock_irqrestore(&lp->spinlock, flags);
2175
2176 return 0;
2177}
2178
2179/*------------------------------------------------------------------*/
2180/*
2181 * Wireless Private Handler : get quality threshold
2182 */
2183static int wavelan_get_qthr(struct net_device *dev,
2184 struct iw_request_info *info,
2185 union iwreq_data *wrqu,
2186 char *extra)
2187{
2188 unsigned long ioaddr = dev->base_addr;
2189 net_local *lp = netdev_priv(dev); /* lp is not unused */
2190 psa_t psa;
2191 unsigned long flags;
2192
2193 /* Disable interrupts and save flags. */
2194 spin_lock_irqsave(&lp->spinlock, flags);
2195
2196 psa_read(ioaddr, lp->hacr,
2197 (char *) &psa.psa_quality_thr - (char *) &psa,
2198 (unsigned char *) &psa.psa_quality_thr, 1);
2199 *(extra) = psa.psa_quality_thr & 0x0F;
2200
2201 /* Enable interrupts and restore flags. */
2202 spin_unlock_irqrestore(&lp->spinlock, flags);
2203
2204 return 0;
2205}
2206
2207#ifdef HISTOGRAM
2208/*------------------------------------------------------------------*/
2209/*
2210 * Wireless Private Handler : set histogram
2211 */
2212static int wavelan_set_histo(struct net_device *dev,
2213 struct iw_request_info *info,
2214 union iwreq_data *wrqu,
2215 char *extra)
2216{
2217 net_local *lp = netdev_priv(dev); /* lp is not unused */
2218
2219 /* Check the number of intervals. */
2220 if (wrqu->data.length > 16) {
2221 return(-E2BIG);
2222 }
2223
2224 /* Disable histo while we copy the addresses.
2225 * As we don't disable interrupts, we need to do this */
2226 lp->his_number = 0;
2227
2228 /* Are there ranges to copy? */
2229 if (wrqu->data.length > 0) {
2230 /* Copy interval ranges to the driver */
2231 memcpy(lp->his_range, extra, wrqu->data.length);
2232
2233 {
2234 int i;
2235 printk(KERN_DEBUG "Histo :");
2236 for(i = 0; i < wrqu->data.length; i++)
2237 printk(" %d", lp->his_range[i]);
2238 printk("\n");
2239 }
2240
2241 /* Reset result structure. */
2242 memset(lp->his_sum, 0x00, sizeof(long) * 16);
2243 }
2244
2245 /* Now we can set the number of ranges */
2246 lp->his_number = wrqu->data.length;
2247
2248 return(0);
2249}
2250
2251/*------------------------------------------------------------------*/
2252/*
2253 * Wireless Private Handler : get histogram
2254 */
2255static int wavelan_get_histo(struct net_device *dev,
2256 struct iw_request_info *info,
2257 union iwreq_data *wrqu,
2258 char *extra)
2259{
2260 net_local *lp = netdev_priv(dev); /* lp is not unused */
2261
2262 /* Set the number of intervals. */
2263 wrqu->data.length = lp->his_number;
2264
2265 /* Give back the distribution statistics */
2266 if(lp->his_number > 0)
2267 memcpy(extra, lp->his_sum, sizeof(long) * lp->his_number);
2268
2269 return(0);
2270}
2271#endif /* HISTOGRAM */
2272
2273/*------------------------------------------------------------------*/
2274/*
2275 * Structures to export the Wireless Handlers
2276 */
2277
2278static const iw_handler wavelan_handler[] =
2279{
2280 NULL, /* SIOCSIWNAME */
2281 wavelan_get_name, /* SIOCGIWNAME */
2282 wavelan_set_nwid, /* SIOCSIWNWID */
2283 wavelan_get_nwid, /* SIOCGIWNWID */
2284 wavelan_set_freq, /* SIOCSIWFREQ */
2285 wavelan_get_freq, /* SIOCGIWFREQ */
2286 NULL, /* SIOCSIWMODE */
2287 NULL, /* SIOCGIWMODE */
2288 wavelan_set_sens, /* SIOCSIWSENS */
2289 wavelan_get_sens, /* SIOCGIWSENS */
2290 NULL, /* SIOCSIWRANGE */
2291 wavelan_get_range, /* SIOCGIWRANGE */
2292 NULL, /* SIOCSIWPRIV */
2293 NULL, /* SIOCGIWPRIV */
2294 NULL, /* SIOCSIWSTATS */
2295 NULL, /* SIOCGIWSTATS */
2296 iw_handler_set_spy, /* SIOCSIWSPY */
2297 iw_handler_get_spy, /* SIOCGIWSPY */
2298 iw_handler_set_thrspy, /* SIOCSIWTHRSPY */
2299 iw_handler_get_thrspy, /* SIOCGIWTHRSPY */
2300 NULL, /* SIOCSIWAP */
2301 NULL, /* SIOCGIWAP */
2302 NULL, /* -- hole -- */
2303 NULL, /* SIOCGIWAPLIST */
2304 NULL, /* -- hole -- */
2305 NULL, /* -- hole -- */
2306 NULL, /* SIOCSIWESSID */
2307 NULL, /* SIOCGIWESSID */
2308 NULL, /* SIOCSIWNICKN */
2309 NULL, /* SIOCGIWNICKN */
2310 NULL, /* -- hole -- */
2311 NULL, /* -- hole -- */
2312 NULL, /* SIOCSIWRATE */
2313 NULL, /* SIOCGIWRATE */
2314 NULL, /* SIOCSIWRTS */
2315 NULL, /* SIOCGIWRTS */
2316 NULL, /* SIOCSIWFRAG */
2317 NULL, /* SIOCGIWFRAG */
2318 NULL, /* SIOCSIWTXPOW */
2319 NULL, /* SIOCGIWTXPOW */
2320 NULL, /* SIOCSIWRETRY */
2321 NULL, /* SIOCGIWRETRY */
2322 /* Bummer ! Why those are only at the end ??? */
2323 wavelan_set_encode, /* SIOCSIWENCODE */
2324 wavelan_get_encode, /* SIOCGIWENCODE */
2325};
2326
2327static const iw_handler wavelan_private_handler[] =
2328{
2329 wavelan_set_qthr, /* SIOCIWFIRSTPRIV */
2330 wavelan_get_qthr, /* SIOCIWFIRSTPRIV + 1 */
2331#ifdef HISTOGRAM
2332 wavelan_set_histo, /* SIOCIWFIRSTPRIV + 2 */
2333 wavelan_get_histo, /* SIOCIWFIRSTPRIV + 3 */
2334#endif /* HISTOGRAM */
2335};
2336
2337static const struct iw_priv_args wavelan_private_args[] = {
2338/*{ cmd, set_args, get_args, name } */
2339 { SIOCSIPQTHR, IW_PRIV_TYPE_BYTE | IW_PRIV_SIZE_FIXED | 1, 0, "setqualthr" },
2340 { SIOCGIPQTHR, 0, IW_PRIV_TYPE_BYTE | IW_PRIV_SIZE_FIXED | 1, "getqualthr" },
2341 { SIOCSIPHISTO, IW_PRIV_TYPE_BYTE | 16, 0, "sethisto" },
2342 { SIOCGIPHISTO, 0, IW_PRIV_TYPE_INT | 16, "gethisto" },
2343};
2344
2345static const struct iw_handler_def wavelan_handler_def =
2346{
2347 .num_standard = ARRAY_SIZE(wavelan_handler),
2348 .num_private = ARRAY_SIZE(wavelan_private_handler),
2349 .num_private_args = ARRAY_SIZE(wavelan_private_args),
2350 .standard = wavelan_handler,
2351 .private = wavelan_private_handler,
2352 .private_args = wavelan_private_args,
2353 .get_wireless_stats = wavelan_get_wireless_stats,
2354};
2355
2356/*------------------------------------------------------------------*/
2357/*
2358 * Get wireless statistics.
2359 * Called by /proc/net/wireless
2360 */
2361static iw_stats *wavelan_get_wireless_stats(struct net_device * dev)
2362{
2363 unsigned long ioaddr = dev->base_addr;
2364 net_local *lp = netdev_priv(dev);
2365 mmr_t m;
2366 iw_stats *wstats;
2367 unsigned long flags;
2368
2369#ifdef DEBUG_IOCTL_TRACE
2370 printk(KERN_DEBUG "%s: ->wavelan_get_wireless_stats()\n",
2371 dev->name);
2372#endif
2373
2374 /* Check */
2375 if (lp == (net_local *) NULL)
2376 return (iw_stats *) NULL;
2377
2378 /* Disable interrupts and save flags. */
2379 spin_lock_irqsave(&lp->spinlock, flags);
2380
2381 wstats = &lp->wstats;
2382
2383 /* Get data from the mmc. */
2384 mmc_out(ioaddr, mmwoff(0, mmw_freeze), 1);
2385
2386 mmc_read(ioaddr, mmroff(0, mmr_dce_status), &m.mmr_dce_status, 1);
2387 mmc_read(ioaddr, mmroff(0, mmr_wrong_nwid_l), &m.mmr_wrong_nwid_l,
2388 2);
2389 mmc_read(ioaddr, mmroff(0, mmr_thr_pre_set), &m.mmr_thr_pre_set,
2390 4);
2391
2392 mmc_out(ioaddr, mmwoff(0, mmw_freeze), 0);
2393
2394 /* Copy data to wireless stuff. */
2395 wstats->status = m.mmr_dce_status & MMR_DCE_STATUS;
2396 wstats->qual.qual = m.mmr_sgnl_qual & MMR_SGNL_QUAL;
2397 wstats->qual.level = m.mmr_signal_lvl & MMR_SIGNAL_LVL;
2398 wstats->qual.noise = m.mmr_silence_lvl & MMR_SILENCE_LVL;
2399 wstats->qual.updated = (((m. mmr_signal_lvl & MMR_SIGNAL_LVL_VALID) >> 7)
2400 | ((m.mmr_signal_lvl & MMR_SIGNAL_LVL_VALID) >> 6)
2401 | ((m.mmr_silence_lvl & MMR_SILENCE_LVL_VALID) >> 5));
2402 wstats->discard.nwid += (m.mmr_wrong_nwid_h << 8) | m.mmr_wrong_nwid_l;
2403 wstats->discard.code = 0L;
2404 wstats->discard.misc = 0L;
2405
2406 /* Enable interrupts and restore flags. */
2407 spin_unlock_irqrestore(&lp->spinlock, flags);
2408
2409#ifdef DEBUG_IOCTL_TRACE
2410 printk(KERN_DEBUG "%s: <-wavelan_get_wireless_stats()\n",
2411 dev->name);
2412#endif
2413 return &lp->wstats;
2414}
2415
2416/************************* PACKET RECEPTION *************************/
2417/*
2418 * This part deals with receiving the packets.
2419 * The interrupt handler gets an interrupt when a packet has been
2420 * successfully received and calls this part.
2421 */
2422
2423/*------------------------------------------------------------------*/
2424/*
2425 * This routine does the actual copying of data (including the Ethernet
2426 * header structure) from the WaveLAN card to an sk_buff chain that
2427 * will be passed up to the network interface layer. NOTE: we
2428 * currently don't handle trailer protocols (neither does the rest of
2429 * the network interface), so if that is needed, it will (at least in
2430 * part) be added here. The contents of the receive ring buffer are
2431 * copied to a message chain that is then passed to the kernel.
2432 *
2433 * Note: if any errors occur, the packet is "dropped on the floor".
2434 * (called by wv_packet_rcv())
2435 */
2436static void
2437wv_packet_read(struct net_device * dev, u16 buf_off, int sksize)
2438{
2439 net_local *lp = netdev_priv(dev);
2440 unsigned long ioaddr = dev->base_addr;
2441 struct sk_buff *skb;
2442
2443#ifdef DEBUG_RX_TRACE
2444 printk(KERN_DEBUG "%s: ->wv_packet_read(0x%X, %d)\n",
2445 dev->name, buf_off, sksize);
2446#endif
2447
2448 /* Allocate buffer for the data */
2449 if ((skb = dev_alloc_skb(sksize)) == (struct sk_buff *) NULL) {
2450#ifdef DEBUG_RX_ERROR
2451 printk(KERN_INFO
2452 "%s: wv_packet_read(): could not alloc_skb(%d, GFP_ATOMIC).\n",
2453 dev->name, sksize);
2454#endif
2455 dev->stats.rx_dropped++;
2456 return;
2457 }
2458
2459 /* Copy the packet to the buffer. */
2460 obram_read(ioaddr, buf_off, skb_put(skb, sksize), sksize);
2461 skb->protocol = eth_type_trans(skb, dev);
2462
2463#ifdef DEBUG_RX_INFO
2464 wv_packet_info(skb_mac_header(skb), sksize, dev->name,
2465 "wv_packet_read");
2466#endif /* DEBUG_RX_INFO */
2467
2468 /* Statistics-gathering and associated stuff.
2469 * It seem a bit messy with all the define, but it's really
2470 * simple... */
2471 if (
2472#ifdef IW_WIRELESS_SPY /* defined in iw_handler.h */
2473 (lp->spy_data.spy_number > 0) ||
2474#endif /* IW_WIRELESS_SPY */
2475#ifdef HISTOGRAM
2476 (lp->his_number > 0) ||
2477#endif /* HISTOGRAM */
2478 0) {
2479 u8 stats[3]; /* signal level, noise level, signal quality */
2480
2481 /* Read signal level, silence level and signal quality bytes */
2482 /* Note: in the PCMCIA hardware, these are part of the frame.
2483 * It seems that for the ISA hardware, it's nowhere to be
2484 * found in the frame, so I'm obliged to do this (it has a
2485 * side effect on /proc/net/wireless).
2486 * Any ideas?
2487 */
2488 mmc_out(ioaddr, mmwoff(0, mmw_freeze), 1);
2489 mmc_read(ioaddr, mmroff(0, mmr_signal_lvl), stats, 3);
2490 mmc_out(ioaddr, mmwoff(0, mmw_freeze), 0);
2491
2492#ifdef DEBUG_RX_INFO
2493 printk(KERN_DEBUG
2494 "%s: wv_packet_read(): Signal level %d/63, Silence level %d/63, signal quality %d/16\n",
2495 dev->name, stats[0] & 0x3F, stats[1] & 0x3F,
2496 stats[2] & 0x0F);
2497#endif
2498
2499 /* Spying stuff */
2500#ifdef IW_WIRELESS_SPY
2501 wl_spy_gather(dev, skb_mac_header(skb) + WAVELAN_ADDR_SIZE,
2502 stats);
2503#endif /* IW_WIRELESS_SPY */
2504#ifdef HISTOGRAM
2505 wl_his_gather(dev, stats);
2506#endif /* HISTOGRAM */
2507 }
2508
2509 /*
2510 * Hand the packet to the network module.
2511 */
2512 netif_rx(skb);
2513
2514 /* Keep statistics up to date */
2515 dev->stats.rx_packets++;
2516 dev->stats.rx_bytes += sksize;
2517
2518#ifdef DEBUG_RX_TRACE
2519 printk(KERN_DEBUG "%s: <-wv_packet_read()\n", dev->name);
2520#endif
2521}
2522
2523/*------------------------------------------------------------------*/
2524/*
2525 * Transfer as many packets as we can
2526 * from the device RAM.
2527 * (called in wavelan_interrupt()).
2528 * Note : the spinlock is already grabbed for us.
2529 */
2530static void wv_receive(struct net_device * dev)
2531{
2532 unsigned long ioaddr = dev->base_addr;
2533 net_local *lp = netdev_priv(dev);
2534 fd_t fd;
2535 rbd_t rbd;
2536 int nreaped = 0;
2537
2538#ifdef DEBUG_RX_TRACE
2539 printk(KERN_DEBUG "%s: ->wv_receive()\n", dev->name);
2540#endif
2541
2542 /* Loop on each received packet. */
2543 for (;;) {
2544 obram_read(ioaddr, lp->rx_head, (unsigned char *) &fd,
2545 sizeof(fd));
2546
2547 /* Note about the status :
2548 * It start up to be 0 (the value we set). Then, when the RU
2549 * grab the buffer to prepare for reception, it sets the
2550 * FD_STATUS_B flag. When the RU has finished receiving the
2551 * frame, it clears FD_STATUS_B, set FD_STATUS_C to indicate
2552 * completion and set the other flags to indicate the eventual
2553 * errors. FD_STATUS_OK indicates that the reception was OK.
2554 */
2555
2556 /* If the current frame is not complete, we have reached the end. */
2557 if ((fd.fd_status & FD_STATUS_C) != FD_STATUS_C)
2558 break; /* This is how we exit the loop. */
2559
2560 nreaped++;
2561
2562 /* Check whether frame was correctly received. */
2563 if ((fd.fd_status & FD_STATUS_OK) == FD_STATUS_OK) {
2564 /* Does the frame contain a pointer to the data? Let's check. */
2565 if (fd.fd_rbd_offset != I82586NULL) {
2566 /* Read the receive buffer descriptor */
2567 obram_read(ioaddr, fd.fd_rbd_offset,
2568 (unsigned char *) &rbd,
2569 sizeof(rbd));
2570
2571#ifdef DEBUG_RX_ERROR
2572 if ((rbd.rbd_status & RBD_STATUS_EOF) !=
2573 RBD_STATUS_EOF) printk(KERN_INFO
2574 "%s: wv_receive(): missing EOF flag.\n",
2575 dev->name);
2576
2577 if ((rbd.rbd_status & RBD_STATUS_F) !=
2578 RBD_STATUS_F) printk(KERN_INFO
2579 "%s: wv_receive(): missing F flag.\n",
2580 dev->name);
2581#endif /* DEBUG_RX_ERROR */
2582
2583 /* Read the packet and transmit to Linux */
2584 wv_packet_read(dev, rbd.rbd_bufl,
2585 rbd.
2586 rbd_status &
2587 RBD_STATUS_ACNT);
2588 }
2589#ifdef DEBUG_RX_ERROR
2590 else /* if frame has no data */
2591 printk(KERN_INFO
2592 "%s: wv_receive(): frame has no data.\n",
2593 dev->name);
2594#endif
2595 } else { /* If reception was no successful */
2596
2597 dev->stats.rx_errors++;
2598
2599#ifdef DEBUG_RX_INFO
2600 printk(KERN_DEBUG
2601 "%s: wv_receive(): frame not received successfully (%X).\n",
2602 dev->name, fd.fd_status);
2603#endif
2604
2605#ifdef DEBUG_RX_ERROR
2606 if ((fd.fd_status & FD_STATUS_S6) != 0)
2607 printk(KERN_INFO
2608 "%s: wv_receive(): no EOF flag.\n",
2609 dev->name);
2610#endif
2611
2612 if ((fd.fd_status & FD_STATUS_S7) != 0) {
2613 dev->stats.rx_length_errors++;
2614#ifdef DEBUG_RX_FAIL
2615 printk(KERN_DEBUG
2616 "%s: wv_receive(): frame too short.\n",
2617 dev->name);
2618#endif
2619 }
2620
2621 if ((fd.fd_status & FD_STATUS_S8) != 0) {
2622 dev->stats.rx_over_errors++;
2623#ifdef DEBUG_RX_FAIL
2624 printk(KERN_DEBUG
2625 "%s: wv_receive(): rx DMA overrun.\n",
2626 dev->name);
2627#endif
2628 }
2629
2630 if ((fd.fd_status & FD_STATUS_S9) != 0) {
2631 dev->stats.rx_fifo_errors++;
2632#ifdef DEBUG_RX_FAIL
2633 printk(KERN_DEBUG
2634 "%s: wv_receive(): ran out of resources.\n",
2635 dev->name);
2636#endif
2637 }
2638
2639 if ((fd.fd_status & FD_STATUS_S10) != 0) {
2640 dev->stats.rx_frame_errors++;
2641#ifdef DEBUG_RX_FAIL
2642 printk(KERN_DEBUG
2643 "%s: wv_receive(): alignment error.\n",
2644 dev->name);
2645#endif
2646 }
2647
2648 if ((fd.fd_status & FD_STATUS_S11) != 0) {
2649 dev->stats.rx_crc_errors++;
2650#ifdef DEBUG_RX_FAIL
2651 printk(KERN_DEBUG
2652 "%s: wv_receive(): CRC error.\n",
2653 dev->name);
2654#endif
2655 }
2656 }
2657
2658 fd.fd_status = 0;
2659 obram_write(ioaddr, fdoff(lp->rx_head, fd_status),
2660 (unsigned char *) &fd.fd_status,
2661 sizeof(fd.fd_status));
2662
2663 fd.fd_command = FD_COMMAND_EL;
2664 obram_write(ioaddr, fdoff(lp->rx_head, fd_command),
2665 (unsigned char *) &fd.fd_command,
2666 sizeof(fd.fd_command));
2667
2668 fd.fd_command = 0;
2669 obram_write(ioaddr, fdoff(lp->rx_last, fd_command),
2670 (unsigned char *) &fd.fd_command,
2671 sizeof(fd.fd_command));
2672
2673 lp->rx_last = lp->rx_head;
2674 lp->rx_head = fd.fd_link_offset;
2675 } /* for(;;) -> loop on all frames */
2676
2677#ifdef DEBUG_RX_INFO
2678 if (nreaped > 1)
2679 printk(KERN_DEBUG "%s: wv_receive(): reaped %d\n",
2680 dev->name, nreaped);
2681#endif
2682#ifdef DEBUG_RX_TRACE
2683 printk(KERN_DEBUG "%s: <-wv_receive()\n", dev->name);
2684#endif
2685}
2686
2687/*********************** PACKET TRANSMISSION ***********************/
2688/*
2689 * This part deals with sending packets through the WaveLAN.
2690 *
2691 */
2692
2693/*------------------------------------------------------------------*/
2694/*
2695 * This routine fills in the appropriate registers and memory
2696 * locations on the WaveLAN card and starts the card off on
2697 * the transmit.
2698 *
2699 * The principle:
2700 * Each block contains a transmit command, a NOP command,
2701 * a transmit block descriptor and a buffer.
2702 * The CU read the transmit block which point to the tbd,
2703 * read the tbd and the content of the buffer.
2704 * When it has finish with it, it goes to the next command
2705 * which in our case is the NOP. The NOP points on itself,
2706 * so the CU stop here.
2707 * When we add the next block, we modify the previous nop
2708 * to make it point on the new tx command.
2709 * Simple, isn't it ?
2710 *
2711 * (called in wavelan_packet_xmit())
2712 */
2713static int wv_packet_write(struct net_device * dev, void *buf, short length)
2714{
2715 net_local *lp = netdev_priv(dev);
2716 unsigned long ioaddr = dev->base_addr;
2717 unsigned short txblock;
2718 unsigned short txpred;
2719 unsigned short tx_addr;
2720 unsigned short nop_addr;
2721 unsigned short tbd_addr;
2722 unsigned short buf_addr;
2723 ac_tx_t tx;
2724 ac_nop_t nop;
2725 tbd_t tbd;
2726 int clen = length;
2727 unsigned long flags;
2728
2729#ifdef DEBUG_TX_TRACE
2730 printk(KERN_DEBUG "%s: ->wv_packet_write(%d)\n", dev->name,
2731 length);
2732#endif
2733
2734 spin_lock_irqsave(&lp->spinlock, flags);
2735
2736 /* Check nothing bad has happened */
2737 if (lp->tx_n_in_use == (NTXBLOCKS - 1)) {
2738#ifdef DEBUG_TX_ERROR
2739 printk(KERN_INFO "%s: wv_packet_write(): Tx queue full.\n",
2740 dev->name);
2741#endif
2742 spin_unlock_irqrestore(&lp->spinlock, flags);
2743 return 1;
2744 }
2745
2746 /* Calculate addresses of next block and previous block. */
2747 txblock = lp->tx_first_free;
2748 txpred = txblock - TXBLOCKZ;
2749 if (txpred < OFFSET_CU)
2750 txpred += NTXBLOCKS * TXBLOCKZ;
2751 lp->tx_first_free += TXBLOCKZ;
2752 if (lp->tx_first_free >= OFFSET_CU + NTXBLOCKS * TXBLOCKZ)
2753 lp->tx_first_free -= NTXBLOCKS * TXBLOCKZ;
2754
2755 lp->tx_n_in_use++;
2756
2757 /* Calculate addresses of the different parts of the block. */
2758 tx_addr = txblock;
2759 nop_addr = tx_addr + sizeof(tx);
2760 tbd_addr = nop_addr + sizeof(nop);
2761 buf_addr = tbd_addr + sizeof(tbd);
2762
2763 /*
2764 * Transmit command
2765 */
2766 tx.tx_h.ac_status = 0;
2767 obram_write(ioaddr, toff(ac_tx_t, tx_addr, tx_h.ac_status),
2768 (unsigned char *) &tx.tx_h.ac_status,
2769 sizeof(tx.tx_h.ac_status));
2770
2771 /*
2772 * NOP command
2773 */
2774 nop.nop_h.ac_status = 0;
2775 obram_write(ioaddr, toff(ac_nop_t, nop_addr, nop_h.ac_status),
2776 (unsigned char *) &nop.nop_h.ac_status,
2777 sizeof(nop.nop_h.ac_status));
2778 nop.nop_h.ac_link = nop_addr;
2779 obram_write(ioaddr, toff(ac_nop_t, nop_addr, nop_h.ac_link),
2780 (unsigned char *) &nop.nop_h.ac_link,
2781 sizeof(nop.nop_h.ac_link));
2782
2783 /*
2784 * Transmit buffer descriptor
2785 */
2786 tbd.tbd_status = TBD_STATUS_EOF | (TBD_STATUS_ACNT & clen);
2787 tbd.tbd_next_bd_offset = I82586NULL;
2788 tbd.tbd_bufl = buf_addr;
2789 tbd.tbd_bufh = 0;
2790 obram_write(ioaddr, tbd_addr, (unsigned char *) &tbd, sizeof(tbd));
2791
2792 /*
2793 * Data
2794 */
2795 obram_write(ioaddr, buf_addr, buf, length);
2796
2797 /*
2798 * Overwrite the predecessor NOP link
2799 * so that it points to this txblock.
2800 */
2801 nop_addr = txpred + sizeof(tx);
2802 nop.nop_h.ac_status = 0;
2803 obram_write(ioaddr, toff(ac_nop_t, nop_addr, nop_h.ac_status),
2804 (unsigned char *) &nop.nop_h.ac_status,
2805 sizeof(nop.nop_h.ac_status));
2806 nop.nop_h.ac_link = txblock;
2807 obram_write(ioaddr, toff(ac_nop_t, nop_addr, nop_h.ac_link),
2808 (unsigned char *) &nop.nop_h.ac_link,
2809 sizeof(nop.nop_h.ac_link));
2810
2811 /* Make sure the watchdog will keep quiet for a while */
2812 dev->trans_start = jiffies;
2813
2814 /* Keep stats up to date. */
2815 dev->stats.tx_bytes += length;
2816
2817 if (lp->tx_first_in_use == I82586NULL)
2818 lp->tx_first_in_use = txblock;
2819
2820 if (lp->tx_n_in_use < NTXBLOCKS - 1)
2821 netif_wake_queue(dev);
2822
2823 spin_unlock_irqrestore(&lp->spinlock, flags);
2824
2825#ifdef DEBUG_TX_INFO
2826 wv_packet_info((u8 *) buf, length, dev->name,
2827 "wv_packet_write");
2828#endif /* DEBUG_TX_INFO */
2829
2830#ifdef DEBUG_TX_TRACE
2831 printk(KERN_DEBUG "%s: <-wv_packet_write()\n", dev->name);
2832#endif
2833
2834 return 0;
2835}
2836
2837/*------------------------------------------------------------------*/
2838/*
2839 * This routine is called when we want to send a packet (NET3 callback)
2840 * In this routine, we check if the harware is ready to accept
2841 * the packet. We also prevent reentrance. Then we call the function
2842 * to send the packet.
2843 */
2844static netdev_tx_t wavelan_packet_xmit(struct sk_buff *skb,
2845 struct net_device * dev)
2846{
2847 net_local *lp = netdev_priv(dev);
2848 unsigned long flags;
2849 char data[ETH_ZLEN];
2850
2851#ifdef DEBUG_TX_TRACE
2852 printk(KERN_DEBUG "%s: ->wavelan_packet_xmit(0x%X)\n", dev->name,
2853 (unsigned) skb);
2854#endif
2855
2856 /*
2857 * Block a timer-based transmit from overlapping.
2858 * In other words, prevent reentering this routine.
2859 */
2860 netif_stop_queue(dev);
2861
2862 /* If somebody has asked to reconfigure the controller,
2863 * we can do it now.
2864 */
2865 if (lp->reconfig_82586) {
2866 spin_lock_irqsave(&lp->spinlock, flags);
2867 wv_82586_config(dev);
2868 spin_unlock_irqrestore(&lp->spinlock, flags);
2869 /* Check that we can continue */
2870 if (lp->tx_n_in_use == (NTXBLOCKS - 1))
2871 return NETDEV_TX_BUSY;
2872 }
2873
2874 /* Do we need some padding? */
2875 /* Note : on wireless the propagation time is in the order of 1us,
2876 * and we don't have the Ethernet specific requirement of beeing
2877 * able to detect collisions, therefore in theory we don't really
2878 * need to pad. Jean II */
2879 if (skb->len < ETH_ZLEN) {
2880 memset(data, 0, ETH_ZLEN);
2881 skb_copy_from_linear_data(skb, data, skb->len);
2882 /* Write packet on the card */
2883 if(wv_packet_write(dev, data, ETH_ZLEN))
2884 return NETDEV_TX_BUSY; /* We failed */
2885 }
2886 else if(wv_packet_write(dev, skb->data, skb->len))
2887 return NETDEV_TX_BUSY; /* We failed */
2888
2889
2890 dev_kfree_skb(skb);
2891
2892#ifdef DEBUG_TX_TRACE
2893 printk(KERN_DEBUG "%s: <-wavelan_packet_xmit()\n", dev->name);
2894#endif
2895 return NETDEV_TX_OK;
2896}
2897
2898/*********************** HARDWARE CONFIGURATION ***********************/
2899/*
2900 * This part does the real job of starting and configuring the hardware.
2901 */
2902
2903/*--------------------------------------------------------------------*/
2904/*
2905 * Routine to initialize the Modem Management Controller.
2906 * (called by wv_hw_reset())
2907 */
2908static int wv_mmc_init(struct net_device * dev)
2909{
2910 unsigned long ioaddr = dev->base_addr;
2911 net_local *lp = netdev_priv(dev);
2912 psa_t psa;
2913 mmw_t m;
2914 int configured;
2915
2916#ifdef DEBUG_CONFIG_TRACE
2917 printk(KERN_DEBUG "%s: ->wv_mmc_init()\n", dev->name);
2918#endif
2919
2920 /* Read the parameter storage area. */
2921 psa_read(ioaddr, lp->hacr, 0, (unsigned char *) &psa, sizeof(psa));
2922
2923#ifdef USE_PSA_CONFIG
2924 configured = psa.psa_conf_status & 1;
2925#else
2926 configured = 0;
2927#endif
2928
2929 /* Is the PSA is not configured */
2930 if (!configured) {
2931 /* User will be able to configure NWID later (with iwconfig). */
2932 psa.psa_nwid[0] = 0;
2933 psa.psa_nwid[1] = 0;
2934
2935 /* no NWID checking since NWID is not set */
2936 psa.psa_nwid_select = 0;
2937
2938 /* Disable encryption */
2939 psa.psa_encryption_select = 0;
2940
2941 /* Set to standard values:
2942 * 0x04 for AT,
2943 * 0x01 for MCA,
2944 * 0x04 for PCMCIA and 2.00 card (AT&T 407-024689/E document)
2945 */
2946 if (psa.psa_comp_number & 1)
2947 psa.psa_thr_pre_set = 0x01;
2948 else
2949 psa.psa_thr_pre_set = 0x04;
2950 psa.psa_quality_thr = 0x03;
2951
2952 /* It is configured */
2953 psa.psa_conf_status |= 1;
2954
2955#ifdef USE_PSA_CONFIG
2956 /* Write the psa. */
2957 psa_write(ioaddr, lp->hacr,
2958 (char *) psa.psa_nwid - (char *) &psa,
2959 (unsigned char *) psa.psa_nwid, 4);
2960 psa_write(ioaddr, lp->hacr,
2961 (char *) &psa.psa_thr_pre_set - (char *) &psa,
2962 (unsigned char *) &psa.psa_thr_pre_set, 1);
2963 psa_write(ioaddr, lp->hacr,
2964 (char *) &psa.psa_quality_thr - (char *) &psa,
2965 (unsigned char *) &psa.psa_quality_thr, 1);
2966 psa_write(ioaddr, lp->hacr,
2967 (char *) &psa.psa_conf_status - (char *) &psa,
2968 (unsigned char *) &psa.psa_conf_status, 1);
2969 /* update the Wavelan checksum */
2970 update_psa_checksum(dev, ioaddr, lp->hacr);
2971#endif
2972 }
2973
2974 /* Zero the mmc structure. */
2975 memset(&m, 0x00, sizeof(m));
2976
2977 /* Copy PSA info to the mmc. */
2978 m.mmw_netw_id_l = psa.psa_nwid[1];
2979 m.mmw_netw_id_h = psa.psa_nwid[0];
2980
2981 if (psa.psa_nwid_select & 1)
2982 m.mmw_loopt_sel = 0x00;
2983 else
2984 m.mmw_loopt_sel = MMW_LOOPT_SEL_DIS_NWID;
2985
2986 memcpy(&m.mmw_encr_key, &psa.psa_encryption_key,
2987 sizeof(m.mmw_encr_key));
2988
2989 if (psa.psa_encryption_select)
2990 m.mmw_encr_enable =
2991 MMW_ENCR_ENABLE_EN | MMW_ENCR_ENABLE_MODE;
2992 else
2993 m.mmw_encr_enable = 0;
2994
2995 m.mmw_thr_pre_set = psa.psa_thr_pre_set & 0x3F;
2996 m.mmw_quality_thr = psa.psa_quality_thr & 0x0F;
2997
2998 /*
2999 * Set default modem control parameters.
3000 * See NCR document 407-0024326 Rev. A.
3001 */
3002 m.mmw_jabber_enable = 0x01;
3003 m.mmw_freeze = 0;
3004 m.mmw_anten_sel = MMW_ANTEN_SEL_ALG_EN;
3005 m.mmw_ifs = 0x20;
3006 m.mmw_mod_delay = 0x04;
3007 m.mmw_jam_time = 0x38;
3008
3009 m.mmw_des_io_invert = 0;
3010 m.mmw_decay_prm = 0;
3011 m.mmw_decay_updat_prm = 0;
3012
3013 /* Write all info to MMC. */
3014 mmc_write(ioaddr, 0, (u8 *) & m, sizeof(m));
3015
3016 /* The following code starts the modem of the 2.00 frequency
3017 * selectable cards at power on. It's not strictly needed for the
3018 * following boots.
3019 * The original patch was by Joe Finney for the PCMCIA driver, but
3020 * I've cleaned it up a bit and added documentation.
3021 * Thanks to Loeke Brederveld from Lucent for the info.
3022 */
3023
3024 /* Attempt to recognise 2.00 cards (2.4 GHz frequency selectable)
3025 * Does it work for everybody, especially old cards? */
3026 /* Note: WFREQSEL verifies that it is able to read a sensible
3027 * frequency from EEPROM (address 0x00) and that MMR_FEE_STATUS_ID
3028 * is 0xA (Xilinx version) or 0xB (Ariadne version).
3029 * My test is more crude but does work. */
3030 if (!(mmc_in(ioaddr, mmroff(0, mmr_fee_status)) &
3031 (MMR_FEE_STATUS_DWLD | MMR_FEE_STATUS_BUSY))) {
3032 /* We must download the frequency parameters to the
3033 * synthesizers (from the EEPROM - area 1)
3034 * Note: as the EEPROM is automatically decremented, we set the end
3035 * if the area... */
3036 m.mmw_fee_addr = 0x0F;
3037 m.mmw_fee_ctrl = MMW_FEE_CTRL_READ | MMW_FEE_CTRL_DWLD;
3038 mmc_write(ioaddr, (char *) &m.mmw_fee_ctrl - (char *) &m,
3039 (unsigned char *) &m.mmw_fee_ctrl, 2);
3040
3041 /* Wait until the download is finished. */
3042 fee_wait(ioaddr, 100, 100);
3043
3044#ifdef DEBUG_CONFIG_INFO
3045 /* The frequency was in the last word downloaded. */
3046 mmc_read(ioaddr, (char *) &m.mmw_fee_data_l - (char *) &m,
3047 (unsigned char *) &m.mmw_fee_data_l, 2);
3048
3049 /* Print some info for the user. */
3050 printk(KERN_DEBUG
3051 "%s: WaveLAN 2.00 recognised (frequency select). Current frequency = %ld\n",
3052 dev->name,
3053 ((m.
3054 mmw_fee_data_h << 4) | (m.mmw_fee_data_l >> 4)) *
3055 5 / 2 + 24000L);
3056#endif
3057
3058 /* We must now download the power adjust value (gain) to
3059 * the synthesizers (from the EEPROM - area 7 - DAC). */
3060 m.mmw_fee_addr = 0x61;
3061 m.mmw_fee_ctrl = MMW_FEE_CTRL_READ | MMW_FEE_CTRL_DWLD;
3062 mmc_write(ioaddr, (char *) &m.mmw_fee_ctrl - (char *) &m,
3063 (unsigned char *) &m.mmw_fee_ctrl, 2);
3064
3065 /* Wait until the download is finished. */
3066 }
3067 /* if 2.00 card */
3068#ifdef DEBUG_CONFIG_TRACE
3069 printk(KERN_DEBUG "%s: <-wv_mmc_init()\n", dev->name);
3070#endif
3071 return 0;
3072}
3073
3074/*------------------------------------------------------------------*/
3075/*
3076 * Construct the fd and rbd structures.
3077 * Start the receive unit.
3078 * (called by wv_hw_reset())
3079 */
3080static int wv_ru_start(struct net_device * dev)
3081{
3082 net_local *lp = netdev_priv(dev);
3083 unsigned long ioaddr = dev->base_addr;
3084 u16 scb_cs;
3085 fd_t fd;
3086 rbd_t rbd;
3087 u16 rx;
3088 u16 rx_next;
3089 int i;
3090
3091#ifdef DEBUG_CONFIG_TRACE
3092 printk(KERN_DEBUG "%s: ->wv_ru_start()\n", dev->name);
3093#endif
3094
3095 obram_read(ioaddr, scboff(OFFSET_SCB, scb_status),
3096 (unsigned char *) &scb_cs, sizeof(scb_cs));
3097 if ((scb_cs & SCB_ST_RUS) == SCB_ST_RUS_RDY)
3098 return 0;
3099
3100 lp->rx_head = OFFSET_RU;
3101
3102 for (i = 0, rx = lp->rx_head; i < NRXBLOCKS; i++, rx = rx_next) {
3103 rx_next =
3104 (i == NRXBLOCKS - 1) ? lp->rx_head : rx + RXBLOCKZ;
3105
3106 fd.fd_status = 0;
3107 fd.fd_command = (i == NRXBLOCKS - 1) ? FD_COMMAND_EL : 0;
3108 fd.fd_link_offset = rx_next;
3109 fd.fd_rbd_offset = rx + sizeof(fd);
3110 obram_write(ioaddr, rx, (unsigned char *) &fd, sizeof(fd));
3111
3112 rbd.rbd_status = 0;
3113 rbd.rbd_next_rbd_offset = I82586NULL;
3114 rbd.rbd_bufl = rx + sizeof(fd) + sizeof(rbd);
3115 rbd.rbd_bufh = 0;
3116 rbd.rbd_el_size = RBD_EL | (RBD_SIZE & MAXDATAZ);
3117 obram_write(ioaddr, rx + sizeof(fd),
3118 (unsigned char *) &rbd, sizeof(rbd));
3119
3120 lp->rx_last = rx;
3121 }
3122
3123 obram_write(ioaddr, scboff(OFFSET_SCB, scb_rfa_offset),
3124 (unsigned char *) &lp->rx_head, sizeof(lp->rx_head));
3125
3126 scb_cs = SCB_CMD_RUC_GO;
3127 obram_write(ioaddr, scboff(OFFSET_SCB, scb_command),
3128 (unsigned char *) &scb_cs, sizeof(scb_cs));
3129
3130 set_chan_attn(ioaddr, lp->hacr);
3131
3132 for (i = 1000; i > 0; i--) {
3133 obram_read(ioaddr, scboff(OFFSET_SCB, scb_command),
3134 (unsigned char *) &scb_cs, sizeof(scb_cs));
3135 if (scb_cs == 0)
3136 break;
3137
3138 udelay(10);
3139 }
3140
3141 if (i <= 0) {
3142#ifdef DEBUG_CONFIG_ERROR
3143 printk(KERN_INFO
3144 "%s: wavelan_ru_start(): board not accepting command.\n",
3145 dev->name);
3146#endif
3147 return -1;
3148 }
3149#ifdef DEBUG_CONFIG_TRACE
3150 printk(KERN_DEBUG "%s: <-wv_ru_start()\n", dev->name);
3151#endif
3152 return 0;
3153}
3154
3155/*------------------------------------------------------------------*/
3156/*
3157 * Initialise the transmit blocks.
3158 * Start the command unit executing the NOP
3159 * self-loop of the first transmit block.
3160 *
3161 * Here we create the list of send buffers used to transmit packets
3162 * between the PC and the command unit. For each buffer, we create a
3163 * buffer descriptor (pointing on the buffer), a transmit command
3164 * (pointing to the buffer descriptor) and a NOP command.
3165 * The transmit command is linked to the NOP, and the NOP to itself.
3166 * When we will have finished executing the transmit command, we will
3167 * then loop on the NOP. By releasing the NOP link to a new command,
3168 * we may send another buffer.
3169 *
3170 * (called by wv_hw_reset())
3171 */
3172static int wv_cu_start(struct net_device * dev)
3173{
3174 net_local *lp = netdev_priv(dev);
3175 unsigned long ioaddr = dev->base_addr;
3176 int i;
3177 u16 txblock;
3178 u16 first_nop;
3179 u16 scb_cs;
3180
3181#ifdef DEBUG_CONFIG_TRACE
3182 printk(KERN_DEBUG "%s: ->wv_cu_start()\n", dev->name);
3183#endif
3184
3185 lp->tx_first_free = OFFSET_CU;
3186 lp->tx_first_in_use = I82586NULL;
3187
3188 for (i = 0, txblock = OFFSET_CU;
3189 i < NTXBLOCKS; i++, txblock += TXBLOCKZ) {
3190 ac_tx_t tx;
3191 ac_nop_t nop;
3192 tbd_t tbd;
3193 unsigned short tx_addr;
3194 unsigned short nop_addr;
3195 unsigned short tbd_addr;
3196 unsigned short buf_addr;
3197
3198 tx_addr = txblock;
3199 nop_addr = tx_addr + sizeof(tx);
3200 tbd_addr = nop_addr + sizeof(nop);
3201 buf_addr = tbd_addr + sizeof(tbd);
3202
3203 tx.tx_h.ac_status = 0;
3204 tx.tx_h.ac_command = acmd_transmit | AC_CFLD_I;
3205 tx.tx_h.ac_link = nop_addr;
3206 tx.tx_tbd_offset = tbd_addr;
3207 obram_write(ioaddr, tx_addr, (unsigned char *) &tx,
3208 sizeof(tx));
3209
3210 nop.nop_h.ac_status = 0;
3211 nop.nop_h.ac_command = acmd_nop;
3212 nop.nop_h.ac_link = nop_addr;
3213 obram_write(ioaddr, nop_addr, (unsigned char *) &nop,
3214 sizeof(nop));
3215
3216 tbd.tbd_status = TBD_STATUS_EOF;
3217 tbd.tbd_next_bd_offset = I82586NULL;
3218 tbd.tbd_bufl = buf_addr;
3219 tbd.tbd_bufh = 0;
3220 obram_write(ioaddr, tbd_addr, (unsigned char *) &tbd,
3221 sizeof(tbd));
3222 }
3223
3224 first_nop =
3225 OFFSET_CU + (NTXBLOCKS - 1) * TXBLOCKZ + sizeof(ac_tx_t);
3226 obram_write(ioaddr, scboff(OFFSET_SCB, scb_cbl_offset),
3227 (unsigned char *) &first_nop, sizeof(first_nop));
3228
3229 scb_cs = SCB_CMD_CUC_GO;
3230 obram_write(ioaddr, scboff(OFFSET_SCB, scb_command),
3231 (unsigned char *) &scb_cs, sizeof(scb_cs));
3232
3233 set_chan_attn(ioaddr, lp->hacr);
3234
3235 for (i = 1000; i > 0; i--) {
3236 obram_read(ioaddr, scboff(OFFSET_SCB, scb_command),
3237 (unsigned char *) &scb_cs, sizeof(scb_cs));
3238 if (scb_cs == 0)
3239 break;
3240
3241 udelay(10);
3242 }
3243
3244 if (i <= 0) {
3245#ifdef DEBUG_CONFIG_ERROR
3246 printk(KERN_INFO
3247 "%s: wavelan_cu_start(): board not accepting command.\n",
3248 dev->name);
3249#endif
3250 return -1;
3251 }
3252
3253 lp->tx_n_in_use = 0;
3254 netif_start_queue(dev);
3255#ifdef DEBUG_CONFIG_TRACE
3256 printk(KERN_DEBUG "%s: <-wv_cu_start()\n", dev->name);
3257#endif
3258 return 0;
3259}
3260
3261/*------------------------------------------------------------------*/
3262/*
3263 * This routine does a standard configuration of the WaveLAN
3264 * controller (i82586).
3265 *
3266 * It initialises the scp, iscp and scb structure
3267 * The first two are just pointers to the next.
3268 * The last one is used for basic configuration and for basic
3269 * communication (interrupt status).
3270 *
3271 * (called by wv_hw_reset())
3272 */
3273static int wv_82586_start(struct net_device * dev)
3274{
3275 net_local *lp = netdev_priv(dev);
3276 unsigned long ioaddr = dev->base_addr;
3277 scp_t scp; /* system configuration pointer */
3278 iscp_t iscp; /* intermediate scp */
3279 scb_t scb; /* system control block */
3280 ach_t cb; /* Action command header */
3281 u8 zeroes[512];
3282 int i;
3283
3284#ifdef DEBUG_CONFIG_TRACE
3285 printk(KERN_DEBUG "%s: ->wv_82586_start()\n", dev->name);
3286#endif
3287
3288 /*
3289 * Clear the onboard RAM.
3290 */
3291 memset(&zeroes[0], 0x00, sizeof(zeroes));
3292 for (i = 0; i < I82586_MEMZ; i += sizeof(zeroes))
3293 obram_write(ioaddr, i, &zeroes[0], sizeof(zeroes));
3294
3295 /*
3296 * Construct the command unit structures:
3297 * scp, iscp, scb, cb.
3298 */
3299 memset(&scp, 0x00, sizeof(scp));
3300 scp.scp_sysbus = SCP_SY_16BBUS;
3301 scp.scp_iscpl = OFFSET_ISCP;
3302 obram_write(ioaddr, OFFSET_SCP, (unsigned char *) &scp,
3303 sizeof(scp));
3304
3305 memset(&iscp, 0x00, sizeof(iscp));
3306 iscp.iscp_busy = 1;
3307 iscp.iscp_offset = OFFSET_SCB;
3308 obram_write(ioaddr, OFFSET_ISCP, (unsigned char *) &iscp,
3309 sizeof(iscp));
3310
3311 /* Our first command is to reset the i82586. */
3312 memset(&scb, 0x00, sizeof(scb));
3313 scb.scb_command = SCB_CMD_RESET;
3314 scb.scb_cbl_offset = OFFSET_CU;
3315 scb.scb_rfa_offset = OFFSET_RU;
3316 obram_write(ioaddr, OFFSET_SCB, (unsigned char *) &scb,
3317 sizeof(scb));
3318
3319 set_chan_attn(ioaddr, lp->hacr);
3320
3321 /* Wait for command to finish. */
3322 for (i = 1000; i > 0; i--) {
3323 obram_read(ioaddr, OFFSET_ISCP, (unsigned char *) &iscp,
3324 sizeof(iscp));
3325
3326 if (iscp.iscp_busy == (unsigned short) 0)
3327 break;
3328
3329 udelay(10);
3330 }
3331
3332 if (i <= 0) {
3333#ifdef DEBUG_CONFIG_ERROR
3334 printk(KERN_INFO
3335 "%s: wv_82586_start(): iscp_busy timeout.\n",
3336 dev->name);
3337#endif
3338 return -1;
3339 }
3340
3341 /* Check command completion. */
3342 for (i = 15; i > 0; i--) {
3343 obram_read(ioaddr, OFFSET_SCB, (unsigned char *) &scb,
3344 sizeof(scb));
3345
3346 if (scb.scb_status == (SCB_ST_CX | SCB_ST_CNA))
3347 break;
3348
3349 udelay(10);
3350 }
3351
3352 if (i <= 0) {
3353#ifdef DEBUG_CONFIG_ERROR
3354 printk(KERN_INFO
3355 "%s: wv_82586_start(): status: expected 0x%02x, got 0x%02x.\n",
3356 dev->name, SCB_ST_CX | SCB_ST_CNA, scb.scb_status);
3357#endif
3358 return -1;
3359 }
3360
3361 wv_ack(dev);
3362
3363 /* Set the action command header. */
3364 memset(&cb, 0x00, sizeof(cb));
3365 cb.ac_command = AC_CFLD_EL | (AC_CFLD_CMD & acmd_diagnose);
3366 cb.ac_link = OFFSET_CU;
3367 obram_write(ioaddr, OFFSET_CU, (unsigned char *) &cb, sizeof(cb));
3368
3369 if (wv_synchronous_cmd(dev, "diag()") == -1)
3370 return -1;
3371
3372 obram_read(ioaddr, OFFSET_CU, (unsigned char *) &cb, sizeof(cb));
3373 if (cb.ac_status & AC_SFLD_FAIL) {
3374#ifdef DEBUG_CONFIG_ERROR
3375 printk(KERN_INFO
3376 "%s: wv_82586_start(): i82586 Self Test failed.\n",
3377 dev->name);
3378#endif
3379 return -1;
3380 }
3381#ifdef DEBUG_I82586_SHOW
3382 wv_scb_show(ioaddr);
3383#endif
3384
3385#ifdef DEBUG_CONFIG_TRACE
3386 printk(KERN_DEBUG "%s: <-wv_82586_start()\n", dev->name);
3387#endif
3388 return 0;
3389}
3390
3391/*------------------------------------------------------------------*/
3392/*
3393 * This routine does a standard configuration of the WaveLAN
3394 * controller (i82586).
3395 *
3396 * This routine is a violent hack. We use the first free transmit block
3397 * to make our configuration. In the buffer area, we create the three
3398 * configuration commands (linked). We make the previous NOP point to
3399 * the beginning of the buffer instead of the tx command. After, we go
3400 * as usual to the NOP command.
3401 * Note that only the last command (mc_set) will generate an interrupt.
3402 *
3403 * (called by wv_hw_reset(), wv_82586_reconfig(), wavelan_packet_xmit())
3404 */
3405static void wv_82586_config(struct net_device * dev)
3406{
3407 net_local *lp = netdev_priv(dev);
3408 unsigned long ioaddr = dev->base_addr;
3409 unsigned short txblock;
3410 unsigned short txpred;
3411 unsigned short tx_addr;
3412 unsigned short nop_addr;
3413 unsigned short tbd_addr;
3414 unsigned short cfg_addr;
3415 unsigned short ias_addr;
3416 unsigned short mcs_addr;
3417 ac_tx_t tx;
3418 ac_nop_t nop;
3419 ac_cfg_t cfg; /* Configure action */
3420 ac_ias_t ias; /* IA-setup action */
3421 ac_mcs_t mcs; /* Multicast setup */
3422 struct dev_mc_list *dmi;
3423
3424#ifdef DEBUG_CONFIG_TRACE
3425 printk(KERN_DEBUG "%s: ->wv_82586_config()\n", dev->name);
3426#endif
3427
3428 /* Check nothing bad has happened */
3429 if (lp->tx_n_in_use == (NTXBLOCKS - 1)) {
3430#ifdef DEBUG_CONFIG_ERROR
3431 printk(KERN_INFO "%s: wv_82586_config(): Tx queue full.\n",
3432 dev->name);
3433#endif
3434 return;
3435 }
3436
3437 /* Calculate addresses of next block and previous block. */
3438 txblock = lp->tx_first_free;
3439 txpred = txblock - TXBLOCKZ;
3440 if (txpred < OFFSET_CU)
3441 txpred += NTXBLOCKS * TXBLOCKZ;
3442 lp->tx_first_free += TXBLOCKZ;
3443 if (lp->tx_first_free >= OFFSET_CU + NTXBLOCKS * TXBLOCKZ)
3444 lp->tx_first_free -= NTXBLOCKS * TXBLOCKZ;
3445
3446 lp->tx_n_in_use++;
3447
3448 /* Calculate addresses of the different parts of the block. */
3449 tx_addr = txblock;
3450 nop_addr = tx_addr + sizeof(tx);
3451 tbd_addr = nop_addr + sizeof(nop);
3452 cfg_addr = tbd_addr + sizeof(tbd_t); /* beginning of the buffer */
3453 ias_addr = cfg_addr + sizeof(cfg);
3454 mcs_addr = ias_addr + sizeof(ias);
3455
3456 /*
3457 * Transmit command
3458 */
3459 tx.tx_h.ac_status = 0xFFFF; /* Fake completion value */
3460 obram_write(ioaddr, toff(ac_tx_t, tx_addr, tx_h.ac_status),
3461 (unsigned char *) &tx.tx_h.ac_status,
3462 sizeof(tx.tx_h.ac_status));
3463
3464 /*
3465 * NOP command
3466 */
3467 nop.nop_h.ac_status = 0;
3468 obram_write(ioaddr, toff(ac_nop_t, nop_addr, nop_h.ac_status),
3469 (unsigned char *) &nop.nop_h.ac_status,
3470 sizeof(nop.nop_h.ac_status));
3471 nop.nop_h.ac_link = nop_addr;
3472 obram_write(ioaddr, toff(ac_nop_t, nop_addr, nop_h.ac_link),
3473 (unsigned char *) &nop.nop_h.ac_link,
3474 sizeof(nop.nop_h.ac_link));
3475
3476 /* Create a configure action. */
3477 memset(&cfg, 0x00, sizeof(cfg));
3478
3479 /*
3480 * For Linux we invert AC_CFG_ALOC() so as to conform
3481 * to the way that net packets reach us from above.
3482 * (See also ac_tx_t.)
3483 *
3484 * Updated from Wavelan Manual WCIN085B
3485 */
3486 cfg.cfg_byte_cnt =
3487 AC_CFG_BYTE_CNT(sizeof(ac_cfg_t) - sizeof(ach_t));
3488 cfg.cfg_fifolim = AC_CFG_FIFOLIM(4);
3489 cfg.cfg_byte8 = AC_CFG_SAV_BF(1) | AC_CFG_SRDY(0);
3490 cfg.cfg_byte9 = AC_CFG_ELPBCK(0) |
3491 AC_CFG_ILPBCK(0) |
3492 AC_CFG_PRELEN(AC_CFG_PLEN_2) |
3493 AC_CFG_ALOC(1) | AC_CFG_ADDRLEN(WAVELAN_ADDR_SIZE);
3494 cfg.cfg_byte10 = AC_CFG_BOFMET(1) |
3495 AC_CFG_ACR(6) | AC_CFG_LINPRIO(0);
3496 cfg.cfg_ifs = 0x20;
3497 cfg.cfg_slotl = 0x0C;
3498 cfg.cfg_byte13 = AC_CFG_RETRYNUM(15) | AC_CFG_SLTTMHI(0);
3499 cfg.cfg_byte14 = AC_CFG_FLGPAD(0) |
3500 AC_CFG_BTSTF(0) |
3501 AC_CFG_CRC16(0) |
3502 AC_CFG_NCRC(0) |
3503 AC_CFG_TNCRS(1) |
3504 AC_CFG_MANCH(0) |
3505 AC_CFG_BCDIS(0) | AC_CFG_PRM(lp->promiscuous);
3506 cfg.cfg_byte15 = AC_CFG_ICDS(0) |
3507 AC_CFG_CDTF(0) | AC_CFG_ICSS(0) | AC_CFG_CSTF(0);
3508/*
3509 cfg.cfg_min_frm_len = AC_CFG_MNFRM(64);
3510*/
3511 cfg.cfg_min_frm_len = AC_CFG_MNFRM(8);
3512
3513 cfg.cfg_h.ac_command = (AC_CFLD_CMD & acmd_configure);
3514 cfg.cfg_h.ac_link = ias_addr;
3515 obram_write(ioaddr, cfg_addr, (unsigned char *) &cfg, sizeof(cfg));
3516
3517 /* Set up the MAC address */
3518 memset(&ias, 0x00, sizeof(ias));
3519 ias.ias_h.ac_command = (AC_CFLD_CMD & acmd_ia_setup);
3520 ias.ias_h.ac_link = mcs_addr;
3521 memcpy(&ias.ias_addr[0], (unsigned char *) &dev->dev_addr[0],
3522 sizeof(ias.ias_addr));
3523 obram_write(ioaddr, ias_addr, (unsigned char *) &ias, sizeof(ias));
3524
3525 /* Initialize adapter's Ethernet multicast addresses */
3526 memset(&mcs, 0x00, sizeof(mcs));
3527 mcs.mcs_h.ac_command = AC_CFLD_I | (AC_CFLD_CMD & acmd_mc_setup);
3528 mcs.mcs_h.ac_link = nop_addr;
3529 mcs.mcs_cnt = WAVELAN_ADDR_SIZE * lp->mc_count;
3530 obram_write(ioaddr, mcs_addr, (unsigned char *) &mcs, sizeof(mcs));
3531
3532 /* Any address to set? */
3533 if (lp->mc_count) {
3534 for (dmi = dev->mc_list; dmi; dmi = dmi->next)
3535 outsw(PIOP1(ioaddr), (u16 *) dmi->dmi_addr,
3536 WAVELAN_ADDR_SIZE >> 1);
3537
3538#ifdef DEBUG_CONFIG_INFO
3539 printk(KERN_DEBUG
3540 "%s: wv_82586_config(): set %d multicast addresses:\n",
3541 dev->name, lp->mc_count);
3542 for (dmi = dev->mc_list; dmi; dmi = dmi->next)
3543 printk(KERN_DEBUG " %pM\n", dmi->dmi_addr);
3544#endif
3545 }
3546
3547 /*
3548 * Overwrite the predecessor NOP link
3549 * so that it points to the configure action.
3550 */
3551 nop_addr = txpred + sizeof(tx);
3552 nop.nop_h.ac_status = 0;
3553 obram_write(ioaddr, toff(ac_nop_t, nop_addr, nop_h.ac_status),
3554 (unsigned char *) &nop.nop_h.ac_status,
3555 sizeof(nop.nop_h.ac_status));
3556 nop.nop_h.ac_link = cfg_addr;
3557 obram_write(ioaddr, toff(ac_nop_t, nop_addr, nop_h.ac_link),
3558 (unsigned char *) &nop.nop_h.ac_link,
3559 sizeof(nop.nop_h.ac_link));
3560
3561 /* Job done, clear the flag */
3562 lp->reconfig_82586 = 0;
3563
3564 if (lp->tx_first_in_use == I82586NULL)
3565 lp->tx_first_in_use = txblock;
3566
3567 if (lp->tx_n_in_use == (NTXBLOCKS - 1))
3568 netif_stop_queue(dev);
3569
3570#ifdef DEBUG_CONFIG_TRACE
3571 printk(KERN_DEBUG "%s: <-wv_82586_config()\n", dev->name);
3572#endif
3573}
3574
3575/*------------------------------------------------------------------*/
3576/*
3577 * This routine, called by wavelan_close(), gracefully stops the
3578 * WaveLAN controller (i82586).
3579 * (called by wavelan_close())
3580 */
3581static void wv_82586_stop(struct net_device * dev)
3582{
3583 net_local *lp = netdev_priv(dev);
3584 unsigned long ioaddr = dev->base_addr;
3585 u16 scb_cmd;
3586
3587#ifdef DEBUG_CONFIG_TRACE
3588 printk(KERN_DEBUG "%s: ->wv_82586_stop()\n", dev->name);
3589#endif
3590
3591 /* Suspend both command unit and receive unit. */
3592 scb_cmd =
3593 (SCB_CMD_CUC & SCB_CMD_CUC_SUS) | (SCB_CMD_RUC &
3594 SCB_CMD_RUC_SUS);
3595 obram_write(ioaddr, scboff(OFFSET_SCB, scb_command),
3596 (unsigned char *) &scb_cmd, sizeof(scb_cmd));
3597 set_chan_attn(ioaddr, lp->hacr);
3598
3599 /* No more interrupts */
3600 wv_ints_off(dev);
3601
3602#ifdef DEBUG_CONFIG_TRACE
3603 printk(KERN_DEBUG "%s: <-wv_82586_stop()\n", dev->name);
3604#endif
3605}
3606
3607/*------------------------------------------------------------------*/
3608/*
3609 * Totally reset the WaveLAN and restart it.
3610 * Performs the following actions:
3611 * 1. A power reset (reset DMA)
3612 * 2. Initialize the radio modem (using wv_mmc_init)
3613 * 3. Reset & Configure LAN controller (using wv_82586_start)
3614 * 4. Start the LAN controller's command unit
3615 * 5. Start the LAN controller's receive unit
3616 * (called by wavelan_interrupt(), wavelan_watchdog() & wavelan_open())
3617 */
3618static int wv_hw_reset(struct net_device * dev)
3619{
3620 net_local *lp = netdev_priv(dev);
3621 unsigned long ioaddr = dev->base_addr;
3622
3623#ifdef DEBUG_CONFIG_TRACE
3624 printk(KERN_DEBUG "%s: ->wv_hw_reset(dev=0x%x)\n", dev->name,
3625 (unsigned int) dev);
3626#endif
3627
3628 /* Increase the number of resets done. */
3629 lp->nresets++;
3630
3631 wv_hacr_reset(ioaddr);
3632 lp->hacr = HACR_DEFAULT;
3633
3634 if ((wv_mmc_init(dev) < 0) || (wv_82586_start(dev) < 0))
3635 return -1;
3636
3637 /* Enable the card to send interrupts. */
3638 wv_ints_on(dev);
3639
3640 /* Start card functions */
3641 if (wv_cu_start(dev) < 0)
3642 return -1;
3643
3644 /* Setup the controller and parameters */
3645 wv_82586_config(dev);
3646
3647 /* Finish configuration with the receive unit */
3648 if (wv_ru_start(dev) < 0)
3649 return -1;
3650
3651#ifdef DEBUG_CONFIG_TRACE
3652 printk(KERN_DEBUG "%s: <-wv_hw_reset()\n", dev->name);
3653#endif
3654 return 0;
3655}
3656
3657/*------------------------------------------------------------------*/
3658/*
3659 * Check if there is a WaveLAN at the specific base address.
3660 * As a side effect, this reads the MAC address.
3661 * (called in wavelan_probe() and init_module())
3662 */
3663static int wv_check_ioaddr(unsigned long ioaddr, u8 * mac)
3664{
3665 int i; /* Loop counter */
3666
3667 /* Check if the base address if available. */
3668 if (!request_region(ioaddr, sizeof(ha_t), "wavelan probe"))
3669 return -EBUSY; /* ioaddr already used */
3670
3671 /* Reset host interface */
3672 wv_hacr_reset(ioaddr);
3673
3674 /* Read the MAC address from the parameter storage area. */
3675 psa_read(ioaddr, HACR_DEFAULT, psaoff(0, psa_univ_mac_addr),
3676 mac, 6);
3677
3678 release_region(ioaddr, sizeof(ha_t));
3679
3680 /*
3681 * Check the first three octets of the address for the manufacturer's code.
3682 * Note: if this can't find your WaveLAN card, you've got a
3683 * non-NCR/AT&T/Lucent ISA card. See wavelan.p.h for detail on
3684 * how to configure your card.
3685 */
3686 for (i = 0; i < ARRAY_SIZE(MAC_ADDRESSES); i++)
3687 if ((mac[0] == MAC_ADDRESSES[i][0]) &&
3688 (mac[1] == MAC_ADDRESSES[i][1]) &&
3689 (mac[2] == MAC_ADDRESSES[i][2]))
3690 return 0;
3691
3692#ifdef DEBUG_CONFIG_INFO
3693 printk(KERN_WARNING
3694 "WaveLAN (0x%3X): your MAC address might be %02X:%02X:%02X.\n",
3695 ioaddr, mac[0], mac[1], mac[2]);
3696#endif
3697 return -ENODEV;
3698}
3699
3700/************************ INTERRUPT HANDLING ************************/
3701
3702/*
3703 * This function is the interrupt handler for the WaveLAN card. This
3704 * routine will be called whenever:
3705 */
3706static irqreturn_t wavelan_interrupt(int irq, void *dev_id)
3707{
3708 struct net_device *dev;
3709 unsigned long ioaddr;
3710 net_local *lp;
3711 u16 hasr;
3712 u16 status;
3713 u16 ack_cmd;
3714
3715 dev = dev_id;
3716
3717#ifdef DEBUG_INTERRUPT_TRACE
3718 printk(KERN_DEBUG "%s: ->wavelan_interrupt()\n", dev->name);
3719#endif
3720
3721 lp = netdev_priv(dev);
3722 ioaddr = dev->base_addr;
3723
3724#ifdef DEBUG_INTERRUPT_INFO
3725 /* Check state of our spinlock */
3726 if(spin_is_locked(&lp->spinlock))
3727 printk(KERN_DEBUG
3728 "%s: wavelan_interrupt(): spinlock is already locked !!!\n",
3729 dev->name);
3730#endif
3731
3732 /* Prevent reentrancy. We need to do that because we may have
3733 * multiple interrupt handler running concurrently.
3734 * It is safe because interrupts are disabled before acquiring
3735 * the spinlock. */
3736 spin_lock(&lp->spinlock);
3737
3738 /* We always had spurious interrupts at startup, but lately I
3739 * saw them comming *between* the request_irq() and the
3740 * spin_lock_irqsave() in wavelan_open(), so the spinlock
3741 * protection is no enough.
3742 * So, we also check lp->hacr that will tell us is we enabled
3743 * irqs or not (see wv_ints_on()).
3744 * We can't use netif_running(dev) because we depend on the
3745 * proper processing of the irq generated during the config. */
3746
3747 /* Which interrupt it is ? */
3748 hasr = hasr_read(ioaddr);
3749
3750#ifdef DEBUG_INTERRUPT_INFO
3751 printk(KERN_INFO
3752 "%s: wavelan_interrupt(): hasr 0x%04x; hacr 0x%04x.\n",
3753 dev->name, hasr, lp->hacr);
3754#endif
3755
3756 /* Check modem interrupt */
3757 if ((hasr & HASR_MMC_INTR) && (lp->hacr & HACR_MMC_INT_ENABLE)) {
3758 u8 dce_status;
3759
3760 /*
3761 * Interrupt from the modem management controller.
3762 * This will clear it -- ignored for now.
3763 */
3764 mmc_read(ioaddr, mmroff(0, mmr_dce_status), &dce_status,
3765 sizeof(dce_status));
3766
3767#ifdef DEBUG_INTERRUPT_ERROR
3768 printk(KERN_INFO
3769 "%s: wavelan_interrupt(): unexpected mmc interrupt: status 0x%04x.\n",
3770 dev->name, dce_status);
3771#endif
3772 }
3773
3774 /* Check if not controller interrupt */
3775 if (((hasr & HASR_82586_INTR) == 0) ||
3776 ((lp->hacr & HACR_82586_INT_ENABLE) == 0)) {
3777#ifdef DEBUG_INTERRUPT_ERROR
3778 printk(KERN_INFO
3779 "%s: wavelan_interrupt(): interrupt not coming from i82586 - hasr 0x%04x.\n",
3780 dev->name, hasr);
3781#endif
3782 spin_unlock (&lp->spinlock);
3783 return IRQ_NONE;
3784 }
3785
3786 /* Read interrupt data. */
3787 obram_read(ioaddr, scboff(OFFSET_SCB, scb_status),
3788 (unsigned char *) &status, sizeof(status));
3789
3790 /*
3791 * Acknowledge the interrupt(s).
3792 */
3793 ack_cmd = status & SCB_ST_INT;
3794 obram_write(ioaddr, scboff(OFFSET_SCB, scb_command),
3795 (unsigned char *) &ack_cmd, sizeof(ack_cmd));
3796 set_chan_attn(ioaddr, lp->hacr);
3797
3798#ifdef DEBUG_INTERRUPT_INFO
3799 printk(KERN_DEBUG "%s: wavelan_interrupt(): status 0x%04x.\n",
3800 dev->name, status);
3801#endif
3802
3803 /* Command completed. */
3804 if ((status & SCB_ST_CX) == SCB_ST_CX) {
3805#ifdef DEBUG_INTERRUPT_INFO
3806 printk(KERN_DEBUG
3807 "%s: wavelan_interrupt(): command completed.\n",
3808 dev->name);
3809#endif
3810 wv_complete(dev, ioaddr, lp);
3811 }
3812
3813 /* Frame received. */
3814 if ((status & SCB_ST_FR) == SCB_ST_FR) {
3815#ifdef DEBUG_INTERRUPT_INFO
3816 printk(KERN_DEBUG
3817 "%s: wavelan_interrupt(): received packet.\n",
3818 dev->name);
3819#endif
3820 wv_receive(dev);
3821 }
3822
3823 /* Check the state of the command unit. */
3824 if (((status & SCB_ST_CNA) == SCB_ST_CNA) ||
3825 (((status & SCB_ST_CUS) != SCB_ST_CUS_ACTV) &&
3826 (netif_running(dev)))) {
3827#ifdef DEBUG_INTERRUPT_ERROR
3828 printk(KERN_INFO
3829 "%s: wavelan_interrupt(): CU inactive -- restarting\n",
3830 dev->name);
3831#endif
3832 wv_hw_reset(dev);
3833 }
3834
3835 /* Check the state of the command unit. */
3836 if (((status & SCB_ST_RNR) == SCB_ST_RNR) ||
3837 (((status & SCB_ST_RUS) != SCB_ST_RUS_RDY) &&
3838 (netif_running(dev)))) {
3839#ifdef DEBUG_INTERRUPT_ERROR
3840 printk(KERN_INFO
3841 "%s: wavelan_interrupt(): RU not ready -- restarting\n",
3842 dev->name);
3843#endif
3844 wv_hw_reset(dev);
3845 }
3846
3847 /* Release spinlock */
3848 spin_unlock (&lp->spinlock);
3849
3850#ifdef DEBUG_INTERRUPT_TRACE
3851 printk(KERN_DEBUG "%s: <-wavelan_interrupt()\n", dev->name);
3852#endif
3853 return IRQ_HANDLED;
3854}
3855
3856/*------------------------------------------------------------------*/
3857/*
3858 * Watchdog: when we start a transmission, a timer is set for us in the
3859 * kernel. If the transmission completes, this timer is disabled. If
3860 * the timer expires, we are called and we try to unlock the hardware.
3861 */
3862static void wavelan_watchdog(struct net_device * dev)
3863{
3864 net_local *lp = netdev_priv(dev);
3865 u_long ioaddr = dev->base_addr;
3866 unsigned long flags;
3867 unsigned int nreaped;
3868
3869#ifdef DEBUG_INTERRUPT_TRACE
3870 printk(KERN_DEBUG "%s: ->wavelan_watchdog()\n", dev->name);
3871#endif
3872
3873#ifdef DEBUG_INTERRUPT_ERROR
3874 printk(KERN_INFO "%s: wavelan_watchdog: watchdog timer expired\n",
3875 dev->name);
3876#endif
3877
3878 /* Check that we came here for something */
3879 if (lp->tx_n_in_use <= 0) {
3880 return;
3881 }
3882
3883 spin_lock_irqsave(&lp->spinlock, flags);
3884
3885 /* Try to see if some buffers are not free (in case we missed
3886 * an interrupt */
3887 nreaped = wv_complete(dev, ioaddr, lp);
3888
3889#ifdef DEBUG_INTERRUPT_INFO
3890 printk(KERN_DEBUG
3891 "%s: wavelan_watchdog(): %d reaped, %d remain.\n",
3892 dev->name, nreaped, lp->tx_n_in_use);
3893#endif
3894
3895#ifdef DEBUG_PSA_SHOW
3896 {
3897 psa_t psa;
3898 psa_read(dev, 0, (unsigned char *) &psa, sizeof(psa));
3899 wv_psa_show(&psa);
3900 }
3901#endif
3902#ifdef DEBUG_MMC_SHOW
3903 wv_mmc_show(dev);
3904#endif
3905#ifdef DEBUG_I82586_SHOW
3906 wv_cu_show(dev);
3907#endif
3908
3909 /* If no buffer has been freed */
3910 if (nreaped == 0) {
3911#ifdef DEBUG_INTERRUPT_ERROR
3912 printk(KERN_INFO
3913 "%s: wavelan_watchdog(): cleanup failed, trying reset\n",
3914 dev->name);
3915#endif
3916 wv_hw_reset(dev);
3917 }
3918
3919 /* At this point, we should have some free Tx buffer ;-) */
3920 if (lp->tx_n_in_use < NTXBLOCKS - 1)
3921 netif_wake_queue(dev);
3922
3923 spin_unlock_irqrestore(&lp->spinlock, flags);
3924
3925#ifdef DEBUG_INTERRUPT_TRACE
3926 printk(KERN_DEBUG "%s: <-wavelan_watchdog()\n", dev->name);
3927#endif
3928}
3929
3930/********************* CONFIGURATION CALLBACKS *********************/
3931/*
3932 * Here are the functions called by the Linux networking code (NET3)
3933 * for initialization, configuration and deinstallations of the
3934 * WaveLAN ISA hardware.
3935 */
3936
3937/*------------------------------------------------------------------*/
3938/*
3939 * Configure and start up the WaveLAN PCMCIA adaptor.
3940 * Called by NET3 when it "opens" the device.
3941 */
3942static int wavelan_open(struct net_device * dev)
3943{
3944 net_local *lp = netdev_priv(dev);
3945 unsigned long flags;
3946
3947#ifdef DEBUG_CALLBACK_TRACE
3948 printk(KERN_DEBUG "%s: ->wavelan_open(dev=0x%x)\n", dev->name,
3949 (unsigned int) dev);
3950#endif
3951
3952 /* Check irq */
3953 if (dev->irq == 0) {
3954#ifdef DEBUG_CONFIG_ERROR
3955 printk(KERN_WARNING "%s: wavelan_open(): no IRQ\n",
3956 dev->name);
3957#endif
3958 return -ENXIO;
3959 }
3960
3961 if (request_irq(dev->irq, &wavelan_interrupt, 0, "WaveLAN", dev) != 0)
3962 {
3963#ifdef DEBUG_CONFIG_ERROR
3964 printk(KERN_WARNING "%s: wavelan_open(): invalid IRQ\n",
3965 dev->name);
3966#endif
3967 return -EAGAIN;
3968 }
3969
3970 spin_lock_irqsave(&lp->spinlock, flags);
3971
3972 if (wv_hw_reset(dev) != -1) {
3973 netif_start_queue(dev);
3974 } else {
3975 free_irq(dev->irq, dev);
3976#ifdef DEBUG_CONFIG_ERROR
3977 printk(KERN_INFO
3978 "%s: wavelan_open(): impossible to start the card\n",
3979 dev->name);
3980#endif
3981 spin_unlock_irqrestore(&lp->spinlock, flags);
3982 return -EAGAIN;
3983 }
3984 spin_unlock_irqrestore(&lp->spinlock, flags);
3985
3986#ifdef DEBUG_CALLBACK_TRACE
3987 printk(KERN_DEBUG "%s: <-wavelan_open()\n", dev->name);
3988#endif
3989 return 0;
3990}
3991
3992/*------------------------------------------------------------------*/
3993/*
3994 * Shut down the WaveLAN ISA card.
3995 * Called by NET3 when it "closes" the device.
3996 */
3997static int wavelan_close(struct net_device * dev)
3998{
3999 net_local *lp = netdev_priv(dev);
4000 unsigned long flags;
4001
4002#ifdef DEBUG_CALLBACK_TRACE
4003 printk(KERN_DEBUG "%s: ->wavelan_close(dev=0x%x)\n", dev->name,
4004 (unsigned int) dev);
4005#endif
4006
4007 netif_stop_queue(dev);
4008
4009 /*
4010 * Flush the Tx and disable Rx.
4011 */
4012 spin_lock_irqsave(&lp->spinlock, flags);
4013 wv_82586_stop(dev);
4014 spin_unlock_irqrestore(&lp->spinlock, flags);
4015
4016 free_irq(dev->irq, dev);
4017
4018#ifdef DEBUG_CALLBACK_TRACE
4019 printk(KERN_DEBUG "%s: <-wavelan_close()\n", dev->name);
4020#endif
4021 return 0;
4022}
4023
4024static const struct net_device_ops wavelan_netdev_ops = {
4025 .ndo_open = wavelan_open,
4026 .ndo_stop = wavelan_close,
4027 .ndo_start_xmit = wavelan_packet_xmit,
4028 .ndo_set_multicast_list = wavelan_set_multicast_list,
4029 .ndo_tx_timeout = wavelan_watchdog,
4030 .ndo_change_mtu = eth_change_mtu,
4031 .ndo_validate_addr = eth_validate_addr,
4032#ifdef SET_MAC_ADDRESS
4033 .ndo_set_mac_address = wavelan_set_mac_address
4034#else
4035 .ndo_set_mac_address = eth_mac_addr,
4036#endif
4037};
4038
4039
4040/*------------------------------------------------------------------*/
4041/*
4042 * Probe an I/O address, and if the WaveLAN is there configure the
4043 * device structure
4044 * (called by wavelan_probe() and via init_module()).
4045 */
4046static int __init wavelan_config(struct net_device *dev, unsigned short ioaddr)
4047{
4048 u8 irq_mask;
4049 int irq;
4050 net_local *lp;
4051 mac_addr mac;
4052 int err;
4053
4054 if (!request_region(ioaddr, sizeof(ha_t), "wavelan"))
4055 return -EADDRINUSE;
4056
4057 err = wv_check_ioaddr(ioaddr, mac);
4058 if (err)
4059 goto out;
4060
4061 memcpy(dev->dev_addr, mac, 6);
4062
4063 dev->base_addr = ioaddr;
4064
4065#ifdef DEBUG_CALLBACK_TRACE
4066 printk(KERN_DEBUG "%s: ->wavelan_config(dev=0x%x, ioaddr=0x%lx)\n",
4067 dev->name, (unsigned int) dev, ioaddr);
4068#endif
4069
4070 /* Check IRQ argument on command line. */
4071 if (dev->irq != 0) {
4072 irq_mask = wv_irq_to_psa(dev->irq);
4073
4074 if (irq_mask == 0) {
4075#ifdef DEBUG_CONFIG_ERROR
4076 printk(KERN_WARNING
4077 "%s: wavelan_config(): invalid IRQ %d ignored.\n",
4078 dev->name, dev->irq);
4079#endif
4080 dev->irq = 0;
4081 } else {
4082#ifdef DEBUG_CONFIG_INFO
4083 printk(KERN_DEBUG
4084 "%s: wavelan_config(): changing IRQ to %d\n",
4085 dev->name, dev->irq);
4086#endif
4087 psa_write(ioaddr, HACR_DEFAULT,
4088 psaoff(0, psa_int_req_no), &irq_mask, 1);
4089 /* update the Wavelan checksum */
4090 update_psa_checksum(dev, ioaddr, HACR_DEFAULT);
4091 wv_hacr_reset(ioaddr);
4092 }
4093 }
4094
4095 psa_read(ioaddr, HACR_DEFAULT, psaoff(0, psa_int_req_no),
4096 &irq_mask, 1);
4097 if ((irq = wv_psa_to_irq(irq_mask)) == -1) {
4098#ifdef DEBUG_CONFIG_ERROR
4099 printk(KERN_INFO
4100 "%s: wavelan_config(): could not wavelan_map_irq(%d).\n",
4101 dev->name, irq_mask);
4102#endif
4103 err = -EAGAIN;
4104 goto out;
4105 }
4106
4107 dev->irq = irq;
4108
4109 dev->mem_start = 0x0000;
4110 dev->mem_end = 0x0000;
4111 dev->if_port = 0;
4112
4113 /* Initialize device structures */
4114 memset(netdev_priv(dev), 0, sizeof(net_local));
4115 lp = netdev_priv(dev);
4116
4117 /* Back link to the device structure. */
4118 lp->dev = dev;
4119 /* Add the device at the beginning of the linked list. */
4120 lp->next = wavelan_list;
4121 wavelan_list = lp;
4122
4123 lp->hacr = HACR_DEFAULT;
4124
4125 /* Multicast stuff */
4126 lp->promiscuous = 0;
4127 lp->mc_count = 0;
4128
4129 /* Init spinlock */
4130 spin_lock_init(&lp->spinlock);
4131
4132 dev->netdev_ops = &wavelan_netdev_ops;
4133 dev->watchdog_timeo = WATCHDOG_JIFFIES;
4134 dev->wireless_handlers = &wavelan_handler_def;
4135 lp->wireless_data.spy_data = &lp->spy_data;
4136 dev->wireless_data = &lp->wireless_data;
4137
4138 dev->mtu = WAVELAN_MTU;
4139
4140 /* Display nice information. */
4141 wv_init_info(dev);
4142
4143#ifdef DEBUG_CALLBACK_TRACE
4144 printk(KERN_DEBUG "%s: <-wavelan_config()\n", dev->name);
4145#endif
4146 return 0;
4147out:
4148 release_region(ioaddr, sizeof(ha_t));
4149 return err;
4150}
4151
4152/*------------------------------------------------------------------*/
4153/*
4154 * Check for a network adaptor of this type. Return '0' iff one
4155 * exists. There seem to be different interpretations of
4156 * the initial value of dev->base_addr.
4157 * We follow the example in drivers/net/ne.c.
4158 * (called in "Space.c")
4159 */
4160struct net_device * __init wavelan_probe(int unit)
4161{
4162 struct net_device *dev;
4163 short base_addr;
4164 int def_irq;
4165 int i;
4166 int r = 0;
4167
4168 /* compile-time check the sizes of structures */
4169 BUILD_BUG_ON(sizeof(psa_t) != PSA_SIZE);
4170 BUILD_BUG_ON(sizeof(mmw_t) != MMW_SIZE);
4171 BUILD_BUG_ON(sizeof(mmr_t) != MMR_SIZE);
4172 BUILD_BUG_ON(sizeof(ha_t) != HA_SIZE);
4173
4174 dev = alloc_etherdev(sizeof(net_local));
4175 if (!dev)
4176 return ERR_PTR(-ENOMEM);
4177
4178 sprintf(dev->name, "eth%d", unit);
4179 netdev_boot_setup_check(dev);
4180 base_addr = dev->base_addr;
4181 def_irq = dev->irq;
4182
4183#ifdef DEBUG_CALLBACK_TRACE
4184 printk(KERN_DEBUG
4185 "%s: ->wavelan_probe(dev=%p (base_addr=0x%x))\n",
4186 dev->name, dev, (unsigned int) dev->base_addr);
4187#endif
4188
4189 /* Don't probe at all. */
4190 if (base_addr < 0) {
4191#ifdef DEBUG_CONFIG_ERROR
4192 printk(KERN_WARNING
4193 "%s: wavelan_probe(): invalid base address\n",
4194 dev->name);
4195#endif
4196 r = -ENXIO;
4197 } else if (base_addr > 0x100) { /* Check a single specified location. */
4198 r = wavelan_config(dev, base_addr);
4199#ifdef DEBUG_CONFIG_INFO
4200 if (r != 0)
4201 printk(KERN_DEBUG
4202 "%s: wavelan_probe(): no device at specified base address (0x%X) or address already in use\n",
4203 dev->name, base_addr);
4204#endif
4205
4206#ifdef DEBUG_CALLBACK_TRACE
4207 printk(KERN_DEBUG "%s: <-wavelan_probe()\n", dev->name);
4208#endif
4209 } else { /* Scan all possible addresses of the WaveLAN hardware. */
4210 for (i = 0; i < ARRAY_SIZE(iobase); i++) {
4211 dev->irq = def_irq;
4212 if (wavelan_config(dev, iobase[i]) == 0) {
4213#ifdef DEBUG_CALLBACK_TRACE
4214 printk(KERN_DEBUG
4215 "%s: <-wavelan_probe()\n",
4216 dev->name);
4217#endif
4218 break;
4219 }
4220 }
4221 if (i == ARRAY_SIZE(iobase))
4222 r = -ENODEV;
4223 }
4224 if (r)
4225 goto out;
4226 r = register_netdev(dev);
4227 if (r)
4228 goto out1;
4229 return dev;
4230out1:
4231 release_region(dev->base_addr, sizeof(ha_t));
4232 wavelan_list = wavelan_list->next;
4233out:
4234 free_netdev(dev);
4235 return ERR_PTR(r);
4236}
4237
4238/****************************** MODULE ******************************/
4239/*
4240 * Module entry point: insertion and removal
4241 */
4242
4243#ifdef MODULE
4244/*------------------------------------------------------------------*/
4245/*
4246 * Insertion of the module
4247 * I'm now quite proud of the multi-device support.
4248 */
4249int __init init_module(void)
4250{
4251 int ret = -EIO; /* Return error if no cards found */
4252 int i;
4253
4254#ifdef DEBUG_MODULE_TRACE
4255 printk(KERN_DEBUG "-> init_module()\n");
4256#endif
4257
4258 /* If probing is asked */
4259 if (io[0] == 0) {
4260#ifdef DEBUG_CONFIG_ERROR
4261 printk(KERN_WARNING
4262 "WaveLAN init_module(): doing device probing (bad !)\n");
4263 printk(KERN_WARNING
4264 "Specify base addresses while loading module to correct the problem\n");
4265#endif
4266
4267 /* Copy the basic set of address to be probed. */
4268 for (i = 0; i < ARRAY_SIZE(iobase); i++)
4269 io[i] = iobase[i];
4270 }
4271
4272
4273 /* Loop on all possible base addresses. */
4274 for (i = 0; i < ARRAY_SIZE(io) && io[i] != 0; i++) {
4275 struct net_device *dev = alloc_etherdev(sizeof(net_local));
4276 if (!dev)
4277 break;
4278 if (name[i])
4279 strcpy(dev->name, name[i]); /* Copy name */
4280 dev->base_addr = io[i];
4281 dev->irq = irq[i];
4282
4283 /* Check if there is something at this base address. */
4284 if (wavelan_config(dev, io[i]) == 0) {
4285 if (register_netdev(dev) != 0) {
4286 release_region(dev->base_addr, sizeof(ha_t));
4287 wavelan_list = wavelan_list->next;
4288 } else {
4289 ret = 0;
4290 continue;
4291 }
4292 }
4293 free_netdev(dev);
4294 }
4295
4296#ifdef DEBUG_CONFIG_ERROR
4297 if (!wavelan_list)
4298 printk(KERN_WARNING
4299 "WaveLAN init_module(): no device found\n");
4300#endif
4301
4302#ifdef DEBUG_MODULE_TRACE
4303 printk(KERN_DEBUG "<- init_module()\n");
4304#endif
4305 return ret;
4306}
4307
4308/*------------------------------------------------------------------*/
4309/*
4310 * Removal of the module
4311 */
4312void cleanup_module(void)
4313{
4314#ifdef DEBUG_MODULE_TRACE
4315 printk(KERN_DEBUG "-> cleanup_module()\n");
4316#endif
4317
4318 /* Loop on all devices and release them. */
4319 while (wavelan_list) {
4320 struct net_device *dev = wavelan_list->dev;
4321
4322#ifdef DEBUG_CONFIG_INFO
4323 printk(KERN_DEBUG
4324 "%s: cleanup_module(): removing device at 0x%x\n",
4325 dev->name, (unsigned int) dev);
4326#endif
4327 unregister_netdev(dev);
4328
4329 release_region(dev->base_addr, sizeof(ha_t));
4330 wavelan_list = wavelan_list->next;
4331
4332 free_netdev(dev);
4333 }
4334
4335#ifdef DEBUG_MODULE_TRACE
4336 printk(KERN_DEBUG "<- cleanup_module()\n");
4337#endif
4338}
4339#endif /* MODULE */
4340MODULE_LICENSE("GPL");
4341
4342/*
4343 * This software may only be used and distributed
4344 * according to the terms of the GNU General Public License.
4345 *
4346 * This software was developed as a component of the
4347 * Linux operating system.
4348 * It is based on other device drivers and information
4349 * either written or supplied by:
4350 * Ajay Bakre (bakre@paul.rutgers.edu),
4351 * Donald Becker (becker@scyld.com),
4352 * Loeke Brederveld (Loeke.Brederveld@Utrecht.NCR.com),
4353 * Anders Klemets (klemets@it.kth.se),
4354 * Vladimir V. Kolpakov (w@stier.koenig.ru),
4355 * Marc Meertens (Marc.Meertens@Utrecht.NCR.com),
4356 * Pauline Middelink (middelin@polyware.iaf.nl),
4357 * Robert Morris (rtm@das.harvard.edu),
4358 * Jean Tourrilhes (jt@hplb.hpl.hp.com),
4359 * Girish Welling (welling@paul.rutgers.edu),
4360 *
4361 * Thanks go also to:
4362 * James Ashton (jaa101@syseng.anu.edu.au),
4363 * Alan Cox (alan@lxorguk.ukuu.org.uk),
4364 * Allan Creighton (allanc@cs.usyd.edu.au),
4365 * Matthew Geier (matthew@cs.usyd.edu.au),
4366 * Remo di Giovanni (remo@cs.usyd.edu.au),
4367 * Eckhard Grah (grah@wrcs1.urz.uni-wuppertal.de),
4368 * Vipul Gupta (vgupta@cs.binghamton.edu),
4369 * Mark Hagan (mhagan@wtcpost.daytonoh.NCR.COM),
4370 * Tim Nicholson (tim@cs.usyd.edu.au),
4371 * Ian Parkin (ian@cs.usyd.edu.au),
4372 * John Rosenberg (johnr@cs.usyd.edu.au),
4373 * George Rossi (george@phm.gov.au),
4374 * Arthur Scott (arthur@cs.usyd.edu.au),
4375 * Peter Storey,
4376 * for their assistance and advice.
4377 *
4378 * Please send bug reports, updates, comments to:
4379 *
4380 * Bruce Janson Email: bruce@cs.usyd.edu.au
4381 * Basser Department of Computer Science Phone: +61-2-9351-3423
4382 * University of Sydney, N.S.W., 2006, AUSTRALIA Fax: +61-2-9351-3838
4383 */
diff --git a/drivers/net/wireless/wavelan.h b/drivers/net/wireless/wavelan.h
deleted file mode 100644
index 9ab360558ffd..000000000000
--- a/drivers/net/wireless/wavelan.h
+++ /dev/null
@@ -1,370 +0,0 @@
1/*
2 * WaveLAN ISA driver
3 *
4 * Jean II - HPLB '96
5 *
6 * Reorganisation and extension of the driver.
7 * Original copyright follows. See wavelan.p.h for details.
8 *
9 * This file contains the declarations for the WaveLAN hardware. Note that
10 * the WaveLAN ISA includes a i82586 controller (see definitions in
11 * file i82586.h).
12 *
13 * The main difference between the ISA hardware and the PCMCIA one is
14 * the Ethernet controller (i82586 instead of i82593).
15 * The i82586 allows multiple transmit buffers. The PSA needs to be accessed
16 * through the host interface.
17 */
18
19#ifndef _WAVELAN_H
20#define _WAVELAN_H
21
22/************************** MAGIC NUMBERS ***************************/
23
24/* Detection of the WaveLAN card is done by reading the MAC
25 * address from the card and checking it. If you have a non-AT&T
26 * product (OEM, like DEC RoamAbout, Digital Ocean, or Epson),
27 * you might need to modify this part to accommodate your hardware.
28 */
29static const char MAC_ADDRESSES[][3] =
30{
31 { 0x08, 0x00, 0x0E }, /* AT&T WaveLAN (standard) & DEC RoamAbout */
32 { 0x08, 0x00, 0x6A }, /* AT&T WaveLAN (alternate) */
33 { 0x00, 0x00, 0xE1 }, /* Hitachi Wavelan */
34 { 0x00, 0x60, 0x1D } /* Lucent Wavelan (another one) */
35 /* Add your card here and send me the patch! */
36};
37
38#define WAVELAN_ADDR_SIZE 6 /* Size of a MAC address */
39
40#define WAVELAN_MTU 1500 /* Maximum size of WaveLAN packet */
41
42#define MAXDATAZ (WAVELAN_ADDR_SIZE + WAVELAN_ADDR_SIZE + 2 + WAVELAN_MTU)
43
44/*
45 * Constants used to convert channels to frequencies
46 */
47
48/* Frequency available in the 2.0 modem, in units of 250 kHz
49 * (as read in the offset register of the dac area).
50 * Used to map channel numbers used by `wfreqsel' to frequencies
51 */
52static const short channel_bands[] = { 0x30, 0x58, 0x64, 0x7A, 0x80, 0xA8,
53 0xD0, 0xF0, 0xF8, 0x150 };
54
55/* Frequencies of the 1.0 modem (fixed frequencies).
56 * Use to map the PSA `subband' to a frequency
57 * Note : all frequencies apart from the first one need to be multiplied by 10
58 */
59static const int fixed_bands[] = { 915e6, 2.425e8, 2.46e8, 2.484e8, 2.4305e8 };
60
61
62
63/*************************** PC INTERFACE ****************************/
64
65/*
66 * Host Adaptor structure.
67 * (base is board port address).
68 */
69typedef union hacs_u hacs_u;
70union hacs_u
71{
72 unsigned short hu_command; /* Command register */
73#define HACR_RESET 0x0001 /* Reset board */
74#define HACR_CA 0x0002 /* Set Channel Attention for 82586 */
75#define HACR_16BITS 0x0004 /* 16-bit operation (0 => 8bits) */
76#define HACR_OUT0 0x0008 /* General purpose output pin 0 */
77 /* not used - must be 1 */
78#define HACR_OUT1 0x0010 /* General purpose output pin 1 */
79 /* not used - must be 1 */
80#define HACR_82586_INT_ENABLE 0x0020 /* Enable 82586 interrupts */
81#define HACR_MMC_INT_ENABLE 0x0040 /* Enable MMC interrupts */
82#define HACR_INTR_CLR_ENABLE 0x0080 /* Enable interrupt status read/clear */
83 unsigned short hu_status; /* Status Register */
84#define HASR_82586_INTR 0x0001 /* Interrupt request from 82586 */
85#define HASR_MMC_INTR 0x0002 /* Interrupt request from MMC */
86#define HASR_MMC_BUSY 0x0004 /* MMC busy indication */
87#define HASR_PSA_BUSY 0x0008 /* LAN parameter storage area busy */
88} __attribute__ ((packed));
89
90typedef struct ha_t ha_t;
91struct ha_t
92{
93 hacs_u ha_cs; /* Command and status registers */
94#define ha_command ha_cs.hu_command
95#define ha_status ha_cs.hu_status
96 unsigned short ha_mmcr; /* Modem Management Ctrl Register */
97 unsigned short ha_pior0; /* Program I/O Address Register Port 0 */
98 unsigned short ha_piop0; /* Program I/O Port 0 */
99 unsigned short ha_pior1; /* Program I/O Address Register Port 1 */
100 unsigned short ha_piop1; /* Program I/O Port 1 */
101 unsigned short ha_pior2; /* Program I/O Address Register Port 2 */
102 unsigned short ha_piop2; /* Program I/O Port 2 */
103};
104
105#define HA_SIZE 16
106
107#define hoff(p,f) (unsigned short)((void *)(&((ha_t *)((void *)0 + (p)))->f) - (void *)0)
108#define HACR(p) hoff(p, ha_command)
109#define HASR(p) hoff(p, ha_status)
110#define MMCR(p) hoff(p, ha_mmcr)
111#define PIOR0(p) hoff(p, ha_pior0)
112#define PIOP0(p) hoff(p, ha_piop0)
113#define PIOR1(p) hoff(p, ha_pior1)
114#define PIOP1(p) hoff(p, ha_piop1)
115#define PIOR2(p) hoff(p, ha_pior2)
116#define PIOP2(p) hoff(p, ha_piop2)
117
118/*
119 * Program I/O Mode Register values.
120 */
121#define STATIC_PIO 0 /* Mode 1: static mode */
122 /* RAM access ??? */
123#define AUTOINCR_PIO 1 /* Mode 2: auto increment mode */
124 /* RAM access ??? */
125#define AUTODECR_PIO 2 /* Mode 3: auto decrement mode */
126 /* RAM access ??? */
127#define PARAM_ACCESS_PIO 3 /* Mode 4: LAN parameter access mode */
128 /* Parameter access. */
129#define PIO_MASK 3 /* register mask */
130#define PIOM(cmd,piono) ((u_short)cmd << 10 << (piono * 2))
131
132#define HACR_DEFAULT (HACR_OUT0 | HACR_OUT1 | HACR_16BITS | PIOM(STATIC_PIO, 0) | PIOM(AUTOINCR_PIO, 1) | PIOM(PARAM_ACCESS_PIO, 2))
133#define HACR_INTRON (HACR_82586_INT_ENABLE | HACR_MMC_INT_ENABLE | HACR_INTR_CLR_ENABLE)
134
135/************************** MEMORY LAYOUT **************************/
136
137/*
138 * Onboard 64 k RAM layout.
139 * (Offsets from 0x0000.)
140 */
141#define OFFSET_RU 0x0000 /* 75% memory */
142#define OFFSET_CU 0xC000 /* 25% memory */
143#define OFFSET_SCB (OFFSET_ISCP - sizeof(scb_t))
144#define OFFSET_ISCP (OFFSET_SCP - sizeof(iscp_t))
145#define OFFSET_SCP I82586_SCP_ADDR
146
147#define RXBLOCKZ (sizeof(fd_t) + sizeof(rbd_t) + MAXDATAZ)
148#define TXBLOCKZ (sizeof(ac_tx_t) + sizeof(ac_nop_t) + sizeof(tbd_t) + MAXDATAZ)
149
150#define NRXBLOCKS ((OFFSET_CU - OFFSET_RU) / RXBLOCKZ)
151#define NTXBLOCKS ((OFFSET_SCB - OFFSET_CU) / TXBLOCKZ)
152
153/********************** PARAMETER STORAGE AREA **********************/
154
155/*
156 * Parameter Storage Area (PSA).
157 */
158typedef struct psa_t psa_t;
159struct psa_t
160{
161 unsigned char psa_io_base_addr_1; /* [0x00] Base address 1 ??? */
162 unsigned char psa_io_base_addr_2; /* [0x01] Base address 2 */
163 unsigned char psa_io_base_addr_3; /* [0x02] Base address 3 */
164 unsigned char psa_io_base_addr_4; /* [0x03] Base address 4 */
165 unsigned char psa_rem_boot_addr_1; /* [0x04] Remote Boot Address 1 */
166 unsigned char psa_rem_boot_addr_2; /* [0x05] Remote Boot Address 2 */
167 unsigned char psa_rem_boot_addr_3; /* [0x06] Remote Boot Address 3 */
168 unsigned char psa_holi_params; /* [0x07] HOst Lan Interface (HOLI) Parameters */
169 unsigned char psa_int_req_no; /* [0x08] Interrupt Request Line */
170 unsigned char psa_unused0[7]; /* [0x09-0x0F] unused */
171
172 unsigned char psa_univ_mac_addr[WAVELAN_ADDR_SIZE]; /* [0x10-0x15] Universal (factory) MAC Address */
173 unsigned char psa_local_mac_addr[WAVELAN_ADDR_SIZE]; /* [0x16-1B] Local MAC Address */
174 unsigned char psa_univ_local_sel; /* [0x1C] Universal Local Selection */
175#define PSA_UNIVERSAL 0 /* Universal (factory) */
176#define PSA_LOCAL 1 /* Local */
177 unsigned char psa_comp_number; /* [0x1D] Compatibility Number: */
178#define PSA_COMP_PC_AT_915 0 /* PC-AT 915 MHz */
179#define PSA_COMP_PC_MC_915 1 /* PC-MC 915 MHz */
180#define PSA_COMP_PC_AT_2400 2 /* PC-AT 2.4 GHz */
181#define PSA_COMP_PC_MC_2400 3 /* PC-MC 2.4 GHz */
182#define PSA_COMP_PCMCIA_915 4 /* PCMCIA 915 MHz or 2.0 */
183 unsigned char psa_thr_pre_set; /* [0x1E] Modem Threshold Preset */
184 unsigned char psa_feature_select; /* [0x1F] Call code required (1=on) */
185#define PSA_FEATURE_CALL_CODE 0x01 /* Call code required (Japan) */
186 unsigned char psa_subband; /* [0x20] Subband */
187#define PSA_SUBBAND_915 0 /* 915 MHz or 2.0 */
188#define PSA_SUBBAND_2425 1 /* 2425 MHz */
189#define PSA_SUBBAND_2460 2 /* 2460 MHz */
190#define PSA_SUBBAND_2484 3 /* 2484 MHz */
191#define PSA_SUBBAND_2430_5 4 /* 2430.5 MHz */
192 unsigned char psa_quality_thr; /* [0x21] Modem Quality Threshold */
193 unsigned char psa_mod_delay; /* [0x22] Modem Delay (?) (reserved) */
194 unsigned char psa_nwid[2]; /* [0x23-0x24] Network ID */
195 unsigned char psa_nwid_select; /* [0x25] Network ID Select On/Off */
196 unsigned char psa_encryption_select; /* [0x26] Encryption On/Off */
197 unsigned char psa_encryption_key[8]; /* [0x27-0x2E] Encryption Key */
198 unsigned char psa_databus_width; /* [0x2F] AT bus width select 8/16 */
199 unsigned char psa_call_code[8]; /* [0x30-0x37] (Japan) Call Code */
200 unsigned char psa_nwid_prefix[2]; /* [0x38-0x39] Roaming domain */
201 unsigned char psa_reserved[2]; /* [0x3A-0x3B] Reserved - fixed 00 */
202 unsigned char psa_conf_status; /* [0x3C] Conf Status, bit 0=1:config*/
203 unsigned char psa_crc[2]; /* [0x3D] CRC-16 over PSA */
204 unsigned char psa_crc_status; /* [0x3F] CRC Valid Flag */
205};
206
207#define PSA_SIZE 64
208
209/* Calculate offset of a field in the above structure.
210 * Warning: only even addresses are used. */
211#define psaoff(p,f) ((unsigned short) ((void *)(&((psa_t *) ((void *) NULL + (p)))->f) - (void *) NULL))
212
213/******************** MODEM MANAGEMENT INTERFACE ********************/
214
215/*
216 * Modem Management Controller (MMC) write structure.
217 */
218typedef struct mmw_t mmw_t;
219struct mmw_t
220{
221 unsigned char mmw_encr_key[8]; /* encryption key */
222 unsigned char mmw_encr_enable; /* Enable or disable encryption. */
223#define MMW_ENCR_ENABLE_MODE 0x02 /* mode of security option */
224#define MMW_ENCR_ENABLE_EN 0x01 /* Enable security option. */
225 unsigned char mmw_unused0[1]; /* unused */
226 unsigned char mmw_des_io_invert; /* encryption option */
227#define MMW_DES_IO_INVERT_RES 0x0F /* reserved */
228#define MMW_DES_IO_INVERT_CTRL 0xF0 /* control (?) (set to 0) */
229 unsigned char mmw_unused1[5]; /* unused */
230 unsigned char mmw_loopt_sel; /* looptest selection */
231#define MMW_LOOPT_SEL_DIS_NWID 0x40 /* Disable NWID filtering. */
232#define MMW_LOOPT_SEL_INT 0x20 /* Activate Attention Request. */
233#define MMW_LOOPT_SEL_LS 0x10 /* looptest, no collision avoidance */
234#define MMW_LOOPT_SEL_LT3A 0x08 /* looptest 3a */
235#define MMW_LOOPT_SEL_LT3B 0x04 /* looptest 3b */
236#define MMW_LOOPT_SEL_LT3C 0x02 /* looptest 3c */
237#define MMW_LOOPT_SEL_LT3D 0x01 /* looptest 3d */
238 unsigned char mmw_jabber_enable; /* jabber timer enable */
239 /* Abort transmissions > 200 ms */
240 unsigned char mmw_freeze; /* freeze or unfreeze signal level */
241 /* 0 : signal level & qual updated for every new message, 1 : frozen */
242 unsigned char mmw_anten_sel; /* antenna selection */
243#define MMW_ANTEN_SEL_SEL 0x01 /* direct antenna selection */
244#define MMW_ANTEN_SEL_ALG_EN 0x02 /* antenna selection algo. enable */
245 unsigned char mmw_ifs; /* inter frame spacing */
246 /* min time between transmission in bit periods (.5 us) - bit 0 ignored */
247 unsigned char mmw_mod_delay; /* modem delay (synchro) */
248 unsigned char mmw_jam_time; /* jamming time (after collision) */
249 unsigned char mmw_unused2[1]; /* unused */
250 unsigned char mmw_thr_pre_set; /* level threshold preset */
251 /* Discard all packet with signal < this value (4) */
252 unsigned char mmw_decay_prm; /* decay parameters */
253 unsigned char mmw_decay_updat_prm; /* decay update parameters */
254 unsigned char mmw_quality_thr; /* quality (z-quotient) threshold */
255 /* Discard all packet with quality < this value (3) */
256 unsigned char mmw_netw_id_l; /* NWID low order byte */
257 unsigned char mmw_netw_id_h; /* NWID high order byte */
258 /* Network ID or Domain : create virtual net on the air */
259
260 /* 2.0 Hardware extension - frequency selection support */
261 unsigned char mmw_mode_select; /* for analog tests (set to 0) */
262 unsigned char mmw_unused3[1]; /* unused */
263 unsigned char mmw_fee_ctrl; /* frequency EEPROM control */
264#define MMW_FEE_CTRL_PRE 0x10 /* Enable protected instructions. */
265#define MMW_FEE_CTRL_DWLD 0x08 /* Download EEPROM to mmc. */
266#define MMW_FEE_CTRL_CMD 0x07 /* EEPROM commands: */
267#define MMW_FEE_CTRL_READ 0x06 /* Read */
268#define MMW_FEE_CTRL_WREN 0x04 /* Write enable */
269#define MMW_FEE_CTRL_WRITE 0x05 /* Write data to address. */
270#define MMW_FEE_CTRL_WRALL 0x04 /* Write data to all addresses. */
271#define MMW_FEE_CTRL_WDS 0x04 /* Write disable */
272#define MMW_FEE_CTRL_PRREAD 0x16 /* Read addr from protect register */
273#define MMW_FEE_CTRL_PREN 0x14 /* Protect register enable */
274#define MMW_FEE_CTRL_PRCLEAR 0x17 /* Unprotect all registers. */
275#define MMW_FEE_CTRL_PRWRITE 0x15 /* Write address in protect register */
276#define MMW_FEE_CTRL_PRDS 0x14 /* Protect register disable */
277 /* Never issue the PRDS command: it's irreversible! */
278
279 unsigned char mmw_fee_addr; /* EEPROM address */
280#define MMW_FEE_ADDR_CHANNEL 0xF0 /* Select the channel. */
281#define MMW_FEE_ADDR_OFFSET 0x0F /* Offset in channel data */
282#define MMW_FEE_ADDR_EN 0xC0 /* FEE_CTRL enable operations */
283#define MMW_FEE_ADDR_DS 0x00 /* FEE_CTRL disable operations */
284#define MMW_FEE_ADDR_ALL 0x40 /* FEE_CTRL all operations */
285#define MMW_FEE_ADDR_CLEAR 0xFF /* FEE_CTRL clear operations */
286
287 unsigned char mmw_fee_data_l; /* Write data to EEPROM. */
288 unsigned char mmw_fee_data_h; /* high octet */
289 unsigned char mmw_ext_ant; /* Setting for external antenna */
290#define MMW_EXT_ANT_EXTANT 0x01 /* Select external antenna */
291#define MMW_EXT_ANT_POL 0x02 /* Polarity of the antenna */
292#define MMW_EXT_ANT_INTERNAL 0x00 /* Internal antenna */
293#define MMW_EXT_ANT_EXTERNAL 0x03 /* External antenna */
294#define MMW_EXT_ANT_IQ_TEST 0x1C /* IQ test pattern (set to 0) */
295} __attribute__ ((packed));
296
297#define MMW_SIZE 37
298
299#define mmwoff(p,f) (unsigned short)((void *)(&((mmw_t *)((void *)0 + (p)))->f) - (void *)0)
300
301/*
302 * Modem Management Controller (MMC) read structure.
303 */
304typedef struct mmr_t mmr_t;
305struct mmr_t
306{
307 unsigned char mmr_unused0[8]; /* unused */
308 unsigned char mmr_des_status; /* encryption status */
309 unsigned char mmr_des_avail; /* encryption available (0x55 read) */
310#define MMR_DES_AVAIL_DES 0x55 /* DES available */
311#define MMR_DES_AVAIL_AES 0x33 /* AES (AT&T) available */
312 unsigned char mmr_des_io_invert; /* des I/O invert register */
313 unsigned char mmr_unused1[5]; /* unused */
314 unsigned char mmr_dce_status; /* DCE status */
315#define MMR_DCE_STATUS_RX_BUSY 0x01 /* receiver busy */
316#define MMR_DCE_STATUS_LOOPT_IND 0x02 /* loop test indicated */
317#define MMR_DCE_STATUS_TX_BUSY 0x04 /* transmitter on */
318#define MMR_DCE_STATUS_JBR_EXPIRED 0x08 /* jabber timer expired */
319#define MMR_DCE_STATUS 0x0F /* mask to get the bits */
320 unsigned char mmr_dsp_id; /* DSP ID (AA = Daedalus rev A) */
321 unsigned char mmr_unused2[2]; /* unused */
322 unsigned char mmr_correct_nwid_l; /* # of correct NWIDs rxd (low) */
323 unsigned char mmr_correct_nwid_h; /* # of correct NWIDs rxd (high) */
324 /* Warning: read high-order octet first! */
325 unsigned char mmr_wrong_nwid_l; /* # of wrong NWIDs rxd (low) */
326 unsigned char mmr_wrong_nwid_h; /* # of wrong NWIDs rxd (high) */
327 unsigned char mmr_thr_pre_set; /* level threshold preset */
328#define MMR_THR_PRE_SET 0x3F /* level threshold preset */
329#define MMR_THR_PRE_SET_CUR 0x80 /* Current signal above it */
330 unsigned char mmr_signal_lvl; /* signal level */
331#define MMR_SIGNAL_LVL 0x3F /* signal level */
332#define MMR_SIGNAL_LVL_VALID 0x80 /* Updated since last read */
333 unsigned char mmr_silence_lvl; /* silence level (noise) */
334#define MMR_SILENCE_LVL 0x3F /* silence level */
335#define MMR_SILENCE_LVL_VALID 0x80 /* Updated since last read */
336 unsigned char mmr_sgnl_qual; /* signal quality */
337#define MMR_SGNL_QUAL 0x0F /* signal quality */
338#define MMR_SGNL_QUAL_ANT 0x80 /* current antenna used */
339 unsigned char mmr_netw_id_l; /* NWID low order byte (?) */
340 unsigned char mmr_unused3[3]; /* unused */
341
342 /* 2.0 Hardware extension - frequency selection support */
343 unsigned char mmr_fee_status; /* Status of frequency EEPROM */
344#define MMR_FEE_STATUS_ID 0xF0 /* Modem revision ID */
345#define MMR_FEE_STATUS_DWLD 0x08 /* Download in progress */
346#define MMR_FEE_STATUS_BUSY 0x04 /* EEPROM busy */
347 unsigned char mmr_unused4[1]; /* unused */
348 unsigned char mmr_fee_data_l; /* Read data from EEPROM (low) */
349 unsigned char mmr_fee_data_h; /* Read data from EEPROM (high) */
350} __attribute__ ((packed));
351
352#define MMR_SIZE 36
353
354#define mmroff(p,f) (unsigned short)((void *)(&((mmr_t *)((void *)0 + (p)))->f) - (void *)0)
355
356/* Make the two above structures one */
357typedef union mm_t
358{
359 struct mmw_t w; /* Write to the mmc */
360 struct mmr_t r; /* Read from the mmc */
361} mm_t;
362
363#endif /* _WAVELAN_H */
364
365/*
366 * This software may only be used and distributed
367 * according to the terms of the GNU General Public License.
368 *
369 * For more details, see wavelan.c.
370 */
diff --git a/drivers/net/wireless/wavelan.p.h b/drivers/net/wireless/wavelan.p.h
deleted file mode 100644
index dbe8de6e5f52..000000000000
--- a/drivers/net/wireless/wavelan.p.h
+++ /dev/null
@@ -1,696 +0,0 @@
1/*
2 * WaveLAN ISA driver
3 *
4 * Jean II - HPLB '96
5 *
6 * Reorganisation and extension of the driver.
7 *
8 * This file contains all definitions and declarations necessary for the
9 * WaveLAN ISA driver. This file is a private header, so it should
10 * be included only in wavelan.c!
11 */
12
13#ifndef WAVELAN_P_H
14#define WAVELAN_P_H
15
16/************************** DOCUMENTATION ***************************/
17/*
18 * This driver provides a Linux interface to the WaveLAN ISA hardware.
19 * The WaveLAN is a product of Lucent (http://www.wavelan.com/).
20 * This division was formerly part of NCR and then AT&T.
21 * WaveLANs are also distributed by DEC (RoamAbout DS) and Digital Ocean.
22 *
23 * To learn how to use this driver, read the NET3 HOWTO.
24 * If you want to exploit the many other functionalities, read the comments
25 * in the code.
26 *
27 * This driver is the result of the effort of many people (see below).
28 */
29
30/* ------------------------ SPECIFIC NOTES ------------------------ */
31/*
32 * Web page
33 * --------
34 * I try to maintain a web page with the Wireless LAN Howto at :
35 * http://www.hpl.hp.com/personal/Jean_Tourrilhes/Linux/Wavelan.html
36 *
37 * SMP
38 * ---
39 * We now are SMP compliant (I eventually fixed the remaining bugs).
40 * The driver has been tested on a dual P6-150 and survived my usual
41 * set of torture tests.
42 * Anyway, I spent enough time chasing interrupt re-entrancy during
43 * errors or reconfigure, and I designed the locked/unlocked sections
44 * of the driver with great care, and with the recent addition of
45 * the spinlock (thanks to the new API), we should be quite close to
46 * the truth.
47 * The SMP/IRQ locking is quite coarse and conservative (i.e. not fast),
48 * but better safe than sorry (especially at 2 Mb/s ;-).
49 *
50 * I have also looked into disabling only our interrupt on the card
51 * (via HACR) instead of all interrupts in the processor (via cli),
52 * so that other driver are not impacted, and it look like it's
53 * possible, but it's very tricky to do right (full of races). As
54 * the gain would be mostly for SMP systems, it can wait...
55 *
56 * Debugging and options
57 * ---------------------
58 * You will find below a set of '#define" allowing a very fine control
59 * on the driver behaviour and the debug messages printed.
60 * The main options are :
61 * o SET_PSA_CRC, to have your card correctly recognised by
62 * an access point and the Point-to-Point diagnostic tool.
63 * o USE_PSA_CONFIG, to read configuration from the PSA (EEprom)
64 * (otherwise we always start afresh with some defaults)
65 *
66 * wavelan.o is too darned big
67 * ---------------------------
68 * That's true! There is a very simple way to reduce the driver
69 * object by 33%! Comment out the following line:
70 * #include <linux/wireless.h>
71 * Other compile options can also reduce the size of it...
72 *
73 * MAC address and hardware detection:
74 * -----------------------------------
75 * The detection code for the WaveLAN checks that the first three
76 * octets of the MAC address fit the company code. This type of
77 * detection works well for AT&T cards (because the AT&T code is
78 * hardcoded in wavelan.h), but of course will fail for other
79 * manufacturers.
80 *
81 * If you are sure that your card is derived from the WaveLAN,
82 * here is the way to configure it:
83 * 1) Get your MAC address
84 * a) With your card utilities (wfreqsel, instconf, etc.)
85 * b) With the driver:
86 * o compile the kernel with DEBUG_CONFIG_INFO enabled
87 * o Boot and look the card messages
88 * 2) Set your MAC code (3 octets) in MAC_ADDRESSES[][3] (wavelan.h)
89 * 3) Compile and verify
90 * 4) Send me the MAC code. I will include it in the next version.
91 *
92 */
93
94/* --------------------- WIRELESS EXTENSIONS --------------------- */
95/*
96 * This driver is the first to support "wireless extensions".
97 * This set of extensions provides a standard way to control the wireless
98 * characteristics of the hardware. Applications such as mobile IP may
99 * take advantage of it.
100 *
101 * It might be a good idea as well to fetch the wireless tools to
102 * configure the device and play a bit.
103 */
104
105/* ---------------------------- FILES ---------------------------- */
106/*
107 * wavelan.c: actual code for the driver: C functions
108 *
109 * wavelan.p.h: private header: local types and variables for driver
110 *
111 * wavelan.h: description of the hardware interface and structs
112 *
113 * i82586.h: description of the Ethernet controller
114 */
115
116/* --------------------------- HISTORY --------------------------- */
117/*
118 * This is based on information in the drivers' headers. It may not be
119 * accurate, and I guarantee only my best effort.
120 *
121 * The history of the WaveLAN drivers is as complicated as the history of
122 * the WaveLAN itself (NCR -> AT&T -> Lucent).
123 *
124 * It all started with Anders Klemets <klemets@paul.rutgers.edu>
125 * writing a WaveLAN ISA driver for the Mach microkernel. Girish
126 * Welling <welling@paul.rutgers.edu> had also worked on it.
127 * Keith Moore modified this for the PCMCIA hardware.
128 *
129 * Robert Morris <rtm@das.harvard.edu> ported these two drivers to BSDI
130 * and added specific PCMCIA support (there is currently no equivalent
131 * of the PCMCIA package under BSD).
132 *
133 * Jim Binkley <jrb@cs.pdx.edu> ported both BSDI drivers to FreeBSD.
134 *
135 * Bruce Janson <bruce@cs.usyd.edu.au> ported the BSDI ISA driver to Linux.
136 *
137 * Anthony D. Joseph <adj@lcs.mit.edu> started to modify Bruce's driver
138 * (with help of the BSDI PCMCIA driver) for PCMCIA.
139 * Yunzhou Li <yunzhou@strat.iol.unh.edu> finished this work.
140 * Joe Finney <joe@comp.lancs.ac.uk> patched the driver to start
141 * 2.00 cards correctly (2.4 GHz with frequency selection).
142 * David Hinds <dahinds@users.sourceforge.net> integrated the whole in his
143 * PCMCIA package (and bug corrections).
144 *
145 * I (Jean Tourrilhes - jt@hplb.hpl.hp.com) then started to make some
146 * patches to the PCMCIA driver. Later, I added code in the ISA driver
147 * for Wireless Extensions and full support of frequency selection
148 * cards. Then, I did the same to the PCMCIA driver, and did some
149 * reorganisation. Finally, I came back to the ISA driver to
150 * upgrade it at the same level as the PCMCIA one and reorganise
151 * the code.
152 * Loeke Brederveld <lbrederv@wavelan.com> from Lucent has given me
153 * much needed information on the WaveLAN hardware.
154 */
155
156/* The original copyrights and literature mention others' names and
157 * credits. I don't know what their part in this development was.
158 */
159
160/* By the way, for the copyright and legal stuff:
161 * almost everybody wrote code under the GNU or BSD license (or similar),
162 * and want their original copyright to remain somewhere in the
163 * code (for myself, I go with the GPL).
164 * Nobody wants to take responsibility for anything, except the fame.
165 */
166
167/* --------------------------- CREDITS --------------------------- */
168/*
169 * This software was developed as a component of the
170 * Linux operating system.
171 * It is based on other device drivers and information
172 * either written or supplied by:
173 * Ajay Bakre <bakre@paul.rutgers.edu>,
174 * Donald Becker <becker@cesdis.gsfc.nasa.gov>,
175 * Loeke Brederveld <Loeke.Brederveld@Utrecht.NCR.com>,
176 * Brent Elphick <belphick@uwaterloo.ca>,
177 * Anders Klemets <klemets@it.kth.se>,
178 * Vladimir V. Kolpakov <w@stier.koenig.ru>,
179 * Marc Meertens <Marc.Meertens@Utrecht.NCR.com>,
180 * Pauline Middelink <middelin@polyware.iaf.nl>,
181 * Robert Morris <rtm@das.harvard.edu>,
182 * Jean Tourrilhes <jt@hpl.hp.com>,
183 * Girish Welling <welling@paul.rutgers.edu>,
184 * Clark Woodworth <clark@hiway1.exit109.com>
185 * Yongguang Zhang <ygz@isl.hrl.hac.com>
186 *
187 * Thanks go also to:
188 * James Ashton <jaa101@syseng.anu.edu.au>,
189 * Alan Cox <alan@lxorguk.ukuu.org.uk>,
190 * Allan Creighton <allanc@cs.usyd.edu.au>,
191 * Matthew Geier <matthew@cs.usyd.edu.au>,
192 * Remo di Giovanni <remo@cs.usyd.edu.au>,
193 * Eckhard Grah <grah@wrcs1.urz.uni-wuppertal.de>,
194 * Vipul Gupta <vgupta@cs.binghamton.edu>,
195 * Mark Hagan <mhagan@wtcpost.daytonoh.NCR.COM>,
196 * Tim Nicholson <tim@cs.usyd.edu.au>,
197 * Ian Parkin <ian@cs.usyd.edu.au>,
198 * John Rosenberg <johnr@cs.usyd.edu.au>,
199 * George Rossi <george@phm.gov.au>,
200 * Arthur Scott <arthur@cs.usyd.edu.au>,
201 * Stanislav Sinyagin <stas@isf.ru>
202 * and Peter Storey for their assistance and advice.
203 *
204 * Additional Credits:
205 *
206 * My development has been done initially under Debian 1.1 (Linux 2.0.x)
207 * and now under Debian 2.2, initially with an HP Vectra XP/60, and now
208 * an HP Vectra XP/90.
209 *
210 */
211
212/* ------------------------- IMPROVEMENTS ------------------------- */
213/*
214 * I proudly present:
215 *
216 * Changes made in first pre-release:
217 * ----------------------------------
218 * - reorganisation of the code, function name change
219 * - creation of private header (wavelan.p.h)
220 * - reorganised debug messages
221 * - more comments, history, etc.
222 * - mmc_init: configure the PSA if not done
223 * - mmc_init: correct default value of level threshold for PCMCIA
224 * - mmc_init: 2.00 detection better code for 2.00 initialization
225 * - better info at startup
226 * - IRQ setting (note: this setting is permanent)
227 * - watchdog: change strategy (and solve module removal problems)
228 * - add wireless extensions (ioctl and get_wireless_stats)
229 * get/set nwid/frequency on fly, info for /proc/net/wireless
230 * - more wireless extensions: SETSPY and GETSPY
231 * - make wireless extensions optional
232 * - private ioctl to set/get quality and level threshold, histogram
233 * - remove /proc/net/wavelan
234 * - suppress useless stuff from lp (net_local)
235 * - kernel 2.1 support (copy_to/from_user instead of memcpy_to/fromfs)
236 * - add message level (debug stuff in /var/adm/debug and errors not
237 * displayed at console and still in /var/adm/messages)
238 * - multi device support
239 * - start fixing the probe (init code)
240 * - more inlines
241 * - man page
242 * - many other minor details and cleanups
243 *
244 * Changes made in second pre-release:
245 * -----------------------------------
246 * - clean up init code (probe and module init)
247 * - better multiple device support (module)
248 * - name assignment (module)
249 *
250 * Changes made in third pre-release:
251 * ----------------------------------
252 * - be more conservative on timers
253 * - preliminary support for multicast (I still lack some details)
254 *
255 * Changes made in fourth pre-release:
256 * -----------------------------------
257 * - multicast (revisited and finished)
258 * - avoid reset in set_multicast_list (a really big hack)
259 * if somebody could apply this code for other i82586 based drivers
260 * - share onboard memory 75% RU and 25% CU (instead of 50/50)
261 *
262 * Changes made for release in 2.1.15:
263 * -----------------------------------
264 * - change the detection code for multi manufacturer code support
265 *
266 * Changes made for release in 2.1.17:
267 * -----------------------------------
268 * - update to wireless extensions changes
269 * - silly bug in card initial configuration (psa_conf_status)
270 *
271 * Changes made for release in 2.1.27 & 2.0.30:
272 * --------------------------------------------
273 * - small bug in debug code (probably not the last one...)
274 * - remove extern keyword for wavelan_probe()
275 * - level threshold is now a standard wireless extension (version 4 !)
276 * - modules parameters types (new module interface)
277 *
278 * Changes made for release in 2.1.36:
279 * -----------------------------------
280 * - byte count stats (courtesy of David Hinds)
281 * - remove dev_tint stuff (courtesy of David Hinds)
282 * - encryption setting from Brent Elphick (thanks a lot!)
283 * - 'ioaddr' to 'u_long' for the Alpha (thanks to Stanislav Sinyagin)
284 *
285 * Other changes (not by me) :
286 * -------------------------
287 * - Spelling and gramar "rectification".
288 *
289 * Changes made for release in 2.0.37 & 2.2.2 :
290 * ------------------------------------------
291 * - Correct status in /proc/net/wireless
292 * - Set PSA CRC to make PtP diagnostic tool happy (Bob Gray)
293 * - Module init code don't fail if we found at least one card in
294 * the address list (Karlis Peisenieks)
295 * - Missing parenthesis (Christopher Peterson)
296 * - Correct i82586 configuration parameters
297 * - Encryption initialisation bug (Robert McCormack)
298 * - New mac addresses detected in the probe
299 * - Increase watchdog for busy environments
300 *
301 * Changes made for release in 2.0.38 & 2.2.7 :
302 * ------------------------------------------
303 * - Correct the reception logic to better report errors and avoid
304 * sending bogus packet up the stack
305 * - Delay RU config to avoid corrupting first received packet
306 * - Change config completion code (to actually check something)
307 * - Avoid reading out of bound in skbuf to transmit
308 * - Rectify a lot of (useless) debugging code
309 * - Change the way to `#ifdef SET_PSA_CRC'
310 *
311 * Changes made for release in 2.2.11 & 2.3.13 :
312 * -------------------------------------------
313 * - Change e-mail and web page addresses
314 * - Watchdog timer is now correctly expressed in HZ, not in jiffies
315 * - Add channel number to the list of frequencies in range
316 * - Add the (short) list of bit-rates in range
317 * - Developp a new sensitivity... (sens.value & sens.fixed)
318 *
319 * Changes made for release in 2.2.14 & 2.3.23 :
320 * -------------------------------------------
321 * - Fix check for root permission (break instead of exit)
322 * - New nwid & encoding setting (Wireless Extension 9)
323 *
324 * Changes made for release in 2.3.49 :
325 * ----------------------------------
326 * - Indentation reformating (Alan)
327 * - Update to new network API (softnet - 2.3.43) :
328 * o replace dev->tbusy (Alan)
329 * o replace dev->tstart (Alan)
330 * o remove dev->interrupt (Alan)
331 * o add SMP locking via spinlock in splxx (me)
332 * o add spinlock in interrupt handler (me)
333 * o use kernel watchdog instead of ours (me)
334 * o increase watchdog timeout (kernel is more sensitive) (me)
335 * o verify that all the changes make sense and work (me)
336 * - Fixup a potential gotcha when reconfiguring and thighten a bit
337 * the interactions with Tx queue.
338 *
339 * Changes made for release in 2.4.0 :
340 * ---------------------------------
341 * - Fix spinlock stupid bugs that I left in. The driver is now SMP
342 * compliant and doesn't lockup at startup.
343 *
344 * Changes made for release in 2.5.2 :
345 * ---------------------------------
346 * - Use new driver API for Wireless Extensions :
347 * o got rid of wavelan_ioctl()
348 * o use a bunch of iw_handler instead
349 *
350 * Changes made for release in 2.5.35 :
351 * ----------------------------------
352 * - Set dev->trans_start to avoid filling the logs
353 * - Handle better spurious/bogus interrupt
354 * - Avoid deadlocks in mmc_out()/mmc_in()
355 *
356 * Wishes & dreams:
357 * ----------------
358 * - roaming (see Pcmcia driver)
359 */
360
361/***************************** INCLUDES *****************************/
362
363#include <linux/module.h>
364
365#include <linux/kernel.h>
366#include <linux/sched.h>
367#include <linux/types.h>
368#include <linux/fcntl.h>
369#include <linux/interrupt.h>
370#include <linux/stat.h>
371#include <linux/ptrace.h>
372#include <linux/ioport.h>
373#include <linux/in.h>
374#include <linux/string.h>
375#include <linux/delay.h>
376#include <linux/bitops.h>
377#include <asm/system.h>
378#include <asm/io.h>
379#include <asm/dma.h>
380#include <asm/uaccess.h>
381#include <linux/errno.h>
382#include <linux/netdevice.h>
383#include <linux/etherdevice.h>
384#include <linux/skbuff.h>
385#include <linux/slab.h>
386#include <linux/timer.h>
387#include <linux/init.h>
388
389#include <linux/wireless.h> /* Wireless extensions */
390#include <net/iw_handler.h> /* Wireless handlers */
391
392/* WaveLAN declarations */
393#include "i82586.h"
394#include "wavelan.h"
395
396/************************** DRIVER OPTIONS **************************/
397/*
398 * `#define' or `#undef' the following constant to change the behaviour
399 * of the driver...
400 */
401#undef SET_PSA_CRC /* Calculate and set the CRC on PSA (slower) */
402#define USE_PSA_CONFIG /* Use info from the PSA. */
403#undef EEPROM_IS_PROTECTED /* doesn't seem to be necessary */
404#define MULTICAST_AVOID /* Avoid extra multicast (I'm sceptical). */
405#undef SET_MAC_ADDRESS /* Experimental */
406
407/* Warning: this stuff will slow down the driver. */
408#define WIRELESS_SPY /* Enable spying addresses. */
409#undef HISTOGRAM /* Enable histogram of signal level. */
410
411/****************************** DEBUG ******************************/
412
413#undef DEBUG_MODULE_TRACE /* module insertion/removal */
414#undef DEBUG_CALLBACK_TRACE /* calls made by Linux */
415#undef DEBUG_INTERRUPT_TRACE /* calls to handler */
416#undef DEBUG_INTERRUPT_INFO /* type of interrupt and so on */
417#define DEBUG_INTERRUPT_ERROR /* problems */
418#undef DEBUG_CONFIG_TRACE /* Trace the config functions. */
419#undef DEBUG_CONFIG_INFO /* what's going on */
420#define DEBUG_CONFIG_ERROR /* errors on configuration */
421#undef DEBUG_TX_TRACE /* transmission calls */
422#undef DEBUG_TX_INFO /* header of the transmitted packet */
423#undef DEBUG_TX_FAIL /* Normal failure conditions */
424#define DEBUG_TX_ERROR /* Unexpected conditions */
425#undef DEBUG_RX_TRACE /* transmission calls */
426#undef DEBUG_RX_INFO /* header of the received packet */
427#undef DEBUG_RX_FAIL /* Normal failure conditions */
428#define DEBUG_RX_ERROR /* Unexpected conditions */
429
430#undef DEBUG_PACKET_DUMP /* Dump packet on the screen if defined to 32. */
431#undef DEBUG_IOCTL_TRACE /* misc. call by Linux */
432#undef DEBUG_IOCTL_INFO /* various debugging info */
433#define DEBUG_IOCTL_ERROR /* what's going wrong */
434#define DEBUG_BASIC_SHOW /* Show basic startup info. */
435#undef DEBUG_VERSION_SHOW /* Print version info. */
436#undef DEBUG_PSA_SHOW /* Dump PSA to screen. */
437#undef DEBUG_MMC_SHOW /* Dump mmc to screen. */
438#undef DEBUG_SHOW_UNUSED /* Show unused fields too. */
439#undef DEBUG_I82586_SHOW /* Show i82586 status. */
440#undef DEBUG_DEVICE_SHOW /* Show device parameters. */
441
442/************************ CONSTANTS & MACROS ************************/
443
444#ifdef DEBUG_VERSION_SHOW
445static const char *version = "wavelan.c : v24 (SMP + wireless extensions) 11/12/01\n";
446#endif
447
448/* Watchdog temporisation */
449#define WATCHDOG_JIFFIES (512*HZ/100)
450
451/* ------------------------ PRIVATE IOCTL ------------------------ */
452
453#define SIOCSIPQTHR SIOCIWFIRSTPRIV /* Set quality threshold */
454#define SIOCGIPQTHR SIOCIWFIRSTPRIV + 1 /* Get quality threshold */
455
456#define SIOCSIPHISTO SIOCIWFIRSTPRIV + 2 /* Set histogram ranges */
457#define SIOCGIPHISTO SIOCIWFIRSTPRIV + 3 /* Get histogram values */
458
459/****************************** TYPES ******************************/
460
461/* Shortcuts */
462typedef struct iw_statistics iw_stats;
463typedef struct iw_quality iw_qual;
464typedef struct iw_freq iw_freq;typedef struct net_local net_local;
465typedef struct timer_list timer_list;
466
467/* Basic types */
468typedef u_char mac_addr[WAVELAN_ADDR_SIZE]; /* Hardware address */
469
470/*
471 * Static specific data for the interface.
472 *
473 * For each network interface, Linux keeps data in two structures: "device"
474 * keeps the generic data (same format for everybody) and "net_local" keeps
475 * additional specific data.
476 */
477struct net_local
478{
479 net_local * next; /* linked list of the devices */
480 struct net_device * dev; /* reverse link */
481 spinlock_t spinlock; /* Serialize access to the hardware (SMP) */
482 int nresets; /* number of hardware resets */
483 u_char reconfig_82586; /* We need to reconfigure the controller. */
484 u_char promiscuous; /* promiscuous mode */
485 int mc_count; /* number of multicast addresses */
486 u_short hacr; /* current host interface state */
487
488 int tx_n_in_use;
489 u_short rx_head;
490 u_short rx_last;
491 u_short tx_first_free;
492 u_short tx_first_in_use;
493
494 iw_stats wstats; /* Wireless-specific statistics */
495
496 struct iw_spy_data spy_data;
497 struct iw_public_data wireless_data;
498
499#ifdef HISTOGRAM
500 int his_number; /* number of intervals */
501 u_char his_range[16]; /* boundaries of interval ]n-1; n] */
502 u_long his_sum[16]; /* sum in interval */
503#endif /* HISTOGRAM */
504};
505
506/**************************** PROTOTYPES ****************************/
507
508/* ----------------------- MISC. SUBROUTINES ------------------------ */
509static u_char
510 wv_irq_to_psa(int);
511static int
512 wv_psa_to_irq(u_char);
513/* ------------------- HOST ADAPTER SUBROUTINES ------------------- */
514static inline u_short /* data */
515 hasr_read(u_long); /* Read the host interface: base address */
516static inline void
517 hacr_write(u_long, /* Write to host interface: base address */
518 u_short), /* data */
519 hacr_write_slow(u_long,
520 u_short),
521 set_chan_attn(u_long, /* ioaddr */
522 u_short), /* hacr */
523 wv_hacr_reset(u_long), /* ioaddr */
524 wv_16_off(u_long, /* ioaddr */
525 u_short), /* hacr */
526 wv_16_on(u_long, /* ioaddr */
527 u_short), /* hacr */
528 wv_ints_off(struct net_device *),
529 wv_ints_on(struct net_device *);
530/* ----------------- MODEM MANAGEMENT SUBROUTINES ----------------- */
531static void
532 psa_read(u_long, /* Read the Parameter Storage Area. */
533 u_short, /* hacr */
534 int, /* offset in PSA */
535 u_char *, /* buffer to fill */
536 int), /* size to read */
537 psa_write(u_long, /* Write to the PSA. */
538 u_short, /* hacr */
539 int, /* offset in PSA */
540 u_char *, /* buffer in memory */
541 int); /* length of buffer */
542static inline void
543 mmc_out(u_long, /* Write 1 byte to the Modem Manag Control. */
544 u_short,
545 u_char),
546 mmc_write(u_long, /* Write n bytes to the MMC. */
547 u_char,
548 u_char *,
549 int);
550static inline u_char /* Read 1 byte from the MMC. */
551 mmc_in(u_long,
552 u_short);
553static inline void
554 mmc_read(u_long, /* Read n bytes from the MMC. */
555 u_char,
556 u_char *,
557 int),
558 fee_wait(u_long, /* Wait for frequency EEPROM: base address */
559 int, /* base delay to wait for */
560 int); /* time to wait */
561static void
562 fee_read(u_long, /* Read the frequency EEPROM: base address */
563 u_short, /* destination offset */
564 u_short *, /* data buffer */
565 int); /* number of registers */
566/* ---------------------- I82586 SUBROUTINES ----------------------- */
567static /*inline*/ void
568 obram_read(u_long, /* ioaddr */
569 u_short, /* o */
570 u_char *, /* b */
571 int); /* n */
572static inline void
573 obram_write(u_long, /* ioaddr */
574 u_short, /* o */
575 u_char *, /* b */
576 int); /* n */
577static void
578 wv_ack(struct net_device *);
579static inline int
580 wv_synchronous_cmd(struct net_device *,
581 const char *),
582 wv_config_complete(struct net_device *,
583 u_long,
584 net_local *);
585static int
586 wv_complete(struct net_device *,
587 u_long,
588 net_local *);
589static inline void
590 wv_82586_reconfig(struct net_device *);
591/* ------------------- DEBUG & INFO SUBROUTINES ------------------- */
592#ifdef DEBUG_I82586_SHOW
593static void
594 wv_scb_show(unsigned short);
595#endif
596static inline void
597 wv_init_info(struct net_device *); /* display startup info */
598/* ------------------- IOCTL, STATS & RECONFIG ------------------- */
599static iw_stats *
600 wavelan_get_wireless_stats(struct net_device *);
601static void
602 wavelan_set_multicast_list(struct net_device *);
603/* ----------------------- PACKET RECEPTION ----------------------- */
604static inline void
605 wv_packet_read(struct net_device *, /* Read a packet from a frame. */
606 u_short,
607 int),
608 wv_receive(struct net_device *); /* Read all packets waiting. */
609/* --------------------- PACKET TRANSMISSION --------------------- */
610static inline int
611 wv_packet_write(struct net_device *, /* Write a packet to the Tx buffer. */
612 void *,
613 short);
614static netdev_tx_t
615 wavelan_packet_xmit(struct sk_buff *, /* Send a packet. */
616 struct net_device *);
617/* -------------------- HARDWARE CONFIGURATION -------------------- */
618static inline int
619 wv_mmc_init(struct net_device *), /* Initialize the modem. */
620 wv_ru_start(struct net_device *), /* Start the i82586 receiver unit. */
621 wv_cu_start(struct net_device *), /* Start the i82586 command unit. */
622 wv_82586_start(struct net_device *); /* Start the i82586. */
623static void
624 wv_82586_config(struct net_device *); /* Configure the i82586. */
625static inline void
626 wv_82586_stop(struct net_device *);
627static int
628 wv_hw_reset(struct net_device *), /* Reset the WaveLAN hardware. */
629 wv_check_ioaddr(u_long, /* ioaddr */
630 u_char *); /* mac address (read) */
631/* ---------------------- INTERRUPT HANDLING ---------------------- */
632static irqreturn_t
633 wavelan_interrupt(int, /* interrupt handler */
634 void *);
635static void
636 wavelan_watchdog(struct net_device *); /* transmission watchdog */
637/* ------------------- CONFIGURATION CALLBACKS ------------------- */
638static int
639 wavelan_open(struct net_device *), /* Open the device. */
640 wavelan_close(struct net_device *), /* Close the device. */
641 wavelan_config(struct net_device *, unsigned short);/* Configure one device. */
642extern struct net_device *wavelan_probe(int unit); /* See Space.c. */
643
644/**************************** VARIABLES ****************************/
645
646/*
647 * This is the root of the linked list of WaveLAN drivers
648 * It is use to verify that we don't reuse the same base address
649 * for two different drivers and to clean up when removing the module.
650 */
651static net_local * wavelan_list = (net_local *) NULL;
652
653/*
654 * This table is used to translate the PSA value to IRQ number
655 * and vice versa.
656 */
657static u_char irqvals[] =
658{
659 0, 0, 0, 0x01,
660 0x02, 0x04, 0, 0x08,
661 0, 0, 0x10, 0x20,
662 0x40, 0, 0, 0x80,
663};
664
665/*
666 * Table of the available I/O addresses (base addresses) for WaveLAN
667 */
668static unsigned short iobase[] =
669{
670#if 0
671 /* Leave out 0x3C0 for now -- seems to clash with some video
672 * controllers.
673 * Leave out the others too -- we will always use 0x390 and leave
674 * 0x300 for the Ethernet device.
675 * Jean II: 0x3E0 is fine as well.
676 */
677 0x300, 0x390, 0x3E0, 0x3C0
678#endif /* 0 */
679 0x390, 0x3E0
680};
681
682#ifdef MODULE
683/* Parameters set by insmod */
684static int io[4];
685static int irq[4];
686static char *name[4];
687module_param_array(io, int, NULL, 0);
688module_param_array(irq, int, NULL, 0);
689module_param_array(name, charp, NULL, 0);
690
691MODULE_PARM_DESC(io, "WaveLAN I/O base address(es),required");
692MODULE_PARM_DESC(irq, "WaveLAN IRQ number(s)");
693MODULE_PARM_DESC(name, "WaveLAN interface neme(s)");
694#endif /* MODULE */
695
696#endif /* WAVELAN_P_H */
diff --git a/drivers/net/wireless/wavelan_cs.c b/drivers/net/wireless/wavelan_cs.c
deleted file mode 100644
index 431a20ec6db6..000000000000
--- a/drivers/net/wireless/wavelan_cs.c
+++ /dev/null
@@ -1,4635 +0,0 @@
1/*
2 * Wavelan Pcmcia driver
3 *
4 * Jean II - HPLB '96
5 *
6 * Reorganisation and extension of the driver.
7 * Original copyright follow. See wavelan_cs.p.h for details.
8 *
9 * This code is derived from Anthony D. Joseph's code and all the changes here
10 * are also under the original copyright below.
11 *
12 * This code supports version 2.00 of WaveLAN/PCMCIA cards (2.4GHz), and
13 * can work on Linux 2.0.36 with support of David Hinds' PCMCIA Card Services
14 *
15 * Joe Finney (joe@comp.lancs.ac.uk) at Lancaster University in UK added
16 * critical code in the routine to initialize the Modem Management Controller.
17 *
18 * Thanks to Alan Cox and Bruce Janson for their advice.
19 *
20 * -- Yunzhou Li (scip4166@nus.sg)
21 *
22#ifdef WAVELAN_ROAMING
23 * Roaming support added 07/22/98 by Justin Seger (jseger@media.mit.edu)
24 * based on patch by Joe Finney from Lancaster University.
25#endif
26 *
27 * Lucent (formerly AT&T GIS, formerly NCR) WaveLAN PCMCIA card: An
28 * Ethernet-like radio transceiver controlled by an Intel 82593 coprocessor.
29 *
30 * A non-shared memory PCMCIA ethernet driver for linux
31 *
32 * ISA version modified to support PCMCIA by Anthony Joseph (adj@lcs.mit.edu)
33 *
34 *
35 * Joseph O'Sullivan & John Langford (josullvn@cs.cmu.edu & jcl@cs.cmu.edu)
36 *
37 * Apr 2 '98 made changes to bring the i82593 control/int handling in line
38 * with offical specs...
39 *
40 ****************************************************************************
41 * Copyright 1995
42 * Anthony D. Joseph
43 * Massachusetts Institute of Technology
44 *
45 * Permission to use, copy, modify, and distribute this program
46 * for any purpose and without fee is hereby granted, provided
47 * that this copyright and permission notice appear on all copies
48 * and supporting documentation, the name of M.I.T. not be used
49 * in advertising or publicity pertaining to distribution of the
50 * program without specific prior permission, and notice be given
51 * in supporting documentation that copying and distribution is
52 * by permission of M.I.T. M.I.T. makes no representations about
53 * the suitability of this software for any purpose. It is pro-
54 * vided "as is" without express or implied warranty.
55 ****************************************************************************
56 *
57 */
58
59/* Do *NOT* add other headers here, you are guaranteed to be wrong - Jean II */
60#include "wavelan_cs.p.h" /* Private header */
61
62#ifdef WAVELAN_ROAMING
63static void wl_cell_expiry(unsigned long data);
64static void wl_del_wavepoint(wavepoint_history *wavepoint, struct net_local *lp);
65static void wv_nwid_filter(unsigned char mode, net_local *lp);
66#endif /* WAVELAN_ROAMING */
67
68/************************* MISC SUBROUTINES **************************/
69/*
70 * Subroutines which won't fit in one of the following category
71 * (wavelan modem or i82593)
72 */
73
74/******************* MODEM MANAGEMENT SUBROUTINES *******************/
75/*
76 * Useful subroutines to manage the modem of the wavelan
77 */
78
79/*------------------------------------------------------------------*/
80/*
81 * Read from card's Host Adaptor Status Register.
82 */
83static inline u_char
84hasr_read(u_long base)
85{
86 return(inb(HASR(base)));
87} /* hasr_read */
88
89/*------------------------------------------------------------------*/
90/*
91 * Write to card's Host Adapter Command Register.
92 */
93static inline void
94hacr_write(u_long base,
95 u_char hacr)
96{
97 outb(hacr, HACR(base));
98} /* hacr_write */
99
100/*------------------------------------------------------------------*/
101/*
102 * Write to card's Host Adapter Command Register. Include a delay for
103 * those times when it is needed.
104 */
105static void
106hacr_write_slow(u_long base,
107 u_char hacr)
108{
109 hacr_write(base, hacr);
110 /* delay might only be needed sometimes */
111 mdelay(1);
112} /* hacr_write_slow */
113
114/*------------------------------------------------------------------*/
115/*
116 * Read the Parameter Storage Area from the WaveLAN card's memory
117 */
118static void
119psa_read(struct net_device * dev,
120 int o, /* offset in PSA */
121 u_char * b, /* buffer to fill */
122 int n) /* size to read */
123{
124 net_local *lp = netdev_priv(dev);
125 u_char __iomem *ptr = lp->mem + PSA_ADDR + (o << 1);
126
127 while(n-- > 0)
128 {
129 *b++ = readb(ptr);
130 /* Due to a lack of address decode pins, the WaveLAN PCMCIA card
131 * only supports reading even memory addresses. That means the
132 * increment here MUST be two.
133 * Because of that, we can't use memcpy_fromio()...
134 */
135 ptr += 2;
136 }
137} /* psa_read */
138
139/*------------------------------------------------------------------*/
140/*
141 * Write the Parameter Storage Area to the WaveLAN card's memory
142 */
143static void
144psa_write(struct net_device * dev,
145 int o, /* Offset in psa */
146 u_char * b, /* Buffer in memory */
147 int n) /* Length of buffer */
148{
149 net_local *lp = netdev_priv(dev);
150 u_char __iomem *ptr = lp->mem + PSA_ADDR + (o << 1);
151 int count = 0;
152 unsigned int base = dev->base_addr;
153 /* As there seem to have no flag PSA_BUSY as in the ISA model, we are
154 * oblige to verify this address to know when the PSA is ready... */
155 volatile u_char __iomem *verify = lp->mem + PSA_ADDR +
156 (psaoff(0, psa_comp_number) << 1);
157
158 /* Authorize writing to PSA */
159 hacr_write(base, HACR_PWR_STAT | HACR_ROM_WEN);
160
161 while(n-- > 0)
162 {
163 /* write to PSA */
164 writeb(*b++, ptr);
165 ptr += 2;
166
167 /* I don't have the spec, so I don't know what the correct
168 * sequence to write is. This hack seem to work for me... */
169 count = 0;
170 while((readb(verify) != PSA_COMP_PCMCIA_915) && (count++ < 100))
171 mdelay(1);
172 }
173
174 /* Put the host interface back in standard state */
175 hacr_write(base, HACR_DEFAULT);
176} /* psa_write */
177
178#ifdef SET_PSA_CRC
179/*------------------------------------------------------------------*/
180/*
181 * Calculate the PSA CRC
182 * Thanks to Valster, Nico <NVALSTER@wcnd.nl.lucent.com> for the code
183 * NOTE: By specifying a length including the CRC position the
184 * returned value should be zero. (i.e. a correct checksum in the PSA)
185 *
186 * The Windows drivers don't use the CRC, but the AP and the PtP tool
187 * depend on it.
188 */
189static u_short
190psa_crc(unsigned char * psa, /* The PSA */
191 int size) /* Number of short for CRC */
192{
193 int byte_cnt; /* Loop on the PSA */
194 u_short crc_bytes = 0; /* Data in the PSA */
195 int bit_cnt; /* Loop on the bits of the short */
196
197 for(byte_cnt = 0; byte_cnt < size; byte_cnt++ )
198 {
199 crc_bytes ^= psa[byte_cnt]; /* Its an xor */
200
201 for(bit_cnt = 1; bit_cnt < 9; bit_cnt++ )
202 {
203 if(crc_bytes & 0x0001)
204 crc_bytes = (crc_bytes >> 1) ^ 0xA001;
205 else
206 crc_bytes >>= 1 ;
207 }
208 }
209
210 return crc_bytes;
211} /* psa_crc */
212#endif /* SET_PSA_CRC */
213
214/*------------------------------------------------------------------*/
215/*
216 * update the checksum field in the Wavelan's PSA
217 */
218static void
219update_psa_checksum(struct net_device * dev)
220{
221#ifdef SET_PSA_CRC
222 psa_t psa;
223 u_short crc;
224
225 /* read the parameter storage area */
226 psa_read(dev, 0, (unsigned char *) &psa, sizeof(psa));
227
228 /* update the checksum */
229 crc = psa_crc((unsigned char *) &psa,
230 sizeof(psa) - sizeof(psa.psa_crc[0]) - sizeof(psa.psa_crc[1])
231 - sizeof(psa.psa_crc_status));
232
233 psa.psa_crc[0] = crc & 0xFF;
234 psa.psa_crc[1] = (crc & 0xFF00) >> 8;
235
236 /* Write it ! */
237 psa_write(dev, (char *)&psa.psa_crc - (char *)&psa,
238 (unsigned char *)&psa.psa_crc, 2);
239
240#ifdef DEBUG_IOCTL_INFO
241 printk (KERN_DEBUG "%s: update_psa_checksum(): crc = 0x%02x%02x\n",
242 dev->name, psa.psa_crc[0], psa.psa_crc[1]);
243
244 /* Check again (luxury !) */
245 crc = psa_crc((unsigned char *) &psa,
246 sizeof(psa) - sizeof(psa.psa_crc_status));
247
248 if(crc != 0)
249 printk(KERN_WARNING "%s: update_psa_checksum(): CRC does not agree with PSA data (even after recalculating)\n", dev->name);
250#endif /* DEBUG_IOCTL_INFO */
251#endif /* SET_PSA_CRC */
252} /* update_psa_checksum */
253
254/*------------------------------------------------------------------*/
255/*
256 * Write 1 byte to the MMC.
257 */
258static void
259mmc_out(u_long base,
260 u_short o,
261 u_char d)
262{
263 int count = 0;
264
265 /* Wait for MMC to go idle */
266 while((count++ < 100) && (inb(HASR(base)) & HASR_MMI_BUSY))
267 udelay(10);
268
269 outb((u_char)((o << 1) | MMR_MMI_WR), MMR(base));
270 outb(d, MMD(base));
271}
272
273/*------------------------------------------------------------------*/
274/*
275 * Routine to write bytes to the Modem Management Controller.
276 * We start by the end because it is the way it should be !
277 */
278static void
279mmc_write(u_long base,
280 u_char o,
281 u_char * b,
282 int n)
283{
284 o += n;
285 b += n;
286
287 while(n-- > 0 )
288 mmc_out(base, --o, *(--b));
289} /* mmc_write */
290
291/*------------------------------------------------------------------*/
292/*
293 * Read 1 byte from the MMC.
294 * Optimised version for 1 byte, avoid using memory...
295 */
296static u_char
297mmc_in(u_long base,
298 u_short o)
299{
300 int count = 0;
301
302 while((count++ < 100) && (inb(HASR(base)) & HASR_MMI_BUSY))
303 udelay(10);
304 outb(o << 1, MMR(base)); /* Set the read address */
305
306 outb(0, MMD(base)); /* Required dummy write */
307
308 while((count++ < 100) && (inb(HASR(base)) & HASR_MMI_BUSY))
309 udelay(10);
310 return (u_char) (inb(MMD(base))); /* Now do the actual read */
311}
312
313/*------------------------------------------------------------------*/
314/*
315 * Routine to read bytes from the Modem Management Controller.
316 * The implementation is complicated by a lack of address lines,
317 * which prevents decoding of the low-order bit.
318 * (code has just been moved in the above function)
319 * We start by the end because it is the way it should be !
320 */
321static void
322mmc_read(u_long base,
323 u_char o,
324 u_char * b,
325 int n)
326{
327 o += n;
328 b += n;
329
330 while(n-- > 0)
331 *(--b) = mmc_in(base, --o);
332} /* mmc_read */
333
334/*------------------------------------------------------------------*/
335/*
336 * Get the type of encryption available...
337 */
338static inline int
339mmc_encr(u_long base) /* i/o port of the card */
340{
341 int temp;
342
343 temp = mmc_in(base, mmroff(0, mmr_des_avail));
344 if((temp != MMR_DES_AVAIL_DES) && (temp != MMR_DES_AVAIL_AES))
345 return 0;
346 else
347 return temp;
348}
349
350/*------------------------------------------------------------------*/
351/*
352 * Wait for the frequency EEprom to complete a command...
353 */
354static void
355fee_wait(u_long base, /* i/o port of the card */
356 int delay, /* Base delay to wait for */
357 int number) /* Number of time to wait */
358{
359 int count = 0; /* Wait only a limited time */
360
361 while((count++ < number) &&
362 (mmc_in(base, mmroff(0, mmr_fee_status)) & MMR_FEE_STATUS_BUSY))
363 udelay(delay);
364}
365
366/*------------------------------------------------------------------*/
367/*
368 * Read bytes from the Frequency EEprom (frequency select cards).
369 */
370static void
371fee_read(u_long base, /* i/o port of the card */
372 u_short o, /* destination offset */
373 u_short * b, /* data buffer */
374 int n) /* number of registers */
375{
376 b += n; /* Position at the end of the area */
377
378 /* Write the address */
379 mmc_out(base, mmwoff(0, mmw_fee_addr), o + n - 1);
380
381 /* Loop on all buffer */
382 while(n-- > 0)
383 {
384 /* Write the read command */
385 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_READ);
386
387 /* Wait until EEprom is ready (should be quick !) */
388 fee_wait(base, 10, 100);
389
390 /* Read the value */
391 *--b = ((mmc_in(base, mmroff(0, mmr_fee_data_h)) << 8) |
392 mmc_in(base, mmroff(0, mmr_fee_data_l)));
393 }
394}
395
396
397/*------------------------------------------------------------------*/
398/*
399 * Write bytes from the Frequency EEprom (frequency select cards).
400 * This is a bit complicated, because the frequency eeprom has to
401 * be unprotected and the write enabled.
402 * Jean II
403 */
404static void
405fee_write(u_long base, /* i/o port of the card */
406 u_short o, /* destination offset */
407 u_short * b, /* data buffer */
408 int n) /* number of registers */
409{
410 b += n; /* Position at the end of the area */
411
412#ifdef EEPROM_IS_PROTECTED /* disabled */
413#ifdef DOESNT_SEEM_TO_WORK /* disabled */
414 /* Ask to read the protected register */
415 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRREAD);
416
417 fee_wait(base, 10, 100);
418
419 /* Read the protected register */
420 printk("Protected 2 : %02X-%02X\n",
421 mmc_in(base, mmroff(0, mmr_fee_data_h)),
422 mmc_in(base, mmroff(0, mmr_fee_data_l)));
423#endif /* DOESNT_SEEM_TO_WORK */
424
425 /* Enable protected register */
426 mmc_out(base, mmwoff(0, mmw_fee_addr), MMW_FEE_ADDR_EN);
427 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PREN);
428
429 fee_wait(base, 10, 100);
430
431 /* Unprotect area */
432 mmc_out(base, mmwoff(0, mmw_fee_addr), o + n);
433 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRWRITE);
434#ifdef DOESNT_SEEM_TO_WORK /* disabled */
435 /* Or use : */
436 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRCLEAR);
437#endif /* DOESNT_SEEM_TO_WORK */
438
439 fee_wait(base, 10, 100);
440#endif /* EEPROM_IS_PROTECTED */
441
442 /* Write enable */
443 mmc_out(base, mmwoff(0, mmw_fee_addr), MMW_FEE_ADDR_EN);
444 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_WREN);
445
446 fee_wait(base, 10, 100);
447
448 /* Write the EEprom address */
449 mmc_out(base, mmwoff(0, mmw_fee_addr), o + n - 1);
450
451 /* Loop on all buffer */
452 while(n-- > 0)
453 {
454 /* Write the value */
455 mmc_out(base, mmwoff(0, mmw_fee_data_h), (*--b) >> 8);
456 mmc_out(base, mmwoff(0, mmw_fee_data_l), *b & 0xFF);
457
458 /* Write the write command */
459 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_WRITE);
460
461 /* Wavelan doc says : wait at least 10 ms for EEBUSY = 0 */
462 mdelay(10);
463 fee_wait(base, 10, 100);
464 }
465
466 /* Write disable */
467 mmc_out(base, mmwoff(0, mmw_fee_addr), MMW_FEE_ADDR_DS);
468 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_WDS);
469
470 fee_wait(base, 10, 100);
471
472#ifdef EEPROM_IS_PROTECTED /* disabled */
473 /* Reprotect EEprom */
474 mmc_out(base, mmwoff(0, mmw_fee_addr), 0x00);
475 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRWRITE);
476
477 fee_wait(base, 10, 100);
478#endif /* EEPROM_IS_PROTECTED */
479}
480
481/******************* WaveLAN Roaming routines... ********************/
482
483#ifdef WAVELAN_ROAMING /* Conditional compile, see wavelan_cs.h */
484
485static unsigned char WAVELAN_BEACON_ADDRESS[] = {0x09,0x00,0x0e,0x20,0x03,0x00};
486
487static void wv_roam_init(struct net_device *dev)
488{
489 net_local *lp= netdev_priv(dev);
490
491 /* Do not remove this unless you have a good reason */
492 printk(KERN_NOTICE "%s: Warning, you have enabled roaming on"
493 " device %s !\n", dev->name, dev->name);
494 printk(KERN_NOTICE "Roaming is currently an experimental unsupported feature"
495 " of the Wavelan driver.\n");
496 printk(KERN_NOTICE "It may work, but may also make the driver behave in"
497 " erratic ways or crash.\n");
498
499 lp->wavepoint_table.head=NULL; /* Initialise WavePoint table */
500 lp->wavepoint_table.num_wavepoints=0;
501 lp->wavepoint_table.locked=0;
502 lp->curr_point=NULL; /* No default WavePoint */
503 lp->cell_search=0;
504
505 lp->cell_timer.data=(long)lp; /* Start cell expiry timer */
506 lp->cell_timer.function=wl_cell_expiry;
507 lp->cell_timer.expires=jiffies+CELL_TIMEOUT;
508 add_timer(&lp->cell_timer);
509
510 wv_nwid_filter(NWID_PROMISC,lp) ; /* Enter NWID promiscuous mode */
511 /* to build up a good WavePoint */
512 /* table... */
513 printk(KERN_DEBUG "WaveLAN: Roaming enabled on device %s\n",dev->name);
514}
515
516static void wv_roam_cleanup(struct net_device *dev)
517{
518 wavepoint_history *ptr,*old_ptr;
519 net_local *lp= netdev_priv(dev);
520
521 printk(KERN_DEBUG "WaveLAN: Roaming Disabled on device %s\n",dev->name);
522
523 /* Fixme : maybe we should check that the timer exist before deleting it */
524 del_timer(&lp->cell_timer); /* Remove cell expiry timer */
525 ptr=lp->wavepoint_table.head; /* Clear device's WavePoint table */
526 while(ptr!=NULL)
527 {
528 old_ptr=ptr;
529 ptr=ptr->next;
530 wl_del_wavepoint(old_ptr,lp);
531 }
532}
533
534/* Enable/Disable NWID promiscuous mode on a given device */
535static void wv_nwid_filter(unsigned char mode, net_local *lp)
536{
537 mm_t m;
538 unsigned long flags;
539
540#ifdef WAVELAN_ROAMING_DEBUG
541 printk(KERN_DEBUG "WaveLAN: NWID promisc %s, device %s\n",(mode==NWID_PROMISC) ? "on" : "off", lp->dev->name);
542#endif
543
544 /* Disable interrupts & save flags */
545 spin_lock_irqsave(&lp->spinlock, flags);
546
547 m.w.mmw_loopt_sel = (mode==NWID_PROMISC) ? MMW_LOOPT_SEL_DIS_NWID : 0x00;
548 mmc_write(lp->dev->base_addr, (char *)&m.w.mmw_loopt_sel - (char *)&m, (unsigned char *)&m.w.mmw_loopt_sel, 1);
549
550 if(mode==NWID_PROMISC)
551 lp->cell_search=1;
552 else
553 lp->cell_search=0;
554
555 /* ReEnable interrupts & restore flags */
556 spin_unlock_irqrestore(&lp->spinlock, flags);
557}
558
559/* Find a record in the WavePoint table matching a given NWID */
560static wavepoint_history *wl_roam_check(unsigned short nwid, net_local *lp)
561{
562 wavepoint_history *ptr=lp->wavepoint_table.head;
563
564 while(ptr!=NULL){
565 if(ptr->nwid==nwid)
566 return ptr;
567 ptr=ptr->next;
568 }
569 return NULL;
570}
571
572/* Create a new wavepoint table entry */
573static wavepoint_history *wl_new_wavepoint(unsigned short nwid, unsigned char seq, net_local* lp)
574{
575 wavepoint_history *new_wavepoint;
576
577#ifdef WAVELAN_ROAMING_DEBUG
578 printk(KERN_DEBUG "WaveLAN: New Wavepoint, NWID:%.4X\n",nwid);
579#endif
580
581 if(lp->wavepoint_table.num_wavepoints==MAX_WAVEPOINTS)
582 return NULL;
583
584 new_wavepoint = kmalloc(sizeof(wavepoint_history),GFP_ATOMIC);
585 if(new_wavepoint==NULL)
586 return NULL;
587
588 new_wavepoint->nwid=nwid; /* New WavePoints NWID */
589 new_wavepoint->average_fast=0; /* Running Averages..*/
590 new_wavepoint->average_slow=0;
591 new_wavepoint->qualptr=0; /* Start of ringbuffer */
592 new_wavepoint->last_seq=seq-1; /* Last sequence no.seen */
593 memset(new_wavepoint->sigqual,0,WAVEPOINT_HISTORY);/* Empty ringbuffer */
594
595 new_wavepoint->next=lp->wavepoint_table.head;/* Add to wavepoint table */
596 new_wavepoint->prev=NULL;
597
598 if(lp->wavepoint_table.head!=NULL)
599 lp->wavepoint_table.head->prev=new_wavepoint;
600
601 lp->wavepoint_table.head=new_wavepoint;
602
603 lp->wavepoint_table.num_wavepoints++; /* no. of visible wavepoints */
604
605 return new_wavepoint;
606}
607
608/* Remove a wavepoint entry from WavePoint table */
609static void wl_del_wavepoint(wavepoint_history *wavepoint, struct net_local *lp)
610{
611 if(wavepoint==NULL)
612 return;
613
614 if(lp->curr_point==wavepoint)
615 lp->curr_point=NULL;
616
617 if(wavepoint->prev!=NULL)
618 wavepoint->prev->next=wavepoint->next;
619
620 if(wavepoint->next!=NULL)
621 wavepoint->next->prev=wavepoint->prev;
622
623 if(lp->wavepoint_table.head==wavepoint)
624 lp->wavepoint_table.head=wavepoint->next;
625
626 lp->wavepoint_table.num_wavepoints--;
627 kfree(wavepoint);
628}
629
630/* Timer callback function - checks WavePoint table for stale entries */
631static void wl_cell_expiry(unsigned long data)
632{
633 net_local *lp=(net_local *)data;
634 wavepoint_history *wavepoint=lp->wavepoint_table.head,*old_point;
635
636#if WAVELAN_ROAMING_DEBUG > 1
637 printk(KERN_DEBUG "WaveLAN: Wavepoint timeout, dev %s\n",lp->dev->name);
638#endif
639
640 if(lp->wavepoint_table.locked)
641 {
642#if WAVELAN_ROAMING_DEBUG > 1
643 printk(KERN_DEBUG "WaveLAN: Wavepoint table locked...\n");
644#endif
645
646 lp->cell_timer.expires=jiffies+1; /* If table in use, come back later */
647 add_timer(&lp->cell_timer);
648 return;
649 }
650
651 while(wavepoint!=NULL)
652 {
653 if(time_after(jiffies, wavepoint->last_seen + CELL_TIMEOUT))
654 {
655#ifdef WAVELAN_ROAMING_DEBUG
656 printk(KERN_DEBUG "WaveLAN: Bye bye %.4X\n",wavepoint->nwid);
657#endif
658
659 old_point=wavepoint;
660 wavepoint=wavepoint->next;
661 wl_del_wavepoint(old_point,lp);
662 }
663 else
664 wavepoint=wavepoint->next;
665 }
666 lp->cell_timer.expires=jiffies+CELL_TIMEOUT;
667 add_timer(&lp->cell_timer);
668}
669
670/* Update SNR history of a wavepoint */
671static void wl_update_history(wavepoint_history *wavepoint, unsigned char sigqual, unsigned char seq)
672{
673 int i=0,num_missed=0,ptr=0;
674 int average_fast=0,average_slow=0;
675
676 num_missed=(seq-wavepoint->last_seq)%WAVEPOINT_HISTORY;/* Have we missed
677 any beacons? */
678 if(num_missed)
679 for(i=0;i<num_missed;i++)
680 {
681 wavepoint->sigqual[wavepoint->qualptr++]=0; /* If so, enter them as 0's */
682 wavepoint->qualptr %=WAVEPOINT_HISTORY; /* in the ringbuffer. */
683 }
684 wavepoint->last_seen=jiffies; /* Add beacon to history */
685 wavepoint->last_seq=seq;
686 wavepoint->sigqual[wavepoint->qualptr++]=sigqual;
687 wavepoint->qualptr %=WAVEPOINT_HISTORY;
688 ptr=(wavepoint->qualptr-WAVEPOINT_FAST_HISTORY+WAVEPOINT_HISTORY)%WAVEPOINT_HISTORY;
689
690 for(i=0;i<WAVEPOINT_FAST_HISTORY;i++) /* Update running averages */
691 {
692 average_fast+=wavepoint->sigqual[ptr++];
693 ptr %=WAVEPOINT_HISTORY;
694 }
695
696 average_slow=average_fast;
697 for(i=WAVEPOINT_FAST_HISTORY;i<WAVEPOINT_HISTORY;i++)
698 {
699 average_slow+=wavepoint->sigqual[ptr++];
700 ptr %=WAVEPOINT_HISTORY;
701 }
702
703 wavepoint->average_fast=average_fast/WAVEPOINT_FAST_HISTORY;
704 wavepoint->average_slow=average_slow/WAVEPOINT_HISTORY;
705}
706
707/* Perform a handover to a new WavePoint */
708static void wv_roam_handover(wavepoint_history *wavepoint, net_local *lp)
709{
710 unsigned int base = lp->dev->base_addr;
711 mm_t m;
712 unsigned long flags;
713
714 if(wavepoint==lp->curr_point) /* Sanity check... */
715 {
716 wv_nwid_filter(!NWID_PROMISC,lp);
717 return;
718 }
719
720#ifdef WAVELAN_ROAMING_DEBUG
721 printk(KERN_DEBUG "WaveLAN: Doing handover to %.4X, dev %s\n",wavepoint->nwid,lp->dev->name);
722#endif
723
724 /* Disable interrupts & save flags */
725 spin_lock_irqsave(&lp->spinlock, flags);
726
727 m.w.mmw_netw_id_l = wavepoint->nwid & 0xFF;
728 m.w.mmw_netw_id_h = (wavepoint->nwid & 0xFF00) >> 8;
729
730 mmc_write(base, (char *)&m.w.mmw_netw_id_l - (char *)&m, (unsigned char *)&m.w.mmw_netw_id_l, 2);
731
732 /* ReEnable interrupts & restore flags */
733 spin_unlock_irqrestore(&lp->spinlock, flags);
734
735 wv_nwid_filter(!NWID_PROMISC,lp);
736 lp->curr_point=wavepoint;
737}
738
739/* Called when a WavePoint beacon is received */
740static void wl_roam_gather(struct net_device * dev,
741 u_char * hdr, /* Beacon header */
742 u_char * stats) /* SNR, Signal quality
743 of packet */
744{
745 wavepoint_beacon *beacon= (wavepoint_beacon *)hdr; /* Rcvd. Beacon */
746 unsigned short nwid=ntohs(beacon->nwid);
747 unsigned short sigqual=stats[2] & MMR_SGNL_QUAL; /* SNR of beacon */
748 wavepoint_history *wavepoint=NULL; /* WavePoint table entry */
749 net_local *lp = netdev_priv(dev); /* Device info */
750
751#ifdef I_NEED_THIS_FEATURE
752 /* Some people don't need this, some other may need it */
753 nwid=nwid^ntohs(beacon->domain_id);
754#endif
755
756#if WAVELAN_ROAMING_DEBUG > 1
757 printk(KERN_DEBUG "WaveLAN: beacon, dev %s:\n",dev->name);
758 printk(KERN_DEBUG "Domain: %.4X NWID: %.4X SigQual=%d\n",ntohs(beacon->domain_id),nwid,sigqual);
759#endif
760
761 lp->wavepoint_table.locked=1; /* <Mutex> */
762
763 wavepoint=wl_roam_check(nwid,lp); /* Find WavePoint table entry */
764 if(wavepoint==NULL) /* If no entry, Create a new one... */
765 {
766 wavepoint=wl_new_wavepoint(nwid,beacon->seq,lp);
767 if(wavepoint==NULL)
768 goto out;
769 }
770 if(lp->curr_point==NULL) /* If this is the only WavePoint, */
771 wv_roam_handover(wavepoint, lp); /* Jump on it! */
772
773 wl_update_history(wavepoint, sigqual, beacon->seq); /* Update SNR history
774 stats. */
775
776 if(lp->curr_point->average_slow < SEARCH_THRESH_LOW) /* If our current */
777 if(!lp->cell_search) /* WavePoint is getting faint, */
778 wv_nwid_filter(NWID_PROMISC,lp); /* start looking for a new one */
779
780 if(wavepoint->average_slow >
781 lp->curr_point->average_slow + WAVELAN_ROAMING_DELTA)
782 wv_roam_handover(wavepoint, lp); /* Handover to a better WavePoint */
783
784 if(lp->curr_point->average_slow > SEARCH_THRESH_HIGH) /* If our SNR is */
785 if(lp->cell_search) /* getting better, drop out of cell search mode */
786 wv_nwid_filter(!NWID_PROMISC,lp);
787
788out:
789 lp->wavepoint_table.locked=0; /* </MUTEX> :-) */
790}
791
792/* Test this MAC frame a WavePoint beacon */
793static inline int WAVELAN_BEACON(unsigned char *data)
794{
795 wavepoint_beacon *beacon= (wavepoint_beacon *)data;
796 static const wavepoint_beacon beacon_template={0xaa,0xaa,0x03,0x08,0x00,0x0e,0x20,0x03,0x00};
797
798 if(memcmp(beacon,&beacon_template,9)==0)
799 return 1;
800 else
801 return 0;
802}
803#endif /* WAVELAN_ROAMING */
804
805/************************ I82593 SUBROUTINES *************************/
806/*
807 * Useful subroutines to manage the Ethernet controller
808 */
809
810/*------------------------------------------------------------------*/
811/*
812 * Routine to synchronously send a command to the i82593 chip.
813 * Should be called with interrupts disabled.
814 * (called by wv_packet_write(), wv_ru_stop(), wv_ru_start(),
815 * wv_82593_config() & wv_diag())
816 */
817static int
818wv_82593_cmd(struct net_device * dev,
819 char * str,
820 int cmd,
821 int result)
822{
823 unsigned int base = dev->base_addr;
824 int status;
825 int wait_completed;
826 long spin;
827
828 /* Spin until the chip finishes executing its current command (if any) */
829 spin = 1000;
830 do
831 {
832 /* Time calibration of the loop */
833 udelay(10);
834
835 /* Read the interrupt register */
836 outb(OP0_NOP | CR0_STATUS_3, LCCR(base));
837 status = inb(LCSR(base));
838 }
839 while(((status & SR3_EXEC_STATE_MASK) != SR3_EXEC_IDLE) && (spin-- > 0));
840
841 /* If the interrupt hasn't been posted */
842 if (spin < 0) {
843#ifdef DEBUG_INTERRUPT_ERROR
844 printk(KERN_INFO "wv_82593_cmd: %s timeout (previous command), status 0x%02x\n",
845 str, status);
846#endif
847 return(FALSE);
848 }
849
850 /* Issue the command to the controller */
851 outb(cmd, LCCR(base));
852
853 /* If we don't have to check the result of the command
854 * Note : this mean that the irq handler will deal with that */
855 if(result == SR0_NO_RESULT)
856 return(TRUE);
857
858 /* We are waiting for command completion */
859 wait_completed = TRUE;
860
861 /* Busy wait while the LAN controller executes the command. */
862 spin = 1000;
863 do
864 {
865 /* Time calibration of the loop */
866 udelay(10);
867
868 /* Read the interrupt register */
869 outb(CR0_STATUS_0 | OP0_NOP, LCCR(base));
870 status = inb(LCSR(base));
871
872 /* Check if there was an interrupt posted */
873 if((status & SR0_INTERRUPT))
874 {
875 /* Acknowledge the interrupt */
876 outb(CR0_INT_ACK | OP0_NOP, LCCR(base));
877
878 /* Check if interrupt is a command completion */
879 if(((status & SR0_BOTH_RX_TX) != SR0_BOTH_RX_TX) &&
880 ((status & SR0_BOTH_RX_TX) != 0x0) &&
881 !(status & SR0_RECEPTION))
882 {
883 /* Signal command completion */
884 wait_completed = FALSE;
885 }
886 else
887 {
888 /* Note : Rx interrupts will be handled later, because we can
889 * handle multiple Rx packets at once */
890#ifdef DEBUG_INTERRUPT_INFO
891 printk(KERN_INFO "wv_82593_cmd: not our interrupt\n");
892#endif
893 }
894 }
895 }
896 while(wait_completed && (spin-- > 0));
897
898 /* If the interrupt hasn't be posted */
899 if(wait_completed)
900 {
901#ifdef DEBUG_INTERRUPT_ERROR
902 printk(KERN_INFO "wv_82593_cmd: %s timeout, status 0x%02x\n",
903 str, status);
904#endif
905 return(FALSE);
906 }
907
908 /* Check the return code returned by the card (see above) against
909 * the expected return code provided by the caller */
910 if((status & SR0_EVENT_MASK) != result)
911 {
912#ifdef DEBUG_INTERRUPT_ERROR
913 printk(KERN_INFO "wv_82593_cmd: %s failed, status = 0x%x\n",
914 str, status);
915#endif
916 return(FALSE);
917 }
918
919 return(TRUE);
920} /* wv_82593_cmd */
921
922/*------------------------------------------------------------------*/
923/*
924 * This routine does a 593 op-code number 7, and obtains the diagnose
925 * status for the WaveLAN.
926 */
927static inline int
928wv_diag(struct net_device * dev)
929{
930 return(wv_82593_cmd(dev, "wv_diag(): diagnose",
931 OP0_DIAGNOSE, SR0_DIAGNOSE_PASSED));
932} /* wv_diag */
933
934/*------------------------------------------------------------------*/
935/*
936 * Routine to read len bytes from the i82593's ring buffer, starting at
937 * chip address addr. The results read from the chip are stored in buf.
938 * The return value is the address to use for next the call.
939 */
940static int
941read_ringbuf(struct net_device * dev,
942 int addr,
943 char * buf,
944 int len)
945{
946 unsigned int base = dev->base_addr;
947 int ring_ptr = addr;
948 int chunk_len;
949 char * buf_ptr = buf;
950
951 /* Get all the buffer */
952 while(len > 0)
953 {
954 /* Position the Program I/O Register at the ring buffer pointer */
955 outb(ring_ptr & 0xff, PIORL(base));
956 outb(((ring_ptr >> 8) & PIORH_MASK), PIORH(base));
957
958 /* First, determine how much we can read without wrapping around the
959 ring buffer */
960 if((addr + len) < (RX_BASE + RX_SIZE))
961 chunk_len = len;
962 else
963 chunk_len = RX_BASE + RX_SIZE - addr;
964 insb(PIOP(base), buf_ptr, chunk_len);
965 buf_ptr += chunk_len;
966 len -= chunk_len;
967 ring_ptr = (ring_ptr - RX_BASE + chunk_len) % RX_SIZE + RX_BASE;
968 }
969 return(ring_ptr);
970} /* read_ringbuf */
971
972/*------------------------------------------------------------------*/
973/*
974 * Reconfigure the i82593, or at least ask for it...
975 * Because wv_82593_config use the transmission buffer, we must do it
976 * when we are sure that there is no transmission, so we do it now
977 * or in wavelan_packet_xmit() (I can't find any better place,
978 * wavelan_interrupt is not an option...), so you may experience
979 * some delay sometime...
980 */
981static void
982wv_82593_reconfig(struct net_device * dev)
983{
984 net_local * lp = netdev_priv(dev);
985 struct pcmcia_device * link = lp->link;
986 unsigned long flags;
987
988 /* Arm the flag, will be cleard in wv_82593_config() */
989 lp->reconfig_82593 = TRUE;
990
991 /* Check if we can do it now ! */
992 if((link->open) && (netif_running(dev)) && !(netif_queue_stopped(dev)))
993 {
994 spin_lock_irqsave(&lp->spinlock, flags); /* Disable interrupts */
995 wv_82593_config(dev);
996 spin_unlock_irqrestore(&lp->spinlock, flags); /* Re-enable interrupts */
997 }
998 else
999 {
1000#ifdef DEBUG_IOCTL_INFO
1001 printk(KERN_DEBUG
1002 "%s: wv_82593_reconfig(): delayed (state = %lX, link = %d)\n",
1003 dev->name, dev->state, link->open);
1004#endif
1005 }
1006}
1007
1008/********************* DEBUG & INFO SUBROUTINES *********************/
1009/*
1010 * This routines are used in the code to show debug informations.
1011 * Most of the time, it dump the content of hardware structures...
1012 */
1013
1014#ifdef DEBUG_PSA_SHOW
1015/*------------------------------------------------------------------*/
1016/*
1017 * Print the formatted contents of the Parameter Storage Area.
1018 */
1019static void
1020wv_psa_show(psa_t * p)
1021{
1022 printk(KERN_DEBUG "##### wavelan psa contents: #####\n");
1023 printk(KERN_DEBUG "psa_io_base_addr_1: 0x%02X %02X %02X %02X\n",
1024 p->psa_io_base_addr_1,
1025 p->psa_io_base_addr_2,
1026 p->psa_io_base_addr_3,
1027 p->psa_io_base_addr_4);
1028 printk(KERN_DEBUG "psa_rem_boot_addr_1: 0x%02X %02X %02X\n",
1029 p->psa_rem_boot_addr_1,
1030 p->psa_rem_boot_addr_2,
1031 p->psa_rem_boot_addr_3);
1032 printk(KERN_DEBUG "psa_holi_params: 0x%02x, ", p->psa_holi_params);
1033 printk("psa_int_req_no: %d\n", p->psa_int_req_no);
1034#ifdef DEBUG_SHOW_UNUSED
1035 printk(KERN_DEBUG "psa_unused0[]: %pM\n", p->psa_unused0);
1036#endif /* DEBUG_SHOW_UNUSED */
1037 printk(KERN_DEBUG "psa_univ_mac_addr[]: %pM\n", p->psa_univ_mac_addr);
1038 printk(KERN_DEBUG "psa_local_mac_addr[]: %pM\n", p->psa_local_mac_addr);
1039 printk(KERN_DEBUG "psa_univ_local_sel: %d, ", p->psa_univ_local_sel);
1040 printk("psa_comp_number: %d, ", p->psa_comp_number);
1041 printk("psa_thr_pre_set: 0x%02x\n", p->psa_thr_pre_set);
1042 printk(KERN_DEBUG "psa_feature_select/decay_prm: 0x%02x, ",
1043 p->psa_feature_select);
1044 printk("psa_subband/decay_update_prm: %d\n", p->psa_subband);
1045 printk(KERN_DEBUG "psa_quality_thr: 0x%02x, ", p->psa_quality_thr);
1046 printk("psa_mod_delay: 0x%02x\n", p->psa_mod_delay);
1047 printk(KERN_DEBUG "psa_nwid: 0x%02x%02x, ", p->psa_nwid[0], p->psa_nwid[1]);
1048 printk("psa_nwid_select: %d\n", p->psa_nwid_select);
1049 printk(KERN_DEBUG "psa_encryption_select: %d, ", p->psa_encryption_select);
1050 printk("psa_encryption_key[]: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
1051 p->psa_encryption_key[0],
1052 p->psa_encryption_key[1],
1053 p->psa_encryption_key[2],
1054 p->psa_encryption_key[3],
1055 p->psa_encryption_key[4],
1056 p->psa_encryption_key[5],
1057 p->psa_encryption_key[6],
1058 p->psa_encryption_key[7]);
1059 printk(KERN_DEBUG "psa_databus_width: %d\n", p->psa_databus_width);
1060 printk(KERN_DEBUG "psa_call_code/auto_squelch: 0x%02x, ",
1061 p->psa_call_code[0]);
1062 printk("psa_call_code[]: %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1063 p->psa_call_code[0],
1064 p->psa_call_code[1],
1065 p->psa_call_code[2],
1066 p->psa_call_code[3],
1067 p->psa_call_code[4],
1068 p->psa_call_code[5],
1069 p->psa_call_code[6],
1070 p->psa_call_code[7]);
1071#ifdef DEBUG_SHOW_UNUSED
1072 printk(KERN_DEBUG "psa_reserved[]: %02X:%02X\n",
1073 p->psa_reserved[0],
1074 p->psa_reserved[1]);
1075#endif /* DEBUG_SHOW_UNUSED */
1076 printk(KERN_DEBUG "psa_conf_status: %d, ", p->psa_conf_status);
1077 printk("psa_crc: 0x%02x%02x, ", p->psa_crc[0], p->psa_crc[1]);
1078 printk("psa_crc_status: 0x%02x\n", p->psa_crc_status);
1079} /* wv_psa_show */
1080#endif /* DEBUG_PSA_SHOW */
1081
1082#ifdef DEBUG_MMC_SHOW
1083/*------------------------------------------------------------------*/
1084/*
1085 * Print the formatted status of the Modem Management Controller.
1086 * This function need to be completed...
1087 */
1088static void
1089wv_mmc_show(struct net_device * dev)
1090{
1091 unsigned int base = dev->base_addr;
1092 net_local * lp = netdev_priv(dev);
1093 mmr_t m;
1094
1095 /* Basic check */
1096 if(hasr_read(base) & HASR_NO_CLK)
1097 {
1098 printk(KERN_WARNING "%s: wv_mmc_show: modem not connected\n",
1099 dev->name);
1100 return;
1101 }
1102
1103 spin_lock_irqsave(&lp->spinlock, flags);
1104
1105 /* Read the mmc */
1106 mmc_out(base, mmwoff(0, mmw_freeze), 1);
1107 mmc_read(base, 0, (u_char *)&m, sizeof(m));
1108 mmc_out(base, mmwoff(0, mmw_freeze), 0);
1109
1110 /* Don't forget to update statistics */
1111 lp->wstats.discard.nwid += (m.mmr_wrong_nwid_h << 8) | m.mmr_wrong_nwid_l;
1112
1113 spin_unlock_irqrestore(&lp->spinlock, flags);
1114
1115 printk(KERN_DEBUG "##### wavelan modem status registers: #####\n");
1116#ifdef DEBUG_SHOW_UNUSED
1117 printk(KERN_DEBUG "mmc_unused0[]: %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1118 m.mmr_unused0[0],
1119 m.mmr_unused0[1],
1120 m.mmr_unused0[2],
1121 m.mmr_unused0[3],
1122 m.mmr_unused0[4],
1123 m.mmr_unused0[5],
1124 m.mmr_unused0[6],
1125 m.mmr_unused0[7]);
1126#endif /* DEBUG_SHOW_UNUSED */
1127 printk(KERN_DEBUG "Encryption algorithm: %02X - Status: %02X\n",
1128 m.mmr_des_avail, m.mmr_des_status);
1129#ifdef DEBUG_SHOW_UNUSED
1130 printk(KERN_DEBUG "mmc_unused1[]: %02X:%02X:%02X:%02X:%02X\n",
1131 m.mmr_unused1[0],
1132 m.mmr_unused1[1],
1133 m.mmr_unused1[2],
1134 m.mmr_unused1[3],
1135 m.mmr_unused1[4]);
1136#endif /* DEBUG_SHOW_UNUSED */
1137 printk(KERN_DEBUG "dce_status: 0x%x [%s%s%s%s]\n",
1138 m.mmr_dce_status,
1139 (m.mmr_dce_status & MMR_DCE_STATUS_RX_BUSY) ? "energy detected,":"",
1140 (m.mmr_dce_status & MMR_DCE_STATUS_LOOPT_IND) ?
1141 "loop test indicated," : "",
1142 (m.mmr_dce_status & MMR_DCE_STATUS_TX_BUSY) ? "transmitter on," : "",
1143 (m.mmr_dce_status & MMR_DCE_STATUS_JBR_EXPIRED) ?
1144 "jabber timer expired," : "");
1145 printk(KERN_DEBUG "Dsp ID: %02X\n",
1146 m.mmr_dsp_id);
1147#ifdef DEBUG_SHOW_UNUSED
1148 printk(KERN_DEBUG "mmc_unused2[]: %02X:%02X\n",
1149 m.mmr_unused2[0],
1150 m.mmr_unused2[1]);
1151#endif /* DEBUG_SHOW_UNUSED */
1152 printk(KERN_DEBUG "# correct_nwid: %d, # wrong_nwid: %d\n",
1153 (m.mmr_correct_nwid_h << 8) | m.mmr_correct_nwid_l,
1154 (m.mmr_wrong_nwid_h << 8) | m.mmr_wrong_nwid_l);
1155 printk(KERN_DEBUG "thr_pre_set: 0x%x [current signal %s]\n",
1156 m.mmr_thr_pre_set & MMR_THR_PRE_SET,
1157 (m.mmr_thr_pre_set & MMR_THR_PRE_SET_CUR) ? "above" : "below");
1158 printk(KERN_DEBUG "signal_lvl: %d [%s], ",
1159 m.mmr_signal_lvl & MMR_SIGNAL_LVL,
1160 (m.mmr_signal_lvl & MMR_SIGNAL_LVL_VALID) ? "new msg" : "no new msg");
1161 printk("silence_lvl: %d [%s], ", m.mmr_silence_lvl & MMR_SILENCE_LVL,
1162 (m.mmr_silence_lvl & MMR_SILENCE_LVL_VALID) ? "update done" : "no new update");
1163 printk("sgnl_qual: 0x%x [%s]\n", m.mmr_sgnl_qual & MMR_SGNL_QUAL,
1164 (m.mmr_sgnl_qual & MMR_SGNL_QUAL_ANT) ? "Antenna 1" : "Antenna 0");
1165#ifdef DEBUG_SHOW_UNUSED
1166 printk(KERN_DEBUG "netw_id_l: %x\n", m.mmr_netw_id_l);
1167#endif /* DEBUG_SHOW_UNUSED */
1168} /* wv_mmc_show */
1169#endif /* DEBUG_MMC_SHOW */
1170
1171#ifdef DEBUG_I82593_SHOW
1172/*------------------------------------------------------------------*/
1173/*
1174 * Print the formatted status of the i82593's receive unit.
1175 */
1176static void
1177wv_ru_show(struct net_device * dev)
1178{
1179 net_local *lp = netdev_priv(dev);
1180
1181 printk(KERN_DEBUG "##### wavelan i82593 receiver status: #####\n");
1182 printk(KERN_DEBUG "ru: rfp %d stop %d", lp->rfp, lp->stop);
1183 /*
1184 * Not implemented yet...
1185 */
1186 printk("\n");
1187} /* wv_ru_show */
1188#endif /* DEBUG_I82593_SHOW */
1189
1190#ifdef DEBUG_DEVICE_SHOW
1191/*------------------------------------------------------------------*/
1192/*
1193 * Print the formatted status of the WaveLAN PCMCIA device driver.
1194 */
1195static void
1196wv_dev_show(struct net_device * dev)
1197{
1198 printk(KERN_DEBUG "dev:");
1199 printk(" state=%lX,", dev->state);
1200 printk(" trans_start=%ld,", dev->trans_start);
1201 printk(" flags=0x%x,", dev->flags);
1202 printk("\n");
1203} /* wv_dev_show */
1204
1205/*------------------------------------------------------------------*/
1206/*
1207 * Print the formatted status of the WaveLAN PCMCIA device driver's
1208 * private information.
1209 */
1210static void
1211wv_local_show(struct net_device * dev)
1212{
1213 net_local *lp = netdev_priv(dev);
1214
1215 printk(KERN_DEBUG "local:");
1216 /*
1217 * Not implemented yet...
1218 */
1219 printk("\n");
1220} /* wv_local_show */
1221#endif /* DEBUG_DEVICE_SHOW */
1222
1223#if defined(DEBUG_RX_INFO) || defined(DEBUG_TX_INFO)
1224/*------------------------------------------------------------------*/
1225/*
1226 * Dump packet header (and content if necessary) on the screen
1227 */
1228static void
1229wv_packet_info(u_char * p, /* Packet to dump */
1230 int length, /* Length of the packet */
1231 char * msg1, /* Name of the device */
1232 char * msg2) /* Name of the function */
1233{
1234 int i;
1235 int maxi;
1236
1237 printk(KERN_DEBUG "%s: %s(): dest %pM, length %d\n",
1238 msg1, msg2, p, length);
1239 printk(KERN_DEBUG "%s: %s(): src %pM, type 0x%02X%02X\n",
1240 msg1, msg2, &p[6], p[12], p[13]);
1241
1242#ifdef DEBUG_PACKET_DUMP
1243
1244 printk(KERN_DEBUG "data=\"");
1245
1246 if((maxi = length) > DEBUG_PACKET_DUMP)
1247 maxi = DEBUG_PACKET_DUMP;
1248 for(i = 14; i < maxi; i++)
1249 if(p[i] >= ' ' && p[i] <= '~')
1250 printk(" %c", p[i]);
1251 else
1252 printk("%02X", p[i]);
1253 if(maxi < length)
1254 printk("..");
1255 printk("\"\n");
1256 printk(KERN_DEBUG "\n");
1257#endif /* DEBUG_PACKET_DUMP */
1258}
1259#endif /* defined(DEBUG_RX_INFO) || defined(DEBUG_TX_INFO) */
1260
1261/*------------------------------------------------------------------*/
1262/*
1263 * This is the information which is displayed by the driver at startup
1264 * There is a lot of flag to configure it at your will...
1265 */
1266static void
1267wv_init_info(struct net_device * dev)
1268{
1269 unsigned int base = dev->base_addr;
1270 psa_t psa;
1271
1272 /* Read the parameter storage area */
1273 psa_read(dev, 0, (unsigned char *) &psa, sizeof(psa));
1274
1275#ifdef DEBUG_PSA_SHOW
1276 wv_psa_show(&psa);
1277#endif
1278#ifdef DEBUG_MMC_SHOW
1279 wv_mmc_show(dev);
1280#endif
1281#ifdef DEBUG_I82593_SHOW
1282 wv_ru_show(dev);
1283#endif
1284
1285#ifdef DEBUG_BASIC_SHOW
1286 /* Now, let's go for the basic stuff */
1287 printk(KERN_NOTICE "%s: WaveLAN: port %#x, irq %d, hw_addr %pM",
1288 dev->name, base, dev->irq, dev->dev_addr);
1289
1290 /* Print current network id */
1291 if(psa.psa_nwid_select)
1292 printk(", nwid 0x%02X-%02X", psa.psa_nwid[0], psa.psa_nwid[1]);
1293 else
1294 printk(", nwid off");
1295
1296 /* If 2.00 card */
1297 if(!(mmc_in(base, mmroff(0, mmr_fee_status)) &
1298 (MMR_FEE_STATUS_DWLD | MMR_FEE_STATUS_BUSY)))
1299 {
1300 unsigned short freq;
1301
1302 /* Ask the EEprom to read the frequency from the first area */
1303 fee_read(base, 0x00 /* 1st area - frequency... */,
1304 &freq, 1);
1305
1306 /* Print frequency */
1307 printk(", 2.00, %ld", (freq >> 6) + 2400L);
1308
1309 /* Hack !!! */
1310 if(freq & 0x20)
1311 printk(".5");
1312 }
1313 else
1314 {
1315 printk(", PCMCIA, ");
1316 switch (psa.psa_subband)
1317 {
1318 case PSA_SUBBAND_915:
1319 printk("915");
1320 break;
1321 case PSA_SUBBAND_2425:
1322 printk("2425");
1323 break;
1324 case PSA_SUBBAND_2460:
1325 printk("2460");
1326 break;
1327 case PSA_SUBBAND_2484:
1328 printk("2484");
1329 break;
1330 case PSA_SUBBAND_2430_5:
1331 printk("2430.5");
1332 break;
1333 default:
1334 printk("unknown");
1335 }
1336 }
1337
1338 printk(" MHz\n");
1339#endif /* DEBUG_BASIC_SHOW */
1340
1341#ifdef DEBUG_VERSION_SHOW
1342 /* Print version information */
1343 printk(KERN_NOTICE "%s", version);
1344#endif
1345} /* wv_init_info */
1346
1347/********************* IOCTL, STATS & RECONFIG *********************/
1348/*
1349 * We found here routines that are called by Linux on differents
1350 * occasions after the configuration and not for transmitting data
1351 * These may be called when the user use ifconfig, /proc/net/dev
1352 * or wireless extensions
1353 */
1354
1355
1356/*------------------------------------------------------------------*/
1357/*
1358 * Set or clear the multicast filter for this adaptor.
1359 * num_addrs == -1 Promiscuous mode, receive all packets
1360 * num_addrs == 0 Normal mode, clear multicast list
1361 * num_addrs > 0 Multicast mode, receive normal and MC packets,
1362 * and do best-effort filtering.
1363 */
1364
1365static void
1366wavelan_set_multicast_list(struct net_device * dev)
1367{
1368 net_local * lp = netdev_priv(dev);
1369
1370#ifdef DEBUG_IOCTL_TRACE
1371 printk(KERN_DEBUG "%s: ->wavelan_set_multicast_list()\n", dev->name);
1372#endif
1373
1374#ifdef DEBUG_IOCTL_INFO
1375 printk(KERN_DEBUG "%s: wavelan_set_multicast_list(): setting Rx mode %02X to %d addresses.\n",
1376 dev->name, dev->flags, dev->mc_count);
1377#endif
1378
1379 if(dev->flags & IFF_PROMISC)
1380 {
1381 /*
1382 * Enable promiscuous mode: receive all packets.
1383 */
1384 if(!lp->promiscuous)
1385 {
1386 lp->promiscuous = 1;
1387 lp->allmulticast = 0;
1388 lp->mc_count = 0;
1389
1390 wv_82593_reconfig(dev);
1391 }
1392 }
1393 else
1394 /* If all multicast addresses
1395 * or too much multicast addresses for the hardware filter */
1396 if((dev->flags & IFF_ALLMULTI) ||
1397 (dev->mc_count > I82593_MAX_MULTICAST_ADDRESSES))
1398 {
1399 /*
1400 * Disable promiscuous mode, but active the all multicast mode
1401 */
1402 if(!lp->allmulticast)
1403 {
1404 lp->promiscuous = 0;
1405 lp->allmulticast = 1;
1406 lp->mc_count = 0;
1407
1408 wv_82593_reconfig(dev);
1409 }
1410 }
1411 else
1412 /* If there is some multicast addresses to send */
1413 if(dev->mc_list != (struct dev_mc_list *) NULL)
1414 {
1415 /*
1416 * Disable promiscuous mode, but receive all packets
1417 * in multicast list
1418 */
1419#ifdef MULTICAST_AVOID
1420 if(lp->promiscuous || lp->allmulticast ||
1421 (dev->mc_count != lp->mc_count))
1422#endif
1423 {
1424 lp->promiscuous = 0;
1425 lp->allmulticast = 0;
1426 lp->mc_count = dev->mc_count;
1427
1428 wv_82593_reconfig(dev);
1429 }
1430 }
1431 else
1432 {
1433 /*
1434 * Switch to normal mode: disable promiscuous mode and
1435 * clear the multicast list.
1436 */
1437 if(lp->promiscuous || lp->mc_count == 0)
1438 {
1439 lp->promiscuous = 0;
1440 lp->allmulticast = 0;
1441 lp->mc_count = 0;
1442
1443 wv_82593_reconfig(dev);
1444 }
1445 }
1446#ifdef DEBUG_IOCTL_TRACE
1447 printk(KERN_DEBUG "%s: <-wavelan_set_multicast_list()\n", dev->name);
1448#endif
1449}
1450
1451/*------------------------------------------------------------------*/
1452/*
1453 * This function doesn't exist...
1454 * (Note : it was a nice way to test the reconfigure stuff...)
1455 */
1456#ifdef SET_MAC_ADDRESS
1457static int
1458wavelan_set_mac_address(struct net_device * dev,
1459 void * addr)
1460{
1461 struct sockaddr * mac = addr;
1462
1463 /* Copy the address */
1464 memcpy(dev->dev_addr, mac->sa_data, WAVELAN_ADDR_SIZE);
1465
1466 /* Reconfig the beast */
1467 wv_82593_reconfig(dev);
1468
1469 return 0;
1470}
1471#endif /* SET_MAC_ADDRESS */
1472
1473
1474/*------------------------------------------------------------------*/
1475/*
1476 * Frequency setting (for hardware able of it)
1477 * It's a bit complicated and you don't really want to look into it...
1478 */
1479static int
1480wv_set_frequency(u_long base, /* i/o port of the card */
1481 iw_freq * frequency)
1482{
1483 const int BAND_NUM = 10; /* Number of bands */
1484 long freq = 0L; /* offset to 2.4 GHz in .5 MHz */
1485#ifdef DEBUG_IOCTL_INFO
1486 int i;
1487#endif
1488
1489 /* Setting by frequency */
1490 /* Theoritically, you may set any frequency between
1491 * the two limits with a 0.5 MHz precision. In practice,
1492 * I don't want you to have trouble with local
1493 * regulations... */
1494 if((frequency->e == 1) &&
1495 (frequency->m >= (int) 2.412e8) && (frequency->m <= (int) 2.487e8))
1496 {
1497 freq = ((frequency->m / 10000) - 24000L) / 5;
1498 }
1499
1500 /* Setting by channel (same as wfreqsel) */
1501 /* Warning : each channel is 22MHz wide, so some of the channels
1502 * will interfere... */
1503 if((frequency->e == 0) &&
1504 (frequency->m >= 0) && (frequency->m < BAND_NUM))
1505 {
1506 /* Get frequency offset. */
1507 freq = channel_bands[frequency->m] >> 1;
1508 }
1509
1510 /* Verify if the frequency is allowed */
1511 if(freq != 0L)
1512 {
1513 u_short table[10]; /* Authorized frequency table */
1514
1515 /* Read the frequency table */
1516 fee_read(base, 0x71 /* frequency table */,
1517 table, 10);
1518
1519#ifdef DEBUG_IOCTL_INFO
1520 printk(KERN_DEBUG "Frequency table :");
1521 for(i = 0; i < 10; i++)
1522 {
1523 printk(" %04X",
1524 table[i]);
1525 }
1526 printk("\n");
1527#endif
1528
1529 /* Look in the table if the frequency is allowed */
1530 if(!(table[9 - ((freq - 24) / 16)] &
1531 (1 << ((freq - 24) % 16))))
1532 return -EINVAL; /* not allowed */
1533 }
1534 else
1535 return -EINVAL;
1536
1537 /* If we get a usable frequency */
1538 if(freq != 0L)
1539 {
1540 unsigned short area[16];
1541 unsigned short dac[2];
1542 unsigned short area_verify[16];
1543 unsigned short dac_verify[2];
1544 /* Corresponding gain (in the power adjust value table)
1545 * see AT&T Wavelan Data Manual, REF 407-024689/E, page 3-8
1546 * & WCIN062D.DOC, page 6.2.9 */
1547 unsigned short power_limit[] = { 40, 80, 120, 160, 0 };
1548 int power_band = 0; /* Selected band */
1549 unsigned short power_adjust; /* Correct value */
1550
1551 /* Search for the gain */
1552 power_band = 0;
1553 while((freq > power_limit[power_band]) &&
1554 (power_limit[++power_band] != 0))
1555 ;
1556
1557 /* Read the first area */
1558 fee_read(base, 0x00,
1559 area, 16);
1560
1561 /* Read the DAC */
1562 fee_read(base, 0x60,
1563 dac, 2);
1564
1565 /* Read the new power adjust value */
1566 fee_read(base, 0x6B - (power_band >> 1),
1567 &power_adjust, 1);
1568 if(power_band & 0x1)
1569 power_adjust >>= 8;
1570 else
1571 power_adjust &= 0xFF;
1572
1573#ifdef DEBUG_IOCTL_INFO
1574 printk(KERN_DEBUG "Wavelan EEprom Area 1 :");
1575 for(i = 0; i < 16; i++)
1576 {
1577 printk(" %04X",
1578 area[i]);
1579 }
1580 printk("\n");
1581
1582 printk(KERN_DEBUG "Wavelan EEprom DAC : %04X %04X\n",
1583 dac[0], dac[1]);
1584#endif
1585
1586 /* Frequency offset (for info only...) */
1587 area[0] = ((freq << 5) & 0xFFE0) | (area[0] & 0x1F);
1588
1589 /* Receiver Principle main divider coefficient */
1590 area[3] = (freq >> 1) + 2400L - 352L;
1591 area[2] = ((freq & 0x1) << 4) | (area[2] & 0xFFEF);
1592
1593 /* Transmitter Main divider coefficient */
1594 area[13] = (freq >> 1) + 2400L;
1595 area[12] = ((freq & 0x1) << 4) | (area[2] & 0xFFEF);
1596
1597 /* Others part of the area are flags, bit streams or unused... */
1598
1599 /* Set the value in the DAC */
1600 dac[1] = ((power_adjust >> 1) & 0x7F) | (dac[1] & 0xFF80);
1601 dac[0] = ((power_adjust & 0x1) << 4) | (dac[0] & 0xFFEF);
1602
1603 /* Write the first area */
1604 fee_write(base, 0x00,
1605 area, 16);
1606
1607 /* Write the DAC */
1608 fee_write(base, 0x60,
1609 dac, 2);
1610
1611 /* We now should verify here that the EEprom writing was ok */
1612
1613 /* ReRead the first area */
1614 fee_read(base, 0x00,
1615 area_verify, 16);
1616
1617 /* ReRead the DAC */
1618 fee_read(base, 0x60,
1619 dac_verify, 2);
1620
1621 /* Compare */
1622 if(memcmp(area, area_verify, 16 * 2) ||
1623 memcmp(dac, dac_verify, 2 * 2))
1624 {
1625#ifdef DEBUG_IOCTL_ERROR
1626 printk(KERN_INFO "Wavelan: wv_set_frequency : unable to write new frequency to EEprom (?)\n");
1627#endif
1628 return -EOPNOTSUPP;
1629 }
1630
1631 /* We must download the frequency parameters to the
1632 * synthetisers (from the EEprom - area 1)
1633 * Note : as the EEprom is auto decremented, we set the end
1634 * if the area... */
1635 mmc_out(base, mmwoff(0, mmw_fee_addr), 0x0F);
1636 mmc_out(base, mmwoff(0, mmw_fee_ctrl),
1637 MMW_FEE_CTRL_READ | MMW_FEE_CTRL_DWLD);
1638
1639 /* Wait until the download is finished */
1640 fee_wait(base, 100, 100);
1641
1642 /* We must now download the power adjust value (gain) to
1643 * the synthetisers (from the EEprom - area 7 - DAC) */
1644 mmc_out(base, mmwoff(0, mmw_fee_addr), 0x61);
1645 mmc_out(base, mmwoff(0, mmw_fee_ctrl),
1646 MMW_FEE_CTRL_READ | MMW_FEE_CTRL_DWLD);
1647
1648 /* Wait until the download is finished */
1649 fee_wait(base, 100, 100);
1650
1651#ifdef DEBUG_IOCTL_INFO
1652 /* Verification of what we have done... */
1653
1654 printk(KERN_DEBUG "Wavelan EEprom Area 1 :");
1655 for(i = 0; i < 16; i++)
1656 {
1657 printk(" %04X",
1658 area_verify[i]);
1659 }
1660 printk("\n");
1661
1662 printk(KERN_DEBUG "Wavelan EEprom DAC : %04X %04X\n",
1663 dac_verify[0], dac_verify[1]);
1664#endif
1665
1666 return 0;
1667 }
1668 else
1669 return -EINVAL; /* Bah, never get there... */
1670}
1671
1672/*------------------------------------------------------------------*/
1673/*
1674 * Give the list of available frequencies
1675 */
1676static int
1677wv_frequency_list(u_long base, /* i/o port of the card */
1678 iw_freq * list, /* List of frequency to fill */
1679 int max) /* Maximum number of frequencies */
1680{
1681 u_short table[10]; /* Authorized frequency table */
1682 long freq = 0L; /* offset to 2.4 GHz in .5 MHz + 12 MHz */
1683 int i; /* index in the table */
1684 const int BAND_NUM = 10; /* Number of bands */
1685 int c = 0; /* Channel number */
1686
1687 /* Read the frequency table */
1688 fee_read(base, 0x71 /* frequency table */,
1689 table, 10);
1690
1691 /* Look all frequencies */
1692 i = 0;
1693 for(freq = 0; freq < 150; freq++)
1694 /* Look in the table if the frequency is allowed */
1695 if(table[9 - (freq / 16)] & (1 << (freq % 16)))
1696 {
1697 /* Compute approximate channel number */
1698 while((((channel_bands[c] >> 1) - 24) < freq) &&
1699 (c < BAND_NUM))
1700 c++;
1701 list[i].i = c; /* Set the list index */
1702
1703 /* put in the list */
1704 list[i].m = (((freq + 24) * 5) + 24000L) * 10000;
1705 list[i++].e = 1;
1706
1707 /* Check number */
1708 if(i >= max)
1709 return(i);
1710 }
1711
1712 return(i);
1713}
1714
1715#ifdef IW_WIRELESS_SPY
1716/*------------------------------------------------------------------*/
1717/*
1718 * Gather wireless spy statistics : for each packet, compare the source
1719 * address with out list, and if match, get the stats...
1720 * Sorry, but this function really need wireless extensions...
1721 */
1722static inline void
1723wl_spy_gather(struct net_device * dev,
1724 u_char * mac, /* MAC address */
1725 u_char * stats) /* Statistics to gather */
1726{
1727 struct iw_quality wstats;
1728
1729 wstats.qual = stats[2] & MMR_SGNL_QUAL;
1730 wstats.level = stats[0] & MMR_SIGNAL_LVL;
1731 wstats.noise = stats[1] & MMR_SILENCE_LVL;
1732 wstats.updated = 0x7;
1733
1734 /* Update spy records */
1735 wireless_spy_update(dev, mac, &wstats);
1736}
1737#endif /* IW_WIRELESS_SPY */
1738
1739#ifdef HISTOGRAM
1740/*------------------------------------------------------------------*/
1741/*
1742 * This function calculate an histogram on the signal level.
1743 * As the noise is quite constant, it's like doing it on the SNR.
1744 * We have defined a set of interval (lp->his_range), and each time
1745 * the level goes in that interval, we increment the count (lp->his_sum).
1746 * With this histogram you may detect if one wavelan is really weak,
1747 * or you may also calculate the mean and standard deviation of the level...
1748 */
1749static inline void
1750wl_his_gather(struct net_device * dev,
1751 u_char * stats) /* Statistics to gather */
1752{
1753 net_local * lp = netdev_priv(dev);
1754 u_char level = stats[0] & MMR_SIGNAL_LVL;
1755 int i;
1756
1757 /* Find the correct interval */
1758 i = 0;
1759 while((i < (lp->his_number - 1)) && (level >= lp->his_range[i++]))
1760 ;
1761
1762 /* Increment interval counter */
1763 (lp->his_sum[i])++;
1764}
1765#endif /* HISTOGRAM */
1766
1767static void wl_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1768{
1769 strncpy(info->driver, "wavelan_cs", sizeof(info->driver)-1);
1770}
1771
1772static const struct ethtool_ops ops = {
1773 .get_drvinfo = wl_get_drvinfo
1774};
1775
1776/*------------------------------------------------------------------*/
1777/*
1778 * Wireless Handler : get protocol name
1779 */
1780static int wavelan_get_name(struct net_device *dev,
1781 struct iw_request_info *info,
1782 union iwreq_data *wrqu,
1783 char *extra)
1784{
1785 strcpy(wrqu->name, "WaveLAN");
1786 return 0;
1787}
1788
1789/*------------------------------------------------------------------*/
1790/*
1791 * Wireless Handler : set NWID
1792 */
1793static int wavelan_set_nwid(struct net_device *dev,
1794 struct iw_request_info *info,
1795 union iwreq_data *wrqu,
1796 char *extra)
1797{
1798 unsigned int base = dev->base_addr;
1799 net_local *lp = netdev_priv(dev);
1800 psa_t psa;
1801 mm_t m;
1802 unsigned long flags;
1803 int ret = 0;
1804
1805 /* Disable interrupts and save flags. */
1806 spin_lock_irqsave(&lp->spinlock, flags);
1807
1808 /* Set NWID in WaveLAN. */
1809 if (!wrqu->nwid.disabled) {
1810 /* Set NWID in psa */
1811 psa.psa_nwid[0] = (wrqu->nwid.value & 0xFF00) >> 8;
1812 psa.psa_nwid[1] = wrqu->nwid.value & 0xFF;
1813 psa.psa_nwid_select = 0x01;
1814 psa_write(dev,
1815 (char *) psa.psa_nwid - (char *) &psa,
1816 (unsigned char *) psa.psa_nwid, 3);
1817
1818 /* Set NWID in mmc. */
1819 m.w.mmw_netw_id_l = psa.psa_nwid[1];
1820 m.w.mmw_netw_id_h = psa.psa_nwid[0];
1821 mmc_write(base,
1822 (char *) &m.w.mmw_netw_id_l -
1823 (char *) &m,
1824 (unsigned char *) &m.w.mmw_netw_id_l, 2);
1825 mmc_out(base, mmwoff(0, mmw_loopt_sel), 0x00);
1826 } else {
1827 /* Disable NWID in the psa. */
1828 psa.psa_nwid_select = 0x00;
1829 psa_write(dev,
1830 (char *) &psa.psa_nwid_select -
1831 (char *) &psa,
1832 (unsigned char *) &psa.psa_nwid_select,
1833 1);
1834
1835 /* Disable NWID in the mmc (no filtering). */
1836 mmc_out(base, mmwoff(0, mmw_loopt_sel),
1837 MMW_LOOPT_SEL_DIS_NWID);
1838 }
1839 /* update the Wavelan checksum */
1840 update_psa_checksum(dev);
1841
1842 /* Enable interrupts and restore flags. */
1843 spin_unlock_irqrestore(&lp->spinlock, flags);
1844
1845 return ret;
1846}
1847
1848/*------------------------------------------------------------------*/
1849/*
1850 * Wireless Handler : get NWID
1851 */
1852static int wavelan_get_nwid(struct net_device *dev,
1853 struct iw_request_info *info,
1854 union iwreq_data *wrqu,
1855 char *extra)
1856{
1857 net_local *lp = netdev_priv(dev);
1858 psa_t psa;
1859 unsigned long flags;
1860 int ret = 0;
1861
1862 /* Disable interrupts and save flags. */
1863 spin_lock_irqsave(&lp->spinlock, flags);
1864
1865 /* Read the NWID. */
1866 psa_read(dev,
1867 (char *) psa.psa_nwid - (char *) &psa,
1868 (unsigned char *) psa.psa_nwid, 3);
1869 wrqu->nwid.value = (psa.psa_nwid[0] << 8) + psa.psa_nwid[1];
1870 wrqu->nwid.disabled = !(psa.psa_nwid_select);
1871 wrqu->nwid.fixed = 1; /* Superfluous */
1872
1873 /* Enable interrupts and restore flags. */
1874 spin_unlock_irqrestore(&lp->spinlock, flags);
1875
1876 return ret;
1877}
1878
1879/*------------------------------------------------------------------*/
1880/*
1881 * Wireless Handler : set frequency
1882 */
1883static int wavelan_set_freq(struct net_device *dev,
1884 struct iw_request_info *info,
1885 union iwreq_data *wrqu,
1886 char *extra)
1887{
1888 unsigned int base = dev->base_addr;
1889 net_local *lp = netdev_priv(dev);
1890 unsigned long flags;
1891 int ret;
1892
1893 /* Disable interrupts and save flags. */
1894 spin_lock_irqsave(&lp->spinlock, flags);
1895
1896 /* Attempt to recognise 2.00 cards (2.4 GHz frequency selectable). */
1897 if (!(mmc_in(base, mmroff(0, mmr_fee_status)) &
1898 (MMR_FEE_STATUS_DWLD | MMR_FEE_STATUS_BUSY)))
1899 ret = wv_set_frequency(base, &(wrqu->freq));
1900 else
1901 ret = -EOPNOTSUPP;
1902
1903 /* Enable interrupts and restore flags. */
1904 spin_unlock_irqrestore(&lp->spinlock, flags);
1905
1906 return ret;
1907}
1908
1909/*------------------------------------------------------------------*/
1910/*
1911 * Wireless Handler : get frequency
1912 */
1913static int wavelan_get_freq(struct net_device *dev,
1914 struct iw_request_info *info,
1915 union iwreq_data *wrqu,
1916 char *extra)
1917{
1918 unsigned int base = dev->base_addr;
1919 net_local *lp = netdev_priv(dev);
1920 psa_t psa;
1921 unsigned long flags;
1922 int ret = 0;
1923
1924 /* Disable interrupts and save flags. */
1925 spin_lock_irqsave(&lp->spinlock, flags);
1926
1927 /* Attempt to recognise 2.00 cards (2.4 GHz frequency selectable).
1928 * Does it work for everybody, especially old cards? */
1929 if (!(mmc_in(base, mmroff(0, mmr_fee_status)) &
1930 (MMR_FEE_STATUS_DWLD | MMR_FEE_STATUS_BUSY))) {
1931 unsigned short freq;
1932
1933 /* Ask the EEPROM to read the frequency from the first area. */
1934 fee_read(base, 0x00, &freq, 1);
1935 wrqu->freq.m = ((freq >> 5) * 5 + 24000L) * 10000;
1936 wrqu->freq.e = 1;
1937 } else {
1938 psa_read(dev,
1939 (char *) &psa.psa_subband - (char *) &psa,
1940 (unsigned char *) &psa.psa_subband, 1);
1941
1942 if (psa.psa_subband <= 4) {
1943 wrqu->freq.m = fixed_bands[psa.psa_subband];
1944 wrqu->freq.e = (psa.psa_subband != 0);
1945 } else
1946 ret = -EOPNOTSUPP;
1947 }
1948
1949 /* Enable interrupts and restore flags. */
1950 spin_unlock_irqrestore(&lp->spinlock, flags);
1951
1952 return ret;
1953}
1954
1955/*------------------------------------------------------------------*/
1956/*
1957 * Wireless Handler : set level threshold
1958 */
1959static int wavelan_set_sens(struct net_device *dev,
1960 struct iw_request_info *info,
1961 union iwreq_data *wrqu,
1962 char *extra)
1963{
1964 unsigned int base = dev->base_addr;
1965 net_local *lp = netdev_priv(dev);
1966 psa_t psa;
1967 unsigned long flags;
1968 int ret = 0;
1969
1970 /* Disable interrupts and save flags. */
1971 spin_lock_irqsave(&lp->spinlock, flags);
1972
1973 /* Set the level threshold. */
1974 /* We should complain loudly if wrqu->sens.fixed = 0, because we
1975 * can't set auto mode... */
1976 psa.psa_thr_pre_set = wrqu->sens.value & 0x3F;
1977 psa_write(dev,
1978 (char *) &psa.psa_thr_pre_set - (char *) &psa,
1979 (unsigned char *) &psa.psa_thr_pre_set, 1);
1980 /* update the Wavelan checksum */
1981 update_psa_checksum(dev);
1982 mmc_out(base, mmwoff(0, mmw_thr_pre_set),
1983 psa.psa_thr_pre_set);
1984
1985 /* Enable interrupts and restore flags. */
1986 spin_unlock_irqrestore(&lp->spinlock, flags);
1987
1988 return ret;
1989}
1990
1991/*------------------------------------------------------------------*/
1992/*
1993 * Wireless Handler : get level threshold
1994 */
1995static int wavelan_get_sens(struct net_device *dev,
1996 struct iw_request_info *info,
1997 union iwreq_data *wrqu,
1998 char *extra)
1999{
2000 net_local *lp = netdev_priv(dev);
2001 psa_t psa;
2002 unsigned long flags;
2003 int ret = 0;
2004
2005 /* Disable interrupts and save flags. */
2006 spin_lock_irqsave(&lp->spinlock, flags);
2007
2008 /* Read the level threshold. */
2009 psa_read(dev,
2010 (char *) &psa.psa_thr_pre_set - (char *) &psa,
2011 (unsigned char *) &psa.psa_thr_pre_set, 1);
2012 wrqu->sens.value = psa.psa_thr_pre_set & 0x3F;
2013 wrqu->sens.fixed = 1;
2014
2015 /* Enable interrupts and restore flags. */
2016 spin_unlock_irqrestore(&lp->spinlock, flags);
2017
2018 return ret;
2019}
2020
2021/*------------------------------------------------------------------*/
2022/*
2023 * Wireless Handler : set encryption key
2024 */
2025static int wavelan_set_encode(struct net_device *dev,
2026 struct iw_request_info *info,
2027 union iwreq_data *wrqu,
2028 char *extra)
2029{
2030 unsigned int base = dev->base_addr;
2031 net_local *lp = netdev_priv(dev);
2032 unsigned long flags;
2033 psa_t psa;
2034 int ret = 0;
2035
2036 /* Disable interrupts and save flags. */
2037 spin_lock_irqsave(&lp->spinlock, flags);
2038
2039 /* Check if capable of encryption */
2040 if (!mmc_encr(base)) {
2041 ret = -EOPNOTSUPP;
2042 }
2043
2044 /* Check the size of the key */
2045 if((wrqu->encoding.length != 8) && (wrqu->encoding.length != 0)) {
2046 ret = -EINVAL;
2047 }
2048
2049 if(!ret) {
2050 /* Basic checking... */
2051 if (wrqu->encoding.length == 8) {
2052 /* Copy the key in the driver */
2053 memcpy(psa.psa_encryption_key, extra,
2054 wrqu->encoding.length);
2055 psa.psa_encryption_select = 1;
2056
2057 psa_write(dev,
2058 (char *) &psa.psa_encryption_select -
2059 (char *) &psa,
2060 (unsigned char *) &psa.
2061 psa_encryption_select, 8 + 1);
2062
2063 mmc_out(base, mmwoff(0, mmw_encr_enable),
2064 MMW_ENCR_ENABLE_EN | MMW_ENCR_ENABLE_MODE);
2065 mmc_write(base, mmwoff(0, mmw_encr_key),
2066 (unsigned char *) &psa.
2067 psa_encryption_key, 8);
2068 }
2069
2070 /* disable encryption */
2071 if (wrqu->encoding.flags & IW_ENCODE_DISABLED) {
2072 psa.psa_encryption_select = 0;
2073 psa_write(dev,
2074 (char *) &psa.psa_encryption_select -
2075 (char *) &psa,
2076 (unsigned char *) &psa.
2077 psa_encryption_select, 1);
2078
2079 mmc_out(base, mmwoff(0, mmw_encr_enable), 0);
2080 }
2081 /* update the Wavelan checksum */
2082 update_psa_checksum(dev);
2083 }
2084
2085 /* Enable interrupts and restore flags. */
2086 spin_unlock_irqrestore(&lp->spinlock, flags);
2087
2088 return ret;
2089}
2090
2091/*------------------------------------------------------------------*/
2092/*
2093 * Wireless Handler : get encryption key
2094 */
2095static int wavelan_get_encode(struct net_device *dev,
2096 struct iw_request_info *info,
2097 union iwreq_data *wrqu,
2098 char *extra)
2099{
2100 unsigned int base = dev->base_addr;
2101 net_local *lp = netdev_priv(dev);
2102 psa_t psa;
2103 unsigned long flags;
2104 int ret = 0;
2105
2106 /* Disable interrupts and save flags. */
2107 spin_lock_irqsave(&lp->spinlock, flags);
2108
2109 /* Check if encryption is available */
2110 if (!mmc_encr(base)) {
2111 ret = -EOPNOTSUPP;
2112 } else {
2113 /* Read the encryption key */
2114 psa_read(dev,
2115 (char *) &psa.psa_encryption_select -
2116 (char *) &psa,
2117 (unsigned char *) &psa.
2118 psa_encryption_select, 1 + 8);
2119
2120 /* encryption is enabled ? */
2121 if (psa.psa_encryption_select)
2122 wrqu->encoding.flags = IW_ENCODE_ENABLED;
2123 else
2124 wrqu->encoding.flags = IW_ENCODE_DISABLED;
2125 wrqu->encoding.flags |= mmc_encr(base);
2126
2127 /* Copy the key to the user buffer */
2128 wrqu->encoding.length = 8;
2129 memcpy(extra, psa.psa_encryption_key, wrqu->encoding.length);
2130 }
2131
2132 /* Enable interrupts and restore flags. */
2133 spin_unlock_irqrestore(&lp->spinlock, flags);
2134
2135 return ret;
2136}
2137
2138#ifdef WAVELAN_ROAMING_EXT
2139/*------------------------------------------------------------------*/
2140/*
2141 * Wireless Handler : set ESSID (domain)
2142 */
2143static int wavelan_set_essid(struct net_device *dev,
2144 struct iw_request_info *info,
2145 union iwreq_data *wrqu,
2146 char *extra)
2147{
2148 net_local *lp = netdev_priv(dev);
2149 unsigned long flags;
2150 int ret = 0;
2151
2152 /* Disable interrupts and save flags. */
2153 spin_lock_irqsave(&lp->spinlock, flags);
2154
2155 /* Check if disable */
2156 if(wrqu->data.flags == 0)
2157 lp->filter_domains = 0;
2158 else {
2159 char essid[IW_ESSID_MAX_SIZE + 1];
2160 char * endp;
2161
2162 /* Terminate the string */
2163 memcpy(essid, extra, wrqu->data.length);
2164 essid[IW_ESSID_MAX_SIZE] = '\0';
2165
2166#ifdef DEBUG_IOCTL_INFO
2167 printk(KERN_DEBUG "SetEssid : ``%s''\n", essid);
2168#endif /* DEBUG_IOCTL_INFO */
2169
2170 /* Convert to a number (note : Wavelan specific) */
2171 lp->domain_id = simple_strtoul(essid, &endp, 16);
2172 /* Has it worked ? */
2173 if(endp > essid)
2174 lp->filter_domains = 1;
2175 else {
2176 lp->filter_domains = 0;
2177 ret = -EINVAL;
2178 }
2179 }
2180
2181 /* Enable interrupts and restore flags. */
2182 spin_unlock_irqrestore(&lp->spinlock, flags);
2183
2184 return ret;
2185}
2186
2187/*------------------------------------------------------------------*/
2188/*
2189 * Wireless Handler : get ESSID (domain)
2190 */
2191static int wavelan_get_essid(struct net_device *dev,
2192 struct iw_request_info *info,
2193 union iwreq_data *wrqu,
2194 char *extra)
2195{
2196 net_local *lp = netdev_priv(dev);
2197
2198 /* Is the domain ID active ? */
2199 wrqu->data.flags = lp->filter_domains;
2200
2201 /* Copy Domain ID into a string (Wavelan specific) */
2202 /* Sound crazy, be we can't have a snprintf in the kernel !!! */
2203 sprintf(extra, "%lX", lp->domain_id);
2204 extra[IW_ESSID_MAX_SIZE] = '\0';
2205
2206 /* Set the length */
2207 wrqu->data.length = strlen(extra);
2208
2209 return 0;
2210}
2211
2212/*------------------------------------------------------------------*/
2213/*
2214 * Wireless Handler : set AP address
2215 */
2216static int wavelan_set_wap(struct net_device *dev,
2217 struct iw_request_info *info,
2218 union iwreq_data *wrqu,
2219 char *extra)
2220{
2221#ifdef DEBUG_IOCTL_INFO
2222 printk(KERN_DEBUG "Set AP to : %pM\n", wrqu->ap_addr.sa_data);
2223#endif /* DEBUG_IOCTL_INFO */
2224
2225 return -EOPNOTSUPP;
2226}
2227
2228/*------------------------------------------------------------------*/
2229/*
2230 * Wireless Handler : get AP address
2231 */
2232static int wavelan_get_wap(struct net_device *dev,
2233 struct iw_request_info *info,
2234 union iwreq_data *wrqu,
2235 char *extra)
2236{
2237 /* Should get the real McCoy instead of own Ethernet address */
2238 memcpy(wrqu->ap_addr.sa_data, dev->dev_addr, WAVELAN_ADDR_SIZE);
2239 wrqu->ap_addr.sa_family = ARPHRD_ETHER;
2240
2241 return -EOPNOTSUPP;
2242}
2243#endif /* WAVELAN_ROAMING_EXT */
2244
2245#ifdef WAVELAN_ROAMING
2246/*------------------------------------------------------------------*/
2247/*
2248 * Wireless Handler : set mode
2249 */
2250static int wavelan_set_mode(struct net_device *dev,
2251 struct iw_request_info *info,
2252 union iwreq_data *wrqu,
2253 char *extra)
2254{
2255 net_local *lp = netdev_priv(dev);
2256 unsigned long flags;
2257 int ret = 0;
2258
2259 /* Disable interrupts and save flags. */
2260 spin_lock_irqsave(&lp->spinlock, flags);
2261
2262 /* Check mode */
2263 switch(wrqu->mode) {
2264 case IW_MODE_ADHOC:
2265 if(do_roaming) {
2266 wv_roam_cleanup(dev);
2267 do_roaming = 0;
2268 }
2269 break;
2270 case IW_MODE_INFRA:
2271 if(!do_roaming) {
2272 wv_roam_init(dev);
2273 do_roaming = 1;
2274 }
2275 break;
2276 default:
2277 ret = -EINVAL;
2278 }
2279
2280 /* Enable interrupts and restore flags. */
2281 spin_unlock_irqrestore(&lp->spinlock, flags);
2282
2283 return ret;
2284}
2285
2286/*------------------------------------------------------------------*/
2287/*
2288 * Wireless Handler : get mode
2289 */
2290static int wavelan_get_mode(struct net_device *dev,
2291 struct iw_request_info *info,
2292 union iwreq_data *wrqu,
2293 char *extra)
2294{
2295 if(do_roaming)
2296 wrqu->mode = IW_MODE_INFRA;
2297 else
2298 wrqu->mode = IW_MODE_ADHOC;
2299
2300 return 0;
2301}
2302#endif /* WAVELAN_ROAMING */
2303
2304/*------------------------------------------------------------------*/
2305/*
2306 * Wireless Handler : get range info
2307 */
2308static int wavelan_get_range(struct net_device *dev,
2309 struct iw_request_info *info,
2310 union iwreq_data *wrqu,
2311 char *extra)
2312{
2313 unsigned int base = dev->base_addr;
2314 net_local *lp = netdev_priv(dev);
2315 struct iw_range *range = (struct iw_range *) extra;
2316 unsigned long flags;
2317 int ret = 0;
2318
2319 /* Set the length (very important for backward compatibility) */
2320 wrqu->data.length = sizeof(struct iw_range);
2321
2322 /* Set all the info we don't care or don't know about to zero */
2323 memset(range, 0, sizeof(struct iw_range));
2324
2325 /* Set the Wireless Extension versions */
2326 range->we_version_compiled = WIRELESS_EXT;
2327 range->we_version_source = 9;
2328
2329 /* Set information in the range struct. */
2330 range->throughput = 1.4 * 1000 * 1000; /* don't argue on this ! */
2331 range->min_nwid = 0x0000;
2332 range->max_nwid = 0xFFFF;
2333
2334 range->sensitivity = 0x3F;
2335 range->max_qual.qual = MMR_SGNL_QUAL;
2336 range->max_qual.level = MMR_SIGNAL_LVL;
2337 range->max_qual.noise = MMR_SILENCE_LVL;
2338 range->avg_qual.qual = MMR_SGNL_QUAL; /* Always max */
2339 /* Need to get better values for those two */
2340 range->avg_qual.level = 30;
2341 range->avg_qual.noise = 8;
2342
2343 range->num_bitrates = 1;
2344 range->bitrate[0] = 2000000; /* 2 Mb/s */
2345
2346 /* Event capability (kernel + driver) */
2347 range->event_capa[0] = (IW_EVENT_CAPA_MASK(0x8B02) |
2348 IW_EVENT_CAPA_MASK(0x8B04) |
2349 IW_EVENT_CAPA_MASK(0x8B06));
2350 range->event_capa[1] = IW_EVENT_CAPA_K_1;
2351
2352 /* Disable interrupts and save flags. */
2353 spin_lock_irqsave(&lp->spinlock, flags);
2354
2355 /* Attempt to recognise 2.00 cards (2.4 GHz frequency selectable). */
2356 if (!(mmc_in(base, mmroff(0, mmr_fee_status)) &
2357 (MMR_FEE_STATUS_DWLD | MMR_FEE_STATUS_BUSY))) {
2358 range->num_channels = 10;
2359 range->num_frequency = wv_frequency_list(base, range->freq,
2360 IW_MAX_FREQUENCIES);
2361 } else
2362 range->num_channels = range->num_frequency = 0;
2363
2364 /* Encryption supported ? */
2365 if (mmc_encr(base)) {
2366 range->encoding_size[0] = 8; /* DES = 64 bits key */
2367 range->num_encoding_sizes = 1;
2368 range->max_encoding_tokens = 1; /* Only one key possible */
2369 } else {
2370 range->num_encoding_sizes = 0;
2371 range->max_encoding_tokens = 0;
2372 }
2373
2374 /* Enable interrupts and restore flags. */
2375 spin_unlock_irqrestore(&lp->spinlock, flags);
2376
2377 return ret;
2378}
2379
2380/*------------------------------------------------------------------*/
2381/*
2382 * Wireless Private Handler : set quality threshold
2383 */
2384static int wavelan_set_qthr(struct net_device *dev,
2385 struct iw_request_info *info,
2386 union iwreq_data *wrqu,
2387 char *extra)
2388{
2389 unsigned int base = dev->base_addr;
2390 net_local *lp = netdev_priv(dev);
2391 psa_t psa;
2392 unsigned long flags;
2393
2394 /* Disable interrupts and save flags. */
2395 spin_lock_irqsave(&lp->spinlock, flags);
2396
2397 psa.psa_quality_thr = *(extra) & 0x0F;
2398 psa_write(dev,
2399 (char *) &psa.psa_quality_thr - (char *) &psa,
2400 (unsigned char *) &psa.psa_quality_thr, 1);
2401 /* update the Wavelan checksum */
2402 update_psa_checksum(dev);
2403 mmc_out(base, mmwoff(0, mmw_quality_thr),
2404 psa.psa_quality_thr);
2405
2406 /* Enable interrupts and restore flags. */
2407 spin_unlock_irqrestore(&lp->spinlock, flags);
2408
2409 return 0;
2410}
2411
2412/*------------------------------------------------------------------*/
2413/*
2414 * Wireless Private Handler : get quality threshold
2415 */
2416static int wavelan_get_qthr(struct net_device *dev,
2417 struct iw_request_info *info,
2418 union iwreq_data *wrqu,
2419 char *extra)
2420{
2421 net_local *lp = netdev_priv(dev);
2422 psa_t psa;
2423 unsigned long flags;
2424
2425 /* Disable interrupts and save flags. */
2426 spin_lock_irqsave(&lp->spinlock, flags);
2427
2428 psa_read(dev,
2429 (char *) &psa.psa_quality_thr - (char *) &psa,
2430 (unsigned char *) &psa.psa_quality_thr, 1);
2431 *(extra) = psa.psa_quality_thr & 0x0F;
2432
2433 /* Enable interrupts and restore flags. */
2434 spin_unlock_irqrestore(&lp->spinlock, flags);
2435
2436 return 0;
2437}
2438
2439#ifdef WAVELAN_ROAMING
2440/*------------------------------------------------------------------*/
2441/*
2442 * Wireless Private Handler : set roaming
2443 */
2444static int wavelan_set_roam(struct net_device *dev,
2445 struct iw_request_info *info,
2446 union iwreq_data *wrqu,
2447 char *extra)
2448{
2449 net_local *lp = netdev_priv(dev);
2450 unsigned long flags;
2451
2452 /* Disable interrupts and save flags. */
2453 spin_lock_irqsave(&lp->spinlock, flags);
2454
2455 /* Note : should check if user == root */
2456 if(do_roaming && (*extra)==0)
2457 wv_roam_cleanup(dev);
2458 else if(do_roaming==0 && (*extra)!=0)
2459 wv_roam_init(dev);
2460
2461 do_roaming = (*extra);
2462
2463 /* Enable interrupts and restore flags. */
2464 spin_unlock_irqrestore(&lp->spinlock, flags);
2465
2466 return 0;
2467}
2468
2469/*------------------------------------------------------------------*/
2470/*
2471 * Wireless Private Handler : get quality threshold
2472 */
2473static int wavelan_get_roam(struct net_device *dev,
2474 struct iw_request_info *info,
2475 union iwreq_data *wrqu,
2476 char *extra)
2477{
2478 *(extra) = do_roaming;
2479
2480 return 0;
2481}
2482#endif /* WAVELAN_ROAMING */
2483
2484#ifdef HISTOGRAM
2485/*------------------------------------------------------------------*/
2486/*
2487 * Wireless Private Handler : set histogram
2488 */
2489static int wavelan_set_histo(struct net_device *dev,
2490 struct iw_request_info *info,
2491 union iwreq_data *wrqu,
2492 char *extra)
2493{
2494 net_local *lp = netdev_priv(dev);
2495
2496 /* Check the number of intervals. */
2497 if (wrqu->data.length > 16) {
2498 return(-E2BIG);
2499 }
2500
2501 /* Disable histo while we copy the addresses.
2502 * As we don't disable interrupts, we need to do this */
2503 lp->his_number = 0;
2504
2505 /* Are there ranges to copy? */
2506 if (wrqu->data.length > 0) {
2507 /* Copy interval ranges to the driver */
2508 memcpy(lp->his_range, extra, wrqu->data.length);
2509
2510 {
2511 int i;
2512 printk(KERN_DEBUG "Histo :");
2513 for(i = 0; i < wrqu->data.length; i++)
2514 printk(" %d", lp->his_range[i]);
2515 printk("\n");
2516 }
2517
2518 /* Reset result structure. */
2519 memset(lp->his_sum, 0x00, sizeof(long) * 16);
2520 }
2521
2522 /* Now we can set the number of ranges */
2523 lp->his_number = wrqu->data.length;
2524
2525 return(0);
2526}
2527
2528/*------------------------------------------------------------------*/
2529/*
2530 * Wireless Private Handler : get histogram
2531 */
2532static int wavelan_get_histo(struct net_device *dev,
2533 struct iw_request_info *info,
2534 union iwreq_data *wrqu,
2535 char *extra)
2536{
2537 net_local *lp = netdev_priv(dev);
2538
2539 /* Set the number of intervals. */
2540 wrqu->data.length = lp->his_number;
2541
2542 /* Give back the distribution statistics */
2543 if(lp->his_number > 0)
2544 memcpy(extra, lp->his_sum, sizeof(long) * lp->his_number);
2545
2546 return(0);
2547}
2548#endif /* HISTOGRAM */
2549
2550/*------------------------------------------------------------------*/
2551/*
2552 * Structures to export the Wireless Handlers
2553 */
2554
2555static const struct iw_priv_args wavelan_private_args[] = {
2556/*{ cmd, set_args, get_args, name } */
2557 { SIOCSIPQTHR, IW_PRIV_TYPE_BYTE | IW_PRIV_SIZE_FIXED | 1, 0, "setqualthr" },
2558 { SIOCGIPQTHR, 0, IW_PRIV_TYPE_BYTE | IW_PRIV_SIZE_FIXED | 1, "getqualthr" },
2559 { SIOCSIPROAM, IW_PRIV_TYPE_BYTE | IW_PRIV_SIZE_FIXED | 1, 0, "setroam" },
2560 { SIOCGIPROAM, 0, IW_PRIV_TYPE_BYTE | IW_PRIV_SIZE_FIXED | 1, "getroam" },
2561 { SIOCSIPHISTO, IW_PRIV_TYPE_BYTE | 16, 0, "sethisto" },
2562 { SIOCGIPHISTO, 0, IW_PRIV_TYPE_INT | 16, "gethisto" },
2563};
2564
2565static const iw_handler wavelan_handler[] =
2566{
2567 NULL, /* SIOCSIWNAME */
2568 wavelan_get_name, /* SIOCGIWNAME */
2569 wavelan_set_nwid, /* SIOCSIWNWID */
2570 wavelan_get_nwid, /* SIOCGIWNWID */
2571 wavelan_set_freq, /* SIOCSIWFREQ */
2572 wavelan_get_freq, /* SIOCGIWFREQ */
2573#ifdef WAVELAN_ROAMING
2574 wavelan_set_mode, /* SIOCSIWMODE */
2575 wavelan_get_mode, /* SIOCGIWMODE */
2576#else /* WAVELAN_ROAMING */
2577 NULL, /* SIOCSIWMODE */
2578 NULL, /* SIOCGIWMODE */
2579#endif /* WAVELAN_ROAMING */
2580 wavelan_set_sens, /* SIOCSIWSENS */
2581 wavelan_get_sens, /* SIOCGIWSENS */
2582 NULL, /* SIOCSIWRANGE */
2583 wavelan_get_range, /* SIOCGIWRANGE */
2584 NULL, /* SIOCSIWPRIV */
2585 NULL, /* SIOCGIWPRIV */
2586 NULL, /* SIOCSIWSTATS */
2587 NULL, /* SIOCGIWSTATS */
2588 iw_handler_set_spy, /* SIOCSIWSPY */
2589 iw_handler_get_spy, /* SIOCGIWSPY */
2590 iw_handler_set_thrspy, /* SIOCSIWTHRSPY */
2591 iw_handler_get_thrspy, /* SIOCGIWTHRSPY */
2592#ifdef WAVELAN_ROAMING_EXT
2593 wavelan_set_wap, /* SIOCSIWAP */
2594 wavelan_get_wap, /* SIOCGIWAP */
2595 NULL, /* -- hole -- */
2596 NULL, /* SIOCGIWAPLIST */
2597 NULL, /* -- hole -- */
2598 NULL, /* -- hole -- */
2599 wavelan_set_essid, /* SIOCSIWESSID */
2600 wavelan_get_essid, /* SIOCGIWESSID */
2601#else /* WAVELAN_ROAMING_EXT */
2602 NULL, /* SIOCSIWAP */
2603 NULL, /* SIOCGIWAP */
2604 NULL, /* -- hole -- */
2605 NULL, /* SIOCGIWAPLIST */
2606 NULL, /* -- hole -- */
2607 NULL, /* -- hole -- */
2608 NULL, /* SIOCSIWESSID */
2609 NULL, /* SIOCGIWESSID */
2610#endif /* WAVELAN_ROAMING_EXT */
2611 NULL, /* SIOCSIWNICKN */
2612 NULL, /* SIOCGIWNICKN */
2613 NULL, /* -- hole -- */
2614 NULL, /* -- hole -- */
2615 NULL, /* SIOCSIWRATE */
2616 NULL, /* SIOCGIWRATE */
2617 NULL, /* SIOCSIWRTS */
2618 NULL, /* SIOCGIWRTS */
2619 NULL, /* SIOCSIWFRAG */
2620 NULL, /* SIOCGIWFRAG */
2621 NULL, /* SIOCSIWTXPOW */
2622 NULL, /* SIOCGIWTXPOW */
2623 NULL, /* SIOCSIWRETRY */
2624 NULL, /* SIOCGIWRETRY */
2625 wavelan_set_encode, /* SIOCSIWENCODE */
2626 wavelan_get_encode, /* SIOCGIWENCODE */
2627};
2628
2629static const iw_handler wavelan_private_handler[] =
2630{
2631 wavelan_set_qthr, /* SIOCIWFIRSTPRIV */
2632 wavelan_get_qthr, /* SIOCIWFIRSTPRIV + 1 */
2633#ifdef WAVELAN_ROAMING
2634 wavelan_set_roam, /* SIOCIWFIRSTPRIV + 2 */
2635 wavelan_get_roam, /* SIOCIWFIRSTPRIV + 3 */
2636#else /* WAVELAN_ROAMING */
2637 NULL, /* SIOCIWFIRSTPRIV + 2 */
2638 NULL, /* SIOCIWFIRSTPRIV + 3 */
2639#endif /* WAVELAN_ROAMING */
2640#ifdef HISTOGRAM
2641 wavelan_set_histo, /* SIOCIWFIRSTPRIV + 4 */
2642 wavelan_get_histo, /* SIOCIWFIRSTPRIV + 5 */
2643#endif /* HISTOGRAM */
2644};
2645
2646static const struct iw_handler_def wavelan_handler_def =
2647{
2648 .num_standard = ARRAY_SIZE(wavelan_handler),
2649 .num_private = ARRAY_SIZE(wavelan_private_handler),
2650 .num_private_args = ARRAY_SIZE(wavelan_private_args),
2651 .standard = wavelan_handler,
2652 .private = wavelan_private_handler,
2653 .private_args = wavelan_private_args,
2654 .get_wireless_stats = wavelan_get_wireless_stats,
2655};
2656
2657/*------------------------------------------------------------------*/
2658/*
2659 * Get wireless statistics
2660 * Called by /proc/net/wireless...
2661 */
2662static iw_stats *
2663wavelan_get_wireless_stats(struct net_device * dev)
2664{
2665 unsigned int base = dev->base_addr;
2666 net_local * lp = netdev_priv(dev);
2667 mmr_t m;
2668 iw_stats * wstats;
2669 unsigned long flags;
2670
2671#ifdef DEBUG_IOCTL_TRACE
2672 printk(KERN_DEBUG "%s: ->wavelan_get_wireless_stats()\n", dev->name);
2673#endif
2674
2675 /* Disable interrupts & save flags */
2676 spin_lock_irqsave(&lp->spinlock, flags);
2677
2678 wstats = &lp->wstats;
2679
2680 /* Get data from the mmc */
2681 mmc_out(base, mmwoff(0, mmw_freeze), 1);
2682
2683 mmc_read(base, mmroff(0, mmr_dce_status), &m.mmr_dce_status, 1);
2684 mmc_read(base, mmroff(0, mmr_wrong_nwid_l), &m.mmr_wrong_nwid_l, 2);
2685 mmc_read(base, mmroff(0, mmr_thr_pre_set), &m.mmr_thr_pre_set, 4);
2686
2687 mmc_out(base, mmwoff(0, mmw_freeze), 0);
2688
2689 /* Copy data to wireless stuff */
2690 wstats->status = m.mmr_dce_status & MMR_DCE_STATUS;
2691 wstats->qual.qual = m.mmr_sgnl_qual & MMR_SGNL_QUAL;
2692 wstats->qual.level = m.mmr_signal_lvl & MMR_SIGNAL_LVL;
2693 wstats->qual.noise = m.mmr_silence_lvl & MMR_SILENCE_LVL;
2694 wstats->qual.updated = (((m.mmr_signal_lvl & MMR_SIGNAL_LVL_VALID) >> 7) |
2695 ((m.mmr_signal_lvl & MMR_SIGNAL_LVL_VALID) >> 6) |
2696 ((m.mmr_silence_lvl & MMR_SILENCE_LVL_VALID) >> 5));
2697 wstats->discard.nwid += (m.mmr_wrong_nwid_h << 8) | m.mmr_wrong_nwid_l;
2698 wstats->discard.code = 0L;
2699 wstats->discard.misc = 0L;
2700
2701 /* ReEnable interrupts & restore flags */
2702 spin_unlock_irqrestore(&lp->spinlock, flags);
2703
2704#ifdef DEBUG_IOCTL_TRACE
2705 printk(KERN_DEBUG "%s: <-wavelan_get_wireless_stats()\n", dev->name);
2706#endif
2707 return &lp->wstats;
2708}
2709
2710/************************* PACKET RECEPTION *************************/
2711/*
2712 * This part deal with receiving the packets.
2713 * The interrupt handler get an interrupt when a packet has been
2714 * successfully received and called this part...
2715 */
2716
2717/*------------------------------------------------------------------*/
2718/*
2719 * Calculate the starting address of the frame pointed to by the receive
2720 * frame pointer and verify that the frame seem correct
2721 * (called by wv_packet_rcv())
2722 */
2723static int
2724wv_start_of_frame(struct net_device * dev,
2725 int rfp, /* end of frame */
2726 int wrap) /* start of buffer */
2727{
2728 unsigned int base = dev->base_addr;
2729 int rp;
2730 int len;
2731
2732 rp = (rfp - 5 + RX_SIZE) % RX_SIZE;
2733 outb(rp & 0xff, PIORL(base));
2734 outb(((rp >> 8) & PIORH_MASK), PIORH(base));
2735 len = inb(PIOP(base));
2736 len |= inb(PIOP(base)) << 8;
2737
2738 /* Sanity checks on size */
2739 /* Frame too big */
2740 if(len > MAXDATAZ + 100)
2741 {
2742#ifdef DEBUG_RX_ERROR
2743 printk(KERN_INFO "%s: wv_start_of_frame: Received frame too large, rfp %d len 0x%x\n",
2744 dev->name, rfp, len);
2745#endif
2746 return(-1);
2747 }
2748
2749 /* Frame too short */
2750 if(len < 7)
2751 {
2752#ifdef DEBUG_RX_ERROR
2753 printk(KERN_INFO "%s: wv_start_of_frame: Received null frame, rfp %d len 0x%x\n",
2754 dev->name, rfp, len);
2755#endif
2756 return(-1);
2757 }
2758
2759 /* Wrap around buffer */
2760 if(len > ((wrap - (rfp - len) + RX_SIZE) % RX_SIZE)) /* magic formula ! */
2761 {
2762#ifdef DEBUG_RX_ERROR
2763 printk(KERN_INFO "%s: wv_start_of_frame: wrap around buffer, wrap %d rfp %d len 0x%x\n",
2764 dev->name, wrap, rfp, len);
2765#endif
2766 return(-1);
2767 }
2768
2769 return((rp - len + RX_SIZE) % RX_SIZE);
2770} /* wv_start_of_frame */
2771
2772/*------------------------------------------------------------------*/
2773/*
2774 * This routine does the actual copy of data (including the ethernet
2775 * header structure) from the WaveLAN card to an sk_buff chain that
2776 * will be passed up to the network interface layer. NOTE: We
2777 * currently don't handle trailer protocols (neither does the rest of
2778 * the network interface), so if that is needed, it will (at least in
2779 * part) be added here. The contents of the receive ring buffer are
2780 * copied to a message chain that is then passed to the kernel.
2781 *
2782 * Note: if any errors occur, the packet is "dropped on the floor"
2783 * (called by wv_packet_rcv())
2784 */
2785static void
2786wv_packet_read(struct net_device * dev,
2787 int fd_p,
2788 int sksize)
2789{
2790 net_local * lp = netdev_priv(dev);
2791 struct sk_buff * skb;
2792
2793#ifdef DEBUG_RX_TRACE
2794 printk(KERN_DEBUG "%s: ->wv_packet_read(0x%X, %d)\n",
2795 dev->name, fd_p, sksize);
2796#endif
2797
2798 /* Allocate some buffer for the new packet */
2799 if((skb = dev_alloc_skb(sksize+2)) == (struct sk_buff *) NULL)
2800 {
2801#ifdef DEBUG_RX_ERROR
2802 printk(KERN_INFO "%s: wv_packet_read(): could not alloc_skb(%d, GFP_ATOMIC)\n",
2803 dev->name, sksize);
2804#endif
2805 dev->stats.rx_dropped++;
2806 /*
2807 * Not only do we want to return here, but we also need to drop the
2808 * packet on the floor to clear the interrupt.
2809 */
2810 return;
2811 }
2812
2813 skb_reserve(skb, 2);
2814 fd_p = read_ringbuf(dev, fd_p, (char *) skb_put(skb, sksize), sksize);
2815 skb->protocol = eth_type_trans(skb, dev);
2816
2817#ifdef DEBUG_RX_INFO
2818 wv_packet_info(skb_mac_header(skb), sksize, dev->name, "wv_packet_read");
2819#endif /* DEBUG_RX_INFO */
2820
2821 /* Statistics gathering & stuff associated.
2822 * It seem a bit messy with all the define, but it's really simple... */
2823 if(
2824#ifdef IW_WIRELESS_SPY
2825 (lp->spy_data.spy_number > 0) ||
2826#endif /* IW_WIRELESS_SPY */
2827#ifdef HISTOGRAM
2828 (lp->his_number > 0) ||
2829#endif /* HISTOGRAM */
2830#ifdef WAVELAN_ROAMING
2831 (do_roaming) ||
2832#endif /* WAVELAN_ROAMING */
2833 0)
2834 {
2835 u_char stats[3]; /* Signal level, Noise level, Signal quality */
2836
2837 /* read signal level, silence level and signal quality bytes */
2838 fd_p = read_ringbuf(dev, (fd_p + 4) % RX_SIZE + RX_BASE,
2839 stats, 3);
2840#ifdef DEBUG_RX_INFO
2841 printk(KERN_DEBUG "%s: wv_packet_read(): Signal level %d/63, Silence level %d/63, signal quality %d/16\n",
2842 dev->name, stats[0] & 0x3F, stats[1] & 0x3F, stats[2] & 0x0F);
2843#endif
2844
2845#ifdef WAVELAN_ROAMING
2846 if(do_roaming)
2847 if(WAVELAN_BEACON(skb->data))
2848 wl_roam_gather(dev, skb->data, stats);
2849#endif /* WAVELAN_ROAMING */
2850
2851#ifdef WIRELESS_SPY
2852 wl_spy_gather(dev, skb_mac_header(skb) + WAVELAN_ADDR_SIZE, stats);
2853#endif /* WIRELESS_SPY */
2854#ifdef HISTOGRAM
2855 wl_his_gather(dev, stats);
2856#endif /* HISTOGRAM */
2857 }
2858
2859 /*
2860 * Hand the packet to the Network Module
2861 */
2862 netif_rx(skb);
2863
2864 /* Keep stats up to date */
2865 dev->stats.rx_packets++;
2866 dev->stats.rx_bytes += sksize;
2867
2868#ifdef DEBUG_RX_TRACE
2869 printk(KERN_DEBUG "%s: <-wv_packet_read()\n", dev->name);
2870#endif
2871 return;
2872}
2873
2874/*------------------------------------------------------------------*/
2875/*
2876 * This routine is called by the interrupt handler to initiate a
2877 * packet transfer from the card to the network interface layer above
2878 * this driver. This routine checks if a buffer has been successfully
2879 * received by the WaveLAN card. If so, the routine wv_packet_read is
2880 * called to do the actual transfer of the card's data including the
2881 * ethernet header into a packet consisting of an sk_buff chain.
2882 * (called by wavelan_interrupt())
2883 * Note : the spinlock is already grabbed for us and irq are disabled.
2884 */
2885static void
2886wv_packet_rcv(struct net_device * dev)
2887{
2888 unsigned int base = dev->base_addr;
2889 net_local * lp = netdev_priv(dev);
2890 int newrfp;
2891 int rp;
2892 int len;
2893 int f_start;
2894 int status;
2895 int i593_rfp;
2896 int stat_ptr;
2897 u_char c[4];
2898
2899#ifdef DEBUG_RX_TRACE
2900 printk(KERN_DEBUG "%s: ->wv_packet_rcv()\n", dev->name);
2901#endif
2902
2903 /* Get the new receive frame pointer from the i82593 chip */
2904 outb(CR0_STATUS_2 | OP0_NOP, LCCR(base));
2905 i593_rfp = inb(LCSR(base));
2906 i593_rfp |= inb(LCSR(base)) << 8;
2907 i593_rfp %= RX_SIZE;
2908
2909 /* Get the new receive frame pointer from the WaveLAN card.
2910 * It is 3 bytes more than the increment of the i82593 receive
2911 * frame pointer, for each packet. This is because it includes the
2912 * 3 roaming bytes added by the mmc.
2913 */
2914 newrfp = inb(RPLL(base));
2915 newrfp |= inb(RPLH(base)) << 8;
2916 newrfp %= RX_SIZE;
2917
2918#ifdef DEBUG_RX_INFO
2919 printk(KERN_DEBUG "%s: wv_packet_rcv(): i593_rfp %d stop %d newrfp %d lp->rfp %d\n",
2920 dev->name, i593_rfp, lp->stop, newrfp, lp->rfp);
2921#endif
2922
2923#ifdef DEBUG_RX_ERROR
2924 /* If no new frame pointer... */
2925 if(lp->overrunning || newrfp == lp->rfp)
2926 printk(KERN_INFO "%s: wv_packet_rcv(): no new frame: i593_rfp %d stop %d newrfp %d lp->rfp %d\n",
2927 dev->name, i593_rfp, lp->stop, newrfp, lp->rfp);
2928#endif
2929
2930 /* Read all frames (packets) received */
2931 while(newrfp != lp->rfp)
2932 {
2933 /* A frame is composed of the packet, followed by a status word,
2934 * the length of the frame (word) and the mmc info (SNR & qual).
2935 * It's because the length is at the end that we can only scan
2936 * frames backward. */
2937
2938 /* Find the first frame by skipping backwards over the frames */
2939 rp = newrfp; /* End of last frame */
2940 while(((f_start = wv_start_of_frame(dev, rp, newrfp)) != lp->rfp) &&
2941 (f_start != -1))
2942 rp = f_start;
2943
2944 /* If we had a problem */
2945 if(f_start == -1)
2946 {
2947#ifdef DEBUG_RX_ERROR
2948 printk(KERN_INFO "wavelan_cs: cannot find start of frame ");
2949 printk(" i593_rfp %d stop %d newrfp %d lp->rfp %d\n",
2950 i593_rfp, lp->stop, newrfp, lp->rfp);
2951#endif
2952 lp->rfp = rp; /* Get to the last usable frame */
2953 continue;
2954 }
2955
2956 /* f_start point to the beggining of the first frame received
2957 * and rp to the beggining of the next one */
2958
2959 /* Read status & length of the frame */
2960 stat_ptr = (rp - 7 + RX_SIZE) % RX_SIZE;
2961 stat_ptr = read_ringbuf(dev, stat_ptr, c, 4);
2962 status = c[0] | (c[1] << 8);
2963 len = c[2] | (c[3] << 8);
2964
2965 /* Check status */
2966 if((status & RX_RCV_OK) != RX_RCV_OK)
2967 {
2968 dev->stats.rx_errors++;
2969 if(status & RX_NO_SFD)
2970 dev->stats.rx_frame_errors++;
2971 if(status & RX_CRC_ERR)
2972 dev->stats.rx_crc_errors++;
2973 if(status & RX_OVRRUN)
2974 dev->stats.rx_over_errors++;
2975
2976#ifdef DEBUG_RX_FAIL
2977 printk(KERN_DEBUG "%s: wv_packet_rcv(): packet not received ok, status = 0x%x\n",
2978 dev->name, status);
2979#endif
2980 }
2981 else
2982 /* Read the packet and transmit to Linux */
2983 wv_packet_read(dev, f_start, len - 2);
2984
2985 /* One frame has been processed, skip it */
2986 lp->rfp = rp;
2987 }
2988
2989 /*
2990 * Update the frame stop register, but set it to less than
2991 * the full 8K to allow space for 3 bytes of signal strength
2992 * per packet.
2993 */
2994 lp->stop = (i593_rfp + RX_SIZE - ((RX_SIZE / 64) * 3)) % RX_SIZE;
2995 outb(OP0_SWIT_TO_PORT_1 | CR0_CHNL, LCCR(base));
2996 outb(CR1_STOP_REG_UPDATE | (lp->stop >> RX_SIZE_SHIFT), LCCR(base));
2997 outb(OP1_SWIT_TO_PORT_0, LCCR(base));
2998
2999#ifdef DEBUG_RX_TRACE
3000 printk(KERN_DEBUG "%s: <-wv_packet_rcv()\n", dev->name);
3001#endif
3002}
3003
3004/*********************** PACKET TRANSMISSION ***********************/
3005/*
3006 * This part deal with sending packet through the wavelan
3007 * We copy the packet to the send buffer and then issue the send
3008 * command to the i82593. The result of this operation will be
3009 * checked in wavelan_interrupt()
3010 */
3011
3012/*------------------------------------------------------------------*/
3013/*
3014 * This routine fills in the appropriate registers and memory
3015 * locations on the WaveLAN card and starts the card off on
3016 * the transmit.
3017 * (called in wavelan_packet_xmit())
3018 */
3019static void
3020wv_packet_write(struct net_device * dev,
3021 void * buf,
3022 short length)
3023{
3024 net_local * lp = netdev_priv(dev);
3025 unsigned int base = dev->base_addr;
3026 unsigned long flags;
3027 int clen = length;
3028 register u_short xmtdata_base = TX_BASE;
3029
3030#ifdef DEBUG_TX_TRACE
3031 printk(KERN_DEBUG "%s: ->wv_packet_write(%d)\n", dev->name, length);
3032#endif
3033
3034 spin_lock_irqsave(&lp->spinlock, flags);
3035
3036 /* Write the length of data buffer followed by the buffer */
3037 outb(xmtdata_base & 0xff, PIORL(base));
3038 outb(((xmtdata_base >> 8) & PIORH_MASK) | PIORH_SEL_TX, PIORH(base));
3039 outb(clen & 0xff, PIOP(base)); /* lsb */
3040 outb(clen >> 8, PIOP(base)); /* msb */
3041
3042 /* Send the data */
3043 outsb(PIOP(base), buf, clen);
3044
3045 /* Indicate end of transmit chain */
3046 outb(OP0_NOP, PIOP(base));
3047 /* josullvn@cs.cmu.edu: need to send a second NOP for alignment... */
3048 outb(OP0_NOP, PIOP(base));
3049
3050 /* Reset the transmit DMA pointer */
3051 hacr_write_slow(base, HACR_PWR_STAT | HACR_TX_DMA_RESET);
3052 hacr_write(base, HACR_DEFAULT);
3053 /* Send the transmit command */
3054 wv_82593_cmd(dev, "wv_packet_write(): transmit",
3055 OP0_TRANSMIT, SR0_NO_RESULT);
3056
3057 /* Make sure the watchdog will keep quiet for a while */
3058 dev->trans_start = jiffies;
3059
3060 /* Keep stats up to date */
3061 dev->stats.tx_bytes += length;
3062
3063 spin_unlock_irqrestore(&lp->spinlock, flags);
3064
3065#ifdef DEBUG_TX_INFO
3066 wv_packet_info((u_char *) buf, length, dev->name, "wv_packet_write");
3067#endif /* DEBUG_TX_INFO */
3068
3069#ifdef DEBUG_TX_TRACE
3070 printk(KERN_DEBUG "%s: <-wv_packet_write()\n", dev->name);
3071#endif
3072}
3073
3074/*------------------------------------------------------------------*/
3075/*
3076 * This routine is called when we want to send a packet (NET3 callback)
3077 * In this routine, we check if the harware is ready to accept
3078 * the packet. We also prevent reentrance. Then, we call the function
3079 * to send the packet...
3080 */
3081static netdev_tx_t
3082wavelan_packet_xmit(struct sk_buff * skb,
3083 struct net_device * dev)
3084{
3085 net_local * lp = netdev_priv(dev);
3086 unsigned long flags;
3087
3088#ifdef DEBUG_TX_TRACE
3089 printk(KERN_DEBUG "%s: ->wavelan_packet_xmit(0x%X)\n", dev->name,
3090 (unsigned) skb);
3091#endif
3092
3093 /*
3094 * Block a timer-based transmit from overlapping a previous transmit.
3095 * In other words, prevent reentering this routine.
3096 */
3097 netif_stop_queue(dev);
3098
3099 /* If somebody has asked to reconfigure the controller,
3100 * we can do it now */
3101 if(lp->reconfig_82593)
3102 {
3103 spin_lock_irqsave(&lp->spinlock, flags); /* Disable interrupts */
3104 wv_82593_config(dev);
3105 spin_unlock_irqrestore(&lp->spinlock, flags); /* Re-enable interrupts */
3106 /* Note : the configure procedure was totally synchronous,
3107 * so the Tx buffer is now free */
3108 }
3109
3110 /* Check if we need some padding */
3111 /* Note : on wireless the propagation time is in the order of 1us,
3112 * and we don't have the Ethernet specific requirement of beeing
3113 * able to detect collisions, therefore in theory we don't really
3114 * need to pad. Jean II */
3115 if (skb_padto(skb, ETH_ZLEN))
3116 return NETDEV_TX_OK;
3117
3118 wv_packet_write(dev, skb->data, skb->len);
3119
3120 dev_kfree_skb(skb);
3121
3122#ifdef DEBUG_TX_TRACE
3123 printk(KERN_DEBUG "%s: <-wavelan_packet_xmit()\n", dev->name);
3124#endif
3125 return NETDEV_TX_OK;
3126}
3127
3128/********************** HARDWARE CONFIGURATION **********************/
3129/*
3130 * This part do the real job of starting and configuring the hardware.
3131 */
3132
3133/*------------------------------------------------------------------*/
3134/*
3135 * Routine to initialize the Modem Management Controller.
3136 * (called by wv_hw_config())
3137 */
3138static int
3139wv_mmc_init(struct net_device * dev)
3140{
3141 unsigned int base = dev->base_addr;
3142 psa_t psa;
3143 mmw_t m;
3144 int configured;
3145 int i; /* Loop counter */
3146
3147#ifdef DEBUG_CONFIG_TRACE
3148 printk(KERN_DEBUG "%s: ->wv_mmc_init()\n", dev->name);
3149#endif
3150
3151 /* Read the parameter storage area */
3152 psa_read(dev, 0, (unsigned char *) &psa, sizeof(psa));
3153
3154 /*
3155 * Check the first three octets of the MAC addr for the manufacturer's code.
3156 * Note: If you get the error message below, you've got a
3157 * non-NCR/AT&T/Lucent PCMCIA cards, see wavelan_cs.h for detail on
3158 * how to configure your card...
3159 */
3160 for (i = 0; i < ARRAY_SIZE(MAC_ADDRESSES); i++)
3161 if ((psa.psa_univ_mac_addr[0] == MAC_ADDRESSES[i][0]) &&
3162 (psa.psa_univ_mac_addr[1] == MAC_ADDRESSES[i][1]) &&
3163 (psa.psa_univ_mac_addr[2] == MAC_ADDRESSES[i][2]))
3164 break;
3165
3166 /* If we have not found it... */
3167 if (i == ARRAY_SIZE(MAC_ADDRESSES))
3168 {
3169#ifdef DEBUG_CONFIG_ERRORS
3170 printk(KERN_WARNING "%s: wv_mmc_init(): Invalid MAC address: %02X:%02X:%02X:...\n",
3171 dev->name, psa.psa_univ_mac_addr[0],
3172 psa.psa_univ_mac_addr[1], psa.psa_univ_mac_addr[2]);
3173#endif
3174 return FALSE;
3175 }
3176
3177 /* Get the MAC address */
3178 memcpy(&dev->dev_addr[0], &psa.psa_univ_mac_addr[0], WAVELAN_ADDR_SIZE);
3179
3180#ifdef USE_PSA_CONFIG
3181 configured = psa.psa_conf_status & 1;
3182#else
3183 configured = 0;
3184#endif
3185
3186 /* Is the PSA is not configured */
3187 if(!configured)
3188 {
3189 /* User will be able to configure NWID after (with iwconfig) */
3190 psa.psa_nwid[0] = 0;
3191 psa.psa_nwid[1] = 0;
3192
3193 /* As NWID is not set : no NWID checking */
3194 psa.psa_nwid_select = 0;
3195
3196 /* Disable encryption */
3197 psa.psa_encryption_select = 0;
3198
3199 /* Set to standard values
3200 * 0x04 for AT,
3201 * 0x01 for MCA,
3202 * 0x04 for PCMCIA and 2.00 card (AT&T 407-024689/E document)
3203 */
3204 if (psa.psa_comp_number & 1)
3205 psa.psa_thr_pre_set = 0x01;
3206 else
3207 psa.psa_thr_pre_set = 0x04;
3208 psa.psa_quality_thr = 0x03;
3209
3210 /* It is configured */
3211 psa.psa_conf_status |= 1;
3212
3213#ifdef USE_PSA_CONFIG
3214 /* Write the psa */
3215 psa_write(dev, (char *)psa.psa_nwid - (char *)&psa,
3216 (unsigned char *)psa.psa_nwid, 4);
3217 psa_write(dev, (char *)&psa.psa_thr_pre_set - (char *)&psa,
3218 (unsigned char *)&psa.psa_thr_pre_set, 1);
3219 psa_write(dev, (char *)&psa.psa_quality_thr - (char *)&psa,
3220 (unsigned char *)&psa.psa_quality_thr, 1);
3221 psa_write(dev, (char *)&psa.psa_conf_status - (char *)&psa,
3222 (unsigned char *)&psa.psa_conf_status, 1);
3223 /* update the Wavelan checksum */
3224 update_psa_checksum(dev);
3225#endif /* USE_PSA_CONFIG */
3226 }
3227
3228 /* Zero the mmc structure */
3229 memset(&m, 0x00, sizeof(m));
3230
3231 /* Copy PSA info to the mmc */
3232 m.mmw_netw_id_l = psa.psa_nwid[1];
3233 m.mmw_netw_id_h = psa.psa_nwid[0];
3234
3235 if(psa.psa_nwid_select & 1)
3236 m.mmw_loopt_sel = 0x00;
3237 else
3238 m.mmw_loopt_sel = MMW_LOOPT_SEL_DIS_NWID;
3239
3240 memcpy(&m.mmw_encr_key, &psa.psa_encryption_key,
3241 sizeof(m.mmw_encr_key));
3242
3243 if(psa.psa_encryption_select)
3244 m.mmw_encr_enable = MMW_ENCR_ENABLE_EN | MMW_ENCR_ENABLE_MODE;
3245 else
3246 m.mmw_encr_enable = 0;
3247
3248 m.mmw_thr_pre_set = psa.psa_thr_pre_set & 0x3F;
3249 m.mmw_quality_thr = psa.psa_quality_thr & 0x0F;
3250
3251 /*
3252 * Set default modem control parameters.
3253 * See NCR document 407-0024326 Rev. A.
3254 */
3255 m.mmw_jabber_enable = 0x01;
3256 m.mmw_anten_sel = MMW_ANTEN_SEL_ALG_EN;
3257 m.mmw_ifs = 0x20;
3258 m.mmw_mod_delay = 0x04;
3259 m.mmw_jam_time = 0x38;
3260
3261 m.mmw_des_io_invert = 0;
3262 m.mmw_freeze = 0;
3263 m.mmw_decay_prm = 0;
3264 m.mmw_decay_updat_prm = 0;
3265
3266 /* Write all info to mmc */
3267 mmc_write(base, 0, (u_char *)&m, sizeof(m));
3268
3269 /* The following code start the modem of the 2.00 frequency
3270 * selectable cards at power on. It's not strictly needed for the
3271 * following boots...
3272 * The original patch was by Joe Finney for the PCMCIA driver, but
3273 * I've cleaned it a bit and add documentation.
3274 * Thanks to Loeke Brederveld from Lucent for the info.
3275 */
3276
3277 /* Attempt to recognise 2.00 cards (2.4 GHz frequency selectable)
3278 * (does it work for everybody ? - especially old cards...) */
3279 /* Note : WFREQSEL verify that it is able to read from EEprom
3280 * a sensible frequency (address 0x00) + that MMR_FEE_STATUS_ID
3281 * is 0xA (Xilinx version) or 0xB (Ariadne version).
3282 * My test is more crude but do work... */
3283 if(!(mmc_in(base, mmroff(0, mmr_fee_status)) &
3284 (MMR_FEE_STATUS_DWLD | MMR_FEE_STATUS_BUSY)))
3285 {
3286 /* We must download the frequency parameters to the
3287 * synthetisers (from the EEprom - area 1)
3288 * Note : as the EEprom is auto decremented, we set the end
3289 * if the area... */
3290 m.mmw_fee_addr = 0x0F;
3291 m.mmw_fee_ctrl = MMW_FEE_CTRL_READ | MMW_FEE_CTRL_DWLD;
3292 mmc_write(base, (char *)&m.mmw_fee_ctrl - (char *)&m,
3293 (unsigned char *)&m.mmw_fee_ctrl, 2);
3294
3295 /* Wait until the download is finished */
3296 fee_wait(base, 100, 100);
3297
3298#ifdef DEBUG_CONFIG_INFO
3299 /* The frequency was in the last word downloaded... */
3300 mmc_read(base, (char *)&m.mmw_fee_data_l - (char *)&m,
3301 (unsigned char *)&m.mmw_fee_data_l, 2);
3302
3303 /* Print some info for the user */
3304 printk(KERN_DEBUG "%s: Wavelan 2.00 recognised (frequency select) : Current frequency = %ld\n",
3305 dev->name,
3306 ((m.mmw_fee_data_h << 4) |
3307 (m.mmw_fee_data_l >> 4)) * 5 / 2 + 24000L);
3308#endif
3309
3310 /* We must now download the power adjust value (gain) to
3311 * the synthetisers (from the EEprom - area 7 - DAC) */
3312 m.mmw_fee_addr = 0x61;
3313 m.mmw_fee_ctrl = MMW_FEE_CTRL_READ | MMW_FEE_CTRL_DWLD;
3314 mmc_write(base, (char *)&m.mmw_fee_ctrl - (char *)&m,
3315 (unsigned char *)&m.mmw_fee_ctrl, 2);
3316
3317 /* Wait until the download is finished */
3318 } /* if 2.00 card */
3319
3320#ifdef DEBUG_CONFIG_TRACE
3321 printk(KERN_DEBUG "%s: <-wv_mmc_init()\n", dev->name);
3322#endif
3323 return TRUE;
3324}
3325
3326/*------------------------------------------------------------------*/
3327/*
3328 * Routine to gracefully turn off reception, and wait for any commands
3329 * to complete.
3330 * (called in wv_ru_start() and wavelan_close() and wavelan_event())
3331 */
3332static int
3333wv_ru_stop(struct net_device * dev)
3334{
3335 unsigned int base = dev->base_addr;
3336 net_local * lp = netdev_priv(dev);
3337 unsigned long flags;
3338 int status;
3339 int spin;
3340
3341#ifdef DEBUG_CONFIG_TRACE
3342 printk(KERN_DEBUG "%s: ->wv_ru_stop()\n", dev->name);
3343#endif
3344
3345 spin_lock_irqsave(&lp->spinlock, flags);
3346
3347 /* First, send the LAN controller a stop receive command */
3348 wv_82593_cmd(dev, "wv_graceful_shutdown(): stop-rcv",
3349 OP0_STOP_RCV, SR0_NO_RESULT);
3350
3351 /* Then, spin until the receive unit goes idle */
3352 spin = 300;
3353 do
3354 {
3355 udelay(10);
3356 outb(OP0_NOP | CR0_STATUS_3, LCCR(base));
3357 status = inb(LCSR(base));
3358 }
3359 while(((status & SR3_RCV_STATE_MASK) != SR3_RCV_IDLE) && (spin-- > 0));
3360
3361 /* Now, spin until the chip finishes executing its current command */
3362 do
3363 {
3364 udelay(10);
3365 outb(OP0_NOP | CR0_STATUS_3, LCCR(base));
3366 status = inb(LCSR(base));
3367 }
3368 while(((status & SR3_EXEC_STATE_MASK) != SR3_EXEC_IDLE) && (spin-- > 0));
3369
3370 spin_unlock_irqrestore(&lp->spinlock, flags);
3371
3372 /* If there was a problem */
3373 if(spin <= 0)
3374 {
3375#ifdef DEBUG_CONFIG_ERRORS
3376 printk(KERN_INFO "%s: wv_ru_stop(): The chip doesn't want to stop...\n",
3377 dev->name);
3378#endif
3379 return FALSE;
3380 }
3381
3382#ifdef DEBUG_CONFIG_TRACE
3383 printk(KERN_DEBUG "%s: <-wv_ru_stop()\n", dev->name);
3384#endif
3385 return TRUE;
3386} /* wv_ru_stop */
3387
3388/*------------------------------------------------------------------*/
3389/*
3390 * This routine starts the receive unit running. First, it checks if
3391 * the card is actually ready. Then the card is instructed to receive
3392 * packets again.
3393 * (called in wv_hw_reset() & wavelan_open())
3394 */
3395static int
3396wv_ru_start(struct net_device * dev)
3397{
3398 unsigned int base = dev->base_addr;
3399 net_local * lp = netdev_priv(dev);
3400 unsigned long flags;
3401
3402#ifdef DEBUG_CONFIG_TRACE
3403 printk(KERN_DEBUG "%s: ->wv_ru_start()\n", dev->name);
3404#endif
3405
3406 /*
3407 * We need to start from a quiescent state. To do so, we could check
3408 * if the card is already running, but instead we just try to shut
3409 * it down. First, we disable reception (in case it was already enabled).
3410 */
3411 if(!wv_ru_stop(dev))
3412 return FALSE;
3413
3414 spin_lock_irqsave(&lp->spinlock, flags);
3415
3416 /* Now we know that no command is being executed. */
3417
3418 /* Set the receive frame pointer and stop pointer */
3419 lp->rfp = 0;
3420 outb(OP0_SWIT_TO_PORT_1 | CR0_CHNL, LCCR(base));
3421
3422 /* Reset ring management. This sets the receive frame pointer to 1 */
3423 outb(OP1_RESET_RING_MNGMT, LCCR(base));
3424
3425#if 0
3426 /* XXX the i82593 manual page 6-4 seems to indicate that the stop register
3427 should be set as below */
3428 /* outb(CR1_STOP_REG_UPDATE|((RX_SIZE - 0x40)>> RX_SIZE_SHIFT),LCCR(base));*/
3429#elif 0
3430 /* but I set it 0 instead */
3431 lp->stop = 0;
3432#else
3433 /* but I set it to 3 bytes per packet less than 8K */
3434 lp->stop = (0 + RX_SIZE - ((RX_SIZE / 64) * 3)) % RX_SIZE;
3435#endif
3436 outb(CR1_STOP_REG_UPDATE | (lp->stop >> RX_SIZE_SHIFT), LCCR(base));
3437 outb(OP1_INT_ENABLE, LCCR(base));
3438 outb(OP1_SWIT_TO_PORT_0, LCCR(base));
3439
3440 /* Reset receive DMA pointer */
3441 hacr_write_slow(base, HACR_PWR_STAT | HACR_TX_DMA_RESET);
3442 hacr_write_slow(base, HACR_DEFAULT);
3443
3444 /* Receive DMA on channel 1 */
3445 wv_82593_cmd(dev, "wv_ru_start(): rcv-enable",
3446 CR0_CHNL | OP0_RCV_ENABLE, SR0_NO_RESULT);
3447
3448#ifdef DEBUG_I82593_SHOW
3449 {
3450 int status;
3451 int opri;
3452 int spin = 10000;
3453
3454 /* spin until the chip starts receiving */
3455 do
3456 {
3457 outb(OP0_NOP | CR0_STATUS_3, LCCR(base));
3458 status = inb(LCSR(base));
3459 if(spin-- <= 0)
3460 break;
3461 }
3462 while(((status & SR3_RCV_STATE_MASK) != SR3_RCV_ACTIVE) &&
3463 ((status & SR3_RCV_STATE_MASK) != SR3_RCV_READY));
3464 printk(KERN_DEBUG "rcv status is 0x%x [i:%d]\n",
3465 (status & SR3_RCV_STATE_MASK), i);
3466 }
3467#endif
3468
3469 spin_unlock_irqrestore(&lp->spinlock, flags);
3470
3471#ifdef DEBUG_CONFIG_TRACE
3472 printk(KERN_DEBUG "%s: <-wv_ru_start()\n", dev->name);
3473#endif
3474 return TRUE;
3475}
3476
3477/*------------------------------------------------------------------*/
3478/*
3479 * This routine does a standard config of the WaveLAN controller (i82593).
3480 * In the ISA driver, this is integrated in wavelan_hardware_reset()
3481 * (called by wv_hw_config(), wv_82593_reconfig() & wavelan_packet_xmit())
3482 */
3483static int
3484wv_82593_config(struct net_device * dev)
3485{
3486 unsigned int base = dev->base_addr;
3487 net_local * lp = netdev_priv(dev);
3488 struct i82593_conf_block cfblk;
3489 int ret = TRUE;
3490
3491#ifdef DEBUG_CONFIG_TRACE
3492 printk(KERN_DEBUG "%s: ->wv_82593_config()\n", dev->name);
3493#endif
3494
3495 /* Create & fill i82593 config block
3496 *
3497 * Now conform to Wavelan document WCIN085B
3498 */
3499 memset(&cfblk, 0x00, sizeof(struct i82593_conf_block));
3500 cfblk.d6mod = FALSE; /* Run in i82593 advanced mode */
3501 cfblk.fifo_limit = 5; /* = 56 B rx and 40 B tx fifo thresholds */
3502 cfblk.forgnesi = FALSE; /* 0=82C501, 1=AMD7992B compatibility */
3503 cfblk.fifo_32 = 1;
3504 cfblk.throttle_enb = FALSE;
3505 cfblk.contin = TRUE; /* enable continuous mode */
3506 cfblk.cntrxint = FALSE; /* enable continuous mode receive interrupts */
3507 cfblk.addr_len = WAVELAN_ADDR_SIZE;
3508 cfblk.acloc = TRUE; /* Disable source addr insertion by i82593 */
3509 cfblk.preamb_len = 0; /* 2 bytes preamble (SFD) */
3510 cfblk.loopback = FALSE;
3511 cfblk.lin_prio = 0; /* conform to 802.3 backoff algorithm */
3512 cfblk.exp_prio = 5; /* conform to 802.3 backoff algorithm */
3513 cfblk.bof_met = 1; /* conform to 802.3 backoff algorithm */
3514 cfblk.ifrm_spc = 0x20 >> 4; /* 32 bit times interframe spacing */
3515 cfblk.slottim_low = 0x20 >> 5; /* 32 bit times slot time */
3516 cfblk.slottim_hi = 0x0;
3517 cfblk.max_retr = 15;
3518 cfblk.prmisc = ((lp->promiscuous) ? TRUE: FALSE); /* Promiscuous mode */
3519 cfblk.bc_dis = FALSE; /* Enable broadcast reception */
3520 cfblk.crs_1 = TRUE; /* Transmit without carrier sense */
3521 cfblk.nocrc_ins = FALSE; /* i82593 generates CRC */
3522 cfblk.crc_1632 = FALSE; /* 32-bit Autodin-II CRC */
3523 cfblk.crs_cdt = FALSE; /* CD not to be interpreted as CS */
3524 cfblk.cs_filter = 0; /* CS is recognized immediately */
3525 cfblk.crs_src = FALSE; /* External carrier sense */
3526 cfblk.cd_filter = 0; /* CD is recognized immediately */
3527 cfblk.min_fr_len = ETH_ZLEN >> 2; /* Minimum frame length 64 bytes */
3528 cfblk.lng_typ = FALSE; /* Length field > 1500 = type field */
3529 cfblk.lng_fld = TRUE; /* Disable 802.3 length field check */
3530 cfblk.rxcrc_xf = TRUE; /* Don't transfer CRC to memory */
3531 cfblk.artx = TRUE; /* Disable automatic retransmission */
3532 cfblk.sarec = TRUE; /* Disable source addr trig of CD */
3533 cfblk.tx_jabber = TRUE; /* Disable jabber jam sequence */
3534 cfblk.hash_1 = FALSE; /* Use bits 0-5 in mc address hash */
3535 cfblk.lbpkpol = TRUE; /* Loopback pin active high */
3536 cfblk.fdx = FALSE; /* Disable full duplex operation */
3537 cfblk.dummy_6 = 0x3f; /* all ones */
3538 cfblk.mult_ia = FALSE; /* No multiple individual addresses */
3539 cfblk.dis_bof = FALSE; /* Disable the backoff algorithm ?! */
3540 cfblk.dummy_1 = TRUE; /* set to 1 */
3541 cfblk.tx_ifs_retrig = 3; /* Hmm... Disabled */
3542#ifdef MULTICAST_ALL
3543 cfblk.mc_all = (lp->allmulticast ? TRUE: FALSE); /* Allow all multicasts */
3544#else
3545 cfblk.mc_all = FALSE; /* No multicast all mode */
3546#endif
3547 cfblk.rcv_mon = 0; /* Monitor mode disabled */
3548 cfblk.frag_acpt = TRUE; /* Do not accept fragments */
3549 cfblk.tstrttrs = FALSE; /* No start transmission threshold */
3550 cfblk.fretx = TRUE; /* FIFO automatic retransmission */
3551 cfblk.syncrqs = FALSE; /* Synchronous DRQ deassertion... */
3552 cfblk.sttlen = TRUE; /* 6 byte status registers */
3553 cfblk.rx_eop = TRUE; /* Signal EOP on packet reception */
3554 cfblk.tx_eop = TRUE; /* Signal EOP on packet transmission */
3555 cfblk.rbuf_size = RX_SIZE>>11; /* Set receive buffer size */
3556 cfblk.rcvstop = TRUE; /* Enable Receive Stop Register */
3557
3558#ifdef DEBUG_I82593_SHOW
3559 print_hex_dump(KERN_DEBUG, "wavelan_cs: config block: ", DUMP_PREFIX_NONE,
3560 16, 1, &cfblk, sizeof(struct i82593_conf_block), false);
3561#endif
3562
3563 /* Copy the config block to the i82593 */
3564 outb(TX_BASE & 0xff, PIORL(base));
3565 outb(((TX_BASE >> 8) & PIORH_MASK) | PIORH_SEL_TX, PIORH(base));
3566 outb(sizeof(struct i82593_conf_block) & 0xff, PIOP(base)); /* lsb */
3567 outb(sizeof(struct i82593_conf_block) >> 8, PIOP(base)); /* msb */
3568 outsb(PIOP(base), (char *) &cfblk, sizeof(struct i82593_conf_block));
3569
3570 /* reset transmit DMA pointer */
3571 hacr_write_slow(base, HACR_PWR_STAT | HACR_TX_DMA_RESET);
3572 hacr_write(base, HACR_DEFAULT);
3573 if(!wv_82593_cmd(dev, "wv_82593_config(): configure",
3574 OP0_CONFIGURE, SR0_CONFIGURE_DONE))
3575 ret = FALSE;
3576
3577 /* Initialize adapter's ethernet MAC address */
3578 outb(TX_BASE & 0xff, PIORL(base));
3579 outb(((TX_BASE >> 8) & PIORH_MASK) | PIORH_SEL_TX, PIORH(base));
3580 outb(WAVELAN_ADDR_SIZE, PIOP(base)); /* byte count lsb */
3581 outb(0, PIOP(base)); /* byte count msb */
3582 outsb(PIOP(base), &dev->dev_addr[0], WAVELAN_ADDR_SIZE);
3583
3584 /* reset transmit DMA pointer */
3585 hacr_write_slow(base, HACR_PWR_STAT | HACR_TX_DMA_RESET);
3586 hacr_write(base, HACR_DEFAULT);
3587 if(!wv_82593_cmd(dev, "wv_82593_config(): ia-setup",
3588 OP0_IA_SETUP, SR0_IA_SETUP_DONE))
3589 ret = FALSE;
3590
3591#ifdef WAVELAN_ROAMING
3592 /* If roaming is enabled, join the "Beacon Request" multicast group... */
3593 /* But only if it's not in there already! */
3594 if(do_roaming)
3595 dev_mc_add(dev,WAVELAN_BEACON_ADDRESS, WAVELAN_ADDR_SIZE, 1);
3596#endif /* WAVELAN_ROAMING */
3597
3598 /* If any multicast address to set */
3599 if(lp->mc_count)
3600 {
3601 struct dev_mc_list * dmi;
3602 int addrs_len = WAVELAN_ADDR_SIZE * lp->mc_count;
3603
3604#ifdef DEBUG_CONFIG_INFO
3605 printk(KERN_DEBUG "%s: wv_hw_config(): set %d multicast addresses:\n",
3606 dev->name, lp->mc_count);
3607 for(dmi=dev->mc_list; dmi; dmi=dmi->next)
3608 printk(KERN_DEBUG " %pM\n", dmi->dmi_addr);
3609#endif
3610
3611 /* Initialize adapter's ethernet multicast addresses */
3612 outb(TX_BASE & 0xff, PIORL(base));
3613 outb(((TX_BASE >> 8) & PIORH_MASK) | PIORH_SEL_TX, PIORH(base));
3614 outb(addrs_len & 0xff, PIOP(base)); /* byte count lsb */
3615 outb((addrs_len >> 8), PIOP(base)); /* byte count msb */
3616 for(dmi=dev->mc_list; dmi; dmi=dmi->next)
3617 outsb(PIOP(base), dmi->dmi_addr, dmi->dmi_addrlen);
3618
3619 /* reset transmit DMA pointer */
3620 hacr_write_slow(base, HACR_PWR_STAT | HACR_TX_DMA_RESET);
3621 hacr_write(base, HACR_DEFAULT);
3622 if(!wv_82593_cmd(dev, "wv_82593_config(): mc-setup",
3623 OP0_MC_SETUP, SR0_MC_SETUP_DONE))
3624 ret = FALSE;
3625 lp->mc_count = dev->mc_count; /* remember to avoid repeated reset */
3626 }
3627
3628 /* Job done, clear the flag */
3629 lp->reconfig_82593 = FALSE;
3630
3631#ifdef DEBUG_CONFIG_TRACE
3632 printk(KERN_DEBUG "%s: <-wv_82593_config()\n", dev->name);
3633#endif
3634 return(ret);
3635}
3636
3637/*------------------------------------------------------------------*/
3638/*
3639 * Read the Access Configuration Register, perform a software reset,
3640 * and then re-enable the card's software.
3641 *
3642 * If I understand correctly : reset the pcmcia interface of the
3643 * wavelan.
3644 * (called by wv_config())
3645 */
3646static int
3647wv_pcmcia_reset(struct net_device * dev)
3648{
3649 int i;
3650 conf_reg_t reg = { 0, CS_READ, CISREG_COR, 0 };
3651 struct pcmcia_device * link = ((net_local *)netdev_priv(dev))->link;
3652
3653#ifdef DEBUG_CONFIG_TRACE
3654 printk(KERN_DEBUG "%s: ->wv_pcmcia_reset()\n", dev->name);
3655#endif
3656
3657 i = pcmcia_access_configuration_register(link, &reg);
3658 if (i != 0)
3659 {
3660 cs_error(link, AccessConfigurationRegister, i);
3661 return FALSE;
3662 }
3663
3664#ifdef DEBUG_CONFIG_INFO
3665 printk(KERN_DEBUG "%s: wavelan_pcmcia_reset(): Config reg is 0x%x\n",
3666 dev->name, (u_int) reg.Value);
3667#endif
3668
3669 reg.Action = CS_WRITE;
3670 reg.Value = reg.Value | COR_SW_RESET;
3671 i = pcmcia_access_configuration_register(link, &reg);
3672 if (i != 0)
3673 {
3674 cs_error(link, AccessConfigurationRegister, i);
3675 return FALSE;
3676 }
3677
3678 reg.Action = CS_WRITE;
3679 reg.Value = COR_LEVEL_IRQ | COR_CONFIG;
3680 i = pcmcia_access_configuration_register(link, &reg);
3681 if (i != 0)
3682 {
3683 cs_error(link, AccessConfigurationRegister, i);
3684 return FALSE;
3685 }
3686
3687#ifdef DEBUG_CONFIG_TRACE
3688 printk(KERN_DEBUG "%s: <-wv_pcmcia_reset()\n", dev->name);
3689#endif
3690 return TRUE;
3691}
3692
3693/*------------------------------------------------------------------*/
3694/*
3695 * wavelan_hw_config() is called after a CARD_INSERTION event is
3696 * received, to configure the wavelan hardware.
3697 * Note that the reception will be enabled in wavelan->open(), so the
3698 * device is configured but idle...
3699 * Performs the following actions:
3700 * 1. A pcmcia software reset (using wv_pcmcia_reset())
3701 * 2. A power reset (reset DMA)
3702 * 3. Reset the LAN controller
3703 * 4. Initialize the radio modem (using wv_mmc_init)
3704 * 5. Configure LAN controller (using wv_82593_config)
3705 * 6. Perform a diagnostic on the LAN controller
3706 * (called by wavelan_event() & wv_hw_reset())
3707 */
3708static int
3709wv_hw_config(struct net_device * dev)
3710{
3711 net_local * lp = netdev_priv(dev);
3712 unsigned int base = dev->base_addr;
3713 unsigned long flags;
3714 int ret = FALSE;
3715
3716#ifdef DEBUG_CONFIG_TRACE
3717 printk(KERN_DEBUG "%s: ->wv_hw_config()\n", dev->name);
3718#endif
3719
3720 /* compile-time check the sizes of structures */
3721 BUILD_BUG_ON(sizeof(psa_t) != PSA_SIZE);
3722 BUILD_BUG_ON(sizeof(mmw_t) != MMW_SIZE);
3723 BUILD_BUG_ON(sizeof(mmr_t) != MMR_SIZE);
3724
3725 /* Reset the pcmcia interface */
3726 if(wv_pcmcia_reset(dev) == FALSE)
3727 return FALSE;
3728
3729 /* Disable interrupts */
3730 spin_lock_irqsave(&lp->spinlock, flags);
3731
3732 /* Disguised goto ;-) */
3733 do
3734 {
3735 /* Power UP the module + reset the modem + reset host adapter
3736 * (in fact, reset DMA channels) */
3737 hacr_write_slow(base, HACR_RESET);
3738 hacr_write(base, HACR_DEFAULT);
3739
3740 /* Check if the module has been powered up... */
3741 if(hasr_read(base) & HASR_NO_CLK)
3742 {
3743#ifdef DEBUG_CONFIG_ERRORS
3744 printk(KERN_WARNING "%s: wv_hw_config(): modem not connected or not a wavelan card\n",
3745 dev->name);
3746#endif
3747 break;
3748 }
3749
3750 /* initialize the modem */
3751 if(wv_mmc_init(dev) == FALSE)
3752 {
3753#ifdef DEBUG_CONFIG_ERRORS
3754 printk(KERN_WARNING "%s: wv_hw_config(): Can't configure the modem\n",
3755 dev->name);
3756#endif
3757 break;
3758 }
3759
3760 /* reset the LAN controller (i82593) */
3761 outb(OP0_RESET, LCCR(base));
3762 mdelay(1); /* A bit crude ! */
3763
3764 /* Initialize the LAN controller */
3765 if(wv_82593_config(dev) == FALSE)
3766 {
3767#ifdef DEBUG_CONFIG_ERRORS
3768 printk(KERN_INFO "%s: wv_hw_config(): i82593 init failed\n",
3769 dev->name);
3770#endif
3771 break;
3772 }
3773
3774 /* Diagnostic */
3775 if(wv_diag(dev) == FALSE)
3776 {
3777#ifdef DEBUG_CONFIG_ERRORS
3778 printk(KERN_INFO "%s: wv_hw_config(): i82593 diagnostic failed\n",
3779 dev->name);
3780#endif
3781 break;
3782 }
3783
3784 /*
3785 * insert code for loopback test here
3786 */
3787
3788 /* The device is now configured */
3789 lp->configured = 1;
3790 ret = TRUE;
3791 }
3792 while(0);
3793
3794 /* Re-enable interrupts */
3795 spin_unlock_irqrestore(&lp->spinlock, flags);
3796
3797#ifdef DEBUG_CONFIG_TRACE
3798 printk(KERN_DEBUG "%s: <-wv_hw_config()\n", dev->name);
3799#endif
3800 return(ret);
3801}
3802
3803/*------------------------------------------------------------------*/
3804/*
3805 * Totally reset the wavelan and restart it.
3806 * Performs the following actions:
3807 * 1. Call wv_hw_config()
3808 * 2. Start the LAN controller's receive unit
3809 * (called by wavelan_event(), wavelan_watchdog() and wavelan_open())
3810 */
3811static void
3812wv_hw_reset(struct net_device * dev)
3813{
3814 net_local * lp = netdev_priv(dev);
3815
3816#ifdef DEBUG_CONFIG_TRACE
3817 printk(KERN_DEBUG "%s: ->wv_hw_reset()\n", dev->name);
3818#endif
3819
3820 lp->nresets++;
3821 lp->configured = 0;
3822
3823 /* Call wv_hw_config() for most of the reset & init stuff */
3824 if(wv_hw_config(dev) == FALSE)
3825 return;
3826
3827 /* start receive unit */
3828 wv_ru_start(dev);
3829
3830#ifdef DEBUG_CONFIG_TRACE
3831 printk(KERN_DEBUG "%s: <-wv_hw_reset()\n", dev->name);
3832#endif
3833}
3834
3835/*------------------------------------------------------------------*/
3836/*
3837 * wv_pcmcia_config() is called after a CARD_INSERTION event is
3838 * received, to configure the PCMCIA socket, and to make the ethernet
3839 * device available to the system.
3840 * (called by wavelan_event())
3841 */
3842static int
3843wv_pcmcia_config(struct pcmcia_device * link)
3844{
3845 struct net_device * dev = (struct net_device *) link->priv;
3846 int i;
3847 win_req_t req;
3848 memreq_t mem;
3849 net_local * lp = netdev_priv(dev);
3850
3851
3852#ifdef DEBUG_CONFIG_TRACE
3853 printk(KERN_DEBUG "->wv_pcmcia_config(0x%p)\n", link);
3854#endif
3855
3856 do
3857 {
3858 i = pcmcia_request_io(link, &link->io);
3859 if (i != 0)
3860 {
3861 cs_error(link, RequestIO, i);
3862 break;
3863 }
3864
3865 /*
3866 * Now allocate an interrupt line. Note that this does not
3867 * actually assign a handler to the interrupt.
3868 */
3869 i = pcmcia_request_irq(link, &link->irq);
3870 if (i != 0)
3871 {
3872 cs_error(link, RequestIRQ, i);
3873 break;
3874 }
3875
3876 /*
3877 * This actually configures the PCMCIA socket -- setting up
3878 * the I/O windows and the interrupt mapping.
3879 */
3880 link->conf.ConfigIndex = 1;
3881 i = pcmcia_request_configuration(link, &link->conf);
3882 if (i != 0)
3883 {
3884 cs_error(link, RequestConfiguration, i);
3885 break;
3886 }
3887
3888 /*
3889 * Allocate a small memory window. Note that the struct pcmcia_device
3890 * structure provides space for one window handle -- if your
3891 * device needs several windows, you'll need to keep track of
3892 * the handles in your private data structure, link->priv.
3893 */
3894 req.Attributes = WIN_DATA_WIDTH_8|WIN_MEMORY_TYPE_AM|WIN_ENABLE;
3895 req.Base = req.Size = 0;
3896 req.AccessSpeed = mem_speed;
3897 i = pcmcia_request_window(&link, &req, &link->win);
3898 if (i != 0)
3899 {
3900 cs_error(link, RequestWindow, i);
3901 break;
3902 }
3903
3904 lp->mem = ioremap(req.Base, req.Size);
3905 dev->mem_start = (u_long)lp->mem;
3906 dev->mem_end = dev->mem_start + req.Size;
3907
3908 mem.CardOffset = 0; mem.Page = 0;
3909 i = pcmcia_map_mem_page(link->win, &mem);
3910 if (i != 0)
3911 {
3912 cs_error(link, MapMemPage, i);
3913 break;
3914 }
3915
3916 /* Feed device with this info... */
3917 dev->irq = link->irq.AssignedIRQ;
3918 dev->base_addr = link->io.BasePort1;
3919 netif_start_queue(dev);
3920
3921#ifdef DEBUG_CONFIG_INFO
3922 printk(KERN_DEBUG "wv_pcmcia_config: MEMSTART %p IRQ %d IOPORT 0x%x\n",
3923 lp->mem, dev->irq, (u_int) dev->base_addr);
3924#endif
3925
3926 SET_NETDEV_DEV(dev, &handle_to_dev(link));
3927 i = register_netdev(dev);
3928 if(i != 0)
3929 {
3930#ifdef DEBUG_CONFIG_ERRORS
3931 printk(KERN_INFO "wv_pcmcia_config(): register_netdev() failed\n");
3932#endif
3933 break;
3934 }
3935 }
3936 while(0); /* Humm... Disguised goto !!! */
3937
3938 /* If any step failed, release any partially configured state */
3939 if(i != 0)
3940 {
3941 wv_pcmcia_release(link);
3942 return FALSE;
3943 }
3944
3945 strcpy(((net_local *) netdev_priv(dev))->node.dev_name, dev->name);
3946 link->dev_node = &((net_local *) netdev_priv(dev))->node;
3947
3948#ifdef DEBUG_CONFIG_TRACE
3949 printk(KERN_DEBUG "<-wv_pcmcia_config()\n");
3950#endif
3951 return TRUE;
3952}
3953
3954/*------------------------------------------------------------------*/
3955/*
3956 * After a card is removed, wv_pcmcia_release() will unregister the net
3957 * device, and release the PCMCIA configuration. If the device is
3958 * still open, this will be postponed until it is closed.
3959 */
3960static void
3961wv_pcmcia_release(struct pcmcia_device *link)
3962{
3963 struct net_device * dev = (struct net_device *) link->priv;
3964 net_local * lp = netdev_priv(dev);
3965
3966#ifdef DEBUG_CONFIG_TRACE
3967 printk(KERN_DEBUG "%s: -> wv_pcmcia_release(0x%p)\n", dev->name, link);
3968#endif
3969
3970 iounmap(lp->mem);
3971 pcmcia_disable_device(link);
3972
3973#ifdef DEBUG_CONFIG_TRACE
3974 printk(KERN_DEBUG "%s: <- wv_pcmcia_release()\n", dev->name);
3975#endif
3976}
3977
3978/************************ INTERRUPT HANDLING ************************/
3979
3980/*
3981 * This function is the interrupt handler for the WaveLAN card. This
3982 * routine will be called whenever:
3983 * 1. A packet is received.
3984 * 2. A packet has successfully been transferred and the unit is
3985 * ready to transmit another packet.
3986 * 3. A command has completed execution.
3987 */
3988static irqreturn_t
3989wavelan_interrupt(int irq,
3990 void * dev_id)
3991{
3992 struct net_device * dev = dev_id;
3993 net_local * lp;
3994 unsigned int base;
3995 int status0;
3996 u_int tx_status;
3997
3998#ifdef DEBUG_INTERRUPT_TRACE
3999 printk(KERN_DEBUG "%s: ->wavelan_interrupt()\n", dev->name);
4000#endif
4001
4002 lp = netdev_priv(dev);
4003 base = dev->base_addr;
4004
4005#ifdef DEBUG_INTERRUPT_INFO
4006 /* Check state of our spinlock (it should be cleared) */
4007 if(spin_is_locked(&lp->spinlock))
4008 printk(KERN_DEBUG
4009 "%s: wavelan_interrupt(): spinlock is already locked !!!\n",
4010 dev->name);
4011#endif
4012
4013 /* Prevent reentrancy. We need to do that because we may have
4014 * multiple interrupt handler running concurently.
4015 * It is safe because interrupts are disabled before aquiring
4016 * the spinlock. */
4017 spin_lock(&lp->spinlock);
4018
4019 /* Treat all pending interrupts */
4020 while(1)
4021 {
4022 /* ---------------- INTERRUPT CHECKING ---------------- */
4023 /*
4024 * Look for the interrupt and verify the validity
4025 */
4026 outb(CR0_STATUS_0 | OP0_NOP, LCCR(base));
4027 status0 = inb(LCSR(base));
4028
4029#ifdef DEBUG_INTERRUPT_INFO
4030 printk(KERN_DEBUG "status0 0x%x [%s => 0x%x]", status0,
4031 (status0&SR0_INTERRUPT)?"int":"no int",status0&~SR0_INTERRUPT);
4032 if(status0&SR0_INTERRUPT)
4033 {
4034 printk(" [%s => %d]\n", (status0 & SR0_CHNL) ? "chnl" :
4035 ((status0 & SR0_EXECUTION) ? "cmd" :
4036 ((status0 & SR0_RECEPTION) ? "recv" : "unknown")),
4037 (status0 & SR0_EVENT_MASK));
4038 }
4039 else
4040 printk("\n");
4041#endif
4042
4043 /* Return if no actual interrupt from i82593 (normal exit) */
4044 if(!(status0 & SR0_INTERRUPT))
4045 break;
4046
4047 /* If interrupt is both Rx and Tx or none...
4048 * This code in fact is there to catch the spurious interrupt
4049 * when you remove the wavelan pcmcia card from the socket */
4050 if(((status0 & SR0_BOTH_RX_TX) == SR0_BOTH_RX_TX) ||
4051 ((status0 & SR0_BOTH_RX_TX) == 0x0))
4052 {
4053#ifdef DEBUG_INTERRUPT_INFO
4054 printk(KERN_INFO "%s: wv_interrupt(): bogus interrupt (or from dead card) : %X\n",
4055 dev->name, status0);
4056#endif
4057 /* Acknowledge the interrupt */
4058 outb(CR0_INT_ACK | OP0_NOP, LCCR(base));
4059 break;
4060 }
4061
4062 /* ----------------- RECEIVING PACKET ----------------- */
4063 /*
4064 * When the wavelan signal the reception of a new packet,
4065 * we call wv_packet_rcv() to copy if from the buffer and
4066 * send it to NET3
4067 */
4068 if(status0 & SR0_RECEPTION)
4069 {
4070#ifdef DEBUG_INTERRUPT_INFO
4071 printk(KERN_DEBUG "%s: wv_interrupt(): receive\n", dev->name);
4072#endif
4073
4074 if((status0 & SR0_EVENT_MASK) == SR0_STOP_REG_HIT)
4075 {
4076#ifdef DEBUG_INTERRUPT_ERROR
4077 printk(KERN_INFO "%s: wv_interrupt(): receive buffer overflow\n",
4078 dev->name);
4079#endif
4080 dev->stats.rx_over_errors++;
4081 lp->overrunning = 1;
4082 }
4083
4084 /* Get the packet */
4085 wv_packet_rcv(dev);
4086 lp->overrunning = 0;
4087
4088 /* Acknowledge the interrupt */
4089 outb(CR0_INT_ACK | OP0_NOP, LCCR(base));
4090 continue;
4091 }
4092
4093 /* ---------------- COMMAND COMPLETION ---------------- */
4094 /*
4095 * Interrupts issued when the i82593 has completed a command.
4096 * Most likely : transmission done
4097 */
4098
4099 /* If a transmission has been done */
4100 if((status0 & SR0_EVENT_MASK) == SR0_TRANSMIT_DONE ||
4101 (status0 & SR0_EVENT_MASK) == SR0_RETRANSMIT_DONE ||
4102 (status0 & SR0_EVENT_MASK) == SR0_TRANSMIT_NO_CRC_DONE)
4103 {
4104#ifdef DEBUG_TX_ERROR
4105 if((status0 & SR0_EVENT_MASK) == SR0_TRANSMIT_NO_CRC_DONE)
4106 printk(KERN_INFO "%s: wv_interrupt(): packet transmitted without CRC.\n",
4107 dev->name);
4108#endif
4109
4110 /* Get transmission status */
4111 tx_status = inb(LCSR(base));
4112 tx_status |= (inb(LCSR(base)) << 8);
4113#ifdef DEBUG_INTERRUPT_INFO
4114 printk(KERN_DEBUG "%s: wv_interrupt(): transmission done\n",
4115 dev->name);
4116 {
4117 u_int rcv_bytes;
4118 u_char status3;
4119 rcv_bytes = inb(LCSR(base));
4120 rcv_bytes |= (inb(LCSR(base)) << 8);
4121 status3 = inb(LCSR(base));
4122 printk(KERN_DEBUG "tx_status 0x%02x rcv_bytes 0x%02x status3 0x%x\n",
4123 tx_status, rcv_bytes, (u_int) status3);
4124 }
4125#endif
4126 /* Check for possible errors */
4127 if((tx_status & TX_OK) != TX_OK)
4128 {
4129 dev->stats.tx_errors++;
4130
4131 if(tx_status & TX_FRTL)
4132 {
4133#ifdef DEBUG_TX_ERROR
4134 printk(KERN_INFO "%s: wv_interrupt(): frame too long\n",
4135 dev->name);
4136#endif
4137 }
4138 if(tx_status & TX_UND_RUN)
4139 {
4140#ifdef DEBUG_TX_FAIL
4141 printk(KERN_DEBUG "%s: wv_interrupt(): DMA underrun\n",
4142 dev->name);
4143#endif
4144 dev->stats.tx_aborted_errors++;
4145 }
4146 if(tx_status & TX_LOST_CTS)
4147 {
4148#ifdef DEBUG_TX_FAIL
4149 printk(KERN_DEBUG "%s: wv_interrupt(): no CTS\n", dev->name);
4150#endif
4151 dev->stats.tx_carrier_errors++;
4152 }
4153 if(tx_status & TX_LOST_CRS)
4154 {
4155#ifdef DEBUG_TX_FAIL
4156 printk(KERN_DEBUG "%s: wv_interrupt(): no carrier\n",
4157 dev->name);
4158#endif
4159 dev->stats.tx_carrier_errors++;
4160 }
4161 if(tx_status & TX_HRT_BEAT)
4162 {
4163#ifdef DEBUG_TX_FAIL
4164 printk(KERN_DEBUG "%s: wv_interrupt(): heart beat\n", dev->name);
4165#endif
4166 dev->stats.tx_heartbeat_errors++;
4167 }
4168 if(tx_status & TX_DEFER)
4169 {
4170#ifdef DEBUG_TX_FAIL
4171 printk(KERN_DEBUG "%s: wv_interrupt(): channel jammed\n",
4172 dev->name);
4173#endif
4174 }
4175 /* Ignore late collisions since they're more likely to happen
4176 * here (the WaveLAN design prevents the LAN controller from
4177 * receiving while it is transmitting). We take action only when
4178 * the maximum retransmit attempts is exceeded.
4179 */
4180 if(tx_status & TX_COLL)
4181 {
4182 if(tx_status & TX_MAX_COL)
4183 {
4184#ifdef DEBUG_TX_FAIL
4185 printk(KERN_DEBUG "%s: wv_interrupt(): channel congestion\n",
4186 dev->name);
4187#endif
4188 if(!(tx_status & TX_NCOL_MASK))
4189 {
4190 dev->stats.collisions += 0x10;
4191 }
4192 }
4193 }
4194 } /* if(!(tx_status & TX_OK)) */
4195
4196 dev->stats.collisions += (tx_status & TX_NCOL_MASK);
4197 dev->stats.tx_packets++;
4198
4199 netif_wake_queue(dev);
4200 outb(CR0_INT_ACK | OP0_NOP, LCCR(base)); /* Acknowledge the interrupt */
4201 }
4202 else /* if interrupt = transmit done or retransmit done */
4203 {
4204#ifdef DEBUG_INTERRUPT_ERROR
4205 printk(KERN_INFO "wavelan_cs: unknown interrupt, status0 = %02x\n",
4206 status0);
4207#endif
4208 outb(CR0_INT_ACK | OP0_NOP, LCCR(base)); /* Acknowledge the interrupt */
4209 }
4210 } /* while(1) */
4211
4212 spin_unlock(&lp->spinlock);
4213
4214#ifdef DEBUG_INTERRUPT_TRACE
4215 printk(KERN_DEBUG "%s: <-wavelan_interrupt()\n", dev->name);
4216#endif
4217
4218 /* We always return IRQ_HANDLED, because we will receive empty
4219 * interrupts under normal operations. Anyway, it doesn't matter
4220 * as we are dealing with an ISA interrupt that can't be shared.
4221 *
4222 * Explanation : under heavy receive, the following happens :
4223 * ->wavelan_interrupt()
4224 * (status0 & SR0_INTERRUPT) != 0
4225 * ->wv_packet_rcv()
4226 * (status0 & SR0_INTERRUPT) != 0
4227 * ->wv_packet_rcv()
4228 * (status0 & SR0_INTERRUPT) == 0 // i.e. no more event
4229 * <-wavelan_interrupt()
4230 * ->wavelan_interrupt()
4231 * (status0 & SR0_INTERRUPT) == 0 // i.e. empty interrupt
4232 * <-wavelan_interrupt()
4233 * Jean II */
4234 return IRQ_HANDLED;
4235} /* wv_interrupt */
4236
4237/*------------------------------------------------------------------*/
4238/*
4239 * Watchdog: when we start a transmission, a timer is set for us in the
4240 * kernel. If the transmission completes, this timer is disabled. If
4241 * the timer expires, we are called and we try to unlock the hardware.
4242 *
4243 * Note : This watchdog is move clever than the one in the ISA driver,
4244 * because it try to abort the current command before reseting
4245 * everything...
4246 * On the other hand, it's a bit simpler, because we don't have to
4247 * deal with the multiple Tx buffers...
4248 */
4249static void
4250wavelan_watchdog(struct net_device * dev)
4251{
4252 net_local * lp = netdev_priv(dev);
4253 unsigned int base = dev->base_addr;
4254 unsigned long flags;
4255 int aborted = FALSE;
4256
4257#ifdef DEBUG_INTERRUPT_TRACE
4258 printk(KERN_DEBUG "%s: ->wavelan_watchdog()\n", dev->name);
4259#endif
4260
4261#ifdef DEBUG_INTERRUPT_ERROR
4262 printk(KERN_INFO "%s: wavelan_watchdog: watchdog timer expired\n",
4263 dev->name);
4264#endif
4265
4266 spin_lock_irqsave(&lp->spinlock, flags);
4267
4268 /* Ask to abort the current command */
4269 outb(OP0_ABORT, LCCR(base));
4270
4271 /* Wait for the end of the command (a bit hackish) */
4272 if(wv_82593_cmd(dev, "wavelan_watchdog(): abort",
4273 OP0_NOP | CR0_STATUS_3, SR0_EXECUTION_ABORTED))
4274 aborted = TRUE;
4275
4276 /* Release spinlock here so that wv_hw_reset() can grab it */
4277 spin_unlock_irqrestore(&lp->spinlock, flags);
4278
4279 /* Check if we were successful in aborting it */
4280 if(!aborted)
4281 {
4282 /* It seem that it wasn't enough */
4283#ifdef DEBUG_INTERRUPT_ERROR
4284 printk(KERN_INFO "%s: wavelan_watchdog: abort failed, trying reset\n",
4285 dev->name);
4286#endif
4287 wv_hw_reset(dev);
4288 }
4289
4290#ifdef DEBUG_PSA_SHOW
4291 {
4292 psa_t psa;
4293 psa_read(dev, 0, (unsigned char *) &psa, sizeof(psa));
4294 wv_psa_show(&psa);
4295 }
4296#endif
4297#ifdef DEBUG_MMC_SHOW
4298 wv_mmc_show(dev);
4299#endif
4300#ifdef DEBUG_I82593_SHOW
4301 wv_ru_show(dev);
4302#endif
4303
4304 /* We are no more waiting for something... */
4305 netif_wake_queue(dev);
4306
4307#ifdef DEBUG_INTERRUPT_TRACE
4308 printk(KERN_DEBUG "%s: <-wavelan_watchdog()\n", dev->name);
4309#endif
4310}
4311
4312/********************* CONFIGURATION CALLBACKS *********************/
4313/*
4314 * Here are the functions called by the pcmcia package (cardmgr) and
4315 * linux networking (NET3) for initialization, configuration and
4316 * deinstallations of the Wavelan Pcmcia Hardware.
4317 */
4318
4319/*------------------------------------------------------------------*/
4320/*
4321 * Configure and start up the WaveLAN PCMCIA adaptor.
4322 * Called by NET3 when it "open" the device.
4323 */
4324static int
4325wavelan_open(struct net_device * dev)
4326{
4327 net_local * lp = netdev_priv(dev);
4328 struct pcmcia_device * link = lp->link;
4329 unsigned int base = dev->base_addr;
4330
4331#ifdef DEBUG_CALLBACK_TRACE
4332 printk(KERN_DEBUG "%s: ->wavelan_open(dev=0x%x)\n", dev->name,
4333 (unsigned int) dev);
4334#endif
4335
4336 /* Check if the modem is powered up (wavelan_close() power it down */
4337 if(hasr_read(base) & HASR_NO_CLK)
4338 {
4339 /* Power up (power up time is 250us) */
4340 hacr_write(base, HACR_DEFAULT);
4341
4342 /* Check if the module has been powered up... */
4343 if(hasr_read(base) & HASR_NO_CLK)
4344 {
4345#ifdef DEBUG_CONFIG_ERRORS
4346 printk(KERN_WARNING "%s: wavelan_open(): modem not connected\n",
4347 dev->name);
4348#endif
4349 return FALSE;
4350 }
4351 }
4352
4353 /* Start reception and declare the driver ready */
4354 if(!lp->configured)
4355 return FALSE;
4356 if(!wv_ru_start(dev))
4357 wv_hw_reset(dev); /* If problem : reset */
4358 netif_start_queue(dev);
4359
4360 /* Mark the device as used */
4361 link->open++;
4362
4363#ifdef WAVELAN_ROAMING
4364 if(do_roaming)
4365 wv_roam_init(dev);
4366#endif /* WAVELAN_ROAMING */
4367
4368#ifdef DEBUG_CALLBACK_TRACE
4369 printk(KERN_DEBUG "%s: <-wavelan_open()\n", dev->name);
4370#endif
4371 return 0;
4372}
4373
4374/*------------------------------------------------------------------*/
4375/*
4376 * Shutdown the WaveLAN PCMCIA adaptor.
4377 * Called by NET3 when it "close" the device.
4378 */
4379static int
4380wavelan_close(struct net_device * dev)
4381{
4382 struct pcmcia_device * link = ((net_local *)netdev_priv(dev))->link;
4383 unsigned int base = dev->base_addr;
4384
4385#ifdef DEBUG_CALLBACK_TRACE
4386 printk(KERN_DEBUG "%s: ->wavelan_close(dev=0x%x)\n", dev->name,
4387 (unsigned int) dev);
4388#endif
4389
4390 /* If the device isn't open, then nothing to do */
4391 if(!link->open)
4392 {
4393#ifdef DEBUG_CONFIG_INFO
4394 printk(KERN_DEBUG "%s: wavelan_close(): device not open\n", dev->name);
4395#endif
4396 return 0;
4397 }
4398
4399#ifdef WAVELAN_ROAMING
4400 /* Cleanup of roaming stuff... */
4401 if(do_roaming)
4402 wv_roam_cleanup(dev);
4403#endif /* WAVELAN_ROAMING */
4404
4405 link->open--;
4406
4407 /* If the card is still present */
4408 if(netif_running(dev))
4409 {
4410 netif_stop_queue(dev);
4411
4412 /* Stop receiving new messages and wait end of transmission */
4413 wv_ru_stop(dev);
4414
4415 /* Power down the module */
4416 hacr_write(base, HACR_DEFAULT & (~HACR_PWR_STAT));
4417 }
4418
4419#ifdef DEBUG_CALLBACK_TRACE
4420 printk(KERN_DEBUG "%s: <-wavelan_close()\n", dev->name);
4421#endif
4422 return 0;
4423}
4424
4425static const struct net_device_ops wavelan_netdev_ops = {
4426 .ndo_open = wavelan_open,
4427 .ndo_stop = wavelan_close,
4428 .ndo_start_xmit = wavelan_packet_xmit,
4429 .ndo_set_multicast_list = wavelan_set_multicast_list,
4430#ifdef SET_MAC_ADDRESS
4431 .ndo_set_mac_address = wavelan_set_mac_address,
4432#endif
4433 .ndo_tx_timeout = wavelan_watchdog,
4434 .ndo_change_mtu = eth_change_mtu,
4435 .ndo_validate_addr = eth_validate_addr,
4436};
4437
4438/*------------------------------------------------------------------*/
4439/*
4440 * wavelan_attach() creates an "instance" of the driver, allocating
4441 * local data structures for one device (one interface). The device
4442 * is registered with Card Services.
4443 *
4444 * The dev_link structure is initialized, but we don't actually
4445 * configure the card at this point -- we wait until we receive a
4446 * card insertion event.
4447 */
4448static int
4449wavelan_probe(struct pcmcia_device *p_dev)
4450{
4451 struct net_device * dev; /* Interface generic data */
4452 net_local * lp; /* Interface specific data */
4453 int ret;
4454
4455#ifdef DEBUG_CALLBACK_TRACE
4456 printk(KERN_DEBUG "-> wavelan_attach()\n");
4457#endif
4458
4459 /* The io structure describes IO port mapping */
4460 p_dev->io.NumPorts1 = 8;
4461 p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
4462 p_dev->io.IOAddrLines = 3;
4463
4464 /* Interrupt setup */
4465 p_dev->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING | IRQ_HANDLE_PRESENT;
4466 p_dev->irq.IRQInfo1 = IRQ_LEVEL_ID;
4467 p_dev->irq.Handler = wavelan_interrupt;
4468
4469 /* General socket configuration */
4470 p_dev->conf.Attributes = CONF_ENABLE_IRQ;
4471 p_dev->conf.IntType = INT_MEMORY_AND_IO;
4472
4473 /* Allocate the generic data structure */
4474 dev = alloc_etherdev(sizeof(net_local));
4475 if (!dev)
4476 return -ENOMEM;
4477
4478 p_dev->priv = p_dev->irq.Instance = dev;
4479
4480 lp = netdev_priv(dev);
4481
4482 /* Init specific data */
4483 lp->configured = 0;
4484 lp->reconfig_82593 = FALSE;
4485 lp->nresets = 0;
4486 /* Multicast stuff */
4487 lp->promiscuous = 0;
4488 lp->allmulticast = 0;
4489 lp->mc_count = 0;
4490
4491 /* Init spinlock */
4492 spin_lock_init(&lp->spinlock);
4493
4494 /* back links */
4495 lp->dev = dev;
4496
4497 /* wavelan NET3 callbacks */
4498 dev->netdev_ops = &wavelan_netdev_ops;
4499 dev->watchdog_timeo = WATCHDOG_JIFFIES;
4500 SET_ETHTOOL_OPS(dev, &ops);
4501
4502 dev->wireless_handlers = &wavelan_handler_def;
4503 lp->wireless_data.spy_data = &lp->spy_data;
4504 dev->wireless_data = &lp->wireless_data;
4505
4506 /* Other specific data */
4507 dev->mtu = WAVELAN_MTU;
4508
4509 ret = wv_pcmcia_config(p_dev);
4510 if (ret)
4511 return ret;
4512
4513 ret = wv_hw_config(dev);
4514 if (ret) {
4515 dev->irq = 0;
4516 pcmcia_disable_device(p_dev);
4517 return ret;
4518 }
4519
4520 wv_init_info(dev);
4521
4522#ifdef DEBUG_CALLBACK_TRACE
4523 printk(KERN_DEBUG "<- wavelan_attach()\n");
4524#endif
4525
4526 return 0;
4527}
4528
4529/*------------------------------------------------------------------*/
4530/*
4531 * This deletes a driver "instance". The device is de-registered with
4532 * Card Services. If it has been released, all local data structures
4533 * are freed. Otherwise, the structures will be freed when the device
4534 * is released.
4535 */
4536static void
4537wavelan_detach(struct pcmcia_device *link)
4538{
4539#ifdef DEBUG_CALLBACK_TRACE
4540 printk(KERN_DEBUG "-> wavelan_detach(0x%p)\n", link);
4541#endif
4542
4543 /* Some others haven't done their job : give them another chance */
4544 wv_pcmcia_release(link);
4545
4546 /* Free pieces */
4547 if(link->priv)
4548 {
4549 struct net_device * dev = (struct net_device *) link->priv;
4550
4551 /* Remove ourselves from the kernel list of ethernet devices */
4552 /* Warning : can't be called from interrupt, timer or wavelan_close() */
4553 if (link->dev_node)
4554 unregister_netdev(dev);
4555 link->dev_node = NULL;
4556 ((net_local *)netdev_priv(dev))->link = NULL;
4557 ((net_local *)netdev_priv(dev))->dev = NULL;
4558 free_netdev(dev);
4559 }
4560
4561#ifdef DEBUG_CALLBACK_TRACE
4562 printk(KERN_DEBUG "<- wavelan_detach()\n");
4563#endif
4564}
4565
4566static int wavelan_suspend(struct pcmcia_device *link)
4567{
4568 struct net_device * dev = (struct net_device *) link->priv;
4569
4570 /* NB: wavelan_close will be called, but too late, so we are
4571 * obliged to close nicely the wavelan here. David, could you
4572 * close the device before suspending them ? And, by the way,
4573 * could you, on resume, add a "route add -net ..." after the
4574 * ifconfig up ? Thanks... */
4575
4576 /* Stop receiving new messages and wait end of transmission */
4577 wv_ru_stop(dev);
4578
4579 if (link->open)
4580 netif_device_detach(dev);
4581
4582 /* Power down the module */
4583 hacr_write(dev->base_addr, HACR_DEFAULT & (~HACR_PWR_STAT));
4584
4585 return 0;
4586}
4587
4588static int wavelan_resume(struct pcmcia_device *link)
4589{
4590 struct net_device * dev = (struct net_device *) link->priv;
4591
4592 if (link->open) {
4593 wv_hw_reset(dev);
4594 netif_device_attach(dev);
4595 }
4596
4597 return 0;
4598}
4599
4600
4601static struct pcmcia_device_id wavelan_ids[] = {
4602 PCMCIA_DEVICE_PROD_ID12("AT&T","WaveLAN/PCMCIA", 0xe7c5affd, 0x1bc50975),
4603 PCMCIA_DEVICE_PROD_ID12("Digital", "RoamAbout/DS", 0x9999ab35, 0x00d05e06),
4604 PCMCIA_DEVICE_PROD_ID12("Lucent Technologies", "WaveLAN/PCMCIA", 0x23eb9949, 0x1bc50975),
4605 PCMCIA_DEVICE_PROD_ID12("NCR", "WaveLAN/PCMCIA", 0x24358cd4, 0x1bc50975),
4606 PCMCIA_DEVICE_NULL,
4607};
4608MODULE_DEVICE_TABLE(pcmcia, wavelan_ids);
4609
4610static struct pcmcia_driver wavelan_driver = {
4611 .owner = THIS_MODULE,
4612 .drv = {
4613 .name = "wavelan_cs",
4614 },
4615 .probe = wavelan_probe,
4616 .remove = wavelan_detach,
4617 .id_table = wavelan_ids,
4618 .suspend = wavelan_suspend,
4619 .resume = wavelan_resume,
4620};
4621
4622static int __init
4623init_wavelan_cs(void)
4624{
4625 return pcmcia_register_driver(&wavelan_driver);
4626}
4627
4628static void __exit
4629exit_wavelan_cs(void)
4630{
4631 pcmcia_unregister_driver(&wavelan_driver);
4632}
4633
4634module_init(init_wavelan_cs);
4635module_exit(exit_wavelan_cs);
diff --git a/drivers/net/wireless/wavelan_cs.h b/drivers/net/wireless/wavelan_cs.h
deleted file mode 100644
index 2e4bfe4147c6..000000000000
--- a/drivers/net/wireless/wavelan_cs.h
+++ /dev/null
@@ -1,386 +0,0 @@
1/*
2 * Wavelan Pcmcia driver
3 *
4 * Jean II - HPLB '96
5 *
6 * Reorganization and extension of the driver.
7 * Original copyright follow. See wavelan_cs.h for details.
8 *
9 * This file contain the declarations of the Wavelan hardware. Note that
10 * the Pcmcia Wavelan include a i82593 controller (see definitions in
11 * file i82593.h).
12 *
13 * The main difference between the pcmcia hardware and the ISA one is
14 * the Ethernet Controller (i82593 instead of i82586). The i82593 allow
15 * only one send buffer. The PSA (Parameter Storage Area : EEprom for
16 * permanent storage of various info) is memory mapped, but not the
17 * MMI (Modem Management Interface).
18 */
19
20/*
21 * Definitions for the AT&T GIS (formerly NCR) WaveLAN PCMCIA card:
22 * An Ethernet-like radio transceiver controlled by an Intel 82593
23 * coprocessor.
24 *
25 *
26 ****************************************************************************
27 * Copyright 1995
28 * Anthony D. Joseph
29 * Massachusetts Institute of Technology
30 *
31 * Permission to use, copy, modify, and distribute this program
32 * for any purpose and without fee is hereby granted, provided
33 * that this copyright and permission notice appear on all copies
34 * and supporting documentation, the name of M.I.T. not be used
35 * in advertising or publicity pertaining to distribution of the
36 * program without specific prior permission, and notice be given
37 * in supporting documentation that copying and distribution is
38 * by permission of M.I.T. M.I.T. makes no representations about
39 * the suitability of this software for any purpose. It is pro-
40 * vided "as is" without express or implied warranty.
41 ****************************************************************************
42 *
43 *
44 * Credits:
45 * Special thanks to Jan Hoogendoorn of AT&T GIS Utrecht for
46 * providing extremely useful information about WaveLAN PCMCIA hardware
47 *
48 * This driver is based upon several other drivers, in particular:
49 * David Hinds' Linux driver for the PCMCIA 3c589 ethernet adapter
50 * Bruce Janson's Linux driver for the AT-bus WaveLAN adapter
51 * Anders Klemets' PCMCIA WaveLAN adapter driver
52 * Robert Morris' BSDI driver for the PCMCIA WaveLAN adapter
53 */
54
55#ifndef _WAVELAN_CS_H
56#define _WAVELAN_CS_H
57
58/************************** MAGIC NUMBERS ***************************/
59
60/* The detection of the wavelan card is made by reading the MAC address
61 * from the card and checking it. If you have a non AT&T product (OEM,
62 * like DEC RoamAbout, or Digital Ocean, Epson, ...), you must modify this
63 * part to accommodate your hardware...
64 */
65static const unsigned char MAC_ADDRESSES[][3] =
66{
67 { 0x08, 0x00, 0x0E }, /* AT&T Wavelan (standard) & DEC RoamAbout */
68 { 0x08, 0x00, 0x6A }, /* AT&T Wavelan (alternate) */
69 { 0x00, 0x00, 0xE1 }, /* Hitachi Wavelan */
70 { 0x00, 0x60, 0x1D } /* Lucent Wavelan (another one) */
71 /* Add your card here and send me the patch ! */
72};
73
74/*
75 * Constants used to convert channels to frequencies
76 */
77
78/* Frequency available in the 2.0 modem, in units of 250 kHz
79 * (as read in the offset register of the dac area).
80 * Used to map channel numbers used by `wfreqsel' to frequencies
81 */
82static const short channel_bands[] = { 0x30, 0x58, 0x64, 0x7A, 0x80, 0xA8,
83 0xD0, 0xF0, 0xF8, 0x150 };
84
85/* Frequencies of the 1.0 modem (fixed frequencies).
86 * Use to map the PSA `subband' to a frequency
87 * Note : all frequencies apart from the first one need to be multiplied by 10
88 */
89static const int fixed_bands[] = { 915e6, 2.425e8, 2.46e8, 2.484e8, 2.4305e8 };
90
91
92/*************************** PC INTERFACE ****************************/
93
94/* WaveLAN host interface definitions */
95
96#define LCCR(base) (base) /* LAN Controller Command Register */
97#define LCSR(base) (base) /* LAN Controller Status Register */
98#define HACR(base) (base+0x1) /* Host Adapter Command Register */
99#define HASR(base) (base+0x1) /* Host Adapter Status Register */
100#define PIORL(base) (base+0x2) /* Program I/O Register Low */
101#define RPLL(base) (base+0x2) /* Receive Pointer Latched Low */
102#define PIORH(base) (base+0x3) /* Program I/O Register High */
103#define RPLH(base) (base+0x3) /* Receive Pointer Latched High */
104#define PIOP(base) (base+0x4) /* Program I/O Port */
105#define MMR(base) (base+0x6) /* MMI Address Register */
106#define MMD(base) (base+0x7) /* MMI Data Register */
107
108/* Host Adaptor Command Register bit definitions */
109
110#define HACR_LOF (1 << 3) /* Lock Out Flag, toggle every 250ms */
111#define HACR_PWR_STAT (1 << 4) /* Power State, 1=active, 0=sleep */
112#define HACR_TX_DMA_RESET (1 << 5) /* Reset transmit DMA ptr on high */
113#define HACR_RX_DMA_RESET (1 << 6) /* Reset receive DMA ptr on high */
114#define HACR_ROM_WEN (1 << 7) /* EEPROM write enabled when true */
115
116#define HACR_RESET (HACR_TX_DMA_RESET | HACR_RX_DMA_RESET)
117#define HACR_DEFAULT (HACR_PWR_STAT)
118
119/* Host Adapter Status Register bit definitions */
120
121#define HASR_MMI_BUSY (1 << 2) /* MMI is busy when true */
122#define HASR_LOF (1 << 3) /* Lock out flag status */
123#define HASR_NO_CLK (1 << 4) /* active when modem not connected */
124
125/* Miscellaneous bit definitions */
126
127#define PIORH_SEL_TX (1 << 5) /* PIOR points to 0=rx/1=tx buffer */
128#define MMR_MMI_WR (1 << 0) /* Next MMI cycle is 0=read, 1=write */
129#define PIORH_MASK 0x1f /* only low 5 bits are significant */
130#define RPLH_MASK 0x1f /* only low 5 bits are significant */
131#define MMI_ADDR_MASK 0x7e /* Bits 1-6 of MMR are significant */
132
133/* Attribute Memory map */
134
135#define CIS_ADDR 0x0000 /* Card Information Status Register */
136#define PSA_ADDR 0x0e00 /* Parameter Storage Area address */
137#define EEPROM_ADDR 0x1000 /* EEPROM address (unused ?) */
138#define COR_ADDR 0x4000 /* Configuration Option Register */
139
140/* Configuration Option Register bit definitions */
141
142#define COR_CONFIG (1 << 0) /* Config Index, 0 when unconfigured */
143#define COR_SW_RESET (1 << 7) /* Software Reset on true */
144#define COR_LEVEL_IRQ (1 << 6) /* Level IRQ */
145
146/* Local Memory map */
147
148#define RX_BASE 0x0000 /* Receive memory, 8 kB */
149#define TX_BASE 0x2000 /* Transmit memory, 2 kB */
150#define UNUSED_BASE 0x2800 /* Unused, 22 kB */
151#define RX_SIZE (TX_BASE-RX_BASE) /* Size of receive area */
152#define RX_SIZE_SHIFT 6 /* Bits to shift in stop register */
153
154#define TRUE 1
155#define FALSE 0
156
157#define MOD_ENAL 1
158#define MOD_PROM 2
159
160/* Size of a MAC address */
161#define WAVELAN_ADDR_SIZE 6
162
163/* Maximum size of Wavelan packet */
164#define WAVELAN_MTU 1500
165
166#define MAXDATAZ (6 + 6 + 2 + WAVELAN_MTU)
167
168/********************** PARAMETER STORAGE AREA **********************/
169
170/*
171 * Parameter Storage Area (PSA).
172 */
173typedef struct psa_t psa_t;
174struct psa_t
175{
176 /* For the PCMCIA Adapter, locations 0x00-0x0F are unused and fixed at 00 */
177 unsigned char psa_io_base_addr_1; /* [0x00] Base address 1 ??? */
178 unsigned char psa_io_base_addr_2; /* [0x01] Base address 2 */
179 unsigned char psa_io_base_addr_3; /* [0x02] Base address 3 */
180 unsigned char psa_io_base_addr_4; /* [0x03] Base address 4 */
181 unsigned char psa_rem_boot_addr_1; /* [0x04] Remote Boot Address 1 */
182 unsigned char psa_rem_boot_addr_2; /* [0x05] Remote Boot Address 2 */
183 unsigned char psa_rem_boot_addr_3; /* [0x06] Remote Boot Address 3 */
184 unsigned char psa_holi_params; /* [0x07] HOst Lan Interface (HOLI) Parameters */
185 unsigned char psa_int_req_no; /* [0x08] Interrupt Request Line */
186 unsigned char psa_unused0[7]; /* [0x09-0x0F] unused */
187
188 unsigned char psa_univ_mac_addr[WAVELAN_ADDR_SIZE]; /* [0x10-0x15] Universal (factory) MAC Address */
189 unsigned char psa_local_mac_addr[WAVELAN_ADDR_SIZE]; /* [0x16-1B] Local MAC Address */
190 unsigned char psa_univ_local_sel; /* [0x1C] Universal Local Selection */
191#define PSA_UNIVERSAL 0 /* Universal (factory) */
192#define PSA_LOCAL 1 /* Local */
193 unsigned char psa_comp_number; /* [0x1D] Compatability Number: */
194#define PSA_COMP_PC_AT_915 0 /* PC-AT 915 MHz */
195#define PSA_COMP_PC_MC_915 1 /* PC-MC 915 MHz */
196#define PSA_COMP_PC_AT_2400 2 /* PC-AT 2.4 GHz */
197#define PSA_COMP_PC_MC_2400 3 /* PC-MC 2.4 GHz */
198#define PSA_COMP_PCMCIA_915 4 /* PCMCIA 915 MHz or 2.0 */
199 unsigned char psa_thr_pre_set; /* [0x1E] Modem Threshold Preset */
200 unsigned char psa_feature_select; /* [0x1F] Call code required (1=on) */
201#define PSA_FEATURE_CALL_CODE 0x01 /* Call code required (Japan) */
202 unsigned char psa_subband; /* [0x20] Subband */
203#define PSA_SUBBAND_915 0 /* 915 MHz or 2.0 */
204#define PSA_SUBBAND_2425 1 /* 2425 MHz */
205#define PSA_SUBBAND_2460 2 /* 2460 MHz */
206#define PSA_SUBBAND_2484 3 /* 2484 MHz */
207#define PSA_SUBBAND_2430_5 4 /* 2430.5 MHz */
208 unsigned char psa_quality_thr; /* [0x21] Modem Quality Threshold */
209 unsigned char psa_mod_delay; /* [0x22] Modem Delay ??? (reserved) */
210 unsigned char psa_nwid[2]; /* [0x23-0x24] Network ID */
211 unsigned char psa_nwid_select; /* [0x25] Network ID Select On Off */
212 unsigned char psa_encryption_select; /* [0x26] Encryption On Off */
213 unsigned char psa_encryption_key[8]; /* [0x27-0x2E] Encryption Key */
214 unsigned char psa_databus_width; /* [0x2F] AT bus width select 8/16 */
215 unsigned char psa_call_code[8]; /* [0x30-0x37] (Japan) Call Code */
216 unsigned char psa_nwid_prefix[2]; /* [0x38-0x39] Roaming domain */
217 unsigned char psa_reserved[2]; /* [0x3A-0x3B] Reserved - fixed 00 */
218 unsigned char psa_conf_status; /* [0x3C] Conf Status, bit 0=1:config*/
219 unsigned char psa_crc[2]; /* [0x3D] CRC-16 over PSA */
220 unsigned char psa_crc_status; /* [0x3F] CRC Valid Flag */
221};
222
223/* Size for structure checking (if padding is correct) */
224#define PSA_SIZE 64
225
226/* Calculate offset of a field in the above structure
227 * Warning : only even addresses are used */
228#define psaoff(p,f) ((unsigned short) ((void *)(&((psa_t *) ((void *) NULL + (p)))->f) - (void *) NULL))
229
230/******************** MODEM MANAGEMENT INTERFACE ********************/
231
232/*
233 * Modem Management Controller (MMC) write structure.
234 */
235typedef struct mmw_t mmw_t;
236struct mmw_t
237{
238 unsigned char mmw_encr_key[8]; /* encryption key */
239 unsigned char mmw_encr_enable; /* enable/disable encryption */
240#define MMW_ENCR_ENABLE_MODE 0x02 /* Mode of security option */
241#define MMW_ENCR_ENABLE_EN 0x01 /* Enable security option */
242 unsigned char mmw_unused0[1]; /* unused */
243 unsigned char mmw_des_io_invert; /* Encryption option */
244#define MMW_DES_IO_INVERT_RES 0x0F /* Reserved */
245#define MMW_DES_IO_INVERT_CTRL 0xF0 /* Control ??? (set to 0) */
246 unsigned char mmw_unused1[5]; /* unused */
247 unsigned char mmw_loopt_sel; /* looptest selection */
248#define MMW_LOOPT_SEL_DIS_NWID 0x40 /* disable NWID filtering */
249#define MMW_LOOPT_SEL_INT 0x20 /* activate Attention Request */
250#define MMW_LOOPT_SEL_LS 0x10 /* looptest w/o collision avoidance */
251#define MMW_LOOPT_SEL_LT3A 0x08 /* looptest 3a */
252#define MMW_LOOPT_SEL_LT3B 0x04 /* looptest 3b */
253#define MMW_LOOPT_SEL_LT3C 0x02 /* looptest 3c */
254#define MMW_LOOPT_SEL_LT3D 0x01 /* looptest 3d */
255 unsigned char mmw_jabber_enable; /* jabber timer enable */
256 /* Abort transmissions > 200 ms */
257 unsigned char mmw_freeze; /* freeze / unfreeeze signal level */
258 /* 0 : signal level & qual updated for every new message, 1 : frozen */
259 unsigned char mmw_anten_sel; /* antenna selection */
260#define MMW_ANTEN_SEL_SEL 0x01 /* direct antenna selection */
261#define MMW_ANTEN_SEL_ALG_EN 0x02 /* antenna selection algo. enable */
262 unsigned char mmw_ifs; /* inter frame spacing */
263 /* min time between transmission in bit periods (.5 us) - bit 0 ignored */
264 unsigned char mmw_mod_delay; /* modem delay (synchro) */
265 unsigned char mmw_jam_time; /* jamming time (after collision) */
266 unsigned char mmw_unused2[1]; /* unused */
267 unsigned char mmw_thr_pre_set; /* level threshold preset */
268 /* Discard all packet with signal < this value (4) */
269 unsigned char mmw_decay_prm; /* decay parameters */
270 unsigned char mmw_decay_updat_prm; /* decay update parameterz */
271 unsigned char mmw_quality_thr; /* quality (z-quotient) threshold */
272 /* Discard all packet with quality < this value (3) */
273 unsigned char mmw_netw_id_l; /* NWID low order byte */
274 unsigned char mmw_netw_id_h; /* NWID high order byte */
275 /* Network ID or Domain : create virtual net on the air */
276
277 /* 2.0 Hardware extension - frequency selection support */
278 unsigned char mmw_mode_select; /* for analog tests (set to 0) */
279 unsigned char mmw_unused3[1]; /* unused */
280 unsigned char mmw_fee_ctrl; /* frequency eeprom control */
281#define MMW_FEE_CTRL_PRE 0x10 /* Enable protected instructions */
282#define MMW_FEE_CTRL_DWLD 0x08 /* Download eeprom to mmc */
283#define MMW_FEE_CTRL_CMD 0x07 /* EEprom commands : */
284#define MMW_FEE_CTRL_READ 0x06 /* Read */
285#define MMW_FEE_CTRL_WREN 0x04 /* Write enable */
286#define MMW_FEE_CTRL_WRITE 0x05 /* Write data to address */
287#define MMW_FEE_CTRL_WRALL 0x04 /* Write data to all addresses */
288#define MMW_FEE_CTRL_WDS 0x04 /* Write disable */
289#define MMW_FEE_CTRL_PRREAD 0x16 /* Read addr from protect register */
290#define MMW_FEE_CTRL_PREN 0x14 /* Protect register enable */
291#define MMW_FEE_CTRL_PRCLEAR 0x17 /* Unprotect all registers */
292#define MMW_FEE_CTRL_PRWRITE 0x15 /* Write addr in protect register */
293#define MMW_FEE_CTRL_PRDS 0x14 /* Protect register disable */
294 /* Never issue this command (PRDS) : it's irreversible !!! */
295
296 unsigned char mmw_fee_addr; /* EEprom address */
297#define MMW_FEE_ADDR_CHANNEL 0xF0 /* Select the channel */
298#define MMW_FEE_ADDR_OFFSET 0x0F /* Offset in channel data */
299#define MMW_FEE_ADDR_EN 0xC0 /* FEE_CTRL enable operations */
300#define MMW_FEE_ADDR_DS 0x00 /* FEE_CTRL disable operations */
301#define MMW_FEE_ADDR_ALL 0x40 /* FEE_CTRL all operations */
302#define MMW_FEE_ADDR_CLEAR 0xFF /* FEE_CTRL clear operations */
303
304 unsigned char mmw_fee_data_l; /* Write data to EEprom */
305 unsigned char mmw_fee_data_h; /* high octet */
306 unsigned char mmw_ext_ant; /* Setting for external antenna */
307#define MMW_EXT_ANT_EXTANT 0x01 /* Select external antenna */
308#define MMW_EXT_ANT_POL 0x02 /* Polarity of the antenna */
309#define MMW_EXT_ANT_INTERNAL 0x00 /* Internal antenna */
310#define MMW_EXT_ANT_EXTERNAL 0x03 /* External antenna */
311#define MMW_EXT_ANT_IQ_TEST 0x1C /* IQ test pattern (set to 0) */
312} __attribute__((packed));
313
314/* Size for structure checking (if padding is correct) */
315#define MMW_SIZE 37
316
317/* Calculate offset of a field in the above structure */
318#define mmwoff(p,f) (unsigned short)((void *)(&((mmw_t *)((void *)0 + (p)))->f) - (void *)0)
319
320
321/*
322 * Modem Management Controller (MMC) read structure.
323 */
324typedef struct mmr_t mmr_t;
325struct mmr_t
326{
327 unsigned char mmr_unused0[8]; /* unused */
328 unsigned char mmr_des_status; /* encryption status */
329 unsigned char mmr_des_avail; /* encryption available (0x55 read) */
330#define MMR_DES_AVAIL_DES 0x55 /* DES available */
331#define MMR_DES_AVAIL_AES 0x33 /* AES (AT&T) available */
332 unsigned char mmr_des_io_invert; /* des I/O invert register */
333 unsigned char mmr_unused1[5]; /* unused */
334 unsigned char mmr_dce_status; /* DCE status */
335#define MMR_DCE_STATUS_RX_BUSY 0x01 /* receiver busy */
336#define MMR_DCE_STATUS_LOOPT_IND 0x02 /* loop test indicated */
337#define MMR_DCE_STATUS_TX_BUSY 0x04 /* transmitter on */
338#define MMR_DCE_STATUS_JBR_EXPIRED 0x08 /* jabber timer expired */
339#define MMR_DCE_STATUS 0x0F /* mask to get the bits */
340 unsigned char mmr_dsp_id; /* DSP id (AA = Daedalus rev A) */
341 unsigned char mmr_unused2[2]; /* unused */
342 unsigned char mmr_correct_nwid_l; /* # of correct NWID's rxd (low) */
343 unsigned char mmr_correct_nwid_h; /* # of correct NWID's rxd (high) */
344 /* Warning : Read high order octet first !!! */
345 unsigned char mmr_wrong_nwid_l; /* # of wrong NWID's rxd (low) */
346 unsigned char mmr_wrong_nwid_h; /* # of wrong NWID's rxd (high) */
347 unsigned char mmr_thr_pre_set; /* level threshold preset */
348#define MMR_THR_PRE_SET 0x3F /* level threshold preset */
349#define MMR_THR_PRE_SET_CUR 0x80 /* Current signal above it */
350 unsigned char mmr_signal_lvl; /* signal level */
351#define MMR_SIGNAL_LVL 0x3F /* signal level */
352#define MMR_SIGNAL_LVL_VALID 0x80 /* Updated since last read */
353 unsigned char mmr_silence_lvl; /* silence level (noise) */
354#define MMR_SILENCE_LVL 0x3F /* silence level */
355#define MMR_SILENCE_LVL_VALID 0x80 /* Updated since last read */
356 unsigned char mmr_sgnl_qual; /* signal quality */
357#define MMR_SGNL_QUAL 0x0F /* signal quality */
358#define MMR_SGNL_QUAL_ANT 0x80 /* current antenna used */
359 unsigned char mmr_netw_id_l; /* NWID low order byte ??? */
360 unsigned char mmr_unused3[3]; /* unused */
361
362 /* 2.0 Hardware extension - frequency selection support */
363 unsigned char mmr_fee_status; /* Status of frequency eeprom */
364#define MMR_FEE_STATUS_ID 0xF0 /* Modem revision id */
365#define MMR_FEE_STATUS_DWLD 0x08 /* Download in progress */
366#define MMR_FEE_STATUS_BUSY 0x04 /* EEprom busy */
367 unsigned char mmr_unused4[1]; /* unused */
368 unsigned char mmr_fee_data_l; /* Read data from eeprom (low) */
369 unsigned char mmr_fee_data_h; /* Read data from eeprom (high) */
370};
371
372/* Size for structure checking (if padding is correct) */
373#define MMR_SIZE 36
374
375/* Calculate offset of a field in the above structure */
376#define mmroff(p,f) (unsigned short)((void *)(&((mmr_t *)((void *)0 + (p)))->f) - (void *)0)
377
378
379/* Make the two above structures one */
380typedef union mm_t
381{
382 struct mmw_t w; /* Write to the mmc */
383 struct mmr_t r; /* Read from the mmc */
384} mm_t;
385
386#endif /* _WAVELAN_CS_H */
diff --git a/drivers/net/wireless/wavelan_cs.p.h b/drivers/net/wireless/wavelan_cs.p.h
deleted file mode 100644
index 81d91531c4f9..000000000000
--- a/drivers/net/wireless/wavelan_cs.p.h
+++ /dev/null
@@ -1,766 +0,0 @@
1/*
2 * Wavelan Pcmcia driver
3 *
4 * Jean II - HPLB '96
5 *
6 * Reorganisation and extension of the driver.
7 *
8 * This file contain all definition and declarations necessary for the
9 * wavelan pcmcia driver. This file is a private header, so it should
10 * be included only on wavelan_cs.c !!!
11 */
12
13#ifndef WAVELAN_CS_P_H
14#define WAVELAN_CS_P_H
15
16/************************** DOCUMENTATION **************************/
17/*
18 * This driver provide a Linux interface to the Wavelan Pcmcia hardware
19 * The Wavelan is a product of Lucent (http://www.wavelan.com/).
20 * This division was formerly part of NCR and then AT&T.
21 * Wavelan are also distributed by DEC (RoamAbout DS)...
22 *
23 * To know how to use this driver, read the PCMCIA HOWTO.
24 * If you want to exploit the many other fonctionalities, look comments
25 * in the code...
26 *
27 * This driver is the result of the effort of many peoples (see below).
28 */
29
30/* ------------------------ SPECIFIC NOTES ------------------------ */
31/*
32 * Web page
33 * --------
34 * I try to maintain a web page with the Wireless LAN Howto at :
35 * http://www.hpl.hp.com/personal/Jean_Tourrilhes/Linux/Wavelan.html
36 *
37 * SMP
38 * ---
39 * We now are SMP compliant (I eventually fixed the remaining bugs).
40 * The driver has been tested on a dual P6-150 and survived my usual
41 * set of torture tests.
42 * Anyway, I spent enough time chasing interrupt re-entrancy during
43 * errors or reconfigure, and I designed the locked/unlocked sections
44 * of the driver with great care, and with the recent addition of
45 * the spinlock (thanks to the new API), we should be quite close to
46 * the truth.
47 * The SMP/IRQ locking is quite coarse and conservative (i.e. not fast),
48 * but better safe than sorry (especially at 2 Mb/s ;-).
49 *
50 * I have also looked into disabling only our interrupt on the card
51 * (via HACR) instead of all interrupts in the processor (via cli),
52 * so that other driver are not impacted, and it look like it's
53 * possible, but it's very tricky to do right (full of races). As
54 * the gain would be mostly for SMP systems, it can wait...
55 *
56 * Debugging and options
57 * ---------------------
58 * You will find below a set of '#define" allowing a very fine control
59 * on the driver behaviour and the debug messages printed.
60 * The main options are :
61 * o WAVELAN_ROAMING, for the experimental roaming support.
62 * o SET_PSA_CRC, to have your card correctly recognised by
63 * an access point and the Point-to-Point diagnostic tool.
64 * o USE_PSA_CONFIG, to read configuration from the PSA (EEprom)
65 * (otherwise we always start afresh with some defaults)
66 *
67 * wavelan_cs.o is darn too big
68 * -------------------------
69 * That's true ! There is a very simple way to reduce the driver
70 * object by 33% (yes !). Comment out the following line :
71 * #include <linux/wireless.h>
72 * Other compile options can also reduce the size of it...
73 *
74 * MAC address and hardware detection :
75 * ----------------------------------
76 * The detection code of the wavelan chech that the first 3
77 * octets of the MAC address fit the company code. This type of
78 * detection work well for AT&T cards (because the AT&T code is
79 * hardcoded in wavelan_cs.h), but of course will fail for other
80 * manufacturer.
81 *
82 * If you are sure that your card is derived from the wavelan,
83 * here is the way to configure it :
84 * 1) Get your MAC address
85 * a) With your card utilities (wfreqsel, instconf, ...)
86 * b) With the driver :
87 * o compile the kernel with DEBUG_CONFIG_INFO enabled
88 * o Boot and look the card messages
89 * 2) Set your MAC code (3 octets) in MAC_ADDRESSES[][3] (wavelan_cs.h)
90 * 3) Compile & verify
91 * 4) Send me the MAC code - I will include it in the next version...
92 *
93 */
94
95/* --------------------- WIRELESS EXTENSIONS --------------------- */
96/*
97 * This driver is the first one to support "wireless extensions".
98 * This set of extensions provide you some way to control the wireless
99 * caracteristics of the hardware in a standard way and support for
100 * applications for taking advantage of it (like Mobile IP).
101 *
102 * It might be a good idea as well to fetch the wireless tools to
103 * configure the device and play a bit.
104 */
105
106/* ---------------------------- FILES ---------------------------- */
107/*
108 * wavelan_cs.c : The actual code for the driver - C functions
109 *
110 * wavelan_cs.p.h : Private header : local types / vars for the driver
111 *
112 * wavelan_cs.h : Description of the hardware interface & structs
113 *
114 * i82593.h : Description if the Ethernet controller
115 */
116
117/* --------------------------- HISTORY --------------------------- */
118/*
119 * The history of the Wavelan drivers is as complicated as history of
120 * the Wavelan itself (NCR -> AT&T -> Lucent).
121 *
122 * All started with Anders Klemets <klemets@paul.rutgers.edu>,
123 * writing a Wavelan ISA driver for the MACH microkernel. Girish
124 * Welling <welling@paul.rutgers.edu> had also worked on it.
125 * Keith Moore modify this for the Pcmcia hardware.
126 *
127 * Robert Morris <rtm@das.harvard.edu> port these two drivers to BSDI
128 * and add specific Pcmcia support (there is currently no equivalent
129 * of the PCMCIA package under BSD...).
130 *
131 * Jim Binkley <jrb@cs.pdx.edu> port both BSDI drivers to FreeBSD.
132 *
133 * Bruce Janson <bruce@cs.usyd.edu.au> port the BSDI ISA driver to Linux.
134 *
135 * Anthony D. Joseph <adj@lcs.mit.edu> started modify Bruce driver
136 * (with help of the BSDI PCMCIA driver) for PCMCIA.
137 * Yunzhou Li <yunzhou@strat.iol.unh.edu> finished is work.
138 * Joe Finney <joe@comp.lancs.ac.uk> patched the driver to start
139 * correctly 2.00 cards (2.4 GHz with frequency selection).
140 * David Hinds <dahinds@users.sourceforge.net> integrated the whole in his
141 * Pcmcia package (+ bug corrections).
142 *
143 * I (Jean Tourrilhes - jt@hplb.hpl.hp.com) then started to make some
144 * patchs to the Pcmcia driver. After, I added code in the ISA driver
145 * for Wireless Extensions and full support of frequency selection
146 * cards. Now, I'm doing the same to the Pcmcia driver + some
147 * reorganisation.
148 * Loeke Brederveld <lbrederv@wavelan.com> from Lucent has given me
149 * much needed informations on the Wavelan hardware.
150 */
151
152/* By the way : for the copyright & legal stuff :
153 * Almost everybody wrote code under GNU or BSD license (or alike),
154 * and want that their original copyright remain somewhere in the
155 * code (for myself, I go with the GPL).
156 * Nobody want to take responsibility for anything, except the fame...
157 */
158
159/* --------------------------- CREDITS --------------------------- */
160/*
161 * Credits:
162 * Special thanks to Jan Hoogendoorn of AT&T GIS Utrecht and
163 * Loeke Brederveld of Lucent for providing extremely useful
164 * information about WaveLAN PCMCIA hardware
165 *
166 * This driver is based upon several other drivers, in particular:
167 * David Hinds' Linux driver for the PCMCIA 3c589 ethernet adapter
168 * Bruce Janson's Linux driver for the AT-bus WaveLAN adapter
169 * Anders Klemets' PCMCIA WaveLAN adapter driver
170 * Robert Morris' BSDI driver for the PCMCIA WaveLAN adapter
171 *
172 * Additional Credits:
173 *
174 * This software was originally developed under Linux 1.2.3
175 * (Slackware 2.0 distribution).
176 * And then under Linux 2.0.x (Debian 1.1 -> 2.2 - pcmcia 2.8.18+)
177 * with an HP OmniBook 4000 and then a 5500.
178 *
179 * It is based on other device drivers and information either written
180 * or supplied by:
181 * James Ashton (jaa101@syseng.anu.edu.au),
182 * Ajay Bakre (bakre@paul.rutgers.edu),
183 * Donald Becker (becker@super.org),
184 * Jim Binkley <jrb@cs.pdx.edu>,
185 * Loeke Brederveld <lbrederv@wavelan.com>,
186 * Allan Creighton (allanc@cs.su.oz.au),
187 * Brent Elphick <belphick@uwaterloo.ca>,
188 * Joe Finney <joe@comp.lancs.ac.uk>,
189 * Matthew Geier (matthew@cs.su.oz.au),
190 * Remo di Giovanni (remo@cs.su.oz.au),
191 * Mark Hagan (mhagan@wtcpost.daytonoh.NCR.COM),
192 * David Hinds <dahinds@users.sourceforge.net>,
193 * Jan Hoogendoorn (c/o marteijn@lucent.com),
194 * Bruce Janson <bruce@cs.usyd.edu.au>,
195 * Anthony D. Joseph <adj@lcs.mit.edu>,
196 * Anders Klemets (klemets@paul.rutgers.edu),
197 * Yunzhou Li <yunzhou@strat.iol.unh.edu>,
198 * Marc Meertens (mmeertens@lucent.com),
199 * Keith Moore,
200 * Robert Morris (rtm@das.harvard.edu),
201 * Ian Parkin (ian@cs.su.oz.au),
202 * John Rosenberg (johnr@cs.su.oz.au),
203 * George Rossi (george@phm.gov.au),
204 * Arthur Scott (arthur@cs.su.oz.au),
205 * Stanislav Sinyagin <stas@isf.ru>
206 * Peter Storey,
207 * Jean Tourrilhes <jt@hpl.hp.com>,
208 * Girish Welling (welling@paul.rutgers.edu)
209 * Clark Woodworth <clark@hiway1.exit109.com>
210 * Yongguang Zhang <ygz@isl.hrl.hac.com>...
211 */
212
213/* ------------------------- IMPROVEMENTS ------------------------- */
214/*
215 * I proudly present :
216 *
217 * Changes made in 2.8.22 :
218 * ----------------------
219 * - improved wv_set_multicast_list
220 * - catch spurious interrupt
221 * - correct release of the device
222 *
223 * Changes mades in release :
224 * ------------------------
225 * - Reorganisation of the code, function name change
226 * - Creation of private header (wavelan_cs.h)
227 * - Reorganised debug messages
228 * - More comments, history, ...
229 * - Configure earlier (in "insert" instead of "open")
230 * and do things only once
231 * - mmc_init : configure the PSA if not done
232 * - mmc_init : 2.00 detection better code for 2.00 init
233 * - better info at startup
234 * - Correct a HUGE bug (volatile & uncalibrated busy loop)
235 * in wv_82593_cmd => config speedup
236 * - Stop receiving & power down on close (and power up on open)
237 * use "ifconfig down" & "ifconfig up ; route add -net ..."
238 * - Send packets : add watchdog instead of pooling
239 * - Receive : check frame wrap around & try to recover some frames
240 * - wavelan_set_multicast_list : avoid reset
241 * - add wireless extensions (ioctl & get_wireless_stats)
242 * get/set nwid/frequency on fly, info for /proc/net/wireless
243 * - Suppress useless stuff from lp (net_local), but add link
244 * - More inlines
245 * - Lot of others minor details & cleanups
246 *
247 * Changes made in second release :
248 * ------------------------------
249 * - Optimise wv_85893_reconfig stuff, fix potential problems
250 * - Change error values for ioctl
251 * - Non blocking wv_ru_stop() + call wv_reset() in case of problems
252 * - Remove development printk from wavelan_watchdog()
253 * - Remove of the watchdog to wavelan_close instead of wavelan_release
254 * fix potential problems...
255 * - Start debugging suspend stuff (but it's still a bit weird)
256 * - Debug & optimize dump header/packet in Rx & Tx (debug)
257 * - Use "readb" and "writeb" to be kernel 2.1 compliant
258 * - Better handling of bogus interrupts
259 * - Wireless extension : SETSPY and GETSPY
260 * - Remove old stuff (stats - for those needing it, just ask me...)
261 * - Make wireless extensions optional
262 *
263 * Changes made in third release :
264 * -----------------------------
265 * - cleanups & typos
266 * - modif wireless ext (spy -> only one pointer)
267 * - new private ioctl to set/get quality & level threshold
268 * - Init : correct default value of level threshold for pcmcia
269 * - kill watchdog in hw_reset
270 * - more 2.1 support (copy_to/from_user instead of memcpy_to/fromfs)
271 * - Add message level (debug stuff in /var/adm/debug & errors not
272 * displayed at console and still in /var/adm/messages)
273 *
274 * Changes made in fourth release :
275 * ------------------------------
276 * - multicast support (yes !) thanks to Yongguang Zhang.
277 *
278 * Changes made in fifth release (2.9.0) :
279 * -------------------------------------
280 * - Revisited multicast code (it was mostly wrong).
281 * - protect code in wv_82593_reconfig with dev->tbusy (oups !)
282 *
283 * Changes made in sixth release (2.9.1a) :
284 * --------------------------------------
285 * - Change the detection code for multi manufacturer code support
286 * - Correct bug (hang kernel) in init when we were "rejecting" a card
287 *
288 * Changes made in seventh release (2.9.1b) :
289 * ----------------------------------------
290 * - Update to wireless extensions changes
291 * - Silly bug in card initial configuration (psa_conf_status)
292 *
293 * Changes made in eigth release :
294 * -----------------------------
295 * - Small bug in debug code (probably not the last one...)
296 * - 1.2.13 support (thanks to Clark Woodworth)
297 *
298 * Changes made for release in 2.9.2b :
299 * ----------------------------------
300 * - Level threshold is now a standard wireless extension (version 4 !)
301 * - modules parameters types for kernel > 2.1.17
302 * - updated man page
303 * - Others cleanup from David Hinds
304 *
305 * Changes made for release in 2.9.5 :
306 * ---------------------------------
307 * - byte count stats (courtesy of David Hinds)
308 * - Remove dev_tint stuff (courtesy of David Hinds)
309 * - Others cleanup from David Hinds
310 * - Encryption setting from Brent Elphick (thanks a lot !)
311 * - 'base' to 'u_long' for the Alpha (thanks to Stanislav Sinyagin)
312 *
313 * Changes made for release in 2.9.6 :
314 * ---------------------------------
315 * - fix bug : no longuer disable watchdog in case of bogus interrupt
316 * - increase timeout in config code for picky hardware
317 * - mask unused bits in status (Wireless Extensions)
318 *
319 * Changes integrated by Justin Seger <jseger@MIT.EDU> & David Hinds :
320 * -----------------------------------------------------------------
321 * - Roaming "hack" from Joe Finney <joe@comp.lancs.ac.uk>
322 * - PSA CRC code from Bob Gray <rgray@bald.cs.dartmouth.edu>
323 * - Better initialisation of the i82593 controller
324 * from Joseph K. O'Sullivan <josullvn+@cs.cmu.edu>
325 *
326 * Changes made for release in 3.0.10 :
327 * ----------------------------------
328 * - Fix eject "hang" of the driver under 2.2.X :
329 * o create wv_flush_stale_links()
330 * o Rename wavelan_release to wv_pcmcia_release & move up
331 * o move unregister_netdev to wavelan_detach()
332 * o wavelan_release() no longer call wavelan_detach()
333 * o Suppress "release" timer
334 * o Other cleanups & fixes
335 * - New MAC address in the probe
336 * - Reorg PSA_CRC code (endian neutral & cleaner)
337 * - Correct initialisation of the i82593 from Lucent manual
338 * - Put back the watchdog, with larger timeout
339 * - TRANSMIT_NO_CRC is a "normal" error, so recover from it
340 * from Derrick J Brashear <shadow@dementia.org>
341 * - Better handling of TX and RX normal failure conditions
342 * - #ifdef out all the roaming code
343 * - Add ESSID & "AP current address" ioctl stubs
344 * - General cleanup of the code
345 *
346 * Changes made for release in 3.0.13 :
347 * ----------------------------------
348 * - Re-enable compilation of roaming code by default, but with
349 * do_roaming = 0
350 * - Nuke `nwid=nwid^ntohs(beacon->domain_id)' in wl_roam_gather
351 * at the demand of John Carol Langford <jcl@gs176.sp.cs.cmu.edu>
352 * - Introduced WAVELAN_ROAMING_EXT for incomplete ESSID stuff.
353 *
354 * Changes made for release in 3.0.15 :
355 * ----------------------------------
356 * - Change e-mail and web page addresses
357 * - Watchdog timer is now correctly expressed in HZ, not in jiffies
358 * - Add channel number to the list of frequencies in range
359 * - Add the (short) list of bit-rates in range
360 * - Developp a new sensitivity... (sens.value & sens.fixed)
361 *
362 * Changes made for release in 3.1.2 :
363 * ---------------------------------
364 * - Fix check for root permission (break instead of exit)
365 * - New nwid & encoding setting (Wireless Extension 9)
366 *
367 * Changes made for release in 3.1.12 :
368 * ----------------------------------
369 * - reworked wv_82593_cmd to avoid using the IRQ handler and doing
370 * ugly things with interrupts.
371 * - Add IRQ protection in 82593_config/ru_start/ru_stop/watchdog
372 * - Update to new network API (softnet - 2.3.43) :
373 * o replace dev->tbusy (David + me)
374 * o replace dev->tstart (David + me)
375 * o remove dev->interrupt (David)
376 * o add SMP locking via spinlock in splxx (me)
377 * o add spinlock in interrupt handler (me)
378 * o use kernel watchdog instead of ours (me)
379 * o verify that all the changes make sense and work (me)
380 * - Re-sync kernel/pcmcia versions (not much actually)
381 * - A few other cleanups (David & me)...
382 *
383 * Changes made for release in 3.1.22 :
384 * ----------------------------------
385 * - Check that SMP works, remove annoying log message
386 *
387 * Changes made for release in 3.1.24 :
388 * ----------------------------------
389 * - Fix unfrequent card lockup when watchdog was reseting the hardware :
390 * o control first busy loop in wv_82593_cmd()
391 * o Extend spinlock protection in wv_hw_config()
392 *
393 * Changes made for release in 3.1.33 :
394 * ----------------------------------
395 * - Optional use new driver API for Wireless Extensions :
396 * o got rid of wavelan_ioctl()
397 * o use a bunch of iw_handler instead
398 *
399 * Changes made for release in 3.2.1 :
400 * ---------------------------------
401 * - Set dev->trans_start to avoid filling the logs
402 * (and generating useless abort commands)
403 * - Avoid deadlocks in mmc_out()/mmc_in()
404 *
405 * Wishes & dreams:
406 * ----------------
407 * - Cleanup and integrate the roaming code
408 * (std debug, set DomainID, decay avg and co...)
409 */
410
411/***************************** INCLUDES *****************************/
412
413/* Linux headers that we need */
414#include <linux/module.h>
415#include <linux/kernel.h>
416#include <linux/init.h>
417#include <linux/sched.h>
418#include <linux/ptrace.h>
419#include <linux/slab.h>
420#include <linux/string.h>
421#include <linux/timer.h>
422#include <linux/interrupt.h>
423#include <linux/spinlock.h>
424#include <linux/in.h>
425#include <linux/delay.h>
426#include <linux/bitops.h>
427#include <asm/uaccess.h>
428#include <asm/io.h>
429#include <asm/system.h>
430
431#include <linux/netdevice.h>
432#include <linux/etherdevice.h>
433#include <linux/skbuff.h>
434#include <linux/if_arp.h>
435#include <linux/ioport.h>
436#include <linux/fcntl.h>
437#include <linux/ethtool.h>
438#include <linux/wireless.h> /* Wireless extensions */
439#include <net/iw_handler.h> /* New driver API */
440
441/* Pcmcia headers that we need */
442#include <pcmcia/cs_types.h>
443#include <pcmcia/cs.h>
444#include <pcmcia/cistpl.h>
445#include <pcmcia/cisreg.h>
446#include <pcmcia/ds.h>
447
448/* Wavelan declarations */
449#include "i82593.h" /* Definitions for the Intel chip */
450
451#include "wavelan_cs.h" /* Others bits of the hardware */
452
453/************************** DRIVER OPTIONS **************************/
454/*
455 * `#define' or `#undef' the following constant to change the behaviour
456 * of the driver...
457 */
458#define WAVELAN_ROAMING /* Include experimental roaming code */
459#undef WAVELAN_ROAMING_EXT /* Enable roaming wireless extensions */
460#undef SET_PSA_CRC /* Set the CRC in PSA (slower) */
461#define USE_PSA_CONFIG /* Use info from the PSA */
462#undef EEPROM_IS_PROTECTED /* Doesn't seem to be necessary */
463#define MULTICAST_AVOID /* Avoid extra multicast (I'm sceptical) */
464#undef SET_MAC_ADDRESS /* Experimental */
465
466/* Warning : these stuff will slow down the driver... */
467#define WIRELESS_SPY /* Enable spying addresses */
468#undef HISTOGRAM /* Enable histogram of sig level... */
469
470/****************************** DEBUG ******************************/
471
472#undef DEBUG_MODULE_TRACE /* Module insertion/removal */
473#undef DEBUG_CALLBACK_TRACE /* Calls made by Linux */
474#undef DEBUG_INTERRUPT_TRACE /* Calls to handler */
475#undef DEBUG_INTERRUPT_INFO /* type of interrupt & so on */
476#define DEBUG_INTERRUPT_ERROR /* problems */
477#undef DEBUG_CONFIG_TRACE /* Trace the config functions */
478#undef DEBUG_CONFIG_INFO /* What's going on... */
479#define DEBUG_CONFIG_ERRORS /* Errors on configuration */
480#undef DEBUG_TX_TRACE /* Transmission calls */
481#undef DEBUG_TX_INFO /* Header of the transmitted packet */
482#undef DEBUG_TX_FAIL /* Normal failure conditions */
483#define DEBUG_TX_ERROR /* Unexpected conditions */
484#undef DEBUG_RX_TRACE /* Transmission calls */
485#undef DEBUG_RX_INFO /* Header of the transmitted packet */
486#undef DEBUG_RX_FAIL /* Normal failure conditions */
487#define DEBUG_RX_ERROR /* Unexpected conditions */
488#undef DEBUG_PACKET_DUMP /* Dump packet on the screen */
489#undef DEBUG_IOCTL_TRACE /* Misc call by Linux */
490#undef DEBUG_IOCTL_INFO /* Various debug info */
491#define DEBUG_IOCTL_ERROR /* What's going wrong */
492#define DEBUG_BASIC_SHOW /* Show basic startup info */
493#undef DEBUG_VERSION_SHOW /* Print version info */
494#undef DEBUG_PSA_SHOW /* Dump psa to screen */
495#undef DEBUG_MMC_SHOW /* Dump mmc to screen */
496#undef DEBUG_SHOW_UNUSED /* Show also unused fields */
497#undef DEBUG_I82593_SHOW /* Show i82593 status */
498#undef DEBUG_DEVICE_SHOW /* Show device parameters */
499
500/************************ CONSTANTS & MACROS ************************/
501
502#ifdef DEBUG_VERSION_SHOW
503static const char *version = "wavelan_cs.c : v24 (SMP + wireless extensions) 11/1/02\n";
504#endif
505
506/* Watchdog temporisation */
507#define WATCHDOG_JIFFIES (256*HZ/100)
508
509/* Fix a bug in some old wireless extension definitions */
510#ifndef IW_ESSID_MAX_SIZE
511#define IW_ESSID_MAX_SIZE 32
512#endif
513
514/* ------------------------ PRIVATE IOCTL ------------------------ */
515
516#define SIOCSIPQTHR SIOCIWFIRSTPRIV /* Set quality threshold */
517#define SIOCGIPQTHR SIOCIWFIRSTPRIV + 1 /* Get quality threshold */
518#define SIOCSIPROAM SIOCIWFIRSTPRIV + 2 /* Set roaming state */
519#define SIOCGIPROAM SIOCIWFIRSTPRIV + 3 /* Get roaming state */
520
521#define SIOCSIPHISTO SIOCIWFIRSTPRIV + 4 /* Set histogram ranges */
522#define SIOCGIPHISTO SIOCIWFIRSTPRIV + 5 /* Get histogram values */
523
524/*************************** WaveLAN Roaming **************************/
525#ifdef WAVELAN_ROAMING /* Conditional compile, see above in options */
526
527#define WAVELAN_ROAMING_DEBUG 0 /* 1 = Trace of handover decisions */
528 /* 2 = Info on each beacon rcvd... */
529#define MAX_WAVEPOINTS 7 /* Max visible at one time */
530#define WAVEPOINT_HISTORY 5 /* SNR sample history slow search */
531#define WAVEPOINT_FAST_HISTORY 2 /* SNR sample history fast search */
532#define SEARCH_THRESH_LOW 10 /* SNR to enter cell search */
533#define SEARCH_THRESH_HIGH 13 /* SNR to leave cell search */
534#define WAVELAN_ROAMING_DELTA 1 /* Hysteresis value (+/- SNR) */
535#define CELL_TIMEOUT 2*HZ /* in jiffies */
536
537#define FAST_CELL_SEARCH 1 /* Boolean values... */
538#define NWID_PROMISC 1 /* for code clarity. */
539
540typedef struct wavepoint_beacon
541{
542 unsigned char dsap, /* Unused */
543 ssap, /* Unused */
544 ctrl, /* Unused */
545 O,U,I, /* Unused */
546 spec_id1, /* Unused */
547 spec_id2, /* Unused */
548 pdu_type, /* Unused */
549 seq; /* WavePoint beacon sequence number */
550 __be16 domain_id, /* WavePoint Domain ID */
551 nwid; /* WavePoint NWID */
552} wavepoint_beacon;
553
554typedef struct wavepoint_history
555{
556 unsigned short nwid; /* WavePoint's NWID */
557 int average_slow; /* SNR running average */
558 int average_fast; /* SNR running average */
559 unsigned char sigqual[WAVEPOINT_HISTORY]; /* Ringbuffer of recent SNR's */
560 unsigned char qualptr; /* Index into ringbuffer */
561 unsigned char last_seq; /* Last seq. no seen for WavePoint */
562 struct wavepoint_history *next; /* Next WavePoint in table */
563 struct wavepoint_history *prev; /* Previous WavePoint in table */
564 unsigned long last_seen; /* Time of last beacon recvd, jiffies */
565} wavepoint_history;
566
567struct wavepoint_table
568{
569 wavepoint_history *head; /* Start of ringbuffer */
570 int num_wavepoints; /* No. of WavePoints visible */
571 unsigned char locked; /* Table lock */
572};
573
574#endif /* WAVELAN_ROAMING */
575
576/****************************** TYPES ******************************/
577
578/* Shortcuts */
579typedef struct iw_statistics iw_stats;
580typedef struct iw_quality iw_qual;
581typedef struct iw_freq iw_freq;
582typedef struct net_local net_local;
583typedef struct timer_list timer_list;
584
585/* Basic types */
586typedef u_char mac_addr[WAVELAN_ADDR_SIZE]; /* Hardware address */
587
588/*
589 * Static specific data for the interface.
590 *
591 * For each network interface, Linux keep data in two structure. "device"
592 * keep the generic data (same format for everybody) and "net_local" keep
593 * the additional specific data.
594 */
595struct net_local
596{
597 dev_node_t node; /* ???? What is this stuff ???? */
598 struct net_device * dev; /* Reverse link... */
599 spinlock_t spinlock; /* Serialize access to the hardware (SMP) */
600 struct pcmcia_device * link; /* pcmcia structure */
601 int nresets; /* Number of hw resets */
602 u_char configured; /* If it is configured */
603 u_char reconfig_82593; /* Need to reconfigure the controller */
604 u_char promiscuous; /* Promiscuous mode */
605 u_char allmulticast; /* All Multicast mode */
606 int mc_count; /* Number of multicast addresses */
607
608 int stop; /* Current i82593 Stop Hit Register */
609 int rfp; /* Last DMA machine receive pointer */
610 int overrunning; /* Receiver overrun flag */
611
612 iw_stats wstats; /* Wireless specific stats */
613
614 struct iw_spy_data spy_data;
615 struct iw_public_data wireless_data;
616
617#ifdef HISTOGRAM
618 int his_number; /* Number of intervals */
619 u_char his_range[16]; /* Boundaries of interval ]n-1; n] */
620 u_long his_sum[16]; /* Sum in interval */
621#endif /* HISTOGRAM */
622#ifdef WAVELAN_ROAMING
623 u_long domain_id; /* Domain ID we lock on for roaming */
624 int filter_domains; /* Check Domain ID of beacon found */
625 struct wavepoint_table wavepoint_table; /* Table of visible WavePoints*/
626 wavepoint_history * curr_point; /* Current wavepoint */
627 int cell_search; /* Searching for new cell? */
628 struct timer_list cell_timer; /* Garbage collection */
629#endif /* WAVELAN_ROAMING */
630 void __iomem *mem;
631};
632
633/* ----------------- MODEM MANAGEMENT SUBROUTINES ----------------- */
634static inline u_char /* data */
635 hasr_read(u_long); /* Read the host interface : base address */
636static void
637 hacr_write(u_long, /* Write to host interface : base address */
638 u_char), /* data */
639 hacr_write_slow(u_long,
640 u_char);
641static void
642 psa_read(struct net_device *, /* Read the Parameter Storage Area */
643 int, /* offset in PSA */
644 u_char *, /* buffer to fill */
645 int), /* size to read */
646 psa_write(struct net_device *, /* Write to the PSA */
647 int, /* Offset in psa */
648 u_char *, /* Buffer in memory */
649 int); /* Length of buffer */
650static void
651 mmc_out(u_long, /* Write 1 byte to the Modem Manag Control */
652 u_short,
653 u_char),
654 mmc_write(u_long, /* Write n bytes to the MMC */
655 u_char,
656 u_char *,
657 int);
658static u_char /* Read 1 byte from the MMC */
659 mmc_in(u_long,
660 u_short);
661static void
662 mmc_read(u_long, /* Read n bytes from the MMC */
663 u_char,
664 u_char *,
665 int),
666 fee_wait(u_long, /* Wait for frequency EEprom : base address */
667 int, /* Base delay to wait for */
668 int); /* Number of time to wait */
669static void
670 fee_read(u_long, /* Read the frequency EEprom : base address */
671 u_short, /* destination offset */
672 u_short *, /* data buffer */
673 int); /* number of registers */
674/* ---------------------- I82593 SUBROUTINES ----------------------- */
675static int
676 wv_82593_cmd(struct net_device *, /* synchronously send a command to i82593 */
677 char *,
678 int,
679 int);
680static inline int
681 wv_diag(struct net_device *); /* Diagnostique the i82593 */
682static int
683 read_ringbuf(struct net_device *, /* Read a receive buffer */
684 int,
685 char *,
686 int);
687static void
688 wv_82593_reconfig(struct net_device *); /* Reconfigure the controller */
689/* ------------------- DEBUG & INFO SUBROUTINES ------------------- */
690static void
691 wv_init_info(struct net_device *); /* display startup info */
692/* ------------------- IOCTL, STATS & RECONFIG ------------------- */
693static iw_stats *
694 wavelan_get_wireless_stats(struct net_device *);
695/* ----------------------- PACKET RECEPTION ----------------------- */
696static int
697 wv_start_of_frame(struct net_device *, /* Seek beggining of current frame */
698 int, /* end of frame */
699 int); /* start of buffer */
700static void
701 wv_packet_read(struct net_device *, /* Read a packet from a frame */
702 int,
703 int),
704 wv_packet_rcv(struct net_device *); /* Read all packets waiting */
705/* --------------------- PACKET TRANSMISSION --------------------- */
706static void
707 wv_packet_write(struct net_device *, /* Write a packet to the Tx buffer */
708 void *,
709 short);
710static netdev_tx_t
711 wavelan_packet_xmit(struct sk_buff *, /* Send a packet */
712 struct net_device *);
713/* -------------------- HARDWARE CONFIGURATION -------------------- */
714static int
715 wv_mmc_init(struct net_device *); /* Initialize the modem */
716static int
717 wv_ru_stop(struct net_device *), /* Stop the i82593 receiver unit */
718 wv_ru_start(struct net_device *); /* Start the i82593 receiver unit */
719static int
720 wv_82593_config(struct net_device *); /* Configure the i82593 */
721static int
722 wv_pcmcia_reset(struct net_device *); /* Reset the pcmcia interface */
723static int
724 wv_hw_config(struct net_device *); /* Reset & configure the whole hardware */
725static void
726 wv_hw_reset(struct net_device *); /* Same, + start receiver unit */
727static int
728 wv_pcmcia_config(struct pcmcia_device *); /* Configure the pcmcia interface */
729static void
730 wv_pcmcia_release(struct pcmcia_device *);/* Remove a device */
731/* ---------------------- INTERRUPT HANDLING ---------------------- */
732static irqreturn_t
733 wavelan_interrupt(int, /* Interrupt handler */
734 void *);
735static void
736 wavelan_watchdog(struct net_device *); /* Transmission watchdog */
737/* ------------------- CONFIGURATION CALLBACKS ------------------- */
738static int
739 wavelan_open(struct net_device *), /* Open the device */
740 wavelan_close(struct net_device *); /* Close the device */
741static void
742 wavelan_detach(struct pcmcia_device *p_dev); /* Destroy a removed device */
743
744/**************************** VARIABLES ****************************/
745
746/*
747 * Parameters that can be set with 'insmod'
748 * The exact syntax is 'insmod wavelan_cs.o <var>=<value>'
749 */
750
751/* Shared memory speed, in ns */
752static int mem_speed = 0;
753
754/* New module interface */
755module_param(mem_speed, int, 0);
756
757#ifdef WAVELAN_ROAMING /* Conditional compile, see above in options */
758/* Enable roaming mode ? No ! Please keep this to 0 */
759static int do_roaming = 0;
760module_param(do_roaming, bool, 0);
761#endif /* WAVELAN_ROAMING */
762
763MODULE_LICENSE("GPL");
764
765#endif /* WAVELAN_CS_P_H */
766
diff --git a/drivers/net/wireless/wl12xx/Kconfig b/drivers/net/wireless/wl12xx/Kconfig
index 88060e117541..785e0244e305 100644
--- a/drivers/net/wireless/wl12xx/Kconfig
+++ b/drivers/net/wireless/wl12xx/Kconfig
@@ -1,6 +1,6 @@
1menuconfig WL12XX 1menuconfig WL12XX
2 tristate "TI wl12xx driver support" 2 tristate "TI wl12xx driver support"
3 depends on MAC80211 && WLAN_80211 && EXPERIMENTAL 3 depends on MAC80211 && EXPERIMENTAL
4 ---help--- 4 ---help---
5 This will enable TI wl12xx driver support. The drivers make 5 This will enable TI wl12xx driver support. The drivers make
6 use of the mac80211 stack. 6 use of the mac80211 stack.
@@ -42,6 +42,7 @@ config WL1251_SDIO
42config WL1271 42config WL1271
43 tristate "TI wl1271 support" 43 tristate "TI wl1271 support"
44 depends on WL12XX && SPI_MASTER && GENERIC_HARDIRQS 44 depends on WL12XX && SPI_MASTER && GENERIC_HARDIRQS
45 depends on INET
45 select FW_LOADER 46 select FW_LOADER
46 select CRC7 47 select CRC7
47 ---help--- 48 ---help---
diff --git a/drivers/net/wireless/wl12xx/wl1251_main.c b/drivers/net/wireless/wl12xx/wl1251_main.c
index 48b0bfd6c55a..da3bf1cebc08 100644
--- a/drivers/net/wireless/wl12xx/wl1251_main.c
+++ b/drivers/net/wireless/wl12xx/wl1251_main.c
@@ -1311,7 +1311,8 @@ int wl1251_init_ieee80211(struct wl1251 *wl)
1311 wl->hw->channel_change_time = 10000; 1311 wl->hw->channel_change_time = 10000;
1312 1312
1313 wl->hw->flags = IEEE80211_HW_SIGNAL_DBM | 1313 wl->hw->flags = IEEE80211_HW_SIGNAL_DBM |
1314 IEEE80211_HW_NOISE_DBM; 1314 IEEE80211_HW_NOISE_DBM |
1315 IEEE80211_HW_SUPPORTS_PS;
1315 1316
1316 wl->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 1317 wl->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1317 wl->hw->wiphy->max_scan_ssids = 1; 1318 wl->hw->wiphy->max_scan_ssids = 1;
diff --git a/drivers/net/wireless/wl12xx/wl1271.h b/drivers/net/wireless/wl12xx/wl1271.h
index 566f1521ec22..94359b1a861f 100644
--- a/drivers/net/wireless/wl12xx/wl1271.h
+++ b/drivers/net/wireless/wl12xx/wl1271.h
@@ -417,6 +417,9 @@ struct wl1271 {
417 /* PSM mode requested */ 417 /* PSM mode requested */
418 bool psm_requested; 418 bool psm_requested;
419 419
420 /* retry counter for PSM entries */
421 u8 psm_entry_retry;
422
420 /* in dBm */ 423 /* in dBm */
421 int power_level; 424 int power_level;
422 425
diff --git a/drivers/net/wireless/wl12xx/wl1271_acx.c b/drivers/net/wireless/wl12xx/wl1271_acx.c
index bf5a8680a462..5cc89bbdac7a 100644
--- a/drivers/net/wireless/wl12xx/wl1271_acx.c
+++ b/drivers/net/wireless/wl12xx/wl1271_acx.c
@@ -141,7 +141,7 @@ int wl1271_acx_tx_power(struct wl1271 *wl, int power)
141 * calibration, to avoid distortions 141 * calibration, to avoid distortions
142 */ 142 */
143 /* acx->current_tx_power = power * 10; */ 143 /* acx->current_tx_power = power * 10; */
144 acx->current_tx_power = 70; 144 acx->current_tx_power = 120;
145 145
146 ret = wl1271_cmd_configure(wl, DOT11_CUR_TX_PWR, acx, sizeof(*acx)); 146 ret = wl1271_cmd_configure(wl, DOT11_CUR_TX_PWR, acx, sizeof(*acx));
147 if (ret < 0) { 147 if (ret < 0) {
diff --git a/drivers/net/wireless/wl12xx/wl1271_boot.c b/drivers/net/wireless/wl12xx/wl1271_boot.c
index ba4a2b4f0f56..b7c96454cca3 100644
--- a/drivers/net/wireless/wl12xx/wl1271_boot.c
+++ b/drivers/net/wireless/wl12xx/wl1271_boot.c
@@ -380,7 +380,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
380 } 380 }
381 } 381 }
382 382
383 if (loop >= INIT_LOOP) { 383 if (loop > INIT_LOOP) {
384 wl1271_error("timeout waiting for the hardware to " 384 wl1271_error("timeout waiting for the hardware to "
385 "complete initialization"); 385 "complete initialization");
386 return -EIO; 386 return -EIO;
@@ -407,7 +407,8 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
407 407
408 /* unmask required mbox events */ 408 /* unmask required mbox events */
409 wl->event_mask = BSS_LOSE_EVENT_ID | 409 wl->event_mask = BSS_LOSE_EVENT_ID |
410 SCAN_COMPLETE_EVENT_ID; 410 SCAN_COMPLETE_EVENT_ID |
411 PS_REPORT_EVENT_ID;
411 412
412 ret = wl1271_event_unmask(wl); 413 ret = wl1271_event_unmask(wl);
413 if (ret < 0) { 414 if (ret < 0) {
diff --git a/drivers/net/wireless/wl12xx/wl1271_cmd.c b/drivers/net/wireless/wl12xx/wl1271_cmd.c
index 0666328ce9ab..990eb01b4c71 100644
--- a/drivers/net/wireless/wl12xx/wl1271_cmd.c
+++ b/drivers/net/wireless/wl12xx/wl1271_cmd.c
@@ -42,12 +42,14 @@
42 * @buf: buffer containing the command, must work with dma 42 * @buf: buffer containing the command, must work with dma
43 * @len: length of the buffer 43 * @len: length of the buffer
44 */ 44 */
45int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len) 45int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
46 size_t res_len)
46{ 47{
47 struct wl1271_cmd_header *cmd; 48 struct wl1271_cmd_header *cmd;
48 unsigned long timeout; 49 unsigned long timeout;
49 u32 intr; 50 u32 intr;
50 int ret = 0; 51 int ret = 0;
52 u16 status;
51 53
52 cmd = buf; 54 cmd = buf;
53 cmd->id = cpu_to_le16(id); 55 cmd->id = cpu_to_le16(id);
@@ -74,6 +76,17 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len)
74 intr = wl1271_spi_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); 76 intr = wl1271_spi_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
75 } 77 }
76 78
79 /* read back the status code of the command */
80 if (res_len == 0)
81 res_len = sizeof(struct wl1271_cmd_header);
82 wl1271_spi_read(wl, wl->cmd_box_addr, cmd, res_len, false);
83
84 status = le16_to_cpu(cmd->status);
85 if (status != CMD_STATUS_SUCCESS) {
86 wl1271_error("command execute failure %d", status);
87 ret = -EIO;
88 }
89
77 wl1271_spi_write32(wl, ACX_REG_INTERRUPT_ACK, 90 wl1271_spi_write32(wl, ACX_REG_INTERRUPT_ACK,
78 WL1271_ACX_INTR_CMD_COMPLETE); 91 WL1271_ACX_INTR_CMD_COMPLETE);
79 92
@@ -262,7 +275,7 @@ int wl1271_cmd_join(struct wl1271 *wl)
262 wl->tx_security_seq_16 = 0; 275 wl->tx_security_seq_16 = 0;
263 wl->tx_security_seq_32 = 0; 276 wl->tx_security_seq_32 = 0;
264 277
265 ret = wl1271_cmd_send(wl, CMD_START_JOIN, join, sizeof(*join)); 278 ret = wl1271_cmd_send(wl, CMD_START_JOIN, join, sizeof(*join), 0);
266 if (ret < 0) { 279 if (ret < 0) {
267 wl1271_error("failed to initiate cmd join"); 280 wl1271_error("failed to initiate cmd join");
268 goto out_free; 281 goto out_free;
@@ -294,35 +307,21 @@ out:
294int wl1271_cmd_test(struct wl1271 *wl, void *buf, size_t buf_len, u8 answer) 307int wl1271_cmd_test(struct wl1271 *wl, void *buf, size_t buf_len, u8 answer)
295{ 308{
296 int ret; 309 int ret;
310 size_t res_len = 0;
297 311
298 wl1271_debug(DEBUG_CMD, "cmd test"); 312 wl1271_debug(DEBUG_CMD, "cmd test");
299 313
300 ret = wl1271_cmd_send(wl, CMD_TEST, buf, buf_len); 314 if (answer)
315 res_len = buf_len;
316
317 ret = wl1271_cmd_send(wl, CMD_TEST, buf, buf_len, res_len);
301 318
302 if (ret < 0) { 319 if (ret < 0) {
303 wl1271_warning("TEST command failed"); 320 wl1271_warning("TEST command failed");
304 return ret; 321 return ret;
305 } 322 }
306 323
307 if (answer) { 324 return ret;
308 struct wl1271_command *cmd_answer;
309 u16 status;
310
311 /*
312 * The test command got in, we can read the answer.
313 * The answer would be a wl1271_command, where the
314 * parameter array contains the actual answer.
315 */
316 wl1271_spi_read(wl, wl->cmd_box_addr, buf, buf_len, false);
317
318 cmd_answer = buf;
319 status = le16_to_cpu(cmd_answer->header.status);
320
321 if (status != CMD_STATUS_SUCCESS)
322 wl1271_error("TEST command answer error: %d", status);
323 }
324
325 return 0;
326} 325}
327 326
328/** 327/**
@@ -345,21 +344,10 @@ int wl1271_cmd_interrogate(struct wl1271 *wl, u16 id, void *buf, size_t len)
345 /* payload length, does not include any headers */ 344 /* payload length, does not include any headers */
346 acx->len = cpu_to_le16(len - sizeof(*acx)); 345 acx->len = cpu_to_le16(len - sizeof(*acx));
347 346
348 ret = wl1271_cmd_send(wl, CMD_INTERROGATE, acx, sizeof(*acx)); 347 ret = wl1271_cmd_send(wl, CMD_INTERROGATE, acx, sizeof(*acx), len);
349 if (ret < 0) { 348 if (ret < 0)
350 wl1271_error("INTERROGATE command failed"); 349 wl1271_error("INTERROGATE command failed");
351 goto out;
352 }
353 350
354 /* the interrogate command got in, we can read the answer */
355 wl1271_spi_read(wl, wl->cmd_box_addr, buf, len, false);
356
357 acx = buf;
358 if (le16_to_cpu(acx->cmd.status) != CMD_STATUS_SUCCESS)
359 wl1271_error("INTERROGATE command error: %d",
360 le16_to_cpu(acx->cmd.status));
361
362out:
363 return ret; 351 return ret;
364} 352}
365 353
@@ -383,7 +371,7 @@ int wl1271_cmd_configure(struct wl1271 *wl, u16 id, void *buf, size_t len)
383 /* payload length, does not include any headers */ 371 /* payload length, does not include any headers */
384 acx->len = cpu_to_le16(len - sizeof(*acx)); 372 acx->len = cpu_to_le16(len - sizeof(*acx));
385 373
386 ret = wl1271_cmd_send(wl, CMD_CONFIGURE, acx, len); 374 ret = wl1271_cmd_send(wl, CMD_CONFIGURE, acx, len, 0);
387 if (ret < 0) { 375 if (ret < 0) {
388 wl1271_warning("CONFIGURE command NOK"); 376 wl1271_warning("CONFIGURE command NOK");
389 return ret; 377 return ret;
@@ -416,7 +404,7 @@ int wl1271_cmd_data_path(struct wl1271 *wl, u8 channel, bool enable)
416 cmd_tx = CMD_DISABLE_TX; 404 cmd_tx = CMD_DISABLE_TX;
417 } 405 }
418 406
419 ret = wl1271_cmd_send(wl, cmd_rx, cmd, sizeof(*cmd)); 407 ret = wl1271_cmd_send(wl, cmd_rx, cmd, sizeof(*cmd), 0);
420 if (ret < 0) { 408 if (ret < 0) {
421 wl1271_error("rx %s cmd for channel %d failed", 409 wl1271_error("rx %s cmd for channel %d failed",
422 enable ? "start" : "stop", channel); 410 enable ? "start" : "stop", channel);
@@ -426,7 +414,7 @@ int wl1271_cmd_data_path(struct wl1271 *wl, u8 channel, bool enable)
426 wl1271_debug(DEBUG_BOOT, "rx %s cmd channel %d", 414 wl1271_debug(DEBUG_BOOT, "rx %s cmd channel %d",
427 enable ? "start" : "stop", channel); 415 enable ? "start" : "stop", channel);
428 416
429 ret = wl1271_cmd_send(wl, cmd_tx, cmd, sizeof(*cmd)); 417 ret = wl1271_cmd_send(wl, cmd_tx, cmd, sizeof(*cmd), 0);
430 if (ret < 0) { 418 if (ret < 0) {
431 wl1271_error("tx %s cmd for channel %d failed", 419 wl1271_error("tx %s cmd for channel %d failed",
432 enable ? "start" : "stop", channel); 420 enable ? "start" : "stop", channel);
@@ -468,7 +456,7 @@ int wl1271_cmd_ps_mode(struct wl1271 *wl, u8 ps_mode)
468 ps_params->null_data_rate = cpu_to_le32(1); /* 1 Mbps */ 456 ps_params->null_data_rate = cpu_to_le32(1); /* 1 Mbps */
469 457
470 ret = wl1271_cmd_send(wl, CMD_SET_PS_MODE, ps_params, 458 ret = wl1271_cmd_send(wl, CMD_SET_PS_MODE, ps_params,
471 sizeof(*ps_params)); 459 sizeof(*ps_params), 0);
472 if (ret < 0) { 460 if (ret < 0) {
473 wl1271_error("cmd set_ps_mode failed"); 461 wl1271_error("cmd set_ps_mode failed");
474 goto out; 462 goto out;
@@ -499,19 +487,14 @@ int wl1271_cmd_read_memory(struct wl1271 *wl, u32 addr, void *answer,
499 cmd->addr = cpu_to_le32(addr); 487 cmd->addr = cpu_to_le32(addr);
500 cmd->size = cpu_to_le32(len); 488 cmd->size = cpu_to_le32(len);
501 489
502 ret = wl1271_cmd_send(wl, CMD_READ_MEMORY, cmd, sizeof(*cmd)); 490 ret = wl1271_cmd_send(wl, CMD_READ_MEMORY, cmd, sizeof(*cmd),
491 sizeof(*cmd));
503 if (ret < 0) { 492 if (ret < 0) {
504 wl1271_error("read memory command failed: %d", ret); 493 wl1271_error("read memory command failed: %d", ret);
505 goto out; 494 goto out;
506 } 495 }
507 496
508 /* the read command got in, we can now read the answer */ 497 /* the read command got in */
509 wl1271_spi_read(wl, wl->cmd_box_addr, cmd, sizeof(*cmd), false);
510
511 if (le16_to_cpu(cmd->header.status) != CMD_STATUS_SUCCESS)
512 wl1271_error("error in read command result: %d",
513 le16_to_cpu(cmd->header.status));
514
515 memcpy(answer, cmd->value, len); 498 memcpy(answer, cmd->value, len);
516 499
517out: 500out:
@@ -613,7 +596,7 @@ int wl1271_cmd_scan(struct wl1271 *wl, u8 *ssid, size_t len,
613 trigger->timeout = 0; 596 trigger->timeout = 0;
614 597
615 ret = wl1271_cmd_send(wl, CMD_TRIGGER_SCAN_TO, trigger, 598 ret = wl1271_cmd_send(wl, CMD_TRIGGER_SCAN_TO, trigger,
616 sizeof(*trigger)); 599 sizeof(*trigger), 0);
617 if (ret < 0) { 600 if (ret < 0) {
618 wl1271_error("trigger scan to failed for hw scan"); 601 wl1271_error("trigger scan to failed for hw scan");
619 goto out; 602 goto out;
@@ -636,20 +619,10 @@ int wl1271_cmd_scan(struct wl1271 *wl, u8 *ssid, size_t len,
636 } 619 }
637 } 620 }
638 621
639 ret = wl1271_cmd_send(wl, CMD_SCAN, params, sizeof(*params)); 622 ret = wl1271_cmd_send(wl, CMD_SCAN, params, sizeof(*params), 0);
640 if (ret < 0) { 623 if (ret < 0) {
641 wl1271_error("SCAN failed"); 624 wl1271_error("SCAN failed");
642 goto out;
643 }
644
645 wl1271_spi_read(wl, wl->cmd_box_addr, params, sizeof(*params),
646 false);
647
648 if (le16_to_cpu(params->header.status) != CMD_STATUS_SUCCESS) {
649 wl1271_error("Scan command error: %d",
650 le16_to_cpu(params->header.status));
651 wl->scanning = false; 625 wl->scanning = false;
652 ret = -EIO;
653 goto out; 626 goto out;
654 } 627 }
655 628
@@ -684,7 +657,7 @@ int wl1271_cmd_template_set(struct wl1271 *wl, u16 template_id,
684 if (buf) 657 if (buf)
685 memcpy(cmd->template_data, buf, buf_len); 658 memcpy(cmd->template_data, buf, buf_len);
686 659
687 ret = wl1271_cmd_send(wl, CMD_SET_TEMPLATE, cmd, sizeof(*cmd)); 660 ret = wl1271_cmd_send(wl, CMD_SET_TEMPLATE, cmd, sizeof(*cmd), 0);
688 if (ret < 0) { 661 if (ret < 0) {
689 wl1271_warning("cmd set_template failed: %d", ret); 662 wl1271_warning("cmd set_template failed: %d", ret);
690 goto out_free; 663 goto out_free;
@@ -863,7 +836,7 @@ int wl1271_cmd_set_default_wep_key(struct wl1271 *wl, u8 id)
863 cmd->key_action = cpu_to_le16(KEY_SET_ID); 836 cmd->key_action = cpu_to_le16(KEY_SET_ID);
864 cmd->key_type = KEY_WEP; 837 cmd->key_type = KEY_WEP;
865 838
866 ret = wl1271_cmd_send(wl, CMD_SET_KEYS, cmd, sizeof(*cmd)); 839 ret = wl1271_cmd_send(wl, CMD_SET_KEYS, cmd, sizeof(*cmd), 0);
867 if (ret < 0) { 840 if (ret < 0) {
868 wl1271_warning("cmd set_default_wep_key failed: %d", ret); 841 wl1271_warning("cmd set_default_wep_key failed: %d", ret);
869 goto out; 842 goto out;
@@ -920,7 +893,7 @@ int wl1271_cmd_set_key(struct wl1271 *wl, u16 action, u8 id, u8 key_type,
920 893
921 wl1271_dump(DEBUG_CRYPT, "TARGET KEY: ", cmd, sizeof(*cmd)); 894 wl1271_dump(DEBUG_CRYPT, "TARGET KEY: ", cmd, sizeof(*cmd));
922 895
923 ret = wl1271_cmd_send(wl, CMD_SET_KEYS, cmd, sizeof(*cmd)); 896 ret = wl1271_cmd_send(wl, CMD_SET_KEYS, cmd, sizeof(*cmd), 0);
924 if (ret < 0) { 897 if (ret < 0) {
925 wl1271_warning("could not set keys"); 898 wl1271_warning("could not set keys");
926 goto out; 899 goto out;
@@ -950,7 +923,7 @@ int wl1271_cmd_disconnect(struct wl1271 *wl)
950 /* disconnect reason is not used in immediate disconnections */ 923 /* disconnect reason is not used in immediate disconnections */
951 cmd->type = DISCONNECT_IMMEDIATE; 924 cmd->type = DISCONNECT_IMMEDIATE;
952 925
953 ret = wl1271_cmd_send(wl, CMD_DISCONNECT, cmd, sizeof(*cmd)); 926 ret = wl1271_cmd_send(wl, CMD_DISCONNECT, cmd, sizeof(*cmd), 0);
954 if (ret < 0) { 927 if (ret < 0) {
955 wl1271_error("failed to send disconnect command"); 928 wl1271_error("failed to send disconnect command");
956 goto out_free; 929 goto out_free;
diff --git a/drivers/net/wireless/wl12xx/wl1271_cmd.h b/drivers/net/wireless/wl12xx/wl1271_cmd.h
index 174b8209dbf3..9d7061b3c8a0 100644
--- a/drivers/net/wireless/wl12xx/wl1271_cmd.h
+++ b/drivers/net/wireless/wl12xx/wl1271_cmd.h
@@ -29,7 +29,8 @@
29 29
30struct acx_header; 30struct acx_header;
31 31
32int wl1271_cmd_send(struct wl1271 *wl, u16 type, void *buf, size_t buf_len); 32int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
33 size_t res_len);
33int wl1271_cmd_join(struct wl1271 *wl); 34int wl1271_cmd_join(struct wl1271 *wl);
34int wl1271_cmd_test(struct wl1271 *wl, void *buf, size_t buf_len, u8 answer); 35int wl1271_cmd_test(struct wl1271 *wl, void *buf, size_t buf_len, u8 answer);
35int wl1271_cmd_interrogate(struct wl1271 *wl, u16 id, void *buf, size_t len); 36int wl1271_cmd_interrogate(struct wl1271 *wl, u16 id, void *buf, size_t len);
diff --git a/drivers/net/wireless/wl12xx/wl1271_conf.h b/drivers/net/wireless/wl12xx/wl1271_conf.h
index 061d47520a32..565373ede265 100644
--- a/drivers/net/wireless/wl12xx/wl1271_conf.h
+++ b/drivers/net/wireless/wl12xx/wl1271_conf.h
@@ -712,6 +712,14 @@ struct conf_conn_settings {
712 * Range 0 - 255 712 * Range 0 - 255
713 */ 713 */
714 u8 bet_max_consecutive; 714 u8 bet_max_consecutive;
715
716 /*
717 * Specifies the maximum number of times to try PSM entry if it fails
718 * (if sending the appropriate null-func message fails.)
719 *
720 * Range 0 - 255
721 */
722 u8 psm_entry_retries;
715}; 723};
716 724
717#define CONF_SR_ERR_TBL_MAX_VALUES 14 725#define CONF_SR_ERR_TBL_MAX_VALUES 14
diff --git a/drivers/net/wireless/wl12xx/wl1271_event.c b/drivers/net/wireless/wl12xx/wl1271_event.c
index 31d396ba9188..e135d894b42a 100644
--- a/drivers/net/wireless/wl12xx/wl1271_event.c
+++ b/drivers/net/wireless/wl12xx/wl1271_event.c
@@ -68,6 +68,40 @@ static int wl1271_event_scan_complete(struct wl1271 *wl,
68 return 0; 68 return 0;
69} 69}
70 70
71static int wl1271_event_ps_report(struct wl1271 *wl,
72 struct event_mailbox *mbox,
73 bool *beacon_loss)
74{
75 int ret = 0;
76
77 wl1271_debug(DEBUG_EVENT, "ps_status: 0x%x", mbox->ps_status);
78
79 switch (mbox->ps_status) {
80 case EVENT_ENTER_POWER_SAVE_FAIL:
81 if (wl->psm_entry_retry < wl->conf.conn.psm_entry_retries) {
82 wl->psm_entry_retry++;
83 wl1271_error("PSM entry failed, retrying %d\n",
84 wl->psm_entry_retry);
85 ret = wl1271_ps_set_mode(wl, STATION_POWER_SAVE_MODE);
86 } else {
87 wl->psm_entry_retry = 0;
88 *beacon_loss = true;
89 }
90 break;
91 case EVENT_ENTER_POWER_SAVE_SUCCESS:
92 wl->psm_entry_retry = 0;
93 break;
94 case EVENT_EXIT_POWER_SAVE_FAIL:
95 wl1271_info("PSM exit failed");
96 break;
97 case EVENT_EXIT_POWER_SAVE_SUCCESS:
98 default:
99 break;
100 }
101
102 return ret;
103}
104
71static void wl1271_event_mbox_dump(struct event_mailbox *mbox) 105static void wl1271_event_mbox_dump(struct event_mailbox *mbox)
72{ 106{
73 wl1271_debug(DEBUG_EVENT, "MBOX DUMP:"); 107 wl1271_debug(DEBUG_EVENT, "MBOX DUMP:");
@@ -79,6 +113,7 @@ static int wl1271_event_process(struct wl1271 *wl, struct event_mailbox *mbox)
79{ 113{
80 int ret; 114 int ret;
81 u32 vector; 115 u32 vector;
116 bool beacon_loss = false;
82 117
83 wl1271_event_mbox_dump(mbox); 118 wl1271_event_mbox_dump(mbox);
84 119
@@ -101,7 +136,25 @@ static int wl1271_event_process(struct wl1271 *wl, struct event_mailbox *mbox)
101 wl1271_debug(DEBUG_EVENT, "BSS_LOSE_EVENT"); 136 wl1271_debug(DEBUG_EVENT, "BSS_LOSE_EVENT");
102 137
103 /* indicate to the stack, that beacons have been lost */ 138 /* indicate to the stack, that beacons have been lost */
139 beacon_loss = true;
140 }
141
142 if (vector & PS_REPORT_EVENT_ID) {
143 wl1271_debug(DEBUG_EVENT, "PS_REPORT_EVENT");
144 ret = wl1271_event_ps_report(wl, mbox, &beacon_loss);
145 if (ret < 0)
146 return ret;
147 }
148
149 if (beacon_loss) {
150 /* Obviously, it's dangerous to release the mutex while
151 we are holding many of the variables in the wl struct.
152 That's why it's done last in the function, and care must
153 be taken that nothing more is done after this function
154 returns. */
155 mutex_unlock(&wl->mutex);
104 ieee80211_beacon_loss(wl->vif); 156 ieee80211_beacon_loss(wl->vif);
157 mutex_lock(&wl->mutex);
105 } 158 }
106 159
107 return 0; 160 return 0;
diff --git a/drivers/net/wireless/wl12xx/wl1271_event.h b/drivers/net/wireless/wl12xx/wl1271_event.h
index 3ab53d331f15..4e3f55ebb1a8 100644
--- a/drivers/net/wireless/wl12xx/wl1271_event.h
+++ b/drivers/net/wireless/wl12xx/wl1271_event.h
@@ -63,6 +63,13 @@ enum {
63 EVENT_MBOX_ALL_EVENT_ID = 0x7fffffff, 63 EVENT_MBOX_ALL_EVENT_ID = 0x7fffffff,
64}; 64};
65 65
66enum {
67 EVENT_ENTER_POWER_SAVE_FAIL = 0,
68 EVENT_ENTER_POWER_SAVE_SUCCESS,
69 EVENT_EXIT_POWER_SAVE_FAIL,
70 EVENT_EXIT_POWER_SAVE_SUCCESS,
71};
72
66struct event_debug_report { 73struct event_debug_report {
67 u8 debug_event_id; 74 u8 debug_event_id;
68 u8 num_params; 75 u8 num_params;
diff --git a/drivers/net/wireless/wl12xx/wl1271_init.c b/drivers/net/wireless/wl12xx/wl1271_init.c
index 417b4152feb1..7c2017f480ea 100644
--- a/drivers/net/wireless/wl12xx/wl1271_init.c
+++ b/drivers/net/wireless/wl12xx/wl1271_init.c
@@ -303,12 +303,15 @@ int wl1271_hw_init(struct wl1271 *wl)
303{ 303{
304 int ret; 304 int ret;
305 305
306 /* FIXME: the following parameter setting functions return error
307 * codes - the reason is so far unknown. The -EIO is therefore
308 * ignored for the time being. */
306 ret = wl1271_init_general_parms(wl); 309 ret = wl1271_init_general_parms(wl);
307 if (ret < 0) 310 if (ret < 0 && ret != -EIO)
308 return ret; 311 return ret;
309 312
310 ret = wl1271_init_radio_parms(wl); 313 ret = wl1271_init_radio_parms(wl);
311 if (ret < 0) 314 if (ret < 0 && ret != -EIO)
312 return ret; 315 return ret;
313 316
314 /* Template settings */ 317 /* Template settings */
diff --git a/drivers/net/wireless/wl12xx/wl1271_main.c b/drivers/net/wireless/wl12xx/wl1271_main.c
index 86132bb00787..d2149fcd3cf1 100644
--- a/drivers/net/wireless/wl12xx/wl1271_main.c
+++ b/drivers/net/wireless/wl12xx/wl1271_main.c
@@ -222,7 +222,8 @@ static struct conf_drv_settings default_conf = {
222 .snr_pkt_avg_weight = 10 222 .snr_pkt_avg_weight = 10
223 }, 223 },
224 .bet_enable = CONF_BET_MODE_ENABLE, 224 .bet_enable = CONF_BET_MODE_ENABLE,
225 .bet_max_consecutive = 100 225 .bet_max_consecutive = 100,
226 .psm_entry_retries = 3
226 }, 227 },
227 .init = { 228 .init = {
228 .sr_err_tbl = { 229 .sr_err_tbl = {
@@ -973,6 +974,7 @@ static void wl1271_op_stop(struct ieee80211_hw *hw)
973 wl->rx_counter = 0; 974 wl->rx_counter = 0;
974 wl->elp = false; 975 wl->elp = false;
975 wl->psm = 0; 976 wl->psm = 0;
977 wl->psm_entry_retry = 0;
976 wl->tx_queue_stopped = false; 978 wl->tx_queue_stopped = false;
977 wl->power_level = WL1271_DEFAULT_POWER_LEVEL; 979 wl->power_level = WL1271_DEFAULT_POWER_LEVEL;
978 wl->tx_blocks_available = 0; 980 wl->tx_blocks_available = 0;
@@ -1067,11 +1069,11 @@ static int wl1271_op_config_interface(struct ieee80211_hw *hw,
1067 ret = wl1271_cmd_join(wl); 1069 ret = wl1271_cmd_join(wl);
1068 if (ret < 0) 1070 if (ret < 0)
1069 goto out_sleep; 1071 goto out_sleep;
1070 }
1071 1072
1072 ret = wl1271_cmd_build_null_data(wl); 1073 ret = wl1271_cmd_build_null_data(wl);
1073 if (ret < 0) 1074 if (ret < 0)
1074 goto out_sleep; 1075 goto out_sleep;
1076 }
1075 1077
1076 wl->ssid_len = conf->ssid_len; 1078 wl->ssid_len = conf->ssid_len;
1077 if (wl->ssid_len) 1079 if (wl->ssid_len)
@@ -1137,10 +1139,6 @@ static int wl1271_op_config(struct ieee80211_hw *hw, u32 changed)
1137 wl->channel = channel; 1139 wl->channel = channel;
1138 } 1140 }
1139 1141
1140 ret = wl1271_cmd_build_null_data(wl);
1141 if (ret < 0)
1142 goto out_sleep;
1143
1144 if (conf->flags & IEEE80211_CONF_PS && !wl->psm_requested) { 1142 if (conf->flags & IEEE80211_CONF_PS && !wl->psm_requested) {
1145 wl1271_info("psm enabled"); 1143 wl1271_info("psm enabled");
1146 1144
@@ -1165,7 +1163,7 @@ static int wl1271_op_config(struct ieee80211_hw *hw, u32 changed)
1165 if (conf->power_level != wl->power_level) { 1163 if (conf->power_level != wl->power_level) {
1166 ret = wl1271_acx_tx_power(wl, conf->power_level); 1164 ret = wl1271_acx_tx_power(wl, conf->power_level);
1167 if (ret < 0) 1165 if (ret < 0)
1168 goto out; 1166 goto out_sleep;
1169 1167
1170 wl->power_level = conf->power_level; 1168 wl->power_level = conf->power_level;
1171 } 1169 }
@@ -1826,6 +1824,7 @@ static int __devinit wl1271_probe(struct spi_device *spi)
1826 wl->elp = false; 1824 wl->elp = false;
1827 wl->psm = 0; 1825 wl->psm = 0;
1828 wl->psm_requested = false; 1826 wl->psm_requested = false;
1827 wl->psm_entry_retry = 0;
1829 wl->tx_queue_stopped = false; 1828 wl->tx_queue_stopped = false;
1830 wl->power_level = WL1271_DEFAULT_POWER_LEVEL; 1829 wl->power_level = WL1271_DEFAULT_POWER_LEVEL;
1831 wl->basic_rate_set = WL1271_DEFAULT_BASIC_RATE_SET; 1830 wl->basic_rate_set = WL1271_DEFAULT_BASIC_RATE_SET;
diff --git a/drivers/net/wireless/wl12xx/wl1271_rx.c b/drivers/net/wireless/wl12xx/wl1271_rx.c
index 37d81ab6acc0..ca645f38109b 100644
--- a/drivers/net/wireless/wl12xx/wl1271_rx.c
+++ b/drivers/net/wireless/wl12xx/wl1271_rx.c
@@ -159,7 +159,7 @@ static void wl1271_rx_handle_data(struct wl1271 *wl, u32 length)
159 u8 *buf; 159 u8 *buf;
160 u8 beacon = 0; 160 u8 beacon = 0;
161 161
162 skb = dev_alloc_skb(length); 162 skb = __dev_alloc_skb(length, GFP_KERNEL);
163 if (!skb) { 163 if (!skb) {
164 wl1271_error("Couldn't allocate RX frame"); 164 wl1271_error("Couldn't allocate RX frame");
165 return; 165 return;
diff --git a/drivers/net/wireless/zd1211rw/Kconfig b/drivers/net/wireless/zd1211rw/Kconfig
index 74b31eafe72d..5f809695f71a 100644
--- a/drivers/net/wireless/zd1211rw/Kconfig
+++ b/drivers/net/wireless/zd1211rw/Kconfig
@@ -1,6 +1,6 @@
1config ZD1211RW 1config ZD1211RW
2 tristate "ZyDAS ZD1211/ZD1211B USB-wireless support" 2 tristate "ZyDAS ZD1211/ZD1211B USB-wireless support"
3 depends on USB && MAC80211 && WLAN_80211 && EXPERIMENTAL 3 depends on USB && MAC80211 && EXPERIMENTAL
4 select FW_LOADER 4 select FW_LOADER
5 ---help--- 5 ---help---
6 This is an experimental driver for the ZyDAS ZD1211/ZD1211B wireless 6 This is an experimental driver for the ZyDAS ZD1211/ZD1211B wireless
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-20 08:45:03 -0500