diff options
author | Vivek Natarajan <vivek.natraj@gmail.com> | 2009-08-14 01:57:16 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-08-20 11:35:51 -0400 |
commit | db91f2e4d410bf3011b3649b9257e5b3c60b25ff (patch) | |
tree | 0a9ee7cd004198ae7b6a76fb8f5aa5671b61e716 /drivers/net/wireless | |
parent | 1e711bee566e26f03e51d5a754e7c8a57e489f9f (diff) |
ath9k: Add open loop power control support for AR9287.
Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/calib.c | 44 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.c | 20 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/phy.h | 7 |
3 files changed, 52 insertions, 19 deletions
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c index 26d87527acbd..20f74b5b5703 100644 --- a/drivers/net/wireless/ath/ath9k/calib.c +++ b/drivers/net/wireless/ath/ath9k/calib.c | |||
@@ -729,26 +729,42 @@ s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan) | |||
729 | static void ath9k_olc_temp_compensation(struct ath_hw *ah) | 729 | static void ath9k_olc_temp_compensation(struct ath_hw *ah) |
730 | { | 730 | { |
731 | u32 rddata, i; | 731 | u32 rddata, i; |
732 | int delta, currPDADC, regval; | 732 | int delta, currPDADC, regval, slope; |
733 | 733 | ||
734 | rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); | 734 | rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); |
735 | |||
736 | currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); | 735 | currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); |
737 | 736 | ||
738 | if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G)) | ||
739 | delta = (currPDADC - ah->initPDADC + 4) / 8; | ||
740 | else | ||
741 | delta = (currPDADC - ah->initPDADC + 5) / 10; | ||
742 | 737 | ||
743 | if (delta != ah->PDADCdelta) { | 738 | if (OLC_FOR_AR9287_10_LATER) { |
744 | ah->PDADCdelta = delta; | 739 | if (ah->initPDADC == 0 || currPDADC == 0) { |
745 | for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) { | 740 | return; |
746 | regval = ah->originalGain[i] - delta; | 741 | } else { |
747 | if (regval < 0) | 742 | slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE); |
748 | regval = 0; | 743 | if (slope == 0) |
744 | delta = 0; | ||
745 | else | ||
746 | delta = ((currPDADC - ah->initPDADC)*4) / slope; | ||
747 | REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11, | ||
748 | AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta); | ||
749 | REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11, | ||
750 | AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta); | ||
751 | } | ||
752 | } else { | ||
753 | if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G)) | ||
754 | delta = (currPDADC - ah->initPDADC + 4) / 8; | ||
755 | else | ||
756 | delta = (currPDADC - ah->initPDADC + 5) / 10; | ||
757 | |||
758 | if (delta != ah->PDADCdelta) { | ||
759 | ah->PDADCdelta = delta; | ||
760 | for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) { | ||
761 | regval = ah->originalGain[i] - delta; | ||
762 | if (regval < 0) | ||
763 | regval = 0; | ||
749 | 764 | ||
750 | REG_RMW_FIELD(ah, AR_PHY_TX_GAIN_TBL1 + i * 4, | 765 | REG_RMW_FIELD(ah, AR_PHY_TX_GAIN_TBL1 + i * 4, |
751 | AR_PHY_TX_GAIN, regval); | 766 | AR_PHY_TX_GAIN, regval); |
767 | } | ||
752 | } | 768 | } |
753 | } | 769 | } |
754 | } | 770 | } |
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 9f1b34d9861a..125e689f7c5c 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
@@ -1332,11 +1332,21 @@ static void ath9k_olc_init(struct ath_hw *ah) | |||
1332 | { | 1332 | { |
1333 | u32 i; | 1333 | u32 i; |
1334 | 1334 | ||
1335 | for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) | 1335 | if (OLC_FOR_AR9287_10_LATER) { |
1336 | ah->originalGain[i] = | 1336 | REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, |
1337 | MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), | 1337 | AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL); |
1338 | AR_PHY_TX_GAIN); | 1338 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0, |
1339 | ah->PDADCdelta = 0; | 1339 | AR9287_AN_TXPC0_TXPCMODE, |
1340 | AR9287_AN_TXPC0_TXPCMODE_S, | ||
1341 | AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE); | ||
1342 | udelay(100); | ||
1343 | } else { | ||
1344 | for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) | ||
1345 | ah->originalGain[i] = | ||
1346 | MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), | ||
1347 | AR_PHY_TX_GAIN); | ||
1348 | ah->PDADCdelta = 0; | ||
1349 | } | ||
1340 | } | 1350 | } |
1341 | 1351 | ||
1342 | static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, | 1352 | static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, |
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h index e83cd4ab87f0..dfda6f444648 100644 --- a/drivers/net/wireless/ath/ath9k/phy.h +++ b/drivers/net/wireless/ath/ath9k/phy.h | |||
@@ -490,11 +490,18 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, | |||
490 | #define AR_PHY_TX_PWRCTRL9 0xa27C | 490 | #define AR_PHY_TX_PWRCTRL9 0xa27C |
491 | #define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 | 491 | #define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 |
492 | #define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 | 492 | #define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 |
493 | #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 | ||
494 | #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 | ||
493 | 495 | ||
494 | #define AR_PHY_TX_GAIN_TBL1 0xa300 | 496 | #define AR_PHY_TX_GAIN_TBL1 0xa300 |
495 | #define AR_PHY_TX_GAIN 0x0007F000 | 497 | #define AR_PHY_TX_GAIN 0x0007F000 |
496 | #define AR_PHY_TX_GAIN_S 12 | 498 | #define AR_PHY_TX_GAIN_S 12 |
497 | 499 | ||
500 | #define AR_PHY_CH0_TX_PWRCTRL11 0xa398 | ||
501 | #define AR_PHY_CH1_TX_PWRCTRL11 0xb398 | ||
502 | #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00 | ||
503 | #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10 | ||
504 | |||
498 | #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 | 505 | #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 |
499 | #define AR_PHY_MASK2_M_31_45 0xa3a4 | 506 | #define AR_PHY_MASK2_M_31_45 0xa3a4 |
500 | #define AR_PHY_MASK2_M_16_30 0xa3a8 | 507 | #define AR_PHY_MASK2_M_16_30 0xa3a8 |