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authorLarry Finger <Larry.Finger@lwfinger.net>2014-09-22 10:39:27 -0400
committerJohn W. Linville <linville@tuxdriver.com>2014-09-26 17:25:00 -0400
commit34ed780a6afc4df5e3285d20fac721c591e0724e (patch)
tree222af39b8ed4876c99cce6f6f6575f2ca0a53d76 /drivers/net/wireless
parent21e4b0726dc671c423e2dc9a85364716219c4502 (diff)
rtlwifi: Fix problems with building an allyesconfig
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/rtlwifi/core.c98
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/Makefile1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/hw.c7
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/phy.c4
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/phy.h1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.c96
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h126
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.c135
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.h94
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/Makefile1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/hw.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/pwrseqcmd.c130
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/pwrseqcmd.h98
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/Makefile1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/hw.c16
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/pwrseqcmd.c140
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/pwrseqcmd.h95
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/hw.c7
20 files changed, 223 insertions, 833 deletions
diff --git a/drivers/net/wireless/rtlwifi/core.c b/drivers/net/wireless/rtlwifi/core.c
index dea754aecdaf..10a3bc6dca80 100644
--- a/drivers/net/wireless/rtlwifi/core.c
+++ b/drivers/net/wireless/rtlwifi/core.c
@@ -28,6 +28,7 @@
28#include "cam.h" 28#include "cam.h"
29#include "base.h" 29#include "base.h"
30#include "ps.h" 30#include "ps.h"
31#include "pwrseqcmd.h"
31 32
32#include "btcoexist/rtl_btc.h" 33#include "btcoexist/rtl_btc.h"
33#include <linux/firmware.h> 34#include <linux/firmware.h>
@@ -1670,6 +1671,103 @@ static void rtl_op_flush(struct ieee80211_hw *hw,
1670 rtlpriv->intf_ops->flush(hw, queues, drop); 1671 rtlpriv->intf_ops->flush(hw, queues, drop);
1671} 1672}
1672 1673
1674/* Description:
1675 * This routine deals with the Power Configuration CMD
1676 * parsing for RTL8723/RTL8188E Series IC.
1677 * Assumption:
1678 * We should follow specific format that was released from HW SD.
1679 */
1680bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
1681 u8 faversion, u8 interface_type,
1682 struct wlan_pwr_cfg pwrcfgcmd[])
1683{
1684 struct wlan_pwr_cfg cfg_cmd = {0};
1685 bool polling_bit = false;
1686 u32 ary_idx = 0;
1687 u8 value = 0;
1688 u32 offset = 0;
1689 u32 polling_count = 0;
1690 u32 max_polling_cnt = 5000;
1691
1692 do {
1693 cfg_cmd = pwrcfgcmd[ary_idx];
1694 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1695 "rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), famsk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
1696 GET_PWR_CFG_OFFSET(cfg_cmd),
1697 GET_PWR_CFG_CUT_MASK(cfg_cmd),
1698 GET_PWR_CFG_FAB_MASK(cfg_cmd),
1699 GET_PWR_CFG_INTF_MASK(cfg_cmd),
1700 GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd),
1701 GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd));
1702
1703 if ((GET_PWR_CFG_FAB_MASK(cfg_cmd)&faversion) &&
1704 (GET_PWR_CFG_CUT_MASK(cfg_cmd)&cut_version) &&
1705 (GET_PWR_CFG_INTF_MASK(cfg_cmd)&interface_type)) {
1706 switch (GET_PWR_CFG_CMD(cfg_cmd)) {
1707 case PWR_CMD_READ:
1708 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1709 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
1710 break;
1711 case PWR_CMD_WRITE:
1712 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1713 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
1714 offset = GET_PWR_CFG_OFFSET(cfg_cmd);
1715
1716 /*Read the value from system register*/
1717 value = rtl_read_byte(rtlpriv, offset);
1718 value &= (~(GET_PWR_CFG_MASK(cfg_cmd)));
1719 value |= (GET_PWR_CFG_VALUE(cfg_cmd) &
1720 GET_PWR_CFG_MASK(cfg_cmd));
1721
1722 /*Write the value back to sytem register*/
1723 rtl_write_byte(rtlpriv, offset, value);
1724 break;
1725 case PWR_CMD_POLLING:
1726 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1727 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
1728 polling_bit = false;
1729 offset = GET_PWR_CFG_OFFSET(cfg_cmd);
1730
1731 do {
1732 value = rtl_read_byte(rtlpriv, offset);
1733
1734 value &= GET_PWR_CFG_MASK(cfg_cmd);
1735 if (value ==
1736 (GET_PWR_CFG_VALUE(cfg_cmd) &
1737 GET_PWR_CFG_MASK(cfg_cmd)))
1738 polling_bit = true;
1739 else
1740 udelay(10);
1741
1742 if (polling_count++ > max_polling_cnt)
1743 return false;
1744 } while (!polling_bit);
1745 break;
1746 case PWR_CMD_DELAY:
1747 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1748 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
1749 if (GET_PWR_CFG_VALUE(cfg_cmd) ==
1750 PWRSEQ_DELAY_US)
1751 udelay(GET_PWR_CFG_OFFSET(cfg_cmd));
1752 else
1753 mdelay(GET_PWR_CFG_OFFSET(cfg_cmd));
1754 break;
1755 case PWR_CMD_END:
1756 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1757 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
1758 return true;
1759 default:
1760 RT_ASSERT(false,
1761 "rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
1762 break;
1763 }
1764 }
1765 ary_idx++;
1766 } while (1);
1767
1768 return true;
1769}
1770EXPORT_SYMBOL(rtl_hal_pwrseqcmdparsing);
1673const struct ieee80211_ops rtl_ops = { 1771const struct ieee80211_ops rtl_ops = {
1674 .start = rtl_op_start, 1772 .start = rtl_op_start,
1675 .stop = rtl_op_stop, 1773 .stop = rtl_op_stop,
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/Makefile b/drivers/net/wireless/rtlwifi/rtl8188ee/Makefile
index 5b194e97f4b3..a85419a37651 100644
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/Makefile
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/Makefile
@@ -5,7 +5,6 @@ rtl8188ee-objs := \
5 led.o \ 5 led.o \
6 phy.o \ 6 phy.o \
7 pwrseq.o \ 7 pwrseq.o \
8 pwrseqcmd.o \
9 rf.o \ 8 rf.o \
10 sw.o \ 9 sw.o \
11 table.o \ 10 table.o \
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/hw.c b/drivers/net/wireless/rtlwifi/rtl8188ee/hw.c
index d4709e11504c..f74b7fb531c2 100644
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/hw.c
@@ -37,7 +37,6 @@
37#include "fw.h" 37#include "fw.h"
38#include "led.h" 38#include "led.h"
39#include "hw.h" 39#include "hw.h"
40#include "pwrseqcmd.h"
41#include "pwrseq.h" 40#include "pwrseq.h"
42 41
43#define LLT_CONFIG 5 42#define LLT_CONFIG 5
@@ -850,7 +849,7 @@ static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
850 /* HW Power on sequence */ 849 /* HW Power on sequence */
851 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 850 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
852 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 851 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
853 RTL8188E_NIC_ENABLE_FLOW)) { 852 RTL8188EE_NIC_ENABLE_FLOW)) {
854 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 853 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
855 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n"); 854 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
856 return false; 855 return false;
@@ -1422,7 +1421,7 @@ static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1422 1421
1423 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1422 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1424 PWR_INTF_PCI_MSK, 1423 PWR_INTF_PCI_MSK,
1425 RTL8188E_NIC_LPS_ENTER_FLOW); 1424 RTL8188EE_NIC_LPS_ENTER_FLOW);
1426 1425
1427 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1426 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1428 1427
@@ -1437,7 +1436,7 @@ static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1437 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0)))); 1436 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1438 1437
1439 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1438 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1440 PWR_INTF_PCI_MSK, RTL8188E_NIC_DISABLE_FLOW); 1439 PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);
1441 1440
1442 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1); 1441 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1443 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3)))); 1442 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/phy.c b/drivers/net/wireless/rtlwifi/rtl8188ee/phy.c
index 2acc67d966d5..3f6c59cdeaba 100644
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/phy.c
@@ -2100,10 +2100,6 @@ void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw)
2100 rtlphy->lck_inprogress = false; 2100 rtlphy->lck_inprogress = false;
2101} 2101}
2102 2102
2103void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2104{
2105}
2106
2107void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) 2103void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2108{ 2104{
2109 _rtl88e_phy_set_rfpath_switch(hw, bmain, false); 2105 _rtl88e_phy_set_rfpath_switch(hw, bmain, false);
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/phy.h b/drivers/net/wireless/rtlwifi/rtl8188ee/phy.h
index 4dae55b7c535..b29bd77210f4 100644
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/phy.h
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/phy.h
@@ -222,7 +222,6 @@ void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
222void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw); 222void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
223u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw); 223u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw);
224void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery); 224void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
225void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
226void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw); 225void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw);
227void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain); 226void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
228bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 227bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.c b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.c
index e4e030615332..ef28c8ea1e84 100644
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.c
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.c
@@ -28,78 +28,78 @@
28 28
29/* drivers should parse below arrays and do the corresponding actions */ 29/* drivers should parse below arrays and do the corresponding actions */
30/*3 Power on Array*/ 30/*3 Power on Array*/
31struct wlan_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 31struct wlan_pwr_cfg rtl8188ee_power_on_flow[RTL8188EE_TRANS_CARDEMU_TO_ACT_STEPS
32 + RTL8188E_TRANS_END_STEPS] = { 32 + RTL8188EE_TRANS_END_STEPS] = {
33 RTL8188E_TRANS_CARDEMU_TO_ACT 33 RTL8188EE_TRANS_CARDEMU_TO_ACT
34 RTL8188E_TRANS_END 34 RTL8188EE_TRANS_END
35}; 35};
36 36
37/*3Radio off GPIO Array */ 37/*3Radio off GPIO Array */
38struct wlan_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 38struct wlan_pwr_cfg rtl8188ee_radio_off_flow[RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS
39 + RTL8188E_TRANS_END_STEPS] = { 39 + RTL8188EE_TRANS_END_STEPS] = {
40 RTL8188E_TRANS_ACT_TO_CARDEMU 40 RTL8188EE_TRANS_ACT_TO_CARDEMU
41 RTL8188E_TRANS_END 41 RTL8188EE_TRANS_END
42}; 42};
43 43
44/*3Card Disable Array*/ 44/*3Card Disable Array*/
45struct wlan_pwr_cfg rtl8188E_card_disable_flow 45struct wlan_pwr_cfg rtl8188ee_card_disable_flow
46 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 46 [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
47 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + 47 RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
48 RTL8188E_TRANS_END_STEPS] = { 48 RTL8188EE_TRANS_END_STEPS] = {
49 RTL8188E_TRANS_ACT_TO_CARDEMU 49 RTL8188EE_TRANS_ACT_TO_CARDEMU
50 RTL8188E_TRANS_CARDEMU_TO_CARDDIS 50 RTL8188EE_TRANS_CARDEMU_TO_CARDDIS
51 RTL8188E_TRANS_END 51 RTL8188EE_TRANS_END
52}; 52};
53 53
54/*3 Card Enable Array*/ 54/*3 Card Enable Array*/
55struct wlan_pwr_cfg rtl8188E_card_enable_flow 55struct wlan_pwr_cfg rtl8188ee_card_enable_flow
56 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 56 [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
57 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + 57 RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
58 RTL8188E_TRANS_END_STEPS] = { 58 RTL8188EE_TRANS_END_STEPS] = {
59 RTL8188E_TRANS_CARDDIS_TO_CARDEMU 59 RTL8188EE_TRANS_CARDDIS_TO_CARDEMU
60 RTL8188E_TRANS_CARDEMU_TO_ACT 60 RTL8188EE_TRANS_CARDEMU_TO_ACT
61 RTL8188E_TRANS_END 61 RTL8188EE_TRANS_END
62}; 62};
63 63
64/*3Suspend Array*/ 64/*3Suspend Array*/
65struct wlan_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 65struct wlan_pwr_cfg rtl8188ee_suspend_flow[RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS
66 + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 66 + RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS
67 + RTL8188E_TRANS_END_STEPS] = { 67 + RTL8188EE_TRANS_END_STEPS] = {
68 RTL8188E_TRANS_ACT_TO_CARDEMU 68 RTL8188EE_TRANS_ACT_TO_CARDEMU
69 RTL8188E_TRANS_CARDEMU_TO_SUS 69 RTL8188EE_TRANS_CARDEMU_TO_SUS
70 RTL8188E_TRANS_END 70 RTL8188EE_TRANS_END
71}; 71};
72 72
73/*3 Resume Array*/ 73/*3 Resume Array*/
74struct wlan_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 74struct wlan_pwr_cfg rtl8188ee_resume_flow[RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS
75 + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 75 + RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS
76 + RTL8188E_TRANS_END_STEPS] = { 76 + RTL8188EE_TRANS_END_STEPS] = {
77 RTL8188E_TRANS_SUS_TO_CARDEMU 77 RTL8188EE_TRANS_SUS_TO_CARDEMU
78 RTL8188E_TRANS_CARDEMU_TO_ACT 78 RTL8188EE_TRANS_CARDEMU_TO_ACT
79 RTL8188E_TRANS_END 79 RTL8188EE_TRANS_END
80}; 80};
81 81
82/*3HWPDN Array*/ 82/*3HWPDN Array*/
83struct wlan_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 83struct wlan_pwr_cfg rtl8188ee_hwpdn_flow[RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS
84 + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 84 + RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS
85 + RTL8188E_TRANS_END_STEPS] = { 85 + RTL8188EE_TRANS_END_STEPS] = {
86 RTL8188E_TRANS_ACT_TO_CARDEMU 86 RTL8188EE_TRANS_ACT_TO_CARDEMU
87 RTL8188E_TRANS_CARDEMU_TO_PDN 87 RTL8188EE_TRANS_CARDEMU_TO_PDN
88 RTL8188E_TRANS_END 88 RTL8188EE_TRANS_END
89}; 89};
90 90
91/*3 Enter LPS */ 91/*3 Enter LPS */
92struct wlan_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS 92struct wlan_pwr_cfg rtl8188ee_enter_lps_flow[RTL8188EE_TRANS_ACT_TO_LPS_STEPS
93 + RTL8188E_TRANS_END_STEPS] = { 93 + RTL8188EE_TRANS_END_STEPS] = {
94 /*FW behavior*/ 94 /*FW behavior*/
95 RTL8188E_TRANS_ACT_TO_LPS 95 RTL8188EE_TRANS_ACT_TO_LPS
96 RTL8188E_TRANS_END 96 RTL8188EE_TRANS_END
97}; 97};
98 98
99/*3 Leave LPS */ 99/*3 Leave LPS */
100struct wlan_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS 100struct wlan_pwr_cfg rtl8188ee_leave_lps_flow[RTL8188EE_TRANS_LPS_TO_ACT_STEPS
101 + RTL8188E_TRANS_END_STEPS] = { 101 + RTL8188EE_TRANS_END_STEPS] = {
102 /*FW behavior*/ 102 /*FW behavior*/
103 RTL8188E_TRANS_LPS_TO_ACT 103 RTL8188EE_TRANS_LPS_TO_ACT
104 RTL8188E_TRANS_END 104 RTL8188EE_TRANS_END
105}; 105};
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h
index 970afe6ef4d2..79103347d967 100644
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h
@@ -27,7 +27,7 @@
27#define __RTL8723E_PWRSEQ_H__ 27#define __RTL8723E_PWRSEQ_H__
28 28
29#include "pwrseqcmd.h" 29#include "pwrseqcmd.h"
30/* Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd 30/* Check document WM-20110607-Paul-RTL8188EE_Power_Architecture-R02.vsd
31 * There are 6 HW Power States: 31 * There are 6 HW Power States:
32 * 0: POFF--Power Off 32 * 0: POFF--Power Off
33 * 1: PDN--Power Down 33 * 1: PDN--Power Down
@@ -46,24 +46,24 @@
46 * TRANS_LPS_TO_ACT 46 * TRANS_LPS_TO_ACT
47 * 47 *
48 * TRANS_END 48 * TRANS_END
49 * PWR SEQ Version: rtl8188E_PwrSeq_V09.h 49 * PWR SEQ Version: rtl8188ee_PwrSeq_V09.h
50 */ 50 */
51 51
52#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10 52#define RTL8188EE_TRANS_CARDEMU_TO_ACT_STEPS 10
53#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10 53#define RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS 10
54#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10 54#define RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS 10
55#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10 55#define RTL8188EE_TRANS_SUS_TO_CARDEMU_STEPS 10
56#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10 56#define RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS 10
57#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10 57#define RTL8188EE_TRANS_PDN_TO_CARDEMU_STEPS 10
58#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15 58#define RTL8188EE_TRANS_ACT_TO_LPS_STEPS 15
59#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15 59#define RTL8188EE_TRANS_LPS_TO_ACT_STEPS 15
60#define RTL8188E_TRANS_END_STEPS 1 60#define RTL8188EE_TRANS_END_STEPS 1
61 61
62/* The following macros have the following format: 62/* The following macros have the following format:
63 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value 63 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
64 * comments }, 64 * comments },
65 */ 65 */
66#define RTL8188E_TRANS_CARDEMU_TO_ACT \ 66#define RTL8188EE_TRANS_CARDEMU_TO_ACT \
67 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 67 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
68 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \ 68 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \
69 /* wait till 0x04[17] = 1 power ready*/}, \ 69 /* wait till 0x04[17] = 1 power ready*/}, \
@@ -92,7 +92,7 @@
92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \ 92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
93 /*SDIO Driving*/}, 93 /*SDIO Driving*/},
94 94
95#define RTL8188E_TRANS_ACT_TO_CARDEMU \ 95#define RTL8188EE_TRANS_ACT_TO_CARDEMU \
96 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 96 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \ 97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
98 /*0x1F[7:0] = 0 turn off RF*/}, \ 98 /*0x1F[7:0] = 0 turn off RF*/}, \
@@ -106,7 +106,7 @@
106 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0 \ 106 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0 \
107 /*wait till 0x04[9] = 0 polling until return 0 to disable*/}, 107 /*wait till 0x04[9] = 0 polling until return 0 to disable*/},
108 108
109#define RTL8188E_TRANS_CARDEMU_TO_SUS \ 109#define RTL8188EE_TRANS_CARDEMU_TO_SUS \
110 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 110 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
111 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \ 111 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
112 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3) \ 112 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3) \
@@ -133,7 +133,7 @@
133 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \ 133 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \
134 /*wait power state to suspend*/}, 134 /*wait power state to suspend*/},
135 135
136#define RTL8188E_TRANS_SUS_TO_CARDEMU \ 136#define RTL8188EE_TRANS_SUS_TO_CARDEMU \
137 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 137 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
138 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \ 138 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \
139 /*Set SDIO suspend local register*/}, \ 139 /*Set SDIO suspend local register*/}, \
@@ -144,7 +144,7 @@
144 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0 \ 144 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0 \
145 /*0x04[12:11] = 2b'01enable WL suspend*/}, 145 /*0x04[12:11] = 2b'01enable WL suspend*/},
146 146
147#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ 147#define RTL8188EE_TRANS_CARDEMU_TO_CARDDIS \
148 {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 148 {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
149 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \ 149 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
150 /*0x24[23] = 2b'01 schmit trigger */}, \ 150 /*0x24[23] = 2b'01 schmit trigger */}, \
@@ -170,7 +170,7 @@
170 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \ 170 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \
171 /*wait power state to suspend*/}, 171 /*wait power state to suspend*/},
172 172
173#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ 173#define RTL8188EE_TRANS_CARDDIS_TO_CARDEMU \
174 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 174 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
175 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \ 175 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \
176 /*Set SDIO suspend local register*/}, \ 176 /*Set SDIO suspend local register*/}, \
@@ -181,18 +181,18 @@
181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0 \ 181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0 \
182 /*0x04[12:11] = 2b'01enable WL suspend*/}, 182 /*0x04[12:11] = 2b'01enable WL suspend*/},
183 183
184#define RTL8188E_TRANS_CARDEMU_TO_PDN \ 184#define RTL8188EE_TRANS_CARDEMU_TO_PDN \
185 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 185 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
186 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0/* 0x04[16] = 0*/}, \ 186 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0/* 0x04[16] = 0*/}, \
187 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 187 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
188 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \ 188 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
189 /* 0x04[15] = 1*/}, 189 /* 0x04[15] = 1*/},
190 190
191#define RTL8188E_TRANS_PDN_TO_CARDEMU \ 191#define RTL8188EE_TRANS_PDN_TO_CARDEMU \
192 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 192 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
193 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/}, 193 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/},
194 194
195#define RTL8188E_TRANS_ACT_TO_LPS \ 195#define RTL8188EE_TRANS_ACT_TO_LPS \
196 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 196 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
197 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \ 197 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
198 /*Tx Pause*/}, \ 198 /*Tx Pause*/}, \
@@ -225,7 +225,7 @@
225 /*Respond TxOK to scheduler*/}, 225 /*Respond TxOK to scheduler*/},
226 226
227 227
228#define RTL8188E_TRANS_LPS_TO_ACT \ 228#define RTL8188EE_TRANS_LPS_TO_ACT \
229 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 229 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
230 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \ 230 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
231 /*SDIO RPWM*/}, \ 231 /*SDIO RPWM*/}, \
@@ -260,52 +260,52 @@
260 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \ 260 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
261 /*. 0x522 = 0*/}, 261 /*. 0x522 = 0*/},
262 262
263#define RTL8188E_TRANS_END \ 263#define RTL8188EE_TRANS_END \
264 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 264 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
265 0, PWR_CMD_END, 0, 0} 265 0, PWR_CMD_END, 0, 0}
266 266
267extern struct wlan_pwr_cfg rtl8188E_power_on_flow 267extern struct wlan_pwr_cfg rtl8188ee_power_on_flow
268 [RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + 268 [RTL8188EE_TRANS_CARDEMU_TO_ACT_STEPS +
269 RTL8188E_TRANS_END_STEPS]; 269 RTL8188EE_TRANS_END_STEPS];
270extern struct wlan_pwr_cfg rtl8188E_radio_off_flow 270extern struct wlan_pwr_cfg rtl8188ee_radio_off_flow
271 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 271 [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
272 RTL8188E_TRANS_END_STEPS]; 272 RTL8188EE_TRANS_END_STEPS];
273extern struct wlan_pwr_cfg rtl8188E_card_disable_flow 273extern struct wlan_pwr_cfg rtl8188ee_card_disable_flow
274 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 274 [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
275 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + 275 RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
276 RTL8188E_TRANS_END_STEPS]; 276 RTL8188EE_TRANS_END_STEPS];
277extern struct wlan_pwr_cfg rtl8188E_card_enable_flow 277extern struct wlan_pwr_cfg rtl8188ee_card_enable_flow
278 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 278 [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
279 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + 279 RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
280 RTL8188E_TRANS_END_STEPS]; 280 RTL8188EE_TRANS_END_STEPS];
281extern struct wlan_pwr_cfg rtl8188E_suspend_flow 281extern struct wlan_pwr_cfg rtl8188ee_suspend_flow
282 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 282 [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
283 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + 283 RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS +
284 RTL8188E_TRANS_END_STEPS]; 284 RTL8188EE_TRANS_END_STEPS];
285extern struct wlan_pwr_cfg rtl8188E_resume_flow 285extern struct wlan_pwr_cfg rtl8188ee_resume_flow
286 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 286 [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
287 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + 287 RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS +
288 RTL8188E_TRANS_END_STEPS]; 288 RTL8188EE_TRANS_END_STEPS];
289extern struct wlan_pwr_cfg rtl8188E_hwpdn_flow 289extern struct wlan_pwr_cfg rtl8188ee_hwpdn_flow
290 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 290 [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
291 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + 291 RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
292 RTL8188E_TRANS_END_STEPS]; 292 RTL8188EE_TRANS_END_STEPS];
293extern struct wlan_pwr_cfg rtl8188E_enter_lps_flow 293extern struct wlan_pwr_cfg rtl8188ee_enter_lps_flow
294 [RTL8188E_TRANS_ACT_TO_LPS_STEPS + 294 [RTL8188EE_TRANS_ACT_TO_LPS_STEPS +
295 RTL8188E_TRANS_END_STEPS]; 295 RTL8188EE_TRANS_END_STEPS];
296extern struct wlan_pwr_cfg rtl8188E_leave_lps_flow 296extern struct wlan_pwr_cfg rtl8188ee_leave_lps_flow
297 [RTL8188E_TRANS_LPS_TO_ACT_STEPS + 297 [RTL8188EE_TRANS_LPS_TO_ACT_STEPS +
298 RTL8188E_TRANS_END_STEPS]; 298 RTL8188EE_TRANS_END_STEPS];
299 299
300/* RTL8723 Power Configuration CMDs for PCIe interface */ 300/* RTL8723 Power Configuration CMDs for PCIe interface */
301#define RTL8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow 301#define RTL8188EE_NIC_PWR_ON_FLOW rtl8188ee_power_on_flow
302#define RTL8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow 302#define RTL8188EE_NIC_RF_OFF_FLOW rtl8188ee_radio_off_flow
303#define RTL8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow 303#define RTL8188EE_NIC_DISABLE_FLOW rtl8188ee_card_disable_flow
304#define RTL8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow 304#define RTL8188EE_NIC_ENABLE_FLOW rtl8188ee_card_enable_flow
305#define RTL8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow 305#define RTL8188EE_NIC_SUSPEND_FLOW rtl8188ee_suspend_flow
306#define RTL8188E_NIC_RESUME_FLOW rtl8188E_resume_flow 306#define RTL8188EE_NIC_RESUME_FLOW rtl8188ee_resume_flow
307#define RTL8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow 307#define RTL8188EE_NIC_PDN_FLOW rtl8188ee_hwpdn_flow
308#define RTL8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow 308#define RTL8188EE_NIC_LPS_ENTER_FLOW rtl8188ee_enter_lps_flow
309#define RTL8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow 309#define RTL8188EE_NIC_LPS_LEAVE_FLOW rtl8188ee_leave_lps_flow
310 310
311#endif 311#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.c b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.c
deleted file mode 100644
index eceedcd38974..000000000000
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.c
+++ /dev/null
@@ -1,135 +0,0 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "pwrseqcmd.h"
27#include "pwrseq.h"
28
29
30/* Description:
31* This routine deal with the Power Configuration CMDs
32* parsing for RTL8723/RTL8188E Series IC.
33* Assumption:
34* We should follow specific format which was released from HW SD.
35*
36* 2011.07.07, added by Roger.
37*/
38bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
39 u8 fab_version, u8 interface_type,
40 struct wlan_pwr_cfg pwrcfgcmd[])
41
42{
43 struct wlan_pwr_cfg pwr_cfg_cmd = {0};
44 bool b_polling_bit = false;
45 u32 ary_idx = 0;
46 u8 value = 0;
47 u32 offset = 0;
48 u32 polling_count = 0;
49 u32 max_polling_cnt = 5000;
50
51 do {
52 pwr_cfg_cmd = pwrcfgcmd[ary_idx];
53 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
54 "rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), fab_msk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
55 GET_PWR_CFG_OFFSET(pwr_cfg_cmd),
56 GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd),
57 GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd),
58 GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd),
59 GET_PWR_CFG_BASE(pwr_cfg_cmd),
60 GET_PWR_CFG_CMD(pwr_cfg_cmd),
61 GET_PWR_CFG_MASK(pwr_cfg_cmd),
62 GET_PWR_CFG_VALUE(pwr_cfg_cmd));
63
64 if ((GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd)&fab_version) &&
65 (GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd)&cut_version) &&
66 (GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd)&interface_type)) {
67 switch (GET_PWR_CFG_CMD(pwr_cfg_cmd)) {
68 case PWR_CMD_READ:
69 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
70 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
71 break;
72 case PWR_CMD_WRITE:
73 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
74 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
75 offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
76
77 /*Read the value from system register*/
78 value = rtl_read_byte(rtlpriv, offset);
79 value &= (~(GET_PWR_CFG_MASK(pwr_cfg_cmd)));
80 value |= (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
81 & GET_PWR_CFG_MASK(pwr_cfg_cmd));
82
83 /*Write the back to sytem register*/
84 rtl_write_byte(rtlpriv, offset, value);
85 break;
86 case PWR_CMD_POLLING:
87 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
88 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
89 b_polling_bit = false;
90 offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
91
92 do {
93 value = rtl_read_byte(rtlpriv, offset);
94
95 value &= GET_PWR_CFG_MASK(pwr_cfg_cmd);
96 if (value ==
97 (GET_PWR_CFG_VALUE(pwr_cfg_cmd) &
98 GET_PWR_CFG_MASK(pwr_cfg_cmd)))
99 b_polling_bit = true;
100 else
101 udelay(10);
102
103 if (polling_count++ > max_polling_cnt) {
104 RT_TRACE(rtlpriv, COMP_INIT,
105 DBG_LOUD,
106 "polling fail in pwrseqcmd\n");
107 return false;
108 }
109 } while (!b_polling_bit);
110
111 break;
112 case PWR_CMD_DELAY:
113 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
114 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
115 if (GET_PWR_CFG_VALUE(pwr_cfg_cmd) ==
116 PWRSEQ_DELAY_US)
117 udelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
118 else
119 mdelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
120 break;
121 case PWR_CMD_END:
122 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
123 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
124 return true;
125 default:
126 RT_ASSERT(false,
127 "rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
128 break;
129 }
130 }
131 ary_idx++;
132 } while (1);
133
134 return true;
135}
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.h b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.h
deleted file mode 100644
index dff77a5cef23..000000000000
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.h
+++ /dev/null
@@ -1,94 +0,0 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8723E_PWRSEQCMD_H__
27#define __RTL8723E_PWRSEQCMD_H__
28
29#include "../wifi.h"
30/*---------------------------------------------*/
31/* The value of cmd: 4 bits */
32/*---------------------------------------------*/
33#define PWR_CMD_READ 0x00
34#define PWR_CMD_WRITE 0x01
35#define PWR_CMD_POLLING 0x02
36#define PWR_CMD_DELAY 0x03
37#define PWR_CMD_END 0x04
38
39/* define the base address of each block */
40#define PWR_BASEADDR_MAC 0x00
41#define PWR_BASEADDR_USB 0x01
42#define PWR_BASEADDR_PCIE 0x02
43#define PWR_BASEADDR_SDIO 0x03
44
45#define PWR_INTF_SDIO_MSK BIT(0)
46#define PWR_INTF_USB_MSK BIT(1)
47#define PWR_INTF_PCI_MSK BIT(2)
48#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
49
50#define PWR_FAB_TSMC_MSK BIT(0)
51#define PWR_FAB_UMC_MSK BIT(1)
52#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
53
54#define PWR_CUT_TESTCHIP_MSK BIT(0)
55#define PWR_CUT_A_MSK BIT(1)
56#define PWR_CUT_B_MSK BIT(2)
57#define PWR_CUT_C_MSK BIT(3)
58#define PWR_CUT_D_MSK BIT(4)
59#define PWR_CUT_E_MSK BIT(5)
60#define PWR_CUT_F_MSK BIT(6)
61#define PWR_CUT_G_MSK BIT(7)
62#define PWR_CUT_ALL_MSK 0xFF
63
64enum pwrseq_delay_unit {
65 PWRSEQ_DELAY_US,
66 PWRSEQ_DELAY_MS,
67};
68
69struct wlan_pwr_cfg {
70 u16 offset;
71 u8 cut_msk;
72 u8 fab_msk:4;
73 u8 interface_msk:4;
74 u8 base:4;
75 u8 cmd:4;
76 u8 msk;
77 u8 value;
78
79};
80
81#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
82#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
83#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
84#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
85#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
86#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
87#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
88#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
89
90bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
91 u8 fab_version, u8 interface_type,
92 struct wlan_pwr_cfg pwrcfgcmd[]);
93
94#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/Makefile b/drivers/net/wireless/rtlwifi/rtl8723ae/Makefile
index 4ed731f09b1f..9c34a85fdb89 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/Makefile
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/Makefile
@@ -10,7 +10,6 @@ rtl8723ae-objs := \
10 led.o \ 10 led.o \
11 phy.o \ 11 phy.o \
12 pwrseq.o \ 12 pwrseq.o \
13 pwrseqcmd.o \
14 rf.o \ 13 rf.o \
15 sw.o \ 14 sw.o \
16 table.o \ 15 table.o \
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
index dd8e76cb03aa..3338206af947 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
@@ -43,7 +43,7 @@
43#include "../rtl8723com/fw_common.h" 43#include "../rtl8723com/fw_common.h"
44#include "led.h" 44#include "led.h"
45#include "hw.h" 45#include "hw.h"
46#include "pwrseqcmd.h" 46#include "../pwrseqcmd.h"
47#include "pwrseq.h" 47#include "pwrseq.h"
48#include "btc.h" 48#include "btc.h"
49 49
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.c b/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.c
index df6ca9a57f7f..f907d7fd1ea4 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.c
@@ -27,7 +27,7 @@
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29 29
30#include "pwrseqcmd.h" 30#include "../pwrseqcmd.h"
31#include "pwrseq.h" 31#include "pwrseq.h"
32 32
33/* drivers should parse arrays below and do the corresponding actions */ 33/* drivers should parse arrays below and do the corresponding actions */
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseqcmd.c b/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseqcmd.c
deleted file mode 100644
index 239eb4473dd1..000000000000
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseqcmd.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "pwrseqcmd.h"
31#include "pwrseq.h"
32
33/* Description:
34 * This routine deals with the Power Configuration CMD
35 * parsing for RTL8723/RTL8188E Series IC.
36 * Assumption:
37 * We should follow specific format that was released from HW SD.
38 */
39bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
40 u8 faversion, u8 interface_type,
41 struct wlan_pwr_cfg pwrcfgcmd[])
42{
43 struct wlan_pwr_cfg cfg_cmd = {0};
44 bool polling_bit = false;
45 u32 ary_idx = 0;
46 u8 value = 0;
47 u32 offset = 0;
48 u32 polling_count = 0;
49 u32 max_polling_cnt = 5000;
50
51 do {
52 cfg_cmd = pwrcfgcmd[ary_idx];
53 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
54 "rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), famsk(%#x),"
55 "interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
56 GET_PWR_CFG_OFFSET(cfg_cmd),
57 GET_PWR_CFG_CUT_MASK(cfg_cmd),
58 GET_PWR_CFG_FAB_MASK(cfg_cmd),
59 GET_PWR_CFG_INTF_MASK(cfg_cmd),
60 GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd),
61 GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd));
62
63 if ((GET_PWR_CFG_FAB_MASK(cfg_cmd)&faversion) &&
64 (GET_PWR_CFG_CUT_MASK(cfg_cmd)&cut_version) &&
65 (GET_PWR_CFG_INTF_MASK(cfg_cmd)&interface_type)) {
66 switch (GET_PWR_CFG_CMD(cfg_cmd)) {
67 case PWR_CMD_READ:
68 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
69 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
70 break;
71 case PWR_CMD_WRITE:
72 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
73 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
74 offset = GET_PWR_CFG_OFFSET(cfg_cmd);
75
76 /*Read the value from system register*/
77 value = rtl_read_byte(rtlpriv, offset);
78 value &= (~(GET_PWR_CFG_MASK(cfg_cmd)));
79 value |= (GET_PWR_CFG_VALUE(cfg_cmd) &
80 GET_PWR_CFG_MASK(cfg_cmd));
81
82 /*Write the value back to sytem register*/
83 rtl_write_byte(rtlpriv, offset, value);
84 break;
85 case PWR_CMD_POLLING:
86 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
87 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
88 polling_bit = false;
89 offset = GET_PWR_CFG_OFFSET(cfg_cmd);
90
91 do {
92 value = rtl_read_byte(rtlpriv, offset);
93
94 value &= GET_PWR_CFG_MASK(cfg_cmd);
95 if (value ==
96 (GET_PWR_CFG_VALUE(cfg_cmd)
97 & GET_PWR_CFG_MASK(cfg_cmd)))
98 polling_bit = true;
99 else
100 udelay(10);
101
102 if (polling_count++ > max_polling_cnt)
103 return false;
104 } while (!polling_bit);
105 break;
106 case PWR_CMD_DELAY:
107 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
108 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
109 if (GET_PWR_CFG_VALUE(cfg_cmd) ==
110 PWRSEQ_DELAY_US)
111 udelay(GET_PWR_CFG_OFFSET(cfg_cmd));
112 else
113 mdelay(GET_PWR_CFG_OFFSET(cfg_cmd));
114 break;
115 case PWR_CMD_END:
116 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
117 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
118 return true;
119 default:
120 RT_ASSERT(false,
121 "rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
122 break;
123 }
124
125 }
126 ary_idx++;
127 } while (1);
128
129 return true;
130}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseqcmd.h b/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseqcmd.h
deleted file mode 100644
index 6e0f3ea37ec0..000000000000
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseqcmd.h
+++ /dev/null
@@ -1,98 +0,0 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8723E_PWRSEQCMD_H__
31#define __RTL8723E_PWRSEQCMD_H__
32
33#include "../wifi.h"
34/*---------------------------------------------
35 * 3 The value of cmd: 4 bits
36 *---------------------------------------------
37 */
38#define PWR_CMD_READ 0x00
39#define PWR_CMD_WRITE 0x01
40#define PWR_CMD_POLLING 0x02
41#define PWR_CMD_DELAY 0x03
42#define PWR_CMD_END 0x04
43
44/* define the base address of each block */
45#define PWR_BASEADDR_MAC 0x00
46#define PWR_BASEADDR_USB 0x01
47#define PWR_BASEADDR_PCIE 0x02
48#define PWR_BASEADDR_SDIO 0x03
49
50#define PWR_INTF_SDIO_MSK BIT(0)
51#define PWR_INTF_USB_MSK BIT(1)
52#define PWR_INTF_PCI_MSK BIT(2)
53#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
54
55#define PWR_FAB_TSMC_MSK BIT(0)
56#define PWR_FAB_UMC_MSK BIT(1)
57#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
58
59#define PWR_CUT_TESTCHIP_MSK BIT(0)
60#define PWR_CUT_A_MSK BIT(1)
61#define PWR_CUT_B_MSK BIT(2)
62#define PWR_CUT_C_MSK BIT(3)
63#define PWR_CUT_D_MSK BIT(4)
64#define PWR_CUT_E_MSK BIT(5)
65#define PWR_CUT_F_MSK BIT(6)
66#define PWR_CUT_G_MSK BIT(7)
67#define PWR_CUT_ALL_MSK 0xFF
68
69enum pwrseq_delay_unit {
70 PWRSEQ_DELAY_US,
71 PWRSEQ_DELAY_MS,
72};
73
74struct wlan_pwr_cfg {
75 u16 offset;
76 u8 cut_msk;
77 u8 fab_msk:4;
78 u8 interface_msk:4;
79 u8 base:4;
80 u8 cmd:4;
81 u8 msk;
82 u8 value;
83};
84
85#define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset)
86#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk)
87#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk)
88#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk)
89#define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base)
90#define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd)
91#define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk)
92#define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value)
93
94bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
95 u8 fab_version, u8 interface_type,
96 struct wlan_pwr_cfg pwrcfgcmd[]);
97
98#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/Makefile b/drivers/net/wireless/rtlwifi/rtl8723be/Makefile
index 4a75aab0539a..59e416abd93a 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/Makefile
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/Makefile
@@ -8,7 +8,6 @@ rtl8723be-objs := \
8 led.o \ 8 led.o \
9 phy.o \ 9 phy.o \
10 pwrseq.o \ 10 pwrseq.o \
11 pwrseqcmd.o \
12 rf.o \ 11 rf.o \
13 sw.o \ 12 sw.o \
14 table.o \ 13 table.o \
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/hw.c b/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
index 1b939183f39d..c0689c1d8d76 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
@@ -39,7 +39,7 @@
39#include "../rtl8723com/fw_common.h" 39#include "../rtl8723com/fw_common.h"
40#include "led.h" 40#include "led.h"
41#include "hw.h" 41#include "hw.h"
42#include "pwrseqcmd.h" 42#include "../pwrseqcmd.h"
43#include "pwrseq.h" 43#include "pwrseq.h"
44#include "../btcoexist/rtl_btc.h" 44#include "../btcoexist/rtl_btc.h"
45 45
@@ -815,9 +815,9 @@ static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
815 mac_func_enable = false; 815 mac_func_enable = false;
816 816
817 /* HW Power on sequence */ 817 /* HW Power on sequence */
818 if (!rtlbe_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 818 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
819 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 819 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
820 RTL8723_NIC_ENABLE_FLOW)) { 820 RTL8723_NIC_ENABLE_FLOW)) {
821 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 821 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
822 "init MAC Fail as power on failure\n"); 822 "init MAC Fail as power on failure\n");
823 return false; 823 return false;
@@ -1306,8 +1306,8 @@ static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1306 1306
1307 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1307 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1308 /* 1. Run LPS WL RFOFF flow */ 1308 /* 1. Run LPS WL RFOFF flow */
1309 rtlbe_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1309 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1310 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW); 1310 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1311 1311
1312 /* 2. 0x1F[7:0] = 0 */ 1312 /* 2. 0x1F[7:0] = 0 */
1313 /* turn off RF */ 1313 /* turn off RF */
@@ -1325,8 +1325,8 @@ static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1325 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1325 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1326 1326
1327 /* HW card disable configuration. */ 1327 /* HW card disable configuration. */
1328 rtlbe_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1328 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1329 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW); 1329 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1330 1330
1331 /* Reset MCU IO Wrapper */ 1331 /* Reset MCU IO Wrapper */
1332 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1332 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.c b/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.c
index b5167e73fecf..a1bb1f6116fb 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.c
@@ -23,7 +23,7 @@
23 * 23 *
24 *****************************************************************************/ 24 *****************************************************************************/
25 25
26#include "pwrseqcmd.h" 26#include "../pwrseqcmd.h"
27#include "pwrseq.h" 27#include "pwrseq.h"
28 28
29 29
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/pwrseqcmd.c b/drivers/net/wireless/rtlwifi/rtl8723be/pwrseqcmd.c
deleted file mode 100644
index cf57a4964ad3..000000000000
--- a/drivers/net/wireless/rtlwifi/rtl8723be/pwrseqcmd.c
+++ /dev/null
@@ -1,140 +0,0 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "pwrseqcmd.h"
27#include "pwrseq.h"
28
29/* Description:
30 * This routine deal with the Power Configuration CMDs
31 * parsing for RTL8723/RTL8188E Series IC.
32 * Assumption:
33 * We should follow specific format which was released from HW SD.
34 *
35 * 2011.07.07, added by Roger.
36 */
37bool rtlbe_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
38 u8 fab_version, u8 interface_type,
39 struct wlan_pwr_cfg pwrcfgcmd[])
40
41{
42 struct wlan_pwr_cfg pwr_cfg_cmd = {0};
43 bool b_polling_bit = false;
44 u32 ary_idx = 0;
45 u8 value = 0;
46 u32 offset = 0;
47 u32 polling_count = 0;
48 u32 max_polling_cnt = 5000;
49
50 do {
51 pwr_cfg_cmd = pwrcfgcmd[ary_idx];
52 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
53 "rtlbe_hal_pwrseqcmdparsing(): "
54 "offset(%#x),cut_msk(%#x), fab_msk(%#x),"
55 "interface_msk(%#x), base(%#x), "
56 "cmd(%#x), msk(%#x), value(%#x)\n",
57 GET_PWR_CFG_OFFSET(pwr_cfg_cmd),
58 GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd),
59 GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd),
60 GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd),
61 GET_PWR_CFG_BASE(pwr_cfg_cmd),
62 GET_PWR_CFG_CMD(pwr_cfg_cmd),
63 GET_PWR_CFG_MASK(pwr_cfg_cmd),
64 GET_PWR_CFG_VALUE(pwr_cfg_cmd));
65
66 if ((GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd)&fab_version) &&
67 (GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd)&cut_version) &&
68 (GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd)&interface_type)) {
69 switch (GET_PWR_CFG_CMD(pwr_cfg_cmd)) {
70 case PWR_CMD_READ:
71 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
72 "rtlbe_hal_pwrseqcmdparsing(): "
73 "PWR_CMD_READ\n");
74 break;
75 case PWR_CMD_WRITE:
76 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
77 "rtlbe_hal_pwrseqcmdparsing(): "
78 "PWR_CMD_WRITE\n");
79 offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
80
81 /*Read the value from system register*/
82 value = rtl_read_byte(rtlpriv, offset);
83 value &= (~(GET_PWR_CFG_MASK(pwr_cfg_cmd)));
84 value = value | (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
85 & GET_PWR_CFG_MASK(pwr_cfg_cmd));
86
87 /*Write the value back to sytem register*/
88 rtl_write_byte(rtlpriv, offset, value);
89 break;
90 case PWR_CMD_POLLING:
91 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
92 "rtlbe_hal_pwrseqcmdparsing(): "
93 "PWR_CMD_POLLING\n");
94 b_polling_bit = false;
95 offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
96
97 do {
98 value = rtl_read_byte(rtlpriv, offset);
99
100 value &= GET_PWR_CFG_MASK(pwr_cfg_cmd);
101 if (value ==
102 (GET_PWR_CFG_VALUE(pwr_cfg_cmd) &
103 GET_PWR_CFG_MASK(pwr_cfg_cmd)))
104 b_polling_bit = true;
105 else
106 udelay(10);
107
108 if (polling_count++ > max_polling_cnt)
109 return false;
110
111 } while (!b_polling_bit);
112 break;
113 case PWR_CMD_DELAY:
114 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
115 "rtlbe_hal_pwrseqcmdparsing(): "
116 "PWR_CMD_DELAY\n");
117 if (GET_PWR_CFG_VALUE(pwr_cfg_cmd) ==
118 PWRSEQ_DELAY_US)
119 udelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
120 else
121 mdelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
122 break;
123 case PWR_CMD_END:
124 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
125 "rtlbe_hal_pwrseqcmdparsing(): "
126 "PWR_CMD_END\n");
127 return true;
128 default:
129 RT_ASSERT(false,
130 "rtlbe_hal_pwrseqcmdparsing(): "
131 "Unknown CMD!!\n");
132 break;
133 }
134 }
135
136 ary_idx++;
137 } while (1);
138
139 return true;
140}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/pwrseqcmd.h b/drivers/net/wireless/rtlwifi/rtl8723be/pwrseqcmd.h
deleted file mode 100644
index ce14a3b5cb71..000000000000
--- a/drivers/net/wireless/rtlwifi/rtl8723be/pwrseqcmd.h
+++ /dev/null
@@ -1,95 +0,0 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8723BE_PWRSEQCMD_H__
27#define __RTL8723BE_PWRSEQCMD_H__
28
29#include "../wifi.h"
30/*---------------------------------------------*/
31/*The value of cmd: 4 bits */
32/*---------------------------------------------*/
33#define PWR_CMD_READ 0x00
34#define PWR_CMD_WRITE 0x01
35#define PWR_CMD_POLLING 0x02
36#define PWR_CMD_DELAY 0x03
37#define PWR_CMD_END 0x04
38
39/* define the base address of each block */
40#define PWR_BASEADDR_MAC 0x00
41#define PWR_BASEADDR_USB 0x01
42#define PWR_BASEADDR_PCIE 0x02
43#define PWR_BASEADDR_SDIO 0x03
44
45#define PWR_INTF_SDIO_MSK BIT(0)
46#define PWR_INTF_USB_MSK BIT(1)
47#define PWR_INTF_PCI_MSK BIT(2)
48#define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
49
50#define PWR_FAB_TSMC_MSK BIT(0)
51#define PWR_FAB_UMC_MSK BIT(1)
52#define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
53
54#define PWR_CUT_TESTCHIP_MSK BIT(0)
55#define PWR_CUT_A_MSK BIT(1)
56#define PWR_CUT_B_MSK BIT(2)
57#define PWR_CUT_C_MSK BIT(3)
58#define PWR_CUT_D_MSK BIT(4)
59#define PWR_CUT_E_MSK BIT(5)
60#define PWR_CUT_F_MSK BIT(6)
61#define PWR_CUT_G_MSK BIT(7)
62#define PWR_CUT_ALL_MSK 0xFF
63
64
65enum pwrseq_delay_unit {
66 PWRSEQ_DELAY_US,
67 PWRSEQ_DELAY_MS,
68};
69
70struct wlan_pwr_cfg {
71 u16 offset;
72 u8 cut_msk;
73 u8 fab_msk:4;
74 u8 interface_msk:4;
75 u8 base:4;
76 u8 cmd:4;
77 u8 msk;
78 u8 value;
79
80};
81
82#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
83#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
84#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
85#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
86#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
87#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
88#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
89#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
90
91bool rtlbe_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
92 u8 fab_version, u8 interface_type,
93 struct wlan_pwr_cfg pwrcfgcmd[]);
94
95#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/hw.c b/drivers/net/wireless/rtlwifi/rtl8821ae/hw.c
index edb7557e0d44..58bbaf432b0e 100644
--- a/drivers/net/wireless/rtlwifi/rtl8821ae/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/hw.c
@@ -43,13 +43,6 @@
43 43
44#define LLT_CONFIG 5 44#define LLT_CONFIG 5
45 45
46bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
47 u8 faversion, u8 interface_type,
48 struct wlan_pwr_cfg pwrcfgcmd[])
49{
50 return false;
51}
52
53static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw) 46static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
54{ 47{
55 struct rtl_priv *rtlpriv = rtl_priv(hw); 48 struct rtl_priv *rtlpriv = rtl_priv(hw);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-08 04:08:26 -0500