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authorFelix Fietkau <nbd@openwrt.org>2010-12-11 18:51:09 -0500
committerJohn W. Linville <linville@tuxdriver.com>2010-12-13 15:23:31 -0500
commit115277a3bc0683d04da797268ddafdc3bf67ca33 (patch)
tree54b802c99b966ddeb912d595148d4868fb3ec24c /drivers/net/wireless
parent4ddfcd7daf57247ff718b849a152d97a80b7ae4d (diff)
ath9k_hw: merge ath9k_hw_get_gain_boundaries_pdadcs between eeprom_def.c and eeprom_4k.c
Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c190
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h8
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c169
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c164
4 files changed, 200 insertions, 331 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index 3d99b6cdd2cb..d54cfa4e8057 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -279,6 +279,196 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
279 } 279 }
280} 280}
281 281
282void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
283 struct ath9k_channel *chan,
284 void *pRawDataSet,
285 u8 *bChans, u16 availPiers,
286 u16 tPdGainOverlap,
287 u16 *pPdGainBoundaries, u8 *pPDADCValues,
288 u16 numXpdGains)
289{
290 int i, j, k;
291 int16_t ss;
292 u16 idxL = 0, idxR = 0, numPiers;
293 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
294 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
295 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
296 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
297 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
298 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
299
300 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
301 u8 minPwrT4[AR5416_NUM_PD_GAINS];
302 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
303 int16_t vpdStep;
304 int16_t tmpVal;
305 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
306 bool match;
307 int16_t minDelta = 0;
308 struct chan_centers centers;
309 int pdgain_boundary_default;
310 struct cal_data_per_freq *data_def = pRawDataSet;
311 struct cal_data_per_freq_4k *data_4k = pRawDataSet;
312 bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
313
314 memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
315 ath9k_hw_get_channel_centers(ah, chan, &centers);
316
317 for (numPiers = 0; numPiers < availPiers; numPiers++) {
318 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
319 break;
320 }
321
322 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
323 IS_CHAN_2GHZ(chan)),
324 bChans, numPiers, &idxL, &idxR);
325
326 if (match) {
327 if (eeprom_4k) {
328 for (i = 0; i < numXpdGains; i++) {
329 minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
330 maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
331 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
332 data_4k[idxL].pwrPdg[i],
333 data_4k[idxL].vpdPdg[i],
334 AR5416_PD_GAIN_ICEPTS,
335 vpdTableI[i]);
336 }
337 } else {
338 for (i = 0; i < numXpdGains; i++) {
339 minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
340 maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
341 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
342 data_def[idxL].pwrPdg[i],
343 data_def[idxL].vpdPdg[i],
344 AR5416_PD_GAIN_ICEPTS,
345 vpdTableI[i]);
346 }
347 }
348 } else {
349 for (i = 0; i < numXpdGains; i++) {
350 if (eeprom_4k) {
351 pVpdL = data_4k[idxL].vpdPdg[i];
352 pPwrL = data_4k[idxL].pwrPdg[i];
353 pVpdR = data_4k[idxR].vpdPdg[i];
354 pPwrR = data_4k[idxR].pwrPdg[i];
355 } else {
356 pVpdL = data_def[idxL].vpdPdg[i];
357 pPwrL = data_def[idxL].pwrPdg[i];
358 pVpdR = data_def[idxR].vpdPdg[i];
359 pPwrR = data_def[idxR].pwrPdg[i];
360 }
361
362 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
363
364 maxPwrT4[i] =
365 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
366 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
367
368
369 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
370 pPwrL, pVpdL,
371 AR5416_PD_GAIN_ICEPTS,
372 vpdTableL[i]);
373 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
374 pPwrR, pVpdR,
375 AR5416_PD_GAIN_ICEPTS,
376 vpdTableR[i]);
377
378 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
379 vpdTableI[i][j] =
380 (u8)(ath9k_hw_interpolate((u16)
381 FREQ2FBIN(centers.
382 synth_center,
383 IS_CHAN_2GHZ
384 (chan)),
385 bChans[idxL], bChans[idxR],
386 vpdTableL[i][j], vpdTableR[i][j]));
387 }
388 }
389 }
390
391 k = 0;
392
393 for (i = 0; i < numXpdGains; i++) {
394 if (i == (numXpdGains - 1))
395 pPdGainBoundaries[i] =
396 (u16)(maxPwrT4[i] / 2);
397 else
398 pPdGainBoundaries[i] =
399 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
400
401 pPdGainBoundaries[i] =
402 min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
403
404 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
405 minDelta = pPdGainBoundaries[0] - 23;
406 pPdGainBoundaries[0] = 23;
407 } else {
408 minDelta = 0;
409 }
410
411 if (i == 0) {
412 if (AR_SREV_9280_20_OR_LATER(ah))
413 ss = (int16_t)(0 - (minPwrT4[i] / 2));
414 else
415 ss = 0;
416 } else {
417 ss = (int16_t)((pPdGainBoundaries[i - 1] -
418 (minPwrT4[i] / 2)) -
419 tPdGainOverlap + 1 + minDelta);
420 }
421 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
422 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
423
424 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
425 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
426 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
427 ss++;
428 }
429
430 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
431 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
432 (minPwrT4[i] / 2));
433 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
434 tgtIndex : sizeCurrVpdTable;
435
436 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
437 pPDADCValues[k++] = vpdTableI[i][ss++];
438 }
439
440 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
441 vpdTableI[i][sizeCurrVpdTable - 2]);
442 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
443
444 if (tgtIndex >= maxIndex) {
445 while ((ss <= tgtIndex) &&
446 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
447 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
448 (ss - maxIndex + 1) * vpdStep));
449 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
450 255 : tmpVal);
451 ss++;
452 }
453 }
454 }
455
456 if (eeprom_4k)
457 pdgain_boundary_default = 58;
458 else
459 pdgain_boundary_default = pPdGainBoundaries[i - 1];
460
461 while (i < AR5416_PD_GAINS_IN_MASK) {
462 pPdGainBoundaries[i] = pdgain_boundary_default;
463 i++;
464 }
465
466 while (k < AR5416_NUM_PDADC_VALUES) {
467 pPDADCValues[k] = pPDADCValues[k - 1];
468 k++;
469 }
470}
471
282int ath9k_hw_eeprom_init(struct ath_hw *ah) 472int ath9k_hw_eeprom_init(struct ath_hw *ah)
283{ 473{
284 int status; 474 int status;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index 833dd0c3feba..1f6b712898e6 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -691,6 +691,14 @@ u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
691void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah); 691void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
692int ath9k_hw_eeprom_init(struct ath_hw *ah); 692int ath9k_hw_eeprom_init(struct ath_hw *ah);
693 693
694void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
695 struct ath9k_channel *chan,
696 void *pRawDataSet,
697 u8 *bChans, u16 availPiers,
698 u16 tPdGainOverlap,
699 u16 *pPdGainBoundaries, u8 *pPDADCValues,
700 u16 numXpdGains);
701
694#define ar5416_get_ntxchains(_txchainmask) \ 702#define ar5416_get_ntxchains(_txchainmask) \
695 (((_txchainmask >> 2) & 1) + \ 703 (((_txchainmask >> 2) & 1) + \
696 ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 704 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 6102309bc163..b0f744687900 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -227,173 +227,6 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
227 } 227 }
228} 228}
229 229
230static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
231 struct ath9k_channel *chan,
232 struct cal_data_per_freq_4k *pRawDataSet,
233 u8 *bChans, u16 availPiers,
234 u16 tPdGainOverlap,
235 u16 *pPdGainBoundaries, u8 *pPDADCValues,
236 u16 numXpdGains)
237{
238#define TMP_VAL_VPD_TABLE \
239 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
240 int i, j, k;
241 int16_t ss;
242 u16 idxL = 0, idxR = 0, numPiers;
243 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
244 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
245 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
246 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
247 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
248 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
249
250 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
251 u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
252 u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
253 int16_t vpdStep;
254 int16_t tmpVal;
255 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
256 bool match;
257 int16_t minDelta = 0;
258 struct chan_centers centers;
259#define PD_GAIN_BOUNDARY_DEFAULT 58;
260
261 memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
262 ath9k_hw_get_channel_centers(ah, chan, &centers);
263
264 for (numPiers = 0; numPiers < availPiers; numPiers++) {
265 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
266 break;
267 }
268
269 match = ath9k_hw_get_lower_upper_index(
270 (u8)FREQ2FBIN(centers.synth_center,
271 IS_CHAN_2GHZ(chan)), bChans, numPiers,
272 &idxL, &idxR);
273
274 if (match) {
275 for (i = 0; i < numXpdGains; i++) {
276 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
277 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
278 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
279 pRawDataSet[idxL].pwrPdg[i],
280 pRawDataSet[idxL].vpdPdg[i],
281 AR5416_PD_GAIN_ICEPTS,
282 vpdTableI[i]);
283 }
284 } else {
285 for (i = 0; i < numXpdGains; i++) {
286 pVpdL = pRawDataSet[idxL].vpdPdg[i];
287 pPwrL = pRawDataSet[idxL].pwrPdg[i];
288 pVpdR = pRawDataSet[idxR].vpdPdg[i];
289 pPwrR = pRawDataSet[idxR].pwrPdg[i];
290
291 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
292
293 maxPwrT4[i] =
294 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
295 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
296
297
298 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
299 pPwrL, pVpdL,
300 AR5416_PD_GAIN_ICEPTS,
301 vpdTableL[i]);
302 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
303 pPwrR, pVpdR,
304 AR5416_PD_GAIN_ICEPTS,
305 vpdTableR[i]);
306
307 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
308 vpdTableI[i][j] =
309 (u8)(ath9k_hw_interpolate((u16)
310 FREQ2FBIN(centers.
311 synth_center,
312 IS_CHAN_2GHZ
313 (chan)),
314 bChans[idxL], bChans[idxR],
315 vpdTableL[i][j], vpdTableR[i][j]));
316 }
317 }
318 }
319
320 k = 0;
321
322 for (i = 0; i < numXpdGains; i++) {
323 if (i == (numXpdGains - 1))
324 pPdGainBoundaries[i] =
325 (u16)(maxPwrT4[i] / 2);
326 else
327 pPdGainBoundaries[i] =
328 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
329
330 pPdGainBoundaries[i] =
331 min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
332
333 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
334 minDelta = pPdGainBoundaries[0] - 23;
335 pPdGainBoundaries[0] = 23;
336 } else {
337 minDelta = 0;
338 }
339
340 if (i == 0) {
341 if (AR_SREV_9280_20_OR_LATER(ah))
342 ss = (int16_t)(0 - (minPwrT4[i] / 2));
343 else
344 ss = 0;
345 } else {
346 ss = (int16_t)((pPdGainBoundaries[i - 1] -
347 (minPwrT4[i] / 2)) -
348 tPdGainOverlap + 1 + minDelta);
349 }
350 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
351 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
352
353 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
354 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
355 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
356 ss++;
357 }
358
359 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
360 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
361 (minPwrT4[i] / 2));
362 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
363 tgtIndex : sizeCurrVpdTable;
364
365 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
366 pPDADCValues[k++] = vpdTableI[i][ss++];
367
368 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
369 vpdTableI[i][sizeCurrVpdTable - 2]);
370 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
371
372 if (tgtIndex >= maxIndex) {
373 while ((ss <= tgtIndex) &&
374 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
375 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
376 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
377 255 : tmpVal);
378 ss++;
379 }
380 }
381 }
382
383 while (i < AR5416_PD_GAINS_IN_MASK) {
384 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
385 i++;
386 }
387
388 while (k < AR5416_NUM_PDADC_VALUES) {
389 pPDADCValues[k] = pPDADCValues[k - 1];
390 k++;
391 }
392
393 return;
394#undef TMP_VAL_VPD_TABLE
395}
396
397static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, 230static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
398 struct ath9k_channel *chan, 231 struct ath9k_channel *chan,
399 int16_t *pTxPowerIndexOffset) 232 int16_t *pTxPowerIndexOffset)
@@ -455,7 +288,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
455 if (pEepData->baseEepHeader.txMask & (1 << i)) { 288 if (pEepData->baseEepHeader.txMask & (1 << i)) {
456 pRawDataset = pEepData->calPierData2G[i]; 289 pRawDataset = pEepData->calPierData2G[i];
457 290
458 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan, 291 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
459 pRawDataset, pCalBChans, 292 pRawDataset, pCalBChans,
460 numPiers, pdGainOverlap_t2, 293 numPiers, pdGainOverlap_t2,
461 gainBoundaries, 294 gainBoundaries,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index da96a78f996d..ad3e234a673b 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -588,168 +588,6 @@ static void ath9k_hw_def_set_addac(struct ath_hw *ah,
588#undef XPA_LVL_FREQ 588#undef XPA_LVL_FREQ
589} 589}
590 590
591static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
592 struct ath9k_channel *chan,
593 struct cal_data_per_freq *pRawDataSet,
594 u8 *bChans, u16 availPiers,
595 u16 tPdGainOverlap,
596 u16 *pPdGainBoundaries, u8 *pPDADCValues,
597 u16 numXpdGains)
598{
599 int i, j, k;
600 int16_t ss;
601 u16 idxL = 0, idxR = 0, numPiers;
602 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
603 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
604 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
605 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
606 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
607 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
608
609 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
610 u8 minPwrT4[AR5416_NUM_PD_GAINS];
611 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
612 int16_t vpdStep;
613 int16_t tmpVal;
614 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
615 bool match;
616 int16_t minDelta = 0;
617 struct chan_centers centers;
618
619 memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
620 ath9k_hw_get_channel_centers(ah, chan, &centers);
621
622 for (numPiers = 0; numPiers < availPiers; numPiers++) {
623 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
624 break;
625 }
626
627 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
628 IS_CHAN_2GHZ(chan)),
629 bChans, numPiers, &idxL, &idxR);
630
631 if (match) {
632 for (i = 0; i < numXpdGains; i++) {
633 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
634 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
635 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
636 pRawDataSet[idxL].pwrPdg[i],
637 pRawDataSet[idxL].vpdPdg[i],
638 AR5416_PD_GAIN_ICEPTS,
639 vpdTableI[i]);
640 }
641 } else {
642 for (i = 0; i < numXpdGains; i++) {
643 pVpdL = pRawDataSet[idxL].vpdPdg[i];
644 pPwrL = pRawDataSet[idxL].pwrPdg[i];
645 pVpdR = pRawDataSet[idxR].vpdPdg[i];
646 pPwrR = pRawDataSet[idxR].pwrPdg[i];
647
648 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
649
650 maxPwrT4[i] =
651 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
652 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
653
654
655 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
656 pPwrL, pVpdL,
657 AR5416_PD_GAIN_ICEPTS,
658 vpdTableL[i]);
659 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
660 pPwrR, pVpdR,
661 AR5416_PD_GAIN_ICEPTS,
662 vpdTableR[i]);
663
664 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
665 vpdTableI[i][j] =
666 (u8)(ath9k_hw_interpolate((u16)
667 FREQ2FBIN(centers.
668 synth_center,
669 IS_CHAN_2GHZ
670 (chan)),
671 bChans[idxL], bChans[idxR],
672 vpdTableL[i][j], vpdTableR[i][j]));
673 }
674 }
675 }
676
677 k = 0;
678
679 for (i = 0; i < numXpdGains; i++) {
680 if (i == (numXpdGains - 1))
681 pPdGainBoundaries[i] =
682 (u16)(maxPwrT4[i] / 2);
683 else
684 pPdGainBoundaries[i] =
685 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
686
687 pPdGainBoundaries[i] =
688 min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
689
690 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
691 minDelta = pPdGainBoundaries[0] - 23;
692 pPdGainBoundaries[0] = 23;
693 } else {
694 minDelta = 0;
695 }
696
697 if (i == 0) {
698 if (AR_SREV_9280_20_OR_LATER(ah))
699 ss = (int16_t)(0 - (minPwrT4[i] / 2));
700 else
701 ss = 0;
702 } else {
703 ss = (int16_t)((pPdGainBoundaries[i - 1] -
704 (minPwrT4[i] / 2)) -
705 tPdGainOverlap + 1 + minDelta);
706 }
707 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
708 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
709
710 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
711 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
712 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
713 ss++;
714 }
715
716 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
717 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
718 (minPwrT4[i] / 2));
719 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
720 tgtIndex : sizeCurrVpdTable;
721
722 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
723 pPDADCValues[k++] = vpdTableI[i][ss++];
724 }
725
726 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
727 vpdTableI[i][sizeCurrVpdTable - 2]);
728 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
729
730 if (tgtIndex >= maxIndex) {
731 while ((ss <= tgtIndex) &&
732 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
733 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
734 (ss - maxIndex + 1) * vpdStep));
735 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
736 255 : tmpVal);
737 ss++;
738 }
739 }
740 }
741
742 while (i < AR5416_PD_GAINS_IN_MASK) {
743 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
744 i++;
745 }
746
747 while (k < AR5416_NUM_PDADC_VALUES) {
748 pPDADCValues[k] = pPDADCValues[k - 1];
749 k++;
750 }
751}
752
753static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah, 591static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
754 u16 *gb, 592 u16 *gb,
755 u16 numXpdGain, 593 u16 numXpdGain,
@@ -916,7 +754,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
916 ath9k_olc_get_pdadcs(ah, pcdacIdx, 754 ath9k_olc_get_pdadcs(ah, pcdacIdx,
917 txPower/2, pdadcValues); 755 txPower/2, pdadcValues);
918 } else { 756 } else {
919 ath9k_hw_get_def_gain_boundaries_pdadcs(ah, 757 ath9k_hw_get_gain_boundaries_pdadcs(ah,
920 chan, pRawDataset, 758 chan, pRawDataset,
921 pCalBChans, numPiers, 759 pCalBChans, numPiers,
922 pdGainOverlap_t2, 760 pdGainOverlap_t2,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 15:24:06 -0500