aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless
diff options
context:
space:
mode:
authorNick Kossifidis <mick@madwifi-project.org>2009-02-08 23:08:51 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-02-13 13:44:47 -0500
commita406c139091902acebafb2462b64ba498901e820 (patch)
treec3db1c89dc6019026fe66f9d21d608aa1052cf37 /drivers/net/wireless
parent8892e4ec62f1553d36c88e613890aa4d7c5a372e (diff)
ath5k: Update initvals
* Update initvals to match legacy and Sam's HAL Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/ath5k/initvals.c1575
-rw-r--r--drivers/net/wireless/ath5k/reg.h44
-rw-r--r--drivers/net/wireless/ath5k/reset.c15
3 files changed, 687 insertions, 947 deletions
diff --git a/drivers/net/wireless/ath5k/initvals.c b/drivers/net/wireless/ath5k/initvals.c
index 450bd6e945ff..44886434187b 100644
--- a/drivers/net/wireless/ath5k/initvals.c
+++ b/drivers/net/wireless/ath5k/initvals.c
@@ -2,7 +2,7 @@
2 * Initial register settings functions 2 * Initial register settings functions
3 * 3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * 7 *
8 * Permission to use, copy, modify, and distribute this software for any 8 * Permission to use, copy, modify, and distribute this software for any
@@ -340,7 +340,7 @@ static const struct ath5k_ini ar5211_ini[] = {
340 * common on all cards/modes. 340 * common on all cards/modes.
341 * Note: Table is rewritten during 341 * Note: Table is rewritten during
342 * txpower setup later using calibration 342 * txpower setup later using calibration
343 * data etc. so next write is non-common 343 * data etc. so next write is non-common */
344 { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff }, 344 { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff },
345 { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff }, 345 { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff },
346 { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff }, 346 { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff },
@@ -371,7 +371,7 @@ static const struct ath5k_ini ar5211_ini[] = {
371 { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff }, 371 { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff },
372 { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff }, 372 { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff },
373 { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff }, 373 { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff },
374 { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff },*/ 374 { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff },
375 { AR5K_PHY_CCKTXCTL, 0x00000000 }, 375 { AR5K_PHY_CCKTXCTL, 0x00000000 },
376 { AR5K_PHY(642), 0x503e4646 }, 376 { AR5K_PHY(642), 0x503e4646 },
377 { AR5K_PHY_GAIN_2GHZ, 0x6480416c }, 377 { AR5K_PHY_GAIN_2GHZ, 0x6480416c },
@@ -386,85 +386,85 @@ static const struct ath5k_ini ar5211_ini[] = {
386}; 386};
387 387
388/* Initial mode-specific settings for AR5211 388/* Initial mode-specific settings for AR5211
389 * XXX: how about g / gTurbo ? RF5111 supports it, how about AR5211 ? 389 * 5211 supports OFDM-only g (draft g) but we
390 * Maybe 5211 supports OFDM-only g but we need to test it ! 390 * need to test it !
391 */ 391 */
392static const struct ath5k_ini_mode ar5211_ini_mode[] = { 392static const struct ath5k_ini_mode ar5211_ini_mode[] = {
393 { AR5K_TXCFG, 393 { AR5K_TXCFG,
394 /* a aTurbo b */ 394 /* a aTurbo b g (OFDM) */
395 { 0x00000015, 0x00000015, 0x0000001d } }, 395 { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },
396 { AR5K_QUEUE_DFS_LOCAL_IFS(0), 396 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
397 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, 397 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
398 { AR5K_QUEUE_DFS_LOCAL_IFS(1), 398 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
399 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, 399 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
400 { AR5K_QUEUE_DFS_LOCAL_IFS(2), 400 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
401 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, 401 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
402 { AR5K_QUEUE_DFS_LOCAL_IFS(3), 402 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
403 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, 403 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
404 { AR5K_QUEUE_DFS_LOCAL_IFS(4), 404 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
405 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, 405 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
406 { AR5K_QUEUE_DFS_LOCAL_IFS(5), 406 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
407 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, 407 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
408 { AR5K_QUEUE_DFS_LOCAL_IFS(6), 408 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
409 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, 409 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
410 { AR5K_QUEUE_DFS_LOCAL_IFS(7), 410 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
411 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, 411 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
412 { AR5K_QUEUE_DFS_LOCAL_IFS(8), 412 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
413 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, 413 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
414 { AR5K_QUEUE_DFS_LOCAL_IFS(9), 414 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
415 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, 415 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
416 { AR5K_DCU_GBL_IFS_SLOT, 416 { AR5K_DCU_GBL_IFS_SLOT,
417 { 0x00000168, 0x000001e0, 0x000001b8 } }, 417 { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },
418 { AR5K_DCU_GBL_IFS_SIFS, 418 { AR5K_DCU_GBL_IFS_SIFS,
419 { 0x00000230, 0x000001e0, 0x000000b0 } }, 419 { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },
420 { AR5K_DCU_GBL_IFS_EIFS, 420 { AR5K_DCU_GBL_IFS_EIFS,
421 { 0x00000d98, 0x00001180, 0x00001f48 } }, 421 { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },
422 { AR5K_DCU_GBL_IFS_MISC, 422 { AR5K_DCU_GBL_IFS_MISC,
423 { 0x0000a0e0, 0x00014068, 0x00005880 } }, 423 { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },
424 { AR5K_TIME_OUT, 424 { AR5K_TIME_OUT,
425 { 0x04000400, 0x08000800, 0x20003000 } }, 425 { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },
426 { AR5K_USEC_5211, 426 { AR5K_USEC_5211,
427 { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95 } }, 427 { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },
428 { AR5K_PHY_TURBO, 428 { AR5K_PHY_TURBO,
429 { 0x00000000, 0x00000003, 0x00000000 } }, 429 { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },
430 { AR5K_PHY(8), 430 { AR5K_PHY(8),
431 { 0x02020200, 0x02020200, 0x02010200 } }, 431 { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },
432 { AR5K_PHY(9), 432 { AR5K_PHY(9),
433 { 0x00000e0e, 0x00000e0e, 0x00000707 } }, 433 { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },
434 { AR5K_PHY(10), 434 { AR5K_PHY(10),
435 { 0x0a020001, 0x0a020001, 0x05010000 } }, 435 { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },
436 { AR5K_PHY(13), 436 { AR5K_PHY(13),
437 { 0x00000e0e, 0x00000e0e, 0x00000e0e } }, 437 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
438 { AR5K_PHY(14), 438 { AR5K_PHY(14),
439 { 0x00000007, 0x00000007, 0x0000000b } }, 439 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },
440 { AR5K_PHY(17), 440 { AR5K_PHY(17),
441 { 0x1372169c, 0x137216a5, 0x137216a8 } }, 441 { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },
442 { AR5K_PHY(18), 442 { AR5K_PHY(18),
443 { 0x0018ba67, 0x0018ba67, 0x0018ba69 } }, 443 { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
444 { AR5K_PHY(20), 444 { AR5K_PHY(20),
445 { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, 445 { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
446 { AR5K_PHY_SIG, 446 { AR5K_PHY_SIG,
447 { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e } }, 447 { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
448 { AR5K_PHY_AGCCOARSE, 448 { AR5K_PHY_AGCCOARSE,
449 { 0x31375d5e, 0x31375d5e, 0x313a5d5e } }, 449 { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
450 { AR5K_PHY_AGCCTL, 450 { AR5K_PHY_AGCCTL,
451 { 0x0000bd10, 0x0000bd10, 0x0000bd38 } }, 451 { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
452 { AR5K_PHY_NF, 452 { AR5K_PHY_NF,
453 { 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, 453 { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
454 { AR5K_PHY_RX_DELAY, 454 { AR5K_PHY_RX_DELAY,
455 { 0x00002710, 0x00002710, 0x0000157c } }, 455 { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },
456 { AR5K_PHY(70), 456 { AR5K_PHY(70),
457 { 0x00000190, 0x00000190, 0x00000084 } }, 457 { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },
458 { AR5K_PHY_FRAME_CTL_5211, 458 { AR5K_PHY_FRAME_CTL_5211,
459 { 0x6fe01020, 0x6fe01020, 0x6fe00920 } }, 459 { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
460 { AR5K_PHY_PCDAC_TXPOWER_BASE_5211, 460 { AR5K_PHY_PCDAC_TXPOWER_BASE,
461 { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff } }, 461 { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
462 { AR5K_RF_BUFFER_CONTROL_4, 462 { AR5K_RF_BUFFER_CONTROL_4,
463 { 0x00000010, 0x00000014, 0x00000010 } }, 463 { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },
464}; 464};
465 465
466/* Initial register settings for AR5212 */ 466/* Initial register settings for AR5212 */
467static const struct ath5k_ini ar5212_ini[] = { 467static const struct ath5k_ini ar5212_ini_common_start[] = {
468 { AR5K_RXDP, 0x00000000 }, 468 { AR5K_RXDP, 0x00000000 },
469 { AR5K_RXCFG, 0x00000005 }, 469 { AR5K_RXCFG, 0x00000005 },
470 { AR5K_MIBC, 0x00000000 }, 470 { AR5K_MIBC, 0x00000000 },
@@ -485,91 +485,83 @@ static const struct ath5k_ini ar5212_ini[] = {
485 { AR5K_QUEUE_TXDP(9), 0x00000000 }, 485 { AR5K_QUEUE_TXDP(9), 0x00000000 },
486 { AR5K_DCU_FP, 0x00000000 }, 486 { AR5K_DCU_FP, 0x00000000 },
487 { AR5K_DCU_TXP, 0x00000000 }, 487 { AR5K_DCU_TXP, 0x00000000 },
488 { AR5K_DCU_TX_FILTER_0_BASE, 0x00000000 }, 488 /* Tx filter table 0 (32 entries) */
489 /* Unknown table */ 489 { AR5K_DCU_TX_FILTER_0(0), 0x00000000 }, /* DCU 0 */
490 { 0x1078, 0x00000000 }, 490 { AR5K_DCU_TX_FILTER_0(1), 0x00000000 },
491 { 0x10b8, 0x00000000 }, 491 { AR5K_DCU_TX_FILTER_0(2), 0x00000000 },
492 { 0x10f8, 0x00000000 }, 492 { AR5K_DCU_TX_FILTER_0(3), 0x00000000 },
493 { 0x1138, 0x00000000 }, 493 { AR5K_DCU_TX_FILTER_0(4), 0x00000000 }, /* DCU 1 */
494 { 0x1178, 0x00000000 }, 494 { AR5K_DCU_TX_FILTER_0(5), 0x00000000 },
495 { 0x11b8, 0x00000000 }, 495 { AR5K_DCU_TX_FILTER_0(6), 0x00000000 },
496 { 0x11f8, 0x00000000 }, 496 { AR5K_DCU_TX_FILTER_0(7), 0x00000000 },
497 { 0x1238, 0x00000000 }, 497 { AR5K_DCU_TX_FILTER_0(8), 0x00000000 }, /* DCU 2 */
498 { 0x1278, 0x00000000 }, 498 { AR5K_DCU_TX_FILTER_0(9), 0x00000000 },
499 { 0x12b8, 0x00000000 }, 499 { AR5K_DCU_TX_FILTER_0(10), 0x00000000 },
500 { 0x12f8, 0x00000000 }, 500 { AR5K_DCU_TX_FILTER_0(11), 0x00000000 },
501 { 0x1338, 0x00000000 }, 501 { AR5K_DCU_TX_FILTER_0(12), 0x00000000 }, /* DCU 3 */
502 { 0x1378, 0x00000000 }, 502 { AR5K_DCU_TX_FILTER_0(13), 0x00000000 },
503 { 0x13b8, 0x00000000 }, 503 { AR5K_DCU_TX_FILTER_0(14), 0x00000000 },
504 { 0x13f8, 0x00000000 }, 504 { AR5K_DCU_TX_FILTER_0(15), 0x00000000 },
505 { 0x1438, 0x00000000 }, 505 { AR5K_DCU_TX_FILTER_0(16), 0x00000000 }, /* DCU 4 */
506 { 0x1478, 0x00000000 }, 506 { AR5K_DCU_TX_FILTER_0(17), 0x00000000 },
507 { 0x14b8, 0x00000000 }, 507 { AR5K_DCU_TX_FILTER_0(18), 0x00000000 },
508 { 0x14f8, 0x00000000 }, 508 { AR5K_DCU_TX_FILTER_0(19), 0x00000000 },
509 { 0x1538, 0x00000000 }, 509 { AR5K_DCU_TX_FILTER_0(20), 0x00000000 }, /* DCU 5 */
510 { 0x1578, 0x00000000 }, 510 { AR5K_DCU_TX_FILTER_0(21), 0x00000000 },
511 { 0x15b8, 0x00000000 }, 511 { AR5K_DCU_TX_FILTER_0(22), 0x00000000 },
512 { 0x15f8, 0x00000000 }, 512 { AR5K_DCU_TX_FILTER_0(23), 0x00000000 },
513 { 0x1638, 0x00000000 }, 513 { AR5K_DCU_TX_FILTER_0(24), 0x00000000 }, /* DCU 6 */
514 { 0x1678, 0x00000000 }, 514 { AR5K_DCU_TX_FILTER_0(25), 0x00000000 },
515 { 0x16b8, 0x00000000 }, 515 { AR5K_DCU_TX_FILTER_0(26), 0x00000000 },
516 { 0x16f8, 0x00000000 }, 516 { AR5K_DCU_TX_FILTER_0(27), 0x00000000 },
517 { 0x1738, 0x00000000 }, 517 { AR5K_DCU_TX_FILTER_0(28), 0x00000000 }, /* DCU 7 */
518 { 0x1778, 0x00000000 }, 518 { AR5K_DCU_TX_FILTER_0(29), 0x00000000 },
519 { 0x17b8, 0x00000000 }, 519 { AR5K_DCU_TX_FILTER_0(30), 0x00000000 },
520 { 0x17f8, 0x00000000 }, 520 { AR5K_DCU_TX_FILTER_0(31), 0x00000000 },
521 { 0x103c, 0x00000000 }, 521 /* Tx filter table 1 (16 entries) */
522 { 0x107c, 0x00000000 }, 522 { AR5K_DCU_TX_FILTER_1(0), 0x00000000 },
523 { 0x10bc, 0x00000000 }, 523 { AR5K_DCU_TX_FILTER_1(1), 0x00000000 },
524 { 0x10fc, 0x00000000 }, 524 { AR5K_DCU_TX_FILTER_1(2), 0x00000000 },
525 { 0x113c, 0x00000000 }, 525 { AR5K_DCU_TX_FILTER_1(3), 0x00000000 },
526 { 0x117c, 0x00000000 }, 526 { AR5K_DCU_TX_FILTER_1(4), 0x00000000 },
527 { 0x11bc, 0x00000000 }, 527 { AR5K_DCU_TX_FILTER_1(5), 0x00000000 },
528 { 0x11fc, 0x00000000 }, 528 { AR5K_DCU_TX_FILTER_1(6), 0x00000000 },
529 { 0x123c, 0x00000000 }, 529 { AR5K_DCU_TX_FILTER_1(7), 0x00000000 },
530 { 0x127c, 0x00000000 }, 530 { AR5K_DCU_TX_FILTER_1(8), 0x00000000 },
531 { 0x12bc, 0x00000000 }, 531 { AR5K_DCU_TX_FILTER_1(9), 0x00000000 },
532 { 0x12fc, 0x00000000 }, 532 { AR5K_DCU_TX_FILTER_1(10), 0x00000000 },
533 { 0x133c, 0x00000000 }, 533 { AR5K_DCU_TX_FILTER_1(11), 0x00000000 },
534 { 0x137c, 0x00000000 }, 534 { AR5K_DCU_TX_FILTER_1(12), 0x00000000 },
535 { 0x13bc, 0x00000000 }, 535 { AR5K_DCU_TX_FILTER_1(13), 0x00000000 },
536 { 0x13fc, 0x00000000 }, 536 { AR5K_DCU_TX_FILTER_1(14), 0x00000000 },
537 { 0x143c, 0x00000000 }, 537 { AR5K_DCU_TX_FILTER_1(15), 0x00000000 },
538 { 0x147c, 0x00000000 }, 538 { AR5K_DCU_TX_FILTER_CLR, 0x00000000 },
539 { AR5K_DCU_TX_FILTER_SET, 0x00000000 },
539 { AR5K_DCU_TX_FILTER_CLR, 0x00000000 }, 540 { AR5K_DCU_TX_FILTER_CLR, 0x00000000 },
540 { AR5K_DCU_TX_FILTER_SET, 0x00000000 }, 541 { AR5K_DCU_TX_FILTER_SET, 0x00000000 },
541 { AR5K_STA_ID1, 0x00000000 }, 542 { AR5K_STA_ID1, 0x00000000 },
542 { AR5K_BSS_ID0, 0x00000000 }, 543 { AR5K_BSS_ID0, 0x00000000 },
543 { AR5K_BSS_ID1, 0x00000000 }, 544 { AR5K_BSS_ID1, 0x00000000 },
544 /*{ AR5K_RSSI_THR, 0x00000000 },*/ /* Found on SuperAG cards */ 545 { AR5K_BEACON_5211, 0x00000000 },
545 { AR5K_BEACON_5211, 0x00000000 }, /* Found on SuperAG cards */ 546 { AR5K_CFP_PERIOD_5211, 0x00000000 },
546 { AR5K_CFP_PERIOD_5211, 0x00000000 }, /* Found on SuperAG cards */ 547 { AR5K_TIMER0_5211, 0x00000030 },
547 { AR5K_TIMER0_5211, 0x00000030 }, /* Found on SuperAG cards */ 548 { AR5K_TIMER1_5211, 0x0007ffff },
548 { AR5K_TIMER1_5211, 0x0007ffff }, /* Found on SuperAG cards */ 549 { AR5K_TIMER2_5211, 0x01ffffff },
549 { AR5K_TIMER2_5211, 0x01ffffff }, /* Found on SuperAG cards */ 550 { AR5K_TIMER3_5211, 0x00000031 },
550 { AR5K_TIMER3_5211, 0x00000031 }, /* Found on SuperAG cards */ 551 { AR5K_CFP_DUR_5211, 0x00000000 },
551 { AR5K_CFP_DUR_5211, 0x00000000 }, /* Found on SuperAG cards */
552 { AR5K_RX_FILTER_5211, 0x00000000 }, 552 { AR5K_RX_FILTER_5211, 0x00000000 },
553 { AR5K_DIAG_SW_5211, 0x00000000 }, 553 { AR5K_DIAG_SW_5211, 0x00000000 },
554 { AR5K_ADDAC_TEST, 0x00000000 }, 554 { AR5K_ADDAC_TEST, 0x00000000 },
555 { AR5K_DEFAULT_ANTENNA, 0x00000000 }, 555 { AR5K_DEFAULT_ANTENNA, 0x00000000 },
556 { 0x8080, 0x00000000 }, 556 { AR5K_FRAME_CTL_QOSM, 0x000fc78f },
557 /*{ 0x805c, 0xffffc7ff },*/ /* Old value */
558 { 0x805c, 0x000fc78f },
559 { AR5K_NAV_5211, 0x00000000 }, /* Not found on recent */
560 { AR5K_RTS_OK_5211, 0x00000000 }, /* dumps but it makes */
561 { AR5K_RTS_FAIL_5211, 0x00000000 }, /* sense to reset counters */
562 { AR5K_ACK_FAIL_5211, 0x00000000 }, /* since pcu registers */
563 { AR5K_FCS_FAIL_5211, 0x00000000 }, /* are skiped during chan*/
564 { AR5K_BEACON_CNT_5211, 0x00000000 }, /* change */
565 { AR5K_XRMODE, 0x2a82301a }, 557 { AR5K_XRMODE, 0x2a82301a },
566 { AR5K_XRDELAY, 0x05dc01e0 }, 558 { AR5K_XRDELAY, 0x05dc01e0 },
567 { AR5K_XRTIMEOUT, 0x1f402710 }, 559 { AR5K_XRTIMEOUT, 0x1f402710 },
568 { AR5K_XRCHIRP, 0x01f40000 }, 560 { AR5K_XRCHIRP, 0x01f40000 },
569 { AR5K_XRSTOMP, 0x00001e1c }, 561 { AR5K_XRSTOMP, 0x00001e1c },
570 { AR5K_SLEEP0, 0x0002aaaa }, /* Found on SuperAG cards */ 562 { AR5K_SLEEP0, 0x0002aaaa },
571 { AR5K_SLEEP1, 0x02005555 }, /* Found on SuperAG cards */ 563 { AR5K_SLEEP1, 0x02005555 },
572 { AR5K_SLEEP2, 0x00000000 }, /* Found on SuperAG cards */ 564 { AR5K_SLEEP2, 0x00000000 },
573 { AR5K_BSS_IDM0, 0xffffffff }, 565 { AR5K_BSS_IDM0, 0xffffffff },
574 { AR5K_BSS_IDM1, 0x0000ffff }, 566 { AR5K_BSS_IDM1, 0x0000ffff },
575 { AR5K_TXPC, 0x00000000 }, 567 { AR5K_TXPC, 0x00000000 },
@@ -577,7 +569,8 @@ static const struct ath5k_ini ar5212_ini[] = {
577 { AR5K_PROFCNT_RX, 0x00000000 }, 569 { AR5K_PROFCNT_RX, 0x00000000 },
578 { AR5K_PROFCNT_RXCLR, 0x00000000 }, 570 { AR5K_PROFCNT_RXCLR, 0x00000000 },
579 { AR5K_PROFCNT_CYCLE, 0x00000000 }, 571 { AR5K_PROFCNT_CYCLE, 0x00000000 },
580 { 0x80fc, 0x00000088 }, 572 { AR5K_QUIET_CTL1, 0x00000088 },
573 /* Initial rate duration table (32 entries )*/
581 { AR5K_RATE_DUR(0), 0x00000000 }, 574 { AR5K_RATE_DUR(0), 0x00000000 },
582 { AR5K_RATE_DUR(1), 0x0000008c }, 575 { AR5K_RATE_DUR(1), 0x0000008c },
583 { AR5K_RATE_DUR(2), 0x000000e4 }, 576 { AR5K_RATE_DUR(2), 0x000000e4 },
@@ -610,881 +603,625 @@ static const struct ath5k_ini ar5212_ini[] = {
610 { AR5K_RATE_DUR(29), 0x0000007f }, 603 { AR5K_RATE_DUR(29), 0x0000007f },
611 { AR5K_RATE_DUR(30), 0x000000a2 }, 604 { AR5K_RATE_DUR(30), 0x000000a2 },
612 { AR5K_RATE_DUR(31), 0x00000000 }, 605 { AR5K_RATE_DUR(31), 0x00000000 },
613 { 0x8100, 0x00010002}, 606 { AR5K_QUIET_CTL2, 0x00010002 },
614 { AR5K_TSF_PARM, 0x00000001 }, 607 { AR5K_TSF_PARM, 0x00000001 },
615 { 0x8108, 0x000000c0 }, 608 { AR5K_QOS_NOACK, 0x000000c0 },
616 { AR5K_PHY_ERR_FIL, 0x00000000 }, 609 { AR5K_PHY_ERR_FIL, 0x00000000 },
617 { 0x8110, 0x00000168 }, 610 { AR5K_XRLAT_TX, 0x00000168 },
618 { 0x8114, 0x00000000 }, 611 { AR5K_ACKSIFS, 0x00000000 },
619 /* Some kind of table 612 /* Rate -> db table
620 * also notice ...03<-02<-01<-00) */ 613 * notice ...03<-02<-01<-00 ! */
621 { 0x87c0, 0x03020100 }, 614 { AR5K_RATE2DB(0), 0x03020100 },
622 { 0x87c4, 0x07060504 }, 615 { AR5K_RATE2DB(1), 0x07060504 },
623 { 0x87c8, 0x0b0a0908 }, 616 { AR5K_RATE2DB(2), 0x0b0a0908 },
624 { 0x87cc, 0x0f0e0d0c }, 617 { AR5K_RATE2DB(3), 0x0f0e0d0c },
625 { 0x87d0, 0x13121110 }, 618 { AR5K_RATE2DB(4), 0x13121110 },
626 { 0x87d4, 0x17161514 }, 619 { AR5K_RATE2DB(5), 0x17161514 },
627 { 0x87d8, 0x1b1a1918 }, 620 { AR5K_RATE2DB(6), 0x1b1a1918 },
628 { 0x87dc, 0x1f1e1d1c }, 621 { AR5K_RATE2DB(7), 0x1f1e1d1c },
629 /* loop ? */ 622 /* Db -> Rate table */
630 { 0x87e0, 0x03020100 }, 623 { AR5K_DB2RATE(0), 0x03020100 },
631 { 0x87e4, 0x07060504 }, 624 { AR5K_DB2RATE(1), 0x07060504 },
632 { 0x87e8, 0x0b0a0908 }, 625 { AR5K_DB2RATE(2), 0x0b0a0908 },
633 { 0x87ec, 0x0f0e0d0c }, 626 { AR5K_DB2RATE(3), 0x0f0e0d0c },
634 { 0x87f0, 0x13121110 }, 627 { AR5K_DB2RATE(4), 0x13121110 },
635 { 0x87f4, 0x17161514 }, 628 { AR5K_DB2RATE(5), 0x17161514 },
636 { 0x87f8, 0x1b1a1918 }, 629 { AR5K_DB2RATE(6), 0x1b1a1918 },
637 { 0x87fc, 0x1f1e1d1c }, 630 { AR5K_DB2RATE(7), 0x1f1e1d1c },
638 /* PHY registers */ 631 /* PHY registers (Common settings
639 /*{ AR5K_PHY_AGC, 0x00000000 },*/ 632 * for all chips/modes) */
640 { AR5K_PHY(3), 0xad848e19 }, 633 { AR5K_PHY(3), 0xad848e19 },
641 { AR5K_PHY(4), 0x7d28e000 }, 634 { AR5K_PHY(4), 0x7d28e000 },
642 { AR5K_PHY_TIMING_3, 0x9c0a9f6b }, 635 { AR5K_PHY_TIMING_3, 0x9c0a9f6b },
643 { AR5K_PHY_ACT, 0x00000000 }, 636 { AR5K_PHY_ACT, 0x00000000 },
644 /*{ AR5K_PHY(11), 0x00022ffe },*/ 637 { AR5K_PHY(16), 0x206a017a },
645 /*{ AR5K_PHY(15), 0x00020100 },*/ 638 { AR5K_PHY(21), 0x00000859 },
646 { AR5K_PHY(16), 0x206a017a }, 639 { AR5K_PHY_BIN_MASK_1, 0x00000000 },
647 /*{ AR5K_PHY(19), 0x1284613c },*/ 640 { AR5K_PHY_BIN_MASK_2, 0x00000000 },
648 { AR5K_PHY(21), 0x00000859 }, 641 { AR5K_PHY_BIN_MASK_3, 0x00000000 },
649 { AR5K_PHY(64), 0x00000000 }, 642 { AR5K_PHY_BIN_MASK_CTL, 0x00800000 },
650 { AR5K_PHY(65), 0x00000000 }, 643 { AR5K_PHY_ANT_CTL, 0x00000001 },
651 { AR5K_PHY(66), 0x00000000 },
652 { AR5K_PHY(67), 0x00800000 },
653 { AR5K_PHY(68), 0x00000001 },
654 /*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */ 644 /*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */
655 { AR5K_PHY(71), 0x00000c80 }, 645 { AR5K_PHY_MAX_RX_LEN, 0x00000c80 },
656 { AR5K_PHY_IQ, 0x05100000 }, 646 { AR5K_PHY_IQ, 0x05100000 },
657 { AR5K_PHY(74), 0x00000001 }, 647 { AR5K_PHY_WARM_RESET, 0x00000001 },
658 { AR5K_PHY(75), 0x00000004 }, 648 { AR5K_PHY_CTL, 0x00000004 },
659 { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 }, 649 { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 },
660 { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d }, 650 { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d },
661 { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f }, 651 { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f },
662 /*{ AR5K_PHY(80), 0x00000004 },*/ 652 { AR5K_PHY(82), 0x9280b212 },
663 { AR5K_PHY(82), 0x9280b212 }, 653 { AR5K_PHY_RADAR, 0x5d50e188 },
664 { AR5K_PHY_RADAR, 0x5d50e188 },
665 /*{ AR5K_PHY(86), 0x000000ff },*/ 654 /*{ AR5K_PHY(86), 0x000000ff },*/
666 { AR5K_PHY(87), 0x004b6a8e }, 655 { AR5K_PHY(87), 0x004b6a8e },
667 { AR5K_PHY(90), 0x000003ce }, 656 { AR5K_PHY_NFTHRES, 0x000003ce },
668 { AR5K_PHY(92), 0x192fb515 }, 657 { AR5K_PHY_RESTART, 0x192fb515 },
669 /*{ AR5K_PHY(93), 0x00000000 },*/ 658 { AR5K_PHY(94), 0x00000001 },
670 { AR5K_PHY(94), 0x00000001 }, 659 { AR5K_PHY_RFBUS_REQ, 0x00000000 },
671 { AR5K_PHY(95), 0x00000000 },
672 /*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */ 660 /*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */
673 /*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */ 661 /*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */
674 { AR5K_PHY(644), 0x00806333 }, 662 { AR5K_PHY(644), 0x00806333 },
675 { AR5K_PHY(645), 0x00106c10 }, 663 { AR5K_PHY(645), 0x00106c10 },
676 { AR5K_PHY(646), 0x009c4060 }, 664 { AR5K_PHY(646), 0x009c4060 },
677 { AR5K_PHY(647), 0x1483800a }, 665 /* { AR5K_PHY(647), 0x1483800a }, */
678 /* { AR5K_PHY(648), 0x018830c6 },*/ /* 2413/2425 */ 666 /* { AR5K_PHY(648), 0x01831061 }, */ /* Old value */
679 { AR5K_PHY(648), 0x01831061 }, 667 { AR5K_PHY(648), 0x018830c6 },
680 { AR5K_PHY(649), 0x00000400 }, 668 { AR5K_PHY(649), 0x00000400 },
681 /*{ AR5K_PHY(650), 0x000001b5 },*/ 669 /*{ AR5K_PHY(650), 0x000001b5 },*/
682 { AR5K_PHY(651), 0x00000000 }, 670 { AR5K_PHY(651), 0x00000000 },
683 { AR5K_PHY_TXPOWER_RATE3, 0x20202020 }, 671 { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
684 { AR5K_PHY_TXPOWER_RATE2, 0x20202020 }, 672 { AR5K_PHY_TXPOWER_RATE2, 0x20202020 },
685 /*{ AR5K_PHY(655), 0x13c889af },*/ 673 /*{ AR5K_PHY(655), 0x13c889af },*/
686 { AR5K_PHY(656), 0x38490a20 }, 674 { AR5K_PHY(656), 0x38490a20 },
687 { AR5K_PHY(657), 0x00007bb6 }, 675 { AR5K_PHY(657), 0x00007bb6 },
688 { AR5K_PHY(658), 0x0fff3ffc }, 676 { AR5K_PHY(658), 0x0fff3ffc },
689 /*{ AR5K_PHY_CCKTXCTL, 0x00000000 },*/
690}; 677};
691 678
692/* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */ 679/* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
693static const struct ath5k_ini_mode ar5212_ini_mode_start[] = { 680static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
694 { AR5K_PHY(640),
695 /* a/XR aTurbo b g (DYN) gTurbo */
696 { 0x00000008, 0x00000008, 0x0000000b, 0x0000000e, 0x0000000e } },
697 { AR5K_PHY(0),
698 { 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 } },
699 { AR5K_QUEUE_DFS_LOCAL_IFS(0), 681 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
700 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, 682 /* a/XR aTurbo b g (DYN) gTurbo */
683 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
701 { AR5K_QUEUE_DFS_LOCAL_IFS(1), 684 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
702 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, 685 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
703 { AR5K_QUEUE_DFS_LOCAL_IFS(2), 686 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
704 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, 687 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
705 { AR5K_QUEUE_DFS_LOCAL_IFS(3), 688 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
706 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, 689 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
707 { AR5K_QUEUE_DFS_LOCAL_IFS(4), 690 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
708 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, 691 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
709 { AR5K_QUEUE_DFS_LOCAL_IFS(5), 692 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
710 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, 693 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
711 { AR5K_QUEUE_DFS_LOCAL_IFS(6), 694 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
712 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, 695 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
713 { AR5K_QUEUE_DFS_LOCAL_IFS(7), 696 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
714 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, 697 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
715 { AR5K_QUEUE_DFS_LOCAL_IFS(8), 698 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
716 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, 699 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
717 { AR5K_QUEUE_DFS_LOCAL_IFS(9), 700 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
718 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, 701 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
719 { AR5K_DCU_GBL_IFS_SIFS, 702 { AR5K_DCU_GBL_IFS_SIFS,
720 { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } }, 703 { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
721 { AR5K_DCU_GBL_IFS_SLOT, 704 { AR5K_DCU_GBL_IFS_SLOT,
722 { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } }, 705 { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
723 { AR5K_DCU_GBL_IFS_EIFS, 706 { AR5K_DCU_GBL_IFS_EIFS,
724 { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } }, 707 { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
725 { AR5K_DCU_GBL_IFS_MISC, 708 { AR5K_DCU_GBL_IFS_MISC,
726 { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } }, 709 { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
727 { AR5K_TIME_OUT, 710 { AR5K_TIME_OUT,
728 { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } }, 711 { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
729 { AR5K_PHY_TURBO, 712 { AR5K_PHY_TURBO,
730 { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } }, 713 { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
731 { AR5K_PHY(8), 714 { AR5K_PHY(8),
732 { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } }, 715 { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
733 { AR5K_PHY(9), 716 { AR5K_PHY_RF_CTL2,
734 { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } }, 717 { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
735 { AR5K_PHY(17), 718 { AR5K_PHY_SETTLING,
736 { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } }, 719 { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
737 { AR5K_PHY_AGCCTL, 720 { AR5K_PHY_AGCCTL,
738 { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d18 } }, 721 { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d18 } },
739 { AR5K_PHY_NF, 722 { AR5K_PHY_NF,
740 { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, 723 { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
741 { AR5K_PHY(26), 724 { AR5K_PHY_WEAK_OFDM_HIGH_THR,
742 { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } }, 725 { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
743 { AR5K_PHY(70), 726 { AR5K_PHY(70),
744 { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } }, 727 { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
745 { AR5K_PHY(73), 728 { AR5K_PHY_OFDM_SELFCORR,
746 { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } }, 729 { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
747 { 0xa230, 730 { 0xa230,
748 { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } }, 731 { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
749}; 732};
750 733
751/* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */ 734/* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
752/* New dump pending */ 735static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
753static const struct ath5k_ini_mode ar5212_rf5111_ini_mode_end[] = {
754 { AR5K_PHY(640), /* This one differs from ar5212_ini_mode_start ! */
755 /* a/XR aTurbo b g (DYN) gTurbo */
756 { 0x00000000, 0x00000000, 0x00000003, 0x00000006, 0x00000006 } },
757 { AR5K_TXCFG, 736 { AR5K_TXCFG,
758 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } }, 737 /* a/XR aTurbo b g (DYN) gTurbo */
738 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
759 { AR5K_USEC_5211, 739 { AR5K_USEC_5211,
760 { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } }, 740 { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
761 { AR5K_PHY(10), 741 { AR5K_PHY_RF_CTL3,
762 { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } }, 742 { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
763 { AR5K_PHY(13), 743 { AR5K_PHY_RF_CTL4,
764 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, 744 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
765 { AR5K_PHY(14), 745 { AR5K_PHY_PA_CTL,
766 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, 746 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
767 { AR5K_PHY(18), 747 { AR5K_PHY_GAIN,
768 { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } }, 748 { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
769 { AR5K_PHY(20), 749 { AR5K_PHY_DESIRED_SIZE,
770 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, 750 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
771 { AR5K_PHY_SIG, 751 { AR5K_PHY_SIG,
772 { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } }, 752 { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
773 { AR5K_PHY_AGCCOARSE, 753 { AR5K_PHY_AGCCOARSE,
774 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } }, 754 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
775 { AR5K_PHY(27), 755 { AR5K_PHY_WEAK_OFDM_LOW_THR,
776 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } }, 756 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
777 { AR5K_PHY_RX_DELAY, 757 { AR5K_PHY_RX_DELAY,
778 { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } }, 758 { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
779 { AR5K_PHY_FRAME_CTL_5211, 759 { AR5K_PHY_FRAME_CTL_5211,
780 { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } }, 760 { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
781 { AR5K_PHY_GAIN_2GHZ, 761 { AR5K_PHY_GAIN_2GHZ,
782 { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } }, 762 { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
783 { 0xa21c, 763 { AR5K_PHY_CCK_RX_CTL_4,
784 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } }, 764 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
785 { AR5K_DCU_FP, 765};
786 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 766
787 { AR5K_PHY_AGC, 767static const struct ath5k_ini rf5111_ini_common_end[] = {
788 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 768 { AR5K_DCU_FP, 0x00000000 },
789 { AR5K_PHY(11), 769 { AR5K_PHY_AGC, 0x00000000 },
790 { 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe } }, 770 { AR5K_PHY_ADC_CTL, 0x00022ffe },
791 { AR5K_PHY(15), 771 { 0x983c, 0x00020100 },
792 { 0x00020100, 0x00020100, 0x00020100, 0x00020100, 0x00020100 } }, 772 { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
793 { AR5K_PHY(19), 773 { AR5K_PHY_PAPD_PROBE, 0x00004883 },
794 { 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c } }, 774 { 0x9940, 0x00000004 },
795 { AR5K_PHY_PAPD_PROBE, 775 { 0x9958, 0x000000ff },
796 { 0x00004883, 0x00004883, 0x00004883, 0x00004883, 0x00004883 } }, 776 { 0x9974, 0x00000000 },
797 { AR5K_PHY(80), 777 { AR5K_PHY_SPENDING, 0x00000018 },
798 { 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 } }, 778 { AR5K_PHY_CCKTXCTL, 0x00000000 },
799 { AR5K_PHY(86), 779 { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 },
800 { 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } }, 780 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
801 { AR5K_PHY(93), 781 { 0xa23c, 0x13c889af },
802 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
803 { AR5K_PHY_SPENDING,
804 { 0x00000018, 0x00000018, 0x00000018, 0x00000018, 0x00000018 } },
805 { AR5K_PHY_CCKTXCTL,
806 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
807 { AR5K_PHY(642),
808 { 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
809 { 0xa228,
810 { 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5 } },
811 { 0xa23c,
812 { 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af } },
813}; 782};
814 783
815/* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */ 784/* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
816/* XXX: No dumps for turbog yet, but i found settings from old values so it should be ok */ 785static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
817static const struct ath5k_ini_mode ar5212_rf5112_ini_mode_end[] = {
818 { AR5K_TXCFG, 786 { AR5K_TXCFG,
819 /* a/XR aTurbo b g (DYN) gTurbo */ 787 /* a/XR aTurbo b g (DYN) gTurbo */
820 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } }, 788 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
821 { AR5K_USEC_5211, 789 { AR5K_USEC_5211,
822 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, 790 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
823 { AR5K_PHY(10), 791 { AR5K_PHY_RF_CTL3,
824 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } }, 792 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
825 { AR5K_PHY(13), 793 { AR5K_PHY_RF_CTL4,
826 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, 794 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
827 { AR5K_PHY(14), 795 { AR5K_PHY_PA_CTL,
828 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, 796 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
829 { AR5K_PHY(18), 797 { AR5K_PHY_GAIN,
830 { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } }, 798 { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
831 { AR5K_PHY(20), 799 { AR5K_PHY_DESIRED_SIZE,
832 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, 800 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
833 { AR5K_PHY_SIG, 801 { AR5K_PHY_SIG,
834 { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7ee80d2e } }, 802 { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7ee80d2e } },
835 { AR5K_PHY_AGCCOARSE, 803 { AR5K_PHY_AGCCOARSE,
836 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } }, 804 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
837 { AR5K_PHY(27), 805 { AR5K_PHY_WEAK_OFDM_LOW_THR,
838 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, 806 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
839 { AR5K_PHY_RX_DELAY, 807 { AR5K_PHY_RX_DELAY,
840 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, 808 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
841 { AR5K_PHY_FRAME_CTL_5211, 809 { AR5K_PHY_FRAME_CTL_5211,
842 { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } }, 810 { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
843 { AR5K_PHY_CCKTXCTL, 811 { AR5K_PHY_CCKTXCTL,
844 { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } }, 812 { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
845 { AR5K_PHY(642), 813 { AR5K_PHY_CCK_CROSSCORR,
846 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, 814 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
847 { AR5K_PHY_GAIN_2GHZ, 815 { AR5K_PHY_GAIN_2GHZ,
848 { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } }, 816 { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
849 { 0xa21c, 817 { AR5K_PHY_CCK_RX_CTL_4,
850 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } }, 818 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
851 { AR5K_DCU_FP, 819};
852 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 820
853 { AR5K_PHY_AGC, 821static const struct ath5k_ini rf5112_ini_common_end[] = {
854 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 822 { AR5K_DCU_FP, 0x00000000 },
855 { AR5K_PHY(11), 823 { AR5K_PHY_AGC, 0x00000000 },
856 { 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe } }, 824 { AR5K_PHY_ADC_CTL, 0x00022ffe },
857 { AR5K_PHY(15), 825 { 0x983c, 0x00020100 },
858 { 0x00020100, 0x00020100, 0x00020100, 0x00020100, 0x00020100 } }, 826 { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
859 { AR5K_PHY(19), 827 { AR5K_PHY_PAPD_PROBE, 0x00004882 },
860 { 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c } }, 828 { 0x9940, 0x00000004 },
861 { AR5K_PHY_PAPD_PROBE, 829 { 0x9958, 0x000000ff },
862 { 0x00004882, 0x00004882, 0x00004882, 0x00004882, 0x00004882 } }, 830 { 0x9974, 0x00000000 },
863 { AR5K_PHY(80), 831 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
864 { 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 } }, 832 { 0xa23c, 0x13c889af },
865 { AR5K_PHY(86),
866 { 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } },
867 { AR5K_PHY(93),
868 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
869 { 0xa228,
870 { 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5 } },
871 { 0xa23c,
872 { 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af } },
873}; 833};
874 834
875/* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */ 835/* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
876/* XXX: No dumps for turbog yet, so turbog is the same with g here with some
877 * minor tweaking based on dumps from other chips */
878static const struct ath5k_ini_mode rf5413_ini_mode_end[] = { 836static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
879 { AR5K_TXCFG, 837 { AR5K_TXCFG,
880 /* a/XR aTurbo b g gTurbo */ 838 /* a/XR aTurbo b g (DYN) gTurbo */
881 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } }, 839 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
882 { AR5K_USEC_5211, 840 { AR5K_USEC_5211,
883 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, 841 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
884 { AR5K_PHY(10), 842 { AR5K_PHY_RF_CTL3,
885 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } }, 843 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
886 { AR5K_PHY(13), 844 { AR5K_PHY_RF_CTL4,
887 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, 845 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
888 { AR5K_PHY(14), 846 { AR5K_PHY_PA_CTL,
889 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, 847 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
890 { AR5K_PHY(18), 848 { AR5K_PHY_GAIN,
891 { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } }, 849 { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
892 { AR5K_PHY(20), 850 { AR5K_PHY_DESIRED_SIZE,
893 { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } }, 851 { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
894 { AR5K_PHY_SIG, 852 { AR5K_PHY_SIG,
895 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } }, 853 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
896 { AR5K_PHY_AGCCOARSE, 854 { AR5K_PHY_AGCCOARSE,
897 { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } }, 855 { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
898 { AR5K_PHY(27), 856 { AR5K_PHY_WEAK_OFDM_LOW_THR,
899 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, 857 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
900 { AR5K_PHY_RX_DELAY, 858 { AR5K_PHY_RX_DELAY,
901 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, 859 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
902 { AR5K_PHY_FRAME_CTL_5211, 860 { AR5K_PHY_FRAME_CTL_5211,
903 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } }, 861 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
904 { AR5K_PHY_CCKTXCTL, 862 { AR5K_PHY_CCKTXCTL,
905 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 863 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
906 { AR5K_PHY(642), 864 { AR5K_PHY_CCK_CROSSCORR,
907 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, 865 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
908 { AR5K_PHY_GAIN_2GHZ, 866 { AR5K_PHY_GAIN_2GHZ,
909 { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } }, 867 { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
910 { 0xa21c, 868 { AR5K_PHY_CCK_RX_CTL_4,
911 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } }, 869 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
912 { 0xa300, 870 { 0xa300,
913 { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } }, 871 { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
914 { 0xa304, 872 { 0xa304,
915 { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } }, 873 { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
916 { 0xa308, 874 { 0xa308,
917 { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } }, 875 { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
918 { 0xa30c, 876 { 0xa30c,
919 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } }, 877 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
920 { 0xa310, 878 { 0xa310,
921 { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } }, 879 { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
922 { 0xa314, 880 { 0xa314,
923 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } }, 881 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
924 { 0xa318, 882 { 0xa318,
925 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } }, 883 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
926 { 0xa31c, 884 { 0xa31c,
927 { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } }, 885 { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
928 { 0xa320, 886 { 0xa320,
929 { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } }, 887 { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
930 { 0xa324, 888 { 0xa324,
931 { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } }, 889 { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
932 { 0xa328, 890 { 0xa328,
933 { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } }, 891 { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
934 { 0xa32c, 892 { 0xa32c,
935 { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } }, 893 { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
936 { 0xa330, 894 { 0xa330,
937 { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } }, 895 { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
938 { 0xa334, 896 { 0xa334,
939 { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } }, 897 { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
940 { AR5K_DCU_FP, 898};
941 { 0x000003e0, 0x000003e0, 0x000003e0, 0x000003e0, 0x000003e0 } }, 899
942 { 0x4068, 900static const struct ath5k_ini rf5413_ini_common_end[] = {
943 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, 901 { AR5K_DCU_FP, 0x000003e0 },
944 { 0x8060, 902 { AR5K_5414_CBCFG, 0x00000010 },
945 { 0x0000000f, 0x0000000f, 0x0000000f, 0x0000000f, 0x0000000f } }, 903 { AR5K_SEQ_MASK, 0x0000000f },
946 { 0x809c, 904 { 0x809c, 0x00000000 },
947 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 905 { 0x80a0, 0x00000000 },
948 { 0x80a0, 906 { AR5K_MIC_QOS_CTL, 0x00000000 },
949 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 907 { AR5K_MIC_QOS_SEL, 0x00000000 },
950 { 0x8118, 908 { AR5K_MISC_MODE, 0x00000000 },
951 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 909 { AR5K_OFDM_FIL_CNT, 0x00000000 },
952 { 0x811c, 910 { AR5K_CCK_FIL_CNT, 0x00000000 },
953 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 911 { AR5K_PHYERR_CNT1, 0x00000000 },
954 { 0x8120, 912 { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
955 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 913 { AR5K_PHYERR_CNT2, 0x00000000 },
956 { 0x8124, 914 { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
957 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 915 { AR5K_TSF_THRES, 0x00000000 },
958 { 0x8128, 916 { 0x8140, 0x800003f9 },
959 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 917 { 0x8144, 0x00000000 },
960 { 0x812c, 918 { AR5K_PHY_AGC, 0x00000000 },
961 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 919 { AR5K_PHY_ADC_CTL, 0x0000a000 },
962 { 0x8130, 920 { 0x983c, 0x00200400 },
963 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 921 { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
964 { 0x8134, 922 { AR5K_PHY_SCR, 0x0000001f },
965 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 923 { AR5K_PHY_SLMT, 0x00000080 },
966 { 0x8138, 924 { AR5K_PHY_SCAL, 0x0000000e },
967 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 925 { 0x9958, 0x00081fff },
968 { 0x813c, 926 { AR5K_PHY_TIMING_7, 0x00000000 },
969 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 927 { AR5K_PHY_TIMING_8, 0x02800000 },
970 { 0x8140, 928 { AR5K_PHY_TIMING_11, 0x00000000 },
971 { 0x800003f9, 0x800003f9, 0x800003f9, 0x800003f9, 0x800003f9 } }, 929 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
972 { 0x8144, 930 { 0x99e4, 0xaaaaaaaa },
973 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 931 { 0x99e8, 0x3c466478 },
974 { AR5K_PHY_AGC, 932 { 0x99ec, 0x000000aa },
975 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 933 { AR5K_PHY_SCLOCK, 0x0000000c },
976 { AR5K_PHY(11), 934 { AR5K_PHY_SDELAY, 0x000000ff },
977 { 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000 } }, 935 { AR5K_PHY_SPENDING, 0x00000014 },
978 { AR5K_PHY(15), 936 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
979 { 0x00200400, 0x00200400, 0x00200400, 0x00200400, 0x00200400 } }, 937 { 0xa23c, 0x93c889af },
980 { AR5K_PHY(19), 938 { AR5K_PHY_FAST_ADC, 0x00000001 },
981 { 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c } }, 939 { 0xa250, 0x0000a000 },
982 { AR5K_PHY_SCR, 940 { AR5K_PHY_BLUETOOTH, 0x00000000 },
983 { 0x0000001f, 0x0000001f, 0x0000001f, 0x0000001f, 0x0000001f } }, 941 { AR5K_PHY_TPC_RG1, 0x0cc75380 },
984 { AR5K_PHY_SLMT, 942 { 0xa25c, 0x0f0f0f01 },
985 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, 943 { 0xa260, 0x5f690f01 },
986 { AR5K_PHY_SCAL, 944 { 0xa264, 0x00418a11 },
987 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } }, 945 { 0xa268, 0x00000000 },
988 { AR5K_PHY(86), 946 { AR5K_PHY_TPC_RG5, 0x0c30c16a },
989 { 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff } }, 947 { 0xa270, 0x00820820 },
990 { AR5K_PHY(96), 948 { 0xa274, 0x081b7caa },
991 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 949 { 0xa278, 0x1ce739ce },
992 { AR5K_PHY(97), 950 { 0xa27c, 0x051701ce },
993 { 0x02800000, 0x02800000, 0x02800000, 0x02800000, 0x02800000 } }, 951 { 0xa338, 0x00000000 },
994 { AR5K_PHY(104), 952 { 0xa33c, 0x00000000 },
995 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 953 { 0xa340, 0x00000000 },
996 { AR5K_PHY(120), 954 { 0xa344, 0x00000000 },
997 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, 955 { 0xa348, 0x3fffffff },
998 { AR5K_PHY(121), 956 { 0xa34c, 0x3fffffff },
999 { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa } }, 957 { 0xa350, 0x3fffffff },
1000 { AR5K_PHY(122), 958 { 0xa354, 0x0003ffff },
1001 { 0x3c466478, 0x3c466478, 0x3c466478, 0x3c466478, 0x3c466478 } }, 959 { 0xa358, 0x79a8aa1f },
1002 { AR5K_PHY(123), 960 { 0xa35c, 0x066c420f },
1003 { 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa } }, 961 { 0xa360, 0x0f282207 },
1004 { AR5K_PHY_SCLOCK, 962 { 0xa364, 0x17601685 },
1005 { 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c } }, 963 { 0xa368, 0x1f801104 },
1006 { AR5K_PHY_SDELAY, 964 { 0xa36c, 0x37a00c03 },
1007 { 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } }, 965 { 0xa370, 0x3fc40883 },
1008 { AR5K_PHY_SPENDING, 966 { 0xa374, 0x57c00803 },
1009 { 0x00000014, 0x00000014, 0x00000014, 0x00000014, 0x00000014 } }, 967 { 0xa378, 0x5fd80682 },
1010 { 0xa228, 968 { 0xa37c, 0x7fe00482 },
1011 { 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5 } }, 969 { 0xa380, 0x7f3c7bba },
1012 { 0xa23c, 970 { 0xa384, 0xf3307ff0 },
1013 { 0x93c889af, 0x93c889af, 0x93c889af, 0x93c889af, 0x93c889af } },
1014 { 0xa24c,
1015 { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
1016 { 0xa250,
1017 { 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000 } },
1018 { 0xa254,
1019 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1020 { 0xa258,
1021 { 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380 } },
1022 { 0xa25c,
1023 { 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01 } },
1024 { 0xa260,
1025 { 0x5f690f01, 0x5f690f01, 0x5f690f01, 0x5f690f01, 0x5f690f01 } },
1026 { 0xa264,
1027 { 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11 } },
1028 { 0xa268,
1029 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1030 { 0xa26c,
1031 { 0x0c30c16a, 0x0c30c16a, 0x0c30c16a, 0x0c30c16a, 0x0c30c16a } },
1032 { 0xa270,
1033 { 0x00820820, 0x00820820, 0x00820820, 0x00820820, 0x00820820 } },
1034 { 0xa274,
1035 { 0x081b7caa, 0x081b7caa, 0x081b7caa, 0x081b7caa, 0x081b7caa } },
1036 { 0xa278,
1037 { 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce } },
1038 { 0xa27c,
1039 { 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce } },
1040 { 0xa338,
1041 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1042 { 0xa33c,
1043 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1044 { 0xa340,
1045 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1046 { 0xa344,
1047 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1048 { 0xa348,
1049 { 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1050 { 0xa34c,
1051 { 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1052 { 0xa350,
1053 { 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1054 { 0xa354,
1055 { 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff } },
1056 { 0xa358,
1057 { 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f } },
1058 { 0xa35c,
1059 { 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f } },
1060 { 0xa360,
1061 { 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207 } },
1062 { 0xa364,
1063 { 0x17601685, 0x17601685, 0x17601685, 0x17601685, 0x17601685 } },
1064 { 0xa368,
1065 { 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104 } },
1066 { 0xa36c,
1067 { 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03 } },
1068 { 0xa370,
1069 { 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883 } },
1070 { 0xa374,
1071 { 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803 } },
1072 { 0xa378,
1073 { 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682 } },
1074 { 0xa37c,
1075 { 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482 } },
1076 { 0xa380,
1077 { 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba } },
1078 { 0xa384,
1079 { 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0 } },
1080}; 971};
1081 972
1082/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */ 973/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
1083/* XXX: No dumps for turbog yet, so turbog is the same with g here with some 974/* XXX: a mode ? */
1084 * minor tweaking based on dumps from other chips */
1085static const struct ath5k_ini_mode rf2413_ini_mode_end[] = { 975static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
1086 { AR5K_TXCFG, 976 { AR5K_TXCFG,
1087 /* b g gTurbo */ 977 /* a/XR aTurbo b g (DYN) gTurbo */
1088 { 0x00000015, 0x00000015, 0x00000015 } }, 978 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
1089 { AR5K_USEC_5211, 979 { AR5K_USEC_5211,
1090 { 0x04e01395, 0x12e013ab, 0x098813cf } }, 980 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
1091 { AR5K_PHY(10), 981 { AR5K_PHY_RF_CTL3,
1092 { 0x05020000, 0x0a020001, 0x0a020001 } }, 982 { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } },
1093 { AR5K_PHY(13), 983 { AR5K_PHY_RF_CTL4,
1094 { 0x00000e00, 0x00000e00, 0x00000e00 } }, 984 { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } },
1095 { AR5K_PHY(14), 985 { AR5K_PHY_PA_CTL,
1096 { 0x0000000a, 0x0000000a, 0x0000000a } }, 986 { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } },
1097 { AR5K_PHY(18), 987 { AR5K_PHY_GAIN,
1098 { 0x001a6a64, 0x001a6a64, 0x001a6a64 } }, 988 { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
1099 { AR5K_PHY(20), 989 { AR5K_PHY_DESIRED_SIZE,
1100 { 0x0de8b0da, 0x0c98b0da, 0x0c98b0da } }, 990 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } },
1101 { AR5K_PHY_SIG, 991 { AR5K_PHY_SIG,
1102 { 0x7ee80d2e, 0x7ec80d2e, 0x7ec80d2e } }, 992 { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } },
1103 { AR5K_PHY_AGCCOARSE, 993 { AR5K_PHY_AGCCOARSE,
1104 { 0x3137665e, 0x3139605e, 0x3139605e } }, 994 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } },
1105 { AR5K_PHY(27), 995 { AR5K_PHY_WEAK_OFDM_LOW_THR,
1106 { 0x050cb081, 0x050cb081, 0x050cb081 } }, 996 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
1107 { AR5K_PHY_RX_DELAY, 997 { AR5K_PHY_RX_DELAY,
1108 { 0x0000044c, 0x00000898, 0x000007d0 } }, 998 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
1109 { AR5K_PHY_FRAME_CTL_5211, 999 { AR5K_PHY_FRAME_CTL_5211,
1110 { 0xf7b80d00, 0xf7b81000, 0xf7b81000 } }, 1000 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
1111 { AR5K_PHY_CCKTXCTL, 1001 { AR5K_PHY_CCKTXCTL,
1112 { 0x00000000, 0x00000000, 0x00000000 } }, 1002 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1113 { AR5K_PHY(642), 1003 { AR5K_PHY_CCK_CROSSCORR,
1114 { 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, 1004 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
1115 { AR5K_PHY_GAIN_2GHZ, 1005 { AR5K_PHY_GAIN_2GHZ,
1116 { 0x0042c140, 0x0042c140, 0x0042c140 } }, 1006 { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } },
1117 { 0xa21c, 1007 { AR5K_PHY_CCK_RX_CTL_4,
1118 { 0x1863800a, 0x1883800a, 0x1883800a } }, 1008 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
1119 { AR5K_DCU_FP, 1009};
1120 { 0x000003e0, 0x000003e0, 0x000003e0 } }, 1010
1121 { 0x8060, 1011static const struct ath5k_ini rf2413_ini_common_end[] = {
1122 { 0x0000000f, 0x0000000f, 0x0000000f } }, 1012 { AR5K_DCU_FP, 0x000003e0 },
1123 { 0x8118, 1013 { AR5K_SEQ_MASK, 0x0000000f },
1124 { 0x00000000, 0x00000000, 0x00000000 } }, 1014 { AR5K_MIC_QOS_CTL, 0x00000000 },
1125 { 0x811c, 1015 { AR5K_MIC_QOS_SEL, 0x00000000 },
1126 { 0x00000000, 0x00000000, 0x00000000 } }, 1016 { AR5K_MISC_MODE, 0x00000000 },
1127 { 0x8120, 1017 { AR5K_OFDM_FIL_CNT, 0x00000000 },
1128 { 0x00000000, 0x00000000, 0x00000000 } }, 1018 { AR5K_CCK_FIL_CNT, 0x00000000 },
1129 { 0x8124, 1019 { AR5K_PHYERR_CNT1, 0x00000000 },
1130 { 0x00000000, 0x00000000, 0x00000000 } }, 1020 { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
1131 { 0x8128, 1021 { AR5K_PHYERR_CNT2, 0x00000000 },
1132 { 0x00000000, 0x00000000, 0x00000000 } }, 1022 { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
1133 { 0x812c, 1023 { AR5K_TSF_THRES, 0x00000000 },
1134 { 0x00000000, 0x00000000, 0x00000000 } }, 1024 { 0x8140, 0x800000a8 },
1135 { 0x8130, 1025 { 0x8144, 0x00000000 },
1136 { 0x00000000, 0x00000000, 0x00000000 } }, 1026 { AR5K_PHY_AGC, 0x00000000 },
1137 { 0x8134, 1027 { AR5K_PHY_ADC_CTL, 0x0000a000 },
1138 { 0x00000000, 0x00000000, 0x00000000 } }, 1028 { 0x983c, 0x00200400 },
1139 { 0x8138, 1029 { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
1140 { 0x00000000, 0x00000000, 0x00000000 } }, 1030 { AR5K_PHY_SCR, 0x0000001f },
1141 { 0x813c, 1031 { AR5K_PHY_SLMT, 0x00000080 },
1142 { 0x00000000, 0x00000000, 0x00000000 } }, 1032 { AR5K_PHY_SCAL, 0x0000000e },
1143 { 0x8140, 1033 { 0x9958, 0x000000ff },
1144 { 0x800000a8, 0x800000a8, 0x800000a8 } }, 1034 { AR5K_PHY_TIMING_7, 0x00000000 },
1145 { 0x8144, 1035 { AR5K_PHY_TIMING_8, 0x02800000 },
1146 { 0x00000000, 0x00000000, 0x00000000 } }, 1036 { AR5K_PHY_TIMING_11, 0x00000000 },
1147 { AR5K_PHY_AGC, 1037 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
1148 { 0x00000000, 0x00000000, 0x00000000 } }, 1038 { 0x99e4, 0xaaaaaaaa },
1149 { AR5K_PHY(11), 1039 { 0x99e8, 0x3c466478 },
1150 { 0x0000a000, 0x0000a000, 0x0000a000 } }, 1040 { 0x99ec, 0x000000aa },
1151 { AR5K_PHY(15), 1041 { AR5K_PHY_SCLOCK, 0x0000000c },
1152 { 0x00200400, 0x00200400, 0x00200400 } }, 1042 { AR5K_PHY_SDELAY, 0x000000ff },
1153 { AR5K_PHY(19), 1043 { AR5K_PHY_SPENDING, 0x00000014 },
1154 { 0x1284233c, 0x1284233c, 0x1284233c } }, 1044 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
1155 { AR5K_PHY_SCR, 1045 { 0xa23c, 0x93c889af },
1156 { 0x0000001f, 0x0000001f, 0x0000001f } }, 1046 { AR5K_PHY_FAST_ADC, 0x00000001 },
1157 { AR5K_PHY_SLMT, 1047 { 0xa250, 0x0000a000 },
1158 { 0x00000080, 0x00000080, 0x00000080 } }, 1048 { AR5K_PHY_BLUETOOTH, 0x00000000 },
1159 { AR5K_PHY_SCAL, 1049 { AR5K_PHY_TPC_RG1, 0x0cc75380 },
1160 { 0x0000000e, 0x0000000e, 0x0000000e } }, 1050 { 0xa25c, 0x0f0f0f01 },
1161 { AR5K_PHY(86), 1051 { 0xa260, 0x5f690f01 },
1162 { 0x000000ff, 0x000000ff, 0x000000ff } }, 1052 { 0xa264, 0x00418a11 },
1163 { AR5K_PHY(96), 1053 { 0xa268, 0x00000000 },
1164 { 0x00000000, 0x00000000, 0x00000000 } }, 1054 { AR5K_PHY_TPC_RG5, 0x0c30c16a },
1165 { AR5K_PHY(97), 1055 { 0xa270, 0x00820820 },
1166 { 0x02800000, 0x02800000, 0x02800000 } }, 1056 { 0xa274, 0x001b7caa },
1167 { AR5K_PHY(104), 1057 { 0xa278, 0x1ce739ce },
1168 { 0x00000000, 0x00000000, 0x00000000 } }, 1058 { 0xa27c, 0x051701ce },
1169 { AR5K_PHY(120), 1059 { 0xa300, 0x18010000 },
1170 { 0x00000000, 0x00000000, 0x00000000 } }, 1060 { 0xa304, 0x30032602 },
1171 { AR5K_PHY(121), 1061 { 0xa308, 0x48073e06 },
1172 { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa } }, 1062 { 0xa30c, 0x560b4c0a },
1173 { AR5K_PHY(122), 1063 { 0xa310, 0x641a600f },
1174 { 0x3c466478, 0x3c466478, 0x3c466478 } }, 1064 { 0xa314, 0x784f6e1b },
1175 { AR5K_PHY(123), 1065 { 0xa318, 0x868f7c5a },
1176 { 0x000000aa, 0x000000aa, 0x000000aa } }, 1066 { 0xa31c, 0x8ecf865b },
1177 { AR5K_PHY_SCLOCK, 1067 { 0xa320, 0x9d4f970f },
1178 { 0x0000000c, 0x0000000c, 0x0000000c } }, 1068 { 0xa324, 0xa5cfa18f },
1179 { AR5K_PHY_SDELAY, 1069 { 0xa328, 0xb55faf1f },
1180 { 0x000000ff, 0x000000ff, 0x000000ff } }, 1070 { 0xa32c, 0xbddfb99f },
1181 { AR5K_PHY_SPENDING, 1071 { 0xa330, 0xcd7fc73f },
1182 { 0x00000014, 0x00000014, 0x00000014 } }, 1072 { 0xa334, 0xd5ffd1bf },
1183 { 0xa228, 1073 { 0xa338, 0x00000000 },
1184 { 0x000009b5, 0x000009b5, 0x000009b5 } }, 1074 { 0xa33c, 0x00000000 },
1185 { 0xa23c, 1075 { 0xa340, 0x00000000 },
1186 { 0x93c889af, 0x93c889af, 0x93c889af } }, 1076 { 0xa344, 0x00000000 },
1187 { 0xa24c, 1077 { 0xa348, 0x3fffffff },
1188 { 0x00000001, 0x00000001, 0x00000001 } }, 1078 { 0xa34c, 0x3fffffff },
1189 { 0xa250, 1079 { 0xa350, 0x3fffffff },
1190 { 0x0000a000, 0x0000a000, 0x0000a000 } }, 1080 { 0xa354, 0x0003ffff },
1191 { 0xa254, 1081 { 0xa358, 0x79a8aa1f },
1192 { 0x00000000, 0x00000000, 0x00000000 } }, 1082 { 0xa35c, 0x066c420f },
1193 { 0xa258, 1083 { 0xa360, 0x0f282207 },
1194 { 0x0cc75380, 0x0cc75380, 0x0cc75380 } }, 1084 { 0xa364, 0x17601685 },
1195 { 0xa25c, 1085 { 0xa368, 0x1f801104 },
1196 { 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01 } }, 1086 { 0xa36c, 0x37a00c03 },
1197 { 0xa260, 1087 { 0xa370, 0x3fc40883 },
1198 { 0x5f690f01, 0x5f690f01, 0x5f690f01 } }, 1088 { 0xa374, 0x57c00803 },
1199 { 0xa264, 1089 { 0xa378, 0x5fd80682 },
1200 { 0x00418a11, 0x00418a11, 0x00418a11 } }, 1090 { 0xa37c, 0x7fe00482 },
1201 { 0xa268, 1091 { 0xa380, 0x7f3c7bba },
1202 { 0x00000000, 0x00000000, 0x00000000 } }, 1092 { 0xa384, 0xf3307ff0 },
1203 { 0xa26c,
1204 { 0x0c30c16a, 0x0c30c16a, 0x0c30c16a } },
1205 { 0xa270,
1206 { 0x00820820, 0x00820820, 0x00820820 } },
1207 { 0xa274,
1208 { 0x001b7caa, 0x001b7caa, 0x001b7caa } },
1209 { 0xa278,
1210 { 0x1ce739ce, 0x1ce739ce, 0x1ce739ce } },
1211 { 0xa27c,
1212 { 0x051701ce, 0x051701ce, 0x051701ce } },
1213 { 0xa300,
1214 { 0x18010000, 0x18010000, 0x18010000 } },
1215 { 0xa304,
1216 { 0x30032602, 0x30032602, 0x30032602 } },
1217 { 0xa308,
1218 { 0x48073e06, 0x48073e06, 0x48073e06 } },
1219 { 0xa30c,
1220 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
1221 { 0xa310,
1222 { 0x641a600f, 0x641a600f, 0x641a600f } },
1223 { 0xa314,
1224 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
1225 { 0xa318,
1226 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
1227 { 0xa31c,
1228 { 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
1229 { 0xa320,
1230 { 0x9d4f970f, 0x9d4f970f, 0x9d4f970f } },
1231 { 0xa324,
1232 { 0xa5cfa18f, 0xa5cfa18f, 0xa5cfa18f } },
1233 { 0xa328,
1234 { 0xb55faf1f, 0xb55faf1f, 0xb55faf1f } },
1235 { 0xa32c,
1236 { 0xbddfb99f, 0xbddfb99f, 0xbddfb99f } },
1237 { 0xa330,
1238 { 0xcd7fc73f, 0xcd7fc73f, 0xcd7fc73f } },
1239 { 0xa334,
1240 { 0xd5ffd1bf, 0xd5ffd1bf, 0xd5ffd1bf } },
1241 { 0xa338,
1242 { 0x00000000, 0x00000000, 0x00000000 } },
1243 { 0xa33c,
1244 { 0x00000000, 0x00000000, 0x00000000 } },
1245 { 0xa340,
1246 { 0x00000000, 0x00000000, 0x00000000 } },
1247 { 0xa344,
1248 { 0x00000000, 0x00000000, 0x00000000 } },
1249 { 0xa348,
1250 { 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1251 { 0xa34c,
1252 { 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1253 { 0xa350,
1254 { 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1255 { 0xa354,
1256 { 0x0003ffff, 0x0003ffff, 0x0003ffff } },
1257 { 0xa358,
1258 { 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f } },
1259 { 0xa35c,
1260 { 0x066c420f, 0x066c420f, 0x066c420f } },
1261 { 0xa360,
1262 { 0x0f282207, 0x0f282207, 0x0f282207 } },
1263 { 0xa364,
1264 { 0x17601685, 0x17601685, 0x17601685 } },
1265 { 0xa368,
1266 { 0x1f801104, 0x1f801104, 0x1f801104 } },
1267 { 0xa36c,
1268 { 0x37a00c03, 0x37a00c03, 0x37a00c03 } },
1269 { 0xa370,
1270 { 0x3fc40883, 0x3fc40883, 0x3fc40883 } },
1271 { 0xa374,
1272 { 0x57c00803, 0x57c00803, 0x57c00803 } },
1273 { 0xa378,
1274 { 0x5fd80682, 0x5fd80682, 0x5fd80682 } },
1275 { 0xa37c,
1276 { 0x7fe00482, 0x7fe00482, 0x7fe00482 } },
1277 { 0xa380,
1278 { 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba } },
1279 { 0xa384,
1280 { 0xf3307ff0, 0xf3307ff0, 0xf3307ff0 } },
1281}; 1093};
1282 1094
1283/* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */ 1095/* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
1284/* XXX: No dumps for turbog yet, so turbog is the same with g here with some 1096/* XXX: a mode ? */
1285 * minor tweaking based on dumps from other chips */
1286static const struct ath5k_ini_mode rf2425_ini_mode_end[] = { 1097static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
1287 { AR5K_TXCFG, 1098 { AR5K_TXCFG,
1288 /* g gTurbo */ 1099 /* a/XR aTurbo b g (DYN) gTurbo */
1289 { 0x00000015, 0x00000015 } }, 1100 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
1290 { AR5K_USEC_5211, 1101 { AR5K_USEC_5211,
1291 { 0x12e013ab, 0x098813cf } }, 1102 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
1292 { AR5K_PHY_TURBO, 1103 { AR5K_PHY_TURBO,
1293 { 0x00000000, 0x00000003 } }, 1104 { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } },
1294 { AR5K_PHY(10), 1105 { AR5K_PHY_RF_CTL3,
1295 { 0x0a020001, 0x0a020001 } }, 1106 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
1296 { AR5K_PHY(13), 1107 { AR5K_PHY_RF_CTL4,
1297 { 0x00000e0e, 0x00000e0e } }, 1108 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
1298 { AR5K_PHY(14), 1109 { AR5K_PHY_PA_CTL,
1299 { 0x0000000b, 0x0000000b } }, 1110 { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } },
1300 { AR5K_PHY(17), 1111 { AR5K_PHY_SETTLING,
1301 { 0x13721422, 0x13721422 } }, 1112 { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } },
1302 { AR5K_PHY(18), 1113 { AR5K_PHY_GAIN,
1303 { 0x00199a65, 0x00199a65 } }, 1114 { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } },
1304 { AR5K_PHY(20), 1115 { AR5K_PHY_DESIRED_SIZE,
1305 { 0x0c98b0da, 0x0c98b0da } }, 1116 { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
1306 { AR5K_PHY_SIG, 1117 { AR5K_PHY_SIG,
1307 { 0x7ec80d2e, 0x7ec80d2e } }, 1118 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
1308 { AR5K_PHY_AGCCOARSE, 1119 { AR5K_PHY_AGCCOARSE,
1309 { 0x3139605e, 0x3139605e } }, 1120 { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
1310 { AR5K_PHY(27), 1121 { AR5K_PHY_WEAK_OFDM_LOW_THR,
1311 { 0x050cb081, 0x050cb081 } }, 1122 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
1312 { AR5K_PHY_RX_DELAY, 1123 { AR5K_PHY_RX_DELAY,
1313 { 0x00000898, 0x000007d0 } }, 1124 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
1314 { AR5K_PHY_FRAME_CTL_5211, 1125 { AR5K_PHY_FRAME_CTL_5211,
1315 { 0xf7b81000, 0xf7b81000 } }, 1126 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
1316 { AR5K_PHY_CCKTXCTL, 1127 { AR5K_PHY_CCKTXCTL,
1317 { 0x00000000, 0x00000000 } }, 1128 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1318 { AR5K_PHY(642), 1129 { AR5K_PHY_CCK_CROSSCORR,
1319 { 0xd03e6788, 0xd03e6788 } }, 1130 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
1320 { AR5K_PHY_GAIN_2GHZ, 1131 { AR5K_PHY_GAIN_2GHZ,
1321 { 0x0052c140, 0x0052c140 } }, 1132 { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } },
1322 { 0xa21c, 1133 { AR5K_PHY_CCK_RX_CTL_4,
1323 { 0x1883800a, 0x1883800a } }, 1134 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
1324 { 0xa324, 1135 { 0xa324,
1325 { 0xa7cfa7cf, 0xa7cfa7cf } }, 1136 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1326 { 0xa328, 1137 { 0xa328,
1327 { 0xa7cfa7cf, 0xa7cfa7cf } }, 1138 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1328 { 0xa32c, 1139 { 0xa32c,
1329 { 0xa7cfa7cf, 0xa7cfa7cf } }, 1140 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1330 { 0xa330, 1141 { 0xa330,
1331 { 0xa7cfa7cf, 0xa7cfa7cf } }, 1142 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1332 { 0xa334, 1143 { 0xa334,
1333 { 0xa7cfa7cf, 0xa7cfa7cf } }, 1144 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1334 { AR5K_DCU_FP, 1145};
1335 { 0x000003e0, 0x000003e0 } }, 1146
1336 { 0x8060, 1147static const struct ath5k_ini rf2425_ini_common_end[] = {
1337 { 0x0000000f, 0x0000000f } }, 1148 { AR5K_DCU_FP, 0x000003e0 },
1338 { 0x809c, 1149 { AR5K_SEQ_MASK, 0x0000000f },
1339 { 0x00000000, 0x00000000 } }, 1150 { 0x809c, 0x00000000 },
1340 { 0x80a0, 1151 { 0x80a0, 0x00000000 },
1341 { 0x00000000, 0x00000000 } }, 1152 { AR5K_MIC_QOS_CTL, 0x00000000 },
1342 { 0x8118, 1153 { AR5K_MIC_QOS_SEL, 0x00000000 },
1343 { 0x00000000, 0x00000000 } }, 1154 { AR5K_MISC_MODE, 0x00000000 },
1344 { 0x811c, 1155 { AR5K_OFDM_FIL_CNT, 0x00000000 },
1345 { 0x00000000, 0x00000000 } }, 1156 { AR5K_CCK_FIL_CNT, 0x00000000 },
1346 { 0x8120, 1157 { AR5K_PHYERR_CNT1, 0x00000000 },
1347 { 0x00000000, 0x00000000 } }, 1158 { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
1348 { 0x8124, 1159 { AR5K_PHYERR_CNT2, 0x00000000 },
1349 { 0x00000000, 0x00000000 } }, 1160 { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
1350 { 0x8128, 1161 { AR5K_TSF_THRES, 0x00000000 },
1351 { 0x00000000, 0x00000000 } }, 1162 { 0x8140, 0x800003f9 },
1352 { 0x812c, 1163 { 0x8144, 0x00000000 },
1353 { 0x00000000, 0x00000000 } }, 1164 { AR5K_PHY_AGC, 0x00000000 },
1354 { 0x8130, 1165 { AR5K_PHY_ADC_CTL, 0x0000a000 },
1355 { 0x00000000, 0x00000000 } }, 1166 { 0x983c, 0x00200400 },
1356 { 0x8134, 1167 { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
1357 { 0x00000000, 0x00000000 } }, 1168 { AR5K_PHY_SCR, 0x0000001f },
1358 { 0x8138, 1169 { AR5K_PHY_SLMT, 0x00000080 },
1359 { 0x00000000, 0x00000000 } }, 1170 { AR5K_PHY_SCAL, 0x0000000e },
1360 { 0x813c, 1171 { 0x9958, 0x00081fff },
1361 { 0x00000000, 0x00000000 } }, 1172 { AR5K_PHY_TIMING_7, 0x00000000 },
1362 { 0x8140, 1173 { AR5K_PHY_TIMING_8, 0x02800000 },
1363 { 0x800003f9, 0x800003f9 } }, 1174 { AR5K_PHY_TIMING_11, 0x00000000 },
1364 { 0x8144, 1175 { 0x99dc, 0xfebadbe8 },
1365 { 0x00000000, 0x00000000 } }, 1176 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
1366 { AR5K_PHY_AGC, 1177 { 0x99e4, 0xaaaaaaaa },
1367 { 0x00000000, 0x00000000 } }, 1178 { 0x99e8, 0x3c466478 },
1368 { AR5K_PHY(11), 1179 { 0x99ec, 0x000000aa },
1369 { 0x0000a000, 0x0000a000 } }, 1180 { AR5K_PHY_SCLOCK, 0x0000000c },
1370 { AR5K_PHY(15), 1181 { AR5K_PHY_SDELAY, 0x000000ff },
1371 { 0x00200400, 0x00200400 } }, 1182 { AR5K_PHY_SPENDING, 0x00000014 },
1372 { AR5K_PHY(19), 1183 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
1373 { 0x1284233c, 0x1284233c } }, 1184 { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
1374 { AR5K_PHY_SCR, 1185 { AR5K_PHY_TXPOWER_RATE4, 0x20202020 },
1375 { 0x0000001f, 0x0000001f } }, 1186 { 0xa23c, 0x93c889af },
1376 { AR5K_PHY_SLMT, 1187 { AR5K_PHY_FAST_ADC, 0x00000001 },
1377 { 0x00000080, 0x00000080 } }, 1188 { 0xa250, 0x0000a000 },
1378 { AR5K_PHY_SCAL, 1189 { AR5K_PHY_BLUETOOTH, 0x00000000 },
1379 { 0x0000000e, 0x0000000e } }, 1190 { AR5K_PHY_TPC_RG1, 0x0cc75380 },
1380 { AR5K_PHY(86), 1191 { 0xa25c, 0x0f0f0f01 },
1381 { 0x00081fff, 0x00081fff } }, 1192 { 0xa260, 0x5f690f01 },
1382 { AR5K_PHY(96), 1193 { 0xa264, 0x00418a11 },
1383 { 0x00000000, 0x00000000 } }, 1194 { 0xa268, 0x00000000 },
1384 { AR5K_PHY(97), 1195 { AR5K_PHY_TPC_RG5, 0x0c30c166 },
1385 { 0x02800000, 0x02800000 } }, 1196 { 0xa270, 0x00820820 },
1386 { AR5K_PHY(104), 1197 { 0xa274, 0x081a3caa },
1387 { 0x00000000, 0x00000000 } }, 1198 { 0xa278, 0x1ce739ce },
1388 { AR5K_PHY(119), 1199 { 0xa27c, 0x051701ce },
1389 { 0xfebadbe8, 0xfebadbe8 } }, 1200 { 0xa300, 0x16010000 },
1390 { AR5K_PHY(120), 1201 { 0xa304, 0x2c032402 },
1391 { 0x00000000, 0x00000000 } }, 1202 { 0xa308, 0x48433e42 },
1392 { AR5K_PHY(121), 1203 { 0xa30c, 0x5a0f500b },
1393 { 0xaaaaaaaa, 0xaaaaaaaa } }, 1204 { 0xa310, 0x6c4b624a },
1394 { AR5K_PHY(122), 1205 { 0xa314, 0x7e8b748a },
1395 { 0x3c466478, 0x3c466478 } }, 1206 { 0xa318, 0x96cf8ccb },
1396 { AR5K_PHY(123), 1207 { 0xa31c, 0xa34f9d0f },
1397 { 0x000000aa, 0x000000aa } }, 1208 { 0xa320, 0xa7cfa58f },
1398 { AR5K_PHY_SCLOCK, 1209 { 0xa348, 0x3fffffff },
1399 { 0x0000000c, 0x0000000c } }, 1210 { 0xa34c, 0x3fffffff },
1400 { AR5K_PHY_SDELAY, 1211 { 0xa350, 0x3fffffff },
1401 { 0x000000ff, 0x000000ff } }, 1212 { 0xa354, 0x0003ffff },
1402 { AR5K_PHY_SPENDING, 1213 { 0xa358, 0x79a8aa1f },
1403 { 0x00000014, 0x00000014 } }, 1214 { 0xa35c, 0x066c420f },
1404 { 0xa228, 1215 { 0xa360, 0x0f282207 },
1405 { 0x000009b5, 0x000009b5 } }, 1216 { 0xa364, 0x17601685 },
1406 { AR5K_PHY_TXPOWER_RATE3, 1217 { 0xa368, 0x1f801104 },
1407 { 0x20202020, 0x20202020 } }, 1218 { 0xa36c, 0x37a00c03 },
1408 { AR5K_PHY_TXPOWER_RATE4, 1219 { 0xa370, 0x3fc40883 },
1409 { 0x20202020, 0x20202020 } }, 1220 { 0xa374, 0x57c00803 },
1410 { 0xa23c, 1221 { 0xa378, 0x5fd80682 },
1411 { 0x93c889af, 0x93c889af } }, 1222 { 0xa37c, 0x7fe00482 },
1412 { 0xa24c, 1223 { 0xa380, 0x7f3c7bba },
1413 { 0x00000001, 0x00000001 } }, 1224 { 0xa384, 0xf3307ff0 },
1414 { 0xa250,
1415 { 0x0000a000, 0x0000a000 } },
1416 { 0xa254,
1417 { 0x00000000, 0x00000000 } },
1418 { 0xa258,
1419 { 0x0cc75380, 0x0cc75380 } },
1420 { 0xa25c,
1421 { 0x0f0f0f01, 0x0f0f0f01 } },
1422 { 0xa260,
1423 { 0x5f690f01, 0x5f690f01 } },
1424 { 0xa264,
1425 { 0x00418a11, 0x00418a11 } },
1426 { 0xa268,
1427 { 0x00000000, 0x00000000 } },
1428 { 0xa26c,
1429 { 0x0c30c166, 0x0c30c166 } },
1430 { 0xa270,
1431 { 0x00820820, 0x00820820 } },
1432 { 0xa274,
1433 { 0x081a3caa, 0x081a3caa } },
1434 { 0xa278,
1435 { 0x1ce739ce, 0x1ce739ce } },
1436 { 0xa27c,
1437 { 0x051701ce, 0x051701ce } },
1438 { 0xa300,
1439 { 0x16010000, 0x16010000 } },
1440 { 0xa304,
1441 { 0x2c032402, 0x2c032402 } },
1442 { 0xa308,
1443 { 0x48433e42, 0x48433e42 } },
1444 { 0xa30c,
1445 { 0x5a0f500b, 0x5a0f500b } },
1446 { 0xa310,
1447 { 0x6c4b624a, 0x6c4b624a } },
1448 { 0xa314,
1449 { 0x7e8b748a, 0x7e8b748a } },
1450 { 0xa318,
1451 { 0x96cf8ccb, 0x96cf8ccb } },
1452 { 0xa31c,
1453 { 0xa34f9d0f, 0xa34f9d0f } },
1454 { 0xa320,
1455 { 0xa7cfa58f, 0xa7cfa58f } },
1456 { 0xa348,
1457 { 0x3fffffff, 0x3fffffff } },
1458 { 0xa34c,
1459 { 0x3fffffff, 0x3fffffff } },
1460 { 0xa350,
1461 { 0x3fffffff, 0x3fffffff } },
1462 { 0xa354,
1463 { 0x0003ffff, 0x0003ffff } },
1464 { 0xa358,
1465 { 0x79a8aa1f, 0x79a8aa1f } },
1466 { 0xa35c,
1467 { 0x066c420f, 0x066c420f } },
1468 { 0xa360,
1469 { 0x0f282207, 0x0f282207 } },
1470 { 0xa364,
1471 { 0x17601685, 0x17601685 } },
1472 { 0xa368,
1473 { 0x1f801104, 0x1f801104 } },
1474 { 0xa36c,
1475 { 0x37a00c03, 0x37a00c03 } },
1476 { 0xa370,
1477 { 0x3fc40883, 0x3fc40883 } },
1478 { 0xa374,
1479 { 0x57c00803, 0x57c00803 } },
1480 { 0xa378,
1481 { 0x5fd80682, 0x5fd80682 } },
1482 { 0xa37c,
1483 { 0x7fe00482, 0x7fe00482 } },
1484 { 0xa380,
1485 { 0x7f3c7bba, 0x7f3c7bba } },
1486 { 0xa384,
1487 { 0xf3307ff0, 0xf3307ff0 } },
1488}; 1225};
1489 1226
1490/* 1227/*
@@ -1560,7 +1297,7 @@ static const struct ath5k_ini rf5111_ini_bbgain[] = {
1560 { AR5K_BB_GAIN(63), 0x00000016 }, 1297 { AR5K_BB_GAIN(63), 0x00000016 },
1561}; 1298};
1562 1299
1563/* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414) */ 1300/* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */
1564static const struct ath5k_ini rf5112_ini_bbgain[] = { 1301static const struct ath5k_ini rf5112_ini_bbgain[] = {
1565 { AR5K_BB_GAIN(0), 0x00000000 }, 1302 { AR5K_BB_GAIN(0), 0x00000000 },
1566 { AR5K_BB_GAIN(1), 0x00000001 }, 1303 { AR5K_BB_GAIN(1), 0x00000001 },
@@ -1691,87 +1428,97 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
1691 /* 1428 /*
1692 * Write initial settings common for all modes 1429 * Write initial settings common for all modes
1693 */ 1430 */
1694 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini), 1431 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
1695 ar5212_ini, change_channel); 1432 ar5212_ini_common_start, change_channel);
1696 1433
1697 /* Second set of mode-specific settings */ 1434 /* Second set of mode-specific settings */
1698 if (ah->ah_radio == AR5K_RF5111) { 1435 switch (ah->ah_radio) {
1436 case AR5K_RF5111:
1699 1437
1700 ath5k_hw_ini_mode_registers(ah, 1438 ath5k_hw_ini_mode_registers(ah,
1701 ARRAY_SIZE(ar5212_rf5111_ini_mode_end), 1439 ARRAY_SIZE(rf5111_ini_mode_end),
1702 ar5212_rf5111_ini_mode_end, mode); 1440 rf5111_ini_mode_end, mode);
1441
1442 ath5k_hw_ini_registers(ah,
1443 ARRAY_SIZE(rf5111_ini_common_end),
1444 rf5111_ini_common_end, change_channel);
1703 1445
1704 /* Baseband gain table */ 1446 /* Baseband gain table */
1705 ath5k_hw_ini_registers(ah, 1447 ath5k_hw_ini_registers(ah,
1706 ARRAY_SIZE(rf5111_ini_bbgain), 1448 ARRAY_SIZE(rf5111_ini_bbgain),
1707 rf5111_ini_bbgain, change_channel); 1449 rf5111_ini_bbgain, change_channel);
1708 1450
1709 } else if (ah->ah_radio == AR5K_RF5112) { 1451 break;
1452 case AR5K_RF5112:
1710 1453
1711 ath5k_hw_ini_mode_registers(ah, 1454 ath5k_hw_ini_mode_registers(ah,
1712 ARRAY_SIZE(ar5212_rf5112_ini_mode_end), 1455 ARRAY_SIZE(rf5112_ini_mode_end),
1713 ar5212_rf5112_ini_mode_end, mode); 1456 rf5112_ini_mode_end, mode);
1457
1458 ath5k_hw_ini_registers(ah,
1459 ARRAY_SIZE(rf5112_ini_common_end),
1460 rf5112_ini_common_end, change_channel);
1714 1461
1715 ath5k_hw_ini_registers(ah, 1462 ath5k_hw_ini_registers(ah,
1716 ARRAY_SIZE(rf5112_ini_bbgain), 1463 ARRAY_SIZE(rf5112_ini_bbgain),
1717 rf5112_ini_bbgain, change_channel); 1464 rf5112_ini_bbgain, change_channel);
1718 1465
1719 } else if (ah->ah_radio == AR5K_RF5413) { 1466 break;
1467 case AR5K_RF5413:
1720 1468
1721 ath5k_hw_ini_mode_registers(ah, 1469 ath5k_hw_ini_mode_registers(ah,
1722 ARRAY_SIZE(rf5413_ini_mode_end), 1470 ARRAY_SIZE(rf5413_ini_mode_end),
1723 rf5413_ini_mode_end, mode); 1471 rf5413_ini_mode_end, mode);
1724 1472
1725 ath5k_hw_ini_registers(ah, 1473 ath5k_hw_ini_registers(ah,
1474 ARRAY_SIZE(rf5413_ini_common_end),
1475 rf5413_ini_common_end, change_channel);
1476
1477 ath5k_hw_ini_registers(ah,
1726 ARRAY_SIZE(rf5112_ini_bbgain), 1478 ARRAY_SIZE(rf5112_ini_bbgain),
1727 rf5112_ini_bbgain, change_channel); 1479 rf5112_ini_bbgain, change_channel);
1728 1480
1729 } else if (ah->ah_radio == AR5K_RF2413) { 1481 break;
1730 1482 case AR5K_RF2316:
1731 if (mode < 2) { 1483 case AR5K_RF2413:
1732 ATH5K_ERR(ah->ah_sc,
1733 "unsupported channel mode: %d\n", mode);
1734 return -EINVAL;
1735 }
1736 mode = mode - 2;
1737
1738 /* Override a setting from ar5212_ini */
1739 ath5k_hw_reg_write(ah, 0x018830c6, AR5K_PHY(648));
1740 1484
1741 ath5k_hw_ini_mode_registers(ah, 1485 ath5k_hw_ini_mode_registers(ah,
1742 ARRAY_SIZE(rf2413_ini_mode_end), 1486 ARRAY_SIZE(rf2413_ini_mode_end),
1743 rf2413_ini_mode_end, mode); 1487 rf2413_ini_mode_end, mode);
1744 1488
1745 /* Baseband gain table */
1746 ath5k_hw_ini_registers(ah, 1489 ath5k_hw_ini_registers(ah,
1747 ARRAY_SIZE(rf5112_ini_bbgain), 1490 ARRAY_SIZE(rf2413_ini_common_end),
1748 rf5112_ini_bbgain, change_channel); 1491 rf2413_ini_common_end, change_channel);
1749
1750 } else if (ah->ah_radio == AR5K_RF2425) {
1751 1492
1752 if (mode < 2) { 1493 /* Override settings from rf2413_ini_common_end */
1753 ATH5K_ERR(ah->ah_sc, 1494 if (ah->ah_radio == AR5K_RF2316) {
1754 "unsupported channel mode: %d\n", mode); 1495 ath5k_hw_reg_write(ah, 0x00004000,
1755 return -EINVAL; 1496 AR5K_PHY_AGC);
1497 ath5k_hw_reg_write(ah, 0x081b7caa,
1498 0xa274);
1756 } 1499 }
1757 1500
1758 /* Map b to g */ 1501 ath5k_hw_ini_registers(ah,
1759 if (mode == 2) 1502 ARRAY_SIZE(rf5112_ini_bbgain),
1760 mode = 0; 1503 rf5112_ini_bbgain, change_channel);
1761 else 1504 break;
1762 mode = mode - 3; 1505 case AR5K_RF2317:
1763 1506 case AR5K_RF2425:
1764 /* Override a setting from ar5212_ini */
1765 ath5k_hw_reg_write(ah, 0x018830c6, AR5K_PHY(648));
1766 1507
1767 ath5k_hw_ini_mode_registers(ah, 1508 ath5k_hw_ini_mode_registers(ah,
1768 ARRAY_SIZE(rf2425_ini_mode_end), 1509 ARRAY_SIZE(rf2425_ini_mode_end),
1769 rf2425_ini_mode_end, mode); 1510 rf2425_ini_mode_end, mode);
1770 1511
1771 /* Baseband gain table */ 1512 ath5k_hw_ini_registers(ah,
1513 ARRAY_SIZE(rf2413_ini_common_end),
1514 rf2413_ini_common_end, change_channel);
1515
1772 ath5k_hw_ini_registers(ah, 1516 ath5k_hw_ini_registers(ah,
1773 ARRAY_SIZE(rf5112_ini_bbgain), 1517 ARRAY_SIZE(rf5112_ini_bbgain),
1774 rf5112_ini_bbgain, change_channel); 1518 rf5112_ini_bbgain, change_channel);
1519 break;
1520 default:
1521 return -EINVAL;
1775 1522
1776 } 1523 }
1777 1524
diff --git a/drivers/net/wireless/ath5k/reg.h b/drivers/net/wireless/ath5k/reg.h
index 9aa22ef84101..84f4669278a7 100644
--- a/drivers/net/wireless/ath5k/reg.h
+++ b/drivers/net/wireless/ath5k/reg.h
@@ -811,6 +811,8 @@
811 811
812/* 812/*
813 * DCU transmit filter table 0 (32 entries) 813 * DCU transmit filter table 0 (32 entries)
814 * each entry contains a 32bit slice of the
815 * 128bit tx filter for each DCU (4 slices per DCU)
814 */ 816 */
815#define AR5K_DCU_TX_FILTER_0_BASE 0x1038 817#define AR5K_DCU_TX_FILTER_0_BASE 0x1038
816#define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64)) 818#define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
@@ -819,7 +821,7 @@
819 * DCU transmit filter table 1 (16 entries) 821 * DCU transmit filter table 1 (16 entries)
820 */ 822 */
821#define AR5K_DCU_TX_FILTER_1_BASE 0x103c 823#define AR5K_DCU_TX_FILTER_1_BASE 0x103c
822#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + ((_n - 32) * 64)) 824#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
823 825
824/* 826/*
825 * DCU clear transmit filter register 827 * DCU clear transmit filter register
@@ -1447,7 +1449,7 @@
1447 AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) 1449 AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)
1448 1450
1449/* 1451/*
1450 * Last beacon timestamp register 1452 * Last beacon timestamp register (Read Only)
1451 */ 1453 */
1452#define AR5K_LAST_TSTP 0x8080 1454#define AR5K_LAST_TSTP 0x8080
1453 1455
@@ -2219,9 +2221,7 @@
2219#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */ 2221#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */
2220 2222
2221/* 2223/*
2222 * PHY PAPD probe register [5111+ (?)] 2224 * PHY PAPD probe register [5111+]
2223 * Is this only present in 5212 ?
2224 * Because it's always 0 in 5211 initialization code
2225 */ 2225 */
2226#define AR5K_PHY_PAPD_PROBE 0x9930 2226#define AR5K_PHY_PAPD_PROBE 0x9930
2227#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001 2227#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001
@@ -2363,21 +2363,21 @@
2363#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff 2363#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff
2364#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0 2364#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0
2365 2365
2366#define AR_PHY_TIMING_9 0x9998 2366#define AR5K_PHY_TIMING_9 0x9998
2367#define AR_PHY_TIMING_10 0x999c 2367#define AR5K_PHY_TIMING_10 0x999c
2368#define AR_PHY_TIMING_10_PILOT_MASK_2 0x000fffff 2368#define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
2369#define AR_PHY_TIMING_10_PILOT_MASK_2_S 0 2369#define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0
2370 2370
2371/* 2371/*
2372 * Spur mitigation control 2372 * Spur mitigation control
2373 */ 2373 */
2374#define AR_PHY_TIMING_11 0x99a0 /* Register address */ 2374#define AR5K_PHY_TIMING_11 0x99a0 /* Register address */
2375#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */ 2375#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */
2376#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0 2376#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
2377#define AR_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */ 2377#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */
2378#define AR_PHY_TIMING_11_SPUR_FREQ_SD_S 20 2378#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20
2379#define AR_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */ 2379#define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */
2380#define AR_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */ 2380#define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */
2381 2381
2382/* 2382/*
2383 * Gain tables 2383 * Gain tables
@@ -2481,11 +2481,7 @@
2481/* 2481/*
2482 * PHY PCDAC TX power table 2482 * PHY PCDAC TX power table
2483 */ 2483 */
2484#define AR5K_PHY_PCDAC_TXPOWER_BASE_5211 0xa180 2484#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180
2485#define AR5K_PHY_PCDAC_TXPOWER_BASE_2413 0xa280
2486#define AR5K_PHY_PCDAC_TXPOWER_BASE (ah->ah_radio >= AR5K_RF2413 ? \
2487 AR5K_PHY_PCDAC_TXPOWER_BASE_2413 :\
2488 AR5K_PHY_PCDAC_TXPOWER_BASE_5211)
2489#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) 2485#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))
2490 2486
2491/* 2487/*
@@ -2566,3 +2562,9 @@
2566#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16 2562#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16
2567#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000 2563#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
2568#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22 2564#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
2565
2566/*
2567 * PHY PDADC Tx power table
2568 */
2569#define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280
2570#define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
diff --git a/drivers/net/wireless/ath5k/reset.c b/drivers/net/wireless/ath5k/reset.c
index 40cf4c7b63b2..579c64ce6108 100644
--- a/drivers/net/wireless/ath5k/reset.c
+++ b/drivers/net/wireless/ath5k/reset.c
@@ -457,15 +457,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
457 * 5210 only comes with RF5110 457 * 5210 only comes with RF5110
458 */ 458 */
459 if (ah->ah_version != AR5K_AR5210) { 459 if (ah->ah_version != AR5K_AR5210) {
460 if (ah->ah_radio != AR5K_RF5111 &&
461 ah->ah_radio != AR5K_RF5112 &&
462 ah->ah_radio != AR5K_RF5413 &&
463 ah->ah_radio != AR5K_RF2413 &&
464 ah->ah_radio != AR5K_RF2425) {
465 ATH5K_ERR(ah->ah_sc,
466 "invalid phy radio: %u\n", ah->ah_radio);
467 return -EINVAL;
468 }
469 460
470 switch (channel->hw_value & CHANNEL_MODES) { 461 switch (channel->hw_value & CHANNEL_MODES) {
471 case CHANNEL_A: 462 case CHANNEL_A:
@@ -510,11 +501,11 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
510 return -EINVAL; 501 return -EINVAL;
511 } 502 }
512 503
513 /* PHY access enable */
514 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
515
516 } 504 }
517 505
506 /* PHY access enable */
507 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
508
518 ret = ath5k_hw_write_initvals(ah, mode, change_channel); 509 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
519 if (ret) 510 if (ret)
520 return ret; 511 return ret;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 16:22:32 -0500