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authorGabor Juhos <juhosg@openwrt.org>2013-04-05 02:27:03 -0400
committerJohn W. Linville <linville@tuxdriver.com>2013-04-10 14:10:32 -0400
commit1d6205d0da456065a90d16017fd279d86bf33731 (patch)
tree9d7392a31806cc64ff29c582c4f6e33a4538835e /drivers/net/wireless
parentc517123a0ee98c9d41d09b1984cafce176d5858f (diff)
rt2x00: rt61pci: use the rt2x00mmio_* routines
Use the recently introduced rt2x00mmio_* routines instead of the rt2x00pci_* variants. The patch contains no functional changes. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: Helmut Schaa <helmut.schaa@googlemail.com> Acked-by: Gertjan van Wingerde <gwingerde@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c515
1 files changed, 259 insertions, 256 deletions
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 9d630b4ee3e5..fc99258ae777 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -58,12 +58,12 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
58 * and we will print an error. 58 * and we will print an error.
59 */ 59 */
60#define WAIT_FOR_BBP(__dev, __reg) \ 60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg)) 61 rt2x00mmio_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
62#define WAIT_FOR_RF(__dev, __reg) \ 62#define WAIT_FOR_RF(__dev, __reg) \
63 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg)) 63 rt2x00mmio_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
64#define WAIT_FOR_MCU(__dev, __reg) \ 64#define WAIT_FOR_MCU(__dev, __reg) \
65 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 65 rt2x00mmio_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg)) 66 H2M_MAILBOX_CSR_OWNER, (__reg))
67 67
68static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, 68static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
69 const unsigned int word, const u8 value) 69 const unsigned int word, const u8 value)
@@ -83,7 +83,7 @@ static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
83 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); 83 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
84 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0); 84 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
85 85
86 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg); 86 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
87 } 87 }
88 88
89 mutex_unlock(&rt2x00dev->csr_mutex); 89 mutex_unlock(&rt2x00dev->csr_mutex);
@@ -110,7 +110,7 @@ static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
110 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); 110 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
111 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1); 111 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
112 112
113 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg); 113 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
114 114
115 WAIT_FOR_BBP(rt2x00dev, &reg); 115 WAIT_FOR_BBP(rt2x00dev, &reg);
116 } 116 }
@@ -138,7 +138,7 @@ static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
138 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0); 138 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
139 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1); 139 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
140 140
141 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg); 141 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg);
142 rt2x00_rf_write(rt2x00dev, word, value); 142 rt2x00_rf_write(rt2x00dev, word, value);
143 } 143 }
144 144
@@ -162,12 +162,12 @@ static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
162 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token); 162 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
163 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0); 163 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
164 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1); 164 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
165 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); 165 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
166 166
167 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg); 167 rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
168 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command); 168 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
169 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1); 169 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
170 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg); 170 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg);
171 } 171 }
172 172
173 mutex_unlock(&rt2x00dev->csr_mutex); 173 mutex_unlock(&rt2x00dev->csr_mutex);
@@ -179,7 +179,7 @@ static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
179 struct rt2x00_dev *rt2x00dev = eeprom->data; 179 struct rt2x00_dev *rt2x00dev = eeprom->data;
180 u32 reg; 180 u32 reg;
181 181
182 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 182 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
183 183
184 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); 184 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
185 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); 185 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
@@ -201,15 +201,15 @@ static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
201 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT, 201 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
202 !!eeprom->reg_chip_select); 202 !!eeprom->reg_chip_select);
203 203
204 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg); 204 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
205} 205}
206 206
207#ifdef CONFIG_RT2X00_LIB_DEBUGFS 207#ifdef CONFIG_RT2X00_LIB_DEBUGFS
208static const struct rt2x00debug rt61pci_rt2x00debug = { 208static const struct rt2x00debug rt61pci_rt2x00debug = {
209 .owner = THIS_MODULE, 209 .owner = THIS_MODULE,
210 .csr = { 210 .csr = {
211 .read = rt2x00pci_register_read, 211 .read = rt2x00mmio_register_read,
212 .write = rt2x00pci_register_write, 212 .write = rt2x00mmio_register_write,
213 .flags = RT2X00DEBUGFS_OFFSET, 213 .flags = RT2X00DEBUGFS_OFFSET,
214 .word_base = CSR_REG_BASE, 214 .word_base = CSR_REG_BASE,
215 .word_size = sizeof(u32), 215 .word_size = sizeof(u32),
@@ -243,7 +243,7 @@ static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
243{ 243{
244 u32 reg; 244 u32 reg;
245 245
246 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg); 246 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
247 return rt2x00_get_field32(reg, MAC_CSR13_VAL5); 247 return rt2x00_get_field32(reg, MAC_CSR13_VAL5);
248} 248}
249 249
@@ -294,10 +294,10 @@ static int rt61pci_blink_set(struct led_classdev *led_cdev,
294 container_of(led_cdev, struct rt2x00_led, led_dev); 294 container_of(led_cdev, struct rt2x00_led, led_dev);
295 u32 reg; 295 u32 reg;
296 296
297 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg); 297 rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, &reg);
298 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on); 298 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
299 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off); 299 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
300 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg); 300 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg);
301 301
302 return 0; 302 return 0;
303} 303}
@@ -339,7 +339,7 @@ static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
339 */ 339 */
340 mask = (0xf << crypto->bssidx); 340 mask = (0xf << crypto->bssidx);
341 341
342 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg); 342 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg);
343 reg &= mask; 343 reg &= mask;
344 344
345 if (reg && reg == mask) 345 if (reg && reg == mask)
@@ -358,8 +358,8 @@ static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
358 sizeof(key_entry.rx_mic)); 358 sizeof(key_entry.rx_mic));
359 359
360 reg = SHARED_KEY_ENTRY(key->hw_key_idx); 360 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
361 rt2x00pci_register_multiwrite(rt2x00dev, reg, 361 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
362 &key_entry, sizeof(key_entry)); 362 &key_entry, sizeof(key_entry));
363 363
364 /* 364 /*
365 * The cipher types are stored over 2 registers. 365 * The cipher types are stored over 2 registers.
@@ -372,16 +372,16 @@ static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
372 field.bit_offset = (3 * key->hw_key_idx); 372 field.bit_offset = (3 * key->hw_key_idx);
373 field.bit_mask = 0x7 << field.bit_offset; 373 field.bit_mask = 0x7 << field.bit_offset;
374 374
375 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg); 375 rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, &reg);
376 rt2x00_set_field32(&reg, field, crypto->cipher); 376 rt2x00_set_field32(&reg, field, crypto->cipher);
377 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg); 377 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg);
378 } else { 378 } else {
379 field.bit_offset = (3 * (key->hw_key_idx - 8)); 379 field.bit_offset = (3 * (key->hw_key_idx - 8));
380 field.bit_mask = 0x7 << field.bit_offset; 380 field.bit_mask = 0x7 << field.bit_offset;
381 381
382 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg); 382 rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, &reg);
383 rt2x00_set_field32(&reg, field, crypto->cipher); 383 rt2x00_set_field32(&reg, field, crypto->cipher);
384 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg); 384 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg);
385 } 385 }
386 386
387 /* 387 /*
@@ -404,12 +404,12 @@ static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
404 */ 404 */
405 mask = 1 << key->hw_key_idx; 405 mask = 1 << key->hw_key_idx;
406 406
407 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg); 407 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg);
408 if (crypto->cmd == SET_KEY) 408 if (crypto->cmd == SET_KEY)
409 reg |= mask; 409 reg |= mask;
410 else if (crypto->cmd == DISABLE_KEY) 410 else if (crypto->cmd == DISABLE_KEY)
411 reg &= ~mask; 411 reg &= ~mask;
412 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg); 412 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg);
413 413
414 return 0; 414 return 0;
415} 415}
@@ -433,10 +433,10 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
433 * When both registers are full, we drop the key. 433 * When both registers are full, we drop the key.
434 * Otherwise, we use the first invalid entry. 434 * Otherwise, we use the first invalid entry.
435 */ 435 */
436 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg); 436 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg);
437 if (reg && reg == ~0) { 437 if (reg && reg == ~0) {
438 key->hw_key_idx = 32; 438 key->hw_key_idx = 32;
439 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg); 439 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg);
440 if (reg && reg == ~0) 440 if (reg && reg == ~0)
441 return -ENOSPC; 441 return -ENOSPC;
442 } 442 }
@@ -458,21 +458,21 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
458 addr_entry.cipher = crypto->cipher; 458 addr_entry.cipher = crypto->cipher;
459 459
460 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 460 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
461 rt2x00pci_register_multiwrite(rt2x00dev, reg, 461 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
462 &key_entry, sizeof(key_entry)); 462 &key_entry, sizeof(key_entry));
463 463
464 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); 464 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
465 rt2x00pci_register_multiwrite(rt2x00dev, reg, 465 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
466 &addr_entry, sizeof(addr_entry)); 466 &addr_entry, sizeof(addr_entry));
467 467
468 /* 468 /*
469 * Enable pairwise lookup table for given BSS idx. 469 * Enable pairwise lookup table for given BSS idx.
470 * Without this, received frames will not be decrypted 470 * Without this, received frames will not be decrypted
471 * by the hardware. 471 * by the hardware.
472 */ 472 */
473 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg); 473 rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, &reg);
474 reg |= (1 << crypto->bssidx); 474 reg |= (1 << crypto->bssidx);
475 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg); 475 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg);
476 476
477 /* 477 /*
478 * The driver does not support the IV/EIV generation 478 * The driver does not support the IV/EIV generation
@@ -495,21 +495,21 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
495 if (key->hw_key_idx < 32) { 495 if (key->hw_key_idx < 32) {
496 mask = 1 << key->hw_key_idx; 496 mask = 1 << key->hw_key_idx;
497 497
498 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg); 498 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg);
499 if (crypto->cmd == SET_KEY) 499 if (crypto->cmd == SET_KEY)
500 reg |= mask; 500 reg |= mask;
501 else if (crypto->cmd == DISABLE_KEY) 501 else if (crypto->cmd == DISABLE_KEY)
502 reg &= ~mask; 502 reg &= ~mask;
503 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg); 503 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg);
504 } else { 504 } else {
505 mask = 1 << (key->hw_key_idx - 32); 505 mask = 1 << (key->hw_key_idx - 32);
506 506
507 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg); 507 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg);
508 if (crypto->cmd == SET_KEY) 508 if (crypto->cmd == SET_KEY)
509 reg |= mask; 509 reg |= mask;
510 else if (crypto->cmd == DISABLE_KEY) 510 else if (crypto->cmd == DISABLE_KEY)
511 reg &= ~mask; 511 reg &= ~mask;
512 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg); 512 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg);
513 } 513 }
514 514
515 return 0; 515 return 0;
@@ -526,7 +526,7 @@ static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
526 * and broadcast frames will always be accepted since 526 * and broadcast frames will always be accepted since
527 * there is no filter for it at this time. 527 * there is no filter for it at this time.
528 */ 528 */
529 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg); 529 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
530 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC, 530 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
531 !(filter_flags & FIF_FCSFAIL)); 531 !(filter_flags & FIF_FCSFAIL));
532 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, 532 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
@@ -544,7 +544,7 @@ static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
544 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0); 544 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
545 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 545 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
546 !(filter_flags & FIF_CONTROL)); 546 !(filter_flags & FIF_CONTROL));
547 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 547 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
548} 548}
549 549
550static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev, 550static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
@@ -558,9 +558,9 @@ static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
558 /* 558 /*
559 * Enable synchronisation. 559 * Enable synchronisation.
560 */ 560 */
561 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 561 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
562 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync); 562 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
563 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 563 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
564 } 564 }
565 565
566 if (flags & CONFIG_UPDATE_MAC) { 566 if (flags & CONFIG_UPDATE_MAC) {
@@ -568,8 +568,8 @@ static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
568 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); 568 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
569 conf->mac[1] = cpu_to_le32(reg); 569 conf->mac[1] = cpu_to_le32(reg);
570 570
571 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, 571 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR2,
572 conf->mac, sizeof(conf->mac)); 572 conf->mac, sizeof(conf->mac));
573 } 573 }
574 574
575 if (flags & CONFIG_UPDATE_BSSID) { 575 if (flags & CONFIG_UPDATE_BSSID) {
@@ -577,8 +577,9 @@ static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
577 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3); 577 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
578 conf->bssid[1] = cpu_to_le32(reg); 578 conf->bssid[1] = cpu_to_le32(reg);
579 579
580 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, 580 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR4,
581 conf->bssid, sizeof(conf->bssid)); 581 conf->bssid,
582 sizeof(conf->bssid));
582 } 583 }
583} 584}
584 585
@@ -588,40 +589,40 @@ static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
588{ 589{
589 u32 reg; 590 u32 reg;
590 591
591 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg); 592 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
592 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); 593 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
593 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); 594 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
594 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 595 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
595 596
596 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 597 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
597 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg); 598 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg);
598 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1); 599 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
599 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 600 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
600 !!erp->short_preamble); 601 !!erp->short_preamble);
601 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); 602 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
602 } 603 }
603 604
604 if (changed & BSS_CHANGED_BASIC_RATES) 605 if (changed & BSS_CHANGED_BASIC_RATES)
605 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, 606 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5,
606 erp->basic_rates); 607 erp->basic_rates);
607 608
608 if (changed & BSS_CHANGED_BEACON_INT) { 609 if (changed & BSS_CHANGED_BEACON_INT) {
609 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 610 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
610 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 611 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
611 erp->beacon_int * 16); 612 erp->beacon_int * 16);
612 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 613 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
613 } 614 }
614 615
615 if (changed & BSS_CHANGED_ERP_SLOT) { 616 if (changed & BSS_CHANGED_ERP_SLOT) {
616 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg); 617 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg);
617 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time); 618 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
618 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); 619 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
619 620
620 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg); 621 rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, &reg);
621 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs); 622 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
622 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); 623 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
623 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs); 624 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
624 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg); 625 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg);
625 } 626 }
626} 627}
627 628
@@ -714,7 +715,7 @@ static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
714{ 715{
715 u32 reg; 716 u32 reg;
716 717
717 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg); 718 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
718 719
719 rt2x00_set_field32(&reg, MAC_CSR13_DIR4, 0); 720 rt2x00_set_field32(&reg, MAC_CSR13_DIR4, 0);
720 rt2x00_set_field32(&reg, MAC_CSR13_VAL4, p1); 721 rt2x00_set_field32(&reg, MAC_CSR13_VAL4, p1);
@@ -722,7 +723,7 @@ static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
722 rt2x00_set_field32(&reg, MAC_CSR13_DIR3, 0); 723 rt2x00_set_field32(&reg, MAC_CSR13_DIR3, 0);
723 rt2x00_set_field32(&reg, MAC_CSR13_VAL3, !p2); 724 rt2x00_set_field32(&reg, MAC_CSR13_VAL3, !p2);
724 725
725 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg); 726 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
726} 727}
727 728
728static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev, 729static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
@@ -821,14 +822,14 @@ static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
821 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) 822 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
822 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); 823 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
823 824
824 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg); 825 rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, &reg);
825 826
826 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 827 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
827 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); 828 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
828 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 829 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
829 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); 830 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
830 831
831 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg); 832 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg);
832 833
833 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) 834 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
834 rt61pci_config_antenna_5x(rt2x00dev, ant); 835 rt61pci_config_antenna_5x(rt2x00dev, ant);
@@ -928,7 +929,7 @@ static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
928{ 929{
929 u32 reg; 930 u32 reg;
930 931
931 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg); 932 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg);
932 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); 933 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
933 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); 934 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
934 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); 935 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
@@ -936,7 +937,7 @@ static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
936 libconf->conf->long_frame_max_tx_count); 937 libconf->conf->long_frame_max_tx_count);
937 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, 938 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
938 libconf->conf->short_frame_max_tx_count); 939 libconf->conf->short_frame_max_tx_count);
939 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); 940 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
940} 941}
941 942
942static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev, 943static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
@@ -948,7 +949,7 @@ static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
948 u32 reg; 949 u32 reg;
949 950
950 if (state == STATE_SLEEP) { 951 if (state == STATE_SLEEP) {
951 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg); 952 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg);
952 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 953 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
953 rt2x00dev->beacon_int - 10); 954 rt2x00dev->beacon_int - 10);
954 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 955 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
@@ -957,27 +958,29 @@ static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
957 958
958 /* We must first disable autowake before it can be enabled */ 959 /* We must first disable autowake before it can be enabled */
959 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0); 960 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
960 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg); 961 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
961 962
962 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1); 963 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
963 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg); 964 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
964 965
965 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005); 966 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
966 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c); 967 0x00000005);
967 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060); 968 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
969 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
968 970
969 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0); 971 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
970 } else { 972 } else {
971 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg); 973 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg);
972 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0); 974 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
973 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); 975 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
974 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0); 976 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
975 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0); 977 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
976 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg); 978 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
977 979
978 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); 980 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
979 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018); 981 0x00000007);
980 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020); 982 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
983 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
981 984
982 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); 985 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
983 } 986 }
@@ -1013,13 +1016,13 @@ static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1013 /* 1016 /*
1014 * Update FCS error count from register. 1017 * Update FCS error count from register.
1015 */ 1018 */
1016 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg); 1019 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg);
1017 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); 1020 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1018 1021
1019 /* 1022 /*
1020 * Update False CCA count from register. 1023 * Update False CCA count from register.
1021 */ 1024 */
1022 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg); 1025 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg);
1023 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); 1026 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1024} 1027}
1025 1028
@@ -1138,16 +1141,16 @@ static void rt61pci_start_queue(struct data_queue *queue)
1138 1141
1139 switch (queue->qid) { 1142 switch (queue->qid) {
1140 case QID_RX: 1143 case QID_RX:
1141 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg); 1144 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1142 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0); 1145 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1143 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 1146 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1144 break; 1147 break;
1145 case QID_BEACON: 1148 case QID_BEACON:
1146 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 1149 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1147 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1); 1150 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1148 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1); 1151 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1149 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 1152 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1150 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1153 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1151 break; 1154 break;
1152 default: 1155 default:
1153 break; 1156 break;
@@ -1161,24 +1164,24 @@ static void rt61pci_kick_queue(struct data_queue *queue)
1161 1164
1162 switch (queue->qid) { 1165 switch (queue->qid) {
1163 case QID_AC_VO: 1166 case QID_AC_VO:
1164 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 1167 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1165 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1); 1168 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1166 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1169 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1167 break; 1170 break;
1168 case QID_AC_VI: 1171 case QID_AC_VI:
1169 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 1172 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1170 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1); 1173 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1171 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1174 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1172 break; 1175 break;
1173 case QID_AC_BE: 1176 case QID_AC_BE:
1174 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 1177 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1175 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1); 1178 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1176 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1179 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1177 break; 1180 break;
1178 case QID_AC_BK: 1181 case QID_AC_BK:
1179 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 1182 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1180 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1); 1183 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1181 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1184 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1182 break; 1185 break;
1183 default: 1186 default:
1184 break; 1187 break;
@@ -1192,36 +1195,36 @@ static void rt61pci_stop_queue(struct data_queue *queue)
1192 1195
1193 switch (queue->qid) { 1196 switch (queue->qid) {
1194 case QID_AC_VO: 1197 case QID_AC_VO:
1195 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 1198 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1196 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1); 1199 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1197 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1200 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1198 break; 1201 break;
1199 case QID_AC_VI: 1202 case QID_AC_VI:
1200 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 1203 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1201 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1); 1204 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1202 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1205 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1203 break; 1206 break;
1204 case QID_AC_BE: 1207 case QID_AC_BE:
1205 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 1208 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1206 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1); 1209 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1207 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1210 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1208 break; 1211 break;
1209 case QID_AC_BK: 1212 case QID_AC_BK:
1210 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 1213 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1211 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1); 1214 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1212 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1215 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1213 break; 1216 break;
1214 case QID_RX: 1217 case QID_RX:
1215 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg); 1218 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1216 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1); 1219 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1217 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 1220 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1218 break; 1221 break;
1219 case QID_BEACON: 1222 case QID_BEACON:
1220 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 1223 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1221 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); 1224 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1222 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); 1225 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1223 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1226 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1224 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1227 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1225 1228
1226 /* 1229 /*
1227 * Wait for possibly running tbtt tasklets. 1230 * Wait for possibly running tbtt tasklets.
@@ -1299,7 +1302,7 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1299 * Wait for stable hardware. 1302 * Wait for stable hardware.
1300 */ 1303 */
1301 for (i = 0; i < 100; i++) { 1304 for (i = 0; i < 100; i++) {
1302 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 1305 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg);
1303 if (reg) 1306 if (reg)
1304 break; 1307 break;
1305 msleep(1); 1308 msleep(1);
@@ -1315,10 +1318,10 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1315 */ 1318 */
1316 reg = 0; 1319 reg = 0;
1317 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1); 1320 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1318 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1321 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1319 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); 1322 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1320 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 1323 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1321 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0); 1324 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1322 1325
1323 /* 1326 /*
1324 * Write firmware to device. 1327 * Write firmware to device.
@@ -1326,19 +1329,19 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1326 reg = 0; 1329 reg = 0;
1327 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1); 1330 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1328 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1); 1331 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1329 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1332 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1330 1333
1331 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 1334 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1332 data, len); 1335 data, len);
1333 1336
1334 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0); 1337 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1335 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1338 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1336 1339
1337 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0); 1340 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1338 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1341 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1339 1342
1340 for (i = 0; i < 100; i++) { 1343 for (i = 0; i < 100; i++) {
1341 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg); 1344 rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1342 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) 1345 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1343 break; 1346 break;
1344 msleep(1); 1347 msleep(1);
@@ -1360,16 +1363,16 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1360 reg = 0; 1363 reg = 0;
1361 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1); 1364 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1362 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1); 1365 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1363 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1366 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1364 1367
1365 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg); 1368 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1366 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0); 1369 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1367 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0); 1370 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1368 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1371 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1369 1372
1370 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg); 1373 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1371 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1); 1374 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1372 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1375 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1373 1376
1374 return 0; 1377 return 0;
1375} 1378}
@@ -1379,7 +1382,7 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1379 */ 1382 */
1380static bool rt61pci_get_entry_state(struct queue_entry *entry) 1383static bool rt61pci_get_entry_state(struct queue_entry *entry)
1381{ 1384{
1382 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1385 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1383 u32 word; 1386 u32 word;
1384 1387
1385 if (entry->queue->qid == QID_RX) { 1388 if (entry->queue->qid == QID_RX) {
@@ -1396,7 +1399,7 @@ static bool rt61pci_get_entry_state(struct queue_entry *entry)
1396 1399
1397static void rt61pci_clear_entry(struct queue_entry *entry) 1400static void rt61pci_clear_entry(struct queue_entry *entry)
1398{ 1401{
1399 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1402 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1400 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1403 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1401 u32 word; 1404 u32 word;
1402 1405
@@ -1419,13 +1422,13 @@ static void rt61pci_clear_entry(struct queue_entry *entry)
1419 1422
1420static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) 1423static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1421{ 1424{
1422 struct queue_entry_priv_pci *entry_priv; 1425 struct queue_entry_priv_mmio *entry_priv;
1423 u32 reg; 1426 u32 reg;
1424 1427
1425 /* 1428 /*
1426 * Initialize registers. 1429 * Initialize registers.
1427 */ 1430 */
1428 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg); 1431 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1429 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE, 1432 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1430 rt2x00dev->tx[0].limit); 1433 rt2x00dev->tx[0].limit);
1431 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE, 1434 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
@@ -1434,67 +1437,67 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1434 rt2x00dev->tx[2].limit); 1437 rt2x00dev->tx[2].limit);
1435 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE, 1438 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1436 rt2x00dev->tx[3].limit); 1439 rt2x00dev->tx[3].limit);
1437 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg); 1440 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg);
1438 1441
1439 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg); 1442 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1440 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE, 1443 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1441 rt2x00dev->tx[0].desc_size / 4); 1444 rt2x00dev->tx[0].desc_size / 4);
1442 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg); 1445 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg);
1443 1446
1444 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 1447 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1445 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg); 1448 rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1446 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, 1449 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1447 entry_priv->desc_dma); 1450 entry_priv->desc_dma);
1448 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg); 1451 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1449 1452
1450 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 1453 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1451 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg); 1454 rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1452 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, 1455 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1453 entry_priv->desc_dma); 1456 entry_priv->desc_dma);
1454 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg); 1457 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1455 1458
1456 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; 1459 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1457 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg); 1460 rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1458 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, 1461 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1459 entry_priv->desc_dma); 1462 entry_priv->desc_dma);
1460 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg); 1463 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1461 1464
1462 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; 1465 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1463 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg); 1466 rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1464 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, 1467 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1465 entry_priv->desc_dma); 1468 entry_priv->desc_dma);
1466 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg); 1469 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1467 1470
1468 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg); 1471 rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, &reg);
1469 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); 1472 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1470 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE, 1473 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1471 rt2x00dev->rx->desc_size / 4); 1474 rt2x00dev->rx->desc_size / 4);
1472 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); 1475 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1473 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg); 1476 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg);
1474 1477
1475 entry_priv = rt2x00dev->rx->entries[0].priv_data; 1478 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1476 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg); 1479 rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1477 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, 1480 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1478 entry_priv->desc_dma); 1481 entry_priv->desc_dma);
1479 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg); 1482 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg);
1480 1483
1481 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg); 1484 rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1482 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2); 1485 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1483 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2); 1486 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1484 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2); 1487 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1485 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2); 1488 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1486 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); 1489 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1487 1490
1488 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg); 1491 rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1489 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); 1492 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1490 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); 1493 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1491 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); 1494 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1492 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); 1495 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1493 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); 1496 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1494 1497
1495 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg); 1498 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1496 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1); 1499 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1497 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg); 1500 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1498 1501
1499 return 0; 1502 return 0;
1500} 1503}
@@ -1503,13 +1506,13 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1503{ 1506{
1504 u32 reg; 1507 u32 reg;
1505 1508
1506 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg); 1509 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1507 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1); 1510 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1508 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0); 1511 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1509 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0); 1512 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1510 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 1513 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1511 1514
1512 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg); 1515 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, &reg);
1513 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ 1516 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1514 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1); 1517 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1515 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ 1518 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
@@ -1518,12 +1521,12 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1518 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1); 1521 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1519 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ 1522 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1520 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1); 1523 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1521 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg); 1524 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg);
1522 1525
1523 /* 1526 /*
1524 * CCK TXD BBP registers 1527 * CCK TXD BBP registers
1525 */ 1528 */
1526 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg); 1529 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, &reg);
1527 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13); 1530 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1528 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1); 1531 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1529 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12); 1532 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
@@ -1532,76 +1535,76 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1532 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1); 1535 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1533 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10); 1536 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1534 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1); 1537 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1535 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg); 1538 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg);
1536 1539
1537 /* 1540 /*
1538 * OFDM TXD BBP registers 1541 * OFDM TXD BBP registers
1539 */ 1542 */
1540 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg); 1543 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, &reg);
1541 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7); 1544 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1542 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1); 1545 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1543 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6); 1546 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1544 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1); 1547 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1545 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5); 1548 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1546 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1); 1549 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1547 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg); 1550 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg);
1548 1551
1549 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg); 1552 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, &reg);
1550 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59); 1553 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1551 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53); 1554 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1552 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49); 1555 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1553 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46); 1556 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1554 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg); 1557 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg);
1555 1558
1556 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg); 1559 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, &reg);
1557 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44); 1560 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1558 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42); 1561 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1559 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42); 1562 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1560 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42); 1563 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1561 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg); 1564 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg);
1562 1565
1563 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 1566 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1564 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0); 1567 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1565 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); 1568 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1566 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0); 1569 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1567 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); 1570 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1568 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1571 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1569 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); 1572 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1570 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1573 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1571 1574
1572 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); 1575 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1573 1576
1574 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); 1577 rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1575 1578
1576 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg); 1579 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg);
1577 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0); 1580 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1578 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); 1581 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
1579 1582
1580 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); 1583 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1581 1584
1582 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) 1585 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1583 return -EBUSY; 1586 return -EBUSY;
1584 1587
1585 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); 1588 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1586 1589
1587 /* 1590 /*
1588 * Invalidate all Shared Keys (SEC_CSR0), 1591 * Invalidate all Shared Keys (SEC_CSR0),
1589 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) 1592 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1590 */ 1593 */
1591 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000); 1594 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1592 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000); 1595 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1593 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000); 1596 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1594 1597
1595 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); 1598 rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1596 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); 1599 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1597 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606); 1600 rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1598 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); 1601 rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1599 1602
1600 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); 1603 rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1601 1604
1602 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); 1605 rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1603 1606
1604 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); 1607 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1605 1608
1606 /* 1609 /*
1607 * Clear all beacons 1610 * Clear all beacons
@@ -1609,36 +1612,36 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1609 * the first byte since that byte contains the VALID and OWNER 1612 * the first byte since that byte contains the VALID and OWNER
1610 * bits which (when set to 0) will invalidate the entire beacon. 1613 * bits which (when set to 0) will invalidate the entire beacon.
1611 */ 1614 */
1612 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0); 1615 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1613 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0); 1616 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1614 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0); 1617 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1615 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0); 1618 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1616 1619
1617 /* 1620 /*
1618 * We must clear the error counters. 1621 * We must clear the error counters.
1619 * These registers are cleared on read, 1622 * These registers are cleared on read,
1620 * so we may pass a useless variable to store the value. 1623 * so we may pass a useless variable to store the value.
1621 */ 1624 */
1622 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg); 1625 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg);
1623 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg); 1626 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg);
1624 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg); 1627 rt2x00mmio_register_read(rt2x00dev, STA_CSR2, &reg);
1625 1628
1626 /* 1629 /*
1627 * Reset MAC and BBP registers. 1630 * Reset MAC and BBP registers.
1628 */ 1631 */
1629 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg); 1632 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1630 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1); 1633 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1631 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1); 1634 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1632 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1635 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1633 1636
1634 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg); 1637 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1635 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0); 1638 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1636 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0); 1639 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1637 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1640 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1638 1641
1639 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg); 1642 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1640 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1); 1643 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1641 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1644 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1642 1645
1643 return 0; 1646 return 0;
1644} 1647}
@@ -1722,11 +1725,11 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1722 * should clear the register to assure a clean state. 1725 * should clear the register to assure a clean state.
1723 */ 1726 */
1724 if (state == STATE_RADIO_IRQ_ON) { 1727 if (state == STATE_RADIO_IRQ_ON) {
1725 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 1728 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1726 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 1729 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1727 1730
1728 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg); 1731 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1729 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); 1732 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1730 } 1733 }
1731 1734
1732 /* 1735 /*
@@ -1735,15 +1738,15 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1735 */ 1738 */
1736 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); 1739 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1737 1740
1738 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 1741 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1739 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask); 1742 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1740 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask); 1743 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1741 rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask); 1744 rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
1742 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask); 1745 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1743 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); 1746 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1744 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 1747 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
1745 1748
1746 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg); 1749 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1747 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask); 1750 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1748 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask); 1751 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1749 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask); 1752 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
@@ -1753,7 +1756,7 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1753 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask); 1756 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1754 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask); 1757 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1755 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask); 1758 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
1756 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); 1759 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1757 1760
1758 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); 1761 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1759 1762
@@ -1783,9 +1786,9 @@ static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1783 /* 1786 /*
1784 * Enable RX. 1787 * Enable RX.
1785 */ 1788 */
1786 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg); 1789 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1787 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1); 1790 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1788 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg); 1791 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1789 1792
1790 return 0; 1793 return 0;
1791} 1794}
@@ -1795,7 +1798,7 @@ static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1795 /* 1798 /*
1796 * Disable power 1799 * Disable power
1797 */ 1800 */
1798 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818); 1801 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1799} 1802}
1800 1803
1801static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) 1804static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
@@ -1806,10 +1809,10 @@ static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1806 1809
1807 put_to_sleep = (state != STATE_AWAKE); 1810 put_to_sleep = (state != STATE_AWAKE);
1808 1811
1809 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg); 1812 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, &reg);
1810 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); 1813 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1811 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); 1814 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1812 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg); 1815 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
1813 1816
1814 /* 1817 /*
1815 * Device is not guaranteed to be in the requested state yet. 1818 * Device is not guaranteed to be in the requested state yet.
@@ -1817,11 +1820,11 @@ static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1817 * device has entered the correct state. 1820 * device has entered the correct state.
1818 */ 1821 */
1819 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1822 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1820 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg2); 1823 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, &reg2);
1821 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); 1824 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1822 if (state == !put_to_sleep) 1825 if (state == !put_to_sleep)
1823 return 0; 1826 return 0;
1824 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg); 1827 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
1825 msleep(10); 1828 msleep(10);
1826 } 1829 }
1827 1830
@@ -1869,7 +1872,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry,
1869 struct txentry_desc *txdesc) 1872 struct txentry_desc *txdesc)
1870{ 1873{
1871 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1874 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1872 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1875 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1873 __le32 *txd = entry_priv->desc; 1876 __le32 *txd = entry_priv->desc;
1874 u32 word; 1877 u32 word;
1875 1878
@@ -1967,7 +1970,7 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1967 struct txentry_desc *txdesc) 1970 struct txentry_desc *txdesc)
1968{ 1971{
1969 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1972 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1970 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1973 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1971 unsigned int beacon_base; 1974 unsigned int beacon_base;
1972 unsigned int padding_len; 1975 unsigned int padding_len;
1973 u32 orig_reg, reg; 1976 u32 orig_reg, reg;
@@ -1976,10 +1979,10 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1976 * Disable beaconing while we are reloading the beacon data, 1979 * Disable beaconing while we are reloading the beacon data,
1977 * otherwise we might be sending out invalid data. 1980 * otherwise we might be sending out invalid data.
1978 */ 1981 */
1979 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 1982 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1980 orig_reg = reg; 1983 orig_reg = reg;
1981 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1984 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1982 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1985 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1983 1986
1984 /* 1987 /*
1985 * Write the TX descriptor for the beacon. 1988 * Write the TX descriptor for the beacon.
@@ -1999,16 +2002,16 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1999 ERROR(rt2x00dev, "Failure padding beacon, aborting\n"); 2002 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
2000 /* skb freed by skb_pad() on failure */ 2003 /* skb freed by skb_pad() on failure */
2001 entry->skb = NULL; 2004 entry->skb = NULL;
2002 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, orig_reg); 2005 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
2003 return; 2006 return;
2004 } 2007 }
2005 2008
2006 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 2009 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2007 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base, 2010 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base,
2008 entry_priv->desc, TXINFO_SIZE); 2011 entry_priv->desc, TXINFO_SIZE);
2009 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE, 2012 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
2010 entry->skb->data, 2013 entry->skb->data,
2011 entry->skb->len + padding_len); 2014 entry->skb->len + padding_len);
2012 2015
2013 /* 2016 /*
2014 * Enable beaconing again. 2017 * Enable beaconing again.
@@ -2016,10 +2019,10 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
2016 * For Wi-Fi faily generated beacons between participating 2019 * For Wi-Fi faily generated beacons between participating
2017 * stations. Set TBTT phase adaptive adjustment step to 8us. 2020 * stations. Set TBTT phase adaptive adjustment step to 8us.
2018 */ 2021 */
2019 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 2022 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
2020 2023
2021 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 2024 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2022 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 2025 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
2023 2026
2024 /* 2027 /*
2025 * Clean up beacon skb. 2028 * Clean up beacon skb.
@@ -2037,21 +2040,21 @@ static void rt61pci_clear_beacon(struct queue_entry *entry)
2037 * Disable beaconing while we are reloading the beacon data, 2040 * Disable beaconing while we are reloading the beacon data,
2038 * otherwise we might be sending out invalid data. 2041 * otherwise we might be sending out invalid data.
2039 */ 2042 */
2040 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 2043 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
2041 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 2044 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2042 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 2045 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
2043 2046
2044 /* 2047 /*
2045 * Clear beacon. 2048 * Clear beacon.
2046 */ 2049 */
2047 rt2x00pci_register_write(rt2x00dev, 2050 rt2x00mmio_register_write(rt2x00dev,
2048 HW_BEACON_OFFSET(entry->entry_idx), 0); 2051 HW_BEACON_OFFSET(entry->entry_idx), 0);
2049 2052
2050 /* 2053 /*
2051 * Enable beaconing again. 2054 * Enable beaconing again.
2052 */ 2055 */
2053 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 2056 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2054 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 2057 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
2055} 2058}
2056 2059
2057/* 2060/*
@@ -2089,7 +2092,7 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry,
2089 struct rxdone_entry_desc *rxdesc) 2092 struct rxdone_entry_desc *rxdesc)
2090{ 2093{
2091 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 2094 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2092 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 2095 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
2093 u32 word0; 2096 u32 word0;
2094 u32 word1; 2097 u32 word1;
2095 2098
@@ -2155,7 +2158,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2155 struct data_queue *queue; 2158 struct data_queue *queue;
2156 struct queue_entry *entry; 2159 struct queue_entry *entry;
2157 struct queue_entry *entry_done; 2160 struct queue_entry *entry_done;
2158 struct queue_entry_priv_pci *entry_priv; 2161 struct queue_entry_priv_mmio *entry_priv;
2159 struct txdone_entry_desc txdesc; 2162 struct txdone_entry_desc txdesc;
2160 u32 word; 2163 u32 word;
2161 u32 reg; 2164 u32 reg;
@@ -2173,7 +2176,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2173 * tx ring size for now. 2176 * tx ring size for now.
2174 */ 2177 */
2175 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) { 2178 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
2176 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg); 2179 rt2x00mmio_register_read(rt2x00dev, STA_CSR4, &reg);
2177 if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) 2180 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2178 break; 2181 break;
2179 2182
@@ -2260,9 +2263,9 @@ static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
2260 */ 2263 */
2261 spin_lock_irq(&rt2x00dev->irqmask_lock); 2264 spin_lock_irq(&rt2x00dev->irqmask_lock);
2262 2265
2263 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 2266 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2264 rt2x00_set_field32(&reg, irq_field, 0); 2267 rt2x00_set_field32(&reg, irq_field, 0);
2265 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 2268 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
2266 2269
2267 spin_unlock_irq(&rt2x00dev->irqmask_lock); 2270 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2268} 2271}
@@ -2278,9 +2281,9 @@ static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
2278 */ 2281 */
2279 spin_lock_irq(&rt2x00dev->irqmask_lock); 2282 spin_lock_irq(&rt2x00dev->irqmask_lock);
2280 2283
2281 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg); 2284 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2282 rt2x00_set_field32(&reg, irq_field, 0); 2285 rt2x00_set_field32(&reg, irq_field, 0);
2283 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); 2286 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2284 2287
2285 spin_unlock_irq(&rt2x00dev->irqmask_lock); 2288 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2286} 2289}
@@ -2304,7 +2307,7 @@ static void rt61pci_tbtt_tasklet(unsigned long data)
2304static void rt61pci_rxdone_tasklet(unsigned long data) 2307static void rt61pci_rxdone_tasklet(unsigned long data)
2305{ 2308{
2306 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; 2309 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2307 if (rt2x00pci_rxdone(rt2x00dev)) 2310 if (rt2x00mmio_rxdone(rt2x00dev))
2308 tasklet_schedule(&rt2x00dev->rxdone_tasklet); 2311 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2309 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 2312 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2310 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE); 2313 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
@@ -2314,8 +2317,8 @@ static void rt61pci_autowake_tasklet(unsigned long data)
2314{ 2317{
2315 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; 2318 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2316 rt61pci_wakeup(rt2x00dev); 2319 rt61pci_wakeup(rt2x00dev);
2317 rt2x00pci_register_write(rt2x00dev, 2320 rt2x00mmio_register_write(rt2x00dev,
2318 M2H_CMD_DONE_CSR, 0xffffffff); 2321 M2H_CMD_DONE_CSR, 0xffffffff);
2319 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 2322 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2320 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP); 2323 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
2321} 2324}
@@ -2330,11 +2333,11 @@ static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2330 * Get the interrupt sources & saved to local variable. 2333 * Get the interrupt sources & saved to local variable.
2331 * Write register value back to clear pending interrupts. 2334 * Write register value back to clear pending interrupts.
2332 */ 2335 */
2333 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu); 2336 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2334 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); 2337 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2335 2338
2336 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 2339 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2337 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 2340 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2338 2341
2339 if (!reg && !reg_mcu) 2342 if (!reg && !reg_mcu)
2340 return IRQ_NONE; 2343 return IRQ_NONE;
@@ -2371,13 +2374,13 @@ static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2371 */ 2374 */
2372 spin_lock(&rt2x00dev->irqmask_lock); 2375 spin_lock(&rt2x00dev->irqmask_lock);
2373 2376
2374 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 2377 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2375 reg |= mask; 2378 reg |= mask;
2376 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 2379 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
2377 2380
2378 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg); 2381 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2379 reg |= mask_mcu; 2382 reg |= mask_mcu;
2380 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); 2383 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2381 2384
2382 spin_unlock(&rt2x00dev->irqmask_lock); 2385 spin_unlock(&rt2x00dev->irqmask_lock);
2383 2386
@@ -2395,7 +2398,7 @@ static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2395 u8 *mac; 2398 u8 *mac;
2396 s8 value; 2399 s8 value;
2397 2400
2398 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 2401 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
2399 2402
2400 eeprom.data = rt2x00dev; 2403 eeprom.data = rt2x00dev;
2401 eeprom.register_read = rt61pci_eepromregister_read; 2404 eeprom.register_read = rt61pci_eepromregister_read;
@@ -2513,7 +2516,7 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2513 * Identify RF chipset. 2516 * Identify RF chipset.
2514 */ 2517 */
2515 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 2518 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2516 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 2519 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg);
2517 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), 2520 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2518 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); 2521 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2519 2522
@@ -2838,7 +2841,7 @@ static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2838 /* 2841 /*
2839 * Disable power saving. 2842 * Disable power saving.
2840 */ 2843 */
2841 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); 2844 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2842 2845
2843 /* 2846 /*
2844 * Allocate eeprom data. 2847 * Allocate eeprom data.
@@ -2855,9 +2858,9 @@ static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2855 * Enable rfkill polling by setting GPIO direction of the 2858 * Enable rfkill polling by setting GPIO direction of the
2856 * rfkill switch GPIO pin correctly. 2859 * rfkill switch GPIO pin correctly.
2857 */ 2860 */
2858 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg); 2861 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
2859 rt2x00_set_field32(&reg, MAC_CSR13_DIR5, 1); 2862 rt2x00_set_field32(&reg, MAC_CSR13_DIR5, 1);
2860 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg); 2863 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
2861 2864
2862 /* 2865 /*
2863 * Initialize hw specifications. 2866 * Initialize hw specifications.
@@ -2927,25 +2930,25 @@ static int rt61pci_conf_tx(struct ieee80211_hw *hw,
2927 field.bit_offset = (queue_idx & 1) * 16; 2930 field.bit_offset = (queue_idx & 1) * 16;
2928 field.bit_mask = 0xffff << field.bit_offset; 2931 field.bit_mask = 0xffff << field.bit_offset;
2929 2932
2930 rt2x00pci_register_read(rt2x00dev, offset, &reg); 2933 rt2x00mmio_register_read(rt2x00dev, offset, &reg);
2931 rt2x00_set_field32(&reg, field, queue->txop); 2934 rt2x00_set_field32(&reg, field, queue->txop);
2932 rt2x00pci_register_write(rt2x00dev, offset, reg); 2935 rt2x00mmio_register_write(rt2x00dev, offset, reg);
2933 2936
2934 /* Update WMM registers */ 2937 /* Update WMM registers */
2935 field.bit_offset = queue_idx * 4; 2938 field.bit_offset = queue_idx * 4;
2936 field.bit_mask = 0xf << field.bit_offset; 2939 field.bit_mask = 0xf << field.bit_offset;
2937 2940
2938 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg); 2941 rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, &reg);
2939 rt2x00_set_field32(&reg, field, queue->aifs); 2942 rt2x00_set_field32(&reg, field, queue->aifs);
2940 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg); 2943 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg);
2941 2944
2942 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg); 2945 rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, &reg);
2943 rt2x00_set_field32(&reg, field, queue->cw_min); 2946 rt2x00_set_field32(&reg, field, queue->cw_min);
2944 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg); 2947 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg);
2945 2948
2946 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg); 2949 rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, &reg);
2947 rt2x00_set_field32(&reg, field, queue->cw_max); 2950 rt2x00_set_field32(&reg, field, queue->cw_max);
2948 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg); 2951 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg);
2949 2952
2950 return 0; 2953 return 0;
2951} 2954}
@@ -2956,9 +2959,9 @@ static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2956 u64 tsf; 2959 u64 tsf;
2957 u32 reg; 2960 u32 reg;
2958 2961
2959 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg); 2962 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, &reg);
2960 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; 2963 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2961 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg); 2964 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, &reg);
2962 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); 2965 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2963 2966
2964 return tsf; 2967 return tsf;
@@ -2997,8 +3000,8 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2997 .get_firmware_name = rt61pci_get_firmware_name, 3000 .get_firmware_name = rt61pci_get_firmware_name,
2998 .check_firmware = rt61pci_check_firmware, 3001 .check_firmware = rt61pci_check_firmware,
2999 .load_firmware = rt61pci_load_firmware, 3002 .load_firmware = rt61pci_load_firmware,
3000 .initialize = rt2x00pci_initialize, 3003 .initialize = rt2x00mmio_initialize,
3001 .uninitialize = rt2x00pci_uninitialize, 3004 .uninitialize = rt2x00mmio_uninitialize,
3002 .get_entry_state = rt61pci_get_entry_state, 3005 .get_entry_state = rt61pci_get_entry_state,
3003 .clear_entry = rt61pci_clear_entry, 3006 .clear_entry = rt61pci_clear_entry,
3004 .set_device_state = rt61pci_set_device_state, 3007 .set_device_state = rt61pci_set_device_state,
@@ -3009,7 +3012,7 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
3009 .start_queue = rt61pci_start_queue, 3012 .start_queue = rt61pci_start_queue,
3010 .kick_queue = rt61pci_kick_queue, 3013 .kick_queue = rt61pci_kick_queue,
3011 .stop_queue = rt61pci_stop_queue, 3014 .stop_queue = rt61pci_stop_queue,
3012 .flush_queue = rt2x00pci_flush_queue, 3015 .flush_queue = rt2x00mmio_flush_queue,
3013 .write_tx_desc = rt61pci_write_tx_desc, 3016 .write_tx_desc = rt61pci_write_tx_desc,
3014 .write_beacon = rt61pci_write_beacon, 3017 .write_beacon = rt61pci_write_beacon,
3015 .clear_beacon = rt61pci_clear_beacon, 3018 .clear_beacon = rt61pci_clear_beacon,
@@ -3027,21 +3030,21 @@ static const struct data_queue_desc rt61pci_queue_rx = {
3027 .entry_num = 32, 3030 .entry_num = 32,
3028 .data_size = DATA_FRAME_SIZE, 3031 .data_size = DATA_FRAME_SIZE,
3029 .desc_size = RXD_DESC_SIZE, 3032 .desc_size = RXD_DESC_SIZE,
3030 .priv_size = sizeof(struct queue_entry_priv_pci), 3033 .priv_size = sizeof(struct queue_entry_priv_mmio),
3031}; 3034};
3032 3035
3033static const struct data_queue_desc rt61pci_queue_tx = { 3036static const struct data_queue_desc rt61pci_queue_tx = {
3034 .entry_num = 32, 3037 .entry_num = 32,
3035 .data_size = DATA_FRAME_SIZE, 3038 .data_size = DATA_FRAME_SIZE,
3036 .desc_size = TXD_DESC_SIZE, 3039 .desc_size = TXD_DESC_SIZE,
3037 .priv_size = sizeof(struct queue_entry_priv_pci), 3040 .priv_size = sizeof(struct queue_entry_priv_mmio),
3038}; 3041};
3039 3042
3040static const struct data_queue_desc rt61pci_queue_bcn = { 3043static const struct data_queue_desc rt61pci_queue_bcn = {
3041 .entry_num = 4, 3044 .entry_num = 4,
3042 .data_size = 0, /* No DMA required for beacons */ 3045 .data_size = 0, /* No DMA required for beacons */
3043 .desc_size = TXINFO_SIZE, 3046 .desc_size = TXINFO_SIZE,
3044 .priv_size = sizeof(struct queue_entry_priv_pci), 3047 .priv_size = sizeof(struct queue_entry_priv_mmio),
3045}; 3048};
3046 3049
3047static const struct rt2x00_ops rt61pci_ops = { 3050static const struct rt2x00_ops rt61pci_ops = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 01:15:44 -0500