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authorTomas Winkler <tomas.winkler@intel.com>2008-03-25 19:33:37 -0400
committerJohn W. Linville <linville@tuxdriver.com>2008-03-27 16:03:17 -0400
commit3395f6e9cf48469d7ee05703cad1502002741c16 (patch)
treeca07b726dde7d42e113e9105e3c10f7ae9b1cb3a /drivers/net/wireless
parentab53d8af6772b22d4d68b1bcd74f7a5dba693983 (diff)
iwlwifi: rename iwl-4965-io.h to iwl-io.h
This patch renames iwl-4965-io.h back to iw-io.h it also remove 4965 from all functions it supplies Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c215
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.h1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-debugfs.c8
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.c26
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-io.h (renamed from drivers/net/wireless/iwlwifi/iwl-4965-io.h)238
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-led.c9
-rw-r--r--drivers/net/wireless/iwlwifi/iwl4965-base.c233
7 files changed, 364 insertions, 366 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 8b5cacb14618..e5f64d7fbfde 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -41,6 +41,7 @@
41#include "iwl-eeprom.h" 41#include "iwl-eeprom.h"
42#include "iwl-core.h" 42#include "iwl-core.h"
43#include "iwl-4965.h" 43#include "iwl-4965.h"
44#include "iwl-io.h"
44#include "iwl-helpers.h" 45#include "iwl-helpers.h"
45 46
46/* module parameters */ 47/* module parameters */
@@ -315,20 +316,20 @@ int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
315 unsigned long flags; 316 unsigned long flags;
316 317
317 spin_lock_irqsave(&priv->lock, flags); 318 spin_lock_irqsave(&priv->lock, flags);
318 rc = iwl4965_grab_nic_access(priv); 319 rc = iwl_grab_nic_access(priv);
319 if (rc) { 320 if (rc) {
320 spin_unlock_irqrestore(&priv->lock, flags); 321 spin_unlock_irqrestore(&priv->lock, flags);
321 return rc; 322 return rc;
322 } 323 }
323 324
324 /* stop Rx DMA */ 325 /* stop Rx DMA */
325 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 326 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
326 rc = iwl4965_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, 327 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
327 (1 << 24), 1000); 328 (1 << 24), 1000);
328 if (rc < 0) 329 if (rc < 0)
329 IWL_ERROR("Can't stop Rx DMA.\n"); 330 IWL_ERROR("Can't stop Rx DMA.\n");
330 331
331 iwl4965_release_nic_access(priv); 332 iwl_release_nic_access(priv);
332 spin_unlock_irqrestore(&priv->lock, flags); 333 spin_unlock_irqrestore(&priv->lock, flags);
333 334
334 return 0; 335 return 0;
@@ -372,7 +373,7 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
372 unsigned long flags; 373 unsigned long flags;
373 374
374 spin_lock_irqsave(&priv->lock, flags); 375 spin_lock_irqsave(&priv->lock, flags);
375 ret = iwl4965_grab_nic_access(priv); 376 ret = iwl_grab_nic_access(priv);
376 if (ret) { 377 if (ret) {
377 spin_unlock_irqrestore(&priv->lock, flags); 378 spin_unlock_irqrestore(&priv->lock, flags);
378 return ret; 379 return ret;
@@ -385,15 +386,15 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
385 &val); 386 &val);
386 387
387 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) 388 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
388 iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 389 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
389 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 390 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
390 ~APMG_PS_CTRL_MSK_PWR_SRC); 391 ~APMG_PS_CTRL_MSK_PWR_SRC);
391 } else 392 } else
392 iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 393 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
393 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 394 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
394 ~APMG_PS_CTRL_MSK_PWR_SRC); 395 ~APMG_PS_CTRL_MSK_PWR_SRC);
395 396
396 iwl4965_release_nic_access(priv); 397 iwl_release_nic_access(priv);
397 spin_unlock_irqrestore(&priv->lock, flags); 398 spin_unlock_irqrestore(&priv->lock, flags);
398 399
399 return ret; 400 return ret;
@@ -406,7 +407,7 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
406 unsigned int rb_size; 407 unsigned int rb_size;
407 408
408 spin_lock_irqsave(&priv->lock, flags); 409 spin_lock_irqsave(&priv->lock, flags);
409 rc = iwl4965_grab_nic_access(priv); 410 rc = iwl_grab_nic_access(priv);
410 if (rc) { 411 if (rc) {
411 spin_unlock_irqrestore(&priv->lock, flags); 412 spin_unlock_irqrestore(&priv->lock, flags);
412 return rc; 413 return rc;
@@ -418,34 +419,34 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
418 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 419 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
419 420
420 /* Stop Rx DMA */ 421 /* Stop Rx DMA */
421 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 422 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
422 423
423 /* Reset driver's Rx queue write index */ 424 /* Reset driver's Rx queue write index */
424 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 425 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
425 426
426 /* Tell device where to find RBD circular buffer in DRAM */ 427 /* Tell device where to find RBD circular buffer in DRAM */
427 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 428 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
428 rxq->dma_addr >> 8); 429 rxq->dma_addr >> 8);
429 430
430 /* Tell device where in DRAM to update its Rx status */ 431 /* Tell device where in DRAM to update its Rx status */
431 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, 432 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
432 (priv->hw_setting.shared_phys + 433 (priv->hw_setting.shared_phys +
433 offsetof(struct iwl4965_shared, val0)) >> 4); 434 offsetof(struct iwl4965_shared, val0)) >> 4);
434 435
435 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */ 436 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
436 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 437 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
437 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 438 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
438 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 439 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
439 rb_size | 440 rb_size |
440 /*0x10 << 4 | */ 441 /*0x10 << 4 | */
441 (RX_QUEUE_SIZE_LOG << 442 (RX_QUEUE_SIZE_LOG <<
442 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT)); 443 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
443 444
444 /* 445 /*
445 * iwl4965_write32(priv,CSR_INT_COAL_REG,0); 446 * iwl_write32(priv,CSR_INT_COAL_REG,0);
446 */ 447 */
447 448
448 iwl4965_release_nic_access(priv); 449 iwl_release_nic_access(priv);
449 spin_unlock_irqrestore(&priv->lock, flags); 450 spin_unlock_irqrestore(&priv->lock, flags);
450 451
451 return 0; 452 return 0;
@@ -458,13 +459,13 @@ static int iwl4965_kw_init(struct iwl_priv *priv)
458 int rc; 459 int rc;
459 460
460 spin_lock_irqsave(&priv->lock, flags); 461 spin_lock_irqsave(&priv->lock, flags);
461 rc = iwl4965_grab_nic_access(priv); 462 rc = iwl_grab_nic_access(priv);
462 if (rc) 463 if (rc)
463 goto out; 464 goto out;
464 465
465 iwl4965_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG, 466 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
466 priv->kw.dma_addr >> 4); 467 priv->kw.dma_addr >> 4);
467 iwl4965_release_nic_access(priv); 468 iwl_release_nic_access(priv);
468out: 469out:
469 spin_unlock_irqrestore(&priv->lock, flags); 470 spin_unlock_irqrestore(&priv->lock, flags);
470 return rc; 471 return rc;
@@ -524,7 +525,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
524 525
525 spin_lock_irqsave(&priv->lock, flags); 526 spin_lock_irqsave(&priv->lock, flags);
526 527
527 rc = iwl4965_grab_nic_access(priv); 528 rc = iwl_grab_nic_access(priv);
528 if (unlikely(rc)) { 529 if (unlikely(rc)) {
529 IWL_ERROR("TX reset failed"); 530 IWL_ERROR("TX reset failed");
530 spin_unlock_irqrestore(&priv->lock, flags); 531 spin_unlock_irqrestore(&priv->lock, flags);
@@ -532,8 +533,8 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
532 } 533 }
533 534
534 /* Turn off all Tx DMA channels */ 535 /* Turn off all Tx DMA channels */
535 iwl4965_write_prph(priv, KDR_SCD_TXFACT, 0); 536 iwl_write_prph(priv, KDR_SCD_TXFACT, 0);
536 iwl4965_release_nic_access(priv); 537 iwl_release_nic_access(priv);
537 spin_unlock_irqrestore(&priv->lock, flags); 538 spin_unlock_irqrestore(&priv->lock, flags);
538 539
539 /* Tell 4965 where to find the keep-warm buffer */ 540 /* Tell 4965 where to find the keep-warm buffer */
@@ -580,11 +581,11 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv)
580 /* nic_init */ 581 /* nic_init */
581 spin_lock_irqsave(&priv->lock, flags); 582 spin_lock_irqsave(&priv->lock, flags);
582 583
583 iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS, 584 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
584 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 585 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
585 586
586 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 587 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
587 rc = iwl4965_poll_bit(priv, CSR_GP_CNTRL, 588 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
588 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 589 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
589 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 590 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
590 if (rc < 0) { 591 if (rc < 0) {
@@ -593,26 +594,25 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv)
593 return rc; 594 return rc;
594 } 595 }
595 596
596 rc = iwl4965_grab_nic_access(priv); 597 rc = iwl_grab_nic_access(priv);
597 if (rc) { 598 if (rc) {
598 spin_unlock_irqrestore(&priv->lock, flags); 599 spin_unlock_irqrestore(&priv->lock, flags);
599 return rc; 600 return rc;
600 } 601 }
601 602
602 iwl4965_read_prph(priv, APMG_CLK_CTRL_REG); 603 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
603 604
604 iwl4965_write_prph(priv, APMG_CLK_CTRL_REG, 605 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
605 APMG_CLK_VAL_DMA_CLK_RQT | 606 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
606 APMG_CLK_VAL_BSM_CLK_RQT); 607 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
607 iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
608 608
609 udelay(20); 609 udelay(20);
610 610
611 iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 611 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
612 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 612 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
613 613
614 iwl4965_release_nic_access(priv); 614 iwl_release_nic_access(priv);
615 iwl4965_write32(priv, CSR_INT_COALESCING, 512 / 32); 615 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
616 spin_unlock_irqrestore(&priv->lock, flags); 616 spin_unlock_irqrestore(&priv->lock, flags);
617 617
618 /* Determine HW type */ 618 /* Determine HW type */
@@ -648,26 +648,24 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv)
648 648
649 /* set CSR_HW_CONFIG_REG for uCode use */ 649 /* set CSR_HW_CONFIG_REG for uCode use */
650 650
651 iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG, 651 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
652 CSR49_HW_IF_CONFIG_REG_BIT_4965_R | 652 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
653 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI | 653 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
654 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI); 654 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
655 655
656 rc = iwl4965_grab_nic_access(priv); 656 rc = iwl_grab_nic_access(priv);
657 if (rc < 0) { 657 if (rc < 0) {
658 spin_unlock_irqrestore(&priv->lock, flags); 658 spin_unlock_irqrestore(&priv->lock, flags);
659 IWL_DEBUG_INFO("Failed to init the card\n"); 659 IWL_DEBUG_INFO("Failed to init the card\n");
660 return rc; 660 return rc;
661 } 661 }
662 662
663 iwl4965_read_prph(priv, APMG_PS_CTRL_REG); 663 iwl_read_prph(priv, APMG_PS_CTRL_REG);
664 iwl4965_set_bits_prph(priv, APMG_PS_CTRL_REG, 664 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
665 APMG_PS_CTRL_VAL_RESET_REQ);
666 udelay(5); 665 udelay(5);
667 iwl4965_clear_bits_prph(priv, APMG_PS_CTRL_REG, 666 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
668 APMG_PS_CTRL_VAL_RESET_REQ);
669 667
670 iwl4965_release_nic_access(priv); 668 iwl_release_nic_access(priv);
671 spin_unlock_irqrestore(&priv->lock, flags); 669 spin_unlock_irqrestore(&priv->lock, flags);
672 670
673 iwl4965_hw_card_show_info(priv); 671 iwl4965_hw_card_show_info(priv);
@@ -720,16 +718,16 @@ int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
720 spin_lock_irqsave(&priv->lock, flags); 718 spin_lock_irqsave(&priv->lock, flags);
721 719
722 /* set stop master bit */ 720 /* set stop master bit */
723 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 721 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
724 722
725 reg_val = iwl4965_read32(priv, CSR_GP_CNTRL); 723 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
726 724
727 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE == 725 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
728 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE)) 726 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
729 IWL_DEBUG_INFO("Card in power save, master is already " 727 IWL_DEBUG_INFO("Card in power save, master is already "
730 "stopped\n"); 728 "stopped\n");
731 else { 729 else {
732 rc = iwl4965_poll_bit(priv, CSR_RESET, 730 rc = iwl_poll_bit(priv, CSR_RESET,
733 CSR_RESET_REG_FLAG_MASTER_DISABLED, 731 CSR_RESET_REG_FLAG_MASTER_DISABLED,
734 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 732 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
735 if (rc < 0) { 733 if (rc < 0) {
@@ -756,18 +754,17 @@ void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
756 /* Stop each Tx DMA channel, and wait for it to be idle */ 754 /* Stop each Tx DMA channel, and wait for it to be idle */
757 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) { 755 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
758 spin_lock_irqsave(&priv->lock, flags); 756 spin_lock_irqsave(&priv->lock, flags);
759 if (iwl4965_grab_nic_access(priv)) { 757 if (iwl_grab_nic_access(priv)) {
760 spin_unlock_irqrestore(&priv->lock, flags); 758 spin_unlock_irqrestore(&priv->lock, flags);
761 continue; 759 continue;
762 } 760 }
763 761
764 iwl4965_write_direct32(priv, 762 iwl_write_direct32(priv,
765 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 763 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
766 0x0); 764 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
767 iwl4965_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG, 765 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
768 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE 766 (txq_id), 200);
769 (txq_id), 200); 767 iwl_release_nic_access(priv);
770 iwl4965_release_nic_access(priv);
771 spin_unlock_irqrestore(&priv->lock, flags); 768 spin_unlock_irqrestore(&priv->lock, flags);
772 } 769 }
773 770
@@ -784,29 +781,29 @@ int iwl4965_hw_nic_reset(struct iwl_priv *priv)
784 781
785 spin_lock_irqsave(&priv->lock, flags); 782 spin_lock_irqsave(&priv->lock, flags);
786 783
787 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 784 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
788 785
789 udelay(10); 786 udelay(10);
790 787
791 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 788 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
792 rc = iwl4965_poll_bit(priv, CSR_RESET, 789 rc = iwl_poll_bit(priv, CSR_RESET,
793 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 790 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
794 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25); 791 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
795 792
796 udelay(10); 793 udelay(10);
797 794
798 rc = iwl4965_grab_nic_access(priv); 795 rc = iwl_grab_nic_access(priv);
799 if (!rc) { 796 if (!rc) {
800 iwl4965_write_prph(priv, APMG_CLK_EN_REG, 797 iwl_write_prph(priv, APMG_CLK_EN_REG,
801 APMG_CLK_VAL_DMA_CLK_RQT | 798 APMG_CLK_VAL_DMA_CLK_RQT |
802 APMG_CLK_VAL_BSM_CLK_RQT); 799 APMG_CLK_VAL_BSM_CLK_RQT);
803 800
804 udelay(10); 801 udelay(10);
805 802
806 iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 803 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
807 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 804 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
808 805
809 iwl4965_release_nic_access(priv); 806 iwl_release_nic_access(priv);
810 } 807 }
811 808
812 clear_bit(STATUS_HCMD_ACTIVE, &priv->status); 809 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
@@ -872,7 +869,7 @@ void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
872 int ret = 0; 869 int ret = 0;
873 870
874 spin_lock_irqsave(&priv->lock, flags); 871 spin_lock_irqsave(&priv->lock, flags);
875 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, 872 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
876 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 873 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
877 spin_unlock_irqrestore(&priv->lock, flags); 874 spin_unlock_irqrestore(&priv->lock, flags);
878 875
@@ -1733,9 +1730,9 @@ static void iwl4965_bg_txpower_work(struct work_struct *work)
1733 */ 1730 */
1734static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index) 1731static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
1735{ 1732{
1736 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 1733 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
1737 (index & 0xff) | (txq_id << 8)); 1734 (index & 0xff) | (txq_id << 8));
1738 iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index); 1735 iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
1739} 1736}
1740 1737
1741/** 1738/**
@@ -1755,7 +1752,7 @@ static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
1755 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0; 1752 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1756 1753
1757 /* Set up and activate */ 1754 /* Set up and activate */
1758 iwl4965_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id), 1755 iwl_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
1759 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1756 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1760 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | 1757 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1761 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) | 1758 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
@@ -1807,46 +1804,46 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1807 priv->chain_noise_data.delta_gain_code[i] = 1804 priv->chain_noise_data.delta_gain_code[i] =
1808 CHAIN_NOISE_DELTA_GAIN_INIT_VAL; 1805 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
1809#endif /* CONFIG_IWL4965_SENSITIVITY*/ 1806#endif /* CONFIG_IWL4965_SENSITIVITY*/
1810 ret = iwl4965_grab_nic_access(priv); 1807 ret = iwl_grab_nic_access(priv);
1811 if (ret) { 1808 if (ret) {
1812 spin_unlock_irqrestore(&priv->lock, flags); 1809 spin_unlock_irqrestore(&priv->lock, flags);
1813 return ret; 1810 return ret;
1814 } 1811 }
1815 1812
1816 /* Clear 4965's internal Tx Scheduler data base */ 1813 /* Clear 4965's internal Tx Scheduler data base */
1817 priv->scd_base_addr = iwl4965_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR); 1814 priv->scd_base_addr = iwl_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
1818 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET; 1815 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1819 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4) 1816 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1820 iwl4965_write_targ_mem(priv, a, 0); 1817 iwl_write_targ_mem(priv, a, 0);
1821 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4) 1818 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
1822 iwl4965_write_targ_mem(priv, a, 0); 1819 iwl_write_targ_mem(priv, a, 0);
1823 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4) 1820 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
1824 iwl4965_write_targ_mem(priv, a, 0); 1821 iwl_write_targ_mem(priv, a, 0);
1825 1822
1826 /* Tel 4965 where to find Tx byte count tables */ 1823 /* Tel 4965 where to find Tx byte count tables */
1827 iwl4965_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR, 1824 iwl_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
1828 (priv->hw_setting.shared_phys + 1825 (priv->hw_setting.shared_phys +
1829 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10); 1826 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
1830 1827
1831 /* Disable chain mode for all queues */ 1828 /* Disable chain mode for all queues */
1832 iwl4965_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0); 1829 iwl_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
1833 1830
1834 /* Initialize each Tx queue (including the command queue) */ 1831 /* Initialize each Tx queue (including the command queue) */
1835 for (i = 0; i < priv->hw_setting.max_txq_num; i++) { 1832 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
1836 1833
1837 /* TFD circular buffer read/write indexes */ 1834 /* TFD circular buffer read/write indexes */
1838 iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0); 1835 iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
1839 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 1836 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1840 1837
1841 /* Max Tx Window size for Scheduler-ACK mode */ 1838 /* Max Tx Window size for Scheduler-ACK mode */
1842 iwl4965_write_targ_mem(priv, priv->scd_base_addr + 1839 iwl_write_targ_mem(priv, priv->scd_base_addr +
1843 SCD_CONTEXT_QUEUE_OFFSET(i), 1840 SCD_CONTEXT_QUEUE_OFFSET(i),
1844 (SCD_WIN_SIZE << 1841 (SCD_WIN_SIZE <<
1845 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & 1842 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1846 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 1843 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1847 1844
1848 /* Frame limit */ 1845 /* Frame limit */
1849 iwl4965_write_targ_mem(priv, priv->scd_base_addr + 1846 iwl_write_targ_mem(priv, priv->scd_base_addr +
1850 SCD_CONTEXT_QUEUE_OFFSET(i) + 1847 SCD_CONTEXT_QUEUE_OFFSET(i) +
1851 sizeof(u32), 1848 sizeof(u32),
1852 (SCD_FRAME_LIMIT << 1849 (SCD_FRAME_LIMIT <<
@@ -1854,11 +1851,11 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1854 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 1851 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1855 1852
1856 } 1853 }
1857 iwl4965_write_prph(priv, KDR_SCD_INTERRUPT_MASK, 1854 iwl_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
1858 (1 << priv->hw_setting.max_txq_num) - 1); 1855 (1 << priv->hw_setting.max_txq_num) - 1);
1859 1856
1860 /* Activate all Tx DMA/FIFO channels */ 1857 /* Activate all Tx DMA/FIFO channels */
1861 iwl4965_write_prph(priv, KDR_SCD_TXFACT, 1858 iwl_write_prph(priv, KDR_SCD_TXFACT,
1862 SCD_TXFACT_REG_TXFIFO_MASK(0, 7)); 1859 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1863 1860
1864 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 1861 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
@@ -1870,7 +1867,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1870 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 1867 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1871 } 1868 }
1872 1869
1873 iwl4965_release_nic_access(priv); 1870 iwl_release_nic_access(priv);
1874 spin_unlock_irqrestore(&priv->lock, flags); 1871 spin_unlock_irqrestore(&priv->lock, flags);
1875 1872
1876 return ret; 1873 return ret;
@@ -2929,22 +2926,22 @@ int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq
2929 int txq_id = txq->q.id; 2926 int txq_id = txq->q.id;
2930 2927
2931 spin_lock_irqsave(&priv->lock, flags); 2928 spin_lock_irqsave(&priv->lock, flags);
2932 rc = iwl4965_grab_nic_access(priv); 2929 rc = iwl_grab_nic_access(priv);
2933 if (rc) { 2930 if (rc) {
2934 spin_unlock_irqrestore(&priv->lock, flags); 2931 spin_unlock_irqrestore(&priv->lock, flags);
2935 return rc; 2932 return rc;
2936 } 2933 }
2937 2934
2938 /* Circular buffer (TFD queue in DRAM) physical base address */ 2935 /* Circular buffer (TFD queue in DRAM) physical base address */
2939 iwl4965_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), 2936 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
2940 txq->q.dma_addr >> 8); 2937 txq->q.dma_addr >> 8);
2941 2938
2942 /* Enable DMA channel, using same id as for TFD queue */ 2939 /* Enable DMA channel, using same id as for TFD queue */
2943 iwl4965_write_direct32( 2940 iwl_write_direct32(
2944 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 2941 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2945 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 2942 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2946 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); 2943 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
2947 iwl4965_release_nic_access(priv); 2944 iwl_release_nic_access(priv);
2948 spin_unlock_irqrestore(&priv->lock, flags); 2945 spin_unlock_irqrestore(&priv->lock, flags);
2949 2946
2950 return 0; 2947 return 0;
@@ -4259,7 +4256,7 @@ static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
4259{ 4256{
4260 /* Simply stop the queue, but don't change any configuration; 4257 /* Simply stop the queue, but don't change any configuration;
4261 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 4258 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
4262 iwl4965_write_prph(priv, 4259 iwl_write_prph(priv,
4263 KDR_SCD_QUEUE_STATUS_BITS(txq_id), 4260 KDR_SCD_QUEUE_STATUS_BITS(txq_id),
4264 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| 4261 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
4265 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 4262 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
@@ -4280,24 +4277,24 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
4280 return -EINVAL; 4277 return -EINVAL;
4281 } 4278 }
4282 4279
4283 ret = iwl4965_grab_nic_access(priv); 4280 ret = iwl_grab_nic_access(priv);
4284 if (ret) 4281 if (ret)
4285 return ret; 4282 return ret;
4286 4283
4287 iwl4965_tx_queue_stop_scheduler(priv, txq_id); 4284 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4288 4285
4289 iwl4965_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id)); 4286 iwl_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
4290 4287
4291 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 4288 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4292 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 4289 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
4293 /* supposes that ssn_idx is valid (!= 0xFFF) */ 4290 /* supposes that ssn_idx is valid (!= 0xFFF) */
4294 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); 4291 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4295 4292
4296 iwl4965_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id)); 4293 iwl_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
4297 iwl4965_txq_ctx_deactivate(priv, txq_id); 4294 iwl4965_txq_ctx_deactivate(priv, txq_id);
4298 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 4295 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
4299 4296
4300 iwl4965_release_nic_access(priv); 4297 iwl_release_nic_access(priv);
4301 4298
4302 return 0; 4299 return 0;
4303} 4300}
@@ -4432,14 +4429,14 @@ static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
4432 tbl_dw_addr = priv->scd_base_addr + 4429 tbl_dw_addr = priv->scd_base_addr +
4433 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 4430 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
4434 4431
4435 tbl_dw = iwl4965_read_targ_mem(priv, tbl_dw_addr); 4432 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
4436 4433
4437 if (txq_id & 0x1) 4434 if (txq_id & 0x1)
4438 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 4435 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
4439 else 4436 else
4440 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 4437 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
4441 4438
4442 iwl4965_write_targ_mem(priv, tbl_dw_addr, tbl_dw); 4439 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
4443 4440
4444 return 0; 4441 return 0;
4445} 4442}
@@ -4469,7 +4466,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4469 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid); 4466 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
4470 4467
4471 spin_lock_irqsave(&priv->lock, flags); 4468 spin_lock_irqsave(&priv->lock, flags);
4472 rc = iwl4965_grab_nic_access(priv); 4469 rc = iwl_grab_nic_access(priv);
4473 if (rc) { 4470 if (rc) {
4474 spin_unlock_irqrestore(&priv->lock, flags); 4471 spin_unlock_irqrestore(&priv->lock, flags);
4475 return rc; 4472 return rc;
@@ -4482,7 +4479,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4482 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id); 4479 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
4483 4480
4484 /* Set this queue as a chain-building queue */ 4481 /* Set this queue as a chain-building queue */
4485 iwl4965_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id)); 4482 iwl_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
4486 4483
4487 /* Place first TFD at index corresponding to start sequence number. 4484 /* Place first TFD at index corresponding to start sequence number.
4488 * Assumes that ssn_idx is valid (!= 0xFFF) */ 4485 * Assumes that ssn_idx is valid (!= 0xFFF) */
@@ -4491,22 +4488,22 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4491 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); 4488 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4492 4489
4493 /* Set up Tx window size and frame limit for this queue */ 4490 /* Set up Tx window size and frame limit for this queue */
4494 iwl4965_write_targ_mem(priv, 4491 iwl_write_targ_mem(priv,
4495 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id), 4492 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
4496 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & 4493 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4497 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 4494 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
4498 4495
4499 iwl4965_write_targ_mem(priv, priv->scd_base_addr + 4496 iwl_write_targ_mem(priv, priv->scd_base_addr +
4500 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 4497 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
4501 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) 4498 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
4502 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 4499 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4503 4500
4504 iwl4965_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id)); 4501 iwl_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
4505 4502
4506 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 4503 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
4507 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 4504 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
4508 4505
4509 iwl4965_release_nic_access(priv); 4506 iwl_release_nic_access(priv);
4510 spin_unlock_irqrestore(&priv->lock, flags); 4507 spin_unlock_irqrestore(&priv->lock, flags);
4511 4508
4512 return 0; 4509 return 0;
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.h b/drivers/net/wireless/iwlwifi/iwl-4965.h
index 32c21d266f98..98644d9c7803 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.h
@@ -1266,6 +1266,5 @@ extern const struct iwl_channel_info *iwl_get_channel_info(
1266 const struct iwl_priv *priv, enum ieee80211_band band, u16 channel); 1266 const struct iwl_priv *priv, enum ieee80211_band band, u16 channel);
1267 1267
1268/* Requires full declaration of iwl_priv before including */ 1268/* Requires full declaration of iwl_priv before including */
1269#include "iwl-4965-io.h"
1270 1269
1271#endif /* __iwl4965_4965_h__ */ 1270#endif /* __iwl4965_4965_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
index c659bd3bc346..b2cc552de738 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debugfs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
@@ -36,7 +36,7 @@
36 36
37#include "iwl-4965.h" 37#include "iwl-4965.h"
38#include "iwl-debug.h" 38#include "iwl-debug.h"
39#include "iwl-4965-io.h" 39#include "iwl-io.h"
40 40
41 41
42/* create and remove of files */ 42/* create and remove of files */
@@ -141,9 +141,9 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
141 printk(KERN_DEBUG "offset is: 0x%x\tlen is: 0x%x\n", 141 printk(KERN_DEBUG "offset is: 0x%x\tlen is: 0x%x\n",
142 priv->dbgfs->sram_offset, priv->dbgfs->sram_len); 142 priv->dbgfs->sram_offset, priv->dbgfs->sram_len);
143 143
144 iwl4965_grab_nic_access(priv); 144 iwl_grab_nic_access(priv);
145 for (i = priv->dbgfs->sram_len; i > 0; i -= 4) { 145 for (i = priv->dbgfs->sram_len; i > 0; i -= 4) {
146 val = iwl4965_read_targ_mem(priv, priv->dbgfs->sram_offset + \ 146 val = iwl_read_targ_mem(priv, priv->dbgfs->sram_offset + \
147 priv->dbgfs->sram_len - i); 147 priv->dbgfs->sram_len - i);
148 if (i < 4) { 148 if (i < 4) {
149 switch (i) { 149 switch (i) {
@@ -161,7 +161,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
161 pos += sprintf(buf+pos, "0x%08x ", val); 161 pos += sprintf(buf+pos, "0x%08x ", val);
162 } 162 }
163 pos += sprintf(buf+pos, "\n"); 163 pos += sprintf(buf+pos, "\n");
164 iwl4965_release_nic_access(priv); 164 iwl_release_nic_access(priv);
165 165
166 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 166 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
167 return ret; 167 return ret;
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index 72cad56fbd93..a07d5dcb7abc 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -73,7 +73,7 @@
73#include "iwl-core.h" 73#include "iwl-core.h"
74#include "iwl-debug.h" 74#include "iwl-debug.h"
75#include "iwl-eeprom.h" 75#include "iwl-eeprom.h"
76#include "iwl-4965-io.h" 76#include "iwl-io.h"
77 77
78/************************** EEPROM BANDS **************************** 78/************************** EEPROM BANDS ****************************
79 * 79 *
@@ -144,7 +144,7 @@ static const u8 iwl_eeprom_band_7[] = { /* 5.2 FAT channel */
144 144
145int iwlcore_eeprom_verify_signature(struct iwl_priv *priv) 145int iwlcore_eeprom_verify_signature(struct iwl_priv *priv)
146{ 146{
147 u32 gp = iwl4965_read32(priv, CSR_EEPROM_GP); 147 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
148 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { 148 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
149 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp); 149 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
150 return -ENOENT; 150 return -ENOENT;
@@ -166,14 +166,14 @@ int iwlcore_eeprom_acquire_semaphore(struct iwl_priv *priv)
166 166
167 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) { 167 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
168 /* Request semaphore */ 168 /* Request semaphore */
169 iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG, 169 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
170 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 170 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
171 171
172 /* See if we got it */ 172 /* See if we got it */
173 ret = iwl4965_poll_bit(priv, CSR_HW_IF_CONFIG_REG, 173 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
174 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 174 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
175 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 175 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
176 EEPROM_SEM_TIMEOUT); 176 EEPROM_SEM_TIMEOUT);
177 if (ret >= 0) { 177 if (ret >= 0) {
178 IWL_DEBUG_IO("Acquired semaphore after %d tries.\n", 178 IWL_DEBUG_IO("Acquired semaphore after %d tries.\n",
179 count+1); 179 count+1);
@@ -187,7 +187,7 @@ EXPORT_SYMBOL(iwlcore_eeprom_acquire_semaphore);
187 187
188void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv) 188void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv)
189{ 189{
190 iwl4965_clear_bit(priv, CSR_HW_IF_CONFIG_REG, 190 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
191 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 191 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
192 192
193} 193}
@@ -204,7 +204,7 @@ EXPORT_SYMBOL(iwlcore_eeprom_release_semaphore);
204int iwl_eeprom_init(struct iwl_priv *priv) 204int iwl_eeprom_init(struct iwl_priv *priv)
205{ 205{
206 u16 *e = (u16 *)&priv->eeprom; 206 u16 *e = (u16 *)&priv->eeprom;
207 u32 gp = iwl4965_read32(priv, CSR_EEPROM_GP); 207 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
208 u32 r; 208 u32 r;
209 int sz = sizeof(priv->eeprom); 209 int sz = sizeof(priv->eeprom);
210 int ret; 210 int ret;
@@ -231,12 +231,12 @@ int iwl_eeprom_init(struct iwl_priv *priv)
231 231
232 /* eeprom is an array of 16bit values */ 232 /* eeprom is an array of 16bit values */
233 for (addr = 0; addr < sz; addr += sizeof(u16)) { 233 for (addr = 0; addr < sz; addr += sizeof(u16)) {
234 _iwl4965_write32(priv, CSR_EEPROM_REG, addr << 1); 234 _iwl_write32(priv, CSR_EEPROM_REG, addr << 1);
235 _iwl4965_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD); 235 _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
236 236
237 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT; 237 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
238 i += IWL_EEPROM_ACCESS_DELAY) { 238 i += IWL_EEPROM_ACCESS_DELAY) {
239 r = _iwl4965_read_direct32(priv, CSR_EEPROM_REG); 239 r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
240 if (r & CSR_EEPROM_REG_READ_VALID_MSK) 240 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
241 break; 241 break;
242 udelay(IWL_EEPROM_ACCESS_DELAY); 242 udelay(IWL_EEPROM_ACCESS_DELAY);
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-io.h b/drivers/net/wireless/iwlwifi/iwl-io.h
index fba7d03d4291..09cc094340b0 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-io.h
+++ b/drivers/net/wireless/iwlwifi/iwl-io.h
@@ -26,8 +26,8 @@
26 * 26 *
27 *****************************************************************************/ 27 *****************************************************************************/
28 28
29#ifndef __iwl4965_io_h__ 29#ifndef __iwl_io_h__
30#define __iwl4965_io_h__ 30#define __iwl_io_h__
31 31
32#include <linux/io.h> 32#include <linux/io.h>
33 33
@@ -49,8 +49,8 @@
49 * 49 *
50 * If you wish to call the function without any debug or state checking, 50 * If you wish to call the function without any debug or state checking,
51 * you should use the single _ prefix version (as is used by dependent IO 51 * you should use the single _ prefix version (as is used by dependent IO
52 * routines, for example _iwl4965_read_direct32 calls the non-check version of 52 * routines, for example _iwl_read_direct32 calls the non-check version of
53 * _iwl4965_read32.) 53 * _iwl_read32.)
54 * 54 *
55 * These declarations are *extremely* useful in quickly isolating code deltas 55 * These declarations are *extremely* useful in quickly isolating code deltas
56 * which result in misconfiguring of the hardware I/O. In combination with 56 * which result in misconfiguring of the hardware I/O. In combination with
@@ -59,39 +59,39 @@
59 * 59 *
60 */ 60 */
61 61
62#define _iwl4965_write32(priv, ofs, val) writel((val), (priv)->hw_base + (ofs)) 62#define _iwl_write32(priv, ofs, val) writel((val), (priv)->hw_base + (ofs))
63#ifdef CONFIG_IWLWIFI_DEBUG 63#ifdef CONFIG_IWLWIFI_DEBUG
64static inline void __iwl4965_write32(const char *f, u32 l, struct iwl_priv *priv, 64static inline void __iwl_write32(const char *f, u32 l, struct iwl_priv *priv,
65 u32 ofs, u32 val) 65 u32 ofs, u32 val)
66{ 66{
67 IWL_DEBUG_IO("write32(0x%08X, 0x%08X) - %s %d\n", ofs, val, f, l); 67 IWL_DEBUG_IO("write32(0x%08X, 0x%08X) - %s %d\n", ofs, val, f, l);
68 _iwl4965_write32(priv, ofs, val); 68 _iwl_write32(priv, ofs, val);
69} 69}
70#define iwl4965_write32(priv, ofs, val) \ 70#define iwl_write32(priv, ofs, val) \
71 __iwl4965_write32(__FILE__, __LINE__, priv, ofs, val) 71 __iwl_write32(__FILE__, __LINE__, priv, ofs, val)
72#else 72#else
73#define iwl4965_write32(priv, ofs, val) _iwl4965_write32(priv, ofs, val) 73#define iwl_write32(priv, ofs, val) _iwl_write32(priv, ofs, val)
74#endif 74#endif
75 75
76#define _iwl4965_read32(priv, ofs) readl((priv)->hw_base + (ofs)) 76#define _iwl_read32(priv, ofs) readl((priv)->hw_base + (ofs))
77#ifdef CONFIG_IWLWIFI_DEBUG 77#ifdef CONFIG_IWLWIFI_DEBUG
78static inline u32 __iwl4965_read32(char *f, u32 l, struct iwl_priv *priv, u32 ofs) 78static inline u32 __iwl_read32(char *f, u32 l, struct iwl_priv *priv, u32 ofs)
79{ 79{
80 IWL_DEBUG_IO("read_direct32(0x%08X) - %s %d\n", ofs, f, l); 80 IWL_DEBUG_IO("read_direct32(0x%08X) - %s %d\n", ofs, f, l);
81 return _iwl4965_read32(priv, ofs); 81 return _iwl_read32(priv, ofs);
82} 82}
83#define iwl4965_read32(priv, ofs) __iwl4965_read32(__FILE__, __LINE__, priv, ofs) 83#define iwl_read32(priv, ofs) __iwl_read32(__FILE__, __LINE__, priv, ofs)
84#else 84#else
85#define iwl4965_read32(p, o) _iwl4965_read32(p, o) 85#define iwl_read32(p, o) _iwl_read32(p, o)
86#endif 86#endif
87 87
88static inline int _iwl4965_poll_bit(struct iwl_priv *priv, u32 addr, 88static inline int _iwl_poll_bit(struct iwl_priv *priv, u32 addr,
89 u32 bits, u32 mask, int timeout) 89 u32 bits, u32 mask, int timeout)
90{ 90{
91 int i = 0; 91 int i = 0;
92 92
93 do { 93 do {
94 if ((_iwl4965_read32(priv, addr) & mask) == (bits & mask)) 94 if ((_iwl_read32(priv, addr) & mask) == (bits & mask))
95 return i; 95 return i;
96 mdelay(10); 96 mdelay(10);
97 i += 10; 97 i += 10;
@@ -100,57 +100,57 @@ static inline int _iwl4965_poll_bit(struct iwl_priv *priv, u32 addr,
100 return -ETIMEDOUT; 100 return -ETIMEDOUT;
101} 101}
102#ifdef CONFIG_IWLWIFI_DEBUG 102#ifdef CONFIG_IWLWIFI_DEBUG
103static inline int __iwl4965_poll_bit(const char *f, u32 l, 103static inline int __iwl_poll_bit(const char *f, u32 l,
104 struct iwl_priv *priv, u32 addr, 104 struct iwl_priv *priv, u32 addr,
105 u32 bits, u32 mask, int timeout) 105 u32 bits, u32 mask, int timeout)
106{ 106{
107 int ret = _iwl4965_poll_bit(priv, addr, bits, mask, timeout); 107 int ret = _iwl_poll_bit(priv, addr, bits, mask, timeout);
108 IWL_DEBUG_IO("poll_bit(0x%08X, 0x%08X, 0x%08X) - %s- %s %d\n", 108 IWL_DEBUG_IO("poll_bit(0x%08X, 0x%08X, 0x%08X) - %s- %s %d\n",
109 addr, bits, mask, 109 addr, bits, mask,
110 unlikely(ret == -ETIMEDOUT)?"timeout":"", f, l); 110 unlikely(ret == -ETIMEDOUT)?"timeout":"", f, l);
111 return ret; 111 return ret;
112} 112}
113#define iwl4965_poll_bit(priv, addr, bits, mask, timeout) \ 113#define iwl_poll_bit(priv, addr, bits, mask, timeout) \
114 __iwl4965_poll_bit(__FILE__, __LINE__, priv, addr, bits, mask, timeout) 114 __iwl_poll_bit(__FILE__, __LINE__, priv, addr, bits, mask, timeout)
115#else 115#else
116#define iwl4965_poll_bit(p, a, b, m, t) _iwl4965_poll_bit(p, a, b, m, t) 116#define iwl_poll_bit(p, a, b, m, t) _iwl_poll_bit(p, a, b, m, t)
117#endif 117#endif
118 118
119static inline void _iwl4965_set_bit(struct iwl_priv *priv, u32 reg, u32 mask) 119static inline void _iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
120{ 120{
121 _iwl4965_write32(priv, reg, _iwl4965_read32(priv, reg) | mask); 121 _iwl_write32(priv, reg, _iwl_read32(priv, reg) | mask);
122} 122}
123#ifdef CONFIG_IWLWIFI_DEBUG 123#ifdef CONFIG_IWLWIFI_DEBUG
124static inline void __iwl4965_set_bit(const char *f, u32 l, 124static inline void __iwl_set_bit(const char *f, u32 l,
125 struct iwl_priv *priv, u32 reg, u32 mask) 125 struct iwl_priv *priv, u32 reg, u32 mask)
126{ 126{
127 u32 val = _iwl4965_read32(priv, reg) | mask; 127 u32 val = _iwl_read32(priv, reg) | mask;
128 IWL_DEBUG_IO("set_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val); 128 IWL_DEBUG_IO("set_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
129 _iwl4965_write32(priv, reg, val); 129 _iwl_write32(priv, reg, val);
130} 130}
131#define iwl4965_set_bit(p, r, m) __iwl4965_set_bit(__FILE__, __LINE__, p, r, m) 131#define iwl_set_bit(p, r, m) __iwl_set_bit(__FILE__, __LINE__, p, r, m)
132#else 132#else
133#define iwl4965_set_bit(p, r, m) _iwl4965_set_bit(p, r, m) 133#define iwl_set_bit(p, r, m) _iwl_set_bit(p, r, m)
134#endif 134#endif
135 135
136static inline void _iwl4965_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask) 136static inline void _iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
137{ 137{
138 _iwl4965_write32(priv, reg, _iwl4965_read32(priv, reg) & ~mask); 138 _iwl_write32(priv, reg, _iwl_read32(priv, reg) & ~mask);
139} 139}
140#ifdef CONFIG_IWLWIFI_DEBUG 140#ifdef CONFIG_IWLWIFI_DEBUG
141static inline void __iwl4965_clear_bit(const char *f, u32 l, 141static inline void __iwl_clear_bit(const char *f, u32 l,
142 struct iwl_priv *priv, u32 reg, u32 mask) 142 struct iwl_priv *priv, u32 reg, u32 mask)
143{ 143{
144 u32 val = _iwl4965_read32(priv, reg) & ~mask; 144 u32 val = _iwl_read32(priv, reg) & ~mask;
145 IWL_DEBUG_IO("clear_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val); 145 IWL_DEBUG_IO("clear_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
146 _iwl4965_write32(priv, reg, val); 146 _iwl_write32(priv, reg, val);
147} 147}
148#define iwl4965_clear_bit(p, r, m) __iwl4965_clear_bit(__FILE__, __LINE__, p, r, m) 148#define iwl_clear_bit(p, r, m) __iwl_clear_bit(__FILE__, __LINE__, p, r, m)
149#else 149#else
150#define iwl4965_clear_bit(p, r, m) _iwl4965_clear_bit(p, r, m) 150#define iwl_clear_bit(p, r, m) _iwl_clear_bit(p, r, m)
151#endif 151#endif
152 152
153static inline int _iwl4965_grab_nic_access(struct iwl_priv *priv) 153static inline int _iwl_grab_nic_access(struct iwl_priv *priv)
154{ 154{
155 int ret; 155 int ret;
156 u32 gp_ctl; 156 u32 gp_ctl;
@@ -165,7 +165,7 @@ static inline int _iwl4965_grab_nic_access(struct iwl_priv *priv)
165 "wakes up NIC\n"); 165 "wakes up NIC\n");
166 166
167 /* 10 msec allows time for NIC to complete its data save */ 167 /* 10 msec allows time for NIC to complete its data save */
168 gp_ctl = _iwl4965_read32(priv, CSR_GP_CNTRL); 168 gp_ctl = _iwl_read32(priv, CSR_GP_CNTRL);
169 if (gp_ctl & CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY) { 169 if (gp_ctl & CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY) {
170 IWL_DEBUG_RF_KILL("Wait for complete power-down, " 170 IWL_DEBUG_RF_KILL("Wait for complete power-down, "
171 "gpctl = 0x%08x\n", gp_ctl); 171 "gpctl = 0x%08x\n", gp_ctl);
@@ -176,8 +176,8 @@ static inline int _iwl4965_grab_nic_access(struct iwl_priv *priv)
176 } 176 }
177 177
178 /* this bit wakes up the NIC */ 178 /* this bit wakes up the NIC */
179 _iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 179 _iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
180 ret = _iwl4965_poll_bit(priv, CSR_GP_CNTRL, 180 ret = _iwl_poll_bit(priv, CSR_GP_CNTRL,
181 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 181 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
182 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 182 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
183 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 50); 183 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 50);
@@ -193,7 +193,7 @@ static inline int _iwl4965_grab_nic_access(struct iwl_priv *priv)
193} 193}
194 194
195#ifdef CONFIG_IWLWIFI_DEBUG 195#ifdef CONFIG_IWLWIFI_DEBUG
196static inline int __iwl4965_grab_nic_access(const char *f, u32 l, 196static inline int __iwl_grab_nic_access(const char *f, u32 l,
197 struct iwl_priv *priv) 197 struct iwl_priv *priv)
198{ 198{
199 if (atomic_read(&priv->restrict_refcnt)) 199 if (atomic_read(&priv->restrict_refcnt))
@@ -201,98 +201,98 @@ static inline int __iwl4965_grab_nic_access(const char *f, u32 l,
201 "line %d.\n", l); 201 "line %d.\n", l);
202 202
203 IWL_DEBUG_IO("grabbing nic access - %s %d\n", f, l); 203 IWL_DEBUG_IO("grabbing nic access - %s %d\n", f, l);
204 return _iwl4965_grab_nic_access(priv); 204 return _iwl_grab_nic_access(priv);
205} 205}
206#define iwl4965_grab_nic_access(priv) \ 206#define iwl_grab_nic_access(priv) \
207 __iwl4965_grab_nic_access(__FILE__, __LINE__, priv) 207 __iwl_grab_nic_access(__FILE__, __LINE__, priv)
208#else 208#else
209#define iwl4965_grab_nic_access(priv) \ 209#define iwl_grab_nic_access(priv) \
210 _iwl4965_grab_nic_access(priv) 210 _iwl_grab_nic_access(priv)
211#endif 211#endif
212 212
213static inline void _iwl4965_release_nic_access(struct iwl_priv *priv) 213static inline void _iwl_release_nic_access(struct iwl_priv *priv)
214{ 214{
215#ifdef CONFIG_IWLWIFI_DEBUG 215#ifdef CONFIG_IWLWIFI_DEBUG
216 if (atomic_dec_and_test(&priv->restrict_refcnt)) 216 if (atomic_dec_and_test(&priv->restrict_refcnt))
217#endif 217#endif
218 _iwl4965_clear_bit(priv, CSR_GP_CNTRL, 218 _iwl_clear_bit(priv, CSR_GP_CNTRL,
219 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 219 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
220} 220}
221#ifdef CONFIG_IWLWIFI_DEBUG 221#ifdef CONFIG_IWLWIFI_DEBUG
222static inline void __iwl4965_release_nic_access(const char *f, u32 l, 222static inline void __iwl_release_nic_access(const char *f, u32 l,
223 struct iwl_priv *priv) 223 struct iwl_priv *priv)
224{ 224{
225 if (atomic_read(&priv->restrict_refcnt) <= 0) 225 if (atomic_read(&priv->restrict_refcnt) <= 0)
226 IWL_ERROR("Release unheld nic access at line %d.\n", l); 226 IWL_ERROR("Release unheld nic access at line %d.\n", l);
227 227
228 IWL_DEBUG_IO("releasing nic access - %s %d\n", f, l); 228 IWL_DEBUG_IO("releasing nic access - %s %d\n", f, l);
229 _iwl4965_release_nic_access(priv); 229 _iwl_release_nic_access(priv);
230} 230}
231#define iwl4965_release_nic_access(priv) \ 231#define iwl_release_nic_access(priv) \
232 __iwl4965_release_nic_access(__FILE__, __LINE__, priv) 232 __iwl_release_nic_access(__FILE__, __LINE__, priv)
233#else 233#else
234#define iwl4965_release_nic_access(priv) \ 234#define iwl_release_nic_access(priv) \
235 _iwl4965_release_nic_access(priv) 235 _iwl_release_nic_access(priv)
236#endif 236#endif
237 237
238static inline u32 _iwl4965_read_direct32(struct iwl_priv *priv, u32 reg) 238static inline u32 _iwl_read_direct32(struct iwl_priv *priv, u32 reg)
239{ 239{
240 return _iwl4965_read32(priv, reg); 240 return _iwl_read32(priv, reg);
241} 241}
242#ifdef CONFIG_IWLWIFI_DEBUG 242#ifdef CONFIG_IWLWIFI_DEBUG
243static inline u32 __iwl4965_read_direct32(const char *f, u32 l, 243static inline u32 __iwl_read_direct32(const char *f, u32 l,
244 struct iwl_priv *priv, u32 reg) 244 struct iwl_priv *priv, u32 reg)
245{ 245{
246 u32 value = _iwl4965_read_direct32(priv, reg); 246 u32 value = _iwl_read_direct32(priv, reg);
247 if (!atomic_read(&priv->restrict_refcnt)) 247 if (!atomic_read(&priv->restrict_refcnt))
248 IWL_ERROR("Nic access not held from %s %d\n", f, l); 248 IWL_ERROR("Nic access not held from %s %d\n", f, l);
249 IWL_DEBUG_IO("read_direct32(0x%4X) = 0x%08x - %s %d \n", reg, value, 249 IWL_DEBUG_IO("read_direct32(0x%4X) = 0x%08x - %s %d \n", reg, value,
250 f, l); 250 f, l);
251 return value; 251 return value;
252} 252}
253#define iwl4965_read_direct32(priv, reg) \ 253#define iwl_read_direct32(priv, reg) \
254 __iwl4965_read_direct32(__FILE__, __LINE__, priv, reg) 254 __iwl_read_direct32(__FILE__, __LINE__, priv, reg)
255#else 255#else
256#define iwl4965_read_direct32 _iwl4965_read_direct32 256#define iwl_read_direct32 _iwl_read_direct32
257#endif 257#endif
258 258
259static inline void _iwl4965_write_direct32(struct iwl_priv *priv, 259static inline void _iwl_write_direct32(struct iwl_priv *priv,
260 u32 reg, u32 value) 260 u32 reg, u32 value)
261{ 261{
262 _iwl4965_write32(priv, reg, value); 262 _iwl_write32(priv, reg, value);
263} 263}
264#ifdef CONFIG_IWLWIFI_DEBUG 264#ifdef CONFIG_IWLWIFI_DEBUG
265static void __iwl4965_write_direct32(u32 line, 265static void __iwl_write_direct32(u32 line,
266 struct iwl_priv *priv, u32 reg, u32 value) 266 struct iwl_priv *priv, u32 reg, u32 value)
267{ 267{
268 if (!atomic_read(&priv->restrict_refcnt)) 268 if (!atomic_read(&priv->restrict_refcnt))
269 IWL_ERROR("Nic access not held from line %d\n", line); 269 IWL_ERROR("Nic access not held from line %d\n", line);
270 _iwl4965_write_direct32(priv, reg, value); 270 _iwl_write_direct32(priv, reg, value);
271} 271}
272#define iwl4965_write_direct32(priv, reg, value) \ 272#define iwl_write_direct32(priv, reg, value) \
273 __iwl4965_write_direct32(__LINE__, priv, reg, value) 273 __iwl_write_direct32(__LINE__, priv, reg, value)
274#else 274#else
275#define iwl4965_write_direct32 _iwl4965_write_direct32 275#define iwl_write_direct32 _iwl_write_direct32
276#endif 276#endif
277 277
278static inline void iwl4965_write_reg_buf(struct iwl_priv *priv, 278static inline void iwl_write_reg_buf(struct iwl_priv *priv,
279 u32 reg, u32 len, u32 *values) 279 u32 reg, u32 len, u32 *values)
280{ 280{
281 u32 count = sizeof(u32); 281 u32 count = sizeof(u32);
282 282
283 if ((priv != NULL) && (values != NULL)) { 283 if ((priv != NULL) && (values != NULL)) {
284 for (; 0 < len; len -= count, reg += count, values++) 284 for (; 0 < len; len -= count, reg += count, values++)
285 _iwl4965_write_direct32(priv, reg, *values); 285 _iwl_write_direct32(priv, reg, *values);
286 } 286 }
287} 287}
288 288
289static inline int _iwl4965_poll_direct_bit(struct iwl_priv *priv, 289static inline int _iwl_poll_direct_bit(struct iwl_priv *priv,
290 u32 addr, u32 mask, int timeout) 290 u32 addr, u32 mask, int timeout)
291{ 291{
292 int i = 0; 292 int i = 0;
293 293
294 do { 294 do {
295 if ((_iwl4965_read_direct32(priv, addr) & mask) == mask) 295 if ((_iwl_read_direct32(priv, addr) & mask) == mask)
296 return i; 296 return i;
297 mdelay(10); 297 mdelay(10);
298 i += 10; 298 i += 10;
@@ -302,11 +302,11 @@ static inline int _iwl4965_poll_direct_bit(struct iwl_priv *priv,
302} 302}
303 303
304#ifdef CONFIG_IWLWIFI_DEBUG 304#ifdef CONFIG_IWLWIFI_DEBUG
305static inline int __iwl4965_poll_direct_bit(const char *f, u32 l, 305static inline int __iwl_poll_direct_bit(const char *f, u32 l,
306 struct iwl_priv *priv, 306 struct iwl_priv *priv,
307 u32 addr, u32 mask, int timeout) 307 u32 addr, u32 mask, int timeout)
308{ 308{
309 int ret = _iwl4965_poll_direct_bit(priv, addr, mask, timeout); 309 int ret = _iwl_poll_direct_bit(priv, addr, mask, timeout);
310 310
311 if (unlikely(ret == -ETIMEDOUT)) 311 if (unlikely(ret == -ETIMEDOUT))
312 IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) - " 312 IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) - "
@@ -316,111 +316,111 @@ static inline int __iwl4965_poll_direct_bit(const char *f, u32 l,
316 "- %s %d\n", addr, mask, ret, f, l); 316 "- %s %d\n", addr, mask, ret, f, l);
317 return ret; 317 return ret;
318} 318}
319#define iwl4965_poll_direct_bit(priv, addr, mask, timeout) \ 319#define iwl_poll_direct_bit(priv, addr, mask, timeout) \
320 __iwl4965_poll_direct_bit(__FILE__, __LINE__, priv, addr, mask, timeout) 320 __iwl_poll_direct_bit(__FILE__, __LINE__, priv, addr, mask, timeout)
321#else 321#else
322#define iwl4965_poll_direct_bit _iwl4965_poll_direct_bit 322#define iwl_poll_direct_bit _iwl_poll_direct_bit
323#endif 323#endif
324 324
325static inline u32 _iwl4965_read_prph(struct iwl_priv *priv, u32 reg) 325static inline u32 _iwl_read_prph(struct iwl_priv *priv, u32 reg)
326{ 326{
327 _iwl4965_write_direct32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); 327 _iwl_write_direct32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
328 return _iwl4965_read_direct32(priv, HBUS_TARG_PRPH_RDAT); 328 return _iwl_read_direct32(priv, HBUS_TARG_PRPH_RDAT);
329} 329}
330#ifdef CONFIG_IWLWIFI_DEBUG 330#ifdef CONFIG_IWLWIFI_DEBUG
331static inline u32 __iwl4965_read_prph(u32 line, struct iwl_priv *priv, u32 reg) 331static inline u32 __iwl_read_prph(u32 line, struct iwl_priv *priv, u32 reg)
332{ 332{
333 if (!atomic_read(&priv->restrict_refcnt)) 333 if (!atomic_read(&priv->restrict_refcnt))
334 IWL_ERROR("Nic access not held from line %d\n", line); 334 IWL_ERROR("Nic access not held from line %d\n", line);
335 return _iwl4965_read_prph(priv, reg); 335 return _iwl_read_prph(priv, reg);
336} 336}
337 337
338#define iwl4965_read_prph(priv, reg) \ 338#define iwl_read_prph(priv, reg) \
339 __iwl4965_read_prph(__LINE__, priv, reg) 339 __iwl_read_prph(__LINE__, priv, reg)
340#else 340#else
341#define iwl4965_read_prph _iwl4965_read_prph 341#define iwl_read_prph _iwl_read_prph
342#endif 342#endif
343 343
344static inline void _iwl4965_write_prph(struct iwl_priv *priv, 344static inline void _iwl_write_prph(struct iwl_priv *priv,
345 u32 addr, u32 val) 345 u32 addr, u32 val)
346{ 346{
347 _iwl4965_write_direct32(priv, HBUS_TARG_PRPH_WADDR, 347 _iwl_write_direct32(priv, HBUS_TARG_PRPH_WADDR,
348 ((addr & 0x0000FFFF) | (3 << 24))); 348 ((addr & 0x0000FFFF) | (3 << 24)));
349 _iwl4965_write_direct32(priv, HBUS_TARG_PRPH_WDAT, val); 349 _iwl_write_direct32(priv, HBUS_TARG_PRPH_WDAT, val);
350} 350}
351#ifdef CONFIG_IWLWIFI_DEBUG 351#ifdef CONFIG_IWLWIFI_DEBUG
352static inline void __iwl4965_write_prph(u32 line, struct iwl_priv *priv, 352static inline void __iwl_write_prph(u32 line, struct iwl_priv *priv,
353 u32 addr, u32 val) 353 u32 addr, u32 val)
354{ 354{
355 if (!atomic_read(&priv->restrict_refcnt)) 355 if (!atomic_read(&priv->restrict_refcnt))
356 IWL_ERROR("Nic access from line %d\n", line); 356 IWL_ERROR("Nic access from line %d\n", line);
357 _iwl4965_write_prph(priv, addr, val); 357 _iwl_write_prph(priv, addr, val);
358} 358}
359 359
360#define iwl4965_write_prph(priv, addr, val) \ 360#define iwl_write_prph(priv, addr, val) \
361 __iwl4965_write_prph(__LINE__, priv, addr, val); 361 __iwl_write_prph(__LINE__, priv, addr, val);
362#else 362#else
363#define iwl4965_write_prph _iwl4965_write_prph 363#define iwl_write_prph _iwl_write_prph
364#endif 364#endif
365 365
366#define _iwl4965_set_bits_prph(priv, reg, mask) \ 366#define _iwl_set_bits_prph(priv, reg, mask) \
367 _iwl4965_write_prph(priv, reg, (_iwl4965_read_prph(priv, reg) | mask)) 367 _iwl_write_prph(priv, reg, (_iwl_read_prph(priv, reg) | mask))
368#ifdef CONFIG_IWLWIFI_DEBUG 368#ifdef CONFIG_IWLWIFI_DEBUG
369static inline void __iwl4965_set_bits_prph(u32 line, struct iwl_priv *priv, 369static inline void __iwl_set_bits_prph(u32 line, struct iwl_priv *priv,
370 u32 reg, u32 mask) 370 u32 reg, u32 mask)
371{ 371{
372 if (!atomic_read(&priv->restrict_refcnt)) 372 if (!atomic_read(&priv->restrict_refcnt))
373 IWL_ERROR("Nic access not held from line %d\n", line); 373 IWL_ERROR("Nic access not held from line %d\n", line);
374 374
375 _iwl4965_set_bits_prph(priv, reg, mask); 375 _iwl_set_bits_prph(priv, reg, mask);
376} 376}
377#define iwl4965_set_bits_prph(priv, reg, mask) \ 377#define iwl_set_bits_prph(priv, reg, mask) \
378 __iwl4965_set_bits_prph(__LINE__, priv, reg, mask) 378 __iwl_set_bits_prph(__LINE__, priv, reg, mask)
379#else 379#else
380#define iwl4965_set_bits_prph _iwl4965_set_bits_prph 380#define iwl_set_bits_prph _iwl_set_bits_prph
381#endif 381#endif
382 382
383#define _iwl4965_set_bits_mask_prph(priv, reg, bits, mask) \ 383#define _iwl_set_bits_mask_prph(priv, reg, bits, mask) \
384 _iwl4965_write_prph(priv, reg, ((_iwl4965_read_prph(priv, reg) & mask) | bits)) 384 _iwl_write_prph(priv, reg, ((_iwl_read_prph(priv, reg) & mask) | bits))
385 385
386#ifdef CONFIG_IWLWIFI_DEBUG 386#ifdef CONFIG_IWLWIFI_DEBUG
387static inline void __iwl4965_set_bits_mask_prph(u32 line, 387static inline void __iwl_set_bits_mask_prph(u32 line,
388 struct iwl_priv *priv, u32 reg, u32 bits, u32 mask) 388 struct iwl_priv *priv, u32 reg, u32 bits, u32 mask)
389{ 389{
390 if (!atomic_read(&priv->restrict_refcnt)) 390 if (!atomic_read(&priv->restrict_refcnt))
391 IWL_ERROR("Nic access not held from line %d\n", line); 391 IWL_ERROR("Nic access not held from line %d\n", line);
392 _iwl4965_set_bits_mask_prph(priv, reg, bits, mask); 392 _iwl_set_bits_mask_prph(priv, reg, bits, mask);
393} 393}
394#define iwl4965_set_bits_mask_prph(priv, reg, bits, mask) \ 394#define iwl_set_bits_mask_prph(priv, reg, bits, mask) \
395 __iwl4965_set_bits_mask_prph(__LINE__, priv, reg, bits, mask) 395 __iwl_set_bits_mask_prph(__LINE__, priv, reg, bits, mask)
396#else 396#else
397#define iwl4965_set_bits_mask_prph _iwl4965_set_bits_mask_prph 397#define iwl_set_bits_mask_prph _iwl_set_bits_mask_prph
398#endif 398#endif
399 399
400static inline void iwl4965_clear_bits_prph(struct iwl_priv 400static inline void iwl_clear_bits_prph(struct iwl_priv
401 *priv, u32 reg, u32 mask) 401 *priv, u32 reg, u32 mask)
402{ 402{
403 u32 val = _iwl4965_read_prph(priv, reg); 403 u32 val = _iwl_read_prph(priv, reg);
404 _iwl4965_write_prph(priv, reg, (val & ~mask)); 404 _iwl_write_prph(priv, reg, (val & ~mask));
405} 405}
406 406
407static inline u32 iwl4965_read_targ_mem(struct iwl_priv *priv, u32 addr) 407static inline u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
408{ 408{
409 iwl4965_write_direct32(priv, HBUS_TARG_MEM_RADDR, addr); 409 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, addr);
410 return iwl4965_read_direct32(priv, HBUS_TARG_MEM_RDAT); 410 return iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
411} 411}
412 412
413static inline void iwl4965_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val) 413static inline void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
414{ 414{
415 iwl4965_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr); 415 iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
416 iwl4965_write_direct32(priv, HBUS_TARG_MEM_WDAT, val); 416 iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, val);
417} 417}
418 418
419static inline void iwl4965_write_targ_mem_buf(struct iwl_priv *priv, u32 addr, 419static inline void iwl_write_targ_mem_buf(struct iwl_priv *priv, u32 addr,
420 u32 len, u32 *values) 420 u32 len, u32 *values)
421{ 421{
422 iwl4965_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr); 422 iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
423 for (; 0 < len; len -= sizeof(u32), values++) 423 for (; 0 < len; len -= sizeof(u32), values++)
424 iwl4965_write_direct32(priv, HBUS_TARG_MEM_WDAT, *values); 424 iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, *values);
425} 425}
426#endif 426#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-led.c b/drivers/net/wireless/iwlwifi/iwl-led.c
index 6f5424bd365b..d59ad1844e25 100644
--- a/drivers/net/wireless/iwlwifi/iwl-led.c
+++ b/drivers/net/wireless/iwlwifi/iwl-led.c
@@ -40,6 +40,7 @@
40#include <asm/unaligned.h> 40#include <asm/unaligned.h>
41 41
42#include "iwl-4965.h" 42#include "iwl-4965.h"
43#include "iwl-io.h"
43#include "iwl-core.h" 44#include "iwl-core.h"
44#include "iwl-helpers.h" 45#include "iwl-helpers.h"
45 46
@@ -85,9 +86,9 @@ static int iwl_send_led_cmd(struct iwl_priv *priv,
85 }; 86 };
86 u32 reg; 87 u32 reg;
87 88
88 reg = iwl4965_read32(priv, CSR_LED_REG); 89 reg = iwl_read32(priv, CSR_LED_REG);
89 if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) 90 if (reg != (reg & CSR_LED_BSM_CTRL_MSK))
90 iwl4965_write32(priv, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK); 91 iwl_write32(priv, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK);
91 92
92 return iwl_send_cmd(priv, &cmd); 93 return iwl_send_cmd(priv, &cmd);
93} 94}
@@ -126,7 +127,7 @@ static int iwl4965_led_pattern(struct iwl_priv *priv, int led_id,
126static int iwl4965_led_on_reg(struct iwl_priv *priv, int led_id) 127static int iwl4965_led_on_reg(struct iwl_priv *priv, int led_id)
127{ 128{
128 IWL_DEBUG_LED("led on %d\n", led_id); 129 IWL_DEBUG_LED("led on %d\n", led_id);
129 iwl4965_write32(priv, CSR_LED_REG, CSR_LED_REG_TRUN_ON); 130 iwl_write32(priv, CSR_LED_REG, CSR_LED_REG_TRUN_ON);
130 return 0; 131 return 0;
131} 132}
132 133
@@ -150,7 +151,7 @@ int iwl4965_led_off(struct iwl_priv *priv, int led_id)
150static int iwl4965_led_off_reg(struct iwl_priv *priv, int led_id) 151static int iwl4965_led_off_reg(struct iwl_priv *priv, int led_id)
151{ 152{
152 IWL_DEBUG_LED("radio off\n"); 153 IWL_DEBUG_LED("radio off\n");
153 iwl4965_write32(priv, CSR_LED_REG, CSR_LED_REG_TRUN_OFF); 154 iwl_write32(priv, CSR_LED_REG, CSR_LED_REG_TRUN_OFF);
154 return 0; 155 return 0;
155} 156}
156 157
diff --git a/drivers/net/wireless/iwlwifi/iwl4965-base.c b/drivers/net/wireless/iwlwifi/iwl4965-base.c
index a04127a8acf7..9e49e8ce3348 100644
--- a/drivers/net/wireless/iwlwifi/iwl4965-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl4965-base.c
@@ -48,6 +48,7 @@
48#include "iwl-eeprom.h" 48#include "iwl-eeprom.h"
49#include "iwl-core.h" 49#include "iwl-core.h"
50#include "iwl-4965.h" 50#include "iwl-4965.h"
51#include "iwl-io.h"
51#include "iwl-helpers.h" 52#include "iwl-helpers.h"
52 53
53static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv, 54static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv,
@@ -2616,7 +2617,7 @@ static void iwl4965_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
2616 /* FIXME: This is a workaround for AP */ 2617 /* FIXME: This is a workaround for AP */
2617 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { 2618 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
2618 spin_lock_irqsave(&priv->lock, flags); 2619 spin_lock_irqsave(&priv->lock, flags);
2619 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET, 2620 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
2620 CSR_UCODE_SW_BIT_RFKILL); 2621 CSR_UCODE_SW_BIT_RFKILL);
2621 spin_unlock_irqrestore(&priv->lock, flags); 2622 spin_unlock_irqrestore(&priv->lock, flags);
2622 iwl4965_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0); 2623 iwl4965_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
@@ -2626,7 +2627,7 @@ static void iwl4965_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
2626 } 2627 }
2627 2628
2628 spin_lock_irqsave(&priv->lock, flags); 2629 spin_lock_irqsave(&priv->lock, flags);
2629 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 2630 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2630 2631
2631 clear_bit(STATUS_RF_KILL_SW, &priv->status); 2632 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2632 spin_unlock_irqrestore(&priv->lock, flags); 2633 spin_unlock_irqrestore(&priv->lock, flags);
@@ -2635,9 +2636,9 @@ static void iwl4965_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
2635 msleep(10); 2636 msleep(10);
2636 2637
2637 spin_lock_irqsave(&priv->lock, flags); 2638 spin_lock_irqsave(&priv->lock, flags);
2638 iwl4965_read32(priv, CSR_UCODE_DRV_GP1); 2639 iwl_read32(priv, CSR_UCODE_DRV_GP1);
2639 if (!iwl4965_grab_nic_access(priv)) 2640 if (!iwl_grab_nic_access(priv))
2640 iwl4965_release_nic_access(priv); 2641 iwl_release_nic_access(priv);
2641 spin_unlock_irqrestore(&priv->lock, flags); 2642 spin_unlock_irqrestore(&priv->lock, flags);
2642 2643
2643 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { 2644 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
@@ -3514,35 +3515,35 @@ static void iwl4965_rx_card_state_notif(struct iwl_priv *priv,
3514 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | 3515 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3515 RF_CARD_DISABLED)) { 3516 RF_CARD_DISABLED)) {
3516 3517
3517 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET, 3518 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
3518 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 3519 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3519 3520
3520 if (!iwl4965_grab_nic_access(priv)) { 3521 if (!iwl_grab_nic_access(priv)) {
3521 iwl4965_write_direct32( 3522 iwl_write_direct32(
3522 priv, HBUS_TARG_MBX_C, 3523 priv, HBUS_TARG_MBX_C,
3523 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 3524 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3524 3525
3525 iwl4965_release_nic_access(priv); 3526 iwl_release_nic_access(priv);
3526 } 3527 }
3527 3528
3528 if (!(flags & RXON_CARD_DISABLED)) { 3529 if (!(flags & RXON_CARD_DISABLED)) {
3529 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, 3530 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
3530 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 3531 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3531 if (!iwl4965_grab_nic_access(priv)) { 3532 if (!iwl_grab_nic_access(priv)) {
3532 iwl4965_write_direct32( 3533 iwl_write_direct32(
3533 priv, HBUS_TARG_MBX_C, 3534 priv, HBUS_TARG_MBX_C,
3534 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 3535 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3535 3536
3536 iwl4965_release_nic_access(priv); 3537 iwl_release_nic_access(priv);
3537 } 3538 }
3538 } 3539 }
3539 3540
3540 if (flags & RF_CARD_DISABLED) { 3541 if (flags & RF_CARD_DISABLED) {
3541 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET, 3542 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
3542 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 3543 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
3543 iwl4965_read32(priv, CSR_UCODE_DRV_GP1); 3544 iwl_read32(priv, CSR_UCODE_DRV_GP1);
3544 if (!iwl4965_grab_nic_access(priv)) 3545 if (!iwl_grab_nic_access(priv))
3545 iwl4965_release_nic_access(priv); 3546 iwl_release_nic_access(priv);
3546 } 3547 }
3547 } 3548 }
3548 3549
@@ -3756,27 +3757,27 @@ int iwl4965_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl4965_rx_q
3756 3757
3757 /* If power-saving is in use, make sure device is awake */ 3758 /* If power-saving is in use, make sure device is awake */
3758 if (test_bit(STATUS_POWER_PMI, &priv->status)) { 3759 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3759 reg = iwl4965_read32(priv, CSR_UCODE_DRV_GP1); 3760 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
3760 3761
3761 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 3762 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3762 iwl4965_set_bit(priv, CSR_GP_CNTRL, 3763 iwl_set_bit(priv, CSR_GP_CNTRL,
3763 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 3764 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3764 goto exit_unlock; 3765 goto exit_unlock;
3765 } 3766 }
3766 3767
3767 rc = iwl4965_grab_nic_access(priv); 3768 rc = iwl_grab_nic_access(priv);
3768 if (rc) 3769 if (rc)
3769 goto exit_unlock; 3770 goto exit_unlock;
3770 3771
3771 /* Device expects a multiple of 8 */ 3772 /* Device expects a multiple of 8 */
3772 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, 3773 iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
3773 q->write & ~0x7); 3774 q->write & ~0x7);
3774 iwl4965_release_nic_access(priv); 3775 iwl_release_nic_access(priv);
3775 3776
3776 /* Else device is assumed to be awake */ 3777 /* Else device is assumed to be awake */
3777 } else 3778 } else
3778 /* Device expects a multiple of 8 */ 3779 /* Device expects a multiple of 8 */
3779 iwl4965_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); 3780 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
3780 3781
3781 3782
3782 q->need_update = 0; 3783 q->need_update = 0;
@@ -4213,27 +4214,27 @@ static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv,
4213 /* wake up nic if it's powered down ... 4214 /* wake up nic if it's powered down ...
4214 * uCode will wake up, and interrupt us again, so next 4215 * uCode will wake up, and interrupt us again, so next
4215 * time we'll skip this part. */ 4216 * time we'll skip this part. */
4216 reg = iwl4965_read32(priv, CSR_UCODE_DRV_GP1); 4217 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
4217 4218
4218 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 4219 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4219 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); 4220 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
4220 iwl4965_set_bit(priv, CSR_GP_CNTRL, 4221 iwl_set_bit(priv, CSR_GP_CNTRL,
4221 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 4222 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4222 return rc; 4223 return rc;
4223 } 4224 }
4224 4225
4225 /* restore this queue's parameters in nic hardware. */ 4226 /* restore this queue's parameters in nic hardware. */
4226 rc = iwl4965_grab_nic_access(priv); 4227 rc = iwl_grab_nic_access(priv);
4227 if (rc) 4228 if (rc)
4228 return rc; 4229 return rc;
4229 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 4230 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
4230 txq->q.write_ptr | (txq_id << 8)); 4231 txq->q.write_ptr | (txq_id << 8));
4231 iwl4965_release_nic_access(priv); 4232 iwl_release_nic_access(priv);
4232 4233
4233 /* else not in power-save mode, uCode will never sleep when we're 4234 /* else not in power-save mode, uCode will never sleep when we're
4234 * trying to tx (during RFKILL, we're not trying to tx). */ 4235 * trying to tx (during RFKILL, we're not trying to tx). */
4235 } else 4236 } else
4236 iwl4965_write32(priv, HBUS_TARG_WRPTR, 4237 iwl_write32(priv, HBUS_TARG_WRPTR,
4237 txq->q.write_ptr | (txq_id << 8)); 4238 txq->q.write_ptr | (txq_id << 8));
4238 4239
4239 txq->need_update = 0; 4240 txq->need_update = 0;
@@ -4268,7 +4269,7 @@ static void iwl4965_enable_interrupts(struct iwl_priv *priv)
4268{ 4269{
4269 IWL_DEBUG_ISR("Enabling interrupts\n"); 4270 IWL_DEBUG_ISR("Enabling interrupts\n");
4270 set_bit(STATUS_INT_ENABLED, &priv->status); 4271 set_bit(STATUS_INT_ENABLED, &priv->status);
4271 iwl4965_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK); 4272 iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
4272} 4273}
4273 4274
4274static inline void iwl4965_disable_interrupts(struct iwl_priv *priv) 4275static inline void iwl4965_disable_interrupts(struct iwl_priv *priv)
@@ -4276,12 +4277,12 @@ static inline void iwl4965_disable_interrupts(struct iwl_priv *priv)
4276 clear_bit(STATUS_INT_ENABLED, &priv->status); 4277 clear_bit(STATUS_INT_ENABLED, &priv->status);
4277 4278
4278 /* disable interrupts from uCode/NIC to host */ 4279 /* disable interrupts from uCode/NIC to host */
4279 iwl4965_write32(priv, CSR_INT_MASK, 0x00000000); 4280 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
4280 4281
4281 /* acknowledge/clear/reset any interrupts still pending 4282 /* acknowledge/clear/reset any interrupts still pending
4282 * from uCode or flow handler (Rx/Tx DMA) */ 4283 * from uCode or flow handler (Rx/Tx DMA) */
4283 iwl4965_write32(priv, CSR_INT, 0xffffffff); 4284 iwl_write32(priv, CSR_INT, 0xffffffff);
4284 iwl4965_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); 4285 iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
4285 IWL_DEBUG_ISR("Disabled interrupts\n"); 4286 IWL_DEBUG_ISR("Disabled interrupts\n");
4286} 4287}
4287 4288
@@ -4322,28 +4323,28 @@ static void iwl4965_dump_nic_error_log(struct iwl_priv *priv)
4322 return; 4323 return;
4323 } 4324 }
4324 4325
4325 rc = iwl4965_grab_nic_access(priv); 4326 rc = iwl_grab_nic_access(priv);
4326 if (rc) { 4327 if (rc) {
4327 IWL_WARNING("Can not read from adapter at this time.\n"); 4328 IWL_WARNING("Can not read from adapter at this time.\n");
4328 return; 4329 return;
4329 } 4330 }
4330 4331
4331 count = iwl4965_read_targ_mem(priv, base); 4332 count = iwl_read_targ_mem(priv, base);
4332 4333
4333 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { 4334 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4334 IWL_ERROR("Start IWL Error Log Dump:\n"); 4335 IWL_ERROR("Start IWL Error Log Dump:\n");
4335 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count); 4336 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
4336 } 4337 }
4337 4338
4338 desc = iwl4965_read_targ_mem(priv, base + 1 * sizeof(u32)); 4339 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
4339 blink1 = iwl4965_read_targ_mem(priv, base + 3 * sizeof(u32)); 4340 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
4340 blink2 = iwl4965_read_targ_mem(priv, base + 4 * sizeof(u32)); 4341 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
4341 ilink1 = iwl4965_read_targ_mem(priv, base + 5 * sizeof(u32)); 4342 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
4342 ilink2 = iwl4965_read_targ_mem(priv, base + 6 * sizeof(u32)); 4343 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
4343 data1 = iwl4965_read_targ_mem(priv, base + 7 * sizeof(u32)); 4344 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
4344 data2 = iwl4965_read_targ_mem(priv, base + 8 * sizeof(u32)); 4345 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
4345 line = iwl4965_read_targ_mem(priv, base + 9 * sizeof(u32)); 4346 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
4346 time = iwl4965_read_targ_mem(priv, base + 11 * sizeof(u32)); 4347 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
4347 4348
4348 IWL_ERROR("Desc Time " 4349 IWL_ERROR("Desc Time "
4349 "data1 data2 line\n"); 4350 "data1 data2 line\n");
@@ -4353,7 +4354,7 @@ static void iwl4965_dump_nic_error_log(struct iwl_priv *priv)
4353 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, 4354 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
4354 ilink1, ilink2); 4355 ilink1, ilink2);
4355 4356
4356 iwl4965_release_nic_access(priv); 4357 iwl_release_nic_access(priv);
4357} 4358}
4358 4359
4359#define EVENT_START_OFFSET (4 * sizeof(u32)) 4360#define EVENT_START_OFFSET (4 * sizeof(u32))
@@ -4361,7 +4362,7 @@ static void iwl4965_dump_nic_error_log(struct iwl_priv *priv)
4361/** 4362/**
4362 * iwl4965_print_event_log - Dump error event log to syslog 4363 * iwl4965_print_event_log - Dump error event log to syslog
4363 * 4364 *
4364 * NOTE: Must be called with iwl4965_grab_nic_access() already obtained! 4365 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
4365 */ 4366 */
4366static void iwl4965_print_event_log(struct iwl_priv *priv, u32 start_idx, 4367static void iwl4965_print_event_log(struct iwl_priv *priv, u32 start_idx,
4367 u32 num_events, u32 mode) 4368 u32 num_events, u32 mode)
@@ -4387,14 +4388,14 @@ static void iwl4965_print_event_log(struct iwl_priv *priv, u32 start_idx,
4387 /* "time" is actually "data" for mode 0 (no timestamp). 4388 /* "time" is actually "data" for mode 0 (no timestamp).
4388 * place event id # at far right for easier visual parsing. */ 4389 * place event id # at far right for easier visual parsing. */
4389 for (i = 0; i < num_events; i++) { 4390 for (i = 0; i < num_events; i++) {
4390 ev = iwl4965_read_targ_mem(priv, ptr); 4391 ev = iwl_read_targ_mem(priv, ptr);
4391 ptr += sizeof(u32); 4392 ptr += sizeof(u32);
4392 time = iwl4965_read_targ_mem(priv, ptr); 4393 time = iwl_read_targ_mem(priv, ptr);
4393 ptr += sizeof(u32); 4394 ptr += sizeof(u32);
4394 if (mode == 0) 4395 if (mode == 0)
4395 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */ 4396 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4396 else { 4397 else {
4397 data = iwl4965_read_targ_mem(priv, ptr); 4398 data = iwl_read_targ_mem(priv, ptr);
4398 ptr += sizeof(u32); 4399 ptr += sizeof(u32);
4399 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev); 4400 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4400 } 4401 }
@@ -4417,24 +4418,24 @@ static void iwl4965_dump_nic_event_log(struct iwl_priv *priv)
4417 return; 4418 return;
4418 } 4419 }
4419 4420
4420 rc = iwl4965_grab_nic_access(priv); 4421 rc = iwl_grab_nic_access(priv);
4421 if (rc) { 4422 if (rc) {
4422 IWL_WARNING("Can not read from adapter at this time.\n"); 4423 IWL_WARNING("Can not read from adapter at this time.\n");
4423 return; 4424 return;
4424 } 4425 }
4425 4426
4426 /* event log header */ 4427 /* event log header */
4427 capacity = iwl4965_read_targ_mem(priv, base); 4428 capacity = iwl_read_targ_mem(priv, base);
4428 mode = iwl4965_read_targ_mem(priv, base + (1 * sizeof(u32))); 4429 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
4429 num_wraps = iwl4965_read_targ_mem(priv, base + (2 * sizeof(u32))); 4430 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
4430 next_entry = iwl4965_read_targ_mem(priv, base + (3 * sizeof(u32))); 4431 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
4431 4432
4432 size = num_wraps ? capacity : next_entry; 4433 size = num_wraps ? capacity : next_entry;
4433 4434
4434 /* bail out if nothing in log */ 4435 /* bail out if nothing in log */
4435 if (size == 0) { 4436 if (size == 0) {
4436 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); 4437 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
4437 iwl4965_release_nic_access(priv); 4438 iwl_release_nic_access(priv);
4438 return; 4439 return;
4439 } 4440 }
4440 4441
@@ -4450,7 +4451,7 @@ static void iwl4965_dump_nic_event_log(struct iwl_priv *priv)
4450 /* (then/else) start at top of log */ 4451 /* (then/else) start at top of log */
4451 iwl4965_print_event_log(priv, 0, next_entry, mode); 4452 iwl4965_print_event_log(priv, 0, next_entry, mode);
4452 4453
4453 iwl4965_release_nic_access(priv); 4454 iwl_release_nic_access(priv);
4454} 4455}
4455 4456
4456/** 4457/**
@@ -4522,19 +4523,19 @@ static void iwl4965_irq_tasklet(struct iwl_priv *priv)
4522 /* Ack/clear/reset pending uCode interrupts. 4523 /* Ack/clear/reset pending uCode interrupts.
4523 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 4524 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4524 * and will clear only when CSR_FH_INT_STATUS gets cleared. */ 4525 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
4525 inta = iwl4965_read32(priv, CSR_INT); 4526 inta = iwl_read32(priv, CSR_INT);
4526 iwl4965_write32(priv, CSR_INT, inta); 4527 iwl_write32(priv, CSR_INT, inta);
4527 4528
4528 /* Ack/clear/reset pending flow-handler (DMA) interrupts. 4529 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4529 * Any new interrupts that happen after this, either while we're 4530 * Any new interrupts that happen after this, either while we're
4530 * in this tasklet, or later, will show up in next ISR/tasklet. */ 4531 * in this tasklet, or later, will show up in next ISR/tasklet. */
4531 inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS); 4532 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
4532 iwl4965_write32(priv, CSR_FH_INT_STATUS, inta_fh); 4533 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
4533 4534
4534#ifdef CONFIG_IWLWIFI_DEBUG 4535#ifdef CONFIG_IWLWIFI_DEBUG
4535 if (iwl_debug_level & IWL_DL_ISR) { 4536 if (iwl_debug_level & IWL_DL_ISR) {
4536 /* just for debug */ 4537 /* just for debug */
4537 inta_mask = iwl4965_read32(priv, CSR_INT_MASK); 4538 inta_mask = iwl_read32(priv, CSR_INT_MASK);
4538 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", 4539 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4539 inta, inta_mask, inta_fh); 4540 inta, inta_mask, inta_fh);
4540 } 4541 }
@@ -4583,7 +4584,7 @@ static void iwl4965_irq_tasklet(struct iwl_priv *priv)
4583 /* HW RF KILL switch toggled */ 4584 /* HW RF KILL switch toggled */
4584 if (inta & CSR_INT_BIT_RF_KILL) { 4585 if (inta & CSR_INT_BIT_RF_KILL) {
4585 int hw_rf_kill = 0; 4586 int hw_rf_kill = 0;
4586 if (!(iwl4965_read32(priv, CSR_GP_CNTRL) & 4587 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
4587 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) 4588 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4588 hw_rf_kill = 1; 4589 hw_rf_kill = 1;
4589 4590
@@ -4658,9 +4659,9 @@ static void iwl4965_irq_tasklet(struct iwl_priv *priv)
4658 4659
4659#ifdef CONFIG_IWLWIFI_DEBUG 4660#ifdef CONFIG_IWLWIFI_DEBUG
4660 if (iwl_debug_level & (IWL_DL_ISR)) { 4661 if (iwl_debug_level & (IWL_DL_ISR)) {
4661 inta = iwl4965_read32(priv, CSR_INT); 4662 inta = iwl_read32(priv, CSR_INT);
4662 inta_mask = iwl4965_read32(priv, CSR_INT_MASK); 4663 inta_mask = iwl_read32(priv, CSR_INT_MASK);
4663 inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS); 4664 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
4664 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " 4665 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4665 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); 4666 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4666 } 4667 }
@@ -4682,12 +4683,12 @@ static irqreturn_t iwl4965_isr(int irq, void *data)
4682 * back-to-back ISRs and sporadic interrupts from our NIC. 4683 * back-to-back ISRs and sporadic interrupts from our NIC.
4683 * If we have something to service, the tasklet will re-enable ints. 4684 * If we have something to service, the tasklet will re-enable ints.
4684 * If we *don't* have something, we'll re-enable before leaving here. */ 4685 * If we *don't* have something, we'll re-enable before leaving here. */
4685 inta_mask = iwl4965_read32(priv, CSR_INT_MASK); /* just for debug */ 4686 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
4686 iwl4965_write32(priv, CSR_INT_MASK, 0x00000000); 4687 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
4687 4688
4688 /* Discover which interrupts are active/pending */ 4689 /* Discover which interrupts are active/pending */
4689 inta = iwl4965_read32(priv, CSR_INT); 4690 inta = iwl_read32(priv, CSR_INT);
4690 inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS); 4691 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
4691 4692
4692 /* Ignore interrupt if there's nothing in NIC to service. 4693 /* Ignore interrupt if there's nothing in NIC to service.
4693 * This may be due to IRQ shared with another device, 4694 * This may be due to IRQ shared with another device,
@@ -5054,18 +5055,18 @@ static int iwl4965_verify_inst_full(struct iwl_priv *priv, __le32 *image,
5054 5055
5055 IWL_DEBUG_INFO("ucode inst image size is %u\n", len); 5056 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5056 5057
5057 rc = iwl4965_grab_nic_access(priv); 5058 rc = iwl_grab_nic_access(priv);
5058 if (rc) 5059 if (rc)
5059 return rc; 5060 return rc;
5060 5061
5061 iwl4965_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); 5062 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
5062 5063
5063 errcnt = 0; 5064 errcnt = 0;
5064 for (; len > 0; len -= sizeof(u32), image++) { 5065 for (; len > 0; len -= sizeof(u32), image++) {
5065 /* read data comes through single port, auto-incr addr */ 5066 /* read data comes through single port, auto-incr addr */
5066 /* NOTE: Use the debugless read so we don't flood kernel log 5067 /* NOTE: Use the debugless read so we don't flood kernel log
5067 * if IWL_DL_IO is set */ 5068 * if IWL_DL_IO is set */
5068 val = _iwl4965_read_direct32(priv, HBUS_TARG_MEM_RDAT); 5069 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
5069 if (val != le32_to_cpu(*image)) { 5070 if (val != le32_to_cpu(*image)) {
5070 IWL_ERROR("uCode INST section is invalid at " 5071 IWL_ERROR("uCode INST section is invalid at "
5071 "offset 0x%x, is 0x%x, s/b 0x%x\n", 5072 "offset 0x%x, is 0x%x, s/b 0x%x\n",
@@ -5077,7 +5078,7 @@ static int iwl4965_verify_inst_full(struct iwl_priv *priv, __le32 *image,
5077 } 5078 }
5078 } 5079 }
5079 5080
5080 iwl4965_release_nic_access(priv); 5081 iwl_release_nic_access(priv);
5081 5082
5082 if (!errcnt) 5083 if (!errcnt)
5083 IWL_DEBUG_INFO 5084 IWL_DEBUG_INFO
@@ -5101,7 +5102,7 @@ static int iwl4965_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32
5101 5102
5102 IWL_DEBUG_INFO("ucode inst image size is %u\n", len); 5103 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5103 5104
5104 rc = iwl4965_grab_nic_access(priv); 5105 rc = iwl_grab_nic_access(priv);
5105 if (rc) 5106 if (rc)
5106 return rc; 5107 return rc;
5107 5108
@@ -5109,9 +5110,9 @@ static int iwl4965_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32
5109 /* read data comes through single port, auto-incr addr */ 5110 /* read data comes through single port, auto-incr addr */
5110 /* NOTE: Use the debugless read so we don't flood kernel log 5111 /* NOTE: Use the debugless read so we don't flood kernel log
5111 * if IWL_DL_IO is set */ 5112 * if IWL_DL_IO is set */
5112 iwl4965_write_direct32(priv, HBUS_TARG_MEM_RADDR, 5113 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
5113 i + RTC_INST_LOWER_BOUND); 5114 i + RTC_INST_LOWER_BOUND);
5114 val = _iwl4965_read_direct32(priv, HBUS_TARG_MEM_RDAT); 5115 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
5115 if (val != le32_to_cpu(*image)) { 5116 if (val != le32_to_cpu(*image)) {
5116#if 0 /* Enable this if you want to see details */ 5117#if 0 /* Enable this if you want to see details */
5117 IWL_ERROR("uCode INST section is invalid at " 5118 IWL_ERROR("uCode INST section is invalid at "
@@ -5125,7 +5126,7 @@ static int iwl4965_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32
5125 } 5126 }
5126 } 5127 }
5127 5128
5128 iwl4965_release_nic_access(priv); 5129 iwl_release_nic_access(priv);
5129 5130
5130 return rc; 5131 return rc;
5131} 5132}
@@ -5192,11 +5193,11 @@ static int iwl4965_verify_bsm(struct iwl_priv *priv)
5192 IWL_DEBUG_INFO("Begin verify bsm\n"); 5193 IWL_DEBUG_INFO("Begin verify bsm\n");
5193 5194
5194 /* verify BSM SRAM contents */ 5195 /* verify BSM SRAM contents */
5195 val = iwl4965_read_prph(priv, BSM_WR_DWCOUNT_REG); 5196 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
5196 for (reg = BSM_SRAM_LOWER_BOUND; 5197 for (reg = BSM_SRAM_LOWER_BOUND;
5197 reg < BSM_SRAM_LOWER_BOUND + len; 5198 reg < BSM_SRAM_LOWER_BOUND + len;
5198 reg += sizeof(u32), image ++) { 5199 reg += sizeof(u32), image ++) {
5199 val = iwl4965_read_prph(priv, reg); 5200 val = iwl_read_prph(priv, reg);
5200 if (val != le32_to_cpu(*image)) { 5201 if (val != le32_to_cpu(*image)) {
5201 IWL_ERROR("BSM uCode verification failed at " 5202 IWL_ERROR("BSM uCode verification failed at "
5202 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", 5203 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
@@ -5273,42 +5274,42 @@ static int iwl4965_load_bsm(struct iwl_priv *priv)
5273 inst_len = priv->ucode_init.len; 5274 inst_len = priv->ucode_init.len;
5274 data_len = priv->ucode_init_data.len; 5275 data_len = priv->ucode_init_data.len;
5275 5276
5276 rc = iwl4965_grab_nic_access(priv); 5277 rc = iwl_grab_nic_access(priv);
5277 if (rc) 5278 if (rc)
5278 return rc; 5279 return rc;
5279 5280
5280 iwl4965_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); 5281 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5281 iwl4965_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); 5282 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5282 iwl4965_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); 5283 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5283 iwl4965_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); 5284 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
5284 5285
5285 /* Fill BSM memory with bootstrap instructions */ 5286 /* Fill BSM memory with bootstrap instructions */
5286 for (reg_offset = BSM_SRAM_LOWER_BOUND; 5287 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5287 reg_offset < BSM_SRAM_LOWER_BOUND + len; 5288 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5288 reg_offset += sizeof(u32), image++) 5289 reg_offset += sizeof(u32), image++)
5289 _iwl4965_write_prph(priv, reg_offset, 5290 _iwl_write_prph(priv, reg_offset,
5290 le32_to_cpu(*image)); 5291 le32_to_cpu(*image));
5291 5292
5292 rc = iwl4965_verify_bsm(priv); 5293 rc = iwl4965_verify_bsm(priv);
5293 if (rc) { 5294 if (rc) {
5294 iwl4965_release_nic_access(priv); 5295 iwl_release_nic_access(priv);
5295 return rc; 5296 return rc;
5296 } 5297 }
5297 5298
5298 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ 5299 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
5299 iwl4965_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); 5300 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5300 iwl4965_write_prph(priv, BSM_WR_MEM_DST_REG, 5301 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
5301 RTC_INST_LOWER_BOUND); 5302 RTC_INST_LOWER_BOUND);
5302 iwl4965_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); 5303 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
5303 5304
5304 /* Load bootstrap code into instruction SRAM now, 5305 /* Load bootstrap code into instruction SRAM now,
5305 * to prepare to load "initialize" uCode */ 5306 * to prepare to load "initialize" uCode */
5306 iwl4965_write_prph(priv, BSM_WR_CTRL_REG, 5307 iwl_write_prph(priv, BSM_WR_CTRL_REG,
5307 BSM_WR_CTRL_REG_BIT_START); 5308 BSM_WR_CTRL_REG_BIT_START);
5308 5309
5309 /* Wait for load of bootstrap uCode to finish */ 5310 /* Wait for load of bootstrap uCode to finish */
5310 for (i = 0; i < 100; i++) { 5311 for (i = 0; i < 100; i++) {
5311 done = iwl4965_read_prph(priv, BSM_WR_CTRL_REG); 5312 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
5312 if (!(done & BSM_WR_CTRL_REG_BIT_START)) 5313 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5313 break; 5314 break;
5314 udelay(10); 5315 udelay(10);
@@ -5322,10 +5323,10 @@ static int iwl4965_load_bsm(struct iwl_priv *priv)
5322 5323
5323 /* Enable future boot loads whenever power management unit triggers it 5324 /* Enable future boot loads whenever power management unit triggers it
5324 * (e.g. when powering back up after power-save shutdown) */ 5325 * (e.g. when powering back up after power-save shutdown) */
5325 iwl4965_write_prph(priv, BSM_WR_CTRL_REG, 5326 iwl_write_prph(priv, BSM_WR_CTRL_REG,
5326 BSM_WR_CTRL_REG_BIT_START_EN); 5327 BSM_WR_CTRL_REG_BIT_START_EN);
5327 5328
5328 iwl4965_release_nic_access(priv); 5329 iwl_release_nic_access(priv);
5329 5330
5330 return 0; 5331 return 0;
5331} 5332}
@@ -5333,7 +5334,7 @@ static int iwl4965_load_bsm(struct iwl_priv *priv)
5333static void iwl4965_nic_start(struct iwl_priv *priv) 5334static void iwl4965_nic_start(struct iwl_priv *priv)
5334{ 5335{
5335 /* Remove all resets to allow NIC to operate */ 5336 /* Remove all resets to allow NIC to operate */
5336 iwl4965_write32(priv, CSR_RESET, 0); 5337 iwl_write32(priv, CSR_RESET, 0);
5337} 5338}
5338 5339
5339 5340
@@ -5555,24 +5556,24 @@ static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
5555 pdata = priv->ucode_data_backup.p_addr >> 4; 5556 pdata = priv->ucode_data_backup.p_addr >> 4;
5556 5557
5557 spin_lock_irqsave(&priv->lock, flags); 5558 spin_lock_irqsave(&priv->lock, flags);
5558 rc = iwl4965_grab_nic_access(priv); 5559 rc = iwl_grab_nic_access(priv);
5559 if (rc) { 5560 if (rc) {
5560 spin_unlock_irqrestore(&priv->lock, flags); 5561 spin_unlock_irqrestore(&priv->lock, flags);
5561 return rc; 5562 return rc;
5562 } 5563 }
5563 5564
5564 /* Tell bootstrap uCode where to find image to load */ 5565 /* Tell bootstrap uCode where to find image to load */
5565 iwl4965_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); 5566 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5566 iwl4965_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); 5567 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5567 iwl4965_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, 5568 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
5568 priv->ucode_data.len); 5569 priv->ucode_data.len);
5569 5570
5570 /* Inst bytecount must be last to set up, bit 31 signals uCode 5571 /* Inst bytecount must be last to set up, bit 31 signals uCode
5571 * that all new ptr/size info is in place */ 5572 * that all new ptr/size info is in place */
5572 iwl4965_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, 5573 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
5573 priv->ucode_code.len | BSM_DRAM_INST_LOAD); 5574 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5574 5575
5575 iwl4965_release_nic_access(priv); 5576 iwl_release_nic_access(priv);
5576 5577
5577 spin_unlock_irqrestore(&priv->lock, flags); 5578 spin_unlock_irqrestore(&priv->lock, flags);
5578 5579
@@ -5752,7 +5753,7 @@ static void __iwl4965_down(struct iwl_priv *priv)
5752 clear_bit(STATUS_EXIT_PENDING, &priv->status); 5753 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5753 5754
5754 /* stop and reset the on-board processor */ 5755 /* stop and reset the on-board processor */
5755 iwl4965_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 5756 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
5756 5757
5757 /* tell the device to stop sending interrupts */ 5758 /* tell the device to stop sending interrupts */
5758 iwl4965_disable_interrupts(priv); 5759 iwl4965_disable_interrupts(priv);
@@ -5788,7 +5789,7 @@ static void __iwl4965_down(struct iwl_priv *priv)
5788 STATUS_FW_ERROR; 5789 STATUS_FW_ERROR;
5789 5790
5790 spin_lock_irqsave(&priv->lock, flags); 5791 spin_lock_irqsave(&priv->lock, flags);
5791 iwl4965_clear_bit(priv, CSR_GP_CNTRL, 5792 iwl_clear_bit(priv, CSR_GP_CNTRL,
5792 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 5793 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
5793 spin_unlock_irqrestore(&priv->lock, flags); 5794 spin_unlock_irqrestore(&priv->lock, flags);
5794 5795
@@ -5796,17 +5797,17 @@ static void __iwl4965_down(struct iwl_priv *priv)
5796 iwl4965_hw_rxq_stop(priv); 5797 iwl4965_hw_rxq_stop(priv);
5797 5798
5798 spin_lock_irqsave(&priv->lock, flags); 5799 spin_lock_irqsave(&priv->lock, flags);
5799 if (!iwl4965_grab_nic_access(priv)) { 5800 if (!iwl_grab_nic_access(priv)) {
5800 iwl4965_write_prph(priv, APMG_CLK_DIS_REG, 5801 iwl_write_prph(priv, APMG_CLK_DIS_REG,
5801 APMG_CLK_VAL_DMA_CLK_RQT); 5802 APMG_CLK_VAL_DMA_CLK_RQT);
5802 iwl4965_release_nic_access(priv); 5803 iwl_release_nic_access(priv);
5803 } 5804 }
5804 spin_unlock_irqrestore(&priv->lock, flags); 5805 spin_unlock_irqrestore(&priv->lock, flags);
5805 5806
5806 udelay(5); 5807 udelay(5);
5807 5808
5808 iwl4965_hw_nic_stop_master(priv); 5809 iwl4965_hw_nic_stop_master(priv);
5809 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 5810 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5810 iwl4965_hw_nic_reset(priv); 5811 iwl4965_hw_nic_reset(priv);
5811 5812
5812 exit: 5813 exit:
@@ -5852,7 +5853,7 @@ static int __iwl4965_up(struct iwl_priv *priv)
5852 } 5853 }
5853 5854
5854 /* If platform's RF_KILL switch is NOT set to KILL */ 5855 /* If platform's RF_KILL switch is NOT set to KILL */
5855 if (iwl4965_read32(priv, CSR_GP_CNTRL) & 5856 if (iwl_read32(priv, CSR_GP_CNTRL) &
5856 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 5857 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5857 clear_bit(STATUS_RF_KILL_HW, &priv->status); 5858 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5858 else { 5859 else {
@@ -5863,7 +5864,7 @@ static int __iwl4965_up(struct iwl_priv *priv)
5863 } 5864 }
5864 } 5865 }
5865 5866
5866 iwl4965_write32(priv, CSR_INT, 0xFFFFFFFF); 5867 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5867 5868
5868 rc = iwl4965_hw_nic_init(priv); 5869 rc = iwl4965_hw_nic_init(priv);
5869 if (rc) { 5870 if (rc) {
@@ -5872,17 +5873,17 @@ static int __iwl4965_up(struct iwl_priv *priv)
5872 } 5873 }
5873 5874
5874 /* make sure rfkill handshake bits are cleared */ 5875 /* make sure rfkill handshake bits are cleared */
5875 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5876 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5876 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, 5877 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
5877 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 5878 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5878 5879
5879 /* clear (again), then enable host interrupts */ 5880 /* clear (again), then enable host interrupts */
5880 iwl4965_write32(priv, CSR_INT, 0xFFFFFFFF); 5881 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5881 iwl4965_enable_interrupts(priv); 5882 iwl4965_enable_interrupts(priv);
5882 5883
5883 /* really make sure rfkill handshake bits are cleared */ 5884 /* really make sure rfkill handshake bits are cleared */
5884 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5885 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5885 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5886 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5886 5887
5887 /* Copy original ucode data image from disk into backup cache. 5888 /* Copy original ucode data image from disk into backup cache.
5888 * This will be used to initialize the on-board processor's 5889 * This will be used to initialize the on-board processor's
@@ -8082,11 +8083,11 @@ static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
8082 * 4. Read EEPROM 8083 * 4. Read EEPROM
8083 *****************/ 8084 *****************/
8084 /* nic init */ 8085 /* nic init */
8085 iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS, 8086 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
8086 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 8087 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8087 8088
8088 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 8089 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8089 err = iwl4965_poll_bit(priv, CSR_GP_CNTRL, 8090 err = iwl_poll_bit(priv, CSR_GP_CNTRL,
8090 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 8091 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8091 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 8092 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8092 if (err < 0) { 8093 if (err < 0) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 23:16:22 -0500