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authorJoe Perches <joe@perches.com>2012-01-04 22:40:42 -0500
committerJohn W. Linville <linville@tuxdriver.com>2012-01-24 14:07:40 -0500
commit4c48869f5d6e4ee4a773fd67a01e1b934faa57f8 (patch)
tree878d8c265368820db9dd2e24ec834f213ce31063 /drivers/net/wireless/rtlwifi
parentf30d7507a8116e2099a9135c873411db8c0a3dc6 (diff)
rtlwifi: Convert RTPRINT macro to use ##__VA_ARGS__
Consolidate printks to avoid possible message interleaving and reduce the object size. Remove unnecessary RTPRINT parentheses. Coalesce formats. Align arguments. $ size drivers/net/wireless/rtlwifi/built-in.o* text data bss dec hex filename 590002 55333 127560 772895 bcb1f drivers/net/wireless/rtlwifi/built-in.o.new 594841 55333 129680 779854 be64e drivers/net/wireless/rtlwifi/built-in.o.old Signed-off-by: Joe Perches <joe@perches.com> Acked-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rtlwifi')
-rw-r--r--drivers/net/wireless/rtlwifi/debug.h6
-rw-r--r--drivers/net/wireless/rtlwifi/efuse.c28
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/hw.c74
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/rf.c77
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/hw.c71
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/rf.c65
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/phy.c250
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/rf.c69
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/hw.c85
9 files changed, 355 insertions, 370 deletions
diff --git a/drivers/net/wireless/rtlwifi/debug.h b/drivers/net/wireless/rtlwifi/debug.h
index 8c1396933540..8b51a828effa 100644
--- a/drivers/net/wireless/rtlwifi/debug.h
+++ b/drivers/net/wireless/rtlwifi/debug.h
@@ -175,11 +175,11 @@ do { \
175 } \ 175 } \
176} while (0) 176} while (0)
177 177
178#define RTPRINT(rtlpriv, dbgtype, dbgflag, printstr) \ 178#define RTPRINT(rtlpriv, dbgtype, dbgflag, fmt, ...) \
179do { \ 179do { \
180 if (unlikely(rtlpriv->dbg.dbgp_type[dbgtype] & dbgflag)) { \ 180 if (unlikely(rtlpriv->dbg.dbgp_type[dbgtype] & dbgflag)) { \
181 printk(KERN_DEBUG "%s: ", KBUILD_MODNAME); \ 181 printk(KERN_DEBUG KBUILD_MODNAME ": " fmt, \
182 printk printstr; \ 182 ##__VA_ARGS__); \
183 } \ 183 } \
184} while (0) 184} while (0)
185 185
diff --git a/drivers/net/wireless/rtlwifi/efuse.c b/drivers/net/wireless/rtlwifi/efuse.c
index 2885131cf1a0..a079a31b4ed7 100644
--- a/drivers/net/wireless/rtlwifi/efuse.c
+++ b/drivers/net/wireless/rtlwifi/efuse.c
@@ -280,7 +280,7 @@ void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf)
280 if (*rtemp8 != 0xFF) { 280 if (*rtemp8 != 0xFF) {
281 efuse_utilized++; 281 efuse_utilized++;
282 RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL, 282 RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
283 ("Addr=%d\n", efuse_addr)); 283 "Addr=%d\n", efuse_addr);
284 efuse_addr++; 284 efuse_addr++;
285 } 285 }
286 286
@@ -290,13 +290,13 @@ void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf)
290 if (offset < efuse_max_section) { 290 if (offset < efuse_max_section) {
291 wren = (*rtemp8 & 0x0f); 291 wren = (*rtemp8 & 0x0f);
292 RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL, 292 RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
293 ("offset-%d Worden=%x\n", offset, wren)); 293 "offset-%d Worden=%x\n", offset, wren);
294 294
295 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 295 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
296 if (!(wren & 0x01)) { 296 if (!(wren & 0x01)) {
297 RTPRINT(rtlpriv, FEEPROM, 297 RTPRINT(rtlpriv, FEEPROM,
298 EFUSE_READ_ALL, ("Addr=%d\n", 298 EFUSE_READ_ALL,
299 efuse_addr)); 299 "Addr=%d\n", efuse_addr);
300 300
301 read_efuse_byte(hw, efuse_addr, rtemp8); 301 read_efuse_byte(hw, efuse_addr, rtemp8);
302 efuse_addr++; 302 efuse_addr++;
@@ -308,8 +308,8 @@ void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf)
308 break; 308 break;
309 309
310 RTPRINT(rtlpriv, FEEPROM, 310 RTPRINT(rtlpriv, FEEPROM,
311 EFUSE_READ_ALL, ("Addr=%d\n", 311 EFUSE_READ_ALL,
312 efuse_addr)); 312 "Addr=%d\n", efuse_addr);
313 313
314 read_efuse_byte(hw, efuse_addr, rtemp8); 314 read_efuse_byte(hw, efuse_addr, rtemp8);
315 efuse_addr++; 315 efuse_addr++;
@@ -326,7 +326,7 @@ void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf)
326 } 326 }
327 327
328 RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL, 328 RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
329 ("Addr=%d\n", efuse_addr)); 329 "Addr=%d\n", efuse_addr);
330 read_efuse_byte(hw, efuse_addr, rtemp8); 330 read_efuse_byte(hw, efuse_addr, rtemp8);
331 if (*rtemp8 != 0xFF && (efuse_addr < efuse_len)) { 331 if (*rtemp8 != 0xFF && (efuse_addr < efuse_len)) {
332 efuse_utilized++; 332 efuse_utilized++;
@@ -850,7 +850,7 @@ static void efuse_write_data_case1(struct ieee80211_hw *hw, u16 *efuse_addr,
850 } 850 }
851 } 851 }
852 } 852 }
853 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, ("efuse PG_STATE_HEADER-1\n")); 853 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, "efuse PG_STATE_HEADER-1\n");
854} 854}
855 855
856static void efuse_write_data_case2(struct ieee80211_hw *hw, u16 *efuse_addr, 856static void efuse_write_data_case2(struct ieee80211_hw *hw, u16 *efuse_addr,
@@ -915,7 +915,7 @@ static void efuse_write_data_case2(struct ieee80211_hw *hw, u16 *efuse_addr,
915 } 915 }
916 916
917 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, 917 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
918 ("efuse PG_STATE_HEADER-2\n")); 918 "efuse PG_STATE_HEADER-2\n");
919 } 919 }
920} 920}
921 921
@@ -935,7 +935,7 @@ static int efuse_pg_packet_write(struct ieee80211_hw *hw,
935 if (efuse_get_current_size(hw) >= 935 if (efuse_get_current_size(hw) >=
936 (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES)) { 936 (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES)) {
937 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, 937 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
938 ("efuse_pg_packet_write error\n")); 938 "efuse_pg_packet_write error\n");
939 return false; 939 return false;
940 } 940 }
941 941
@@ -947,7 +947,7 @@ static int efuse_pg_packet_write(struct ieee80211_hw *hw,
947 efuse_word_enable_data_read(word_en, data, target_pkt.data); 947 efuse_word_enable_data_read(word_en, data, target_pkt.data);
948 target_word_cnts = efuse_calculate_word_cnts(target_pkt.word_en); 948 target_word_cnts = efuse_calculate_word_cnts(target_pkt.word_en);
949 949
950 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, ("efuse Power ON\n")); 950 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, "efuse Power ON\n");
951 951
952 while (continual && (efuse_addr < 952 while (continual && (efuse_addr <
953 (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES))) { 953 (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES))) {
@@ -955,7 +955,7 @@ static int efuse_pg_packet_write(struct ieee80211_hw *hw,
955 if (write_state == PG_STATE_HEADER) { 955 if (write_state == PG_STATE_HEADER) {
956 badworden = 0x0F; 956 badworden = 0x0F;
957 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, 957 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
958 ("efuse PG_STATE_HEADER\n")); 958 "efuse PG_STATE_HEADER\n");
959 959
960 if (efuse_one_byte_read(hw, efuse_addr, &efuse_data) && 960 if (efuse_one_byte_read(hw, efuse_addr, &efuse_data) &&
961 (efuse_data != 0xFF)) 961 (efuse_data != 0xFF))
@@ -975,7 +975,7 @@ static int efuse_pg_packet_write(struct ieee80211_hw *hw,
975 975
976 } else if (write_state == PG_STATE_DATA) { 976 } else if (write_state == PG_STATE_DATA) {
977 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, 977 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
978 ("efuse PG_STATE_DATA\n")); 978 "efuse PG_STATE_DATA\n");
979 badworden = 979 badworden =
980 efuse_word_enable_data_write(hw, efuse_addr + 1, 980 efuse_word_enable_data_write(hw, efuse_addr + 1,
981 target_pkt.word_en, 981 target_pkt.word_en,
@@ -998,7 +998,7 @@ static int efuse_pg_packet_write(struct ieee80211_hw *hw,
998 result = false; 998 result = false;
999 } 999 }
1000 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, 1000 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
1001 ("efuse PG_STATE_HEADER-3\n")); 1001 "efuse PG_STATE_HEADER-3\n");
1002 } 1002 }
1003 } 1003 }
1004 } 1004 }
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
index 4aa228fe96e9..2d01673a2087 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
@@ -1362,25 +1362,24 @@ static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1362 for (rf_path = 0; rf_path < 2; rf_path++) 1362 for (rf_path = 0; rf_path < 2; rf_path++)
1363 for (i = 0; i < 3; i++) 1363 for (i = 0; i < 3; i++)
1364 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1364 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1365 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path, 1365 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1366 i, 1366 rf_path, i,
1367 rtlefuse-> 1367 rtlefuse->
1368 eeprom_chnlarea_txpwr_cck[rf_path][i])); 1368 eeprom_chnlarea_txpwr_cck[rf_path][i]);
1369 for (rf_path = 0; rf_path < 2; rf_path++) 1369 for (rf_path = 0; rf_path < 2; rf_path++)
1370 for (i = 0; i < 3; i++) 1370 for (i = 0; i < 3; i++)
1371 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1371 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1372 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1372 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1373 rf_path, i, 1373 rf_path, i,
1374 rtlefuse-> 1374 rtlefuse->
1375 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i])); 1375 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1376 for (rf_path = 0; rf_path < 2; rf_path++) 1376 for (rf_path = 0; rf_path < 2; rf_path++)
1377 for (i = 0; i < 3; i++) 1377 for (i = 0; i < 3; i++)
1378 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1378 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1379 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1379 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1380 rf_path, i, 1380 rf_path, i,
1381 rtlefuse-> 1381 rtlefuse->
1382 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path] 1382 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]);
1383 [i]));
1384 1383
1385 for (rf_path = 0; rf_path < 2; rf_path++) { 1384 for (rf_path = 0; rf_path < 2; rf_path++) {
1386 for (i = 0; i < 14; i++) { 1385 for (i = 0; i < 14; i++) {
@@ -1411,11 +1410,11 @@ static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1411 1410
1412 for (i = 0; i < 14; i++) { 1411 for (i = 0; i < 14; i++) {
1413 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1412 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1414 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = " 1413 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1415 "[0x%x / 0x%x / 0x%x]\n", rf_path, i, 1414 rf_path, i,
1416 rtlefuse->txpwrlevel_cck[rf_path][i], 1415 rtlefuse->txpwrlevel_cck[rf_path][i],
1417 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1416 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1418 rtlefuse->txpwrlevel_ht40_2s[rf_path][i])); 1417 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1419 } 1418 }
1420 } 1419 }
1421 1420
@@ -1452,13 +1451,13 @@ static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1452 } 1451 }
1453 1452
1454 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1453 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1455 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n", 1454 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1456 rf_path, i, 1455 rf_path, i,
1457 rtlefuse->pwrgroup_ht20[rf_path][i])); 1456 rtlefuse->pwrgroup_ht20[rf_path][i]);
1458 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1457 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1459 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n", 1458 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1460 rf_path, i, 1459 rf_path, i,
1461 rtlefuse->pwrgroup_ht40[rf_path][i])); 1460 rtlefuse->pwrgroup_ht40[rf_path][i]);
1462 } 1461 }
1463 } 1462 }
1464 1463
@@ -1497,27 +1496,27 @@ static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1497 1496
1498 for (i = 0; i < 14; i++) 1497 for (i = 0; i < 14; i++)
1499 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1498 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1500 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1499 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1501 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i])); 1500 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1502 for (i = 0; i < 14; i++) 1501 for (i = 0; i < 14; i++)
1503 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1502 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1504 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, 1503 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1505 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i])); 1504 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1506 for (i = 0; i < 14; i++) 1505 for (i = 0; i < 14; i++)
1507 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1506 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1508 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1507 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1509 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i])); 1508 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1510 for (i = 0; i < 14; i++) 1509 for (i = 0; i < 14; i++)
1511 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1510 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1512 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, 1511 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1513 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i])); 1512 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1514 1513
1515 if (!autoload_fail) 1514 if (!autoload_fail)
1516 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 1515 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1517 else 1516 else
1518 rtlefuse->eeprom_regulatory = 0; 1517 rtlefuse->eeprom_regulatory = 0;
1519 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1518 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1520 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory)); 1519 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1521 1520
1522 if (!autoload_fail) { 1521 if (!autoload_fail) {
1523 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 1522 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
@@ -1526,10 +1525,9 @@ static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1526 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 1525 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1527 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 1526 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1528 } 1527 }
1529 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1528 RTPRINT(rtlpriv, FINIT, INIT_TxPower, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1530 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1529 rtlefuse->eeprom_tssi[RF90_PATH_A],
1531 rtlefuse->eeprom_tssi[RF90_PATH_A], 1530 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1532 rtlefuse->eeprom_tssi[RF90_PATH_B]));
1533 1531
1534 if (!autoload_fail) 1532 if (!autoload_fail)
1535 tempval = hwinfo[EEPROM_THERMAL_METER]; 1533 tempval = hwinfo[EEPROM_THERMAL_METER];
@@ -1542,7 +1540,7 @@ static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1542 1540
1543 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1541 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1544 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1542 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1545 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter)); 1543 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1546} 1544}
1547 1545
1548static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw) 1546static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
index 3ba1a4feeb3f..5ef960499a43 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
@@ -123,8 +123,8 @@ void rtl92ce_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
123 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval); 123 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
124 124
125 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 125 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
126 ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, 126 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n",
127 RTXAGC_A_CCK1_MCS32)); 127 tmpval, RTXAGC_A_CCK1_MCS32);
128 128
129 tmpval = tx_agc[RF90_PATH_A] >> 8; 129 tmpval = tx_agc[RF90_PATH_A] >> 8;
130 130
@@ -133,22 +133,22 @@ void rtl92ce_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
133 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); 133 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
134 134
135 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 135 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
136 ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, 136 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n",
137 RTXAGC_B_CCK11_A_CCK2_11)); 137 tmpval, RTXAGC_B_CCK11_A_CCK2_11);
138 138
139 tmpval = tx_agc[RF90_PATH_B] >> 24; 139 tmpval = tx_agc[RF90_PATH_B] >> 24;
140 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval); 140 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
141 141
142 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 142 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
143 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, 143 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n",
144 RTXAGC_B_CCK11_A_CCK2_11)); 144 tmpval, RTXAGC_B_CCK11_A_CCK2_11);
145 145
146 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; 146 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
147 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); 147 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
148 148
149 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 149 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
150 ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, 150 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
151 RTXAGC_B_CCK1_55_MCS32)); 151 tmpval, RTXAGC_B_CCK1_55_MCS32);
152} 152}
153 153
154static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw, 154static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
@@ -171,8 +171,8 @@ static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
171 (powerBase0 << 8) | powerBase0; 171 (powerBase0 << 8) | powerBase0;
172 *(ofdmbase + i) = powerBase0; 172 *(ofdmbase + i) = powerBase0;
173 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 173 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
174 (" [OFDM power base index rf(%c) = 0x%x]\n", 174 " [OFDM power base index rf(%c) = 0x%x]\n",
175 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i))); 175 i == 0 ? 'A' : 'B', *(ofdmbase + i));
176 } 176 }
177 177
178 for (i = 0; i < 2; i++) { 178 for (i = 0; i < 2; i++) {
@@ -187,8 +187,8 @@ static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
187 *(mcsbase + i) = powerBase1; 187 *(mcsbase + i) = powerBase1;
188 188
189 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 189 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
190 (" [MCS power base index rf(%c) = 0x%x]\n", 190 " [MCS power base index rf(%c) = 0x%x]\n",
191 ((i == 0) ? 'A' : 'B'), *(mcsbase + i))); 191 i == 0 ? 'A' : 'B', *(mcsbase + i));
192 } 192 }
193} 193}
194 194
@@ -215,9 +215,8 @@ static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
215 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]); 215 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
216 216
217 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 217 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
218 ("RTK better performance, " 218 "RTK better performance, writeVal(%c) = 0x%x\n",
219 "writeVal(%c) = 0x%x\n", 219 rf == 0 ? 'A' : 'B', writeVal);
220 ((rf == 0) ? 'A' : 'B'), writeVal));
221 break; 220 break;
222 case 1: 221 case 1:
223 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { 222 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
@@ -225,9 +224,8 @@ static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
225 powerBase1[rf]); 224 powerBase1[rf]);
226 225
227 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 226 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
228 ("Realtek regulatory, 40MHz, " 227 "Realtek regulatory, 40MHz, writeVal(%c) = 0x%x\n",
229 "writeVal(%c) = 0x%x\n", 228 rf == 0 ? 'A' : 'B', writeVal);
230 ((rf == 0) ? 'A' : 'B'), writeVal));
231 } else { 229 } else {
232 if (rtlphy->pwrgroup_cnt == 1) 230 if (rtlphy->pwrgroup_cnt == 1)
233 chnlgroup = 0; 231 chnlgroup = 0;
@@ -249,9 +247,8 @@ static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
249 powerBase1[rf]); 247 powerBase1[rf]);
250 248
251 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 249 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
252 ("Realtek regulatory, 20MHz, " 250 "Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n",
253 "writeVal(%c) = 0x%x\n", 251 rf == 0 ? 'A' : 'B', writeVal);
254 ((rf == 0) ? 'A' : 'B'), writeVal));
255 } 252 }
256 break; 253 break;
257 case 2: 254 case 2:
@@ -259,27 +256,24 @@ static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
259 ((index < 2) ? powerBase0[rf] : powerBase1[rf]); 256 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
260 257
261 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 258 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
262 ("Better regulatory, " 259 "Better regulatory, writeVal(%c) = 0x%x\n",
263 "writeVal(%c) = 0x%x\n", 260 rf == 0 ? 'A' : 'B', writeVal);
264 ((rf == 0) ? 'A' : 'B'), writeVal));
265 break; 261 break;
266 case 3: 262 case 3:
267 chnlgroup = 0; 263 chnlgroup = 0;
268 264
269 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { 265 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
270 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 266 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
271 ("customer's limit, 40MHz " 267 "customer's limit, 40MHz rf(%c) = 0x%x\n",
272 "rf(%c) = 0x%x\n", 268 rf == 0 ? 'A' : 'B',
273 ((rf == 0) ? 'A' : 'B'), 269 rtlefuse->pwrgroup_ht40[rf][channel -
274 rtlefuse->pwrgroup_ht40[rf][channel - 270 1]);
275 1]));
276 } else { 271 } else {
277 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 272 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
278 ("customer's limit, 20MHz " 273 "customer's limit, 20MHz rf(%c) = 0x%x\n",
279 "rf(%c) = 0x%x\n", 274 rf == 0 ? 'A' : 'B',
280 ((rf == 0) ? 'A' : 'B'), 275 rtlefuse->pwrgroup_ht20[rf][channel -
281 rtlefuse->pwrgroup_ht20[rf][channel - 276 1]);
282 1]));
283 } 277 }
284 for (i = 0; i < 4; i++) { 278 for (i = 0; i < 4; i++) {
285 pwr_diff_limit[i] = 279 pwr_diff_limit[i] =
@@ -311,15 +305,15 @@ static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
311 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]); 305 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
312 306
313 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 307 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
314 ("Customer's limit rf(%c) = 0x%x\n", 308 "Customer's limit rf(%c) = 0x%x\n",
315 ((rf == 0) ? 'A' : 'B'), customer_limit)); 309 rf == 0 ? 'A' : 'B', customer_limit);
316 310
317 writeVal = customer_limit + 311 writeVal = customer_limit +
318 ((index < 2) ? powerBase0[rf] : powerBase1[rf]); 312 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
319 313
320 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 314 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
321 ("Customer, writeVal rf(%c)= 0x%x\n", 315 "Customer, writeVal rf(%c)= 0x%x\n",
322 ((rf == 0) ? 'A' : 'B'), writeVal)); 316 rf == 0 ? 'A' : 'B', writeVal);
323 break; 317 break;
324 default: 318 default:
325 chnlgroup = 0; 319 chnlgroup = 0;
@@ -329,9 +323,8 @@ static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
329 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]); 323 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
330 324
331 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 325 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
332 ("RTK better performance, writeVal " 326 "RTK better performance, writeVal rf(%c) = 0x%x\n",
333 "rf(%c) = 0x%x\n", 327 rf == 0 ? 'A' : 'B', writeVal);
334 ((rf == 0) ? 'A' : 'B'), writeVal));
335 break; 328 break;
336 } 329 }
337 330
@@ -383,7 +376,7 @@ static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw,
383 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal); 376 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
384 377
385 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 378 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
386 ("Set 0x%x = %08x\n", regoffset, writeVal)); 379 "Set 0x%x = %08x\n", regoffset, writeVal);
387 380
388 if (((get_rf_type(rtlphy) == RF_2T2R) && 381 if (((get_rf_type(rtlphy) == RF_2T2R) &&
389 (regoffset == RTXAGC_A_MCS15_MCS12 || 382 (regoffset == RTXAGC_A_MCS15_MCS12 ||
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
index 80bd17d85935..de1542f14856 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
@@ -162,24 +162,24 @@ static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
162 for (rf_path = 0; rf_path < 2; rf_path++) 162 for (rf_path = 0; rf_path < 2; rf_path++)
163 for (i = 0; i < 3; i++) 163 for (i = 0; i < 3; i++)
164 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 164 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
165 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path, 165 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
166 i, rtlefuse-> 166 rf_path, i,
167 eeprom_chnlarea_txpwr_cck[rf_path][i])); 167 rtlefuse->
168 eeprom_chnlarea_txpwr_cck[rf_path][i]);
168 for (rf_path = 0; rf_path < 2; rf_path++) 169 for (rf_path = 0; rf_path < 2; rf_path++)
169 for (i = 0; i < 3; i++) 170 for (i = 0; i < 3; i++)
170 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 171 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
171 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 172 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
172 rf_path, i, 173 rf_path, i,
173 rtlefuse-> 174 rtlefuse->
174 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i])); 175 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
175 for (rf_path = 0; rf_path < 2; rf_path++) 176 for (rf_path = 0; rf_path < 2; rf_path++)
176 for (i = 0; i < 3; i++) 177 for (i = 0; i < 3; i++)
177 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 178 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
178 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 179 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
179 rf_path, i, 180 rf_path, i,
180 rtlefuse-> 181 rtlefuse->
181 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path] 182 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]);
182 [i]));
183 for (rf_path = 0; rf_path < 2; rf_path++) { 183 for (rf_path = 0; rf_path < 2; rf_path++) {
184 for (i = 0; i < 14; i++) { 184 for (i = 0; i < 14; i++) {
185 index = _rtl92c_get_chnl_group((u8) i); 185 index = _rtl92c_get_chnl_group((u8) i);
@@ -205,11 +205,10 @@ static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
205 } 205 }
206 for (i = 0; i < 14; i++) { 206 for (i = 0; i < 14; i++) {
207 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 207 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
208 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = " 208 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
209 "[0x%x / 0x%x / 0x%x]\n", rf_path, i, 209 rtlefuse->txpwrlevel_cck[rf_path][i],
210 rtlefuse->txpwrlevel_cck[rf_path][i], 210 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
211 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 211 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
212 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
213 } 212 }
214 } 213 }
215 for (i = 0; i < 3; i++) { 214 for (i = 0; i < 3; i++) {
@@ -242,13 +241,13 @@ static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
242 & 0xf0) >> 4); 241 & 0xf0) >> 4);
243 } 242 }
244 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 243 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
245 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n", 244 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
246 rf_path, i, 245 rf_path, i,
247 rtlefuse->pwrgroup_ht20[rf_path][i])); 246 rtlefuse->pwrgroup_ht20[rf_path][i]);
248 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 247 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
249 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n", 248 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
250 rf_path, i, 249 rf_path, i,
251 rtlefuse->pwrgroup_ht40[rf_path][i])); 250 rtlefuse->pwrgroup_ht40[rf_path][i]);
252 } 251 }
253 } 252 }
254 for (i = 0; i < 14; i++) { 253 for (i = 0; i < 14; i++) {
@@ -277,26 +276,26 @@ static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
277 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 276 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
278 for (i = 0; i < 14; i++) 277 for (i = 0; i < 14; i++)
279 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 278 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
280 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, 279 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
281 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i])); 280 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
282 for (i = 0; i < 14; i++) 281 for (i = 0; i < 14; i++)
283 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 282 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
284 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, 283 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
285 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i])); 284 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
286 for (i = 0; i < 14; i++) 285 for (i = 0; i < 14; i++)
287 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 286 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
288 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, 287 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
289 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i])); 288 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
290 for (i = 0; i < 14; i++) 289 for (i = 0; i < 14; i++)
291 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 290 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
292 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, 291 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
293 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i])); 292 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
294 if (!autoload_fail) 293 if (!autoload_fail)
295 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 294 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
296 else 295 else
297 rtlefuse->eeprom_regulatory = 0; 296 rtlefuse->eeprom_regulatory = 0;
298 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 297 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
299 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory)); 298 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
300 if (!autoload_fail) { 299 if (!autoload_fail) {
301 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 300 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
302 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; 301 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
@@ -305,9 +304,9 @@ static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
305 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 304 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
306 } 305 }
307 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 306 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
308 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n", 307 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
309 rtlefuse->eeprom_tssi[RF90_PATH_A], 308 rtlefuse->eeprom_tssi[RF90_PATH_A],
310 rtlefuse->eeprom_tssi[RF90_PATH_B])); 309 rtlefuse->eeprom_tssi[RF90_PATH_B]);
311 if (!autoload_fail) 310 if (!autoload_fail)
312 tempval = hwinfo[EEPROM_THERMAL_METER]; 311 tempval = hwinfo[EEPROM_THERMAL_METER];
313 else 312 else
@@ -320,7 +319,7 @@ static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
320 rtlefuse->apk_thermalmeterignore = true; 319 rtlefuse->apk_thermalmeterignore = true;
321 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 320 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
322 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 321 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
323 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter)); 322 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
324} 323}
325 324
326static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents) 325static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c
index 7b48ee9acb15..e132cb30a309 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c
@@ -140,26 +140,26 @@ void rtl92cu_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
140 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval); 140 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
141 141
142 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 142 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
143 ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, 143 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n",
144 RTXAGC_A_CCK1_MCS32)); 144 tmpval, RTXAGC_A_CCK1_MCS32);
145 145
146 tmpval = tx_agc[RF90_PATH_A] >> 8; 146 tmpval = tx_agc[RF90_PATH_A] >> 8;
147 if (mac->mode == WIRELESS_MODE_B) 147 if (mac->mode == WIRELESS_MODE_B)
148 tmpval = tmpval & 0xff00ffff; 148 tmpval = tmpval & 0xff00ffff;
149 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); 149 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
150 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 150 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
151 ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, 151 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n",
152 RTXAGC_B_CCK11_A_CCK2_11)); 152 tmpval, RTXAGC_B_CCK11_A_CCK2_11);
153 tmpval = tx_agc[RF90_PATH_B] >> 24; 153 tmpval = tx_agc[RF90_PATH_B] >> 24;
154 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval); 154 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
155 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 155 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
156 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, 156 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n",
157 RTXAGC_B_CCK11_A_CCK2_11)); 157 tmpval, RTXAGC_B_CCK11_A_CCK2_11);
158 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; 158 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
159 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); 159 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
160 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 160 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
161 ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, 161 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
162 RTXAGC_B_CCK1_55_MCS32)); 162 tmpval, RTXAGC_B_CCK1_55_MCS32);
163} 163}
164 164
165static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw, 165static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
@@ -181,8 +181,8 @@ static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
181 (powerBase0 << 8) | powerBase0; 181 (powerBase0 << 8) | powerBase0;
182 *(ofdmbase + i) = powerBase0; 182 *(ofdmbase + i) = powerBase0;
183 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 183 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
184 (" [OFDM power base index rf(%c) = 0x%x]\n", 184 " [OFDM power base index rf(%c) = 0x%x]\n",
185 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i))); 185 i == 0 ? 'A' : 'B', *(ofdmbase + i));
186 } 186 }
187 for (i = 0; i < 2; i++) { 187 for (i = 0; i < 2; i++) {
188 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) { 188 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
@@ -194,8 +194,8 @@ static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
194 (powerBase1 << 16) | (powerBase1 << 8) | powerBase1; 194 (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
195 *(mcsbase + i) = powerBase1; 195 *(mcsbase + i) = powerBase1;
196 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 196 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
197 (" [MCS power base index rf(%c) = 0x%x]\n", 197 " [MCS power base index rf(%c) = 0x%x]\n",
198 ((i == 0) ? 'A' : 'B'), *(mcsbase + i))); 198 i == 0 ? 'A' : 'B', *(mcsbase + i));
199 } 199 }
200} 200}
201 201
@@ -219,8 +219,8 @@ static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
219 [chnlgroup][index + (rf ? 8 : 0)] 219 [chnlgroup][index + (rf ? 8 : 0)]
220 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]); 220 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
221 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 221 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
222 ("RTK better performance,writeVal(%c) = 0x%x\n", 222 "RTK better performance,writeVal(%c) = 0x%x\n",
223 ((rf == 0) ? 'A' : 'B'), writeVal)); 223 rf == 0 ? 'A' : 'B', writeVal);
224 break; 224 break;
225 case 1: 225 case 1:
226 if (rtlphy->pwrgroup_cnt == 1) 226 if (rtlphy->pwrgroup_cnt == 1)
@@ -244,32 +244,31 @@ static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
244 ((index < 2) ? powerBase0[rf] : 244 ((index < 2) ? powerBase0[rf] :
245 powerBase1[rf]); 245 powerBase1[rf]);
246 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 246 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
247 ("Realtek regulatory, 20MHz, " 247 "Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n",
248 "writeVal(%c) = 0x%x\n", 248 rf == 0 ? 'A' : 'B', writeVal);
249 ((rf == 0) ? 'A' : 'B'), writeVal));
250 break; 249 break;
251 case 2: 250 case 2:
252 writeVal = ((index < 2) ? powerBase0[rf] : 251 writeVal = ((index < 2) ? powerBase0[rf] :
253 powerBase1[rf]); 252 powerBase1[rf]);
254 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 253 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
255 ("Better regulatory,writeVal(%c) = 0x%x\n", 254 "Better regulatory,writeVal(%c) = 0x%x\n",
256 ((rf == 0) ? 'A' : 'B'), writeVal)); 255 rf == 0 ? 'A' : 'B', writeVal);
257 break; 256 break;
258 case 3: 257 case 3:
259 chnlgroup = 0; 258 chnlgroup = 0;
260 if (rtlphy->current_chan_bw == 259 if (rtlphy->current_chan_bw ==
261 HT_CHANNEL_WIDTH_20_40) { 260 HT_CHANNEL_WIDTH_20_40) {
262 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 261 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
263 ("customer's limit, 40MHzrf(%c) = " 262 "customer's limit, 40MHzrf(%c) = 0x%x\n",
264 "0x%x\n", ((rf == 0) ? 'A' : 'B'), 263 rf == 0 ? 'A' : 'B',
265 rtlefuse->pwrgroup_ht40[rf] 264 rtlefuse->pwrgroup_ht40[rf]
266 [channel - 1])); 265 [channel - 1]);
267 } else { 266 } else {
268 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 267 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
269 ("customer's limit, 20MHz rf(%c) = " 268 "customer's limit, 20MHz rf(%c) = 0x%x\n",
270 "0x%x\n", ((rf == 0) ? 'A' : 'B'), 269 rf == 0 ? 'A' : 'B',
271 rtlefuse->pwrgroup_ht20[rf] 270 rtlefuse->pwrgroup_ht20[rf]
272 [channel - 1])); 271 [channel - 1]);
273 } 272 }
274 for (i = 0; i < 4; i++) { 273 for (i = 0; i < 4; i++) {
275 pwr_diff_limit[i] = 274 pwr_diff_limit[i] =
@@ -297,22 +296,22 @@ static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
297 (pwr_diff_limit[2] << 16) | 296 (pwr_diff_limit[2] << 16) |
298 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]); 297 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
299 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 298 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
300 ("Customer's limit rf(%c) = 0x%x\n", 299 "Customer's limit rf(%c) = 0x%x\n",
301 ((rf == 0) ? 'A' : 'B'), customer_limit)); 300 rf == 0 ? 'A' : 'B', customer_limit);
302 writeVal = customer_limit + ((index < 2) ? 301 writeVal = customer_limit + ((index < 2) ?
303 powerBase0[rf] : powerBase1[rf]); 302 powerBase0[rf] : powerBase1[rf]);
304 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 303 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
305 ("Customer, writeVal rf(%c)= 0x%x\n", 304 "Customer, writeVal rf(%c)= 0x%x\n",
306 ((rf == 0) ? 'A' : 'B'), writeVal)); 305 rf == 0 ? 'A' : 'B', writeVal);
307 break; 306 break;
308 default: 307 default:
309 chnlgroup = 0; 308 chnlgroup = 0;
310 writeVal = rtlphy->mcs_txpwrlevel_origoffset[chnlgroup] 309 writeVal = rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
311 [index + (rf ? 8 : 0)] + ((index < 2) ? 310 [index + (rf ? 8 : 0)] + ((index < 2) ?
312 powerBase0[rf] : powerBase1[rf]); 311 powerBase0[rf] : powerBase1[rf]);
313 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ("RTK better " 312 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
314 "performance, writeValrf(%c) = 0x%x\n", 313 "RTK better performance, writeValrf(%c) = 0x%x\n",
315 ((rf == 0) ? 'A' : 'B'), writeVal)); 314 rf == 0 ? 'A' : 'B', writeVal);
316 break; 315 break;
317 } 316 }
318 if (rtlpriv->dm.dynamic_txhighpower_lvl == 317 if (rtlpriv->dm.dynamic_txhighpower_lvl ==
@@ -365,7 +364,7 @@ static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw,
365 regoffset = regoffset_b[index]; 364 regoffset = regoffset_b[index];
366 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal); 365 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
367 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 366 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
368 ("Set 0x%x = %08x\n", regoffset, writeVal)); 367 "Set 0x%x = %08x\n", regoffset, writeVal);
369 if (((get_rf_type(rtlphy) == RF_2T2R) && 368 if (((get_rf_type(rtlphy) == RF_2T2R) &&
370 (regoffset == RTXAGC_A_MCS15_MCS12 || 369 (regoffset == RTXAGC_A_MCS15_MCS12 ||
371 regoffset == RTXAGC_B_MCS15_MCS12)) || 370 regoffset == RTXAGC_B_MCS15_MCS12)) ||
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
index 82cc052fc98f..c736b9334888 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
@@ -1446,8 +1446,8 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1446 if (rtlhal->current_bandtype == BAND_ON_5G) { 1446 if (rtlhal->current_bandtype == BAND_ON_5G) {
1447 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); 1447 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1448 u4tmp = curveindex_5g[channel - 1]; 1448 u4tmp = curveindex_5g[channel - 1];
1449 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ver 1 set RF-A, 5G, " 1449 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1450 "0x28 = 0x%x !!\n", u4tmp)); 1450 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
1451 for (i = 0; i < RF_CHNL_NUM_5G; i++) { 1451 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1452 if (channel == rf_chnl_5g[i] && channel <= 140) 1452 if (channel == rf_chnl_5g[i] && channel <= 140)
1453 index = 0; 1453 index = 0;
@@ -1545,8 +1545,8 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1545 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1545 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1546 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); 1546 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1547 u4tmp = curveindex_2g[channel - 1]; 1547 u4tmp = curveindex_2g[channel - 1];
1548 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ver 3 set RF-B, 2G, " 1548 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1549 "0x28 = 0x%x !!\n", u4tmp)); 1549 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
1550 if (channel == 1 || channel == 2 || channel == 4 || channel == 9 1550 if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1551 || channel == 10 || channel == 11 || channel == 12) 1551 || channel == 10 || channel == 11 || channel == 12)
1552 index = 0; 1552 index = 0;
@@ -1589,8 +1589,8 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1589 BRFREGOFFSETMASK)); 1589 BRFREGOFFSETMASK));
1590 } 1590 }
1591 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1591 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1592 ("cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 1592 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1593 rf_syn_g4_for_c_cut_2g | (u4tmp << 11))); 1593 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1594 1594
1595 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, 1595 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1596 BRFREGOFFSETMASK, 1596 BRFREGOFFSETMASK,
@@ -1637,9 +1637,9 @@ static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1637 u32 regeac, rege94, rege9c, regea4; 1637 u32 regeac, rege94, rege9c, regea4;
1638 u8 result = 0; 1638 u8 result = 0;
1639 1639
1640 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK!\n")); 1640 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1641 /* path-A IQK setting */ 1641 /* path-A IQK setting */
1642 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n")); 1642 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1643 if (rtlhal->interfaceindex == 0) { 1643 if (rtlhal->interfaceindex == 0) {
1644 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c1f); 1644 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c1f);
1645 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c1f); 1645 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c1f);
@@ -1657,26 +1657,26 @@ static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1657 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x28160206); 1657 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x28160206);
1658 } 1658 }
1659 /* LO calibration setting */ 1659 /* LO calibration setting */
1660 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n")); 1660 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1661 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911); 1661 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1662 /* One shot, path A LOK & IQK */ 1662 /* One shot, path A LOK & IQK */
1663 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); 1663 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1664 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000); 1664 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1665 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000); 1665 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1666 /* delay x ms */ 1666 /* delay x ms */
1667 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1667 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1668 ("Delay %d ms for One shot, path A LOK & IQK.\n", 1668 "Delay %d ms for One shot, path A LOK & IQK\n",
1669 IQK_DELAY_TIME)); 1669 IQK_DELAY_TIME);
1670 mdelay(IQK_DELAY_TIME); 1670 mdelay(IQK_DELAY_TIME);
1671 /* Check failed */ 1671 /* Check failed */
1672 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1672 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1673 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac)); 1673 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1674 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD); 1674 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1675 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe94 = 0x%x\n", rege94)); 1675 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1676 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD); 1676 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1677 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe9c = 0x%x\n", rege9c)); 1677 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1678 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD); 1678 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1679 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regea4)); 1679 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1680 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && 1680 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1681 (((rege9c & 0x03FF0000) >> 16) != 0x42)) 1681 (((rege9c & 0x03FF0000) >> 16) != 0x42))
1682 result |= 0x01; 1682 result |= 0x01;
@@ -1687,7 +1687,7 @@ static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1687 (((regeac & 0x03FF0000) >> 16) != 0x36)) 1687 (((regeac & 0x03FF0000) >> 16) != 0x36))
1688 result |= 0x02; 1688 result |= 0x02;
1689 else 1689 else
1690 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); 1690 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n");
1691 return result; 1691 return result;
1692} 1692}
1693 1693
@@ -1708,9 +1708,9 @@ static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1708 TxOKBit = BIT(31); 1708 TxOKBit = BIT(31);
1709 RxOKBit = BIT(30); 1709 RxOKBit = BIT(30);
1710 } 1710 }
1711 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK!\n")); 1711 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1712 /* path-A IQK setting */ 1712 /* path-A IQK setting */
1713 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n")); 1713 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1714 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f); 1714 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1715 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f); 1715 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1716 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140307); 1716 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140307);
@@ -1723,7 +1723,7 @@ static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1723 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68110000); 1723 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68110000);
1724 } 1724 }
1725 /* LO calibration setting */ 1725 /* LO calibration setting */
1726 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n")); 1726 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1727 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911); 1727 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1728 /* path-A PA on */ 1728 /* path-A PA on */
1729 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x07000f60); 1729 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x07000f60);
@@ -1731,29 +1731,29 @@ static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1731 for (i = 0; i < retrycount; i++) { 1731 for (i = 0; i < retrycount; i++) {
1732 /* One shot, path A LOK & IQK */ 1732 /* One shot, path A LOK & IQK */
1733 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1733 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1734 ("One shot, path A LOK & IQK!\n")); 1734 "One shot, path A LOK & IQK!\n");
1735 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000); 1735 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1736 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000); 1736 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1737 /* delay x ms */ 1737 /* delay x ms */
1738 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1738 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1739 ("Delay %d ms for One shot, path A LOK & IQK.\n", 1739 "Delay %d ms for One shot, path A LOK & IQK.\n",
1740 IQK_DELAY_TIME)); 1740 IQK_DELAY_TIME);
1741 mdelay(IQK_DELAY_TIME * 10); 1741 mdelay(IQK_DELAY_TIME * 10);
1742 /* Check failed */ 1742 /* Check failed */
1743 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1743 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1744 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac)); 1744 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1745 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD); 1745 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1746 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe94 = 0x%x\n", rege94)); 1746 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1747 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD); 1747 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1748 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe9c = 0x%x\n", rege9c)); 1748 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1749 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD); 1749 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1750 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regea4)); 1750 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1751 if (!(regeac & TxOKBit) && 1751 if (!(regeac & TxOKBit) &&
1752 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { 1752 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1753 result |= 0x01; 1753 result |= 0x01;
1754 } else { /* if Tx not OK, ignore Rx */ 1754 } else { /* if Tx not OK, ignore Rx */
1755 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1755 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1756 ("Path A Tx IQK fail!!\n")); 1756 "Path A Tx IQK fail!!\n");
1757 continue; 1757 continue;
1758 } 1758 }
1759 1759
@@ -1764,7 +1764,7 @@ static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1764 break; 1764 break;
1765 } else { 1765 } else {
1766 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1766 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1767 ("Path A Rx IQK fail!!\n")); 1767 "Path A Rx IQK fail!!\n");
1768 } 1768 }
1769 } 1769 }
1770 /* path A PA off */ 1770 /* path A PA off */
@@ -1782,27 +1782,26 @@ static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1782 u32 regeac, regeb4, regebc, regec4, regecc; 1782 u32 regeac, regeb4, regebc, regec4, regecc;
1783 u8 result = 0; 1783 u8 result = 0;
1784 1784
1785 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQK!\n")); 1785 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1786 /* One shot, path B LOK & IQK */ 1786 /* One shot, path B LOK & IQK */
1787 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); 1787 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1788 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000002); 1788 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000002);
1789 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000000); 1789 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000000);
1790 /* delay x ms */ 1790 /* delay x ms */
1791 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1791 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1792 ("Delay %d ms for One shot, path B LOK & IQK.\n", 1792 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1793 IQK_DELAY_TIME));
1794 mdelay(IQK_DELAY_TIME); 1793 mdelay(IQK_DELAY_TIME);
1795 /* Check failed */ 1794 /* Check failed */
1796 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1795 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1797 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac)); 1796 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1798 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD); 1797 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1799 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regeb4)); 1798 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1800 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD); 1799 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1801 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xebc = 0x%x\n", regebc)); 1800 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1802 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD); 1801 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1803 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regec4)); 1802 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1804 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD); 1803 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1805 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xecc = 0x%x\n", regecc)); 1804 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1806 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && 1805 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1807 (((regebc & 0x03FF0000) >> 16) != 0x42)) 1806 (((regebc & 0x03FF0000) >> 16) != 0x42))
1808 result |= 0x01; 1807 result |= 0x01;
@@ -1812,7 +1811,7 @@ static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1812 (((regecc & 0x03FF0000) >> 16) != 0x36)) 1811 (((regecc & 0x03FF0000) >> 16) != 0x36))
1813 result |= 0x02; 1812 result |= 0x02;
1814 else 1813 else
1815 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n")); 1814 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n");
1816 return result; 1815 return result;
1817} 1816}
1818 1817
@@ -1826,9 +1825,9 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1826 u8 i; 1825 u8 i;
1827 u8 retrycount = 2; 1826 u8 retrycount = 2;
1828 1827
1829 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQK!\n")); 1828 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1830 /* path-A IQK setting */ 1829 /* path-A IQK setting */
1831 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n")); 1830 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1832 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f); 1831 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1833 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f); 1832 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1834 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82110000); 1833 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82110000);
@@ -1841,7 +1840,7 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1841 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68160960); 1840 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68160960);
1842 1841
1843 /* LO calibration setting */ 1842 /* LO calibration setting */
1844 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n")); 1843 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1845 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911); 1844 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1846 1845
1847 /* path-B PA on */ 1846 /* path-B PA on */
@@ -1851,26 +1850,26 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1851 for (i = 0; i < retrycount; i++) { 1850 for (i = 0; i < retrycount; i++) {
1852 /* One shot, path B LOK & IQK */ 1851 /* One shot, path B LOK & IQK */
1853 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1852 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1854 ("One shot, path A LOK & IQK!\n")); 1853 "One shot, path A LOK & IQK!\n");
1855 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xfa000000); 1854 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xfa000000);
1856 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000); 1855 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1857 1856
1858 /* delay x ms */ 1857 /* delay x ms */
1859 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1858 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1860 ("Delay %d ms for One shot, path B LOK & IQK.\n", 10)); 1859 "Delay %d ms for One shot, path B LOK & IQK.\n", 10);
1861 mdelay(IQK_DELAY_TIME * 10); 1860 mdelay(IQK_DELAY_TIME * 10);
1862 1861
1863 /* Check failed */ 1862 /* Check failed */
1864 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1863 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1865 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac)); 1864 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1866 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD); 1865 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1867 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regeb4)); 1866 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1868 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD); 1867 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1869 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xebc = 0x%x\n", regebc)); 1868 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1870 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD); 1869 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1871 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regec4)); 1870 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1872 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD); 1871 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1873 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xecc = 0x%x\n", regecc)); 1872 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1874 if (!(regeac & BIT(31)) && 1873 if (!(regeac & BIT(31)) &&
1875 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) 1874 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1876 result |= 0x01; 1875 result |= 0x01;
@@ -1882,7 +1881,7 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1882 break; 1881 break;
1883 } else { 1882 } else {
1884 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1883 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1885 ("Path B Rx IQK fail!!\n")); 1884 "Path B Rx IQK fail!!\n");
1886 } 1885 }
1887 } 1886 }
1888 1887
@@ -1901,7 +1900,7 @@ static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1901 struct rtl_priv *rtlpriv = rtl_priv(hw); 1900 struct rtl_priv *rtlpriv = rtl_priv(hw);
1902 u32 i; 1901 u32 i;
1903 1902
1904 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Save ADDA parameters.\n")); 1903 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n");
1905 for (i = 0; i < regnum; i++) 1904 for (i = 0; i < regnum; i++)
1906 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], BMASKDWORD); 1905 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], BMASKDWORD);
1907} 1906}
@@ -1912,7 +1911,7 @@ static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1912 struct rtl_priv *rtlpriv = rtl_priv(hw); 1911 struct rtl_priv *rtlpriv = rtl_priv(hw);
1913 u32 i; 1912 u32 i;
1914 1913
1915 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Save MAC parameters.\n")); 1914 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n");
1916 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1915 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1917 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); 1916 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1918 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); 1917 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
@@ -1926,7 +1925,7 @@ static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1926 u32 i; 1925 u32 i;
1927 1926
1928 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1927 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1929 ("Reload ADDA power saving parameters !\n")); 1928 "Reload ADDA power saving parameters !\n");
1930 for (i = 0; i < regnum; i++) 1929 for (i = 0; i < regnum; i++)
1931 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, adda_backup[i]); 1930 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, adda_backup[i]);
1932} 1931}
@@ -1937,7 +1936,7 @@ static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1937 struct rtl_priv *rtlpriv = rtl_priv(hw); 1936 struct rtl_priv *rtlpriv = rtl_priv(hw);
1938 u32 i; 1937 u32 i;
1939 1938
1940 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Reload MAC parameters !\n")); 1939 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n");
1941 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1940 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1942 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); 1941 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1943 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]); 1942 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
@@ -1950,7 +1949,7 @@ static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1950 u32 pathon; 1949 u32 pathon;
1951 u32 i; 1950 u32 i;
1952 1951
1953 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ADDA ON.\n")); 1952 RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n");
1954 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; 1953 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1955 if (patha_on) 1954 if (patha_on)
1956 pathon = rtlpriv->rtlhal.interfaceindex == 0 ? 1955 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
@@ -1965,7 +1964,7 @@ static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1965 struct rtl_priv *rtlpriv = rtl_priv(hw); 1964 struct rtl_priv *rtlpriv = rtl_priv(hw);
1966 u32 i; 1965 u32 i;
1967 1966
1968 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("MAC settings for Calibration.\n")); 1967 RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n");
1969 rtl_write_byte(rtlpriv, macreg[0], 0x3F); 1968 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1970 1969
1971 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) 1970 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
@@ -1977,7 +1976,7 @@ static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1977static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw) 1976static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1978{ 1977{
1979 struct rtl_priv *rtlpriv = rtl_priv(hw); 1978 struct rtl_priv *rtlpriv = rtl_priv(hw);
1980 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A standby mode!\n")); 1979 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n");
1981 1980
1982 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x0); 1981 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x0);
1983 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 0x00010000); 1982 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 0x00010000);
@@ -1990,7 +1989,7 @@ static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1990 u32 mode; 1989 u32 mode;
1991 1990
1992 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1991 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1993 ("BB Switch to %s mode!\n", (pi_mode ? "PI" : "SI"))); 1992 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1994 mode = pi_mode ? 0x01000100 : 0x01000000; 1993 mode = pi_mode ? 0x01000100 : 0x01000000;
1995 rtl_set_bbreg(hw, 0x820, BMASKDWORD, mode); 1994 rtl_set_bbreg(hw, 0x820, BMASKDWORD, mode);
1996 rtl_set_bbreg(hw, 0x828, BMASKDWORD, mode); 1995 rtl_set_bbreg(hw, 0x828, BMASKDWORD, mode);
@@ -2022,12 +2021,12 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2022 const u32 retrycount = 2; 2021 const u32 retrycount = 2;
2023 u32 bbvalue; 2022 u32 bbvalue;
2024 2023
2025 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK for 2.4G :Start!!!\n")); 2024 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n");
2026 if (t == 0) { 2025 if (t == 0) {
2027 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD); 2026 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
2028 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("==>0x%08x\n", bbvalue)); 2027 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
2029 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQ Calibration for %s\n", 2028 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
2030 (is2t ? "2T2R" : "1T1R"))); 2029 is2t ? "2T2R" : "1T1R");
2031 2030
2032 /* Save ADDA parameters, turn Path A ADDA on */ 2031 /* Save ADDA parameters, turn Path A ADDA on */
2033 _rtl92d_phy_save_adda_registers(hw, adda_reg, 2032 _rtl92d_phy_save_adda_registers(hw, adda_reg,
@@ -2065,7 +2064,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2065 if (is2t) 2064 if (is2t)
2066 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000); 2065 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2067 /* IQ calibration setting */ 2066 /* IQ calibration setting */
2068 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK setting!\n")); 2067 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
2069 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000); 2068 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2070 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x01007c00); 2069 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x01007c00);
2071 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800); 2070 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
@@ -2073,7 +2072,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2073 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t); 2072 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
2074 if (patha_ok == 0x03) { 2073 if (patha_ok == 0x03) {
2075 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2074 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2076 ("Path A IQK Success!!\n")); 2075 "Path A IQK Success!!\n");
2077 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 2076 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2078 0x3FF0000) >> 16; 2077 0x3FF0000) >> 16;
2079 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) & 2078 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
@@ -2086,7 +2085,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2086 } else if (i == (retrycount - 1) && patha_ok == 0x01) { 2085 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
2087 /* Tx IQK OK */ 2086 /* Tx IQK OK */
2088 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2087 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2089 ("Path A IQK Only Tx Success!!\n")); 2088 "Path A IQK Only Tx Success!!\n");
2090 2089
2091 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 2090 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2092 0x3FF0000) >> 16; 2091 0x3FF0000) >> 16;
@@ -2095,7 +2094,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2095 } 2094 }
2096 } 2095 }
2097 if (0x00 == patha_ok) 2096 if (0x00 == patha_ok)
2098 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK failed!!\n")); 2097 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n");
2099 if (is2t) { 2098 if (is2t) {
2100 _rtl92d_phy_patha_standby(hw); 2099 _rtl92d_phy_patha_standby(hw);
2101 /* Turn Path B ADDA on */ 2100 /* Turn Path B ADDA on */
@@ -2104,7 +2103,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2104 pathb_ok = _rtl92d_phy_pathb_iqk(hw); 2103 pathb_ok = _rtl92d_phy_pathb_iqk(hw);
2105 if (pathb_ok == 0x03) { 2104 if (pathb_ok == 0x03) {
2106 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2105 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2107 ("Path B IQK Success!!\n")); 2106 "Path B IQK Success!!\n");
2108 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 2107 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
2109 BMASKDWORD) & 0x3FF0000) >> 16; 2108 BMASKDWORD) & 0x3FF0000) >> 16;
2110 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 2109 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
@@ -2117,7 +2116,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2117 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 2116 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
2118 /* Tx IQK OK */ 2117 /* Tx IQK OK */
2119 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2118 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2120 ("Path B Only Tx IQK Success!!\n")); 2119 "Path B Only Tx IQK Success!!\n");
2121 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 2120 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
2122 BMASKDWORD) & 0x3FF0000) >> 16; 2121 BMASKDWORD) & 0x3FF0000) >> 16;
2123 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 2122 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
@@ -2126,12 +2125,12 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2126 } 2125 }
2127 if (0x00 == pathb_ok) 2126 if (0x00 == pathb_ok)
2128 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2127 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2129 ("Path B IQK failed!!\n")); 2128 "Path B IQK failed!!\n");
2130 } 2129 }
2131 2130
2132 /* Back to BB mode, load original value */ 2131 /* Back to BB mode, load original value */
2133 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2132 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2134 ("IQK:Back to BB mode, load original value!\n")); 2133 "IQK:Back to BB mode, load original value!\n");
2135 2134
2136 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0); 2135 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2137 if (t != 0) { 2136 if (t != 0) {
@@ -2156,7 +2155,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2156 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x01008c00); 2155 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x01008c00);
2157 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x01008c00); 2156 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x01008c00);
2158 } 2157 }
2159 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("<==\n")); 2158 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
2160} 2159}
2161 2160
2162static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, 2161static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
@@ -2188,13 +2187,13 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2188 /* Note: IQ calibration must be performed after loading 2187 /* Note: IQ calibration must be performed after loading
2189 * PHY_REG.txt , and radio_a, radio_b.txt */ 2188 * PHY_REG.txt , and radio_a, radio_b.txt */
2190 2189
2191 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK for 5G NORMAL:Start!!!\n")); 2190 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n");
2192 mdelay(IQK_DELAY_TIME * 20); 2191 mdelay(IQK_DELAY_TIME * 20);
2193 if (t == 0) { 2192 if (t == 0) {
2194 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD); 2193 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
2195 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("==>0x%08x\n", bbvalue)); 2194 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
2196 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQ Calibration for %s\n", 2195 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
2197 (is2t ? "2T2R" : "1T1R"))); 2196 is2t ? "2T2R" : "1T1R");
2198 /* Save ADDA parameters, turn Path A ADDA on */ 2197 /* Save ADDA parameters, turn Path A ADDA on */
2199 _rtl92d_phy_save_adda_registers(hw, adda_reg, 2198 _rtl92d_phy_save_adda_registers(hw, adda_reg,
2200 rtlphy->adda_backup, 2199 rtlphy->adda_backup,
@@ -2231,13 +2230,13 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2231 if (is2t) 2230 if (is2t)
2232 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000); 2231 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2233 /* IQ calibration setting */ 2232 /* IQ calibration setting */
2234 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK setting!\n")); 2233 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
2235 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000); 2234 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2236 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x10007c00); 2235 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x10007c00);
2237 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800); 2236 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
2238 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t); 2237 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2239 if (patha_ok == 0x03) { 2238 if (patha_ok == 0x03) {
2240 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK Success!!\n")); 2239 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n");
2241 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 2240 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2242 0x3FF0000) >> 16; 2241 0x3FF0000) >> 16;
2243 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) & 2242 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
@@ -2248,14 +2247,14 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2248 0x3FF0000) >> 16; 2247 0x3FF0000) >> 16;
2249 } else if (patha_ok == 0x01) { /* Tx IQK OK */ 2248 } else if (patha_ok == 0x01) { /* Tx IQK OK */
2250 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2249 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2251 ("Path A IQK Only Tx Success!!\n")); 2250 "Path A IQK Only Tx Success!!\n");
2252 2251
2253 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 2252 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2254 0x3FF0000) >> 16; 2253 0x3FF0000) >> 16;
2255 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) & 2254 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2256 0x3FF0000) >> 16; 2255 0x3FF0000) >> 16;
2257 } else { 2256 } else {
2258 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK Fail!!\n")); 2257 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n");
2259 } 2258 }
2260 if (is2t) { 2259 if (is2t) {
2261 /* _rtl92d_phy_patha_standby(hw); */ 2260 /* _rtl92d_phy_patha_standby(hw); */
@@ -2264,7 +2263,7 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2264 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw); 2263 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2265 if (pathb_ok == 0x03) { 2264 if (pathb_ok == 0x03) {
2266 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2265 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2267 ("Path B IQK Success!!\n")); 2266 "Path B IQK Success!!\n");
2268 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) & 2267 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2269 0x3FF0000) >> 16; 2268 0x3FF0000) >> 16;
2270 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) & 2269 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
@@ -2275,20 +2274,20 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2275 0x3FF0000) >> 16; 2274 0x3FF0000) >> 16;
2276 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ 2275 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2277 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2276 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2278 ("Path B Only Tx IQK Success!!\n")); 2277 "Path B Only Tx IQK Success!!\n");
2279 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) & 2278 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2280 0x3FF0000) >> 16; 2279 0x3FF0000) >> 16;
2281 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) & 2280 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2282 0x3FF0000) >> 16; 2281 0x3FF0000) >> 16;
2283 } else { 2282 } else {
2284 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2283 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2285 ("Path B IQK failed!!\n")); 2284 "Path B IQK failed!!\n");
2286 } 2285 }
2287 } 2286 }
2288 2287
2289 /* Back to BB mode, load original value */ 2288 /* Back to BB mode, load original value */
2290 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2289 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2291 ("IQK:Back to BB mode, load original value!\n")); 2290 "IQK:Back to BB mode, load original value!\n");
2292 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0); 2291 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2293 if (t != 0) { 2292 if (t != 0) {
2294 if (is2t) 2293 if (is2t)
@@ -2310,7 +2309,7 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2310 rtlphy->adda_backup, 2309 rtlphy->adda_backup,
2311 IQK_ADDA_REG_NUM); 2310 IQK_ADDA_REG_NUM);
2312 } 2311 }
2313 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("<==\n")); 2312 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
2314} 2313}
2315 2314
2316static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw, 2315static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
@@ -2384,8 +2383,7 @@ static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2384 rtlhal->macphymode == DUALMAC_DUALPHY; 2383 rtlhal->macphymode == DUALMAC_DUALPHY;
2385 2384
2386 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2385 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2387 ("Path A IQ Calibration %s !\n", 2386 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2388 (iqk_ok) ? "Success" : "Failed"));
2389 if (final_candidate == 0xFF) { 2387 if (final_candidate == 0xFF) {
2390 return; 2388 return;
2391 } else if (iqk_ok) { 2389 } else if (iqk_ok) {
@@ -2395,8 +2393,9 @@ static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2395 if ((val_x & 0x00000200) != 0) 2393 if ((val_x & 0x00000200) != 0)
2396 val_x = val_x | 0xFFFFFC00; 2394 val_x = val_x | 0xFFFFFC00;
2397 tx0_a = (val_x * oldval_0) >> 8; 2395 tx0_a = (val_x * oldval_0) >> 8;
2398 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("X = 0x%x, tx0_a = 0x%x," 2396 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2399 " oldval_0 0x%x\n", val_x, tx0_a, oldval_0)); 2397 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2398 val_x, tx0_a, oldval_0);
2400 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a); 2399 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2401 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 2400 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2402 ((val_x * oldval_0 >> 7) & 0x1)); 2401 ((val_x * oldval_0 >> 7) & 0x1));
@@ -2408,8 +2407,9 @@ static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2408 rtlhal->current_bandtype == BAND_ON_5G) 2407 rtlhal->current_bandtype == BAND_ON_5G)
2409 val_y += 3; 2408 val_y += 3;
2410 tx0_c = (val_y * oldval_0) >> 8; 2409 tx0_c = (val_y * oldval_0) >> 8;
2411 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Y = 0x%lx, tx0_c = 0x%lx\n", 2410 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2412 val_y, tx0_c)); 2411 "Y = 0x%lx, tx0_c = 0x%lx\n",
2412 val_y, tx0_c);
2413 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 2413 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2414 ((tx0_c & 0x3C0) >> 6)); 2414 ((tx0_c & 0x3C0) >> 6));
2415 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000, 2415 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
@@ -2417,11 +2417,11 @@ static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2417 if (is2t) 2417 if (is2t)
2418 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), 2418 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2419 ((val_y * oldval_0 >> 7) & 0x1)); 2419 ((val_y * oldval_0 >> 7) & 0x1));
2420 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xC80 = 0x%x\n", 2420 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2421 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 2421 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2422 BMASKDWORD))); 2422 BMASKDWORD));
2423 if (txonly) { 2423 if (txonly) {
2424 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("only Tx OK\n")); 2424 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n");
2425 return; 2425 return;
2426 } 2426 }
2427 reg = result[final_candidate][2]; 2427 reg = result[final_candidate][2];
@@ -2441,8 +2441,8 @@ static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2441 u32 oldval_1, val_x, tx1_a, reg; 2441 u32 oldval_1, val_x, tx1_a, reg;
2442 long val_y, tx1_c; 2442 long val_y, tx1_c;
2443 2443
2444 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n", 2444 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2445 (iqk_ok) ? "Success" : "Failed")); 2445 iqk_ok ? "Success" : "Failed");
2446 if (final_candidate == 0xFF) { 2446 if (final_candidate == 0xFF) {
2447 return; 2447 return;
2448 } else if (iqk_ok) { 2448 } else if (iqk_ok) {
@@ -2452,8 +2452,8 @@ static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2452 if ((val_x & 0x00000200) != 0) 2452 if ((val_x & 0x00000200) != 0)
2453 val_x = val_x | 0xFFFFFC00; 2453 val_x = val_x | 0xFFFFFC00;
2454 tx1_a = (val_x * oldval_1) >> 8; 2454 tx1_a = (val_x * oldval_1) >> 8;
2455 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("X = 0x%x, tx1_a = 0x%x\n", 2455 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2456 val_x, tx1_a)); 2456 val_x, tx1_a);
2457 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a); 2457 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2458 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 2458 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2459 ((val_x * oldval_1 >> 7) & 0x1)); 2459 ((val_x * oldval_1 >> 7) & 0x1));
@@ -2463,8 +2463,8 @@ static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2463 if (rtlhal->current_bandtype == BAND_ON_5G) 2463 if (rtlhal->current_bandtype == BAND_ON_5G)
2464 val_y += 3; 2464 val_y += 3;
2465 tx1_c = (val_y * oldval_1) >> 8; 2465 tx1_c = (val_y * oldval_1) >> 8;
2466 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Y = 0x%lx, tx1_c = 0x%lx\n", 2466 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2467 val_y, tx1_c)); 2467 val_y, tx1_c);
2468 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 2468 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2469 ((tx1_c & 0x3C0) >> 6)); 2469 ((tx1_c & 0x3C0) >> 6));
2470 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000, 2470 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
@@ -2496,7 +2496,7 @@ void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2496 unsigned long flag = 0; 2496 unsigned long flag = 0;
2497 2497
2498 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2498 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2499 ("IQK:Start!!!channel %d\n", rtlphy->current_channel)); 2499 "IQK:Start!!!channel %d\n", rtlphy->current_channel);
2500 for (i = 0; i < 8; i++) { 2500 for (i = 0; i < 8; i++) {
2501 result[0][i] = 0; 2501 result[0][i] = 0;
2502 result[1][i] = 0; 2502 result[1][i] = 0;
@@ -2510,7 +2510,7 @@ void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2510 is23simular = false; 2510 is23simular = false;
2511 is13simular = false; 2511 is13simular = false;
2512 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2512 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2513 ("IQK !!!currentband %d\n", rtlhal->current_bandtype)); 2513 "IQK !!!currentband %d\n", rtlhal->current_bandtype);
2514 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 2514 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2515 for (i = 0; i < 3; i++) { 2515 for (i = 0; i < 3; i++) {
2516 if (rtlhal->current_bandtype == BAND_ON_5G) { 2516 if (rtlhal->current_bandtype == BAND_ON_5G) {
@@ -2562,10 +2562,9 @@ void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2562 regec4 = result[i][6]; 2562 regec4 = result[i][6];
2563 regecc = result[i][7]; 2563 regecc = result[i][7];
2564 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2564 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2565 ("IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx " 2565 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2566 "regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n ",
2567 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 2566 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2568 regecc)); 2567 regecc);
2569 } 2568 }
2570 if (final_candidate != 0xff) { 2569 if (final_candidate != 0xff) {
2571 rtlphy->reg_e94 = rege94 = result[final_candidate][0]; 2570 rtlphy->reg_e94 = rege94 = result[final_candidate][0];
@@ -2577,12 +2576,11 @@ void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2577 regec4 = result[final_candidate][6]; 2576 regec4 = result[final_candidate][6];
2578 regecc = result[final_candidate][7]; 2577 regecc = result[final_candidate][7];
2579 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2578 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2580 ("IQK: final_candidate is %x\n", final_candidate)); 2579 "IQK: final_candidate is %x\n", final_candidate);
2581 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2580 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2582 ("IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx " 2581 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2583 "regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n ",
2584 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 2582 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2585 regecc)); 2583 regecc);
2586 patha_ok = pathb_ok = true; 2584 patha_ok = pathb_ok = true;
2587 } else { 2585 } else {
2588 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */ 2586 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
@@ -2716,8 +2714,8 @@ static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2716 } 2714 }
2717 } 2715 }
2718 smallest_abs_val = 0xffffffff; 2716 smallest_abs_val = 0xffffffff;
2719 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("curveindex[%d] = %x\n", i, 2717 RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",
2720 curveindex[i])); 2718 i, curveindex[i]);
2721 } 2719 }
2722} 2720}
2723 2721
@@ -2733,13 +2731,13 @@ static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2733 bool bneed_powerdown_radio = false; 2731 bool bneed_powerdown_radio = false;
2734 2732
2735 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath); 2733 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
2736 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("band type = %d\n", 2734 RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
2737 rtlpriv->rtlhal.current_bandtype)); 2735 rtlpriv->rtlhal.current_bandtype);
2738 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("channel = %d\n", channel)); 2736 RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel);
2739 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */ 2737 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2740 u4tmp = curveindex_5g[channel-1]; 2738 u4tmp = curveindex_5g[channel-1];
2741 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2739 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2742 ("ver 1 set RF-A, 5G, 0x28 = 0x%ulx !!\n", u4tmp)); 2740 "ver 1 set RF-A, 5G, 0x28 = 0x%ulx !!\n", u4tmp);
2743 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 2741 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2744 rtlpriv->rtlhal.interfaceindex == 1) { 2742 rtlpriv->rtlhal.interfaceindex == 1) {
2745 bneed_powerdown_radio = 2743 bneed_powerdown_radio =
@@ -2758,7 +2756,7 @@ static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2758 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) { 2756 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2759 u4tmp = curveindex_2g[channel-1]; 2757 u4tmp = curveindex_2g[channel-1];
2760 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2758 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2761 ("ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n", u4tmp)); 2759 "ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n", u4tmp);
2762 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 2760 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2763 rtlpriv->rtlhal.interfaceindex == 0) { 2761 rtlpriv->rtlhal.interfaceindex == 0) {
2764 bneed_powerdown_radio = 2762 bneed_powerdown_radio =
@@ -2770,8 +2768,8 @@ static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2770 } 2768 }
2771 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); 2769 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2772 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2770 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2773 ("ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n", 2771 "ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n",
2774 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800))); 2772 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800));
2775 if (bneed_powerdown_radio) 2773 if (bneed_powerdown_radio)
2776 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); 2774 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2777 if (rtlpriv->rtlhal.during_mac0init_radiob) 2775 if (rtlpriv->rtlhal.during_mac0init_radiob)
@@ -2825,20 +2823,20 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2825 RF_SYN_G6, BRFREGOFFSETMASK); 2823 RF_SYN_G6, BRFREGOFFSETMASK);
2826 } 2824 }
2827 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2825 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2828 ("PHY_LCK finish delay for %d ms=2\n", timecount)); 2826 "PHY_LCK finish delay for %d ms=2\n", timecount);
2829 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, BRFREGOFFSETMASK); 2827 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, BRFREGOFFSETMASK);
2830 if (index == 0 && rtlhal->interfaceindex == 0) { 2828 if (index == 0 && rtlhal->interfaceindex == 0) {
2831 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2829 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2832 ("path-A / 5G LCK\n")); 2830 "path-A / 5G LCK\n");
2833 } else { 2831 } else {
2834 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2832 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2835 ("path-B / 2.4G LCK\n")); 2833 "path-B / 2.4G LCK\n");
2836 } 2834 }
2837 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2); 2835 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2);
2838 /* Set LC calibration off */ 2836 /* Set LC calibration off */
2839 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, 2837 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2840 0x08000, 0x0); 2838 0x08000, 0x0);
2841 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("set RF 0x18[15] = 0\n")); 2839 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n");
2842 /* save Curve-counting number */ 2840 /* save Curve-counting number */
2843 for (i = 0; i < CV_CURVE_CNT; i++) { 2841 for (i = 0; i < CV_CURVE_CNT; i++) {
2844 u32 readval = 0, readval2 = 0; 2842 u32 readval = 0, readval2 = 0;
@@ -2888,7 +2886,7 @@ static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2888{ 2886{
2889 struct rtl_priv *rtlpriv = rtl_priv(hw); 2887 struct rtl_priv *rtlpriv = rtl_priv(hw);
2890 2888
2891 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("cosa PHY_LCK ver=2\n")); 2889 RTPRINT(rtlpriv, FINIT, INIT_IQK, "cosa PHY_LCK ver=2\n");
2892 _rtl92d_phy_lc_calibrate_sw(hw, is2t); 2890 _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2893} 2891}
2894 2892
@@ -2906,8 +2904,8 @@ void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2906 2904
2907 rtlphy->lck_inprogress = true; 2905 rtlphy->lck_inprogress = true;
2908 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2906 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2909 ("LCK:Start!!! currentband %x delay %d ms\n", 2907 "LCK:Start!!! currentband %x delay %d ms\n",
2910 rtlhal->current_bandtype, timecount)); 2908 rtlhal->current_bandtype, timecount);
2911 if (IS_92D_SINGLEPHY(rtlhal->version)) { 2909 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2912 _rtl92d_phy_lc_calibrate(hw, true); 2910 _rtl92d_phy_lc_calibrate(hw, true);
2913 } else { 2911 } else {
@@ -2915,7 +2913,7 @@ void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2915 _rtl92d_phy_lc_calibrate(hw, false); 2913 _rtl92d_phy_lc_calibrate(hw, false);
2916 } 2914 }
2917 rtlphy->lck_inprogress = false; 2915 rtlphy->lck_inprogress = false;
2918 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LCK:Finish!!!\n")); 2916 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n");
2919} 2917}
2920 2918
2921void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta) 2919void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/rf.c b/drivers/net/wireless/rtlwifi/rtl8192de/rf.c
index 3bf21c2cf085..2e174f48946b 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/rf.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/rf.c
@@ -127,23 +127,23 @@ void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
127 tmpval = tx_agc[RF90_PATH_A] & 0xff; 127 tmpval = tx_agc[RF90_PATH_A] & 0xff;
128 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, BMASKBYTE1, tmpval); 128 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, BMASKBYTE1, tmpval);
129 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 129 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
130 ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, 130 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n",
131 RTXAGC_A_CCK1_MCS32)); 131 tmpval, RTXAGC_A_CCK1_MCS32);
132 tmpval = tx_agc[RF90_PATH_A] >> 8; 132 tmpval = tx_agc[RF90_PATH_A] >> 8;
133 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); 133 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
134 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 134 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
135 ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, 135 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n",
136 RTXAGC_B_CCK11_A_CCK2_11)); 136 tmpval, RTXAGC_B_CCK11_A_CCK2_11);
137 tmpval = tx_agc[RF90_PATH_B] >> 24; 137 tmpval = tx_agc[RF90_PATH_B] >> 24;
138 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, BMASKBYTE0, tmpval); 138 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, BMASKBYTE0, tmpval);
139 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 139 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
140 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, 140 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n",
141 RTXAGC_B_CCK11_A_CCK2_11)); 141 tmpval, RTXAGC_B_CCK11_A_CCK2_11);
142 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; 142 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
143 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); 143 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
144 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 144 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
145 ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, 145 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
146 RTXAGC_B_CCK1_55_MCS32)); 146 tmpval, RTXAGC_B_CCK1_55_MCS32);
147} 147}
148 148
149static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw, 149static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw,
@@ -165,8 +165,8 @@ static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw,
165 (powerbase0 << 8) | powerbase0; 165 (powerbase0 << 8) | powerbase0;
166 *(ofdmbase + i) = powerbase0; 166 *(ofdmbase + i) = powerbase0;
167 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 167 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
168 (" [OFDM power base index rf(%c) = 0x%x]\n", 168 " [OFDM power base index rf(%c) = 0x%x]\n",
169 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i))); 169 i == 0 ? 'A' : 'B', *(ofdmbase + i));
170 } 170 }
171 171
172 for (i = 0; i < 2; i++) { 172 for (i = 0; i < 2; i++) {
@@ -179,8 +179,8 @@ static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw,
179 (powerbase1 << 8) | powerbase1; 179 (powerbase1 << 8) | powerbase1;
180 *(mcsbase + i) = powerbase1; 180 *(mcsbase + i) = powerbase1;
181 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 181 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
182 (" [MCS power base index rf(%c) = 0x%x]\n", 182 " [MCS power base index rf(%c) = 0x%x]\n",
183 ((i == 0) ? 'A' : 'B'), *(mcsbase + i))); 183 i == 0 ? 'A' : 'B', *(mcsbase + i));
184 } 184 }
185} 185}
186 186
@@ -232,9 +232,9 @@ static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
232 (rf ? 8 : 0)] + ((index < 2) ? 232 (rf ? 8 : 0)] + ((index < 2) ?
233 powerbase0[rf] : 233 powerbase0[rf] :
234 powerbase1[rf]); 234 powerbase1[rf]);
235 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ("RTK better " 235 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
236 "performance, writeval(%c) = 0x%x\n", 236 "RTK better performance, writeval(%c) = 0x%x\n",
237 ((rf == 0) ? 'A' : 'B'), writeval)); 237 rf == 0 ? 'A' : 'B', writeval);
238 break; 238 break;
239 case 1: 239 case 1:
240 if (rtlphy->pwrgroup_cnt == 1) 240 if (rtlphy->pwrgroup_cnt == 1)
@@ -253,33 +253,31 @@ static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
253 powerbase0[rf] : 253 powerbase0[rf] :
254 powerbase1[rf]); 254 powerbase1[rf]);
255 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 255 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
256 ("Realtek regulatory, " 256 "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
257 "20MHz, writeval(%c) = 0x%x\n", 257 rf == 0 ? 'A' : 'B', writeval);
258 ((rf == 0) ? 'A' : 'B'),
259 writeval));
260 } 258 }
261 break; 259 break;
262 case 2: 260 case 2:
263 writeval = ((index < 2) ? powerbase0[rf] : 261 writeval = ((index < 2) ? powerbase0[rf] :
264 powerbase1[rf]); 262 powerbase1[rf]);
265 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ("Better regulatory, " 263 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
266 "writeval(%c) = 0x%x\n", 264 "Better regulatory, writeval(%c) = 0x%x\n",
267 ((rf == 0) ? 'A' : 'B'), writeval)); 265 rf == 0 ? 'A' : 'B', writeval);
268 break; 266 break;
269 case 3: 267 case 3:
270 chnlgroup = 0; 268 chnlgroup = 0;
271 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { 269 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
272 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 270 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
273 ("customer's limit, 40MHz rf(%c) = " 271 "customer's limit, 40MHz rf(%c) = 0x%x\n",
274 "0x%x\n", ((rf == 0) ? 'A' : 'B'), 272 rf == 0 ? 'A' : 'B',
275 rtlefuse->pwrgroup_ht40[rf] 273 rtlefuse->pwrgroup_ht40[rf]
276 [channel - 1])); 274 [channel - 1]);
277 } else { 275 } else {
278 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 276 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
279 ("customer's limit, 20MHz rf(%c) = " 277 "customer's limit, 20MHz rf(%c) = 0x%x\n",
280 "0x%x\n", ((rf == 0) ? 'A' : 'B'), 278 rf == 0 ? 'A' : 'B',
281 rtlefuse->pwrgroup_ht20[rf] 279 rtlefuse->pwrgroup_ht20[rf]
282 [channel - 1])); 280 [channel - 1]);
283 } 281 }
284 for (i = 0; i < 4; i++) { 282 for (i = 0; i < 4; i++) {
285 pwr_diff_limit[i] = 283 pwr_diff_limit[i] =
@@ -308,13 +306,13 @@ static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
308 (pwr_diff_limit[1] << 8) | 306 (pwr_diff_limit[1] << 8) |
309 (pwr_diff_limit[0]); 307 (pwr_diff_limit[0]);
310 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 308 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
311 ("Customer's limit rf(%c) = 0x%x\n", 309 "Customer's limit rf(%c) = 0x%x\n",
312 ((rf == 0) ? 'A' : 'B'), customer_limit)); 310 rf == 0 ? 'A' : 'B', customer_limit);
313 writeval = customer_limit + ((index < 2) ? 311 writeval = customer_limit + ((index < 2) ?
314 powerbase0[rf] : powerbase1[rf]); 312 powerbase0[rf] : powerbase1[rf]);
315 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 313 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
316 ("Customer, writeval rf(%c)= 0x%x\n", 314 "Customer, writeval rf(%c)= 0x%x\n",
317 ((rf == 0) ? 'A' : 'B'), writeval)); 315 rf == 0 ? 'A' : 'B', writeval);
318 break; 316 break;
319 default: 317 default:
320 chnlgroup = 0; 318 chnlgroup = 0;
@@ -323,9 +321,8 @@ static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
323 (rf ? 8 : 0)] + ((index < 2) ? 321 (rf ? 8 : 0)] + ((index < 2) ?
324 powerbase0[rf] : powerbase1[rf]); 322 powerbase0[rf] : powerbase1[rf]);
325 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 323 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
326 ("RTK better performance, writeval " 324 "RTK better performance, writeval rf(%c) = 0x%x\n",
327 "rf(%c) = 0x%x\n", 325 rf == 0 ? 'A' : 'B', writeval);
328 ((rf == 0) ? 'A' : 'B'), writeval));
329 break; 326 break;
330 } 327 }
331 *(p_outwriteval + rf) = writeval; 328 *(p_outwriteval + rf) = writeval;
@@ -367,7 +364,7 @@ static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw,
367 regoffset = regoffset_b[index]; 364 regoffset = regoffset_b[index];
368 rtl_set_bbreg(hw, regoffset, BMASKDWORD, writeval); 365 rtl_set_bbreg(hw, regoffset, BMASKDWORD, writeval);
369 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 366 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
370 ("Set 0x%x = %08x\n", regoffset, writeval)); 367 "Set 0x%x = %08x\n", regoffset, writeval);
371 if (((get_rf_type(rtlphy) == RF_2T2R) && 368 if (((get_rf_type(rtlphy) == RF_2T2R) &&
372 (regoffset == RTXAGC_A_MCS15_MCS12 || 369 (regoffset == RTXAGC_A_MCS15_MCS12 ||
373 regoffset == RTXAGC_B_MCS15_MCS12)) || 370 regoffset == RTXAGC_B_MCS15_MCS12)) ||
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/hw.c b/drivers/net/wireless/rtlwifi/rtl8192se/hw.c
index dffcafe01a39..acab8781cc7e 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/hw.c
@@ -1704,23 +1704,24 @@ static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1704 for (rf_path = 0; rf_path < 2; rf_path++) 1704 for (rf_path = 0; rf_path < 2; rf_path++)
1705 for (i = 0; i < 3; i++) 1705 for (i = 0; i < 3; i++)
1706 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1706 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1707 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path, 1707 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1708 i, rtlefuse->eeprom_chnlarea_txpwr_cck 1708 rf_path, i,
1709 [rf_path][i])); 1709 rtlefuse->eeprom_chnlarea_txpwr_cck
1710 [rf_path][i]);
1710 for (rf_path = 0; rf_path < 2; rf_path++) 1711 for (rf_path = 0; rf_path < 2; rf_path++)
1711 for (i = 0; i < 3; i++) 1712 for (i = 0; i < 3; i++)
1712 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1713 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1713 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1714 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1714 rf_path, i, 1715 rf_path, i,
1715 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1716 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1716 [rf_path][i])); 1717 [rf_path][i]);
1717 for (rf_path = 0; rf_path < 2; rf_path++) 1718 for (rf_path = 0; rf_path < 2; rf_path++)
1718 for (i = 0; i < 3; i++) 1719 for (i = 0; i < 3; i++)
1719 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1720 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1720 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1721 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1721 rf_path, i, 1722 rf_path, i,
1722 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif 1723 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1723 [rf_path][i])); 1724 [rf_path][i]);
1724 1725
1725 for (rf_path = 0; rf_path < 2; rf_path++) { 1726 for (rf_path = 0; rf_path < 2; rf_path++) {
1726 1727
@@ -1751,11 +1752,11 @@ static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1751 1752
1752 for (i = 0; i < 14; i++) { 1753 for (i = 0; i < 14; i++) {
1753 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1754 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1754 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = " 1755 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1755 "[0x%x / 0x%x / 0x%x]\n", rf_path, i, 1756 rf_path, i,
1756 rtlefuse->txpwrlevel_cck[rf_path][i], 1757 rtlefuse->txpwrlevel_cck[rf_path][i],
1757 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1758 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1758 rtlefuse->txpwrlevel_ht40_2s[rf_path][i])); 1759 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1759 } 1760 }
1760 } 1761 }
1761 1762
@@ -1788,13 +1789,13 @@ static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1788 0xf0) >> 4); 1789 0xf0) >> 4);
1789 1790
1790 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1791 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1791 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n", 1792 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1792 rf_path, i, 1793 rf_path, i,
1793 rtlefuse->pwrgroup_ht20[rf_path][i])); 1794 rtlefuse->pwrgroup_ht20[rf_path][i]);
1794 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1795 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1795 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n", 1796 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1796 rf_path, i, 1797 rf_path, i,
1797 rtlefuse->pwrgroup_ht40[rf_path][i])); 1798 rtlefuse->pwrgroup_ht40[rf_path][i]);
1798 } 1799 }
1799 } 1800 }
1800 1801
@@ -1849,27 +1850,27 @@ static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1849 (hwinfo[EEPROM_REGULATORY] & 0x1); 1850 (hwinfo[EEPROM_REGULATORY] & 0x1);
1850 } 1851 }
1851 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1852 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1852 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory)); 1853 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1853 1854
1854 for (i = 0; i < 14; i++) 1855 for (i = 0; i < 14; i++)
1855 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1856 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1856 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1857 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1857 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i])); 1858 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1858 for (i = 0; i < 14; i++) 1859 for (i = 0; i < 14; i++)
1859 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1860 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1860 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, 1861 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1861 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i])); 1862 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1862 for (i = 0; i < 14; i++) 1863 for (i = 0; i < 14; i++)
1863 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1864 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1864 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1865 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1865 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i])); 1866 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1866 for (i = 0; i < 14; i++) 1867 for (i = 0; i < 14; i++)
1867 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1868 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1868 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, 1869 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1869 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i])); 1870 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1870 1871
1871 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPwrSafetyFlag = %d\n", 1872 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1872 rtlefuse->txpwr_safetyflag)); 1873 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1873 1874
1874 /* Read RF-indication and Tx Power gain 1875 /* Read RF-indication and Tx Power gain
1875 * index diff of legacy to HT OFDM rate. */ 1876 * index diff of legacy to HT OFDM rate. */
@@ -1878,8 +1879,8 @@ static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1878 rtlefuse->legacy_httxpowerdiff = 1879 rtlefuse->legacy_httxpowerdiff =
1879 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0]; 1880 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1880 1881
1881 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPowerDiff = %#x\n", 1882 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1882 rtlefuse->eeprom_txpowerdiff)); 1883 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1883 1884
1884 /* Get TSSI value for each path. */ 1885 /* Get TSSI value for each path. */
1885 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A]; 1886 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
@@ -1887,16 +1888,16 @@ static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1887 usvalue = *(u8 *)&hwinfo[EEPROM_TSSI_B]; 1888 usvalue = *(u8 *)&hwinfo[EEPROM_TSSI_B];
1888 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff); 1889 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1889 1890
1890 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1891 RTPRINT(rtlpriv, FINIT, INIT_TxPower, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1891 rtlefuse->eeprom_tssi[RF90_PATH_A], 1892 rtlefuse->eeprom_tssi[RF90_PATH_A],
1892 rtlefuse->eeprom_tssi[RF90_PATH_B])); 1893 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1893 1894
1894 /* Read antenna tx power offset of B/C/D to A from EEPROM */ 1895 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1895 /* and read ThermalMeter from EEPROM */ 1896 /* and read ThermalMeter from EEPROM */
1896 tempval = *(u8 *)&hwinfo[EEPROM_THERMALMETER]; 1897 tempval = *(u8 *)&hwinfo[EEPROM_THERMALMETER];
1897 rtlefuse->eeprom_thermalmeter = tempval; 1898 rtlefuse->eeprom_thermalmeter = tempval;
1898 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("thermalmeter = 0x%x\n", 1899 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1899 rtlefuse->eeprom_thermalmeter)); 1900 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1900 1901
1901 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */ 1902 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1902 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f); 1903 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
@@ -1912,8 +1913,8 @@ static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1912 /* Version ID, Channel plan */ 1913 /* Version ID, Channel plan */
1913 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN]; 1914 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1914 rtlefuse->txpwr_fromeprom = true; 1915 rtlefuse->txpwr_fromeprom = true;
1915 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("EEPROM ChannelPlan = 0x%4x\n", 1916 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1916 rtlefuse->eeprom_channelplan)); 1917 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1917 1918
1918 /* Read Customer ID or Board Type!!! */ 1919 /* Read Customer ID or Board Type!!! */
1919 tempval = *(u8 *)&hwinfo[EEPROM_BOARDTYPE]; 1920 tempval = *(u8 *)&hwinfo[EEPROM_BOARDTYPE];
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-11 23:20:37 -0500