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authorLarry Finger <Larry.Finger@lwfinger.net>2013-03-24 23:06:42 -0400
committerJohn W. Linville <linville@tuxdriver.com>2013-04-01 16:20:13 -0400
commitf0eb856e0b6cbd21244afc0f252cec718ecf88fb (patch)
tree77d5cb7faf46f7ffd6b79a6d97be72b4eef422b1 /drivers/net/wireless/rtlwifi
parenta269913c52ad37952a4d9953bb6d748f7299c304 (diff)
rtlwifi: rtl8188ee: Add new driver
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Cc: jcheung@suse.com Cc: machen@suse.com Cc: mmarek@suse.cz Cc: page_he@realsil.com.cn Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rtlwifi')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/def.h324
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/dm.c1794
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/dm.h326
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/fw.c830
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/fw.h301
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/hw.c2529
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/hw.h68
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/led.c157
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/led.h38
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/phy.c2212
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/phy.h237
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.c109
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h327
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.c140
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.h97
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/reg.h2258
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/rf.c467
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/rf.h46
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/sw.c400
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/sw.h36
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/table.c643
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/table.h47
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/trx.c817
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/trx.h795
24 files changed, 14998 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/def.h b/drivers/net/wireless/rtlwifi/rtl8188ee/def.h
new file mode 100644
index 000000000000..c764fff9ebe6
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/def.h
@@ -0,0 +1,324 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_DEF_H__
31#define __RTL92C_DEF_H__
32
33#define HAL_RETRY_LIMIT_INFRA 48
34#define HAL_RETRY_LIMIT_AP_ADHOC 7
35
36#define RESET_DELAY_8185 20
37
38#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
39#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
40
41#define NUM_OF_FIRMWARE_QUEUE 10
42#define NUM_OF_PAGES_IN_FW 0x100
43#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
44#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
45#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
46#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
47#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
48#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
49#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
50#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
51#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
52#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
53
54#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
55#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
56#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
57#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
58#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
59
60#define MAX_LINES_HWCONFIG_TXT 1000
61#define MAX_BYTES_LINE_HWCONFIG_TXT 256
62
63#define SW_THREE_WIRE 0
64#define HW_THREE_WIRE 2
65
66#define BT_DEMO_BOARD 0
67#define BT_QA_BOARD 1
68#define BT_FPGA 2
69
70#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
71#define HAL_PRIME_CHNL_OFFSET_LOWER 1
72#define HAL_PRIME_CHNL_OFFSET_UPPER 2
73
74#define MAX_H2C_QUEUE_NUM 10
75
76#define RX_MPDU_QUEUE 0
77#define RX_CMD_QUEUE 1
78#define RX_MAX_QUEUE 2
79#define AC2QUEUEID(_AC) (_AC)
80
81#define C2H_RX_CMD_HDR_LEN 8
82#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
83 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
84#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
85 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
86#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
87 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
88#define GET_C2H_CMD_CONTINUE(__prxhdr) \
89 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
90#define GET_C2H_CMD_CONTENT(__prxhdr) \
91 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
92
93#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
94 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
95#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
96 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
97#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
98 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
99#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
100 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
101#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
102 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
103#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
104 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
105#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
106 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
107#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
108 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
109#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
110 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
111
112#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
113
114
115/* [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3
116 * [7] Manufacturer: TSMC=0, UMC=1
117 * [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2
118 * [3] Chip type: TEST=0, NORMAL=1
119 * [2:0] IC type: 81xxC=0, 8723=1, 92D=2
120 */
121#define CHIP_8723 BIT(0)
122#define CHIP_92D BIT(1)
123#define NORMAL_CHIP BIT(3)
124#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
125#define RF_TYPE_1T2R BIT(4)
126#define RF_TYPE_2T2R BIT(5)
127#define CHIP_VENDOR_UMC BIT(7)
128#define B_CUT_VERSION BIT(12)
129#define C_CUT_VERSION BIT(13)
130#define D_CUT_VERSION ((BIT(12)|BIT(13)))
131#define E_CUT_VERSION BIT(14)
132
133
134/* MASK */
135#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
136#define CHIP_TYPE_MASK BIT(3)
137#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
138#define MANUFACTUER_MASK BIT(7)
139#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
140#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
141
142/* Get element */
143#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
144#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
145#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
146#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
147#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
148#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
149
150
151#define IS_81XXC(version) \
152 ((GET_CVID_IC_TYPE(version) == 0) ? true : false)
153#define IS_8723_SERIES(version) \
154 ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? true : false)
155#define IS_92D(version) \
156 ((GET_CVID_IC_TYPE(version) == CHIP_92D) ? true : false)
157
158#define IS_NORMAL_CHIP(version) \
159 ((GET_CVID_CHIP_TYPE(version)) ? true : false)
160#define IS_NORMAL_CHIP92D(version) \
161 ((GET_CVID_CHIP_TYPE(version)) ? true : false)
162
163#define IS_1T1R(version) \
164 ((GET_CVID_RF_TYPE(version)) ? false : true)
165#define IS_1T2R(version) \
166 ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? true : false)
167#define IS_2T2R(version) \
168 ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? true : false)
169#define IS_CHIP_VENDOR_UMC(version) \
170 ((GET_CVID_MANUFACTUER(version)) ? true : false)
171
172#define IS_92C_SERIAL(version) \
173 ((IS_81XXC(version) && IS_2T2R(version)) ? true : false)
174#define IS_81xxC_VENDOR_UMC_A_CUT(version) \
175 (IS_81XXC(version) ? ((IS_CHIP_VENDOR_UMC(version)) ? \
176 ((GET_CVID_CUT_VERSION(version)) ? false : true) : false) : false)
177#define IS_81xxC_VENDOR_UMC_B_CUT(version) \
178 (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? \
179 ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true \
180 : false) : false) : false)
181
182enum version_8188e {
183 VERSION_TEST_CHIP_88E = 0x00,
184 VERSION_NORMAL_CHIP_88E = 0x01,
185 VERSION_UNKNOWN = 0xFF,
186};
187
188enum rx_packet_type {
189 NORMAL_RX,
190 TX_REPORT1,
191 TX_REPORT2,
192 HIS_REPORT,
193};
194
195enum rtl819x_loopback_e {
196 RTL819X_NO_LOOPBACK = 0,
197 RTL819X_MAC_LOOPBACK = 1,
198 RTL819X_DMA_LOOPBACK = 2,
199 RTL819X_CCK_LOOPBACK = 3,
200};
201
202enum rf_optype {
203 RF_OP_BY_SW_3WIRE = 0,
204 RF_OP_BY_FW,
205 RF_OP_MAX
206};
207
208enum rf_power_state {
209 RF_ON,
210 RF_OFF,
211 RF_SLEEP,
212 RF_SHUT_DOWN,
213};
214
215enum power_save_mode {
216 POWER_SAVE_MODE_ACTIVE,
217 POWER_SAVE_MODE_SAVE,
218};
219
220enum power_polocy_config {
221 POWERCFG_MAX_POWER_SAVINGS,
222 POWERCFG_GLOBAL_POWER_SAVINGS,
223 POWERCFG_LOCAL_POWER_SAVINGS,
224 POWERCFG_LENOVO,
225};
226
227enum interface_select_pci {
228 INTF_SEL1_MINICARD,
229 INTF_SEL0_PCIE,
230 INTF_SEL2_RSV,
231 INTF_SEL3_RSV,
232};
233
234enum hal_fw_c2h_cmd_id {
235 HAL_FW_C2H_CMD_Read_MACREG,
236 HAL_FW_C2H_CMD_Read_BBREG,
237 HAL_FW_C2H_CMD_Read_RFREG,
238 HAL_FW_C2H_CMD_Read_EEPROM,
239 HAL_FW_C2H_CMD_Read_EFUSE,
240 HAL_FW_C2H_CMD_Read_CAM,
241 HAL_FW_C2H_CMD_Get_BasicRate,
242 HAL_FW_C2H_CMD_Get_DataRate,
243 HAL_FW_C2H_CMD_Survey,
244 HAL_FW_C2H_CMD_SurveyDone,
245 HAL_FW_C2H_CMD_JoinBss,
246 HAL_FW_C2H_CMD_AddSTA,
247 HAL_FW_C2H_CMD_DelSTA,
248 HAL_FW_C2H_CMD_AtimDone,
249 HAL_FW_C2H_CMD_TX_Report,
250 HAL_FW_C2H_CMD_CCX_Report,
251 HAL_FW_C2H_CMD_DTM_Report,
252 HAL_FW_C2H_CMD_TX_Rate_Statistics,
253 HAL_FW_C2H_CMD_C2HLBK,
254 HAL_FW_C2H_CMD_C2HDBG,
255 HAL_FW_C2H_CMD_C2HFEEDBACK,
256 HAL_FW_C2H_CMD_MAX
257};
258
259enum wake_on_wlan_mode {
260 ewowlandisable,
261 ewakeonmagicpacketonly,
262 ewakeonpatternmatchonly,
263 ewakeonbothtypepacket
264};
265
266enum rtl_desc_qsel {
267 QSLT_BK = 0x2,
268 QSLT_BE = 0x0,
269 QSLT_VI = 0x5,
270 QSLT_VO = 0x7,
271 QSLT_BEACON = 0x10,
272 QSLT_HIGH = 0x11,
273 QSLT_MGNT = 0x12,
274 QSLT_CMD = 0x13,
275};
276
277enum rtl_desc92c_rate {
278 DESC92C_RATE1M = 0x00,
279 DESC92C_RATE2M = 0x01,
280 DESC92C_RATE5_5M = 0x02,
281 DESC92C_RATE11M = 0x03,
282
283 DESC92C_RATE6M = 0x04,
284 DESC92C_RATE9M = 0x05,
285 DESC92C_RATE12M = 0x06,
286 DESC92C_RATE18M = 0x07,
287 DESC92C_RATE24M = 0x08,
288 DESC92C_RATE36M = 0x09,
289 DESC92C_RATE48M = 0x0a,
290 DESC92C_RATE54M = 0x0b,
291
292 DESC92C_RATEMCS0 = 0x0c,
293 DESC92C_RATEMCS1 = 0x0d,
294 DESC92C_RATEMCS2 = 0x0e,
295 DESC92C_RATEMCS3 = 0x0f,
296 DESC92C_RATEMCS4 = 0x10,
297 DESC92C_RATEMCS5 = 0x11,
298 DESC92C_RATEMCS6 = 0x12,
299 DESC92C_RATEMCS7 = 0x13,
300 DESC92C_RATEMCS8 = 0x14,
301 DESC92C_RATEMCS9 = 0x15,
302 DESC92C_RATEMCS10 = 0x16,
303 DESC92C_RATEMCS11 = 0x17,
304 DESC92C_RATEMCS12 = 0x18,
305 DESC92C_RATEMCS13 = 0x19,
306 DESC92C_RATEMCS14 = 0x1a,
307 DESC92C_RATEMCS15 = 0x1b,
308 DESC92C_RATEMCS15_SG = 0x1c,
309 DESC92C_RATEMCS32 = 0x20,
310};
311
312struct phy_sts_cck_8192s_t {
313 u8 adc_pwdb_X[4];
314 u8 sq_rpt;
315 u8 cck_agc_rpt;
316};
317
318struct h2c_cmd_8192c {
319 u8 element_id;
320 u32 cmd_len;
321 u8 *p_cmdbuffer;
322};
323
324#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/dm.c b/drivers/net/wireless/rtlwifi/rtl8188ee/dm.c
new file mode 100644
index 000000000000..0a338cccbdfa
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/dm.c
@@ -0,0 +1,1794 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "base.h"
32#include "pci.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "dm.h"
37#include "fw.h"
38#include "trx.h"
39
40static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
41 0x7f8001fe, /* 0, +6.0dB */
42 0x788001e2, /* 1, +5.5dB */
43 0x71c001c7, /* 2, +5.0dB */
44 0x6b8001ae, /* 3, +4.5dB */
45 0x65400195, /* 4, +4.0dB */
46 0x5fc0017f, /* 5, +3.5dB */
47 0x5a400169, /* 6, +3.0dB */
48 0x55400155, /* 7, +2.5dB */
49 0x50800142, /* 8, +2.0dB */
50 0x4c000130, /* 9, +1.5dB */
51 0x47c0011f, /* 10, +1.0dB */
52 0x43c0010f, /* 11, +0.5dB */
53 0x40000100, /* 12, +0dB */
54 0x3c8000f2, /* 13, -0.5dB */
55 0x390000e4, /* 14, -1.0dB */
56 0x35c000d7, /* 15, -1.5dB */
57 0x32c000cb, /* 16, -2.0dB */
58 0x300000c0, /* 17, -2.5dB */
59 0x2d4000b5, /* 18, -3.0dB */
60 0x2ac000ab, /* 19, -3.5dB */
61 0x288000a2, /* 20, -4.0dB */
62 0x26000098, /* 21, -4.5dB */
63 0x24000090, /* 22, -5.0dB */
64 0x22000088, /* 23, -5.5dB */
65 0x20000080, /* 24, -6.0dB */
66 0x1e400079, /* 25, -6.5dB */
67 0x1c800072, /* 26, -7.0dB */
68 0x1b00006c, /* 27. -7.5dB */
69 0x19800066, /* 28, -8.0dB */
70 0x18000060, /* 29, -8.5dB */
71 0x16c0005b, /* 30, -9.0dB */
72 0x15800056, /* 31, -9.5dB */
73 0x14400051, /* 32, -10.0dB */
74 0x1300004c, /* 33, -10.5dB */
75 0x12000048, /* 34, -11.0dB */
76 0x11000044, /* 35, -11.5dB */
77 0x10000040, /* 36, -12.0dB */
78 0x0f00003c, /* 37, -12.5dB */
79 0x0e400039, /* 38, -13.0dB */
80 0x0d800036, /* 39, -13.5dB */
81 0x0cc00033, /* 40, -14.0dB */
82 0x0c000030, /* 41, -14.5dB */
83 0x0b40002d, /* 42, -15.0dB */
84};
85
86static const u8 cck_tbl_ch1_13[CCK_TABLE_SIZE][8] = {
87 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
88 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
89 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
90 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
91 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
92 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
93 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
94 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
95 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
96 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
97 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
98 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
99 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
100 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
101 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
102 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
103 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
104 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
105 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
106 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
107 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/
108 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/
109 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/
110 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/
111 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/
112 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/
113 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/
114 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/
115 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/
116 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/
117 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/
118 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/
119 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/
120};
121
122static const u8 cck_tbl_ch14[CCK_TABLE_SIZE][8] = {
123 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
124 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
125 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
126 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
127 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
128 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
129 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
130 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
131 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
132 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
133 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
134 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
135 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
136 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
137 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
138 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
139 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
140 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
141 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
142 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
143 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/
144 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/
145 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/
146 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/
147 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/
148 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/
149 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/
150 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/
151 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/
152 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/
153 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/
154 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/
155 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/
156};
157
158#define CAL_SWING_OFF(_off, _dir, _size, _del) \
159 do { \
160 for (_off = 0; _off < _size; _off++) { \
161 if (_del < thermal_threshold[_dir][_off]) { \
162 if (_off != 0) \
163 _off--; \
164 break; \
165 } \
166 } \
167 if (_off >= _size) \
168 _off = _size - 1; \
169 } while (0)
170
171static void rtl88e_set_iqk_matrix(struct ieee80211_hw *hw,
172 u8 ofdm_index, u8 rfpath,
173 long iqk_result_x, long iqk_result_y)
174{
175 long ele_a = 0, ele_d, ele_c = 0, value32;
176
177 ele_d = (ofdmswing_table[ofdm_index] & 0xFFC00000)>>22;
178
179 if (iqk_result_x != 0) {
180 if ((iqk_result_x & 0x00000200) != 0)
181 iqk_result_x = iqk_result_x | 0xFFFFFC00;
182 ele_a = ((iqk_result_x * ele_d)>>8)&0x000003FF;
183
184 if ((iqk_result_y & 0x00000200) != 0)
185 iqk_result_y = iqk_result_y | 0xFFFFFC00;
186 ele_c = ((iqk_result_y * ele_d)>>8)&0x000003FF;
187
188 switch (rfpath) {
189 case RF90_PATH_A:
190 value32 = (ele_d << 22)|((ele_c & 0x3F)<<16) | ele_a;
191 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBAL, MASKDWORD,
192 value32);
193 value32 = (ele_c & 0x000003C0) >> 6;
194 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, value32);
195 value32 = ((iqk_result_x * ele_d) >> 7) & 0x01;
196 rtl_set_bbreg(hw, ROFDM0_ECCATHRES, BIT(24), value32);
197 break;
198 case RF90_PATH_B:
199 value32 = (ele_d << 22)|((ele_c & 0x3F)<<16) | ele_a;
200 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBAL,
201 MASKDWORD, value32);
202 value32 = (ele_c & 0x000003C0) >> 6;
203 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, MASKH4BITS, value32);
204 value32 = ((iqk_result_x * ele_d) >> 7) & 0x01;
205 rtl_set_bbreg(hw, ROFDM0_ECCATHRES, BIT(28), value32);
206 break;
207 default:
208 break;
209 }
210 } else {
211 switch (rfpath) {
212 case RF90_PATH_A:
213 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBAL, MASKDWORD,
214 ofdmswing_table[ofdm_index]);
215 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, 0x00);
216 rtl_set_bbreg(hw, ROFDM0_ECCATHRES, BIT(24), 0x00);
217 break;
218 case RF90_PATH_B:
219 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBAL, MASKDWORD,
220 ofdmswing_table[ofdm_index]);
221 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, MASKH4BITS, 0x00);
222 rtl_set_bbreg(hw, ROFDM0_ECCATHRES, BIT(28), 0x00);
223 break;
224 default:
225 break;
226 }
227 }
228}
229
230void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw,
231 u8 type, u8 *pdirection, u32 *poutwrite_val)
232{
233 struct rtl_priv *rtlpriv = rtl_priv(hw);
234 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
235 u8 pwr_val = 0;
236 u8 cck_base = rtldm->swing_idx_cck_base;
237 u8 cck_val = rtldm->swing_idx_cck;
238 u8 ofdm_base = rtldm->swing_idx_ofdm_base;
239 u8 ofdm_val = rtlpriv->dm.swing_idx_ofdm[RF90_PATH_A];
240
241 if (type == 0) {
242 if (ofdm_val <= ofdm_base) {
243 *pdirection = 1;
244 pwr_val = ofdm_base - ofdm_val;
245 } else {
246 *pdirection = 2;
247 pwr_val = ofdm_val - ofdm_base;
248 }
249 } else if (type == 1) {
250 if (cck_val <= cck_base) {
251 *pdirection = 1;
252 pwr_val = cck_base - cck_val;
253 } else {
254 *pdirection = 2;
255 pwr_val = cck_val - cck_base;
256 }
257 }
258
259 if (pwr_val >= TXPWRTRACK_MAX_IDX && (*pdirection == 1))
260 pwr_val = TXPWRTRACK_MAX_IDX;
261
262 *poutwrite_val = pwr_val | (pwr_val << 8) | (pwr_val << 16) |
263 (pwr_val << 24);
264}
265
266
267static void rtl88e_chk_tx_track(struct ieee80211_hw *hw,
268 enum pwr_track_control_method method,
269 u8 rfpath, u8 index)
270{
271 struct rtl_priv *rtlpriv = rtl_priv(hw);
272 struct rtl_phy *rtlphy = &(rtlpriv->phy);
273 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
274 int jj = rtldm->swing_idx_cck;
275 int i;
276
277 if (method == TXAGC) {
278 if (rtldm->swing_flag_ofdm == true ||
279 rtldm->swing_flag_cck == true) {
280 u8 chan = rtlphy->current_channel;
281 rtl88e_phy_set_txpower_level(hw, chan);
282 rtldm->swing_flag_ofdm = false;
283 rtldm->swing_flag_cck = false;
284 }
285 } else if (method == BBSWING) {
286 if (!rtldm->cck_inch14) {
287 for (i = 0; i < 8; i++)
288 rtl_write_byte(rtlpriv, 0xa22 + i,
289 cck_tbl_ch1_13[jj][i]);
290 } else {
291 for (i = 0; i < 8; i++)
292 rtl_write_byte(rtlpriv, 0xa22 + i,
293 cck_tbl_ch14[jj][i]);
294 }
295
296 if (rfpath == RF90_PATH_A) {
297 long x = rtlphy->iqk_matrix[index].value[0][0];
298 long y = rtlphy->iqk_matrix[index].value[0][1];
299 u8 indx = rtldm->swing_idx_ofdm[rfpath];
300 rtl88e_set_iqk_matrix(hw, indx, rfpath, x, y);
301 } else if (rfpath == RF90_PATH_B) {
302 u8 indx = rtldm->swing_idx_ofdm[rfpath];
303 long x = rtlphy->iqk_matrix[indx].value[0][4];
304 long y = rtlphy->iqk_matrix[indx].value[0][5];
305 rtl88e_set_iqk_matrix(hw, indx, rfpath, x, y);
306 }
307 } else {
308 return;
309 }
310}
311
312static void rtl88e_dm_diginit(struct ieee80211_hw *hw)
313{
314 struct rtl_priv *rtlpriv = rtl_priv(hw);
315 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
316
317 dm_dig->dig_enable_flag = true;
318 dm_dig->cur_igvalue = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f);
319 dm_dig->pre_igvalue = 0;
320 dm_dig->cursta_cstate = DIG_STA_DISCONNECT;
321 dm_dig->presta_cstate = DIG_STA_DISCONNECT;
322 dm_dig->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
323 dm_dig->rssi_lowthresh = DM_DIG_THRESH_LOW;
324 dm_dig->rssi_highthresh = DM_DIG_THRESH_HIGH;
325 dm_dig->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
326 dm_dig->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
327 dm_dig->rx_gain_max = DM_DIG_MAX;
328 dm_dig->rx_gain_min = DM_DIG_MIN;
329 dm_dig->back_val = DM_DIG_BACKOFF_DEFAULT;
330 dm_dig->back_range_max = DM_DIG_BACKOFF_MAX;
331 dm_dig->back_range_min = DM_DIG_BACKOFF_MIN;
332 dm_dig->pre_cck_cca_thres = 0xff;
333 dm_dig->cur_cck_cca_thres = 0x83;
334 dm_dig->forbidden_igi = DM_DIG_MIN;
335 dm_dig->large_fa_hit = 0;
336 dm_dig->recover_cnt = 0;
337 dm_dig->dig_min_0 = 0x25;
338 dm_dig->dig_min_1 = 0x25;
339 dm_dig->media_connect_0 = false;
340 dm_dig->media_connect_1 = false;
341 rtlpriv->dm.dm_initialgain_enable = true;
342}
343
344static u8 rtl88e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
345{
346 struct rtl_priv *rtlpriv = rtl_priv(hw);
347 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
348 long rssi_val_min = 0;
349
350 if ((dm_dig->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
351 (dm_dig->cursta_cstate == DIG_STA_CONNECT)) {
352 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
353 rssi_val_min =
354 (rtlpriv->dm.entry_min_undec_sm_pwdb >
355 rtlpriv->dm.undec_sm_pwdb) ?
356 rtlpriv->dm.undec_sm_pwdb :
357 rtlpriv->dm.entry_min_undec_sm_pwdb;
358 else
359 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
360 } else if (dm_dig->cursta_cstate == DIG_STA_CONNECT ||
361 dm_dig->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
362 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
363 } else if (dm_dig->curmultista_cstate ==
364 DIG_MULTISTA_CONNECT) {
365 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
366 }
367 return (u8)rssi_val_min;
368}
369
370static void rtl88e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
371{
372 u32 ret_value;
373 struct rtl_priv *rtlpriv = rtl_priv(hw);
374 struct false_alarm_statistics *alm_cnt = &(rtlpriv->falsealm_cnt);
375
376 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1);
377 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1);
378
379 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD);
380 alm_cnt->cnt_fast_fsync_fail = (ret_value&0xffff);
381 alm_cnt->cnt_sb_search_fail = ((ret_value&0xffff0000)>>16);
382
383 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
384 alm_cnt->cnt_ofdm_cca = (ret_value&0xffff);
385 alm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
386
387 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
388 alm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
389 alm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
390
391 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
392 alm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
393 alm_cnt->cnt_ofdm_fail = alm_cnt->cnt_parity_fail +
394 alm_cnt->cnt_rate_illegal +
395 alm_cnt->cnt_crc8_fail +
396 alm_cnt->cnt_mcs_fail +
397 alm_cnt->cnt_fast_fsync_fail +
398 alm_cnt->cnt_sb_search_fail;
399
400 ret_value = rtl_get_bbreg(hw, REG_SC_CNT, MASKDWORD);
401 alm_cnt->cnt_bw_lsc = (ret_value & 0xffff);
402 alm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16);
403
404 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(12), 1);
405 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
406
407 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
408 alm_cnt->cnt_cck_fail = ret_value;
409
410 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
411 alm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
412
413 ret_value = rtl_get_bbreg(hw, RCCK0_CCA_CNT, MASKDWORD);
414 alm_cnt->cnt_cck_cca = ((ret_value & 0xff) << 8) |
415 ((ret_value&0xFF00)>>8);
416
417 alm_cnt->cnt_all = alm_cnt->cnt_fast_fsync_fail +
418 alm_cnt->cnt_sb_search_fail +
419 alm_cnt->cnt_parity_fail +
420 alm_cnt->cnt_rate_illegal +
421 alm_cnt->cnt_crc8_fail +
422 alm_cnt->cnt_mcs_fail +
423 alm_cnt->cnt_cck_fail;
424 alm_cnt->cnt_cca_all = alm_cnt->cnt_ofdm_cca + alm_cnt->cnt_cck_cca;
425
426 rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 1);
427 rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 0);
428 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 1);
429 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 0);
430 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0);
431 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0);
432 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 0);
433 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 2);
434 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 0);
435 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 2);
436
437 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
438 "cnt_parity_fail = %d, cnt_rate_illegal = %d, "
439 "cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
440 alm_cnt->cnt_parity_fail,
441 alm_cnt->cnt_rate_illegal,
442 alm_cnt->cnt_crc8_fail, alm_cnt->cnt_mcs_fail);
443
444 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
445 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
446 alm_cnt->cnt_ofdm_fail,
447 alm_cnt->cnt_cck_fail, alm_cnt->cnt_all);
448}
449
450static void rtl88e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
451{
452 struct rtl_priv *rtlpriv = rtl_priv(hw);
453 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
454 u8 cur_cck_cca_thresh;
455
456 if (dm_dig->cursta_cstate == DIG_STA_CONNECT) {
457 dm_dig->rssi_val_min = rtl88e_dm_initial_gain_min_pwdb(hw);
458 if (dm_dig->rssi_val_min > 25) {
459 cur_cck_cca_thresh = 0xcd;
460 } else if ((dm_dig->rssi_val_min <= 25) &&
461 (dm_dig->rssi_val_min > 10)) {
462 cur_cck_cca_thresh = 0x83;
463 } else {
464 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
465 cur_cck_cca_thresh = 0x83;
466 else
467 cur_cck_cca_thresh = 0x40;
468 }
469
470 } else {
471 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
472 cur_cck_cca_thresh = 0x83;
473 else
474 cur_cck_cca_thresh = 0x40;
475 }
476
477 if (dm_dig->cur_cck_cca_thres != cur_cck_cca_thresh)
478 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, cur_cck_cca_thresh);
479
480 dm_dig->cur_cck_cca_thres = cur_cck_cca_thresh;
481 dm_dig->pre_cck_cca_thres = dm_dig->cur_cck_cca_thres;
482 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
483 "CCK cca thresh hold =%x\n", dm_dig->cur_cck_cca_thres);
484}
485
486static void rtl88e_dm_dig(struct ieee80211_hw *hw)
487{
488 struct rtl_priv *rtlpriv = rtl_priv(hw);
489 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
490 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
491 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
492 u8 dig_min, dig_maxofmin;
493 bool bfirstconnect;
494 u8 dm_dig_max, dm_dig_min;
495 u8 current_igi = dm_dig->cur_igvalue;
496
497 if (rtlpriv->dm.dm_initialgain_enable == false)
498 return;
499 if (dm_dig->dig_enable_flag == false)
500 return;
501 if (mac->act_scanning == true)
502 return;
503
504 if (mac->link_state >= MAC80211_LINKED)
505 dm_dig->cursta_cstate = DIG_STA_CONNECT;
506 else
507 dm_dig->cursta_cstate = DIG_STA_DISCONNECT;
508 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
509 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
510 dm_dig->cursta_cstate = DIG_STA_DISCONNECT;
511
512 dm_dig_max = DM_DIG_MAX;
513 dm_dig_min = DM_DIG_MIN;
514 dig_maxofmin = DM_DIG_MAX_AP;
515 dig_min = dm_dig->dig_min_0;
516 bfirstconnect = ((mac->link_state >= MAC80211_LINKED) ? true : false) &&
517 (dm_dig->media_connect_0 == false);
518
519 dm_dig->rssi_val_min =
520 rtl88e_dm_initial_gain_min_pwdb(hw);
521
522 if (mac->link_state >= MAC80211_LINKED) {
523 if ((dm_dig->rssi_val_min + 20) > dm_dig_max)
524 dm_dig->rx_gain_max = dm_dig_max;
525 else if ((dm_dig->rssi_val_min + 20) < dm_dig_min)
526 dm_dig->rx_gain_max = dm_dig_min;
527 else
528 dm_dig->rx_gain_max = dm_dig->rssi_val_min + 20;
529
530 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
531 dig_min = dm_dig->antdiv_rssi_max;
532 } else {
533 if (dm_dig->rssi_val_min < dm_dig_min)
534 dig_min = dm_dig_min;
535 else if (dm_dig->rssi_val_min < dig_maxofmin)
536 dig_min = dig_maxofmin;
537 else
538 dig_min = dm_dig->rssi_val_min;
539 }
540 } else {
541 dm_dig->rx_gain_max = dm_dig_max;
542 dig_min = dm_dig_min;
543 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "no link\n");
544 }
545
546 if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
547 dm_dig->large_fa_hit++;
548 if (dm_dig->forbidden_igi < current_igi) {
549 dm_dig->forbidden_igi = current_igi;
550 dm_dig->large_fa_hit = 1;
551 }
552
553 if (dm_dig->large_fa_hit >= 3) {
554 if ((dm_dig->forbidden_igi + 1) > dm_dig->rx_gain_max)
555 dm_dig->rx_gain_min = dm_dig->rx_gain_max;
556 else
557 dm_dig->rx_gain_min = dm_dig->forbidden_igi + 1;
558 dm_dig->recover_cnt = 3600;
559 }
560 } else {
561 if (dm_dig->recover_cnt != 0) {
562 dm_dig->recover_cnt--;
563 } else {
564 if (dm_dig->large_fa_hit == 0) {
565 if ((dm_dig->forbidden_igi - 1) < dig_min) {
566 dm_dig->forbidden_igi = dig_min;
567 dm_dig->rx_gain_min = dig_min;
568 } else {
569 dm_dig->forbidden_igi--;
570 dm_dig->rx_gain_min =
571 dm_dig->forbidden_igi + 1;
572 }
573 } else if (dm_dig->large_fa_hit == 3) {
574 dm_dig->large_fa_hit = 0;
575 }
576 }
577 }
578
579 if (dm_dig->cursta_cstate == DIG_STA_CONNECT) {
580 if (bfirstconnect) {
581 current_igi = dm_dig->rssi_val_min;
582 } else {
583 if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
584 current_igi += 2;
585 else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
586 current_igi++;
587 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
588 current_igi--;
589 }
590 } else {
591 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
592 current_igi += 2;
593 else if (rtlpriv->falsealm_cnt.cnt_all > 8000)
594 current_igi++;
595 else if (rtlpriv->falsealm_cnt.cnt_all < 500)
596 current_igi--;
597 }
598
599 if (current_igi > DM_DIG_FA_UPPER)
600 current_igi = DM_DIG_FA_UPPER;
601 else if (current_igi < DM_DIG_FA_LOWER)
602 current_igi = DM_DIG_FA_LOWER;
603
604 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
605 current_igi = DM_DIG_FA_UPPER;
606
607 dm_dig->cur_igvalue = current_igi;
608 rtl88e_dm_write_dig(hw);
609 dm_dig->media_connect_0 = ((mac->link_state >= MAC80211_LINKED) ?
610 true : false);
611 dm_dig->dig_min_0 = dig_min;
612
613 rtl88e_dm_cck_packet_detection_thresh(hw);
614}
615
616static void rtl88e_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
617{
618 struct rtl_priv *rtlpriv = rtl_priv(hw);
619
620 rtlpriv->dm.dynamic_txpower_enable = false;
621
622 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
623 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
624}
625
626static void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
627{
628 struct rtl_priv *rtlpriv = rtl_priv(hw);
629 struct rtl_phy *rtlphy = &(rtlpriv->phy);
630 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
631 long undec_sm_pwdb;
632
633 if (!rtlpriv->dm.dynamic_txpower_enable)
634 return;
635
636 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
637 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
638 return;
639 }
640
641 if ((mac->link_state < MAC80211_LINKED) &&
642 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
643 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
644 "Not connected\n");
645
646 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
647
648 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
649 return;
650 }
651
652 if (mac->link_state >= MAC80211_LINKED) {
653 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
654 undec_sm_pwdb =
655 rtlpriv->dm.entry_min_undec_sm_pwdb;
656 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
657 "AP Client PWDB = 0x%lx\n",
658 undec_sm_pwdb);
659 } else {
660 undec_sm_pwdb =
661 rtlpriv->dm.undec_sm_pwdb;
662 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
663 "STA Default Port PWDB = 0x%lx\n",
664 undec_sm_pwdb);
665 }
666 } else {
667 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
668
669 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
670 "AP Ext Port PWDB = 0x%lx\n", undec_sm_pwdb);
671 }
672
673 if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
674 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
675 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
676 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr = 0x0)\n");
677 } else if ((undec_sm_pwdb <
678 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
679 (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
680 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
681 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
682 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr = 0x10)\n");
683 } else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
684 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
685 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
686 "TXHIGHPWRLEVEL_NORMAL\n");
687 }
688
689 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
690 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
691 "PHY_SetTxPowerLevel8192S() Channel = %d\n",
692 rtlphy->current_channel);
693 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel);
694 }
695
696 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
697}
698
699void rtl88e_dm_write_dig(struct ieee80211_hw *hw)
700{
701 struct rtl_priv *rtlpriv = rtl_priv(hw);
702 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
703
704 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
705 "cur_igvalue = 0x%x, "
706 "pre_igvalue = 0x%x, back_val = %d\n",
707 dm_dig->cur_igvalue, dm_dig->pre_igvalue,
708 dm_dig->back_val);
709
710 if (dm_dig->cur_igvalue > 0x3f)
711 dm_dig->cur_igvalue = 0x3f;
712 if (dm_dig->pre_igvalue != dm_dig->cur_igvalue) {
713 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
714 dm_dig->cur_igvalue);
715
716 dm_dig->pre_igvalue = dm_dig->cur_igvalue;
717 }
718}
719
720static void rtl88e_dm_pwdb_monitor(struct ieee80211_hw *hw)
721{
722 struct rtl_priv *rtlpriv = rtl_priv(hw);
723 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
724 struct rtl_sta_info *drv_priv;
725 static u64 last_txok;
726 static u64 last_rx;
727 long tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff;
728
729 if (rtlhal->oem_id == RT_CID_819x_HP) {
730 u64 cur_txok_cnt = 0;
731 u64 cur_rxok_cnt = 0;
732 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok;
733 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rx;
734 last_txok = cur_txok_cnt;
735 last_rx = cur_rxok_cnt;
736
737 if (cur_rxok_cnt > (cur_txok_cnt * 6))
738 rtl_write_dword(rtlpriv, REG_ARFR0, 0x8f015);
739 else
740 rtl_write_dword(rtlpriv, REG_ARFR0, 0xff015);
741 }
742
743 /* AP & ADHOC & MESH */
744 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
745 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
746 if (drv_priv->rssi_stat.undec_sm_pwdb < tmp_entry_min_pwdb)
747 tmp_entry_min_pwdb = drv_priv->rssi_stat.undec_sm_pwdb;
748 if (drv_priv->rssi_stat.undec_sm_pwdb > tmp_entry_max_pwdb)
749 tmp_entry_max_pwdb = drv_priv->rssi_stat.undec_sm_pwdb;
750 }
751 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
752
753 /* If associated entry is found */
754 if (tmp_entry_max_pwdb != 0) {
755 rtlpriv->dm.entry_max_undec_sm_pwdb = tmp_entry_max_pwdb;
756 RTPRINT(rtlpriv, FDM, DM_PWDB, "EntryMaxPWDB = 0x%lx(%ld)\n",
757 tmp_entry_max_pwdb, tmp_entry_max_pwdb);
758 } else {
759 rtlpriv->dm.entry_max_undec_sm_pwdb = 0;
760 }
761 /* If associated entry is found */
762 if (tmp_entry_min_pwdb != 0xff) {
763 rtlpriv->dm.entry_min_undec_sm_pwdb = tmp_entry_min_pwdb;
764 RTPRINT(rtlpriv, FDM, DM_PWDB, "EntryMinPWDB = 0x%lx(%ld)\n",
765 tmp_entry_min_pwdb, tmp_entry_min_pwdb);
766 } else {
767 rtlpriv->dm.entry_min_undec_sm_pwdb = 0;
768 }
769 /* Indicate Rx signal strength to FW. */
770 if (!rtlpriv->dm.useramask)
771 rtl_write_byte(rtlpriv, 0x4fe, rtlpriv->dm.undec_sm_pwdb);
772}
773
774void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw)
775{
776 struct rtl_priv *rtlpriv = rtl_priv(hw);
777
778 rtlpriv->dm.current_turbo_edca = false;
779 rtlpriv->dm.is_any_nonbepkts = false;
780 rtlpriv->dm.is_cur_rdlstate = false;
781}
782
783static void rtl88e_dm_check_edca_turbo(struct ieee80211_hw *hw)
784{
785 struct rtl_priv *rtlpriv = rtl_priv(hw);
786 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
787 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
788 static u64 last_txok_cnt;
789 static u64 last_rxok_cnt;
790 static u32 last_bt_edca_ul;
791 static u32 last_bt_edca_dl;
792 u64 cur_txok_cnt = 0;
793 u64 cur_rxok_cnt = 0;
794 u32 edca_be_ul = 0x5ea42b;
795 u32 edca_be_dl = 0x5ea42b;
796 bool change_edca = false;
797
798 if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
799 (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
800 rtlpriv->dm.current_turbo_edca = false;
801 last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
802 last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
803 }
804
805 if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
806 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
807 change_edca = true;
808 }
809
810 if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
811 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
812 change_edca = true;
813 }
814
815 if (mac->link_state != MAC80211_LINKED) {
816 rtlpriv->dm.current_turbo_edca = false;
817 return;
818 }
819
820 if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
821 if (!(edca_be_ul & 0xffff0000))
822 edca_be_ul |= 0x005e0000;
823
824 if (!(edca_be_dl & 0xffff0000))
825 edca_be_dl |= 0x005e0000;
826 }
827
828 if ((change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
829 (!rtlpriv->dm.disable_framebursting))) {
830 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
831 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
832
833 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
834 if (!rtlpriv->dm.is_cur_rdlstate ||
835 !rtlpriv->dm.current_turbo_edca) {
836 rtl_write_dword(rtlpriv,
837 REG_EDCA_BE_PARAM,
838 edca_be_dl);
839 rtlpriv->dm.is_cur_rdlstate = true;
840 }
841 } else {
842 if (rtlpriv->dm.is_cur_rdlstate ||
843 !rtlpriv->dm.current_turbo_edca) {
844 rtl_write_dword(rtlpriv,
845 REG_EDCA_BE_PARAM,
846 edca_be_ul);
847 rtlpriv->dm.is_cur_rdlstate = false;
848 }
849 }
850 rtlpriv->dm.current_turbo_edca = true;
851 } else {
852 if (rtlpriv->dm.current_turbo_edca) {
853 u8 tmp = AC0_BE;
854 rtlpriv->cfg->ops->set_hw_reg(hw,
855 HW_VAR_AC_PARAM,
856 (u8 *)(&tmp));
857 rtlpriv->dm.current_turbo_edca = false;
858 }
859 }
860
861 rtlpriv->dm.is_any_nonbepkts = false;
862 last_txok_cnt = rtlpriv->stats.txbytesunicast;
863 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
864}
865
866static void rtl88e_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
867 *hw)
868{
869 struct rtl_priv *rtlpriv = rtl_priv(hw);
870 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
871 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
872 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
873 u8 thermalvalue = 0, delta, delta_lck, delta_iqk, off;
874 u8 th_avg_cnt = 0;
875 u32 thermalvalue_avg = 0;
876 long ele_d, temp_cck;
877 char ofdm_index[2], cck_index = 0, ofdm_old[2] = {0, 0}, cck_old = 0;
878 int i = 0;
879 bool is2t = false;
880
881 u8 ofdm_min_index = 6, rf = (is2t) ? 2 : 1;
882 u8 index_for_channel;
883 enum _dec_inc {dec, power_inc};
884
885 /* 0.1 the following TWO tables decide the final index of
886 * OFDM/CCK swing table
887 */
888 char del_tbl_idx[2][15] = {
889 {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11},
890 {0, 0, -1, -2, -3, -4, -4, -4, -4, -5, -7, -8, -9, -9, -10}
891 };
892 u8 thermal_threshold[2][15] = {
893 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27},
894 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25}
895 };
896
897 /*Initilization (7 steps in total) */
898 rtlpriv->dm.txpower_trackinginit = true;
899 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
900 "rtl88e_dm_txpower_tracking_callback_thermalmeter\n");
901
902 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xfc00);
903 if (!thermalvalue)
904 return;
905 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
906 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
907 thermalvalue, rtlpriv->dm.thermalvalue,
908 rtlefuse->eeprom_thermalmeter);
909
910 /*1. Query OFDM Default Setting: Path A*/
911 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBAL, MASKDWORD) & MASKOFDM_D;
912 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
913 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
914 ofdm_old[0] = (u8) i;
915 rtldm->swing_idx_ofdm_base = (u8)i;
916 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
917 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index = 0x%x\n",
918 ROFDM0_XATXIQIMBAL,
919 ele_d, ofdm_old[0]);
920 break;
921 }
922 }
923
924 if (is2t) {
925 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBAL,
926 MASKDWORD) & MASKOFDM_D;
927 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
928 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
929 ofdm_old[1] = (u8)i;
930
931 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
932 DBG_LOUD,
933 "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index = 0x%x\n",
934 ROFDM0_XBTXIQIMBAL, ele_d,
935 ofdm_old[1]);
936 break;
937 }
938 }
939 }
940 /*2.Query CCK default setting From 0xa24*/
941 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
942 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
943 if (rtlpriv->dm.cck_inch14) {
944 if (memcmp(&temp_cck, &cck_tbl_ch14[i][2], 4) == 0) {
945 cck_old = (u8)i;
946 rtldm->swing_idx_cck_base = (u8)i;
947 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
948 "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch 14 %d\n",
949 RCCK0_TXFILTER2, temp_cck, cck_old,
950 rtlpriv->dm.cck_inch14);
951 break;
952 }
953 } else {
954 if (memcmp(&temp_cck, &cck_tbl_ch1_13[i][2], 4) == 0) {
955 cck_old = (u8)i;
956 rtldm->swing_idx_cck_base = (u8)i;
957 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
958 "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n",
959 RCCK0_TXFILTER2, temp_cck, cck_old,
960 rtlpriv->dm.cck_inch14);
961 break;
962 }
963 }
964 }
965
966 /*3 Initialize ThermalValues of RFCalibrateInfo*/
967 if (!rtldm->thermalvalue) {
968 rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter;
969 rtlpriv->dm.thermalvalue_lck = thermalvalue;
970 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
971 for (i = 0; i < rf; i++)
972 rtlpriv->dm.ofdm_index[i] = ofdm_old[i];
973 rtlpriv->dm.cck_index = cck_old;
974 }
975
976 /*4 Calculate average thermal meter*/
977 rtldm->thermalvalue_avg[rtldm->thermalvalue_avg_index] = thermalvalue;
978 rtldm->thermalvalue_avg_index++;
979 if (rtldm->thermalvalue_avg_index == AVG_THERMAL_NUM_88E)
980 rtldm->thermalvalue_avg_index = 0;
981
982 for (i = 0; i < AVG_THERMAL_NUM_88E; i++) {
983 if (rtldm->thermalvalue_avg[i]) {
984 thermalvalue_avg += rtldm->thermalvalue_avg[i];
985 th_avg_cnt++;
986 }
987 }
988
989 if (th_avg_cnt)
990 thermalvalue = (u8)(thermalvalue_avg / th_avg_cnt);
991
992 /* 5 Calculate delta, delta_LCK, delta_IQK.*/
993 if (rtlhal->reloadtxpowerindex) {
994 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
995 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
996 (rtlefuse->eeprom_thermalmeter - thermalvalue);
997 rtlhal->reloadtxpowerindex = false;
998 rtlpriv->dm.done_txpower = false;
999 } else if (rtlpriv->dm.done_txpower) {
1000 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
1001 (thermalvalue - rtlpriv->dm.thermalvalue) :
1002 (rtlpriv->dm.thermalvalue - thermalvalue);
1003 } else {
1004 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
1005 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
1006 (rtlefuse->eeprom_thermalmeter - thermalvalue);
1007 }
1008 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
1009 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
1010 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
1011 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
1012 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
1013 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
1014
1015 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1016 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
1017 "eeprom_thermalmeter 0x%x delta 0x%x "
1018 "delta_lck 0x%x delta_iqk 0x%x\n",
1019 thermalvalue, rtlpriv->dm.thermalvalue,
1020 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
1021 delta_iqk);
1022 /* 6 If necessary, do LCK.*/
1023 if (delta_lck >= 8) {
1024 rtlpriv->dm.thermalvalue_lck = thermalvalue;
1025 rtl88e_phy_lc_calibrate(hw);
1026 }
1027
1028 /* 7 If necessary, move the index of swing table to adjust Tx power. */
1029 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
1030 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
1031 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
1032 (rtlefuse->eeprom_thermalmeter - thermalvalue);
1033
1034 /* 7.1 Get the final CCK_index and OFDM_index for each
1035 * swing table.
1036 */
1037 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
1038 CAL_SWING_OFF(off, power_inc, IDX_MAP, delta);
1039 for (i = 0; i < rf; i++)
1040 ofdm_index[i] = rtldm->ofdm_index[i] +
1041 del_tbl_idx[power_inc][off];
1042 cck_index = rtldm->cck_index +
1043 del_tbl_idx[power_inc][off];
1044 } else {
1045 CAL_SWING_OFF(off, dec, IDX_MAP, delta);
1046 for (i = 0; i < rf; i++)
1047 ofdm_index[i] = rtldm->ofdm_index[i] +
1048 del_tbl_idx[dec][off];
1049 cck_index = rtldm->cck_index + del_tbl_idx[dec][off];
1050 }
1051
1052 /* 7.2 Handle boundary conditions of index.*/
1053 for (i = 0; i < rf; i++) {
1054 if (ofdm_index[i] > OFDM_TABLE_SIZE-1)
1055 ofdm_index[i] = OFDM_TABLE_SIZE-1;
1056 else if (rtldm->ofdm_index[i] < ofdm_min_index)
1057 ofdm_index[i] = ofdm_min_index;
1058 }
1059
1060 if (cck_index > CCK_TABLE_SIZE - 1)
1061 cck_index = CCK_TABLE_SIZE - 1;
1062 else if (cck_index < 0)
1063 cck_index = 0;
1064
1065 /*7.3Configure the Swing Table to adjust Tx Power.*/
1066 if (rtlpriv->dm.txpower_track_control) {
1067 rtldm->done_txpower = true;
1068 rtldm->swing_idx_ofdm[RF90_PATH_A] =
1069 (u8)ofdm_index[RF90_PATH_A];
1070 if (is2t)
1071 rtldm->swing_idx_ofdm[RF90_PATH_B] =
1072 (u8)ofdm_index[RF90_PATH_B];
1073 rtldm->swing_idx_cck = cck_index;
1074 if (rtldm->swing_idx_ofdm_cur !=
1075 rtldm->swing_idx_ofdm[0]) {
1076 rtldm->swing_idx_ofdm_cur =
1077 rtldm->swing_idx_ofdm[0];
1078 rtldm->swing_flag_ofdm = true;
1079 }
1080
1081 if (rtldm->swing_idx_cck != rtldm->swing_idx_cck) {
1082 rtldm->swing_idx_cck_cur = rtldm->swing_idx_cck;
1083 rtldm->swing_flag_cck = true;
1084 }
1085
1086 rtl88e_chk_tx_track(hw, TXAGC, 0, 0);
1087
1088 if (is2t)
1089 rtl88e_chk_tx_track(hw, BBSWING,
1090 RF90_PATH_B,
1091 index_for_channel);
1092 }
1093 }
1094
1095 if (delta_iqk >= 8) {
1096 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1097 rtl88e_phy_iq_calibrate(hw, false);
1098 }
1099
1100 if (rtldm->txpower_track_control)
1101 rtldm->thermalvalue = thermalvalue;
1102 rtldm->txpowercount = 0;
1103 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "end\n");
1104}
1105
1106static void rtl88e_dm_init_txpower_tracking(struct ieee80211_hw *hw)
1107{
1108 struct rtl_priv *rtlpriv = rtl_priv(hw);
1109
1110 rtlpriv->dm.txpower_tracking = true;
1111 rtlpriv->dm.txpower_trackinginit = false;
1112 rtlpriv->dm.txpowercount = 0;
1113 rtlpriv->dm.txpower_track_control = true;
1114
1115 rtlpriv->dm.swing_idx_ofdm[RF90_PATH_A] = 12;
1116 rtlpriv->dm.swing_idx_ofdm_cur = 12;
1117 rtlpriv->dm.swing_flag_ofdm = false;
1118 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1119 " rtlpriv->dm.txpower_tracking = %d\n",
1120 rtlpriv->dm.txpower_tracking);
1121}
1122
1123void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1124{
1125 struct rtl_priv *rtlpriv = rtl_priv(hw);
1126 static u8 tm_trigger;
1127
1128 if (!rtlpriv->dm.txpower_tracking)
1129 return;
1130
1131 if (!tm_trigger) {
1132 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17)|BIT(16),
1133 0x03);
1134 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1135 "Trigger 88E Thermal Meter!!\n");
1136 tm_trigger = 1;
1137 return;
1138 } else {
1139 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1140 "Schedule TxPowerTracking !!\n");
1141 rtl88e_dm_txpower_tracking_callback_thermalmeter(hw);
1142 tm_trigger = 0;
1143 }
1144}
1145
1146void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1147{
1148 struct rtl_priv *rtlpriv = rtl_priv(hw);
1149 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1150
1151 p_ra->ratr_state = DM_RATR_STA_INIT;
1152 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1153
1154 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1155 rtlpriv->dm.useramask = true;
1156 else
1157 rtlpriv->dm.useramask = false;
1158}
1159
1160static void rtl88e_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1161{
1162 struct rtl_priv *rtlpriv = rtl_priv(hw);
1163 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1164 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1165 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1166 struct ieee80211_sta *sta = NULL;
1167 u32 low_rssi, hi_rssi;
1168
1169 if (is_hal_stop(rtlhal)) {
1170 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1171 "driver is going to unload\n");
1172 return;
1173 }
1174
1175 if (!rtlpriv->dm.useramask) {
1176 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1177 "driver does not control rate adaptive mask\n");
1178 return;
1179 }
1180
1181 if (mac->link_state == MAC80211_LINKED &&
1182 mac->opmode == NL80211_IFTYPE_STATION) {
1183 switch (p_ra->pre_ratr_state) {
1184 case DM_RATR_STA_HIGH:
1185 hi_rssi = 50;
1186 low_rssi = 20;
1187 break;
1188 case DM_RATR_STA_MIDDLE:
1189 hi_rssi = 55;
1190 low_rssi = 20;
1191 break;
1192 case DM_RATR_STA_LOW:
1193 hi_rssi = 50;
1194 low_rssi = 25;
1195 break;
1196 default:
1197 hi_rssi = 50;
1198 low_rssi = 20;
1199 break;
1200 }
1201
1202 if (rtlpriv->dm.undec_sm_pwdb > (long)hi_rssi)
1203 p_ra->ratr_state = DM_RATR_STA_HIGH;
1204 else if (rtlpriv->dm.undec_sm_pwdb > (long)low_rssi)
1205 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
1206 else
1207 p_ra->ratr_state = DM_RATR_STA_LOW;
1208
1209 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
1210 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1211 "RSSI = %ld\n",
1212 rtlpriv->dm.undec_sm_pwdb);
1213 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1214 "RSSI_LEVEL = %d\n", p_ra->ratr_state);
1215 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1216 "PreState = %d, CurState = %d\n",
1217 p_ra->pre_ratr_state, p_ra->ratr_state);
1218
1219 rcu_read_lock();
1220 sta = rtl_find_sta(hw, mac->bssid);
1221 if (sta)
1222 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
1223 p_ra->ratr_state);
1224 rcu_read_unlock();
1225
1226 p_ra->pre_ratr_state = p_ra->ratr_state;
1227 }
1228 }
1229}
1230
1231static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1232{
1233 struct rtl_priv *rtlpriv = rtl_priv(hw);
1234 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1235
1236 dm_pstable->pre_ccastate = CCA_MAX;
1237 dm_pstable->cur_ccasate = CCA_MAX;
1238 dm_pstable->pre_rfstate = RF_MAX;
1239 dm_pstable->cur_rfstate = RF_MAX;
1240 dm_pstable->rssi_val_min = 0;
1241}
1242
1243static void rtl88e_dm_update_rx_idle_ant(struct ieee80211_hw *hw, u8 ant)
1244{
1245 struct rtl_priv *rtlpriv = rtl_priv(hw);
1246 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1247 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1248 struct fast_ant_training *fat_tbl = &(rtldm->fat_table);
1249 u32 def_ant, opt_ant;
1250
1251 if (fat_tbl->rx_idle_ant != ant) {
1252 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1253 "need to update rx idle ant\n");
1254 if (ant == MAIN_ANT) {
1255 def_ant = (fat_tbl->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1256 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
1257 opt_ant = (fat_tbl->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1258 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
1259 } else {
1260 def_ant = (fat_tbl->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1261 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
1262 opt_ant = (fat_tbl->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1263 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
1264 }
1265
1266 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
1267 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(5) |
1268 BIT(4) | BIT(3), def_ant);
1269 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(8) |
1270 BIT(7) | BIT(6), opt_ant);
1271 rtl_set_bbreg(hw, DM_REG_ANTSEL_CTRL_11N, BIT(14) |
1272 BIT(13) | BIT(12), def_ant);
1273 rtl_set_bbreg(hw, DM_REG_RESP_TX_11N, BIT(6) | BIT(7),
1274 def_ant);
1275 } else if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) {
1276 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(5) |
1277 BIT(4) | BIT(3), def_ant);
1278 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(8) |
1279 BIT(7) | BIT(6), opt_ant);
1280 }
1281 }
1282 fat_tbl->rx_idle_ant = ant;
1283 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RxIdleAnt %s\n",
1284 ((ant == MAIN_ANT) ? ("MAIN_ANT") : ("AUX_ANT")));
1285}
1286
1287static void rtl88e_dm_update_tx_ant(struct ieee80211_hw *hw,
1288 u8 ant, u32 mac_id)
1289{
1290 struct rtl_priv *rtlpriv = rtl_priv(hw);
1291 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1292 struct fast_ant_training *fat_tbl = &(rtldm->fat_table);
1293 u8 target_ant;
1294
1295 if (ant == MAIN_ANT)
1296 target_ant = MAIN_ANT_CG_TRX;
1297 else
1298 target_ant = AUX_ANT_CG_TRX;
1299
1300 fat_tbl->antsel_a[mac_id] = target_ant & BIT(0);
1301 fat_tbl->antsel_b[mac_id] = (target_ant & BIT(1)) >> 1;
1302 fat_tbl->antsel_c[mac_id] = (target_ant & BIT(2)) >> 2;
1303 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "txfrominfo target ant %s\n",
1304 ((ant == MAIN_ANT) ? ("MAIN_ANT") : ("AUX_ANT")));
1305 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "antsel_tr_mux = 3'b%d%d%d\n",
1306 fat_tbl->antsel_c[mac_id],
1307 fat_tbl->antsel_b[mac_id], fat_tbl->antsel_a[mac_id]);
1308}
1309
1310static void rtl88e_dm_rx_hw_antena_div_init(struct ieee80211_hw *hw)
1311{
1312 u32 value32;
1313 /*MAC Setting*/
1314 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1315 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 |
1316 (BIT(23) | BIT(25)));
1317 /*Pin Setting*/
1318 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1319 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1320 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 1);
1321 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1322 /*OFDM Setting*/
1323 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1324 /*CCK Setting*/
1325 rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1326 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1327 rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT);
1328 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201);
1329}
1330
1331static void rtl88e_dm_trx_hw_antenna_div_init(struct ieee80211_hw *hw)
1332{
1333 u32 value32;
1334
1335 /*MAC Setting*/
1336 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1337 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 |
1338 (BIT(23) | BIT(25)));
1339 /*Pin Setting*/
1340 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1341 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1342 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0);
1343 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1344 /*OFDM Setting*/
1345 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1346 /*CCK Setting*/
1347 rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1348 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1349 /*TX Setting*/
1350 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 0);
1351 rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT);
1352 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201);
1353}
1354
1355static void rtl88e_dm_fast_training_init(struct ieee80211_hw *hw)
1356{
1357 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1358 struct fast_ant_training *fat_tbl = &(rtldm->fat_table);
1359 u32 ant_combo = 2;
1360 u32 value32, i;
1361
1362 for (i = 0; i < 6; i++) {
1363 fat_tbl->bssid[i] = 0;
1364 fat_tbl->ant_sum[i] = 0;
1365 fat_tbl->ant_cnt[i] = 0;
1366 fat_tbl->ant_ave[i] = 0;
1367 }
1368 fat_tbl->train_idx = 0;
1369 fat_tbl->fat_state = FAT_NORMAL_STATE;
1370
1371 /*MAC Setting*/
1372 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1373 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) |
1374 BIT(25)));
1375 value32 = rtl_get_bbreg(hw, DM_REG_ANT_TRAIN_2, MASKDWORD);
1376 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_2, MASKDWORD, value32 | (BIT(16) |
1377 BIT(17)));
1378 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_2, MASKLWORD, 0);
1379 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_1, MASKDWORD, 0);
1380
1381 /*Pin Setting*/
1382 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1383 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1384 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0);
1385 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1386
1387 /*OFDM Setting*/
1388 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1389 /*antenna mapping table*/
1390 if (ant_combo == 2) {
1391 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE0, 1);
1392 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE1, 2);
1393 } else if (ant_combo == 7) {
1394 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE0, 1);
1395 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE1, 2);
1396 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE2, 2);
1397 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE3, 3);
1398 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING2_11N, MASKBYTE0, 4);
1399 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING2_11N, MASKBYTE1, 5);
1400 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING2_11N, MASKBYTE2, 6);
1401 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING2_11N, MASKBYTE3, 7);
1402 }
1403
1404 /*TX Setting*/
1405 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 1);
1406 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), 0);
1407 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), 1);
1408 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(2) | BIT(1) | BIT(0),
1409 (ant_combo - 1));
1410
1411 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1412}
1413
1414static void rtl88e_dm_antenna_div_init(struct ieee80211_hw *hw)
1415{
1416 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1417
1418 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1419 rtl88e_dm_rx_hw_antena_div_init(hw);
1420 else if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1421 rtl88e_dm_trx_hw_antenna_div_init(hw);
1422 else if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)
1423 rtl88e_dm_fast_training_init(hw);
1424}
1425
1426void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
1427 u8 *pdesc, u32 mac_id)
1428{
1429 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1430 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1431 struct fast_ant_training *fat_tbl = &(rtldm->fat_table);
1432
1433 if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
1434 (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)) {
1435 SET_TX_DESC_ANTSEL_A(pdesc, fat_tbl->antsel_a[mac_id]);
1436 SET_TX_DESC_ANTSEL_B(pdesc, fat_tbl->antsel_b[mac_id]);
1437 SET_TX_DESC_ANTSEL_C(pdesc, fat_tbl->antsel_c[mac_id]);
1438 }
1439}
1440
1441void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw,
1442 u8 antsel_tr_mux, u32 mac_id, u32 rx_pwdb_all)
1443{
1444 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1445 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1446 struct fast_ant_training *fat_tbl = &(rtldm->fat_table);
1447
1448 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
1449 if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
1450 fat_tbl->main_ant_sum[mac_id] += rx_pwdb_all;
1451 fat_tbl->main_ant_cnt[mac_id]++;
1452 } else {
1453 fat_tbl->aux_ant_sum[mac_id] += rx_pwdb_all;
1454 fat_tbl->aux_ant_cnt[mac_id]++;
1455 }
1456 } else if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) {
1457 if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
1458 fat_tbl->main_ant_sum[mac_id] += rx_pwdb_all;
1459 fat_tbl->main_ant_cnt[mac_id]++;
1460 } else {
1461 fat_tbl->aux_ant_sum[mac_id] += rx_pwdb_all;
1462 fat_tbl->aux_ant_cnt[mac_id]++;
1463 }
1464 }
1465}
1466
1467static void rtl88e_dm_hw_ant_div(struct ieee80211_hw *hw)
1468{
1469 struct rtl_priv *rtlpriv = rtl_priv(hw);
1470 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
1471 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1472 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1473 struct rtl_sta_info *drv_priv;
1474 struct fast_ant_training *fat_tbl = &(rtldm->fat_table);
1475 u32 i, min_rssi = 0xff, ant_div_max_rssi = 0, max_rssi = 0;
1476 u32 local_min_rssi, local_max_rssi;
1477 u32 main_rssi, aux_rssi;
1478 u8 rx_idle_ant = 0, target_ant = 7;
1479
1480 i = 0;
1481 main_rssi = (fat_tbl->main_ant_cnt[i] != 0) ?
1482 (fat_tbl->main_ant_sum[i] /
1483 fat_tbl->main_ant_cnt[i]) : 0;
1484 aux_rssi = (fat_tbl->aux_ant_cnt[i] != 0) ?
1485 (fat_tbl->aux_ant_sum[i] / fat_tbl->aux_ant_cnt[i]) : 0;
1486 target_ant = (main_rssi == aux_rssi) ?
1487 fat_tbl->rx_idle_ant : ((main_rssi >= aux_rssi) ?
1488 MAIN_ANT : AUX_ANT);
1489 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1490 "main_ant_sum %d main_ant_cnt %d\n",
1491 fat_tbl->main_ant_sum[i], fat_tbl->main_ant_cnt[i]);
1492 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1493 "aux_ant_sum %d aux_ant_cnt %d\n",
1494 fat_tbl->aux_ant_sum[i],
1495 fat_tbl->aux_ant_cnt[i]);
1496 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1497 "main_rssi %d aux_rssi%d\n", main_rssi, aux_rssi);
1498 local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;
1499 if ((local_max_rssi > ant_div_max_rssi) && (local_max_rssi < 40))
1500 ant_div_max_rssi = local_max_rssi;
1501 if (local_max_rssi > max_rssi)
1502 max_rssi = local_max_rssi;
1503
1504 if ((fat_tbl->rx_idle_ant == MAIN_ANT) && (main_rssi == 0))
1505 main_rssi = aux_rssi;
1506 else if ((fat_tbl->rx_idle_ant == AUX_ANT) && (aux_rssi == 0))
1507 aux_rssi = main_rssi;
1508
1509 local_min_rssi = (main_rssi > aux_rssi) ? aux_rssi : main_rssi;
1510 if (local_min_rssi < min_rssi) {
1511 min_rssi = local_min_rssi;
1512 rx_idle_ant = target_ant;
1513 }
1514 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1515 rtl88e_dm_update_tx_ant(hw, target_ant, i);
1516
1517 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
1518 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC) {
1519 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1520 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
1521 i++;
1522 main_rssi = (fat_tbl->main_ant_cnt[i] != 0) ?
1523 (fat_tbl->main_ant_sum[i] /
1524 fat_tbl->main_ant_cnt[i]) : 0;
1525 aux_rssi = (fat_tbl->aux_ant_cnt[i] != 0) ?
1526 (fat_tbl->aux_ant_sum[i] /
1527 fat_tbl->aux_ant_cnt[i]) : 0;
1528 target_ant = (main_rssi == aux_rssi) ?
1529 fat_tbl->rx_idle_ant : ((main_rssi >=
1530 aux_rssi) ? MAIN_ANT : AUX_ANT);
1531
1532
1533 local_max_rssi = max_t(u32, main_rssi, aux_rssi);
1534 if ((local_max_rssi > ant_div_max_rssi) &&
1535 (local_max_rssi < 40))
1536 ant_div_max_rssi = local_max_rssi;
1537 if (local_max_rssi > max_rssi)
1538 max_rssi = local_max_rssi;
1539
1540 if ((fat_tbl->rx_idle_ant == MAIN_ANT) && !main_rssi)
1541 main_rssi = aux_rssi;
1542 else if ((fat_tbl->rx_idle_ant == AUX_ANT) &&
1543 (aux_rssi == 0))
1544 aux_rssi = main_rssi;
1545
1546 local_min_rssi = (main_rssi > aux_rssi) ?
1547 aux_rssi : main_rssi;
1548 if (local_min_rssi < min_rssi) {
1549 min_rssi = local_min_rssi;
1550 rx_idle_ant = target_ant;
1551 }
1552 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1553 rtl88e_dm_update_tx_ant(hw, target_ant, i);
1554 }
1555 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1556 }
1557
1558 for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
1559 fat_tbl->main_ant_sum[i] = 0;
1560 fat_tbl->aux_ant_sum[i] = 0;
1561 fat_tbl->main_ant_cnt[i] = 0;
1562 fat_tbl->aux_ant_cnt[i] = 0;
1563 }
1564
1565 rtl88e_dm_update_rx_idle_ant(hw, rx_idle_ant);
1566
1567 dm_dig->antdiv_rssi_max = ant_div_max_rssi;
1568 dm_dig->rssi_max = max_rssi;
1569}
1570
1571static void rtl88e_set_next_mac_address_target(struct ieee80211_hw *hw)
1572{
1573 struct rtl_priv *rtlpriv = rtl_priv(hw);
1574 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1575 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1576 struct rtl_sta_info *drv_priv;
1577 struct fast_ant_training *fat_tbl = &(rtldm->fat_table);
1578 u32 value32, i, j = 0;
1579
1580 if (mac->link_state >= MAC80211_LINKED) {
1581 for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
1582 if ((fat_tbl->train_idx + 1) == ASSOCIATE_ENTRY_NUM)
1583 fat_tbl->train_idx = 0;
1584 else
1585 fat_tbl->train_idx++;
1586
1587 if (fat_tbl->train_idx == 0) {
1588 value32 = (mac->mac_addr[5] << 8) |
1589 mac->mac_addr[4];
1590 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_2,
1591 MASKLWORD, value32);
1592
1593 value32 = (mac->mac_addr[3] << 24) |
1594 (mac->mac_addr[2] << 16) |
1595 (mac->mac_addr[1] << 8) |
1596 mac->mac_addr[0];
1597 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_1,
1598 MASKDWORD, value32);
1599 break;
1600 }
1601
1602 if (rtlpriv->mac80211.opmode !=
1603 NL80211_IFTYPE_STATION) {
1604 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1605 list_for_each_entry(drv_priv,
1606 &rtlpriv->entry_list,
1607 list) {
1608 j++;
1609 if (j != fat_tbl->train_idx)
1610 continue;
1611
1612 value32 = (drv_priv->mac_addr[5] << 8) |
1613 drv_priv->mac_addr[4];
1614 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_2,
1615 MASKLWORD, value32);
1616
1617 value32 = (drv_priv->mac_addr[3]<<24) |
1618 (drv_priv->mac_addr[2]<<16) |
1619 (drv_priv->mac_addr[1]<<8) |
1620 drv_priv->mac_addr[0];
1621 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_1,
1622 MASKDWORD, value32);
1623 break;
1624 }
1625 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1626 /*find entry, break*/
1627 if (j == fat_tbl->train_idx)
1628 break;
1629 }
1630 }
1631 }
1632}
1633
1634static void rtl88e_dm_fast_ant_training(struct ieee80211_hw *hw)
1635{
1636 struct rtl_priv *rtlpriv = rtl_priv(hw);
1637 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1638 struct fast_ant_training *fat_tbl = &(rtldm->fat_table);
1639 u32 i, max_rssi = 0;
1640 u8 target_ant = 2;
1641 bool bpkt_filter_match = false;
1642
1643 if (fat_tbl->fat_state == FAT_TRAINING_STATE) {
1644 for (i = 0; i < 7; i++) {
1645 if (fat_tbl->ant_cnt[i] == 0) {
1646 fat_tbl->ant_ave[i] = 0;
1647 } else {
1648 fat_tbl->ant_ave[i] = fat_tbl->ant_sum[i] /
1649 fat_tbl->ant_cnt[i];
1650 bpkt_filter_match = true;
1651 }
1652
1653 if (fat_tbl->ant_ave[i] > max_rssi) {
1654 max_rssi = fat_tbl->ant_ave[i];
1655 target_ant = (u8) i;
1656 }
1657 }
1658
1659 if (bpkt_filter_match == false) {
1660 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N,
1661 BIT(16), 0);
1662 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1663 } else {
1664 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N,
1665 BIT(16), 0);
1666 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(8) |
1667 BIT(7) | BIT(6), target_ant);
1668 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 1);
1669
1670 fat_tbl->antsel_a[fat_tbl->train_idx] =
1671 target_ant & BIT(0);
1672 fat_tbl->antsel_b[fat_tbl->train_idx] =
1673 (target_ant & BIT(1)) >> 1;
1674 fat_tbl->antsel_c[fat_tbl->train_idx] =
1675 (target_ant & BIT(2)) >> 2;
1676
1677 if (target_ant == 0)
1678 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1679 }
1680
1681 for (i = 0; i < 7; i++) {
1682 fat_tbl->ant_sum[i] = 0;
1683 fat_tbl->ant_cnt[i] = 0;
1684 }
1685
1686 fat_tbl->fat_state = FAT_NORMAL_STATE;
1687 return;
1688 }
1689
1690 if (fat_tbl->fat_state == FAT_NORMAL_STATE) {
1691 rtl88e_set_next_mac_address_target(hw);
1692
1693 fat_tbl->fat_state = FAT_TRAINING_STATE;
1694 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N, BIT(16), 1);
1695 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1696
1697 mod_timer(&rtlpriv->works.fast_antenna_training_timer,
1698 jiffies + MSECS(RTL_WATCH_DOG_TIME));
1699 }
1700}
1701
1702void rtl88e_dm_fast_antenna_training_callback(unsigned long data)
1703{
1704 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
1705
1706 rtl88e_dm_fast_ant_training(hw);
1707}
1708
1709static void rtl88e_dm_antenna_diversity(struct ieee80211_hw *hw)
1710{
1711 struct rtl_priv *rtlpriv = rtl_priv(hw);
1712 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1713 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1714 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1715 struct fast_ant_training *fat_tbl = &(rtldm->fat_table);
1716
1717 if (mac->link_state < MAC80211_LINKED) {
1718 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "No Link\n");
1719 if (fat_tbl->becomelinked == true) {
1720 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1721 "need to turn off HW AntDiv\n");
1722 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1723 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N,
1724 BIT(15), 0);
1725 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1726 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N,
1727 BIT(21), 0);
1728 fat_tbl->becomelinked =
1729 (mac->link_state == MAC80211_LINKED) ? true : false;
1730 }
1731 return;
1732 } else {
1733 if (fat_tbl->becomelinked == false) {
1734 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1735 "Need to turn on HW AntDiv\n");
1736 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1737 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N,
1738 BIT(15), 1);
1739 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1740 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N,
1741 BIT(21), 1);
1742 fat_tbl->becomelinked =
1743 (mac->link_state >= MAC80211_LINKED) ? true : false;
1744 }
1745 }
1746
1747 if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
1748 (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV))
1749 rtl88e_dm_hw_ant_div(hw);
1750 else if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)
1751 rtl88e_dm_fast_ant_training(hw);
1752}
1753
1754void rtl88e_dm_init(struct ieee80211_hw *hw)
1755{
1756 struct rtl_priv *rtlpriv = rtl_priv(hw);
1757
1758 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1759 rtl88e_dm_diginit(hw);
1760 rtl88e_dm_init_dynamic_txpower(hw);
1761 rtl88e_dm_init_edca_turbo(hw);
1762 rtl88e_dm_init_rate_adaptive_mask(hw);
1763 rtl88e_dm_init_txpower_tracking(hw);
1764 rtl92c_dm_init_dynamic_bb_powersaving(hw);
1765 rtl88e_dm_antenna_div_init(hw);
1766}
1767
1768void rtl88e_dm_watchdog(struct ieee80211_hw *hw)
1769{
1770 struct rtl_priv *rtlpriv = rtl_priv(hw);
1771 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1772 bool fw_current_inpsmode = false;
1773 bool fw_ps_awake = true;
1774
1775 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1776 (u8 *)(&fw_current_inpsmode));
1777 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1778 (u8 *)(&fw_ps_awake));
1779 if (ppsc->p2p_ps_info.p2p_ps_mode)
1780 fw_ps_awake = false;
1781
1782 if ((ppsc->rfpwr_state == ERFON) &&
1783 ((!fw_current_inpsmode) && fw_ps_awake) &&
1784 (!ppsc->rfchange_inprogress)) {
1785 rtl88e_dm_pwdb_monitor(hw);
1786 rtl88e_dm_dig(hw);
1787 rtl88e_dm_false_alarm_counter_statistics(hw);
1788 rtl92c_dm_dynamic_txpower(hw);
1789 rtl88e_dm_check_txpower_tracking(hw);
1790 rtl88e_dm_refresh_rate_adaptive_mask(hw);
1791 rtl88e_dm_check_edca_turbo(hw);
1792 rtl88e_dm_antenna_diversity(hw);
1793 }
1794}
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/dm.h b/drivers/net/wireless/rtlwifi/rtl8188ee/dm.h
new file mode 100644
index 000000000000..0e07f72ea158
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/dm.h
@@ -0,0 +1,326 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL88E_DM_H__
31#define __RTL88E_DM_H__
32
33#define MAIN_ANT 0
34#define AUX_ANT 1
35#define MAIN_ANT_CG_TRX 1
36#define AUX_ANT_CG_TRX 0
37#define MAIN_ANT_CGCS_RX 0
38#define AUX_ANT_CGCS_RX 1
39
40/*RF REG LIST*/
41#define DM_REG_RF_MODE_11N 0x00
42#define DM_REG_RF_0B_11N 0x0B
43#define DM_REG_CHNBW_11N 0x18
44#define DM_REG_T_METER_11N 0x24
45#define DM_REG_RF_25_11N 0x25
46#define DM_REG_RF_26_11N 0x26
47#define DM_REG_RF_27_11N 0x27
48#define DM_REG_RF_2B_11N 0x2B
49#define DM_REG_RF_2C_11N 0x2C
50#define DM_REG_RXRF_A3_11N 0x3C
51#define DM_REG_T_METER_92D_11N 0x42
52#define DM_REG_T_METER_88E_11N 0x42
53
54/*BB REG LIST*/
55/*PAGE 8 */
56#define DM_REG_BB_CTRL_11N 0x800
57#define DM_REG_RF_PIN_11N 0x804
58#define DM_REG_PSD_CTRL_11N 0x808
59#define DM_REG_TX_ANT_CTRL_11N 0x80C
60#define DM_REG_BB_PWR_SAV5_11N 0x818
61#define DM_REG_CCK_RPT_FORMAT_11N 0x824
62#define DM_REG_RX_DEFAULT_A_11N 0x858
63#define DM_REG_RX_DEFAULT_B_11N 0x85A
64#define DM_REG_BB_PWR_SAV3_11N 0x85C
65#define DM_REG_ANTSEL_CTRL_11N 0x860
66#define DM_REG_RX_ANT_CTRL_11N 0x864
67#define DM_REG_PIN_CTRL_11N 0x870
68#define DM_REG_BB_PWR_SAV1_11N 0x874
69#define DM_REG_ANTSEL_PATH_11N 0x878
70#define DM_REG_BB_3WIRE_11N 0x88C
71#define DM_REG_SC_CNT_11N 0x8C4
72#define DM_REG_PSD_DATA_11N 0x8B4
73/*PAGE 9*/
74#define DM_REG_ANT_MAPPING1_11N 0x914
75#define DM_REG_ANT_MAPPING2_11N 0x918
76/*PAGE A*/
77#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
78#define DM_REG_CCK_CCA_11N 0xA0A
79#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
80#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
81#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
82#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
83#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
84#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
85#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
86#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
87#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
88#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
89#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
90#define DM_REG_CCK_FA_RST_11N 0xA2C
91#define DM_REG_CCK_FA_MSB_11N 0xA58
92#define DM_REG_CCK_FA_LSB_11N 0xA5C
93#define DM_REG_CCK_CCA_CNT_11N 0xA60
94#define DM_REG_BB_PWR_SAV4_11N 0xA74
95/*PAGE B */
96#define DM_REG_LNA_SWITCH_11N 0xB2C
97#define DM_REG_PATH_SWITCH_11N 0xB30
98#define DM_REG_RSSI_CTRL_11N 0xB38
99#define DM_REG_CONFIG_ANTA_11N 0xB68
100#define DM_REG_RSSI_BT_11N 0xB9C
101/*PAGE C */
102#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
103#define DM_REG_RX_PATH_11N 0xC04
104#define DM_REG_TRMUX_11N 0xC08
105#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
106#define DM_REG_RXIQI_MATRIX_11N 0xC14
107#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
108#define DM_REG_IGI_A_11N 0xC50
109#define DM_REG_ANTDIV_PARA2_11N 0xC54
110#define DM_REG_IGI_B_11N 0xC58
111#define DM_REG_ANTDIV_PARA3_11N 0xC5C
112#define DM_REG_BB_PWR_SAV2_11N 0xC70
113#define DM_REG_RX_OFF_11N 0xC7C
114#define DM_REG_TXIQK_MATRIXA_11N 0xC80
115#define DM_REG_TXIQK_MATRIXB_11N 0xC88
116#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
117#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
118#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
119#define DM_REG_ANTDIV_PARA1_11N 0xCA4
120#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
121/*PAGE D */
122#define DM_REG_OFDM_FA_RSTD_11N 0xD00
123#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
124#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
125#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
126/*PAGE E */
127#define DM_REG_TXAGC_A_6_18_11N 0xE00
128#define DM_REG_TXAGC_A_24_54_11N 0xE04
129#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
130#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
131#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
132#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
133#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
134#define DM_REG_FPGA0_IQK_11N 0xE28
135#define DM_REG_TXIQK_TONE_A_11N 0xE30
136#define DM_REG_RXIQK_TONE_A_11N 0xE34
137#define DM_REG_TXIQK_PI_A_11N 0xE38
138#define DM_REG_RXIQK_PI_A_11N 0xE3C
139#define DM_REG_TXIQK_11N 0xE40
140#define DM_REG_RXIQK_11N 0xE44
141#define DM_REG_IQK_AGC_PTS_11N 0xE48
142#define DM_REG_IQK_AGC_RSP_11N 0xE4C
143#define DM_REG_BLUETOOTH_11N 0xE6C
144#define DM_REG_RX_WAIT_CCA_11N 0xE70
145#define DM_REG_TX_CCK_RFON_11N 0xE74
146#define DM_REG_TX_CCK_BBON_11N 0xE78
147#define DM_REG_OFDM_RFON_11N 0xE7C
148#define DM_REG_OFDM_BBON_11N 0xE80
149#define DM_REG_TX2RX_11N 0xE84
150#define DM_REG_TX2TX_11N 0xE88
151#define DM_REG_RX_CCK_11N 0xE8C
152#define DM_REG_RX_OFDM_11N 0xED0
153#define DM_REG_RX_WAIT_RIFS_11N 0xED4
154#define DM_REG_RX2RX_11N 0xED8
155#define DM_REG_STANDBY_11N 0xEDC
156#define DM_REG_SLEEP_11N 0xEE0
157#define DM_REG_PMPD_ANAEN_11N 0xEEC
158
159
160/*MAC REG LIST*/
161#define DM_REG_BB_RST_11N 0x02
162#define DM_REG_ANTSEL_PIN_11N 0x4C
163#define DM_REG_EARLY_MODE_11N 0x4D0
164#define DM_REG_RSSI_MONITOR_11N 0x4FE
165#define DM_REG_EDCA_VO_11N 0x500
166#define DM_REG_EDCA_VI_11N 0x504
167#define DM_REG_EDCA_BE_11N 0x508
168#define DM_REG_EDCA_BK_11N 0x50C
169#define DM_REG_TXPAUSE_11N 0x522
170#define DM_REG_RESP_TX_11N 0x6D8
171#define DM_REG_ANT_TRAIN_1 0x7b0
172#define DM_REG_ANT_TRAIN_2 0x7b4
173
174/*DIG Related*/
175#define DM_BIT_IGI_11N 0x0000007F
176
177#define HAL_DM_DIG_DISABLE BIT(0)
178#define HAL_DM_HIPWR_DISABLE BIT(1)
179
180#define OFDM_TABLE_LENGTH 43
181#define CCK_TABLE_LENGTH 33
182
183#define OFDM_TABLE_SIZE 43
184#define CCK_TABLE_SIZE 33
185
186#define BW_AUTO_SWITCH_HIGH_LOW 25
187#define BW_AUTO_SWITCH_LOW_HIGH 30
188
189#define DM_DIG_THRESH_HIGH 40
190#define DM_DIG_THRESH_LOW 35
191
192#define DM_FALSEALARM_THRESH_LOW 400
193#define DM_FALSEALARM_THRESH_HIGH 1000
194
195#define DM_DIG_MAX 0x3e
196#define DM_DIG_MIN 0x1e
197
198#define DM_DIG_MAX_AP 0x32
199#define DM_DIG_MIN_AP 0x20
200
201#define DM_DIG_FA_UPPER 0x3e
202#define DM_DIG_FA_LOWER 0x1e
203#define DM_DIG_FA_TH0 0x200
204#define DM_DIG_FA_TH1 0x300
205#define DM_DIG_FA_TH2 0x400
206
207#define DM_DIG_BACKOFF_MAX 12
208#define DM_DIG_BACKOFF_MIN -4
209#define DM_DIG_BACKOFF_DEFAULT 10
210
211#define RXPATHSELECTION_SS_TH_LOW 30
212#define RXPATHSELECTION_DIFF_TH 18
213
214#define DM_RATR_STA_INIT 0
215#define DM_RATR_STA_HIGH 1
216#define DM_RATR_STA_MIDDLE 2
217#define DM_RATR_STA_LOW 3
218
219#define CTS2SELF_THVAL 30
220#define REGC38_TH 20
221
222#define WAIOTTHVAL 25
223
224#define TXHIGHPWRLEVEL_NORMAL 0
225#define TXHIGHPWRLEVEL_LEVEL1 1
226#define TXHIGHPWRLEVEL_LEVEL2 2
227#define TXHIGHPWRLEVEL_BT1 3
228#define TXHIGHPWRLEVEL_BT2 4
229
230#define DM_TYPE_BYFW 0
231#define DM_TYPE_BYDRIVER 1
232
233#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
234#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
235#define TXPWRTRACK_MAX_IDX 6
236
237struct swat_t {
238 u8 failure_cnt;
239 u8 try_flag;
240 u8 stop_trying;
241 long pre_rssi;
242 long trying_threshold;
243 u8 cur_antenna;
244 u8 pre_antenna;
245};
246
247enum FAT_STATE {
248 FAT_NORMAL_STATE = 0,
249 FAT_TRAINING_STATE = 1,
250};
251
252enum tag_dynamic_init_gain_operation_type_definition {
253 DIG_TYPE_THRESH_HIGH = 0,
254 DIG_TYPE_THRESH_LOW = 1,
255 DIG_TYPE_BACKOFF = 2,
256 DIG_TYPE_RX_GAIN_MIN = 3,
257 DIG_TYPE_RX_GAIN_MAX = 4,
258 DIG_TYPE_ENABLE = 5,
259 DIG_TYPE_DISABLE = 6,
260 DIG_OP_TYPE_MAX
261};
262
263enum tag_cck_packet_detection_threshold_type_definition {
264 CCK_PD_STAGE_LOWRSSI = 0,
265 CCK_PD_STAGE_HIGHRSSI = 1,
266 CCK_FA_STAGE_LOW = 2,
267 CCK_FA_STAGE_HIGH = 3,
268 CCK_PD_STAGE_MAX = 4,
269};
270
271enum dm_1r_cca_e {
272 CCA_1R = 0,
273 CCA_2R = 1,
274 CCA_MAX = 2,
275};
276
277enum dm_rf_e {
278 RF_SAVE = 0,
279 RF_NORMAL = 1,
280 RF_MAX = 2,
281};
282
283enum dm_sw_ant_switch_e {
284 ANS_ANTENNA_B = 1,
285 ANS_ANTENNA_A = 2,
286 ANS_ANTENNA_MAX = 3,
287};
288
289enum dm_dig_ext_port_alg_e {
290 DIG_EXT_PORT_STAGE_0 = 0,
291 DIG_EXT_PORT_STAGE_1 = 1,
292 DIG_EXT_PORT_STAGE_2 = 2,
293 DIG_EXT_PORT_STAGE_3 = 3,
294 DIG_EXT_PORT_STAGE_MAX = 4,
295};
296
297enum dm_dig_connect_e {
298 DIG_STA_DISCONNECT = 0,
299 DIG_STA_CONNECT = 1,
300 DIG_STA_BEFORE_CONNECT = 2,
301 DIG_MULTISTA_DISCONNECT = 3,
302 DIG_MULTISTA_CONNECT = 4,
303 DIG_CONNECT_MAX
304};
305
306enum pwr_track_control_method {
307 BBSWING,
308 TXAGC
309};
310
311void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
312 u8 *pdesc, u32 mac_id);
313void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw, u8 antsel_tr_mux,
314 u32 mac_id, u32 rx_pwdb_all);
315void rtl88e_dm_fast_antenna_training_callback(unsigned long data);
316void rtl88e_dm_init(struct ieee80211_hw *hw);
317void rtl88e_dm_watchdog(struct ieee80211_hw *hw);
318void rtl88e_dm_write_dig(struct ieee80211_hw *hw);
319void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw);
320void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw);
321void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
322void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw,
323 u8 type, u8 *pdirection,
324 u32 *poutwrite_val);
325
326#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/fw.c b/drivers/net/wireless/rtlwifi/rtl8188ee/fw.c
new file mode 100644
index 000000000000..66ff30ba28ce
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/fw.c
@@ -0,0 +1,830 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "pci.h"
32#include "base.h"
33#include "reg.h"
34#include "def.h"
35#include "fw.h"
36
37#include <linux/kmemleak.h>
38
39static void _rtl88e_enable_fw_download(struct ieee80211_hw *hw, bool enable)
40{
41 struct rtl_priv *rtlpriv = rtl_priv(hw);
42 u8 tmp;
43
44 if (enable) {
45 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
46 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04);
47
48 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
49 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
50
51 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
52 rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
53 } else {
54 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
55 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
56
57 rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);
58 }
59}
60
61static void _rtl88e_fw_block_write(struct ieee80211_hw *hw,
62 const u8 *buffer, u32 size)
63{
64 struct rtl_priv *rtlpriv = rtl_priv(hw);
65 u32 blk_sz = sizeof(u32);
66 u8 *buf_ptr = (u8 *)buffer;
67 u32 *pu4BytePtr = (u32 *)buffer;
68 u32 i, offset, blk_cnt, remain;
69
70 blk_cnt = size / blk_sz;
71 remain = size % blk_sz;
72
73 for (i = 0; i < blk_cnt; i++) {
74 offset = i * blk_sz;
75 rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
76 *(pu4BytePtr + i));
77 }
78
79 if (remain) {
80 offset = blk_cnt * blk_sz;
81 buf_ptr += offset;
82 for (i = 0; i < remain; i++) {
83 rtl_write_byte(rtlpriv, (FW_8192C_START_ADDRESS +
84 offset + i), *(buf_ptr + i));
85 }
86 }
87}
88
89static void _rtl88e_fw_page_write(struct ieee80211_hw *hw,
90 u32 page, const u8 *buffer, u32 size)
91{
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93 u8 value8;
94 u8 u8page = (u8) (page & 0x07);
95
96 value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
97
98 rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
99 _rtl88e_fw_block_write(hw, buffer, size);
100}
101
102static void _rtl88e_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
103{
104 u32 fwlen = *pfwlen;
105 u8 remain = (u8) (fwlen % 4);
106
107 remain = (remain == 0) ? 0 : (4 - remain);
108
109 while (remain > 0) {
110 pfwbuf[fwlen] = 0;
111 fwlen++;
112 remain--;
113 }
114
115 *pfwlen = fwlen;
116}
117
118static void _rtl88e_write_fw(struct ieee80211_hw *hw,
119 enum version_8188e version, u8 *buffer, u32 size)
120{
121 struct rtl_priv *rtlpriv = rtl_priv(hw);
122 u8 *buf_ptr = (u8 *)buffer;
123 u32 page_no, remain;
124 u32 page, offset;
125
126 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "FW size is %d bytes,\n", size);
127
128 _rtl88e_fill_dummy(buf_ptr, &size);
129
130 page_no = size / FW_8192C_PAGE_SIZE;
131 remain = size % FW_8192C_PAGE_SIZE;
132
133 if (page_no > 8) {
134 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
135 "Page numbers should not greater then 8\n");
136 }
137
138 for (page = 0; page < page_no; page++) {
139 offset = page * FW_8192C_PAGE_SIZE;
140 _rtl88e_fw_page_write(hw, page, (buf_ptr + offset),
141 FW_8192C_PAGE_SIZE);
142 }
143
144 if (remain) {
145 offset = page_no * FW_8192C_PAGE_SIZE;
146 page = page_no;
147 _rtl88e_fw_page_write(hw, page, (buf_ptr + offset), remain);
148 }
149}
150
151static int _rtl88e_fw_free_to_go(struct ieee80211_hw *hw)
152{
153 struct rtl_priv *rtlpriv = rtl_priv(hw);
154 int err = -EIO;
155 u32 counter = 0;
156 u32 value32;
157
158 do {
159 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
160 } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
161 (!(value32 & FWDL_CHKSUM_RPT)));
162
163 if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
164 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
165 "chksum report faill ! REG_MCUFWDL:0x%08x .\n",
166 value32);
167 goto exit;
168 }
169
170 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
171 "Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32);
172
173 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
174 value32 |= MCUFWDL_RDY;
175 value32 &= ~WINTINI_RDY;
176 rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
177
178 rtl88e_firmware_selfreset(hw);
179 counter = 0;
180
181 do {
182 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
183 if (value32 & WINTINI_RDY) {
184 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
185 "Polling FW ready success!! REG_MCUFWDL:0x%08x.\n",
186 value32);
187 err = 0;
188 goto exit;
189 }
190
191 udelay(FW_8192C_POLLING_DELAY);
192
193 } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
194
195 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
196 "Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", value32);
197
198exit:
199 return err;
200}
201
202int rtl88e_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw)
203{
204 struct rtl_priv *rtlpriv = rtl_priv(hw);
205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
206 struct rtl92c_firmware_header *pfwheader;
207 u8 *pfwdata;
208 u32 fwsize;
209 int err;
210 enum version_8188e version = rtlhal->version;
211
212 if (!rtlhal->pfirmware)
213 return 1;
214
215 pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware;
216 pfwdata = (u8 *)rtlhal->pfirmware;
217 fwsize = rtlhal->fwsize;
218 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
219 "normal Firmware SIZE %d\n", fwsize);
220
221 if (IS_FW_HEADER_EXIST(pfwheader)) {
222 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
223 "Firmware Version(%d), Signature(%#x), Size(%d)\n",
224 pfwheader->version, pfwheader->signature,
225 (int)sizeof(struct rtl92c_firmware_header));
226
227 pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
228 fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
229 }
230
231 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
232 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
233 rtl88e_firmware_selfreset(hw);
234 }
235 _rtl88e_enable_fw_download(hw, true);
236 _rtl88e_write_fw(hw, version, pfwdata, fwsize);
237 _rtl88e_enable_fw_download(hw, false);
238
239 err = _rtl88e_fw_free_to_go(hw);
240
241 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
242 "Firmware is%s ready to run!\n", err ? " not" : "");
243 return 0;
244}
245
246static bool _rtl88e_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
247{
248 struct rtl_priv *rtlpriv = rtl_priv(hw);
249 u8 val_hmetfr;
250
251 val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
252 if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
253 return true;
254 return false;
255}
256
257static void _rtl88e_fill_h2c_command(struct ieee80211_hw *hw,
258 u8 element_id, u32 cmd_len,
259 u8 *cmd_b)
260{
261 struct rtl_priv *rtlpriv = rtl_priv(hw);
262 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
263 u8 boxnum;
264 u16 box_reg = 0, box_extreg = 0;
265 u8 u1b_tmp;
266 bool isfw_read = false;
267 u8 buf_index = 0;
268 bool write_sucess = false;
269 u8 wait_h2c_limit = 100;
270 u8 wait_writeh2c_limit = 100;
271 u8 boxc[4], boxext[2];
272 u32 h2c_waitcounter = 0;
273 unsigned long flag;
274 u8 idx;
275
276 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
277
278 while (true) {
279 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
280 if (rtlhal->h2c_setinprogress) {
281 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
282 "H2C set in progress! Wait to set..element_id(%d).\n",
283 element_id);
284
285 while (rtlhal->h2c_setinprogress) {
286 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
287 flag);
288 h2c_waitcounter++;
289 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
290 "Wait 100 us (%d times)...\n",
291 h2c_waitcounter);
292 udelay(100);
293
294 if (h2c_waitcounter > 1000)
295 return;
296 spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
297 flag);
298 }
299 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
300 } else {
301 rtlhal->h2c_setinprogress = true;
302 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
303 break;
304 }
305 }
306
307 while (!write_sucess) {
308 wait_writeh2c_limit--;
309 if (wait_writeh2c_limit == 0) {
310 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
311 "Write H2C fail because no trigger for FW INT!\n");
312 break;
313 }
314
315 boxnum = rtlhal->last_hmeboxnum;
316 switch (boxnum) {
317 case 0:
318 box_reg = REG_HMEBOX_0;
319 box_extreg = REG_HMEBOX_EXT_0;
320 break;
321 case 1:
322 box_reg = REG_HMEBOX_1;
323 box_extreg = REG_HMEBOX_EXT_1;
324 break;
325 case 2:
326 box_reg = REG_HMEBOX_2;
327 box_extreg = REG_HMEBOX_EXT_2;
328 break;
329 case 3:
330 box_reg = REG_HMEBOX_3;
331 box_extreg = REG_HMEBOX_EXT_3;
332 break;
333 default:
334 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
335 "switch case not processed\n");
336 break;
337 }
338
339 isfw_read = _rtl88e_check_fw_read_last_h2c(hw, boxnum);
340 while (!isfw_read) {
341 wait_h2c_limit--;
342 if (wait_h2c_limit == 0) {
343 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
344 "Wating too long for FW read "
345 "clear HMEBox(%d)!\n", boxnum);
346 break;
347 }
348
349 udelay(10);
350
351 isfw_read = _rtl88e_check_fw_read_last_h2c(hw, boxnum);
352 u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
353 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
354 "Wating for FW read clear HMEBox(%d)!!! "
355 "0x130 = %2x\n", boxnum, u1b_tmp);
356 }
357
358 if (!isfw_read) {
359 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
360 "Write H2C register BOX[%d] fail!!!!! "
361 "Fw do not read.\n", boxnum);
362 break;
363 }
364
365 memset(boxc, 0, sizeof(boxc));
366 memset(boxext, 0, sizeof(boxext));
367 boxc[0] = element_id;
368 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
369 "Write element_id box_reg(%4x) = %2x\n",
370 box_reg, element_id);
371
372 switch (cmd_len) {
373 case 1:
374 case 2:
375 case 3:
376 /*boxc[0] &= ~(BIT(7));*/
377 memcpy((u8 *)(boxc) + 1, cmd_b + buf_index, cmd_len);
378
379 for (idx = 0; idx < 4; idx++)
380 rtl_write_byte(rtlpriv, box_reg+idx, boxc[idx]);
381 break;
382 case 4:
383 case 5:
384 case 6:
385 case 7:
386 /*boxc[0] |= (BIT(7));*/
387 memcpy((u8 *)(boxext), cmd_b + buf_index+3, cmd_len-3);
388 memcpy((u8 *)(boxc) + 1, cmd_b + buf_index, 3);
389
390 for (idx = 0; idx < 2; idx++) {
391 rtl_write_byte(rtlpriv, box_extreg + idx,
392 boxext[idx]);
393 }
394
395 for (idx = 0; idx < 4; idx++) {
396 rtl_write_byte(rtlpriv, box_reg + idx,
397 boxc[idx]);
398 }
399 break;
400 default:
401 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
402 "switch case not processed\n");
403 break;
404 }
405
406 write_sucess = true;
407
408 rtlhal->last_hmeboxnum = boxnum + 1;
409 if (rtlhal->last_hmeboxnum == 4)
410 rtlhal->last_hmeboxnum = 0;
411
412 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
413 "pHalData->last_hmeboxnum = %d\n",
414 rtlhal->last_hmeboxnum);
415 }
416
417 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
418 rtlhal->h2c_setinprogress = false;
419 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
420
421 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
422}
423
424void rtl88e_fill_h2c_cmd(struct ieee80211_hw *hw,
425 u8 element_id, u32 cmd_len, u8 *cmd_b)
426{
427 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
428 u32 tmp_cmdbuf[2];
429
430 if (rtlhal->fw_ready == false) {
431 RT_ASSERT(false, "fail H2C cmd - Fw download fail!!!\n");
432 return;
433 }
434
435 memset(tmp_cmdbuf, 0, 8);
436 memcpy(tmp_cmdbuf, cmd_b, cmd_len);
437 _rtl88e_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
438
439 return;
440}
441
442void rtl88e_firmware_selfreset(struct ieee80211_hw *hw)
443{
444 u8 u1b_tmp;
445 struct rtl_priv *rtlpriv = rtl_priv(hw);
446
447 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
448 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
449 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp | BIT(2)));
450 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
451 "8051Reset88E(): 8051 reset success.\n");
452}
453
454void rtl88e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
455{
456 struct rtl_priv *rtlpriv = rtl_priv(hw);
457 u8 u1_h2c_set_pwrmode[H2C_88E_PWEMODE_LENGTH] = { 0 };
458 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
459 u8 power_state = 0;
460
461 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
462 SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
463 SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, 0);
464 SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
465 (rtlpriv->mac80211.p2p) ?
466 ppsc->smart_ps : 1);
467 SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
468 ppsc->reg_max_lps_awakeintvl);
469 SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
470 if (mode == FW_PS_ACTIVE_MODE)
471 power_state |= FW_PWR_STATE_ACTIVE;
472 else
473 power_state |= FW_PWR_STATE_RF_OFF;
474 SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
475
476 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
477 "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
478 u1_h2c_set_pwrmode, H2C_88E_PWEMODE_LENGTH);
479 rtl88e_fill_h2c_cmd(hw, H2C_88E_SETPWRMODE, H2C_88E_PWEMODE_LENGTH,
480 u1_h2c_set_pwrmode);
481}
482
483void rtl88e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
484{
485 u8 u1_joinbssrpt_parm[1] = { 0 };
486
487 SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
488
489 rtl88e_fill_h2c_cmd(hw, H2C_88E_JOINBSSRPT, 1, u1_joinbssrpt_parm);
490}
491
492void rtl88e_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw,
493 u8 ap_offload_enable)
494{
495 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
496 u8 u1_apoffload_parm[H2C_88E_AP_OFFLOAD_LENGTH] = { 0 };
497
498 SET_H2CCMD_AP_OFFLOAD_ON(u1_apoffload_parm, ap_offload_enable);
499 SET_H2CCMD_AP_OFFLOAD_HIDDEN(u1_apoffload_parm, mac->hiddenssid);
500 SET_H2CCMD_AP_OFFLOAD_DENYANY(u1_apoffload_parm, 0);
501
502 rtl88e_fill_h2c_cmd(hw, H2C_88E_AP_OFFLOAD, H2C_88E_AP_OFFLOAD_LENGTH,
503 u1_apoffload_parm);
504}
505
506static bool _rtl88e_cmd_send_packet(struct ieee80211_hw *hw,
507 struct sk_buff *skb)
508{
509 struct rtl_priv *rtlpriv = rtl_priv(hw);
510 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
511 struct rtl8192_tx_ring *ring;
512 struct rtl_tx_desc *pdesc;
513 struct sk_buff *pskb = NULL;
514 unsigned long flags;
515
516 ring = &rtlpci->tx_ring[BEACON_QUEUE];
517
518 pskb = __skb_dequeue(&ring->queue);
519 if (pskb)
520 kfree_skb(pskb);
521
522 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
523
524 pdesc = &ring->desc[0];
525
526 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
527
528 __skb_queue_tail(&ring->queue, skb);
529
530 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
531
532 rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
533
534 return true;
535}
536
537#define BEACON_PG 0 /* ->1 */
538#define PSPOLL_PG 2
539#define NULL_PG 3
540#define PROBERSP_PG 4 /* ->5 */
541
542#define TOTAL_RESERVED_PKT_LEN 768
543
544static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
545 /* page 0 beacon */
546 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
547 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
548 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
549 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
550 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
551 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
552 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
553 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
554 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
555 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
556 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
557 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
558 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
559 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
560 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
561 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
562
563 /* page 1 beacon */
564 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
565 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
566 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
567 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
568 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
569 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
570 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
571 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
572 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
573 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
574 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
575 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
576 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
577 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
578 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
579 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
580
581 /* page 2 ps-poll */
582 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
583 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
584 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
585 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
586 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
587 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
588 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
589 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
590 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
591 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
592 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
593 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
594 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
595 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
596 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
597 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
598
599 /* page 3 null */
600 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
601 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
602 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
603 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
604 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
606 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
607 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
608 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
609 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
610 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
611 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
612 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
613 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
614 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
616
617 /* page 4 probe_resp */
618 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
619 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
620 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
621 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
622 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
623 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
624 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
625 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
626 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
627 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
628 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
629 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
630 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
631 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
632 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
633 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
634
635 /* page 5 probe_resp */
636 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
637 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
638 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
639 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
640 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
641 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
642 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
643 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
644 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
646 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
647 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
648 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
649 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
650 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
651 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
652};
653
654void rtl88e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
655{
656 struct rtl_priv *rtlpriv = rtl_priv(hw);
657 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
658 struct sk_buff *skb = NULL;
659
660 u32 totalpacketlen;
661 u8 u1RsvdPageLoc[5] = { 0 };
662
663 u8 *beacon;
664 u8 *pspoll;
665 u8 *nullfunc;
666 u8 *probersp;
667 /*---------------------------------------------------------
668 * (1) beacon
669 *---------------------------------------------------------
670 */
671 beacon = &reserved_page_packet[BEACON_PG * 128];
672 SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
673 SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
674
675 /*-------------------------------------------------------
676 * (2) ps-poll
677 *--------------------------------------------------------
678 */
679 pspoll = &reserved_page_packet[PSPOLL_PG * 128];
680 SET_80211_PS_POLL_AID(pspoll, (mac->assoc_id | 0xc000));
681 SET_80211_PS_POLL_BSSID(pspoll, mac->bssid);
682 SET_80211_PS_POLL_TA(pspoll, mac->mac_addr);
683
684 SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
685
686 /*--------------------------------------------------------
687 * (3) null data
688 *---------------------------------------------------------
689 */
690 nullfunc = &reserved_page_packet[NULL_PG * 128];
691 SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
692 SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
693 SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
694
695 SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
696
697 /*---------------------------------------------------------
698 * (4) probe response
699 *----------------------------------------------------------
700 */
701 probersp = &reserved_page_packet[PROBERSP_PG * 128];
702 SET_80211_HDR_ADDRESS1(probersp, mac->bssid);
703 SET_80211_HDR_ADDRESS2(probersp, mac->mac_addr);
704 SET_80211_HDR_ADDRESS3(probersp, mac->bssid);
705
706 SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
707
708 totalpacketlen = TOTAL_RESERVED_PKT_LEN;
709
710 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
711 "rtl88e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
712 &reserved_page_packet[0], totalpacketlen);
713 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
714 "rtl88e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
715 u1RsvdPageLoc, 3);
716
717 skb = dev_alloc_skb(totalpacketlen);
718 if (!skb)
719 return;
720 kmemleak_not_leak(skb);
721 memcpy(skb_put(skb, totalpacketlen),
722 &reserved_page_packet, totalpacketlen);
723
724 if (_rtl88e_cmd_send_packet(hw, skb)) {
725 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
726 "Set RSVD page location to Fw.\n");
727 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
728 "H2C_RSVDPAGE:\n", u1RsvdPageLoc, 3);
729 rtl88e_fill_h2c_cmd(hw, H2C_88E_RSVDPAGE,
730 sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
731 } else
732 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
733 "Set RSVD page location to Fw FAIL!!!!!!.\n");
734}
735
736/*Shoud check FW support p2p or not.*/
737static void rtl88e_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
738{
739 u8 u1_ctwindow_period[1] = {ctwindow};
740
741 rtl88e_fill_h2c_cmd(hw, H2C_88E_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
742}
743
744void rtl88e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
745{
746 struct rtl_priv *rtlpriv = rtl_priv(hw);
747 struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
748 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
749 struct rtl_p2p_ps_info *p2pinfo = &(rtlps->p2p_ps_info);
750 struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
751 u8 i;
752 u16 ctwindow;
753 u32 start_time, tsf_low;
754
755 switch (p2p_ps_state) {
756 case P2P_PS_DISABLE:
757 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
758 memset(p2p_ps_offload, 0, sizeof(struct p2p_ps_offload_t));
759 break;
760 case P2P_PS_ENABLE:
761 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
762 /* update CTWindow value. */
763 if (p2pinfo->ctwindow > 0) {
764 p2p_ps_offload->ctwindow_en = 1;
765 ctwindow = p2pinfo->ctwindow;
766 rtl88e_set_p2p_ctw_period_cmd(hw, ctwindow);
767 }
768 /* hw only support 2 set of NoA */
769 for (i = 0; i < p2pinfo->noa_num; i++) {
770 /* To control the register setting for which NOA*/
771 rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
772 if (i == 0)
773 p2p_ps_offload->noa0_en = 1;
774 else
775 p2p_ps_offload->noa1_en = 1;
776
777 /* config P2P NoA Descriptor Register */
778 rtl_write_dword(rtlpriv, 0x5E0,
779 p2pinfo->noa_duration[i]);
780 rtl_write_dword(rtlpriv, 0x5E4,
781 p2pinfo->noa_interval[i]);
782
783 /*Get Current TSF value */
784 tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
785
786 start_time = p2pinfo->noa_start_time[i];
787 if (p2pinfo->noa_count_type[i] != 1) {
788 while (start_time <= (tsf_low + (50 * 1024))) {
789 start_time += p2pinfo->noa_interval[i];
790 if (p2pinfo->noa_count_type[i] != 255)
791 p2pinfo->noa_count_type[i]--;
792 }
793 }
794 rtl_write_dword(rtlpriv, 0x5E8, start_time);
795 rtl_write_dword(rtlpriv, 0x5EC,
796 p2pinfo->noa_count_type[i]);
797 }
798
799 if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
800 /* rst p2p circuit */
801 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
802
803 p2p_ps_offload->offload_en = 1;
804
805 if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
806 p2p_ps_offload->role = 1;
807 p2p_ps_offload->allstasleep = 0;
808 } else {
809 p2p_ps_offload->role = 0;
810 }
811
812 p2p_ps_offload->discovery = 0;
813 }
814 break;
815 case P2P_PS_SCAN:
816 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN\n");
817 p2p_ps_offload->discovery = 1;
818 break;
819 case P2P_PS_SCAN_DONE:
820 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN_DONE\n");
821 p2p_ps_offload->discovery = 0;
822 p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
823 break;
824 default:
825 break;
826 }
827
828 rtl88e_fill_h2c_cmd(hw, H2C_88E_P2P_PS_OFFLOAD, 1,
829 (u8 *)p2p_ps_offload);
830}
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/fw.h b/drivers/net/wireless/rtlwifi/rtl8188ee/fw.h
new file mode 100644
index 000000000000..854a9875cd5f
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/fw.h
@@ -0,0 +1,301 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 * Larry Finger <Larry.Finger@lwfinger.net>
26 *
27 *****************************************************************************/
28
29#ifndef __RTL92C__FW__H__
30#define __RTL92C__FW__H__
31
32#define FW_8192C_SIZE 0x8000
33#define FW_8192C_START_ADDRESS 0x1000
34#define FW_8192C_END_ADDRESS 0x5FFF
35#define FW_8192C_PAGE_SIZE 4096
36#define FW_8192C_POLLING_DELAY 5
37#define FW_8192C_POLLING_TIMEOUT_COUNT 3000
38
39#define IS_FW_HEADER_EXIST(_pfwhdr) \
40 ((_pfwhdr->signature&0xFFFF) == 0x88E1)
41#define USE_OLD_WOWLAN_DEBUG_FW 0
42
43#define H2C_88E_RSVDPAGE_LOC_LEN 5
44#define H2C_88E_PWEMODE_LENGTH 5
45#define H2C_88E_JOINBSSRPT_LENGTH 1
46#define H2C_88E_AP_OFFLOAD_LENGTH 3
47#define H2C_88E_WOWLAN_LENGTH 3
48#define H2C_88E_KEEP_ALIVE_CTRL_LENGTH 3
49#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
50#define H2C_88E_REMOTE_WAKE_CTRL_LEN 1
51#else
52#define H2C_88E_REMOTE_WAKE_CTRL_LEN 3
53#endif
54#define H2C_88E_AOAC_GLOBAL_INFO_LEN 2
55#define H2C_88E_AOAC_RSVDPAGE_LOC_LEN 7
56
57/* Fw PS state for RPWM.
58 * BIT[2:0] = HW state
59 * BIT[3] = Protocol PS state, 1: register active state, 0: register sleep state
60 * BIT[4] = sub-state
61 */
62#define FW_PS_GO_ON BIT(0)
63#define FW_PS_TX_NULL BIT(1)
64#define FW_PS_RF_ON BIT(2)
65#define FW_PS_REGISTER_ACTIVE BIT(3)
66
67#define FW_PS_DPS BIT(0)
68#define FW_PS_LCLK (FW_PS_DPS)
69#define FW_PS_RF_OFF BIT(1)
70#define FW_PS_ALL_ON BIT(2)
71#define FW_PS_ST_ACTIVE BIT(3)
72#define FW_PS_ISR_ENABLE BIT(4)
73#define FW_PS_IMR_ENABLE BIT(5)
74
75
76#define FW_PS_ACK BIT(6)
77#define FW_PS_TOGGLE BIT(7)
78
79 /* 88E RPWM value*/
80 /* BIT[0] = 1: 32k, 0: 40M*/
81#define FW_PS_CLOCK_OFF BIT(0) /* 32k*/
82#define FW_PS_CLOCK_ON 0 /*40M*/
83
84#define FW_PS_STATE_MASK (0x0F)
85#define FW_PS_STATE_HW_MASK (0x07)
86/*ISR_ENABLE, IMR_ENABLE, and PS mode should be inherited.*/
87#define FW_PS_STATE_INT_MASK (0x3F)
88
89#define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x))
90#define FW_PS_STATE_HW(x) (FW_PS_STATE_HW_MASK & (x))
91#define FW_PS_STATE_INT(x) (FW_PS_STATE_INT_MASK & (x))
92#define FW_PS_ISR_VAL(x) ((x) & 0x70)
93#define FW_PS_IMR_MASK(x) ((x) & 0xDF)
94#define FW_PS_KEEP_IMR(x) ((x) & 0x20)
95
96#define FW_PS_STATE_S0 (FW_PS_DPS)
97#define FW_PS_STATE_S1 (FW_PS_LCLK)
98#define FW_PS_STATE_S2 (FW_PS_RF_OFF)
99#define FW_PS_STATE_S3 (FW_PS_ALL_ON)
100#define FW_PS_STATE_S4 ((FW_PS_ST_ACTIVE) | (FW_PS_ALL_ON))
101
102#define FW_PS_STATE_ALL_ON_88E (FW_PS_CLOCK_ON)
103#define FW_PS_STATE_RF_ON_88E (FW_PS_CLOCK_ON)
104#define FW_PS_STATE_RF_OFF_88E (FW_PS_CLOCK_ON)
105#define FW_PS_STATE_RF_OFF_LOW_PWR_88E (FW_PS_CLOCK_OFF)
106
107#define FW_PS_STATE_ALL_ON_92C (FW_PS_STATE_S4)
108#define FW_PS_STATE_RF_ON_92C (FW_PS_STATE_S3)
109#define FW_PS_STATE_RF_OFF_92C (FW_PS_STATE_S2)
110#define FW_PS_STATE_RF_OFF_LOW_PWR_92C (FW_PS_STATE_S1)
111
112/* For 88E H2C PwrMode Cmd ID 5.*/
113#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
114#define FW_PWR_STATE_RF_OFF 0
115
116#define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK)
117#define FW_PS_IS_CLK_ON(x) ((x) & (FW_PS_RF_OFF | FW_PS_ALL_ON))
118#define FW_PS_IS_RF_ON(x) ((x) & (FW_PS_ALL_ON))
119#define FW_PS_IS_ACTIVE(x) ((x) & (FW_PS_ST_ACTIVE))
120#define FW_PS_IS_CPWM_INT(x) ((x) & 0x40)
121
122#define FW_CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
123
124#define IS_IN_LOW_POWER_STATE_88E(fwpsstate) \
125 (FW_PS_STATE(fwpsstate) == FW_PS_CLOCK_OFF)
126
127#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
128#define FW_PWR_STATE_RF_OFF 0
129
130struct rtl92c_firmware_header {
131 u16 signature;
132 u8 category;
133 u8 function;
134 u16 version;
135 u8 subversion;
136 u8 rsvd1;
137 u8 month;
138 u8 date;
139 u8 hour;
140 u8 minute;
141 u16 ramcodesize;
142 u16 rsvd2;
143 u32 svnindex;
144 u32 rsvd3;
145 u32 rsvd4;
146 u32 rsvd5;
147};
148
149enum rtl8192c_h2c_cmd {
150 H2C_88E_RSVDPAGE = 0,
151 H2C_88E_JOINBSSRPT = 1,
152 H2C_88E_SCAN = 2,
153 H2C_88E_KEEP_ALIVE_CTRL = 3,
154 H2C_88E_DISCONNECT_DECISION = 4,
155#if (USE_OLD_WOWLAN_DEBUG_FW == 1)
156 H2C_88E_WO_WLAN = 5,
157#endif
158 H2C_88E_INIT_OFFLOAD = 6,
159#if (USE_OLD_WOWLAN_DEBUG_FW == 1)
160 H2C_88E_REMOTE_WAKE_CTRL = 7,
161#endif
162 H2C_88E_AP_OFFLOAD = 8,
163 H2C_88E_BCN_RSVDPAGE = 9,
164 H2C_88E_PROBERSP_RSVDPAGE = 10,
165
166 H2C_88E_SETPWRMODE = 0x20,
167 H2C_88E_PS_TUNING_PARA = 0x21,
168 H2C_88E_PS_TUNING_PARA2 = 0x22,
169 H2C_88E_PS_LPS_PARA = 0x23,
170 H2C_88E_P2P_PS_OFFLOAD = 024,
171
172#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
173 H2C_88E_WO_WLAN = 0x80,
174 H2C_88E_REMOTE_WAKE_CTRL = 0x81,
175 H2C_88E_AOAC_GLOBAL_INFO = 0x82,
176 H2C_88E_AOAC_RSVDPAGE = 0x83,
177#endif
178 /* Not defined in new 88E H2C CMD Format */
179 H2C_88E_RA_MASK,
180 H2C_88E_SELECTIVE_SUSPEND_ROF_CMD,
181 H2C_88E_P2P_PS_MODE,
182 H2C_88E_PSD_RESULT,
183 /*Not defined CTW CMD for P2P yet*/
184 H2C_88E_P2P_PS_CTW_CMD,
185 MAX_88E_H2CCMD
186};
187
188#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
189
190#define SET_88E_H2CCMD_WOWLAN_FUNC_ENABLE(__cmd, __value) \
191 SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
192#define SET_88E_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__cmd, __value) \
193 SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
194#define SET_88E_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__cmd, __value) \
195 SET_BITS_TO_LE_1BYTE(__cmd, 2, 1, __value)
196#define SET_88E_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__cmd, __value) \
197 SET_BITS_TO_LE_1BYTE(__cmd, 3, 1, __value)
198#define SET_88E_H2CCMD_WOWLAN_ALL_PKT_DROP(__cmd, __value) \
199 SET_BITS_TO_LE_1BYTE(__cmd, 4, 1, __value)
200#define SET_88E_H2CCMD_WOWLAN_GPIO_ACTIVE(__cmd, __value) \
201 SET_BITS_TO_LE_1BYTE(__cmd, 5, 1, __value)
202#define SET_88E_H2CCMD_WOWLAN_REKEY_WAKE_UP(__cmd, __value) \
203 SET_BITS_TO_LE_1BYTE(__cmd, 6, 1, __value)
204#define SET_88E_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__cmd, __value) \
205 SET_BITS_TO_LE_1BYTE(__cmd, 7, 1, __value)
206#define SET_88E_H2CCMD_WOWLAN_GPIONUM(__cmd, __value) \
207 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
208#define SET_88E_H2CCMD_WOWLAN_GPIO_DURATION(__cmd, __value) \
209 SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
210
211
212#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
213 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
214#define SET_H2CCMD_PWRMODE_PARM_RLBM(__cmd, __value) \
215 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 4, __value)
216#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__cmd, __value) \
217 SET_BITS_TO_LE_1BYTE((__cmd)+1, 4, 4, __value)
218#define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__cmd, __value) \
219 SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
220#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__cmd, __value) \
221 SET_BITS_TO_LE_1BYTE((__cmd)+3, 0, 8, __value)
222#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__cmd, __value) \
223 SET_BITS_TO_LE_1BYTE((__cmd)+4, 0, 8, __value)
224#define GET_88E_H2CCMD_PWRMODE_PARM_MODE(__cmd) \
225 LE_BITS_TO_1BYTE(__cmd, 0, 8)
226
227#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \
228 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
229#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \
230 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
231#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
232 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
233#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
234 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
235
236/* AP_OFFLOAD */
237#define SET_H2CCMD_AP_OFFLOAD_ON(__cmd, __value) \
238 SET_BITS_TO_LE_1BYTE(__cmd, 0, 8, __value)
239#define SET_H2CCMD_AP_OFFLOAD_HIDDEN(__cmd, __value) \
240 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
241#define SET_H2CCMD_AP_OFFLOAD_DENYANY(__cmd, __value) \
242 SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
243#define SET_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__cmd, __value) \
244 SET_BITS_TO_LE_1BYTE((__cmd)+3, 0, 8, __value)
245
246/* Keep Alive Control*/
247#define SET_88E_H2CCMD_KEEP_ALIVE_ENABLE(__cmd, __value) \
248 SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
249#define SET_88E_H2CCMD_KEEP_ALIVE_ACCPEPT_USER_DEFINED(__cmd, __value) \
250 SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
251#define SET_88E_H2CCMD_KEEP_ALIVE_PERIOD(__cmd, __value) \
252 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
253
254/*REMOTE_WAKE_CTRL */
255#define SET_88E_H2CCMD_REMOTE_WAKE_CTRL_EN(__cmd, __value) \
256 SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __value)
257#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
258#define SET_88E_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__cmd, __value) \
259 SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __value)
260#define SET_88E_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__cmd, __value) \
261 SET_BITS_TO_LE_1BYTE(__cmd, 2, 1, __value)
262#define SET_88E_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__cmd, __value) \
263 SET_BITS_TO_LE_1BYTE(__cmd, 3, 1, __value)
264#else
265#define SET_88E_H2_REM_WAKE_ENC_ALG(__cmd, __value) \
266 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
267#define SET_88E_H2CCMD_REMOTE_WAKE_CTRL_GROUP_ENC_ALG(__cmd, __value) \
268 SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
269#endif
270
271/* GTK_OFFLOAD */
272#define SET_88E_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__cmd, __value) \
273 SET_BITS_TO_LE_1BYTE(__cmd, 0, 8, __value)
274#define SET_88E_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__cmd, __value) \
275 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
276
277/* AOAC_RSVDPAGE_LOC */
278#define SET_88E_H2CCMD_AOAC_RSVD_LOC_REM_WAKE_CTRL_INFO(__cmd, __value) \
279 SET_BITS_TO_LE_1BYTE((__cmd), 0, 8, __value)
280#define SET_88E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__cmd, __value) \
281 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 8, __value)
282#define SET_88E_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__cmd, __value) \
283 SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __value)
284#define SET_88E_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__cmd, __value) \
285 SET_BITS_TO_LE_1BYTE((__cmd)+3, 0, 8, __value)
286#define SET_88E_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__cmd, __value) \
287 SET_BITS_TO_LE_1BYTE((__cmd)+4, 0, 8, __value)
288
289int rtl88e_download_fw(struct ieee80211_hw *hw,
290 bool buse_wake_on_wlan_fw);
291void rtl88e_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
292 u32 cmd_len, u8 *p_cmdbuffer);
293void rtl88e_firmware_selfreset(struct ieee80211_hw *hw);
294void rtl88e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
295void rtl88e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
296 u8 mstatus);
297void rtl88e_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw, u8 enable);
298void rtl88e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
299void rtl88e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
300
301#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/hw.c b/drivers/net/wireless/rtlwifi/rtl8188ee/hw.c
new file mode 100644
index 000000000000..d734d19a066f
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/hw.c
@@ -0,0 +1,2529 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "efuse.h"
32#include "base.h"
33#include "regd.h"
34#include "cam.h"
35#include "ps.h"
36#include "pci.h"
37#include "reg.h"
38#include "def.h"
39#include "phy.h"
40#include "dm.h"
41#include "fw.h"
42#include "led.h"
43#include "hw.h"
44#include "pwrseqcmd.h"
45#include "pwrseq.h"
46
47#define LLT_CONFIG 5
48
49static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
50 u8 set_bits, u8 clear_bits)
51{
52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
53 struct rtl_priv *rtlpriv = rtl_priv(hw);
54
55 rtlpci->reg_bcn_ctrl_val |= set_bits;
56 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
57
58 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
59}
60
61static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
62{
63 struct rtl_priv *rtlpriv = rtl_priv(hw);
64 u8 tmp1byte;
65
66 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
67 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
68 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
69 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
70 tmp1byte &= ~(BIT(0));
71 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
72}
73
74static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
75{
76 struct rtl_priv *rtlpriv = rtl_priv(hw);
77 u8 tmp1byte;
78
79 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
80 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
81 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
82 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
83 tmp1byte |= BIT(0);
84 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
85}
86
87static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
88{
89 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
90}
91
92static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
93{
94 struct rtl_priv *rtlpriv = rtl_priv(hw);
95 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
96 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
97
98 while (skb_queue_len(&ring->queue)) {
99 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
100 struct sk_buff *skb = __skb_dequeue(&ring->queue);
101
102 pci_unmap_single(rtlpci->pdev,
103 rtlpriv->cfg->ops->get_desc(
104 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
105 skb->len, PCI_DMA_TODEVICE);
106 kfree_skb(skb);
107 ring->idx = (ring->idx + 1) % ring->entries;
108 }
109}
110
111static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
112{
113 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
114}
115
116static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
117 u8 rpwm_val, bool need_turn_off_ckk)
118{
119 struct rtl_priv *rtlpriv = rtl_priv(hw);
120 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
121 bool support_remote_wake_up;
122 u32 count = 0, isr_regaddr, content;
123 bool schedule_timer = need_turn_off_ckk;
124
125 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
126 (u8 *)(&support_remote_wake_up));
127 if (!rtlhal->fw_ready)
128 return;
129 if (!rtlpriv->psc.fw_current_inpsmode)
130 return;
131
132 while (1) {
133 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
134 if (rtlhal->fw_clk_change_in_progress) {
135 while (rtlhal->fw_clk_change_in_progress) {
136 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
137 udelay(100);
138 if (++count > 1000)
139 return;
140 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
141 }
142 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
143 } else {
144 rtlhal->fw_clk_change_in_progress = false;
145 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
146 }
147 }
148
149 if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
150 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
151 (u8 *)(&rpwm_val));
152 if (FW_PS_IS_ACK(rpwm_val)) {
153 isr_regaddr = REG_HISR;
154 content = rtl_read_dword(rtlpriv, isr_regaddr);
155 while (!(content & IMR_CPWM) && (count < 500)) {
156 udelay(50);
157 count++;
158 content = rtl_read_dword(rtlpriv, isr_regaddr);
159 }
160
161 if (content & IMR_CPWM) {
162 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
163 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
164 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
165 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
166 rtlhal->fw_ps_state);
167 }
168 }
169
170 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
171 rtlhal->fw_clk_change_in_progress = false;
172 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
173 if (schedule_timer) {
174 mod_timer(&rtlpriv->works.fw_clockoff_timer,
175 jiffies + MSECS(10));
176 }
177 } else {
178 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
179 rtlhal->fw_clk_change_in_progress = false;
180 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
181 }
182}
183
184static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
185 u8 rpwm_val)
186{
187 struct rtl_priv *rtlpriv = rtl_priv(hw);
188 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
189 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
190 struct rtl8192_tx_ring *ring;
191 enum rf_pwrstate rtstate;
192 bool schedule_timer = false;
193 u8 queue;
194
195 if (!rtlhal->fw_ready)
196 return;
197 if (!rtlpriv->psc.fw_current_inpsmode)
198 return;
199 if (!rtlhal->allow_sw_to_change_hwclc)
200 return;
201 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
202 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
203 return;
204
205 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
206 ring = &rtlpci->tx_ring[queue];
207 if (skb_queue_len(&ring->queue)) {
208 schedule_timer = true;
209 break;
210 }
211 }
212
213 if (schedule_timer) {
214 mod_timer(&rtlpriv->works.fw_clockoff_timer,
215 jiffies + MSECS(10));
216 return;
217 }
218
219 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
220 FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
221 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
222 if (!rtlhal->fw_clk_change_in_progress) {
223 rtlhal->fw_clk_change_in_progress = true;
224 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
225 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
226 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
227 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
228 (u8 *)(&rpwm_val));
229 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
230 rtlhal->fw_clk_change_in_progress = false;
231 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
232 } else {
233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
234 mod_timer(&rtlpriv->works.fw_clockoff_timer,
235 jiffies + MSECS(10));
236 }
237 }
238}
239
240static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
241{
242 u8 rpwm_val = 0;
243
244 rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
245 _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
246}
247
248static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
249{
250 u8 rpwm_val = 0;
251
252 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
253 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
254}
255
256void rtl88ee_fw_clk_off_timer_callback(unsigned long data)
257{
258 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
259
260 _rtl88ee_set_fw_ps_rf_off_low_power(hw);
261}
262
263static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
264{
265 struct rtl_priv *rtlpriv = rtl_priv(hw);
266 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
267 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
268 bool fw_current_inps = false;
269 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
270
271 if (ppsc->low_power_enable) {
272 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
273 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
274 rtlhal->allow_sw_to_change_hwclc = false;
275 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
276 (u8 *)(&fw_pwrmode));
277 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
278 (u8 *)(&fw_current_inps));
279 } else {
280 rpwm_val = FW_PS_STATE_ALL_ON_88E; /* RF on */
281 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
282 (u8 *)(&rpwm_val));
283 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
284 (u8 *)(&fw_pwrmode));
285 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
286 (u8 *)(&fw_current_inps));
287 }
288}
289
290static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
291{
292 struct rtl_priv *rtlpriv = rtl_priv(hw);
293 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
294 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
295 bool fw_current_inps = true;
296 u8 rpwm_val;
297
298 if (ppsc->low_power_enable) {
299 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E; /* RF off */
300 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
301 (u8 *)(&fw_current_inps));
302 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
303 (u8 *)(&ppsc->fwctrl_psmode));
304 rtlhal->allow_sw_to_change_hwclc = true;
305 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
306 } else {
307 rpwm_val = FW_PS_STATE_RF_OFF_88E; /* RF off */
308 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
309 (u8 *)(&fw_current_inps));
310 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
311 (u8 *)(&ppsc->fwctrl_psmode));
312 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
313 (u8 *)(&rpwm_val));
314 }
315}
316
317void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
318{
319 struct rtl_priv *rtlpriv = rtl_priv(hw);
320 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
321 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
322
323 switch (variable) {
324 case HW_VAR_RCR:
325 *((u32 *)(val)) = rtlpci->receive_config;
326 break;
327 case HW_VAR_RF_STATE:
328 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
329 break;
330 case HW_VAR_FWLPS_RF_ON:{
331 enum rf_pwrstate rfstate;
332 u32 val_rcr;
333
334 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
335 (u8 *)(&rfstate));
336 if (rfstate == ERFOFF) {
337 *((bool *)(val)) = true;
338 } else {
339 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
340 val_rcr &= 0x00070000;
341 if (val_rcr)
342 *((bool *)(val)) = false;
343 else
344 *((bool *)(val)) = true;
345 }
346 break;
347 }
348 case HW_VAR_FW_PSMODE_STATUS:
349 *((bool *)(val)) = ppsc->fw_current_inpsmode;
350 break;
351 case HW_VAR_CORRECT_TSF:{
352 u64 tsf;
353 u32 *ptsf_low = (u32 *)&tsf;
354 u32 *ptsf_high = ((u32 *)&tsf) + 1;
355
356 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
357 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
358
359 *((u64 *)(val)) = tsf;
360 break; }
361 default:
362 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
363 "switch case not process %x\n", variable);
364 break;
365 }
366}
367
368void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
369{
370 struct rtl_priv *rtlpriv = rtl_priv(hw);
371 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
372 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
373 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
374 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
375 u8 idx;
376
377 switch (variable) {
378 case HW_VAR_ETHER_ADDR:
379 for (idx = 0; idx < ETH_ALEN; idx++)
380 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
381 break;
382 case HW_VAR_BASIC_RATE:{
383 u16 rate_cfg = ((u16 *)val)[0];
384 u8 rate_index = 0;
385 rate_cfg = rate_cfg & 0x15f;
386 rate_cfg |= 0x01;
387 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
388 rtl_write_byte(rtlpriv, REG_RRSR + 1, (rate_cfg >> 8) & 0xff);
389 while (rate_cfg > 0x1) {
390 rate_cfg = (rate_cfg >> 1);
391 rate_index++;
392 }
393 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
394 break; }
395 case HW_VAR_BSSID:
396 for (idx = 0; idx < ETH_ALEN; idx++)
397 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
398 break;
399 case HW_VAR_SIFS:
400 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
401 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
402
403 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
404 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
405
406 if (!mac->ht_enable)
407 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
408 else
409 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
410 *((u16 *)val));
411 break;
412 case HW_VAR_SLOT_TIME:{
413 u8 e_aci;
414
415 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
416 "HW_VAR_SLOT_TIME %x\n", val[0]);
417
418 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
419
420 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
421 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
422 (u8 *)(&e_aci));
423 }
424 break; }
425 case HW_VAR_ACK_PREAMBLE:{
426 u8 reg_tmp;
427 u8 short_preamble = (bool) (*(u8 *)val);
428 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
429 if (short_preamble) {
430 reg_tmp |= 0x02;
431 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
432 } else {
433 reg_tmp |= 0xFD;
434 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
435 }
436 break; }
437 case HW_VAR_WPA_CONFIG:
438 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
439 break;
440 case HW_VAR_AMPDU_MIN_SPACE:{
441 u8 min_spacing_to_set;
442 u8 sec_min_space;
443
444 min_spacing_to_set = *((u8 *)val);
445 if (min_spacing_to_set <= 7) {
446 sec_min_space = 0;
447
448 if (min_spacing_to_set < sec_min_space)
449 min_spacing_to_set = sec_min_space;
450
451 mac->min_space_cfg = ((mac->min_space_cfg &
452 0xf8) | min_spacing_to_set);
453
454 *val = min_spacing_to_set;
455
456 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
457 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
458 mac->min_space_cfg);
459
460 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
461 mac->min_space_cfg);
462 }
463 break; }
464 case HW_VAR_SHORTGI_DENSITY:{
465 u8 density_to_set;
466
467 density_to_set = *((u8 *)val);
468 mac->min_space_cfg |= (density_to_set << 3);
469
470 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
471 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
472 mac->min_space_cfg);
473
474 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
475 mac->min_space_cfg);
476 break; }
477 case HW_VAR_AMPDU_FACTOR:{
478 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
479 u8 factor;
480 u8 *reg = NULL;
481 u8 id = 0;
482
483 reg = regtoset_normal;
484
485 factor = *((u8 *)val);
486 if (factor <= 3) {
487 factor = (1 << (factor + 2));
488 if (factor > 0xf)
489 factor = 0xf;
490
491 for (id = 0; id < 4; id++) {
492 if ((reg[id] & 0xf0) > (factor << 4))
493 reg[id] = (reg[id] & 0x0f) |
494 (factor << 4);
495
496 if ((reg[id] & 0x0f) > factor)
497 reg[id] = (reg[id] & 0xf0) | (factor);
498
499 rtl_write_byte(rtlpriv, (REG_AGGLEN_LMT + id),
500 reg[id]);
501 }
502
503 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
504 "Set HW_VAR_AMPDU_FACTOR: %#x\n", factor);
505 }
506 break; }
507 case HW_VAR_AC_PARAM:{
508 u8 e_aci = *((u8 *)val);
509 rtl88e_dm_init_edca_turbo(hw);
510
511 if (rtlpci->acm_method != eAcmWay2_SW)
512 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
513 (u8 *)(&e_aci));
514 break; }
515 case HW_VAR_ACM_CTRL:{
516 u8 e_aci = *((u8 *)val);
517 union aci_aifsn *p_aci_aifsn =
518 (union aci_aifsn *)(&(mac->ac[0].aifs));
519 u8 acm = p_aci_aifsn->f.acm;
520 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
521
522 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
523
524 if (acm) {
525 switch (e_aci) {
526 case AC0_BE:
527 acm_ctrl |= ACMHW_BEQEN;
528 break;
529 case AC2_VI:
530 acm_ctrl |= ACMHW_VIQEN;
531 break;
532 case AC3_VO:
533 acm_ctrl |= ACMHW_VOQEN;
534 break;
535 default:
536 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
537 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
538 acm);
539 break;
540 }
541 } else {
542 switch (e_aci) {
543 case AC0_BE:
544 acm_ctrl &= (~ACMHW_BEQEN);
545 break;
546 case AC2_VI:
547 acm_ctrl &= (~ACMHW_VIQEN);
548 break;
549 case AC3_VO:
550 acm_ctrl &= (~ACMHW_BEQEN);
551 break;
552 default:
553 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
554 "switch case not process\n");
555 break;
556 }
557 }
558
559 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
560 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
561 acm_ctrl);
562 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
563 break; }
564 case HW_VAR_RCR:
565 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
566 rtlpci->receive_config = ((u32 *)(val))[0];
567 break;
568 case HW_VAR_RETRY_LIMIT:{
569 u8 retry_limit = ((u8 *)(val))[0];
570
571 rtl_write_word(rtlpriv, REG_RL,
572 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
573 retry_limit << RETRY_LIMIT_LONG_SHIFT);
574 break; }
575 case HW_VAR_DUAL_TSF_RST:
576 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
577 break;
578 case HW_VAR_EFUSE_BYTES:
579 rtlefuse->efuse_usedbytes = *((u16 *)val);
580 break;
581 case HW_VAR_EFUSE_USAGE:
582 rtlefuse->efuse_usedpercentage = *((u8 *)val);
583 break;
584 case HW_VAR_IO_CMD:
585 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
586 break;
587 case HW_VAR_SET_RPWM:{
588 u8 rpwm_val;
589
590 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
591 udelay(1);
592
593 if (rpwm_val & BIT(7)) {
594 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
595 (*(u8 *)val));
596 } else {
597 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
598 ((*(u8 *)val) | BIT(7)));
599 }
600 break; }
601 case HW_VAR_H2C_FW_PWRMODE:
602 rtl88e_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
603 break;
604 case HW_VAR_FW_PSMODE_STATUS:
605 ppsc->fw_current_inpsmode = *((bool *)val);
606 break;
607 case HW_VAR_RESUME_CLK_ON:
608 _rtl88ee_set_fw_ps_rf_on(hw);
609 break;
610 case HW_VAR_FW_LPS_ACTION:{
611 bool enter_fwlps = *((bool *)val);
612
613 if (enter_fwlps)
614 _rtl88ee_fwlps_enter(hw);
615 else
616 _rtl88ee_fwlps_leave(hw);
617 break; }
618 case HW_VAR_H2C_FW_JOINBSSRPT:{
619 u8 mstatus = (*(u8 *)val);
620 u8 tmp, tmp_reg422, uval;
621 u8 count = 0, dlbcn_count = 0;
622 bool recover = false;
623
624 if (mstatus == RT_MEDIA_CONNECT) {
625 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
626
627 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
628 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(0)));
629
630 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
631 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
632
633 tmp_reg422 = rtl_read_byte(rtlpriv,
634 REG_FWHW_TXQ_CTRL + 2);
635 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
636 tmp_reg422 & (~BIT(6)));
637 if (tmp_reg422 & BIT(6))
638 recover = true;
639
640 do {
641 uval = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
642 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
643 (uval | BIT(0)));
644 _rtl88ee_return_beacon_queue_skb(hw);
645
646 rtl88e_set_fw_rsvdpagepkt(hw, 0);
647 uval = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
648 count = 0;
649 while (!(uval & BIT(0)) && count < 20) {
650 count++;
651 udelay(10);
652 uval = rtl_read_byte(rtlpriv,
653 REG_TDECTRL+2);
654 }
655 dlbcn_count++;
656 } while (!(uval & BIT(0)) && dlbcn_count < 5);
657
658 if (uval & BIT(0))
659 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
660
661 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
662 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
663
664 if (recover) {
665 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
666 tmp_reg422);
667 }
668 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & ~(BIT(0))));
669 }
670 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
671 break; }
672 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
673 rtl88e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
674 break;
675 case HW_VAR_AID:{
676 u16 u2btmp;
677 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
678 u2btmp &= 0xC000;
679 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
680 mac->assoc_id));
681 break; }
682 case HW_VAR_CORRECT_TSF:{
683 u8 btype_ibss = ((u8 *)(val))[0];
684
685 if (btype_ibss == true)
686 _rtl88ee_stop_tx_beacon(hw);
687
688 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
689
690 rtl_write_dword(rtlpriv, REG_TSFTR,
691 (u32) (mac->tsf & 0xffffffff));
692 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
693 (u32) ((mac->tsf >> 32) & 0xffffffff));
694
695 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
696
697 if (btype_ibss == true)
698 _rtl88ee_resume_tx_beacon(hw);
699 break; }
700 default:
701 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
702 "switch case not process %x\n", variable);
703 break;
704 }
705}
706
707static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
708{
709 struct rtl_priv *rtlpriv = rtl_priv(hw);
710 bool status = true;
711 long count = 0;
712 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
713 _LLT_OP(_LLT_WRITE_ACCESS);
714
715 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
716
717 do {
718 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
719 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
720 break;
721
722 if (count > POLLING_LLT_THRESHOLD) {
723 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
724 "Failed to polling write LLT done at address %d!\n",
725 address);
726 status = false;
727 break;
728 }
729 } while (++count);
730
731 return status;
732}
733
734static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
735{
736 struct rtl_priv *rtlpriv = rtl_priv(hw);
737 unsigned short i;
738 u8 txpktbuf_bndy;
739 u8 maxpage;
740 bool status;
741
742 maxpage = 0xAF;
743 txpktbuf_bndy = 0xAB;
744
745 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
746 rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
747
748
749 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
750 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
751
752 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
753 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
754
755 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
756 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
757 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
758
759 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
760 status = _rtl88ee_llt_write(hw, i, i + 1);
761 if (true != status)
762 return status;
763 }
764
765 status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
766 if (true != status)
767 return status;
768
769 for (i = txpktbuf_bndy; i < maxpage; i++) {
770 status = _rtl88ee_llt_write(hw, i, (i + 1));
771 if (true != status)
772 return status;
773 }
774
775 status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
776 if (true != status)
777 return status;
778
779 return true;
780}
781
782static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
783{
784 struct rtl_priv *rtlpriv = rtl_priv(hw);
785 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
786 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
787 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
788
789 if (rtlpriv->rtlhal.up_first_time)
790 return;
791
792 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
793 rtl88ee_sw_led_on(hw, pLed0);
794 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
795 rtl88ee_sw_led_on(hw, pLed0);
796 else
797 rtl88ee_sw_led_off(hw, pLed0);
798}
799
800static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
801{
802 struct rtl_priv *rtlpriv = rtl_priv(hw);
803 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
804 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
805 u8 bytetmp;
806 u16 wordtmp;
807
808 /*Disable XTAL OUTPUT for power saving. YJ, add, 111206. */
809 bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
810 rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
811 /*Auto Power Down to CHIP-off State*/
812 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
813 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
814
815 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
816 /* HW Power on sequence */
817 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
818 PWR_INTF_PCI_MSK,
819 Rtl8188E_NIC_ENABLE_FLOW)) {
820 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
821 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
822 return false;
823 }
824
825 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
826 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
827
828 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
829 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
830
831 bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
832 rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
833
834 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
835 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
836
837 bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
838 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
839 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
840 rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
841
842 /*Add for wake up online*/
843 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
844
845 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
846 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
847 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
848 rtl_write_byte(rtlpriv, 0x367, 0x80);
849
850 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
851 rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
852 rtl_write_byte(rtlpriv, REG_CR+2, 0x00);
853
854 if (!rtlhal->mac_func_enable) {
855 if (_rtl88ee_llt_table_init(hw) == false) {
856 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
857 "LLT table init fail\n");
858 return false;
859 }
860 }
861
862
863 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
864 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
865
866 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
867 wordtmp &= 0xf;
868 wordtmp |= 0xE771;
869 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
870
871 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
872 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
873 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
874
875 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
876 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
877 DMA_BIT_MASK(32));
878 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
879 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
880 DMA_BIT_MASK(32));
881 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
882 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
883 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
884 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
885 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
886 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
887 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
888 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
889 rtl_write_dword(rtlpriv, REG_HQ_DESA,
890 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
891 DMA_BIT_MASK(32));
892 rtl_write_dword(rtlpriv, REG_RX_DESA,
893 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
894 DMA_BIT_MASK(32));
895
896 /* if we want to support 64 bit DMA, we should set it here,
897 * but at the moment we do not support 64 bit DMA
898 */
899
900 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
901
902 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
903 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
904
905 if (rtlhal->earlymode_enable) {/*Early mode enable*/
906 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
907 bytetmp |= 0x1f;
908 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
909 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
910 }
911 _rtl88ee_gen_refresh_led_state(hw);
912 return true;
913}
914
915static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
916{
917 struct rtl_priv *rtlpriv = rtl_priv(hw);
918 u32 reg_prsr;
919
920 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
921
922 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
923 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
924}
925
926static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
927{
928 struct rtl_priv *rtlpriv = rtl_priv(hw);
929 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
930 u8 tmp1byte = 0;
931 u32 tmp4Byte = 0, count;
932
933 rtl_write_word(rtlpriv, 0x354, 0x8104);
934 rtl_write_word(rtlpriv, 0x358, 0x24);
935
936 rtl_write_word(rtlpriv, 0x350, 0x70c);
937 rtl_write_byte(rtlpriv, 0x352, 0x2);
938 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
939 count = 0;
940 while (tmp1byte && count < 20) {
941 udelay(10);
942 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
943 count++;
944 }
945 if (0 == tmp1byte) {
946 tmp4Byte = rtl_read_dword(rtlpriv, 0x34c);
947 rtl_write_dword(rtlpriv, 0x348, tmp4Byte|BIT(31));
948 rtl_write_word(rtlpriv, 0x350, 0xf70c);
949 rtl_write_byte(rtlpriv, 0x352, 0x1);
950 }
951
952 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
953 count = 0;
954 while (tmp1byte && count < 20) {
955 udelay(10);
956 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
957 count++;
958 }
959
960 rtl_write_word(rtlpriv, 0x350, 0x718);
961 rtl_write_byte(rtlpriv, 0x352, 0x2);
962 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
963 count = 0;
964 while (tmp1byte && count < 20) {
965 udelay(10);
966 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
967 count++;
968 }
969 if (ppsc->support_backdoor || (0 == tmp1byte)) {
970 tmp4Byte = rtl_read_dword(rtlpriv, 0x34c);
971 rtl_write_dword(rtlpriv, 0x348, tmp4Byte|BIT(11)|BIT(12));
972 rtl_write_word(rtlpriv, 0x350, 0xf718);
973 rtl_write_byte(rtlpriv, 0x352, 0x1);
974 }
975 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
976 count = 0;
977 while (tmp1byte && count < 20) {
978 udelay(10);
979 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
980 count++;
981 }
982}
983
984void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
985{
986 struct rtl_priv *rtlpriv = rtl_priv(hw);
987 u8 sec_reg_value;
988
989 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
990 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
991 rtlpriv->sec.pairwise_enc_algorithm,
992 rtlpriv->sec.group_enc_algorithm);
993
994 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
995 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
996 "not open hw encryption\n");
997 return;
998 }
999 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1000
1001 if (rtlpriv->sec.use_defaultkey) {
1002 sec_reg_value |= SCR_TXUSEDK;
1003 sec_reg_value |= SCR_RXUSEDK;
1004 }
1005
1006 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1007
1008 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1009
1010 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1011 "The SECR-value %x\n", sec_reg_value);
1012 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1013}
1014
1015int rtl88ee_hw_init(struct ieee80211_hw *hw)
1016{
1017 struct rtl_priv *rtlpriv = rtl_priv(hw);
1018 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1019 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1020 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1021 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1022 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1023 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1024 bool rtstatus = true;
1025 int err = 0;
1026 u8 tmp_u1b, u1byte;
1027
1028 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Rtl8188EE hw init\n");
1029 rtlpriv->rtlhal.being_init_adapter = true;
1030 rtlpriv->intf_ops->disable_aspm(hw);
1031
1032 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1033 u1byte = rtl_read_byte(rtlpriv, REG_CR);
1034 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1035 rtlhal->mac_func_enable = true;
1036 } else {
1037 rtlhal->mac_func_enable = false;
1038 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1039 }
1040
1041 rtstatus = _rtl88ee_init_mac(hw);
1042 if (rtstatus != true) {
1043 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1044 err = 1;
1045 return err;
1046 }
1047
1048 err = rtl88e_download_fw(hw, false);
1049 if (err) {
1050 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1051 "Failed to download FW. Init HW without FW now..\n");
1052 err = 1;
1053 rtlhal->fw_ready = false;
1054 return err;
1055 } else {
1056 rtlhal->fw_ready = true;
1057 }
1058 /*fw related variable initialize */
1059 rtlhal->last_hmeboxnum = 0;
1060 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1061 rtlhal->fw_clk_change_in_progress = false;
1062 rtlhal->allow_sw_to_change_hwclc = false;
1063 ppsc->fw_current_inpsmode = false;
1064
1065 rtl88e_phy_mac_config(hw);
1066 /* because last function modifies RCR, we update
1067 * rcr var here, or TP will be unstable for receive_config
1068 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1069 * RCR_APP_ICV will cause mac80211 disassoc for cisco 1252
1070 */
1071 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1072 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1073
1074 rtl88e_phy_bb_config(hw);
1075 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1076 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1077
1078 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1079 rtl88e_phy_rf_config(hw);
1080
1081 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1082 RF_CHNLBW, RFREG_OFFSET_MASK);
1083 rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1084
1085 _rtl88ee_hw_configure(hw);
1086 rtl_cam_reset_all_entry(hw);
1087 rtl88ee_enable_hw_security_config(hw);
1088
1089 rtlhal->mac_func_enable = true;
1090 ppsc->rfpwr_state = ERFON;
1091
1092 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1093 _rtl88ee_enable_aspm_back_door(hw);
1094 rtlpriv->intf_ops->enable_aspm(hw);
1095
1096 if (ppsc->rfpwr_state == ERFON) {
1097 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1098 ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1099 (rtlhal->oem_id == RT_CID_819x_HP))) {
1100 rtl88e_phy_set_rfpath_switch(hw, true);
1101 rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1102 } else {
1103 rtl88e_phy_set_rfpath_switch(hw, false);
1104 rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1105 }
1106 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1107 "rx idle ant %s\n",
1108 (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1109 ("MAIN_ANT") : ("AUX_ANT"));
1110
1111 if (rtlphy->iqk_initialized) {
1112 rtl88e_phy_iq_calibrate(hw, true);
1113 } else {
1114 rtl88e_phy_iq_calibrate(hw, false);
1115 rtlphy->iqk_initialized = true;
1116 }
1117 rtl88e_dm_check_txpower_tracking(hw);
1118 rtl88e_phy_lc_calibrate(hw);
1119 }
1120
1121 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1122 if (!(tmp_u1b & BIT(0))) {
1123 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1124 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1125 }
1126
1127 if (!(tmp_u1b & BIT(4))) {
1128 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1129 tmp_u1b &= 0x0F;
1130 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1131 udelay(10);
1132 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1133 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1134 }
1135 rtl_write_byte(rtlpriv, REG_NAV_CTRL+2, ((30000+127)/128));
1136 rtl88e_dm_init(hw);
1137 rtlpriv->rtlhal.being_init_adapter = false;
1138 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "end of Rtl8188EE hw init %x\n",
1139 err);
1140 return 0;
1141}
1142
1143static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1144{
1145 struct rtl_priv *rtlpriv = rtl_priv(hw);
1146 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1147 enum version_8188e version = VERSION_UNKNOWN;
1148 u32 value32;
1149
1150 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1151 if (value32 & TRP_VAUX_EN) {
1152 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1153 } else {
1154 version = NORMAL_CHIP;
1155 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1156 version = version | ((value32 & VENDOR_ID) ?
1157 CHIP_VENDOR_UMC : 0);
1158 }
1159
1160 rtlphy->rf_type = RF_1T1R;
1161 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1162 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1163 "RF_2T2R" : "RF_1T1R");
1164
1165 return version;
1166}
1167
1168static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1169 enum nl80211_iftype type)
1170{
1171 struct rtl_priv *rtlpriv = rtl_priv(hw);
1172 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1173 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1174 bt_msr &= 0xfc;
1175
1176 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1177 type == NL80211_IFTYPE_STATION) {
1178 _rtl88ee_stop_tx_beacon(hw);
1179 _rtl88ee_enable_bcn_sub_func(hw);
1180 } else if (type == NL80211_IFTYPE_ADHOC ||
1181 type == NL80211_IFTYPE_AP ||
1182 type == NL80211_IFTYPE_MESH_POINT) {
1183 _rtl88ee_resume_tx_beacon(hw);
1184 _rtl88ee_disable_bcn_sub_func(hw);
1185 } else {
1186 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1187 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1188 type);
1189 }
1190
1191 switch (type) {
1192 case NL80211_IFTYPE_UNSPECIFIED:
1193 bt_msr |= MSR_NOLINK;
1194 ledaction = LED_CTL_LINK;
1195 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1196 "Set Network type to NO LINK!\n");
1197 break;
1198 case NL80211_IFTYPE_ADHOC:
1199 bt_msr |= MSR_ADHOC;
1200 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1201 "Set Network type to Ad Hoc!\n");
1202 break;
1203 case NL80211_IFTYPE_STATION:
1204 bt_msr |= MSR_INFRA;
1205 ledaction = LED_CTL_LINK;
1206 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1207 "Set Network type to STA!\n");
1208 break;
1209 case NL80211_IFTYPE_AP:
1210 bt_msr |= MSR_AP;
1211 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1212 "Set Network type to AP!\n");
1213 break;
1214 case NL80211_IFTYPE_MESH_POINT:
1215 bt_msr |= MSR_ADHOC;
1216 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1217 "Set Network type to Mesh Point!\n");
1218 break;
1219 default:
1220 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1221 "Network type %d not support!\n", type);
1222 return 1;
1223 }
1224
1225 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1226 rtlpriv->cfg->ops->led_control(hw, ledaction);
1227 if ((bt_msr & 0xfc) == MSR_AP)
1228 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1229 else
1230 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1231 return 0;
1232}
1233
1234void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1235{
1236 struct rtl_priv *rtlpriv = rtl_priv(hw);
1237 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1238 u32 reg_rcr = rtlpci->receive_config;
1239
1240 if (rtlpriv->psc.rfpwr_state != ERFON)
1241 return;
1242
1243 if (check_bssid == true) {
1244 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1245 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1246 (u8 *)(&reg_rcr));
1247 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1248 } else if (check_bssid == false) {
1249 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1250 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1251 rtlpriv->cfg->ops->set_hw_reg(hw,
1252 HW_VAR_RCR, (u8 *)(&reg_rcr));
1253 }
1254}
1255
1256int rtl88ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1257{
1258 struct rtl_priv *rtlpriv = rtl_priv(hw);
1259
1260 if (_rtl88ee_set_media_status(hw, type))
1261 return -EOPNOTSUPP;
1262
1263 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1264 if (type != NL80211_IFTYPE_AP &&
1265 type != NL80211_IFTYPE_MESH_POINT)
1266 rtl88ee_set_check_bssid(hw, true);
1267 } else {
1268 rtl88ee_set_check_bssid(hw, false);
1269 }
1270
1271 return 0;
1272}
1273
1274/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1275void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1276{
1277 struct rtl_priv *rtlpriv = rtl_priv(hw);
1278 rtl88e_dm_init_edca_turbo(hw);
1279 switch (aci) {
1280 case AC1_BK:
1281 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1282 break;
1283 case AC0_BE:
1284 break;
1285 case AC2_VI:
1286 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1287 break;
1288 case AC3_VO:
1289 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1290 break;
1291 default:
1292 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1293 break;
1294 }
1295}
1296
1297void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1298{
1299 struct rtl_priv *rtlpriv = rtl_priv(hw);
1300 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1301
1302 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1303 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1304 rtlpci->irq_enabled = true;
1305 /* there are some C2H CMDs have been sent before system interrupt
1306 * is enabled, e.g., C2H, CPWM.
1307 * So we need to clear all C2H events that FW has notified, otherwise
1308 * FW won't schedule any commands anymore.
1309 */
1310 rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1311 /*enable system interrupt*/
1312 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1313}
1314
1315void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1316{
1317 struct rtl_priv *rtlpriv = rtl_priv(hw);
1318 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1319
1320 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1321 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1322 rtlpci->irq_enabled = false;
1323 synchronize_irq(rtlpci->pdev->irq);
1324}
1325
1326static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1327{
1328 struct rtl_priv *rtlpriv = rtl_priv(hw);
1329 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1330 u8 u1b_tmp;
1331 u32 count = 0;
1332 rtlhal->mac_func_enable = false;
1333 rtlpriv->intf_ops->enable_aspm(hw);
1334
1335 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1336 u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1337 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1338
1339 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1340 while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1341 udelay(10);
1342 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1343 count++;
1344 }
1345 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1346
1347 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1348 PWR_INTF_PCI_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
1349
1350 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1351
1352 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1353 rtl88e_firmware_selfreset(hw);
1354
1355 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1356 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1357 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1358
1359 u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1360 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1361
1362 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1363 PWR_INTF_PCI_MSK, Rtl8188E_NIC_DISABLE_FLOW);
1364
1365 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1366 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1367 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1368 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1369
1370 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1371
1372 u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1373 rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1374 rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1375
1376 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1377 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1378 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1379 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1380
1381 rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1382}
1383
1384void rtl88ee_card_disable(struct ieee80211_hw *hw)
1385{
1386 struct rtl_priv *rtlpriv = rtl_priv(hw);
1387 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1388 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1389 enum nl80211_iftype opmode;
1390
1391 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1392
1393 mac->link_state = MAC80211_NOLINK;
1394 opmode = NL80211_IFTYPE_UNSPECIFIED;
1395
1396 _rtl88ee_set_media_status(hw, opmode);
1397
1398 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1399 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1400 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1401
1402 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1403 _rtl88ee_poweroff_adapter(hw);
1404
1405 /* after power off we should do iqk again */
1406 rtlpriv->phy.iqk_initialized = false;
1407}
1408
1409void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1410 u32 *p_inta, u32 *p_intb)
1411{
1412 struct rtl_priv *rtlpriv = rtl_priv(hw);
1413 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1414
1415 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1416 rtl_write_dword(rtlpriv, ISR, *p_inta);
1417
1418 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1419 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1420}
1421
1422void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1423{
1424 struct rtl_priv *rtlpriv = rtl_priv(hw);
1425 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1426 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1427 u16 bcn_interval, atim_window;
1428
1429 bcn_interval = mac->beacon_interval;
1430 atim_window = 2; /*FIX MERGE */
1431 rtl88ee_disable_interrupt(hw);
1432 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1433 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1434 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1435 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1436 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1437 rtl_write_byte(rtlpriv, 0x606, 0x30);
1438 rtlpci->reg_bcn_ctrl_val |= BIT(3);
1439 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1440 /*rtl88ee_enable_interrupt(hw);*/
1441}
1442
1443void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1444{
1445 struct rtl_priv *rtlpriv = rtl_priv(hw);
1446 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1447 u16 bcn_interval = mac->beacon_interval;
1448
1449 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1450 "beacon_interval:%d\n", bcn_interval);
1451 /*rtl88ee_disable_interrupt(hw);*/
1452 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1453 /*rtl88ee_enable_interrupt(hw);*/
1454}
1455
1456void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1457 u32 add_msr, u32 rm_msr)
1458{
1459 struct rtl_priv *rtlpriv = rtl_priv(hw);
1460 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1461
1462 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1463 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1464
1465 rtl88ee_disable_interrupt(hw);
1466 if (add_msr)
1467 rtlpci->irq_mask[0] |= add_msr;
1468 if (rm_msr)
1469 rtlpci->irq_mask[0] &= (~rm_msr);
1470 rtl88ee_enable_interrupt(hw);
1471}
1472
1473static inline u8 get_chnl_group(u8 chnl)
1474{
1475 u8 group;
1476
1477 group = chnl / 3;
1478 if (chnl == 14)
1479 group = 5;
1480
1481 return group;
1482}
1483
1484static void set_diff0_2g(struct txpower_info_2g *pwr2g, u8 *hwinfo, u32 path,
1485 u32 i, u32 eadr)
1486{
1487 pwr2g->bw40_diff[path][i] = 0;
1488 if (hwinfo[eadr] == 0xFF) {
1489 pwr2g->bw20_diff[path][i] = 0x02;
1490 } else {
1491 pwr2g->bw20_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1492 /*bit sign number to 8 bit sign number*/
1493 if (pwr2g->bw20_diff[path][i] & BIT(3))
1494 pwr2g->bw20_diff[path][i] |= 0xF0;
1495 }
1496
1497 if (hwinfo[eadr] == 0xFF) {
1498 pwr2g->ofdm_diff[path][i] = 0x04;
1499 } else {
1500 pwr2g->ofdm_diff[path][i] = (hwinfo[eadr] & 0x0f);
1501 /*bit sign number to 8 bit sign number*/
1502 if (pwr2g->ofdm_diff[path][i] & BIT(3))
1503 pwr2g->ofdm_diff[path][i] |= 0xF0;
1504 }
1505 pwr2g->cck_diff[path][i] = 0;
1506}
1507
1508static void set_diff0_5g(struct txpower_info_5g *pwr5g, u8 *hwinfo, u32 path,
1509 u32 i, u32 eadr)
1510{
1511 pwr5g->bw40_diff[path][i] = 0;
1512 if (hwinfo[eadr] == 0xFF) {
1513 pwr5g->bw20_diff[path][i] = 0;
1514 } else {
1515 pwr5g->bw20_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1516 /*bit sign number to 8 bit sign number*/
1517 if (pwr5g->bw20_diff[path][i] & BIT(3))
1518 pwr5g->bw20_diff[path][i] |= 0xF0;
1519 }
1520
1521 if (hwinfo[eadr] == 0xFF) {
1522 pwr5g->ofdm_diff[path][i] = 0x04;
1523 } else {
1524 pwr5g->ofdm_diff[path][i] = (hwinfo[eadr] & 0x0f);
1525 /*bit sign number to 8 bit sign number*/
1526 if (pwr5g->ofdm_diff[path][i] & BIT(3))
1527 pwr5g->ofdm_diff[path][i] |= 0xF0;
1528 }
1529}
1530
1531static void set_diff1_2g(struct txpower_info_2g *pwr2g, u8 *hwinfo, u32 path,
1532 u32 i, u32 eadr)
1533{
1534 if (hwinfo[eadr] == 0xFF) {
1535 pwr2g->bw40_diff[path][i] = 0xFE;
1536 } else {
1537 pwr2g->bw40_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1538 if (pwr2g->bw40_diff[path][i] & BIT(3))
1539 pwr2g->bw40_diff[path][i] |= 0xF0;
1540 }
1541
1542 if (hwinfo[eadr] == 0xFF) {
1543 pwr2g->bw20_diff[path][i] = 0xFE;
1544 } else {
1545 pwr2g->bw20_diff[path][i] = (hwinfo[eadr]&0x0f);
1546 if (pwr2g->bw20_diff[path][i] & BIT(3))
1547 pwr2g->bw20_diff[path][i] |= 0xF0;
1548 }
1549}
1550
1551static void set_diff1_5g(struct txpower_info_5g *pwr5g, u8 *hwinfo, u32 path,
1552 u32 i, u32 eadr)
1553{
1554 if (hwinfo[eadr] == 0xFF) {
1555 pwr5g->bw40_diff[path][i] = 0xFE;
1556 } else {
1557 pwr5g->bw40_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1558 if (pwr5g->bw40_diff[path][i] & BIT(3))
1559 pwr5g->bw40_diff[path][i] |= 0xF0;
1560 }
1561
1562 if (hwinfo[eadr] == 0xFF) {
1563 pwr5g->bw20_diff[path][i] = 0xFE;
1564 } else {
1565 pwr5g->bw20_diff[path][i] = (hwinfo[eadr] & 0x0f);
1566 if (pwr5g->bw20_diff[path][i] & BIT(3))
1567 pwr5g->bw20_diff[path][i] |= 0xF0;
1568 }
1569}
1570
1571static void set_diff2_2g(struct txpower_info_2g *pwr2g, u8 *hwinfo, u32 path,
1572 u32 i, u32 eadr)
1573{
1574 if (hwinfo[eadr] == 0xFF) {
1575 pwr2g->ofdm_diff[path][i] = 0xFE;
1576 } else {
1577 pwr2g->ofdm_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1578 if (pwr2g->ofdm_diff[path][i] & BIT(3))
1579 pwr2g->ofdm_diff[path][i] |= 0xF0;
1580 }
1581
1582 if (hwinfo[eadr] == 0xFF) {
1583 pwr2g->cck_diff[path][i] = 0xFE;
1584 } else {
1585 pwr2g->cck_diff[path][i] = (hwinfo[eadr]&0x0f);
1586 if (pwr2g->cck_diff[path][i] & BIT(3))
1587 pwr2g->cck_diff[path][i] |= 0xF0;
1588 }
1589}
1590
1591static void _rtl8188e_read_power_value_fromprom(struct ieee80211_hw *hw,
1592 struct txpower_info_2g *pwr2g,
1593 struct txpower_info_5g *pwr5g,
1594 bool autoload_fail,
1595 u8 *hwinfo)
1596{
1597 struct rtl_priv *rtlpriv = rtl_priv(hw);
1598 u32 path, eadr = EEPROM_TX_PWR_INX, i;
1599
1600 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1601 "hal_ReadPowerValueFromPROM88E(): PROMContent[0x%x]= 0x%x\n",
1602 (eadr+1), hwinfo[eadr+1]);
1603 if (0xFF == hwinfo[eadr+1])
1604 autoload_fail = true;
1605
1606 if (autoload_fail) {
1607 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1608 "auto load fail : Use Default value!\n");
1609 for (path = 0; path < MAX_RF_PATH; path++) {
1610 /* 2.4G default value */
1611 for (i = 0; i < MAX_CHNL_GROUP_24G; i++) {
1612 pwr2g->index_cck_base[path][i] = 0x2D;
1613 pwr2g->index_bw40_base[path][i] = 0x2D;
1614 }
1615 for (i = 0; i < MAX_TX_COUNT; i++) {
1616 if (i == 0) {
1617 pwr2g->bw20_diff[path][0] = 0x02;
1618 pwr2g->ofdm_diff[path][0] = 0x04;
1619 } else {
1620 pwr2g->bw20_diff[path][i] = 0xFE;
1621 pwr2g->bw40_diff[path][i] = 0xFE;
1622 pwr2g->cck_diff[path][i] = 0xFE;
1623 pwr2g->ofdm_diff[path][i] = 0xFE;
1624 }
1625 }
1626 }
1627 return;
1628 }
1629
1630 for (path = 0; path < MAX_RF_PATH; path++) {
1631 /*2.4G default value*/
1632 for (i = 0; i < MAX_CHNL_GROUP_24G; i++) {
1633 pwr2g->index_cck_base[path][i] = hwinfo[eadr++];
1634 if (pwr2g->index_cck_base[path][i] == 0xFF)
1635 pwr2g->index_cck_base[path][i] = 0x2D;
1636 }
1637 for (i = 0; i < MAX_CHNL_GROUP_24G-1; i++) {
1638 pwr2g->index_bw40_base[path][i] = hwinfo[eadr++];
1639 if (pwr2g->index_bw40_base[path][i] == 0xFF)
1640 pwr2g->index_bw40_base[path][i] = 0x2D;
1641 }
1642 for (i = 0; i < MAX_TX_COUNT; i++) {
1643 if (i == 0) {
1644 set_diff0_2g(pwr2g, hwinfo, path, i, eadr);
1645 eadr++;
1646 } else {
1647 set_diff1_2g(pwr2g, hwinfo, path, i, eadr);
1648 eadr++;
1649
1650 set_diff2_2g(pwr2g, hwinfo, path, i, eadr);
1651 eadr++;
1652 }
1653 }
1654
1655 /*5G default value*/
1656 for (i = 0; i < MAX_CHNL_GROUP_5G; i++) {
1657 pwr5g->index_bw40_base[path][i] = hwinfo[eadr++];
1658 if (pwr5g->index_bw40_base[path][i] == 0xFF)
1659 pwr5g->index_bw40_base[path][i] = 0xFE;
1660 }
1661
1662 for (i = 0; i < MAX_TX_COUNT; i++) {
1663 if (i == 0) {
1664 set_diff0_5g(pwr5g, hwinfo, path, i, eadr);
1665 eadr++;
1666 } else {
1667 set_diff1_5g(pwr5g, hwinfo, path, i, eadr);
1668 eadr++;
1669 }
1670 }
1671
1672 if (hwinfo[eadr] == 0xFF) {
1673 pwr5g->ofdm_diff[path][1] = 0xFE;
1674 pwr5g->ofdm_diff[path][2] = 0xFE;
1675 } else {
1676 pwr5g->ofdm_diff[path][1] = (hwinfo[eadr] & 0xf0) >> 4;
1677 pwr5g->ofdm_diff[path][2] = (hwinfo[eadr] & 0x0f);
1678 }
1679 eadr++;
1680
1681 if (hwinfo[eadr] == 0xFF)
1682 pwr5g->ofdm_diff[path][3] = 0xFE;
1683 else
1684 pwr5g->ofdm_diff[path][3] = (hwinfo[eadr]&0x0f);
1685 eadr++;
1686
1687 for (i = 1; i < MAX_TX_COUNT; i++) {
1688 if (pwr5g->ofdm_diff[path][i] == 0xFF)
1689 pwr5g->ofdm_diff[path][i] = 0xFE;
1690 else if (pwr5g->ofdm_diff[path][i] & BIT(3))
1691 pwr5g->ofdm_diff[path][i] |= 0xF0;
1692 }
1693 }
1694}
1695
1696static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1697 bool autoload_fail,
1698 u8 *hwinfo)
1699{
1700 struct rtl_priv *rtlpriv = rtl_priv(hw);
1701 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1702 struct txpower_info_2g pwrinfo24g;
1703 struct txpower_info_5g pwrinfo5g;
1704 u8 rf_path, index;
1705 u8 i;
1706 int jj = EEPROM_RF_BOARD_OPTION_88E;
1707 int kk = EEPROM_THERMAL_METER_88E;
1708
1709 _rtl8188e_read_power_value_fromprom(hw, &pwrinfo24g, &pwrinfo5g,
1710 autoload_fail, hwinfo);
1711
1712 for (rf_path = 0; rf_path < 2; rf_path++) {
1713 for (i = 0; i < 14; i++) {
1714 index = get_chnl_group(i+1);
1715
1716 rtlefuse->txpwrlevel_cck[rf_path][i] =
1717 pwrinfo24g.index_cck_base[rf_path][index];
1718 if (i == 13)
1719 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1720 pwrinfo24g.index_bw40_base[rf_path][4];
1721 else
1722 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1723 pwrinfo24g.index_bw40_base[rf_path][index];
1724 rtlefuse->txpwr_ht20diff[rf_path][i] =
1725 pwrinfo24g.bw20_diff[rf_path][0];
1726 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1727 pwrinfo24g.ofdm_diff[rf_path][0];
1728 }
1729
1730 for (i = 0; i < 14; i++) {
1731 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1732 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = "
1733 "[0x%x / 0x%x ]\n", rf_path, i,
1734 rtlefuse->txpwrlevel_cck[rf_path][i],
1735 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1736 }
1737 }
1738
1739 if (!autoload_fail)
1740 rtlefuse->eeprom_thermalmeter = hwinfo[kk];
1741 else
1742 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1743
1744 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1745 rtlefuse->apk_thermalmeterignore = true;
1746 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1747 }
1748
1749 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1750 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1751 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1752
1753 if (!autoload_fail) {
1754 rtlefuse->eeprom_regulatory = hwinfo[jj] & 0x07;/*bit0~2*/
1755 if (hwinfo[jj] == 0xFF)
1756 rtlefuse->eeprom_regulatory = 0;
1757 } else {
1758 rtlefuse->eeprom_regulatory = 0;
1759 }
1760 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1761 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1762}
1763
1764static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1765{
1766 struct rtl_priv *rtlpriv = rtl_priv(hw);
1767 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1768 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1769 struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
1770 u16 i, usvalue;
1771 u8 hwinfo[HWSET_MAX_SIZE];
1772 u16 eeprom_id;
1773 int jj = EEPROM_RF_BOARD_OPTION_88E;
1774 int kk = EEPROM_RF_FEATURE_OPTION_88E;
1775
1776 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1777 rtl_efuse_shadow_map_update(hw);
1778
1779 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1780 HWSET_MAX_SIZE);
1781 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1782 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1783 "RTL819X Not boot from eeprom, check it !!");
1784 }
1785
1786 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1787 hwinfo, HWSET_MAX_SIZE);
1788
1789 eeprom_id = *((u16 *)&hwinfo[0]);
1790 if (eeprom_id != RTL8188E_EEPROM_ID) {
1791 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1792 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1793 rtlefuse->autoload_failflag = true;
1794 } else {
1795 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1796 rtlefuse->autoload_failflag = false;
1797 }
1798
1799 if (rtlefuse->autoload_failflag == true)
1800 return;
1801 /*VID DID SVID SDID*/
1802 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1803 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1804 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1805 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1806 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1807 "EEPROMId = 0x%4x\n", eeprom_id);
1808 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1809 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1810 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1811 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1812 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1813 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1814 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1815 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1816 /*customer ID*/
1817 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1818 if (rtlefuse->eeprom_oemid == 0xFF)
1819 rtlefuse->eeprom_oemid = 0;
1820
1821 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1822 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1823 /*EEPROM version*/
1824 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1825 /*mac address*/
1826 for (i = 0; i < 6; i += 2) {
1827 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1828 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
1829 }
1830
1831 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1832 "dev_addr: %pM\n", rtlefuse->dev_addr);
1833 /*channel plan */
1834 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1835 /* set channel paln to world wide 13 */
1836 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1837 /*tx power*/
1838 _rtl88ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1839 hwinfo);
1840 rtlefuse->txpwr_fromeprom = true;
1841
1842 rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1843 rtlefuse->autoload_failflag,
1844 hwinfo);
1845 /*board type*/
1846 rtlefuse->board_type = (((*(u8 *)&hwinfo[jj]) & 0xE0) >> 5);
1847 /*Wake on wlan*/
1848 rtlefuse->wowlan_enable = ((hwinfo[kk] & 0x40) >> 6);
1849 /*parse xtal*/
1850 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1851 if (hwinfo[EEPROM_XTAL_88E])
1852 rtlefuse->crystalcap = 0x20;
1853 /*antenna diversity*/
1854 rtlefuse->antenna_div_cfg = (hwinfo[jj] & 0x18) >> 3;
1855 if (hwinfo[jj] == 0xFF)
1856 rtlefuse->antenna_div_cfg = 0;
1857 if (rppriv->bt_coexist.eeprom_bt_coexist != 0 &&
1858 rppriv->bt_coexist.eeprom_bt_ant_num == ANT_X1)
1859 rtlefuse->antenna_div_cfg = 0;
1860
1861 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1862 if (rtlefuse->antenna_div_type == 0xFF)
1863 rtlefuse->antenna_div_type = 0x01;
1864 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1865 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1866 rtlefuse->antenna_div_cfg = 1;
1867
1868 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1869 switch (rtlefuse->eeprom_oemid) {
1870 case EEPROM_CID_DEFAULT:
1871 if (rtlefuse->eeprom_did == 0x8179) {
1872 if (rtlefuse->eeprom_svid == 0x1025) {
1873 rtlhal->oem_id = RT_CID_819x_Acer;
1874 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1875 rtlefuse->eeprom_smid == 0x0179) ||
1876 (rtlefuse->eeprom_svid == 0x17AA &&
1877 rtlefuse->eeprom_smid == 0x0179)) {
1878 rtlhal->oem_id = RT_CID_819x_Lenovo;
1879 } else if (rtlefuse->eeprom_svid == 0x103c &&
1880 rtlefuse->eeprom_smid == 0x197d) {
1881 rtlhal->oem_id = RT_CID_819x_HP;
1882 } else {
1883 rtlhal->oem_id = RT_CID_DEFAULT;
1884 }
1885 } else {
1886 rtlhal->oem_id = RT_CID_DEFAULT;
1887 }
1888 break;
1889 case EEPROM_CID_TOSHIBA:
1890 rtlhal->oem_id = RT_CID_TOSHIBA;
1891 break;
1892 case EEPROM_CID_QMI:
1893 rtlhal->oem_id = RT_CID_819x_QMI;
1894 break;
1895 case EEPROM_CID_WHQL:
1896 default:
1897 rtlhal->oem_id = RT_CID_DEFAULT;
1898 break;
1899 }
1900 }
1901}
1902
1903static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1904{
1905 struct rtl_priv *rtlpriv = rtl_priv(hw);
1906 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1907 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1908
1909 pcipriv->ledctl.led_opendrain = true;
1910
1911 switch (rtlhal->oem_id) {
1912 case RT_CID_819x_HP:
1913 pcipriv->ledctl.led_opendrain = true;
1914 break;
1915 case RT_CID_819x_Lenovo:
1916 case RT_CID_DEFAULT:
1917 case RT_CID_TOSHIBA:
1918 case RT_CID_CCX:
1919 case RT_CID_819x_Acer:
1920 case RT_CID_WHQL:
1921 default:
1922 break;
1923 }
1924 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1925 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1926}
1927
1928void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
1929{
1930 struct rtl_priv *rtlpriv = rtl_priv(hw);
1931 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1932 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1933 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1934 u8 tmp_u1b;
1935
1936 rtlhal->version = _rtl88ee_read_chip_version(hw);
1937 if (get_rf_type(rtlphy) == RF_1T1R) {
1938 rtlpriv->dm.rfpath_rxenable[0] = true;
1939 } else {
1940 rtlpriv->dm.rfpath_rxenable[0] = true;
1941 rtlpriv->dm.rfpath_rxenable[1] = true;
1942 }
1943 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1944 rtlhal->version);
1945 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1946 if (tmp_u1b & BIT(4)) {
1947 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1948 rtlefuse->epromtype = EEPROM_93C46;
1949 } else {
1950 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1951 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1952 }
1953 if (tmp_u1b & BIT(5)) {
1954 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1955 rtlefuse->autoload_failflag = false;
1956 _rtl88ee_read_adapter_info(hw);
1957 } else {
1958 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1959 }
1960 _rtl88ee_hal_customized_behavior(hw);
1961}
1962
1963static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
1964 struct ieee80211_sta *sta)
1965{
1966 struct rtl_priv *rtlpriv = rtl_priv(hw);
1967 struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
1968 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1969 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1970 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1971 u32 ratr_value;
1972 u8 ratr_index = 0;
1973 u8 nmode = mac->ht_enable;
1974 u8 mimo_ps = IEEE80211_SMPS_OFF;
1975 u16 shortgi_rate;
1976 u32 tmp_ratr_value;
1977 u8 ctx40 = mac->bw_40;
1978 u16 cap = sta->ht_cap.cap;
1979 u8 short40 = (cap & IEEE80211_HT_CAP_SGI_40) ? 1 : 0;
1980 u8 short20 = (cap & IEEE80211_HT_CAP_SGI_20) ? 1 : 0;
1981 enum wireless_mode wirelessmode = mac->mode;
1982
1983 if (rtlhal->current_bandtype == BAND_ON_5G)
1984 ratr_value = sta->supp_rates[1] << 4;
1985 else
1986 ratr_value = sta->supp_rates[0];
1987 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1988 ratr_value = 0xfff;
1989 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1990 sta->ht_cap.mcs.rx_mask[0] << 12);
1991 switch (wirelessmode) {
1992 case WIRELESS_MODE_B:
1993 if (ratr_value & 0x0000000c)
1994 ratr_value &= 0x0000000d;
1995 else
1996 ratr_value &= 0x0000000f;
1997 break;
1998 case WIRELESS_MODE_G:
1999 ratr_value &= 0x00000FF5;
2000 break;
2001 case WIRELESS_MODE_N_24G:
2002 case WIRELESS_MODE_N_5G:
2003 nmode = 1;
2004 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2005 ratr_value &= 0x0007F005;
2006 } else {
2007 u32 ratr_mask;
2008
2009 if (get_rf_type(rtlphy) == RF_1T2R ||
2010 get_rf_type(rtlphy) == RF_1T1R)
2011 ratr_mask = 0x000ff005;
2012 else
2013 ratr_mask = 0x0f0ff005;
2014
2015 ratr_value &= ratr_mask;
2016 }
2017 break;
2018 default:
2019 if (rtlphy->rf_type == RF_1T2R)
2020 ratr_value &= 0x000ff0ff;
2021 else
2022 ratr_value &= 0x0f0ff0ff;
2023
2024 break;
2025 }
2026
2027 if ((rppriv->bt_coexist.bt_coexistence) &&
2028 (rppriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
2029 (rppriv->bt_coexist.bt_cur_state) &&
2030 (rppriv->bt_coexist.bt_ant_isolation) &&
2031 ((rppriv->bt_coexist.bt_service == BT_SCO) ||
2032 (rppriv->bt_coexist.bt_service == BT_BUSY)))
2033 ratr_value &= 0x0fffcfc0;
2034 else
2035 ratr_value &= 0x0FFFFFFF;
2036
2037 if (nmode && ((ctx40 && short40) ||
2038 (!ctx40 && short20))) {
2039 ratr_value |= 0x10000000;
2040 tmp_ratr_value = (ratr_value >> 12);
2041
2042 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2043 if ((1 << shortgi_rate) & tmp_ratr_value)
2044 break;
2045 }
2046
2047 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2048 (shortgi_rate << 4) | (shortgi_rate);
2049 }
2050
2051 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2052
2053 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2054 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2055}
2056
2057static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2058 struct ieee80211_sta *sta, u8 rssi)
2059{
2060 struct rtl_priv *rtlpriv = rtl_priv(hw);
2061 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2062 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2063 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2064 struct rtl_sta_info *sta_entry = NULL;
2065 u32 ratr_bitmap;
2066 u8 ratr_index;
2067 u16 cap = sta->ht_cap.cap;
2068 u8 ctx40 = (cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2069 u8 short40 = (cap & IEEE80211_HT_CAP_SGI_40) ? 1 : 0;
2070 u8 short20 = (cap & IEEE80211_HT_CAP_SGI_20) ? 1 : 0;
2071 enum wireless_mode wirelessmode = 0;
2072 bool shortgi = false;
2073 u8 rate_mask[5];
2074 u8 macid = 0;
2075 u8 mimo_ps = IEEE80211_SMPS_OFF;
2076
2077 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2078 wirelessmode = sta_entry->wireless_mode;
2079 if (mac->opmode == NL80211_IFTYPE_STATION ||
2080 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2081 ctx40 = mac->bw_40;
2082 else if (mac->opmode == NL80211_IFTYPE_AP ||
2083 mac->opmode == NL80211_IFTYPE_ADHOC)
2084 macid = sta->aid + 1;
2085
2086 if (rtlhal->current_bandtype == BAND_ON_5G)
2087 ratr_bitmap = sta->supp_rates[1] << 4;
2088 else
2089 ratr_bitmap = sta->supp_rates[0];
2090 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2091 ratr_bitmap = 0xfff;
2092 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2093 sta->ht_cap.mcs.rx_mask[0] << 12);
2094 switch (wirelessmode) {
2095 case WIRELESS_MODE_B:
2096 ratr_index = RATR_INX_WIRELESS_B;
2097 if (ratr_bitmap & 0x0000000c)
2098 ratr_bitmap &= 0x0000000d;
2099 else
2100 ratr_bitmap &= 0x0000000f;
2101 break;
2102 case WIRELESS_MODE_G:
2103 ratr_index = RATR_INX_WIRELESS_GB;
2104
2105 if (rssi == 1)
2106 ratr_bitmap &= 0x00000f00;
2107 else if (rssi == 2)
2108 ratr_bitmap &= 0x00000ff0;
2109 else
2110 ratr_bitmap &= 0x00000ff5;
2111 break;
2112 case WIRELESS_MODE_A:
2113 ratr_index = RATR_INX_WIRELESS_A;
2114 ratr_bitmap &= 0x00000ff0;
2115 break;
2116 case WIRELESS_MODE_N_24G:
2117 case WIRELESS_MODE_N_5G:
2118 ratr_index = RATR_INX_WIRELESS_NGB;
2119
2120 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2121 if (rssi == 1)
2122 ratr_bitmap &= 0x00070000;
2123 else if (rssi == 2)
2124 ratr_bitmap &= 0x0007f000;
2125 else
2126 ratr_bitmap &= 0x0007f005;
2127 } else {
2128 if (rtlphy->rf_type == RF_1T2R ||
2129 rtlphy->rf_type == RF_1T1R) {
2130 if (ctx40) {
2131 if (rssi == 1)
2132 ratr_bitmap &= 0x000f0000;
2133 else if (rssi == 2)
2134 ratr_bitmap &= 0x000ff000;
2135 else
2136 ratr_bitmap &= 0x000ff015;
2137 } else {
2138 if (rssi == 1)
2139 ratr_bitmap &= 0x000f0000;
2140 else if (rssi == 2)
2141 ratr_bitmap &= 0x000ff000;
2142 else
2143 ratr_bitmap &= 0x000ff005;
2144 }
2145 } else {
2146 if (ctx40) {
2147 if (rssi == 1)
2148 ratr_bitmap &= 0x0f8f0000;
2149 else if (rssi == 2)
2150 ratr_bitmap &= 0x0f8ff000;
2151 else
2152 ratr_bitmap &= 0x0f8ff015;
2153 } else {
2154 if (rssi == 1)
2155 ratr_bitmap &= 0x0f8f0000;
2156 else if (rssi == 2)
2157 ratr_bitmap &= 0x0f8ff000;
2158 else
2159 ratr_bitmap &= 0x0f8ff005;
2160 }
2161 }
2162 }
2163
2164 if ((ctx40 && short40) || (!ctx40 && short20)) {
2165 if (macid == 0)
2166 shortgi = true;
2167 else if (macid == 1)
2168 shortgi = false;
2169 }
2170 break;
2171 default:
2172 ratr_index = RATR_INX_WIRELESS_NGB;
2173
2174 if (rtlphy->rf_type == RF_1T2R)
2175 ratr_bitmap &= 0x000ff0ff;
2176 else
2177 ratr_bitmap &= 0x0f0ff0ff;
2178 break;
2179 }
2180 sta_entry->ratr_index = ratr_index;
2181
2182 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2183 "ratr_bitmap :%x\n", ratr_bitmap);
2184 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2185 (ratr_index << 28);
2186 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2187 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2188 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2189 ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2190 rate_mask[2], rate_mask[3], rate_mask[4]);
2191 rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2192 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2193}
2194
2195void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2196 struct ieee80211_sta *sta, u8 rssi)
2197{
2198 struct rtl_priv *rtlpriv = rtl_priv(hw);
2199
2200 if (rtlpriv->dm.useramask)
2201 rtl88ee_update_hal_rate_mask(hw, sta, rssi);
2202 else
2203 rtl88ee_update_hal_rate_table(hw, sta);
2204}
2205
2206void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2207{
2208 struct rtl_priv *rtlpriv = rtl_priv(hw);
2209 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2210 u16 sifs_timer;
2211
2212 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2213 (u8 *)&mac->slot_time);
2214 if (!mac->ht_enable)
2215 sifs_timer = 0x0a0a;
2216 else
2217 sifs_timer = 0x0e0e;
2218 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2219}
2220
2221bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2222{
2223 struct rtl_priv *rtlpriv = rtl_priv(hw);
2224 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2225 enum rf_pwrstate state_toset;
2226 u32 u4tmp;
2227 bool actuallyset = false;
2228
2229 if (rtlpriv->rtlhal.being_init_adapter)
2230 return false;
2231
2232 if (ppsc->swrf_processing)
2233 return false;
2234
2235 spin_lock(&rtlpriv->locks.rf_ps_lock);
2236 if (ppsc->rfchange_inprogress) {
2237 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2238 return false;
2239 } else {
2240 ppsc->rfchange_inprogress = true;
2241 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2242 }
2243
2244 u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2245 state_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2246
2247
2248 if ((ppsc->hwradiooff == true) && (state_toset == ERFON)) {
2249 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2250 "GPIOChangeRF - HW Radio ON, RF ON\n");
2251
2252 state_toset = ERFON;
2253 ppsc->hwradiooff = false;
2254 actuallyset = true;
2255 } else if ((ppsc->hwradiooff == false) && (state_toset == ERFOFF)) {
2256 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2257 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2258
2259 state_toset = ERFOFF;
2260 ppsc->hwradiooff = true;
2261 actuallyset = true;
2262 }
2263
2264 if (actuallyset) {
2265 spin_lock(&rtlpriv->locks.rf_ps_lock);
2266 ppsc->rfchange_inprogress = false;
2267 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2268 } else {
2269 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2270 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2271
2272 spin_lock(&rtlpriv->locks.rf_ps_lock);
2273 ppsc->rfchange_inprogress = false;
2274 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2275 }
2276
2277 *valid = 1;
2278 return !ppsc->hwradiooff;
2279}
2280
2281static void add_one_key(struct ieee80211_hw *hw, u8 *macaddr,
2282 struct rtl_mac *mac, u32 key, u32 id,
2283 u8 enc_algo, bool is_pairwise)
2284{
2285 struct rtl_priv *rtlpriv = rtl_priv(hw);
2286 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2287
2288 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "add one entry\n");
2289 if (is_pairwise) {
2290 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "set Pairwise key\n");
2291
2292 rtl_cam_add_one_entry(hw, macaddr, key, id, enc_algo,
2293 CAM_CONFIG_NO_USEDK,
2294 rtlpriv->sec.key_buf[key]);
2295 } else {
2296 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "set group key\n");
2297
2298 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2299 rtl_cam_add_one_entry(hw, rtlefuse->dev_addr,
2300 PAIRWISE_KEYIDX,
2301 CAM_PAIRWISE_KEY_POSITION,
2302 enc_algo,
2303 CAM_CONFIG_NO_USEDK,
2304 rtlpriv->sec.key_buf[id]);
2305 }
2306
2307 rtl_cam_add_one_entry(hw, macaddr, key, id, enc_algo,
2308 CAM_CONFIG_NO_USEDK,
2309 rtlpriv->sec.key_buf[id]);
2310 }
2311}
2312
2313void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key,
2314 u8 *mac_ad, bool is_group, u8 enc_algo,
2315 bool is_wepkey, bool clear_all)
2316{
2317 struct rtl_priv *rtlpriv = rtl_priv(hw);
2318 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2319 u8 *macaddr = mac_ad;
2320 u32 id = 0;
2321 bool is_pairwise = false;
2322
2323 static u8 cam_const_addr[4][6] = {
2324 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2325 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2326 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2327 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2328 };
2329 static u8 cam_const_broad[] = {
2330 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2331 };
2332
2333 if (clear_all) {
2334 u8 idx = 0;
2335 u8 cam_offset = 0;
2336 u8 clear_number = 5;
2337
2338 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2339
2340 for (idx = 0; idx < clear_number; idx++) {
2341 rtl_cam_mark_invalid(hw, cam_offset + idx);
2342 rtl_cam_empty_entry(hw, cam_offset + idx);
2343
2344 if (idx < 5) {
2345 memset(rtlpriv->sec.key_buf[idx], 0,
2346 MAX_KEY_LEN);
2347 rtlpriv->sec.key_len[idx] = 0;
2348 }
2349 }
2350
2351 } else {
2352 switch (enc_algo) {
2353 case WEP40_ENCRYPTION:
2354 enc_algo = CAM_WEP40;
2355 break;
2356 case WEP104_ENCRYPTION:
2357 enc_algo = CAM_WEP104;
2358 break;
2359 case TKIP_ENCRYPTION:
2360 enc_algo = CAM_TKIP;
2361 break;
2362 case AESCCMP_ENCRYPTION:
2363 enc_algo = CAM_AES;
2364 break;
2365 default:
2366 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2367 "switch case not processed\n");
2368 enc_algo = CAM_TKIP;
2369 break;
2370 }
2371
2372 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2373 macaddr = cam_const_addr[key];
2374 id = key;
2375 } else {
2376 if (is_group) {
2377 macaddr = cam_const_broad;
2378 id = key;
2379 } else {
2380 if (mac->opmode == NL80211_IFTYPE_AP ||
2381 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2382 id = rtl_cam_get_free_entry(hw, mac_ad);
2383 if (id >= TOTAL_CAM_ENTRY) {
2384 RT_TRACE(rtlpriv, COMP_SEC,
2385 DBG_EMERG,
2386 "Can not find free hw security cam entry\n");
2387 return;
2388 }
2389 } else {
2390 id = CAM_PAIRWISE_KEY_POSITION;
2391 }
2392
2393 key = PAIRWISE_KEYIDX;
2394 is_pairwise = true;
2395 }
2396 }
2397
2398 if (rtlpriv->sec.key_len[key] == 0) {
2399 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2400 "delete one entry, id is %d\n", id);
2401 if (mac->opmode == NL80211_IFTYPE_AP ||
2402 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2403 rtl_cam_del_entry(hw, mac_ad);
2404 rtl_cam_delete_one_entry(hw, mac_ad, id);
2405 } else {
2406 add_one_key(hw, macaddr, mac, key, id, enc_algo,
2407 is_pairwise);
2408 }
2409 }
2410}
2411
2412static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2413{
2414 struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
2415 struct bt_coexist_info coexist = rppriv->bt_coexist;
2416
2417 coexist.bt_coexistence = rppriv->bt_coexist.eeprom_bt_coexist;
2418 coexist.bt_ant_num = coexist.eeprom_bt_ant_num;
2419 coexist.bt_coexist_type = coexist.eeprom_bt_type;
2420
2421 if (coexist.reg_bt_iso == 2)
2422 coexist.bt_ant_isolation = coexist.eeprom_bt_ant_isol;
2423 else
2424 coexist.bt_ant_isolation = coexist.reg_bt_iso;
2425
2426 coexist.bt_radio_shared_type = coexist.eeprom_bt_radio_shared;
2427
2428 if (coexist.bt_coexistence) {
2429 if (coexist.reg_bt_sco == 1)
2430 coexist.bt_service = BT_OTHER_ACTION;
2431 else if (coexist.reg_bt_sco == 2)
2432 coexist.bt_service = BT_SCO;
2433 else if (coexist.reg_bt_sco == 4)
2434 coexist.bt_service = BT_BUSY;
2435 else if (coexist.reg_bt_sco == 5)
2436 coexist.bt_service = BT_OTHERBUSY;
2437 else
2438 coexist.bt_service = BT_IDLE;
2439
2440 coexist.bt_edca_ul = 0;
2441 coexist.bt_edca_dl = 0;
2442 coexist.bt_rssi_state = 0xff;
2443 }
2444}
2445
2446void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2447 bool auto_load_fail, u8 *hwinfo)
2448{
2449 rtl8188ee_bt_var_init(hw);
2450}
2451
2452void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2453{
2454 struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
2455
2456 /* 0:Low, 1:High, 2:From Efuse. */
2457 rppriv->bt_coexist.reg_bt_iso = 2;
2458 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2459 rppriv->bt_coexist.reg_bt_sco = 3;
2460 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2461 rppriv->bt_coexist.reg_bt_sco = 0;
2462}
2463
2464void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2465{
2466 struct rtl_priv *rtlpriv = rtl_priv(hw);
2467 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2468 struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
2469 struct bt_coexist_info coexist = rppriv->bt_coexist;
2470 u8 u1_tmp;
2471
2472 if (coexist.bt_coexistence &&
2473 ((coexist.bt_coexist_type == BT_CSR_BC4) ||
2474 coexist.bt_coexist_type == BT_CSR_BC8)) {
2475 if (coexist.bt_ant_isolation)
2476 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2477
2478 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2479 BIT_OFFSET_LEN_MASK_32(0, 1);
2480 u1_tmp = u1_tmp | ((coexist.bt_ant_isolation == 1) ?
2481 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2482 ((coexist.bt_service == BT_SCO) ?
2483 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2484 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2485
2486 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2487 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2488 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2489
2490 /* Config to 1T1R. */
2491 if (rtlphy->rf_type == RF_1T1R) {
2492 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2493 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2494 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2495
2496 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2497 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2498 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2499 }
2500 }
2501}
2502
2503void rtl88ee_suspend(struct ieee80211_hw *hw)
2504{
2505}
2506
2507void rtl88ee_resume(struct ieee80211_hw *hw)
2508{
2509}
2510
2511/* Turn on AAP (RCR:bit 0) for promicuous mode. */
2512void rtl88ee_allow_all_destaddr(struct ieee80211_hw *hw,
2513 bool allow_all_da, bool write_into_reg)
2514{
2515 struct rtl_priv *rtlpriv = rtl_priv(hw);
2516 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2517
2518 if (allow_all_da) /* Set BIT0 */
2519 rtlpci->receive_config |= RCR_AAP;
2520 else /* Clear BIT0 */
2521 rtlpci->receive_config &= ~RCR_AAP;
2522
2523 if (write_into_reg)
2524 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2525
2526 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2527 "receive_config = 0x%08X, write_into_reg =%d\n",
2528 rtlpci->receive_config, write_into_reg);
2529}
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/hw.h b/drivers/net/wireless/rtlwifi/rtl8188ee/hw.h
new file mode 100644
index 000000000000..b4460a41bd01
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/hw.h
@@ -0,0 +1,68 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CE_HW_H__
31#define __RTL92CE_HW_H__
32
33void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
34void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw);
35void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
36 u32 *p_inta, u32 *p_intb);
37int rtl88ee_hw_init(struct ieee80211_hw *hw);
38void rtl88ee_card_disable(struct ieee80211_hw *hw);
39void rtl88ee_enable_interrupt(struct ieee80211_hw *hw);
40void rtl88ee_disable_interrupt(struct ieee80211_hw *hw);
41int rtl88ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
42void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
43void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci);
44void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw);
45void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw);
46void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
47 u32 add_msr, u32 rm_msr);
48void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
49void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
50 struct ieee80211_sta *sta, u8 rssi_level);
51void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw);
52bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
53void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw);
54void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
55 u8 *p_macaddr, bool is_group, u8 enc_algo,
56 bool is_wepkey, bool clear_all);
57
58void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
59 bool autoload_fail, u8 *hwinfo);
60void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw);
61void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw);
62void rtl88ee_suspend(struct ieee80211_hw *hw);
63void rtl88ee_resume(struct ieee80211_hw *hw);
64void rtl88ee_allow_all_destaddr(struct ieee80211_hw *hw,
65 bool allow_all_da, bool write_into_reg);
66void rtl88ee_fw_clk_off_timer_callback(unsigned long data);
67
68#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/led.c b/drivers/net/wireless/rtlwifi/rtl8188ee/led.c
new file mode 100644
index 000000000000..95d42afd7719
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/led.c
@@ -0,0 +1,157 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "pci.h"
32#include "reg.h"
33#include "led.h"
34
35static void rtl88ee_init_led(struct ieee80211_hw *hw,
36 struct rtl_led *pled, enum rtl_led_pin ledpin)
37{
38 pled->hw = hw;
39 pled->ledpin = ledpin;
40 pled->ledon = false;
41}
42
43void rtl88ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
44{
45 u8 ledcfg;
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47
48 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
49 "LedAddr:%X ledpin =%d\n", REG_LEDCFG2, pled->ledpin);
50
51 switch (pled->ledpin) {
52 case LED_PIN_GPIO0:
53 break;
54 case LED_PIN_LED0:
55 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
56 rtl_write_byte(rtlpriv, REG_LEDCFG2,
57 (ledcfg & 0xf0) | BIT(5) | BIT(6));
58 break;
59 case LED_PIN_LED1:
60 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
61 rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg & 0x10);
62 break;
63 default:
64 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
65 "switch case not processed\n");
66 break;
67 }
68 pled->ledon = true;
69}
70
71void rtl88ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
72{
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
75 u8 ledcfg;
76 u8 val;
77
78 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
79 "LedAddr:%X ledpin =%d\n", REG_LEDCFG2, pled->ledpin);
80
81 switch (pled->ledpin) {
82 case LED_PIN_GPIO0:
83 break;
84 case LED_PIN_LED0:
85 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
86 ledcfg &= 0xf0;
87 val = ledcfg | BIT(3) | BIT(5) | BIT(6);
88 if (pcipriv->ledctl.led_opendrain == true) {
89 rtl_write_byte(rtlpriv, REG_LEDCFG2, val);
90 ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
91 val = ledcfg & 0xFE;
92 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, val);
93 } else {
94 rtl_write_byte(rtlpriv, REG_LEDCFG2, val);
95 }
96 break;
97 case LED_PIN_LED1:
98 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
99 ledcfg &= 0x10;
100 rtl_write_byte(rtlpriv, REG_LEDCFG1, (ledcfg | BIT(3)));
101 break;
102 default:
103 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
104 "switch case not processed\n");
105 break;
106 }
107 pled->ledon = false;
108}
109
110void rtl88ee_init_sw_leds(struct ieee80211_hw *hw)
111{
112 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
113
114 rtl88ee_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0);
115 rtl88ee_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1);
116}
117
118static void rtl88ee_sw_led_control(struct ieee80211_hw *hw,
119 enum led_ctl_mode ledaction)
120{
121 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
122 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
123
124 switch (ledaction) {
125 case LED_CTL_POWER_ON:
126 case LED_CTL_LINK:
127 case LED_CTL_NO_LINK:
128 rtl88ee_sw_led_on(hw, pLed0);
129 break;
130 case LED_CTL_POWER_OFF:
131 rtl88ee_sw_led_off(hw, pLed0);
132 break;
133 default:
134 break;
135 }
136}
137
138void rtl88ee_led_control(struct ieee80211_hw *hw,
139 enum led_ctl_mode ledaction)
140{
141 struct rtl_priv *rtlpriv = rtl_priv(hw);
142 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
143
144 if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
145 (ledaction == LED_CTL_TX ||
146 ledaction == LED_CTL_RX ||
147 ledaction == LED_CTL_SITE_SURVEY ||
148 ledaction == LED_CTL_LINK ||
149 ledaction == LED_CTL_NO_LINK ||
150 ledaction == LED_CTL_START_TO_LINK ||
151 ledaction == LED_CTL_POWER_ON)) {
152 return;
153 }
154 RT_TRACE(rtlpriv, COMP_LED, DBG_TRACE, "ledaction %d,\n",
155 ledaction);
156 rtl88ee_sw_led_control(hw, ledaction);
157}
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/led.h b/drivers/net/wireless/rtlwifi/rtl8188ee/led.h
new file mode 100644
index 000000000000..4073f6f847b2
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/led.h
@@ -0,0 +1,38 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CE_LED_H__
31#define __RTL92CE_LED_H__
32
33void rtl88ee_init_sw_leds(struct ieee80211_hw *hw);
34void rtl88ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
35void rtl88ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
36void rtl88ee_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
37
38#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/phy.c b/drivers/net/wireless/rtlwifi/rtl8188ee/phy.c
new file mode 100644
index 000000000000..c2856315a8c9
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/phy.c
@@ -0,0 +1,2212 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "pci.h"
32#include "ps.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "rf.h"
37#include "dm.h"
38#include "table.h"
39
40static void set_baseband_phy_config(struct ieee80211_hw *hw);
41static void set_baseband_agc_config(struct ieee80211_hw *hw);
42static void store_pwrindex_offset(struct ieee80211_hw *hw,
43 u32 regaddr, u32 bitmask,
44 u32 data);
45static bool check_cond(struct ieee80211_hw *hw, const u32 condition);
46
47static u32 rf_serial_read(struct ieee80211_hw *hw,
48 enum radio_path rfpath, u32 offset)
49{
50 struct rtl_priv *rtlpriv = rtl_priv(hw);
51 struct rtl_phy *rtlphy = &(rtlpriv->phy);
52 struct bb_reg_def *phreg = &rtlphy->phyreg_def[rfpath];
53 u32 newoffset;
54 u32 tmplong, tmplong2;
55 u8 rfpi_enable = 0;
56 u32 ret;
57 int jj = RF90_PATH_A;
58 int kk = RF90_PATH_B;
59
60 offset &= 0xff;
61 newoffset = offset;
62 if (RT_CANNOT_IO(hw)) {
63 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
64 return 0xFFFFFFFF;
65 }
66 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
67 if (rfpath == jj)
68 tmplong2 = tmplong;
69 else
70 tmplong2 = rtl_get_bbreg(hw, phreg->rfhssi_para2, MASKDWORD);
71 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
72 (newoffset << 23) | BLSSIREADEDGE;
73 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
74 tmplong & (~BLSSIREADEDGE));
75 mdelay(1);
76 rtl_set_bbreg(hw, phreg->rfhssi_para2, MASKDWORD, tmplong2);
77 mdelay(2);
78 if (rfpath == jj)
79 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
80 BIT(8));
81 else if (rfpath == kk)
82 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
83 BIT(8));
84 if (rfpi_enable)
85 ret = rtl_get_bbreg(hw, phreg->rf_rbpi, BLSSIREADBACKDATA);
86 else
87 ret = rtl_get_bbreg(hw, phreg->rf_rb, BLSSIREADBACKDATA);
88 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]= 0x%x\n",
89 rfpath, phreg->rf_rb, ret);
90 return ret;
91}
92
93static void rf_serial_write(struct ieee80211_hw *hw,
94 enum radio_path rfpath, u32 offset,
95 u32 data)
96{
97 u32 data_and_addr;
98 u32 newoffset;
99 struct rtl_priv *rtlpriv = rtl_priv(hw);
100 struct rtl_phy *rtlphy = &(rtlpriv->phy);
101 struct bb_reg_def *phreg = &rtlphy->phyreg_def[rfpath];
102
103 if (RT_CANNOT_IO(hw)) {
104 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
105 return;
106 }
107 offset &= 0xff;
108 newoffset = offset;
109 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
110 rtl_set_bbreg(hw, phreg->rf3wire_offset, MASKDWORD, data_and_addr);
111 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]= 0x%x\n",
112 rfpath, phreg->rf3wire_offset, data_and_addr);
113}
114
115static u32 cal_bit_shift(u32 bitmask)
116{
117 u32 i;
118
119 for (i = 0; i <= 31; i++) {
120 if (((bitmask >> i) & 0x1) == 1)
121 break;
122 }
123 return i;
124}
125
126static bool config_bb_with_header(struct ieee80211_hw *hw,
127 u8 configtype)
128{
129 if (configtype == BASEBAND_CONFIG_PHY_REG)
130 set_baseband_phy_config(hw);
131 else if (configtype == BASEBAND_CONFIG_AGC_TAB)
132 set_baseband_agc_config(hw);
133 return true;
134}
135
136static bool config_bb_with_pgheader(struct ieee80211_hw *hw,
137 u8 configtype)
138{
139 struct rtl_priv *rtlpriv = rtl_priv(hw);
140 int i;
141 u32 *table_pg;
142 u16 tbl_page_len;
143 u32 v1 = 0, v2 = 0;
144
145 tbl_page_len = RTL8188EEPHY_REG_ARRAY_PGLEN;
146 table_pg = RTL8188EEPHY_REG_ARRAY_PG;
147
148 if (configtype == BASEBAND_CONFIG_PHY_REG) {
149 for (i = 0; i < tbl_page_len; i = i + 3) {
150 v1 = table_pg[i];
151 v2 = table_pg[i + 1];
152
153 if (v1 < 0xcdcdcdcd) {
154 if (table_pg[i] == 0xfe)
155 mdelay(50);
156 else if (table_pg[i] == 0xfd)
157 mdelay(5);
158 else if (table_pg[i] == 0xfc)
159 mdelay(1);
160 else if (table_pg[i] == 0xfb)
161 udelay(50);
162 else if (table_pg[i] == 0xfa)
163 udelay(5);
164 else if (table_pg[i] == 0xf9)
165 udelay(1);
166
167 store_pwrindex_offset(hw, table_pg[i],
168 table_pg[i + 1],
169 table_pg[i + 2]);
170 continue;
171 } else {
172 if (!check_cond(hw, table_pg[i])) {
173 /*don't need the hw_body*/
174 i += 2; /* skip the pair of expression*/
175 v1 = table_pg[i];
176 v2 = table_pg[i + 1];
177 while (v2 != 0xDEAD) {
178 i += 3;
179 v1 = table_pg[i];
180 v2 = table_pg[i + 1];
181 }
182 }
183 }
184 }
185 } else {
186 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
187 "configtype != BaseBand_Config_PHY_REG\n");
188 }
189 return true;
190}
191
192static bool config_parafile(struct ieee80211_hw *hw)
193{
194 struct rtl_priv *rtlpriv = rtl_priv(hw);
195 struct rtl_phy *rtlphy = &(rtlpriv->phy);
196 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw));
197 bool rtstatus;
198
199 rtstatus = config_bb_with_header(hw, BASEBAND_CONFIG_PHY_REG);
200 if (rtstatus != true) {
201 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
202 return false;
203 }
204
205 if (fuse->autoload_failflag == false) {
206 rtlphy->pwrgroup_cnt = 0;
207 rtstatus = config_bb_with_pgheader(hw, BASEBAND_CONFIG_PHY_REG);
208 }
209 if (rtstatus != true) {
210 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
211 return false;
212 }
213 rtstatus = config_bb_with_header(hw, BASEBAND_CONFIG_AGC_TAB);
214 if (rtstatus != true) {
215 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
216 return false;
217 }
218 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
219 RFPGA0_XA_HSSIPARAMETER2, 0x200));
220
221 return true;
222}
223
224static void rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
225{
226 struct rtl_priv *rtlpriv = rtl_priv(hw);
227 struct rtl_phy *rtlphy = &(rtlpriv->phy);
228 int jj = RF90_PATH_A;
229 int kk = RF90_PATH_B;
230
231 rtlphy->phyreg_def[jj].rfintfs = RFPGA0_XAB_RFINTERFACESW;
232 rtlphy->phyreg_def[kk].rfintfs = RFPGA0_XAB_RFINTERFACESW;
233 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
234 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
235
236 rtlphy->phyreg_def[jj].rfintfi = RFPGA0_XAB_RFINTERFACERB;
237 rtlphy->phyreg_def[kk].rfintfi = RFPGA0_XAB_RFINTERFACERB;
238 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
239 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
240
241 rtlphy->phyreg_def[jj].rfintfo = RFPGA0_XA_RFINTERFACEOE;
242 rtlphy->phyreg_def[kk].rfintfo = RFPGA0_XB_RFINTERFACEOE;
243
244 rtlphy->phyreg_def[jj].rfintfe = RFPGA0_XA_RFINTERFACEOE;
245 rtlphy->phyreg_def[kk].rfintfe = RFPGA0_XB_RFINTERFACEOE;
246
247 rtlphy->phyreg_def[jj].rf3wire_offset = RFPGA0_XA_LSSIPARAMETER;
248 rtlphy->phyreg_def[kk].rf3wire_offset = RFPGA0_XB_LSSIPARAMETER;
249
250 rtlphy->phyreg_def[jj].rflssi_select = rFPGA0_XAB_RFPARAMETER;
251 rtlphy->phyreg_def[kk].rflssi_select = rFPGA0_XAB_RFPARAMETER;
252 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
253 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
254
255 rtlphy->phyreg_def[jj].rftxgain_stage = RFPGA0_TXGAINSTAGE;
256 rtlphy->phyreg_def[kk].rftxgain_stage = RFPGA0_TXGAINSTAGE;
257 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
258 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
259
260 rtlphy->phyreg_def[jj].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
261 rtlphy->phyreg_def[kk].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
262
263 rtlphy->phyreg_def[jj].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
264 rtlphy->phyreg_def[kk].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
265
266 rtlphy->phyreg_def[jj].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
267 rtlphy->phyreg_def[kk].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
268 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
269 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
270
271 rtlphy->phyreg_def[jj].rfagc_control1 = ROFDM0_XAAGCCORE1;
272 rtlphy->phyreg_def[kk].rfagc_control1 = ROFDM0_XBAGCCORE1;
273 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
274 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
275
276 rtlphy->phyreg_def[jj].rfagc_control2 = ROFDM0_XAAGCCORE2;
277 rtlphy->phyreg_def[kk].rfagc_control2 = ROFDM0_XBAGCCORE2;
278 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
279 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
280
281 rtlphy->phyreg_def[jj].rfrxiq_imbal = ROFDM0_XARXIQIMBAL;
282 rtlphy->phyreg_def[kk].rfrxiq_imbal = ROFDM0_XBRXIQIMBAL;
283 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBAL;
284 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBAL;
285
286 rtlphy->phyreg_def[jj].rfrx_afe = ROFDM0_XARXAFE;
287 rtlphy->phyreg_def[kk].rfrx_afe = ROFDM0_XBRXAFE;
288 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
289 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
290
291 rtlphy->phyreg_def[jj].rftxiq_imbal = ROFDM0_XATXIQIMBAL;
292 rtlphy->phyreg_def[kk].rftxiq_imbal = ROFDM0_XBTXIQIMBAL;
293 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBAL;
294 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBAL;
295
296 rtlphy->phyreg_def[jj].rftx_afe = ROFDM0_XATXAFE;
297 rtlphy->phyreg_def[kk].rftx_afe = ROFDM0_XBTXAFE;
298
299 rtlphy->phyreg_def[jj].rf_rb = RFPGA0_XA_LSSIREADBACK;
300 rtlphy->phyreg_def[kk].rf_rb = RFPGA0_XB_LSSIREADBACK;
301
302 rtlphy->phyreg_def[jj].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
303 rtlphy->phyreg_def[kk].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
304}
305
306static bool rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
307 u32 cmdtableidx, u32 cmdtablesz,
308 enum swchnlcmd_id cmdid,
309 u32 para1, u32 para2, u32 msdelay)
310{
311 struct swchnlcmd *pcmd;
312
313 if (cmdtable == NULL) {
314 RT_ASSERT(false, "cmdtable cannot be NULL.\n");
315 return false;
316 }
317
318 if (cmdtableidx >= cmdtablesz)
319 return false;
320
321 pcmd = cmdtable + cmdtableidx;
322 pcmd->cmdid = cmdid;
323 pcmd->para1 = para1;
324 pcmd->para2 = para2;
325 pcmd->msdelay = msdelay;
326 return true;
327}
328
329static bool chnl_step_by_step(struct ieee80211_hw *hw,
330 u8 channel, u8 *stage, u8 *step,
331 u32 *delay)
332{
333 struct rtl_priv *rtlpriv = rtl_priv(hw);
334 struct rtl_phy *rtlphy = &(rtlpriv->phy);
335 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
336 u32 precommoncmdcnt;
337 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
338 u32 postcommoncmdcnt;
339 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
340 u32 rfdependcmdcnt;
341 struct swchnlcmd *currentcmd = NULL;
342 u8 rfpath;
343 u8 num_total_rfpath = rtlphy->num_total_rfpath;
344
345 precommoncmdcnt = 0;
346 rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
347 MAX_PRECMD_CNT,
348 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
349 rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
350 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
351
352 postcommoncmdcnt = 0;
353
354 rtl88e_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
355 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
356
357 rfdependcmdcnt = 0;
358
359 RT_ASSERT((channel >= 1 && channel <= 14),
360 "illegal channel for Zebra: %d\n", channel);
361
362 rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
363 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
364 RF_CHNLBW, channel, 10);
365
366 rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
367 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
368 0);
369
370 do {
371 switch (*stage) {
372 case 0:
373 currentcmd = &precommoncmd[*step];
374 break;
375 case 1:
376 currentcmd = &rfdependcmd[*step];
377 break;
378 case 2:
379 currentcmd = &postcommoncmd[*step];
380 break;
381 }
382
383 if (currentcmd->cmdid == CMDID_END) {
384 if ((*stage) == 2) {
385 return true;
386 } else {
387 (*stage)++;
388 (*step) = 0;
389 continue;
390 }
391 }
392
393 switch (currentcmd->cmdid) {
394 case CMDID_SET_TXPOWEROWER_LEVEL:
395 rtl88e_phy_set_txpower_level(hw, channel);
396 break;
397 case CMDID_WRITEPORT_ULONG:
398 rtl_write_dword(rtlpriv, currentcmd->para1,
399 currentcmd->para2);
400 break;
401 case CMDID_WRITEPORT_USHORT:
402 rtl_write_word(rtlpriv, currentcmd->para1,
403 (u16) currentcmd->para2);
404 break;
405 case CMDID_WRITEPORT_UCHAR:
406 rtl_write_byte(rtlpriv, currentcmd->para1,
407 (u8) currentcmd->para2);
408 break;
409 case CMDID_RF_WRITEREG:
410 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
411 rtlphy->rfreg_chnlval[rfpath] =
412 ((rtlphy->rfreg_chnlval[rfpath] &
413 0xfffffc00) | currentcmd->para2);
414
415 rtl_set_rfreg(hw, (enum radio_path)rfpath,
416 currentcmd->para1,
417 RFREG_OFFSET_MASK,
418 rtlphy->rfreg_chnlval[rfpath]);
419 }
420 break;
421 default:
422 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
423 "switch case not processed\n");
424 break;
425 }
426
427 break;
428 } while (true);
429
430 (*delay) = currentcmd->msdelay;
431 (*step)++;
432 return false;
433}
434
435static long rtl88e_pwr_idx_dbm(struct ieee80211_hw *hw,
436 enum wireless_mode wirelessmode,
437 u8 txpwridx)
438{
439 long offset;
440 long pwrout_dbm;
441
442 switch (wirelessmode) {
443 case WIRELESS_MODE_B:
444 offset = -7;
445 break;
446 case WIRELESS_MODE_G:
447 case WIRELESS_MODE_N_24G:
448 offset = -8;
449 break;
450 default:
451 offset = -8;
452 break;
453 }
454 pwrout_dbm = txpwridx / 2 + offset;
455 return pwrout_dbm;
456}
457
458static void rtl88e_phy_set_io(struct ieee80211_hw *hw)
459{
460 struct rtl_priv *rtlpriv = rtl_priv(hw);
461 struct rtl_phy *rtlphy = &(rtlpriv->phy);
462 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
463
464 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
465 "--->Cmd(%#x), set_io_inprogress(%d)\n",
466 rtlphy->current_io_type, rtlphy->set_io_inprogress);
467 switch (rtlphy->current_io_type) {
468 case IO_CMD_RESUME_DM_BY_SCAN:
469 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
470 /*rtl92c_dm_write_dig(hw);*/
471 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel);
472 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83);
473 break;
474 case IO_CMD_PAUSE_DM_BY_SCAN:
475 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
476 dm_digtable->cur_igvalue = 0x17;
477 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40);
478 break;
479 default:
480 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
481 "switch case not processed\n");
482 break;
483 }
484 rtlphy->set_io_inprogress = false;
485 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
486 "(%#x)\n", rtlphy->current_io_type);
487}
488
489u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
490{
491 struct rtl_priv *rtlpriv = rtl_priv(hw);
492 u32 returnvalue, originalvalue, bitshift;
493
494 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
495 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
496 originalvalue = rtl_read_dword(rtlpriv, regaddr);
497 bitshift = cal_bit_shift(bitmask);
498 returnvalue = (originalvalue & bitmask) >> bitshift;
499
500 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
501 "BBR MASK = 0x%x Addr[0x%x]= 0x%x\n", bitmask,
502 regaddr, originalvalue);
503
504 return returnvalue;
505}
506
507void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw,
508 u32 regaddr, u32 bitmask, u32 data)
509{
510 struct rtl_priv *rtlpriv = rtl_priv(hw);
511 u32 originalvalue, bitshift;
512
513 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
514 "regaddr(%#x), bitmask(%#x),data(%#x)\n",
515 regaddr, bitmask, data);
516
517 if (bitmask != MASKDWORD) {
518 originalvalue = rtl_read_dword(rtlpriv, regaddr);
519 bitshift = cal_bit_shift(bitmask);
520 data = ((originalvalue & (~bitmask)) | (data << bitshift));
521 }
522
523 rtl_write_dword(rtlpriv, regaddr, data);
524
525 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
526 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
527 regaddr, bitmask, data);
528}
529
530u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw,
531 enum radio_path rfpath, u32 regaddr, u32 bitmask)
532{
533 struct rtl_priv *rtlpriv = rtl_priv(hw);
534 u32 original_value, readback_value, bitshift;
535 unsigned long flags;
536
537 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
538 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
539 regaddr, rfpath, bitmask);
540
541 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
542
543
544 original_value = rf_serial_read(hw, rfpath, regaddr);
545 bitshift = cal_bit_shift(bitmask);
546 readback_value = (original_value & bitmask) >> bitshift;
547
548 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
549
550 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
551 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
552 regaddr, rfpath, bitmask, original_value);
553
554 return readback_value;
555}
556
557void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw,
558 enum radio_path rfpath,
559 u32 regaddr, u32 bitmask, u32 data)
560{
561 struct rtl_priv *rtlpriv = rtl_priv(hw);
562 u32 original_value, bitshift;
563 unsigned long flags;
564
565 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
566 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
567 regaddr, bitmask, data, rfpath);
568
569 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
570
571 if (bitmask != RFREG_OFFSET_MASK) {
572 original_value = rf_serial_read(hw, rfpath, regaddr);
573 bitshift = cal_bit_shift(bitmask);
574 data = ((original_value & (~bitmask)) |
575 (data << bitshift));
576 }
577
578 rf_serial_write(hw, rfpath, regaddr, data);
579
580
581 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
582
583 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
584 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
585 regaddr, bitmask, data, rfpath);
586}
587
588static bool config_mac_with_header(struct ieee80211_hw *hw)
589{
590 struct rtl_priv *rtlpriv = rtl_priv(hw);
591 u32 i;
592 u32 arraylength;
593 u32 *ptrarray;
594
595 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8188EMACPHY_Array\n");
596 arraylength = RTL8188EEMAC_1T_ARRAYLEN;
597 ptrarray = RTL8188EEMAC_1T_ARRAY;
598 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
599 "Img:RTL8188EEMAC_1T_ARRAY LEN %d\n", arraylength);
600 for (i = 0; i < arraylength; i = i + 2)
601 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
602 return true;
603}
604
605bool rtl88e_phy_mac_config(struct ieee80211_hw *hw)
606{
607 struct rtl_priv *rtlpriv = rtl_priv(hw);
608 bool rtstatus = config_mac_with_header(hw);
609
610 rtl_write_byte(rtlpriv, 0x04CA, 0x0B);
611 return rtstatus;
612}
613
614bool rtl88e_phy_bb_config(struct ieee80211_hw *hw)
615{
616 bool rtstatus = true;
617 struct rtl_priv *rtlpriv = rtl_priv(hw);
618 u16 regval;
619 u8 reg_hwparafile = 1;
620 u32 tmp;
621 rtl88e_phy_init_bb_rf_register_definition(hw);
622 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
623 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
624 regval | BIT(13) | BIT(0) | BIT(1));
625
626 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
627 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
628 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
629 FEN_BB_GLB_RSTN | FEN_BBRSTB);
630 tmp = rtl_read_dword(rtlpriv, 0x4c);
631 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23));
632 if (reg_hwparafile == 1)
633 rtstatus = config_parafile(hw);
634 return rtstatus;
635}
636
637bool rtl88e_phy_rf_config(struct ieee80211_hw *hw)
638{
639 return rtl88e_phy_rf6052_config(hw);
640}
641
642static bool check_cond(struct ieee80211_hw *hw,
643 const u32 condition)
644{
645 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
646 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw));
647 u32 _board = fuse->board_type; /*need efuse define*/
648 u32 _interface = rtlhal->interface;
649 u32 _platform = 0x08;/*SupportPlatform */
650 u32 cond = condition;
651
652 if (condition == 0xCDCDCDCD)
653 return true;
654
655 cond = condition & 0xFF;
656 if ((_board & cond) == 0 && cond != 0x1F)
657 return false;
658
659 cond = condition & 0xFF00;
660 cond = cond >> 8;
661 if ((_interface & cond) == 0 && cond != 0x07)
662 return false;
663
664 cond = condition & 0xFF0000;
665 cond = cond >> 16;
666 if ((_platform & cond) == 0 && cond != 0x0F)
667 return false;
668 return true;
669}
670
671static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw,
672 u32 addr, u32 data, enum radio_path rfpath,
673 u32 regaddr)
674{
675 if (addr == 0xffe) {
676 mdelay(50);
677 } else if (addr == 0xfd) {
678 mdelay(5);
679 } else if (addr == 0xfc) {
680 mdelay(1);
681 } else if (addr == 0xfb) {
682 udelay(50);
683 } else if (addr == 0xfa) {
684 udelay(5);
685 } else if (addr == 0xf9) {
686 udelay(1);
687 } else {
688 rtl_set_rfreg(hw, rfpath, regaddr,
689 RFREG_OFFSET_MASK,
690 data);
691 udelay(1);
692 }
693}
694
695static void rtl88_config_s(struct ieee80211_hw *hw,
696 u32 addr, u32 data)
697{
698 u32 content = 0x1000; /*RF Content: radio_a_txt*/
699 u32 maskforphyset = (u32)(content & 0xE000);
700
701 _rtl8188e_config_rf_reg(hw, addr, data, RF90_PATH_A,
702 addr | maskforphyset);
703}
704
705static void _rtl8188e_config_bb_reg(struct ieee80211_hw *hw,
706 u32 addr, u32 data)
707{
708 if (addr == 0xfe) {
709 mdelay(50);
710 } else if (addr == 0xfd) {
711 mdelay(5);
712 } else if (addr == 0xfc) {
713 mdelay(1);
714 } else if (addr == 0xfb) {
715 udelay(50);
716 } else if (addr == 0xfa) {
717 udelay(5);
718 } else if (addr == 0xf9) {
719 udelay(1);
720 } else {
721 rtl_set_bbreg(hw, addr, MASKDWORD, data);
722 udelay(1);
723 }
724}
725
726
727#define NEXT_PAIR(v1, v2, i) \
728 do { \
729 i += 2; v1 = array_table[i]; \
730 v2 = array_table[i + 1]; \
731 } while (0)
732
733static void set_baseband_agc_config(struct ieee80211_hw *hw)
734{
735 int i;
736 u32 *array_table;
737 u16 arraylen;
738 struct rtl_priv *rtlpriv = rtl_priv(hw);
739 u32 v1 = 0, v2 = 0;
740
741 arraylen = RTL8188EEAGCTAB_1TARRAYLEN;
742 array_table = RTL8188EEAGCTAB_1TARRAY;
743
744 for (i = 0; i < arraylen; i += 2) {
745 v1 = array_table[i];
746 v2 = array_table[i + 1];
747 if (v1 < 0xCDCDCDCD) {
748 rtl_set_bbreg(hw, array_table[i], MASKDWORD,
749 array_table[i + 1]);
750 udelay(1);
751 continue;
752 } else {/*This line is the start line of branch.*/
753 if (!check_cond(hw, array_table[i])) {
754 /*Discard the following (offset, data) pairs*/
755 NEXT_PAIR(v1, v2, i);
756 while (v2 != 0xDEAD && v2 != 0xCDEF &&
757 v2 != 0xCDCD && i < arraylen - 2) {
758 NEXT_PAIR(v1, v2, i);
759 }
760 i -= 2; /* compensate for loop's += 2*/
761 } else {
762 /* Configure matched pairs and skip to end */
763 NEXT_PAIR(v1, v2, i);
764 while (v2 != 0xDEAD && v2 != 0xCDEF &&
765 v2 != 0xCDCD && i < arraylen - 2) {
766 rtl_set_bbreg(hw, array_table[i],
767 MASKDWORD,
768 array_table[i + 1]);
769 udelay(1);
770 NEXT_PAIR(v1, v2, i);
771 }
772
773 while (v2 != 0xDEAD && i < arraylen - 2)
774 NEXT_PAIR(v1, v2, i);
775 }
776 }
777 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
778 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
779 array_table[i],
780 array_table[i + 1]);
781 }
782}
783
784static void set_baseband_phy_config(struct ieee80211_hw *hw)
785{
786 int i;
787 u32 *array_table;
788 u16 arraylen;
789 u32 v1 = 0, v2 = 0;
790
791 arraylen = RTL8188EEPHY_REG_1TARRAYLEN;
792 array_table = RTL8188EEPHY_REG_1TARRAY;
793
794 for (i = 0; i < arraylen; i += 2) {
795 v1 = array_table[i];
796 v2 = array_table[i + 1];
797 if (v1 < 0xcdcdcdcd) {
798 _rtl8188e_config_bb_reg(hw, v1, v2);
799 } else {/*This line is the start line of branch.*/
800 if (!check_cond(hw, array_table[i])) {
801 /*Discard the following (offset, data) pairs*/
802 NEXT_PAIR(v1, v2, i);
803 while (v2 != 0xDEAD &&
804 v2 != 0xCDEF &&
805 v2 != 0xCDCD && i < arraylen - 2)
806 NEXT_PAIR(v1, v2, i);
807 i -= 2; /* prevent from for-loop += 2*/
808 } else {
809 /* Configure matched pairs and skip to end */
810 NEXT_PAIR(v1, v2, i);
811 while (v2 != 0xDEAD &&
812 v2 != 0xCDEF &&
813 v2 != 0xCDCD && i < arraylen - 2) {
814 _rtl8188e_config_bb_reg(hw, v1, v2);
815 NEXT_PAIR(v1, v2, i);
816 }
817
818 while (v2 != 0xDEAD && i < arraylen - 2)
819 NEXT_PAIR(v1, v2, i);
820 }
821 }
822 }
823}
824
825static void store_pwrindex_offset(struct ieee80211_hw *hw,
826 u32 regaddr, u32 bitmask,
827 u32 data)
828{
829 struct rtl_priv *rtlpriv = rtl_priv(hw);
830 struct rtl_phy *rtlphy = &(rtlpriv->phy);
831
832 if (regaddr == RTXAGC_A_RATE18_06) {
833 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0] = data;
834 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
835 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
836 rtlphy->pwrgroup_cnt,
837 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0]);
838 }
839 if (regaddr == RTXAGC_A_RATE54_24) {
840 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1] = data;
841 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
842 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
843 rtlphy->pwrgroup_cnt,
844 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1]);
845 }
846 if (regaddr == RTXAGC_A_CCK1_MCS32) {
847 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6] = data;
848 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
849 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
850 rtlphy->pwrgroup_cnt,
851 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6]);
852 }
853 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
854 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7] = data;
855 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
856 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
857 rtlphy->pwrgroup_cnt,
858 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7]);
859 }
860 if (regaddr == RTXAGC_A_MCS03_MCS00) {
861 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2] = data;
862 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
863 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
864 rtlphy->pwrgroup_cnt,
865 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2]);
866 }
867 if (regaddr == RTXAGC_A_MCS07_MCS04) {
868 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3] = data;
869 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
870 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
871 rtlphy->pwrgroup_cnt,
872 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3]);
873 }
874 if (regaddr == RTXAGC_A_MCS11_MCS08) {
875 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4] = data;
876 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
877 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
878 rtlphy->pwrgroup_cnt,
879 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4]);
880 }
881 if (regaddr == RTXAGC_A_MCS15_MCS12) {
882 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5] = data;
883 if (get_rf_type(rtlphy) == RF_1T1R)
884 rtlphy->pwrgroup_cnt++;
885 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
886 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
887 rtlphy->pwrgroup_cnt,
888 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5]);
889 }
890 if (regaddr == RTXAGC_B_RATE18_06) {
891 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8] = data;
892 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
893 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
894 rtlphy->pwrgroup_cnt,
895 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8]);
896 }
897 if (regaddr == RTXAGC_B_RATE54_24) {
898 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9] = data;
899 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
900 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
901 rtlphy->pwrgroup_cnt,
902 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9]);
903 }
904 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
905 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14] = data;
906 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
907 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
908 rtlphy->pwrgroup_cnt,
909 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14]);
910 }
911 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
912 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15] = data;
913 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
914 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
915 rtlphy->pwrgroup_cnt,
916 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15]);
917 }
918 if (regaddr == RTXAGC_B_MCS03_MCS00) {
919 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10] = data;
920 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
921 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
922 rtlphy->pwrgroup_cnt,
923 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10]);
924 }
925 if (regaddr == RTXAGC_B_MCS07_MCS04) {
926 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11] = data;
927 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
928 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
929 rtlphy->pwrgroup_cnt,
930 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11]);
931 }
932 if (regaddr == RTXAGC_B_MCS11_MCS08) {
933 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12] = data;
934 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
935 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
936 rtlphy->pwrgroup_cnt,
937 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12]);
938 }
939 if (regaddr == RTXAGC_B_MCS15_MCS12) {
940 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13] = data;
941 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
942 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
943 rtlphy->pwrgroup_cnt,
944 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13]);
945 if (get_rf_type(rtlphy) != RF_1T1R)
946 rtlphy->pwrgroup_cnt++;
947 }
948}
949
950#define READ_NEXT_RF_PAIR(v1, v2, i) \
951 do { \
952 i += 2; v1 = a_table[i]; \
953 v2 = a_table[i + 1]; \
954 } while (0)
955
956bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
957 enum radio_path rfpath)
958{
959 int i;
960 u32 *a_table;
961 u16 a_len;
962 struct rtl_priv *rtlpriv = rtl_priv(hw);
963 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
964 u32 v1 = 0, v2 = 0;
965
966 a_len = RTL8188EE_RADIOA_1TARRAYLEN;
967 a_table = RTL8188EE_RADIOA_1TARRAY;
968 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
969 "Radio_A:RTL8188EE_RADIOA_1TARRAY %d\n", a_len);
970 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
971 switch (rfpath) {
972 case RF90_PATH_A:
973 for (i = 0; i < a_len; i = i + 2) {
974 v1 = a_table[i];
975 v2 = a_table[i + 1];
976 if (v1 < 0xcdcdcdcd) {
977 rtl88_config_s(hw, v1, v2);
978 } else {/*This line is the start line of branch.*/
979 if (!check_cond(hw, a_table[i])) {
980 /* Discard the following (offset, data)
981 * pairs
982 */
983 READ_NEXT_RF_PAIR(v1, v2, i);
984 while (v2 != 0xDEAD && v2 != 0xCDEF &&
985 v2 != 0xCDCD && i < a_len - 2)
986 READ_NEXT_RF_PAIR(v1, v2, i);
987 i -= 2; /* prevent from for-loop += 2*/
988 } else {
989 /* Configure matched pairs and skip to
990 * end of if-else.
991 */
992 READ_NEXT_RF_PAIR(v1, v2, i);
993 while (v2 != 0xDEAD && v2 != 0xCDEF &&
994 v2 != 0xCDCD && i < a_len - 2) {
995 rtl88_config_s(hw, v1, v2);
996 READ_NEXT_RF_PAIR(v1, v2, i);
997 }
998
999 while (v2 != 0xDEAD && i < a_len - 2)
1000 READ_NEXT_RF_PAIR(v1, v2, i);
1001 }
1002 }
1003 }
1004
1005 if (rtlhal->oem_id == RT_CID_819x_HP)
1006 rtl88_config_s(hw, 0x52, 0x7E4BD);
1007
1008 break;
1009
1010 case RF90_PATH_B:
1011 case RF90_PATH_C:
1012 case RF90_PATH_D:
1013 default:
1014 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1015 "switch case not processed\n");
1016 break;
1017 }
1018 return true;
1019}
1020
1021void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1022{
1023 struct rtl_priv *rtlpriv = rtl_priv(hw);
1024 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1025
1026 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1,
1027 MASKBYTE0);
1028 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1,
1029 MASKBYTE0);
1030 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1,
1031 MASKBYTE0);
1032 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1,
1033 MASKBYTE0);
1034
1035 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1036 "Default initial gain (c50 = 0x%x, c58 = 0x%x, c60 = 0x%x, c68 = 0x%x\n",
1037 rtlphy->default_initialgain[0],
1038 rtlphy->default_initialgain[1],
1039 rtlphy->default_initialgain[2],
1040 rtlphy->default_initialgain[3]);
1041
1042 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
1043 MASKBYTE0);
1044 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1045 MASKDWORD);
1046
1047 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1048 "Default framesync (0x%x) = 0x%x\n",
1049 ROFDM0_RXDETECTOR3, rtlphy->framesync);
1050}
1051
1052void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
1053{
1054 struct rtl_priv *rtlpriv = rtl_priv(hw);
1055 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1056 u8 level;
1057 long dbm;
1058
1059 level = rtlphy->cur_cck_txpwridx;
1060 dbm = rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_B, level);
1061 level = rtlphy->cur_ofdm24g_txpwridx;
1062 if (rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_G, level) > dbm)
1063 dbm = rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_G, level);
1064 level = rtlphy->cur_ofdm24g_txpwridx;
1065 if (rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_N_24G, level) > dbm)
1066 dbm = rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_N_24G, level);
1067 *powerlevel = dbm;
1068}
1069
1070static void _rtl88e_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1071 u8 *cckpower, u8 *ofdm, u8 *bw20_pwr,
1072 u8 *bw40_pwr)
1073{
1074 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw));
1075 u8 i = (channel - 1);
1076 u8 rf_path = 0;
1077 int jj = RF90_PATH_A;
1078 int kk = RF90_PATH_B;
1079
1080 for (rf_path = 0; rf_path < 2; rf_path++) {
1081 if (rf_path == jj) {
1082 cckpower[jj] = fuse->txpwrlevel_cck[jj][i];
1083 if (fuse->txpwr_ht20diff[jj][i] > 0x0f) /*-8~7 */
1084 bw20_pwr[jj] = fuse->txpwrlevel_ht40_1s[jj][i] -
1085 (~(fuse->txpwr_ht20diff[jj][i]) + 1);
1086 else
1087 bw20_pwr[jj] = fuse->txpwrlevel_ht40_1s[jj][i] +
1088 fuse->txpwr_ht20diff[jj][i];
1089 if (fuse->txpwr_legacyhtdiff[jj][i] > 0xf)
1090 ofdm[jj] = fuse->txpwrlevel_ht40_1s[jj][i] -
1091 (~(fuse->txpwr_legacyhtdiff[jj][i])+1);
1092 else
1093 ofdm[jj] = fuse->txpwrlevel_ht40_1s[jj][i] +
1094 fuse->txpwr_legacyhtdiff[jj][i];
1095 bw40_pwr[jj] = fuse->txpwrlevel_ht40_1s[jj][i];
1096
1097 } else if (rf_path == kk) {
1098 cckpower[kk] = fuse->txpwrlevel_cck[kk][i];
1099 bw20_pwr[kk] = fuse->txpwrlevel_ht40_1s[kk][i] +
1100 fuse->txpwr_ht20diff[kk][i];
1101 ofdm[kk] = fuse->txpwrlevel_ht40_1s[kk][i] +
1102 fuse->txpwr_legacyhtdiff[kk][i];
1103 bw40_pwr[kk] = fuse->txpwrlevel_ht40_1s[kk][i];
1104 }
1105 }
1106}
1107
1108static void _rtl88e_ccxpower_index_check(struct ieee80211_hw *hw,
1109 u8 channel, u8 *cckpower,
1110 u8 *ofdm, u8 *bw20_pwr,
1111 u8 *bw40_pwr)
1112{
1113 struct rtl_priv *rtlpriv = rtl_priv(hw);
1114 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1115
1116 rtlphy->cur_cck_txpwridx = cckpower[0];
1117 rtlphy->cur_ofdm24g_txpwridx = ofdm[0];
1118 rtlphy->cur_bw20_txpwridx = bw20_pwr[0];
1119 rtlphy->cur_bw40_txpwridx = bw40_pwr[0];
1120}
1121
1122void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1123{
1124 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw));
1125 u8 cckpower[MAX_TX_COUNT] = {0}, ofdm[MAX_TX_COUNT] = {0};
1126 u8 bw20_pwr[MAX_TX_COUNT] = {0}, bw40_pwr[MAX_TX_COUNT] = {0};
1127
1128 if (fuse->txpwr_fromeprom == false)
1129 return;
1130 _rtl88e_get_txpower_index(hw, channel, &cckpower[0], &ofdm[0],
1131 &bw20_pwr[0], &bw40_pwr[0]);
1132 _rtl88e_ccxpower_index_check(hw, channel, &cckpower[0], &ofdm[0],
1133 &bw20_pwr[0], &bw40_pwr[0]);
1134 rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpower[0]);
1135 rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdm[0], &bw20_pwr[0],
1136 &bw40_pwr[0], channel);
1137}
1138
1139void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1140{
1141 struct rtl_priv *rtlpriv = rtl_priv(hw);
1142 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1143 enum io_type iotype;
1144
1145 if (!is_hal_stop(rtlhal)) {
1146 switch (operation) {
1147 case SCAN_OPT_BACKUP:
1148 iotype = IO_CMD_PAUSE_DM_BY_SCAN;
1149 rtlpriv->cfg->ops->set_hw_reg(hw,
1150 HW_VAR_IO_CMD,
1151 (u8 *)&iotype);
1152 break;
1153 case SCAN_OPT_RESTORE:
1154 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1155 rtlpriv->cfg->ops->set_hw_reg(hw,
1156 HW_VAR_IO_CMD,
1157 (u8 *)&iotype);
1158 break;
1159 default:
1160 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1161 "Unknown Scan Backup operation.\n");
1162 break;
1163 }
1164 }
1165}
1166
1167void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1168{
1169 struct rtl_priv *rtlpriv = rtl_priv(hw);
1170 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1171 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1172 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1173 u8 reg_bw_opmode;
1174 u8 reg_prsr_rsc;
1175
1176 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1177 "Switch to %s bandwidth\n",
1178 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1179 "20MHz" : "40MHz");
1180
1181 if (is_hal_stop(rtlhal)) {
1182 rtlphy->set_bwmode_inprogress = false;
1183 return;
1184 }
1185
1186 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1187 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1188
1189 switch (rtlphy->current_chan_bw) {
1190 case HT_CHANNEL_WIDTH_20:
1191 reg_bw_opmode |= BW_OPMODE_20MHZ;
1192 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1193 break;
1194 case HT_CHANNEL_WIDTH_20_40:
1195 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1196 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1197 reg_prsr_rsc =
1198 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
1199 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1200 break;
1201 default:
1202 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1203 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1204 break;
1205 }
1206
1207 switch (rtlphy->current_chan_bw) {
1208 case HT_CHANNEL_WIDTH_20:
1209 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1210 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1211 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/
1212 break;
1213 case HT_CHANNEL_WIDTH_20_40:
1214 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1215 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1216
1217 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1218 (mac->cur_40_prime_sc >> 1));
1219 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1220 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/
1221
1222 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1223 (mac->cur_40_prime_sc ==
1224 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1225 break;
1226 default:
1227 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1228 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1229 break;
1230 }
1231 rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1232 rtlphy->set_bwmode_inprogress = false;
1233 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
1234}
1235
1236void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
1237 enum nl80211_channel_type ch_type)
1238{
1239 struct rtl_priv *rtlpriv = rtl_priv(hw);
1240 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1241 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1242 u8 tmp_bw = rtlphy->current_chan_bw;
1243
1244 if (rtlphy->set_bwmode_inprogress)
1245 return;
1246 rtlphy->set_bwmode_inprogress = true;
1247 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1248 rtl88e_phy_set_bw_mode_callback(hw);
1249 } else {
1250 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1251 "FALSE driver sleep or unload\n");
1252 rtlphy->set_bwmode_inprogress = false;
1253 rtlphy->current_chan_bw = tmp_bw;
1254 }
1255}
1256
1257void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1258{
1259 struct rtl_priv *rtlpriv = rtl_priv(hw);
1260 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1261 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1262 u32 delay;
1263
1264 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1265 "switch to channel%d\n", rtlphy->current_channel);
1266 if (is_hal_stop(rtlhal))
1267 return;
1268 do {
1269 if (!rtlphy->sw_chnl_inprogress)
1270 break;
1271 if (!chnl_step_by_step(hw, rtlphy->current_channel,
1272 &rtlphy->sw_chnl_stage,
1273 &rtlphy->sw_chnl_step, &delay)) {
1274 if (delay > 0)
1275 mdelay(delay);
1276 else
1277 continue;
1278 } else {
1279 rtlphy->sw_chnl_inprogress = false;
1280 }
1281 break;
1282 } while (true);
1283 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
1284}
1285
1286u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw)
1287{
1288 struct rtl_priv *rtlpriv = rtl_priv(hw);
1289 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1290 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1291
1292 if (rtlphy->sw_chnl_inprogress)
1293 return 0;
1294 if (rtlphy->set_bwmode_inprogress)
1295 return 0;
1296 RT_ASSERT((rtlphy->current_channel <= 14),
1297 "WIRELESS_MODE_G but channel>14");
1298 rtlphy->sw_chnl_inprogress = true;
1299 rtlphy->sw_chnl_stage = 0;
1300 rtlphy->sw_chnl_step = 0;
1301 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1302 rtl88e_phy_sw_chnl_callback(hw);
1303 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1304 "sw_chnl_inprogress false schdule workitem current channel %d\n",
1305 rtlphy->current_channel);
1306 rtlphy->sw_chnl_inprogress = false;
1307 } else {
1308 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1309 "sw_chnl_inprogress false driver sleep or unload\n");
1310 rtlphy->sw_chnl_inprogress = false;
1311 }
1312 return 1;
1313}
1314
1315static u8 _rtl88e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1316{
1317 u32 reg_eac, reg_e94, reg_e9c;
1318 u8 result = 0x00;
1319
1320 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c);
1321 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c);
1322 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a);
1323 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000);
1324
1325 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1326 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1327 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1328
1329 mdelay(IQK_DELAY_TIME);
1330
1331 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1332 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1333 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1334
1335 if (!(reg_eac & BIT(28)) &&
1336 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1337 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1338 result |= 0x01;
1339 return result;
1340}
1341
1342static u8 _rtl88e_phy_path_b_iqk(struct ieee80211_hw *hw)
1343{
1344 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1345 u8 result = 0x00;
1346
1347 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1348 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1349 mdelay(IQK_DELAY_TIME);
1350 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1351 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1352 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1353 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1354 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1355
1356 if (!(reg_eac & BIT(31)) &&
1357 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1358 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1359 result |= 0x01;
1360 else
1361 return result;
1362 if (!(reg_eac & BIT(30)) &&
1363 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1364 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1365 result |= 0x02;
1366 return result;
1367}
1368
1369static u8 _rtl88e_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
1370{
1371 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u32temp;
1372 u8 result = 0x00;
1373 int jj = RF90_PATH_A;
1374
1375 /*Get TXIMR Setting*/
1376 /*Modify RX IQK mode table*/
1377 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1378 rtl_set_rfreg(hw, jj, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1379 rtl_set_rfreg(hw, jj, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1380 rtl_set_rfreg(hw, jj, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1381 rtl_set_rfreg(hw, jj, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
1382 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1383
1384 /*IQK Setting*/
1385 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1386 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800);
1387
1388 /*path a IQK setting*/
1389 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1390 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1391 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804);
1392 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);
1393
1394 /*LO calibration Setting*/
1395 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1396 /*one shot, path A LOK & iqk*/
1397 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1398 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1399
1400 mdelay(IQK_DELAY_TIME);
1401
1402 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1403 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1404 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1405
1406
1407 if (!(reg_eac & BIT(28)) &&
1408 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1409 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1410 result |= 0x01;
1411 else
1412 return result;
1413
1414 u32temp = 0x80007C00 | (reg_e94&0x3FF0000) |
1415 ((reg_e9c&0x3FF0000) >> 16);
1416 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
1417 /*RX IQK*/
1418 /*Modify RX IQK mode table*/
1419 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1420 rtl_set_rfreg(hw, jj, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1421 rtl_set_rfreg(hw, jj, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1422 rtl_set_rfreg(hw, jj, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1423 rtl_set_rfreg(hw, jj, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
1424 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1425
1426 /*IQK Setting*/
1427 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1428
1429 /*path a IQK setting*/
1430 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1431 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1432 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05);
1433 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05);
1434
1435 /*LO calibration Setting*/
1436 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1437 /*one shot, path A LOK & iqk*/
1438 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1439 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1440
1441 mdelay(IQK_DELAY_TIME);
1442
1443 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1444 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1445 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1446 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1447
1448 if (!(reg_eac & BIT(27)) &&
1449 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1450 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1451 result |= 0x02;
1452 return result;
1453}
1454
1455static void fill_iqk(struct ieee80211_hw *hw, bool iqk_ok, long result[][8],
1456 u8 final, bool btxonly)
1457{
1458 u32 oldval_0, x, tx0_a, reg;
1459 long y, tx0_c;
1460
1461 if (final == 0xFF) {
1462 return;
1463 } else if (iqk_ok) {
1464 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBAL,
1465 MASKDWORD) >> 22) & 0x3FF;
1466 x = result[final][0];
1467 if ((x & 0x00000200) != 0)
1468 x = x | 0xFFFFFC00;
1469 tx0_a = (x * oldval_0) >> 8;
1470 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBAL, 0x3FF, tx0_a);
1471 rtl_set_bbreg(hw, ROFDM0_ECCATHRES, BIT(31),
1472 ((x * oldval_0 >> 7) & 0x1));
1473 y = result[final][1];
1474 if ((y & 0x00000200) != 0)
1475 y |= 0xFFFFFC00;
1476 tx0_c = (y * oldval_0) >> 8;
1477 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1478 ((tx0_c & 0x3C0) >> 6));
1479 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBAL, 0x003F0000,
1480 (tx0_c & 0x3F));
1481 rtl_set_bbreg(hw, ROFDM0_ECCATHRES, BIT(29),
1482 ((y * oldval_0 >> 7) & 0x1));
1483 if (btxonly)
1484 return;
1485 reg = result[final][2];
1486 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBAL, 0x3FF, reg);
1487 reg = result[final][3] & 0x3F;
1488 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBAL, 0xFC00, reg);
1489 reg = (result[final][3] >> 6) & 0xF;
1490 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1491 }
1492}
1493
1494static void save_adda_reg(struct ieee80211_hw *hw,
1495 const u32 *addareg, u32 *backup,
1496 u32 registernum)
1497{
1498 u32 i;
1499
1500 for (i = 0; i < registernum; i++)
1501 backup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1502}
1503
1504static void save_mac_reg(struct ieee80211_hw *hw, const u32 *macreg,
1505 u32 *macbackup)
1506{
1507 struct rtl_priv *rtlpriv = rtl_priv(hw);
1508 u32 i;
1509
1510 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1511 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1512 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1513}
1514
1515static void reload_adda(struct ieee80211_hw *hw, const u32 *addareg,
1516 u32 *backup, u32 reg_num)
1517{
1518 u32 i;
1519
1520 for (i = 0; i < reg_num; i++)
1521 rtl_set_bbreg(hw, addareg[i], MASKDWORD, backup[i]);
1522}
1523
1524static void reload_mac(struct ieee80211_hw *hw, const u32 *macreg,
1525 u32 *macbackup)
1526{
1527 struct rtl_priv *rtlpriv = rtl_priv(hw);
1528 u32 i;
1529
1530 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1531 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1532 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1533}
1534
1535static void _rtl88e_phy_path_adda_on(struct ieee80211_hw *hw,
1536 const u32 *addareg, bool is_patha_on,
1537 bool is2t)
1538{
1539 u32 pathon;
1540 u32 i;
1541
1542 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1543 if (false == is2t) {
1544 pathon = 0x0bdb25a0;
1545 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1546 } else {
1547 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
1548 }
1549
1550 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1551 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
1552}
1553
1554static void _rtl88e_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1555 const u32 *macreg,
1556 u32 *macbackup)
1557{
1558 struct rtl_priv *rtlpriv = rtl_priv(hw);
1559 u32 i = 0;
1560
1561 rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1562
1563 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1564 rtl_write_byte(rtlpriv, macreg[i],
1565 (u8) (macbackup[i] & (~BIT(3))));
1566 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1567}
1568
1569static void _rtl88e_phy_path_a_standby(struct ieee80211_hw *hw)
1570{
1571 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1572 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1573 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1574}
1575
1576static void _rtl88e_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1577{
1578 u32 mode;
1579
1580 mode = pi_mode ? 0x01000100 : 0x01000000;
1581 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1582 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1583}
1584
1585static bool sim_comp(struct ieee80211_hw *hw, long result[][8], u8 c1, u8 c2)
1586{
1587 u32 i, j, diff, bitmap, bound;
1588 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1589
1590 u8 final[2] = {0xFF, 0xFF};
1591 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1592
1593 if (is2t)
1594 bound = 8;
1595 else
1596 bound = 4;
1597
1598 bitmap = 0;
1599
1600 for (i = 0; i < bound; i++) {
1601 diff = (result[c1][i] > result[c2][i]) ?
1602 (result[c1][i] - result[c2][i]) :
1603 (result[c2][i] - result[c1][i]);
1604
1605 if (diff > MAX_TOLERANCE) {
1606 if ((i == 2 || i == 6) && !bitmap) {
1607 if (result[c1][i] + result[c1][i + 1] == 0)
1608 final[(i / 4)] = c2;
1609 else if (result[c2][i] + result[c2][i + 1] == 0)
1610 final[(i / 4)] = c1;
1611 else
1612 bitmap = bitmap | (1 << i);
1613 } else {
1614 bitmap = bitmap | (1 << i);
1615 }
1616 }
1617 }
1618
1619 if (bitmap == 0) {
1620 for (i = 0; i < (bound / 4); i++) {
1621 if (final[i] != 0xFF) {
1622 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1623 result[3][j] = result[final[i]][j];
1624 bresult = false;
1625 }
1626 }
1627 return bresult;
1628 } else if (!(bitmap & 0x0F)) {
1629 for (i = 0; i < 4; i++)
1630 result[3][i] = result[c1][i];
1631 return false;
1632 } else if (!(bitmap & 0xF0) && is2t) {
1633 for (i = 4; i < 8; i++)
1634 result[3][i] = result[c1][i];
1635 return false;
1636 } else {
1637 return false;
1638 }
1639}
1640
1641static void _rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw,
1642 long result[][8], u8 t, bool is2t)
1643{
1644 struct rtl_priv *rtlpriv = rtl_priv(hw);
1645 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1646 u32 i;
1647 u8 patha_ok, pathb_ok;
1648 const u32 adda_reg[IQK_ADDA_REG_NUM] = {
1649 0x85c, 0xe6c, 0xe70, 0xe74,
1650 0xe78, 0xe7c, 0xe80, 0xe84,
1651 0xe88, 0xe8c, 0xed0, 0xed4,
1652 0xed8, 0xedc, 0xee0, 0xeec
1653 };
1654 const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1655 0x522, 0x550, 0x551, 0x040
1656 };
1657 const u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1658 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR, RFPGA0_XCD_RFINTERFACESW,
1659 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0x800
1660 };
1661 const u32 retrycount = 2;
1662
1663 if (t == 0) {
1664 save_adda_reg(hw, adda_reg, rtlphy->adda_backup, 16);
1665 save_mac_reg(hw, iqk_mac_reg, rtlphy->iqk_mac_backup);
1666 save_adda_reg(hw, iqk_bb_reg, rtlphy->iqk_bb_backup,
1667 IQK_BB_REG_NUM);
1668 }
1669 _rtl88e_phy_path_adda_on(hw, adda_reg, true, is2t);
1670 if (t == 0) {
1671 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1672 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1673 }
1674
1675 if (!rtlphy->rfpi_enable)
1676 _rtl88e_phy_pi_mode_switch(hw, true);
1677 /*BB Setting*/
1678 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00);
1679 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1680 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1681 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1682
1683 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01);
1684 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01);
1685 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00);
1686 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00);
1687
1688 if (is2t) {
1689 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1690 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1691 }
1692 _rtl88e_phy_mac_setting_calibration(hw, iqk_mac_reg,
1693 rtlphy->iqk_mac_backup);
1694 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1695 if (is2t)
1696 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1697
1698 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1699 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1700 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800);
1701 for (i = 0; i < retrycount; i++) {
1702 patha_ok = _rtl88e_phy_path_a_iqk(hw, is2t);
1703 if (patha_ok == 0x01) {
1704 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1705 "Path A Tx IQK Success!!\n");
1706 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1707 0x3FF0000) >> 16;
1708 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1709 0x3FF0000) >> 16;
1710 break;
1711 }
1712 }
1713
1714 for (i = 0; i < retrycount; i++) {
1715 patha_ok = _rtl88e_phy_path_a_rx_iqk(hw, is2t);
1716 if (patha_ok == 0x03) {
1717 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1718 "Path A Rx IQK Success!!\n");
1719 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1720 0x3FF0000) >> 16;
1721 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1722 0x3FF0000) >> 16;
1723 break;
1724 } else {
1725 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1726 "Path a RX iqk fail!!!\n");
1727 }
1728 }
1729
1730 if (0 == patha_ok) {
1731 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1732 "Path A IQK Success!!\n");
1733 }
1734 if (is2t) {
1735 _rtl88e_phy_path_a_standby(hw);
1736 _rtl88e_phy_path_adda_on(hw, adda_reg, false, is2t);
1737 for (i = 0; i < retrycount; i++) {
1738 pathb_ok = _rtl88e_phy_path_b_iqk(hw);
1739 if (pathb_ok == 0x03) {
1740 result[t][4] = (rtl_get_bbreg(hw,
1741 0xeb4, MASKDWORD) &
1742 0x3FF0000) >> 16;
1743 result[t][5] =
1744 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1745 0x3FF0000) >> 16;
1746 result[t][6] =
1747 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1748 0x3FF0000) >> 16;
1749 result[t][7] =
1750 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1751 0x3FF0000) >> 16;
1752 break;
1753 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1754 result[t][4] = (rtl_get_bbreg(hw,
1755 0xeb4, MASKDWORD) &
1756 0x3FF0000) >> 16;
1757 }
1758 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1759 0x3FF0000) >> 16;
1760 }
1761 }
1762
1763 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1764
1765 if (t != 0) {
1766 if (!rtlphy->rfpi_enable)
1767 _rtl88e_phy_pi_mode_switch(hw, false);
1768 reload_adda(hw, adda_reg, rtlphy->adda_backup, 16);
1769 reload_mac(hw, iqk_mac_reg, rtlphy->iqk_mac_backup);
1770 reload_adda(hw, iqk_bb_reg, rtlphy->iqk_bb_backup,
1771 IQK_BB_REG_NUM);
1772
1773 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1774 if (is2t)
1775 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1776 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1777 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1778 }
1779 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "88ee IQK Finish!!\n");
1780}
1781
1782static void _rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1783{
1784 u8 tmpreg;
1785 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1786 struct rtl_priv *rtlpriv = rtl_priv(hw);
1787 int jj = RF90_PATH_A;
1788 int kk = RF90_PATH_B;
1789
1790 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1791
1792 if ((tmpreg & 0x70) != 0)
1793 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
1794 else
1795 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1796
1797 if ((tmpreg & 0x70) != 0) {
1798 rf_a_mode = rtl_get_rfreg(hw, jj, 0x00, MASK12BITS);
1799
1800 if (is2t)
1801 rf_b_mode = rtl_get_rfreg(hw, kk, 0x00,
1802 MASK12BITS);
1803
1804 rtl_set_rfreg(hw, jj, 0x00, MASK12BITS,
1805 (rf_a_mode & 0x8FFFF) | 0x10000);
1806
1807 if (is2t)
1808 rtl_set_rfreg(hw, kk, 0x00, MASK12BITS,
1809 (rf_b_mode & 0x8FFFF) | 0x10000);
1810 }
1811 lc_cal = rtl_get_rfreg(hw, jj, 0x18, MASK12BITS);
1812
1813 rtl_set_rfreg(hw, jj, 0x18, MASK12BITS, lc_cal | 0x08000);
1814
1815 mdelay(100);
1816
1817 if ((tmpreg & 0x70) != 0) {
1818 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
1819 rtl_set_rfreg(hw, jj, 0x00, MASK12BITS, rf_a_mode);
1820
1821 if (is2t)
1822 rtl_set_rfreg(hw, kk, 0x00, MASK12BITS,
1823 rf_b_mode);
1824 } else {
1825 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1826 }
1827 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1828}
1829
1830static void rfpath_switch(struct ieee80211_hw *hw,
1831 bool bmain, bool is2t)
1832{
1833 struct rtl_priv *rtlpriv = rtl_priv(hw);
1834 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1835 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw));
1836 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1837
1838 if (is_hal_stop(rtlhal)) {
1839 u8 u1btmp;
1840 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0);
1841 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7));
1842 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1843 }
1844 if (is2t) {
1845 if (bmain)
1846 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1847 BIT(5) | BIT(6), 0x1);
1848 else
1849 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1850 BIT(5) | BIT(6), 0x2);
1851 } else {
1852 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
1853 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
1854
1855 /* We use the RF definition of MAIN and AUX, left antenna and
1856 * right antenna repectively.
1857 * Default output at AUX.
1858 */
1859 if (bmain) {
1860 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(14) |
1861 BIT(13) | BIT(12), 0);
1862 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(5) |
1863 BIT(4) | BIT(3), 0);
1864 if (fuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1865 rtl_set_bbreg(hw, RCONFIG_RAM64X16, BIT(31), 0);
1866 } else {
1867 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(14) |
1868 BIT(13) | BIT(12), 1);
1869 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(5) |
1870 BIT(4) | BIT(3), 1);
1871 if (fuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1872 rtl_set_bbreg(hw, RCONFIG_RAM64X16, BIT(31), 1);
1873 }
1874 }
1875}
1876
1877#undef IQK_ADDA_REG_NUM
1878#undef IQK_DELAY_TIME
1879
1880void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1881{
1882 struct rtl_priv *rtlpriv = rtl_priv(hw);
1883 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1884 long result[4][8];
1885 u8 i, final;
1886 bool patha_ok;
1887 long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_tmp = 0;
1888 bool is12simular, is13simular, is23simular;
1889 u32 iqk_bb_reg[9] = {
1890 ROFDM0_XARXIQIMBAL,
1891 ROFDM0_XBRXIQIMBAL,
1892 ROFDM0_ECCATHRES,
1893 ROFDM0_AGCRSSITABLE,
1894 ROFDM0_XATXIQIMBAL,
1895 ROFDM0_XBTXIQIMBAL,
1896 ROFDM0_XCTXAFE,
1897 ROFDM0_XDTXAFE,
1898 ROFDM0_RXIQEXTANTA
1899 };
1900
1901 if (recovery) {
1902 reload_adda(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 9);
1903 return;
1904 }
1905
1906 memset(result, 0, 32 * sizeof(long));
1907 final = 0xff;
1908 patha_ok = false;
1909 is12simular = false;
1910 is23simular = false;
1911 is13simular = false;
1912 for (i = 0; i < 3; i++) {
1913 if (get_rf_type(rtlphy) == RF_2T2R)
1914 _rtl88e_phy_iq_calibrate(hw, result, i, true);
1915 else
1916 _rtl88e_phy_iq_calibrate(hw, result, i, false);
1917 if (i == 1) {
1918 is12simular = sim_comp(hw, result, 0, 1);
1919 if (is12simular) {
1920 final = 0;
1921 break;
1922 }
1923 }
1924 if (i == 2) {
1925 is13simular = sim_comp(hw, result, 0, 2);
1926 if (is13simular) {
1927 final = 0;
1928 break;
1929 }
1930 is23simular = sim_comp(hw, result, 1, 2);
1931 if (is23simular) {
1932 final = 1;
1933 } else {
1934 for (i = 0; i < 8; i++)
1935 reg_tmp += result[3][i];
1936
1937 if (reg_tmp != 0)
1938 final = 3;
1939 else
1940 final = 0xFF;
1941 }
1942 }
1943 }
1944 for (i = 0; i < 4; i++) {
1945 reg_e94 = result[i][0];
1946 reg_e9c = result[i][1];
1947 reg_ea4 = result[i][2];
1948 reg_eb4 = result[i][4];
1949 reg_ebc = result[i][5];
1950 }
1951 if (final != 0xff) {
1952 reg_e94 = result[final][0];
1953 rtlphy->reg_e94 = reg_e94;
1954 reg_e9c = result[final][1];
1955 rtlphy->reg_e9c = reg_e9c;
1956 reg_ea4 = result[final][2];
1957 reg_eb4 = result[final][4];
1958 rtlphy->reg_eb4 = reg_eb4;
1959 reg_ebc = result[final][5];
1960 rtlphy->reg_ebc = reg_ebc;
1961 patha_ok = true;
1962 } else {
1963 rtlphy->reg_e94 = 0x100;
1964 rtlphy->reg_eb4 = 0x100;
1965 rtlphy->reg_ebc = 0x0;
1966 rtlphy->reg_e9c = 0x0;
1967 }
1968 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1969 fill_iqk(hw, patha_ok, result, final, (reg_ea4 == 0));
1970 if (final != 0xFF) {
1971 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
1972 rtlphy->iqk_matrix[0].value[0][i] = result[final][i];
1973 rtlphy->iqk_matrix[0].iqk_done = true;
1974 }
1975 save_adda_reg(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 9);
1976}
1977
1978void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw)
1979{
1980 struct rtl_priv *rtlpriv = rtl_priv(hw);
1981 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1982 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1983 bool start_conttx = false, singletone = false;
1984 u32 timeout = 2000, timecount = 0;
1985
1986 if (start_conttx || singletone)
1987 return;
1988
1989 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
1990 udelay(50);
1991 timecount += 50;
1992 }
1993
1994 rtlphy->lck_inprogress = true;
1995 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1996 "LCK:Start!!! currentband %x delay %d ms\n",
1997 rtlhal->current_bandtype, timecount);
1998
1999 _rtl88e_phy_lc_calibrate(hw, false);
2000
2001 rtlphy->lck_inprogress = false;
2002}
2003
2004void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2005{
2006 struct rtl_priv *rtlpriv = rtl_priv(hw);
2007 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2008
2009 if (rtlphy->apk_done)
2010 return;
2011 return;
2012}
2013
2014void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2015{
2016 rfpath_switch(hw, bmain, false);
2017}
2018
2019bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2020{
2021 struct rtl_priv *rtlpriv = rtl_priv(hw);
2022 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2023 bool postprocessing = false;
2024
2025 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2026 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2027 iotype, rtlphy->set_io_inprogress);
2028 do {
2029 switch (iotype) {
2030 case IO_CMD_RESUME_DM_BY_SCAN:
2031 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2032 "[IO CMD] Resume DM after scan.\n");
2033 postprocessing = true;
2034 break;
2035 case IO_CMD_PAUSE_DM_BY_SCAN:
2036 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2037 "[IO CMD] Pause DM before scan.\n");
2038 postprocessing = true;
2039 break;
2040 default:
2041 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2042 "switch case not processed\n");
2043 break;
2044 }
2045 } while (false);
2046 if (postprocessing && !rtlphy->set_io_inprogress) {
2047 rtlphy->set_io_inprogress = true;
2048 rtlphy->current_io_type = iotype;
2049 } else {
2050 return false;
2051 }
2052 rtl88e_phy_set_io(hw);
2053 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
2054 return true;
2055}
2056
2057static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw)
2058{
2059 struct rtl_priv *rtlpriv = rtl_priv(hw);
2060
2061 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2062 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2063 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/
2064 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2065 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2066 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2067}
2068
2069static void _rtl88ee_phy_set_rf_sleep(struct ieee80211_hw *hw)
2070{
2071 struct rtl_priv *rtlpriv = rtl_priv(hw);
2072 int jj = RF90_PATH_A;
2073
2074 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2075 rtl_set_rfreg(hw, jj, 0x00, RFREG_OFFSET_MASK, 0x00);
2076 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2077 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2078}
2079
2080static bool _rtl88ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
2081 enum rf_pwrstate rfpwr_state)
2082{
2083 struct rtl_priv *rtlpriv = rtl_priv(hw);
2084 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2085 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2086 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2087 struct rtl8192_tx_ring *ring = NULL;
2088 bool bresult = true;
2089 u8 i, queue_id;
2090
2091 switch (rfpwr_state) {
2092 case ERFON:{
2093 if ((ppsc->rfpwr_state == ERFOFF) &&
2094 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2095 bool rtstatus;
2096 u32 init = 0;
2097 do {
2098 init++;
2099 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2100 "IPS Set eRf nic enable\n");
2101 rtstatus = rtl_ps_enable_nic(hw);
2102 } while ((rtstatus != true) && (init < 10));
2103 RT_CLEAR_PS_LEVEL(ppsc,
2104 RT_RF_OFF_LEVL_HALT_NIC);
2105 } else {
2106 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2107 "Set ERFON sleeped:%d ms\n",
2108 jiffies_to_msecs(jiffies - ppsc->
2109 last_sleep_jiffies));
2110 ppsc->last_awake_jiffies = jiffies;
2111 rtl88ee_phy_set_rf_on(hw);
2112 }
2113 if (mac->link_state == MAC80211_LINKED)
2114 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK);
2115 else
2116 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
2117 break; }
2118 case ERFOFF:{
2119 for (queue_id = 0, i = 0;
2120 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2121 ring = &pcipriv->dev.tx_ring[queue_id];
2122 if (skb_queue_len(&ring->queue) == 0) {
2123 queue_id++;
2124 continue;
2125 } else {
2126 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2127 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2128 (i + 1), queue_id,
2129 skb_queue_len(&ring->queue));
2130
2131 udelay(10);
2132 i++;
2133 }
2134 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2135 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2136 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2137 MAX_DOZE_WAITING_TIMES_9x,
2138 queue_id,
2139 skb_queue_len(&ring->queue));
2140 break;
2141 }
2142 }
2143 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
2144 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2145 "IPS Set eRf nic disable\n");
2146 rtl_ps_disable_nic(hw);
2147 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2148 } else {
2149 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
2150 rtlpriv->cfg->ops->led_control(hw,
2151 LED_CTL_NO_LINK);
2152 } else {
2153 rtlpriv->cfg->ops->led_control(hw,
2154 LED_CTL_POWER_OFF);
2155 }
2156 }
2157 break; }
2158 case ERFSLEEP:{
2159 if (ppsc->rfpwr_state == ERFOFF)
2160 break;
2161 for (queue_id = 0, i = 0;
2162 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2163 ring = &pcipriv->dev.tx_ring[queue_id];
2164 if (skb_queue_len(&ring->queue) == 0) {
2165 queue_id++;
2166 continue;
2167 } else {
2168 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2169 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2170 (i + 1), queue_id,
2171 skb_queue_len(&ring->queue));
2172
2173 udelay(10);
2174 i++;
2175 }
2176 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2177 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2178 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2179 MAX_DOZE_WAITING_TIMES_9x,
2180 queue_id,
2181 skb_queue_len(&ring->queue));
2182 break;
2183 }
2184 }
2185 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2186 "Set ERFSLEEP awaked:%d ms\n",
2187 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
2188 ppsc->last_sleep_jiffies = jiffies;
2189 _rtl88ee_phy_set_rf_sleep(hw);
2190 break; }
2191 default:
2192 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2193 "switch case not processed\n");
2194 bresult = false;
2195 break;
2196 }
2197 if (bresult)
2198 ppsc->rfpwr_state = rfpwr_state;
2199 return bresult;
2200}
2201
2202bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
2203 enum rf_pwrstate rfpwr_state)
2204{
2205 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2206 bool bresult;
2207
2208 if (rfpwr_state == ppsc->rfpwr_state)
2209 return false;
2210 bresult = _rtl88ee_phy_set_rf_power_state(hw, rfpwr_state);
2211 return bresult;
2212}
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/phy.h b/drivers/net/wireless/rtlwifi/rtl8188ee/phy.h
new file mode 100644
index 000000000000..4f047c6ee096
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/phy.h
@@ -0,0 +1,237 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_PHY_H__
31#define __RTL92C_PHY_H__
32
33/*It must always set to 4, otherwise read efuse table secquence will be wrong.*/
34#define MAX_TX_COUNT 4
35
36#define MAX_PRECMD_CNT 16
37#define MAX_RFDEPENDCMD_CNT 16
38#define MAX_POSTCMD_CNT 16
39
40#define MAX_DOZE_WAITING_TIMES_9x 64
41
42#define RT_CANNOT_IO(hw) false
43#define HIGHPOWER_RADIOA_ARRAYLEN 22
44
45#define IQK_ADDA_REG_NUM 16
46#define IQK_BB_REG_NUM 9
47#define MAX_TOLERANCE 5
48#define IQK_DELAY_TIME 10
49#define IDX_MAP 15
50
51#define APK_BB_REG_NUM 5
52#define APK_AFE_REG_NUM 16
53#define APK_CURVE_REG_NUM 4
54#define PATH_NUM 2
55
56#define LOOP_LIMIT 5
57#define MAX_STALL_TIME 50
58#define ANTENNADIVERSITYVALUE 0x80
59#define MAX_TXPWR_IDX_NMODE_92S 63
60#define RESET_CNT_LIMIT 3
61
62#define IQK_ADDA_REG_NUM 16
63#define IQK_MAC_REG_NUM 4
64
65#define RF6052_MAX_PATH 2
66
67#define CT_OFFSET_MAC_ADDR 0X16
68
69#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
70#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
71#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
72#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
73#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
74
75#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
76#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
77
78#define CT_OFFSET_CHANNEL_PLAH 0x75
79#define CT_OFFSET_THERMAL_METER 0x78
80#define CT_OFFSET_RF_OPTION 0x79
81#define CT_OFFSET_VERSION 0x7E
82#define CT_OFFSET_CUSTOMER_ID 0x7F
83
84#define RTL92C_MAX_PATH_NUM 2
85
86enum swchnlcmd_id {
87 CMDID_END,
88 CMDID_SET_TXPOWEROWER_LEVEL,
89 CMDID_BBREGWRITE10,
90 CMDID_WRITEPORT_ULONG,
91 CMDID_WRITEPORT_USHORT,
92 CMDID_WRITEPORT_UCHAR,
93 CMDID_RF_WRITEREG,
94};
95
96struct swchnlcmd {
97 enum swchnlcmd_id cmdid;
98 u32 para1;
99 u32 para2;
100 u32 msdelay;
101};
102
103enum hw90_block_e {
104 HW90_BLOCK_MAC = 0,
105 HW90_BLOCK_PHY0 = 1,
106 HW90_BLOCK_PHY1 = 2,
107 HW90_BLOCK_RF = 3,
108 HW90_BLOCK_MAXIMUM = 4,
109};
110
111enum baseband_config_type {
112 BASEBAND_CONFIG_PHY_REG = 0,
113 BASEBAND_CONFIG_AGC_TAB = 1,
114};
115
116enum ra_offset_area {
117 RA_OFFSET_LEGACY_OFDM1,
118 RA_OFFSET_LEGACY_OFDM2,
119 RA_OFFSET_HT_OFDM1,
120 RA_OFFSET_HT_OFDM2,
121 RA_OFFSET_HT_OFDM3,
122 RA_OFFSET_HT_OFDM4,
123 RA_OFFSET_HT_CCK,
124};
125
126enum antenna_path {
127 ANTENNA_NONE,
128 ANTENNA_D,
129 ANTENNA_C,
130 ANTENNA_CD,
131 ANTENNA_B,
132 ANTENNA_BD,
133 ANTENNA_BC,
134 ANTENNA_BCD,
135 ANTENNA_A,
136 ANTENNA_AD,
137 ANTENNA_AC,
138 ANTENNA_ACD,
139 ANTENNA_AB,
140 ANTENNA_ABD,
141 ANTENNA_ABC,
142 ANTENNA_ABCD
143};
144
145struct r_antenna_select_ofdm {
146 u32 r_tx_antenna:4;
147 u32 r_ant_l:4;
148 u32 r_ant_non_ht:4;
149 u32 r_ant_ht1:4;
150 u32 r_ant_ht2:4;
151 u32 r_ant_ht_s1:4;
152 u32 r_ant_non_ht_s1:4;
153 u32 ofdm_txsc:2;
154 u32 reserved:2;
155};
156
157struct r_antenna_select_cck {
158 u8 r_cckrx_enable_2:2;
159 u8 r_cckrx_enable:2;
160 u8 r_ccktx_enable:4;
161};
162
163
164struct efuse_contents {
165 u8 mac_addr[ETH_ALEN];
166 u8 cck_tx_power_idx[6];
167 u8 ht40_1s_tx_power_idx[6];
168 u8 ht40_2s_tx_power_idx_diff[3];
169 u8 ht20_tx_power_idx_diff[3];
170 u8 ofdm_tx_power_idx_diff[3];
171 u8 ht40_max_power_offset[3];
172 u8 ht20_max_power_offset[3];
173 u8 channel_plan;
174 u8 thermal_meter;
175 u8 rf_option[5];
176 u8 version;
177 u8 oem_id;
178 u8 regulatory;
179};
180
181struct tx_power_struct {
182 u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
183 u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
184 u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
185 u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
186 u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
187 u8 legacy_ht_txpowerdiff;
188 u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
189 u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
190 u8 pwrgroup_cnt;
191 u32 mcs_original_offset[4][16];
192};
193
194enum _ANT_DIV_TYPE {
195 NO_ANTDIV = 0xFF,
196 CG_TRX_HW_ANTDIV = 0x01,
197 CGCS_RX_HW_ANTDIV = 0x02,
198 FIXED_HW_ANTDIV = 0x03,
199 CG_TRX_SMART_ANTDIV = 0x04,
200 CGCS_RX_SW_ANTDIV = 0x05,
201};
202
203extern u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw,
204 u32 regaddr, u32 bitmask);
205extern void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw,
206 u32 regaddr, u32 bitmask, u32 data);
207extern u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw,
208 enum radio_path rfpath, u32 regaddr,
209 u32 bitmask);
210extern void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw,
211 enum radio_path rfpath, u32 regaddr,
212 u32 bitmask, u32 data);
213extern bool rtl88e_phy_mac_config(struct ieee80211_hw *hw);
214extern bool rtl88e_phy_bb_config(struct ieee80211_hw *hw);
215extern bool rtl88e_phy_rf_config(struct ieee80211_hw *hw);
216extern void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
217extern void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw,
218 long *powerlevel);
219extern void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
220extern void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw,
221 u8 operation);
222extern void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
223extern void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
224 enum nl80211_channel_type ch_type);
225extern void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
226extern u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw);
227extern void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
228void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
229void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw);
230void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
231bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
232 enum radio_path rfpath);
233bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
234extern bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
235 enum rf_pwrstate rfpwr_state);
236
237#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.c b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.c
new file mode 100644
index 000000000000..6dc4e3a954f6
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.c
@@ -0,0 +1,109 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "pwrseqcmd.h"
31#include "pwrseq.h"
32
33/* drivers should parse below arrays and do the corresponding actions */
34/*3 Power on Array*/
35struct wlan_pwr_cfg rtl8188e_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS +
36 RTL8188E_TRANS_END_STEPS] = {
37 RTL8188E_TRANS_CARDEMU_TO_ACT
38 RTL8188E_TRANS_END
39};
40
41/*3Radio off GPIO Array */
42struct wlan_pwr_cfg rtl8188e_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
43 + RTL8188E_TRANS_END_STEPS] = {
44 RTL8188E_TRANS_ACT_TO_CARDEMU
45 RTL8188E_TRANS_END
46};
47
48/*3Card Disable Array*/
49struct wlan_pwr_cfg rtl8188e_card_disable_flow
50 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
51 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
52 RTL8188E_TRANS_END_STEPS] = {
53 RTL8188E_TRANS_ACT_TO_CARDEMU
54 RTL8188E_TRANS_CARDEMU_TO_CARDDIS
55 RTL8188E_TRANS_END
56};
57
58/*3 Card Enable Array*/
59struct wlan_pwr_cfg rtl8188e_card_enable_flow
60 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
61 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
62 RTL8188E_TRANS_END_STEPS] = {
63 RTL8188E_TRANS_CARDDIS_TO_CARDEMU
64 RTL8188E_TRANS_CARDEMU_TO_ACT
65 RTL8188E_TRANS_END
66};
67
68/*3Suspend Array*/
69struct wlan_pwr_cfg rtl8188e_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
70 + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS
71 + RTL8188E_TRANS_END_STEPS] = {
72 RTL8188E_TRANS_ACT_TO_CARDEMU
73 RTL8188E_TRANS_CARDEMU_TO_SUS
74 RTL8188E_TRANS_END
75};
76
77/*3 Resume Array*/
78struct wlan_pwr_cfg rtl8188e_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
79 + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS
80 + RTL8188E_TRANS_END_STEPS] = {
81 RTL8188E_TRANS_SUS_TO_CARDEMU
82 RTL8188E_TRANS_CARDEMU_TO_ACT
83 RTL8188E_TRANS_END
84};
85
86/*3HWPDN Array*/
87struct wlan_pwr_cfg rtl8188e_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
88 + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS
89 + RTL8188E_TRANS_END_STEPS] = {
90 RTL8188E_TRANS_ACT_TO_CARDEMU
91 RTL8188E_TRANS_CARDEMU_TO_PDN
92 RTL8188E_TRANS_END
93};
94
95/*3 Enter LPS */
96struct wlan_pwr_cfg rtl8188e_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS
97 + RTL8188E_TRANS_END_STEPS] = {
98 /*FW behavior*/
99 RTL8188E_TRANS_ACT_TO_LPS
100 RTL8188E_TRANS_END
101};
102
103/*3 Leave LPS */
104struct wlan_pwr_cfg rtl8188e_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS
105 + RTL8188E_TRANS_END_STEPS] = {
106 /*FW behavior*/
107 RTL8188E_TRANS_LPS_TO_ACT
108 RTL8188E_TRANS_END
109};
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h
new file mode 100644
index 000000000000..028ec6dd52b4
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h
@@ -0,0 +1,327 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8723E_PWRSEQ_H__
31#define __RTL8723E_PWRSEQ_H__
32
33#include "pwrseqcmd.h"
34/*
35 Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
36 There are 6 HW Power States:
37 0: POFF--Power Off
38 1: PDN--Power Down
39 2: CARDEMU--Card Emulation
40 3: ACT--Active Mode
41 4: LPS--Low Power State
42 5: SUS--Suspend
43
44 The transision from different states are defined below
45 TRANS_CARDEMU_TO_ACT
46 TRANS_ACT_TO_CARDEMU
47 TRANS_CARDEMU_TO_SUS
48 TRANS_SUS_TO_CARDEMU
49 TRANS_CARDEMU_TO_PDN
50 TRANS_ACT_TO_LPS
51 TRANS_LPS_TO_ACT
52
53 TRANS_END
54 PWR SEQ Version: rtl8188e_PwrSeq_V09.h
55*/
56
57#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
58#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
59#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
60#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
61#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
62#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
63#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
64#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
65#define RTL8188E_TRANS_END_STEPS 1
66
67
68#define RTL8188E_TRANS_CARDEMU_TO_ACT \
69 /* format */ \
70 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
71 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
72 /* wait till 0x04[17] = 1 power ready*/ \
73 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
74 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
75 /* 0x02[1:0] = 0 reset BB*/ \
76 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0}, \
77 {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
78 /*0x24[23] = 2b'01 schmit trigger */ \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
80 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
81 /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \
82 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
83 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
84 /*0x04[12:11] = 2b'00 disable WL suspend*/ \
85 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0}, \
86 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
87 /*0x04[8] = 1 polling until return 0*/ \
88 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
89 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
90 /*wait till 0x04[8] = 0*/ \
91 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
92 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*LDO normal mode*/\
94 {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO Driving*/\
96
97#define RTL8188E_TRANS_ACT_TO_CARDEMU \
98 /* format */ \
99 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
100 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
101 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/\
102 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
103 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*LDO Sleep mode*/\
104 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
105 /*0x04[9] = 1 turn off MAC by HW state machine*/ \
106 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
107 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
108 /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
109 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
110
111
112#define RTL8188E_TRANS_CARDEMU_TO_SUS \
113 /* format */ \
114 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
115 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
116 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
117 /*0x04[12:11] = 2b'01enable WL suspend*/ \
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
119 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
120 /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \
121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)},\
122 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
123 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
124 /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
125 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7)}, \
126 {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
127 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
128 /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
129 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
130 {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
131 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
132 /*Set USB suspend enable local register 0xfe10[4]= 1 */ \
133 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
134 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
135 /*Set SDIO suspend local register*/ \
136 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
137 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
138 /*wait power state to suspend*/ \
139 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
140
141#define RTL8188E_TRANS_SUS_TO_CARDEMU \
142 /* format */ \
143 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
144 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
145 /*Set SDIO suspend local register*/ \
146 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
147 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
148 /*wait power state to suspend*/ \
149 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
150 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
151 /*0x04[12:11] = 2b'01enable WL suspend*/ \
152 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
153
154#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
155 /* format */ \
156 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
157 {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
158 /*0x24[23] = 2b'01 schmit trigger */ \
159 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
160 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
161 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
162 /*0x04[12:11] = 2b'01 enable WL suspend*/ \
163 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
164 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
165 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
166 /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
167 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
168 {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
169 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
170 /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
171 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
172 {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
173 /*Set USB suspend enable local register 0xfe10[4]= 1 */ \
174 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
175 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
176 /*Set SDIO suspend local register*/ \
177 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
178 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
179 PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
180
181#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
182 /* format */ \
183 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
184 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
185 PWR_BASEADDR_SDIO,\
186 PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
187 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
188 PWR_BASEADDR_SDIO,\
189 PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
190 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
191 PWR_BASEADDR_MAC, \
192 PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
193 /*0x04[12:11] = 2b'01enable WL suspend*/
194
195
196#define RTL8188E_TRANS_CARDEMU_TO_PDN \
197 /* format */ \
198 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
199 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
200 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/ \
201 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
203
204
205#define RTL8188E_TRANS_PDN_TO_CARDEMU \
206 /* format */ \
207 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
208 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
209 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
210
211
212#define RTL8188E_TRANS_ACT_TO_LPS \
213 /* format */ \
214 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
215 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
216 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
217 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
218 /*zero if no pkt is tx*/\
219 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
220 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
221 /*Should be zero if no packet is transmitting*/ \
222 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
223 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
224 /*Should be zero if no packet is transmitting*/ \
225 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
226 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
227 /*Should be zero if no packet is transmitting*/ \
228 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
229 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
230 /*CCK and OFDM are disabled, and clock are gated*/ \
231 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
232 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
233 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\
234 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
235 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
236 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
237 /*check if removed later*/ \
238 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
239 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
240 /*Respond TxOK to scheduler*/ \
241 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
242
243
244#define RTL8188E_TRANS_LPS_TO_ACT \
245 /* format */ \
246 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
247 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
248 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
249 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
250 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
251 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
252 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
253 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
254 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
255 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
256 /*. 0x08[4] = 0 switch TSF to 40M*/ \
257 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
258 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
259 /*Polling 0x109[7]= 0 TSF in 40M*/ \
260 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
261 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
262 /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
263 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
264 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
265 /*. 0x101[1] = 1*/\
266 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
267 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
268 /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
269 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
270 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
271 /*. 0x02[1:0] = 2b'11 enable BB macro*/\
272 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, \
273 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
274 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
275
276
277#define RTL8188E_TRANS_END \
278 /* format */ \
279 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
280 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
281 0, PWR_CMD_END, 0, 0}
282
283extern struct wlan_pwr_cfg rtl8188e_power_on_flow
284 [RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS +
285 RTL8188E_TRANS_END_STEPS];
286extern struct wlan_pwr_cfg rtl8188e_radio_off_flow
287 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
288 RTL8188E_TRANS_END_STEPS];
289extern struct wlan_pwr_cfg rtl8188e_card_disable_flow
290 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
291 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
292 RTL8188E_TRANS_END_STEPS];
293extern struct wlan_pwr_cfg rtl8188e_card_enable_flow
294 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
295 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
296 RTL8188E_TRANS_END_STEPS];
297extern struct wlan_pwr_cfg rtl8188e_suspend_flow
298 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
299 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
300 RTL8188E_TRANS_END_STEPS];
301extern struct wlan_pwr_cfg rtl8188e_resume_flow
302 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
303 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
304 RTL8188E_TRANS_END_STEPS];
305extern struct wlan_pwr_cfg rtl8188e_hwpdn_flow
306 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
307 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
308 RTL8188E_TRANS_END_STEPS];
309extern struct wlan_pwr_cfg rtl8188e_enter_lps_flow
310 [RTL8188E_TRANS_ACT_TO_LPS_STEPS +
311 RTL8188E_TRANS_END_STEPS];
312extern struct wlan_pwr_cfg rtl8188e_leave_lps_flow
313 [RTL8188E_TRANS_LPS_TO_ACT_STEPS +
314 RTL8188E_TRANS_END_STEPS];
315
316/* RTL8723 Power Configuration CMDs for PCIe interface */
317#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188e_power_on_flow
318#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188e_radio_off_flow
319#define Rtl8188E_NIC_DISABLE_FLOW rtl8188e_card_disable_flow
320#define Rtl8188E_NIC_ENABLE_FLOW rtl8188e_card_enable_flow
321#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188e_suspend_flow
322#define Rtl8188E_NIC_RESUME_FLOW rtl8188e_resume_flow
323#define Rtl8188E_NIC_PDN_FLOW rtl8188e_hwpdn_flow
324#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188e_enter_lps_flow
325#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188e_leave_lps_flow
326
327#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.c b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.c
new file mode 100644
index 000000000000..4798000ed53a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.c
@@ -0,0 +1,140 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "pwrseq.h"
31
32
33/* Description:
34 * This routine deal with the Power Configuration CMDs
35 * parsing for RTL8723/RTL8188E Series IC.
36 * Assumption:
37 * We should follow specific format which was released from HW SD.
38 *
39 * 2011.07.07, added by Roger.
40 */
41
42bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
43 u8 fab_version, u8 interface_type,
44 struct wlan_pwr_cfg pwrcfgcmd[])
45{
46 struct wlan_pwr_cfg cmd = {0};
47 bool polling_bit = false;
48 u32 ary_idx = 0;
49 u8 val = 0;
50 u32 offset = 0;
51 u32 polling_count = 0;
52 u32 max_polling_cnt = 5000;
53
54 do {
55 cmd = pwrcfgcmd[ary_idx];
56 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
57 "rtl_hal_pwrseqcmdparsing(): offset(%#x), cut_msk(%#x), fab_msk(%#x),"
58 "interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), val(%#x)\n",
59 GET_PWR_CFG_OFFSET(cmd),
60 GET_PWR_CFG_CUT_MASK(cmd),
61 GET_PWR_CFG_FAB_MASK(cmd),
62 GET_PWR_CFG_INTF_MASK(cmd),
63 GET_PWR_CFG_BASE(cmd),
64 GET_PWR_CFG_CMD(cmd),
65 GET_PWR_CFG_MASK(cmd),
66 GET_PWR_CFG_VALUE(cmd));
67
68 if ((GET_PWR_CFG_FAB_MASK(cmd) & fab_version) &&
69 (GET_PWR_CFG_CUT_MASK(cmd) & cut_version) &&
70 (GET_PWR_CFG_INTF_MASK(cmd) & interface_type)) {
71 switch (GET_PWR_CFG_CMD(cmd)) {
72 case PWR_CMD_READ:
73 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
74 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
75 break;
76 case PWR_CMD_WRITE: {
77 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
78 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
79 offset = GET_PWR_CFG_OFFSET(cmd);
80
81 /*Read the val from system register*/
82 val = rtl_read_byte(rtlpriv, offset);
83 val &= (~(GET_PWR_CFG_MASK(cmd)));
84 val |= (GET_PWR_CFG_VALUE(cmd) &
85 GET_PWR_CFG_MASK(cmd));
86
87 /*Write the val back to sytem register*/
88 rtl_write_byte(rtlpriv, offset, val);
89 }
90 break;
91 case PWR_CMD_POLLING:
92 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
93 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
94 polling_bit = false;
95 offset = GET_PWR_CFG_OFFSET(cmd);
96
97 do {
98 val = rtl_read_byte(rtlpriv, offset);
99
100 val = val & GET_PWR_CFG_MASK(cmd);
101 if (val == (GET_PWR_CFG_VALUE(cmd) &
102 GET_PWR_CFG_MASK(cmd)))
103 polling_bit = true;
104 else
105 udelay(10);
106
107 if (polling_count++ > max_polling_cnt) {
108 RT_TRACE(rtlpriv, COMP_INIT,
109 DBG_LOUD,
110 "polling fail in pwrseqcmd\n");
111 return false;
112 }
113 } while (!polling_bit);
114
115 break;
116 case PWR_CMD_DELAY:
117 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
118 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
119 if (GET_PWR_CFG_VALUE(cmd) == PWRSEQ_DELAY_US)
120 udelay(GET_PWR_CFG_OFFSET(cmd));
121 else
122 mdelay(GET_PWR_CFG_OFFSET(cmd));
123 break;
124 case PWR_CMD_END:
125 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
126 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
127 return true;
128 break;
129 default:
130 RT_ASSERT(false,
131 "rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
132 break;
133 }
134 }
135
136 ary_idx++;
137 } while (1);
138
139 return true;
140}
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.h b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.h
new file mode 100644
index 000000000000..622ea7e72b22
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.h
@@ -0,0 +1,97 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8723E_PWRSEQCMD_H__
31#define __RTL8723E_PWRSEQCMD_H__
32
33#include "wifi.h"
34/*---------------------------------------------*/
35/* The value of cmd: 4 bits */
36/*---------------------------------------------*/
37#define PWR_CMD_READ 0x00
38#define PWR_CMD_WRITE 0x01
39#define PWR_CMD_POLLING 0x02
40#define PWR_CMD_DELAY 0x03
41#define PWR_CMD_END 0x04
42
43/* define the base address of each block */
44#define PWR_BASEADDR_MAC 0x00
45#define PWR_BASEADDR_USB 0x01
46#define PWR_BASEADDR_PCIE 0x02
47#define PWR_BASEADDR_SDIO 0x03
48
49#define PWR_INTF_SDIO_MSK BIT(0)
50#define PWR_INTF_USB_MSK BIT(1)
51#define PWR_INTF_PCI_MSK BIT(2)
52#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
53
54#define PWR_FAB_TSMC_MSK BIT(0)
55#define PWR_FAB_UMC_MSK BIT(1)
56#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
57
58#define PWR_CUT_TESTCHIP_MSK BIT(0)
59#define PWR_CUT_A_MSK BIT(1)
60#define PWR_CUT_B_MSK BIT(2)
61#define PWR_CUT_C_MSK BIT(3)
62#define PWR_CUT_D_MSK BIT(4)
63#define PWR_CUT_E_MSK BIT(5)
64#define PWR_CUT_F_MSK BIT(6)
65#define PWR_CUT_G_MSK BIT(7)
66#define PWR_CUT_ALL_MSK 0xFF
67
68enum pwrseq_delay_unit {
69 PWRSEQ_DELAY_US,
70 PWRSEQ_DELAY_MS,
71};
72
73struct wlan_pwr_cfg {
74 u16 offset;
75 u8 cut_msk;
76 u8 fab_msk:4;
77 u8 interface_msk:4;
78 u8 base:4;
79 u8 cmd:4;
80 u8 msk;
81 u8 value;
82};
83
84#define GET_PWR_CFG_OFFSET(__PWR) (__PWR.offset)
85#define GET_PWR_CFG_CUT_MASK(__PWR) (__PWR.cut_msk)
86#define GET_PWR_CFG_FAB_MASK(__PWR) (__PWR.fab_msk)
87#define GET_PWR_CFG_INTF_MASK(__PWR) (__PWR.interface_msk)
88#define GET_PWR_CFG_BASE(__PWR) (__PWR.base)
89#define GET_PWR_CFG_CMD(__PWR) (__PWR.cmd)
90#define GET_PWR_CFG_MASK(__PWR) (__PWR.msk)
91#define GET_PWR_CFG_VALUE(__PWR) (__PWR.value)
92
93bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
94 u8 fab_version, u8 interface_type,
95 struct wlan_pwr_cfg pwrcfgcmd[]);
96
97#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/reg.h b/drivers/net/wireless/rtlwifi/rtl8188ee/reg.h
new file mode 100644
index 000000000000..d849abf7d94a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/reg.h
@@ -0,0 +1,2258 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_REG_H__
31#define __RTL92C_REG_H__
32
33#define TXPKT_BUF_SELECT 0x69
34#define RXPKT_BUF_SELECT 0xA5
35#define DISABLE_TRXPKT_BUF_ACCESS 0x0
36
37#define REG_SYS_ISO_CTRL 0x0000
38#define REG_SYS_FUNC_EN 0x0002
39#define REG_APS_FSMCO 0x0004
40#define REG_SYS_CLKR 0x0008
41#define REG_9346CR 0x000A
42#define REG_EE_VPD 0x000C
43#define REG_AFE_MISC 0x0010
44#define REG_SPS0_CTRL 0x0011
45#define REG_SPS_OCP_CFG 0x0018
46#define REG_RSV_CTRL 0x001C
47#define REG_RF_CTRL 0x001F
48#define REG_LDOA15_CTRL 0x0020
49#define REG_LDOV12D_CTRL 0x0021
50#define REG_LDOHCI12_CTRL 0x0022
51#define REG_LPLDO_CTRL 0x0023
52#define REG_AFE_XTAL_CTRL 0x0024
53#define REG_AFE_LDO_CTRL 0x0027 /* 1.5v for 8188EE test
54 * chip, 1.4v for MP chip
55 */
56#define REG_AFE_PLL_CTRL 0x0028
57#define REG_EFUSE_CTRL 0x0030
58#define REG_EFUSE_TEST 0x0034
59#define REG_PWR_DATA 0x0038
60#define REG_CAL_TIMER 0x003C
61#define REG_ACLK_MON 0x003E
62#define REG_GPIO_MUXCFG 0x0040
63#define REG_GPIO_IO_SEL 0x0042
64#define REG_MAC_PINMUX_CFG 0x0043
65#define REG_GPIO_PIN_CTRL 0x0044
66#define REG_GPIO_INTM 0x0048
67#define REG_LEDCFG0 0x004C
68#define REG_LEDCFG1 0x004D
69#define REG_LEDCFG2 0x004E
70#define REG_LEDCFG3 0x004F
71#define REG_FSIMR 0x0050
72#define REG_FSISR 0x0054
73#define REG_HSIMR 0x0058
74#define REG_HSISR 0x005c
75#define REG_GPIO_PIN_CTRL_2 0x0060
76#define REG_GPIO_IO_SEL_2 0x0062
77#define REG_GPIO_OUTPUT 0x006c
78#define REG_AFE_XTAL_CTRL_EXT 0x0078
79#define REG_XCK_OUT_CTRL 0x007c
80#define REG_MCUFWDL 0x0080
81#define REG_WOL_EVENT 0x0081
82#define REG_MCUTSTCFG 0x0084
83
84
85#define REG_HIMR 0x00B0
86#define REG_HISR 0x00B4
87#define REG_HIMRE 0x00B8
88#define REG_HISRE 0x00BC
89
90#define REG_EFUSE_ACCESS 0x00CF
91
92#define REG_BIST_SCAN 0x00D0
93#define REG_BIST_RPT 0x00D4
94#define REG_BIST_ROM_RPT 0x00D8
95#define REG_USB_SIE_INTF 0x00E0
96#define REG_PCIE_MIO_INTF 0x00E4
97#define REG_PCIE_MIO_INTD 0x00E8
98#define REG_HPON_FSM 0x00EC
99#define REG_SYS_CFG 0x00F0
100
101#define REG_CR 0x0100
102#define REG_PBP 0x0104
103#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
104#define REG_TRXDMA_CTRL 0x010C
105#define REG_TRXFF_BNDY 0x0114
106#define REG_TRXFF_STATUS 0x0118
107#define REG_RXFF_PTR 0x011C
108
109#define REG_CPWM 0x012F
110#define REG_FWIMR 0x0130
111#define REG_FWISR 0x0134
112#define REG_PKTBUF_DBG_CTRL 0x0140
113#define REG_PKTBUF_DBG_DATA_L 0x0144
114#define REG_PKTBUF_DBG_DATA_H 0x0148
115#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2)
116
117#define REG_TC0_CTRL 0x0150
118#define REG_TC1_CTRL 0x0154
119#define REG_TC2_CTRL 0x0158
120#define REG_TC3_CTRL 0x015C
121#define REG_TC4_CTRL 0x0160
122#define REG_TCUNIT_BASE 0x0164
123#define REG_MBIST_START 0x0174
124#define REG_MBIST_DONE 0x0178
125#define REG_MBIST_FAIL 0x017C
126#define REG_32K_CTRL 0x0194
127#define REG_C2HEVT_MSG_NORMAL 0x01A0
128#define REG_C2HEVT_CLEAR 0x01AF
129#define REG_C2HEVT_MSG_TEST 0x01B8
130#define REG_MCUTST_1 0x01c0
131#define REG_FMETHR 0x01C8
132#define REG_HMETFR 0x01CC
133#define REG_HMEBOX_0 0x01D0
134#define REG_HMEBOX_1 0x01D4
135#define REG_HMEBOX_2 0x01D8
136#define REG_HMEBOX_3 0x01DC
137
138#define REG_LLT_INIT 0x01E0
139#define REG_BB_ACCEESS_CTRL 0x01E8
140#define REG_BB_ACCESS_DATA 0x01EC
141
142#define REG_HMEBOX_EXT_0 0x01F0
143#define REG_HMEBOX_EXT_1 0x01F4
144#define REG_HMEBOX_EXT_2 0x01F8
145#define REG_HMEBOX_EXT_3 0x01FC
146
147#define REG_RQPN 0x0200
148#define REG_FIFOPAGE 0x0204
149#define REG_TDECTRL 0x0208
150#define REG_TXDMA_OFFSET_CHK 0x020C
151#define REG_TXDMA_STATUS 0x0210
152#define REG_RQPN_NPQ 0x0214
153
154#define REG_RXDMA_AGG_PG_TH 0x0280
155#define REG_FW_UPD_RDPTR 0x0284 /* FW shall update this
156 * register before FW * write
157 * RXPKT_RELEASE_POLL to 1
158 */
159#define REG_RXDMA_CONTROL 0x0286 /* Control the RX DMA.*/
160#define REG_RXPKT_NUM 0x0287 /* The number of packets
161 * in RXPKTBUF.
162 */
163#define REG_PCIE_CTRL_REG 0x0300
164#define REG_INT_MIG 0x0304
165#define REG_BCNQ_DESA 0x0308
166#define REG_HQ_DESA 0x0310
167#define REG_MGQ_DESA 0x0318
168#define REG_VOQ_DESA 0x0320
169#define REG_VIQ_DESA 0x0328
170#define REG_BEQ_DESA 0x0330
171#define REG_BKQ_DESA 0x0338
172#define REG_RX_DESA 0x0340
173
174#define REG_DBI 0x0348
175#define REG_MDIO 0x0354
176#define REG_DBG_SEL 0x0360
177#define REG_PCIE_HRPWM 0x0361
178#define REG_PCIE_HCPWM 0x0363
179#define REG_UART_CTRL 0x0364
180#define REG_WATCH_DOG 0x0368
181#define REG_UART_TX_DESA 0x0370
182#define REG_UART_RX_DESA 0x0378
183
184
185#define REG_HDAQ_DESA_NODEF 0x0000
186#define REG_CMDQ_DESA_NODEF 0x0000
187
188#define REG_VOQ_INFORMATION 0x0400
189#define REG_VIQ_INFORMATION 0x0404
190#define REG_BEQ_INFORMATION 0x0408
191#define REG_BKQ_INFORMATION 0x040C
192#define REG_MGQ_INFORMATION 0x0410
193#define REG_HGQ_INFORMATION 0x0414
194#define REG_BCNQ_INFORMATION 0x0418
195#define REG_TXPKT_EMPTY 0x041A
196
197
198#define REG_CPU_MGQ_INFORMATION 0x041C
199#define REG_FWHW_TXQ_CTRL 0x0420
200#define REG_HWSEQ_CTRL 0x0423
201#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
202#define REG_TXPKTBUF_MGQ_BDNY 0x0425
203#define REG_MULTI_BCNQ_EN 0x0426
204#define REG_MULTI_BCNQ_OFFSET 0x0427
205#define REG_SPEC_SIFS 0x0428
206#define REG_RL 0x042A
207#define REG_DARFRC 0x0430
208#define REG_RARFRC 0x0438
209#define REG_RRSR 0x0440
210#define REG_ARFR0 0x0444
211#define REG_ARFR1 0x0448
212#define REG_ARFR2 0x044C
213#define REG_ARFR3 0x0450
214#define REG_AGGLEN_LMT 0x0458
215#define REG_AMPDU_MIN_SPACE 0x045C
216#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
217#define REG_FAST_EDCA_CTRL 0x0460
218#define REG_RD_RESP_PKT_TH 0x0463
219#define REG_INIRTS_RATE_SEL 0x0480
220#define REG_INIDATA_RATE_SEL 0x0484
221#define REG_POWER_STATUS 0x04A4
222#define REG_POWER_STAGE1 0x04B4
223#define REG_POWER_STAGE2 0x04B8
224#define REG_PKT_LIFE_TIME 0x04C0
225#define REG_STBC_SETTING 0x04C4
226#define REG_PROT_MODE_CTRL 0x04C8
227#define REG_BAR_MODE_CTRL 0x04CC
228#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
229#define REG_EARLY_MODE_CONTROL 0x04D0
230#define REG_NQOS_SEQ 0x04DC
231#define REG_QOS_SEQ 0x04DE
232#define REG_NEED_CPU_HANDLE 0x04E0
233#define REG_PKT_LOSE_RPT 0x04E1
234#define REG_PTCL_ERR_STATUS 0x04E2
235#define REG_TX_RPT_CTRL 0x04EC
236#define REG_TX_RPT_TIME 0x04F0
237#define REG_DUMMY 0x04FC
238
239#define REG_EDCA_VO_PARAM 0x0500
240#define REG_EDCA_VI_PARAM 0x0504
241#define REG_EDCA_BE_PARAM 0x0508
242#define REG_EDCA_BK_PARAM 0x050C
243#define REG_BCNTCFG 0x0510
244#define REG_PIFS 0x0512
245#define REG_RDG_PIFS 0x0513
246#define REG_SIFS_CTX 0x0514
247#define REG_SIFS_TRX 0x0516
248#define REG_AGGR_BREAK_TIME 0x051A
249#define REG_SLOT 0x051B
250#define REG_TX_PTCL_CTRL 0x0520
251#define REG_TXPAUSE 0x0522
252#define REG_DIS_TXREQ_CLR 0x0523
253#define REG_RD_CTRL 0x0524
254#define REG_TBTT_PROHIBIT 0x0540
255#define REG_RD_NAV_NXT 0x0544
256#define REG_NAV_PROT_LEN 0x0546
257#define REG_BCN_CTRL 0x0550
258#define REG_USTIME_TSF 0x0551
259#define REG_MBID_NUM 0x0552
260#define REG_DUAL_TSF_RST 0x0553
261#define REG_BCN_INTERVAL 0x0554
262#define REG_MBSSID_BCN_SPACE 0x0554
263#define REG_DRVERLYINT 0x0558
264#define REG_BCNDMATIM 0x0559
265#define REG_ATIMWND 0x055A
266#define REG_BCN_MAX_ERR 0x055D
267#define REG_RXTSF_OFFSET_CCK 0x055E
268#define REG_RXTSF_OFFSET_OFDM 0x055F
269#define REG_TSFTR 0x0560
270#define REG_INIT_TSFTR 0x0564
271#define REG_PSTIMER 0x0580
272#define REG_TIMER0 0x0584
273#define REG_TIMER1 0x0588
274#define REG_ACMHWCTRL 0x05C0
275#define REG_ACMRSTCTRL 0x05C1
276#define REG_ACMAVG 0x05C2
277#define REG_VO_ADMTIME 0x05C4
278#define REG_VI_ADMTIME 0x05C6
279#define REG_BE_ADMTIME 0x05C8
280#define REG_EDCA_RANDOM_GEN 0x05CC
281#define REG_SCH_TXCMD 0x05D0
282
283#define REG_APSD_CTRL 0x0600
284#define REG_BWOPMODE 0x0603
285#define REG_TCR 0x0604
286#define REG_RCR 0x0608
287#define REG_RX_PKT_LIMIT 0x060C
288#define REG_RX_DLK_TIME 0x060D
289#define REG_RX_DRVINFO_SZ 0x060F
290
291#define REG_MACID 0x0610
292#define REG_BSSID 0x0618
293#define REG_MAR 0x0620
294#define REG_MBIDCAMCFG 0x0628
295
296#define REG_USTIME_EDCA 0x0638
297#define REG_MAC_SPEC_SIFS 0x063A
298#define REG_RESP_SIFS_CCK 0x063C
299#define REG_RESP_SIFS_OFDM 0x063E
300#define REG_ACKTO 0x0640
301#define REG_CTS2TO 0x0641
302#define REG_EIFS 0x0642
303
304#define REG_NAV_CTRL 0x0650
305#define REG_BACAMCMD 0x0654
306#define REG_BACAMCONTENT 0x0658
307#define REG_LBDLY 0x0660
308#define REG_FWDLY 0x0661
309#define REG_RXERR_RPT 0x0664
310#define REG_TRXPTCL_CTL 0x0668
311
312#define REG_CAMCMD 0x0670
313#define REG_CAMWRITE 0x0674
314#define REG_CAMREAD 0x0678
315#define REG_CAMDBG 0x067C
316#define REG_SECCFG 0x0680
317
318#define REG_WOW_CTRL 0x0690
319#define REG_PSSTATUS 0x0691
320#define REG_PS_RX_INFO 0x0692
321#define REG_UAPSD_TID 0x0693
322#define REG_LPNAV_CTRL 0x0694
323#define REG_WKFMCAM_NUM 0x0698
324#define REG_WKFMCAM_RWD 0x069C
325#define REG_RXFLTMAP0 0x06A0
326#define REG_RXFLTMAP1 0x06A2
327#define REG_RXFLTMAP2 0x06A4
328#define REG_BCN_PSR_RPT 0x06A8
329#define REG_CALB32K_CTRL 0x06AC
330#define REG_PKT_MON_CTRL 0x06B4
331#define REG_BT_COEX_TABLE 0x06C0
332#define REG_WMAC_RESP_TXINFO 0x06D8
333
334#define REG_USB_INFO 0xFE17
335#define REG_USB_SPECIAL_OPTION 0xFE55
336#define REG_USB_DMA_AGG_TO 0xFE5B
337#define REG_USB_AGG_TO 0xFE5C
338#define REG_USB_AGG_TH 0xFE5D
339
340#define REG_TEST_USB_TXQS 0xFE48
341#define REG_TEST_SIE_VID 0xFE60
342#define REG_TEST_SIE_PID 0xFE62
343#define REG_TEST_SIE_OPTIONAL 0xFE64
344#define REG_TEST_SIE_CHIRP_K 0xFE65
345#define REG_TEST_SIE_PHY 0xFE66
346#define REG_TEST_SIE_MAC_ADDR 0xFE70
347#define REG_TEST_SIE_STRING 0xFE80
348
349#define REG_NORMAL_SIE_VID 0xFE60
350#define REG_NORMAL_SIE_PID 0xFE62
351#define REG_NORMAL_SIE_OPTIONAL 0xFE64
352#define REG_NORMAL_SIE_EP 0xFE65
353#define REG_NORMAL_SIE_PHY 0xFE68
354#define REG_NORMAL_SIE_MAC_ADDR 0xFE70
355#define REG_NORMAL_SIE_STRING 0xFE80
356
357#define CR9346 REG_9346CR
358#define MSR (REG_CR + 2)
359#define ISR REG_HISR
360#define TSFR REG_TSFTR
361
362#define MACIDR0 REG_MACID
363#define MACIDR4 (REG_MACID + 4)
364
365#define PBP REG_PBP
366
367#define IDR0 MACIDR0
368#define IDR4 MACIDR4
369
370#define UNUSED_REGISTER 0x1BF
371#define DCAM UNUSED_REGISTER
372#define PSR UNUSED_REGISTER
373#define BBADDR UNUSED_REGISTER
374#define PHYDATAR UNUSED_REGISTER
375
376#define INVALID_BBRF_VALUE 0x12345678
377
378#define MAX_MSS_DENSITY_2T 0x13
379#define MAX_MSS_DENSITY_1T 0x0A
380
381#define CMDEEPROM_EN BIT(5)
382#define CMDEEPROM_SEL BIT(4)
383#define CMD9346CR_9356SEL BIT(4)
384#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL)
385#define AUTOLOAD_EFUSE CMDEEPROM_EN
386
387#define GPIOSEL_GPIO 0
388#define GPIOSEL_ENBT BIT(5)
389
390#define GPIO_IN REG_GPIO_PIN_CTRL
391#define GPIO_OUT (REG_GPIO_PIN_CTRL+1)
392#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)
393#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
394
395/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
396#define HSIMR_GPIO12_0_INT_EN BIT(0)
397#define HSIMR_SPS_OCP_INT_EN BIT(5)
398#define HSIMR_RON_INT_EN BIT(6)
399#define HSIMR_PDN_INT_EN BIT(7)
400#define HSIMR_GPIO9_INT_EN BIT(25)
401
402
403/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
404#define HSISR_GPIO12_0_INT BIT(0)
405#define HSISR_SPS_OCP_INT BIT(5)
406#define HSISR_RON_INT_EN BIT(6)
407#define HSISR_PDNINT BIT(7)
408#define HSISR_GPIO9_INT BIT(25)
409
410#define MSR_NOLINK 0x00
411#define MSR_ADHOC 0x01
412#define MSR_INFRA 0x02
413#define MSR_AP 0x03
414
415#define RRSR_RSC_OFFSET 21
416#define RRSR_SHORT_OFFSET 23
417#define RRSR_RSC_BW_40M 0x600000
418#define RRSR_RSC_UPSUBCHNL 0x400000
419#define RRSR_RSC_LOWSUBCHNL 0x200000
420#define RRSR_SHORT 0x800000
421#define RRSR_1M BIT(0)
422#define RRSR_2M BIT(1)
423#define RRSR_5_5M BIT(2)
424#define RRSR_11M BIT(3)
425#define RRSR_6M BIT(4)
426#define RRSR_9M BIT(5)
427#define RRSR_12M BIT(6)
428#define RRSR_18M BIT(7)
429#define RRSR_24M BIT(8)
430#define RRSR_36M BIT(9)
431#define RRSR_48M BIT(10)
432#define RRSR_54M BIT(11)
433#define RRSR_MCS0 BIT(12)
434#define RRSR_MCS1 BIT(13)
435#define RRSR_MCS2 BIT(14)
436#define RRSR_MCS3 BIT(15)
437#define RRSR_MCS4 BIT(16)
438#define RRSR_MCS5 BIT(17)
439#define RRSR_MCS6 BIT(18)
440#define RRSR_MCS7 BIT(19)
441#define BRSR_ACKSHORTPMB BIT(23)
442
443#define RATR_1M 0x00000001
444#define RATR_2M 0x00000002
445#define RATR_55M 0x00000004
446#define RATR_11M 0x00000008
447#define RATR_6M 0x00000010
448#define RATR_9M 0x00000020
449#define RATR_12M 0x00000040
450#define RATR_18M 0x00000080
451#define RATR_24M 0x00000100
452#define RATR_36M 0x00000200
453#define RATR_48M 0x00000400
454#define RATR_54M 0x00000800
455#define RATR_MCS0 0x00001000
456#define RATR_MCS1 0x00002000
457#define RATR_MCS2 0x00004000
458#define RATR_MCS3 0x00008000
459#define RATR_MCS4 0x00010000
460#define RATR_MCS5 0x00020000
461#define RATR_MCS6 0x00040000
462#define RATR_MCS7 0x00080000
463#define RATR_MCS8 0x00100000
464#define RATR_MCS9 0x00200000
465#define RATR_MCS10 0x00400000
466#define RATR_MCS11 0x00800000
467#define RATR_MCS12 0x01000000
468#define RATR_MCS13 0x02000000
469#define RATR_MCS14 0x04000000
470#define RATR_MCS15 0x08000000
471
472#define RATE_1M BIT(0)
473#define RATE_2M BIT(1)
474#define RATE_5_5M BIT(2)
475#define RATE_11M BIT(3)
476#define RATE_6M BIT(4)
477#define RATE_9M BIT(5)
478#define RATE_12M BIT(6)
479#define RATE_18M BIT(7)
480#define RATE_24M BIT(8)
481#define RATE_36M BIT(9)
482#define RATE_48M BIT(10)
483#define RATE_54M BIT(11)
484#define RATE_MCS0 BIT(12)
485#define RATE_MCS1 BIT(13)
486#define RATE_MCS2 BIT(14)
487#define RATE_MCS3 BIT(15)
488#define RATE_MCS4 BIT(16)
489#define RATE_MCS5 BIT(17)
490#define RATE_MCS6 BIT(18)
491#define RATE_MCS7 BIT(19)
492#define RATE_MCS8 BIT(20)
493#define RATE_MCS9 BIT(21)
494#define RATE_MCS10 BIT(22)
495#define RATE_MCS11 BIT(23)
496#define RATE_MCS12 BIT(24)
497#define RATE_MCS13 BIT(25)
498#define RATE_MCS14 BIT(26)
499#define RATE_MCS15 BIT(27)
500
501#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
502#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \
503 RATR_24M | RATR_36M | RATR_48M | RATR_54M)
504#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
505 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
506 RATR_MCS6 | RATR_MCS7)
507#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
508 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
509 RATR_MCS14 | RATR_MCS15)
510
511#define BW_OPMODE_20MHZ BIT(2)
512#define BW_OPMODE_5G BIT(1)
513#define BW_OPMODE_11J BIT(0)
514
515#define CAM_VALID BIT(15)
516#define CAM_NOTVALID 0x0000
517#define CAM_USEDK BIT(5)
518
519#define CAM_NONE 0x0
520#define CAM_WEP40 0x01
521#define CAM_TKIP 0x02
522#define CAM_AES 0x04
523#define CAM_WEP104 0x05
524
525#define TOTAL_CAM_ENTRY 32
526#define HALF_CAM_ENTRY 16
527
528#define CAM_WRITE BIT(16)
529#define CAM_READ 0x00000000
530#define CAM_POLLINIG BIT(31)
531
532#define SCR_USEDK 0x01
533#define SCR_TXSEC_ENABLE 0x02
534#define SCR_RXSEC_ENABLE 0x04
535
536#define WOW_PMEN BIT(0)
537#define WOW_WOMEN BIT(1)
538#define WOW_MAGIC BIT(2)
539#define WOW_UWF BIT(3)
540
541/*********************************************
542* 8188 IMR/ISR bits
543**********************************************/
544#define IMR_DISABLED 0x0
545/* IMR DW0(0x0060-0063) Bit 0-31 */
546#define IMR_TXCCK BIT(30) /* TXRPT interrupt when CCX bit of
547 * the packet is set
548 */
549#define IMR_PSTIMEOUT BIT(29) /* Power Save Time Out Interrupt */
550#define IMR_GTINT4 BIT(28) /* When GTIMER4 expires,
551 * this bit is set to 1
552 */
553#define IMR_GTINT3 BIT(27) /* When GTIMER3 expires,
554 * this bit is set to 1
555 */
556#define IMR_TBDER BIT(26) /* Transmit Beacon0 Error */
557#define IMR_TBDOK BIT(25) /* Transmit Beacon0 OK */
558#define IMR_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle ind int */
559#define IMR_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
560#define IMR_BCNDOK0 BIT(16) /* Beacon Queue DMA OK0 */
561#define IMR_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & HSISR is
562 * true, this bit is set to 1)
563 */
564#define IMR_BCNDMAINT_E BIT(14) /* Beacon DMA Int Extension for Win7 */
565#define IMR_ATIMEND BIT(12) /* CTWidnow End or ATIM Window End */
566#define IMR_HISR1_IND_INT BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is
567 * true, this bit is set to 1)
568 */
569#define IMR_C2HCMD BIT(10) /* CPU to Host Command INT Status,
570 * Write 1 clear
571 */
572#define IMR_CPWM2 BIT(9) /* CPU power Mode exchange INT Status,
573 * Write 1 clear
574 */
575#define IMR_CPWM BIT(8) /* CPU power Mode exchange INT Status,
576 * Write 1 clear
577 */
578#define IMR_HIGHDOK BIT(7) /* High Queue DMA OK */
579#define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK */
580#define IMR_BKDOK BIT(5) /* AC_BK DMA OK */
581#define IMR_BEDOK BIT(4) /* AC_BE DMA OK */
582#define IMR_VIDOK BIT(3) /* AC_VI DMA OK */
583#define IMR_VODOK BIT(2) /* AC_VO DMA OK */
584#define IMR_RDU BIT(1) /* Rx Descriptor Unavailable */
585#define IMR_ROK BIT(0) /* Receive DMA OK */
586
587/* IMR DW1(0x00B4-00B7) Bit 0-31 */
588#define IMR_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */
589#define IMR_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */
590#define IMR_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */
591#define IMR_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */
592#define IMR_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */
593#define IMR_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */
594#define IMR_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */
595#define IMR_BCNDOK7 BIT(20) /* Beacon Queue DMA OK Interrup 7 */
596#define IMR_BCNDOK6 BIT(19) /* Beacon Queue DMA OK Interrup 6 */
597#define IMR_BCNDOK5 BIT(18) /* Beacon Queue DMA OK Interrup 5 */
598#define IMR_BCNDOK4 BIT(17) /* Beacon Queue DMA OK Interrup 4 */
599#define IMR_BCNDOK3 BIT(16) /* Beacon Queue DMA OK Interrup 3 */
600#define IMR_BCNDOK2 BIT(15) /* Beacon Queue DMA OK Interrup 2 */
601#define IMR_BCNDOK1 BIT(14) /* Beacon Queue DMA OK Interrup 1 */
602#define IMR_ATIMEND_E BIT(13) /* ATIM Window End Extension for Win7 */
603#define IMR_TXERR BIT(11) /* Tx Err Flag Int Status,
604 * write 1 clear.
605 */
606#define IMR_RXERR BIT(10) /* Rx Err Flag INT Status,
607 * Write 1 clear
608 */
609#define IMR_TXFOVW BIT(9) /* Transmit FIFO Overflow */
610#define IMR_RXFOVW BIT(8) /* Receive FIFO Overflow */
611
612
613#define HWSET_MAX_SIZE 512
614#define EFUSE_MAX_SECTION 64
615#define EFUSE_REAL_CONTENT_LEN 256
616#define EFUSE_OOB_PROTECT_BYTES 18 /* PG data exclude header,
617 * dummy 7 bytes frome CP
618 * test and reserved 1byte.
619 */
620
621#define EEPROM_DEFAULT_TSSI 0x0
622#define EEPROM_DEFAULT_TXPOWERDIFF 0x0
623#define EEPROM_DEFAULT_CRYSTALCAP 0x5
624#define EEPROM_DEFAULT_BOARDTYPE 0x02
625#define EEPROM_DEFAULT_TXPOWER 0x1010
626#define EEPROM_DEFAULT_HT2T_TXPWR 0x10
627
628#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
629#define EEPROM_DEFAULT_THERMALMETER 0x18
630#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0
631#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5
632#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22
633#define EEPROM_DEFAULT_HT40_2SDIFF 0x0
634#define EEPROM_DEFAULT_HT20_DIFF 2
635#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
636#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
637#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
638
639#define RF_OPTION1 0x79
640#define RF_OPTION2 0x7A
641#define RF_OPTION3 0x7B
642#define RF_OPTION4 0x7C
643
644#define EEPROM_DEFAULT_PID 0x1234
645#define EEPROM_DEFAULT_VID 0x5678
646#define EEPROM_DEFAULT_CUSTOMERID 0xAB
647#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD
648#define EEPROM_DEFAULT_VERSION 0
649
650#define EEPROM_CHANNEL_PLAN_FCC 0x0
651#define EEPROM_CHANNEL_PLAN_IC 0x1
652#define EEPROM_CHANNEL_PLAN_ETSI 0x2
653#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
654#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
655#define EEPROM_CHANNEL_PLAN_MKK 0x5
656#define EEPROM_CHANNEL_PLAN_MKK1 0x6
657#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
658#define EEPROM_CHANNEL_PLAN_TELEC 0x8
659#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
660#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
661#define EEPROM_CHANNEL_PLAN_NCC 0xB
662#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
663
664#define EEPROM_CID_DEFAULT 0x0
665#define EEPROM_CID_TOSHIBA 0x4
666#define EEPROM_CID_CCX 0x10
667#define EEPROM_CID_QMI 0x0D
668#define EEPROM_CID_WHQL 0xFE
669
670#define RTL8188E_EEPROM_ID 0x8129
671
672#define EEPROM_HPON 0x02
673#define EEPROM_CLK 0x06
674#define EEPROM_TESTR 0x08
675
676#define EEPROM_TXPOWERCCK 0x10
677#define EEPROM_TXPOWERHT40_1S 0x16
678#define EEPROM_TXPOWERHT20DIFF 0x1B
679#define EEPROM_TXPOWER_OFDMDIFF 0x1B
680
681#define EEPROM_TX_PWR_INX 0x10
682
683#define EEPROM_CHANNELPLAN 0xB8
684#define EEPROM_XTAL_88E 0xB9
685#define EEPROM_THERMAL_METER_88E 0xBA
686#define EEPROM_IQK_LCK_88E 0xBB
687
688#define EEPROM_RF_BOARD_OPTION_88E 0xC1
689#define EEPROM_RF_FEATURE_OPTION_88E 0xC2
690#define EEPROM_RF_BT_SETTING_88E 0xC3
691#define EEPROM_VERSION 0xC4
692#define EEPROM_CUSTOMER_ID 0xC5
693#define EEPROM_RF_ANTENNA_OPT_88E 0xC9
694
695#define EEPROM_MAC_ADDR 0xD0
696#define EEPROM_VID 0xD6
697#define EEPROM_DID 0xD8
698#define EEPROM_SVID 0xDA
699#define EEPROM_SMID 0xDC
700
701#define STOPBECON BIT(6)
702#define STOPHIGHT BIT(5)
703#define STOPMGT BIT(4)
704#define STOPVO BIT(3)
705#define STOPVI BIT(2)
706#define STOPBE BIT(1)
707#define STOPBK BIT(0)
708
709#define RCR_APPFCS BIT(31)
710#define RCR_APP_MIC BIT(30)
711#define RCR_APP_ICV BIT(29)
712#define RCR_APP_PHYST_RXFF BIT(28)
713#define RCR_APP_BA_SSN BIT(27)
714#define RCR_ENMBID BIT(24)
715#define RCR_LSIGEN BIT(23)
716#define RCR_MFBEN BIT(22)
717#define RCR_HTC_LOC_CTRL BIT(14)
718#define RCR_AMF BIT(13)
719#define RCR_ACF BIT(12)
720#define RCR_ADF BIT(11)
721#define RCR_AICV BIT(9)
722#define RCR_ACRC32 BIT(8)
723#define RCR_CBSSID_BCN BIT(7)
724#define RCR_CBSSID_DATA BIT(6)
725#define RCR_CBSSID RCR_CBSSID_DATA
726#define RCR_APWRMGT BIT(5)
727#define RCR_ADD3 BIT(4)
728#define RCR_AB BIT(3)
729#define RCR_AM BIT(2)
730#define RCR_APM BIT(1)
731#define RCR_AAP BIT(0)
732#define RCR_MXDMA_OFFSET 8
733#define RCR_FIFO_OFFSET 13
734
735#define RSV_CTRL 0x001C
736#define RD_CTRL 0x0524
737
738#define REG_USB_INFO 0xFE17
739#define REG_USB_SPECIAL_OPTION 0xFE55
740#define REG_USB_DMA_AGG_TO 0xFE5B
741#define REG_USB_AGG_TO 0xFE5C
742#define REG_USB_AGG_TH 0xFE5D
743
744#define REG_USB_VID 0xFE60
745#define REG_USB_PID 0xFE62
746#define REG_USB_OPTIONAL 0xFE64
747#define REG_USB_CHIRP_K 0xFE65
748#define REG_USB_PHY 0xFE66
749#define REG_USB_MAC_ADDR 0xFE70
750#define REG_USB_HRPWM 0xFE58
751#define REG_USB_HCPWM 0xFE57
752
753#define SW18_FPWM BIT(3)
754
755#define ISO_MD2PP BIT(0)
756#define ISO_UA2USB BIT(1)
757#define ISO_UD2CORE BIT(2)
758#define ISO_PA2PCIE BIT(3)
759#define ISO_PD2CORE BIT(4)
760#define ISO_IP2MAC BIT(5)
761#define ISO_DIOP BIT(6)
762#define ISO_DIOE BIT(7)
763#define ISO_EB2CORE BIT(8)
764#define ISO_DIOR BIT(9)
765
766#define PWC_EV25V BIT(14)
767#define PWC_EV12V BIT(15)
768
769#define FEN_BBRSTB BIT(0)
770#define FEN_BB_GLB_RSTN BIT(1)
771#define FEN_USBA BIT(2)
772#define FEN_UPLL BIT(3)
773#define FEN_USBD BIT(4)
774#define FEN_DIO_PCIE BIT(5)
775#define FEN_PCIEA BIT(6)
776#define FEN_PPLL BIT(7)
777#define FEN_PCIED BIT(8)
778#define FEN_DIOE BIT(9)
779#define FEN_CPUEN BIT(10)
780#define FEN_DCORE BIT(11)
781#define FEN_ELDR BIT(12)
782#define FEN_DIO_RF BIT(13)
783#define FEN_HWPDN BIT(14)
784#define FEN_MREGEN BIT(15)
785
786#define PFM_LDALL BIT(0)
787#define PFM_ALDN BIT(1)
788#define PFM_LDKP BIT(2)
789#define PFM_WOWL BIT(3)
790#define ENPDN BIT(4)
791#define PDN_PL BIT(5)
792#define APFM_ONMAC BIT(8)
793#define APFM_OFF BIT(9)
794#define APFM_RSM BIT(10)
795#define AFSM_HSUS BIT(11)
796#define AFSM_PCIE BIT(12)
797#define APDM_MAC BIT(13)
798#define APDM_HOST BIT(14)
799#define APDM_HPDN BIT(15)
800#define RDY_MACON BIT(16)
801#define SUS_HOST BIT(17)
802#define ROP_ALD BIT(20)
803#define ROP_PWR BIT(21)
804#define ROP_SPS BIT(22)
805#define SOP_MRST BIT(25)
806#define SOP_FUSE BIT(26)
807#define SOP_ABG BIT(27)
808#define SOP_AMB BIT(28)
809#define SOP_RCK BIT(29)
810#define SOP_A8M BIT(30)
811#define XOP_BTCK BIT(31)
812
813#define ANAD16V_EN BIT(0)
814#define ANA8M BIT(1)
815#define MACSLP BIT(4)
816#define LOADER_CLK_EN BIT(5)
817#define _80M_SSC_DIS BIT(7)
818#define _80M_SSC_EN_HO BIT(8)
819#define PHY_SSC_RSTB BIT(9)
820#define SEC_CLK_EN BIT(10)
821#define MAC_CLK_EN BIT(11)
822#define SYS_CLK_EN BIT(12)
823#define RING_CLK_EN BIT(13)
824
825#define BOOT_FROM_EEPROM BIT(4)
826#define EEPROM_EN BIT(5)
827
828#define AFE_BGEN BIT(0)
829#define AFE_MBEN BIT(1)
830#define MAC_ID_EN BIT(7)
831
832#define WLOCK_ALL BIT(0)
833#define WLOCK_00 BIT(1)
834#define WLOCK_04 BIT(2)
835#define WLOCK_08 BIT(3)
836#define WLOCK_40 BIT(4)
837#define R_DIS_PRST_0 BIT(5)
838#define R_DIS_PRST_1 BIT(6)
839#define LOCK_ALL_EN BIT(7)
840
841#define RF_EN BIT(0)
842#define RF_RSTB BIT(1)
843#define RF_SDMRSTB BIT(2)
844
845#define LDA15_EN BIT(0)
846#define LDA15_STBY BIT(1)
847#define LDA15_OBUF BIT(2)
848#define LDA15_REG_VOS BIT(3)
849#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
850
851#define LDV12_EN BIT(0)
852#define LDV12_SDBY BIT(1)
853#define LPLDO_HSM BIT(2)
854#define LPLDO_LSM_DIS BIT(3)
855#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
856
857#define XTAL_EN BIT(0)
858#define XTAL_BSEL BIT(1)
859#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
860#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
861#define XTAL_GATE_USB BIT(8)
862#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
863#define XTAL_GATE_AFE BIT(11)
864#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
865#define XTAL_RF_GATE BIT(14)
866#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
867#define XTAL_GATE_DIG BIT(17)
868#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
869#define XTAL_BT_GATE BIT(20)
870#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
871#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
872
873#define CKDLY_AFE BIT(26)
874#define CKDLY_USB BIT(27)
875#define CKDLY_DIG BIT(28)
876#define CKDLY_BT BIT(29)
877
878#define APLL_EN BIT(0)
879#define APLL_320_EN BIT(1)
880#define APLL_FREF_SEL BIT(2)
881#define APLL_EDGE_SEL BIT(3)
882#define APLL_WDOGB BIT(4)
883#define APLL_LPFEN BIT(5)
884
885#define APLL_REF_CLK_13MHZ 0x1
886#define APLL_REF_CLK_19_2MHZ 0x2
887#define APLL_REF_CLK_20MHZ 0x3
888#define APLL_REF_CLK_25MHZ 0x4
889#define APLL_REF_CLK_26MHZ 0x5
890#define APLL_REF_CLK_38_4MHZ 0x6
891#define APLL_REF_CLK_40MHZ 0x7
892
893#define APLL_320EN BIT(14)
894#define APLL_80EN BIT(15)
895#define APLL_1MEN BIT(24)
896
897#define ALD_EN BIT(18)
898#define EF_PD BIT(19)
899#define EF_FLAG BIT(31)
900
901#define EF_TRPT BIT(7)
902#define LDOE25_EN BIT(31)
903
904#define RSM_EN BIT(0)
905#define TIMER_EN BIT(4)
906
907#define TRSW0EN BIT(2)
908#define TRSW1EN BIT(3)
909#define EROM_EN BIT(4)
910#define ENBT BIT(5)
911#define ENUART BIT(8)
912#define UART_910 BIT(9)
913#define ENPMAC BIT(10)
914#define SIC_SWRST BIT(11)
915#define ENSIC BIT(12)
916#define SIC_23 BIT(13)
917#define ENHDP BIT(14)
918#define SIC_LBK BIT(15)
919
920#define LED0PL BIT(4)
921#define LED1PL BIT(12)
922#define LED0DIS BIT(7)
923
924#define MCUFWDL_EN BIT(0)
925#define MCUFWDL_RDY BIT(1)
926#define FWDL_CHKSUM_RPT BIT(2)
927#define MACINI_RDY BIT(3)
928#define BBINI_RDY BIT(4)
929#define RFINI_RDY BIT(5)
930#define WINTINI_RDY BIT(6)
931#define CPRST BIT(23)
932
933#define XCLK_VLD BIT(0)
934#define ACLK_VLD BIT(1)
935#define UCLK_VLD BIT(2)
936#define PCLK_VLD BIT(3)
937#define PCIRSTB BIT(4)
938#define V15_VLD BIT(5)
939#define TRP_B15V_EN BIT(7)
940#define SIC_IDLE BIT(8)
941#define BD_MAC2 BIT(9)
942#define BD_MAC1 BIT(10)
943#define IC_MACPHY_MODE BIT(11)
944#define VENDOR_ID BIT(19)
945#define PAD_HWPD_IDN BIT(22)
946#define TRP_VAUX_EN BIT(23)
947#define TRP_BT_EN BIT(24)
948#define BD_PKG_SEL BIT(25)
949#define BD_HCI_SEL BIT(26)
950#define TYPE_ID BIT(27)
951
952#define CHIP_VER_RTL_MASK 0xF000
953#define CHIP_VER_RTL_SHIFT 12
954
955#define REG_LBMODE (REG_CR + 3)
956
957#define HCI_TXDMA_EN BIT(0)
958#define HCI_RXDMA_EN BIT(1)
959#define TXDMA_EN BIT(2)
960#define RXDMA_EN BIT(3)
961#define PROTOCOL_EN BIT(4)
962#define SCHEDULE_EN BIT(5)
963#define MACTXEN BIT(6)
964#define MACRXEN BIT(7)
965#define ENSWBCN BIT(8)
966#define ENSEC BIT(9)
967
968#define _NETTYPE(x) (((x) & 0x3) << 16)
969#define MASK_NETTYPE 0x30000
970#define NT_NO_LINK 0x0
971#define NT_LINK_AD_HOC 0x1
972#define NT_LINK_AP 0x2
973#define NT_AS_AP 0x3
974
975#define _LBMODE(x) (((x) & 0xF) << 24)
976#define MASK_LBMODE 0xF000000
977#define LOOPBACK_NORMAL 0x0
978#define LOOPBACK_IMMEDIATELY 0xB
979#define LOOPBACK_MAC_DELAY 0x3
980#define LOOPBACK_PHY 0x1
981#define LOOPBACK_DMA 0x7
982
983#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
984#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
985#define _PSRX_MASK 0xF
986#define _PSTX_MASK 0xF0
987#define _PSRX(x) (x)
988#define _PSTX(x) ((x) << 4)
989
990#define PBP_64 0x0
991#define PBP_128 0x1
992#define PBP_256 0x2
993#define PBP_512 0x3
994#define PBP_1024 0x4
995
996#define RXDMA_ARBBW_EN BIT(0)
997#define RXSHFT_EN BIT(1)
998#define RXDMA_AGG_EN BIT(2)
999#define QS_VO_QUEUE BIT(8)
1000#define QS_VI_QUEUE BIT(9)
1001#define QS_BE_QUEUE BIT(10)
1002#define QS_BK_QUEUE BIT(11)
1003#define QS_MANAGER_QUEUE BIT(12)
1004#define QS_HIGH_QUEUE BIT(13)
1005
1006#define HQSEL_VOQ BIT(0)
1007#define HQSEL_VIQ BIT(1)
1008#define HQSEL_BEQ BIT(2)
1009#define HQSEL_BKQ BIT(3)
1010#define HQSEL_MGTQ BIT(4)
1011#define HQSEL_HIQ BIT(5)
1012
1013#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
1014#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
1015#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
1016#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)
1017#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)
1018#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)
1019
1020#define QUEUE_LOW 1
1021#define QUEUE_NORMAL 2
1022#define QUEUE_HIGH 3
1023
1024#define _LLT_NO_ACTIVE 0x0
1025#define _LLT_WRITE_ACCESS 0x1
1026#define _LLT_READ_ACCESS 0x2
1027
1028#define _LLT_INIT_DATA(x) ((x) & 0xFF)
1029#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
1030#define _LLT_OP(x) (((x) & 0x3) << 30)
1031#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
1032
1033#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
1034#define BB_WRITE_EN BIT(30)
1035#define BB_READ_EN BIT(31)
1036
1037#define _HPQ(x) ((x) & 0xFF)
1038#define _LPQ(x) (((x) & 0xFF) << 8)
1039#define _PUBQ(x) (((x) & 0xFF) << 16)
1040#define _NPQ(x) ((x) & 0xFF)
1041
1042#define HPQ_PUBLIC_DIS BIT(24)
1043#define LPQ_PUBLIC_DIS BIT(25)
1044#define LD_RQPN BIT(31)
1045
1046#define BCN_VALID BIT(16)
1047#define BCN_HEAD(x) (((x) & 0xFF) << 8)
1048#define BCN_HEAD_MASK 0xFF00
1049
1050#define BLK_DESC_NUM_SHIFT 4
1051#define BLK_DESC_NUM_MASK 0xF
1052
1053#define DROP_DATA_EN BIT(9)
1054
1055#define EN_AMPDU_RTY_NEW BIT(7)
1056
1057#define _INIRTSMCS_SEL(x) ((x) & 0x3F)
1058
1059#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
1060#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
1061
1062#define RATE_REG_BITMAP_ALL 0xFFFFF
1063
1064#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
1065
1066#define _RRSR_RSC(x) (((x) & 0x3) << 21)
1067#define RRSR_RSC_RESERVED 0x0
1068#define RRSR_RSC_UPPER_SUBCHANNEL 0x1
1069#define RRSR_RSC_LOWER_SUBCHANNEL 0x2
1070#define RRSR_RSC_DUPLICATE_MODE 0x3
1071
1072#define USE_SHORT_G1 BIT(20)
1073
1074#define _AGGLMT_MCS0(x) ((x) & 0xF)
1075#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
1076#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
1077#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
1078#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
1079#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
1080#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
1081#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
1082
1083#define RETRY_LIMIT_SHORT_SHIFT 8
1084#define RETRY_LIMIT_LONG_SHIFT 0
1085
1086#define _DARF_RC1(x) ((x) & 0x1F)
1087#define _DARF_RC2(x) (((x) & 0x1F) << 8)
1088#define _DARF_RC3(x) (((x) & 0x1F) << 16)
1089#define _DARF_RC4(x) (((x) & 0x1F) << 24)
1090#define _DARF_RC5(x) ((x) & 0x1F)
1091#define _DARF_RC6(x) (((x) & 0x1F) << 8)
1092#define _DARF_RC7(x) (((x) & 0x1F) << 16)
1093#define _DARF_RC8(x) (((x) & 0x1F) << 24)
1094
1095#define _RARF_RC1(x) ((x) & 0x1F)
1096#define _RARF_RC2(x) (((x) & 0x1F) << 8)
1097#define _RARF_RC3(x) (((x) & 0x1F) << 16)
1098#define _RARF_RC4(x) (((x) & 0x1F) << 24)
1099#define _RARF_RC5(x) ((x) & 0x1F)
1100#define _RARF_RC6(x) (((x) & 0x1F) << 8)
1101#define _RARF_RC7(x) (((x) & 0x1F) << 16)
1102#define _RARF_RC8(x) (((x) & 0x1F) << 24)
1103
1104#define AC_PARAM_TXOP_LIMIT_OFFSET 16
1105#define AC_PARAM_ECW_MAX_OFFSET 12
1106#define AC_PARAM_ECW_MIN_OFFSET 8
1107#define AC_PARAM_AIFS_OFFSET 0
1108
1109#define _AIFS(x) (x)
1110#define _ECW_MAX_MIN(x) ((x) << 8)
1111#define _TXOP_LIMIT(x) ((x) << 16)
1112
1113#define _BCNIFS(x) ((x) & 0xFF)
1114#define _BCNECW(x) ((((x) & 0xF)) << 8)
1115
1116#define _LRL(x) ((x) & 0x3F)
1117#define _SRL(x) (((x) & 0x3F) << 8)
1118
1119#define _SIFS_CCK_CTX(x) ((x) & 0xFF)
1120#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8);
1121
1122#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
1123#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8);
1124
1125#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
1126
1127#define DIS_EDCA_CNT_DWN BIT(11)
1128
1129#define EN_MBSSID BIT(1)
1130#define EN_TXBCN_RPT BIT(2)
1131#define EN_BCN_FUNCTION BIT(3)
1132
1133#define TSFTR_RST BIT(0)
1134#define TSFTR1_RST BIT(1)
1135
1136#define STOP_BCNQ BIT(6)
1137
1138#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
1139#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
1140
1141#define ACMHW_HWEN BIT(0)
1142#define ACMHW_BEQEN BIT(1)
1143#define ACMHW_VIQEN BIT(2)
1144#define ACMHW_VOQEN BIT(3)
1145#define ACMHW_BEQSTATUS BIT(4)
1146#define ACMHW_VIQSTATUS BIT(5)
1147#define ACMHW_VOQSTATUS BIT(6)
1148
1149#define APSDOFF BIT(6)
1150#define APSDOFF_STATUS BIT(7)
1151
1152#define BW_20MHZ BIT(2)
1153
1154#define RATE_BITMAP_ALL 0xFFFFF
1155
1156#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
1157
1158#define TSFRST BIT(0)
1159#define DIS_GCLK BIT(1)
1160#define PAD_SEL BIT(2)
1161#define PWR_ST BIT(6)
1162#define PWRBIT_OW_EN BIT(7)
1163#define ACRC BIT(8)
1164#define CFENDFORM BIT(9)
1165#define ICV BIT(10)
1166
1167#define AAP BIT(0)
1168#define APM BIT(1)
1169#define AM BIT(2)
1170#define AB BIT(3)
1171#define ADD3 BIT(4)
1172#define APWRMGT BIT(5)
1173#define CBSSID BIT(6)
1174#define CBSSID_DATA BIT(6)
1175#define CBSSID_BCN BIT(7)
1176#define ACRC32 BIT(8)
1177#define AICV BIT(9)
1178#define ADF BIT(11)
1179#define ACF BIT(12)
1180#define AMF BIT(13)
1181#define HTC_LOC_CTRL BIT(14)
1182#define UC_DATA_EN BIT(16)
1183#define BM_DATA_EN BIT(17)
1184#define MFBEN BIT(22)
1185#define LSIGEN BIT(23)
1186#define ENMBID BIT(24)
1187#define APP_BASSN BIT(27)
1188#define APP_PHYSTS BIT(28)
1189#define APP_ICV BIT(29)
1190#define APP_MIC BIT(30)
1191#define APP_FCS BIT(31)
1192
1193#define _MIN_SPACE(x) ((x) & 0x7)
1194#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
1195
1196#define RXERR_TYPE_OFDM_PPDU 0
1197#define RXERR_TYPE_OFDM_FALSE_ALARM 1
1198#define RXERR_TYPE_OFDM_MPDU_OK 2
1199#define RXERR_TYPE_OFDM_MPDU_FAIL 3
1200#define RXERR_TYPE_CCK_PPDU 4
1201#define RXERR_TYPE_CCK_FALSE_ALARM 5
1202#define RXERR_TYPE_CCK_MPDU_OK 6
1203#define RXERR_TYPE_CCK_MPDU_FAIL 7
1204#define RXERR_TYPE_HT_PPDU 8
1205#define RXERR_TYPE_HT_FALSE_ALARM 9
1206#define RXERR_TYPE_HT_MPDU_TOTAL 10
1207#define RXERR_TYPE_HT_MPDU_OK 11
1208#define RXERR_TYPE_HT_MPDU_FAIL 12
1209#define RXERR_TYPE_RX_FULL_DROP 15
1210
1211#define RXERR_COUNTER_MASK 0xFFFFF
1212#define RXERR_RPT_RST BIT(27)
1213#define _RXERR_RPT_SEL(type) ((type) << 28)
1214
1215#define SCR_TXUSEDK BIT(0)
1216#define SCR_RXUSEDK BIT(1)
1217#define SCR_TXENCENABLE BIT(2)
1218#define SCR_RXDECENABLE BIT(3)
1219#define SCR_SKBYA2 BIT(4)
1220#define SCR_NOSKMC BIT(5)
1221#define SCR_TXBCUSEDK BIT(6)
1222#define SCR_RXBCUSEDK BIT(7)
1223
1224#define USB_IS_HIGH_SPEED 0
1225#define USB_IS_FULL_SPEED 1
1226#define USB_SPEED_MASK BIT(5)
1227
1228#define USB_NORMAL_SIE_EP_MASK 0xF
1229#define USB_NORMAL_SIE_EP_SHIFT 4
1230
1231#define USB_TEST_EP_MASK 0x30
1232#define USB_TEST_EP_SHIFT 4
1233
1234#define USB_AGG_EN BIT(3)
1235
1236#define MAC_ADDR_LEN 6
1237#define LAST_ENTRY_OF_TX_PKT_BUFFER 175/*255 88e*/
1238
1239#define POLLING_LLT_THRESHOLD 20
1240#define POLLING_READY_TIMEOUT_COUNT 3000
1241
1242#define MAX_MSS_DENSITY_2T 0x13
1243#define MAX_MSS_DENSITY_1T 0x0A
1244
1245#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
1246#define EPROM_CMD_CONFIG 0x3
1247#define EPROM_CMD_LOAD 1
1248
1249#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE
1250
1251#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1252
1253#define RPMAC_RESET 0x100
1254#define RPMAC_TXSTART 0x104
1255#define RPMAC_TXLEGACYSIG 0x108
1256#define RPMAC_TXHTSIG1 0x10c
1257#define RPMAC_TXHTSIG2 0x110
1258#define RPMAC_PHYDEBUG 0x114
1259#define RPMAC_TXPACKETNUM 0x118
1260#define RPMAC_TXIDLE 0x11c
1261#define RPMAC_TXMACHEADER0 0x120
1262#define RPMAC_TXMACHEADER1 0x124
1263#define RPMAC_TXMACHEADER2 0x128
1264#define RPMAC_TXMACHEADER3 0x12c
1265#define RPMAC_TXMACHEADER4 0x130
1266#define RPMAC_TXMACHEADER5 0x134
1267#define RPMAC_TXDADATYPE 0x138
1268#define RPMAC_TXRANDOMSEED 0x13c
1269#define RPMAC_CCKPLCPPREAMBLE 0x140
1270#define RPMAC_CCKPLCPHEADER 0x144
1271#define RPMAC_CCKCRC16 0x148
1272#define RPMAC_OFDMRXCRC32OK 0x170
1273#define RPMAC_OFDMRXCRC32Er 0x174
1274#define RPMAC_OFDMRXPARITYER 0x178
1275#define RPMAC_OFDMRXCRC8ER 0x17c
1276#define RPMAC_CCKCRXRC16ER 0x180
1277#define RPMAC_CCKCRXRC32ER 0x184
1278#define RPMAC_CCKCRXRC32OK 0x188
1279#define RPMAC_TXSTATUS 0x18c
1280
1281#define RFPGA0_RFMOD 0x800
1282
1283#define RFPGA0_TXINFO 0x804
1284#define RFPGA0_PSDFUNCTION 0x808
1285
1286#define RFPGA0_TXGAINSTAGE 0x80c
1287
1288#define RFPGA0_RFTIMING1 0x810
1289#define RFPGA0_RFTIMING2 0x814
1290
1291#define RFPGA0_XA_HSSIPARAMETER1 0x820
1292#define RFPGA0_XA_HSSIPARAMETER2 0x824
1293#define RFPGA0_XB_HSSIPARAMETER1 0x828
1294#define RFPGA0_XB_HSSIPARAMETER2 0x82c
1295
1296#define RFPGA0_XA_LSSIPARAMETER 0x840
1297#define RFPGA0_XB_LSSIPARAMETER 0x844
1298
1299#define RFPGA0_RFWAKEUPPARAMETER 0x850
1300#define RFPGA0_RFSLEEPUPPARAMETER 0x854
1301
1302#define RFPGA0_XAB_SWITCHCONTROL 0x858
1303#define RFPGA0_XCD_SWITCHCONTROL 0x85c
1304
1305#define RFPGA0_XA_RFINTERFACEOE 0x860
1306#define RFPGA0_XB_RFINTERFACEOE 0x864
1307
1308#define RFPGA0_XAB_RFINTERFACESW 0x870
1309#define RFPGA0_XCD_RFINTERFACESW 0x874
1310
1311#define rFPGA0_XAB_RFPARAMETER 0x878
1312#define rFPGA0_XCD_RFPARAMETER 0x87c
1313
1314#define RFPGA0_ANALOGPARAMETER1 0x880
1315#define RFPGA0_ANALOGPARAMETER2 0x884
1316#define RFPGA0_ANALOGPARAMETER3 0x888
1317#define RFPGA0_ANALOGPARAMETER4 0x88c
1318
1319#define RFPGA0_XA_LSSIREADBACK 0x8a0
1320#define RFPGA0_XB_LSSIREADBACK 0x8a4
1321#define RFPGA0_XC_LSSIREADBACK 0x8a8
1322#define RFPGA0_XD_LSSIREADBACK 0x8ac
1323
1324#define RFPGA0_PSDREPORT 0x8b4
1325#define TRANSCEIVEA_HSPI_READBACK 0x8b8
1326#define TRANSCEIVEB_HSPI_READBACK 0x8bc
1327#define REG_SC_CNT 0x8c4
1328#define RFPGA0_XAB_RFINTERFACERB 0x8e0
1329#define RFPGA0_XCD_RFINTERFACERB 0x8e4
1330
1331#define RFPGA1_RFMOD 0x900
1332
1333#define RFPGA1_TXBLOCK 0x904
1334#define RFPGA1_DEBUGSELECT 0x908
1335#define RFPGA1_TXINFO 0x90c
1336
1337#define RCCK0_SYSTEM 0xa00
1338
1339#define RCCK0_AFESETTING 0xa04
1340#define RCCK0_CCA 0xa08
1341
1342#define RCCK0_RXAGC1 0xa0c
1343#define RCCK0_RXAGC2 0xa10
1344
1345#define RCCK0_RXHP 0xa14
1346
1347#define RCCK0_DSPPARAMETER1 0xa18
1348#define RCCK0_DSPPARAMETER2 0xa1c
1349
1350#define RCCK0_TXFILTER1 0xa20
1351#define RCCK0_TXFILTER2 0xa24
1352#define RCCK0_DEBUGPORT 0xa28
1353#define RCCK0_FALSEALARMREPORT 0xa2c
1354#define RCCK0_TRSSIREPORT 0xa50
1355#define RCCK0_RXREPORT 0xa54
1356#define RCCK0_FACOUNTERLOWER 0xa5c
1357#define RCCK0_FACOUNTERUPPER 0xa58
1358#define RCCK0_CCA_CNT 0xa60
1359
1360
1361/* PageB(0xB00) */
1362#define RPDP_ANTA 0xb00
1363#define RPDP_ANTA_4 0xb04
1364#define RPDP_ANTA_8 0xb08
1365#define RPDP_ANTA_C 0xb0c
1366#define RPDP_ANTA_10 0xb10
1367#define RPDP_ANTA_14 0xb14
1368#define RPDP_ANTA_18 0xb18
1369#define RPDP_ANTA_1C 0xb1c
1370#define RPDP_ANTA_20 0xb20
1371#define RPDP_ANTA_24 0xb24
1372
1373#define RCONFIG_PMPD_ANTA 0xb28
1374#define RCONFIG_RAM64X16 0xb2c
1375
1376#define RBNDA 0xb30
1377#define RHSSIPAR 0xb34
1378
1379#define RCONFIG_ANTA 0xb68
1380#define RCONFIG_ANTB 0xb6c
1381
1382#define RPDP_ANTB 0xb70
1383#define RPDP_ANTB_4 0xb74
1384#define RPDP_ANTB_8 0xb78
1385#define RPDP_ANTB_C 0xb7c
1386#define RPDP_ANTB_10 0xb80
1387#define RPDP_ANTB_14 0xb84
1388#define RPDP_ANTB_18 0xb88
1389#define RPDP_ANTB_1C 0xb8c
1390#define RPDP_ANTB_20 0xb90
1391#define RPDP_ANTB_24 0xb94
1392
1393#define RCONFIG_PMPD_ANTB 0xb98
1394
1395#define RBNDB 0xba0
1396
1397#define RAPK 0xbd8
1398#define rPm_Rx0_AntA 0xbdc
1399#define rPm_Rx1_AntA 0xbe0
1400#define rPm_Rx2_AntA 0xbe4
1401#define rPm_Rx3_AntA 0xbe8
1402#define rPm_Rx0_AntB 0xbec
1403#define rPm_Rx1_AntB 0xbf0
1404#define rPm_Rx2_AntB 0xbf4
1405#define rPm_Rx3_AntB 0xbf8
1406
1407/*Page C*/
1408#define ROFDM0_LSTF 0xc00
1409
1410#define ROFDM0_TRXPATHENABLE 0xc04
1411#define ROFDM0_TRMUXPAR 0xc08
1412#define ROFDM0_TRSWISOLATION 0xc0c
1413
1414#define ROFDM0_XARXAFE 0xc10
1415#define ROFDM0_XARXIQIMBAL 0xc14
1416#define ROFDM0_XBRXAFE 0xc18
1417#define ROFDM0_XBRXIQIMBAL 0xc1c
1418#define ROFDM0_XCRXAFE 0xc20
1419#define ROFDM0_XCRXIQIMBAL 0xc24
1420#define ROFDM0_XDRXAFE 0xc28
1421#define ROFDM0_XDRXIQIMBAL 0xc2c
1422
1423#define ROFDM0_RXDETECTOR1 0xc30
1424#define ROFDM0_RXDETECTOR2 0xc34
1425#define ROFDM0_RXDETECTOR3 0xc38
1426#define ROFDM0_RXDETECTOR4 0xc3c
1427
1428#define ROFDM0_RXDSP 0xc40
1429#define ROFDM0_CFOANDDAGC 0xc44
1430#define ROFDM0_CCADROPTHRES 0xc48
1431#define ROFDM0_ECCATHRES 0xc4c
1432
1433#define ROFDM0_XAAGCCORE1 0xc50
1434#define ROFDM0_XAAGCCORE2 0xc54
1435#define ROFDM0_XBAGCCORE1 0xc58
1436#define ROFDM0_XBAGCCORE2 0xc5c
1437#define ROFDM0_XCAGCCORE1 0xc60
1438#define ROFDM0_XCAGCCORE2 0xc64
1439#define ROFDM0_XDAGCCORE1 0xc68
1440#define ROFDM0_XDAGCCORE2 0xc6c
1441
1442#define ROFDM0_AGCPARAMETER1 0xc70
1443#define ROFDM0_AGCPARAMETER2 0xc74
1444#define ROFDM0_AGCRSSITABLE 0xc78
1445#define ROFDM0_HTSTFAGC 0xc7c
1446
1447#define ROFDM0_XATXIQIMBAL 0xc80
1448#define ROFDM0_XATXAFE 0xc84
1449#define ROFDM0_XBTXIQIMBAL 0xc88
1450#define ROFDM0_XBTXAFE 0xc8c
1451#define ROFDM0_XCTXIQIMBAL 0xc90
1452#define ROFDM0_XCTXAFE 0xc94
1453#define ROFDM0_XDTXIQIMBAL 0xc98
1454#define ROFDM0_XDTXAFE 0xc9c
1455
1456#define ROFDM0_RXIQEXTANTA 0xca0
1457#define ROFDM0_TXCOEFF1 0xca4
1458#define ROFDM0_TXCOEFF2 0xca8
1459#define ROFDM0_TXCOEFF3 0xcac
1460#define ROFDM0_TXCOEFF4 0xcb0
1461#define ROFDM0_TXCOEFF5 0xcb4
1462#define ROFDM0_TXCOEFF6 0xcb8
1463
1464#define ROFDM0_RXHPPARAMETER 0xce0
1465#define ROFDM0_TXPSEUDONOISEWGT 0xce4
1466#define ROFDM0_FRAMESYNC 0xcf0
1467#define ROFDM0_DFSREPORT 0xcf4
1468
1469
1470#define ROFDM1_LSTF 0xd00
1471#define ROFDM1_TRXPATHENABLE 0xd04
1472
1473#define ROFDM1_CF0 0xd08
1474#define ROFDM1_CSI1 0xd10
1475#define ROFDM1_SBD 0xd14
1476#define ROFDM1_CSI2 0xd18
1477#define ROFDM1_CFOTRACKING 0xd2c
1478#define ROFDM1_TRXMESAURE1 0xd34
1479#define ROFDM1_INTFDET 0xd3c
1480#define ROFDM1_PSEUDONOISESTATEAB 0xd50
1481#define ROFDM1_PSEUDONOISESTATECD 0xd54
1482#define ROFDM1_RXPSEUDONOISEWGT 0xd58
1483
1484#define ROFDM_PHYCOUNTER1 0xda0
1485#define ROFDM_PHYCOUNTER2 0xda4
1486#define ROFDM_PHYCOUNTER3 0xda8
1487
1488#define ROFDM_SHORTCFOAB 0xdac
1489#define ROFDM_SHORTCFOCD 0xdb0
1490#define ROFDM_LONGCFOAB 0xdb4
1491#define ROFDM_LONGCFOCD 0xdb8
1492#define ROFDM_TAILCF0AB 0xdbc
1493#define ROFDM_TAILCF0CD 0xdc0
1494#define ROFDM_PWMEASURE1 0xdc4
1495#define ROFDM_PWMEASURE2 0xdc8
1496#define ROFDM_BWREPORT 0xdcc
1497#define ROFDM_AGCREPORT 0xdd0
1498#define ROFDM_RXSNR 0xdd4
1499#define ROFDM_RXEVMCSI 0xdd8
1500#define ROFDM_SIGREPORT 0xddc
1501
1502#define RTXAGC_A_RATE18_06 0xe00
1503#define RTXAGC_A_RATE54_24 0xe04
1504#define RTXAGC_A_CCK1_MCS32 0xe08
1505#define RTXAGC_A_MCS03_MCS00 0xe10
1506#define RTXAGC_A_MCS07_MCS04 0xe14
1507#define RTXAGC_A_MCS11_MCS08 0xe18
1508#define RTXAGC_A_MCS15_MCS12 0xe1c
1509
1510#define RTXAGC_B_RATE18_06 0x830
1511#define RTXAGC_B_RATE54_24 0x834
1512#define RTXAGC_B_CCK1_55_MCS32 0x838
1513#define RTXAGC_B_MCS03_MCS00 0x83c
1514#define RTXAGC_B_MCS07_MCS04 0x848
1515#define RTXAGC_B_MCS11_MCS08 0x84c
1516#define RTXAGC_B_MCS15_MCS12 0x868
1517#define RTXAGC_B_CCK11_A_CCK2_11 0x86c
1518
1519#define RFPGA0_IQK 0xe28
1520#define RTX_IQK_TONE_A 0xe30
1521#define RRX_IQK_TONE_A 0xe34
1522#define RTX_IQK_PI_A 0xe38
1523#define RRX_IQK_PI_A 0xe3c
1524
1525#define RTX_IQK 0xe40
1526#define RRX_IQK 0xe44
1527#define RIQK_AGC_PTS 0xe48
1528#define RIQK_AGC_RSP 0xe4c
1529#define RTX_IQK_TONE_B 0xe50
1530#define RRX_IQK_TONE_B 0xe54
1531#define RTX_IQK_PI_B 0xe58
1532#define RRX_IQK_PI_B 0xe5c
1533#define RIQK_AGC_CONT 0xe60
1534
1535#define RBLUE_TOOTH 0xe6c
1536#define RRX_WAIT_CCA 0xe70
1537#define RTX_CCK_RFON 0xe74
1538#define RTX_CCK_BBON 0xe78
1539#define RTX_OFDM_RFON 0xe7c
1540#define RTX_OFDM_BBON 0xe80
1541#define RTX_TO_RX 0xe84
1542#define RTX_TO_TX 0xe88
1543#define RRX_CCK 0xe8c
1544
1545#define RTX_POWER_BEFORE_IQK_A 0xe94
1546#define RTX_POWER_AFTER_IQK_A 0xe9c
1547
1548#define RRX_POWER_BEFORE_IQK_A 0xea0
1549#define RRX_POWER_BEFORE_IQK_A_2 0xea4
1550#define RRX_POWER_AFTER_IQK_A 0xea8
1551#define RRX_POWER_AFTER_IQK_A_2 0xeac
1552
1553#define RTX_POWER_BEFORE_IQK_B 0xeb4
1554#define RTX_POWER_AFTER_IQK_B 0xebc
1555
1556#define RRX_POWER_BEFORE_IQK_B 0xec0
1557#define RRX_POWER_BEFORE_IQK_B_2 0xec4
1558#define RRX_POWER_AFTER_IQK_B 0xec8
1559#define RRX_POWER_AFTER_IQK_B_2 0xecc
1560
1561#define RRX_OFDM 0xed0
1562#define RRX_WAIT_RIFS 0xed4
1563#define RRX_TO_RX 0xed8
1564#define RSTANDBY 0xedc
1565#define RSLEEP 0xee0
1566#define RPMPD_ANAEN 0xeec
1567
1568#define RZEBRA1_HSSIENABLE 0x0
1569#define RZEBRA1_TRXENABLE1 0x1
1570#define RZEBRA1_TRXENABLE2 0x2
1571#define RZEBRA1_AGC 0x4
1572#define RZEBRA1_CHARGEPUMP 0x5
1573#define RZEBRA1_CHANNEL 0x7
1574
1575#define RZEBRA1_TXGAIN 0x8
1576#define RZEBRA1_TXLPF 0x9
1577#define RZEBRA1_RXLPF 0xb
1578#define RZEBRA1_RXHPFCORNER 0xc
1579
1580#define RGLOBALCTRL 0
1581#define RRTL8256_TXLPF 19
1582#define RRTL8256_RXLPF 11
1583#define RRTL8258_TXLPF 0x11
1584#define RRTL8258_RXLPF 0x13
1585#define RRTL8258_RSSILPF 0xa
1586
1587#define RF_AC 0x00
1588
1589#define RF_IQADJ_G1 0x01
1590#define RF_IQADJ_G2 0x02
1591#define RF_POW_TRSW 0x05
1592
1593#define RF_GAIN_RX 0x06
1594#define RF_GAIN_TX 0x07
1595
1596#define RF_TXM_IDAC 0x08
1597#define RF_BS_IQGEN 0x0F
1598
1599#define RF_MODE1 0x10
1600#define RF_MODE2 0x11
1601
1602#define RF_RX_AGC_HP 0x12
1603#define RF_TX_AGC 0x13
1604#define RF_BIAS 0x14
1605#define RF_IPA 0x15
1606#define RF_POW_ABILITY 0x17
1607#define RF_MODE_AG 0x18
1608#define RRFCHANNEL 0x18
1609#define RF_CHNLBW 0x18
1610#define RF_TOP 0x19
1611
1612#define RF_RX_G1 0x1A
1613#define RF_RX_G2 0x1B
1614
1615#define RF_RX_BB2 0x1C
1616#define RF_RX_BB1 0x1D
1617
1618#define RF_RCK1 0x1E
1619#define RF_RCK2 0x1F
1620
1621#define RF_TX_G1 0x20
1622#define RF_TX_G2 0x21
1623#define RF_TX_G3 0x22
1624
1625#define RF_TX_BB1 0x23
1626#define RF_T_METER 0x42
1627
1628#define RF_SYN_G1 0x25
1629#define RF_SYN_G2 0x26
1630#define RF_SYN_G3 0x27
1631#define RF_SYN_G4 0x28
1632#define RF_SYN_G5 0x29
1633#define RF_SYN_G6 0x2A
1634#define RF_SYN_G7 0x2B
1635#define RF_SYN_G8 0x2C
1636
1637#define RF_RCK_OS 0x30
1638#define RF_TXPA_G1 0x31
1639#define RF_TXPA_G2 0x32
1640#define RF_TXPA_G3 0x33
1641
1642#define RF_TX_BIAS_A 0x35
1643#define RF_TX_BIAS_D 0x36
1644#define RF_LOBF_9 0x38
1645#define RF_RXRF_A3 0x3C
1646#define RF_TRSW 0x3F
1647
1648#define RF_TXRF_A2 0x41
1649#define RF_TXPA_G4 0x46
1650#define RF_TXPA_A4 0x4B
1651
1652#define RF_WE_LUT 0xEF
1653
1654#define BBBRESETB 0x100
1655#define BGLOBALRESETB 0x200
1656#define BOFDMTXSTART 0x4
1657#define BCCKTXSTART 0x8
1658#define BCRC32DEBUG 0x100
1659#define BPMACLOOPBACK 0x10
1660#define BTXLSIG 0xffffff
1661#define BOFDMTXRATE 0xf
1662#define BOFDMTXRESERVED 0x10
1663#define BOFDMTXLENGTH 0x1ffe0
1664#define BOFDMTXPARITY 0x20000
1665#define BTXHTSIG1 0xffffff
1666#define BTXHTMCSRATE 0x7f
1667#define BTXHTBW 0x80
1668#define BTXHTLENGTH 0xffff00
1669#define BTXHTSIG2 0xffffff
1670#define BTXHTSMOOTHING 0x1
1671#define BTXHTSOUNDING 0x2
1672#define BTXHTRESERVED 0x4
1673#define BTXHTAGGREATION 0x8
1674#define BTXHTSTBC 0x30
1675#define BTXHTADVANCECODING 0x40
1676#define BTXHTSHORTGI 0x80
1677#define BTXHTNUMBERHT_LTF 0x300
1678#define BTXHTCRC8 0x3fc00
1679#define BCOUNTERRESET 0x10000
1680#define BNUMOFOFDMTX 0xffff
1681#define BNUMOFCCKTX 0xffff0000
1682#define BTXIDLEINTERVAL 0xffff
1683#define BOFDMSERVICE 0xffff0000
1684#define BTXMACHEADER 0xffffffff
1685#define BTXDATAINIT 0xff
1686#define BTXHTMODE 0x100
1687#define BTXDATATYPE 0x30000
1688#define BTXRANDOMSEED 0xffffffff
1689#define BCCKTXPREAMBLE 0x1
1690#define BCCKTXSFD 0xffff0000
1691#define BCCKTXSIG 0xff
1692#define BCCKTXSERVICE 0xff00
1693#define BCCKLENGTHEXT 0x8000
1694#define BCCKTXLENGHT 0xffff0000
1695#define BCCKTXCRC16 0xffff
1696#define BCCKTXSTATUS 0x1
1697#define BOFDMTXSTATUS 0x2
1698#define IS_BB_REG_OFFSET_92S(_offset) \
1699 ((_offset >= 0x800) && (_offset <= 0xfff))
1700
1701#define BRFMOD 0x1
1702#define BJAPANMODE 0x2
1703#define BCCKTXSC 0x30
1704#define BCCKEN 0x1000000
1705#define BOFDMEN 0x2000000
1706
1707#define BOFDMRXADCPHASE 0x10000
1708#define BOFDMTXDACPHASE 0x40000
1709#define BXATXAGC 0x3f
1710
1711#define BXBTXAGC 0xf00
1712#define BXCTXAGC 0xf000
1713#define BXDTXAGC 0xf0000
1714
1715#define BPASTART 0xf0000000
1716#define BTRSTART 0x00f00000
1717#define BRFSTART 0x0000f000
1718#define BBBSTART 0x000000f0
1719#define BBBCCKSTART 0x0000000f
1720#define BPAEND 0xf
1721#define BTREND 0x0f000000
1722#define BRFEND 0x000f0000
1723#define BCCAMASK 0x000000f0
1724#define BR2RCCAMASK 0x00000f00
1725#define BHSSI_R2TDELAY 0xf8000000
1726#define BHSSI_T2RDELAY 0xf80000
1727#define BCONTXHSSI 0x400
1728#define BIGFROMCCK 0x200
1729#define BAGCADDRESS 0x3f
1730#define BRXHPTX 0x7000
1731#define BRXHP2RX 0x38000
1732#define BRXHPCCKINI 0xc0000
1733#define BAGCTXCODE 0xc00000
1734#define BAGCRXCODE 0x300000
1735
1736#define B3WIREDATALENGTH 0x800
1737#define B3WIREADDREAALENGTH 0x400
1738
1739#define B3WIRERFPOWERDOWN 0x1
1740#define B5GPAPEPOLARITY 0x40000000
1741#define B2GPAPEPOLARITY 0x80000000
1742#define BRFSW_TXDEFAULTANT 0x3
1743#define BRFSW_TXOPTIONANT 0x30
1744#define BRFSW_RXDEFAULTANT 0x300
1745#define BRFSW_RXOPTIONANT 0x3000
1746#define BRFSI_3WIREDATA 0x1
1747#define BRFSI_3WIRECLOCK 0x2
1748#define BRFSI_3WIRELOAD 0x4
1749#define BRFSI_3WIRERW 0x8
1750#define BRFSI_3WIRE 0xf
1751
1752#define BRFSI_RFENV 0x10
1753
1754#define BRFSI_TRSW 0x20
1755#define BRFSI_TRSWB 0x40
1756#define BRFSI_ANTSW 0x100
1757#define BRFSI_ANTSWB 0x200
1758#define BRFSI_PAPE 0x400
1759#define BRFSI_PAPE5G 0x800
1760#define BBANDSELECT 0x1
1761#define BHTSIG2_GI 0x80
1762#define BHTSIG2_SMOOTHING 0x01
1763#define BHTSIG2_SOUNDING 0x02
1764#define BHTSIG2_AGGREATON 0x08
1765#define BHTSIG2_STBC 0x30
1766#define BHTSIG2_ADVCODING 0x40
1767#define BHTSIG2_NUMOFHTLTF 0x300
1768#define BHTSIG2_CRC8 0x3fc
1769#define BHTSIG1_MCS 0x7f
1770#define BHTSIG1_BANDWIDTH 0x80
1771#define BHTSIG1_HTLENGTH 0xffff
1772#define BLSIG_RATE 0xf
1773#define BLSIG_RESERVED 0x10
1774#define BLSIG_LENGTH 0x1fffe
1775#define BLSIG_PARITY 0x20
1776#define BCCKRXPHASE 0x4
1777
1778#define BLSSIREADADDRESS 0x7f800000
1779#define BLSSIREADEDGE 0x80000000
1780
1781#define BLSSIREADBACKDATA 0xfffff
1782
1783#define BLSSIREADOKFLAG 0x1000
1784#define BCCKSAMPLERATE 0x8
1785#define BREGULATOR0STANDBY 0x1
1786#define BREGULATORPLLSTANDBY 0x2
1787#define BREGULATOR1STANDBY 0x4
1788#define BPLLPOWERUP 0x8
1789#define BDPLLPOWERUP 0x10
1790#define BDA10POWERUP 0x20
1791#define BAD7POWERUP 0x200
1792#define BDA6POWERUP 0x2000
1793#define BXTALPOWERUP 0x4000
1794#define B40MDCLKPOWERUP 0x8000
1795#define BDA6DEBUGMODE 0x20000
1796#define BDA6SWING 0x380000
1797
1798#define BADCLKPHASE 0x4000000
1799#define B80MCLKDELAY 0x18000000
1800#define BAFEWATCHDOGENABLE 0x20000000
1801
1802#define BXTALCAP01 0xc0000000
1803#define BXTALCAP23 0x3
1804#define BXTALCAP92X 0x0f000000
1805#define BXTALCAP 0x0f000000
1806
1807#define BINTDIFCLKENABLE 0x400
1808#define BEXTSIGCLKENABLE 0x800
1809#define BBANDGAP_MBIAS_POWERUP 0x10000
1810#define BAD11SH_GAIN 0xc0000
1811#define BAD11NPUT_RANGE 0x700000
1812#define BAD110P_CURRENT 0x3800000
1813#define BLPATH_LOOPBACK 0x4000000
1814#define BQPATH_LOOPBACK 0x8000000
1815#define BAFE_LOOPBACK 0x10000000
1816#define BDA10_SWING 0x7e0
1817#define BDA10_REVERSE 0x800
1818#define BDA_CLK_SOURCE 0x1000
1819#define BDA7INPUT_RANGE 0x6000
1820#define BDA7_GAIN 0x38000
1821#define BDA7OUTPUT_CM_MODE 0x40000
1822#define BDA7INPUT_CM_MODE 0x380000
1823#define BDA7CURRENT 0xc00000
1824#define BREGULATOR_ADJUST 0x7000000
1825#define BAD11POWERUP_ATTX 0x1
1826#define BDA10PS_ATTX 0x10
1827#define BAD11POWERUP_ATRX 0x100
1828#define BDA10PS_ATRX 0x1000
1829#define BCCKRX_AGC_FORMAT 0x200
1830#define BPSDFFT_SAMPLE_POINT 0xc000
1831#define BPSD_AVERAGE_NUM 0x3000
1832#define BIQPATH_CONTROL 0xc00
1833#define BPSD_FREQ 0x3ff
1834#define BPSD_ANTENNA_PATH 0x30
1835#define BPSD_IQ_SWITCH 0x40
1836#define BPSD_RX_TRIGGER 0x400000
1837#define BPSD_TX_TRIGGERCW 0x80000000
1838#define BPSD_SINE_TONE_SCALE 0x7f000000
1839#define BPSD_REPORT 0xffff
1840
1841#define BOFDM_TXSC 0x30000000
1842#define BCCK_TXON 0x1
1843#define BOFDM_TXON 0x2
1844#define BDEBUG_PAGE 0xfff
1845#define BDEBUG_ITEM 0xff
1846#define BANTL 0x10
1847#define BANT_NONHT 0x100
1848#define BANT_HT1 0x1000
1849#define BANT_HT2 0x10000
1850#define BANT_HT1S1 0x100000
1851#define BANT_NONHTS1 0x1000000
1852
1853#define BCCK_BBMODE 0x3
1854#define BCCK_TXPOWERSAVING 0x80
1855#define BCCK_RXPOWERSAVING 0x40
1856
1857#define BCCK_SIDEBAND 0x10
1858
1859#define BCCK_SCRAMBLE 0x8
1860#define BCCK_ANTDIVERSITY 0x8000
1861#define BCCK_CARRIER_RECOVERY 0x4000
1862#define BCCK_TXRATE 0x3000
1863#define BCCK_DCCANCEL 0x0800
1864#define BCCK_ISICANCEL 0x0400
1865#define BCCK_MATCH_FILTER 0x0200
1866#define BCCK_EQUALIZER 0x0100
1867#define BCCK_PREAMBLE_DETECT 0x800000
1868#define BCCK_FAST_FALSECCA 0x400000
1869#define BCCK_CH_ESTSTART 0x300000
1870#define BCCK_CCA_COUNT 0x080000
1871#define BCCK_CS_LIM 0x070000
1872#define BCCK_BIST_MODE 0x80000000
1873#define BCCK_CCAMASK 0x40000000
1874#define BCCK_TX_DAC_PHASE 0x4
1875#define BCCK_RX_ADC_PHASE 0x20000000
1876#define BCCKR_CP_MODE 0x0100
1877#define BCCK_TXDC_OFFSET 0xf0
1878#define BCCK_RXDC_OFFSET 0xf
1879#define BCCK_CCA_MODE 0xc000
1880#define BCCK_FALSECS_LIM 0x3f00
1881#define BCCK_CS_RATIO 0xc00000
1882#define BCCK_CORGBIT_SEL 0x300000
1883#define BCCK_PD_LIM 0x0f0000
1884#define BCCK_NEWCCA 0x80000000
1885#define BCCK_RXHP_OF_IG 0x8000
1886#define BCCK_RXIG 0x7f00
1887#define BCCK_LNA_POLARITY 0x800000
1888#define BCCK_RX1ST_BAIN 0x7f0000
1889#define BCCK_RF_EXTEND 0x20000000
1890#define BCCK_RXAGC_SATLEVEL 0x1f000000
1891#define BCCK_RXAGC_SATCOUNT 0xe0
1892#define BCCKRXRFSETTLE 0x1f
1893#define BCCK_FIXED_RXAGC 0x8000
1894#define BCCK_ANTENNA_POLARITY 0x2000
1895#define BCCK_TXFILTER_TYPE 0x0c00
1896#define BCCK_RXAGC_REPORTTYPE 0x0300
1897#define BCCK_RXDAGC_EN 0x80000000
1898#define BCCK_RXDAGC_PERIOD 0x20000000
1899#define BCCK_RXDAGC_SATLEVEL 0x1f000000
1900#define BCCK_TIMING_RECOVERY 0x800000
1901#define BCCK_TXC0 0x3f0000
1902#define BCCK_TXC1 0x3f000000
1903#define BCCK_TXC2 0x3f
1904#define BCCK_TXC3 0x3f00
1905#define BCCK_TXC4 0x3f0000
1906#define BCCK_TXC5 0x3f000000
1907#define BCCK_TXC6 0x3f
1908#define BCCK_TXC7 0x3f00
1909#define BCCK_DEBUGPORT 0xff0000
1910#define BCCK_DAC_DEBUG 0x0f000000
1911#define BCCK_FALSEALARM_ENABLE 0x8000
1912#define BCCK_FALSEALARM_READ 0x4000
1913#define BCCK_TRSSI 0x7f
1914#define BCCK_RXAGC_REPORT 0xfe
1915#define BCCK_RXREPORT_ANTSEL 0x80000000
1916#define BCCK_RXREPORT_MFOFF 0x40000000
1917#define BCCK_RXREPORT_SQLOSS 0x20000000
1918#define BCCK_RXREPORT_PKTLOSS 0x10000000
1919#define BCCK_RXREPORT_LOCKEDBIT 0x08000000
1920#define BCCK_RXREPORT_RATEERROR 0x04000000
1921#define BCCK_RXREPORT_RXRATE 0x03000000
1922#define BCCK_RXFA_COUNTER_LOWER 0xff
1923#define BCCK_RXFA_COUNTER_UPPER 0xff000000
1924#define BCCK_RXHPAGC_START 0xe000
1925#define BCCK_RXHPAGC_FINAL 0x1c00
1926#define BCCK_RXFALSEALARM_ENABLE 0x8000
1927#define BCCK_FACOUNTER_FREEZE 0x4000
1928#define BCCK_TXPATH_SEL 0x10000000
1929#define BCCK_DEFAULT_RXPATH 0xc000000
1930#define BCCK_OPTION_RXPATH 0x3000000
1931
1932#define BNUM_OFSTF 0x3
1933#define BSHIFT_L 0xc0
1934#define BGI_TH 0xc
1935#define BRXPATH_A 0x1
1936#define BRXPATH_B 0x2
1937#define BRXPATH_C 0x4
1938#define BRXPATH_D 0x8
1939#define BTXPATH_A 0x1
1940#define BTXPATH_B 0x2
1941#define BTXPATH_C 0x4
1942#define BTXPATH_D 0x8
1943#define BTRSSI_FREQ 0x200
1944#define BADC_BACKOFF 0x3000
1945#define BDFIR_BACKOFF 0xc000
1946#define BTRSSI_LATCH_PHASE 0x10000
1947#define BRX_LDC_OFFSET 0xff
1948#define BRX_QDC_OFFSET 0xff00
1949#define BRX_DFIR_MODE 0x1800000
1950#define BRX_DCNF_TYPE 0xe000000
1951#define BRXIQIMB_A 0x3ff
1952#define BRXIQIMB_B 0xfc00
1953#define BRXIQIMB_C 0x3f0000
1954#define BRXIQIMB_D 0xffc00000
1955#define BDC_DC_NOTCH 0x60000
1956#define BRXNB_NOTCH 0x1f000000
1957#define BPD_TH 0xf
1958#define BPD_TH_OPT2 0xc000
1959#define BPWED_TH 0x700
1960#define BIFMF_WIN_L 0x800
1961#define BPD_OPTION 0x1000
1962#define BMF_WIN_L 0xe000
1963#define BBW_SEARCH_L 0x30000
1964#define BWIN_ENH_L 0xc0000
1965#define BBW_TH 0x700000
1966#define BED_TH2 0x3800000
1967#define BBW_OPTION 0x4000000
1968#define BRADIO_TH 0x18000000
1969#define BWINDOW_L 0xe0000000
1970#define BSBD_OPTION 0x1
1971#define BFRAME_TH 0x1c
1972#define BFS_OPTION 0x60
1973#define BDC_SLOPE_CHECK 0x80
1974#define BFGUARD_COUNTER_DC_L 0xe00
1975#define BFRAME_WEIGHT_SHORT 0x7000
1976#define BSUB_TUNE 0xe00000
1977#define BFRAME_DC_LENGTH 0xe000000
1978#define BSBD_START_OFFSET 0x30000000
1979#define BFRAME_TH_2 0x7
1980#define BFRAME_GI2_TH 0x38
1981#define BGI2_SYNC_EN 0x40
1982#define BSARCH_SHORT_EARLY 0x300
1983#define BSARCH_SHORT_LATE 0xc00
1984#define BSARCH_GI2_LATE 0x70000
1985#define BCFOANTSUM 0x1
1986#define BCFOACC 0x2
1987#define BCFOSTARTOFFSET 0xc
1988#define BCFOLOOPBACK 0x70
1989#define BCFOSUMWEIGHT 0x80
1990#define BDAGCENABLE 0x10000
1991#define BTXIQIMB_A 0x3ff
1992#define BTXIQIMB_B 0xfc00
1993#define BTXIQIMB_C 0x3f0000
1994#define BTXIQIMB_D 0xffc00000
1995#define BTXIDCOFFSET 0xff
1996#define BTXIQDCOFFSET 0xff00
1997#define BTXDFIRMODE 0x10000
1998#define BTXPESUDO_NOISEON 0x4000000
1999#define BTXPESUDO_NOISE_A 0xff
2000#define BTXPESUDO_NOISE_B 0xff00
2001#define BTXPESUDO_NOISE_C 0xff0000
2002#define BTXPESUDO_NOISE_D 0xff000000
2003#define BCCA_DROPOPTION 0x20000
2004#define BCCA_DROPTHRES 0xfff00000
2005#define BEDCCA_H 0xf
2006#define BEDCCA_L 0xf0
2007#define BLAMBDA_ED 0x300
2008#define BRX_INITIALGAIN 0x7f
2009#define BRX_ANTDIV_EN 0x80
2010#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
2011#define BRX_HIGHPOWER_FLOW 0x8000
2012#define BRX_AGC_FREEZE_THRES 0xc0000
2013#define BRX_FREEZESTEP_AGC1 0x300000
2014#define BRX_FREEZESTEP_AGC2 0xc00000
2015#define BRX_FREEZESTEP_AGC3 0x3000000
2016#define BRX_FREEZESTEP_AGC0 0xc000000
2017#define BRXRSSI_CMP_EN 0x10000000
2018#define BRXQUICK_AGCEN 0x20000000
2019#define BRXAGC_FREEZE_THRES_MODE 0x40000000
2020#define BRX_OVERFLOW_CHECKTYPE 0x80000000
2021#define BRX_AGCSHIFT 0x7f
2022#define BTRSW_TRI_ONLY 0x80
2023#define BPOWER_THRES 0x300
2024#define BRXAGC_EN 0x1
2025#define BRXAGC_TOGETHER_EN 0x2
2026#define BRXAGC_MIN 0x4
2027#define BRXHP_INI 0x7
2028#define BRXHP_TRLNA 0x70
2029#define BRXHP_RSSI 0x700
2030#define BRXHP_BBP1 0x7000
2031#define BRXHP_BBP2 0x70000
2032#define BRXHP_BBP3 0x700000
2033#define BRSSI_H 0x7f0000
2034#define BRSSI_GEN 0x7f000000
2035#define BRXSETTLE_TRSW 0x7
2036#define BRXSETTLE_LNA 0x38
2037#define BRXSETTLE_RSSI 0x1c0
2038#define BRXSETTLE_BBP 0xe00
2039#define BRXSETTLE_RXHP 0x7000
2040#define BRXSETTLE_ANTSW_RSSI 0x38000
2041#define BRXSETTLE_ANTSW 0xc0000
2042#define BRXPROCESS_TIME_DAGC 0x300000
2043#define BRXSETTLE_HSSI 0x400000
2044#define BRXPROCESS_TIME_BBPPW 0x800000
2045#define BRXANTENNA_POWER_SHIFT 0x3000000
2046#define BRSSI_TABLE_SELECT 0xc000000
2047#define BRXHP_FINAL 0x7000000
2048#define BRXHPSETTLE_BBP 0x7
2049#define BRXHTSETTLE_HSSI 0x8
2050#define BRXHTSETTLE_RXHP 0x70
2051#define BRXHTSETTLE_BBPPW 0x80
2052#define BRXHTSETTLE_IDLE 0x300
2053#define BRXHTSETTLE_RESERVED 0x1c00
2054#define BRXHT_RXHP_EN 0x8000
2055#define BRXAGC_FREEZE_THRES 0x30000
2056#define BRXAGC_TOGETHEREN 0x40000
2057#define BRXHTAGC_MIN 0x80000
2058#define BRXHTAGC_EN 0x100000
2059#define BRXHTDAGC_EN 0x200000
2060#define BRXHT_RXHP_BBP 0x1c00000
2061#define BRXHT_RXHP_FINAL 0xe0000000
2062#define BRXPW_RADIO_TH 0x3
2063#define BRXPW_RADIO_EN 0x4
2064#define BRXMF_HOLD 0x3800
2065#define BRXPD_DELAY_TH1 0x38
2066#define BRXPD_DELAY_TH2 0x1c0
2067#define BRXPD_DC_COUNT_MAX 0x600
2068#define BRXPD_DELAY_TH 0x8000
2069#define BRXPROCESS_DELAY 0xf0000
2070#define BRXSEARCHRANGE_GI2_EARLY 0x700000
2071#define BRXFRAME_FUARD_COUNTER_L 0x3800000
2072#define BRXSGI_GUARD_L 0xc000000
2073#define BRXSGI_SEARCH_L 0x30000000
2074#define BRXSGI_TH 0xc0000000
2075#define BDFSCNT0 0xff
2076#define BDFSCNT1 0xff00
2077#define BDFSFLAG 0xf0000
2078#define BMF_WEIGHT_SUM 0x300000
2079#define BMINIDX_TH 0x7f000000
2080#define BDAFORMAT 0x40000
2081#define BTXCH_EMU_ENABLE 0x01000000
2082#define BTRSW_ISOLATION_A 0x7f
2083#define BTRSW_ISOLATION_B 0x7f00
2084#define BTRSW_ISOLATION_C 0x7f0000
2085#define BTRSW_ISOLATION_D 0x7f000000
2086#define BEXT_LNA_GAIN 0x7c00
2087
2088#define BSTBC_EN 0x4
2089#define BANTENNA_MAPPING 0x10
2090#define BNSS 0x20
2091#define BCFO_ANTSUM_ID 0x200
2092#define BPHY_COUNTER_RESET 0x8000000
2093#define BCFO_REPORT_GET 0x4000000
2094#define BOFDM_CONTINUE_TX 0x10000000
2095#define BOFDM_SINGLE_CARRIER 0x20000000
2096#define BOFDM_SINGLE_TONE 0x40000000
2097#define BHT_DETECT 0x100
2098#define BCFOEN 0x10000
2099#define BCFOVALUE 0xfff00000
2100#define BSIGTONE_RE 0x3f
2101#define BSIGTONE_IM 0x7f00
2102#define BCOUNTER_CCA 0xffff
2103#define BCOUNTER_PARITYFAIL 0xffff0000
2104#define BCOUNTER_RATEILLEGAL 0xffff
2105#define BCOUNTER_CRC8FAIL 0xffff0000
2106#define BCOUNTER_MCSNOSUPPORT 0xffff
2107#define BCOUNTER_FASTSYNC 0xffff
2108#define BSHORTCFO 0xfff
2109#define BSHORTCFOT_LENGTH 12
2110#define BSHORTCFOF_LENGTH 11
2111#define BLONGCFO 0x7ff
2112#define BLONGCFOT_LENGTH 11
2113#define BLONGCFOF_LENGTH 11
2114#define BTAILCFO 0x1fff
2115#define BTAILCFOT_LENGTH 13
2116#define BTAILCFOF_LENGTH 12
2117#define BNOISE_EN_PWDB 0xffff
2118#define BCC_POWER_DB 0xffff0000
2119#define BMOISE_PWDB 0xffff
2120#define BPOWERMEAST_LENGTH 10
2121#define BPOWERMEASF_LENGTH 3
2122#define BRX_HT_BW 0x1
2123#define BRXSC 0x6
2124#define BRX_HT 0x8
2125#define BNB_INTF_DET_ON 0x1
2126#define BINTF_WIN_LEN_CFG 0x30
2127#define BNB_INTF_TH_CFG 0x1c0
2128#define BRFGAIN 0x3f
2129#define BTABLESEL 0x40
2130#define BTRSW 0x80
2131#define BRXSNR_A 0xff
2132#define BRXSNR_B 0xff00
2133#define BRXSNR_C 0xff0000
2134#define BRXSNR_D 0xff000000
2135#define BSNR_EVMT_LENGTH 8
2136#define BSNR_EVMF_LENGTH 1
2137#define BCSI1ST 0xff
2138#define BCSI2ND 0xff00
2139#define BRXEVM1ST 0xff0000
2140#define BRXEVM2ND 0xff000000
2141#define BSIGEVM 0xff
2142#define BPWDB 0xff00
2143#define BSGIEN 0x10000
2144
2145#define BSFACTOR_QMA1 0xf
2146#define BSFACTOR_QMA2 0xf0
2147#define BSFACTOR_QMA3 0xf00
2148#define BSFACTOR_QMA4 0xf000
2149#define BSFACTOR_QMA5 0xf0000
2150#define BSFACTOR_QMA6 0xf0000
2151#define BSFACTOR_QMA7 0xf00000
2152#define BSFACTOR_QMA8 0xf000000
2153#define BSFACTOR_QMA9 0xf0000000
2154#define BCSI_SCHEME 0x100000
2155
2156#define BNOISE_LVL_TOP_SET 0x3
2157#define BCHSMOOTH 0x4
2158#define BCHSMOOTH_CFG1 0x38
2159#define BCHSMOOTH_CFG2 0x1c0
2160#define BCHSMOOTH_CFG3 0xe00
2161#define BCHSMOOTH_CFG4 0x7000
2162#define BMRCMODE 0x800000
2163#define BTHEVMCFG 0x7000000
2164
2165#define BLOOP_FIT_TYPE 0x1
2166#define BUPD_CFO 0x40
2167#define BUPD_CFO_OFFDATA 0x80
2168#define BADV_UPD_CFO 0x100
2169#define BADV_TIME_CTRL 0x800
2170#define BUPD_CLKO 0x1000
2171#define BFC 0x6000
2172#define BTRACKING_MODE 0x8000
2173#define BPHCMP_ENABLE 0x10000
2174#define BUPD_CLKO_LTF 0x20000
2175#define BCOM_CH_CFO 0x40000
2176#define BCSI_ESTI_MODE 0x80000
2177#define BADV_UPD_EQZ 0x100000
2178#define BUCHCFG 0x7000000
2179#define BUPDEQZ 0x8000000
2180
2181#define BRX_PESUDO_NOISE_ON 0x20000000
2182#define BRX_PESUDO_NOISE_A 0xff
2183#define BRX_PESUDO_NOISE_B 0xff00
2184#define BRX_PESUDO_NOISE_C 0xff0000
2185#define BRX_PESUDO_NOISE_D 0xff000000
2186#define BRX_PESUDO_NOISESTATE_A 0xffff
2187#define BRX_PESUDO_NOISESTATE_B 0xffff0000
2188#define BRX_PESUDO_NOISESTATE_C 0xffff
2189#define BRX_PESUDO_NOISESTATE_D 0xffff0000
2190
2191#define BZEBRA1_HSSIENABLE 0x8
2192#define BZEBRA1_TRXCONTROL 0xc00
2193#define BZEBRA1_TRXGAINSETTING 0x07f
2194#define BZEBRA1_RXCOUNTER 0xc00
2195#define BZEBRA1_TXCHANGEPUMP 0x38
2196#define BZEBRA1_RXCHANGEPUMP 0x7
2197#define BZEBRA1_CHANNEL_NUM 0xf80
2198#define BZEBRA1_TXLPFBW 0x400
2199#define BZEBRA1_RXLPFBW 0x600
2200
2201#define BRTL8256REG_MODE_CTRL1 0x100
2202#define BRTL8256REG_MODE_CTRL0 0x40
2203#define BRTL8256REG_TXLPFBW 0x18
2204#define BRTL8256REG_RXLPFBW 0x600
2205
2206#define BRTL8258_TXLPFBW 0xc
2207#define BRTL8258_RXLPFBW 0xc00
2208#define BRTL8258_RSSILPFBW 0xc0
2209
2210#define BBYTE0 0x1
2211#define BBYTE1 0x2
2212#define BBYTE2 0x4
2213#define BBYTE3 0x8
2214#define BWORD0 0x3
2215#define BWORD1 0xc
2216#define BWORD 0xf
2217
2218#define MASKBYTE0 0xff
2219#define MASKBYTE1 0xff00
2220#define MASKBYTE2 0xff0000
2221#define MASKBYTE3 0xff000000
2222#define MASKHWORD 0xffff0000
2223#define MASKLWORD 0x0000ffff
2224#define MASKDWORD 0xffffffff
2225#define MASK12BITS 0xfff
2226#define MASKH4BITS 0xf0000000
2227#define MASKOFDM_D 0xffc00000
2228#define MASKCCK 0x3f3f3f3f
2229
2230#define MASK4BITS 0x0f
2231#define MASK20BITS 0xfffff
2232#define RFREG_OFFSET_MASK 0xfffff
2233
2234#define BENABLE 0x1
2235#define BDISABLE 0x0
2236
2237#define LEFT_ANTENNA 0x0
2238#define RIGHT_ANTENNA 0x1
2239
2240#define TCHECK_TXSTATUS 500
2241#define TUPDATE_RXCOUNTER 100
2242
2243#define REG_UN_USED_REGISTER 0x01bf
2244
2245/* WOL bit information */
2246#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
2247#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
2248#define HAL92C_WOL_DISASSOC_EVENT BIT(2)
2249#define HAL92C_WOL_DEAUTH_EVENT BIT(3)
2250#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4)
2251
2252#define WOL_REASON_PTK_UPDATE BIT(0)
2253#define WOL_REASON_GTK_UPDATE BIT(1)
2254#define WOL_REASON_DISASSOC BIT(2)
2255#define WOL_REASON_DEAUTH BIT(3)
2256#define WOL_REASON_FW_DISCONNECT BIT(4)
2257
2258#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/rf.c b/drivers/net/wireless/rtlwifi/rtl8188ee/rf.c
new file mode 100644
index 000000000000..e62bcab6ed4d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/rf.c
@@ -0,0 +1,467 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "reg.h"
32#include "def.h"
33#include "phy.h"
34#include "rf.h"
35#include "dm.h"
36
37void rtl88e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
38{
39 struct rtl_priv *rtlpriv = rtl_priv(hw);
40 struct rtl_phy *rtlphy = &(rtlpriv->phy);
41
42 switch (bandwidth) {
43 case HT_CHANNEL_WIDTH_20:
44 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
45 0xfffff3ff) | BIT(10) | BIT(11));
46 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
47 rtlphy->rfreg_chnlval[0]);
48 break;
49 case HT_CHANNEL_WIDTH_20_40:
50 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
51 0xfffff3ff) | BIT(10));
52 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
53 rtlphy->rfreg_chnlval[0]);
54 break;
55 default:
56 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
57 "unknown bandwidth: %#X\n", bandwidth);
58 break;
59 }
60}
61
62void rtl88e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
63 u8 *plevel)
64{
65 struct rtl_priv *rtlpriv = rtl_priv(hw);
66 struct rtl_phy *rtlphy = &(rtlpriv->phy);
67 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
68 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
69 u32 tx_agc[2] = {0, 0}, tmpval;
70 bool turbo_scanoff = false;
71 u8 idx1, idx2;
72 u8 *ptr;
73 u8 direction;
74 u32 pwrtrac_value;
75
76 if (rtlefuse->eeprom_regulatory != 0)
77 turbo_scanoff = true;
78
79 if (mac->act_scanning == true) {
80 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
81 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
82
83 if (turbo_scanoff) {
84 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
85 tx_agc[idx1] = plevel[idx1] |
86 (plevel[idx1] << 8) |
87 (plevel[idx1] << 16) |
88 (plevel[idx1] << 24);
89 }
90 }
91 } else {
92 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
93 tx_agc[idx1] = plevel[idx1] | (plevel[idx1] << 8) |
94 (plevel[idx1] << 16) |
95 (plevel[idx1] << 24);
96 }
97
98 if (rtlefuse->eeprom_regulatory == 0) {
99 tmpval = (rtlphy->mcs_offset[0][6]) +
100 (rtlphy->mcs_offset[0][7] << 8);
101 tx_agc[RF90_PATH_A] += tmpval;
102
103 tmpval = (rtlphy->mcs_offset[0][14]) +
104 (rtlphy->mcs_offset[0][15] << 24);
105 tx_agc[RF90_PATH_B] += tmpval;
106 }
107 }
108
109 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
110 ptr = (u8 *)(&(tx_agc[idx1]));
111 for (idx2 = 0; idx2 < 4; idx2++) {
112 if (*ptr > RF6052_MAX_TX_PWR)
113 *ptr = RF6052_MAX_TX_PWR;
114 ptr++;
115 }
116 }
117 rtl88e_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
118 if (direction == 1) {
119 tx_agc[0] += pwrtrac_value;
120 tx_agc[1] += pwrtrac_value;
121 } else if (direction == 2) {
122 tx_agc[0] -= pwrtrac_value;
123 tx_agc[1] -= pwrtrac_value;
124 }
125 tmpval = tx_agc[RF90_PATH_A] & 0xff;
126 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
127
128 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
129 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
130 RTXAGC_A_CCK1_MCS32);
131
132 tmpval = tx_agc[RF90_PATH_A] >> 8;
133
134 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
135
136 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
137 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
138 RTXAGC_B_CCK11_A_CCK2_11);
139
140 tmpval = tx_agc[RF90_PATH_B] >> 24;
141 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
142
143 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
144 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
145 RTXAGC_B_CCK11_A_CCK2_11);
146
147 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
148 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
149
150 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
151 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
152 RTXAGC_B_CCK1_55_MCS32);
153}
154
155static void rtl88e_phy_get_power_base(struct ieee80211_hw *hw,
156 u8 *pwrlvlofdm, u8 *pwrlvlbw20,
157 u8 *pwrlvlbw40, u8 channel,
158 u32 *ofdmbase, u32 *mcsbase)
159{
160 struct rtl_priv *rtlpriv = rtl_priv(hw);
161 struct rtl_phy *rtlphy = &(rtlpriv->phy);
162 u32 base0, base1;
163 u8 i, powerlevel[2];
164
165 for (i = 0; i < 2; i++) {
166 base0 = pwrlvlofdm[i];
167
168 base0 = (base0 << 24) | (base0 << 16) |
169 (base0 << 8) | base0;
170 *(ofdmbase + i) = base0;
171 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
172 "[OFDM power base index rf(%c) = 0x%x]\n",
173 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
174 }
175
176 for (i = 0; i < 2; i++) {
177 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
178 powerlevel[i] = pwrlvlbw20[i];
179 else
180 powerlevel[i] = pwrlvlbw40[i];
181 base1 = powerlevel[i];
182 base1 = (base1 << 24) |
183 (base1 << 16) | (base1 << 8) | base1;
184
185 *(mcsbase + i) = base1;
186
187 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
188 "[MCS power base index rf(%c) = 0x%x]\n",
189 ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
190 }
191}
192
193static void get_txpwr_by_reg(struct ieee80211_hw *hw, u8 chan, u8 index,
194 u32 *base0, u32 *base1, u32 *outval)
195{
196 struct rtl_priv *rtlpriv = rtl_priv(hw);
197 struct rtl_phy *rtlphy = &(rtlpriv->phy);
198 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
199 u8 i, chg = 0, pwr_lim[4], pwr_diff = 0, cust_pwr_dif;
200 u32 writeval, cust_lim, rf, tmp;
201 u8 ch = chan - 1;
202 u8 j;
203
204 for (rf = 0; rf < 2; rf++) {
205 j = index + (rf ? 8 : 0);
206 tmp = ((index < 2) ? base0[rf] : base1[rf]);
207 switch (rtlefuse->eeprom_regulatory) {
208 case 0:
209 chg = 0;
210
211 writeval = rtlphy->mcs_offset[chg][j] + tmp;
212
213 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
214 "RTK better performance, "
215 "writeval(%c) = 0x%x\n",
216 ((rf == 0) ? 'A' : 'B'), writeval);
217 break;
218 case 1:
219 if (rtlphy->pwrgroup_cnt == 1) {
220 chg = 0;
221 } else {
222 chg = chan / 3;
223 if (chan == 14)
224 chg = 5;
225 }
226 writeval = rtlphy->mcs_offset[chg][j] + tmp;
227
228 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
229 "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
230 ((rf == 0) ? 'A' : 'B'), writeval);
231 break;
232 case 2:
233 writeval = ((index < 2) ? base0[rf] : base1[rf]);
234
235 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
236 "Better regulatory, writeval(%c) = 0x%x\n",
237 ((rf == 0) ? 'A' : 'B'), writeval);
238 break;
239 case 3:
240 chg = 0;
241
242 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
243 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
244 "customer's limit, 40MHz rf(%c) = 0x%x\n",
245 ((rf == 0) ? 'A' : 'B'),
246 rtlefuse->pwrgroup_ht40[rf][ch]);
247 } else {
248 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
249 "customer's limit, 20MHz rf(%c) = 0x%x\n",
250 ((rf == 0) ? 'A' : 'B'),
251 rtlefuse->pwrgroup_ht20[rf][ch]);
252 }
253
254 if (index < 2)
255 pwr_diff = rtlefuse->txpwr_legacyhtdiff[rf][ch];
256 else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
257 pwr_diff = rtlefuse->txpwr_ht20diff[rf][ch];
258
259 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
260 cust_pwr_dif = rtlefuse->pwrgroup_ht40[rf][ch];
261 else
262 cust_pwr_dif = rtlefuse->pwrgroup_ht20[rf][ch];
263
264 if (pwr_diff > cust_pwr_dif)
265 pwr_diff = 0;
266 else
267 pwr_diff = cust_pwr_dif - pwr_diff;
268
269 for (i = 0; i < 4; i++) {
270 pwr_lim[i] = (u8)((rtlphy->mcs_offset[chg][j] &
271 (0x7f << (i * 8))) >> (i * 8));
272
273 if (pwr_lim[i] > pwr_diff)
274 pwr_lim[i] = pwr_diff;
275 }
276
277 cust_lim = (pwr_lim[3] << 24) | (pwr_lim[2] << 16) |
278 (pwr_lim[1] << 8) | (pwr_lim[0]);
279
280 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
281 "Customer's limit rf(%c) = 0x%x\n",
282 ((rf == 0) ? 'A' : 'B'), cust_lim);
283
284 writeval = cust_lim + tmp;
285
286 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
287 "Customer, writeval rf(%c) = 0x%x\n",
288 ((rf == 0) ? 'A' : 'B'), writeval);
289 break;
290 default:
291 chg = 0;
292 writeval = rtlphy->mcs_offset[chg][j] + tmp;
293
294 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
295 "RTK better performance, writeval "
296 "rf(%c) = 0x%x\n",
297 ((rf == 0) ? 'A' : 'B'), writeval);
298 break;
299 }
300
301 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
302 writeval = writeval - 0x06060606;
303 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
304 TXHIGHPWRLEVEL_BT2)
305 writeval -= 0x0c0c0c0c;
306 *(outval + rf) = writeval;
307 }
308}
309
310static void write_ofdm_pwr(struct ieee80211_hw *hw, u8 index, u32 *pvalue)
311{
312 struct rtl_priv *rtlpriv = rtl_priv(hw);
313 u16 regoffset_a[6] = {
314 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
315 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
316 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
317 };
318 u16 regoffset_b[6] = {
319 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
320 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
321 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
322 };
323 u8 i, rf, pwr_val[4];
324 u32 writeval;
325 u16 regoffset;
326
327 for (rf = 0; rf < 2; rf++) {
328 writeval = pvalue[rf];
329 for (i = 0; i < 4; i++) {
330 pwr_val[i] = (u8) ((writeval & (0x7f <<
331 (i * 8))) >> (i * 8));
332
333 if (pwr_val[i] > RF6052_MAX_TX_PWR)
334 pwr_val[i] = RF6052_MAX_TX_PWR;
335 }
336 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
337 (pwr_val[1] << 8) | pwr_val[0];
338
339 if (rf == 0)
340 regoffset = regoffset_a[index];
341 else
342 regoffset = regoffset_b[index];
343 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
344
345 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
346 "Set 0x%x = %08x\n", regoffset, writeval);
347 }
348}
349
350void rtl88e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
351 u8 *pwrlvlofdm,
352 u8 *pwrlvlbw20,
353 u8 *pwrlvlbw40, u8 chan)
354{
355 u32 writeval[2], base0[2], base1[2];
356 u8 index;
357 u8 direction;
358 u32 pwrtrac_value;
359
360 rtl88e_phy_get_power_base(hw, pwrlvlofdm, pwrlvlbw20,
361 pwrlvlbw40, chan, &base0[0],
362 &base1[0]);
363
364 rtl88e_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
365
366 for (index = 0; index < 6; index++) {
367 get_txpwr_by_reg(hw, chan, index, &base0[0], &base1[0],
368 &writeval[0]);
369 if (direction == 1) {
370 writeval[0] += pwrtrac_value;
371 writeval[1] += pwrtrac_value;
372 } else if (direction == 2) {
373 writeval[0] -= pwrtrac_value;
374 writeval[1] -= pwrtrac_value;
375 }
376 write_ofdm_pwr(hw, index, &writeval[0]);
377 }
378}
379
380static bool rf6052_conf_para(struct ieee80211_hw *hw)
381{
382 struct rtl_priv *rtlpriv = rtl_priv(hw);
383 struct rtl_phy *rtlphy = &(rtlpriv->phy);
384 u32 u4val = 0;
385 u8 rfpath;
386 bool rtstatus = true;
387 struct bb_reg_def *pphyreg;
388
389 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
390 pphyreg = &rtlphy->phyreg_def[rfpath];
391
392 switch (rfpath) {
393 case RF90_PATH_A:
394 case RF90_PATH_C:
395 u4val = rtl_get_bbreg(hw, pphyreg->rfintfs,
396 BRFSI_RFENV);
397 break;
398 case RF90_PATH_B:
399 case RF90_PATH_D:
400 u4val = rtl_get_bbreg(hw, pphyreg->rfintfs,
401 BRFSI_RFENV << 16);
402 break;
403 }
404
405 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
406 udelay(1);
407
408 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
409 udelay(1);
410
411 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
412 B3WIREADDREAALENGTH, 0x0);
413 udelay(1);
414
415 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
416 udelay(1);
417
418 switch (rfpath) {
419 case RF90_PATH_A:
420 rtstatus = rtl88e_phy_config_rf_with_headerfile(hw,
421 (enum radio_path)rfpath);
422 break;
423 case RF90_PATH_B:
424 rtstatus = rtl88e_phy_config_rf_with_headerfile(hw,
425 (enum radio_path)rfpath);
426 break;
427 case RF90_PATH_C:
428 break;
429 case RF90_PATH_D:
430 break;
431 }
432
433 switch (rfpath) {
434 case RF90_PATH_A:
435 case RF90_PATH_C:
436 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, u4val);
437 break;
438 case RF90_PATH_B:
439 case RF90_PATH_D:
440 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
441 u4val);
442 break;
443 }
444
445 if (rtstatus != true) {
446 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
447 "Radio[%d] Fail!!", rfpath);
448 return false;
449 }
450 }
451
452 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
453 return rtstatus;
454}
455
456bool rtl88e_phy_rf6052_config(struct ieee80211_hw *hw)
457{
458 struct rtl_priv *rtlpriv = rtl_priv(hw);
459 struct rtl_phy *rtlphy = &(rtlpriv->phy);
460
461 if (rtlphy->rf_type == RF_1T1R)
462 rtlphy->num_total_rfpath = 1;
463 else
464 rtlphy->num_total_rfpath = 2;
465
466 return rf6052_conf_para(hw);
467}
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/rf.h b/drivers/net/wireless/rtlwifi/rtl8188ee/rf.h
new file mode 100644
index 000000000000..a39a2a3dbcc9
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/rf.h
@@ -0,0 +1,46 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_RF_H__
31#define __RTL92C_RF_H__
32
33#define RF6052_MAX_TX_PWR 0x3F
34#define RF6052_MAX_REG 0x3F
35
36void rtl88e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
37 u8 bandwidth);
38void rtl88e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
39 u8 *ppowerlevel);
40void rtl88e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
41 u8 *ppowerlevel_ofdm,
42 u8 *ppowerlevel_bw20,
43 u8 *ppowerlevel_bw40, u8 channel);
44bool rtl88e_phy_rf6052_config(struct ieee80211_hw *hw);
45
46#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/sw.c b/drivers/net/wireless/rtlwifi/rtl8188ee/sw.c
new file mode 100644
index 000000000000..e8ce1897f383
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/sw.c
@@ -0,0 +1,400 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "core.h"
32#include "pci.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "dm.h"
37#include "hw.h"
38#include "sw.h"
39#include "trx.h"
40#include "led.h"
41#include "table.h"
42
43#include <linux/vmalloc.h>
44#include <linux/module.h>
45
46static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw)
47{
48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
49
50 /*close ASPM for AMD defaultly */
51 rtlpci->const_amdpci_aspm = 0;
52
53 /* ASPM PS mode.
54 * 0 - Disable ASPM,
55 * 1 - Enable ASPM without Clock Req,
56 * 2 - Enable ASPM with Clock Req,
57 * 3 - Alwyas Enable ASPM with Clock Req,
58 * 4 - Always Enable ASPM without Clock Req.
59 * set defult to RTL8192CE:3 RTL8192E:2
60 */
61 rtlpci->const_pci_aspm = 3;
62
63 /*Setting for PCI-E device */
64 rtlpci->const_devicepci_aspm_setting = 0x03;
65
66 /*Setting for PCI-E bridge */
67 rtlpci->const_hostpci_aspm_setting = 0x02;
68
69 /* In Hw/Sw Radio Off situation.
70 * 0 - Default,
71 * 1 - From ASPM setting without low Mac Pwr,
72 * 2 - From ASPM setting with low Mac Pwr,
73 * 3 - Bus D3
74 * set default to RTL8192CE:0 RTL8192SE:2
75 */
76 rtlpci->const_hwsw_rfoff_d3 = 0;
77
78 /* This setting works for those device with
79 * backdoor ASPM setting such as EPHY setting.
80 * 0 - Not support ASPM,
81 * 1 - Support ASPM,
82 * 2 - According to chipset.
83 */
84 rtlpci->const_support_pciaspm = 1;
85}
86
87int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
88{
89 int err = 0;
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 u8 tid;
93
94 rtl8188ee_bt_reg_init(hw);
95
96 rtlpriv->dm.dm_initialgain_enable = 1;
97 rtlpriv->dm.dm_flag = 0;
98 rtlpriv->dm.disable_framebursting = 0;
99 rtlpriv->dm.thermalvalue = 0;
100 rtlpci->transmit_config = CFENDFORM | BIT(15);
101
102 /* compatible 5G band 88ce just 2.4G band & smsp */
103 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
104 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
105 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
106
107 rtlpci->receive_config = (RCR_APPFCS |
108 RCR_APP_MIC |
109 RCR_APP_ICV |
110 RCR_APP_PHYST_RXFF |
111 RCR_HTC_LOC_CTRL |
112 RCR_AMF |
113 RCR_ACF |
114 RCR_ADF |
115 RCR_AICV |
116 RCR_ACRC32 |
117 RCR_AB |
118 RCR_AM |
119 RCR_APM |
120 0);
121
122 rtlpci->irq_mask[0] =
123 (u32) (IMR_PSTIMEOUT |
124 IMR_HSISR_IND_ON_INT |
125 IMR_C2HCMD |
126 IMR_HIGHDOK |
127 IMR_MGNTDOK |
128 IMR_BKDOK |
129 IMR_BEDOK |
130 IMR_VIDOK |
131 IMR_VODOK |
132 IMR_RDU |
133 IMR_ROK |
134 0);
135 rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0);
136 rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN);
137
138 /* for debug level */
139 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
140 /* for LPS & IPS */
141 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
142 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
143 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
144 if (!rtlpriv->psc.inactiveps)
145 pr_info("rtl8188ee: Power Save off (module option)\n");
146 if (!rtlpriv->psc.fwctrl_lps)
147 pr_info("rtl8188ee: FW Power Save off (module option)\n");
148 rtlpriv->psc.reg_fwctrl_lps = 3;
149 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
150 /* for ASPM, you can close aspm through
151 * set const_support_pciaspm = 0
152 */
153 rtl88e_init_aspm_vars(hw);
154
155 if (rtlpriv->psc.reg_fwctrl_lps == 1)
156 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
157 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
158 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
159 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
160 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
161
162 /* for firmware buf */
163 rtlpriv->rtlhal.pfirmware = vmalloc(0x8000);
164 if (!rtlpriv->rtlhal.pfirmware) {
165 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
166 "Can't alloc buffer for fw.\n");
167 return 1;
168 }
169
170 rtlpriv->cfg->fw_name = "rtlwifi/rtl8188efw.bin";
171 rtlpriv->max_fw_size = 0x8000;
172 pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
173 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
174 rtlpriv->io.dev, GFP_KERNEL, hw,
175 rtl_fw_cb);
176 if (err) {
177 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
178 "Failed to request firmware!\n");
179 return 1;
180 }
181
182 /* for early mode */
183 rtlpriv->rtlhal.earlymode_enable = false;
184 rtlpriv->rtlhal.max_earlymode_num = 10;
185 for (tid = 0; tid < 8; tid++)
186 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
187
188 /*low power */
189 rtlpriv->psc.low_power_enable = false;
190 if (rtlpriv->psc.low_power_enable) {
191 init_timer(&rtlpriv->works.fw_clockoff_timer);
192 setup_timer(&rtlpriv->works.fw_clockoff_timer,
193 rtl88ee_fw_clk_off_timer_callback,
194 (unsigned long)hw);
195 }
196
197 init_timer(&rtlpriv->works.fast_antenna_training_timer);
198 setup_timer(&rtlpriv->works.fast_antenna_training_timer,
199 rtl88e_dm_fast_antenna_training_callback,
200 (unsigned long)hw);
201 return err;
202}
203
204void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw)
205{
206 struct rtl_priv *rtlpriv = rtl_priv(hw);
207
208 if (rtlpriv->rtlhal.pfirmware) {
209 vfree(rtlpriv->rtlhal.pfirmware);
210 rtlpriv->rtlhal.pfirmware = NULL;
211 }
212
213 if (rtlpriv->psc.low_power_enable)
214 del_timer_sync(&rtlpriv->works.fw_clockoff_timer);
215
216 del_timer_sync(&rtlpriv->works.fast_antenna_training_timer);
217}
218
219static struct rtl_hal_ops rtl8188ee_hal_ops = {
220 .init_sw_vars = rtl88e_init_sw_vars,
221 .deinit_sw_vars = rtl88e_deinit_sw_vars,
222 .read_eeprom_info = rtl88ee_read_eeprom_info,
223 .interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/
224 .hw_init = rtl88ee_hw_init,
225 .hw_disable = rtl88ee_card_disable,
226 .hw_suspend = rtl88ee_suspend,
227 .hw_resume = rtl88ee_resume,
228 .enable_interrupt = rtl88ee_enable_interrupt,
229 .disable_interrupt = rtl88ee_disable_interrupt,
230 .set_network_type = rtl88ee_set_network_type,
231 .set_chk_bssid = rtl88ee_set_check_bssid,
232 .set_qos = rtl88ee_set_qos,
233 .set_bcn_reg = rtl88ee_set_beacon_related_registers,
234 .set_bcn_intv = rtl88ee_set_beacon_interval,
235 .update_interrupt_mask = rtl88ee_update_interrupt_mask,
236 .get_hw_reg = rtl88ee_get_hw_reg,
237 .set_hw_reg = rtl88ee_set_hw_reg,
238 .update_rate_tbl = rtl88ee_update_hal_rate_tbl,
239 .fill_tx_desc = rtl88ee_tx_fill_desc,
240 .fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc,
241 .query_rx_desc = rtl88ee_rx_query_desc,
242 .set_channel_access = rtl88ee_update_channel_access_setting,
243 .radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking,
244 .set_bw_mode = rtl88e_phy_set_bw_mode,
245 .switch_channel = rtl88e_phy_sw_chnl,
246 .dm_watchdog = rtl88e_dm_watchdog,
247 .scan_operation_backup = rtl88e_phy_scan_operation_backup,
248 .set_rf_power_state = rtl88e_phy_set_rf_power_state,
249 .led_control = rtl88ee_led_control,
250 .set_desc = rtl88ee_set_desc,
251 .get_desc = rtl88ee_get_desc,
252 .tx_polling = rtl88ee_tx_polling,
253 .enable_hw_sec = rtl88ee_enable_hw_security_config,
254 .set_key = rtl88ee_set_key,
255 .init_sw_leds = rtl88ee_init_sw_leds,
256 .allow_all_destaddr = rtl88ee_allow_all_destaddr,
257 .get_bbreg = rtl88e_phy_query_bb_reg,
258 .set_bbreg = rtl88e_phy_set_bb_reg,
259 .get_rfreg = rtl88e_phy_query_rf_reg,
260 .set_rfreg = rtl88e_phy_set_rf_reg,
261};
262
263static struct rtl_mod_params rtl88ee_mod_params = {
264 .sw_crypto = false,
265 .inactiveps = true,
266 .swctrl_lps = false,
267 .fwctrl_lps = true,
268 .debug = DBG_EMERG,
269};
270
271static struct rtl_hal_cfg rtl88ee_hal_cfg = {
272 .bar_id = 2,
273 .write_readback = true,
274 .name = "rtl88e_pci",
275 .ops = &rtl8188ee_hal_ops,
276 .mod_params = &rtl88ee_mod_params,
277
278 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
279 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
280 .maps[SYS_CLK] = REG_SYS_CLKR,
281 .maps[MAC_RCR_AM] = AM,
282 .maps[MAC_RCR_AB] = AB,
283 .maps[MAC_RCR_ACRC32] = ACRC32,
284 .maps[MAC_RCR_ACF] = ACF,
285 .maps[MAC_RCR_AAP] = AAP,
286
287 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
288
289 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
290 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
291 .maps[EFUSE_CLK] = 0,
292 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
293 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
294 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
295 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
296 .maps[EFUSE_ANA8M] = ANA8M,
297 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
298 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
299 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
300 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
301
302 .maps[RWCAM] = REG_CAMCMD,
303 .maps[WCAMI] = REG_CAMWRITE,
304 .maps[RCAMO] = REG_CAMREAD,
305 .maps[CAMDBG] = REG_CAMDBG,
306 .maps[SECR] = REG_SECCFG,
307 .maps[SEC_CAM_NONE] = CAM_NONE,
308 .maps[SEC_CAM_WEP40] = CAM_WEP40,
309 .maps[SEC_CAM_TKIP] = CAM_TKIP,
310 .maps[SEC_CAM_AES] = CAM_AES,
311 .maps[SEC_CAM_WEP104] = CAM_WEP104,
312
313 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
314 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
315 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
316 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
317 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
318 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
319/* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
320 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
321 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
322 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
323 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
324 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
325 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
326 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
327/* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
328/* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
329
330 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
331 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
332 .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
333 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
334 .maps[RTL_IMR_RDU] = IMR_RDU,
335 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
336 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
337 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
338 .maps[RTL_IMR_TBDER] = IMR_TBDER,
339 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
340 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
341 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
342 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
343 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
344 .maps[RTL_IMR_VODOK] = IMR_VODOK,
345 .maps[RTL_IMR_ROK] = IMR_ROK,
346 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
347
348 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
349 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
350 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
351 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
352 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
353 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
354 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
355 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
356 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
357 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
358 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
359 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
360
361 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
362 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
363};
364
365static DEFINE_PCI_DEVICE_TABLE(rtl88ee_pci_ids) = {
366 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)},
367 {},
368};
369
370MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids);
371
372MODULE_AUTHOR("zhiyuan_yang <zhiyuan_yang@realsil.com.cn>");
373MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
374MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
375MODULE_LICENSE("GPL");
376MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless");
377MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin");
378
379module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444);
380module_param_named(debug, rtl88ee_mod_params.debug, int, 0444);
381module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444);
382module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444);
383module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444);
384MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
385MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
386MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
387MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
388MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
389
390static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
391
392static struct pci_driver rtl88ee_driver = {
393 .name = KBUILD_MODNAME,
394 .id_table = rtl88ee_pci_ids,
395 .probe = rtl_pci_probe,
396 .remove = rtl_pci_disconnect,
397 .driver.pm = &rtlwifi_pm_ops,
398};
399
400module_pci_driver(rtl88ee_driver);
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/sw.h b/drivers/net/wireless/rtlwifi/rtl8188ee/sw.h
new file mode 100644
index 000000000000..85e02b3bdff8
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/sw.h
@@ -0,0 +1,36 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CE_SW_H__
31#define __RTL92CE_SW_H__
32
33int rtl88e_init_sw_vars(struct ieee80211_hw *hw);
34void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw);
35
36#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/table.c b/drivers/net/wireless/rtlwifi/rtl8188ee/table.c
new file mode 100644
index 000000000000..fad373f97b2c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/table.c
@@ -0,0 +1,643 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Created on 2010/ 5/18, 1:41
27 *
28 * Larry Finger <Larry.Finger@lwfinger.net>
29 *
30 *****************************************************************************/
31
32#include "table.h"
33
34u32 RTL8188EEPHY_REG_1TARRAY[] = {
35 0x800, 0x80040000,
36 0x804, 0x00000003,
37 0x808, 0x0000FC00,
38 0x80C, 0x0000000A,
39 0x810, 0x10001331,
40 0x814, 0x020C3D10,
41 0x818, 0x02200385,
42 0x81C, 0x00000000,
43 0x820, 0x01000100,
44 0x824, 0x00390204,
45 0x828, 0x00000000,
46 0x82C, 0x00000000,
47 0x830, 0x00000000,
48 0x834, 0x00000000,
49 0x838, 0x00000000,
50 0x83C, 0x00000000,
51 0x840, 0x00010000,
52 0x844, 0x00000000,
53 0x848, 0x00000000,
54 0x84C, 0x00000000,
55 0x850, 0x00000000,
56 0x854, 0x00000000,
57 0x858, 0x569A11A9,
58 0x85C, 0x01000014,
59 0x860, 0x66F60110,
60 0x864, 0x061F0649,
61 0x868, 0x00000000,
62 0x86C, 0x27272700,
63 0x870, 0x07000760,
64 0x874, 0x25004000,
65 0x878, 0x00000808,
66 0x87C, 0x00000000,
67 0x880, 0xB0000C1C,
68 0x884, 0x00000001,
69 0x888, 0x00000000,
70 0x88C, 0xCCC000C0,
71 0x890, 0x00000800,
72 0x894, 0xFFFFFFFE,
73 0x898, 0x40302010,
74 0x89C, 0x00706050,
75 0x900, 0x00000000,
76 0x904, 0x00000023,
77 0x908, 0x00000000,
78 0x90C, 0x81121111,
79 0x910, 0x00000002,
80 0x914, 0x00000201,
81 0xA00, 0x00D047C8,
82 0xA04, 0x80FF000C,
83 0xA08, 0x8C838300,
84 0xA0C, 0x2E7F120F,
85 0xA10, 0x9500BB78,
86 0xA14, 0x1114D028,
87 0xA18, 0x00881117,
88 0xA1C, 0x89140F00,
89 0xA20, 0x1A1B0000,
90 0xA24, 0x090E1317,
91 0xA28, 0x00000204,
92 0xA2C, 0x00D30000,
93 0xA70, 0x101FBF00,
94 0xA74, 0x00000007,
95 0xA78, 0x00000900,
96 0xA7C, 0x225B0606,
97 0xA80, 0x218075B1,
98 0xB2C, 0x80000000,
99 0xC00, 0x48071D40,
100 0xC04, 0x03A05611,
101 0xC08, 0x000000E4,
102 0xC0C, 0x6C6C6C6C,
103 0xC10, 0x08800000,
104 0xC14, 0x40000100,
105 0xC18, 0x08800000,
106 0xC1C, 0x40000100,
107 0xC20, 0x00000000,
108 0xC24, 0x00000000,
109 0xC28, 0x00000000,
110 0xC2C, 0x00000000,
111 0xC30, 0x69E9AC47,
112 0xC34, 0x469652AF,
113 0xC38, 0x49795994,
114 0xC3C, 0x0A97971C,
115 0xC40, 0x1F7C403F,
116 0xC44, 0x000100B7,
117 0xC48, 0xEC020107,
118 0xC4C, 0x007F037F,
119 0xC50, 0x69553420,
120 0xC54, 0x43BC0094,
121 0xC58, 0x00013169,
122 0xC5C, 0x00250492,
123 0xC60, 0x00000000,
124 0xC64, 0x7112848B,
125 0xC68, 0x47C00BFF,
126 0xC6C, 0x00000036,
127 0xC70, 0x2C7F000D,
128 0xC74, 0x020610DB,
129 0xC78, 0x0000001F,
130 0xC7C, 0x00B91612,
131 0xC80, 0x390000E4,
132 0xC84, 0x20F60000,
133 0xC88, 0x40000100,
134 0xC8C, 0x20200000,
135 0xC90, 0x00091521,
136 0xC94, 0x00000000,
137 0xC98, 0x00121820,
138 0xC9C, 0x00007F7F,
139 0xCA0, 0x00000000,
140 0xCA4, 0x000300A0,
141 0xCA8, 0x00000000,
142 0xCAC, 0x00000000,
143 0xCB0, 0x00000000,
144 0xCB4, 0x00000000,
145 0xCB8, 0x00000000,
146 0xCBC, 0x28000000,
147 0xCC0, 0x00000000,
148 0xCC4, 0x00000000,
149 0xCC8, 0x00000000,
150 0xCCC, 0x00000000,
151 0xCD0, 0x00000000,
152 0xCD4, 0x00000000,
153 0xCD8, 0x64B22427,
154 0xCDC, 0x00766932,
155 0xCE0, 0x00222222,
156 0xCE4, 0x00000000,
157 0xCE8, 0x37644302,
158 0xCEC, 0x2F97D40C,
159 0xD00, 0x00000740,
160 0xD04, 0x00020401,
161 0xD08, 0x0000907F,
162 0xD0C, 0x20010201,
163 0xD10, 0xA0633333,
164 0xD14, 0x3333BC43,
165 0xD18, 0x7A8F5B6F,
166 0xD2C, 0xCC979975,
167 0xD30, 0x00000000,
168 0xD34, 0x80608000,
169 0xD38, 0x00000000,
170 0xD3C, 0x00127353,
171 0xD40, 0x00000000,
172 0xD44, 0x00000000,
173 0xD48, 0x00000000,
174 0xD4C, 0x00000000,
175 0xD50, 0x6437140A,
176 0xD54, 0x00000000,
177 0xD58, 0x00000282,
178 0xD5C, 0x30032064,
179 0xD60, 0x4653DE68,
180 0xD64, 0x04518A3C,
181 0xD68, 0x00002101,
182 0xD6C, 0x2A201C16,
183 0xD70, 0x1812362E,
184 0xD74, 0x322C2220,
185 0xD78, 0x000E3C24,
186 0xE00, 0x2D2D2D2D,
187 0xE04, 0x2D2D2D2D,
188 0xE08, 0x0390272D,
189 0xE10, 0x2D2D2D2D,
190 0xE14, 0x2D2D2D2D,
191 0xE18, 0x2D2D2D2D,
192 0xE1C, 0x2D2D2D2D,
193 0xE28, 0x00000000,
194 0xE30, 0x1000DC1F,
195 0xE34, 0x10008C1F,
196 0xE38, 0x02140102,
197 0xE3C, 0x681604C2,
198 0xE40, 0x01007C00,
199 0xE44, 0x01004800,
200 0xE48, 0xFB000000,
201 0xE4C, 0x000028D1,
202 0xE50, 0x1000DC1F,
203 0xE54, 0x10008C1F,
204 0xE58, 0x02140102,
205 0xE5C, 0x28160D05,
206 0xE60, 0x00000008,
207 0xE68, 0x001B25A4,
208 0xE6C, 0x00C00014,
209 0xE70, 0x00C00014,
210 0xE74, 0x01000014,
211 0xE78, 0x01000014,
212 0xE7C, 0x01000014,
213 0xE80, 0x01000014,
214 0xE84, 0x00C00014,
215 0xE88, 0x01000014,
216 0xE8C, 0x00C00014,
217 0xED0, 0x00C00014,
218 0xED4, 0x00C00014,
219 0xED8, 0x00C00014,
220 0xEDC, 0x00000014,
221 0xEE0, 0x00000014,
222 0xEEC, 0x01C00014,
223 0xF14, 0x00000003,
224 0xF4C, 0x00000000,
225 0xF00, 0x00000300,
226
227};
228
229u32 RTL8188EEPHY_REG_ARRAY_PG[] = {
230 0xE00, 0xFFFFFFFF, 0x06070809,
231 0xE04, 0xFFFFFFFF, 0x02020405,
232 0xE08, 0x0000FF00, 0x00000006,
233 0x86C, 0xFFFFFF00, 0x00020400,
234 0xE10, 0xFFFFFFFF, 0x08090A0B,
235 0xE14, 0xFFFFFFFF, 0x01030607,
236 0xE18, 0xFFFFFFFF, 0x08090A0B,
237 0xE1C, 0xFFFFFFFF, 0x01030607,
238 0xE00, 0xFFFFFFFF, 0x00000000,
239 0xE04, 0xFFFFFFFF, 0x00000000,
240 0xE08, 0x0000FF00, 0x00000000,
241 0x86C, 0xFFFFFF00, 0x00000000,
242 0xE10, 0xFFFFFFFF, 0x00000000,
243 0xE14, 0xFFFFFFFF, 0x00000000,
244 0xE18, 0xFFFFFFFF, 0x00000000,
245 0xE1C, 0xFFFFFFFF, 0x00000000,
246 0xE00, 0xFFFFFFFF, 0x02020202,
247 0xE04, 0xFFFFFFFF, 0x00020202,
248 0xE08, 0x0000FF00, 0x00000000,
249 0x86C, 0xFFFFFF00, 0x00000000,
250 0xE10, 0xFFFFFFFF, 0x04040404,
251 0xE14, 0xFFFFFFFF, 0x00020404,
252 0xE18, 0xFFFFFFFF, 0x00000000,
253 0xE1C, 0xFFFFFFFF, 0x00000000,
254 0xE00, 0xFFFFFFFF, 0x02020202,
255 0xE04, 0xFFFFFFFF, 0x00020202,
256 0xE08, 0x0000FF00, 0x00000000,
257 0x86C, 0xFFFFFF00, 0x00000000,
258 0xE10, 0xFFFFFFFF, 0x04040404,
259 0xE14, 0xFFFFFFFF, 0x00020404,
260 0xE18, 0xFFFFFFFF, 0x00000000,
261 0xE1C, 0xFFFFFFFF, 0x00000000,
262 0xE00, 0xFFFFFFFF, 0x00000000,
263 0xE04, 0xFFFFFFFF, 0x00000000,
264 0xE08, 0x0000FF00, 0x00000000,
265 0x86C, 0xFFFFFF00, 0x00000000,
266 0xE10, 0xFFFFFFFF, 0x00000000,
267 0xE14, 0xFFFFFFFF, 0x00000000,
268 0xE18, 0xFFFFFFFF, 0x00000000,
269 0xE1C, 0xFFFFFFFF, 0x00000000,
270 0xE00, 0xFFFFFFFF, 0x02020202,
271 0xE04, 0xFFFFFFFF, 0x00020202,
272 0xE08, 0x0000FF00, 0x00000000,
273 0x86C, 0xFFFFFF00, 0x00000000,
274 0xE10, 0xFFFFFFFF, 0x04040404,
275 0xE14, 0xFFFFFFFF, 0x00020404,
276 0xE18, 0xFFFFFFFF, 0x00000000,
277 0xE1C, 0xFFFFFFFF, 0x00000000,
278 0xE00, 0xFFFFFFFF, 0x00000000,
279 0xE04, 0xFFFFFFFF, 0x00000000,
280 0xE08, 0x0000FF00, 0x00000000,
281 0x86C, 0xFFFFFF00, 0x00000000,
282 0xE10, 0xFFFFFFFF, 0x00000000,
283 0xE14, 0xFFFFFFFF, 0x00000000,
284 0xE18, 0xFFFFFFFF, 0x00000000,
285 0xE1C, 0xFFFFFFFF, 0x00000000,
286 0xE00, 0xFFFFFFFF, 0x00000000,
287 0xE04, 0xFFFFFFFF, 0x00000000,
288 0xE08, 0x0000FF00, 0x00000000,
289 0x86C, 0xFFFFFF00, 0x00000000,
290 0xE10, 0xFFFFFFFF, 0x00000000,
291 0xE14, 0xFFFFFFFF, 0x00000000,
292 0xE18, 0xFFFFFFFF, 0x00000000,
293 0xE1C, 0xFFFFFFFF, 0x00000000,
294 0xE00, 0xFFFFFFFF, 0x00000000,
295 0xE04, 0xFFFFFFFF, 0x00000000,
296 0xE08, 0x0000FF00, 0x00000000,
297 0x86C, 0xFFFFFF00, 0x00000000,
298 0xE10, 0xFFFFFFFF, 0x00000000,
299 0xE14, 0xFFFFFFFF, 0x00000000,
300 0xE18, 0xFFFFFFFF, 0x00000000,
301 0xE1C, 0xFFFFFFFF, 0x00000000,
302 0xE00, 0xFFFFFFFF, 0x00000000,
303 0xE04, 0xFFFFFFFF, 0x00000000,
304 0xE08, 0x0000FF00, 0x00000000,
305 0x86C, 0xFFFFFF00, 0x00000000,
306 0xE10, 0xFFFFFFFF, 0x00000000,
307 0xE14, 0xFFFFFFFF, 0x00000000,
308 0xE18, 0xFFFFFFFF, 0x00000000,
309 0xE1C, 0xFFFFFFFF, 0x00000000,
310 0xE00, 0xFFFFFFFF, 0x00000000,
311 0xE04, 0xFFFFFFFF, 0x00000000,
312 0xE08, 0x0000FF00, 0x00000000,
313 0x86C, 0xFFFFFF00, 0x00000000,
314 0xE10, 0xFFFFFFFF, 0x00000000,
315 0xE14, 0xFFFFFFFF, 0x00000000,
316 0xE18, 0xFFFFFFFF, 0x00000000,
317 0xE1C, 0xFFFFFFFF, 0x00000000,
318
319};
320
321u32 RTL8188EE_RADIOA_1TARRAY[] = {
322 0x000, 0x00030000,
323 0x008, 0x00084000,
324 0x018, 0x00000407,
325 0x019, 0x00000012,
326 0x01E, 0x00080009,
327 0x01F, 0x00000880,
328 0x02F, 0x0001A060,
329 0x03F, 0x00000000,
330 0x042, 0x000060C0,
331 0x057, 0x000D0000,
332 0x058, 0x000BE180,
333 0x067, 0x00001552,
334 0x083, 0x00000000,
335 0x0B0, 0x000FF8FC,
336 0x0B1, 0x00054400,
337 0x0B2, 0x000CCC19,
338 0x0B4, 0x00043003,
339 0x0B6, 0x0004953E,
340 0x0B7, 0x0001C718,
341 0x0B8, 0x000060FF,
342 0x0B9, 0x00080001,
343 0x0BA, 0x00040000,
344 0x0BB, 0x00000400,
345 0x0BF, 0x000C0000,
346 0x0C2, 0x00002400,
347 0x0C3, 0x00000009,
348 0x0C4, 0x00040C91,
349 0x0C5, 0x00099999,
350 0x0C6, 0x000000A3,
351 0x0C7, 0x00088820,
352 0x0C8, 0x00076C06,
353 0x0C9, 0x00000000,
354 0x0CA, 0x00080000,
355 0x0DF, 0x00000180,
356 0x0EF, 0x000001A0,
357 0x051, 0x0006B27D,
358 0x052, 0x0007E49D,
359 0x053, 0x00000073,
360 0x056, 0x00051FF3,
361 0x035, 0x00000086,
362 0x035, 0x00000186,
363 0x035, 0x00000286,
364 0x036, 0x00001C25,
365 0x036, 0x00009C25,
366 0x036, 0x00011C25,
367 0x036, 0x00019C25,
368 0x0B6, 0x00048538,
369 0x018, 0x00000C07,
370 0x05A, 0x0004BD00,
371 0x019, 0x000739D0,
372 0x034, 0x0000ADF3,
373 0x034, 0x00009DF0,
374 0x034, 0x00008DED,
375 0x034, 0x00007DEA,
376 0x034, 0x00006DE7,
377 0x034, 0x000054EE,
378 0x034, 0x000044EB,
379 0x034, 0x000034E8,
380 0x034, 0x0000246B,
381 0x034, 0x00001468,
382 0x034, 0x0000006D,
383 0x000, 0x00030159,
384 0x084, 0x00068200,
385 0x086, 0x000000CE,
386 0x087, 0x00048A00,
387 0x08E, 0x00065540,
388 0x08F, 0x00088000,
389 0x0EF, 0x000020A0,
390 0x03B, 0x000F02B0,
391 0x03B, 0x000EF7B0,
392 0x03B, 0x000D4FB0,
393 0x03B, 0x000CF060,
394 0x03B, 0x000B0090,
395 0x03B, 0x000A0080,
396 0x03B, 0x00090080,
397 0x03B, 0x0008F780,
398 0x03B, 0x000722B0,
399 0x03B, 0x0006F7B0,
400 0x03B, 0x00054FB0,
401 0x03B, 0x0004F060,
402 0x03B, 0x00030090,
403 0x03B, 0x00020080,
404 0x03B, 0x00010080,
405 0x03B, 0x0000F780,
406 0x0EF, 0x000000A0,
407 0x000, 0x00010159,
408 0x018, 0x0000F407,
409 0xFFE, 0x00000000,
410 0xFFE, 0x00000000,
411 0x01F, 0x00080003,
412 0xFFE, 0x00000000,
413 0xFFE, 0x00000000,
414 0x01E, 0x00000001,
415 0x01F, 0x00080000,
416 0x000, 0x00033E60,
417
418};
419
420u32 RTL8188EEMAC_1T_ARRAY[] = {
421 0x026, 0x00000041,
422 0x027, 0x00000035,
423 0x428, 0x0000000A,
424 0x429, 0x00000010,
425 0x430, 0x00000000,
426 0x431, 0x00000001,
427 0x432, 0x00000002,
428 0x433, 0x00000004,
429 0x434, 0x00000005,
430 0x435, 0x00000006,
431 0x436, 0x00000007,
432 0x437, 0x00000008,
433 0x438, 0x00000000,
434 0x439, 0x00000000,
435 0x43A, 0x00000001,
436 0x43B, 0x00000002,
437 0x43C, 0x00000004,
438 0x43D, 0x00000005,
439 0x43E, 0x00000006,
440 0x43F, 0x00000007,
441 0x440, 0x0000005D,
442 0x441, 0x00000001,
443 0x442, 0x00000000,
444 0x444, 0x00000015,
445 0x445, 0x000000F0,
446 0x446, 0x0000000F,
447 0x447, 0x00000000,
448 0x458, 0x00000041,
449 0x459, 0x000000A8,
450 0x45A, 0x00000072,
451 0x45B, 0x000000B9,
452 0x460, 0x00000066,
453 0x461, 0x00000066,
454 0x480, 0x00000008,
455 0x4C8, 0x000000FF,
456 0x4C9, 0x00000008,
457 0x4CC, 0x000000FF,
458 0x4CD, 0x000000FF,
459 0x4CE, 0x00000001,
460 0x4D3, 0x00000001,
461 0x500, 0x00000026,
462 0x501, 0x000000A2,
463 0x502, 0x0000002F,
464 0x503, 0x00000000,
465 0x504, 0x00000028,
466 0x505, 0x000000A3,
467 0x506, 0x0000005E,
468 0x507, 0x00000000,
469 0x508, 0x0000002B,
470 0x509, 0x000000A4,
471 0x50A, 0x0000005E,
472 0x50B, 0x00000000,
473 0x50C, 0x0000004F,
474 0x50D, 0x000000A4,
475 0x50E, 0x00000000,
476 0x50F, 0x00000000,
477 0x512, 0x0000001C,
478 0x514, 0x0000000A,
479 0x516, 0x0000000A,
480 0x525, 0x0000004F,
481 0x550, 0x00000010,
482 0x551, 0x00000010,
483 0x559, 0x00000002,
484 0x55D, 0x000000FF,
485 0x605, 0x00000030,
486 0x608, 0x0000000E,
487 0x609, 0x0000002A,
488 0x620, 0x000000FF,
489 0x621, 0x000000FF,
490 0x622, 0x000000FF,
491 0x623, 0x000000FF,
492 0x624, 0x000000FF,
493 0x625, 0x000000FF,
494 0x626, 0x000000FF,
495 0x627, 0x000000FF,
496 0x652, 0x00000020,
497 0x63C, 0x0000000A,
498 0x63D, 0x0000000A,
499 0x63E, 0x0000000E,
500 0x63F, 0x0000000E,
501 0x640, 0x00000040,
502 0x66E, 0x00000005,
503 0x700, 0x00000021,
504 0x701, 0x00000043,
505 0x702, 0x00000065,
506 0x703, 0x00000087,
507 0x708, 0x00000021,
508 0x709, 0x00000043,
509 0x70A, 0x00000065,
510 0x70B, 0x00000087,
511
512};
513
514u32 RTL8188EEAGCTAB_1TARRAY[] = {
515 0xC78, 0xFB000001,
516 0xC78, 0xFB010001,
517 0xC78, 0xFB020001,
518 0xC78, 0xFB030001,
519 0xC78, 0xFB040001,
520 0xC78, 0xFB050001,
521 0xC78, 0xFA060001,
522 0xC78, 0xF9070001,
523 0xC78, 0xF8080001,
524 0xC78, 0xF7090001,
525 0xC78, 0xF60A0001,
526 0xC78, 0xF50B0001,
527 0xC78, 0xF40C0001,
528 0xC78, 0xF30D0001,
529 0xC78, 0xF20E0001,
530 0xC78, 0xF10F0001,
531 0xC78, 0xF0100001,
532 0xC78, 0xEF110001,
533 0xC78, 0xEE120001,
534 0xC78, 0xED130001,
535 0xC78, 0xEC140001,
536 0xC78, 0xEB150001,
537 0xC78, 0xEA160001,
538 0xC78, 0xE9170001,
539 0xC78, 0xE8180001,
540 0xC78, 0xE7190001,
541 0xC78, 0xE61A0001,
542 0xC78, 0xE51B0001,
543 0xC78, 0xE41C0001,
544 0xC78, 0xE31D0001,
545 0xC78, 0xE21E0001,
546 0xC78, 0xE11F0001,
547 0xC78, 0x8A200001,
548 0xC78, 0x89210001,
549 0xC78, 0x88220001,
550 0xC78, 0x87230001,
551 0xC78, 0x86240001,
552 0xC78, 0x85250001,
553 0xC78, 0x84260001,
554 0xC78, 0x83270001,
555 0xC78, 0x82280001,
556 0xC78, 0x6B290001,
557 0xC78, 0x6A2A0001,
558 0xC78, 0x692B0001,
559 0xC78, 0x682C0001,
560 0xC78, 0x672D0001,
561 0xC78, 0x662E0001,
562 0xC78, 0x652F0001,
563 0xC78, 0x64300001,
564 0xC78, 0x63310001,
565 0xC78, 0x62320001,
566 0xC78, 0x61330001,
567 0xC78, 0x46340001,
568 0xC78, 0x45350001,
569 0xC78, 0x44360001,
570 0xC78, 0x43370001,
571 0xC78, 0x42380001,
572 0xC78, 0x41390001,
573 0xC78, 0x403A0001,
574 0xC78, 0x403B0001,
575 0xC78, 0x403C0001,
576 0xC78, 0x403D0001,
577 0xC78, 0x403E0001,
578 0xC78, 0x403F0001,
579 0xC78, 0xFB400001,
580 0xC78, 0xFB410001,
581 0xC78, 0xFB420001,
582 0xC78, 0xFB430001,
583 0xC78, 0xFB440001,
584 0xC78, 0xFB450001,
585 0xC78, 0xFB460001,
586 0xC78, 0xFB470001,
587 0xC78, 0xFB480001,
588 0xC78, 0xFA490001,
589 0xC78, 0xF94A0001,
590 0xC78, 0xF84B0001,
591 0xC78, 0xF74C0001,
592 0xC78, 0xF64D0001,
593 0xC78, 0xF54E0001,
594 0xC78, 0xF44F0001,
595 0xC78, 0xF3500001,
596 0xC78, 0xF2510001,
597 0xC78, 0xF1520001,
598 0xC78, 0xF0530001,
599 0xC78, 0xEF540001,
600 0xC78, 0xEE550001,
601 0xC78, 0xED560001,
602 0xC78, 0xEC570001,
603 0xC78, 0xEB580001,
604 0xC78, 0xEA590001,
605 0xC78, 0xE95A0001,
606 0xC78, 0xE85B0001,
607 0xC78, 0xE75C0001,
608 0xC78, 0xE65D0001,
609 0xC78, 0xE55E0001,
610 0xC78, 0xE45F0001,
611 0xC78, 0xE3600001,
612 0xC78, 0xE2610001,
613 0xC78, 0xC3620001,
614 0xC78, 0xC2630001,
615 0xC78, 0xC1640001,
616 0xC78, 0x8B650001,
617 0xC78, 0x8A660001,
618 0xC78, 0x89670001,
619 0xC78, 0x88680001,
620 0xC78, 0x87690001,
621 0xC78, 0x866A0001,
622 0xC78, 0x856B0001,
623 0xC78, 0x846C0001,
624 0xC78, 0x676D0001,
625 0xC78, 0x666E0001,
626 0xC78, 0x656F0001,
627 0xC78, 0x64700001,
628 0xC78, 0x63710001,
629 0xC78, 0x62720001,
630 0xC78, 0x61730001,
631 0xC78, 0x60740001,
632 0xC78, 0x46750001,
633 0xC78, 0x45760001,
634 0xC78, 0x44770001,
635 0xC78, 0x43780001,
636 0xC78, 0x42790001,
637 0xC78, 0x417A0001,
638 0xC78, 0x407B0001,
639 0xC78, 0x407C0001,
640 0xC78, 0x407D0001,
641 0xC78, 0x407E0001,
642 0xC78, 0x407F0001,
643};
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/table.h b/drivers/net/wireless/rtlwifi/rtl8188ee/table.h
new file mode 100644
index 000000000000..c1218e835129
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/table.h
@@ -0,0 +1,47 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Created on 2010/ 5/18, 1:41
27 *
28 * Larry Finger <Larry.Finger@lwfinger.net>
29 *
30 *****************************************************************************/
31
32#ifndef __RTL92CE_TABLE__H_
33#define __RTL92CE_TABLE__H_
34
35#include <linux/types.h>
36#define RTL8188EEPHY_REG_1TARRAYLEN 382
37extern u32 RTL8188EEPHY_REG_1TARRAY[];
38#define RTL8188EEPHY_REG_ARRAY_PGLEN 264
39extern u32 RTL8188EEPHY_REG_ARRAY_PG[];
40#define RTL8188EE_RADIOA_1TARRAYLEN 190
41extern u32 RTL8188EE_RADIOA_1TARRAY[];
42#define RTL8188EEMAC_1T_ARRAYLEN 180
43extern u32 RTL8188EEMAC_1T_ARRAY[];
44#define RTL8188EEAGCTAB_1TARRAYLEN 256
45extern u32 RTL8188EEAGCTAB_1TARRAY[];
46
47#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/trx.c b/drivers/net/wireless/rtlwifi/rtl8188ee/trx.c
new file mode 100644
index 000000000000..251853178de2
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/trx.c
@@ -0,0 +1,817 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "pci.h"
32#include "base.h"
33#include "stats.h"
34#include "reg.h"
35#include "def.h"
36#include "phy.h"
37#include "trx.h"
38#include "led.h"
39#include "dm.h"
40
41static u8 _rtl88ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
42{
43 __le16 fc = rtl_get_fc(skb);
44
45 if (unlikely(ieee80211_is_beacon(fc)))
46 return QSLT_BEACON;
47 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
48 return QSLT_MGNT;
49
50 return skb->priority;
51}
52
53static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
54 struct rtl_stats *pstatus, u8 *pdesc,
55 struct rx_fwinfo_88e *p_drvinfo,
56 bool bpacket_match_bssid,
57 bool bpacket_toself, bool packet_beacon)
58{
59 struct rtl_priv *rtlpriv = rtl_priv(hw);
60 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
61 struct phy_sts_cck_8192s_t *cck_buf;
62 struct phy_status_rpt *phystrpt = (struct phy_status_rpt *)p_drvinfo;
63 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
64 char rx_pwr_all = 0, rx_pwr[4];
65 u8 rf_rx_num = 0, evm, pwdb_all;
66 u8 i, max_spatial_stream;
67 u32 rssi, total_rssi = 0;
68 bool is_cck = pstatus->is_cck;
69 u8 lan_idx, vga_idx;
70
71 /* Record it for next packet processing */
72 pstatus->packet_matchbssid = bpacket_match_bssid;
73 pstatus->packet_toself = bpacket_toself;
74 pstatus->packet_beacon = packet_beacon;
75 pstatus->rx_mimo_sig_qual[0] = -1;
76 pstatus->rx_mimo_sig_qual[1] = -1;
77
78 if (is_cck) {
79 u8 cck_hipwr;
80 u8 cck_agc_rpt;
81 /* CCK Driver info Structure is not the same as OFDM packet. */
82 cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
83 cck_agc_rpt = cck_buf->cck_agc_rpt;
84
85 /* (1)Hardware does not provide RSSI for CCK
86 * (2)PWDB, Average PWDB cacluated by
87 * hardware (for rate adaptive)
88 */
89 if (ppsc->rfpwr_state == ERFON)
90 cck_hipwr = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
91 BIT(9));
92 else
93 cck_hipwr = false;
94
95 lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
96 vga_idx = (cck_agc_rpt & 0x1f);
97 switch (lan_idx) {
98 case 7:
99 if (vga_idx <= 27)
100 rx_pwr_all = -100 + 2 * (27 - vga_idx);
101 else
102 rx_pwr_all = -100;
103 break;
104 case 6:
105 rx_pwr_all = -48 + 2 * (2 - vga_idx); /*VGA_idx = 2~0*/
106 break;
107 case 5:
108 rx_pwr_all = -42 + 2 * (7 - vga_idx); /*VGA_idx = 7~5*/
109 break;
110 case 4:
111 rx_pwr_all = -36 + 2 * (7 - vga_idx); /*VGA_idx = 7~4*/
112 break;
113 case 3:
114 rx_pwr_all = -24 + 2 * (7 - vga_idx); /*VGA_idx = 7~0*/
115 break;
116 case 2:
117 if (cck_hipwr)
118 rx_pwr_all = -12 + 2 * (5 - vga_idx);
119 else
120 rx_pwr_all = -6 + 2 * (5 - vga_idx);
121 break;
122 case 1:
123 rx_pwr_all = 8 - 2 * vga_idx;
124 break;
125 case 0:
126 rx_pwr_all = 14 - 2 * vga_idx;
127 break;
128 default:
129 break;
130 }
131 rx_pwr_all += 6;
132 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
133 /* CCK gain is smaller than OFDM/MCS gain,
134 * so we add gain diff by experiences,
135 * the val is 6
136 */
137 pwdb_all += 6;
138 if (pwdb_all > 100)
139 pwdb_all = 100;
140 /* modify the offset to make the same
141 * gain index with OFDM.
142 */
143 if (pwdb_all > 34 && pwdb_all <= 42)
144 pwdb_all -= 2;
145 else if (pwdb_all > 26 && pwdb_all <= 34)
146 pwdb_all -= 6;
147 else if (pwdb_all > 14 && pwdb_all <= 26)
148 pwdb_all -= 8;
149 else if (pwdb_all > 4 && pwdb_all <= 14)
150 pwdb_all -= 4;
151 if (cck_hipwr == false) {
152 if (pwdb_all >= 80)
153 pwdb_all = ((pwdb_all - 80)<<1) +
154 ((pwdb_all - 80)>>1) + 80;
155 else if ((pwdb_all <= 78) && (pwdb_all >= 20))
156 pwdb_all += 3;
157 if (pwdb_all > 100)
158 pwdb_all = 100;
159 }
160
161 pstatus->rx_pwdb_all = pwdb_all;
162 pstatus->recvsignalpower = rx_pwr_all;
163
164 /* (3) Get Signal Quality (EVM) */
165 if (bpacket_match_bssid) {
166 u8 sq;
167
168 if (pstatus->rx_pwdb_all > 40) {
169 sq = 100;
170 } else {
171 sq = cck_buf->sq_rpt;
172 if (sq > 64)
173 sq = 0;
174 else if (sq < 20)
175 sq = 100;
176 else
177 sq = ((64 - sq) * 100) / 44;
178 }
179
180 pstatus->signalquality = sq;
181 pstatus->rx_mimo_sig_qual[0] = sq;
182 pstatus->rx_mimo_sig_qual[1] = -1;
183 }
184 } else {
185 rtlpriv->dm.rfpath_rxenable[0] =
186 rtlpriv->dm.rfpath_rxenable[1] = true;
187
188 /* (1)Get RSSI for HT rate */
189 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
190 /* we will judge RF RX path now. */
191 if (rtlpriv->dm.rfpath_rxenable[i])
192 rf_rx_num++;
193
194 rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f) * 2)-110;
195
196 /* Translate DBM to percentage. */
197 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
198 total_rssi += rssi;
199
200 /* Get Rx snr value in DB */
201 rtlpriv->stats.rx_snr_db[i] = p_drvinfo->rxsnr[i] / 2;
202
203 /* Record Signal Strength for next packet */
204 if (bpacket_match_bssid)
205 pstatus->rx_mimo_signalstrength[i] = (u8) rssi;
206 }
207
208 /* (2)PWDB, Average PWDB cacluated by
209 * hardware (for rate adaptive)
210 */
211 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
212
213 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
214 pstatus->rx_pwdb_all = pwdb_all;
215 pstatus->rxpower = rx_pwr_all;
216 pstatus->recvsignalpower = rx_pwr_all;
217
218 /* (3)EVM of HT rate */
219 if (pstatus->is_ht && pstatus->rate >= DESC92C_RATEMCS8 &&
220 pstatus->rate <= DESC92C_RATEMCS15)
221 max_spatial_stream = 2;
222 else
223 max_spatial_stream = 1;
224
225 for (i = 0; i < max_spatial_stream; i++) {
226 evm = rtl_evm_db_to_percentage(p_drvinfo->rxevm[i]);
227
228 if (bpacket_match_bssid) {
229 /* Fill value in RFD, Get the first
230 * spatial stream only
231 */
232 if (i == 0)
233 pstatus->signalquality = evm & 0xff;
234 pstatus->rx_mimo_sig_qual[i] = evm & 0xff;
235 }
236 }
237 }
238
239 /* UI BSS List signal strength(in percentage),
240 * make it good looking, from 0~100.
241 */
242 if (is_cck)
243 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
244 pwdb_all));
245 else if (rf_rx_num != 0)
246 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
247 total_rssi /= rf_rx_num));
248 /*HW antenna diversity*/
249 rtldm->fat_table.antsel_rx_keep_0 = phystrpt->ant_sel;
250 rtldm->fat_table.antsel_rx_keep_1 = phystrpt->ant_sel_b;
251 rtldm->fat_table.antsel_rx_keep_2 = phystrpt->antsel_rx_keep_2;
252}
253
254static void _rtl88ee_smart_antenna(struct ieee80211_hw *hw,
255 struct rtl_stats *pstatus)
256{
257 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
258 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
259 u8 ant_mux;
260 struct fast_ant_training *pfat = &(rtldm->fat_table);
261
262 if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV) {
263 if (pfat->fat_state == FAT_TRAINING_STATE) {
264 if (pstatus->packet_toself) {
265 ant_mux = (pfat->antsel_rx_keep_2 << 2) |
266 (pfat->antsel_rx_keep_1 << 1) |
267 pfat->antsel_rx_keep_0;
268 pfat->ant_sum[ant_mux] += pstatus->rx_pwdb_all;
269 pfat->ant_cnt[ant_mux]++;
270 }
271 }
272 } else if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
273 (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)) {
274 if (pstatus->packet_toself || pstatus->packet_matchbssid) {
275 ant_mux = (pfat->antsel_rx_keep_2 << 2) |
276 (pfat->antsel_rx_keep_1 << 1) |
277 pfat->antsel_rx_keep_0;
278 rtl88e_dm_ant_sel_statistics(hw, ant_mux, 0,
279 pstatus->rx_pwdb_all);
280 }
281 }
282}
283
284static void _rtl88ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
285 struct sk_buff *skb, struct rtl_stats *pstatus,
286 u8 *pdesc, struct rx_fwinfo_88e *p_drvinfo)
287{
288 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
289 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
290 struct ieee80211_hdr *hdr;
291 u8 *tmp_buf;
292 u8 *praddr;
293 u8 *psaddr;
294 __le16 fc;
295 u16 type, ufc;
296 bool match_bssid, packet_toself, packet_beacon, addr;
297
298 tmp_buf = skb->data + pstatus->rx_drvinfo_size + pstatus->rx_bufshift;
299
300 hdr = (struct ieee80211_hdr *)tmp_buf;
301 fc = hdr->frame_control;
302 ufc = le16_to_cpu(fc);
303 type = WLAN_FC_GET_TYPE(fc);
304 praddr = hdr->addr1;
305 psaddr = ieee80211_get_SA(hdr);
306 memcpy(pstatus->psaddr, psaddr, ETH_ALEN);
307
308 addr = (!compare_ether_addr(mac->bssid, (ufc & IEEE80211_FCTL_TODS) ?
309 hdr->addr1 : (ufc & IEEE80211_FCTL_FROMDS) ?
310 hdr->addr2 : hdr->addr3));
311 match_bssid = ((IEEE80211_FTYPE_CTL != type) && (!pstatus->hwerror) &&
312 (!pstatus->crc) && (!pstatus->icv)) && addr;
313
314 addr = (!compare_ether_addr(praddr, rtlefuse->dev_addr));
315 packet_toself = match_bssid && addr;
316
317 if (ieee80211_is_beacon(fc))
318 packet_beacon = true;
319
320 _rtl88ee_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
321 match_bssid, packet_toself, packet_beacon);
322 _rtl88ee_smart_antenna(hw, pstatus);
323 rtl_process_phyinfo(hw, tmp_buf, pstatus);
324}
325
326static void insert_em(struct rtl_tcb_desc *ptcb_desc, u8 *virtualaddress)
327{
328 u32 dwtmp = 0;
329
330 memset(virtualaddress, 0, 8);
331
332 SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
333 if (ptcb_desc->empkt_num == 1) {
334 dwtmp = ptcb_desc->empkt_len[0];
335 } else {
336 dwtmp = ptcb_desc->empkt_len[0];
337 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
338 dwtmp += ptcb_desc->empkt_len[1];
339 }
340 SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
341
342 if (ptcb_desc->empkt_num <= 3) {
343 dwtmp = ptcb_desc->empkt_len[2];
344 } else {
345 dwtmp = ptcb_desc->empkt_len[2];
346 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
347 dwtmp += ptcb_desc->empkt_len[3];
348 }
349 SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
350 if (ptcb_desc->empkt_num <= 5) {
351 dwtmp = ptcb_desc->empkt_len[4];
352 } else {
353 dwtmp = ptcb_desc->empkt_len[4];
354 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
355 dwtmp += ptcb_desc->empkt_len[5];
356 }
357 SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
358 SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
359 if (ptcb_desc->empkt_num <= 7) {
360 dwtmp = ptcb_desc->empkt_len[6];
361 } else {
362 dwtmp = ptcb_desc->empkt_len[6];
363 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
364 dwtmp += ptcb_desc->empkt_len[7];
365 }
366 SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
367 if (ptcb_desc->empkt_num <= 9) {
368 dwtmp = ptcb_desc->empkt_len[8];
369 } else {
370 dwtmp = ptcb_desc->empkt_len[8];
371 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
372 dwtmp += ptcb_desc->empkt_len[9];
373 }
374 SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
375}
376
377bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,
378 struct rtl_stats *status,
379 struct ieee80211_rx_status *rx_status,
380 u8 *pdesc, struct sk_buff *skb)
381{
382 struct rtl_priv *rtlpriv = rtl_priv(hw);
383 struct rx_fwinfo_88e *p_drvinfo;
384 struct ieee80211_hdr *hdr;
385
386 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
387 status->packet_report_type = (u8)GET_RX_STATUS_DESC_RPT_SEL(pdesc);
388 if (status->packet_report_type == TX_REPORT2)
389 status->length = (u16) GET_RX_RPT2_DESC_PKT_LEN(pdesc);
390 else
391 status->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
392 status->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
393 RX_DRV_INFO_SIZE_UNIT;
394 status->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
395 status->icv = (u16) GET_RX_DESC_ICV(pdesc);
396 status->crc = (u16) GET_RX_DESC_CRC32(pdesc);
397 status->hwerror = (status->crc | status->icv);
398 status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
399 status->rate = (u8) GET_RX_DESC_RXMCS(pdesc);
400 status->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
401 status->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
402 status->isfirst_ampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1) &&
403 (GET_RX_DESC_FAGGR(pdesc) == 1));
404 if (status->packet_report_type == NORMAL_RX)
405 status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
406 status->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
407 status->is_ht = (bool)GET_RX_DESC_RXHT(pdesc);
408
409 status->is_cck = RTL8188_RX_HAL_IS_CCK_RATE(status->rate);
410
411 status->macid = GET_RX_DESC_MACID(pdesc);
412 if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
413 status->wake_match = BIT(2);
414 else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
415 status->wake_match = BIT(1);
416 else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc))
417 status->wake_match = BIT(0);
418 else
419 status->wake_match = 0;
420 if (status->wake_match)
421 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
422 "Get Wakeup Packet!! WakeMatch =%d\n",
423 status->wake_match);
424 rx_status->freq = hw->conf.channel->center_freq;
425 rx_status->band = hw->conf.channel->band;
426
427 if (status->crc)
428 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
429
430 if (status->rx_is40Mhzpacket)
431 rx_status->flag |= RX_FLAG_40MHZ;
432
433 if (status->is_ht)
434 rx_status->flag |= RX_FLAG_HT;
435
436 rx_status->flag |= RX_FLAG_MACTIME_START;
437
438 /* hw will set status->decrypted true, if it finds the
439 * frame is open data frame or mgmt frame.
440 * So hw will not decryption robust managment frame
441 * for IEEE80211w but still set status->decrypted
442 * true, so here we should set it back to undecrypted
443 * for IEEE80211w frame, and mac80211 sw will help
444 * to decrypt it
445 */
446 if (status->decrypted) {
447 hdr = (struct ieee80211_hdr *)(skb->data +
448 status->rx_drvinfo_size + status->rx_bufshift);
449
450 if (!hdr) {
451 /* During testing, hdr was NULL */
452 return false;
453 }
454 if ((ieee80211_is_robust_mgmt_frame(hdr)) &&
455 (ieee80211_has_protected(hdr->frame_control)))
456 rx_status->flag &= ~RX_FLAG_DECRYPTED;
457 else
458 rx_status->flag |= RX_FLAG_DECRYPTED;
459 }
460
461 /* rate_idx: index of data rate into band's
462 * supported rates or MCS index if HT rates
463 * are use (RX_FLAG_HT)
464 * Notice: this is diff with windows define
465 */
466 rx_status->rate_idx = rtlwifi_rate_mapping(hw, status->is_ht,
467 status->rate, false);
468
469 rx_status->mactime = status->timestamp_low;
470 if (phystatus == true) {
471 p_drvinfo = (struct rx_fwinfo_88e *)(skb->data +
472 status->rx_bufshift);
473
474 _rtl88ee_translate_rx_signal_stuff(hw, skb, status, pdesc,
475 p_drvinfo);
476 }
477
478 /*rx_status->qual = status->signal; */
479 rx_status->signal = status->recvsignalpower + 10;
480 /*rx_status->noise = -status->noise; */
481 if (status->packet_report_type == TX_REPORT2) {
482 status->macid_valid_entry[0] =
483 GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
484 status->macid_valid_entry[1] =
485 GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
486 }
487 return true;
488}
489
490void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
491 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
492 struct ieee80211_tx_info *info,
493 struct ieee80211_sta *sta,
494 struct sk_buff *skb,
495 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
496{
497 struct rtl_priv *rtlpriv = rtl_priv(hw);
498 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
499 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
500 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
501 u8 *pdesc = (u8 *)pdesc_tx;
502 u16 seq_number;
503 __le16 fc = hdr->frame_control;
504 unsigned int buf_len = 0;
505 unsigned int skb_len = skb->len;
506 u8 fw_qsel = _rtl88ee_map_hwqueue_to_fwqueue(skb, hw_queue);
507 bool firstseg = ((hdr->seq_ctrl &
508 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
509 bool lastseg = ((hdr->frame_control &
510 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
511 dma_addr_t mapping;
512 u8 bw_40 = 0;
513 u8 short_gi = 0;
514
515 if (mac->opmode == NL80211_IFTYPE_STATION) {
516 bw_40 = mac->bw_40;
517 } else if (mac->opmode == NL80211_IFTYPE_AP ||
518 mac->opmode == NL80211_IFTYPE_ADHOC) {
519 if (sta)
520 bw_40 = sta->ht_cap.cap &
521 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
522 }
523 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
524 rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
525 /* reserve 8 byte for AMPDU early mode */
526 if (rtlhal->earlymode_enable) {
527 skb_push(skb, EM_HDR_LEN);
528 memset(skb->data, 0, EM_HDR_LEN);
529 }
530 buf_len = skb->len;
531 mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
532 PCI_DMA_TODEVICE);
533 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
534 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
535 "DMA mapping error");
536 return;
537 }
538 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_88e));
539 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
540 firstseg = true;
541 lastseg = true;
542 }
543 if (firstseg) {
544 if (rtlhal->earlymode_enable) {
545 SET_TX_DESC_PKT_OFFSET(pdesc, 1);
546 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN +
547 EM_HDR_LEN);
548 if (ptcb_desc->empkt_num) {
549 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
550 "Insert 8 byte.pTcb->EMPktNum:%d\n",
551 ptcb_desc->empkt_num);
552 insert_em(ptcb_desc, (u8 *)(skb->data));
553 }
554 } else {
555 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
556 }
557
558 ptcb_desc->use_driver_rate = true;
559 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
560 if (ptcb_desc->hw_rate > DESC92C_RATEMCS0)
561 short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
562 else
563 short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
564 SET_TX_DESC_DATA_SHORTGI(pdesc, short_gi);
565
566 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
567 SET_TX_DESC_AGG_ENABLE(pdesc, 1);
568 SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
569 }
570 SET_TX_DESC_SEQ(pdesc, seq_number);
571 SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable &&
572 !ptcb_desc->cts_enable) ? 1 : 0));
573 SET_TX_DESC_HW_RTS_ENABLE(pdesc, 0);
574 SET_TX_DESC_CTS2SELF(pdesc, ((ptcb_desc->cts_enable) ? 1 : 0));
575 SET_TX_DESC_RTS_STBC(pdesc, ((ptcb_desc->rts_stbc) ? 1 : 0));
576
577 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
578 SET_TX_DESC_RTS_BW(pdesc, 0);
579 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
580 SET_TX_DESC_RTS_SHORT(pdesc,
581 ((ptcb_desc->rts_rate <= DESC92C_RATE54M) ?
582 (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
583 (ptcb_desc->rts_use_shortgi ? 1 : 0)));
584
585 if (ptcb_desc->btx_enable_sw_calc_duration)
586 SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
587
588 if (bw_40) {
589 if (ptcb_desc->packet_bw) {
590 SET_TX_DESC_DATA_BW(pdesc, 1);
591 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
592 } else {
593 SET_TX_DESC_DATA_BW(pdesc, 0);
594 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
595 mac->cur_40_prime_sc);
596 }
597 } else {
598 SET_TX_DESC_DATA_BW(pdesc, 0);
599 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
600 }
601
602 SET_TX_DESC_LINIP(pdesc, 0);
603 SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb_len);
604 if (sta) {
605 u8 ampdu_density = sta->ht_cap.ampdu_density;
606 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
607 }
608 if (info->control.hw_key) {
609 struct ieee80211_key_conf *keyconf;
610 keyconf = info->control.hw_key;
611 switch (keyconf->cipher) {
612 case WLAN_CIPHER_SUITE_WEP40:
613 case WLAN_CIPHER_SUITE_WEP104:
614 case WLAN_CIPHER_SUITE_TKIP:
615 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
616 break;
617 case WLAN_CIPHER_SUITE_CCMP:
618 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
619 break;
620 default:
621 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
622 break;
623 }
624 }
625
626 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
627 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
628 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
629 SET_TX_DESC_DISABLE_FB(pdesc, ptcb_desc->disable_ratefallback ?
630 1 : 0);
631 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
632
633 /* Set TxRate and RTSRate in TxDesc */
634 /* This prevent Tx initial rate of new-coming packets */
635 /* from being overwritten by retried packet rate.*/
636 if (!ptcb_desc->use_driver_rate) {
637 /*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */
638 /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
639 }
640 if (ieee80211_is_data_qos(fc)) {
641 if (mac->rdg_en) {
642 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
643 "Enable RDG function.\n");
644 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
645 SET_TX_DESC_HTC(pdesc, 1);
646 }
647 }
648 }
649
650 SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
651 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
652 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) buf_len);
653 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
654 if (rtlpriv->dm.useramask) {
655 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
656 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
657 } else {
658 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
659 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
660 }
661 if (ieee80211_is_data_qos(fc))
662 SET_TX_DESC_QOS(pdesc, 1);
663
664 if (!ieee80211_is_data_qos(fc))
665 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
666 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
667 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
668 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
669 SET_TX_DESC_BMC(pdesc, 1);
670
671 rtl88e_dm_set_tx_ant_by_tx_info(hw, pdesc, ptcb_desc->mac_id);
672 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
673}
674
675void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
676 u8 *pdesc, bool firstseg,
677 bool lastseg, struct sk_buff *skb)
678{
679 struct rtl_priv *rtlpriv = rtl_priv(hw);
680 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
681 u8 fw_queue = QSLT_BEACON;
682
683 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
684 skb->data, skb->len,
685 PCI_DMA_TODEVICE);
686
687 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
688 __le16 fc = hdr->frame_control;
689
690 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
691 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
692 "DMA mapping error");
693 return;
694 }
695 CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
696
697 if (firstseg)
698 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
699
700 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
701
702 SET_TX_DESC_SEQ(pdesc, 0);
703
704 SET_TX_DESC_LINIP(pdesc, 0);
705
706 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
707
708 SET_TX_DESC_FIRST_SEG(pdesc, 1);
709 SET_TX_DESC_LAST_SEG(pdesc, 1);
710
711 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
712
713 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
714
715 SET_TX_DESC_RATE_ID(pdesc, 7);
716 SET_TX_DESC_MACID(pdesc, 0);
717
718 SET_TX_DESC_OWN(pdesc, 1);
719
720 SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len));
721
722 SET_TX_DESC_FIRST_SEG(pdesc, 1);
723 SET_TX_DESC_LAST_SEG(pdesc, 1);
724
725 SET_TX_DESC_OFFSET(pdesc, 0x20);
726
727 SET_TX_DESC_USE_RATE(pdesc, 1);
728
729 if (!ieee80211_is_data_qos(fc))
730 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
731
732 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
733 "H2C Tx Cmd Content\n",
734 pdesc, TX_DESC_SIZE);
735}
736
737void rtl88ee_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
738{
739 if (istx == true) {
740 switch (desc_name) {
741 case HW_DESC_OWN:
742 SET_TX_DESC_OWN(pdesc, 1);
743 break;
744 case HW_DESC_TX_NEXTDESC_ADDR:
745 SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val);
746 break;
747 default:
748 RT_ASSERT(false, "ERR txdesc :%d not processed\n",
749 desc_name);
750 break;
751 }
752 } else {
753 switch (desc_name) {
754 case HW_DESC_RXOWN:
755 SET_RX_DESC_OWN(pdesc, 1);
756 break;
757 case HW_DESC_RXBUFF_ADDR:
758 SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *)val);
759 break;
760 case HW_DESC_RXPKT_LEN:
761 SET_RX_DESC_PKT_LEN(pdesc, *(u32 *)val);
762 break;
763 case HW_DESC_RXERO:
764 SET_RX_DESC_EOR(pdesc, 1);
765 break;
766 default:
767 RT_ASSERT(false, "ERR rxdesc :%d not processed\n",
768 desc_name);
769 break;
770 }
771 }
772}
773
774u32 rtl88ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
775{
776 u32 ret = 0;
777
778 if (istx == true) {
779 switch (desc_name) {
780 case HW_DESC_OWN:
781 ret = GET_TX_DESC_OWN(pdesc);
782 break;
783 case HW_DESC_TXBUFF_ADDR:
784 ret = GET_TX_DESC_TX_BUFFER_ADDRESS(pdesc);
785 break;
786 default:
787 RT_ASSERT(false, "ERR txdesc :%d not processed\n",
788 desc_name);
789 break;
790 }
791 } else {
792 switch (desc_name) {
793 case HW_DESC_OWN:
794 ret = GET_RX_DESC_OWN(pdesc);
795 break;
796 case HW_DESC_RXPKT_LEN:
797 ret = GET_RX_DESC_PKT_LEN(pdesc);
798 break;
799 default:
800 RT_ASSERT(false, "ERR rxdesc :%d not processed\n",
801 desc_name);
802 break;
803 }
804 }
805 return ret;
806}
807
808void rtl88ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
809{
810 struct rtl_priv *rtlpriv = rtl_priv(hw);
811 if (hw_queue == BEACON_QUEUE) {
812 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4));
813 } else {
814 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG,
815 BIT(0) << (hw_queue));
816 }
817}
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/trx.h b/drivers/net/wireless/rtlwifi/rtl8188ee/trx.h
new file mode 100644
index 000000000000..d3a02e73f53a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/trx.h
@@ -0,0 +1,795 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CE_TRX_H__
31#define __RTL92CE_TRX_H__
32
33#define TX_DESC_SIZE 64
34#define TX_DESC_AGGR_SUBFRAME_SIZE 32
35
36#define RX_DESC_SIZE 32
37#define RX_DRV_INFO_SIZE_UNIT 8
38
39#define TX_DESC_NEXT_DESC_OFFSET 40
40#define USB_HWDESC_HEADER_LEN 32
41#define CRCLENGTH 4
42
43#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
44 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
45#define SET_TX_DESC_OFFSET(__pdesc, __val) \
46 SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
47#define SET_TX_DESC_BMC(__pdesc, __val) \
48 SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
49#define SET_TX_DESC_HTC(__pdesc, __val) \
50 SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
51#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
52 SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
53#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
54 SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
55#define SET_TX_DESC_LINIP(__pdesc, __val) \
56 SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
57#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
58 SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
59#define SET_TX_DESC_GF(__pdesc, __val) \
60 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
61#define SET_TX_DESC_OWN(__pdesc, __val) \
62 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
63
64#define GET_TX_DESC_PKT_SIZE(__pdesc) \
65 LE_BITS_TO_4BYTE(__pdesc, 0, 16)
66#define GET_TX_DESC_OFFSET(__pdesc) \
67 LE_BITS_TO_4BYTE(__pdesc, 16, 8)
68#define GET_TX_DESC_BMC(__pdesc) \
69 LE_BITS_TO_4BYTE(__pdesc, 24, 1)
70#define GET_TX_DESC_HTC(__pdesc) \
71 LE_BITS_TO_4BYTE(__pdesc, 25, 1)
72#define GET_TX_DESC_LAST_SEG(__pdesc) \
73 LE_BITS_TO_4BYTE(__pdesc, 26, 1)
74#define GET_TX_DESC_FIRST_SEG(__pdesc) \
75 LE_BITS_TO_4BYTE(__pdesc, 27, 1)
76#define GET_TX_DESC_LINIP(__pdesc) \
77 LE_BITS_TO_4BYTE(__pdesc, 28, 1)
78#define GET_TX_DESC_NO_ACM(__pdesc) \
79 LE_BITS_TO_4BYTE(__pdesc, 29, 1)
80#define GET_TX_DESC_GF(__pdesc) \
81 LE_BITS_TO_4BYTE(__pdesc, 30, 1)
82#define GET_TX_DESC_OWN(__pdesc) \
83 LE_BITS_TO_4BYTE(__pdesc, 31, 1)
84
85#define SET_TX_DESC_MACID(__pdesc, __val) \
86 SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 6, __val)
87#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
88 SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
89#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
90 SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
91#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
92 SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
93#define SET_TX_DESC_PIFS(__pdesc, __val) \
94 SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
95#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
96 SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 4, __val)
97#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
98 SET_BITS_TO_LE_4BYTE(__pdesc+4, 20, 1, __val)
99#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
100 SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
101#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
102 SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val)
103#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
104 SET_BITS_TO_LE_4BYTE(__pdesc+4, 26, 5, __val)
105#define SET_TX_DESC_PADDING_LEN(__pdesc, __val) \
106 SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 8, __val)
107
108#define GET_TX_DESC_MACID(__pdesc) \
109 LE_BITS_TO_4BYTE(__pdesc+4, 0, 5)
110#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
111 LE_BITS_TO_4BYTE(__pdesc+4, 5, 1)
112#define GET_TX_DESC_AGG_BREAK(__pdesc) \
113 LE_BITS_TO_4BYTE(__pdesc+4, 6, 1)
114#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
115 LE_BITS_TO_4BYTE(__pdesc+4, 7, 1)
116#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
117 LE_BITS_TO_4BYTE(__pdesc+4, 8, 5)
118#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
119 LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
120#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
121 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
122#define GET_TX_DESC_PIFS(__pdesc) \
123 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
124#define GET_TX_DESC_RATE_ID(__pdesc) \
125 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
126#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
127 LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
128#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
129 LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
130#define GET_TX_DESC_SEC_TYPE(__pdesc) \
131 LE_BITS_TO_4BYTE(__pdesc+4, 22, 2)
132#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
133 LE_BITS_TO_4BYTE(__pdesc+4, 24, 8)
134
135#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
136 SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 6, __val)
137#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
138 SET_BITS_TO_LE_4BYTE(__pdesc+8, 6, 6, __val)
139#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
140 SET_BITS_TO_LE_4BYTE(__pdesc+8, 12, 1, __val)
141#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
142 SET_BITS_TO_LE_4BYTE(__pdesc+8, 13, 1, __val)
143#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
144 SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 2, __val)
145#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
146 SET_BITS_TO_LE_4BYTE(__pdesc+8, 16, 1, __val)
147#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
148 SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
149#define SET_TX_DESC_RAW(__pdesc, __val) \
150 SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
151#define SET_TX_DESC_CCX(__pdesc, __val) \
152 SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
153#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
154 SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
155#define SET_TX_DESC_BT_INT(__pdesc, __val) \
156 SET_BITS_TO_LE_4BYTE(__pdesc+8, 23, 1, __val)
157#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
158 SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 1, __val)
159#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
160 SET_BITS_TO_LE_4BYTE(__pdesc+8, 25, 1, __val)
161#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \
162 SET_BITS_TO_LE_4BYTE(__pdesc+8, 26, 2, __val)
163#define SET_TX_DESC_TX_ANTL(__pdesc, __val) \
164 SET_BITS_TO_LE_4BYTE(__pdesc+8, 28, 2, __val)
165#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
166 SET_BITS_TO_LE_4BYTE(__pdesc+8, 30, 2, __val)
167
168#define GET_TX_DESC_RTS_RC(__pdesc) \
169 LE_BITS_TO_4BYTE(__pdesc+8, 0, 6)
170#define GET_TX_DESC_DATA_RC(__pdesc) \
171 LE_BITS_TO_4BYTE(__pdesc+8, 6, 6)
172#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
173 LE_BITS_TO_4BYTE(__pdesc+8, 14, 2)
174#define GET_TX_DESC_MORE_FRAG(__pdesc) \
175 LE_BITS_TO_4BYTE(__pdesc+8, 17, 1)
176#define GET_TX_DESC_RAW(__pdesc) \
177 LE_BITS_TO_4BYTE(__pdesc+8, 18, 1)
178#define GET_TX_DESC_CCX(__pdesc) \
179 LE_BITS_TO_4BYTE(__pdesc+8, 19, 1)
180#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
181 LE_BITS_TO_4BYTE(__pdesc+8, 20, 3)
182#define GET_TX_DESC_ANTSEL_A(__pdesc) \
183 LE_BITS_TO_4BYTE(__pdesc+8, 24, 1)
184#define GET_TX_DESC_ANTSEL_B(__pdesc) \
185 LE_BITS_TO_4BYTE(__pdesc+8, 25, 1)
186#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
187 LE_BITS_TO_4BYTE(__pdesc+8, 26, 2)
188#define GET_TX_DESC_TX_ANTL(__pdesc) \
189 LE_BITS_TO_4BYTE(__pdesc+8, 28, 2)
190#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
191 LE_BITS_TO_4BYTE(__pdesc+8, 30, 2)
192
193#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
194 SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 8, __val)
195#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
196 SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 8, __val)
197#define SET_TX_DESC_SEQ(__pdesc, __val) \
198 SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 12, __val)
199#define SET_TX_DESC_CPU_HANDLE(__pdesc, __val) \
200 SET_BITS_TO_LE_4BYTE(__pdesc+12, 28, 1, __val)
201#define SET_TX_DESC_TAG1(__pdesc, __val) \
202 SET_BITS_TO_LE_4BYTE(__pdesc+12, 29, 1, __val)
203#define SET_TX_DESC_TRIGGER_INT(__pdesc, __val) \
204 SET_BITS_TO_LE_4BYTE(__pdesc+12, 30, 1, __val)
205#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
206 SET_BITS_TO_LE_4BYTE(__pdesc+12, 31, 1, __val)
207
208
209#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
210 LE_BITS_TO_4BYTE(__pdesc+12, 0, 8)
211#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
212 LE_BITS_TO_4BYTE(__pdesc+12, 8, 8)
213#define GET_TX_DESC_SEQ(__pdesc) \
214 LE_BITS_TO_4BYTE(__pdesc+12, 16, 12)
215
216
217#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
218 SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 5, __val)
219#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
220 SET_BITS_TO_LE_4BYTE(__pdesc+16, 5, 1, __val)
221#define SET_TX_DESC_QOS(__pdesc, __val) \
222 SET_BITS_TO_LE_4BYTE(__pdesc+16, 6, 1, __val)
223#define SET_TX_DESC_HWSEQ_SSN(__pdesc, __val) \
224 SET_BITS_TO_LE_4BYTE(__pdesc+16, 7, 1, __val)
225#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
226 SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 1, __val)
227#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
228 SET_BITS_TO_LE_4BYTE(__pdesc+16, 9, 1, __val)
229#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
230 SET_BITS_TO_LE_4BYTE(__pdesc+16, 10, 1, __val)
231#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
232 SET_BITS_TO_LE_4BYTE(__pdesc+16, 11, 1, __val)
233#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
234 SET_BITS_TO_LE_4BYTE(__pdesc+16, 12, 1, __val)
235#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
236 SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 1, __val)
237#define SET_TX_DESC_PORT_ID(__pdesc, __val) \
238 SET_BITS_TO_LE_4BYTE(__pdesc+16, 14, 1, __val)
239#define SET_TX_DESC_PWR_STATUS(__pdesc, __val) \
240 SET_BITS_TO_LE_4BYTE(__pdesc+16, 15, 3, __val)
241#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \
242 SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 1, __val)
243#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \
244 SET_BITS_TO_LE_4BYTE(__pdesc+16, 19, 1, __val)
245#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
246 SET_BITS_TO_LE_4BYTE(__pdesc+16, 20, 2, __val)
247#define SET_TX_DESC_TX_STBC(__pdesc, __val) \
248 SET_BITS_TO_LE_4BYTE(__pdesc+16, 22, 2, __val)
249#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
250 SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 1, __val)
251#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
252 SET_BITS_TO_LE_4BYTE(__pdesc+16, 25, 1, __val)
253#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
254 SET_BITS_TO_LE_4BYTE(__pdesc+16, 26, 1, __val)
255#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
256 SET_BITS_TO_LE_4BYTE(__pdesc+16, 27, 1, __val)
257#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
258 SET_BITS_TO_LE_4BYTE(__pdesc+16, 28, 2, __val)
259#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
260 SET_BITS_TO_LE_4BYTE(__pdesc+16, 30, 2, __val)
261
262#define GET_TX_DESC_RTS_RATE(__pdesc) \
263 LE_BITS_TO_4BYTE(__pdesc+16, 0, 5)
264#define GET_TX_DESC_AP_DCFE(__pdesc) \
265 LE_BITS_TO_4BYTE(__pdesc+16, 5, 1)
266#define GET_TX_DESC_QOS(__pdesc) \
267 LE_BITS_TO_4BYTE(__pdesc+16, 6, 1)
268#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
269 LE_BITS_TO_4BYTE(__pdesc+16, 7, 1)
270#define GET_TX_DESC_USE_RATE(__pdesc) \
271 LE_BITS_TO_4BYTE(__pdesc+16, 8, 1)
272#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
273 LE_BITS_TO_4BYTE(__pdesc+16, 9, 1)
274#define GET_TX_DESC_DISABLE_FB(__pdesc) \
275 LE_BITS_TO_4BYTE(__pdesc+16, 10, 1)
276#define GET_TX_DESC_CTS2SELF(__pdesc) \
277 LE_BITS_TO_4BYTE(__pdesc+16, 11, 1)
278#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
279 LE_BITS_TO_4BYTE(__pdesc+16, 12, 1)
280#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
281 LE_BITS_TO_4BYTE(__pdesc+16, 13, 1)
282#define GET_TX_DESC_PORT_ID(__pdesc) \
283 LE_BITS_TO_4BYTE(__pdesc+16, 14, 1)
284#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
285 LE_BITS_TO_4BYTE(__pdesc+16, 18, 1)
286#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
287 LE_BITS_TO_4BYTE(__pdesc+16, 19, 1)
288#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
289 LE_BITS_TO_4BYTE(__pdesc+16, 20, 2)
290#define GET_TX_DESC_TX_STBC(__pdesc) \
291 LE_BITS_TO_4BYTE(__pdesc+16, 22, 2)
292#define GET_TX_DESC_DATA_SHORT(__pdesc) \
293 LE_BITS_TO_4BYTE(__pdesc+16, 24, 1)
294#define GET_TX_DESC_DATA_BW(__pdesc) \
295 LE_BITS_TO_4BYTE(__pdesc+16, 25, 1)
296#define GET_TX_DESC_RTS_SHORT(__pdesc) \
297 LE_BITS_TO_4BYTE(__pdesc+16, 26, 1)
298#define GET_TX_DESC_RTS_BW(__pdesc) \
299 LE_BITS_TO_4BYTE(__pdesc+16, 27, 1)
300#define GET_TX_DESC_RTS_SC(__pdesc) \
301 LE_BITS_TO_4BYTE(__pdesc+16, 28, 2)
302#define GET_TX_DESC_RTS_STBC(__pdesc) \
303 LE_BITS_TO_4BYTE(__pdesc+16, 30, 2)
304
305#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
306 SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 6, __val)
307#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
308 SET_BITS_TO_LE_4BYTE(__pdesc+20, 6, 1, __val)
309#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
310 SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val)
311#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
312 SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 5, __val)
313#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
314 SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val)
315#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
316 SET_BITS_TO_LE_4BYTE(__pdesc+20, 17, 1, __val)
317#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
318 SET_BITS_TO_LE_4BYTE(__pdesc+20, 18, 6, __val)
319#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
320 SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 8, __val)
321
322#define GET_TX_DESC_TX_RATE(__pdesc) \
323 LE_BITS_TO_4BYTE(__pdesc+20, 0, 6)
324#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
325 LE_BITS_TO_4BYTE(__pdesc+20, 6, 1)
326#define GET_TX_DESC_CCX_TAG(__pdesc) \
327 LE_BITS_TO_4BYTE(__pdesc+20, 7, 1)
328#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
329 LE_BITS_TO_4BYTE(__pdesc+20, 8, 5)
330#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
331 LE_BITS_TO_4BYTE(__pdesc+20, 13, 4)
332#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
333 LE_BITS_TO_4BYTE(__pdesc+20, 17, 1)
334#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
335 LE_BITS_TO_4BYTE(__pdesc+20, 18, 6)
336#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \
337 LE_BITS_TO_4BYTE(__pdesc+20, 24, 8)
338
339#define SET_TX_DESC_TXAGC_A(__pdesc, __val) \
340 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 5, __val)
341#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
342 SET_BITS_TO_LE_4BYTE(__pdesc+24, 5, 5, __val)
343#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
344 SET_BITS_TO_LE_4BYTE(__pdesc+24, 10, 1, __val)
345#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
346 SET_BITS_TO_LE_4BYTE(__pdesc+24, 11, 5, __val)
347#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
348 SET_BITS_TO_LE_4BYTE(__pdesc+24, 16, 4, __val)
349#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \
350 SET_BITS_TO_LE_4BYTE(__pdesc+24, 20, 4, __val)
351#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \
352 SET_BITS_TO_LE_4BYTE(__pdesc+24, 24, 4, __val)
353#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \
354 SET_BITS_TO_LE_4BYTE(__pdesc+24, 28, 4, __val)
355
356#define GET_TX_DESC_TXAGC_A(__pdesc) \
357 LE_BITS_TO_4BYTE(__pdesc+24, 0, 5)
358#define GET_TX_DESC_TXAGC_B(__pdesc) \
359 LE_BITS_TO_4BYTE(__pdesc+24, 5, 5)
360#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
361 LE_BITS_TO_4BYTE(__pdesc+24, 10, 1)
362#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
363 LE_BITS_TO_4BYTE(__pdesc+24, 11, 5)
364#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
365 LE_BITS_TO_4BYTE(__pdesc+24, 16, 4)
366#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
367 LE_BITS_TO_4BYTE(__pdesc+24, 20, 4)
368#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
369 LE_BITS_TO_4BYTE(__pdesc+24, 24, 4)
370#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
371 LE_BITS_TO_4BYTE(__pdesc+24, 28, 4)
372
373#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
374 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val)
375#define SET_TX_DESC_SW_OFFSET30(__pdesc, __val) \
376 SET_BITS_TO_LE_4BYTE(__pdesc+28, 16, 8, __val)
377#define SET_TX_DESC_SW_OFFSET31(__pdesc, __val) \
378 SET_BITS_TO_LE_4BYTE(__pdesc+28, 24, 4, __val)
379#define SET_TX_DESC_ANTSEL_C(__pdesc, __val) \
380 SET_BITS_TO_LE_4BYTE(__pdesc+28, 29, 1, __val)
381#define SET_TX_DESC_NULL_0(__pdesc, __val) \
382 SET_BITS_TO_LE_4BYTE(__pdesc+28, 30, 1, __val)
383#define SET_TX_DESC_NULL_1(__pdesc, __val) \
384 SET_BITS_TO_LE_4BYTE(__pdesc+28, 30, 1, __val)
385
386#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
387 LE_BITS_TO_4BYTE(__pdesc+28, 0, 16)
388
389
390#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
391 SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 32, __val)
392#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
393 SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 32, __val)
394
395#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
396 LE_BITS_TO_4BYTE(__pdesc+32, 0, 32)
397#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
398 LE_BITS_TO_4BYTE(__pdesc+36, 0, 32)
399
400#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
401 SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
402#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
403 SET_BITS_TO_LE_4BYTE(__pdesc+44, 0, 32, __val)
404
405#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
406 LE_BITS_TO_4BYTE(__pdesc+40, 0, 32)
407#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \
408 LE_BITS_TO_4BYTE(__pdesc+44, 0, 32)
409
410#define GET_RX_DESC_PKT_LEN(__pdesc) \
411 LE_BITS_TO_4BYTE(__pdesc, 0, 14)
412#define GET_RX_DESC_CRC32(__pdesc) \
413 LE_BITS_TO_4BYTE(__pdesc, 14, 1)
414#define GET_RX_DESC_ICV(__pdesc) \
415 LE_BITS_TO_4BYTE(__pdesc, 15, 1)
416#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
417 LE_BITS_TO_4BYTE(__pdesc, 16, 4)
418#define GET_RX_DESC_SECURITY(__pdesc) \
419 LE_BITS_TO_4BYTE(__pdesc, 20, 3)
420#define GET_RX_DESC_QOS(__pdesc) \
421 LE_BITS_TO_4BYTE(__pdesc, 23, 1)
422#define GET_RX_DESC_SHIFT(__pdesc) \
423 LE_BITS_TO_4BYTE(__pdesc, 24, 2)
424#define GET_RX_DESC_PHYST(__pdesc) \
425 LE_BITS_TO_4BYTE(__pdesc, 26, 1)
426#define GET_RX_DESC_SWDEC(__pdesc) \
427 LE_BITS_TO_4BYTE(__pdesc, 27, 1)
428#define GET_RX_DESC_LS(__pdesc) \
429 LE_BITS_TO_4BYTE(__pdesc, 28, 1)
430#define GET_RX_DESC_FS(__pdesc) \
431 LE_BITS_TO_4BYTE(__pdesc, 29, 1)
432#define GET_RX_DESC_EOR(__pdesc) \
433 LE_BITS_TO_4BYTE(__pdesc, 30, 1)
434#define GET_RX_DESC_OWN(__pdesc) \
435 LE_BITS_TO_4BYTE(__pdesc, 31, 1)
436
437#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
438 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
439#define SET_RX_DESC_EOR(__pdesc, __val) \
440 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
441#define SET_RX_DESC_OWN(__pdesc, __val) \
442 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
443
444#define GET_RX_DESC_MACID(__pdesc) \
445 LE_BITS_TO_4BYTE(__pdesc+4, 0, 6)
446#define GET_RX_DESC_PAGGR(__pdesc) \
447 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
448#define GET_RX_DESC_FAGGR(__pdesc) \
449 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
450#define GET_RX_DESC_A1_FIT(__pdesc) \
451 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
452#define GET_RX_DESC_A2_FIT(__pdesc) \
453 LE_BITS_TO_4BYTE(__pdesc+4, 20, 4)
454#define GET_RX_DESC_PAM(__pdesc) \
455 LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
456#define GET_RX_DESC_PWR(__pdesc) \
457 LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
458#define GET_RX_DESC_MD(__pdesc) \
459 LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
460#define GET_RX_DESC_MF(__pdesc) \
461 LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
462#define GET_RX_DESC_TYPE(__pdesc) \
463 LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
464#define GET_RX_DESC_MC(__pdesc) \
465 LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
466#define GET_RX_DESC_BC(__pdesc) \
467 LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
468#define GET_RX_DESC_SEQ(__pdesc) \
469 LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
470#define GET_RX_DESC_FRAG(__pdesc) \
471 LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
472
473#define GET_RX_DESC_RXMCS(__pdesc) \
474 LE_BITS_TO_4BYTE(__pdesc+12, 0, 6)
475#define GET_RX_DESC_RXHT(__pdesc) \
476 LE_BITS_TO_4BYTE(__pdesc+12, 6, 1)
477#define GET_RX_STATUS_DESC_RX_GF(__pdesc) \
478 LE_BITS_TO_4BYTE(__pdesc+12, 7, 1)
479#define GET_RX_DESC_SPLCP(__pdesc) \
480 LE_BITS_TO_4BYTE(__pdesc+12, 8, 1)
481#define GET_RX_DESC_BW(__pdesc) \
482 LE_BITS_TO_4BYTE(__pdesc+12, 9, 1)
483#define GET_RX_DESC_HTC(__pdesc) \
484 LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
485#define GET_RX_STATUS_DESC_EOSP(__pdesc) \
486 LE_BITS_TO_4BYTE(__pdesc+12, 11, 1)
487#define GET_RX_STATUS_DESC_BSSID_FIT(__pdesc) \
488 LE_BITS_TO_4BYTE(__pdesc+12, 12, 2)
489#define GET_RX_STATUS_DESC_RPT_SEL(__pdesc) \
490 LE_BITS_TO_4BYTE(__pdesc+12, 14, 2)
491
492#define GET_RX_STATUS_DESC_PATTERN_MATCH(__pdesc) \
493 LE_BITS_TO_4BYTE(__pdesc+12, 29, 1)
494#define GET_RX_STATUS_DESC_UNICAST_MATCH(__pdesc) \
495 LE_BITS_TO_4BYTE(__pdesc+12, 30, 1)
496#define GET_RX_STATUS_DESC_MAGIC_MATCH(__pdesc) \
497 LE_BITS_TO_4BYTE(__pdesc+12, 31, 1)
498
499#define GET_RX_DESC_IV1(__pdesc) \
500 LE_BITS_TO_4BYTE(__pdesc+16, 0, 32)
501#define GET_RX_DESC_TSFL(__pdesc) \
502 LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
503
504#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
505 LE_BITS_TO_4BYTE(__pdesc+24, 0, 32)
506#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
507 LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
508
509#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
510 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
511#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
512 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
513
514/* TX report 2 format in Rx desc*/
515
516#define GET_RX_RPT2_DESC_PKT_LEN(__status) \
517 LE_BITS_TO_4BYTE(__status, 0, 9)
518#define GET_RX_RPT2_DESC_MACID_VALID_1(__status) \
519 LE_BITS_TO_4BYTE(__status+16, 0, 32)
520#define GET_RX_RPT2_DESC_MACID_VALID_2(__status) \
521 LE_BITS_TO_4BYTE(__status+20, 0, 32)
522
523#define SET_EARLYMODE_PKTNUM(__paddr, __value) \
524 SET_BITS_TO_LE_4BYTE(__paddr, 0, 4, __value)
525#define SET_EARLYMODE_LEN0(__paddr, __value) \
526 SET_BITS_TO_LE_4BYTE(__paddr, 4, 12, __value)
527#define SET_EARLYMODE_LEN1(__paddr, __value) \
528 SET_BITS_TO_LE_4BYTE(__paddr, 16, 12, __value)
529#define SET_EARLYMODE_LEN2_1(__paddr, __value) \
530 SET_BITS_TO_LE_4BYTE(__paddr, 28, 4, __value)
531#define SET_EARLYMODE_LEN2_2(__paddr, __value) \
532 SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 8, __value)
533#define SET_EARLYMODE_LEN3(__paddr, __value) \
534 SET_BITS_TO_LE_4BYTE(__paddr+4, 8, 12, __value)
535#define SET_EARLYMODE_LEN4(__paddr, __value) \
536 SET_BITS_TO_LE_4BYTE(__paddr+4, 20, 12, __value)
537
538#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
539do { \
540 if (_size > TX_DESC_NEXT_DESC_OFFSET) \
541 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
542 else \
543 memset(__pdesc, 0, _size); \
544} while (0)
545
546#define RTL8188_RX_HAL_IS_CCK_RATE(rxmcs)\
547 (rxmcs == DESC92C_RATE1M ||\
548 rxmcs == DESC92C_RATE2M ||\
549 rxmcs == DESC92C_RATE5_5M ||\
550 rxmcs == DESC92C_RATE11M)
551
552struct phy_rx_agc_info_t {
553 #if __LITTLE_ENDIAN
554 u8 gain:7, trsw:1;
555 #else
556 u8 trsw:1, gain:7;
557 #endif
558};
559struct phy_status_rpt {
560 struct phy_rx_agc_info_t path_agc[2];
561 u8 ch_corr[2];
562 u8 cck_sig_qual_ofdm_pwdb_all;
563 u8 cck_agc_rpt_ofdm_cfosho_a;
564 u8 cck_rpt_b_ofdm_cfosho_b;
565 u8 rsvd_1;
566 u8 noise_power_db_msb;
567 u8 path_cfotail[2];
568 u8 pcts_mask[2];
569 u8 stream_rxevm[2];
570 u8 path_rxsnr[2];
571 u8 noise_power_db_lsb;
572 u8 rsvd_2[3];
573 u8 stream_csi[2];
574 u8 stream_target_csi[2];
575 u8 sig_evm;
576 u8 rsvd_3;
577#if __LITTLE_ENDIAN
578 u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
579 u8 sgi_en:1;
580 u8 rxsc:2;
581 u8 idle_long:1;
582 u8 r_ant_train_en:1;
583 u8 ant_sel_b:1;
584 u8 ant_sel:1;
585#else /* _BIG_ENDIAN_ */
586 u8 ant_sel:1;
587 u8 ant_sel_b:1;
588 u8 r_ant_train_en:1;
589 u8 idle_long:1;
590 u8 rxsc:2;
591 u8 sgi_en:1;
592 u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
593#endif
594} __packed;
595
596struct rx_fwinfo_88e {
597 u8 gain_trsw[4];
598 u8 pwdb_all;
599 u8 cfosho[4];
600 u8 cfotail[4];
601 char rxevm[2];
602 char rxsnr[4];
603 u8 pdsnr[2];
604 u8 csi_current[2];
605 u8 csi_target[2];
606 u8 sigevm;
607 u8 max_ex_pwr;
608 u8 ex_intf_flag:1;
609 u8 sgi_en:1;
610 u8 rxsc:2;
611 u8 reserve:4;
612} __packed;
613
614struct tx_desc_88e {
615 u32 pktsize:16;
616 u32 offset:8;
617 u32 bmc:1;
618 u32 htc:1;
619 u32 lastseg:1;
620 u32 firstseg:1;
621 u32 linip:1;
622 u32 noacm:1;
623 u32 gf:1;
624 u32 own:1;
625
626 u32 macid:6;
627 u32 rsvd0:2;
628 u32 queuesel:5;
629 u32 rd_nav_ext:1;
630 u32 lsig_txop_en:1;
631 u32 pifs:1;
632 u32 rateid:4;
633 u32 nav_usehdr:1;
634 u32 en_descid:1;
635 u32 sectype:2;
636 u32 pktoffset:8;
637
638 u32 rts_rc:6;
639 u32 data_rc:6;
640 u32 agg_en:1;
641 u32 rdg_en:1;
642 u32 bar_retryht:2;
643 u32 agg_break:1;
644 u32 morefrag:1;
645 u32 raw:1;
646 u32 ccx:1;
647 u32 ampdudensity:3;
648 u32 bt_int:1;
649 u32 ant_sela:1;
650 u32 ant_selb:1;
651 u32 txant_cck:2;
652 u32 txant_l:2;
653 u32 txant_ht:2;
654
655 u32 nextheadpage:8;
656 u32 tailpage:8;
657 u32 seq:12;
658 u32 cpu_handle:1;
659 u32 tag1:1;
660 u32 trigger_int:1;
661 u32 hwseq_en:1;
662
663 u32 rtsrate:5;
664 u32 apdcfe:1;
665 u32 qos:1;
666 u32 hwseq_ssn:1;
667 u32 userrate:1;
668 u32 dis_rtsfb:1;
669 u32 dis_datafb:1;
670 u32 cts2self:1;
671 u32 rts_en:1;
672 u32 hwrts_en:1;
673 u32 portid:1;
674 u32 pwr_status:3;
675 u32 waitdcts:1;
676 u32 cts2ap_en:1;
677 u32 txsc:2;
678 u32 stbc:2;
679 u32 txshort:1;
680 u32 txbw:1;
681 u32 rtsshort:1;
682 u32 rtsbw:1;
683 u32 rtssc:2;
684 u32 rtsstbc:2;
685
686 u32 txrate:6;
687 u32 shortgi:1;
688 u32 ccxt:1;
689 u32 txrate_fb_lmt:5;
690 u32 rtsrate_fb_lmt:4;
691 u32 retrylmt_en:1;
692 u32 txretrylmt:6;
693 u32 usb_txaggnum:8;
694
695 u32 txagca:5;
696 u32 txagcb:5;
697 u32 usemaxlen:1;
698 u32 maxaggnum:5;
699 u32 mcsg1maxlen:4;
700 u32 mcsg2maxlen:4;
701 u32 mcsg3maxlen:4;
702 u32 mcs7sgimaxlen:4;
703
704 u32 txbuffersize:16;
705 u32 sw_offset30:8;
706 u32 sw_offset31:4;
707 u32 rsvd1:1;
708 u32 antsel_c:1;
709 u32 null_0:1;
710 u32 null_1:1;
711
712 u32 txbuffaddr;
713 u32 txbufferaddr64;
714 u32 nextdescaddress;
715 u32 nextdescaddress64;
716
717 u32 reserve_pass_pcie_mm_limit[4];
718} __packed;
719
720struct rx_desc_88e {
721 u32 length:14;
722 u32 crc32:1;
723 u32 icverror:1;
724 u32 drv_infosize:4;
725 u32 security:3;
726 u32 qos:1;
727 u32 shift:2;
728 u32 phystatus:1;
729 u32 swdec:1;
730 u32 lastseg:1;
731 u32 firstseg:1;
732 u32 eor:1;
733 u32 own:1;
734
735 u32 macid:6;
736 u32 tid:4;
737 u32 hwrsvd:5;
738 u32 paggr:1;
739 u32 faggr:1;
740 u32 a1_fit:4;
741 u32 a2_fit:4;
742 u32 pam:1;
743 u32 pwr:1;
744 u32 moredata:1;
745 u32 morefrag:1;
746 u32 type:2;
747 u32 mc:1;
748 u32 bc:1;
749
750 u32 seq:12;
751 u32 frag:4;
752 u32 nextpktlen:14;
753 u32 nextind:1;
754 u32 rsvd:1;
755
756 u32 rxmcs:6;
757 u32 rxht:1;
758 u32 amsdu:1;
759 u32 splcp:1;
760 u32 bandwidth:1;
761 u32 htc:1;
762 u32 tcpchk_rpt:1;
763 u32 ipcchk_rpt:1;
764 u32 tcpchk_valid:1;
765 u32 hwpcerr:1;
766 u32 hwpcind:1;
767 u32 iv0:16;
768
769 u32 iv1;
770
771 u32 tsfl;
772
773 u32 bufferaddress;
774 u32 bufferaddress64;
775
776} __packed;
777
778void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
779 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
780 struct ieee80211_tx_info *info,
781 struct ieee80211_sta *sta,
782 struct sk_buff *skb,
783 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
784bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,
785 struct rtl_stats *status,
786 struct ieee80211_rx_status *rx_status,
787 u8 *pdesc, struct sk_buff *skb);
788void rtl88ee_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val);
789u32 rtl88ee_get_desc(u8 *pdesc, bool istx, u8 desc_name);
790void rtl88ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
791void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
792 bool b_firstseg, bool b_lastseg,
793 struct sk_buff *skb);
794
795#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 23:40:31 -0500