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authorLarry Finger <Larry.Finger@lwfinger.net>2011-02-19 17:28:47 -0500
committerJohn W. Linville <linville@tuxdriver.com>2011-02-21 15:39:56 -0500
commita9dd591919788b38c9177a41dcb40a7a0620cdd0 (patch)
tree52389ed02f7278ae28a292f4143974e83005d4e9 /drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
parent69081624c7b2138b137738e307cb67e2dafd6e9b (diff)
rtlwifi: Make changes in rtlwifi/rtl8192ce/reg.h to support rtl8192cu
This change modifies rtlwifi/rtl8192ce/reg.h to support rtl8192cu. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8192ce/reg.h')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/reg.h71
1 files changed, 68 insertions, 3 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
index 875d51465225..9ffbadc281f2 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
@@ -63,7 +63,15 @@
63#define REG_LEDCFG3 0x004F 63#define REG_LEDCFG3 0x004F
64#define REG_FSIMR 0x0050 64#define REG_FSIMR 0x0050
65#define REG_FSISR 0x0054 65#define REG_FSISR 0x0054
66 66#define REG_HSIMR 0x0058
67#define REG_HSISR 0x005c
68
69/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
70#define REG_GPIO_PIN_CTRL_2 0x0060
71/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
72#define REG_GPIO_IO_SEL_2 0x0062
73/* RTL8723 WIFI/BT/GPS Multi-Function control source. */
74#define REG_MULTI_FUNC_CTRL 0x0068
67#define REG_MCUFWDL 0x0080 75#define REG_MCUFWDL 0x0080
68 76
69#define REG_HMEBOX_EXT_0 0x0088 77#define REG_HMEBOX_EXT_0 0x0088
@@ -79,6 +87,7 @@
79#define REG_PCIE_MIO_INTD 0x00E8 87#define REG_PCIE_MIO_INTD 0x00E8
80#define REG_HPON_FSM 0x00EC 88#define REG_HPON_FSM 0x00EC
81#define REG_SYS_CFG 0x00F0 89#define REG_SYS_CFG 0x00F0
90#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only.*/
82 91
83#define REG_CR 0x0100 92#define REG_CR 0x0100
84#define REG_PBP 0x0104 93#define REG_PBP 0x0104
@@ -209,6 +218,8 @@
209#define REG_RDG_PIFS 0x0513 218#define REG_RDG_PIFS 0x0513
210#define REG_SIFS_CTX 0x0514 219#define REG_SIFS_CTX 0x0514
211#define REG_SIFS_TRX 0x0516 220#define REG_SIFS_TRX 0x0516
221#define REG_SIFS_CCK 0x0514
222#define REG_SIFS_OFDM 0x0516
212#define REG_AGGR_BREAK_TIME 0x051A 223#define REG_AGGR_BREAK_TIME 0x051A
213#define REG_SLOT 0x051B 224#define REG_SLOT 0x051B
214#define REG_TX_PTCL_CTRL 0x0520 225#define REG_TX_PTCL_CTRL 0x0520
@@ -261,6 +272,10 @@
261#define REG_MAC_SPEC_SIFS 0x063A 272#define REG_MAC_SPEC_SIFS 0x063A
262#define REG_RESP_SIFS_CCK 0x063C 273#define REG_RESP_SIFS_CCK 0x063C
263#define REG_RESP_SIFS_OFDM 0x063E 274#define REG_RESP_SIFS_OFDM 0x063E
275/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
276#define REG_R2T_SIFS 0x063C
277/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
278#define REG_T2T_SIFS 0x063E
264#define REG_ACKTO 0x0640 279#define REG_ACKTO 0x0640
265#define REG_CTS2TO 0x0641 280#define REG_CTS2TO 0x0641
266#define REG_EIFS 0x0642 281#define REG_EIFS 0x0642
@@ -641,9 +656,10 @@
641#define STOPBE BIT(1) 656#define STOPBE BIT(1)
642#define STOPBK BIT(0) 657#define STOPBK BIT(0)
643 658
644#define RCR_APPFCS BIT(31) 659#define RCR_APP_FCS BIT(31)
645#define RCR_APP_MIC BIT(30) 660#define RCR_APP_MIC BIT(30)
646#define RCR_APP_ICV BIT(29) 661#define RCR_APP_ICV BIT(29)
662#define RCR_APP_PHYSTS BIT(28)
647#define RCR_APP_PHYST_RXFF BIT(28) 663#define RCR_APP_PHYST_RXFF BIT(28)
648#define RCR_APP_BA_SSN BIT(27) 664#define RCR_APP_BA_SSN BIT(27)
649#define RCR_ENMBID BIT(24) 665#define RCR_ENMBID BIT(24)
@@ -759,6 +775,7 @@
759 775
760#define BOOT_FROM_EEPROM BIT(4) 776#define BOOT_FROM_EEPROM BIT(4)
761#define EEPROM_EN BIT(5) 777#define EEPROM_EN BIT(5)
778#define EEPROMSEL BOOT_FROM_EEPROM
762 779
763#define AFE_BGEN BIT(0) 780#define AFE_BGEN BIT(0)
764#define AFE_MBEN BIT(1) 781#define AFE_MBEN BIT(1)
@@ -876,6 +893,8 @@
876#define BD_MAC2 BIT(9) 893#define BD_MAC2 BIT(9)
877#define BD_MAC1 BIT(10) 894#define BD_MAC1 BIT(10)
878#define IC_MACPHY_MODE BIT(11) 895#define IC_MACPHY_MODE BIT(11)
896#define BT_FUNC BIT(16)
897#define VENDOR_ID BIT(19)
879#define PAD_HWPD_IDN BIT(22) 898#define PAD_HWPD_IDN BIT(22)
880#define TRP_VAUX_EN BIT(23) 899#define TRP_VAUX_EN BIT(23)
881#define TRP_BT_EN BIT(24) 900#define TRP_BT_EN BIT(24)
@@ -883,6 +902,28 @@
883#define BD_HCI_SEL BIT(26) 902#define BD_HCI_SEL BIT(26)
884#define TYPE_ID BIT(27) 903#define TYPE_ID BIT(27)
885 904
905/* REG_GPIO_OUTSTS (For RTL8723 only) */
906#define EFS_HCI_SEL (BIT(0)|BIT(1))
907#define PAD_HCI_SEL (BIT(2)|BIT(3))
908#define HCI_SEL (BIT(4)|BIT(5))
909#define PKG_SEL_HCI BIT(6)
910#define FEN_GPS BIT(7)
911#define FEN_BT BIT(8)
912#define FEN_WL BIT(9)
913#define FEN_PCI BIT(10)
914#define FEN_USB BIT(11)
915#define BTRF_HWPDN_N BIT(12)
916#define WLRF_HWPDN_N BIT(13)
917#define PDN_BT_N BIT(14)
918#define PDN_GPS_N BIT(15)
919#define BT_CTL_HWPDN BIT(16)
920#define GPS_CTL_HWPDN BIT(17)
921#define PPHY_SUSB BIT(20)
922#define UPHY_SUSB BIT(21)
923#define PCI_SUSEN BIT(22)
924#define USB_SUSEN BIT(23)
925#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
926
886#define CHIP_VER_RTL_MASK 0xF000 927#define CHIP_VER_RTL_MASK 0xF000
887#define CHIP_VER_RTL_SHIFT 12 928#define CHIP_VER_RTL_SHIFT 12
888 929
@@ -1184,6 +1225,30 @@
1184 1225
1185#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1226#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1186 1227
1228/* REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
1229/* Enable GPIO[9] as WiFi HW PDn source */
1230#define WL_HWPDN_EN BIT(0)
1231/* WiFi HW PDn polarity control */
1232#define WL_HWPDN_SL BIT(1)
1233/* WiFi function enable */
1234#define WL_FUNC_EN BIT(2)
1235/* Enable GPIO[9] as WiFi RF HW PDn source */
1236#define WL_HWROF_EN BIT(3)
1237/* Enable GPIO[11] as BT HW PDn source */
1238#define BT_HWPDN_EN BIT(16)
1239/* BT HW PDn polarity control */
1240#define BT_HWPDN_SL BIT(17)
1241/* BT function enable */
1242#define BT_FUNC_EN BIT(18)
1243/* Enable GPIO[11] as BT/GPS RF HW PDn source */
1244#define BT_HWROF_EN BIT(19)
1245/* Enable GPIO[10] as GPS HW PDn source */
1246#define GPS_HWPDN_EN BIT(20)
1247/* GPS HW PDn polarity control */
1248#define GPS_HWPDN_SL BIT(21)
1249/* GPS function enable */
1250#define GPS_FUNC_EN BIT(22)
1251
1187#define RPMAC_RESET 0x100 1252#define RPMAC_RESET 0x100
1188#define RPMAC_TXSTART 0x104 1253#define RPMAC_TXSTART 0x104
1189#define RPMAC_TXLEGACYSIG 0x108 1254#define RPMAC_TXLEGACYSIG 0x108
@@ -1496,7 +1561,7 @@
1496#define BTXHTSTBC 0x30 1561#define BTXHTSTBC 0x30
1497#define BTXHTADVANCECODING 0x40 1562#define BTXHTADVANCECODING 0x40
1498#define BTXHTSHORTGI 0x80 1563#define BTXHTSHORTGI 0x80
1499#define BTXHTNUMBERHT_LT F 0x300 1564#define BTXHTNUMBERHT_LTF 0x300
1500#define BTXHTCRC8 0x3fc00 1565#define BTXHTCRC8 0x3fc00
1501#define BCOUNTERRESET 0x10000 1566#define BCOUNTERRESET 0x10000
1502#define BNUMOFOFDMTX 0xffff 1567#define BNUMOFOFDMTX 0xffff