diff options
author | Larry Finger <Larry.Finger@lwfinger.net> | 2013-03-24 23:06:42 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2013-04-01 16:20:13 -0400 |
commit | f0eb856e0b6cbd21244afc0f252cec718ecf88fb (patch) | |
tree | 77d5cb7faf46f7ffd6b79a6d97be72b4eef422b1 /drivers/net/wireless/rtlwifi/rtl8188ee/sw.c | |
parent | a269913c52ad37952a4d9953bb6d748f7299c304 (diff) |
rtlwifi: rtl8188ee: Add new driver
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Cc: jcheung@suse.com
Cc: machen@suse.com
Cc: mmarek@suse.cz
Cc: page_he@realsil.com.cn
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8188ee/sw.c')
-rw-r--r-- | drivers/net/wireless/rtlwifi/rtl8188ee/sw.c | 400 |
1 files changed, 400 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/sw.c b/drivers/net/wireless/rtlwifi/rtl8188ee/sw.c new file mode 100644 index 000000000000..e8ce1897f383 --- /dev/null +++ b/drivers/net/wireless/rtlwifi/rtl8188ee/sw.c | |||
@@ -0,0 +1,400 @@ | |||
1 | /****************************************************************************** | ||
2 | * | ||
3 | * Copyright(c) 2009-2013 Realtek Corporation. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it | ||
6 | * under the terms of version 2 of the GNU General Public License as | ||
7 | * published by the Free Software Foundation. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
12 | * more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License along with | ||
15 | * this program; if not, write to the Free Software Foundation, Inc., | ||
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | ||
17 | * | ||
18 | * The full GNU General Public License is included in this distribution in the | ||
19 | * file called LICENSE. | ||
20 | * | ||
21 | * Contact Information: | ||
22 | * wlanfae <wlanfae@realtek.com> | ||
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | ||
24 | * Hsinchu 300, Taiwan. | ||
25 | * | ||
26 | * Larry Finger <Larry.Finger@lwfinger.net> | ||
27 | * | ||
28 | *****************************************************************************/ | ||
29 | |||
30 | #include "wifi.h" | ||
31 | #include "core.h" | ||
32 | #include "pci.h" | ||
33 | #include "reg.h" | ||
34 | #include "def.h" | ||
35 | #include "phy.h" | ||
36 | #include "dm.h" | ||
37 | #include "hw.h" | ||
38 | #include "sw.h" | ||
39 | #include "trx.h" | ||
40 | #include "led.h" | ||
41 | #include "table.h" | ||
42 | |||
43 | #include <linux/vmalloc.h> | ||
44 | #include <linux/module.h> | ||
45 | |||
46 | static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw) | ||
47 | { | ||
48 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | ||
49 | |||
50 | /*close ASPM for AMD defaultly */ | ||
51 | rtlpci->const_amdpci_aspm = 0; | ||
52 | |||
53 | /* ASPM PS mode. | ||
54 | * 0 - Disable ASPM, | ||
55 | * 1 - Enable ASPM without Clock Req, | ||
56 | * 2 - Enable ASPM with Clock Req, | ||
57 | * 3 - Alwyas Enable ASPM with Clock Req, | ||
58 | * 4 - Always Enable ASPM without Clock Req. | ||
59 | * set defult to RTL8192CE:3 RTL8192E:2 | ||
60 | */ | ||
61 | rtlpci->const_pci_aspm = 3; | ||
62 | |||
63 | /*Setting for PCI-E device */ | ||
64 | rtlpci->const_devicepci_aspm_setting = 0x03; | ||
65 | |||
66 | /*Setting for PCI-E bridge */ | ||
67 | rtlpci->const_hostpci_aspm_setting = 0x02; | ||
68 | |||
69 | /* In Hw/Sw Radio Off situation. | ||
70 | * 0 - Default, | ||
71 | * 1 - From ASPM setting without low Mac Pwr, | ||
72 | * 2 - From ASPM setting with low Mac Pwr, | ||
73 | * 3 - Bus D3 | ||
74 | * set default to RTL8192CE:0 RTL8192SE:2 | ||
75 | */ | ||
76 | rtlpci->const_hwsw_rfoff_d3 = 0; | ||
77 | |||
78 | /* This setting works for those device with | ||
79 | * backdoor ASPM setting such as EPHY setting. | ||
80 | * 0 - Not support ASPM, | ||
81 | * 1 - Support ASPM, | ||
82 | * 2 - According to chipset. | ||
83 | */ | ||
84 | rtlpci->const_support_pciaspm = 1; | ||
85 | } | ||
86 | |||
87 | int rtl88e_init_sw_vars(struct ieee80211_hw *hw) | ||
88 | { | ||
89 | int err = 0; | ||
90 | struct rtl_priv *rtlpriv = rtl_priv(hw); | ||
91 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | ||
92 | u8 tid; | ||
93 | |||
94 | rtl8188ee_bt_reg_init(hw); | ||
95 | |||
96 | rtlpriv->dm.dm_initialgain_enable = 1; | ||
97 | rtlpriv->dm.dm_flag = 0; | ||
98 | rtlpriv->dm.disable_framebursting = 0; | ||
99 | rtlpriv->dm.thermalvalue = 0; | ||
100 | rtlpci->transmit_config = CFENDFORM | BIT(15); | ||
101 | |||
102 | /* compatible 5G band 88ce just 2.4G band & smsp */ | ||
103 | rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G; | ||
104 | rtlpriv->rtlhal.bandset = BAND_ON_2_4G; | ||
105 | rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY; | ||
106 | |||
107 | rtlpci->receive_config = (RCR_APPFCS | | ||
108 | RCR_APP_MIC | | ||
109 | RCR_APP_ICV | | ||
110 | RCR_APP_PHYST_RXFF | | ||
111 | RCR_HTC_LOC_CTRL | | ||
112 | RCR_AMF | | ||
113 | RCR_ACF | | ||
114 | RCR_ADF | | ||
115 | RCR_AICV | | ||
116 | RCR_ACRC32 | | ||
117 | RCR_AB | | ||
118 | RCR_AM | | ||
119 | RCR_APM | | ||
120 | 0); | ||
121 | |||
122 | rtlpci->irq_mask[0] = | ||
123 | (u32) (IMR_PSTIMEOUT | | ||
124 | IMR_HSISR_IND_ON_INT | | ||
125 | IMR_C2HCMD | | ||
126 | IMR_HIGHDOK | | ||
127 | IMR_MGNTDOK | | ||
128 | IMR_BKDOK | | ||
129 | IMR_BEDOK | | ||
130 | IMR_VIDOK | | ||
131 | IMR_VODOK | | ||
132 | IMR_RDU | | ||
133 | IMR_ROK | | ||
134 | 0); | ||
135 | rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0); | ||
136 | rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN); | ||
137 | |||
138 | /* for debug level */ | ||
139 | rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; | ||
140 | /* for LPS & IPS */ | ||
141 | rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; | ||
142 | rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; | ||
143 | rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; | ||
144 | if (!rtlpriv->psc.inactiveps) | ||
145 | pr_info("rtl8188ee: Power Save off (module option)\n"); | ||
146 | if (!rtlpriv->psc.fwctrl_lps) | ||
147 | pr_info("rtl8188ee: FW Power Save off (module option)\n"); | ||
148 | rtlpriv->psc.reg_fwctrl_lps = 3; | ||
149 | rtlpriv->psc.reg_max_lps_awakeintvl = 5; | ||
150 | /* for ASPM, you can close aspm through | ||
151 | * set const_support_pciaspm = 0 | ||
152 | */ | ||
153 | rtl88e_init_aspm_vars(hw); | ||
154 | |||
155 | if (rtlpriv->psc.reg_fwctrl_lps == 1) | ||
156 | rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; | ||
157 | else if (rtlpriv->psc.reg_fwctrl_lps == 2) | ||
158 | rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; | ||
159 | else if (rtlpriv->psc.reg_fwctrl_lps == 3) | ||
160 | rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; | ||
161 | |||
162 | /* for firmware buf */ | ||
163 | rtlpriv->rtlhal.pfirmware = vmalloc(0x8000); | ||
164 | if (!rtlpriv->rtlhal.pfirmware) { | ||
165 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | ||
166 | "Can't alloc buffer for fw.\n"); | ||
167 | return 1; | ||
168 | } | ||
169 | |||
170 | rtlpriv->cfg->fw_name = "rtlwifi/rtl8188efw.bin"; | ||
171 | rtlpriv->max_fw_size = 0x8000; | ||
172 | pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name); | ||
173 | err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name, | ||
174 | rtlpriv->io.dev, GFP_KERNEL, hw, | ||
175 | rtl_fw_cb); | ||
176 | if (err) { | ||
177 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | ||
178 | "Failed to request firmware!\n"); | ||
179 | return 1; | ||
180 | } | ||
181 | |||
182 | /* for early mode */ | ||
183 | rtlpriv->rtlhal.earlymode_enable = false; | ||
184 | rtlpriv->rtlhal.max_earlymode_num = 10; | ||
185 | for (tid = 0; tid < 8; tid++) | ||
186 | skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]); | ||
187 | |||
188 | /*low power */ | ||
189 | rtlpriv->psc.low_power_enable = false; | ||
190 | if (rtlpriv->psc.low_power_enable) { | ||
191 | init_timer(&rtlpriv->works.fw_clockoff_timer); | ||
192 | setup_timer(&rtlpriv->works.fw_clockoff_timer, | ||
193 | rtl88ee_fw_clk_off_timer_callback, | ||
194 | (unsigned long)hw); | ||
195 | } | ||
196 | |||
197 | init_timer(&rtlpriv->works.fast_antenna_training_timer); | ||
198 | setup_timer(&rtlpriv->works.fast_antenna_training_timer, | ||
199 | rtl88e_dm_fast_antenna_training_callback, | ||
200 | (unsigned long)hw); | ||
201 | return err; | ||
202 | } | ||
203 | |||
204 | void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw) | ||
205 | { | ||
206 | struct rtl_priv *rtlpriv = rtl_priv(hw); | ||
207 | |||
208 | if (rtlpriv->rtlhal.pfirmware) { | ||
209 | vfree(rtlpriv->rtlhal.pfirmware); | ||
210 | rtlpriv->rtlhal.pfirmware = NULL; | ||
211 | } | ||
212 | |||
213 | if (rtlpriv->psc.low_power_enable) | ||
214 | del_timer_sync(&rtlpriv->works.fw_clockoff_timer); | ||
215 | |||
216 | del_timer_sync(&rtlpriv->works.fast_antenna_training_timer); | ||
217 | } | ||
218 | |||
219 | static struct rtl_hal_ops rtl8188ee_hal_ops = { | ||
220 | .init_sw_vars = rtl88e_init_sw_vars, | ||
221 | .deinit_sw_vars = rtl88e_deinit_sw_vars, | ||
222 | .read_eeprom_info = rtl88ee_read_eeprom_info, | ||
223 | .interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/ | ||
224 | .hw_init = rtl88ee_hw_init, | ||
225 | .hw_disable = rtl88ee_card_disable, | ||
226 | .hw_suspend = rtl88ee_suspend, | ||
227 | .hw_resume = rtl88ee_resume, | ||
228 | .enable_interrupt = rtl88ee_enable_interrupt, | ||
229 | .disable_interrupt = rtl88ee_disable_interrupt, | ||
230 | .set_network_type = rtl88ee_set_network_type, | ||
231 | .set_chk_bssid = rtl88ee_set_check_bssid, | ||
232 | .set_qos = rtl88ee_set_qos, | ||
233 | .set_bcn_reg = rtl88ee_set_beacon_related_registers, | ||
234 | .set_bcn_intv = rtl88ee_set_beacon_interval, | ||
235 | .update_interrupt_mask = rtl88ee_update_interrupt_mask, | ||
236 | .get_hw_reg = rtl88ee_get_hw_reg, | ||
237 | .set_hw_reg = rtl88ee_set_hw_reg, | ||
238 | .update_rate_tbl = rtl88ee_update_hal_rate_tbl, | ||
239 | .fill_tx_desc = rtl88ee_tx_fill_desc, | ||
240 | .fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc, | ||
241 | .query_rx_desc = rtl88ee_rx_query_desc, | ||
242 | .set_channel_access = rtl88ee_update_channel_access_setting, | ||
243 | .radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking, | ||
244 | .set_bw_mode = rtl88e_phy_set_bw_mode, | ||
245 | .switch_channel = rtl88e_phy_sw_chnl, | ||
246 | .dm_watchdog = rtl88e_dm_watchdog, | ||
247 | .scan_operation_backup = rtl88e_phy_scan_operation_backup, | ||
248 | .set_rf_power_state = rtl88e_phy_set_rf_power_state, | ||
249 | .led_control = rtl88ee_led_control, | ||
250 | .set_desc = rtl88ee_set_desc, | ||
251 | .get_desc = rtl88ee_get_desc, | ||
252 | .tx_polling = rtl88ee_tx_polling, | ||
253 | .enable_hw_sec = rtl88ee_enable_hw_security_config, | ||
254 | .set_key = rtl88ee_set_key, | ||
255 | .init_sw_leds = rtl88ee_init_sw_leds, | ||
256 | .allow_all_destaddr = rtl88ee_allow_all_destaddr, | ||
257 | .get_bbreg = rtl88e_phy_query_bb_reg, | ||
258 | .set_bbreg = rtl88e_phy_set_bb_reg, | ||
259 | .get_rfreg = rtl88e_phy_query_rf_reg, | ||
260 | .set_rfreg = rtl88e_phy_set_rf_reg, | ||
261 | }; | ||
262 | |||
263 | static struct rtl_mod_params rtl88ee_mod_params = { | ||
264 | .sw_crypto = false, | ||
265 | .inactiveps = true, | ||
266 | .swctrl_lps = false, | ||
267 | .fwctrl_lps = true, | ||
268 | .debug = DBG_EMERG, | ||
269 | }; | ||
270 | |||
271 | static struct rtl_hal_cfg rtl88ee_hal_cfg = { | ||
272 | .bar_id = 2, | ||
273 | .write_readback = true, | ||
274 | .name = "rtl88e_pci", | ||
275 | .ops = &rtl8188ee_hal_ops, | ||
276 | .mod_params = &rtl88ee_mod_params, | ||
277 | |||
278 | .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, | ||
279 | .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, | ||
280 | .maps[SYS_CLK] = REG_SYS_CLKR, | ||
281 | .maps[MAC_RCR_AM] = AM, | ||
282 | .maps[MAC_RCR_AB] = AB, | ||
283 | .maps[MAC_RCR_ACRC32] = ACRC32, | ||
284 | .maps[MAC_RCR_ACF] = ACF, | ||
285 | .maps[MAC_RCR_AAP] = AAP, | ||
286 | |||
287 | .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS, | ||
288 | |||
289 | .maps[EFUSE_TEST] = REG_EFUSE_TEST, | ||
290 | .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, | ||
291 | .maps[EFUSE_CLK] = 0, | ||
292 | .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, | ||
293 | .maps[EFUSE_PWC_EV12V] = PWC_EV12V, | ||
294 | .maps[EFUSE_FEN_ELDR] = FEN_ELDR, | ||
295 | .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, | ||
296 | .maps[EFUSE_ANA8M] = ANA8M, | ||
297 | .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, | ||
298 | .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, | ||
299 | .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, | ||
300 | .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES, | ||
301 | |||
302 | .maps[RWCAM] = REG_CAMCMD, | ||
303 | .maps[WCAMI] = REG_CAMWRITE, | ||
304 | .maps[RCAMO] = REG_CAMREAD, | ||
305 | .maps[CAMDBG] = REG_CAMDBG, | ||
306 | .maps[SECR] = REG_SECCFG, | ||
307 | .maps[SEC_CAM_NONE] = CAM_NONE, | ||
308 | .maps[SEC_CAM_WEP40] = CAM_WEP40, | ||
309 | .maps[SEC_CAM_TKIP] = CAM_TKIP, | ||
310 | .maps[SEC_CAM_AES] = CAM_AES, | ||
311 | .maps[SEC_CAM_WEP104] = CAM_WEP104, | ||
312 | |||
313 | .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, | ||
314 | .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, | ||
315 | .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, | ||
316 | .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, | ||
317 | .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, | ||
318 | .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, | ||
319 | /* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/ | ||
320 | .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, | ||
321 | .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, | ||
322 | .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, | ||
323 | .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, | ||
324 | .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, | ||
325 | .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, | ||
326 | .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, | ||
327 | /* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/ | ||
328 | /* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/ | ||
329 | |||
330 | .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, | ||
331 | .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, | ||
332 | .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0, | ||
333 | .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, | ||
334 | .maps[RTL_IMR_RDU] = IMR_RDU, | ||
335 | .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, | ||
336 | .maps[RTL_IMR_BDOK] = IMR_BCNDOK0, | ||
337 | .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, | ||
338 | .maps[RTL_IMR_TBDER] = IMR_TBDER, | ||
339 | .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, | ||
340 | .maps[RTL_IMR_TBDOK] = IMR_TBDOK, | ||
341 | .maps[RTL_IMR_BKDOK] = IMR_BKDOK, | ||
342 | .maps[RTL_IMR_BEDOK] = IMR_BEDOK, | ||
343 | .maps[RTL_IMR_VIDOK] = IMR_VIDOK, | ||
344 | .maps[RTL_IMR_VODOK] = IMR_VODOK, | ||
345 | .maps[RTL_IMR_ROK] = IMR_ROK, | ||
346 | .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER), | ||
347 | |||
348 | .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M, | ||
349 | .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M, | ||
350 | .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M, | ||
351 | .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M, | ||
352 | .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M, | ||
353 | .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M, | ||
354 | .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M, | ||
355 | .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M, | ||
356 | .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M, | ||
357 | .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M, | ||
358 | .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M, | ||
359 | .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M, | ||
360 | |||
361 | .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7, | ||
362 | .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15, | ||
363 | }; | ||
364 | |||
365 | static DEFINE_PCI_DEVICE_TABLE(rtl88ee_pci_ids) = { | ||
366 | {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)}, | ||
367 | {}, | ||
368 | }; | ||
369 | |||
370 | MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids); | ||
371 | |||
372 | MODULE_AUTHOR("zhiyuan_yang <zhiyuan_yang@realsil.com.cn>"); | ||
373 | MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); | ||
374 | MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); | ||
375 | MODULE_LICENSE("GPL"); | ||
376 | MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless"); | ||
377 | MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin"); | ||
378 | |||
379 | module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444); | ||
380 | module_param_named(debug, rtl88ee_mod_params.debug, int, 0444); | ||
381 | module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444); | ||
382 | module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444); | ||
383 | module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444); | ||
384 | MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); | ||
385 | MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); | ||
386 | MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); | ||
387 | MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); | ||
388 | MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); | ||
389 | |||
390 | static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); | ||
391 | |||
392 | static struct pci_driver rtl88ee_driver = { | ||
393 | .name = KBUILD_MODNAME, | ||
394 | .id_table = rtl88ee_pci_ids, | ||
395 | .probe = rtl_pci_probe, | ||
396 | .remove = rtl_pci_disconnect, | ||
397 | .driver.pm = &rtlwifi_pm_ops, | ||
398 | }; | ||
399 | |||
400 | module_pci_driver(rtl88ee_driver); | ||